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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
e3bb37b5
L		 138static void set_code_flag (int);
139static void set_16bit_gcc_code_flag (int);
140static void set_intel_syntax (int);
1efbbeb4 141static void set_intel_mnemonic (int);
db51cc60 142static void set_allow_index_reg (int);
cb19c032 143static void set_sse_check (int);
e3bb37b5 144static void set_cpu_arch (int);
6482c264 145#ifdef TE_PE
e3bb37b5 146static void pe_directive_secrel (int);
6482c264 147#endif
e3bb37b5
L		 148static void signed_cons (int);
149static char *output_invalid (int c);
ee86248c
JB		 150static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
151 const char *);
152static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
153 const char *);
a7619375 154static int i386_att_operand (char *);
e3bb37b5 155static int i386_intel_operand (char *, int);
ee86248c
JB		 156static int i386_intel_simplify (expressionS *);
157static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 158static const reg_entry *parse_register (char *, char **);
159static char *parse_insn (char *, char *);
160static char *parse_operands (char *, const char *);
161static void swap_operands (void);
4d456e3d 162static void swap_2_operands (int, int);
e3bb37b5
L		 163static void optimize_imm (void);
164static void optimize_disp (void);
d3ce72d0 165static const insn_template *match_template (void);
e3bb37b5
L		 166static int check_string (void);
167static int process_suffix (void);
168static int check_byte_reg (void);
169static int check_long_reg (void);
170static int check_qword_reg (void);
171static int check_word_reg (void);
172static int finalize_imm (void);
173static int process_operands (void);
174static const seg_entry *build_modrm_byte (void);
175static void output_insn (void);
176static void output_imm (fragS *, offsetT);
177static void output_disp (fragS *, offsetT);
29b0f896 178#ifndef I386COFF
e3bb37b5 179static void s_bss (int);
252b5132 180#endif
17d4e2a2
L		 181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182static void handle_large_common (int small ATTRIBUTE_UNUSED);
183#endif
252b5132 184
a847613f 185static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 186
c0f3af97
L		 187/* VEX prefix. */
188typedef struct
189{
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes[3];
192 unsigned int length;
193 /* Destination or source register specifier. */
194 const reg_entry *register_specifier;
195} vex_prefix;
196
252b5132 197/* 'md_assemble ()' gathers together information and puts it into a
47926f60 198 i386_insn. */
252b5132 199
520dc8e8
AM		 200union i386_op
201 {
202 expressionS *disps;
203 expressionS *imms;
204 const reg_entry *regs;
205 };
206
252b5132
RH		 207struct _i386_insn
208 {
47926f60 209 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 210 insn_template tm;
252b5132 211
7d5e4556
L		 212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
252b5132
RH		 214 char suffix;
215
47926f60 216 /* OPERANDS gives the number of given operands. */
252b5132
RH		 217 unsigned int operands;
218
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
47926f60 221 operands. */
252b5132
RH		 222 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
223
224 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 225 use OP[i] for the corresponding operand. */
40fb9820 226 i386_operand_type types[MAX_OPERANDS];
252b5132 227
520dc8e8
AM		 228 /* Displacement expression, immediate expression, or register for each
229 operand. */
230 union i386_op op[MAX_OPERANDS];
252b5132 231
3e73aa7c
JH		 232 /* Flags for operands. */
233 unsigned int flags[MAX_OPERANDS];
234#define Operand_PCrel 1
235
252b5132 236 /* Relocation type for operand */
f86103b7 237 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 238
252b5132
RH		 239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry *base_reg;
242 const reg_entry *index_reg;
243 unsigned int log2_scale_factor;
244
245 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 246 explicit segment overrides are given. */
ce8a8b2f 247 const seg_entry *seg[2];
252b5132
RH		 248
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes;
252 unsigned char prefix[MAX_PREFIXES];
253
254 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 255 addressing modes of this insn are encoded. */
252b5132 256 modrm_byte rm;
3e73aa7c 257 rex_byte rex;
252b5132 258 sib_byte sib;
c0f3af97 259 vex_prefix vex;
b6169b20
L		 260
261 /* Swap operand in encoding. */
4473e004 262 unsigned int swap_operand;
252b5132
RH		 263 };
264
265typedef struct _i386_insn i386_insn;
266
267/* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
32137342 269const char extra_symbol_chars[] = "*%-(["
252b5132 270#ifdef LEX_AT
32137342
NC		 271 "@"
272#endif
273#ifdef LEX_QM
274 "?"
252b5132 275#endif
32137342 276 ;
252b5132 277
29b0f896
AM		 278#if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 280 && !defined (TE_GNU) \
29b0f896 281 && !defined (TE_LINUX) \
32137342 282 && !defined (TE_NETWARE) \
29b0f896
AM		 283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
252b5132 285/* This array holds the chars that always start a comment. If the
b3b91714
AM		 286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288const char *i386_comment_chars = "#/";
289#define SVR4_COMMENT_CHARS 1
252b5132 290#define PREFIX_SEPARATOR '\\'
252b5132 291
b3b91714
AM		 292#else
293const char *i386_comment_chars = "#";
294#define PREFIX_SEPARATOR '/'
295#endif
296
252b5132
RH		 297/* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 301 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
252b5132 304 '/' isn't otherwise defined. */
b3b91714 305const char line_comment_chars[] = "#/";
252b5132 306
63a0b638 307const char line_separator_chars[] = ";";
252b5132 308
ce8a8b2f
AM		 309/* Chars that can be used to separate mant from exp in floating point
310 nums. */
252b5132
RH		 311const char EXP_CHARS[] = "eE";
312
ce8a8b2f
AM		 313/* Chars that mean this number is a floating point constant
314 As in 0f12.456
315 or 0d1.2345e12. */
252b5132
RH		 316const char FLT_CHARS[] = "fFdDxX";
317
ce8a8b2f 318/* Tables for lexical analysis. */
252b5132
RH		 319static char mnemonic_chars[256];
320static char register_chars[256];
321static char operand_chars[256];
322static char identifier_chars[256];
323static char digit_chars[256];
324
ce8a8b2f 325/* Lexical macros. */
252b5132
RH		 326#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327#define is_operand_char(x) (operand_chars[(unsigned char) x])
328#define is_register_char(x) (register_chars[(unsigned char) x])
329#define is_space_char(x) ((x) == ' ')
330#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331#define is_digit_char(x) (digit_chars[(unsigned char) x])
332
0234cb7c 333/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 334static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
335
336/* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
47926f60 339 assembler instruction). */
252b5132 340static char save_stack[32];
ce8a8b2f 341static char *save_stack_p;
252b5132
RH		 342#define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344#define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
346
47926f60 347/* The instruction we're assembling. */
252b5132
RH		 348static i386_insn i;
349
350/* Possible templates for current insn. */
351static const templates *current_templates;
352
31b2323c
L		 353/* Per instruction expressionS buffers: max displacements & immediates. */
354static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
355static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 356
47926f60 357/* Current operand we are working on. */
ee86248c 358static int this_operand = -1;
252b5132 359
3e73aa7c
JH		 360/* We support four different modes. FLAG_CODE variable is used to distinguish
361 these. */
362
363enum flag_code {
364 CODE_32BIT,
365 CODE_16BIT,
366 CODE_64BIT };
367
368static enum flag_code flag_code;
4fa24527 369static unsigned int object_64bit;
3e73aa7c
JH		 370static int use_rela_relocations = 0;
371
372/* The names used to print error messages. */
b77a7acd 373static const char *flag_code_names[] =
3e73aa7c
JH		 374 {
375 "32",
376 "16",
377 "64"
378 };
252b5132 379
47926f60
KH		 380/* 1 for intel syntax,
381 0 if att syntax. */
382static int intel_syntax = 0;
252b5132 383
1efbbeb4
L		 384/* 1 for intel mnemonic,
385 0 if att mnemonic. */
386static int intel_mnemonic = !SYSV386_COMPAT;
387
5209009a 388/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 389static int old_gcc = OLDGCC_COMPAT;
390
a60de03c
JB		 391/* 1 if pseudo registers are permitted. */
392static int allow_pseudo_reg = 0;
393
47926f60
KH		 394/* 1 if register prefix % not required. */
395static int allow_naked_reg = 0;
252b5132 396
ba104c83 397/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 398static int allow_index_reg = 0;
399
daf50ae7
L		 400static enum
401 {
402 sse_check_none = 0,
403 sse_check_warning,
404 sse_check_error
405 }
406sse_check;
407
2ca3ace5
L		 408/* Register prefix used for error message. */
409static const char *register_prefix = "%";
410
47926f60
KH		 411/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414static char stackop_size = '\0';
eecb386c 415
12b55ccc
L		 416/* Non-zero to optimize code alignment. */
417int optimize_align_code = 1;
418
47926f60
KH		 419/* Non-zero to quieten some warnings. */
420static int quiet_warnings = 0;
a38cf1db 421
47926f60
KH		 422/* CPU name. */
423static const char *cpu_arch_name = NULL;
6305a203 424static char *cpu_sub_arch_name = NULL;
a38cf1db 425
47926f60 426/* CPU feature flags. */
40fb9820
L		 427static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
428
ccc9c027
L		 429/* If we have selected a cpu we are generating instructions for. */
430static int cpu_arch_tune_set = 0;
431
9103f4f4 432/* Cpu we are generating instructions for. */
fbf3f584 433enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 434
435/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 436static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 437
ccc9c027 438/* CPU instruction set architecture used. */
fbf3f584 439enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 440
9103f4f4 441/* CPU feature flags of instruction set architecture used. */
fbf3f584 442i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 443
fddf5b5b
AM		 444/* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446static unsigned int no_cond_jump_promotion = 0;
447
c0f3af97
L		 448/* Encode SSE instructions with VEX prefix. */
449static unsigned int sse2avx;
450
539f890d
L		 451/* Encode scalar AVX instructions with specific vector length. */
452static enum
453 {
454 vex128 = 0,
455 vex256
456 } avxscalar;
457
29b0f896 458/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 459static symbolS *GOT_symbol;
29b0f896 460
a4447b93
RH		 461/* The dwarf2 return column, adjusted for 32 or 64 bit. */
462unsigned int x86_dwarf2_return_column;
463
464/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
465int x86_cie_data_alignment;
466
252b5132 467/* Interface to relax_segment.
fddf5b5b
AM		 468 There are 3 major relax states for 386 jump insns because the
469 different types of jumps add different sizes to frags when we're
470 figuring out what sort of jump to choose to reach a given label. */
252b5132 471
47926f60 472/* Types. */
93c2a809
AM		 473#define UNCOND_JUMP 0
474#define COND_JUMP 1
475#define COND_JUMP86 2
fddf5b5b 476
47926f60 477/* Sizes. */
252b5132
RH		 478#define CODE16 1
479#define SMALL 0
29b0f896 480#define SMALL16 (SMALL | CODE16)
252b5132 481#define BIG 2
29b0f896 482#define BIG16 (BIG | CODE16)
252b5132
RH		 483
484#ifndef INLINE
485#ifdef __GNUC__
486#define INLINE __inline__
487#else
488#define INLINE
489#endif
490#endif
491
fddf5b5b
AM		 492#define ENCODE_RELAX_STATE(type, size) \
493 ((relax_substateT) (((type) << 2) | (size)))
494#define TYPE_FROM_RELAX_STATE(s) \
495 ((s) >> 2)
496#define DISP_SIZE_FROM_RELAX_STATE(s) \
497 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 498
499/* This table is used by relax_frag to promote short jumps to long
500 ones where necessary. SMALL (short) jumps may be promoted to BIG
501 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
502 don't allow a short jump in a 32 bit code segment to be promoted to
503 a 16 bit offset jump because it's slower (requires data size
504 prefix), and doesn't work, unless the destination is in the bottom
505 64k of the code segment (The top 16 bits of eip are zeroed). */
506
507const relax_typeS md_relax_table[] =
508{
24eab124
AM		 509 /* The fields are:
510 1) most positive reach of this state,
511 2) most negative reach of this state,
93c2a809 512 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 513 4) which index into the table to try if we can't fit into this one. */
252b5132 514
fddf5b5b 515 /* UNCOND_JUMP states. */
93c2a809
AM		 516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
518 /* dword jmp adds 4 bytes to frag:
519 0 extra opcode bytes, 4 displacement bytes. */
252b5132 520 {0, 0, 4, 0},
93c2a809
AM		 521 /* word jmp adds 2 byte2 to frag:
522 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 523 {0, 0, 2, 0},
524
93c2a809
AM		 525 /* COND_JUMP states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
530 {0, 0, 5, 0},
fddf5b5b 531 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 532 1 extra opcode byte, 2 displacement bytes. */
533 {0, 0, 3, 0},
534
535 /* COND_JUMP86 states. */
536 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
537 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
538 /* dword conditionals adds 5 bytes to frag:
539 1 extra opcode byte, 4 displacement bytes. */
540 {0, 0, 5, 0},
541 /* word conditionals add 4 bytes to frag:
542 1 displacement byte and a 3 byte long branch insn. */
543 {0, 0, 4, 0}
252b5132
RH		 544};
545
9103f4f4
L		 546static const arch_entry cpu_arch[] =
547{
8a2c8fef
L		 548 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
549 CPU_GENERIC32_FLAGS, 0 },
550 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
551 CPU_GENERIC64_FLAGS, 0 },
552 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
553 CPU_NONE_FLAGS, 0 },
554 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
555 CPU_I186_FLAGS, 0 },
556 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
557 CPU_I286_FLAGS, 0 },
558 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
559 CPU_I386_FLAGS, 0 },
560 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
561 CPU_I486_FLAGS, 0 },
562 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
563 CPU_I586_FLAGS, 0 },
564 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
565 CPU_I686_FLAGS, 0 },
566 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
567 CPU_I586_FLAGS, 0 },
568 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
569 CPU_I686_FLAGS, 0 },
570 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
571 CPU_P2_FLAGS, 0 },
572 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
573 CPU_P3_FLAGS, 0 },
574 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
575 CPU_P4_FLAGS, 0 },
576 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
577 CPU_CORE_FLAGS, 0 },
578 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
579 CPU_NOCONA_FLAGS, 0 },
580 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
581 CPU_CORE_FLAGS, 1 },
582 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
583 CPU_CORE_FLAGS, 0 },
584 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
585 CPU_CORE2_FLAGS, 1 },
586 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
587 CPU_CORE2_FLAGS, 0 },
588 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
589 CPU_COREI7_FLAGS, 0 },
590 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
591 CPU_L1OM_FLAGS, 0 },
592 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
593 CPU_K6_FLAGS, 0 },
594 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
595 CPU_K6_2_FLAGS, 0 },
596 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
597 CPU_ATHLON_FLAGS, 0 },
598 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
599 CPU_K8_FLAGS, 1 },
600 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
601 CPU_K8_FLAGS, 0 },
602 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
603 CPU_K8_FLAGS, 0 },
604 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
605 CPU_AMDFAM10_FLAGS, 0 },
68339fdf
SP		 606 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
607 CPU_BDVER1_FLAGS, 0 },
8a2c8fef
L		 608 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
609 CPU_8087_FLAGS, 0 },
610 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
611 CPU_287_FLAGS, 0 },
612 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
613 CPU_387_FLAGS, 0 },
614 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
615 CPU_ANY87_FLAGS, 0 },
616 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
617 CPU_MMX_FLAGS, 0 },
618 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
619 CPU_3DNOWA_FLAGS, 0 },
620 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
621 CPU_SSE_FLAGS, 0 },
622 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
623 CPU_SSE2_FLAGS, 0 },
624 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
625 CPU_SSE3_FLAGS, 0 },
626 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
627 CPU_SSSE3_FLAGS, 0 },
628 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
629 CPU_SSE4_1_FLAGS, 0 },
630 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
631 CPU_SSE4_2_FLAGS, 0 },
632 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
633 CPU_SSE4_2_FLAGS, 0 },
634 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
635 CPU_ANY_SSE_FLAGS, 0 },
636 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
637 CPU_AVX_FLAGS, 0 },
638 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
639 CPU_ANY_AVX_FLAGS, 0 },
640 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
641 CPU_VMX_FLAGS, 0 },
642 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
643 CPU_SMX_FLAGS, 0 },
644 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
645 CPU_XSAVE_FLAGS, 0 },
646 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
647 CPU_AES_FLAGS, 0 },
648 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
649 CPU_PCLMUL_FLAGS, 0 },
650 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
651 CPU_PCLMUL_FLAGS, 1 },
652 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
653 CPU_FMA_FLAGS, 0 },
654 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
655 CPU_FMA4_FLAGS, 0 },
656 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
657 CPU_XOP_FLAGS, 0 },
658 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
659 CPU_LWP_FLAGS, 0 },
660 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
661 CPU_MOVBE_FLAGS, 0 },
662 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
663 CPU_EPT_FLAGS, 0 },
664 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
665 CPU_CLFLUSH_FLAGS, 0 },
666 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
667 CPU_SYSCALL_FLAGS, 0 },
668 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
669 CPU_RDTSCP_FLAGS, 0 },
670 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
671 CPU_3DNOW_FLAGS, 0 },
672 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
673 CPU_3DNOWA_FLAGS, 0 },
674 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
675 CPU_PADLOCK_FLAGS, 0 },
676 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
677 CPU_SVME_FLAGS, 1 },
678 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
679 CPU_SVME_FLAGS, 0 },
680 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
681 CPU_SSE4A_FLAGS, 0 },
682 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
683 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 684};
685
704209c0 686#ifdef I386COFF
a6c24e68
NC		 687/* Like s_lcomm_internal in gas/read.c but the alignment string
688 is allowed to be optional. */
689
690static symbolS *
691pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
692{
693 addressT align = 0;
694
695 SKIP_WHITESPACE ();
696
7ab9ffdd 697 if (needs_align
a6c24e68
NC		 698 && *input_line_pointer == ',')
699 {
700 align = parse_align (needs_align - 1);
7ab9ffdd 701
a6c24e68
NC		 702 if (align == (addressT) -1)
703 return NULL;
704 }
705 else
706 {
707 if (size >= 8)
708 align = 3;
709 else if (size >= 4)
710 align = 2;
711 else if (size >= 2)
712 align = 1;
713 else
714 align = 0;
715 }
716
717 bss_alloc (symbolP, size, align);
718 return symbolP;
719}
720
704209c0 721static void
a6c24e68
NC		 722pe_lcomm (int needs_align)
723{
724 s_comm_internal (needs_align * 2, pe_lcomm_internal);
725}
704209c0 726#endif
a6c24e68 727
29b0f896
AM		 728const pseudo_typeS md_pseudo_table[] =
729{
730#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
731 {"align", s_align_bytes, 0},
732#else
733 {"align", s_align_ptwo, 0},
734#endif
735 {"arch", set_cpu_arch, 0},
736#ifndef I386COFF
737 {"bss", s_bss, 0},
a6c24e68
NC		 738#else
739 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 740#endif
741 {"ffloat", float_cons, 'f'},
742 {"dfloat", float_cons, 'd'},
743 {"tfloat", float_cons, 'x'},
744 {"value", cons, 2},
d182319b 745 {"slong", signed_cons, 4},
29b0f896
AM		 746 {"noopt", s_ignore, 0},
747 {"optim", s_ignore, 0},
748 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
749 {"code16", set_code_flag, CODE_16BIT},
750 {"code32", set_code_flag, CODE_32BIT},
751 {"code64", set_code_flag, CODE_64BIT},
752 {"intel_syntax", set_intel_syntax, 1},
753 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 754 {"intel_mnemonic", set_intel_mnemonic, 1},
755 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 756 {"allow_index_reg", set_allow_index_reg, 1},
757 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 758 {"sse_check", set_sse_check, 0},
3b22753a
L		 759#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
760 {"largecomm", handle_large_common, 0},
07a53e5c 761#else
e3bb37b5 762 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 763 {"loc", dwarf2_directive_loc, 0},
764 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 765#endif
6482c264
NC		 766#ifdef TE_PE
767 {"secrel32", pe_directive_secrel, 0},
768#endif
29b0f896
AM		 769 {0, 0, 0}
770};
771
772/* For interface with expression (). */
773extern char *input_line_pointer;
774
775/* Hash table for instruction mnemonic lookup. */
776static struct hash_control *op_hash;
777
778/* Hash table for register lookup. */
779static struct hash_control *reg_hash;
780\f
252b5132 781void
e3bb37b5 782i386_align_code (fragS *fragP, int count)
252b5132 783{
ce8a8b2f
AM		 784 /* Various efficient no-op patterns for aligning code labels.
785 Note: Don't try to assemble the instructions in the comments.
786 0L and 0w are not legal. */
252b5132
RH		 787 static const char f32_1[] =
788 {0x90}; /* nop */
789 static const char f32_2[] =
ccc9c027 790 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 791 static const char f32_3[] =
792 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
793 static const char f32_4[] =
794 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
795 static const char f32_5[] =
796 {0x90, /* nop */
797 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
798 static const char f32_6[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
800 static const char f32_7[] =
801 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
802 static const char f32_8[] =
803 {0x90, /* nop */
804 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
805 static const char f32_9[] =
806 {0x89,0xf6, /* movl %esi,%esi */
807 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
808 static const char f32_10[] =
809 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_11[] =
812 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
814 static const char f32_12[] =
815 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
816 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
817 static const char f32_13[] =
818 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
819 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
820 static const char f32_14[] =
821 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
822 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 823 static const char f16_3[] =
824 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 825 static const char f16_4[] =
826 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
827 static const char f16_5[] =
828 {0x90, /* nop */
829 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
830 static const char f16_6[] =
831 {0x89,0xf6, /* mov %si,%si */
832 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
833 static const char f16_7[] =
834 {0x8d,0x74,0x00, /* lea 0(%si),%si */
835 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
836 static const char f16_8[] =
837 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
838 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 839 static const char jump_31[] =
840 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
841 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
842 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
843 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 844 static const char *const f32_patt[] = {
845 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 846 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 847 };
848 static const char *const f16_patt[] = {
76bc74dc 849 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 850 };
ccc9c027
L		 851 /* nopl (%[re]ax) */
852 static const char alt_3[] =
853 {0x0f,0x1f,0x00};
854 /* nopl 0(%[re]ax) */
855 static const char alt_4[] =
856 {0x0f,0x1f,0x40,0x00};
857 /* nopl 0(%[re]ax,%[re]ax,1) */
858 static const char alt_5[] =
859 {0x0f,0x1f,0x44,0x00,0x00};
860 /* nopw 0(%[re]ax,%[re]ax,1) */
861 static const char alt_6[] =
862 {0x66,0x0f,0x1f,0x44,0x00,0x00};
863 /* nopl 0L(%[re]ax) */
864 static const char alt_7[] =
865 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
866 /* nopl 0L(%[re]ax,%[re]ax,1) */
867 static const char alt_8[] =
868 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 /* nopw 0L(%[re]ax,%[re]ax,1) */
870 static const char alt_9[] =
871 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
872 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
873 static const char alt_10[] =
874 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 /* data16
876 nopw %cs:0L(%[re]ax,%[re]ax,1) */
877 static const char alt_long_11[] =
878 {0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 nopw %cs:0L(%[re]ax,%[re]ax,1) */
883 static const char alt_long_12[] =
884 {0x66,
885 0x66,
886 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
887 /* data16
888 data16
889 data16
890 nopw %cs:0L(%[re]ax,%[re]ax,1) */
891 static const char alt_long_13[] =
892 {0x66,
893 0x66,
894 0x66,
895 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 /* data16
897 data16
898 data16
899 data16
900 nopw %cs:0L(%[re]ax,%[re]ax,1) */
901 static const char alt_long_14[] =
902 {0x66,
903 0x66,
904 0x66,
905 0x66,
906 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
907 /* data16
908 data16
909 data16
910 data16
911 data16
912 nopw %cs:0L(%[re]ax,%[re]ax,1) */
913 static const char alt_long_15[] =
914 {0x66,
915 0x66,
916 0x66,
917 0x66,
918 0x66,
919 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
920 /* nopl 0(%[re]ax,%[re]ax,1)
921 nopw 0(%[re]ax,%[re]ax,1) */
922 static const char alt_short_11[] =
923 {0x0f,0x1f,0x44,0x00,0x00,
924 0x66,0x0f,0x1f,0x44,0x00,0x00};
925 /* nopw 0(%[re]ax,%[re]ax,1)
926 nopw 0(%[re]ax,%[re]ax,1) */
927 static const char alt_short_12[] =
928 {0x66,0x0f,0x1f,0x44,0x00,0x00,
929 0x66,0x0f,0x1f,0x44,0x00,0x00};
930 /* nopw 0(%[re]ax,%[re]ax,1)
931 nopl 0L(%[re]ax) */
932 static const char alt_short_13[] =
933 {0x66,0x0f,0x1f,0x44,0x00,0x00,
934 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
935 /* nopl 0L(%[re]ax)
936 nopl 0L(%[re]ax) */
937 static const char alt_short_14[] =
938 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
939 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
940 /* nopl 0L(%[re]ax)
941 nopl 0L(%[re]ax,%[re]ax,1) */
942 static const char alt_short_15[] =
943 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
944 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
945 static const char *const alt_short_patt[] = {
946 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
947 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
948 alt_short_14, alt_short_15
949 };
950 static const char *const alt_long_patt[] = {
951 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
952 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
953 alt_long_14, alt_long_15
954 };
252b5132 955
76bc74dc
L		 956 /* Only align for at least a positive non-zero boundary. */
957 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 958 return;
3e73aa7c 959
ccc9c027
L		 960 /* We need to decide which NOP sequence to use for 32bit and
961 64bit. When -mtune= is used:
4eed87de 962
76bc74dc
L		 963 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
964 PROCESSOR_GENERIC32, f32_patt will be used.
965 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 966 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
967 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 968 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 969 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 970 will be used.
ccc9c027 971
76bc74dc
L		 972 When -mtune= isn't used, alt_long_patt will be used if
973 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
974 be used.
ccc9c027
L		 975
976 When -march= or .arch is used, we can't use anything beyond
977 cpu_arch_isa_flags. */
978
979 if (flag_code == CODE_16BIT)
980 {
ccc9c027 981 if (count > 8)
33fef721 982 {
76bc74dc
L		 983 memcpy (fragP->fr_literal + fragP->fr_fix,
984 jump_31, count);
985 /* Adjust jump offset. */
986 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 987 }
76bc74dc
L		 988 else
989 memcpy (fragP->fr_literal + fragP->fr_fix,
990 f16_patt[count - 1], count);
252b5132 991 }
33fef721 992 else
ccc9c027
L		 993 {
994 const char *const *patt = NULL;
995
fbf3f584 996 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 997 {
998 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
999 switch (cpu_arch_tune)
1000 {
1001 case PROCESSOR_UNKNOWN:
1002 /* We use cpu_arch_isa_flags to check if we SHOULD
1003 optimize for Cpu686. */
fbf3f584 1004 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 1005 patt = alt_long_patt;
ccc9c027
L		 1006 else
1007 patt = f32_patt;
1008 break;
ccc9c027
L		 1009 case PROCESSOR_PENTIUMPRO:
1010 case PROCESSOR_PENTIUM4:
1011 case PROCESSOR_NOCONA:
ef05d495 1012 case PROCESSOR_CORE:
76bc74dc 1013 case PROCESSOR_CORE2:
bd5295b2 1014 case PROCESSOR_COREI7:
3632d14b 1015 case PROCESSOR_L1OM:
76bc74dc
L		 1016 case PROCESSOR_GENERIC64:
1017 patt = alt_long_patt;
1018 break;
ccc9c027
L		 1019 case PROCESSOR_K6:
1020 case PROCESSOR_ATHLON:
1021 case PROCESSOR_K8:
4eed87de 1022 case PROCESSOR_AMDFAM10:
68339fdf 1023 case PROCESSOR_BDVER1:
ccc9c027
L		 1024 patt = alt_short_patt;
1025 break;
76bc74dc 1026 case PROCESSOR_I386:
ccc9c027
L		 1027 case PROCESSOR_I486:
1028 case PROCESSOR_PENTIUM:
1029 case PROCESSOR_GENERIC32:
1030 patt = f32_patt;
1031 break;
4eed87de 1032 }
ccc9c027
L		 1033 }
1034 else
1035 {
fbf3f584 1036 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1037 {
1038 case PROCESSOR_UNKNOWN:
e6a14101 1039 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1040 PROCESSOR_UNKNOWN. */
1041 abort ();
1042 break;
1043
76bc74dc 1044 case PROCESSOR_I386:
ccc9c027
L		 1045 case PROCESSOR_I486:
1046 case PROCESSOR_PENTIUM:
ccc9c027
L		 1047 case PROCESSOR_K6:
1048 case PROCESSOR_ATHLON:
1049 case PROCESSOR_K8:
4eed87de 1050 case PROCESSOR_AMDFAM10:
68339fdf 1051 case PROCESSOR_BDVER1:
ccc9c027
L		 1052 case PROCESSOR_GENERIC32:
1053 /* We use cpu_arch_isa_flags to check if we CAN optimize
1054 for Cpu686. */
fbf3f584 1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1056 patt = alt_short_patt;
1057 else
1058 patt = f32_patt;
1059 break;
76bc74dc
L		 1060 case PROCESSOR_PENTIUMPRO:
1061 case PROCESSOR_PENTIUM4:
1062 case PROCESSOR_NOCONA:
1063 case PROCESSOR_CORE:
ef05d495 1064 case PROCESSOR_CORE2:
bd5295b2 1065 case PROCESSOR_COREI7:
3632d14b 1066 case PROCESSOR_L1OM:
fbf3f584 1067 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1068 patt = alt_long_patt;
1069 else
1070 patt = f32_patt;
1071 break;
1072 case PROCESSOR_GENERIC64:
76bc74dc 1073 patt = alt_long_patt;
ccc9c027 1074 break;
4eed87de 1075 }
ccc9c027
L		 1076 }
1077
76bc74dc
L		 1078 if (patt == f32_patt)
1079 {
1080 /* If the padding is less than 15 bytes, we use the normal
1081 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1082 its offset. */
1083 int limit;
76ba9986 1084
711eedef
L		 1085 /* For 64bit, the limit is 3 bytes. */
1086 if (flag_code == CODE_64BIT
1087 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1088 limit = 3;
1089 else
1090 limit = 15;
1091 if (count < limit)
76bc74dc
L		 1092 memcpy (fragP->fr_literal + fragP->fr_fix,
1093 patt[count - 1], count);
1094 else
1095 {
1096 memcpy (fragP->fr_literal + fragP->fr_fix,
1097 jump_31, count);
1098 /* Adjust jump offset. */
1099 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1100 }
1101 }
1102 else
1103 {
1104 /* Maximum length of an instruction is 15 byte. If the
1105 padding is greater than 15 bytes and we don't use jump,
1106 we have to break it into smaller pieces. */
1107 int padding = count;
1108 while (padding > 15)
1109 {
1110 padding -= 15;
1111 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1112 patt [14], 15);
1113 }
1114
1115 if (padding)
1116 memcpy (fragP->fr_literal + fragP->fr_fix,
1117 patt [padding - 1], padding);
1118 }
ccc9c027 1119 }
33fef721 1120 fragP->fr_var = count;
252b5132
RH		 1121}
1122
c6fb90c8 1123static INLINE int
0dfbf9d7 1124operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1125{
0dfbf9d7 1126 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1127 {
1128 case 3:
0dfbf9d7 1129 if (x->array[2])
c6fb90c8
L		 1130 return 0;
1131 case 2:
0dfbf9d7 1132 if (x->array[1])
c6fb90c8
L		 1133 return 0;
1134 case 1:
0dfbf9d7 1135 return !x->array[0];
c6fb90c8
L		 1136 default:
1137 abort ();
1138 }
40fb9820
L		 1139}
1140
c6fb90c8 1141static INLINE void
0dfbf9d7 1142operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1143{
0dfbf9d7 1144 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1145 {
1146 case 3:
0dfbf9d7 1147 x->array[2] = v;
c6fb90c8 1148 case 2:
0dfbf9d7 1149 x->array[1] = v;
c6fb90c8 1150 case 1:
0dfbf9d7 1151 x->array[0] = v;
c6fb90c8
L		 1152 break;
1153 default:
1154 abort ();
1155 }
1156}
40fb9820 1157
c6fb90c8 1158static INLINE int
0dfbf9d7
L		 1159operand_type_equal (const union i386_operand_type *x,
1160 const union i386_operand_type *y)
c6fb90c8 1161{
0dfbf9d7 1162 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1163 {
1164 case 3:
0dfbf9d7 1165 if (x->array[2] != y->array[2])
c6fb90c8
L		 1166 return 0;
1167 case 2:
0dfbf9d7 1168 if (x->array[1] != y->array[1])
c6fb90c8
L		 1169 return 0;
1170 case 1:
0dfbf9d7 1171 return x->array[0] == y->array[0];
c6fb90c8
L		 1172 break;
1173 default:
1174 abort ();
1175 }
1176}
40fb9820 1177
0dfbf9d7
L		 1178static INLINE int
1179cpu_flags_all_zero (const union i386_cpu_flags *x)
1180{
1181 switch (ARRAY_SIZE(x->array))
1182 {
1183 case 3:
1184 if (x->array[2])
1185 return 0;
1186 case 2:
1187 if (x->array[1])
1188 return 0;
1189 case 1:
1190 return !x->array[0];
1191 default:
1192 abort ();
1193 }
1194}
1195
1196static INLINE void
1197cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1198{
1199 switch (ARRAY_SIZE(x->array))
1200 {
1201 case 3:
1202 x->array[2] = v;
1203 case 2:
1204 x->array[1] = v;
1205 case 1:
1206 x->array[0] = v;
1207 break;
1208 default:
1209 abort ();
1210 }
1211}
1212
1213static INLINE int
1214cpu_flags_equal (const union i386_cpu_flags *x,
1215 const union i386_cpu_flags *y)
1216{
1217 switch (ARRAY_SIZE(x->array))
1218 {
1219 case 3:
1220 if (x->array[2] != y->array[2])
1221 return 0;
1222 case 2:
1223 if (x->array[1] != y->array[1])
1224 return 0;
1225 case 1:
1226 return x->array[0] == y->array[0];
1227 break;
1228 default:
1229 abort ();
1230 }
1231}
c6fb90c8
L		 1232
1233static INLINE int
1234cpu_flags_check_cpu64 (i386_cpu_flags f)
1235{
1236 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1237 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1238}
1239
c6fb90c8
L		 1240static INLINE i386_cpu_flags
1241cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1242{
c6fb90c8
L		 1243 switch (ARRAY_SIZE (x.array))
1244 {
1245 case 3:
1246 x.array [2] &= y.array [2];
1247 case 2:
1248 x.array [1] &= y.array [1];
1249 case 1:
1250 x.array [0] &= y.array [0];
1251 break;
1252 default:
1253 abort ();
1254 }
1255 return x;
1256}
40fb9820 1257
c6fb90c8
L		 1258static INLINE i386_cpu_flags
1259cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1260{
c6fb90c8 1261 switch (ARRAY_SIZE (x.array))
40fb9820 1262 {
c6fb90c8
L		 1263 case 3:
1264 x.array [2] |= y.array [2];
1265 case 2:
1266 x.array [1] |= y.array [1];
1267 case 1:
1268 x.array [0] |= y.array [0];
40fb9820
L		 1269 break;
1270 default:
1271 abort ();
1272 }
40fb9820
L		 1273 return x;
1274}
1275
309d3373
JB		 1276static INLINE i386_cpu_flags
1277cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1278{
1279 switch (ARRAY_SIZE (x.array))
1280 {
1281 case 3:
1282 x.array [2] &= ~y.array [2];
1283 case 2:
1284 x.array [1] &= ~y.array [1];
1285 case 1:
1286 x.array [0] &= ~y.array [0];
1287 break;
1288 default:
1289 abort ();
1290 }
1291 return x;
1292}
1293
c0f3af97
L		 1294#define CPU_FLAGS_ARCH_MATCH 0x1
1295#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1296#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1297#define CPU_FLAGS_PCLMUL_MATCH 0x8
1298#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1299
a5ff0eb2 1300#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1301 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1302 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1303#define CPU_FLAGS_PERFECT_MATCH \
1304 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1305
1306/* Return CPU flags match bits. */
3629bb00 1307
40fb9820 1308static int
d3ce72d0 1309cpu_flags_match (const insn_template *t)
40fb9820 1310{
c0f3af97
L		 1311 i386_cpu_flags x = t->cpu_flags;
1312 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1313
1314 x.bitfield.cpu64 = 0;
1315 x.bitfield.cpuno64 = 0;
1316
0dfbf9d7 1317 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1318 {
1319 /* This instruction is available on all archs. */
1320 match |= CPU_FLAGS_32BIT_MATCH;
1321 }
3629bb00
L		 1322 else
1323 {
c0f3af97 1324 /* This instruction is available only on some archs. */
3629bb00
L		 1325 i386_cpu_flags cpu = cpu_arch_flags;
1326
1327 cpu.bitfield.cpu64 = 0;
1328 cpu.bitfield.cpuno64 = 0;
1329 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1330 if (!cpu_flags_all_zero (&cpu))
1331 {
a5ff0eb2
L		 1332 if (x.bitfield.cpuavx)
1333 {
ce2f5b3c 1334 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1335 if (cpu.bitfield.cpuavx)
1336 {
1337 /* Check SSE2AVX. */
1338 if (!t->opcode_modifier.sse2avx|| sse2avx)
1339 {
1340 match |= (CPU_FLAGS_ARCH_MATCH
1341 | CPU_FLAGS_AVX_MATCH);
1342 /* Check AES. */
1343 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1344 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1345 /* Check PCLMUL. */
1346 if (!x.bitfield.cpupclmul
1347 || cpu.bitfield.cpupclmul)
1348 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1349 }
1350 }
1351 else
1352 match |= CPU_FLAGS_ARCH_MATCH;
1353 }
1354 else
c0f3af97
L		 1355 match |= CPU_FLAGS_32BIT_MATCH;
1356 }
3629bb00 1357 }
c0f3af97 1358 return match;
40fb9820
L		 1359}
1360
c6fb90c8
L		 1361static INLINE i386_operand_type
1362operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1363{
c6fb90c8
L		 1364 switch (ARRAY_SIZE (x.array))
1365 {
1366 case 3:
1367 x.array [2] &= y.array [2];
1368 case 2:
1369 x.array [1] &= y.array [1];
1370 case 1:
1371 x.array [0] &= y.array [0];
1372 break;
1373 default:
1374 abort ();
1375 }
1376 return x;
40fb9820
L		 1377}
1378
c6fb90c8
L		 1379static INLINE i386_operand_type
1380operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1381{
c6fb90c8 1382 switch (ARRAY_SIZE (x.array))
40fb9820 1383 {
c6fb90c8
L		 1384 case 3:
1385 x.array [2] |= y.array [2];
1386 case 2:
1387 x.array [1] |= y.array [1];
1388 case 1:
1389 x.array [0] |= y.array [0];
40fb9820
L		 1390 break;
1391 default:
1392 abort ();
1393 }
c6fb90c8
L		 1394 return x;
1395}
40fb9820 1396
c6fb90c8
L		 1397static INLINE i386_operand_type
1398operand_type_xor (i386_operand_type x, i386_operand_type y)
1399{
1400 switch (ARRAY_SIZE (x.array))
1401 {
1402 case 3:
1403 x.array [2] ^= y.array [2];
1404 case 2:
1405 x.array [1] ^= y.array [1];
1406 case 1:
1407 x.array [0] ^= y.array [0];
1408 break;
1409 default:
1410 abort ();
1411 }
40fb9820
L		 1412 return x;
1413}
1414
1415static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1416static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1417static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1418static const i386_operand_type inoutportreg
1419 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1420static const i386_operand_type reg16_inoutportreg
1421 = OPERAND_TYPE_REG16_INOUTPORTREG;
1422static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1423static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1424static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1425static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1426static const i386_operand_type anydisp
1427 = OPERAND_TYPE_ANYDISP;
40fb9820 1428static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1429static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1430static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1431static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1432static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1433static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1434static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1435static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1436static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1437static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1438static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1439static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1440
1441enum operand_type
1442{
1443 reg,
40fb9820
L		 1444 imm,
1445 disp,
1446 anymem
1447};
1448
c6fb90c8 1449static INLINE int
40fb9820
L		 1450operand_type_check (i386_operand_type t, enum operand_type c)
1451{
1452 switch (c)
1453 {
1454 case reg:
1455 return (t.bitfield.reg8
1456 || t.bitfield.reg16
1457 || t.bitfield.reg32
1458 || t.bitfield.reg64);
1459
40fb9820
L		 1460 case imm:
1461 return (t.bitfield.imm8
1462 || t.bitfield.imm8s
1463 || t.bitfield.imm16
1464 || t.bitfield.imm32
1465 || t.bitfield.imm32s
1466 || t.bitfield.imm64);
1467
1468 case disp:
1469 return (t.bitfield.disp8
1470 || t.bitfield.disp16
1471 || t.bitfield.disp32
1472 || t.bitfield.disp32s
1473 || t.bitfield.disp64);
1474
1475 case anymem:
1476 return (t.bitfield.disp8
1477 || t.bitfield.disp16
1478 || t.bitfield.disp32
1479 || t.bitfield.disp32s
1480 || t.bitfield.disp64
1481 || t.bitfield.baseindex);
1482
1483 default:
1484 abort ();
1485 }
2cfe26b6
AM		 1486
1487 return 0;
40fb9820
L		 1488}
1489
5c07affc
L		 1490/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1491 operand J for instruction template T. */
1492
1493static INLINE int
d3ce72d0 1494match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1495{
1496 return !((i.types[j].bitfield.byte
1497 && !t->operand_types[j].bitfield.byte)
1498 || (i.types[j].bitfield.word
1499 && !t->operand_types[j].bitfield.word)
1500 || (i.types[j].bitfield.dword
1501 && !t->operand_types[j].bitfield.dword)
1502 || (i.types[j].bitfield.qword
1503 && !t->operand_types[j].bitfield.qword));
1504}
1505
1506/* Return 1 if there is no conflict in any size on operand J for
1507 instruction template T. */
1508
1509static INLINE int
d3ce72d0 1510match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1511{
1512 return (match_reg_size (t, j)
1513 && !((i.types[j].bitfield.unspecified
1514 && !t->operand_types[j].bitfield.unspecified)
1515 || (i.types[j].bitfield.fword
1516 && !t->operand_types[j].bitfield.fword)
1517 || (i.types[j].bitfield.tbyte
1518 && !t->operand_types[j].bitfield.tbyte)
1519 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1520 && !t->operand_types[j].bitfield.xmmword)
1521 || (i.types[j].bitfield.ymmword
1522 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1523}
1524
1525/* Return 1 if there is no size conflict on any operands for
1526 instruction template T. */
1527
1528static INLINE int
d3ce72d0 1529operand_size_match (const insn_template *t)
5c07affc
L		 1530{
1531 unsigned int j;
1532 int match = 1;
1533
1534 /* Don't check jump instructions. */
1535 if (t->opcode_modifier.jump
1536 || t->opcode_modifier.jumpbyte
1537 || t->opcode_modifier.jumpdword
1538 || t->opcode_modifier.jumpintersegment)
1539 return match;
1540
1541 /* Check memory and accumulator operand size. */
1542 for (j = 0; j < i.operands; j++)
1543 {
1544 if (t->operand_types[j].bitfield.anysize)
1545 continue;
1546
1547 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1548 {
1549 match = 0;
1550 break;
1551 }
1552
1553 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1554 {
1555 match = 0;
1556 break;
1557 }
1558 }
1559
1560 if (match
1561 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1562 return match;
1563
1564 /* Check reverse. */
9c2799c2 1565 gas_assert (i.operands == 2);
5c07affc
L		 1566
1567 match = 1;
1568 for (j = 0; j < 2; j++)
1569 {
1570 if (t->operand_types[j].bitfield.acc
1571 && !match_reg_size (t, j ? 0 : 1))
1572 {
1573 match = 0;
1574 break;
1575 }
1576
1577 if (i.types[j].bitfield.mem
1578 && !match_mem_size (t, j ? 0 : 1))
1579 {
1580 match = 0;
1581 break;
1582 }
1583 }
1584
1585 return match;
1586}
1587
c6fb90c8 1588static INLINE int
40fb9820
L		 1589operand_type_match (i386_operand_type overlap,
1590 i386_operand_type given)
1591{
1592 i386_operand_type temp = overlap;
1593
1594 temp.bitfield.jumpabsolute = 0;
7d5e4556 1595 temp.bitfield.unspecified = 0;
5c07affc
L		 1596 temp.bitfield.byte = 0;
1597 temp.bitfield.word = 0;
1598 temp.bitfield.dword = 0;
1599 temp.bitfield.fword = 0;
1600 temp.bitfield.qword = 0;
1601 temp.bitfield.tbyte = 0;
1602 temp.bitfield.xmmword = 0;
c0f3af97 1603 temp.bitfield.ymmword = 0;
0dfbf9d7 1604 if (operand_type_all_zero (&temp))
40fb9820
L		 1605 return 0;
1606
1607 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1608 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1609}
1610
7d5e4556 1611/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1612 unless the expected operand type register overlap is null.
1613 Note that Acc in a template matches every size of reg. */
1614
c6fb90c8 1615static INLINE int
40fb9820
L		 1616operand_type_register_match (i386_operand_type m0,
1617 i386_operand_type g0,
1618 i386_operand_type t0,
1619 i386_operand_type m1,
1620 i386_operand_type g1,
1621 i386_operand_type t1)
1622{
1623 if (!operand_type_check (g0, reg))
1624 return 1;
1625
1626 if (!operand_type_check (g1, reg))
1627 return 1;
1628
1629 if (g0.bitfield.reg8 == g1.bitfield.reg8
1630 && g0.bitfield.reg16 == g1.bitfield.reg16
1631 && g0.bitfield.reg32 == g1.bitfield.reg32
1632 && g0.bitfield.reg64 == g1.bitfield.reg64)
1633 return 1;
1634
1635 if (m0.bitfield.acc)
1636 {
1637 t0.bitfield.reg8 = 1;
1638 t0.bitfield.reg16 = 1;
1639 t0.bitfield.reg32 = 1;
1640 t0.bitfield.reg64 = 1;
1641 }
1642
1643 if (m1.bitfield.acc)
1644 {
1645 t1.bitfield.reg8 = 1;
1646 t1.bitfield.reg16 = 1;
1647 t1.bitfield.reg32 = 1;
1648 t1.bitfield.reg64 = 1;
1649 }
1650
1651 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1652 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1653 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1654 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1655}
1656
252b5132 1657static INLINE unsigned int
40fb9820 1658mode_from_disp_size (i386_operand_type t)
252b5132 1659{
40fb9820
L		 1660 if (t.bitfield.disp8)
1661 return 1;
1662 else if (t.bitfield.disp16
1663 || t.bitfield.disp32
1664 || t.bitfield.disp32s)
1665 return 2;
1666 else
1667 return 0;
252b5132
RH		 1668}
1669
1670static INLINE int
e3bb37b5 1671fits_in_signed_byte (offsetT num)
252b5132
RH		 1672{
1673 return (num >= -128) && (num <= 127);
47926f60 1674}
252b5132
RH		 1675
1676static INLINE int
e3bb37b5 1677fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1678{
1679 return (num & 0xff) == num;
47926f60 1680}
252b5132
RH		 1681
1682static INLINE int
e3bb37b5 1683fits_in_unsigned_word (offsetT num)
252b5132
RH		 1684{
1685 return (num & 0xffff) == num;
47926f60 1686}
252b5132
RH		 1687
1688static INLINE int
e3bb37b5 1689fits_in_signed_word (offsetT num)
252b5132
RH		 1690{
1691 return (-32768 <= num) && (num <= 32767);
47926f60 1692}
2a962e6d 1693
3e73aa7c 1694static INLINE int
e3bb37b5 1695fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1696{
1697#ifndef BFD64
1698 return 1;
1699#else
1700 return (!(((offsetT) -1 << 31) & num)
1701 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1702#endif
1703} /* fits_in_signed_long() */
2a962e6d 1704
3e73aa7c 1705static INLINE int
e3bb37b5 1706fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1707{
1708#ifndef BFD64
1709 return 1;
1710#else
1711 return (num & (((offsetT) 2 << 31) - 1)) == num;
1712#endif
1713} /* fits_in_unsigned_long() */
252b5132 1714
a683cc34
SP		 1715static INLINE int
1716fits_in_imm4 (offsetT num)
1717{
1718 return (num & 0xf) == num;
1719}
1720
40fb9820 1721static i386_operand_type
e3bb37b5 1722smallest_imm_type (offsetT num)
252b5132 1723{
40fb9820 1724 i386_operand_type t;
7ab9ffdd 1725
0dfbf9d7 1726 operand_type_set (&t, 0);
40fb9820
L		 1727 t.bitfield.imm64 = 1;
1728
1729 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1730 {
1731 /* This code is disabled on the 486 because all the Imm1 forms
1732 in the opcode table are slower on the i486. They're the
1733 versions with the implicitly specified single-position
1734 displacement, which has another syntax if you really want to
1735 use that form. */
40fb9820
L		 1736 t.bitfield.imm1 = 1;
1737 t.bitfield.imm8 = 1;
1738 t.bitfield.imm8s = 1;
1739 t.bitfield.imm16 = 1;
1740 t.bitfield.imm32 = 1;
1741 t.bitfield.imm32s = 1;
1742 }
1743 else if (fits_in_signed_byte (num))
1744 {
1745 t.bitfield.imm8 = 1;
1746 t.bitfield.imm8s = 1;
1747 t.bitfield.imm16 = 1;
1748 t.bitfield.imm32 = 1;
1749 t.bitfield.imm32s = 1;
1750 }
1751 else if (fits_in_unsigned_byte (num))
1752 {
1753 t.bitfield.imm8 = 1;
1754 t.bitfield.imm16 = 1;
1755 t.bitfield.imm32 = 1;
1756 t.bitfield.imm32s = 1;
1757 }
1758 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1759 {
1760 t.bitfield.imm16 = 1;
1761 t.bitfield.imm32 = 1;
1762 t.bitfield.imm32s = 1;
1763 }
1764 else if (fits_in_signed_long (num))
1765 {
1766 t.bitfield.imm32 = 1;
1767 t.bitfield.imm32s = 1;
1768 }
1769 else if (fits_in_unsigned_long (num))
1770 t.bitfield.imm32 = 1;
1771
1772 return t;
47926f60 1773}
252b5132 1774
847f7ad4 1775static offsetT
e3bb37b5 1776offset_in_range (offsetT val, int size)
847f7ad4 1777{
508866be 1778 addressT mask;
ba2adb93 1779
847f7ad4
AM		 1780 switch (size)
1781 {
508866be
L		 1782 case 1: mask = ((addressT) 1 << 8) - 1; break;
1783 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1784 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1785#ifdef BFD64
1786 case 8: mask = ((addressT) 2 << 63) - 1; break;
1787#endif
47926f60 1788 default: abort ();
847f7ad4
AM		 1789 }
1790
9de868bf
L		 1791#ifdef BFD64
1792 /* If BFD64, sign extend val for 32bit address mode. */
1793 if (flag_code != CODE_64BIT
1794 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1795 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1796 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1797#endif
ba2adb93 1798
47926f60 1799 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1800 {
1801 char buf1[40], buf2[40];
1802
1803 sprint_value (buf1, val);
1804 sprint_value (buf2, val & mask);
1805 as_warn (_("%s shortened to %s"), buf1, buf2);
1806 }
1807 return val & mask;
1808}
1809
c32fa91d
L		 1810enum PREFIX_GROUP
1811{
1812 PREFIX_EXIST = 0,
1813 PREFIX_LOCK,
1814 PREFIX_REP,
1815 PREFIX_OTHER
1816};
1817
1818/* Returns
1819 a. PREFIX_EXIST if attempting to add a prefix where one from the
1820 same class already exists.
1821 b. PREFIX_LOCK if lock prefix is added.
1822 c. PREFIX_REP if rep/repne prefix is added.
1823 d. PREFIX_OTHER if other prefix is added.
1824 */
1825
1826static enum PREFIX_GROUP
e3bb37b5 1827add_prefix (unsigned int prefix)
252b5132 1828{
c32fa91d 1829 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1830 unsigned int q;
252b5132 1831
29b0f896
AM		 1832 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1833 && flag_code == CODE_64BIT)
b1905489 1834 {
161a04f6
L		 1835 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1836 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1837 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1838 ret = PREFIX_EXIST;
b1905489
JB		 1839 q = REX_PREFIX;
1840 }
3e73aa7c 1841 else
b1905489
JB		 1842 {
1843 switch (prefix)
1844 {
1845 default:
1846 abort ();
1847
1848 case CS_PREFIX_OPCODE:
1849 case DS_PREFIX_OPCODE:
1850 case ES_PREFIX_OPCODE:
1851 case FS_PREFIX_OPCODE:
1852 case GS_PREFIX_OPCODE:
1853 case SS_PREFIX_OPCODE:
1854 q = SEG_PREFIX;
1855 break;
1856
1857 case REPNE_PREFIX_OPCODE:
1858 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1859 q = REP_PREFIX;
1860 ret = PREFIX_REP;
1861 break;
1862
b1905489 1863 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1864 q = LOCK_PREFIX;
1865 ret = PREFIX_LOCK;
b1905489
JB		 1866 break;
1867
1868 case FWAIT_OPCODE:
1869 q = WAIT_PREFIX;
1870 break;
1871
1872 case ADDR_PREFIX_OPCODE:
1873 q = ADDR_PREFIX;
1874 break;
1875
1876 case DATA_PREFIX_OPCODE:
1877 q = DATA_PREFIX;
1878 break;
1879 }
1880 if (i.prefix[q] != 0)
c32fa91d 1881 ret = PREFIX_EXIST;
b1905489 1882 }
252b5132 1883
b1905489 1884 if (ret)
252b5132 1885 {
b1905489
JB		 1886 if (!i.prefix[q])
1887 ++i.prefixes;
1888 i.prefix[q] |= prefix;
252b5132 1889 }
b1905489
JB		 1890 else
1891 as_bad (_("same type of prefix used twice"));
252b5132 1892
252b5132
RH		 1893 return ret;
1894}
1895
1896static void
e3bb37b5 1897set_code_flag (int value)
eecb386c 1898{
1e9cc1c2 1899 flag_code = (enum flag_code) value;
40fb9820
L		 1900 if (flag_code == CODE_64BIT)
1901 {
1902 cpu_arch_flags.bitfield.cpu64 = 1;
1903 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1904 }
1905 else
1906 {
1907 cpu_arch_flags.bitfield.cpu64 = 0;
1908 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1909 }
1910 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1911 {
1912 as_bad (_("64bit mode not supported on this CPU."));
1913 }
40fb9820 1914 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1915 {
1916 as_bad (_("32bit mode not supported on this CPU."));
1917 }
eecb386c
AM		 1918 stackop_size = '\0';
1919}
1920
1921static void
e3bb37b5 1922set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1923{
1e9cc1c2 1924 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1925 if (flag_code != CODE_16BIT)
1926 abort ();
1927 cpu_arch_flags.bitfield.cpu64 = 0;
1928 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1929 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1930}
1931
1932static void
e3bb37b5 1933set_intel_syntax (int syntax_flag)
252b5132
RH		 1934{
1935 /* Find out if register prefixing is specified. */
1936 int ask_naked_reg = 0;
1937
1938 SKIP_WHITESPACE ();
29b0f896 1939 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1940 {
1941 char *string = input_line_pointer;
1942 int e = get_symbol_end ();
1943
47926f60 1944 if (strcmp (string, "prefix") == 0)
252b5132 1945 ask_naked_reg = 1;
47926f60 1946 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1947 ask_naked_reg = -1;
1948 else
d0b47220 1949 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1950 *input_line_pointer = e;
1951 }
1952 demand_empty_rest_of_line ();
c3332e24 1953
252b5132
RH		 1954 intel_syntax = syntax_flag;
1955
1956 if (ask_naked_reg == 0)
f86103b7
AM		 1957 allow_naked_reg = (intel_syntax
1958 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1959 else
1960 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1961
ee86248c 1962 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1963
e4a3b5a4 1964 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1965 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1966 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1967}
1968
1efbbeb4
L		 1969static void
1970set_intel_mnemonic (int mnemonic_flag)
1971{
e1d4d893 1972 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1973}
1974
db51cc60
L		 1975static void
1976set_allow_index_reg (int flag)
1977{
1978 allow_index_reg = flag;
1979}
1980
cb19c032
L		 1981static void
1982set_sse_check (int dummy ATTRIBUTE_UNUSED)
1983{
1984 SKIP_WHITESPACE ();
1985
1986 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1987 {
1988 char *string = input_line_pointer;
1989 int e = get_symbol_end ();
1990
1991 if (strcmp (string, "none") == 0)
1992 sse_check = sse_check_none;
1993 else if (strcmp (string, "warning") == 0)
1994 sse_check = sse_check_warning;
1995 else if (strcmp (string, "error") == 0)
1996 sse_check = sse_check_error;
1997 else
1998 as_bad (_("bad argument to sse_check directive."));
1999 *input_line_pointer = e;
2000 }
2001 else
2002 as_bad (_("missing argument for sse_check directive"));
2003
2004 demand_empty_rest_of_line ();
2005}
2006
8a9036a4
L		 2007static void
2008check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2009 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2010{
2011#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2012 static const char *arch;
2013
2014 /* Intel LIOM is only supported on ELF. */
2015 if (!IS_ELF)
2016 return;
2017
2018 if (!arch)
2019 {
2020 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2021 use default_arch. */
2022 arch = cpu_arch_name;
2023 if (!arch)
2024 arch = default_arch;
2025 }
2026
3632d14b 2027 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2028 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2029 || new_flag.bitfield.cpul1om)
8a9036a4 2030 return;
76ba9986 2031
8a9036a4
L		 2032 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2033#endif
2034}
2035
e413e4e9 2036static void
e3bb37b5 2037set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2038{
47926f60 2039 SKIP_WHITESPACE ();
e413e4e9 2040
29b0f896 2041 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2042 {
2043 char *string = input_line_pointer;
2044 int e = get_symbol_end ();
91d6fa6a 2045 unsigned int j;
40fb9820 2046 i386_cpu_flags flags;
e413e4e9 2047
91d6fa6a 2048 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2049 {
91d6fa6a 2050 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2051 {
91d6fa6a 2052 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2053
5c6af06e
JB		 2054 if (*string != '.')
2055 {
91d6fa6a 2056 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2057 cpu_sub_arch_name = NULL;
91d6fa6a 2058 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2059 if (flag_code == CODE_64BIT)
2060 {
2061 cpu_arch_flags.bitfield.cpu64 = 1;
2062 cpu_arch_flags.bitfield.cpuno64 = 0;
2063 }
2064 else
2065 {
2066 cpu_arch_flags.bitfield.cpu64 = 0;
2067 cpu_arch_flags.bitfield.cpuno64 = 1;
2068 }
91d6fa6a
NC		 2069 cpu_arch_isa = cpu_arch[j].type;
2070 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2071 if (!cpu_arch_tune_set)
2072 {
2073 cpu_arch_tune = cpu_arch_isa;
2074 cpu_arch_tune_flags = cpu_arch_isa_flags;
2075 }
5c6af06e
JB		 2076 break;
2077 }
40fb9820 2078
309d3373
JB		 2079 if (strncmp (string + 1, "no", 2))
2080 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2081 cpu_arch[j].flags);
309d3373
JB		 2082 else
2083 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 2084 cpu_arch[j].flags);
0dfbf9d7 2085 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2086 {
6305a203
L		 2087 if (cpu_sub_arch_name)
2088 {
2089 char *name = cpu_sub_arch_name;
2090 cpu_sub_arch_name = concat (name,
91d6fa6a 2091 cpu_arch[j].name,
1bf57e9f 2092 (const char *) NULL);
6305a203
L		 2093 free (name);
2094 }
2095 else
91d6fa6a 2096 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2097 cpu_arch_flags = flags;
5c6af06e
JB		 2098 }
2099 *input_line_pointer = e;
2100 demand_empty_rest_of_line ();
2101 return;
e413e4e9
AM		 2102 }
2103 }
91d6fa6a 2104 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2105 as_bad (_("no such architecture: `%s'"), string);
2106
2107 *input_line_pointer = e;
2108 }
2109 else
2110 as_bad (_("missing cpu architecture"));
2111
fddf5b5b
AM		 2112 no_cond_jump_promotion = 0;
2113 if (*input_line_pointer == ','
29b0f896 2114 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2115 {
2116 char *string = ++input_line_pointer;
2117 int e = get_symbol_end ();
2118
2119 if (strcmp (string, "nojumps") == 0)
2120 no_cond_jump_promotion = 1;
2121 else if (strcmp (string, "jumps") == 0)
2122 ;
2123 else
2124 as_bad (_("no such architecture modifier: `%s'"), string);
2125
2126 *input_line_pointer = e;
2127 }
2128
e413e4e9
AM		 2129 demand_empty_rest_of_line ();
2130}
2131
8a9036a4
L		 2132enum bfd_architecture
2133i386_arch (void)
2134{
3632d14b 2135 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2136 {
2137 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2138 || flag_code != CODE_64BIT)
2139 as_fatal (_("Intel L1OM is 64bit ELF only"));
2140 return bfd_arch_l1om;
2141 }
2142 else
2143 return bfd_arch_i386;
2144}
2145
b9d79e03
JH		 2146unsigned long
2147i386_mach ()
2148{
2149 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2150 {
3632d14b 2151 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2152 {
2153 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2154 as_fatal (_("Intel L1OM is 64bit ELF only"));
2155 return bfd_mach_l1om;
2156 }
2157 else
2158 return bfd_mach_x86_64;
2159 }
b9d79e03
JH		 2160 else if (!strcmp (default_arch, "i386"))
2161 return bfd_mach_i386_i386;
2162 else
2163 as_fatal (_("Unknown architecture"));
2164}
b9d79e03 2165\f
252b5132
RH		 2166void
2167md_begin ()
2168{
2169 const char *hash_err;
2170
47926f60 2171 /* Initialize op_hash hash table. */
252b5132
RH		 2172 op_hash = hash_new ();
2173
2174 {
d3ce72d0 2175 const insn_template *optab;
29b0f896 2176 templates *core_optab;
252b5132 2177
47926f60
KH		 2178 /* Setup for loop. */
2179 optab = i386_optab;
252b5132
RH		 2180 core_optab = (templates *) xmalloc (sizeof (templates));
2181 core_optab->start = optab;
2182
2183 while (1)
2184 {
2185 ++optab;
2186 if (optab->name == NULL
2187 || strcmp (optab->name, (optab - 1)->name) != 0)
2188 {
2189 /* different name --> ship out current template list;
47926f60 2190 add to hash table; & begin anew. */
252b5132
RH		 2191 core_optab->end = optab;
2192 hash_err = hash_insert (op_hash,
2193 (optab - 1)->name,
5a49b8ac 2194 (void *) core_optab);
252b5132
RH		 2195 if (hash_err)
2196 {
252b5132
RH		 2197 as_fatal (_("Internal Error: Can't hash %s: %s"),
2198 (optab - 1)->name,
2199 hash_err);
2200 }
2201 if (optab->name == NULL)
2202 break;
2203 core_optab = (templates *) xmalloc (sizeof (templates));
2204 core_optab->start = optab;
2205 }
2206 }
2207 }
2208
47926f60 2209 /* Initialize reg_hash hash table. */
252b5132
RH		 2210 reg_hash = hash_new ();
2211 {
29b0f896 2212 const reg_entry *regtab;
c3fe08fa 2213 unsigned int regtab_size = i386_regtab_size;
252b5132 2214
c3fe08fa 2215 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2216 {
5a49b8ac 2217 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2218 if (hash_err)
3e73aa7c
JH		 2219 as_fatal (_("Internal Error: Can't hash %s: %s"),
2220 regtab->reg_name,
2221 hash_err);
252b5132
RH		 2222 }
2223 }
2224
47926f60 2225 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2226 {
29b0f896
AM		 2227 int c;
2228 char *p;
252b5132
RH		 2229
2230 for (c = 0; c < 256; c++)
2231 {
3882b010 2232 if (ISDIGIT (c))
252b5132
RH		 2233 {
2234 digit_chars[c] = c;
2235 mnemonic_chars[c] = c;
2236 register_chars[c] = c;
2237 operand_chars[c] = c;
2238 }
3882b010 2239 else if (ISLOWER (c))
252b5132
RH		 2240 {
2241 mnemonic_chars[c] = c;
2242 register_chars[c] = c;
2243 operand_chars[c] = c;
2244 }
3882b010 2245 else if (ISUPPER (c))
252b5132 2246 {
3882b010 2247 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2248 register_chars[c] = mnemonic_chars[c];
2249 operand_chars[c] = c;
2250 }
2251
3882b010 2252 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2253 identifier_chars[c] = c;
2254 else if (c >= 128)
2255 {
2256 identifier_chars[c] = c;
2257 operand_chars[c] = c;
2258 }
2259 }
2260
2261#ifdef LEX_AT
2262 identifier_chars['@'] = '@';
32137342
NC		 2263#endif
2264#ifdef LEX_QM
2265 identifier_chars['?'] = '?';
2266 operand_chars['?'] = '?';
252b5132 2267#endif
252b5132 2268 digit_chars['-'] = '-';
c0f3af97 2269 mnemonic_chars['_'] = '_';
791fe849 2270 mnemonic_chars['-'] = '-';
0003779b 2271 mnemonic_chars['.'] = '.';
252b5132
RH		 2272 identifier_chars['_'] = '_';
2273 identifier_chars['.'] = '.';
2274
2275 for (p = operand_special_chars; *p != '\0'; p++)
2276 operand_chars[(unsigned char) *p] = *p;
2277 }
2278
2279#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2280 if (IS_ELF)
252b5132
RH		 2281 {
2282 record_alignment (text_section, 2);
2283 record_alignment (data_section, 2);
2284 record_alignment (bss_section, 2);
2285 }
2286#endif
a4447b93
RH		 2287
2288 if (flag_code == CODE_64BIT)
2289 {
2290 x86_dwarf2_return_column = 16;
2291 x86_cie_data_alignment = -8;
2292 }
2293 else
2294 {
2295 x86_dwarf2_return_column = 8;
2296 x86_cie_data_alignment = -4;
2297 }
252b5132
RH		 2298}
2299
2300void
e3bb37b5 2301i386_print_statistics (FILE *file)
252b5132
RH		 2302{
2303 hash_print_statistics (file, "i386 opcode", op_hash);
2304 hash_print_statistics (file, "i386 register", reg_hash);
2305}
2306\f
252b5132
RH		 2307#ifdef DEBUG386
2308
ce8a8b2f 2309/* Debugging routines for md_assemble. */
d3ce72d0 2310static void pte (insn_template *);
40fb9820 2311static void pt (i386_operand_type);
e3bb37b5
L		 2312static void pe (expressionS *);
2313static void ps (symbolS *);
252b5132
RH		 2314
2315static void
e3bb37b5 2316pi (char *line, i386_insn *x)
252b5132 2317{
09f131f2 2318 unsigned int i;
252b5132
RH		 2319
2320 fprintf (stdout, "%s: template ", line);
2321 pte (&x->tm);
09f131f2
JH		 2322 fprintf (stdout, " address: base %s index %s scale %x\n",
2323 x->base_reg ? x->base_reg->reg_name : "none",
2324 x->index_reg ? x->index_reg->reg_name : "none",
2325 x->log2_scale_factor);
2326 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2327 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2328 fprintf (stdout, " sib: base %x index %x scale %x\n",
2329 x->sib.base, x->sib.index, x->sib.scale);
2330 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2331 (x->rex & REX_W) != 0,
2332 (x->rex & REX_R) != 0,
2333 (x->rex & REX_X) != 0,
2334 (x->rex & REX_B) != 0);
252b5132
RH		 2335 for (i = 0; i < x->operands; i++)
2336 {
2337 fprintf (stdout, " #%d: ", i + 1);
2338 pt (x->types[i]);
2339 fprintf (stdout, "\n");
40fb9820
L		 2340 if (x->types[i].bitfield.reg8
2341 || x->types[i].bitfield.reg16
2342 || x->types[i].bitfield.reg32
2343 || x->types[i].bitfield.reg64
2344 || x->types[i].bitfield.regmmx
2345 || x->types[i].bitfield.regxmm
c0f3af97 2346 || x->types[i].bitfield.regymm
40fb9820
L		 2347 || x->types[i].bitfield.sreg2
2348 || x->types[i].bitfield.sreg3
2349 || x->types[i].bitfield.control
2350 || x->types[i].bitfield.debug
2351 || x->types[i].bitfield.test)
520dc8e8 2352 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2353 if (operand_type_check (x->types[i], imm))
520dc8e8 2354 pe (x->op[i].imms);
40fb9820 2355 if (operand_type_check (x->types[i], disp))
520dc8e8 2356 pe (x->op[i].disps);
252b5132
RH		 2357 }
2358}
2359
2360static void
d3ce72d0 2361pte (insn_template *t)
252b5132 2362{
09f131f2 2363 unsigned int i;
252b5132 2364 fprintf (stdout, " %d operands ", t->operands);
47926f60 2365 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2366 if (t->extension_opcode != None)
2367 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2368 if (t->opcode_modifier.d)
252b5132 2369 fprintf (stdout, "D");
40fb9820 2370 if (t->opcode_modifier.w)
252b5132
RH		 2371 fprintf (stdout, "W");
2372 fprintf (stdout, "\n");
2373 for (i = 0; i < t->operands; i++)
2374 {
2375 fprintf (stdout, " #%d type ", i + 1);
2376 pt (t->operand_types[i]);
2377 fprintf (stdout, "\n");
2378 }
2379}
2380
2381static void
e3bb37b5 2382pe (expressionS *e)
252b5132 2383{
24eab124 2384 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2385 fprintf (stdout, " add_number %ld (%lx)\n",
2386 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2387 if (e->X_add_symbol)
2388 {
2389 fprintf (stdout, " add_symbol ");
2390 ps (e->X_add_symbol);
2391 fprintf (stdout, "\n");
2392 }
2393 if (e->X_op_symbol)
2394 {
2395 fprintf (stdout, " op_symbol ");
2396 ps (e->X_op_symbol);
2397 fprintf (stdout, "\n");
2398 }
2399}
2400
2401static void
e3bb37b5 2402ps (symbolS *s)
252b5132
RH		 2403{
2404 fprintf (stdout, "%s type %s%s",
2405 S_GET_NAME (s),
2406 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2407 segment_name (S_GET_SEGMENT (s)));
2408}
2409
7b81dfbb 2410static struct type_name
252b5132 2411 {
40fb9820
L		 2412 i386_operand_type mask;
2413 const char *name;
252b5132 2414 }
7b81dfbb 2415const type_names[] =
252b5132 2416{
40fb9820
L		 2417 { OPERAND_TYPE_REG8, "r8" },
2418 { OPERAND_TYPE_REG16, "r16" },
2419 { OPERAND_TYPE_REG32, "r32" },
2420 { OPERAND_TYPE_REG64, "r64" },
2421 { OPERAND_TYPE_IMM8, "i8" },
2422 { OPERAND_TYPE_IMM8, "i8s" },
2423 { OPERAND_TYPE_IMM16, "i16" },
2424 { OPERAND_TYPE_IMM32, "i32" },
2425 { OPERAND_TYPE_IMM32S, "i32s" },
2426 { OPERAND_TYPE_IMM64, "i64" },
2427 { OPERAND_TYPE_IMM1, "i1" },
2428 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2429 { OPERAND_TYPE_DISP8, "d8" },
2430 { OPERAND_TYPE_DISP16, "d16" },
2431 { OPERAND_TYPE_DISP32, "d32" },
2432 { OPERAND_TYPE_DISP32S, "d32s" },
2433 { OPERAND_TYPE_DISP64, "d64" },
2434 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2435 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2436 { OPERAND_TYPE_CONTROL, "control reg" },
2437 { OPERAND_TYPE_TEST, "test reg" },
2438 { OPERAND_TYPE_DEBUG, "debug reg" },
2439 { OPERAND_TYPE_FLOATREG, "FReg" },
2440 { OPERAND_TYPE_FLOATACC, "FAcc" },
2441 { OPERAND_TYPE_SREG2, "SReg2" },
2442 { OPERAND_TYPE_SREG3, "SReg3" },
2443 { OPERAND_TYPE_ACC, "Acc" },
2444 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2445 { OPERAND_TYPE_REGMMX, "rMMX" },
2446 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2447 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2448 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2449};
2450
2451static void
40fb9820 2452pt (i386_operand_type t)
252b5132 2453{
40fb9820 2454 unsigned int j;
c6fb90c8 2455 i386_operand_type a;
252b5132 2456
40fb9820 2457 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2458 {
2459 a = operand_type_and (t, type_names[j].mask);
0349dc08 2460 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2461 fprintf (stdout, "%s, ", type_names[j].name);
2462 }
252b5132
RH		 2463 fflush (stdout);
2464}
2465
2466#endif /* DEBUG386 */
2467\f
252b5132 2468static bfd_reloc_code_real_type
3956db08 2469reloc (unsigned int size,
64e74474
AM		 2470 int pcrel,
2471 int sign,
2472 bfd_reloc_code_real_type other)
252b5132 2473{
47926f60 2474 if (other != NO_RELOC)
3956db08 2475 {
91d6fa6a 2476 reloc_howto_type *rel;
3956db08
JB		 2477
2478 if (size == 8)
2479 switch (other)
2480 {
64e74474
AM		 2481 case BFD_RELOC_X86_64_GOT32:
2482 return BFD_RELOC_X86_64_GOT64;
2483 break;
2484 case BFD_RELOC_X86_64_PLTOFF64:
2485 return BFD_RELOC_X86_64_PLTOFF64;
2486 break;
2487 case BFD_RELOC_X86_64_GOTPC32:
2488 other = BFD_RELOC_X86_64_GOTPC64;
2489 break;
2490 case BFD_RELOC_X86_64_GOTPCREL:
2491 other = BFD_RELOC_X86_64_GOTPCREL64;
2492 break;
2493 case BFD_RELOC_X86_64_TPOFF32:
2494 other = BFD_RELOC_X86_64_TPOFF64;
2495 break;
2496 case BFD_RELOC_X86_64_DTPOFF32:
2497 other = BFD_RELOC_X86_64_DTPOFF64;
2498 break;
2499 default:
2500 break;
3956db08 2501 }
e05278af
JB		 2502
2503 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2504 if (size == 4 && flag_code != CODE_64BIT)
2505 sign = -1;
2506
91d6fa6a
NC		 2507 rel = bfd_reloc_type_lookup (stdoutput, other);
2508 if (!rel)
3956db08 2509 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2510 else if (size != bfd_get_reloc_size (rel))
3956db08 2511 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2512 bfd_get_reloc_size (rel),
3956db08 2513 size);
91d6fa6a 2514 else if (pcrel && !rel->pc_relative)
3956db08 2515 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2516 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2517 && !sign)
91d6fa6a 2518 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2519 && sign > 0))
3956db08
JB		 2520 as_bad (_("relocated field and relocation type differ in signedness"));
2521 else
2522 return other;
2523 return NO_RELOC;
2524 }
252b5132
RH		 2525
2526 if (pcrel)
2527 {
3e73aa7c 2528 if (!sign)
3956db08 2529 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2530 switch (size)
2531 {
2532 case 1: return BFD_RELOC_8_PCREL;
2533 case 2: return BFD_RELOC_16_PCREL;
2534 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2535 case 8: return BFD_RELOC_64_PCREL;
252b5132 2536 }
3956db08 2537 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2538 }
2539 else
2540 {
3956db08 2541 if (sign > 0)
e5cb08ac 2542 switch (size)
3e73aa7c
JH		 2543 {
2544 case 4: return BFD_RELOC_X86_64_32S;
2545 }
2546 else
2547 switch (size)
2548 {
2549 case 1: return BFD_RELOC_8;
2550 case 2: return BFD_RELOC_16;
2551 case 4: return BFD_RELOC_32;
2552 case 8: return BFD_RELOC_64;
2553 }
3956db08
JB		 2554 as_bad (_("cannot do %s %u byte relocation"),
2555 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2556 }
2557
0cc9e1d3 2558 return NO_RELOC;
252b5132
RH		 2559}
2560
47926f60
KH		 2561/* Here we decide which fixups can be adjusted to make them relative to
2562 the beginning of the section instead of the symbol. Basically we need
2563 to make sure that the dynamic relocations are done correctly, so in
2564 some cases we force the original symbol to be used. */
2565
252b5132 2566int
e3bb37b5 2567tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2568{
6d249963 2569#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2570 if (!IS_ELF)
31312f95
AM		 2571 return 1;
2572
a161fe53
AM		 2573 /* Don't adjust pc-relative references to merge sections in 64-bit
2574 mode. */
2575 if (use_rela_relocations
2576 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2577 && fixP->fx_pcrel)
252b5132 2578 return 0;
31312f95 2579
8d01d9a9
AJ		 2580 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2581 and changed later by validate_fix. */
2582 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2583 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2584 return 0;
2585
ce8a8b2f 2586 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2587 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2588 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2589 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2590 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2591 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2592 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2593 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2594 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2595 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2596 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2597 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2598 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2599 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2600 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2601 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2602 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2603 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2604 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2605 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2606 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2607 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2608 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2609 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2610 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2611 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2612 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2613 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2614 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2615 return 0;
31312f95 2616#endif
252b5132
RH		 2617 return 1;
2618}
252b5132 2619
b4cac588 2620static int
e3bb37b5 2621intel_float_operand (const char *mnemonic)
252b5132 2622{
9306ca4a
JB		 2623 /* Note that the value returned is meaningful only for opcodes with (memory)
2624 operands, hence the code here is free to improperly handle opcodes that
2625 have no operands (for better performance and smaller code). */
2626
2627 if (mnemonic[0] != 'f')
2628 return 0; /* non-math */
2629
2630 switch (mnemonic[1])
2631 {
2632 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2633 the fs segment override prefix not currently handled because no
2634 call path can make opcodes without operands get here */
2635 case 'i':
2636 return 2 /* integer op */;
2637 case 'l':
2638 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2639 return 3; /* fldcw/fldenv */
2640 break;
2641 case 'n':
2642 if (mnemonic[2] != 'o' /* fnop */)
2643 return 3; /* non-waiting control op */
2644 break;
2645 case 'r':
2646 if (mnemonic[2] == 's')
2647 return 3; /* frstor/frstpm */
2648 break;
2649 case 's':
2650 if (mnemonic[2] == 'a')
2651 return 3; /* fsave */
2652 if (mnemonic[2] == 't')
2653 {
2654 switch (mnemonic[3])
2655 {
2656 case 'c': /* fstcw */
2657 case 'd': /* fstdw */
2658 case 'e': /* fstenv */
2659 case 's': /* fsts[gw] */
2660 return 3;
2661 }
2662 }
2663 break;
2664 case 'x':
2665 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2666 return 0; /* fxsave/fxrstor are not really math ops */
2667 break;
2668 }
252b5132 2669
9306ca4a 2670 return 1;
252b5132
RH		 2671}
2672
c0f3af97
L		 2673/* Build the VEX prefix. */
2674
2675static void
d3ce72d0 2676build_vex_prefix (const insn_template *t)
c0f3af97
L		 2677{
2678 unsigned int register_specifier;
2679 unsigned int implied_prefix;
2680 unsigned int vector_length;
2681
2682 /* Check register specifier. */
2683 if (i.vex.register_specifier)
2684 {
2685 register_specifier = i.vex.register_specifier->reg_num;
2686 if ((i.vex.register_specifier->reg_flags & RegRex))
2687 register_specifier += 8;
2688 register_specifier = ~register_specifier & 0xf;
2689 }
2690 else
2691 register_specifier = 0xf;
2692
fa99fab2
L		 2693 /* Use 2-byte VEX prefix by swappping destination and source
2694 operand. */
2695 if (!i.swap_operand
2696 && i.operands == i.reg_operands
7f399153 2697 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2698 && i.tm.opcode_modifier.s
2699 && i.rex == REX_B)
2700 {
2701 unsigned int xchg = i.operands - 1;
2702 union i386_op temp_op;
2703 i386_operand_type temp_type;
2704
2705 temp_type = i.types[xchg];
2706 i.types[xchg] = i.types[0];
2707 i.types[0] = temp_type;
2708 temp_op = i.op[xchg];
2709 i.op[xchg] = i.op[0];
2710 i.op[0] = temp_op;
2711
9c2799c2 2712 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2713
2714 i.rex = REX_R;
2715 xchg = i.rm.regmem;
2716 i.rm.regmem = i.rm.reg;
2717 i.rm.reg = xchg;
2718
2719 /* Use the next insn. */
2720 i.tm = t[1];
2721 }
2722
539f890d
L		 2723 if (i.tm.opcode_modifier.vex == VEXScalar)
2724 vector_length = avxscalar;
2725 else
2726 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2727
2728 switch ((i.tm.base_opcode >> 8) & 0xff)
2729 {
2730 case 0:
2731 implied_prefix = 0;
2732 break;
2733 case DATA_PREFIX_OPCODE:
2734 implied_prefix = 1;
2735 break;
2736 case REPE_PREFIX_OPCODE:
2737 implied_prefix = 2;
2738 break;
2739 case REPNE_PREFIX_OPCODE:
2740 implied_prefix = 3;
2741 break;
2742 default:
2743 abort ();
2744 }
2745
2746 /* Use 2-byte VEX prefix if possible. */
7f399153 2747 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2748 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2749 {
2750 /* 2-byte VEX prefix. */
2751 unsigned int r;
2752
2753 i.vex.length = 2;
2754 i.vex.bytes[0] = 0xc5;
2755
2756 /* Check the REX.R bit. */
2757 r = (i.rex & REX_R) ? 0 : 1;
2758 i.vex.bytes[1] = (r << 7
2759 | register_specifier << 3
2760 | vector_length << 2
2761 | implied_prefix);
2762 }
2763 else
2764 {
2765 /* 3-byte VEX prefix. */
2766 unsigned int m, w;
2767
f88c9eb0 2768 i.vex.length = 3;
f88c9eb0 2769
7f399153 2770 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2771 {
7f399153
L		 2772 case VEX0F:
2773 m = 0x1;
80de6e00 2774 i.vex.bytes[0] = 0xc4;
7f399153
L		 2775 break;
2776 case VEX0F38:
2777 m = 0x2;
80de6e00 2778 i.vex.bytes[0] = 0xc4;
7f399153
L		 2779 break;
2780 case VEX0F3A:
2781 m = 0x3;
80de6e00 2782 i.vex.bytes[0] = 0xc4;
7f399153
L		 2783 break;
2784 case XOP08:
5dd85c99
SP		 2785 m = 0x8;
2786 i.vex.bytes[0] = 0x8f;
7f399153
L		 2787 break;
2788 case XOP09:
f88c9eb0
SP		 2789 m = 0x9;
2790 i.vex.bytes[0] = 0x8f;
7f399153
L		 2791 break;
2792 case XOP0A:
f88c9eb0
SP		 2793 m = 0xa;
2794 i.vex.bytes[0] = 0x8f;
7f399153
L		 2795 break;
2796 default:
2797 abort ();
f88c9eb0 2798 }
c0f3af97 2799
c0f3af97
L		 2800 /* The high 3 bits of the second VEX byte are 1's compliment
2801 of RXB bits from REX. */
2802 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2803
2804 /* Check the REX.W bit. */
2805 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2806 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2807 {
2808 if (w)
2809 abort ();
2810
1ef99a7b 2811 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2812 w = 1;
2813 }
2814
2815 i.vex.bytes[2] = (w << 7
2816 | register_specifier << 3
2817 | vector_length << 2
2818 | implied_prefix);
2819 }
2820}
2821
65da13b5
L		 2822static void
2823process_immext (void)
2824{
2825 expressionS *exp;
2826
2827 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2828 {
1fed0ba1
L		 2829 /* SSE3 Instructions have the fixed operands with an opcode
2830 suffix which is coded in the same place as an 8-bit immediate
2831 field would be. Here we check those operands and remove them
2832 afterwards. */
65da13b5
L		 2833 unsigned int x;
2834
2835 for (x = 0; x < i.operands; x++)
2836 if (i.op[x].regs->reg_num != x)
2837 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2838 register_prefix, i.op[x].regs->reg_name, x + 1,
2839 i.tm.name);
2840
2841 i.operands = 0;
65da13b5
L		 2842 }
2843
c0f3af97 2844 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2845 which is coded in the same place as an 8-bit immediate field
2846 would be. Here we fake an 8-bit immediate operand from the
2847 opcode suffix stored in tm.extension_opcode.
2848
c1e679ec 2849 AVX instructions also use this encoding, for some of
c0f3af97 2850 3 argument instructions. */
65da13b5 2851
9c2799c2 2852 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2853 && (i.operands <= 2
2854 || (i.tm.opcode_modifier.vex
2855 && i.operands <= 4)));
65da13b5
L		 2856
2857 exp = &im_expressions[i.imm_operands++];
2858 i.op[i.operands].imms = exp;
2859 i.types[i.operands] = imm8;
2860 i.operands++;
2861 exp->X_op = O_constant;
2862 exp->X_add_number = i.tm.extension_opcode;
2863 i.tm.extension_opcode = None;
2864}
2865
252b5132
RH		 2866/* This is the guts of the machine-dependent assembler. LINE points to a
2867 machine dependent instruction. This function is supposed to emit
2868 the frags/bytes it assembles to. */
2869
2870void
65da13b5 2871md_assemble (char *line)
252b5132 2872{
40fb9820 2873 unsigned int j;
252b5132 2874 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2875 const insn_template *t;
252b5132 2876
47926f60 2877 /* Initialize globals. */
252b5132
RH		 2878 memset (&i, '\0', sizeof (i));
2879 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2880 i.reloc[j] = NO_RELOC;
252b5132
RH		 2881 memset (disp_expressions, '\0', sizeof (disp_expressions));
2882 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2883 save_stack_p = save_stack;
252b5132
RH		 2884
2885 /* First parse an instruction mnemonic & call i386_operand for the operands.
2886 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2887 start of a (possibly prefixed) mnemonic. */
252b5132 2888
29b0f896
AM		 2889 line = parse_insn (line, mnemonic);
2890 if (line == NULL)
2891 return;
252b5132 2892
29b0f896 2893 line = parse_operands (line, mnemonic);
ee86248c 2894 this_operand = -1;
29b0f896
AM		 2895 if (line == NULL)
2896 return;
252b5132 2897
29b0f896
AM		 2898 /* Now we've parsed the mnemonic into a set of templates, and have the
2899 operands at hand. */
2900
2901 /* All intel opcodes have reversed operands except for "bound" and
2902 "enter". We also don't reverse intersegment "jmp" and "call"
2903 instructions with 2 immediate operands so that the immediate segment
050dfa73 2904 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2905 if (intel_syntax
2906 && i.operands > 1
29b0f896 2907 && (strcmp (mnemonic, "bound") != 0)
30123838 2908 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2909 && !(operand_type_check (i.types[0], imm)
2910 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2911 swap_operands ();
2912
ec56d5c0
JB		 2913 /* The order of the immediates should be reversed
2914 for 2 immediates extrq and insertq instructions */
2915 if (i.imm_operands == 2
2916 && (strcmp (mnemonic, "extrq") == 0
2917 || strcmp (mnemonic, "insertq") == 0))
2918 swap_2_operands (0, 1);
2919
29b0f896
AM		 2920 if (i.imm_operands)
2921 optimize_imm ();
2922
b300c311
L		 2923 /* Don't optimize displacement for movabs since it only takes 64bit
2924 displacement. */
2925 if (i.disp_operands
2926 && (flag_code != CODE_64BIT
2927 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2928 optimize_disp ();
2929
2930 /* Next, we find a template that matches the given insn,
2931 making sure the overlap of the given operands types is consistent
2932 with the template operand types. */
252b5132 2933
fa99fab2 2934 if (!(t = match_template ()))
29b0f896 2935 return;
252b5132 2936
daf50ae7 2937 if (sse_check != sse_check_none
81f8a913 2938 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2939 && (i.tm.cpu_flags.bitfield.cpusse
2940 || i.tm.cpu_flags.bitfield.cpusse2
2941 || i.tm.cpu_flags.bitfield.cpusse3
2942 || i.tm.cpu_flags.bitfield.cpussse3
2943 || i.tm.cpu_flags.bitfield.cpusse4_1
2944 || i.tm.cpu_flags.bitfield.cpusse4_2))
2945 {
2946 (sse_check == sse_check_warning
2947 ? as_warn
2948 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2949 }
2950
321fd21e
L		 2951 /* Zap movzx and movsx suffix. The suffix has been set from
2952 "word ptr" or "byte ptr" on the source operand in Intel syntax
2953 or extracted from mnemonic in AT&T syntax. But we'll use
2954 the destination register to choose the suffix for encoding. */
2955 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2956 {
321fd21e
L		 2957 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2958 there is no suffix, the default will be byte extension. */
2959 if (i.reg_operands != 2
2960 && !i.suffix
7ab9ffdd 2961 && intel_syntax)
321fd21e
L		 2962 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2963
2964 i.suffix = 0;
cd61ebfe 2965 }
24eab124 2966
40fb9820 2967 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2968 if (!add_prefix (FWAIT_OPCODE))
2969 return;
252b5132 2970
c1ba0266
L		 2971 /* Check for lock without a lockable instruction. Destination operand
2972 must be memory unless it is xchg (0x86). */
c32fa91d
L		 2973 if (i.prefix[LOCK_PREFIX]
2974 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 2975 || i.mem_operands == 0
2976 || (i.tm.base_opcode != 0x86
2977 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 2978 {
2979 as_bad (_("expecting lockable instruction after `lock'"));
2980 return;
2981 }
2982
29b0f896 2983 /* Check string instruction segment overrides. */
40fb9820 2984 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2985 {
2986 if (!check_string ())
5dd0794d 2987 return;
fc0763e6 2988 i.disp_operands = 0;
29b0f896 2989 }
5dd0794d 2990
29b0f896
AM		 2991 if (!process_suffix ())
2992 return;
e413e4e9 2993
bc0844ae
L		 2994 /* Update operand types. */
2995 for (j = 0; j < i.operands; j++)
2996 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2997
29b0f896
AM		 2998 /* Make still unresolved immediate matches conform to size of immediate
2999 given in i.suffix. */
3000 if (!finalize_imm ())
3001 return;
252b5132 3002
40fb9820 3003 if (i.types[0].bitfield.imm1)
29b0f896 3004 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3005
9afe6eb8
L		 3006 /* We only need to check those implicit registers for instructions
3007 with 3 operands or less. */
3008 if (i.operands <= 3)
3009 for (j = 0; j < i.operands; j++)
3010 if (i.types[j].bitfield.inoutportreg
3011 || i.types[j].bitfield.shiftcount
3012 || i.types[j].bitfield.acc
3013 || i.types[j].bitfield.floatacc)
3014 i.reg_operands--;
40fb9820 3015
c0f3af97
L		 3016 /* ImmExt should be processed after SSE2AVX. */
3017 if (!i.tm.opcode_modifier.sse2avx
3018 && i.tm.opcode_modifier.immext)
65da13b5 3019 process_immext ();
252b5132 3020
29b0f896
AM		 3021 /* For insns with operands there are more diddles to do to the opcode. */
3022 if (i.operands)
3023 {
3024 if (!process_operands ())
3025 return;
3026 }
40fb9820 3027 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3028 {
3029 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3030 as_warn (_("translating to `%sp'"), i.tm.name);
3031 }
252b5132 3032
c0f3af97 3033 if (i.tm.opcode_modifier.vex)
fa99fab2 3034 build_vex_prefix (t);
c0f3af97 3035
5dd85c99
SP		 3036 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3037 instructions may define INT_OPCODE as well, so avoid this corner
3038 case for those instructions that use MODRM. */
3039 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3040 && !i.tm.opcode_modifier.modrm
3041 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3042 {
3043 i.tm.base_opcode = INT3_OPCODE;
3044 i.imm_operands = 0;
3045 }
252b5132 3046
40fb9820
L		 3047 if ((i.tm.opcode_modifier.jump
3048 || i.tm.opcode_modifier.jumpbyte
3049 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3050 && i.op[0].disps->X_op == O_constant)
3051 {
3052 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3053 the absolute address given by the constant. Since ix86 jumps and
3054 calls are pc relative, we need to generate a reloc. */
3055 i.op[0].disps->X_add_symbol = &abs_symbol;
3056 i.op[0].disps->X_op = O_symbol;
3057 }
252b5132 3058
40fb9820 3059 if (i.tm.opcode_modifier.rex64)
161a04f6 3060 i.rex |= REX_W;
252b5132 3061
29b0f896
AM		 3062 /* For 8 bit registers we need an empty rex prefix. Also if the
3063 instruction already has a prefix, we need to convert old
3064 registers to new ones. */
773f551c 3065
40fb9820 3066 if ((i.types[0].bitfield.reg8
29b0f896 3067 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3068 || (i.types[1].bitfield.reg8
29b0f896 3069 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3070 || ((i.types[0].bitfield.reg8
3071 || i.types[1].bitfield.reg8)
29b0f896
AM		 3072 && i.rex != 0))
3073 {
3074 int x;
726c5dcd 3075
29b0f896
AM		 3076 i.rex |= REX_OPCODE;
3077 for (x = 0; x < 2; x++)
3078 {
3079 /* Look for 8 bit operand that uses old registers. */
40fb9820 3080 if (i.types[x].bitfield.reg8
29b0f896 3081 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3082 {
29b0f896
AM		 3083 /* In case it is "hi" register, give up. */
3084 if (i.op[x].regs->reg_num > 3)
a540244d 3085 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3086 "instruction requiring REX prefix."),
a540244d 3087 register_prefix, i.op[x].regs->reg_name);
773f551c 3088
29b0f896
AM		 3089 /* Otherwise it is equivalent to the extended register.
3090 Since the encoding doesn't change this is merely
3091 cosmetic cleanup for debug output. */
3092
3093 i.op[x].regs = i.op[x].regs + 8;
773f551c 3094 }
29b0f896
AM		 3095 }
3096 }
773f551c 3097
7ab9ffdd 3098 if (i.rex != 0)
29b0f896
AM		 3099 add_prefix (REX_OPCODE | i.rex);
3100
3101 /* We are ready to output the insn. */
3102 output_insn ();
3103}
3104
3105static char *
e3bb37b5 3106parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3107{
3108 char *l = line;
3109 char *token_start = l;
3110 char *mnem_p;
5c6af06e 3111 int supported;
d3ce72d0 3112 const insn_template *t;
b6169b20 3113 char *dot_p = NULL;
29b0f896
AM		 3114
3115 /* Non-zero if we found a prefix only acceptable with string insns. */
3116 const char *expecting_string_instruction = NULL;
45288df1 3117
29b0f896
AM		 3118 while (1)
3119 {
3120 mnem_p = mnemonic;
3121 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3122 {
b6169b20
L		 3123 if (*mnem_p == '.')
3124 dot_p = mnem_p;
29b0f896
AM		 3125 mnem_p++;
3126 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3127 {
29b0f896
AM		 3128 as_bad (_("no such instruction: `%s'"), token_start);
3129 return NULL;
3130 }
3131 l++;
3132 }
3133 if (!is_space_char (*l)
3134 && *l != END_OF_INSN
e44823cf
JB		 3135 && (intel_syntax
3136 || (*l != PREFIX_SEPARATOR
3137 && *l != ',')))
29b0f896
AM		 3138 {
3139 as_bad (_("invalid character %s in mnemonic"),
3140 output_invalid (*l));
3141 return NULL;
3142 }
3143 if (token_start == l)
3144 {
e44823cf 3145 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3146 as_bad (_("expecting prefix; got nothing"));
3147 else
3148 as_bad (_("expecting mnemonic; got nothing"));
3149 return NULL;
3150 }
45288df1 3151
29b0f896 3152 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3153 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3154
29b0f896
AM		 3155 if (*l != END_OF_INSN
3156 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3157 && current_templates
40fb9820 3158 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3159 {
c6fb90c8 3160 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3161 {
3162 as_bad ((flag_code != CODE_64BIT
3163 ? _("`%s' is only supported in 64-bit mode")
3164 : _("`%s' is not supported in 64-bit mode")),
3165 current_templates->start->name);
3166 return NULL;
3167 }
29b0f896
AM		 3168 /* If we are in 16-bit mode, do not allow addr16 or data16.
3169 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3170 if ((current_templates->start->opcode_modifier.size16
3171 || current_templates->start->opcode_modifier.size32)
29b0f896 3172 && flag_code != CODE_64BIT
40fb9820 3173 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3174 ^ (flag_code == CODE_16BIT)))
3175 {
3176 as_bad (_("redundant %s prefix"),
3177 current_templates->start->name);
3178 return NULL;
45288df1 3179 }
29b0f896
AM		 3180 /* Add prefix, checking for repeated prefixes. */
3181 switch (add_prefix (current_templates->start->base_opcode))
3182 {
c32fa91d 3183 case PREFIX_EXIST:
29b0f896 3184 return NULL;
c32fa91d 3185 case PREFIX_REP:
29b0f896
AM		 3186 expecting_string_instruction = current_templates->start->name;
3187 break;
c32fa91d
L		 3188 default:
3189 break;
29b0f896
AM		 3190 }
3191 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3192 token_start = ++l;
3193 }
3194 else
3195 break;
3196 }
45288df1 3197
30a55f88 3198 if (!current_templates)
b6169b20 3199 {
30a55f88
L		 3200 /* Check if we should swap operand in encoding. */
3201 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3202 i.swap_operand = 1;
3203 else
3204 goto check_suffix;
3205 mnem_p = dot_p;
3206 *dot_p = '\0';
d3ce72d0 3207 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3208 }
3209
29b0f896
AM		 3210 if (!current_templates)
3211 {
b6169b20 3212check_suffix:
29b0f896
AM		 3213 /* See if we can get a match by trimming off a suffix. */
3214 switch (mnem_p[-1])
3215 {
3216 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3217 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3218 i.suffix = SHORT_MNEM_SUFFIX;
3219 else
29b0f896
AM		 3220 case BYTE_MNEM_SUFFIX:
3221 case QWORD_MNEM_SUFFIX:
3222 i.suffix = mnem_p[-1];
3223 mnem_p[-1] = '\0';
d3ce72d0
NC		 3224 current_templates = (const templates *) hash_find (op_hash,
3225 mnemonic);
29b0f896
AM		 3226 break;
3227 case SHORT_MNEM_SUFFIX:
3228 case LONG_MNEM_SUFFIX:
3229 if (!intel_syntax)
3230 {
3231 i.suffix = mnem_p[-1];
3232 mnem_p[-1] = '\0';
d3ce72d0
NC		 3233 current_templates = (const templates *) hash_find (op_hash,
3234 mnemonic);
29b0f896
AM		 3235 }
3236 break;
252b5132 3237
29b0f896
AM		 3238 /* Intel Syntax. */
3239 case 'd':
3240 if (intel_syntax)
3241 {
9306ca4a 3242 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3243 i.suffix = SHORT_MNEM_SUFFIX;
3244 else
3245 i.suffix = LONG_MNEM_SUFFIX;
3246 mnem_p[-1] = '\0';
d3ce72d0
NC		 3247 current_templates = (const templates *) hash_find (op_hash,
3248 mnemonic);
29b0f896
AM		 3249 }
3250 break;
3251 }
3252 if (!current_templates)
3253 {
3254 as_bad (_("no such instruction: `%s'"), token_start);
3255 return NULL;
3256 }
3257 }
252b5132 3258
40fb9820
L		 3259 if (current_templates->start->opcode_modifier.jump
3260 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3261 {
3262 /* Check for a branch hint. We allow ",pt" and ",pn" for
3263 predict taken and predict not taken respectively.
3264 I'm not sure that branch hints actually do anything on loop
3265 and jcxz insns (JumpByte) for current Pentium4 chips. They
3266 may work in the future and it doesn't hurt to accept them
3267 now. */
3268 if (l[0] == ',' && l[1] == 'p')
3269 {
3270 if (l[2] == 't')
3271 {
3272 if (!add_prefix (DS_PREFIX_OPCODE))
3273 return NULL;
3274 l += 3;
3275 }
3276 else if (l[2] == 'n')
3277 {
3278 if (!add_prefix (CS_PREFIX_OPCODE))
3279 return NULL;
3280 l += 3;
3281 }
3282 }
3283 }
3284 /* Any other comma loses. */
3285 if (*l == ',')
3286 {
3287 as_bad (_("invalid character %s in mnemonic"),
3288 output_invalid (*l));
3289 return NULL;
3290 }
252b5132 3291
29b0f896 3292 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3293 supported = 0;
3294 for (t = current_templates->start; t < current_templates->end; ++t)
3295 {
c0f3af97
L		 3296 supported |= cpu_flags_match (t);
3297 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3298 goto skip;
5c6af06e 3299 }
3629bb00 3300
c0f3af97 3301 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3302 {
3303 as_bad (flag_code == CODE_64BIT
3304 ? _("`%s' is not supported in 64-bit mode")
3305 : _("`%s' is only supported in 64-bit mode"),
3306 current_templates->start->name);
3307 return NULL;
3308 }
c0f3af97 3309 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3310 {
3629bb00 3311 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3312 current_templates->start->name,
41aacd83 3313 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3314 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3315 return NULL;
29b0f896 3316 }
3629bb00
L		 3317
3318skip:
3319 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3320 && (flag_code != CODE_16BIT))
29b0f896
AM		 3321 {
3322 as_warn (_("use .code16 to ensure correct addressing mode"));
3323 }
252b5132 3324
29b0f896 3325 /* Check for rep/repne without a string instruction. */
f41bbced 3326 if (expecting_string_instruction)
29b0f896 3327 {
f41bbced
JB		 3328 static templates override;
3329
3330 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3331 if (t->opcode_modifier.isstring)
f41bbced
JB		 3332 break;
3333 if (t >= current_templates->end)
3334 {
3335 as_bad (_("expecting string instruction after `%s'"),
64e74474 3336 expecting_string_instruction);
f41bbced
JB		 3337 return NULL;
3338 }
3339 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3340 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3341 break;
3342 override.end = t;
3343 current_templates = &override;
29b0f896 3344 }
252b5132 3345
29b0f896
AM		 3346 return l;
3347}
252b5132 3348
29b0f896 3349static char *
e3bb37b5 3350parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3351{
3352 char *token_start;
3138f287 3353
29b0f896
AM		 3354 /* 1 if operand is pending after ','. */
3355 unsigned int expecting_operand = 0;
252b5132 3356
29b0f896
AM		 3357 /* Non-zero if operand parens not balanced. */
3358 unsigned int paren_not_balanced;
3359
3360 while (*l != END_OF_INSN)
3361 {
3362 /* Skip optional white space before operand. */
3363 if (is_space_char (*l))
3364 ++l;
3365 if (!is_operand_char (*l) && *l != END_OF_INSN)
3366 {
3367 as_bad (_("invalid character %s before operand %d"),
3368 output_invalid (*l),
3369 i.operands + 1);
3370 return NULL;
3371 }
3372 token_start = l; /* after white space */
3373 paren_not_balanced = 0;
3374 while (paren_not_balanced || *l != ',')
3375 {
3376 if (*l == END_OF_INSN)
3377 {
3378 if (paren_not_balanced)
3379 {
3380 if (!intel_syntax)
3381 as_bad (_("unbalanced parenthesis in operand %d."),
3382 i.operands + 1);
3383 else
3384 as_bad (_("unbalanced brackets in operand %d."),
3385 i.operands + 1);
3386 return NULL;
3387 }
3388 else
3389 break; /* we are done */
3390 }
3391 else if (!is_operand_char (*l) && !is_space_char (*l))
3392 {
3393 as_bad (_("invalid character %s in operand %d"),
3394 output_invalid (*l),
3395 i.operands + 1);
3396 return NULL;
3397 }
3398 if (!intel_syntax)
3399 {
3400 if (*l == '(')
3401 ++paren_not_balanced;
3402 if (*l == ')')
3403 --paren_not_balanced;
3404 }
3405 else
3406 {
3407 if (*l == '[')
3408 ++paren_not_balanced;
3409 if (*l == ']')
3410 --paren_not_balanced;
3411 }
3412 l++;
3413 }
3414 if (l != token_start)
3415 { /* Yes, we've read in another operand. */
3416 unsigned int operand_ok;
3417 this_operand = i.operands++;
7d5e4556 3418 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3419 if (i.operands > MAX_OPERANDS)
3420 {
3421 as_bad (_("spurious operands; (%d operands/instruction max)"),
3422 MAX_OPERANDS);
3423 return NULL;
3424 }
3425 /* Now parse operand adding info to 'i' as we go along. */
3426 END_STRING_AND_SAVE (l);
3427
3428 if (intel_syntax)
3429 operand_ok =
3430 i386_intel_operand (token_start,
3431 intel_float_operand (mnemonic));
3432 else
a7619375 3433 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3434
3435 RESTORE_END_STRING (l);
3436 if (!operand_ok)
3437 return NULL;
3438 }
3439 else
3440 {
3441 if (expecting_operand)
3442 {
3443 expecting_operand_after_comma:
3444 as_bad (_("expecting operand after ','; got nothing"));
3445 return NULL;
3446 }
3447 if (*l == ',')
3448 {
3449 as_bad (_("expecting operand before ','; got nothing"));
3450 return NULL;
3451 }
3452 }
7f3f1ea2 3453
29b0f896
AM		 3454 /* Now *l must be either ',' or END_OF_INSN. */
3455 if (*l == ',')
3456 {
3457 if (*++l == END_OF_INSN)
3458 {
3459 /* Just skip it, if it's \n complain. */
3460 goto expecting_operand_after_comma;
3461 }
3462 expecting_operand = 1;
3463 }
3464 }
3465 return l;
3466}
7f3f1ea2 3467
050dfa73 3468static void
4d456e3d 3469swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3470{
3471 union i386_op temp_op;
40fb9820 3472 i386_operand_type temp_type;
050dfa73 3473 enum bfd_reloc_code_real temp_reloc;
4eed87de 3474
050dfa73
MM		 3475 temp_type = i.types[xchg2];
3476 i.types[xchg2] = i.types[xchg1];
3477 i.types[xchg1] = temp_type;
3478 temp_op = i.op[xchg2];
3479 i.op[xchg2] = i.op[xchg1];
3480 i.op[xchg1] = temp_op;
3481 temp_reloc = i.reloc[xchg2];
3482 i.reloc[xchg2] = i.reloc[xchg1];
3483 i.reloc[xchg1] = temp_reloc;
3484}
3485
29b0f896 3486static void
e3bb37b5 3487swap_operands (void)
29b0f896 3488{
b7c61d9a 3489 switch (i.operands)
050dfa73 3490 {
c0f3af97 3491 case 5:
b7c61d9a 3492 case 4:
4d456e3d 3493 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3494 case 3:
3495 case 2:
4d456e3d 3496 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3497 break;
3498 default:
3499 abort ();
29b0f896 3500 }
29b0f896
AM		 3501
3502 if (i.mem_operands == 2)
3503 {
3504 const seg_entry *temp_seg;
3505 temp_seg = i.seg[0];
3506 i.seg[0] = i.seg[1];
3507 i.seg[1] = temp_seg;
3508 }
3509}
252b5132 3510
29b0f896
AM		 3511/* Try to ensure constant immediates are represented in the smallest
3512 opcode possible. */
3513static void
e3bb37b5 3514optimize_imm (void)
29b0f896
AM		 3515{
3516 char guess_suffix = 0;
3517 int op;
252b5132 3518
29b0f896
AM		 3519 if (i.suffix)
3520 guess_suffix = i.suffix;
3521 else if (i.reg_operands)
3522 {
3523 /* Figure out a suffix from the last register operand specified.
3524 We can't do this properly yet, ie. excluding InOutPortReg,
3525 but the following works for instructions with immediates.
3526 In any case, we can't set i.suffix yet. */
3527 for (op = i.operands; --op >= 0;)
40fb9820 3528 if (i.types[op].bitfield.reg8)
7ab9ffdd 3529 {
40fb9820
L		 3530 guess_suffix = BYTE_MNEM_SUFFIX;
3531 break;
3532 }
3533 else if (i.types[op].bitfield.reg16)
252b5132 3534 {
40fb9820
L		 3535 guess_suffix = WORD_MNEM_SUFFIX;
3536 break;
3537 }
3538 else if (i.types[op].bitfield.reg32)
3539 {
3540 guess_suffix = LONG_MNEM_SUFFIX;
3541 break;
3542 }
3543 else if (i.types[op].bitfield.reg64)
3544 {
3545 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3546 break;
252b5132 3547 }
29b0f896
AM		 3548 }
3549 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3550 guess_suffix = WORD_MNEM_SUFFIX;
3551
3552 for (op = i.operands; --op >= 0;)
40fb9820 3553 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3554 {
3555 switch (i.op[op].imms->X_op)
252b5132 3556 {
29b0f896
AM		 3557 case O_constant:
3558 /* If a suffix is given, this operand may be shortened. */
3559 switch (guess_suffix)
252b5132 3560 {
29b0f896 3561 case LONG_MNEM_SUFFIX:
40fb9820
L		 3562 i.types[op].bitfield.imm32 = 1;
3563 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3564 break;
3565 case WORD_MNEM_SUFFIX:
40fb9820
L		 3566 i.types[op].bitfield.imm16 = 1;
3567 i.types[op].bitfield.imm32 = 1;
3568 i.types[op].bitfield.imm32s = 1;
3569 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3570 break;
3571 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3572 i.types[op].bitfield.imm8 = 1;
3573 i.types[op].bitfield.imm8s = 1;
3574 i.types[op].bitfield.imm16 = 1;
3575 i.types[op].bitfield.imm32 = 1;
3576 i.types[op].bitfield.imm32s = 1;
3577 i.types[op].bitfield.imm64 = 1;
29b0f896 3578 break;
252b5132 3579 }
252b5132 3580
29b0f896
AM		 3581 /* If this operand is at most 16 bits, convert it
3582 to a signed 16 bit number before trying to see
3583 whether it will fit in an even smaller size.
3584 This allows a 16-bit operand such as $0xffe0 to
3585 be recognised as within Imm8S range. */
40fb9820 3586 if ((i.types[op].bitfield.imm16)
29b0f896 3587 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3588 {
29b0f896
AM		 3589 i.op[op].imms->X_add_number =
3590 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3591 }
40fb9820 3592 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3593 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3594 == 0))
3595 {
3596 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3597 ^ ((offsetT) 1 << 31))
3598 - ((offsetT) 1 << 31));
3599 }
40fb9820 3600 i.types[op]
c6fb90c8
L		 3601 = operand_type_or (i.types[op],
3602 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3603
29b0f896
AM		 3604 /* We must avoid matching of Imm32 templates when 64bit
3605 only immediate is available. */
3606 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3607 i.types[op].bitfield.imm32 = 0;
29b0f896 3608 break;
252b5132 3609
29b0f896
AM		 3610 case O_absent:
3611 case O_register:
3612 abort ();
3613
3614 /* Symbols and expressions. */
3615 default:
9cd96992
JB		 3616 /* Convert symbolic operand to proper sizes for matching, but don't
3617 prevent matching a set of insns that only supports sizes other
3618 than those matching the insn suffix. */
3619 {
40fb9820 3620 i386_operand_type mask, allowed;
d3ce72d0 3621 const insn_template *t;
9cd96992 3622
0dfbf9d7
L		 3623 operand_type_set (&mask, 0);
3624 operand_type_set (&allowed, 0);
40fb9820 3625
4eed87de
AM		 3626 for (t = current_templates->start;
3627 t < current_templates->end;
3628 ++t)
c6fb90c8
L		 3629 allowed = operand_type_or (allowed,
3630 t->operand_types[op]);
9cd96992
JB		 3631 switch (guess_suffix)
3632 {
3633 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3634 mask.bitfield.imm64 = 1;
3635 mask.bitfield.imm32s = 1;
9cd96992
JB		 3636 break;
3637 case LONG_MNEM_SUFFIX:
40fb9820 3638 mask.bitfield.imm32 = 1;
9cd96992
JB		 3639 break;
3640 case WORD_MNEM_SUFFIX:
40fb9820 3641 mask.bitfield.imm16 = 1;
9cd96992
JB		 3642 break;
3643 case BYTE_MNEM_SUFFIX:
40fb9820 3644 mask.bitfield.imm8 = 1;
9cd96992
JB		 3645 break;
3646 default:
9cd96992
JB		 3647 break;
3648 }
c6fb90c8 3649 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3650 if (!operand_type_all_zero (&allowed))
c6fb90c8 3651 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3652 }
29b0f896 3653 break;
252b5132 3654 }
29b0f896
AM		 3655 }
3656}
47926f60 3657
29b0f896
AM		 3658/* Try to use the smallest displacement type too. */
3659static void
e3bb37b5 3660optimize_disp (void)
29b0f896
AM		 3661{
3662 int op;
3e73aa7c 3663
29b0f896 3664 for (op = i.operands; --op >= 0;)
40fb9820 3665 if (operand_type_check (i.types[op], disp))
252b5132 3666 {
b300c311 3667 if (i.op[op].disps->X_op == O_constant)
252b5132 3668 {
91d6fa6a 3669 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3670
40fb9820 3671 if (i.types[op].bitfield.disp16
91d6fa6a 3672 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3673 {
3674 /* If this operand is at most 16 bits, convert
3675 to a signed 16 bit number and don't use 64bit
3676 displacement. */
91d6fa6a 3677 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3678 i.types[op].bitfield.disp64 = 0;
b300c311 3679 }
40fb9820 3680 if (i.types[op].bitfield.disp32
91d6fa6a 3681 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3682 {
3683 /* If this operand is at most 32 bits, convert
3684 to a signed 32 bit number and don't use 64bit
3685 displacement. */
91d6fa6a
NC		 3686 op_disp &= (((offsetT) 2 << 31) - 1);
3687 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3688 i.types[op].bitfield.disp64 = 0;
b300c311 3689 }
91d6fa6a 3690 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3691 {
40fb9820
L		 3692 i.types[op].bitfield.disp8 = 0;
3693 i.types[op].bitfield.disp16 = 0;
3694 i.types[op].bitfield.disp32 = 0;
3695 i.types[op].bitfield.disp32s = 0;
3696 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3697 i.op[op].disps = 0;
3698 i.disp_operands--;
3699 }
3700 else if (flag_code == CODE_64BIT)
3701 {
91d6fa6a 3702 if (fits_in_signed_long (op_disp))
28a9d8f5 3703 {
40fb9820
L		 3704 i.types[op].bitfield.disp64 = 0;
3705 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3706 }
0e1147d9 3707 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3708 && fits_in_unsigned_long (op_disp))
40fb9820 3709 i.types[op].bitfield.disp32 = 1;
b300c311 3710 }
40fb9820
L		 3711 if ((i.types[op].bitfield.disp32
3712 || i.types[op].bitfield.disp32s
3713 || i.types[op].bitfield.disp16)
91d6fa6a 3714 && fits_in_signed_byte (op_disp))
40fb9820 3715 i.types[op].bitfield.disp8 = 1;
252b5132 3716 }
67a4f2b7
AO		 3717 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3718 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3719 {
3720 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3721 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3722 i.types[op].bitfield.disp8 = 0;
3723 i.types[op].bitfield.disp16 = 0;
3724 i.types[op].bitfield.disp32 = 0;
3725 i.types[op].bitfield.disp32s = 0;
3726 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3727 }
3728 else
b300c311 3729 /* We only support 64bit displacement on constants. */
40fb9820 3730 i.types[op].bitfield.disp64 = 0;
252b5132 3731 }
29b0f896
AM		 3732}
3733
a683cc34
SP		 3734/* Check if operands are valid for the instrucrtion. Update VEX
3735 operand types. */
3736
3737static int
3738VEX_check_operands (const insn_template *t)
3739{
3740 if (!t->opcode_modifier.vex)
3741 return 0;
3742
3743 /* Only check VEX_Imm4, which must be the first operand. */
3744 if (t->operand_types[0].bitfield.vec_imm4)
3745 {
3746 if (i.op[0].imms->X_op != O_constant
3747 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3748 return 1;
3749
3750 /* Turn off Imm8 so that update_imm won't complain. */
3751 i.types[0] = vec_imm4;
3752 }
3753
3754 return 0;
3755}
3756
d3ce72d0 3757static const insn_template *
e3bb37b5 3758match_template (void)
29b0f896
AM		 3759{
3760 /* Points to template once we've found it. */
d3ce72d0 3761 const insn_template *t;
40fb9820 3762 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3763 i386_operand_type overlap4;
29b0f896 3764 unsigned int found_reverse_match;
40fb9820
L		 3765 i386_opcode_modifier suffix_check;
3766 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3767 int addr_prefix_disp;
a5c311ca 3768 unsigned int j;
3629bb00 3769 unsigned int found_cpu_match;
45664ddb 3770 unsigned int check_register;
29b0f896 3771
c0f3af97
L		 3772#if MAX_OPERANDS != 5
3773# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3774#endif
3775
29b0f896 3776 found_reverse_match = 0;
539e75ad 3777 addr_prefix_disp = -1;
40fb9820
L		 3778
3779 memset (&suffix_check, 0, sizeof (suffix_check));
3780 if (i.suffix == BYTE_MNEM_SUFFIX)
3781 suffix_check.no_bsuf = 1;
3782 else if (i.suffix == WORD_MNEM_SUFFIX)
3783 suffix_check.no_wsuf = 1;
3784 else if (i.suffix == SHORT_MNEM_SUFFIX)
3785 suffix_check.no_ssuf = 1;
3786 else if (i.suffix == LONG_MNEM_SUFFIX)
3787 suffix_check.no_lsuf = 1;
3788 else if (i.suffix == QWORD_MNEM_SUFFIX)
3789 suffix_check.no_qsuf = 1;
3790 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3791 suffix_check.no_ldsuf = 1;
29b0f896 3792
45aa61fe 3793 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3794 {
539e75ad
L		 3795 addr_prefix_disp = -1;
3796
29b0f896
AM		 3797 /* Must have right number of operands. */
3798 if (i.operands != t->operands)
3799 continue;
3800
50aecf8c 3801 /* Check processor support. */
c0f3af97
L		 3802 found_cpu_match = (cpu_flags_match (t)
3803 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3804 if (!found_cpu_match)
3805 continue;
3806
e1d4d893
L		 3807 /* Check old gcc support. */
3808 if (!old_gcc && t->opcode_modifier.oldgcc)
3809 continue;
3810
3811 /* Check AT&T mnemonic. */
3812 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3813 continue;
3814
5c07affc
L		 3815 /* Check AT&T syntax Intel syntax. */
3816 if ((intel_syntax && t->opcode_modifier.attsyntax)
3817 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3818 continue;
3819
20592a94 3820 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3821 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3822 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3823 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3824 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3825 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3826 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3827 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3828 continue;
3829
5c07affc 3830 if (!operand_size_match (t))
7d5e4556 3831 continue;
539e75ad 3832
5c07affc
L		 3833 for (j = 0; j < MAX_OPERANDS; j++)
3834 operand_types[j] = t->operand_types[j];
3835
45aa61fe
AM		 3836 /* In general, don't allow 64-bit operands in 32-bit mode. */
3837 if (i.suffix == QWORD_MNEM_SUFFIX
3838 && flag_code != CODE_64BIT
3839 && (intel_syntax
40fb9820 3840 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3841 && !intel_float_operand (t->name))
3842 : intel_float_operand (t->name) != 2)
40fb9820 3843 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3844 && !operand_types[0].bitfield.regxmm
3845 && !operand_types[0].bitfield.regymm)
40fb9820 3846 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3847 && !!operand_types[t->operands > 1].bitfield.regxmm
3848 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3849 && (t->base_opcode != 0x0fc7
3850 || t->extension_opcode != 1 /* cmpxchg8b */))
3851 continue;
3852
192dc9c6
JB		 3853 /* In general, don't allow 32-bit operands on pre-386. */
3854 else if (i.suffix == LONG_MNEM_SUFFIX
3855 && !cpu_arch_flags.bitfield.cpui386
3856 && (intel_syntax
3857 ? (!t->opcode_modifier.ignoresize
3858 && !intel_float_operand (t->name))
3859 : intel_float_operand (t->name) != 2)
3860 && ((!operand_types[0].bitfield.regmmx
3861 && !operand_types[0].bitfield.regxmm)
3862 || (!operand_types[t->operands > 1].bitfield.regmmx
3863 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3864 continue;
3865
29b0f896 3866 /* Do not verify operands when there are none. */
50aecf8c 3867 else
29b0f896 3868 {
c6fb90c8 3869 if (!t->operands)
2dbab7d5
L		 3870 /* We've found a match; break out of loop. */
3871 break;
29b0f896 3872 }
252b5132 3873
539e75ad
L		 3874 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3875 into Disp32/Disp16/Disp32 operand. */
3876 if (i.prefix[ADDR_PREFIX] != 0)
3877 {
40fb9820 3878 /* There should be only one Disp operand. */
539e75ad
L		 3879 switch (flag_code)
3880 {
3881 case CODE_16BIT:
40fb9820
L		 3882 for (j = 0; j < MAX_OPERANDS; j++)
3883 {
3884 if (operand_types[j].bitfield.disp16)
3885 {
3886 addr_prefix_disp = j;
3887 operand_types[j].bitfield.disp32 = 1;
3888 operand_types[j].bitfield.disp16 = 0;
3889 break;
3890 }
3891 }
539e75ad
L		 3892 break;
3893 case CODE_32BIT:
40fb9820
L		 3894 for (j = 0; j < MAX_OPERANDS; j++)
3895 {
3896 if (operand_types[j].bitfield.disp32)
3897 {
3898 addr_prefix_disp = j;
3899 operand_types[j].bitfield.disp32 = 0;
3900 operand_types[j].bitfield.disp16 = 1;
3901 break;
3902 }
3903 }
539e75ad
L		 3904 break;
3905 case CODE_64BIT:
40fb9820
L		 3906 for (j = 0; j < MAX_OPERANDS; j++)
3907 {
3908 if (operand_types[j].bitfield.disp64)
3909 {
3910 addr_prefix_disp = j;
3911 operand_types[j].bitfield.disp64 = 0;
3912 operand_types[j].bitfield.disp32 = 1;
3913 break;
3914 }
3915 }
539e75ad
L		 3916 break;
3917 }
539e75ad
L		 3918 }
3919
45664ddb
L		 3920 /* We check register size only if size of operands can be
3921 encoded the canonical way. */
3922 check_register = t->opcode_modifier.w;
c6fb90c8 3923 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3924 switch (t->operands)
3925 {
3926 case 1:
40fb9820 3927 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3928 continue;
3929 break;
3930 case 2:
8b38ad71
L		 3931 /* xchg %eax, %eax is a special case. It is an aliase for nop
3932 only in 32bit mode and we can use opcode 0x90. In 64bit
3933 mode, we can't use 0x90 for xchg %eax, %eax since it should
3934 zero-extend %eax to %rax. */
3935 if (flag_code == CODE_64BIT
3936 && t->base_opcode == 0x90
0dfbf9d7
L		 3937 && operand_type_equal (&i.types [0], &acc32)
3938 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3939 continue;
b6169b20
L		 3940 if (i.swap_operand)
3941 {
3942 /* If we swap operand in encoding, we either match
3943 the next one or reverse direction of operands. */
3944 if (t->opcode_modifier.s)
3945 continue;
3946 else if (t->opcode_modifier.d)
3947 goto check_reverse;
3948 }
3949
29b0f896 3950 case 3:
fa99fab2
L		 3951 /* If we swap operand in encoding, we match the next one. */
3952 if (i.swap_operand && t->opcode_modifier.s)
3953 continue;
f48ff2ae 3954 case 4:
c0f3af97 3955 case 5:
c6fb90c8 3956 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3957 if (!operand_type_match (overlap0, i.types[0])
3958 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3959 || (check_register
3960 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3961 operand_types[0],
3962 overlap1, i.types[1],
3963 operand_types[1])))
29b0f896
AM		 3964 {
3965 /* Check if other direction is valid ... */
40fb9820 3966 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3967 continue;
3968
b6169b20 3969check_reverse:
29b0f896 3970 /* Try reversing direction of operands. */
c6fb90c8
L		 3971 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3972 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3973 if (!operand_type_match (overlap0, i.types[0])
3974 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3975 || (check_register
3976 && !operand_type_register_match (overlap0,
3977 i.types[0],
3978 operand_types[1],
3979 overlap1,
3980 i.types[1],
3981 operand_types[0])))
29b0f896
AM		 3982 {
3983 /* Does not match either direction. */
3984 continue;
3985 }
3986 /* found_reverse_match holds which of D or FloatDR
3987 we've found. */
40fb9820 3988 if (t->opcode_modifier.d)
8a2ed489 3989 found_reverse_match = Opcode_D;
40fb9820 3990 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3991 found_reverse_match = Opcode_FloatD;
3992 else
3993 found_reverse_match = 0;
40fb9820 3994 if (t->opcode_modifier.floatr)
8a2ed489 3995 found_reverse_match |= Opcode_FloatR;
29b0f896 3996 }
f48ff2ae 3997 else
29b0f896 3998 {
f48ff2ae 3999 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4000 switch (t->operands)
4001 {
c0f3af97
L		 4002 case 5:
4003 overlap4 = operand_type_and (i.types[4],
4004 operand_types[4]);
d1cbb4db 4005 case 4:
c6fb90c8
L		 4006 overlap3 = operand_type_and (i.types[3],
4007 operand_types[3]);
d1cbb4db 4008 case 3:
c6fb90c8
L		 4009 overlap2 = operand_type_and (i.types[2],
4010 operand_types[2]);
d1cbb4db
L		 4011 break;
4012 }
29b0f896 4013
f48ff2ae
L		 4014 switch (t->operands)
4015 {
c0f3af97
L		 4016 case 5:
4017 if (!operand_type_match (overlap4, i.types[4])
4018 || !operand_type_register_match (overlap3,
4019 i.types[3],
4020 operand_types[3],
4021 overlap4,
4022 i.types[4],
4023 operand_types[4]))
4024 continue;
f48ff2ae 4025 case 4:
40fb9820 4026 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4027 || (check_register
4028 && !operand_type_register_match (overlap2,
4029 i.types[2],
4030 operand_types[2],
4031 overlap3,
4032 i.types[3],
4033 operand_types[3])))
f48ff2ae
L		 4034 continue;
4035 case 3:
4036 /* Here we make use of the fact that there are no
4037 reverse match 3 operand instructions, and all 3
4038 operand instructions only need to be checked for
4039 register consistency between operands 2 and 3. */
40fb9820 4040 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4041 || (check_register
4042 && !operand_type_register_match (overlap1,
4043 i.types[1],
4044 operand_types[1],
4045 overlap2,
4046 i.types[2],
4047 operand_types[2])))
f48ff2ae
L		 4048 continue;
4049 break;
4050 }
29b0f896 4051 }
f48ff2ae 4052 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4053 slip through to break. */
4054 }
3629bb00 4055 if (!found_cpu_match)
29b0f896
AM		 4056 {
4057 found_reverse_match = 0;
4058 continue;
4059 }
c0f3af97 4060
a683cc34
SP		 4061 /* Check if VEX operands are valid. */
4062 if (VEX_check_operands (t))
4063 continue;
4064
29b0f896
AM		 4065 /* We've found a match; break out of loop. */
4066 break;
4067 }
4068
4069 if (t == current_templates->end)
4070 {
4071 /* We found no match. */
95f283e8
L		 4072 if (intel_syntax)
4073 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4074 current_templates->start->name);
4075 else
4076 as_bad (_("suffix or operands invalid for `%s'"),
4077 current_templates->start->name);
fa99fab2 4078 return NULL;
29b0f896 4079 }
252b5132 4080
29b0f896
AM		 4081 if (!quiet_warnings)
4082 {
4083 if (!intel_syntax
40fb9820
L		 4084 && (i.types[0].bitfield.jumpabsolute
4085 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4086 {
4087 as_warn (_("indirect %s without `*'"), t->name);
4088 }
4089
40fb9820
L		 4090 if (t->opcode_modifier.isprefix
4091 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4092 {
4093 /* Warn them that a data or address size prefix doesn't
4094 affect assembly of the next line of code. */
4095 as_warn (_("stand-alone `%s' prefix"), t->name);
4096 }
4097 }
4098
4099 /* Copy the template we found. */
4100 i.tm = *t;
539e75ad
L		 4101
4102 if (addr_prefix_disp != -1)
4103 i.tm.operand_types[addr_prefix_disp]
4104 = operand_types[addr_prefix_disp];
4105
29b0f896
AM		 4106 if (found_reverse_match)
4107 {
4108 /* If we found a reverse match we must alter the opcode
4109 direction bit. found_reverse_match holds bits to change
4110 (different for int & float insns). */
4111
4112 i.tm.base_opcode ^= found_reverse_match;
4113
539e75ad
L		 4114 i.tm.operand_types[0] = operand_types[1];
4115 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4116 }
4117
fa99fab2 4118 return t;
29b0f896
AM		 4119}
4120
4121static int
e3bb37b5 4122check_string (void)
29b0f896 4123{
40fb9820
L		 4124 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4125 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4126 {
4127 if (i.seg[0] != NULL && i.seg[0] != &es)
4128 {
a87af027 4129 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4130 i.tm.name,
a87af027
JB		 4131 mem_op + 1,
4132 register_prefix);
29b0f896
AM		 4133 return 0;
4134 }
4135 /* There's only ever one segment override allowed per instruction.
4136 This instruction possibly has a legal segment override on the
4137 second operand, so copy the segment to where non-string
4138 instructions store it, allowing common code. */
4139 i.seg[0] = i.seg[1];
4140 }
40fb9820 4141 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4142 {
4143 if (i.seg[1] != NULL && i.seg[1] != &es)
4144 {
a87af027 4145 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4146 i.tm.name,
a87af027
JB		 4147 mem_op + 2,
4148 register_prefix);
29b0f896
AM		 4149 return 0;
4150 }
4151 }
4152 return 1;
4153}
4154
4155static int
543613e9 4156process_suffix (void)
29b0f896
AM		 4157{
4158 /* If matched instruction specifies an explicit instruction mnemonic
4159 suffix, use it. */
40fb9820
L		 4160 if (i.tm.opcode_modifier.size16)
4161 i.suffix = WORD_MNEM_SUFFIX;
4162 else if (i.tm.opcode_modifier.size32)
4163 i.suffix = LONG_MNEM_SUFFIX;
4164 else if (i.tm.opcode_modifier.size64)
4165 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4166 else if (i.reg_operands)
4167 {
4168 /* If there's no instruction mnemonic suffix we try to invent one
4169 based on register operands. */
4170 if (!i.suffix)
4171 {
4172 /* We take i.suffix from the last register operand specified,
4173 Destination register type is more significant than source
381d071f
L		 4174 register type. crc32 in SSE4.2 prefers source register
4175 type. */
4176 if (i.tm.base_opcode == 0xf20f38f1)
4177 {
40fb9820
L		 4178 if (i.types[0].bitfield.reg16)
4179 i.suffix = WORD_MNEM_SUFFIX;
4180 else if (i.types[0].bitfield.reg32)
4181 i.suffix = LONG_MNEM_SUFFIX;
4182 else if (i.types[0].bitfield.reg64)
4183 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4184 }
9344ff29 4185 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4186 {
40fb9820 4187 if (i.types[0].bitfield.reg8)
20592a94
L		 4188 i.suffix = BYTE_MNEM_SUFFIX;
4189 }
381d071f
L		 4190
4191 if (!i.suffix)
4192 {
4193 int op;
4194
20592a94
L		 4195 if (i.tm.base_opcode == 0xf20f38f1
4196 || i.tm.base_opcode == 0xf20f38f0)
4197 {
4198 /* We have to know the operand size for crc32. */
4199 as_bad (_("ambiguous memory operand size for `%s`"),
4200 i.tm.name);
4201 return 0;
4202 }
4203
381d071f 4204 for (op = i.operands; --op >= 0;)
40fb9820 4205 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4206 {
40fb9820
L		 4207 if (i.types[op].bitfield.reg8)
4208 {
4209 i.suffix = BYTE_MNEM_SUFFIX;
4210 break;
4211 }
4212 else if (i.types[op].bitfield.reg16)
4213 {
4214 i.suffix = WORD_MNEM_SUFFIX;
4215 break;
4216 }
4217 else if (i.types[op].bitfield.reg32)
4218 {
4219 i.suffix = LONG_MNEM_SUFFIX;
4220 break;
4221 }
4222 else if (i.types[op].bitfield.reg64)
4223 {
4224 i.suffix = QWORD_MNEM_SUFFIX;
4225 break;
4226 }
381d071f
L		 4227 }
4228 }
29b0f896
AM		 4229 }
4230 else if (i.suffix == BYTE_MNEM_SUFFIX)
4231 {
2eb952a4
L		 4232 if (intel_syntax
4233 && i.tm.opcode_modifier.ignoresize
4234 && i.tm.opcode_modifier.no_bsuf)
4235 i.suffix = 0;
4236 else if (!check_byte_reg ())
29b0f896
AM		 4237 return 0;
4238 }
4239 else if (i.suffix == LONG_MNEM_SUFFIX)
4240 {
2eb952a4
L		 4241 if (intel_syntax
4242 && i.tm.opcode_modifier.ignoresize
4243 && i.tm.opcode_modifier.no_lsuf)
4244 i.suffix = 0;
4245 else if (!check_long_reg ())
29b0f896
AM		 4246 return 0;
4247 }
4248 else if (i.suffix == QWORD_MNEM_SUFFIX)
4249 {
955e1e6a
L		 4250 if (intel_syntax
4251 && i.tm.opcode_modifier.ignoresize
4252 && i.tm.opcode_modifier.no_qsuf)
4253 i.suffix = 0;
4254 else if (!check_qword_reg ())
29b0f896
AM		 4255 return 0;
4256 }
4257 else if (i.suffix == WORD_MNEM_SUFFIX)
4258 {
2eb952a4
L		 4259 if (intel_syntax
4260 && i.tm.opcode_modifier.ignoresize
4261 && i.tm.opcode_modifier.no_wsuf)
4262 i.suffix = 0;
4263 else if (!check_word_reg ())
29b0f896
AM		 4264 return 0;
4265 }
c0f3af97
L		 4266 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4267 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4268 {
c0f3af97 4269 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4270 should check if it is a valid suffix. */
4271 }
40fb9820 4272 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4273 /* Do nothing if the instruction is going to ignore the prefix. */
4274 ;
4275 else
4276 abort ();
4277 }
40fb9820 4278 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4279 && !i.suffix
4280 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4281 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4282 {
4283 i.suffix = stackop_size;
4284 }
9306ca4a
JB		 4285 else if (intel_syntax
4286 && !i.suffix
40fb9820
L		 4287 && (i.tm.operand_types[0].bitfield.jumpabsolute
4288 || i.tm.opcode_modifier.jumpbyte
4289 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4290 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4291 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4292 {
4293 switch (flag_code)
4294 {
4295 case CODE_64BIT:
40fb9820 4296 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4297 {
4298 i.suffix = QWORD_MNEM_SUFFIX;
4299 break;
4300 }
4301 case CODE_32BIT:
40fb9820 4302 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4303 i.suffix = LONG_MNEM_SUFFIX;
4304 break;
4305 case CODE_16BIT:
40fb9820 4306 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4307 i.suffix = WORD_MNEM_SUFFIX;
4308 break;
4309 }
4310 }
252b5132 4311
9306ca4a 4312 if (!i.suffix)
29b0f896 4313 {
9306ca4a
JB		 4314 if (!intel_syntax)
4315 {
40fb9820 4316 if (i.tm.opcode_modifier.w)
9306ca4a 4317 {
4eed87de
AM		 4318 as_bad (_("no instruction mnemonic suffix given and "
4319 "no register operands; can't size instruction"));
9306ca4a
JB		 4320 return 0;
4321 }
4322 }
4323 else
4324 {
40fb9820 4325 unsigned int suffixes;
7ab9ffdd 4326
40fb9820
L		 4327 suffixes = !i.tm.opcode_modifier.no_bsuf;
4328 if (!i.tm.opcode_modifier.no_wsuf)
4329 suffixes |= 1 << 1;
4330 if (!i.tm.opcode_modifier.no_lsuf)
4331 suffixes |= 1 << 2;
fc4adea1 4332 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4333 suffixes |= 1 << 3;
4334 if (!i.tm.opcode_modifier.no_ssuf)
4335 suffixes |= 1 << 4;
4336 if (!i.tm.opcode_modifier.no_qsuf)
4337 suffixes |= 1 << 5;
4338
4339 /* There are more than suffix matches. */
4340 if (i.tm.opcode_modifier.w
9306ca4a 4341 || ((suffixes & (suffixes - 1))
40fb9820
L		 4342 && !i.tm.opcode_modifier.defaultsize
4343 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4344 {
4345 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4346 return 0;
4347 }
4348 }
29b0f896 4349 }
252b5132 4350
9306ca4a
JB		 4351 /* Change the opcode based on the operand size given by i.suffix;
4352 We don't need to change things for byte insns. */
4353
582d5edd
L		 4354 if (i.suffix
4355 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4356 && i.suffix != XMMWORD_MNEM_SUFFIX
4357 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4358 {
4359 /* It's not a byte, select word/dword operation. */
40fb9820 4360 if (i.tm.opcode_modifier.w)
29b0f896 4361 {
40fb9820 4362 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4363 i.tm.base_opcode |= 8;
4364 else
4365 i.tm.base_opcode |= 1;
4366 }
0f3f3d8b 4367
29b0f896
AM		 4368 /* Now select between word & dword operations via the operand
4369 size prefix, except for instructions that will ignore this
4370 prefix anyway. */
ca61edf2 4371 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4372 {
ca61edf2
L		 4373 /* The address size override prefix changes the size of the
4374 first operand. */
40fb9820
L		 4375 if ((flag_code == CODE_32BIT
4376 && i.op->regs[0].reg_type.bitfield.reg16)
4377 || (flag_code != CODE_32BIT
4378 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4379 if (!add_prefix (ADDR_PREFIX_OPCODE))
4380 return 0;
4381 }
4382 else if (i.suffix != QWORD_MNEM_SUFFIX
4383 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4384 && !i.tm.opcode_modifier.ignoresize
4385 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4386 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4387 || (flag_code == CODE_64BIT
40fb9820 4388 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4389 {
4390 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4391
40fb9820 4392 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4393 prefix = ADDR_PREFIX_OPCODE;
252b5132 4394
29b0f896
AM		 4395 if (!add_prefix (prefix))
4396 return 0;
24eab124 4397 }
252b5132 4398
29b0f896
AM		 4399 /* Set mode64 for an operand. */
4400 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4401 && flag_code == CODE_64BIT
40fb9820 4402 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4403 {
4404 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4405 need rex64. cmpxchg8b is also a special case. */
4406 if (! (i.operands == 2
4407 && i.tm.base_opcode == 0x90
4408 && i.tm.extension_opcode == None
0dfbf9d7
L		 4409 && operand_type_equal (&i.types [0], &acc64)
4410 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4411 && ! (i.operands == 1
4412 && i.tm.base_opcode == 0xfc7
4413 && i.tm.extension_opcode == 1
40fb9820
L		 4414 && !operand_type_check (i.types [0], reg)
4415 && operand_type_check (i.types [0], anymem)))
f6bee062 4416 i.rex |= REX_W;
46e883c5 4417 }
3e73aa7c 4418
29b0f896
AM		 4419 /* Size floating point instruction. */
4420 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4421 if (i.tm.opcode_modifier.floatmf)
543613e9 4422 i.tm.base_opcode ^= 4;
29b0f896 4423 }
7ecd2f8b 4424
29b0f896
AM		 4425 return 1;
4426}
3e73aa7c 4427
29b0f896 4428static int
543613e9 4429check_byte_reg (void)
29b0f896
AM		 4430{
4431 int op;
543613e9 4432
29b0f896
AM		 4433 for (op = i.operands; --op >= 0;)
4434 {
4435 /* If this is an eight bit register, it's OK. If it's the 16 or
4436 32 bit version of an eight bit register, we will just use the
4437 low portion, and that's OK too. */
40fb9820 4438 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4439 continue;
4440
9344ff29
L		 4441 /* crc32 doesn't generate this warning. */
4442 if (i.tm.base_opcode == 0xf20f38f0)
4443 continue;
4444
40fb9820
L		 4445 if ((i.types[op].bitfield.reg16
4446 || i.types[op].bitfield.reg32
4447 || i.types[op].bitfield.reg64)
4448 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4449 {
4450 /* Prohibit these changes in the 64bit mode, since the
4451 lowering is more complicated. */
4452 if (flag_code == CODE_64BIT
40fb9820 4453 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4454 {
2ca3ace5
L		 4455 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4456 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4457 i.suffix);
4458 return 0;
4459 }
4460#if REGISTER_WARNINGS
4461 if (!quiet_warnings
40fb9820 4462 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4463 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4464 register_prefix,
40fb9820 4465 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4466 ? REGNAM_AL - REGNAM_AX
4467 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4468 register_prefix,
29b0f896
AM		 4469 i.op[op].regs->reg_name,
4470 i.suffix);
4471#endif
4472 continue;
4473 }
4474 /* Any other register is bad. */
40fb9820
L		 4475 if (i.types[op].bitfield.reg16
4476 || i.types[op].bitfield.reg32
4477 || i.types[op].bitfield.reg64
4478 || i.types[op].bitfield.regmmx
4479 || i.types[op].bitfield.regxmm
c0f3af97 4480 || i.types[op].bitfield.regymm
40fb9820
L		 4481 || i.types[op].bitfield.sreg2
4482 || i.types[op].bitfield.sreg3
4483 || i.types[op].bitfield.control
4484 || i.types[op].bitfield.debug
4485 || i.types[op].bitfield.test
4486 || i.types[op].bitfield.floatreg
4487 || i.types[op].bitfield.floatacc)
29b0f896 4488 {
a540244d
L		 4489 as_bad (_("`%s%s' not allowed with `%s%c'"),
4490 register_prefix,
29b0f896
AM		 4491 i.op[op].regs->reg_name,
4492 i.tm.name,
4493 i.suffix);
4494 return 0;
4495 }
4496 }
4497 return 1;
4498}
4499
4500static int
e3bb37b5 4501check_long_reg (void)
29b0f896
AM		 4502{
4503 int op;
4504
4505 for (op = i.operands; --op >= 0;)
4506 /* Reject eight bit registers, except where the template requires
4507 them. (eg. movzb) */
40fb9820
L		 4508 if (i.types[op].bitfield.reg8
4509 && (i.tm.operand_types[op].bitfield.reg16
4510 || i.tm.operand_types[op].bitfield.reg32
4511 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4512 {
a540244d
L		 4513 as_bad (_("`%s%s' not allowed with `%s%c'"),
4514 register_prefix,
29b0f896
AM		 4515 i.op[op].regs->reg_name,
4516 i.tm.name,
4517 i.suffix);
4518 return 0;
4519 }
4520 /* Warn if the e prefix on a general reg is missing. */
4521 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4522 && i.types[op].bitfield.reg16
4523 && (i.tm.operand_types[op].bitfield.reg32
4524 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4525 {
4526 /* Prohibit these changes in the 64bit mode, since the
4527 lowering is more complicated. */
4528 if (flag_code == CODE_64BIT)
252b5132 4529 {
2ca3ace5
L		 4530 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4531 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4532 i.suffix);
4533 return 0;
252b5132 4534 }
29b0f896
AM		 4535#if REGISTER_WARNINGS
4536 else
a540244d
L		 4537 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4538 register_prefix,
29b0f896 4539 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4540 register_prefix,
29b0f896
AM		 4541 i.op[op].regs->reg_name,
4542 i.suffix);
4543#endif
252b5132 4544 }
29b0f896 4545 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4546 else if (i.types[op].bitfield.reg64
4547 && (i.tm.operand_types[op].bitfield.reg32
4548 || i.tm.operand_types[op].bitfield.acc))
252b5132 4549 {
34828aad 4550 if (intel_syntax
ca61edf2 4551 && i.tm.opcode_modifier.toqword
40fb9820 4552 && !i.types[0].bitfield.regxmm)
34828aad 4553 {
ca61edf2 4554 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4555 i.suffix = QWORD_MNEM_SUFFIX;
4556 }
4557 else
4558 {
4559 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4560 register_prefix, i.op[op].regs->reg_name,
4561 i.suffix);
4562 return 0;
4563 }
29b0f896
AM		 4564 }
4565 return 1;
4566}
252b5132 4567
29b0f896 4568static int
e3bb37b5 4569check_qword_reg (void)
29b0f896
AM		 4570{
4571 int op;
252b5132 4572
29b0f896
AM		 4573 for (op = i.operands; --op >= 0; )
4574 /* Reject eight bit registers, except where the template requires
4575 them. (eg. movzb) */
40fb9820
L		 4576 if (i.types[op].bitfield.reg8
4577 && (i.tm.operand_types[op].bitfield.reg16
4578 || i.tm.operand_types[op].bitfield.reg32
4579 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4580 {
a540244d
L		 4581 as_bad (_("`%s%s' not allowed with `%s%c'"),
4582 register_prefix,
29b0f896
AM		 4583 i.op[op].regs->reg_name,
4584 i.tm.name,
4585 i.suffix);
4586 return 0;
4587 }
4588 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4589 else if ((i.types[op].bitfield.reg16
4590 || i.types[op].bitfield.reg32)
4591 && (i.tm.operand_types[op].bitfield.reg32
4592 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4593 {
4594 /* Prohibit these changes in the 64bit mode, since the
4595 lowering is more complicated. */
34828aad 4596 if (intel_syntax
ca61edf2 4597 && i.tm.opcode_modifier.todword
40fb9820 4598 && !i.types[0].bitfield.regxmm)
34828aad 4599 {
ca61edf2 4600 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4601 i.suffix = LONG_MNEM_SUFFIX;
4602 }
4603 else
4604 {
4605 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4606 register_prefix, i.op[op].regs->reg_name,
4607 i.suffix);
4608 return 0;
4609 }
252b5132 4610 }
29b0f896
AM		 4611 return 1;
4612}
252b5132 4613
29b0f896 4614static int
e3bb37b5 4615check_word_reg (void)
29b0f896
AM		 4616{
4617 int op;
4618 for (op = i.operands; --op >= 0;)
4619 /* Reject eight bit registers, except where the template requires
4620 them. (eg. movzb) */
40fb9820
L		 4621 if (i.types[op].bitfield.reg8
4622 && (i.tm.operand_types[op].bitfield.reg16
4623 || i.tm.operand_types[op].bitfield.reg32
4624 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4625 {
a540244d
L		 4626 as_bad (_("`%s%s' not allowed with `%s%c'"),
4627 register_prefix,
29b0f896
AM		 4628 i.op[op].regs->reg_name,
4629 i.tm.name,
4630 i.suffix);
4631 return 0;
4632 }
4633 /* Warn if the e prefix on a general reg is present. */
4634 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4635 && i.types[op].bitfield.reg32
4636 && (i.tm.operand_types[op].bitfield.reg16
4637 || i.tm.operand_types[op].bitfield.acc))
252b5132 4638 {
29b0f896
AM		 4639 /* Prohibit these changes in the 64bit mode, since the
4640 lowering is more complicated. */
4641 if (flag_code == CODE_64BIT)
252b5132 4642 {
2ca3ace5
L		 4643 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4644 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4645 i.suffix);
4646 return 0;
252b5132 4647 }
29b0f896
AM		 4648 else
4649#if REGISTER_WARNINGS
a540244d
L		 4650 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4651 register_prefix,
29b0f896 4652 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4653 register_prefix,
29b0f896
AM		 4654 i.op[op].regs->reg_name,
4655 i.suffix);
4656#endif
4657 }
4658 return 1;
4659}
252b5132 4660
29b0f896 4661static int
40fb9820 4662update_imm (unsigned int j)
29b0f896 4663{
bc0844ae 4664 i386_operand_type overlap = i.types[j];
40fb9820
L		 4665 if ((overlap.bitfield.imm8
4666 || overlap.bitfield.imm8s
4667 || overlap.bitfield.imm16
4668 || overlap.bitfield.imm32
4669 || overlap.bitfield.imm32s
4670 || overlap.bitfield.imm64)
0dfbf9d7
L		 4671 && !operand_type_equal (&overlap, &imm8)
4672 && !operand_type_equal (&overlap, &imm8s)
4673 && !operand_type_equal (&overlap, &imm16)
4674 && !operand_type_equal (&overlap, &imm32)
4675 && !operand_type_equal (&overlap, &imm32s)
4676 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4677 {
4678 if (i.suffix)
4679 {
40fb9820
L		 4680 i386_operand_type temp;
4681
0dfbf9d7 4682 operand_type_set (&temp, 0);
7ab9ffdd 4683 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4684 {
4685 temp.bitfield.imm8 = overlap.bitfield.imm8;
4686 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4687 }
4688 else if (i.suffix == WORD_MNEM_SUFFIX)
4689 temp.bitfield.imm16 = overlap.bitfield.imm16;
4690 else if (i.suffix == QWORD_MNEM_SUFFIX)
4691 {
4692 temp.bitfield.imm64 = overlap.bitfield.imm64;
4693 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4694 }
4695 else
4696 temp.bitfield.imm32 = overlap.bitfield.imm32;
4697 overlap = temp;
29b0f896 4698 }
0dfbf9d7
L		 4699 else if (operand_type_equal (&overlap, &imm16_32_32s)
4700 || operand_type_equal (&overlap, &imm16_32)
4701 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4702 {
40fb9820 4703 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4704 overlap = imm16;
40fb9820 4705 else
65da13b5 4706 overlap = imm32s;
29b0f896 4707 }
0dfbf9d7
L		 4708 if (!operand_type_equal (&overlap, &imm8)
4709 && !operand_type_equal (&overlap, &imm8s)
4710 && !operand_type_equal (&overlap, &imm16)
4711 && !operand_type_equal (&overlap, &imm32)
4712 && !operand_type_equal (&overlap, &imm32s)
4713 && !operand_type_equal (&overlap, &imm64))
29b0f896 4714 {
4eed87de
AM		 4715 as_bad (_("no instruction mnemonic suffix given; "
4716 "can't determine immediate size"));
29b0f896
AM		 4717 return 0;
4718 }
4719 }
40fb9820 4720 i.types[j] = overlap;
29b0f896 4721
40fb9820
L		 4722 return 1;
4723}
4724
4725static int
4726finalize_imm (void)
4727{
bc0844ae 4728 unsigned int j, n;
29b0f896 4729
bc0844ae
L		 4730 /* Update the first 2 immediate operands. */
4731 n = i.operands > 2 ? 2 : i.operands;
4732 if (n)
4733 {
4734 for (j = 0; j < n; j++)
4735 if (update_imm (j) == 0)
4736 return 0;
40fb9820 4737
bc0844ae
L		 4738 /* The 3rd operand can't be immediate operand. */
4739 gas_assert (operand_type_check (i.types[2], imm) == 0);
4740 }
29b0f896
AM		 4741
4742 return 1;
4743}
4744
c0f3af97
L		 4745static int
4746bad_implicit_operand (int xmm)
4747{
91d6fa6a
NC		 4748 const char *ireg = xmm ? "xmm0" : "ymm0";
4749
c0f3af97
L		 4750 if (intel_syntax)
4751 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4752 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4753 else
4754 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4755 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4756 return 0;
4757}
4758
29b0f896 4759static int
e3bb37b5 4760process_operands (void)
29b0f896
AM		 4761{
4762 /* Default segment register this instruction will use for memory
4763 accesses. 0 means unknown. This is only for optimizing out
4764 unnecessary segment overrides. */
4765 const seg_entry *default_seg = 0;
4766
2426c15f 4767 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4768 {
91d6fa6a
NC		 4769 unsigned int dupl = i.operands;
4770 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4771 unsigned int j;
4772
c0f3af97 4773 /* The destination must be an xmm register. */
9c2799c2 4774 gas_assert (i.reg_operands
91d6fa6a 4775 && MAX_OPERANDS > dupl
7ab9ffdd 4776 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4777
4778 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4779 {
c0f3af97 4780 /* The first operand is implicit and must be xmm0. */
9c2799c2 4781 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4782 if (i.op[0].regs->reg_num != 0)
4783 return bad_implicit_operand (1);
4784
8cd7925b 4785 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4786 {
4787 /* Keep xmm0 for instructions with VEX prefix and 3
4788 sources. */
4789 goto duplicate;
4790 }
e2ec9d29 4791 else
c0f3af97
L		 4792 {
4793 /* We remove the first xmm0 and keep the number of
4794 operands unchanged, which in fact duplicates the
4795 destination. */
4796 for (j = 1; j < i.operands; j++)
4797 {
4798 i.op[j - 1] = i.op[j];
4799 i.types[j - 1] = i.types[j];
4800 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4801 }
4802 }
4803 }
4804 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4805 {
91d6fa6a 4806 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4807 && (i.tm.opcode_modifier.vexsources
4808 == VEX3SOURCES));
c0f3af97
L		 4809
4810 /* Add the implicit xmm0 for instructions with VEX prefix
4811 and 3 sources. */
4812 for (j = i.operands; j > 0; j--)
4813 {
4814 i.op[j] = i.op[j - 1];
4815 i.types[j] = i.types[j - 1];
4816 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4817 }
4818 i.op[0].regs
4819 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4820 i.types[0] = regxmm;
c0f3af97
L		 4821 i.tm.operand_types[0] = regxmm;
4822
4823 i.operands += 2;
4824 i.reg_operands += 2;
4825 i.tm.operands += 2;
4826
91d6fa6a 4827 dupl++;
c0f3af97 4828 dest++;
91d6fa6a
NC		 4829 i.op[dupl] = i.op[dest];
4830 i.types[dupl] = i.types[dest];
4831 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4832 }
c0f3af97
L		 4833 else
4834 {
4835duplicate:
4836 i.operands++;
4837 i.reg_operands++;
4838 i.tm.operands++;
4839
91d6fa6a
NC		 4840 i.op[dupl] = i.op[dest];
4841 i.types[dupl] = i.types[dest];
4842 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4843 }
4844
4845 if (i.tm.opcode_modifier.immext)
4846 process_immext ();
4847 }
4848 else if (i.tm.opcode_modifier.firstxmm0)
4849 {
4850 unsigned int j;
4851
4852 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4853 gas_assert (i.reg_operands
7ab9ffdd
L		 4854 && (operand_type_equal (&i.types[0], &regxmm)
4855 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4856 if (i.op[0].regs->reg_num != 0)
4857 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4858
4859 for (j = 1; j < i.operands; j++)
4860 {
4861 i.op[j - 1] = i.op[j];
4862 i.types[j - 1] = i.types[j];
4863
4864 /* We need to adjust fields in i.tm since they are used by
4865 build_modrm_byte. */
4866 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4867 }
4868
e2ec9d29
L		 4869 i.operands--;
4870 i.reg_operands--;
e2ec9d29
L		 4871 i.tm.operands--;
4872 }
4873 else if (i.tm.opcode_modifier.regkludge)
4874 {
4875 /* The imul $imm, %reg instruction is converted into
4876 imul $imm, %reg, %reg, and the clr %reg instruction
4877 is converted into xor %reg, %reg. */
4878
4879 unsigned int first_reg_op;
4880
4881 if (operand_type_check (i.types[0], reg))
4882 first_reg_op = 0;
4883 else
4884 first_reg_op = 1;
4885 /* Pretend we saw the extra register operand. */
9c2799c2 4886 gas_assert (i.reg_operands == 1
7ab9ffdd 4887 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4888 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4889 i.types[first_reg_op + 1] = i.types[first_reg_op];
4890 i.operands++;
4891 i.reg_operands++;
29b0f896
AM		 4892 }
4893
40fb9820 4894 if (i.tm.opcode_modifier.shortform)
29b0f896 4895 {
40fb9820
L		 4896 if (i.types[0].bitfield.sreg2
4897 || i.types[0].bitfield.sreg3)
29b0f896 4898 {
4eed87de
AM		 4899 if (i.tm.base_opcode == POP_SEG_SHORT
4900 && i.op[0].regs->reg_num == 1)
29b0f896 4901 {
a87af027 4902 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4903 return 0;
29b0f896 4904 }
4eed87de
AM		 4905 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4906 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4907 i.rex |= REX_B;
4eed87de
AM		 4908 }
4909 else
4910 {
7ab9ffdd 4911 /* The register or float register operand is in operand
85f10a01 4912 0 or 1. */
40fb9820 4913 unsigned int op;
7ab9ffdd
L		 4914
4915 if (i.types[0].bitfield.floatreg
4916 || operand_type_check (i.types[0], reg))
4917 op = 0;
4918 else
4919 op = 1;
4eed87de
AM		 4920 /* Register goes in low 3 bits of opcode. */
4921 i.tm.base_opcode |= i.op[op].regs->reg_num;
4922 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4923 i.rex |= REX_B;
40fb9820 4924 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4925 {
4eed87de
AM		 4926 /* Warn about some common errors, but press on regardless.
4927 The first case can be generated by gcc (<= 2.8.1). */
4928 if (i.operands == 2)
4929 {
4930 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4931 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4932 register_prefix, i.op[!intel_syntax].regs->reg_name,
4933 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4934 }
4935 else
4936 {
4937 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4938 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4939 register_prefix, i.op[0].regs->reg_name);
4eed87de 4940 }
29b0f896
AM		 4941 }
4942 }
4943 }
40fb9820 4944 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4945 {
4946 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4947 must be put into the modrm byte). Now, we make the modrm and
4948 index base bytes based on all the info we've collected. */
29b0f896
AM		 4949
4950 default_seg = build_modrm_byte ();
4951 }
8a2ed489 4952 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4953 {
4954 default_seg = &ds;
4955 }
40fb9820 4956 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4957 {
4958 /* For the string instructions that allow a segment override
4959 on one of their operands, the default segment is ds. */
4960 default_seg = &ds;
4961 }
4962
75178d9d
L		 4963 if (i.tm.base_opcode == 0x8d /* lea */
4964 && i.seg[0]
4965 && !quiet_warnings)
30123838 4966 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4967
4968 /* If a segment was explicitly specified, and the specified segment
4969 is not the default, use an opcode prefix to select it. If we
4970 never figured out what the default segment is, then default_seg
4971 will be zero at this point, and the specified segment prefix will
4972 always be used. */
29b0f896
AM		 4973 if ((i.seg[0]) && (i.seg[0] != default_seg))
4974 {
4975 if (!add_prefix (i.seg[0]->seg_prefix))
4976 return 0;
4977 }
4978 return 1;
4979}
4980
4981static const seg_entry *
e3bb37b5 4982build_modrm_byte (void)
29b0f896
AM		 4983{
4984 const seg_entry *default_seg = 0;
c0f3af97 4985 unsigned int source, dest;
8cd7925b 4986 int vex_3_sources;
c0f3af97
L		 4987
4988 /* The first operand of instructions with VEX prefix and 3 sources
4989 must be VEX_Imm4. */
8cd7925b 4990 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 4991 if (vex_3_sources)
4992 {
91d6fa6a 4993 unsigned int nds, reg_slot;
4c2c6516 4994 expressionS *exp;
c0f3af97 4995
922d8de8 4996 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 4997 && i.tm.opcode_modifier.immext)
4998 {
4999 dest = i.operands - 2;
5000 gas_assert (dest == 3);
5001 }
922d8de8 5002 else
a683cc34 5003 dest = i.operands - 1;
c0f3af97 5004 nds = dest - 1;
922d8de8 5005
a683cc34
SP		 5006 /* There are 2 kinds of instructions:
5007 1. 5 operands: 4 register operands or 3 register operands
5008 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5009 VexW0 or VexW1. The destination must be either XMM or YMM
5010 register.
5011 2. 4 operands: 4 register operands or 3 register operands
5012 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5013 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5014 || (i.reg_operands == 3 && i.mem_operands == 1))
5015 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5016 && (i.tm.opcode_modifier.veximmext
5017 || (i.imm_operands == 1
5018 && i.types[0].bitfield.vec_imm4
5019 && (i.tm.opcode_modifier.vexw == VEXW0
5020 || i.tm.opcode_modifier.vexw == VEXW1)
5021 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5022 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5023
5024 if (i.imm_operands == 0)
5025 {
5026 /* When there is no immediate operand, generate an 8bit
5027 immediate operand to encode the first operand. */
5028 exp = &im_expressions[i.imm_operands++];
5029 i.op[i.operands].imms = exp;
5030 i.types[i.operands] = imm8;
5031 i.operands++;
5032 /* If VexW1 is set, the first operand is the source and
5033 the second operand is encoded in the immediate operand. */
5034 if (i.tm.opcode_modifier.vexw == VEXW1)
5035 {
5036 source = 0;
5037 reg_slot = 1;
5038 }
5039 else
5040 {
5041 source = 1;
5042 reg_slot = 0;
5043 }
5044
5045 /* FMA swaps REG and NDS. */
5046 if (i.tm.cpu_flags.bitfield.cpufma)
5047 {
5048 unsigned int tmp;
5049 tmp = reg_slot;
5050 reg_slot = nds;
5051 nds = tmp;
5052 }
5053
5054 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
5055 || operand_type_equal (&i.tm.operand_types[reg_slot],
5056 &regymm));
5057 exp->X_op = O_constant;
5058 exp->X_add_number
5059 = ((i.op[reg_slot].regs->reg_num
5060 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5061 }
922d8de8 5062 else
a683cc34
SP		 5063 {
5064 unsigned int imm_slot;
5065
5066 if (i.tm.opcode_modifier.vexw == VEXW0)
5067 {
5068 /* If VexW0 is set, the third operand is the source and
5069 the second operand is encoded in the immediate
5070 operand. */
5071 source = 2;
5072 reg_slot = 1;
5073 }
5074 else
5075 {
5076 /* VexW1 is set, the second operand is the source and
5077 the third operand is encoded in the immediate
5078 operand. */
5079 source = 1;
5080 reg_slot = 2;
5081 }
5082
5083 if (i.tm.opcode_modifier.immext)
5084 {
5085 /* When ImmExt is set, the immdiate byte is the last
5086 operand. */
5087 imm_slot = i.operands - 1;
5088 source--;
5089 reg_slot--;
5090 }
5091 else
5092 {
5093 imm_slot = 0;
5094
5095 /* Turn on Imm8 so that output_imm will generate it. */
5096 i.types[imm_slot].bitfield.imm8 = 1;
5097 }
5098
5099 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
5100 || operand_type_equal (&i.tm.operand_types[reg_slot],
5101 &regymm));
5102 i.op[imm_slot].imms->X_add_number
5103 |= ((i.op[reg_slot].regs->reg_num
5104 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5105 }
5106
5107 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5108 || operand_type_equal (&i.tm.operand_types[nds],
5109 &regymm));
dae39acc 5110 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5111 }
5112 else
5113 source = dest = 0;
29b0f896
AM		 5114
5115 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5116 implicit registers do not count. If there are 3 register
5117 operands, it must be a instruction with VexNDS. For a
5118 instruction with VexNDD, the destination register is encoded
5119 in VEX prefix. If there are 4 register operands, it must be
5120 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5121 if (i.mem_operands == 0
5122 && ((i.reg_operands == 2
2426c15f 5123 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5124 || (i.reg_operands == 3
2426c15f 5125 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5126 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5127 {
cab737b9
L		 5128 switch (i.operands)
5129 {
5130 case 2:
5131 source = 0;
5132 break;
5133 case 3:
c81128dc
L		 5134 /* When there are 3 operands, one of them may be immediate,
5135 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5136 the first operand must be shift count register (cl) or it
5137 is an instruction with VexNDS. */
9c2799c2 5138 gas_assert (i.imm_operands == 1
7ab9ffdd 5139 || (i.imm_operands == 0
2426c15f 5140 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5141 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5142 if (operand_type_check (i.types[0], imm)
5143 || i.types[0].bitfield.shiftcount)
5144 source = 1;
5145 else
5146 source = 0;
cab737b9
L		 5147 break;
5148 case 4:
368d64cc
L		 5149 /* When there are 4 operands, the first two must be 8bit
5150 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5151 one.
5152
5153 For instructions with VexNDS, if the first operand
5154 an imm8, the source operand is the 2nd one. If the last
5155 operand is imm8, the source operand is the first one. */
9c2799c2 5156 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5157 && i.types[0].bitfield.imm8
5158 && i.types[1].bitfield.imm8)
2426c15f 5159 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5160 && i.imm_operands == 1
5161 && (i.types[0].bitfield.imm8
5162 || i.types[i.operands - 1].bitfield.imm8)));
2426c15f 5163 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5164 {
5165 if (i.types[0].bitfield.imm8)
5166 source = 1;
5167 else
5168 source = 0;
5169 }
5170 else
5171 source = 2;
5172 break;
5173 case 5:
cab737b9
L		 5174 break;
5175 default:
5176 abort ();
5177 }
5178
c0f3af97
L		 5179 if (!vex_3_sources)
5180 {
5181 dest = source + 1;
5182
2426c15f 5183 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5184 {
5185 /* For instructions with VexNDS, the register-only
5186 source operand must be XMM or YMM register. It is
fa99fab2
L		 5187 encoded in VEX prefix. We need to clear RegMem bit
5188 before calling operand_type_equal. */
5189 i386_operand_type op = i.tm.operand_types[dest];
5190 op.bitfield.regmem = 0;
c0f3af97 5191 if ((dest + 1) >= i.operands
fa99fab2
L		 5192 || (!operand_type_equal (&op, &regxmm)
5193 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5194 abort ();
5195 i.vex.register_specifier = i.op[dest].regs;
5196 dest++;
5197 }
5198 }
29b0f896
AM		 5199
5200 i.rm.mode = 3;
5201 /* One of the register operands will be encoded in the i.tm.reg
5202 field, the other in the combined i.tm.mode and i.tm.regmem
5203 fields. If no form of this instruction supports a memory
5204 destination operand, then we assume the source operand may
5205 sometimes be a memory operand and so we need to store the
5206 destination in the i.rm.reg field. */
40fb9820
L		 5207 if (!i.tm.operand_types[dest].bitfield.regmem
5208 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5209 {
5210 i.rm.reg = i.op[dest].regs->reg_num;
5211 i.rm.regmem = i.op[source].regs->reg_num;
5212 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5213 i.rex |= REX_R;
29b0f896 5214 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5215 i.rex |= REX_B;
29b0f896
AM		 5216 }
5217 else
5218 {
5219 i.rm.reg = i.op[source].regs->reg_num;
5220 i.rm.regmem = i.op[dest].regs->reg_num;
5221 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5222 i.rex |= REX_B;
29b0f896 5223 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5224 i.rex |= REX_R;
29b0f896 5225 }
161a04f6 5226 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5227 {
40fb9820
L		 5228 if (!i.types[0].bitfield.control
5229 && !i.types[1].bitfield.control)
c4a530c5 5230 abort ();
161a04f6 5231 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5232 add_prefix (LOCK_PREFIX_OPCODE);
5233 }
29b0f896
AM		 5234 }
5235 else
5236 { /* If it's not 2 reg operands... */
c0f3af97
L		 5237 unsigned int mem;
5238
29b0f896
AM		 5239 if (i.mem_operands)
5240 {
5241 unsigned int fake_zero_displacement = 0;
99018f42 5242 unsigned int op;
4eed87de 5243
7ab9ffdd
L		 5244 for (op = 0; op < i.operands; op++)
5245 if (operand_type_check (i.types[op], anymem))
5246 break;
7ab9ffdd 5247 gas_assert (op < i.operands);
29b0f896
AM		 5248
5249 default_seg = &ds;
5250
5251 if (i.base_reg == 0)
5252 {
5253 i.rm.mode = 0;
5254 if (!i.disp_operands)
5255 fake_zero_displacement = 1;
5256 if (i.index_reg == 0)
5257 {
5258 /* Operand is just <disp> */
20f0a1fc 5259 if (flag_code == CODE_64BIT)
29b0f896
AM		 5260 {
5261 /* 64bit mode overwrites the 32bit absolute
5262 addressing by RIP relative addressing and
5263 absolute addressing is encoded by one of the
5264 redundant SIB forms. */
5265 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5266 i.sib.base = NO_BASE_REGISTER;
5267 i.sib.index = NO_INDEX_REGISTER;
fc225355 5268 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5269 ? disp32s : disp32);
20f0a1fc 5270 }
fc225355
L		 5271 else if ((flag_code == CODE_16BIT)
5272 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5273 {
5274 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5275 i.types[op] = disp16;
20f0a1fc
NC		 5276 }
5277 else
5278 {
5279 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5280 i.types[op] = disp32;
29b0f896
AM		 5281 }
5282 }
5283 else /* !i.base_reg && i.index_reg */
5284 {
db51cc60
L		 5285 if (i.index_reg->reg_num == RegEiz
5286 || i.index_reg->reg_num == RegRiz)
5287 i.sib.index = NO_INDEX_REGISTER;
5288 else
5289 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5290 i.sib.base = NO_BASE_REGISTER;
5291 i.sib.scale = i.log2_scale_factor;
5292 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5293 i.types[op].bitfield.disp8 = 0;
5294 i.types[op].bitfield.disp16 = 0;
5295 i.types[op].bitfield.disp64 = 0;
29b0f896 5296 if (flag_code != CODE_64BIT)
40fb9820
L		 5297 {
5298 /* Must be 32 bit */
5299 i.types[op].bitfield.disp32 = 1;
5300 i.types[op].bitfield.disp32s = 0;
5301 }
29b0f896 5302 else
40fb9820
L		 5303 {
5304 i.types[op].bitfield.disp32 = 0;
5305 i.types[op].bitfield.disp32s = 1;
5306 }
29b0f896 5307 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5308 i.rex |= REX_X;
29b0f896
AM		 5309 }
5310 }
5311 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5312 else if (i.base_reg->reg_num == RegRip ||
5313 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5314 {
5315 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5316 i.types[op].bitfield.disp8 = 0;
5317 i.types[op].bitfield.disp16 = 0;
5318 i.types[op].bitfield.disp32 = 0;
5319 i.types[op].bitfield.disp32s = 1;
5320 i.types[op].bitfield.disp64 = 0;
71903a11 5321 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5322 if (! i.disp_operands)
5323 fake_zero_displacement = 1;
29b0f896 5324 }
40fb9820 5325 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5326 {
5327 switch (i.base_reg->reg_num)
5328 {
5329 case 3: /* (%bx) */
5330 if (i.index_reg == 0)
5331 i.rm.regmem = 7;
5332 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5333 i.rm.regmem = i.index_reg->reg_num - 6;
5334 break;
5335 case 5: /* (%bp) */
5336 default_seg = &ss;
5337 if (i.index_reg == 0)
5338 {
5339 i.rm.regmem = 6;
40fb9820 5340 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5341 {
5342 /* fake (%bp) into 0(%bp) */
40fb9820 5343 i.types[op].bitfield.disp8 = 1;
252b5132 5344 fake_zero_displacement = 1;
29b0f896
AM		 5345 }
5346 }
5347 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5348 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5349 break;
5350 default: /* (%si) -> 4 or (%di) -> 5 */
5351 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5352 }
5353 i.rm.mode = mode_from_disp_size (i.types[op]);
5354 }
5355 else /* i.base_reg and 32/64 bit mode */
5356 {
5357 if (flag_code == CODE_64BIT
40fb9820
L		 5358 && operand_type_check (i.types[op], disp))
5359 {
5360 i386_operand_type temp;
0dfbf9d7 5361 operand_type_set (&temp, 0);
40fb9820
L		 5362 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5363 i.types[op] = temp;
5364 if (i.prefix[ADDR_PREFIX] == 0)
5365 i.types[op].bitfield.disp32s = 1;
5366 else
5367 i.types[op].bitfield.disp32 = 1;
5368 }
20f0a1fc 5369
29b0f896
AM		 5370 i.rm.regmem = i.base_reg->reg_num;
5371 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5372 i.rex |= REX_B;
29b0f896
AM		 5373 i.sib.base = i.base_reg->reg_num;
5374 /* x86-64 ignores REX prefix bit here to avoid decoder
5375 complications. */
5376 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5377 {
5378 default_seg = &ss;
5379 if (i.disp_operands == 0)
5380 {
5381 fake_zero_displacement = 1;
40fb9820 5382 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5383 }
5384 }
5385 else if (i.base_reg->reg_num == ESP_REG_NUM)
5386 {
5387 default_seg = &ss;
5388 }
5389 i.sib.scale = i.log2_scale_factor;
5390 if (i.index_reg == 0)
5391 {
5392 /* <disp>(%esp) becomes two byte modrm with no index
5393 register. We've already stored the code for esp
5394 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5395 Any base register besides %esp will not use the
5396 extra modrm byte. */
5397 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5398 }
5399 else
5400 {
db51cc60
L		 5401 if (i.index_reg->reg_num == RegEiz
5402 || i.index_reg->reg_num == RegRiz)
5403 i.sib.index = NO_INDEX_REGISTER;
5404 else
5405 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5406 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5407 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5408 i.rex |= REX_X;
29b0f896 5409 }
67a4f2b7
AO		 5410
5411 if (i.disp_operands
5412 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5413 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5414 i.rm.mode = 0;
5415 else
5416 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5417 }
252b5132 5418
29b0f896
AM		 5419 if (fake_zero_displacement)
5420 {
5421 /* Fakes a zero displacement assuming that i.types[op]
5422 holds the correct displacement size. */
5423 expressionS *exp;
5424
9c2799c2 5425 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5426 exp = &disp_expressions[i.disp_operands++];
5427 i.op[op].disps = exp;
5428 exp->X_op = O_constant;
5429 exp->X_add_number = 0;
5430 exp->X_add_symbol = (symbolS *) 0;
5431 exp->X_op_symbol = (symbolS *) 0;
5432 }
c0f3af97
L		 5433
5434 mem = op;
29b0f896 5435 }
c0f3af97
L		 5436 else
5437 mem = ~0;
252b5132 5438
8c43a48b 5439 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5440 {
5441 if (operand_type_check (i.types[0], imm))
5442 i.vex.register_specifier = NULL;
5443 else
5444 {
5445 /* VEX.vvvv encodes one of the sources when the first
5446 operand is not an immediate. */
1ef99a7b 5447 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5448 i.vex.register_specifier = i.op[0].regs;
5449 else
5450 i.vex.register_specifier = i.op[1].regs;
5451 }
5452
5453 /* Destination is a XMM register encoded in the ModRM.reg
5454 and VEX.R bit. */
5455 i.rm.reg = i.op[2].regs->reg_num;
5456 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5457 i.rex |= REX_R;
5458
5459 /* ModRM.rm and VEX.B encodes the other source. */
5460 if (!i.mem_operands)
5461 {
5462 i.rm.mode = 3;
5463
1ef99a7b 5464 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5465 i.rm.regmem = i.op[1].regs->reg_num;
5466 else
5467 i.rm.regmem = i.op[0].regs->reg_num;
5468
5469 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5470 i.rex |= REX_B;
5471 }
5472 }
2426c15f 5473 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5474 {
5475 i.vex.register_specifier = i.op[2].regs;
5476 if (!i.mem_operands)
5477 {
5478 i.rm.mode = 3;
5479 i.rm.regmem = i.op[1].regs->reg_num;
5480 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5481 i.rex |= REX_B;
5482 }
5483 }
29b0f896
AM		 5484 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5485 (if any) based on i.tm.extension_opcode. Again, we must be
5486 careful to make sure that segment/control/debug/test/MMX
5487 registers are coded into the i.rm.reg field. */
f88c9eb0 5488 else if (i.reg_operands)
29b0f896 5489 {
99018f42 5490 unsigned int op;
7ab9ffdd
L		 5491 unsigned int vex_reg = ~0;
5492
5493 for (op = 0; op < i.operands; op++)
5494 if (i.types[op].bitfield.reg8
5495 || i.types[op].bitfield.reg16
5496 || i.types[op].bitfield.reg32
5497 || i.types[op].bitfield.reg64
5498 || i.types[op].bitfield.regmmx
5499 || i.types[op].bitfield.regxmm
5500 || i.types[op].bitfield.regymm
5501 || i.types[op].bitfield.sreg2
5502 || i.types[op].bitfield.sreg3
5503 || i.types[op].bitfield.control
5504 || i.types[op].bitfield.debug
5505 || i.types[op].bitfield.test)
5506 break;
c0209578 5507
7ab9ffdd
L		 5508 if (vex_3_sources)
5509 op = dest;
2426c15f 5510 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5511 {
5512 /* For instructions with VexNDS, the register-only
5513 source operand is encoded in VEX prefix. */
5514 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5515
7ab9ffdd 5516 if (op > mem)
c0f3af97 5517 {
7ab9ffdd
L		 5518 vex_reg = op++;
5519 gas_assert (op < i.operands);
c0f3af97
L		 5520 }
5521 else
c0f3af97 5522 {
7ab9ffdd
L		 5523 vex_reg = op + 1;
5524 gas_assert (vex_reg < i.operands);
c0f3af97 5525 }
7ab9ffdd 5526 }
2426c15f 5527 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5528 {
5529 /* For instructions with VexNDD, there should be
5530 no memory operand and the register destination
5531 is encoded in VEX prefix. */
5532 gas_assert (i.mem_operands == 0
5533 && (op + 2) == i.operands);
5534 vex_reg = op + 1;
5535 }
5536 else
5537 gas_assert (op < i.operands);
99018f42 5538
7ab9ffdd
L		 5539 if (vex_reg != (unsigned int) ~0)
5540 {
5541 gas_assert (i.reg_operands == 2);
5542
5543 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5544 &regxmm)
7ab9ffdd
L		 5545 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5546 &regymm))
5547 abort ();
f88c9eb0 5548
7ab9ffdd
L		 5549 i.vex.register_specifier = i.op[vex_reg].regs;
5550 }
5551
1b9f0c97
L		 5552 /* Don't set OP operand twice. */
5553 if (vex_reg != op)
7ab9ffdd 5554 {
1b9f0c97
L		 5555 /* If there is an extension opcode to put here, the
5556 register number must be put into the regmem field. */
5557 if (i.tm.extension_opcode != None)
5558 {
5559 i.rm.regmem = i.op[op].regs->reg_num;
5560 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5561 i.rex |= REX_B;
5562 }
5563 else
5564 {
5565 i.rm.reg = i.op[op].regs->reg_num;
5566 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5567 i.rex |= REX_R;
5568 }
7ab9ffdd 5569 }
252b5132 5570
29b0f896
AM		 5571 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5572 must set it to 3 to indicate this is a register operand
5573 in the regmem field. */
5574 if (!i.mem_operands)
5575 i.rm.mode = 3;
5576 }
252b5132 5577
29b0f896 5578 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5579 if (i.tm.extension_opcode != None)
29b0f896
AM		 5580 i.rm.reg = i.tm.extension_opcode;
5581 }
5582 return default_seg;
5583}
252b5132 5584
29b0f896 5585static void
e3bb37b5 5586output_branch (void)
29b0f896
AM		 5587{
5588 char *p;
5589 int code16;
5590 int prefix;
5591 relax_substateT subtype;
5592 symbolS *sym;
5593 offsetT off;
5594
5595 code16 = 0;
5596 if (flag_code == CODE_16BIT)
5597 code16 = CODE16;
5598
5599 prefix = 0;
5600 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5601 {
29b0f896
AM		 5602 prefix = 1;
5603 i.prefixes -= 1;
5604 code16 ^= CODE16;
252b5132 5605 }
29b0f896
AM		 5606 /* Pentium4 branch hints. */
5607 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5608 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5609 {
29b0f896
AM		 5610 prefix++;
5611 i.prefixes--;
5612 }
5613 if (i.prefix[REX_PREFIX] != 0)
5614 {
5615 prefix++;
5616 i.prefixes--;
2f66722d
AM		 5617 }
5618
29b0f896
AM		 5619 if (i.prefixes != 0 && !intel_syntax)
5620 as_warn (_("skipping prefixes on this instruction"));
5621
5622 /* It's always a symbol; End frag & setup for relax.
5623 Make sure there is enough room in this frag for the largest
5624 instruction we may generate in md_convert_frag. This is 2
5625 bytes for the opcode and room for the prefix and largest
5626 displacement. */
5627 frag_grow (prefix + 2 + 4);
5628 /* Prefix and 1 opcode byte go in fr_fix. */
5629 p = frag_more (prefix + 1);
5630 if (i.prefix[DATA_PREFIX] != 0)
5631 *p++ = DATA_PREFIX_OPCODE;
5632 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5633 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5634 *p++ = i.prefix[SEG_PREFIX];
5635 if (i.prefix[REX_PREFIX] != 0)
5636 *p++ = i.prefix[REX_PREFIX];
5637 *p = i.tm.base_opcode;
5638
5639 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5640 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5641 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5642 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5643 else
5644 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5645 subtype |= code16;
3e73aa7c 5646
29b0f896
AM		 5647 sym = i.op[0].disps->X_add_symbol;
5648 off = i.op[0].disps->X_add_number;
3e73aa7c 5649
29b0f896
AM		 5650 if (i.op[0].disps->X_op != O_constant
5651 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5652 {
29b0f896
AM		 5653 /* Handle complex expressions. */
5654 sym = make_expr_symbol (i.op[0].disps);
5655 off = 0;
5656 }
3e73aa7c 5657
29b0f896
AM		 5658 /* 1 possible extra opcode + 4 byte displacement go in var part.
5659 Pass reloc in fr_var. */
5660 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5661}
3e73aa7c 5662
29b0f896 5663static void
e3bb37b5 5664output_jump (void)
29b0f896
AM		 5665{
5666 char *p;
5667 int size;
3e02c1cc 5668 fixS *fixP;
29b0f896 5669
40fb9820 5670 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5671 {
5672 /* This is a loop or jecxz type instruction. */
5673 size = 1;
5674 if (i.prefix[ADDR_PREFIX] != 0)
5675 {
5676 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5677 i.prefixes -= 1;
5678 }
5679 /* Pentium4 branch hints. */
5680 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5681 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5682 {
5683 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5684 i.prefixes--;
3e73aa7c
JH		 5685 }
5686 }
29b0f896
AM		 5687 else
5688 {
5689 int code16;
3e73aa7c 5690
29b0f896
AM		 5691 code16 = 0;
5692 if (flag_code == CODE_16BIT)
5693 code16 = CODE16;
3e73aa7c 5694
29b0f896
AM		 5695 if (i.prefix[DATA_PREFIX] != 0)
5696 {
5697 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5698 i.prefixes -= 1;
5699 code16 ^= CODE16;
5700 }
252b5132 5701
29b0f896
AM		 5702 size = 4;
5703 if (code16)
5704 size = 2;
5705 }
9fcc94b6 5706
29b0f896
AM		 5707 if (i.prefix[REX_PREFIX] != 0)
5708 {
5709 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5710 i.prefixes -= 1;
5711 }
252b5132 5712
29b0f896
AM		 5713 if (i.prefixes != 0 && !intel_syntax)
5714 as_warn (_("skipping prefixes on this instruction"));
e0890092 5715
29b0f896
AM		 5716 p = frag_more (1 + size);
5717 *p++ = i.tm.base_opcode;
e0890092 5718
3e02c1cc
AM		 5719 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5720 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5721
5722 /* All jumps handled here are signed, but don't use a signed limit
5723 check for 32 and 16 bit jumps as we want to allow wrap around at
5724 4G and 64k respectively. */
5725 if (size == 1)
5726 fixP->fx_signed = 1;
29b0f896 5727}
e0890092 5728
29b0f896 5729static void
e3bb37b5 5730output_interseg_jump (void)
29b0f896
AM		 5731{
5732 char *p;
5733 int size;
5734 int prefix;
5735 int code16;
252b5132 5736
29b0f896
AM		 5737 code16 = 0;
5738 if (flag_code == CODE_16BIT)
5739 code16 = CODE16;
a217f122 5740
29b0f896
AM		 5741 prefix = 0;
5742 if (i.prefix[DATA_PREFIX] != 0)
5743 {
5744 prefix = 1;
5745 i.prefixes -= 1;
5746 code16 ^= CODE16;
5747 }
5748 if (i.prefix[REX_PREFIX] != 0)
5749 {
5750 prefix++;
5751 i.prefixes -= 1;
5752 }
252b5132 5753
29b0f896
AM		 5754 size = 4;
5755 if (code16)
5756 size = 2;
252b5132 5757
29b0f896
AM		 5758 if (i.prefixes != 0 && !intel_syntax)
5759 as_warn (_("skipping prefixes on this instruction"));
252b5132 5760
29b0f896
AM		 5761 /* 1 opcode; 2 segment; offset */
5762 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5763
29b0f896
AM		 5764 if (i.prefix[DATA_PREFIX] != 0)
5765 *p++ = DATA_PREFIX_OPCODE;
252b5132 5766
29b0f896
AM		 5767 if (i.prefix[REX_PREFIX] != 0)
5768 *p++ = i.prefix[REX_PREFIX];
252b5132 5769
29b0f896
AM		 5770 *p++ = i.tm.base_opcode;
5771 if (i.op[1].imms->X_op == O_constant)
5772 {
5773 offsetT n = i.op[1].imms->X_add_number;
252b5132 5774
29b0f896
AM		 5775 if (size == 2
5776 && !fits_in_unsigned_word (n)
5777 && !fits_in_signed_word (n))
5778 {
5779 as_bad (_("16-bit jump out of range"));
5780 return;
5781 }
5782 md_number_to_chars (p, n, size);
5783 }
5784 else
5785 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5786 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5787 if (i.op[0].imms->X_op != O_constant)
5788 as_bad (_("can't handle non absolute segment in `%s'"),
5789 i.tm.name);
5790 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5791}
a217f122 5792
29b0f896 5793static void
e3bb37b5 5794output_insn (void)
29b0f896 5795{
2bbd9c25
JJ		 5796 fragS *insn_start_frag;
5797 offsetT insn_start_off;
5798
29b0f896
AM		 5799 /* Tie dwarf2 debug info to the address at the start of the insn.
5800 We can't do this after the insn has been output as the current
5801 frag may have been closed off. eg. by frag_var. */
5802 dwarf2_emit_insn (0);
5803
2bbd9c25
JJ		 5804 insn_start_frag = frag_now;
5805 insn_start_off = frag_now_fix ();
5806
29b0f896 5807 /* Output jumps. */
40fb9820 5808 if (i.tm.opcode_modifier.jump)
29b0f896 5809 output_branch ();
40fb9820
L		 5810 else if (i.tm.opcode_modifier.jumpbyte
5811 || i.tm.opcode_modifier.jumpdword)
29b0f896 5812 output_jump ();
40fb9820 5813 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5814 output_interseg_jump ();
5815 else
5816 {
5817 /* Output normal instructions here. */
5818 char *p;
5819 unsigned char *q;
47465058 5820 unsigned int j;
331d2d0d 5821 unsigned int prefix;
4dffcebc 5822
c0f3af97
L		 5823 /* Since the VEX prefix contains the implicit prefix, we don't
5824 need the explicit prefix. */
5825 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5826 {
c0f3af97 5827 switch (i.tm.opcode_length)
bc4bd9ab 5828 {
c0f3af97
L		 5829 case 3:
5830 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5831 {
c0f3af97
L		 5832 prefix = (i.tm.base_opcode >> 24) & 0xff;
5833 goto check_prefix;
5834 }
5835 break;
5836 case 2:
5837 if ((i.tm.base_opcode & 0xff0000) != 0)
5838 {
5839 prefix = (i.tm.base_opcode >> 16) & 0xff;
5840 if (i.tm.cpu_flags.bitfield.cpupadlock)
5841 {
4dffcebc 5842check_prefix:
c0f3af97 5843 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5844 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5845 != REPE_PREFIX_OPCODE))
5846 add_prefix (prefix);
5847 }
5848 else
4dffcebc
L		 5849 add_prefix (prefix);
5850 }
c0f3af97
L		 5851 break;
5852 case 1:
5853 break;
5854 default:
5855 abort ();
bc4bd9ab 5856 }
c0f3af97
L		 5857
5858 /* The prefix bytes. */
5859 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5860 if (*q)
5861 FRAG_APPEND_1_CHAR (*q);
0f10071e 5862 }
252b5132 5863
c0f3af97
L		 5864 if (i.tm.opcode_modifier.vex)
5865 {
5866 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5867 if (*q)
5868 switch (j)
5869 {
5870 case REX_PREFIX:
5871 /* REX byte is encoded in VEX prefix. */
5872 break;
5873 case SEG_PREFIX:
5874 case ADDR_PREFIX:
5875 FRAG_APPEND_1_CHAR (*q);
5876 break;
5877 default:
5878 /* There should be no other prefixes for instructions
5879 with VEX prefix. */
5880 abort ();
5881 }
5882
5883 /* Now the VEX prefix. */
5884 p = frag_more (i.vex.length);
5885 for (j = 0; j < i.vex.length; j++)
5886 p[j] = i.vex.bytes[j];
5887 }
252b5132 5888
29b0f896 5889 /* Now the opcode; be careful about word order here! */
4dffcebc 5890 if (i.tm.opcode_length == 1)
29b0f896
AM		 5891 {
5892 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5893 }
5894 else
5895 {
4dffcebc 5896 switch (i.tm.opcode_length)
331d2d0d 5897 {
4dffcebc 5898 case 3:
331d2d0d
L		 5899 p = frag_more (3);
5900 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5901 break;
5902 case 2:
5903 p = frag_more (2);
5904 break;
5905 default:
5906 abort ();
5907 break;
331d2d0d 5908 }
0f10071e 5909
29b0f896
AM		 5910 /* Put out high byte first: can't use md_number_to_chars! */
5911 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5912 *p = i.tm.base_opcode & 0xff;
5913 }
3e73aa7c 5914
29b0f896 5915 /* Now the modrm byte and sib byte (if present). */
40fb9820 5916 if (i.tm.opcode_modifier.modrm)
29b0f896 5917 {
4a3523fa
L		 5918 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5919 | i.rm.reg << 3
5920 | i.rm.mode << 6));
29b0f896
AM		 5921 /* If i.rm.regmem == ESP (4)
5922 && i.rm.mode != (Register mode)
5923 && not 16 bit
5924 ==> need second modrm byte. */
5925 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5926 && i.rm.mode != 3
40fb9820 5927 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5928 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5929 | i.sib.index << 3
5930 | i.sib.scale << 6));
29b0f896 5931 }
3e73aa7c 5932
29b0f896 5933 if (i.disp_operands)
2bbd9c25 5934 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5935
29b0f896 5936 if (i.imm_operands)
2bbd9c25 5937 output_imm (insn_start_frag, insn_start_off);
29b0f896 5938 }
252b5132 5939
29b0f896
AM		 5940#ifdef DEBUG386
5941 if (flag_debug)
5942 {
7b81dfbb 5943 pi ("" /*line*/, &i);
29b0f896
AM		 5944 }
5945#endif /* DEBUG386 */
5946}
252b5132 5947
e205caa7
L		 5948/* Return the size of the displacement operand N. */
5949
5950static int
5951disp_size (unsigned int n)
5952{
5953 int size = 4;
40fb9820
L		 5954 if (i.types[n].bitfield.disp64)
5955 size = 8;
5956 else if (i.types[n].bitfield.disp8)
5957 size = 1;
5958 else if (i.types[n].bitfield.disp16)
5959 size = 2;
e205caa7
L		 5960 return size;
5961}
5962
5963/* Return the size of the immediate operand N. */
5964
5965static int
5966imm_size (unsigned int n)
5967{
5968 int size = 4;
40fb9820
L		 5969 if (i.types[n].bitfield.imm64)
5970 size = 8;
5971 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5972 size = 1;
5973 else if (i.types[n].bitfield.imm16)
5974 size = 2;
e205caa7
L		 5975 return size;
5976}
5977
29b0f896 5978static void
64e74474 5979output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5980{
5981 char *p;
5982 unsigned int n;
252b5132 5983
29b0f896
AM		 5984 for (n = 0; n < i.operands; n++)
5985 {
40fb9820 5986 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5987 {
5988 if (i.op[n].disps->X_op == O_constant)
5989 {
e205caa7 5990 int size = disp_size (n);
29b0f896 5991 offsetT val;
252b5132 5992
29b0f896
AM		 5993 val = offset_in_range (i.op[n].disps->X_add_number,
5994 size);
5995 p = frag_more (size);
5996 md_number_to_chars (p, val, size);
5997 }
5998 else
5999 {
f86103b7 6000 enum bfd_reloc_code_real reloc_type;
e205caa7 6001 int size = disp_size (n);
40fb9820 6002 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6003 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6004
e205caa7 6005 /* We can't have 8 bit displacement here. */
9c2799c2 6006 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6007
29b0f896
AM		 6008 /* The PC relative address is computed relative
6009 to the instruction boundary, so in case immediate
6010 fields follows, we need to adjust the value. */
6011 if (pcrel && i.imm_operands)
6012 {
29b0f896 6013 unsigned int n1;
e205caa7 6014 int sz = 0;
252b5132 6015
29b0f896 6016 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6017 if (operand_type_check (i.types[n1], imm))
252b5132 6018 {
e205caa7
L		 6019 /* Only one immediate is allowed for PC
6020 relative address. */
9c2799c2 6021 gas_assert (sz == 0);
e205caa7
L		 6022 sz = imm_size (n1);
6023 i.op[n].disps->X_add_number -= sz;
252b5132 6024 }
29b0f896 6025 /* We should find the immediate. */
9c2799c2 6026 gas_assert (sz != 0);
29b0f896 6027 }
520dc8e8 6028
29b0f896 6029 p = frag_more (size);
2bbd9c25 6030 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6031 if (GOT_symbol
2bbd9c25 6032 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6033 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6034 || reloc_type == BFD_RELOC_X86_64_32S
6035 || (reloc_type == BFD_RELOC_64
6036 && object_64bit))
d6ab8113
JB		 6037 && (i.op[n].disps->X_op == O_symbol
6038 || (i.op[n].disps->X_op == O_add
6039 && ((symbol_get_value_expression
6040 (i.op[n].disps->X_op_symbol)->X_op)
6041 == O_subtract))))
6042 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6043 {
6044 offsetT add;
6045
6046 if (insn_start_frag == frag_now)
6047 add = (p - frag_now->fr_literal) - insn_start_off;
6048 else
6049 {
6050 fragS *fr;
6051
6052 add = insn_start_frag->fr_fix - insn_start_off;
6053 for (fr = insn_start_frag->fr_next;
6054 fr && fr != frag_now; fr = fr->fr_next)
6055 add += fr->fr_fix;
6056 add += p - frag_now->fr_literal;
6057 }
6058
4fa24527 6059 if (!object_64bit)
7b81dfbb
AJ		 6060 {
6061 reloc_type = BFD_RELOC_386_GOTPC;
6062 i.op[n].imms->X_add_number += add;
6063 }
6064 else if (reloc_type == BFD_RELOC_64)
6065 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6066 else
7b81dfbb
AJ		 6067 /* Don't do the adjustment for x86-64, as there
6068 the pcrel addressing is relative to the _next_
6069 insn, and that is taken care of in other code. */
d6ab8113 6070 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6071 }
062cd5e7 6072 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6073 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6074 }
6075 }
6076 }
6077}
252b5132 6078
29b0f896 6079static void
64e74474 6080output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6081{
6082 char *p;
6083 unsigned int n;
252b5132 6084
29b0f896
AM		 6085 for (n = 0; n < i.operands; n++)
6086 {
40fb9820 6087 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6088 {
6089 if (i.op[n].imms->X_op == O_constant)
6090 {
e205caa7 6091 int size = imm_size (n);
29b0f896 6092 offsetT val;
b4cac588 6093
29b0f896
AM		 6094 val = offset_in_range (i.op[n].imms->X_add_number,
6095 size);
6096 p = frag_more (size);
6097 md_number_to_chars (p, val, size);
6098 }
6099 else
6100 {
6101 /* Not absolute_section.
6102 Need a 32-bit fixup (don't support 8bit
6103 non-absolute imms). Try to support other
6104 sizes ... */
f86103b7 6105 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6106 int size = imm_size (n);
6107 int sign;
29b0f896 6108
40fb9820 6109 if (i.types[n].bitfield.imm32s
a7d61044 6110 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6111 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6112 sign = 1;
e205caa7
L		 6113 else
6114 sign = 0;
520dc8e8 6115
29b0f896
AM		 6116 p = frag_more (size);
6117 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6118
2bbd9c25
JJ		 6119 /* This is tough to explain. We end up with this one if we
6120 * have operands that look like
6121 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6122 * obtain the absolute address of the GOT, and it is strongly
6123 * preferable from a performance point of view to avoid using
6124 * a runtime relocation for this. The actual sequence of
6125 * instructions often look something like:
6126 *
6127 * call .L66
6128 * .L66:
6129 * popl %ebx
6130 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6131 *
6132 * The call and pop essentially return the absolute address
6133 * of the label .L66 and store it in %ebx. The linker itself
6134 * will ultimately change the first operand of the addl so
6135 * that %ebx points to the GOT, but to keep things simple, the
6136 * .o file must have this operand set so that it generates not
6137 * the absolute address of .L66, but the absolute address of
6138 * itself. This allows the linker itself simply treat a GOTPC
6139 * relocation as asking for a pcrel offset to the GOT to be
6140 * added in, and the addend of the relocation is stored in the
6141 * operand field for the instruction itself.
6142 *
6143 * Our job here is to fix the operand so that it would add
6144 * the correct offset so that %ebx would point to itself. The
6145 * thing that is tricky is that .-.L66 will point to the
6146 * beginning of the instruction, so we need to further modify
6147 * the operand so that it will point to itself. There are
6148 * other cases where you have something like:
6149 *
6150 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6151 *
6152 * and here no correction would be required. Internally in
6153 * the assembler we treat operands of this form as not being
6154 * pcrel since the '.' is explicitly mentioned, and I wonder
6155 * whether it would simplify matters to do it this way. Who
6156 * knows. In earlier versions of the PIC patches, the
6157 * pcrel_adjust field was used to store the correction, but
6158 * since the expression is not pcrel, I felt it would be
6159 * confusing to do it this way. */
6160
d6ab8113 6161 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6162 || reloc_type == BFD_RELOC_X86_64_32S
6163 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6164 && GOT_symbol
6165 && GOT_symbol == i.op[n].imms->X_add_symbol
6166 && (i.op[n].imms->X_op == O_symbol
6167 || (i.op[n].imms->X_op == O_add
6168 && ((symbol_get_value_expression
6169 (i.op[n].imms->X_op_symbol)->X_op)
6170 == O_subtract))))
6171 {
2bbd9c25
JJ		 6172 offsetT add;
6173
6174 if (insn_start_frag == frag_now)
6175 add = (p - frag_now->fr_literal) - insn_start_off;
6176 else
6177 {
6178 fragS *fr;
6179
6180 add = insn_start_frag->fr_fix - insn_start_off;
6181 for (fr = insn_start_frag->fr_next;
6182 fr && fr != frag_now; fr = fr->fr_next)
6183 add += fr->fr_fix;
6184 add += p - frag_now->fr_literal;
6185 }
6186
4fa24527 6187 if (!object_64bit)
d6ab8113 6188 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6189 else if (size == 4)
d6ab8113 6190 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6191 else if (size == 8)
6192 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6193 i.op[n].imms->X_add_number += add;
29b0f896 6194 }
29b0f896
AM		 6195 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6196 i.op[n].imms, 0, reloc_type);
6197 }
6198 }
6199 }
252b5132
RH		 6200}
6201\f
d182319b
JB		 6202/* x86_cons_fix_new is called via the expression parsing code when a
6203 reloc is needed. We use this hook to get the correct .got reloc. */
6204static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6205static int cons_sign = -1;
6206
6207void
e3bb37b5 6208x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6209 expressionS *exp)
d182319b
JB		 6210{
6211 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6212
6213 got_reloc = NO_RELOC;
6214
6215#ifdef TE_PE
6216 if (exp->X_op == O_secrel)
6217 {
6218 exp->X_op = O_symbol;
6219 r = BFD_RELOC_32_SECREL;
6220 }
6221#endif
6222
6223 fix_new_exp (frag, off, len, exp, 0, r);
6224}
6225
718ddfc0
JB		 6226#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6227# define lex_got(reloc, adjust, types) NULL
6228#else
f3c180ae
AM		 6229/* Parse operands of the form
6230 <symbol>@GOTOFF+<nnn>
6231 and similar .plt or .got references.
6232
6233 If we find one, set up the correct relocation in RELOC and copy the
6234 input string, minus the `@GOTOFF' into a malloc'd buffer for
6235 parsing by the calling routine. Return this buffer, and if ADJUST
6236 is non-null set it to the length of the string we removed from the
6237 input line. Otherwise return NULL. */
6238static char *
91d6fa6a 6239lex_got (enum bfd_reloc_code_real *rel,
64e74474 6240 int *adjust,
40fb9820 6241 i386_operand_type *types)
f3c180ae 6242{
7b81dfbb
AJ		 6243 /* Some of the relocations depend on the size of what field is to
6244 be relocated. But in our callers i386_immediate and i386_displacement
6245 we don't yet know the operand size (this will be set by insn
6246 matching). Hence we record the word32 relocation here,
6247 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6248 static const struct {
6249 const char *str;
4fa24527 6250 const enum bfd_reloc_code_real rel[2];
40fb9820 6251 const i386_operand_type types64;
f3c180ae 6252 } gotrel[] = {
1e9cc1c2 6253 { "PLTOFF", { _dummy_first_bfd_reloc_code_real,
4eed87de 6254 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6255 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6256 { "PLT", { BFD_RELOC_386_PLT32,
6257 BFD_RELOC_X86_64_PLT32 },
40fb9820 6258 OPERAND_TYPE_IMM32_32S_DISP32 },
1e9cc1c2 6259 { "GOTPLT", { _dummy_first_bfd_reloc_code_real,
4eed87de 6260 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6261 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6262 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6263 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6264 OPERAND_TYPE_IMM64_DISP64 },
1e9cc1c2 6265 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real,
4eed87de 6266 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6267 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6268 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6269 BFD_RELOC_X86_64_TLSGD },
40fb9820 6270 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de 6271 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
1e9cc1c2 6272 _dummy_first_bfd_reloc_code_real },
40fb9820 6273 OPERAND_TYPE_NONE },
1e9cc1c2 6274 { "TLSLD", { _dummy_first_bfd_reloc_code_real,
4eed87de 6275 BFD_RELOC_X86_64_TLSLD },
40fb9820 6276 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6277 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6278 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6279 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6280 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6281 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6282 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6283 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
1e9cc1c2 6284 _dummy_first_bfd_reloc_code_real },
40fb9820 6285 OPERAND_TYPE_NONE },
4eed87de
AM		 6286 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6287 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6288
40fb9820 6289 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de 6290 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
1e9cc1c2 6291 _dummy_first_bfd_reloc_code_real },
40fb9820 6292 OPERAND_TYPE_NONE },
4eed87de 6293 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
1e9cc1c2 6294 _dummy_first_bfd_reloc_code_real },
40fb9820 6295 OPERAND_TYPE_NONE },
4eed87de
AM		 6296 { "GOT", { BFD_RELOC_386_GOT32,
6297 BFD_RELOC_X86_64_GOT32 },
40fb9820 6298 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6299 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6300 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6301 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6302 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6303 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6304 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6305 };
6306 char *cp;
6307 unsigned int j;
6308
718ddfc0
JB		 6309 if (!IS_ELF)
6310 return NULL;
6311
f3c180ae 6312 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6313 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6314 return NULL;
6315
47465058 6316 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6317 {
6318 int len;
6319
6320 len = strlen (gotrel[j].str);
28f81592 6321 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6322 {
4fa24527 6323 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6324 {
28f81592
AM		 6325 int first, second;
6326 char *tmpbuf, *past_reloc;
f3c180ae 6327
91d6fa6a 6328 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6329 if (adjust)
6330 *adjust = len;
f3c180ae 6331
3956db08
JB		 6332 if (types)
6333 {
6334 if (flag_code != CODE_64BIT)
40fb9820
L		 6335 {
6336 types->bitfield.imm32 = 1;
6337 types->bitfield.disp32 = 1;
6338 }
3956db08
JB		 6339 else
6340 *types = gotrel[j].types64;
6341 }
6342
f3c180ae
AM		 6343 if (GOT_symbol == NULL)
6344 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6345
28f81592 6346 /* The length of the first part of our input line. */
f3c180ae 6347 first = cp - input_line_pointer;
28f81592
AM		 6348
6349 /* The second part goes from after the reloc token until
67c11a9b 6350 (and including) an end_of_line char or comma. */
28f81592 6351 past_reloc = cp + 1 + len;
67c11a9b
AM		 6352 cp = past_reloc;
6353 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6354 ++cp;
6355 second = cp + 1 - past_reloc;
28f81592
AM		 6356
6357 /* Allocate and copy string. The trailing NUL shouldn't
6358 be necessary, but be safe. */
1e9cc1c2 6359 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6360 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6361 if (second != 0 && *past_reloc != ' ')
6362 /* Replace the relocation token with ' ', so that
6363 errors like foo@GOTOFF1 will be detected. */
6364 tmpbuf[first++] = ' ';
6365 memcpy (tmpbuf + first, past_reloc, second);
6366 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6367 return tmpbuf;
6368 }
6369
4fa24527
JB		 6370 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6371 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6372 return NULL;
6373 }
6374 }
6375
6376 /* Might be a symbol version string. Don't as_bad here. */
6377 return NULL;
6378}
6379
f3c180ae 6380void
e3bb37b5 6381x86_cons (expressionS *exp, int size)
f3c180ae 6382{
ee86248c
JB		 6383 intel_syntax = -intel_syntax;
6384
4fa24527 6385 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6386 {
6387 /* Handle @GOTOFF and the like in an expression. */
6388 char *save;
6389 char *gotfree_input_line;
6390 int adjust;
6391
6392 save = input_line_pointer;
3956db08 6393 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6394 if (gotfree_input_line)
6395 input_line_pointer = gotfree_input_line;
6396
6397 expression (exp);
6398
6399 if (gotfree_input_line)
6400 {
6401 /* expression () has merrily parsed up to the end of line,
6402 or a comma - in the wrong buffer. Transfer how far
6403 input_line_pointer has moved to the right buffer. */
6404 input_line_pointer = (save
6405 + (input_line_pointer - gotfree_input_line)
6406 + adjust);
6407 free (gotfree_input_line);
3992d3b7
AM		 6408 if (exp->X_op == O_constant
6409 || exp->X_op == O_absent
6410 || exp->X_op == O_illegal
6411 || exp->X_op == O_register
6412 || exp->X_op == O_big)
6413 {
6414 char c = *input_line_pointer;
6415 *input_line_pointer = 0;
6416 as_bad (_("missing or invalid expression `%s'"), save);
6417 *input_line_pointer = c;
6418 }
f3c180ae
AM		 6419 }
6420 }
6421 else
6422 expression (exp);
ee86248c
JB		 6423
6424 intel_syntax = -intel_syntax;
6425
6426 if (intel_syntax)
6427 i386_intel_simplify (exp);
f3c180ae
AM		 6428}
6429#endif
6430
9f32dd5b
L		 6431static void
6432signed_cons (int size)
6482c264 6433{
d182319b
JB		 6434 if (flag_code == CODE_64BIT)
6435 cons_sign = 1;
6436 cons (size);
6437 cons_sign = -1;
6482c264
NC		 6438}
6439
d182319b 6440#ifdef TE_PE
6482c264
NC		 6441static void
6442pe_directive_secrel (dummy)
6443 int dummy ATTRIBUTE_UNUSED;
6444{
6445 expressionS exp;
6446
6447 do
6448 {
6449 expression (&exp);
6450 if (exp.X_op == O_symbol)
6451 exp.X_op = O_secrel;
6452
6453 emit_expr (&exp, 4);
6454 }
6455 while (*input_line_pointer++ == ',');
6456
6457 input_line_pointer--;
6458 demand_empty_rest_of_line ();
6459}
6482c264
NC		 6460#endif
6461
252b5132 6462static int
70e41ade 6463i386_immediate (char *imm_start)
252b5132
RH		 6464{
6465 char *save_input_line_pointer;
f3c180ae 6466 char *gotfree_input_line;
252b5132 6467 segT exp_seg = 0;
47926f60 6468 expressionS *exp;
40fb9820
L		 6469 i386_operand_type types;
6470
0dfbf9d7 6471 operand_type_set (&types, ~0);
252b5132
RH		 6472
6473 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6474 {
31b2323c
L		 6475 as_bad (_("at most %d immediate operands are allowed"),
6476 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6477 return 0;
6478 }
6479
6480 exp = &im_expressions[i.imm_operands++];
520dc8e8 6481 i.op[this_operand].imms = exp;
252b5132
RH		 6482
6483 if (is_space_char (*imm_start))
6484 ++imm_start;
6485
6486 save_input_line_pointer = input_line_pointer;
6487 input_line_pointer = imm_start;
6488
3956db08 6489 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6490 if (gotfree_input_line)
6491 input_line_pointer = gotfree_input_line;
252b5132
RH		 6492
6493 exp_seg = expression (exp);
6494
83183c0c 6495 SKIP_WHITESPACE ();
252b5132 6496 if (*input_line_pointer)
f3c180ae 6497 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6498
6499 input_line_pointer = save_input_line_pointer;
f3c180ae 6500 if (gotfree_input_line)
ee86248c
JB		 6501 {
6502 free (gotfree_input_line);
6503
6504 if (exp->X_op == O_constant || exp->X_op == O_register)
6505 exp->X_op = O_illegal;
6506 }
6507
6508 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6509}
252b5132 6510
ee86248c
JB		 6511static int
6512i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6513 i386_operand_type types, const char *imm_start)
6514{
6515 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6516 {
313c53d1
L		 6517 if (imm_start)
6518 as_bad (_("missing or invalid immediate expression `%s'"),
6519 imm_start);
3992d3b7 6520 return 0;
252b5132 6521 }
3e73aa7c 6522 else if (exp->X_op == O_constant)
252b5132 6523 {
47926f60 6524 /* Size it properly later. */
40fb9820 6525 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6526 /* If BFD64, sign extend val. */
4eed87de
AM		 6527 if (!use_rela_relocations
6528 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6529 exp->X_add_number
6530 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6531 }
4c63da97 6532#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6533 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6534 && exp_seg != absolute_section
47926f60 6535 && exp_seg != text_section
24eab124
AM		 6536 && exp_seg != data_section
6537 && exp_seg != bss_section
6538 && exp_seg != undefined_section
f86103b7 6539 && !bfd_is_com_section (exp_seg))
252b5132 6540 {
d0b47220 6541 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6542 return 0;
6543 }
6544#endif
bb8f5920
L		 6545 else if (!intel_syntax && exp->X_op == O_register)
6546 {
313c53d1
L		 6547 if (imm_start)
6548 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6549 return 0;
6550 }
252b5132
RH		 6551 else
6552 {
6553 /* This is an address. The size of the address will be
24eab124 6554 determined later, depending on destination register,
3e73aa7c 6555 suffix, or the default for the section. */
40fb9820
L		 6556 i.types[this_operand].bitfield.imm8 = 1;
6557 i.types[this_operand].bitfield.imm16 = 1;
6558 i.types[this_operand].bitfield.imm32 = 1;
6559 i.types[this_operand].bitfield.imm32s = 1;
6560 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6561 i.types[this_operand] = operand_type_and (i.types[this_operand],
6562 types);
252b5132
RH		 6563 }
6564
6565 return 1;
6566}
6567
551c1ca1 6568static char *
e3bb37b5 6569i386_scale (char *scale)
252b5132 6570{
551c1ca1
AM		 6571 offsetT val;
6572 char *save = input_line_pointer;
252b5132 6573
551c1ca1
AM		 6574 input_line_pointer = scale;
6575 val = get_absolute_expression ();
6576
6577 switch (val)
252b5132 6578 {
551c1ca1 6579 case 1:
252b5132
RH		 6580 i.log2_scale_factor = 0;
6581 break;
551c1ca1 6582 case 2:
252b5132
RH		 6583 i.log2_scale_factor = 1;
6584 break;
551c1ca1 6585 case 4:
252b5132
RH		 6586 i.log2_scale_factor = 2;
6587 break;
551c1ca1 6588 case 8:
252b5132
RH		 6589 i.log2_scale_factor = 3;
6590 break;
6591 default:
a724f0f4
JB		 6592 {
6593 char sep = *input_line_pointer;
6594
6595 *input_line_pointer = '\0';
6596 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6597 scale);
6598 *input_line_pointer = sep;
6599 input_line_pointer = save;
6600 return NULL;
6601 }
252b5132 6602 }
29b0f896 6603 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6604 {
6605 as_warn (_("scale factor of %d without an index register"),
24eab124 6606 1 << i.log2_scale_factor);
252b5132 6607 i.log2_scale_factor = 0;
252b5132 6608 }
551c1ca1
AM		 6609 scale = input_line_pointer;
6610 input_line_pointer = save;
6611 return scale;
252b5132
RH		 6612}
6613
252b5132 6614static int
e3bb37b5 6615i386_displacement (char *disp_start, char *disp_end)
252b5132 6616{
29b0f896 6617 expressionS *exp;
252b5132
RH		 6618 segT exp_seg = 0;
6619 char *save_input_line_pointer;
f3c180ae 6620 char *gotfree_input_line;
40fb9820
L		 6621 int override;
6622 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6623 int ret;
252b5132 6624
31b2323c
L		 6625 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6626 {
6627 as_bad (_("at most %d displacement operands are allowed"),
6628 MAX_MEMORY_OPERANDS);
6629 return 0;
6630 }
6631
0dfbf9d7 6632 operand_type_set (&bigdisp, 0);
40fb9820
L		 6633 if ((i.types[this_operand].bitfield.jumpabsolute)
6634 || (!current_templates->start->opcode_modifier.jump
6635 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6636 {
40fb9820 6637 bigdisp.bitfield.disp32 = 1;
e05278af 6638 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6639 if (flag_code == CODE_64BIT)
6640 {
6641 if (!override)
6642 {
6643 bigdisp.bitfield.disp32s = 1;
6644 bigdisp.bitfield.disp64 = 1;
6645 }
6646 }
6647 else if ((flag_code == CODE_16BIT) ^ override)
6648 {
6649 bigdisp.bitfield.disp32 = 0;
6650 bigdisp.bitfield.disp16 = 1;
6651 }
e05278af
JB		 6652 }
6653 else
6654 {
6655 /* For PC-relative branches, the width of the displacement
6656 is dependent upon data size, not address size. */
e05278af 6657 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6658 if (flag_code == CODE_64BIT)
6659 {
6660 if (override || i.suffix == WORD_MNEM_SUFFIX)
6661 bigdisp.bitfield.disp16 = 1;
6662 else
6663 {
6664 bigdisp.bitfield.disp32 = 1;
6665 bigdisp.bitfield.disp32s = 1;
6666 }
6667 }
6668 else
e05278af
JB		 6669 {
6670 if (!override)
6671 override = (i.suffix == (flag_code != CODE_16BIT
6672 ? WORD_MNEM_SUFFIX
6673 : LONG_MNEM_SUFFIX));
40fb9820
L		 6674 bigdisp.bitfield.disp32 = 1;
6675 if ((flag_code == CODE_16BIT) ^ override)
6676 {
6677 bigdisp.bitfield.disp32 = 0;
6678 bigdisp.bitfield.disp16 = 1;
6679 }
e05278af 6680 }
e05278af 6681 }
c6fb90c8
L		 6682 i.types[this_operand] = operand_type_or (i.types[this_operand],
6683 bigdisp);
252b5132
RH		 6684
6685 exp = &disp_expressions[i.disp_operands];
520dc8e8 6686 i.op[this_operand].disps = exp;
252b5132
RH		 6687 i.disp_operands++;
6688 save_input_line_pointer = input_line_pointer;
6689 input_line_pointer = disp_start;
6690 END_STRING_AND_SAVE (disp_end);
6691
6692#ifndef GCC_ASM_O_HACK
6693#define GCC_ASM_O_HACK 0
6694#endif
6695#if GCC_ASM_O_HACK
6696 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6697 if (i.types[this_operand].bitfield.baseIndex
24eab124 6698 && displacement_string_end[-1] == '+')
252b5132
RH		 6699 {
6700 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6701 constraint within gcc asm statements.
6702 For instance:
6703
6704 #define _set_tssldt_desc(n,addr,limit,type) \
6705 __asm__ __volatile__ ( \
6706 "movw %w2,%0\n\t" \
6707 "movw %w1,2+%0\n\t" \
6708 "rorl $16,%1\n\t" \
6709 "movb %b1,4+%0\n\t" \
6710 "movb %4,5+%0\n\t" \
6711 "movb $0,6+%0\n\t" \
6712 "movb %h1,7+%0\n\t" \
6713 "rorl $16,%1" \
6714 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6715
6716 This works great except that the output assembler ends
6717 up looking a bit weird if it turns out that there is
6718 no offset. You end up producing code that looks like:
6719
6720 #APP
6721 movw $235,(%eax)
6722 movw %dx,2+(%eax)
6723 rorl $16,%edx
6724 movb %dl,4+(%eax)
6725 movb $137,5+(%eax)
6726 movb $0,6+(%eax)
6727 movb %dh,7+(%eax)
6728 rorl $16,%edx
6729 #NO_APP
6730
47926f60 6731 So here we provide the missing zero. */
24eab124
AM		 6732
6733 *displacement_string_end = '0';
252b5132
RH		 6734 }
6735#endif
3956db08 6736 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6737 if (gotfree_input_line)
6738 input_line_pointer = gotfree_input_line;
252b5132 6739
24eab124 6740 exp_seg = expression (exp);
252b5132 6741
636c26b0
AM		 6742 SKIP_WHITESPACE ();
6743 if (*input_line_pointer)
6744 as_bad (_("junk `%s' after expression"), input_line_pointer);
6745#if GCC_ASM_O_HACK
6746 RESTORE_END_STRING (disp_end + 1);
6747#endif
636c26b0 6748 input_line_pointer = save_input_line_pointer;
636c26b0 6749 if (gotfree_input_line)
ee86248c
JB		 6750 {
6751 free (gotfree_input_line);
6752
6753 if (exp->X_op == O_constant || exp->X_op == O_register)
6754 exp->X_op = O_illegal;
6755 }
6756
6757 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6758
6759 RESTORE_END_STRING (disp_end);
6760
6761 return ret;
6762}
6763
6764static int
6765i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6766 i386_operand_type types, const char *disp_start)
6767{
6768 i386_operand_type bigdisp;
6769 int ret = 1;
636c26b0 6770
24eab124
AM		 6771 /* We do this to make sure that the section symbol is in
6772 the symbol table. We will ultimately change the relocation
47926f60 6773 to be relative to the beginning of the section. */
1ae12ab7 6774 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6775 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6776 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6777 {
636c26b0 6778 if (exp->X_op != O_symbol)
3992d3b7 6779 goto inv_disp;
636c26b0 6780
e5cb08ac 6781 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6782 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6783 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6784 exp->X_op = O_subtract;
6785 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6786 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6787 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6788 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6789 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6790 else
29b0f896 6791 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6792 }
252b5132 6793
3992d3b7
AM		 6794 else if (exp->X_op == O_absent
6795 || exp->X_op == O_illegal
ee86248c 6796 || exp->X_op == O_big)
2daf4fd8 6797 {
3992d3b7
AM		 6798 inv_disp:
6799 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6800 disp_start);
3992d3b7 6801 ret = 0;
2daf4fd8
AM		 6802 }
6803
0e1147d9
L		 6804 else if (flag_code == CODE_64BIT
6805 && !i.prefix[ADDR_PREFIX]
6806 && exp->X_op == O_constant)
6807 {
6808 /* Since displacement is signed extended to 64bit, don't allow
6809 disp32 and turn off disp32s if they are out of range. */
6810 i.types[this_operand].bitfield.disp32 = 0;
6811 if (!fits_in_signed_long (exp->X_add_number))
6812 {
6813 i.types[this_operand].bitfield.disp32s = 0;
6814 if (i.types[this_operand].bitfield.baseindex)
6815 {
6816 as_bad (_("0x%lx out range of signed 32bit displacement"),
6817 (long) exp->X_add_number);
6818 ret = 0;
6819 }
6820 }
6821 }
6822
4c63da97 6823#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6824 else if (exp->X_op != O_constant
6825 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6826 && exp_seg != absolute_section
6827 && exp_seg != text_section
6828 && exp_seg != data_section
6829 && exp_seg != bss_section
6830 && exp_seg != undefined_section
6831 && !bfd_is_com_section (exp_seg))
24eab124 6832 {
d0b47220 6833 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6834 ret = 0;
24eab124 6835 }
252b5132 6836#endif
3956db08 6837
40fb9820
L		 6838 /* Check if this is a displacement only operand. */
6839 bigdisp = i.types[this_operand];
6840 bigdisp.bitfield.disp8 = 0;
6841 bigdisp.bitfield.disp16 = 0;
6842 bigdisp.bitfield.disp32 = 0;
6843 bigdisp.bitfield.disp32s = 0;
6844 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6845 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6846 i.types[this_operand] = operand_type_and (i.types[this_operand],
6847 types);
3956db08 6848
3992d3b7 6849 return ret;
252b5132
RH		 6850}
6851
eecb386c 6852/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6853 Return 1 on success, 0 on a failure. */
6854
252b5132 6855static int
e3bb37b5 6856i386_index_check (const char *operand_string)
252b5132 6857{
3e73aa7c 6858 int ok;
fc0763e6 6859 const char *kind = "base/index";
24eab124 6860#if INFER_ADDR_PREFIX
eecb386c
AM		 6861 int fudged = 0;
6862
24eab124
AM		 6863 tryprefix:
6864#endif
3e73aa7c 6865 ok = 1;
fc0763e6
JB		 6866 if (current_templates->start->opcode_modifier.isstring
6867 && !current_templates->start->opcode_modifier.immext
6868 && (current_templates->end[-1].opcode_modifier.isstring
6869 || i.mem_operands))
6870 {
6871 /* Memory operands of string insns are special in that they only allow
6872 a single register (rDI, rSI, or rBX) as their memory address. */
6873 unsigned int expected;
6874
6875 kind = "string address";
6876
6877 if (current_templates->start->opcode_modifier.w)
6878 {
6879 i386_operand_type type = current_templates->end[-1].operand_types[0];
6880
6881 if (!type.bitfield.baseindex
6882 || ((!i.mem_operands != !intel_syntax)
6883 && current_templates->end[-1].operand_types[1]
6884 .bitfield.baseindex))
6885 type = current_templates->end[-1].operand_types[1];
6886 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6887 }
6888 else
6889 expected = 3 /* rBX */;
6890
6891 if (!i.base_reg || i.index_reg
6892 || operand_type_check (i.types[this_operand], disp))
6893 ok = -1;
6894 else if (!(flag_code == CODE_64BIT
6895 ? i.prefix[ADDR_PREFIX]
6896 ? i.base_reg->reg_type.bitfield.reg32
6897 : i.base_reg->reg_type.bitfield.reg64
6898 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6899 ? i.base_reg->reg_type.bitfield.reg32
6900 : i.base_reg->reg_type.bitfield.reg16))
6901 ok = 0;
6902 else if (i.base_reg->reg_num != expected)
6903 ok = -1;
6904
6905 if (ok < 0)
6906 {
6907 unsigned int j;
6908
6909 for (j = 0; j < i386_regtab_size; ++j)
6910 if ((flag_code == CODE_64BIT
6911 ? i.prefix[ADDR_PREFIX]
6912 ? i386_regtab[j].reg_type.bitfield.reg32
6913 : i386_regtab[j].reg_type.bitfield.reg64
6914 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6915 ? i386_regtab[j].reg_type.bitfield.reg32
6916 : i386_regtab[j].reg_type.bitfield.reg16)
6917 && i386_regtab[j].reg_num == expected)
6918 break;
9c2799c2 6919 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6920 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6921 operand_string,
6922 intel_syntax ? '[' : '(',
6923 register_prefix,
6924 i386_regtab[j].reg_name,
6925 intel_syntax ? ']' : ')');
6926 ok = 1;
6927 }
6928 }
6929 else if (flag_code == CODE_64BIT)
64e74474 6930 {
64e74474 6931 if ((i.base_reg
40fb9820
L		 6932 && ((i.prefix[ADDR_PREFIX] == 0
6933 && !i.base_reg->reg_type.bitfield.reg64)
6934 || (i.prefix[ADDR_PREFIX]
6935 && !i.base_reg->reg_type.bitfield.reg32))
6936 && (i.index_reg
9a04903e
JB		 6937 || i.base_reg->reg_num !=
6938 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6939 || (i.index_reg
40fb9820
L		 6940 && (!i.index_reg->reg_type.bitfield.baseindex
6941 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6942 && i.index_reg->reg_num != RegRiz
6943 && !i.index_reg->reg_type.bitfield.reg64
6944 )
40fb9820 6945 || (i.prefix[ADDR_PREFIX]
db51cc60 6946 && i.index_reg->reg_num != RegEiz
40fb9820 6947 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6948 ok = 0;
3e73aa7c
JH		 6949 }
6950 else
6951 {
6952 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6953 {
6954 /* 16bit checks. */
6955 if ((i.base_reg
40fb9820
L		 6956 && (!i.base_reg->reg_type.bitfield.reg16
6957 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6958 || (i.index_reg
40fb9820
L		 6959 && (!i.index_reg->reg_type.bitfield.reg16
6960 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6961 || !(i.base_reg
6962 && i.base_reg->reg_num < 6
6963 && i.index_reg->reg_num >= 6
6964 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6965 ok = 0;
6966 }
6967 else
e5cb08ac 6968 {
3e73aa7c
JH		 6969 /* 32bit checks. */
6970 if ((i.base_reg
40fb9820 6971 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6972 || (i.index_reg
db51cc60
L		 6973 && ((!i.index_reg->reg_type.bitfield.reg32
6974 && i.index_reg->reg_num != RegEiz)
40fb9820 6975 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6976 ok = 0;
3e73aa7c
JH		 6977 }
6978 }
6979 if (!ok)
24eab124
AM		 6980 {
6981#if INFER_ADDR_PREFIX
fc0763e6 6982 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6983 {
6984 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6985 i.prefixes += 1;
b23bac36
AM		 6986 /* Change the size of any displacement too. At most one of
6987 Disp16 or Disp32 is set.
6988 FIXME. There doesn't seem to be any real need for separate
6989 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6990 Removing them would probably clean up the code quite a lot. */
4eed87de 6991 if (flag_code != CODE_64BIT
40fb9820
L		 6992 && (i.types[this_operand].bitfield.disp16
6993 || i.types[this_operand].bitfield.disp32))
6994 i.types[this_operand]
c6fb90c8 6995 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6996 fudged = 1;
24eab124
AM		 6997 goto tryprefix;
6998 }
eecb386c 6999 if (fudged)
fc0763e6
JB		 7000 as_bad (_("`%s' is not a valid %s expression"),
7001 operand_string,
7002 kind);
eecb386c 7003 else
c388dee8 7004#endif
fc0763e6 7005 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7006 operand_string,
fc0763e6
JB		 7007 flag_code_names[i.prefix[ADDR_PREFIX]
7008 ? flag_code == CODE_32BIT
7009 ? CODE_16BIT
7010 : CODE_32BIT
7011 : flag_code],
7012 kind);
24eab124 7013 }
20f0a1fc 7014 return ok;
24eab124 7015}
252b5132 7016
fc0763e6 7017/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7018 on error. */
252b5132 7019
252b5132 7020static int
a7619375 7021i386_att_operand (char *operand_string)
252b5132 7022{
af6bdddf
AM		 7023 const reg_entry *r;
7024 char *end_op;
24eab124 7025 char *op_string = operand_string;
252b5132 7026
24eab124 7027 if (is_space_char (*op_string))
252b5132
RH		 7028 ++op_string;
7029
24eab124 7030 /* We check for an absolute prefix (differentiating,
47926f60 7031 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7032 if (*op_string == ABSOLUTE_PREFIX)
7033 {
7034 ++op_string;
7035 if (is_space_char (*op_string))
7036 ++op_string;
40fb9820 7037 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7038 }
252b5132 7039
47926f60 7040 /* Check if operand is a register. */
4d1bb795 7041 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7042 {
40fb9820
L		 7043 i386_operand_type temp;
7044
24eab124
AM		 7045 /* Check for a segment override by searching for ':' after a
7046 segment register. */
7047 op_string = end_op;
7048 if (is_space_char (*op_string))
7049 ++op_string;
40fb9820
L		 7050 if (*op_string == ':'
7051 && (r->reg_type.bitfield.sreg2
7052 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7053 {
7054 switch (r->reg_num)
7055 {
7056 case 0:
7057 i.seg[i.mem_operands] = &es;
7058 break;
7059 case 1:
7060 i.seg[i.mem_operands] = &cs;
7061 break;
7062 case 2:
7063 i.seg[i.mem_operands] = &ss;
7064 break;
7065 case 3:
7066 i.seg[i.mem_operands] = &ds;
7067 break;
7068 case 4:
7069 i.seg[i.mem_operands] = &fs;
7070 break;
7071 case 5:
7072 i.seg[i.mem_operands] = &gs;
7073 break;
7074 }
252b5132 7075
24eab124 7076 /* Skip the ':' and whitespace. */
252b5132
RH		 7077 ++op_string;
7078 if (is_space_char (*op_string))
24eab124 7079 ++op_string;
252b5132 7080
24eab124
AM		 7081 if (!is_digit_char (*op_string)
7082 && !is_identifier_char (*op_string)
7083 && *op_string != '('
7084 && *op_string != ABSOLUTE_PREFIX)
7085 {
7086 as_bad (_("bad memory operand `%s'"), op_string);
7087 return 0;
7088 }
47926f60 7089 /* Handle case of %es:*foo. */
24eab124
AM		 7090 if (*op_string == ABSOLUTE_PREFIX)
7091 {
7092 ++op_string;
7093 if (is_space_char (*op_string))
7094 ++op_string;
40fb9820 7095 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7096 }
7097 goto do_memory_reference;
7098 }
7099 if (*op_string)
7100 {
d0b47220 7101 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7102 return 0;
7103 }
40fb9820
L		 7104 temp = r->reg_type;
7105 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7106 i.types[this_operand] = operand_type_or (i.types[this_operand],
7107 temp);
7d5e4556 7108 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7109 i.op[this_operand].regs = r;
24eab124
AM		 7110 i.reg_operands++;
7111 }
af6bdddf
AM		 7112 else if (*op_string == REGISTER_PREFIX)
7113 {
7114 as_bad (_("bad register name `%s'"), op_string);
7115 return 0;
7116 }
24eab124 7117 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7118 {
24eab124 7119 ++op_string;
40fb9820 7120 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7121 {
d0b47220 7122 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7123 return 0;
7124 }
7125 if (!i386_immediate (op_string))
7126 return 0;
7127 }
7128 else if (is_digit_char (*op_string)
7129 || is_identifier_char (*op_string)
e5cb08ac 7130 || *op_string == '(')
24eab124 7131 {
47926f60 7132 /* This is a memory reference of some sort. */
af6bdddf 7133 char *base_string;
252b5132 7134
47926f60 7135 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7136 char *displacement_string_start;
7137 char *displacement_string_end;
252b5132 7138
24eab124 7139 do_memory_reference:
24eab124 7140 if ((i.mem_operands == 1
40fb9820 7141 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7142 || i.mem_operands == 2)
7143 {
7144 as_bad (_("too many memory references for `%s'"),
7145 current_templates->start->name);
7146 return 0;
7147 }
252b5132 7148
24eab124
AM		 7149 /* Check for base index form. We detect the base index form by
7150 looking for an ')' at the end of the operand, searching
7151 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7152 after the '('. */
af6bdddf 7153 base_string = op_string + strlen (op_string);
c3332e24 7154
af6bdddf
AM		 7155 --base_string;
7156 if (is_space_char (*base_string))
7157 --base_string;
252b5132 7158
47926f60 7159 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7160 displacement_string_start = op_string;
7161 displacement_string_end = base_string + 1;
252b5132 7162
24eab124
AM		 7163 if (*base_string == ')')
7164 {
af6bdddf 7165 char *temp_string;
24eab124
AM		 7166 unsigned int parens_balanced = 1;
7167 /* We've already checked that the number of left & right ()'s are
47926f60 7168 equal, so this loop will not be infinite. */
24eab124
AM		 7169 do
7170 {
7171 base_string--;
7172 if (*base_string == ')')
7173 parens_balanced++;
7174 if (*base_string == '(')
7175 parens_balanced--;
7176 }
7177 while (parens_balanced);
c3332e24 7178
af6bdddf 7179 temp_string = base_string;
c3332e24 7180
24eab124 7181 /* Skip past '(' and whitespace. */
252b5132
RH		 7182 ++base_string;
7183 if (is_space_char (*base_string))
24eab124 7184 ++base_string;
252b5132 7185
af6bdddf 7186 if (*base_string == ','
4eed87de
AM		 7187 || ((i.base_reg = parse_register (base_string, &end_op))
7188 != NULL))
252b5132 7189 {
af6bdddf 7190 displacement_string_end = temp_string;
252b5132 7191
40fb9820 7192 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7193
af6bdddf 7194 if (i.base_reg)
24eab124 7195 {
24eab124
AM		 7196 base_string = end_op;
7197 if (is_space_char (*base_string))
7198 ++base_string;
af6bdddf
AM		 7199 }
7200
7201 /* There may be an index reg or scale factor here. */
7202 if (*base_string == ',')
7203 {
7204 ++base_string;
7205 if (is_space_char (*base_string))
7206 ++base_string;
7207
4eed87de
AM		 7208 if ((i.index_reg = parse_register (base_string, &end_op))
7209 != NULL)
24eab124 7210 {
af6bdddf 7211 base_string = end_op;
24eab124
AM		 7212 if (is_space_char (*base_string))
7213 ++base_string;
af6bdddf
AM		 7214 if (*base_string == ',')
7215 {
7216 ++base_string;
7217 if (is_space_char (*base_string))
7218 ++base_string;
7219 }
e5cb08ac 7220 else if (*base_string != ')')
af6bdddf 7221 {
4eed87de
AM		 7222 as_bad (_("expecting `,' or `)' "
7223 "after index register in `%s'"),
af6bdddf
AM		 7224 operand_string);
7225 return 0;
7226 }
24eab124 7227 }
af6bdddf 7228 else if (*base_string == REGISTER_PREFIX)
24eab124 7229 {
af6bdddf 7230 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7231 return 0;
7232 }
252b5132 7233
47926f60 7234 /* Check for scale factor. */
551c1ca1 7235 if (*base_string != ')')
af6bdddf 7236 {
551c1ca1
AM		 7237 char *end_scale = i386_scale (base_string);
7238
7239 if (!end_scale)
af6bdddf 7240 return 0;
24eab124 7241
551c1ca1 7242 base_string = end_scale;
af6bdddf
AM		 7243 if (is_space_char (*base_string))
7244 ++base_string;
7245 if (*base_string != ')')
7246 {
4eed87de
AM		 7247 as_bad (_("expecting `)' "
7248 "after scale factor in `%s'"),
af6bdddf
AM		 7249 operand_string);
7250 return 0;
7251 }
7252 }
7253 else if (!i.index_reg)
24eab124 7254 {
4eed87de
AM		 7255 as_bad (_("expecting index register or scale factor "
7256 "after `,'; got '%c'"),
af6bdddf 7257 *base_string);
24eab124
AM		 7258 return 0;
7259 }
7260 }
af6bdddf 7261 else if (*base_string != ')')
24eab124 7262 {
4eed87de
AM		 7263 as_bad (_("expecting `,' or `)' "
7264 "after base register in `%s'"),
af6bdddf 7265 operand_string);
24eab124
AM		 7266 return 0;
7267 }
c3332e24 7268 }
af6bdddf 7269 else if (*base_string == REGISTER_PREFIX)
c3332e24 7270 {
af6bdddf 7271 as_bad (_("bad register name `%s'"), base_string);
24eab124 7272 return 0;
c3332e24 7273 }
24eab124
AM		 7274 }
7275
7276 /* If there's an expression beginning the operand, parse it,
7277 assuming displacement_string_start and
7278 displacement_string_end are meaningful. */
7279 if (displacement_string_start != displacement_string_end)
7280 {
7281 if (!i386_displacement (displacement_string_start,
7282 displacement_string_end))
7283 return 0;
7284 }
7285
7286 /* Special case for (%dx) while doing input/output op. */
7287 if (i.base_reg
0dfbf9d7
L		 7288 && operand_type_equal (&i.base_reg->reg_type,
7289 &reg16_inoutportreg)
24eab124
AM		 7290 && i.index_reg == 0
7291 && i.log2_scale_factor == 0
7292 && i.seg[i.mem_operands] == 0
40fb9820 7293 && !operand_type_check (i.types[this_operand], disp))
24eab124 7294 {
65da13b5 7295 i.types[this_operand] = inoutportreg;
24eab124
AM		 7296 return 1;
7297 }
7298
eecb386c
AM		 7299 if (i386_index_check (operand_string) == 0)
7300 return 0;
5c07affc 7301 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7302 i.mem_operands++;
7303 }
7304 else
ce8a8b2f
AM		 7305 {
7306 /* It's not a memory operand; argh! */
24eab124
AM		 7307 as_bad (_("invalid char %s beginning operand %d `%s'"),
7308 output_invalid (*op_string),
7309 this_operand + 1,
7310 op_string);
7311 return 0;
7312 }
47926f60 7313 return 1; /* Normal return. */
252b5132
RH		 7314}
7315\f
ee7fcc42
AM		 7316/* md_estimate_size_before_relax()
7317
7318 Called just before relax() for rs_machine_dependent frags. The x86
7319 assembler uses these frags to handle variable size jump
7320 instructions.
7321
7322 Any symbol that is now undefined will not become defined.
7323 Return the correct fr_subtype in the frag.
7324 Return the initial "guess for variable size of frag" to caller.
7325 The guess is actually the growth beyond the fixed part. Whatever
7326 we do to grow the fixed or variable part contributes to our
7327 returned value. */
7328
252b5132
RH		 7329int
7330md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7331 fragS *fragP;
7332 segT segment;
252b5132 7333{
252b5132 7334 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7335 check for un-relaxable symbols. On an ELF system, we can't relax
7336 an externally visible symbol, because it may be overridden by a
7337 shared library. */
7338 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7339#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7340 || (IS_ELF
31312f95 7341 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7342 || S_IS_WEAK (fragP->fr_symbol)
7343 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7344 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7345#endif
7346#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7347 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7348 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7349#endif
7350 )
252b5132 7351 {
b98ef147
AM		 7352 /* Symbol is undefined in this segment, or we need to keep a
7353 reloc so that weak symbols can be overridden. */
7354 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7355 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7356 unsigned char *opcode;
7357 int old_fr_fix;
f6af82bd 7358
ee7fcc42 7359 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7360 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7361 else if (size == 2)
f6af82bd
AM		 7362 reloc_type = BFD_RELOC_16_PCREL;
7363 else
7364 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7365
ee7fcc42
AM		 7366 old_fr_fix = fragP->fr_fix;
7367 opcode = (unsigned char *) fragP->fr_opcode;
7368
fddf5b5b 7369 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7370 {
fddf5b5b
AM		 7371 case UNCOND_JUMP:
7372 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7373 opcode[0] = 0xe9;
252b5132 7374 fragP->fr_fix += size;
062cd5e7
AS		 7375 fix_new (fragP, old_fr_fix, size,
7376 fragP->fr_symbol,
7377 fragP->fr_offset, 1,
7378 reloc_type);
252b5132
RH		 7379 break;
7380
fddf5b5b 7381 case COND_JUMP86:
412167cb
AM		 7382 if (size == 2
7383 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7384 {
7385 /* Negate the condition, and branch past an
7386 unconditional jump. */
7387 opcode[0] ^= 1;
7388 opcode[1] = 3;
7389 /* Insert an unconditional jump. */
7390 opcode[2] = 0xe9;
7391 /* We added two extra opcode bytes, and have a two byte
7392 offset. */
7393 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7394 fix_new (fragP, old_fr_fix + 2, 2,
7395 fragP->fr_symbol,
7396 fragP->fr_offset, 1,
7397 reloc_type);
fddf5b5b
AM		 7398 break;
7399 }
7400 /* Fall through. */
7401
7402 case COND_JUMP:
412167cb
AM		 7403 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7404 {
3e02c1cc
AM		 7405 fixS *fixP;
7406
412167cb 7407 fragP->fr_fix += 1;
3e02c1cc
AM		 7408 fixP = fix_new (fragP, old_fr_fix, 1,
7409 fragP->fr_symbol,
7410 fragP->fr_offset, 1,
7411 BFD_RELOC_8_PCREL);
7412 fixP->fx_signed = 1;
412167cb
AM		 7413 break;
7414 }
93c2a809 7415
24eab124 7416 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7417 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7418 opcode[1] = opcode[0] + 0x10;
f6af82bd 7419 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7420 /* We've added an opcode byte. */
7421 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7422 fix_new (fragP, old_fr_fix + 1, size,
7423 fragP->fr_symbol,
7424 fragP->fr_offset, 1,
7425 reloc_type);
252b5132 7426 break;
fddf5b5b
AM		 7427
7428 default:
7429 BAD_CASE (fragP->fr_subtype);
7430 break;
252b5132
RH		 7431 }
7432 frag_wane (fragP);
ee7fcc42 7433 return fragP->fr_fix - old_fr_fix;
252b5132 7434 }
93c2a809 7435
93c2a809
AM		 7436 /* Guess size depending on current relax state. Initially the relax
7437 state will correspond to a short jump and we return 1, because
7438 the variable part of the frag (the branch offset) is one byte
7439 long. However, we can relax a section more than once and in that
7440 case we must either set fr_subtype back to the unrelaxed state,
7441 or return the value for the appropriate branch. */
7442 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7443}
7444
47926f60
KH		 7445/* Called after relax() is finished.
7446
7447 In: Address of frag.
7448 fr_type == rs_machine_dependent.
7449 fr_subtype is what the address relaxed to.
7450
7451 Out: Any fixSs and constants are set up.
7452 Caller will turn frag into a ".space 0". */
7453
252b5132
RH		 7454void
7455md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7456 bfd *abfd ATTRIBUTE_UNUSED;
7457 segT sec ATTRIBUTE_UNUSED;
29b0f896 7458 fragS *fragP;
252b5132 7459{
29b0f896 7460 unsigned char *opcode;
252b5132 7461 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7462 offsetT target_address;
7463 offsetT opcode_address;
252b5132 7464 unsigned int extension = 0;
847f7ad4 7465 offsetT displacement_from_opcode_start;
252b5132
RH		 7466
7467 opcode = (unsigned char *) fragP->fr_opcode;
7468
47926f60 7469 /* Address we want to reach in file space. */
252b5132 7470 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7471
47926f60 7472 /* Address opcode resides at in file space. */
252b5132
RH		 7473 opcode_address = fragP->fr_address + fragP->fr_fix;
7474
47926f60 7475 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7476 displacement_from_opcode_start = target_address - opcode_address;
7477
fddf5b5b 7478 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7479 {
47926f60
KH		 7480 /* Don't have to change opcode. */
7481 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7482 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7483 }
7484 else
7485 {
7486 if (no_cond_jump_promotion
7487 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7488 as_warn_where (fragP->fr_file, fragP->fr_line,
7489 _("long jump required"));
252b5132 7490
fddf5b5b
AM		 7491 switch (fragP->fr_subtype)
7492 {
7493 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7494 extension = 4; /* 1 opcode + 4 displacement */
7495 opcode[0] = 0xe9;
7496 where_to_put_displacement = &opcode[1];
7497 break;
252b5132 7498
fddf5b5b
AM		 7499 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7500 extension = 2; /* 1 opcode + 2 displacement */
7501 opcode[0] = 0xe9;
7502 where_to_put_displacement = &opcode[1];
7503 break;
252b5132 7504
fddf5b5b
AM		 7505 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7506 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7507 extension = 5; /* 2 opcode + 4 displacement */
7508 opcode[1] = opcode[0] + 0x10;
7509 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7510 where_to_put_displacement = &opcode[2];
7511 break;
252b5132 7512
fddf5b5b
AM		 7513 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7514 extension = 3; /* 2 opcode + 2 displacement */
7515 opcode[1] = opcode[0] + 0x10;
7516 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7517 where_to_put_displacement = &opcode[2];
7518 break;
252b5132 7519
fddf5b5b
AM		 7520 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7521 extension = 4;
7522 opcode[0] ^= 1;
7523 opcode[1] = 3;
7524 opcode[2] = 0xe9;
7525 where_to_put_displacement = &opcode[3];
7526 break;
7527
7528 default:
7529 BAD_CASE (fragP->fr_subtype);
7530 break;
7531 }
252b5132 7532 }
fddf5b5b 7533
7b81dfbb
AJ		 7534 /* If size if less then four we are sure that the operand fits,
7535 but if it's 4, then it could be that the displacement is larger
7536 then -/+ 2GB. */
7537 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7538 && object_64bit
7539 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7540 + ((addressT) 1 << 31))
7541 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7542 {
7543 as_bad_where (fragP->fr_file, fragP->fr_line,
7544 _("jump target out of range"));
7545 /* Make us emit 0. */
7546 displacement_from_opcode_start = extension;
7547 }
47926f60 7548 /* Now put displacement after opcode. */
252b5132
RH		 7549 md_number_to_chars ((char *) where_to_put_displacement,
7550 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7551 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7552 fragP->fr_fix += extension;
7553}
7554\f
252b5132
RH		 7555/* Apply a fixup (fixS) to segment data, once it has been determined
7556 by our caller that we have all the info we need to fix it up.
7557
7558 On the 386, immediates, displacements, and data pointers are all in
7559 the same (little-endian) format, so we don't need to care about which
7560 we are handling. */
7561
94f592af 7562void
55cf6793 7563md_apply_fix (fixP, valP, seg)
47926f60
KH		 7564 /* The fix we're to put in. */
7565 fixS *fixP;
47926f60 7566 /* Pointer to the value of the bits. */
c6682705 7567 valueT *valP;
47926f60
KH		 7568 /* Segment fix is from. */
7569 segT seg ATTRIBUTE_UNUSED;
252b5132 7570{
94f592af 7571 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7572 valueT value = *valP;
252b5132 7573
f86103b7 7574#if !defined (TE_Mach)
93382f6d
AM		 7575 if (fixP->fx_pcrel)
7576 {
7577 switch (fixP->fx_r_type)
7578 {
5865bb77
ILT		 7579 default:
7580 break;
7581
d6ab8113
JB		 7582 case BFD_RELOC_64:
7583 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7584 break;
93382f6d 7585 case BFD_RELOC_32:
ae8887b5 7586 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7587 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7588 break;
7589 case BFD_RELOC_16:
7590 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7591 break;
7592 case BFD_RELOC_8:
7593 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7594 break;
7595 }
7596 }
252b5132 7597
a161fe53 7598 if (fixP->fx_addsy != NULL
31312f95 7599 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7600 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7601 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7602 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7603 && !use_rela_relocations)
252b5132 7604 {
31312f95
AM		 7605 /* This is a hack. There should be a better way to handle this.
7606 This covers for the fact that bfd_install_relocation will
7607 subtract the current location (for partial_inplace, PC relative
7608 relocations); see more below. */
252b5132 7609#ifndef OBJ_AOUT
718ddfc0 7610 if (IS_ELF
252b5132
RH		 7611#ifdef TE_PE
7612 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7613#endif
7614 )
7615 value += fixP->fx_where + fixP->fx_frag->fr_address;
7616#endif
7617#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7618 if (IS_ELF)
252b5132 7619 {
6539b54b 7620 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7621
6539b54b 7622 if ((sym_seg == seg
2f66722d 7623 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7624 && sym_seg != absolute_section))
af65af87 7625 && !generic_force_reloc (fixP))
2f66722d
AM		 7626 {
7627 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7628 bfd_install_relocation subtracts them out again. I think
7629 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7630 it. FIXME. */
7631 value += fixP->fx_where + fixP->fx_frag->fr_address;
7632 }
252b5132
RH		 7633 }
7634#endif
7635#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7636 /* For some reason, the PE format does not store a
7637 section address offset for a PC relative symbol. */
7638 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7639 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7640 value += md_pcrel_from (fixP);
7641#endif
7642 }
fbeb56a4
DK		 7643#if defined (OBJ_COFF) && defined (TE_PE)
7644 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7645 {
7646 value -= S_GET_VALUE (fixP->fx_addsy);
7647 }
7648#endif
252b5132
RH		 7649
7650 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7651 and we must not disappoint it. */
252b5132 7652#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7653 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7654 switch (fixP->fx_r_type)
7655 {
7656 case BFD_RELOC_386_PLT32:
3e73aa7c 7657 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7658 /* Make the jump instruction point to the address of the operand. At
7659 runtime we merely add the offset to the actual PLT entry. */
7660 value = -4;
7661 break;
31312f95 7662
13ae64f3
JJ		 7663 case BFD_RELOC_386_TLS_GD:
7664 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7665 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7666 case BFD_RELOC_386_TLS_IE:
7667 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7668 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7669 case BFD_RELOC_X86_64_TLSGD:
7670 case BFD_RELOC_X86_64_TLSLD:
7671 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7672 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7673 value = 0; /* Fully resolved at runtime. No addend. */
7674 /* Fallthrough */
7675 case BFD_RELOC_386_TLS_LE:
7676 case BFD_RELOC_386_TLS_LDO_32:
7677 case BFD_RELOC_386_TLS_LE_32:
7678 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7679 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7680 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7681 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7682 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7683 break;
7684
67a4f2b7
AO		 7685 case BFD_RELOC_386_TLS_DESC_CALL:
7686 case BFD_RELOC_X86_64_TLSDESC_CALL:
7687 value = 0; /* Fully resolved at runtime. No addend. */
7688 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7689 fixP->fx_done = 0;
7690 return;
7691
00f7efb6
JJ		 7692 case BFD_RELOC_386_GOT32:
7693 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7694 value = 0; /* Fully resolved at runtime. No addend. */
7695 break;
47926f60
KH		 7696
7697 case BFD_RELOC_VTABLE_INHERIT:
7698 case BFD_RELOC_VTABLE_ENTRY:
7699 fixP->fx_done = 0;
94f592af 7700 return;
47926f60
KH		 7701
7702 default:
7703 break;
7704 }
7705#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7706 *valP = value;
f86103b7 7707#endif /* !defined (TE_Mach) */
3e73aa7c 7708
3e73aa7c 7709 /* Are we finished with this relocation now? */
c6682705 7710 if (fixP->fx_addsy == NULL)
3e73aa7c 7711 fixP->fx_done = 1;
fbeb56a4
DK		 7712#if defined (OBJ_COFF) && defined (TE_PE)
7713 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7714 {
7715 fixP->fx_done = 0;
7716 /* Remember value for tc_gen_reloc. */
7717 fixP->fx_addnumber = value;
7718 /* Clear out the frag for now. */
7719 value = 0;
7720 }
7721#endif
3e73aa7c
JH		 7722 else if (use_rela_relocations)
7723 {
7724 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7725 /* Remember value for tc_gen_reloc. */
7726 fixP->fx_addnumber = value;
3e73aa7c
JH		 7727 value = 0;
7728 }
f86103b7 7729
94f592af 7730 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7731}
252b5132 7732\f
252b5132 7733char *
499ac353 7734md_atof (int type, char *litP, int *sizeP)
252b5132 7735{
499ac353
NC		 7736 /* This outputs the LITTLENUMs in REVERSE order;
7737 in accord with the bigendian 386. */
7738 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7739}
7740\f
2d545b82 7741static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7742
252b5132 7743static char *
e3bb37b5 7744output_invalid (int c)
252b5132 7745{
3882b010 7746 if (ISPRINT (c))
f9f21a03
L		 7747 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7748 "'%c'", c);
252b5132 7749 else
f9f21a03 7750 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7751 "(0x%x)", (unsigned char) c);
252b5132
RH		 7752 return output_invalid_buf;
7753}
7754
af6bdddf 7755/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7756
7757static const reg_entry *
4d1bb795 7758parse_real_register (char *reg_string, char **end_op)
252b5132 7759{
af6bdddf
AM		 7760 char *s = reg_string;
7761 char *p;
252b5132
RH		 7762 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7763 const reg_entry *r;
7764
7765 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7766 if (*s == REGISTER_PREFIX)
7767 ++s;
7768
7769 if (is_space_char (*s))
7770 ++s;
7771
7772 p = reg_name_given;
af6bdddf 7773 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7774 {
7775 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7776 return (const reg_entry *) NULL;
7777 s++;
252b5132
RH		 7778 }
7779
6588847e
DN		 7780 /* For naked regs, make sure that we are not dealing with an identifier.
7781 This prevents confusing an identifier like `eax_var' with register
7782 `eax'. */
7783 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7784 return (const reg_entry *) NULL;
7785
af6bdddf 7786 *end_op = s;
252b5132
RH		 7787
7788 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7789
5f47d35b 7790 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7791 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7792 {
5f47d35b
AM		 7793 if (is_space_char (*s))
7794 ++s;
7795 if (*s == '(')
7796 {
af6bdddf 7797 ++s;
5f47d35b
AM		 7798 if (is_space_char (*s))
7799 ++s;
7800 if (*s >= '0' && *s <= '7')
7801 {
db557034 7802 int fpr = *s - '0';
af6bdddf 7803 ++s;
5f47d35b
AM		 7804 if (is_space_char (*s))
7805 ++s;
7806 if (*s == ')')
7807 {
7808 *end_op = s + 1;
1e9cc1c2 7809 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7810 know (r);
7811 return r + fpr;
5f47d35b 7812 }
5f47d35b 7813 }
47926f60 7814 /* We have "%st(" then garbage. */
5f47d35b
AM		 7815 return (const reg_entry *) NULL;
7816 }
7817 }
7818
a60de03c
JB		 7819 if (r == NULL || allow_pseudo_reg)
7820 return r;
7821
0dfbf9d7 7822 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7823 return (const reg_entry *) NULL;
7824
192dc9c6
JB		 7825 if ((r->reg_type.bitfield.reg32
7826 || r->reg_type.bitfield.sreg3
7827 || r->reg_type.bitfield.control
7828 || r->reg_type.bitfield.debug
7829 || r->reg_type.bitfield.test)
7830 && !cpu_arch_flags.bitfield.cpui386)
7831 return (const reg_entry *) NULL;
7832
309d3373
JB		 7833 if (r->reg_type.bitfield.floatreg
7834 && !cpu_arch_flags.bitfield.cpu8087
7835 && !cpu_arch_flags.bitfield.cpu287
7836 && !cpu_arch_flags.bitfield.cpu387)
7837 return (const reg_entry *) NULL;
7838
192dc9c6
JB		 7839 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7840 return (const reg_entry *) NULL;
7841
7842 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7843 return (const reg_entry *) NULL;
7844
40f12533
L		 7845 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7846 return (const reg_entry *) NULL;
7847
db51cc60 7848 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7849 if (!allow_index_reg
db51cc60
L		 7850 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7851 return (const reg_entry *) NULL;
7852
a60de03c
JB		 7853 if (((r->reg_flags & (RegRex64 | RegRex))
7854 || r->reg_type.bitfield.reg64)
40fb9820 7855 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7856 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7857 && flag_code != CODE_64BIT)
20f0a1fc 7858 return (const reg_entry *) NULL;
1ae00879 7859
b7240065
JB		 7860 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7861 return (const reg_entry *) NULL;
7862
252b5132
RH		 7863 return r;
7864}
4d1bb795
JB		 7865
7866/* REG_STRING starts *before* REGISTER_PREFIX. */
7867
7868static const reg_entry *
7869parse_register (char *reg_string, char **end_op)
7870{
7871 const reg_entry *r;
7872
7873 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7874 r = parse_real_register (reg_string, end_op);
7875 else
7876 r = NULL;
7877 if (!r)
7878 {
7879 char *save = input_line_pointer;
7880 char c;
7881 symbolS *symbolP;
7882
7883 input_line_pointer = reg_string;
7884 c = get_symbol_end ();
7885 symbolP = symbol_find (reg_string);
7886 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7887 {
7888 const expressionS *e = symbol_get_value_expression (symbolP);
7889
7890 know (e->X_op == O_register);
4eed87de 7891 know (e->X_add_number >= 0
c3fe08fa 7892 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7893 r = i386_regtab + e->X_add_number;
7894 *end_op = input_line_pointer;
7895 }
7896 *input_line_pointer = c;
7897 input_line_pointer = save;
7898 }
7899 return r;
7900}
7901
7902int
7903i386_parse_name (char *name, expressionS *e, char *nextcharP)
7904{
7905 const reg_entry *r;
7906 char *end = input_line_pointer;
7907
7908 *end = *nextcharP;
7909 r = parse_register (name, &input_line_pointer);
7910 if (r && end <= input_line_pointer)
7911 {
7912 *nextcharP = *input_line_pointer;
7913 *input_line_pointer = 0;
7914 e->X_op = O_register;
7915 e->X_add_number = r - i386_regtab;
7916 return 1;
7917 }
7918 input_line_pointer = end;
7919 *end = 0;
ee86248c 7920 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7921}
7922
7923void
7924md_operand (expressionS *e)
7925{
ee86248c
JB		 7926 char *end;
7927 const reg_entry *r;
4d1bb795 7928
ee86248c
JB		 7929 switch (*input_line_pointer)
7930 {
7931 case REGISTER_PREFIX:
7932 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7933 if (r)
7934 {
7935 e->X_op = O_register;
7936 e->X_add_number = r - i386_regtab;
7937 input_line_pointer = end;
7938 }
ee86248c
JB		 7939 break;
7940
7941 case '[':
9c2799c2 7942 gas_assert (intel_syntax);
ee86248c
JB		 7943 end = input_line_pointer++;
7944 expression (e);
7945 if (*input_line_pointer == ']')
7946 {
7947 ++input_line_pointer;
7948 e->X_op_symbol = make_expr_symbol (e);
7949 e->X_add_symbol = NULL;
7950 e->X_add_number = 0;
7951 e->X_op = O_index;
7952 }
7953 else
7954 {
7955 e->X_op = O_absent;
7956 input_line_pointer = end;
7957 }
7958 break;
4d1bb795
JB		 7959 }
7960}
7961
252b5132 7962\f
4cc782b5 7963#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7964const char *md_shortopts = "kVQ:sqn";
252b5132 7965#else
12b55ccc 7966const char *md_shortopts = "qn";
252b5132 7967#endif
6e0b89ee 7968
3e73aa7c 7969#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7970#define OPTION_64 (OPTION_MD_BASE + 1)
7971#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7972#define OPTION_MARCH (OPTION_MD_BASE + 3)
7973#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7974#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7975#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7976#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7977#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7978#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7979#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7980#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
539f890d 7981#define OPTION_MAVXSCALAR (OPTION_MSSE_CHECK + 11)
b3b91714 7982
99ad8390
NC		 7983struct option md_longopts[] =
7984{
3e73aa7c 7985 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7986#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7987 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7988 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7989#endif
b3b91714 7990 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7991 {"march", required_argument, NULL, OPTION_MARCH},
7992 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7993 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7994 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7995 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7996 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7997 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7998 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7999 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8000 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8001 {NULL, no_argument, NULL, 0}
8002};
8003size_t md_longopts_size = sizeof (md_longopts);
8004
8005int
9103f4f4 8006md_parse_option (int c, char *arg)
252b5132 8007{
91d6fa6a 8008 unsigned int j;
6305a203 8009 char *arch, *next;
9103f4f4 8010
252b5132
RH		 8011 switch (c)
8012 {
12b55ccc
L		 8013 case 'n':
8014 optimize_align_code = 0;
8015 break;
8016
a38cf1db
AM		 8017 case 'q':
8018 quiet_warnings = 1;
252b5132
RH		 8019 break;
8020
8021#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8022 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8023 should be emitted or not. FIXME: Not implemented. */
8024 case 'Q':
252b5132
RH		 8025 break;
8026
8027 /* -V: SVR4 argument to print version ID. */
8028 case 'V':
8029 print_version_id ();
8030 break;
8031
a38cf1db
AM		 8032 /* -k: Ignore for FreeBSD compatibility. */
8033 case 'k':
252b5132 8034 break;
4cc782b5
ILT		 8035
8036 case 's':
8037 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8038 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8039 break;
99ad8390 8040#endif
321098a5
L		 8041#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8042 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8043 case OPTION_64:
8044 {
8045 const char **list, **l;
8046
3e73aa7c
JH		 8047 list = bfd_target_list ();
8048 for (l = list; *l != NULL; l++)
8620418b 8049 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8050 || strcmp (*l, "coff-x86-64") == 0
8051 || strcmp (*l, "pe-x86-64") == 0
8052 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8053 {
8054 default_arch = "x86_64";
8055 break;
8056 }
3e73aa7c 8057 if (*l == NULL)
6e0b89ee 8058 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8059 free (list);
8060 }
8061 break;
8062#endif
252b5132 8063
6e0b89ee
AM		 8064 case OPTION_32:
8065 default_arch = "i386";
8066 break;
8067
b3b91714
AM		 8068 case OPTION_DIVIDE:
8069#ifdef SVR4_COMMENT_CHARS
8070 {
8071 char *n, *t;
8072 const char *s;
8073
8074 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8075 t = n;
8076 for (s = i386_comment_chars; *s != '\0'; s++)
8077 if (*s != '/')
8078 *t++ = *s;
8079 *t = '\0';
8080 i386_comment_chars = n;
8081 }
8082#endif
8083 break;
8084
9103f4f4 8085 case OPTION_MARCH:
6305a203
L		 8086 arch = xstrdup (arg);
8087 do
9103f4f4 8088 {
6305a203
L		 8089 if (*arch == '.')
8090 as_fatal (_("Invalid -march= option: `%s'"), arg);
8091 next = strchr (arch, '+');
8092 if (next)
8093 *next++ = '\0';
91d6fa6a 8094 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8095 {
91d6fa6a 8096 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8097 {
6305a203 8098 /* Processor. */
91d6fa6a 8099 cpu_arch_name = cpu_arch[j].name;
6305a203 8100 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8101 cpu_arch_flags = cpu_arch[j].flags;
8102 cpu_arch_isa = cpu_arch[j].type;
8103 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8104 if (!cpu_arch_tune_set)
8105 {
8106 cpu_arch_tune = cpu_arch_isa;
8107 cpu_arch_tune_flags = cpu_arch_isa_flags;
8108 }
8109 break;
8110 }
91d6fa6a
NC		 8111 else if (*cpu_arch [j].name == '.'
8112 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8113 {
8114 /* ISA entension. */
8115 i386_cpu_flags flags;
309d3373
JB		 8116
8117 if (strncmp (arch, "no", 2))
8118 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8119 cpu_arch[j].flags);
309d3373
JB		 8120 else
8121 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 8122 cpu_arch[j].flags);
0dfbf9d7 8123 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8124 {
8125 if (cpu_sub_arch_name)
8126 {
8127 char *name = cpu_sub_arch_name;
8128 cpu_sub_arch_name = concat (name,
91d6fa6a 8129 cpu_arch[j].name,
1bf57e9f 8130 (const char *) NULL);
6305a203
L		 8131 free (name);
8132 }
8133 else
91d6fa6a 8134 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8135 cpu_arch_flags = flags;
8136 }
8137 break;
ccc9c027 8138 }
9103f4f4 8139 }
6305a203 8140
91d6fa6a 8141 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8142 as_fatal (_("Invalid -march= option: `%s'"), arg);
8143
8144 arch = next;
9103f4f4 8145 }
6305a203 8146 while (next != NULL );
9103f4f4
L		 8147 break;
8148
8149 case OPTION_MTUNE:
8150 if (*arg == '.')
8151 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8152 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8153 {
91d6fa6a 8154 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8155 {
ccc9c027 8156 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8157 cpu_arch_tune = cpu_arch [j].type;
8158 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8159 break;
8160 }
8161 }
91d6fa6a 8162 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8163 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8164 break;
8165
1efbbeb4
L		 8166 case OPTION_MMNEMONIC:
8167 if (strcasecmp (arg, "att") == 0)
8168 intel_mnemonic = 0;
8169 else if (strcasecmp (arg, "intel") == 0)
8170 intel_mnemonic = 1;
8171 else
8172 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8173 break;
8174
8175 case OPTION_MSYNTAX:
8176 if (strcasecmp (arg, "att") == 0)
8177 intel_syntax = 0;
8178 else if (strcasecmp (arg, "intel") == 0)
8179 intel_syntax = 1;
8180 else
8181 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8182 break;
8183
8184 case OPTION_MINDEX_REG:
8185 allow_index_reg = 1;
8186 break;
8187
8188 case OPTION_MNAKED_REG:
8189 allow_naked_reg = 1;
8190 break;
8191
8192 case OPTION_MOLD_GCC:
8193 old_gcc = 1;
1efbbeb4
L		 8194 break;
8195
c0f3af97
L		 8196 case OPTION_MSSE2AVX:
8197 sse2avx = 1;
8198 break;
8199
daf50ae7
L		 8200 case OPTION_MSSE_CHECK:
8201 if (strcasecmp (arg, "error") == 0)
8202 sse_check = sse_check_error;
8203 else if (strcasecmp (arg, "warning") == 0)
8204 sse_check = sse_check_warning;
8205 else if (strcasecmp (arg, "none") == 0)
8206 sse_check = sse_check_none;
8207 else
8208 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8209 break;
8210
539f890d
L		 8211 case OPTION_MAVXSCALAR:
8212 if (strcasecmp (arg, "128") == 0)
8213 avxscalar = vex128;
8214 else if (strcasecmp (arg, "256") == 0)
8215 avxscalar = vex256;
8216 else
8217 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8218 break;
8219
252b5132
RH		 8220 default:
8221 return 0;
8222 }
8223 return 1;
8224}
8225
8a2c8fef
L		 8226#define MESSAGE_TEMPLATE \
8227" "
8228
8229static void
8230show_arch (FILE *stream, int ext)
8231{
8232 static char message[] = MESSAGE_TEMPLATE;
8233 char *start = message + 27;
8234 char *p;
8235 int size = sizeof (MESSAGE_TEMPLATE);
8236 int left;
8237 const char *name;
8238 int len;
8239 unsigned int j;
8240
8241 p = start;
8242 left = size - (start - message);
8243 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8244 {
8245 /* Should it be skipped? */
8246 if (cpu_arch [j].skip)
8247 continue;
8248
8249 name = cpu_arch [j].name;
8250 len = cpu_arch [j].len;
8251 if (*name == '.')
8252 {
8253 /* It is an extension. Skip if we aren't asked to show it. */
8254 if (ext)
8255 {
8256 name++;
8257 len--;
8258 }
8259 else
8260 continue;
8261 }
8262 else if (ext)
8263 {
8264 /* It is an processor. Skip if we show only extension. */
8265 continue;
8266 }
8267
8268 /* Reserve 2 spaces for ", " or ",\0" */
8269 left -= len + 2;
8270
8271 /* Check if there is any room. */
8272 if (left >= 0)
8273 {
8274 if (p != start)
8275 {
8276 *p++ = ',';
8277 *p++ = ' ';
8278 }
8279 p = mempcpy (p, name, len);
8280 }
8281 else
8282 {
8283 /* Output the current message now and start a new one. */
8284 *p++ = ',';
8285 *p = '\0';
8286 fprintf (stream, "%s\n", message);
8287 p = start;
8288 left = size - (start - message) - len - 2;
8289
8290 gas_assert (left >= 0);
8291
8292 p = mempcpy (p, name, len);
8293 }
8294 }
8295
8296 *p = '\0';
8297 fprintf (stream, "%s\n", message);
8298}
8299
252b5132 8300void
8a2c8fef 8301md_show_usage (FILE *stream)
252b5132 8302{
4cc782b5
ILT		 8303#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8304 fprintf (stream, _("\
a38cf1db
AM		 8305 -Q ignored\n\
8306 -V print assembler version number\n\
b3b91714
AM		 8307 -k ignored\n"));
8308#endif
8309 fprintf (stream, _("\
12b55ccc 8310 -n Do not optimize code alignment\n\
b3b91714
AM		 8311 -q quieten some warnings\n"));
8312#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8313 fprintf (stream, _("\
a38cf1db 8314 -s ignored\n"));
b3b91714 8315#endif
321098a5
L		 8316#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8317 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8318 fprintf (stream, _("\
8319 --32/--64 generate 32bit/64bit code\n"));
8320#endif
b3b91714
AM		 8321#ifdef SVR4_COMMENT_CHARS
8322 fprintf (stream, _("\
8323 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8324#else
8325 fprintf (stream, _("\
b3b91714 8326 --divide ignored\n"));
4cc782b5 8327#endif
9103f4f4 8328 fprintf (stream, _("\
6305a203 8329 -march=CPU[,+EXTENSION...]\n\
8a2c8fef
L		 8330 generate code for CPU and EXTENSION, CPU is one of:\n"));
8331 show_arch (stream, 0);
8332 fprintf (stream, _("\
8333 EXTENSION is combination of:\n"));
8334 show_arch (stream, 1);
6305a203 8335 fprintf (stream, _("\
8a2c8fef
L		 8336 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8337 show_arch (stream, 0);
ba104c83 8338 fprintf (stream, _("\
c0f3af97
L		 8339 -msse2avx encode SSE instructions with VEX prefix\n"));
8340 fprintf (stream, _("\
daf50ae7
L		 8341 -msse-check=[none|error|warning]\n\
8342 check SSE instructions\n"));
8343 fprintf (stream, _("\
539f890d
L		 8344 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8345 length\n"));
8346 fprintf (stream, _("\
ba104c83
L		 8347 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8348 fprintf (stream, _("\
8349 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8350 fprintf (stream, _("\
8351 -mindex-reg support pseudo index registers\n"));
8352 fprintf (stream, _("\
8353 -mnaked-reg don't require `%%' prefix for registers\n"));
8354 fprintf (stream, _("\
8355 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8356}
8357
3e73aa7c 8358#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8359 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8360 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8361
8362/* Pick the target format to use. */
8363
47926f60 8364const char *
e3bb37b5 8365i386_target_format (void)
252b5132 8366{
3e73aa7c 8367 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8368 {
8369 set_code_flag (CODE_64BIT);
0dfbf9d7 8370 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8371 {
8372 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8373 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8374 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8375 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8376 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8377 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8378 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8379 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8380 cpu_arch_isa_flags.bitfield.cpusse = 1;
8381 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 8382 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 8383 }
0dfbf9d7 8384 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8385 {
8386 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8387 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8388 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8389 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8390 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8391 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8392 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8393 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8394 cpu_arch_tune_flags.bitfield.cpusse = 1;
8395 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8396 }
9103f4f4 8397 }
3e73aa7c 8398 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8399 {
8400 set_code_flag (CODE_32BIT);
0dfbf9d7 8401 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8402 {
8403 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8404 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8405 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8406 }
0dfbf9d7 8407 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8408 {
8409 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8410 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8411 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8412 }
9103f4f4 8413 }
3e73aa7c
JH		 8414 else
8415 as_fatal (_("Unknown architecture"));
252b5132
RH		 8416 switch (OUTPUT_FLAVOR)
8417 {
9384f2ff 8418#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8419 case bfd_target_aout_flavour:
47926f60 8420 return AOUT_TARGET_FORMAT;
4c63da97 8421#endif
9384f2ff
AM		 8422#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8423# if defined (TE_PE) || defined (TE_PEP)
8424 case bfd_target_coff_flavour:
8425 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8426# elif defined (TE_GO32)
0561d57c
JK		 8427 case bfd_target_coff_flavour:
8428 return "coff-go32";
9384f2ff 8429# else
252b5132
RH		 8430 case bfd_target_coff_flavour:
8431 return "coff-i386";
9384f2ff 8432# endif
4c63da97 8433#endif
3e73aa7c 8434#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8435 case bfd_target_elf_flavour:
3e73aa7c 8436 {
e5cb08ac 8437 if (flag_code == CODE_64BIT)
4fa24527
JB		 8438 {
8439 object_64bit = 1;
8440 use_rela_relocations = 1;
8441 }
3632d14b 8442 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8443 {
8444 if (flag_code != CODE_64BIT)
8445 as_fatal (_("Intel L1OM is 64bit only"));
8446 return ELF_TARGET_L1OM_FORMAT;
8447 }
8448 else
8449 return (flag_code == CODE_64BIT
8450 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8451 }
e57f8c65
TG		 8452#endif
8453#if defined (OBJ_MACH_O)
8454 case bfd_target_mach_o_flavour:
8455 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8456#endif
252b5132
RH		 8457 default:
8458 abort ();
8459 return NULL;
8460 }
8461}
8462
47926f60 8463#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8464
8465#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8466void
8467i386_elf_emit_arch_note (void)
a847613f 8468{
718ddfc0 8469 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8470 {
8471 char *p;
8472 asection *seg = now_seg;
8473 subsegT subseg = now_subseg;
8474 Elf_Internal_Note i_note;
8475 Elf_External_Note e_note;
8476 asection *note_secp;
8477 int len;
8478
8479 /* Create the .note section. */
8480 note_secp = subseg_new (".note", 0);
8481 bfd_set_section_flags (stdoutput,
8482 note_secp,
8483 SEC_HAS_CONTENTS | SEC_READONLY);
8484
8485 /* Process the arch string. */
8486 len = strlen (cpu_arch_name);
8487
8488 i_note.namesz = len + 1;
8489 i_note.descsz = 0;
8490 i_note.type = NT_ARCH;
8491 p = frag_more (sizeof (e_note.namesz));
8492 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8493 p = frag_more (sizeof (e_note.descsz));
8494 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8495 p = frag_more (sizeof (e_note.type));
8496 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8497 p = frag_more (len + 1);
8498 strcpy (p, cpu_arch_name);
8499
8500 frag_align (2, 0, 0);
8501
8502 subseg_set (seg, subseg);
8503 }
8504}
8505#endif
252b5132 8506\f
252b5132
RH		 8507symbolS *
8508md_undefined_symbol (name)
8509 char *name;
8510{
18dc2407
ILT		 8511 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8512 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8513 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8514 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8515 {
8516 if (!GOT_symbol)
8517 {
8518 if (symbol_find (name))
8519 as_bad (_("GOT already in symbol table"));
8520 GOT_symbol = symbol_new (name, undefined_section,
8521 (valueT) 0, &zero_address_frag);
8522 };
8523 return GOT_symbol;
8524 }
252b5132
RH		 8525 return 0;
8526}
8527
8528/* Round up a section size to the appropriate boundary. */
47926f60 8529
252b5132
RH		 8530valueT
8531md_section_align (segment, size)
ab9da554 8532 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8533 valueT size;
8534{
4c63da97
AM		 8535#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8536 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8537 {
8538 /* For a.out, force the section size to be aligned. If we don't do
8539 this, BFD will align it for us, but it will not write out the
8540 final bytes of the section. This may be a bug in BFD, but it is
8541 easier to fix it here since that is how the other a.out targets
8542 work. */
8543 int align;
8544
8545 align = bfd_get_section_alignment (stdoutput, segment);
8546 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8547 }
252b5132
RH		 8548#endif
8549
8550 return size;
8551}
8552
8553/* On the i386, PC-relative offsets are relative to the start of the
8554 next instruction. That is, the address of the offset, plus its
8555 size, since the offset is always the last part of the insn. */
8556
8557long
e3bb37b5 8558md_pcrel_from (fixS *fixP)
252b5132
RH		 8559{
8560 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8561}
8562
8563#ifndef I386COFF
8564
8565static void
e3bb37b5 8566s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8567{
29b0f896 8568 int temp;
252b5132 8569
8a75718c
JB		 8570#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8571 if (IS_ELF)
8572 obj_elf_section_change_hook ();
8573#endif
252b5132
RH		 8574 temp = get_absolute_expression ();
8575 subseg_set (bss_section, (subsegT) temp);
8576 demand_empty_rest_of_line ();
8577}
8578
8579#endif
8580
252b5132 8581void
e3bb37b5 8582i386_validate_fix (fixS *fixp)
252b5132
RH		 8583{
8584 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8585 {
23df1078
JH		 8586 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8587 {
4fa24527 8588 if (!object_64bit)
23df1078
JH		 8589 abort ();
8590 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8591 }
8592 else
8593 {
4fa24527 8594 if (!object_64bit)
d6ab8113
JB		 8595 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8596 else
8597 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8598 }
252b5132
RH		 8599 fixp->fx_subsy = 0;
8600 }
8601}
8602
252b5132
RH		 8603arelent *
8604tc_gen_reloc (section, fixp)
ab9da554 8605 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8606 fixS *fixp;
8607{
8608 arelent *rel;
8609 bfd_reloc_code_real_type code;
8610
8611 switch (fixp->fx_r_type)
8612 {
3e73aa7c
JH		 8613 case BFD_RELOC_X86_64_PLT32:
8614 case BFD_RELOC_X86_64_GOT32:
8615 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8616 case BFD_RELOC_386_PLT32:
8617 case BFD_RELOC_386_GOT32:
8618 case BFD_RELOC_386_GOTOFF:
8619 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8620 case BFD_RELOC_386_TLS_GD:
8621 case BFD_RELOC_386_TLS_LDM:
8622 case BFD_RELOC_386_TLS_LDO_32:
8623 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8624 case BFD_RELOC_386_TLS_IE:
8625 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8626 case BFD_RELOC_386_TLS_LE_32:
8627 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8628 case BFD_RELOC_386_TLS_GOTDESC:
8629 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8630 case BFD_RELOC_X86_64_TLSGD:
8631 case BFD_RELOC_X86_64_TLSLD:
8632 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8633 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8634 case BFD_RELOC_X86_64_GOTTPOFF:
8635 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8636 case BFD_RELOC_X86_64_TPOFF64:
8637 case BFD_RELOC_X86_64_GOTOFF64:
8638 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8639 case BFD_RELOC_X86_64_GOT64:
8640 case BFD_RELOC_X86_64_GOTPCREL64:
8641 case BFD_RELOC_X86_64_GOTPC64:
8642 case BFD_RELOC_X86_64_GOTPLT64:
8643 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8644 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8645 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8646 case BFD_RELOC_RVA:
8647 case BFD_RELOC_VTABLE_ENTRY:
8648 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8649#ifdef TE_PE
8650 case BFD_RELOC_32_SECREL:
8651#endif
252b5132
RH		 8652 code = fixp->fx_r_type;
8653 break;
dbbaec26
L		 8654 case BFD_RELOC_X86_64_32S:
8655 if (!fixp->fx_pcrel)
8656 {
8657 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8658 code = fixp->fx_r_type;
8659 break;
8660 }
252b5132 8661 default:
93382f6d 8662 if (fixp->fx_pcrel)
252b5132 8663 {
93382f6d
AM		 8664 switch (fixp->fx_size)
8665 {
8666 default:
b091f402
AM		 8667 as_bad_where (fixp->fx_file, fixp->fx_line,
8668 _("can not do %d byte pc-relative relocation"),
8669 fixp->fx_size);
93382f6d
AM		 8670 code = BFD_RELOC_32_PCREL;
8671 break;
8672 case 1: code = BFD_RELOC_8_PCREL; break;
8673 case 2: code = BFD_RELOC_16_PCREL; break;
8674 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8675#ifdef BFD64
8676 case 8: code = BFD_RELOC_64_PCREL; break;
8677#endif
93382f6d
AM		 8678 }
8679 }
8680 else
8681 {
8682 switch (fixp->fx_size)
8683 {
8684 default:
b091f402
AM		 8685 as_bad_where (fixp->fx_file, fixp->fx_line,
8686 _("can not do %d byte relocation"),
8687 fixp->fx_size);
93382f6d
AM		 8688 code = BFD_RELOC_32;
8689 break;
8690 case 1: code = BFD_RELOC_8; break;
8691 case 2: code = BFD_RELOC_16; break;
8692 case 4: code = BFD_RELOC_32; break;
937149dd 8693#ifdef BFD64
3e73aa7c 8694 case 8: code = BFD_RELOC_64; break;
937149dd 8695#endif
93382f6d 8696 }
252b5132
RH		 8697 }
8698 break;
8699 }
252b5132 8700
d182319b
JB		 8701 if ((code == BFD_RELOC_32
8702 || code == BFD_RELOC_32_PCREL
8703 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8704 && GOT_symbol
8705 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8706 {
4fa24527 8707 if (!object_64bit)
d6ab8113
JB		 8708 code = BFD_RELOC_386_GOTPC;
8709 else
8710 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8711 }
7b81dfbb
AJ		 8712 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8713 && GOT_symbol
8714 && fixp->fx_addsy == GOT_symbol)
8715 {
8716 code = BFD_RELOC_X86_64_GOTPC64;
8717 }
252b5132
RH		 8718
8719 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8720 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8721 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8722
8723 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8724
3e73aa7c
JH		 8725 if (!use_rela_relocations)
8726 {
8727 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8728 vtable entry to be used in the relocation's section offset. */
8729 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8730 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8731#if defined (OBJ_COFF) && defined (TE_PE)
8732 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8733 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8734 else
8735#endif
c6682705 8736 rel->addend = 0;
3e73aa7c
JH		 8737 }
8738 /* Use the rela in 64bit mode. */
252b5132 8739 else
3e73aa7c 8740 {
062cd5e7
AS		 8741 if (!fixp->fx_pcrel)
8742 rel->addend = fixp->fx_offset;
8743 else
8744 switch (code)
8745 {
8746 case BFD_RELOC_X86_64_PLT32:
8747 case BFD_RELOC_X86_64_GOT32:
8748 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8749 case BFD_RELOC_X86_64_TLSGD:
8750 case BFD_RELOC_X86_64_TLSLD:
8751 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8752 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8753 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8754 rel->addend = fixp->fx_offset - fixp->fx_size;
8755 break;
8756 default:
8757 rel->addend = (section->vma
8758 - fixp->fx_size
8759 + fixp->fx_addnumber
8760 + md_pcrel_from (fixp));
8761 break;
8762 }
3e73aa7c
JH		 8763 }
8764
252b5132
RH		 8765 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8766 if (rel->howto == NULL)
8767 {
8768 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8769 _("cannot represent relocation type %s"),
252b5132
RH		 8770 bfd_get_reloc_code_name (code));
8771 /* Set howto to a garbage value so that we can keep going. */
8772 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8773 gas_assert (rel->howto != NULL);
252b5132
RH		 8774 }
8775
8776 return rel;
8777}
8778
ee86248c 8779#include "tc-i386-intel.c"
54cfded0 8780
a60de03c
JB		 8781void
8782tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8783{
a60de03c
JB		 8784 int saved_naked_reg;
8785 char saved_register_dot;
54cfded0 8786
a60de03c
JB		 8787 saved_naked_reg = allow_naked_reg;
8788 allow_naked_reg = 1;
8789 saved_register_dot = register_chars['.'];
8790 register_chars['.'] = '.';
8791 allow_pseudo_reg = 1;
8792 expression_and_evaluate (exp);
8793 allow_pseudo_reg = 0;
8794 register_chars['.'] = saved_register_dot;
8795 allow_naked_reg = saved_naked_reg;
8796
8797 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8798 {
a60de03c
JB		 8799 if ((addressT) exp->X_add_number < i386_regtab_size)
8800 {
8801 exp->X_op = O_constant;
8802 exp->X_add_number = i386_regtab[exp->X_add_number]
8803 .dw2_regnum[flag_code >> 1];
8804 }
8805 else
8806 exp->X_op = O_illegal;
54cfded0 8807 }
54cfded0
AM		 8808}
8809
8810void
8811tc_x86_frame_initial_instructions (void)
8812{
a60de03c
JB		 8813 static unsigned int sp_regno[2];
8814
8815 if (!sp_regno[flag_code >> 1])
8816 {
8817 char *saved_input = input_line_pointer;
8818 char sp[][4] = {"esp", "rsp"};
8819 expressionS exp;
a4447b93 8820
a60de03c
JB		 8821 input_line_pointer = sp[flag_code >> 1];
8822 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8823 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8824 sp_regno[flag_code >> 1] = exp.X_add_number;
8825 input_line_pointer = saved_input;
8826 }
a4447b93 8827
a60de03c 8828 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8829 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8830}
d2b2c203
DJ		 8831
8832int
8833i386_elf_section_type (const char *str, size_t len)
8834{
8835 if (flag_code == CODE_64BIT
8836 && len == sizeof ("unwind") - 1
8837 && strncmp (str, "unwind", 6) == 0)
8838 return SHT_X86_64_UNWIND;
8839
8840 return -1;
8841}
bb41ade5 8842
ad5fec3b
EB		 8843#ifdef TE_SOLARIS
8844void
8845i386_solaris_fix_up_eh_frame (segT sec)
8846{
8847 if (flag_code == CODE_64BIT)
8848 elf_section_type (sec) = SHT_X86_64_UNWIND;
8849}
8850#endif
8851
bb41ade5
AM		 8852#ifdef TE_PE
8853void
8854tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8855{
91d6fa6a 8856 expressionS exp;
bb41ade5 8857
91d6fa6a
NC		 8858 exp.X_op = O_secrel;
8859 exp.X_add_symbol = symbol;
8860 exp.X_add_number = 0;
8861 emit_expr (&exp, size);
bb41ade5
AM		 8862}
8863#endif
3b22753a
L		 8864
8865#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8866/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8867
01e1a5bc 8868bfd_vma
3b22753a
L		 8869x86_64_section_letter (int letter, char **ptr_msg)
8870{
8871 if (flag_code == CODE_64BIT)
8872 {
8873 if (letter == 'l')
8874 return SHF_X86_64_LARGE;
8875
8876 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8877 }
3b22753a 8878 else
64e74474 8879 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8880 return -1;
8881}
8882
01e1a5bc 8883bfd_vma
3b22753a
L		 8884x86_64_section_word (char *str, size_t len)
8885{
8620418b 8886 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8887 return SHF_X86_64_LARGE;
8888
8889 return -1;
8890}
8891
8892static void
8893handle_large_common (int small ATTRIBUTE_UNUSED)
8894{
8895 if (flag_code != CODE_64BIT)
8896 {
8897 s_comm_internal (0, elf_common_parse);
8898 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8899 }
8900 else
8901 {
8902 static segT lbss_section;
8903 asection *saved_com_section_ptr = elf_com_section_ptr;
8904 asection *saved_bss_section = bss_section;
8905
8906 if (lbss_section == NULL)
8907 {
8908 flagword applicable;
8909 segT seg = now_seg;
8910 subsegT subseg = now_subseg;
8911
8912 /* The .lbss section is for local .largecomm symbols. */
8913 lbss_section = subseg_new (".lbss", 0);
8914 applicable = bfd_applicable_section_flags (stdoutput);
8915 bfd_set_section_flags (stdoutput, lbss_section,
8916 applicable & SEC_ALLOC);
8917 seg_info (lbss_section)->bss = 1;
8918
8919 subseg_set (seg, subseg);
8920 }
8921
8922 elf_com_section_ptr = &_bfd_elf_large_com_section;
8923 bss_section = lbss_section;
8924
8925 s_comm_internal (0, elf_common_parse);
8926
8927 elf_com_section_ptr = saved_com_section_ptr;
8928 bss_section = saved_bss_section;
8929 }
8930}
8931#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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