]>
Commit | Line | Data |
---|---|---|
b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
fd67aa11 | 2 | Copyright (C) 1989-2024 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
c7defc53 | 33 | #include "scfi.h" |
b52c4ee4 IB |
34 | #include "gen-sframe.h" |
35 | #include "sframe.h" | |
d2b2c203 | 36 | #include "elf/x86-64.h" |
40fb9820 | 37 | #include "opcodes/i386-init.h" |
5c139202 | 38 | #include "opcodes/i386-mnem.h" |
41fd2579 | 39 | #include <limits.h> |
41fd2579 | 40 | |
c3332e24 | 41 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 42 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
43 | #endif |
44 | ||
29b0f896 AM |
45 | #ifndef DEFAULT_ARCH |
46 | #define DEFAULT_ARCH "i386" | |
246fcdee | 47 | #endif |
252b5132 | 48 | |
edde18a5 AM |
49 | #ifndef INLINE |
50 | #if __GNUC__ >= 2 | |
51 | #define INLINE __inline__ | |
52 | #else | |
53 | #define INLINE | |
54 | #endif | |
55 | #endif | |
56 | ||
6305a203 L |
57 | /* Prefixes will be emitted in the order defined below. |
58 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
59 | instruction, and so must come before any prefixes. | |
60 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 61 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
62 | #define WAIT_PREFIX 0 |
63 | #define SEG_PREFIX 1 | |
64 | #define ADDR_PREFIX 2 | |
65 | #define DATA_PREFIX 3 | |
c32fa91d | 66 | #define REP_PREFIX 4 |
42164a71 | 67 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 68 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 69 | #define LOCK_PREFIX 5 |
4e9ac44a L |
70 | #define REX_PREFIX 6 /* must come last. */ |
71 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
72 | |
73 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
74 | #define REGISTER_PREFIX '%' | |
75 | #define IMMEDIATE_PREFIX '$' | |
76 | #define ABSOLUTE_PREFIX '*' | |
77 | ||
78 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
79 | memory operand size in Intel syntax. */ | |
80 | #define WORD_MNEM_SUFFIX 'w' | |
81 | #define BYTE_MNEM_SUFFIX 'b' | |
82 | #define SHORT_MNEM_SUFFIX 's' | |
83 | #define LONG_MNEM_SUFFIX 'l' | |
84 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
85 | |
86 | #define END_OF_INSN '\0' | |
87 | ||
05909f23 JB |
88 | #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } } |
89 | ||
79dec6b7 JB |
90 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
91 | #define commutative staticrounding | |
92 | ||
6305a203 L |
93 | /* |
94 | 'templates' is for grouping together 'template' structures for opcodes | |
95 | of the same name. This is only used for storing the insns in the grand | |
96 | ole hash table of insns. | |
97 | The templates themselves start at START and range up to (but not including) | |
98 | END. | |
99 | */ | |
100 | typedef struct | |
101 | { | |
d3ce72d0 NC |
102 | const insn_template *start; |
103 | const insn_template *end; | |
6305a203 L |
104 | } |
105 | templates; | |
106 | ||
107 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
108 | typedef struct | |
109 | { | |
110 | unsigned int regmem; /* codes register or memory operand */ | |
111 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
112 | unsigned int mode; /* how to interpret regmem & reg */ | |
113 | } | |
114 | modrm_byte; | |
115 | ||
116 | /* x86-64 extension prefix. */ | |
117 | typedef int rex_byte; | |
118 | ||
6305a203 L |
119 | /* 386 opcode byte to code indirect addressing. */ |
120 | typedef struct | |
121 | { | |
122 | unsigned base; | |
123 | unsigned index; | |
124 | unsigned scale; | |
125 | } | |
126 | sib_byte; | |
127 | ||
6305a203 L |
128 | /* x86 arch names, types and features */ |
129 | typedef struct | |
130 | { | |
131 | const char *name; /* arch name */ | |
6ceeed25 JB |
132 | unsigned int len:8; /* arch string length */ |
133 | bool skip:1; /* show_arch should skip this. */ | |
6305a203 | 134 | enum processor_type type; /* arch type */ |
4fc85f37 | 135 | enum { vsz_none, vsz_set, vsz_reset } vsz; /* vector size control */ |
ae89daec JB |
136 | i386_cpu_flags enable; /* cpu feature enable flags */ |
137 | i386_cpu_flags disable; /* cpu feature disable flags */ | |
6305a203 L |
138 | } |
139 | arch_entry; | |
140 | ||
78f12dd3 | 141 | static void update_code_flag (int, int); |
edd67638 | 142 | static void s_insn (int); |
1e7dd4a0 | 143 | static void s_noopt (int); |
e3bb37b5 L |
144 | static void set_code_flag (int); |
145 | static void set_16bit_gcc_code_flag (int); | |
146 | static void set_intel_syntax (int); | |
1efbbeb4 | 147 | static void set_intel_mnemonic (int); |
db51cc60 | 148 | static void set_allow_index_reg (int); |
7bab8ab5 | 149 | static void set_check (int); |
e3bb37b5 | 150 | static void set_cpu_arch (int); |
6482c264 | 151 | #ifdef TE_PE |
e3bb37b5 | 152 | static void pe_directive_secrel (int); |
145667f8 | 153 | static void pe_directive_secidx (int); |
6482c264 | 154 | #endif |
e3bb37b5 L |
155 | static void signed_cons (int); |
156 | static char *output_invalid (int c); | |
ee86248c JB |
157 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
158 | const char *); | |
159 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
160 | const char *); | |
a7619375 | 161 | static int i386_att_operand (char *); |
e3bb37b5 | 162 | static int i386_intel_operand (char *, int); |
ee86248c JB |
163 | static int i386_intel_simplify (expressionS *); |
164 | static int i386_intel_parse_name (const char *, expressionS *); | |
4f081312 | 165 | static const reg_entry *parse_register (const char *, char **); |
edd67638 | 166 | static const char *parse_insn (const char *, char *, bool); |
e3bb37b5 L |
167 | static char *parse_operands (char *, const char *); |
168 | static void swap_operands (void); | |
783c187b | 169 | static void swap_2_operands (unsigned int, unsigned int); |
ed719294 | 170 | static enum i386_flag_code i386_addressing_mode (void); |
e3bb37b5 | 171 | static void optimize_imm (void); |
0de704b9 | 172 | static bool optimize_disp (const insn_template *t); |
83b16ac6 | 173 | static const insn_template *match_template (char); |
e3bb37b5 L |
174 | static int check_string (void); |
175 | static int process_suffix (void); | |
176 | static int check_byte_reg (void); | |
177 | static int check_long_reg (void); | |
178 | static int check_qword_reg (void); | |
179 | static int check_word_reg (void); | |
180 | static int finalize_imm (void); | |
181 | static int process_operands (void); | |
5e042380 | 182 | static const reg_entry *build_modrm_byte (void); |
b5482fe5 | 183 | static void output_insn (const struct last_insn *); |
e3bb37b5 L |
184 | static void output_imm (fragS *, offsetT); |
185 | static void output_disp (fragS *, offsetT); | |
d4064aad | 186 | #ifdef OBJ_AOUT |
e3bb37b5 | 187 | static void s_bss (int); |
252b5132 | 188 | #endif |
17d4e2a2 L |
189 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
190 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
191 | |
192 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
193 | static unsigned int x86_isa_1_used; | |
194 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
195 | static unsigned int x86_feature_2_used; | |
196 | /* Generate x86 used ISA and feature properties. */ | |
197 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 198 | #endif |
252b5132 | 199 | |
a847613f | 200 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 201 | |
8a6fb3f9 JB |
202 | /* parse_register() returns this when a register alias cannot be used. */ |
203 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
204 | { Dw2Inval, Dw2Inval } }; | |
205 | ||
34684862 | 206 | static const reg_entry *reg_eax; |
5e042380 JB |
207 | static const reg_entry *reg_ds; |
208 | static const reg_entry *reg_es; | |
209 | static const reg_entry *reg_ss; | |
6288d05f | 210 | static const reg_entry *reg_st0; |
6225c532 JB |
211 | static const reg_entry *reg_k0; |
212 | ||
c0f3af97 L |
213 | /* VEX prefix. */ |
214 | typedef struct | |
215 | { | |
43234a1e L |
216 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
217 | unsigned char bytes[4]; | |
c0f3af97 L |
218 | unsigned int length; |
219 | /* Destination or source register specifier. */ | |
220 | const reg_entry *register_specifier; | |
221 | } vex_prefix; | |
222 | ||
252b5132 | 223 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 224 | i386_insn. */ |
252b5132 | 225 | |
520dc8e8 AM |
226 | union i386_op |
227 | { | |
228 | expressionS *disps; | |
229 | expressionS *imms; | |
230 | const reg_entry *regs; | |
231 | }; | |
232 | ||
a65babc9 L |
233 | enum i386_error |
234 | { | |
b4d65f2d | 235 | no_error, /* Must be first. */ |
86e026a4 | 236 | operand_size_mismatch, |
a65babc9 L |
237 | operand_type_mismatch, |
238 | register_type_mismatch, | |
239 | number_of_operands_mismatch, | |
240 | invalid_instruction_suffix, | |
241 | bad_imm4, | |
a65babc9 L |
242 | unsupported_with_intel_mnemonic, |
243 | unsupported_syntax, | |
80d61d8d | 244 | unsupported_EGPR_for_addressing, |
dd74a603 | 245 | unsupported_nf, |
6c30d220 | 246 | unsupported, |
9db83a32 JB |
247 | unsupported_on_arch, |
248 | unsupported_64bit, | |
54294d73 JB |
249 | no_vex_encoding, |
250 | no_evex_encoding, | |
260cd341 | 251 | invalid_sib_address, |
6c30d220 | 252 | invalid_vsib_address, |
7bab8ab5 | 253 | invalid_vector_register_set, |
260cd341 | 254 | invalid_tmm_register_set, |
0cc78721 | 255 | invalid_dest_and_src_register_set, |
08a98d4c | 256 | invalid_dest_register_set, |
80d61d8d | 257 | invalid_pseudo_prefix, |
43234a1e L |
258 | unsupported_vector_index_register, |
259 | unsupported_broadcast, | |
43234a1e L |
260 | broadcast_needed, |
261 | unsupported_masking, | |
262 | mask_not_on_destination, | |
263 | no_default_mask, | |
264 | unsupported_rc_sae, | |
54294d73 | 265 | unsupported_vector_size, |
08a98d4c | 266 | unsupported_rsp_register, |
58bceb18 | 267 | internal_error, |
a65babc9 L |
268 | }; |
269 | ||
252b5132 RH |
270 | struct _i386_insn |
271 | { | |
47926f60 | 272 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 273 | insn_template tm; |
252b5132 | 274 | |
7d5e4556 L |
275 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
276 | or qword, if given. */ | |
252b5132 RH |
277 | char suffix; |
278 | ||
9a182d04 JB |
279 | /* OPCODE_LENGTH holds the number of base opcode bytes. */ |
280 | unsigned char opcode_length; | |
281 | ||
47926f60 | 282 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
283 | unsigned int operands; |
284 | ||
285 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
286 | of given register, displacement, memory operands and immediate | |
47926f60 | 287 | operands. */ |
252b5132 RH |
288 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
289 | ||
290 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 291 | use OP[i] for the corresponding operand. */ |
40fb9820 | 292 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 293 | |
520dc8e8 AM |
294 | /* Displacement expression, immediate expression, or register for each |
295 | operand. */ | |
296 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 297 | |
3e73aa7c JH |
298 | /* Flags for operands. */ |
299 | unsigned int flags[MAX_OPERANDS]; | |
300 | #define Operand_PCrel 1 | |
c48dadc9 | 301 | #define Operand_Mem 2 |
c032bc4f | 302 | #define Operand_Signed 4 /* .insn only */ |
3e73aa7c | 303 | |
252b5132 | 304 | /* Relocation type for operand */ |
f86103b7 | 305 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 306 | |
252b5132 RH |
307 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
308 | the base index byte below. */ | |
309 | const reg_entry *base_reg; | |
310 | const reg_entry *index_reg; | |
311 | unsigned int log2_scale_factor; | |
312 | ||
313 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 314 | explicit segment overrides are given. */ |
5e042380 | 315 | const reg_entry *seg[2]; |
252b5132 RH |
316 | |
317 | /* PREFIX holds all the given prefix opcodes (usually null). | |
318 | PREFIXES is the number of prefix opcodes. */ | |
319 | unsigned int prefixes; | |
320 | unsigned char prefix[MAX_PREFIXES]; | |
321 | ||
d0c2e3ec JB |
322 | /* .insn allows for reserved opcode spaces. */ |
323 | unsigned char insn_opcode_space; | |
324 | ||
c032bc4f JB |
325 | /* .insn also allows (requires) specifying immediate size. */ |
326 | unsigned char imm_bits[MAX_OPERANDS]; | |
327 | ||
50128d0c | 328 | /* Register is in low 3 bits of opcode. */ |
5b7c81bd | 329 | bool short_form; |
50128d0c | 330 | |
6f2f06be | 331 | /* The operand to a branch insn indicates an absolute branch. */ |
5b7c81bd | 332 | bool jumpabsolute; |
6f2f06be | 333 | |
a4d3acd2 JB |
334 | /* The operand to a branch insn indicates a far branch. */ |
335 | bool far_branch; | |
336 | ||
9373f275 L |
337 | /* There is a memory operand of (%dx) which should be only used |
338 | with input/output instructions. */ | |
339 | bool input_output_operand; | |
340 | ||
921eafea L |
341 | /* Extended states. */ |
342 | enum | |
343 | { | |
344 | /* Use MMX state. */ | |
345 | xstate_mmx = 1 << 0, | |
346 | /* Use XMM state. */ | |
347 | xstate_xmm = 1 << 1, | |
348 | /* Use YMM state. */ | |
349 | xstate_ymm = 1 << 2 | xstate_xmm, | |
350 | /* Use ZMM state. */ | |
351 | xstate_zmm = 1 << 3 | xstate_ymm, | |
352 | /* Use TMM state. */ | |
32930e4e L |
353 | xstate_tmm = 1 << 4, |
354 | /* Use MASK state. */ | |
355 | xstate_mask = 1 << 5 | |
921eafea | 356 | } xstate; |
260cd341 | 357 | |
e379e5f3 | 358 | /* Has GOTPC or TLS relocation. */ |
5b7c81bd | 359 | bool has_gotpc_tls_reloc; |
e379e5f3 | 360 | |
252b5132 | 361 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 362 | addressing modes of this insn are encoded. */ |
252b5132 | 363 | modrm_byte rm; |
3e73aa7c | 364 | rex_byte rex; |
43234a1e | 365 | rex_byte vrex; |
80d61d8d | 366 | rex_byte rex2; |
252b5132 | 367 | sib_byte sib; |
c0f3af97 | 368 | vex_prefix vex; |
b6169b20 | 369 | |
6225c532 JB |
370 | /* Masking attributes. |
371 | ||
372 | The struct describes masking, applied to OPERAND in the instruction. | |
373 | REG is a pointer to the corresponding mask register. ZEROING tells | |
374 | whether merging or zeroing mask is used. */ | |
375 | struct Mask_Operation | |
376 | { | |
377 | const reg_entry *reg; | |
378 | unsigned int zeroing; | |
379 | /* The operand where this operation is associated. */ | |
380 | unsigned int operand; | |
381 | } mask; | |
43234a1e L |
382 | |
383 | /* Rounding control and SAE attributes. */ | |
ca5312a2 JB |
384 | struct RC_Operation |
385 | { | |
386 | enum rc_type | |
387 | { | |
388 | rc_none = -1, | |
389 | rne, | |
390 | rd, | |
391 | ru, | |
392 | rz, | |
393 | saeonly | |
394 | } type; | |
7063667e JB |
395 | /* In Intel syntax the operand modifier form is supposed to be used, but |
396 | we continue to accept the immediate forms as well. */ | |
397 | bool modifier; | |
ca5312a2 | 398 | } rounding; |
43234a1e | 399 | |
5273a3cd JB |
400 | /* Broadcasting attributes. |
401 | ||
402 | The struct describes broadcasting, applied to OPERAND. TYPE is | |
403 | expresses the broadcast factor. */ | |
404 | struct Broadcast_Operation | |
405 | { | |
0cc78721 | 406 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */ |
5273a3cd JB |
407 | unsigned int type; |
408 | ||
409 | /* Index of broadcasted operand. */ | |
410 | unsigned int operand; | |
411 | ||
412 | /* Number of bytes to broadcast. */ | |
413 | unsigned int bytes; | |
414 | } broadcast; | |
43234a1e L |
415 | |
416 | /* Compressed disp8*N attribute. */ | |
417 | unsigned int memshift; | |
418 | ||
86fa6981 L |
419 | /* Prefer load or store in encoding. */ |
420 | enum | |
421 | { | |
422 | dir_encoding_default = 0, | |
423 | dir_encoding_load, | |
64c49ab3 JB |
424 | dir_encoding_store, |
425 | dir_encoding_swap | |
86fa6981 | 426 | } dir_encoding; |
891edac4 | 427 | |
41eb8e88 | 428 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
429 | enum |
430 | { | |
431 | disp_encoding_default = 0, | |
432 | disp_encoding_8bit, | |
41eb8e88 | 433 | disp_encoding_16bit, |
a501d77e L |
434 | disp_encoding_32bit |
435 | } disp_encoding; | |
f8a5c266 | 436 | |
6b6b6807 | 437 | /* Prefer the REX byte in encoding. */ |
5b7c81bd | 438 | bool rex_encoding; |
6b6b6807 | 439 | |
80d61d8d CL |
440 | /* Prefer the REX2 prefix in encoding. */ |
441 | bool rex2_encoding; | |
442 | ||
dd74a603 CL |
443 | /* No CSPAZO flags update. */ |
444 | bool has_nf; | |
445 | ||
b6f8c7c4 | 446 | /* Disable instruction size optimization. */ |
5b7c81bd | 447 | bool no_optimize; |
b6f8c7c4 | 448 | |
e346d50a | 449 | /* How to encode instructions. */ |
86fa6981 L |
450 | enum |
451 | { | |
e346d50a JB |
452 | encoding_default = 0, |
453 | encoding_vex, | |
454 | encoding_vex3, | |
eb3f3841 | 455 | encoding_egpr, /* REX2 or EVEX. */ |
e346d50a JB |
456 | encoding_evex, |
457 | encoding_evex512, | |
458 | encoding_error | |
459 | } encoding; | |
86fa6981 | 460 | |
d5de92cf L |
461 | /* REP prefix. */ |
462 | const char *rep_prefix; | |
463 | ||
165de32a L |
464 | /* HLE prefix. */ |
465 | const char *hle_prefix; | |
42164a71 | 466 | |
7e8b059b L |
467 | /* Have BND prefix. */ |
468 | const char *bnd_prefix; | |
469 | ||
04ef582a L |
470 | /* Have NOTRACK prefix. */ |
471 | const char *notrack_prefix; | |
472 | ||
891edac4 | 473 | /* Error message. */ |
a65babc9 | 474 | enum i386_error error; |
252b5132 RH |
475 | }; |
476 | ||
477 | typedef struct _i386_insn i386_insn; | |
478 | ||
43234a1e L |
479 | /* Link RC type with corresponding string, that'll be looked for in |
480 | asm. */ | |
481 | struct RC_name | |
482 | { | |
483 | enum rc_type type; | |
484 | const char *name; | |
485 | unsigned int len; | |
486 | }; | |
487 | ||
488 | static const struct RC_name RC_NamesTable[] = | |
489 | { | |
490 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
491 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
492 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
493 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
494 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
495 | }; | |
496 | ||
3bfea8ba L |
497 | /* To be indexed by segment register number. */ |
498 | static const unsigned char i386_seg_prefixes[] = { | |
499 | ES_PREFIX_OPCODE, | |
500 | CS_PREFIX_OPCODE, | |
501 | SS_PREFIX_OPCODE, | |
502 | DS_PREFIX_OPCODE, | |
503 | FS_PREFIX_OPCODE, | |
504 | GS_PREFIX_OPCODE | |
505 | }; | |
506 | ||
252b5132 RH |
507 | /* List of chars besides those in app.c:symbol_chars that can start an |
508 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 509 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 510 | #ifdef LEX_AT |
32137342 NC |
511 | "@" |
512 | #endif | |
513 | #ifdef LEX_QM | |
514 | "?" | |
252b5132 | 515 | #endif |
32137342 | 516 | ; |
252b5132 | 517 | |
b3983e5f JB |
518 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
519 | && !defined (TE_GNU) \ | |
520 | && !defined (TE_LINUX) \ | |
d85e70a3 | 521 | && !defined (TE_Haiku) \ |
b3983e5f JB |
522 | && !defined (TE_FreeBSD) \ |
523 | && !defined (TE_DragonFly) \ | |
524 | && !defined (TE_NetBSD)) | |
252b5132 | 525 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
526 | pre-processor is disabled, these aren't very useful. The option |
527 | --divide will remove '/' from this list. */ | |
528 | const char *i386_comment_chars = "#/"; | |
529 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 530 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 531 | |
b3b91714 AM |
532 | #else |
533 | const char *i386_comment_chars = "#"; | |
534 | #define PREFIX_SEPARATOR '/' | |
535 | #endif | |
536 | ||
252b5132 RH |
537 | /* This array holds the chars that only start a comment at the beginning of |
538 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
539 | .line and .file directives will appear in the pre-processed output. |
540 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 541 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
542 | #NO_APP at the beginning of its output. |
543 | Also note that comments started like this one will always work if | |
252b5132 | 544 | '/' isn't otherwise defined. */ |
b3b91714 | 545 | const char line_comment_chars[] = "#/"; |
252b5132 | 546 | |
63a0b638 | 547 | const char line_separator_chars[] = ";"; |
252b5132 | 548 | |
ce8a8b2f AM |
549 | /* Chars that can be used to separate mant from exp in floating point |
550 | nums. */ | |
252b5132 RH |
551 | const char EXP_CHARS[] = "eE"; |
552 | ||
ce8a8b2f AM |
553 | /* Chars that mean this number is a floating point constant |
554 | As in 0f12.456 | |
555 | or 0d1.2345e12. */ | |
de133cf9 | 556 | const char FLT_CHARS[] = "fFdDxXhHbB"; |
252b5132 | 557 | |
ce8a8b2f | 558 | /* Tables for lexical analysis. */ |
252b5132 RH |
559 | static char mnemonic_chars[256]; |
560 | static char register_chars[256]; | |
561 | static char operand_chars[256]; | |
252b5132 | 562 | |
ce8a8b2f | 563 | /* Lexical macros. */ |
252b5132 RH |
564 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
565 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
566 | #define is_space_char(x) ((x) == ' ') | |
252b5132 | 567 | |
d2b1a14d JB |
568 | /* All non-digit non-letter characters that may occur in an operand and |
569 | which aren't already in extra_symbol_chars[]. */ | |
570 | static const char operand_special_chars[] = "$+,)._~/<>|&^!=:@]"; | |
252b5132 RH |
571 | |
572 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
573 | effect this we maintain a stack of saved characters that we've smashed | |
574 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 575 | assembler instruction). */ |
252b5132 | 576 | static char save_stack[32]; |
ce8a8b2f | 577 | static char *save_stack_p; |
252b5132 RH |
578 | #define END_STRING_AND_SAVE(s) \ |
579 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
580 | #define RESTORE_END_STRING(s) \ | |
581 | do { *(s) = *--save_stack_p; } while (0) | |
582 | ||
47926f60 | 583 | /* The instruction we're assembling. */ |
252b5132 RH |
584 | static i386_insn i; |
585 | ||
586 | /* Possible templates for current insn. */ | |
d3b01414 | 587 | static templates current_templates; |
252b5132 | 588 | |
31b2323c L |
589 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
590 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
591 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 592 | |
47926f60 | 593 | /* Current operand we are working on. */ |
ee86248c | 594 | static int this_operand = -1; |
252b5132 | 595 | |
d0c2e3ec JB |
596 | /* Are we processing a .insn directive? */ |
597 | #define dot_insn() (i.tm.mnem_off == MN__insn) | |
598 | ||
ed719294 JB |
599 | enum i386_flag_code i386_flag_code; |
600 | #define flag_code i386_flag_code /* Permit to continue using original name. */ | |
4fa24527 | 601 | static unsigned int object_64bit; |
862be3fb | 602 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 603 | static int use_rela_relocations = 0; |
e379e5f3 L |
604 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
605 | static const char *tls_get_addr; | |
3e73aa7c | 606 | |
071c5d81 | 607 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7af8ed2d | 608 | |
351f65ca L |
609 | /* The ELF ABI to use. */ |
610 | enum x86_elf_abi | |
611 | { | |
612 | I386_ABI, | |
7f56bc95 L |
613 | X86_64_ABI, |
614 | X86_64_X32_ABI | |
351f65ca L |
615 | }; |
616 | ||
617 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 618 | #endif |
351f65ca | 619 | |
167ad85b TG |
620 | #if defined (TE_PE) || defined (TE_PEP) |
621 | /* Use big object file format. */ | |
622 | static int use_big_obj = 0; | |
623 | #endif | |
624 | ||
8dcea932 L |
625 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
626 | /* 1 if generating code for a shared library. */ | |
627 | static int shared = 0; | |
b52c4ee4 IB |
628 | |
629 | unsigned int x86_sframe_cfa_sp_reg; | |
3e3e792a | 630 | /* The other CFA base register for SFrame stack trace info. */ |
b52c4ee4 IB |
631 | unsigned int x86_sframe_cfa_fp_reg; |
632 | unsigned int x86_sframe_cfa_ra_reg; | |
633 | ||
8dcea932 L |
634 | #endif |
635 | ||
47926f60 KH |
636 | /* 1 for intel syntax, |
637 | 0 if att syntax. */ | |
638 | static int intel_syntax = 0; | |
252b5132 | 639 | |
4b5aaf5f L |
640 | static enum x86_64_isa |
641 | { | |
642 | amd64 = 1, /* AMD64 ISA. */ | |
643 | intel64 /* Intel64 ISA. */ | |
644 | } isa64; | |
e89c5eaa | 645 | |
1efbbeb4 L |
646 | /* 1 for intel mnemonic, |
647 | 0 if att mnemonic. */ | |
648 | static int intel_mnemonic = !SYSV386_COMPAT; | |
649 | ||
a60de03c JB |
650 | /* 1 if pseudo registers are permitted. */ |
651 | static int allow_pseudo_reg = 0; | |
652 | ||
47926f60 KH |
653 | /* 1 if register prefix % not required. */ |
654 | static int allow_naked_reg = 0; | |
252b5132 | 655 | |
33eaf5de | 656 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
657 | instructions supporting it, even if this prefix wasn't specified |
658 | explicitly. */ | |
659 | static int add_bnd_prefix = 0; | |
660 | ||
ba104c83 | 661 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
662 | static int allow_index_reg = 0; |
663 | ||
d022bddd IT |
664 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
665 | specified explicitly. */ | |
666 | static int omit_lock_prefix = 0; | |
667 | ||
e4e00185 AS |
668 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
669 | "lock addl $0, (%{re}sp)". */ | |
670 | static int avoid_fence = 0; | |
671 | ||
ae531041 L |
672 | /* 1 if lfence should be inserted after every load. */ |
673 | static int lfence_after_load = 0; | |
674 | ||
675 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
676 | static enum lfence_before_indirect_branch_kind | |
677 | { | |
678 | lfence_branch_none = 0, | |
679 | lfence_branch_register, | |
680 | lfence_branch_memory, | |
681 | lfence_branch_all | |
682 | } | |
683 | lfence_before_indirect_branch; | |
684 | ||
685 | /* Non-zero if lfence should be inserted before ret. */ | |
686 | static enum lfence_before_ret_kind | |
687 | { | |
688 | lfence_before_ret_none = 0, | |
689 | lfence_before_ret_not, | |
a09f656b | 690 | lfence_before_ret_or, |
691 | lfence_before_ret_shl | |
ae531041 L |
692 | } |
693 | lfence_before_ret; | |
694 | ||
0cb4071e L |
695 | /* 1 if the assembler should generate relax relocations. */ |
696 | ||
697 | static int generate_relax_relocations | |
698 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
699 | ||
7bab8ab5 | 700 | static enum check_kind |
daf50ae7 | 701 | { |
7bab8ab5 JB |
702 | check_none = 0, |
703 | check_warning, | |
704 | check_error | |
daf50ae7 | 705 | } |
7bab8ab5 | 706 | sse_check, operand_check = check_warning; |
daf50ae7 | 707 | |
e379e5f3 L |
708 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
709 | static int align_branch_power = 0; | |
710 | ||
711 | /* Types of branches to align. */ | |
712 | enum align_branch_kind | |
713 | { | |
714 | align_branch_none = 0, | |
715 | align_branch_jcc = 1, | |
716 | align_branch_fused = 2, | |
717 | align_branch_jmp = 3, | |
718 | align_branch_call = 4, | |
719 | align_branch_indirect = 5, | |
720 | align_branch_ret = 6 | |
721 | }; | |
722 | ||
723 | /* Type bits of branches to align. */ | |
724 | enum align_branch_bit | |
725 | { | |
726 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
727 | align_branch_fused_bit = 1 << align_branch_fused, | |
728 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
729 | align_branch_call_bit = 1 << align_branch_call, | |
730 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
731 | align_branch_ret_bit = 1 << align_branch_ret | |
732 | }; | |
733 | ||
734 | static unsigned int align_branch = (align_branch_jcc_bit | |
735 | | align_branch_fused_bit | |
736 | | align_branch_jmp_bit); | |
737 | ||
79d72f45 HL |
738 | /* Types of condition jump used by macro-fusion. */ |
739 | enum mf_jcc_kind | |
740 | { | |
741 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
742 | mf_jcc_jc, /* base opcode 0x72 */ | |
743 | mf_jcc_je, /* base opcode 0x74 */ | |
744 | mf_jcc_jna, /* base opcode 0x76 */ | |
745 | mf_jcc_js, /* base opcode 0x78 */ | |
746 | mf_jcc_jp, /* base opcode 0x7a */ | |
747 | mf_jcc_jl, /* base opcode 0x7c */ | |
748 | mf_jcc_jle, /* base opcode 0x7e */ | |
749 | }; | |
750 | ||
751 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
752 | enum mf_cmp_kind | |
753 | { | |
754 | mf_cmp_test_and, /* test/cmp */ | |
755 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
756 | mf_cmp_incdec /* inc/dec */ | |
757 | }; | |
758 | ||
e379e5f3 L |
759 | /* The maximum padding size for fused jcc. CMP like instruction can |
760 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
761 | prefixes. */ | |
762 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
763 | ||
764 | /* The maximum number of prefixes added for an instruction. */ | |
765 | static unsigned int align_branch_prefix_size = 5; | |
766 | ||
b6f8c7c4 L |
767 | /* Optimization: |
768 | 1. Clear the REX_W bit with register operand if possible. | |
769 | 2. Above plus use 128bit vector instruction to clear the full vector | |
770 | register. | |
771 | */ | |
772 | static int optimize = 0; | |
773 | ||
774 | /* Optimization: | |
775 | 1. Clear the REX_W bit with register operand if possible. | |
776 | 2. Above plus use 128bit vector instruction to clear the full vector | |
777 | register. | |
778 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
779 | "testb $imm7,%r8". | |
780 | */ | |
781 | static int optimize_for_space = 0; | |
782 | ||
2ca3ace5 L |
783 | /* Register prefix used for error message. */ |
784 | static const char *register_prefix = "%"; | |
785 | ||
47926f60 KH |
786 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
787 | leave, push, and pop instructions so that gcc has the same stack | |
788 | frame as in 32 bit mode. */ | |
789 | static char stackop_size = '\0'; | |
eecb386c | 790 | |
12b55ccc L |
791 | /* Non-zero to optimize code alignment. */ |
792 | int optimize_align_code = 1; | |
793 | ||
47926f60 KH |
794 | /* Non-zero to quieten some warnings. */ |
795 | static int quiet_warnings = 0; | |
a38cf1db | 796 | |
d59a54c2 JB |
797 | /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */ |
798 | static bool pre_386_16bit_warned; | |
799 | ||
47926f60 KH |
800 | /* CPU name. */ |
801 | static const char *cpu_arch_name = NULL; | |
6305a203 | 802 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 803 | |
47926f60 | 804 | /* CPU feature flags. */ |
cd75cd85 | 805 | i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
40fb9820 | 806 | |
3e624fa4 JB |
807 | /* ISA extensions available in 64-bit mode only. */ |
808 | static const i386_cpu_flags cpu_64_flags = CPU_ANY_64_FLAGS; | |
809 | ||
ccc9c027 L |
810 | /* If we have selected a cpu we are generating instructions for. */ |
811 | static int cpu_arch_tune_set = 0; | |
812 | ||
9103f4f4 | 813 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 814 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 | 815 | |
ccc9c027 | 816 | /* CPU instruction set architecture used. */ |
fbf3f584 | 817 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 818 | |
9103f4f4 | 819 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 820 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 821 | |
fddf5b5b AM |
822 | /* If set, conditional jumps are not automatically promoted to handle |
823 | larger than a byte offset. */ | |
f68697e8 | 824 | static bool no_cond_jump_promotion = false; |
fddf5b5b | 825 | |
5cc00775 JB |
826 | /* This will be set from an expression parser hook if there's any |
827 | applicable operator involved in an expression. */ | |
828 | static enum { | |
829 | expr_operator_none, | |
830 | expr_operator_present, | |
831 | expr_large_value, | |
832 | } expr_mode; | |
833 | ||
c0f3af97 L |
834 | /* Encode SSE instructions with VEX prefix. */ |
835 | static unsigned int sse2avx; | |
836 | ||
c8480b58 L |
837 | /* Encode aligned vector move as unaligned vector move. */ |
838 | static unsigned int use_unaligned_vector_move; | |
839 | ||
4fc85f37 | 840 | /* Maximum permitted vector size. */ |
fa88a361 HJ |
841 | #define VSZ128 0 |
842 | #define VSZ256 1 | |
843 | #define VSZ512 2 | |
4fc85f37 JB |
844 | #define VSZ_DEFAULT VSZ512 |
845 | static unsigned int vector_size = VSZ_DEFAULT; | |
846 | ||
539f890d L |
847 | /* Encode scalar AVX instructions with specific vector length. */ |
848 | static enum | |
849 | { | |
850 | vex128 = 0, | |
851 | vex256 | |
852 | } avxscalar; | |
853 | ||
03751133 L |
854 | /* Encode VEX WIG instructions with specific vex.w. */ |
855 | static enum | |
856 | { | |
857 | vexw0 = 0, | |
858 | vexw1 | |
859 | } vexwig; | |
860 | ||
43234a1e L |
861 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
862 | static enum | |
863 | { | |
864 | evexl128 = 0, | |
865 | evexl256, | |
866 | evexl512 | |
867 | } evexlig; | |
868 | ||
869 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
870 | static enum | |
871 | { | |
872 | evexw0 = 0, | |
873 | evexw1 | |
874 | } evexwig; | |
875 | ||
d3d3c6db IT |
876 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
877 | static enum rc_type evexrcig = rne; | |
878 | ||
29b0f896 | 879 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 880 | static symbolS *GOT_symbol; |
29b0f896 | 881 | |
a4447b93 RH |
882 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
883 | unsigned int x86_dwarf2_return_column; | |
884 | ||
885 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
886 | int x86_cie_data_alignment; | |
887 | ||
252b5132 | 888 | /* Interface to relax_segment. |
fddf5b5b AM |
889 | There are 3 major relax states for 386 jump insns because the |
890 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
891 | figuring out what sort of jump to choose to reach a given label. |
892 | ||
893 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
894 | branches which are handled by md_estimate_size_before_relax() and | |
895 | i386_generic_table_relax_frag(). */ | |
252b5132 | 896 | |
47926f60 | 897 | /* Types. */ |
93c2a809 AM |
898 | #define UNCOND_JUMP 0 |
899 | #define COND_JUMP 1 | |
900 | #define COND_JUMP86 2 | |
e379e5f3 L |
901 | #define BRANCH_PADDING 3 |
902 | #define BRANCH_PREFIX 4 | |
903 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 904 | |
47926f60 | 905 | /* Sizes. */ |
252b5132 RH |
906 | #define CODE16 1 |
907 | #define SMALL 0 | |
29b0f896 | 908 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 909 | #define BIG 2 |
29b0f896 | 910 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
911 | |
912 | #ifndef INLINE | |
913 | #ifdef __GNUC__ | |
914 | #define INLINE __inline__ | |
915 | #else | |
916 | #define INLINE | |
917 | #endif | |
918 | #endif | |
919 | ||
fddf5b5b AM |
920 | #define ENCODE_RELAX_STATE(type, size) \ |
921 | ((relax_substateT) (((type) << 2) | (size))) | |
922 | #define TYPE_FROM_RELAX_STATE(s) \ | |
923 | ((s) >> 2) | |
924 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
925 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
926 | |
927 | /* This table is used by relax_frag to promote short jumps to long | |
928 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
929 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
930 | don't allow a short jump in a 32 bit code segment to be promoted to | |
931 | a 16 bit offset jump because it's slower (requires data size | |
932 | prefix), and doesn't work, unless the destination is in the bottom | |
933 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
934 | ||
935 | const relax_typeS md_relax_table[] = | |
936 | { | |
24eab124 AM |
937 | /* The fields are: |
938 | 1) most positive reach of this state, | |
939 | 2) most negative reach of this state, | |
93c2a809 | 940 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 941 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 942 | |
fddf5b5b | 943 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
944 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
945 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
946 | /* dword jmp adds 4 bytes to frag: | |
947 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 948 | {0, 0, 4, 0}, |
93c2a809 AM |
949 | /* word jmp adds 2 byte2 to frag: |
950 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
951 | {0, 0, 2, 0}, |
952 | ||
93c2a809 AM |
953 | /* COND_JUMP states. */ |
954 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
955 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
956 | /* dword conditionals adds 5 bytes to frag: | |
957 | 1 extra opcode byte, 4 displacement bytes. */ | |
958 | {0, 0, 5, 0}, | |
fddf5b5b | 959 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
960 | 1 extra opcode byte, 2 displacement bytes. */ |
961 | {0, 0, 3, 0}, | |
962 | ||
963 | /* COND_JUMP86 states. */ | |
964 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
965 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
966 | /* dword conditionals adds 5 bytes to frag: | |
967 | 1 extra opcode byte, 4 displacement bytes. */ | |
968 | {0, 0, 5, 0}, | |
969 | /* word conditionals add 4 bytes to frag: | |
970 | 1 displacement byte and a 3 byte long branch insn. */ | |
971 | {0, 0, 4, 0} | |
252b5132 RH |
972 | }; |
973 | ||
6ceeed25 | 974 | #define ARCH(n, t, f, s) \ |
4fc85f37 | 975 | { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \ |
ae89daec JB |
976 | CPU_NONE_FLAGS } |
977 | #define SUBARCH(n, e, d, s) \ | |
4fc85f37 | 978 | { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \ |
ae89daec | 979 | CPU_ ## d ## _FLAGS } |
4fc85f37 JB |
980 | #define VECARCH(n, e, d, v) \ |
981 | { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \ | |
982 | CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS } | |
6ceeed25 | 983 | |
9103f4f4 L |
984 | static const arch_entry cpu_arch[] = |
985 | { | |
3ce2ebcf JB |
986 | /* Do not replace the first two entries - i386_target_format() and |
987 | set_cpu_arch() rely on them being there in this order. */ | |
6ceeed25 JB |
988 | ARCH (generic32, GENERIC32, GENERIC32, false), |
989 | ARCH (generic64, GENERIC64, GENERIC64, false), | |
990 | ARCH (i8086, UNKNOWN, NONE, false), | |
4d97c5c8 JB |
991 | ARCH (i186, UNKNOWN, 186, false), |
992 | ARCH (i286, UNKNOWN, 286, false), | |
993 | ARCH (i386, I386, 386, false), | |
994 | ARCH (i486, I486, 486, false), | |
995 | ARCH (i586, PENTIUM, 586, false), | |
4d97c5c8 | 996 | ARCH (pentium, PENTIUM, 586, false), |
c8be4b6f | 997 | ARCH (i686, I686, 686, false), |
6ceeed25 JB |
998 | ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false), |
999 | ARCH (pentiumii, PENTIUMPRO, P2, false), | |
1000 | ARCH (pentiumiii, PENTIUMPRO, P3, false), | |
1001 | ARCH (pentium4, PENTIUM4, P4, false), | |
1002 | ARCH (prescott, NOCONA, CORE, false), | |
1003 | ARCH (nocona, NOCONA, NOCONA, false), | |
1004 | ARCH (yonah, CORE, CORE, true), | |
1005 | ARCH (core, CORE, CORE, false), | |
1006 | ARCH (merom, CORE2, CORE2, true), | |
1007 | ARCH (core2, CORE2, CORE2, false), | |
1008 | ARCH (corei7, COREI7, COREI7, false), | |
1009 | ARCH (iamcu, IAMCU, IAMCU, false), | |
1010 | ARCH (k6, K6, K6, false), | |
1011 | ARCH (k6_2, K6, K6_2, false), | |
1012 | ARCH (athlon, ATHLON, ATHLON, false), | |
1013 | ARCH (sledgehammer, K8, K8, true), | |
1014 | ARCH (opteron, K8, K8, false), | |
1015 | ARCH (k8, K8, K8, false), | |
1016 | ARCH (amdfam10, AMDFAM10, AMDFAM10, false), | |
1017 | ARCH (bdver1, BD, BDVER1, false), | |
1018 | ARCH (bdver2, BD, BDVER2, false), | |
1019 | ARCH (bdver3, BD, BDVER3, false), | |
1020 | ARCH (bdver4, BD, BDVER4, false), | |
1021 | ARCH (znver1, ZNVER, ZNVER1, false), | |
1022 | ARCH (znver2, ZNVER, ZNVER2, false), | |
1023 | ARCH (znver3, ZNVER, ZNVER3, false), | |
b0e8fa7f | 1024 | ARCH (znver4, ZNVER, ZNVER4, false), |
b143c979 | 1025 | ARCH (znver5, ZNVER, ZNVER5, false), |
6ceeed25 JB |
1026 | ARCH (btver1, BT, BTVER1, false), |
1027 | ARCH (btver2, BT, BTVER2, false), | |
1028 | ||
4d97c5c8 JB |
1029 | SUBARCH (8087, 8087, ANY_8087, false), |
1030 | SUBARCH (87, NONE, ANY_8087, false), /* Disable only! */ | |
ae89daec JB |
1031 | SUBARCH (287, 287, ANY_287, false), |
1032 | SUBARCH (387, 387, ANY_387, false), | |
1033 | SUBARCH (687, 687, ANY_687, false), | |
4d97c5c8 | 1034 | SUBARCH (cmov, CMOV, CMOV, false), |
88bd2203 | 1035 | SUBARCH (fxsr, FXSR, ANY_FXSR, false), |
ae89daec JB |
1036 | SUBARCH (mmx, MMX, ANY_MMX, false), |
1037 | SUBARCH (sse, SSE, ANY_SSE, false), | |
1038 | SUBARCH (sse2, SSE2, ANY_SSE2, false), | |
1039 | SUBARCH (sse3, SSE3, ANY_SSE3, false), | |
1040 | SUBARCH (sse4a, SSE4A, ANY_SSE4A, false), | |
1041 | SUBARCH (ssse3, SSSE3, ANY_SSSE3, false), | |
1042 | SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false), | |
1043 | SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false), | |
1044 | SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false), | |
4fc85f37 JB |
1045 | VECARCH (avx, AVX, ANY_AVX, reset), |
1046 | VECARCH (avx2, AVX2, ANY_AVX2, reset), | |
1047 | VECARCH (avx512f, AVX512F, ANY_AVX512F, reset), | |
1048 | VECARCH (avx512cd, AVX512CD, ANY_AVX512CD, reset), | |
1049 | VECARCH (avx512er, AVX512ER, ANY_AVX512ER, reset), | |
1050 | VECARCH (avx512pf, AVX512PF, ANY_AVX512PF, reset), | |
1051 | VECARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, reset), | |
1052 | VECARCH (avx512bw, AVX512BW, ANY_AVX512BW, reset), | |
1053 | VECARCH (avx512vl, AVX512VL, ANY_AVX512VL, reset), | |
cafa5ef7 | 1054 | SUBARCH (monitor, MONITOR, MONITOR, false), |
25626f79 JB |
1055 | SUBARCH (vmx, VMX, ANY_VMX, false), |
1056 | SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false), | |
ae89daec | 1057 | SUBARCH (smx, SMX, SMX, false), |
5091b9ee JB |
1058 | SUBARCH (xsave, XSAVE, ANY_XSAVE, false), |
1059 | SUBARCH (xsaveopt, XSAVEOPT, ANY_XSAVEOPT, false), | |
1060 | SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false), | |
1061 | SUBARCH (xsaves, XSAVES, ANY_XSAVES, false), | |
1062 | SUBARCH (aes, AES, ANY_AES, false), | |
d54678eb JB |
1063 | SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false), |
1064 | SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true), | |
ae89daec JB |
1065 | SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false), |
1066 | SUBARCH (rdrnd, RDRND, RDRND, false), | |
5091b9ee | 1067 | SUBARCH (f16c, F16C, ANY_F16C, false), |
ae89daec | 1068 | SUBARCH (bmi2, BMI2, BMI2, false), |
5091b9ee JB |
1069 | SUBARCH (fma, FMA, ANY_FMA, false), |
1070 | SUBARCH (fma4, FMA4, ANY_FMA4, false), | |
1071 | SUBARCH (xop, XOP, ANY_XOP, false), | |
1072 | SUBARCH (lwp, LWP, ANY_LWP, false), | |
ae89daec JB |
1073 | SUBARCH (movbe, MOVBE, MOVBE, false), |
1074 | SUBARCH (cx16, CX16, CX16, false), | |
c3bb24f5 | 1075 | SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false), |
25626f79 | 1076 | SUBARCH (ept, EPT, ANY_EPT, false), |
ae89daec JB |
1077 | SUBARCH (lzcnt, LZCNT, LZCNT, false), |
1078 | SUBARCH (popcnt, POPCNT, POPCNT, false), | |
1079 | SUBARCH (hle, HLE, HLE, false), | |
760ab3d0 JB |
1080 | SUBARCH (rtm, RTM, ANY_RTM, false), |
1081 | SUBARCH (tsx, TSX, TSX, false), | |
ae89daec JB |
1082 | SUBARCH (invpcid, INVPCID, INVPCID, false), |
1083 | SUBARCH (clflush, CLFLUSH, CLFLUSH, false), | |
1084 | SUBARCH (nop, NOP, NOP, false), | |
1085 | SUBARCH (syscall, SYSCALL, SYSCALL, false), | |
1086 | SUBARCH (rdtscp, RDTSCP, RDTSCP, false), | |
5091b9ee JB |
1087 | SUBARCH (3dnow, 3DNOW, ANY_3DNOW, false), |
1088 | SUBARCH (3dnowa, 3DNOWA, ANY_3DNOWA, false), | |
ae89daec | 1089 | SUBARCH (padlock, PADLOCK, PADLOCK, false), |
0919e770 JB |
1090 | SUBARCH (pacifica, SVME, ANY_SVME, true), |
1091 | SUBARCH (svme, SVME, ANY_SVME, false), | |
ae89daec JB |
1092 | SUBARCH (abm, ABM, ABM, false), |
1093 | SUBARCH (bmi, BMI, BMI, false), | |
1094 | SUBARCH (tbm, TBM, TBM, false), | |
1095 | SUBARCH (adx, ADX, ADX, false), | |
1096 | SUBARCH (rdseed, RDSEED, RDSEED, false), | |
1097 | SUBARCH (prfchw, PRFCHW, PRFCHW, false), | |
1098 | SUBARCH (smap, SMAP, SMAP, false), | |
5091b9ee JB |
1099 | SUBARCH (mpx, MPX, ANY_MPX, false), |
1100 | SUBARCH (sha, SHA, ANY_SHA, false), | |
ae89daec JB |
1101 | SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false), |
1102 | SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false), | |
1103 | SUBARCH (se1, SE1, SE1, false), | |
1104 | SUBARCH (clwb, CLWB, CLWB, false), | |
4fc85f37 JB |
1105 | VECARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, reset), |
1106 | VECARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, reset), | |
1107 | VECARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, reset), | |
1108 | VECARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, reset), | |
1109 | VECARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, reset), | |
1110 | VECARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, reset), | |
1111 | VECARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, reset), | |
1112 | VECARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, reset), | |
1113 | VECARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, reset), | |
ae89daec JB |
1114 | SUBARCH (clzero, CLZERO, CLZERO, false), |
1115 | SUBARCH (mwaitx, MWAITX, MWAITX, false), | |
5091b9ee | 1116 | SUBARCH (ospke, OSPKE, ANY_OSPKE, false), |
ae89daec JB |
1117 | SUBARCH (rdpid, RDPID, RDPID, false), |
1118 | SUBARCH (ptwrite, PTWRITE, PTWRITE, false), | |
4d97c5c8 JB |
1119 | SUBARCH (ibt, IBT, IBT, false), |
1120 | SUBARCH (shstk, SHSTK, SHSTK, false), | |
88bd2203 | 1121 | SUBARCH (gfni, GFNI, ANY_GFNI, false), |
4fc85f37 JB |
1122 | VECARCH (vaes, VAES, ANY_VAES, reset), |
1123 | VECARCH (vpclmulqdq, VPCLMULQDQ, ANY_VPCLMULQDQ, reset), | |
ae89daec JB |
1124 | SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false), |
1125 | SUBARCH (pconfig, PCONFIG, PCONFIG, false), | |
1126 | SUBARCH (waitpkg, WAITPKG, WAITPKG, false), | |
1127 | SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false), | |
1128 | SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false), | |
1129 | SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false), | |
5091b9ee | 1130 | SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false), |
d100d8c1 | 1131 | SUBARCH (amx_complex, AMX_COMPLEX, ANY_AMX_COMPLEX, false), |
ae89daec | 1132 | SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false), |
4d97c5c8 JB |
1133 | SUBARCH (movdiri, MOVDIRI, MOVDIRI, false), |
1134 | SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false), | |
4fc85f37 JB |
1135 | VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset), |
1136 | VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT, | |
1137 | ANY_AVX512_VP2INTERSECT, reset), | |
4d97c5c8 JB |
1138 | SUBARCH (tdx, TDX, TDX, false), |
1139 | SUBARCH (enqcmd, ENQCMD, ENQCMD, false), | |
1140 | SUBARCH (serialize, SERIALIZE, SERIALIZE, false), | |
ae89daec JB |
1141 | SUBARCH (rdpru, RDPRU, RDPRU, false), |
1142 | SUBARCH (mcommit, MCOMMIT, MCOMMIT, false), | |
0919e770 | 1143 | SUBARCH (sev_es, SEV_ES, ANY_SEV_ES, false), |
760ab3d0 | 1144 | SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false), |
88bd2203 JB |
1145 | SUBARCH (kl, KL, ANY_KL, false), |
1146 | SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false), | |
4d97c5c8 JB |
1147 | SUBARCH (uintr, UINTR, UINTR, false), |
1148 | SUBARCH (hreset, HRESET, HRESET, false), | |
4fc85f37 | 1149 | VECARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, reset), |
ef07be45 | 1150 | SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false), |
4fc85f37 JB |
1151 | VECARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, reset), |
1152 | VECARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, reset), | |
4d97c5c8 JB |
1153 | SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false), |
1154 | SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), | |
1155 | SUBARCH (msrlist, MSRLIST, MSRLIST, false), | |
4fc85f37 | 1156 | VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset), |
4d97c5c8 | 1157 | SUBARCH (rao_int, RAO_INT, RAO_INT, false), |
0919e770 | 1158 | SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false), |
c88ed92f ZJ |
1159 | SUBARCH (fred, FRED, ANY_FRED, false), |
1160 | SUBARCH (lkgs, LKGS, ANY_LKGS, false), | |
4fc85f37 JB |
1161 | VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset), |
1162 | VECARCH (sha512, SHA512, ANY_SHA512, reset), | |
1163 | VECARCH (sm3, SM3, ANY_SM3, reset), | |
1164 | VECARCH (sm4, SM4, ANY_SM4, reset), | |
b5c37946 | 1165 | SUBARCH (pbndkb, PBNDKB, PBNDKB, false), |
4fc85f37 | 1166 | VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), |
8170af78 | 1167 | SUBARCH (user_msr, USER_MSR, USER_MSR, false), |
80d61d8d | 1168 | SUBARCH (apx_f, APX_F, APX_F, false), |
293f5f65 L |
1169 | }; |
1170 | ||
6ceeed25 JB |
1171 | #undef SUBARCH |
1172 | #undef ARCH | |
1173 | ||
704209c0 | 1174 | #ifdef I386COFF |
a6c24e68 NC |
1175 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1176 | is allowed to be optional. */ | |
1177 | ||
1178 | static symbolS * | |
1179 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1180 | { | |
1181 | addressT align = 0; | |
1182 | ||
1183 | SKIP_WHITESPACE (); | |
1184 | ||
7ab9ffdd | 1185 | if (needs_align |
a6c24e68 NC |
1186 | && *input_line_pointer == ',') |
1187 | { | |
1188 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1189 | |
a6c24e68 NC |
1190 | if (align == (addressT) -1) |
1191 | return NULL; | |
1192 | } | |
1193 | else | |
1194 | { | |
1195 | if (size >= 8) | |
1196 | align = 3; | |
1197 | else if (size >= 4) | |
1198 | align = 2; | |
1199 | else if (size >= 2) | |
1200 | align = 1; | |
1201 | else | |
1202 | align = 0; | |
1203 | } | |
1204 | ||
1205 | bss_alloc (symbolP, size, align); | |
1206 | return symbolP; | |
1207 | } | |
1208 | ||
704209c0 | 1209 | static void |
a6c24e68 NC |
1210 | pe_lcomm (int needs_align) |
1211 | { | |
1212 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1213 | } | |
704209c0 | 1214 | #endif |
a6c24e68 | 1215 | |
29b0f896 AM |
1216 | const pseudo_typeS md_pseudo_table[] = |
1217 | { | |
1218 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1219 | {"align", s_align_bytes, 0}, | |
1220 | #else | |
1221 | {"align", s_align_ptwo, 0}, | |
1222 | #endif | |
1223 | {"arch", set_cpu_arch, 0}, | |
d4064aad | 1224 | #ifdef OBJ_AOUT |
29b0f896 | 1225 | {"bss", s_bss, 0}, |
d4064aad JB |
1226 | #endif |
1227 | #ifdef I386COFF | |
a6c24e68 | 1228 | {"lcomm", pe_lcomm, 1}, |
29b0f896 AM |
1229 | #endif |
1230 | {"ffloat", float_cons, 'f'}, | |
1231 | {"dfloat", float_cons, 'd'}, | |
1232 | {"tfloat", float_cons, 'x'}, | |
7d19d096 | 1233 | {"hfloat", float_cons, 'h'}, |
de133cf9 | 1234 | {"bfloat16", float_cons, 'b'}, |
29b0f896 | 1235 | {"value", cons, 2}, |
d182319b | 1236 | {"slong", signed_cons, 4}, |
edd67638 | 1237 | {"insn", s_insn, 0}, |
1e7dd4a0 | 1238 | {"noopt", s_noopt, 0}, |
29b0f896 AM |
1239 | {"optim", s_ignore, 0}, |
1240 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1241 | {"code16", set_code_flag, CODE_16BIT}, | |
1242 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1243 | #ifdef BFD64 |
29b0f896 | 1244 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1245 | #endif |
29b0f896 AM |
1246 | {"intel_syntax", set_intel_syntax, 1}, |
1247 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1248 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1249 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1250 | {"allow_index_reg", set_allow_index_reg, 1}, |
1251 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1252 | {"sse_check", set_check, 0}, |
1253 | {"operand_check", set_check, 1}, | |
3b22753a L |
1254 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1255 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1256 | #else |
68d20676 | 1257 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1258 | {"loc", dwarf2_directive_loc, 0}, |
1259 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1260 | #endif |
6482c264 NC |
1261 | #ifdef TE_PE |
1262 | {"secrel32", pe_directive_secrel, 0}, | |
145667f8 | 1263 | {"secidx", pe_directive_secidx, 0}, |
6482c264 | 1264 | #endif |
29b0f896 AM |
1265 | {0, 0, 0} |
1266 | }; | |
1267 | ||
1268 | /* For interface with expression (). */ | |
1269 | extern char *input_line_pointer; | |
1270 | ||
1271 | /* Hash table for instruction mnemonic lookup. */ | |
629310ab | 1272 | static htab_t op_hash; |
29b0f896 AM |
1273 | |
1274 | /* Hash table for register lookup. */ | |
629310ab | 1275 | static htab_t reg_hash; |
29b0f896 | 1276 | \f |
ce8a8b2f AM |
1277 | /* Various efficient no-op patterns for aligning code labels. |
1278 | Note: Don't try to assemble the instructions in the comments. | |
1279 | 0L and 0w are not legal. */ | |
62a02d25 L |
1280 | static const unsigned char f32_1[] = |
1281 | {0x90}; /* nop */ | |
1282 | static const unsigned char f32_2[] = | |
1283 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1284 | static const unsigned char f32_3[] = | |
1285 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
ad9f3230 JB |
1286 | #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */ |
1287 | static const unsigned char f32_5[] = | |
1288 | {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */ | |
62a02d25 L |
1289 | static const unsigned char f32_6[] = |
1290 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
ad9f3230 JB |
1291 | #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */ |
1292 | static const unsigned char f32_8[] = | |
1293 | {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */ | |
d164359d JB |
1294 | static const unsigned char f64_3[] = |
1295 | {0x48,0x89,0xf6}; /* mov %rsi,%rsi */ | |
1296 | static const unsigned char f64_4[] = | |
1297 | {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */ | |
1298 | #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */ | |
1299 | static const unsigned char f64_6[] = | |
1300 | {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */ | |
1301 | static const unsigned char f64_7[] = | |
1302 | {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */ | |
1303 | #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */ | |
1304 | static const unsigned char f64_9[] = | |
1305 | {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */ | |
5e0729b6 | 1306 | #define f16_2 (f64_3 + 1) /* mov %si,%si */ |
62a02d25 | 1307 | static const unsigned char f16_3[] = |
3ae729d5 | 1308 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
ad9f3230 JB |
1309 | #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */ |
1310 | static const unsigned char f16_5[] = | |
1311 | {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */ | |
3ae729d5 L |
1312 | static const unsigned char jump_disp8[] = |
1313 | {0xeb}; /* jmp disp8 */ | |
1314 | static const unsigned char jump32_disp32[] = | |
1315 | {0xe9}; /* jmp disp32 */ | |
1316 | static const unsigned char jump16_disp32[] = | |
1317 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1318 | /* 32-bit NOPs patterns. */ |
1319 | static const unsigned char *const f32_patt[] = { | |
ad9f3230 | 1320 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8 |
62a02d25 | 1321 | }; |
d164359d JB |
1322 | /* 64-bit NOPs patterns. */ |
1323 | static const unsigned char *const f64_patt[] = { | |
1324 | f32_1, f32_2, f64_3, f64_4, f64_5, f64_6, f64_7, f64_8, f64_9 | |
1325 | }; | |
62a02d25 L |
1326 | /* 16-bit NOPs patterns. */ |
1327 | static const unsigned char *const f16_patt[] = { | |
ad9f3230 | 1328 | f32_1, f16_2, f16_3, f16_4, f16_5 |
62a02d25 L |
1329 | }; |
1330 | /* nopl (%[re]ax) */ | |
1331 | static const unsigned char alt_3[] = | |
1332 | {0x0f,0x1f,0x00}; | |
1333 | /* nopl 0(%[re]ax) */ | |
1334 | static const unsigned char alt_4[] = | |
1335 | {0x0f,0x1f,0x40,0x00}; | |
1336 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1337 | #define alt_5 (alt_6 + 1) |
62a02d25 L |
1338 | /* nopw 0(%[re]ax,%[re]ax,1) */ |
1339 | static const unsigned char alt_6[] = | |
1340 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1341 | /* nopl 0L(%[re]ax) */ | |
1342 | static const unsigned char alt_7[] = | |
1343 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1344 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1345 | #define alt_8 (alt_9 + 1) |
62a02d25 L |
1346 | /* nopw 0L(%[re]ax,%[re]ax,1) */ |
1347 | static const unsigned char alt_9[] = | |
1348 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1349 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1350 | #define alt_10 (alt_11 + 1) |
3ae729d5 L |
1351 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1352 | static const unsigned char alt_11[] = | |
1353 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1354 | /* 32-bit and 64-bit NOPs patterns. */ |
1355 | static const unsigned char *const alt_patt[] = { | |
1356 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1357 | alt_9, alt_10, alt_11 |
62a02d25 L |
1358 | }; |
1359 | ||
1360 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1361 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1362 | ||
1363 | static void | |
1364 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1365 | int count, int max_single_nop_size) | |
1366 | ||
1367 | { | |
3ae729d5 L |
1368 | /* Place the longer NOP first. */ |
1369 | int last; | |
1370 | int offset; | |
3076e594 NC |
1371 | const unsigned char *nops; |
1372 | ||
1373 | if (max_single_nop_size < 1) | |
1374 | { | |
1375 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1376 | max_single_nop_size); | |
1377 | return; | |
1378 | } | |
1379 | ||
1380 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1381 | last = count % max_single_nop_size; |
1382 | ||
1383 | count -= last; | |
1384 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1385 | memcpy (where + offset, nops, max_single_nop_size); | |
1386 | ||
1387 | if (last) | |
1388 | { | |
1389 | nops = patt[last - 1]; | |
ad9f3230 | 1390 | memcpy (where + offset, nops, last); |
3ae729d5 | 1391 | } |
62a02d25 L |
1392 | } |
1393 | ||
3ae729d5 L |
1394 | static INLINE int |
1395 | fits_in_imm7 (offsetT num) | |
1396 | { | |
1397 | return (num & 0x7f) == num; | |
1398 | } | |
1399 | ||
1400 | static INLINE int | |
1401 | fits_in_imm31 (offsetT num) | |
1402 | { | |
1403 | return (num & 0x7fffffff) == num; | |
1404 | } | |
62a02d25 L |
1405 | |
1406 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1407 | single NOP instruction LIMIT. */ | |
1408 | ||
1409 | void | |
3ae729d5 | 1410 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1411 | { |
3ae729d5 | 1412 | const unsigned char *const *patt = NULL; |
62a02d25 | 1413 | int max_single_nop_size; |
3ae729d5 L |
1414 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1415 | int max_number_of_nops; | |
62a02d25 | 1416 | |
3ae729d5 | 1417 | switch (fragP->fr_type) |
62a02d25 | 1418 | { |
3ae729d5 L |
1419 | case rs_fill_nop: |
1420 | case rs_align_code: | |
1421 | break; | |
e379e5f3 L |
1422 | case rs_machine_dependent: |
1423 | /* Allow NOP padding for jumps and calls. */ | |
1424 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1425 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1426 | break; | |
1427 | /* Fall through. */ | |
3ae729d5 | 1428 | default: |
62a02d25 L |
1429 | return; |
1430 | } | |
1431 | ||
ccc9c027 L |
1432 | /* We need to decide which NOP sequence to use for 32bit and |
1433 | 64bit. When -mtune= is used: | |
4eed87de | 1434 | |
c8be4b6f | 1435 | 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and |
76bc74dc | 1436 | PROCESSOR_GENERIC32, f32_patt will be used. |
80b8656c L |
1437 | 2. For the rest, alt_patt will be used. |
1438 | ||
1439 | When -mtune= isn't used, alt_patt will be used if | |
d164359d | 1440 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will |
76bc74dc | 1441 | be used. |
ccc9c027 L |
1442 | |
1443 | When -march= or .arch is used, we can't use anything beyond | |
1444 | cpu_arch_isa_flags. */ | |
1445 | ||
d12c7ab8 | 1446 | if (fragP->tc_frag_data.code == CODE_16BIT) |
ccc9c027 | 1447 | { |
3ae729d5 L |
1448 | patt = f16_patt; |
1449 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1450 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1451 | max_number_of_nops = 2; | |
252b5132 | 1452 | } |
33fef721 | 1453 | else |
ccc9c027 | 1454 | { |
d164359d | 1455 | patt = fragP->tc_frag_data.code == CODE_64BIT ? f64_patt : f32_patt; |
fbf3f584 | 1456 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 | 1457 | { |
cd75cd85 JB |
1458 | /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless |
1459 | explicitly disabled. */ | |
d12c7ab8 | 1460 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1461 | { |
1462 | case PROCESSOR_UNKNOWN: | |
1463 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 | 1464 | optimize with nops. */ |
9f314ead | 1465 | if (fragP->tc_frag_data.isanop) |
80b8656c | 1466 | patt = alt_patt; |
ccc9c027 | 1467 | break; |
c8be4b6f JB |
1468 | |
1469 | case PROCESSOR_PENTIUMPRO: | |
ccc9c027 L |
1470 | case PROCESSOR_PENTIUM4: |
1471 | case PROCESSOR_NOCONA: | |
ef05d495 | 1472 | case PROCESSOR_CORE: |
76bc74dc | 1473 | case PROCESSOR_CORE2: |
bd5295b2 | 1474 | case PROCESSOR_COREI7: |
76bc74dc | 1475 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1476 | case PROCESSOR_K6: |
1477 | case PROCESSOR_ATHLON: | |
1478 | case PROCESSOR_K8: | |
4eed87de | 1479 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1480 | case PROCESSOR_BD: |
029f3522 | 1481 | case PROCESSOR_ZNVER: |
7b458c12 | 1482 | case PROCESSOR_BT: |
cd75cd85 JB |
1483 | if (fragP->tc_frag_data.cpunop) |
1484 | patt = alt_patt; | |
ccc9c027 | 1485 | break; |
cd75cd85 | 1486 | |
76bc74dc | 1487 | case PROCESSOR_I386: |
ccc9c027 L |
1488 | case PROCESSOR_I486: |
1489 | case PROCESSOR_PENTIUM: | |
c8be4b6f | 1490 | case PROCESSOR_I686: |
81486035 | 1491 | case PROCESSOR_IAMCU: |
ccc9c027 | 1492 | case PROCESSOR_GENERIC32: |
ccc9c027 | 1493 | break; |
c368d2a8 JB |
1494 | case PROCESSOR_NONE: |
1495 | abort (); | |
4eed87de | 1496 | } |
ccc9c027 L |
1497 | } |
1498 | else | |
1499 | { | |
fbf3f584 | 1500 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1501 | { |
1502 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1503 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1504 | PROCESSOR_UNKNOWN. */ |
1505 | abort (); | |
1506 | break; | |
1507 | ||
cd75cd85 | 1508 | default: |
ccc9c027 | 1509 | /* We use cpu_arch_isa_flags to check if we CAN optimize |
22109423 | 1510 | with nops. */ |
9f314ead | 1511 | if (fragP->tc_frag_data.isanop) |
80b8656c | 1512 | patt = alt_patt; |
ccc9c027 | 1513 | break; |
cd75cd85 | 1514 | |
c368d2a8 JB |
1515 | case PROCESSOR_NONE: |
1516 | abort (); | |
4eed87de | 1517 | } |
ccc9c027 L |
1518 | } |
1519 | ||
d164359d | 1520 | if (patt != alt_patt) |
76bc74dc | 1521 | { |
d164359d JB |
1522 | max_single_nop_size = patt == f32_patt ? ARRAY_SIZE (f32_patt) |
1523 | : ARRAY_SIZE (f64_patt); | |
3ae729d5 L |
1524 | /* Limit number of NOPs to 2 for older processors. */ |
1525 | max_number_of_nops = 2; | |
76bc74dc L |
1526 | } |
1527 | else | |
1528 | { | |
3ae729d5 L |
1529 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1530 | /* Limit number of NOPs to 7 for newer processors. */ | |
1531 | max_number_of_nops = 7; | |
1532 | } | |
1533 | } | |
1534 | ||
1535 | if (limit == 0) | |
1536 | limit = max_single_nop_size; | |
1537 | ||
1538 | if (fragP->fr_type == rs_fill_nop) | |
1539 | { | |
1540 | /* Output NOPs for .nop directive. */ | |
1541 | if (limit > max_single_nop_size) | |
1542 | { | |
1543 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1544 | _("invalid single nop size: %d " | |
1545 | "(expect within [0, %d])"), | |
1546 | limit, max_single_nop_size); | |
1547 | return; | |
1548 | } | |
1549 | } | |
e379e5f3 | 1550 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1551 | fragP->fr_var = count; |
1552 | ||
0aa5d0c9 JB |
1553 | /* Emit a plain NOP first when the last thing we saw may not have been |
1554 | a proper instruction (e.g. a stand-alone prefix or .byte). */ | |
1555 | if (!fragP->tc_frag_data.last_insn_normal) | |
1556 | { | |
1557 | *where++ = 0x90; | |
1558 | --count; | |
1559 | } | |
1560 | ||
3ae729d5 L |
1561 | if ((count / max_single_nop_size) > max_number_of_nops) |
1562 | { | |
1563 | /* Generate jump over NOPs. */ | |
1564 | offsetT disp = count - 2; | |
1565 | if (fits_in_imm7 (disp)) | |
1566 | { | |
1567 | /* Use "jmp disp8" if possible. */ | |
1568 | count = disp; | |
1569 | where[0] = jump_disp8[0]; | |
1570 | where[1] = count; | |
1571 | where += 2; | |
1572 | } | |
1573 | else | |
1574 | { | |
1575 | unsigned int size_of_jump; | |
1576 | ||
1577 | if (flag_code == CODE_16BIT) | |
1578 | { | |
1579 | where[0] = jump16_disp32[0]; | |
1580 | where[1] = jump16_disp32[1]; | |
1581 | size_of_jump = 2; | |
1582 | } | |
1583 | else | |
1584 | { | |
1585 | where[0] = jump32_disp32[0]; | |
1586 | size_of_jump = 1; | |
1587 | } | |
1588 | ||
1589 | count -= size_of_jump + 4; | |
1590 | if (!fits_in_imm31 (count)) | |
1591 | { | |
1592 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1593 | _("jump over nop padding out of range")); | |
1594 | return; | |
1595 | } | |
1596 | ||
1597 | md_number_to_chars (where + size_of_jump, count, 4); | |
1598 | where += size_of_jump + 4; | |
76bc74dc | 1599 | } |
ccc9c027 | 1600 | } |
3ae729d5 L |
1601 | |
1602 | /* Generate multiple NOPs. */ | |
1603 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1604 | } |
1605 | ||
c6fb90c8 | 1606 | static INLINE int |
0dfbf9d7 | 1607 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1608 | { |
0dfbf9d7 | 1609 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1610 | { |
1611 | case 3: | |
0dfbf9d7 | 1612 | if (x->array[2]) |
c6fb90c8 | 1613 | return 0; |
1a0670f3 | 1614 | /* Fall through. */ |
c6fb90c8 | 1615 | case 2: |
0dfbf9d7 | 1616 | if (x->array[1]) |
c6fb90c8 | 1617 | return 0; |
1a0670f3 | 1618 | /* Fall through. */ |
c6fb90c8 | 1619 | case 1: |
0dfbf9d7 | 1620 | return !x->array[0]; |
c6fb90c8 L |
1621 | default: |
1622 | abort (); | |
1623 | } | |
40fb9820 L |
1624 | } |
1625 | ||
c6fb90c8 | 1626 | static INLINE void |
0dfbf9d7 | 1627 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1628 | { |
0dfbf9d7 | 1629 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1630 | { |
1631 | case 3: | |
0dfbf9d7 | 1632 | x->array[2] = v; |
1a0670f3 | 1633 | /* Fall through. */ |
c6fb90c8 | 1634 | case 2: |
0dfbf9d7 | 1635 | x->array[1] = v; |
1a0670f3 | 1636 | /* Fall through. */ |
c6fb90c8 | 1637 | case 1: |
0dfbf9d7 | 1638 | x->array[0] = v; |
1a0670f3 | 1639 | /* Fall through. */ |
c6fb90c8 L |
1640 | break; |
1641 | default: | |
1642 | abort (); | |
1643 | } | |
bab6aec1 JB |
1644 | |
1645 | x->bitfield.class = ClassNone; | |
75e5731b | 1646 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1647 | } |
40fb9820 | 1648 | |
c6fb90c8 | 1649 | static INLINE int |
0dfbf9d7 L |
1650 | operand_type_equal (const union i386_operand_type *x, |
1651 | const union i386_operand_type *y) | |
c6fb90c8 | 1652 | { |
0dfbf9d7 | 1653 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1654 | { |
1655 | case 3: | |
0dfbf9d7 | 1656 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1657 | return 0; |
1a0670f3 | 1658 | /* Fall through. */ |
c6fb90c8 | 1659 | case 2: |
0dfbf9d7 | 1660 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1661 | return 0; |
1a0670f3 | 1662 | /* Fall through. */ |
c6fb90c8 | 1663 | case 1: |
0dfbf9d7 | 1664 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1665 | break; |
1666 | default: | |
1667 | abort (); | |
1668 | } | |
1669 | } | |
40fb9820 | 1670 | |
734dfd1c | 1671 | static INLINE bool |
a5e91879 | 1672 | _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu) |
734dfd1c JB |
1673 | { |
1674 | switch (cpu) | |
1675 | { | |
a5e91879 JB |
1676 | case Cpu287: return a->bitfield.cpu287; |
1677 | case Cpu387: return a->bitfield.cpu387; | |
1678 | case Cpu3dnow: return a->bitfield.cpu3dnow; | |
1679 | case Cpu3dnowA: return a->bitfield.cpu3dnowa; | |
1680 | case CpuAVX: return a->bitfield.cpuavx; | |
1681 | case CpuHLE: return a->bitfield.cpuhle; | |
1682 | case CpuAVX512F: return a->bitfield.cpuavx512f; | |
1683 | case CpuAVX512VL: return a->bitfield.cpuavx512vl; | |
80d61d8d | 1684 | case CpuAPX_F: return a->bitfield.cpuapx_f; |
a5e91879 JB |
1685 | case Cpu64: return a->bitfield.cpu64; |
1686 | case CpuNo64: return a->bitfield.cpuno64; | |
734dfd1c JB |
1687 | default: |
1688 | gas_assert (cpu < CpuAttrEnums); | |
1689 | } | |
a5e91879 JB |
1690 | return a->bitfield.isa == cpu + 1u; |
1691 | } | |
1692 | ||
1693 | static INLINE bool | |
1694 | is_cpu (const insn_template *t, enum i386_cpu cpu) | |
1695 | { | |
1696 | return _is_cpu(&t->cpu, cpu); | |
1697 | } | |
1698 | ||
1699 | static INLINE bool | |
1700 | maybe_cpu (const insn_template *t, enum i386_cpu cpu) | |
1701 | { | |
1702 | return _is_cpu(&t->cpu_any, cpu); | |
734dfd1c JB |
1703 | } |
1704 | ||
1705 | static i386_cpu_flags cpu_flags_from_attr (i386_cpu_attr a) | |
1706 | { | |
1707 | const unsigned int bps = sizeof (a.array[0]) * CHAR_BIT; | |
1708 | i386_cpu_flags f = { .array[0] = 0 }; | |
1709 | ||
a12915cc | 1710 | switch (ARRAY_SIZE (a.array)) |
734dfd1c JB |
1711 | { |
1712 | case 1: | |
1713 | f.array[CpuAttrEnums / bps] | |
a12915cc JB |
1714 | #ifndef WORDS_BIGENDIAN |
1715 | |= (a.array[0] >> CpuIsaBits) << (CpuAttrEnums % bps); | |
1716 | #else | |
1717 | |= (a.array[0] << CpuIsaBits) >> (CpuAttrEnums % bps); | |
1718 | #endif | |
1719 | if (CpuMax / bps > CpuAttrEnums / bps) | |
734dfd1c | 1720 | f.array[CpuAttrEnums / bps + 1] |
a12915cc | 1721 | #ifndef WORDS_BIGENDIAN |
734dfd1c | 1722 | = (a.array[0] >> CpuIsaBits) >> (bps - CpuAttrEnums % bps); |
a12915cc JB |
1723 | #else |
1724 | = (a.array[0] << CpuIsaBits) << (bps - CpuAttrEnums % bps); | |
1725 | #endif | |
734dfd1c | 1726 | break; |
a12915cc | 1727 | |
734dfd1c JB |
1728 | default: |
1729 | abort (); | |
1730 | } | |
1731 | ||
1732 | if (a.bitfield.isa) | |
a12915cc | 1733 | #ifndef WORDS_BIGENDIAN |
734dfd1c | 1734 | f.array[(a.bitfield.isa - 1) / bps] |= 1u << ((a.bitfield.isa - 1) % bps); |
a12915cc JB |
1735 | #else |
1736 | f.array[(a.bitfield.isa - 1) / bps] |= 1u << (~(a.bitfield.isa - 1) % bps); | |
1737 | #endif | |
734dfd1c JB |
1738 | |
1739 | return f; | |
1740 | } | |
1741 | ||
0dfbf9d7 L |
1742 | static INLINE int |
1743 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1744 | { | |
1745 | switch (ARRAY_SIZE(x->array)) | |
1746 | { | |
75f8266a KL |
1747 | case 5: |
1748 | if (x->array[4]) | |
1749 | return 0; | |
1750 | /* Fall through. */ | |
53467f57 IT |
1751 | case 4: |
1752 | if (x->array[3]) | |
1753 | return 0; | |
1754 | /* Fall through. */ | |
0dfbf9d7 L |
1755 | case 3: |
1756 | if (x->array[2]) | |
1757 | return 0; | |
1a0670f3 | 1758 | /* Fall through. */ |
0dfbf9d7 L |
1759 | case 2: |
1760 | if (x->array[1]) | |
1761 | return 0; | |
1a0670f3 | 1762 | /* Fall through. */ |
0dfbf9d7 L |
1763 | case 1: |
1764 | return !x->array[0]; | |
1765 | default: | |
1766 | abort (); | |
1767 | } | |
1768 | } | |
1769 | ||
0dfbf9d7 L |
1770 | static INLINE int |
1771 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1772 | const union i386_cpu_flags *y) | |
1773 | { | |
1774 | switch (ARRAY_SIZE(x->array)) | |
1775 | { | |
75f8266a KL |
1776 | case 5: |
1777 | if (x->array[4] != y->array[4]) | |
1778 | return 0; | |
1779 | /* Fall through. */ | |
53467f57 IT |
1780 | case 4: |
1781 | if (x->array[3] != y->array[3]) | |
1782 | return 0; | |
1783 | /* Fall through. */ | |
0dfbf9d7 L |
1784 | case 3: |
1785 | if (x->array[2] != y->array[2]) | |
1786 | return 0; | |
1a0670f3 | 1787 | /* Fall through. */ |
0dfbf9d7 L |
1788 | case 2: |
1789 | if (x->array[1] != y->array[1]) | |
1790 | return 0; | |
1a0670f3 | 1791 | /* Fall through. */ |
0dfbf9d7 L |
1792 | case 1: |
1793 | return x->array[0] == y->array[0]; | |
1794 | break; | |
1795 | default: | |
1796 | abort (); | |
1797 | } | |
1798 | } | |
c6fb90c8 L |
1799 | |
1800 | static INLINE int | |
c0260ac6 | 1801 | cpu_flags_check_cpu64 (const insn_template *t) |
c6fb90c8 | 1802 | { |
c0260ac6 JB |
1803 | return flag_code == CODE_64BIT |
1804 | ? !t->cpu.bitfield.cpuno64 | |
1805 | : !t->cpu.bitfield.cpu64; | |
40fb9820 L |
1806 | } |
1807 | ||
c6fb90c8 L |
1808 | static INLINE i386_cpu_flags |
1809 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1810 | { |
c6fb90c8 L |
1811 | switch (ARRAY_SIZE (x.array)) |
1812 | { | |
75f8266a KL |
1813 | case 5: |
1814 | x.array [4] &= y.array [4]; | |
1815 | /* Fall through. */ | |
53467f57 IT |
1816 | case 4: |
1817 | x.array [3] &= y.array [3]; | |
1818 | /* Fall through. */ | |
c6fb90c8 L |
1819 | case 3: |
1820 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1821 | /* Fall through. */ |
c6fb90c8 L |
1822 | case 2: |
1823 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1824 | /* Fall through. */ |
c6fb90c8 L |
1825 | case 1: |
1826 | x.array [0] &= y.array [0]; | |
1827 | break; | |
1828 | default: | |
1829 | abort (); | |
1830 | } | |
1831 | return x; | |
1832 | } | |
40fb9820 | 1833 | |
c6fb90c8 L |
1834 | static INLINE i386_cpu_flags |
1835 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1836 | { |
c6fb90c8 | 1837 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1838 | { |
75f8266a KL |
1839 | case 5: |
1840 | x.array [4] |= y.array [4]; | |
1841 | /* Fall through. */ | |
53467f57 IT |
1842 | case 4: |
1843 | x.array [3] |= y.array [3]; | |
1844 | /* Fall through. */ | |
c6fb90c8 L |
1845 | case 3: |
1846 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1847 | /* Fall through. */ |
c6fb90c8 L |
1848 | case 2: |
1849 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1850 | /* Fall through. */ |
c6fb90c8 L |
1851 | case 1: |
1852 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1853 | break; |
1854 | default: | |
1855 | abort (); | |
1856 | } | |
40fb9820 L |
1857 | return x; |
1858 | } | |
1859 | ||
309d3373 JB |
1860 | static INLINE i386_cpu_flags |
1861 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1862 | { | |
1863 | switch (ARRAY_SIZE (x.array)) | |
1864 | { | |
75f8266a KL |
1865 | case 5: |
1866 | x.array [4] &= ~y.array [4]; | |
1867 | /* Fall through. */ | |
53467f57 IT |
1868 | case 4: |
1869 | x.array [3] &= ~y.array [3]; | |
1870 | /* Fall through. */ | |
309d3373 JB |
1871 | case 3: |
1872 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1873 | /* Fall through. */ |
309d3373 JB |
1874 | case 2: |
1875 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1876 | /* Fall through. */ |
309d3373 JB |
1877 | case 1: |
1878 | x.array [0] &= ~y.array [0]; | |
1879 | break; | |
1880 | default: | |
1881 | abort (); | |
1882 | } | |
1883 | return x; | |
1884 | } | |
1885 | ||
6c0946d0 JB |
1886 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1887 | ||
6177c84d | 1888 | static INLINE bool need_evex_encoding (const insn_template *t) |
a6f3add0 | 1889 | { |
e346d50a JB |
1890 | return i.encoding == encoding_evex |
1891 | || i.encoding == encoding_evex512 | |
eb3f3841 | 1892 | || (t->opcode_modifier.vex && i.encoding == encoding_egpr) |
a6f3add0 JB |
1893 | || i.mask.reg; |
1894 | } | |
1895 | ||
c0f3af97 L |
1896 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1897 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1898 | ||
c0f3af97 | 1899 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1900 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1901 | |
1902 | /* Return CPU flags match bits. */ | |
3629bb00 | 1903 | |
40fb9820 | 1904 | static int |
d3ce72d0 | 1905 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1906 | { |
a5e91879 JB |
1907 | i386_cpu_flags cpu, active, all = cpu_flags_from_attr (t->cpu); |
1908 | i386_cpu_flags any = cpu_flags_from_attr (t->cpu_any); | |
c0260ac6 | 1909 | int match = cpu_flags_check_cpu64 (t) ? CPU_FLAGS_64BIT_MATCH : 0; |
40fb9820 | 1910 | |
a5e91879 JB |
1911 | all.bitfield.cpu64 = 0; |
1912 | all.bitfield.cpuno64 = 0; | |
1913 | gas_assert (!any.bitfield.cpu64); | |
1914 | gas_assert (!any.bitfield.cpuno64); | |
40fb9820 | 1915 | |
a5e91879 | 1916 | if (cpu_flags_all_zero (&all) && cpu_flags_all_zero (&any)) |
c0f3af97 L |
1917 | { |
1918 | /* This instruction is available on all archs. */ | |
a5e91879 | 1919 | return match | CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1920 | } |
3e624fa4 | 1921 | |
a5e91879 | 1922 | /* This instruction is available only on some archs. */ |
3629bb00 | 1923 | |
a5e91879 JB |
1924 | /* Dual VEX/EVEX templates may need stripping of one of the flags. */ |
1925 | if (t->opcode_modifier.vex && t->opcode_modifier.evex) | |
1926 | { | |
1927 | /* Dual AVX/AVX512 templates need to retain AVX512* only if we already | |
1928 | know that EVEX encoding will be needed. */ | |
1929 | if ((any.bitfield.cpuavx || any.bitfield.cpuavx2 || any.bitfield.cpufma) | |
1930 | && (any.bitfield.cpuavx512f || any.bitfield.cpuavx512vl)) | |
a6f3add0 | 1931 | { |
6177c84d | 1932 | if (need_evex_encoding (t)) |
a6f3add0 | 1933 | { |
a5e91879 JB |
1934 | any.bitfield.cpuavx = 0; |
1935 | any.bitfield.cpuavx2 = 0; | |
1936 | any.bitfield.cpufma = 0; | |
1937 | } | |
6177c84d | 1938 | /* need_evex_encoding(t) isn't reliable before operands were |
a5e91879 JB |
1939 | parsed. */ |
1940 | else if (i.operands) | |
1941 | { | |
1942 | any.bitfield.cpuavx512f = 0; | |
1943 | any.bitfield.cpuavx512vl = 0; | |
a6f3add0 JB |
1944 | } |
1945 | } | |
7c3df3c6 JB |
1946 | |
1947 | /* Dual non-APX/APX templates need massaging from what APX_F() in the | |
1948 | opcode table has produced. While the direct transformation of the | |
1949 | incoming cpuid&(cpuid|APX_F) would be to cpuid&(cpuid) / cpuid&(APX_F) | |
1950 | respectively, it's cheaper to move to just cpuid / cpuid&APX_F | |
1951 | instead. */ | |
1952 | if (any.bitfield.cpuapx_f | |
1953 | && (any.bitfield.cpubmi || any.bitfield.cpubmi2 | |
1954 | || any.bitfield.cpuavx512f || any.bitfield.cpuavx512bw | |
1955 | || any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile | |
5190fa38 | 1956 | || any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr)) |
7c3df3c6 JB |
1957 | { |
1958 | /* These checks (verifying that APX_F() was properly used in the | |
1959 | opcode table entry) make sure there's no need for an "else" to | |
1960 | the "if()" below. */ | |
1961 | gas_assert (!cpu_flags_all_zero (&all)); | |
1962 | cpu = cpu_flags_and (all, any); | |
1963 | gas_assert (cpu_flags_equal (&cpu, &all)); | |
1964 | ||
1965 | if (need_evex_encoding (t)) | |
1966 | all = any; | |
1967 | ||
1968 | memset (&any, 0, sizeof (any)); | |
1969 | } | |
a5e91879 | 1970 | } |
a6f3add0 | 1971 | |
a5e91879 JB |
1972 | if (flag_code != CODE_64BIT) |
1973 | active = cpu_flags_and_not (cpu_arch_flags, cpu_64_flags); | |
1974 | else | |
1975 | active = cpu_arch_flags; | |
1976 | cpu = cpu_flags_and (all, active); | |
1977 | if (cpu_flags_equal (&cpu, &all)) | |
1978 | { | |
22c36940 JB |
1979 | /* AVX and AVX2 present at the same time express an operand size |
1980 | dependency - strip AVX2 for the purposes here. The operand size | |
1981 | dependent check occurs in check_vecOperands(). */ | |
a5e91879 JB |
1982 | if (any.bitfield.cpuavx && any.bitfield.cpuavx2) |
1983 | any.bitfield.cpuavx2 = 0; | |
22c36940 | 1984 | |
a5e91879 JB |
1985 | cpu = cpu_flags_and (any, active); |
1986 | if (cpu_flags_all_zero (&any) || !cpu_flags_all_zero (&cpu)) | |
b58829cd | 1987 | match |= CPU_FLAGS_ARCH_MATCH; |
3629bb00 | 1988 | } |
c0f3af97 | 1989 | return match; |
40fb9820 L |
1990 | } |
1991 | ||
c6fb90c8 L |
1992 | static INLINE i386_operand_type |
1993 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1994 | { |
bab6aec1 JB |
1995 | if (x.bitfield.class != y.bitfield.class) |
1996 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1997 | if (x.bitfield.instance != y.bitfield.instance) |
1998 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1999 | |
c6fb90c8 L |
2000 | switch (ARRAY_SIZE (x.array)) |
2001 | { | |
2002 | case 3: | |
2003 | x.array [2] &= y.array [2]; | |
1a0670f3 | 2004 | /* Fall through. */ |
c6fb90c8 L |
2005 | case 2: |
2006 | x.array [1] &= y.array [1]; | |
1a0670f3 | 2007 | /* Fall through. */ |
c6fb90c8 L |
2008 | case 1: |
2009 | x.array [0] &= y.array [0]; | |
2010 | break; | |
2011 | default: | |
2012 | abort (); | |
2013 | } | |
2014 | return x; | |
40fb9820 L |
2015 | } |
2016 | ||
73053c1f JB |
2017 | static INLINE i386_operand_type |
2018 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
2019 | { | |
bab6aec1 | 2020 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2021 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2022 | |
73053c1f JB |
2023 | switch (ARRAY_SIZE (x.array)) |
2024 | { | |
2025 | case 3: | |
2026 | x.array [2] &= ~y.array [2]; | |
2027 | /* Fall through. */ | |
2028 | case 2: | |
2029 | x.array [1] &= ~y.array [1]; | |
2030 | /* Fall through. */ | |
2031 | case 1: | |
2032 | x.array [0] &= ~y.array [0]; | |
2033 | break; | |
2034 | default: | |
2035 | abort (); | |
2036 | } | |
2037 | return x; | |
2038 | } | |
2039 | ||
c6fb90c8 L |
2040 | static INLINE i386_operand_type |
2041 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 2042 | { |
bab6aec1 JB |
2043 | gas_assert (x.bitfield.class == ClassNone || |
2044 | y.bitfield.class == ClassNone || | |
2045 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
2046 | gas_assert (x.bitfield.instance == InstanceNone || |
2047 | y.bitfield.instance == InstanceNone || | |
2048 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 2049 | |
c6fb90c8 | 2050 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 2051 | { |
c6fb90c8 L |
2052 | case 3: |
2053 | x.array [2] |= y.array [2]; | |
1a0670f3 | 2054 | /* Fall through. */ |
c6fb90c8 L |
2055 | case 2: |
2056 | x.array [1] |= y.array [1]; | |
1a0670f3 | 2057 | /* Fall through. */ |
c6fb90c8 L |
2058 | case 1: |
2059 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2060 | break; |
2061 | default: | |
2062 | abort (); | |
2063 | } | |
c6fb90c8 L |
2064 | return x; |
2065 | } | |
40fb9820 | 2066 | |
c6fb90c8 L |
2067 | static INLINE i386_operand_type |
2068 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2069 | { | |
bab6aec1 | 2070 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2071 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2072 | |
c6fb90c8 L |
2073 | switch (ARRAY_SIZE (x.array)) |
2074 | { | |
2075 | case 3: | |
2076 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2077 | /* Fall through. */ |
c6fb90c8 L |
2078 | case 2: |
2079 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2080 | /* Fall through. */ |
c6fb90c8 L |
2081 | case 1: |
2082 | x.array [0] ^= y.array [0]; | |
2083 | break; | |
2084 | default: | |
2085 | abort (); | |
2086 | } | |
40fb9820 L |
2087 | return x; |
2088 | } | |
2089 | ||
05909f23 JB |
2090 | static const i386_operand_type anydisp = { |
2091 | .bitfield = { .disp8 = 1, .disp16 = 1, .disp32 = 1, .disp64 = 1 } | |
2092 | }; | |
40fb9820 L |
2093 | |
2094 | enum operand_type | |
2095 | { | |
2096 | reg, | |
40fb9820 L |
2097 | imm, |
2098 | disp, | |
2099 | anymem | |
2100 | }; | |
2101 | ||
c6fb90c8 | 2102 | static INLINE int |
40fb9820 L |
2103 | operand_type_check (i386_operand_type t, enum operand_type c) |
2104 | { | |
2105 | switch (c) | |
2106 | { | |
2107 | case reg: | |
bab6aec1 | 2108 | return t.bitfield.class == Reg; |
40fb9820 | 2109 | |
40fb9820 L |
2110 | case imm: |
2111 | return (t.bitfield.imm8 | |
2112 | || t.bitfield.imm8s | |
2113 | || t.bitfield.imm16 | |
2114 | || t.bitfield.imm32 | |
2115 | || t.bitfield.imm32s | |
2116 | || t.bitfield.imm64); | |
2117 | ||
2118 | case disp: | |
2119 | return (t.bitfield.disp8 | |
2120 | || t.bitfield.disp16 | |
2121 | || t.bitfield.disp32 | |
40fb9820 L |
2122 | || t.bitfield.disp64); |
2123 | ||
2124 | case anymem: | |
2125 | return (t.bitfield.disp8 | |
2126 | || t.bitfield.disp16 | |
2127 | || t.bitfield.disp32 | |
40fb9820 L |
2128 | || t.bitfield.disp64 |
2129 | || t.bitfield.baseindex); | |
2130 | ||
2131 | default: | |
2132 | abort (); | |
2133 | } | |
2cfe26b6 AM |
2134 | |
2135 | return 0; | |
40fb9820 L |
2136 | } |
2137 | ||
7a54636a L |
2138 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2139 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2140 | |
2141 | static INLINE int | |
7a54636a L |
2142 | match_operand_size (const insn_template *t, unsigned int wanted, |
2143 | unsigned int given) | |
5c07affc | 2144 | { |
3ac21baa JB |
2145 | return !((i.types[given].bitfield.byte |
2146 | && !t->operand_types[wanted].bitfield.byte) | |
2147 | || (i.types[given].bitfield.word | |
2148 | && !t->operand_types[wanted].bitfield.word) | |
2149 | || (i.types[given].bitfield.dword | |
2150 | && !t->operand_types[wanted].bitfield.dword) | |
2151 | || (i.types[given].bitfield.qword | |
9db83a32 JB |
2152 | && (!t->operand_types[wanted].bitfield.qword |
2153 | /* Don't allow 64-bit (memory) operands outside of 64-bit | |
2154 | mode, when they're used where a 64-bit GPR could also | |
2155 | be used. Checking is needed for Intel Syntax only. */ | |
2156 | || (intel_syntax | |
2157 | && flag_code != CODE_64BIT | |
2158 | && (t->operand_types[wanted].bitfield.class == Reg | |
2159 | || t->operand_types[wanted].bitfield.class == Accum | |
2160 | || t->opcode_modifier.isstring)))) | |
3ac21baa JB |
2161 | || (i.types[given].bitfield.tbyte |
2162 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2163 | } |
2164 | ||
dd40ce22 L |
2165 | /* Return 1 if there is no conflict in SIMD register between operand |
2166 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2167 | |
2168 | static INLINE int | |
dd40ce22 L |
2169 | match_simd_size (const insn_template *t, unsigned int wanted, |
2170 | unsigned int given) | |
1b54b8d7 | 2171 | { |
3ac21baa JB |
2172 | return !((i.types[given].bitfield.xmmword |
2173 | && !t->operand_types[wanted].bitfield.xmmword) | |
2174 | || (i.types[given].bitfield.ymmword | |
2175 | && !t->operand_types[wanted].bitfield.ymmword) | |
2176 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2177 | && !t->operand_types[wanted].bitfield.zmmword) |
2178 | || (i.types[given].bitfield.tmmword | |
2179 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2180 | } |
2181 | ||
7a54636a L |
2182 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2183 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2184 | |
2185 | static INLINE int | |
dd40ce22 L |
2186 | match_mem_size (const insn_template *t, unsigned int wanted, |
2187 | unsigned int given) | |
5c07affc | 2188 | { |
7a54636a | 2189 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2190 | && !((i.types[given].bitfield.unspecified |
5273a3cd | 2191 | && !i.broadcast.type |
a5748e0d | 2192 | && !i.broadcast.bytes |
3ac21baa JB |
2193 | && !t->operand_types[wanted].bitfield.unspecified) |
2194 | || (i.types[given].bitfield.fword | |
2195 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2196 | /* For scalar opcode templates to allow register and memory |
2197 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2198 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2199 | down-conversion vpmov*. */ | |
3528c362 | 2200 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2201 | && t->operand_types[wanted].bitfield.byte |
2202 | + t->operand_types[wanted].bitfield.word | |
2203 | + t->operand_types[wanted].bitfield.dword | |
2204 | + t->operand_types[wanted].bitfield.qword | |
2205 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2206 | ? (i.types[given].bitfield.xmmword |
2207 | || i.types[given].bitfield.ymmword | |
2208 | || i.types[given].bitfield.zmmword) | |
2209 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2210 | } |
2211 | ||
3ac21baa JB |
2212 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2213 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2214 | is no size conflict on any operands for the template with operands reversed | |
2215 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2216 | |
3ac21baa JB |
2217 | #define MATCH_STRAIGHT 1 |
2218 | #define MATCH_REVERSE 2 | |
2219 | ||
2220 | static INLINE unsigned int | |
d3ce72d0 | 2221 | operand_size_match (const insn_template *t) |
5c07affc | 2222 | { |
3ac21baa | 2223 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2224 | |
0cfa3eb3 | 2225 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2226 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2227 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2228 | return match; |
2229 | ||
2230 | /* Check memory and accumulator operand size. */ | |
2231 | for (j = 0; j < i.operands; j++) | |
2232 | { | |
3528c362 JB |
2233 | if (i.types[j].bitfield.class != Reg |
2234 | && i.types[j].bitfield.class != RegSIMD | |
255571cd | 2235 | && t->opcode_modifier.operandconstraint == ANY_SIZE) |
5c07affc L |
2236 | continue; |
2237 | ||
bab6aec1 | 2238 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2239 | && !match_operand_size (t, j, j)) |
5c07affc L |
2240 | { |
2241 | match = 0; | |
2242 | break; | |
2243 | } | |
2244 | ||
3528c362 | 2245 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2246 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2247 | { |
2248 | match = 0; | |
2249 | break; | |
2250 | } | |
2251 | ||
75e5731b | 2252 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2253 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2254 | { |
2255 | match = 0; | |
2256 | break; | |
2257 | } | |
2258 | ||
c48dadc9 | 2259 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2260 | { |
2261 | match = 0; | |
2262 | break; | |
2263 | } | |
2264 | } | |
2265 | ||
3ac21baa | 2266 | if (!t->opcode_modifier.d) |
7b94647a | 2267 | return match; |
5c07affc L |
2268 | |
2269 | /* Check reverse. */ | |
aa180741 | 2270 | gas_assert (i.operands >= 2); |
5c07affc | 2271 | |
f5eb1d70 | 2272 | for (j = 0; j < i.operands; j++) |
5c07affc | 2273 | { |
f5eb1d70 JB |
2274 | unsigned int given = i.operands - j - 1; |
2275 | ||
aa180741 | 2276 | /* For FMA4 and XOP insns VEX.W controls just the first two |
3083f376 | 2277 | register operands. And APX_F insns just swap the two source operands, |
2278 | with the 3rd one being the destination. */ | |
2279 | if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP) | |
2280 | || is_cpu (t, CpuAPX_F)) | |
8bd915b7 JB |
2281 | given = j < 2 ? 1 - j : j; |
2282 | ||
bab6aec1 | 2283 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2284 | && !match_operand_size (t, j, given)) |
7b94647a | 2285 | return match; |
5c07affc | 2286 | |
3528c362 | 2287 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2288 | && !match_simd_size (t, j, given)) |
7b94647a | 2289 | return match; |
dbbc8b7e | 2290 | |
75e5731b | 2291 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2292 | && (!match_operand_size (t, j, given) |
2293 | || !match_simd_size (t, j, given))) | |
7b94647a | 2294 | return match; |
dbbc8b7e | 2295 | |
f5eb1d70 | 2296 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
7b94647a | 2297 | return match; |
5c07affc L |
2298 | } |
2299 | ||
3ac21baa | 2300 | return match | MATCH_REVERSE; |
5c07affc L |
2301 | } |
2302 | ||
c6fb90c8 | 2303 | static INLINE int |
40fb9820 L |
2304 | operand_type_match (i386_operand_type overlap, |
2305 | i386_operand_type given) | |
2306 | { | |
2307 | i386_operand_type temp = overlap; | |
2308 | ||
7d5e4556 | 2309 | temp.bitfield.unspecified = 0; |
5c07affc L |
2310 | temp.bitfield.byte = 0; |
2311 | temp.bitfield.word = 0; | |
2312 | temp.bitfield.dword = 0; | |
2313 | temp.bitfield.fword = 0; | |
2314 | temp.bitfield.qword = 0; | |
2315 | temp.bitfield.tbyte = 0; | |
2316 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2317 | temp.bitfield.ymmword = 0; |
43234a1e | 2318 | temp.bitfield.zmmword = 0; |
260cd341 | 2319 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2320 | if (operand_type_all_zero (&temp)) |
891edac4 | 2321 | goto mismatch; |
40fb9820 | 2322 | |
6f2f06be | 2323 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2324 | return 1; |
2325 | ||
dc1e8a47 | 2326 | mismatch: |
a65babc9 | 2327 | i.error = operand_type_mismatch; |
891edac4 | 2328 | return 0; |
40fb9820 L |
2329 | } |
2330 | ||
7d5e4556 | 2331 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2332 | unless the expected operand type register overlap is null. |
8ee52bcf | 2333 | Intel syntax sized memory operands are also checked here. */ |
40fb9820 | 2334 | |
c6fb90c8 | 2335 | static INLINE int |
dc821c5f | 2336 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2337 | i386_operand_type t0, |
40fb9820 L |
2338 | i386_operand_type g1, |
2339 | i386_operand_type t1) | |
2340 | { | |
bab6aec1 | 2341 | if (g0.bitfield.class != Reg |
3528c362 | 2342 | && g0.bitfield.class != RegSIMD |
8ee52bcf JB |
2343 | && (g0.bitfield.unspecified |
2344 | || !operand_type_check (g0, anymem))) | |
40fb9820 L |
2345 | return 1; |
2346 | ||
bab6aec1 | 2347 | if (g1.bitfield.class != Reg |
3528c362 | 2348 | && g1.bitfield.class != RegSIMD |
8ee52bcf JB |
2349 | && (g1.bitfield.unspecified |
2350 | || !operand_type_check (g1, anymem))) | |
40fb9820 L |
2351 | return 1; |
2352 | ||
dc821c5f JB |
2353 | if (g0.bitfield.byte == g1.bitfield.byte |
2354 | && g0.bitfield.word == g1.bitfield.word | |
2355 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2356 | && g0.bitfield.qword == g1.bitfield.qword |
2357 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2358 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2359 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2360 | return 1; |
2361 | ||
c4d09633 JB |
2362 | /* If expectations overlap in no more than a single size, all is fine. */ |
2363 | g0 = operand_type_and (t0, t1); | |
2364 | if (g0.bitfield.byte | |
2365 | + g0.bitfield.word | |
2366 | + g0.bitfield.dword | |
2367 | + g0.bitfield.qword | |
2368 | + g0.bitfield.xmmword | |
2369 | + g0.bitfield.ymmword | |
2370 | + g0.bitfield.zmmword <= 1) | |
891edac4 L |
2371 | return 1; |
2372 | ||
a65babc9 | 2373 | i.error = register_type_mismatch; |
891edac4 L |
2374 | |
2375 | return 0; | |
40fb9820 L |
2376 | } |
2377 | ||
4c692bc7 JB |
2378 | static INLINE unsigned int |
2379 | register_number (const reg_entry *r) | |
2380 | { | |
2381 | unsigned int nr = r->reg_num; | |
2382 | ||
2383 | if (r->reg_flags & RegRex) | |
2384 | nr += 8; | |
2385 | ||
80d61d8d | 2386 | if (r->reg_flags & (RegVRex | RegRex2)) |
200cbe0f L |
2387 | nr += 16; |
2388 | ||
4c692bc7 JB |
2389 | return nr; |
2390 | } | |
2391 | ||
252b5132 | 2392 | static INLINE unsigned int |
40fb9820 | 2393 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2394 | { |
b5014f7a | 2395 | if (t.bitfield.disp8) |
40fb9820 L |
2396 | return 1; |
2397 | else if (t.bitfield.disp16 | |
a775efc8 | 2398 | || t.bitfield.disp32) |
40fb9820 L |
2399 | return 2; |
2400 | else | |
2401 | return 0; | |
252b5132 RH |
2402 | } |
2403 | ||
2404 | static INLINE int | |
65879393 | 2405 | fits_in_signed_byte (addressT num) |
252b5132 | 2406 | { |
65879393 | 2407 | return num + 0x80 <= 0xff; |
47926f60 | 2408 | } |
252b5132 RH |
2409 | |
2410 | static INLINE int | |
65879393 | 2411 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2412 | { |
65879393 | 2413 | return num <= 0xff; |
47926f60 | 2414 | } |
252b5132 RH |
2415 | |
2416 | static INLINE int | |
65879393 | 2417 | fits_in_unsigned_word (addressT num) |
252b5132 | 2418 | { |
65879393 | 2419 | return num <= 0xffff; |
47926f60 | 2420 | } |
252b5132 RH |
2421 | |
2422 | static INLINE int | |
65879393 | 2423 | fits_in_signed_word (addressT num) |
252b5132 | 2424 | { |
65879393 | 2425 | return num + 0x8000 <= 0xffff; |
47926f60 | 2426 | } |
2a962e6d | 2427 | |
3e73aa7c | 2428 | static INLINE int |
65879393 | 2429 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2430 | { |
2431 | #ifndef BFD64 | |
2432 | return 1; | |
2433 | #else | |
65879393 | 2434 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2435 | #endif |
2436 | } /* fits_in_signed_long() */ | |
2a962e6d | 2437 | |
3e73aa7c | 2438 | static INLINE int |
65879393 | 2439 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2440 | { |
2441 | #ifndef BFD64 | |
2442 | return 1; | |
2443 | #else | |
65879393 | 2444 | return num <= 0xffffffff; |
3e73aa7c JH |
2445 | #endif |
2446 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2447 | |
a442cac5 JB |
2448 | static INLINE valueT extend_to_32bit_address (addressT num) |
2449 | { | |
2450 | #ifdef BFD64 | |
2451 | if (fits_in_unsigned_long(num)) | |
2452 | return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
2453 | ||
2454 | if (!fits_in_signed_long (num)) | |
2455 | return num & 0xffffffff; | |
2456 | #endif | |
2457 | ||
2458 | return num; | |
2459 | } | |
2460 | ||
43234a1e | 2461 | static INLINE int |
b5014f7a | 2462 | fits_in_disp8 (offsetT num) |
43234a1e L |
2463 | { |
2464 | int shift = i.memshift; | |
2465 | unsigned int mask; | |
2466 | ||
2467 | if (shift == -1) | |
2468 | abort (); | |
2469 | ||
2470 | mask = (1 << shift) - 1; | |
2471 | ||
2472 | /* Return 0 if NUM isn't properly aligned. */ | |
2473 | if ((num & mask)) | |
2474 | return 0; | |
2475 | ||
2476 | /* Check if NUM will fit in 8bit after shift. */ | |
2477 | return fits_in_signed_byte (num >> shift); | |
2478 | } | |
2479 | ||
a683cc34 SP |
2480 | static INLINE int |
2481 | fits_in_imm4 (offsetT num) | |
2482 | { | |
0ff3b7d0 | 2483 | /* Despite the name, check for imm3 if we're dealing with EVEX. */ |
eb3f3841 JB |
2484 | return (num & (i.encoding != encoding_evex |
2485 | && i.encoding != encoding_egpr ? 0xf : 7)) == num; | |
a683cc34 SP |
2486 | } |
2487 | ||
40fb9820 | 2488 | static i386_operand_type |
e3bb37b5 | 2489 | smallest_imm_type (offsetT num) |
252b5132 | 2490 | { |
40fb9820 | 2491 | i386_operand_type t; |
7ab9ffdd | 2492 | |
0dfbf9d7 | 2493 | operand_type_set (&t, 0); |
40fb9820 L |
2494 | t.bitfield.imm64 = 1; |
2495 | ||
2496 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2497 | { |
2498 | /* This code is disabled on the 486 because all the Imm1 forms | |
2499 | in the opcode table are slower on the i486. They're the | |
2500 | versions with the implicitly specified single-position | |
2501 | displacement, which has another syntax if you really want to | |
2502 | use that form. */ | |
40fb9820 L |
2503 | t.bitfield.imm1 = 1; |
2504 | t.bitfield.imm8 = 1; | |
2505 | t.bitfield.imm8s = 1; | |
2506 | t.bitfield.imm16 = 1; | |
2507 | t.bitfield.imm32 = 1; | |
2508 | t.bitfield.imm32s = 1; | |
2509 | } | |
2510 | else if (fits_in_signed_byte (num)) | |
2511 | { | |
c34d1cc9 JB |
2512 | if (fits_in_unsigned_byte (num)) |
2513 | t.bitfield.imm8 = 1; | |
40fb9820 L |
2514 | t.bitfield.imm8s = 1; |
2515 | t.bitfield.imm16 = 1; | |
8170af78 HL |
2516 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2517 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2518 | t.bitfield.imm32s = 1; |
2519 | } | |
2520 | else if (fits_in_unsigned_byte (num)) | |
2521 | { | |
2522 | t.bitfield.imm8 = 1; | |
2523 | t.bitfield.imm16 = 1; | |
2524 | t.bitfield.imm32 = 1; | |
2525 | t.bitfield.imm32s = 1; | |
2526 | } | |
2527 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2528 | { | |
2529 | t.bitfield.imm16 = 1; | |
8170af78 HL |
2530 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2531 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2532 | t.bitfield.imm32s = 1; |
2533 | } | |
2534 | else if (fits_in_signed_long (num)) | |
2535 | { | |
8170af78 HL |
2536 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2537 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2538 | t.bitfield.imm32s = 1; |
2539 | } | |
2540 | else if (fits_in_unsigned_long (num)) | |
2541 | t.bitfield.imm32 = 1; | |
2542 | ||
2543 | return t; | |
47926f60 | 2544 | } |
252b5132 | 2545 | |
847f7ad4 | 2546 | static offsetT |
e3bb37b5 | 2547 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2548 | { |
508866be | 2549 | addressT mask; |
ba2adb93 | 2550 | |
847f7ad4 AM |
2551 | switch (size) |
2552 | { | |
508866be L |
2553 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2554 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3e73aa7c | 2555 | #ifdef BFD64 |
64965897 | 2556 | case 4: mask = ((addressT) 1 << 32) - 1; break; |
3e73aa7c | 2557 | #endif |
64965897 | 2558 | case sizeof (val): return val; |
47926f60 | 2559 | default: abort (); |
847f7ad4 AM |
2560 | } |
2561 | ||
4fe51f7d | 2562 | if ((val & ~mask) != 0 && (-val & ~mask) != 0) |
f493c217 AM |
2563 | as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64), |
2564 | (uint64_t) val, (uint64_t) (val & mask)); | |
847f7ad4 | 2565 | |
847f7ad4 AM |
2566 | return val & mask; |
2567 | } | |
2568 | ||
76d3f746 JB |
2569 | static INLINE const char *insn_name (const insn_template *t) |
2570 | { | |
5c139202 | 2571 | return &i386_mnemonics[t->mnem_off]; |
76d3f746 JB |
2572 | } |
2573 | ||
c32fa91d L |
2574 | enum PREFIX_GROUP |
2575 | { | |
2576 | PREFIX_EXIST = 0, | |
2577 | PREFIX_LOCK, | |
2578 | PREFIX_REP, | |
04ef582a | 2579 | PREFIX_DS, |
c32fa91d L |
2580 | PREFIX_OTHER |
2581 | }; | |
2582 | ||
2583 | /* Returns | |
2584 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2585 | same class already exists. | |
2586 | b. PREFIX_LOCK if lock prefix is added. | |
2587 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2588 | d. PREFIX_DS if ds prefix is added. |
2589 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2590 | */ |
2591 | ||
2592 | static enum PREFIX_GROUP | |
e3bb37b5 | 2593 | add_prefix (unsigned int prefix) |
252b5132 | 2594 | { |
c32fa91d | 2595 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2596 | unsigned int q; |
252b5132 | 2597 | |
29b0f896 AM |
2598 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2599 | && flag_code == CODE_64BIT) | |
b1905489 | 2600 | { |
161a04f6 | 2601 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2602 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2603 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2604 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2605 | ret = PREFIX_EXIST; |
b1905489 JB |
2606 | q = REX_PREFIX; |
2607 | } | |
3e73aa7c | 2608 | else |
b1905489 JB |
2609 | { |
2610 | switch (prefix) | |
2611 | { | |
2612 | default: | |
2613 | abort (); | |
2614 | ||
b1905489 | 2615 | case DS_PREFIX_OPCODE: |
04ef582a L |
2616 | ret = PREFIX_DS; |
2617 | /* Fall through. */ | |
2618 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2619 | case ES_PREFIX_OPCODE: |
2620 | case FS_PREFIX_OPCODE: | |
2621 | case GS_PREFIX_OPCODE: | |
2622 | case SS_PREFIX_OPCODE: | |
2623 | q = SEG_PREFIX; | |
2624 | break; | |
2625 | ||
2626 | case REPNE_PREFIX_OPCODE: | |
2627 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2628 | q = REP_PREFIX; |
2629 | ret = PREFIX_REP; | |
2630 | break; | |
2631 | ||
b1905489 | 2632 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2633 | q = LOCK_PREFIX; |
2634 | ret = PREFIX_LOCK; | |
b1905489 JB |
2635 | break; |
2636 | ||
2637 | case FWAIT_OPCODE: | |
2638 | q = WAIT_PREFIX; | |
2639 | break; | |
2640 | ||
2641 | case ADDR_PREFIX_OPCODE: | |
2642 | q = ADDR_PREFIX; | |
2643 | break; | |
2644 | ||
2645 | case DATA_PREFIX_OPCODE: | |
2646 | q = DATA_PREFIX; | |
2647 | break; | |
2648 | } | |
2649 | if (i.prefix[q] != 0) | |
c32fa91d | 2650 | ret = PREFIX_EXIST; |
b1905489 | 2651 | } |
252b5132 | 2652 | |
b1905489 | 2653 | if (ret) |
252b5132 | 2654 | { |
b1905489 JB |
2655 | if (!i.prefix[q]) |
2656 | ++i.prefixes; | |
2657 | i.prefix[q] |= prefix; | |
252b5132 | 2658 | } |
b1905489 JB |
2659 | else |
2660 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2661 | |
252b5132 RH |
2662 | return ret; |
2663 | } | |
2664 | ||
2665 | static void | |
78f12dd3 | 2666 | update_code_flag (int value, int check) |
eecb386c | 2667 | { |
b44fef84 JB |
2668 | PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad; |
2669 | ||
da5f9eb4 | 2670 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpu64 ) |
b44fef84 JB |
2671 | { |
2672 | as_error (_("64bit mode not supported on `%s'."), | |
2673 | cpu_arch_name ? cpu_arch_name : default_arch); | |
2674 | return; | |
2675 | } | |
2676 | ||
2677 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) | |
2678 | { | |
2679 | as_error (_("32bit mode not supported on `%s'."), | |
2680 | cpu_arch_name ? cpu_arch_name : default_arch); | |
2681 | return; | |
2682 | } | |
78f12dd3 | 2683 | |
1e9cc1c2 | 2684 | flag_code = (enum flag_code) value; |
b44fef84 | 2685 | |
eecb386c AM |
2686 | stackop_size = '\0'; |
2687 | } | |
2688 | ||
78f12dd3 L |
2689 | static void |
2690 | set_code_flag (int value) | |
2691 | { | |
2692 | update_code_flag (value, 0); | |
2693 | } | |
2694 | ||
eecb386c | 2695 | static void |
e3bb37b5 | 2696 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2697 | { |
1e9cc1c2 | 2698 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2699 | if (flag_code != CODE_16BIT) |
2700 | abort (); | |
9306ca4a | 2701 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2702 | } |
2703 | ||
213f15cf JB |
2704 | static void |
2705 | _set_intel_syntax (int syntax_flag) | |
2706 | { | |
2707 | intel_syntax = syntax_flag; | |
2708 | ||
2709 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); | |
2710 | ||
2711 | register_prefix = allow_naked_reg ? "" : "%"; | |
2712 | } | |
2713 | ||
252b5132 | 2714 | static void |
e3bb37b5 | 2715 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2716 | { |
2717 | /* Find out if register prefixing is specified. */ | |
2718 | int ask_naked_reg = 0; | |
2719 | ||
2720 | SKIP_WHITESPACE (); | |
29b0f896 | 2721 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2722 | { |
d02603dc NC |
2723 | char *string; |
2724 | int e = get_symbol_name (&string); | |
252b5132 | 2725 | |
47926f60 | 2726 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2727 | ask_naked_reg = 1; |
47926f60 | 2728 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2729 | ask_naked_reg = -1; |
2730 | else | |
d0b47220 | 2731 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2732 | (void) restore_line_pointer (e); |
252b5132 RH |
2733 | } |
2734 | demand_empty_rest_of_line (); | |
c3332e24 | 2735 | |
252b5132 | 2736 | if (ask_naked_reg == 0) |
213f15cf | 2737 | allow_naked_reg = (syntax_flag |
f86103b7 | 2738 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 RH |
2739 | else |
2740 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2741 | |
213f15cf | 2742 | _set_intel_syntax (syntax_flag); |
252b5132 RH |
2743 | } |
2744 | ||
1efbbeb4 L |
2745 | static void |
2746 | set_intel_mnemonic (int mnemonic_flag) | |
2747 | { | |
e1d4d893 | 2748 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2749 | } |
2750 | ||
db51cc60 L |
2751 | static void |
2752 | set_allow_index_reg (int flag) | |
2753 | { | |
2754 | allow_index_reg = flag; | |
2755 | } | |
2756 | ||
cb19c032 | 2757 | static void |
7bab8ab5 | 2758 | set_check (int what) |
cb19c032 | 2759 | { |
7bab8ab5 JB |
2760 | enum check_kind *kind; |
2761 | const char *str; | |
2762 | ||
2763 | if (what) | |
2764 | { | |
2765 | kind = &operand_check; | |
2766 | str = "operand"; | |
2767 | } | |
2768 | else | |
2769 | { | |
2770 | kind = &sse_check; | |
2771 | str = "sse"; | |
2772 | } | |
2773 | ||
cb19c032 L |
2774 | SKIP_WHITESPACE (); |
2775 | ||
2776 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2777 | { | |
d02603dc NC |
2778 | char *string; |
2779 | int e = get_symbol_name (&string); | |
cb19c032 L |
2780 | |
2781 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2782 | *kind = check_none; |
cb19c032 | 2783 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2784 | *kind = check_warning; |
cb19c032 | 2785 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2786 | *kind = check_error; |
cb19c032 | 2787 | else |
7bab8ab5 | 2788 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2789 | (void) restore_line_pointer (e); |
cb19c032 L |
2790 | } |
2791 | else | |
7bab8ab5 | 2792 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2793 | |
2794 | demand_empty_rest_of_line (); | |
2795 | } | |
2796 | ||
8a9036a4 L |
2797 | static void |
2798 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2799 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2800 | { |
2801 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2802 | static const char *arch; | |
2803 | ||
c085ab00 | 2804 | /* Intel MCU is only supported on ELF. */ |
8a9036a4 L |
2805 | if (!IS_ELF) |
2806 | return; | |
2807 | ||
2808 | if (!arch) | |
2809 | { | |
2810 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2811 | use default_arch. */ | |
2812 | arch = cpu_arch_name; | |
2813 | if (!arch) | |
2814 | arch = default_arch; | |
2815 | } | |
2816 | ||
81486035 | 2817 | /* If we are targeting Intel MCU, we must enable it. */ |
648d04db JB |
2818 | if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU) |
2819 | == new_flag.bitfield.cpuiamcu) | |
81486035 L |
2820 | return; |
2821 | ||
8a9036a4 L |
2822 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2823 | #endif | |
2824 | } | |
2825 | ||
8180707f | 2826 | static void |
bd483d21 | 2827 | extend_cpu_sub_arch_name (const char *pfx, const char *name) |
8180707f JB |
2828 | { |
2829 | if (cpu_sub_arch_name) | |
2830 | cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name, | |
bd483d21 | 2831 | pfx, name, (const char *) NULL); |
8180707f | 2832 | else |
bd483d21 JB |
2833 | cpu_sub_arch_name = concat (pfx, name, (const char *) NULL); |
2834 | } | |
2835 | ||
2836 | static void isa_enable (unsigned int idx) | |
2837 | { | |
2838 | i386_cpu_flags flags = cpu_flags_or (cpu_arch_flags, cpu_arch[idx].enable); | |
2839 | ||
2840 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2841 | { | |
2842 | extend_cpu_sub_arch_name (".", cpu_arch[idx].name); | |
2843 | cpu_arch_flags = flags; | |
2844 | } | |
2845 | ||
2846 | cpu_arch_isa_flags = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[idx].enable); | |
2847 | } | |
2848 | ||
2849 | static void isa_disable (unsigned int idx) | |
2850 | { | |
2851 | i386_cpu_flags flags | |
2852 | = cpu_flags_and_not (cpu_arch_flags, cpu_arch[idx].disable); | |
2853 | ||
2854 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2855 | { | |
2856 | extend_cpu_sub_arch_name (".no", cpu_arch[idx].name); | |
2857 | cpu_arch_flags = flags; | |
2858 | } | |
2859 | ||
2860 | cpu_arch_isa_flags | |
2861 | = cpu_flags_and_not (cpu_arch_isa_flags, cpu_arch[idx].disable); | |
8180707f JB |
2862 | } |
2863 | ||
e413e4e9 | 2864 | static void |
e3bb37b5 | 2865 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2866 | { |
f68697e8 JB |
2867 | typedef struct arch_stack_entry |
2868 | { | |
2869 | const struct arch_stack_entry *prev; | |
2870 | const char *name; | |
2871 | char *sub_name; | |
2872 | i386_cpu_flags flags; | |
2873 | i386_cpu_flags isa_flags; | |
2874 | enum processor_type isa; | |
2875 | enum flag_code flag_code; | |
4fc85f37 | 2876 | unsigned int vector_size; |
f68697e8 JB |
2877 | char stackop_size; |
2878 | bool no_cond_jump_promotion; | |
2879 | } arch_stack_entry; | |
2880 | static const arch_stack_entry *arch_stack_top; | |
dfab07b9 JB |
2881 | char *s; |
2882 | int e; | |
2883 | const char *string; | |
2884 | unsigned int j = 0; | |
f68697e8 | 2885 | |
47926f60 | 2886 | SKIP_WHITESPACE (); |
e413e4e9 | 2887 | |
dfab07b9 JB |
2888 | if (is_end_of_line[(unsigned char) *input_line_pointer]) |
2889 | { | |
2890 | as_bad (_("missing cpu architecture")); | |
2891 | input_line_pointer++; | |
2892 | return; | |
2893 | } | |
2894 | ||
2895 | e = get_symbol_name (&s); | |
2896 | string = s; | |
2897 | ||
2898 | if (strcmp (string, "push") == 0) | |
e413e4e9 | 2899 | { |
dfab07b9 | 2900 | arch_stack_entry *top = XNEW (arch_stack_entry); |
e413e4e9 | 2901 | |
dfab07b9 JB |
2902 | top->name = cpu_arch_name; |
2903 | if (cpu_sub_arch_name) | |
2904 | top->sub_name = xstrdup (cpu_sub_arch_name); | |
2905 | else | |
2906 | top->sub_name = NULL; | |
2907 | top->flags = cpu_arch_flags; | |
2908 | top->isa = cpu_arch_isa; | |
2909 | top->isa_flags = cpu_arch_isa_flags; | |
2910 | top->flag_code = flag_code; | |
4fc85f37 | 2911 | top->vector_size = vector_size; |
dfab07b9 JB |
2912 | top->stackop_size = stackop_size; |
2913 | top->no_cond_jump_promotion = no_cond_jump_promotion; | |
2914 | ||
2915 | top->prev = arch_stack_top; | |
2916 | arch_stack_top = top; | |
2917 | ||
2918 | (void) restore_line_pointer (e); | |
2919 | demand_empty_rest_of_line (); | |
2920 | return; | |
2921 | } | |
2922 | ||
2923 | if (strcmp (string, "pop") == 0) | |
2924 | { | |
2925 | const arch_stack_entry *top = arch_stack_top; | |
2926 | ||
2927 | if (!top) | |
2928 | as_bad (_(".arch stack is empty")); | |
2929 | else if (top->flag_code != flag_code | |
2930 | || top->stackop_size != stackop_size) | |
2931 | { | |
2932 | static const unsigned int bits[] = { | |
2933 | [CODE_16BIT] = 16, | |
2934 | [CODE_32BIT] = 32, | |
2935 | [CODE_64BIT] = 64, | |
2936 | }; | |
2937 | ||
2938 | as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"), | |
2939 | bits[top->flag_code], | |
2940 | top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : ""); | |
2941 | } | |
2942 | else | |
3ce2ebcf | 2943 | { |
dfab07b9 JB |
2944 | arch_stack_top = top->prev; |
2945 | ||
2946 | cpu_arch_name = top->name; | |
2947 | free (cpu_sub_arch_name); | |
2948 | cpu_sub_arch_name = top->sub_name; | |
2949 | cpu_arch_flags = top->flags; | |
2950 | cpu_arch_isa = top->isa; | |
2951 | cpu_arch_isa_flags = top->isa_flags; | |
4fc85f37 | 2952 | vector_size = top->vector_size; |
dfab07b9 JB |
2953 | no_cond_jump_promotion = top->no_cond_jump_promotion; |
2954 | ||
2955 | XDELETE (top); | |
2956 | } | |
2957 | ||
2958 | (void) restore_line_pointer (e); | |
2959 | demand_empty_rest_of_line (); | |
2960 | return; | |
2961 | } | |
2962 | ||
2963 | if (strcmp (string, "default") == 0) | |
2964 | { | |
2965 | if (strcmp (default_arch, "iamcu") == 0) | |
2966 | string = default_arch; | |
2967 | else | |
2968 | { | |
2969 | static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS; | |
2970 | ||
2971 | cpu_arch_name = NULL; | |
2972 | free (cpu_sub_arch_name); | |
2973 | cpu_sub_arch_name = NULL; | |
2974 | cpu_arch_flags = cpu_unknown_flags; | |
dfab07b9 JB |
2975 | cpu_arch_isa = PROCESSOR_UNKNOWN; |
2976 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; | |
2977 | if (!cpu_arch_tune_set) | |
fb263707 | 2978 | cpu_arch_tune = PROCESSOR_UNKNOWN; |
dfab07b9 | 2979 | |
4fc85f37 JB |
2980 | vector_size = VSZ_DEFAULT; |
2981 | ||
dfab07b9 JB |
2982 | j = ARRAY_SIZE (cpu_arch) + 1; |
2983 | } | |
2984 | } | |
2985 | ||
2986 | for (; j < ARRAY_SIZE (cpu_arch); j++) | |
2987 | { | |
2988 | if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0 | |
2989 | && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE)) | |
2990 | { | |
2991 | if (*string != '.') | |
2992 | { | |
2993 | check_cpu_arch_compatible (string, cpu_arch[j].enable); | |
3ce2ebcf | 2994 | |
da5f9eb4 | 2995 | if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 ) |
1d07cfb4 JB |
2996 | { |
2997 | as_bad (_("64bit mode not supported on `%s'."), | |
2998 | cpu_arch[j].name); | |
2999 | (void) restore_line_pointer (e); | |
3000 | ignore_rest_of_line (); | |
3001 | return; | |
3002 | } | |
3003 | ||
3004 | if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386) | |
3005 | { | |
3006 | as_bad (_("32bit mode not supported on `%s'."), | |
3007 | cpu_arch[j].name); | |
3008 | (void) restore_line_pointer (e); | |
3009 | ignore_rest_of_line (); | |
3010 | return; | |
3011 | } | |
3012 | ||
dfab07b9 | 3013 | cpu_arch_name = cpu_arch[j].name; |
3ce2ebcf JB |
3014 | free (cpu_sub_arch_name); |
3015 | cpu_sub_arch_name = NULL; | |
dfab07b9 | 3016 | cpu_arch_flags = cpu_arch[j].enable; |
dfab07b9 JB |
3017 | cpu_arch_isa = cpu_arch[j].type; |
3018 | cpu_arch_isa_flags = cpu_arch[j].enable; | |
3ce2ebcf | 3019 | if (!cpu_arch_tune_set) |
fb263707 | 3020 | cpu_arch_tune = cpu_arch_isa; |
4fc85f37 JB |
3021 | |
3022 | vector_size = VSZ_DEFAULT; | |
3023 | ||
dfab07b9 JB |
3024 | pre_386_16bit_warned = false; |
3025 | break; | |
3ce2ebcf | 3026 | } |
f68697e8 | 3027 | |
dfab07b9 JB |
3028 | if (cpu_flags_all_zero (&cpu_arch[j].enable)) |
3029 | continue; | |
f68697e8 | 3030 | |
bd483d21 | 3031 | isa_enable (j); |
f68697e8 JB |
3032 | |
3033 | (void) restore_line_pointer (e); | |
4fc85f37 JB |
3034 | |
3035 | switch (cpu_arch[j].vsz) | |
3036 | { | |
3037 | default: | |
3038 | break; | |
3039 | ||
3040 | case vsz_set: | |
3041 | #ifdef SVR4_COMMENT_CHARS | |
3042 | if (*input_line_pointer == ':' || *input_line_pointer == '/') | |
3043 | #else | |
3044 | if (*input_line_pointer == '/') | |
3045 | #endif | |
3046 | { | |
3047 | ++input_line_pointer; | |
3048 | switch (get_absolute_expression ()) | |
3049 | { | |
3050 | case 512: vector_size = VSZ512; break; | |
3051 | case 256: vector_size = VSZ256; break; | |
3052 | case 128: vector_size = VSZ128; break; | |
3053 | default: | |
3054 | as_bad (_("Unrecognized vector size specifier")); | |
3055 | ignore_rest_of_line (); | |
3056 | return; | |
3057 | } | |
3058 | break; | |
3059 | } | |
3060 | /* Fall through. */ | |
3061 | case vsz_reset: | |
3062 | vector_size = VSZ_DEFAULT; | |
3063 | break; | |
3064 | } | |
3065 | ||
f68697e8 JB |
3066 | demand_empty_rest_of_line (); |
3067 | return; | |
3068 | } | |
dfab07b9 | 3069 | } |
3ce2ebcf | 3070 | |
dfab07b9 JB |
3071 | if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch)) |
3072 | { | |
3073 | /* Disable an ISA extension. */ | |
3074 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
3075 | if (cpu_arch[j].type == PROCESSOR_NONE | |
3076 | && strcmp (string + 3, cpu_arch[j].name) == 0) | |
3077 | { | |
bd483d21 | 3078 | isa_disable (j); |
e413e4e9 | 3079 | |
4fc85f37 JB |
3080 | if (cpu_arch[j].vsz == vsz_set) |
3081 | vector_size = VSZ_DEFAULT; | |
3082 | ||
dfab07b9 JB |
3083 | (void) restore_line_pointer (e); |
3084 | demand_empty_rest_of_line (); | |
3085 | return; | |
3086 | } | |
e413e4e9 | 3087 | } |
dfab07b9 JB |
3088 | |
3089 | if (j == ARRAY_SIZE (cpu_arch)) | |
3090 | as_bad (_("no such architecture: `%s'"), string); | |
3091 | ||
3092 | *input_line_pointer = e; | |
e413e4e9 | 3093 | |
fddf5b5b AM |
3094 | no_cond_jump_promotion = 0; |
3095 | if (*input_line_pointer == ',' | |
29b0f896 | 3096 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 3097 | { |
d02603dc | 3098 | ++input_line_pointer; |
dfab07b9 JB |
3099 | e = get_symbol_name (&s); |
3100 | string = s; | |
fddf5b5b AM |
3101 | |
3102 | if (strcmp (string, "nojumps") == 0) | |
3103 | no_cond_jump_promotion = 1; | |
3104 | else if (strcmp (string, "jumps") == 0) | |
3105 | ; | |
3106 | else | |
3107 | as_bad (_("no such architecture modifier: `%s'"), string); | |
3108 | ||
d02603dc | 3109 | (void) restore_line_pointer (e); |
fddf5b5b AM |
3110 | } |
3111 | ||
e413e4e9 AM |
3112 | demand_empty_rest_of_line (); |
3113 | } | |
3114 | ||
8a9036a4 L |
3115 | enum bfd_architecture |
3116 | i386_arch (void) | |
3117 | { | |
c085ab00 | 3118 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 | 3119 | { |
ed049bd6 | 3120 | if (!IS_ELF || flag_code == CODE_64BIT) |
81486035 L |
3121 | as_fatal (_("Intel MCU is 32bit ELF only")); |
3122 | return bfd_arch_iamcu; | |
3123 | } | |
8a9036a4 L |
3124 | else |
3125 | return bfd_arch_i386; | |
3126 | } | |
3127 | ||
b9d79e03 | 3128 | unsigned long |
7016a5d5 | 3129 | i386_mach (void) |
b9d79e03 | 3130 | { |
d34049e8 | 3131 | if (startswith (default_arch, "x86_64")) |
8a9036a4 | 3132 | { |
c085ab00 | 3133 | if (default_arch[6] == '\0') |
8a9036a4 | 3134 | return bfd_mach_x86_64; |
351f65ca L |
3135 | else |
3136 | return bfd_mach_x64_32; | |
8a9036a4 | 3137 | } |
5197d474 L |
3138 | else if (!strcmp (default_arch, "i386") |
3139 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
3140 | { |
3141 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
3142 | { | |
ed049bd6 | 3143 | if (!IS_ELF) |
81486035 L |
3144 | as_fatal (_("Intel MCU is 32bit ELF only")); |
3145 | return bfd_mach_i386_iamcu; | |
3146 | } | |
3147 | else | |
3148 | return bfd_mach_i386_i386; | |
3149 | } | |
b9d79e03 | 3150 | else |
2b5d6a91 | 3151 | as_fatal (_("unknown architecture")); |
b9d79e03 | 3152 | } |
b9d79e03 | 3153 | \f |
99f0fb12 JB |
3154 | #include "opcodes/i386-tbl.h" |
3155 | ||
d3b01414 JB |
3156 | static void |
3157 | op_lookup (const char *mnemonic) | |
3158 | { | |
3159 | i386_op_off_t *pos = str_hash_find (op_hash, mnemonic); | |
3160 | ||
3161 | if (pos != NULL) | |
3162 | { | |
3163 | current_templates.start = &i386_optab[pos[0]]; | |
3164 | current_templates.end = &i386_optab[pos[1]]; | |
3165 | } | |
3166 | else | |
3167 | current_templates.end = current_templates.start = NULL; | |
3168 | } | |
3169 | ||
252b5132 | 3170 | void |
7016a5d5 | 3171 | md_begin (void) |
252b5132 | 3172 | { |
86fa6981 L |
3173 | /* Support pseudo prefixes like {disp32}. */ |
3174 | lex_type ['{'] = LEX_BEGIN_NAME; | |
3175 | ||
47926f60 | 3176 | /* Initialize op_hash hash table. */ |
629310ab | 3177 | op_hash = str_htab_create (); |
252b5132 RH |
3178 | |
3179 | { | |
d3b01414 JB |
3180 | const i386_op_off_t *cur = i386_op_sets; |
3181 | const i386_op_off_t *end = cur + ARRAY_SIZE (i386_op_sets) - 1; | |
3182 | ||
3183 | for (; cur < end; ++cur) | |
3184 | if (str_hash_insert (op_hash, insn_name (&i386_optab[*cur]), cur, 0)) | |
3185 | as_fatal (_("duplicate %s"), insn_name (&i386_optab[*cur])); | |
252b5132 RH |
3186 | } |
3187 | ||
47926f60 | 3188 | /* Initialize reg_hash hash table. */ |
629310ab | 3189 | reg_hash = str_htab_create (); |
252b5132 | 3190 | { |
29b0f896 | 3191 | const reg_entry *regtab; |
c3fe08fa | 3192 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3193 | |
c3fe08fa | 3194 | for (regtab = i386_regtab; regtab_size--; regtab++) |
6225c532 | 3195 | { |
6288d05f JB |
3196 | switch (regtab->reg_type.bitfield.class) |
3197 | { | |
3198 | case Reg: | |
34684862 JB |
3199 | if (regtab->reg_type.bitfield.dword) |
3200 | { | |
3201 | if (regtab->reg_type.bitfield.instance == Accum) | |
3202 | reg_eax = regtab; | |
3203 | } | |
3204 | else if (regtab->reg_type.bitfield.tbyte) | |
6288d05f JB |
3205 | { |
3206 | /* There's no point inserting st(<N>) in the hash table, as | |
3207 | parentheses aren't included in register_chars[] anyway. */ | |
3208 | if (regtab->reg_type.bitfield.instance != Accum) | |
3209 | continue; | |
3210 | reg_st0 = regtab; | |
3211 | } | |
3212 | break; | |
3213 | ||
5e042380 JB |
3214 | case SReg: |
3215 | switch (regtab->reg_num) | |
3216 | { | |
3217 | case 0: reg_es = regtab; break; | |
3218 | case 2: reg_ss = regtab; break; | |
3219 | case 3: reg_ds = regtab; break; | |
3220 | } | |
3221 | break; | |
3222 | ||
6288d05f JB |
3223 | case RegMask: |
3224 | if (!regtab->reg_num) | |
3225 | reg_k0 = regtab; | |
3226 | break; | |
3227 | } | |
3228 | ||
6225c532 JB |
3229 | if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL) |
3230 | as_fatal (_("duplicate %s"), regtab->reg_name); | |
6225c532 | 3231 | } |
252b5132 RH |
3232 | } |
3233 | ||
47926f60 | 3234 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3235 | { |
29b0f896 | 3236 | int c; |
d2b1a14d | 3237 | const char *p; |
252b5132 RH |
3238 | |
3239 | for (c = 0; c < 256; c++) | |
3240 | { | |
014fbcda | 3241 | if (ISDIGIT (c) || ISLOWER (c)) |
252b5132 RH |
3242 | { |
3243 | mnemonic_chars[c] = c; | |
3244 | register_chars[c] = c; | |
3245 | operand_chars[c] = c; | |
3246 | } | |
3882b010 | 3247 | else if (ISUPPER (c)) |
252b5132 | 3248 | { |
3882b010 | 3249 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3250 | register_chars[c] = mnemonic_chars[c]; |
3251 | operand_chars[c] = c; | |
3252 | } | |
b3983e5f JB |
3253 | #ifdef SVR4_COMMENT_CHARS |
3254 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3255 | operand_chars[c] = c; | |
3256 | #endif | |
252b5132 | 3257 | |
4795cd4a JB |
3258 | if (c >= 128) |
3259 | operand_chars[c] = c; | |
252b5132 RH |
3260 | } |
3261 | ||
c0f3af97 | 3262 | mnemonic_chars['_'] = '_'; |
791fe849 | 3263 | mnemonic_chars['-'] = '-'; |
0003779b | 3264 | mnemonic_chars['.'] = '.'; |
252b5132 | 3265 | |
d2b1a14d JB |
3266 | for (p = extra_symbol_chars; *p != '\0'; p++) |
3267 | operand_chars[(unsigned char) *p] = *p; | |
252b5132 RH |
3268 | for (p = operand_special_chars; *p != '\0'; p++) |
3269 | operand_chars[(unsigned char) *p] = *p; | |
3270 | } | |
3271 | ||
fabb73d1 | 3272 | if (object_64bit) |
a4447b93 | 3273 | { |
ca19b261 KT |
3274 | #if defined (OBJ_COFF) && defined (TE_PE) |
3275 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3276 | ? 32 : 16); | |
3277 | #else | |
a4447b93 | 3278 | x86_dwarf2_return_column = 16; |
ca19b261 | 3279 | #endif |
61ff971f | 3280 | x86_cie_data_alignment = -8; |
b52c4ee4 | 3281 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
788b11d9 JB |
3282 | x86_sframe_cfa_sp_reg = REG_SP; |
3283 | x86_sframe_cfa_fp_reg = REG_FP; | |
b52c4ee4 | 3284 | #endif |
a4447b93 RH |
3285 | } |
3286 | else | |
3287 | { | |
3288 | x86_dwarf2_return_column = 8; | |
3289 | x86_cie_data_alignment = -4; | |
3290 | } | |
e379e5f3 L |
3291 | |
3292 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3293 | can be turned into BRANCH_PREFIX frag. */ | |
3294 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3295 | abort (); | |
252b5132 RH |
3296 | } |
3297 | ||
3298 | void | |
e3bb37b5 | 3299 | i386_print_statistics (FILE *file) |
252b5132 | 3300 | { |
629310ab ML |
3301 | htab_print_statistics (file, "i386 opcode", op_hash); |
3302 | htab_print_statistics (file, "i386 register", reg_hash); | |
252b5132 | 3303 | } |
654d6f31 AM |
3304 | |
3305 | void | |
3306 | i386_md_end (void) | |
3307 | { | |
3308 | htab_delete (op_hash); | |
3309 | htab_delete (reg_hash); | |
3310 | } | |
252b5132 | 3311 | \f |
252b5132 RH |
3312 | #ifdef DEBUG386 |
3313 | ||
ce8a8b2f | 3314 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3315 | static void pte (insn_template *); |
40fb9820 | 3316 | static void pt (i386_operand_type); |
e3bb37b5 L |
3317 | static void pe (expressionS *); |
3318 | static void ps (symbolS *); | |
252b5132 RH |
3319 | |
3320 | static void | |
2c703856 | 3321 | pi (const char *line, i386_insn *x) |
252b5132 | 3322 | { |
09137c09 | 3323 | unsigned int j; |
252b5132 RH |
3324 | |
3325 | fprintf (stdout, "%s: template ", line); | |
3326 | pte (&x->tm); | |
09f131f2 JH |
3327 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3328 | x->base_reg ? x->base_reg->reg_name : "none", | |
3329 | x->index_reg ? x->index_reg->reg_name : "none", | |
3330 | x->log2_scale_factor); | |
3331 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3332 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3333 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3334 | x->sib.base, x->sib.index, x->sib.scale); | |
3335 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3336 | (x->rex & REX_W) != 0, |
3337 | (x->rex & REX_R) != 0, | |
3338 | (x->rex & REX_X) != 0, | |
3339 | (x->rex & REX_B) != 0); | |
09137c09 | 3340 | for (j = 0; j < x->operands; j++) |
252b5132 | 3341 | { |
09137c09 SP |
3342 | fprintf (stdout, " #%d: ", j + 1); |
3343 | pt (x->types[j]); | |
252b5132 | 3344 | fprintf (stdout, "\n"); |
bab6aec1 | 3345 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3346 | || x->types[j].bitfield.class == RegMMX |
3347 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3348 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3349 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3350 | || x->types[j].bitfield.class == RegCR |
3351 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3352 | || x->types[j].bitfield.class == RegTR |
3353 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3354 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3355 | if (operand_type_check (x->types[j], imm)) | |
3356 | pe (x->op[j].imms); | |
3357 | if (operand_type_check (x->types[j], disp)) | |
3358 | pe (x->op[j].disps); | |
252b5132 RH |
3359 | } |
3360 | } | |
3361 | ||
3362 | static void | |
d3ce72d0 | 3363 | pte (insn_template *t) |
252b5132 | 3364 | { |
b933fa4b | 3365 | static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; |
441f6aca | 3366 | static const char *const opc_spc[] = { |
0cc78721 | 3367 | NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL, |
441f6aca JB |
3368 | "XOP08", "XOP09", "XOP0A", |
3369 | }; | |
09137c09 | 3370 | unsigned int j; |
441f6aca | 3371 | |
252b5132 | 3372 | fprintf (stdout, " %d operands ", t->operands); |
441f6aca JB |
3373 | if (opc_pfx[t->opcode_modifier.opcodeprefix]) |
3374 | fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]); | |
ddb62495 JB |
3375 | if (opc_spc[t->opcode_space]) |
3376 | fprintf (stdout, "space %s ", opc_spc[t->opcode_space]); | |
47926f60 | 3377 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3378 | if (t->extension_opcode != None) |
3379 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3380 | if (t->opcode_modifier.d) |
252b5132 | 3381 | fprintf (stdout, "D"); |
40fb9820 | 3382 | if (t->opcode_modifier.w) |
252b5132 RH |
3383 | fprintf (stdout, "W"); |
3384 | fprintf (stdout, "\n"); | |
09137c09 | 3385 | for (j = 0; j < t->operands; j++) |
252b5132 | 3386 | { |
09137c09 SP |
3387 | fprintf (stdout, " #%d type ", j + 1); |
3388 | pt (t->operand_types[j]); | |
252b5132 RH |
3389 | fprintf (stdout, "\n"); |
3390 | } | |
3391 | } | |
3392 | ||
3393 | static void | |
e3bb37b5 | 3394 | pe (expressionS *e) |
252b5132 | 3395 | { |
24eab124 | 3396 | fprintf (stdout, " operation %d\n", e->X_op); |
b8281767 AM |
3397 | fprintf (stdout, " add_number %" PRId64 " (%" PRIx64 ")\n", |
3398 | (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number); | |
252b5132 RH |
3399 | if (e->X_add_symbol) |
3400 | { | |
3401 | fprintf (stdout, " add_symbol "); | |
3402 | ps (e->X_add_symbol); | |
3403 | fprintf (stdout, "\n"); | |
3404 | } | |
3405 | if (e->X_op_symbol) | |
3406 | { | |
3407 | fprintf (stdout, " op_symbol "); | |
3408 | ps (e->X_op_symbol); | |
3409 | fprintf (stdout, "\n"); | |
3410 | } | |
3411 | } | |
3412 | ||
3413 | static void | |
e3bb37b5 | 3414 | ps (symbolS *s) |
252b5132 RH |
3415 | { |
3416 | fprintf (stdout, "%s type %s%s", | |
3417 | S_GET_NAME (s), | |
3418 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3419 | segment_name (S_GET_SEGMENT (s))); | |
3420 | } | |
3421 | ||
7b81dfbb | 3422 | static struct type_name |
252b5132 | 3423 | { |
40fb9820 L |
3424 | i386_operand_type mask; |
3425 | const char *name; | |
252b5132 | 3426 | } |
7b81dfbb | 3427 | const type_names[] = |
252b5132 | 3428 | { |
05909f23 JB |
3429 | { { .bitfield = { .class = Reg, .byte = 1 } }, "r8" }, |
3430 | { { .bitfield = { .class = Reg, .word = 1 } }, "r16" }, | |
3431 | { { .bitfield = { .class = Reg, .dword = 1 } }, "r32" }, | |
3432 | { { .bitfield = { .class = Reg, .qword = 1 } }, "r64" }, | |
3433 | { { .bitfield = { .instance = Accum, .byte = 1 } }, "acc8" }, | |
3434 | { { .bitfield = { .instance = Accum, .word = 1 } }, "acc16" }, | |
3435 | { { .bitfield = { .instance = Accum, .dword = 1 } }, "acc32" }, | |
3436 | { { .bitfield = { .instance = Accum, .qword = 1 } }, "acc64" }, | |
3437 | { { .bitfield = { .imm8 = 1 } }, "i8" }, | |
3438 | { { .bitfield = { .imm8s = 1 } }, "i8s" }, | |
3439 | { { .bitfield = { .imm16 = 1 } }, "i16" }, | |
3440 | { { .bitfield = { .imm32 = 1 } }, "i32" }, | |
3441 | { { .bitfield = { .imm32s = 1 } }, "i32s" }, | |
3442 | { { .bitfield = { .imm64 = 1 } }, "i64" }, | |
3443 | { { .bitfield = { .imm1 = 1 } }, "i1" }, | |
3444 | { { .bitfield = { .baseindex = 1 } }, "BaseIndex" }, | |
3445 | { { .bitfield = { .disp8 = 1 } }, "d8" }, | |
3446 | { { .bitfield = { .disp16 = 1 } }, "d16" }, | |
3447 | { { .bitfield = { .disp32 = 1 } }, "d32" }, | |
3448 | { { .bitfield = { .disp64 = 1 } }, "d64" }, | |
3449 | { { .bitfield = { .instance = RegD, .word = 1 } }, "InOutPortReg" }, | |
3450 | { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" }, | |
3451 | { { .bitfield = { .class = RegCR } }, "control reg" }, | |
3452 | { { .bitfield = { .class = RegTR } }, "test reg" }, | |
3453 | { { .bitfield = { .class = RegDR } }, "debug reg" }, | |
3454 | { { .bitfield = { .class = Reg, .tbyte = 1 } }, "FReg" }, | |
3455 | { { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" }, | |
3456 | { { .bitfield = { .class = SReg } }, "SReg" }, | |
3457 | { { .bitfield = { .class = RegMMX } }, "rMMX" }, | |
3458 | { { .bitfield = { .class = RegSIMD, .xmmword = 1 } }, "rXMM" }, | |
3459 | { { .bitfield = { .class = RegSIMD, .ymmword = 1 } }, "rYMM" }, | |
3460 | { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" }, | |
3461 | { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" }, | |
3462 | { { .bitfield = { .class = RegMask } }, "Mask reg" }, | |
252b5132 RH |
3463 | }; |
3464 | ||
3465 | static void | |
40fb9820 | 3466 | pt (i386_operand_type t) |
252b5132 | 3467 | { |
40fb9820 | 3468 | unsigned int j; |
c6fb90c8 | 3469 | i386_operand_type a; |
252b5132 | 3470 | |
40fb9820 | 3471 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3472 | { |
3473 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3474 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3475 | fprintf (stdout, "%s, ", type_names[j].name); |
3476 | } | |
252b5132 RH |
3477 | fflush (stdout); |
3478 | } | |
3479 | ||
3480 | #endif /* DEBUG386 */ | |
3481 | \f | |
252b5132 | 3482 | static bfd_reloc_code_real_type |
3956db08 | 3483 | reloc (unsigned int size, |
64e74474 AM |
3484 | int pcrel, |
3485 | int sign, | |
3486 | bfd_reloc_code_real_type other) | |
252b5132 | 3487 | { |
47926f60 | 3488 | if (other != NO_RELOC) |
3956db08 | 3489 | { |
91d6fa6a | 3490 | reloc_howto_type *rel; |
3956db08 JB |
3491 | |
3492 | if (size == 8) | |
3493 | switch (other) | |
3494 | { | |
64e74474 AM |
3495 | case BFD_RELOC_X86_64_GOT32: |
3496 | return BFD_RELOC_X86_64_GOT64; | |
3497 | break; | |
553d1284 L |
3498 | case BFD_RELOC_X86_64_GOTPLT64: |
3499 | return BFD_RELOC_X86_64_GOTPLT64; | |
3500 | break; | |
64e74474 AM |
3501 | case BFD_RELOC_X86_64_PLTOFF64: |
3502 | return BFD_RELOC_X86_64_PLTOFF64; | |
3503 | break; | |
3504 | case BFD_RELOC_X86_64_GOTPC32: | |
3505 | other = BFD_RELOC_X86_64_GOTPC64; | |
3506 | break; | |
3507 | case BFD_RELOC_X86_64_GOTPCREL: | |
3508 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3509 | break; | |
3510 | case BFD_RELOC_X86_64_TPOFF32: | |
3511 | other = BFD_RELOC_X86_64_TPOFF64; | |
3512 | break; | |
3513 | case BFD_RELOC_X86_64_DTPOFF32: | |
3514 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3515 | break; | |
3516 | default: | |
3517 | break; | |
3956db08 | 3518 | } |
e05278af | 3519 | |
8ce3d284 | 3520 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3521 | if (other == BFD_RELOC_SIZE32) |
3522 | { | |
3523 | if (size == 8) | |
1ab668bf | 3524 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3525 | if (pcrel) |
1ab668bf AM |
3526 | { |
3527 | as_bad (_("there are no pc-relative size relocations")); | |
3528 | return NO_RELOC; | |
3529 | } | |
8fd4256d | 3530 | } |
8ce3d284 | 3531 | #endif |
8fd4256d | 3532 | |
e05278af | 3533 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3534 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3535 | sign = -1; |
3536 | ||
91d6fa6a NC |
3537 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3538 | if (!rel) | |
3956db08 | 3539 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3540 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3541 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3542 | bfd_get_reloc_size (rel), |
3956db08 | 3543 | size); |
91d6fa6a | 3544 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3545 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3546 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3547 | && !sign) |
91d6fa6a | 3548 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3549 | && sign > 0)) |
3956db08 JB |
3550 | as_bad (_("relocated field and relocation type differ in signedness")); |
3551 | else | |
3552 | return other; | |
3553 | return NO_RELOC; | |
3554 | } | |
252b5132 RH |
3555 | |
3556 | if (pcrel) | |
3557 | { | |
3e73aa7c | 3558 | if (!sign) |
3956db08 | 3559 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3560 | switch (size) |
3561 | { | |
3562 | case 1: return BFD_RELOC_8_PCREL; | |
3563 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3564 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3565 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3566 | } |
3956db08 | 3567 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3568 | } |
3569 | else | |
3570 | { | |
3956db08 | 3571 | if (sign > 0) |
e5cb08ac | 3572 | switch (size) |
3e73aa7c JH |
3573 | { |
3574 | case 4: return BFD_RELOC_X86_64_32S; | |
3575 | } | |
3576 | else | |
3577 | switch (size) | |
3578 | { | |
3579 | case 1: return BFD_RELOC_8; | |
3580 | case 2: return BFD_RELOC_16; | |
3581 | case 4: return BFD_RELOC_32; | |
3582 | case 8: return BFD_RELOC_64; | |
3583 | } | |
3956db08 JB |
3584 | as_bad (_("cannot do %s %u byte relocation"), |
3585 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3586 | } |
3587 | ||
0cc9e1d3 | 3588 | return NO_RELOC; |
252b5132 RH |
3589 | } |
3590 | ||
071c5d81 | 3591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
47926f60 KH |
3592 | /* Here we decide which fixups can be adjusted to make them relative to |
3593 | the beginning of the section instead of the symbol. Basically we need | |
3594 | to make sure that the dynamic relocations are done correctly, so in | |
3595 | some cases we force the original symbol to be used. */ | |
3596 | ||
252b5132 | 3597 | int |
071c5d81 | 3598 | tc_i386_fix_adjustable (fixS *fixP) |
252b5132 | 3599 | { |
718ddfc0 | 3600 | if (!IS_ELF) |
31312f95 AM |
3601 | return 1; |
3602 | ||
a161fe53 AM |
3603 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3604 | mode. */ | |
3605 | if (use_rela_relocations | |
3606 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3607 | && fixP->fx_pcrel) | |
252b5132 | 3608 | return 0; |
31312f95 | 3609 | |
8d01d9a9 AJ |
3610 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3611 | and changed later by validate_fix. */ | |
3612 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3613 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3614 | return 0; | |
3615 | ||
8fd4256d L |
3616 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3617 | for size relocations. */ | |
3618 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3619 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3620 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3621 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3622 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3623 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3624 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3625 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3626 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3627 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3628 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3629 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3630 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3631 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3632 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3633 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3634 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3635 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3636 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
3d5a60de | 3637 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX |
bffbf940 JJ |
3638 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3639 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3640 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3641 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 | 3642 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
a533c8df | 3643 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTTPOFF |
5bc71c2a | 3644 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTTPOFF |
bffbf940 | 3645 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 |
d6ab8113 JB |
3646 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3647 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 | 3648 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
a533c8df | 3649 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC |
67a4f2b7 | 3650 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL |
252b5132 RH |
3651 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3652 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3653 | return 0; | |
3654 | return 1; | |
3655 | } | |
071c5d81 | 3656 | #endif |
252b5132 | 3657 | |
a9aabc23 JB |
3658 | static INLINE bool |
3659 | want_disp32 (const insn_template *t) | |
3660 | { | |
3661 | return flag_code != CODE_64BIT | |
3662 | || i.prefix[ADDR_PREFIX] | |
7fc69528 | 3663 | || (t->mnem_off == MN_lea |
fe134c65 JB |
3664 | && (!i.types[1].bitfield.qword |
3665 | || t->opcode_modifier.size == SIZE32)); | |
a9aabc23 JB |
3666 | } |
3667 | ||
b4cac588 | 3668 | static int |
e3bb37b5 | 3669 | intel_float_operand (const char *mnemonic) |
252b5132 | 3670 | { |
9306ca4a JB |
3671 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3672 | operands, hence the code here is free to improperly handle opcodes that | |
3673 | have no operands (for better performance and smaller code). */ | |
3674 | ||
3675 | if (mnemonic[0] != 'f') | |
3676 | return 0; /* non-math */ | |
3677 | ||
3678 | switch (mnemonic[1]) | |
3679 | { | |
3680 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3681 | the fs segment override prefix not currently handled because no | |
3682 | call path can make opcodes without operands get here */ | |
3683 | case 'i': | |
3684 | return 2 /* integer op */; | |
3685 | case 'l': | |
3686 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3687 | return 3; /* fldcw/fldenv */ | |
3688 | break; | |
3689 | case 'n': | |
3690 | if (mnemonic[2] != 'o' /* fnop */) | |
3691 | return 3; /* non-waiting control op */ | |
3692 | break; | |
3693 | case 'r': | |
3694 | if (mnemonic[2] == 's') | |
3695 | return 3; /* frstor/frstpm */ | |
3696 | break; | |
3697 | case 's': | |
3698 | if (mnemonic[2] == 'a') | |
3699 | return 3; /* fsave */ | |
3700 | if (mnemonic[2] == 't') | |
3701 | { | |
3702 | switch (mnemonic[3]) | |
3703 | { | |
3704 | case 'c': /* fstcw */ | |
3705 | case 'd': /* fstdw */ | |
3706 | case 'e': /* fstenv */ | |
3707 | case 's': /* fsts[gw] */ | |
3708 | return 3; | |
3709 | } | |
3710 | } | |
3711 | break; | |
3712 | case 'x': | |
3713 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3714 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3715 | break; | |
3716 | } | |
252b5132 | 3717 | |
9306ca4a | 3718 | return 1; |
252b5132 RH |
3719 | } |
3720 | ||
9a182d04 JB |
3721 | static INLINE void |
3722 | install_template (const insn_template *t) | |
3723 | { | |
3724 | unsigned int l; | |
3725 | ||
3726 | i.tm = *t; | |
3727 | ||
a6f3add0 JB |
3728 | /* Dual VEX/EVEX templates need stripping one of the possible variants. */ |
3729 | if (t->opcode_modifier.vex && t->opcode_modifier.evex) | |
6177c84d | 3730 | { |
a5e91879 JB |
3731 | if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2) |
3732 | || maybe_cpu (t, CpuFMA)) | |
3733 | && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL))) | |
a6f3add0 | 3734 | { |
6177c84d | 3735 | if (need_evex_encoding (t)) |
a6f3add0 JB |
3736 | { |
3737 | i.tm.opcode_modifier.vex = 0; | |
a5e91879 JB |
3738 | i.tm.cpu.bitfield.cpuavx512f = i.tm.cpu_any.bitfield.cpuavx512f; |
3739 | i.tm.cpu.bitfield.cpuavx512vl = i.tm.cpu_any.bitfield.cpuavx512vl; | |
a6f3add0 JB |
3740 | } |
3741 | else | |
3742 | { | |
3743 | i.tm.opcode_modifier.evex = 0; | |
a5e91879 JB |
3744 | if (i.tm.cpu_any.bitfield.cpuavx) |
3745 | i.tm.cpu.bitfield.cpuavx = 1; | |
3746 | else if (!i.tm.cpu.bitfield.isa) | |
3747 | i.tm.cpu.bitfield.isa = i.tm.cpu_any.bitfield.isa; | |
3748 | else | |
3749 | gas_assert (i.tm.cpu.bitfield.isa == i.tm.cpu_any.bitfield.isa); | |
a6f3add0 JB |
3750 | } |
3751 | } | |
6177c84d CL |
3752 | |
3753 | if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE) | |
3754 | || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ) | |
3755 | || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI) | |
5190fa38 | 3756 | || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)) |
6177c84d CL |
3757 | && maybe_cpu (t, CpuAPX_F)) |
3758 | { | |
3759 | if (need_evex_encoding (t)) | |
3760 | i.tm.opcode_modifier.vex = 0; | |
3761 | else | |
3762 | i.tm.opcode_modifier.evex = 0; | |
3763 | } | |
3764 | } | |
a6f3add0 | 3765 | |
9a182d04 JB |
3766 | /* Note that for pseudo prefixes this produces a length of 1. But for them |
3767 | the length isn't interesting at all. */ | |
3768 | for (l = 1; l < 4; ++l) | |
3769 | if (!(t->base_opcode >> (8 * l))) | |
3770 | break; | |
3771 | ||
3772 | i.opcode_length = l; | |
3773 | } | |
3774 | ||
c0f3af97 L |
3775 | /* Build the VEX prefix. */ |
3776 | ||
3777 | static void | |
d3ce72d0 | 3778 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3779 | { |
3780 | unsigned int register_specifier; | |
c0f3af97 | 3781 | unsigned int vector_length; |
03751133 | 3782 | unsigned int w; |
c0f3af97 L |
3783 | |
3784 | /* Check register specifier. */ | |
3785 | if (i.vex.register_specifier) | |
43234a1e L |
3786 | { |
3787 | register_specifier = | |
3788 | ~register_number (i.vex.register_specifier) & 0xf; | |
3789 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3790 | } | |
c0f3af97 L |
3791 | else |
3792 | register_specifier = 0xf; | |
3793 | ||
79f0fa25 L |
3794 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3795 | if there are more than 1 register operand. */ | |
3796 | if (i.reg_operands > 1 | |
e346d50a | 3797 | && i.encoding != encoding_vex3 |
86fa6981 | 3798 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3799 | && i.operands == i.reg_operands |
dbbc8b7e | 3800 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
ddb62495 | 3801 | && i.tm.opcode_space == SPACE_0F |
dbbc8b7e | 3802 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3803 | && i.rex == REX_B) |
3804 | { | |
67748abf | 3805 | unsigned int xchg; |
fa99fab2 | 3806 | |
67748abf | 3807 | swap_2_operands (0, i.operands - 1); |
fa99fab2 | 3808 | |
9c2799c2 | 3809 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3810 | |
3811 | i.rex = REX_R; | |
3812 | xchg = i.rm.regmem; | |
3813 | i.rm.regmem = i.rm.reg; | |
3814 | i.rm.reg = xchg; | |
3815 | ||
dbbc8b7e JB |
3816 | if (i.tm.opcode_modifier.d) |
3817 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
2c735193 | 3818 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
dbbc8b7e | 3819 | else /* Use the next insn. */ |
9a182d04 | 3820 | install_template (&t[1]); |
fa99fab2 L |
3821 | } |
3822 | ||
79dec6b7 JB |
3823 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3824 | are no memory operands and at least 3 register ones. */ | |
3825 | if (i.reg_operands >= 3 | |
e346d50a | 3826 | && i.encoding != encoding_vex3 |
79dec6b7 JB |
3827 | && i.reg_operands == i.operands - i.imm_operands |
3828 | && i.tm.opcode_modifier.vex | |
3829 | && i.tm.opcode_modifier.commutative | |
7440781b JB |
3830 | /* .commutative aliases .staticrounding; disambiguate. */ |
3831 | && !i.tm.opcode_modifier.sae | |
33740f21 JB |
3832 | && (i.tm.opcode_modifier.sse2avx |
3833 | || (optimize > 1 && !i.no_optimize)) | |
79dec6b7 JB |
3834 | && i.rex == REX_B |
3835 | && i.vex.register_specifier | |
3836 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3837 | { | |
3838 | unsigned int xchg = i.operands - i.reg_operands; | |
79dec6b7 | 3839 | |
ddb62495 | 3840 | gas_assert (i.tm.opcode_space == SPACE_0F); |
79dec6b7 JB |
3841 | gas_assert (!i.tm.opcode_modifier.sae); |
3842 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3843 | &i.types[i.operands - 3])); | |
3844 | gas_assert (i.rm.mode == 3); | |
3845 | ||
67748abf | 3846 | swap_2_operands (xchg, xchg + 1); |
79dec6b7 JB |
3847 | |
3848 | i.rex = 0; | |
3849 | xchg = i.rm.regmem | 8; | |
3850 | i.rm.regmem = ~register_specifier & 0xf; | |
3851 | gas_assert (!(i.rm.regmem & 8)); | |
3852 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3853 | register_specifier = ~xchg & 0xf; | |
3854 | } | |
3855 | ||
539f890d L |
3856 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3857 | vector_length = avxscalar; | |
10c17abd JB |
3858 | else if (i.tm.opcode_modifier.vex == VEX256) |
3859 | vector_length = 1; | |
d0c2e3ec JB |
3860 | else if (dot_insn () && i.tm.opcode_modifier.vex == VEX128) |
3861 | vector_length = 0; | |
539f890d | 3862 | else |
10c17abd | 3863 | { |
56522fc5 | 3864 | unsigned int op; |
10c17abd | 3865 | |
c7213af9 L |
3866 | /* Determine vector length from the last multi-length vector |
3867 | operand. */ | |
10c17abd | 3868 | vector_length = 0; |
56522fc5 | 3869 | for (op = t->operands; op--;) |
10c17abd JB |
3870 | if (t->operand_types[op].bitfield.xmmword |
3871 | && t->operand_types[op].bitfield.ymmword | |
3872 | && i.types[op].bitfield.ymmword) | |
3873 | { | |
3874 | vector_length = 1; | |
3875 | break; | |
3876 | } | |
3877 | } | |
c0f3af97 | 3878 | |
03751133 L |
3879 | /* Check the REX.W bit and VEXW. */ |
3880 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3881 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
ebe82bfd | 3882 | else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W)) |
03751133 L |
3883 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; |
3884 | else | |
931d03b7 | 3885 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3886 | |
c0f3af97 | 3887 | /* Use 2-byte VEX prefix if possible. */ |
03751133 | 3888 | if (w == 0 |
e346d50a | 3889 | && i.encoding != encoding_vex3 |
ddb62495 | 3890 | && i.tm.opcode_space == SPACE_0F |
c0f3af97 L |
3891 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3892 | { | |
3893 | /* 2-byte VEX prefix. */ | |
3894 | unsigned int r; | |
3895 | ||
3896 | i.vex.length = 2; | |
3897 | i.vex.bytes[0] = 0xc5; | |
3898 | ||
3899 | /* Check the REX.R bit. */ | |
3900 | r = (i.rex & REX_R) ? 0 : 1; | |
3901 | i.vex.bytes[1] = (r << 7 | |
3902 | | register_specifier << 3 | |
3903 | | vector_length << 2 | |
35648716 | 3904 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3905 | } |
3906 | else | |
3907 | { | |
3908 | /* 3-byte VEX prefix. */ | |
f88c9eb0 | 3909 | i.vex.length = 3; |
f88c9eb0 | 3910 | |
ddb62495 | 3911 | switch (i.tm.opcode_space) |
5dd85c99 | 3912 | { |
441f6aca JB |
3913 | case SPACE_0F: |
3914 | case SPACE_0F38: | |
3915 | case SPACE_0F3A: | |
8170af78 | 3916 | case SPACE_VEXMAP7: |
80de6e00 | 3917 | i.vex.bytes[0] = 0xc4; |
7f399153 | 3918 | break; |
441f6aca JB |
3919 | case SPACE_XOP08: |
3920 | case SPACE_XOP09: | |
3921 | case SPACE_XOP0A: | |
f88c9eb0 | 3922 | i.vex.bytes[0] = 0x8f; |
7f399153 L |
3923 | break; |
3924 | default: | |
3925 | abort (); | |
f88c9eb0 | 3926 | } |
c0f3af97 | 3927 | |
c0f3af97 L |
3928 | /* The high 3 bits of the second VEX byte are 1's compliment |
3929 | of RXB bits from REX. */ | |
d0c2e3ec JB |
3930 | i.vex.bytes[1] = ((~i.rex & 7) << 5) |
3931 | | (!dot_insn () ? i.tm.opcode_space | |
3932 | : i.insn_opcode_space); | |
c0f3af97 | 3933 | |
c0f3af97 L |
3934 | i.vex.bytes[2] = (w << 7 |
3935 | | register_specifier << 3 | |
3936 | | vector_length << 2 | |
35648716 | 3937 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3938 | } |
3939 | } | |
3940 | ||
5b7c81bd | 3941 | static INLINE bool |
7a8655d2 JB |
3942 | is_any_vex_encoding (const insn_template *t) |
3943 | { | |
706ce984 | 3944 | return t->opcode_modifier.vex || t->opcode_modifier.evex; |
7a8655d2 JB |
3945 | } |
3946 | ||
6177c84d CL |
3947 | /* We can use this function only when the current encoding is evex. */ |
3948 | static INLINE bool | |
3949 | is_apx_evex_encoding (void) | |
3950 | { | |
dd74a603 | 3951 | return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4 || i.has_nf |
6177c84d CL |
3952 | || (i.vex.register_specifier |
3953 | && (i.vex.register_specifier->reg_flags & RegRex2)); | |
3954 | } | |
3955 | ||
80d61d8d CL |
3956 | static INLINE bool |
3957 | is_apx_rex2_encoding (void) | |
3958 | { | |
ac32c879 | 3959 | return i.rex2 || i.rex2_encoding |
3037cefe | 3960 | || i.tm.opcode_modifier.rex2; |
80d61d8d CL |
3961 | } |
3962 | ||
a5748e0d JB |
3963 | static unsigned int |
3964 | get_broadcast_bytes (const insn_template *t, bool diag) | |
3965 | { | |
3966 | unsigned int op, bytes; | |
3967 | const i386_operand_type *types; | |
3968 | ||
3969 | if (i.broadcast.type) | |
9b345ce8 | 3970 | return (1 << (t->opcode_modifier.broadcast - 1)) * i.broadcast.type; |
a5748e0d JB |
3971 | |
3972 | gas_assert (intel_syntax); | |
3973 | ||
3974 | for (op = 0; op < t->operands; ++op) | |
3975 | if (t->operand_types[op].bitfield.baseindex) | |
3976 | break; | |
3977 | ||
3978 | gas_assert (op < t->operands); | |
3979 | ||
706ce984 | 3980 | if (t->opcode_modifier.evex != EVEXDYN) |
a5748e0d JB |
3981 | switch (i.broadcast.bytes) |
3982 | { | |
3983 | case 1: | |
3984 | if (t->operand_types[op].bitfield.word) | |
3985 | return 2; | |
3986 | /* Fall through. */ | |
3987 | case 2: | |
3988 | if (t->operand_types[op].bitfield.dword) | |
3989 | return 4; | |
3990 | /* Fall through. */ | |
3991 | case 4: | |
3992 | if (t->operand_types[op].bitfield.qword) | |
3993 | return 8; | |
3994 | /* Fall through. */ | |
3995 | case 8: | |
3996 | if (t->operand_types[op].bitfield.xmmword) | |
3997 | return 16; | |
3998 | if (t->operand_types[op].bitfield.ymmword) | |
3999 | return 32; | |
4000 | if (t->operand_types[op].bitfield.zmmword) | |
4001 | return 64; | |
4002 | /* Fall through. */ | |
4003 | default: | |
4004 | abort (); | |
4005 | } | |
4006 | ||
4007 | gas_assert (op + 1 < t->operands); | |
4008 | ||
4009 | if (t->operand_types[op + 1].bitfield.xmmword | |
4010 | + t->operand_types[op + 1].bitfield.ymmword | |
4011 | + t->operand_types[op + 1].bitfield.zmmword > 1) | |
4012 | { | |
4013 | types = &i.types[op + 1]; | |
4014 | diag = false; | |
4015 | } | |
4016 | else /* Ambiguous - guess with a preference to non-AVX512VL forms. */ | |
4017 | types = &t->operand_types[op]; | |
4018 | ||
4019 | if (types->bitfield.zmmword) | |
4020 | bytes = 64; | |
4021 | else if (types->bitfield.ymmword) | |
4022 | bytes = 32; | |
4023 | else | |
4024 | bytes = 16; | |
4025 | ||
4026 | if (diag) | |
4027 | as_warn (_("ambiguous broadcast for `%s', using %u-bit form"), | |
76d3f746 | 4028 | insn_name (t), bytes * 8); |
a5748e0d JB |
4029 | |
4030 | return bytes; | |
4031 | } | |
4032 | ||
43234a1e L |
4033 | /* Build the EVEX prefix. */ |
4034 | ||
4035 | static void | |
4036 | build_evex_prefix (void) | |
4037 | { | |
35648716 | 4038 | unsigned int register_specifier, w; |
43234a1e L |
4039 | rex_byte vrex_used = 0; |
4040 | ||
4041 | /* Check register specifier. */ | |
4042 | if (i.vex.register_specifier) | |
4043 | { | |
4044 | gas_assert ((i.vrex & REX_X) == 0); | |
4045 | ||
4046 | register_specifier = i.vex.register_specifier->reg_num; | |
4047 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
4048 | register_specifier += 8; | |
4049 | /* The upper 16 registers are encoded in the fourth byte of the | |
4050 | EVEX prefix. */ | |
4051 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
4052 | i.vex.bytes[3] = 0x8; | |
4053 | register_specifier = ~register_specifier & 0xf; | |
4054 | } | |
4055 | else | |
4056 | { | |
4057 | register_specifier = 0xf; | |
4058 | ||
4059 | /* Encode upper 16 vector index register in the fourth byte of | |
4060 | the EVEX prefix. */ | |
4061 | if (!(i.vrex & REX_X)) | |
4062 | i.vex.bytes[3] = 0x8; | |
4063 | else | |
4064 | vrex_used |= REX_X; | |
4065 | } | |
4066 | ||
43234a1e L |
4067 | /* 4 byte EVEX prefix. */ |
4068 | i.vex.length = 4; | |
4069 | i.vex.bytes[0] = 0x62; | |
4070 | ||
43234a1e L |
4071 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
4072 | bits from REX. */ | |
ddb62495 | 4073 | gas_assert (i.tm.opcode_space >= SPACE_0F); |
5190fa38 | 4074 | gas_assert (i.tm.opcode_space <= SPACE_VEXMAP7); |
d0c2e3ec JB |
4075 | i.vex.bytes[1] = ((~i.rex & 7) << 5) |
4076 | | (!dot_insn () ? i.tm.opcode_space | |
4077 | : i.insn_opcode_space); | |
43234a1e L |
4078 | |
4079 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
4080 | REX_R bit in VREX. */ | |
4081 | if (!(i.vrex & REX_R)) | |
4082 | i.vex.bytes[1] |= 0x10; | |
4083 | else | |
4084 | vrex_used |= REX_R; | |
4085 | ||
4086 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
4087 | { | |
4088 | /* When all operands are registers, the REX_X bit in REX is not | |
4089 | used. We reuse it to encode the upper 16 registers, which is | |
4090 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
4091 | as 1's compliment. */ | |
4092 | if ((i.vrex & REX_B)) | |
4093 | { | |
4094 | vrex_used |= REX_B; | |
4095 | i.vex.bytes[1] &= ~0x40; | |
4096 | } | |
4097 | } | |
4098 | ||
4099 | /* EVEX instructions shouldn't need the REX prefix. */ | |
4100 | i.vrex &= ~vrex_used; | |
4101 | gas_assert (i.vrex == 0); | |
4102 | ||
6865c043 L |
4103 | /* Check the REX.W bit and VEXW. */ |
4104 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
4105 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
4106 | else if (i.tm.opcode_modifier.vexw) | |
4107 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
4108 | else | |
931d03b7 | 4109 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e | 4110 | |
43234a1e | 4111 | /* The third byte of the EVEX prefix. */ |
35648716 JB |
4112 | i.vex.bytes[2] = ((w << 7) |
4113 | | (register_specifier << 3) | |
4114 | | 4 /* Encode the U bit. */ | |
4115 | | i.tm.opcode_modifier.opcodeprefix); | |
43234a1e L |
4116 | |
4117 | /* The fourth byte of the EVEX prefix. */ | |
4118 | /* The zeroing-masking bit. */ | |
6225c532 | 4119 | if (i.mask.reg && i.mask.zeroing) |
43234a1e L |
4120 | i.vex.bytes[3] |= 0x80; |
4121 | ||
4122 | /* Don't always set the broadcast bit if there is no RC. */ | |
ca5312a2 | 4123 | if (i.rounding.type == rc_none) |
43234a1e L |
4124 | { |
4125 | /* Encode the vector length. */ | |
4126 | unsigned int vec_length; | |
4127 | ||
706ce984 | 4128 | if (i.tm.opcode_modifier.evex == EVEXDYN) |
e771e7c9 | 4129 | { |
56522fc5 | 4130 | unsigned int op; |
e771e7c9 | 4131 | |
c7213af9 L |
4132 | /* Determine vector length from the last multi-length vector |
4133 | operand. */ | |
56522fc5 | 4134 | for (op = i.operands; op--;) |
e771e7c9 JB |
4135 | if (i.tm.operand_types[op].bitfield.xmmword |
4136 | + i.tm.operand_types[op].bitfield.ymmword | |
4137 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
4138 | { | |
4139 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
4140 | { |
4141 | i.tm.opcode_modifier.evex = EVEX512; | |
4142 | break; | |
4143 | } | |
e771e7c9 | 4144 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
4145 | { |
4146 | i.tm.opcode_modifier.evex = EVEX256; | |
4147 | break; | |
4148 | } | |
e771e7c9 | 4149 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
4150 | { |
4151 | i.tm.opcode_modifier.evex = EVEX128; | |
4152 | break; | |
4153 | } | |
9b345ce8 JB |
4154 | else if ((i.broadcast.type || i.broadcast.bytes) |
4155 | && op == i.broadcast.operand) | |
625cbd7a | 4156 | { |
a5748e0d | 4157 | switch (get_broadcast_bytes (&i.tm, true)) |
625cbd7a JB |
4158 | { |
4159 | case 64: | |
4160 | i.tm.opcode_modifier.evex = EVEX512; | |
4161 | break; | |
4162 | case 32: | |
4163 | i.tm.opcode_modifier.evex = EVEX256; | |
4164 | break; | |
4165 | case 16: | |
4166 | i.tm.opcode_modifier.evex = EVEX128; | |
4167 | break; | |
4168 | default: | |
c7213af9 | 4169 | abort (); |
625cbd7a | 4170 | } |
c7213af9 | 4171 | break; |
625cbd7a | 4172 | } |
e771e7c9 | 4173 | } |
c7213af9 | 4174 | |
56522fc5 | 4175 | if (op >= MAX_OPERANDS) |
c7213af9 | 4176 | abort (); |
e771e7c9 JB |
4177 | } |
4178 | ||
43234a1e L |
4179 | switch (i.tm.opcode_modifier.evex) |
4180 | { | |
4181 | case EVEXLIG: /* LL' is ignored */ | |
4182 | vec_length = evexlig << 5; | |
4183 | break; | |
4184 | case EVEX128: | |
4185 | vec_length = 0 << 5; | |
4186 | break; | |
4187 | case EVEX256: | |
4188 | vec_length = 1 << 5; | |
4189 | break; | |
4190 | case EVEX512: | |
4191 | vec_length = 2 << 5; | |
4192 | break; | |
d0c2e3ec JB |
4193 | case EVEX_L3: |
4194 | if (dot_insn ()) | |
4195 | { | |
4196 | vec_length = 3 << 5; | |
4197 | break; | |
4198 | } | |
4199 | /* Fall through. */ | |
43234a1e L |
4200 | default: |
4201 | abort (); | |
4202 | break; | |
4203 | } | |
4204 | i.vex.bytes[3] |= vec_length; | |
4205 | /* Encode the broadcast bit. */ | |
9b345ce8 | 4206 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e L |
4207 | i.vex.bytes[3] |= 0x10; |
4208 | } | |
ca5312a2 JB |
4209 | else if (i.rounding.type != saeonly) |
4210 | i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5); | |
43234a1e | 4211 | else |
ca5312a2 | 4212 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e | 4213 | |
6225c532 JB |
4214 | if (i.mask.reg) |
4215 | i.vex.bytes[3] |= i.mask.reg->reg_num; | |
43234a1e L |
4216 | } |
4217 | ||
80d61d8d CL |
4218 | /* Build (2 bytes) rex2 prefix. |
4219 | | D5h | | |
4220 | | m | R4 X4 B4 | W R X B | | |
4221 | ||
4222 | Rex2 reuses i.vex as they both encode i.tm.opcode_space in their prefixes. | |
4223 | */ | |
4224 | static void | |
4225 | build_rex2_prefix (void) | |
4226 | { | |
4227 | i.vex.length = 2; | |
4228 | i.vex.bytes[0] = 0xd5; | |
4229 | /* For the W R X B bits, the variables of rex prefix will be reused. */ | |
4230 | i.vex.bytes[1] = ((i.tm.opcode_space << 7) | |
4231 | | (i.rex2 << 4) | i.rex); | |
4232 | } | |
4233 | ||
6177c84d CL |
4234 | /* Build the EVEX prefix (4-byte) for evex insn |
4235 | | 62h | | |
4236 | | `R`X`B`R' | B'mmm | | |
4237 | | W | v`v`v`v | `x' | pp | | |
4238 | | z| L'L | b | `v | aaa | | |
4239 | */ | |
4240 | static void | |
4241 | build_apx_evex_prefix (void) | |
4242 | { | |
4243 | build_evex_prefix (); | |
4244 | if (i.rex2 & REX_R) | |
4245 | i.vex.bytes[1] &= ~0x10; | |
4246 | if (i.rex2 & REX_B) | |
4247 | i.vex.bytes[1] |= 0x08; | |
4248 | if (i.rex2 & REX_X) | |
4249 | i.vex.bytes[2] &= ~0x04; | |
4250 | if (i.vex.register_specifier | |
4251 | && i.vex.register_specifier->reg_flags & RegRex2) | |
4252 | i.vex.bytes[3] &= ~0x08; | |
3083f376 | 4253 | |
4254 | /* Encode the NDD bit of the instruction promoted from the legacy | |
4255 | space. */ | |
4256 | if (i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4) | |
4257 | i.vex.bytes[3] |= 0x10; | |
dd74a603 CL |
4258 | |
4259 | /* Encode the NF bit. */ | |
4260 | if (i.has_nf) | |
4261 | i.vex.bytes[3] |= 0x04; | |
6177c84d CL |
4262 | } |
4263 | ||
ce705688 JB |
4264 | static void establish_rex (void) |
4265 | { | |
4266 | /* Note that legacy encodings have at most 2 non-immediate operands. */ | |
4267 | unsigned int first = i.imm_operands; | |
4268 | unsigned int last = i.operands > first ? i.operands - first - 1 : first; | |
4269 | ||
4270 | /* Respect a user-specified REX prefix. */ | |
4271 | i.rex |= i.prefix[REX_PREFIX] & REX_OPCODE; | |
4272 | ||
4273 | /* For 8 bit registers we need an empty rex prefix. Also if the | |
4274 | instruction already has a prefix, we need to convert old | |
4275 | registers to new ones. */ | |
4276 | ||
4277 | if ((i.types[first].bitfield.class == Reg && i.types[first].bitfield.byte | |
80d61d8d CL |
4278 | && ((i.op[first].regs->reg_flags & RegRex64) != 0 || i.rex != 0 |
4279 | || i.rex2 != 0)) | |
ce705688 | 4280 | || (i.types[last].bitfield.class == Reg && i.types[last].bitfield.byte |
80d61d8d CL |
4281 | && ((i.op[last].regs->reg_flags & RegRex64) != 0 || i.rex != 0 |
4282 | || i.rex2 != 0))) | |
ce705688 JB |
4283 | { |
4284 | unsigned int x; | |
4285 | ||
80d61d8d CL |
4286 | if (!is_apx_rex2_encoding () && !is_any_vex_encoding(&i.tm)) |
4287 | i.rex |= REX_OPCODE; | |
ce705688 JB |
4288 | for (x = first; x <= last; x++) |
4289 | { | |
4290 | /* Look for 8 bit operand that uses old registers. */ | |
4291 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte | |
4292 | && (i.op[x].regs->reg_flags & RegRex64) == 0) | |
4293 | { | |
4294 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); | |
4295 | /* In case it is "hi" register, give up. */ | |
4296 | if (i.op[x].regs->reg_num > 3) | |
4297 | as_bad (_("can't encode register '%s%s' in an " | |
80d61d8d | 4298 | "instruction requiring REX/REX2 prefix"), |
ce705688 JB |
4299 | register_prefix, i.op[x].regs->reg_name); |
4300 | ||
4301 | /* Otherwise it is equivalent to the extended register. | |
4302 | Since the encoding doesn't change this is merely | |
4303 | cosmetic cleanup for debug output. */ | |
4304 | i.op[x].regs += 8; | |
4305 | } | |
4306 | } | |
4307 | } | |
4308 | ||
192781a3 | 4309 | if (i.rex == 0 && i.rex2 == 0 && (i.rex_encoding || i.rex2_encoding)) |
ce705688 JB |
4310 | { |
4311 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4312 | that uses legacy register. If it is "hi" register, don't add | |
80d61d8d | 4313 | rex and rex2 prefix. */ |
ce705688 JB |
4314 | unsigned int x; |
4315 | ||
4316 | for (x = first; x <= last; x++) | |
4317 | if (i.types[x].bitfield.class == Reg | |
4318 | && i.types[x].bitfield.byte | |
4319 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4320 | && i.op[x].regs->reg_num > 3) | |
4321 | { | |
4322 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); | |
4323 | i.rex_encoding = false; | |
80d61d8d | 4324 | i.rex2_encoding = false; |
ce705688 JB |
4325 | break; |
4326 | } | |
4327 | ||
4328 | if (i.rex_encoding) | |
4329 | i.rex = REX_OPCODE; | |
4330 | } | |
4331 | ||
192781a3 CL |
4332 | if (is_apx_rex2_encoding ()) |
4333 | { | |
4334 | build_rex2_prefix (); | |
4335 | /* The individual REX.RXBW bits got consumed. */ | |
4336 | i.rex &= REX_OPCODE; | |
4337 | } | |
4338 | else if (i.rex != 0) | |
4339 | add_prefix (REX_OPCODE | i.rex); | |
ce705688 JB |
4340 | } |
4341 | ||
65da13b5 L |
4342 | static void |
4343 | process_immext (void) | |
4344 | { | |
4345 | expressionS *exp; | |
4346 | ||
c0f3af97 | 4347 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
4348 | which is coded in the same place as an 8-bit immediate field |
4349 | would be. Here we fake an 8-bit immediate operand from the | |
4350 | opcode suffix stored in tm.extension_opcode. | |
4351 | ||
c1e679ec | 4352 | AVX instructions also use this encoding, for some of |
c0f3af97 | 4353 | 3 argument instructions. */ |
65da13b5 | 4354 | |
43234a1e | 4355 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 4356 | && (i.operands <= 2 |
7a8655d2 | 4357 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 4358 | && i.operands <= 4))); |
65da13b5 L |
4359 | |
4360 | exp = &im_expressions[i.imm_operands++]; | |
4361 | i.op[i.operands].imms = exp; | |
be1643ff | 4362 | i.types[i.operands].bitfield.imm8 = 1; |
65da13b5 L |
4363 | i.operands++; |
4364 | exp->X_op = O_constant; | |
4365 | exp->X_add_number = i.tm.extension_opcode; | |
4366 | i.tm.extension_opcode = None; | |
4367 | } | |
4368 | ||
42164a71 L |
4369 | |
4370 | static int | |
4371 | check_hle (void) | |
4372 | { | |
742732c7 | 4373 | switch (i.tm.opcode_modifier.prefixok) |
42164a71 L |
4374 | { |
4375 | default: | |
4376 | abort (); | |
742732c7 JB |
4377 | case PrefixLock: |
4378 | case PrefixNone: | |
4379 | case PrefixNoTrack: | |
4380 | case PrefixRep: | |
165de32a | 4381 | as_bad (_("invalid instruction `%s' after `%s'"), |
76d3f746 | 4382 | insn_name (&i.tm), i.hle_prefix); |
42164a71 | 4383 | return 0; |
742732c7 | 4384 | case PrefixHLELock: |
42164a71 L |
4385 | if (i.prefix[LOCK_PREFIX]) |
4386 | return 1; | |
165de32a | 4387 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4388 | return 0; |
742732c7 | 4389 | case PrefixHLEAny: |
42164a71 | 4390 | return 1; |
742732c7 | 4391 | case PrefixHLERelease: |
42164a71 L |
4392 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4393 | { | |
4394 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
76d3f746 | 4395 | insn_name (&i.tm)); |
42164a71 L |
4396 | return 0; |
4397 | } | |
8dc0818e | 4398 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4399 | { |
4400 | as_bad (_("memory destination needed for instruction `%s'" | |
76d3f746 | 4401 | " after `xrelease'"), insn_name (&i.tm)); |
42164a71 L |
4402 | return 0; |
4403 | } | |
4404 | return 1; | |
4405 | } | |
4406 | } | |
4407 | ||
c8480b58 L |
4408 | /* Encode aligned vector move as unaligned vector move. */ |
4409 | ||
4410 | static void | |
4411 | encode_with_unaligned_vector_move (void) | |
4412 | { | |
4413 | switch (i.tm.base_opcode) | |
4414 | { | |
b3a9fe6f L |
4415 | case 0x28: /* Load instructions. */ |
4416 | case 0x29: /* Store instructions. */ | |
c8480b58 | 4417 | /* movaps/movapd/vmovaps/vmovapd. */ |
ddb62495 | 4418 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 | 4419 | && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66) |
b3a9fe6f | 4420 | i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1); |
c8480b58 | 4421 | break; |
b3a9fe6f L |
4422 | case 0x6f: /* Load instructions. */ |
4423 | case 0x7f: /* Store instructions. */ | |
c8480b58 | 4424 | /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */ |
ddb62495 | 4425 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 L |
4426 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66) |
4427 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
4428 | break; | |
4429 | default: | |
4430 | break; | |
4431 | } | |
4432 | } | |
4433 | ||
b6f8c7c4 L |
4434 | /* Try the shortest encoding by shortening operand size. */ |
4435 | ||
4436 | static void | |
4437 | optimize_encoding (void) | |
4438 | { | |
a0a1771e | 4439 | unsigned int j; |
b6f8c7c4 | 4440 | |
7fc69528 | 4441 | if (i.tm.mnem_off == MN_lea) |
fe134c65 JB |
4442 | { |
4443 | /* Optimize: -O: | |
4444 | lea symbol, %rN -> mov $symbol, %rN | |
4445 | lea (%rM), %rN -> mov %rM, %rN | |
4446 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4447 | ||
4448 | and in 32-bit mode for 16-bit addressing | |
4449 | ||
4450 | lea (%rM), %rN -> movzx %rM, %rN | |
4451 | ||
4452 | and in 64-bit mode zap 32-bit addressing in favor of using a | |
4453 | 32-bit (or less) destination. | |
4454 | */ | |
4455 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4456 | { | |
4457 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4458 | i.tm.opcode_modifier.size = SIZE32; | |
4459 | i.prefix[ADDR_PREFIX] = 0; | |
4460 | } | |
4461 | ||
4462 | if (!i.index_reg && !i.base_reg) | |
4463 | { | |
4464 | /* Handle: | |
4465 | lea symbol, %rN -> mov $symbol, %rN | |
4466 | */ | |
4467 | if (flag_code == CODE_64BIT) | |
4468 | { | |
4469 | /* Don't transform a relocation to a 16-bit one. */ | |
4470 | if (i.op[0].disps | |
4471 | && i.op[0].disps->X_op != O_constant | |
4472 | && i.op[1].regs->reg_type.bitfield.word) | |
4473 | return; | |
4474 | ||
4475 | if (!i.op[1].regs->reg_type.bitfield.qword | |
4476 | || i.tm.opcode_modifier.size == SIZE32) | |
4477 | { | |
4478 | i.tm.base_opcode = 0xb8; | |
4479 | i.tm.opcode_modifier.modrm = 0; | |
4480 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4481 | i.types[0].bitfield.imm32 = 1; | |
4482 | else | |
4483 | { | |
4484 | i.tm.opcode_modifier.size = SIZE16; | |
4485 | i.types[0].bitfield.imm16 = 1; | |
4486 | } | |
4487 | } | |
4488 | else | |
4489 | { | |
4490 | /* Subject to further optimization below. */ | |
4491 | i.tm.base_opcode = 0xc7; | |
4492 | i.tm.extension_opcode = 0; | |
4493 | i.types[0].bitfield.imm32s = 1; | |
4494 | i.types[0].bitfield.baseindex = 0; | |
4495 | } | |
4496 | } | |
4497 | /* Outside of 64-bit mode address and operand sizes have to match if | |
4498 | a relocation is involved, as otherwise we wouldn't (currently) or | |
4499 | even couldn't express the relocation correctly. */ | |
4500 | else if (i.op[0].disps | |
4501 | && i.op[0].disps->X_op != O_constant | |
4502 | && ((!i.prefix[ADDR_PREFIX]) | |
4503 | != (flag_code == CODE_32BIT | |
4504 | ? i.op[1].regs->reg_type.bitfield.dword | |
4505 | : i.op[1].regs->reg_type.bitfield.word))) | |
4506 | return; | |
7772f168 JB |
4507 | /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit |
4508 | destination is going to grow encoding size. */ | |
4509 | else if (flag_code == CODE_16BIT | |
4510 | && (optimize <= 1 || optimize_for_space) | |
4511 | && !i.prefix[ADDR_PREFIX] | |
4512 | && i.op[1].regs->reg_type.bitfield.dword) | |
4513 | return; | |
fe134c65 JB |
4514 | else |
4515 | { | |
4516 | i.tm.base_opcode = 0xb8; | |
4517 | i.tm.opcode_modifier.modrm = 0; | |
4518 | if (i.op[1].regs->reg_type.bitfield.dword) | |
4519 | i.types[0].bitfield.imm32 = 1; | |
4520 | else | |
4521 | i.types[0].bitfield.imm16 = 1; | |
4522 | ||
4523 | if (i.op[0].disps | |
4524 | && i.op[0].disps->X_op == O_constant | |
4525 | && i.op[1].regs->reg_type.bitfield.dword | |
60cfa10c L |
4526 | /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence |
4527 | GCC 5. */ | |
4528 | && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT)) | |
fe134c65 JB |
4529 | i.op[0].disps->X_add_number &= 0xffff; |
4530 | } | |
4531 | ||
4532 | i.tm.operand_types[0] = i.types[0]; | |
4533 | i.imm_operands = 1; | |
4534 | if (!i.op[0].imms) | |
4535 | { | |
4536 | i.op[0].imms = &im_expressions[0]; | |
4537 | i.op[0].imms->X_op = O_absent; | |
4538 | } | |
4539 | } | |
4540 | else if (i.op[0].disps | |
4541 | && (i.op[0].disps->X_op != O_constant | |
4542 | || i.op[0].disps->X_add_number)) | |
4543 | return; | |
4544 | else | |
4545 | { | |
4546 | /* Handle: | |
4547 | lea (%rM), %rN -> mov %rM, %rN | |
4548 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4549 | lea (%rM), %rN -> movzx %rM, %rN | |
4550 | */ | |
4551 | const reg_entry *addr_reg; | |
4552 | ||
4553 | if (!i.index_reg && i.base_reg->reg_num != RegIP) | |
4554 | addr_reg = i.base_reg; | |
4555 | else if (!i.base_reg | |
4556 | && i.index_reg->reg_num != RegIZ | |
4557 | && !i.log2_scale_factor) | |
4558 | addr_reg = i.index_reg; | |
4559 | else | |
4560 | return; | |
4561 | ||
4562 | if (addr_reg->reg_type.bitfield.word | |
4563 | && i.op[1].regs->reg_type.bitfield.dword) | |
4564 | { | |
4565 | if (flag_code != CODE_32BIT) | |
4566 | return; | |
ddb62495 | 4567 | i.tm.opcode_space = SPACE_0F; |
fe134c65 JB |
4568 | i.tm.base_opcode = 0xb7; |
4569 | } | |
4570 | else | |
4571 | i.tm.base_opcode = 0x8b; | |
4572 | ||
4573 | if (addr_reg->reg_type.bitfield.dword | |
4574 | && i.op[1].regs->reg_type.bitfield.qword) | |
4575 | i.tm.opcode_modifier.size = SIZE32; | |
4576 | ||
4577 | i.op[0].regs = addr_reg; | |
4578 | i.reg_operands = 2; | |
4579 | } | |
4580 | ||
4581 | i.mem_operands = 0; | |
4582 | i.disp_operands = 0; | |
4583 | i.prefix[ADDR_PREFIX] = 0; | |
4584 | i.prefix[SEG_PREFIX] = 0; | |
4585 | i.seg[0] = NULL; | |
4586 | } | |
4587 | ||
b6f8c7c4 | 4588 | if (optimize_for_space |
7fc69528 | 4589 | && i.tm.mnem_off == MN_test |
b6f8c7c4 L |
4590 | && i.reg_operands == 1 |
4591 | && i.imm_operands == 1 | |
4592 | && !i.types[1].bitfield.byte | |
4593 | && i.op[0].imms->X_op == O_constant | |
7fc69528 | 4594 | && fits_in_imm7 (i.op[0].imms->X_add_number)) |
b6f8c7c4 L |
4595 | { |
4596 | /* Optimize: -Os: | |
4597 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4598 | */ | |
4599 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4600 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4601 | { | |
4602 | i.types[1].bitfield.byte = 1; | |
4603 | /* Ignore the suffix. */ | |
4604 | i.suffix = 0; | |
80d61d8d CL |
4605 | /* Convert to byte registers. 8-bit registers are special, |
4606 | RegRex64 and non-RegRex64 each have 8 registers. */ | |
7697afb6 | 4607 | if (i.types[1].bitfield.word) |
80d61d8d | 4608 | /* 32 (or 40) 8-bit registers. */ |
7697afb6 | 4609 | j = 32; |
80d61d8d CL |
4610 | else if (i.types[1].bitfield.dword) |
4611 | /* 32 (or 40) 8-bit registers + 32 16-bit registers. */ | |
4612 | j = 64; | |
7697afb6 | 4613 | else |
80d61d8d CL |
4614 | /* 32 (or 40) 8-bit registers + 32 16-bit registers |
4615 | + 32 32-bit registers. */ | |
4616 | j = 96; | |
4617 | ||
4618 | /* In 64-bit mode, the following byte registers cannot be accessed | |
4619 | if using the Rex and Rex2 prefix: AH, BH, CH, DH */ | |
4620 | if (!(i.op[1].regs->reg_flags & (RegRex | RegRex2)) && base_regnum < 4) | |
7697afb6 JB |
4621 | j += 8; |
4622 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4623 | } |
4624 | } | |
4625 | else if (flag_code == CODE_64BIT | |
ddb62495 | 4626 | && i.tm.opcode_space == SPACE_BASE |
d3d50934 L |
4627 | && ((i.types[1].bitfield.qword |
4628 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4629 | && i.imm_operands == 1 |
4630 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4631 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4632 | && i.tm.extension_opcode == None |
4633 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4634 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
7fc69528 | 4635 | && (i.tm.base_opcode == 0x24 |
b6f8c7c4 L |
4636 | || (i.tm.base_opcode == 0x80 |
4637 | && i.tm.extension_opcode == 0x4) | |
7fc69528 JB |
4638 | || i.tm.mnem_off == MN_test |
4639 | || ((i.tm.base_opcode | 1) == 0xc7 | |
b8364fa7 JB |
4640 | && i.tm.extension_opcode == 0x0))) |
4641 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4642 | && i.tm.base_opcode == 0x83 | |
4643 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4644 | || (i.types[0].bitfield.qword |
4645 | && ((i.reg_operands == 2 | |
4646 | && i.op[0].regs == i.op[1].regs | |
7fc69528 JB |
4647 | && (i.tm.mnem_off == MN_xor |
4648 | || i.tm.mnem_off == MN_sub)) | |
4649 | || i.tm.mnem_off == MN_clr)))) | |
b6f8c7c4 L |
4650 | { |
4651 | /* Optimize: -O: | |
4652 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4653 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4654 | testq $imm31, %r64 -> testl $imm31, %r32 |
4655 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4656 | subq %r64, %r64 -> subl %r32, %r32 | |
4657 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4658 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4659 | */ | |
04784e33 JB |
4660 | i.tm.opcode_modifier.size = SIZE32; |
4661 | if (i.imm_operands) | |
4662 | { | |
4663 | i.types[0].bitfield.imm32 = 1; | |
4664 | i.types[0].bitfield.imm32s = 0; | |
4665 | i.types[0].bitfield.imm64 = 0; | |
4666 | } | |
4667 | else | |
4668 | { | |
4669 | i.types[0].bitfield.dword = 1; | |
4670 | i.types[0].bitfield.qword = 0; | |
4671 | } | |
4672 | i.types[1].bitfield.dword = 1; | |
4673 | i.types[1].bitfield.qword = 0; | |
7fc69528 | 4674 | if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea) |
b6f8c7c4 L |
4675 | { |
4676 | /* Handle | |
4677 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4678 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4679 | */ | |
4680 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4681 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4682 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
507916b8 | 4683 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4684 | { |
4685 | /* Handle | |
4686 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4687 | */ | |
507916b8 | 4688 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4689 | i.tm.extension_opcode = None; |
507916b8 | 4690 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4691 | i.tm.opcode_modifier.modrm = 0; |
4692 | } | |
4693 | } | |
4694 | } | |
c73a37b2 JB |
4695 | else if (i.reg_operands == 3 |
4696 | && i.op[0].regs == i.op[1].regs | |
4697 | && i.encoding != encoding_evex | |
4698 | && (i.tm.mnem_off == MN_xor | |
4699 | || i.tm.mnem_off == MN_sub)) | |
4700 | { | |
4701 | /* Optimize: -O: | |
4702 | xorb %rNb, %rNb, %rMb -> xorl %rMd, %rMd | |
4703 | xorw %rNw, %rNw, %rMw -> xorl %rMd, %rMd | |
4704 | xorl %rNd, %rNd, %rMd -> xorl %rMd, %rMd | |
4705 | xorq %rN, %rN, %rM -> xorl %rMd, %rMd | |
4706 | subb %rNb, %rNb, %rMb -> subl %rMd, %rMd | |
4707 | subw %rNw, %rNw, %rMw -> subl %rMd, %rMd | |
4708 | subl %rNd, %rNd, %rMd -> subl %rMd, %rMd | |
4709 | subq %rN, %rN, %rM -> subl %rMd, %rMd | |
4710 | */ | |
4711 | i.tm.opcode_space = SPACE_BASE; | |
4712 | i.tm.opcode_modifier.evex = 0; | |
4713 | i.tm.opcode_modifier.size = SIZE32; | |
4714 | i.types[0].bitfield.byte = 0; | |
4715 | i.types[0].bitfield.word = 0; | |
4716 | i.types[0].bitfield.dword = 1; | |
4717 | i.types[0].bitfield.qword = 0; | |
4718 | i.op[0].regs = i.op[2].regs; | |
4719 | i.types[1] = i.types[0]; | |
4720 | i.op[1].regs = i.op[2].regs; | |
4721 | i.reg_operands = 2; | |
4722 | } | |
5641ec01 JB |
4723 | else if (optimize > 1 |
4724 | && !optimize_for_space | |
4725 | && i.reg_operands == 2 | |
4726 | && i.op[0].regs == i.op[1].regs | |
7fc69528 | 4727 | && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or) |
5641ec01 JB |
4728 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) |
4729 | { | |
4730 | /* Optimize: -O2: | |
4731 | andb %rN, %rN -> testb %rN, %rN | |
4732 | andw %rN, %rN -> testw %rN, %rN | |
4733 | andq %rN, %rN -> testq %rN, %rN | |
4734 | orb %rN, %rN -> testb %rN, %rN | |
4735 | orw %rN, %rN -> testw %rN, %rN | |
4736 | orq %rN, %rN -> testq %rN, %rN | |
4737 | ||
4738 | and outside of 64-bit mode | |
4739 | ||
4740 | andl %rN, %rN -> testl %rN, %rN | |
4741 | orl %rN, %rN -> testl %rN, %rN | |
4742 | */ | |
4743 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4744 | } | |
ad2f4436 JB |
4745 | else if (i.tm.base_opcode == 0xba |
4746 | && i.tm.opcode_space == SPACE_0F | |
4747 | && i.reg_operands == 1 | |
4748 | && i.op[0].imms->X_op == O_constant | |
4749 | && i.op[0].imms->X_add_number >= 0) | |
4750 | { | |
4751 | /* Optimize: -O: | |
4752 | btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16) | |
4753 | btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8) | |
4754 | btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4755 | ||
4756 | With <BT> one of bts, btr, and bts also: | |
4757 | <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16) | |
4758 | <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4759 | */ | |
4760 | switch (flag_code) | |
4761 | { | |
4762 | case CODE_64BIT: | |
4763 | if (i.tm.extension_opcode != 4) | |
4764 | break; | |
4765 | if (i.types[1].bitfield.qword | |
4766 | && i.op[0].imms->X_add_number < 32 | |
4767 | && !(i.op[1].regs->reg_flags & RegRex)) | |
4768 | i.tm.opcode_modifier.size = SIZE32; | |
4769 | /* Fall through. */ | |
4770 | case CODE_32BIT: | |
4771 | if (i.types[1].bitfield.word | |
4772 | && i.op[0].imms->X_add_number < 16) | |
4773 | i.tm.opcode_modifier.size = SIZE32; | |
4774 | break; | |
4775 | case CODE_16BIT: | |
4776 | if (i.op[0].imms->X_add_number < 16) | |
4777 | i.tm.opcode_modifier.size = SIZE16; | |
4778 | break; | |
4779 | } | |
4780 | } | |
99112332 | 4781 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4782 | && i.op[0].regs == i.op[1].regs |
4783 | && !i.types[2].bitfield.xmmword | |
4784 | && (i.tm.opcode_modifier.vex | |
6225c532 | 4785 | || ((!i.mask.reg || i.mask.zeroing) |
706ce984 | 4786 | && i.tm.opcode_modifier.evex |
e346d50a | 4787 | && (i.encoding != encoding_evex |
dd22218c | 4788 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
734dfd1c | 4789 | || is_cpu (&i.tm, CpuAVX512VL) |
7091c612 | 4790 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4791 | && i.types[2].bitfield.ymmword)))) |
ddb62495 | 4792 | && i.tm.opcode_space == SPACE_0F |
5844ccaa JB |
4793 | && ((i.tm.base_opcode | 2) == 0x57 |
4794 | || i.tm.base_opcode == 0xdf | |
4795 | || i.tm.base_opcode == 0xef | |
4796 | || (i.tm.base_opcode | 3) == 0xfb | |
4797 | || i.tm.base_opcode == 0x42 | |
4798 | || i.tm.base_opcode == 0x47)) | |
b6f8c7c4 | 4799 | { |
99112332 | 4800 | /* Optimize: -O1: |
8305403a L |
4801 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4802 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4803 | EVEX VOP %zmmM, %zmmM, %zmmN |
4804 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4805 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4806 | EVEX VOP %ymmM, %ymmM, %ymmN |
4807 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4808 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4809 | VEX VOP %ymmM, %ymmM, %ymmN |
4810 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4811 | VOP, one of vpandn and vpxor: | |
4812 | VEX VOP %ymmM, %ymmM, %ymmN | |
4813 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4814 | VOP, one of vpandnd and vpandnq: | |
4815 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4816 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4817 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4818 | EVEX VOP %ymmM, %ymmM, %ymmN |
4819 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4820 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4821 | VOP, one of vpxord and vpxorq: |
4822 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4823 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4824 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4825 | EVEX VOP %ymmM, %ymmM, %ymmN |
4826 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4827 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4828 | VOP, one of kxord and kxorq: |
4829 | VEX VOP %kM, %kM, %kN | |
4830 | -> VEX kxorw %kM, %kM, %kN | |
4831 | VOP, one of kandnd and kandnq: | |
4832 | VEX VOP %kM, %kM, %kN | |
4833 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4834 | */ |
706ce984 | 4835 | if (i.tm.opcode_modifier.evex) |
b6f8c7c4 | 4836 | { |
e346d50a | 4837 | if (i.encoding != encoding_evex) |
b6f8c7c4 L |
4838 | { |
4839 | i.tm.opcode_modifier.vex = VEX128; | |
4840 | i.tm.opcode_modifier.vexw = VEXW0; | |
4841 | i.tm.opcode_modifier.evex = 0; | |
e346d50a | 4842 | i.encoding = encoding_vex; |
a6f3add0 | 4843 | i.mask.reg = NULL; |
b6f8c7c4 | 4844 | } |
7b1d7ca1 | 4845 | else if (optimize > 1) |
dd22218c L |
4846 | i.tm.opcode_modifier.evex = EVEX128; |
4847 | else | |
4848 | return; | |
b6f8c7c4 | 4849 | } |
f74a6307 | 4850 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 | 4851 | { |
35648716 | 4852 | i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; |
1424ad86 JB |
4853 | i.tm.opcode_modifier.vexw = VEXW0; |
4854 | } | |
b6f8c7c4 L |
4855 | else |
4856 | i.tm.opcode_modifier.vex = VEX128; | |
4857 | ||
4858 | if (i.tm.opcode_modifier.vex) | |
4859 | for (j = 0; j < 3; j++) | |
4860 | { | |
4861 | i.types[j].bitfield.xmmword = 1; | |
4862 | i.types[j].bitfield.ymmword = 0; | |
4863 | } | |
4864 | } | |
e346d50a | 4865 | else if (i.encoding != encoding_evex |
eb3f3841 | 4866 | && i.encoding != encoding_egpr |
97ed31ae | 4867 | && !i.types[0].bitfield.zmmword |
392a5972 | 4868 | && !i.types[1].bitfield.zmmword |
6225c532 | 4869 | && !i.mask.reg |
9b345ce8 | 4870 | && !i.broadcast.type |
a5748e0d | 4871 | && !i.broadcast.bytes |
706ce984 | 4872 | && i.tm.opcode_modifier.evex |
35648716 JB |
4873 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4874 | || (i.tm.base_opcode & ~4) == 0xdb | |
4875 | || (i.tm.base_opcode & ~4) == 0xeb) | |
97ed31ae L |
4876 | && i.tm.extension_opcode == None) |
4877 | { | |
4878 | /* Optimize: -O1: | |
4879 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4880 | vmovdqu32 and vmovdqu64: | |
4881 | EVEX VOP %xmmM, %xmmN | |
4882 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4883 | EVEX VOP %ymmM, %ymmN | |
4884 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4885 | EVEX VOP %xmmM, mem | |
4886 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4887 | EVEX VOP %ymmM, mem | |
4888 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4889 | EVEX VOP mem, %xmmN | |
4890 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4891 | EVEX VOP mem, %ymmN | |
4892 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4893 | VOP, one of vpand, vpandn, vpor, vpxor: |
4894 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4895 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4896 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4897 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4898 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4899 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4900 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4901 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4902 | */ |
a0a1771e | 4903 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4904 | if (operand_type_check (i.types[j], disp) |
4905 | && i.op[j].disps->X_op == O_constant) | |
4906 | { | |
4907 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4908 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4909 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4910 | int evex_disp8, vex_disp8; | |
4911 | unsigned int memshift = i.memshift; | |
4912 | offsetT n = i.op[j].disps->X_add_number; | |
4913 | ||
4914 | evex_disp8 = fits_in_disp8 (n); | |
4915 | i.memshift = 0; | |
4916 | vex_disp8 = fits_in_disp8 (n); | |
4917 | if (evex_disp8 != vex_disp8) | |
4918 | { | |
4919 | i.memshift = memshift; | |
4920 | return; | |
4921 | } | |
4922 | ||
4923 | i.types[j].bitfield.disp8 = vex_disp8; | |
4924 | break; | |
4925 | } | |
35648716 JB |
4926 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4927 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2) | |
4928 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
97ed31ae L |
4929 | i.tm.opcode_modifier.vex |
4930 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4931 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 | 4932 | /* VPAND, VPOR, and VPXOR are commutative. */ |
35648716 | 4933 | if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf) |
79dec6b7 | 4934 | i.tm.opcode_modifier.commutative = 1; |
97ed31ae L |
4935 | i.tm.opcode_modifier.evex = 0; |
4936 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4937 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4938 | i.tm.opcode_modifier.disp8memshift = 0; |
4939 | i.memshift = 0; | |
a0a1771e JB |
4940 | if (j < i.operands) |
4941 | i.types[j].bitfield.disp8 | |
4942 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4943 | } |
b5c37946 SJ |
4944 | else if (optimize_for_space |
4945 | && i.tm.base_opcode == 0x29 | |
4946 | && i.tm.opcode_space == SPACE_0F38 | |
4947 | && i.operands == i.reg_operands | |
4948 | && i.op[0].regs == i.op[1].regs | |
4949 | && (!i.tm.opcode_modifier.vex | |
4950 | || !(i.op[0].regs->reg_flags & RegRex)) | |
706ce984 | 4951 | && !i.tm.opcode_modifier.evex) |
b5c37946 SJ |
4952 | { |
4953 | /* Optimize: -Os: | |
4954 | pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN | |
4955 | vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8) | |
4956 | vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8) | |
4957 | */ | |
4958 | i.tm.opcode_space = SPACE_0F; | |
4959 | i.tm.base_opcode = 0x76; | |
4960 | } | |
4961 | else if (((i.tm.base_opcode >= 0x64 | |
4962 | && i.tm.base_opcode <= 0x66 | |
4963 | && i.tm.opcode_space == SPACE_0F) | |
4964 | || (i.tm.base_opcode == 0x37 | |
4965 | && i.tm.opcode_space == SPACE_0F38)) | |
4966 | && i.operands == i.reg_operands | |
4967 | && i.op[0].regs == i.op[1].regs | |
706ce984 | 4968 | && !i.tm.opcode_modifier.evex) |
b5c37946 SJ |
4969 | { |
4970 | /* Optimize: -O: | |
4971 | pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN | |
4972 | pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN | |
4973 | vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8) | |
4974 | vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7) | |
4975 | vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8) | |
4976 | vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7) | |
4977 | */ | |
4978 | i.tm.opcode_space = SPACE_0F; | |
4979 | i.tm.base_opcode = 0xef; | |
4980 | if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex)) | |
4981 | { | |
4982 | if (i.operands == 2) | |
4983 | { | |
4984 | gas_assert (i.tm.opcode_modifier.sse2avx); | |
4985 | ||
4986 | i.operands = 3; | |
4987 | i.reg_operands = 3; | |
4988 | i.tm.operands = 3; | |
4989 | ||
4990 | i.op[2].regs = i.op[0].regs; | |
4991 | i.types[2] = i.types[0]; | |
4992 | i.flags[2] = i.flags[0]; | |
4993 | i.tm.operand_types[2] = i.tm.operand_types[0]; | |
4994 | ||
4995 | i.tm.opcode_modifier.sse2avx = 0; | |
4996 | } | |
4997 | i.op[0].regs -= i.op[0].regs->reg_num + 8; | |
4998 | i.op[1].regs = i.op[0].regs; | |
4999 | } | |
5000 | } | |
5001 | else if (optimize_for_space | |
5002 | && i.tm.base_opcode == 0x59 | |
5003 | && i.tm.opcode_space == SPACE_0F38 | |
5004 | && i.operands == i.reg_operands | |
5005 | && i.tm.opcode_modifier.vex | |
5006 | && !(i.op[0].regs->reg_flags & RegRex) | |
5007 | && i.op[0].regs->reg_type.bitfield.xmmword | |
e346d50a | 5008 | && i.encoding != encoding_vex3) |
b5c37946 SJ |
5009 | { |
5010 | /* Optimize: -Os: | |
5011 | vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8) | |
5012 | */ | |
5013 | i.tm.opcode_space = SPACE_0F; | |
5014 | i.tm.base_opcode = 0x6c; | |
5015 | i.tm.opcode_modifier.vexvvvv = 1; | |
5016 | ||
5017 | ++i.operands; | |
5018 | ++i.reg_operands; | |
5019 | ++i.tm.operands; | |
5020 | ||
5021 | i.op[2].regs = i.op[0].regs; | |
5022 | i.types[2] = i.types[0]; | |
5023 | i.flags[2] = i.flags[0]; | |
5024 | i.tm.operand_types[2] = i.tm.operand_types[0]; | |
5025 | ||
5026 | swap_2_operands (1, 2); | |
5027 | } | |
b6f8c7c4 L |
5028 | } |
5029 | ||
1e7dd4a0 JB |
5030 | static void |
5031 | s_noopt (int dummy ATTRIBUTE_UNUSED) | |
5032 | { | |
5033 | if (!is_it_end_of_statement ()) | |
5034 | as_warn (_("`.noopt' arguments ignored")); | |
5035 | ||
5036 | optimize = 0; | |
5037 | optimize_for_space = 0; | |
5038 | ||
5039 | ignore_rest_of_line (); | |
5040 | } | |
5041 | ||
ae531041 L |
5042 | /* Return non-zero for load instruction. */ |
5043 | ||
5044 | static int | |
5045 | load_insn_p (void) | |
5046 | { | |
5047 | unsigned int dest; | |
5048 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
5049 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
5050 | ||
5051 | if (!any_vex_p) | |
5052 | { | |
ef07be45 CL |
5053 | /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, |
5054 | bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ | |
255571cd | 5055 | if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE) |
ae531041 L |
5056 | return 0; |
5057 | ||
389d00a5 | 5058 | /* pop. */ |
6d86a545 | 5059 | if (i.tm.mnem_off == MN_pop) |
389d00a5 JB |
5060 | return 1; |
5061 | } | |
5062 | ||
ddb62495 | 5063 | if (i.tm.opcode_space == SPACE_BASE) |
389d00a5 JB |
5064 | { |
5065 | /* popf, popa. */ | |
5066 | if (i.tm.base_opcode == 0x9d | |
a09f656b | 5067 | || i.tm.base_opcode == 0x61) |
ae531041 L |
5068 | return 1; |
5069 | ||
5070 | /* movs, cmps, lods, scas. */ | |
5071 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
5072 | return 1; | |
5073 | ||
a09f656b | 5074 | /* outs, xlatb. */ |
5075 | if (base_opcode == 0x6f | |
5076 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 5077 | return 1; |
a09f656b | 5078 | /* NB: For AMD-specific insns with implicit memory operands, |
5079 | they're intentionally not covered. */ | |
ae531041 L |
5080 | } |
5081 | ||
5082 | /* No memory operand. */ | |
5083 | if (!i.mem_operands) | |
5084 | return 0; | |
5085 | ||
5086 | if (any_vex_p) | |
5087 | { | |
7fc69528 | 5088 | if (i.tm.mnem_off == MN_vldmxcsr) |
ae531041 L |
5089 | return 1; |
5090 | } | |
ddb62495 | 5091 | else if (i.tm.opcode_space == SPACE_BASE) |
ae531041 L |
5092 | { |
5093 | /* test, not, neg, mul, imul, div, idiv. */ | |
aa4c197d | 5094 | if (base_opcode == 0xf7 && i.tm.extension_opcode != 1) |
ae531041 L |
5095 | return 1; |
5096 | ||
5097 | /* inc, dec. */ | |
5098 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
5099 | return 1; | |
5100 | ||
5101 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
5102 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
5103 | return 1; | |
5104 | ||
ae531041 | 5105 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
aa4c197d | 5106 | if ((base_opcode == 0xc1 || (base_opcode | 2) == 0xd3) |
ae531041 L |
5107 | && i.tm.extension_opcode != 6) |
5108 | return 1; | |
5109 | ||
ae531041 | 5110 | /* Check for x87 instructions. */ |
aa4c197d | 5111 | if ((base_opcode | 6) == 0xdf) |
ae531041 L |
5112 | { |
5113 | /* Skip fst, fstp, fstenv, fstcw. */ | |
5114 | if (i.tm.base_opcode == 0xd9 | |
5115 | && (i.tm.extension_opcode == 2 | |
5116 | || i.tm.extension_opcode == 3 | |
5117 | || i.tm.extension_opcode == 6 | |
5118 | || i.tm.extension_opcode == 7)) | |
5119 | return 0; | |
5120 | ||
5121 | /* Skip fisttp, fist, fistp, fstp. */ | |
5122 | if (i.tm.base_opcode == 0xdb | |
5123 | && (i.tm.extension_opcode == 1 | |
5124 | || i.tm.extension_opcode == 2 | |
5125 | || i.tm.extension_opcode == 3 | |
5126 | || i.tm.extension_opcode == 7)) | |
5127 | return 0; | |
5128 | ||
5129 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
5130 | if (i.tm.base_opcode == 0xdd | |
5131 | && (i.tm.extension_opcode == 1 | |
5132 | || i.tm.extension_opcode == 2 | |
5133 | || i.tm.extension_opcode == 3 | |
5134 | || i.tm.extension_opcode == 6 | |
5135 | || i.tm.extension_opcode == 7)) | |
5136 | return 0; | |
5137 | ||
5138 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
5139 | if (i.tm.base_opcode == 0xdf | |
5140 | && (i.tm.extension_opcode == 1 | |
5141 | || i.tm.extension_opcode == 2 | |
5142 | || i.tm.extension_opcode == 3 | |
5143 | || i.tm.extension_opcode == 6 | |
5144 | || i.tm.extension_opcode == 7)) | |
5145 | return 0; | |
5146 | ||
5147 | return 1; | |
5148 | } | |
5149 | } | |
ddb62495 | 5150 | else if (i.tm.opcode_space == SPACE_0F) |
389d00a5 JB |
5151 | { |
5152 | /* bt, bts, btr, btc. */ | |
5153 | if (i.tm.base_opcode == 0xba | |
aa4c197d | 5154 | && (i.tm.extension_opcode | 3) == 7) |
389d00a5 JB |
5155 | return 1; |
5156 | ||
5157 | /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */ | |
5158 | if (i.tm.base_opcode == 0xc7 | |
5159 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE | |
5160 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3 | |
5161 | || i.tm.extension_opcode == 6)) | |
5162 | return 1; | |
5163 | ||
5164 | /* fxrstor, ldmxcsr, xrstor. */ | |
5165 | if (i.tm.base_opcode == 0xae | |
5166 | && (i.tm.extension_opcode == 1 | |
5167 | || i.tm.extension_opcode == 2 | |
5168 | || i.tm.extension_opcode == 5)) | |
5169 | return 1; | |
5170 | ||
5171 | /* lgdt, lidt, lmsw. */ | |
5172 | if (i.tm.base_opcode == 0x01 | |
5173 | && (i.tm.extension_opcode == 2 | |
5174 | || i.tm.extension_opcode == 3 | |
5175 | || i.tm.extension_opcode == 6)) | |
5176 | return 1; | |
5177 | } | |
ae531041 L |
5178 | |
5179 | dest = i.operands - 1; | |
5180 | ||
5181 | /* Check fake imm8 operand and 3 source operands. */ | |
5182 | if ((i.tm.opcode_modifier.immext | |
aa180741 | 5183 | || i.reg_operands + i.mem_operands == 4) |
ae531041 L |
5184 | && i.types[dest].bitfield.imm8) |
5185 | dest--; | |
5186 | ||
389d00a5 | 5187 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */ |
ddb62495 | 5188 | if (i.tm.opcode_space == SPACE_BASE |
aa4c197d | 5189 | && ((base_opcode | 0x38) == 0x39 |
389d00a5 JB |
5190 | || (base_opcode | 2) == 0x87)) |
5191 | return 1; | |
5192 | ||
7fc69528 | 5193 | if (i.tm.mnem_off == MN_xadd) |
ae531041 L |
5194 | return 1; |
5195 | ||
5196 | /* Check for load instruction. */ | |
5197 | return (i.types[dest].bitfield.class != ClassNone | |
5198 | || i.types[dest].bitfield.instance == Accum); | |
5199 | } | |
5200 | ||
5201 | /* Output lfence, 0xfaee8, after instruction. */ | |
5202 | ||
5203 | static void | |
5204 | insert_lfence_after (void) | |
5205 | { | |
5206 | if (lfence_after_load && load_insn_p ()) | |
5207 | { | |
a09f656b | 5208 | /* There are also two REP string instructions that require |
5209 | special treatment. Specifically, the compare string (CMPS) | |
5210 | and scan string (SCAS) instructions set EFLAGS in a manner | |
5211 | that depends on the data being compared/scanned. When used | |
5212 | with a REP prefix, the number of iterations may therefore | |
5213 | vary depending on this data. If the data is a program secret | |
5214 | chosen by the adversary using an LVI method, | |
5215 | then this data-dependent behavior may leak some aspect | |
5216 | of the secret. */ | |
aa4c197d | 5217 | if (((i.tm.base_opcode | 0x9) == 0xaf) |
a09f656b | 5218 | && i.prefix[REP_PREFIX]) |
5219 | { | |
5220 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
76d3f746 | 5221 | insn_name (&i.tm)); |
a09f656b | 5222 | } |
ae531041 L |
5223 | char *p = frag_more (3); |
5224 | *p++ = 0xf; | |
5225 | *p++ = 0xae; | |
5226 | *p = 0xe8; | |
5227 | } | |
5228 | } | |
5229 | ||
5230 | /* Output lfence, 0xfaee8, before instruction. */ | |
5231 | ||
5232 | static void | |
b5482fe5 | 5233 | insert_lfence_before (const struct last_insn *last_insn) |
ae531041 L |
5234 | { |
5235 | char *p; | |
5236 | ||
ddb62495 | 5237 | if (i.tm.opcode_space != SPACE_BASE) |
ae531041 L |
5238 | return; |
5239 | ||
5240 | if (i.tm.base_opcode == 0xff | |
5241 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
5242 | { | |
5243 | /* Insert lfence before indirect branch if needed. */ | |
5244 | ||
5245 | if (lfence_before_indirect_branch == lfence_branch_none) | |
5246 | return; | |
5247 | ||
5248 | if (i.operands != 1) | |
5249 | abort (); | |
5250 | ||
5251 | if (i.reg_operands == 1) | |
5252 | { | |
5253 | /* Indirect branch via register. Don't insert lfence with | |
5254 | -mlfence-after-load=yes. */ | |
5255 | if (lfence_after_load | |
5256 | || lfence_before_indirect_branch == lfence_branch_memory) | |
5257 | return; | |
5258 | } | |
5259 | else if (i.mem_operands == 1 | |
5260 | && lfence_before_indirect_branch != lfence_branch_register) | |
5261 | { | |
5262 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
76d3f746 | 5263 | insn_name (&i.tm)); |
ae531041 L |
5264 | return; |
5265 | } | |
5266 | else | |
5267 | return; | |
5268 | ||
b5482fe5 | 5269 | if (last_insn->kind != last_insn_other) |
ae531041 | 5270 | { |
b5482fe5 | 5271 | as_warn_where (last_insn->file, last_insn->line, |
ae531041 | 5272 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), |
b5482fe5 | 5273 | last_insn->name, insn_name (&i.tm)); |
ae531041 L |
5274 | return; |
5275 | } | |
5276 | ||
5277 | p = frag_more (3); | |
5278 | *p++ = 0xf; | |
5279 | *p++ = 0xae; | |
5280 | *p = 0xe8; | |
5281 | return; | |
5282 | } | |
5283 | ||
503648e4 | 5284 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 | 5285 | if (lfence_before_ret != lfence_before_ret_none |
aa4c197d | 5286 | && (i.tm.base_opcode | 1) == 0xc3) |
ae531041 | 5287 | { |
b5482fe5 | 5288 | if (last_insn->kind != last_insn_other) |
ae531041 | 5289 | { |
b5482fe5 | 5290 | as_warn_where (last_insn->file, last_insn->line, |
ae531041 | 5291 | _("`%s` skips -mlfence-before-ret on `%s`"), |
b5482fe5 | 5292 | last_insn->name, insn_name (&i.tm)); |
ae531041 L |
5293 | return; |
5294 | } | |
a09f656b | 5295 | |
a09f656b | 5296 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 5297 | char prefix = flag_code == CODE_64BIT |
5298 | ? 0x48 | |
5299 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 5300 | |
5301 | if (lfence_before_ret == lfence_before_ret_not) | |
5302 | { | |
5303 | /* not: 0xf71424, may add prefix | |
5304 | for operand size override or 64-bit code. */ | |
5305 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
5306 | if (prefix) | |
5307 | *p++ = prefix; | |
ae531041 L |
5308 | *p++ = 0xf7; |
5309 | *p++ = 0x14; | |
5310 | *p++ = 0x24; | |
a09f656b | 5311 | if (prefix) |
5312 | *p++ = prefix; | |
ae531041 L |
5313 | *p++ = 0xf7; |
5314 | *p++ = 0x14; | |
5315 | *p++ = 0x24; | |
5316 | } | |
a09f656b | 5317 | else |
5318 | { | |
5319 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
5320 | if (prefix) | |
5321 | *p++ = prefix; | |
5322 | if (lfence_before_ret == lfence_before_ret_or) | |
5323 | { | |
5324 | /* or: 0x830c2400, may add prefix | |
5325 | for operand size override or 64-bit code. */ | |
5326 | *p++ = 0x83; | |
5327 | *p++ = 0x0c; | |
5328 | } | |
5329 | else | |
5330 | { | |
5331 | /* shl: 0xc1242400, may add prefix | |
5332 | for operand size override or 64-bit code. */ | |
5333 | *p++ = 0xc1; | |
5334 | *p++ = 0x24; | |
5335 | } | |
5336 | ||
5337 | *p++ = 0x24; | |
5338 | *p++ = 0x0; | |
5339 | } | |
5340 | ||
ae531041 L |
5341 | *p++ = 0xf; |
5342 | *p++ = 0xae; | |
5343 | *p = 0xe8; | |
5344 | } | |
5345 | } | |
5346 | ||
edd67638 JB |
5347 | /* Shared helper for md_assemble() and s_insn(). */ |
5348 | static void init_globals (void) | |
5349 | { | |
5350 | unsigned int j; | |
5351 | ||
5352 | memset (&i, '\0', sizeof (i)); | |
5353 | i.rounding.type = rc_none; | |
5354 | for (j = 0; j < MAX_OPERANDS; j++) | |
5355 | i.reloc[j] = NO_RELOC; | |
5356 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
5357 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
5358 | save_stack_p = save_stack; | |
5359 | } | |
5360 | ||
04784e33 JB |
5361 | /* Helper for md_assemble() to decide whether to prepare for a possible 2nd |
5362 | parsing pass. Instead of introducing a rarely use new insn attribute this | |
5363 | utilizes a common pattern between affected templates. It is deemed | |
5364 | acceptable that this will lead to unnecessary pass 2 preparations in a | |
5365 | limited set of cases. */ | |
5366 | static INLINE bool may_need_pass2 (const insn_template *t) | |
5367 | { | |
5368 | return t->opcode_modifier.sse2avx | |
5369 | /* Note that all SSE2AVX templates have at least one operand. */ | |
a28fedbc | 5370 | ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD |
ddb62495 | 5371 | : (t->opcode_space == SPACE_0F |
a28fedbc | 5372 | && (t->base_opcode | 1) == 0xbf) |
ddb62495 | 5373 | || (t->opcode_space == SPACE_BASE |
a28fedbc | 5374 | && t->base_opcode == 0x63); |
04784e33 JB |
5375 | } |
5376 | ||
c7defc53 IB |
5377 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
5378 | ||
5379 | /* DWARF register number for EFLAGS. Used for pushf/popf insns. */ | |
5380 | #define GINSN_DW2_REGNUM_EFLAGS 49 | |
5381 | /* DWARF register number for RSI. Used as dummy value when RegIP/RegIZ. */ | |
5382 | #define GINSN_DW2_REGNUM_RSI_DUMMY 4 | |
5383 | ||
5384 | /* Identify the callee-saved registers in System V AMD64 ABI. */ | |
5385 | ||
5386 | bool | |
5387 | x86_scfi_callee_saved_p (unsigned int dw2reg_num) | |
5388 | { | |
5389 | if (dw2reg_num == 3 /* rbx. */ | |
5390 | || dw2reg_num == REG_FP /* rbp. */ | |
5391 | || dw2reg_num == REG_SP /* rsp. */ | |
5392 | || (dw2reg_num >= 12 && dw2reg_num <= 15) /* r12 - r15. */) | |
5393 | return true; | |
5394 | ||
5395 | return false; | |
5396 | } | |
5397 | ||
5398 | /* Check whether an instruction prefix which affects operation size | |
5399 | accompanies. For insns in the legacy space, setting REX.W takes precedence | |
5400 | over the operand-size prefix (66H) when both are used. | |
5401 | ||
5402 | The current users of this API are in the handlers for PUSH, POP or other | |
5403 | instructions which affect the stack pointer implicitly: the operation size | |
5404 | (16, 32, or 64 bits) determines the amount by which the stack pointer is | |
5405 | incremented / decremented (2, 4 or 8). */ | |
5406 | ||
5407 | static bool | |
5408 | ginsn_opsize_prefix_p (void) | |
5409 | { | |
5410 | return (!(i.prefix[REX_PREFIX] & REX_W) && i.prefix[DATA_PREFIX]); | |
5411 | } | |
5412 | ||
5413 | /* Get the DWARF register number for the given register entry. | |
5414 | For specific byte/word/dword register accesses like al, cl, ah, ch, r8d, | |
5415 | r20w etc., we need to identify the DWARF register number for the | |
5416 | corresponding 8-byte GPR. | |
5417 | ||
5418 | This function is a hack - it relies on relative ordering of reg entries in | |
5419 | the i386_regtab. FIXME - it will be good to allow a more direct way to get | |
5420 | this information. */ | |
5421 | ||
5422 | static unsigned int | |
5423 | ginsn_dw2_regnum (const reg_entry *ireg) | |
5424 | { | |
c7defc53 | 5425 | const reg_entry *temp = ireg; |
066673f6 | 5426 | unsigned int dwarf_reg = Dw2Inval, idx = 0; |
c7defc53 IB |
5427 | |
5428 | /* ginsn creation is available for AMD64 abi only ATM. Other flag_code | |
5429 | are not expected. */ | |
5430 | gas_assert (ireg && flag_code == CODE_64BIT); | |
5431 | ||
5432 | /* Watch out for RegIP, RegIZ. These are expected to appear only with | |
5433 | base/index addressing modes. Although creating inaccurate data | |
5434 | dependencies, using a dummy value (lets say volatile register rsi) will | |
5435 | not hurt SCFI. TBD_GINSN_GEN_NOT_SCFI. */ | |
5436 | if (ireg->reg_num == RegIP || ireg->reg_num == RegIZ) | |
5437 | return GINSN_DW2_REGNUM_RSI_DUMMY; | |
5438 | ||
fabb73d1 | 5439 | dwarf_reg = ireg->dw2_regnum[object_64bit]; |
c7defc53 IB |
5440 | |
5441 | if (dwarf_reg == Dw2Inval) | |
5442 | { | |
5443 | if (ireg <= &i386_regtab[3]) | |
5444 | /* For al, cl, dl, bl, bump over to axl, cxl, dxl, bxl respectively by | |
5445 | adding 8. */ | |
5446 | temp = ireg + 8; | |
5447 | else if (ireg <= &i386_regtab[7]) | |
5448 | /* For ah, ch, dh, bh, bump over to axl, cxl, dxl, bxl respectively by | |
5449 | adding 4. */ | |
5450 | temp = ireg + 4; | |
5451 | else | |
5452 | { | |
5453 | /* The code relies on the relative ordering of the reg entries in | |
5454 | i386_regtab. There are 32 register entries between axl-r31b, | |
5455 | ax-r31w etc. The assertions here ensures the code does not | |
5456 | recurse indefinitely. */ | |
5457 | gas_assert ((temp - &i386_regtab[0]) >= 0); | |
5458 | idx = temp - &i386_regtab[0]; | |
5459 | gas_assert (idx + 32 < i386_regtab_size - 1); | |
5460 | ||
5461 | temp = temp + 32; | |
5462 | } | |
5463 | ||
5464 | dwarf_reg = ginsn_dw2_regnum (temp); | |
5465 | } | |
5466 | ||
5467 | /* Sanity check - failure may indicate state corruption, bad ginsn or | |
5468 | perhaps the i386-reg table and the current function got out of sync. */ | |
066673f6 | 5469 | gas_assert (dwarf_reg < Dw2Inval); |
c7defc53 | 5470 | |
066673f6 | 5471 | return dwarf_reg; |
c7defc53 IB |
5472 | } |
5473 | ||
5474 | static ginsnS * | |
5475 | x86_ginsn_addsub_reg_mem (const symbolS *insn_end_sym) | |
5476 | { | |
5477 | unsigned int dw2_regnum; | |
5478 | unsigned int src1_dw2_regnum; | |
5479 | ginsnS *ginsn = NULL; | |
5480 | ginsnS * (*ginsn_func) (const symbolS *, bool, | |
5481 | enum ginsn_src_type, unsigned int, offsetT, | |
5482 | enum ginsn_src_type, unsigned int, offsetT, | |
5483 | enum ginsn_dst_type, unsigned int, offsetT); | |
5484 | uint16_t opcode = i.tm.base_opcode; | |
5485 | ||
5486 | gas_assert (i.tm.opcode_space == SPACE_BASE | |
5487 | && (opcode == 0x1 || opcode == 0x29)); | |
5488 | ginsn_func = (opcode == 0x1) ? ginsn_new_add : ginsn_new_sub; | |
5489 | ||
5490 | /* op %reg, symbol or even other cases where destination involves indirect | |
5491 | access are unnecessary for SCFI correctness. TBD_GINSN_GEN_NOT_SCFI. */ | |
5492 | if (i.mem_operands) | |
5493 | return ginsn; | |
5494 | ||
f8c50ae2 IB |
5495 | /* Skip detection of 8/16/32-bit op size; 'add/sub reg, reg/mem' ops always |
5496 | make the dest reg untraceable for SCFI. */ | |
5497 | ||
c7defc53 IB |
5498 | /* op reg, reg/mem. */ |
5499 | src1_dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
5500 | /* Of interest only when second opnd is not memory. */ | |
5501 | if (i.reg_operands == 2) | |
5502 | { | |
5503 | dw2_regnum = ginsn_dw2_regnum (i.op[1].regs); | |
5504 | ginsn = ginsn_func (insn_end_sym, true, | |
5505 | GINSN_SRC_REG, src1_dw2_regnum, 0, | |
5506 | GINSN_SRC_REG, dw2_regnum, 0, | |
5507 | GINSN_DST_REG, dw2_regnum, 0); | |
5508 | ginsn_set_where (ginsn); | |
5509 | } | |
5510 | ||
5511 | return ginsn; | |
5512 | } | |
5513 | ||
5514 | static ginsnS * | |
5515 | x86_ginsn_addsub_mem_reg (const symbolS *insn_end_sym) | |
5516 | { | |
5517 | unsigned int dw2_regnum; | |
5518 | unsigned int src1_dw2_regnum; | |
5519 | const reg_entry *mem_reg; | |
5520 | int32_t gdisp = 0; | |
5521 | ginsnS *ginsn = NULL; | |
5522 | ginsnS * (*ginsn_func) (const symbolS *, bool, | |
5523 | enum ginsn_src_type, unsigned int, offsetT, | |
5524 | enum ginsn_src_type, unsigned int, offsetT, | |
5525 | enum ginsn_dst_type, unsigned int, offsetT); | |
5526 | uint16_t opcode = i.tm.base_opcode; | |
5527 | ||
5528 | gas_assert (i.tm.opcode_space == SPACE_BASE | |
5529 | && (opcode == 0x3 || opcode == 0x2b)); | |
5530 | ginsn_func = (opcode == 0x3) ? ginsn_new_add : ginsn_new_sub; | |
5531 | ||
5532 | /* op symbol, %reg. */ | |
5533 | if (i.mem_operands && !i.base_reg && !i.index_reg) | |
5534 | return ginsn; | |
5535 | ||
f8c50ae2 IB |
5536 | /* Skip detection of 8/16/32-bit op size; 'add/sub reg/mem, reg' ops always |
5537 | make the dest reg untraceable for SCFI. */ | |
5538 | ||
c7defc53 IB |
5539 | /* op reg/mem, %reg. */ |
5540 | dw2_regnum = ginsn_dw2_regnum (i.op[1].regs); | |
5541 | ||
5542 | if (i.reg_operands == 2) | |
5543 | { | |
5544 | src1_dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
5545 | ginsn = ginsn_func (insn_end_sym, true, | |
5546 | GINSN_SRC_REG, src1_dw2_regnum, 0, | |
5547 | GINSN_SRC_REG, dw2_regnum, 0, | |
5548 | GINSN_DST_REG, dw2_regnum, 0); | |
5549 | ginsn_set_where (ginsn); | |
5550 | } | |
5551 | else if (i.mem_operands) | |
5552 | { | |
5553 | mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; | |
5554 | src1_dw2_regnum = ginsn_dw2_regnum (mem_reg); | |
5555 | if (i.disp_operands == 1) | |
5556 | gdisp = i.op[0].disps->X_add_number; | |
5557 | ginsn = ginsn_func (insn_end_sym, true, | |
5558 | GINSN_SRC_INDIRECT, src1_dw2_regnum, gdisp, | |
5559 | GINSN_SRC_REG, dw2_regnum, 0, | |
5560 | GINSN_DST_REG, dw2_regnum, 0); | |
5561 | ginsn_set_where (ginsn); | |
5562 | } | |
5563 | ||
5564 | return ginsn; | |
5565 | } | |
5566 | ||
5567 | static ginsnS * | |
5568 | x86_ginsn_alu_imm (const symbolS *insn_end_sym) | |
5569 | { | |
5570 | offsetT src_imm; | |
5571 | unsigned int dw2_regnum; | |
5572 | ginsnS *ginsn = NULL; | |
5573 | enum ginsn_src_type src_type = GINSN_SRC_REG; | |
5574 | enum ginsn_dst_type dst_type = GINSN_DST_REG; | |
5575 | ||
5576 | ginsnS * (*ginsn_func) (const symbolS *, bool, | |
5577 | enum ginsn_src_type, unsigned int, offsetT, | |
5578 | enum ginsn_src_type, unsigned int, offsetT, | |
5579 | enum ginsn_dst_type, unsigned int, offsetT); | |
5580 | ||
5581 | /* FIXME - create ginsn where dest is REG_SP / REG_FP only ? */ | |
5582 | /* Map for insn.tm.extension_opcode | |
5583 | 000 ADD 100 AND | |
5584 | 001 OR 101 SUB | |
5585 | 010 ADC 110 XOR | |
5586 | 011 SBB 111 CMP */ | |
5587 | ||
5588 | /* add/sub/and imm, %reg only at this time for SCFI. | |
5589 | Although all three ('and', 'or' , 'xor') make the destination reg | |
5590 | untraceable, 'and' op is handled but not 'or' / 'xor' because we will look | |
5591 | into supporting the DRAP pattern at some point. Other opcodes ('adc', | |
5592 | 'sbb' and 'cmp') are not generated here either. The ginsn representation | |
5593 | does not have support for the latter three opcodes; GINSN_TYPE_OTHER may | |
5594 | be added for these after x86_ginsn_unhandled () invocation if the | |
5595 | destination register is REG_SP or REG_FP. */ | |
5596 | if (i.tm.extension_opcode == 5) | |
5597 | ginsn_func = ginsn_new_sub; | |
5598 | else if (i.tm.extension_opcode == 4) | |
5599 | ginsn_func = ginsn_new_and; | |
5600 | else if (i.tm.extension_opcode == 0) | |
5601 | ginsn_func = ginsn_new_add; | |
5602 | else | |
5603 | return ginsn; | |
5604 | ||
5605 | /* TBD_GINSN_REPRESENTATION_LIMIT: There is no representation for when a | |
5606 | symbol is used as an operand, like so: | |
5607 | addq $simd_cmp_op+8, %rdx | |
5608 | Skip generating any ginsn for this. */ | |
5609 | if (i.imm_operands == 1 | |
5610 | && i.op[0].imms->X_op != O_constant) | |
5611 | return ginsn; | |
5612 | ||
5613 | /* addq $1, symbol | |
5614 | addq $1, -16(%rbp) | |
5615 | These are not of interest for SCFI. Also, TBD_GINSN_GEN_NOT_SCFI. */ | |
5616 | if (i.mem_operands == 1) | |
5617 | return ginsn; | |
5618 | ||
f8c50ae2 IB |
5619 | /* 8/16/32-bit op size makes the destination reg untraceable for SCFI. |
5620 | Deal with this via the x86_ginsn_unhandled () code path. */ | |
5621 | if (i.suffix != QWORD_MNEM_SUFFIX) | |
5622 | return ginsn; | |
5623 | ||
c7defc53 IB |
5624 | gas_assert (i.imm_operands == 1); |
5625 | src_imm = i.op[0].imms->X_add_number; | |
5626 | /* The second operand may be a register or indirect access. For SCFI, only | |
5627 | the case when the second opnd is a register is interesting. Revisit this | |
5628 | if generating ginsns for a different gen mode TBD_GINSN_GEN_NOT_SCFI. */ | |
5629 | if (i.reg_operands == 1) | |
5630 | { | |
5631 | dw2_regnum = ginsn_dw2_regnum (i.op[1].regs); | |
5632 | /* For ginsn, keep the imm as second src operand. */ | |
5633 | ginsn = ginsn_func (insn_end_sym, true, | |
5634 | src_type, dw2_regnum, 0, | |
5635 | GINSN_SRC_IMM, 0, src_imm, | |
5636 | dst_type, dw2_regnum, 0); | |
5637 | ||
5638 | ginsn_set_where (ginsn); | |
5639 | } | |
5640 | ||
5641 | return ginsn; | |
5642 | } | |
5643 | ||
5644 | /* Create ginsn(s) for MOV operations. | |
5645 | ||
5646 | The generated ginsns corresponding to mov with indirect access to memory | |
5647 | (src or dest) suffer with loss of information: when both index and base | |
5648 | registers are at play, only base register gets conveyed in ginsn. Note | |
5649 | this TBD_GINSN_GEN_NOT_SCFI. */ | |
5650 | ||
5651 | static ginsnS * | |
5652 | x86_ginsn_move (const symbolS *insn_end_sym) | |
5653 | { | |
5654 | ginsnS *ginsn = NULL; | |
5655 | unsigned int dst_reg; | |
5656 | unsigned int src_reg; | |
5657 | offsetT src_disp = 0; | |
5658 | offsetT dst_disp = 0; | |
5659 | const reg_entry *dst = NULL; | |
5660 | const reg_entry *src = NULL; | |
5661 | uint16_t opcode = i.tm.base_opcode; | |
5662 | enum ginsn_src_type src_type = GINSN_SRC_REG; | |
5663 | enum ginsn_dst_type dst_type = GINSN_DST_REG; | |
5664 | ||
5665 | /* mov %reg, symbol or mov symbol, %reg. | |
5666 | Not of interest for SCFI. Also, TBD_GINSN_GEN_NOT_SCFI. */ | |
5667 | if (i.mem_operands == 1 && !i.base_reg && !i.index_reg) | |
5668 | return ginsn; | |
5669 | ||
f8c50ae2 IB |
5670 | /* 8/16/32-bit op size makes the destination reg untraceable for SCFI. |
5671 | Handle mov reg, reg only. mov to or from a memory operand will make | |
5672 | dest reg, when present, untraceable, irrespective of the op size. */ | |
5673 | if (i.reg_operands == 2 && i.suffix != QWORD_MNEM_SUFFIX) | |
5674 | return ginsn; | |
5675 | ||
c7defc53 IB |
5676 | gas_assert (i.tm.opcode_space == SPACE_BASE); |
5677 | if (opcode == 0x8b || opcode == 0x8a) | |
5678 | { | |
5679 | /* mov disp(%reg), %reg. */ | |
5680 | if (i.mem_operands) | |
5681 | { | |
5682 | src = (i.base_reg) ? i.base_reg : i.index_reg; | |
5683 | if (i.disp_operands == 1) | |
5684 | src_disp = i.op[0].disps->X_add_number; | |
5685 | src_type = GINSN_SRC_INDIRECT; | |
5686 | } | |
5687 | else | |
5688 | src = i.op[0].regs; | |
5689 | ||
5690 | dst = i.op[1].regs; | |
5691 | } | |
5692 | else if (opcode == 0x89 || opcode == 0x88) | |
5693 | { | |
5694 | /* mov %reg, disp(%reg). */ | |
5695 | src = i.op[0].regs; | |
5696 | if (i.mem_operands) | |
5697 | { | |
5698 | dst = (i.base_reg) ? i.base_reg : i.index_reg; | |
5699 | if (i.disp_operands == 1) | |
5700 | dst_disp = i.op[1].disps->X_add_number; | |
5701 | dst_type = GINSN_DST_INDIRECT; | |
5702 | } | |
5703 | else | |
5704 | dst = i.op[1].regs; | |
5705 | } | |
5706 | ||
5707 | src_reg = ginsn_dw2_regnum (src); | |
5708 | dst_reg = ginsn_dw2_regnum (dst); | |
5709 | ||
5710 | ginsn = ginsn_new_mov (insn_end_sym, true, | |
5711 | src_type, src_reg, src_disp, | |
5712 | dst_type, dst_reg, dst_disp); | |
5713 | ginsn_set_where (ginsn); | |
5714 | ||
5715 | return ginsn; | |
5716 | } | |
5717 | ||
5718 | /* Generate appropriate ginsn for lea. | |
09812f08 IB |
5719 | |
5720 | Unhandled sub-cases (marked with TBD_GINSN_GEN_NOT_SCFI) also suffer with | |
5721 | some loss of information in the final ginsn chosen eventually (type | |
5722 | GINSN_TYPE_OTHER). But this is fine for now for GINSN_GEN_SCFI generation | |
c7defc53 IB |
5723 | mode. */ |
5724 | ||
5725 | static ginsnS * | |
5726 | x86_ginsn_lea (const symbolS *insn_end_sym) | |
5727 | { | |
5728 | offsetT src_disp = 0; | |
5729 | ginsnS *ginsn = NULL; | |
09812f08 IB |
5730 | unsigned int src1_reg; |
5731 | const reg_entry *src1; | |
c7defc53 IB |
5732 | offsetT index_scale; |
5733 | unsigned int dst_reg; | |
09812f08 | 5734 | bool index_regiz_p; |
c7defc53 | 5735 | |
03fa0c63 | 5736 | if ((!i.base_reg) != (!i.index_reg || i.index_reg->reg_num == RegIZ)) |
c7defc53 | 5737 | { |
09812f08 IB |
5738 | /* lea disp(%base), %dst or lea disp(,%index,imm), %dst. |
5739 | Either index_reg or base_reg exists, but not both. Further, as per | |
5740 | above, the case when just %index exists but is equal to RegIZ is | |
5741 | excluded. If not excluded, a GINSN_TYPE_MOV of %rsi | |
5742 | (GINSN_DW2_REGNUM_RSI_DUMMY) to %dst will be generated by this block. | |
5743 | Such a mov ginsn is imprecise; so, exclude now and generate | |
5744 | GINSN_TYPE_OTHER instead later via the x86_ginsn_unhandled (). | |
5745 | Excluding other cases is required due to | |
5746 | TBD_GINSN_REPRESENTATION_LIMIT. */ | |
c7defc53 | 5747 | |
c7defc53 | 5748 | index_scale = i.log2_scale_factor; |
09812f08 IB |
5749 | index_regiz_p = i.index_reg && i.index_reg->reg_num == RegIZ; |
5750 | src1 = i.base_reg ? i.base_reg : i.index_reg; | |
5751 | src1_reg = ginsn_dw2_regnum (src1); | |
c7defc53 | 5752 | dst_reg = ginsn_dw2_regnum (i.op[1].regs); |
09812f08 IB |
5753 | /* It makes sense to represent a scale factor of 1 precisely here |
5754 | (i.e., not using GINSN_TYPE_OTHER, but rather similar to the | |
5755 | base-without-index case). A non-zero scale factor is still OK if | |
5756 | the index reg is zero reg. | |
5757 | However, skip from here the case when disp has a symbol instead. | |
5758 | TBD_GINSN_REPRESENTATION_LIMIT. */ | |
5759 | if ((!index_scale || index_regiz_p) | |
5760 | && (!i.disp_operands || i.op[0].disps->X_op == O_constant)) | |
5761 | { | |
5762 | if (i.disp_operands) | |
5763 | src_disp = i.op[0].disps->X_add_number; | |
c7defc53 | 5764 | |
09812f08 IB |
5765 | if (src_disp) |
5766 | /* Generate an ADD ginsn. */ | |
5767 | ginsn = ginsn_new_add (insn_end_sym, true, | |
5768 | GINSN_SRC_REG, src1_reg, 0, | |
5769 | GINSN_SRC_IMM, 0, src_disp, | |
5770 | GINSN_DST_REG, dst_reg, 0); | |
5771 | else | |
5772 | /* Generate a MOV ginsn. */ | |
5773 | ginsn = ginsn_new_mov (insn_end_sym, true, | |
5774 | GINSN_SRC_REG, src1_reg, 0, | |
5775 | GINSN_DST_REG, dst_reg, 0); | |
5776 | ||
5777 | ginsn_set_where (ginsn); | |
5778 | } | |
5779 | } | |
5780 | /* Skip handling other cases here, | |
5781 | - when (i.index_reg && i.base_reg) is true, | |
5782 | e.g., lea disp(%base,%index,imm), %dst | |
5783 | We do not have a ginsn representation for multiply. | |
5784 | - or, when (!i.index_reg && !i.base_reg) is true, | |
5785 | e.g., lea symbol, %dst | |
5786 | Not a frequent pattern. If %dst is a register of interest, the user is | |
5787 | likely to use a MOV op anyway. | |
5788 | Deal with these via the x86_ginsn_unhandled () code path to generate | |
5789 | GINSN_TYPE_OTHER when necessary. TBD_GINSN_GEN_NOT_SCFI. */ | |
c7defc53 IB |
5790 | |
5791 | return ginsn; | |
5792 | } | |
5793 | ||
5794 | static ginsnS * | |
5795 | x86_ginsn_jump (const symbolS *insn_end_sym, bool cond_p) | |
5796 | { | |
5797 | ginsnS *ginsn = NULL; | |
5798 | const symbolS *src_symbol; | |
5799 | ginsnS * (*ginsn_func) (const symbolS *sym, bool real_p, | |
5800 | enum ginsn_src_type src_type, unsigned int src_reg, | |
5801 | const symbolS *src_ginsn_sym); | |
5802 | ||
5803 | gas_assert (i.disp_operands == 1); | |
5804 | ||
5805 | ginsn_func = cond_p ? ginsn_new_jump_cond : ginsn_new_jump; | |
5806 | if (i.op[0].disps->X_op == O_symbol && !i.op[0].disps->X_add_number) | |
5807 | { | |
5808 | src_symbol = i.op[0].disps->X_add_symbol; | |
5809 | ginsn = ginsn_func (insn_end_sym, true, | |
5810 | GINSN_SRC_SYMBOL, 0, src_symbol); | |
5811 | ||
5812 | ginsn_set_where (ginsn); | |
5813 | } | |
5814 | else | |
5815 | { | |
5816 | /* A non-zero addend in jump/JCC target makes control-flow tracking | |
5817 | difficult. Skip SCFI for now. */ | |
5818 | as_bad (_("SCFI: `%s' insn with non-zero addend to sym not supported"), | |
5819 | cond_p ? "JCC" : "jmp"); | |
5820 | return ginsn; | |
5821 | } | |
5822 | ||
5823 | return ginsn; | |
5824 | } | |
5825 | ||
5826 | static ginsnS * | |
5827 | x86_ginsn_enter (const symbolS *insn_end_sym) | |
5828 | { | |
5829 | ginsnS *ginsn = NULL; | |
5830 | ginsnS *ginsn_next = NULL; | |
5831 | ginsnS *ginsn_last = NULL; | |
5832 | /* In 64-bit mode, the default stack update size is 8 bytes. */ | |
5833 | int stack_opnd_size = 8; | |
5834 | ||
5835 | gas_assert (i.imm_operands == 2); | |
5836 | ||
5837 | /* For non-zero size operands, bail out as untraceable for SCFI. */ | |
5838 | if (i.op[0].imms->X_op != O_constant || i.op[0].imms->X_add_symbol != 0 | |
5839 | || i.op[1].imms->X_op != O_constant || i.op[1].imms->X_add_symbol != 0) | |
5840 | { | |
5841 | as_bad ("SCFI: enter insn with non-zero operand not supported"); | |
5842 | return ginsn; | |
5843 | } | |
5844 | ||
5845 | /* Check if this is a 16-bit op. */ | |
5846 | if (ginsn_opsize_prefix_p ()) | |
5847 | stack_opnd_size = 2; | |
5848 | ||
5849 | /* If the nesting level is 0, the processor pushes the frame pointer from | |
5850 | the BP/EBP/RBP register onto the stack, copies the current stack | |
5851 | pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and | |
5852 | loads the SP/ESP/RSP register with the current stack-pointer value | |
5853 | minus the value in the size operand. */ | |
5854 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
5855 | GINSN_SRC_REG, REG_SP, 0, | |
5856 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
5857 | GINSN_DST_REG, REG_SP, 0); | |
5858 | ginsn_set_where (ginsn); | |
5859 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
5860 | GINSN_SRC_REG, REG_FP, | |
5861 | GINSN_DST_INDIRECT, REG_SP, 0); | |
5862 | ginsn_set_where (ginsn_next); | |
5863 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
5864 | ginsn_last = ginsn_new_mov (insn_end_sym, false, | |
5865 | GINSN_SRC_REG, REG_SP, 0, | |
5866 | GINSN_DST_REG, REG_FP, 0); | |
5867 | ginsn_set_where (ginsn_last); | |
5868 | gas_assert (!ginsn_link_next (ginsn_next, ginsn_last)); | |
5869 | ||
5870 | return ginsn; | |
5871 | } | |
5872 | ||
5873 | static ginsnS * | |
5874 | x86_ginsn_leave (const symbolS *insn_end_sym) | |
5875 | { | |
5876 | ginsnS *ginsn = NULL; | |
5877 | ginsnS *ginsn_next = NULL; | |
5878 | ginsnS *ginsn_last = NULL; | |
5879 | /* In 64-bit mode, the default stack update size is 8 bytes. */ | |
5880 | int stack_opnd_size = 8; | |
5881 | ||
5882 | /* Check if this is a 16-bit op. */ | |
5883 | if (ginsn_opsize_prefix_p ()) | |
5884 | stack_opnd_size = 2; | |
5885 | ||
5886 | /* The 'leave' instruction copies the contents of the RBP register | |
5887 | into the RSP register to release all stack space allocated to the | |
5888 | procedure. */ | |
5889 | ginsn = ginsn_new_mov (insn_end_sym, false, | |
5890 | GINSN_SRC_REG, REG_FP, 0, | |
5891 | GINSN_DST_REG, REG_SP, 0); | |
5892 | ginsn_set_where (ginsn); | |
5893 | /* Then it restores the old value of the RBP register from the stack. */ | |
5894 | ginsn_next = ginsn_new_load (insn_end_sym, false, | |
5895 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
5896 | GINSN_DST_REG, REG_FP); | |
5897 | ginsn_set_where (ginsn_next); | |
5898 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
5899 | ginsn_last = ginsn_new_add (insn_end_sym, false, | |
5900 | GINSN_SRC_REG, REG_SP, 0, | |
5901 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
5902 | GINSN_DST_REG, REG_SP, 0); | |
5903 | ginsn_set_where (ginsn_next); | |
5904 | gas_assert (!ginsn_link_next (ginsn_next, ginsn_last)); | |
5905 | ||
5906 | return ginsn; | |
5907 | } | |
5908 | ||
5909 | /* Check if an instruction is whitelisted. | |
5910 | ||
5911 | Some instructions may appear with REG_SP or REG_FP as destination, because | |
5912 | which they are deemed 'interesting' for SCFI. Whitelist them here if they | |
5913 | do not affect SCFI correctness. */ | |
5914 | ||
5915 | static bool | |
5916 | x86_ginsn_safe_to_skip_p (void) | |
5917 | { | |
5918 | bool skip_p = false; | |
5919 | uint16_t opcode = i.tm.base_opcode; | |
5920 | ||
5921 | switch (opcode) | |
5922 | { | |
5923 | case 0x80: | |
5924 | case 0x81: | |
5925 | case 0x83: | |
5926 | if (i.tm.opcode_space != SPACE_BASE) | |
5927 | break; | |
5928 | /* cmp imm, reg/rem. */ | |
5929 | if (i.tm.extension_opcode == 7) | |
5930 | skip_p = true; | |
5931 | break; | |
5932 | ||
5933 | case 0x38: | |
5934 | case 0x39: | |
5935 | case 0x3a: | |
5936 | case 0x3b: | |
5937 | if (i.tm.opcode_space != SPACE_BASE) | |
5938 | break; | |
5939 | /* cmp imm/reg/mem, reg/rem. */ | |
5940 | skip_p = true; | |
5941 | break; | |
5942 | ||
5943 | case 0xf6: | |
5944 | case 0xf7: | |
5945 | case 0x84: | |
5946 | case 0x85: | |
5947 | /* test imm/reg/mem, reg/mem. */ | |
5948 | if (i.tm.opcode_space != SPACE_BASE) | |
5949 | break; | |
5950 | skip_p = true; | |
5951 | break; | |
5952 | ||
5953 | default: | |
5954 | break; | |
5955 | } | |
5956 | ||
5957 | return skip_p; | |
5958 | } | |
5959 | ||
5960 | #define X86_GINSN_UNHANDLED_NONE 0 | |
5961 | #define X86_GINSN_UNHANDLED_DEST_REG 1 | |
5962 | #define X86_GINSN_UNHANDLED_CFG 2 | |
5963 | #define X86_GINSN_UNHANDLED_STACKOP 3 | |
5964 | #define X86_GINSN_UNHANDLED_UNEXPECTED 4 | |
5965 | ||
5966 | /* Check the input insn for its impact on the correctness of the synthesized | |
5967 | CFI. Returns an error code to the caller. */ | |
5968 | ||
5969 | static int | |
5970 | x86_ginsn_unhandled (void) | |
5971 | { | |
5972 | int err = X86_GINSN_UNHANDLED_NONE; | |
5973 | const reg_entry *reg_op; | |
5974 | unsigned int dw2_regnum; | |
5975 | ||
5976 | /* Keep an eye out for instructions affecting control flow. */ | |
5977 | if (i.tm.opcode_modifier.jump) | |
5978 | err = X86_GINSN_UNHANDLED_CFG; | |
5979 | /* Also, for any instructions involving an implicit update to the stack | |
5980 | pointer. */ | |
5981 | else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_STACK_OP) | |
5982 | err = X86_GINSN_UNHANDLED_STACKOP; | |
5983 | /* Finally, also check if the missed instructions are affecting REG_SP or | |
5984 | REG_FP. The destination operand is the last at all stages of assembly | |
5985 | (due to following AT&T syntax layout in the internal representation). In | |
5986 | case of Intel syntax input, this still remains true as swap_operands () | |
5987 | is done by now. | |
5988 | PS: These checks do not involve index / base reg, as indirect memory | |
5989 | accesses via REG_SP or REG_FP do not affect SCFI correctness. | |
5990 | (Also note these instructions are candidates for other ginsn generation | |
5991 | modes in future. TBD_GINSN_GEN_NOT_SCFI.) */ | |
5992 | else if (i.operands && i.reg_operands | |
5993 | && !(i.flags[i.operands - 1] & Operand_Mem)) | |
5994 | { | |
5995 | reg_op = i.op[i.operands - 1].regs; | |
5996 | if (reg_op) | |
5997 | { | |
5998 | dw2_regnum = ginsn_dw2_regnum (reg_op); | |
5999 | if (dw2_regnum == REG_SP || dw2_regnum == REG_FP) | |
6000 | err = X86_GINSN_UNHANDLED_DEST_REG; | |
6001 | } | |
6002 | else | |
6003 | /* Something unexpected. Indicate to caller. */ | |
6004 | err = X86_GINSN_UNHANDLED_UNEXPECTED; | |
6005 | } | |
6006 | ||
6007 | return err; | |
6008 | } | |
6009 | ||
6010 | /* Generate one or more generic GAS instructions, a.k.a, ginsns for the current | |
6011 | machine instruction. | |
6012 | ||
6013 | Returns the head of linked list of ginsn(s) added, if success; Returns NULL | |
6014 | if failure. | |
6015 | ||
6016 | The input ginsn_gen_mode GMODE determines the set of minimal necessary | |
6017 | ginsns necessary for correctness of any passes applicable for that mode. | |
6018 | For supporting the GINSN_GEN_SCFI generation mode, following is the list of | |
6019 | machine instructions that must be translated into the corresponding ginsns | |
6020 | to ensure correctness of SCFI: | |
6021 | - All instructions affecting the two registers that could potentially | |
6022 | be used as the base register for CFA tracking. For SCFI, the base | |
6023 | register for CFA tracking is limited to REG_SP and REG_FP only for | |
6024 | now. | |
6025 | - All change of flow instructions: conditional and unconditional branches, | |
6026 | call and return from functions. | |
6027 | - All instructions that can potentially be a register save / restore | |
6028 | operation. | |
6029 | - All instructions that perform stack manipulation implicitly: the CALL, | |
6030 | RET, PUSH, POP, ENTER, and LEAVE instructions. | |
6031 | ||
6032 | The function currently supports GINSN_GEN_SCFI ginsn generation mode only. | |
6033 | To support other generation modes will require work on this target-specific | |
6034 | process of creation of ginsns: | |
6035 | - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as | |
6036 | possible starting points. | |
6037 | - Also note that ginsn representation may need enhancements. Specifically, | |
6038 | note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers. | |
6039 | */ | |
6040 | ||
6041 | static ginsnS * | |
6042 | x86_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode) | |
6043 | { | |
6044 | int err = 0; | |
6045 | uint16_t opcode; | |
6046 | unsigned int dw2_regnum; | |
6047 | const reg_entry *mem_reg; | |
6048 | ginsnS *ginsn = NULL; | |
6049 | ginsnS *ginsn_next = NULL; | |
6050 | /* In 64-bit mode, the default stack update size is 8 bytes. */ | |
6051 | int stack_opnd_size = 8; | |
6052 | ||
6053 | /* Currently supports generation of selected ginsns, sufficient for | |
6054 | the use-case of SCFI only. */ | |
6055 | if (gmode != GINSN_GEN_SCFI) | |
6056 | return ginsn; | |
6057 | ||
6058 | opcode = i.tm.base_opcode; | |
6059 | ||
6060 | /* Until it is clear how to handle APX NDD and other new opcodes, disallow | |
6061 | them from SCFI. */ | |
6062 | if (is_apx_rex2_encoding () | |
6063 | || (i.tm.opcode_modifier.evex && is_apx_evex_encoding ())) | |
6064 | { | |
6065 | as_bad (_("SCFI: unsupported APX op %#x may cause incorrect CFI"), | |
6066 | opcode); | |
6067 | return ginsn; | |
6068 | } | |
6069 | ||
6070 | switch (opcode) | |
6071 | { | |
f8c50ae2 IB |
6072 | |
6073 | /* Add opcodes 0x0/0x2 and sub opcodes 0x28/0x2a (with opcode_space | |
6074 | SPACE_BASE) are 8-bit ops. While they are relevant for SCFI | |
6075 | correctness, skip handling them here and use the x86_ginsn_unhandled | |
6076 | code path to generate GINSN_TYPE_OTHER when necessary. */ | |
6077 | ||
c7defc53 IB |
6078 | case 0x1: /* add reg, reg/mem. */ |
6079 | case 0x29: /* sub reg, reg/mem. */ | |
6080 | if (i.tm.opcode_space != SPACE_BASE) | |
6081 | break; | |
6082 | ginsn = x86_ginsn_addsub_reg_mem (insn_end_sym); | |
6083 | break; | |
6084 | ||
6085 | case 0x3: /* add reg/mem, reg. */ | |
6086 | case 0x2b: /* sub reg/mem, reg. */ | |
6087 | if (i.tm.opcode_space != SPACE_BASE) | |
6088 | break; | |
6089 | ginsn = x86_ginsn_addsub_mem_reg (insn_end_sym); | |
6090 | break; | |
6091 | ||
6092 | case 0xa0: /* push fs. */ | |
6093 | case 0xa8: /* push gs. */ | |
6094 | /* push fs / push gs have opcode_space == SPACE_0F. */ | |
6095 | if (i.tm.opcode_space != SPACE_0F) | |
6096 | break; | |
6097 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6098 | /* Check if operation size is 16-bit. */ | |
6099 | if (ginsn_opsize_prefix_p ()) | |
6100 | stack_opnd_size = 2; | |
6101 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6102 | GINSN_SRC_REG, REG_SP, 0, | |
6103 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6104 | GINSN_DST_REG, REG_SP, 0); | |
6105 | ginsn_set_where (ginsn); | |
6106 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6107 | GINSN_SRC_REG, dw2_regnum, | |
6108 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6109 | ginsn_set_where (ginsn_next); | |
6110 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6111 | break; | |
6112 | ||
6113 | case 0xa1: /* pop fs. */ | |
6114 | case 0xa9: /* pop gs. */ | |
6115 | /* pop fs / pop gs have opcode_space == SPACE_0F. */ | |
6116 | if (i.tm.opcode_space != SPACE_0F) | |
6117 | break; | |
6118 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6119 | /* Check if operation size is 16-bit. */ | |
6120 | if (ginsn_opsize_prefix_p ()) | |
6121 | stack_opnd_size = 2; | |
6122 | ginsn = ginsn_new_load (insn_end_sym, false, | |
6123 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
6124 | GINSN_DST_REG, dw2_regnum); | |
6125 | ginsn_set_where (ginsn); | |
6126 | ginsn_next = ginsn_new_add (insn_end_sym, false, | |
6127 | GINSN_SRC_REG, REG_SP, 0, | |
6128 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6129 | GINSN_DST_REG, REG_SP, 0); | |
6130 | ginsn_set_where (ginsn_next); | |
6131 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6132 | break; | |
6133 | ||
6134 | case 0x50 ... 0x57: | |
6135 | if (i.tm.opcode_space != SPACE_BASE) | |
6136 | break; | |
6137 | /* push reg. */ | |
6138 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6139 | /* Check if operation size is 16-bit. */ | |
6140 | if (ginsn_opsize_prefix_p ()) | |
6141 | stack_opnd_size = 2; | |
6142 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6143 | GINSN_SRC_REG, REG_SP, 0, | |
6144 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6145 | GINSN_DST_REG, REG_SP, 0); | |
6146 | ginsn_set_where (ginsn); | |
6147 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6148 | GINSN_SRC_REG, dw2_regnum, | |
6149 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6150 | ginsn_set_where (ginsn_next); | |
6151 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6152 | break; | |
6153 | ||
6154 | case 0x58 ... 0x5f: | |
6155 | if (i.tm.opcode_space != SPACE_BASE) | |
6156 | break; | |
6157 | /* pop reg. */ | |
6158 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6159 | ginsn = ginsn_new_load (insn_end_sym, false, | |
6160 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
6161 | GINSN_DST_REG, dw2_regnum); | |
6162 | ginsn_set_where (ginsn); | |
6163 | /* Check if operation size is 16-bit. */ | |
6164 | if (ginsn_opsize_prefix_p ()) | |
6165 | stack_opnd_size = 2; | |
6166 | ginsn_next = ginsn_new_add (insn_end_sym, false, | |
6167 | GINSN_SRC_REG, REG_SP, 0, | |
6168 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6169 | GINSN_DST_REG, REG_SP, 0); | |
6170 | ginsn_set_where (ginsn_next); | |
6171 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6172 | break; | |
6173 | ||
6174 | case 0x6a: /* push imm8. */ | |
6175 | case 0x68: /* push imm16/imm32. */ | |
6176 | if (i.tm.opcode_space != SPACE_BASE) | |
6177 | break; | |
6178 | /* Check if operation size is 16-bit. */ | |
6179 | if (ginsn_opsize_prefix_p ()) | |
6180 | stack_opnd_size = 2; | |
6181 | /* Skip getting the value of imm from machine instruction | |
6182 | because this is not important for SCFI. */ | |
6183 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6184 | GINSN_SRC_REG, REG_SP, 0, | |
6185 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6186 | GINSN_DST_REG, REG_SP, 0); | |
6187 | ginsn_set_where (ginsn); | |
6188 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6189 | GINSN_SRC_IMM, 0, | |
6190 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6191 | ginsn_set_where (ginsn_next); | |
6192 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6193 | break; | |
6194 | ||
6195 | /* PS: Opcodes 0x80 ... 0x8f with opcode_space SPACE_0F are present | |
6196 | only after relaxation. They do not need to be handled for ginsn | |
6197 | creation. */ | |
6198 | case 0x70 ... 0x7f: | |
6199 | if (i.tm.opcode_space != SPACE_BASE) | |
6200 | break; | |
6201 | ginsn = x86_ginsn_jump (insn_end_sym, true); | |
6202 | break; | |
6203 | ||
6204 | case 0x80: | |
6205 | case 0x81: | |
6206 | case 0x83: | |
6207 | if (i.tm.opcode_space != SPACE_BASE) | |
6208 | break; | |
6209 | ginsn = x86_ginsn_alu_imm (insn_end_sym); | |
6210 | break; | |
6211 | ||
6212 | case 0x8a: /* mov r/m8, r8. */ | |
6213 | case 0x8b: /* mov r/m(16/32/64), r(16/32/64). */ | |
6214 | case 0x88: /* mov r8, r/m8. */ | |
6215 | case 0x89: /* mov r(16/32/64), r/m(16/32/64). */ | |
6216 | if (i.tm.opcode_space != SPACE_BASE) | |
6217 | break; | |
6218 | ginsn = x86_ginsn_move (insn_end_sym); | |
6219 | break; | |
6220 | ||
6221 | case 0x8d: | |
6222 | if (i.tm.opcode_space != SPACE_BASE) | |
6223 | break; | |
09812f08 | 6224 | /* lea disp(%base,%index,imm), %dst. */ |
c7defc53 IB |
6225 | ginsn = x86_ginsn_lea (insn_end_sym); |
6226 | break; | |
6227 | ||
6228 | case 0x8f: | |
6229 | if (i.tm.opcode_space != SPACE_BASE) | |
6230 | break; | |
6231 | /* pop to reg/mem. */ | |
6232 | if (i.mem_operands) | |
6233 | { | |
6234 | mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; | |
6235 | /* Use dummy register if no base or index. Unlike other opcodes, | |
6236 | ginsns must be generated as this affect stack pointer. */ | |
6237 | dw2_regnum = (mem_reg | |
6238 | ? ginsn_dw2_regnum (mem_reg) | |
6239 | : GINSN_DW2_REGNUM_RSI_DUMMY); | |
6240 | } | |
6241 | else | |
6242 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6243 | ginsn = ginsn_new_load (insn_end_sym, false, | |
6244 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
6245 | GINSN_DST_INDIRECT, dw2_regnum); | |
6246 | ginsn_set_where (ginsn); | |
6247 | /* Check if operation size is 16-bit. */ | |
6248 | if (ginsn_opsize_prefix_p ()) | |
6249 | stack_opnd_size = 2; | |
6250 | ginsn_next = ginsn_new_add (insn_end_sym, false, | |
6251 | GINSN_SRC_REG, REG_SP, 0, | |
6252 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6253 | GINSN_DST_REG, REG_SP, 0); | |
6254 | ginsn_set_where (ginsn_next); | |
6255 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6256 | break; | |
6257 | ||
6258 | case 0x9c: | |
6259 | if (i.tm.opcode_space != SPACE_BASE) | |
6260 | break; | |
6261 | /* pushf / pushfq. */ | |
6262 | /* Check if operation size is 16-bit. */ | |
6263 | if (ginsn_opsize_prefix_p ()) | |
6264 | stack_opnd_size = 2; | |
6265 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6266 | GINSN_SRC_REG, REG_SP, 0, | |
6267 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6268 | GINSN_DST_REG, REG_SP, 0); | |
6269 | ginsn_set_where (ginsn); | |
6270 | /* FIXME - hardcode the actual DWARF reg number value. As for SCFI | |
6271 | correctness, although this behaves simply a placeholder value; its | |
6272 | just clearer if the value is correct. */ | |
6273 | dw2_regnum = GINSN_DW2_REGNUM_EFLAGS; | |
6274 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6275 | GINSN_SRC_REG, dw2_regnum, | |
6276 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6277 | ginsn_set_where (ginsn_next); | |
6278 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6279 | break; | |
6280 | ||
6281 | case 0x9d: | |
6282 | if (i.tm.opcode_space != SPACE_BASE) | |
6283 | break; | |
6284 | /* popf / popfq. */ | |
6285 | /* Check if operation size is 16-bit. */ | |
6286 | if (ginsn_opsize_prefix_p ()) | |
6287 | stack_opnd_size = 2; | |
6288 | /* FIXME - hardcode the actual DWARF reg number value. As for SCFI | |
6289 | correctness, although this behaves simply a placeholder value; its | |
6290 | just clearer if the value is correct. */ | |
6291 | dw2_regnum = GINSN_DW2_REGNUM_EFLAGS; | |
6292 | ginsn = ginsn_new_load (insn_end_sym, false, | |
6293 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
6294 | GINSN_DST_REG, dw2_regnum); | |
6295 | ginsn_set_where (ginsn); | |
6296 | ginsn_next = ginsn_new_add (insn_end_sym, false, | |
6297 | GINSN_SRC_REG, REG_SP, 0, | |
6298 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6299 | GINSN_DST_REG, REG_SP, 0); | |
6300 | ginsn_set_where (ginsn_next); | |
6301 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6302 | break; | |
6303 | ||
6304 | case 0xff: | |
6305 | if (i.tm.opcode_space != SPACE_BASE) | |
6306 | break; | |
6307 | /* push from reg/mem. */ | |
6308 | if (i.tm.extension_opcode == 6) | |
6309 | { | |
6310 | /* Check if operation size is 16-bit. */ | |
6311 | if (ginsn_opsize_prefix_p ()) | |
6312 | stack_opnd_size = 2; | |
6313 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6314 | GINSN_SRC_REG, REG_SP, 0, | |
6315 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6316 | GINSN_DST_REG, REG_SP, 0); | |
6317 | ginsn_set_where (ginsn); | |
6318 | if (i.mem_operands) | |
6319 | { | |
6320 | mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; | |
6321 | /* Use dummy register if no base or index. Unlike other opcodes, | |
6322 | ginsns must be generated as this affect stack pointer. */ | |
6323 | dw2_regnum = (mem_reg | |
6324 | ? ginsn_dw2_regnum (mem_reg) | |
6325 | : GINSN_DW2_REGNUM_RSI_DUMMY); | |
6326 | } | |
6327 | else | |
6328 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6329 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6330 | GINSN_SRC_INDIRECT, dw2_regnum, | |
6331 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6332 | ginsn_set_where (ginsn_next); | |
6333 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6334 | } | |
6335 | else if (i.tm.extension_opcode == 4) | |
6336 | { | |
6337 | /* jmp r/m. E.g., notrack jmp *%rax. */ | |
6338 | if (i.reg_operands) | |
6339 | { | |
6340 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6341 | ginsn = ginsn_new_jump (insn_end_sym, true, | |
6342 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6343 | ginsn_set_where (ginsn); | |
6344 | } | |
6345 | else if (i.mem_operands && i.index_reg) | |
6346 | { | |
6347 | /* jmp *0x0(,%rax,8). */ | |
6348 | dw2_regnum = ginsn_dw2_regnum (i.index_reg); | |
6349 | ginsn = ginsn_new_jump (insn_end_sym, true, | |
6350 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6351 | ginsn_set_where (ginsn); | |
6352 | } | |
6353 | else if (i.mem_operands && i.base_reg) | |
6354 | { | |
6355 | dw2_regnum = ginsn_dw2_regnum (i.base_reg); | |
6356 | ginsn = ginsn_new_jump (insn_end_sym, true, | |
6357 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6358 | ginsn_set_where (ginsn); | |
6359 | } | |
6360 | } | |
6361 | else if (i.tm.extension_opcode == 2) | |
6362 | { | |
6363 | /* 0xFF /2 (call). */ | |
6364 | if (i.reg_operands) | |
6365 | { | |
6366 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6367 | ginsn = ginsn_new_call (insn_end_sym, true, | |
6368 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6369 | ginsn_set_where (ginsn); | |
6370 | } | |
6371 | else if (i.mem_operands && i.base_reg) | |
6372 | { | |
6373 | dw2_regnum = ginsn_dw2_regnum (i.base_reg); | |
6374 | ginsn = ginsn_new_call (insn_end_sym, true, | |
6375 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6376 | ginsn_set_where (ginsn); | |
6377 | } | |
6378 | } | |
6379 | break; | |
6380 | ||
6381 | case 0xc2: /* ret imm16. */ | |
6382 | case 0xc3: /* ret. */ | |
6383 | if (i.tm.opcode_space != SPACE_BASE) | |
6384 | break; | |
6385 | /* Near ret. */ | |
6386 | ginsn = ginsn_new_return (insn_end_sym, true); | |
6387 | ginsn_set_where (ginsn); | |
6388 | break; | |
6389 | ||
6390 | case 0xc8: | |
6391 | if (i.tm.opcode_space != SPACE_BASE) | |
6392 | break; | |
6393 | /* enter. */ | |
6394 | ginsn = x86_ginsn_enter (insn_end_sym); | |
6395 | break; | |
6396 | ||
6397 | case 0xc9: | |
6398 | if (i.tm.opcode_space != SPACE_BASE) | |
6399 | break; | |
6400 | /* leave. */ | |
6401 | ginsn = x86_ginsn_leave (insn_end_sym); | |
6402 | break; | |
6403 | ||
6404 | case 0xe0 ... 0xe2: /* loop / loope / loopne. */ | |
6405 | case 0xe3: /* jecxz / jrcxz. */ | |
6406 | if (i.tm.opcode_space != SPACE_BASE) | |
6407 | break; | |
6408 | ginsn = x86_ginsn_jump (insn_end_sym, true); | |
6409 | ginsn_set_where (ginsn); | |
6410 | break; | |
6411 | ||
6412 | case 0xe8: | |
6413 | if (i.tm.opcode_space != SPACE_BASE) | |
6414 | break; | |
6415 | /* PS: SCFI machinery does not care about which func is being | |
6416 | called. OK to skip that info. */ | |
6417 | ginsn = ginsn_new_call (insn_end_sym, true, | |
6418 | GINSN_SRC_SYMBOL, 0, NULL); | |
6419 | ginsn_set_where (ginsn); | |
6420 | break; | |
6421 | ||
6422 | /* PS: opcode 0xe9 appears only after relaxation. Skip here. */ | |
6423 | case 0xeb: | |
6424 | /* If opcode_space != SPACE_BASE, this is not a jmp insn. Skip it | |
6425 | for GINSN_GEN_SCFI. */ | |
6426 | if (i.tm.opcode_space != SPACE_BASE) | |
6427 | break; | |
6428 | /* Unconditional jmp. */ | |
6429 | ginsn = x86_ginsn_jump (insn_end_sym, false); | |
6430 | ginsn_set_where (ginsn); | |
6431 | break; | |
6432 | ||
6433 | default: | |
6434 | /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for | |
6435 | GINSN_GEN_SCFI mode. */ | |
6436 | break; | |
6437 | } | |
6438 | ||
6439 | if (!ginsn && !x86_ginsn_safe_to_skip_p ()) | |
6440 | { | |
6441 | /* For all unhandled insns that are not whitelisted, check that they do | |
6442 | not impact SCFI correctness. */ | |
6443 | err = x86_ginsn_unhandled (); | |
6444 | switch (err) | |
6445 | { | |
6446 | case X86_GINSN_UNHANDLED_NONE: | |
6447 | break; | |
6448 | case X86_GINSN_UNHANDLED_DEST_REG: | |
6449 | /* Not all writes to REG_FP are harmful in context of SCFI. Simply | |
6450 | generate a GINSN_TYPE_OTHER with destination set to the | |
6451 | appropriate register. The SCFI machinery will bail out if this | |
6452 | ginsn affects SCFI correctness. */ | |
6453 | dw2_regnum = ginsn_dw2_regnum (i.op[i.operands - 1].regs); | |
6454 | ginsn = ginsn_new_other (insn_end_sym, true, | |
6455 | GINSN_SRC_IMM, 0, | |
6456 | GINSN_SRC_IMM, 0, | |
6457 | GINSN_DST_REG, dw2_regnum); | |
6458 | ginsn_set_where (ginsn); | |
6459 | break; | |
6460 | case X86_GINSN_UNHANDLED_CFG: | |
6461 | case X86_GINSN_UNHANDLED_STACKOP: | |
6462 | as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"), opcode); | |
6463 | break; | |
6464 | case X86_GINSN_UNHANDLED_UNEXPECTED: | |
6465 | as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"), | |
6466 | opcode); | |
6467 | break; | |
6468 | default: | |
6469 | abort (); | |
6470 | break; | |
6471 | } | |
6472 | } | |
6473 | ||
6474 | return ginsn; | |
6475 | } | |
6476 | ||
6477 | #endif | |
6478 | ||
252b5132 RH |
6479 | /* This is the guts of the machine-dependent assembler. LINE points to a |
6480 | machine dependent instruction. This function is supposed to emit | |
6481 | the frags/bytes it assembles to. */ | |
6482 | ||
6483 | void | |
65da13b5 | 6484 | md_assemble (char *line) |
252b5132 | 6485 | { |
40fb9820 | 6486 | unsigned int j; |
9db83a32 | 6487 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix = 0, *copy = NULL; |
04784e33 JB |
6488 | const char *end, *pass1_mnem = NULL; |
6489 | enum i386_error pass1_err = 0; | |
d3ce72d0 | 6490 | const insn_template *t; |
b5482fe5 JB |
6491 | struct last_insn *last_insn |
6492 | = &seg_info(now_seg)->tc_segment_info_data.last_insn; | |
252b5132 | 6493 | |
47926f60 | 6494 | /* Initialize globals. */ |
d3b01414 | 6495 | current_templates.end = current_templates.start = NULL; |
04784e33 | 6496 | retry: |
edd67638 | 6497 | init_globals (); |
252b5132 | 6498 | |
175ce60f JB |
6499 | /* Suppress optimization when the last thing we saw may not have been |
6500 | a proper instruction (e.g. a stand-alone prefix or .byte). */ | |
6501 | if (last_insn->kind != last_insn_other) | |
6502 | i.no_optimize = true; | |
6503 | ||
252b5132 RH |
6504 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
6505 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 6506 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 6507 | |
edd67638 | 6508 | end = parse_insn (line, mnemonic, false); |
5317ad2c | 6509 | if (end == NULL) |
04784e33 JB |
6510 | { |
6511 | if (pass1_mnem != NULL) | |
6512 | goto match_error; | |
9db83a32 JB |
6513 | if (i.error != no_error) |
6514 | { | |
d3b01414 JB |
6515 | gas_assert (current_templates.start != NULL); |
6516 | if (may_need_pass2 (current_templates.start) && !i.suffix) | |
9db83a32 JB |
6517 | goto no_match; |
6518 | /* No point in trying a 2nd pass - it'll only find the same suffix | |
6519 | again. */ | |
6520 | mnem_suffix = i.suffix; | |
6521 | goto match_error; | |
6522 | } | |
04784e33 JB |
6523 | return; |
6524 | } | |
d3b01414 | 6525 | t = current_templates.start; |
6d86a545 | 6526 | if (may_need_pass2 (t)) |
04784e33 JB |
6527 | { |
6528 | /* Make a copy of the full line in case we need to retry. */ | |
6529 | copy = xstrdup (line); | |
6530 | } | |
5317ad2c | 6531 | line += end - line; |
83b16ac6 | 6532 | mnem_suffix = i.suffix; |
252b5132 | 6533 | |
29b0f896 | 6534 | line = parse_operands (line, mnemonic); |
ee86248c | 6535 | this_operand = -1; |
29b0f896 | 6536 | if (line == NULL) |
04784e33 JB |
6537 | { |
6538 | free (copy); | |
6539 | return; | |
6540 | } | |
252b5132 | 6541 | |
29b0f896 AM |
6542 | /* Now we've parsed the mnemonic into a set of templates, and have the |
6543 | operands at hand. */ | |
6544 | ||
b630c145 | 6545 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
c0e54661 | 6546 | "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", |
b0e8fa7f TJ |
6547 | "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse |
6548 | intersegment "jmp" and "call" instructions with 2 immediate operands so | |
6549 | that the immediate segment precedes the offset consistently in Intel and | |
6550 | AT&T modes. */ | |
4d456e3d L |
6551 | if (intel_syntax |
6552 | && i.operands > 1 | |
6d86a545 JB |
6553 | && (t->mnem_off != MN_bound) |
6554 | && !startswith (mnemonic, "invlpg") | |
d34049e8 ML |
6555 | && !startswith (mnemonic, "monitor") |
6556 | && !startswith (mnemonic, "mwait") | |
6d86a545 | 6557 | && (t->mnem_off != MN_pvalidate) |
d34049e8 | 6558 | && !startswith (mnemonic, "rmp") |
6d86a545 JB |
6559 | && (t->mnem_off != MN_tpause) |
6560 | && (t->mnem_off != MN_umwait) | |
47c0279b JB |
6561 | && !(i.operands == 2 |
6562 | && operand_type_check (i.types[0], imm) | |
40fb9820 | 6563 | && operand_type_check (i.types[1], imm))) |
29b0f896 AM |
6564 | swap_operands (); |
6565 | ||
e7d74879 JB |
6566 | /* The order of the immediates should be reversed for 2-immediates EXTRQ |
6567 | and INSERTQ instructions. Also UWRMSR wants its immediate to be in the | |
6568 | "canonical" place (first), despite it appearing last (in AT&T syntax, or | |
6569 | because of the swapping above) in the incoming set of operands. */ | |
6570 | if ((i.imm_operands == 2 | |
6571 | && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) | |
6572 | || (t->mnem_off == MN_uwrmsr && i.imm_operands | |
6573 | && i.operands > i.imm_operands)) | |
ec56d5c0 JB |
6574 | swap_2_operands (0, 1); |
6575 | ||
29b0f896 | 6576 | if (i.imm_operands) |
8170af78 HL |
6577 | { |
6578 | /* For USER_MSR instructions, imm32 stands for the name of an model specific | |
6579 | register (MSR). That's an unsigned quantity, whereas all other insns with | |
6580 | 32-bit immediate and 64-bit operand size use sign-extended | |
6581 | immediates (imm32s). Therefore these insns are special-cased, bypassing | |
6582 | the normal handling of immediates here. */ | |
d3b01414 | 6583 | if (is_cpu(current_templates.start, CpuUSER_MSR)) |
8170af78 HL |
6584 | { |
6585 | for (j = 0; j < i.operands; j++) | |
6586 | { | |
6587 | if (operand_type_check(i.types[j], imm)) | |
6588 | i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number); | |
6589 | } | |
6590 | } | |
6591 | else | |
6592 | optimize_imm (); | |
6593 | } | |
29b0f896 | 6594 | |
0de704b9 JB |
6595 | if (i.disp_operands && !optimize_disp (t)) |
6596 | return; | |
29b0f896 AM |
6597 | |
6598 | /* Next, we find a template that matches the given insn, | |
6599 | making sure the overlap of the given operands types is consistent | |
6600 | with the template operand types. */ | |
252b5132 | 6601 | |
83b16ac6 | 6602 | if (!(t = match_template (mnem_suffix))) |
04784e33 JB |
6603 | { |
6604 | const char *err_msg; | |
6605 | ||
6606 | if (copy && !mnem_suffix) | |
6607 | { | |
6608 | line = copy; | |
6609 | copy = NULL; | |
9db83a32 | 6610 | no_match: |
04784e33 | 6611 | pass1_err = i.error; |
d3b01414 | 6612 | pass1_mnem = insn_name (current_templates.start); |
04784e33 JB |
6613 | goto retry; |
6614 | } | |
9db83a32 JB |
6615 | |
6616 | /* If a non-/only-64bit template (group) was found in pass 1, and if | |
6617 | _some_ template (group) was found in pass 2, squash pass 1's | |
6618 | error. */ | |
6619 | if (pass1_err == unsupported_64bit) | |
6620 | pass1_mnem = NULL; | |
6621 | ||
04784e33 | 6622 | match_error: |
9db83a32 JB |
6623 | free (copy); |
6624 | ||
04784e33 JB |
6625 | switch (pass1_mnem ? pass1_err : i.error) |
6626 | { | |
6627 | default: | |
6628 | abort (); | |
6629 | case operand_size_mismatch: | |
6630 | err_msg = _("operand size mismatch"); | |
6631 | break; | |
6632 | case operand_type_mismatch: | |
6633 | err_msg = _("operand type mismatch"); | |
6634 | break; | |
6635 | case register_type_mismatch: | |
6636 | err_msg = _("register type mismatch"); | |
6637 | break; | |
6638 | case number_of_operands_mismatch: | |
6639 | err_msg = _("number of operands mismatch"); | |
6640 | break; | |
6641 | case invalid_instruction_suffix: | |
6642 | err_msg = _("invalid instruction suffix"); | |
6643 | break; | |
6644 | case bad_imm4: | |
6645 | err_msg = _("constant doesn't fit in 4 bits"); | |
6646 | break; | |
6647 | case unsupported_with_intel_mnemonic: | |
6648 | err_msg = _("unsupported with Intel mnemonic"); | |
6649 | break; | |
6650 | case unsupported_syntax: | |
6651 | err_msg = _("unsupported syntax"); | |
6652 | break; | |
80d61d8d CL |
6653 | case unsupported_EGPR_for_addressing: |
6654 | err_msg = _("extended GPR cannot be used as base/index"); | |
6655 | break; | |
dd74a603 CL |
6656 | case unsupported_nf: |
6657 | err_msg = _("{nf} unsupported"); | |
6658 | break; | |
04784e33 JB |
6659 | case unsupported: |
6660 | as_bad (_("unsupported instruction `%s'"), | |
d3b01414 | 6661 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
04784e33 | 6662 | return; |
9db83a32 JB |
6663 | case unsupported_on_arch: |
6664 | as_bad (_("`%s' is not supported on `%s%s'"), | |
d3b01414 | 6665 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
9db83a32 JB |
6666 | cpu_arch_name ? cpu_arch_name : default_arch, |
6667 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
6668 | return; | |
6669 | case unsupported_64bit: | |
6670 | if (ISLOWER (mnem_suffix)) | |
e8b4b7b2 NC |
6671 | { |
6672 | if (flag_code == CODE_64BIT) | |
6673 | as_bad (_("`%s%c' is not supported in 64-bit mode"), | |
d3b01414 | 6674 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
e8b4b7b2 NC |
6675 | mnem_suffix); |
6676 | else | |
6677 | as_bad (_("`%s%c' is only supported in 64-bit mode"), | |
d3b01414 | 6678 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
e8b4b7b2 NC |
6679 | mnem_suffix); |
6680 | } | |
9db83a32 | 6681 | else |
e8b4b7b2 NC |
6682 | { |
6683 | if (flag_code == CODE_64BIT) | |
6684 | as_bad (_("`%s' is not supported in 64-bit mode"), | |
d3b01414 | 6685 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
e8b4b7b2 NC |
6686 | else |
6687 | as_bad (_("`%s' is only supported in 64-bit mode"), | |
d3b01414 | 6688 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
e8b4b7b2 | 6689 | } |
9db83a32 | 6690 | return; |
54294d73 JB |
6691 | case no_vex_encoding: |
6692 | err_msg = _("no VEX/XOP encoding"); | |
6693 | break; | |
6694 | case no_evex_encoding: | |
6695 | err_msg = _("no EVEX encoding"); | |
6696 | break; | |
04784e33 JB |
6697 | case invalid_sib_address: |
6698 | err_msg = _("invalid SIB address"); | |
6699 | break; | |
6700 | case invalid_vsib_address: | |
6701 | err_msg = _("invalid VSIB address"); | |
6702 | break; | |
6703 | case invalid_vector_register_set: | |
6704 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6705 | break; | |
6706 | case invalid_tmm_register_set: | |
6707 | err_msg = _("all tmm registers must be distinct"); | |
6708 | break; | |
6709 | case invalid_dest_and_src_register_set: | |
6710 | err_msg = _("destination and source registers must be distinct"); | |
6711 | break; | |
08a98d4c MZ |
6712 | case invalid_dest_register_set: |
6713 | err_msg = _("two dest registers must be distinct"); | |
6714 | break; | |
80d61d8d CL |
6715 | case invalid_pseudo_prefix: |
6716 | err_msg = _("rex2 pseudo prefix cannot be used"); | |
6717 | break; | |
04784e33 JB |
6718 | case unsupported_vector_index_register: |
6719 | err_msg = _("unsupported vector index register"); | |
6720 | break; | |
6721 | case unsupported_broadcast: | |
6722 | err_msg = _("unsupported broadcast"); | |
6723 | break; | |
6724 | case broadcast_needed: | |
6725 | err_msg = _("broadcast is needed for operand of such type"); | |
6726 | break; | |
6727 | case unsupported_masking: | |
6728 | err_msg = _("unsupported masking"); | |
6729 | break; | |
6730 | case mask_not_on_destination: | |
6731 | err_msg = _("mask not on destination operand"); | |
6732 | break; | |
6733 | case no_default_mask: | |
6734 | err_msg = _("default mask isn't allowed"); | |
6735 | break; | |
6736 | case unsupported_rc_sae: | |
6737 | err_msg = _("unsupported static rounding/sae"); | |
6738 | break; | |
54294d73 JB |
6739 | case unsupported_vector_size: |
6740 | as_bad (_("vector size above %u required for `%s'"), 128u << vector_size, | |
d3b01414 | 6741 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
54294d73 | 6742 | return; |
08a98d4c MZ |
6743 | case unsupported_rsp_register: |
6744 | err_msg = _("'rsp' register cannot be used"); | |
6745 | break; | |
58bceb18 JB |
6746 | case internal_error: |
6747 | err_msg = _("internal error"); | |
6748 | break; | |
04784e33 JB |
6749 | } |
6750 | as_bad (_("%s for `%s'"), err_msg, | |
d3b01414 | 6751 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
04784e33 JB |
6752 | return; |
6753 | } | |
6754 | ||
6755 | free (copy); | |
252b5132 | 6756 | |
7bab8ab5 | 6757 | if (sse_check != check_none |
ffb86450 JB |
6758 | /* The opcode space check isn't strictly needed; it's there only to |
6759 | bypass the logic below when easily possible. */ | |
ddb62495 JB |
6760 | && t->opcode_space >= SPACE_0F |
6761 | && t->opcode_space <= SPACE_0F3A | |
734dfd1c | 6762 | && !is_cpu (&i.tm, CpuSSE4a) |
ffb86450 | 6763 | && !is_any_vex_encoding (t)) |
daf50ae7 | 6764 | { |
06360a5c JB |
6765 | /* Some KL and all WideKL insns have only implicit %xmm operands. */ |
6766 | bool simd = is_cpu (t, CpuKL) || is_cpu (t, CpuWideKL); | |
ffb86450 JB |
6767 | |
6768 | for (j = 0; j < t->operands; ++j) | |
6769 | { | |
6770 | if (t->operand_types[j].bitfield.class == RegMMX) | |
6771 | break; | |
6772 | if (t->operand_types[j].bitfield.class == RegSIMD) | |
6773 | simd = true; | |
6774 | } | |
6775 | ||
6776 | if (j >= t->operands && simd) | |
6777 | (sse_check == check_warning | |
6778 | ? as_warn | |
76d3f746 | 6779 | : as_bad) (_("SSE instruction `%s' is used"), insn_name (&i.tm)); |
daf50ae7 L |
6780 | } |
6781 | ||
40fb9820 | 6782 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
6783 | if (!add_prefix (FWAIT_OPCODE)) |
6784 | return; | |
252b5132 | 6785 | |
d5de92cf | 6786 | /* Check if REP prefix is OK. */ |
742732c7 | 6787 | if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep) |
d5de92cf L |
6788 | { |
6789 | as_bad (_("invalid instruction `%s' after `%s'"), | |
76d3f746 | 6790 | insn_name (&i.tm), i.rep_prefix); |
d5de92cf L |
6791 | return; |
6792 | } | |
6793 | ||
c1ba0266 L |
6794 | /* Check for lock without a lockable instruction. Destination operand |
6795 | must be memory unless it is xchg (0x86). */ | |
9a4a4499 JB |
6796 | if (i.prefix[LOCK_PREFIX]) |
6797 | { | |
6798 | if (i.tm.opcode_modifier.prefixok < PrefixLock | |
c1ba0266 L |
6799 | || i.mem_operands == 0 |
6800 | || (i.tm.base_opcode != 0x86 | |
9a4a4499 JB |
6801 | && !(i.flags[i.operands - 1] & Operand_Mem))) |
6802 | { | |
6803 | as_bad (_("expecting lockable instruction after `lock'")); | |
6804 | return; | |
6805 | } | |
6806 | ||
6807 | /* Zap the redundant prefix from XCHG when optimizing. */ | |
6808 | if (i.tm.base_opcode == 0x86 && optimize && !i.no_optimize) | |
6809 | i.prefix[LOCK_PREFIX] = 0; | |
c32fa91d L |
6810 | } |
6811 | ||
e3669c7f JB |
6812 | if (is_any_vex_encoding (&i.tm) |
6813 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
6814 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX) | |
7a8655d2 | 6815 | { |
e3669c7f JB |
6816 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
6817 | if (i.prefix[DATA_PREFIX]) | |
6818 | { | |
76d3f746 | 6819 | as_bad (_("data size prefix invalid with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
6820 | return; |
6821 | } | |
6822 | ||
6823 | /* Don't allow e.g. KMOV in TLS code sequences. */ | |
6824 | for (j = i.imm_operands; j < i.operands; ++j) | |
6825 | switch (i.reloc[j]) | |
6826 | { | |
5bc71c2a L |
6827 | case BFD_RELOC_X86_64_GOTTPOFF: |
6828 | if (i.tm.mnem_off == MN_add | |
6829 | && i.tm.opcode_space == SPACE_EVEXMAP4 | |
6830 | && i.mem_operands == 1 | |
6831 | && i.base_reg | |
6832 | && i.base_reg->reg_num == RegIP | |
6833 | && i.tm.operand_types[0].bitfield.class == Reg | |
6834 | && i.tm.operand_types[2].bitfield.class == Reg) | |
6835 | /* Allow APX: add %reg1, foo@gottpoff(%rip), %reg2. */ | |
6836 | break; | |
6837 | /* Fall through. */ | |
e3669c7f JB |
6838 | case BFD_RELOC_386_TLS_GOTIE: |
6839 | case BFD_RELOC_386_TLS_LE_32: | |
e3669c7f | 6840 | case BFD_RELOC_X86_64_TLSLD: |
76d3f746 | 6841 | as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
6842 | return; |
6843 | default: | |
6844 | break; | |
6845 | } | |
7a8655d2 JB |
6846 | } |
6847 | ||
42164a71 | 6848 | /* Check if HLE prefix is OK. */ |
165de32a | 6849 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
6850 | return; |
6851 | ||
7e8b059b L |
6852 | /* Check BND prefix. */ |
6853 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
6854 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
6855 | ||
04ef582a | 6856 | /* Check NOTRACK prefix. */ |
742732c7 | 6857 | if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack) |
9fef80d6 | 6858 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
04ef582a | 6859 | |
734dfd1c | 6860 | if (is_cpu (&i.tm, CpuMPX)) |
327e8c42 JB |
6861 | { |
6862 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
6863 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
6864 | else if (flag_code != CODE_16BIT | |
6865 | ? i.prefix[ADDR_PREFIX] | |
6866 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
6867 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
6868 | } | |
7e8b059b L |
6869 | |
6870 | /* Insert BND prefix. */ | |
76d3a78a JB |
6871 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
6872 | { | |
6873 | if (!i.prefix[BND_PREFIX]) | |
6874 | add_prefix (BND_PREFIX_OPCODE); | |
6875 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
6876 | { | |
6877 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
6878 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
6879 | } | |
6880 | } | |
7e8b059b | 6881 | |
29b0f896 | 6882 | /* Check string instruction segment overrides. */ |
51c8edf6 | 6883 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 6884 | { |
51c8edf6 | 6885 | gas_assert (i.mem_operands); |
29b0f896 | 6886 | if (!check_string ()) |
5dd0794d | 6887 | return; |
fc0763e6 | 6888 | i.disp_operands = 0; |
29b0f896 | 6889 | } |
5dd0794d | 6890 | |
9373f275 L |
6891 | /* The memory operand of (%dx) should be only used with input/output |
6892 | instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */ | |
6893 | if (i.input_output_operand | |
6894 | && ((i.tm.base_opcode | 0x82) != 0xee | |
ddb62495 | 6895 | || i.tm.opcode_space != SPACE_BASE)) |
9373f275 L |
6896 | { |
6897 | as_bad (_("input/output port address isn't allowed with `%s'"), | |
76d3f746 | 6898 | insn_name (&i.tm)); |
9373f275 L |
6899 | return; |
6900 | } | |
6901 | ||
b6f8c7c4 L |
6902 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
6903 | optimize_encoding (); | |
6904 | ||
eb3f3841 JB |
6905 | /* Past optimization there's no need to distinguish encoding_evex, |
6906 | encoding_evex512, and encoding_egpr anymore. */ | |
e346d50a JB |
6907 | if (i.encoding == encoding_evex512) |
6908 | i.encoding = encoding_evex; | |
eb3f3841 JB |
6909 | else if (i.encoding == encoding_egpr) |
6910 | i.encoding = is_any_vex_encoding (&i.tm) ? encoding_evex | |
6911 | : encoding_default; | |
a6f3add0 | 6912 | |
c8480b58 L |
6913 | if (use_unaligned_vector_move) |
6914 | encode_with_unaligned_vector_move (); | |
6915 | ||
29b0f896 AM |
6916 | if (!process_suffix ()) |
6917 | return; | |
e413e4e9 | 6918 | |
ef07be45 | 6919 | /* Check if IP-relative addressing requirements can be satisfied. */ |
734dfd1c | 6920 | if (is_cpu (&i.tm, CpuPREFETCHI) |
ef07be45 | 6921 | && !(i.base_reg && i.base_reg->reg_num == RegIP)) |
76d3f746 | 6922 | as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i.tm)); |
ef07be45 | 6923 | |
921eafea | 6924 | /* Update operand types and check extended states. */ |
bc0844ae | 6925 | for (j = 0; j < i.operands; j++) |
921eafea L |
6926 | { |
6927 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3d70986f | 6928 | switch (i.tm.operand_types[j].bitfield.class) |
921eafea L |
6929 | { |
6930 | default: | |
6931 | break; | |
6932 | case RegMMX: | |
6933 | i.xstate |= xstate_mmx; | |
6934 | break; | |
6935 | case RegMask: | |
32930e4e | 6936 | i.xstate |= xstate_mask; |
921eafea L |
6937 | break; |
6938 | case RegSIMD: | |
3d70986f | 6939 | if (i.tm.operand_types[j].bitfield.tmmword) |
921eafea | 6940 | i.xstate |= xstate_tmm; |
4fc85f37 | 6941 | else if (i.tm.operand_types[j].bitfield.zmmword |
a6f3add0 | 6942 | && !i.tm.opcode_modifier.vex |
4fc85f37 | 6943 | && vector_size >= VSZ512) |
921eafea | 6944 | i.xstate |= xstate_zmm; |
4fc85f37 JB |
6945 | else if (i.tm.operand_types[j].bitfield.ymmword |
6946 | && vector_size >= VSZ256) | |
921eafea | 6947 | i.xstate |= xstate_ymm; |
3d70986f | 6948 | else if (i.tm.operand_types[j].bitfield.xmmword) |
921eafea L |
6949 | i.xstate |= xstate_xmm; |
6950 | break; | |
6951 | } | |
6952 | } | |
bc0844ae | 6953 | |
29b0f896 AM |
6954 | /* Make still unresolved immediate matches conform to size of immediate |
6955 | given in i.suffix. */ | |
6956 | if (!finalize_imm ()) | |
6957 | return; | |
252b5132 | 6958 | |
40fb9820 | 6959 | if (i.types[0].bitfield.imm1) |
29b0f896 | 6960 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 6961 | |
29b0f896 AM |
6962 | /* For insns with operands there are more diddles to do to the opcode. */ |
6963 | if (i.operands) | |
6964 | { | |
6965 | if (!process_operands ()) | |
6966 | return; | |
6967 | } | |
255571cd | 6968 | else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) |
29b0f896 AM |
6969 | { |
6970 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
76d3f746 | 6971 | as_warn (_("translating to `%sp'"), insn_name (&i.tm)); |
29b0f896 | 6972 | } |
252b5132 | 6973 | |
7a8655d2 | 6974 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 6975 | { |
c1dc7af5 | 6976 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 6977 | { |
c1dc7af5 | 6978 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
76d3f746 | 6979 | insn_name (&i.tm)); |
9e5e5283 L |
6980 | return; |
6981 | } | |
c0f3af97 | 6982 | |
0b9404fd JB |
6983 | /* Check for explicit REX prefix. */ |
6984 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
6985 | { | |
76d3f746 | 6986 | as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm)); |
0b9404fd JB |
6987 | return; |
6988 | } | |
6989 | ||
80d61d8d CL |
6990 | /* Check for explicit REX2 prefix. */ |
6991 | if (i.rex2_encoding) | |
6992 | { | |
6993 | as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm)); | |
6994 | return; | |
6995 | } | |
6996 | ||
6177c84d CL |
6997 | if (is_apx_evex_encoding ()) |
6998 | build_apx_evex_prefix (); | |
6999 | else if (i.tm.opcode_modifier.vex) | |
9e5e5283 L |
7000 | build_vex_prefix (t); |
7001 | else | |
7002 | build_evex_prefix (); | |
0b9404fd JB |
7003 | |
7004 | /* The individual REX.RXBW bits got consumed. */ | |
7005 | i.rex &= REX_OPCODE; | |
6177c84d CL |
7006 | |
7007 | /* The rex2 bits got consumed. */ | |
7008 | i.rex2 = 0; | |
9e5e5283 | 7009 | } |
43234a1e | 7010 | |
7fc69528 JB |
7011 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
7012 | if (i.tm.mnem_off == MN_int | |
a6461c02 | 7013 | && i.op[0].imms->X_add_number == 3) |
29b0f896 AM |
7014 | { |
7015 | i.tm.base_opcode = INT3_OPCODE; | |
7016 | i.imm_operands = 0; | |
7017 | } | |
252b5132 | 7018 | |
0cfa3eb3 JB |
7019 | if ((i.tm.opcode_modifier.jump == JUMP |
7020 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
7021 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
7022 | && i.op[0].disps->X_op == O_constant) |
7023 | { | |
7024 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
7025 | the absolute address given by the constant. Since ix86 jumps and | |
7026 | calls are pc relative, we need to generate a reloc. */ | |
7027 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
7028 | i.op[0].disps->X_op = O_symbol; | |
7029 | } | |
252b5132 | 7030 | |
ce705688 | 7031 | establish_rex (); |
29b0f896 | 7032 | |
b5482fe5 | 7033 | insert_lfence_before (last_insn); |
ae531041 | 7034 | |
29b0f896 | 7035 | /* We are ready to output the insn. */ |
b5482fe5 | 7036 | output_insn (last_insn); |
e379e5f3 | 7037 | |
c7defc53 IB |
7038 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
7039 | /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been | |
7040 | performed in i386_target_format. */ | |
7041 | if (IS_ELF && flag_synth_cfi) | |
7042 | { | |
7043 | ginsnS *ginsn; | |
7044 | ginsn = x86_ginsn_new (symbol_temp_new_now (), frch_ginsn_gen_mode ()); | |
7045 | frch_ginsn_data_append (ginsn); | |
7046 | } | |
7047 | #endif | |
7048 | ||
ae531041 L |
7049 | insert_lfence_after (); |
7050 | ||
e379e5f3 L |
7051 | if (i.tm.opcode_modifier.isprefix) |
7052 | { | |
b5482fe5 JB |
7053 | last_insn->kind = last_insn_prefix; |
7054 | last_insn->name = insn_name (&i.tm); | |
7055 | last_insn->file = as_where (&last_insn->line); | |
e379e5f3 L |
7056 | } |
7057 | else | |
b5482fe5 | 7058 | last_insn->kind = last_insn_other; |
29b0f896 AM |
7059 | } |
7060 | ||
9db83a32 JB |
7061 | /* The Q suffix is generally valid only in 64-bit mode, with very few |
7062 | exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild | |
7063 | and fisttp only one of their two templates is matched below: That's | |
7064 | sufficient since other relevant attributes are the same between both | |
7065 | respective templates. */ | |
7066 | static INLINE bool q_suffix_allowed(const insn_template *t) | |
7067 | { | |
7068 | return flag_code == CODE_64BIT | |
ddb62495 | 7069 | || (t->opcode_space == SPACE_BASE |
9db83a32 JB |
7070 | && t->base_opcode == 0xdf |
7071 | && (t->extension_opcode & 1)) /* fild / fistp / fisttp */ | |
7fc69528 | 7072 | || t->mnem_off == MN_cmpxchg8b; |
9db83a32 JB |
7073 | } |
7074 | ||
5317ad2c | 7075 | static const char * |
edd67638 | 7076 | parse_insn (const char *line, char *mnemonic, bool prefix_only) |
29b0f896 | 7077 | { |
5317ad2c | 7078 | const char *l = line, *token_start = l; |
29b0f896 | 7079 | char *mnem_p; |
d3b01414 | 7080 | bool pass1 = !current_templates.start; |
5c6af06e | 7081 | int supported; |
d3ce72d0 | 7082 | const insn_template *t; |
b6169b20 | 7083 | char *dot_p = NULL; |
29b0f896 | 7084 | |
29b0f896 AM |
7085 | while (1) |
7086 | { | |
7087 | mnem_p = mnemonic; | |
778415f5 JB |
7088 | /* Pseudo-prefixes start with an opening figure brace. */ |
7089 | if ((*mnem_p = *l) == '{') | |
7090 | { | |
7091 | ++mnem_p; | |
7092 | ++l; | |
7093 | } | |
29b0f896 AM |
7094 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
7095 | { | |
b6169b20 L |
7096 | if (*mnem_p == '.') |
7097 | dot_p = mnem_p; | |
29b0f896 AM |
7098 | mnem_p++; |
7099 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 7100 | { |
778415f5 | 7101 | too_long: |
29b0f896 AM |
7102 | as_bad (_("no such instruction: `%s'"), token_start); |
7103 | return NULL; | |
7104 | } | |
7105 | l++; | |
7106 | } | |
778415f5 JB |
7107 | /* Pseudo-prefixes end with a closing figure brace. */ |
7108 | if (*mnemonic == '{' && *l == '}') | |
7109 | { | |
7110 | *mnem_p++ = *l++; | |
7111 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
7112 | goto too_long; | |
7113 | *mnem_p = '\0'; | |
7114 | ||
7115 | /* Point l at the closing brace if there's no other separator. */ | |
7116 | if (*l != END_OF_INSN && !is_space_char (*l) | |
7117 | && *l != PREFIX_SEPARATOR) | |
7118 | --l; | |
7119 | } | |
7120 | else if (!is_space_char (*l) | |
7121 | && *l != END_OF_INSN | |
7122 | && (intel_syntax | |
7123 | || (*l != PREFIX_SEPARATOR && *l != ','))) | |
29b0f896 | 7124 | { |
edd67638 JB |
7125 | if (prefix_only) |
7126 | break; | |
29b0f896 AM |
7127 | as_bad (_("invalid character %s in mnemonic"), |
7128 | output_invalid (*l)); | |
7129 | return NULL; | |
7130 | } | |
7131 | if (token_start == l) | |
7132 | { | |
e44823cf | 7133 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
7134 | as_bad (_("expecting prefix; got nothing")); |
7135 | else | |
7136 | as_bad (_("expecting mnemonic; got nothing")); | |
7137 | return NULL; | |
7138 | } | |
45288df1 | 7139 | |
29b0f896 | 7140 | /* Look up instruction (or prefix) via hash table. */ |
d3b01414 | 7141 | op_lookup (mnemonic); |
47926f60 | 7142 | |
29b0f896 AM |
7143 | if (*l != END_OF_INSN |
7144 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
d3b01414 JB |
7145 | && current_templates.start |
7146 | && current_templates.start->opcode_modifier.isprefix) | |
29b0f896 | 7147 | { |
d3b01414 | 7148 | supported = cpu_flags_match (current_templates.start); |
3086ed9a | 7149 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
2dd88dca JB |
7150 | { |
7151 | as_bad ((flag_code != CODE_64BIT | |
7152 | ? _("`%s' is only supported in 64-bit mode") | |
7153 | : _("`%s' is not supported in 64-bit mode")), | |
d3b01414 | 7154 | insn_name (current_templates.start)); |
2dd88dca JB |
7155 | return NULL; |
7156 | } | |
3086ed9a JB |
7157 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
7158 | { | |
7159 | as_bad (_("`%s' is not supported on `%s%s'"), | |
d3b01414 | 7160 | insn_name (current_templates.start), |
3086ed9a JB |
7161 | cpu_arch_name ? cpu_arch_name : default_arch, |
7162 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
7163 | return NULL; | |
7164 | } | |
29b0f896 AM |
7165 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
7166 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
d3b01414 JB |
7167 | if ((current_templates.start->opcode_modifier.size == SIZE16 |
7168 | || current_templates.start->opcode_modifier.size == SIZE32) | |
29b0f896 | 7169 | && flag_code != CODE_64BIT |
d3b01414 | 7170 | && ((current_templates.start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
7171 | ^ (flag_code == CODE_16BIT))) |
7172 | { | |
7173 | as_bad (_("redundant %s prefix"), | |
d3b01414 | 7174 | insn_name (current_templates.start)); |
29b0f896 | 7175 | return NULL; |
45288df1 | 7176 | } |
31184569 | 7177 | |
d3b01414 | 7178 | if (current_templates.start->base_opcode == PSEUDO_PREFIX) |
29b0f896 | 7179 | { |
86fa6981 | 7180 | /* Handle pseudo prefixes. */ |
d3b01414 | 7181 | switch (current_templates.start->extension_opcode) |
86fa6981 | 7182 | { |
41eb8e88 | 7183 | case Prefix_Disp8: |
86fa6981 L |
7184 | /* {disp8} */ |
7185 | i.disp_encoding = disp_encoding_8bit; | |
7186 | break; | |
41eb8e88 L |
7187 | case Prefix_Disp16: |
7188 | /* {disp16} */ | |
7189 | i.disp_encoding = disp_encoding_16bit; | |
7190 | break; | |
7191 | case Prefix_Disp32: | |
86fa6981 L |
7192 | /* {disp32} */ |
7193 | i.disp_encoding = disp_encoding_32bit; | |
7194 | break; | |
41eb8e88 | 7195 | case Prefix_Load: |
86fa6981 L |
7196 | /* {load} */ |
7197 | i.dir_encoding = dir_encoding_load; | |
7198 | break; | |
41eb8e88 | 7199 | case Prefix_Store: |
86fa6981 L |
7200 | /* {store} */ |
7201 | i.dir_encoding = dir_encoding_store; | |
7202 | break; | |
41eb8e88 | 7203 | case Prefix_VEX: |
42e04b36 | 7204 | /* {vex} */ |
e346d50a | 7205 | i.encoding = encoding_vex; |
86fa6981 | 7206 | break; |
41eb8e88 | 7207 | case Prefix_VEX3: |
86fa6981 | 7208 | /* {vex3} */ |
e346d50a | 7209 | i.encoding = encoding_vex3; |
86fa6981 | 7210 | break; |
41eb8e88 | 7211 | case Prefix_EVEX: |
86fa6981 | 7212 | /* {evex} */ |
e346d50a | 7213 | i.encoding = encoding_evex; |
86fa6981 | 7214 | break; |
41eb8e88 | 7215 | case Prefix_REX: |
6b6b6807 | 7216 | /* {rex} */ |
5b7c81bd | 7217 | i.rex_encoding = true; |
6b6b6807 | 7218 | break; |
80d61d8d CL |
7219 | case Prefix_REX2: |
7220 | /* {rex2} */ | |
7221 | i.rex2_encoding = true; | |
7222 | break; | |
dd74a603 CL |
7223 | case Prefix_NF: |
7224 | /* {nf} */ | |
7225 | i.has_nf = true; | |
7226 | if (i.encoding == encoding_default) | |
7227 | i.encoding = encoding_evex; | |
7228 | break; | |
41eb8e88 | 7229 | case Prefix_NoOptimize: |
b6f8c7c4 | 7230 | /* {nooptimize} */ |
5b7c81bd | 7231 | i.no_optimize = true; |
b6f8c7c4 | 7232 | break; |
86fa6981 L |
7233 | default: |
7234 | abort (); | |
7235 | } | |
dd74a603 CL |
7236 | if (i.has_nf && i.encoding != encoding_evex) |
7237 | { | |
7238 | as_bad (_("{nf} cannot be combined with {vex}/{vex3}")); | |
7239 | return NULL; | |
7240 | } | |
86fa6981 L |
7241 | } |
7242 | else | |
7243 | { | |
7244 | /* Add prefix, checking for repeated prefixes. */ | |
d3b01414 | 7245 | switch (add_prefix (current_templates.start->base_opcode)) |
86fa6981 | 7246 | { |
4e9ac44a L |
7247 | case PREFIX_EXIST: |
7248 | return NULL; | |
7249 | case PREFIX_DS: | |
d3b01414 JB |
7250 | if (is_cpu (current_templates.start, CpuIBT)) |
7251 | i.notrack_prefix = insn_name (current_templates.start); | |
4e9ac44a L |
7252 | break; |
7253 | case PREFIX_REP: | |
d3b01414 JB |
7254 | if (is_cpu (current_templates.start, CpuHLE)) |
7255 | i.hle_prefix = insn_name (current_templates.start); | |
7256 | else if (is_cpu (current_templates.start, CpuMPX)) | |
7257 | i.bnd_prefix = insn_name (current_templates.start); | |
4e9ac44a | 7258 | else |
d3b01414 | 7259 | i.rep_prefix = insn_name (current_templates.start); |
4e9ac44a L |
7260 | break; |
7261 | default: | |
7262 | break; | |
86fa6981 | 7263 | } |
29b0f896 AM |
7264 | } |
7265 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
7266 | token_start = ++l; | |
7267 | } | |
7268 | else | |
7269 | break; | |
7270 | } | |
45288df1 | 7271 | |
edd67638 JB |
7272 | if (prefix_only) |
7273 | return token_start; | |
7274 | ||
d3b01414 | 7275 | if (!current_templates.start) |
b6169b20 | 7276 | { |
07d5e953 JB |
7277 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
7278 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 7279 | encoding. */ |
30a55f88 | 7280 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
97f31cb4 JB |
7281 | { |
7282 | if (i.dir_encoding == dir_encoding_default) | |
7283 | i.dir_encoding = dir_encoding_swap; | |
7284 | else | |
7285 | as_warn (_("ignoring `.s' suffix due to earlier `{%s}'"), | |
7286 | i.dir_encoding == dir_encoding_load ? "load" : "store"); | |
7287 | } | |
8d63c93e | 7288 | else if (mnem_p - 3 == dot_p |
a501d77e L |
7289 | && dot_p[1] == 'd' |
7290 | && dot_p[2] == '8') | |
97f31cb4 JB |
7291 | { |
7292 | if (i.disp_encoding == disp_encoding_default) | |
7293 | i.disp_encoding = disp_encoding_8bit; | |
7294 | else if (i.disp_encoding != disp_encoding_8bit) | |
7295 | as_warn (_("ignoring `.d8' suffix due to earlier `{disp<N>}'")); | |
7296 | } | |
8d63c93e | 7297 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
7298 | && dot_p[1] == 'd' |
7299 | && dot_p[2] == '3' | |
7300 | && dot_p[3] == '2') | |
97f31cb4 JB |
7301 | { |
7302 | if (i.disp_encoding == disp_encoding_default) | |
7303 | i.disp_encoding = disp_encoding_32bit; | |
7304 | else if (i.disp_encoding != disp_encoding_32bit) | |
7305 | as_warn (_("ignoring `.d32' suffix due to earlier `{disp<N>}'")); | |
7306 | } | |
30a55f88 L |
7307 | else |
7308 | goto check_suffix; | |
7309 | mnem_p = dot_p; | |
7310 | *dot_p = '\0'; | |
d3b01414 | 7311 | op_lookup (mnemonic); |
b6169b20 L |
7312 | } |
7313 | ||
d3b01414 | 7314 | if (!current_templates.start || !pass1) |
29b0f896 | 7315 | { |
d3b01414 | 7316 | current_templates.start = NULL; |
04784e33 | 7317 | |
dc1e8a47 | 7318 | check_suffix: |
1c529385 | 7319 | if (mnem_p > mnemonic) |
29b0f896 | 7320 | { |
1c529385 LH |
7321 | /* See if we can get a match by trimming off a suffix. */ |
7322 | switch (mnem_p[-1]) | |
29b0f896 | 7323 | { |
1c529385 LH |
7324 | case WORD_MNEM_SUFFIX: |
7325 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
7326 | i.suffix = SHORT_MNEM_SUFFIX; |
7327 | else | |
1c529385 LH |
7328 | /* Fall through. */ |
7329 | case BYTE_MNEM_SUFFIX: | |
7330 | case QWORD_MNEM_SUFFIX: | |
7331 | i.suffix = mnem_p[-1]; | |
29b0f896 | 7332 | mnem_p[-1] = '\0'; |
d3b01414 | 7333 | op_lookup (mnemonic); |
1c529385 LH |
7334 | break; |
7335 | case SHORT_MNEM_SUFFIX: | |
7336 | case LONG_MNEM_SUFFIX: | |
7337 | if (!intel_syntax) | |
7338 | { | |
7339 | i.suffix = mnem_p[-1]; | |
7340 | mnem_p[-1] = '\0'; | |
d3b01414 | 7341 | op_lookup (mnemonic); |
1c529385 LH |
7342 | } |
7343 | break; | |
7344 | ||
7345 | /* Intel Syntax. */ | |
7346 | case 'd': | |
7347 | if (intel_syntax) | |
7348 | { | |
7349 | if (intel_float_operand (mnemonic) == 1) | |
7350 | i.suffix = SHORT_MNEM_SUFFIX; | |
7351 | else | |
7352 | i.suffix = LONG_MNEM_SUFFIX; | |
7353 | mnem_p[-1] = '\0'; | |
d3b01414 | 7354 | op_lookup (mnemonic); |
1c529385 | 7355 | } |
04784e33 JB |
7356 | /* For compatibility reasons accept MOVSD and CMPSD without |
7357 | operands even in AT&T mode. */ | |
7358 | else if (*l == END_OF_INSN | |
7359 | || (is_space_char (*l) && l[1] == END_OF_INSN)) | |
7360 | { | |
7361 | mnem_p[-1] = '\0'; | |
d3b01414 JB |
7362 | op_lookup (mnemonic); |
7363 | if (current_templates.start != NULL | |
04784e33 | 7364 | /* MOVS or CMPS */ |
d3b01414 JB |
7365 | && (current_templates.start->base_opcode | 2) == 0xa6 |
7366 | && current_templates.start->opcode_space | |
04784e33 JB |
7367 | == SPACE_BASE |
7368 | && mnem_p[-2] == 's') | |
7369 | { | |
7370 | as_warn (_("found `%sd'; assuming `%sl' was meant"), | |
7371 | mnemonic, mnemonic); | |
7372 | i.suffix = LONG_MNEM_SUFFIX; | |
7373 | } | |
7374 | else | |
7375 | { | |
d3b01414 | 7376 | current_templates.start = NULL; |
04784e33 JB |
7377 | mnem_p[-1] = 'd'; |
7378 | } | |
7379 | } | |
1c529385 | 7380 | break; |
29b0f896 | 7381 | } |
29b0f896 | 7382 | } |
1c529385 | 7383 | |
d3b01414 | 7384 | if (!current_templates.start) |
29b0f896 | 7385 | { |
04784e33 JB |
7386 | if (pass1) |
7387 | as_bad (_("no such instruction: `%s'"), token_start); | |
29b0f896 AM |
7388 | return NULL; |
7389 | } | |
7390 | } | |
252b5132 | 7391 | |
d3b01414 JB |
7392 | if (current_templates.start->opcode_modifier.jump == JUMP |
7393 | || current_templates.start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
7394 | { |
7395 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
7396 | predict taken and predict not taken respectively. | |
7397 | I'm not sure that branch hints actually do anything on loop | |
7398 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
7399 | may work in the future and it doesn't hurt to accept them | |
7400 | now. */ | |
7401 | if (l[0] == ',' && l[1] == 'p') | |
7402 | { | |
7403 | if (l[2] == 't') | |
7404 | { | |
7405 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
7406 | return NULL; | |
7407 | l += 3; | |
7408 | } | |
7409 | else if (l[2] == 'n') | |
7410 | { | |
7411 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
7412 | return NULL; | |
7413 | l += 3; | |
7414 | } | |
7415 | } | |
7416 | } | |
7417 | /* Any other comma loses. */ | |
7418 | if (*l == ',') | |
7419 | { | |
7420 | as_bad (_("invalid character %s in mnemonic"), | |
7421 | output_invalid (*l)); | |
7422 | return NULL; | |
7423 | } | |
252b5132 | 7424 | |
29b0f896 | 7425 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e | 7426 | supported = 0; |
d3b01414 | 7427 | for (t = current_templates.start; t < current_templates.end; ++t) |
5c6af06e | 7428 | { |
c0f3af97 | 7429 | supported |= cpu_flags_match (t); |
9db83a32 JB |
7430 | |
7431 | if (i.suffix == QWORD_MNEM_SUFFIX && !q_suffix_allowed (t)) | |
7432 | supported &= ~CPU_FLAGS_64BIT_MATCH; | |
7433 | ||
c0f3af97 | 7434 | if (supported == CPU_FLAGS_PERFECT_MATCH) |
d59a54c2 | 7435 | return l; |
29b0f896 | 7436 | } |
3629bb00 | 7437 | |
9db83a32 JB |
7438 | if (pass1) |
7439 | { | |
7440 | if (supported & CPU_FLAGS_64BIT_MATCH) | |
7441 | i.error = unsupported_on_arch; | |
7442 | else | |
7443 | i.error = unsupported_64bit; | |
7444 | } | |
252b5132 | 7445 | |
548d0ee6 | 7446 | return NULL; |
29b0f896 | 7447 | } |
252b5132 | 7448 | |
29b0f896 | 7449 | static char * |
e3bb37b5 | 7450 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
7451 | { |
7452 | char *token_start; | |
3138f287 | 7453 | |
29b0f896 AM |
7454 | /* 1 if operand is pending after ','. */ |
7455 | unsigned int expecting_operand = 0; | |
252b5132 | 7456 | |
29b0f896 AM |
7457 | while (*l != END_OF_INSN) |
7458 | { | |
e68c3d59 JB |
7459 | /* Non-zero if operand parens not balanced. */ |
7460 | unsigned int paren_not_balanced = 0; | |
7461 | /* True if inside double quotes. */ | |
7462 | bool in_quotes = false; | |
7463 | ||
29b0f896 AM |
7464 | /* Skip optional white space before operand. */ |
7465 | if (is_space_char (*l)) | |
7466 | ++l; | |
d02603dc | 7467 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
7468 | { |
7469 | as_bad (_("invalid character %s before operand %d"), | |
7470 | output_invalid (*l), | |
7471 | i.operands + 1); | |
7472 | return NULL; | |
7473 | } | |
d02603dc | 7474 | token_start = l; /* After white space. */ |
e68c3d59 | 7475 | while (in_quotes || paren_not_balanced || *l != ',') |
29b0f896 AM |
7476 | { |
7477 | if (*l == END_OF_INSN) | |
7478 | { | |
e68c3d59 JB |
7479 | if (in_quotes) |
7480 | { | |
7481 | as_bad (_("unbalanced double quotes in operand %d."), | |
7482 | i.operands + 1); | |
7483 | return NULL; | |
7484 | } | |
29b0f896 AM |
7485 | if (paren_not_balanced) |
7486 | { | |
98ff9f1c JB |
7487 | know (!intel_syntax); |
7488 | as_bad (_("unbalanced parenthesis in operand %d."), | |
7489 | i.operands + 1); | |
29b0f896 AM |
7490 | return NULL; |
7491 | } | |
7492 | else | |
7493 | break; /* we are done */ | |
7494 | } | |
e68c3d59 JB |
7495 | else if (*l == '\\' && l[1] == '"') |
7496 | ++l; | |
7497 | else if (*l == '"') | |
7498 | in_quotes = !in_quotes; | |
7499 | else if (!in_quotes && !is_operand_char (*l) && !is_space_char (*l)) | |
29b0f896 AM |
7500 | { |
7501 | as_bad (_("invalid character %s in operand %d"), | |
7502 | output_invalid (*l), | |
7503 | i.operands + 1); | |
7504 | return NULL; | |
7505 | } | |
e68c3d59 | 7506 | if (!intel_syntax && !in_quotes) |
29b0f896 AM |
7507 | { |
7508 | if (*l == '(') | |
7509 | ++paren_not_balanced; | |
7510 | if (*l == ')') | |
7511 | --paren_not_balanced; | |
7512 | } | |
29b0f896 AM |
7513 | l++; |
7514 | } | |
7515 | if (l != token_start) | |
7516 | { /* Yes, we've read in another operand. */ | |
7517 | unsigned int operand_ok; | |
7518 | this_operand = i.operands++; | |
7519 | if (i.operands > MAX_OPERANDS) | |
7520 | { | |
7521 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
7522 | MAX_OPERANDS); | |
7523 | return NULL; | |
7524 | } | |
9d46ce34 | 7525 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
7526 | /* Now parse operand adding info to 'i' as we go along. */ |
7527 | END_STRING_AND_SAVE (l); | |
7528 | ||
1286ab78 L |
7529 | if (i.mem_operands > 1) |
7530 | { | |
7531 | as_bad (_("too many memory references for `%s'"), | |
7532 | mnemonic); | |
7533 | return 0; | |
7534 | } | |
7535 | ||
29b0f896 AM |
7536 | if (intel_syntax) |
7537 | operand_ok = | |
7538 | i386_intel_operand (token_start, | |
7539 | intel_float_operand (mnemonic)); | |
7540 | else | |
a7619375 | 7541 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
7542 | |
7543 | RESTORE_END_STRING (l); | |
7544 | if (!operand_ok) | |
7545 | return NULL; | |
7546 | } | |
7547 | else | |
7548 | { | |
7549 | if (expecting_operand) | |
7550 | { | |
7551 | expecting_operand_after_comma: | |
7552 | as_bad (_("expecting operand after ','; got nothing")); | |
7553 | return NULL; | |
7554 | } | |
7555 | if (*l == ',') | |
7556 | { | |
7557 | as_bad (_("expecting operand before ','; got nothing")); | |
7558 | return NULL; | |
7559 | } | |
7560 | } | |
7f3f1ea2 | 7561 | |
29b0f896 AM |
7562 | /* Now *l must be either ',' or END_OF_INSN. */ |
7563 | if (*l == ',') | |
7564 | { | |
7565 | if (*++l == END_OF_INSN) | |
7566 | { | |
7567 | /* Just skip it, if it's \n complain. */ | |
7568 | goto expecting_operand_after_comma; | |
7569 | } | |
7570 | expecting_operand = 1; | |
7571 | } | |
7572 | } | |
7573 | return l; | |
7574 | } | |
7f3f1ea2 | 7575 | |
050dfa73 | 7576 | static void |
783c187b | 7577 | swap_2_operands (unsigned int xchg1, unsigned int xchg2) |
050dfa73 MM |
7578 | { |
7579 | union i386_op temp_op; | |
40fb9820 | 7580 | i386_operand_type temp_type; |
c48dadc9 | 7581 | unsigned int temp_flags; |
050dfa73 | 7582 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 7583 | |
050dfa73 MM |
7584 | temp_type = i.types[xchg2]; |
7585 | i.types[xchg2] = i.types[xchg1]; | |
7586 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
7587 | |
7588 | temp_flags = i.flags[xchg2]; | |
7589 | i.flags[xchg2] = i.flags[xchg1]; | |
7590 | i.flags[xchg1] = temp_flags; | |
7591 | ||
050dfa73 MM |
7592 | temp_op = i.op[xchg2]; |
7593 | i.op[xchg2] = i.op[xchg1]; | |
7594 | i.op[xchg1] = temp_op; | |
c48dadc9 | 7595 | |
050dfa73 MM |
7596 | temp_reloc = i.reloc[xchg2]; |
7597 | i.reloc[xchg2] = i.reloc[xchg1]; | |
7598 | i.reloc[xchg1] = temp_reloc; | |
43234a1e | 7599 | |
c032bc4f JB |
7600 | temp_flags = i.imm_bits[xchg2]; |
7601 | i.imm_bits[xchg2] = i.imm_bits[xchg1]; | |
7602 | i.imm_bits[xchg1] = temp_flags; | |
7603 | ||
6225c532 | 7604 | if (i.mask.reg) |
43234a1e | 7605 | { |
6225c532 JB |
7606 | if (i.mask.operand == xchg1) |
7607 | i.mask.operand = xchg2; | |
7608 | else if (i.mask.operand == xchg2) | |
7609 | i.mask.operand = xchg1; | |
43234a1e | 7610 | } |
a5748e0d | 7611 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 7612 | { |
5273a3cd JB |
7613 | if (i.broadcast.operand == xchg1) |
7614 | i.broadcast.operand = xchg2; | |
7615 | else if (i.broadcast.operand == xchg2) | |
7616 | i.broadcast.operand = xchg1; | |
43234a1e | 7617 | } |
050dfa73 MM |
7618 | } |
7619 | ||
29b0f896 | 7620 | static void |
e3bb37b5 | 7621 | swap_operands (void) |
29b0f896 | 7622 | { |
b7c61d9a | 7623 | switch (i.operands) |
050dfa73 | 7624 | { |
c0f3af97 | 7625 | case 5: |
b7c61d9a | 7626 | case 4: |
4d456e3d | 7627 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 7628 | /* Fall through. */ |
b7c61d9a L |
7629 | case 3: |
7630 | case 2: | |
4d456e3d | 7631 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
7632 | break; |
7633 | default: | |
7634 | abort (); | |
29b0f896 | 7635 | } |
29b0f896 AM |
7636 | |
7637 | if (i.mem_operands == 2) | |
7638 | { | |
5e042380 | 7639 | const reg_entry *temp_seg; |
29b0f896 AM |
7640 | temp_seg = i.seg[0]; |
7641 | i.seg[0] = i.seg[1]; | |
7642 | i.seg[1] = temp_seg; | |
7643 | } | |
7644 | } | |
252b5132 | 7645 | |
29b0f896 AM |
7646 | /* Try to ensure constant immediates are represented in the smallest |
7647 | opcode possible. */ | |
7648 | static void | |
e3bb37b5 | 7649 | optimize_imm (void) |
29b0f896 AM |
7650 | { |
7651 | char guess_suffix = 0; | |
7652 | int op; | |
252b5132 | 7653 | |
29b0f896 AM |
7654 | if (i.suffix) |
7655 | guess_suffix = i.suffix; | |
7656 | else if (i.reg_operands) | |
7657 | { | |
7658 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
7659 | We can't do this properly yet, i.e. excluding special register |
7660 | instances, but the following works for instructions with | |
7661 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 7662 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
7663 | if (i.types[op].bitfield.class != Reg) |
7664 | continue; | |
7665 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 7666 | { |
40fb9820 L |
7667 | guess_suffix = BYTE_MNEM_SUFFIX; |
7668 | break; | |
7669 | } | |
bab6aec1 | 7670 | else if (i.types[op].bitfield.word) |
252b5132 | 7671 | { |
40fb9820 L |
7672 | guess_suffix = WORD_MNEM_SUFFIX; |
7673 | break; | |
7674 | } | |
bab6aec1 | 7675 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
7676 | { |
7677 | guess_suffix = LONG_MNEM_SUFFIX; | |
7678 | break; | |
7679 | } | |
bab6aec1 | 7680 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
7681 | { |
7682 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 7683 | break; |
252b5132 | 7684 | } |
29b0f896 | 7685 | } |
f79d55e1 JB |
7686 | else if ((flag_code == CODE_16BIT) |
7687 | ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W))) | |
29b0f896 | 7688 | guess_suffix = WORD_MNEM_SUFFIX; |
fb1c1058 JB |
7689 | else if (flag_code != CODE_64BIT |
7690 | || (!(i.prefix[REX_PREFIX] & REX_W) | |
7691 | /* A more generic (but also more involved) way of dealing | |
7692 | with the special case(s) would be to go look for | |
7693 | DefaultSize attributes on any of the templates. */ | |
d3b01414 | 7694 | && current_templates.start->mnem_off != MN_push)) |
5cc00775 | 7695 | guess_suffix = LONG_MNEM_SUFFIX; |
29b0f896 AM |
7696 | |
7697 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 7698 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
7699 | { |
7700 | switch (i.op[op].imms->X_op) | |
252b5132 | 7701 | { |
29b0f896 AM |
7702 | case O_constant: |
7703 | /* If a suffix is given, this operand may be shortened. */ | |
7704 | switch (guess_suffix) | |
252b5132 | 7705 | { |
29b0f896 | 7706 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
7707 | i.types[op].bitfield.imm32 = 1; |
7708 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
7709 | break; |
7710 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
7711 | i.types[op].bitfield.imm16 = 1; |
7712 | i.types[op].bitfield.imm32 = 1; | |
7713 | i.types[op].bitfield.imm32s = 1; | |
7714 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
7715 | break; |
7716 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
7717 | i.types[op].bitfield.imm8 = 1; |
7718 | i.types[op].bitfield.imm8s = 1; | |
7719 | i.types[op].bitfield.imm16 = 1; | |
7720 | i.types[op].bitfield.imm32 = 1; | |
7721 | i.types[op].bitfield.imm32s = 1; | |
7722 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 7723 | break; |
252b5132 | 7724 | } |
252b5132 | 7725 | |
29b0f896 AM |
7726 | /* If this operand is at most 16 bits, convert it |
7727 | to a signed 16 bit number before trying to see | |
7728 | whether it will fit in an even smaller size. | |
7729 | This allows a 16-bit operand such as $0xffe0 to | |
7730 | be recognised as within Imm8S range. */ | |
40fb9820 | 7731 | if ((i.types[op].bitfield.imm16) |
7e96fb68 | 7732 | && fits_in_unsigned_word (i.op[op].imms->X_add_number)) |
252b5132 | 7733 | { |
87ed972d JB |
7734 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
7735 | ^ 0x8000) - 0x8000); | |
29b0f896 | 7736 | } |
a28def75 L |
7737 | #ifdef BFD64 |
7738 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 7739 | if ((i.types[op].bitfield.imm32) |
7e96fb68 | 7740 | && fits_in_unsigned_long (i.op[op].imms->X_add_number)) |
29b0f896 AM |
7741 | { |
7742 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
7743 | ^ ((offsetT) 1 << 31)) | |
7744 | - ((offsetT) 1 << 31)); | |
7745 | } | |
a28def75 | 7746 | #endif |
40fb9820 | 7747 | i.types[op] |
c6fb90c8 L |
7748 | = operand_type_or (i.types[op], |
7749 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 7750 | |
29b0f896 AM |
7751 | /* We must avoid matching of Imm32 templates when 64bit |
7752 | only immediate is available. */ | |
7753 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 7754 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 7755 | break; |
252b5132 | 7756 | |
29b0f896 AM |
7757 | case O_absent: |
7758 | case O_register: | |
7759 | abort (); | |
7760 | ||
7761 | /* Symbols and expressions. */ | |
7762 | default: | |
9cd96992 JB |
7763 | /* Convert symbolic operand to proper sizes for matching, but don't |
7764 | prevent matching a set of insns that only supports sizes other | |
7765 | than those matching the insn suffix. */ | |
7766 | { | |
40fb9820 | 7767 | i386_operand_type mask, allowed; |
d3b01414 | 7768 | const insn_template *t = current_templates.start; |
9cd96992 | 7769 | |
0dfbf9d7 | 7770 | operand_type_set (&mask, 0); |
9cd96992 JB |
7771 | switch (guess_suffix) |
7772 | { | |
7773 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
7774 | mask.bitfield.imm64 = 1; |
7775 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
7776 | break; |
7777 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 7778 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
7779 | break; |
7780 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 7781 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
7782 | break; |
7783 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 7784 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
7785 | break; |
7786 | default: | |
9cd96992 JB |
7787 | break; |
7788 | } | |
8f0212ac JB |
7789 | |
7790 | allowed = operand_type_and (t->operand_types[op], mask); | |
d3b01414 | 7791 | while (++t < current_templates.end) |
8f0212ac JB |
7792 | { |
7793 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
7794 | allowed = operand_type_and (allowed, mask); | |
7795 | } | |
7796 | ||
0dfbf9d7 | 7797 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 7798 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 7799 | } |
29b0f896 | 7800 | break; |
252b5132 | 7801 | } |
29b0f896 AM |
7802 | } |
7803 | } | |
47926f60 | 7804 | |
29b0f896 | 7805 | /* Try to use the smallest displacement type too. */ |
0de704b9 JB |
7806 | static bool |
7807 | optimize_disp (const insn_template *t) | |
29b0f896 | 7808 | { |
0de704b9 | 7809 | unsigned int op; |
3e73aa7c | 7810 | |
0de704b9 JB |
7811 | if (!want_disp32 (t) |
7812 | && (!t->opcode_modifier.jump | |
7813 | || i.jumpabsolute || i.types[0].bitfield.baseindex)) | |
7814 | { | |
7815 | for (op = 0; op < i.operands; ++op) | |
7816 | { | |
7817 | const expressionS *exp = i.op[op].disps; | |
7818 | ||
7819 | if (!operand_type_check (i.types[op], disp)) | |
7820 | continue; | |
7821 | ||
7822 | if (exp->X_op != O_constant) | |
7823 | continue; | |
7824 | ||
7825 | /* Since displacement is signed extended to 64bit, don't allow | |
7826 | disp32 if it is out of range. */ | |
7827 | if (fits_in_signed_long (exp->X_add_number)) | |
7828 | continue; | |
7829 | ||
7830 | i.types[op].bitfield.disp32 = 0; | |
7831 | if (i.types[op].bitfield.baseindex) | |
7832 | { | |
7833 | as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"), | |
7834 | (uint64_t) exp->X_add_number); | |
7835 | return false; | |
7836 | } | |
7837 | } | |
7838 | } | |
7839 | ||
7840 | /* Don't optimize displacement for movabs since it only takes 64bit | |
7841 | displacement. */ | |
7842 | if (i.disp_encoding > disp_encoding_8bit | |
7843 | || (flag_code == CODE_64BIT && t->mnem_off == MN_movabs)) | |
7844 | return true; | |
7845 | ||
7846 | for (op = i.operands; op-- > 0;) | |
40fb9820 | 7847 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 7848 | { |
b300c311 | 7849 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 7850 | { |
91d6fa6a | 7851 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 7852 | |
91d6fa6a | 7853 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 7854 | { |
2f2be86b JB |
7855 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7856 | i.op[op].disps = NULL; | |
b300c311 | 7857 | i.disp_operands--; |
f185acdd JB |
7858 | continue; |
7859 | } | |
7860 | ||
7861 | if (i.types[op].bitfield.disp16 | |
cd613c1f | 7862 | && fits_in_unsigned_word (op_disp)) |
f185acdd JB |
7863 | { |
7864 | /* If this operand is at most 16 bits, convert | |
7865 | to a signed 16 bit number and don't use 64bit | |
7866 | displacement. */ | |
7867 | op_disp = ((op_disp ^ 0x8000) - 0x8000); | |
7868 | i.types[op].bitfield.disp64 = 0; | |
b300c311 | 7869 | } |
f185acdd | 7870 | |
28a167a4 | 7871 | #ifdef BFD64 |
a50187b2 | 7872 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ |
a775efc8 JB |
7873 | if ((flag_code != CODE_64BIT |
7874 | ? i.types[op].bitfield.disp32 | |
0de704b9 JB |
7875 | : want_disp32 (t) |
7876 | && (!t->opcode_modifier.jump | |
a775efc8 | 7877 | || i.jumpabsolute || i.types[op].bitfield.baseindex)) |
a50187b2 | 7878 | && fits_in_unsigned_long (op_disp)) |
b300c311 | 7879 | { |
a50187b2 JB |
7880 | /* If this operand is at most 32 bits, convert |
7881 | to a signed 32 bit number and don't use 64bit | |
7882 | displacement. */ | |
7883 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
7884 | i.types[op].bitfield.disp64 = 0; | |
7885 | i.types[op].bitfield.disp32 = 1; | |
7886 | } | |
28a167a4 | 7887 | |
a50187b2 JB |
7888 | if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp)) |
7889 | { | |
7890 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 7891 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 7892 | } |
28a167a4 | 7893 | #endif |
40fb9820 | 7894 | if ((i.types[op].bitfield.disp32 |
40fb9820 | 7895 | || i.types[op].bitfield.disp16) |
b5014f7a | 7896 | && fits_in_disp8 (op_disp)) |
40fb9820 | 7897 | i.types[op].bitfield.disp8 = 1; |
77c59789 JB |
7898 | |
7899 | i.op[op].disps->X_add_number = op_disp; | |
252b5132 | 7900 | } |
67a4f2b7 AO |
7901 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
7902 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
7903 | { | |
7904 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
7905 | i.op[op].disps, 0, i.reloc[op]); | |
2f2be86b | 7906 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
67a4f2b7 AO |
7907 | } |
7908 | else | |
b300c311 | 7909 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 7910 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 7911 | } |
0de704b9 JB |
7912 | |
7913 | return true; | |
29b0f896 AM |
7914 | } |
7915 | ||
4a1b91ea L |
7916 | /* Return 1 if there is a match in broadcast bytes between operand |
7917 | GIVEN and instruction template T. */ | |
7918 | ||
7919 | static INLINE int | |
7920 | match_broadcast_size (const insn_template *t, unsigned int given) | |
7921 | { | |
7922 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
7923 | && i.types[given].bitfield.byte) | |
7924 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
7925 | && i.types[given].bitfield.word) | |
7926 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
7927 | && i.types[given].bitfield.dword) | |
7928 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
7929 | && i.types[given].bitfield.qword)); | |
7930 | } | |
7931 | ||
6c30d220 L |
7932 | /* Check if operands are valid for the instruction. */ |
7933 | ||
7934 | static int | |
7935 | check_VecOperands (const insn_template *t) | |
7936 | { | |
43234a1e | 7937 | unsigned int op; |
e2195274 | 7938 | i386_cpu_flags cpu; |
e2195274 JB |
7939 | |
7940 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
7941 | any one operand are implicity requiring AVX512VL support if the actual | |
7942 | operand size is YMMword or XMMword. Since this function runs after | |
a61cb9db L |
7943 | template matching, there's no need to check for YMMword/XMMword in |
7944 | the template. */ | |
734dfd1c | 7945 | cpu = cpu_flags_and (cpu_flags_from_attr (t->cpu), avx512); |
e2195274 | 7946 | if (!cpu_flags_all_zero (&cpu) |
734dfd1c | 7947 | && !is_cpu (t, CpuAVX512VL) |
a6f3add0 | 7948 | && !cpu_arch_flags.bitfield.cpuavx512vl |
6177c84d | 7949 | && (!t->opcode_modifier.vex || need_evex_encoding (t))) |
e2195274 JB |
7950 | { |
7951 | for (op = 0; op < t->operands; ++op) | |
7952 | { | |
7953 | if (t->operand_types[op].bitfield.zmmword | |
7954 | && (i.types[op].bitfield.ymmword | |
7955 | || i.types[op].bitfield.xmmword)) | |
7956 | { | |
54294d73 | 7957 | i.error = operand_size_mismatch; |
e2195274 JB |
7958 | return 1; |
7959 | } | |
7960 | } | |
7961 | } | |
43234a1e | 7962 | |
22c36940 JB |
7963 | /* Somewhat similarly, templates specifying both AVX and AVX2 are |
7964 | requiring AVX2 support if the actual operand size is YMMword. */ | |
a5e91879 | 7965 | if (maybe_cpu (t, CpuAVX) && maybe_cpu (t, CpuAVX2) |
22c36940 JB |
7966 | && !cpu_arch_flags.bitfield.cpuavx2) |
7967 | { | |
7968 | for (op = 0; op < t->operands; ++op) | |
7969 | { | |
7970 | if (t->operand_types[op].bitfield.xmmword | |
7971 | && i.types[op].bitfield.ymmword) | |
7972 | { | |
54294d73 | 7973 | i.error = operand_size_mismatch; |
22c36940 JB |
7974 | return 1; |
7975 | } | |
7976 | } | |
7977 | } | |
7978 | ||
6c30d220 | 7979 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 7980 | if (!t->opcode_modifier.sib |
6c30d220 | 7981 | && i.index_reg |
1b54b8d7 JB |
7982 | && (i.index_reg->reg_type.bitfield.xmmword |
7983 | || i.index_reg->reg_type.bitfield.ymmword | |
7984 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
7985 | { |
7986 | i.error = unsupported_vector_index_register; | |
7987 | return 1; | |
7988 | } | |
7989 | ||
ad8ecc81 | 7990 | /* Check if default mask is allowed. */ |
255571cd | 7991 | if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK |
6225c532 | 7992 | && (!i.mask.reg || i.mask.reg->reg_num == 0)) |
ad8ecc81 MZ |
7993 | { |
7994 | i.error = no_default_mask; | |
7995 | return 1; | |
7996 | } | |
7997 | ||
7bab8ab5 JB |
7998 | /* For VSIB byte, we need a vector register for index, and all vector |
7999 | registers must be distinct. */ | |
260cd341 | 8000 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
8001 | { |
8002 | if (!i.index_reg | |
63112cd6 | 8003 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 8004 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 8005 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 8006 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 8007 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 8008 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
8009 | { |
8010 | i.error = invalid_vsib_address; | |
8011 | return 1; | |
8012 | } | |
8013 | ||
6225c532 JB |
8014 | gas_assert (i.reg_operands == 2 || i.mask.reg); |
8015 | if (i.reg_operands == 2 && !i.mask.reg) | |
43234a1e | 8016 | { |
3528c362 | 8017 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
8018 | gas_assert (i.types[0].bitfield.xmmword |
8019 | || i.types[0].bitfield.ymmword); | |
3528c362 | 8020 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
8021 | gas_assert (i.types[2].bitfield.xmmword |
8022 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
8023 | if (operand_check == check_none) |
8024 | return 0; | |
8025 | if (register_number (i.op[0].regs) | |
8026 | != register_number (i.index_reg) | |
8027 | && register_number (i.op[2].regs) | |
8028 | != register_number (i.index_reg) | |
8029 | && register_number (i.op[0].regs) | |
8030 | != register_number (i.op[2].regs)) | |
8031 | return 0; | |
8032 | if (operand_check == check_error) | |
8033 | { | |
8034 | i.error = invalid_vector_register_set; | |
8035 | return 1; | |
8036 | } | |
8037 | as_warn (_("mask, index, and destination registers should be distinct")); | |
8038 | } | |
6225c532 | 8039 | else if (i.reg_operands == 1 && i.mask.reg) |
8444f82a | 8040 | { |
3528c362 | 8041 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
8042 | && (i.types[1].bitfield.xmmword |
8043 | || i.types[1].bitfield.ymmword | |
8044 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
8045 | && (register_number (i.op[1].regs) |
8046 | == register_number (i.index_reg))) | |
8047 | { | |
8048 | if (operand_check == check_error) | |
8049 | { | |
8050 | i.error = invalid_vector_register_set; | |
8051 | return 1; | |
8052 | } | |
8053 | if (operand_check != check_none) | |
8054 | as_warn (_("index and destination registers should be distinct")); | |
8055 | } | |
8056 | } | |
43234a1e | 8057 | } |
7bab8ab5 | 8058 | |
fc141319 L |
8059 | /* For AMX instructions with 3 TMM register operands, all operands |
8060 | must be distinct. */ | |
8061 | if (i.reg_operands == 3 | |
8062 | && t->operand_types[0].bitfield.tmmword | |
8063 | && (i.op[0].regs == i.op[1].regs | |
8064 | || i.op[0].regs == i.op[2].regs | |
8065 | || i.op[1].regs == i.op[2].regs)) | |
8066 | { | |
8067 | i.error = invalid_tmm_register_set; | |
8068 | return 1; | |
260cd341 LC |
8069 | } |
8070 | ||
0cc78721 CL |
8071 | /* For some special instructions require that destination must be distinct |
8072 | from source registers. */ | |
255571cd | 8073 | if (t->opcode_modifier.operandconstraint == DISTINCT_DEST) |
0cc78721 CL |
8074 | { |
8075 | unsigned int dest_reg = i.operands - 1; | |
8076 | ||
8077 | know (i.operands >= 3); | |
8078 | ||
8079 | /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */ | |
8080 | if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs | |
8081 | || (i.reg_operands > 2 | |
8082 | && i.op[dest_reg - 2].regs == i.op[dest_reg].regs)) | |
8083 | { | |
8084 | i.error = invalid_dest_and_src_register_set; | |
8085 | return 1; | |
8086 | } | |
8087 | } | |
8088 | ||
43234a1e L |
8089 | /* Check if broadcast is supported by the instruction and is applied |
8090 | to the memory operand. */ | |
a5748e0d | 8091 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 8092 | { |
8e6e0792 | 8093 | i386_operand_type type, overlap; |
43234a1e L |
8094 | |
8095 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 8096 | and its broadcast bytes match the memory operand. */ |
5273a3cd | 8097 | op = i.broadcast.operand; |
8e6e0792 | 8098 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 8099 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 8100 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 8101 | && !match_broadcast_size (t, op))) |
43234a1e L |
8102 | { |
8103 | bad_broadcast: | |
8104 | i.error = unsupported_broadcast; | |
8105 | return 1; | |
8106 | } | |
8e6e0792 JB |
8107 | |
8108 | operand_type_set (&type, 0); | |
a5748e0d | 8109 | switch (get_broadcast_bytes (t, false)) |
8e6e0792 | 8110 | { |
4a1b91ea L |
8111 | case 2: |
8112 | type.bitfield.word = 1; | |
8113 | break; | |
8114 | case 4: | |
8115 | type.bitfield.dword = 1; | |
8116 | break; | |
8e6e0792 JB |
8117 | case 8: |
8118 | type.bitfield.qword = 1; | |
8119 | break; | |
8120 | case 16: | |
8121 | type.bitfield.xmmword = 1; | |
8122 | break; | |
8123 | case 32: | |
4fc85f37 JB |
8124 | if (vector_size < VSZ256) |
8125 | goto bad_broadcast; | |
8e6e0792 JB |
8126 | type.bitfield.ymmword = 1; |
8127 | break; | |
8128 | case 64: | |
4fc85f37 JB |
8129 | if (vector_size < VSZ512) |
8130 | goto bad_broadcast; | |
8e6e0792 JB |
8131 | type.bitfield.zmmword = 1; |
8132 | break; | |
8133 | default: | |
8134 | goto bad_broadcast; | |
8135 | } | |
8136 | ||
8137 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
8138 | if (t->operand_types[op].bitfield.class == RegSIMD |
8139 | && t->operand_types[op].bitfield.byte | |
8140 | + t->operand_types[op].bitfield.word | |
8141 | + t->operand_types[op].bitfield.dword | |
8142 | + t->operand_types[op].bitfield.qword > 1) | |
8143 | { | |
8144 | overlap.bitfield.xmmword = 0; | |
8145 | overlap.bitfield.ymmword = 0; | |
8146 | overlap.bitfield.zmmword = 0; | |
8147 | } | |
8e6e0792 JB |
8148 | if (operand_type_all_zero (&overlap)) |
8149 | goto bad_broadcast; | |
8150 | ||
9c19e9ec | 8151 | if (t->opcode_modifier.checkoperandsize) |
8e6e0792 JB |
8152 | { |
8153 | unsigned int j; | |
8154 | ||
e2195274 | 8155 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
8156 | for (j = 0; j < i.operands; ++j) |
8157 | { | |
8158 | if (j != op | |
8159 | && !operand_type_register_match(i.types[j], | |
8160 | t->operand_types[j], | |
8161 | type, | |
8162 | t->operand_types[op])) | |
8163 | goto bad_broadcast; | |
8164 | } | |
8165 | } | |
43234a1e L |
8166 | } |
8167 | /* If broadcast is supported in this instruction, we need to check if | |
8168 | operand of one-element size isn't specified without broadcast. */ | |
8169 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
8170 | { | |
8171 | /* Find memory operand. */ | |
8172 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 8173 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
8174 | break; |
8175 | gas_assert (op < i.operands); | |
8176 | /* Check size of the memory operand. */ | |
4a1b91ea | 8177 | if (match_broadcast_size (t, op)) |
43234a1e L |
8178 | { |
8179 | i.error = broadcast_needed; | |
8180 | return 1; | |
8181 | } | |
8182 | } | |
c39e5b26 JB |
8183 | else |
8184 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
8185 | |
8186 | /* Check if requested masking is supported. */ | |
6225c532 | 8187 | if (i.mask.reg) |
43234a1e | 8188 | { |
b1c79256 | 8189 | if (!t->opcode_modifier.masking) |
ae2387fe | 8190 | { |
b1c79256 JB |
8191 | i.error = unsupported_masking; |
8192 | return 1; | |
8193 | } | |
8194 | ||
8195 | /* Common rules for masking: | |
8196 | - mask register destinations permit only zeroing-masking, without | |
8197 | that actually being expressed by a {z} operand suffix or EVEX.z, | |
8198 | - memory destinations allow only merging-masking, | |
8199 | - scatter/gather insns (i.e. ones using vSIB) only allow merging- | |
8200 | masking. */ | |
8201 | if (i.mask.zeroing | |
8202 | && (t->operand_types[t->operands - 1].bitfield.class == RegMask | |
8203 | || (i.flags[t->operands - 1] & Operand_Mem) | |
8204 | || t->opcode_modifier.sib)) | |
8205 | { | |
8206 | i.error = unsupported_masking; | |
8207 | return 1; | |
ae2387fe | 8208 | } |
43234a1e L |
8209 | } |
8210 | ||
8211 | /* Check if masking is applied to dest operand. */ | |
6225c532 | 8212 | if (i.mask.reg && (i.mask.operand != i.operands - 1)) |
43234a1e L |
8213 | { |
8214 | i.error = mask_not_on_destination; | |
8215 | return 1; | |
8216 | } | |
8217 | ||
43234a1e | 8218 | /* Check RC/SAE. */ |
ca5312a2 | 8219 | if (i.rounding.type != rc_none) |
43234a1e | 8220 | { |
a80195f1 | 8221 | if (!t->opcode_modifier.sae |
cf665fee JB |
8222 | || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding) |
8223 | || i.mem_operands) | |
43234a1e L |
8224 | { |
8225 | i.error = unsupported_rc_sae; | |
8226 | return 1; | |
8227 | } | |
cf665fee JB |
8228 | |
8229 | /* Non-EVEX.LIG forms need to have a ZMM register as at least one | |
8230 | operand. */ | |
8231 | if (t->opcode_modifier.evex != EVEXLIG) | |
7bab8ab5 | 8232 | { |
cf665fee JB |
8233 | for (op = 0; op < t->operands; ++op) |
8234 | if (i.types[op].bitfield.zmmword) | |
8235 | break; | |
8236 | if (op >= t->operands) | |
8237 | { | |
8238 | i.error = operand_size_mismatch; | |
8239 | return 1; | |
8240 | } | |
7bab8ab5 | 8241 | } |
6c30d220 L |
8242 | } |
8243 | ||
da4977e0 | 8244 | /* Check the special Imm4 cases; must be the first operand. */ |
eea43579 | 8245 | if ((is_cpu (t, CpuXOP) && t->operands == 5) |
ec6b11e7 JB |
8246 | || (t->opcode_space == SPACE_0F3A |
8247 | && (t->base_opcode | 3) == 0x0b | |
8248 | && is_cpu (t, CpuAPX_F))) | |
da4977e0 JB |
8249 | { |
8250 | if (i.op[0].imms->X_op != O_constant | |
8251 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
8252 | { | |
8253 | i.error = bad_imm4; | |
8254 | return 1; | |
8255 | } | |
8256 | ||
8257 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
eea43579 JB |
8258 | if (t->operands == 5) |
8259 | operand_type_set (&i.types[0], 0); | |
da4977e0 JB |
8260 | } |
8261 | ||
43234a1e | 8262 | /* Check vector Disp8 operand. */ |
b5014f7a | 8263 | if (t->opcode_modifier.disp8memshift |
a6f3add0 | 8264 | && (!t->opcode_modifier.vex |
6177c84d | 8265 | || need_evex_encoding (t)) |
1a42a9fe | 8266 | && i.disp_encoding <= disp_encoding_8bit) |
43234a1e | 8267 | { |
9b345ce8 | 8268 | if (i.broadcast.type || i.broadcast.bytes) |
4a1b91ea | 8269 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 8270 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 8271 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
8272 | else |
8273 | { | |
125ff819 | 8274 | const i386_operand_type *type = NULL, *fallback = NULL; |
7091c612 JB |
8275 | |
8276 | i.memshift = 0; | |
8277 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 8278 | if (i.flags[op] & Operand_Mem) |
7091c612 | 8279 | { |
4174bfff JB |
8280 | if (t->opcode_modifier.evex == EVEXLIG) |
8281 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
8282 | else if (t->operand_types[op].bitfield.xmmword | |
8283 | + t->operand_types[op].bitfield.ymmword | |
8284 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
8285 | type = &t->operand_types[op]; |
8286 | else if (!i.types[op].bitfield.unspecified) | |
8287 | type = &i.types[op]; | |
125ff819 JB |
8288 | else /* Ambiguities get resolved elsewhere. */ |
8289 | fallback = &t->operand_types[op]; | |
7091c612 | 8290 | } |
3528c362 | 8291 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 8292 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
8293 | { |
8294 | if (i.types[op].bitfield.zmmword) | |
8295 | i.memshift = 6; | |
8296 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
8297 | i.memshift = 5; | |
8298 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
8299 | i.memshift = 4; | |
8300 | } | |
8301 | ||
125ff819 JB |
8302 | if (!type && !i.memshift) |
8303 | type = fallback; | |
7091c612 JB |
8304 | if (type) |
8305 | { | |
8306 | if (type->bitfield.zmmword) | |
8307 | i.memshift = 6; | |
8308 | else if (type->bitfield.ymmword) | |
8309 | i.memshift = 5; | |
8310 | else if (type->bitfield.xmmword) | |
8311 | i.memshift = 4; | |
8312 | } | |
8313 | ||
8314 | /* For the check in fits_in_disp8(). */ | |
8315 | if (i.memshift == 0) | |
8316 | i.memshift = -1; | |
8317 | } | |
43234a1e L |
8318 | |
8319 | for (op = 0; op < i.operands; op++) | |
8320 | if (operand_type_check (i.types[op], disp) | |
8321 | && i.op[op].disps->X_op == O_constant) | |
8322 | { | |
b5014f7a | 8323 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 8324 | { |
b5014f7a JB |
8325 | i.types[op].bitfield.disp8 = 1; |
8326 | return 0; | |
43234a1e | 8327 | } |
b5014f7a | 8328 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
8329 | } |
8330 | } | |
b5014f7a JB |
8331 | |
8332 | i.memshift = 0; | |
43234a1e | 8333 | |
6c30d220 L |
8334 | return 0; |
8335 | } | |
8336 | ||
da4977e0 | 8337 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
8338 | |
8339 | static int | |
da4977e0 | 8340 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 8341 | { |
e346d50a | 8342 | if (i.encoding == encoding_error) |
da4977e0 JB |
8343 | { |
8344 | i.error = unsupported; | |
8345 | return 1; | |
8346 | } | |
8347 | ||
4fc85f37 JB |
8348 | /* Vector size restrictions. */ |
8349 | if ((vector_size < VSZ512 | |
fa88a361 | 8350 | && t->opcode_modifier.evex == EVEX512) |
4fc85f37 JB |
8351 | || (vector_size < VSZ256 |
8352 | && (t->opcode_modifier.evex == EVEX256 | |
fa88a361 | 8353 | || t->opcode_modifier.vex == VEX256))) |
4fc85f37 | 8354 | { |
54294d73 | 8355 | i.error = unsupported_vector_size; |
4fc85f37 JB |
8356 | return 1; |
8357 | } | |
8358 | ||
eb3f3841 | 8359 | switch (i.encoding) |
43234a1e | 8360 | { |
eb3f3841 JB |
8361 | case encoding_default: |
8362 | break; | |
8363 | ||
8364 | case encoding_vex: | |
8365 | case encoding_vex3: | |
8366 | /* This instruction must be encoded with VEX prefix. */ | |
8367 | if (!t->opcode_modifier.vex) | |
8368 | { | |
8369 | i.error = no_vex_encoding; | |
8370 | return 1; | |
8371 | } | |
8372 | break; | |
8373 | ||
8374 | case encoding_evex: | |
8375 | case encoding_evex512: | |
86fa6981 | 8376 | /* This instruction must be encoded with EVEX prefix. */ |
706ce984 | 8377 | if (!t->opcode_modifier.evex) |
86fa6981 | 8378 | { |
54294d73 | 8379 | i.error = no_evex_encoding; |
86fa6981 L |
8380 | return 1; |
8381 | } | |
eb3f3841 | 8382 | break; |
43234a1e | 8383 | |
eb3f3841 JB |
8384 | case encoding_egpr: |
8385 | /* This instruction must be encoded with REX2 or EVEX prefix. */ | |
8386 | if (t->opcode_modifier.vex && !t->opcode_modifier.evex) | |
86fa6981 | 8387 | { |
eb3f3841 | 8388 | i.error = no_evex_encoding; |
86fa6981 L |
8389 | return 1; |
8390 | } | |
eb3f3841 JB |
8391 | break; |
8392 | ||
8393 | default: | |
8394 | abort (); | |
86fa6981 | 8395 | } |
a683cc34 | 8396 | |
a683cc34 SP |
8397 | return 0; |
8398 | } | |
8399 | ||
80d61d8d CL |
8400 | /* Check if Egprs operands are valid for the instruction. */ |
8401 | ||
8402 | static bool | |
8403 | check_EgprOperands (const insn_template *t) | |
8404 | { | |
8405 | if (!t->opcode_modifier.noegpr) | |
192781a3 | 8406 | return false; |
80d61d8d CL |
8407 | |
8408 | for (unsigned int op = 0; op < i.operands; op++) | |
8409 | { | |
8410 | if (i.types[op].bitfield.class != Reg) | |
8411 | continue; | |
8412 | ||
8413 | if (i.op[op].regs->reg_flags & RegRex2) | |
8414 | { | |
8415 | i.error = register_type_mismatch; | |
192781a3 | 8416 | return true; |
80d61d8d CL |
8417 | } |
8418 | } | |
8419 | ||
8420 | if ((i.index_reg && (i.index_reg->reg_flags & RegRex2)) | |
8421 | || (i.base_reg && (i.base_reg->reg_flags & RegRex2))) | |
8422 | { | |
8423 | i.error = unsupported_EGPR_for_addressing; | |
192781a3 | 8424 | return true; |
80d61d8d CL |
8425 | } |
8426 | ||
8427 | /* Check if pseudo prefix {rex2} is valid. */ | |
ebe82bfd | 8428 | if (i.rex2_encoding && !t->opcode_modifier.sse2avx) |
80d61d8d CL |
8429 | { |
8430 | i.error = invalid_pseudo_prefix; | |
192781a3 | 8431 | return true; |
80d61d8d CL |
8432 | } |
8433 | ||
192781a3 | 8434 | return false; |
80d61d8d CL |
8435 | } |
8436 | ||
08a98d4c MZ |
8437 | /* Check if APX operands are valid for the instruction. */ |
8438 | static bool | |
8439 | check_APX_operands (const insn_template *t) | |
8440 | { | |
8441 | /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers. | |
8442 | */ | |
8443 | switch (t->mnem_off) | |
8444 | { | |
8445 | case MN_pop2: | |
8446 | case MN_pop2p: | |
8447 | if (register_number (i.op[0].regs) == register_number (i.op[1].regs)) | |
8448 | { | |
8449 | i.error = invalid_dest_register_set; | |
8450 | return 1; | |
8451 | } | |
8452 | /* fall through */ | |
8453 | case MN_push2: | |
8454 | case MN_push2p: | |
8455 | if (register_number (i.op[0].regs) == 4 | |
8456 | || register_number (i.op[1].regs) == 4) | |
8457 | { | |
8458 | i.error = unsupported_rsp_register; | |
8459 | return 1; | |
8460 | } | |
8461 | break; | |
8462 | } | |
8463 | return 0; | |
8464 | } | |
8465 | ||
6967f19d HL |
8466 | /* Check if the instruction use the REX registers or REX prefix. */ |
8467 | static bool | |
8468 | check_Rex_required (void) | |
8469 | { | |
8470 | for (unsigned int op = 0; op < i.operands; op++) | |
8471 | { | |
8472 | if (i.types[op].bitfield.class != Reg) | |
8473 | continue; | |
8474 | ||
8475 | if (i.op[op].regs->reg_flags & (RegRex | RegRex64)) | |
8476 | return true; | |
8477 | } | |
8478 | ||
8479 | if ((i.index_reg && (i.index_reg->reg_flags & (RegRex | RegRex64))) | |
8480 | || (i.base_reg && (i.base_reg->reg_flags & (RegRex | RegRex64)))) | |
8481 | return true; | |
8482 | ||
8483 | /* Check pseudo prefix {rex} are valid. */ | |
8484 | return i.rex_encoding; | |
8485 | } | |
8486 | ||
8487 | /* Optimize APX NDD insns to legacy insns. */ | |
8488 | static unsigned int | |
8489 | can_convert_NDD_to_legacy (const insn_template *t) | |
8490 | { | |
8491 | unsigned int match_dest_op = ~0; | |
8492 | ||
dd74a603 | 8493 | if (!i.has_nf && i.reg_operands >= 2) |
6967f19d HL |
8494 | { |
8495 | unsigned int dest = i.operands - 1; | |
8496 | unsigned int src1 = i.operands - 2; | |
8497 | unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0; | |
8498 | ||
8499 | if (i.types[src1].bitfield.class == Reg | |
8500 | && i.op[src1].regs == i.op[dest].regs) | |
8501 | match_dest_op = src1; | |
8502 | /* If the first operand is the same as the third operand, | |
8503 | these instructions need to support the ability to commutative | |
8504 | the first two operands and still not change the semantics in order | |
8505 | to be optimized. */ | |
8506 | else if (optimize > 1 | |
8507 | && t->opcode_modifier.commutative | |
8508 | && i.types[src2].bitfield.class == Reg | |
8509 | && i.op[src2].regs == i.op[dest].regs) | |
8510 | match_dest_op = src2; | |
8511 | } | |
8512 | return match_dest_op; | |
8513 | } | |
8514 | ||
7b94647a JB |
8515 | /* Helper function for the progress() macro in match_template(). */ |
8516 | static INLINE enum i386_error progress (enum i386_error new, | |
8517 | enum i386_error last, | |
8518 | unsigned int line, unsigned int *line_p) | |
8519 | { | |
8520 | if (line <= *line_p) | |
8521 | return last; | |
8522 | *line_p = line; | |
8523 | return new; | |
8524 | } | |
8525 | ||
d3ce72d0 | 8526 | static const insn_template * |
83b16ac6 | 8527 | match_template (char mnem_suffix) |
29b0f896 AM |
8528 | { |
8529 | /* Points to template once we've found it. */ | |
d3ce72d0 | 8530 | const insn_template *t; |
40fb9820 | 8531 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 8532 | i386_operand_type overlap4; |
29b0f896 | 8533 | unsigned int found_reverse_match; |
40fb9820 | 8534 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 8535 | int addr_prefix_disp; |
7b94647a JB |
8536 | unsigned int j, size_match, check_register, errline = __LINE__; |
8537 | enum i386_error specific_error = number_of_operands_mismatch; | |
8538 | #define progress(err) progress (err, specific_error, __LINE__, &errline) | |
29b0f896 | 8539 | |
c0f3af97 L |
8540 | #if MAX_OPERANDS != 5 |
8541 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
8542 | #endif |
8543 | ||
29b0f896 | 8544 | found_reverse_match = 0; |
539e75ad | 8545 | addr_prefix_disp = -1; |
40fb9820 | 8546 | |
d3b01414 | 8547 | for (t = current_templates.start; t < current_templates.end; t++) |
29b0f896 | 8548 | { |
539e75ad | 8549 | addr_prefix_disp = -1; |
dbbc8b7e | 8550 | found_reverse_match = 0; |
539e75ad | 8551 | |
7b94647a | 8552 | /* Must have right number of operands. */ |
29b0f896 AM |
8553 | if (i.operands != t->operands) |
8554 | continue; | |
8555 | ||
b58829cd JB |
8556 | /* Skip SSE2AVX templates when inapplicable. */ |
8557 | if (t->opcode_modifier.sse2avx | |
8558 | && (!sse2avx || i.prefix[DATA_PREFIX])) | |
8559 | { | |
8560 | /* Another non-SSE2AVX template has to follow. */ | |
8561 | gas_assert (t + 1 < current_templates.end); | |
8562 | continue; | |
8563 | } | |
8564 | ||
50aecf8c | 8565 | /* Check processor support. */ |
7b94647a | 8566 | specific_error = progress (unsupported); |
45a4bb20 | 8567 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
8568 | continue; |
8569 | ||
e1d4d893 | 8570 | /* Check AT&T mnemonic. */ |
7b94647a | 8571 | specific_error = progress (unsupported_with_intel_mnemonic); |
35266cb1 JB |
8572 | if (!intel_syntax && intel_mnemonic |
8573 | && t->opcode_modifier.dialect == ATT_MNEMONIC) | |
1efbbeb4 L |
8574 | continue; |
8575 | ||
4b5aaf5f | 8576 | /* Check AT&T/Intel syntax. */ |
7b94647a | 8577 | specific_error = progress (unsupported_syntax); |
7d3182d6 | 8578 | if (intel_syntax |
35266cb1 JB |
8579 | ? t->opcode_modifier.dialect >= ATT_SYNTAX |
8580 | : t->opcode_modifier.dialect == INTEL_SYNTAX) | |
1efbbeb4 L |
8581 | continue; |
8582 | ||
dd74a603 CL |
8583 | /* Check NF support. */ |
8584 | specific_error = progress (unsupported_nf); | |
8585 | if (i.has_nf && !t->opcode_modifier.nf) | |
8586 | continue; | |
8587 | ||
4b5aaf5f L |
8588 | /* Check Intel64/AMD64 ISA. */ |
8589 | switch (isa64) | |
8590 | { | |
8591 | default: | |
8592 | /* Default: Don't accept Intel64. */ | |
8593 | if (t->opcode_modifier.isa64 == INTEL64) | |
8594 | continue; | |
8595 | break; | |
8596 | case amd64: | |
8597 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
8598 | if (t->opcode_modifier.isa64 >= INTEL64) | |
8599 | continue; | |
8600 | break; | |
8601 | case intel64: | |
8602 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 8603 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
8604 | continue; |
8605 | break; | |
8606 | } | |
8607 | ||
dc2be329 | 8608 | /* Check the suffix. */ |
7b94647a | 8609 | specific_error = progress (invalid_instruction_suffix); |
7505bb03 JB |
8610 | if ((t->opcode_modifier.no_bsuf && mnem_suffix == BYTE_MNEM_SUFFIX) |
8611 | || (t->opcode_modifier.no_wsuf && mnem_suffix == WORD_MNEM_SUFFIX) | |
8612 | || (t->opcode_modifier.no_lsuf && mnem_suffix == LONG_MNEM_SUFFIX) | |
8613 | || (t->opcode_modifier.no_ssuf && mnem_suffix == SHORT_MNEM_SUFFIX) | |
8614 | || (t->opcode_modifier.no_qsuf && mnem_suffix == QWORD_MNEM_SUFFIX)) | |
83b16ac6 | 8615 | continue; |
29b0f896 | 8616 | |
7b94647a | 8617 | specific_error = progress (operand_size_mismatch); |
3ac21baa JB |
8618 | size_match = operand_size_match (t); |
8619 | if (!size_match) | |
7d5e4556 | 8620 | continue; |
539e75ad | 8621 | |
6f2f06be JB |
8622 | /* This is intentionally not |
8623 | ||
0cfa3eb3 | 8624 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
8625 | |
8626 | as the case of a missing * on the operand is accepted (perhaps with | |
8627 | a warning, issued further down). */ | |
7b94647a | 8628 | specific_error = progress (operand_type_mismatch); |
0cfa3eb3 | 8629 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
7b94647a | 8630 | continue; |
6f2f06be | 8631 | |
a4d3acd2 JB |
8632 | /* In Intel syntax, normally we can check for memory operand size when |
8633 | there is no mnemonic suffix. But jmp and call have 2 different | |
8634 | encodings with Dword memory operand size. Skip the "near" one | |
8635 | (permitting a register operand) when "far" was requested. */ | |
8636 | if (i.far_branch | |
8637 | && t->opcode_modifier.jump == JUMP_ABSOLUTE | |
8638 | && t->operand_types[0].bitfield.class == Reg) | |
8639 | continue; | |
8640 | ||
5c07affc L |
8641 | for (j = 0; j < MAX_OPERANDS; j++) |
8642 | operand_types[j] = t->operand_types[j]; | |
8643 | ||
9db83a32 | 8644 | /* In general, don't allow 32-bit operands on pre-386. */ |
7b94647a JB |
8645 | specific_error = progress (mnem_suffix ? invalid_instruction_suffix |
8646 | : operand_size_mismatch); | |
4873e243 | 8647 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
9db83a32 JB |
8648 | if (i.suffix == LONG_MNEM_SUFFIX |
8649 | && !cpu_arch_flags.bitfield.cpui386 | |
45aa61fe | 8650 | && (intel_syntax |
3cd7f3e3 | 8651 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
76d3f746 JB |
8652 | && !intel_float_operand (insn_name (t))) |
8653 | : intel_float_operand (insn_name (t)) != 2) | |
4873e243 JB |
8654 | && (t->operands == i.imm_operands |
8655 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
8656 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
8657 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
8658 | || (operand_types[j].bitfield.class != RegMMX | |
8659 | && operand_types[j].bitfield.class != RegSIMD | |
8660 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 8661 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
8662 | continue; |
8663 | ||
29b0f896 | 8664 | /* Do not verify operands when there are none. */ |
e365e234 | 8665 | if (!t->operands) |
da4977e0 JB |
8666 | { |
8667 | if (VEX_check_encoding (t)) | |
8668 | { | |
7b94647a | 8669 | specific_error = progress (i.error); |
da4977e0 JB |
8670 | continue; |
8671 | } | |
8672 | ||
80d61d8d CL |
8673 | /* Check if pseudo prefix {rex2} is valid. */ |
8674 | if (t->opcode_modifier.noegpr && i.rex2_encoding) | |
8675 | { | |
8676 | specific_error = progress (invalid_pseudo_prefix); | |
8677 | continue; | |
8678 | } | |
8679 | ||
da4977e0 JB |
8680 | /* We've found a match; break out of loop. */ |
8681 | break; | |
8682 | } | |
252b5132 | 8683 | |
48bcea9f JB |
8684 | if (!t->opcode_modifier.jump |
8685 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
8686 | { | |
8687 | /* There should be only one Disp operand. */ | |
8688 | for (j = 0; j < MAX_OPERANDS; j++) | |
8689 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 8690 | break; |
48bcea9f JB |
8691 | if (j < MAX_OPERANDS) |
8692 | { | |
5b7c81bd | 8693 | bool override = (i.prefix[ADDR_PREFIX] != 0); |
48bcea9f JB |
8694 | |
8695 | addr_prefix_disp = j; | |
8696 | ||
a775efc8 JB |
8697 | /* Address size prefix will turn Disp64 operand into Disp32 and |
8698 | Disp32/Disp16 one into Disp16/Disp32 respectively. */ | |
48bcea9f | 8699 | switch (flag_code) |
40fb9820 | 8700 | { |
48bcea9f JB |
8701 | case CODE_16BIT: |
8702 | override = !override; | |
8703 | /* Fall through. */ | |
8704 | case CODE_32BIT: | |
8705 | if (operand_types[j].bitfield.disp32 | |
8706 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 8707 | { |
48bcea9f JB |
8708 | operand_types[j].bitfield.disp16 = override; |
8709 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 8710 | } |
a775efc8 | 8711 | gas_assert (!operand_types[j].bitfield.disp64); |
48bcea9f JB |
8712 | break; |
8713 | ||
8714 | case CODE_64BIT: | |
a775efc8 | 8715 | if (operand_types[j].bitfield.disp64) |
40fb9820 | 8716 | { |
a775efc8 | 8717 | gas_assert (!operand_types[j].bitfield.disp32); |
48bcea9f | 8718 | operand_types[j].bitfield.disp32 = override; |
a775efc8 | 8719 | operand_types[j].bitfield.disp64 = !override; |
40fb9820 | 8720 | } |
48bcea9f JB |
8721 | operand_types[j].bitfield.disp16 = 0; |
8722 | break; | |
40fb9820 | 8723 | } |
539e75ad | 8724 | } |
48bcea9f | 8725 | } |
539e75ad | 8726 | |
56ffb741 | 8727 | /* We check register size if needed. */ |
9c19e9ec | 8728 | if (t->opcode_modifier.checkoperandsize) |
e2195274 JB |
8729 | { |
8730 | check_register = (1 << t->operands) - 1; | |
a5748e0d | 8731 | if (i.broadcast.type || i.broadcast.bytes) |
5273a3cd | 8732 | check_register &= ~(1 << i.broadcast.operand); |
e2195274 JB |
8733 | } |
8734 | else | |
8735 | check_register = 0; | |
8736 | ||
c6fb90c8 | 8737 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
8738 | switch (t->operands) |
8739 | { | |
8740 | case 1: | |
40fb9820 | 8741 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 | 8742 | continue; |
ae9a0a51 JB |
8743 | |
8744 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
8745 | {store} pseudo prefix on an applicable insn. */ | |
8746 | if (!t->opcode_modifier.modrm | |
8747 | && i.reg_operands == 1 | |
8748 | && ((i.dir_encoding == dir_encoding_load | |
8749 | && t->mnem_off != MN_pop) | |
8750 | || (i.dir_encoding == dir_encoding_store | |
8751 | && t->mnem_off != MN_push)) | |
8752 | /* Avoid BSWAP. */ | |
8753 | && t->mnem_off != MN_bswap) | |
8754 | continue; | |
29b0f896 | 8755 | break; |
ae9a0a51 | 8756 | |
29b0f896 | 8757 | case 2: |
33eaf5de | 8758 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
8759 | only in 32bit mode and we can use opcode 0x90. In 64bit |
8760 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
8761 | zero-extend %eax to %rax. */ | |
ae9a0a51 JB |
8762 | if (t->base_opcode == 0x90 |
8763 | && t->opcode_space == SPACE_BASE) | |
8764 | { | |
8765 | if (flag_code == CODE_64BIT | |
8766 | && i.types[0].bitfield.instance == Accum | |
8767 | && i.types[0].bitfield.dword | |
8768 | && i.types[1].bitfield.instance == Accum) | |
8769 | continue; | |
8770 | ||
8771 | /* Allow the ModR/M encoding to be requested by using the | |
8772 | {load} or {store} pseudo prefix. */ | |
8773 | if (i.dir_encoding == dir_encoding_load | |
8774 | || i.dir_encoding == dir_encoding_store) | |
8775 | continue; | |
8776 | } | |
e3669c7f JB |
8777 | |
8778 | if (t->base_opcode == MOV_AX_DISP32 | |
ddb62495 | 8779 | && t->opcode_space == SPACE_BASE |
69196391 | 8780 | && t->mnem_off != MN_movabs) |
e3669c7f JB |
8781 | { |
8782 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ | |
8783 | if (i.reloc[0] == BFD_RELOC_386_GOT32) | |
8784 | continue; | |
8785 | ||
8786 | /* xrelease mov %eax, <disp> is another special case. It must not | |
8787 | match the accumulator-only encoding of mov. */ | |
8788 | if (i.hle_prefix) | |
8789 | continue; | |
ae9a0a51 JB |
8790 | |
8791 | /* Allow the ModR/M encoding to be requested by using a suitable | |
8792 | {load} or {store} pseudo prefix. */ | |
8793 | if (i.dir_encoding == (i.types[0].bitfield.instance == Accum | |
8794 | ? dir_encoding_store | |
8795 | : dir_encoding_load) | |
8796 | && !i.types[0].bitfield.disp64 | |
8797 | && !i.types[1].bitfield.disp64) | |
8798 | continue; | |
8799 | } | |
8800 | ||
8801 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
8802 | {store} pseudo prefix on an applicable insn. */ | |
8803 | if (!t->opcode_modifier.modrm | |
8804 | && i.reg_operands == 1 | |
8805 | && i.imm_operands == 1 | |
8806 | && (i.dir_encoding == dir_encoding_load | |
8807 | || i.dir_encoding == dir_encoding_store) | |
8808 | && t->opcode_space == SPACE_BASE) | |
8809 | { | |
8810 | if (t->base_opcode == 0xb0 /* mov $imm, %reg */ | |
8811 | && i.dir_encoding == dir_encoding_store) | |
8812 | continue; | |
8813 | ||
8814 | if ((t->base_opcode | 0x38) == 0x3c /* <alu> $imm, %acc */ | |
8815 | && (t->base_opcode != 0x3c /* cmp $imm, %acc */ | |
8816 | || i.dir_encoding == dir_encoding_load)) | |
8817 | continue; | |
8818 | ||
8819 | if (t->base_opcode == 0xa8 /* test $imm, %acc */ | |
8820 | && i.dir_encoding == dir_encoding_load) | |
8821 | continue; | |
e3669c7f | 8822 | } |
f5eb1d70 JB |
8823 | /* Fall through. */ |
8824 | ||
8825 | case 3: | |
3ac21baa JB |
8826 | if (!(size_match & MATCH_STRAIGHT)) |
8827 | goto check_reverse; | |
64c49ab3 JB |
8828 | /* Reverse direction of operands if swapping is possible in the first |
8829 | place (operands need to be symmetric) and | |
8830 | - the load form is requested, and the template is a store form, | |
8831 | - the store form is requested, and the template is a load form, | |
8832 | - the non-default (swapped) form is requested. */ | |
8833 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
3083f376 | 8834 | |
8835 | j = i.operands - 1 - (t->opcode_space == SPACE_EVEXMAP4 | |
8836 | && t->opcode_modifier.vexvvvv); | |
8837 | ||
f5eb1d70 | 8838 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
8839 | && !operand_type_all_zero (&overlap1)) |
8840 | switch (i.dir_encoding) | |
8841 | { | |
8842 | case dir_encoding_load: | |
3083f376 | 8843 | if (operand_type_check (operand_types[j], anymem) |
dfd69174 | 8844 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
8845 | goto check_reverse; |
8846 | break; | |
8847 | ||
8848 | case dir_encoding_store: | |
3083f376 | 8849 | if (!operand_type_check (operand_types[j], anymem) |
dfd69174 | 8850 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
8851 | goto check_reverse; |
8852 | break; | |
8853 | ||
8854 | case dir_encoding_swap: | |
8855 | goto check_reverse; | |
8856 | ||
8857 | case dir_encoding_default: | |
8858 | break; | |
8859 | } | |
3083f376 | 8860 | |
86fa6981 | 8861 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
8862 | if ((i.dir_encoding == dir_encoding_store |
8863 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
8864 | && i.mem_operands == 0 |
8865 | && t->opcode_modifier.load) | |
fa99fab2 | 8866 | continue; |
1a0670f3 | 8867 | /* Fall through. */ |
f48ff2ae | 8868 | case 4: |
c0f3af97 | 8869 | case 5: |
c6fb90c8 | 8870 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
8871 | if (!operand_type_match (overlap0, i.types[0]) |
8872 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 8873 | || ((check_register & 3) == 3 |
dc821c5f | 8874 | && !operand_type_register_match (i.types[0], |
40fb9820 | 8875 | operand_types[0], |
dc821c5f | 8876 | i.types[1], |
40fb9820 | 8877 | operand_types[1]))) |
29b0f896 | 8878 | { |
7b94647a JB |
8879 | specific_error = progress (i.error); |
8880 | ||
29b0f896 | 8881 | /* Check if other direction is valid ... */ |
38e314eb | 8882 | if (!t->opcode_modifier.d) |
29b0f896 AM |
8883 | continue; |
8884 | ||
dc1e8a47 | 8885 | check_reverse: |
3ac21baa JB |
8886 | if (!(size_match & MATCH_REVERSE)) |
8887 | continue; | |
29b0f896 | 8888 | /* Try reversing direction of operands. */ |
734dfd1c | 8889 | j = is_cpu (t, CpuFMA4) |
3083f376 | 8890 | || is_cpu (t, CpuXOP) |
8891 | || is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1; | |
8bd915b7 JB |
8892 | overlap0 = operand_type_and (i.types[0], operand_types[j]); |
8893 | overlap1 = operand_type_and (i.types[j], operand_types[0]); | |
c975cec5 | 8894 | overlap2 = operand_type_and (i.types[1], operand_types[1]); |
3083f376 | 8895 | gas_assert (t->operands != 3 || !check_register |
8896 | || is_cpu (t, CpuAPX_F)); | |
40fb9820 | 8897 | if (!operand_type_match (overlap0, i.types[0]) |
8bd915b7 | 8898 | || !operand_type_match (overlap1, i.types[j]) |
c975cec5 JB |
8899 | || (t->operands == 3 |
8900 | && !operand_type_match (overlap2, i.types[1])) | |
45664ddb | 8901 | || (check_register |
dc821c5f | 8902 | && !operand_type_register_match (i.types[0], |
8bd915b7 JB |
8903 | operand_types[j], |
8904 | i.types[j], | |
45664ddb | 8905 | operand_types[0]))) |
29b0f896 AM |
8906 | { |
8907 | /* Does not match either direction. */ | |
7b94647a | 8908 | specific_error = progress (i.error); |
29b0f896 AM |
8909 | continue; |
8910 | } | |
ac9226cf | 8911 | /* found_reverse_match holds which variant of D |
29b0f896 | 8912 | we've found. */ |
38e314eb JB |
8913 | if (!t->opcode_modifier.d) |
8914 | found_reverse_match = 0; | |
8915 | else if (operand_types[0].bitfield.tbyte) | |
ac9226cf | 8916 | { |
4943d587 JB |
8917 | if (t->opcode_modifier.operandconstraint != UGH) |
8918 | found_reverse_match = Opcode_FloatD; | |
bd782808 JB |
8919 | else |
8920 | found_reverse_match = ~0; | |
ac9226cf | 8921 | /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */ |
bd782808 | 8922 | if ((t->extension_opcode & 4) |
ac9226cf JB |
8923 | && (intel_syntax || intel_mnemonic)) |
8924 | found_reverse_match |= Opcode_FloatR; | |
8925 | } | |
734dfd1c | 8926 | else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)) |
8bd915b7 JB |
8927 | { |
8928 | found_reverse_match = Opcode_VexW; | |
8929 | goto check_operands_345; | |
8930 | } | |
dd74a603 CL |
8931 | else if (t->opcode_space == SPACE_EVEXMAP4 |
8932 | && t->opcode_modifier.w) | |
3083f376 | 8933 | { |
8934 | found_reverse_match = Opcode_D; | |
8935 | goto check_operands_345; | |
8936 | } | |
ddb62495 JB |
8937 | else if (t->opcode_space != SPACE_BASE |
8938 | && (t->opcode_space != SPACE_0F | |
2c735193 JB |
8939 | /* MOV to/from CR/DR/TR, as an exception, follow |
8940 | the base opcode space encoding model. */ | |
8941 | || (t->base_opcode | 7) != 0x27)) | |
dbbc8b7e | 8942 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e |
2c735193 | 8943 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
a33ef3c2 | 8944 | else if (!t->opcode_modifier.commutative) |
38e314eb | 8945 | found_reverse_match = Opcode_D; |
a33ef3c2 JB |
8946 | else |
8947 | found_reverse_match = ~0; | |
29b0f896 | 8948 | } |
f48ff2ae | 8949 | else |
29b0f896 | 8950 | { |
f48ff2ae | 8951 | /* Found a forward 2 operand match here. */ |
8bd915b7 | 8952 | check_operands_345: |
d1cbb4db L |
8953 | switch (t->operands) |
8954 | { | |
c0f3af97 | 8955 | case 5: |
3d0738af | 8956 | overlap4 = operand_type_and (i.types[4], operand_types[4]); |
c0f3af97 | 8957 | if (!operand_type_match (overlap4, i.types[4]) |
dc821c5f | 8958 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 8959 | operand_types[3], |
c0f3af97 L |
8960 | i.types[4], |
8961 | operand_types[4])) | |
7b94647a JB |
8962 | { |
8963 | specific_error = progress (i.error); | |
8964 | continue; | |
8965 | } | |
1a0670f3 | 8966 | /* Fall through. */ |
f48ff2ae | 8967 | case 4: |
3d0738af | 8968 | overlap3 = operand_type_and (i.types[3], operand_types[3]); |
40fb9820 | 8969 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
8970 | || ((check_register & 0xa) == 0xa |
8971 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
8972 | operand_types[1], |
8973 | i.types[3], | |
e2195274 JB |
8974 | operand_types[3])) |
8975 | || ((check_register & 0xc) == 0xc | |
8976 | && !operand_type_register_match (i.types[2], | |
8977 | operand_types[2], | |
8978 | i.types[3], | |
8979 | operand_types[3]))) | |
7b94647a JB |
8980 | { |
8981 | specific_error = progress (i.error); | |
8982 | continue; | |
8983 | } | |
1a0670f3 | 8984 | /* Fall through. */ |
f48ff2ae | 8985 | case 3: |
3d0738af | 8986 | overlap2 = operand_type_and (i.types[2], operand_types[2]); |
40fb9820 | 8987 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
8988 | || ((check_register & 5) == 5 |
8989 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
8990 | operand_types[0], |
8991 | i.types[2], | |
e2195274 JB |
8992 | operand_types[2])) |
8993 | || ((check_register & 6) == 6 | |
8994 | && !operand_type_register_match (i.types[1], | |
8995 | operand_types[1], | |
8996 | i.types[2], | |
8997 | operand_types[2]))) | |
7b94647a JB |
8998 | { |
8999 | specific_error = progress (i.error); | |
9000 | continue; | |
9001 | } | |
f48ff2ae L |
9002 | break; |
9003 | } | |
29b0f896 | 9004 | } |
f48ff2ae | 9005 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
9006 | slip through to break. */ |
9007 | } | |
c0f3af97 | 9008 | |
9bb4d860 L |
9009 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ |
9010 | if (VEX_check_encoding (t)) | |
da4977e0 | 9011 | { |
7b94647a | 9012 | specific_error = progress (i.error); |
da4977e0 JB |
9013 | continue; |
9014 | } | |
9015 | ||
80d61d8d CL |
9016 | /* Check if EGPR operands(r16-r31) are valid. */ |
9017 | if (check_EgprOperands (t)) | |
9018 | { | |
9019 | specific_error = progress (i.error); | |
9020 | continue; | |
9021 | } | |
9022 | ||
9bb4d860 L |
9023 | /* Check if vector operands are valid. */ |
9024 | if (check_VecOperands (t)) | |
5614d22c | 9025 | { |
7b94647a | 9026 | specific_error = progress (i.error); |
5614d22c JB |
9027 | continue; |
9028 | } | |
a683cc34 | 9029 | |
08a98d4c MZ |
9030 | /* Check if APX operands are valid. */ |
9031 | if (check_APX_operands (t)) | |
9032 | { | |
9033 | specific_error = progress (i.error); | |
9034 | continue; | |
9035 | } | |
9036 | ||
58bceb18 | 9037 | /* Check whether to use the shorter VEX encoding for certain insns where |
39bb3ade JB |
9038 | the EVEX encoding comes first in the table. This requires the respective |
9039 | AVX-* feature to be explicitly enabled. | |
9040 | ||
9041 | Most of the respective insns have just a single EVEX and a single VEX | |
9042 | template. The one that's presently different is generated using the | |
9043 | Vxy / Exy constructs: There are 3 suffix-less EVEX forms, the latter | |
9044 | two of which may fall back to their two corresponding VEX forms. */ | |
9045 | j = t->mnem_off != MN_vcvtneps2bf16 ? 1 : 2; | |
d3b01414 | 9046 | if ((t == current_templates.start || j > 1) |
58bceb18 JB |
9047 | && t->opcode_modifier.disp8memshift |
9048 | && !t->opcode_modifier.vex | |
6177c84d | 9049 | && !need_evex_encoding (t) |
d3b01414 | 9050 | && t + j < current_templates.end |
39bb3ade | 9051 | && t[j].opcode_modifier.vex) |
58bceb18 JB |
9052 | { |
9053 | i386_cpu_flags cpu; | |
9054 | unsigned int memshift = i.memshift; | |
9055 | ||
9056 | i.memshift = 0; | |
39bb3ade JB |
9057 | cpu = cpu_flags_and (cpu_flags_from_attr (t[j].cpu), |
9058 | cpu_arch_isa_flags); | |
58bceb18 JB |
9059 | if (!cpu_flags_all_zero (&cpu) |
9060 | && (!i.types[0].bitfield.disp8 | |
9061 | || !operand_type_check (i.types[0], disp) | |
9062 | || i.op[0].disps->X_op != O_constant | |
9063 | || fits_in_disp8 (i.op[0].disps->X_add_number))) | |
9064 | { | |
9065 | specific_error = progress (internal_error); | |
39bb3ade | 9066 | t += j - 1; |
58bceb18 JB |
9067 | continue; |
9068 | } | |
9069 | i.memshift = memshift; | |
9070 | } | |
9071 | ||
6967f19d HL |
9072 | /* If we can optimize a NDD insn to legacy insn, like |
9073 | add %r16, %r8, %r8 -> add %r16, %r8, | |
9074 | add %r8, %r16, %r8 -> add %r16, %r8, then rematch template. | |
9075 | Note that the semantics have not been changed. */ | |
9076 | if (optimize | |
9077 | && !i.no_optimize | |
e346d50a | 9078 | && i.encoding != encoding_evex |
0ebcbb1b JB |
9079 | && ((t + 1 < current_templates.end |
9080 | && !t[1].opcode_modifier.evex | |
9081 | && t[1].opcode_space <= SPACE_0F38 | |
9082 | && t->opcode_modifier.vexvvvv == VexVVVV_DST) | |
9083 | || t->mnem_off == MN_movbe) | |
6967f19d HL |
9084 | && (i.types[i.operands - 1].bitfield.dword |
9085 | || i.types[i.operands - 1].bitfield.qword)) | |
9086 | { | |
9087 | unsigned int match_dest_op = can_convert_NDD_to_legacy (t); | |
9088 | ||
9089 | if (match_dest_op != (unsigned int) ~0) | |
9090 | { | |
9091 | size_match = true; | |
9092 | /* We ensure that the next template has the same input | |
9093 | operands as the original matching template by the first | |
9094 | opernd (ATT). To avoid someone support new NDD insns and | |
9095 | put it in the wrong position. */ | |
9096 | overlap0 = operand_type_and (i.types[0], | |
9097 | t[1].operand_types[0]); | |
9098 | if (t->opcode_modifier.d) | |
9099 | overlap1 = operand_type_and (i.types[0], | |
9100 | t[1].operand_types[1]); | |
9101 | if (!operand_type_match (overlap0, i.types[0]) | |
9102 | && (!t->opcode_modifier.d | |
9103 | || !operand_type_match (overlap1, i.types[0]))) | |
9104 | size_match = false; | |
9105 | ||
9106 | if (size_match | |
9107 | && (t[1].opcode_space <= SPACE_0F | |
9108 | /* Some non-legacy-map0/1 insns can be shorter when | |
9109 | legacy-encoded and when no REX prefix is required. */ | |
9110 | || (!check_EgprOperands (t + 1) | |
9111 | && !check_Rex_required () | |
9112 | && !i.op[i.operands - 1].regs->reg_type.bitfield.qword))) | |
9113 | { | |
9114 | if (i.operands > 2 && match_dest_op == i.operands - 3) | |
9115 | swap_2_operands (match_dest_op, i.operands - 2); | |
9116 | ||
9117 | --i.operands; | |
9118 | --i.reg_operands; | |
9119 | ||
0ebcbb1b JB |
9120 | if (t->mnem_off == MN_movbe) |
9121 | { | |
9122 | gas_assert (t[1].mnem_off == MN_bswap); | |
9123 | ++current_templates.end; | |
9124 | } | |
9125 | ||
6967f19d HL |
9126 | specific_error = progress (internal_error); |
9127 | continue; | |
9128 | } | |
9129 | ||
9130 | } | |
9131 | } | |
9132 | ||
29b0f896 AM |
9133 | /* We've found a match; break out of loop. */ |
9134 | break; | |
9135 | } | |
9136 | ||
7b94647a JB |
9137 | #undef progress |
9138 | ||
d3b01414 | 9139 | if (t == current_templates.end) |
29b0f896 AM |
9140 | { |
9141 | /* We found no match. */ | |
04784e33 | 9142 | i.error = specific_error; |
fa99fab2 | 9143 | return NULL; |
29b0f896 | 9144 | } |
252b5132 | 9145 | |
29b0f896 AM |
9146 | if (!quiet_warnings) |
9147 | { | |
9148 | if (!intel_syntax | |
0cfa3eb3 | 9149 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
76d3f746 | 9150 | as_warn (_("indirect %s without `*'"), insn_name (t)); |
29b0f896 | 9151 | |
40fb9820 | 9152 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 9153 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
9154 | { |
9155 | /* Warn them that a data or address size prefix doesn't | |
9156 | affect assembly of the next line of code. */ | |
76d3f746 | 9157 | as_warn (_("stand-alone `%s' prefix"), insn_name (t)); |
29b0f896 AM |
9158 | } |
9159 | } | |
9160 | ||
9161 | /* Copy the template we found. */ | |
9a182d04 | 9162 | install_template (t); |
539e75ad L |
9163 | |
9164 | if (addr_prefix_disp != -1) | |
9165 | i.tm.operand_types[addr_prefix_disp] | |
9166 | = operand_types[addr_prefix_disp]; | |
9167 | ||
09de03fc JB |
9168 | /* APX insns acting on byte operands are WIG, yet that can't be expressed |
9169 | in the templates (they're also covering word/dword/qword operands). */ | |
9170 | if (t->opcode_space == SPACE_EVEXMAP4 && !t->opcode_modifier.vexw && | |
9171 | i.types[i.operands - 1].bitfield.byte) | |
9172 | { | |
9173 | gas_assert (t->opcode_modifier.w); | |
9174 | i.tm.opcode_modifier.vexw = VEXWIG; | |
9175 | } | |
9176 | ||
8bd915b7 | 9177 | switch (found_reverse_match) |
29b0f896 | 9178 | { |
8bd915b7 JB |
9179 | case 0: |
9180 | break; | |
9181 | ||
bd782808 JB |
9182 | case Opcode_FloatR: |
9183 | case Opcode_FloatR | Opcode_FloatD: | |
9184 | i.tm.extension_opcode ^= Opcode_FloatR >> 3; | |
9185 | found_reverse_match &= Opcode_FloatD; | |
9186 | ||
9187 | /* Fall through. */ | |
8bd915b7 | 9188 | default: |
dfd69174 JB |
9189 | /* If we found a reverse match we must alter the opcode direction |
9190 | bit and clear/flip the regmem modifier one. found_reverse_match | |
9191 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
9192 | |
9193 | i.tm.base_opcode ^= found_reverse_match; | |
9194 | ||
3083f376 | 9195 | if (i.tm.opcode_space == SPACE_EVEXMAP4) |
9196 | goto swap_first_2; | |
9197 | ||
dfd69174 JB |
9198 | /* Certain SIMD insns have their load forms specified in the opcode |
9199 | table, and hence we need to _set_ RegMem instead of clearing it. | |
9200 | We need to avoid setting the bit though on insns like KMOVW. */ | |
9201 | i.tm.opcode_modifier.regmem | |
9202 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
9203 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
9204 | && !i.tm.opcode_modifier.regmem; | |
a33ef3c2 JB |
9205 | |
9206 | /* Fall through. */ | |
9207 | case ~0: | |
9208 | i.tm.operand_types[0] = operand_types[i.operands - 1]; | |
9209 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
8bd915b7 JB |
9210 | break; |
9211 | ||
9212 | case Opcode_VexW: | |
9213 | /* Only the first two register operands need reversing, alongside | |
9214 | flipping VEX.W. */ | |
9215 | i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1; | |
9216 | ||
3083f376 | 9217 | swap_first_2: |
8bd915b7 JB |
9218 | j = i.tm.operand_types[0].bitfield.imm8; |
9219 | i.tm.operand_types[j] = operand_types[j + 1]; | |
9220 | i.tm.operand_types[j + 1] = operand_types[j]; | |
9221 | break; | |
29b0f896 AM |
9222 | } |
9223 | ||
fa99fab2 | 9224 | return t; |
29b0f896 AM |
9225 | } |
9226 | ||
9227 | static int | |
e3bb37b5 | 9228 | check_string (void) |
29b0f896 | 9229 | { |
51c8edf6 JB |
9230 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
9231 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 9232 | |
5e042380 | 9233 | if (i.seg[op] != NULL && i.seg[op] != reg_es) |
29b0f896 | 9234 | { |
51c8edf6 | 9235 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
76d3f746 | 9236 | insn_name (&i.tm), |
51c8edf6 JB |
9237 | intel_syntax ? i.tm.operands - es_op : es_op + 1, |
9238 | register_prefix); | |
9239 | return 0; | |
29b0f896 | 9240 | } |
51c8edf6 JB |
9241 | |
9242 | /* There's only ever one segment override allowed per instruction. | |
9243 | This instruction possibly has a legal segment override on the | |
9244 | second operand, so copy the segment to where non-string | |
9245 | instructions store it, allowing common code. */ | |
9246 | i.seg[op] = i.seg[1]; | |
9247 | ||
29b0f896 AM |
9248 | return 1; |
9249 | } | |
9250 | ||
9251 | static int | |
543613e9 | 9252 | process_suffix (void) |
29b0f896 | 9253 | { |
7fc69528 | 9254 | bool is_movx = false; |
8b65b895 | 9255 | |
29b0f896 AM |
9256 | /* If matched instruction specifies an explicit instruction mnemonic |
9257 | suffix, use it. */ | |
673fe0f0 | 9258 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 9259 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 9260 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 9261 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 9262 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 9263 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 9264 | else if (i.reg_operands |
c8f8eebc | 9265 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
255571cd | 9266 | && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG) |
29b0f896 | 9267 | { |
65fca059 | 9268 | unsigned int numop = i.operands; |
389d00a5 JB |
9269 | |
9270 | /* MOVSX/MOVZX */ | |
ddb62495 | 9271 | is_movx = (i.tm.opcode_space == SPACE_0F |
389d00a5 | 9272 | && (i.tm.base_opcode | 8) == 0xbe) |
ddb62495 | 9273 | || (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 9274 | && i.tm.base_opcode == 0x63 |
734dfd1c | 9275 | && is_cpu (&i.tm, Cpu64)); |
389d00a5 | 9276 | |
65fca059 JB |
9277 | /* movsx/movzx want only their source operand considered here, for the |
9278 | ambiguity checking below. The suffix will be replaced afterwards | |
9279 | to represent the destination (register). */ | |
389d00a5 | 9280 | if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63)) |
65fca059 JB |
9281 | --i.operands; |
9282 | ||
643bb870 | 9283 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
7fc69528 | 9284 | if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword) |
643bb870 JB |
9285 | i.rex |= REX_W; |
9286 | ||
29b0f896 | 9287 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 9288 | based on GPR operands. */ |
29b0f896 AM |
9289 | if (!i.suffix) |
9290 | { | |
9291 | /* We take i.suffix from the last register operand specified, | |
9292 | Destination register type is more significant than source | |
381d071f L |
9293 | register type. crc32 in SSE4.2 prefers source register |
9294 | type. */ | |
7fc69528 | 9295 | unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands; |
20592a94 | 9296 | |
1a035124 JB |
9297 | while (op--) |
9298 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
9299 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
9300 | { | |
9301 | if (i.types[op].bitfield.class != Reg) | |
9302 | continue; | |
9303 | if (i.types[op].bitfield.byte) | |
9304 | i.suffix = BYTE_MNEM_SUFFIX; | |
9305 | else if (i.types[op].bitfield.word) | |
9306 | i.suffix = WORD_MNEM_SUFFIX; | |
9307 | else if (i.types[op].bitfield.dword) | |
9308 | i.suffix = LONG_MNEM_SUFFIX; | |
9309 | else if (i.types[op].bitfield.qword) | |
9310 | i.suffix = QWORD_MNEM_SUFFIX; | |
9311 | else | |
9312 | continue; | |
9313 | break; | |
9314 | } | |
65fca059 JB |
9315 | |
9316 | /* As an exception, movsx/movzx silently default to a byte source | |
9317 | in AT&T mode. */ | |
389d00a5 | 9318 | if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax) |
65fca059 | 9319 | i.suffix = BYTE_MNEM_SUFFIX; |
29b0f896 AM |
9320 | } |
9321 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
9322 | { | |
1cb0ab18 | 9323 | if (!check_byte_reg ()) |
29b0f896 AM |
9324 | return 0; |
9325 | } | |
9326 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
9327 | { | |
1cb0ab18 | 9328 | if (!check_long_reg ()) |
29b0f896 AM |
9329 | return 0; |
9330 | } | |
9331 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
9332 | { | |
1cb0ab18 | 9333 | if (!check_qword_reg ()) |
29b0f896 AM |
9334 | return 0; |
9335 | } | |
9336 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
9337 | { | |
1cb0ab18 | 9338 | if (!check_word_reg ()) |
29b0f896 AM |
9339 | return 0; |
9340 | } | |
3cd7f3e3 L |
9341 | else if (intel_syntax |
9342 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
9343 | /* Do nothing if the instruction is going to ignore the prefix. */ |
9344 | ; | |
9345 | else | |
9346 | abort (); | |
65fca059 JB |
9347 | |
9348 | /* Undo the movsx/movzx change done above. */ | |
9349 | i.operands = numop; | |
29b0f896 | 9350 | } |
3cd7f3e3 L |
9351 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
9352 | && !i.suffix) | |
29b0f896 | 9353 | { |
13e600d0 JB |
9354 | i.suffix = stackop_size; |
9355 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
9356 | { |
9357 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
9358 | .code16gcc directive to support 16-bit mode with | |
9359 | 32-bit address. For IRET without a suffix, generate | |
9360 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
9361 | handler. */ | |
13e600d0 JB |
9362 | if (i.tm.base_opcode == 0xcf) |
9363 | { | |
9364 | i.suffix = WORD_MNEM_SUFFIX; | |
9365 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
9366 | } | |
9367 | /* Warn about changed behavior for segment register push/pop. */ | |
9368 | else if ((i.tm.base_opcode | 1) == 0x07) | |
9369 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
76d3f746 | 9370 | insn_name (&i.tm)); |
06f74c5c | 9371 | } |
29b0f896 | 9372 | } |
c006a730 | 9373 | else if (!i.suffix |
0cfa3eb3 JB |
9374 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
9375 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
9376 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
ddb62495 | 9377 | || (i.tm.opcode_space == SPACE_0F |
389d00a5 | 9378 | && i.tm.base_opcode == 0x01 /* [ls][gi]dt */ |
64e74474 | 9379 | && i.tm.extension_opcode <= 3))) |
9306ca4a JB |
9380 | { |
9381 | switch (flag_code) | |
9382 | { | |
9383 | case CODE_64BIT: | |
40fb9820 | 9384 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 9385 | { |
828c2a25 JB |
9386 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9387 | || i.tm.opcode_modifier.no_lsuf) | |
9388 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
9389 | break; |
9390 | } | |
1a0670f3 | 9391 | /* Fall through. */ |
9306ca4a | 9392 | case CODE_32BIT: |
40fb9820 | 9393 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
9394 | i.suffix = LONG_MNEM_SUFFIX; |
9395 | break; | |
9396 | case CODE_16BIT: | |
40fb9820 | 9397 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
9398 | i.suffix = WORD_MNEM_SUFFIX; |
9399 | break; | |
9400 | } | |
9401 | } | |
252b5132 | 9402 | |
c006a730 | 9403 | if (!i.suffix |
3cd7f3e3 | 9404 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
9405 | /* Also cover lret/retf/iret in 64-bit mode. */ |
9406 | || (flag_code == CODE_64BIT | |
9407 | && !i.tm.opcode_modifier.no_lsuf | |
9408 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 9409 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
9410 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
9411 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
9412 | /* Accept FLDENV et al without suffix. */ |
9413 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 9414 | { |
6c0946d0 | 9415 | unsigned int suffixes, evex = 0; |
c006a730 JB |
9416 | |
9417 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
9418 | if (!i.tm.opcode_modifier.no_wsuf) | |
9419 | suffixes |= 1 << 1; | |
9420 | if (!i.tm.opcode_modifier.no_lsuf) | |
9421 | suffixes |= 1 << 2; | |
c006a730 JB |
9422 | if (!i.tm.opcode_modifier.no_ssuf) |
9423 | suffixes |= 1 << 4; | |
9424 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
9425 | suffixes |= 1 << 5; | |
9426 | ||
6c0946d0 JB |
9427 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
9428 | also suitable for AT&T syntax mode, it was requested that this be | |
9429 | restricted to just Intel syntax. */ | |
a5748e0d JB |
9430 | if (intel_syntax && is_any_vex_encoding (&i.tm) |
9431 | && !i.broadcast.type && !i.broadcast.bytes) | |
6c0946d0 | 9432 | { |
b9915cbc | 9433 | unsigned int op; |
6c0946d0 | 9434 | |
b9915cbc | 9435 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 9436 | { |
4fc85f37 JB |
9437 | if (vector_size < VSZ512) |
9438 | { | |
9439 | i.tm.operand_types[op].bitfield.zmmword = 0; | |
9440 | if (vector_size < VSZ256) | |
9441 | { | |
9442 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
9443 | if (i.tm.operand_types[op].bitfield.xmmword | |
706ce984 | 9444 | && i.tm.opcode_modifier.evex == EVEXDYN) |
4fc85f37 JB |
9445 | i.tm.opcode_modifier.evex = EVEX128; |
9446 | } | |
9447 | else if (i.tm.operand_types[op].bitfield.ymmword | |
9448 | && !i.tm.operand_types[op].bitfield.xmmword | |
706ce984 | 9449 | && i.tm.opcode_modifier.evex == EVEXDYN) |
4fc85f37 JB |
9450 | i.tm.opcode_modifier.evex = EVEX256; |
9451 | } | |
706ce984 | 9452 | else if (i.tm.opcode_modifier.evex |
4fc85f37 | 9453 | && !cpu_arch_flags.bitfield.cpuavx512vl) |
6c0946d0 | 9454 | { |
b9915cbc JB |
9455 | if (i.tm.operand_types[op].bitfield.ymmword) |
9456 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
9457 | if (i.tm.operand_types[op].bitfield.zmmword) | |
9458 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
706ce984 | 9459 | if (i.tm.opcode_modifier.evex == EVEXDYN) |
b9915cbc JB |
9460 | i.tm.opcode_modifier.evex = EVEX512; |
9461 | } | |
6c0946d0 | 9462 | |
b9915cbc JB |
9463 | if (i.tm.operand_types[op].bitfield.xmmword |
9464 | + i.tm.operand_types[op].bitfield.ymmword | |
9465 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
9466 | continue; | |
6c0946d0 | 9467 | |
b9915cbc JB |
9468 | /* Any properly sized operand disambiguates the insn. */ |
9469 | if (i.types[op].bitfield.xmmword | |
9470 | || i.types[op].bitfield.ymmword | |
9471 | || i.types[op].bitfield.zmmword) | |
9472 | { | |
9473 | suffixes &= ~(7 << 6); | |
9474 | evex = 0; | |
9475 | break; | |
9476 | } | |
6c0946d0 | 9477 | |
b9915cbc JB |
9478 | if ((i.flags[op] & Operand_Mem) |
9479 | && i.tm.operand_types[op].bitfield.unspecified) | |
9480 | { | |
9481 | if (i.tm.operand_types[op].bitfield.xmmword) | |
9482 | suffixes |= 1 << 6; | |
9483 | if (i.tm.operand_types[op].bitfield.ymmword) | |
9484 | suffixes |= 1 << 7; | |
9485 | if (i.tm.operand_types[op].bitfield.zmmword) | |
9486 | suffixes |= 1 << 8; | |
706ce984 | 9487 | if (i.tm.opcode_modifier.evex) |
b9915cbc | 9488 | evex = EVEX512; |
6c0946d0 JB |
9489 | } |
9490 | } | |
9491 | } | |
9492 | ||
9493 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 9494 | if (suffixes & (suffixes - 1)) |
9306ca4a | 9495 | { |
873494c8 | 9496 | if (intel_syntax |
3cd7f3e3 | 9497 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 9498 | || operand_check == check_error)) |
9306ca4a | 9499 | { |
76d3f746 | 9500 | as_bad (_("ambiguous operand size for `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
9501 | return 0; |
9502 | } | |
c006a730 | 9503 | if (operand_check == check_error) |
9306ca4a | 9504 | { |
c006a730 | 9505 | as_bad (_("no instruction mnemonic suffix given and " |
76d3f746 | 9506 | "no register operands; can't size `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
9507 | return 0; |
9508 | } | |
c006a730 | 9509 | if (operand_check == check_warning) |
873494c8 JB |
9510 | as_warn (_("%s; using default for `%s'"), |
9511 | intel_syntax | |
9512 | ? _("ambiguous operand size") | |
9513 | : _("no instruction mnemonic suffix given and " | |
9514 | "no register operands"), | |
76d3f746 | 9515 | insn_name (&i.tm)); |
c006a730 JB |
9516 | |
9517 | if (i.tm.opcode_modifier.floatmf) | |
9518 | i.suffix = SHORT_MNEM_SUFFIX; | |
389d00a5 | 9519 | else if (is_movx) |
65fca059 | 9520 | /* handled below */; |
6c0946d0 JB |
9521 | else if (evex) |
9522 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
9523 | else if (flag_code == CODE_16BIT) |
9524 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 9525 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 9526 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
9527 | else |
9528 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 9529 | } |
29b0f896 | 9530 | } |
252b5132 | 9531 | |
389d00a5 | 9532 | if (is_movx) |
65fca059 JB |
9533 | { |
9534 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
9535 | In AT&T syntax, if there is no suffix (warned about above), the default | |
9536 | will be byte extension. */ | |
9537 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
9538 | i.tm.base_opcode |= 1; | |
9539 | ||
9540 | /* For further processing, the suffix should represent the destination | |
9541 | (register). This is already the case when one was used with | |
9542 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
9543 | no suffix to begin with. */ | |
9544 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
9545 | { | |
9546 | if (i.types[1].bitfield.word) | |
9547 | i.suffix = WORD_MNEM_SUFFIX; | |
9548 | else if (i.types[1].bitfield.qword) | |
9549 | i.suffix = QWORD_MNEM_SUFFIX; | |
9550 | else | |
9551 | i.suffix = LONG_MNEM_SUFFIX; | |
9552 | ||
9553 | i.tm.opcode_modifier.w = 0; | |
9554 | } | |
9555 | } | |
9556 | ||
50128d0c JB |
9557 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
9558 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
9559 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
9560 | ||
d2224064 JB |
9561 | /* Change the opcode based on the operand size given by i.suffix. */ |
9562 | switch (i.suffix) | |
29b0f896 | 9563 | { |
d2224064 JB |
9564 | /* Size floating point instruction. */ |
9565 | case LONG_MNEM_SUFFIX: | |
9566 | if (i.tm.opcode_modifier.floatmf) | |
9567 | { | |
9568 | i.tm.base_opcode ^= 4; | |
9569 | break; | |
9570 | } | |
9571 | /* fall through */ | |
9572 | case WORD_MNEM_SUFFIX: | |
9573 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 9574 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 9575 | if (i.tm.opcode_modifier.w) |
29b0f896 | 9576 | { |
50128d0c | 9577 | if (i.short_form) |
29b0f896 AM |
9578 | i.tm.base_opcode |= 8; |
9579 | else | |
9580 | i.tm.base_opcode |= 1; | |
9581 | } | |
4e3be89f JB |
9582 | |
9583 | /* Set mode64 for an operand. */ | |
9584 | if (i.suffix == QWORD_MNEM_SUFFIX) | |
9585 | { | |
9586 | if (flag_code == CODE_64BIT | |
9587 | && !i.tm.opcode_modifier.norex64 | |
9588 | && !i.tm.opcode_modifier.vexw | |
9589 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
9590 | need rex64. */ | |
9591 | && ! (i.operands == 2 | |
9592 | && i.tm.base_opcode == 0x90 | |
9593 | && i.tm.opcode_space == SPACE_BASE | |
9594 | && i.types[0].bitfield.instance == Accum | |
9595 | && i.types[1].bitfield.instance == Accum)) | |
9596 | i.rex |= REX_W; | |
9597 | ||
9598 | break; | |
9599 | } | |
9600 | ||
d2224064 JB |
9601 | /* fall through */ |
9602 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
9603 | /* Now select between word & dword operations via the operand |
9604 | size prefix, except for instructions that will ignore this | |
9605 | prefix anyway. */ | |
4e3be89f | 9606 | if (i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc | 9607 | && !i.tm.opcode_modifier.floatmf |
6177c84d CL |
9608 | && (!is_any_vex_encoding (&i.tm) |
9609 | || i.tm.opcode_space == SPACE_EVEXMAP4) | |
c8f8eebc JB |
9610 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
9611 | || (flag_code == CODE_64BIT | |
9612 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
9613 | { |
9614 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 9615 | |
0cfa3eb3 | 9616 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 9617 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 9618 | |
6177c84d CL |
9619 | /* The DATA PREFIX of EVEX promoted from legacy APX instructions |
9620 | needs to be adjusted. */ | |
9621 | if (i.tm.opcode_space == SPACE_EVEXMAP4) | |
9622 | { | |
9623 | gas_assert (!i.tm.opcode_modifier.opcodeprefix); | |
9624 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; | |
9625 | } | |
9626 | else if (!add_prefix (prefix)) | |
29b0f896 | 9627 | return 0; |
24eab124 | 9628 | } |
252b5132 | 9629 | |
d2224064 | 9630 | break; |
8bbb3ad8 JB |
9631 | |
9632 | case 0: | |
f9a6a8f0 | 9633 | /* Select word/dword/qword operation with explicit data sizing prefix |
8bbb3ad8 JB |
9634 | when there are no suitable register operands. */ |
9635 | if (i.tm.opcode_modifier.w | |
9636 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
9637 | && (!i.reg_operands | |
9638 | || (i.reg_operands == 1 | |
9639 | /* ShiftCount */ | |
9640 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
9641 | /* InOutPortReg */ | |
9642 | || i.tm.operand_types[0].bitfield.instance == RegD | |
9643 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7fc69528 | 9644 | || i.tm.mnem_off == MN_crc32)))) |
8bbb3ad8 JB |
9645 | i.tm.base_opcode |= 1; |
9646 | break; | |
29b0f896 | 9647 | } |
7ecd2f8b | 9648 | |
255571cd | 9649 | if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG) |
c0a30a9f | 9650 | { |
c8f8eebc JB |
9651 | gas_assert (!i.suffix); |
9652 | gas_assert (i.reg_operands); | |
c0a30a9f | 9653 | |
c8f8eebc JB |
9654 | if (i.tm.operand_types[0].bitfield.instance == Accum |
9655 | || i.operands == 1) | |
9656 | { | |
9657 | /* The address size override prefix changes the size of the | |
9658 | first operand. */ | |
9659 | if (flag_code == CODE_64BIT | |
9660 | && i.op[0].regs->reg_type.bitfield.word) | |
9661 | { | |
9662 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
76d3f746 | 9663 | insn_name (&i.tm)); |
c8f8eebc JB |
9664 | return 0; |
9665 | } | |
9666 | ||
9667 | if ((flag_code == CODE_32BIT | |
9668 | ? i.op[0].regs->reg_type.bitfield.word | |
9669 | : i.op[0].regs->reg_type.bitfield.dword) | |
9670 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
9671 | return 0; | |
9672 | } | |
c0a30a9f L |
9673 | else |
9674 | { | |
c8f8eebc JB |
9675 | /* Check invalid register operand when the address size override |
9676 | prefix changes the size of register operands. */ | |
9677 | unsigned int op; | |
9678 | enum { need_word, need_dword, need_qword } need; | |
9679 | ||
27f13469 | 9680 | /* Check the register operand for the address size prefix if |
b3a3496f | 9681 | the memory operand has no real registers, like symbol, DISP |
829f3fe1 | 9682 | or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */ |
27f13469 L |
9683 | if (i.mem_operands == 1 |
9684 | && i.reg_operands == 1 | |
9685 | && i.operands == 2 | |
27f13469 | 9686 | && i.types[1].bitfield.class == Reg |
b3a3496f L |
9687 | && (flag_code == CODE_32BIT |
9688 | ? i.op[1].regs->reg_type.bitfield.word | |
9689 | : i.op[1].regs->reg_type.bitfield.dword) | |
9690 | && ((i.base_reg == NULL && i.index_reg == NULL) | |
829f3fe1 JB |
9691 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
9692 | || (x86_elf_abi == X86_64_X32_ABI | |
9693 | && i.base_reg | |
b3a3496f L |
9694 | && i.base_reg->reg_num == RegIP |
9695 | && i.base_reg->reg_type.bitfield.qword)) | |
829f3fe1 JB |
9696 | #else |
9697 | || 0) | |
9698 | #endif | |
27f13469 L |
9699 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
9700 | return 0; | |
9701 | ||
c8f8eebc JB |
9702 | if (flag_code == CODE_32BIT) |
9703 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
9704 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
9705 | need = need_dword; |
9706 | else | |
9707 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 9708 | |
c8f8eebc JB |
9709 | for (op = 0; op < i.operands; op++) |
9710 | { | |
9711 | if (i.types[op].bitfield.class != Reg) | |
9712 | continue; | |
9713 | ||
9714 | switch (need) | |
9715 | { | |
9716 | case need_word: | |
9717 | if (i.op[op].regs->reg_type.bitfield.word) | |
9718 | continue; | |
9719 | break; | |
9720 | case need_dword: | |
9721 | if (i.op[op].regs->reg_type.bitfield.dword) | |
9722 | continue; | |
9723 | break; | |
9724 | case need_qword: | |
9725 | if (i.op[op].regs->reg_type.bitfield.qword) | |
9726 | continue; | |
9727 | break; | |
9728 | } | |
9729 | ||
9730 | as_bad (_("invalid register operand size for `%s'"), | |
76d3f746 | 9731 | insn_name (&i.tm)); |
c8f8eebc JB |
9732 | return 0; |
9733 | } | |
9734 | } | |
c0a30a9f L |
9735 | } |
9736 | ||
29b0f896 AM |
9737 | return 1; |
9738 | } | |
3e73aa7c | 9739 | |
29b0f896 | 9740 | static int |
543613e9 | 9741 | check_byte_reg (void) |
29b0f896 AM |
9742 | { |
9743 | int op; | |
543613e9 | 9744 | |
29b0f896 AM |
9745 | for (op = i.operands; --op >= 0;) |
9746 | { | |
dc821c5f | 9747 | /* Skip non-register operands. */ |
bab6aec1 | 9748 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
9749 | continue; |
9750 | ||
29b0f896 AM |
9751 | /* If this is an eight bit register, it's OK. If it's the 16 or |
9752 | 32 bit version of an eight bit register, we will just use the | |
9753 | low portion, and that's OK too. */ | |
dc821c5f | 9754 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
9755 | continue; |
9756 | ||
5a819eb9 | 9757 | /* I/O port address operands are OK too. */ |
75e5731b JB |
9758 | if (i.tm.operand_types[op].bitfield.instance == RegD |
9759 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
9760 | continue; |
9761 | ||
9706160a | 9762 | /* crc32 only wants its source operand checked here. */ |
7fc69528 | 9763 | if (i.tm.mnem_off == MN_crc32 && op != 0) |
9344ff29 L |
9764 | continue; |
9765 | ||
29b0f896 | 9766 | /* Any other register is bad. */ |
73c76375 JB |
9767 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
9768 | register_prefix, i.op[op].regs->reg_name, | |
76d3f746 | 9769 | insn_name (&i.tm), i.suffix); |
73c76375 | 9770 | return 0; |
29b0f896 AM |
9771 | } |
9772 | return 1; | |
9773 | } | |
9774 | ||
9775 | static int | |
e3bb37b5 | 9776 | check_long_reg (void) |
29b0f896 AM |
9777 | { |
9778 | int op; | |
9779 | ||
9780 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 9781 | /* Skip non-register operands. */ |
bab6aec1 | 9782 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 9783 | continue; |
29b0f896 AM |
9784 | /* Reject eight bit registers, except where the template requires |
9785 | them. (eg. movzb) */ | |
dc821c5f | 9786 | else if (i.types[op].bitfield.byte |
bab6aec1 | 9787 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 9788 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
9789 | && (i.tm.operand_types[op].bitfield.word |
9790 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 9791 | { |
a540244d L |
9792 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
9793 | register_prefix, | |
29b0f896 | 9794 | i.op[op].regs->reg_name, |
76d3f746 | 9795 | insn_name (&i.tm), |
29b0f896 AM |
9796 | i.suffix); |
9797 | return 0; | |
9798 | } | |
d9a1b711 JB |
9799 | /* Error if the e prefix on a general reg is missing, or if the r |
9800 | prefix on a general reg is present. */ | |
9801 | else if ((i.types[op].bitfield.word | |
9802 | || i.types[op].bitfield.qword) | |
bab6aec1 | 9803 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 9804 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 9805 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 9806 | { |
be4c5e58 L |
9807 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
9808 | register_prefix, i.op[op].regs->reg_name, | |
9809 | i.suffix); | |
9810 | return 0; | |
252b5132 | 9811 | } |
29b0f896 AM |
9812 | return 1; |
9813 | } | |
252b5132 | 9814 | |
29b0f896 | 9815 | static int |
e3bb37b5 | 9816 | check_qword_reg (void) |
29b0f896 AM |
9817 | { |
9818 | int op; | |
252b5132 | 9819 | |
29b0f896 | 9820 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 9821 | /* Skip non-register operands. */ |
bab6aec1 | 9822 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 9823 | continue; |
29b0f896 AM |
9824 | /* Reject eight bit registers, except where the template requires |
9825 | them. (eg. movzb) */ | |
dc821c5f | 9826 | else if (i.types[op].bitfield.byte |
bab6aec1 | 9827 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 9828 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 9829 | && (i.tm.operand_types[op].bitfield.word |
742b55c7 JB |
9830 | || i.tm.operand_types[op].bitfield.dword |
9831 | || i.tm.operand_types[op].bitfield.qword)) | |
29b0f896 | 9832 | { |
a540244d L |
9833 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
9834 | register_prefix, | |
29b0f896 | 9835 | i.op[op].regs->reg_name, |
76d3f746 | 9836 | insn_name (&i.tm), |
29b0f896 AM |
9837 | i.suffix); |
9838 | return 0; | |
9839 | } | |
d9a1b711 | 9840 | /* Error if the r prefix on a general reg is missing. */ |
dc821c5f JB |
9841 | else if ((i.types[op].bitfield.word |
9842 | || i.types[op].bitfield.dword) | |
bab6aec1 | 9843 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 9844 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 9845 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
9846 | { |
9847 | /* Prohibit these changes in the 64bit mode, since the | |
9848 | lowering is more complicated. */ | |
1cb0ab18 JB |
9849 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
9850 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
9851 | return 0; | |
252b5132 | 9852 | } |
29b0f896 AM |
9853 | return 1; |
9854 | } | |
252b5132 | 9855 | |
29b0f896 | 9856 | static int |
e3bb37b5 | 9857 | check_word_reg (void) |
29b0f896 AM |
9858 | { |
9859 | int op; | |
9860 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 9861 | /* Skip non-register operands. */ |
bab6aec1 | 9862 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 9863 | continue; |
29b0f896 AM |
9864 | /* Reject eight bit registers, except where the template requires |
9865 | them. (eg. movzb) */ | |
dc821c5f | 9866 | else if (i.types[op].bitfield.byte |
bab6aec1 | 9867 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 9868 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
9869 | && (i.tm.operand_types[op].bitfield.word |
9870 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 9871 | { |
a540244d L |
9872 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
9873 | register_prefix, | |
29b0f896 | 9874 | i.op[op].regs->reg_name, |
76d3f746 | 9875 | insn_name (&i.tm), |
29b0f896 AM |
9876 | i.suffix); |
9877 | return 0; | |
9878 | } | |
9706160a JB |
9879 | /* Error if the e or r prefix on a general reg is present. */ |
9880 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 9881 | || i.types[op].bitfield.qword) |
bab6aec1 | 9882 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 9883 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 9884 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 9885 | { |
9706160a JB |
9886 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
9887 | register_prefix, i.op[op].regs->reg_name, | |
9888 | i.suffix); | |
9889 | return 0; | |
29b0f896 AM |
9890 | } |
9891 | return 1; | |
9892 | } | |
252b5132 | 9893 | |
29b0f896 | 9894 | static int |
40fb9820 | 9895 | update_imm (unsigned int j) |
29b0f896 | 9896 | { |
bc0844ae | 9897 | i386_operand_type overlap = i.types[j]; |
c34d1cc9 JB |
9898 | |
9899 | if (i.tm.operand_types[j].bitfield.imm8 | |
9900 | && i.tm.operand_types[j].bitfield.imm8s | |
9901 | && overlap.bitfield.imm8 && overlap.bitfield.imm8s) | |
9902 | { | |
9903 | /* This combination is used on 8-bit immediates where e.g. $~0 is | |
9904 | desirable to permit. We're past operand type matching, so simply | |
9905 | put things back in the shape they were before introducing the | |
9906 | distinction between Imm8, Imm8S, and Imm8|Imm8S. */ | |
9907 | overlap.bitfield.imm8s = 0; | |
9908 | } | |
9909 | ||
be1643ff JB |
9910 | if (overlap.bitfield.imm8 |
9911 | + overlap.bitfield.imm8s | |
9912 | + overlap.bitfield.imm16 | |
9913 | + overlap.bitfield.imm32 | |
9914 | + overlap.bitfield.imm32s | |
9915 | + overlap.bitfield.imm64 > 1) | |
29b0f896 | 9916 | { |
05909f23 JB |
9917 | static const i386_operand_type imm16 = { .bitfield = { .imm16 = 1 } }; |
9918 | static const i386_operand_type imm32 = { .bitfield = { .imm32 = 1 } }; | |
9919 | static const i386_operand_type imm32s = { .bitfield = { .imm32s = 1 } }; | |
9920 | static const i386_operand_type imm16_32 = { .bitfield = | |
9921 | { .imm16 = 1, .imm32 = 1 } | |
9922 | }; | |
9923 | static const i386_operand_type imm16_32s = { .bitfield = | |
9924 | { .imm16 = 1, .imm32s = 1 } | |
9925 | }; | |
9926 | static const i386_operand_type imm16_32_32s = { .bitfield = | |
9927 | { .imm16 = 1, .imm32 = 1, .imm32s = 1 } | |
9928 | }; | |
9929 | ||
29b0f896 AM |
9930 | if (i.suffix) |
9931 | { | |
40fb9820 L |
9932 | i386_operand_type temp; |
9933 | ||
0dfbf9d7 | 9934 | operand_type_set (&temp, 0); |
7ab9ffdd | 9935 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
9936 | { |
9937 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
9938 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
9939 | } | |
9940 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
9941 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
9942 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
9943 | { | |
9944 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
9945 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
9946 | } | |
9947 | else | |
9948 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
9949 | overlap = temp; | |
29b0f896 | 9950 | } |
0dfbf9d7 L |
9951 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
9952 | || operand_type_equal (&overlap, &imm16_32) | |
9953 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 9954 | { |
f79d55e1 JB |
9955 | if ((flag_code == CODE_16BIT) |
9956 | ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W))) | |
65da13b5 | 9957 | overlap = imm16; |
40fb9820 | 9958 | else |
65da13b5 | 9959 | overlap = imm32s; |
29b0f896 | 9960 | } |
8bbb3ad8 JB |
9961 | else if (i.prefix[REX_PREFIX] & REX_W) |
9962 | overlap = operand_type_and (overlap, imm32s); | |
9963 | else if (i.prefix[DATA_PREFIX]) | |
9964 | overlap = operand_type_and (overlap, | |
9965 | flag_code != CODE_16BIT ? imm16 : imm32); | |
be1643ff JB |
9966 | if (overlap.bitfield.imm8 |
9967 | + overlap.bitfield.imm8s | |
9968 | + overlap.bitfield.imm16 | |
9969 | + overlap.bitfield.imm32 | |
9970 | + overlap.bitfield.imm32s | |
9971 | + overlap.bitfield.imm64 != 1) | |
29b0f896 | 9972 | { |
4eed87de AM |
9973 | as_bad (_("no instruction mnemonic suffix given; " |
9974 | "can't determine immediate size")); | |
29b0f896 AM |
9975 | return 0; |
9976 | } | |
9977 | } | |
40fb9820 | 9978 | i.types[j] = overlap; |
29b0f896 | 9979 | |
40fb9820 L |
9980 | return 1; |
9981 | } | |
9982 | ||
9983 | static int | |
9984 | finalize_imm (void) | |
9985 | { | |
bc0844ae | 9986 | unsigned int j, n; |
29b0f896 | 9987 | |
bc0844ae L |
9988 | /* Update the first 2 immediate operands. */ |
9989 | n = i.operands > 2 ? 2 : i.operands; | |
9990 | if (n) | |
9991 | { | |
9992 | for (j = 0; j < n; j++) | |
9993 | if (update_imm (j) == 0) | |
9994 | return 0; | |
40fb9820 | 9995 | |
bc0844ae L |
9996 | /* The 3rd operand can't be immediate operand. */ |
9997 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
9998 | } | |
29b0f896 AM |
9999 | |
10000 | return 1; | |
10001 | } | |
10002 | ||
0a3eba42 JB |
10003 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
10004 | bool do_sse2avx) | |
10005 | { | |
10006 | if (r->reg_flags & RegRex) | |
10007 | { | |
10008 | if (i.rex & rex_bit) | |
10009 | as_bad (_("same type of prefix used twice")); | |
10010 | i.rex |= rex_bit; | |
10011 | } | |
10012 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
10013 | { | |
10014 | gas_assert (i.vex.register_specifier == r); | |
10015 | i.vex.register_specifier += 8; | |
10016 | } | |
10017 | ||
10018 | if (r->reg_flags & RegVRex) | |
10019 | i.vrex |= rex_bit; | |
80d61d8d CL |
10020 | |
10021 | if (r->reg_flags & RegRex2) | |
10022 | i.rex2 |= rex_bit; | |
10023 | } | |
10024 | ||
10025 | static INLINE void | |
10026 | set_rex_rex2 (const reg_entry *r, unsigned int rex_bit) | |
10027 | { | |
10028 | if ((r->reg_flags & RegRex) != 0) | |
10029 | i.rex |= rex_bit; | |
10030 | if ((r->reg_flags & RegRex2) != 0) | |
10031 | i.rex2 |= rex_bit; | |
0a3eba42 JB |
10032 | } |
10033 | ||
29b0f896 | 10034 | static int |
e3bb37b5 | 10035 | process_operands (void) |
29b0f896 AM |
10036 | { |
10037 | /* Default segment register this instruction will use for memory | |
10038 | accesses. 0 means unknown. This is only for optimizing out | |
10039 | unnecessary segment overrides. */ | |
5e042380 | 10040 | const reg_entry *default_seg = NULL; |
29b0f896 | 10041 | |
3083f376 | 10042 | for (unsigned int j = 0; j < i.operands; j++) |
10043 | if (i.types[j].bitfield.instance != InstanceNone) | |
10044 | i.reg_operands--; | |
31b4cda3 | 10045 | |
a5aeccd9 JB |
10046 | if (i.tm.opcode_modifier.sse2avx) |
10047 | { | |
10048 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
10049 | need converting. */ | |
10050 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
10051 | i.prefix[REX_PREFIX] = 0; | |
10052 | i.rex_encoding = 0; | |
ebe82bfd | 10053 | i.rex2_encoding = 0; |
a5aeccd9 | 10054 | } |
c423d21a JB |
10055 | /* ImmExt should be processed after SSE2AVX. */ |
10056 | else if (i.tm.opcode_modifier.immext) | |
10057 | process_immext (); | |
a5aeccd9 | 10058 | |
ecb96e55 JB |
10059 | /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg, |
10060 | not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a | |
10061 | new destination operand here, while converting the source one to register | |
10062 | number 0. */ | |
10063 | if (i.tm.mnem_off == MN_tilezero) | |
10064 | { | |
10065 | i.op[1].regs = i.op[0].regs; | |
10066 | i.op[0].regs -= i.op[0].regs->reg_num; | |
10067 | i.types[1] = i.types[0]; | |
10068 | i.tm.operand_types[1] = i.tm.operand_types[0]; | |
10069 | i.flags[1] = i.flags[0]; | |
10070 | i.operands++; | |
10071 | i.reg_operands++; | |
10072 | i.tm.operands++; | |
10073 | } | |
10074 | ||
2426c15f | 10075 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 10076 | { |
05909f23 JB |
10077 | static const i386_operand_type regxmm = { |
10078 | .bitfield = { .class = RegSIMD, .xmmword = 1 } | |
10079 | }; | |
91d6fa6a NC |
10080 | unsigned int dupl = i.operands; |
10081 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
10082 | unsigned int j; |
10083 | ||
c0f3af97 | 10084 | /* The destination must be an xmm register. */ |
9c2799c2 | 10085 | gas_assert (i.reg_operands |
91d6fa6a | 10086 | && MAX_OPERANDS > dupl |
7ab9ffdd | 10087 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 10088 | |
75e5731b | 10089 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 10090 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 10091 | { |
95dfdd85 JB |
10092 | /* Keep xmm0 for instructions with VEX prefix and 3 |
10093 | sources. */ | |
10094 | i.tm.operand_types[0].bitfield.instance = InstanceNone; | |
10095 | i.tm.operand_types[0].bitfield.class = RegSIMD; | |
31b4cda3 | 10096 | i.reg_operands++; |
95dfdd85 | 10097 | goto duplicate; |
c0f3af97 | 10098 | } |
95dfdd85 JB |
10099 | |
10100 | if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0) | |
7ab9ffdd | 10101 | { |
aa180741 | 10102 | gas_assert ((MAX_OPERANDS - 1) > dupl); |
c0f3af97 L |
10103 | |
10104 | /* Add the implicit xmm0 for instructions with VEX prefix | |
10105 | and 3 sources. */ | |
10106 | for (j = i.operands; j > 0; j--) | |
10107 | { | |
10108 | i.op[j] = i.op[j - 1]; | |
10109 | i.types[j] = i.types[j - 1]; | |
10110 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 10111 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
10112 | } |
10113 | i.op[0].regs | |
629310ab | 10114 | = (const reg_entry *) str_hash_find (reg_hash, "xmm0"); |
7ab9ffdd | 10115 | i.types[0] = regxmm; |
c0f3af97 L |
10116 | i.tm.operand_types[0] = regxmm; |
10117 | ||
10118 | i.operands += 2; | |
10119 | i.reg_operands += 2; | |
10120 | i.tm.operands += 2; | |
10121 | ||
91d6fa6a | 10122 | dupl++; |
c0f3af97 | 10123 | dest++; |
91d6fa6a NC |
10124 | i.op[dupl] = i.op[dest]; |
10125 | i.types[dupl] = i.types[dest]; | |
10126 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 10127 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 10128 | } |
c0f3af97 L |
10129 | else |
10130 | { | |
dc1e8a47 | 10131 | duplicate: |
c0f3af97 L |
10132 | i.operands++; |
10133 | i.reg_operands++; | |
10134 | i.tm.operands++; | |
10135 | ||
91d6fa6a NC |
10136 | i.op[dupl] = i.op[dest]; |
10137 | i.types[dupl] = i.types[dest]; | |
10138 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 10139 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
10140 | } |
10141 | ||
10142 | if (i.tm.opcode_modifier.immext) | |
10143 | process_immext (); | |
10144 | } | |
75e5731b | 10145 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
bd782808 | 10146 | && i.tm.opcode_modifier.modrm) |
c0f3af97 L |
10147 | { |
10148 | unsigned int j; | |
10149 | ||
9fcfb3d7 L |
10150 | for (j = 1; j < i.operands; j++) |
10151 | { | |
10152 | i.op[j - 1] = i.op[j]; | |
10153 | i.types[j - 1] = i.types[j]; | |
10154 | ||
10155 | /* We need to adjust fields in i.tm since they are used by | |
10156 | build_modrm_byte. */ | |
10157 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
10158 | |
10159 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
10160 | } |
10161 | ||
31b4cda3 JB |
10162 | /* No adjustment to i.reg_operands: This was already done at the top |
10163 | of the function. */ | |
e2ec9d29 | 10164 | i.operands--; |
e2ec9d29 L |
10165 | i.tm.operands--; |
10166 | } | |
255571cd | 10167 | else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP) |
920d2ddc | 10168 | { |
a477a8c4 JB |
10169 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
10170 | ||
920d2ddc | 10171 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 10172 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
10173 | regnum = register_number (i.op[1].regs); |
10174 | first_reg_in_group = regnum & ~3; | |
10175 | last_reg_in_group = first_reg_in_group + 3; | |
10176 | if (regnum != first_reg_in_group) | |
10177 | as_warn (_("source register `%s%s' implicitly denotes" | |
10178 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
10179 | register_prefix, i.op[1].regs->reg_name, | |
10180 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
10181 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
76d3f746 | 10182 | insn_name (&i.tm)); |
a477a8c4 | 10183 | } |
255571cd | 10184 | else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE) |
e2ec9d29 L |
10185 | { |
10186 | /* The imul $imm, %reg instruction is converted into | |
10187 | imul $imm, %reg, %reg, and the clr %reg instruction | |
10188 | is converted into xor %reg, %reg. */ | |
10189 | ||
10190 | unsigned int first_reg_op; | |
10191 | ||
10192 | if (operand_type_check (i.types[0], reg)) | |
10193 | first_reg_op = 0; | |
10194 | else | |
10195 | first_reg_op = 1; | |
10196 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 10197 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 10198 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
10199 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
10200 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
10201 | i.operands++; | |
10202 | i.reg_operands++; | |
29b0f896 AM |
10203 | } |
10204 | ||
85b80b0f | 10205 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
10206 | { |
10207 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
10208 | must be put into the modrm byte). Now, we make the modrm and |
10209 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
10210 | |
10211 | default_seg = build_modrm_byte (); | |
bd782808 JB |
10212 | |
10213 | if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) | |
10214 | { | |
10215 | /* Warn about some common errors, but press on regardless. */ | |
10216 | if (i.operands == 2) | |
10217 | { | |
10218 | /* Reversed arguments on faddp or fmulp. */ | |
10219 | as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i.tm), | |
10220 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
10221 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
10222 | } | |
10223 | else if (i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
10224 | { | |
10225 | /* Extraneous `l' suffix on fp insn. */ | |
10226 | as_warn (_("translating to `%s %s%s'"), insn_name (&i.tm), | |
10227 | register_prefix, i.op[0].regs->reg_name); | |
10228 | } | |
10229 | } | |
29b0f896 | 10230 | } |
0ff3b7d0 | 10231 | else if (i.types[0].bitfield.class == SReg && !dot_insn ()) |
85b80b0f JB |
10232 | { |
10233 | if (flag_code != CODE_64BIT | |
10234 | ? i.tm.base_opcode == POP_SEG_SHORT | |
10235 | && i.op[0].regs->reg_num == 1 | |
389d00a5 | 10236 | : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff) |
85b80b0f JB |
10237 | && i.op[0].regs->reg_num < 4) |
10238 | { | |
10239 | as_bad (_("you can't `%s %s%s'"), | |
76d3f746 | 10240 | insn_name (&i.tm), register_prefix, i.op[0].regs->reg_name); |
85b80b0f JB |
10241 | return 0; |
10242 | } | |
389d00a5 | 10243 | if (i.op[0].regs->reg_num > 3 |
ddb62495 | 10244 | && i.tm.opcode_space == SPACE_BASE ) |
85b80b0f | 10245 | { |
389d00a5 | 10246 | i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff; |
ddb62495 | 10247 | i.tm.opcode_space = SPACE_0F; |
85b80b0f JB |
10248 | } |
10249 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
10250 | } | |
ddb62495 | 10251 | else if (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 10252 | && (i.tm.base_opcode & ~3) == MOV_AX_DISP32) |
29b0f896 | 10253 | { |
5e042380 | 10254 | default_seg = reg_ds; |
29b0f896 | 10255 | } |
40fb9820 | 10256 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
10257 | { |
10258 | /* For the string instructions that allow a segment override | |
10259 | on one of their operands, the default segment is ds. */ | |
5e042380 | 10260 | default_seg = reg_ds; |
29b0f896 | 10261 | } |
50128d0c | 10262 | else if (i.short_form) |
85b80b0f | 10263 | { |
0ff3b7d0 JB |
10264 | /* The register operand is in the 1st or 2nd non-immediate operand. */ |
10265 | const reg_entry *r = i.op[i.imm_operands].regs; | |
85b80b0f | 10266 | |
0ff3b7d0 JB |
10267 | if (!dot_insn () |
10268 | && r->reg_type.bitfield.instance == Accum | |
10269 | && i.op[i.imm_operands + 1].regs) | |
10270 | r = i.op[i.imm_operands + 1].regs; | |
85b80b0f | 10271 | /* Register goes in low 3 bits of opcode. */ |
4943d587 | 10272 | i.tm.base_opcode |= r->reg_num; |
0a3eba42 | 10273 | set_rex_vrex (r, REX_B, false); |
0ff3b7d0 JB |
10274 | |
10275 | if (dot_insn () && i.reg_operands == 2) | |
10276 | { | |
10277 | gas_assert (is_any_vex_encoding (&i.tm) | |
e346d50a | 10278 | || i.encoding != encoding_default); |
0ff3b7d0 JB |
10279 | i.vex.register_specifier = i.op[i.operands - 1].regs; |
10280 | } | |
10281 | } | |
10282 | else if (i.reg_operands == 1 | |
10283 | && !i.flags[i.operands - 1] | |
10284 | && i.tm.operand_types[i.operands - 1].bitfield.instance | |
10285 | == InstanceNone) | |
10286 | { | |
10287 | gas_assert (is_any_vex_encoding (&i.tm) | |
e346d50a | 10288 | || i.encoding != encoding_default); |
0ff3b7d0 | 10289 | i.vex.register_specifier = i.op[i.operands - 1].regs; |
85b80b0f | 10290 | } |
29b0f896 | 10291 | |
514a8bb0 | 10292 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
7fc69528 | 10293 | && i.tm.mnem_off == MN_lea) |
92334ad2 JB |
10294 | { |
10295 | if (!quiet_warnings) | |
76d3f746 | 10296 | as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm)); |
739d7649 | 10297 | if (optimize && !i.no_optimize) |
92334ad2 JB |
10298 | { |
10299 | i.seg[0] = NULL; | |
10300 | i.prefix[SEG_PREFIX] = 0; | |
10301 | } | |
10302 | } | |
52271982 AM |
10303 | |
10304 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
10305 | is neither the default nor the one already recorded from a prefix, |
10306 | use an opcode prefix to select it. If we never figured out what | |
10307 | the default segment is, then default_seg will be zero at this | |
10308 | point, and the specified segment prefix will always be used. */ | |
10309 | if (i.seg[0] | |
10310 | && i.seg[0] != default_seg | |
5e042380 | 10311 | && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX]) |
29b0f896 | 10312 | { |
5e042380 | 10313 | if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num])) |
29b0f896 AM |
10314 | return 0; |
10315 | } | |
10316 | return 1; | |
10317 | } | |
10318 | ||
5e042380 | 10319 | static const reg_entry * |
e3bb37b5 | 10320 | build_modrm_byte (void) |
29b0f896 | 10321 | { |
5e042380 | 10322 | const reg_entry *default_seg = NULL; |
ecb96e55 JB |
10323 | unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext |
10324 | /* Compensate for kludge in md_assemble(). */ | |
10325 | + i.tm.operand_types[0].bitfield.imm1; | |
10326 | unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext; | |
10327 | unsigned int v, op, reg_slot = ~0; | |
10328 | ||
10329 | /* Accumulator (in particular %st), shift count (%cl), and alike need | |
10330 | to be skipped just like immediate operands do. */ | |
10331 | if (i.tm.operand_types[source].bitfield.instance) | |
10332 | ++source; | |
10333 | while (i.tm.operand_types[dest].bitfield.instance) | |
10334 | --dest; | |
10335 | ||
10336 | for (op = source; op < i.operands; ++op) | |
10337 | if (i.tm.operand_types[op].bitfield.baseindex) | |
10338 | break; | |
c0f3af97 | 10339 | |
ecb96e55 | 10340 | if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4) |
c0f3af97 | 10341 | { |
4c2c6516 | 10342 | expressionS *exp; |
c0f3af97 | 10343 | |
a683cc34 | 10344 | /* There are 2 kinds of instructions: |
bed3d976 | 10345 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 10346 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 10347 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 10348 | ZMM register. |
bed3d976 | 10349 | 2. 4 operands: 4 register operands or 3 register operands |
0ff3b7d0 JB |
10350 | plus 1 memory operand, with VexXDS. |
10351 | 3. Other equivalent combinations when coming from s_insn(). */ | |
eea96d3f | 10352 | gas_assert (i.tm.opcode_modifier.vexvvvv |
0ff3b7d0 JB |
10353 | && i.tm.opcode_modifier.vexw); |
10354 | gas_assert (dot_insn () | |
10355 | || i.tm.operand_types[dest].bitfield.class == RegSIMD); | |
a683cc34 | 10356 | |
ecb96e55 JB |
10357 | /* Of the first two non-immediate operands the one with the template |
10358 | not allowing for a memory one is encoded in the immediate operand. */ | |
10359 | if (source == op) | |
10360 | reg_slot = source + 1; | |
48db9223 | 10361 | else |
ecb96e55 | 10362 | reg_slot = source++; |
48db9223 | 10363 | |
0ff3b7d0 JB |
10364 | if (!dot_insn ()) |
10365 | { | |
10366 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); | |
10367 | gas_assert (!(i.op[reg_slot].regs->reg_flags & RegVRex)); | |
10368 | } | |
10369 | else | |
10370 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class != ClassNone); | |
10371 | ||
a683cc34 | 10372 | if (i.imm_operands == 0) |
bed3d976 JB |
10373 | { |
10374 | /* When there is no immediate operand, generate an 8bit | |
10375 | immediate operand to encode the first operand. */ | |
10376 | exp = &im_expressions[i.imm_operands++]; | |
10377 | i.op[i.operands].imms = exp; | |
be1643ff | 10378 | i.types[i.operands].bitfield.imm8 = 1; |
bed3d976 JB |
10379 | i.operands++; |
10380 | ||
bed3d976 | 10381 | exp->X_op = O_constant; |
43234a1e | 10382 | } |
922d8de8 | 10383 | else |
bed3d976 | 10384 | { |
9d3bf266 JB |
10385 | gas_assert (i.imm_operands == 1); |
10386 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
10387 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 10388 | |
9d3bf266 JB |
10389 | /* Turn on Imm8 again so that output_imm will generate it. */ |
10390 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 10391 | |
0ff3b7d0 | 10392 | exp = i.op[0].imms; |
bed3d976 | 10393 | } |
0ff3b7d0 | 10394 | exp->X_add_number |= register_number (i.op[reg_slot].regs) |
706ce984 | 10395 | << (3 + !(i.tm.opcode_modifier.evex |
e346d50a | 10396 | || i.encoding == encoding_evex)); |
c0f3af97 | 10397 | } |
f12dc422 | 10398 | |
3083f376 | 10399 | if (i.tm.opcode_modifier.vexvvvv == VexVVVV_DST) |
10400 | { | |
10401 | v = dest; | |
10402 | dest-- ; | |
10403 | } | |
10404 | else | |
10405 | { | |
10406 | for (v = source + 1; v < dest; ++v) | |
10407 | if (v != reg_slot) | |
10408 | break; | |
10409 | if (v >= dest) | |
10410 | v = ~0; | |
10411 | } | |
ecb96e55 JB |
10412 | if (i.tm.extension_opcode != None) |
10413 | { | |
10414 | if (dest != source) | |
10415 | v = dest; | |
10416 | dest = ~0; | |
10417 | } | |
10418 | gas_assert (source < dest); | |
10419 | if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES | |
10420 | && source != op) | |
10421 | { | |
10422 | unsigned int tmp = source; | |
f12dc422 | 10423 | |
ecb96e55 JB |
10424 | source = v; |
10425 | v = tmp; | |
10426 | } | |
29b0f896 | 10427 | |
ecb96e55 JB |
10428 | if (v < MAX_OPERANDS) |
10429 | { | |
10430 | gas_assert (i.tm.opcode_modifier.vexvvvv); | |
10431 | i.vex.register_specifier = i.op[v].regs; | |
29b0f896 | 10432 | } |
c0f3af97 | 10433 | |
ecb96e55 JB |
10434 | if (op < i.operands) |
10435 | { | |
29b0f896 AM |
10436 | if (i.mem_operands) |
10437 | { | |
10438 | unsigned int fake_zero_displacement = 0; | |
4eed87de | 10439 | |
ecb96e55 | 10440 | gas_assert (i.flags[op] & Operand_Mem); |
29b0f896 | 10441 | |
63112cd6 | 10442 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 10443 | { |
260cd341 LC |
10444 | /* The index register of VSIB shouldn't be RegIZ. */ |
10445 | if (i.tm.opcode_modifier.sib != SIBMEM | |
10446 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
10447 | abort (); |
10448 | ||
10449 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
10450 | if (!i.base_reg) | |
10451 | { | |
10452 | i.sib.base = NO_BASE_REGISTER; | |
10453 | i.sib.scale = i.log2_scale_factor; | |
2f2be86b | 10454 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 10455 | i.types[op].bitfield.disp32 = 1; |
6c30d220 | 10456 | } |
260cd341 LC |
10457 | |
10458 | /* Since the mandatory SIB always has index register, so | |
10459 | the code logic remains unchanged. The non-mandatory SIB | |
10460 | without index register is allowed and will be handled | |
10461 | later. */ | |
10462 | if (i.index_reg) | |
10463 | { | |
10464 | if (i.index_reg->reg_num == RegIZ) | |
10465 | i.sib.index = NO_INDEX_REGISTER; | |
10466 | else | |
10467 | i.sib.index = i.index_reg->reg_num; | |
5b7c81bd | 10468 | set_rex_vrex (i.index_reg, REX_X, false); |
260cd341 | 10469 | } |
6c30d220 L |
10470 | } |
10471 | ||
5e042380 | 10472 | default_seg = reg_ds; |
29b0f896 AM |
10473 | |
10474 | if (i.base_reg == 0) | |
10475 | { | |
10476 | i.rm.mode = 0; | |
10477 | if (!i.disp_operands) | |
9bb129e8 | 10478 | fake_zero_displacement = 1; |
29b0f896 AM |
10479 | if (i.index_reg == 0) |
10480 | { | |
260cd341 LC |
10481 | /* Both check for VSIB and mandatory non-vector SIB. */ |
10482 | gas_assert (!i.tm.opcode_modifier.sib | |
10483 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 10484 | /* Operand is just <disp> */ |
2f2be86b | 10485 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
20f0a1fc | 10486 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
10487 | { |
10488 | /* 64bit mode overwrites the 32bit absolute | |
10489 | addressing by RIP relative addressing and | |
10490 | absolute addressing is encoded by one of the | |
10491 | redundant SIB forms. */ | |
10492 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
10493 | i.sib.base = NO_BASE_REGISTER; | |
10494 | i.sib.index = NO_INDEX_REGISTER; | |
a775efc8 | 10495 | i.types[op].bitfield.disp32 = 1; |
20f0a1fc | 10496 | } |
fc225355 L |
10497 | else if ((flag_code == CODE_16BIT) |
10498 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
10499 | { |
10500 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2f2be86b | 10501 | i.types[op].bitfield.disp16 = 1; |
20f0a1fc NC |
10502 | } |
10503 | else | |
10504 | { | |
10505 | i.rm.regmem = NO_BASE_REGISTER; | |
2f2be86b | 10506 | i.types[op].bitfield.disp32 = 1; |
29b0f896 AM |
10507 | } |
10508 | } | |
63112cd6 | 10509 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 10510 | { |
6c30d220 | 10511 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 10512 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
10513 | i.sib.index = NO_INDEX_REGISTER; |
10514 | else | |
10515 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
10516 | i.sib.base = NO_BASE_REGISTER; |
10517 | i.sib.scale = i.log2_scale_factor; | |
10518 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2f2be86b | 10519 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 10520 | i.types[op].bitfield.disp32 = 1; |
80d61d8d | 10521 | set_rex_rex2 (i.index_reg, REX_X); |
29b0f896 AM |
10522 | } |
10523 | } | |
10524 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 10525 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 10526 | { |
63112cd6 | 10527 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 10528 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
10529 | i.types[op].bitfield.disp8 = 0; |
10530 | i.types[op].bitfield.disp16 = 0; | |
a775efc8 | 10531 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 10532 | i.types[op].bitfield.disp64 = 0; |
71903a11 | 10533 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
10534 | if (! i.disp_operands) |
10535 | fake_zero_displacement = 1; | |
29b0f896 | 10536 | } |
dc821c5f | 10537 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 10538 | { |
63112cd6 | 10539 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
10540 | switch (i.base_reg->reg_num) |
10541 | { | |
10542 | case 3: /* (%bx) */ | |
10543 | if (i.index_reg == 0) | |
10544 | i.rm.regmem = 7; | |
10545 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
10546 | i.rm.regmem = i.index_reg->reg_num - 6; | |
10547 | break; | |
10548 | case 5: /* (%bp) */ | |
5e042380 | 10549 | default_seg = reg_ss; |
29b0f896 AM |
10550 | if (i.index_reg == 0) |
10551 | { | |
10552 | i.rm.regmem = 6; | |
40fb9820 | 10553 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
10554 | { |
10555 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 10556 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
10557 | i.types[op].bitfield.disp16 = 1; |
10558 | else | |
10559 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 10560 | fake_zero_displacement = 1; |
29b0f896 AM |
10561 | } |
10562 | } | |
10563 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
10564 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
10565 | break; | |
10566 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
10567 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
10568 | } | |
41eb8e88 L |
10569 | if (!fake_zero_displacement |
10570 | && !i.disp_operands | |
10571 | && i.disp_encoding) | |
10572 | { | |
10573 | fake_zero_displacement = 1; | |
10574 | if (i.disp_encoding == disp_encoding_8bit) | |
10575 | i.types[op].bitfield.disp8 = 1; | |
10576 | else | |
10577 | i.types[op].bitfield.disp16 = 1; | |
10578 | } | |
29b0f896 AM |
10579 | i.rm.mode = mode_from_disp_size (i.types[op]); |
10580 | } | |
10581 | else /* i.base_reg and 32/64 bit mode */ | |
10582 | { | |
a9aabc23 | 10583 | if (operand_type_check (i.types[op], disp)) |
40fb9820 | 10584 | { |
73053c1f JB |
10585 | i.types[op].bitfield.disp16 = 0; |
10586 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 10587 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 10588 | } |
20f0a1fc | 10589 | |
63112cd6 | 10590 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 10591 | i.rm.regmem = i.base_reg->reg_num; |
80d61d8d | 10592 | set_rex_rex2 (i.base_reg, REX_B); |
29b0f896 AM |
10593 | i.sib.base = i.base_reg->reg_num; |
10594 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
10595 | complications. */ | |
848930b2 JB |
10596 | if (!(i.base_reg->reg_flags & RegRex) |
10597 | && (i.base_reg->reg_num == EBP_REG_NUM | |
10598 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
5e042380 | 10599 | default_seg = reg_ss; |
848930b2 | 10600 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 10601 | { |
848930b2 | 10602 | fake_zero_displacement = 1; |
1a02d6b0 L |
10603 | if (i.disp_encoding == disp_encoding_32bit) |
10604 | i.types[op].bitfield.disp32 = 1; | |
10605 | else | |
10606 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
10607 | } |
10608 | i.sib.scale = i.log2_scale_factor; | |
10609 | if (i.index_reg == 0) | |
10610 | { | |
260cd341 LC |
10611 | /* Only check for VSIB. */ |
10612 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
10613 | && i.tm.opcode_modifier.sib != VECSIB256 | |
10614 | && i.tm.opcode_modifier.sib != VECSIB512); | |
10615 | ||
29b0f896 AM |
10616 | /* <disp>(%esp) becomes two byte modrm with no index |
10617 | register. We've already stored the code for esp | |
10618 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
10619 | Any base register besides %esp will not use the | |
10620 | extra modrm byte. */ | |
10621 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 10622 | } |
63112cd6 | 10623 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 10624 | { |
e968fc9b | 10625 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
10626 | i.sib.index = NO_INDEX_REGISTER; |
10627 | else | |
10628 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 | 10629 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
80d61d8d | 10630 | set_rex_rex2 (i.index_reg, REX_X); |
29b0f896 | 10631 | } |
67a4f2b7 AO |
10632 | |
10633 | if (i.disp_operands | |
10634 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
10635 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
10636 | i.rm.mode = 0; | |
10637 | else | |
a501d77e L |
10638 | { |
10639 | if (!fake_zero_displacement | |
10640 | && !i.disp_operands | |
10641 | && i.disp_encoding) | |
10642 | { | |
10643 | fake_zero_displacement = 1; | |
10644 | if (i.disp_encoding == disp_encoding_8bit) | |
10645 | i.types[op].bitfield.disp8 = 1; | |
10646 | else | |
10647 | i.types[op].bitfield.disp32 = 1; | |
10648 | } | |
10649 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
10650 | } | |
29b0f896 | 10651 | } |
252b5132 | 10652 | |
29b0f896 AM |
10653 | if (fake_zero_displacement) |
10654 | { | |
10655 | /* Fakes a zero displacement assuming that i.types[op] | |
10656 | holds the correct displacement size. */ | |
10657 | expressionS *exp; | |
10658 | ||
9c2799c2 | 10659 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
10660 | exp = &disp_expressions[i.disp_operands++]; |
10661 | i.op[op].disps = exp; | |
10662 | exp->X_op = O_constant; | |
10663 | exp->X_add_number = 0; | |
10664 | exp->X_add_symbol = (symbolS *) 0; | |
10665 | exp->X_op_symbol = (symbolS *) 0; | |
10666 | } | |
10667 | } | |
ecb96e55 JB |
10668 | else |
10669 | { | |
10670 | i.rm.mode = 3; | |
10671 | i.rm.regmem = i.op[op].regs->reg_num; | |
10672 | set_rex_vrex (i.op[op].regs, REX_B, false); | |
10673 | } | |
252b5132 | 10674 | |
ecb96e55 JB |
10675 | if (op == dest) |
10676 | dest = ~0; | |
10677 | if (op == source) | |
10678 | source = ~0; | |
10679 | } | |
10680 | else | |
10681 | { | |
10682 | i.rm.mode = 3; | |
10683 | if (!i.tm.opcode_modifier.regmem) | |
f88c9eb0 | 10684 | { |
ecb96e55 JB |
10685 | gas_assert (source < MAX_OPERANDS); |
10686 | i.rm.regmem = i.op[source].regs->reg_num; | |
10687 | set_rex_vrex (i.op[source].regs, REX_B, | |
10688 | dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx); | |
10689 | source = ~0; | |
f88c9eb0 | 10690 | } |
ecb96e55 | 10691 | else |
29b0f896 | 10692 | { |
ecb96e55 JB |
10693 | gas_assert (dest < MAX_OPERANDS); |
10694 | i.rm.regmem = i.op[dest].regs->reg_num; | |
10695 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); | |
10696 | dest = ~0; | |
29b0f896 | 10697 | } |
ecb96e55 | 10698 | } |
252b5132 | 10699 | |
ecb96e55 JB |
10700 | /* Fill in i.rm.reg field with extension opcode (if any) or the |
10701 | appropriate register. */ | |
10702 | if (i.tm.extension_opcode != None) | |
10703 | i.rm.reg = i.tm.extension_opcode; | |
10704 | else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS) | |
10705 | { | |
10706 | i.rm.reg = i.op[dest].regs->reg_num; | |
10707 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); | |
10708 | } | |
10709 | else | |
10710 | { | |
10711 | gas_assert (source < MAX_OPERANDS); | |
10712 | i.rm.reg = i.op[source].regs->reg_num; | |
10713 | set_rex_vrex (i.op[source].regs, REX_R, false); | |
29b0f896 | 10714 | } |
ecb96e55 JB |
10715 | |
10716 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) | |
10717 | { | |
10718 | gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR); | |
10719 | i.rex &= ~REX_R; | |
10720 | add_prefix (LOCK_PREFIX_OPCODE); | |
10721 | } | |
10722 | ||
29b0f896 AM |
10723 | return default_seg; |
10724 | } | |
252b5132 | 10725 | |
48ef937e JB |
10726 | static INLINE void |
10727 | frag_opcode_byte (unsigned char byte) | |
10728 | { | |
10729 | if (now_seg != absolute_section) | |
10730 | FRAG_APPEND_1_CHAR (byte); | |
10731 | else | |
10732 | ++abs_section_offset; | |
10733 | } | |
10734 | ||
376cd056 JB |
10735 | static unsigned int |
10736 | flip_code16 (unsigned int code16) | |
10737 | { | |
10738 | gas_assert (i.tm.operands == 1); | |
10739 | ||
10740 | return !(i.prefix[REX_PREFIX] & REX_W) | |
10741 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
376cd056 JB |
10742 | : i.tm.operand_types[0].bitfield.disp16) |
10743 | ? CODE16 : 0; | |
10744 | } | |
10745 | ||
29b0f896 | 10746 | static void |
e3bb37b5 | 10747 | output_branch (void) |
29b0f896 AM |
10748 | { |
10749 | char *p; | |
f8a5c266 | 10750 | int size; |
29b0f896 AM |
10751 | int code16; |
10752 | int prefix; | |
10753 | relax_substateT subtype; | |
10754 | symbolS *sym; | |
10755 | offsetT off; | |
10756 | ||
48ef937e JB |
10757 | if (now_seg == absolute_section) |
10758 | { | |
10759 | as_bad (_("relaxable branches not supported in absolute section")); | |
10760 | return; | |
10761 | } | |
10762 | ||
f8a5c266 | 10763 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
1a42a9fe | 10764 | size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL; |
29b0f896 AM |
10765 | |
10766 | prefix = 0; | |
10767 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 10768 | { |
29b0f896 AM |
10769 | prefix = 1; |
10770 | i.prefixes -= 1; | |
376cd056 | 10771 | code16 ^= flip_code16(code16); |
252b5132 | 10772 | } |
29b0f896 AM |
10773 | /* Pentium4 branch hints. */ |
10774 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
10775 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 10776 | { |
29b0f896 AM |
10777 | prefix++; |
10778 | i.prefixes--; | |
10779 | } | |
10780 | if (i.prefix[REX_PREFIX] != 0) | |
10781 | { | |
10782 | prefix++; | |
10783 | i.prefixes--; | |
2f66722d AM |
10784 | } |
10785 | ||
7e8b059b L |
10786 | /* BND prefixed jump. */ |
10787 | if (i.prefix[BND_PREFIX] != 0) | |
10788 | { | |
6cb0a70e JB |
10789 | prefix++; |
10790 | i.prefixes--; | |
7e8b059b L |
10791 | } |
10792 | ||
f2810fe0 | 10793 | if (i.prefixes != 0) |
76d3f746 | 10794 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
29b0f896 AM |
10795 | |
10796 | /* It's always a symbol; End frag & setup for relax. | |
10797 | Make sure there is enough room in this frag for the largest | |
10798 | instruction we may generate in md_convert_frag. This is 2 | |
10799 | bytes for the opcode and room for the prefix and largest | |
10800 | displacement. */ | |
10801 | frag_grow (prefix + 2 + 4); | |
10802 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
10803 | p = frag_more (prefix + 1); | |
10804 | if (i.prefix[DATA_PREFIX] != 0) | |
10805 | *p++ = DATA_PREFIX_OPCODE; | |
10806 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
10807 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
10808 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
10809 | if (i.prefix[BND_PREFIX] != 0) |
10810 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
10811 | if (i.prefix[REX_PREFIX] != 0) |
10812 | *p++ = i.prefix[REX_PREFIX]; | |
10813 | *p = i.tm.base_opcode; | |
10814 | ||
10815 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 10816 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 10817 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 10818 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 10819 | else |
f8a5c266 | 10820 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 10821 | subtype |= code16; |
3e73aa7c | 10822 | |
29b0f896 AM |
10823 | sym = i.op[0].disps->X_add_symbol; |
10824 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 10825 | |
29b0f896 AM |
10826 | if (i.op[0].disps->X_op != O_constant |
10827 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 10828 | { |
29b0f896 AM |
10829 | /* Handle complex expressions. */ |
10830 | sym = make_expr_symbol (i.op[0].disps); | |
10831 | off = 0; | |
10832 | } | |
3e73aa7c | 10833 | |
29b0f896 AM |
10834 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
10835 | Pass reloc in fr_var. */ | |
d258b828 | 10836 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 10837 | } |
3e73aa7c | 10838 | |
bd7ab16b L |
10839 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10840 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
10841 | symbol S. */ | |
10842 | ||
5b7c81bd | 10843 | static bool |
bd7ab16b L |
10844 | need_plt32_p (symbolS *s) |
10845 | { | |
10846 | /* PLT32 relocation is ELF only. */ | |
10847 | if (!IS_ELF) | |
5b7c81bd | 10848 | return false; |
bd7ab16b | 10849 | |
a5def729 RO |
10850 | #ifdef TE_SOLARIS |
10851 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
10852 | krtld support it. */ | |
5b7c81bd | 10853 | return false; |
a5def729 RO |
10854 | #endif |
10855 | ||
bd7ab16b L |
10856 | /* Since there is no need to prepare for PLT branch on x86-64, we |
10857 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
10858 | be used as a marker for 32-bit PC-relative branches. */ | |
10859 | if (!object_64bit) | |
5b7c81bd | 10860 | return false; |
bd7ab16b | 10861 | |
44365e88 | 10862 | if (s == NULL) |
5b7c81bd | 10863 | return false; |
44365e88 | 10864 | |
bd7ab16b L |
10865 | /* Weak or undefined symbol need PLT32 relocation. */ |
10866 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
5b7c81bd | 10867 | return true; |
bd7ab16b L |
10868 | |
10869 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
10870 | if (! S_IS_EXTERNAL (s)) | |
5b7c81bd | 10871 | return false; |
bd7ab16b L |
10872 | |
10873 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
10874 | non-default visibilities are treated as normal global symbol | |
10875 | so that PLT32 relocation can be used as a marker for 32-bit | |
10876 | PC-relative branches. It is useful for linker relaxation. */ | |
5b7c81bd | 10877 | return true; |
bd7ab16b L |
10878 | } |
10879 | #endif | |
10880 | ||
29b0f896 | 10881 | static void |
e3bb37b5 | 10882 | output_jump (void) |
29b0f896 AM |
10883 | { |
10884 | char *p; | |
10885 | int size; | |
3e02c1cc | 10886 | fixS *fixP; |
bd7ab16b | 10887 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 10888 | |
0cfa3eb3 | 10889 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
10890 | { |
10891 | /* This is a loop or jecxz type instruction. */ | |
10892 | size = 1; | |
10893 | if (i.prefix[ADDR_PREFIX] != 0) | |
10894 | { | |
48ef937e | 10895 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
10896 | i.prefixes -= 1; |
10897 | } | |
10898 | /* Pentium4 branch hints. */ | |
10899 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
10900 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
10901 | { | |
48ef937e | 10902 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 10903 | i.prefixes--; |
3e73aa7c JH |
10904 | } |
10905 | } | |
29b0f896 AM |
10906 | else |
10907 | { | |
10908 | int code16; | |
3e73aa7c | 10909 | |
29b0f896 AM |
10910 | code16 = 0; |
10911 | if (flag_code == CODE_16BIT) | |
10912 | code16 = CODE16; | |
3e73aa7c | 10913 | |
29b0f896 AM |
10914 | if (i.prefix[DATA_PREFIX] != 0) |
10915 | { | |
48ef937e | 10916 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 10917 | i.prefixes -= 1; |
376cd056 | 10918 | code16 ^= flip_code16(code16); |
29b0f896 | 10919 | } |
252b5132 | 10920 | |
29b0f896 AM |
10921 | size = 4; |
10922 | if (code16) | |
10923 | size = 2; | |
10924 | } | |
9fcc94b6 | 10925 | |
6cb0a70e JB |
10926 | /* BND prefixed jump. */ |
10927 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 10928 | { |
48ef937e | 10929 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
10930 | i.prefixes -= 1; |
10931 | } | |
252b5132 | 10932 | |
6cb0a70e | 10933 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 10934 | { |
48ef937e | 10935 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
10936 | i.prefixes -= 1; |
10937 | } | |
10938 | ||
f2810fe0 | 10939 | if (i.prefixes != 0) |
76d3f746 | 10940 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
e0890092 | 10941 | |
48ef937e JB |
10942 | if (now_seg == absolute_section) |
10943 | { | |
9a182d04 | 10944 | abs_section_offset += i.opcode_length + size; |
48ef937e JB |
10945 | return; |
10946 | } | |
10947 | ||
9a182d04 JB |
10948 | p = frag_more (i.opcode_length + size); |
10949 | switch (i.opcode_length) | |
42164a71 L |
10950 | { |
10951 | case 2: | |
10952 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 10953 | /* Fall through. */ |
42164a71 L |
10954 | case 1: |
10955 | *p++ = i.tm.base_opcode; | |
10956 | break; | |
10957 | default: | |
10958 | abort (); | |
10959 | } | |
e0890092 | 10960 | |
bd7ab16b | 10961 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
10962 | if (flag_code == CODE_64BIT && size == 4 |
10963 | && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0 | |
bd7ab16b L |
10964 | && need_plt32_p (i.op[0].disps->X_add_symbol)) |
10965 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
10966 | #endif | |
10967 | ||
10968 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
10969 | ||
3e02c1cc | 10970 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 10971 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc | 10972 | |
eb19308f JB |
10973 | /* All jumps handled here are signed, but don't unconditionally use a |
10974 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
10975 | around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN) | |
10976 | respectively. */ | |
10977 | switch (size) | |
10978 | { | |
10979 | case 1: | |
10980 | fixP->fx_signed = 1; | |
10981 | break; | |
10982 | ||
10983 | case 2: | |
7fc69528 | 10984 | if (i.tm.mnem_off == MN_xbegin) |
eb19308f JB |
10985 | fixP->fx_signed = 1; |
10986 | break; | |
10987 | ||
10988 | case 4: | |
10989 | if (flag_code == CODE_64BIT) | |
10990 | fixP->fx_signed = 1; | |
10991 | break; | |
10992 | } | |
29b0f896 | 10993 | } |
e0890092 | 10994 | |
29b0f896 | 10995 | static void |
e3bb37b5 | 10996 | output_interseg_jump (void) |
29b0f896 AM |
10997 | { |
10998 | char *p; | |
10999 | int size; | |
11000 | int prefix; | |
11001 | int code16; | |
252b5132 | 11002 | |
29b0f896 AM |
11003 | code16 = 0; |
11004 | if (flag_code == CODE_16BIT) | |
11005 | code16 = CODE16; | |
a217f122 | 11006 | |
29b0f896 AM |
11007 | prefix = 0; |
11008 | if (i.prefix[DATA_PREFIX] != 0) | |
11009 | { | |
11010 | prefix = 1; | |
11011 | i.prefixes -= 1; | |
11012 | code16 ^= CODE16; | |
11013 | } | |
6cb0a70e JB |
11014 | |
11015 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 11016 | |
29b0f896 AM |
11017 | size = 4; |
11018 | if (code16) | |
11019 | size = 2; | |
252b5132 | 11020 | |
f2810fe0 | 11021 | if (i.prefixes != 0) |
76d3f746 | 11022 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
252b5132 | 11023 | |
48ef937e JB |
11024 | if (now_seg == absolute_section) |
11025 | { | |
11026 | abs_section_offset += prefix + 1 + 2 + size; | |
11027 | return; | |
11028 | } | |
11029 | ||
29b0f896 AM |
11030 | /* 1 opcode; 2 segment; offset */ |
11031 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 11032 | |
29b0f896 AM |
11033 | if (i.prefix[DATA_PREFIX] != 0) |
11034 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 11035 | |
29b0f896 AM |
11036 | if (i.prefix[REX_PREFIX] != 0) |
11037 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 11038 | |
29b0f896 AM |
11039 | *p++ = i.tm.base_opcode; |
11040 | if (i.op[1].imms->X_op == O_constant) | |
11041 | { | |
11042 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 11043 | |
29b0f896 AM |
11044 | if (size == 2 |
11045 | && !fits_in_unsigned_word (n) | |
11046 | && !fits_in_signed_word (n)) | |
11047 | { | |
11048 | as_bad (_("16-bit jump out of range")); | |
11049 | return; | |
11050 | } | |
11051 | md_number_to_chars (p, n, size); | |
11052 | } | |
11053 | else | |
11054 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 11055 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
6d96a594 C |
11056 | |
11057 | p += size; | |
11058 | if (i.op[0].imms->X_op == O_constant) | |
11059 | md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2); | |
11060 | else | |
11061 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
11062 | i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0])); | |
29b0f896 | 11063 | } |
a217f122 | 11064 | |
b4a3a7b4 L |
11065 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11066 | void | |
11067 | x86_cleanup (void) | |
11068 | { | |
11069 | char *p; | |
11070 | asection *seg = now_seg; | |
11071 | subsegT subseg = now_subseg; | |
11072 | asection *sec; | |
11073 | unsigned int alignment, align_size_1; | |
11074 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
11075 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
11076 | unsigned int padding; | |
11077 | ||
1273b2f8 | 11078 | if (!IS_ELF || !x86_used_note) |
b4a3a7b4 L |
11079 | return; |
11080 | ||
b4a3a7b4 L |
11081 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
11082 | ||
11083 | /* The .note.gnu.property section layout: | |
11084 | ||
11085 | Field Length Contents | |
11086 | ---- ---- ---- | |
11087 | n_namsz 4 4 | |
11088 | n_descsz 4 The note descriptor size | |
11089 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
11090 | n_name 4 "GNU" | |
11091 | n_desc n_descsz The program property array | |
11092 | .... .... .... | |
11093 | */ | |
11094 | ||
11095 | /* Create the .note.gnu.property section. */ | |
11096 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 11097 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
11098 | (SEC_ALLOC |
11099 | | SEC_LOAD | |
11100 | | SEC_DATA | |
11101 | | SEC_HAS_CONTENTS | |
11102 | | SEC_READONLY)); | |
11103 | ||
11104 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
11105 | { | |
11106 | align_size_1 = 7; | |
11107 | alignment = 3; | |
11108 | } | |
11109 | else | |
11110 | { | |
11111 | align_size_1 = 3; | |
11112 | alignment = 2; | |
11113 | } | |
11114 | ||
fd361982 | 11115 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
11116 | elf_section_type (sec) = SHT_NOTE; |
11117 | ||
1273b2f8 L |
11118 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size |
11119 | + 4-byte data */ | |
11120 | isa_1_descsz_raw = 4 + 4 + 4; | |
11121 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
11122 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
b4a3a7b4 L |
11123 | |
11124 | feature_2_descsz_raw = isa_1_descsz; | |
11125 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
1273b2f8 | 11126 | + 4-byte data */ |
b4a3a7b4 L |
11127 | feature_2_descsz_raw += 4 + 4 + 4; |
11128 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
11129 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
11130 | & ~align_size_1); | |
11131 | ||
11132 | descsz = feature_2_descsz; | |
11133 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
11134 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
11135 | ||
11136 | /* Write n_namsz. */ | |
11137 | md_number_to_chars (p, (valueT) 4, 4); | |
11138 | ||
11139 | /* Write n_descsz. */ | |
11140 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
11141 | ||
11142 | /* Write n_type. */ | |
11143 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
11144 | ||
11145 | /* Write n_name. */ | |
11146 | memcpy (p + 4 * 3, "GNU", 4); | |
11147 | ||
1273b2f8 L |
11148 | /* Write 4-byte type. */ |
11149 | md_number_to_chars (p + 4 * 4, | |
11150 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
b4a3a7b4 | 11151 | |
1273b2f8 L |
11152 | /* Write 4-byte data size. */ |
11153 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
b4a3a7b4 | 11154 | |
1273b2f8 L |
11155 | /* Write 4-byte data. */ |
11156 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
b4a3a7b4 | 11157 | |
1273b2f8 L |
11158 | /* Zero out paddings. */ |
11159 | padding = isa_1_descsz - isa_1_descsz_raw; | |
11160 | if (padding) | |
11161 | memset (p + 4 * 7, 0, padding); | |
b4a3a7b4 L |
11162 | |
11163 | /* Write 4-byte type. */ | |
11164 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
11165 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
11166 | ||
11167 | /* Write 4-byte data size. */ | |
11168 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
11169 | ||
11170 | /* Write 4-byte data. */ | |
11171 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
11172 | (valueT) x86_feature_2_used, 4); | |
11173 | ||
11174 | /* Zero out paddings. */ | |
11175 | padding = feature_2_descsz - feature_2_descsz_raw; | |
11176 | if (padding) | |
11177 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
11178 | ||
11179 | /* We probably can't restore the current segment, for there likely | |
11180 | isn't one yet... */ | |
11181 | if (seg && subseg) | |
11182 | subseg_set (seg, subseg); | |
11183 | } | |
b52c4ee4 IB |
11184 | |
11185 | bool | |
11186 | x86_support_sframe_p (void) | |
11187 | { | |
3e3e792a | 11188 | /* At this time, SFrame stack trace is supported for AMD64 ABI only. */ |
b52c4ee4 IB |
11189 | return (x86_elf_abi == X86_64_ABI); |
11190 | } | |
11191 | ||
11192 | bool | |
11193 | x86_sframe_ra_tracking_p (void) | |
11194 | { | |
11195 | /* In AMD64, return address is always stored on the stack at a fixed offset | |
11196 | from the CFA (provided via x86_sframe_cfa_ra_offset ()). | |
11197 | Do not track explicitly via an SFrame Frame Row Entry. */ | |
11198 | return false; | |
11199 | } | |
11200 | ||
11201 | offsetT | |
11202 | x86_sframe_cfa_ra_offset (void) | |
11203 | { | |
11204 | gas_assert (x86_elf_abi == X86_64_ABI); | |
11205 | return (offsetT) -8; | |
11206 | } | |
11207 | ||
11208 | unsigned char | |
11209 | x86_sframe_get_abi_arch (void) | |
11210 | { | |
11211 | unsigned char sframe_abi_arch = 0; | |
11212 | ||
11213 | if (x86_support_sframe_p ()) | |
11214 | { | |
11215 | gas_assert (!target_big_endian); | |
11216 | sframe_abi_arch = SFRAME_ABI_AMD64_ENDIAN_LITTLE; | |
11217 | } | |
11218 | ||
11219 | return sframe_abi_arch; | |
11220 | } | |
11221 | ||
b4a3a7b4 L |
11222 | #endif |
11223 | ||
9c33702b JB |
11224 | static unsigned int |
11225 | encoding_length (const fragS *start_frag, offsetT start_off, | |
11226 | const char *frag_now_ptr) | |
11227 | { | |
11228 | unsigned int len = 0; | |
11229 | ||
11230 | if (start_frag != frag_now) | |
11231 | { | |
11232 | const fragS *fr = start_frag; | |
11233 | ||
11234 | do { | |
11235 | len += fr->fr_fix; | |
11236 | fr = fr->fr_next; | |
11237 | } while (fr && fr != frag_now); | |
11238 | } | |
11239 | ||
11240 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
11241 | } | |
11242 | ||
e379e5f3 | 11243 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
11244 | be macro-fused with conditional jumps. |
11245 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
11246 | or is one of the following format: | |
11247 | ||
11248 | cmp m, imm | |
11249 | add m, imm | |
11250 | sub m, imm | |
11251 | test m, imm | |
11252 | and m, imm | |
11253 | inc m | |
11254 | dec m | |
11255 | ||
11256 | it is unfusible. */ | |
e379e5f3 L |
11257 | |
11258 | static int | |
79d72f45 | 11259 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
11260 | { |
11261 | /* No RIP address. */ | |
11262 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
11263 | return 0; | |
11264 | ||
389d00a5 | 11265 | /* No opcodes outside of base encoding space. */ |
ddb62495 | 11266 | if (i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
11267 | return 0; |
11268 | ||
79d72f45 HL |
11269 | /* add, sub without add/sub m, imm. */ |
11270 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
11271 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
11272 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 11273 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 11274 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
11275 | { |
11276 | *mf_cmp_p = mf_cmp_alu_cmp; | |
11277 | return !(i.mem_operands && i.imm_operands); | |
11278 | } | |
e379e5f3 | 11279 | |
79d72f45 HL |
11280 | /* and without and m, imm. */ |
11281 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
11282 | || ((i.tm.base_opcode | 3) == 0x83 | |
11283 | && i.tm.extension_opcode == 0x4)) | |
11284 | { | |
11285 | *mf_cmp_p = mf_cmp_test_and; | |
11286 | return !(i.mem_operands && i.imm_operands); | |
11287 | } | |
11288 | ||
11289 | /* test without test m imm. */ | |
e379e5f3 L |
11290 | if ((i.tm.base_opcode | 1) == 0x85 |
11291 | || (i.tm.base_opcode | 1) == 0xa9 | |
11292 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
11293 | && i.tm.extension_opcode == 0)) |
11294 | { | |
11295 | *mf_cmp_p = mf_cmp_test_and; | |
11296 | return !(i.mem_operands && i.imm_operands); | |
11297 | } | |
11298 | ||
11299 | /* cmp without cmp m, imm. */ | |
11300 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
11301 | || ((i.tm.base_opcode | 3) == 0x83 |
11302 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
11303 | { |
11304 | *mf_cmp_p = mf_cmp_alu_cmp; | |
11305 | return !(i.mem_operands && i.imm_operands); | |
11306 | } | |
e379e5f3 | 11307 | |
79d72f45 | 11308 | /* inc, dec without inc/dec m. */ |
734dfd1c | 11309 | if ((is_cpu (&i.tm, CpuNo64) |
e379e5f3 L |
11310 | && (i.tm.base_opcode | 0xf) == 0x4f) |
11311 | || ((i.tm.base_opcode | 1) == 0xff | |
11312 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
11313 | { |
11314 | *mf_cmp_p = mf_cmp_incdec; | |
11315 | return !i.mem_operands; | |
11316 | } | |
e379e5f3 L |
11317 | |
11318 | return 0; | |
11319 | } | |
11320 | ||
11321 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
11322 | ||
11323 | static int | |
b5482fe5 JB |
11324 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind *mf_cmp_p, |
11325 | const struct last_insn *last_insn) | |
e379e5f3 L |
11326 | { |
11327 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
11328 | if (!align_branch_power | |
11329 | || now_seg == absolute_section | |
11330 | || !cpu_arch_flags.bitfield.cpui386 | |
11331 | || !(align_branch & align_branch_fused_bit)) | |
11332 | return 0; | |
11333 | ||
79d72f45 | 11334 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 | 11335 | { |
b5482fe5 | 11336 | if (last_insn->kind == last_insn_other) |
e379e5f3 L |
11337 | return 1; |
11338 | if (flag_debug) | |
b5482fe5 | 11339 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 11340 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 11341 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
11342 | } |
11343 | ||
11344 | return 0; | |
11345 | } | |
11346 | ||
11347 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
11348 | ||
11349 | static int | |
b5482fe5 | 11350 | add_branch_prefix_frag_p (const struct last_insn *last_insn) |
e379e5f3 L |
11351 | { |
11352 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
11353 | to PadLock instructions since they include prefixes in opcode. */ | |
11354 | if (!align_branch_power | |
11355 | || !align_branch_prefix_size | |
11356 | || now_seg == absolute_section | |
734dfd1c | 11357 | || is_cpu (&i.tm, CpuPadLock) |
e379e5f3 L |
11358 | || !cpu_arch_flags.bitfield.cpui386) |
11359 | return 0; | |
11360 | ||
11361 | /* Don't add prefix if it is a prefix or there is no operand in case | |
11362 | that segment prefix is special. */ | |
11363 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
11364 | return 0; | |
11365 | ||
b5482fe5 | 11366 | if (last_insn->kind == last_insn_other) |
e379e5f3 L |
11367 | return 1; |
11368 | ||
11369 | if (flag_debug) | |
b5482fe5 | 11370 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 11371 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 11372 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
11373 | |
11374 | return 0; | |
11375 | } | |
11376 | ||
11377 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
11378 | ||
11379 | static int | |
79d72f45 | 11380 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
b5482fe5 JB |
11381 | enum mf_jcc_kind *mf_jcc_p, |
11382 | const struct last_insn *last_insn) | |
e379e5f3 L |
11383 | { |
11384 | int add_padding; | |
11385 | ||
11386 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
11387 | if (!align_branch_power | |
11388 | || now_seg == absolute_section | |
389d00a5 | 11389 | || !cpu_arch_flags.bitfield.cpui386 |
ddb62495 | 11390 | || i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
11391 | return 0; |
11392 | ||
11393 | add_padding = 0; | |
11394 | ||
11395 | /* Check for jcc and direct jmp. */ | |
11396 | if (i.tm.opcode_modifier.jump == JUMP) | |
11397 | { | |
11398 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
11399 | { | |
11400 | *branch_p = align_branch_jmp; | |
11401 | add_padding = align_branch & align_branch_jmp_bit; | |
11402 | } | |
11403 | else | |
11404 | { | |
79d72f45 HL |
11405 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
11406 | igore the lowest bit. */ | |
11407 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
11408 | *branch_p = align_branch_jcc; |
11409 | if ((align_branch & align_branch_jcc_bit)) | |
11410 | add_padding = 1; | |
11411 | } | |
11412 | } | |
e379e5f3 L |
11413 | else if ((i.tm.base_opcode | 1) == 0xc3) |
11414 | { | |
11415 | /* Near ret. */ | |
11416 | *branch_p = align_branch_ret; | |
11417 | if ((align_branch & align_branch_ret_bit)) | |
11418 | add_padding = 1; | |
11419 | } | |
11420 | else | |
11421 | { | |
11422 | /* Check for indirect jmp, direct and indirect calls. */ | |
11423 | if (i.tm.base_opcode == 0xe8) | |
11424 | { | |
11425 | /* Direct call. */ | |
11426 | *branch_p = align_branch_call; | |
11427 | if ((align_branch & align_branch_call_bit)) | |
11428 | add_padding = 1; | |
11429 | } | |
11430 | else if (i.tm.base_opcode == 0xff | |
11431 | && (i.tm.extension_opcode == 2 | |
11432 | || i.tm.extension_opcode == 4)) | |
11433 | { | |
11434 | /* Indirect call and jmp. */ | |
11435 | *branch_p = align_branch_indirect; | |
11436 | if ((align_branch & align_branch_indirect_bit)) | |
11437 | add_padding = 1; | |
11438 | } | |
11439 | ||
11440 | if (add_padding | |
11441 | && i.disp_operands | |
11442 | && tls_get_addr | |
11443 | && (i.op[0].disps->X_op == O_symbol | |
11444 | || (i.op[0].disps->X_op == O_subtract | |
11445 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
11446 | { | |
11447 | symbolS *s = i.op[0].disps->X_add_symbol; | |
11448 | /* No padding to call to global or undefined tls_get_addr. */ | |
11449 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
11450 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
11451 | return 0; | |
11452 | } | |
11453 | } | |
11454 | ||
11455 | if (add_padding | |
b5482fe5 | 11456 | && last_insn->kind != last_insn_other) |
e379e5f3 L |
11457 | { |
11458 | if (flag_debug) | |
b5482fe5 | 11459 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 11460 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 11461 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
11462 | return 0; |
11463 | } | |
11464 | ||
11465 | return add_padding; | |
11466 | } | |
11467 | ||
29b0f896 | 11468 | static void |
b5482fe5 | 11469 | output_insn (const struct last_insn *last_insn) |
29b0f896 | 11470 | { |
2bbd9c25 JJ |
11471 | fragS *insn_start_frag; |
11472 | offsetT insn_start_off; | |
e379e5f3 L |
11473 | fragS *fragP = NULL; |
11474 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
11475 | /* The initializer is arbitrary just to avoid uninitialized error. |
11476 | it's actually either assigned in add_branch_padding_frag_p | |
11477 | or never be used. */ | |
11478 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 11479 | |
b4a3a7b4 | 11480 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 11481 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 | 11482 | { |
32930e4e | 11483 | if ((i.xstate & xstate_tmm) == xstate_tmm |
734dfd1c | 11484 | || is_cpu (&i.tm, CpuAMX_TILE)) |
32930e4e L |
11485 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; |
11486 | ||
734dfd1c JB |
11487 | if (is_cpu (&i.tm, Cpu8087) |
11488 | || is_cpu (&i.tm, Cpu287) | |
11489 | || is_cpu (&i.tm, Cpu387) | |
11490 | || is_cpu (&i.tm, Cpu687) | |
11491 | || is_cpu (&i.tm, CpuFISTTP)) | |
b4a3a7b4 | 11492 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; |
014d61ea | 11493 | |
921eafea | 11494 | if ((i.xstate & xstate_mmx) |
7fc69528 JB |
11495 | || i.tm.mnem_off == MN_emms |
11496 | || i.tm.mnem_off == MN_femms) | |
b4a3a7b4 | 11497 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
014d61ea | 11498 | |
32930e4e L |
11499 | if (i.index_reg) |
11500 | { | |
11501 | if (i.index_reg->reg_type.bitfield.zmmword) | |
11502 | i.xstate |= xstate_zmm; | |
11503 | else if (i.index_reg->reg_type.bitfield.ymmword) | |
11504 | i.xstate |= xstate_ymm; | |
11505 | else if (i.index_reg->reg_type.bitfield.xmmword) | |
11506 | i.xstate |= xstate_xmm; | |
11507 | } | |
014d61ea JB |
11508 | |
11509 | /* vzeroall / vzeroupper */ | |
734dfd1c | 11510 | if (i.tm.base_opcode == 0x77 && is_cpu (&i.tm, CpuAVX)) |
014d61ea JB |
11511 | i.xstate |= xstate_ymm; |
11512 | ||
c4694f17 | 11513 | if ((i.xstate & xstate_xmm) |
389d00a5 JB |
11514 | /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */ |
11515 | || (i.tm.base_opcode == 0xae | |
734dfd1c JB |
11516 | && (is_cpu (&i.tm, CpuSSE) |
11517 | || is_cpu (&i.tm, CpuAVX))) | |
11518 | || is_cpu (&i.tm, CpuWideKL) | |
11519 | || is_cpu (&i.tm, CpuKL)) | |
b4a3a7b4 | 11520 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
014d61ea | 11521 | |
921eafea | 11522 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 11523 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 11524 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 | 11525 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
6225c532 | 11526 | if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask) |
32930e4e | 11527 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK; |
734dfd1c | 11528 | if (is_cpu (&i.tm, CpuFXSR)) |
b4a3a7b4 | 11529 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; |
734dfd1c | 11530 | if (is_cpu (&i.tm, CpuXsave)) |
b4a3a7b4 | 11531 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; |
734dfd1c | 11532 | if (is_cpu (&i.tm, CpuXsaveopt)) |
b4a3a7b4 | 11533 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; |
734dfd1c | 11534 | if (is_cpu (&i.tm, CpuXSAVEC)) |
b4a3a7b4 | 11535 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; |
b0ab0693 L |
11536 | |
11537 | if (x86_feature_2_used | |
734dfd1c JB |
11538 | || is_cpu (&i.tm, CpuCMOV) |
11539 | || is_cpu (&i.tm, CpuSYSCALL) | |
7fc69528 | 11540 | || i.tm.mnem_off == MN_cmpxchg8b) |
b0ab0693 | 11541 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; |
734dfd1c JB |
11542 | if (is_cpu (&i.tm, CpuSSE3) |
11543 | || is_cpu (&i.tm, CpuSSSE3) | |
11544 | || is_cpu (&i.tm, CpuSSE4_1) | |
11545 | || is_cpu (&i.tm, CpuSSE4_2) | |
11546 | || is_cpu (&i.tm, CpuCX16) | |
11547 | || is_cpu (&i.tm, CpuPOPCNT) | |
b0ab0693 L |
11548 | /* LAHF-SAHF insns in 64-bit mode. */ |
11549 | || (flag_code == CODE_64BIT | |
35648716 | 11550 | && (i.tm.base_opcode | 1) == 0x9f |
ddb62495 | 11551 | && i.tm.opcode_space == SPACE_BASE)) |
b0ab0693 | 11552 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2; |
734dfd1c JB |
11553 | if (is_cpu (&i.tm, CpuAVX) |
11554 | || is_cpu (&i.tm, CpuAVX2) | |
a9860005 JB |
11555 | /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ, |
11556 | XOP, FMA4, LPW, TBM, and AMX. */ | |
b0ab0693 | 11557 | || (i.tm.opcode_modifier.vex |
734dfd1c JB |
11558 | && !is_cpu (&i.tm, CpuAVX512F) |
11559 | && !is_cpu (&i.tm, CpuAVX512BW) | |
11560 | && !is_cpu (&i.tm, CpuAVX512DQ) | |
11561 | && !is_cpu (&i.tm, CpuXOP) | |
11562 | && !is_cpu (&i.tm, CpuFMA4) | |
11563 | && !is_cpu (&i.tm, CpuLWP) | |
11564 | && !is_cpu (&i.tm, CpuTBM) | |
b0ab0693 | 11565 | && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM)) |
734dfd1c JB |
11566 | || is_cpu (&i.tm, CpuF16C) |
11567 | || is_cpu (&i.tm, CpuFMA) | |
11568 | || is_cpu (&i.tm, CpuLZCNT) | |
11569 | || is_cpu (&i.tm, CpuMovbe) | |
11570 | || is_cpu (&i.tm, CpuXSAVES) | |
b0ab0693 L |
11571 | || (x86_feature_2_used |
11572 | & (GNU_PROPERTY_X86_FEATURE_2_XSAVE | |
11573 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT | |
11574 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0) | |
11575 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3; | |
734dfd1c JB |
11576 | if (is_cpu (&i.tm, CpuAVX512F) |
11577 | || is_cpu (&i.tm, CpuAVX512BW) | |
11578 | || is_cpu (&i.tm, CpuAVX512DQ) | |
11579 | || is_cpu (&i.tm, CpuAVX512VL) | |
a9860005 JB |
11580 | /* Any EVEX encoded insns except for AVX512ER, AVX512PF, |
11581 | AVX512-4FMAPS, and AVX512-4VNNIW. */ | |
b0ab0693 | 11582 | || (i.tm.opcode_modifier.evex |
734dfd1c JB |
11583 | && !is_cpu (&i.tm, CpuAVX512ER) |
11584 | && !is_cpu (&i.tm, CpuAVX512PF) | |
11585 | && !is_cpu (&i.tm, CpuAVX512_4FMAPS) | |
11586 | && !is_cpu (&i.tm, CpuAVX512_4VNNIW))) | |
b0ab0693 | 11587 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4; |
b4a3a7b4 L |
11588 | } |
11589 | #endif | |
11590 | ||
29b0f896 AM |
11591 | /* Tie dwarf2 debug info to the address at the start of the insn. |
11592 | We can't do this after the insn has been output as the current | |
11593 | frag may have been closed off. eg. by frag_var. */ | |
11594 | dwarf2_emit_insn (0); | |
11595 | ||
2bbd9c25 JJ |
11596 | insn_start_frag = frag_now; |
11597 | insn_start_off = frag_now_fix (); | |
11598 | ||
b5482fe5 | 11599 | if (add_branch_padding_frag_p (&branch, &mf_jcc, last_insn)) |
e379e5f3 L |
11600 | { |
11601 | char *p; | |
11602 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
11603 | unsigned int max_branch_padding_size = 14; | |
11604 | ||
11605 | /* Align section to boundary. */ | |
11606 | record_alignment (now_seg, align_branch_power); | |
11607 | ||
11608 | /* Make room for padding. */ | |
11609 | frag_grow (max_branch_padding_size); | |
11610 | ||
11611 | /* Start of the padding. */ | |
11612 | p = frag_more (0); | |
11613 | ||
11614 | fragP = frag_now; | |
11615 | ||
11616 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
11617 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
11618 | NULL, 0, p); | |
11619 | ||
79d72f45 | 11620 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
11621 | fragP->tc_frag_data.branch_type = branch; |
11622 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
11623 | } | |
11624 | ||
d59a54c2 JB |
11625 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT) |
11626 | && !pre_386_16bit_warned) | |
11627 | { | |
11628 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
11629 | pre_386_16bit_warned = true; | |
11630 | } | |
11631 | ||
29b0f896 | 11632 | /* Output jumps. */ |
0cfa3eb3 | 11633 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 11634 | output_branch (); |
0cfa3eb3 JB |
11635 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
11636 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 11637 | output_jump (); |
0cfa3eb3 | 11638 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
11639 | output_interseg_jump (); |
11640 | else | |
11641 | { | |
11642 | /* Output normal instructions here. */ | |
11643 | char *p; | |
11644 | unsigned char *q; | |
47465058 | 11645 | unsigned int j; |
79d72f45 | 11646 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 11647 | |
e4e00185 | 11648 | if (avoid_fence |
389d00a5 JB |
11649 | && (i.tm.base_opcode == 0xaee8 |
11650 | || i.tm.base_opcode == 0xaef0 | |
11651 | || i.tm.base_opcode == 0xaef8)) | |
48ef937e JB |
11652 | { |
11653 | /* Encode lfence, mfence, and sfence as | |
11654 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
47f4115a | 11655 | if (flag_code == CODE_16BIT) |
76d3f746 | 11656 | as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i.tm)); |
47f4115a JB |
11657 | else if (omit_lock_prefix) |
11658 | as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"), | |
76d3f746 | 11659 | insn_name (&i.tm)); |
47f4115a | 11660 | else if (now_seg != absolute_section) |
48ef937e JB |
11661 | { |
11662 | offsetT val = 0x240483f0ULL; | |
11663 | ||
11664 | p = frag_more (5); | |
11665 | md_number_to_chars (p, val, 5); | |
11666 | } | |
11667 | else | |
11668 | abs_section_offset += 5; | |
11669 | return; | |
11670 | } | |
e4e00185 | 11671 | |
d022bddd IT |
11672 | /* Some processors fail on LOCK prefix. This options makes |
11673 | assembler ignore LOCK prefix and serves as a workaround. */ | |
11674 | if (omit_lock_prefix) | |
11675 | { | |
35648716 JB |
11676 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE |
11677 | && i.tm.opcode_modifier.isprefix) | |
d022bddd IT |
11678 | return; |
11679 | i.prefix[LOCK_PREFIX] = 0; | |
11680 | } | |
11681 | ||
e379e5f3 L |
11682 | if (branch) |
11683 | /* Skip if this is a branch. */ | |
11684 | ; | |
b5482fe5 | 11685 | else if (add_fused_jcc_padding_frag_p (&mf_cmp, last_insn)) |
e379e5f3 L |
11686 | { |
11687 | /* Make room for padding. */ | |
11688 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
11689 | p = frag_more (0); | |
11690 | ||
11691 | fragP = frag_now; | |
11692 | ||
11693 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
11694 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
11695 | NULL, 0, p); | |
11696 | ||
79d72f45 | 11697 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
11698 | fragP->tc_frag_data.branch_type = align_branch_fused; |
11699 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
11700 | } | |
b5482fe5 | 11701 | else if (add_branch_prefix_frag_p (last_insn)) |
e379e5f3 L |
11702 | { |
11703 | unsigned int max_prefix_size = align_branch_prefix_size; | |
11704 | ||
11705 | /* Make room for padding. */ | |
11706 | frag_grow (max_prefix_size); | |
11707 | p = frag_more (0); | |
11708 | ||
11709 | fragP = frag_now; | |
11710 | ||
11711 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
11712 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
11713 | NULL, 0, p); | |
11714 | ||
11715 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
11716 | } | |
11717 | ||
43234a1e L |
11718 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
11719 | don't need the explicit prefix. */ | |
cf665fee | 11720 | if (!is_any_vex_encoding (&i.tm)) |
bc4bd9ab | 11721 | { |
7b47a312 | 11722 | switch (i.tm.opcode_modifier.opcodeprefix) |
bc4bd9ab | 11723 | { |
7b47a312 L |
11724 | case PREFIX_0X66: |
11725 | add_prefix (0x66); | |
11726 | break; | |
11727 | case PREFIX_0XF2: | |
11728 | add_prefix (0xf2); | |
11729 | break; | |
11730 | case PREFIX_0XF3: | |
734dfd1c | 11731 | if (!is_cpu (&i.tm, CpuPadLock) |
8b65b895 L |
11732 | || (i.prefix[REP_PREFIX] != 0xf3)) |
11733 | add_prefix (0xf3); | |
c0f3af97 | 11734 | break; |
7b47a312 | 11735 | case PREFIX_NONE: |
9a182d04 | 11736 | switch (i.opcode_length) |
c0f3af97 | 11737 | { |
7b47a312 | 11738 | case 2: |
7b47a312 | 11739 | break; |
9a182d04 | 11740 | case 1: |
7b47a312 | 11741 | /* Check for pseudo prefixes. */ |
9a182d04 JB |
11742 | if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode) |
11743 | break; | |
7b47a312 L |
11744 | as_bad_where (insn_start_frag->fr_file, |
11745 | insn_start_frag->fr_line, | |
11746 | _("pseudo prefix without instruction")); | |
11747 | return; | |
11748 | default: | |
11749 | abort (); | |
4dffcebc | 11750 | } |
c0f3af97 | 11751 | break; |
c0f3af97 L |
11752 | default: |
11753 | abort (); | |
bc4bd9ab | 11754 | } |
c0f3af97 | 11755 | |
6d19a37a | 11756 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
11757 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
11758 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
11759 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
11760 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
11761 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 | 11762 | if (x86_elf_abi == X86_64_X32_ABI |
a533c8df | 11763 | && !is_apx_rex2_encoding () |
cf61b747 | 11764 | && i.operands == 2 |
14470f07 L |
11765 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
11766 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
11767 | && i.prefix[REX_PREFIX] == 0) |
11768 | add_prefix (REX_OPCODE); | |
6d19a37a | 11769 | #endif |
cf61b747 | 11770 | |
c0f3af97 L |
11771 | /* The prefix bytes. */ |
11772 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
11773 | if (*q) | |
48ef937e | 11774 | frag_opcode_byte (*q); |
80d61d8d CL |
11775 | |
11776 | if (is_apx_rex2_encoding ()) | |
11777 | { | |
11778 | frag_opcode_byte (i.vex.bytes[0]); | |
11779 | frag_opcode_byte (i.vex.bytes[1]); | |
11780 | } | |
0f10071e | 11781 | } |
ae5c1c7b | 11782 | else |
c0f3af97 L |
11783 | { |
11784 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
11785 | if (*q) | |
11786 | switch (j) | |
11787 | { | |
c0f3af97 L |
11788 | case SEG_PREFIX: |
11789 | case ADDR_PREFIX: | |
48ef937e | 11790 | frag_opcode_byte (*q); |
c0f3af97 L |
11791 | break; |
11792 | default: | |
11793 | /* There should be no other prefixes for instructions | |
11794 | with VEX prefix. */ | |
11795 | abort (); | |
11796 | } | |
11797 | ||
43234a1e L |
11798 | /* For EVEX instructions i.vrex should become 0 after |
11799 | build_evex_prefix. For VEX instructions upper 16 registers | |
11800 | aren't available, so VREX should be 0. */ | |
11801 | if (i.vrex) | |
11802 | abort (); | |
c0f3af97 | 11803 | /* Now the VEX prefix. */ |
48ef937e JB |
11804 | if (now_seg != absolute_section) |
11805 | { | |
11806 | p = frag_more (i.vex.length); | |
11807 | for (j = 0; j < i.vex.length; j++) | |
11808 | p[j] = i.vex.bytes[j]; | |
11809 | } | |
11810 | else | |
11811 | abs_section_offset += i.vex.length; | |
c0f3af97 | 11812 | } |
252b5132 | 11813 | |
29b0f896 | 11814 | /* Now the opcode; be careful about word order here! */ |
389d00a5 JB |
11815 | j = i.opcode_length; |
11816 | if (!i.vex.length) | |
ddb62495 | 11817 | switch (i.tm.opcode_space) |
389d00a5 JB |
11818 | { |
11819 | case SPACE_BASE: | |
11820 | break; | |
11821 | case SPACE_0F: | |
11822 | ++j; | |
11823 | break; | |
11824 | case SPACE_0F38: | |
11825 | case SPACE_0F3A: | |
11826 | j += 2; | |
11827 | break; | |
11828 | default: | |
11829 | abort (); | |
11830 | } | |
11831 | ||
48ef937e | 11832 | if (now_seg == absolute_section) |
389d00a5 JB |
11833 | abs_section_offset += j; |
11834 | else if (j == 1) | |
29b0f896 AM |
11835 | { |
11836 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
11837 | } | |
11838 | else | |
11839 | { | |
389d00a5 JB |
11840 | p = frag_more (j); |
11841 | if (!i.vex.length | |
ddb62495 | 11842 | && i.tm.opcode_space != SPACE_BASE) |
389d00a5 JB |
11843 | { |
11844 | *p++ = 0x0f; | |
ddb62495 JB |
11845 | if (i.tm.opcode_space != SPACE_0F) |
11846 | *p++ = i.tm.opcode_space == SPACE_0F38 | |
389d00a5 JB |
11847 | ? 0x38 : 0x3a; |
11848 | } | |
11849 | ||
9a182d04 | 11850 | switch (i.opcode_length) |
331d2d0d | 11851 | { |
4dffcebc | 11852 | case 2: |
389d00a5 JB |
11853 | /* Put out high byte first: can't use md_number_to_chars! */ |
11854 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
11855 | /* Fall through. */ | |
11856 | case 1: | |
11857 | *p = i.tm.base_opcode & 0xff; | |
4dffcebc L |
11858 | break; |
11859 | default: | |
11860 | abort (); | |
11861 | break; | |
331d2d0d | 11862 | } |
0f10071e | 11863 | |
29b0f896 | 11864 | } |
3e73aa7c | 11865 | |
29b0f896 | 11866 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 11867 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 11868 | { |
48ef937e JB |
11869 | frag_opcode_byte ((i.rm.regmem << 0) |
11870 | | (i.rm.reg << 3) | |
11871 | | (i.rm.mode << 6)); | |
29b0f896 AM |
11872 | /* If i.rm.regmem == ESP (4) |
11873 | && i.rm.mode != (Register mode) | |
11874 | && not 16 bit | |
11875 | ==> need second modrm byte. */ | |
11876 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
11877 | && i.rm.mode != 3 | |
dc821c5f | 11878 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
11879 | frag_opcode_byte ((i.sib.base << 0) |
11880 | | (i.sib.index << 3) | |
11881 | | (i.sib.scale << 6)); | |
29b0f896 | 11882 | } |
3e73aa7c | 11883 | |
29b0f896 | 11884 | if (i.disp_operands) |
2bbd9c25 | 11885 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 11886 | |
29b0f896 | 11887 | if (i.imm_operands) |
2bbd9c25 | 11888 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
11889 | |
11890 | /* | |
11891 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
11892 | * absolute section, and abs_section_offset not getting updated as data | |
11893 | * gets added to the frag breaks the logic below. | |
11894 | */ | |
11895 | if (now_seg != absolute_section) | |
11896 | { | |
11897 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
11898 | if (j > 15) | |
0afc614c L |
11899 | { |
11900 | if (dot_insn ()) | |
11901 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
11902 | j); | |
11903 | else | |
11904 | as_bad (_("instruction length of %u bytes exceeds the limit of 15"), | |
11905 | j); | |
11906 | } | |
e379e5f3 L |
11907 | else if (fragP) |
11908 | { | |
11909 | /* NB: Don't add prefix with GOTPC relocation since | |
11910 | output_disp() above depends on the fixed encoding | |
11911 | length. Can't add prefix with TLS relocation since | |
11912 | it breaks TLS linker optimization. */ | |
11913 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
11914 | /* Prefix count on the current instruction. */ | |
11915 | unsigned int count = i.vex.length; | |
11916 | unsigned int k; | |
11917 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
11918 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
11919 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
11920 | count++; | |
11921 | ||
11922 | /* Count prefixes for extended opcode maps. */ | |
11923 | if (!i.vex.length) | |
ddb62495 | 11924 | switch (i.tm.opcode_space) |
e379e5f3 | 11925 | { |
389d00a5 | 11926 | case SPACE_BASE: |
e379e5f3 | 11927 | break; |
389d00a5 JB |
11928 | case SPACE_0F: |
11929 | count++; | |
e379e5f3 | 11930 | break; |
389d00a5 JB |
11931 | case SPACE_0F38: |
11932 | case SPACE_0F3A: | |
11933 | count += 2; | |
e379e5f3 L |
11934 | break; |
11935 | default: | |
11936 | abort (); | |
11937 | } | |
11938 | ||
11939 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11940 | == BRANCH_PREFIX) | |
11941 | { | |
11942 | /* Set the maximum prefix size in BRANCH_PREFIX | |
11943 | frag. */ | |
11944 | if (fragP->tc_frag_data.max_bytes > max) | |
11945 | fragP->tc_frag_data.max_bytes = max; | |
11946 | if (fragP->tc_frag_data.max_bytes > count) | |
11947 | fragP->tc_frag_data.max_bytes -= count; | |
11948 | else | |
11949 | fragP->tc_frag_data.max_bytes = 0; | |
11950 | } | |
11951 | else | |
11952 | { | |
11953 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
11954 | frag. */ | |
11955 | unsigned int max_prefix_size; | |
11956 | if (align_branch_prefix_size > max) | |
11957 | max_prefix_size = max; | |
11958 | else | |
11959 | max_prefix_size = align_branch_prefix_size; | |
11960 | if (max_prefix_size > count) | |
11961 | fragP->tc_frag_data.max_prefix_length | |
11962 | = max_prefix_size - count; | |
11963 | } | |
11964 | ||
11965 | /* Use existing segment prefix if possible. Use CS | |
11966 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
11967 | segment prefix with ESP/EBP base register and use DS | |
11968 | segment prefix without ESP/EBP base register. */ | |
11969 | if (i.prefix[SEG_PREFIX]) | |
11970 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
11971 | else if (flag_code == CODE_64BIT) | |
11972 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
11973 | else if (i.base_reg | |
11974 | && (i.base_reg->reg_num == 4 | |
11975 | || i.base_reg->reg_num == 5)) | |
11976 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
11977 | else | |
11978 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
11979 | } | |
9c33702b | 11980 | } |
29b0f896 | 11981 | } |
252b5132 | 11982 | |
e379e5f3 L |
11983 | /* NB: Don't work with COND_JUMP86 without i386. */ |
11984 | if (align_branch_power | |
11985 | && now_seg != absolute_section | |
11986 | && cpu_arch_flags.bitfield.cpui386) | |
11987 | { | |
11988 | /* Terminate each frag so that we can add prefix and check for | |
11989 | fused jcc. */ | |
11990 | frag_wane (frag_now); | |
11991 | frag_new (0); | |
11992 | } | |
11993 | ||
29b0f896 AM |
11994 | #ifdef DEBUG386 |
11995 | if (flag_debug) | |
11996 | { | |
7b81dfbb | 11997 | pi ("" /*line*/, &i); |
29b0f896 AM |
11998 | } |
11999 | #endif /* DEBUG386 */ | |
12000 | } | |
252b5132 | 12001 | |
e205caa7 L |
12002 | /* Return the size of the displacement operand N. */ |
12003 | ||
12004 | static int | |
12005 | disp_size (unsigned int n) | |
12006 | { | |
12007 | int size = 4; | |
43234a1e | 12008 | |
b5014f7a | 12009 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
12010 | size = 8; |
12011 | else if (i.types[n].bitfield.disp8) | |
12012 | size = 1; | |
12013 | else if (i.types[n].bitfield.disp16) | |
12014 | size = 2; | |
e205caa7 L |
12015 | return size; |
12016 | } | |
12017 | ||
12018 | /* Return the size of the immediate operand N. */ | |
12019 | ||
12020 | static int | |
12021 | imm_size (unsigned int n) | |
12022 | { | |
12023 | int size = 4; | |
40fb9820 L |
12024 | if (i.types[n].bitfield.imm64) |
12025 | size = 8; | |
12026 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
12027 | size = 1; | |
12028 | else if (i.types[n].bitfield.imm16) | |
12029 | size = 2; | |
e205caa7 L |
12030 | return size; |
12031 | } | |
12032 | ||
29b0f896 | 12033 | static void |
64e74474 | 12034 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
12035 | { |
12036 | char *p; | |
12037 | unsigned int n; | |
252b5132 | 12038 | |
29b0f896 AM |
12039 | for (n = 0; n < i.operands; n++) |
12040 | { | |
b5014f7a | 12041 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 12042 | { |
48ef937e JB |
12043 | int size = disp_size (n); |
12044 | ||
12045 | if (now_seg == absolute_section) | |
12046 | abs_section_offset += size; | |
12047 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 12048 | { |
43234a1e | 12049 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 12050 | |
629cfaf1 JB |
12051 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
12052 | size); | |
29b0f896 AM |
12053 | p = frag_more (size); |
12054 | md_number_to_chars (p, val, size); | |
12055 | } | |
12056 | else | |
12057 | { | |
f86103b7 | 12058 | enum bfd_reloc_code_real reloc_type; |
a775efc8 JB |
12059 | bool pcrel = (i.flags[n] & Operand_PCrel) != 0; |
12060 | bool sign = (flag_code == CODE_64BIT && size == 4 | |
12061 | && (!want_disp32 (&i.tm) | |
12062 | || (i.tm.opcode_modifier.jump && !i.jumpabsolute | |
12063 | && !i.types[n].bitfield.baseindex))) | |
12064 | || pcrel; | |
02a86693 | 12065 | fixS *fixP; |
29b0f896 | 12066 | |
e205caa7 | 12067 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 12068 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 12069 | |
29b0f896 AM |
12070 | /* The PC relative address is computed relative |
12071 | to the instruction boundary, so in case immediate | |
12072 | fields follows, we need to adjust the value. */ | |
12073 | if (pcrel && i.imm_operands) | |
12074 | { | |
29b0f896 | 12075 | unsigned int n1; |
e205caa7 | 12076 | int sz = 0; |
252b5132 | 12077 | |
29b0f896 | 12078 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 12079 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 12080 | { |
e205caa7 | 12081 | /* Only one immediate is allowed for PC |
e3bf0aad JB |
12082 | relative address, except with .insn. */ |
12083 | gas_assert (sz == 0 || dot_insn ()); | |
12084 | sz += imm_size (n1); | |
252b5132 | 12085 | } |
e3bf0aad | 12086 | /* We should find at least one immediate. */ |
9c2799c2 | 12087 | gas_assert (sz != 0); |
e3bf0aad | 12088 | i.op[n].disps->X_add_number -= sz; |
29b0f896 | 12089 | } |
520dc8e8 | 12090 | |
29b0f896 | 12091 | p = frag_more (size); |
d258b828 | 12092 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 12093 | if (GOT_symbol |
2bbd9c25 | 12094 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 12095 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
12096 | || reloc_type == BFD_RELOC_X86_64_32S |
12097 | || (reloc_type == BFD_RELOC_64 | |
12098 | && object_64bit)) | |
d6ab8113 JB |
12099 | && (i.op[n].disps->X_op == O_symbol |
12100 | || (i.op[n].disps->X_op == O_add | |
12101 | && ((symbol_get_value_expression | |
12102 | (i.op[n].disps->X_op_symbol)->X_op) | |
12103 | == O_subtract)))) | |
12104 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 12105 | { |
4fa24527 | 12106 | if (!object_64bit) |
7b81dfbb AJ |
12107 | { |
12108 | reloc_type = BFD_RELOC_386_GOTPC; | |
5b7c81bd | 12109 | i.has_gotpc_tls_reloc = true; |
98da05bf | 12110 | i.op[n].disps->X_add_number += |
d583596c | 12111 | encoding_length (insn_start_frag, insn_start_off, p); |
7b81dfbb AJ |
12112 | } |
12113 | else if (reloc_type == BFD_RELOC_64) | |
12114 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 12115 | else |
7b81dfbb AJ |
12116 | /* Don't do the adjustment for x86-64, as there |
12117 | the pcrel addressing is relative to the _next_ | |
12118 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 12119 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 12120 | } |
e379e5f3 L |
12121 | else if (align_branch_power) |
12122 | { | |
12123 | switch (reloc_type) | |
12124 | { | |
12125 | case BFD_RELOC_386_TLS_GD: | |
12126 | case BFD_RELOC_386_TLS_LDM: | |
12127 | case BFD_RELOC_386_TLS_IE: | |
12128 | case BFD_RELOC_386_TLS_IE_32: | |
12129 | case BFD_RELOC_386_TLS_GOTIE: | |
12130 | case BFD_RELOC_386_TLS_GOTDESC: | |
12131 | case BFD_RELOC_386_TLS_DESC_CALL: | |
12132 | case BFD_RELOC_X86_64_TLSGD: | |
12133 | case BFD_RELOC_X86_64_TLSLD: | |
12134 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 12135 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
5bc71c2a | 12136 | case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: |
e379e5f3 | 12137 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 12138 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
e379e5f3 | 12139 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
5b7c81bd | 12140 | i.has_gotpc_tls_reloc = true; |
e379e5f3 L |
12141 | default: |
12142 | break; | |
12143 | } | |
12144 | } | |
02a86693 L |
12145 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
12146 | size, i.op[n].disps, pcrel, | |
12147 | reloc_type); | |
eb19308f JB |
12148 | |
12149 | if (flag_code == CODE_64BIT && size == 4 && pcrel | |
12150 | && !i.prefix[ADDR_PREFIX]) | |
12151 | fixP->fx_signed = 1; | |
12152 | ||
5bc71c2a L |
12153 | if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF |
12154 | && i.tm.opcode_space == SPACE_EVEXMAP4) | |
12155 | { | |
12156 | /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is | |
12157 | allowed in md_assemble. Set fx_tcbit2 for EVEX | |
12158 | prefix. */ | |
12159 | fixP->fx_tcbit2 = 1; | |
12160 | continue; | |
12161 | } | |
12162 | ||
12163 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
12164 | { | |
12165 | if (reloc_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
12166 | { | |
12167 | /* Set fx_tcbit for REX2 prefix. */ | |
12168 | if (is_apx_rex2_encoding ()) | |
12169 | fixP->fx_tcbit = 1; | |
12170 | continue; | |
12171 | } | |
12172 | } | |
12173 | /* In 64-bit, i386_validate_fix updates only (%rip) | |
12174 | relocations. */ | |
12175 | else if (object_64bit) | |
12176 | continue; | |
3d5a60de | 12177 | |
02a86693 L |
12178 | /* Check for "call/jmp *mem", "mov mem, %reg", |
12179 | "test %reg, mem" and "binop mem, %reg" where binop | |
12180 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
12181 | instructions without data prefix. Always generate |
12182 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
12183 | if (i.prefix[DATA_PREFIX] == 0 | |
0cb4071e L |
12184 | && (i.rm.mode == 2 |
12185 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
ddb62495 | 12186 | && i.tm.opcode_space == SPACE_BASE |
02a86693 L |
12187 | && ((i.operands == 1 |
12188 | && i.tm.base_opcode == 0xff | |
12189 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
12190 | || (i.operands == 2 | |
12191 | && (i.tm.base_opcode == 0x8b | |
12192 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 12193 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
12194 | { |
12195 | if (object_64bit) | |
12196 | { | |
5bc71c2a L |
12197 | if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF) |
12198 | { | |
12199 | /* Set fx_tcbit for REX2 prefix. */ | |
12200 | if (is_apx_rex2_encoding ()) | |
12201 | fixP->fx_tcbit = 1; | |
12202 | } | |
820a7755 | 12203 | else if (generate_relax_relocations) |
5bc71c2a L |
12204 | { |
12205 | /* Set fx_tcbit3 for REX2 prefix. */ | |
12206 | if (is_apx_rex2_encoding ()) | |
12207 | fixP->fx_tcbit3 = 1; | |
12208 | else if (i.rex) | |
12209 | fixP->fx_tcbit2 = 1; | |
12210 | else | |
12211 | fixP->fx_tcbit = 1; | |
12212 | } | |
02a86693 | 12213 | } |
820a7755 JB |
12214 | else if (generate_relax_relocations |
12215 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
12216 | fixP->fx_tcbit2 = 1; |
12217 | } | |
29b0f896 AM |
12218 | } |
12219 | } | |
12220 | } | |
12221 | } | |
252b5132 | 12222 | |
29b0f896 | 12223 | static void |
64e74474 | 12224 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
12225 | { |
12226 | char *p; | |
12227 | unsigned int n; | |
252b5132 | 12228 | |
29b0f896 AM |
12229 | for (n = 0; n < i.operands; n++) |
12230 | { | |
40fb9820 | 12231 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 12232 | { |
48ef937e JB |
12233 | int size = imm_size (n); |
12234 | ||
12235 | if (now_seg == absolute_section) | |
12236 | abs_section_offset += size; | |
12237 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 12238 | { |
29b0f896 | 12239 | offsetT val; |
b4cac588 | 12240 | |
29b0f896 AM |
12241 | val = offset_in_range (i.op[n].imms->X_add_number, |
12242 | size); | |
12243 | p = frag_more (size); | |
12244 | md_number_to_chars (p, val, size); | |
12245 | } | |
12246 | else | |
12247 | { | |
12248 | /* Not absolute_section. | |
12249 | Need a 32-bit fixup (don't support 8bit | |
12250 | non-absolute imms). Try to support other | |
12251 | sizes ... */ | |
f86103b7 | 12252 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 12253 | int sign; |
29b0f896 | 12254 | |
40fb9820 | 12255 | if (i.types[n].bitfield.imm32s |
a7d61044 | 12256 | && (i.suffix == QWORD_MNEM_SUFFIX |
c032bc4f | 12257 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf) |
f79d55e1 | 12258 | || (i.prefix[REX_PREFIX] & REX_W) |
c032bc4f | 12259 | || dot_insn ())) |
29b0f896 | 12260 | sign = 1; |
e205caa7 L |
12261 | else |
12262 | sign = 0; | |
520dc8e8 | 12263 | |
29b0f896 | 12264 | p = frag_more (size); |
d258b828 | 12265 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 12266 | |
2bbd9c25 JJ |
12267 | /* This is tough to explain. We end up with this one if we |
12268 | * have operands that look like | |
12269 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
12270 | * obtain the absolute address of the GOT, and it is strongly | |
12271 | * preferable from a performance point of view to avoid using | |
12272 | * a runtime relocation for this. The actual sequence of | |
12273 | * instructions often look something like: | |
12274 | * | |
12275 | * call .L66 | |
12276 | * .L66: | |
12277 | * popl %ebx | |
12278 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
12279 | * | |
12280 | * The call and pop essentially return the absolute address | |
12281 | * of the label .L66 and store it in %ebx. The linker itself | |
12282 | * will ultimately change the first operand of the addl so | |
12283 | * that %ebx points to the GOT, but to keep things simple, the | |
12284 | * .o file must have this operand set so that it generates not | |
12285 | * the absolute address of .L66, but the absolute address of | |
12286 | * itself. This allows the linker itself simply treat a GOTPC | |
12287 | * relocation as asking for a pcrel offset to the GOT to be | |
12288 | * added in, and the addend of the relocation is stored in the | |
12289 | * operand field for the instruction itself. | |
12290 | * | |
12291 | * Our job here is to fix the operand so that it would add | |
12292 | * the correct offset so that %ebx would point to itself. The | |
12293 | * thing that is tricky is that .-.L66 will point to the | |
12294 | * beginning of the instruction, so we need to further modify | |
12295 | * the operand so that it will point to itself. There are | |
12296 | * other cases where you have something like: | |
12297 | * | |
12298 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
12299 | * | |
12300 | * and here no correction would be required. Internally in | |
12301 | * the assembler we treat operands of this form as not being | |
12302 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
12303 | * whether it would simplify matters to do it this way. Who | |
12304 | * knows. In earlier versions of the PIC patches, the | |
12305 | * pcrel_adjust field was used to store the correction, but | |
12306 | * since the expression is not pcrel, I felt it would be | |
12307 | * confusing to do it this way. */ | |
12308 | ||
d6ab8113 | 12309 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
12310 | || reloc_type == BFD_RELOC_X86_64_32S |
12311 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
12312 | && GOT_symbol |
12313 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
12314 | && (i.op[n].imms->X_op == O_symbol | |
12315 | || (i.op[n].imms->X_op == O_add | |
12316 | && ((symbol_get_value_expression | |
12317 | (i.op[n].imms->X_op_symbol)->X_op) | |
12318 | == O_subtract)))) | |
12319 | { | |
4fa24527 | 12320 | if (!object_64bit) |
d6ab8113 | 12321 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 12322 | else if (size == 4) |
d6ab8113 | 12323 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
12324 | else if (size == 8) |
12325 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
5b7c81bd | 12326 | i.has_gotpc_tls_reloc = true; |
d583596c JB |
12327 | i.op[n].imms->X_add_number += |
12328 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 12329 | } |
29b0f896 AM |
12330 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
12331 | i.op[n].imms, 0, reloc_type); | |
12332 | } | |
12333 | } | |
12334 | } | |
252b5132 RH |
12335 | } |
12336 | \f | |
d182319b JB |
12337 | /* x86_cons_fix_new is called via the expression parsing code when a |
12338 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
12339 | static int cons_sign = -1; |
12340 | ||
12341 | void | |
e3bb37b5 | 12342 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 12343 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 12344 | { |
d258b828 | 12345 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
12346 | |
12347 | #ifdef TE_PE | |
12348 | if (exp->X_op == O_secrel) | |
12349 | { | |
12350 | exp->X_op = O_symbol; | |
12351 | r = BFD_RELOC_32_SECREL; | |
12352 | } | |
145667f8 MH |
12353 | else if (exp->X_op == O_secidx) |
12354 | r = BFD_RELOC_16_SECIDX; | |
d182319b JB |
12355 | #endif |
12356 | ||
12357 | fix_new_exp (frag, off, len, exp, 0, r); | |
12358 | } | |
12359 | ||
357d1bd8 L |
12360 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
12361 | purpose of the `.dc.a' internal pseudo-op. */ | |
12362 | ||
12363 | int | |
12364 | x86_address_bytes (void) | |
12365 | { | |
12366 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
12367 | return 4; | |
12368 | return stdoutput->arch_info->bits_per_address / 8; | |
12369 | } | |
12370 | ||
deea4973 JB |
12371 | #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
12372 | || defined (LEX_AT)) && !defined (TE_PE) | |
d258b828 | 12373 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 12374 | #else |
f3c180ae AM |
12375 | /* Parse operands of the form |
12376 | <symbol>@GOTOFF+<nnn> | |
12377 | and similar .plt or .got references. | |
12378 | ||
12379 | If we find one, set up the correct relocation in RELOC and copy the | |
12380 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
12381 | parsing by the calling routine. Return this buffer, and if ADJUST | |
12382 | is non-null set it to the length of the string we removed from the | |
12383 | input line. Otherwise return NULL. */ | |
12384 | static char * | |
91d6fa6a | 12385 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 12386 | int *adjust, |
d258b828 | 12387 | i386_operand_type *types) |
f3c180ae | 12388 | { |
7b81dfbb AJ |
12389 | /* Some of the relocations depend on the size of what field is to |
12390 | be relocated. But in our callers i386_immediate and i386_displacement | |
12391 | we don't yet know the operand size (this will be set by insn | |
12392 | matching). Hence we record the word32 relocation here, | |
12393 | and adjust the reloc according to the real size in reloc(). */ | |
145667f8 MH |
12394 | static const struct |
12395 | { | |
f3c180ae | 12396 | const char *str; |
cff8d58a | 12397 | int len; |
4fa24527 | 12398 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 12399 | const i386_operand_type types64; |
5b7c81bd | 12400 | bool need_GOT_symbol; |
145667f8 MH |
12401 | } |
12402 | gotrel[] = | |
12403 | { | |
05909f23 JB |
12404 | |
12405 | #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \ | |
12406 | { .imm32 = 1, .imm32s = 1, .disp32 = 1 } } | |
12407 | #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \ | |
12408 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } } | |
12409 | #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \ | |
12410 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } } | |
12411 | #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \ | |
12412 | { .imm64 = 1, .disp64 = 1 } } | |
12413 | ||
deea4973 | 12414 | #ifndef TE_PE |
8ce3d284 | 12415 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
12416 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
12417 | BFD_RELOC_SIZE32 }, | |
05909f23 | 12418 | { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false }, |
8ce3d284 | 12419 | #endif |
cff8d58a L |
12420 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
12421 | BFD_RELOC_X86_64_PLTOFF64 }, | |
05909f23 | 12422 | { .bitfield = { .imm64 = 1 } }, true }, |
cff8d58a L |
12423 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
12424 | BFD_RELOC_X86_64_PLT32 }, | |
a775efc8 | 12425 | OPERAND_TYPE_IMM32_32S_DISP32, false }, |
cff8d58a L |
12426 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
12427 | BFD_RELOC_X86_64_GOTPLT64 }, | |
5b7c81bd | 12428 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
12429 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
12430 | BFD_RELOC_X86_64_GOTOFF64 }, | |
5b7c81bd | 12431 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
12432 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
12433 | BFD_RELOC_X86_64_GOTPCREL }, | |
a775efc8 | 12434 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12435 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
12436 | BFD_RELOC_X86_64_TLSGD }, | |
a775efc8 | 12437 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12438 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
12439 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 12440 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
12441 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
12442 | BFD_RELOC_X86_64_TLSLD }, | |
a775efc8 | 12443 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12444 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
12445 | BFD_RELOC_X86_64_GOTTPOFF }, | |
a775efc8 | 12446 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12447 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
12448 | BFD_RELOC_X86_64_TPOFF32 }, | |
a775efc8 | 12449 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
12450 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
12451 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 12452 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
12453 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
12454 | BFD_RELOC_X86_64_DTPOFF32 }, | |
a775efc8 | 12455 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
12456 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
12457 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 12458 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
12459 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
12460 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 12461 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
12462 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
12463 | BFD_RELOC_X86_64_GOT32 }, | |
a775efc8 | 12464 | OPERAND_TYPE_IMM32_32S_64_DISP32, true }, |
cff8d58a L |
12465 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
12466 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
a775efc8 | 12467 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12468 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
12469 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
a775efc8 | 12470 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
deea4973 JB |
12471 | #else /* TE_PE */ |
12472 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
12473 | BFD_RELOC_32_SECREL }, | |
a775efc8 | 12474 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, false }, |
deea4973 | 12475 | #endif |
05909f23 JB |
12476 | |
12477 | #undef OPERAND_TYPE_IMM32_32S_DISP32 | |
12478 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32 | |
12479 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64 | |
12480 | #undef OPERAND_TYPE_IMM64_DISP64 | |
12481 | ||
f3c180ae AM |
12482 | }; |
12483 | char *cp; | |
12484 | unsigned int j; | |
12485 | ||
deea4973 | 12486 | #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE) |
718ddfc0 JB |
12487 | if (!IS_ELF) |
12488 | return NULL; | |
d382c579 | 12489 | #endif |
718ddfc0 | 12490 | |
f3c180ae | 12491 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 12492 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
12493 | return NULL; |
12494 | ||
47465058 | 12495 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 12496 | { |
cff8d58a | 12497 | int len = gotrel[j].len; |
28f81592 | 12498 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 12499 | { |
4fa24527 | 12500 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 12501 | { |
28f81592 AM |
12502 | int first, second; |
12503 | char *tmpbuf, *past_reloc; | |
f3c180ae | 12504 | |
91d6fa6a | 12505 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 12506 | |
3956db08 JB |
12507 | if (types) |
12508 | { | |
12509 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
12510 | { |
12511 | types->bitfield.imm32 = 1; | |
12512 | types->bitfield.disp32 = 1; | |
12513 | } | |
3956db08 JB |
12514 | else |
12515 | *types = gotrel[j].types64; | |
12516 | } | |
12517 | ||
844bf810 | 12518 | if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL) |
f3c180ae AM |
12519 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
12520 | ||
28f81592 | 12521 | /* The length of the first part of our input line. */ |
f3c180ae | 12522 | first = cp - input_line_pointer; |
28f81592 AM |
12523 | |
12524 | /* The second part goes from after the reloc token until | |
67c11a9b | 12525 | (and including) an end_of_line char or comma. */ |
28f81592 | 12526 | past_reloc = cp + 1 + len; |
67c11a9b AM |
12527 | cp = past_reloc; |
12528 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
12529 | ++cp; | |
12530 | second = cp + 1 - past_reloc; | |
28f81592 AM |
12531 | |
12532 | /* Allocate and copy string. The trailing NUL shouldn't | |
12533 | be necessary, but be safe. */ | |
add39d23 | 12534 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 12535 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
12536 | if (second != 0 && *past_reloc != ' ') |
12537 | /* Replace the relocation token with ' ', so that | |
12538 | errors like foo@GOTOFF1 will be detected. */ | |
12539 | tmpbuf[first++] = ' '; | |
af89796a L |
12540 | else |
12541 | /* Increment length by 1 if the relocation token is | |
12542 | removed. */ | |
12543 | len++; | |
12544 | if (adjust) | |
12545 | *adjust = len; | |
0787a12d AM |
12546 | memcpy (tmpbuf + first, past_reloc, second); |
12547 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
12548 | return tmpbuf; |
12549 | } | |
12550 | ||
4fa24527 JB |
12551 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
12552 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
12553 | return NULL; |
12554 | } | |
12555 | } | |
12556 | ||
12557 | /* Might be a symbol version string. Don't as_bad here. */ | |
12558 | return NULL; | |
12559 | } | |
4e4f7c87 | 12560 | #endif |
f3c180ae | 12561 | |
62ebcb5c | 12562 | bfd_reloc_code_real_type |
e3bb37b5 | 12563 | x86_cons (expressionS *exp, int size) |
f3c180ae | 12564 | { |
62ebcb5c AM |
12565 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
12566 | ||
6b50f5f4 JB |
12567 | intel_syntax = -intel_syntax; |
12568 | exp->X_md = 0; | |
5cc00775 | 12569 | expr_mode = expr_operator_none; |
6b50f5f4 | 12570 | |
2748c1b1 L |
12571 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
12572 | && !defined (LEX_AT)) \ | |
12573 | || defined (TE_PE) | |
4fa24527 | 12574 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
12575 | { |
12576 | /* Handle @GOTOFF and the like in an expression. */ | |
12577 | char *save; | |
12578 | char *gotfree_input_line; | |
4a57f2cf | 12579 | int adjust = 0; |
f3c180ae AM |
12580 | |
12581 | save = input_line_pointer; | |
d258b828 | 12582 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
12583 | if (gotfree_input_line) |
12584 | input_line_pointer = gotfree_input_line; | |
12585 | ||
12586 | expression (exp); | |
12587 | ||
12588 | if (gotfree_input_line) | |
12589 | { | |
12590 | /* expression () has merrily parsed up to the end of line, | |
12591 | or a comma - in the wrong buffer. Transfer how far | |
12592 | input_line_pointer has moved to the right buffer. */ | |
12593 | input_line_pointer = (save | |
12594 | + (input_line_pointer - gotfree_input_line) | |
12595 | + adjust); | |
12596 | free (gotfree_input_line); | |
3992d3b7 AM |
12597 | if (exp->X_op == O_constant |
12598 | || exp->X_op == O_absent | |
12599 | || exp->X_op == O_illegal | |
0398aac5 | 12600 | || exp->X_op == O_register |
3992d3b7 AM |
12601 | || exp->X_op == O_big) |
12602 | { | |
12603 | char c = *input_line_pointer; | |
12604 | *input_line_pointer = 0; | |
12605 | as_bad (_("missing or invalid expression `%s'"), save); | |
12606 | *input_line_pointer = c; | |
12607 | } | |
b9519cfe L |
12608 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
12609 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
12610 | && exp->X_op != O_symbol) | |
12611 | { | |
12612 | char c = *input_line_pointer; | |
12613 | *input_line_pointer = 0; | |
12614 | as_bad (_("invalid PLT expression `%s'"), save); | |
12615 | *input_line_pointer = c; | |
12616 | } | |
f3c180ae AM |
12617 | } |
12618 | } | |
12619 | else | |
6b50f5f4 | 12620 | #endif |
f3c180ae | 12621 | expression (exp); |
ee86248c JB |
12622 | |
12623 | intel_syntax = -intel_syntax; | |
12624 | ||
12625 | if (intel_syntax) | |
12626 | i386_intel_simplify (exp); | |
62ebcb5c | 12627 | |
a442cac5 | 12628 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ |
5cc00775 JB |
12629 | if (size <= 4 && expr_mode == expr_operator_present |
12630 | && exp->X_op == O_constant && !object_64bit) | |
a442cac5 JB |
12631 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
12632 | ||
62ebcb5c | 12633 | return got_reloc; |
f3c180ae | 12634 | } |
f3c180ae | 12635 | |
9f32dd5b L |
12636 | static void |
12637 | signed_cons (int size) | |
6482c264 | 12638 | { |
a442cac5 | 12639 | if (object_64bit) |
d182319b JB |
12640 | cons_sign = 1; |
12641 | cons (size); | |
12642 | cons_sign = -1; | |
6482c264 NC |
12643 | } |
12644 | ||
edd67638 JB |
12645 | static void |
12646 | s_insn (int dummy ATTRIBUTE_UNUSED) | |
12647 | { | |
393fbe8d | 12648 | char mnemonic[MAX_MNEM_SIZE], *line = input_line_pointer, *ptr; |
edd67638 JB |
12649 | char *saved_ilp = find_end_of_line (line, false), saved_char; |
12650 | const char *end; | |
12651 | unsigned int j; | |
12652 | valueT val; | |
12653 | bool vex = false, xop = false, evex = false; | |
b5482fe5 | 12654 | struct last_insn *last_insn; |
edd67638 JB |
12655 | |
12656 | init_globals (); | |
12657 | ||
12658 | saved_char = *saved_ilp; | |
12659 | *saved_ilp = 0; | |
12660 | ||
12661 | end = parse_insn (line, mnemonic, true); | |
12662 | if (end == NULL) | |
12663 | { | |
12664 | bad: | |
12665 | *saved_ilp = saved_char; | |
12666 | ignore_rest_of_line (); | |
d0c2e3ec | 12667 | i.tm.mnem_off = 0; |
edd67638 JB |
12668 | return; |
12669 | } | |
12670 | line += end - line; | |
12671 | ||
d3b01414 JB |
12672 | current_templates.start = &i.tm; |
12673 | current_templates.end = &i.tm + 1; | |
edd67638 | 12674 | i.tm.mnem_off = MN__insn; |
393fbe8d | 12675 | i.tm.extension_opcode = None; |
edd67638 JB |
12676 | |
12677 | if (startswith (line, "VEX") | |
12678 | && (line[3] == '.' || is_space_char (line[3]))) | |
12679 | { | |
12680 | vex = true; | |
12681 | line += 3; | |
12682 | } | |
12683 | else if (startswith (line, "XOP") && ISDIGIT (line[3])) | |
12684 | { | |
12685 | char *e; | |
12686 | unsigned long n = strtoul (line + 3, &e, 16); | |
12687 | ||
12688 | if (e == line + 5 && n >= 0x08 && n <= 0x1f | |
12689 | && (*e == '.' || is_space_char (*e))) | |
12690 | { | |
12691 | xop = true; | |
d0c2e3ec JB |
12692 | /* Arrange for build_vex_prefix() to emit 0x8f. */ |
12693 | i.tm.opcode_space = SPACE_XOP08; | |
12694 | i.insn_opcode_space = n; | |
edd67638 JB |
12695 | line = e; |
12696 | } | |
12697 | } | |
12698 | else if (startswith (line, "EVEX") | |
12699 | && (line[4] == '.' || is_space_char (line[4]))) | |
12700 | { | |
12701 | evex = true; | |
12702 | line += 4; | |
12703 | } | |
12704 | ||
12705 | if (vex || xop | |
e346d50a | 12706 | ? i.encoding == encoding_evex |
edd67638 | 12707 | : evex |
e346d50a JB |
12708 | ? i.encoding == encoding_vex |
12709 | || i.encoding == encoding_vex3 | |
12710 | : i.encoding != encoding_default) | |
edd67638 JB |
12711 | { |
12712 | as_bad (_("pseudo-prefix conflicts with encoding specifier")); | |
12713 | goto bad; | |
12714 | } | |
12715 | ||
e346d50a JB |
12716 | if (line > end && i.encoding == encoding_default) |
12717 | i.encoding = evex ? encoding_evex : encoding_vex; | |
0ff3b7d0 | 12718 | |
e346d50a | 12719 | if (i.encoding != encoding_default) |
1adecddd JB |
12720 | { |
12721 | /* Only address size and segment override prefixes are permitted with | |
12722 | VEX/XOP/EVEX encodings. */ | |
12723 | const unsigned char *p = i.prefix; | |
12724 | ||
12725 | for (j = 0; j < ARRAY_SIZE (i.prefix); ++j, ++p) | |
12726 | { | |
12727 | if (!*p) | |
12728 | continue; | |
12729 | ||
12730 | switch (j) | |
12731 | { | |
12732 | case SEG_PREFIX: | |
12733 | case ADDR_PREFIX: | |
12734 | break; | |
12735 | default: | |
12736 | as_bad (_("illegal prefix used with VEX/XOP/EVEX")); | |
12737 | goto bad; | |
12738 | } | |
12739 | } | |
12740 | } | |
12741 | ||
edd67638 JB |
12742 | if (line > end && *line == '.') |
12743 | { | |
d0c2e3ec JB |
12744 | /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */ |
12745 | switch (line[1]) | |
12746 | { | |
12747 | case 'L': | |
12748 | switch (line[2]) | |
12749 | { | |
12750 | case '0': | |
12751 | if (evex) | |
12752 | i.tm.opcode_modifier.evex = EVEX128; | |
12753 | else | |
12754 | i.tm.opcode_modifier.vex = VEX128; | |
12755 | break; | |
12756 | ||
12757 | case '1': | |
12758 | if (evex) | |
12759 | i.tm.opcode_modifier.evex = EVEX256; | |
12760 | else | |
12761 | i.tm.opcode_modifier.vex = VEX256; | |
12762 | break; | |
12763 | ||
12764 | case '2': | |
12765 | if (evex) | |
12766 | i.tm.opcode_modifier.evex = EVEX512; | |
12767 | break; | |
12768 | ||
12769 | case '3': | |
12770 | if (evex) | |
12771 | i.tm.opcode_modifier.evex = EVEX_L3; | |
12772 | break; | |
12773 | ||
12774 | case 'I': | |
12775 | if (line[3] == 'G') | |
12776 | { | |
12777 | if (evex) | |
12778 | i.tm.opcode_modifier.evex = EVEXLIG; | |
12779 | else | |
12780 | i.tm.opcode_modifier.vex = VEXScalar; /* LIG */ | |
12781 | ++line; | |
12782 | } | |
12783 | break; | |
12784 | } | |
12785 | ||
12786 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) | |
12787 | line += 3; | |
12788 | break; | |
12789 | ||
12790 | case '1': | |
12791 | if (line[2] == '2' && line[3] == '8') | |
12792 | { | |
12793 | if (evex) | |
12794 | i.tm.opcode_modifier.evex = EVEX128; | |
12795 | else | |
12796 | i.tm.opcode_modifier.vex = VEX128; | |
12797 | line += 4; | |
12798 | } | |
12799 | break; | |
12800 | ||
12801 | case '2': | |
12802 | if (line[2] == '5' && line[3] == '6') | |
12803 | { | |
12804 | if (evex) | |
12805 | i.tm.opcode_modifier.evex = EVEX256; | |
12806 | else | |
12807 | i.tm.opcode_modifier.vex = VEX256; | |
12808 | line += 4; | |
12809 | } | |
12810 | break; | |
12811 | ||
12812 | case '5': | |
12813 | if (evex && line[2] == '1' && line[3] == '2') | |
12814 | { | |
12815 | i.tm.opcode_modifier.evex = EVEX512; | |
12816 | line += 4; | |
12817 | } | |
12818 | break; | |
12819 | } | |
12820 | } | |
12821 | ||
12822 | if (line > end && *line == '.') | |
12823 | { | |
12824 | /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */ | |
12825 | switch (line[1]) | |
12826 | { | |
12827 | case 'N': | |
12828 | if (line[2] == 'P') | |
12829 | line += 3; | |
12830 | break; | |
12831 | ||
12832 | case '6': | |
12833 | if (line[2] == '6') | |
12834 | { | |
12835 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; | |
12836 | line += 3; | |
12837 | } | |
12838 | break; | |
12839 | ||
12840 | case 'F': case 'f': | |
12841 | if (line[2] == '3') | |
12842 | { | |
12843 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
12844 | line += 3; | |
12845 | } | |
12846 | else if (line[2] == '2') | |
12847 | { | |
12848 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2; | |
12849 | line += 3; | |
12850 | } | |
12851 | break; | |
12852 | } | |
12853 | } | |
12854 | ||
12855 | if (line > end && !xop && *line == '.') | |
12856 | { | |
12857 | /* Encoding space (VEX.mmmmm, EVEX.mmmm). */ | |
12858 | switch (line[1]) | |
12859 | { | |
12860 | case '0': | |
12861 | if (TOUPPER (line[2]) != 'F') | |
12862 | break; | |
12863 | if (line[3] == '.' || is_space_char (line[3])) | |
12864 | { | |
12865 | i.insn_opcode_space = SPACE_0F; | |
12866 | line += 3; | |
12867 | } | |
12868 | else if (line[3] == '3' | |
12869 | && (line[4] == '8' || TOUPPER (line[4]) == 'A') | |
12870 | && (line[5] == '.' || is_space_char (line[5]))) | |
12871 | { | |
12872 | i.insn_opcode_space = line[4] == '8' ? SPACE_0F38 : SPACE_0F3A; | |
12873 | line += 5; | |
12874 | } | |
12875 | break; | |
12876 | ||
12877 | case 'M': | |
12878 | if (ISDIGIT (line[2]) && line[2] != '0') | |
12879 | { | |
12880 | char *e; | |
12881 | unsigned long n = strtoul (line + 2, &e, 10); | |
12882 | ||
12883 | if (n <= (evex ? 15 : 31) | |
12884 | && (*e == '.' || is_space_char (*e))) | |
12885 | { | |
12886 | i.insn_opcode_space = n; | |
12887 | line = e; | |
12888 | } | |
12889 | } | |
12890 | break; | |
12891 | } | |
12892 | } | |
12893 | ||
12894 | if (line > end && *line == '.' && line[1] == 'W') | |
12895 | { | |
12896 | /* VEX.W, XOP.W, EVEX.W */ | |
12897 | switch (line[2]) | |
12898 | { | |
12899 | case '0': | |
12900 | i.tm.opcode_modifier.vexw = VEXW0; | |
12901 | break; | |
12902 | ||
12903 | case '1': | |
12904 | i.tm.opcode_modifier.vexw = VEXW1; | |
12905 | break; | |
12906 | ||
12907 | case 'I': | |
12908 | if (line[3] == 'G') | |
12909 | { | |
12910 | i.tm.opcode_modifier.vexw = VEXWIG; | |
12911 | ++line; | |
12912 | } | |
12913 | break; | |
12914 | } | |
12915 | ||
12916 | if (i.tm.opcode_modifier.vexw) | |
12917 | line += 3; | |
12918 | } | |
12919 | ||
12920 | if (line > end && *line && !is_space_char (*line)) | |
12921 | { | |
12922 | /* Improve diagnostic a little. */ | |
12923 | if (*line == '.' && line[1] && !is_space_char (line[1])) | |
12924 | ++line; | |
12925 | goto done; | |
edd67638 JB |
12926 | } |
12927 | ||
393fbe8d JB |
12928 | /* Before processing the opcode expression, find trailing "+r" or |
12929 | "/<digit>" specifiers. */ | |
12930 | for (ptr = line; ; ++ptr) | |
12931 | { | |
12932 | unsigned long n; | |
12933 | char *e; | |
12934 | ||
12935 | ptr = strpbrk (ptr, "+/,"); | |
12936 | if (ptr == NULL || *ptr == ',') | |
12937 | break; | |
12938 | ||
12939 | if (*ptr == '+' && ptr[1] == 'r' | |
12940 | && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ','))) | |
12941 | { | |
12942 | *ptr = ' '; | |
12943 | ptr[1] = ' '; | |
12944 | i.short_form = true; | |
12945 | break; | |
12946 | } | |
12947 | ||
12948 | if (*ptr == '/' && ISDIGIT (ptr[1]) | |
12949 | && (n = strtoul (ptr + 1, &e, 8)) < 8 | |
12950 | && e == ptr + 2 | |
12951 | && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ','))) | |
12952 | { | |
12953 | *ptr = ' '; | |
12954 | ptr[1] = ' '; | |
12955 | i.tm.extension_opcode = n; | |
12956 | i.tm.opcode_modifier.modrm = 1; | |
12957 | break; | |
12958 | } | |
12959 | } | |
12960 | ||
edd67638 JB |
12961 | input_line_pointer = line; |
12962 | val = get_absolute_expression (); | |
12963 | line = input_line_pointer; | |
12964 | ||
393fbe8d JB |
12965 | if (i.short_form && (val & 7)) |
12966 | as_warn ("`+r' assumes low three opcode bits to be clear"); | |
12967 | ||
edd67638 JB |
12968 | for (j = 1; j < sizeof(val); ++j) |
12969 | if (!(val >> (j * 8))) | |
12970 | break; | |
12971 | ||
12972 | /* Trim off a prefix if present. */ | |
12973 | if (j > 1 && !vex && !xop && !evex) | |
12974 | { | |
12975 | uint8_t byte = val >> ((j - 1) * 8); | |
12976 | ||
12977 | switch (byte) | |
12978 | { | |
12979 | case DATA_PREFIX_OPCODE: | |
12980 | case REPE_PREFIX_OPCODE: | |
12981 | case REPNE_PREFIX_OPCODE: | |
12982 | if (!add_prefix (byte)) | |
12983 | goto bad; | |
12984 | val &= ((uint64_t)1 << (--j * 8)) - 1; | |
12985 | break; | |
12986 | } | |
12987 | } | |
12988 | ||
6804f42c JB |
12989 | /* Parse operands, if any, before evaluating encoding space. */ |
12990 | if (*line == ',') | |
12991 | { | |
12992 | i.memshift = -1; | |
12993 | ||
12994 | ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]); | |
12995 | this_operand = -1; | |
12996 | if (!ptr) | |
12997 | goto bad; | |
12998 | line = ptr; | |
12999 | ||
13000 | if (!i.operands) | |
13001 | { | |
13002 | as_bad (_("expecting operand after ','; got nothing")); | |
13003 | goto done; | |
13004 | } | |
13005 | ||
13006 | if (i.mem_operands > 1) | |
13007 | { | |
13008 | as_bad (_("too many memory references for `%s'"), | |
13009 | &i386_mnemonics[MN__insn]); | |
13010 | goto done; | |
13011 | } | |
13012 | ||
13013 | /* No need to distinguish encoding_evex and encoding_evex512. */ | |
13014 | if (i.encoding == encoding_evex512) | |
13015 | i.encoding = encoding_evex; | |
13016 | } | |
13017 | ||
edd67638 | 13018 | /* Trim off encoding space. */ |
d0c2e3ec | 13019 | if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f) |
edd67638 JB |
13020 | { |
13021 | uint8_t byte = val >> ((--j - 1) * 8); | |
13022 | ||
d0c2e3ec | 13023 | i.insn_opcode_space = SPACE_0F; |
6804f42c JB |
13024 | switch (byte & -(j > 1 && !i.rex2_encoding |
13025 | && (i.encoding != encoding_egpr || evex))) | |
edd67638 JB |
13026 | { |
13027 | case 0x38: | |
d0c2e3ec | 13028 | i.insn_opcode_space = SPACE_0F38; |
edd67638 JB |
13029 | --j; |
13030 | break; | |
13031 | case 0x3a: | |
d0c2e3ec | 13032 | i.insn_opcode_space = SPACE_0F3A; |
edd67638 JB |
13033 | --j; |
13034 | break; | |
13035 | } | |
d0c2e3ec | 13036 | i.tm.opcode_space = i.insn_opcode_space; |
edd67638 JB |
13037 | val &= ((uint64_t)1 << (j * 8)) - 1; |
13038 | } | |
d0c2e3ec JB |
13039 | if (!i.tm.opcode_space && (vex || evex)) |
13040 | /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5. | |
13041 | Also avoid hitting abort() there or in build_evex_prefix(). */ | |
13042 | i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F | |
13043 | : SPACE_0F38; | |
edd67638 JB |
13044 | |
13045 | if (j > 2) | |
13046 | { | |
13047 | as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val); | |
6804f42c | 13048 | goto done; |
edd67638 JB |
13049 | } |
13050 | i.opcode_length = j; | |
0ff3b7d0 JB |
13051 | |
13052 | /* Handle operands, if any. */ | |
6804f42c | 13053 | if (i.operands) |
0ff3b7d0 JB |
13054 | { |
13055 | i386_operand_type combined; | |
f7377a91 | 13056 | expressionS *disp_exp = NULL; |
0ff3b7d0 JB |
13057 | bool changed; |
13058 | ||
eb3f3841 JB |
13059 | if (i.encoding == encoding_egpr) |
13060 | { | |
13061 | if (vex || xop) | |
13062 | { | |
13063 | as_bad (_("eGPR use conflicts with encoding specifier")); | |
13064 | goto done; | |
13065 | } | |
13066 | if (evex) | |
13067 | i.encoding = encoding_evex; | |
13068 | else | |
13069 | i.encoding = encoding_default; | |
13070 | } | |
13071 | ||
0ff3b7d0 JB |
13072 | /* Are we to emit ModR/M encoding? */ |
13073 | if (!i.short_form | |
13074 | && (i.mem_operands | |
e346d50a | 13075 | || i.reg_operands > (i.encoding != encoding_default) |
0ff3b7d0 JB |
13076 | || i.tm.extension_opcode != None)) |
13077 | i.tm.opcode_modifier.modrm = 1; | |
13078 | ||
13079 | if (!i.tm.opcode_modifier.modrm | |
13080 | && (i.reg_operands | |
e346d50a | 13081 | > i.short_form + 0U + (i.encoding != encoding_default) |
0ff3b7d0 JB |
13082 | || i.mem_operands)) |
13083 | { | |
13084 | as_bad (_("too many register/memory operands")); | |
13085 | goto done; | |
13086 | } | |
13087 | ||
13088 | /* Enforce certain constraints on operands. */ | |
13089 | switch (i.reg_operands + i.mem_operands | |
13090 | + (i.tm.extension_opcode != None)) | |
13091 | { | |
13092 | case 0: | |
13093 | if (i.short_form) | |
13094 | { | |
13095 | as_bad (_("too few register/memory operands")); | |
13096 | goto done; | |
13097 | } | |
13098 | /* Fall through. */ | |
13099 | case 1: | |
13100 | if (i.tm.opcode_modifier.modrm) | |
13101 | { | |
13102 | as_bad (_("too few register/memory operands")); | |
13103 | goto done; | |
13104 | } | |
13105 | break; | |
13106 | ||
13107 | case 2: | |
13108 | break; | |
13109 | ||
13110 | case 4: | |
13111 | if (i.imm_operands | |
13112 | && (i.op[0].imms->X_op != O_constant | |
13113 | || !fits_in_imm4 (i.op[0].imms->X_add_number))) | |
13114 | { | |
13115 | as_bad (_("constant doesn't fit in %d bits"), evex ? 3 : 4); | |
13116 | goto done; | |
13117 | } | |
13118 | /* Fall through. */ | |
13119 | case 3: | |
e346d50a | 13120 | if (i.encoding != encoding_default) |
0ff3b7d0 JB |
13121 | { |
13122 | i.tm.opcode_modifier.vexvvvv = 1; | |
13123 | break; | |
13124 | } | |
13125 | /* Fall through. */ | |
13126 | default: | |
13127 | as_bad (_("too many register/memory operands")); | |
13128 | goto done; | |
13129 | } | |
13130 | ||
13131 | /* Bring operands into canonical order (imm, mem, reg). */ | |
13132 | do | |
13133 | { | |
13134 | changed = false; | |
13135 | ||
13136 | for (j = 1; j < i.operands; ++j) | |
13137 | { | |
13138 | if ((!operand_type_check (i.types[j - 1], imm) | |
13139 | && operand_type_check (i.types[j], imm)) | |
13140 | || (i.types[j - 1].bitfield.class != ClassNone | |
13141 | && i.types[j].bitfield.class == ClassNone)) | |
13142 | { | |
13143 | swap_2_operands (j - 1, j); | |
13144 | changed = true; | |
13145 | } | |
13146 | } | |
13147 | } | |
13148 | while (changed); | |
13149 | ||
13150 | /* For Intel syntax swap the order of register operands. */ | |
13151 | if (intel_syntax) | |
13152 | switch (i.reg_operands) | |
13153 | { | |
13154 | case 0: | |
13155 | case 1: | |
13156 | break; | |
13157 | ||
13158 | case 4: | |
13159 | swap_2_operands (i.imm_operands + i.mem_operands + 1, i.operands - 2); | |
13160 | /* Fall through. */ | |
13161 | case 3: | |
13162 | case 2: | |
13163 | swap_2_operands (i.imm_operands + i.mem_operands, i.operands - 1); | |
13164 | break; | |
13165 | ||
13166 | default: | |
13167 | abort (); | |
13168 | } | |
13169 | ||
13170 | /* Enforce constraints when using VSIB. */ | |
13171 | if (i.index_reg | |
13172 | && (i.index_reg->reg_type.bitfield.xmmword | |
13173 | || i.index_reg->reg_type.bitfield.ymmword | |
13174 | || i.index_reg->reg_type.bitfield.zmmword)) | |
13175 | { | |
e346d50a | 13176 | if (i.encoding == encoding_default) |
0ff3b7d0 JB |
13177 | { |
13178 | as_bad (_("VSIB unavailable with legacy encoding")); | |
13179 | goto done; | |
13180 | } | |
13181 | ||
e346d50a | 13182 | if (i.encoding == encoding_evex |
0ff3b7d0 JB |
13183 | && i.reg_operands > 1) |
13184 | { | |
13185 | /* We could allow two register operands, encoding the 2nd one in | |
13186 | an 8-bit immediate like for 4-register-operand insns, but that | |
13187 | would require ugly fiddling with process_operands() and/or | |
13188 | build_modrm_byte(). */ | |
13189 | as_bad (_("too many register operands with VSIB")); | |
13190 | goto done; | |
13191 | } | |
13192 | ||
13193 | i.tm.opcode_modifier.sib = 1; | |
13194 | } | |
13195 | ||
13196 | /* Establish operand size encoding. */ | |
13197 | operand_type_set (&combined, 0); | |
f7377a91 | 13198 | |
0ff3b7d0 JB |
13199 | for (j = i.imm_operands; j < i.operands; ++j) |
13200 | { | |
3e4a511b | 13201 | /* Look for 8-bit operands that use old registers. */ |
e346d50a | 13202 | if (i.encoding != encoding_default |
3e4a511b JB |
13203 | && flag_code == CODE_64BIT |
13204 | && i.types[j].bitfield.class == Reg | |
13205 | && i.types[j].bitfield.byte | |
13206 | && !(i.op[j].regs->reg_flags & RegRex64) | |
13207 | && i.op[j].regs->reg_num > 3) | |
13208 | as_bad (_("can't encode register '%s%s' with VEX/XOP/EVEX"), | |
13209 | register_prefix, i.op[j].regs->reg_name); | |
13210 | ||
0ff3b7d0 JB |
13211 | i.types[j].bitfield.instance = InstanceNone; |
13212 | ||
13213 | if (operand_type_check (i.types[j], disp)) | |
f7377a91 JB |
13214 | { |
13215 | i.types[j].bitfield.baseindex = 1; | |
13216 | disp_exp = i.op[j].disps; | |
13217 | } | |
13218 | ||
13219 | if (evex && i.types[j].bitfield.baseindex) | |
13220 | { | |
13221 | unsigned int n = i.memshift; | |
13222 | ||
13223 | if (i.types[j].bitfield.byte) | |
13224 | n = 0; | |
13225 | else if (i.types[j].bitfield.word) | |
13226 | n = 1; | |
13227 | else if (i.types[j].bitfield.dword) | |
13228 | n = 2; | |
13229 | else if (i.types[j].bitfield.qword) | |
13230 | n = 3; | |
13231 | else if (i.types[j].bitfield.xmmword) | |
13232 | n = 4; | |
13233 | else if (i.types[j].bitfield.ymmword) | |
13234 | n = 5; | |
13235 | else if (i.types[j].bitfield.zmmword) | |
13236 | n = 6; | |
13237 | ||
13238 | if (i.memshift < 32 && n != i.memshift) | |
13239 | as_warn ("conflicting memory operand size specifiers"); | |
13240 | i.memshift = n; | |
13241 | } | |
0ff3b7d0 JB |
13242 | |
13243 | if ((i.broadcast.type || i.broadcast.bytes) | |
13244 | && j == i.broadcast.operand) | |
13245 | continue; | |
13246 | ||
13247 | combined = operand_type_or (combined, i.types[j]); | |
13248 | combined.bitfield.class = ClassNone; | |
13249 | } | |
13250 | ||
f7377a91 JB |
13251 | switch ((i.broadcast.type ? i.broadcast.type : 1) |
13252 | << (i.memshift < 32 ? i.memshift : 0)) | |
13253 | { | |
13254 | case 64: combined.bitfield.zmmword = 1; break; | |
13255 | case 32: combined.bitfield.ymmword = 1; break; | |
13256 | case 16: combined.bitfield.xmmword = 1; break; | |
13257 | case 8: combined.bitfield.qword = 1; break; | |
13258 | case 4: combined.bitfield.dword = 1; break; | |
13259 | } | |
13260 | ||
e346d50a | 13261 | if (i.encoding == encoding_default) |
0ff3b7d0 JB |
13262 | { |
13263 | if (flag_code == CODE_64BIT && combined.bitfield.qword) | |
13264 | i.rex |= REX_W; | |
13265 | else if ((flag_code == CODE_16BIT ? combined.bitfield.dword | |
13266 | : combined.bitfield.word) | |
13267 | && !add_prefix (DATA_PREFIX_OPCODE)) | |
13268 | goto done; | |
13269 | } | |
13270 | else if (!i.tm.opcode_modifier.vexw) | |
13271 | { | |
13272 | if (flag_code == CODE_64BIT) | |
13273 | { | |
13274 | if (combined.bitfield.qword) | |
13275 | i.tm.opcode_modifier.vexw = VEXW1; | |
13276 | else if (combined.bitfield.dword) | |
13277 | i.tm.opcode_modifier.vexw = VEXW0; | |
13278 | } | |
13279 | ||
13280 | if (!i.tm.opcode_modifier.vexw) | |
13281 | i.tm.opcode_modifier.vexw = VEXWIG; | |
13282 | } | |
13283 | ||
13284 | if (vex || xop) | |
13285 | { | |
13286 | if (!i.tm.opcode_modifier.vex) | |
13287 | { | |
13288 | if (combined.bitfield.ymmword) | |
13289 | i.tm.opcode_modifier.vex = VEX256; | |
13290 | else if (combined.bitfield.xmmword) | |
13291 | i.tm.opcode_modifier.vex = VEX128; | |
13292 | } | |
13293 | } | |
13294 | else if (evex) | |
13295 | { | |
13296 | if (!i.tm.opcode_modifier.evex) | |
13297 | { | |
13298 | /* Do _not_ consider AVX512VL here. */ | |
13299 | if (i.rounding.type != rc_none || combined.bitfield.zmmword) | |
13300 | i.tm.opcode_modifier.evex = EVEX512; | |
13301 | else if (combined.bitfield.ymmword) | |
13302 | i.tm.opcode_modifier.evex = EVEX256; | |
13303 | else if (combined.bitfield.xmmword) | |
13304 | i.tm.opcode_modifier.evex = EVEX128; | |
13305 | } | |
f7377a91 JB |
13306 | |
13307 | if (i.memshift >= 32) | |
13308 | { | |
13309 | unsigned int n = 0; | |
13310 | ||
13311 | switch (i.tm.opcode_modifier.evex) | |
13312 | { | |
13313 | case EVEX512: n = 64; break; | |
13314 | case EVEX256: n = 32; break; | |
13315 | case EVEX128: n = 16; break; | |
13316 | } | |
13317 | ||
13318 | if (i.broadcast.type) | |
13319 | n /= i.broadcast.type; | |
13320 | ||
13321 | if (n > 0) | |
13322 | for (i.memshift = 0; !(n & 1); n >>= 1) | |
13323 | ++i.memshift; | |
13324 | else if (disp_exp != NULL && disp_exp->X_op == O_constant | |
13325 | && disp_exp->X_add_number != 0 | |
13326 | && i.disp_encoding != disp_encoding_32bit) | |
13327 | { | |
13328 | if (!quiet_warnings) | |
13329 | as_warn ("cannot determine memory operand size"); | |
13330 | i.disp_encoding = disp_encoding_32bit; | |
13331 | } | |
13332 | } | |
0ff3b7d0 JB |
13333 | } |
13334 | ||
f7377a91 JB |
13335 | if (i.memshift >= 32) |
13336 | i.memshift = 0; | |
13337 | else if (!evex) | |
e346d50a | 13338 | i.encoding = encoding_error; |
f7377a91 | 13339 | |
0ff3b7d0 JB |
13340 | if (i.disp_operands && !optimize_disp (&i.tm)) |
13341 | goto done; | |
13342 | ||
c032bc4f JB |
13343 | /* Establish size for immediate operands. */ |
13344 | for (j = 0; j < i.imm_operands; ++j) | |
13345 | { | |
13346 | expressionS *expP = i.op[j].imms; | |
13347 | ||
13348 | gas_assert (operand_type_check (i.types[j], imm)); | |
13349 | operand_type_set (&i.types[j], 0); | |
13350 | ||
13351 | if (i.imm_bits[j] > 32) | |
13352 | i.types[j].bitfield.imm64 = 1; | |
13353 | else if (i.imm_bits[j] > 16) | |
13354 | { | |
13355 | if (flag_code == CODE_64BIT && (i.flags[j] & Operand_Signed)) | |
13356 | i.types[j].bitfield.imm32s = 1; | |
13357 | else | |
13358 | i.types[j].bitfield.imm32 = 1; | |
13359 | } | |
13360 | else if (i.imm_bits[j] > 8) | |
13361 | i.types[j].bitfield.imm16 = 1; | |
13362 | else if (i.imm_bits[j] > 0) | |
13363 | { | |
13364 | if (i.flags[j] & Operand_Signed) | |
13365 | i.types[j].bitfield.imm8s = 1; | |
13366 | else | |
13367 | i.types[j].bitfield.imm8 = 1; | |
13368 | } | |
13369 | else if (expP->X_op == O_constant) | |
13370 | { | |
13371 | i.types[j] = smallest_imm_type (expP->X_add_number); | |
13372 | i.types[j].bitfield.imm1 = 0; | |
13373 | /* Oddly enough imm_size() checks imm64 first, so the bit needs | |
13374 | zapping since smallest_imm_type() sets it unconditionally. */ | |
13375 | if (flag_code != CODE_64BIT) | |
13376 | { | |
13377 | i.types[j].bitfield.imm64 = 0; | |
13378 | i.types[j].bitfield.imm32s = 0; | |
13379 | i.types[j].bitfield.imm32 = 1; | |
13380 | } | |
13381 | else if (i.types[j].bitfield.imm32 || i.types[j].bitfield.imm32s) | |
13382 | i.types[j].bitfield.imm64 = 0; | |
13383 | } | |
13384 | else | |
13385 | /* Non-constant expressions are sized heuristically. */ | |
13386 | switch (flag_code) | |
13387 | { | |
13388 | case CODE_64BIT: i.types[j].bitfield.imm32s = 1; break; | |
13389 | case CODE_32BIT: i.types[j].bitfield.imm32 = 1; break; | |
13390 | case CODE_16BIT: i.types[j].bitfield.imm16 = 1; break; | |
13391 | } | |
13392 | } | |
13393 | ||
0ff3b7d0 JB |
13394 | for (j = 0; j < i.operands; ++j) |
13395 | i.tm.operand_types[j] = i.types[j]; | |
13396 | ||
13397 | process_operands (); | |
13398 | } | |
13399 | ||
13400 | /* Don't set opcode until after processing operands, to avoid any | |
13401 | potential special casing there. */ | |
13402 | i.tm.base_opcode |= val; | |
13403 | ||
e346d50a JB |
13404 | if (i.encoding == encoding_error |
13405 | || (i.encoding != encoding_evex | |
0ff3b7d0 JB |
13406 | ? i.broadcast.type || i.broadcast.bytes |
13407 | || i.rounding.type != rc_none | |
13408 | || i.mask.reg | |
f586e340 JB |
13409 | : (i.mem_operands && i.rounding.type != rc_none) |
13410 | || ((i.broadcast.type || i.broadcast.bytes) | |
13411 | && !(i.flags[i.broadcast.operand] & Operand_Mem)))) | |
0ff3b7d0 JB |
13412 | { |
13413 | as_bad (_("conflicting .insn operands")); | |
13414 | goto done; | |
13415 | } | |
edd67638 | 13416 | |
d0c2e3ec JB |
13417 | if (vex || xop) |
13418 | { | |
13419 | if (!i.tm.opcode_modifier.vex) | |
13420 | i.tm.opcode_modifier.vex = VEXScalar; /* LIG */ | |
13421 | ||
13422 | build_vex_prefix (NULL); | |
13423 | i.rex &= REX_OPCODE; | |
13424 | } | |
13425 | else if (evex) | |
13426 | { | |
13427 | if (!i.tm.opcode_modifier.evex) | |
13428 | i.tm.opcode_modifier.evex = EVEXLIG; | |
13429 | ||
13430 | build_evex_prefix (); | |
13431 | i.rex &= REX_OPCODE; | |
13432 | } | |
ce705688 JB |
13433 | else |
13434 | establish_rex (); | |
d0c2e3ec | 13435 | |
b5482fe5 JB |
13436 | last_insn = &seg_info(now_seg)->tc_segment_info_data.last_insn; |
13437 | output_insn (last_insn); | |
13438 | last_insn->kind = last_insn_directive; | |
13439 | last_insn->name = ".insn directive"; | |
13440 | last_insn->file = as_where (&last_insn->line); | |
edd67638 | 13441 | |
c7defc53 IB |
13442 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
13443 | /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been | |
13444 | performed in i386_target_format. */ | |
13445 | if (IS_ELF && flag_synth_cfi) | |
13446 | as_bad (_("SCFI: hand-crafting instructions not supported")); | |
13447 | #endif | |
13448 | ||
d0c2e3ec | 13449 | done: |
edd67638 JB |
13450 | *saved_ilp = saved_char; |
13451 | input_line_pointer = line; | |
13452 | ||
13453 | demand_empty_rest_of_line (); | |
d0c2e3ec JB |
13454 | |
13455 | /* Make sure dot_insn() won't yield "true" anymore. */ | |
13456 | i.tm.mnem_off = 0; | |
edd67638 JB |
13457 | } |
13458 | ||
d182319b | 13459 | #ifdef TE_PE |
6482c264 | 13460 | static void |
7016a5d5 | 13461 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
13462 | { |
13463 | expressionS exp; | |
13464 | ||
13465 | do | |
13466 | { | |
13467 | expression (&exp); | |
13468 | if (exp.X_op == O_symbol) | |
13469 | exp.X_op = O_secrel; | |
13470 | ||
13471 | emit_expr (&exp, 4); | |
13472 | } | |
13473 | while (*input_line_pointer++ == ','); | |
13474 | ||
13475 | input_line_pointer--; | |
13476 | demand_empty_rest_of_line (); | |
13477 | } | |
145667f8 MH |
13478 | |
13479 | static void | |
13480 | pe_directive_secidx (int dummy ATTRIBUTE_UNUSED) | |
13481 | { | |
13482 | expressionS exp; | |
13483 | ||
13484 | do | |
13485 | { | |
13486 | expression (&exp); | |
13487 | if (exp.X_op == O_symbol) | |
13488 | exp.X_op = O_secidx; | |
13489 | ||
13490 | emit_expr (&exp, 2); | |
13491 | } | |
13492 | while (*input_line_pointer++ == ','); | |
13493 | ||
13494 | input_line_pointer--; | |
13495 | demand_empty_rest_of_line (); | |
13496 | } | |
6482c264 NC |
13497 | #endif |
13498 | ||
7063667e JB |
13499 | /* Handle Rounding Control / SAE specifiers. */ |
13500 | ||
13501 | static char * | |
13502 | RC_SAE_specifier (const char *pstr) | |
13503 | { | |
13504 | unsigned int j; | |
13505 | ||
13506 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
13507 | { | |
13508 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
13509 | { | |
13510 | if (i.rounding.type != rc_none) | |
13511 | { | |
13512 | as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name); | |
13513 | return NULL; | |
13514 | } | |
13515 | ||
eb3f3841 JB |
13516 | switch (i.encoding) |
13517 | { | |
13518 | case encoding_default: | |
13519 | case encoding_egpr: | |
13520 | i.encoding = encoding_evex512; | |
13521 | break; | |
13522 | case encoding_evex: | |
13523 | case encoding_evex512: | |
13524 | break; | |
13525 | default: | |
13526 | return NULL; | |
13527 | } | |
a6f3add0 | 13528 | |
7063667e JB |
13529 | i.rounding.type = RC_NamesTable[j].type; |
13530 | ||
13531 | return (char *)(pstr + RC_NamesTable[j].len); | |
13532 | } | |
13533 | } | |
13534 | ||
13535 | return NULL; | |
13536 | } | |
13537 | ||
43234a1e L |
13538 | /* Handle Vector operations. */ |
13539 | ||
13540 | static char * | |
f70c6814 | 13541 | check_VecOperations (char *op_string) |
43234a1e L |
13542 | { |
13543 | const reg_entry *mask; | |
13544 | const char *saved; | |
13545 | char *end_op; | |
13546 | ||
f70c6814 | 13547 | while (*op_string) |
43234a1e L |
13548 | { |
13549 | saved = op_string; | |
13550 | if (*op_string == '{') | |
13551 | { | |
13552 | op_string++; | |
13553 | ||
13554 | /* Check broadcasts. */ | |
d34049e8 | 13555 | if (startswith (op_string, "1to")) |
43234a1e | 13556 | { |
5273a3cd | 13557 | unsigned int bcst_type; |
43234a1e | 13558 | |
5273a3cd | 13559 | if (i.broadcast.type) |
43234a1e L |
13560 | goto duplicated_vec_op; |
13561 | ||
13562 | op_string += 3; | |
13563 | if (*op_string == '8') | |
8e6e0792 | 13564 | bcst_type = 8; |
b28d1bda | 13565 | else if (*op_string == '4') |
8e6e0792 | 13566 | bcst_type = 4; |
b28d1bda | 13567 | else if (*op_string == '2') |
8e6e0792 | 13568 | bcst_type = 2; |
43234a1e L |
13569 | else if (*op_string == '1' |
13570 | && *(op_string+1) == '6') | |
13571 | { | |
8e6e0792 | 13572 | bcst_type = 16; |
43234a1e L |
13573 | op_string++; |
13574 | } | |
0cc78721 CL |
13575 | else if (*op_string == '3' |
13576 | && *(op_string+1) == '2') | |
13577 | { | |
13578 | bcst_type = 32; | |
13579 | op_string++; | |
13580 | } | |
43234a1e L |
13581 | else |
13582 | { | |
13583 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
13584 | return NULL; | |
13585 | } | |
13586 | op_string++; | |
13587 | ||
eb3f3841 JB |
13588 | switch (i.encoding) |
13589 | { | |
13590 | case encoding_default: | |
13591 | case encoding_egpr: | |
13592 | i.encoding = encoding_evex; | |
13593 | break; | |
13594 | case encoding_evex: | |
13595 | case encoding_evex512: | |
13596 | break; | |
13597 | default: | |
13598 | goto unknown_vec_op; | |
13599 | } | |
a6f3add0 | 13600 | |
5273a3cd JB |
13601 | i.broadcast.type = bcst_type; |
13602 | i.broadcast.operand = this_operand; | |
f7377a91 JB |
13603 | |
13604 | /* For .insn a data size specifier may be appended. */ | |
13605 | if (dot_insn () && *op_string == ':') | |
13606 | goto dot_insn_modifier; | |
13607 | } | |
13608 | /* Check .insn special cases. */ | |
13609 | else if (dot_insn () && *op_string == ':') | |
13610 | { | |
13611 | dot_insn_modifier: | |
c032bc4f | 13612 | switch (op_string[1]) |
f7377a91 JB |
13613 | { |
13614 | unsigned long n; | |
13615 | ||
c032bc4f | 13616 | case 'd': |
f7377a91 JB |
13617 | if (i.memshift < 32) |
13618 | goto duplicated_vec_op; | |
13619 | ||
13620 | n = strtoul (op_string + 2, &end_op, 0); | |
13621 | if (n) | |
13622 | for (i.memshift = 0; !(n & 1); n >>= 1) | |
13623 | ++i.memshift; | |
13624 | if (i.memshift < 32 && n == 1) | |
13625 | op_string = end_op; | |
c032bc4f JB |
13626 | break; |
13627 | ||
13628 | case 's': case 'u': | |
13629 | /* This isn't really a "vector" operation, but a sign/size | |
13630 | specifier for immediate operands of .insn. Note that AT&T | |
13631 | syntax handles the same in i386_immediate(). */ | |
13632 | if (!intel_syntax) | |
13633 | break; | |
13634 | ||
13635 | if (i.imm_bits[this_operand]) | |
13636 | goto duplicated_vec_op; | |
13637 | ||
13638 | n = strtoul (op_string + 2, &end_op, 0); | |
13639 | if (n && n <= (flag_code == CODE_64BIT ? 64 : 32)) | |
13640 | { | |
13641 | i.imm_bits[this_operand] = n; | |
13642 | if (op_string[1] == 's') | |
13643 | i.flags[this_operand] |= Operand_Signed; | |
13644 | op_string = end_op; | |
13645 | } | |
13646 | break; | |
f7377a91 | 13647 | } |
43234a1e L |
13648 | } |
13649 | /* Check masking operation. */ | |
13650 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
13651 | { | |
8a6fb3f9 JB |
13652 | if (mask == &bad_reg) |
13653 | return NULL; | |
13654 | ||
43234a1e | 13655 | /* k0 can't be used for write mask. */ |
f74a6307 | 13656 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 13657 | { |
6d2cd6b2 JB |
13658 | as_bad (_("`%s%s' can't be used for write mask"), |
13659 | register_prefix, mask->reg_name); | |
43234a1e L |
13660 | return NULL; |
13661 | } | |
13662 | ||
6225c532 | 13663 | if (!i.mask.reg) |
43234a1e | 13664 | { |
6225c532 JB |
13665 | i.mask.reg = mask; |
13666 | i.mask.operand = this_operand; | |
43234a1e | 13667 | } |
6225c532 JB |
13668 | else if (i.mask.reg->reg_num) |
13669 | goto duplicated_vec_op; | |
43234a1e L |
13670 | else |
13671 | { | |
6225c532 | 13672 | i.mask.reg = mask; |
43234a1e L |
13673 | |
13674 | /* Only "{z}" is allowed here. No need to check | |
13675 | zeroing mask explicitly. */ | |
6225c532 | 13676 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
13677 | { |
13678 | as_bad (_("invalid write mask `%s'"), saved); | |
13679 | return NULL; | |
13680 | } | |
13681 | } | |
13682 | ||
13683 | op_string = end_op; | |
13684 | } | |
13685 | /* Check zeroing-flag for masking operation. */ | |
13686 | else if (*op_string == 'z') | |
13687 | { | |
6225c532 | 13688 | if (!i.mask.reg) |
43234a1e | 13689 | { |
6225c532 JB |
13690 | i.mask.reg = reg_k0; |
13691 | i.mask.zeroing = 1; | |
13692 | i.mask.operand = this_operand; | |
43234a1e L |
13693 | } |
13694 | else | |
13695 | { | |
6225c532 | 13696 | if (i.mask.zeroing) |
43234a1e L |
13697 | { |
13698 | duplicated_vec_op: | |
13699 | as_bad (_("duplicated `%s'"), saved); | |
13700 | return NULL; | |
13701 | } | |
13702 | ||
6225c532 | 13703 | i.mask.zeroing = 1; |
43234a1e L |
13704 | |
13705 | /* Only "{%k}" is allowed here. No need to check mask | |
13706 | register explicitly. */ | |
6225c532 | 13707 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
13708 | { |
13709 | as_bad (_("invalid zeroing-masking `%s'"), | |
13710 | saved); | |
13711 | return NULL; | |
13712 | } | |
13713 | } | |
13714 | ||
13715 | op_string++; | |
13716 | } | |
7063667e JB |
13717 | else if (intel_syntax |
13718 | && (op_string = RC_SAE_specifier (op_string)) != NULL) | |
13719 | i.rounding.modifier = true; | |
43234a1e L |
13720 | else |
13721 | goto unknown_vec_op; | |
13722 | ||
13723 | if (*op_string != '}') | |
13724 | { | |
13725 | as_bad (_("missing `}' in `%s'"), saved); | |
13726 | return NULL; | |
13727 | } | |
13728 | op_string++; | |
0ba3a731 L |
13729 | |
13730 | /* Strip whitespace since the addition of pseudo prefixes | |
13731 | changed how the scrubber treats '{'. */ | |
13732 | if (is_space_char (*op_string)) | |
13733 | ++op_string; | |
13734 | ||
43234a1e L |
13735 | continue; |
13736 | } | |
13737 | unknown_vec_op: | |
13738 | /* We don't know this one. */ | |
13739 | as_bad (_("unknown vector operation: `%s'"), saved); | |
13740 | return NULL; | |
13741 | } | |
13742 | ||
6225c532 | 13743 | if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num) |
6d2cd6b2 JB |
13744 | { |
13745 | as_bad (_("zeroing-masking only allowed with write mask")); | |
13746 | return NULL; | |
13747 | } | |
13748 | ||
43234a1e L |
13749 | return op_string; |
13750 | } | |
13751 | ||
252b5132 | 13752 | static int |
70e41ade | 13753 | i386_immediate (char *imm_start) |
252b5132 RH |
13754 | { |
13755 | char *save_input_line_pointer; | |
f3c180ae | 13756 | char *gotfree_input_line; |
252b5132 | 13757 | segT exp_seg = 0; |
47926f60 | 13758 | expressionS *exp; |
40fb9820 L |
13759 | i386_operand_type types; |
13760 | ||
0dfbf9d7 | 13761 | operand_type_set (&types, ~0); |
252b5132 RH |
13762 | |
13763 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
13764 | { | |
31b2323c L |
13765 | as_bad (_("at most %d immediate operands are allowed"), |
13766 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
13767 | return 0; |
13768 | } | |
13769 | ||
13770 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 13771 | i.op[this_operand].imms = exp; |
252b5132 RH |
13772 | |
13773 | if (is_space_char (*imm_start)) | |
13774 | ++imm_start; | |
13775 | ||
13776 | save_input_line_pointer = input_line_pointer; | |
13777 | input_line_pointer = imm_start; | |
13778 | ||
d258b828 | 13779 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
13780 | if (gotfree_input_line) |
13781 | input_line_pointer = gotfree_input_line; | |
252b5132 | 13782 | |
5cc00775 | 13783 | expr_mode = expr_operator_none; |
252b5132 RH |
13784 | exp_seg = expression (exp); |
13785 | ||
c032bc4f JB |
13786 | /* For .insn immediates there may be a size specifier. */ |
13787 | if (dot_insn () && *input_line_pointer == '{' && input_line_pointer[1] == ':' | |
13788 | && (input_line_pointer[2] == 's' || input_line_pointer[2] == 'u')) | |
13789 | { | |
13790 | char *e; | |
13791 | unsigned long n = strtoul (input_line_pointer + 3, &e, 0); | |
13792 | ||
13793 | if (*e == '}' && n && n <= (flag_code == CODE_64BIT ? 64 : 32)) | |
13794 | { | |
13795 | i.imm_bits[this_operand] = n; | |
13796 | if (input_line_pointer[2] == 's') | |
13797 | i.flags[this_operand] |= Operand_Signed; | |
13798 | input_line_pointer = e + 1; | |
13799 | } | |
13800 | } | |
13801 | ||
83183c0c | 13802 | SKIP_WHITESPACE (); |
252b5132 | 13803 | if (*input_line_pointer) |
f3c180ae | 13804 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
13805 | |
13806 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 13807 | if (gotfree_input_line) |
ee86248c JB |
13808 | { |
13809 | free (gotfree_input_line); | |
13810 | ||
9aac24b1 | 13811 | if (exp->X_op == O_constant) |
ee86248c JB |
13812 | exp->X_op = O_illegal; |
13813 | } | |
13814 | ||
9aac24b1 JB |
13815 | if (exp_seg == reg_section) |
13816 | { | |
13817 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
13818 | return 0; | |
13819 | } | |
13820 | ||
ee86248c JB |
13821 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
13822 | } | |
252b5132 | 13823 | |
ee86248c JB |
13824 | static int |
13825 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
13826 | i386_operand_type types, const char *imm_start) | |
13827 | { | |
13828 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 13829 | { |
313c53d1 L |
13830 | if (imm_start) |
13831 | as_bad (_("missing or invalid immediate expression `%s'"), | |
13832 | imm_start); | |
3992d3b7 | 13833 | return 0; |
252b5132 | 13834 | } |
3e73aa7c | 13835 | else if (exp->X_op == O_constant) |
252b5132 | 13836 | { |
47926f60 | 13837 | /* Size it properly later. */ |
40fb9820 | 13838 | i.types[this_operand].bitfield.imm64 = 1; |
a442cac5 JB |
13839 | |
13840 | /* If not 64bit, sign/zero extend val, to account for wraparound | |
13841 | when !BFD64. */ | |
5cc00775 JB |
13842 | if (expr_mode == expr_operator_present |
13843 | && flag_code != CODE_64BIT && !object_64bit) | |
a442cac5 | 13844 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
252b5132 | 13845 | } |
4c63da97 | 13846 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 13847 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 13848 | && exp_seg != absolute_section |
47926f60 | 13849 | && exp_seg != text_section |
24eab124 AM |
13850 | && exp_seg != data_section |
13851 | && exp_seg != bss_section | |
13852 | && exp_seg != undefined_section | |
f86103b7 | 13853 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 13854 | { |
d0b47220 | 13855 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
13856 | return 0; |
13857 | } | |
13858 | #endif | |
13859 | else | |
13860 | { | |
13861 | /* This is an address. The size of the address will be | |
24eab124 | 13862 | determined later, depending on destination register, |
3e73aa7c | 13863 | suffix, or the default for the section. */ |
40fb9820 L |
13864 | i.types[this_operand].bitfield.imm8 = 1; |
13865 | i.types[this_operand].bitfield.imm16 = 1; | |
13866 | i.types[this_operand].bitfield.imm32 = 1; | |
13867 | i.types[this_operand].bitfield.imm32s = 1; | |
13868 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
13869 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
13870 | types); | |
252b5132 RH |
13871 | } |
13872 | ||
13873 | return 1; | |
13874 | } | |
13875 | ||
551c1ca1 | 13876 | static char * |
e3bb37b5 | 13877 | i386_scale (char *scale) |
252b5132 | 13878 | { |
551c1ca1 AM |
13879 | offsetT val; |
13880 | char *save = input_line_pointer; | |
252b5132 | 13881 | |
551c1ca1 AM |
13882 | input_line_pointer = scale; |
13883 | val = get_absolute_expression (); | |
13884 | ||
13885 | switch (val) | |
252b5132 | 13886 | { |
551c1ca1 | 13887 | case 1: |
252b5132 RH |
13888 | i.log2_scale_factor = 0; |
13889 | break; | |
551c1ca1 | 13890 | case 2: |
252b5132 RH |
13891 | i.log2_scale_factor = 1; |
13892 | break; | |
551c1ca1 | 13893 | case 4: |
252b5132 RH |
13894 | i.log2_scale_factor = 2; |
13895 | break; | |
551c1ca1 | 13896 | case 8: |
252b5132 RH |
13897 | i.log2_scale_factor = 3; |
13898 | break; | |
13899 | default: | |
a724f0f4 JB |
13900 | { |
13901 | char sep = *input_line_pointer; | |
13902 | ||
13903 | *input_line_pointer = '\0'; | |
13904 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
13905 | scale); | |
13906 | *input_line_pointer = sep; | |
13907 | input_line_pointer = save; | |
13908 | return NULL; | |
13909 | } | |
252b5132 | 13910 | } |
29b0f896 | 13911 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
13912 | { |
13913 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 13914 | 1 << i.log2_scale_factor); |
252b5132 | 13915 | i.log2_scale_factor = 0; |
252b5132 | 13916 | } |
551c1ca1 AM |
13917 | scale = input_line_pointer; |
13918 | input_line_pointer = save; | |
13919 | return scale; | |
252b5132 RH |
13920 | } |
13921 | ||
252b5132 | 13922 | static int |
e3bb37b5 | 13923 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 13924 | { |
29b0f896 | 13925 | expressionS *exp; |
252b5132 RH |
13926 | segT exp_seg = 0; |
13927 | char *save_input_line_pointer; | |
f3c180ae | 13928 | char *gotfree_input_line; |
40fb9820 L |
13929 | int override; |
13930 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 13931 | int ret; |
252b5132 | 13932 | |
31b2323c L |
13933 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
13934 | { | |
13935 | as_bad (_("at most %d displacement operands are allowed"), | |
13936 | MAX_MEMORY_OPERANDS); | |
13937 | return 0; | |
13938 | } | |
13939 | ||
0dfbf9d7 | 13940 | operand_type_set (&bigdisp, 0); |
6f2f06be | 13941 | if (i.jumpabsolute |
48bcea9f | 13942 | || i.types[this_operand].bitfield.baseindex |
d3b01414 JB |
13943 | || (current_templates.start->opcode_modifier.jump != JUMP |
13944 | && current_templates.start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 13945 | { |
48bcea9f | 13946 | i386_addressing_mode (); |
e05278af | 13947 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
13948 | if (flag_code == CODE_64BIT) |
13949 | { | |
a775efc8 | 13950 | bigdisp.bitfield.disp32 = 1; |
40fb9820 | 13951 | if (!override) |
a775efc8 | 13952 | bigdisp.bitfield.disp64 = 1; |
40fb9820 L |
13953 | } |
13954 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 13955 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
13956 | else |
13957 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
13958 | } |
13959 | else | |
13960 | { | |
376cd056 JB |
13961 | /* For PC-relative branches, the width of the displacement may be |
13962 | dependent upon data size, but is never dependent upon address size. | |
13963 | Also make sure to not unintentionally match against a non-PC-relative | |
13964 | branch template. */ | |
d3b01414 | 13965 | const insn_template *t = current_templates.start; |
5b7c81bd | 13966 | bool has_intel64 = false; |
376cd056 | 13967 | |
d3b01414 | 13968 | while (++t < current_templates.end) |
376cd056 JB |
13969 | { |
13970 | if (t->opcode_modifier.jump | |
d3b01414 | 13971 | != current_templates.start->opcode_modifier.jump) |
376cd056 | 13972 | break; |
4b5aaf5f | 13973 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
5b7c81bd | 13974 | has_intel64 = true; |
376cd056 | 13975 | } |
d3b01414 | 13976 | current_templates.end = t; |
376cd056 | 13977 | |
e05278af | 13978 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
13979 | if (flag_code == CODE_64BIT) |
13980 | { | |
376cd056 JB |
13981 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
13982 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
13983 | bigdisp.bitfield.disp16 = 1; |
13984 | else | |
a775efc8 | 13985 | bigdisp.bitfield.disp32 = 1; |
40fb9820 L |
13986 | } |
13987 | else | |
e05278af JB |
13988 | { |
13989 | if (!override) | |
13990 | override = (i.suffix == (flag_code != CODE_16BIT | |
13991 | ? WORD_MNEM_SUFFIX | |
13992 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
13993 | bigdisp.bitfield.disp32 = 1; |
13994 | if ((flag_code == CODE_16BIT) ^ override) | |
13995 | { | |
13996 | bigdisp.bitfield.disp32 = 0; | |
13997 | bigdisp.bitfield.disp16 = 1; | |
13998 | } | |
e05278af | 13999 | } |
e05278af | 14000 | } |
c6fb90c8 L |
14001 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
14002 | bigdisp); | |
252b5132 RH |
14003 | |
14004 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 14005 | i.op[this_operand].disps = exp; |
252b5132 RH |
14006 | i.disp_operands++; |
14007 | save_input_line_pointer = input_line_pointer; | |
14008 | input_line_pointer = disp_start; | |
14009 | END_STRING_AND_SAVE (disp_end); | |
14010 | ||
14011 | #ifndef GCC_ASM_O_HACK | |
14012 | #define GCC_ASM_O_HACK 0 | |
14013 | #endif | |
14014 | #if GCC_ASM_O_HACK | |
14015 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 14016 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 14017 | && displacement_string_end[-1] == '+') |
252b5132 RH |
14018 | { |
14019 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
14020 | constraint within gcc asm statements. |
14021 | For instance: | |
14022 | ||
14023 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
14024 | __asm__ __volatile__ ( \ | |
14025 | "movw %w2,%0\n\t" \ | |
14026 | "movw %w1,2+%0\n\t" \ | |
14027 | "rorl $16,%1\n\t" \ | |
14028 | "movb %b1,4+%0\n\t" \ | |
14029 | "movb %4,5+%0\n\t" \ | |
14030 | "movb $0,6+%0\n\t" \ | |
14031 | "movb %h1,7+%0\n\t" \ | |
14032 | "rorl $16,%1" \ | |
14033 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
14034 | ||
14035 | This works great except that the output assembler ends | |
14036 | up looking a bit weird if it turns out that there is | |
14037 | no offset. You end up producing code that looks like: | |
14038 | ||
14039 | #APP | |
14040 | movw $235,(%eax) | |
14041 | movw %dx,2+(%eax) | |
14042 | rorl $16,%edx | |
14043 | movb %dl,4+(%eax) | |
14044 | movb $137,5+(%eax) | |
14045 | movb $0,6+(%eax) | |
14046 | movb %dh,7+(%eax) | |
14047 | rorl $16,%edx | |
14048 | #NO_APP | |
14049 | ||
47926f60 | 14050 | So here we provide the missing zero. */ |
24eab124 AM |
14051 | |
14052 | *displacement_string_end = '0'; | |
252b5132 RH |
14053 | } |
14054 | #endif | |
d258b828 | 14055 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
14056 | if (gotfree_input_line) |
14057 | input_line_pointer = gotfree_input_line; | |
252b5132 | 14058 | |
5cc00775 | 14059 | expr_mode = expr_operator_none; |
24eab124 | 14060 | exp_seg = expression (exp); |
252b5132 | 14061 | |
636c26b0 AM |
14062 | SKIP_WHITESPACE (); |
14063 | if (*input_line_pointer) | |
14064 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
14065 | #if GCC_ASM_O_HACK | |
14066 | RESTORE_END_STRING (disp_end + 1); | |
14067 | #endif | |
636c26b0 | 14068 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 14069 | if (gotfree_input_line) |
ee86248c JB |
14070 | { |
14071 | free (gotfree_input_line); | |
14072 | ||
14073 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
14074 | exp->X_op = O_illegal; | |
14075 | } | |
14076 | ||
14077 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
14078 | ||
14079 | RESTORE_END_STRING (disp_end); | |
14080 | ||
14081 | return ret; | |
14082 | } | |
14083 | ||
14084 | static int | |
14085 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
14086 | i386_operand_type types, const char *disp_start) | |
14087 | { | |
ee86248c | 14088 | int ret = 1; |
636c26b0 | 14089 | |
24eab124 AM |
14090 | /* We do this to make sure that the section symbol is in |
14091 | the symbol table. We will ultimately change the relocation | |
47926f60 | 14092 | to be relative to the beginning of the section. */ |
1ae12ab7 | 14093 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
14094 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
14095 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 14096 | { |
636c26b0 | 14097 | if (exp->X_op != O_symbol) |
3992d3b7 | 14098 | goto inv_disp; |
636c26b0 | 14099 | |
e5cb08ac | 14100 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
14101 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
14102 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 14103 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
14104 | exp->X_op = O_subtract; |
14105 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 14106 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 14107 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
14108 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
14109 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 14110 | else |
29b0f896 | 14111 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 14112 | } |
252b5132 | 14113 | |
3992d3b7 AM |
14114 | else if (exp->X_op == O_absent |
14115 | || exp->X_op == O_illegal | |
ee86248c | 14116 | || exp->X_op == O_big) |
2daf4fd8 | 14117 | { |
3992d3b7 AM |
14118 | inv_disp: |
14119 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 14120 | disp_start); |
3992d3b7 | 14121 | ret = 0; |
2daf4fd8 AM |
14122 | } |
14123 | ||
a50187b2 JB |
14124 | else if (exp->X_op == O_constant) |
14125 | { | |
14126 | /* Sizing gets taken care of by optimize_disp(). | |
14127 | ||
14128 | If not 64bit, sign/zero extend val, to account for wraparound | |
14129 | when !BFD64. */ | |
5cc00775 JB |
14130 | if (expr_mode == expr_operator_present |
14131 | && flag_code != CODE_64BIT && !object_64bit) | |
a50187b2 JB |
14132 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
14133 | } | |
14134 | ||
4c63da97 | 14135 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
a50187b2 | 14136 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
3992d3b7 AM |
14137 | && exp_seg != absolute_section |
14138 | && exp_seg != text_section | |
14139 | && exp_seg != data_section | |
14140 | && exp_seg != bss_section | |
14141 | && exp_seg != undefined_section | |
14142 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 14143 | { |
d0b47220 | 14144 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 14145 | ret = 0; |
24eab124 | 14146 | } |
252b5132 | 14147 | #endif |
3956db08 | 14148 | |
d3b01414 | 14149 | else if (current_templates.start->opcode_modifier.jump == JUMP_BYTE) |
48bcea9f JB |
14150 | i.types[this_operand].bitfield.disp8 = 1; |
14151 | ||
40fb9820 | 14152 | /* Check if this is a displacement only operand. */ |
02b83698 JB |
14153 | if (!i.types[this_operand].bitfield.baseindex) |
14154 | i.types[this_operand] = | |
14155 | operand_type_or (operand_type_and_not (i.types[this_operand], anydisp), | |
14156 | operand_type_and (i.types[this_operand], types)); | |
3956db08 | 14157 | |
3992d3b7 | 14158 | return ret; |
252b5132 RH |
14159 | } |
14160 | ||
2abc2bec JB |
14161 | /* Return the active addressing mode, taking address override and |
14162 | registers forming the address into consideration. Update the | |
14163 | address override prefix if necessary. */ | |
47926f60 | 14164 | |
2abc2bec JB |
14165 | static enum flag_code |
14166 | i386_addressing_mode (void) | |
252b5132 | 14167 | { |
be05d201 L |
14168 | enum flag_code addr_mode; |
14169 | ||
14170 | if (i.prefix[ADDR_PREFIX]) | |
14171 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 | 14172 | else if (flag_code == CODE_16BIT |
d3b01414 | 14173 | && is_cpu (current_templates.start, CpuMPX) |
a23b33b3 JB |
14174 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic |
14175 | from md_assemble() by "is not a valid base/index expression" | |
14176 | when there is a base and/or index. */ | |
14177 | && !i.types[this_operand].bitfield.baseindex) | |
14178 | { | |
14179 | /* MPX insn memory operands with neither base nor index must be forced | |
14180 | to use 32-bit addressing in 16-bit mode. */ | |
14181 | addr_mode = CODE_32BIT; | |
14182 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
14183 | ++i.prefixes; | |
14184 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
14185 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
14186 | } | |
be05d201 L |
14187 | else |
14188 | { | |
14189 | addr_mode = flag_code; | |
14190 | ||
24eab124 | 14191 | #if INFER_ADDR_PREFIX |
be05d201 L |
14192 | if (i.mem_operands == 0) |
14193 | { | |
14194 | /* Infer address prefix from the first memory operand. */ | |
14195 | const reg_entry *addr_reg = i.base_reg; | |
14196 | ||
14197 | if (addr_reg == NULL) | |
14198 | addr_reg = i.index_reg; | |
eecb386c | 14199 | |
be05d201 L |
14200 | if (addr_reg) |
14201 | { | |
e968fc9b | 14202 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
14203 | addr_mode = CODE_32BIT; |
14204 | else if (flag_code != CODE_64BIT | |
dc821c5f | 14205 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
14206 | addr_mode = CODE_16BIT; |
14207 | ||
14208 | if (addr_mode != flag_code) | |
14209 | { | |
14210 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
14211 | i.prefixes += 1; | |
14212 | /* Change the size of any displacement too. At most one | |
14213 | of Disp16 or Disp32 is set. | |
14214 | FIXME. There doesn't seem to be any real need for | |
14215 | separate Disp16 and Disp32 flags. The same goes for | |
14216 | Imm16 and Imm32. Removing them would probably clean | |
14217 | up the code quite a lot. */ | |
14218 | if (flag_code != CODE_64BIT | |
14219 | && (i.types[this_operand].bitfield.disp16 | |
14220 | || i.types[this_operand].bitfield.disp32)) | |
05909f23 JB |
14221 | { |
14222 | static const i386_operand_type disp16_32 = { | |
14223 | .bitfield = { .disp16 = 1, .disp32 = 1 } | |
14224 | }; | |
14225 | ||
14226 | i.types[this_operand] | |
14227 | = operand_type_xor (i.types[this_operand], disp16_32); | |
14228 | } | |
be05d201 L |
14229 | } |
14230 | } | |
14231 | } | |
24eab124 | 14232 | #endif |
be05d201 L |
14233 | } |
14234 | ||
2abc2bec JB |
14235 | return addr_mode; |
14236 | } | |
14237 | ||
14238 | /* Make sure the memory operand we've been dealt is valid. | |
14239 | Return 1 on success, 0 on a failure. */ | |
14240 | ||
14241 | static int | |
14242 | i386_index_check (const char *operand_string) | |
14243 | { | |
14244 | const char *kind = "base/index"; | |
14245 | enum flag_code addr_mode = i386_addressing_mode (); | |
d3b01414 | 14246 | const insn_template *t = current_templates.end - 1; |
2abc2bec | 14247 | |
77a19f0e | 14248 | if (t->opcode_modifier.isstring) |
fc0763e6 JB |
14249 | { |
14250 | /* Memory operands of string insns are special in that they only allow | |
14251 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 | 14252 | const reg_entry *expected_reg; |
069a1561 | 14253 | static const char di_si[][2][4] = |
be05d201 L |
14254 | { |
14255 | { "esi", "edi" }, | |
14256 | { "si", "di" }, | |
14257 | { "rsi", "rdi" } | |
14258 | }; | |
069a1561 | 14259 | static const char bx[][4] = { "ebx", "bx", "rbx" }; |
fc0763e6 JB |
14260 | |
14261 | kind = "string address"; | |
14262 | ||
a152332d | 14263 | if (t->opcode_modifier.prefixok == PrefixRep) |
fc0763e6 | 14264 | { |
77a19f0e | 14265 | int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0; |
51c8edf6 | 14266 | int op = 0; |
fc0763e6 | 14267 | |
77a19f0e | 14268 | if (!t->operand_types[0].bitfield.baseindex |
fc0763e6 | 14269 | || ((!i.mem_operands != !intel_syntax) |
77a19f0e | 14270 | && t->operand_types[1].bitfield.baseindex)) |
51c8edf6 | 14271 | op = 1; |
fe0e921f AM |
14272 | expected_reg |
14273 | = (const reg_entry *) str_hash_find (reg_hash, | |
14274 | di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
14275 | } |
14276 | else | |
fe0e921f AM |
14277 | expected_reg |
14278 | = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); | |
fc0763e6 | 14279 | |
be05d201 L |
14280 | if (i.base_reg != expected_reg |
14281 | || i.index_reg | |
fc0763e6 | 14282 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 14283 | { |
be05d201 L |
14284 | /* The second memory operand must have the same size as |
14285 | the first one. */ | |
14286 | if (i.mem_operands | |
14287 | && i.base_reg | |
14288 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 14289 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 14290 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
14291 | ? i.base_reg->reg_type.bitfield.dword |
14292 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
14293 | goto bad_address; |
14294 | ||
fc0763e6 JB |
14295 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
14296 | operand_string, | |
14297 | intel_syntax ? '[' : '(', | |
14298 | register_prefix, | |
be05d201 | 14299 | expected_reg->reg_name, |
fc0763e6 | 14300 | intel_syntax ? ']' : ')'); |
be05d201 | 14301 | return 1; |
fc0763e6 | 14302 | } |
be05d201 L |
14303 | else |
14304 | return 1; | |
14305 | ||
dc1e8a47 | 14306 | bad_address: |
be05d201 L |
14307 | as_bad (_("`%s' is not a valid %s expression"), |
14308 | operand_string, kind); | |
14309 | return 0; | |
3e73aa7c JH |
14310 | } |
14311 | else | |
14312 | { | |
d3b01414 | 14313 | t = current_templates.start; |
77a19f0e | 14314 | |
be05d201 L |
14315 | if (addr_mode != CODE_16BIT) |
14316 | { | |
14317 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
14318 | if (i.disp_encoding == disp_encoding_16bit) |
14319 | { | |
14320 | bad_disp: | |
14321 | as_bad (_("invalid `%s' prefix"), | |
14322 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
14323 | return 0; | |
14324 | } | |
14325 | ||
be05d201 | 14326 | if ((i.base_reg |
e968fc9b JB |
14327 | && ((addr_mode == CODE_64BIT |
14328 | ? !i.base_reg->reg_type.bitfield.qword | |
14329 | : !i.base_reg->reg_type.bitfield.dword) | |
14330 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
14331 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 14332 | || (i.index_reg |
1b54b8d7 JB |
14333 | && !i.index_reg->reg_type.bitfield.xmmword |
14334 | && !i.index_reg->reg_type.bitfield.ymmword | |
14335 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 14336 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
14337 | ? !i.index_reg->reg_type.bitfield.qword |
14338 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
14339 | || !i.index_reg->reg_type.bitfield.baseindex))) |
14340 | goto bad_address; | |
8178be5b | 14341 | |
260cd341 | 14342 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
7fc69528 JB |
14343 | if (t->mnem_off == MN_bndmk |
14344 | || t->mnem_off == MN_bndldx | |
14345 | || t->mnem_off == MN_bndstx | |
a152332d | 14346 | || t->opcode_modifier.sib == SIBMEM) |
8178be5b JB |
14347 | { |
14348 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 14349 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
14350 | { |
14351 | as_bad (_("`%s' cannot be used here"), operand_string); | |
14352 | return 0; | |
14353 | } | |
14354 | ||
14355 | /* bndldx and bndstx ignore their scale factor. */ | |
7fc69528 | 14356 | if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx) |
8178be5b JB |
14357 | && i.log2_scale_factor) |
14358 | as_warn (_("register scaling is being ignored here")); | |
14359 | } | |
be05d201 L |
14360 | } |
14361 | else | |
3e73aa7c | 14362 | { |
be05d201 | 14363 | /* 16-bit checks. */ |
41eb8e88 L |
14364 | if (i.disp_encoding == disp_encoding_32bit) |
14365 | goto bad_disp; | |
14366 | ||
3e73aa7c | 14367 | if ((i.base_reg |
dc821c5f | 14368 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 14369 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 14370 | || (i.index_reg |
dc821c5f | 14371 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 14372 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
14373 | || !(i.base_reg |
14374 | && i.base_reg->reg_num < 6 | |
14375 | && i.index_reg->reg_num >= 6 | |
14376 | && i.log2_scale_factor == 0)))) | |
be05d201 | 14377 | goto bad_address; |
3e73aa7c JH |
14378 | } |
14379 | } | |
be05d201 | 14380 | return 1; |
24eab124 | 14381 | } |
252b5132 | 14382 | |
43234a1e L |
14383 | /* Handle vector immediates. */ |
14384 | ||
14385 | static int | |
14386 | RC_SAE_immediate (const char *imm_start) | |
14387 | { | |
43234a1e | 14388 | const char *pstr = imm_start; |
43234a1e L |
14389 | |
14390 | if (*pstr != '{') | |
14391 | return 0; | |
14392 | ||
7063667e JB |
14393 | pstr = RC_SAE_specifier (pstr + 1); |
14394 | if (pstr == NULL) | |
43234a1e L |
14395 | return 0; |
14396 | ||
14397 | if (*pstr++ != '}') | |
14398 | { | |
14399 | as_bad (_("Missing '}': '%s'"), imm_start); | |
14400 | return 0; | |
14401 | } | |
14402 | /* RC/SAE immediate string should contain nothing more. */; | |
14403 | if (*pstr != 0) | |
14404 | { | |
14405 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
14406 | return 0; | |
14407 | } | |
14408 | ||
cf665fee JB |
14409 | /* Internally this doesn't count as an operand. */ |
14410 | --i.operands; | |
43234a1e | 14411 | |
43234a1e L |
14412 | return 1; |
14413 | } | |
14414 | ||
9d299bea JB |
14415 | static INLINE bool starts_memory_operand (char c) |
14416 | { | |
014fbcda | 14417 | return ISDIGIT (c) |
4795cd4a | 14418 | || is_name_beginner (c) |
014fbcda | 14419 | || strchr ("([\"+-!~", c); |
9d299bea JB |
14420 | } |
14421 | ||
fc0763e6 | 14422 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 14423 | on error. */ |
252b5132 | 14424 | |
252b5132 | 14425 | static int |
a7619375 | 14426 | i386_att_operand (char *operand_string) |
252b5132 | 14427 | { |
af6bdddf AM |
14428 | const reg_entry *r; |
14429 | char *end_op; | |
24eab124 | 14430 | char *op_string = operand_string; |
252b5132 | 14431 | |
24eab124 | 14432 | if (is_space_char (*op_string)) |
252b5132 RH |
14433 | ++op_string; |
14434 | ||
24eab124 | 14435 | /* We check for an absolute prefix (differentiating, |
47926f60 | 14436 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
ccb05c9c | 14437 | if (*op_string == ABSOLUTE_PREFIX |
d3b01414 | 14438 | && current_templates.start->opcode_modifier.jump) |
24eab124 AM |
14439 | { |
14440 | ++op_string; | |
14441 | if (is_space_char (*op_string)) | |
14442 | ++op_string; | |
5b7c81bd | 14443 | i.jumpabsolute = true; |
24eab124 | 14444 | } |
252b5132 | 14445 | |
47926f60 | 14446 | /* Check if operand is a register. */ |
4d1bb795 | 14447 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 14448 | { |
40fb9820 L |
14449 | i386_operand_type temp; |
14450 | ||
8a6fb3f9 JB |
14451 | if (r == &bad_reg) |
14452 | return 0; | |
14453 | ||
24eab124 AM |
14454 | /* Check for a segment override by searching for ':' after a |
14455 | segment register. */ | |
14456 | op_string = end_op; | |
14457 | if (is_space_char (*op_string)) | |
14458 | ++op_string; | |
00cee14f | 14459 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 | 14460 | { |
5e042380 | 14461 | i.seg[i.mem_operands] = r; |
252b5132 | 14462 | |
24eab124 | 14463 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
14464 | ++op_string; |
14465 | if (is_space_char (*op_string)) | |
24eab124 | 14466 | ++op_string; |
252b5132 | 14467 | |
47926f60 | 14468 | /* Handle case of %es:*foo. */ |
ccb05c9c | 14469 | if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX |
d3b01414 | 14470 | && current_templates.start->opcode_modifier.jump) |
24eab124 AM |
14471 | { |
14472 | ++op_string; | |
14473 | if (is_space_char (*op_string)) | |
14474 | ++op_string; | |
5b7c81bd | 14475 | i.jumpabsolute = true; |
24eab124 | 14476 | } |
c8d541e2 | 14477 | |
9d299bea | 14478 | if (!starts_memory_operand (*op_string)) |
c8d541e2 JB |
14479 | { |
14480 | as_bad (_("bad memory operand `%s'"), op_string); | |
14481 | return 0; | |
14482 | } | |
24eab124 AM |
14483 | goto do_memory_reference; |
14484 | } | |
43234a1e L |
14485 | |
14486 | /* Handle vector operations. */ | |
14487 | if (*op_string == '{') | |
14488 | { | |
f70c6814 | 14489 | op_string = check_VecOperations (op_string); |
43234a1e L |
14490 | if (op_string == NULL) |
14491 | return 0; | |
14492 | } | |
14493 | ||
24eab124 AM |
14494 | if (*op_string) |
14495 | { | |
d0b47220 | 14496 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
14497 | return 0; |
14498 | } | |
0ff3b7d0 JB |
14499 | |
14500 | /* Reject pseudo registers for .insn. */ | |
14501 | if (dot_insn () && r->reg_type.bitfield.class == ClassNone) | |
14502 | { | |
14503 | as_bad (_("`%s%s' cannot be used here"), | |
14504 | register_prefix, r->reg_name); | |
14505 | return 0; | |
14506 | } | |
14507 | ||
40fb9820 L |
14508 | temp = r->reg_type; |
14509 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
14510 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
14511 | temp); | |
7d5e4556 | 14512 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 14513 | i.op[this_operand].regs = r; |
24eab124 | 14514 | i.reg_operands++; |
cf665fee JB |
14515 | |
14516 | /* A GPR may follow an RC or SAE immediate only if a (vector) register | |
14517 | operand was also present earlier on. */ | |
14518 | if (i.rounding.type != rc_none && temp.bitfield.class == Reg | |
14519 | && i.reg_operands == 1) | |
14520 | { | |
14521 | unsigned int j; | |
14522 | ||
14523 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j) | |
14524 | if (i.rounding.type == RC_NamesTable[j].type) | |
14525 | break; | |
14526 | as_bad (_("`%s': misplaced `{%s}'"), | |
d3b01414 | 14527 | insn_name (current_templates.start), RC_NamesTable[j].name); |
cf665fee JB |
14528 | return 0; |
14529 | } | |
24eab124 | 14530 | } |
af6bdddf AM |
14531 | else if (*op_string == REGISTER_PREFIX) |
14532 | { | |
14533 | as_bad (_("bad register name `%s'"), op_string); | |
14534 | return 0; | |
14535 | } | |
24eab124 | 14536 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 14537 | { |
24eab124 | 14538 | ++op_string; |
6f2f06be | 14539 | if (i.jumpabsolute) |
24eab124 | 14540 | { |
d0b47220 | 14541 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
14542 | return 0; |
14543 | } | |
14544 | if (!i386_immediate (op_string)) | |
14545 | return 0; | |
cf665fee JB |
14546 | if (i.rounding.type != rc_none) |
14547 | { | |
14548 | as_bad (_("`%s': RC/SAE operand must follow immediate operands"), | |
d3b01414 | 14549 | insn_name (current_templates.start)); |
cf665fee JB |
14550 | return 0; |
14551 | } | |
24eab124 | 14552 | } |
43234a1e L |
14553 | else if (RC_SAE_immediate (operand_string)) |
14554 | { | |
cf665fee JB |
14555 | /* If it is a RC or SAE immediate, do the necessary placement check: |
14556 | Only another immediate or a GPR may precede it. */ | |
14557 | if (i.mem_operands || i.reg_operands + i.imm_operands > 1 | |
14558 | || (i.reg_operands == 1 | |
14559 | && i.op[0].regs->reg_type.bitfield.class != Reg)) | |
14560 | { | |
14561 | as_bad (_("`%s': misplaced `%s'"), | |
d3b01414 | 14562 | insn_name (current_templates.start), operand_string); |
cf665fee JB |
14563 | return 0; |
14564 | } | |
43234a1e | 14565 | } |
9d299bea | 14566 | else if (starts_memory_operand (*op_string)) |
24eab124 | 14567 | { |
47926f60 | 14568 | /* This is a memory reference of some sort. */ |
af6bdddf | 14569 | char *base_string; |
252b5132 | 14570 | |
47926f60 | 14571 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
14572 | char *displacement_string_start; |
14573 | char *displacement_string_end; | |
252b5132 | 14574 | |
24eab124 | 14575 | do_memory_reference: |
24eab124 AM |
14576 | /* Check for base index form. We detect the base index form by |
14577 | looking for an ')' at the end of the operand, searching | |
14578 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
14579 | after the '('. */ | |
af6bdddf | 14580 | base_string = op_string + strlen (op_string); |
c3332e24 | 14581 | |
43234a1e | 14582 | /* Handle vector operations. */ |
6b5ba0d4 JB |
14583 | --base_string; |
14584 | if (is_space_char (*base_string)) | |
14585 | --base_string; | |
14586 | ||
14587 | if (*base_string == '}') | |
43234a1e | 14588 | { |
6b5ba0d4 JB |
14589 | char *vop_start = NULL; |
14590 | ||
14591 | while (base_string-- > op_string) | |
14592 | { | |
14593 | if (*base_string == '"') | |
14594 | break; | |
14595 | if (*base_string != '{') | |
14596 | continue; | |
14597 | ||
14598 | vop_start = base_string; | |
14599 | ||
14600 | --base_string; | |
14601 | if (is_space_char (*base_string)) | |
14602 | --base_string; | |
14603 | ||
14604 | if (*base_string != '}') | |
14605 | break; | |
14606 | ||
14607 | vop_start = NULL; | |
14608 | } | |
14609 | ||
14610 | if (!vop_start) | |
14611 | { | |
14612 | as_bad (_("unbalanced figure braces")); | |
14613 | return 0; | |
14614 | } | |
14615 | ||
f70c6814 | 14616 | if (check_VecOperations (vop_start) == NULL) |
43234a1e | 14617 | return 0; |
43234a1e L |
14618 | } |
14619 | ||
47926f60 | 14620 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
14621 | displacement_string_start = op_string; |
14622 | displacement_string_end = base_string + 1; | |
252b5132 | 14623 | |
24eab124 AM |
14624 | if (*base_string == ')') |
14625 | { | |
af6bdddf | 14626 | char *temp_string; |
e87fb6a6 JB |
14627 | unsigned int parens_not_balanced = 0; |
14628 | bool in_quotes = false; | |
e68c3d59 | 14629 | |
24eab124 | 14630 | /* We've already checked that the number of left & right ()'s are |
e87fb6a6 JB |
14631 | equal, and that there's a matching set of double quotes. */ |
14632 | end_op = base_string; | |
14633 | for (temp_string = op_string; temp_string < end_op; temp_string++) | |
24eab124 | 14634 | { |
e87fb6a6 JB |
14635 | if (*temp_string == '\\' && temp_string[1] == '"') |
14636 | ++temp_string; | |
14637 | else if (*temp_string == '"') | |
14638 | in_quotes = !in_quotes; | |
14639 | else if (!in_quotes) | |
14640 | { | |
14641 | if (*temp_string == '(' && !parens_not_balanced++) | |
14642 | base_string = temp_string; | |
14643 | if (*temp_string == ')') | |
14644 | --parens_not_balanced; | |
14645 | } | |
24eab124 | 14646 | } |
c3332e24 | 14647 | |
af6bdddf | 14648 | temp_string = base_string; |
c3332e24 | 14649 | |
24eab124 | 14650 | /* Skip past '(' and whitespace. */ |
4f081312 | 14651 | gas_assert (*base_string == '('); |
e87fb6a6 | 14652 | ++base_string; |
252b5132 | 14653 | if (is_space_char (*base_string)) |
24eab124 | 14654 | ++base_string; |
252b5132 | 14655 | |
af6bdddf | 14656 | if (*base_string == ',' |
4eed87de AM |
14657 | || ((i.base_reg = parse_register (base_string, &end_op)) |
14658 | != NULL)) | |
252b5132 | 14659 | { |
af6bdddf | 14660 | displacement_string_end = temp_string; |
252b5132 | 14661 | |
40fb9820 | 14662 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 14663 | |
af6bdddf | 14664 | if (i.base_reg) |
24eab124 | 14665 | { |
8a6fb3f9 JB |
14666 | if (i.base_reg == &bad_reg) |
14667 | return 0; | |
24eab124 AM |
14668 | base_string = end_op; |
14669 | if (is_space_char (*base_string)) | |
14670 | ++base_string; | |
af6bdddf AM |
14671 | } |
14672 | ||
14673 | /* There may be an index reg or scale factor here. */ | |
14674 | if (*base_string == ',') | |
14675 | { | |
14676 | ++base_string; | |
14677 | if (is_space_char (*base_string)) | |
14678 | ++base_string; | |
14679 | ||
4eed87de AM |
14680 | if ((i.index_reg = parse_register (base_string, &end_op)) |
14681 | != NULL) | |
24eab124 | 14682 | { |
8a6fb3f9 JB |
14683 | if (i.index_reg == &bad_reg) |
14684 | return 0; | |
af6bdddf | 14685 | base_string = end_op; |
24eab124 AM |
14686 | if (is_space_char (*base_string)) |
14687 | ++base_string; | |
af6bdddf AM |
14688 | if (*base_string == ',') |
14689 | { | |
14690 | ++base_string; | |
14691 | if (is_space_char (*base_string)) | |
14692 | ++base_string; | |
14693 | } | |
e5cb08ac | 14694 | else if (*base_string != ')') |
af6bdddf | 14695 | { |
4eed87de AM |
14696 | as_bad (_("expecting `,' or `)' " |
14697 | "after index register in `%s'"), | |
af6bdddf AM |
14698 | operand_string); |
14699 | return 0; | |
14700 | } | |
24eab124 | 14701 | } |
af6bdddf | 14702 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 14703 | { |
f76bf5e0 L |
14704 | end_op = strchr (base_string, ','); |
14705 | if (end_op) | |
14706 | *end_op = '\0'; | |
af6bdddf | 14707 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
14708 | return 0; |
14709 | } | |
252b5132 | 14710 | |
47926f60 | 14711 | /* Check for scale factor. */ |
551c1ca1 | 14712 | if (*base_string != ')') |
af6bdddf | 14713 | { |
551c1ca1 AM |
14714 | char *end_scale = i386_scale (base_string); |
14715 | ||
14716 | if (!end_scale) | |
af6bdddf | 14717 | return 0; |
24eab124 | 14718 | |
551c1ca1 | 14719 | base_string = end_scale; |
af6bdddf AM |
14720 | if (is_space_char (*base_string)) |
14721 | ++base_string; | |
14722 | if (*base_string != ')') | |
14723 | { | |
4eed87de AM |
14724 | as_bad (_("expecting `)' " |
14725 | "after scale factor in `%s'"), | |
af6bdddf AM |
14726 | operand_string); |
14727 | return 0; | |
14728 | } | |
14729 | } | |
14730 | else if (!i.index_reg) | |
24eab124 | 14731 | { |
4eed87de AM |
14732 | as_bad (_("expecting index register or scale factor " |
14733 | "after `,'; got '%c'"), | |
af6bdddf | 14734 | *base_string); |
24eab124 AM |
14735 | return 0; |
14736 | } | |
14737 | } | |
af6bdddf | 14738 | else if (*base_string != ')') |
24eab124 | 14739 | { |
4eed87de AM |
14740 | as_bad (_("expecting `,' or `)' " |
14741 | "after base register in `%s'"), | |
af6bdddf | 14742 | operand_string); |
24eab124 AM |
14743 | return 0; |
14744 | } | |
c3332e24 | 14745 | } |
af6bdddf | 14746 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 14747 | { |
f76bf5e0 L |
14748 | end_op = strchr (base_string, ','); |
14749 | if (end_op) | |
14750 | *end_op = '\0'; | |
af6bdddf | 14751 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 14752 | return 0; |
c3332e24 | 14753 | } |
24eab124 AM |
14754 | } |
14755 | ||
14756 | /* If there's an expression beginning the operand, parse it, | |
14757 | assuming displacement_string_start and | |
14758 | displacement_string_end are meaningful. */ | |
14759 | if (displacement_string_start != displacement_string_end) | |
14760 | { | |
14761 | if (!i386_displacement (displacement_string_start, | |
14762 | displacement_string_end)) | |
14763 | return 0; | |
14764 | } | |
14765 | ||
14766 | /* Special case for (%dx) while doing input/output op. */ | |
14767 | if (i.base_reg | |
75e5731b JB |
14768 | && i.base_reg->reg_type.bitfield.instance == RegD |
14769 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
14770 | && i.index_reg == 0 |
14771 | && i.log2_scale_factor == 0 | |
14772 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 14773 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 14774 | { |
2fb5be8d | 14775 | i.types[this_operand] = i.base_reg->reg_type; |
f0a4cb15 CL |
14776 | i.op[this_operand].regs = i.base_reg; |
14777 | i.base_reg = NULL; | |
9373f275 | 14778 | i.input_output_operand = true; |
24eab124 AM |
14779 | return 1; |
14780 | } | |
14781 | ||
eecb386c AM |
14782 | if (i386_index_check (operand_string) == 0) |
14783 | return 0; | |
c48dadc9 | 14784 | i.flags[this_operand] |= Operand_Mem; |
24eab124 AM |
14785 | i.mem_operands++; |
14786 | } | |
14787 | else | |
ce8a8b2f AM |
14788 | { |
14789 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
14790 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
14791 | output_invalid (*op_string), | |
14792 | this_operand + 1, | |
14793 | op_string); | |
14794 | return 0; | |
14795 | } | |
47926f60 | 14796 | return 1; /* Normal return. */ |
252b5132 RH |
14797 | } |
14798 | \f | |
fa94de6b RM |
14799 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
14800 | that an rs_machine_dependent frag may reach. */ | |
14801 | ||
14802 | unsigned int | |
14803 | i386_frag_max_var (fragS *frag) | |
14804 | { | |
14805 | /* The only relaxable frags are for jumps. | |
14806 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
14807 | gas_assert (frag->fr_type == rs_machine_dependent); | |
14808 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
14809 | } | |
14810 | ||
b084df0b L |
14811 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14812 | static int | |
8dcea932 | 14813 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
14814 | { |
14815 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
14816 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
14817 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
14818 | return 0; | |
14819 | ||
14820 | if (!S_IS_EXTERNAL (fr_symbol)) | |
14821 | /* Symbol may be weak or local. */ | |
14822 | return !S_IS_WEAK (fr_symbol); | |
14823 | ||
8dcea932 L |
14824 | /* Global symbols with non-default visibility can't be preempted. */ |
14825 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
14826 | return 1; | |
14827 | ||
14828 | if (fr_var != NO_RELOC) | |
14829 | switch ((enum bfd_reloc_code_real) fr_var) | |
14830 | { | |
14831 | case BFD_RELOC_386_PLT32: | |
14832 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 14833 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
14834 | return 0; |
14835 | default: | |
14836 | abort (); | |
14837 | } | |
14838 | ||
b084df0b L |
14839 | /* Global symbols with default visibility in a shared library may be |
14840 | preempted by another definition. */ | |
8dcea932 | 14841 | return !shared; |
b084df0b L |
14842 | } |
14843 | #endif | |
14844 | ||
79d72f45 HL |
14845 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
14846 | Note also work for Skylake and Cascadelake. | |
14847 | --------------------------------------------------------------------- | |
14848 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
14849 | | ------ | ----------- | ------- | -------- | | |
14850 | | Jo | N | N | Y | | |
14851 | | Jno | N | N | Y | | |
14852 | | Jc/Jb | Y | N | Y | | |
14853 | | Jae/Jnb | Y | N | Y | | |
14854 | | Je/Jz | Y | Y | Y | | |
14855 | | Jne/Jnz | Y | Y | Y | | |
14856 | | Jna/Jbe | Y | N | Y | | |
14857 | | Ja/Jnbe | Y | N | Y | | |
14858 | | Js | N | N | Y | | |
14859 | | Jns | N | N | Y | | |
14860 | | Jp/Jpe | N | N | Y | | |
14861 | | Jnp/Jpo | N | N | Y | | |
14862 | | Jl/Jnge | Y | Y | Y | | |
14863 | | Jge/Jnl | Y | Y | Y | | |
14864 | | Jle/Jng | Y | Y | Y | | |
14865 | | Jg/Jnle | Y | Y | Y | | |
14866 | --------------------------------------------------------------------- */ | |
14867 | static int | |
14868 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
14869 | { | |
14870 | if (mf_cmp == mf_cmp_alu_cmp) | |
14871 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
14872 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
14873 | if (mf_cmp == mf_cmp_incdec) | |
14874 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
14875 | || mf_jcc == mf_jcc_jle); | |
14876 | if (mf_cmp == mf_cmp_test_and) | |
14877 | return 1; | |
14878 | return 0; | |
14879 | } | |
14880 | ||
e379e5f3 L |
14881 | /* Return the next non-empty frag. */ |
14882 | ||
14883 | static fragS * | |
14884 | i386_next_non_empty_frag (fragS *fragP) | |
14885 | { | |
14886 | /* There may be a frag with a ".fill 0" when there is no room in | |
14887 | the current frag for frag_grow in output_insn. */ | |
14888 | for (fragP = fragP->fr_next; | |
14889 | (fragP != NULL | |
14890 | && fragP->fr_type == rs_fill | |
14891 | && fragP->fr_fix == 0); | |
14892 | fragP = fragP->fr_next) | |
14893 | ; | |
14894 | return fragP; | |
14895 | } | |
14896 | ||
14897 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
14898 | ||
14899 | static fragS * | |
79d72f45 | 14900 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 14901 | { |
79d72f45 HL |
14902 | fragS *branch_fragP; |
14903 | if (!pad_fragP) | |
e379e5f3 L |
14904 | return NULL; |
14905 | ||
79d72f45 HL |
14906 | if (pad_fragP->fr_type == rs_machine_dependent |
14907 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
14908 | == BRANCH_PADDING)) |
14909 | { | |
79d72f45 HL |
14910 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
14911 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 14912 | return NULL; |
79d72f45 HL |
14913 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
14914 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
14915 | pad_fragP->tc_frag_data.mf_type)) | |
14916 | return branch_fragP; | |
e379e5f3 L |
14917 | } |
14918 | ||
14919 | return NULL; | |
14920 | } | |
14921 | ||
14922 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
14923 | ||
14924 | static void | |
14925 | i386_classify_machine_dependent_frag (fragS *fragP) | |
14926 | { | |
14927 | fragS *cmp_fragP; | |
14928 | fragS *pad_fragP; | |
14929 | fragS *branch_fragP; | |
14930 | fragS *next_fragP; | |
14931 | unsigned int max_prefix_length; | |
14932 | ||
14933 | if (fragP->tc_frag_data.classified) | |
14934 | return; | |
14935 | ||
14936 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
14937 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
14938 | for (next_fragP = fragP; | |
14939 | next_fragP != NULL; | |
14940 | next_fragP = next_fragP->fr_next) | |
14941 | { | |
14942 | next_fragP->tc_frag_data.classified = 1; | |
14943 | if (next_fragP->fr_type == rs_machine_dependent) | |
14944 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
14945 | { | |
14946 | case BRANCH_PADDING: | |
14947 | /* The BRANCH_PADDING frag must be followed by a branch | |
14948 | frag. */ | |
14949 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
14950 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
14951 | break; | |
14952 | case FUSED_JCC_PADDING: | |
14953 | /* Check if this is a fused jcc: | |
14954 | FUSED_JCC_PADDING | |
14955 | CMP like instruction | |
14956 | BRANCH_PADDING | |
14957 | COND_JUMP | |
14958 | */ | |
14959 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
14960 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 14961 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
14962 | if (branch_fragP) |
14963 | { | |
14964 | /* The BRANCH_PADDING frag is merged with the | |
14965 | FUSED_JCC_PADDING frag. */ | |
14966 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
14967 | /* CMP like instruction size. */ | |
14968 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
14969 | frag_wane (pad_fragP); | |
14970 | /* Skip to branch_fragP. */ | |
14971 | next_fragP = branch_fragP; | |
14972 | } | |
14973 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
14974 | { | |
14975 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
14976 | a fused jcc. */ | |
14977 | next_fragP->fr_subtype | |
14978 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
14979 | next_fragP->tc_frag_data.max_bytes | |
14980 | = next_fragP->tc_frag_data.max_prefix_length; | |
14981 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
14982 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
14983 | } | |
14984 | else | |
14985 | frag_wane (next_fragP); | |
14986 | break; | |
14987 | } | |
14988 | } | |
14989 | ||
14990 | /* Stop if there is no BRANCH_PREFIX. */ | |
14991 | if (!align_branch_prefix_size) | |
14992 | return; | |
14993 | ||
14994 | /* Scan for BRANCH_PREFIX. */ | |
14995 | for (; fragP != NULL; fragP = fragP->fr_next) | |
14996 | { | |
14997 | if (fragP->fr_type != rs_machine_dependent | |
14998 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
14999 | != BRANCH_PREFIX)) | |
15000 | continue; | |
15001 | ||
15002 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
15003 | COND_JUMP_PREFIX. */ | |
15004 | max_prefix_length = 0; | |
15005 | for (next_fragP = fragP; | |
15006 | next_fragP != NULL; | |
15007 | next_fragP = next_fragP->fr_next) | |
15008 | { | |
15009 | if (next_fragP->fr_type == rs_fill) | |
15010 | /* Skip rs_fill frags. */ | |
15011 | continue; | |
15012 | else if (next_fragP->fr_type != rs_machine_dependent) | |
15013 | /* Stop for all other frags. */ | |
15014 | break; | |
15015 | ||
15016 | /* rs_machine_dependent frags. */ | |
15017 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15018 | == BRANCH_PREFIX) | |
15019 | { | |
15020 | /* Count BRANCH_PREFIX frags. */ | |
15021 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
15022 | { | |
15023 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
15024 | frag_wane (next_fragP); | |
15025 | } | |
15026 | else | |
15027 | max_prefix_length | |
15028 | += next_fragP->tc_frag_data.max_bytes; | |
15029 | } | |
15030 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15031 | == BRANCH_PADDING) | |
15032 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15033 | == FUSED_JCC_PADDING)) | |
15034 | { | |
15035 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
15036 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
15037 | break; | |
15038 | } | |
15039 | else | |
15040 | /* Stop for other rs_machine_dependent frags. */ | |
15041 | break; | |
15042 | } | |
15043 | ||
15044 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
15045 | ||
15046 | /* Skip to the next frag. */ | |
15047 | fragP = next_fragP; | |
15048 | } | |
15049 | } | |
15050 | ||
15051 | /* Compute padding size for | |
15052 | ||
15053 | FUSED_JCC_PADDING | |
15054 | CMP like instruction | |
15055 | BRANCH_PADDING | |
15056 | COND_JUMP/UNCOND_JUMP | |
15057 | ||
15058 | or | |
15059 | ||
15060 | BRANCH_PADDING | |
15061 | COND_JUMP/UNCOND_JUMP | |
15062 | */ | |
15063 | ||
15064 | static int | |
15065 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
15066 | { | |
15067 | unsigned int offset, size, padding_size; | |
15068 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
15069 | ||
15070 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
15071 | if (!address) | |
15072 | address = fragP->fr_address; | |
15073 | address += fragP->fr_fix; | |
15074 | ||
15075 | /* CMP like instrunction size. */ | |
15076 | size = fragP->tc_frag_data.cmp_size; | |
15077 | ||
15078 | /* The base size of the branch frag. */ | |
15079 | size += branch_fragP->fr_fix; | |
15080 | ||
15081 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
15082 | branch frag. */ | |
15083 | if (branch_fragP->fr_type == rs_machine_dependent) | |
15084 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
15085 | ||
15086 | /* Check if branch is within boundary and doesn't end at the last | |
15087 | byte. */ | |
15088 | offset = address & ((1U << align_branch_power) - 1); | |
15089 | if ((offset + size) >= (1U << align_branch_power)) | |
15090 | /* Padding needed to avoid crossing boundary. */ | |
15091 | padding_size = (1U << align_branch_power) - offset; | |
15092 | else | |
15093 | /* No padding needed. */ | |
15094 | padding_size = 0; | |
15095 | ||
15096 | /* The return value may be saved in tc_frag_data.length which is | |
15097 | unsigned byte. */ | |
15098 | if (!fits_in_unsigned_byte (padding_size)) | |
15099 | abort (); | |
15100 | ||
15101 | return padding_size; | |
15102 | } | |
15103 | ||
15104 | /* i386_generic_table_relax_frag() | |
15105 | ||
15106 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
15107 | grow/shrink padding to align branch frags. Hand others to | |
15108 | relax_frag(). */ | |
15109 | ||
15110 | long | |
15111 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
15112 | { | |
15113 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
15114 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
15115 | { | |
15116 | long padding_size = i386_branch_padding_size (fragP, 0); | |
15117 | long grow = padding_size - fragP->tc_frag_data.length; | |
15118 | ||
15119 | /* When the BRANCH_PREFIX frag is used, the computed address | |
15120 | must match the actual address and there should be no padding. */ | |
15121 | if (fragP->tc_frag_data.padding_address | |
15122 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
15123 | || padding_size)) | |
15124 | abort (); | |
15125 | ||
15126 | /* Update the padding size. */ | |
15127 | if (grow) | |
15128 | fragP->tc_frag_data.length = padding_size; | |
15129 | ||
15130 | return grow; | |
15131 | } | |
15132 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
15133 | { | |
15134 | fragS *padding_fragP, *next_fragP; | |
15135 | long padding_size, left_size, last_size; | |
15136 | ||
15137 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
15138 | if (!padding_fragP) | |
15139 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
15140 | return (fragP->tc_frag_data.length | |
15141 | - fragP->tc_frag_data.last_length); | |
15142 | ||
15143 | /* Compute the relative address of the padding frag in the very | |
15144 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
15145 | if (!fragP->tc_frag_data.padding_address) | |
15146 | fragP->tc_frag_data.padding_address | |
15147 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
15148 | ||
15149 | /* First update the last length from the previous interation. */ | |
15150 | left_size = fragP->tc_frag_data.prefix_length; | |
15151 | for (next_fragP = fragP; | |
15152 | next_fragP != padding_fragP; | |
15153 | next_fragP = next_fragP->fr_next) | |
15154 | if (next_fragP->fr_type == rs_machine_dependent | |
15155 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15156 | == BRANCH_PREFIX)) | |
15157 | { | |
15158 | if (left_size) | |
15159 | { | |
15160 | int max = next_fragP->tc_frag_data.max_bytes; | |
15161 | if (max) | |
15162 | { | |
15163 | int size; | |
15164 | if (max > left_size) | |
15165 | size = left_size; | |
15166 | else | |
15167 | size = max; | |
15168 | left_size -= size; | |
15169 | next_fragP->tc_frag_data.last_length = size; | |
15170 | } | |
15171 | } | |
15172 | else | |
15173 | next_fragP->tc_frag_data.last_length = 0; | |
15174 | } | |
15175 | ||
15176 | /* Check the padding size for the padding frag. */ | |
15177 | padding_size = i386_branch_padding_size | |
15178 | (padding_fragP, (fragP->fr_address | |
15179 | + fragP->tc_frag_data.padding_address)); | |
15180 | ||
15181 | last_size = fragP->tc_frag_data.prefix_length; | |
15182 | /* Check if there is change from the last interation. */ | |
15183 | if (padding_size == last_size) | |
15184 | { | |
15185 | /* Update the expected address of the padding frag. */ | |
15186 | padding_fragP->tc_frag_data.padding_address | |
15187 | = (fragP->fr_address + padding_size | |
15188 | + fragP->tc_frag_data.padding_address); | |
15189 | return 0; | |
15190 | } | |
15191 | ||
15192 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
15193 | { | |
15194 | /* No padding if there is no sufficient room. Clear the | |
15195 | expected address of the padding frag. */ | |
15196 | padding_fragP->tc_frag_data.padding_address = 0; | |
15197 | padding_size = 0; | |
15198 | } | |
15199 | else | |
15200 | /* Store the expected address of the padding frag. */ | |
15201 | padding_fragP->tc_frag_data.padding_address | |
15202 | = (fragP->fr_address + padding_size | |
15203 | + fragP->tc_frag_data.padding_address); | |
15204 | ||
15205 | fragP->tc_frag_data.prefix_length = padding_size; | |
15206 | ||
15207 | /* Update the length for the current interation. */ | |
15208 | left_size = padding_size; | |
15209 | for (next_fragP = fragP; | |
15210 | next_fragP != padding_fragP; | |
15211 | next_fragP = next_fragP->fr_next) | |
15212 | if (next_fragP->fr_type == rs_machine_dependent | |
15213 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15214 | == BRANCH_PREFIX)) | |
15215 | { | |
15216 | if (left_size) | |
15217 | { | |
15218 | int max = next_fragP->tc_frag_data.max_bytes; | |
15219 | if (max) | |
15220 | { | |
15221 | int size; | |
15222 | if (max > left_size) | |
15223 | size = left_size; | |
15224 | else | |
15225 | size = max; | |
15226 | left_size -= size; | |
15227 | next_fragP->tc_frag_data.length = size; | |
15228 | } | |
15229 | } | |
15230 | else | |
15231 | next_fragP->tc_frag_data.length = 0; | |
15232 | } | |
15233 | ||
15234 | return (fragP->tc_frag_data.length | |
15235 | - fragP->tc_frag_data.last_length); | |
15236 | } | |
15237 | return relax_frag (segment, fragP, stretch); | |
15238 | } | |
15239 | ||
ee7fcc42 AM |
15240 | /* md_estimate_size_before_relax() |
15241 | ||
15242 | Called just before relax() for rs_machine_dependent frags. The x86 | |
15243 | assembler uses these frags to handle variable size jump | |
15244 | instructions. | |
15245 | ||
15246 | Any symbol that is now undefined will not become defined. | |
15247 | Return the correct fr_subtype in the frag. | |
15248 | Return the initial "guess for variable size of frag" to caller. | |
15249 | The guess is actually the growth beyond the fixed part. Whatever | |
15250 | we do to grow the fixed or variable part contributes to our | |
15251 | returned value. */ | |
15252 | ||
252b5132 | 15253 | int |
7016a5d5 | 15254 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 15255 | { |
e379e5f3 L |
15256 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
15257 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
15258 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
15259 | { | |
15260 | i386_classify_machine_dependent_frag (fragP); | |
15261 | return fragP->tc_frag_data.length; | |
15262 | } | |
15263 | ||
252b5132 | 15264 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
15265 | check for un-relaxable symbols. On an ELF system, we can't relax |
15266 | an externally visible symbol, because it may be overridden by a | |
15267 | shared library. */ | |
15268 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 15269 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 15270 | || (IS_ELF |
8dcea932 L |
15271 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
15272 | fragP->fr_var)) | |
fbeb56a4 DK |
15273 | #endif |
15274 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 15275 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 15276 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
15277 | #endif |
15278 | ) | |
252b5132 | 15279 | { |
b98ef147 AM |
15280 | /* Symbol is undefined in this segment, or we need to keep a |
15281 | reloc so that weak symbols can be overridden. */ | |
15282 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 15283 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
15284 | unsigned char *opcode; |
15285 | int old_fr_fix; | |
eb19308f | 15286 | fixS *fixP = NULL; |
f6af82bd | 15287 | |
ee7fcc42 | 15288 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 15289 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 15290 | else if (size == 2) |
f6af82bd | 15291 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b | 15292 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
ed719294 JB |
15293 | else if (fragP->tc_frag_data.code == CODE_64BIT |
15294 | && fragP->fr_offset == 0 | |
1ef3994a | 15295 | && need_plt32_p (fragP->fr_symbol)) |
bd7ab16b L |
15296 | reloc_type = BFD_RELOC_X86_64_PLT32; |
15297 | #endif | |
f6af82bd AM |
15298 | else |
15299 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 15300 | |
ee7fcc42 AM |
15301 | old_fr_fix = fragP->fr_fix; |
15302 | opcode = (unsigned char *) fragP->fr_opcode; | |
15303 | ||
fddf5b5b | 15304 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 15305 | { |
fddf5b5b AM |
15306 | case UNCOND_JUMP: |
15307 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 15308 | opcode[0] = 0xe9; |
252b5132 | 15309 | fragP->fr_fix += size; |
eb19308f JB |
15310 | fixP = fix_new (fragP, old_fr_fix, size, |
15311 | fragP->fr_symbol, | |
15312 | fragP->fr_offset, 1, | |
15313 | reloc_type); | |
252b5132 RH |
15314 | break; |
15315 | ||
fddf5b5b | 15316 | case COND_JUMP86: |
412167cb AM |
15317 | if (size == 2 |
15318 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
15319 | { |
15320 | /* Negate the condition, and branch past an | |
15321 | unconditional jump. */ | |
15322 | opcode[0] ^= 1; | |
15323 | opcode[1] = 3; | |
15324 | /* Insert an unconditional jump. */ | |
15325 | opcode[2] = 0xe9; | |
15326 | /* We added two extra opcode bytes, and have a two byte | |
15327 | offset. */ | |
15328 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
15329 | fix_new (fragP, old_fr_fix + 2, 2, |
15330 | fragP->fr_symbol, | |
15331 | fragP->fr_offset, 1, | |
15332 | reloc_type); | |
fddf5b5b AM |
15333 | break; |
15334 | } | |
15335 | /* Fall through. */ | |
15336 | ||
15337 | case COND_JUMP: | |
412167cb AM |
15338 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
15339 | { | |
15340 | fragP->fr_fix += 1; | |
3e02c1cc AM |
15341 | fixP = fix_new (fragP, old_fr_fix, 1, |
15342 | fragP->fr_symbol, | |
15343 | fragP->fr_offset, 1, | |
15344 | BFD_RELOC_8_PCREL); | |
15345 | fixP->fx_signed = 1; | |
412167cb AM |
15346 | break; |
15347 | } | |
93c2a809 | 15348 | |
24eab124 | 15349 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 15350 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 15351 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 15352 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
15353 | /* We've added an opcode byte. */ |
15354 | fragP->fr_fix += 1 + size; | |
eb19308f JB |
15355 | fixP = fix_new (fragP, old_fr_fix + 1, size, |
15356 | fragP->fr_symbol, | |
15357 | fragP->fr_offset, 1, | |
15358 | reloc_type); | |
252b5132 | 15359 | break; |
fddf5b5b AM |
15360 | |
15361 | default: | |
15362 | BAD_CASE (fragP->fr_subtype); | |
15363 | break; | |
252b5132 | 15364 | } |
eb19308f JB |
15365 | |
15366 | /* All jumps handled here are signed, but don't unconditionally use a | |
15367 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
15368 | around at 4G (outside of 64-bit mode) and 64k. */ | |
15369 | if (size == 4 && flag_code == CODE_64BIT) | |
15370 | fixP->fx_signed = 1; | |
15371 | ||
252b5132 | 15372 | frag_wane (fragP); |
ee7fcc42 | 15373 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 15374 | } |
93c2a809 | 15375 | |
93c2a809 AM |
15376 | /* Guess size depending on current relax state. Initially the relax |
15377 | state will correspond to a short jump and we return 1, because | |
15378 | the variable part of the frag (the branch offset) is one byte | |
15379 | long. However, we can relax a section more than once and in that | |
15380 | case we must either set fr_subtype back to the unrelaxed state, | |
15381 | or return the value for the appropriate branch. */ | |
15382 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
15383 | } |
15384 | ||
47926f60 KH |
15385 | /* Called after relax() is finished. |
15386 | ||
15387 | In: Address of frag. | |
15388 | fr_type == rs_machine_dependent. | |
15389 | fr_subtype is what the address relaxed to. | |
15390 | ||
15391 | Out: Any fixSs and constants are set up. | |
15392 | Caller will turn frag into a ".space 0". */ | |
15393 | ||
252b5132 | 15394 | void |
7016a5d5 TG |
15395 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
15396 | fragS *fragP) | |
252b5132 | 15397 | { |
29b0f896 | 15398 | unsigned char *opcode; |
252b5132 | 15399 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
15400 | offsetT target_address; |
15401 | offsetT opcode_address; | |
252b5132 | 15402 | unsigned int extension = 0; |
847f7ad4 | 15403 | offsetT displacement_from_opcode_start; |
252b5132 | 15404 | |
e379e5f3 L |
15405 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
15406 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
15407 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
15408 | { | |
15409 | /* Generate nop padding. */ | |
15410 | unsigned int size = fragP->tc_frag_data.length; | |
15411 | if (size) | |
15412 | { | |
15413 | if (size > fragP->tc_frag_data.max_bytes) | |
15414 | abort (); | |
15415 | ||
15416 | if (flag_debug) | |
15417 | { | |
15418 | const char *msg; | |
15419 | const char *branch = "branch"; | |
15420 | const char *prefix = ""; | |
15421 | fragS *padding_fragP; | |
15422 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
15423 | == BRANCH_PREFIX) | |
15424 | { | |
15425 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
15426 | switch (fragP->tc_frag_data.default_prefix) | |
15427 | { | |
15428 | default: | |
15429 | abort (); | |
15430 | break; | |
15431 | case CS_PREFIX_OPCODE: | |
15432 | prefix = " cs"; | |
15433 | break; | |
15434 | case DS_PREFIX_OPCODE: | |
15435 | prefix = " ds"; | |
15436 | break; | |
15437 | case ES_PREFIX_OPCODE: | |
15438 | prefix = " es"; | |
15439 | break; | |
15440 | case FS_PREFIX_OPCODE: | |
15441 | prefix = " fs"; | |
15442 | break; | |
15443 | case GS_PREFIX_OPCODE: | |
15444 | prefix = " gs"; | |
15445 | break; | |
15446 | case SS_PREFIX_OPCODE: | |
15447 | prefix = " ss"; | |
15448 | break; | |
15449 | } | |
15450 | if (padding_fragP) | |
15451 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
15452 | "%s within %d-byte boundary\n"); | |
15453 | else | |
15454 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
15455 | "align %s within %d-byte boundary\n"); | |
15456 | } | |
15457 | else | |
15458 | { | |
15459 | padding_fragP = fragP; | |
15460 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
15461 | "%s within %d-byte boundary\n"); | |
15462 | } | |
15463 | ||
15464 | if (padding_fragP) | |
15465 | switch (padding_fragP->tc_frag_data.branch_type) | |
15466 | { | |
15467 | case align_branch_jcc: | |
15468 | branch = "jcc"; | |
15469 | break; | |
15470 | case align_branch_fused: | |
15471 | branch = "fused jcc"; | |
15472 | break; | |
15473 | case align_branch_jmp: | |
15474 | branch = "jmp"; | |
15475 | break; | |
15476 | case align_branch_call: | |
15477 | branch = "call"; | |
15478 | break; | |
15479 | case align_branch_indirect: | |
15480 | branch = "indiret branch"; | |
15481 | break; | |
15482 | case align_branch_ret: | |
15483 | branch = "ret"; | |
15484 | break; | |
15485 | default: | |
15486 | break; | |
15487 | } | |
15488 | ||
15489 | fprintf (stdout, msg, | |
15490 | fragP->fr_file, fragP->fr_line, size, prefix, | |
15491 | (long long) fragP->fr_address, branch, | |
15492 | 1 << align_branch_power); | |
15493 | } | |
15494 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
15495 | memset (fragP->fr_opcode, | |
15496 | fragP->tc_frag_data.default_prefix, size); | |
15497 | else | |
15498 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
15499 | size, 0); | |
15500 | fragP->fr_fix += size; | |
15501 | } | |
15502 | return; | |
15503 | } | |
15504 | ||
252b5132 RH |
15505 | opcode = (unsigned char *) fragP->fr_opcode; |
15506 | ||
47926f60 | 15507 | /* Address we want to reach in file space. */ |
252b5132 | 15508 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 15509 | |
47926f60 | 15510 | /* Address opcode resides at in file space. */ |
252b5132 RH |
15511 | opcode_address = fragP->fr_address + fragP->fr_fix; |
15512 | ||
47926f60 | 15513 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
15514 | displacement_from_opcode_start = target_address - opcode_address; |
15515 | ||
fddf5b5b | 15516 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 15517 | { |
47926f60 KH |
15518 | /* Don't have to change opcode. */ |
15519 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 15520 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
15521 | } |
15522 | else | |
15523 | { | |
15524 | if (no_cond_jump_promotion | |
15525 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
15526 | as_warn_where (fragP->fr_file, fragP->fr_line, |
15527 | _("long jump required")); | |
252b5132 | 15528 | |
fddf5b5b AM |
15529 | switch (fragP->fr_subtype) |
15530 | { | |
15531 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
15532 | extension = 4; /* 1 opcode + 4 displacement */ | |
15533 | opcode[0] = 0xe9; | |
15534 | where_to_put_displacement = &opcode[1]; | |
15535 | break; | |
252b5132 | 15536 | |
fddf5b5b AM |
15537 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
15538 | extension = 2; /* 1 opcode + 2 displacement */ | |
15539 | opcode[0] = 0xe9; | |
15540 | where_to_put_displacement = &opcode[1]; | |
15541 | break; | |
252b5132 | 15542 | |
fddf5b5b AM |
15543 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
15544 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
15545 | extension = 5; /* 2 opcode + 4 displacement */ | |
15546 | opcode[1] = opcode[0] + 0x10; | |
15547 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
15548 | where_to_put_displacement = &opcode[2]; | |
15549 | break; | |
252b5132 | 15550 | |
fddf5b5b AM |
15551 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
15552 | extension = 3; /* 2 opcode + 2 displacement */ | |
15553 | opcode[1] = opcode[0] + 0x10; | |
15554 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
15555 | where_to_put_displacement = &opcode[2]; | |
15556 | break; | |
252b5132 | 15557 | |
fddf5b5b AM |
15558 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
15559 | extension = 4; | |
15560 | opcode[0] ^= 1; | |
15561 | opcode[1] = 3; | |
15562 | opcode[2] = 0xe9; | |
15563 | where_to_put_displacement = &opcode[3]; | |
15564 | break; | |
15565 | ||
15566 | default: | |
15567 | BAD_CASE (fragP->fr_subtype); | |
15568 | break; | |
15569 | } | |
252b5132 | 15570 | } |
fddf5b5b | 15571 | |
7b81dfbb AJ |
15572 | /* If size if less then four we are sure that the operand fits, |
15573 | but if it's 4, then it could be that the displacement is larger | |
15574 | then -/+ 2GB. */ | |
15575 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
15576 | && object_64bit | |
15577 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
15578 | + ((addressT) 1 << 31)) |
15579 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
15580 | { |
15581 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
15582 | _("jump target out of range")); | |
15583 | /* Make us emit 0. */ | |
15584 | displacement_from_opcode_start = extension; | |
15585 | } | |
47926f60 | 15586 | /* Now put displacement after opcode. */ |
252b5132 RH |
15587 | md_number_to_chars ((char *) where_to_put_displacement, |
15588 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 15589 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
15590 | fragP->fr_fix += extension; |
15591 | } | |
15592 | \f | |
7016a5d5 | 15593 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
15594 | by our caller that we have all the info we need to fix it up. |
15595 | ||
7016a5d5 TG |
15596 | Parameter valP is the pointer to the value of the bits. |
15597 | ||
252b5132 RH |
15598 | On the 386, immediates, displacements, and data pointers are all in |
15599 | the same (little-endian) format, so we don't need to care about which | |
15600 | we are handling. */ | |
15601 | ||
94f592af | 15602 | void |
7016a5d5 | 15603 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15604 | { |
94f592af | 15605 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 15606 | valueT value = *valP; |
252b5132 | 15607 | |
f86103b7 | 15608 | #if !defined (TE_Mach) |
93382f6d AM |
15609 | if (fixP->fx_pcrel) |
15610 | { | |
15611 | switch (fixP->fx_r_type) | |
15612 | { | |
5865bb77 ILT |
15613 | default: |
15614 | break; | |
15615 | ||
d6ab8113 JB |
15616 | case BFD_RELOC_64: |
15617 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
15618 | break; | |
93382f6d | 15619 | case BFD_RELOC_32: |
ae8887b5 | 15620 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
15621 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
15622 | break; | |
15623 | case BFD_RELOC_16: | |
15624 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
15625 | break; | |
15626 | case BFD_RELOC_8: | |
15627 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
15628 | break; | |
15629 | } | |
15630 | } | |
252b5132 | 15631 | |
a161fe53 | 15632 | if (fixP->fx_addsy != NULL |
31312f95 | 15633 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 15634 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 15635 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 15636 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 15637 | && !use_rela_relocations) |
252b5132 | 15638 | { |
31312f95 AM |
15639 | /* This is a hack. There should be a better way to handle this. |
15640 | This covers for the fact that bfd_install_relocation will | |
15641 | subtract the current location (for partial_inplace, PC relative | |
15642 | relocations); see more below. */ | |
252b5132 | 15643 | #ifndef OBJ_AOUT |
718ddfc0 | 15644 | if (IS_ELF |
252b5132 RH |
15645 | #ifdef TE_PE |
15646 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
15647 | #endif | |
15648 | ) | |
15649 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
15650 | #endif | |
15651 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 15652 | if (IS_ELF) |
252b5132 | 15653 | { |
6539b54b | 15654 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 15655 | |
6539b54b | 15656 | if ((sym_seg == seg |
2f66722d | 15657 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 15658 | && sym_seg != absolute_section)) |
af65af87 | 15659 | && !generic_force_reloc (fixP)) |
2f66722d AM |
15660 | { |
15661 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
15662 | bfd_install_relocation subtracts them out again. I think |
15663 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
15664 | it. FIXME. */ |
15665 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
15666 | } | |
252b5132 RH |
15667 | } |
15668 | #endif | |
15669 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
15670 | /* For some reason, the PE format does not store a |
15671 | section address offset for a PC relative symbol. */ | |
15672 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 15673 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
15674 | value += md_pcrel_from (fixP); |
15675 | #endif | |
15676 | } | |
fbeb56a4 | 15677 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
15678 | if (fixP->fx_addsy != NULL |
15679 | && S_IS_WEAK (fixP->fx_addsy) | |
15680 | /* PR 16858: Do not modify weak function references. */ | |
15681 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 15682 | { |
296a8689 NC |
15683 | #if !defined (TE_PEP) |
15684 | /* For x86 PE weak function symbols are neither PC-relative | |
15685 | nor do they set S_IS_FUNCTION. So the only reliable way | |
15686 | to detect them is to check the flags of their containing | |
15687 | section. */ | |
15688 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
15689 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
15690 | ; | |
15691 | else | |
15692 | #endif | |
fbeb56a4 DK |
15693 | value -= S_GET_VALUE (fixP->fx_addsy); |
15694 | } | |
15695 | #endif | |
252b5132 RH |
15696 | |
15697 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 15698 | and we must not disappoint it. */ |
252b5132 | 15699 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 15700 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
15701 | switch (fixP->fx_r_type) |
15702 | { | |
15703 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 15704 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
15705 | /* Make the jump instruction point to the address of the operand. |
15706 | At runtime we merely add the offset to the actual PLT entry. | |
15707 | NB: Subtract the offset size only for jump instructions. */ | |
15708 | if (fixP->fx_pcrel) | |
15709 | value = -4; | |
47926f60 | 15710 | break; |
31312f95 | 15711 | |
13ae64f3 JJ |
15712 | case BFD_RELOC_386_TLS_GD: |
15713 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 15714 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
15715 | case BFD_RELOC_386_TLS_IE: |
15716 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 15717 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
15718 | case BFD_RELOC_X86_64_TLSGD: |
15719 | case BFD_RELOC_X86_64_TLSLD: | |
15720 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 15721 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
5bc71c2a | 15722 | case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: |
67a4f2b7 | 15723 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 15724 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
00f7efb6 JJ |
15725 | value = 0; /* Fully resolved at runtime. No addend. */ |
15726 | /* Fallthrough */ | |
15727 | case BFD_RELOC_386_TLS_LE: | |
15728 | case BFD_RELOC_386_TLS_LDO_32: | |
15729 | case BFD_RELOC_386_TLS_LE_32: | |
15730 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 15731 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 15732 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 15733 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
15734 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15735 | break; | |
15736 | ||
67a4f2b7 AO |
15737 | case BFD_RELOC_386_TLS_DESC_CALL: |
15738 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
15739 | value = 0; /* Fully resolved at runtime. No addend. */ | |
15740 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15741 | fixP->fx_done = 0; | |
15742 | return; | |
15743 | ||
47926f60 KH |
15744 | case BFD_RELOC_VTABLE_INHERIT: |
15745 | case BFD_RELOC_VTABLE_ENTRY: | |
15746 | fixP->fx_done = 0; | |
94f592af | 15747 | return; |
47926f60 KH |
15748 | |
15749 | default: | |
15750 | break; | |
15751 | } | |
15752 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
a442cac5 JB |
15753 | |
15754 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ | |
15755 | if (!object_64bit) | |
15756 | value = extend_to_32bit_address (value); | |
15757 | ||
c6682705 | 15758 | *valP = value; |
f86103b7 | 15759 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 15760 | |
3e73aa7c | 15761 | /* Are we finished with this relocation now? */ |
c6682705 | 15762 | if (fixP->fx_addsy == NULL) |
b8188555 JB |
15763 | { |
15764 | fixP->fx_done = 1; | |
15765 | switch (fixP->fx_r_type) | |
15766 | { | |
15767 | case BFD_RELOC_X86_64_32S: | |
15768 | fixP->fx_signed = 1; | |
15769 | break; | |
15770 | ||
15771 | default: | |
15772 | break; | |
15773 | } | |
15774 | } | |
fbeb56a4 DK |
15775 | #if defined (OBJ_COFF) && defined (TE_PE) |
15776 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
15777 | { | |
15778 | fixP->fx_done = 0; | |
15779 | /* Remember value for tc_gen_reloc. */ | |
15780 | fixP->fx_addnumber = value; | |
15781 | /* Clear out the frag for now. */ | |
15782 | value = 0; | |
15783 | } | |
15784 | #endif | |
3e73aa7c JH |
15785 | else if (use_rela_relocations) |
15786 | { | |
46fb6d5a JB |
15787 | if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC) |
15788 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
15789 | /* Remember value for tc_gen_reloc. */ |
15790 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
15791 | value = 0; |
15792 | } | |
f86103b7 | 15793 | |
94f592af | 15794 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 15795 | } |
252b5132 | 15796 | \f |
6d4af3c2 | 15797 | const char * |
499ac353 | 15798 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 15799 | { |
499ac353 NC |
15800 | /* This outputs the LITTLENUMs in REVERSE order; |
15801 | in accord with the bigendian 386. */ | |
5b7c81bd | 15802 | return ieee_md_atof (type, litP, sizeP, false); |
252b5132 RH |
15803 | } |
15804 | \f | |
2d545b82 | 15805 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 15806 | |
252b5132 | 15807 | static char * |
e3bb37b5 | 15808 | output_invalid (int c) |
252b5132 | 15809 | { |
3882b010 | 15810 | if (ISPRINT (c)) |
f9f21a03 L |
15811 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
15812 | "'%c'", c); | |
252b5132 | 15813 | else |
f9f21a03 | 15814 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 15815 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
15816 | return output_invalid_buf; |
15817 | } | |
15818 | ||
8a6fb3f9 JB |
15819 | /* Verify that @r can be used in the current context. */ |
15820 | ||
5b7c81bd | 15821 | static bool check_register (const reg_entry *r) |
8a6fb3f9 JB |
15822 | { |
15823 | if (allow_pseudo_reg) | |
5b7c81bd | 15824 | return true; |
8a6fb3f9 JB |
15825 | |
15826 | if (operand_type_all_zero (&r->reg_type)) | |
5b7c81bd | 15827 | return false; |
8a6fb3f9 JB |
15828 | |
15829 | if ((r->reg_type.bitfield.dword | |
15830 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
15831 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 15832 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 | 15833 | && !cpu_arch_flags.bitfield.cpui386) |
5b7c81bd | 15834 | return false; |
8a6fb3f9 | 15835 | |
22e00a3f JB |
15836 | if (r->reg_type.bitfield.class == RegTR |
15837 | && (flag_code == CODE_64BIT | |
15838 | || !cpu_arch_flags.bitfield.cpui386 | |
15839 | || cpu_arch_isa_flags.bitfield.cpui586 | |
15840 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
5b7c81bd | 15841 | return false; |
22e00a3f | 15842 | |
8a6fb3f9 | 15843 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
5b7c81bd | 15844 | return false; |
8a6fb3f9 JB |
15845 | |
15846 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
15847 | { | |
15848 | if (r->reg_type.bitfield.zmmword | |
15849 | || r->reg_type.bitfield.class == RegMask) | |
5b7c81bd | 15850 | return false; |
8a6fb3f9 JB |
15851 | |
15852 | if (!cpu_arch_flags.bitfield.cpuavx) | |
15853 | { | |
15854 | if (r->reg_type.bitfield.ymmword) | |
5b7c81bd | 15855 | return false; |
8a6fb3f9 JB |
15856 | |
15857 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
5b7c81bd | 15858 | return false; |
8a6fb3f9 JB |
15859 | } |
15860 | } | |
15861 | ||
a6f3add0 JB |
15862 | if (r->reg_type.bitfield.zmmword) |
15863 | { | |
15864 | if (vector_size < VSZ512) | |
15865 | return false; | |
15866 | ||
eb3f3841 JB |
15867 | switch (i.encoding) |
15868 | { | |
15869 | case encoding_default: | |
15870 | case encoding_egpr: | |
15871 | i.encoding = encoding_evex512; | |
15872 | break; | |
15873 | case encoding_evex: | |
15874 | case encoding_evex512: | |
15875 | break; | |
15876 | default: | |
15877 | i.encoding = encoding_error; | |
15878 | break; | |
15879 | } | |
a6f3add0 | 15880 | } |
4fc85f37 JB |
15881 | |
15882 | if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword) | |
15883 | return false; | |
15884 | ||
260cd341 LC |
15885 | if (r->reg_type.bitfield.tmmword |
15886 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
15887 | || flag_code != CODE_64BIT)) | |
5b7c81bd | 15888 | return false; |
260cd341 | 15889 | |
8a6fb3f9 | 15890 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
5b7c81bd | 15891 | return false; |
8a6fb3f9 JB |
15892 | |
15893 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
15894 | if (!allow_index_reg && r->reg_num == RegIZ) | |
5b7c81bd | 15895 | return false; |
8a6fb3f9 JB |
15896 | |
15897 | /* Upper 16 vector registers are only available with VREX in 64bit | |
15898 | mode, and require EVEX encoding. */ | |
15899 | if (r->reg_flags & RegVRex) | |
15900 | { | |
15901 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
15902 | || flag_code != CODE_64BIT) | |
5b7c81bd | 15903 | return false; |
8a6fb3f9 | 15904 | |
eb3f3841 JB |
15905 | switch (i.encoding) |
15906 | { | |
15907 | case encoding_default: | |
15908 | case encoding_egpr: | |
15909 | case encoding_evex512: | |
15910 | i.encoding = encoding_evex; | |
15911 | break; | |
15912 | case encoding_evex: | |
15913 | break; | |
15914 | default: | |
15915 | i.encoding = encoding_error; | |
15916 | break; | |
15917 | } | |
8a6fb3f9 JB |
15918 | } |
15919 | ||
80d61d8d CL |
15920 | if (r->reg_flags & RegRex2) |
15921 | { | |
15922 | if (!cpu_arch_flags.bitfield.cpuapx_f | |
15923 | || flag_code != CODE_64BIT) | |
15924 | return false; | |
6177c84d | 15925 | |
eb3f3841 JB |
15926 | switch (i.encoding) |
15927 | { | |
15928 | case encoding_default: | |
15929 | i.encoding = encoding_egpr; | |
15930 | break; | |
15931 | case encoding_egpr: | |
15932 | case encoding_evex: | |
15933 | case encoding_evex512: | |
15934 | break; | |
15935 | default: | |
15936 | i.encoding = encoding_error; | |
15937 | break; | |
15938 | } | |
80d61d8d CL |
15939 | } |
15940 | ||
8a6fb3f9 | 15941 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
da5f9eb4 | 15942 | && (!cpu_arch_flags.bitfield.cpu64 |
0ff3b7d0 JB |
15943 | || r->reg_type.bitfield.class != RegCR |
15944 | || dot_insn ()) | |
8a6fb3f9 | 15945 | && flag_code != CODE_64BIT) |
5b7c81bd | 15946 | return false; |
8a6fb3f9 JB |
15947 | |
15948 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
15949 | && !intel_syntax) | |
5b7c81bd | 15950 | return false; |
8a6fb3f9 | 15951 | |
5b7c81bd | 15952 | return true; |
8a6fb3f9 JB |
15953 | } |
15954 | ||
af6bdddf | 15955 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
15956 | |
15957 | static const reg_entry * | |
74e05e01 | 15958 | parse_real_register (const char *reg_string, char **end_op) |
252b5132 | 15959 | { |
74e05e01 | 15960 | const char *s = reg_string; |
af6bdddf | 15961 | char *p; |
252b5132 RH |
15962 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
15963 | const reg_entry *r; | |
15964 | ||
15965 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
15966 | if (*s == REGISTER_PREFIX) | |
15967 | ++s; | |
15968 | ||
15969 | if (is_space_char (*s)) | |
15970 | ++s; | |
15971 | ||
15972 | p = reg_name_given; | |
af6bdddf | 15973 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
15974 | { |
15975 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
15976 | return (const reg_entry *) NULL; |
15977 | s++; | |
252b5132 RH |
15978 | } |
15979 | ||
4795cd4a | 15980 | if (is_part_of_name (*s)) |
6588847e DN |
15981 | return (const reg_entry *) NULL; |
15982 | ||
74e05e01 | 15983 | *end_op = (char *) s; |
252b5132 | 15984 | |
629310ab | 15985 | r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given); |
252b5132 | 15986 | |
5f47d35b | 15987 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
6288d05f | 15988 | if (r == reg_st0) |
5f47d35b | 15989 | { |
0e0eea78 JB |
15990 | if (!cpu_arch_flags.bitfield.cpu8087 |
15991 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
15992 | && !cpu_arch_flags.bitfield.cpu387 |
15993 | && !allow_pseudo_reg) | |
0e0eea78 JB |
15994 | return (const reg_entry *) NULL; |
15995 | ||
5f47d35b AM |
15996 | if (is_space_char (*s)) |
15997 | ++s; | |
15998 | if (*s == '(') | |
15999 | { | |
af6bdddf | 16000 | ++s; |
5f47d35b AM |
16001 | if (is_space_char (*s)) |
16002 | ++s; | |
16003 | if (*s >= '0' && *s <= '7') | |
16004 | { | |
db557034 | 16005 | int fpr = *s - '0'; |
af6bdddf | 16006 | ++s; |
5f47d35b AM |
16007 | if (is_space_char (*s)) |
16008 | ++s; | |
16009 | if (*s == ')') | |
16010 | { | |
74e05e01 | 16011 | *end_op = (char *) s + 1; |
6288d05f | 16012 | know (r[fpr].reg_num == fpr); |
db557034 | 16013 | return r + fpr; |
5f47d35b | 16014 | } |
5f47d35b | 16015 | } |
47926f60 | 16016 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
16017 | return (const reg_entry *) NULL; |
16018 | } | |
16019 | } | |
16020 | ||
8a6fb3f9 | 16021 | return r && check_register (r) ? r : NULL; |
252b5132 | 16022 | } |
4d1bb795 JB |
16023 | |
16024 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
16025 | ||
16026 | static const reg_entry * | |
4f081312 | 16027 | parse_register (const char *reg_string, char **end_op) |
4d1bb795 JB |
16028 | { |
16029 | const reg_entry *r; | |
16030 | ||
16031 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
16032 | r = parse_real_register (reg_string, end_op); | |
16033 | else | |
16034 | r = NULL; | |
16035 | if (!r) | |
16036 | { | |
16037 | char *save = input_line_pointer; | |
4f081312 | 16038 | char *buf = xstrdup (reg_string), *name; |
4d1bb795 JB |
16039 | symbolS *symbolP; |
16040 | ||
4f081312 JB |
16041 | input_line_pointer = buf; |
16042 | get_symbol_name (&name); | |
16043 | symbolP = symbol_find (name); | |
d50c498a | 16044 | while (symbolP && symbol_equated_p (symbolP)) |
64d23078 JB |
16045 | { |
16046 | const expressionS *e = symbol_get_value_expression(symbolP); | |
16047 | ||
d50c498a | 16048 | if (e->X_add_number) |
64d23078 JB |
16049 | break; |
16050 | symbolP = e->X_add_symbol; | |
16051 | } | |
4d1bb795 JB |
16052 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
16053 | { | |
16054 | const expressionS *e = symbol_get_value_expression (symbolP); | |
16055 | ||
0ccade1a JB |
16056 | if (e->X_op == O_register) |
16057 | { | |
16058 | know (e->X_add_number >= 0 | |
16059 | && (valueT) e->X_add_number < i386_regtab_size); | |
16060 | r = i386_regtab + e->X_add_number; | |
4f081312 | 16061 | *end_op = (char *) reg_string + (input_line_pointer - buf); |
0ccade1a JB |
16062 | } |
16063 | if (r && !check_register (r)) | |
8a6fb3f9 | 16064 | { |
3b55a1d0 JB |
16065 | as_bad (_("register '%s%s' cannot be used here"), |
16066 | register_prefix, r->reg_name); | |
16067 | r = &bad_reg; | |
8a6fb3f9 | 16068 | } |
4d1bb795 | 16069 | } |
4d1bb795 | 16070 | input_line_pointer = save; |
4f081312 | 16071 | free (buf); |
4d1bb795 JB |
16072 | } |
16073 | return r; | |
16074 | } | |
16075 | ||
16076 | int | |
16077 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
16078 | { | |
4faaa10f | 16079 | const reg_entry *r = NULL; |
4d1bb795 JB |
16080 | char *end = input_line_pointer; |
16081 | ||
6acf9130 JB |
16082 | /* We only know the terminating character here. It being double quote could |
16083 | be the closing one of a quoted symbol name, or an opening one from a | |
16084 | following string (or another quoted symbol name). Since the latter can't | |
16085 | be valid syntax for anything, bailing in either case is good enough. */ | |
16086 | if (*nextcharP == '"') | |
16087 | return 0; | |
16088 | ||
4d1bb795 | 16089 | *end = *nextcharP; |
4faaa10f JB |
16090 | if (*name == REGISTER_PREFIX || allow_naked_reg) |
16091 | r = parse_real_register (name, &input_line_pointer); | |
4d1bb795 JB |
16092 | if (r && end <= input_line_pointer) |
16093 | { | |
16094 | *nextcharP = *input_line_pointer; | |
16095 | *input_line_pointer = 0; | |
f847749a JB |
16096 | e->X_op = O_register; |
16097 | e->X_add_number = r - i386_regtab; | |
4d1bb795 JB |
16098 | return 1; |
16099 | } | |
16100 | input_line_pointer = end; | |
16101 | *end = 0; | |
ee86248c | 16102 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
16103 | } |
16104 | ||
16105 | void | |
16106 | md_operand (expressionS *e) | |
16107 | { | |
ee86248c JB |
16108 | char *end; |
16109 | const reg_entry *r; | |
4d1bb795 | 16110 | |
ee86248c JB |
16111 | switch (*input_line_pointer) |
16112 | { | |
16113 | case REGISTER_PREFIX: | |
16114 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
16115 | if (r) |
16116 | { | |
16117 | e->X_op = O_register; | |
16118 | e->X_add_number = r - i386_regtab; | |
16119 | input_line_pointer = end; | |
16120 | } | |
ee86248c JB |
16121 | break; |
16122 | ||
16123 | case '[': | |
9c2799c2 | 16124 | gas_assert (intel_syntax); |
ee86248c JB |
16125 | end = input_line_pointer++; |
16126 | expression (e); | |
16127 | if (*input_line_pointer == ']') | |
16128 | { | |
16129 | ++input_line_pointer; | |
16130 | e->X_op_symbol = make_expr_symbol (e); | |
16131 | e->X_add_symbol = NULL; | |
16132 | e->X_add_number = 0; | |
16133 | e->X_op = O_index; | |
16134 | } | |
16135 | else | |
16136 | { | |
16137 | e->X_op = O_absent; | |
16138 | input_line_pointer = end; | |
16139 | } | |
16140 | break; | |
4d1bb795 JB |
16141 | } |
16142 | } | |
16143 | ||
5cc00775 JB |
16144 | #ifdef BFD64 |
16145 | /* To maintain consistency with !BFD64 builds of gas record, whether any | |
16146 | (binary) operator was involved in an expression. As expressions are | |
16147 | evaluated in only 32 bits when !BFD64, we use this to decide whether to | |
16148 | truncate results. */ | |
16149 | bool i386_record_operator (operatorT op, | |
16150 | const expressionS *left, | |
16151 | const expressionS *right) | |
16152 | { | |
16153 | if (op == O_absent) | |
16154 | return false; | |
16155 | ||
16156 | if (!left) | |
16157 | { | |
16158 | /* Since the expression parser applies unary operators fine to bignum | |
16159 | operands, we don't need to be concerned of respective operands not | |
16160 | fitting in 32 bits. */ | |
16161 | if (right->X_op == O_constant && right->X_unsigned | |
16162 | && !fits_in_unsigned_long (right->X_add_number)) | |
16163 | return false; | |
16164 | } | |
16165 | /* This isn't entirely right: The pattern can also result when constant | |
16166 | expressions are folded (e.g. 0xffffffff + 1). */ | |
16167 | else if ((left->X_op == O_constant && left->X_unsigned | |
16168 | && !fits_in_unsigned_long (left->X_add_number)) | |
16169 | || (right->X_op == O_constant && right->X_unsigned | |
16170 | && !fits_in_unsigned_long (right->X_add_number))) | |
16171 | expr_mode = expr_large_value; | |
16172 | ||
16173 | if (expr_mode != expr_large_value) | |
16174 | expr_mode = expr_operator_present; | |
16175 | ||
16176 | return false; | |
16177 | } | |
16178 | #endif | |
252b5132 | 16179 | \f |
4cc782b5 | 16180 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 16181 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 16182 | #else |
b6f8c7c4 | 16183 | const char *md_shortopts = "qnO::"; |
252b5132 | 16184 | #endif |
6e0b89ee | 16185 | |
3e73aa7c | 16186 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
16187 | #define OPTION_64 (OPTION_MD_BASE + 1) |
16188 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
16189 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
16190 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
16191 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
16192 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
16193 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
16194 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 16195 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 16196 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 16197 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
16198 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
16199 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
16200 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 16201 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
16202 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
16203 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 16204 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 16205 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 16206 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 16207 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
16208 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
16209 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 16210 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 16211 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 16212 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
16213 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
16214 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
16215 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 16216 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
16217 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
16218 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
16219 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
c8480b58 | 16220 | #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34) |
b3b91714 | 16221 | |
99ad8390 NC |
16222 | struct option md_longopts[] = |
16223 | { | |
3e73aa7c | 16224 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 16225 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 16226 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 16227 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
16228 | #endif |
16229 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 16230 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 16231 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 16232 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 16233 | #endif |
b3b91714 | 16234 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
16235 | {"march", required_argument, NULL, OPTION_MARCH}, |
16236 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
16237 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
16238 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
16239 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
16240 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 16241 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
c8480b58 | 16242 | {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE}, |
daf50ae7 | 16243 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 16244 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 16245 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 16246 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 16247 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
16248 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
16249 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
16250 | # if defined (TE_PE) || defined (TE_PEP) |
16251 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
16252 | #endif | |
d1982f93 | 16253 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 16254 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 16255 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 16256 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
16257 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
16258 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
16259 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 16260 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
16261 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
16262 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
16263 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
16264 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
16265 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
16266 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
16267 | {NULL, no_argument, NULL, 0} |
16268 | }; | |
16269 | size_t md_longopts_size = sizeof (md_longopts); | |
16270 | ||
16271 | int | |
17b9d67d | 16272 | md_parse_option (int c, const char *arg) |
252b5132 | 16273 | { |
91d6fa6a | 16274 | unsigned int j; |
e379e5f3 | 16275 | char *arch, *next, *saved, *type; |
9103f4f4 | 16276 | |
252b5132 RH |
16277 | switch (c) |
16278 | { | |
12b55ccc L |
16279 | case 'n': |
16280 | optimize_align_code = 0; | |
16281 | break; | |
16282 | ||
a38cf1db AM |
16283 | case 'q': |
16284 | quiet_warnings = 1; | |
252b5132 RH |
16285 | break; |
16286 | ||
16287 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
16288 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
16289 | should be emitted or not. FIXME: Not implemented. */ | |
16290 | case 'Q': | |
d4693039 JB |
16291 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
16292 | return 0; | |
252b5132 RH |
16293 | break; |
16294 | ||
16295 | /* -V: SVR4 argument to print version ID. */ | |
16296 | case 'V': | |
16297 | print_version_id (); | |
16298 | break; | |
16299 | ||
a38cf1db AM |
16300 | /* -k: Ignore for FreeBSD compatibility. */ |
16301 | case 'k': | |
252b5132 | 16302 | break; |
4cc782b5 ILT |
16303 | |
16304 | case 's': | |
16305 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 16306 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 16307 | break; |
8dcea932 L |
16308 | |
16309 | case OPTION_MSHARED: | |
16310 | shared = 1; | |
16311 | break; | |
b4a3a7b4 L |
16312 | |
16313 | case OPTION_X86_USED_NOTE: | |
16314 | if (strcasecmp (arg, "yes") == 0) | |
16315 | x86_used_note = 1; | |
16316 | else if (strcasecmp (arg, "no") == 0) | |
16317 | x86_used_note = 0; | |
16318 | else | |
16319 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
16320 | break; | |
16321 | ||
16322 | ||
99ad8390 | 16323 | #endif |
321098a5 | 16324 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 16325 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
16326 | case OPTION_64: |
16327 | { | |
16328 | const char **list, **l; | |
16329 | ||
3e73aa7c JH |
16330 | list = bfd_target_list (); |
16331 | for (l = list; *l != NULL; l++) | |
08dedd66 | 16332 | if (startswith (*l, "elf64-x86-64") |
99ad8390 NC |
16333 | || strcmp (*l, "coff-x86-64") == 0 |
16334 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
16335 | || strcmp (*l, "pei-x86-64") == 0 |
16336 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
16337 | { |
16338 | default_arch = "x86_64"; | |
16339 | break; | |
16340 | } | |
3e73aa7c | 16341 | if (*l == NULL) |
2b5d6a91 | 16342 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
16343 | free (list); |
16344 | } | |
16345 | break; | |
16346 | #endif | |
252b5132 | 16347 | |
351f65ca | 16348 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 16349 | case OPTION_X32: |
351f65ca L |
16350 | if (IS_ELF) |
16351 | { | |
16352 | const char **list, **l; | |
16353 | ||
16354 | list = bfd_target_list (); | |
16355 | for (l = list; *l != NULL; l++) | |
08dedd66 | 16356 | if (startswith (*l, "elf32-x86-64")) |
351f65ca L |
16357 | { |
16358 | default_arch = "x86_64:32"; | |
16359 | break; | |
16360 | } | |
16361 | if (*l == NULL) | |
2b5d6a91 | 16362 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
16363 | free (list); |
16364 | } | |
16365 | else | |
16366 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
16367 | break; | |
16368 | #endif | |
16369 | ||
6e0b89ee | 16370 | case OPTION_32: |
590a0fed JB |
16371 | { |
16372 | const char **list, **l; | |
16373 | ||
16374 | list = bfd_target_list (); | |
16375 | for (l = list; *l != NULL; l++) | |
16376 | if (strstr (*l, "-i386") | |
16377 | || strstr (*l, "-go32")) | |
16378 | { | |
16379 | default_arch = "i386"; | |
16380 | break; | |
16381 | } | |
16382 | if (*l == NULL) | |
16383 | as_fatal (_("no compiled in support for ix86")); | |
16384 | free (list); | |
16385 | } | |
6e0b89ee AM |
16386 | break; |
16387 | ||
b3b91714 AM |
16388 | case OPTION_DIVIDE: |
16389 | #ifdef SVR4_COMMENT_CHARS | |
16390 | { | |
16391 | char *n, *t; | |
16392 | const char *s; | |
16393 | ||
add39d23 | 16394 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
16395 | t = n; |
16396 | for (s = i386_comment_chars; *s != '\0'; s++) | |
16397 | if (*s != '/') | |
16398 | *t++ = *s; | |
16399 | *t = '\0'; | |
16400 | i386_comment_chars = n; | |
16401 | } | |
16402 | #endif | |
16403 | break; | |
16404 | ||
9103f4f4 | 16405 | case OPTION_MARCH: |
293f5f65 L |
16406 | saved = xstrdup (arg); |
16407 | arch = saved; | |
16408 | /* Allow -march=+nosse. */ | |
16409 | if (*arch == '+') | |
16410 | arch++; | |
6305a203 | 16411 | do |
9103f4f4 | 16412 | { |
4fc85f37 JB |
16413 | char *vsz; |
16414 | ||
6305a203 | 16415 | if (*arch == '.') |
2b5d6a91 | 16416 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
16417 | next = strchr (arch, '+'); |
16418 | if (next) | |
16419 | *next++ = '\0'; | |
4fc85f37 JB |
16420 | vsz = strchr (arch, '/'); |
16421 | if (vsz) | |
16422 | *vsz++ = '\0'; | |
91d6fa6a | 16423 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 16424 | { |
4fc85f37 JB |
16425 | if (vsz && cpu_arch[j].vsz != vsz_set) |
16426 | continue; | |
16427 | ||
ae89daec JB |
16428 | if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE |
16429 | && strcmp (arch, cpu_arch[j].name) == 0) | |
ccc9c027 | 16430 | { |
6305a203 | 16431 | /* Processor. */ |
ae89daec | 16432 | if (! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
16433 | continue; |
16434 | ||
91d6fa6a | 16435 | cpu_arch_name = cpu_arch[j].name; |
d92c7521 | 16436 | free (cpu_sub_arch_name); |
6305a203 | 16437 | cpu_sub_arch_name = NULL; |
ae89daec | 16438 | cpu_arch_flags = cpu_arch[j].enable; |
91d6fa6a | 16439 | cpu_arch_isa = cpu_arch[j].type; |
ae89daec | 16440 | cpu_arch_isa_flags = cpu_arch[j].enable; |
6305a203 | 16441 | if (!cpu_arch_tune_set) |
fb263707 | 16442 | cpu_arch_tune = cpu_arch_isa; |
4fc85f37 | 16443 | vector_size = VSZ_DEFAULT; |
6305a203 L |
16444 | break; |
16445 | } | |
ae89daec JB |
16446 | else if (cpu_arch[j].type == PROCESSOR_NONE |
16447 | && strcmp (arch, cpu_arch[j].name) == 0 | |
16448 | && !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
6305a203 | 16449 | { |
33eaf5de | 16450 | /* ISA extension. */ |
bd483d21 | 16451 | isa_enable (j); |
4fc85f37 JB |
16452 | |
16453 | switch (cpu_arch[j].vsz) | |
16454 | { | |
16455 | default: | |
16456 | break; | |
16457 | ||
16458 | case vsz_set: | |
16459 | if (vsz) | |
16460 | { | |
16461 | char *end; | |
16462 | unsigned long val = strtoul (vsz, &end, 0); | |
16463 | ||
16464 | if (*end) | |
16465 | val = 0; | |
16466 | switch (val) | |
16467 | { | |
16468 | case 512: vector_size = VSZ512; break; | |
16469 | case 256: vector_size = VSZ256; break; | |
16470 | case 128: vector_size = VSZ128; break; | |
16471 | default: | |
16472 | as_warn (_("Unrecognized vector size specifier ignored")); | |
16473 | break; | |
16474 | } | |
16475 | break; | |
16476 | } | |
16477 | /* Fall through. */ | |
16478 | case vsz_reset: | |
16479 | vector_size = VSZ_DEFAULT; | |
16480 | break; | |
16481 | } | |
16482 | ||
6305a203 | 16483 | break; |
ccc9c027 | 16484 | } |
9103f4f4 | 16485 | } |
6305a203 | 16486 | |
ae89daec | 16487 | if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no")) |
293f5f65 | 16488 | { |
33eaf5de | 16489 | /* Disable an ISA extension. */ |
ae89daec JB |
16490 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
16491 | if (cpu_arch[j].type == PROCESSOR_NONE | |
16492 | && strcmp (arch + 2, cpu_arch[j].name) == 0) | |
293f5f65 | 16493 | { |
bd483d21 | 16494 | isa_disable (j); |
4fc85f37 JB |
16495 | if (cpu_arch[j].vsz == vsz_set) |
16496 | vector_size = VSZ_DEFAULT; | |
293f5f65 L |
16497 | break; |
16498 | } | |
293f5f65 L |
16499 | } |
16500 | ||
91d6fa6a | 16501 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 16502 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
16503 | |
16504 | arch = next; | |
9103f4f4 | 16505 | } |
293f5f65 L |
16506 | while (next != NULL); |
16507 | free (saved); | |
9103f4f4 L |
16508 | break; |
16509 | ||
16510 | case OPTION_MTUNE: | |
16511 | if (*arg == '.') | |
2b5d6a91 | 16512 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 16513 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 16514 | { |
ae89daec JB |
16515 | if (cpu_arch[j].type != PROCESSOR_NONE |
16516 | && strcmp (arg, cpu_arch[j].name) == 0) | |
9103f4f4 | 16517 | { |
ccc9c027 | 16518 | cpu_arch_tune_set = 1; |
91d6fa6a | 16519 | cpu_arch_tune = cpu_arch [j].type; |
9103f4f4 L |
16520 | break; |
16521 | } | |
16522 | } | |
91d6fa6a | 16523 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 16524 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
16525 | break; |
16526 | ||
1efbbeb4 L |
16527 | case OPTION_MMNEMONIC: |
16528 | if (strcasecmp (arg, "att") == 0) | |
16529 | intel_mnemonic = 0; | |
16530 | else if (strcasecmp (arg, "intel") == 0) | |
16531 | intel_mnemonic = 1; | |
16532 | else | |
2b5d6a91 | 16533 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
16534 | break; |
16535 | ||
16536 | case OPTION_MSYNTAX: | |
16537 | if (strcasecmp (arg, "att") == 0) | |
213f15cf | 16538 | _set_intel_syntax (0); |
1efbbeb4 | 16539 | else if (strcasecmp (arg, "intel") == 0) |
213f15cf | 16540 | _set_intel_syntax (1); |
1efbbeb4 | 16541 | else |
2b5d6a91 | 16542 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
16543 | break; |
16544 | ||
16545 | case OPTION_MINDEX_REG: | |
16546 | allow_index_reg = 1; | |
16547 | break; | |
16548 | ||
16549 | case OPTION_MNAKED_REG: | |
16550 | allow_naked_reg = 1; | |
213f15cf | 16551 | register_prefix = ""; |
1efbbeb4 L |
16552 | break; |
16553 | ||
c0f3af97 L |
16554 | case OPTION_MSSE2AVX: |
16555 | sse2avx = 1; | |
16556 | break; | |
16557 | ||
c8480b58 L |
16558 | case OPTION_MUSE_UNALIGNED_VECTOR_MOVE: |
16559 | use_unaligned_vector_move = 1; | |
16560 | break; | |
16561 | ||
daf50ae7 L |
16562 | case OPTION_MSSE_CHECK: |
16563 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 16564 | sse_check = check_error; |
daf50ae7 | 16565 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 16566 | sse_check = check_warning; |
daf50ae7 | 16567 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 16568 | sse_check = check_none; |
daf50ae7 | 16569 | else |
2b5d6a91 | 16570 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
16571 | break; |
16572 | ||
7bab8ab5 JB |
16573 | case OPTION_MOPERAND_CHECK: |
16574 | if (strcasecmp (arg, "error") == 0) | |
16575 | operand_check = check_error; | |
16576 | else if (strcasecmp (arg, "warning") == 0) | |
16577 | operand_check = check_warning; | |
16578 | else if (strcasecmp (arg, "none") == 0) | |
16579 | operand_check = check_none; | |
16580 | else | |
16581 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
16582 | break; | |
16583 | ||
539f890d L |
16584 | case OPTION_MAVXSCALAR: |
16585 | if (strcasecmp (arg, "128") == 0) | |
16586 | avxscalar = vex128; | |
16587 | else if (strcasecmp (arg, "256") == 0) | |
16588 | avxscalar = vex256; | |
16589 | else | |
2b5d6a91 | 16590 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
16591 | break; |
16592 | ||
03751133 L |
16593 | case OPTION_MVEXWIG: |
16594 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 16595 | vexwig = vexw0; |
03751133 | 16596 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 16597 | vexwig = vexw1; |
03751133 L |
16598 | else |
16599 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
16600 | break; | |
16601 | ||
7e8b059b L |
16602 | case OPTION_MADD_BND_PREFIX: |
16603 | add_bnd_prefix = 1; | |
16604 | break; | |
16605 | ||
43234a1e L |
16606 | case OPTION_MEVEXLIG: |
16607 | if (strcmp (arg, "128") == 0) | |
16608 | evexlig = evexl128; | |
16609 | else if (strcmp (arg, "256") == 0) | |
16610 | evexlig = evexl256; | |
16611 | else if (strcmp (arg, "512") == 0) | |
16612 | evexlig = evexl512; | |
16613 | else | |
16614 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
16615 | break; | |
16616 | ||
d3d3c6db IT |
16617 | case OPTION_MEVEXRCIG: |
16618 | if (strcmp (arg, "rne") == 0) | |
16619 | evexrcig = rne; | |
16620 | else if (strcmp (arg, "rd") == 0) | |
16621 | evexrcig = rd; | |
16622 | else if (strcmp (arg, "ru") == 0) | |
16623 | evexrcig = ru; | |
16624 | else if (strcmp (arg, "rz") == 0) | |
16625 | evexrcig = rz; | |
16626 | else | |
16627 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
16628 | break; | |
16629 | ||
43234a1e L |
16630 | case OPTION_MEVEXWIG: |
16631 | if (strcmp (arg, "0") == 0) | |
16632 | evexwig = evexw0; | |
16633 | else if (strcmp (arg, "1") == 0) | |
16634 | evexwig = evexw1; | |
16635 | else | |
16636 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
16637 | break; | |
16638 | ||
167ad85b TG |
16639 | # if defined (TE_PE) || defined (TE_PEP) |
16640 | case OPTION_MBIG_OBJ: | |
16641 | use_big_obj = 1; | |
16642 | break; | |
16643 | #endif | |
16644 | ||
d1982f93 | 16645 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
16646 | if (strcasecmp (arg, "yes") == 0) |
16647 | omit_lock_prefix = 1; | |
16648 | else if (strcasecmp (arg, "no") == 0) | |
16649 | omit_lock_prefix = 0; | |
16650 | else | |
16651 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
16652 | break; | |
16653 | ||
e4e00185 AS |
16654 | case OPTION_MFENCE_AS_LOCK_ADD: |
16655 | if (strcasecmp (arg, "yes") == 0) | |
16656 | avoid_fence = 1; | |
16657 | else if (strcasecmp (arg, "no") == 0) | |
16658 | avoid_fence = 0; | |
16659 | else | |
16660 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
16661 | break; | |
16662 | ||
ae531041 L |
16663 | case OPTION_MLFENCE_AFTER_LOAD: |
16664 | if (strcasecmp (arg, "yes") == 0) | |
16665 | lfence_after_load = 1; | |
16666 | else if (strcasecmp (arg, "no") == 0) | |
16667 | lfence_after_load = 0; | |
16668 | else | |
16669 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
16670 | break; | |
16671 | ||
16672 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
16673 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 16674 | { |
16675 | lfence_before_indirect_branch = lfence_branch_all; | |
16676 | if (lfence_before_ret == lfence_before_ret_none) | |
16677 | lfence_before_ret = lfence_before_ret_shl; | |
16678 | } | |
ae531041 L |
16679 | else if (strcasecmp (arg, "memory") == 0) |
16680 | lfence_before_indirect_branch = lfence_branch_memory; | |
16681 | else if (strcasecmp (arg, "register") == 0) | |
16682 | lfence_before_indirect_branch = lfence_branch_register; | |
16683 | else if (strcasecmp (arg, "none") == 0) | |
16684 | lfence_before_indirect_branch = lfence_branch_none; | |
16685 | else | |
16686 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
16687 | arg); | |
16688 | break; | |
16689 | ||
16690 | case OPTION_MLFENCE_BEFORE_RET: | |
16691 | if (strcasecmp (arg, "or") == 0) | |
16692 | lfence_before_ret = lfence_before_ret_or; | |
16693 | else if (strcasecmp (arg, "not") == 0) | |
16694 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 16695 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
16696 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
16697 | else if (strcasecmp (arg, "none") == 0) |
16698 | lfence_before_ret = lfence_before_ret_none; | |
16699 | else | |
16700 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
16701 | arg); | |
16702 | break; | |
16703 | ||
0cb4071e L |
16704 | case OPTION_MRELAX_RELOCATIONS: |
16705 | if (strcasecmp (arg, "yes") == 0) | |
16706 | generate_relax_relocations = 1; | |
16707 | else if (strcasecmp (arg, "no") == 0) | |
16708 | generate_relax_relocations = 0; | |
16709 | else | |
16710 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
16711 | break; | |
16712 | ||
e379e5f3 L |
16713 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
16714 | { | |
16715 | char *end; | |
16716 | long int align = strtoul (arg, &end, 0); | |
16717 | if (*end == '\0') | |
16718 | { | |
16719 | if (align == 0) | |
16720 | { | |
16721 | align_branch_power = 0; | |
16722 | break; | |
16723 | } | |
16724 | else if (align >= 16) | |
16725 | { | |
16726 | int align_power; | |
16727 | for (align_power = 0; | |
16728 | (align & 1) == 0; | |
16729 | align >>= 1, align_power++) | |
16730 | continue; | |
16731 | /* Limit alignment power to 31. */ | |
16732 | if (align == 1 && align_power < 32) | |
16733 | { | |
16734 | align_branch_power = align_power; | |
16735 | break; | |
16736 | } | |
16737 | } | |
16738 | } | |
16739 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
16740 | } | |
16741 | break; | |
16742 | ||
16743 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
16744 | { | |
16745 | char *end; | |
16746 | int align = strtoul (arg, &end, 0); | |
16747 | /* Some processors only support 5 prefixes. */ | |
16748 | if (*end == '\0' && align >= 0 && align < 6) | |
16749 | { | |
16750 | align_branch_prefix_size = align; | |
16751 | break; | |
16752 | } | |
16753 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
16754 | arg); | |
16755 | } | |
16756 | break; | |
16757 | ||
16758 | case OPTION_MALIGN_BRANCH: | |
16759 | align_branch = 0; | |
16760 | saved = xstrdup (arg); | |
16761 | type = saved; | |
16762 | do | |
16763 | { | |
16764 | next = strchr (type, '+'); | |
16765 | if (next) | |
16766 | *next++ = '\0'; | |
16767 | if (strcasecmp (type, "jcc") == 0) | |
16768 | align_branch |= align_branch_jcc_bit; | |
16769 | else if (strcasecmp (type, "fused") == 0) | |
16770 | align_branch |= align_branch_fused_bit; | |
16771 | else if (strcasecmp (type, "jmp") == 0) | |
16772 | align_branch |= align_branch_jmp_bit; | |
16773 | else if (strcasecmp (type, "call") == 0) | |
16774 | align_branch |= align_branch_call_bit; | |
16775 | else if (strcasecmp (type, "ret") == 0) | |
16776 | align_branch |= align_branch_ret_bit; | |
16777 | else if (strcasecmp (type, "indirect") == 0) | |
16778 | align_branch |= align_branch_indirect_bit; | |
16779 | else | |
16780 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
16781 | type = next; | |
16782 | } | |
16783 | while (next != NULL); | |
16784 | free (saved); | |
16785 | break; | |
16786 | ||
76cf450b L |
16787 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
16788 | align_branch_power = 5; | |
16789 | align_branch_prefix_size = 5; | |
16790 | align_branch = (align_branch_jcc_bit | |
16791 | | align_branch_fused_bit | |
16792 | | align_branch_jmp_bit); | |
16793 | break; | |
16794 | ||
5db04b09 | 16795 | case OPTION_MAMD64: |
4b5aaf5f | 16796 | isa64 = amd64; |
5db04b09 L |
16797 | break; |
16798 | ||
16799 | case OPTION_MINTEL64: | |
4b5aaf5f | 16800 | isa64 = intel64; |
5db04b09 L |
16801 | break; |
16802 | ||
b6f8c7c4 L |
16803 | case 'O': |
16804 | if (arg == NULL) | |
16805 | { | |
16806 | optimize = 1; | |
16807 | /* Turn off -Os. */ | |
16808 | optimize_for_space = 0; | |
16809 | } | |
16810 | else if (*arg == 's') | |
16811 | { | |
16812 | optimize_for_space = 1; | |
16813 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 16814 | optimize = INT_MAX; |
b6f8c7c4 L |
16815 | } |
16816 | else | |
16817 | { | |
16818 | optimize = atoi (arg); | |
16819 | /* Turn off -Os. */ | |
16820 | optimize_for_space = 0; | |
16821 | } | |
16822 | break; | |
16823 | ||
252b5132 RH |
16824 | default: |
16825 | return 0; | |
16826 | } | |
16827 | return 1; | |
16828 | } | |
16829 | ||
8a2c8fef L |
16830 | #define MESSAGE_TEMPLATE \ |
16831 | " " | |
16832 | ||
293f5f65 L |
16833 | static char * |
16834 | output_message (FILE *stream, char *p, char *message, char *start, | |
16835 | int *left_p, const char *name, int len) | |
16836 | { | |
16837 | int size = sizeof (MESSAGE_TEMPLATE); | |
16838 | int left = *left_p; | |
16839 | ||
16840 | /* Reserve 2 spaces for ", " or ",\0" */ | |
16841 | left -= len + 2; | |
16842 | ||
16843 | /* Check if there is any room. */ | |
16844 | if (left >= 0) | |
16845 | { | |
16846 | if (p != start) | |
16847 | { | |
16848 | *p++ = ','; | |
16849 | *p++ = ' '; | |
16850 | } | |
16851 | p = mempcpy (p, name, len); | |
16852 | } | |
16853 | else | |
16854 | { | |
16855 | /* Output the current message now and start a new one. */ | |
16856 | *p++ = ','; | |
16857 | *p = '\0'; | |
16858 | fprintf (stream, "%s\n", message); | |
16859 | p = start; | |
16860 | left = size - (start - message) - len - 2; | |
16861 | ||
16862 | gas_assert (left >= 0); | |
16863 | ||
16864 | p = mempcpy (p, name, len); | |
16865 | } | |
16866 | ||
16867 | *left_p = left; | |
16868 | return p; | |
16869 | } | |
16870 | ||
8a2c8fef | 16871 | static void |
1ded5609 | 16872 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
16873 | { |
16874 | static char message[] = MESSAGE_TEMPLATE; | |
16875 | char *start = message + 27; | |
16876 | char *p; | |
16877 | int size = sizeof (MESSAGE_TEMPLATE); | |
16878 | int left; | |
16879 | const char *name; | |
16880 | int len; | |
16881 | unsigned int j; | |
16882 | ||
16883 | p = start; | |
16884 | left = size - (start - message); | |
3ce2ebcf JB |
16885 | |
16886 | if (!ext && check) | |
16887 | { | |
16888 | p = output_message (stream, p, message, start, &left, | |
16889 | STRING_COMMA_LEN ("default")); | |
f68697e8 JB |
16890 | p = output_message (stream, p, message, start, &left, |
16891 | STRING_COMMA_LEN ("push")); | |
16892 | p = output_message (stream, p, message, start, &left, | |
16893 | STRING_COMMA_LEN ("pop")); | |
3ce2ebcf JB |
16894 | } |
16895 | ||
8a2c8fef L |
16896 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
16897 | { | |
16898 | /* Should it be skipped? */ | |
16899 | if (cpu_arch [j].skip) | |
16900 | continue; | |
16901 | ||
16902 | name = cpu_arch [j].name; | |
16903 | len = cpu_arch [j].len; | |
ae89daec | 16904 | if (cpu_arch[j].type == PROCESSOR_NONE) |
8a2c8fef L |
16905 | { |
16906 | /* It is an extension. Skip if we aren't asked to show it. */ | |
ae89daec | 16907 | if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable)) |
8a2c8fef L |
16908 | continue; |
16909 | } | |
16910 | else if (ext) | |
16911 | { | |
16912 | /* It is an processor. Skip if we show only extension. */ | |
16913 | continue; | |
16914 | } | |
ae89daec | 16915 | else if (check && ! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
16916 | { |
16917 | /* It is an impossible processor - skip. */ | |
16918 | continue; | |
16919 | } | |
8a2c8fef | 16920 | |
293f5f65 | 16921 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
16922 | } |
16923 | ||
293f5f65 L |
16924 | /* Display disabled extensions. */ |
16925 | if (ext) | |
ae89daec | 16926 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
293f5f65 | 16927 | { |
ae89daec JB |
16928 | char *str; |
16929 | ||
16930 | if (cpu_arch[j].type != PROCESSOR_NONE | |
16931 | || !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
16932 | continue; | |
16933 | str = xasprintf ("no%s", cpu_arch[j].name); | |
16934 | p = output_message (stream, p, message, start, &left, str, | |
16935 | strlen (str)); | |
16936 | free (str); | |
293f5f65 L |
16937 | } |
16938 | ||
8a2c8fef L |
16939 | *p = '\0'; |
16940 | fprintf (stream, "%s\n", message); | |
16941 | } | |
16942 | ||
252b5132 | 16943 | void |
8a2c8fef | 16944 | md_show_usage (FILE *stream) |
252b5132 | 16945 | { |
4cc782b5 ILT |
16946 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
16947 | fprintf (stream, _("\ | |
d4693039 | 16948 | -Qy, -Qn ignored\n\ |
a38cf1db | 16949 | -V print assembler version number\n\ |
b3b91714 AM |
16950 | -k ignored\n")); |
16951 | #endif | |
16952 | fprintf (stream, _("\ | |
7ebd68d1 NC |
16953 | -n do not optimize code alignment\n\ |
16954 | -O{012s} attempt some code optimizations\n\ | |
b3b91714 AM |
16955 | -q quieten some warnings\n")); |
16956 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
16957 | fprintf (stream, _("\ | |
a38cf1db | 16958 | -s ignored\n")); |
b3b91714 | 16959 | #endif |
b00af7c8 JB |
16960 | #ifdef BFD64 |
16961 | # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
16962 | fprintf (stream, _("\ | |
16963 | --32/--64/--x32 generate 32bit/64bit/x32 object\n")); | |
16964 | # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O) | |
751d281c | 16965 | fprintf (stream, _("\ |
b00af7c8 JB |
16966 | --32/--64 generate 32bit/64bit object\n")); |
16967 | # endif | |
751d281c | 16968 | #endif |
b3b91714 AM |
16969 | #ifdef SVR4_COMMENT_CHARS |
16970 | fprintf (stream, _("\ | |
16971 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
16972 | #else |
16973 | fprintf (stream, _("\ | |
b3b91714 | 16974 | --divide ignored\n")); |
4cc782b5 | 16975 | #endif |
9103f4f4 | 16976 | fprintf (stream, _("\ |
6305a203 | 16977 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 16978 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 16979 | show_arch (stream, 0, 1); |
8a2c8fef | 16980 | fprintf (stream, _("\ |
ae89daec | 16981 | EXTENSION is combination of (possibly \"no\"-prefixed):\n")); |
1ded5609 | 16982 | show_arch (stream, 1, 0); |
6305a203 | 16983 | fprintf (stream, _("\ |
8a2c8fef | 16984 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 16985 | show_arch (stream, 0, 0); |
ba104c83 | 16986 | fprintf (stream, _("\ |
c0f3af97 L |
16987 | -msse2avx encode SSE instructions with VEX prefix\n")); |
16988 | fprintf (stream, _("\ | |
c8480b58 L |
16989 | -muse-unaligned-vector-move\n\ |
16990 | encode aligned vector move as unaligned vector move\n")); | |
16991 | fprintf (stream, _("\ | |
7a6a03c4 | 16992 | -msse-check=[none|error|warning] (default: none)\n\ |
daf50ae7 L |
16993 | check SSE instructions\n")); |
16994 | fprintf (stream, _("\ | |
7c5c05ef | 16995 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
16996 | check operand combinations for validity\n")); |
16997 | fprintf (stream, _("\ | |
7c5c05ef L |
16998 | -mavxscalar=[128|256] (default: 128)\n\ |
16999 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
17000 | length\n")); |
17001 | fprintf (stream, _("\ | |
03751133 L |
17002 | -mvexwig=[0|1] (default: 0)\n\ |
17003 | encode VEX instructions with specific VEX.W value\n\ | |
17004 | for VEX.W bit ignored instructions\n")); | |
17005 | fprintf (stream, _("\ | |
7c5c05ef L |
17006 | -mevexlig=[128|256|512] (default: 128)\n\ |
17007 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
17008 | length\n")); |
17009 | fprintf (stream, _("\ | |
7c5c05ef L |
17010 | -mevexwig=[0|1] (default: 0)\n\ |
17011 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
17012 | for EVEX.W bit ignored instructions\n")); |
17013 | fprintf (stream, _("\ | |
7c5c05ef | 17014 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
17015 | encode EVEX instructions with specific EVEX.RC value\n\ |
17016 | for SAE-only ignored instructions\n")); | |
17017 | fprintf (stream, _("\ | |
7c5c05ef L |
17018 | -mmnemonic=[att|intel] ")); |
17019 | if (SYSV386_COMPAT) | |
17020 | fprintf (stream, _("(default: att)\n")); | |
17021 | else | |
17022 | fprintf (stream, _("(default: intel)\n")); | |
17023 | fprintf (stream, _("\ | |
7d3182d6 | 17024 | use AT&T/Intel mnemonic (AT&T syntax only)\n")); |
ba104c83 | 17025 | fprintf (stream, _("\ |
7c5c05ef L |
17026 | -msyntax=[att|intel] (default: att)\n\ |
17027 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
17028 | fprintf (stream, _("\ |
17029 | -mindex-reg support pseudo index registers\n")); | |
17030 | fprintf (stream, _("\ | |
17031 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
17032 | fprintf (stream, _("\ | |
7e8b059b | 17033 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 17034 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
17035 | fprintf (stream, _("\ |
17036 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
17037 | fprintf (stream, _("\ |
17038 | -mx86-used-note=[no|yes] ")); | |
17039 | if (DEFAULT_X86_USED_NOTE) | |
17040 | fprintf (stream, _("(default: yes)\n")); | |
17041 | else | |
17042 | fprintf (stream, _("(default: no)\n")); | |
17043 | fprintf (stream, _("\ | |
17044 | generate x86 used ISA and feature properties\n")); | |
17045 | #endif | |
17046 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
17047 | fprintf (stream, _("\ |
17048 | -mbig-obj generate big object files\n")); | |
17049 | #endif | |
d022bddd | 17050 | fprintf (stream, _("\ |
7c5c05ef | 17051 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 17052 | strip all lock prefixes\n")); |
5db04b09 | 17053 | fprintf (stream, _("\ |
7c5c05ef | 17054 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
17055 | encode lfence, mfence and sfence as\n\ |
17056 | lock addl $0x0, (%%{re}sp)\n")); | |
17057 | fprintf (stream, _("\ | |
7c5c05ef L |
17058 | -mrelax-relocations=[no|yes] ")); |
17059 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
17060 | fprintf (stream, _("(default: yes)\n")); | |
17061 | else | |
17062 | fprintf (stream, _("(default: no)\n")); | |
17063 | fprintf (stream, _("\ | |
0cb4071e L |
17064 | generate relax relocations\n")); |
17065 | fprintf (stream, _("\ | |
e379e5f3 L |
17066 | -malign-branch-boundary=NUM (default: 0)\n\ |
17067 | align branches within NUM byte boundary\n")); | |
17068 | fprintf (stream, _("\ | |
17069 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
17070 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
17071 | indirect\n\ | |
17072 | specify types of branches to align\n")); | |
17073 | fprintf (stream, _("\ | |
17074 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
17075 | align branches with NUM prefixes per instruction\n")); | |
17076 | fprintf (stream, _("\ | |
76cf450b L |
17077 | -mbranches-within-32B-boundaries\n\ |
17078 | align branches within 32 byte boundary\n")); | |
17079 | fprintf (stream, _("\ | |
ae531041 L |
17080 | -mlfence-after-load=[no|yes] (default: no)\n\ |
17081 | generate lfence after load\n")); | |
17082 | fprintf (stream, _("\ | |
17083 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
17084 | generate lfence before indirect near branch\n")); | |
17085 | fprintf (stream, _("\ | |
a09f656b | 17086 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
17087 | generate lfence before ret\n")); |
17088 | fprintf (stream, _("\ | |
7c5c05ef | 17089 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
17090 | fprintf (stream, _("\ |
17091 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
17092 | } |
17093 | ||
3e73aa7c | 17094 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 17095 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 17096 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
17097 | |
17098 | /* Pick the target format to use. */ | |
17099 | ||
47926f60 | 17100 | const char * |
e3bb37b5 | 17101 | i386_target_format (void) |
252b5132 | 17102 | { |
d34049e8 | 17103 | if (startswith (default_arch, "x86_64")) |
351f65ca L |
17104 | { |
17105 | update_code_flag (CODE_64BIT, 1); | |
071c5d81 | 17106 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
351f65ca | 17107 | if (default_arch[6] == '\0') |
7f56bc95 | 17108 | x86_elf_abi = X86_64_ABI; |
351f65ca | 17109 | else |
7f56bc95 | 17110 | x86_elf_abi = X86_64_X32_ABI; |
071c5d81 | 17111 | #endif |
351f65ca | 17112 | } |
3e73aa7c | 17113 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 17114 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
17115 | else if (!strcmp (default_arch, "iamcu")) |
17116 | { | |
17117 | update_code_flag (CODE_32BIT, 1); | |
17118 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
17119 | { | |
17120 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
17121 | cpu_arch_name = "iamcu"; | |
d92c7521 | 17122 | free (cpu_sub_arch_name); |
5197d474 L |
17123 | cpu_sub_arch_name = NULL; |
17124 | cpu_arch_flags = iamcu_flags; | |
17125 | cpu_arch_isa = PROCESSOR_IAMCU; | |
17126 | cpu_arch_isa_flags = iamcu_flags; | |
17127 | if (!cpu_arch_tune_set) | |
fb263707 | 17128 | cpu_arch_tune = PROCESSOR_IAMCU; |
5197d474 | 17129 | } |
8d471ec1 | 17130 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
17131 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
17132 | cpu_arch_name); | |
17133 | } | |
3e73aa7c | 17134 | else |
2b5d6a91 | 17135 | as_fatal (_("unknown architecture")); |
89507696 | 17136 | |
c7defc53 IB |
17137 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
17138 | if (IS_ELF && flag_synth_cfi && x86_elf_abi != X86_64_ABI) | |
17139 | as_fatal (_("SCFI is not supported for this ABI")); | |
17140 | #endif | |
17141 | ||
89507696 | 17142 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
ae89daec | 17143 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 17144 | |
252b5132 RH |
17145 | switch (OUTPUT_FLAVOR) |
17146 | { | |
9384f2ff | 17147 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 17148 | case bfd_target_aout_flavour: |
47926f60 | 17149 | return AOUT_TARGET_FORMAT; |
4c63da97 | 17150 | #endif |
9384f2ff AM |
17151 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
17152 | # if defined (TE_PE) || defined (TE_PEP) | |
17153 | case bfd_target_coff_flavour: | |
167ad85b | 17154 | if (flag_code == CODE_64BIT) |
eb19308f JB |
17155 | { |
17156 | object_64bit = 1; | |
17157 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
17158 | } | |
17159 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; | |
9384f2ff | 17160 | # elif defined (TE_GO32) |
0561d57c JK |
17161 | case bfd_target_coff_flavour: |
17162 | return "coff-go32"; | |
9384f2ff | 17163 | # else |
252b5132 RH |
17164 | case bfd_target_coff_flavour: |
17165 | return "coff-i386"; | |
9384f2ff | 17166 | # endif |
4c63da97 | 17167 | #endif |
3e73aa7c | 17168 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 17169 | case bfd_target_elf_flavour: |
3e73aa7c | 17170 | { |
351f65ca L |
17171 | const char *format; |
17172 | ||
17173 | switch (x86_elf_abi) | |
4fa24527 | 17174 | { |
351f65ca L |
17175 | default: |
17176 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
17177 | #ifndef TE_SOLARIS |
17178 | tls_get_addr = "___tls_get_addr"; | |
17179 | #endif | |
351f65ca | 17180 | break; |
7f56bc95 | 17181 | case X86_64_ABI: |
351f65ca | 17182 | use_rela_relocations = 1; |
4fa24527 | 17183 | object_64bit = 1; |
e379e5f3 L |
17184 | #ifndef TE_SOLARIS |
17185 | tls_get_addr = "__tls_get_addr"; | |
17186 | #endif | |
351f65ca L |
17187 | format = ELF_TARGET_FORMAT64; |
17188 | break; | |
7f56bc95 | 17189 | case X86_64_X32_ABI: |
4fa24527 | 17190 | use_rela_relocations = 1; |
351f65ca | 17191 | object_64bit = 1; |
e379e5f3 L |
17192 | #ifndef TE_SOLARIS |
17193 | tls_get_addr = "__tls_get_addr"; | |
17194 | #endif | |
862be3fb | 17195 | disallow_64bit_reloc = 1; |
351f65ca L |
17196 | format = ELF_TARGET_FORMAT32; |
17197 | break; | |
4fa24527 | 17198 | } |
c085ab00 | 17199 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
17200 | { |
17201 | if (x86_elf_abi != I386_ABI) | |
17202 | as_fatal (_("Intel MCU is 32bit only")); | |
17203 | return ELF_TARGET_IAMCU_FORMAT; | |
17204 | } | |
8a9036a4 | 17205 | else |
351f65ca | 17206 | return format; |
3e73aa7c | 17207 | } |
e57f8c65 TG |
17208 | #endif |
17209 | #if defined (OBJ_MACH_O) | |
17210 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
17211 | if (flag_code == CODE_64BIT) |
17212 | { | |
17213 | use_rela_relocations = 1; | |
17214 | object_64bit = 1; | |
17215 | return "mach-o-x86-64"; | |
17216 | } | |
17217 | else | |
17218 | return "mach-o-i386"; | |
4c63da97 | 17219 | #endif |
252b5132 RH |
17220 | default: |
17221 | abort (); | |
17222 | return NULL; | |
17223 | } | |
17224 | } | |
17225 | ||
47926f60 | 17226 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 17227 | \f |
252b5132 | 17228 | symbolS * |
7016a5d5 | 17229 | md_undefined_symbol (char *name) |
252b5132 | 17230 | { |
18dc2407 ILT |
17231 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
17232 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
17233 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
17234 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
17235 | { |
17236 | if (!GOT_symbol) | |
17237 | { | |
17238 | if (symbol_find (name)) | |
17239 | as_bad (_("GOT already in symbol table")); | |
17240 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 17241 | &zero_address_frag, 0); |
24eab124 AM |
17242 | }; |
17243 | return GOT_symbol; | |
17244 | } | |
252b5132 RH |
17245 | return 0; |
17246 | } | |
17247 | ||
071c5d81 | 17248 | #if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) |
252b5132 | 17249 | /* Round up a section size to the appropriate boundary. */ |
47926f60 | 17250 | |
252b5132 | 17251 | valueT |
071c5d81 | 17252 | md_section_align (segT segment, valueT size) |
252b5132 | 17253 | { |
4c63da97 AM |
17254 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) |
17255 | { | |
17256 | /* For a.out, force the section size to be aligned. If we don't do | |
17257 | this, BFD will align it for us, but it will not write out the | |
17258 | final bytes of the section. This may be a bug in BFD, but it is | |
17259 | easier to fix it here since that is how the other a.out targets | |
17260 | work. */ | |
17261 | int align; | |
17262 | ||
fd361982 | 17263 | align = bfd_section_alignment (segment); |
8d3842cd | 17264 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 17265 | } |
252b5132 RH |
17266 | |
17267 | return size; | |
17268 | } | |
071c5d81 | 17269 | #endif |
252b5132 RH |
17270 | |
17271 | /* On the i386, PC-relative offsets are relative to the start of the | |
17272 | next instruction. That is, the address of the offset, plus its | |
17273 | size, since the offset is always the last part of the insn. */ | |
17274 | ||
17275 | long | |
e3bb37b5 | 17276 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
17277 | { |
17278 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
17279 | } | |
17280 | ||
d4064aad | 17281 | #ifdef OBJ_AOUT |
252b5132 RH |
17282 | |
17283 | static void | |
e3bb37b5 | 17284 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17285 | { |
29b0f896 | 17286 | int temp; |
252b5132 RH |
17287 | |
17288 | temp = get_absolute_expression (); | |
17289 | subseg_set (bss_section, (subsegT) temp); | |
17290 | demand_empty_rest_of_line (); | |
17291 | } | |
17292 | ||
17293 | #endif | |
17294 | ||
e379e5f3 L |
17295 | /* Remember constant directive. */ |
17296 | ||
17297 | void | |
17298 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
17299 | { | |
b5482fe5 JB |
17300 | struct last_insn *last_insn |
17301 | = &seg_info(now_seg)->tc_segment_info_data.last_insn; | |
17302 | ||
ce69d081 | 17303 | if (bfd_section_flags (now_seg) & SEC_CODE) |
e379e5f3 | 17304 | { |
b5482fe5 JB |
17305 | last_insn->kind = last_insn_directive; |
17306 | last_insn->name = "constant directive"; | |
17307 | last_insn->file = as_where (&last_insn->line); | |
e379e5f3 L |
17308 | } |
17309 | } | |
17310 | ||
3abbafc2 | 17311 | int |
e3bb37b5 | 17312 | i386_validate_fix (fixS *fixp) |
252b5132 | 17313 | { |
e52a16f2 JB |
17314 | if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section) |
17315 | { | |
17316 | reloc_howto_type *howto; | |
17317 | ||
17318 | howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
17319 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17320 | _("invalid %s relocation against register"), | |
17321 | howto ? howto->name : "<unknown>"); | |
17322 | return 0; | |
17323 | } | |
17324 | ||
3abbafc2 JB |
17325 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
17326 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
17327 | || fixp->fx_r_type == BFD_RELOC_SIZE64) | |
17328 | return IS_ELF && fixp->fx_addsy | |
17329 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
17330 | || S_IS_EXTERNAL (fixp->fx_addsy)); | |
a533c8df | 17331 | |
5bc71c2a L |
17332 | /* BFD_RELOC_X86_64_GOTTPOFF: |
17333 | 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTTPOFF | |
17334 | 2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF | |
17335 | BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
17336 | 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC | |
17337 | BFD_RELOC_32_PCREL: | |
17338 | 1. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX | |
17339 | 2. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX | |
17340 | 3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX | |
17341 | 4. else -> BFD_RELOC_X86_64_GOTPCREL | |
17342 | */ | |
17343 | if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF) | |
a533c8df | 17344 | { |
5bc71c2a | 17345 | if (fixp->fx_tcbit) |
a533c8df | 17346 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTTPOFF; |
5bc71c2a L |
17347 | else if (fixp->fx_tcbit2) |
17348 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_6_GOTTPOFF; | |
a533c8df | 17349 | } |
5bc71c2a L |
17350 | else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
17351 | && fixp->fx_tcbit) | |
17352 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC; | |
3abbafc2 JB |
17353 | #endif |
17354 | ||
02a86693 | 17355 | if (fixp->fx_subsy) |
252b5132 | 17356 | { |
02a86693 | 17357 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 17358 | { |
02a86693 L |
17359 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
17360 | { | |
17361 | if (!object_64bit) | |
17362 | abort (); | |
17363 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
5bc71c2a L |
17364 | if (fixp->fx_tcbit) |
17365 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCRELX; | |
17366 | else if (fixp->fx_tcbit2) | |
17367 | fixp->fx_r_type = BFD_RELOC_X86_64_REX_GOTPCRELX; | |
17368 | else if (fixp->fx_tcbit3) | |
17369 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX; | |
02a86693 L |
17370 | else |
17371 | #endif | |
17372 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
17373 | } | |
d6ab8113 | 17374 | else |
02a86693 L |
17375 | { |
17376 | if (!object_64bit) | |
17377 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
17378 | else | |
17379 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
17380 | } | |
17381 | fixp->fx_subsy = 0; | |
23df1078 | 17382 | } |
252b5132 | 17383 | } |
02a86693 | 17384 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 17385 | else |
02a86693 | 17386 | { |
2585b7a5 L |
17387 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
17388 | to section. Since PLT32 relocation must be against symbols, | |
17389 | turn such PLT32 relocation into PC32 relocation. */ | |
17390 | if (fixp->fx_addsy | |
17391 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
17392 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
17393 | && symbol_section_p (fixp->fx_addsy)) | |
17394 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
17395 | if (!object_64bit) | |
17396 | { | |
17397 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
17398 | && fixp->fx_tcbit2) | |
17399 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
17400 | } | |
02a86693 L |
17401 | } |
17402 | #endif | |
3abbafc2 JB |
17403 | |
17404 | return 1; | |
252b5132 RH |
17405 | } |
17406 | ||
252b5132 | 17407 | arelent * |
7016a5d5 | 17408 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17409 | { |
17410 | arelent *rel; | |
17411 | bfd_reloc_code_real_type code; | |
17412 | ||
17413 | switch (fixp->fx_r_type) | |
17414 | { | |
8ce3d284 | 17415 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3abbafc2 JB |
17416 | symbolS *sym; |
17417 | ||
8fd4256d L |
17418 | case BFD_RELOC_SIZE32: |
17419 | case BFD_RELOC_SIZE64: | |
3abbafc2 JB |
17420 | if (fixp->fx_addsy |
17421 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)) | |
17422 | && (!fixp->fx_subsy | |
17423 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)))) | |
17424 | sym = fixp->fx_addsy; | |
17425 | else if (fixp->fx_subsy | |
17426 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)) | |
17427 | && (!fixp->fx_addsy | |
17428 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)))) | |
17429 | sym = fixp->fx_subsy; | |
17430 | else | |
17431 | sym = NULL; | |
17432 | if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym)) | |
8fd4256d L |
17433 | { |
17434 | /* Resolve size relocation against local symbol to size of | |
17435 | the symbol plus addend. */ | |
3abbafc2 | 17436 | valueT value = S_GET_SIZE (sym); |
44f87162 | 17437 | |
3abbafc2 JB |
17438 | if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) |
17439 | value = bfd_section_size (S_GET_SEGMENT (sym)); | |
17440 | if (sym == fixp->fx_subsy) | |
17441 | { | |
17442 | value = -value; | |
17443 | if (fixp->fx_addsy) | |
17444 | value += S_GET_VALUE (fixp->fx_addsy); | |
17445 | } | |
17446 | else if (fixp->fx_subsy) | |
17447 | value -= S_GET_VALUE (fixp->fx_subsy); | |
44f87162 | 17448 | value += fixp->fx_offset; |
8fd4256d | 17449 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
d965814f | 17450 | && object_64bit |
8fd4256d L |
17451 | && !fits_in_unsigned_long (value)) |
17452 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17453 | _("symbol size computation overflow")); | |
17454 | fixp->fx_addsy = NULL; | |
17455 | fixp->fx_subsy = NULL; | |
17456 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
17457 | return NULL; | |
17458 | } | |
3abbafc2 JB |
17459 | if (!fixp->fx_addsy || fixp->fx_subsy) |
17460 | { | |
17461 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17462 | "unsupported expression involving @size"); | |
17463 | return NULL; | |
17464 | } | |
8ce3d284 | 17465 | #endif |
1a0670f3 | 17466 | /* Fall through. */ |
8fd4256d | 17467 | |
3e73aa7c JH |
17468 | case BFD_RELOC_X86_64_PLT32: |
17469 | case BFD_RELOC_X86_64_GOT32: | |
17470 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
17471 | case BFD_RELOC_X86_64_GOTPCRELX: |
17472 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
3d5a60de | 17473 | case BFD_RELOC_X86_64_CODE_4_GOTPCRELX: |
252b5132 RH |
17474 | case BFD_RELOC_386_PLT32: |
17475 | case BFD_RELOC_386_GOT32: | |
02a86693 | 17476 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
17477 | case BFD_RELOC_386_GOTOFF: |
17478 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
17479 | case BFD_RELOC_386_TLS_GD: |
17480 | case BFD_RELOC_386_TLS_LDM: | |
17481 | case BFD_RELOC_386_TLS_LDO_32: | |
17482 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
17483 | case BFD_RELOC_386_TLS_IE: |
17484 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
17485 | case BFD_RELOC_386_TLS_LE_32: |
17486 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
17487 | case BFD_RELOC_386_TLS_GOTDESC: |
17488 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
17489 | case BFD_RELOC_X86_64_TLSGD: |
17490 | case BFD_RELOC_X86_64_TLSLD: | |
17491 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 17492 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 | 17493 | case BFD_RELOC_X86_64_GOTTPOFF: |
a533c8df | 17494 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
5bc71c2a | 17495 | case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: |
bffbf940 | 17496 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 JB |
17497 | case BFD_RELOC_X86_64_TPOFF64: |
17498 | case BFD_RELOC_X86_64_GOTOFF64: | |
17499 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
17500 | case BFD_RELOC_X86_64_GOT64: |
17501 | case BFD_RELOC_X86_64_GOTPCREL64: | |
17502 | case BFD_RELOC_X86_64_GOTPC64: | |
17503 | case BFD_RELOC_X86_64_GOTPLT64: | |
17504 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 | 17505 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 17506 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
67a4f2b7 | 17507 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
252b5132 RH |
17508 | case BFD_RELOC_RVA: |
17509 | case BFD_RELOC_VTABLE_ENTRY: | |
17510 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
17511 | #ifdef TE_PE |
17512 | case BFD_RELOC_32_SECREL: | |
145667f8 | 17513 | case BFD_RELOC_16_SECIDX: |
6482c264 | 17514 | #endif |
252b5132 RH |
17515 | code = fixp->fx_r_type; |
17516 | break; | |
dbbaec26 L |
17517 | case BFD_RELOC_X86_64_32S: |
17518 | if (!fixp->fx_pcrel) | |
17519 | { | |
17520 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
17521 | code = fixp->fx_r_type; | |
17522 | break; | |
17523 | } | |
1a0670f3 | 17524 | /* Fall through. */ |
252b5132 | 17525 | default: |
93382f6d | 17526 | if (fixp->fx_pcrel) |
252b5132 | 17527 | { |
93382f6d AM |
17528 | switch (fixp->fx_size) |
17529 | { | |
17530 | default: | |
b091f402 AM |
17531 | as_bad_where (fixp->fx_file, fixp->fx_line, |
17532 | _("can not do %d byte pc-relative relocation"), | |
17533 | fixp->fx_size); | |
93382f6d AM |
17534 | code = BFD_RELOC_32_PCREL; |
17535 | break; | |
17536 | case 1: code = BFD_RELOC_8_PCREL; break; | |
17537 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 17538 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
17539 | #ifdef BFD64 |
17540 | case 8: code = BFD_RELOC_64_PCREL; break; | |
17541 | #endif | |
93382f6d AM |
17542 | } |
17543 | } | |
17544 | else | |
17545 | { | |
17546 | switch (fixp->fx_size) | |
17547 | { | |
17548 | default: | |
b091f402 AM |
17549 | as_bad_where (fixp->fx_file, fixp->fx_line, |
17550 | _("can not do %d byte relocation"), | |
17551 | fixp->fx_size); | |
93382f6d AM |
17552 | code = BFD_RELOC_32; |
17553 | break; | |
17554 | case 1: code = BFD_RELOC_8; break; | |
17555 | case 2: code = BFD_RELOC_16; break; | |
17556 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 17557 | #ifdef BFD64 |
3e73aa7c | 17558 | case 8: code = BFD_RELOC_64; break; |
937149dd | 17559 | #endif |
93382f6d | 17560 | } |
252b5132 RH |
17561 | } |
17562 | break; | |
17563 | } | |
252b5132 | 17564 | |
d182319b JB |
17565 | if ((code == BFD_RELOC_32 |
17566 | || code == BFD_RELOC_32_PCREL | |
17567 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
17568 | && GOT_symbol |
17569 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 17570 | { |
4fa24527 | 17571 | if (!object_64bit) |
d6ab8113 JB |
17572 | code = BFD_RELOC_386_GOTPC; |
17573 | else | |
17574 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 17575 | } |
7b81dfbb AJ |
17576 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
17577 | && GOT_symbol | |
17578 | && fixp->fx_addsy == GOT_symbol) | |
17579 | { | |
17580 | code = BFD_RELOC_X86_64_GOTPC64; | |
17581 | } | |
252b5132 | 17582 | |
add39d23 TS |
17583 | rel = XNEW (arelent); |
17584 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 17585 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
17586 | |
17587 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 17588 | |
3e73aa7c JH |
17589 | if (!use_rela_relocations) |
17590 | { | |
17591 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
17592 | vtable entry to be used in the relocation's section offset. */ | |
17593 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17594 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
17595 | #if defined (OBJ_COFF) && defined (TE_PE) |
17596 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
17597 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
17598 | else | |
17599 | #endif | |
c6682705 | 17600 | rel->addend = 0; |
3e73aa7c JH |
17601 | } |
17602 | /* Use the rela in 64bit mode. */ | |
252b5132 | 17603 | else |
3e73aa7c | 17604 | { |
862be3fb L |
17605 | if (disallow_64bit_reloc) |
17606 | switch (code) | |
17607 | { | |
862be3fb L |
17608 | case BFD_RELOC_X86_64_DTPOFF64: |
17609 | case BFD_RELOC_X86_64_TPOFF64: | |
17610 | case BFD_RELOC_64_PCREL: | |
17611 | case BFD_RELOC_X86_64_GOTOFF64: | |
17612 | case BFD_RELOC_X86_64_GOT64: | |
17613 | case BFD_RELOC_X86_64_GOTPCREL64: | |
17614 | case BFD_RELOC_X86_64_GOTPC64: | |
17615 | case BFD_RELOC_X86_64_GOTPLT64: | |
17616 | case BFD_RELOC_X86_64_PLTOFF64: | |
17617 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17618 | _("cannot represent relocation type %s in x32 mode"), | |
17619 | bfd_get_reloc_code_name (code)); | |
17620 | break; | |
17621 | default: | |
17622 | break; | |
17623 | } | |
17624 | ||
062cd5e7 AS |
17625 | if (!fixp->fx_pcrel) |
17626 | rel->addend = fixp->fx_offset; | |
17627 | else | |
17628 | switch (code) | |
17629 | { | |
17630 | case BFD_RELOC_X86_64_PLT32: | |
17631 | case BFD_RELOC_X86_64_GOT32: | |
17632 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
17633 | case BFD_RELOC_X86_64_GOTPCRELX: |
17634 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
3d5a60de | 17635 | case BFD_RELOC_X86_64_CODE_4_GOTPCRELX: |
bffbf940 JJ |
17636 | case BFD_RELOC_X86_64_TLSGD: |
17637 | case BFD_RELOC_X86_64_TLSLD: | |
17638 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 17639 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
5bc71c2a | 17640 | case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: |
67a4f2b7 | 17641 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 17642 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
67a4f2b7 | 17643 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
062cd5e7 AS |
17644 | rel->addend = fixp->fx_offset - fixp->fx_size; |
17645 | break; | |
17646 | default: | |
17647 | rel->addend = (section->vma | |
17648 | - fixp->fx_size | |
17649 | + fixp->fx_addnumber | |
17650 | + md_pcrel_from (fixp)); | |
17651 | break; | |
17652 | } | |
3e73aa7c JH |
17653 | } |
17654 | ||
252b5132 RH |
17655 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
17656 | if (rel->howto == NULL) | |
17657 | { | |
17658 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 17659 | _("cannot represent relocation type %s"), |
252b5132 RH |
17660 | bfd_get_reloc_code_name (code)); |
17661 | /* Set howto to a garbage value so that we can keep going. */ | |
17662 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 17663 | gas_assert (rel->howto != NULL); |
252b5132 RH |
17664 | } |
17665 | ||
17666 | return rel; | |
17667 | } | |
17668 | ||
ee86248c | 17669 | #include "tc-i386-intel.c" |
54cfded0 | 17670 | |
a60de03c JB |
17671 | void |
17672 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 17673 | { |
a60de03c JB |
17674 | int saved_naked_reg; |
17675 | char saved_register_dot; | |
54cfded0 | 17676 | |
a60de03c JB |
17677 | saved_naked_reg = allow_naked_reg; |
17678 | allow_naked_reg = 1; | |
17679 | saved_register_dot = register_chars['.']; | |
17680 | register_chars['.'] = '.'; | |
17681 | allow_pseudo_reg = 1; | |
17682 | expression_and_evaluate (exp); | |
17683 | allow_pseudo_reg = 0; | |
17684 | register_chars['.'] = saved_register_dot; | |
17685 | allow_naked_reg = saved_naked_reg; | |
17686 | ||
e96d56a1 | 17687 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 17688 | { |
066673f6 | 17689 | exp->X_op = O_illegal; |
a60de03c JB |
17690 | if ((addressT) exp->X_add_number < i386_regtab_size) |
17691 | { | |
a60de03c | 17692 | exp->X_add_number = i386_regtab[exp->X_add_number] |
fabb73d1 | 17693 | .dw2_regnum[object_64bit]; |
066673f6 JB |
17694 | if (exp->X_add_number != Dw2Inval) |
17695 | exp->X_op = O_constant; | |
a60de03c | 17696 | } |
54cfded0 | 17697 | } |
54cfded0 AM |
17698 | } |
17699 | ||
17700 | void | |
17701 | tc_x86_frame_initial_instructions (void) | |
17702 | { | |
fabb73d1 | 17703 | cfi_add_CFA_def_cfa (object_64bit ? REG_SP : 4, -x86_cie_data_alignment); |
61ff971f | 17704 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
54cfded0 | 17705 | } |
d2b2c203 | 17706 | |
d7921315 L |
17707 | int |
17708 | x86_dwarf2_addr_size (void) | |
17709 | { | |
17710 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
17711 | if (x86_elf_abi == X86_64_X32_ABI) | |
17712 | return 4; | |
17713 | #endif | |
17714 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
17715 | } | |
17716 | ||
071c5d81 JB |
17717 | #ifdef TE_PE |
17718 | void | |
17719 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
17720 | { | |
17721 | expressionS exp; | |
17722 | ||
17723 | exp.X_op = O_secrel; | |
17724 | exp.X_add_symbol = symbol; | |
17725 | exp.X_add_number = 0; | |
17726 | emit_expr (&exp, size); | |
17727 | } | |
17728 | #endif | |
17729 | ||
17730 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
d2b2c203 DJ |
17731 | int |
17732 | i386_elf_section_type (const char *str, size_t len) | |
17733 | { | |
17734 | if (flag_code == CODE_64BIT | |
17735 | && len == sizeof ("unwind") - 1 | |
d34049e8 | 17736 | && startswith (str, "unwind")) |
d2b2c203 DJ |
17737 | return SHT_X86_64_UNWIND; |
17738 | ||
17739 | return -1; | |
17740 | } | |
bb41ade5 | 17741 | |
da374e94 JB |
17742 | void |
17743 | i386_elf_section_change_hook (void) | |
17744 | { | |
17745 | struct i386_segment_info *info = &seg_info(now_seg)->tc_segment_info_data; | |
17746 | struct i386_segment_info *curr, *prev; | |
17747 | ||
17748 | if (info->subseg == now_subseg) | |
17749 | return; | |
17750 | ||
17751 | /* Find the (or make a) list entry to save state into. */ | |
17752 | for (prev = info; (curr = prev->next) != NULL; prev = curr) | |
17753 | if (curr->subseg == info->subseg) | |
17754 | break; | |
17755 | if (!curr) | |
17756 | { | |
fddee222 | 17757 | curr = notes_alloc (sizeof (*curr)); |
da374e94 JB |
17758 | curr->subseg = info->subseg; |
17759 | curr->next = NULL; | |
17760 | prev->next = curr; | |
17761 | } | |
17762 | curr->last_insn = info->last_insn; | |
17763 | ||
17764 | /* Find the list entry to load state from. */ | |
17765 | for (curr = info->next; curr; curr = curr->next) | |
17766 | if (curr->subseg == now_subseg) | |
17767 | break; | |
17768 | if (curr) | |
17769 | info->last_insn = curr->last_insn; | |
17770 | else | |
17771 | memset (&info->last_insn, 0, sizeof (info->last_insn)); | |
17772 | info->subseg = now_subseg; | |
17773 | } | |
17774 | ||
ad5fec3b EB |
17775 | #ifdef TE_SOLARIS |
17776 | void | |
17777 | i386_solaris_fix_up_eh_frame (segT sec) | |
17778 | { | |
17779 | if (flag_code == CODE_64BIT) | |
17780 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
17781 | } | |
17782 | #endif | |
17783 | ||
3b22753a L |
17784 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ |
17785 | ||
01e1a5bc | 17786 | bfd_vma |
6d4af3c2 | 17787 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
17788 | { |
17789 | if (flag_code == CODE_64BIT) | |
17790 | { | |
17791 | if (letter == 'l') | |
17792 | return SHF_X86_64_LARGE; | |
17793 | ||
8f3bae45 | 17794 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 17795 | } |
3b22753a | 17796 | else |
8f3bae45 | 17797 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
17798 | return -1; |
17799 | } | |
17800 | ||
3b22753a L |
17801 | static void |
17802 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
17803 | { | |
17804 | if (flag_code != CODE_64BIT) | |
17805 | { | |
17806 | s_comm_internal (0, elf_common_parse); | |
17807 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
17808 | } | |
17809 | else | |
17810 | { | |
17811 | static segT lbss_section; | |
17812 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
17813 | asection *saved_bss_section = bss_section; | |
17814 | ||
17815 | if (lbss_section == NULL) | |
17816 | { | |
17817 | flagword applicable; | |
17818 | segT seg = now_seg; | |
17819 | subsegT subseg = now_subseg; | |
17820 | ||
17821 | /* The .lbss section is for local .largecomm symbols. */ | |
17822 | lbss_section = subseg_new (".lbss", 0); | |
17823 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 17824 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
17825 | seg_info (lbss_section)->bss = 1; |
17826 | ||
17827 | subseg_set (seg, subseg); | |
17828 | } | |
17829 | ||
17830 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
17831 | bss_section = lbss_section; | |
17832 | ||
17833 | s_comm_internal (0, elf_common_parse); | |
17834 | ||
17835 | elf_com_section_ptr = saved_com_section_ptr; | |
17836 | bss_section = saved_bss_section; | |
17837 | } | |
17838 | } | |
17839 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |