]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - gas/config/tc-i386.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
MIPS/BFD: Report `bfd_reloc_outofrange' errors as such
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
d3ce72d0 176static const insn_template *match_template (void);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132
RH		 328
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes;
332 unsigned char prefix[MAX_PREFIXES];
333
334 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 335 addressing modes of this insn are encoded. */
252b5132 336 modrm_byte rm;
3e73aa7c 337 rex_byte rex;
43234a1e 338 rex_byte vrex;
252b5132 339 sib_byte sib;
c0f3af97 340 vex_prefix vex;
b6169b20 341
43234a1e
L		 342 /* Masking attributes. */
343 struct Mask_Operation *mask;
344
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation *rounding;
347
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation *broadcast;
350
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift;
353
b6169b20 354 /* Swap operand in encoding. */
4473e004 355 unsigned int swap_operand;
891edac4 356
a501d77e
L		 357 /* Prefer 8bit or 32bit displacement in encoding. */
358 enum
359 {
360 disp_encoding_default = 0,
361 disp_encoding_8bit,
362 disp_encoding_32bit
363 } disp_encoding;
f8a5c266 364
d5de92cf
L		 365 /* REP prefix. */
366 const char *rep_prefix;
367
165de32a
L		 368 /* HLE prefix. */
369 const char *hle_prefix;
42164a71 370
7e8b059b
L		 371 /* Have BND prefix. */
372 const char *bnd_prefix;
373
43234a1e
L		 374 /* Need VREX to support upper 16 registers. */
375 int need_vrex;
376
891edac4 377 /* Error message. */
a65babc9 378 enum i386_error error;
252b5132
RH		 379 };
380
381typedef struct _i386_insn i386_insn;
382
43234a1e
L		 383/* Link RC type with corresponding string, that'll be looked for in
384 asm. */
385struct RC_name
386{
387 enum rc_type type;
388 const char *name;
389 unsigned int len;
390};
391
392static const struct RC_name RC_NamesTable[] =
393{
394 { rne, STRING_COMMA_LEN ("rn-sae") },
395 { rd, STRING_COMMA_LEN ("rd-sae") },
396 { ru, STRING_COMMA_LEN ("ru-sae") },
397 { rz, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly, STRING_COMMA_LEN ("sae") },
399};
400
252b5132
RH		 401/* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 403const char extra_symbol_chars[] = "*%-([{"
252b5132 404#ifdef LEX_AT
32137342
NC		 405 "@"
406#endif
407#ifdef LEX_QM
408 "?"
252b5132 409#endif
32137342 410 ;
252b5132 411
29b0f896
AM		 412#if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 414 && !defined (TE_GNU) \
29b0f896 415 && !defined (TE_LINUX) \
8d63c93e
RM		 416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
29b0f896 418 && !defined (TE_FreeBSD) \
5b806d27 419 && !defined (TE_DragonFly) \
29b0f896 420 && !defined (TE_NetBSD)))
252b5132 421/* This array holds the chars that always start a comment. If the
b3b91714
AM		 422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424const char *i386_comment_chars = "#/";
425#define SVR4_COMMENT_CHARS 1
252b5132 426#define PREFIX_SEPARATOR '\\'
252b5132 427
b3b91714
AM		 428#else
429const char *i386_comment_chars = "#";
430#define PREFIX_SEPARATOR '/'
431#endif
432
252b5132
RH		 433/* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 437 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
252b5132 440 '/' isn't otherwise defined. */
b3b91714 441const char line_comment_chars[] = "#/";
252b5132 442
63a0b638 443const char line_separator_chars[] = ";";
252b5132 444
ce8a8b2f
AM		 445/* Chars that can be used to separate mant from exp in floating point
446 nums. */
252b5132
RH		 447const char EXP_CHARS[] = "eE";
448
ce8a8b2f
AM		 449/* Chars that mean this number is a floating point constant
450 As in 0f12.456
451 or 0d1.2345e12. */
252b5132
RH		 452const char FLT_CHARS[] = "fFdDxX";
453
ce8a8b2f 454/* Tables for lexical analysis. */
252b5132
RH		 455static char mnemonic_chars[256];
456static char register_chars[256];
457static char operand_chars[256];
458static char identifier_chars[256];
459static char digit_chars[256];
460
ce8a8b2f 461/* Lexical macros. */
252b5132
RH		 462#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463#define is_operand_char(x) (operand_chars[(unsigned char) x])
464#define is_register_char(x) (register_chars[(unsigned char) x])
465#define is_space_char(x) ((x) == ' ')
466#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467#define is_digit_char(x) (digit_chars[(unsigned char) x])
468
0234cb7c 469/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 470static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
471
472/* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
47926f60 475 assembler instruction). */
252b5132 476static char save_stack[32];
ce8a8b2f 477static char *save_stack_p;
252b5132
RH		 478#define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480#define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
482
47926f60 483/* The instruction we're assembling. */
252b5132
RH		 484static i386_insn i;
485
486/* Possible templates for current insn. */
487static const templates *current_templates;
488
31b2323c
L		 489/* Per instruction expressionS buffers: max displacements & immediates. */
490static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
491static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 492
47926f60 493/* Current operand we are working on. */
ee86248c 494static int this_operand = -1;
252b5132 495
3e73aa7c
JH		 496/* We support four different modes. FLAG_CODE variable is used to distinguish
497 these. */
498
499enum flag_code {
500 CODE_32BIT,
501 CODE_16BIT,
502 CODE_64BIT };
503
504static enum flag_code flag_code;
4fa24527 505static unsigned int object_64bit;
862be3fb 506static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 507static int use_rela_relocations = 0;
508
7af8ed2d
NC		 509#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
512
351f65ca
L		 513/* The ELF ABI to use. */
514enum x86_elf_abi
515{
516 I386_ABI,
7f56bc95
L		 517 X86_64_ABI,
518 X86_64_X32_ABI
351f65ca
L		 519};
520
521static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 522#endif
351f65ca 523
167ad85b
TG		 524#if defined (TE_PE) || defined (TE_PEP)
525/* Use big object file format. */
526static int use_big_obj = 0;
527#endif
528
8dcea932
L		 529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530/* 1 if generating code for a shared library. */
531static int shared = 0;
532#endif
533
47926f60
KH		 534/* 1 for intel syntax,
535 0 if att syntax. */
536static int intel_syntax = 0;
252b5132 537
1efbbeb4
L		 538/* 1 for intel mnemonic,
539 0 if att mnemonic. */
540static int intel_mnemonic = !SYSV386_COMPAT;
541
5209009a 542/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 543static int old_gcc = OLDGCC_COMPAT;
544
a60de03c
JB		 545/* 1 if pseudo registers are permitted. */
546static int allow_pseudo_reg = 0;
547
47926f60
KH		 548/* 1 if register prefix % not required. */
549static int allow_naked_reg = 0;
252b5132 550
7e8b059b
L		 551/* 1 if the assembler should add BND prefix for all control-tranferring
552 instructions supporting it, even if this prefix wasn't specified
553 explicitly. */
554static int add_bnd_prefix = 0;
555
ba104c83 556/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 557static int allow_index_reg = 0;
558
d022bddd
IT		 559/* 1 if the assembler should ignore LOCK prefix, even if it was
560 specified explicitly. */
561static int omit_lock_prefix = 0;
562
e4e00185
AS		 563/* 1 if the assembler should encode lfence, mfence, and sfence as
564 "lock addl $0, (%{re}sp)". */
565static int avoid_fence = 0;
566
0cb4071e
L		 567/* 1 if the assembler should generate relax relocations. */
568
569static int generate_relax_relocations
570 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
571
7bab8ab5 572static enum check_kind
daf50ae7 573 {
7bab8ab5
JB		 574 check_none = 0,
575 check_warning,
576 check_error
daf50ae7 577 }
7bab8ab5 578sse_check, operand_check = check_warning;
daf50ae7 579
2ca3ace5
L		 580/* Register prefix used for error message. */
581static const char *register_prefix = "%";
582
47926f60
KH		 583/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
584 leave, push, and pop instructions so that gcc has the same stack
585 frame as in 32 bit mode. */
586static char stackop_size = '\0';
eecb386c 587
12b55ccc
L		 588/* Non-zero to optimize code alignment. */
589int optimize_align_code = 1;
590
47926f60
KH		 591/* Non-zero to quieten some warnings. */
592static int quiet_warnings = 0;
a38cf1db 593
47926f60
KH		 594/* CPU name. */
595static const char *cpu_arch_name = NULL;
6305a203 596static char *cpu_sub_arch_name = NULL;
a38cf1db 597
47926f60 598/* CPU feature flags. */
40fb9820
L		 599static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
600
ccc9c027
L		 601/* If we have selected a cpu we are generating instructions for. */
602static int cpu_arch_tune_set = 0;
603
9103f4f4 604/* Cpu we are generating instructions for. */
fbf3f584 605enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 606
607/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 608static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 609
ccc9c027 610/* CPU instruction set architecture used. */
fbf3f584 611enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 612
9103f4f4 613/* CPU feature flags of instruction set architecture used. */
fbf3f584 614i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 615
fddf5b5b
AM		 616/* If set, conditional jumps are not automatically promoted to handle
617 larger than a byte offset. */
618static unsigned int no_cond_jump_promotion = 0;
619
c0f3af97
L		 620/* Encode SSE instructions with VEX prefix. */
621static unsigned int sse2avx;
622
539f890d
L		 623/* Encode scalar AVX instructions with specific vector length. */
624static enum
625 {
626 vex128 = 0,
627 vex256
628 } avxscalar;
629
43234a1e
L		 630/* Encode scalar EVEX LIG instructions with specific vector length. */
631static enum
632 {
633 evexl128 = 0,
634 evexl256,
635 evexl512
636 } evexlig;
637
638/* Encode EVEX WIG instructions with specific evex.w. */
639static enum
640 {
641 evexw0 = 0,
642 evexw1
643 } evexwig;
644
d3d3c6db
IT		 645/* Value to encode in EVEX RC bits, for SAE-only instructions. */
646static enum rc_type evexrcig = rne;
647
29b0f896 648/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 649static symbolS *GOT_symbol;
29b0f896 650
a4447b93
RH		 651/* The dwarf2 return column, adjusted for 32 or 64 bit. */
652unsigned int x86_dwarf2_return_column;
653
654/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
655int x86_cie_data_alignment;
656
252b5132 657/* Interface to relax_segment.
fddf5b5b
AM		 658 There are 3 major relax states for 386 jump insns because the
659 different types of jumps add different sizes to frags when we're
660 figuring out what sort of jump to choose to reach a given label. */
252b5132 661
47926f60 662/* Types. */
93c2a809
AM		 663#define UNCOND_JUMP 0
664#define COND_JUMP 1
665#define COND_JUMP86 2
fddf5b5b 666
47926f60 667/* Sizes. */
252b5132
RH		 668#define CODE16 1
669#define SMALL 0
29b0f896 670#define SMALL16 (SMALL | CODE16)
252b5132 671#define BIG 2
29b0f896 672#define BIG16 (BIG | CODE16)
252b5132
RH		 673
674#ifndef INLINE
675#ifdef __GNUC__
676#define INLINE __inline__
677#else
678#define INLINE
679#endif
680#endif
681
fddf5b5b
AM		 682#define ENCODE_RELAX_STATE(type, size) \
683 ((relax_substateT) (((type) << 2) | (size)))
684#define TYPE_FROM_RELAX_STATE(s) \
685 ((s) >> 2)
686#define DISP_SIZE_FROM_RELAX_STATE(s) \
687 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 688
689/* This table is used by relax_frag to promote short jumps to long
690 ones where necessary. SMALL (short) jumps may be promoted to BIG
691 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
692 don't allow a short jump in a 32 bit code segment to be promoted to
693 a 16 bit offset jump because it's slower (requires data size
694 prefix), and doesn't work, unless the destination is in the bottom
695 64k of the code segment (The top 16 bits of eip are zeroed). */
696
697const relax_typeS md_relax_table[] =
698{
24eab124
AM		 699 /* The fields are:
700 1) most positive reach of this state,
701 2) most negative reach of this state,
93c2a809 702 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 703 4) which index into the table to try if we can't fit into this one. */
252b5132 704
fddf5b5b 705 /* UNCOND_JUMP states. */
93c2a809
AM		 706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
707 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
708 /* dword jmp adds 4 bytes to frag:
709 0 extra opcode bytes, 4 displacement bytes. */
252b5132 710 {0, 0, 4, 0},
93c2a809
AM		 711 /* word jmp adds 2 byte2 to frag:
712 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 713 {0, 0, 2, 0},
714
93c2a809
AM		 715 /* COND_JUMP states. */
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
717 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
718 /* dword conditionals adds 5 bytes to frag:
719 1 extra opcode byte, 4 displacement bytes. */
720 {0, 0, 5, 0},
fddf5b5b 721 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 722 1 extra opcode byte, 2 displacement bytes. */
723 {0, 0, 3, 0},
724
725 /* COND_JUMP86 states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
728 /* dword conditionals adds 5 bytes to frag:
729 1 extra opcode byte, 4 displacement bytes. */
730 {0, 0, 5, 0},
731 /* word conditionals add 4 bytes to frag:
732 1 displacement byte and a 3 byte long branch insn. */
733 {0, 0, 4, 0}
252b5132
RH		 734};
735
9103f4f4
L		 736static const arch_entry cpu_arch[] =
737{
89507696
JB		 738 /* Do not replace the first two entries - i386_target_format()
739 relies on them being there in this order. */
8a2c8fef 740 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 741 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 743 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 745 CPU_NONE_FLAGS, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 747 CPU_I186_FLAGS, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 749 CPU_I286_FLAGS, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 751 CPU_I386_FLAGS, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 753 CPU_I486_FLAGS, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 755 CPU_I586_FLAGS, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 757 CPU_I686_FLAGS, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 759 CPU_I586_FLAGS, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 761 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 763 CPU_P2_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 765 CPU_P3_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 767 CPU_P4_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 769 CPU_CORE_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 771 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 773 CPU_CORE_FLAGS, 1 },
8a2c8fef 774 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 775 CPU_CORE_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 777 CPU_CORE2_FLAGS, 1 },
8a2c8fef 778 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 779 CPU_CORE2_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 781 CPU_COREI7_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 783 CPU_L1OM_FLAGS, 0 },
7a9068fe 784 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 785 CPU_K1OM_FLAGS, 0 },
81486035 786 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 787 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 789 CPU_K6_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 791 CPU_K6_2_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 793 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 795 CPU_K8_FLAGS, 1 },
8a2c8fef 796 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 797 CPU_K8_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 799 CPU_K8_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 801 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 802 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 803 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 804 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 805 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 806 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 807 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 808 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 809 CPU_BDVER4_FLAGS, 0 },
029f3522 810 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 811 CPU_ZNVER1_FLAGS, 0 },
7b458c12 812 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 813 CPU_BTVER1_FLAGS, 0 },
7b458c12 814 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 815 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 817 CPU_8087_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 819 CPU_287_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 821 CPU_387_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 823 CPU_MMX_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 825 CPU_SSE_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 827 CPU_SSE2_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 829 CPU_SSE3_FLAGS, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 831 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 833 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 835 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_AVX_FLAGS, 0 },
6c30d220 840 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_AVX2_FLAGS, 0 },
43234a1e 842 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 843 CPU_AVX512F_FLAGS, 0 },
43234a1e 844 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_AVX512CD_FLAGS, 0 },
43234a1e 846 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_AVX512ER_FLAGS, 0 },
43234a1e 848 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 850 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 852 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 854 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_VMX_FLAGS, 0 },
8729a6f6 858 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_SMX_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 864 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 866 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 868 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_AES_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 876 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 878 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 880 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_F16C_FLAGS, 0 },
6c30d220 882 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_BMI2_FLAGS, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_FMA_FLAGS, 0 },
8a2c8fef 886 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_FMA4_FLAGS, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_XOP_FLAGS, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_LWP_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_MOVBE_FLAGS, 0 },
60aa667e 894 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_CX16_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_EPT_FLAGS, 0 },
6c30d220 898 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_LZCNT_FLAGS, 0 },
42164a71 900 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_HLE_FLAGS, 0 },
42164a71 902 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_RTM_FLAGS, 0 },
6c30d220 904 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_CLFLUSH_FLAGS, 0 },
22109423 908 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_NOP_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_SVME_FLAGS, 1 },
8a2c8fef 922 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_SVME_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_ABM_FLAGS, 0 },
87973e9f 928 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_BMI_FLAGS, 0 },
2a2a0f38 930 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_TBM_FLAGS, 0 },
e2e1fcde 932 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_ADX_FLAGS, 0 },
e2e1fcde 934 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 936 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_PRFCHW_FLAGS, 0 },
5c111e37 938 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_SMAP_FLAGS, 0 },
7e8b059b 940 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_MPX_FLAGS, 0 },
a0046408 942 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SHA_FLAGS, 0 },
963f3586 944 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 946 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 948 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_SE1_FLAGS, 0 },
c5e7287a 950 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_CLWB_FLAGS, 0 },
9d8596f0 952 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 954 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 956 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 958 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_CLZERO_FLAGS, 0 },
9916071f 960 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_MWAITX_FLAGS, 0 },
8eab4136 962 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_OSPKE_FLAGS, 0 },
8bc52696 964 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65
L		 965 CPU_RDPID_FLAGS, 0 },
966};
967
968static const noarch_entry cpu_noarch[] =
969{
970 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
971 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
972 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
973 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
e413e4e9
AM		 974};
975
704209c0 976#ifdef I386COFF
a6c24e68
NC		 977/* Like s_lcomm_internal in gas/read.c but the alignment string
978 is allowed to be optional. */
979
980static symbolS *
981pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
982{
983 addressT align = 0;
984
985 SKIP_WHITESPACE ();
986
7ab9ffdd 987 if (needs_align
a6c24e68
NC		 988 && *input_line_pointer == ',')
989 {
990 align = parse_align (needs_align - 1);
7ab9ffdd 991
a6c24e68
NC		 992 if (align == (addressT) -1)
993 return NULL;
994 }
995 else
996 {
997 if (size >= 8)
998 align = 3;
999 else if (size >= 4)
1000 align = 2;
1001 else if (size >= 2)
1002 align = 1;
1003 else
1004 align = 0;
1005 }
1006
1007 bss_alloc (symbolP, size, align);
1008 return symbolP;
1009}
1010
704209c0 1011static void
a6c24e68
NC		 1012pe_lcomm (int needs_align)
1013{
1014 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1015}
704209c0 1016#endif
a6c24e68 1017
29b0f896
AM		 1018const pseudo_typeS md_pseudo_table[] =
1019{
1020#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1021 {"align", s_align_bytes, 0},
1022#else
1023 {"align", s_align_ptwo, 0},
1024#endif
1025 {"arch", set_cpu_arch, 0},
1026#ifndef I386COFF
1027 {"bss", s_bss, 0},
a6c24e68
NC		 1028#else
1029 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1030#endif
1031 {"ffloat", float_cons, 'f'},
1032 {"dfloat", float_cons, 'd'},
1033 {"tfloat", float_cons, 'x'},
1034 {"value", cons, 2},
d182319b 1035 {"slong", signed_cons, 4},
29b0f896
AM		 1036 {"noopt", s_ignore, 0},
1037 {"optim", s_ignore, 0},
1038 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1039 {"code16", set_code_flag, CODE_16BIT},
1040 {"code32", set_code_flag, CODE_32BIT},
1041 {"code64", set_code_flag, CODE_64BIT},
1042 {"intel_syntax", set_intel_syntax, 1},
1043 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1044 {"intel_mnemonic", set_intel_mnemonic, 1},
1045 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1046 {"allow_index_reg", set_allow_index_reg, 1},
1047 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1048 {"sse_check", set_check, 0},
1049 {"operand_check", set_check, 1},
3b22753a
L		 1050#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1051 {"largecomm", handle_large_common, 0},
07a53e5c 1052#else
e3bb37b5 1053 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1054 {"loc", dwarf2_directive_loc, 0},
1055 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1056#endif
6482c264
NC		 1057#ifdef TE_PE
1058 {"secrel32", pe_directive_secrel, 0},
1059#endif
29b0f896
AM		 1060 {0, 0, 0}
1061};
1062
1063/* For interface with expression (). */
1064extern char *input_line_pointer;
1065
1066/* Hash table for instruction mnemonic lookup. */
1067static struct hash_control *op_hash;
1068
1069/* Hash table for register lookup. */
1070static struct hash_control *reg_hash;
1071\f
252b5132 1072void
e3bb37b5 1073i386_align_code (fragS *fragP, int count)
252b5132 1074{
ce8a8b2f
AM		 1075 /* Various efficient no-op patterns for aligning code labels.
1076 Note: Don't try to assemble the instructions in the comments.
1077 0L and 0w are not legal. */
bad6e36d 1078 static const unsigned char f32_1[] =
252b5132 1079 {0x90}; /* nop */
bad6e36d 1080 static const unsigned char f32_2[] =
ccc9c027 1081 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1082 static const unsigned char f32_3[] =
252b5132 1083 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1084 static const unsigned char f32_4[] =
252b5132 1085 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1086 static const unsigned char f32_5[] =
252b5132
RH		 1087 {0x90, /* nop */
1088 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1089 static const unsigned char f32_6[] =
252b5132 1090 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1091 static const unsigned char f32_7[] =
252b5132 1092 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1093 static const unsigned char f32_8[] =
252b5132
RH		 1094 {0x90, /* nop */
1095 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1096 static const unsigned char f32_9[] =
252b5132
RH		 1097 {0x89,0xf6, /* movl %esi,%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1099 static const unsigned char f32_10[] =
252b5132
RH		 1100 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1101 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1102 static const unsigned char f32_11[] =
252b5132
RH		 1103 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1104 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1105 static const unsigned char f32_12[] =
252b5132
RH		 1106 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1107 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1108 static const unsigned char f32_13[] =
252b5132
RH		 1109 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1110 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1111 static const unsigned char f32_14[] =
252b5132
RH		 1112 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1113 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1114 static const unsigned char f16_3[] =
c3332e24 1115 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1116 static const unsigned char f16_4[] =
252b5132 1117 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1118 static const unsigned char f16_5[] =
252b5132
RH		 1119 {0x90, /* nop */
1120 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1121 static const unsigned char f16_6[] =
252b5132
RH		 1122 {0x89,0xf6, /* mov %si,%si */
1123 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1124 static const unsigned char f16_7[] =
252b5132
RH		 1125 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1126 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1127 static const unsigned char f16_8[] =
252b5132
RH		 1128 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1129 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1130 static const unsigned char jump_31[] =
76bc74dc
L		 1131 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1132 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1133 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1134 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1135 static const unsigned char *const f32_patt[] = {
252b5132 1136 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1137 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1138 };
bad6e36d 1139 static const unsigned char *const f16_patt[] = {
76bc74dc 1140 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1141 };
ccc9c027 1142 /* nopl (%[re]ax) */
bad6e36d 1143 static const unsigned char alt_3[] =
ccc9c027
L		 1144 {0x0f,0x1f,0x00};
1145 /* nopl 0(%[re]ax) */
bad6e36d 1146 static const unsigned char alt_4[] =
ccc9c027
L		 1147 {0x0f,0x1f,0x40,0x00};
1148 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1149 static const unsigned char alt_5[] =
ccc9c027
L		 1150 {0x0f,0x1f,0x44,0x00,0x00};
1151 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1152 static const unsigned char alt_6[] =
ccc9c027
L		 1153 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopl 0L(%[re]ax) */
bad6e36d 1155 static const unsigned char alt_7[] =
ccc9c027
L		 1156 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1157 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1158 static const unsigned char alt_8[] =
ccc9c027
L		 1159 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1160 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1161 static const unsigned char alt_9[] =
ccc9c027
L		 1162 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1163 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1164 static const unsigned char alt_10[] =
ccc9c027 1165 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1166 static const unsigned char *const alt_patt[] = {
ccc9c027 1167 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1168 alt_9, alt_10
ccc9c027 1169 };
252b5132 1170
76bc74dc
L		 1171 /* Only align for at least a positive non-zero boundary. */
1172 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1173 return;
3e73aa7c 1174
ccc9c027
L		 1175 /* We need to decide which NOP sequence to use for 32bit and
1176 64bit. When -mtune= is used:
4eed87de 1177
76bc74dc
L		 1178 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1179 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1180 2. For the rest, alt_patt will be used.
1181
1182 When -mtune= isn't used, alt_patt will be used if
22109423 1183 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1184 be used.
ccc9c027
L		 1185
1186 When -march= or .arch is used, we can't use anything beyond
1187 cpu_arch_isa_flags. */
1188
1189 if (flag_code == CODE_16BIT)
1190 {
ccc9c027 1191 if (count > 8)
33fef721 1192 {
76bc74dc
L		 1193 memcpy (fragP->fr_literal + fragP->fr_fix,
1194 jump_31, count);
1195 /* Adjust jump offset. */
1196 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1197 }
76bc74dc
L		 1198 else
1199 memcpy (fragP->fr_literal + fragP->fr_fix,
1200 f16_patt[count - 1], count);
252b5132 1201 }
33fef721 1202 else
ccc9c027 1203 {
bad6e36d 1204 const unsigned char *const *patt = NULL;
ccc9c027 1205
fbf3f584 1206 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1207 {
1208 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1209 switch (cpu_arch_tune)
1210 {
1211 case PROCESSOR_UNKNOWN:
1212 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1213 optimize with nops. */
1214 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1215 patt = alt_patt;
ccc9c027
L		 1216 else
1217 patt = f32_patt;
1218 break;
ccc9c027
L		 1219 case PROCESSOR_PENTIUM4:
1220 case PROCESSOR_NOCONA:
ef05d495 1221 case PROCESSOR_CORE:
76bc74dc 1222 case PROCESSOR_CORE2:
bd5295b2 1223 case PROCESSOR_COREI7:
3632d14b 1224 case PROCESSOR_L1OM:
7a9068fe 1225 case PROCESSOR_K1OM:
76bc74dc 1226 case PROCESSOR_GENERIC64:
ccc9c027
L		 1227 case PROCESSOR_K6:
1228 case PROCESSOR_ATHLON:
1229 case PROCESSOR_K8:
4eed87de 1230 case PROCESSOR_AMDFAM10:
8aedb9fe 1231 case PROCESSOR_BD:
029f3522 1232 case PROCESSOR_ZNVER:
7b458c12 1233 case PROCESSOR_BT:
80b8656c 1234 patt = alt_patt;
ccc9c027 1235 break;
76bc74dc 1236 case PROCESSOR_I386:
ccc9c027
L		 1237 case PROCESSOR_I486:
1238 case PROCESSOR_PENTIUM:
2dde1948 1239 case PROCESSOR_PENTIUMPRO:
81486035 1240 case PROCESSOR_IAMCU:
ccc9c027
L		 1241 case PROCESSOR_GENERIC32:
1242 patt = f32_patt;
1243 break;
4eed87de 1244 }
ccc9c027
L		 1245 }
1246 else
1247 {
fbf3f584 1248 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1249 {
1250 case PROCESSOR_UNKNOWN:
e6a14101 1251 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1252 PROCESSOR_UNKNOWN. */
1253 abort ();
1254 break;
1255
76bc74dc 1256 case PROCESSOR_I386:
ccc9c027
L		 1257 case PROCESSOR_I486:
1258 case PROCESSOR_PENTIUM:
81486035 1259 case PROCESSOR_IAMCU:
ccc9c027
L		 1260 case PROCESSOR_K6:
1261 case PROCESSOR_ATHLON:
1262 case PROCESSOR_K8:
4eed87de 1263 case PROCESSOR_AMDFAM10:
8aedb9fe 1264 case PROCESSOR_BD:
029f3522 1265 case PROCESSOR_ZNVER:
7b458c12 1266 case PROCESSOR_BT:
ccc9c027
L		 1267 case PROCESSOR_GENERIC32:
1268 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1269 with nops. */
1270 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1271 patt = alt_patt;
ccc9c027
L		 1272 else
1273 patt = f32_patt;
1274 break;
76bc74dc
L		 1275 case PROCESSOR_PENTIUMPRO:
1276 case PROCESSOR_PENTIUM4:
1277 case PROCESSOR_NOCONA:
1278 case PROCESSOR_CORE:
ef05d495 1279 case PROCESSOR_CORE2:
bd5295b2 1280 case PROCESSOR_COREI7:
3632d14b 1281 case PROCESSOR_L1OM:
7a9068fe 1282 case PROCESSOR_K1OM:
22109423 1283 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1284 patt = alt_patt;
ccc9c027
L		 1285 else
1286 patt = f32_patt;
1287 break;
1288 case PROCESSOR_GENERIC64:
80b8656c 1289 patt = alt_patt;
ccc9c027 1290 break;
4eed87de 1291 }
ccc9c027
L		 1292 }
1293
76bc74dc
L		 1294 if (patt == f32_patt)
1295 {
1296 /* If the padding is less than 15 bytes, we use the normal
1297 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1298 its offset. */
1299 int limit;
76ba9986 1300
711eedef
L		 1301 /* For 64bit, the limit is 3 bytes. */
1302 if (flag_code == CODE_64BIT
1303 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1304 limit = 3;
1305 else
1306 limit = 15;
1307 if (count < limit)
76bc74dc
L		 1308 memcpy (fragP->fr_literal + fragP->fr_fix,
1309 patt[count - 1], count);
1310 else
1311 {
1312 memcpy (fragP->fr_literal + fragP->fr_fix,
1313 jump_31, count);
1314 /* Adjust jump offset. */
1315 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1316 }
1317 }
1318 else
1319 {
80b8656c
L		 1320 /* Maximum length of an instruction is 10 byte. If the
1321 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1322 we have to break it into smaller pieces. */
1323 int padding = count;
80b8656c 1324 while (padding > 10)
76bc74dc 1325 {
80b8656c 1326 padding -= 10;
76bc74dc 1327 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1328 patt [9], 10);
76bc74dc
L		 1329 }
1330
1331 if (padding)
1332 memcpy (fragP->fr_literal + fragP->fr_fix,
1333 patt [padding - 1], padding);
1334 }
ccc9c027 1335 }
33fef721 1336 fragP->fr_var = count;
252b5132
RH		 1337}
1338
c6fb90c8 1339static INLINE int
0dfbf9d7 1340operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1341{
0dfbf9d7 1342 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1343 {
1344 case 3:
0dfbf9d7 1345 if (x->array[2])
c6fb90c8
L		 1346 return 0;
1347 case 2:
0dfbf9d7 1348 if (x->array[1])
c6fb90c8
L		 1349 return 0;
1350 case 1:
0dfbf9d7 1351 return !x->array[0];
c6fb90c8
L		 1352 default:
1353 abort ();
1354 }
40fb9820
L		 1355}
1356
c6fb90c8 1357static INLINE void
0dfbf9d7 1358operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1359{
0dfbf9d7 1360 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1361 {
1362 case 3:
0dfbf9d7 1363 x->array[2] = v;
c6fb90c8 1364 case 2:
0dfbf9d7 1365 x->array[1] = v;
c6fb90c8 1366 case 1:
0dfbf9d7 1367 x->array[0] = v;
c6fb90c8
L		 1368 break;
1369 default:
1370 abort ();
1371 }
1372}
40fb9820 1373
c6fb90c8 1374static INLINE int
0dfbf9d7
L		 1375operand_type_equal (const union i386_operand_type *x,
1376 const union i386_operand_type *y)
c6fb90c8 1377{
0dfbf9d7 1378 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1379 {
1380 case 3:
0dfbf9d7 1381 if (x->array[2] != y->array[2])
c6fb90c8
L		 1382 return 0;
1383 case 2:
0dfbf9d7 1384 if (x->array[1] != y->array[1])
c6fb90c8
L		 1385 return 0;
1386 case 1:
0dfbf9d7 1387 return x->array[0] == y->array[0];
c6fb90c8
L		 1388 break;
1389 default:
1390 abort ();
1391 }
1392}
40fb9820 1393
0dfbf9d7
L		 1394static INLINE int
1395cpu_flags_all_zero (const union i386_cpu_flags *x)
1396{
1397 switch (ARRAY_SIZE(x->array))
1398 {
1399 case 3:
1400 if (x->array[2])
1401 return 0;
1402 case 2:
1403 if (x->array[1])
1404 return 0;
1405 case 1:
1406 return !x->array[0];
1407 default:
1408 abort ();
1409 }
1410}
1411
0dfbf9d7
L		 1412static INLINE int
1413cpu_flags_equal (const union i386_cpu_flags *x,
1414 const union i386_cpu_flags *y)
1415{
1416 switch (ARRAY_SIZE(x->array))
1417 {
1418 case 3:
1419 if (x->array[2] != y->array[2])
1420 return 0;
1421 case 2:
1422 if (x->array[1] != y->array[1])
1423 return 0;
1424 case 1:
1425 return x->array[0] == y->array[0];
1426 break;
1427 default:
1428 abort ();
1429 }
1430}
c6fb90c8
L		 1431
1432static INLINE int
1433cpu_flags_check_cpu64 (i386_cpu_flags f)
1434{
1435 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1436 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1437}
1438
c6fb90c8
L		 1439static INLINE i386_cpu_flags
1440cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1441{
c6fb90c8
L		 1442 switch (ARRAY_SIZE (x.array))
1443 {
1444 case 3:
1445 x.array [2] &= y.array [2];
1446 case 2:
1447 x.array [1] &= y.array [1];
1448 case 1:
1449 x.array [0] &= y.array [0];
1450 break;
1451 default:
1452 abort ();
1453 }
1454 return x;
1455}
40fb9820 1456
c6fb90c8
L		 1457static INLINE i386_cpu_flags
1458cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1459{
c6fb90c8 1460 switch (ARRAY_SIZE (x.array))
40fb9820 1461 {
c6fb90c8
L		 1462 case 3:
1463 x.array [2] |= y.array [2];
1464 case 2:
1465 x.array [1] |= y.array [1];
1466 case 1:
1467 x.array [0] |= y.array [0];
40fb9820
L		 1468 break;
1469 default:
1470 abort ();
1471 }
40fb9820
L		 1472 return x;
1473}
1474
309d3373
JB		 1475static INLINE i386_cpu_flags
1476cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1477{
1478 switch (ARRAY_SIZE (x.array))
1479 {
1480 case 3:
1481 x.array [2] &= ~y.array [2];
1482 case 2:
1483 x.array [1] &= ~y.array [1];
1484 case 1:
1485 x.array [0] &= ~y.array [0];
1486 break;
1487 default:
1488 abort ();
1489 }
1490 return x;
1491}
1492
81486035
L		 1493static int
1494valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1495{
1496 if (cpu_arch_isa == PROCESSOR_IAMCU)
1497 {
1498 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1499 i386_cpu_flags compat_flags;
1500 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1501 return cpu_flags_all_zero (&compat_flags);
1502 }
1503 else
1504 return 1;
1505}
1506
c0f3af97
L		 1507#define CPU_FLAGS_ARCH_MATCH 0x1
1508#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1509#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1510#define CPU_FLAGS_PCLMUL_MATCH 0x8
1511#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1512
a5ff0eb2 1513#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1514 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1515 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1516#define CPU_FLAGS_PERFECT_MATCH \
1517 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1518
1519/* Return CPU flags match bits. */
3629bb00 1520
40fb9820 1521static int
d3ce72d0 1522cpu_flags_match (const insn_template *t)
40fb9820 1523{
c0f3af97
L		 1524 i386_cpu_flags x = t->cpu_flags;
1525 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1526
1527 x.bitfield.cpu64 = 0;
1528 x.bitfield.cpuno64 = 0;
1529
0dfbf9d7 1530 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1531 {
1532 /* This instruction is available on all archs. */
1533 match |= CPU_FLAGS_32BIT_MATCH;
1534 }
3629bb00
L		 1535 else
1536 {
c0f3af97 1537 /* This instruction is available only on some archs. */
3629bb00
L		 1538 i386_cpu_flags cpu = cpu_arch_flags;
1539
1540 cpu.bitfield.cpu64 = 0;
1541 cpu.bitfield.cpuno64 = 0;
1542 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1543 if (!cpu_flags_all_zero (&cpu))
1544 {
a5ff0eb2
L		 1545 if (x.bitfield.cpuavx)
1546 {
ce2f5b3c 1547 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1548 if (cpu.bitfield.cpuavx)
1549 {
1550 /* Check SSE2AVX. */
1551 if (!t->opcode_modifier.sse2avx|| sse2avx)
1552 {
1553 match |= (CPU_FLAGS_ARCH_MATCH
1554 | CPU_FLAGS_AVX_MATCH);
1555 /* Check AES. */
1556 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1557 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1558 /* Check PCLMUL. */
1559 if (!x.bitfield.cpupclmul
1560 || cpu.bitfield.cpupclmul)
1561 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1562 }
1563 }
1564 else
1565 match |= CPU_FLAGS_ARCH_MATCH;
1566 }
1567 else
c0f3af97
L		 1568 match |= CPU_FLAGS_32BIT_MATCH;
1569 }
3629bb00 1570 }
c0f3af97 1571 return match;
40fb9820
L		 1572}
1573
c6fb90c8
L		 1574static INLINE i386_operand_type
1575operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1576{
c6fb90c8
L		 1577 switch (ARRAY_SIZE (x.array))
1578 {
1579 case 3:
1580 x.array [2] &= y.array [2];
1581 case 2:
1582 x.array [1] &= y.array [1];
1583 case 1:
1584 x.array [0] &= y.array [0];
1585 break;
1586 default:
1587 abort ();
1588 }
1589 return x;
40fb9820
L		 1590}
1591
c6fb90c8
L		 1592static INLINE i386_operand_type
1593operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1594{
c6fb90c8 1595 switch (ARRAY_SIZE (x.array))
40fb9820 1596 {
c6fb90c8
L		 1597 case 3:
1598 x.array [2] |= y.array [2];
1599 case 2:
1600 x.array [1] |= y.array [1];
1601 case 1:
1602 x.array [0] |= y.array [0];
40fb9820
L		 1603 break;
1604 default:
1605 abort ();
1606 }
c6fb90c8
L		 1607 return x;
1608}
40fb9820 1609
c6fb90c8
L		 1610static INLINE i386_operand_type
1611operand_type_xor (i386_operand_type x, i386_operand_type y)
1612{
1613 switch (ARRAY_SIZE (x.array))
1614 {
1615 case 3:
1616 x.array [2] ^= y.array [2];
1617 case 2:
1618 x.array [1] ^= y.array [1];
1619 case 1:
1620 x.array [0] ^= y.array [0];
1621 break;
1622 default:
1623 abort ();
1624 }
40fb9820
L		 1625 return x;
1626}
1627
1628static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1629static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1630static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1631static const i386_operand_type inoutportreg
1632 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1633static const i386_operand_type reg16_inoutportreg
1634 = OPERAND_TYPE_REG16_INOUTPORTREG;
1635static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1636static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1637static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1638static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1639static const i386_operand_type anydisp
1640 = OPERAND_TYPE_ANYDISP;
40fb9820 1641static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1642static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1643static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1644static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1645static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1646static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1647static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1648static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1649static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1650static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1651static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1652static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1653static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1654static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1655
1656enum operand_type
1657{
1658 reg,
40fb9820
L		 1659 imm,
1660 disp,
1661 anymem
1662};
1663
c6fb90c8 1664static INLINE int
40fb9820
L		 1665operand_type_check (i386_operand_type t, enum operand_type c)
1666{
1667 switch (c)
1668 {
1669 case reg:
1670 return (t.bitfield.reg8
1671 || t.bitfield.reg16
1672 || t.bitfield.reg32
1673 || t.bitfield.reg64);
1674
40fb9820
L		 1675 case imm:
1676 return (t.bitfield.imm8
1677 || t.bitfield.imm8s
1678 || t.bitfield.imm16
1679 || t.bitfield.imm32
1680 || t.bitfield.imm32s
1681 || t.bitfield.imm64);
1682
1683 case disp:
1684 return (t.bitfield.disp8
1685 || t.bitfield.disp16
1686 || t.bitfield.disp32
1687 || t.bitfield.disp32s
1688 || t.bitfield.disp64);
1689
1690 case anymem:
1691 return (t.bitfield.disp8
1692 || t.bitfield.disp16
1693 || t.bitfield.disp32
1694 || t.bitfield.disp32s
1695 || t.bitfield.disp64
1696 || t.bitfield.baseindex);
1697
1698 default:
1699 abort ();
1700 }
2cfe26b6
AM		 1701
1702 return 0;
40fb9820
L		 1703}
1704
5c07affc
L		 1705/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1706 operand J for instruction template T. */
1707
1708static INLINE int
d3ce72d0 1709match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1710{
1711 return !((i.types[j].bitfield.byte
1712 && !t->operand_types[j].bitfield.byte)
1713 || (i.types[j].bitfield.word
1714 && !t->operand_types[j].bitfield.word)
1715 || (i.types[j].bitfield.dword
1716 && !t->operand_types[j].bitfield.dword)
1717 || (i.types[j].bitfield.qword
1718 && !t->operand_types[j].bitfield.qword));
1719}
1720
1721/* Return 1 if there is no conflict in any size on operand J for
1722 instruction template T. */
1723
1724static INLINE int
d3ce72d0 1725match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1726{
1727 return (match_reg_size (t, j)
1728 && !((i.types[j].bitfield.unspecified
af508cb9 1729 && !i.broadcast
5c07affc
L		 1730 && !t->operand_types[j].bitfield.unspecified)
1731 || (i.types[j].bitfield.fword
1732 && !t->operand_types[j].bitfield.fword)
1733 || (i.types[j].bitfield.tbyte
1734 && !t->operand_types[j].bitfield.tbyte)
1735 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1736 && !t->operand_types[j].bitfield.xmmword)
1737 || (i.types[j].bitfield.ymmword
43234a1e
L		 1738 && !t->operand_types[j].bitfield.ymmword)
1739 || (i.types[j].bitfield.zmmword
1740 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1741}
1742
1743/* Return 1 if there is no size conflict on any operands for
1744 instruction template T. */
1745
1746static INLINE int
d3ce72d0 1747operand_size_match (const insn_template *t)
5c07affc
L		 1748{
1749 unsigned int j;
1750 int match = 1;
1751
1752 /* Don't check jump instructions. */
1753 if (t->opcode_modifier.jump
1754 || t->opcode_modifier.jumpbyte
1755 || t->opcode_modifier.jumpdword
1756 || t->opcode_modifier.jumpintersegment)
1757 return match;
1758
1759 /* Check memory and accumulator operand size. */
1760 for (j = 0; j < i.operands; j++)
1761 {
1762 if (t->operand_types[j].bitfield.anysize)
1763 continue;
1764
1765 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1766 {
1767 match = 0;
1768 break;
1769 }
1770
1771 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1772 {
1773 match = 0;
1774 break;
1775 }
1776 }
1777
891edac4 1778 if (match)
5c07affc 1779 return match;
891edac4
L		 1780 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1781 {
1782mismatch:
86e026a4 1783 i.error = operand_size_mismatch;
891edac4
L		 1784 return 0;
1785 }
5c07affc
L		 1786
1787 /* Check reverse. */
9c2799c2 1788 gas_assert (i.operands == 2);
5c07affc
L		 1789
1790 match = 1;
1791 for (j = 0; j < 2; j++)
1792 {
1793 if (t->operand_types[j].bitfield.acc
1794 && !match_reg_size (t, j ? 0 : 1))
891edac4 1795 goto mismatch;
5c07affc
L		 1796
1797 if (i.types[j].bitfield.mem
1798 && !match_mem_size (t, j ? 0 : 1))
891edac4 1799 goto mismatch;
5c07affc
L		 1800 }
1801
1802 return match;
1803}
1804
c6fb90c8 1805static INLINE int
40fb9820
L		 1806operand_type_match (i386_operand_type overlap,
1807 i386_operand_type given)
1808{
1809 i386_operand_type temp = overlap;
1810
1811 temp.bitfield.jumpabsolute = 0;
7d5e4556 1812 temp.bitfield.unspecified = 0;
5c07affc
L		 1813 temp.bitfield.byte = 0;
1814 temp.bitfield.word = 0;
1815 temp.bitfield.dword = 0;
1816 temp.bitfield.fword = 0;
1817 temp.bitfield.qword = 0;
1818 temp.bitfield.tbyte = 0;
1819 temp.bitfield.xmmword = 0;
c0f3af97 1820 temp.bitfield.ymmword = 0;
43234a1e 1821 temp.bitfield.zmmword = 0;
0dfbf9d7 1822 if (operand_type_all_zero (&temp))
891edac4 1823 goto mismatch;
40fb9820 1824
891edac4
L		 1825 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1826 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1827 return 1;
1828
1829mismatch:
a65babc9 1830 i.error = operand_type_mismatch;
891edac4 1831 return 0;
40fb9820
L		 1832}
1833
7d5e4556 1834/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1835 unless the expected operand type register overlap is null.
1836 Note that Acc in a template matches every size of reg. */
1837
c6fb90c8 1838static INLINE int
40fb9820
L		 1839operand_type_register_match (i386_operand_type m0,
1840 i386_operand_type g0,
1841 i386_operand_type t0,
1842 i386_operand_type m1,
1843 i386_operand_type g1,
1844 i386_operand_type t1)
1845{
1846 if (!operand_type_check (g0, reg))
1847 return 1;
1848
1849 if (!operand_type_check (g1, reg))
1850 return 1;
1851
1852 if (g0.bitfield.reg8 == g1.bitfield.reg8
1853 && g0.bitfield.reg16 == g1.bitfield.reg16
1854 && g0.bitfield.reg32 == g1.bitfield.reg32
1855 && g0.bitfield.reg64 == g1.bitfield.reg64)
1856 return 1;
1857
1858 if (m0.bitfield.acc)
1859 {
1860 t0.bitfield.reg8 = 1;
1861 t0.bitfield.reg16 = 1;
1862 t0.bitfield.reg32 = 1;
1863 t0.bitfield.reg64 = 1;
1864 }
1865
1866 if (m1.bitfield.acc)
1867 {
1868 t1.bitfield.reg8 = 1;
1869 t1.bitfield.reg16 = 1;
1870 t1.bitfield.reg32 = 1;
1871 t1.bitfield.reg64 = 1;
1872 }
1873
891edac4
L		 1874 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1875 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1876 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1877 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1878 return 1;
1879
a65babc9 1880 i.error = register_type_mismatch;
891edac4
L		 1881
1882 return 0;
40fb9820
L		 1883}
1884
4c692bc7
JB		 1885static INLINE unsigned int
1886register_number (const reg_entry *r)
1887{
1888 unsigned int nr = r->reg_num;
1889
1890 if (r->reg_flags & RegRex)
1891 nr += 8;
1892
200cbe0f
L		 1893 if (r->reg_flags & RegVRex)
1894 nr += 16;
1895
4c692bc7
JB		 1896 return nr;
1897}
1898
252b5132 1899static INLINE unsigned int
40fb9820 1900mode_from_disp_size (i386_operand_type t)
252b5132 1901{
43234a1e 1902 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1903 return 1;
1904 else if (t.bitfield.disp16
1905 || t.bitfield.disp32
1906 || t.bitfield.disp32s)
1907 return 2;
1908 else
1909 return 0;
252b5132
RH		 1910}
1911
1912static INLINE int
65879393 1913fits_in_signed_byte (addressT num)
252b5132 1914{
65879393 1915 return num + 0x80 <= 0xff;
47926f60 1916}
252b5132
RH		 1917
1918static INLINE int
65879393 1919fits_in_unsigned_byte (addressT num)
252b5132 1920{
65879393 1921 return num <= 0xff;
47926f60 1922}
252b5132
RH		 1923
1924static INLINE int
65879393 1925fits_in_unsigned_word (addressT num)
252b5132 1926{
65879393 1927 return num <= 0xffff;
47926f60 1928}
252b5132
RH		 1929
1930static INLINE int
65879393 1931fits_in_signed_word (addressT num)
252b5132 1932{
65879393 1933 return num + 0x8000 <= 0xffff;
47926f60 1934}
2a962e6d 1935
3e73aa7c 1936static INLINE int
65879393 1937fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1938{
1939#ifndef BFD64
1940 return 1;
1941#else
65879393 1942 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1943#endif
1944} /* fits_in_signed_long() */
2a962e6d 1945
3e73aa7c 1946static INLINE int
65879393 1947fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1948{
1949#ifndef BFD64
1950 return 1;
1951#else
65879393 1952 return num <= 0xffffffff;
3e73aa7c
JH		 1953#endif
1954} /* fits_in_unsigned_long() */
252b5132 1955
43234a1e
L		 1956static INLINE int
1957fits_in_vec_disp8 (offsetT num)
1958{
1959 int shift = i.memshift;
1960 unsigned int mask;
1961
1962 if (shift == -1)
1963 abort ();
1964
1965 mask = (1 << shift) - 1;
1966
1967 /* Return 0 if NUM isn't properly aligned. */
1968 if ((num & mask))
1969 return 0;
1970
1971 /* Check if NUM will fit in 8bit after shift. */
1972 return fits_in_signed_byte (num >> shift);
1973}
1974
a683cc34
SP		 1975static INLINE int
1976fits_in_imm4 (offsetT num)
1977{
1978 return (num & 0xf) == num;
1979}
1980
40fb9820 1981static i386_operand_type
e3bb37b5 1982smallest_imm_type (offsetT num)
252b5132 1983{
40fb9820 1984 i386_operand_type t;
7ab9ffdd 1985
0dfbf9d7 1986 operand_type_set (&t, 0);
40fb9820
L		 1987 t.bitfield.imm64 = 1;
1988
1989 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1990 {
1991 /* This code is disabled on the 486 because all the Imm1 forms
1992 in the opcode table are slower on the i486. They're the
1993 versions with the implicitly specified single-position
1994 displacement, which has another syntax if you really want to
1995 use that form. */
40fb9820
L		 1996 t.bitfield.imm1 = 1;
1997 t.bitfield.imm8 = 1;
1998 t.bitfield.imm8s = 1;
1999 t.bitfield.imm16 = 1;
2000 t.bitfield.imm32 = 1;
2001 t.bitfield.imm32s = 1;
2002 }
2003 else if (fits_in_signed_byte (num))
2004 {
2005 t.bitfield.imm8 = 1;
2006 t.bitfield.imm8s = 1;
2007 t.bitfield.imm16 = 1;
2008 t.bitfield.imm32 = 1;
2009 t.bitfield.imm32s = 1;
2010 }
2011 else if (fits_in_unsigned_byte (num))
2012 {
2013 t.bitfield.imm8 = 1;
2014 t.bitfield.imm16 = 1;
2015 t.bitfield.imm32 = 1;
2016 t.bitfield.imm32s = 1;
2017 }
2018 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2019 {
2020 t.bitfield.imm16 = 1;
2021 t.bitfield.imm32 = 1;
2022 t.bitfield.imm32s = 1;
2023 }
2024 else if (fits_in_signed_long (num))
2025 {
2026 t.bitfield.imm32 = 1;
2027 t.bitfield.imm32s = 1;
2028 }
2029 else if (fits_in_unsigned_long (num))
2030 t.bitfield.imm32 = 1;
2031
2032 return t;
47926f60 2033}
252b5132 2034
847f7ad4 2035static offsetT
e3bb37b5 2036offset_in_range (offsetT val, int size)
847f7ad4 2037{
508866be 2038 addressT mask;
ba2adb93 2039
847f7ad4
AM		 2040 switch (size)
2041 {
508866be
L		 2042 case 1: mask = ((addressT) 1 << 8) - 1; break;
2043 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2044 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2045#ifdef BFD64
2046 case 8: mask = ((addressT) 2 << 63) - 1; break;
2047#endif
47926f60 2048 default: abort ();
847f7ad4
AM		 2049 }
2050
9de868bf
L		 2051#ifdef BFD64
2052 /* If BFD64, sign extend val for 32bit address mode. */
2053 if (flag_code != CODE_64BIT
2054 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2055 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2056 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2057#endif
ba2adb93 2058
47926f60 2059 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2060 {
2061 char buf1[40], buf2[40];
2062
2063 sprint_value (buf1, val);
2064 sprint_value (buf2, val & mask);
2065 as_warn (_("%s shortened to %s"), buf1, buf2);
2066 }
2067 return val & mask;
2068}
2069
c32fa91d
L		 2070enum PREFIX_GROUP
2071{
2072 PREFIX_EXIST = 0,
2073 PREFIX_LOCK,
2074 PREFIX_REP,
2075 PREFIX_OTHER
2076};
2077
2078/* Returns
2079 a. PREFIX_EXIST if attempting to add a prefix where one from the
2080 same class already exists.
2081 b. PREFIX_LOCK if lock prefix is added.
2082 c. PREFIX_REP if rep/repne prefix is added.
2083 d. PREFIX_OTHER if other prefix is added.
2084 */
2085
2086static enum PREFIX_GROUP
e3bb37b5 2087add_prefix (unsigned int prefix)
252b5132 2088{
c32fa91d 2089 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2090 unsigned int q;
252b5132 2091
29b0f896
AM		 2092 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2093 && flag_code == CODE_64BIT)
b1905489 2094 {
161a04f6
L		 2095 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2096 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2097 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2098 ret = PREFIX_EXIST;
b1905489
JB		 2099 q = REX_PREFIX;
2100 }
3e73aa7c 2101 else
b1905489
JB		 2102 {
2103 switch (prefix)
2104 {
2105 default:
2106 abort ();
2107
2108 case CS_PREFIX_OPCODE:
2109 case DS_PREFIX_OPCODE:
2110 case ES_PREFIX_OPCODE:
2111 case FS_PREFIX_OPCODE:
2112 case GS_PREFIX_OPCODE:
2113 case SS_PREFIX_OPCODE:
2114 q = SEG_PREFIX;
2115 break;
2116
2117 case REPNE_PREFIX_OPCODE:
2118 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2119 q = REP_PREFIX;
2120 ret = PREFIX_REP;
2121 break;
2122
b1905489 2123 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2124 q = LOCK_PREFIX;
2125 ret = PREFIX_LOCK;
b1905489
JB		 2126 break;
2127
2128 case FWAIT_OPCODE:
2129 q = WAIT_PREFIX;
2130 break;
2131
2132 case ADDR_PREFIX_OPCODE:
2133 q = ADDR_PREFIX;
2134 break;
2135
2136 case DATA_PREFIX_OPCODE:
2137 q = DATA_PREFIX;
2138 break;
2139 }
2140 if (i.prefix[q] != 0)
c32fa91d 2141 ret = PREFIX_EXIST;
b1905489 2142 }
252b5132 2143
b1905489 2144 if (ret)
252b5132 2145 {
b1905489
JB		 2146 if (!i.prefix[q])
2147 ++i.prefixes;
2148 i.prefix[q] |= prefix;
252b5132 2149 }
b1905489
JB		 2150 else
2151 as_bad (_("same type of prefix used twice"));
252b5132 2152
252b5132
RH		 2153 return ret;
2154}
2155
2156static void
78f12dd3 2157update_code_flag (int value, int check)
eecb386c 2158{
78f12dd3
L		 2159 PRINTF_LIKE ((*as_error));
2160
1e9cc1c2 2161 flag_code = (enum flag_code) value;
40fb9820
L		 2162 if (flag_code == CODE_64BIT)
2163 {
2164 cpu_arch_flags.bitfield.cpu64 = 1;
2165 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2166 }
2167 else
2168 {
2169 cpu_arch_flags.bitfield.cpu64 = 0;
2170 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2171 }
2172 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2173 {
78f12dd3
L		 2174 if (check)
2175 as_error = as_fatal;
2176 else
2177 as_error = as_bad;
2178 (*as_error) (_("64bit mode not supported on `%s'."),
2179 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2180 }
40fb9820 2181 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2182 {
78f12dd3
L		 2183 if (check)
2184 as_error = as_fatal;
2185 else
2186 as_error = as_bad;
2187 (*as_error) (_("32bit mode not supported on `%s'."),
2188 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2189 }
eecb386c
AM		 2190 stackop_size = '\0';
2191}
2192
78f12dd3
L		 2193static void
2194set_code_flag (int value)
2195{
2196 update_code_flag (value, 0);
2197}
2198
eecb386c 2199static void
e3bb37b5 2200set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2201{
1e9cc1c2 2202 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2203 if (flag_code != CODE_16BIT)
2204 abort ();
2205 cpu_arch_flags.bitfield.cpu64 = 0;
2206 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2207 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2208}
2209
2210static void
e3bb37b5 2211set_intel_syntax (int syntax_flag)
252b5132
RH		 2212{
2213 /* Find out if register prefixing is specified. */
2214 int ask_naked_reg = 0;
2215
2216 SKIP_WHITESPACE ();
29b0f896 2217 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2218 {
d02603dc
NC		 2219 char *string;
2220 int e = get_symbol_name (&string);
252b5132 2221
47926f60 2222 if (strcmp (string, "prefix") == 0)
252b5132 2223 ask_naked_reg = 1;
47926f60 2224 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2225 ask_naked_reg = -1;
2226 else
d0b47220 2227 as_bad (_("bad argument to syntax directive."));
d02603dc 2228 (void) restore_line_pointer (e);
252b5132
RH		 2229 }
2230 demand_empty_rest_of_line ();
c3332e24 2231
252b5132
RH		 2232 intel_syntax = syntax_flag;
2233
2234 if (ask_naked_reg == 0)
f86103b7
AM		 2235 allow_naked_reg = (intel_syntax
2236 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2237 else
2238 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2239
ee86248c 2240 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2241
e4a3b5a4 2242 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2243 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2244 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2245}
2246
1efbbeb4
L		 2247static void
2248set_intel_mnemonic (int mnemonic_flag)
2249{
e1d4d893 2250 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2251}
2252
db51cc60
L		 2253static void
2254set_allow_index_reg (int flag)
2255{
2256 allow_index_reg = flag;
2257}
2258
cb19c032 2259static void
7bab8ab5 2260set_check (int what)
cb19c032 2261{
7bab8ab5
JB		 2262 enum check_kind *kind;
2263 const char *str;
2264
2265 if (what)
2266 {
2267 kind = &operand_check;
2268 str = "operand";
2269 }
2270 else
2271 {
2272 kind = &sse_check;
2273 str = "sse";
2274 }
2275
cb19c032
L		 2276 SKIP_WHITESPACE ();
2277
2278 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2279 {
d02603dc
NC		 2280 char *string;
2281 int e = get_symbol_name (&string);
cb19c032
L		 2282
2283 if (strcmp (string, "none") == 0)
7bab8ab5 2284 *kind = check_none;
cb19c032 2285 else if (strcmp (string, "warning") == 0)
7bab8ab5 2286 *kind = check_warning;
cb19c032 2287 else if (strcmp (string, "error") == 0)
7bab8ab5 2288 *kind = check_error;
cb19c032 2289 else
7bab8ab5 2290 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2291 (void) restore_line_pointer (e);
cb19c032
L		 2292 }
2293 else
7bab8ab5 2294 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2295
2296 demand_empty_rest_of_line ();
2297}
2298
8a9036a4
L		 2299static void
2300check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2301 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2302{
2303#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2304 static const char *arch;
2305
2306 /* Intel LIOM is only supported on ELF. */
2307 if (!IS_ELF)
2308 return;
2309
2310 if (!arch)
2311 {
2312 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2313 use default_arch. */
2314 arch = cpu_arch_name;
2315 if (!arch)
2316 arch = default_arch;
2317 }
2318
81486035
L		 2319 /* If we are targeting Intel MCU, we must enable it. */
2320 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2321 || new_flag.bitfield.cpuiamcu)
2322 return;
2323
3632d14b 2324 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2325 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2326 || new_flag.bitfield.cpul1om)
8a9036a4 2327 return;
76ba9986 2328
7a9068fe
L		 2329 /* If we are targeting Intel K1OM, we must enable it. */
2330 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2331 || new_flag.bitfield.cpuk1om)
2332 return;
2333
8a9036a4
L		 2334 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2335#endif
2336}
2337
e413e4e9 2338static void
e3bb37b5 2339set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2340{
47926f60 2341 SKIP_WHITESPACE ();
e413e4e9 2342
29b0f896 2343 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2344 {
d02603dc
NC		 2345 char *string;
2346 int e = get_symbol_name (&string);
91d6fa6a 2347 unsigned int j;
40fb9820 2348 i386_cpu_flags flags;
e413e4e9 2349
91d6fa6a 2350 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2351 {
91d6fa6a 2352 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2353 {
91d6fa6a 2354 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2355
5c6af06e
JB		 2356 if (*string != '.')
2357 {
91d6fa6a 2358 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2359 cpu_sub_arch_name = NULL;
91d6fa6a 2360 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2361 if (flag_code == CODE_64BIT)
2362 {
2363 cpu_arch_flags.bitfield.cpu64 = 1;
2364 cpu_arch_flags.bitfield.cpuno64 = 0;
2365 }
2366 else
2367 {
2368 cpu_arch_flags.bitfield.cpu64 = 0;
2369 cpu_arch_flags.bitfield.cpuno64 = 1;
2370 }
91d6fa6a
NC		 2371 cpu_arch_isa = cpu_arch[j].type;
2372 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2373 if (!cpu_arch_tune_set)
2374 {
2375 cpu_arch_tune = cpu_arch_isa;
2376 cpu_arch_tune_flags = cpu_arch_isa_flags;
2377 }
5c6af06e
JB		 2378 break;
2379 }
40fb9820 2380
293f5f65
L		 2381 flags = cpu_flags_or (cpu_arch_flags,
2382 cpu_arch[j].flags);
81486035
L		 2383
2384 if (!valid_iamcu_cpu_flags (&flags))
2385 as_fatal (_("`%s' isn't valid for Intel MCU"),
2386 cpu_arch[j].name);
2387 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2388 {
6305a203
L		 2389 if (cpu_sub_arch_name)
2390 {
2391 char *name = cpu_sub_arch_name;
2392 cpu_sub_arch_name = concat (name,
91d6fa6a 2393 cpu_arch[j].name,
1bf57e9f 2394 (const char *) NULL);
6305a203
L		 2395 free (name);
2396 }
2397 else
91d6fa6a 2398 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2399 cpu_arch_flags = flags;
a586129e 2400 cpu_arch_isa_flags = flags;
5c6af06e 2401 }
d02603dc 2402 (void) restore_line_pointer (e);
5c6af06e
JB		 2403 demand_empty_rest_of_line ();
2404 return;
e413e4e9
AM		 2405 }
2406 }
293f5f65
L		 2407
2408 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2409 {
2410 /* Disable an ISA entension. */
2411 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2412 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2413 {
2414 flags = cpu_flags_and_not (cpu_arch_flags,
2415 cpu_noarch[j].flags);
2416 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2417 {
2418 if (cpu_sub_arch_name)
2419 {
2420 char *name = cpu_sub_arch_name;
2421 cpu_sub_arch_name = concat (name, string,
2422 (const char *) NULL);
2423 free (name);
2424 }
2425 else
2426 cpu_sub_arch_name = xstrdup (string);
2427 cpu_arch_flags = flags;
2428 cpu_arch_isa_flags = flags;
2429 }
2430 (void) restore_line_pointer (e);
2431 demand_empty_rest_of_line ();
2432 return;
2433 }
2434
2435 j = ARRAY_SIZE (cpu_arch);
2436 }
2437
91d6fa6a 2438 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2439 as_bad (_("no such architecture: `%s'"), string);
2440
2441 *input_line_pointer = e;
2442 }
2443 else
2444 as_bad (_("missing cpu architecture"));
2445
fddf5b5b
AM		 2446 no_cond_jump_promotion = 0;
2447 if (*input_line_pointer == ','
29b0f896 2448 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2449 {
d02603dc
NC		 2450 char *string;
2451 char e;
2452
2453 ++input_line_pointer;
2454 e = get_symbol_name (&string);
fddf5b5b
AM		 2455
2456 if (strcmp (string, "nojumps") == 0)
2457 no_cond_jump_promotion = 1;
2458 else if (strcmp (string, "jumps") == 0)
2459 ;
2460 else
2461 as_bad (_("no such architecture modifier: `%s'"), string);
2462
d02603dc 2463 (void) restore_line_pointer (e);
fddf5b5b
AM		 2464 }
2465
e413e4e9
AM		 2466 demand_empty_rest_of_line ();
2467}
2468
8a9036a4
L		 2469enum bfd_architecture
2470i386_arch (void)
2471{
3632d14b 2472 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2473 {
2474 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2475 || flag_code != CODE_64BIT)
2476 as_fatal (_("Intel L1OM is 64bit ELF only"));
2477 return bfd_arch_l1om;
2478 }
7a9068fe
L		 2479 else if (cpu_arch_isa == PROCESSOR_K1OM)
2480 {
2481 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2482 || flag_code != CODE_64BIT)
2483 as_fatal (_("Intel K1OM is 64bit ELF only"));
2484 return bfd_arch_k1om;
2485 }
81486035
L		 2486 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2487 {
2488 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2489 || flag_code == CODE_64BIT)
2490 as_fatal (_("Intel MCU is 32bit ELF only"));
2491 return bfd_arch_iamcu;
2492 }
8a9036a4
L		 2493 else
2494 return bfd_arch_i386;
2495}
2496
b9d79e03 2497unsigned long
7016a5d5 2498i386_mach (void)
b9d79e03 2499{
351f65ca 2500 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2501 {
3632d14b 2502 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2503 {
351f65ca
L		 2504 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2505 || default_arch[6] != '\0')
8a9036a4
L		 2506 as_fatal (_("Intel L1OM is 64bit ELF only"));
2507 return bfd_mach_l1om;
2508 }
7a9068fe
L		 2509 else if (cpu_arch_isa == PROCESSOR_K1OM)
2510 {
2511 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2512 || default_arch[6] != '\0')
2513 as_fatal (_("Intel K1OM is 64bit ELF only"));
2514 return bfd_mach_k1om;
2515 }
351f65ca 2516 else if (default_arch[6] == '\0')
8a9036a4 2517 return bfd_mach_x86_64;
351f65ca
L		 2518 else
2519 return bfd_mach_x64_32;
8a9036a4 2520 }
5197d474
L		 2521 else if (!strcmp (default_arch, "i386")
2522 || !strcmp (default_arch, "iamcu"))
81486035
L		 2523 {
2524 if (cpu_arch_isa == PROCESSOR_IAMCU)
2525 {
2526 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2527 as_fatal (_("Intel MCU is 32bit ELF only"));
2528 return bfd_mach_i386_iamcu;
2529 }
2530 else
2531 return bfd_mach_i386_i386;
2532 }
b9d79e03 2533 else
2b5d6a91 2534 as_fatal (_("unknown architecture"));
b9d79e03 2535}
b9d79e03 2536\f
252b5132 2537void
7016a5d5 2538md_begin (void)
252b5132
RH		 2539{
2540 const char *hash_err;
2541
47926f60 2542 /* Initialize op_hash hash table. */
252b5132
RH		 2543 op_hash = hash_new ();
2544
2545 {
d3ce72d0 2546 const insn_template *optab;
29b0f896 2547 templates *core_optab;
252b5132 2548
47926f60
KH		 2549 /* Setup for loop. */
2550 optab = i386_optab;
add39d23 2551 core_optab = XNEW (templates);
252b5132
RH		 2552 core_optab->start = optab;
2553
2554 while (1)
2555 {
2556 ++optab;
2557 if (optab->name == NULL
2558 || strcmp (optab->name, (optab - 1)->name) != 0)
2559 {
2560 /* different name --> ship out current template list;
47926f60 2561 add to hash table; & begin anew. */
252b5132
RH		 2562 core_optab->end = optab;
2563 hash_err = hash_insert (op_hash,
2564 (optab - 1)->name,
5a49b8ac 2565 (void *) core_optab);
252b5132
RH		 2566 if (hash_err)
2567 {
b37df7c4 2568 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2569 (optab - 1)->name,
2570 hash_err);
2571 }
2572 if (optab->name == NULL)
2573 break;
add39d23 2574 core_optab = XNEW (templates);
252b5132
RH		 2575 core_optab->start = optab;
2576 }
2577 }
2578 }
2579
47926f60 2580 /* Initialize reg_hash hash table. */
252b5132
RH		 2581 reg_hash = hash_new ();
2582 {
29b0f896 2583 const reg_entry *regtab;
c3fe08fa 2584 unsigned int regtab_size = i386_regtab_size;
252b5132 2585
c3fe08fa 2586 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2587 {
5a49b8ac 2588 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2589 if (hash_err)
b37df7c4 2590 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2591 regtab->reg_name,
2592 hash_err);
252b5132
RH		 2593 }
2594 }
2595
47926f60 2596 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2597 {
29b0f896
AM		 2598 int c;
2599 char *p;
252b5132
RH		 2600
2601 for (c = 0; c < 256; c++)
2602 {
3882b010 2603 if (ISDIGIT (c))
252b5132
RH		 2604 {
2605 digit_chars[c] = c;
2606 mnemonic_chars[c] = c;
2607 register_chars[c] = c;
2608 operand_chars[c] = c;
2609 }
3882b010 2610 else if (ISLOWER (c))
252b5132
RH		 2611 {
2612 mnemonic_chars[c] = c;
2613 register_chars[c] = c;
2614 operand_chars[c] = c;
2615 }
3882b010 2616 else if (ISUPPER (c))
252b5132 2617 {
3882b010 2618 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2619 register_chars[c] = mnemonic_chars[c];
2620 operand_chars[c] = c;
2621 }
43234a1e
L		 2622 else if (c == '{' || c == '}')
2623 operand_chars[c] = c;
252b5132 2624
3882b010 2625 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2626 identifier_chars[c] = c;
2627 else if (c >= 128)
2628 {
2629 identifier_chars[c] = c;
2630 operand_chars[c] = c;
2631 }
2632 }
2633
2634#ifdef LEX_AT
2635 identifier_chars['@'] = '@';
32137342
NC		 2636#endif
2637#ifdef LEX_QM
2638 identifier_chars['?'] = '?';
2639 operand_chars['?'] = '?';
252b5132 2640#endif
252b5132 2641 digit_chars['-'] = '-';
c0f3af97 2642 mnemonic_chars['_'] = '_';
791fe849 2643 mnemonic_chars['-'] = '-';
0003779b 2644 mnemonic_chars['.'] = '.';
252b5132
RH		 2645 identifier_chars['_'] = '_';
2646 identifier_chars['.'] = '.';
2647
2648 for (p = operand_special_chars; *p != '\0'; p++)
2649 operand_chars[(unsigned char) *p] = *p;
2650 }
2651
a4447b93
RH		 2652 if (flag_code == CODE_64BIT)
2653 {
ca19b261
KT		 2654#if defined (OBJ_COFF) && defined (TE_PE)
2655 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2656 ? 32 : 16);
2657#else
a4447b93 2658 x86_dwarf2_return_column = 16;
ca19b261 2659#endif
61ff971f 2660 x86_cie_data_alignment = -8;
a4447b93
RH		 2661 }
2662 else
2663 {
2664 x86_dwarf2_return_column = 8;
2665 x86_cie_data_alignment = -4;
2666 }
252b5132
RH		 2667}
2668
2669void
e3bb37b5 2670i386_print_statistics (FILE *file)
252b5132
RH		 2671{
2672 hash_print_statistics (file, "i386 opcode", op_hash);
2673 hash_print_statistics (file, "i386 register", reg_hash);
2674}
2675\f
252b5132
RH		 2676#ifdef DEBUG386
2677
ce8a8b2f 2678/* Debugging routines for md_assemble. */
d3ce72d0 2679static void pte (insn_template *);
40fb9820 2680static void pt (i386_operand_type);
e3bb37b5
L		 2681static void pe (expressionS *);
2682static void ps (symbolS *);
252b5132
RH		 2683
2684static void
e3bb37b5 2685pi (char *line, i386_insn *x)
252b5132 2686{
09137c09 2687 unsigned int j;
252b5132
RH		 2688
2689 fprintf (stdout, "%s: template ", line);
2690 pte (&x->tm);
09f131f2
JH		 2691 fprintf (stdout, " address: base %s index %s scale %x\n",
2692 x->base_reg ? x->base_reg->reg_name : "none",
2693 x->index_reg ? x->index_reg->reg_name : "none",
2694 x->log2_scale_factor);
2695 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2696 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2697 fprintf (stdout, " sib: base %x index %x scale %x\n",
2698 x->sib.base, x->sib.index, x->sib.scale);
2699 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2700 (x->rex & REX_W) != 0,
2701 (x->rex & REX_R) != 0,
2702 (x->rex & REX_X) != 0,
2703 (x->rex & REX_B) != 0);
09137c09 2704 for (j = 0; j < x->operands; j++)
252b5132 2705 {
09137c09
SP		 2706 fprintf (stdout, " #%d: ", j + 1);
2707 pt (x->types[j]);
252b5132 2708 fprintf (stdout, "\n");
09137c09
SP		 2709 if (x->types[j].bitfield.reg8
2710 || x->types[j].bitfield.reg16
2711 || x->types[j].bitfield.reg32
2712 || x->types[j].bitfield.reg64
2713 || x->types[j].bitfield.regmmx
2714 || x->types[j].bitfield.regxmm
2715 || x->types[j].bitfield.regymm
43234a1e 2716 || x->types[j].bitfield.regzmm
09137c09
SP		 2717 || x->types[j].bitfield.sreg2
2718 || x->types[j].bitfield.sreg3
2719 || x->types[j].bitfield.control
2720 || x->types[j].bitfield.debug
2721 || x->types[j].bitfield.test)
2722 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2723 if (operand_type_check (x->types[j], imm))
2724 pe (x->op[j].imms);
2725 if (operand_type_check (x->types[j], disp))
2726 pe (x->op[j].disps);
252b5132
RH		 2727 }
2728}
2729
2730static void
d3ce72d0 2731pte (insn_template *t)
252b5132 2732{
09137c09 2733 unsigned int j;
252b5132 2734 fprintf (stdout, " %d operands ", t->operands);
47926f60 2735 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2736 if (t->extension_opcode != None)
2737 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2738 if (t->opcode_modifier.d)
252b5132 2739 fprintf (stdout, "D");
40fb9820 2740 if (t->opcode_modifier.w)
252b5132
RH		 2741 fprintf (stdout, "W");
2742 fprintf (stdout, "\n");
09137c09 2743 for (j = 0; j < t->operands; j++)
252b5132 2744 {
09137c09
SP		 2745 fprintf (stdout, " #%d type ", j + 1);
2746 pt (t->operand_types[j]);
252b5132
RH		 2747 fprintf (stdout, "\n");
2748 }
2749}
2750
2751static void
e3bb37b5 2752pe (expressionS *e)
252b5132 2753{
24eab124 2754 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2755 fprintf (stdout, " add_number %ld (%lx)\n",
2756 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2757 if (e->X_add_symbol)
2758 {
2759 fprintf (stdout, " add_symbol ");
2760 ps (e->X_add_symbol);
2761 fprintf (stdout, "\n");
2762 }
2763 if (e->X_op_symbol)
2764 {
2765 fprintf (stdout, " op_symbol ");
2766 ps (e->X_op_symbol);
2767 fprintf (stdout, "\n");
2768 }
2769}
2770
2771static void
e3bb37b5 2772ps (symbolS *s)
252b5132
RH		 2773{
2774 fprintf (stdout, "%s type %s%s",
2775 S_GET_NAME (s),
2776 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2777 segment_name (S_GET_SEGMENT (s)));
2778}
2779
7b81dfbb 2780static struct type_name
252b5132 2781 {
40fb9820
L		 2782 i386_operand_type mask;
2783 const char *name;
252b5132 2784 }
7b81dfbb 2785const type_names[] =
252b5132 2786{
40fb9820
L		 2787 { OPERAND_TYPE_REG8, "r8" },
2788 { OPERAND_TYPE_REG16, "r16" },
2789 { OPERAND_TYPE_REG32, "r32" },
2790 { OPERAND_TYPE_REG64, "r64" },
2791 { OPERAND_TYPE_IMM8, "i8" },
2792 { OPERAND_TYPE_IMM8, "i8s" },
2793 { OPERAND_TYPE_IMM16, "i16" },
2794 { OPERAND_TYPE_IMM32, "i32" },
2795 { OPERAND_TYPE_IMM32S, "i32s" },
2796 { OPERAND_TYPE_IMM64, "i64" },
2797 { OPERAND_TYPE_IMM1, "i1" },
2798 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2799 { OPERAND_TYPE_DISP8, "d8" },
2800 { OPERAND_TYPE_DISP16, "d16" },
2801 { OPERAND_TYPE_DISP32, "d32" },
2802 { OPERAND_TYPE_DISP32S, "d32s" },
2803 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2804 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2805 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2806 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2807 { OPERAND_TYPE_CONTROL, "control reg" },
2808 { OPERAND_TYPE_TEST, "test reg" },
2809 { OPERAND_TYPE_DEBUG, "debug reg" },
2810 { OPERAND_TYPE_FLOATREG, "FReg" },
2811 { OPERAND_TYPE_FLOATACC, "FAcc" },
2812 { OPERAND_TYPE_SREG2, "SReg2" },
2813 { OPERAND_TYPE_SREG3, "SReg3" },
2814 { OPERAND_TYPE_ACC, "Acc" },
2815 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2816 { OPERAND_TYPE_REGMMX, "rMMX" },
2817 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2818 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2819 { OPERAND_TYPE_REGZMM, "rZMM" },
2820 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2821 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2822};
2823
2824static void
40fb9820 2825pt (i386_operand_type t)
252b5132 2826{
40fb9820 2827 unsigned int j;
c6fb90c8 2828 i386_operand_type a;
252b5132 2829
40fb9820 2830 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2831 {
2832 a = operand_type_and (t, type_names[j].mask);
0349dc08 2833 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2834 fprintf (stdout, "%s, ", type_names[j].name);
2835 }
252b5132
RH		 2836 fflush (stdout);
2837}
2838
2839#endif /* DEBUG386 */
2840\f
252b5132 2841static bfd_reloc_code_real_type
3956db08 2842reloc (unsigned int size,
64e74474
AM		 2843 int pcrel,
2844 int sign,
2845 bfd_reloc_code_real_type other)
252b5132 2846{
47926f60 2847 if (other != NO_RELOC)
3956db08 2848 {
91d6fa6a 2849 reloc_howto_type *rel;
3956db08
JB		 2850
2851 if (size == 8)
2852 switch (other)
2853 {
64e74474
AM		 2854 case BFD_RELOC_X86_64_GOT32:
2855 return BFD_RELOC_X86_64_GOT64;
2856 break;
553d1284
L		 2857 case BFD_RELOC_X86_64_GOTPLT64:
2858 return BFD_RELOC_X86_64_GOTPLT64;
2859 break;
64e74474
AM		 2860 case BFD_RELOC_X86_64_PLTOFF64:
2861 return BFD_RELOC_X86_64_PLTOFF64;
2862 break;
2863 case BFD_RELOC_X86_64_GOTPC32:
2864 other = BFD_RELOC_X86_64_GOTPC64;
2865 break;
2866 case BFD_RELOC_X86_64_GOTPCREL:
2867 other = BFD_RELOC_X86_64_GOTPCREL64;
2868 break;
2869 case BFD_RELOC_X86_64_TPOFF32:
2870 other = BFD_RELOC_X86_64_TPOFF64;
2871 break;
2872 case BFD_RELOC_X86_64_DTPOFF32:
2873 other = BFD_RELOC_X86_64_DTPOFF64;
2874 break;
2875 default:
2876 break;
3956db08 2877 }
e05278af 2878
8ce3d284 2879#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2880 if (other == BFD_RELOC_SIZE32)
2881 {
2882 if (size == 8)
1ab668bf 2883 other = BFD_RELOC_SIZE64;
8fd4256d 2884 if (pcrel)
1ab668bf
AM		 2885 {
2886 as_bad (_("there are no pc-relative size relocations"));
2887 return NO_RELOC;
2888 }
8fd4256d 2889 }
8ce3d284 2890#endif
8fd4256d 2891
e05278af 2892 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2893 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2894 sign = -1;
2895
91d6fa6a
NC		 2896 rel = bfd_reloc_type_lookup (stdoutput, other);
2897 if (!rel)
3956db08 2898 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2899 else if (size != bfd_get_reloc_size (rel))
3956db08 2900 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2901 bfd_get_reloc_size (rel),
3956db08 2902 size);
91d6fa6a 2903 else if (pcrel && !rel->pc_relative)
3956db08 2904 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2905 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2906 && !sign)
91d6fa6a 2907 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2908 && sign > 0))
3956db08
JB		 2909 as_bad (_("relocated field and relocation type differ in signedness"));
2910 else
2911 return other;
2912 return NO_RELOC;
2913 }
252b5132
RH		 2914
2915 if (pcrel)
2916 {
3e73aa7c 2917 if (!sign)
3956db08 2918 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2919 switch (size)
2920 {
2921 case 1: return BFD_RELOC_8_PCREL;
2922 case 2: return BFD_RELOC_16_PCREL;
d258b828 2923 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2924 case 8: return BFD_RELOC_64_PCREL;
252b5132 2925 }
3956db08 2926 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2927 }
2928 else
2929 {
3956db08 2930 if (sign > 0)
e5cb08ac 2931 switch (size)
3e73aa7c
JH		 2932 {
2933 case 4: return BFD_RELOC_X86_64_32S;
2934 }
2935 else
2936 switch (size)
2937 {
2938 case 1: return BFD_RELOC_8;
2939 case 2: return BFD_RELOC_16;
2940 case 4: return BFD_RELOC_32;
2941 case 8: return BFD_RELOC_64;
2942 }
3956db08
JB		 2943 as_bad (_("cannot do %s %u byte relocation"),
2944 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2945 }
2946
0cc9e1d3 2947 return NO_RELOC;
252b5132
RH		 2948}
2949
47926f60
KH		 2950/* Here we decide which fixups can be adjusted to make them relative to
2951 the beginning of the section instead of the symbol. Basically we need
2952 to make sure that the dynamic relocations are done correctly, so in
2953 some cases we force the original symbol to be used. */
2954
252b5132 2955int
e3bb37b5 2956tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2957{
6d249963 2958#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2959 if (!IS_ELF)
31312f95
AM		 2960 return 1;
2961
a161fe53
AM		 2962 /* Don't adjust pc-relative references to merge sections in 64-bit
2963 mode. */
2964 if (use_rela_relocations
2965 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2966 && fixP->fx_pcrel)
252b5132 2967 return 0;
31312f95 2968
8d01d9a9
AJ		 2969 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2970 and changed later by validate_fix. */
2971 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2972 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2973 return 0;
2974
8fd4256d
L		 2975 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2976 for size relocations. */
2977 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2978 || fixP->fx_r_type == BFD_RELOC_SIZE64
2979 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2980 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2981 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 2982 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 2983 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2984 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2985 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2986 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2987 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2988 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2989 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2990 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2991 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2992 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2993 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2994 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2995 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 2996 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
2997 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 2998 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2999 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3000 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3001 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3002 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3003 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3004 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3005 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3006 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3007 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3008 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3009 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3010 return 0;
31312f95 3011#endif
252b5132
RH		 3012 return 1;
3013}
252b5132 3014
b4cac588 3015static int
e3bb37b5 3016intel_float_operand (const char *mnemonic)
252b5132 3017{
9306ca4a
JB		 3018 /* Note that the value returned is meaningful only for opcodes with (memory)
3019 operands, hence the code here is free to improperly handle opcodes that
3020 have no operands (for better performance and smaller code). */
3021
3022 if (mnemonic[0] != 'f')
3023 return 0; /* non-math */
3024
3025 switch (mnemonic[1])
3026 {
3027 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3028 the fs segment override prefix not currently handled because no
3029 call path can make opcodes without operands get here */
3030 case 'i':
3031 return 2 /* integer op */;
3032 case 'l':
3033 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3034 return 3; /* fldcw/fldenv */
3035 break;
3036 case 'n':
3037 if (mnemonic[2] != 'o' /* fnop */)
3038 return 3; /* non-waiting control op */
3039 break;
3040 case 'r':
3041 if (mnemonic[2] == 's')
3042 return 3; /* frstor/frstpm */
3043 break;
3044 case 's':
3045 if (mnemonic[2] == 'a')
3046 return 3; /* fsave */
3047 if (mnemonic[2] == 't')
3048 {
3049 switch (mnemonic[3])
3050 {
3051 case 'c': /* fstcw */
3052 case 'd': /* fstdw */
3053 case 'e': /* fstenv */
3054 case 's': /* fsts[gw] */
3055 return 3;
3056 }
3057 }
3058 break;
3059 case 'x':
3060 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3061 return 0; /* fxsave/fxrstor are not really math ops */
3062 break;
3063 }
252b5132 3064
9306ca4a 3065 return 1;
252b5132
RH		 3066}
3067
c0f3af97
L		 3068/* Build the VEX prefix. */
3069
3070static void
d3ce72d0 3071build_vex_prefix (const insn_template *t)
c0f3af97
L		 3072{
3073 unsigned int register_specifier;
3074 unsigned int implied_prefix;
3075 unsigned int vector_length;
3076
3077 /* Check register specifier. */
3078 if (i.vex.register_specifier)
43234a1e
L		 3079 {
3080 register_specifier =
3081 ~register_number (i.vex.register_specifier) & 0xf;
3082 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3083 }
c0f3af97
L		 3084 else
3085 register_specifier = 0xf;
3086
fa99fab2
L		 3087 /* Use 2-byte VEX prefix by swappping destination and source
3088 operand. */
3089 if (!i.swap_operand
3090 && i.operands == i.reg_operands
7f399153 3091 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3092 && i.tm.opcode_modifier.s
3093 && i.rex == REX_B)
3094 {
3095 unsigned int xchg = i.operands - 1;
3096 union i386_op temp_op;
3097 i386_operand_type temp_type;
3098
3099 temp_type = i.types[xchg];
3100 i.types[xchg] = i.types[0];
3101 i.types[0] = temp_type;
3102 temp_op = i.op[xchg];
3103 i.op[xchg] = i.op[0];
3104 i.op[0] = temp_op;
3105
9c2799c2 3106 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3107
3108 i.rex = REX_R;
3109 xchg = i.rm.regmem;
3110 i.rm.regmem = i.rm.reg;
3111 i.rm.reg = xchg;
3112
3113 /* Use the next insn. */
3114 i.tm = t[1];
3115 }
3116
539f890d
L		 3117 if (i.tm.opcode_modifier.vex == VEXScalar)
3118 vector_length = avxscalar;
3119 else
3120 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3121
3122 switch ((i.tm.base_opcode >> 8) & 0xff)
3123 {
3124 case 0:
3125 implied_prefix = 0;
3126 break;
3127 case DATA_PREFIX_OPCODE:
3128 implied_prefix = 1;
3129 break;
3130 case REPE_PREFIX_OPCODE:
3131 implied_prefix = 2;
3132 break;
3133 case REPNE_PREFIX_OPCODE:
3134 implied_prefix = 3;
3135 break;
3136 default:
3137 abort ();
3138 }
3139
3140 /* Use 2-byte VEX prefix if possible. */
7f399153 3141 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3142 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3143 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3144 {
3145 /* 2-byte VEX prefix. */
3146 unsigned int r;
3147
3148 i.vex.length = 2;
3149 i.vex.bytes[0] = 0xc5;
3150
3151 /* Check the REX.R bit. */
3152 r = (i.rex & REX_R) ? 0 : 1;
3153 i.vex.bytes[1] = (r << 7
3154 | register_specifier << 3
3155 | vector_length << 2
3156 | implied_prefix);
3157 }
3158 else
3159 {
3160 /* 3-byte VEX prefix. */
3161 unsigned int m, w;
3162
f88c9eb0 3163 i.vex.length = 3;
f88c9eb0 3164
7f399153 3165 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3166 {
7f399153
L		 3167 case VEX0F:
3168 m = 0x1;
80de6e00 3169 i.vex.bytes[0] = 0xc4;
7f399153
L		 3170 break;
3171 case VEX0F38:
3172 m = 0x2;
80de6e00 3173 i.vex.bytes[0] = 0xc4;
7f399153
L		 3174 break;
3175 case VEX0F3A:
3176 m = 0x3;
80de6e00 3177 i.vex.bytes[0] = 0xc4;
7f399153
L		 3178 break;
3179 case XOP08:
5dd85c99
SP		 3180 m = 0x8;
3181 i.vex.bytes[0] = 0x8f;
7f399153
L		 3182 break;
3183 case XOP09:
f88c9eb0
SP		 3184 m = 0x9;
3185 i.vex.bytes[0] = 0x8f;
7f399153
L		 3186 break;
3187 case XOP0A:
f88c9eb0
SP		 3188 m = 0xa;
3189 i.vex.bytes[0] = 0x8f;
7f399153
L		 3190 break;
3191 default:
3192 abort ();
f88c9eb0 3193 }
c0f3af97 3194
c0f3af97
L		 3195 /* The high 3 bits of the second VEX byte are 1's compliment
3196 of RXB bits from REX. */
3197 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3198
3199 /* Check the REX.W bit. */
3200 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3201 if (i.tm.opcode_modifier.vexw == VEXW1)
3202 w = 1;
c0f3af97
L		 3203
3204 i.vex.bytes[2] = (w << 7
3205 | register_specifier << 3
3206 | vector_length << 2
3207 | implied_prefix);
3208 }
3209}
3210
43234a1e
L		 3211/* Build the EVEX prefix. */
3212
3213static void
3214build_evex_prefix (void)
3215{
3216 unsigned int register_specifier;
3217 unsigned int implied_prefix;
3218 unsigned int m, w;
3219 rex_byte vrex_used = 0;
3220
3221 /* Check register specifier. */
3222 if (i.vex.register_specifier)
3223 {
3224 gas_assert ((i.vrex & REX_X) == 0);
3225
3226 register_specifier = i.vex.register_specifier->reg_num;
3227 if ((i.vex.register_specifier->reg_flags & RegRex))
3228 register_specifier += 8;
3229 /* The upper 16 registers are encoded in the fourth byte of the
3230 EVEX prefix. */
3231 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3232 i.vex.bytes[3] = 0x8;
3233 register_specifier = ~register_specifier & 0xf;
3234 }
3235 else
3236 {
3237 register_specifier = 0xf;
3238
3239 /* Encode upper 16 vector index register in the fourth byte of
3240 the EVEX prefix. */
3241 if (!(i.vrex & REX_X))
3242 i.vex.bytes[3] = 0x8;
3243 else
3244 vrex_used |= REX_X;
3245 }
3246
3247 switch ((i.tm.base_opcode >> 8) & 0xff)
3248 {
3249 case 0:
3250 implied_prefix = 0;
3251 break;
3252 case DATA_PREFIX_OPCODE:
3253 implied_prefix = 1;
3254 break;
3255 case REPE_PREFIX_OPCODE:
3256 implied_prefix = 2;
3257 break;
3258 case REPNE_PREFIX_OPCODE:
3259 implied_prefix = 3;
3260 break;
3261 default:
3262 abort ();
3263 }
3264
3265 /* 4 byte EVEX prefix. */
3266 i.vex.length = 4;
3267 i.vex.bytes[0] = 0x62;
3268
3269 /* mmmm bits. */
3270 switch (i.tm.opcode_modifier.vexopcode)
3271 {
3272 case VEX0F:
3273 m = 1;
3274 break;
3275 case VEX0F38:
3276 m = 2;
3277 break;
3278 case VEX0F3A:
3279 m = 3;
3280 break;
3281 default:
3282 abort ();
3283 break;
3284 }
3285
3286 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3287 bits from REX. */
3288 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3289
3290 /* The fifth bit of the second EVEX byte is 1's compliment of the
3291 REX_R bit in VREX. */
3292 if (!(i.vrex & REX_R))
3293 i.vex.bytes[1] |= 0x10;
3294 else
3295 vrex_used |= REX_R;
3296
3297 if ((i.reg_operands + i.imm_operands) == i.operands)
3298 {
3299 /* When all operands are registers, the REX_X bit in REX is not
3300 used. We reuse it to encode the upper 16 registers, which is
3301 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3302 as 1's compliment. */
3303 if ((i.vrex & REX_B))
3304 {
3305 vrex_used |= REX_B;
3306 i.vex.bytes[1] &= ~0x40;
3307 }
3308 }
3309
3310 /* EVEX instructions shouldn't need the REX prefix. */
3311 i.vrex &= ~vrex_used;
3312 gas_assert (i.vrex == 0);
3313
3314 /* Check the REX.W bit. */
3315 w = (i.rex & REX_W) ? 1 : 0;
3316 if (i.tm.opcode_modifier.vexw)
3317 {
3318 if (i.tm.opcode_modifier.vexw == VEXW1)
3319 w = 1;
3320 }
3321 /* If w is not set it means we are dealing with WIG instruction. */
3322 else if (!w)
3323 {
3324 if (evexwig == evexw1)
3325 w = 1;
3326 }
3327
3328 /* Encode the U bit. */
3329 implied_prefix |= 0x4;
3330
3331 /* The third byte of the EVEX prefix. */
3332 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3333
3334 /* The fourth byte of the EVEX prefix. */
3335 /* The zeroing-masking bit. */
3336 if (i.mask && i.mask->zeroing)
3337 i.vex.bytes[3] |= 0x80;
3338
3339 /* Don't always set the broadcast bit if there is no RC. */
3340 if (!i.rounding)
3341 {
3342 /* Encode the vector length. */
3343 unsigned int vec_length;
3344
3345 switch (i.tm.opcode_modifier.evex)
3346 {
3347 case EVEXLIG: /* LL' is ignored */
3348 vec_length = evexlig << 5;
3349 break;
3350 case EVEX128:
3351 vec_length = 0 << 5;
3352 break;
3353 case EVEX256:
3354 vec_length = 1 << 5;
3355 break;
3356 case EVEX512:
3357 vec_length = 2 << 5;
3358 break;
3359 default:
3360 abort ();
3361 break;
3362 }
3363 i.vex.bytes[3] |= vec_length;
3364 /* Encode the broadcast bit. */
3365 if (i.broadcast)
3366 i.vex.bytes[3] |= 0x10;
3367 }
3368 else
3369 {
3370 if (i.rounding->type != saeonly)
3371 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3372 else
d3d3c6db 3373 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3374 }
3375
3376 if (i.mask && i.mask->mask)
3377 i.vex.bytes[3] |= i.mask->mask->reg_num;
3378}
3379
65da13b5
L		 3380static void
3381process_immext (void)
3382{
3383 expressionS *exp;
3384
4c692bc7
JB		 3385 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3386 && i.operands > 0)
65da13b5 3387 {
4c692bc7
JB		 3388 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3389 with an opcode suffix which is coded in the same place as an
3390 8-bit immediate field would be.
3391 Here we check those operands and remove them afterwards. */
65da13b5
L		 3392 unsigned int x;
3393
3394 for (x = 0; x < i.operands; x++)
4c692bc7 3395 if (register_number (i.op[x].regs) != x)
65da13b5 3396 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3397 register_prefix, i.op[x].regs->reg_name, x + 1,
3398 i.tm.name);
3399
3400 i.operands = 0;
65da13b5
L		 3401 }
3402
9916071f
AP		 3403 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3404 {
3405 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3406 suffix which is coded in the same place as an 8-bit immediate
3407 field would be.
3408 Here we check those operands and remove them afterwards. */
3409 unsigned int x;
3410
3411 if (i.operands != 3)
3412 abort();
3413
3414 for (x = 0; x < 2; x++)
3415 if (register_number (i.op[x].regs) != x)
3416 goto bad_register_operand;
3417
3418 /* Check for third operand for mwaitx/monitorx insn. */
3419 if (register_number (i.op[x].regs)
3420 != (x + (i.tm.extension_opcode == 0xfb)))
3421 {
3422bad_register_operand:
3423 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3424 register_prefix, i.op[x].regs->reg_name, x+1,
3425 i.tm.name);
3426 }
3427
3428 i.operands = 0;
3429 }
3430
c0f3af97 3431 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3432 which is coded in the same place as an 8-bit immediate field
3433 would be. Here we fake an 8-bit immediate operand from the
3434 opcode suffix stored in tm.extension_opcode.
3435
c1e679ec 3436 AVX instructions also use this encoding, for some of
c0f3af97 3437 3 argument instructions. */
65da13b5 3438
43234a1e 3439 gas_assert (i.imm_operands <= 1
7ab9ffdd 3440 && (i.operands <= 2
43234a1e
L		 3441 || ((i.tm.opcode_modifier.vex
3442 || i.tm.opcode_modifier.evex)
7ab9ffdd 3443 && i.operands <= 4)));
65da13b5
L		 3444
3445 exp = &im_expressions[i.imm_operands++];
3446 i.op[i.operands].imms = exp;
3447 i.types[i.operands] = imm8;
3448 i.operands++;
3449 exp->X_op = O_constant;
3450 exp->X_add_number = i.tm.extension_opcode;
3451 i.tm.extension_opcode = None;
3452}
3453
42164a71
L		 3454
3455static int
3456check_hle (void)
3457{
3458 switch (i.tm.opcode_modifier.hleprefixok)
3459 {
3460 default:
3461 abort ();
82c2def5 3462 case HLEPrefixNone:
165de32a
L		 3463 as_bad (_("invalid instruction `%s' after `%s'"),
3464 i.tm.name, i.hle_prefix);
42164a71 3465 return 0;
82c2def5 3466 case HLEPrefixLock:
42164a71
L		 3467 if (i.prefix[LOCK_PREFIX])
3468 return 1;
165de32a 3469 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3470 return 0;
82c2def5 3471 case HLEPrefixAny:
42164a71 3472 return 1;
82c2def5 3473 case HLEPrefixRelease:
42164a71
L		 3474 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3475 {
3476 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3477 i.tm.name);
3478 return 0;
3479 }
3480 if (i.mem_operands == 0
3481 || !operand_type_check (i.types[i.operands - 1], anymem))
3482 {
3483 as_bad (_("memory destination needed for instruction `%s'"
3484 " after `xrelease'"), i.tm.name);
3485 return 0;
3486 }
3487 return 1;
3488 }
3489}
3490
252b5132
RH		 3491/* This is the guts of the machine-dependent assembler. LINE points to a
3492 machine dependent instruction. This function is supposed to emit
3493 the frags/bytes it assembles to. */
3494
3495void
65da13b5 3496md_assemble (char *line)
252b5132 3497{
40fb9820 3498 unsigned int j;
252b5132 3499 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3500 const insn_template *t;
252b5132 3501
47926f60 3502 /* Initialize globals. */
252b5132
RH		 3503 memset (&i, '\0', sizeof (i));
3504 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3505 i.reloc[j] = NO_RELOC;
252b5132
RH		 3506 memset (disp_expressions, '\0', sizeof (disp_expressions));
3507 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3508 save_stack_p = save_stack;
252b5132
RH		 3509
3510 /* First parse an instruction mnemonic & call i386_operand for the operands.
3511 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3512 start of a (possibly prefixed) mnemonic. */
252b5132 3513
29b0f896
AM		 3514 line = parse_insn (line, mnemonic);
3515 if (line == NULL)
3516 return;
252b5132 3517
29b0f896 3518 line = parse_operands (line, mnemonic);
ee86248c 3519 this_operand = -1;
29b0f896
AM		 3520 if (line == NULL)
3521 return;
252b5132 3522
29b0f896
AM		 3523 /* Now we've parsed the mnemonic into a set of templates, and have the
3524 operands at hand. */
3525
3526 /* All intel opcodes have reversed operands except for "bound" and
3527 "enter". We also don't reverse intersegment "jmp" and "call"
3528 instructions with 2 immediate operands so that the immediate segment
050dfa73 3529 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3530 if (intel_syntax
3531 && i.operands > 1
29b0f896 3532 && (strcmp (mnemonic, "bound") != 0)
30123838 3533 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3534 && !(operand_type_check (i.types[0], imm)
3535 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3536 swap_operands ();
3537
ec56d5c0
JB		 3538 /* The order of the immediates should be reversed
3539 for 2 immediates extrq and insertq instructions */
3540 if (i.imm_operands == 2
3541 && (strcmp (mnemonic, "extrq") == 0
3542 || strcmp (mnemonic, "insertq") == 0))
3543 swap_2_operands (0, 1);
3544
29b0f896
AM		 3545 if (i.imm_operands)
3546 optimize_imm ();
3547
b300c311
L		 3548 /* Don't optimize displacement for movabs since it only takes 64bit
3549 displacement. */
3550 if (i.disp_operands
a501d77e 3551 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3552 && (flag_code != CODE_64BIT
3553 || strcmp (mnemonic, "movabs") != 0))
3554 optimize_disp ();
29b0f896
AM		 3555
3556 /* Next, we find a template that matches the given insn,
3557 making sure the overlap of the given operands types is consistent
3558 with the template operand types. */
252b5132 3559
fa99fab2 3560 if (!(t = match_template ()))
29b0f896 3561 return;
252b5132 3562
7bab8ab5 3563 if (sse_check != check_none
81f8a913 3564 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3565 && (i.tm.cpu_flags.bitfield.cpusse
3566 || i.tm.cpu_flags.bitfield.cpusse2
3567 || i.tm.cpu_flags.bitfield.cpusse3
3568 || i.tm.cpu_flags.bitfield.cpussse3
3569 || i.tm.cpu_flags.bitfield.cpusse4_1
3570 || i.tm.cpu_flags.bitfield.cpusse4_2))
3571 {
7bab8ab5 3572 (sse_check == check_warning
daf50ae7
L		 3573 ? as_warn
3574 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3575 }
3576
321fd21e
L		 3577 /* Zap movzx and movsx suffix. The suffix has been set from
3578 "word ptr" or "byte ptr" on the source operand in Intel syntax
3579 or extracted from mnemonic in AT&T syntax. But we'll use
3580 the destination register to choose the suffix for encoding. */
3581 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3582 {
321fd21e
L		 3583 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3584 there is no suffix, the default will be byte extension. */
3585 if (i.reg_operands != 2
3586 && !i.suffix
7ab9ffdd 3587 && intel_syntax)
321fd21e
L		 3588 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3589
3590 i.suffix = 0;
cd61ebfe 3591 }
24eab124 3592
40fb9820 3593 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3594 if (!add_prefix (FWAIT_OPCODE))
3595 return;
252b5132 3596
d5de92cf
L		 3597 /* Check if REP prefix is OK. */
3598 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3599 {
3600 as_bad (_("invalid instruction `%s' after `%s'"),
3601 i.tm.name, i.rep_prefix);
3602 return;
3603 }
3604
c1ba0266
L		 3605 /* Check for lock without a lockable instruction. Destination operand
3606 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3607 if (i.prefix[LOCK_PREFIX]
3608 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3609 || i.mem_operands == 0
3610 || (i.tm.base_opcode != 0x86
3611 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3612 {
3613 as_bad (_("expecting lockable instruction after `lock'"));
3614 return;
3615 }
3616
42164a71 3617 /* Check if HLE prefix is OK. */
165de32a 3618 if (i.hle_prefix && !check_hle ())
42164a71
L		 3619 return;
3620
7e8b059b
L		 3621 /* Check BND prefix. */
3622 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3623 as_bad (_("expecting valid branch instruction after `bnd'"));
3624
3625 if (i.tm.cpu_flags.bitfield.cpumpx
3626 && flag_code == CODE_64BIT
3627 && i.prefix[ADDR_PREFIX])
3628 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3629
3630 /* Insert BND prefix. */
3631 if (add_bnd_prefix
3632 && i.tm.opcode_modifier.bndprefixok
3633 && !i.prefix[BND_PREFIX])
3634 add_prefix (BND_PREFIX_OPCODE);
3635
29b0f896 3636 /* Check string instruction segment overrides. */
40fb9820 3637 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3638 {
3639 if (!check_string ())
5dd0794d 3640 return;
fc0763e6 3641 i.disp_operands = 0;
29b0f896 3642 }
5dd0794d 3643
29b0f896
AM		 3644 if (!process_suffix ())
3645 return;
e413e4e9 3646
bc0844ae
L		 3647 /* Update operand types. */
3648 for (j = 0; j < i.operands; j++)
3649 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3650
29b0f896
AM		 3651 /* Make still unresolved immediate matches conform to size of immediate
3652 given in i.suffix. */
3653 if (!finalize_imm ())
3654 return;
252b5132 3655
40fb9820 3656 if (i.types[0].bitfield.imm1)
29b0f896 3657 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3658
9afe6eb8
L		 3659 /* We only need to check those implicit registers for instructions
3660 with 3 operands or less. */
3661 if (i.operands <= 3)
3662 for (j = 0; j < i.operands; j++)
3663 if (i.types[j].bitfield.inoutportreg
3664 || i.types[j].bitfield.shiftcount
3665 || i.types[j].bitfield.acc
3666 || i.types[j].bitfield.floatacc)
3667 i.reg_operands--;
40fb9820 3668
c0f3af97
L		 3669 /* ImmExt should be processed after SSE2AVX. */
3670 if (!i.tm.opcode_modifier.sse2avx
3671 && i.tm.opcode_modifier.immext)
65da13b5 3672 process_immext ();
252b5132 3673
29b0f896
AM		 3674 /* For insns with operands there are more diddles to do to the opcode. */
3675 if (i.operands)
3676 {
3677 if (!process_operands ())
3678 return;
3679 }
40fb9820 3680 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3681 {
3682 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3683 as_warn (_("translating to `%sp'"), i.tm.name);
3684 }
252b5132 3685
9e5e5283
L		 3686 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3687 {
3688 if (flag_code == CODE_16BIT)
3689 {
3690 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3691 i.tm.name);
3692 return;
3693 }
c0f3af97 3694
9e5e5283
L		 3695 if (i.tm.opcode_modifier.vex)
3696 build_vex_prefix (t);
3697 else
3698 build_evex_prefix ();
3699 }
43234a1e 3700
5dd85c99
SP		 3701 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3702 instructions may define INT_OPCODE as well, so avoid this corner
3703 case for those instructions that use MODRM. */
3704 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3705 && !i.tm.opcode_modifier.modrm
3706 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3707 {
3708 i.tm.base_opcode = INT3_OPCODE;
3709 i.imm_operands = 0;
3710 }
252b5132 3711
40fb9820
L		 3712 if ((i.tm.opcode_modifier.jump
3713 || i.tm.opcode_modifier.jumpbyte
3714 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3715 && i.op[0].disps->X_op == O_constant)
3716 {
3717 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3718 the absolute address given by the constant. Since ix86 jumps and
3719 calls are pc relative, we need to generate a reloc. */
3720 i.op[0].disps->X_add_symbol = &abs_symbol;
3721 i.op[0].disps->X_op = O_symbol;
3722 }
252b5132 3723
40fb9820 3724 if (i.tm.opcode_modifier.rex64)
161a04f6 3725 i.rex |= REX_W;
252b5132 3726
29b0f896
AM		 3727 /* For 8 bit registers we need an empty rex prefix. Also if the
3728 instruction already has a prefix, we need to convert old
3729 registers to new ones. */
773f551c 3730
40fb9820 3731 if ((i.types[0].bitfield.reg8
29b0f896 3732 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3733 || (i.types[1].bitfield.reg8
29b0f896 3734 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3735 || ((i.types[0].bitfield.reg8
3736 || i.types[1].bitfield.reg8)
29b0f896
AM		 3737 && i.rex != 0))
3738 {
3739 int x;
726c5dcd 3740
29b0f896
AM		 3741 i.rex |= REX_OPCODE;
3742 for (x = 0; x < 2; x++)
3743 {
3744 /* Look for 8 bit operand that uses old registers. */
40fb9820 3745 if (i.types[x].bitfield.reg8
29b0f896 3746 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3747 {
29b0f896
AM		 3748 /* In case it is "hi" register, give up. */
3749 if (i.op[x].regs->reg_num > 3)
a540244d 3750 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3751 "instruction requiring REX prefix."),
a540244d 3752 register_prefix, i.op[x].regs->reg_name);
773f551c 3753
29b0f896
AM		 3754 /* Otherwise it is equivalent to the extended register.
3755 Since the encoding doesn't change this is merely
3756 cosmetic cleanup for debug output. */
3757
3758 i.op[x].regs = i.op[x].regs + 8;
773f551c 3759 }
29b0f896
AM		 3760 }
3761 }
773f551c 3762
7ab9ffdd 3763 if (i.rex != 0)
29b0f896
AM		 3764 add_prefix (REX_OPCODE | i.rex);
3765
3766 /* We are ready to output the insn. */
3767 output_insn ();
3768}
3769
3770static char *
e3bb37b5 3771parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3772{
3773 char *l = line;
3774 char *token_start = l;
3775 char *mnem_p;
5c6af06e 3776 int supported;
d3ce72d0 3777 const insn_template *t;
b6169b20 3778 char *dot_p = NULL;
29b0f896 3779
29b0f896
AM		 3780 while (1)
3781 {
3782 mnem_p = mnemonic;
3783 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3784 {
b6169b20
L		 3785 if (*mnem_p == '.')
3786 dot_p = mnem_p;
29b0f896
AM		 3787 mnem_p++;
3788 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3789 {
29b0f896
AM		 3790 as_bad (_("no such instruction: `%s'"), token_start);
3791 return NULL;
3792 }
3793 l++;
3794 }
3795 if (!is_space_char (*l)
3796 && *l != END_OF_INSN
e44823cf
JB		 3797 && (intel_syntax
3798 || (*l != PREFIX_SEPARATOR
3799 && *l != ',')))
29b0f896
AM		 3800 {
3801 as_bad (_("invalid character %s in mnemonic"),
3802 output_invalid (*l));
3803 return NULL;
3804 }
3805 if (token_start == l)
3806 {
e44823cf 3807 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3808 as_bad (_("expecting prefix; got nothing"));
3809 else
3810 as_bad (_("expecting mnemonic; got nothing"));
3811 return NULL;
3812 }
45288df1 3813
29b0f896 3814 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3815 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3816
29b0f896
AM		 3817 if (*l != END_OF_INSN
3818 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3819 && current_templates
40fb9820 3820 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3821 {
c6fb90c8 3822 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3823 {
3824 as_bad ((flag_code != CODE_64BIT
3825 ? _("`%s' is only supported in 64-bit mode")
3826 : _("`%s' is not supported in 64-bit mode")),
3827 current_templates->start->name);
3828 return NULL;
3829 }
29b0f896
AM		 3830 /* If we are in 16-bit mode, do not allow addr16 or data16.
3831 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3832 if ((current_templates->start->opcode_modifier.size16
3833 || current_templates->start->opcode_modifier.size32)
29b0f896 3834 && flag_code != CODE_64BIT
40fb9820 3835 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3836 ^ (flag_code == CODE_16BIT)))
3837 {
3838 as_bad (_("redundant %s prefix"),
3839 current_templates->start->name);
3840 return NULL;
45288df1 3841 }
29b0f896
AM		 3842 /* Add prefix, checking for repeated prefixes. */
3843 switch (add_prefix (current_templates->start->base_opcode))
3844 {
c32fa91d 3845 case PREFIX_EXIST:
29b0f896 3846 return NULL;
c32fa91d 3847 case PREFIX_REP:
42164a71 3848 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3849 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3850 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3851 i.bnd_prefix = current_templates->start->name;
42164a71 3852 else
d5de92cf 3853 i.rep_prefix = current_templates->start->name;
29b0f896 3854 break;
c32fa91d
L		 3855 default:
3856 break;
29b0f896
AM		 3857 }
3858 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3859 token_start = ++l;
3860 }
3861 else
3862 break;
3863 }
45288df1 3864
30a55f88 3865 if (!current_templates)
b6169b20 3866 {
f8a5c266
L		 3867 /* Check if we should swap operand or force 32bit displacement in
3868 encoding. */
30a55f88
L		 3869 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3870 i.swap_operand = 1;
8d63c93e 3871 else if (mnem_p - 3 == dot_p
a501d77e
L		 3872 && dot_p[1] == 'd'
3873 && dot_p[2] == '8')
3874 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3875 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3876 && dot_p[1] == 'd'
3877 && dot_p[2] == '3'
3878 && dot_p[3] == '2')
a501d77e 3879 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3880 else
3881 goto check_suffix;
3882 mnem_p = dot_p;
3883 *dot_p = '\0';
d3ce72d0 3884 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3885 }
3886
29b0f896
AM		 3887 if (!current_templates)
3888 {
b6169b20 3889check_suffix:
29b0f896
AM		 3890 /* See if we can get a match by trimming off a suffix. */
3891 switch (mnem_p[-1])
3892 {
3893 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3894 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3895 i.suffix = SHORT_MNEM_SUFFIX;
3896 else
29b0f896
AM		 3897 case BYTE_MNEM_SUFFIX:
3898 case QWORD_MNEM_SUFFIX:
3899 i.suffix = mnem_p[-1];
3900 mnem_p[-1] = '\0';
d3ce72d0
NC		 3901 current_templates = (const templates *) hash_find (op_hash,
3902 mnemonic);
29b0f896
AM		 3903 break;
3904 case SHORT_MNEM_SUFFIX:
3905 case LONG_MNEM_SUFFIX:
3906 if (!intel_syntax)
3907 {
3908 i.suffix = mnem_p[-1];
3909 mnem_p[-1] = '\0';
d3ce72d0
NC		 3910 current_templates = (const templates *) hash_find (op_hash,
3911 mnemonic);
29b0f896
AM		 3912 }
3913 break;
252b5132 3914
29b0f896
AM		 3915 /* Intel Syntax. */
3916 case 'd':
3917 if (intel_syntax)
3918 {
9306ca4a 3919 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3920 i.suffix = SHORT_MNEM_SUFFIX;
3921 else
3922 i.suffix = LONG_MNEM_SUFFIX;
3923 mnem_p[-1] = '\0';
d3ce72d0
NC		 3924 current_templates = (const templates *) hash_find (op_hash,
3925 mnemonic);
29b0f896
AM		 3926 }
3927 break;
3928 }
3929 if (!current_templates)
3930 {
3931 as_bad (_("no such instruction: `%s'"), token_start);
3932 return NULL;
3933 }
3934 }
252b5132 3935
40fb9820
L		 3936 if (current_templates->start->opcode_modifier.jump
3937 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3938 {
3939 /* Check for a branch hint. We allow ",pt" and ",pn" for
3940 predict taken and predict not taken respectively.
3941 I'm not sure that branch hints actually do anything on loop
3942 and jcxz insns (JumpByte) for current Pentium4 chips. They
3943 may work in the future and it doesn't hurt to accept them
3944 now. */
3945 if (l[0] == ',' && l[1] == 'p')
3946 {
3947 if (l[2] == 't')
3948 {
3949 if (!add_prefix (DS_PREFIX_OPCODE))
3950 return NULL;
3951 l += 3;
3952 }
3953 else if (l[2] == 'n')
3954 {
3955 if (!add_prefix (CS_PREFIX_OPCODE))
3956 return NULL;
3957 l += 3;
3958 }
3959 }
3960 }
3961 /* Any other comma loses. */
3962 if (*l == ',')
3963 {
3964 as_bad (_("invalid character %s in mnemonic"),
3965 output_invalid (*l));
3966 return NULL;
3967 }
252b5132 3968
29b0f896 3969 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3970 supported = 0;
3971 for (t = current_templates->start; t < current_templates->end; ++t)
3972 {
c0f3af97
L		 3973 supported |= cpu_flags_match (t);
3974 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3975 goto skip;
5c6af06e 3976 }
3629bb00 3977
c0f3af97 3978 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3979 {
3980 as_bad (flag_code == CODE_64BIT
3981 ? _("`%s' is not supported in 64-bit mode")
3982 : _("`%s' is only supported in 64-bit mode"),
3983 current_templates->start->name);
3984 return NULL;
3985 }
c0f3af97 3986 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3987 {
3629bb00 3988 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3989 current_templates->start->name,
41aacd83 3990 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3991 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3992 return NULL;
29b0f896 3993 }
3629bb00
L		 3994
3995skip:
3996 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3997 && (flag_code != CODE_16BIT))
29b0f896
AM		 3998 {
3999 as_warn (_("use .code16 to ensure correct addressing mode"));
4000 }
252b5132 4001
29b0f896
AM		 4002 return l;
4003}
252b5132 4004
29b0f896 4005static char *
e3bb37b5 4006parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4007{
4008 char *token_start;
3138f287 4009
29b0f896
AM		 4010 /* 1 if operand is pending after ','. */
4011 unsigned int expecting_operand = 0;
252b5132 4012
29b0f896
AM		 4013 /* Non-zero if operand parens not balanced. */
4014 unsigned int paren_not_balanced;
4015
4016 while (*l != END_OF_INSN)
4017 {
4018 /* Skip optional white space before operand. */
4019 if (is_space_char (*l))
4020 ++l;
d02603dc 4021 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4022 {
4023 as_bad (_("invalid character %s before operand %d"),
4024 output_invalid (*l),
4025 i.operands + 1);
4026 return NULL;
4027 }
d02603dc 4028 token_start = l; /* After white space. */
29b0f896
AM		 4029 paren_not_balanced = 0;
4030 while (paren_not_balanced || *l != ',')
4031 {
4032 if (*l == END_OF_INSN)
4033 {
4034 if (paren_not_balanced)
4035 {
4036 if (!intel_syntax)
4037 as_bad (_("unbalanced parenthesis in operand %d."),
4038 i.operands + 1);
4039 else
4040 as_bad (_("unbalanced brackets in operand %d."),
4041 i.operands + 1);
4042 return NULL;
4043 }
4044 else
4045 break; /* we are done */
4046 }
d02603dc 4047 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4048 {
4049 as_bad (_("invalid character %s in operand %d"),
4050 output_invalid (*l),
4051 i.operands + 1);
4052 return NULL;
4053 }
4054 if (!intel_syntax)
4055 {
4056 if (*l == '(')
4057 ++paren_not_balanced;
4058 if (*l == ')')
4059 --paren_not_balanced;
4060 }
4061 else
4062 {
4063 if (*l == '[')
4064 ++paren_not_balanced;
4065 if (*l == ']')
4066 --paren_not_balanced;
4067 }
4068 l++;
4069 }
4070 if (l != token_start)
4071 { /* Yes, we've read in another operand. */
4072 unsigned int operand_ok;
4073 this_operand = i.operands++;
7d5e4556 4074 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4075 if (i.operands > MAX_OPERANDS)
4076 {
4077 as_bad (_("spurious operands; (%d operands/instruction max)"),
4078 MAX_OPERANDS);
4079 return NULL;
4080 }
4081 /* Now parse operand adding info to 'i' as we go along. */
4082 END_STRING_AND_SAVE (l);
4083
4084 if (intel_syntax)
4085 operand_ok =
4086 i386_intel_operand (token_start,
4087 intel_float_operand (mnemonic));
4088 else
a7619375 4089 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4090
4091 RESTORE_END_STRING (l);
4092 if (!operand_ok)
4093 return NULL;
4094 }
4095 else
4096 {
4097 if (expecting_operand)
4098 {
4099 expecting_operand_after_comma:
4100 as_bad (_("expecting operand after ','; got nothing"));
4101 return NULL;
4102 }
4103 if (*l == ',')
4104 {
4105 as_bad (_("expecting operand before ','; got nothing"));
4106 return NULL;
4107 }
4108 }
7f3f1ea2 4109
29b0f896
AM		 4110 /* Now *l must be either ',' or END_OF_INSN. */
4111 if (*l == ',')
4112 {
4113 if (*++l == END_OF_INSN)
4114 {
4115 /* Just skip it, if it's \n complain. */
4116 goto expecting_operand_after_comma;
4117 }
4118 expecting_operand = 1;
4119 }
4120 }
4121 return l;
4122}
7f3f1ea2 4123
050dfa73 4124static void
4d456e3d 4125swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4126{
4127 union i386_op temp_op;
40fb9820 4128 i386_operand_type temp_type;
050dfa73 4129 enum bfd_reloc_code_real temp_reloc;
4eed87de 4130
050dfa73
MM		 4131 temp_type = i.types[xchg2];
4132 i.types[xchg2] = i.types[xchg1];
4133 i.types[xchg1] = temp_type;
4134 temp_op = i.op[xchg2];
4135 i.op[xchg2] = i.op[xchg1];
4136 i.op[xchg1] = temp_op;
4137 temp_reloc = i.reloc[xchg2];
4138 i.reloc[xchg2] = i.reloc[xchg1];
4139 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4140
4141 if (i.mask)
4142 {
4143 if (i.mask->operand == xchg1)
4144 i.mask->operand = xchg2;
4145 else if (i.mask->operand == xchg2)
4146 i.mask->operand = xchg1;
4147 }
4148 if (i.broadcast)
4149 {
4150 if (i.broadcast->operand == xchg1)
4151 i.broadcast->operand = xchg2;
4152 else if (i.broadcast->operand == xchg2)
4153 i.broadcast->operand = xchg1;
4154 }
4155 if (i.rounding)
4156 {
4157 if (i.rounding->operand == xchg1)
4158 i.rounding->operand = xchg2;
4159 else if (i.rounding->operand == xchg2)
4160 i.rounding->operand = xchg1;
4161 }
050dfa73
MM		 4162}
4163
29b0f896 4164static void
e3bb37b5 4165swap_operands (void)
29b0f896 4166{
b7c61d9a 4167 switch (i.operands)
050dfa73 4168 {
c0f3af97 4169 case 5:
b7c61d9a 4170 case 4:
4d456e3d 4171 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4172 case 3:
4173 case 2:
4d456e3d 4174 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4175 break;
4176 default:
4177 abort ();
29b0f896 4178 }
29b0f896
AM		 4179
4180 if (i.mem_operands == 2)
4181 {
4182 const seg_entry *temp_seg;
4183 temp_seg = i.seg[0];
4184 i.seg[0] = i.seg[1];
4185 i.seg[1] = temp_seg;
4186 }
4187}
252b5132 4188
29b0f896
AM		 4189/* Try to ensure constant immediates are represented in the smallest
4190 opcode possible. */
4191static void
e3bb37b5 4192optimize_imm (void)
29b0f896
AM		 4193{
4194 char guess_suffix = 0;
4195 int op;
252b5132 4196
29b0f896
AM		 4197 if (i.suffix)
4198 guess_suffix = i.suffix;
4199 else if (i.reg_operands)
4200 {
4201 /* Figure out a suffix from the last register operand specified.
4202 We can't do this properly yet, ie. excluding InOutPortReg,
4203 but the following works for instructions with immediates.
4204 In any case, we can't set i.suffix yet. */
4205 for (op = i.operands; --op >= 0;)
40fb9820 4206 if (i.types[op].bitfield.reg8)
7ab9ffdd 4207 {
40fb9820
L		 4208 guess_suffix = BYTE_MNEM_SUFFIX;
4209 break;
4210 }
4211 else if (i.types[op].bitfield.reg16)
252b5132 4212 {
40fb9820
L		 4213 guess_suffix = WORD_MNEM_SUFFIX;
4214 break;
4215 }
4216 else if (i.types[op].bitfield.reg32)
4217 {
4218 guess_suffix = LONG_MNEM_SUFFIX;
4219 break;
4220 }
4221 else if (i.types[op].bitfield.reg64)
4222 {
4223 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4224 break;
252b5132 4225 }
29b0f896
AM		 4226 }
4227 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4228 guess_suffix = WORD_MNEM_SUFFIX;
4229
4230 for (op = i.operands; --op >= 0;)
40fb9820 4231 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4232 {
4233 switch (i.op[op].imms->X_op)
252b5132 4234 {
29b0f896
AM		 4235 case O_constant:
4236 /* If a suffix is given, this operand may be shortened. */
4237 switch (guess_suffix)
252b5132 4238 {
29b0f896 4239 case LONG_MNEM_SUFFIX:
40fb9820
L		 4240 i.types[op].bitfield.imm32 = 1;
4241 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4242 break;
4243 case WORD_MNEM_SUFFIX:
40fb9820
L		 4244 i.types[op].bitfield.imm16 = 1;
4245 i.types[op].bitfield.imm32 = 1;
4246 i.types[op].bitfield.imm32s = 1;
4247 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4248 break;
4249 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4250 i.types[op].bitfield.imm8 = 1;
4251 i.types[op].bitfield.imm8s = 1;
4252 i.types[op].bitfield.imm16 = 1;
4253 i.types[op].bitfield.imm32 = 1;
4254 i.types[op].bitfield.imm32s = 1;
4255 i.types[op].bitfield.imm64 = 1;
29b0f896 4256 break;
252b5132 4257 }
252b5132 4258
29b0f896
AM		 4259 /* If this operand is at most 16 bits, convert it
4260 to a signed 16 bit number before trying to see
4261 whether it will fit in an even smaller size.
4262 This allows a 16-bit operand such as $0xffe0 to
4263 be recognised as within Imm8S range. */
40fb9820 4264 if ((i.types[op].bitfield.imm16)
29b0f896 4265 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4266 {
29b0f896
AM		 4267 i.op[op].imms->X_add_number =
4268 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4269 }
a28def75
L		 4270#ifdef BFD64
4271 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4272 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4273 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4274 == 0))
4275 {
4276 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4277 ^ ((offsetT) 1 << 31))
4278 - ((offsetT) 1 << 31));
4279 }
a28def75 4280#endif
40fb9820 4281 i.types[op]
c6fb90c8
L		 4282 = operand_type_or (i.types[op],
4283 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4284
29b0f896
AM		 4285 /* We must avoid matching of Imm32 templates when 64bit
4286 only immediate is available. */
4287 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4288 i.types[op].bitfield.imm32 = 0;
29b0f896 4289 break;
252b5132 4290
29b0f896
AM		 4291 case O_absent:
4292 case O_register:
4293 abort ();
4294
4295 /* Symbols and expressions. */
4296 default:
9cd96992
JB		 4297 /* Convert symbolic operand to proper sizes for matching, but don't
4298 prevent matching a set of insns that only supports sizes other
4299 than those matching the insn suffix. */
4300 {
40fb9820 4301 i386_operand_type mask, allowed;
d3ce72d0 4302 const insn_template *t;
9cd96992 4303
0dfbf9d7
L		 4304 operand_type_set (&mask, 0);
4305 operand_type_set (&allowed, 0);
40fb9820 4306
4eed87de
AM		 4307 for (t = current_templates->start;
4308 t < current_templates->end;
4309 ++t)
c6fb90c8
L		 4310 allowed = operand_type_or (allowed,
4311 t->operand_types[op]);
9cd96992
JB		 4312 switch (guess_suffix)
4313 {
4314 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4315 mask.bitfield.imm64 = 1;
4316 mask.bitfield.imm32s = 1;
9cd96992
JB		 4317 break;
4318 case LONG_MNEM_SUFFIX:
40fb9820 4319 mask.bitfield.imm32 = 1;
9cd96992
JB		 4320 break;
4321 case WORD_MNEM_SUFFIX:
40fb9820 4322 mask.bitfield.imm16 = 1;
9cd96992
JB		 4323 break;
4324 case BYTE_MNEM_SUFFIX:
40fb9820 4325 mask.bitfield.imm8 = 1;
9cd96992
JB		 4326 break;
4327 default:
9cd96992
JB		 4328 break;
4329 }
c6fb90c8 4330 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4331 if (!operand_type_all_zero (&allowed))
c6fb90c8 4332 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4333 }
29b0f896 4334 break;
252b5132 4335 }
29b0f896
AM		 4336 }
4337}
47926f60 4338
29b0f896
AM		 4339/* Try to use the smallest displacement type too. */
4340static void
e3bb37b5 4341optimize_disp (void)
29b0f896
AM		 4342{
4343 int op;
3e73aa7c 4344
29b0f896 4345 for (op = i.operands; --op >= 0;)
40fb9820 4346 if (operand_type_check (i.types[op], disp))
252b5132 4347 {
b300c311 4348 if (i.op[op].disps->X_op == O_constant)
252b5132 4349 {
91d6fa6a 4350 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4351
40fb9820 4352 if (i.types[op].bitfield.disp16
91d6fa6a 4353 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4354 {
4355 /* If this operand is at most 16 bits, convert
4356 to a signed 16 bit number and don't use 64bit
4357 displacement. */
91d6fa6a 4358 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4359 i.types[op].bitfield.disp64 = 0;
b300c311 4360 }
a28def75
L		 4361#ifdef BFD64
4362 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4363 if (i.types[op].bitfield.disp32
91d6fa6a 4364 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4365 {
4366 /* If this operand is at most 32 bits, convert
4367 to a signed 32 bit number and don't use 64bit
4368 displacement. */
91d6fa6a
NC		 4369 op_disp &= (((offsetT) 2 << 31) - 1);
4370 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4371 i.types[op].bitfield.disp64 = 0;
b300c311 4372 }
a28def75 4373#endif
91d6fa6a 4374 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4375 {
40fb9820
L		 4376 i.types[op].bitfield.disp8 = 0;
4377 i.types[op].bitfield.disp16 = 0;
4378 i.types[op].bitfield.disp32 = 0;
4379 i.types[op].bitfield.disp32s = 0;
4380 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4381 i.op[op].disps = 0;
4382 i.disp_operands--;
4383 }
4384 else if (flag_code == CODE_64BIT)
4385 {
91d6fa6a 4386 if (fits_in_signed_long (op_disp))
28a9d8f5 4387 {
40fb9820
L		 4388 i.types[op].bitfield.disp64 = 0;
4389 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4390 }
0e1147d9 4391 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4392 && fits_in_unsigned_long (op_disp))
40fb9820 4393 i.types[op].bitfield.disp32 = 1;
b300c311 4394 }
40fb9820
L		 4395 if ((i.types[op].bitfield.disp32
4396 || i.types[op].bitfield.disp32s
4397 || i.types[op].bitfield.disp16)
91d6fa6a 4398 && fits_in_signed_byte (op_disp))
40fb9820 4399 i.types[op].bitfield.disp8 = 1;
252b5132 4400 }
67a4f2b7
AO		 4401 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4402 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4403 {
4404 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4405 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4406 i.types[op].bitfield.disp8 = 0;
4407 i.types[op].bitfield.disp16 = 0;
4408 i.types[op].bitfield.disp32 = 0;
4409 i.types[op].bitfield.disp32s = 0;
4410 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4411 }
4412 else
b300c311 4413 /* We only support 64bit displacement on constants. */
40fb9820 4414 i.types[op].bitfield.disp64 = 0;
252b5132 4415 }
29b0f896
AM		 4416}
4417
6c30d220
L		 4418/* Check if operands are valid for the instruction. */
4419
4420static int
4421check_VecOperands (const insn_template *t)
4422{
43234a1e
L		 4423 unsigned int op;
4424
6c30d220
L		 4425 /* Without VSIB byte, we can't have a vector register for index. */
4426 if (!t->opcode_modifier.vecsib
4427 && i.index_reg
4428 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4429 || i.index_reg->reg_type.bitfield.regymm
4430 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4431 {
4432 i.error = unsupported_vector_index_register;
4433 return 1;
4434 }
4435
ad8ecc81
MZ		 4436 /* Check if default mask is allowed. */
4437 if (t->opcode_modifier.nodefmask
4438 && (!i.mask || i.mask->mask->reg_num == 0))
4439 {
4440 i.error = no_default_mask;
4441 return 1;
4442 }
4443
7bab8ab5
JB		 4444 /* For VSIB byte, we need a vector register for index, and all vector
4445 registers must be distinct. */
4446 if (t->opcode_modifier.vecsib)
4447 {
4448 if (!i.index_reg
6c30d220
L		 4449 || !((t->opcode_modifier.vecsib == VecSIB128
4450 && i.index_reg->reg_type.bitfield.regxmm)
4451 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4452 && i.index_reg->reg_type.bitfield.regymm)
4453 || (t->opcode_modifier.vecsib == VecSIB512
4454 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4455 {
4456 i.error = invalid_vsib_address;
4457 return 1;
4458 }
4459
43234a1e
L		 4460 gas_assert (i.reg_operands == 2 || i.mask);
4461 if (i.reg_operands == 2 && !i.mask)
4462 {
4463 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4464 || i.types[0].bitfield.regymm);
43234a1e 4465 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4466 || i.types[2].bitfield.regymm);
43234a1e
L		 4467 if (operand_check == check_none)
4468 return 0;
4469 if (register_number (i.op[0].regs)
4470 != register_number (i.index_reg)
4471 && register_number (i.op[2].regs)
4472 != register_number (i.index_reg)
4473 && register_number (i.op[0].regs)
4474 != register_number (i.op[2].regs))
4475 return 0;
4476 if (operand_check == check_error)
4477 {
4478 i.error = invalid_vector_register_set;
4479 return 1;
4480 }
4481 as_warn (_("mask, index, and destination registers should be distinct"));
4482 }
8444f82a
MZ		 4483 else if (i.reg_operands == 1 && i.mask)
4484 {
4485 if ((i.types[1].bitfield.regymm
4486 || i.types[1].bitfield.regzmm)
4487 && (register_number (i.op[1].regs)
4488 == register_number (i.index_reg)))
4489 {
4490 if (operand_check == check_error)
4491 {
4492 i.error = invalid_vector_register_set;
4493 return 1;
4494 }
4495 if (operand_check != check_none)
4496 as_warn (_("index and destination registers should be distinct"));
4497 }
4498 }
43234a1e 4499 }
7bab8ab5 4500
43234a1e
L		 4501 /* Check if broadcast is supported by the instruction and is applied
4502 to the memory operand. */
4503 if (i.broadcast)
4504 {
4505 int broadcasted_opnd_size;
4506
4507 /* Check if specified broadcast is supported in this instruction,
4508 and it's applied to memory operand of DWORD or QWORD type,
4509 depending on VecESize. */
4510 if (i.broadcast->type != t->opcode_modifier.broadcast
4511 || !i.types[i.broadcast->operand].bitfield.mem
4512 || (t->opcode_modifier.vecesize == 0
4513 && !i.types[i.broadcast->operand].bitfield.dword
4514 && !i.types[i.broadcast->operand].bitfield.unspecified)
4515 || (t->opcode_modifier.vecesize == 1
4516 && !i.types[i.broadcast->operand].bitfield.qword
4517 && !i.types[i.broadcast->operand].bitfield.unspecified))
4518 goto bad_broadcast;
4519
4520 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4521 if (i.broadcast->type == BROADCAST_1TO16)
4522 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4523 else if (i.broadcast->type == BROADCAST_1TO8)
4524 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4525 else if (i.broadcast->type == BROADCAST_1TO4)
4526 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4527 else if (i.broadcast->type == BROADCAST_1TO2)
4528 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4529 else
4530 goto bad_broadcast;
4531
4532 if ((broadcasted_opnd_size == 256
4533 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4534 || (broadcasted_opnd_size == 512
4535 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4536 {
4537 bad_broadcast:
4538 i.error = unsupported_broadcast;
4539 return 1;
4540 }
4541 }
4542 /* If broadcast is supported in this instruction, we need to check if
4543 operand of one-element size isn't specified without broadcast. */
4544 else if (t->opcode_modifier.broadcast && i.mem_operands)
4545 {
4546 /* Find memory operand. */
4547 for (op = 0; op < i.operands; op++)
4548 if (operand_type_check (i.types[op], anymem))
4549 break;
4550 gas_assert (op < i.operands);
4551 /* Check size of the memory operand. */
4552 if ((t->opcode_modifier.vecesize == 0
4553 && i.types[op].bitfield.dword)
4554 || (t->opcode_modifier.vecesize == 1
4555 && i.types[op].bitfield.qword))
4556 {
4557 i.error = broadcast_needed;
4558 return 1;
4559 }
4560 }
4561
4562 /* Check if requested masking is supported. */
4563 if (i.mask
4564 && (!t->opcode_modifier.masking
4565 || (i.mask->zeroing
4566 && t->opcode_modifier.masking == MERGING_MASKING)))
4567 {
4568 i.error = unsupported_masking;
4569 return 1;
4570 }
4571
4572 /* Check if masking is applied to dest operand. */
4573 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4574 {
4575 i.error = mask_not_on_destination;
4576 return 1;
4577 }
4578
43234a1e
L		 4579 /* Check RC/SAE. */
4580 if (i.rounding)
4581 {
4582 if ((i.rounding->type != saeonly
4583 && !t->opcode_modifier.staticrounding)
4584 || (i.rounding->type == saeonly
4585 && (t->opcode_modifier.staticrounding
4586 || !t->opcode_modifier.sae)))
4587 {
4588 i.error = unsupported_rc_sae;
4589 return 1;
4590 }
4591 /* If the instruction has several immediate operands and one of
4592 them is rounding, the rounding operand should be the last
4593 immediate operand. */
4594 if (i.imm_operands > 1
4595 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4596 {
43234a1e 4597 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4598 return 1;
4599 }
6c30d220
L		 4600 }
4601
43234a1e
L		 4602 /* Check vector Disp8 operand. */
4603 if (t->opcode_modifier.disp8memshift)
4604 {
4605 if (i.broadcast)
4606 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4607 else
4608 i.memshift = t->opcode_modifier.disp8memshift;
4609
4610 for (op = 0; op < i.operands; op++)
4611 if (operand_type_check (i.types[op], disp)
4612 && i.op[op].disps->X_op == O_constant)
4613 {
4614 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4615 int vec_disp8_ok
4616 = (i.disp_encoding != disp_encoding_32bit
4617 && fits_in_vec_disp8 (value));
43234a1e
L		 4618 if (t->operand_types [op].bitfield.vec_disp8)
4619 {
4620 if (vec_disp8_ok)
4621 i.types[op].bitfield.vec_disp8 = 1;
4622 else
4623 {
4624 /* Vector insn can only have Vec_Disp8/Disp32 in
4625 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4626 mode. */
4627 i.types[op].bitfield.disp8 = 0;
4628 if (flag_code != CODE_16BIT)
4629 i.types[op].bitfield.disp16 = 0;
4630 }
4631 }
4632 else if (flag_code != CODE_16BIT)
4633 {
4634 /* One form of this instruction supports vector Disp8.
4635 Try vector Disp8 if we need to use Disp32. */
4636 if (vec_disp8_ok && !fits_in_signed_byte (value))
4637 {
4638 i.error = try_vector_disp8;
4639 return 1;
4640 }
4641 }
4642 }
4643 }
4644 else
4645 i.memshift = -1;
4646
6c30d220
L		 4647 return 0;
4648}
4649
43f3e2ee 4650/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4651 operand types. */
4652
4653static int
4654VEX_check_operands (const insn_template *t)
4655{
43234a1e
L		 4656 /* VREX is only valid with EVEX prefix. */
4657 if (i.need_vrex && !t->opcode_modifier.evex)
4658 {
4659 i.error = invalid_register_operand;
4660 return 1;
4661 }
4662
a683cc34
SP		 4663 if (!t->opcode_modifier.vex)
4664 return 0;
4665
4666 /* Only check VEX_Imm4, which must be the first operand. */
4667 if (t->operand_types[0].bitfield.vec_imm4)
4668 {
4669 if (i.op[0].imms->X_op != O_constant
4670 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4671 {
a65babc9 4672 i.error = bad_imm4;
891edac4
L		 4673 return 1;
4674 }
a683cc34
SP		 4675
4676 /* Turn off Imm8 so that update_imm won't complain. */
4677 i.types[0] = vec_imm4;
4678 }
4679
4680 return 0;
4681}
4682
d3ce72d0 4683static const insn_template *
e3bb37b5 4684match_template (void)
29b0f896
AM		 4685{
4686 /* Points to template once we've found it. */
d3ce72d0 4687 const insn_template *t;
40fb9820 4688 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4689 i386_operand_type overlap4;
29b0f896 4690 unsigned int found_reverse_match;
40fb9820
L		 4691 i386_opcode_modifier suffix_check;
4692 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4693 int addr_prefix_disp;
a5c311ca 4694 unsigned int j;
3629bb00 4695 unsigned int found_cpu_match;
45664ddb 4696 unsigned int check_register;
5614d22c 4697 enum i386_error specific_error = 0;
29b0f896 4698
c0f3af97
L		 4699#if MAX_OPERANDS != 5
4700# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4701#endif
4702
29b0f896 4703 found_reverse_match = 0;
539e75ad 4704 addr_prefix_disp = -1;
40fb9820
L		 4705
4706 memset (&suffix_check, 0, sizeof (suffix_check));
4707 if (i.suffix == BYTE_MNEM_SUFFIX)
4708 suffix_check.no_bsuf = 1;
4709 else if (i.suffix == WORD_MNEM_SUFFIX)
4710 suffix_check.no_wsuf = 1;
4711 else if (i.suffix == SHORT_MNEM_SUFFIX)
4712 suffix_check.no_ssuf = 1;
4713 else if (i.suffix == LONG_MNEM_SUFFIX)
4714 suffix_check.no_lsuf = 1;
4715 else if (i.suffix == QWORD_MNEM_SUFFIX)
4716 suffix_check.no_qsuf = 1;
4717 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4718 suffix_check.no_ldsuf = 1;
29b0f896 4719
01559ecc
L		 4720 /* Must have right number of operands. */
4721 i.error = number_of_operands_mismatch;
4722
45aa61fe 4723 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4724 {
539e75ad
L		 4725 addr_prefix_disp = -1;
4726
29b0f896
AM		 4727 if (i.operands != t->operands)
4728 continue;
4729
50aecf8c 4730 /* Check processor support. */
a65babc9 4731 i.error = unsupported;
c0f3af97
L		 4732 found_cpu_match = (cpu_flags_match (t)
4733 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4734 if (!found_cpu_match)
4735 continue;
4736
e1d4d893 4737 /* Check old gcc support. */
a65babc9 4738 i.error = old_gcc_only;
e1d4d893
L		 4739 if (!old_gcc && t->opcode_modifier.oldgcc)
4740 continue;
4741
4742 /* Check AT&T mnemonic. */
a65babc9 4743 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4744 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4745 continue;
4746
891edac4 4747 /* Check AT&T/Intel syntax. */
a65babc9 4748 i.error = unsupported_syntax;
5c07affc
L		 4749 if ((intel_syntax && t->opcode_modifier.attsyntax)
4750 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4751 continue;
4752
20592a94 4753 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4754 i.error = invalid_instruction_suffix;
567e4e96
L		 4755 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4756 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4757 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4758 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4759 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4760 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4761 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4762 continue;
4763
5c07affc 4764 if (!operand_size_match (t))
7d5e4556 4765 continue;
539e75ad 4766
5c07affc
L		 4767 for (j = 0; j < MAX_OPERANDS; j++)
4768 operand_types[j] = t->operand_types[j];
4769
45aa61fe
AM		 4770 /* In general, don't allow 64-bit operands in 32-bit mode. */
4771 if (i.suffix == QWORD_MNEM_SUFFIX
4772 && flag_code != CODE_64BIT
4773 && (intel_syntax
40fb9820 4774 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4775 && !intel_float_operand (t->name))
4776 : intel_float_operand (t->name) != 2)
40fb9820 4777 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4778 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4779 && !operand_types[0].bitfield.regymm
4780 && !operand_types[0].bitfield.regzmm)
40fb9820 4781 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4782 && operand_types[t->operands > 1].bitfield.regxmm
4783 && operand_types[t->operands > 1].bitfield.regymm
4784 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4785 && (t->base_opcode != 0x0fc7
4786 || t->extension_opcode != 1 /* cmpxchg8b */))
4787 continue;
4788
192dc9c6
JB		 4789 /* In general, don't allow 32-bit operands on pre-386. */
4790 else if (i.suffix == LONG_MNEM_SUFFIX
4791 && !cpu_arch_flags.bitfield.cpui386
4792 && (intel_syntax
4793 ? (!t->opcode_modifier.ignoresize
4794 && !intel_float_operand (t->name))
4795 : intel_float_operand (t->name) != 2)
4796 && ((!operand_types[0].bitfield.regmmx
4797 && !operand_types[0].bitfield.regxmm)
4798 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4799 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4800 continue;
4801
29b0f896 4802 /* Do not verify operands when there are none. */
50aecf8c 4803 else
29b0f896 4804 {
c6fb90c8 4805 if (!t->operands)
2dbab7d5
L		 4806 /* We've found a match; break out of loop. */
4807 break;
29b0f896 4808 }
252b5132 4809
539e75ad
L		 4810 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4811 into Disp32/Disp16/Disp32 operand. */
4812 if (i.prefix[ADDR_PREFIX] != 0)
4813 {
40fb9820 4814 /* There should be only one Disp operand. */
539e75ad
L		 4815 switch (flag_code)
4816 {
4817 case CODE_16BIT:
40fb9820
L		 4818 for (j = 0; j < MAX_OPERANDS; j++)
4819 {
4820 if (operand_types[j].bitfield.disp16)
4821 {
4822 addr_prefix_disp = j;
4823 operand_types[j].bitfield.disp32 = 1;
4824 operand_types[j].bitfield.disp16 = 0;
4825 break;
4826 }
4827 }
539e75ad
L		 4828 break;
4829 case CODE_32BIT:
40fb9820
L		 4830 for (j = 0; j < MAX_OPERANDS; j++)
4831 {
4832 if (operand_types[j].bitfield.disp32)
4833 {
4834 addr_prefix_disp = j;
4835 operand_types[j].bitfield.disp32 = 0;
4836 operand_types[j].bitfield.disp16 = 1;
4837 break;
4838 }
4839 }
539e75ad
L		 4840 break;
4841 case CODE_64BIT:
40fb9820
L		 4842 for (j = 0; j < MAX_OPERANDS; j++)
4843 {
4844 if (operand_types[j].bitfield.disp64)
4845 {
4846 addr_prefix_disp = j;
4847 operand_types[j].bitfield.disp64 = 0;
4848 operand_types[j].bitfield.disp32 = 1;
4849 break;
4850 }
4851 }
539e75ad
L		 4852 break;
4853 }
539e75ad
L		 4854 }
4855
02a86693
L		 4856 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4857 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4858 continue;
4859
56ffb741
L		 4860 /* We check register size if needed. */
4861 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4862 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4863 switch (t->operands)
4864 {
4865 case 1:
40fb9820 4866 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4867 continue;
4868 break;
4869 case 2:
8b38ad71
L		 4870 /* xchg %eax, %eax is a special case. It is an aliase for nop
4871 only in 32bit mode and we can use opcode 0x90. In 64bit
4872 mode, we can't use 0x90 for xchg %eax, %eax since it should
4873 zero-extend %eax to %rax. */
4874 if (flag_code == CODE_64BIT
4875 && t->base_opcode == 0x90
0dfbf9d7
L		 4876 && operand_type_equal (&i.types [0], &acc32)
4877 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4878 continue;
b6169b20
L		 4879 if (i.swap_operand)
4880 {
4881 /* If we swap operand in encoding, we either match
4882 the next one or reverse direction of operands. */
4883 if (t->opcode_modifier.s)
4884 continue;
4885 else if (t->opcode_modifier.d)
4886 goto check_reverse;
4887 }
4888
29b0f896 4889 case 3:
fa99fab2
L		 4890 /* If we swap operand in encoding, we match the next one. */
4891 if (i.swap_operand && t->opcode_modifier.s)
4892 continue;
f48ff2ae 4893 case 4:
c0f3af97 4894 case 5:
c6fb90c8 4895 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4896 if (!operand_type_match (overlap0, i.types[0])
4897 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4898 || (check_register
4899 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4900 operand_types[0],
4901 overlap1, i.types[1],
4902 operand_types[1])))
29b0f896
AM		 4903 {
4904 /* Check if other direction is valid ... */
40fb9820 4905 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4906 continue;
4907
b6169b20 4908check_reverse:
29b0f896 4909 /* Try reversing direction of operands. */
c6fb90c8
L		 4910 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4911 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4912 if (!operand_type_match (overlap0, i.types[0])
4913 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4914 || (check_register
4915 && !operand_type_register_match (overlap0,
4916 i.types[0],
4917 operand_types[1],
4918 overlap1,
4919 i.types[1],
4920 operand_types[0])))
29b0f896
AM		 4921 {
4922 /* Does not match either direction. */
4923 continue;
4924 }
4925 /* found_reverse_match holds which of D or FloatDR
4926 we've found. */
40fb9820 4927 if (t->opcode_modifier.d)
8a2ed489 4928 found_reverse_match = Opcode_D;
40fb9820 4929 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4930 found_reverse_match = Opcode_FloatD;
4931 else
4932 found_reverse_match = 0;
40fb9820 4933 if (t->opcode_modifier.floatr)
8a2ed489 4934 found_reverse_match |= Opcode_FloatR;
29b0f896 4935 }
f48ff2ae 4936 else
29b0f896 4937 {
f48ff2ae 4938 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4939 switch (t->operands)
4940 {
c0f3af97
L		 4941 case 5:
4942 overlap4 = operand_type_and (i.types[4],
4943 operand_types[4]);
d1cbb4db 4944 case 4:
c6fb90c8
L		 4945 overlap3 = operand_type_and (i.types[3],
4946 operand_types[3]);
d1cbb4db 4947 case 3:
c6fb90c8
L		 4948 overlap2 = operand_type_and (i.types[2],
4949 operand_types[2]);
d1cbb4db
L		 4950 break;
4951 }
29b0f896 4952
f48ff2ae
L		 4953 switch (t->operands)
4954 {
c0f3af97
L		 4955 case 5:
4956 if (!operand_type_match (overlap4, i.types[4])
4957 || !operand_type_register_match (overlap3,
4958 i.types[3],
4959 operand_types[3],
4960 overlap4,
4961 i.types[4],
4962 operand_types[4]))
4963 continue;
f48ff2ae 4964 case 4:
40fb9820 4965 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4966 || (check_register
4967 && !operand_type_register_match (overlap2,
4968 i.types[2],
4969 operand_types[2],
4970 overlap3,
4971 i.types[3],
4972 operand_types[3])))
f48ff2ae
L		 4973 continue;
4974 case 3:
4975 /* Here we make use of the fact that there are no
4976 reverse match 3 operand instructions, and all 3
4977 operand instructions only need to be checked for
4978 register consistency between operands 2 and 3. */
40fb9820 4979 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4980 || (check_register
4981 && !operand_type_register_match (overlap1,
4982 i.types[1],
4983 operand_types[1],
4984 overlap2,
4985 i.types[2],
4986 operand_types[2])))
f48ff2ae
L		 4987 continue;
4988 break;
4989 }
29b0f896 4990 }
f48ff2ae 4991 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4992 slip through to break. */
4993 }
3629bb00 4994 if (!found_cpu_match)
29b0f896
AM		 4995 {
4996 found_reverse_match = 0;
4997 continue;
4998 }
c0f3af97 4999
5614d22c
JB		 5000 /* Check if vector and VEX operands are valid. */
5001 if (check_VecOperands (t) || VEX_check_operands (t))
5002 {
5003 specific_error = i.error;
5004 continue;
5005 }
a683cc34 5006
29b0f896
AM		 5007 /* We've found a match; break out of loop. */
5008 break;
5009 }
5010
5011 if (t == current_templates->end)
5012 {
5013 /* We found no match. */
a65babc9 5014 const char *err_msg;
5614d22c 5015 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5016 {
5017 default:
5018 abort ();
86e026a4 5019 case operand_size_mismatch:
a65babc9
L		 5020 err_msg = _("operand size mismatch");
5021 break;
5022 case operand_type_mismatch:
5023 err_msg = _("operand type mismatch");
5024 break;
5025 case register_type_mismatch:
5026 err_msg = _("register type mismatch");
5027 break;
5028 case number_of_operands_mismatch:
5029 err_msg = _("number of operands mismatch");
5030 break;
5031 case invalid_instruction_suffix:
5032 err_msg = _("invalid instruction suffix");
5033 break;
5034 case bad_imm4:
4a2608e3 5035 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5036 break;
5037 case old_gcc_only:
5038 err_msg = _("only supported with old gcc");
5039 break;
5040 case unsupported_with_intel_mnemonic:
5041 err_msg = _("unsupported with Intel mnemonic");
5042 break;
5043 case unsupported_syntax:
5044 err_msg = _("unsupported syntax");
5045 break;
5046 case unsupported:
35262a23 5047 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5048 current_templates->start->name);
5049 return NULL;
6c30d220
L		 5050 case invalid_vsib_address:
5051 err_msg = _("invalid VSIB address");
5052 break;
7bab8ab5
JB		 5053 case invalid_vector_register_set:
5054 err_msg = _("mask, index, and destination registers must be distinct");
5055 break;
6c30d220
L		 5056 case unsupported_vector_index_register:
5057 err_msg = _("unsupported vector index register");
5058 break;
43234a1e
L		 5059 case unsupported_broadcast:
5060 err_msg = _("unsupported broadcast");
5061 break;
5062 case broadcast_not_on_src_operand:
5063 err_msg = _("broadcast not on source memory operand");
5064 break;
5065 case broadcast_needed:
5066 err_msg = _("broadcast is needed for operand of such type");
5067 break;
5068 case unsupported_masking:
5069 err_msg = _("unsupported masking");
5070 break;
5071 case mask_not_on_destination:
5072 err_msg = _("mask not on destination operand");
5073 break;
5074 case no_default_mask:
5075 err_msg = _("default mask isn't allowed");
5076 break;
5077 case unsupported_rc_sae:
5078 err_msg = _("unsupported static rounding/sae");
5079 break;
5080 case rc_sae_operand_not_last_imm:
5081 if (intel_syntax)
5082 err_msg = _("RC/SAE operand must precede immediate operands");
5083 else
5084 err_msg = _("RC/SAE operand must follow immediate operands");
5085 break;
5086 case invalid_register_operand:
5087 err_msg = _("invalid register operand");
5088 break;
a65babc9
L		 5089 }
5090 as_bad (_("%s for `%s'"), err_msg,
891edac4 5091 current_templates->start->name);
fa99fab2 5092 return NULL;
29b0f896 5093 }
252b5132 5094
29b0f896
AM		 5095 if (!quiet_warnings)
5096 {
5097 if (!intel_syntax
40fb9820
L		 5098 && (i.types[0].bitfield.jumpabsolute
5099 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5100 {
5101 as_warn (_("indirect %s without `*'"), t->name);
5102 }
5103
40fb9820
L		 5104 if (t->opcode_modifier.isprefix
5105 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5106 {
5107 /* Warn them that a data or address size prefix doesn't
5108 affect assembly of the next line of code. */
5109 as_warn (_("stand-alone `%s' prefix"), t->name);
5110 }
5111 }
5112
5113 /* Copy the template we found. */
5114 i.tm = *t;
539e75ad
L		 5115
5116 if (addr_prefix_disp != -1)
5117 i.tm.operand_types[addr_prefix_disp]
5118 = operand_types[addr_prefix_disp];
5119
29b0f896
AM		 5120 if (found_reverse_match)
5121 {
5122 /* If we found a reverse match we must alter the opcode
5123 direction bit. found_reverse_match holds bits to change
5124 (different for int & float insns). */
5125
5126 i.tm.base_opcode ^= found_reverse_match;
5127
539e75ad
L		 5128 i.tm.operand_types[0] = operand_types[1];
5129 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5130 }
5131
fa99fab2 5132 return t;
29b0f896
AM		 5133}
5134
5135static int
e3bb37b5 5136check_string (void)
29b0f896 5137{
40fb9820
L		 5138 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5139 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5140 {
5141 if (i.seg[0] != NULL && i.seg[0] != &es)
5142 {
a87af027 5143 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5144 i.tm.name,
a87af027
JB		 5145 mem_op + 1,
5146 register_prefix);
29b0f896
AM		 5147 return 0;
5148 }
5149 /* There's only ever one segment override allowed per instruction.
5150 This instruction possibly has a legal segment override on the
5151 second operand, so copy the segment to where non-string
5152 instructions store it, allowing common code. */
5153 i.seg[0] = i.seg[1];
5154 }
40fb9820 5155 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5156 {
5157 if (i.seg[1] != NULL && i.seg[1] != &es)
5158 {
a87af027 5159 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5160 i.tm.name,
a87af027
JB		 5161 mem_op + 2,
5162 register_prefix);
29b0f896
AM		 5163 return 0;
5164 }
5165 }
5166 return 1;
5167}
5168
5169static int
543613e9 5170process_suffix (void)
29b0f896
AM		 5171{
5172 /* If matched instruction specifies an explicit instruction mnemonic
5173 suffix, use it. */
40fb9820
L		 5174 if (i.tm.opcode_modifier.size16)
5175 i.suffix = WORD_MNEM_SUFFIX;
5176 else if (i.tm.opcode_modifier.size32)
5177 i.suffix = LONG_MNEM_SUFFIX;
5178 else if (i.tm.opcode_modifier.size64)
5179 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5180 else if (i.reg_operands)
5181 {
5182 /* If there's no instruction mnemonic suffix we try to invent one
5183 based on register operands. */
5184 if (!i.suffix)
5185 {
5186 /* We take i.suffix from the last register operand specified,
5187 Destination register type is more significant than source
381d071f
L		 5188 register type. crc32 in SSE4.2 prefers source register
5189 type. */
5190 if (i.tm.base_opcode == 0xf20f38f1)
5191 {
40fb9820
L		 5192 if (i.types[0].bitfield.reg16)
5193 i.suffix = WORD_MNEM_SUFFIX;
5194 else if (i.types[0].bitfield.reg32)
5195 i.suffix = LONG_MNEM_SUFFIX;
5196 else if (i.types[0].bitfield.reg64)
5197 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5198 }
9344ff29 5199 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5200 {
40fb9820 5201 if (i.types[0].bitfield.reg8)
20592a94
L		 5202 i.suffix = BYTE_MNEM_SUFFIX;
5203 }
381d071f
L		 5204
5205 if (!i.suffix)
5206 {
5207 int op;
5208
20592a94
L		 5209 if (i.tm.base_opcode == 0xf20f38f1
5210 || i.tm.base_opcode == 0xf20f38f0)
5211 {
5212 /* We have to know the operand size for crc32. */
5213 as_bad (_("ambiguous memory operand size for `%s`"),
5214 i.tm.name);
5215 return 0;
5216 }
5217
381d071f 5218 for (op = i.operands; --op >= 0;)
40fb9820 5219 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5220 {
40fb9820
L		 5221 if (i.types[op].bitfield.reg8)
5222 {
5223 i.suffix = BYTE_MNEM_SUFFIX;
5224 break;
5225 }
5226 else if (i.types[op].bitfield.reg16)
5227 {
5228 i.suffix = WORD_MNEM_SUFFIX;
5229 break;
5230 }
5231 else if (i.types[op].bitfield.reg32)
5232 {
5233 i.suffix = LONG_MNEM_SUFFIX;
5234 break;
5235 }
5236 else if (i.types[op].bitfield.reg64)
5237 {
5238 i.suffix = QWORD_MNEM_SUFFIX;
5239 break;
5240 }
381d071f
L		 5241 }
5242 }
29b0f896
AM		 5243 }
5244 else if (i.suffix == BYTE_MNEM_SUFFIX)
5245 {
2eb952a4
L		 5246 if (intel_syntax
5247 && i.tm.opcode_modifier.ignoresize
5248 && i.tm.opcode_modifier.no_bsuf)
5249 i.suffix = 0;
5250 else if (!check_byte_reg ())
29b0f896
AM		 5251 return 0;
5252 }
5253 else if (i.suffix == LONG_MNEM_SUFFIX)
5254 {
2eb952a4
L		 5255 if (intel_syntax
5256 && i.tm.opcode_modifier.ignoresize
5257 && i.tm.opcode_modifier.no_lsuf)
5258 i.suffix = 0;
5259 else if (!check_long_reg ())
29b0f896
AM		 5260 return 0;
5261 }
5262 else if (i.suffix == QWORD_MNEM_SUFFIX)
5263 {
955e1e6a
L		 5264 if (intel_syntax
5265 && i.tm.opcode_modifier.ignoresize
5266 && i.tm.opcode_modifier.no_qsuf)
5267 i.suffix = 0;
5268 else if (!check_qword_reg ())
29b0f896
AM		 5269 return 0;
5270 }
5271 else if (i.suffix == WORD_MNEM_SUFFIX)
5272 {
2eb952a4
L		 5273 if (intel_syntax
5274 && i.tm.opcode_modifier.ignoresize
5275 && i.tm.opcode_modifier.no_wsuf)
5276 i.suffix = 0;
5277 else if (!check_word_reg ())
29b0f896
AM		 5278 return 0;
5279 }
c0f3af97 5280 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5281 || i.suffix == YMMWORD_MNEM_SUFFIX
5282 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5283 {
43234a1e 5284 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5285 should check if it is a valid suffix. */
5286 }
40fb9820 5287 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5288 /* Do nothing if the instruction is going to ignore the prefix. */
5289 ;
5290 else
5291 abort ();
5292 }
40fb9820 5293 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5294 && !i.suffix
5295 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5296 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5297 {
5298 i.suffix = stackop_size;
5299 }
9306ca4a
JB		 5300 else if (intel_syntax
5301 && !i.suffix
40fb9820
L		 5302 && (i.tm.operand_types[0].bitfield.jumpabsolute
5303 || i.tm.opcode_modifier.jumpbyte
5304 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5305 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5306 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5307 {
5308 switch (flag_code)
5309 {
5310 case CODE_64BIT:
40fb9820 5311 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5312 {
5313 i.suffix = QWORD_MNEM_SUFFIX;
5314 break;
5315 }
5316 case CODE_32BIT:
40fb9820 5317 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5318 i.suffix = LONG_MNEM_SUFFIX;
5319 break;
5320 case CODE_16BIT:
40fb9820 5321 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5322 i.suffix = WORD_MNEM_SUFFIX;
5323 break;
5324 }
5325 }
252b5132 5326
9306ca4a 5327 if (!i.suffix)
29b0f896 5328 {
9306ca4a
JB		 5329 if (!intel_syntax)
5330 {
40fb9820 5331 if (i.tm.opcode_modifier.w)
9306ca4a 5332 {
4eed87de
AM		 5333 as_bad (_("no instruction mnemonic suffix given and "
5334 "no register operands; can't size instruction"));
9306ca4a
JB		 5335 return 0;
5336 }
5337 }
5338 else
5339 {
40fb9820 5340 unsigned int suffixes;
7ab9ffdd 5341
40fb9820
L		 5342 suffixes = !i.tm.opcode_modifier.no_bsuf;
5343 if (!i.tm.opcode_modifier.no_wsuf)
5344 suffixes |= 1 << 1;
5345 if (!i.tm.opcode_modifier.no_lsuf)
5346 suffixes |= 1 << 2;
fc4adea1 5347 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5348 suffixes |= 1 << 3;
5349 if (!i.tm.opcode_modifier.no_ssuf)
5350 suffixes |= 1 << 4;
5351 if (!i.tm.opcode_modifier.no_qsuf)
5352 suffixes |= 1 << 5;
5353
5354 /* There are more than suffix matches. */
5355 if (i.tm.opcode_modifier.w
9306ca4a 5356 || ((suffixes & (suffixes - 1))
40fb9820
L		 5357 && !i.tm.opcode_modifier.defaultsize
5358 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5359 {
5360 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5361 return 0;
5362 }
5363 }
29b0f896 5364 }
252b5132 5365
9306ca4a
JB		 5366 /* Change the opcode based on the operand size given by i.suffix;
5367 We don't need to change things for byte insns. */
5368
582d5edd
L		 5369 if (i.suffix
5370 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5371 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5372 && i.suffix != YMMWORD_MNEM_SUFFIX
5373 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5374 {
5375 /* It's not a byte, select word/dword operation. */
40fb9820 5376 if (i.tm.opcode_modifier.w)
29b0f896 5377 {
40fb9820 5378 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5379 i.tm.base_opcode |= 8;
5380 else
5381 i.tm.base_opcode |= 1;
5382 }
0f3f3d8b 5383
29b0f896
AM		 5384 /* Now select between word & dword operations via the operand
5385 size prefix, except for instructions that will ignore this
5386 prefix anyway. */
ca61edf2 5387 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5388 {
ca61edf2
L		 5389 /* The address size override prefix changes the size of the
5390 first operand. */
40fb9820
L		 5391 if ((flag_code == CODE_32BIT
5392 && i.op->regs[0].reg_type.bitfield.reg16)
5393 || (flag_code != CODE_32BIT
5394 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5395 if (!add_prefix (ADDR_PREFIX_OPCODE))
5396 return 0;
5397 }
5398 else if (i.suffix != QWORD_MNEM_SUFFIX
5399 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5400 && !i.tm.opcode_modifier.ignoresize
5401 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5402 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5403 || (flag_code == CODE_64BIT
40fb9820 5404 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5405 {
5406 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5407
40fb9820 5408 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5409 prefix = ADDR_PREFIX_OPCODE;
252b5132 5410
29b0f896
AM		 5411 if (!add_prefix (prefix))
5412 return 0;
24eab124 5413 }
252b5132 5414
29b0f896
AM		 5415 /* Set mode64 for an operand. */
5416 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5417 && flag_code == CODE_64BIT
40fb9820 5418 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5419 {
5420 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5421 need rex64. cmpxchg8b is also a special case. */
5422 if (! (i.operands == 2
5423 && i.tm.base_opcode == 0x90
5424 && i.tm.extension_opcode == None
0dfbf9d7
L		 5425 && operand_type_equal (&i.types [0], &acc64)
5426 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5427 && ! (i.operands == 1
5428 && i.tm.base_opcode == 0xfc7
5429 && i.tm.extension_opcode == 1
40fb9820
L		 5430 && !operand_type_check (i.types [0], reg)
5431 && operand_type_check (i.types [0], anymem)))
f6bee062 5432 i.rex |= REX_W;
46e883c5 5433 }
3e73aa7c 5434
29b0f896
AM		 5435 /* Size floating point instruction. */
5436 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5437 if (i.tm.opcode_modifier.floatmf)
543613e9 5438 i.tm.base_opcode ^= 4;
29b0f896 5439 }
7ecd2f8b 5440
29b0f896
AM		 5441 return 1;
5442}
3e73aa7c 5443
29b0f896 5444static int
543613e9 5445check_byte_reg (void)
29b0f896
AM		 5446{
5447 int op;
543613e9 5448
29b0f896
AM		 5449 for (op = i.operands; --op >= 0;)
5450 {
5451 /* If this is an eight bit register, it's OK. If it's the 16 or
5452 32 bit version of an eight bit register, we will just use the
5453 low portion, and that's OK too. */
40fb9820 5454 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5455 continue;
5456
5a819eb9
JB		 5457 /* I/O port address operands are OK too. */
5458 if (i.tm.operand_types[op].bitfield.inoutportreg)
5459 continue;
5460
9344ff29
L		 5461 /* crc32 doesn't generate this warning. */
5462 if (i.tm.base_opcode == 0xf20f38f0)
5463 continue;
5464
40fb9820
L		 5465 if ((i.types[op].bitfield.reg16
5466 || i.types[op].bitfield.reg32
5467 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5468 && i.op[op].regs->reg_num < 4
5469 /* Prohibit these changes in 64bit mode, since the lowering
5470 would be more complicated. */
5471 && flag_code != CODE_64BIT)
29b0f896 5472 {
29b0f896 5473#if REGISTER_WARNINGS
5a819eb9 5474 if (!quiet_warnings)
a540244d
L		 5475 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5476 register_prefix,
40fb9820 5477 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5478 ? REGNAM_AL - REGNAM_AX
5479 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5480 register_prefix,
29b0f896
AM		 5481 i.op[op].regs->reg_name,
5482 i.suffix);
5483#endif
5484 continue;
5485 }
5486 /* Any other register is bad. */
40fb9820
L		 5487 if (i.types[op].bitfield.reg16
5488 || i.types[op].bitfield.reg32
5489 || i.types[op].bitfield.reg64
5490 || i.types[op].bitfield.regmmx
5491 || i.types[op].bitfield.regxmm
c0f3af97 5492 || i.types[op].bitfield.regymm
43234a1e 5493 || i.types[op].bitfield.regzmm
40fb9820
L		 5494 || i.types[op].bitfield.sreg2
5495 || i.types[op].bitfield.sreg3
5496 || i.types[op].bitfield.control
5497 || i.types[op].bitfield.debug
5498 || i.types[op].bitfield.test
5499 || i.types[op].bitfield.floatreg
5500 || i.types[op].bitfield.floatacc)
29b0f896 5501 {
a540244d
L		 5502 as_bad (_("`%s%s' not allowed with `%s%c'"),
5503 register_prefix,
29b0f896
AM		 5504 i.op[op].regs->reg_name,
5505 i.tm.name,
5506 i.suffix);
5507 return 0;
5508 }
5509 }
5510 return 1;
5511}
5512
5513static int
e3bb37b5 5514check_long_reg (void)
29b0f896
AM		 5515{
5516 int op;
5517
5518 for (op = i.operands; --op >= 0;)
5519 /* Reject eight bit registers, except where the template requires
5520 them. (eg. movzb) */
40fb9820
L		 5521 if (i.types[op].bitfield.reg8
5522 && (i.tm.operand_types[op].bitfield.reg16
5523 || i.tm.operand_types[op].bitfield.reg32
5524 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5525 {
a540244d
L		 5526 as_bad (_("`%s%s' not allowed with `%s%c'"),
5527 register_prefix,
29b0f896
AM		 5528 i.op[op].regs->reg_name,
5529 i.tm.name,
5530 i.suffix);
5531 return 0;
5532 }
e4630f71 5533 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5534 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5535 && i.types[op].bitfield.reg16
5536 && (i.tm.operand_types[op].bitfield.reg32
5537 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5538 {
5539 /* Prohibit these changes in the 64bit mode, since the
5540 lowering is more complicated. */
5541 if (flag_code == CODE_64BIT)
252b5132 5542 {
2b5d6a91 5543 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5544 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5545 i.suffix);
5546 return 0;
252b5132 5547 }
29b0f896 5548#if REGISTER_WARNINGS
cecf1424
JB		 5549 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5550 register_prefix,
5551 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5552 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5553#endif
252b5132 5554 }
e4630f71 5555 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5556 else if (i.types[op].bitfield.reg64
5557 && (i.tm.operand_types[op].bitfield.reg32
5558 || i.tm.operand_types[op].bitfield.acc))
252b5132 5559 {
34828aad 5560 if (intel_syntax
ca61edf2 5561 && i.tm.opcode_modifier.toqword
40fb9820 5562 && !i.types[0].bitfield.regxmm)
34828aad 5563 {
ca61edf2 5564 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5565 i.suffix = QWORD_MNEM_SUFFIX;
5566 }
5567 else
5568 {
2b5d6a91 5569 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5570 register_prefix, i.op[op].regs->reg_name,
5571 i.suffix);
5572 return 0;
5573 }
29b0f896
AM		 5574 }
5575 return 1;
5576}
252b5132 5577
29b0f896 5578static int
e3bb37b5 5579check_qword_reg (void)
29b0f896
AM		 5580{
5581 int op;
252b5132 5582
29b0f896
AM		 5583 for (op = i.operands; --op >= 0; )
5584 /* Reject eight bit registers, except where the template requires
5585 them. (eg. movzb) */
40fb9820
L		 5586 if (i.types[op].bitfield.reg8
5587 && (i.tm.operand_types[op].bitfield.reg16
5588 || i.tm.operand_types[op].bitfield.reg32
5589 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5590 {
a540244d
L		 5591 as_bad (_("`%s%s' not allowed with `%s%c'"),
5592 register_prefix,
29b0f896
AM		 5593 i.op[op].regs->reg_name,
5594 i.tm.name,
5595 i.suffix);
5596 return 0;
5597 }
e4630f71 5598 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5599 else if ((i.types[op].bitfield.reg16
5600 || i.types[op].bitfield.reg32)
5601 && (i.tm.operand_types[op].bitfield.reg32
5602 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5603 {
5604 /* Prohibit these changes in the 64bit mode, since the
5605 lowering is more complicated. */
34828aad 5606 if (intel_syntax
ca61edf2 5607 && i.tm.opcode_modifier.todword
40fb9820 5608 && !i.types[0].bitfield.regxmm)
34828aad 5609 {
ca61edf2 5610 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5611 i.suffix = LONG_MNEM_SUFFIX;
5612 }
5613 else
5614 {
2b5d6a91 5615 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5616 register_prefix, i.op[op].regs->reg_name,
5617 i.suffix);
5618 return 0;
5619 }
252b5132 5620 }
29b0f896
AM		 5621 return 1;
5622}
252b5132 5623
29b0f896 5624static int
e3bb37b5 5625check_word_reg (void)
29b0f896
AM		 5626{
5627 int op;
5628 for (op = i.operands; --op >= 0;)
5629 /* Reject eight bit registers, except where the template requires
5630 them. (eg. movzb) */
40fb9820
L		 5631 if (i.types[op].bitfield.reg8
5632 && (i.tm.operand_types[op].bitfield.reg16
5633 || i.tm.operand_types[op].bitfield.reg32
5634 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5635 {
a540244d
L		 5636 as_bad (_("`%s%s' not allowed with `%s%c'"),
5637 register_prefix,
29b0f896
AM		 5638 i.op[op].regs->reg_name,
5639 i.tm.name,
5640 i.suffix);
5641 return 0;
5642 }
e4630f71 5643 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5644 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5645 && (i.types[op].bitfield.reg32
5646 || i.types[op].bitfield.reg64)
40fb9820
L		 5647 && (i.tm.operand_types[op].bitfield.reg16
5648 || i.tm.operand_types[op].bitfield.acc))
252b5132 5649 {
29b0f896
AM		 5650 /* Prohibit these changes in the 64bit mode, since the
5651 lowering is more complicated. */
5652 if (flag_code == CODE_64BIT)
252b5132 5653 {
2b5d6a91 5654 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5655 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5656 i.suffix);
5657 return 0;
252b5132 5658 }
29b0f896 5659#if REGISTER_WARNINGS
cecf1424
JB		 5660 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5661 register_prefix,
5662 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5663 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5664#endif
5665 }
5666 return 1;
5667}
252b5132 5668
29b0f896 5669static int
40fb9820 5670update_imm (unsigned int j)
29b0f896 5671{
bc0844ae 5672 i386_operand_type overlap = i.types[j];
40fb9820
L		 5673 if ((overlap.bitfield.imm8
5674 || overlap.bitfield.imm8s
5675 || overlap.bitfield.imm16
5676 || overlap.bitfield.imm32
5677 || overlap.bitfield.imm32s
5678 || overlap.bitfield.imm64)
0dfbf9d7
L		 5679 && !operand_type_equal (&overlap, &imm8)
5680 && !operand_type_equal (&overlap, &imm8s)
5681 && !operand_type_equal (&overlap, &imm16)
5682 && !operand_type_equal (&overlap, &imm32)
5683 && !operand_type_equal (&overlap, &imm32s)
5684 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5685 {
5686 if (i.suffix)
5687 {
40fb9820
L		 5688 i386_operand_type temp;
5689
0dfbf9d7 5690 operand_type_set (&temp, 0);
7ab9ffdd 5691 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5692 {
5693 temp.bitfield.imm8 = overlap.bitfield.imm8;
5694 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5695 }
5696 else if (i.suffix == WORD_MNEM_SUFFIX)
5697 temp.bitfield.imm16 = overlap.bitfield.imm16;
5698 else if (i.suffix == QWORD_MNEM_SUFFIX)
5699 {
5700 temp.bitfield.imm64 = overlap.bitfield.imm64;
5701 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5702 }
5703 else
5704 temp.bitfield.imm32 = overlap.bitfield.imm32;
5705 overlap = temp;
29b0f896 5706 }
0dfbf9d7
L		 5707 else if (operand_type_equal (&overlap, &imm16_32_32s)
5708 || operand_type_equal (&overlap, &imm16_32)
5709 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5710 {
40fb9820 5711 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5712 overlap = imm16;
40fb9820 5713 else
65da13b5 5714 overlap = imm32s;
29b0f896 5715 }
0dfbf9d7
L		 5716 if (!operand_type_equal (&overlap, &imm8)
5717 && !operand_type_equal (&overlap, &imm8s)
5718 && !operand_type_equal (&overlap, &imm16)
5719 && !operand_type_equal (&overlap, &imm32)
5720 && !operand_type_equal (&overlap, &imm32s)
5721 && !operand_type_equal (&overlap, &imm64))
29b0f896 5722 {
4eed87de
AM		 5723 as_bad (_("no instruction mnemonic suffix given; "
5724 "can't determine immediate size"));
29b0f896
AM		 5725 return 0;
5726 }
5727 }
40fb9820 5728 i.types[j] = overlap;
29b0f896 5729
40fb9820
L		 5730 return 1;
5731}
5732
5733static int
5734finalize_imm (void)
5735{
bc0844ae 5736 unsigned int j, n;
29b0f896 5737
bc0844ae
L		 5738 /* Update the first 2 immediate operands. */
5739 n = i.operands > 2 ? 2 : i.operands;
5740 if (n)
5741 {
5742 for (j = 0; j < n; j++)
5743 if (update_imm (j) == 0)
5744 return 0;
40fb9820 5745
bc0844ae
L		 5746 /* The 3rd operand can't be immediate operand. */
5747 gas_assert (operand_type_check (i.types[2], imm) == 0);
5748 }
29b0f896
AM		 5749
5750 return 1;
5751}
5752
c0f3af97
L		 5753static int
5754bad_implicit_operand (int xmm)
5755{
91d6fa6a
NC		 5756 const char *ireg = xmm ? "xmm0" : "ymm0";
5757
c0f3af97
L		 5758 if (intel_syntax)
5759 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5760 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5761 else
5762 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5763 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5764 return 0;
5765}
5766
29b0f896 5767static int
e3bb37b5 5768process_operands (void)
29b0f896
AM		 5769{
5770 /* Default segment register this instruction will use for memory
5771 accesses. 0 means unknown. This is only for optimizing out
5772 unnecessary segment overrides. */
5773 const seg_entry *default_seg = 0;
5774
2426c15f 5775 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5776 {
91d6fa6a
NC		 5777 unsigned int dupl = i.operands;
5778 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5779 unsigned int j;
5780
c0f3af97 5781 /* The destination must be an xmm register. */
9c2799c2 5782 gas_assert (i.reg_operands
91d6fa6a 5783 && MAX_OPERANDS > dupl
7ab9ffdd 5784 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5785
5786 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5787 {
c0f3af97 5788 /* The first operand is implicit and must be xmm0. */
9c2799c2 5789 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5790 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5791 return bad_implicit_operand (1);
5792
8cd7925b 5793 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5794 {
5795 /* Keep xmm0 for instructions with VEX prefix and 3
5796 sources. */
5797 goto duplicate;
5798 }
e2ec9d29 5799 else
c0f3af97
L		 5800 {
5801 /* We remove the first xmm0 and keep the number of
5802 operands unchanged, which in fact duplicates the
5803 destination. */
5804 for (j = 1; j < i.operands; j++)
5805 {
5806 i.op[j - 1] = i.op[j];
5807 i.types[j - 1] = i.types[j];
5808 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5809 }
5810 }
5811 }
5812 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5813 {
91d6fa6a 5814 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5815 && (i.tm.opcode_modifier.vexsources
5816 == VEX3SOURCES));
c0f3af97
L		 5817
5818 /* Add the implicit xmm0 for instructions with VEX prefix
5819 and 3 sources. */
5820 for (j = i.operands; j > 0; j--)
5821 {
5822 i.op[j] = i.op[j - 1];
5823 i.types[j] = i.types[j - 1];
5824 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5825 }
5826 i.op[0].regs
5827 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5828 i.types[0] = regxmm;
c0f3af97
L		 5829 i.tm.operand_types[0] = regxmm;
5830
5831 i.operands += 2;
5832 i.reg_operands += 2;
5833 i.tm.operands += 2;
5834
91d6fa6a 5835 dupl++;
c0f3af97 5836 dest++;
91d6fa6a
NC		 5837 i.op[dupl] = i.op[dest];
5838 i.types[dupl] = i.types[dest];
5839 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5840 }
c0f3af97
L		 5841 else
5842 {
5843duplicate:
5844 i.operands++;
5845 i.reg_operands++;
5846 i.tm.operands++;
5847
91d6fa6a
NC		 5848 i.op[dupl] = i.op[dest];
5849 i.types[dupl] = i.types[dest];
5850 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5851 }
5852
5853 if (i.tm.opcode_modifier.immext)
5854 process_immext ();
5855 }
5856 else if (i.tm.opcode_modifier.firstxmm0)
5857 {
5858 unsigned int j;
5859
43234a1e 5860 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5861 gas_assert (i.reg_operands
7ab9ffdd 5862 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5863 || operand_type_equal (&i.types[0], &regymm)
5864 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5865 if (register_number (i.op[0].regs) != 0)
c0f3af97 5866 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5867
5868 for (j = 1; j < i.operands; j++)
5869 {
5870 i.op[j - 1] = i.op[j];
5871 i.types[j - 1] = i.types[j];
5872
5873 /* We need to adjust fields in i.tm since they are used by
5874 build_modrm_byte. */
5875 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5876 }
5877
e2ec9d29
L		 5878 i.operands--;
5879 i.reg_operands--;
e2ec9d29
L		 5880 i.tm.operands--;
5881 }
5882 else if (i.tm.opcode_modifier.regkludge)
5883 {
5884 /* The imul $imm, %reg instruction is converted into
5885 imul $imm, %reg, %reg, and the clr %reg instruction
5886 is converted into xor %reg, %reg. */
5887
5888 unsigned int first_reg_op;
5889
5890 if (operand_type_check (i.types[0], reg))
5891 first_reg_op = 0;
5892 else
5893 first_reg_op = 1;
5894 /* Pretend we saw the extra register operand. */
9c2799c2 5895 gas_assert (i.reg_operands == 1
7ab9ffdd 5896 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5897 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5898 i.types[first_reg_op + 1] = i.types[first_reg_op];
5899 i.operands++;
5900 i.reg_operands++;
29b0f896
AM		 5901 }
5902
40fb9820 5903 if (i.tm.opcode_modifier.shortform)
29b0f896 5904 {
40fb9820
L		 5905 if (i.types[0].bitfield.sreg2
5906 || i.types[0].bitfield.sreg3)
29b0f896 5907 {
4eed87de
AM		 5908 if (i.tm.base_opcode == POP_SEG_SHORT
5909 && i.op[0].regs->reg_num == 1)
29b0f896 5910 {
a87af027 5911 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5912 return 0;
29b0f896 5913 }
4eed87de
AM		 5914 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5915 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5916 i.rex |= REX_B;
4eed87de
AM		 5917 }
5918 else
5919 {
7ab9ffdd 5920 /* The register or float register operand is in operand
85f10a01 5921 0 or 1. */
40fb9820 5922 unsigned int op;
7ab9ffdd
L		 5923
5924 if (i.types[0].bitfield.floatreg
5925 || operand_type_check (i.types[0], reg))
5926 op = 0;
5927 else
5928 op = 1;
4eed87de
AM		 5929 /* Register goes in low 3 bits of opcode. */
5930 i.tm.base_opcode |= i.op[op].regs->reg_num;
5931 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5932 i.rex |= REX_B;
40fb9820 5933 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5934 {
4eed87de
AM		 5935 /* Warn about some common errors, but press on regardless.
5936 The first case can be generated by gcc (<= 2.8.1). */
5937 if (i.operands == 2)
5938 {
5939 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5940 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5941 register_prefix, i.op[!intel_syntax].regs->reg_name,
5942 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5943 }
5944 else
5945 {
5946 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5947 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5948 register_prefix, i.op[0].regs->reg_name);
4eed87de 5949 }
29b0f896
AM		 5950 }
5951 }
5952 }
40fb9820 5953 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5954 {
5955 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5956 must be put into the modrm byte). Now, we make the modrm and
5957 index base bytes based on all the info we've collected. */
29b0f896
AM		 5958
5959 default_seg = build_modrm_byte ();
5960 }
8a2ed489 5961 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5962 {
5963 default_seg = &ds;
5964 }
40fb9820 5965 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5966 {
5967 /* For the string instructions that allow a segment override
5968 on one of their operands, the default segment is ds. */
5969 default_seg = &ds;
5970 }
5971
75178d9d
L		 5972 if (i.tm.base_opcode == 0x8d /* lea */
5973 && i.seg[0]
5974 && !quiet_warnings)
30123838 5975 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5976
5977 /* If a segment was explicitly specified, and the specified segment
5978 is not the default, use an opcode prefix to select it. If we
5979 never figured out what the default segment is, then default_seg
5980 will be zero at this point, and the specified segment prefix will
5981 always be used. */
29b0f896
AM		 5982 if ((i.seg[0]) && (i.seg[0] != default_seg))
5983 {
5984 if (!add_prefix (i.seg[0]->seg_prefix))
5985 return 0;
5986 }
5987 return 1;
5988}
5989
5990static const seg_entry *
e3bb37b5 5991build_modrm_byte (void)
29b0f896
AM		 5992{
5993 const seg_entry *default_seg = 0;
c0f3af97 5994 unsigned int source, dest;
8cd7925b 5995 int vex_3_sources;
c0f3af97
L		 5996
5997 /* The first operand of instructions with VEX prefix and 3 sources
5998 must be VEX_Imm4. */
8cd7925b 5999 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6000 if (vex_3_sources)
6001 {
91d6fa6a 6002 unsigned int nds, reg_slot;
4c2c6516 6003 expressionS *exp;
c0f3af97 6004
922d8de8 6005 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6006 && i.tm.opcode_modifier.immext)
6007 {
6008 dest = i.operands - 2;
6009 gas_assert (dest == 3);
6010 }
922d8de8 6011 else
a683cc34 6012 dest = i.operands - 1;
c0f3af97 6013 nds = dest - 1;
922d8de8 6014
a683cc34
SP		 6015 /* There are 2 kinds of instructions:
6016 1. 5 operands: 4 register operands or 3 register operands
6017 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6018 VexW0 or VexW1. The destination must be either XMM, YMM or
6019 ZMM register.
a683cc34
SP		 6020 2. 4 operands: 4 register operands or 3 register operands
6021 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6022 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6023 || (i.reg_operands == 3 && i.mem_operands == 1))
6024 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6025 && (i.tm.opcode_modifier.veximmext
6026 || (i.imm_operands == 1
6027 && i.types[0].bitfield.vec_imm4
6028 && (i.tm.opcode_modifier.vexw == VEXW0
6029 || i.tm.opcode_modifier.vexw == VEXW1)
6030 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6031 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6032 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6033
6034 if (i.imm_operands == 0)
6035 {
6036 /* When there is no immediate operand, generate an 8bit
6037 immediate operand to encode the first operand. */
6038 exp = &im_expressions[i.imm_operands++];
6039 i.op[i.operands].imms = exp;
6040 i.types[i.operands] = imm8;
6041 i.operands++;
6042 /* If VexW1 is set, the first operand is the source and
6043 the second operand is encoded in the immediate operand. */
6044 if (i.tm.opcode_modifier.vexw == VEXW1)
6045 {
6046 source = 0;
6047 reg_slot = 1;
6048 }
6049 else
6050 {
6051 source = 1;
6052 reg_slot = 0;
6053 }
6054
6055 /* FMA swaps REG and NDS. */
6056 if (i.tm.cpu_flags.bitfield.cpufma)
6057 {
6058 unsigned int tmp;
6059 tmp = reg_slot;
6060 reg_slot = nds;
6061 nds = tmp;
6062 }
6063
24981e7b
L		 6064 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6065 &regxmm)
a683cc34 6066 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6067 &regymm)
6068 || operand_type_equal (&i.tm.operand_types[reg_slot],
6069 &regzmm));
a683cc34 6070 exp->X_op = O_constant;
4c692bc7 6071 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6072 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6073 }
922d8de8 6074 else
a683cc34
SP		 6075 {
6076 unsigned int imm_slot;
6077
6078 if (i.tm.opcode_modifier.vexw == VEXW0)
6079 {
6080 /* If VexW0 is set, the third operand is the source and
6081 the second operand is encoded in the immediate
6082 operand. */
6083 source = 2;
6084 reg_slot = 1;
6085 }
6086 else
6087 {
6088 /* VexW1 is set, the second operand is the source and
6089 the third operand is encoded in the immediate
6090 operand. */
6091 source = 1;
6092 reg_slot = 2;
6093 }
6094
6095 if (i.tm.opcode_modifier.immext)
6096 {
6097 /* When ImmExt is set, the immdiate byte is the last
6098 operand. */
6099 imm_slot = i.operands - 1;
6100 source--;
6101 reg_slot--;
6102 }
6103 else
6104 {
6105 imm_slot = 0;
6106
6107 /* Turn on Imm8 so that output_imm will generate it. */
6108 i.types[imm_slot].bitfield.imm8 = 1;
6109 }
6110
24981e7b
L		 6111 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6112 &regxmm)
6113 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6114 &regymm)
6115 || operand_type_equal (&i.tm.operand_types[reg_slot],
6116 &regzmm));
a683cc34 6117 i.op[imm_slot].imms->X_add_number
4c692bc7 6118 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6119 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6120 }
6121
6122 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6123 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6124 &regymm)
6125 || operand_type_equal (&i.tm.operand_types[nds],
6126 &regzmm));
dae39acc 6127 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6128 }
6129 else
6130 source = dest = 0;
29b0f896
AM		 6131
6132 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6133 implicit registers do not count. If there are 3 register
6134 operands, it must be a instruction with VexNDS. For a
6135 instruction with VexNDD, the destination register is encoded
6136 in VEX prefix. If there are 4 register operands, it must be
6137 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6138 if (i.mem_operands == 0
6139 && ((i.reg_operands == 2
2426c15f 6140 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6141 || (i.reg_operands == 3
2426c15f 6142 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6143 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6144 {
cab737b9
L		 6145 switch (i.operands)
6146 {
6147 case 2:
6148 source = 0;
6149 break;
6150 case 3:
c81128dc
L		 6151 /* When there are 3 operands, one of them may be immediate,
6152 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6153 the first operand must be shift count register (cl) or it
6154 is an instruction with VexNDS. */
9c2799c2 6155 gas_assert (i.imm_operands == 1
7ab9ffdd 6156 || (i.imm_operands == 0
2426c15f 6157 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6158 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6159 if (operand_type_check (i.types[0], imm)
6160 || i.types[0].bitfield.shiftcount)
6161 source = 1;
6162 else
6163 source = 0;
cab737b9
L		 6164 break;
6165 case 4:
368d64cc
L		 6166 /* When there are 4 operands, the first two must be 8bit
6167 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6168 one.
6169
6170 For instructions with VexNDS, if the first operand
6171 an imm8, the source operand is the 2nd one. If the last
6172 operand is imm8, the source operand is the first one. */
9c2799c2 6173 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6174 && i.types[0].bitfield.imm8
6175 && i.types[1].bitfield.imm8)
2426c15f 6176 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6177 && i.imm_operands == 1
6178 && (i.types[0].bitfield.imm8
43234a1e
L		 6179 || i.types[i.operands - 1].bitfield.imm8
6180 || i.rounding)));
9f2670f2
L		 6181 if (i.imm_operands == 2)
6182 source = 2;
6183 else
c0f3af97
L		 6184 {
6185 if (i.types[0].bitfield.imm8)
6186 source = 1;
6187 else
6188 source = 0;
6189 }
c0f3af97
L		 6190 break;
6191 case 5:
43234a1e
L		 6192 if (i.tm.opcode_modifier.evex)
6193 {
6194 /* For EVEX instructions, when there are 5 operands, the
6195 first one must be immediate operand. If the second one
6196 is immediate operand, the source operand is the 3th
6197 one. If the last one is immediate operand, the source
6198 operand is the 2nd one. */
6199 gas_assert (i.imm_operands == 2
6200 && i.tm.opcode_modifier.sae
6201 && operand_type_check (i.types[0], imm));
6202 if (operand_type_check (i.types[1], imm))
6203 source = 2;
6204 else if (operand_type_check (i.types[4], imm))
6205 source = 1;
6206 else
6207 abort ();
6208 }
cab737b9
L		 6209 break;
6210 default:
6211 abort ();
6212 }
6213
c0f3af97
L		 6214 if (!vex_3_sources)
6215 {
6216 dest = source + 1;
6217
43234a1e
L		 6218 /* RC/SAE operand could be between DEST and SRC. That happens
6219 when one operand is GPR and the other one is XMM/YMM/ZMM
6220 register. */
6221 if (i.rounding && i.rounding->operand == (int) dest)
6222 dest++;
6223
2426c15f 6224 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6225 {
43234a1e
L		 6226 /* For instructions with VexNDS, the register-only source
6227 operand must be 32/64bit integer, XMM, YMM or ZMM
6228 register. It is encoded in VEX prefix. We need to
6229 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6230
6231 i386_operand_type op;
6232 unsigned int vvvv;
6233
6234 /* Check register-only source operand when two source
6235 operands are swapped. */
6236 if (!i.tm.operand_types[source].bitfield.baseindex
6237 && i.tm.operand_types[dest].bitfield.baseindex)
6238 {
6239 vvvv = source;
6240 source = dest;
6241 }
6242 else
6243 vvvv = dest;
6244
6245 op = i.tm.operand_types[vvvv];
fa99fab2 6246 op.bitfield.regmem = 0;
c0f3af97 6247 if ((dest + 1) >= i.operands
ac4eb736
AM		 6248 || (!op.bitfield.reg32
6249 && op.bitfield.reg64
f12dc422 6250 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6251 && !operand_type_equal (&op, &regymm)
6252 && !operand_type_equal (&op, &regzmm)
6253 && !operand_type_equal (&op, &regmask)))
c0f3af97 6254 abort ();
f12dc422 6255 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6256 dest++;
6257 }
6258 }
29b0f896
AM		 6259
6260 i.rm.mode = 3;
6261 /* One of the register operands will be encoded in the i.tm.reg
6262 field, the other in the combined i.tm.mode and i.tm.regmem
6263 fields. If no form of this instruction supports a memory
6264 destination operand, then we assume the source operand may
6265 sometimes be a memory operand and so we need to store the
6266 destination in the i.rm.reg field. */
40fb9820
L		 6267 if (!i.tm.operand_types[dest].bitfield.regmem
6268 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6269 {
6270 i.rm.reg = i.op[dest].regs->reg_num;
6271 i.rm.regmem = i.op[source].regs->reg_num;
6272 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6273 i.rex |= REX_R;
43234a1e
L		 6274 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6275 i.vrex |= REX_R;
29b0f896 6276 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6277 i.rex |= REX_B;
43234a1e
L		 6278 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6279 i.vrex |= REX_B;
29b0f896
AM		 6280 }
6281 else
6282 {
6283 i.rm.reg = i.op[source].regs->reg_num;
6284 i.rm.regmem = i.op[dest].regs->reg_num;
6285 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6286 i.rex |= REX_B;
43234a1e
L		 6287 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6288 i.vrex |= REX_B;
29b0f896 6289 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6290 i.rex |= REX_R;
43234a1e
L		 6291 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6292 i.vrex |= REX_R;
29b0f896 6293 }
161a04f6 6294 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6295 {
40fb9820
L		 6296 if (!i.types[0].bitfield.control
6297 && !i.types[1].bitfield.control)
c4a530c5 6298 abort ();
161a04f6 6299 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6300 add_prefix (LOCK_PREFIX_OPCODE);
6301 }
29b0f896
AM		 6302 }
6303 else
6304 { /* If it's not 2 reg operands... */
c0f3af97
L		 6305 unsigned int mem;
6306
29b0f896
AM		 6307 if (i.mem_operands)
6308 {
6309 unsigned int fake_zero_displacement = 0;
99018f42 6310 unsigned int op;
4eed87de 6311
7ab9ffdd
L		 6312 for (op = 0; op < i.operands; op++)
6313 if (operand_type_check (i.types[op], anymem))
6314 break;
7ab9ffdd 6315 gas_assert (op < i.operands);
29b0f896 6316
6c30d220
L		 6317 if (i.tm.opcode_modifier.vecsib)
6318 {
6319 if (i.index_reg->reg_num == RegEiz
6320 || i.index_reg->reg_num == RegRiz)
6321 abort ();
6322
6323 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6324 if (!i.base_reg)
6325 {
6326 i.sib.base = NO_BASE_REGISTER;
6327 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6328 /* No Vec_Disp8 if there is no base. */
6329 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6330 i.types[op].bitfield.disp8 = 0;
6331 i.types[op].bitfield.disp16 = 0;
6332 i.types[op].bitfield.disp64 = 0;
6333 if (flag_code != CODE_64BIT)
6334 {
6335 /* Must be 32 bit */
6336 i.types[op].bitfield.disp32 = 1;
6337 i.types[op].bitfield.disp32s = 0;
6338 }
6339 else
6340 {
6341 i.types[op].bitfield.disp32 = 0;
6342 i.types[op].bitfield.disp32s = 1;
6343 }
6344 }
6345 i.sib.index = i.index_reg->reg_num;
6346 if ((i.index_reg->reg_flags & RegRex) != 0)
6347 i.rex |= REX_X;
43234a1e
L		 6348 if ((i.index_reg->reg_flags & RegVRex) != 0)
6349 i.vrex |= REX_X;
6c30d220
L		 6350 }
6351
29b0f896
AM		 6352 default_seg = &ds;
6353
6354 if (i.base_reg == 0)
6355 {
6356 i.rm.mode = 0;
6357 if (!i.disp_operands)
6c30d220
L		 6358 {
6359 fake_zero_displacement = 1;
6360 /* Instructions with VSIB byte need 32bit displacement
6361 if there is no base register. */
6362 if (i.tm.opcode_modifier.vecsib)
6363 i.types[op].bitfield.disp32 = 1;
6364 }
29b0f896
AM		 6365 if (i.index_reg == 0)
6366 {
6c30d220 6367 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6368 /* Operand is just <disp> */
20f0a1fc 6369 if (flag_code == CODE_64BIT)
29b0f896
AM		 6370 {
6371 /* 64bit mode overwrites the 32bit absolute
6372 addressing by RIP relative addressing and
6373 absolute addressing is encoded by one of the
6374 redundant SIB forms. */
6375 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6376 i.sib.base = NO_BASE_REGISTER;
6377 i.sib.index = NO_INDEX_REGISTER;
fc225355 6378 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6379 ? disp32s : disp32);
20f0a1fc 6380 }
fc225355
L		 6381 else if ((flag_code == CODE_16BIT)
6382 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6383 {
6384 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6385 i.types[op] = disp16;
20f0a1fc
NC		 6386 }
6387 else
6388 {
6389 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6390 i.types[op] = disp32;
29b0f896
AM		 6391 }
6392 }
6c30d220 6393 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6394 {
6c30d220 6395 /* !i.base_reg && i.index_reg */
db51cc60
L		 6396 if (i.index_reg->reg_num == RegEiz
6397 || i.index_reg->reg_num == RegRiz)
6398 i.sib.index = NO_INDEX_REGISTER;
6399 else
6400 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6401 i.sib.base = NO_BASE_REGISTER;
6402 i.sib.scale = i.log2_scale_factor;
6403 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6404 /* No Vec_Disp8 if there is no base. */
6405 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6406 i.types[op].bitfield.disp8 = 0;
6407 i.types[op].bitfield.disp16 = 0;
6408 i.types[op].bitfield.disp64 = 0;
29b0f896 6409 if (flag_code != CODE_64BIT)
40fb9820
L		 6410 {
6411 /* Must be 32 bit */
6412 i.types[op].bitfield.disp32 = 1;
6413 i.types[op].bitfield.disp32s = 0;
6414 }
29b0f896 6415 else
40fb9820
L		 6416 {
6417 i.types[op].bitfield.disp32 = 0;
6418 i.types[op].bitfield.disp32s = 1;
6419 }
29b0f896 6420 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6421 i.rex |= REX_X;
29b0f896
AM		 6422 }
6423 }
6424 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6425 else if (i.base_reg->reg_num == RegRip ||
6426 i.base_reg->reg_num == RegEip)
29b0f896 6427 {
6c30d220 6428 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6429 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6430 i.types[op].bitfield.disp8 = 0;
6431 i.types[op].bitfield.disp16 = 0;
6432 i.types[op].bitfield.disp32 = 0;
6433 i.types[op].bitfield.disp32s = 1;
6434 i.types[op].bitfield.disp64 = 0;
43234a1e 6435 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6436 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6437 if (! i.disp_operands)
6438 fake_zero_displacement = 1;
29b0f896 6439 }
40fb9820 6440 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6441 {
6c30d220 6442 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6443 switch (i.base_reg->reg_num)
6444 {
6445 case 3: /* (%bx) */
6446 if (i.index_reg == 0)
6447 i.rm.regmem = 7;
6448 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6449 i.rm.regmem = i.index_reg->reg_num - 6;
6450 break;
6451 case 5: /* (%bp) */
6452 default_seg = &ss;
6453 if (i.index_reg == 0)
6454 {
6455 i.rm.regmem = 6;
40fb9820 6456 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6457 {
6458 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6459 if (i.tm.operand_types[op].bitfield.vec_disp8)
6460 i.types[op].bitfield.vec_disp8 = 1;
6461 else
6462 i.types[op].bitfield.disp8 = 1;
252b5132 6463 fake_zero_displacement = 1;
29b0f896
AM		 6464 }
6465 }
6466 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6467 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6468 break;
6469 default: /* (%si) -> 4 or (%di) -> 5 */
6470 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6471 }
6472 i.rm.mode = mode_from_disp_size (i.types[op]);
6473 }
6474 else /* i.base_reg and 32/64 bit mode */
6475 {
6476 if (flag_code == CODE_64BIT
40fb9820
L		 6477 && operand_type_check (i.types[op], disp))
6478 {
6479 i386_operand_type temp;
0dfbf9d7 6480 operand_type_set (&temp, 0);
40fb9820 6481 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6482 temp.bitfield.vec_disp8
6483 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6484 i.types[op] = temp;
6485 if (i.prefix[ADDR_PREFIX] == 0)
6486 i.types[op].bitfield.disp32s = 1;
6487 else
6488 i.types[op].bitfield.disp32 = 1;
6489 }
20f0a1fc 6490
6c30d220
L		 6491 if (!i.tm.opcode_modifier.vecsib)
6492 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6493 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6494 i.rex |= REX_B;
29b0f896
AM		 6495 i.sib.base = i.base_reg->reg_num;
6496 /* x86-64 ignores REX prefix bit here to avoid decoder
6497 complications. */
848930b2
JB		 6498 if (!(i.base_reg->reg_flags & RegRex)
6499 && (i.base_reg->reg_num == EBP_REG_NUM
6500 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6501 default_seg = &ss;
848930b2 6502 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6503 {
848930b2 6504 fake_zero_displacement = 1;
43234a1e
L		 6505 if (i.tm.operand_types [op].bitfield.vec_disp8)
6506 i.types[op].bitfield.vec_disp8 = 1;
6507 else
6508 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6509 }
6510 i.sib.scale = i.log2_scale_factor;
6511 if (i.index_reg == 0)
6512 {
6c30d220 6513 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6514 /* <disp>(%esp) becomes two byte modrm with no index
6515 register. We've already stored the code for esp
6516 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6517 Any base register besides %esp will not use the
6518 extra modrm byte. */
6519 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6520 }
6c30d220 6521 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6522 {
db51cc60
L		 6523 if (i.index_reg->reg_num == RegEiz
6524 || i.index_reg->reg_num == RegRiz)
6525 i.sib.index = NO_INDEX_REGISTER;
6526 else
6527 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6528 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6529 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6530 i.rex |= REX_X;
29b0f896 6531 }
67a4f2b7
AO		 6532
6533 if (i.disp_operands
6534 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6535 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6536 i.rm.mode = 0;
6537 else
a501d77e
L		 6538 {
6539 if (!fake_zero_displacement
6540 && !i.disp_operands
6541 && i.disp_encoding)
6542 {
6543 fake_zero_displacement = 1;
6544 if (i.disp_encoding == disp_encoding_8bit)
6545 i.types[op].bitfield.disp8 = 1;
6546 else
6547 i.types[op].bitfield.disp32 = 1;
6548 }
6549 i.rm.mode = mode_from_disp_size (i.types[op]);
6550 }
29b0f896 6551 }
252b5132 6552
29b0f896
AM		 6553 if (fake_zero_displacement)
6554 {
6555 /* Fakes a zero displacement assuming that i.types[op]
6556 holds the correct displacement size. */
6557 expressionS *exp;
6558
9c2799c2 6559 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6560 exp = &disp_expressions[i.disp_operands++];
6561 i.op[op].disps = exp;
6562 exp->X_op = O_constant;
6563 exp->X_add_number = 0;
6564 exp->X_add_symbol = (symbolS *) 0;
6565 exp->X_op_symbol = (symbolS *) 0;
6566 }
c0f3af97
L		 6567
6568 mem = op;
29b0f896 6569 }
c0f3af97
L		 6570 else
6571 mem = ~0;
252b5132 6572
8c43a48b 6573 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6574 {
6575 if (operand_type_check (i.types[0], imm))
6576 i.vex.register_specifier = NULL;
6577 else
6578 {
6579 /* VEX.vvvv encodes one of the sources when the first
6580 operand is not an immediate. */
1ef99a7b 6581 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6582 i.vex.register_specifier = i.op[0].regs;
6583 else
6584 i.vex.register_specifier = i.op[1].regs;
6585 }
6586
6587 /* Destination is a XMM register encoded in the ModRM.reg
6588 and VEX.R bit. */
6589 i.rm.reg = i.op[2].regs->reg_num;
6590 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6591 i.rex |= REX_R;
6592
6593 /* ModRM.rm and VEX.B encodes the other source. */
6594 if (!i.mem_operands)
6595 {
6596 i.rm.mode = 3;
6597
1ef99a7b 6598 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6599 i.rm.regmem = i.op[1].regs->reg_num;
6600 else
6601 i.rm.regmem = i.op[0].regs->reg_num;
6602
6603 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6604 i.rex |= REX_B;
6605 }
6606 }
2426c15f 6607 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6608 {
6609 i.vex.register_specifier = i.op[2].regs;
6610 if (!i.mem_operands)
6611 {
6612 i.rm.mode = 3;
6613 i.rm.regmem = i.op[1].regs->reg_num;
6614 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6615 i.rex |= REX_B;
6616 }
6617 }
29b0f896
AM		 6618 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6619 (if any) based on i.tm.extension_opcode. Again, we must be
6620 careful to make sure that segment/control/debug/test/MMX
6621 registers are coded into the i.rm.reg field. */
f88c9eb0 6622 else if (i.reg_operands)
29b0f896 6623 {
99018f42 6624 unsigned int op;
7ab9ffdd
L		 6625 unsigned int vex_reg = ~0;
6626
6627 for (op = 0; op < i.operands; op++)
6628 if (i.types[op].bitfield.reg8
6629 || i.types[op].bitfield.reg16
6630 || i.types[op].bitfield.reg32
6631 || i.types[op].bitfield.reg64
6632 || i.types[op].bitfield.regmmx
6633 || i.types[op].bitfield.regxmm
6634 || i.types[op].bitfield.regymm
7e8b059b 6635 || i.types[op].bitfield.regbnd
43234a1e
L		 6636 || i.types[op].bitfield.regzmm
6637 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6638 || i.types[op].bitfield.sreg2
6639 || i.types[op].bitfield.sreg3
6640 || i.types[op].bitfield.control
6641 || i.types[op].bitfield.debug
6642 || i.types[op].bitfield.test)
6643 break;
c0209578 6644
7ab9ffdd
L		 6645 if (vex_3_sources)
6646 op = dest;
2426c15f 6647 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6648 {
6649 /* For instructions with VexNDS, the register-only
6650 source operand is encoded in VEX prefix. */
6651 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6652
7ab9ffdd 6653 if (op > mem)
c0f3af97 6654 {
7ab9ffdd
L		 6655 vex_reg = op++;
6656 gas_assert (op < i.operands);
c0f3af97
L		 6657 }
6658 else
c0f3af97 6659 {
f12dc422
L		 6660 /* Check register-only source operand when two source
6661 operands are swapped. */
6662 if (!i.tm.operand_types[op].bitfield.baseindex
6663 && i.tm.operand_types[op + 1].bitfield.baseindex)
6664 {
6665 vex_reg = op;
6666 op += 2;
6667 gas_assert (mem == (vex_reg + 1)
6668 && op < i.operands);
6669 }
6670 else
6671 {
6672 vex_reg = op + 1;
6673 gas_assert (vex_reg < i.operands);
6674 }
c0f3af97 6675 }
7ab9ffdd 6676 }
2426c15f 6677 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6678 {
f12dc422 6679 /* For instructions with VexNDD, the register destination
7ab9ffdd 6680 is encoded in VEX prefix. */
f12dc422
L		 6681 if (i.mem_operands == 0)
6682 {
6683 /* There is no memory operand. */
6684 gas_assert ((op + 2) == i.operands);
6685 vex_reg = op + 1;
6686 }
6687 else
8d63c93e 6688 {
f12dc422
L		 6689 /* There are only 2 operands. */
6690 gas_assert (op < 2 && i.operands == 2);
6691 vex_reg = 1;
6692 }
7ab9ffdd
L		 6693 }
6694 else
6695 gas_assert (op < i.operands);
99018f42 6696
7ab9ffdd
L		 6697 if (vex_reg != (unsigned int) ~0)
6698 {
f12dc422 6699 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6700
f12dc422
L		 6701 if (type->bitfield.reg32 != 1
6702 && type->bitfield.reg64 != 1
6703 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6704 && !operand_type_equal (type, &regymm)
6705 && !operand_type_equal (type, &regzmm)
6706 && !operand_type_equal (type, &regmask))
7ab9ffdd 6707 abort ();
f88c9eb0 6708
7ab9ffdd
L		 6709 i.vex.register_specifier = i.op[vex_reg].regs;
6710 }
6711
1b9f0c97
L		 6712 /* Don't set OP operand twice. */
6713 if (vex_reg != op)
7ab9ffdd 6714 {
1b9f0c97
L		 6715 /* If there is an extension opcode to put here, the
6716 register number must be put into the regmem field. */
6717 if (i.tm.extension_opcode != None)
6718 {
6719 i.rm.regmem = i.op[op].regs->reg_num;
6720 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6721 i.rex |= REX_B;
43234a1e
L		 6722 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6723 i.vrex |= REX_B;
1b9f0c97
L		 6724 }
6725 else
6726 {
6727 i.rm.reg = i.op[op].regs->reg_num;
6728 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6729 i.rex |= REX_R;
43234a1e
L		 6730 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6731 i.vrex |= REX_R;
1b9f0c97 6732 }
7ab9ffdd 6733 }
252b5132 6734
29b0f896
AM		 6735 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6736 must set it to 3 to indicate this is a register operand
6737 in the regmem field. */
6738 if (!i.mem_operands)
6739 i.rm.mode = 3;
6740 }
252b5132 6741
29b0f896 6742 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6743 if (i.tm.extension_opcode != None)
29b0f896
AM		 6744 i.rm.reg = i.tm.extension_opcode;
6745 }
6746 return default_seg;
6747}
252b5132 6748
29b0f896 6749static void
e3bb37b5 6750output_branch (void)
29b0f896
AM		 6751{
6752 char *p;
f8a5c266 6753 int size;
29b0f896
AM		 6754 int code16;
6755 int prefix;
6756 relax_substateT subtype;
6757 symbolS *sym;
6758 offsetT off;
6759
f8a5c266 6760 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6761 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6762
6763 prefix = 0;
6764 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6765 {
29b0f896
AM		 6766 prefix = 1;
6767 i.prefixes -= 1;
6768 code16 ^= CODE16;
252b5132 6769 }
29b0f896
AM		 6770 /* Pentium4 branch hints. */
6771 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6772 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6773 {
29b0f896
AM		 6774 prefix++;
6775 i.prefixes--;
6776 }
6777 if (i.prefix[REX_PREFIX] != 0)
6778 {
6779 prefix++;
6780 i.prefixes--;
2f66722d
AM		 6781 }
6782
7e8b059b
L		 6783 /* BND prefixed jump. */
6784 if (i.prefix[BND_PREFIX] != 0)
6785 {
6786 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6787 i.prefixes -= 1;
6788 }
6789
29b0f896
AM		 6790 if (i.prefixes != 0 && !intel_syntax)
6791 as_warn (_("skipping prefixes on this instruction"));
6792
6793 /* It's always a symbol; End frag & setup for relax.
6794 Make sure there is enough room in this frag for the largest
6795 instruction we may generate in md_convert_frag. This is 2
6796 bytes for the opcode and room for the prefix and largest
6797 displacement. */
6798 frag_grow (prefix + 2 + 4);
6799 /* Prefix and 1 opcode byte go in fr_fix. */
6800 p = frag_more (prefix + 1);
6801 if (i.prefix[DATA_PREFIX] != 0)
6802 *p++ = DATA_PREFIX_OPCODE;
6803 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6804 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6805 *p++ = i.prefix[SEG_PREFIX];
6806 if (i.prefix[REX_PREFIX] != 0)
6807 *p++ = i.prefix[REX_PREFIX];
6808 *p = i.tm.base_opcode;
6809
6810 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6811 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6812 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6813 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6814 else
f8a5c266 6815 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6816 subtype |= code16;
3e73aa7c 6817
29b0f896
AM		 6818 sym = i.op[0].disps->X_add_symbol;
6819 off = i.op[0].disps->X_add_number;
3e73aa7c 6820
29b0f896
AM		 6821 if (i.op[0].disps->X_op != O_constant
6822 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6823 {
29b0f896
AM		 6824 /* Handle complex expressions. */
6825 sym = make_expr_symbol (i.op[0].disps);
6826 off = 0;
6827 }
3e73aa7c 6828
29b0f896
AM		 6829 /* 1 possible extra opcode + 4 byte displacement go in var part.
6830 Pass reloc in fr_var. */
d258b828 6831 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6832}
3e73aa7c 6833
29b0f896 6834static void
e3bb37b5 6835output_jump (void)
29b0f896
AM		 6836{
6837 char *p;
6838 int size;
3e02c1cc 6839 fixS *fixP;
29b0f896 6840
40fb9820 6841 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6842 {
6843 /* This is a loop or jecxz type instruction. */
6844 size = 1;
6845 if (i.prefix[ADDR_PREFIX] != 0)
6846 {
6847 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6848 i.prefixes -= 1;
6849 }
6850 /* Pentium4 branch hints. */
6851 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6852 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6853 {
6854 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6855 i.prefixes--;
3e73aa7c
JH		 6856 }
6857 }
29b0f896
AM		 6858 else
6859 {
6860 int code16;
3e73aa7c 6861
29b0f896
AM		 6862 code16 = 0;
6863 if (flag_code == CODE_16BIT)
6864 code16 = CODE16;
3e73aa7c 6865
29b0f896
AM		 6866 if (i.prefix[DATA_PREFIX] != 0)
6867 {
6868 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6869 i.prefixes -= 1;
6870 code16 ^= CODE16;
6871 }
252b5132 6872
29b0f896
AM		 6873 size = 4;
6874 if (code16)
6875 size = 2;
6876 }
9fcc94b6 6877
29b0f896
AM		 6878 if (i.prefix[REX_PREFIX] != 0)
6879 {
6880 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6881 i.prefixes -= 1;
6882 }
252b5132 6883
7e8b059b
L		 6884 /* BND prefixed jump. */
6885 if (i.prefix[BND_PREFIX] != 0)
6886 {
6887 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6888 i.prefixes -= 1;
6889 }
6890
29b0f896
AM		 6891 if (i.prefixes != 0 && !intel_syntax)
6892 as_warn (_("skipping prefixes on this instruction"));
e0890092 6893
42164a71
L		 6894 p = frag_more (i.tm.opcode_length + size);
6895 switch (i.tm.opcode_length)
6896 {
6897 case 2:
6898 *p++ = i.tm.base_opcode >> 8;
6899 case 1:
6900 *p++ = i.tm.base_opcode;
6901 break;
6902 default:
6903 abort ();
6904 }
e0890092 6905
3e02c1cc 6906 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6907 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6908
6909 /* All jumps handled here are signed, but don't use a signed limit
6910 check for 32 and 16 bit jumps as we want to allow wrap around at
6911 4G and 64k respectively. */
6912 if (size == 1)
6913 fixP->fx_signed = 1;
29b0f896 6914}
e0890092 6915
29b0f896 6916static void
e3bb37b5 6917output_interseg_jump (void)
29b0f896
AM		 6918{
6919 char *p;
6920 int size;
6921 int prefix;
6922 int code16;
252b5132 6923
29b0f896
AM		 6924 code16 = 0;
6925 if (flag_code == CODE_16BIT)
6926 code16 = CODE16;
a217f122 6927
29b0f896
AM		 6928 prefix = 0;
6929 if (i.prefix[DATA_PREFIX] != 0)
6930 {
6931 prefix = 1;
6932 i.prefixes -= 1;
6933 code16 ^= CODE16;
6934 }
6935 if (i.prefix[REX_PREFIX] != 0)
6936 {
6937 prefix++;
6938 i.prefixes -= 1;
6939 }
252b5132 6940
29b0f896
AM		 6941 size = 4;
6942 if (code16)
6943 size = 2;
252b5132 6944
29b0f896
AM		 6945 if (i.prefixes != 0 && !intel_syntax)
6946 as_warn (_("skipping prefixes on this instruction"));
252b5132 6947
29b0f896
AM		 6948 /* 1 opcode; 2 segment; offset */
6949 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6950
29b0f896
AM		 6951 if (i.prefix[DATA_PREFIX] != 0)
6952 *p++ = DATA_PREFIX_OPCODE;
252b5132 6953
29b0f896
AM		 6954 if (i.prefix[REX_PREFIX] != 0)
6955 *p++ = i.prefix[REX_PREFIX];
252b5132 6956
29b0f896
AM		 6957 *p++ = i.tm.base_opcode;
6958 if (i.op[1].imms->X_op == O_constant)
6959 {
6960 offsetT n = i.op[1].imms->X_add_number;
252b5132 6961
29b0f896
AM		 6962 if (size == 2
6963 && !fits_in_unsigned_word (n)
6964 && !fits_in_signed_word (n))
6965 {
6966 as_bad (_("16-bit jump out of range"));
6967 return;
6968 }
6969 md_number_to_chars (p, n, size);
6970 }
6971 else
6972 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6973 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6974 if (i.op[0].imms->X_op != O_constant)
6975 as_bad (_("can't handle non absolute segment in `%s'"),
6976 i.tm.name);
6977 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6978}
a217f122 6979
29b0f896 6980static void
e3bb37b5 6981output_insn (void)
29b0f896 6982{
2bbd9c25
JJ		 6983 fragS *insn_start_frag;
6984 offsetT insn_start_off;
6985
29b0f896
AM		 6986 /* Tie dwarf2 debug info to the address at the start of the insn.
6987 We can't do this after the insn has been output as the current
6988 frag may have been closed off. eg. by frag_var. */
6989 dwarf2_emit_insn (0);
6990
2bbd9c25
JJ		 6991 insn_start_frag = frag_now;
6992 insn_start_off = frag_now_fix ();
6993
29b0f896 6994 /* Output jumps. */
40fb9820 6995 if (i.tm.opcode_modifier.jump)
29b0f896 6996 output_branch ();
40fb9820
L		 6997 else if (i.tm.opcode_modifier.jumpbyte
6998 || i.tm.opcode_modifier.jumpdword)
29b0f896 6999 output_jump ();
40fb9820 7000 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7001 output_interseg_jump ();
7002 else
7003 {
7004 /* Output normal instructions here. */
7005 char *p;
7006 unsigned char *q;
47465058 7007 unsigned int j;
331d2d0d 7008 unsigned int prefix;
4dffcebc 7009
e4e00185
AS		 7010 if (avoid_fence
7011 && i.tm.base_opcode == 0xfae
7012 && i.operands == 1
7013 && i.imm_operands == 1
7014 && (i.op[0].imms->X_add_number == 0xe8
7015 || i.op[0].imms->X_add_number == 0xf0
7016 || i.op[0].imms->X_add_number == 0xf8))
7017 {
7018 /* Encode lfence, mfence, and sfence as
7019 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7020 offsetT val = 0x240483f0ULL;
7021 p = frag_more (5);
7022 md_number_to_chars (p, val, 5);
7023 return;
7024 }
7025
d022bddd
IT		 7026 /* Some processors fail on LOCK prefix. This options makes
7027 assembler ignore LOCK prefix and serves as a workaround. */
7028 if (omit_lock_prefix)
7029 {
7030 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7031 return;
7032 i.prefix[LOCK_PREFIX] = 0;
7033 }
7034
43234a1e
L		 7035 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7036 don't need the explicit prefix. */
7037 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7038 {
c0f3af97 7039 switch (i.tm.opcode_length)
bc4bd9ab 7040 {
c0f3af97
L		 7041 case 3:
7042 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7043 {
c0f3af97
L		 7044 prefix = (i.tm.base_opcode >> 24) & 0xff;
7045 goto check_prefix;
7046 }
7047 break;
7048 case 2:
7049 if ((i.tm.base_opcode & 0xff0000) != 0)
7050 {
7051 prefix = (i.tm.base_opcode >> 16) & 0xff;
7052 if (i.tm.cpu_flags.bitfield.cpupadlock)
7053 {
4dffcebc 7054check_prefix:
c0f3af97 7055 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7056 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7057 != REPE_PREFIX_OPCODE))
7058 add_prefix (prefix);
7059 }
7060 else
4dffcebc
L		 7061 add_prefix (prefix);
7062 }
c0f3af97
L		 7063 break;
7064 case 1:
7065 break;
7066 default:
7067 abort ();
bc4bd9ab 7068 }
c0f3af97 7069
6d19a37a 7070#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7071 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7072 R_X86_64_GOTTPOFF relocation so that linker can safely
7073 perform IE->LE optimization. */
7074 if (x86_elf_abi == X86_64_X32_ABI
7075 && i.operands == 2
7076 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7077 && i.prefix[REX_PREFIX] == 0)
7078 add_prefix (REX_OPCODE);
6d19a37a 7079#endif
cf61b747 7080
c0f3af97
L		 7081 /* The prefix bytes. */
7082 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7083 if (*q)
7084 FRAG_APPEND_1_CHAR (*q);
0f10071e 7085 }
ae5c1c7b 7086 else
c0f3af97
L		 7087 {
7088 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7089 if (*q)
7090 switch (j)
7091 {
7092 case REX_PREFIX:
7093 /* REX byte is encoded in VEX prefix. */
7094 break;
7095 case SEG_PREFIX:
7096 case ADDR_PREFIX:
7097 FRAG_APPEND_1_CHAR (*q);
7098 break;
7099 default:
7100 /* There should be no other prefixes for instructions
7101 with VEX prefix. */
7102 abort ();
7103 }
7104
43234a1e
L		 7105 /* For EVEX instructions i.vrex should become 0 after
7106 build_evex_prefix. For VEX instructions upper 16 registers
7107 aren't available, so VREX should be 0. */
7108 if (i.vrex)
7109 abort ();
c0f3af97
L		 7110 /* Now the VEX prefix. */
7111 p = frag_more (i.vex.length);
7112 for (j = 0; j < i.vex.length; j++)
7113 p[j] = i.vex.bytes[j];
7114 }
252b5132 7115
29b0f896 7116 /* Now the opcode; be careful about word order here! */
4dffcebc 7117 if (i.tm.opcode_length == 1)
29b0f896
AM		 7118 {
7119 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7120 }
7121 else
7122 {
4dffcebc 7123 switch (i.tm.opcode_length)
331d2d0d 7124 {
43234a1e
L		 7125 case 4:
7126 p = frag_more (4);
7127 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7128 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7129 break;
4dffcebc 7130 case 3:
331d2d0d
L		 7131 p = frag_more (3);
7132 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7133 break;
7134 case 2:
7135 p = frag_more (2);
7136 break;
7137 default:
7138 abort ();
7139 break;
331d2d0d 7140 }
0f10071e 7141
29b0f896
AM		 7142 /* Put out high byte first: can't use md_number_to_chars! */
7143 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7144 *p = i.tm.base_opcode & 0xff;
7145 }
3e73aa7c 7146
29b0f896 7147 /* Now the modrm byte and sib byte (if present). */
40fb9820 7148 if (i.tm.opcode_modifier.modrm)
29b0f896 7149 {
4a3523fa
L		 7150 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7151 | i.rm.reg << 3
7152 | i.rm.mode << 6));
29b0f896
AM		 7153 /* If i.rm.regmem == ESP (4)
7154 && i.rm.mode != (Register mode)
7155 && not 16 bit
7156 ==> need second modrm byte. */
7157 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7158 && i.rm.mode != 3
40fb9820 7159 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7160 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7161 | i.sib.index << 3
7162 | i.sib.scale << 6));
29b0f896 7163 }
3e73aa7c 7164
29b0f896 7165 if (i.disp_operands)
2bbd9c25 7166 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7167
29b0f896 7168 if (i.imm_operands)
2bbd9c25 7169 output_imm (insn_start_frag, insn_start_off);
29b0f896 7170 }
252b5132 7171
29b0f896
AM		 7172#ifdef DEBUG386
7173 if (flag_debug)
7174 {
7b81dfbb 7175 pi ("" /*line*/, &i);
29b0f896
AM		 7176 }
7177#endif /* DEBUG386 */
7178}
252b5132 7179
e205caa7
L		 7180/* Return the size of the displacement operand N. */
7181
7182static int
7183disp_size (unsigned int n)
7184{
7185 int size = 4;
43234a1e
L		 7186
7187 /* Vec_Disp8 has to be 8bit. */
7188 if (i.types[n].bitfield.vec_disp8)
7189 size = 1;
7190 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7191 size = 8;
7192 else if (i.types[n].bitfield.disp8)
7193 size = 1;
7194 else if (i.types[n].bitfield.disp16)
7195 size = 2;
e205caa7
L		 7196 return size;
7197}
7198
7199/* Return the size of the immediate operand N. */
7200
7201static int
7202imm_size (unsigned int n)
7203{
7204 int size = 4;
40fb9820
L		 7205 if (i.types[n].bitfield.imm64)
7206 size = 8;
7207 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7208 size = 1;
7209 else if (i.types[n].bitfield.imm16)
7210 size = 2;
e205caa7
L		 7211 return size;
7212}
7213
29b0f896 7214static void
64e74474 7215output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7216{
7217 char *p;
7218 unsigned int n;
252b5132 7219
29b0f896
AM		 7220 for (n = 0; n < i.operands; n++)
7221 {
43234a1e
L		 7222 if (i.types[n].bitfield.vec_disp8
7223 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7224 {
7225 if (i.op[n].disps->X_op == O_constant)
7226 {
e205caa7 7227 int size = disp_size (n);
43234a1e 7228 offsetT val = i.op[n].disps->X_add_number;
252b5132 7229
43234a1e
L		 7230 if (i.types[n].bitfield.vec_disp8)
7231 val >>= i.memshift;
7232 val = offset_in_range (val, size);
29b0f896
AM		 7233 p = frag_more (size);
7234 md_number_to_chars (p, val, size);
7235 }
7236 else
7237 {
f86103b7 7238 enum bfd_reloc_code_real reloc_type;
e205caa7 7239 int size = disp_size (n);
40fb9820 7240 int sign = i.types[n].bitfield.disp32s;
29b0f896 7241 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7242 fixS *fixP;
29b0f896 7243
e205caa7 7244 /* We can't have 8 bit displacement here. */
9c2799c2 7245 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7246
29b0f896
AM		 7247 /* The PC relative address is computed relative
7248 to the instruction boundary, so in case immediate
7249 fields follows, we need to adjust the value. */
7250 if (pcrel && i.imm_operands)
7251 {
29b0f896 7252 unsigned int n1;
e205caa7 7253 int sz = 0;
252b5132 7254
29b0f896 7255 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7256 if (operand_type_check (i.types[n1], imm))
252b5132 7257 {
e205caa7
L		 7258 /* Only one immediate is allowed for PC
7259 relative address. */
9c2799c2 7260 gas_assert (sz == 0);
e205caa7
L		 7261 sz = imm_size (n1);
7262 i.op[n].disps->X_add_number -= sz;
252b5132 7263 }
29b0f896 7264 /* We should find the immediate. */
9c2799c2 7265 gas_assert (sz != 0);
29b0f896 7266 }
520dc8e8 7267
29b0f896 7268 p = frag_more (size);
d258b828 7269 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7270 if (GOT_symbol
2bbd9c25 7271 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7272 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7273 || reloc_type == BFD_RELOC_X86_64_32S
7274 || (reloc_type == BFD_RELOC_64
7275 && object_64bit))
d6ab8113
JB		 7276 && (i.op[n].disps->X_op == O_symbol
7277 || (i.op[n].disps->X_op == O_add
7278 && ((symbol_get_value_expression
7279 (i.op[n].disps->X_op_symbol)->X_op)
7280 == O_subtract))))
7281 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7282 {
7283 offsetT add;
7284
7285 if (insn_start_frag == frag_now)
7286 add = (p - frag_now->fr_literal) - insn_start_off;
7287 else
7288 {
7289 fragS *fr;
7290
7291 add = insn_start_frag->fr_fix - insn_start_off;
7292 for (fr = insn_start_frag->fr_next;
7293 fr && fr != frag_now; fr = fr->fr_next)
7294 add += fr->fr_fix;
7295 add += p - frag_now->fr_literal;
7296 }
7297
4fa24527 7298 if (!object_64bit)
7b81dfbb
AJ		 7299 {
7300 reloc_type = BFD_RELOC_386_GOTPC;
7301 i.op[n].imms->X_add_number += add;
7302 }
7303 else if (reloc_type == BFD_RELOC_64)
7304 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7305 else
7b81dfbb
AJ		 7306 /* Don't do the adjustment for x86-64, as there
7307 the pcrel addressing is relative to the _next_
7308 insn, and that is taken care of in other code. */
d6ab8113 7309 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7310 }
02a86693
L		 7311 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7312 size, i.op[n].disps, pcrel,
7313 reloc_type);
7314 /* Check for "call/jmp *mem", "mov mem, %reg",
7315 "test %reg, mem" and "binop mem, %reg" where binop
7316 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7317 instructions. Always generate R_386_GOT32X for
7318 "sym*GOT" operand in 32-bit mode. */
7319 if ((generate_relax_relocations
7320 || (!object_64bit
7321 && i.rm.mode == 0
7322 && i.rm.regmem == 5))
7323 && (i.rm.mode == 2
7324 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7325 && ((i.operands == 1
7326 && i.tm.base_opcode == 0xff
7327 && (i.rm.reg == 2 || i.rm.reg == 4))
7328 || (i.operands == 2
7329 && (i.tm.base_opcode == 0x8b
7330 || i.tm.base_opcode == 0x85
7331 || (i.tm.base_opcode & 0xc7) == 0x03))))
7332 {
7333 if (object_64bit)
7334 {
7335 fixP->fx_tcbit = i.rex != 0;
7336 if (i.base_reg
7337 && (i.base_reg->reg_num == RegRip
7338 || i.base_reg->reg_num == RegEip))
7339 fixP->fx_tcbit2 = 1;
7340 }
7341 else
7342 fixP->fx_tcbit2 = 1;
7343 }
29b0f896
AM		 7344 }
7345 }
7346 }
7347}
252b5132 7348
29b0f896 7349static void
64e74474 7350output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7351{
7352 char *p;
7353 unsigned int n;
252b5132 7354
29b0f896
AM		 7355 for (n = 0; n < i.operands; n++)
7356 {
43234a1e
L		 7357 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7358 if (i.rounding && (int) n == i.rounding->operand)
7359 continue;
7360
40fb9820 7361 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7362 {
7363 if (i.op[n].imms->X_op == O_constant)
7364 {
e205caa7 7365 int size = imm_size (n);
29b0f896 7366 offsetT val;
b4cac588 7367
29b0f896
AM		 7368 val = offset_in_range (i.op[n].imms->X_add_number,
7369 size);
7370 p = frag_more (size);
7371 md_number_to_chars (p, val, size);
7372 }
7373 else
7374 {
7375 /* Not absolute_section.
7376 Need a 32-bit fixup (don't support 8bit
7377 non-absolute imms). Try to support other
7378 sizes ... */
f86103b7 7379 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7380 int size = imm_size (n);
7381 int sign;
29b0f896 7382
40fb9820 7383 if (i.types[n].bitfield.imm32s
a7d61044 7384 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7385 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7386 sign = 1;
e205caa7
L		 7387 else
7388 sign = 0;
520dc8e8 7389
29b0f896 7390 p = frag_more (size);
d258b828 7391 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7392
2bbd9c25
JJ		 7393 /* This is tough to explain. We end up with this one if we
7394 * have operands that look like
7395 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7396 * obtain the absolute address of the GOT, and it is strongly
7397 * preferable from a performance point of view to avoid using
7398 * a runtime relocation for this. The actual sequence of
7399 * instructions often look something like:
7400 *
7401 * call .L66
7402 * .L66:
7403 * popl %ebx
7404 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7405 *
7406 * The call and pop essentially return the absolute address
7407 * of the label .L66 and store it in %ebx. The linker itself
7408 * will ultimately change the first operand of the addl so
7409 * that %ebx points to the GOT, but to keep things simple, the
7410 * .o file must have this operand set so that it generates not
7411 * the absolute address of .L66, but the absolute address of
7412 * itself. This allows the linker itself simply treat a GOTPC
7413 * relocation as asking for a pcrel offset to the GOT to be
7414 * added in, and the addend of the relocation is stored in the
7415 * operand field for the instruction itself.
7416 *
7417 * Our job here is to fix the operand so that it would add
7418 * the correct offset so that %ebx would point to itself. The
7419 * thing that is tricky is that .-.L66 will point to the
7420 * beginning of the instruction, so we need to further modify
7421 * the operand so that it will point to itself. There are
7422 * other cases where you have something like:
7423 *
7424 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7425 *
7426 * and here no correction would be required. Internally in
7427 * the assembler we treat operands of this form as not being
7428 * pcrel since the '.' is explicitly mentioned, and I wonder
7429 * whether it would simplify matters to do it this way. Who
7430 * knows. In earlier versions of the PIC patches, the
7431 * pcrel_adjust field was used to store the correction, but
7432 * since the expression is not pcrel, I felt it would be
7433 * confusing to do it this way. */
7434
d6ab8113 7435 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7436 || reloc_type == BFD_RELOC_X86_64_32S
7437 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7438 && GOT_symbol
7439 && GOT_symbol == i.op[n].imms->X_add_symbol
7440 && (i.op[n].imms->X_op == O_symbol
7441 || (i.op[n].imms->X_op == O_add
7442 && ((symbol_get_value_expression
7443 (i.op[n].imms->X_op_symbol)->X_op)
7444 == O_subtract))))
7445 {
2bbd9c25
JJ		 7446 offsetT add;
7447
7448 if (insn_start_frag == frag_now)
7449 add = (p - frag_now->fr_literal) - insn_start_off;
7450 else
7451 {
7452 fragS *fr;
7453
7454 add = insn_start_frag->fr_fix - insn_start_off;
7455 for (fr = insn_start_frag->fr_next;
7456 fr && fr != frag_now; fr = fr->fr_next)
7457 add += fr->fr_fix;
7458 add += p - frag_now->fr_literal;
7459 }
7460
4fa24527 7461 if (!object_64bit)
d6ab8113 7462 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7463 else if (size == 4)
d6ab8113 7464 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7465 else if (size == 8)
7466 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7467 i.op[n].imms->X_add_number += add;
29b0f896 7468 }
29b0f896
AM		 7469 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7470 i.op[n].imms, 0, reloc_type);
7471 }
7472 }
7473 }
252b5132
RH		 7474}
7475\f
d182319b
JB		 7476/* x86_cons_fix_new is called via the expression parsing code when a
7477 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7478static int cons_sign = -1;
7479
7480void
e3bb37b5 7481x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7482 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7483{
d258b828 7484 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7485
7486#ifdef TE_PE
7487 if (exp->X_op == O_secrel)
7488 {
7489 exp->X_op = O_symbol;
7490 r = BFD_RELOC_32_SECREL;
7491 }
7492#endif
7493
7494 fix_new_exp (frag, off, len, exp, 0, r);
7495}
7496
357d1bd8
L		 7497/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7498 purpose of the `.dc.a' internal pseudo-op. */
7499
7500int
7501x86_address_bytes (void)
7502{
7503 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7504 return 4;
7505 return stdoutput->arch_info->bits_per_address / 8;
7506}
7507
d382c579
TG		 7508#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7509 || defined (LEX_AT)
d258b828 7510# define lex_got(reloc, adjust, types) NULL
718ddfc0 7511#else
f3c180ae
AM		 7512/* Parse operands of the form
7513 <symbol>@GOTOFF+<nnn>
7514 and similar .plt or .got references.
7515
7516 If we find one, set up the correct relocation in RELOC and copy the
7517 input string, minus the `@GOTOFF' into a malloc'd buffer for
7518 parsing by the calling routine. Return this buffer, and if ADJUST
7519 is non-null set it to the length of the string we removed from the
7520 input line. Otherwise return NULL. */
7521static char *
91d6fa6a 7522lex_got (enum bfd_reloc_code_real *rel,
64e74474 7523 int *adjust,
d258b828 7524 i386_operand_type *types)
f3c180ae 7525{
7b81dfbb
AJ		 7526 /* Some of the relocations depend on the size of what field is to
7527 be relocated. But in our callers i386_immediate and i386_displacement
7528 we don't yet know the operand size (this will be set by insn
7529 matching). Hence we record the word32 relocation here,
7530 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7531 static const struct {
7532 const char *str;
cff8d58a 7533 int len;
4fa24527 7534 const enum bfd_reloc_code_real rel[2];
40fb9820 7535 const i386_operand_type types64;
f3c180ae 7536 } gotrel[] = {
8ce3d284 7537#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7538 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7539 BFD_RELOC_SIZE32 },
7540 OPERAND_TYPE_IMM32_64 },
8ce3d284 7541#endif
cff8d58a
L		 7542 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7543 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7544 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7545 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7546 BFD_RELOC_X86_64_PLT32 },
40fb9820 7547 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7548 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7549 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7550 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7551 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7552 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7553 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7554 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7555 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7556 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7557 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7558 BFD_RELOC_X86_64_TLSGD },
40fb9820 7559 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7560 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7561 _dummy_first_bfd_reloc_code_real },
40fb9820 7562 OPERAND_TYPE_NONE },
cff8d58a
L		 7563 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7564 BFD_RELOC_X86_64_TLSLD },
40fb9820 7565 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7566 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7567 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7568 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7569 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7570 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7571 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7572 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7573 _dummy_first_bfd_reloc_code_real },
40fb9820 7574 OPERAND_TYPE_NONE },
cff8d58a
L		 7575 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7576 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7577 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7578 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7579 _dummy_first_bfd_reloc_code_real },
40fb9820 7580 OPERAND_TYPE_NONE },
cff8d58a
L		 7581 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7582 _dummy_first_bfd_reloc_code_real },
40fb9820 7583 OPERAND_TYPE_NONE },
cff8d58a
L		 7584 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7585 BFD_RELOC_X86_64_GOT32 },
40fb9820 7586 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7587 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7588 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7589 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7590 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7591 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7592 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7593 };
7594 char *cp;
7595 unsigned int j;
7596
d382c579 7597#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7598 if (!IS_ELF)
7599 return NULL;
d382c579 7600#endif
718ddfc0 7601
f3c180ae 7602 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7603 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7604 return NULL;
7605
47465058 7606 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7607 {
cff8d58a 7608 int len = gotrel[j].len;
28f81592 7609 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7610 {
4fa24527 7611 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7612 {
28f81592
AM		 7613 int first, second;
7614 char *tmpbuf, *past_reloc;
f3c180ae 7615
91d6fa6a 7616 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7617
3956db08
JB		 7618 if (types)
7619 {
7620 if (flag_code != CODE_64BIT)
40fb9820
L		 7621 {
7622 types->bitfield.imm32 = 1;
7623 types->bitfield.disp32 = 1;
7624 }
3956db08
JB		 7625 else
7626 *types = gotrel[j].types64;
7627 }
7628
8fd4256d 7629 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7630 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7631
28f81592 7632 /* The length of the first part of our input line. */
f3c180ae 7633 first = cp - input_line_pointer;
28f81592
AM		 7634
7635 /* The second part goes from after the reloc token until
67c11a9b 7636 (and including) an end_of_line char or comma. */
28f81592 7637 past_reloc = cp + 1 + len;
67c11a9b
AM		 7638 cp = past_reloc;
7639 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7640 ++cp;
7641 second = cp + 1 - past_reloc;
28f81592
AM		 7642
7643 /* Allocate and copy string. The trailing NUL shouldn't
7644 be necessary, but be safe. */
add39d23 7645 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7646 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7647 if (second != 0 && *past_reloc != ' ')
7648 /* Replace the relocation token with ' ', so that
7649 errors like foo@GOTOFF1 will be detected. */
7650 tmpbuf[first++] = ' ';
af89796a
L		 7651 else
7652 /* Increment length by 1 if the relocation token is
7653 removed. */
7654 len++;
7655 if (adjust)
7656 *adjust = len;
0787a12d
AM		 7657 memcpy (tmpbuf + first, past_reloc, second);
7658 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7659 return tmpbuf;
7660 }
7661
4fa24527
JB		 7662 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7663 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7664 return NULL;
7665 }
7666 }
7667
7668 /* Might be a symbol version string. Don't as_bad here. */
7669 return NULL;
7670}
4e4f7c87 7671#endif
f3c180ae 7672
a988325c
NC		 7673#ifdef TE_PE
7674#ifdef lex_got
7675#undef lex_got
7676#endif
7677/* Parse operands of the form
7678 <symbol>@SECREL32+<nnn>
7679
7680 If we find one, set up the correct relocation in RELOC and copy the
7681 input string, minus the `@SECREL32' into a malloc'd buffer for
7682 parsing by the calling routine. Return this buffer, and if ADJUST
7683 is non-null set it to the length of the string we removed from the
34bca508
L		 7684 input line. Otherwise return NULL.
7685
a988325c
NC		 7686 This function is copied from the ELF version above adjusted for PE targets. */
7687
7688static char *
7689lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7690 int *adjust ATTRIBUTE_UNUSED,
d258b828 7691 i386_operand_type *types)
a988325c
NC		 7692{
7693 static const struct
7694 {
7695 const char *str;
7696 int len;
7697 const enum bfd_reloc_code_real rel[2];
7698 const i386_operand_type types64;
7699 }
7700 gotrel[] =
7701 {
7702 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7703 BFD_RELOC_32_SECREL },
7704 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7705 };
7706
7707 char *cp;
7708 unsigned j;
7709
7710 for (cp = input_line_pointer; *cp != '@'; cp++)
7711 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7712 return NULL;
7713
7714 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7715 {
7716 int len = gotrel[j].len;
7717
7718 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7719 {
7720 if (gotrel[j].rel[object_64bit] != 0)
7721 {
7722 int first, second;
7723 char *tmpbuf, *past_reloc;
7724
7725 *rel = gotrel[j].rel[object_64bit];
7726 if (adjust)
7727 *adjust = len;
7728
7729 if (types)
7730 {
7731 if (flag_code != CODE_64BIT)
7732 {
7733 types->bitfield.imm32 = 1;
7734 types->bitfield.disp32 = 1;
7735 }
7736 else
7737 *types = gotrel[j].types64;
7738 }
7739
7740 /* The length of the first part of our input line. */
7741 first = cp - input_line_pointer;
7742
7743 /* The second part goes from after the reloc token until
7744 (and including) an end_of_line char or comma. */
7745 past_reloc = cp + 1 + len;
7746 cp = past_reloc;
7747 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7748 ++cp;
7749 second = cp + 1 - past_reloc;
7750
7751 /* Allocate and copy string. The trailing NUL shouldn't
7752 be necessary, but be safe. */
add39d23 7753 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7754 memcpy (tmpbuf, input_line_pointer, first);
7755 if (second != 0 && *past_reloc != ' ')
7756 /* Replace the relocation token with ' ', so that
7757 errors like foo@SECLREL321 will be detected. */
7758 tmpbuf[first++] = ' ';
7759 memcpy (tmpbuf + first, past_reloc, second);
7760 tmpbuf[first + second] = '\0';
7761 return tmpbuf;
7762 }
7763
7764 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7765 gotrel[j].str, 1 << (5 + object_64bit));
7766 return NULL;
7767 }
7768 }
7769
7770 /* Might be a symbol version string. Don't as_bad here. */
7771 return NULL;
7772}
7773
7774#endif /* TE_PE */
7775
62ebcb5c 7776bfd_reloc_code_real_type
e3bb37b5 7777x86_cons (expressionS *exp, int size)
f3c180ae 7778{
62ebcb5c
AM		 7779 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7780
ee86248c
JB		 7781 intel_syntax = -intel_syntax;
7782
3c7b9c2c 7783 exp->X_md = 0;
4fa24527 7784 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7785 {
7786 /* Handle @GOTOFF and the like in an expression. */
7787 char *save;
7788 char *gotfree_input_line;
4a57f2cf 7789 int adjust = 0;
f3c180ae
AM		 7790
7791 save = input_line_pointer;
d258b828 7792 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7793 if (gotfree_input_line)
7794 input_line_pointer = gotfree_input_line;
7795
7796 expression (exp);
7797
7798 if (gotfree_input_line)
7799 {
7800 /* expression () has merrily parsed up to the end of line,
7801 or a comma - in the wrong buffer. Transfer how far
7802 input_line_pointer has moved to the right buffer. */
7803 input_line_pointer = (save
7804 + (input_line_pointer - gotfree_input_line)
7805 + adjust);
7806 free (gotfree_input_line);
3992d3b7
AM		 7807 if (exp->X_op == O_constant
7808 || exp->X_op == O_absent
7809 || exp->X_op == O_illegal
0398aac5 7810 || exp->X_op == O_register
3992d3b7
AM		 7811 || exp->X_op == O_big)
7812 {
7813 char c = *input_line_pointer;
7814 *input_line_pointer = 0;
7815 as_bad (_("missing or invalid expression `%s'"), save);
7816 *input_line_pointer = c;
7817 }
f3c180ae
AM		 7818 }
7819 }
7820 else
7821 expression (exp);
ee86248c
JB		 7822
7823 intel_syntax = -intel_syntax;
7824
7825 if (intel_syntax)
7826 i386_intel_simplify (exp);
62ebcb5c
AM		 7827
7828 return got_reloc;
f3c180ae 7829}
f3c180ae 7830
9f32dd5b
L		 7831static void
7832signed_cons (int size)
6482c264 7833{
d182319b
JB		 7834 if (flag_code == CODE_64BIT)
7835 cons_sign = 1;
7836 cons (size);
7837 cons_sign = -1;
6482c264
NC		 7838}
7839
d182319b 7840#ifdef TE_PE
6482c264 7841static void
7016a5d5 7842pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7843{
7844 expressionS exp;
7845
7846 do
7847 {
7848 expression (&exp);
7849 if (exp.X_op == O_symbol)
7850 exp.X_op = O_secrel;
7851
7852 emit_expr (&exp, 4);
7853 }
7854 while (*input_line_pointer++ == ',');
7855
7856 input_line_pointer--;
7857 demand_empty_rest_of_line ();
7858}
6482c264
NC		 7859#endif
7860
43234a1e
L		 7861/* Handle Vector operations. */
7862
7863static char *
7864check_VecOperations (char *op_string, char *op_end)
7865{
7866 const reg_entry *mask;
7867 const char *saved;
7868 char *end_op;
7869
7870 while (*op_string
7871 && (op_end == NULL || op_string < op_end))
7872 {
7873 saved = op_string;
7874 if (*op_string == '{')
7875 {
7876 op_string++;
7877
7878 /* Check broadcasts. */
7879 if (strncmp (op_string, "1to", 3) == 0)
7880 {
7881 int bcst_type;
7882
7883 if (i.broadcast)
7884 goto duplicated_vec_op;
7885
7886 op_string += 3;
7887 if (*op_string == '8')
7888 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7889 else if (*op_string == '4')
7890 bcst_type = BROADCAST_1TO4;
7891 else if (*op_string == '2')
7892 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7893 else if (*op_string == '1'
7894 && *(op_string+1) == '6')
7895 {
7896 bcst_type = BROADCAST_1TO16;
7897 op_string++;
7898 }
7899 else
7900 {
7901 as_bad (_("Unsupported broadcast: `%s'"), saved);
7902 return NULL;
7903 }
7904 op_string++;
7905
7906 broadcast_op.type = bcst_type;
7907 broadcast_op.operand = this_operand;
7908 i.broadcast = &broadcast_op;
7909 }
7910 /* Check masking operation. */
7911 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7912 {
7913 /* k0 can't be used for write mask. */
7914 if (mask->reg_num == 0)
7915 {
7916 as_bad (_("`%s' can't be used for write mask"),
7917 op_string);
7918 return NULL;
7919 }
7920
7921 if (!i.mask)
7922 {
7923 mask_op.mask = mask;
7924 mask_op.zeroing = 0;
7925 mask_op.operand = this_operand;
7926 i.mask = &mask_op;
7927 }
7928 else
7929 {
7930 if (i.mask->mask)
7931 goto duplicated_vec_op;
7932
7933 i.mask->mask = mask;
7934
7935 /* Only "{z}" is allowed here. No need to check
7936 zeroing mask explicitly. */
7937 if (i.mask->operand != this_operand)
7938 {
7939 as_bad (_("invalid write mask `%s'"), saved);
7940 return NULL;
7941 }
7942 }
7943
7944 op_string = end_op;
7945 }
7946 /* Check zeroing-flag for masking operation. */
7947 else if (*op_string == 'z')
7948 {
7949 if (!i.mask)
7950 {
7951 mask_op.mask = NULL;
7952 mask_op.zeroing = 1;
7953 mask_op.operand = this_operand;
7954 i.mask = &mask_op;
7955 }
7956 else
7957 {
7958 if (i.mask->zeroing)
7959 {
7960 duplicated_vec_op:
7961 as_bad (_("duplicated `%s'"), saved);
7962 return NULL;
7963 }
7964
7965 i.mask->zeroing = 1;
7966
7967 /* Only "{%k}" is allowed here. No need to check mask
7968 register explicitly. */
7969 if (i.mask->operand != this_operand)
7970 {
7971 as_bad (_("invalid zeroing-masking `%s'"),
7972 saved);
7973 return NULL;
7974 }
7975 }
7976
7977 op_string++;
7978 }
7979 else
7980 goto unknown_vec_op;
7981
7982 if (*op_string != '}')
7983 {
7984 as_bad (_("missing `}' in `%s'"), saved);
7985 return NULL;
7986 }
7987 op_string++;
7988 continue;
7989 }
7990 unknown_vec_op:
7991 /* We don't know this one. */
7992 as_bad (_("unknown vector operation: `%s'"), saved);
7993 return NULL;
7994 }
7995
7996 return op_string;
7997}
7998
252b5132 7999static int
70e41ade 8000i386_immediate (char *imm_start)
252b5132
RH		 8001{
8002 char *save_input_line_pointer;
f3c180ae 8003 char *gotfree_input_line;
252b5132 8004 segT exp_seg = 0;
47926f60 8005 expressionS *exp;
40fb9820
L		 8006 i386_operand_type types;
8007
0dfbf9d7 8008 operand_type_set (&types, ~0);
252b5132
RH		 8009
8010 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8011 {
31b2323c
L		 8012 as_bad (_("at most %d immediate operands are allowed"),
8013 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8014 return 0;
8015 }
8016
8017 exp = &im_expressions[i.imm_operands++];
520dc8e8 8018 i.op[this_operand].imms = exp;
252b5132
RH		 8019
8020 if (is_space_char (*imm_start))
8021 ++imm_start;
8022
8023 save_input_line_pointer = input_line_pointer;
8024 input_line_pointer = imm_start;
8025
d258b828 8026 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8027 if (gotfree_input_line)
8028 input_line_pointer = gotfree_input_line;
252b5132
RH		 8029
8030 exp_seg = expression (exp);
8031
83183c0c 8032 SKIP_WHITESPACE ();
43234a1e
L		 8033
8034 /* Handle vector operations. */
8035 if (*input_line_pointer == '{')
8036 {
8037 input_line_pointer = check_VecOperations (input_line_pointer,
8038 NULL);
8039 if (input_line_pointer == NULL)
8040 return 0;
8041 }
8042
252b5132 8043 if (*input_line_pointer)
f3c180ae 8044 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8045
8046 input_line_pointer = save_input_line_pointer;
f3c180ae 8047 if (gotfree_input_line)
ee86248c
JB		 8048 {
8049 free (gotfree_input_line);
8050
8051 if (exp->X_op == O_constant || exp->X_op == O_register)
8052 exp->X_op = O_illegal;
8053 }
8054
8055 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8056}
252b5132 8057
ee86248c
JB		 8058static int
8059i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8060 i386_operand_type types, const char *imm_start)
8061{
8062 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8063 {
313c53d1
L		 8064 if (imm_start)
8065 as_bad (_("missing or invalid immediate expression `%s'"),
8066 imm_start);
3992d3b7 8067 return 0;
252b5132 8068 }
3e73aa7c 8069 else if (exp->X_op == O_constant)
252b5132 8070 {
47926f60 8071 /* Size it properly later. */
40fb9820 8072 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8073 /* If not 64bit, sign extend val. */
8074 if (flag_code != CODE_64BIT
4eed87de
AM		 8075 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8076 exp->X_add_number
8077 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8078 }
4c63da97 8079#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8080 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8081 && exp_seg != absolute_section
47926f60 8082 && exp_seg != text_section
24eab124
AM		 8083 && exp_seg != data_section
8084 && exp_seg != bss_section
8085 && exp_seg != undefined_section
f86103b7 8086 && !bfd_is_com_section (exp_seg))
252b5132 8087 {
d0b47220 8088 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8089 return 0;
8090 }
8091#endif
a841bdf5 8092 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8093 {
313c53d1
L		 8094 if (imm_start)
8095 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8096 return 0;
8097 }
252b5132
RH		 8098 else
8099 {
8100 /* This is an address. The size of the address will be
24eab124 8101 determined later, depending on destination register,
3e73aa7c 8102 suffix, or the default for the section. */
40fb9820
L		 8103 i.types[this_operand].bitfield.imm8 = 1;
8104 i.types[this_operand].bitfield.imm16 = 1;
8105 i.types[this_operand].bitfield.imm32 = 1;
8106 i.types[this_operand].bitfield.imm32s = 1;
8107 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8108 i.types[this_operand] = operand_type_and (i.types[this_operand],
8109 types);
252b5132
RH		 8110 }
8111
8112 return 1;
8113}
8114
551c1ca1 8115static char *
e3bb37b5 8116i386_scale (char *scale)
252b5132 8117{
551c1ca1
AM		 8118 offsetT val;
8119 char *save = input_line_pointer;
252b5132 8120
551c1ca1
AM		 8121 input_line_pointer = scale;
8122 val = get_absolute_expression ();
8123
8124 switch (val)
252b5132 8125 {
551c1ca1 8126 case 1:
252b5132
RH		 8127 i.log2_scale_factor = 0;
8128 break;
551c1ca1 8129 case 2:
252b5132
RH		 8130 i.log2_scale_factor = 1;
8131 break;
551c1ca1 8132 case 4:
252b5132
RH		 8133 i.log2_scale_factor = 2;
8134 break;
551c1ca1 8135 case 8:
252b5132
RH		 8136 i.log2_scale_factor = 3;
8137 break;
8138 default:
a724f0f4
JB		 8139 {
8140 char sep = *input_line_pointer;
8141
8142 *input_line_pointer = '\0';
8143 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8144 scale);
8145 *input_line_pointer = sep;
8146 input_line_pointer = save;
8147 return NULL;
8148 }
252b5132 8149 }
29b0f896 8150 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8151 {
8152 as_warn (_("scale factor of %d without an index register"),
24eab124 8153 1 << i.log2_scale_factor);
252b5132 8154 i.log2_scale_factor = 0;
252b5132 8155 }
551c1ca1
AM		 8156 scale = input_line_pointer;
8157 input_line_pointer = save;
8158 return scale;
252b5132
RH		 8159}
8160
252b5132 8161static int
e3bb37b5 8162i386_displacement (char *disp_start, char *disp_end)
252b5132 8163{
29b0f896 8164 expressionS *exp;
252b5132
RH		 8165 segT exp_seg = 0;
8166 char *save_input_line_pointer;
f3c180ae 8167 char *gotfree_input_line;
40fb9820
L		 8168 int override;
8169 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8170 int ret;
252b5132 8171
31b2323c
L		 8172 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8173 {
8174 as_bad (_("at most %d displacement operands are allowed"),
8175 MAX_MEMORY_OPERANDS);
8176 return 0;
8177 }
8178
0dfbf9d7 8179 operand_type_set (&bigdisp, 0);
40fb9820
L		 8180 if ((i.types[this_operand].bitfield.jumpabsolute)
8181 || (!current_templates->start->opcode_modifier.jump
8182 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8183 {
40fb9820 8184 bigdisp.bitfield.disp32 = 1;
e05278af 8185 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8186 if (flag_code == CODE_64BIT)
8187 {
8188 if (!override)
8189 {
8190 bigdisp.bitfield.disp32s = 1;
8191 bigdisp.bitfield.disp64 = 1;
8192 }
8193 }
8194 else if ((flag_code == CODE_16BIT) ^ override)
8195 {
8196 bigdisp.bitfield.disp32 = 0;
8197 bigdisp.bitfield.disp16 = 1;
8198 }
e05278af
JB		 8199 }
8200 else
8201 {
8202 /* For PC-relative branches, the width of the displacement
8203 is dependent upon data size, not address size. */
e05278af 8204 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8205 if (flag_code == CODE_64BIT)
8206 {
8207 if (override || i.suffix == WORD_MNEM_SUFFIX)
8208 bigdisp.bitfield.disp16 = 1;
8209 else
8210 {
8211 bigdisp.bitfield.disp32 = 1;
8212 bigdisp.bitfield.disp32s = 1;
8213 }
8214 }
8215 else
e05278af
JB		 8216 {
8217 if (!override)
8218 override = (i.suffix == (flag_code != CODE_16BIT
8219 ? WORD_MNEM_SUFFIX
8220 : LONG_MNEM_SUFFIX));
40fb9820
L		 8221 bigdisp.bitfield.disp32 = 1;
8222 if ((flag_code == CODE_16BIT) ^ override)
8223 {
8224 bigdisp.bitfield.disp32 = 0;
8225 bigdisp.bitfield.disp16 = 1;
8226 }
e05278af 8227 }
e05278af 8228 }
c6fb90c8
L		 8229 i.types[this_operand] = operand_type_or (i.types[this_operand],
8230 bigdisp);
252b5132
RH		 8231
8232 exp = &disp_expressions[i.disp_operands];
520dc8e8 8233 i.op[this_operand].disps = exp;
252b5132
RH		 8234 i.disp_operands++;
8235 save_input_line_pointer = input_line_pointer;
8236 input_line_pointer = disp_start;
8237 END_STRING_AND_SAVE (disp_end);
8238
8239#ifndef GCC_ASM_O_HACK
8240#define GCC_ASM_O_HACK 0
8241#endif
8242#if GCC_ASM_O_HACK
8243 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8244 if (i.types[this_operand].bitfield.baseIndex
24eab124 8245 && displacement_string_end[-1] == '+')
252b5132
RH		 8246 {
8247 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8248 constraint within gcc asm statements.
8249 For instance:
8250
8251 #define _set_tssldt_desc(n,addr,limit,type) \
8252 __asm__ __volatile__ ( \
8253 "movw %w2,%0\n\t" \
8254 "movw %w1,2+%0\n\t" \
8255 "rorl $16,%1\n\t" \
8256 "movb %b1,4+%0\n\t" \
8257 "movb %4,5+%0\n\t" \
8258 "movb $0,6+%0\n\t" \
8259 "movb %h1,7+%0\n\t" \
8260 "rorl $16,%1" \
8261 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8262
8263 This works great except that the output assembler ends
8264 up looking a bit weird if it turns out that there is
8265 no offset. You end up producing code that looks like:
8266
8267 #APP
8268 movw $235,(%eax)
8269 movw %dx,2+(%eax)
8270 rorl $16,%edx
8271 movb %dl,4+(%eax)
8272 movb $137,5+(%eax)
8273 movb $0,6+(%eax)
8274 movb %dh,7+(%eax)
8275 rorl $16,%edx
8276 #NO_APP
8277
47926f60 8278 So here we provide the missing zero. */
24eab124
AM		 8279
8280 *displacement_string_end = '0';
252b5132
RH		 8281 }
8282#endif
d258b828 8283 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8284 if (gotfree_input_line)
8285 input_line_pointer = gotfree_input_line;
252b5132 8286
24eab124 8287 exp_seg = expression (exp);
252b5132 8288
636c26b0
AM		 8289 SKIP_WHITESPACE ();
8290 if (*input_line_pointer)
8291 as_bad (_("junk `%s' after expression"), input_line_pointer);
8292#if GCC_ASM_O_HACK
8293 RESTORE_END_STRING (disp_end + 1);
8294#endif
636c26b0 8295 input_line_pointer = save_input_line_pointer;
636c26b0 8296 if (gotfree_input_line)
ee86248c
JB		 8297 {
8298 free (gotfree_input_line);
8299
8300 if (exp->X_op == O_constant || exp->X_op == O_register)
8301 exp->X_op = O_illegal;
8302 }
8303
8304 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8305
8306 RESTORE_END_STRING (disp_end);
8307
8308 return ret;
8309}
8310
8311static int
8312i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8313 i386_operand_type types, const char *disp_start)
8314{
8315 i386_operand_type bigdisp;
8316 int ret = 1;
636c26b0 8317
24eab124
AM		 8318 /* We do this to make sure that the section symbol is in
8319 the symbol table. We will ultimately change the relocation
47926f60 8320 to be relative to the beginning of the section. */
1ae12ab7 8321 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8322 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8323 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8324 {
636c26b0 8325 if (exp->X_op != O_symbol)
3992d3b7 8326 goto inv_disp;
636c26b0 8327
e5cb08ac 8328 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8329 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8330 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8331 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8332 exp->X_op = O_subtract;
8333 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8334 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8335 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8336 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8337 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8338 else
29b0f896 8339 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8340 }
252b5132 8341
3992d3b7
AM		 8342 else if (exp->X_op == O_absent
8343 || exp->X_op == O_illegal
ee86248c 8344 || exp->X_op == O_big)
2daf4fd8 8345 {
3992d3b7
AM		 8346 inv_disp:
8347 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8348 disp_start);
3992d3b7 8349 ret = 0;
2daf4fd8
AM		 8350 }
8351
0e1147d9
L		 8352 else if (flag_code == CODE_64BIT
8353 && !i.prefix[ADDR_PREFIX]
8354 && exp->X_op == O_constant)
8355 {
8356 /* Since displacement is signed extended to 64bit, don't allow
8357 disp32 and turn off disp32s if they are out of range. */
8358 i.types[this_operand].bitfield.disp32 = 0;
8359 if (!fits_in_signed_long (exp->X_add_number))
8360 {
8361 i.types[this_operand].bitfield.disp32s = 0;
8362 if (i.types[this_operand].bitfield.baseindex)
8363 {
8364 as_bad (_("0x%lx out range of signed 32bit displacement"),
8365 (long) exp->X_add_number);
8366 ret = 0;
8367 }
8368 }
8369 }
8370
4c63da97 8371#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8372 else if (exp->X_op != O_constant
8373 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8374 && exp_seg != absolute_section
8375 && exp_seg != text_section
8376 && exp_seg != data_section
8377 && exp_seg != bss_section
8378 && exp_seg != undefined_section
8379 && !bfd_is_com_section (exp_seg))
24eab124 8380 {
d0b47220 8381 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8382 ret = 0;
24eab124 8383 }
252b5132 8384#endif
3956db08 8385
40fb9820
L		 8386 /* Check if this is a displacement only operand. */
8387 bigdisp = i.types[this_operand];
8388 bigdisp.bitfield.disp8 = 0;
8389 bigdisp.bitfield.disp16 = 0;
8390 bigdisp.bitfield.disp32 = 0;
8391 bigdisp.bitfield.disp32s = 0;
8392 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8393 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8394 i.types[this_operand] = operand_type_and (i.types[this_operand],
8395 types);
3956db08 8396
3992d3b7 8397 return ret;
252b5132
RH		 8398}
8399
eecb386c 8400/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8401 Return 1 on success, 0 on a failure. */
8402
252b5132 8403static int
e3bb37b5 8404i386_index_check (const char *operand_string)
252b5132 8405{
fc0763e6 8406 const char *kind = "base/index";
be05d201
L		 8407 enum flag_code addr_mode;
8408
8409 if (i.prefix[ADDR_PREFIX])
8410 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8411 else
8412 {
8413 addr_mode = flag_code;
8414
24eab124 8415#if INFER_ADDR_PREFIX
be05d201
L		 8416 if (i.mem_operands == 0)
8417 {
8418 /* Infer address prefix from the first memory operand. */
8419 const reg_entry *addr_reg = i.base_reg;
8420
8421 if (addr_reg == NULL)
8422 addr_reg = i.index_reg;
eecb386c 8423
be05d201
L		 8424 if (addr_reg)
8425 {
8426 if (addr_reg->reg_num == RegEip
8427 || addr_reg->reg_num == RegEiz
8428 || addr_reg->reg_type.bitfield.reg32)
8429 addr_mode = CODE_32BIT;
8430 else if (flag_code != CODE_64BIT
8431 && addr_reg->reg_type.bitfield.reg16)
8432 addr_mode = CODE_16BIT;
8433
8434 if (addr_mode != flag_code)
8435 {
8436 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8437 i.prefixes += 1;
8438 /* Change the size of any displacement too. At most one
8439 of Disp16 or Disp32 is set.
8440 FIXME. There doesn't seem to be any real need for
8441 separate Disp16 and Disp32 flags. The same goes for
8442 Imm16 and Imm32. Removing them would probably clean
8443 up the code quite a lot. */
8444 if (flag_code != CODE_64BIT
8445 && (i.types[this_operand].bitfield.disp16
8446 || i.types[this_operand].bitfield.disp32))
8447 i.types[this_operand]
8448 = operand_type_xor (i.types[this_operand], disp16_32);
8449 }
8450 }
8451 }
24eab124 8452#endif
be05d201
L		 8453 }
8454
fc0763e6
JB		 8455 if (current_templates->start->opcode_modifier.isstring
8456 && !current_templates->start->opcode_modifier.immext
8457 && (current_templates->end[-1].opcode_modifier.isstring
8458 || i.mem_operands))
8459 {
8460 /* Memory operands of string insns are special in that they only allow
8461 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8462 const reg_entry *expected_reg;
8463 static const char *di_si[][2] =
8464 {
8465 { "esi", "edi" },
8466 { "si", "di" },
8467 { "rsi", "rdi" }
8468 };
8469 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8470
8471 kind = "string address";
8472
8473 if (current_templates->start->opcode_modifier.w)
8474 {
8475 i386_operand_type type = current_templates->end[-1].operand_types[0];
8476
8477 if (!type.bitfield.baseindex
8478 || ((!i.mem_operands != !intel_syntax)
8479 && current_templates->end[-1].operand_types[1]
8480 .bitfield.baseindex))
8481 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8482 expected_reg = hash_find (reg_hash,
8483 di_si[addr_mode][type.bitfield.esseg]);
8484
fc0763e6
JB		 8485 }
8486 else
be05d201 8487 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8488
be05d201
L		 8489 if (i.base_reg != expected_reg
8490 || i.index_reg
fc0763e6 8491 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8492 {
be05d201
L		 8493 /* The second memory operand must have the same size as
8494 the first one. */
8495 if (i.mem_operands
8496 && i.base_reg
8497 && !((addr_mode == CODE_64BIT
8498 && i.base_reg->reg_type.bitfield.reg64)
8499 || (addr_mode == CODE_32BIT
8500 ? i.base_reg->reg_type.bitfield.reg32
8501 : i.base_reg->reg_type.bitfield.reg16)))
8502 goto bad_address;
8503
fc0763e6
JB		 8504 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8505 operand_string,
8506 intel_syntax ? '[' : '(',
8507 register_prefix,
be05d201 8508 expected_reg->reg_name,
fc0763e6 8509 intel_syntax ? ']' : ')');
be05d201 8510 return 1;
fc0763e6 8511 }
be05d201
L		 8512 else
8513 return 1;
8514
8515bad_address:
8516 as_bad (_("`%s' is not a valid %s expression"),
8517 operand_string, kind);
8518 return 0;
3e73aa7c
JH		 8519 }
8520 else
8521 {
be05d201
L		 8522 if (addr_mode != CODE_16BIT)
8523 {
8524 /* 32-bit/64-bit checks. */
8525 if ((i.base_reg
8526 && (addr_mode == CODE_64BIT
8527 ? !i.base_reg->reg_type.bitfield.reg64
8528 : !i.base_reg->reg_type.bitfield.reg32)
8529 && (i.index_reg
8530 || (i.base_reg->reg_num
8531 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8532 || (i.index_reg
8533 && !i.index_reg->reg_type.bitfield.regxmm
8534 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8535 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8536 && ((addr_mode == CODE_64BIT
8537 ? !(i.index_reg->reg_type.bitfield.reg64
8538 || i.index_reg->reg_num == RegRiz)
8539 : !(i.index_reg->reg_type.bitfield.reg32
8540 || i.index_reg->reg_num == RegEiz))
8541 || !i.index_reg->reg_type.bitfield.baseindex)))
8542 goto bad_address;
8543 }
8544 else
3e73aa7c 8545 {
be05d201 8546 /* 16-bit checks. */
3e73aa7c 8547 if ((i.base_reg
40fb9820
L		 8548 && (!i.base_reg->reg_type.bitfield.reg16
8549 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8550 || (i.index_reg
40fb9820
L		 8551 && (!i.index_reg->reg_type.bitfield.reg16
8552 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8553 || !(i.base_reg
8554 && i.base_reg->reg_num < 6
8555 && i.index_reg->reg_num >= 6
8556 && i.log2_scale_factor == 0))))
be05d201 8557 goto bad_address;
3e73aa7c
JH		 8558 }
8559 }
be05d201 8560 return 1;
24eab124 8561}
252b5132 8562
43234a1e
L		 8563/* Handle vector immediates. */
8564
8565static int
8566RC_SAE_immediate (const char *imm_start)
8567{
8568 unsigned int match_found, j;
8569 const char *pstr = imm_start;
8570 expressionS *exp;
8571
8572 if (*pstr != '{')
8573 return 0;
8574
8575 pstr++;
8576 match_found = 0;
8577 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8578 {
8579 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8580 {
8581 if (!i.rounding)
8582 {
8583 rc_op.type = RC_NamesTable[j].type;
8584 rc_op.operand = this_operand;
8585 i.rounding = &rc_op;
8586 }
8587 else
8588 {
8589 as_bad (_("duplicated `%s'"), imm_start);
8590 return 0;
8591 }
8592 pstr += RC_NamesTable[j].len;
8593 match_found = 1;
8594 break;
8595 }
8596 }
8597 if (!match_found)
8598 return 0;
8599
8600 if (*pstr++ != '}')
8601 {
8602 as_bad (_("Missing '}': '%s'"), imm_start);
8603 return 0;
8604 }
8605 /* RC/SAE immediate string should contain nothing more. */;
8606 if (*pstr != 0)
8607 {
8608 as_bad (_("Junk after '}': '%s'"), imm_start);
8609 return 0;
8610 }
8611
8612 exp = &im_expressions[i.imm_operands++];
8613 i.op[this_operand].imms = exp;
8614
8615 exp->X_op = O_constant;
8616 exp->X_add_number = 0;
8617 exp->X_add_symbol = (symbolS *) 0;
8618 exp->X_op_symbol = (symbolS *) 0;
8619
8620 i.types[this_operand].bitfield.imm8 = 1;
8621 return 1;
8622}
8623
fc0763e6 8624/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8625 on error. */
252b5132 8626
252b5132 8627static int
a7619375 8628i386_att_operand (char *operand_string)
252b5132 8629{
af6bdddf
AM		 8630 const reg_entry *r;
8631 char *end_op;
24eab124 8632 char *op_string = operand_string;
252b5132 8633
24eab124 8634 if (is_space_char (*op_string))
252b5132
RH		 8635 ++op_string;
8636
24eab124 8637 /* We check for an absolute prefix (differentiating,
47926f60 8638 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8639 if (*op_string == ABSOLUTE_PREFIX)
8640 {
8641 ++op_string;
8642 if (is_space_char (*op_string))
8643 ++op_string;
40fb9820 8644 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8645 }
252b5132 8646
47926f60 8647 /* Check if operand is a register. */
4d1bb795 8648 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8649 {
40fb9820
L		 8650 i386_operand_type temp;
8651
24eab124
AM		 8652 /* Check for a segment override by searching for ':' after a
8653 segment register. */
8654 op_string = end_op;
8655 if (is_space_char (*op_string))
8656 ++op_string;
40fb9820
L		 8657 if (*op_string == ':'
8658 && (r->reg_type.bitfield.sreg2
8659 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8660 {
8661 switch (r->reg_num)
8662 {
8663 case 0:
8664 i.seg[i.mem_operands] = &es;
8665 break;
8666 case 1:
8667 i.seg[i.mem_operands] = &cs;
8668 break;
8669 case 2:
8670 i.seg[i.mem_operands] = &ss;
8671 break;
8672 case 3:
8673 i.seg[i.mem_operands] = &ds;
8674 break;
8675 case 4:
8676 i.seg[i.mem_operands] = &fs;
8677 break;
8678 case 5:
8679 i.seg[i.mem_operands] = &gs;
8680 break;
8681 }
252b5132 8682
24eab124 8683 /* Skip the ':' and whitespace. */
252b5132
RH		 8684 ++op_string;
8685 if (is_space_char (*op_string))
24eab124 8686 ++op_string;
252b5132 8687
24eab124
AM		 8688 if (!is_digit_char (*op_string)
8689 && !is_identifier_char (*op_string)
8690 && *op_string != '('
8691 && *op_string != ABSOLUTE_PREFIX)
8692 {
8693 as_bad (_("bad memory operand `%s'"), op_string);
8694 return 0;
8695 }
47926f60 8696 /* Handle case of %es:*foo. */
24eab124
AM		 8697 if (*op_string == ABSOLUTE_PREFIX)
8698 {
8699 ++op_string;
8700 if (is_space_char (*op_string))
8701 ++op_string;
40fb9820 8702 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8703 }
8704 goto do_memory_reference;
8705 }
43234a1e
L		 8706
8707 /* Handle vector operations. */
8708 if (*op_string == '{')
8709 {
8710 op_string = check_VecOperations (op_string, NULL);
8711 if (op_string == NULL)
8712 return 0;
8713 }
8714
24eab124
AM		 8715 if (*op_string)
8716 {
d0b47220 8717 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8718 return 0;
8719 }
40fb9820
L		 8720 temp = r->reg_type;
8721 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8722 i.types[this_operand] = operand_type_or (i.types[this_operand],
8723 temp);
7d5e4556 8724 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8725 i.op[this_operand].regs = r;
24eab124
AM		 8726 i.reg_operands++;
8727 }
af6bdddf
AM		 8728 else if (*op_string == REGISTER_PREFIX)
8729 {
8730 as_bad (_("bad register name `%s'"), op_string);
8731 return 0;
8732 }
24eab124 8733 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8734 {
24eab124 8735 ++op_string;
40fb9820 8736 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8737 {
d0b47220 8738 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8739 return 0;
8740 }
8741 if (!i386_immediate (op_string))
8742 return 0;
8743 }
43234a1e
L		 8744 else if (RC_SAE_immediate (operand_string))
8745 {
8746 /* If it is a RC or SAE immediate, do nothing. */
8747 ;
8748 }
24eab124
AM		 8749 else if (is_digit_char (*op_string)
8750 || is_identifier_char (*op_string)
d02603dc 8751 || *op_string == '"'
e5cb08ac 8752 || *op_string == '(')
24eab124 8753 {
47926f60 8754 /* This is a memory reference of some sort. */
af6bdddf 8755 char *base_string;
252b5132 8756
47926f60 8757 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8758 char *displacement_string_start;
8759 char *displacement_string_end;
43234a1e 8760 char *vop_start;
252b5132 8761
24eab124 8762 do_memory_reference:
24eab124 8763 if ((i.mem_operands == 1
40fb9820 8764 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8765 || i.mem_operands == 2)
8766 {
8767 as_bad (_("too many memory references for `%s'"),
8768 current_templates->start->name);
8769 return 0;
8770 }
252b5132 8771
24eab124
AM		 8772 /* Check for base index form. We detect the base index form by
8773 looking for an ')' at the end of the operand, searching
8774 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8775 after the '('. */
af6bdddf 8776 base_string = op_string + strlen (op_string);
c3332e24 8777
43234a1e
L		 8778 /* Handle vector operations. */
8779 vop_start = strchr (op_string, '{');
8780 if (vop_start && vop_start < base_string)
8781 {
8782 if (check_VecOperations (vop_start, base_string) == NULL)
8783 return 0;
8784 base_string = vop_start;
8785 }
8786
af6bdddf
AM		 8787 --base_string;
8788 if (is_space_char (*base_string))
8789 --base_string;
252b5132 8790
47926f60 8791 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8792 displacement_string_start = op_string;
8793 displacement_string_end = base_string + 1;
252b5132 8794
24eab124
AM		 8795 if (*base_string == ')')
8796 {
af6bdddf 8797 char *temp_string;
24eab124
AM		 8798 unsigned int parens_balanced = 1;
8799 /* We've already checked that the number of left & right ()'s are
47926f60 8800 equal, so this loop will not be infinite. */
24eab124
AM		 8801 do
8802 {
8803 base_string--;
8804 if (*base_string == ')')
8805 parens_balanced++;
8806 if (*base_string == '(')
8807 parens_balanced--;
8808 }
8809 while (parens_balanced);
c3332e24 8810
af6bdddf 8811 temp_string = base_string;
c3332e24 8812
24eab124 8813 /* Skip past '(' and whitespace. */
252b5132
RH		 8814 ++base_string;
8815 if (is_space_char (*base_string))
24eab124 8816 ++base_string;
252b5132 8817
af6bdddf 8818 if (*base_string == ','
4eed87de
AM		 8819 || ((i.base_reg = parse_register (base_string, &end_op))
8820 != NULL))
252b5132 8821 {
af6bdddf 8822 displacement_string_end = temp_string;
252b5132 8823
40fb9820 8824 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8825
af6bdddf 8826 if (i.base_reg)
24eab124 8827 {
24eab124
AM		 8828 base_string = end_op;
8829 if (is_space_char (*base_string))
8830 ++base_string;
af6bdddf
AM		 8831 }
8832
8833 /* There may be an index reg or scale factor here. */
8834 if (*base_string == ',')
8835 {
8836 ++base_string;
8837 if (is_space_char (*base_string))
8838 ++base_string;
8839
4eed87de
AM		 8840 if ((i.index_reg = parse_register (base_string, &end_op))
8841 != NULL)
24eab124 8842 {
af6bdddf 8843 base_string = end_op;
24eab124
AM		 8844 if (is_space_char (*base_string))
8845 ++base_string;
af6bdddf
AM		 8846 if (*base_string == ',')
8847 {
8848 ++base_string;
8849 if (is_space_char (*base_string))
8850 ++base_string;
8851 }
e5cb08ac 8852 else if (*base_string != ')')
af6bdddf 8853 {
4eed87de
AM		 8854 as_bad (_("expecting `,' or `)' "
8855 "after index register in `%s'"),
af6bdddf
AM		 8856 operand_string);
8857 return 0;
8858 }
24eab124 8859 }
af6bdddf 8860 else if (*base_string == REGISTER_PREFIX)
24eab124 8861 {
f76bf5e0
L		 8862 end_op = strchr (base_string, ',');
8863 if (end_op)
8864 *end_op = '\0';
af6bdddf 8865 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8866 return 0;
8867 }
252b5132 8868
47926f60 8869 /* Check for scale factor. */
551c1ca1 8870 if (*base_string != ')')
af6bdddf 8871 {
551c1ca1
AM		 8872 char *end_scale = i386_scale (base_string);
8873
8874 if (!end_scale)
af6bdddf 8875 return 0;
24eab124 8876
551c1ca1 8877 base_string = end_scale;
af6bdddf
AM		 8878 if (is_space_char (*base_string))
8879 ++base_string;
8880 if (*base_string != ')')
8881 {
4eed87de
AM		 8882 as_bad (_("expecting `)' "
8883 "after scale factor in `%s'"),
af6bdddf
AM		 8884 operand_string);
8885 return 0;
8886 }
8887 }
8888 else if (!i.index_reg)
24eab124 8889 {
4eed87de
AM		 8890 as_bad (_("expecting index register or scale factor "
8891 "after `,'; got '%c'"),
af6bdddf 8892 *base_string);
24eab124
AM		 8893 return 0;
8894 }
8895 }
af6bdddf 8896 else if (*base_string != ')')
24eab124 8897 {
4eed87de
AM		 8898 as_bad (_("expecting `,' or `)' "
8899 "after base register in `%s'"),
af6bdddf 8900 operand_string);
24eab124
AM		 8901 return 0;
8902 }
c3332e24 8903 }
af6bdddf 8904 else if (*base_string == REGISTER_PREFIX)
c3332e24 8905 {
f76bf5e0
L		 8906 end_op = strchr (base_string, ',');
8907 if (end_op)
8908 *end_op = '\0';
af6bdddf 8909 as_bad (_("bad register name `%s'"), base_string);
24eab124 8910 return 0;
c3332e24 8911 }
24eab124
AM		 8912 }
8913
8914 /* If there's an expression beginning the operand, parse it,
8915 assuming displacement_string_start and
8916 displacement_string_end are meaningful. */
8917 if (displacement_string_start != displacement_string_end)
8918 {
8919 if (!i386_displacement (displacement_string_start,
8920 displacement_string_end))
8921 return 0;
8922 }
8923
8924 /* Special case for (%dx) while doing input/output op. */
8925 if (i.base_reg
0dfbf9d7
L		 8926 && operand_type_equal (&i.base_reg->reg_type,
8927 &reg16_inoutportreg)
24eab124
AM		 8928 && i.index_reg == 0
8929 && i.log2_scale_factor == 0
8930 && i.seg[i.mem_operands] == 0
40fb9820 8931 && !operand_type_check (i.types[this_operand], disp))
24eab124 8932 {
65da13b5 8933 i.types[this_operand] = inoutportreg;
24eab124
AM		 8934 return 1;
8935 }
8936
eecb386c
AM		 8937 if (i386_index_check (operand_string) == 0)
8938 return 0;
5c07affc 8939 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8940 i.mem_operands++;
8941 }
8942 else
ce8a8b2f
AM		 8943 {
8944 /* It's not a memory operand; argh! */
24eab124
AM		 8945 as_bad (_("invalid char %s beginning operand %d `%s'"),
8946 output_invalid (*op_string),
8947 this_operand + 1,
8948 op_string);
8949 return 0;
8950 }
47926f60 8951 return 1; /* Normal return. */
252b5132
RH		 8952}
8953\f
fa94de6b
RM		 8954/* Calculate the maximum variable size (i.e., excluding fr_fix)
8955 that an rs_machine_dependent frag may reach. */
8956
8957unsigned int
8958i386_frag_max_var (fragS *frag)
8959{
8960 /* The only relaxable frags are for jumps.
8961 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8962 gas_assert (frag->fr_type == rs_machine_dependent);
8963 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8964}
8965
b084df0b
L		 8966#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8967static int
8dcea932 8968elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8969{
8970 /* STT_GNU_IFUNC symbol must go through PLT. */
8971 if ((symbol_get_bfdsym (fr_symbol)->flags
8972 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8973 return 0;
8974
8975 if (!S_IS_EXTERNAL (fr_symbol))
8976 /* Symbol may be weak or local. */
8977 return !S_IS_WEAK (fr_symbol);
8978
8dcea932
L		 8979 /* Global symbols with non-default visibility can't be preempted. */
8980 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8981 return 1;
8982
8983 if (fr_var != NO_RELOC)
8984 switch ((enum bfd_reloc_code_real) fr_var)
8985 {
8986 case BFD_RELOC_386_PLT32:
8987 case BFD_RELOC_X86_64_PLT32:
8988 /* Symbol with PLT relocatin may be preempted. */
8989 return 0;
8990 default:
8991 abort ();
8992 }
8993
b084df0b
L		 8994 /* Global symbols with default visibility in a shared library may be
8995 preempted by another definition. */
8dcea932 8996 return !shared;
b084df0b
L		 8997}
8998#endif
8999
ee7fcc42
AM		 9000/* md_estimate_size_before_relax()
9001
9002 Called just before relax() for rs_machine_dependent frags. The x86
9003 assembler uses these frags to handle variable size jump
9004 instructions.
9005
9006 Any symbol that is now undefined will not become defined.
9007 Return the correct fr_subtype in the frag.
9008 Return the initial "guess for variable size of frag" to caller.
9009 The guess is actually the growth beyond the fixed part. Whatever
9010 we do to grow the fixed or variable part contributes to our
9011 returned value. */
9012
252b5132 9013int
7016a5d5 9014md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9015{
252b5132 9016 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9017 check for un-relaxable symbols. On an ELF system, we can't relax
9018 an externally visible symbol, because it may be overridden by a
9019 shared library. */
9020 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9021#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9022 || (IS_ELF
8dcea932
L		 9023 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9024 fragP->fr_var))
fbeb56a4
DK		 9025#endif
9026#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9027 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9028 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9029#endif
9030 )
252b5132 9031 {
b98ef147
AM		 9032 /* Symbol is undefined in this segment, or we need to keep a
9033 reloc so that weak symbols can be overridden. */
9034 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9035 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9036 unsigned char *opcode;
9037 int old_fr_fix;
f6af82bd 9038
ee7fcc42 9039 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9040 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9041 else if (size == 2)
f6af82bd
AM		 9042 reloc_type = BFD_RELOC_16_PCREL;
9043 else
9044 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9045
ee7fcc42
AM		 9046 old_fr_fix = fragP->fr_fix;
9047 opcode = (unsigned char *) fragP->fr_opcode;
9048
fddf5b5b 9049 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9050 {
fddf5b5b
AM		 9051 case UNCOND_JUMP:
9052 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9053 opcode[0] = 0xe9;
252b5132 9054 fragP->fr_fix += size;
062cd5e7
AS		 9055 fix_new (fragP, old_fr_fix, size,
9056 fragP->fr_symbol,
9057 fragP->fr_offset, 1,
9058 reloc_type);
252b5132
RH		 9059 break;
9060
fddf5b5b 9061 case COND_JUMP86:
412167cb
AM		 9062 if (size == 2
9063 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9064 {
9065 /* Negate the condition, and branch past an
9066 unconditional jump. */
9067 opcode[0] ^= 1;
9068 opcode[1] = 3;
9069 /* Insert an unconditional jump. */
9070 opcode[2] = 0xe9;
9071 /* We added two extra opcode bytes, and have a two byte
9072 offset. */
9073 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9074 fix_new (fragP, old_fr_fix + 2, 2,
9075 fragP->fr_symbol,
9076 fragP->fr_offset, 1,
9077 reloc_type);
fddf5b5b
AM		 9078 break;
9079 }
9080 /* Fall through. */
9081
9082 case COND_JUMP:
412167cb
AM		 9083 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9084 {
3e02c1cc
AM		 9085 fixS *fixP;
9086
412167cb 9087 fragP->fr_fix += 1;
3e02c1cc
AM		 9088 fixP = fix_new (fragP, old_fr_fix, 1,
9089 fragP->fr_symbol,
9090 fragP->fr_offset, 1,
9091 BFD_RELOC_8_PCREL);
9092 fixP->fx_signed = 1;
412167cb
AM		 9093 break;
9094 }
93c2a809 9095
24eab124 9096 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9097 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9098 opcode[1] = opcode[0] + 0x10;
f6af82bd 9099 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9100 /* We've added an opcode byte. */
9101 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9102 fix_new (fragP, old_fr_fix + 1, size,
9103 fragP->fr_symbol,
9104 fragP->fr_offset, 1,
9105 reloc_type);
252b5132 9106 break;
fddf5b5b
AM		 9107
9108 default:
9109 BAD_CASE (fragP->fr_subtype);
9110 break;
252b5132
RH		 9111 }
9112 frag_wane (fragP);
ee7fcc42 9113 return fragP->fr_fix - old_fr_fix;
252b5132 9114 }
93c2a809 9115
93c2a809
AM		 9116 /* Guess size depending on current relax state. Initially the relax
9117 state will correspond to a short jump and we return 1, because
9118 the variable part of the frag (the branch offset) is one byte
9119 long. However, we can relax a section more than once and in that
9120 case we must either set fr_subtype back to the unrelaxed state,
9121 or return the value for the appropriate branch. */
9122 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9123}
9124
47926f60
KH		 9125/* Called after relax() is finished.
9126
9127 In: Address of frag.
9128 fr_type == rs_machine_dependent.
9129 fr_subtype is what the address relaxed to.
9130
9131 Out: Any fixSs and constants are set up.
9132 Caller will turn frag into a ".space 0". */
9133
252b5132 9134void
7016a5d5
TG		 9135md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9136 fragS *fragP)
252b5132 9137{
29b0f896 9138 unsigned char *opcode;
252b5132 9139 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9140 offsetT target_address;
9141 offsetT opcode_address;
252b5132 9142 unsigned int extension = 0;
847f7ad4 9143 offsetT displacement_from_opcode_start;
252b5132
RH		 9144
9145 opcode = (unsigned char *) fragP->fr_opcode;
9146
47926f60 9147 /* Address we want to reach in file space. */
252b5132 9148 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9149
47926f60 9150 /* Address opcode resides at in file space. */
252b5132
RH		 9151 opcode_address = fragP->fr_address + fragP->fr_fix;
9152
47926f60 9153 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9154 displacement_from_opcode_start = target_address - opcode_address;
9155
fddf5b5b 9156 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9157 {
47926f60
KH		 9158 /* Don't have to change opcode. */
9159 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9160 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9161 }
9162 else
9163 {
9164 if (no_cond_jump_promotion
9165 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9166 as_warn_where (fragP->fr_file, fragP->fr_line,
9167 _("long jump required"));
252b5132 9168
fddf5b5b
AM		 9169 switch (fragP->fr_subtype)
9170 {
9171 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9172 extension = 4; /* 1 opcode + 4 displacement */
9173 opcode[0] = 0xe9;
9174 where_to_put_displacement = &opcode[1];
9175 break;
252b5132 9176
fddf5b5b
AM		 9177 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9178 extension = 2; /* 1 opcode + 2 displacement */
9179 opcode[0] = 0xe9;
9180 where_to_put_displacement = &opcode[1];
9181 break;
252b5132 9182
fddf5b5b
AM		 9183 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9184 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9185 extension = 5; /* 2 opcode + 4 displacement */
9186 opcode[1] = opcode[0] + 0x10;
9187 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9188 where_to_put_displacement = &opcode[2];
9189 break;
252b5132 9190
fddf5b5b
AM		 9191 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9192 extension = 3; /* 2 opcode + 2 displacement */
9193 opcode[1] = opcode[0] + 0x10;
9194 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9195 where_to_put_displacement = &opcode[2];
9196 break;
252b5132 9197
fddf5b5b
AM		 9198 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9199 extension = 4;
9200 opcode[0] ^= 1;
9201 opcode[1] = 3;
9202 opcode[2] = 0xe9;
9203 where_to_put_displacement = &opcode[3];
9204 break;
9205
9206 default:
9207 BAD_CASE (fragP->fr_subtype);
9208 break;
9209 }
252b5132 9210 }
fddf5b5b 9211
7b81dfbb
AJ		 9212 /* If size if less then four we are sure that the operand fits,
9213 but if it's 4, then it could be that the displacement is larger
9214 then -/+ 2GB. */
9215 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9216 && object_64bit
9217 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9218 + ((addressT) 1 << 31))
9219 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9220 {
9221 as_bad_where (fragP->fr_file, fragP->fr_line,
9222 _("jump target out of range"));
9223 /* Make us emit 0. */
9224 displacement_from_opcode_start = extension;
9225 }
47926f60 9226 /* Now put displacement after opcode. */
252b5132
RH		 9227 md_number_to_chars ((char *) where_to_put_displacement,
9228 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9229 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9230 fragP->fr_fix += extension;
9231}
9232\f
7016a5d5 9233/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9234 by our caller that we have all the info we need to fix it up.
9235
7016a5d5
TG		 9236 Parameter valP is the pointer to the value of the bits.
9237
252b5132
RH		 9238 On the 386, immediates, displacements, and data pointers are all in
9239 the same (little-endian) format, so we don't need to care about which
9240 we are handling. */
9241
94f592af 9242void
7016a5d5 9243md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9244{
94f592af 9245 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9246 valueT value = *valP;
252b5132 9247
f86103b7 9248#if !defined (TE_Mach)
93382f6d
AM		 9249 if (fixP->fx_pcrel)
9250 {
9251 switch (fixP->fx_r_type)
9252 {
5865bb77
ILT		 9253 default:
9254 break;
9255
d6ab8113
JB		 9256 case BFD_RELOC_64:
9257 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9258 break;
93382f6d 9259 case BFD_RELOC_32:
ae8887b5 9260 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9261 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9262 break;
9263 case BFD_RELOC_16:
9264 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9265 break;
9266 case BFD_RELOC_8:
9267 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9268 break;
9269 }
9270 }
252b5132 9271
a161fe53 9272 if (fixP->fx_addsy != NULL
31312f95 9273 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9274 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9275 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9276 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9277 && !use_rela_relocations)
252b5132 9278 {
31312f95
AM		 9279 /* This is a hack. There should be a better way to handle this.
9280 This covers for the fact that bfd_install_relocation will
9281 subtract the current location (for partial_inplace, PC relative
9282 relocations); see more below. */
252b5132 9283#ifndef OBJ_AOUT
718ddfc0 9284 if (IS_ELF
252b5132
RH		 9285#ifdef TE_PE
9286 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9287#endif
9288 )
9289 value += fixP->fx_where + fixP->fx_frag->fr_address;
9290#endif
9291#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9292 if (IS_ELF)
252b5132 9293 {
6539b54b 9294 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9295
6539b54b 9296 if ((sym_seg == seg
2f66722d 9297 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9298 && sym_seg != absolute_section))
af65af87 9299 && !generic_force_reloc (fixP))
2f66722d
AM		 9300 {
9301 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9302 bfd_install_relocation subtracts them out again. I think
9303 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9304 it. FIXME. */
9305 value += fixP->fx_where + fixP->fx_frag->fr_address;
9306 }
252b5132
RH		 9307 }
9308#endif
9309#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9310 /* For some reason, the PE format does not store a
9311 section address offset for a PC relative symbol. */
9312 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9313 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9314 value += md_pcrel_from (fixP);
9315#endif
9316 }
fbeb56a4 9317#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9318 if (fixP->fx_addsy != NULL
9319 && S_IS_WEAK (fixP->fx_addsy)
9320 /* PR 16858: Do not modify weak function references. */
9321 && ! fixP->fx_pcrel)
fbeb56a4 9322 {
296a8689
NC		 9323#if !defined (TE_PEP)
9324 /* For x86 PE weak function symbols are neither PC-relative
9325 nor do they set S_IS_FUNCTION. So the only reliable way
9326 to detect them is to check the flags of their containing
9327 section. */
9328 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9329 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9330 ;
9331 else
9332#endif
fbeb56a4
DK		 9333 value -= S_GET_VALUE (fixP->fx_addsy);
9334 }
9335#endif
252b5132
RH		 9336
9337 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9338 and we must not disappoint it. */
252b5132 9339#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9340 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9341 switch (fixP->fx_r_type)
9342 {
9343 case BFD_RELOC_386_PLT32:
3e73aa7c 9344 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9345 /* Make the jump instruction point to the address of the operand. At
9346 runtime we merely add the offset to the actual PLT entry. */
9347 value = -4;
9348 break;
31312f95 9349
13ae64f3
JJ		 9350 case BFD_RELOC_386_TLS_GD:
9351 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9352 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9353 case BFD_RELOC_386_TLS_IE:
9354 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9355 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9356 case BFD_RELOC_X86_64_TLSGD:
9357 case BFD_RELOC_X86_64_TLSLD:
9358 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9359 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9360 value = 0; /* Fully resolved at runtime. No addend. */
9361 /* Fallthrough */
9362 case BFD_RELOC_386_TLS_LE:
9363 case BFD_RELOC_386_TLS_LDO_32:
9364 case BFD_RELOC_386_TLS_LE_32:
9365 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9366 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9367 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9368 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9369 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9370 break;
9371
67a4f2b7
AO		 9372 case BFD_RELOC_386_TLS_DESC_CALL:
9373 case BFD_RELOC_X86_64_TLSDESC_CALL:
9374 value = 0; /* Fully resolved at runtime. No addend. */
9375 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9376 fixP->fx_done = 0;
9377 return;
9378
47926f60
KH		 9379 case BFD_RELOC_VTABLE_INHERIT:
9380 case BFD_RELOC_VTABLE_ENTRY:
9381 fixP->fx_done = 0;
94f592af 9382 return;
47926f60
KH		 9383
9384 default:
9385 break;
9386 }
9387#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9388 *valP = value;
f86103b7 9389#endif /* !defined (TE_Mach) */
3e73aa7c 9390
3e73aa7c 9391 /* Are we finished with this relocation now? */
c6682705 9392 if (fixP->fx_addsy == NULL)
3e73aa7c 9393 fixP->fx_done = 1;
fbeb56a4
DK		 9394#if defined (OBJ_COFF) && defined (TE_PE)
9395 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9396 {
9397 fixP->fx_done = 0;
9398 /* Remember value for tc_gen_reloc. */
9399 fixP->fx_addnumber = value;
9400 /* Clear out the frag for now. */
9401 value = 0;
9402 }
9403#endif
3e73aa7c
JH		 9404 else if (use_rela_relocations)
9405 {
9406 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9407 /* Remember value for tc_gen_reloc. */
9408 fixP->fx_addnumber = value;
3e73aa7c
JH		 9409 value = 0;
9410 }
f86103b7 9411
94f592af 9412 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9413}
252b5132 9414\f
6d4af3c2 9415const char *
499ac353 9416md_atof (int type, char *litP, int *sizeP)
252b5132 9417{
499ac353
NC		 9418 /* This outputs the LITTLENUMs in REVERSE order;
9419 in accord with the bigendian 386. */
9420 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9421}
9422\f
2d545b82 9423static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9424
252b5132 9425static char *
e3bb37b5 9426output_invalid (int c)
252b5132 9427{
3882b010 9428 if (ISPRINT (c))
f9f21a03
L		 9429 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9430 "'%c'", c);
252b5132 9431 else
f9f21a03 9432 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9433 "(0x%x)", (unsigned char) c);
252b5132
RH		 9434 return output_invalid_buf;
9435}
9436
af6bdddf 9437/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9438
9439static const reg_entry *
4d1bb795 9440parse_real_register (char *reg_string, char **end_op)
252b5132 9441{
af6bdddf
AM		 9442 char *s = reg_string;
9443 char *p;
252b5132
RH		 9444 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9445 const reg_entry *r;
9446
9447 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9448 if (*s == REGISTER_PREFIX)
9449 ++s;
9450
9451 if (is_space_char (*s))
9452 ++s;
9453
9454 p = reg_name_given;
af6bdddf 9455 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9456 {
9457 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9458 return (const reg_entry *) NULL;
9459 s++;
252b5132
RH		 9460 }
9461
6588847e
DN		 9462 /* For naked regs, make sure that we are not dealing with an identifier.
9463 This prevents confusing an identifier like `eax_var' with register
9464 `eax'. */
9465 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9466 return (const reg_entry *) NULL;
9467
af6bdddf 9468 *end_op = s;
252b5132
RH		 9469
9470 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9471
5f47d35b 9472 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9473 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9474 {
5f47d35b
AM		 9475 if (is_space_char (*s))
9476 ++s;
9477 if (*s == '(')
9478 {
af6bdddf 9479 ++s;
5f47d35b
AM		 9480 if (is_space_char (*s))
9481 ++s;
9482 if (*s >= '0' && *s <= '7')
9483 {
db557034 9484 int fpr = *s - '0';
af6bdddf 9485 ++s;
5f47d35b
AM		 9486 if (is_space_char (*s))
9487 ++s;
9488 if (*s == ')')
9489 {
9490 *end_op = s + 1;
1e9cc1c2 9491 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9492 know (r);
9493 return r + fpr;
5f47d35b 9494 }
5f47d35b 9495 }
47926f60 9496 /* We have "%st(" then garbage. */
5f47d35b
AM		 9497 return (const reg_entry *) NULL;
9498 }
9499 }
9500
a60de03c
JB		 9501 if (r == NULL || allow_pseudo_reg)
9502 return r;
9503
0dfbf9d7 9504 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9505 return (const reg_entry *) NULL;
9506
192dc9c6
JB		 9507 if ((r->reg_type.bitfield.reg32
9508 || r->reg_type.bitfield.sreg3
9509 || r->reg_type.bitfield.control
9510 || r->reg_type.bitfield.debug
9511 || r->reg_type.bitfield.test)
9512 && !cpu_arch_flags.bitfield.cpui386)
9513 return (const reg_entry *) NULL;
9514
309d3373
JB		 9515 if (r->reg_type.bitfield.floatreg
9516 && !cpu_arch_flags.bitfield.cpu8087
9517 && !cpu_arch_flags.bitfield.cpu287
9518 && !cpu_arch_flags.bitfield.cpu387)
9519 return (const reg_entry *) NULL;
9520
192dc9c6
JB		 9521 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9522 return (const reg_entry *) NULL;
9523
9524 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9525 return (const reg_entry *) NULL;
9526
40f12533
L		 9527 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9528 return (const reg_entry *) NULL;
9529
43234a1e
L		 9530 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9531 && !cpu_arch_flags.bitfield.cpuavx512f)
9532 return (const reg_entry *) NULL;
9533
db51cc60 9534 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9535 if (!allow_index_reg
db51cc60
L		 9536 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9537 return (const reg_entry *) NULL;
9538
43234a1e
L		 9539 /* Upper 16 vector register is only available with VREX in 64bit
9540 mode. */
9541 if ((r->reg_flags & RegVRex))
9542 {
9543 if (!cpu_arch_flags.bitfield.cpuvrex
9544 || flag_code != CODE_64BIT)
9545 return (const reg_entry *) NULL;
9546
9547 i.need_vrex = 1;
9548 }
9549
a60de03c
JB		 9550 if (((r->reg_flags & (RegRex64 | RegRex))
9551 || r->reg_type.bitfield.reg64)
40fb9820 9552 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9553 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9554 && flag_code != CODE_64BIT)
20f0a1fc 9555 return (const reg_entry *) NULL;
1ae00879 9556
b7240065
JB		 9557 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9558 return (const reg_entry *) NULL;
9559
252b5132
RH		 9560 return r;
9561}
4d1bb795
JB		 9562
9563/* REG_STRING starts *before* REGISTER_PREFIX. */
9564
9565static const reg_entry *
9566parse_register (char *reg_string, char **end_op)
9567{
9568 const reg_entry *r;
9569
9570 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9571 r = parse_real_register (reg_string, end_op);
9572 else
9573 r = NULL;
9574 if (!r)
9575 {
9576 char *save = input_line_pointer;
9577 char c;
9578 symbolS *symbolP;
9579
9580 input_line_pointer = reg_string;
d02603dc 9581 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9582 symbolP = symbol_find (reg_string);
9583 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9584 {
9585 const expressionS *e = symbol_get_value_expression (symbolP);
9586
0398aac5 9587 know (e->X_op == O_register);
4eed87de 9588 know (e->X_add_number >= 0
c3fe08fa 9589 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9590 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9591 if ((r->reg_flags & RegVRex))
9592 i.need_vrex = 1;
4d1bb795
JB		 9593 *end_op = input_line_pointer;
9594 }
9595 *input_line_pointer = c;
9596 input_line_pointer = save;
9597 }
9598 return r;
9599}
9600
9601int
9602i386_parse_name (char *name, expressionS *e, char *nextcharP)
9603{
9604 const reg_entry *r;
9605 char *end = input_line_pointer;
9606
9607 *end = *nextcharP;
9608 r = parse_register (name, &input_line_pointer);
9609 if (r && end <= input_line_pointer)
9610 {
9611 *nextcharP = *input_line_pointer;
9612 *input_line_pointer = 0;
9613 e->X_op = O_register;
9614 e->X_add_number = r - i386_regtab;
9615 return 1;
9616 }
9617 input_line_pointer = end;
9618 *end = 0;
ee86248c 9619 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9620}
9621
9622void
9623md_operand (expressionS *e)
9624{
ee86248c
JB		 9625 char *end;
9626 const reg_entry *r;
4d1bb795 9627
ee86248c
JB		 9628 switch (*input_line_pointer)
9629 {
9630 case REGISTER_PREFIX:
9631 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9632 if (r)
9633 {
9634 e->X_op = O_register;
9635 e->X_add_number = r - i386_regtab;
9636 input_line_pointer = end;
9637 }
ee86248c
JB		 9638 break;
9639
9640 case '[':
9c2799c2 9641 gas_assert (intel_syntax);
ee86248c
JB		 9642 end = input_line_pointer++;
9643 expression (e);
9644 if (*input_line_pointer == ']')
9645 {
9646 ++input_line_pointer;
9647 e->X_op_symbol = make_expr_symbol (e);
9648 e->X_add_symbol = NULL;
9649 e->X_add_number = 0;
9650 e->X_op = O_index;
9651 }
9652 else
9653 {
9654 e->X_op = O_absent;
9655 input_line_pointer = end;
9656 }
9657 break;
4d1bb795
JB		 9658 }
9659}
9660
252b5132 9661\f
4cc782b5 9662#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9663const char *md_shortopts = "kVQ:sqn";
252b5132 9664#else
12b55ccc 9665const char *md_shortopts = "qn";
252b5132 9666#endif
6e0b89ee 9667
3e73aa7c 9668#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9669#define OPTION_64 (OPTION_MD_BASE + 1)
9670#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9671#define OPTION_MARCH (OPTION_MD_BASE + 3)
9672#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9673#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9674#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9675#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9676#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9677#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9678#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9679#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9680#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9681#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9682#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9683#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9684#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9685#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9686#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9687#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9688#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9689#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9690#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9691#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9692#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9693#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9694
99ad8390
NC		 9695struct option md_longopts[] =
9696{
3e73aa7c 9697 {"32", no_argument, NULL, OPTION_32},
321098a5 9698#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9699 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9700 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9701#endif
9702#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9703 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9704 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9705#endif
b3b91714 9706 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9707 {"march", required_argument, NULL, OPTION_MARCH},
9708 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9709 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9710 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9711 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9712 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9713 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9714 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9715 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9716 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9717 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9718 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9719 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9720 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9721# if defined (TE_PE) || defined (TE_PEP)
9722 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9723#endif
d1982f93 9724 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9725 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9726 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9727 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9728 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9729 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9730 {NULL, no_argument, NULL, 0}
9731};
9732size_t md_longopts_size = sizeof (md_longopts);
9733
9734int
17b9d67d 9735md_parse_option (int c, const char *arg)
252b5132 9736{
91d6fa6a 9737 unsigned int j;
293f5f65 9738 char *arch, *next, *saved;
9103f4f4 9739
252b5132
RH		 9740 switch (c)
9741 {
12b55ccc
L		 9742 case 'n':
9743 optimize_align_code = 0;
9744 break;
9745
a38cf1db
AM		 9746 case 'q':
9747 quiet_warnings = 1;
252b5132
RH		 9748 break;
9749
9750#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9751 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9752 should be emitted or not. FIXME: Not implemented. */
9753 case 'Q':
252b5132
RH		 9754 break;
9755
9756 /* -V: SVR4 argument to print version ID. */
9757 case 'V':
9758 print_version_id ();
9759 break;
9760
a38cf1db
AM		 9761 /* -k: Ignore for FreeBSD compatibility. */
9762 case 'k':
252b5132 9763 break;
4cc782b5
ILT		 9764
9765 case 's':
9766 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9767 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9768 break;
8dcea932
L		 9769
9770 case OPTION_MSHARED:
9771 shared = 1;
9772 break;
99ad8390 9773#endif
321098a5 9774#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9775 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9776 case OPTION_64:
9777 {
9778 const char **list, **l;
9779
3e73aa7c
JH		 9780 list = bfd_target_list ();
9781 for (l = list; *l != NULL; l++)
8620418b 9782 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9783 || strcmp (*l, "coff-x86-64") == 0
9784 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9785 || strcmp (*l, "pei-x86-64") == 0
9786 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9787 {
9788 default_arch = "x86_64";
9789 break;
9790 }
3e73aa7c 9791 if (*l == NULL)
2b5d6a91 9792 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9793 free (list);
9794 }
9795 break;
9796#endif
252b5132 9797
351f65ca 9798#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9799 case OPTION_X32:
351f65ca
L		 9800 if (IS_ELF)
9801 {
9802 const char **list, **l;
9803
9804 list = bfd_target_list ();
9805 for (l = list; *l != NULL; l++)
9806 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9807 {
9808 default_arch = "x86_64:32";
9809 break;
9810 }
9811 if (*l == NULL)
2b5d6a91 9812 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9813 free (list);
9814 }
9815 else
9816 as_fatal (_("32bit x86_64 is only supported for ELF"));
9817 break;
9818#endif
9819
6e0b89ee
AM		 9820 case OPTION_32:
9821 default_arch = "i386";
9822 break;
9823
b3b91714
AM		 9824 case OPTION_DIVIDE:
9825#ifdef SVR4_COMMENT_CHARS
9826 {
9827 char *n, *t;
9828 const char *s;
9829
add39d23 9830 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9831 t = n;
9832 for (s = i386_comment_chars; *s != '\0'; s++)
9833 if (*s != '/')
9834 *t++ = *s;
9835 *t = '\0';
9836 i386_comment_chars = n;
9837 }
9838#endif
9839 break;
9840
9103f4f4 9841 case OPTION_MARCH:
293f5f65
L		 9842 saved = xstrdup (arg);
9843 arch = saved;
9844 /* Allow -march=+nosse. */
9845 if (*arch == '+')
9846 arch++;
6305a203 9847 do
9103f4f4 9848 {
6305a203 9849 if (*arch == '.')
2b5d6a91 9850 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9851 next = strchr (arch, '+');
9852 if (next)
9853 *next++ = '\0';
91d6fa6a 9854 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9855 {
91d6fa6a 9856 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9857 {
6305a203 9858 /* Processor. */
1ded5609
JB		 9859 if (! cpu_arch[j].flags.bitfield.cpui386)
9860 continue;
9861
91d6fa6a 9862 cpu_arch_name = cpu_arch[j].name;
6305a203 9863 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9864 cpu_arch_flags = cpu_arch[j].flags;
9865 cpu_arch_isa = cpu_arch[j].type;
9866 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9867 if (!cpu_arch_tune_set)
9868 {
9869 cpu_arch_tune = cpu_arch_isa;
9870 cpu_arch_tune_flags = cpu_arch_isa_flags;
9871 }
9872 break;
9873 }
91d6fa6a
NC		 9874 else if (*cpu_arch [j].name == '.'
9875 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9876 {
9877 /* ISA entension. */
9878 i386_cpu_flags flags;
309d3373 9879
293f5f65
L		 9880 flags = cpu_flags_or (cpu_arch_flags,
9881 cpu_arch[j].flags);
81486035
L		 9882
9883 if (!valid_iamcu_cpu_flags (&flags))
9884 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9885 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9886 {
9887 if (cpu_sub_arch_name)
9888 {
9889 char *name = cpu_sub_arch_name;
9890 cpu_sub_arch_name = concat (name,
91d6fa6a 9891 cpu_arch[j].name,
1bf57e9f 9892 (const char *) NULL);
6305a203
L		 9893 free (name);
9894 }
9895 else
91d6fa6a 9896 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9897 cpu_arch_flags = flags;
a586129e 9898 cpu_arch_isa_flags = flags;
6305a203
L		 9899 }
9900 break;
ccc9c027 9901 }
9103f4f4 9902 }
6305a203 9903
293f5f65
L		 9904 if (j >= ARRAY_SIZE (cpu_arch))
9905 {
9906 /* Disable an ISA entension. */
9907 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
9908 if (strcmp (arch, cpu_noarch [j].name) == 0)
9909 {
9910 i386_cpu_flags flags;
9911
9912 flags = cpu_flags_and_not (cpu_arch_flags,
9913 cpu_noarch[j].flags);
9914 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9915 {
9916 if (cpu_sub_arch_name)
9917 {
9918 char *name = cpu_sub_arch_name;
9919 cpu_sub_arch_name = concat (arch,
9920 (const char *) NULL);
9921 free (name);
9922 }
9923 else
9924 cpu_sub_arch_name = xstrdup (arch);
9925 cpu_arch_flags = flags;
9926 cpu_arch_isa_flags = flags;
9927 }
9928 break;
9929 }
9930
9931 if (j >= ARRAY_SIZE (cpu_noarch))
9932 j = ARRAY_SIZE (cpu_arch);
9933 }
9934
91d6fa6a 9935 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9936 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9937
9938 arch = next;
9103f4f4 9939 }
293f5f65
L		 9940 while (next != NULL);
9941 free (saved);
9103f4f4
L		 9942 break;
9943
9944 case OPTION_MTUNE:
9945 if (*arg == '.')
2b5d6a91 9946 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9947 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9948 {
91d6fa6a 9949 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9950 {
ccc9c027 9951 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9952 cpu_arch_tune = cpu_arch [j].type;
9953 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9954 break;
9955 }
9956 }
91d6fa6a 9957 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9958 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9959 break;
9960
1efbbeb4
L		 9961 case OPTION_MMNEMONIC:
9962 if (strcasecmp (arg, "att") == 0)
9963 intel_mnemonic = 0;
9964 else if (strcasecmp (arg, "intel") == 0)
9965 intel_mnemonic = 1;
9966 else
2b5d6a91 9967 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9968 break;
9969
9970 case OPTION_MSYNTAX:
9971 if (strcasecmp (arg, "att") == 0)
9972 intel_syntax = 0;
9973 else if (strcasecmp (arg, "intel") == 0)
9974 intel_syntax = 1;
9975 else
2b5d6a91 9976 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9977 break;
9978
9979 case OPTION_MINDEX_REG:
9980 allow_index_reg = 1;
9981 break;
9982
9983 case OPTION_MNAKED_REG:
9984 allow_naked_reg = 1;
9985 break;
9986
9987 case OPTION_MOLD_GCC:
9988 old_gcc = 1;
1efbbeb4
L		 9989 break;
9990
c0f3af97
L		 9991 case OPTION_MSSE2AVX:
9992 sse2avx = 1;
9993 break;
9994
daf50ae7
L		 9995 case OPTION_MSSE_CHECK:
9996 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9997 sse_check = check_error;
daf50ae7 9998 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9999 sse_check = check_warning;
daf50ae7 10000 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10001 sse_check = check_none;
daf50ae7 10002 else
2b5d6a91 10003 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10004 break;
10005
7bab8ab5
JB		 10006 case OPTION_MOPERAND_CHECK:
10007 if (strcasecmp (arg, "error") == 0)
10008 operand_check = check_error;
10009 else if (strcasecmp (arg, "warning") == 0)
10010 operand_check = check_warning;
10011 else if (strcasecmp (arg, "none") == 0)
10012 operand_check = check_none;
10013 else
10014 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10015 break;
10016
539f890d
L		 10017 case OPTION_MAVXSCALAR:
10018 if (strcasecmp (arg, "128") == 0)
10019 avxscalar = vex128;
10020 else if (strcasecmp (arg, "256") == 0)
10021 avxscalar = vex256;
10022 else
2b5d6a91 10023 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10024 break;
10025
7e8b059b
L		 10026 case OPTION_MADD_BND_PREFIX:
10027 add_bnd_prefix = 1;
10028 break;
10029
43234a1e
L		 10030 case OPTION_MEVEXLIG:
10031 if (strcmp (arg, "128") == 0)
10032 evexlig = evexl128;
10033 else if (strcmp (arg, "256") == 0)
10034 evexlig = evexl256;
10035 else if (strcmp (arg, "512") == 0)
10036 evexlig = evexl512;
10037 else
10038 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10039 break;
10040
d3d3c6db
IT		 10041 case OPTION_MEVEXRCIG:
10042 if (strcmp (arg, "rne") == 0)
10043 evexrcig = rne;
10044 else if (strcmp (arg, "rd") == 0)
10045 evexrcig = rd;
10046 else if (strcmp (arg, "ru") == 0)
10047 evexrcig = ru;
10048 else if (strcmp (arg, "rz") == 0)
10049 evexrcig = rz;
10050 else
10051 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10052 break;
10053
43234a1e
L		 10054 case OPTION_MEVEXWIG:
10055 if (strcmp (arg, "0") == 0)
10056 evexwig = evexw0;
10057 else if (strcmp (arg, "1") == 0)
10058 evexwig = evexw1;
10059 else
10060 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10061 break;
10062
167ad85b
TG		 10063# if defined (TE_PE) || defined (TE_PEP)
10064 case OPTION_MBIG_OBJ:
10065 use_big_obj = 1;
10066 break;
10067#endif
10068
d1982f93 10069 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10070 if (strcasecmp (arg, "yes") == 0)
10071 omit_lock_prefix = 1;
10072 else if (strcasecmp (arg, "no") == 0)
10073 omit_lock_prefix = 0;
10074 else
10075 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10076 break;
10077
e4e00185
AS		 10078 case OPTION_MFENCE_AS_LOCK_ADD:
10079 if (strcasecmp (arg, "yes") == 0)
10080 avoid_fence = 1;
10081 else if (strcasecmp (arg, "no") == 0)
10082 avoid_fence = 0;
10083 else
10084 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10085 break;
10086
0cb4071e
L		 10087 case OPTION_MRELAX_RELOCATIONS:
10088 if (strcasecmp (arg, "yes") == 0)
10089 generate_relax_relocations = 1;
10090 else if (strcasecmp (arg, "no") == 0)
10091 generate_relax_relocations = 0;
10092 else
10093 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10094 break;
10095
5db04b09
L		 10096 case OPTION_MAMD64:
10097 cpu_arch_flags.bitfield.cpuamd64 = 1;
10098 cpu_arch_flags.bitfield.cpuintel64 = 0;
10099 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
10100 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
10101 break;
10102
10103 case OPTION_MINTEL64:
10104 cpu_arch_flags.bitfield.cpuamd64 = 0;
10105 cpu_arch_flags.bitfield.cpuintel64 = 1;
10106 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
10107 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
10108 break;
10109
252b5132
RH		 10110 default:
10111 return 0;
10112 }
10113 return 1;
10114}
10115
8a2c8fef
L		 10116#define MESSAGE_TEMPLATE \
10117" "
10118
293f5f65
L		 10119static char *
10120output_message (FILE *stream, char *p, char *message, char *start,
10121 int *left_p, const char *name, int len)
10122{
10123 int size = sizeof (MESSAGE_TEMPLATE);
10124 int left = *left_p;
10125
10126 /* Reserve 2 spaces for ", " or ",\0" */
10127 left -= len + 2;
10128
10129 /* Check if there is any room. */
10130 if (left >= 0)
10131 {
10132 if (p != start)
10133 {
10134 *p++ = ',';
10135 *p++ = ' ';
10136 }
10137 p = mempcpy (p, name, len);
10138 }
10139 else
10140 {
10141 /* Output the current message now and start a new one. */
10142 *p++ = ',';
10143 *p = '\0';
10144 fprintf (stream, "%s\n", message);
10145 p = start;
10146 left = size - (start - message) - len - 2;
10147
10148 gas_assert (left >= 0);
10149
10150 p = mempcpy (p, name, len);
10151 }
10152
10153 *left_p = left;
10154 return p;
10155}
10156
8a2c8fef 10157static void
1ded5609 10158show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10159{
10160 static char message[] = MESSAGE_TEMPLATE;
10161 char *start = message + 27;
10162 char *p;
10163 int size = sizeof (MESSAGE_TEMPLATE);
10164 int left;
10165 const char *name;
10166 int len;
10167 unsigned int j;
10168
10169 p = start;
10170 left = size - (start - message);
10171 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10172 {
10173 /* Should it be skipped? */
10174 if (cpu_arch [j].skip)
10175 continue;
10176
10177 name = cpu_arch [j].name;
10178 len = cpu_arch [j].len;
10179 if (*name == '.')
10180 {
10181 /* It is an extension. Skip if we aren't asked to show it. */
10182 if (ext)
10183 {
10184 name++;
10185 len--;
10186 }
10187 else
10188 continue;
10189 }
10190 else if (ext)
10191 {
10192 /* It is an processor. Skip if we show only extension. */
10193 continue;
10194 }
1ded5609
JB		 10195 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10196 {
10197 /* It is an impossible processor - skip. */
10198 continue;
10199 }
8a2c8fef 10200
293f5f65 10201 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10202 }
10203
293f5f65
L		 10204 /* Display disabled extensions. */
10205 if (ext)
10206 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10207 {
10208 name = cpu_noarch [j].name;
10209 len = cpu_noarch [j].len;
10210 p = output_message (stream, p, message, start, &left, name,
10211 len);
10212 }
10213
8a2c8fef
L		 10214 *p = '\0';
10215 fprintf (stream, "%s\n", message);
10216}
10217
252b5132 10218void
8a2c8fef 10219md_show_usage (FILE *stream)
252b5132 10220{
4cc782b5
ILT		 10221#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10222 fprintf (stream, _("\
a38cf1db
AM		 10223 -Q ignored\n\
10224 -V print assembler version number\n\
b3b91714
AM		 10225 -k ignored\n"));
10226#endif
10227 fprintf (stream, _("\
12b55ccc 10228 -n Do not optimize code alignment\n\
b3b91714
AM		 10229 -q quieten some warnings\n"));
10230#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10231 fprintf (stream, _("\
a38cf1db 10232 -s ignored\n"));
b3b91714 10233#endif
321098a5
L		 10234#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10235 || defined (TE_PE) || defined (TE_PEP))
751d281c 10236 fprintf (stream, _("\
570561f7 10237 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10238#endif
b3b91714
AM		 10239#ifdef SVR4_COMMENT_CHARS
10240 fprintf (stream, _("\
10241 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10242#else
10243 fprintf (stream, _("\
b3b91714 10244 --divide ignored\n"));
4cc782b5 10245#endif
9103f4f4 10246 fprintf (stream, _("\
6305a203 10247 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10248 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10249 show_arch (stream, 0, 1);
8a2c8fef
L		 10250 fprintf (stream, _("\
10251 EXTENSION is combination of:\n"));
1ded5609 10252 show_arch (stream, 1, 0);
6305a203 10253 fprintf (stream, _("\
8a2c8fef 10254 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10255 show_arch (stream, 0, 0);
ba104c83 10256 fprintf (stream, _("\
c0f3af97
L		 10257 -msse2avx encode SSE instructions with VEX prefix\n"));
10258 fprintf (stream, _("\
daf50ae7
L		 10259 -msse-check=[none|error|warning]\n\
10260 check SSE instructions\n"));
10261 fprintf (stream, _("\
7bab8ab5
JB		 10262 -moperand-check=[none|error|warning]\n\
10263 check operand combinations for validity\n"));
10264 fprintf (stream, _("\
539f890d
L		 10265 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10266 length\n"));
10267 fprintf (stream, _("\
43234a1e
L		 10268 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10269 length\n"));
10270 fprintf (stream, _("\
10271 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10272 for EVEX.W bit ignored instructions\n"));
10273 fprintf (stream, _("\
d3d3c6db
IT		 10274 -mevexrcig=[rne|rd|ru|rz]\n\
10275 encode EVEX instructions with specific EVEX.RC value\n\
10276 for SAE-only ignored instructions\n"));
10277 fprintf (stream, _("\
ba104c83
L		 10278 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10279 fprintf (stream, _("\
10280 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10281 fprintf (stream, _("\
10282 -mindex-reg support pseudo index registers\n"));
10283 fprintf (stream, _("\
10284 -mnaked-reg don't require `%%' prefix for registers\n"));
10285 fprintf (stream, _("\
10286 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10287 fprintf (stream, _("\
10288 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10289 fprintf (stream, _("\
10290 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10291# if defined (TE_PE) || defined (TE_PEP)
10292 fprintf (stream, _("\
10293 -mbig-obj generate big object files\n"));
10294#endif
d022bddd
IT		 10295 fprintf (stream, _("\
10296 -momit-lock-prefix=[no|yes]\n\
10297 strip all lock prefixes\n"));
5db04b09 10298 fprintf (stream, _("\
e4e00185
AS		 10299 -mfence-as-lock-add=[no|yes]\n\
10300 encode lfence, mfence and sfence as\n\
10301 lock addl $0x0, (%%{re}sp)\n"));
10302 fprintf (stream, _("\
0cb4071e
L		 10303 -mrelax-relocations=[no|yes]\n\
10304 generate relax relocations\n"));
10305 fprintf (stream, _("\
5db04b09
L		 10306 -mamd64 accept only AMD64 ISA\n"));
10307 fprintf (stream, _("\
10308 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10309}
10310
3e73aa7c 10311#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10312 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10313 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10314
10315/* Pick the target format to use. */
10316
47926f60 10317const char *
e3bb37b5 10318i386_target_format (void)
252b5132 10319{
351f65ca
L		 10320 if (!strncmp (default_arch, "x86_64", 6))
10321 {
10322 update_code_flag (CODE_64BIT, 1);
10323 if (default_arch[6] == '\0')
7f56bc95 10324 x86_elf_abi = X86_64_ABI;
351f65ca 10325 else
7f56bc95 10326 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10327 }
3e73aa7c 10328 else if (!strcmp (default_arch, "i386"))
78f12dd3 10329 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10330 else if (!strcmp (default_arch, "iamcu"))
10331 {
10332 update_code_flag (CODE_32BIT, 1);
10333 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10334 {
10335 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10336 cpu_arch_name = "iamcu";
10337 cpu_sub_arch_name = NULL;
10338 cpu_arch_flags = iamcu_flags;
10339 cpu_arch_isa = PROCESSOR_IAMCU;
10340 cpu_arch_isa_flags = iamcu_flags;
10341 if (!cpu_arch_tune_set)
10342 {
10343 cpu_arch_tune = cpu_arch_isa;
10344 cpu_arch_tune_flags = cpu_arch_isa_flags;
10345 }
10346 }
10347 else
10348 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10349 cpu_arch_name);
10350 }
3e73aa7c 10351 else
2b5d6a91 10352 as_fatal (_("unknown architecture"));
89507696
JB		 10353
10354 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10355 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10356 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10357 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10358
252b5132
RH		 10359 switch (OUTPUT_FLAVOR)
10360 {
9384f2ff 10361#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10362 case bfd_target_aout_flavour:
47926f60 10363 return AOUT_TARGET_FORMAT;
4c63da97 10364#endif
9384f2ff
AM		 10365#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10366# if defined (TE_PE) || defined (TE_PEP)
10367 case bfd_target_coff_flavour:
167ad85b
TG		 10368 if (flag_code == CODE_64BIT)
10369 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10370 else
10371 return "pe-i386";
9384f2ff 10372# elif defined (TE_GO32)
0561d57c
JK		 10373 case bfd_target_coff_flavour:
10374 return "coff-go32";
9384f2ff 10375# else
252b5132
RH		 10376 case bfd_target_coff_flavour:
10377 return "coff-i386";
9384f2ff 10378# endif
4c63da97 10379#endif
3e73aa7c 10380#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10381 case bfd_target_elf_flavour:
3e73aa7c 10382 {
351f65ca
L		 10383 const char *format;
10384
10385 switch (x86_elf_abi)
4fa24527 10386 {
351f65ca
L		 10387 default:
10388 format = ELF_TARGET_FORMAT;
10389 break;
7f56bc95 10390 case X86_64_ABI:
351f65ca 10391 use_rela_relocations = 1;
4fa24527 10392 object_64bit = 1;
351f65ca
L		 10393 format = ELF_TARGET_FORMAT64;
10394 break;
7f56bc95 10395 case X86_64_X32_ABI:
4fa24527 10396 use_rela_relocations = 1;
351f65ca 10397 object_64bit = 1;
862be3fb 10398 disallow_64bit_reloc = 1;
351f65ca
L		 10399 format = ELF_TARGET_FORMAT32;
10400 break;
4fa24527 10401 }
3632d14b 10402 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10403 {
7f56bc95 10404 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10405 as_fatal (_("Intel L1OM is 64bit only"));
10406 return ELF_TARGET_L1OM_FORMAT;
10407 }
b49f93f6 10408 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10409 {
10410 if (x86_elf_abi != X86_64_ABI)
10411 as_fatal (_("Intel K1OM is 64bit only"));
10412 return ELF_TARGET_K1OM_FORMAT;
10413 }
81486035
L		 10414 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10415 {
10416 if (x86_elf_abi != I386_ABI)
10417 as_fatal (_("Intel MCU is 32bit only"));
10418 return ELF_TARGET_IAMCU_FORMAT;
10419 }
8a9036a4 10420 else
351f65ca 10421 return format;
3e73aa7c 10422 }
e57f8c65
TG		 10423#endif
10424#if defined (OBJ_MACH_O)
10425 case bfd_target_mach_o_flavour:
d382c579
TG		 10426 if (flag_code == CODE_64BIT)
10427 {
10428 use_rela_relocations = 1;
10429 object_64bit = 1;
10430 return "mach-o-x86-64";
10431 }
10432 else
10433 return "mach-o-i386";
4c63da97 10434#endif
252b5132
RH		 10435 default:
10436 abort ();
10437 return NULL;
10438 }
10439}
10440
47926f60 10441#endif /* OBJ_MAYBE_ more than one */
252b5132 10442\f
252b5132 10443symbolS *
7016a5d5 10444md_undefined_symbol (char *name)
252b5132 10445{
18dc2407
ILT		 10446 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10447 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10448 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10449 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10450 {
10451 if (!GOT_symbol)
10452 {
10453 if (symbol_find (name))
10454 as_bad (_("GOT already in symbol table"));
10455 GOT_symbol = symbol_new (name, undefined_section,
10456 (valueT) 0, &zero_address_frag);
10457 };
10458 return GOT_symbol;
10459 }
252b5132
RH		 10460 return 0;
10461}
10462
10463/* Round up a section size to the appropriate boundary. */
47926f60 10464
252b5132 10465valueT
7016a5d5 10466md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10467{
4c63da97
AM		 10468#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10469 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10470 {
10471 /* For a.out, force the section size to be aligned. If we don't do
10472 this, BFD will align it for us, but it will not write out the
10473 final bytes of the section. This may be a bug in BFD, but it is
10474 easier to fix it here since that is how the other a.out targets
10475 work. */
10476 int align;
10477
10478 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10479 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10480 }
252b5132
RH		 10481#endif
10482
10483 return size;
10484}
10485
10486/* On the i386, PC-relative offsets are relative to the start of the
10487 next instruction. That is, the address of the offset, plus its
10488 size, since the offset is always the last part of the insn. */
10489
10490long
e3bb37b5 10491md_pcrel_from (fixS *fixP)
252b5132
RH		 10492{
10493 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10494}
10495
10496#ifndef I386COFF
10497
10498static void
e3bb37b5 10499s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10500{
29b0f896 10501 int temp;
252b5132 10502
8a75718c
JB		 10503#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10504 if (IS_ELF)
10505 obj_elf_section_change_hook ();
10506#endif
252b5132
RH		 10507 temp = get_absolute_expression ();
10508 subseg_set (bss_section, (subsegT) temp);
10509 demand_empty_rest_of_line ();
10510}
10511
10512#endif
10513
252b5132 10514void
e3bb37b5 10515i386_validate_fix (fixS *fixp)
252b5132 10516{
02a86693 10517 if (fixp->fx_subsy)
252b5132 10518 {
02a86693 10519 if (fixp->fx_subsy == GOT_symbol)
23df1078 10520 {
02a86693
L		 10521 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10522 {
10523 if (!object_64bit)
10524 abort ();
10525#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10526 if (fixp->fx_tcbit2)
56ceb5b5
L		 10527 fixp->fx_r_type = (fixp->fx_tcbit
10528 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10529 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10530 else
10531#endif
10532 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10533 }
d6ab8113 10534 else
02a86693
L		 10535 {
10536 if (!object_64bit)
10537 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10538 else
10539 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10540 }
10541 fixp->fx_subsy = 0;
23df1078 10542 }
252b5132 10543 }
02a86693
L		 10544#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10545 else if (!object_64bit)
10546 {
10547 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10548 && fixp->fx_tcbit2)
10549 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10550 }
10551#endif
252b5132
RH		 10552}
10553
252b5132 10554arelent *
7016a5d5 10555tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10556{
10557 arelent *rel;
10558 bfd_reloc_code_real_type code;
10559
10560 switch (fixp->fx_r_type)
10561 {
8ce3d284 10562#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10563 case BFD_RELOC_SIZE32:
10564 case BFD_RELOC_SIZE64:
10565 if (S_IS_DEFINED (fixp->fx_addsy)
10566 && !S_IS_EXTERNAL (fixp->fx_addsy))
10567 {
10568 /* Resolve size relocation against local symbol to size of
10569 the symbol plus addend. */
10570 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10571 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10572 && !fits_in_unsigned_long (value))
10573 as_bad_where (fixp->fx_file, fixp->fx_line,
10574 _("symbol size computation overflow"));
10575 fixp->fx_addsy = NULL;
10576 fixp->fx_subsy = NULL;
10577 md_apply_fix (fixp, (valueT *) &value, NULL);
10578 return NULL;
10579 }
8ce3d284 10580#endif
8fd4256d 10581
3e73aa7c
JH		 10582 case BFD_RELOC_X86_64_PLT32:
10583 case BFD_RELOC_X86_64_GOT32:
10584 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10585 case BFD_RELOC_X86_64_GOTPCRELX:
10586 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10587 case BFD_RELOC_386_PLT32:
10588 case BFD_RELOC_386_GOT32:
02a86693 10589 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10590 case BFD_RELOC_386_GOTOFF:
10591 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10592 case BFD_RELOC_386_TLS_GD:
10593 case BFD_RELOC_386_TLS_LDM:
10594 case BFD_RELOC_386_TLS_LDO_32:
10595 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10596 case BFD_RELOC_386_TLS_IE:
10597 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10598 case BFD_RELOC_386_TLS_LE_32:
10599 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10600 case BFD_RELOC_386_TLS_GOTDESC:
10601 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10602 case BFD_RELOC_X86_64_TLSGD:
10603 case BFD_RELOC_X86_64_TLSLD:
10604 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10605 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10606 case BFD_RELOC_X86_64_GOTTPOFF:
10607 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10608 case BFD_RELOC_X86_64_TPOFF64:
10609 case BFD_RELOC_X86_64_GOTOFF64:
10610 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10611 case BFD_RELOC_X86_64_GOT64:
10612 case BFD_RELOC_X86_64_GOTPCREL64:
10613 case BFD_RELOC_X86_64_GOTPC64:
10614 case BFD_RELOC_X86_64_GOTPLT64:
10615 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10616 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10617 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10618 case BFD_RELOC_RVA:
10619 case BFD_RELOC_VTABLE_ENTRY:
10620 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10621#ifdef TE_PE
10622 case BFD_RELOC_32_SECREL:
10623#endif
252b5132
RH		 10624 code = fixp->fx_r_type;
10625 break;
dbbaec26
L		 10626 case BFD_RELOC_X86_64_32S:
10627 if (!fixp->fx_pcrel)
10628 {
10629 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10630 code = fixp->fx_r_type;
10631 break;
10632 }
252b5132 10633 default:
93382f6d 10634 if (fixp->fx_pcrel)
252b5132 10635 {
93382f6d
AM		 10636 switch (fixp->fx_size)
10637 {
10638 default:
b091f402
AM		 10639 as_bad_where (fixp->fx_file, fixp->fx_line,
10640 _("can not do %d byte pc-relative relocation"),
10641 fixp->fx_size);
93382f6d
AM		 10642 code = BFD_RELOC_32_PCREL;
10643 break;
10644 case 1: code = BFD_RELOC_8_PCREL; break;
10645 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10646 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10647#ifdef BFD64
10648 case 8: code = BFD_RELOC_64_PCREL; break;
10649#endif
93382f6d
AM		 10650 }
10651 }
10652 else
10653 {
10654 switch (fixp->fx_size)
10655 {
10656 default:
b091f402
AM		 10657 as_bad_where (fixp->fx_file, fixp->fx_line,
10658 _("can not do %d byte relocation"),
10659 fixp->fx_size);
93382f6d
AM		 10660 code = BFD_RELOC_32;
10661 break;
10662 case 1: code = BFD_RELOC_8; break;
10663 case 2: code = BFD_RELOC_16; break;
10664 case 4: code = BFD_RELOC_32; break;
937149dd 10665#ifdef BFD64
3e73aa7c 10666 case 8: code = BFD_RELOC_64; break;
937149dd 10667#endif
93382f6d 10668 }
252b5132
RH		 10669 }
10670 break;
10671 }
252b5132 10672
d182319b
JB		 10673 if ((code == BFD_RELOC_32
10674 || code == BFD_RELOC_32_PCREL
10675 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10676 && GOT_symbol
10677 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10678 {
4fa24527 10679 if (!object_64bit)
d6ab8113
JB		 10680 code = BFD_RELOC_386_GOTPC;
10681 else
10682 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10683 }
7b81dfbb
AJ		 10684 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10685 && GOT_symbol
10686 && fixp->fx_addsy == GOT_symbol)
10687 {
10688 code = BFD_RELOC_X86_64_GOTPC64;
10689 }
252b5132 10690
add39d23
TS		 10691 rel = XNEW (arelent);
10692 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10693 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10694
10695 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10696
3e73aa7c
JH		 10697 if (!use_rela_relocations)
10698 {
10699 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10700 vtable entry to be used in the relocation's section offset. */
10701 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10702 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10703#if defined (OBJ_COFF) && defined (TE_PE)
10704 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10705 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10706 else
10707#endif
c6682705 10708 rel->addend = 0;
3e73aa7c
JH		 10709 }
10710 /* Use the rela in 64bit mode. */
252b5132 10711 else
3e73aa7c 10712 {
862be3fb
L		 10713 if (disallow_64bit_reloc)
10714 switch (code)
10715 {
862be3fb
L		 10716 case BFD_RELOC_X86_64_DTPOFF64:
10717 case BFD_RELOC_X86_64_TPOFF64:
10718 case BFD_RELOC_64_PCREL:
10719 case BFD_RELOC_X86_64_GOTOFF64:
10720 case BFD_RELOC_X86_64_GOT64:
10721 case BFD_RELOC_X86_64_GOTPCREL64:
10722 case BFD_RELOC_X86_64_GOTPC64:
10723 case BFD_RELOC_X86_64_GOTPLT64:
10724 case BFD_RELOC_X86_64_PLTOFF64:
10725 as_bad_where (fixp->fx_file, fixp->fx_line,
10726 _("cannot represent relocation type %s in x32 mode"),
10727 bfd_get_reloc_code_name (code));
10728 break;
10729 default:
10730 break;
10731 }
10732
062cd5e7
AS		 10733 if (!fixp->fx_pcrel)
10734 rel->addend = fixp->fx_offset;
10735 else
10736 switch (code)
10737 {
10738 case BFD_RELOC_X86_64_PLT32:
10739 case BFD_RELOC_X86_64_GOT32:
10740 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10741 case BFD_RELOC_X86_64_GOTPCRELX:
10742 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10743 case BFD_RELOC_X86_64_TLSGD:
10744 case BFD_RELOC_X86_64_TLSLD:
10745 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10746 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10747 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10748 rel->addend = fixp->fx_offset - fixp->fx_size;
10749 break;
10750 default:
10751 rel->addend = (section->vma
10752 - fixp->fx_size
10753 + fixp->fx_addnumber
10754 + md_pcrel_from (fixp));
10755 break;
10756 }
3e73aa7c
JH		 10757 }
10758
252b5132
RH		 10759 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10760 if (rel->howto == NULL)
10761 {
10762 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10763 _("cannot represent relocation type %s"),
252b5132
RH		 10764 bfd_get_reloc_code_name (code));
10765 /* Set howto to a garbage value so that we can keep going. */
10766 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10767 gas_assert (rel->howto != NULL);
252b5132
RH		 10768 }
10769
10770 return rel;
10771}
10772
ee86248c 10773#include "tc-i386-intel.c"
54cfded0 10774
a60de03c
JB		 10775void
10776tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10777{
a60de03c
JB		 10778 int saved_naked_reg;
10779 char saved_register_dot;
54cfded0 10780
a60de03c
JB		 10781 saved_naked_reg = allow_naked_reg;
10782 allow_naked_reg = 1;
10783 saved_register_dot = register_chars['.'];
10784 register_chars['.'] = '.';
10785 allow_pseudo_reg = 1;
10786 expression_and_evaluate (exp);
10787 allow_pseudo_reg = 0;
10788 register_chars['.'] = saved_register_dot;
10789 allow_naked_reg = saved_naked_reg;
10790
e96d56a1 10791 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10792 {
a60de03c
JB		 10793 if ((addressT) exp->X_add_number < i386_regtab_size)
10794 {
10795 exp->X_op = O_constant;
10796 exp->X_add_number = i386_regtab[exp->X_add_number]
10797 .dw2_regnum[flag_code >> 1];
10798 }
10799 else
10800 exp->X_op = O_illegal;
54cfded0 10801 }
54cfded0
AM		 10802}
10803
10804void
10805tc_x86_frame_initial_instructions (void)
10806{
a60de03c
JB		 10807 static unsigned int sp_regno[2];
10808
10809 if (!sp_regno[flag_code >> 1])
10810 {
10811 char *saved_input = input_line_pointer;
10812 char sp[][4] = {"esp", "rsp"};
10813 expressionS exp;
a4447b93 10814
a60de03c
JB		 10815 input_line_pointer = sp[flag_code >> 1];
10816 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10817 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10818 sp_regno[flag_code >> 1] = exp.X_add_number;
10819 input_line_pointer = saved_input;
10820 }
a4447b93 10821
61ff971f
L		 10822 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10823 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10824}
d2b2c203 10825
d7921315
L		 10826int
10827x86_dwarf2_addr_size (void)
10828{
10829#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10830 if (x86_elf_abi == X86_64_X32_ABI)
10831 return 4;
10832#endif
10833 return bfd_arch_bits_per_address (stdoutput) / 8;
10834}
10835
d2b2c203
DJ		 10836int
10837i386_elf_section_type (const char *str, size_t len)
10838{
10839 if (flag_code == CODE_64BIT
10840 && len == sizeof ("unwind") - 1
10841 && strncmp (str, "unwind", 6) == 0)
10842 return SHT_X86_64_UNWIND;
10843
10844 return -1;
10845}
bb41ade5 10846
ad5fec3b
EB		 10847#ifdef TE_SOLARIS
10848void
10849i386_solaris_fix_up_eh_frame (segT sec)
10850{
10851 if (flag_code == CODE_64BIT)
10852 elf_section_type (sec) = SHT_X86_64_UNWIND;
10853}
10854#endif
10855
bb41ade5
AM		 10856#ifdef TE_PE
10857void
10858tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10859{
91d6fa6a 10860 expressionS exp;
bb41ade5 10861
91d6fa6a
NC		 10862 exp.X_op = O_secrel;
10863 exp.X_add_symbol = symbol;
10864 exp.X_add_number = 0;
10865 emit_expr (&exp, size);
bb41ade5
AM		 10866}
10867#endif
3b22753a
L		 10868
10869#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10870/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10871
01e1a5bc 10872bfd_vma
6d4af3c2 10873x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10874{
10875 if (flag_code == CODE_64BIT)
10876 {
10877 if (letter == 'l')
10878 return SHF_X86_64_LARGE;
10879
8f3bae45 10880 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10881 }
3b22753a 10882 else
8f3bae45 10883 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10884 return -1;
10885}
10886
01e1a5bc 10887bfd_vma
3b22753a
L		 10888x86_64_section_word (char *str, size_t len)
10889{
8620418b 10890 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10891 return SHF_X86_64_LARGE;
10892
10893 return -1;
10894}
10895
10896static void
10897handle_large_common (int small ATTRIBUTE_UNUSED)
10898{
10899 if (flag_code != CODE_64BIT)
10900 {
10901 s_comm_internal (0, elf_common_parse);
10902 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10903 }
10904 else
10905 {
10906 static segT lbss_section;
10907 asection *saved_com_section_ptr = elf_com_section_ptr;
10908 asection *saved_bss_section = bss_section;
10909
10910 if (lbss_section == NULL)
10911 {
10912 flagword applicable;
10913 segT seg = now_seg;
10914 subsegT subseg = now_subseg;
10915
10916 /* The .lbss section is for local .largecomm symbols. */
10917 lbss_section = subseg_new (".lbss", 0);
10918 applicable = bfd_applicable_section_flags (stdoutput);
10919 bfd_set_section_flags (stdoutput, lbss_section,
10920 applicable & SEC_ALLOC);
10921 seg_info (lbss_section)->bss = 1;
10922
10923 subseg_set (seg, subseg);
10924 }
10925
10926 elf_com_section_ptr = &_bfd_elf_large_com_section;
10927 bss_section = lbss_section;
10928
10929 s_comm_internal (0, elf_common_parse);
10930
10931 elf_com_section_ptr = saved_com_section_ptr;
10932 bss_section = saved_bss_section;
10933 }
10934}
10935#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
A mirror of the official binutils-gdb repository