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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
86fa6981
L		 357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
891edac4 364
a501d77e
L		 365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
f8a5c266 372
86fa6981
L		 373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
d5de92cf
L		 382 /* REP prefix. */
383 const char *rep_prefix;
384
165de32a
L		 385 /* HLE prefix. */
386 const char *hle_prefix;
42164a71 387
7e8b059b
L		 388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
04ef582a
L		 391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
891edac4 394 /* Error message. */
a65babc9 395 enum i386_error error;
252b5132
RH		 396 };
397
398typedef struct _i386_insn i386_insn;
399
43234a1e
L		 400/* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402struct RC_name
403{
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407};
408
409static const struct RC_name RC_NamesTable[] =
410{
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416};
417
252b5132
RH		 418/* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 420const char extra_symbol_chars[] = "*%-([{}"
252b5132 421#ifdef LEX_AT
32137342
NC		 422 "@"
423#endif
424#ifdef LEX_QM
425 "?"
252b5132 426#endif
32137342 427 ;
252b5132 428
29b0f896
AM		 429#if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 431 && !defined (TE_GNU) \
29b0f896 432 && !defined (TE_LINUX) \
8d63c93e
RM		 433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
5209009a 563/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 564static int old_gcc = OLDGCC_COMPAT;
565
a60de03c
JB		 566/* 1 if pseudo registers are permitted. */
567static int allow_pseudo_reg = 0;
568
47926f60
KH		 569/* 1 if register prefix % not required. */
570static int allow_naked_reg = 0;
252b5132 571
33eaf5de 572/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 573 instructions supporting it, even if this prefix wasn't specified
574 explicitly. */
575static int add_bnd_prefix = 0;
576
ba104c83 577/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 578static int allow_index_reg = 0;
579
d022bddd
IT		 580/* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582static int omit_lock_prefix = 0;
583
e4e00185
AS		 584/* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586static int avoid_fence = 0;
587
0cb4071e
L		 588/* 1 if the assembler should generate relax relocations. */
589
590static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592
7bab8ab5 593static enum check_kind
daf50ae7 594 {
7bab8ab5
JB		 595 check_none = 0,
596 check_warning,
597 check_error
daf50ae7 598 }
7bab8ab5 599sse_check, operand_check = check_warning;
daf50ae7 600
2ca3ace5
L		 601/* Register prefix used for error message. */
602static const char *register_prefix = "%";
603
47926f60
KH		 604/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607static char stackop_size = '\0';
eecb386c 608
12b55ccc
L		 609/* Non-zero to optimize code alignment. */
610int optimize_align_code = 1;
611
47926f60
KH		 612/* Non-zero to quieten some warnings. */
613static int quiet_warnings = 0;
a38cf1db 614
47926f60
KH		 615/* CPU name. */
616static const char *cpu_arch_name = NULL;
6305a203 617static char *cpu_sub_arch_name = NULL;
a38cf1db 618
47926f60 619/* CPU feature flags. */
40fb9820
L		 620static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621
ccc9c027
L		 622/* If we have selected a cpu we are generating instructions for. */
623static int cpu_arch_tune_set = 0;
624
9103f4f4 625/* Cpu we are generating instructions for. */
fbf3f584 626enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 627
628/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 629static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 630
ccc9c027 631/* CPU instruction set architecture used. */
fbf3f584 632enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 633
9103f4f4 634/* CPU feature flags of instruction set architecture used. */
fbf3f584 635i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 636
fddf5b5b
AM		 637/* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639static unsigned int no_cond_jump_promotion = 0;
640
c0f3af97
L		 641/* Encode SSE instructions with VEX prefix. */
642static unsigned int sse2avx;
643
539f890d
L		 644/* Encode scalar AVX instructions with specific vector length. */
645static enum
646 {
647 vex128 = 0,
648 vex256
649 } avxscalar;
650
43234a1e
L		 651/* Encode scalar EVEX LIG instructions with specific vector length. */
652static enum
653 {
654 evexl128 = 0,
655 evexl256,
656 evexl512
657 } evexlig;
658
659/* Encode EVEX WIG instructions with specific evex.w. */
660static enum
661 {
662 evexw0 = 0,
663 evexw1
664 } evexwig;
665
d3d3c6db
IT		 666/* Value to encode in EVEX RC bits, for SAE-only instructions. */
667static enum rc_type evexrcig = rne;
668
29b0f896 669/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 670static symbolS *GOT_symbol;
29b0f896 671
a4447b93
RH		 672/* The dwarf2 return column, adjusted for 32 or 64 bit. */
673unsigned int x86_dwarf2_return_column;
674
675/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676int x86_cie_data_alignment;
677
252b5132 678/* Interface to relax_segment.
fddf5b5b
AM		 679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
252b5132 682
47926f60 683/* Types. */
93c2a809
AM		 684#define UNCOND_JUMP 0
685#define COND_JUMP 1
686#define COND_JUMP86 2
fddf5b5b 687
47926f60 688/* Sizes. */
252b5132
RH		 689#define CODE16 1
690#define SMALL 0
29b0f896 691#define SMALL16 (SMALL | CODE16)
252b5132 692#define BIG 2
29b0f896 693#define BIG16 (BIG | CODE16)
252b5132
RH		 694
695#ifndef INLINE
696#ifdef __GNUC__
697#define INLINE __inline__
698#else
699#define INLINE
700#endif
701#endif
702
fddf5b5b
AM		 703#define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705#define TYPE_FROM_RELAX_STATE(s) \
706 ((s) >> 2)
707#define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 709
710/* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
717
718const relax_typeS md_relax_table[] =
719{
24eab124
AM		 720 /* The fields are:
721 1) most positive reach of this state,
722 2) most negative reach of this state,
93c2a809 723 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 724 4) which index into the table to try if we can't fit into this one. */
252b5132 725
fddf5b5b 726 /* UNCOND_JUMP states. */
93c2a809
AM		 727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
252b5132 731 {0, 0, 4, 0},
93c2a809
AM		 732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 734 {0, 0, 2, 0},
735
93c2a809
AM		 736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
741 {0, 0, 5, 0},
fddf5b5b 742 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 743 1 extra opcode byte, 2 displacement bytes. */
744 {0, 0, 3, 0},
745
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
751 {0, 0, 5, 0},
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
754 {0, 0, 4, 0}
252b5132
RH		 755};
756
9103f4f4
L		 757static const arch_entry cpu_arch[] =
758{
89507696
JB		 759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
8a2c8fef 761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 762 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 764 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 766 CPU_NONE_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 768 CPU_I186_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 770 CPU_I286_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 772 CPU_I386_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 774 CPU_I486_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 776 CPU_I586_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 778 CPU_I686_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 780 CPU_I586_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 782 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 784 CPU_P2_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 786 CPU_P3_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 788 CPU_P4_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 790 CPU_CORE_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 792 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 794 CPU_CORE_FLAGS, 1 },
8a2c8fef 795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 796 CPU_CORE_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 798 CPU_CORE2_FLAGS, 1 },
8a2c8fef 799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 800 CPU_CORE2_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 802 CPU_COREI7_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 804 CPU_L1OM_FLAGS, 0 },
7a9068fe 805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 806 CPU_K1OM_FLAGS, 0 },
81486035 807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 808 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 810 CPU_K6_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 812 CPU_K6_2_FLAGS, 0 },
8a2c8fef 813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 814 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 816 CPU_K8_FLAGS, 1 },
8a2c8fef 817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 818 CPU_K8_FLAGS, 0 },
8a2c8fef 819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 820 CPU_K8_FLAGS, 0 },
8a2c8fef 821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 822 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 824 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 826 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 828 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 830 CPU_BDVER4_FLAGS, 0 },
029f3522 831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 832 CPU_ZNVER1_FLAGS, 0 },
7b458c12 833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 834 CPU_BTVER1_FLAGS, 0 },
7b458c12 835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 836 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_8087_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_287_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_387_FLAGS, 0 },
1848e567
L		 843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 CPU_687_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_MMX_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_SSE_FLAGS, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_SSE2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_SSE3_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX_FLAGS, 0 },
6c30d220 863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX2_FLAGS, 0 },
43234a1e 865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_AVX512F_FLAGS, 0 },
43234a1e 867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_AVX512CD_FLAGS, 0 },
43234a1e 869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_AVX512ER_FLAGS, 0 },
43234a1e 871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_VMX_FLAGS, 0 },
8729a6f6 881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_SMX_FLAGS, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_AES_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_F16C_FLAGS, 0 },
6c30d220 905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_BMI2_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_FMA_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_FMA4_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_XOP_FLAGS, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_LWP_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_MOVBE_FLAGS, 0 },
60aa667e 917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_CX16_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_EPT_FLAGS, 0 },
6c30d220 921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_LZCNT_FLAGS, 0 },
42164a71 923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_HLE_FLAGS, 0 },
42164a71 925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_RTM_FLAGS, 0 },
6c30d220 927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_CLFLUSH_FLAGS, 0 },
22109423 931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_NOP_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_SVME_FLAGS, 1 },
8a2c8fef 945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_SVME_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_ABM_FLAGS, 0 },
87973e9f 951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_BMI_FLAGS, 0 },
2a2a0f38 953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_TBM_FLAGS, 0 },
e2e1fcde 955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_ADX_FLAGS, 0 },
e2e1fcde 957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_PRFCHW_FLAGS, 0 },
5c111e37 961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SMAP_FLAGS, 0 },
7e8b059b 963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_MPX_FLAGS, 0 },
a0046408 965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_SHA_FLAGS, 0 },
963f3586 967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_SE1_FLAGS, 0 },
c5e7287a 973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
980 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
982 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
984 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
029f3522 985 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 986 CPU_CLZERO_FLAGS, 0 },
9916071f 987 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 988 CPU_MWAITX_FLAGS, 0 },
8eab4136 989 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_OSPKE_FLAGS, 0 },
8bc52696 991 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 993 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
994 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 995 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
996 CPU_CET_FLAGS, 0 },
293f5f65
L		 997};
998
999static const noarch_entry cpu_noarch[] =
1000{
1001 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1002 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1003 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1004 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1005 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1006 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1007 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1008 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1009 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1010 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1011 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1012 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1013 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1014 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1015 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1016 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1017 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1018 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1019 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1020 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1021 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1022 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1023 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1024 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1025 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1026 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
e413e4e9
AM		 1027};
1028
704209c0 1029#ifdef I386COFF
a6c24e68
NC		 1030/* Like s_lcomm_internal in gas/read.c but the alignment string
1031 is allowed to be optional. */
1032
1033static symbolS *
1034pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1035{
1036 addressT align = 0;
1037
1038 SKIP_WHITESPACE ();
1039
7ab9ffdd 1040 if (needs_align
a6c24e68
NC		 1041 && *input_line_pointer == ',')
1042 {
1043 align = parse_align (needs_align - 1);
7ab9ffdd 1044
a6c24e68
NC		 1045 if (align == (addressT) -1)
1046 return NULL;
1047 }
1048 else
1049 {
1050 if (size >= 8)
1051 align = 3;
1052 else if (size >= 4)
1053 align = 2;
1054 else if (size >= 2)
1055 align = 1;
1056 else
1057 align = 0;
1058 }
1059
1060 bss_alloc (symbolP, size, align);
1061 return symbolP;
1062}
1063
704209c0 1064static void
a6c24e68
NC		 1065pe_lcomm (int needs_align)
1066{
1067 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1068}
704209c0 1069#endif
a6c24e68 1070
29b0f896
AM		 1071const pseudo_typeS md_pseudo_table[] =
1072{
1073#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1074 {"align", s_align_bytes, 0},
1075#else
1076 {"align", s_align_ptwo, 0},
1077#endif
1078 {"arch", set_cpu_arch, 0},
1079#ifndef I386COFF
1080 {"bss", s_bss, 0},
a6c24e68
NC		 1081#else
1082 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1083#endif
1084 {"ffloat", float_cons, 'f'},
1085 {"dfloat", float_cons, 'd'},
1086 {"tfloat", float_cons, 'x'},
1087 {"value", cons, 2},
d182319b 1088 {"slong", signed_cons, 4},
29b0f896
AM		 1089 {"noopt", s_ignore, 0},
1090 {"optim", s_ignore, 0},
1091 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1092 {"code16", set_code_flag, CODE_16BIT},
1093 {"code32", set_code_flag, CODE_32BIT},
1094 {"code64", set_code_flag, CODE_64BIT},
1095 {"intel_syntax", set_intel_syntax, 1},
1096 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1097 {"intel_mnemonic", set_intel_mnemonic, 1},
1098 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1099 {"allow_index_reg", set_allow_index_reg, 1},
1100 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1101 {"sse_check", set_check, 0},
1102 {"operand_check", set_check, 1},
3b22753a
L		 1103#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1104 {"largecomm", handle_large_common, 0},
07a53e5c 1105#else
e3bb37b5 1106 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1107 {"loc", dwarf2_directive_loc, 0},
1108 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1109#endif
6482c264
NC		 1110#ifdef TE_PE
1111 {"secrel32", pe_directive_secrel, 0},
1112#endif
29b0f896
AM		 1113 {0, 0, 0}
1114};
1115
1116/* For interface with expression (). */
1117extern char *input_line_pointer;
1118
1119/* Hash table for instruction mnemonic lookup. */
1120static struct hash_control *op_hash;
1121
1122/* Hash table for register lookup. */
1123static struct hash_control *reg_hash;
1124\f
252b5132 1125void
e3bb37b5 1126i386_align_code (fragS *fragP, int count)
252b5132 1127{
ce8a8b2f
AM		 1128 /* Various efficient no-op patterns for aligning code labels.
1129 Note: Don't try to assemble the instructions in the comments.
1130 0L and 0w are not legal. */
bad6e36d 1131 static const unsigned char f32_1[] =
252b5132 1132 {0x90}; /* nop */
bad6e36d 1133 static const unsigned char f32_2[] =
ccc9c027 1134 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1135 static const unsigned char f32_3[] =
252b5132 1136 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1137 static const unsigned char f32_4[] =
252b5132 1138 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1139 static const unsigned char f32_5[] =
252b5132
RH		 1140 {0x90, /* nop */
1141 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1142 static const unsigned char f32_6[] =
252b5132 1143 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1144 static const unsigned char f32_7[] =
252b5132 1145 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1146 static const unsigned char f32_8[] =
252b5132
RH		 1147 {0x90, /* nop */
1148 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1149 static const unsigned char f32_9[] =
252b5132
RH		 1150 {0x89,0xf6, /* movl %esi,%esi */
1151 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1152 static const unsigned char f32_10[] =
252b5132
RH		 1153 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1154 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1155 static const unsigned char f32_11[] =
252b5132
RH		 1156 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1157 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1158 static const unsigned char f32_12[] =
252b5132
RH		 1159 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1160 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1161 static const unsigned char f32_13[] =
252b5132
RH		 1162 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1163 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1164 static const unsigned char f32_14[] =
252b5132
RH		 1165 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1167 static const unsigned char f16_3[] =
c3332e24 1168 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1169 static const unsigned char f16_4[] =
252b5132 1170 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1171 static const unsigned char f16_5[] =
252b5132
RH		 1172 {0x90, /* nop */
1173 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1174 static const unsigned char f16_6[] =
252b5132
RH		 1175 {0x89,0xf6, /* mov %si,%si */
1176 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1177 static const unsigned char f16_7[] =
252b5132
RH		 1178 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1179 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1180 static const unsigned char f16_8[] =
252b5132
RH		 1181 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1182 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1183 static const unsigned char jump_31[] =
76bc74dc
L		 1184 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1185 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1186 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1187 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1188 static const unsigned char *const f32_patt[] = {
252b5132 1189 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1190 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1191 };
bad6e36d 1192 static const unsigned char *const f16_patt[] = {
76bc74dc 1193 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1194 };
ccc9c027 1195 /* nopl (%[re]ax) */
bad6e36d 1196 static const unsigned char alt_3[] =
ccc9c027
L		 1197 {0x0f,0x1f,0x00};
1198 /* nopl 0(%[re]ax) */
bad6e36d 1199 static const unsigned char alt_4[] =
ccc9c027
L		 1200 {0x0f,0x1f,0x40,0x00};
1201 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1202 static const unsigned char alt_5[] =
ccc9c027
L		 1203 {0x0f,0x1f,0x44,0x00,0x00};
1204 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1205 static const unsigned char alt_6[] =
ccc9c027
L		 1206 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1207 /* nopl 0L(%[re]ax) */
bad6e36d 1208 static const unsigned char alt_7[] =
ccc9c027
L		 1209 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1210 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1211 static const unsigned char alt_8[] =
ccc9c027
L		 1212 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1213 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1214 static const unsigned char alt_9[] =
ccc9c027
L		 1215 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1216 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1217 static const unsigned char alt_10[] =
ccc9c027 1218 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1219 static const unsigned char *const alt_patt[] = {
ccc9c027 1220 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1221 alt_9, alt_10
ccc9c027 1222 };
252b5132 1223
76bc74dc
L		 1224 /* Only align for at least a positive non-zero boundary. */
1225 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1226 return;
3e73aa7c 1227
ccc9c027
L		 1228 /* We need to decide which NOP sequence to use for 32bit and
1229 64bit. When -mtune= is used:
4eed87de 1230
76bc74dc
L		 1231 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1232 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1233 2. For the rest, alt_patt will be used.
1234
1235 When -mtune= isn't used, alt_patt will be used if
22109423 1236 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1237 be used.
ccc9c027
L		 1238
1239 When -march= or .arch is used, we can't use anything beyond
1240 cpu_arch_isa_flags. */
1241
1242 if (flag_code == CODE_16BIT)
1243 {
ccc9c027 1244 if (count > 8)
33fef721 1245 {
76bc74dc
L		 1246 memcpy (fragP->fr_literal + fragP->fr_fix,
1247 jump_31, count);
1248 /* Adjust jump offset. */
1249 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1250 }
76bc74dc
L		 1251 else
1252 memcpy (fragP->fr_literal + fragP->fr_fix,
1253 f16_patt[count - 1], count);
252b5132 1254 }
33fef721 1255 else
ccc9c027 1256 {
bad6e36d 1257 const unsigned char *const *patt = NULL;
ccc9c027 1258
fbf3f584 1259 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1260 {
1261 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1262 switch (cpu_arch_tune)
1263 {
1264 case PROCESSOR_UNKNOWN:
1265 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1266 optimize with nops. */
1267 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1268 patt = alt_patt;
ccc9c027
L		 1269 else
1270 patt = f32_patt;
1271 break;
ccc9c027
L		 1272 case PROCESSOR_PENTIUM4:
1273 case PROCESSOR_NOCONA:
ef05d495 1274 case PROCESSOR_CORE:
76bc74dc 1275 case PROCESSOR_CORE2:
bd5295b2 1276 case PROCESSOR_COREI7:
3632d14b 1277 case PROCESSOR_L1OM:
7a9068fe 1278 case PROCESSOR_K1OM:
76bc74dc 1279 case PROCESSOR_GENERIC64:
ccc9c027
L		 1280 case PROCESSOR_K6:
1281 case PROCESSOR_ATHLON:
1282 case PROCESSOR_K8:
4eed87de 1283 case PROCESSOR_AMDFAM10:
8aedb9fe 1284 case PROCESSOR_BD:
029f3522 1285 case PROCESSOR_ZNVER:
7b458c12 1286 case PROCESSOR_BT:
80b8656c 1287 patt = alt_patt;
ccc9c027 1288 break;
76bc74dc 1289 case PROCESSOR_I386:
ccc9c027
L		 1290 case PROCESSOR_I486:
1291 case PROCESSOR_PENTIUM:
2dde1948 1292 case PROCESSOR_PENTIUMPRO:
81486035 1293 case PROCESSOR_IAMCU:
ccc9c027
L		 1294 case PROCESSOR_GENERIC32:
1295 patt = f32_patt;
1296 break;
4eed87de 1297 }
ccc9c027
L		 1298 }
1299 else
1300 {
fbf3f584 1301 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1302 {
1303 case PROCESSOR_UNKNOWN:
e6a14101 1304 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1305 PROCESSOR_UNKNOWN. */
1306 abort ();
1307 break;
1308
76bc74dc 1309 case PROCESSOR_I386:
ccc9c027
L		 1310 case PROCESSOR_I486:
1311 case PROCESSOR_PENTIUM:
81486035 1312 case PROCESSOR_IAMCU:
ccc9c027
L		 1313 case PROCESSOR_K6:
1314 case PROCESSOR_ATHLON:
1315 case PROCESSOR_K8:
4eed87de 1316 case PROCESSOR_AMDFAM10:
8aedb9fe 1317 case PROCESSOR_BD:
029f3522 1318 case PROCESSOR_ZNVER:
7b458c12 1319 case PROCESSOR_BT:
ccc9c027
L		 1320 case PROCESSOR_GENERIC32:
1321 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1322 with nops. */
1323 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1324 patt = alt_patt;
ccc9c027
L		 1325 else
1326 patt = f32_patt;
1327 break;
76bc74dc
L		 1328 case PROCESSOR_PENTIUMPRO:
1329 case PROCESSOR_PENTIUM4:
1330 case PROCESSOR_NOCONA:
1331 case PROCESSOR_CORE:
ef05d495 1332 case PROCESSOR_CORE2:
bd5295b2 1333 case PROCESSOR_COREI7:
3632d14b 1334 case PROCESSOR_L1OM:
7a9068fe 1335 case PROCESSOR_K1OM:
22109423 1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1337 patt = alt_patt;
ccc9c027
L		 1338 else
1339 patt = f32_patt;
1340 break;
1341 case PROCESSOR_GENERIC64:
80b8656c 1342 patt = alt_patt;
ccc9c027 1343 break;
4eed87de 1344 }
ccc9c027
L		 1345 }
1346
76bc74dc
L		 1347 if (patt == f32_patt)
1348 {
1349 /* If the padding is less than 15 bytes, we use the normal
1350 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1351 its offset. */
1352 int limit;
76ba9986 1353
711eedef
L		 1354 /* For 64bit, the limit is 3 bytes. */
1355 if (flag_code == CODE_64BIT
1356 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1357 limit = 3;
1358 else
1359 limit = 15;
1360 if (count < limit)
76bc74dc
L		 1361 memcpy (fragP->fr_literal + fragP->fr_fix,
1362 patt[count - 1], count);
1363 else
1364 {
1365 memcpy (fragP->fr_literal + fragP->fr_fix,
1366 jump_31, count);
1367 /* Adjust jump offset. */
1368 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1369 }
1370 }
1371 else
1372 {
80b8656c
L		 1373 /* Maximum length of an instruction is 10 byte. If the
1374 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1375 we have to break it into smaller pieces. */
1376 int padding = count;
80b8656c 1377 while (padding > 10)
76bc74dc 1378 {
80b8656c 1379 padding -= 10;
76bc74dc 1380 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1381 patt [9], 10);
76bc74dc
L		 1382 }
1383
1384 if (padding)
1385 memcpy (fragP->fr_literal + fragP->fr_fix,
1386 patt [padding - 1], padding);
1387 }
ccc9c027 1388 }
33fef721 1389 fragP->fr_var = count;
252b5132
RH		 1390}
1391
c6fb90c8 1392static INLINE int
0dfbf9d7 1393operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1394{
0dfbf9d7 1395 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1396 {
1397 case 3:
0dfbf9d7 1398 if (x->array[2])
c6fb90c8 1399 return 0;
1a0670f3 1400 /* Fall through. */
c6fb90c8 1401 case 2:
0dfbf9d7 1402 if (x->array[1])
c6fb90c8 1403 return 0;
1a0670f3 1404 /* Fall through. */
c6fb90c8 1405 case 1:
0dfbf9d7 1406 return !x->array[0];
c6fb90c8
L		 1407 default:
1408 abort ();
1409 }
40fb9820
L		 1410}
1411
c6fb90c8 1412static INLINE void
0dfbf9d7 1413operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1414{
0dfbf9d7 1415 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1416 {
1417 case 3:
0dfbf9d7 1418 x->array[2] = v;
1a0670f3 1419 /* Fall through. */
c6fb90c8 1420 case 2:
0dfbf9d7 1421 x->array[1] = v;
1a0670f3 1422 /* Fall through. */
c6fb90c8 1423 case 1:
0dfbf9d7 1424 x->array[0] = v;
1a0670f3 1425 /* Fall through. */
c6fb90c8
L		 1426 break;
1427 default:
1428 abort ();
1429 }
1430}
40fb9820 1431
c6fb90c8 1432static INLINE int
0dfbf9d7
L		 1433operand_type_equal (const union i386_operand_type *x,
1434 const union i386_operand_type *y)
c6fb90c8 1435{
0dfbf9d7 1436 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1437 {
1438 case 3:
0dfbf9d7 1439 if (x->array[2] != y->array[2])
c6fb90c8 1440 return 0;
1a0670f3 1441 /* Fall through. */
c6fb90c8 1442 case 2:
0dfbf9d7 1443 if (x->array[1] != y->array[1])
c6fb90c8 1444 return 0;
1a0670f3 1445 /* Fall through. */
c6fb90c8 1446 case 1:
0dfbf9d7 1447 return x->array[0] == y->array[0];
c6fb90c8
L		 1448 break;
1449 default:
1450 abort ();
1451 }
1452}
40fb9820 1453
0dfbf9d7
L		 1454static INLINE int
1455cpu_flags_all_zero (const union i386_cpu_flags *x)
1456{
1457 switch (ARRAY_SIZE(x->array))
1458 {
1459 case 3:
1460 if (x->array[2])
1461 return 0;
1a0670f3 1462 /* Fall through. */
0dfbf9d7
L		 1463 case 2:
1464 if (x->array[1])
1465 return 0;
1a0670f3 1466 /* Fall through. */
0dfbf9d7
L		 1467 case 1:
1468 return !x->array[0];
1469 default:
1470 abort ();
1471 }
1472}
1473
0dfbf9d7
L		 1474static INLINE int
1475cpu_flags_equal (const union i386_cpu_flags *x,
1476 const union i386_cpu_flags *y)
1477{
1478 switch (ARRAY_SIZE(x->array))
1479 {
1480 case 3:
1481 if (x->array[2] != y->array[2])
1482 return 0;
1a0670f3 1483 /* Fall through. */
0dfbf9d7
L		 1484 case 2:
1485 if (x->array[1] != y->array[1])
1486 return 0;
1a0670f3 1487 /* Fall through. */
0dfbf9d7
L		 1488 case 1:
1489 return x->array[0] == y->array[0];
1490 break;
1491 default:
1492 abort ();
1493 }
1494}
c6fb90c8
L		 1495
1496static INLINE int
1497cpu_flags_check_cpu64 (i386_cpu_flags f)
1498{
1499 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1500 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1501}
1502
c6fb90c8
L		 1503static INLINE i386_cpu_flags
1504cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1505{
c6fb90c8
L		 1506 switch (ARRAY_SIZE (x.array))
1507 {
1508 case 3:
1509 x.array [2] &= y.array [2];
1a0670f3 1510 /* Fall through. */
c6fb90c8
L		 1511 case 2:
1512 x.array [1] &= y.array [1];
1a0670f3 1513 /* Fall through. */
c6fb90c8
L		 1514 case 1:
1515 x.array [0] &= y.array [0];
1516 break;
1517 default:
1518 abort ();
1519 }
1520 return x;
1521}
40fb9820 1522
c6fb90c8
L		 1523static INLINE i386_cpu_flags
1524cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1525{
c6fb90c8 1526 switch (ARRAY_SIZE (x.array))
40fb9820 1527 {
c6fb90c8
L		 1528 case 3:
1529 x.array [2] |= y.array [2];
1a0670f3 1530 /* Fall through. */
c6fb90c8
L		 1531 case 2:
1532 x.array [1] |= y.array [1];
1a0670f3 1533 /* Fall through. */
c6fb90c8
L		 1534 case 1:
1535 x.array [0] |= y.array [0];
40fb9820
L		 1536 break;
1537 default:
1538 abort ();
1539 }
40fb9820
L		 1540 return x;
1541}
1542
309d3373
JB		 1543static INLINE i386_cpu_flags
1544cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1545{
1546 switch (ARRAY_SIZE (x.array))
1547 {
1548 case 3:
1549 x.array [2] &= ~y.array [2];
1a0670f3 1550 /* Fall through. */
309d3373
JB		 1551 case 2:
1552 x.array [1] &= ~y.array [1];
1a0670f3 1553 /* Fall through. */
309d3373
JB		 1554 case 1:
1555 x.array [0] &= ~y.array [0];
1556 break;
1557 default:
1558 abort ();
1559 }
1560 return x;
1561}
1562
c0f3af97
L		 1563#define CPU_FLAGS_ARCH_MATCH 0x1
1564#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1565#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1566#define CPU_FLAGS_PCLMUL_MATCH 0x8
1567#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1568
a5ff0eb2 1569#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1570 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1571 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1572#define CPU_FLAGS_PERFECT_MATCH \
1573 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1574
1575/* Return CPU flags match bits. */
3629bb00 1576
40fb9820 1577static int
d3ce72d0 1578cpu_flags_match (const insn_template *t)
40fb9820 1579{
c0f3af97
L		 1580 i386_cpu_flags x = t->cpu_flags;
1581 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1582
1583 x.bitfield.cpu64 = 0;
1584 x.bitfield.cpuno64 = 0;
1585
0dfbf9d7 1586 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1587 {
1588 /* This instruction is available on all archs. */
1589 match |= CPU_FLAGS_32BIT_MATCH;
1590 }
3629bb00
L		 1591 else
1592 {
c0f3af97 1593 /* This instruction is available only on some archs. */
3629bb00
L		 1594 i386_cpu_flags cpu = cpu_arch_flags;
1595
3629bb00 1596 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1597 if (!cpu_flags_all_zero (&cpu))
1598 {
a5ff0eb2
L		 1599 if (x.bitfield.cpuavx)
1600 {
ce2f5b3c 1601 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1602 if (cpu.bitfield.cpuavx)
1603 {
1604 /* Check SSE2AVX. */
1605 if (!t->opcode_modifier.sse2avx|| sse2avx)
1606 {
1607 match |= (CPU_FLAGS_ARCH_MATCH
1608 | CPU_FLAGS_AVX_MATCH);
1609 /* Check AES. */
1610 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1611 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1612 /* Check PCLMUL. */
1613 if (!x.bitfield.cpupclmul
1614 || cpu.bitfield.cpupclmul)
1615 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1616 }
1617 }
1618 else
1619 match |= CPU_FLAGS_ARCH_MATCH;
1620 }
73b090a9
L		 1621 else if (x.bitfield.cpuavx512vl)
1622 {
1623 /* Match AVX512VL. */
1624 if (cpu.bitfield.cpuavx512vl)
1625 {
1626 /* Need another match. */
1627 cpu.bitfield.cpuavx512vl = 0;
1628 if (!cpu_flags_all_zero (&cpu))
1629 match |= CPU_FLAGS_32BIT_MATCH;
1630 else
1631 match |= CPU_FLAGS_ARCH_MATCH;
1632 }
1633 else
1634 match |= CPU_FLAGS_ARCH_MATCH;
1635 }
a5ff0eb2 1636 else
c0f3af97
L		 1637 match |= CPU_FLAGS_32BIT_MATCH;
1638 }
3629bb00 1639 }
c0f3af97 1640 return match;
40fb9820
L		 1641}
1642
c6fb90c8
L		 1643static INLINE i386_operand_type
1644operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1645{
c6fb90c8
L		 1646 switch (ARRAY_SIZE (x.array))
1647 {
1648 case 3:
1649 x.array [2] &= y.array [2];
1a0670f3 1650 /* Fall through. */
c6fb90c8
L		 1651 case 2:
1652 x.array [1] &= y.array [1];
1a0670f3 1653 /* Fall through. */
c6fb90c8
L		 1654 case 1:
1655 x.array [0] &= y.array [0];
1656 break;
1657 default:
1658 abort ();
1659 }
1660 return x;
40fb9820
L		 1661}
1662
c6fb90c8
L		 1663static INLINE i386_operand_type
1664operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1665{
c6fb90c8 1666 switch (ARRAY_SIZE (x.array))
40fb9820 1667 {
c6fb90c8
L		 1668 case 3:
1669 x.array [2] |= y.array [2];
1a0670f3 1670 /* Fall through. */
c6fb90c8
L		 1671 case 2:
1672 x.array [1] |= y.array [1];
1a0670f3 1673 /* Fall through. */
c6fb90c8
L		 1674 case 1:
1675 x.array [0] |= y.array [0];
40fb9820
L		 1676 break;
1677 default:
1678 abort ();
1679 }
c6fb90c8
L		 1680 return x;
1681}
40fb9820 1682
c6fb90c8
L		 1683static INLINE i386_operand_type
1684operand_type_xor (i386_operand_type x, i386_operand_type y)
1685{
1686 switch (ARRAY_SIZE (x.array))
1687 {
1688 case 3:
1689 x.array [2] ^= y.array [2];
1a0670f3 1690 /* Fall through. */
c6fb90c8
L		 1691 case 2:
1692 x.array [1] ^= y.array [1];
1a0670f3 1693 /* Fall through. */
c6fb90c8
L		 1694 case 1:
1695 x.array [0] ^= y.array [0];
1696 break;
1697 default:
1698 abort ();
1699 }
40fb9820
L		 1700 return x;
1701}
1702
1703static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1704static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1705static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1706static const i386_operand_type inoutportreg
1707 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1708static const i386_operand_type reg16_inoutportreg
1709 = OPERAND_TYPE_REG16_INOUTPORTREG;
1710static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1711static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1712static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1713static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1714static const i386_operand_type anydisp
1715 = OPERAND_TYPE_ANYDISP;
40fb9820 1716static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1717static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1718static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1719static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1720static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1721static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1722static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1723static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1724static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1725static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1726static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1727static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1728static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1729static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1730
1731enum operand_type
1732{
1733 reg,
40fb9820
L		 1734 imm,
1735 disp,
1736 anymem
1737};
1738
c6fb90c8 1739static INLINE int
40fb9820
L		 1740operand_type_check (i386_operand_type t, enum operand_type c)
1741{
1742 switch (c)
1743 {
1744 case reg:
1745 return (t.bitfield.reg8
1746 || t.bitfield.reg16
1747 || t.bitfield.reg32
1748 || t.bitfield.reg64);
1749
40fb9820
L		 1750 case imm:
1751 return (t.bitfield.imm8
1752 || t.bitfield.imm8s
1753 || t.bitfield.imm16
1754 || t.bitfield.imm32
1755 || t.bitfield.imm32s
1756 || t.bitfield.imm64);
1757
1758 case disp:
1759 return (t.bitfield.disp8
1760 || t.bitfield.disp16
1761 || t.bitfield.disp32
1762 || t.bitfield.disp32s
1763 || t.bitfield.disp64);
1764
1765 case anymem:
1766 return (t.bitfield.disp8
1767 || t.bitfield.disp16
1768 || t.bitfield.disp32
1769 || t.bitfield.disp32s
1770 || t.bitfield.disp64
1771 || t.bitfield.baseindex);
1772
1773 default:
1774 abort ();
1775 }
2cfe26b6
AM		 1776
1777 return 0;
40fb9820
L		 1778}
1779
5c07affc
L		 1780/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1781 operand J for instruction template T. */
1782
1783static INLINE int
d3ce72d0 1784match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1785{
1786 return !((i.types[j].bitfield.byte
1787 && !t->operand_types[j].bitfield.byte)
1788 || (i.types[j].bitfield.word
1789 && !t->operand_types[j].bitfield.word)
1790 || (i.types[j].bitfield.dword
1791 && !t->operand_types[j].bitfield.dword)
1792 || (i.types[j].bitfield.qword
1793 && !t->operand_types[j].bitfield.qword));
1794}
1795
1796/* Return 1 if there is no conflict in any size on operand J for
1797 instruction template T. */
1798
1799static INLINE int
d3ce72d0 1800match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1801{
1802 return (match_reg_size (t, j)
1803 && !((i.types[j].bitfield.unspecified
af508cb9 1804 && !i.broadcast
5c07affc
L		 1805 && !t->operand_types[j].bitfield.unspecified)
1806 || (i.types[j].bitfield.fword
1807 && !t->operand_types[j].bitfield.fword)
1808 || (i.types[j].bitfield.tbyte
1809 && !t->operand_types[j].bitfield.tbyte)
1810 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1811 && !t->operand_types[j].bitfield.xmmword)
1812 || (i.types[j].bitfield.ymmword
43234a1e
L		 1813 && !t->operand_types[j].bitfield.ymmword)
1814 || (i.types[j].bitfield.zmmword
1815 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1816}
1817
1818/* Return 1 if there is no size conflict on any operands for
1819 instruction template T. */
1820
1821static INLINE int
d3ce72d0 1822operand_size_match (const insn_template *t)
5c07affc
L		 1823{
1824 unsigned int j;
1825 int match = 1;
1826
1827 /* Don't check jump instructions. */
1828 if (t->opcode_modifier.jump
1829 || t->opcode_modifier.jumpbyte
1830 || t->opcode_modifier.jumpdword
1831 || t->opcode_modifier.jumpintersegment)
1832 return match;
1833
1834 /* Check memory and accumulator operand size. */
1835 for (j = 0; j < i.operands; j++)
1836 {
1837 if (t->operand_types[j].bitfield.anysize)
1838 continue;
1839
1840 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1841 {
1842 match = 0;
1843 break;
1844 }
1845
1846 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1847 {
1848 match = 0;
1849 break;
1850 }
1851 }
1852
891edac4 1853 if (match)
5c07affc 1854 return match;
891edac4
L		 1855 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1856 {
1857mismatch:
86e026a4 1858 i.error = operand_size_mismatch;
891edac4
L		 1859 return 0;
1860 }
5c07affc
L		 1861
1862 /* Check reverse. */
9c2799c2 1863 gas_assert (i.operands == 2);
5c07affc
L		 1864
1865 match = 1;
1866 for (j = 0; j < 2; j++)
1867 {
1868 if (t->operand_types[j].bitfield.acc
1869 && !match_reg_size (t, j ? 0 : 1))
891edac4 1870 goto mismatch;
5c07affc
L		 1871
1872 if (i.types[j].bitfield.mem
1873 && !match_mem_size (t, j ? 0 : 1))
891edac4 1874 goto mismatch;
5c07affc
L		 1875 }
1876
1877 return match;
1878}
1879
c6fb90c8 1880static INLINE int
40fb9820
L		 1881operand_type_match (i386_operand_type overlap,
1882 i386_operand_type given)
1883{
1884 i386_operand_type temp = overlap;
1885
1886 temp.bitfield.jumpabsolute = 0;
7d5e4556 1887 temp.bitfield.unspecified = 0;
5c07affc
L		 1888 temp.bitfield.byte = 0;
1889 temp.bitfield.word = 0;
1890 temp.bitfield.dword = 0;
1891 temp.bitfield.fword = 0;
1892 temp.bitfield.qword = 0;
1893 temp.bitfield.tbyte = 0;
1894 temp.bitfield.xmmword = 0;
c0f3af97 1895 temp.bitfield.ymmword = 0;
43234a1e 1896 temp.bitfield.zmmword = 0;
0dfbf9d7 1897 if (operand_type_all_zero (&temp))
891edac4 1898 goto mismatch;
40fb9820 1899
891edac4
L		 1900 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1901 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1902 return 1;
1903
1904mismatch:
a65babc9 1905 i.error = operand_type_mismatch;
891edac4 1906 return 0;
40fb9820
L		 1907}
1908
7d5e4556 1909/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1910 unless the expected operand type register overlap is null.
1911 Note that Acc in a template matches every size of reg. */
1912
c6fb90c8 1913static INLINE int
40fb9820
L		 1914operand_type_register_match (i386_operand_type m0,
1915 i386_operand_type g0,
1916 i386_operand_type t0,
1917 i386_operand_type m1,
1918 i386_operand_type g1,
1919 i386_operand_type t1)
1920{
1921 if (!operand_type_check (g0, reg))
1922 return 1;
1923
1924 if (!operand_type_check (g1, reg))
1925 return 1;
1926
1927 if (g0.bitfield.reg8 == g1.bitfield.reg8
1928 && g0.bitfield.reg16 == g1.bitfield.reg16
1929 && g0.bitfield.reg32 == g1.bitfield.reg32
1930 && g0.bitfield.reg64 == g1.bitfield.reg64)
1931 return 1;
1932
1933 if (m0.bitfield.acc)
1934 {
1935 t0.bitfield.reg8 = 1;
1936 t0.bitfield.reg16 = 1;
1937 t0.bitfield.reg32 = 1;
1938 t0.bitfield.reg64 = 1;
1939 }
1940
1941 if (m1.bitfield.acc)
1942 {
1943 t1.bitfield.reg8 = 1;
1944 t1.bitfield.reg16 = 1;
1945 t1.bitfield.reg32 = 1;
1946 t1.bitfield.reg64 = 1;
1947 }
1948
891edac4
L		 1949 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1950 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1951 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1952 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1953 return 1;
1954
a65babc9 1955 i.error = register_type_mismatch;
891edac4
L		 1956
1957 return 0;
40fb9820
L		 1958}
1959
4c692bc7
JB		 1960static INLINE unsigned int
1961register_number (const reg_entry *r)
1962{
1963 unsigned int nr = r->reg_num;
1964
1965 if (r->reg_flags & RegRex)
1966 nr += 8;
1967
200cbe0f
L		 1968 if (r->reg_flags & RegVRex)
1969 nr += 16;
1970
4c692bc7
JB		 1971 return nr;
1972}
1973
252b5132 1974static INLINE unsigned int
40fb9820 1975mode_from_disp_size (i386_operand_type t)
252b5132 1976{
43234a1e 1977 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1978 return 1;
1979 else if (t.bitfield.disp16
1980 || t.bitfield.disp32
1981 || t.bitfield.disp32s)
1982 return 2;
1983 else
1984 return 0;
252b5132
RH		 1985}
1986
1987static INLINE int
65879393 1988fits_in_signed_byte (addressT num)
252b5132 1989{
65879393 1990 return num + 0x80 <= 0xff;
47926f60 1991}
252b5132
RH		 1992
1993static INLINE int
65879393 1994fits_in_unsigned_byte (addressT num)
252b5132 1995{
65879393 1996 return num <= 0xff;
47926f60 1997}
252b5132
RH		 1998
1999static INLINE int
65879393 2000fits_in_unsigned_word (addressT num)
252b5132 2001{
65879393 2002 return num <= 0xffff;
47926f60 2003}
252b5132
RH		 2004
2005static INLINE int
65879393 2006fits_in_signed_word (addressT num)
252b5132 2007{
65879393 2008 return num + 0x8000 <= 0xffff;
47926f60 2009}
2a962e6d 2010
3e73aa7c 2011static INLINE int
65879393 2012fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2013{
2014#ifndef BFD64
2015 return 1;
2016#else
65879393 2017 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2018#endif
2019} /* fits_in_signed_long() */
2a962e6d 2020
3e73aa7c 2021static INLINE int
65879393 2022fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2023{
2024#ifndef BFD64
2025 return 1;
2026#else
65879393 2027 return num <= 0xffffffff;
3e73aa7c
JH		 2028#endif
2029} /* fits_in_unsigned_long() */
252b5132 2030
43234a1e
L		 2031static INLINE int
2032fits_in_vec_disp8 (offsetT num)
2033{
2034 int shift = i.memshift;
2035 unsigned int mask;
2036
2037 if (shift == -1)
2038 abort ();
2039
2040 mask = (1 << shift) - 1;
2041
2042 /* Return 0 if NUM isn't properly aligned. */
2043 if ((num & mask))
2044 return 0;
2045
2046 /* Check if NUM will fit in 8bit after shift. */
2047 return fits_in_signed_byte (num >> shift);
2048}
2049
a683cc34
SP		 2050static INLINE int
2051fits_in_imm4 (offsetT num)
2052{
2053 return (num & 0xf) == num;
2054}
2055
40fb9820 2056static i386_operand_type
e3bb37b5 2057smallest_imm_type (offsetT num)
252b5132 2058{
40fb9820 2059 i386_operand_type t;
7ab9ffdd 2060
0dfbf9d7 2061 operand_type_set (&t, 0);
40fb9820
L		 2062 t.bitfield.imm64 = 1;
2063
2064 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2065 {
2066 /* This code is disabled on the 486 because all the Imm1 forms
2067 in the opcode table are slower on the i486. They're the
2068 versions with the implicitly specified single-position
2069 displacement, which has another syntax if you really want to
2070 use that form. */
40fb9820
L		 2071 t.bitfield.imm1 = 1;
2072 t.bitfield.imm8 = 1;
2073 t.bitfield.imm8s = 1;
2074 t.bitfield.imm16 = 1;
2075 t.bitfield.imm32 = 1;
2076 t.bitfield.imm32s = 1;
2077 }
2078 else if (fits_in_signed_byte (num))
2079 {
2080 t.bitfield.imm8 = 1;
2081 t.bitfield.imm8s = 1;
2082 t.bitfield.imm16 = 1;
2083 t.bitfield.imm32 = 1;
2084 t.bitfield.imm32s = 1;
2085 }
2086 else if (fits_in_unsigned_byte (num))
2087 {
2088 t.bitfield.imm8 = 1;
2089 t.bitfield.imm16 = 1;
2090 t.bitfield.imm32 = 1;
2091 t.bitfield.imm32s = 1;
2092 }
2093 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2094 {
2095 t.bitfield.imm16 = 1;
2096 t.bitfield.imm32 = 1;
2097 t.bitfield.imm32s = 1;
2098 }
2099 else if (fits_in_signed_long (num))
2100 {
2101 t.bitfield.imm32 = 1;
2102 t.bitfield.imm32s = 1;
2103 }
2104 else if (fits_in_unsigned_long (num))
2105 t.bitfield.imm32 = 1;
2106
2107 return t;
47926f60 2108}
252b5132 2109
847f7ad4 2110static offsetT
e3bb37b5 2111offset_in_range (offsetT val, int size)
847f7ad4 2112{
508866be 2113 addressT mask;
ba2adb93 2114
847f7ad4
AM		 2115 switch (size)
2116 {
508866be
L		 2117 case 1: mask = ((addressT) 1 << 8) - 1; break;
2118 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2119 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2120#ifdef BFD64
2121 case 8: mask = ((addressT) 2 << 63) - 1; break;
2122#endif
47926f60 2123 default: abort ();
847f7ad4
AM		 2124 }
2125
9de868bf
L		 2126#ifdef BFD64
2127 /* If BFD64, sign extend val for 32bit address mode. */
2128 if (flag_code != CODE_64BIT
2129 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2130 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2131 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2132#endif
ba2adb93 2133
47926f60 2134 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2135 {
2136 char buf1[40], buf2[40];
2137
2138 sprint_value (buf1, val);
2139 sprint_value (buf2, val & mask);
2140 as_warn (_("%s shortened to %s"), buf1, buf2);
2141 }
2142 return val & mask;
2143}
2144
c32fa91d
L		 2145enum PREFIX_GROUP
2146{
2147 PREFIX_EXIST = 0,
2148 PREFIX_LOCK,
2149 PREFIX_REP,
04ef582a 2150 PREFIX_DS,
c32fa91d
L		 2151 PREFIX_OTHER
2152};
2153
2154/* Returns
2155 a. PREFIX_EXIST if attempting to add a prefix where one from the
2156 same class already exists.
2157 b. PREFIX_LOCK if lock prefix is added.
2158 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2159 d. PREFIX_DS if ds prefix is added.
2160 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2161 */
2162
2163static enum PREFIX_GROUP
e3bb37b5 2164add_prefix (unsigned int prefix)
252b5132 2165{
c32fa91d 2166 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2167 unsigned int q;
252b5132 2168
29b0f896
AM		 2169 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2170 && flag_code == CODE_64BIT)
b1905489 2171 {
161a04f6
L		 2172 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2173 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2174 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2175 ret = PREFIX_EXIST;
b1905489
JB		 2176 q = REX_PREFIX;
2177 }
3e73aa7c 2178 else
b1905489
JB		 2179 {
2180 switch (prefix)
2181 {
2182 default:
2183 abort ();
2184
b1905489 2185 case DS_PREFIX_OPCODE:
04ef582a
L		 2186 ret = PREFIX_DS;
2187 /* Fall through. */
2188 case CS_PREFIX_OPCODE:
b1905489
JB		 2189 case ES_PREFIX_OPCODE:
2190 case FS_PREFIX_OPCODE:
2191 case GS_PREFIX_OPCODE:
2192 case SS_PREFIX_OPCODE:
2193 q = SEG_PREFIX;
2194 break;
2195
2196 case REPNE_PREFIX_OPCODE:
2197 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2198 q = REP_PREFIX;
2199 ret = PREFIX_REP;
2200 break;
2201
b1905489 2202 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2203 q = LOCK_PREFIX;
2204 ret = PREFIX_LOCK;
b1905489
JB		 2205 break;
2206
2207 case FWAIT_OPCODE:
2208 q = WAIT_PREFIX;
2209 break;
2210
2211 case ADDR_PREFIX_OPCODE:
2212 q = ADDR_PREFIX;
2213 break;
2214
2215 case DATA_PREFIX_OPCODE:
2216 q = DATA_PREFIX;
2217 break;
2218 }
2219 if (i.prefix[q] != 0)
c32fa91d 2220 ret = PREFIX_EXIST;
b1905489 2221 }
252b5132 2222
b1905489 2223 if (ret)
252b5132 2224 {
b1905489
JB		 2225 if (!i.prefix[q])
2226 ++i.prefixes;
2227 i.prefix[q] |= prefix;
252b5132 2228 }
b1905489
JB		 2229 else
2230 as_bad (_("same type of prefix used twice"));
252b5132 2231
252b5132
RH		 2232 return ret;
2233}
2234
2235static void
78f12dd3 2236update_code_flag (int value, int check)
eecb386c 2237{
78f12dd3
L		 2238 PRINTF_LIKE ((*as_error));
2239
1e9cc1c2 2240 flag_code = (enum flag_code) value;
40fb9820
L		 2241 if (flag_code == CODE_64BIT)
2242 {
2243 cpu_arch_flags.bitfield.cpu64 = 1;
2244 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2245 }
2246 else
2247 {
2248 cpu_arch_flags.bitfield.cpu64 = 0;
2249 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2250 }
2251 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2252 {
78f12dd3
L		 2253 if (check)
2254 as_error = as_fatal;
2255 else
2256 as_error = as_bad;
2257 (*as_error) (_("64bit mode not supported on `%s'."),
2258 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2259 }
40fb9820 2260 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2261 {
78f12dd3
L		 2262 if (check)
2263 as_error = as_fatal;
2264 else
2265 as_error = as_bad;
2266 (*as_error) (_("32bit mode not supported on `%s'."),
2267 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2268 }
eecb386c
AM		 2269 stackop_size = '\0';
2270}
2271
78f12dd3
L		 2272static void
2273set_code_flag (int value)
2274{
2275 update_code_flag (value, 0);
2276}
2277
eecb386c 2278static void
e3bb37b5 2279set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2280{
1e9cc1c2 2281 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2282 if (flag_code != CODE_16BIT)
2283 abort ();
2284 cpu_arch_flags.bitfield.cpu64 = 0;
2285 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2286 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2287}
2288
2289static void
e3bb37b5 2290set_intel_syntax (int syntax_flag)
252b5132
RH		 2291{
2292 /* Find out if register prefixing is specified. */
2293 int ask_naked_reg = 0;
2294
2295 SKIP_WHITESPACE ();
29b0f896 2296 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2297 {
d02603dc
NC		 2298 char *string;
2299 int e = get_symbol_name (&string);
252b5132 2300
47926f60 2301 if (strcmp (string, "prefix") == 0)
252b5132 2302 ask_naked_reg = 1;
47926f60 2303 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2304 ask_naked_reg = -1;
2305 else
d0b47220 2306 as_bad (_("bad argument to syntax directive."));
d02603dc 2307 (void) restore_line_pointer (e);
252b5132
RH		 2308 }
2309 demand_empty_rest_of_line ();
c3332e24 2310
252b5132
RH		 2311 intel_syntax = syntax_flag;
2312
2313 if (ask_naked_reg == 0)
f86103b7
AM		 2314 allow_naked_reg = (intel_syntax
2315 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2316 else
2317 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2318
ee86248c 2319 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2320
e4a3b5a4 2321 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2322 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2323 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2324}
2325
1efbbeb4
L		 2326static void
2327set_intel_mnemonic (int mnemonic_flag)
2328{
e1d4d893 2329 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2330}
2331
db51cc60
L		 2332static void
2333set_allow_index_reg (int flag)
2334{
2335 allow_index_reg = flag;
2336}
2337
cb19c032 2338static void
7bab8ab5 2339set_check (int what)
cb19c032 2340{
7bab8ab5
JB		 2341 enum check_kind *kind;
2342 const char *str;
2343
2344 if (what)
2345 {
2346 kind = &operand_check;
2347 str = "operand";
2348 }
2349 else
2350 {
2351 kind = &sse_check;
2352 str = "sse";
2353 }
2354
cb19c032
L		 2355 SKIP_WHITESPACE ();
2356
2357 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2358 {
d02603dc
NC		 2359 char *string;
2360 int e = get_symbol_name (&string);
cb19c032
L		 2361
2362 if (strcmp (string, "none") == 0)
7bab8ab5 2363 *kind = check_none;
cb19c032 2364 else if (strcmp (string, "warning") == 0)
7bab8ab5 2365 *kind = check_warning;
cb19c032 2366 else if (strcmp (string, "error") == 0)
7bab8ab5 2367 *kind = check_error;
cb19c032 2368 else
7bab8ab5 2369 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2370 (void) restore_line_pointer (e);
cb19c032
L		 2371 }
2372 else
7bab8ab5 2373 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2374
2375 demand_empty_rest_of_line ();
2376}
2377
8a9036a4
L		 2378static void
2379check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2380 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2381{
2382#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2383 static const char *arch;
2384
2385 /* Intel LIOM is only supported on ELF. */
2386 if (!IS_ELF)
2387 return;
2388
2389 if (!arch)
2390 {
2391 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2392 use default_arch. */
2393 arch = cpu_arch_name;
2394 if (!arch)
2395 arch = default_arch;
2396 }
2397
81486035
L		 2398 /* If we are targeting Intel MCU, we must enable it. */
2399 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2400 || new_flag.bitfield.cpuiamcu)
2401 return;
2402
3632d14b 2403 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2404 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2405 || new_flag.bitfield.cpul1om)
8a9036a4 2406 return;
76ba9986 2407
7a9068fe
L		 2408 /* If we are targeting Intel K1OM, we must enable it. */
2409 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2410 || new_flag.bitfield.cpuk1om)
2411 return;
2412
8a9036a4
L		 2413 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2414#endif
2415}
2416
e413e4e9 2417static void
e3bb37b5 2418set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2419{
47926f60 2420 SKIP_WHITESPACE ();
e413e4e9 2421
29b0f896 2422 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2423 {
d02603dc
NC		 2424 char *string;
2425 int e = get_symbol_name (&string);
91d6fa6a 2426 unsigned int j;
40fb9820 2427 i386_cpu_flags flags;
e413e4e9 2428
91d6fa6a 2429 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2430 {
91d6fa6a 2431 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2432 {
91d6fa6a 2433 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2434
5c6af06e
JB		 2435 if (*string != '.')
2436 {
91d6fa6a 2437 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2438 cpu_sub_arch_name = NULL;
91d6fa6a 2439 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2440 if (flag_code == CODE_64BIT)
2441 {
2442 cpu_arch_flags.bitfield.cpu64 = 1;
2443 cpu_arch_flags.bitfield.cpuno64 = 0;
2444 }
2445 else
2446 {
2447 cpu_arch_flags.bitfield.cpu64 = 0;
2448 cpu_arch_flags.bitfield.cpuno64 = 1;
2449 }
91d6fa6a
NC		 2450 cpu_arch_isa = cpu_arch[j].type;
2451 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2452 if (!cpu_arch_tune_set)
2453 {
2454 cpu_arch_tune = cpu_arch_isa;
2455 cpu_arch_tune_flags = cpu_arch_isa_flags;
2456 }
5c6af06e
JB		 2457 break;
2458 }
40fb9820 2459
293f5f65
L		 2460 flags = cpu_flags_or (cpu_arch_flags,
2461 cpu_arch[j].flags);
81486035 2462
5b64d091 2463 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2464 {
6305a203
L		 2465 if (cpu_sub_arch_name)
2466 {
2467 char *name = cpu_sub_arch_name;
2468 cpu_sub_arch_name = concat (name,
91d6fa6a 2469 cpu_arch[j].name,
1bf57e9f 2470 (const char *) NULL);
6305a203
L		 2471 free (name);
2472 }
2473 else
91d6fa6a 2474 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2475 cpu_arch_flags = flags;
a586129e 2476 cpu_arch_isa_flags = flags;
5c6af06e 2477 }
d02603dc 2478 (void) restore_line_pointer (e);
5c6af06e
JB		 2479 demand_empty_rest_of_line ();
2480 return;
e413e4e9
AM		 2481 }
2482 }
293f5f65
L		 2483
2484 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2485 {
33eaf5de 2486 /* Disable an ISA extension. */
293f5f65
L		 2487 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2488 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2489 {
2490 flags = cpu_flags_and_not (cpu_arch_flags,
2491 cpu_noarch[j].flags);
2492 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2493 {
2494 if (cpu_sub_arch_name)
2495 {
2496 char *name = cpu_sub_arch_name;
2497 cpu_sub_arch_name = concat (name, string,
2498 (const char *) NULL);
2499 free (name);
2500 }
2501 else
2502 cpu_sub_arch_name = xstrdup (string);
2503 cpu_arch_flags = flags;
2504 cpu_arch_isa_flags = flags;
2505 }
2506 (void) restore_line_pointer (e);
2507 demand_empty_rest_of_line ();
2508 return;
2509 }
2510
2511 j = ARRAY_SIZE (cpu_arch);
2512 }
2513
91d6fa6a 2514 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2515 as_bad (_("no such architecture: `%s'"), string);
2516
2517 *input_line_pointer = e;
2518 }
2519 else
2520 as_bad (_("missing cpu architecture"));
2521
fddf5b5b
AM		 2522 no_cond_jump_promotion = 0;
2523 if (*input_line_pointer == ','
29b0f896 2524 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2525 {
d02603dc
NC		 2526 char *string;
2527 char e;
2528
2529 ++input_line_pointer;
2530 e = get_symbol_name (&string);
fddf5b5b
AM		 2531
2532 if (strcmp (string, "nojumps") == 0)
2533 no_cond_jump_promotion = 1;
2534 else if (strcmp (string, "jumps") == 0)
2535 ;
2536 else
2537 as_bad (_("no such architecture modifier: `%s'"), string);
2538
d02603dc 2539 (void) restore_line_pointer (e);
fddf5b5b
AM		 2540 }
2541
e413e4e9
AM		 2542 demand_empty_rest_of_line ();
2543}
2544
8a9036a4
L		 2545enum bfd_architecture
2546i386_arch (void)
2547{
3632d14b 2548 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2549 {
2550 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2551 || flag_code != CODE_64BIT)
2552 as_fatal (_("Intel L1OM is 64bit ELF only"));
2553 return bfd_arch_l1om;
2554 }
7a9068fe
L		 2555 else if (cpu_arch_isa == PROCESSOR_K1OM)
2556 {
2557 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2558 || flag_code != CODE_64BIT)
2559 as_fatal (_("Intel K1OM is 64bit ELF only"));
2560 return bfd_arch_k1om;
2561 }
81486035
L		 2562 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2563 {
2564 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2565 || flag_code == CODE_64BIT)
2566 as_fatal (_("Intel MCU is 32bit ELF only"));
2567 return bfd_arch_iamcu;
2568 }
8a9036a4
L		 2569 else
2570 return bfd_arch_i386;
2571}
2572
b9d79e03 2573unsigned long
7016a5d5 2574i386_mach (void)
b9d79e03 2575{
351f65ca 2576 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2577 {
3632d14b 2578 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2579 {
351f65ca
L		 2580 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2581 || default_arch[6] != '\0')
8a9036a4
L		 2582 as_fatal (_("Intel L1OM is 64bit ELF only"));
2583 return bfd_mach_l1om;
2584 }
7a9068fe
L		 2585 else if (cpu_arch_isa == PROCESSOR_K1OM)
2586 {
2587 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2588 || default_arch[6] != '\0')
2589 as_fatal (_("Intel K1OM is 64bit ELF only"));
2590 return bfd_mach_k1om;
2591 }
351f65ca 2592 else if (default_arch[6] == '\0')
8a9036a4 2593 return bfd_mach_x86_64;
351f65ca
L		 2594 else
2595 return bfd_mach_x64_32;
8a9036a4 2596 }
5197d474
L		 2597 else if (!strcmp (default_arch, "i386")
2598 || !strcmp (default_arch, "iamcu"))
81486035
L		 2599 {
2600 if (cpu_arch_isa == PROCESSOR_IAMCU)
2601 {
2602 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2603 as_fatal (_("Intel MCU is 32bit ELF only"));
2604 return bfd_mach_i386_iamcu;
2605 }
2606 else
2607 return bfd_mach_i386_i386;
2608 }
b9d79e03 2609 else
2b5d6a91 2610 as_fatal (_("unknown architecture"));
b9d79e03 2611}
b9d79e03 2612\f
252b5132 2613void
7016a5d5 2614md_begin (void)
252b5132
RH		 2615{
2616 const char *hash_err;
2617
86fa6981
L		 2618 /* Support pseudo prefixes like {disp32}. */
2619 lex_type ['{'] = LEX_BEGIN_NAME;
2620
47926f60 2621 /* Initialize op_hash hash table. */
252b5132
RH		 2622 op_hash = hash_new ();
2623
2624 {
d3ce72d0 2625 const insn_template *optab;
29b0f896 2626 templates *core_optab;
252b5132 2627
47926f60
KH		 2628 /* Setup for loop. */
2629 optab = i386_optab;
add39d23 2630 core_optab = XNEW (templates);
252b5132
RH		 2631 core_optab->start = optab;
2632
2633 while (1)
2634 {
2635 ++optab;
2636 if (optab->name == NULL
2637 || strcmp (optab->name, (optab - 1)->name) != 0)
2638 {
2639 /* different name --> ship out current template list;
47926f60 2640 add to hash table; & begin anew. */
252b5132
RH		 2641 core_optab->end = optab;
2642 hash_err = hash_insert (op_hash,
2643 (optab - 1)->name,
5a49b8ac 2644 (void *) core_optab);
252b5132
RH		 2645 if (hash_err)
2646 {
b37df7c4 2647 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2648 (optab - 1)->name,
2649 hash_err);
2650 }
2651 if (optab->name == NULL)
2652 break;
add39d23 2653 core_optab = XNEW (templates);
252b5132
RH		 2654 core_optab->start = optab;
2655 }
2656 }
2657 }
2658
47926f60 2659 /* Initialize reg_hash hash table. */
252b5132
RH		 2660 reg_hash = hash_new ();
2661 {
29b0f896 2662 const reg_entry *regtab;
c3fe08fa 2663 unsigned int regtab_size = i386_regtab_size;
252b5132 2664
c3fe08fa 2665 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2666 {
5a49b8ac 2667 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2668 if (hash_err)
b37df7c4 2669 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2670 regtab->reg_name,
2671 hash_err);
252b5132
RH		 2672 }
2673 }
2674
47926f60 2675 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2676 {
29b0f896
AM		 2677 int c;
2678 char *p;
252b5132
RH		 2679
2680 for (c = 0; c < 256; c++)
2681 {
3882b010 2682 if (ISDIGIT (c))
252b5132
RH		 2683 {
2684 digit_chars[c] = c;
2685 mnemonic_chars[c] = c;
2686 register_chars[c] = c;
2687 operand_chars[c] = c;
2688 }
3882b010 2689 else if (ISLOWER (c))
252b5132
RH		 2690 {
2691 mnemonic_chars[c] = c;
2692 register_chars[c] = c;
2693 operand_chars[c] = c;
2694 }
3882b010 2695 else if (ISUPPER (c))
252b5132 2696 {
3882b010 2697 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2698 register_chars[c] = mnemonic_chars[c];
2699 operand_chars[c] = c;
2700 }
43234a1e 2701 else if (c == '{' || c == '}')
86fa6981
L		 2702 {
2703 mnemonic_chars[c] = c;
2704 operand_chars[c] = c;
2705 }
252b5132 2706
3882b010 2707 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2708 identifier_chars[c] = c;
2709 else if (c >= 128)
2710 {
2711 identifier_chars[c] = c;
2712 operand_chars[c] = c;
2713 }
2714 }
2715
2716#ifdef LEX_AT
2717 identifier_chars['@'] = '@';
32137342
NC		 2718#endif
2719#ifdef LEX_QM
2720 identifier_chars['?'] = '?';
2721 operand_chars['?'] = '?';
252b5132 2722#endif
252b5132 2723 digit_chars['-'] = '-';
c0f3af97 2724 mnemonic_chars['_'] = '_';
791fe849 2725 mnemonic_chars['-'] = '-';
0003779b 2726 mnemonic_chars['.'] = '.';
252b5132
RH		 2727 identifier_chars['_'] = '_';
2728 identifier_chars['.'] = '.';
2729
2730 for (p = operand_special_chars; *p != '\0'; p++)
2731 operand_chars[(unsigned char) *p] = *p;
2732 }
2733
a4447b93
RH		 2734 if (flag_code == CODE_64BIT)
2735 {
ca19b261
KT		 2736#if defined (OBJ_COFF) && defined (TE_PE)
2737 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2738 ? 32 : 16);
2739#else
a4447b93 2740 x86_dwarf2_return_column = 16;
ca19b261 2741#endif
61ff971f 2742 x86_cie_data_alignment = -8;
a4447b93
RH		 2743 }
2744 else
2745 {
2746 x86_dwarf2_return_column = 8;
2747 x86_cie_data_alignment = -4;
2748 }
252b5132
RH		 2749}
2750
2751void
e3bb37b5 2752i386_print_statistics (FILE *file)
252b5132
RH		 2753{
2754 hash_print_statistics (file, "i386 opcode", op_hash);
2755 hash_print_statistics (file, "i386 register", reg_hash);
2756}
2757\f
252b5132
RH		 2758#ifdef DEBUG386
2759
ce8a8b2f 2760/* Debugging routines for md_assemble. */
d3ce72d0 2761static void pte (insn_template *);
40fb9820 2762static void pt (i386_operand_type);
e3bb37b5
L		 2763static void pe (expressionS *);
2764static void ps (symbolS *);
252b5132
RH		 2765
2766static void
e3bb37b5 2767pi (char *line, i386_insn *x)
252b5132 2768{
09137c09 2769 unsigned int j;
252b5132
RH		 2770
2771 fprintf (stdout, "%s: template ", line);
2772 pte (&x->tm);
09f131f2
JH		 2773 fprintf (stdout, " address: base %s index %s scale %x\n",
2774 x->base_reg ? x->base_reg->reg_name : "none",
2775 x->index_reg ? x->index_reg->reg_name : "none",
2776 x->log2_scale_factor);
2777 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2778 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2779 fprintf (stdout, " sib: base %x index %x scale %x\n",
2780 x->sib.base, x->sib.index, x->sib.scale);
2781 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2782 (x->rex & REX_W) != 0,
2783 (x->rex & REX_R) != 0,
2784 (x->rex & REX_X) != 0,
2785 (x->rex & REX_B) != 0);
09137c09 2786 for (j = 0; j < x->operands; j++)
252b5132 2787 {
09137c09
SP		 2788 fprintf (stdout, " #%d: ", j + 1);
2789 pt (x->types[j]);
252b5132 2790 fprintf (stdout, "\n");
09137c09
SP		 2791 if (x->types[j].bitfield.reg8
2792 || x->types[j].bitfield.reg16
2793 || x->types[j].bitfield.reg32
2794 || x->types[j].bitfield.reg64
2795 || x->types[j].bitfield.regmmx
2796 || x->types[j].bitfield.regxmm
2797 || x->types[j].bitfield.regymm
43234a1e 2798 || x->types[j].bitfield.regzmm
09137c09
SP		 2799 || x->types[j].bitfield.sreg2
2800 || x->types[j].bitfield.sreg3
2801 || x->types[j].bitfield.control
2802 || x->types[j].bitfield.debug
2803 || x->types[j].bitfield.test)
2804 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2805 if (operand_type_check (x->types[j], imm))
2806 pe (x->op[j].imms);
2807 if (operand_type_check (x->types[j], disp))
2808 pe (x->op[j].disps);
252b5132
RH		 2809 }
2810}
2811
2812static void
d3ce72d0 2813pte (insn_template *t)
252b5132 2814{
09137c09 2815 unsigned int j;
252b5132 2816 fprintf (stdout, " %d operands ", t->operands);
47926f60 2817 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2818 if (t->extension_opcode != None)
2819 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2820 if (t->opcode_modifier.d)
252b5132 2821 fprintf (stdout, "D");
40fb9820 2822 if (t->opcode_modifier.w)
252b5132
RH		 2823 fprintf (stdout, "W");
2824 fprintf (stdout, "\n");
09137c09 2825 for (j = 0; j < t->operands; j++)
252b5132 2826 {
09137c09
SP		 2827 fprintf (stdout, " #%d type ", j + 1);
2828 pt (t->operand_types[j]);
252b5132
RH		 2829 fprintf (stdout, "\n");
2830 }
2831}
2832
2833static void
e3bb37b5 2834pe (expressionS *e)
252b5132 2835{
24eab124 2836 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2837 fprintf (stdout, " add_number %ld (%lx)\n",
2838 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2839 if (e->X_add_symbol)
2840 {
2841 fprintf (stdout, " add_symbol ");
2842 ps (e->X_add_symbol);
2843 fprintf (stdout, "\n");
2844 }
2845 if (e->X_op_symbol)
2846 {
2847 fprintf (stdout, " op_symbol ");
2848 ps (e->X_op_symbol);
2849 fprintf (stdout, "\n");
2850 }
2851}
2852
2853static void
e3bb37b5 2854ps (symbolS *s)
252b5132
RH		 2855{
2856 fprintf (stdout, "%s type %s%s",
2857 S_GET_NAME (s),
2858 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2859 segment_name (S_GET_SEGMENT (s)));
2860}
2861
7b81dfbb 2862static struct type_name
252b5132 2863 {
40fb9820
L		 2864 i386_operand_type mask;
2865 const char *name;
252b5132 2866 }
7b81dfbb 2867const type_names[] =
252b5132 2868{
40fb9820
L		 2869 { OPERAND_TYPE_REG8, "r8" },
2870 { OPERAND_TYPE_REG16, "r16" },
2871 { OPERAND_TYPE_REG32, "r32" },
2872 { OPERAND_TYPE_REG64, "r64" },
2873 { OPERAND_TYPE_IMM8, "i8" },
2874 { OPERAND_TYPE_IMM8, "i8s" },
2875 { OPERAND_TYPE_IMM16, "i16" },
2876 { OPERAND_TYPE_IMM32, "i32" },
2877 { OPERAND_TYPE_IMM32S, "i32s" },
2878 { OPERAND_TYPE_IMM64, "i64" },
2879 { OPERAND_TYPE_IMM1, "i1" },
2880 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2881 { OPERAND_TYPE_DISP8, "d8" },
2882 { OPERAND_TYPE_DISP16, "d16" },
2883 { OPERAND_TYPE_DISP32, "d32" },
2884 { OPERAND_TYPE_DISP32S, "d32s" },
2885 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2886 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2887 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2888 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2889 { OPERAND_TYPE_CONTROL, "control reg" },
2890 { OPERAND_TYPE_TEST, "test reg" },
2891 { OPERAND_TYPE_DEBUG, "debug reg" },
2892 { OPERAND_TYPE_FLOATREG, "FReg" },
2893 { OPERAND_TYPE_FLOATACC, "FAcc" },
2894 { OPERAND_TYPE_SREG2, "SReg2" },
2895 { OPERAND_TYPE_SREG3, "SReg3" },
2896 { OPERAND_TYPE_ACC, "Acc" },
2897 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2898 { OPERAND_TYPE_REGMMX, "rMMX" },
2899 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2900 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2901 { OPERAND_TYPE_REGZMM, "rZMM" },
2902 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2903 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2904};
2905
2906static void
40fb9820 2907pt (i386_operand_type t)
252b5132 2908{
40fb9820 2909 unsigned int j;
c6fb90c8 2910 i386_operand_type a;
252b5132 2911
40fb9820 2912 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2913 {
2914 a = operand_type_and (t, type_names[j].mask);
0349dc08 2915 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2916 fprintf (stdout, "%s, ", type_names[j].name);
2917 }
252b5132
RH		 2918 fflush (stdout);
2919}
2920
2921#endif /* DEBUG386 */
2922\f
252b5132 2923static bfd_reloc_code_real_type
3956db08 2924reloc (unsigned int size,
64e74474
AM		 2925 int pcrel,
2926 int sign,
2927 bfd_reloc_code_real_type other)
252b5132 2928{
47926f60 2929 if (other != NO_RELOC)
3956db08 2930 {
91d6fa6a 2931 reloc_howto_type *rel;
3956db08
JB		 2932
2933 if (size == 8)
2934 switch (other)
2935 {
64e74474
AM		 2936 case BFD_RELOC_X86_64_GOT32:
2937 return BFD_RELOC_X86_64_GOT64;
2938 break;
553d1284
L		 2939 case BFD_RELOC_X86_64_GOTPLT64:
2940 return BFD_RELOC_X86_64_GOTPLT64;
2941 break;
64e74474
AM		 2942 case BFD_RELOC_X86_64_PLTOFF64:
2943 return BFD_RELOC_X86_64_PLTOFF64;
2944 break;
2945 case BFD_RELOC_X86_64_GOTPC32:
2946 other = BFD_RELOC_X86_64_GOTPC64;
2947 break;
2948 case BFD_RELOC_X86_64_GOTPCREL:
2949 other = BFD_RELOC_X86_64_GOTPCREL64;
2950 break;
2951 case BFD_RELOC_X86_64_TPOFF32:
2952 other = BFD_RELOC_X86_64_TPOFF64;
2953 break;
2954 case BFD_RELOC_X86_64_DTPOFF32:
2955 other = BFD_RELOC_X86_64_DTPOFF64;
2956 break;
2957 default:
2958 break;
3956db08 2959 }
e05278af 2960
8ce3d284 2961#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2962 if (other == BFD_RELOC_SIZE32)
2963 {
2964 if (size == 8)
1ab668bf 2965 other = BFD_RELOC_SIZE64;
8fd4256d 2966 if (pcrel)
1ab668bf
AM		 2967 {
2968 as_bad (_("there are no pc-relative size relocations"));
2969 return NO_RELOC;
2970 }
8fd4256d 2971 }
8ce3d284 2972#endif
8fd4256d 2973
e05278af 2974 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2975 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2976 sign = -1;
2977
91d6fa6a
NC		 2978 rel = bfd_reloc_type_lookup (stdoutput, other);
2979 if (!rel)
3956db08 2980 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2981 else if (size != bfd_get_reloc_size (rel))
3956db08 2982 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2983 bfd_get_reloc_size (rel),
3956db08 2984 size);
91d6fa6a 2985 else if (pcrel && !rel->pc_relative)
3956db08 2986 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2987 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2988 && !sign)
91d6fa6a 2989 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2990 && sign > 0))
3956db08
JB		 2991 as_bad (_("relocated field and relocation type differ in signedness"));
2992 else
2993 return other;
2994 return NO_RELOC;
2995 }
252b5132
RH		 2996
2997 if (pcrel)
2998 {
3e73aa7c 2999 if (!sign)
3956db08 3000 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3001 switch (size)
3002 {
3003 case 1: return BFD_RELOC_8_PCREL;
3004 case 2: return BFD_RELOC_16_PCREL;
d258b828 3005 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3006 case 8: return BFD_RELOC_64_PCREL;
252b5132 3007 }
3956db08 3008 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3009 }
3010 else
3011 {
3956db08 3012 if (sign > 0)
e5cb08ac 3013 switch (size)
3e73aa7c
JH		 3014 {
3015 case 4: return BFD_RELOC_X86_64_32S;
3016 }
3017 else
3018 switch (size)
3019 {
3020 case 1: return BFD_RELOC_8;
3021 case 2: return BFD_RELOC_16;
3022 case 4: return BFD_RELOC_32;
3023 case 8: return BFD_RELOC_64;
3024 }
3956db08
JB		 3025 as_bad (_("cannot do %s %u byte relocation"),
3026 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3027 }
3028
0cc9e1d3 3029 return NO_RELOC;
252b5132
RH		 3030}
3031
47926f60
KH		 3032/* Here we decide which fixups can be adjusted to make them relative to
3033 the beginning of the section instead of the symbol. Basically we need
3034 to make sure that the dynamic relocations are done correctly, so in
3035 some cases we force the original symbol to be used. */
3036
252b5132 3037int
e3bb37b5 3038tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3039{
6d249963 3040#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3041 if (!IS_ELF)
31312f95
AM		 3042 return 1;
3043
a161fe53
AM		 3044 /* Don't adjust pc-relative references to merge sections in 64-bit
3045 mode. */
3046 if (use_rela_relocations
3047 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3048 && fixP->fx_pcrel)
252b5132 3049 return 0;
31312f95 3050
8d01d9a9
AJ		 3051 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3052 and changed later by validate_fix. */
3053 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3054 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3055 return 0;
3056
8fd4256d
L		 3057 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3058 for size relocations. */
3059 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3060 || fixP->fx_r_type == BFD_RELOC_SIZE64
3061 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3062 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3063 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3064 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3065 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3066 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3067 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3068 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3069 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3070 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3071 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3072 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3073 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3074 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3075 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3076 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3077 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3078 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3079 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3080 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3081 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3082 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3083 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3084 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3085 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3086 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3087 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3088 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3089 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3090 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3091 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3092 return 0;
31312f95 3093#endif
252b5132
RH		 3094 return 1;
3095}
252b5132 3096
b4cac588 3097static int
e3bb37b5 3098intel_float_operand (const char *mnemonic)
252b5132 3099{
9306ca4a
JB		 3100 /* Note that the value returned is meaningful only for opcodes with (memory)
3101 operands, hence the code here is free to improperly handle opcodes that
3102 have no operands (for better performance and smaller code). */
3103
3104 if (mnemonic[0] != 'f')
3105 return 0; /* non-math */
3106
3107 switch (mnemonic[1])
3108 {
3109 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3110 the fs segment override prefix not currently handled because no
3111 call path can make opcodes without operands get here */
3112 case 'i':
3113 return 2 /* integer op */;
3114 case 'l':
3115 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3116 return 3; /* fldcw/fldenv */
3117 break;
3118 case 'n':
3119 if (mnemonic[2] != 'o' /* fnop */)
3120 return 3; /* non-waiting control op */
3121 break;
3122 case 'r':
3123 if (mnemonic[2] == 's')
3124 return 3; /* frstor/frstpm */
3125 break;
3126 case 's':
3127 if (mnemonic[2] == 'a')
3128 return 3; /* fsave */
3129 if (mnemonic[2] == 't')
3130 {
3131 switch (mnemonic[3])
3132 {
3133 case 'c': /* fstcw */
3134 case 'd': /* fstdw */
3135 case 'e': /* fstenv */
3136 case 's': /* fsts[gw] */
3137 return 3;
3138 }
3139 }
3140 break;
3141 case 'x':
3142 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3143 return 0; /* fxsave/fxrstor are not really math ops */
3144 break;
3145 }
252b5132 3146
9306ca4a 3147 return 1;
252b5132
RH		 3148}
3149
c0f3af97
L		 3150/* Build the VEX prefix. */
3151
3152static void
d3ce72d0 3153build_vex_prefix (const insn_template *t)
c0f3af97
L		 3154{
3155 unsigned int register_specifier;
3156 unsigned int implied_prefix;
3157 unsigned int vector_length;
3158
3159 /* Check register specifier. */
3160 if (i.vex.register_specifier)
43234a1e
L		 3161 {
3162 register_specifier =
3163 ~register_number (i.vex.register_specifier) & 0xf;
3164 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3165 }
c0f3af97
L		 3166 else
3167 register_specifier = 0xf;
3168
33eaf5de 3169 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3170 operand. */
86fa6981
L		 3171 if (i.vec_encoding != vex_encoding_vex3
3172 && i.dir_encoding == dir_encoding_default
fa99fab2 3173 && i.operands == i.reg_operands
7f399153 3174 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3175 && i.tm.opcode_modifier.load
fa99fab2
L		 3176 && i.rex == REX_B)
3177 {
3178 unsigned int xchg = i.operands - 1;
3179 union i386_op temp_op;
3180 i386_operand_type temp_type;
3181
3182 temp_type = i.types[xchg];
3183 i.types[xchg] = i.types[0];
3184 i.types[0] = temp_type;
3185 temp_op = i.op[xchg];
3186 i.op[xchg] = i.op[0];
3187 i.op[0] = temp_op;
3188
9c2799c2 3189 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3190
3191 i.rex = REX_R;
3192 xchg = i.rm.regmem;
3193 i.rm.regmem = i.rm.reg;
3194 i.rm.reg = xchg;
3195
3196 /* Use the next insn. */
3197 i.tm = t[1];
3198 }
3199
539f890d
L		 3200 if (i.tm.opcode_modifier.vex == VEXScalar)
3201 vector_length = avxscalar;
3202 else
3203 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3204
3205 switch ((i.tm.base_opcode >> 8) & 0xff)
3206 {
3207 case 0:
3208 implied_prefix = 0;
3209 break;
3210 case DATA_PREFIX_OPCODE:
3211 implied_prefix = 1;
3212 break;
3213 case REPE_PREFIX_OPCODE:
3214 implied_prefix = 2;
3215 break;
3216 case REPNE_PREFIX_OPCODE:
3217 implied_prefix = 3;
3218 break;
3219 default:
3220 abort ();
3221 }
3222
3223 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3224 if (i.vec_encoding != vex_encoding_vex3
3225 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3226 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3227 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3228 {
3229 /* 2-byte VEX prefix. */
3230 unsigned int r;
3231
3232 i.vex.length = 2;
3233 i.vex.bytes[0] = 0xc5;
3234
3235 /* Check the REX.R bit. */
3236 r = (i.rex & REX_R) ? 0 : 1;
3237 i.vex.bytes[1] = (r << 7
3238 | register_specifier << 3
3239 | vector_length << 2
3240 | implied_prefix);
3241 }
3242 else
3243 {
3244 /* 3-byte VEX prefix. */
3245 unsigned int m, w;
3246
f88c9eb0 3247 i.vex.length = 3;
f88c9eb0 3248
7f399153 3249 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3250 {
7f399153
L		 3251 case VEX0F:
3252 m = 0x1;
80de6e00 3253 i.vex.bytes[0] = 0xc4;
7f399153
L		 3254 break;
3255 case VEX0F38:
3256 m = 0x2;
80de6e00 3257 i.vex.bytes[0] = 0xc4;
7f399153
L		 3258 break;
3259 case VEX0F3A:
3260 m = 0x3;
80de6e00 3261 i.vex.bytes[0] = 0xc4;
7f399153
L		 3262 break;
3263 case XOP08:
5dd85c99
SP		 3264 m = 0x8;
3265 i.vex.bytes[0] = 0x8f;
7f399153
L		 3266 break;
3267 case XOP09:
f88c9eb0
SP		 3268 m = 0x9;
3269 i.vex.bytes[0] = 0x8f;
7f399153
L		 3270 break;
3271 case XOP0A:
f88c9eb0
SP		 3272 m = 0xa;
3273 i.vex.bytes[0] = 0x8f;
7f399153
L		 3274 break;
3275 default:
3276 abort ();
f88c9eb0 3277 }
c0f3af97 3278
c0f3af97
L		 3279 /* The high 3 bits of the second VEX byte are 1's compliment
3280 of RXB bits from REX. */
3281 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3282
3283 /* Check the REX.W bit. */
3284 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3285 if (i.tm.opcode_modifier.vexw == VEXW1)
3286 w = 1;
c0f3af97
L		 3287
3288 i.vex.bytes[2] = (w << 7
3289 | register_specifier << 3
3290 | vector_length << 2
3291 | implied_prefix);
3292 }
3293}
3294
43234a1e
L		 3295/* Build the EVEX prefix. */
3296
3297static void
3298build_evex_prefix (void)
3299{
3300 unsigned int register_specifier;
3301 unsigned int implied_prefix;
3302 unsigned int m, w;
3303 rex_byte vrex_used = 0;
3304
3305 /* Check register specifier. */
3306 if (i.vex.register_specifier)
3307 {
3308 gas_assert ((i.vrex & REX_X) == 0);
3309
3310 register_specifier = i.vex.register_specifier->reg_num;
3311 if ((i.vex.register_specifier->reg_flags & RegRex))
3312 register_specifier += 8;
3313 /* The upper 16 registers are encoded in the fourth byte of the
3314 EVEX prefix. */
3315 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3316 i.vex.bytes[3] = 0x8;
3317 register_specifier = ~register_specifier & 0xf;
3318 }
3319 else
3320 {
3321 register_specifier = 0xf;
3322
3323 /* Encode upper 16 vector index register in the fourth byte of
3324 the EVEX prefix. */
3325 if (!(i.vrex & REX_X))
3326 i.vex.bytes[3] = 0x8;
3327 else
3328 vrex_used |= REX_X;
3329 }
3330
3331 switch ((i.tm.base_opcode >> 8) & 0xff)
3332 {
3333 case 0:
3334 implied_prefix = 0;
3335 break;
3336 case DATA_PREFIX_OPCODE:
3337 implied_prefix = 1;
3338 break;
3339 case REPE_PREFIX_OPCODE:
3340 implied_prefix = 2;
3341 break;
3342 case REPNE_PREFIX_OPCODE:
3343 implied_prefix = 3;
3344 break;
3345 default:
3346 abort ();
3347 }
3348
3349 /* 4 byte EVEX prefix. */
3350 i.vex.length = 4;
3351 i.vex.bytes[0] = 0x62;
3352
3353 /* mmmm bits. */
3354 switch (i.tm.opcode_modifier.vexopcode)
3355 {
3356 case VEX0F:
3357 m = 1;
3358 break;
3359 case VEX0F38:
3360 m = 2;
3361 break;
3362 case VEX0F3A:
3363 m = 3;
3364 break;
3365 default:
3366 abort ();
3367 break;
3368 }
3369
3370 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3371 bits from REX. */
3372 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3373
3374 /* The fifth bit of the second EVEX byte is 1's compliment of the
3375 REX_R bit in VREX. */
3376 if (!(i.vrex & REX_R))
3377 i.vex.bytes[1] |= 0x10;
3378 else
3379 vrex_used |= REX_R;
3380
3381 if ((i.reg_operands + i.imm_operands) == i.operands)
3382 {
3383 /* When all operands are registers, the REX_X bit in REX is not
3384 used. We reuse it to encode the upper 16 registers, which is
3385 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3386 as 1's compliment. */
3387 if ((i.vrex & REX_B))
3388 {
3389 vrex_used |= REX_B;
3390 i.vex.bytes[1] &= ~0x40;
3391 }
3392 }
3393
3394 /* EVEX instructions shouldn't need the REX prefix. */
3395 i.vrex &= ~vrex_used;
3396 gas_assert (i.vrex == 0);
3397
3398 /* Check the REX.W bit. */
3399 w = (i.rex & REX_W) ? 1 : 0;
3400 if (i.tm.opcode_modifier.vexw)
3401 {
3402 if (i.tm.opcode_modifier.vexw == VEXW1)
3403 w = 1;
3404 }
3405 /* If w is not set it means we are dealing with WIG instruction. */
3406 else if (!w)
3407 {
3408 if (evexwig == evexw1)
3409 w = 1;
3410 }
3411
3412 /* Encode the U bit. */
3413 implied_prefix |= 0x4;
3414
3415 /* The third byte of the EVEX prefix. */
3416 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3417
3418 /* The fourth byte of the EVEX prefix. */
3419 /* The zeroing-masking bit. */
3420 if (i.mask && i.mask->zeroing)
3421 i.vex.bytes[3] |= 0x80;
3422
3423 /* Don't always set the broadcast bit if there is no RC. */
3424 if (!i.rounding)
3425 {
3426 /* Encode the vector length. */
3427 unsigned int vec_length;
3428
3429 switch (i.tm.opcode_modifier.evex)
3430 {
3431 case EVEXLIG: /* LL' is ignored */
3432 vec_length = evexlig << 5;
3433 break;
3434 case EVEX128:
3435 vec_length = 0 << 5;
3436 break;
3437 case EVEX256:
3438 vec_length = 1 << 5;
3439 break;
3440 case EVEX512:
3441 vec_length = 2 << 5;
3442 break;
3443 default:
3444 abort ();
3445 break;
3446 }
3447 i.vex.bytes[3] |= vec_length;
3448 /* Encode the broadcast bit. */
3449 if (i.broadcast)
3450 i.vex.bytes[3] |= 0x10;
3451 }
3452 else
3453 {
3454 if (i.rounding->type != saeonly)
3455 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3456 else
d3d3c6db 3457 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3458 }
3459
3460 if (i.mask && i.mask->mask)
3461 i.vex.bytes[3] |= i.mask->mask->reg_num;
3462}
3463
65da13b5
L		 3464static void
3465process_immext (void)
3466{
3467 expressionS *exp;
3468
4c692bc7
JB		 3469 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3470 && i.operands > 0)
65da13b5 3471 {
4c692bc7
JB		 3472 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3473 with an opcode suffix which is coded in the same place as an
3474 8-bit immediate field would be.
3475 Here we check those operands and remove them afterwards. */
65da13b5
L		 3476 unsigned int x;
3477
3478 for (x = 0; x < i.operands; x++)
4c692bc7 3479 if (register_number (i.op[x].regs) != x)
65da13b5 3480 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3481 register_prefix, i.op[x].regs->reg_name, x + 1,
3482 i.tm.name);
3483
3484 i.operands = 0;
65da13b5
L		 3485 }
3486
9916071f
AP		 3487 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3488 {
3489 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3490 suffix which is coded in the same place as an 8-bit immediate
3491 field would be.
3492 Here we check those operands and remove them afterwards. */
3493 unsigned int x;
3494
3495 if (i.operands != 3)
3496 abort();
3497
3498 for (x = 0; x < 2; x++)
3499 if (register_number (i.op[x].regs) != x)
3500 goto bad_register_operand;
3501
3502 /* Check for third operand for mwaitx/monitorx insn. */
3503 if (register_number (i.op[x].regs)
3504 != (x + (i.tm.extension_opcode == 0xfb)))
3505 {
3506bad_register_operand:
3507 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3508 register_prefix, i.op[x].regs->reg_name, x+1,
3509 i.tm.name);
3510 }
3511
3512 i.operands = 0;
3513 }
3514
c0f3af97 3515 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3516 which is coded in the same place as an 8-bit immediate field
3517 would be. Here we fake an 8-bit immediate operand from the
3518 opcode suffix stored in tm.extension_opcode.
3519
c1e679ec 3520 AVX instructions also use this encoding, for some of
c0f3af97 3521 3 argument instructions. */
65da13b5 3522
43234a1e 3523 gas_assert (i.imm_operands <= 1
7ab9ffdd 3524 && (i.operands <= 2
43234a1e
L		 3525 || ((i.tm.opcode_modifier.vex
3526 || i.tm.opcode_modifier.evex)
7ab9ffdd 3527 && i.operands <= 4)));
65da13b5
L		 3528
3529 exp = &im_expressions[i.imm_operands++];
3530 i.op[i.operands].imms = exp;
3531 i.types[i.operands] = imm8;
3532 i.operands++;
3533 exp->X_op = O_constant;
3534 exp->X_add_number = i.tm.extension_opcode;
3535 i.tm.extension_opcode = None;
3536}
3537
42164a71
L		 3538
3539static int
3540check_hle (void)
3541{
3542 switch (i.tm.opcode_modifier.hleprefixok)
3543 {
3544 default:
3545 abort ();
82c2def5 3546 case HLEPrefixNone:
165de32a
L		 3547 as_bad (_("invalid instruction `%s' after `%s'"),
3548 i.tm.name, i.hle_prefix);
42164a71 3549 return 0;
82c2def5 3550 case HLEPrefixLock:
42164a71
L		 3551 if (i.prefix[LOCK_PREFIX])
3552 return 1;
165de32a 3553 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3554 return 0;
82c2def5 3555 case HLEPrefixAny:
42164a71 3556 return 1;
82c2def5 3557 case HLEPrefixRelease:
42164a71
L		 3558 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3559 {
3560 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3561 i.tm.name);
3562 return 0;
3563 }
3564 if (i.mem_operands == 0
3565 || !operand_type_check (i.types[i.operands - 1], anymem))
3566 {
3567 as_bad (_("memory destination needed for instruction `%s'"
3568 " after `xrelease'"), i.tm.name);
3569 return 0;
3570 }
3571 return 1;
3572 }
3573}
3574
252b5132
RH		 3575/* This is the guts of the machine-dependent assembler. LINE points to a
3576 machine dependent instruction. This function is supposed to emit
3577 the frags/bytes it assembles to. */
3578
3579void
65da13b5 3580md_assemble (char *line)
252b5132 3581{
40fb9820 3582 unsigned int j;
83b16ac6 3583 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3584 const insn_template *t;
252b5132 3585
47926f60 3586 /* Initialize globals. */
252b5132
RH		 3587 memset (&i, '\0', sizeof (i));
3588 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3589 i.reloc[j] = NO_RELOC;
252b5132
RH		 3590 memset (disp_expressions, '\0', sizeof (disp_expressions));
3591 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3592 save_stack_p = save_stack;
252b5132
RH		 3593
3594 /* First parse an instruction mnemonic & call i386_operand for the operands.
3595 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3596 start of a (possibly prefixed) mnemonic. */
252b5132 3597
29b0f896
AM		 3598 line = parse_insn (line, mnemonic);
3599 if (line == NULL)
3600 return;
83b16ac6 3601 mnem_suffix = i.suffix;
252b5132 3602
29b0f896 3603 line = parse_operands (line, mnemonic);
ee86248c 3604 this_operand = -1;
8325cc63
JB		 3605 xfree (i.memop1_string);
3606 i.memop1_string = NULL;
29b0f896
AM		 3607 if (line == NULL)
3608 return;
252b5132 3609
29b0f896
AM		 3610 /* Now we've parsed the mnemonic into a set of templates, and have the
3611 operands at hand. */
3612
3613 /* All intel opcodes have reversed operands except for "bound" and
3614 "enter". We also don't reverse intersegment "jmp" and "call"
3615 instructions with 2 immediate operands so that the immediate segment
050dfa73 3616 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3617 if (intel_syntax
3618 && i.operands > 1
29b0f896 3619 && (strcmp (mnemonic, "bound") != 0)
30123838 3620 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3621 && !(operand_type_check (i.types[0], imm)
3622 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3623 swap_operands ();
3624
ec56d5c0
JB		 3625 /* The order of the immediates should be reversed
3626 for 2 immediates extrq and insertq instructions */
3627 if (i.imm_operands == 2
3628 && (strcmp (mnemonic, "extrq") == 0
3629 || strcmp (mnemonic, "insertq") == 0))
3630 swap_2_operands (0, 1);
3631
29b0f896
AM		 3632 if (i.imm_operands)
3633 optimize_imm ();
3634
b300c311
L		 3635 /* Don't optimize displacement for movabs since it only takes 64bit
3636 displacement. */
3637 if (i.disp_operands
a501d77e 3638 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3639 && (flag_code != CODE_64BIT
3640 || strcmp (mnemonic, "movabs") != 0))
3641 optimize_disp ();
29b0f896
AM		 3642
3643 /* Next, we find a template that matches the given insn,
3644 making sure the overlap of the given operands types is consistent
3645 with the template operand types. */
252b5132 3646
83b16ac6 3647 if (!(t = match_template (mnem_suffix)))
29b0f896 3648 return;
252b5132 3649
7bab8ab5 3650 if (sse_check != check_none
81f8a913 3651 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3652 && (i.tm.cpu_flags.bitfield.cpusse
3653 || i.tm.cpu_flags.bitfield.cpusse2
3654 || i.tm.cpu_flags.bitfield.cpusse3
3655 || i.tm.cpu_flags.bitfield.cpussse3
3656 || i.tm.cpu_flags.bitfield.cpusse4_1
3657 || i.tm.cpu_flags.bitfield.cpusse4_2))
3658 {
7bab8ab5 3659 (sse_check == check_warning
daf50ae7
L		 3660 ? as_warn
3661 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3662 }
3663
321fd21e
L		 3664 /* Zap movzx and movsx suffix. The suffix has been set from
3665 "word ptr" or "byte ptr" on the source operand in Intel syntax
3666 or extracted from mnemonic in AT&T syntax. But we'll use
3667 the destination register to choose the suffix for encoding. */
3668 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3669 {
321fd21e
L		 3670 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3671 there is no suffix, the default will be byte extension. */
3672 if (i.reg_operands != 2
3673 && !i.suffix
7ab9ffdd 3674 && intel_syntax)
321fd21e
L		 3675 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3676
3677 i.suffix = 0;
cd61ebfe 3678 }
24eab124 3679
40fb9820 3680 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3681 if (!add_prefix (FWAIT_OPCODE))
3682 return;
252b5132 3683
d5de92cf
L		 3684 /* Check if REP prefix is OK. */
3685 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3686 {
3687 as_bad (_("invalid instruction `%s' after `%s'"),
3688 i.tm.name, i.rep_prefix);
3689 return;
3690 }
3691
c1ba0266
L		 3692 /* Check for lock without a lockable instruction. Destination operand
3693 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3694 if (i.prefix[LOCK_PREFIX]
3695 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3696 || i.mem_operands == 0
3697 || (i.tm.base_opcode != 0x86
3698 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3699 {
3700 as_bad (_("expecting lockable instruction after `lock'"));
3701 return;
3702 }
3703
42164a71 3704 /* Check if HLE prefix is OK. */
165de32a 3705 if (i.hle_prefix && !check_hle ())
42164a71
L		 3706 return;
3707
7e8b059b
L		 3708 /* Check BND prefix. */
3709 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3710 as_bad (_("expecting valid branch instruction after `bnd'"));
3711
04ef582a 3712 /* Check NOTRACK prefix. */
9fef80d6
L		 3713 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3714 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3715
327e8c42
JB		 3716 if (i.tm.cpu_flags.bitfield.cpumpx)
3717 {
3718 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3719 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3720 else if (flag_code != CODE_16BIT
3721 ? i.prefix[ADDR_PREFIX]
3722 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3723 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3724 }
7e8b059b
L		 3725
3726 /* Insert BND prefix. */
3727 if (add_bnd_prefix
3728 && i.tm.opcode_modifier.bndprefixok
3729 && !i.prefix[BND_PREFIX])
3730 add_prefix (BND_PREFIX_OPCODE);
3731
29b0f896 3732 /* Check string instruction segment overrides. */
40fb9820 3733 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3734 {
3735 if (!check_string ())
5dd0794d 3736 return;
fc0763e6 3737 i.disp_operands = 0;
29b0f896 3738 }
5dd0794d 3739
29b0f896
AM		 3740 if (!process_suffix ())
3741 return;
e413e4e9 3742
bc0844ae
L		 3743 /* Update operand types. */
3744 for (j = 0; j < i.operands; j++)
3745 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3746
29b0f896
AM		 3747 /* Make still unresolved immediate matches conform to size of immediate
3748 given in i.suffix. */
3749 if (!finalize_imm ())
3750 return;
252b5132 3751
40fb9820 3752 if (i.types[0].bitfield.imm1)
29b0f896 3753 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3754
9afe6eb8
L		 3755 /* We only need to check those implicit registers for instructions
3756 with 3 operands or less. */
3757 if (i.operands <= 3)
3758 for (j = 0; j < i.operands; j++)
3759 if (i.types[j].bitfield.inoutportreg
3760 || i.types[j].bitfield.shiftcount
3761 || i.types[j].bitfield.acc
3762 || i.types[j].bitfield.floatacc)
3763 i.reg_operands--;
40fb9820 3764
c0f3af97
L		 3765 /* ImmExt should be processed after SSE2AVX. */
3766 if (!i.tm.opcode_modifier.sse2avx
3767 && i.tm.opcode_modifier.immext)
65da13b5 3768 process_immext ();
252b5132 3769
29b0f896
AM		 3770 /* For insns with operands there are more diddles to do to the opcode. */
3771 if (i.operands)
3772 {
3773 if (!process_operands ())
3774 return;
3775 }
40fb9820 3776 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3777 {
3778 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3779 as_warn (_("translating to `%sp'"), i.tm.name);
3780 }
252b5132 3781
9e5e5283
L		 3782 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3783 {
3784 if (flag_code == CODE_16BIT)
3785 {
3786 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3787 i.tm.name);
3788 return;
3789 }
c0f3af97 3790
9e5e5283
L		 3791 if (i.tm.opcode_modifier.vex)
3792 build_vex_prefix (t);
3793 else
3794 build_evex_prefix ();
3795 }
43234a1e 3796
5dd85c99
SP		 3797 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3798 instructions may define INT_OPCODE as well, so avoid this corner
3799 case for those instructions that use MODRM. */
3800 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3801 && !i.tm.opcode_modifier.modrm
3802 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3803 {
3804 i.tm.base_opcode = INT3_OPCODE;
3805 i.imm_operands = 0;
3806 }
252b5132 3807
40fb9820
L		 3808 if ((i.tm.opcode_modifier.jump
3809 || i.tm.opcode_modifier.jumpbyte
3810 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3811 && i.op[0].disps->X_op == O_constant)
3812 {
3813 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3814 the absolute address given by the constant. Since ix86 jumps and
3815 calls are pc relative, we need to generate a reloc. */
3816 i.op[0].disps->X_add_symbol = &abs_symbol;
3817 i.op[0].disps->X_op = O_symbol;
3818 }
252b5132 3819
40fb9820 3820 if (i.tm.opcode_modifier.rex64)
161a04f6 3821 i.rex |= REX_W;
252b5132 3822
29b0f896
AM		 3823 /* For 8 bit registers we need an empty rex prefix. Also if the
3824 instruction already has a prefix, we need to convert old
3825 registers to new ones. */
773f551c 3826
40fb9820 3827 if ((i.types[0].bitfield.reg8
29b0f896 3828 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3829 || (i.types[1].bitfield.reg8
29b0f896 3830 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3831 || ((i.types[0].bitfield.reg8
3832 || i.types[1].bitfield.reg8)
29b0f896
AM		 3833 && i.rex != 0))
3834 {
3835 int x;
726c5dcd 3836
29b0f896
AM		 3837 i.rex |= REX_OPCODE;
3838 for (x = 0; x < 2; x++)
3839 {
3840 /* Look for 8 bit operand that uses old registers. */
40fb9820 3841 if (i.types[x].bitfield.reg8
29b0f896 3842 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3843 {
29b0f896
AM		 3844 /* In case it is "hi" register, give up. */
3845 if (i.op[x].regs->reg_num > 3)
a540244d 3846 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3847 "instruction requiring REX prefix."),
a540244d 3848 register_prefix, i.op[x].regs->reg_name);
773f551c 3849
29b0f896
AM		 3850 /* Otherwise it is equivalent to the extended register.
3851 Since the encoding doesn't change this is merely
3852 cosmetic cleanup for debug output. */
3853
3854 i.op[x].regs = i.op[x].regs + 8;
773f551c 3855 }
29b0f896
AM		 3856 }
3857 }
773f551c 3858
7ab9ffdd 3859 if (i.rex != 0)
29b0f896
AM		 3860 add_prefix (REX_OPCODE | i.rex);
3861
3862 /* We are ready to output the insn. */
3863 output_insn ();
3864}
3865
3866static char *
e3bb37b5 3867parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3868{
3869 char *l = line;
3870 char *token_start = l;
3871 char *mnem_p;
5c6af06e 3872 int supported;
d3ce72d0 3873 const insn_template *t;
b6169b20 3874 char *dot_p = NULL;
29b0f896 3875
29b0f896
AM		 3876 while (1)
3877 {
3878 mnem_p = mnemonic;
3879 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3880 {
b6169b20
L		 3881 if (*mnem_p == '.')
3882 dot_p = mnem_p;
29b0f896
AM		 3883 mnem_p++;
3884 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3885 {
29b0f896
AM		 3886 as_bad (_("no such instruction: `%s'"), token_start);
3887 return NULL;
3888 }
3889 l++;
3890 }
3891 if (!is_space_char (*l)
3892 && *l != END_OF_INSN
e44823cf
JB		 3893 && (intel_syntax
3894 || (*l != PREFIX_SEPARATOR
3895 && *l != ',')))
29b0f896
AM		 3896 {
3897 as_bad (_("invalid character %s in mnemonic"),
3898 output_invalid (*l));
3899 return NULL;
3900 }
3901 if (token_start == l)
3902 {
e44823cf 3903 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3904 as_bad (_("expecting prefix; got nothing"));
3905 else
3906 as_bad (_("expecting mnemonic; got nothing"));
3907 return NULL;
3908 }
45288df1 3909
29b0f896 3910 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3911 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3912
29b0f896
AM		 3913 if (*l != END_OF_INSN
3914 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3915 && current_templates
40fb9820 3916 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3917 {
c6fb90c8 3918 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3919 {
3920 as_bad ((flag_code != CODE_64BIT
3921 ? _("`%s' is only supported in 64-bit mode")
3922 : _("`%s' is not supported in 64-bit mode")),
3923 current_templates->start->name);
3924 return NULL;
3925 }
29b0f896
AM		 3926 /* If we are in 16-bit mode, do not allow addr16 or data16.
3927 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3928 if ((current_templates->start->opcode_modifier.size16
3929 || current_templates->start->opcode_modifier.size32)
29b0f896 3930 && flag_code != CODE_64BIT
40fb9820 3931 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3932 ^ (flag_code == CODE_16BIT)))
3933 {
3934 as_bad (_("redundant %s prefix"),
3935 current_templates->start->name);
3936 return NULL;
45288df1 3937 }
86fa6981 3938 if (current_templates->start->opcode_length == 0)
29b0f896 3939 {
86fa6981
L		 3940 /* Handle pseudo prefixes. */
3941 switch (current_templates->start->base_opcode)
3942 {
3943 case 0x0:
3944 /* {disp8} */
3945 i.disp_encoding = disp_encoding_8bit;
3946 break;
3947 case 0x1:
3948 /* {disp32} */
3949 i.disp_encoding = disp_encoding_32bit;
3950 break;
3951 case 0x2:
3952 /* {load} */
3953 i.dir_encoding = dir_encoding_load;
3954 break;
3955 case 0x3:
3956 /* {store} */
3957 i.dir_encoding = dir_encoding_store;
3958 break;
3959 case 0x4:
3960 /* {vex2} */
3961 i.vec_encoding = vex_encoding_vex2;
3962 break;
3963 case 0x5:
3964 /* {vex3} */
3965 i.vec_encoding = vex_encoding_vex3;
3966 break;
3967 case 0x6:
3968 /* {evex} */
3969 i.vec_encoding = vex_encoding_evex;
3970 break;
3971 default:
3972 abort ();
3973 }
3974 }
3975 else
3976 {
3977 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 3978 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 3979 {
4e9ac44a
L		 3980 case PREFIX_EXIST:
3981 return NULL;
3982 case PREFIX_DS:
3983 if (current_templates->start->cpu_flags.bitfield.cpucet)
3984 i.notrack_prefix = current_templates->start->name;
3985 break;
3986 case PREFIX_REP:
3987 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3988 i.hle_prefix = current_templates->start->name;
3989 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3990 i.bnd_prefix = current_templates->start->name;
3991 else
3992 i.rep_prefix = current_templates->start->name;
3993 break;
3994 default:
3995 break;
86fa6981 3996 }
29b0f896
AM		 3997 }
3998 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3999 token_start = ++l;
4000 }
4001 else
4002 break;
4003 }
45288df1 4004
30a55f88 4005 if (!current_templates)
b6169b20 4006 {
f8a5c266
L		 4007 /* Check if we should swap operand or force 32bit displacement in
4008 encoding. */
30a55f88 4009 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4010 i.dir_encoding = dir_encoding_store;
8d63c93e 4011 else if (mnem_p - 3 == dot_p
a501d77e
L		 4012 && dot_p[1] == 'd'
4013 && dot_p[2] == '8')
4014 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4015 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4016 && dot_p[1] == 'd'
4017 && dot_p[2] == '3'
4018 && dot_p[3] == '2')
a501d77e 4019 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4020 else
4021 goto check_suffix;
4022 mnem_p = dot_p;
4023 *dot_p = '\0';
d3ce72d0 4024 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4025 }
4026
29b0f896
AM		 4027 if (!current_templates)
4028 {
b6169b20 4029check_suffix:
29b0f896
AM		 4030 /* See if we can get a match by trimming off a suffix. */
4031 switch (mnem_p[-1])
4032 {
4033 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4034 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4035 i.suffix = SHORT_MNEM_SUFFIX;
4036 else
1a0670f3 4037 /* Fall through. */
29b0f896
AM		 4038 case BYTE_MNEM_SUFFIX:
4039 case QWORD_MNEM_SUFFIX:
4040 i.suffix = mnem_p[-1];
4041 mnem_p[-1] = '\0';
d3ce72d0
NC		 4042 current_templates = (const templates *) hash_find (op_hash,
4043 mnemonic);
29b0f896
AM		 4044 break;
4045 case SHORT_MNEM_SUFFIX:
4046 case LONG_MNEM_SUFFIX:
4047 if (!intel_syntax)
4048 {
4049 i.suffix = mnem_p[-1];
4050 mnem_p[-1] = '\0';
d3ce72d0
NC		 4051 current_templates = (const templates *) hash_find (op_hash,
4052 mnemonic);
29b0f896
AM		 4053 }
4054 break;
252b5132 4055
29b0f896
AM		 4056 /* Intel Syntax. */
4057 case 'd':
4058 if (intel_syntax)
4059 {
9306ca4a 4060 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4061 i.suffix = SHORT_MNEM_SUFFIX;
4062 else
4063 i.suffix = LONG_MNEM_SUFFIX;
4064 mnem_p[-1] = '\0';
d3ce72d0
NC		 4065 current_templates = (const templates *) hash_find (op_hash,
4066 mnemonic);
29b0f896
AM		 4067 }
4068 break;
4069 }
4070 if (!current_templates)
4071 {
4072 as_bad (_("no such instruction: `%s'"), token_start);
4073 return NULL;
4074 }
4075 }
252b5132 4076
40fb9820
L		 4077 if (current_templates->start->opcode_modifier.jump
4078 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4079 {
4080 /* Check for a branch hint. We allow ",pt" and ",pn" for
4081 predict taken and predict not taken respectively.
4082 I'm not sure that branch hints actually do anything on loop
4083 and jcxz insns (JumpByte) for current Pentium4 chips. They
4084 may work in the future and it doesn't hurt to accept them
4085 now. */
4086 if (l[0] == ',' && l[1] == 'p')
4087 {
4088 if (l[2] == 't')
4089 {
4090 if (!add_prefix (DS_PREFIX_OPCODE))
4091 return NULL;
4092 l += 3;
4093 }
4094 else if (l[2] == 'n')
4095 {
4096 if (!add_prefix (CS_PREFIX_OPCODE))
4097 return NULL;
4098 l += 3;
4099 }
4100 }
4101 }
4102 /* Any other comma loses. */
4103 if (*l == ',')
4104 {
4105 as_bad (_("invalid character %s in mnemonic"),
4106 output_invalid (*l));
4107 return NULL;
4108 }
252b5132 4109
29b0f896 4110 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4111 supported = 0;
4112 for (t = current_templates->start; t < current_templates->end; ++t)
4113 {
c0f3af97
L		 4114 supported |= cpu_flags_match (t);
4115 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4116 goto skip;
5c6af06e 4117 }
3629bb00 4118
c0f3af97 4119 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4120 {
4121 as_bad (flag_code == CODE_64BIT
4122 ? _("`%s' is not supported in 64-bit mode")
4123 : _("`%s' is only supported in 64-bit mode"),
4124 current_templates->start->name);
4125 return NULL;
4126 }
c0f3af97 4127 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4128 {
3629bb00 4129 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4130 current_templates->start->name,
41aacd83 4131 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4132 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4133 return NULL;
29b0f896 4134 }
3629bb00
L		 4135
4136skip:
4137 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4138 && (flag_code != CODE_16BIT))
29b0f896
AM		 4139 {
4140 as_warn (_("use .code16 to ensure correct addressing mode"));
4141 }
252b5132 4142
29b0f896
AM		 4143 return l;
4144}
252b5132 4145
29b0f896 4146static char *
e3bb37b5 4147parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4148{
4149 char *token_start;
3138f287 4150
29b0f896
AM		 4151 /* 1 if operand is pending after ','. */
4152 unsigned int expecting_operand = 0;
252b5132 4153
29b0f896
AM		 4154 /* Non-zero if operand parens not balanced. */
4155 unsigned int paren_not_balanced;
4156
4157 while (*l != END_OF_INSN)
4158 {
4159 /* Skip optional white space before operand. */
4160 if (is_space_char (*l))
4161 ++l;
d02603dc 4162 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4163 {
4164 as_bad (_("invalid character %s before operand %d"),
4165 output_invalid (*l),
4166 i.operands + 1);
4167 return NULL;
4168 }
d02603dc 4169 token_start = l; /* After white space. */
29b0f896
AM		 4170 paren_not_balanced = 0;
4171 while (paren_not_balanced || *l != ',')
4172 {
4173 if (*l == END_OF_INSN)
4174 {
4175 if (paren_not_balanced)
4176 {
4177 if (!intel_syntax)
4178 as_bad (_("unbalanced parenthesis in operand %d."),
4179 i.operands + 1);
4180 else
4181 as_bad (_("unbalanced brackets in operand %d."),
4182 i.operands + 1);
4183 return NULL;
4184 }
4185 else
4186 break; /* we are done */
4187 }
d02603dc 4188 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4189 {
4190 as_bad (_("invalid character %s in operand %d"),
4191 output_invalid (*l),
4192 i.operands + 1);
4193 return NULL;
4194 }
4195 if (!intel_syntax)
4196 {
4197 if (*l == '(')
4198 ++paren_not_balanced;
4199 if (*l == ')')
4200 --paren_not_balanced;
4201 }
4202 else
4203 {
4204 if (*l == '[')
4205 ++paren_not_balanced;
4206 if (*l == ']')
4207 --paren_not_balanced;
4208 }
4209 l++;
4210 }
4211 if (l != token_start)
4212 { /* Yes, we've read in another operand. */
4213 unsigned int operand_ok;
4214 this_operand = i.operands++;
4215 if (i.operands > MAX_OPERANDS)
4216 {
4217 as_bad (_("spurious operands; (%d operands/instruction max)"),
4218 MAX_OPERANDS);
4219 return NULL;
4220 }
9d46ce34 4221 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4222 /* Now parse operand adding info to 'i' as we go along. */
4223 END_STRING_AND_SAVE (l);
4224
4225 if (intel_syntax)
4226 operand_ok =
4227 i386_intel_operand (token_start,
4228 intel_float_operand (mnemonic));
4229 else
a7619375 4230 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4231
4232 RESTORE_END_STRING (l);
4233 if (!operand_ok)
4234 return NULL;
4235 }
4236 else
4237 {
4238 if (expecting_operand)
4239 {
4240 expecting_operand_after_comma:
4241 as_bad (_("expecting operand after ','; got nothing"));
4242 return NULL;
4243 }
4244 if (*l == ',')
4245 {
4246 as_bad (_("expecting operand before ','; got nothing"));
4247 return NULL;
4248 }
4249 }
7f3f1ea2 4250
29b0f896
AM		 4251 /* Now *l must be either ',' or END_OF_INSN. */
4252 if (*l == ',')
4253 {
4254 if (*++l == END_OF_INSN)
4255 {
4256 /* Just skip it, if it's \n complain. */
4257 goto expecting_operand_after_comma;
4258 }
4259 expecting_operand = 1;
4260 }
4261 }
4262 return l;
4263}
7f3f1ea2 4264
050dfa73 4265static void
4d456e3d 4266swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4267{
4268 union i386_op temp_op;
40fb9820 4269 i386_operand_type temp_type;
050dfa73 4270 enum bfd_reloc_code_real temp_reloc;
4eed87de 4271
050dfa73
MM		 4272 temp_type = i.types[xchg2];
4273 i.types[xchg2] = i.types[xchg1];
4274 i.types[xchg1] = temp_type;
4275 temp_op = i.op[xchg2];
4276 i.op[xchg2] = i.op[xchg1];
4277 i.op[xchg1] = temp_op;
4278 temp_reloc = i.reloc[xchg2];
4279 i.reloc[xchg2] = i.reloc[xchg1];
4280 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4281
4282 if (i.mask)
4283 {
4284 if (i.mask->operand == xchg1)
4285 i.mask->operand = xchg2;
4286 else if (i.mask->operand == xchg2)
4287 i.mask->operand = xchg1;
4288 }
4289 if (i.broadcast)
4290 {
4291 if (i.broadcast->operand == xchg1)
4292 i.broadcast->operand = xchg2;
4293 else if (i.broadcast->operand == xchg2)
4294 i.broadcast->operand = xchg1;
4295 }
4296 if (i.rounding)
4297 {
4298 if (i.rounding->operand == xchg1)
4299 i.rounding->operand = xchg2;
4300 else if (i.rounding->operand == xchg2)
4301 i.rounding->operand = xchg1;
4302 }
050dfa73
MM		 4303}
4304
29b0f896 4305static void
e3bb37b5 4306swap_operands (void)
29b0f896 4307{
b7c61d9a 4308 switch (i.operands)
050dfa73 4309 {
c0f3af97 4310 case 5:
b7c61d9a 4311 case 4:
4d456e3d 4312 swap_2_operands (1, i.operands - 2);
1a0670f3 4313 /* Fall through. */
b7c61d9a
L		 4314 case 3:
4315 case 2:
4d456e3d 4316 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4317 break;
4318 default:
4319 abort ();
29b0f896 4320 }
29b0f896
AM		 4321
4322 if (i.mem_operands == 2)
4323 {
4324 const seg_entry *temp_seg;
4325 temp_seg = i.seg[0];
4326 i.seg[0] = i.seg[1];
4327 i.seg[1] = temp_seg;
4328 }
4329}
252b5132 4330
29b0f896
AM		 4331/* Try to ensure constant immediates are represented in the smallest
4332 opcode possible. */
4333static void
e3bb37b5 4334optimize_imm (void)
29b0f896
AM		 4335{
4336 char guess_suffix = 0;
4337 int op;
252b5132 4338
29b0f896
AM		 4339 if (i.suffix)
4340 guess_suffix = i.suffix;
4341 else if (i.reg_operands)
4342 {
4343 /* Figure out a suffix from the last register operand specified.
4344 We can't do this properly yet, ie. excluding InOutPortReg,
4345 but the following works for instructions with immediates.
4346 In any case, we can't set i.suffix yet. */
4347 for (op = i.operands; --op >= 0;)
40fb9820 4348 if (i.types[op].bitfield.reg8)
7ab9ffdd 4349 {
40fb9820
L		 4350 guess_suffix = BYTE_MNEM_SUFFIX;
4351 break;
4352 }
4353 else if (i.types[op].bitfield.reg16)
252b5132 4354 {
40fb9820
L		 4355 guess_suffix = WORD_MNEM_SUFFIX;
4356 break;
4357 }
4358 else if (i.types[op].bitfield.reg32)
4359 {
4360 guess_suffix = LONG_MNEM_SUFFIX;
4361 break;
4362 }
4363 else if (i.types[op].bitfield.reg64)
4364 {
4365 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4366 break;
252b5132 4367 }
29b0f896
AM		 4368 }
4369 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4370 guess_suffix = WORD_MNEM_SUFFIX;
4371
4372 for (op = i.operands; --op >= 0;)
40fb9820 4373 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4374 {
4375 switch (i.op[op].imms->X_op)
252b5132 4376 {
29b0f896
AM		 4377 case O_constant:
4378 /* If a suffix is given, this operand may be shortened. */
4379 switch (guess_suffix)
252b5132 4380 {
29b0f896 4381 case LONG_MNEM_SUFFIX:
40fb9820
L		 4382 i.types[op].bitfield.imm32 = 1;
4383 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4384 break;
4385 case WORD_MNEM_SUFFIX:
40fb9820
L		 4386 i.types[op].bitfield.imm16 = 1;
4387 i.types[op].bitfield.imm32 = 1;
4388 i.types[op].bitfield.imm32s = 1;
4389 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4390 break;
4391 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4392 i.types[op].bitfield.imm8 = 1;
4393 i.types[op].bitfield.imm8s = 1;
4394 i.types[op].bitfield.imm16 = 1;
4395 i.types[op].bitfield.imm32 = 1;
4396 i.types[op].bitfield.imm32s = 1;
4397 i.types[op].bitfield.imm64 = 1;
29b0f896 4398 break;
252b5132 4399 }
252b5132 4400
29b0f896
AM		 4401 /* If this operand is at most 16 bits, convert it
4402 to a signed 16 bit number before trying to see
4403 whether it will fit in an even smaller size.
4404 This allows a 16-bit operand such as $0xffe0 to
4405 be recognised as within Imm8S range. */
40fb9820 4406 if ((i.types[op].bitfield.imm16)
29b0f896 4407 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4408 {
29b0f896
AM		 4409 i.op[op].imms->X_add_number =
4410 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4411 }
a28def75
L		 4412#ifdef BFD64
4413 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4414 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4415 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4416 == 0))
4417 {
4418 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4419 ^ ((offsetT) 1 << 31))
4420 - ((offsetT) 1 << 31));
4421 }
a28def75 4422#endif
40fb9820 4423 i.types[op]
c6fb90c8
L		 4424 = operand_type_or (i.types[op],
4425 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4426
29b0f896
AM		 4427 /* We must avoid matching of Imm32 templates when 64bit
4428 only immediate is available. */
4429 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4430 i.types[op].bitfield.imm32 = 0;
29b0f896 4431 break;
252b5132 4432
29b0f896
AM		 4433 case O_absent:
4434 case O_register:
4435 abort ();
4436
4437 /* Symbols and expressions. */
4438 default:
9cd96992
JB		 4439 /* Convert symbolic operand to proper sizes for matching, but don't
4440 prevent matching a set of insns that only supports sizes other
4441 than those matching the insn suffix. */
4442 {
40fb9820 4443 i386_operand_type mask, allowed;
d3ce72d0 4444 const insn_template *t;
9cd96992 4445
0dfbf9d7
L		 4446 operand_type_set (&mask, 0);
4447 operand_type_set (&allowed, 0);
40fb9820 4448
4eed87de
AM		 4449 for (t = current_templates->start;
4450 t < current_templates->end;
4451 ++t)
c6fb90c8
L		 4452 allowed = operand_type_or (allowed,
4453 t->operand_types[op]);
9cd96992
JB		 4454 switch (guess_suffix)
4455 {
4456 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4457 mask.bitfield.imm64 = 1;
4458 mask.bitfield.imm32s = 1;
9cd96992
JB		 4459 break;
4460 case LONG_MNEM_SUFFIX:
40fb9820 4461 mask.bitfield.imm32 = 1;
9cd96992
JB		 4462 break;
4463 case WORD_MNEM_SUFFIX:
40fb9820 4464 mask.bitfield.imm16 = 1;
9cd96992
JB		 4465 break;
4466 case BYTE_MNEM_SUFFIX:
40fb9820 4467 mask.bitfield.imm8 = 1;
9cd96992
JB		 4468 break;
4469 default:
9cd96992
JB		 4470 break;
4471 }
c6fb90c8 4472 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4473 if (!operand_type_all_zero (&allowed))
c6fb90c8 4474 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4475 }
29b0f896 4476 break;
252b5132 4477 }
29b0f896
AM		 4478 }
4479}
47926f60 4480
29b0f896
AM		 4481/* Try to use the smallest displacement type too. */
4482static void
e3bb37b5 4483optimize_disp (void)
29b0f896
AM		 4484{
4485 int op;
3e73aa7c 4486
29b0f896 4487 for (op = i.operands; --op >= 0;)
40fb9820 4488 if (operand_type_check (i.types[op], disp))
252b5132 4489 {
b300c311 4490 if (i.op[op].disps->X_op == O_constant)
252b5132 4491 {
91d6fa6a 4492 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4493
40fb9820 4494 if (i.types[op].bitfield.disp16
91d6fa6a 4495 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4496 {
4497 /* If this operand is at most 16 bits, convert
4498 to a signed 16 bit number and don't use 64bit
4499 displacement. */
91d6fa6a 4500 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4501 i.types[op].bitfield.disp64 = 0;
b300c311 4502 }
a28def75
L		 4503#ifdef BFD64
4504 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4505 if (i.types[op].bitfield.disp32
91d6fa6a 4506 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4507 {
4508 /* If this operand is at most 32 bits, convert
4509 to a signed 32 bit number and don't use 64bit
4510 displacement. */
91d6fa6a
NC		 4511 op_disp &= (((offsetT) 2 << 31) - 1);
4512 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4513 i.types[op].bitfield.disp64 = 0;
b300c311 4514 }
a28def75 4515#endif
91d6fa6a 4516 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4517 {
40fb9820
L		 4518 i.types[op].bitfield.disp8 = 0;
4519 i.types[op].bitfield.disp16 = 0;
4520 i.types[op].bitfield.disp32 = 0;
4521 i.types[op].bitfield.disp32s = 0;
4522 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4523 i.op[op].disps = 0;
4524 i.disp_operands--;
4525 }
4526 else if (flag_code == CODE_64BIT)
4527 {
91d6fa6a 4528 if (fits_in_signed_long (op_disp))
28a9d8f5 4529 {
40fb9820
L		 4530 i.types[op].bitfield.disp64 = 0;
4531 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4532 }
0e1147d9 4533 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4534 && fits_in_unsigned_long (op_disp))
40fb9820 4535 i.types[op].bitfield.disp32 = 1;
b300c311 4536 }
40fb9820
L		 4537 if ((i.types[op].bitfield.disp32
4538 || i.types[op].bitfield.disp32s
4539 || i.types[op].bitfield.disp16)
91d6fa6a 4540 && fits_in_signed_byte (op_disp))
40fb9820 4541 i.types[op].bitfield.disp8 = 1;
252b5132 4542 }
67a4f2b7
AO		 4543 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4544 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4545 {
4546 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4547 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4548 i.types[op].bitfield.disp8 = 0;
4549 i.types[op].bitfield.disp16 = 0;
4550 i.types[op].bitfield.disp32 = 0;
4551 i.types[op].bitfield.disp32s = 0;
4552 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4553 }
4554 else
b300c311 4555 /* We only support 64bit displacement on constants. */
40fb9820 4556 i.types[op].bitfield.disp64 = 0;
252b5132 4557 }
29b0f896
AM		 4558}
4559
6c30d220
L		 4560/* Check if operands are valid for the instruction. */
4561
4562static int
4563check_VecOperands (const insn_template *t)
4564{
43234a1e
L		 4565 unsigned int op;
4566
6c30d220
L		 4567 /* Without VSIB byte, we can't have a vector register for index. */
4568 if (!t->opcode_modifier.vecsib
4569 && i.index_reg
4570 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4571 || i.index_reg->reg_type.bitfield.regymm
4572 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4573 {
4574 i.error = unsupported_vector_index_register;
4575 return 1;
4576 }
4577
ad8ecc81
MZ		 4578 /* Check if default mask is allowed. */
4579 if (t->opcode_modifier.nodefmask
4580 && (!i.mask || i.mask->mask->reg_num == 0))
4581 {
4582 i.error = no_default_mask;
4583 return 1;
4584 }
4585
7bab8ab5
JB		 4586 /* For VSIB byte, we need a vector register for index, and all vector
4587 registers must be distinct. */
4588 if (t->opcode_modifier.vecsib)
4589 {
4590 if (!i.index_reg
6c30d220
L		 4591 || !((t->opcode_modifier.vecsib == VecSIB128
4592 && i.index_reg->reg_type.bitfield.regxmm)
4593 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4594 && i.index_reg->reg_type.bitfield.regymm)
4595 || (t->opcode_modifier.vecsib == VecSIB512
4596 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4597 {
4598 i.error = invalid_vsib_address;
4599 return 1;
4600 }
4601
43234a1e
L		 4602 gas_assert (i.reg_operands == 2 || i.mask);
4603 if (i.reg_operands == 2 && !i.mask)
4604 {
4605 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4606 || i.types[0].bitfield.regymm);
43234a1e 4607 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4608 || i.types[2].bitfield.regymm);
43234a1e
L		 4609 if (operand_check == check_none)
4610 return 0;
4611 if (register_number (i.op[0].regs)
4612 != register_number (i.index_reg)
4613 && register_number (i.op[2].regs)
4614 != register_number (i.index_reg)
4615 && register_number (i.op[0].regs)
4616 != register_number (i.op[2].regs))
4617 return 0;
4618 if (operand_check == check_error)
4619 {
4620 i.error = invalid_vector_register_set;
4621 return 1;
4622 }
4623 as_warn (_("mask, index, and destination registers should be distinct"));
4624 }
8444f82a
MZ		 4625 else if (i.reg_operands == 1 && i.mask)
4626 {
4627 if ((i.types[1].bitfield.regymm
4628 || i.types[1].bitfield.regzmm)
4629 && (register_number (i.op[1].regs)
4630 == register_number (i.index_reg)))
4631 {
4632 if (operand_check == check_error)
4633 {
4634 i.error = invalid_vector_register_set;
4635 return 1;
4636 }
4637 if (operand_check != check_none)
4638 as_warn (_("index and destination registers should be distinct"));
4639 }
4640 }
43234a1e 4641 }
7bab8ab5 4642
43234a1e
L		 4643 /* Check if broadcast is supported by the instruction and is applied
4644 to the memory operand. */
4645 if (i.broadcast)
4646 {
4647 int broadcasted_opnd_size;
4648
4649 /* Check if specified broadcast is supported in this instruction,
4650 and it's applied to memory operand of DWORD or QWORD type,
4651 depending on VecESize. */
4652 if (i.broadcast->type != t->opcode_modifier.broadcast
4653 || !i.types[i.broadcast->operand].bitfield.mem
4654 || (t->opcode_modifier.vecesize == 0
4655 && !i.types[i.broadcast->operand].bitfield.dword
4656 && !i.types[i.broadcast->operand].bitfield.unspecified)
4657 || (t->opcode_modifier.vecesize == 1
4658 && !i.types[i.broadcast->operand].bitfield.qword
4659 && !i.types[i.broadcast->operand].bitfield.unspecified))
4660 goto bad_broadcast;
4661
4662 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4663 if (i.broadcast->type == BROADCAST_1TO16)
4664 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4665 else if (i.broadcast->type == BROADCAST_1TO8)
4666 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4667 else if (i.broadcast->type == BROADCAST_1TO4)
4668 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4669 else if (i.broadcast->type == BROADCAST_1TO2)
4670 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4671 else
4672 goto bad_broadcast;
4673
4674 if ((broadcasted_opnd_size == 256
4675 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4676 || (broadcasted_opnd_size == 512
4677 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4678 {
4679 bad_broadcast:
4680 i.error = unsupported_broadcast;
4681 return 1;
4682 }
4683 }
4684 /* If broadcast is supported in this instruction, we need to check if
4685 operand of one-element size isn't specified without broadcast. */
4686 else if (t->opcode_modifier.broadcast && i.mem_operands)
4687 {
4688 /* Find memory operand. */
4689 for (op = 0; op < i.operands; op++)
4690 if (operand_type_check (i.types[op], anymem))
4691 break;
4692 gas_assert (op < i.operands);
4693 /* Check size of the memory operand. */
4694 if ((t->opcode_modifier.vecesize == 0
4695 && i.types[op].bitfield.dword)
4696 || (t->opcode_modifier.vecesize == 1
4697 && i.types[op].bitfield.qword))
4698 {
4699 i.error = broadcast_needed;
4700 return 1;
4701 }
4702 }
4703
4704 /* Check if requested masking is supported. */
4705 if (i.mask
4706 && (!t->opcode_modifier.masking
4707 || (i.mask->zeroing
4708 && t->opcode_modifier.masking == MERGING_MASKING)))
4709 {
4710 i.error = unsupported_masking;
4711 return 1;
4712 }
4713
4714 /* Check if masking is applied to dest operand. */
4715 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4716 {
4717 i.error = mask_not_on_destination;
4718 return 1;
4719 }
4720
43234a1e
L		 4721 /* Check RC/SAE. */
4722 if (i.rounding)
4723 {
4724 if ((i.rounding->type != saeonly
4725 && !t->opcode_modifier.staticrounding)
4726 || (i.rounding->type == saeonly
4727 && (t->opcode_modifier.staticrounding
4728 || !t->opcode_modifier.sae)))
4729 {
4730 i.error = unsupported_rc_sae;
4731 return 1;
4732 }
4733 /* If the instruction has several immediate operands and one of
4734 them is rounding, the rounding operand should be the last
4735 immediate operand. */
4736 if (i.imm_operands > 1
4737 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4738 {
43234a1e 4739 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4740 return 1;
4741 }
6c30d220
L		 4742 }
4743
43234a1e
L		 4744 /* Check vector Disp8 operand. */
4745 if (t->opcode_modifier.disp8memshift)
4746 {
4747 if (i.broadcast)
4748 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4749 else
4750 i.memshift = t->opcode_modifier.disp8memshift;
4751
4752 for (op = 0; op < i.operands; op++)
4753 if (operand_type_check (i.types[op], disp)
4754 && i.op[op].disps->X_op == O_constant)
4755 {
4756 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4757 int vec_disp8_ok
4758 = (i.disp_encoding != disp_encoding_32bit
4759 && fits_in_vec_disp8 (value));
43234a1e
L		 4760 if (t->operand_types [op].bitfield.vec_disp8)
4761 {
4762 if (vec_disp8_ok)
4763 i.types[op].bitfield.vec_disp8 = 1;
4764 else
4765 {
4766 /* Vector insn can only have Vec_Disp8/Disp32 in
4767 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4768 mode. */
4769 i.types[op].bitfield.disp8 = 0;
4770 if (flag_code != CODE_16BIT)
4771 i.types[op].bitfield.disp16 = 0;
4772 }
4773 }
4774 else if (flag_code != CODE_16BIT)
4775 {
4776 /* One form of this instruction supports vector Disp8.
4777 Try vector Disp8 if we need to use Disp32. */
4778 if (vec_disp8_ok && !fits_in_signed_byte (value))
4779 {
4780 i.error = try_vector_disp8;
4781 return 1;
4782 }
4783 }
4784 }
4785 }
4786 else
4787 i.memshift = -1;
4788
6c30d220
L		 4789 return 0;
4790}
4791
43f3e2ee 4792/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4793 operand types. */
4794
4795static int
4796VEX_check_operands (const insn_template *t)
4797{
86fa6981 4798 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4799 {
86fa6981
L		 4800 /* This instruction must be encoded with EVEX prefix. */
4801 if (!t->opcode_modifier.evex)
4802 {
4803 i.error = unsupported;
4804 return 1;
4805 }
4806 return 0;
43234a1e
L		 4807 }
4808
a683cc34 4809 if (!t->opcode_modifier.vex)
86fa6981
L		 4810 {
4811 /* This instruction template doesn't have VEX prefix. */
4812 if (i.vec_encoding != vex_encoding_default)
4813 {
4814 i.error = unsupported;
4815 return 1;
4816 }
4817 return 0;
4818 }
a683cc34
SP		 4819
4820 /* Only check VEX_Imm4, which must be the first operand. */
4821 if (t->operand_types[0].bitfield.vec_imm4)
4822 {
4823 if (i.op[0].imms->X_op != O_constant
4824 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4825 {
a65babc9 4826 i.error = bad_imm4;
891edac4
L		 4827 return 1;
4828 }
a683cc34
SP		 4829
4830 /* Turn off Imm8 so that update_imm won't complain. */
4831 i.types[0] = vec_imm4;
4832 }
4833
4834 return 0;
4835}
4836
d3ce72d0 4837static const insn_template *
83b16ac6 4838match_template (char mnem_suffix)
29b0f896
AM		 4839{
4840 /* Points to template once we've found it. */
d3ce72d0 4841 const insn_template *t;
40fb9820 4842 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4843 i386_operand_type overlap4;
29b0f896 4844 unsigned int found_reverse_match;
83b16ac6 4845 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4846 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4847 int addr_prefix_disp;
a5c311ca 4848 unsigned int j;
3629bb00 4849 unsigned int found_cpu_match;
45664ddb 4850 unsigned int check_register;
5614d22c 4851 enum i386_error specific_error = 0;
29b0f896 4852
c0f3af97
L		 4853#if MAX_OPERANDS != 5
4854# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4855#endif
4856
29b0f896 4857 found_reverse_match = 0;
539e75ad 4858 addr_prefix_disp = -1;
40fb9820
L		 4859
4860 memset (&suffix_check, 0, sizeof (suffix_check));
4861 if (i.suffix == BYTE_MNEM_SUFFIX)
4862 suffix_check.no_bsuf = 1;
4863 else if (i.suffix == WORD_MNEM_SUFFIX)
4864 suffix_check.no_wsuf = 1;
4865 else if (i.suffix == SHORT_MNEM_SUFFIX)
4866 suffix_check.no_ssuf = 1;
4867 else if (i.suffix == LONG_MNEM_SUFFIX)
4868 suffix_check.no_lsuf = 1;
4869 else if (i.suffix == QWORD_MNEM_SUFFIX)
4870 suffix_check.no_qsuf = 1;
4871 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4872 suffix_check.no_ldsuf = 1;
29b0f896 4873
83b16ac6
JB		 4874 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4875 if (intel_syntax)
4876 {
4877 switch (mnem_suffix)
4878 {
4879 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4880 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4881 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4882 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4883 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4884 }
4885 }
4886
01559ecc
L		 4887 /* Must have right number of operands. */
4888 i.error = number_of_operands_mismatch;
4889
45aa61fe 4890 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4891 {
539e75ad
L		 4892 addr_prefix_disp = -1;
4893
29b0f896
AM		 4894 if (i.operands != t->operands)
4895 continue;
4896
50aecf8c 4897 /* Check processor support. */
a65babc9 4898 i.error = unsupported;
c0f3af97
L		 4899 found_cpu_match = (cpu_flags_match (t)
4900 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4901 if (!found_cpu_match)
4902 continue;
4903
e1d4d893 4904 /* Check old gcc support. */
a65babc9 4905 i.error = old_gcc_only;
e1d4d893
L		 4906 if (!old_gcc && t->opcode_modifier.oldgcc)
4907 continue;
4908
4909 /* Check AT&T mnemonic. */
a65babc9 4910 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4911 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4912 continue;
4913
e92bae62 4914 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4915 i.error = unsupported_syntax;
5c07affc 4916 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4917 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4918 || (intel64 && t->opcode_modifier.amd64)
4919 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4920 continue;
4921
20592a94 4922 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4923 i.error = invalid_instruction_suffix;
567e4e96
L		 4924 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4925 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4926 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4927 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4928 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4929 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4930 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4931 continue;
83b16ac6
JB		 4932 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4933 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4934 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4935 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4936 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4937 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4938 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4939 continue;
29b0f896 4940
5c07affc 4941 if (!operand_size_match (t))
7d5e4556 4942 continue;
539e75ad 4943
5c07affc
L		 4944 for (j = 0; j < MAX_OPERANDS; j++)
4945 operand_types[j] = t->operand_types[j];
4946
45aa61fe
AM		 4947 /* In general, don't allow 64-bit operands in 32-bit mode. */
4948 if (i.suffix == QWORD_MNEM_SUFFIX
4949 && flag_code != CODE_64BIT
4950 && (intel_syntax
40fb9820 4951 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4952 && !intel_float_operand (t->name))
4953 : intel_float_operand (t->name) != 2)
40fb9820 4954 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4955 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4956 && !operand_types[0].bitfield.regymm
4957 && !operand_types[0].bitfield.regzmm)
40fb9820 4958 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4959 && operand_types[t->operands > 1].bitfield.regxmm
4960 && operand_types[t->operands > 1].bitfield.regymm
4961 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4962 && (t->base_opcode != 0x0fc7
4963 || t->extension_opcode != 1 /* cmpxchg8b */))
4964 continue;
4965
192dc9c6
JB		 4966 /* In general, don't allow 32-bit operands on pre-386. */
4967 else if (i.suffix == LONG_MNEM_SUFFIX
4968 && !cpu_arch_flags.bitfield.cpui386
4969 && (intel_syntax
4970 ? (!t->opcode_modifier.ignoresize
4971 && !intel_float_operand (t->name))
4972 : intel_float_operand (t->name) != 2)
4973 && ((!operand_types[0].bitfield.regmmx
4974 && !operand_types[0].bitfield.regxmm)
4975 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4976 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4977 continue;
4978
29b0f896 4979 /* Do not verify operands when there are none. */
50aecf8c 4980 else
29b0f896 4981 {
c6fb90c8 4982 if (!t->operands)
2dbab7d5
L		 4983 /* We've found a match; break out of loop. */
4984 break;
29b0f896 4985 }
252b5132 4986
539e75ad
L		 4987 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4988 into Disp32/Disp16/Disp32 operand. */
4989 if (i.prefix[ADDR_PREFIX] != 0)
4990 {
40fb9820 4991 /* There should be only one Disp operand. */
539e75ad
L		 4992 switch (flag_code)
4993 {
4994 case CODE_16BIT:
40fb9820
L		 4995 for (j = 0; j < MAX_OPERANDS; j++)
4996 {
4997 if (operand_types[j].bitfield.disp16)
4998 {
4999 addr_prefix_disp = j;
5000 operand_types[j].bitfield.disp32 = 1;
5001 operand_types[j].bitfield.disp16 = 0;
5002 break;
5003 }
5004 }
539e75ad
L		 5005 break;
5006 case CODE_32BIT:
40fb9820
L		 5007 for (j = 0; j < MAX_OPERANDS; j++)
5008 {
5009 if (operand_types[j].bitfield.disp32)
5010 {
5011 addr_prefix_disp = j;
5012 operand_types[j].bitfield.disp32 = 0;
5013 operand_types[j].bitfield.disp16 = 1;
5014 break;
5015 }
5016 }
539e75ad
L		 5017 break;
5018 case CODE_64BIT:
40fb9820
L		 5019 for (j = 0; j < MAX_OPERANDS; j++)
5020 {
5021 if (operand_types[j].bitfield.disp64)
5022 {
5023 addr_prefix_disp = j;
5024 operand_types[j].bitfield.disp64 = 0;
5025 operand_types[j].bitfield.disp32 = 1;
5026 break;
5027 }
5028 }
539e75ad
L		 5029 break;
5030 }
539e75ad
L		 5031 }
5032
02a86693
L		 5033 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5034 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5035 continue;
5036
56ffb741
L		 5037 /* We check register size if needed. */
5038 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5039 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5040 switch (t->operands)
5041 {
5042 case 1:
40fb9820 5043 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5044 continue;
5045 break;
5046 case 2:
33eaf5de 5047 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5048 only in 32bit mode and we can use opcode 0x90. In 64bit
5049 mode, we can't use 0x90 for xchg %eax, %eax since it should
5050 zero-extend %eax to %rax. */
5051 if (flag_code == CODE_64BIT
5052 && t->base_opcode == 0x90
0dfbf9d7
L		 5053 && operand_type_equal (&i.types [0], &acc32)
5054 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5055 continue;
86fa6981
L		 5056 /* If we want store form, we reverse direction of operands. */
5057 if (i.dir_encoding == dir_encoding_store
5058 && t->opcode_modifier.d)
5059 goto check_reverse;
1a0670f3 5060 /* Fall through. */
b6169b20 5061
29b0f896 5062 case 3:
86fa6981
L		 5063 /* If we want store form, we skip the current load. */
5064 if (i.dir_encoding == dir_encoding_store
5065 && i.mem_operands == 0
5066 && t->opcode_modifier.load)
fa99fab2 5067 continue;
1a0670f3 5068 /* Fall through. */
f48ff2ae 5069 case 4:
c0f3af97 5070 case 5:
c6fb90c8 5071 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5072 if (!operand_type_match (overlap0, i.types[0])
5073 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5074 || (check_register
5075 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 5076 operand_types[0],
5077 overlap1, i.types[1],
5078 operand_types[1])))
29b0f896
AM		 5079 {
5080 /* Check if other direction is valid ... */
40fb9820 5081 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5082 continue;
5083
b6169b20 5084check_reverse:
29b0f896 5085 /* Try reversing direction of operands. */
c6fb90c8
L		 5086 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5087 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5088 if (!operand_type_match (overlap0, i.types[0])
5089 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5090 || (check_register
5091 && !operand_type_register_match (overlap0,
5092 i.types[0],
5093 operand_types[1],
5094 overlap1,
5095 i.types[1],
5096 operand_types[0])))
29b0f896
AM		 5097 {
5098 /* Does not match either direction. */
5099 continue;
5100 }
5101 /* found_reverse_match holds which of D or FloatDR
5102 we've found. */
40fb9820 5103 if (t->opcode_modifier.d)
8a2ed489 5104 found_reverse_match = Opcode_D;
40fb9820 5105 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5106 found_reverse_match = Opcode_FloatD;
5107 else
5108 found_reverse_match = 0;
40fb9820 5109 if (t->opcode_modifier.floatr)
8a2ed489 5110 found_reverse_match |= Opcode_FloatR;
29b0f896 5111 }
f48ff2ae 5112 else
29b0f896 5113 {
f48ff2ae 5114 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5115 switch (t->operands)
5116 {
c0f3af97
L		 5117 case 5:
5118 overlap4 = operand_type_and (i.types[4],
5119 operand_types[4]);
1a0670f3 5120 /* Fall through. */
d1cbb4db 5121 case 4:
c6fb90c8
L		 5122 overlap3 = operand_type_and (i.types[3],
5123 operand_types[3]);
1a0670f3 5124 /* Fall through. */
d1cbb4db 5125 case 3:
c6fb90c8
L		 5126 overlap2 = operand_type_and (i.types[2],
5127 operand_types[2]);
d1cbb4db
L		 5128 break;
5129 }
29b0f896 5130
f48ff2ae
L		 5131 switch (t->operands)
5132 {
c0f3af97
L		 5133 case 5:
5134 if (!operand_type_match (overlap4, i.types[4])
5135 || !operand_type_register_match (overlap3,
5136 i.types[3],
5137 operand_types[3],
5138 overlap4,
5139 i.types[4],
5140 operand_types[4]))
5141 continue;
1a0670f3 5142 /* Fall through. */
f48ff2ae 5143 case 4:
40fb9820 5144 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5145 || (check_register
5146 && !operand_type_register_match (overlap2,
5147 i.types[2],
5148 operand_types[2],
5149 overlap3,
5150 i.types[3],
5151 operand_types[3])))
f48ff2ae 5152 continue;
1a0670f3 5153 /* Fall through. */
f48ff2ae
L		 5154 case 3:
5155 /* Here we make use of the fact that there are no
5156 reverse match 3 operand instructions, and all 3
5157 operand instructions only need to be checked for
5158 register consistency between operands 2 and 3. */
40fb9820 5159 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5160 || (check_register
5161 && !operand_type_register_match (overlap1,
5162 i.types[1],
5163 operand_types[1],
5164 overlap2,
5165 i.types[2],
5166 operand_types[2])))
f48ff2ae
L		 5167 continue;
5168 break;
5169 }
29b0f896 5170 }
f48ff2ae 5171 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5172 slip through to break. */
5173 }
3629bb00 5174 if (!found_cpu_match)
29b0f896
AM		 5175 {
5176 found_reverse_match = 0;
5177 continue;
5178 }
c0f3af97 5179
5614d22c
JB		 5180 /* Check if vector and VEX operands are valid. */
5181 if (check_VecOperands (t) || VEX_check_operands (t))
5182 {
5183 specific_error = i.error;
5184 continue;
5185 }
a683cc34 5186
29b0f896
AM		 5187 /* We've found a match; break out of loop. */
5188 break;
5189 }
5190
5191 if (t == current_templates->end)
5192 {
5193 /* We found no match. */
a65babc9 5194 const char *err_msg;
5614d22c 5195 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5196 {
5197 default:
5198 abort ();
86e026a4 5199 case operand_size_mismatch:
a65babc9
L		 5200 err_msg = _("operand size mismatch");
5201 break;
5202 case operand_type_mismatch:
5203 err_msg = _("operand type mismatch");
5204 break;
5205 case register_type_mismatch:
5206 err_msg = _("register type mismatch");
5207 break;
5208 case number_of_operands_mismatch:
5209 err_msg = _("number of operands mismatch");
5210 break;
5211 case invalid_instruction_suffix:
5212 err_msg = _("invalid instruction suffix");
5213 break;
5214 case bad_imm4:
4a2608e3 5215 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5216 break;
5217 case old_gcc_only:
5218 err_msg = _("only supported with old gcc");
5219 break;
5220 case unsupported_with_intel_mnemonic:
5221 err_msg = _("unsupported with Intel mnemonic");
5222 break;
5223 case unsupported_syntax:
5224 err_msg = _("unsupported syntax");
5225 break;
5226 case unsupported:
35262a23 5227 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5228 current_templates->start->name);
5229 return NULL;
6c30d220
L		 5230 case invalid_vsib_address:
5231 err_msg = _("invalid VSIB address");
5232 break;
7bab8ab5
JB		 5233 case invalid_vector_register_set:
5234 err_msg = _("mask, index, and destination registers must be distinct");
5235 break;
6c30d220
L		 5236 case unsupported_vector_index_register:
5237 err_msg = _("unsupported vector index register");
5238 break;
43234a1e
L		 5239 case unsupported_broadcast:
5240 err_msg = _("unsupported broadcast");
5241 break;
5242 case broadcast_not_on_src_operand:
5243 err_msg = _("broadcast not on source memory operand");
5244 break;
5245 case broadcast_needed:
5246 err_msg = _("broadcast is needed for operand of such type");
5247 break;
5248 case unsupported_masking:
5249 err_msg = _("unsupported masking");
5250 break;
5251 case mask_not_on_destination:
5252 err_msg = _("mask not on destination operand");
5253 break;
5254 case no_default_mask:
5255 err_msg = _("default mask isn't allowed");
5256 break;
5257 case unsupported_rc_sae:
5258 err_msg = _("unsupported static rounding/sae");
5259 break;
5260 case rc_sae_operand_not_last_imm:
5261 if (intel_syntax)
5262 err_msg = _("RC/SAE operand must precede immediate operands");
5263 else
5264 err_msg = _("RC/SAE operand must follow immediate operands");
5265 break;
5266 case invalid_register_operand:
5267 err_msg = _("invalid register operand");
5268 break;
a65babc9
L		 5269 }
5270 as_bad (_("%s for `%s'"), err_msg,
891edac4 5271 current_templates->start->name);
fa99fab2 5272 return NULL;
29b0f896 5273 }
252b5132 5274
29b0f896
AM		 5275 if (!quiet_warnings)
5276 {
5277 if (!intel_syntax
40fb9820
L		 5278 && (i.types[0].bitfield.jumpabsolute
5279 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5280 {
5281 as_warn (_("indirect %s without `*'"), t->name);
5282 }
5283
40fb9820
L		 5284 if (t->opcode_modifier.isprefix
5285 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5286 {
5287 /* Warn them that a data or address size prefix doesn't
5288 affect assembly of the next line of code. */
5289 as_warn (_("stand-alone `%s' prefix"), t->name);
5290 }
5291 }
5292
5293 /* Copy the template we found. */
5294 i.tm = *t;
539e75ad
L		 5295
5296 if (addr_prefix_disp != -1)
5297 i.tm.operand_types[addr_prefix_disp]
5298 = operand_types[addr_prefix_disp];
5299
29b0f896
AM		 5300 if (found_reverse_match)
5301 {
5302 /* If we found a reverse match we must alter the opcode
5303 direction bit. found_reverse_match holds bits to change
5304 (different for int & float insns). */
5305
5306 i.tm.base_opcode ^= found_reverse_match;
5307
539e75ad
L		 5308 i.tm.operand_types[0] = operand_types[1];
5309 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5310 }
5311
fa99fab2 5312 return t;
29b0f896
AM		 5313}
5314
5315static int
e3bb37b5 5316check_string (void)
29b0f896 5317{
40fb9820
L		 5318 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5319 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5320 {
5321 if (i.seg[0] != NULL && i.seg[0] != &es)
5322 {
a87af027 5323 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5324 i.tm.name,
a87af027
JB		 5325 mem_op + 1,
5326 register_prefix);
29b0f896
AM		 5327 return 0;
5328 }
5329 /* There's only ever one segment override allowed per instruction.
5330 This instruction possibly has a legal segment override on the
5331 second operand, so copy the segment to where non-string
5332 instructions store it, allowing common code. */
5333 i.seg[0] = i.seg[1];
5334 }
40fb9820 5335 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5336 {
5337 if (i.seg[1] != NULL && i.seg[1] != &es)
5338 {
a87af027 5339 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5340 i.tm.name,
a87af027
JB		 5341 mem_op + 2,
5342 register_prefix);
29b0f896
AM		 5343 return 0;
5344 }
5345 }
5346 return 1;
5347}
5348
5349static int
543613e9 5350process_suffix (void)
29b0f896
AM		 5351{
5352 /* If matched instruction specifies an explicit instruction mnemonic
5353 suffix, use it. */
40fb9820
L		 5354 if (i.tm.opcode_modifier.size16)
5355 i.suffix = WORD_MNEM_SUFFIX;
5356 else if (i.tm.opcode_modifier.size32)
5357 i.suffix = LONG_MNEM_SUFFIX;
5358 else if (i.tm.opcode_modifier.size64)
5359 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5360 else if (i.reg_operands)
5361 {
5362 /* If there's no instruction mnemonic suffix we try to invent one
5363 based on register operands. */
5364 if (!i.suffix)
5365 {
5366 /* We take i.suffix from the last register operand specified,
5367 Destination register type is more significant than source
381d071f
L		 5368 register type. crc32 in SSE4.2 prefers source register
5369 type. */
5370 if (i.tm.base_opcode == 0xf20f38f1)
5371 {
40fb9820
L		 5372 if (i.types[0].bitfield.reg16)
5373 i.suffix = WORD_MNEM_SUFFIX;
5374 else if (i.types[0].bitfield.reg32)
5375 i.suffix = LONG_MNEM_SUFFIX;
5376 else if (i.types[0].bitfield.reg64)
5377 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5378 }
9344ff29 5379 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5380 {
40fb9820 5381 if (i.types[0].bitfield.reg8)
20592a94
L		 5382 i.suffix = BYTE_MNEM_SUFFIX;
5383 }
381d071f
L		 5384
5385 if (!i.suffix)
5386 {
5387 int op;
5388
20592a94
L		 5389 if (i.tm.base_opcode == 0xf20f38f1
5390 || i.tm.base_opcode == 0xf20f38f0)
5391 {
5392 /* We have to know the operand size for crc32. */
5393 as_bad (_("ambiguous memory operand size for `%s`"),
5394 i.tm.name);
5395 return 0;
5396 }
5397
381d071f 5398 for (op = i.operands; --op >= 0;)
40fb9820 5399 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5400 {
40fb9820
L		 5401 if (i.types[op].bitfield.reg8)
5402 {
5403 i.suffix = BYTE_MNEM_SUFFIX;
5404 break;
5405 }
5406 else if (i.types[op].bitfield.reg16)
5407 {
5408 i.suffix = WORD_MNEM_SUFFIX;
5409 break;
5410 }
5411 else if (i.types[op].bitfield.reg32)
5412 {
5413 i.suffix = LONG_MNEM_SUFFIX;
5414 break;
5415 }
5416 else if (i.types[op].bitfield.reg64)
5417 {
5418 i.suffix = QWORD_MNEM_SUFFIX;
5419 break;
5420 }
381d071f
L		 5421 }
5422 }
29b0f896
AM		 5423 }
5424 else if (i.suffix == BYTE_MNEM_SUFFIX)
5425 {
2eb952a4
L		 5426 if (intel_syntax
5427 && i.tm.opcode_modifier.ignoresize
5428 && i.tm.opcode_modifier.no_bsuf)
5429 i.suffix = 0;
5430 else if (!check_byte_reg ())
29b0f896
AM		 5431 return 0;
5432 }
5433 else if (i.suffix == LONG_MNEM_SUFFIX)
5434 {
2eb952a4
L		 5435 if (intel_syntax
5436 && i.tm.opcode_modifier.ignoresize
5437 && i.tm.opcode_modifier.no_lsuf)
5438 i.suffix = 0;
5439 else if (!check_long_reg ())
29b0f896
AM		 5440 return 0;
5441 }
5442 else if (i.suffix == QWORD_MNEM_SUFFIX)
5443 {
955e1e6a
L		 5444 if (intel_syntax
5445 && i.tm.opcode_modifier.ignoresize
5446 && i.tm.opcode_modifier.no_qsuf)
5447 i.suffix = 0;
5448 else if (!check_qword_reg ())
29b0f896
AM		 5449 return 0;
5450 }
5451 else if (i.suffix == WORD_MNEM_SUFFIX)
5452 {
2eb952a4
L		 5453 if (intel_syntax
5454 && i.tm.opcode_modifier.ignoresize
5455 && i.tm.opcode_modifier.no_wsuf)
5456 i.suffix = 0;
5457 else if (!check_word_reg ())
29b0f896
AM		 5458 return 0;
5459 }
c0f3af97 5460 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5461 || i.suffix == YMMWORD_MNEM_SUFFIX
5462 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5463 {
43234a1e 5464 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5465 should check if it is a valid suffix. */
5466 }
40fb9820 5467 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5468 /* Do nothing if the instruction is going to ignore the prefix. */
5469 ;
5470 else
5471 abort ();
5472 }
40fb9820 5473 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5474 && !i.suffix
5475 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5476 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5477 {
5478 i.suffix = stackop_size;
5479 }
9306ca4a
JB		 5480 else if (intel_syntax
5481 && !i.suffix
40fb9820
L		 5482 && (i.tm.operand_types[0].bitfield.jumpabsolute
5483 || i.tm.opcode_modifier.jumpbyte
5484 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5485 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5486 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5487 {
5488 switch (flag_code)
5489 {
5490 case CODE_64BIT:
40fb9820 5491 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5492 {
5493 i.suffix = QWORD_MNEM_SUFFIX;
5494 break;
5495 }
1a0670f3 5496 /* Fall through. */
9306ca4a 5497 case CODE_32BIT:
40fb9820 5498 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5499 i.suffix = LONG_MNEM_SUFFIX;
5500 break;
5501 case CODE_16BIT:
40fb9820 5502 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5503 i.suffix = WORD_MNEM_SUFFIX;
5504 break;
5505 }
5506 }
252b5132 5507
9306ca4a 5508 if (!i.suffix)
29b0f896 5509 {
9306ca4a
JB		 5510 if (!intel_syntax)
5511 {
40fb9820 5512 if (i.tm.opcode_modifier.w)
9306ca4a 5513 {
4eed87de
AM		 5514 as_bad (_("no instruction mnemonic suffix given and "
5515 "no register operands; can't size instruction"));
9306ca4a
JB		 5516 return 0;
5517 }
5518 }
5519 else
5520 {
40fb9820 5521 unsigned int suffixes;
7ab9ffdd 5522
40fb9820
L		 5523 suffixes = !i.tm.opcode_modifier.no_bsuf;
5524 if (!i.tm.opcode_modifier.no_wsuf)
5525 suffixes |= 1 << 1;
5526 if (!i.tm.opcode_modifier.no_lsuf)
5527 suffixes |= 1 << 2;
fc4adea1 5528 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5529 suffixes |= 1 << 3;
5530 if (!i.tm.opcode_modifier.no_ssuf)
5531 suffixes |= 1 << 4;
5532 if (!i.tm.opcode_modifier.no_qsuf)
5533 suffixes |= 1 << 5;
5534
5535 /* There are more than suffix matches. */
5536 if (i.tm.opcode_modifier.w
9306ca4a 5537 || ((suffixes & (suffixes - 1))
40fb9820
L		 5538 && !i.tm.opcode_modifier.defaultsize
5539 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5540 {
5541 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5542 return 0;
5543 }
5544 }
29b0f896 5545 }
252b5132 5546
9306ca4a
JB		 5547 /* Change the opcode based on the operand size given by i.suffix;
5548 We don't need to change things for byte insns. */
5549
582d5edd
L		 5550 if (i.suffix
5551 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5552 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5553 && i.suffix != YMMWORD_MNEM_SUFFIX
5554 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5555 {
5556 /* It's not a byte, select word/dword operation. */
40fb9820 5557 if (i.tm.opcode_modifier.w)
29b0f896 5558 {
40fb9820 5559 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5560 i.tm.base_opcode |= 8;
5561 else
5562 i.tm.base_opcode |= 1;
5563 }
0f3f3d8b 5564
29b0f896
AM		 5565 /* Now select between word & dword operations via the operand
5566 size prefix, except for instructions that will ignore this
5567 prefix anyway. */
ca61edf2 5568 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5569 {
ca61edf2
L		 5570 /* The address size override prefix changes the size of the
5571 first operand. */
40fb9820
L		 5572 if ((flag_code == CODE_32BIT
5573 && i.op->regs[0].reg_type.bitfield.reg16)
5574 || (flag_code != CODE_32BIT
5575 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5576 if (!add_prefix (ADDR_PREFIX_OPCODE))
5577 return 0;
5578 }
5579 else if (i.suffix != QWORD_MNEM_SUFFIX
5580 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5581 && !i.tm.opcode_modifier.ignoresize
5582 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5583 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5584 || (flag_code == CODE_64BIT
40fb9820 5585 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5586 {
5587 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5588
40fb9820 5589 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5590 prefix = ADDR_PREFIX_OPCODE;
252b5132 5591
29b0f896
AM		 5592 if (!add_prefix (prefix))
5593 return 0;
24eab124 5594 }
252b5132 5595
29b0f896
AM		 5596 /* Set mode64 for an operand. */
5597 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5598 && flag_code == CODE_64BIT
40fb9820 5599 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5600 {
5601 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5602 need rex64. cmpxchg8b is also a special case. */
5603 if (! (i.operands == 2
5604 && i.tm.base_opcode == 0x90
5605 && i.tm.extension_opcode == None
0dfbf9d7
L		 5606 && operand_type_equal (&i.types [0], &acc64)
5607 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5608 && ! (i.operands == 1
5609 && i.tm.base_opcode == 0xfc7
5610 && i.tm.extension_opcode == 1
40fb9820
L		 5611 && !operand_type_check (i.types [0], reg)
5612 && operand_type_check (i.types [0], anymem)))
f6bee062 5613 i.rex |= REX_W;
46e883c5 5614 }
3e73aa7c 5615
29b0f896
AM		 5616 /* Size floating point instruction. */
5617 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5618 if (i.tm.opcode_modifier.floatmf)
543613e9 5619 i.tm.base_opcode ^= 4;
29b0f896 5620 }
7ecd2f8b 5621
29b0f896
AM		 5622 return 1;
5623}
3e73aa7c 5624
29b0f896 5625static int
543613e9 5626check_byte_reg (void)
29b0f896
AM		 5627{
5628 int op;
543613e9 5629
29b0f896
AM		 5630 for (op = i.operands; --op >= 0;)
5631 {
5632 /* If this is an eight bit register, it's OK. If it's the 16 or
5633 32 bit version of an eight bit register, we will just use the
5634 low portion, and that's OK too. */
40fb9820 5635 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5636 continue;
5637
5a819eb9
JB		 5638 /* I/O port address operands are OK too. */
5639 if (i.tm.operand_types[op].bitfield.inoutportreg)
5640 continue;
5641
9344ff29
L		 5642 /* crc32 doesn't generate this warning. */
5643 if (i.tm.base_opcode == 0xf20f38f0)
5644 continue;
5645
40fb9820
L		 5646 if ((i.types[op].bitfield.reg16
5647 || i.types[op].bitfield.reg32
5648 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5649 && i.op[op].regs->reg_num < 4
5650 /* Prohibit these changes in 64bit mode, since the lowering
5651 would be more complicated. */
5652 && flag_code != CODE_64BIT)
29b0f896 5653 {
29b0f896 5654#if REGISTER_WARNINGS
5a819eb9 5655 if (!quiet_warnings)
a540244d
L		 5656 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5657 register_prefix,
40fb9820 5658 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5659 ? REGNAM_AL - REGNAM_AX
5660 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5661 register_prefix,
29b0f896
AM		 5662 i.op[op].regs->reg_name,
5663 i.suffix);
5664#endif
5665 continue;
5666 }
5667 /* Any other register is bad. */
40fb9820
L		 5668 if (i.types[op].bitfield.reg16
5669 || i.types[op].bitfield.reg32
5670 || i.types[op].bitfield.reg64
5671 || i.types[op].bitfield.regmmx
5672 || i.types[op].bitfield.regxmm
c0f3af97 5673 || i.types[op].bitfield.regymm
43234a1e 5674 || i.types[op].bitfield.regzmm
40fb9820
L		 5675 || i.types[op].bitfield.sreg2
5676 || i.types[op].bitfield.sreg3
5677 || i.types[op].bitfield.control
5678 || i.types[op].bitfield.debug
5679 || i.types[op].bitfield.test
5680 || i.types[op].bitfield.floatreg
5681 || i.types[op].bitfield.floatacc)
29b0f896 5682 {
a540244d
L		 5683 as_bad (_("`%s%s' not allowed with `%s%c'"),
5684 register_prefix,
29b0f896
AM		 5685 i.op[op].regs->reg_name,
5686 i.tm.name,
5687 i.suffix);
5688 return 0;
5689 }
5690 }
5691 return 1;
5692}
5693
5694static int
e3bb37b5 5695check_long_reg (void)
29b0f896
AM		 5696{
5697 int op;
5698
5699 for (op = i.operands; --op >= 0;)
5700 /* Reject eight bit registers, except where the template requires
5701 them. (eg. movzb) */
40fb9820
L		 5702 if (i.types[op].bitfield.reg8
5703 && (i.tm.operand_types[op].bitfield.reg16
5704 || i.tm.operand_types[op].bitfield.reg32
5705 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5706 {
a540244d
L		 5707 as_bad (_("`%s%s' not allowed with `%s%c'"),
5708 register_prefix,
29b0f896
AM		 5709 i.op[op].regs->reg_name,
5710 i.tm.name,
5711 i.suffix);
5712 return 0;
5713 }
e4630f71 5714 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5715 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5716 && i.types[op].bitfield.reg16
5717 && (i.tm.operand_types[op].bitfield.reg32
5718 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5719 {
5720 /* Prohibit these changes in the 64bit mode, since the
5721 lowering is more complicated. */
5722 if (flag_code == CODE_64BIT)
252b5132 5723 {
2b5d6a91 5724 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5725 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5726 i.suffix);
5727 return 0;
252b5132 5728 }
29b0f896 5729#if REGISTER_WARNINGS
cecf1424
JB		 5730 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5731 register_prefix,
5732 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5733 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5734#endif
252b5132 5735 }
e4630f71 5736 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5737 else if (i.types[op].bitfield.reg64
5738 && (i.tm.operand_types[op].bitfield.reg32
5739 || i.tm.operand_types[op].bitfield.acc))
252b5132 5740 {
34828aad 5741 if (intel_syntax
ca61edf2 5742 && i.tm.opcode_modifier.toqword
40fb9820 5743 && !i.types[0].bitfield.regxmm)
34828aad 5744 {
ca61edf2 5745 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5746 i.suffix = QWORD_MNEM_SUFFIX;
5747 }
5748 else
5749 {
2b5d6a91 5750 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5751 register_prefix, i.op[op].regs->reg_name,
5752 i.suffix);
5753 return 0;
5754 }
29b0f896
AM		 5755 }
5756 return 1;
5757}
252b5132 5758
29b0f896 5759static int
e3bb37b5 5760check_qword_reg (void)
29b0f896
AM		 5761{
5762 int op;
252b5132 5763
29b0f896
AM		 5764 for (op = i.operands; --op >= 0; )
5765 /* Reject eight bit registers, except where the template requires
5766 them. (eg. movzb) */
40fb9820
L		 5767 if (i.types[op].bitfield.reg8
5768 && (i.tm.operand_types[op].bitfield.reg16
5769 || i.tm.operand_types[op].bitfield.reg32
5770 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5771 {
a540244d
L		 5772 as_bad (_("`%s%s' not allowed with `%s%c'"),
5773 register_prefix,
29b0f896
AM		 5774 i.op[op].regs->reg_name,
5775 i.tm.name,
5776 i.suffix);
5777 return 0;
5778 }
e4630f71 5779 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5780 else if ((i.types[op].bitfield.reg16
5781 || i.types[op].bitfield.reg32)
33d0ab95 5782 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5783 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5784 {
5785 /* Prohibit these changes in the 64bit mode, since the
5786 lowering is more complicated. */
34828aad 5787 if (intel_syntax
ca61edf2 5788 && i.tm.opcode_modifier.todword
40fb9820 5789 && !i.types[0].bitfield.regxmm)
34828aad 5790 {
ca61edf2 5791 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5792 i.suffix = LONG_MNEM_SUFFIX;
5793 }
5794 else
5795 {
2b5d6a91 5796 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5797 register_prefix, i.op[op].regs->reg_name,
5798 i.suffix);
5799 return 0;
5800 }
252b5132 5801 }
29b0f896
AM		 5802 return 1;
5803}
252b5132 5804
29b0f896 5805static int
e3bb37b5 5806check_word_reg (void)
29b0f896
AM		 5807{
5808 int op;
5809 for (op = i.operands; --op >= 0;)
5810 /* Reject eight bit registers, except where the template requires
5811 them. (eg. movzb) */
40fb9820
L		 5812 if (i.types[op].bitfield.reg8
5813 && (i.tm.operand_types[op].bitfield.reg16
5814 || i.tm.operand_types[op].bitfield.reg32
5815 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5816 {
a540244d
L		 5817 as_bad (_("`%s%s' not allowed with `%s%c'"),
5818 register_prefix,
29b0f896
AM		 5819 i.op[op].regs->reg_name,
5820 i.tm.name,
5821 i.suffix);
5822 return 0;
5823 }
e4630f71 5824 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5825 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5826 && (i.types[op].bitfield.reg32
5827 || i.types[op].bitfield.reg64)
40fb9820
L		 5828 && (i.tm.operand_types[op].bitfield.reg16
5829 || i.tm.operand_types[op].bitfield.acc))
252b5132 5830 {
29b0f896
AM		 5831 /* Prohibit these changes in the 64bit mode, since the
5832 lowering is more complicated. */
5833 if (flag_code == CODE_64BIT)
252b5132 5834 {
2b5d6a91 5835 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5836 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5837 i.suffix);
5838 return 0;
252b5132 5839 }
29b0f896 5840#if REGISTER_WARNINGS
cecf1424
JB		 5841 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5842 register_prefix,
5843 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5844 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5845#endif
5846 }
5847 return 1;
5848}
252b5132 5849
29b0f896 5850static int
40fb9820 5851update_imm (unsigned int j)
29b0f896 5852{
bc0844ae 5853 i386_operand_type overlap = i.types[j];
40fb9820
L		 5854 if ((overlap.bitfield.imm8
5855 || overlap.bitfield.imm8s
5856 || overlap.bitfield.imm16
5857 || overlap.bitfield.imm32
5858 || overlap.bitfield.imm32s
5859 || overlap.bitfield.imm64)
0dfbf9d7
L		 5860 && !operand_type_equal (&overlap, &imm8)
5861 && !operand_type_equal (&overlap, &imm8s)
5862 && !operand_type_equal (&overlap, &imm16)
5863 && !operand_type_equal (&overlap, &imm32)
5864 && !operand_type_equal (&overlap, &imm32s)
5865 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5866 {
5867 if (i.suffix)
5868 {
40fb9820
L		 5869 i386_operand_type temp;
5870
0dfbf9d7 5871 operand_type_set (&temp, 0);
7ab9ffdd 5872 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5873 {
5874 temp.bitfield.imm8 = overlap.bitfield.imm8;
5875 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5876 }
5877 else if (i.suffix == WORD_MNEM_SUFFIX)
5878 temp.bitfield.imm16 = overlap.bitfield.imm16;
5879 else if (i.suffix == QWORD_MNEM_SUFFIX)
5880 {
5881 temp.bitfield.imm64 = overlap.bitfield.imm64;
5882 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5883 }
5884 else
5885 temp.bitfield.imm32 = overlap.bitfield.imm32;
5886 overlap = temp;
29b0f896 5887 }
0dfbf9d7
L		 5888 else if (operand_type_equal (&overlap, &imm16_32_32s)
5889 || operand_type_equal (&overlap, &imm16_32)
5890 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5891 {
40fb9820 5892 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5893 overlap = imm16;
40fb9820 5894 else
65da13b5 5895 overlap = imm32s;
29b0f896 5896 }
0dfbf9d7
L		 5897 if (!operand_type_equal (&overlap, &imm8)
5898 && !operand_type_equal (&overlap, &imm8s)
5899 && !operand_type_equal (&overlap, &imm16)
5900 && !operand_type_equal (&overlap, &imm32)
5901 && !operand_type_equal (&overlap, &imm32s)
5902 && !operand_type_equal (&overlap, &imm64))
29b0f896 5903 {
4eed87de
AM		 5904 as_bad (_("no instruction mnemonic suffix given; "
5905 "can't determine immediate size"));
29b0f896
AM		 5906 return 0;
5907 }
5908 }
40fb9820 5909 i.types[j] = overlap;
29b0f896 5910
40fb9820
L		 5911 return 1;
5912}
5913
5914static int
5915finalize_imm (void)
5916{
bc0844ae 5917 unsigned int j, n;
29b0f896 5918
bc0844ae
L		 5919 /* Update the first 2 immediate operands. */
5920 n = i.operands > 2 ? 2 : i.operands;
5921 if (n)
5922 {
5923 for (j = 0; j < n; j++)
5924 if (update_imm (j) == 0)
5925 return 0;
40fb9820 5926
bc0844ae
L		 5927 /* The 3rd operand can't be immediate operand. */
5928 gas_assert (operand_type_check (i.types[2], imm) == 0);
5929 }
29b0f896
AM		 5930
5931 return 1;
5932}
5933
c0f3af97
L		 5934static int
5935bad_implicit_operand (int xmm)
5936{
91d6fa6a
NC		 5937 const char *ireg = xmm ? "xmm0" : "ymm0";
5938
c0f3af97
L		 5939 if (intel_syntax)
5940 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5941 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5942 else
5943 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5944 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5945 return 0;
5946}
5947
29b0f896 5948static int
e3bb37b5 5949process_operands (void)
29b0f896
AM		 5950{
5951 /* Default segment register this instruction will use for memory
5952 accesses. 0 means unknown. This is only for optimizing out
5953 unnecessary segment overrides. */
5954 const seg_entry *default_seg = 0;
5955
2426c15f 5956 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5957 {
91d6fa6a
NC		 5958 unsigned int dupl = i.operands;
5959 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5960 unsigned int j;
5961
c0f3af97 5962 /* The destination must be an xmm register. */
9c2799c2 5963 gas_assert (i.reg_operands
91d6fa6a 5964 && MAX_OPERANDS > dupl
7ab9ffdd 5965 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5966
5967 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5968 {
c0f3af97 5969 /* The first operand is implicit and must be xmm0. */
9c2799c2 5970 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5971 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5972 return bad_implicit_operand (1);
5973
8cd7925b 5974 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5975 {
5976 /* Keep xmm0 for instructions with VEX prefix and 3
5977 sources. */
5978 goto duplicate;
5979 }
e2ec9d29 5980 else
c0f3af97
L		 5981 {
5982 /* We remove the first xmm0 and keep the number of
5983 operands unchanged, which in fact duplicates the
5984 destination. */
5985 for (j = 1; j < i.operands; j++)
5986 {
5987 i.op[j - 1] = i.op[j];
5988 i.types[j - 1] = i.types[j];
5989 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5990 }
5991 }
5992 }
5993 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5994 {
91d6fa6a 5995 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5996 && (i.tm.opcode_modifier.vexsources
5997 == VEX3SOURCES));
c0f3af97
L		 5998
5999 /* Add the implicit xmm0 for instructions with VEX prefix
6000 and 3 sources. */
6001 for (j = i.operands; j > 0; j--)
6002 {
6003 i.op[j] = i.op[j - 1];
6004 i.types[j] = i.types[j - 1];
6005 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6006 }
6007 i.op[0].regs
6008 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6009 i.types[0] = regxmm;
c0f3af97
L		 6010 i.tm.operand_types[0] = regxmm;
6011
6012 i.operands += 2;
6013 i.reg_operands += 2;
6014 i.tm.operands += 2;
6015
91d6fa6a 6016 dupl++;
c0f3af97 6017 dest++;
91d6fa6a
NC		 6018 i.op[dupl] = i.op[dest];
6019 i.types[dupl] = i.types[dest];
6020 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6021 }
c0f3af97
L		 6022 else
6023 {
6024duplicate:
6025 i.operands++;
6026 i.reg_operands++;
6027 i.tm.operands++;
6028
91d6fa6a
NC		 6029 i.op[dupl] = i.op[dest];
6030 i.types[dupl] = i.types[dest];
6031 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6032 }
6033
6034 if (i.tm.opcode_modifier.immext)
6035 process_immext ();
6036 }
6037 else if (i.tm.opcode_modifier.firstxmm0)
6038 {
6039 unsigned int j;
6040
43234a1e 6041 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 6042 gas_assert (i.reg_operands
7ab9ffdd 6043 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 6044 || operand_type_equal (&i.types[0], &regymm)
6045 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 6046 if (register_number (i.op[0].regs) != 0)
c0f3af97 6047 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 6048
6049 for (j = 1; j < i.operands; j++)
6050 {
6051 i.op[j - 1] = i.op[j];
6052 i.types[j - 1] = i.types[j];
6053
6054 /* We need to adjust fields in i.tm since they are used by
6055 build_modrm_byte. */
6056 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6057 }
6058
e2ec9d29
L		 6059 i.operands--;
6060 i.reg_operands--;
e2ec9d29
L		 6061 i.tm.operands--;
6062 }
920d2ddc
IT		 6063 else if (i.tm.opcode_modifier.implicitquadgroup)
6064 {
6065 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6066 gas_assert (i.operands >= 2
6067 && (operand_type_equal (&i.types[1], &regxmm)
6068 || operand_type_equal (&i.types[1], &regymm)
6069 || operand_type_equal (&i.types[1], &regzmm)));
6070 unsigned int regnum = register_number (i.op[1].regs);
6071 unsigned int first_reg_in_group = regnum & ~3;
6072 unsigned int last_reg_in_group = first_reg_in_group + 3;
6073 if (regnum != first_reg_in_group) {
6074 as_warn (_("the second source register `%s%s' implicitly denotes"
6075 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6076 register_prefix, i.op[1].regs->reg_name,
6077 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6078 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6079 i.tm.name);
6080 }
6081 }
e2ec9d29
L		 6082 else if (i.tm.opcode_modifier.regkludge)
6083 {
6084 /* The imul $imm, %reg instruction is converted into
6085 imul $imm, %reg, %reg, and the clr %reg instruction
6086 is converted into xor %reg, %reg. */
6087
6088 unsigned int first_reg_op;
6089
6090 if (operand_type_check (i.types[0], reg))
6091 first_reg_op = 0;
6092 else
6093 first_reg_op = 1;
6094 /* Pretend we saw the extra register operand. */
9c2799c2 6095 gas_assert (i.reg_operands == 1
7ab9ffdd 6096 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6097 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6098 i.types[first_reg_op + 1] = i.types[first_reg_op];
6099 i.operands++;
6100 i.reg_operands++;
29b0f896
AM		 6101 }
6102
40fb9820 6103 if (i.tm.opcode_modifier.shortform)
29b0f896 6104 {
40fb9820
L		 6105 if (i.types[0].bitfield.sreg2
6106 || i.types[0].bitfield.sreg3)
29b0f896 6107 {
4eed87de
AM		 6108 if (i.tm.base_opcode == POP_SEG_SHORT
6109 && i.op[0].regs->reg_num == 1)
29b0f896 6110 {
a87af027 6111 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6112 return 0;
29b0f896 6113 }
4eed87de
AM		 6114 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6115 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6116 i.rex |= REX_B;
4eed87de
AM		 6117 }
6118 else
6119 {
7ab9ffdd 6120 /* The register or float register operand is in operand
85f10a01 6121 0 or 1. */
40fb9820 6122 unsigned int op;
7ab9ffdd
L		 6123
6124 if (i.types[0].bitfield.floatreg
6125 || operand_type_check (i.types[0], reg))
6126 op = 0;
6127 else
6128 op = 1;
4eed87de
AM		 6129 /* Register goes in low 3 bits of opcode. */
6130 i.tm.base_opcode |= i.op[op].regs->reg_num;
6131 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6132 i.rex |= REX_B;
40fb9820 6133 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6134 {
4eed87de
AM		 6135 /* Warn about some common errors, but press on regardless.
6136 The first case can be generated by gcc (<= 2.8.1). */
6137 if (i.operands == 2)
6138 {
6139 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6140 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6141 register_prefix, i.op[!intel_syntax].regs->reg_name,
6142 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6143 }
6144 else
6145 {
6146 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6147 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6148 register_prefix, i.op[0].regs->reg_name);
4eed87de 6149 }
29b0f896
AM		 6150 }
6151 }
6152 }
40fb9820 6153 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6154 {
6155 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6156 must be put into the modrm byte). Now, we make the modrm and
6157 index base bytes based on all the info we've collected. */
29b0f896
AM		 6158
6159 default_seg = build_modrm_byte ();
6160 }
8a2ed489 6161 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6162 {
6163 default_seg = &ds;
6164 }
40fb9820 6165 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6166 {
6167 /* For the string instructions that allow a segment override
6168 on one of their operands, the default segment is ds. */
6169 default_seg = &ds;
6170 }
6171
75178d9d
L		 6172 if (i.tm.base_opcode == 0x8d /* lea */
6173 && i.seg[0]
6174 && !quiet_warnings)
30123838 6175 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6176
6177 /* If a segment was explicitly specified, and the specified segment
6178 is not the default, use an opcode prefix to select it. If we
6179 never figured out what the default segment is, then default_seg
6180 will be zero at this point, and the specified segment prefix will
6181 always be used. */
29b0f896
AM		 6182 if ((i.seg[0]) && (i.seg[0] != default_seg))
6183 {
6184 if (!add_prefix (i.seg[0]->seg_prefix))
6185 return 0;
6186 }
6187 return 1;
6188}
6189
6190static const seg_entry *
e3bb37b5 6191build_modrm_byte (void)
29b0f896
AM		 6192{
6193 const seg_entry *default_seg = 0;
c0f3af97 6194 unsigned int source, dest;
8cd7925b 6195 int vex_3_sources;
c0f3af97
L		 6196
6197 /* The first operand of instructions with VEX prefix and 3 sources
6198 must be VEX_Imm4. */
8cd7925b 6199 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6200 if (vex_3_sources)
6201 {
91d6fa6a 6202 unsigned int nds, reg_slot;
4c2c6516 6203 expressionS *exp;
c0f3af97 6204
922d8de8 6205 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6206 && i.tm.opcode_modifier.immext)
6207 {
6208 dest = i.operands - 2;
6209 gas_assert (dest == 3);
6210 }
922d8de8 6211 else
a683cc34 6212 dest = i.operands - 1;
c0f3af97 6213 nds = dest - 1;
922d8de8 6214
a683cc34
SP		 6215 /* There are 2 kinds of instructions:
6216 1. 5 operands: 4 register operands or 3 register operands
6217 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6218 VexW0 or VexW1. The destination must be either XMM, YMM or
6219 ZMM register.
a683cc34
SP		 6220 2. 4 operands: 4 register operands or 3 register operands
6221 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6222 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6223 || (i.reg_operands == 3 && i.mem_operands == 1))
6224 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6225 && (i.tm.opcode_modifier.veximmext
6226 || (i.imm_operands == 1
6227 && i.types[0].bitfield.vec_imm4
6228 && (i.tm.opcode_modifier.vexw == VEXW0
6229 || i.tm.opcode_modifier.vexw == VEXW1)
6230 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6231 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6232 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6233
6234 if (i.imm_operands == 0)
6235 {
6236 /* When there is no immediate operand, generate an 8bit
6237 immediate operand to encode the first operand. */
6238 exp = &im_expressions[i.imm_operands++];
6239 i.op[i.operands].imms = exp;
6240 i.types[i.operands] = imm8;
6241 i.operands++;
6242 /* If VexW1 is set, the first operand is the source and
6243 the second operand is encoded in the immediate operand. */
6244 if (i.tm.opcode_modifier.vexw == VEXW1)
6245 {
6246 source = 0;
6247 reg_slot = 1;
6248 }
6249 else
6250 {
6251 source = 1;
6252 reg_slot = 0;
6253 }
6254
6255 /* FMA swaps REG and NDS. */
6256 if (i.tm.cpu_flags.bitfield.cpufma)
6257 {
6258 unsigned int tmp;
6259 tmp = reg_slot;
6260 reg_slot = nds;
6261 nds = tmp;
6262 }
6263
24981e7b
L		 6264 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6265 &regxmm)
a683cc34 6266 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6267 &regymm)
6268 || operand_type_equal (&i.tm.operand_types[reg_slot],
6269 &regzmm));
a683cc34 6270 exp->X_op = O_constant;
4c692bc7 6271 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6272 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6273 }
922d8de8 6274 else
a683cc34
SP		 6275 {
6276 unsigned int imm_slot;
6277
6278 if (i.tm.opcode_modifier.vexw == VEXW0)
6279 {
6280 /* If VexW0 is set, the third operand is the source and
6281 the second operand is encoded in the immediate
6282 operand. */
6283 source = 2;
6284 reg_slot = 1;
6285 }
6286 else
6287 {
6288 /* VexW1 is set, the second operand is the source and
6289 the third operand is encoded in the immediate
6290 operand. */
6291 source = 1;
6292 reg_slot = 2;
6293 }
6294
6295 if (i.tm.opcode_modifier.immext)
6296 {
33eaf5de 6297 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6298 operand. */
6299 imm_slot = i.operands - 1;
6300 source--;
6301 reg_slot--;
6302 }
6303 else
6304 {
6305 imm_slot = 0;
6306
6307 /* Turn on Imm8 so that output_imm will generate it. */
6308 i.types[imm_slot].bitfield.imm8 = 1;
6309 }
6310
24981e7b
L		 6311 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6312 &regxmm)
6313 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6314 &regymm)
6315 || operand_type_equal (&i.tm.operand_types[reg_slot],
6316 &regzmm));
a683cc34 6317 i.op[imm_slot].imms->X_add_number
4c692bc7 6318 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6319 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6320 }
6321
6322 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6323 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6324 &regymm)
6325 || operand_type_equal (&i.tm.operand_types[nds],
6326 &regzmm));
dae39acc 6327 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6328 }
6329 else
6330 source = dest = 0;
29b0f896
AM		 6331
6332 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6333 implicit registers do not count. If there are 3 register
6334 operands, it must be a instruction with VexNDS. For a
6335 instruction with VexNDD, the destination register is encoded
6336 in VEX prefix. If there are 4 register operands, it must be
6337 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6338 if (i.mem_operands == 0
6339 && ((i.reg_operands == 2
2426c15f 6340 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6341 || (i.reg_operands == 3
2426c15f 6342 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6343 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6344 {
cab737b9
L		 6345 switch (i.operands)
6346 {
6347 case 2:
6348 source = 0;
6349 break;
6350 case 3:
c81128dc
L		 6351 /* When there are 3 operands, one of them may be immediate,
6352 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6353 the first operand must be shift count register (cl) or it
6354 is an instruction with VexNDS. */
9c2799c2 6355 gas_assert (i.imm_operands == 1
7ab9ffdd 6356 || (i.imm_operands == 0
2426c15f 6357 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6358 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6359 if (operand_type_check (i.types[0], imm)
6360 || i.types[0].bitfield.shiftcount)
6361 source = 1;
6362 else
6363 source = 0;
cab737b9
L		 6364 break;
6365 case 4:
368d64cc
L		 6366 /* When there are 4 operands, the first two must be 8bit
6367 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6368 one.
6369
6370 For instructions with VexNDS, if the first operand
6371 an imm8, the source operand is the 2nd one. If the last
6372 operand is imm8, the source operand is the first one. */
9c2799c2 6373 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6374 && i.types[0].bitfield.imm8
6375 && i.types[1].bitfield.imm8)
2426c15f 6376 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6377 && i.imm_operands == 1
6378 && (i.types[0].bitfield.imm8
43234a1e
L		 6379 || i.types[i.operands - 1].bitfield.imm8
6380 || i.rounding)));
9f2670f2
L		 6381 if (i.imm_operands == 2)
6382 source = 2;
6383 else
c0f3af97
L		 6384 {
6385 if (i.types[0].bitfield.imm8)
6386 source = 1;
6387 else
6388 source = 0;
6389 }
c0f3af97
L		 6390 break;
6391 case 5:
43234a1e
L		 6392 if (i.tm.opcode_modifier.evex)
6393 {
6394 /* For EVEX instructions, when there are 5 operands, the
6395 first one must be immediate operand. If the second one
6396 is immediate operand, the source operand is the 3th
6397 one. If the last one is immediate operand, the source
6398 operand is the 2nd one. */
6399 gas_assert (i.imm_operands == 2
6400 && i.tm.opcode_modifier.sae
6401 && operand_type_check (i.types[0], imm));
6402 if (operand_type_check (i.types[1], imm))
6403 source = 2;
6404 else if (operand_type_check (i.types[4], imm))
6405 source = 1;
6406 else
6407 abort ();
6408 }
cab737b9
L		 6409 break;
6410 default:
6411 abort ();
6412 }
6413
c0f3af97
L		 6414 if (!vex_3_sources)
6415 {
6416 dest = source + 1;
6417
43234a1e
L		 6418 /* RC/SAE operand could be between DEST and SRC. That happens
6419 when one operand is GPR and the other one is XMM/YMM/ZMM
6420 register. */
6421 if (i.rounding && i.rounding->operand == (int) dest)
6422 dest++;
6423
2426c15f 6424 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6425 {
43234a1e
L		 6426 /* For instructions with VexNDS, the register-only source
6427 operand must be 32/64bit integer, XMM, YMM or ZMM
6428 register. It is encoded in VEX prefix. We need to
6429 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6430
6431 i386_operand_type op;
6432 unsigned int vvvv;
6433
6434 /* Check register-only source operand when two source
6435 operands are swapped. */
6436 if (!i.tm.operand_types[source].bitfield.baseindex
6437 && i.tm.operand_types[dest].bitfield.baseindex)
6438 {
6439 vvvv = source;
6440 source = dest;
6441 }
6442 else
6443 vvvv = dest;
6444
6445 op = i.tm.operand_types[vvvv];
fa99fab2 6446 op.bitfield.regmem = 0;
c0f3af97 6447 if ((dest + 1) >= i.operands
ac4eb736
AM		 6448 || (!op.bitfield.reg32
6449 && op.bitfield.reg64
f12dc422 6450 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6451 && !operand_type_equal (&op, &regymm)
6452 && !operand_type_equal (&op, &regzmm)
6453 && !operand_type_equal (&op, &regmask)))
c0f3af97 6454 abort ();
f12dc422 6455 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6456 dest++;
6457 }
6458 }
29b0f896
AM		 6459
6460 i.rm.mode = 3;
6461 /* One of the register operands will be encoded in the i.tm.reg
6462 field, the other in the combined i.tm.mode and i.tm.regmem
6463 fields. If no form of this instruction supports a memory
6464 destination operand, then we assume the source operand may
6465 sometimes be a memory operand and so we need to store the
6466 destination in the i.rm.reg field. */
40fb9820
L		 6467 if (!i.tm.operand_types[dest].bitfield.regmem
6468 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6469 {
6470 i.rm.reg = i.op[dest].regs->reg_num;
6471 i.rm.regmem = i.op[source].regs->reg_num;
6472 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6473 i.rex |= REX_R;
43234a1e
L		 6474 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6475 i.vrex |= REX_R;
29b0f896 6476 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6477 i.rex |= REX_B;
43234a1e
L		 6478 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6479 i.vrex |= REX_B;
29b0f896
AM		 6480 }
6481 else
6482 {
6483 i.rm.reg = i.op[source].regs->reg_num;
6484 i.rm.regmem = i.op[dest].regs->reg_num;
6485 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6486 i.rex |= REX_B;
43234a1e
L		 6487 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6488 i.vrex |= REX_B;
29b0f896 6489 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6490 i.rex |= REX_R;
43234a1e
L		 6491 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6492 i.vrex |= REX_R;
29b0f896 6493 }
161a04f6 6494 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6495 {
40fb9820
L		 6496 if (!i.types[0].bitfield.control
6497 && !i.types[1].bitfield.control)
c4a530c5 6498 abort ();
161a04f6 6499 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6500 add_prefix (LOCK_PREFIX_OPCODE);
6501 }
29b0f896
AM		 6502 }
6503 else
6504 { /* If it's not 2 reg operands... */
c0f3af97
L		 6505 unsigned int mem;
6506
29b0f896
AM		 6507 if (i.mem_operands)
6508 {
6509 unsigned int fake_zero_displacement = 0;
99018f42 6510 unsigned int op;
4eed87de 6511
7ab9ffdd
L		 6512 for (op = 0; op < i.operands; op++)
6513 if (operand_type_check (i.types[op], anymem))
6514 break;
7ab9ffdd 6515 gas_assert (op < i.operands);
29b0f896 6516
6c30d220
L		 6517 if (i.tm.opcode_modifier.vecsib)
6518 {
6519 if (i.index_reg->reg_num == RegEiz
6520 || i.index_reg->reg_num == RegRiz)
6521 abort ();
6522
6523 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6524 if (!i.base_reg)
6525 {
6526 i.sib.base = NO_BASE_REGISTER;
6527 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6528 /* No Vec_Disp8 if there is no base. */
6529 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6530 i.types[op].bitfield.disp8 = 0;
6531 i.types[op].bitfield.disp16 = 0;
6532 i.types[op].bitfield.disp64 = 0;
6533 if (flag_code != CODE_64BIT)
6534 {
6535 /* Must be 32 bit */
6536 i.types[op].bitfield.disp32 = 1;
6537 i.types[op].bitfield.disp32s = 0;
6538 }
6539 else
6540 {
6541 i.types[op].bitfield.disp32 = 0;
6542 i.types[op].bitfield.disp32s = 1;
6543 }
6544 }
6545 i.sib.index = i.index_reg->reg_num;
6546 if ((i.index_reg->reg_flags & RegRex) != 0)
6547 i.rex |= REX_X;
43234a1e
L		 6548 if ((i.index_reg->reg_flags & RegVRex) != 0)
6549 i.vrex |= REX_X;
6c30d220
L		 6550 }
6551
29b0f896
AM		 6552 default_seg = &ds;
6553
6554 if (i.base_reg == 0)
6555 {
6556 i.rm.mode = 0;
6557 if (!i.disp_operands)
6c30d220
L		 6558 {
6559 fake_zero_displacement = 1;
6560 /* Instructions with VSIB byte need 32bit displacement
6561 if there is no base register. */
6562 if (i.tm.opcode_modifier.vecsib)
6563 i.types[op].bitfield.disp32 = 1;
6564 }
29b0f896
AM		 6565 if (i.index_reg == 0)
6566 {
6c30d220 6567 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6568 /* Operand is just <disp> */
20f0a1fc 6569 if (flag_code == CODE_64BIT)
29b0f896
AM		 6570 {
6571 /* 64bit mode overwrites the 32bit absolute
6572 addressing by RIP relative addressing and
6573 absolute addressing is encoded by one of the
6574 redundant SIB forms. */
6575 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6576 i.sib.base = NO_BASE_REGISTER;
6577 i.sib.index = NO_INDEX_REGISTER;
fc225355 6578 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6579 ? disp32s : disp32);
20f0a1fc 6580 }
fc225355
L		 6581 else if ((flag_code == CODE_16BIT)
6582 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6583 {
6584 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6585 i.types[op] = disp16;
20f0a1fc
NC		 6586 }
6587 else
6588 {
6589 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6590 i.types[op] = disp32;
29b0f896
AM		 6591 }
6592 }
6c30d220 6593 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6594 {
6c30d220 6595 /* !i.base_reg && i.index_reg */
db51cc60
L		 6596 if (i.index_reg->reg_num == RegEiz
6597 || i.index_reg->reg_num == RegRiz)
6598 i.sib.index = NO_INDEX_REGISTER;
6599 else
6600 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6601 i.sib.base = NO_BASE_REGISTER;
6602 i.sib.scale = i.log2_scale_factor;
6603 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6604 /* No Vec_Disp8 if there is no base. */
6605 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6606 i.types[op].bitfield.disp8 = 0;
6607 i.types[op].bitfield.disp16 = 0;
6608 i.types[op].bitfield.disp64 = 0;
29b0f896 6609 if (flag_code != CODE_64BIT)
40fb9820
L		 6610 {
6611 /* Must be 32 bit */
6612 i.types[op].bitfield.disp32 = 1;
6613 i.types[op].bitfield.disp32s = 0;
6614 }
29b0f896 6615 else
40fb9820
L		 6616 {
6617 i.types[op].bitfield.disp32 = 0;
6618 i.types[op].bitfield.disp32s = 1;
6619 }
29b0f896 6620 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6621 i.rex |= REX_X;
29b0f896
AM		 6622 }
6623 }
6624 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6625 else if (i.base_reg->reg_num == RegRip ||
6626 i.base_reg->reg_num == RegEip)
29b0f896 6627 {
6c30d220 6628 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6629 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6630 i.types[op].bitfield.disp8 = 0;
6631 i.types[op].bitfield.disp16 = 0;
6632 i.types[op].bitfield.disp32 = 0;
6633 i.types[op].bitfield.disp32s = 1;
6634 i.types[op].bitfield.disp64 = 0;
43234a1e 6635 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6636 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6637 if (! i.disp_operands)
6638 fake_zero_displacement = 1;
29b0f896 6639 }
40fb9820 6640 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6641 {
6c30d220 6642 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6643 switch (i.base_reg->reg_num)
6644 {
6645 case 3: /* (%bx) */
6646 if (i.index_reg == 0)
6647 i.rm.regmem = 7;
6648 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6649 i.rm.regmem = i.index_reg->reg_num - 6;
6650 break;
6651 case 5: /* (%bp) */
6652 default_seg = &ss;
6653 if (i.index_reg == 0)
6654 {
6655 i.rm.regmem = 6;
40fb9820 6656 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6657 {
6658 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6659 if (i.tm.operand_types[op].bitfield.vec_disp8)
6660 i.types[op].bitfield.vec_disp8 = 1;
6661 else
6662 i.types[op].bitfield.disp8 = 1;
252b5132 6663 fake_zero_displacement = 1;
29b0f896
AM		 6664 }
6665 }
6666 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6667 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6668 break;
6669 default: /* (%si) -> 4 or (%di) -> 5 */
6670 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6671 }
6672 i.rm.mode = mode_from_disp_size (i.types[op]);
6673 }
6674 else /* i.base_reg and 32/64 bit mode */
6675 {
6676 if (flag_code == CODE_64BIT
40fb9820
L		 6677 && operand_type_check (i.types[op], disp))
6678 {
6679 i386_operand_type temp;
0dfbf9d7 6680 operand_type_set (&temp, 0);
40fb9820 6681 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6682 temp.bitfield.vec_disp8
6683 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6684 i.types[op] = temp;
6685 if (i.prefix[ADDR_PREFIX] == 0)
6686 i.types[op].bitfield.disp32s = 1;
6687 else
6688 i.types[op].bitfield.disp32 = 1;
6689 }
20f0a1fc 6690
6c30d220
L		 6691 if (!i.tm.opcode_modifier.vecsib)
6692 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6693 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6694 i.rex |= REX_B;
29b0f896
AM		 6695 i.sib.base = i.base_reg->reg_num;
6696 /* x86-64 ignores REX prefix bit here to avoid decoder
6697 complications. */
848930b2
JB		 6698 if (!(i.base_reg->reg_flags & RegRex)
6699 && (i.base_reg->reg_num == EBP_REG_NUM
6700 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6701 default_seg = &ss;
848930b2 6702 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6703 {
848930b2 6704 fake_zero_displacement = 1;
43234a1e
L		 6705 if (i.tm.operand_types [op].bitfield.vec_disp8)
6706 i.types[op].bitfield.vec_disp8 = 1;
6707 else
6708 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6709 }
6710 i.sib.scale = i.log2_scale_factor;
6711 if (i.index_reg == 0)
6712 {
6c30d220 6713 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6714 /* <disp>(%esp) becomes two byte modrm with no index
6715 register. We've already stored the code for esp
6716 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6717 Any base register besides %esp will not use the
6718 extra modrm byte. */
6719 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6720 }
6c30d220 6721 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6722 {
db51cc60
L		 6723 if (i.index_reg->reg_num == RegEiz
6724 || i.index_reg->reg_num == RegRiz)
6725 i.sib.index = NO_INDEX_REGISTER;
6726 else
6727 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6728 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6729 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6730 i.rex |= REX_X;
29b0f896 6731 }
67a4f2b7
AO		 6732
6733 if (i.disp_operands
6734 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6735 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6736 i.rm.mode = 0;
6737 else
a501d77e
L		 6738 {
6739 if (!fake_zero_displacement
6740 && !i.disp_operands
6741 && i.disp_encoding)
6742 {
6743 fake_zero_displacement = 1;
6744 if (i.disp_encoding == disp_encoding_8bit)
6745 i.types[op].bitfield.disp8 = 1;
6746 else
6747 i.types[op].bitfield.disp32 = 1;
6748 }
6749 i.rm.mode = mode_from_disp_size (i.types[op]);
6750 }
29b0f896 6751 }
252b5132 6752
29b0f896
AM		 6753 if (fake_zero_displacement)
6754 {
6755 /* Fakes a zero displacement assuming that i.types[op]
6756 holds the correct displacement size. */
6757 expressionS *exp;
6758
9c2799c2 6759 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6760 exp = &disp_expressions[i.disp_operands++];
6761 i.op[op].disps = exp;
6762 exp->X_op = O_constant;
6763 exp->X_add_number = 0;
6764 exp->X_add_symbol = (symbolS *) 0;
6765 exp->X_op_symbol = (symbolS *) 0;
6766 }
c0f3af97
L		 6767
6768 mem = op;
29b0f896 6769 }
c0f3af97
L		 6770 else
6771 mem = ~0;
252b5132 6772
8c43a48b 6773 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6774 {
6775 if (operand_type_check (i.types[0], imm))
6776 i.vex.register_specifier = NULL;
6777 else
6778 {
6779 /* VEX.vvvv encodes one of the sources when the first
6780 operand is not an immediate. */
1ef99a7b 6781 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6782 i.vex.register_specifier = i.op[0].regs;
6783 else
6784 i.vex.register_specifier = i.op[1].regs;
6785 }
6786
6787 /* Destination is a XMM register encoded in the ModRM.reg
6788 and VEX.R bit. */
6789 i.rm.reg = i.op[2].regs->reg_num;
6790 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6791 i.rex |= REX_R;
6792
6793 /* ModRM.rm and VEX.B encodes the other source. */
6794 if (!i.mem_operands)
6795 {
6796 i.rm.mode = 3;
6797
1ef99a7b 6798 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6799 i.rm.regmem = i.op[1].regs->reg_num;
6800 else
6801 i.rm.regmem = i.op[0].regs->reg_num;
6802
6803 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6804 i.rex |= REX_B;
6805 }
6806 }
2426c15f 6807 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6808 {
6809 i.vex.register_specifier = i.op[2].regs;
6810 if (!i.mem_operands)
6811 {
6812 i.rm.mode = 3;
6813 i.rm.regmem = i.op[1].regs->reg_num;
6814 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6815 i.rex |= REX_B;
6816 }
6817 }
29b0f896
AM		 6818 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6819 (if any) based on i.tm.extension_opcode. Again, we must be
6820 careful to make sure that segment/control/debug/test/MMX
6821 registers are coded into the i.rm.reg field. */
f88c9eb0 6822 else if (i.reg_operands)
29b0f896 6823 {
99018f42 6824 unsigned int op;
7ab9ffdd
L		 6825 unsigned int vex_reg = ~0;
6826
6827 for (op = 0; op < i.operands; op++)
6828 if (i.types[op].bitfield.reg8
6829 || i.types[op].bitfield.reg16
6830 || i.types[op].bitfield.reg32
6831 || i.types[op].bitfield.reg64
6832 || i.types[op].bitfield.regmmx
6833 || i.types[op].bitfield.regxmm
6834 || i.types[op].bitfield.regymm
7e8b059b 6835 || i.types[op].bitfield.regbnd
43234a1e
L		 6836 || i.types[op].bitfield.regzmm
6837 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6838 || i.types[op].bitfield.sreg2
6839 || i.types[op].bitfield.sreg3
6840 || i.types[op].bitfield.control
6841 || i.types[op].bitfield.debug
6842 || i.types[op].bitfield.test)
6843 break;
c0209578 6844
7ab9ffdd
L		 6845 if (vex_3_sources)
6846 op = dest;
2426c15f 6847 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6848 {
6849 /* For instructions with VexNDS, the register-only
6850 source operand is encoded in VEX prefix. */
6851 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6852
7ab9ffdd 6853 if (op > mem)
c0f3af97 6854 {
7ab9ffdd
L		 6855 vex_reg = op++;
6856 gas_assert (op < i.operands);
c0f3af97
L		 6857 }
6858 else
c0f3af97 6859 {
f12dc422
L		 6860 /* Check register-only source operand when two source
6861 operands are swapped. */
6862 if (!i.tm.operand_types[op].bitfield.baseindex
6863 && i.tm.operand_types[op + 1].bitfield.baseindex)
6864 {
6865 vex_reg = op;
6866 op += 2;
6867 gas_assert (mem == (vex_reg + 1)
6868 && op < i.operands);
6869 }
6870 else
6871 {
6872 vex_reg = op + 1;
6873 gas_assert (vex_reg < i.operands);
6874 }
c0f3af97 6875 }
7ab9ffdd 6876 }
2426c15f 6877 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6878 {
f12dc422 6879 /* For instructions with VexNDD, the register destination
7ab9ffdd 6880 is encoded in VEX prefix. */
f12dc422
L		 6881 if (i.mem_operands == 0)
6882 {
6883 /* There is no memory operand. */
6884 gas_assert ((op + 2) == i.operands);
6885 vex_reg = op + 1;
6886 }
6887 else
8d63c93e 6888 {
f12dc422
L		 6889 /* There are only 2 operands. */
6890 gas_assert (op < 2 && i.operands == 2);
6891 vex_reg = 1;
6892 }
7ab9ffdd
L		 6893 }
6894 else
6895 gas_assert (op < i.operands);
99018f42 6896
7ab9ffdd
L		 6897 if (vex_reg != (unsigned int) ~0)
6898 {
f12dc422 6899 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6900
f12dc422
L		 6901 if (type->bitfield.reg32 != 1
6902 && type->bitfield.reg64 != 1
6903 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6904 && !operand_type_equal (type, &regymm)
6905 && !operand_type_equal (type, &regzmm)
6906 && !operand_type_equal (type, &regmask))
7ab9ffdd 6907 abort ();
f88c9eb0 6908
7ab9ffdd
L		 6909 i.vex.register_specifier = i.op[vex_reg].regs;
6910 }
6911
1b9f0c97
L		 6912 /* Don't set OP operand twice. */
6913 if (vex_reg != op)
7ab9ffdd 6914 {
1b9f0c97
L		 6915 /* If there is an extension opcode to put here, the
6916 register number must be put into the regmem field. */
6917 if (i.tm.extension_opcode != None)
6918 {
6919 i.rm.regmem = i.op[op].regs->reg_num;
6920 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6921 i.rex |= REX_B;
43234a1e
L		 6922 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6923 i.vrex |= REX_B;
1b9f0c97
L		 6924 }
6925 else
6926 {
6927 i.rm.reg = i.op[op].regs->reg_num;
6928 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6929 i.rex |= REX_R;
43234a1e
L		 6930 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6931 i.vrex |= REX_R;
1b9f0c97 6932 }
7ab9ffdd 6933 }
252b5132 6934
29b0f896
AM		 6935 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6936 must set it to 3 to indicate this is a register operand
6937 in the regmem field. */
6938 if (!i.mem_operands)
6939 i.rm.mode = 3;
6940 }
252b5132 6941
29b0f896 6942 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6943 if (i.tm.extension_opcode != None)
29b0f896
AM		 6944 i.rm.reg = i.tm.extension_opcode;
6945 }
6946 return default_seg;
6947}
252b5132 6948
29b0f896 6949static void
e3bb37b5 6950output_branch (void)
29b0f896
AM		 6951{
6952 char *p;
f8a5c266 6953 int size;
29b0f896
AM		 6954 int code16;
6955 int prefix;
6956 relax_substateT subtype;
6957 symbolS *sym;
6958 offsetT off;
6959
f8a5c266 6960 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6961 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6962
6963 prefix = 0;
6964 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6965 {
29b0f896
AM		 6966 prefix = 1;
6967 i.prefixes -= 1;
6968 code16 ^= CODE16;
252b5132 6969 }
29b0f896
AM		 6970 /* Pentium4 branch hints. */
6971 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6972 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6973 {
29b0f896
AM		 6974 prefix++;
6975 i.prefixes--;
6976 }
6977 if (i.prefix[REX_PREFIX] != 0)
6978 {
6979 prefix++;
6980 i.prefixes--;
2f66722d
AM		 6981 }
6982
7e8b059b
L		 6983 /* BND prefixed jump. */
6984 if (i.prefix[BND_PREFIX] != 0)
6985 {
6986 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6987 i.prefixes -= 1;
6988 }
6989
29b0f896
AM		 6990 if (i.prefixes != 0 && !intel_syntax)
6991 as_warn (_("skipping prefixes on this instruction"));
6992
6993 /* It's always a symbol; End frag & setup for relax.
6994 Make sure there is enough room in this frag for the largest
6995 instruction we may generate in md_convert_frag. This is 2
6996 bytes for the opcode and room for the prefix and largest
6997 displacement. */
6998 frag_grow (prefix + 2 + 4);
6999 /* Prefix and 1 opcode byte go in fr_fix. */
7000 p = frag_more (prefix + 1);
7001 if (i.prefix[DATA_PREFIX] != 0)
7002 *p++ = DATA_PREFIX_OPCODE;
7003 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7004 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7005 *p++ = i.prefix[SEG_PREFIX];
7006 if (i.prefix[REX_PREFIX] != 0)
7007 *p++ = i.prefix[REX_PREFIX];
7008 *p = i.tm.base_opcode;
7009
7010 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7011 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7012 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7013 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7014 else
f8a5c266 7015 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7016 subtype |= code16;
3e73aa7c 7017
29b0f896
AM		 7018 sym = i.op[0].disps->X_add_symbol;
7019 off = i.op[0].disps->X_add_number;
3e73aa7c 7020
29b0f896
AM		 7021 if (i.op[0].disps->X_op != O_constant
7022 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7023 {
29b0f896
AM		 7024 /* Handle complex expressions. */
7025 sym = make_expr_symbol (i.op[0].disps);
7026 off = 0;
7027 }
3e73aa7c 7028
29b0f896
AM		 7029 /* 1 possible extra opcode + 4 byte displacement go in var part.
7030 Pass reloc in fr_var. */
d258b828 7031 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7032}
3e73aa7c 7033
29b0f896 7034static void
e3bb37b5 7035output_jump (void)
29b0f896
AM		 7036{
7037 char *p;
7038 int size;
3e02c1cc 7039 fixS *fixP;
29b0f896 7040
40fb9820 7041 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7042 {
7043 /* This is a loop or jecxz type instruction. */
7044 size = 1;
7045 if (i.prefix[ADDR_PREFIX] != 0)
7046 {
7047 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7048 i.prefixes -= 1;
7049 }
7050 /* Pentium4 branch hints. */
7051 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7052 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7053 {
7054 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7055 i.prefixes--;
3e73aa7c
JH		 7056 }
7057 }
29b0f896
AM		 7058 else
7059 {
7060 int code16;
3e73aa7c 7061
29b0f896
AM		 7062 code16 = 0;
7063 if (flag_code == CODE_16BIT)
7064 code16 = CODE16;
3e73aa7c 7065
29b0f896
AM		 7066 if (i.prefix[DATA_PREFIX] != 0)
7067 {
7068 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7069 i.prefixes -= 1;
7070 code16 ^= CODE16;
7071 }
252b5132 7072
29b0f896
AM		 7073 size = 4;
7074 if (code16)
7075 size = 2;
7076 }
9fcc94b6 7077
29b0f896
AM		 7078 if (i.prefix[REX_PREFIX] != 0)
7079 {
7080 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7081 i.prefixes -= 1;
7082 }
252b5132 7083
7e8b059b
L		 7084 /* BND prefixed jump. */
7085 if (i.prefix[BND_PREFIX] != 0)
7086 {
7087 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7088 i.prefixes -= 1;
7089 }
7090
29b0f896
AM		 7091 if (i.prefixes != 0 && !intel_syntax)
7092 as_warn (_("skipping prefixes on this instruction"));
e0890092 7093
42164a71
L		 7094 p = frag_more (i.tm.opcode_length + size);
7095 switch (i.tm.opcode_length)
7096 {
7097 case 2:
7098 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7099 /* Fall through. */
42164a71
L		 7100 case 1:
7101 *p++ = i.tm.base_opcode;
7102 break;
7103 default:
7104 abort ();
7105 }
e0890092 7106
3e02c1cc 7107 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7108 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7109
7110 /* All jumps handled here are signed, but don't use a signed limit
7111 check for 32 and 16 bit jumps as we want to allow wrap around at
7112 4G and 64k respectively. */
7113 if (size == 1)
7114 fixP->fx_signed = 1;
29b0f896 7115}
e0890092 7116
29b0f896 7117static void
e3bb37b5 7118output_interseg_jump (void)
29b0f896
AM		 7119{
7120 char *p;
7121 int size;
7122 int prefix;
7123 int code16;
252b5132 7124
29b0f896
AM		 7125 code16 = 0;
7126 if (flag_code == CODE_16BIT)
7127 code16 = CODE16;
a217f122 7128
29b0f896
AM		 7129 prefix = 0;
7130 if (i.prefix[DATA_PREFIX] != 0)
7131 {
7132 prefix = 1;
7133 i.prefixes -= 1;
7134 code16 ^= CODE16;
7135 }
7136 if (i.prefix[REX_PREFIX] != 0)
7137 {
7138 prefix++;
7139 i.prefixes -= 1;
7140 }
252b5132 7141
29b0f896
AM		 7142 size = 4;
7143 if (code16)
7144 size = 2;
252b5132 7145
29b0f896
AM		 7146 if (i.prefixes != 0 && !intel_syntax)
7147 as_warn (_("skipping prefixes on this instruction"));
252b5132 7148
29b0f896
AM		 7149 /* 1 opcode; 2 segment; offset */
7150 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7151
29b0f896
AM		 7152 if (i.prefix[DATA_PREFIX] != 0)
7153 *p++ = DATA_PREFIX_OPCODE;
252b5132 7154
29b0f896
AM		 7155 if (i.prefix[REX_PREFIX] != 0)
7156 *p++ = i.prefix[REX_PREFIX];
252b5132 7157
29b0f896
AM		 7158 *p++ = i.tm.base_opcode;
7159 if (i.op[1].imms->X_op == O_constant)
7160 {
7161 offsetT n = i.op[1].imms->X_add_number;
252b5132 7162
29b0f896
AM		 7163 if (size == 2
7164 && !fits_in_unsigned_word (n)
7165 && !fits_in_signed_word (n))
7166 {
7167 as_bad (_("16-bit jump out of range"));
7168 return;
7169 }
7170 md_number_to_chars (p, n, size);
7171 }
7172 else
7173 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7174 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7175 if (i.op[0].imms->X_op != O_constant)
7176 as_bad (_("can't handle non absolute segment in `%s'"),
7177 i.tm.name);
7178 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7179}
a217f122 7180
29b0f896 7181static void
e3bb37b5 7182output_insn (void)
29b0f896 7183{
2bbd9c25
JJ		 7184 fragS *insn_start_frag;
7185 offsetT insn_start_off;
7186
29b0f896
AM		 7187 /* Tie dwarf2 debug info to the address at the start of the insn.
7188 We can't do this after the insn has been output as the current
7189 frag may have been closed off. eg. by frag_var. */
7190 dwarf2_emit_insn (0);
7191
2bbd9c25
JJ		 7192 insn_start_frag = frag_now;
7193 insn_start_off = frag_now_fix ();
7194
29b0f896 7195 /* Output jumps. */
40fb9820 7196 if (i.tm.opcode_modifier.jump)
29b0f896 7197 output_branch ();
40fb9820
L		 7198 else if (i.tm.opcode_modifier.jumpbyte
7199 || i.tm.opcode_modifier.jumpdword)
29b0f896 7200 output_jump ();
40fb9820 7201 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7202 output_interseg_jump ();
7203 else
7204 {
7205 /* Output normal instructions here. */
7206 char *p;
7207 unsigned char *q;
47465058 7208 unsigned int j;
331d2d0d 7209 unsigned int prefix;
4dffcebc 7210
e4e00185
AS		 7211 if (avoid_fence
7212 && i.tm.base_opcode == 0xfae
7213 && i.operands == 1
7214 && i.imm_operands == 1
7215 && (i.op[0].imms->X_add_number == 0xe8
7216 || i.op[0].imms->X_add_number == 0xf0
7217 || i.op[0].imms->X_add_number == 0xf8))
7218 {
7219 /* Encode lfence, mfence, and sfence as
7220 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7221 offsetT val = 0x240483f0ULL;
7222 p = frag_more (5);
7223 md_number_to_chars (p, val, 5);
7224 return;
7225 }
7226
d022bddd
IT		 7227 /* Some processors fail on LOCK prefix. This options makes
7228 assembler ignore LOCK prefix and serves as a workaround. */
7229 if (omit_lock_prefix)
7230 {
7231 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7232 return;
7233 i.prefix[LOCK_PREFIX] = 0;
7234 }
7235
43234a1e
L		 7236 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7237 don't need the explicit prefix. */
7238 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7239 {
c0f3af97 7240 switch (i.tm.opcode_length)
bc4bd9ab 7241 {
c0f3af97
L		 7242 case 3:
7243 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7244 {
c0f3af97
L		 7245 prefix = (i.tm.base_opcode >> 24) & 0xff;
7246 goto check_prefix;
7247 }
7248 break;
7249 case 2:
7250 if ((i.tm.base_opcode & 0xff0000) != 0)
7251 {
7252 prefix = (i.tm.base_opcode >> 16) & 0xff;
7253 if (i.tm.cpu_flags.bitfield.cpupadlock)
7254 {
4dffcebc 7255check_prefix:
c0f3af97 7256 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7257 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7258 != REPE_PREFIX_OPCODE))
7259 add_prefix (prefix);
7260 }
7261 else
4dffcebc
L		 7262 add_prefix (prefix);
7263 }
c0f3af97
L		 7264 break;
7265 case 1:
7266 break;
7267 default:
7268 abort ();
bc4bd9ab 7269 }
c0f3af97 7270
6d19a37a 7271#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7272 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7273 R_X86_64_GOTTPOFF relocation so that linker can safely
7274 perform IE->LE optimization. */
7275 if (x86_elf_abi == X86_64_X32_ABI
7276 && i.operands == 2
7277 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7278 && i.prefix[REX_PREFIX] == 0)
7279 add_prefix (REX_OPCODE);
6d19a37a 7280#endif
cf61b747 7281
c0f3af97
L		 7282 /* The prefix bytes. */
7283 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7284 if (*q)
7285 FRAG_APPEND_1_CHAR (*q);
0f10071e 7286 }
ae5c1c7b 7287 else
c0f3af97
L		 7288 {
7289 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7290 if (*q)
7291 switch (j)
7292 {
7293 case REX_PREFIX:
7294 /* REX byte is encoded in VEX prefix. */
7295 break;
7296 case SEG_PREFIX:
7297 case ADDR_PREFIX:
7298 FRAG_APPEND_1_CHAR (*q);
7299 break;
7300 default:
7301 /* There should be no other prefixes for instructions
7302 with VEX prefix. */
7303 abort ();
7304 }
7305
43234a1e
L		 7306 /* For EVEX instructions i.vrex should become 0 after
7307 build_evex_prefix. For VEX instructions upper 16 registers
7308 aren't available, so VREX should be 0. */
7309 if (i.vrex)
7310 abort ();
c0f3af97
L		 7311 /* Now the VEX prefix. */
7312 p = frag_more (i.vex.length);
7313 for (j = 0; j < i.vex.length; j++)
7314 p[j] = i.vex.bytes[j];
7315 }
252b5132 7316
29b0f896 7317 /* Now the opcode; be careful about word order here! */
4dffcebc 7318 if (i.tm.opcode_length == 1)
29b0f896
AM		 7319 {
7320 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7321 }
7322 else
7323 {
4dffcebc 7324 switch (i.tm.opcode_length)
331d2d0d 7325 {
43234a1e
L		 7326 case 4:
7327 p = frag_more (4);
7328 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7329 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7330 break;
4dffcebc 7331 case 3:
331d2d0d
L		 7332 p = frag_more (3);
7333 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7334 break;
7335 case 2:
7336 p = frag_more (2);
7337 break;
7338 default:
7339 abort ();
7340 break;
331d2d0d 7341 }
0f10071e 7342
29b0f896
AM		 7343 /* Put out high byte first: can't use md_number_to_chars! */
7344 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7345 *p = i.tm.base_opcode & 0xff;
7346 }
3e73aa7c 7347
29b0f896 7348 /* Now the modrm byte and sib byte (if present). */
40fb9820 7349 if (i.tm.opcode_modifier.modrm)
29b0f896 7350 {
4a3523fa
L		 7351 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7352 | i.rm.reg << 3
7353 | i.rm.mode << 6));
29b0f896
AM		 7354 /* If i.rm.regmem == ESP (4)
7355 && i.rm.mode != (Register mode)
7356 && not 16 bit
7357 ==> need second modrm byte. */
7358 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7359 && i.rm.mode != 3
40fb9820 7360 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7361 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7362 | i.sib.index << 3
7363 | i.sib.scale << 6));
29b0f896 7364 }
3e73aa7c 7365
29b0f896 7366 if (i.disp_operands)
2bbd9c25 7367 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7368
29b0f896 7369 if (i.imm_operands)
2bbd9c25 7370 output_imm (insn_start_frag, insn_start_off);
29b0f896 7371 }
252b5132 7372
29b0f896
AM		 7373#ifdef DEBUG386
7374 if (flag_debug)
7375 {
7b81dfbb 7376 pi ("" /*line*/, &i);
29b0f896
AM		 7377 }
7378#endif /* DEBUG386 */
7379}
252b5132 7380
e205caa7
L		 7381/* Return the size of the displacement operand N. */
7382
7383static int
7384disp_size (unsigned int n)
7385{
7386 int size = 4;
43234a1e
L		 7387
7388 /* Vec_Disp8 has to be 8bit. */
7389 if (i.types[n].bitfield.vec_disp8)
7390 size = 1;
7391 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7392 size = 8;
7393 else if (i.types[n].bitfield.disp8)
7394 size = 1;
7395 else if (i.types[n].bitfield.disp16)
7396 size = 2;
e205caa7
L		 7397 return size;
7398}
7399
7400/* Return the size of the immediate operand N. */
7401
7402static int
7403imm_size (unsigned int n)
7404{
7405 int size = 4;
40fb9820
L		 7406 if (i.types[n].bitfield.imm64)
7407 size = 8;
7408 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7409 size = 1;
7410 else if (i.types[n].bitfield.imm16)
7411 size = 2;
e205caa7
L		 7412 return size;
7413}
7414
29b0f896 7415static void
64e74474 7416output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7417{
7418 char *p;
7419 unsigned int n;
252b5132 7420
29b0f896
AM		 7421 for (n = 0; n < i.operands; n++)
7422 {
43234a1e
L		 7423 if (i.types[n].bitfield.vec_disp8
7424 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7425 {
7426 if (i.op[n].disps->X_op == O_constant)
7427 {
e205caa7 7428 int size = disp_size (n);
43234a1e 7429 offsetT val = i.op[n].disps->X_add_number;
252b5132 7430
43234a1e
L		 7431 if (i.types[n].bitfield.vec_disp8)
7432 val >>= i.memshift;
7433 val = offset_in_range (val, size);
29b0f896
AM		 7434 p = frag_more (size);
7435 md_number_to_chars (p, val, size);
7436 }
7437 else
7438 {
f86103b7 7439 enum bfd_reloc_code_real reloc_type;
e205caa7 7440 int size = disp_size (n);
40fb9820 7441 int sign = i.types[n].bitfield.disp32s;
29b0f896 7442 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7443 fixS *fixP;
29b0f896 7444
e205caa7 7445 /* We can't have 8 bit displacement here. */
9c2799c2 7446 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7447
29b0f896
AM		 7448 /* The PC relative address is computed relative
7449 to the instruction boundary, so in case immediate
7450 fields follows, we need to adjust the value. */
7451 if (pcrel && i.imm_operands)
7452 {
29b0f896 7453 unsigned int n1;
e205caa7 7454 int sz = 0;
252b5132 7455
29b0f896 7456 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7457 if (operand_type_check (i.types[n1], imm))
252b5132 7458 {
e205caa7
L		 7459 /* Only one immediate is allowed for PC
7460 relative address. */
9c2799c2 7461 gas_assert (sz == 0);
e205caa7
L		 7462 sz = imm_size (n1);
7463 i.op[n].disps->X_add_number -= sz;
252b5132 7464 }
29b0f896 7465 /* We should find the immediate. */
9c2799c2 7466 gas_assert (sz != 0);
29b0f896 7467 }
520dc8e8 7468
29b0f896 7469 p = frag_more (size);
d258b828 7470 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7471 if (GOT_symbol
2bbd9c25 7472 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7473 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7474 || reloc_type == BFD_RELOC_X86_64_32S
7475 || (reloc_type == BFD_RELOC_64
7476 && object_64bit))
d6ab8113
JB		 7477 && (i.op[n].disps->X_op == O_symbol
7478 || (i.op[n].disps->X_op == O_add
7479 && ((symbol_get_value_expression
7480 (i.op[n].disps->X_op_symbol)->X_op)
7481 == O_subtract))))
7482 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7483 {
7484 offsetT add;
7485
7486 if (insn_start_frag == frag_now)
7487 add = (p - frag_now->fr_literal) - insn_start_off;
7488 else
7489 {
7490 fragS *fr;
7491
7492 add = insn_start_frag->fr_fix - insn_start_off;
7493 for (fr = insn_start_frag->fr_next;
7494 fr && fr != frag_now; fr = fr->fr_next)
7495 add += fr->fr_fix;
7496 add += p - frag_now->fr_literal;
7497 }
7498
4fa24527 7499 if (!object_64bit)
7b81dfbb
AJ		 7500 {
7501 reloc_type = BFD_RELOC_386_GOTPC;
7502 i.op[n].imms->X_add_number += add;
7503 }
7504 else if (reloc_type == BFD_RELOC_64)
7505 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7506 else
7b81dfbb
AJ		 7507 /* Don't do the adjustment for x86-64, as there
7508 the pcrel addressing is relative to the _next_
7509 insn, and that is taken care of in other code. */
d6ab8113 7510 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7511 }
02a86693
L		 7512 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7513 size, i.op[n].disps, pcrel,
7514 reloc_type);
7515 /* Check for "call/jmp *mem", "mov mem, %reg",
7516 "test %reg, mem" and "binop mem, %reg" where binop
7517 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7518 instructions. Always generate R_386_GOT32X for
7519 "sym*GOT" operand in 32-bit mode. */
7520 if ((generate_relax_relocations
7521 || (!object_64bit
7522 && i.rm.mode == 0
7523 && i.rm.regmem == 5))
7524 && (i.rm.mode == 2
7525 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7526 && ((i.operands == 1
7527 && i.tm.base_opcode == 0xff
7528 && (i.rm.reg == 2 || i.rm.reg == 4))
7529 || (i.operands == 2
7530 && (i.tm.base_opcode == 0x8b
7531 || i.tm.base_opcode == 0x85
7532 || (i.tm.base_opcode & 0xc7) == 0x03))))
7533 {
7534 if (object_64bit)
7535 {
7536 fixP->fx_tcbit = i.rex != 0;
7537 if (i.base_reg
7538 && (i.base_reg->reg_num == RegRip
7539 || i.base_reg->reg_num == RegEip))
7540 fixP->fx_tcbit2 = 1;
7541 }
7542 else
7543 fixP->fx_tcbit2 = 1;
7544 }
29b0f896
AM		 7545 }
7546 }
7547 }
7548}
252b5132 7549
29b0f896 7550static void
64e74474 7551output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7552{
7553 char *p;
7554 unsigned int n;
252b5132 7555
29b0f896
AM		 7556 for (n = 0; n < i.operands; n++)
7557 {
43234a1e
L		 7558 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7559 if (i.rounding && (int) n == i.rounding->operand)
7560 continue;
7561
40fb9820 7562 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7563 {
7564 if (i.op[n].imms->X_op == O_constant)
7565 {
e205caa7 7566 int size = imm_size (n);
29b0f896 7567 offsetT val;
b4cac588 7568
29b0f896
AM		 7569 val = offset_in_range (i.op[n].imms->X_add_number,
7570 size);
7571 p = frag_more (size);
7572 md_number_to_chars (p, val, size);
7573 }
7574 else
7575 {
7576 /* Not absolute_section.
7577 Need a 32-bit fixup (don't support 8bit
7578 non-absolute imms). Try to support other
7579 sizes ... */
f86103b7 7580 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7581 int size = imm_size (n);
7582 int sign;
29b0f896 7583
40fb9820 7584 if (i.types[n].bitfield.imm32s
a7d61044 7585 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7586 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7587 sign = 1;
e205caa7
L		 7588 else
7589 sign = 0;
520dc8e8 7590
29b0f896 7591 p = frag_more (size);
d258b828 7592 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7593
2bbd9c25
JJ		 7594 /* This is tough to explain. We end up with this one if we
7595 * have operands that look like
7596 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7597 * obtain the absolute address of the GOT, and it is strongly
7598 * preferable from a performance point of view to avoid using
7599 * a runtime relocation for this. The actual sequence of
7600 * instructions often look something like:
7601 *
7602 * call .L66
7603 * .L66:
7604 * popl %ebx
7605 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7606 *
7607 * The call and pop essentially return the absolute address
7608 * of the label .L66 and store it in %ebx. The linker itself
7609 * will ultimately change the first operand of the addl so
7610 * that %ebx points to the GOT, but to keep things simple, the
7611 * .o file must have this operand set so that it generates not
7612 * the absolute address of .L66, but the absolute address of
7613 * itself. This allows the linker itself simply treat a GOTPC
7614 * relocation as asking for a pcrel offset to the GOT to be
7615 * added in, and the addend of the relocation is stored in the
7616 * operand field for the instruction itself.
7617 *
7618 * Our job here is to fix the operand so that it would add
7619 * the correct offset so that %ebx would point to itself. The
7620 * thing that is tricky is that .-.L66 will point to the
7621 * beginning of the instruction, so we need to further modify
7622 * the operand so that it will point to itself. There are
7623 * other cases where you have something like:
7624 *
7625 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7626 *
7627 * and here no correction would be required. Internally in
7628 * the assembler we treat operands of this form as not being
7629 * pcrel since the '.' is explicitly mentioned, and I wonder
7630 * whether it would simplify matters to do it this way. Who
7631 * knows. In earlier versions of the PIC patches, the
7632 * pcrel_adjust field was used to store the correction, but
7633 * since the expression is not pcrel, I felt it would be
7634 * confusing to do it this way. */
7635
d6ab8113 7636 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7637 || reloc_type == BFD_RELOC_X86_64_32S
7638 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7639 && GOT_symbol
7640 && GOT_symbol == i.op[n].imms->X_add_symbol
7641 && (i.op[n].imms->X_op == O_symbol
7642 || (i.op[n].imms->X_op == O_add
7643 && ((symbol_get_value_expression
7644 (i.op[n].imms->X_op_symbol)->X_op)
7645 == O_subtract))))
7646 {
2bbd9c25
JJ		 7647 offsetT add;
7648
7649 if (insn_start_frag == frag_now)
7650 add = (p - frag_now->fr_literal) - insn_start_off;
7651 else
7652 {
7653 fragS *fr;
7654
7655 add = insn_start_frag->fr_fix - insn_start_off;
7656 for (fr = insn_start_frag->fr_next;
7657 fr && fr != frag_now; fr = fr->fr_next)
7658 add += fr->fr_fix;
7659 add += p - frag_now->fr_literal;
7660 }
7661
4fa24527 7662 if (!object_64bit)
d6ab8113 7663 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7664 else if (size == 4)
d6ab8113 7665 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7666 else if (size == 8)
7667 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7668 i.op[n].imms->X_add_number += add;
29b0f896 7669 }
29b0f896
AM		 7670 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7671 i.op[n].imms, 0, reloc_type);
7672 }
7673 }
7674 }
252b5132
RH		 7675}
7676\f
d182319b
JB		 7677/* x86_cons_fix_new is called via the expression parsing code when a
7678 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7679static int cons_sign = -1;
7680
7681void
e3bb37b5 7682x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7683 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7684{
d258b828 7685 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7686
7687#ifdef TE_PE
7688 if (exp->X_op == O_secrel)
7689 {
7690 exp->X_op = O_symbol;
7691 r = BFD_RELOC_32_SECREL;
7692 }
7693#endif
7694
7695 fix_new_exp (frag, off, len, exp, 0, r);
7696}
7697
357d1bd8
L		 7698/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7699 purpose of the `.dc.a' internal pseudo-op. */
7700
7701int
7702x86_address_bytes (void)
7703{
7704 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7705 return 4;
7706 return stdoutput->arch_info->bits_per_address / 8;
7707}
7708
d382c579
TG		 7709#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7710 || defined (LEX_AT)
d258b828 7711# define lex_got(reloc, adjust, types) NULL
718ddfc0 7712#else
f3c180ae
AM		 7713/* Parse operands of the form
7714 <symbol>@GOTOFF+<nnn>
7715 and similar .plt or .got references.
7716
7717 If we find one, set up the correct relocation in RELOC and copy the
7718 input string, minus the `@GOTOFF' into a malloc'd buffer for
7719 parsing by the calling routine. Return this buffer, and if ADJUST
7720 is non-null set it to the length of the string we removed from the
7721 input line. Otherwise return NULL. */
7722static char *
91d6fa6a 7723lex_got (enum bfd_reloc_code_real *rel,
64e74474 7724 int *adjust,
d258b828 7725 i386_operand_type *types)
f3c180ae 7726{
7b81dfbb
AJ		 7727 /* Some of the relocations depend on the size of what field is to
7728 be relocated. But in our callers i386_immediate and i386_displacement
7729 we don't yet know the operand size (this will be set by insn
7730 matching). Hence we record the word32 relocation here,
7731 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7732 static const struct {
7733 const char *str;
cff8d58a 7734 int len;
4fa24527 7735 const enum bfd_reloc_code_real rel[2];
40fb9820 7736 const i386_operand_type types64;
f3c180ae 7737 } gotrel[] = {
8ce3d284 7738#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7739 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7740 BFD_RELOC_SIZE32 },
7741 OPERAND_TYPE_IMM32_64 },
8ce3d284 7742#endif
cff8d58a
L		 7743 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7744 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7745 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7746 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7747 BFD_RELOC_X86_64_PLT32 },
40fb9820 7748 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7749 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7750 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7751 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7752 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7753 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7754 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7755 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7756 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7757 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7758 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7759 BFD_RELOC_X86_64_TLSGD },
40fb9820 7760 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7761 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7762 _dummy_first_bfd_reloc_code_real },
40fb9820 7763 OPERAND_TYPE_NONE },
cff8d58a
L		 7764 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7765 BFD_RELOC_X86_64_TLSLD },
40fb9820 7766 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7767 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7768 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7769 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7770 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7771 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7772 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7773 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7774 _dummy_first_bfd_reloc_code_real },
40fb9820 7775 OPERAND_TYPE_NONE },
cff8d58a
L		 7776 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7777 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7778 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7779 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7780 _dummy_first_bfd_reloc_code_real },
40fb9820 7781 OPERAND_TYPE_NONE },
cff8d58a
L		 7782 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7783 _dummy_first_bfd_reloc_code_real },
40fb9820 7784 OPERAND_TYPE_NONE },
cff8d58a
L		 7785 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7786 BFD_RELOC_X86_64_GOT32 },
40fb9820 7787 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7788 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7789 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7790 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7791 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7792 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7793 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7794 };
7795 char *cp;
7796 unsigned int j;
7797
d382c579 7798#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7799 if (!IS_ELF)
7800 return NULL;
d382c579 7801#endif
718ddfc0 7802
f3c180ae 7803 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7804 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7805 return NULL;
7806
47465058 7807 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7808 {
cff8d58a 7809 int len = gotrel[j].len;
28f81592 7810 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7811 {
4fa24527 7812 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7813 {
28f81592
AM		 7814 int first, second;
7815 char *tmpbuf, *past_reloc;
f3c180ae 7816
91d6fa6a 7817 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7818
3956db08
JB		 7819 if (types)
7820 {
7821 if (flag_code != CODE_64BIT)
40fb9820
L		 7822 {
7823 types->bitfield.imm32 = 1;
7824 types->bitfield.disp32 = 1;
7825 }
3956db08
JB		 7826 else
7827 *types = gotrel[j].types64;
7828 }
7829
8fd4256d 7830 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7831 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7832
28f81592 7833 /* The length of the first part of our input line. */
f3c180ae 7834 first = cp - input_line_pointer;
28f81592
AM		 7835
7836 /* The second part goes from after the reloc token until
67c11a9b 7837 (and including) an end_of_line char or comma. */
28f81592 7838 past_reloc = cp + 1 + len;
67c11a9b
AM		 7839 cp = past_reloc;
7840 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7841 ++cp;
7842 second = cp + 1 - past_reloc;
28f81592
AM		 7843
7844 /* Allocate and copy string. The trailing NUL shouldn't
7845 be necessary, but be safe. */
add39d23 7846 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7847 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7848 if (second != 0 && *past_reloc != ' ')
7849 /* Replace the relocation token with ' ', so that
7850 errors like foo@GOTOFF1 will be detected. */
7851 tmpbuf[first++] = ' ';
af89796a
L		 7852 else
7853 /* Increment length by 1 if the relocation token is
7854 removed. */
7855 len++;
7856 if (adjust)
7857 *adjust = len;
0787a12d
AM		 7858 memcpy (tmpbuf + first, past_reloc, second);
7859 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7860 return tmpbuf;
7861 }
7862
4fa24527
JB		 7863 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7864 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7865 return NULL;
7866 }
7867 }
7868
7869 /* Might be a symbol version string. Don't as_bad here. */
7870 return NULL;
7871}
4e4f7c87 7872#endif
f3c180ae 7873
a988325c
NC		 7874#ifdef TE_PE
7875#ifdef lex_got
7876#undef lex_got
7877#endif
7878/* Parse operands of the form
7879 <symbol>@SECREL32+<nnn>
7880
7881 If we find one, set up the correct relocation in RELOC and copy the
7882 input string, minus the `@SECREL32' into a malloc'd buffer for
7883 parsing by the calling routine. Return this buffer, and if ADJUST
7884 is non-null set it to the length of the string we removed from the
34bca508
L		 7885 input line. Otherwise return NULL.
7886
a988325c
NC		 7887 This function is copied from the ELF version above adjusted for PE targets. */
7888
7889static char *
7890lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7891 int *adjust ATTRIBUTE_UNUSED,
d258b828 7892 i386_operand_type *types)
a988325c
NC		 7893{
7894 static const struct
7895 {
7896 const char *str;
7897 int len;
7898 const enum bfd_reloc_code_real rel[2];
7899 const i386_operand_type types64;
7900 }
7901 gotrel[] =
7902 {
7903 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7904 BFD_RELOC_32_SECREL },
7905 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7906 };
7907
7908 char *cp;
7909 unsigned j;
7910
7911 for (cp = input_line_pointer; *cp != '@'; cp++)
7912 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7913 return NULL;
7914
7915 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7916 {
7917 int len = gotrel[j].len;
7918
7919 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7920 {
7921 if (gotrel[j].rel[object_64bit] != 0)
7922 {
7923 int first, second;
7924 char *tmpbuf, *past_reloc;
7925
7926 *rel = gotrel[j].rel[object_64bit];
7927 if (adjust)
7928 *adjust = len;
7929
7930 if (types)
7931 {
7932 if (flag_code != CODE_64BIT)
7933 {
7934 types->bitfield.imm32 = 1;
7935 types->bitfield.disp32 = 1;
7936 }
7937 else
7938 *types = gotrel[j].types64;
7939 }
7940
7941 /* The length of the first part of our input line. */
7942 first = cp - input_line_pointer;
7943
7944 /* The second part goes from after the reloc token until
7945 (and including) an end_of_line char or comma. */
7946 past_reloc = cp + 1 + len;
7947 cp = past_reloc;
7948 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7949 ++cp;
7950 second = cp + 1 - past_reloc;
7951
7952 /* Allocate and copy string. The trailing NUL shouldn't
7953 be necessary, but be safe. */
add39d23 7954 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7955 memcpy (tmpbuf, input_line_pointer, first);
7956 if (second != 0 && *past_reloc != ' ')
7957 /* Replace the relocation token with ' ', so that
7958 errors like foo@SECLREL321 will be detected. */
7959 tmpbuf[first++] = ' ';
7960 memcpy (tmpbuf + first, past_reloc, second);
7961 tmpbuf[first + second] = '\0';
7962 return tmpbuf;
7963 }
7964
7965 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7966 gotrel[j].str, 1 << (5 + object_64bit));
7967 return NULL;
7968 }
7969 }
7970
7971 /* Might be a symbol version string. Don't as_bad here. */
7972 return NULL;
7973}
7974
7975#endif /* TE_PE */
7976
62ebcb5c 7977bfd_reloc_code_real_type
e3bb37b5 7978x86_cons (expressionS *exp, int size)
f3c180ae 7979{
62ebcb5c
AM		 7980 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7981
ee86248c
JB		 7982 intel_syntax = -intel_syntax;
7983
3c7b9c2c 7984 exp->X_md = 0;
4fa24527 7985 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7986 {
7987 /* Handle @GOTOFF and the like in an expression. */
7988 char *save;
7989 char *gotfree_input_line;
4a57f2cf 7990 int adjust = 0;
f3c180ae
AM		 7991
7992 save = input_line_pointer;
d258b828 7993 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7994 if (gotfree_input_line)
7995 input_line_pointer = gotfree_input_line;
7996
7997 expression (exp);
7998
7999 if (gotfree_input_line)
8000 {
8001 /* expression () has merrily parsed up to the end of line,
8002 or a comma - in the wrong buffer. Transfer how far
8003 input_line_pointer has moved to the right buffer. */
8004 input_line_pointer = (save
8005 + (input_line_pointer - gotfree_input_line)
8006 + adjust);
8007 free (gotfree_input_line);
3992d3b7
AM		 8008 if (exp->X_op == O_constant
8009 || exp->X_op == O_absent
8010 || exp->X_op == O_illegal
0398aac5 8011 || exp->X_op == O_register
3992d3b7
AM		 8012 || exp->X_op == O_big)
8013 {
8014 char c = *input_line_pointer;
8015 *input_line_pointer = 0;
8016 as_bad (_("missing or invalid expression `%s'"), save);
8017 *input_line_pointer = c;
8018 }
f3c180ae
AM		 8019 }
8020 }
8021 else
8022 expression (exp);
ee86248c
JB		 8023
8024 intel_syntax = -intel_syntax;
8025
8026 if (intel_syntax)
8027 i386_intel_simplify (exp);
62ebcb5c
AM		 8028
8029 return got_reloc;
f3c180ae 8030}
f3c180ae 8031
9f32dd5b
L		 8032static void
8033signed_cons (int size)
6482c264 8034{
d182319b
JB		 8035 if (flag_code == CODE_64BIT)
8036 cons_sign = 1;
8037 cons (size);
8038 cons_sign = -1;
6482c264
NC		 8039}
8040
d182319b 8041#ifdef TE_PE
6482c264 8042static void
7016a5d5 8043pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8044{
8045 expressionS exp;
8046
8047 do
8048 {
8049 expression (&exp);
8050 if (exp.X_op == O_symbol)
8051 exp.X_op = O_secrel;
8052
8053 emit_expr (&exp, 4);
8054 }
8055 while (*input_line_pointer++ == ',');
8056
8057 input_line_pointer--;
8058 demand_empty_rest_of_line ();
8059}
6482c264
NC		 8060#endif
8061
43234a1e
L		 8062/* Handle Vector operations. */
8063
8064static char *
8065check_VecOperations (char *op_string, char *op_end)
8066{
8067 const reg_entry *mask;
8068 const char *saved;
8069 char *end_op;
8070
8071 while (*op_string
8072 && (op_end == NULL || op_string < op_end))
8073 {
8074 saved = op_string;
8075 if (*op_string == '{')
8076 {
8077 op_string++;
8078
8079 /* Check broadcasts. */
8080 if (strncmp (op_string, "1to", 3) == 0)
8081 {
8082 int bcst_type;
8083
8084 if (i.broadcast)
8085 goto duplicated_vec_op;
8086
8087 op_string += 3;
8088 if (*op_string == '8')
8089 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8090 else if (*op_string == '4')
8091 bcst_type = BROADCAST_1TO4;
8092 else if (*op_string == '2')
8093 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8094 else if (*op_string == '1'
8095 && *(op_string+1) == '6')
8096 {
8097 bcst_type = BROADCAST_1TO16;
8098 op_string++;
8099 }
8100 else
8101 {
8102 as_bad (_("Unsupported broadcast: `%s'"), saved);
8103 return NULL;
8104 }
8105 op_string++;
8106
8107 broadcast_op.type = bcst_type;
8108 broadcast_op.operand = this_operand;
8109 i.broadcast = &broadcast_op;
8110 }
8111 /* Check masking operation. */
8112 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8113 {
8114 /* k0 can't be used for write mask. */
8115 if (mask->reg_num == 0)
8116 {
8117 as_bad (_("`%s' can't be used for write mask"),
8118 op_string);
8119 return NULL;
8120 }
8121
8122 if (!i.mask)
8123 {
8124 mask_op.mask = mask;
8125 mask_op.zeroing = 0;
8126 mask_op.operand = this_operand;
8127 i.mask = &mask_op;
8128 }
8129 else
8130 {
8131 if (i.mask->mask)
8132 goto duplicated_vec_op;
8133
8134 i.mask->mask = mask;
8135
8136 /* Only "{z}" is allowed here. No need to check
8137 zeroing mask explicitly. */
8138 if (i.mask->operand != this_operand)
8139 {
8140 as_bad (_("invalid write mask `%s'"), saved);
8141 return NULL;
8142 }
8143 }
8144
8145 op_string = end_op;
8146 }
8147 /* Check zeroing-flag for masking operation. */
8148 else if (*op_string == 'z')
8149 {
8150 if (!i.mask)
8151 {
8152 mask_op.mask = NULL;
8153 mask_op.zeroing = 1;
8154 mask_op.operand = this_operand;
8155 i.mask = &mask_op;
8156 }
8157 else
8158 {
8159 if (i.mask->zeroing)
8160 {
8161 duplicated_vec_op:
8162 as_bad (_("duplicated `%s'"), saved);
8163 return NULL;
8164 }
8165
8166 i.mask->zeroing = 1;
8167
8168 /* Only "{%k}" is allowed here. No need to check mask
8169 register explicitly. */
8170 if (i.mask->operand != this_operand)
8171 {
8172 as_bad (_("invalid zeroing-masking `%s'"),
8173 saved);
8174 return NULL;
8175 }
8176 }
8177
8178 op_string++;
8179 }
8180 else
8181 goto unknown_vec_op;
8182
8183 if (*op_string != '}')
8184 {
8185 as_bad (_("missing `}' in `%s'"), saved);
8186 return NULL;
8187 }
8188 op_string++;
8189 continue;
8190 }
8191 unknown_vec_op:
8192 /* We don't know this one. */
8193 as_bad (_("unknown vector operation: `%s'"), saved);
8194 return NULL;
8195 }
8196
8197 return op_string;
8198}
8199
252b5132 8200static int
70e41ade 8201i386_immediate (char *imm_start)
252b5132
RH		 8202{
8203 char *save_input_line_pointer;
f3c180ae 8204 char *gotfree_input_line;
252b5132 8205 segT exp_seg = 0;
47926f60 8206 expressionS *exp;
40fb9820
L		 8207 i386_operand_type types;
8208
0dfbf9d7 8209 operand_type_set (&types, ~0);
252b5132
RH		 8210
8211 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8212 {
31b2323c
L		 8213 as_bad (_("at most %d immediate operands are allowed"),
8214 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8215 return 0;
8216 }
8217
8218 exp = &im_expressions[i.imm_operands++];
520dc8e8 8219 i.op[this_operand].imms = exp;
252b5132
RH		 8220
8221 if (is_space_char (*imm_start))
8222 ++imm_start;
8223
8224 save_input_line_pointer = input_line_pointer;
8225 input_line_pointer = imm_start;
8226
d258b828 8227 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8228 if (gotfree_input_line)
8229 input_line_pointer = gotfree_input_line;
252b5132
RH		 8230
8231 exp_seg = expression (exp);
8232
83183c0c 8233 SKIP_WHITESPACE ();
43234a1e
L		 8234
8235 /* Handle vector operations. */
8236 if (*input_line_pointer == '{')
8237 {
8238 input_line_pointer = check_VecOperations (input_line_pointer,
8239 NULL);
8240 if (input_line_pointer == NULL)
8241 return 0;
8242 }
8243
252b5132 8244 if (*input_line_pointer)
f3c180ae 8245 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8246
8247 input_line_pointer = save_input_line_pointer;
f3c180ae 8248 if (gotfree_input_line)
ee86248c
JB		 8249 {
8250 free (gotfree_input_line);
8251
8252 if (exp->X_op == O_constant || exp->X_op == O_register)
8253 exp->X_op = O_illegal;
8254 }
8255
8256 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8257}
252b5132 8258
ee86248c
JB		 8259static int
8260i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8261 i386_operand_type types, const char *imm_start)
8262{
8263 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8264 {
313c53d1
L		 8265 if (imm_start)
8266 as_bad (_("missing or invalid immediate expression `%s'"),
8267 imm_start);
3992d3b7 8268 return 0;
252b5132 8269 }
3e73aa7c 8270 else if (exp->X_op == O_constant)
252b5132 8271 {
47926f60 8272 /* Size it properly later. */
40fb9820 8273 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8274 /* If not 64bit, sign extend val. */
8275 if (flag_code != CODE_64BIT
4eed87de
AM		 8276 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8277 exp->X_add_number
8278 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8279 }
4c63da97 8280#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8281 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8282 && exp_seg != absolute_section
47926f60 8283 && exp_seg != text_section
24eab124
AM		 8284 && exp_seg != data_section
8285 && exp_seg != bss_section
8286 && exp_seg != undefined_section
f86103b7 8287 && !bfd_is_com_section (exp_seg))
252b5132 8288 {
d0b47220 8289 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8290 return 0;
8291 }
8292#endif
a841bdf5 8293 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8294 {
313c53d1
L		 8295 if (imm_start)
8296 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8297 return 0;
8298 }
252b5132
RH		 8299 else
8300 {
8301 /* This is an address. The size of the address will be
24eab124 8302 determined later, depending on destination register,
3e73aa7c 8303 suffix, or the default for the section. */
40fb9820
L		 8304 i.types[this_operand].bitfield.imm8 = 1;
8305 i.types[this_operand].bitfield.imm16 = 1;
8306 i.types[this_operand].bitfield.imm32 = 1;
8307 i.types[this_operand].bitfield.imm32s = 1;
8308 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8309 i.types[this_operand] = operand_type_and (i.types[this_operand],
8310 types);
252b5132
RH		 8311 }
8312
8313 return 1;
8314}
8315
551c1ca1 8316static char *
e3bb37b5 8317i386_scale (char *scale)
252b5132 8318{
551c1ca1
AM		 8319 offsetT val;
8320 char *save = input_line_pointer;
252b5132 8321
551c1ca1
AM		 8322 input_line_pointer = scale;
8323 val = get_absolute_expression ();
8324
8325 switch (val)
252b5132 8326 {
551c1ca1 8327 case 1:
252b5132
RH		 8328 i.log2_scale_factor = 0;
8329 break;
551c1ca1 8330 case 2:
252b5132
RH		 8331 i.log2_scale_factor = 1;
8332 break;
551c1ca1 8333 case 4:
252b5132
RH		 8334 i.log2_scale_factor = 2;
8335 break;
551c1ca1 8336 case 8:
252b5132
RH		 8337 i.log2_scale_factor = 3;
8338 break;
8339 default:
a724f0f4
JB		 8340 {
8341 char sep = *input_line_pointer;
8342
8343 *input_line_pointer = '\0';
8344 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8345 scale);
8346 *input_line_pointer = sep;
8347 input_line_pointer = save;
8348 return NULL;
8349 }
252b5132 8350 }
29b0f896 8351 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8352 {
8353 as_warn (_("scale factor of %d without an index register"),
24eab124 8354 1 << i.log2_scale_factor);
252b5132 8355 i.log2_scale_factor = 0;
252b5132 8356 }
551c1ca1
AM		 8357 scale = input_line_pointer;
8358 input_line_pointer = save;
8359 return scale;
252b5132
RH		 8360}
8361
252b5132 8362static int
e3bb37b5 8363i386_displacement (char *disp_start, char *disp_end)
252b5132 8364{
29b0f896 8365 expressionS *exp;
252b5132
RH		 8366 segT exp_seg = 0;
8367 char *save_input_line_pointer;
f3c180ae 8368 char *gotfree_input_line;
40fb9820
L		 8369 int override;
8370 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8371 int ret;
252b5132 8372
31b2323c
L		 8373 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8374 {
8375 as_bad (_("at most %d displacement operands are allowed"),
8376 MAX_MEMORY_OPERANDS);
8377 return 0;
8378 }
8379
0dfbf9d7 8380 operand_type_set (&bigdisp, 0);
40fb9820
L		 8381 if ((i.types[this_operand].bitfield.jumpabsolute)
8382 || (!current_templates->start->opcode_modifier.jump
8383 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8384 {
40fb9820 8385 bigdisp.bitfield.disp32 = 1;
e05278af 8386 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8387 if (flag_code == CODE_64BIT)
8388 {
8389 if (!override)
8390 {
8391 bigdisp.bitfield.disp32s = 1;
8392 bigdisp.bitfield.disp64 = 1;
8393 }
8394 }
8395 else if ((flag_code == CODE_16BIT) ^ override)
8396 {
8397 bigdisp.bitfield.disp32 = 0;
8398 bigdisp.bitfield.disp16 = 1;
8399 }
e05278af
JB		 8400 }
8401 else
8402 {
8403 /* For PC-relative branches, the width of the displacement
8404 is dependent upon data size, not address size. */
e05278af 8405 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8406 if (flag_code == CODE_64BIT)
8407 {
8408 if (override || i.suffix == WORD_MNEM_SUFFIX)
8409 bigdisp.bitfield.disp16 = 1;
8410 else
8411 {
8412 bigdisp.bitfield.disp32 = 1;
8413 bigdisp.bitfield.disp32s = 1;
8414 }
8415 }
8416 else
e05278af
JB		 8417 {
8418 if (!override)
8419 override = (i.suffix == (flag_code != CODE_16BIT
8420 ? WORD_MNEM_SUFFIX
8421 : LONG_MNEM_SUFFIX));
40fb9820
L		 8422 bigdisp.bitfield.disp32 = 1;
8423 if ((flag_code == CODE_16BIT) ^ override)
8424 {
8425 bigdisp.bitfield.disp32 = 0;
8426 bigdisp.bitfield.disp16 = 1;
8427 }
e05278af 8428 }
e05278af 8429 }
c6fb90c8
L		 8430 i.types[this_operand] = operand_type_or (i.types[this_operand],
8431 bigdisp);
252b5132
RH		 8432
8433 exp = &disp_expressions[i.disp_operands];
520dc8e8 8434 i.op[this_operand].disps = exp;
252b5132
RH		 8435 i.disp_operands++;
8436 save_input_line_pointer = input_line_pointer;
8437 input_line_pointer = disp_start;
8438 END_STRING_AND_SAVE (disp_end);
8439
8440#ifndef GCC_ASM_O_HACK
8441#define GCC_ASM_O_HACK 0
8442#endif
8443#if GCC_ASM_O_HACK
8444 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8445 if (i.types[this_operand].bitfield.baseIndex
24eab124 8446 && displacement_string_end[-1] == '+')
252b5132
RH		 8447 {
8448 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8449 constraint within gcc asm statements.
8450 For instance:
8451
8452 #define _set_tssldt_desc(n,addr,limit,type) \
8453 __asm__ __volatile__ ( \
8454 "movw %w2,%0\n\t" \
8455 "movw %w1,2+%0\n\t" \
8456 "rorl $16,%1\n\t" \
8457 "movb %b1,4+%0\n\t" \
8458 "movb %4,5+%0\n\t" \
8459 "movb $0,6+%0\n\t" \
8460 "movb %h1,7+%0\n\t" \
8461 "rorl $16,%1" \
8462 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8463
8464 This works great except that the output assembler ends
8465 up looking a bit weird if it turns out that there is
8466 no offset. You end up producing code that looks like:
8467
8468 #APP
8469 movw $235,(%eax)
8470 movw %dx,2+(%eax)
8471 rorl $16,%edx
8472 movb %dl,4+(%eax)
8473 movb $137,5+(%eax)
8474 movb $0,6+(%eax)
8475 movb %dh,7+(%eax)
8476 rorl $16,%edx
8477 #NO_APP
8478
47926f60 8479 So here we provide the missing zero. */
24eab124
AM		 8480
8481 *displacement_string_end = '0';
252b5132
RH		 8482 }
8483#endif
d258b828 8484 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8485 if (gotfree_input_line)
8486 input_line_pointer = gotfree_input_line;
252b5132 8487
24eab124 8488 exp_seg = expression (exp);
252b5132 8489
636c26b0
AM		 8490 SKIP_WHITESPACE ();
8491 if (*input_line_pointer)
8492 as_bad (_("junk `%s' after expression"), input_line_pointer);
8493#if GCC_ASM_O_HACK
8494 RESTORE_END_STRING (disp_end + 1);
8495#endif
636c26b0 8496 input_line_pointer = save_input_line_pointer;
636c26b0 8497 if (gotfree_input_line)
ee86248c
JB		 8498 {
8499 free (gotfree_input_line);
8500
8501 if (exp->X_op == O_constant || exp->X_op == O_register)
8502 exp->X_op = O_illegal;
8503 }
8504
8505 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8506
8507 RESTORE_END_STRING (disp_end);
8508
8509 return ret;
8510}
8511
8512static int
8513i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8514 i386_operand_type types, const char *disp_start)
8515{
8516 i386_operand_type bigdisp;
8517 int ret = 1;
636c26b0 8518
24eab124
AM		 8519 /* We do this to make sure that the section symbol is in
8520 the symbol table. We will ultimately change the relocation
47926f60 8521 to be relative to the beginning of the section. */
1ae12ab7 8522 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8523 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8524 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8525 {
636c26b0 8526 if (exp->X_op != O_symbol)
3992d3b7 8527 goto inv_disp;
636c26b0 8528
e5cb08ac 8529 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8530 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8531 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8532 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8533 exp->X_op = O_subtract;
8534 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8535 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8536 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8537 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8538 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8539 else
29b0f896 8540 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8541 }
252b5132 8542
3992d3b7
AM		 8543 else if (exp->X_op == O_absent
8544 || exp->X_op == O_illegal
ee86248c 8545 || exp->X_op == O_big)
2daf4fd8 8546 {
3992d3b7
AM		 8547 inv_disp:
8548 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8549 disp_start);
3992d3b7 8550 ret = 0;
2daf4fd8
AM		 8551 }
8552
0e1147d9
L		 8553 else if (flag_code == CODE_64BIT
8554 && !i.prefix[ADDR_PREFIX]
8555 && exp->X_op == O_constant)
8556 {
8557 /* Since displacement is signed extended to 64bit, don't allow
8558 disp32 and turn off disp32s if they are out of range. */
8559 i.types[this_operand].bitfield.disp32 = 0;
8560 if (!fits_in_signed_long (exp->X_add_number))
8561 {
8562 i.types[this_operand].bitfield.disp32s = 0;
8563 if (i.types[this_operand].bitfield.baseindex)
8564 {
8565 as_bad (_("0x%lx out range of signed 32bit displacement"),
8566 (long) exp->X_add_number);
8567 ret = 0;
8568 }
8569 }
8570 }
8571
4c63da97 8572#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8573 else if (exp->X_op != O_constant
8574 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8575 && exp_seg != absolute_section
8576 && exp_seg != text_section
8577 && exp_seg != data_section
8578 && exp_seg != bss_section
8579 && exp_seg != undefined_section
8580 && !bfd_is_com_section (exp_seg))
24eab124 8581 {
d0b47220 8582 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8583 ret = 0;
24eab124 8584 }
252b5132 8585#endif
3956db08 8586
40fb9820
L		 8587 /* Check if this is a displacement only operand. */
8588 bigdisp = i.types[this_operand];
8589 bigdisp.bitfield.disp8 = 0;
8590 bigdisp.bitfield.disp16 = 0;
8591 bigdisp.bitfield.disp32 = 0;
8592 bigdisp.bitfield.disp32s = 0;
8593 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8594 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8595 i.types[this_operand] = operand_type_and (i.types[this_operand],
8596 types);
3956db08 8597
3992d3b7 8598 return ret;
252b5132
RH		 8599}
8600
eecb386c 8601/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8602 Return 1 on success, 0 on a failure. */
8603
252b5132 8604static int
e3bb37b5 8605i386_index_check (const char *operand_string)
252b5132 8606{
fc0763e6 8607 const char *kind = "base/index";
be05d201
L		 8608 enum flag_code addr_mode;
8609
8610 if (i.prefix[ADDR_PREFIX])
8611 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8612 else
8613 {
8614 addr_mode = flag_code;
8615
24eab124 8616#if INFER_ADDR_PREFIX
be05d201
L		 8617 if (i.mem_operands == 0)
8618 {
8619 /* Infer address prefix from the first memory operand. */
8620 const reg_entry *addr_reg = i.base_reg;
8621
8622 if (addr_reg == NULL)
8623 addr_reg = i.index_reg;
eecb386c 8624
be05d201
L		 8625 if (addr_reg)
8626 {
8627 if (addr_reg->reg_num == RegEip
8628 || addr_reg->reg_num == RegEiz
8629 || addr_reg->reg_type.bitfield.reg32)
8630 addr_mode = CODE_32BIT;
8631 else if (flag_code != CODE_64BIT
8632 && addr_reg->reg_type.bitfield.reg16)
8633 addr_mode = CODE_16BIT;
8634
8635 if (addr_mode != flag_code)
8636 {
8637 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8638 i.prefixes += 1;
8639 /* Change the size of any displacement too. At most one
8640 of Disp16 or Disp32 is set.
8641 FIXME. There doesn't seem to be any real need for
8642 separate Disp16 and Disp32 flags. The same goes for
8643 Imm16 and Imm32. Removing them would probably clean
8644 up the code quite a lot. */
8645 if (flag_code != CODE_64BIT
8646 && (i.types[this_operand].bitfield.disp16
8647 || i.types[this_operand].bitfield.disp32))
8648 i.types[this_operand]
8649 = operand_type_xor (i.types[this_operand], disp16_32);
8650 }
8651 }
8652 }
24eab124 8653#endif
be05d201
L		 8654 }
8655
fc0763e6
JB		 8656 if (current_templates->start->opcode_modifier.isstring
8657 && !current_templates->start->opcode_modifier.immext
8658 && (current_templates->end[-1].opcode_modifier.isstring
8659 || i.mem_operands))
8660 {
8661 /* Memory operands of string insns are special in that they only allow
8662 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8663 const reg_entry *expected_reg;
8664 static const char *di_si[][2] =
8665 {
8666 { "esi", "edi" },
8667 { "si", "di" },
8668 { "rsi", "rdi" }
8669 };
8670 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8671
8672 kind = "string address";
8673
8325cc63 8674 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8675 {
8676 i386_operand_type type = current_templates->end[-1].operand_types[0];
8677
8678 if (!type.bitfield.baseindex
8679 || ((!i.mem_operands != !intel_syntax)
8680 && current_templates->end[-1].operand_types[1]
8681 .bitfield.baseindex))
8682 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8683 expected_reg = hash_find (reg_hash,
8684 di_si[addr_mode][type.bitfield.esseg]);
8685
fc0763e6
JB		 8686 }
8687 else
be05d201 8688 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8689
be05d201
L		 8690 if (i.base_reg != expected_reg
8691 || i.index_reg
fc0763e6 8692 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8693 {
be05d201
L		 8694 /* The second memory operand must have the same size as
8695 the first one. */
8696 if (i.mem_operands
8697 && i.base_reg
8698 && !((addr_mode == CODE_64BIT
8699 && i.base_reg->reg_type.bitfield.reg64)
8700 || (addr_mode == CODE_32BIT
8701 ? i.base_reg->reg_type.bitfield.reg32
8702 : i.base_reg->reg_type.bitfield.reg16)))
8703 goto bad_address;
8704
fc0763e6
JB		 8705 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8706 operand_string,
8707 intel_syntax ? '[' : '(',
8708 register_prefix,
be05d201 8709 expected_reg->reg_name,
fc0763e6 8710 intel_syntax ? ']' : ')');
be05d201 8711 return 1;
fc0763e6 8712 }
be05d201
L		 8713 else
8714 return 1;
8715
8716bad_address:
8717 as_bad (_("`%s' is not a valid %s expression"),
8718 operand_string, kind);
8719 return 0;
3e73aa7c
JH		 8720 }
8721 else
8722 {
be05d201
L		 8723 if (addr_mode != CODE_16BIT)
8724 {
8725 /* 32-bit/64-bit checks. */
8726 if ((i.base_reg
8727 && (addr_mode == CODE_64BIT
8728 ? !i.base_reg->reg_type.bitfield.reg64
8729 : !i.base_reg->reg_type.bitfield.reg32)
8730 && (i.index_reg
8731 || (i.base_reg->reg_num
8732 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8733 || (i.index_reg
8734 && !i.index_reg->reg_type.bitfield.regxmm
8735 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8736 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8737 && ((addr_mode == CODE_64BIT
8738 ? !(i.index_reg->reg_type.bitfield.reg64
8739 || i.index_reg->reg_num == RegRiz)
8740 : !(i.index_reg->reg_type.bitfield.reg32
8741 || i.index_reg->reg_num == RegEiz))
8742 || !i.index_reg->reg_type.bitfield.baseindex)))
8743 goto bad_address;
8178be5b
JB		 8744
8745 /* bndmk, bndldx, and bndstx have special restrictions. */
8746 if (current_templates->start->base_opcode == 0xf30f1b
8747 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8748 {
8749 /* They cannot use RIP-relative addressing. */
8750 if (i.base_reg && i.base_reg->reg_num == RegRip)
8751 {
8752 as_bad (_("`%s' cannot be used here"), operand_string);
8753 return 0;
8754 }
8755
8756 /* bndldx and bndstx ignore their scale factor. */
8757 if (current_templates->start->base_opcode != 0xf30f1b
8758 && i.log2_scale_factor)
8759 as_warn (_("register scaling is being ignored here"));
8760 }
be05d201
L		 8761 }
8762 else
3e73aa7c 8763 {
be05d201 8764 /* 16-bit checks. */
3e73aa7c 8765 if ((i.base_reg
40fb9820
L		 8766 && (!i.base_reg->reg_type.bitfield.reg16
8767 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8768 || (i.index_reg
40fb9820
L		 8769 && (!i.index_reg->reg_type.bitfield.reg16
8770 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8771 || !(i.base_reg
8772 && i.base_reg->reg_num < 6
8773 && i.index_reg->reg_num >= 6
8774 && i.log2_scale_factor == 0))))
be05d201 8775 goto bad_address;
3e73aa7c
JH		 8776 }
8777 }
be05d201 8778 return 1;
24eab124 8779}
252b5132 8780
43234a1e
L		 8781/* Handle vector immediates. */
8782
8783static int
8784RC_SAE_immediate (const char *imm_start)
8785{
8786 unsigned int match_found, j;
8787 const char *pstr = imm_start;
8788 expressionS *exp;
8789
8790 if (*pstr != '{')
8791 return 0;
8792
8793 pstr++;
8794 match_found = 0;
8795 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8796 {
8797 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8798 {
8799 if (!i.rounding)
8800 {
8801 rc_op.type = RC_NamesTable[j].type;
8802 rc_op.operand = this_operand;
8803 i.rounding = &rc_op;
8804 }
8805 else
8806 {
8807 as_bad (_("duplicated `%s'"), imm_start);
8808 return 0;
8809 }
8810 pstr += RC_NamesTable[j].len;
8811 match_found = 1;
8812 break;
8813 }
8814 }
8815 if (!match_found)
8816 return 0;
8817
8818 if (*pstr++ != '}')
8819 {
8820 as_bad (_("Missing '}': '%s'"), imm_start);
8821 return 0;
8822 }
8823 /* RC/SAE immediate string should contain nothing more. */;
8824 if (*pstr != 0)
8825 {
8826 as_bad (_("Junk after '}': '%s'"), imm_start);
8827 return 0;
8828 }
8829
8830 exp = &im_expressions[i.imm_operands++];
8831 i.op[this_operand].imms = exp;
8832
8833 exp->X_op = O_constant;
8834 exp->X_add_number = 0;
8835 exp->X_add_symbol = (symbolS *) 0;
8836 exp->X_op_symbol = (symbolS *) 0;
8837
8838 i.types[this_operand].bitfield.imm8 = 1;
8839 return 1;
8840}
8841
8325cc63
JB		 8842/* Only string instructions can have a second memory operand, so
8843 reduce current_templates to just those if it contains any. */
8844static int
8845maybe_adjust_templates (void)
8846{
8847 const insn_template *t;
8848
8849 gas_assert (i.mem_operands == 1);
8850
8851 for (t = current_templates->start; t < current_templates->end; ++t)
8852 if (t->opcode_modifier.isstring)
8853 break;
8854
8855 if (t < current_templates->end)
8856 {
8857 static templates aux_templates;
8858 bfd_boolean recheck;
8859
8860 aux_templates.start = t;
8861 for (; t < current_templates->end; ++t)
8862 if (!t->opcode_modifier.isstring)
8863 break;
8864 aux_templates.end = t;
8865
8866 /* Determine whether to re-check the first memory operand. */
8867 recheck = (aux_templates.start != current_templates->start
8868 || t != current_templates->end);
8869
8870 current_templates = &aux_templates;
8871
8872 if (recheck)
8873 {
8874 i.mem_operands = 0;
8875 if (i.memop1_string != NULL
8876 && i386_index_check (i.memop1_string) == 0)
8877 return 0;
8878 i.mem_operands = 1;
8879 }
8880 }
8881
8882 return 1;
8883}
8884
fc0763e6 8885/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8886 on error. */
252b5132 8887
252b5132 8888static int
a7619375 8889i386_att_operand (char *operand_string)
252b5132 8890{
af6bdddf
AM		 8891 const reg_entry *r;
8892 char *end_op;
24eab124 8893 char *op_string = operand_string;
252b5132 8894
24eab124 8895 if (is_space_char (*op_string))
252b5132
RH		 8896 ++op_string;
8897
24eab124 8898 /* We check for an absolute prefix (differentiating,
47926f60 8899 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8900 if (*op_string == ABSOLUTE_PREFIX)
8901 {
8902 ++op_string;
8903 if (is_space_char (*op_string))
8904 ++op_string;
40fb9820 8905 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8906 }
252b5132 8907
47926f60 8908 /* Check if operand is a register. */
4d1bb795 8909 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8910 {
40fb9820
L		 8911 i386_operand_type temp;
8912
24eab124
AM		 8913 /* Check for a segment override by searching for ':' after a
8914 segment register. */
8915 op_string = end_op;
8916 if (is_space_char (*op_string))
8917 ++op_string;
40fb9820
L		 8918 if (*op_string == ':'
8919 && (r->reg_type.bitfield.sreg2
8920 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8921 {
8922 switch (r->reg_num)
8923 {
8924 case 0:
8925 i.seg[i.mem_operands] = &es;
8926 break;
8927 case 1:
8928 i.seg[i.mem_operands] = &cs;
8929 break;
8930 case 2:
8931 i.seg[i.mem_operands] = &ss;
8932 break;
8933 case 3:
8934 i.seg[i.mem_operands] = &ds;
8935 break;
8936 case 4:
8937 i.seg[i.mem_operands] = &fs;
8938 break;
8939 case 5:
8940 i.seg[i.mem_operands] = &gs;
8941 break;
8942 }
252b5132 8943
24eab124 8944 /* Skip the ':' and whitespace. */
252b5132
RH		 8945 ++op_string;
8946 if (is_space_char (*op_string))
24eab124 8947 ++op_string;
252b5132 8948
24eab124
AM		 8949 if (!is_digit_char (*op_string)
8950 && !is_identifier_char (*op_string)
8951 && *op_string != '('
8952 && *op_string != ABSOLUTE_PREFIX)
8953 {
8954 as_bad (_("bad memory operand `%s'"), op_string);
8955 return 0;
8956 }
47926f60 8957 /* Handle case of %es:*foo. */
24eab124
AM		 8958 if (*op_string == ABSOLUTE_PREFIX)
8959 {
8960 ++op_string;
8961 if (is_space_char (*op_string))
8962 ++op_string;
40fb9820 8963 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8964 }
8965 goto do_memory_reference;
8966 }
43234a1e
L		 8967
8968 /* Handle vector operations. */
8969 if (*op_string == '{')
8970 {
8971 op_string = check_VecOperations (op_string, NULL);
8972 if (op_string == NULL)
8973 return 0;
8974 }
8975
24eab124
AM		 8976 if (*op_string)
8977 {
d0b47220 8978 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8979 return 0;
8980 }
40fb9820
L		 8981 temp = r->reg_type;
8982 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8983 i.types[this_operand] = operand_type_or (i.types[this_operand],
8984 temp);
7d5e4556 8985 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8986 i.op[this_operand].regs = r;
24eab124
AM		 8987 i.reg_operands++;
8988 }
af6bdddf
AM		 8989 else if (*op_string == REGISTER_PREFIX)
8990 {
8991 as_bad (_("bad register name `%s'"), op_string);
8992 return 0;
8993 }
24eab124 8994 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8995 {
24eab124 8996 ++op_string;
40fb9820 8997 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8998 {
d0b47220 8999 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9000 return 0;
9001 }
9002 if (!i386_immediate (op_string))
9003 return 0;
9004 }
43234a1e
L		 9005 else if (RC_SAE_immediate (operand_string))
9006 {
9007 /* If it is a RC or SAE immediate, do nothing. */
9008 ;
9009 }
24eab124
AM		 9010 else if (is_digit_char (*op_string)
9011 || is_identifier_char (*op_string)
d02603dc 9012 || *op_string == '"'
e5cb08ac 9013 || *op_string == '(')
24eab124 9014 {
47926f60 9015 /* This is a memory reference of some sort. */
af6bdddf 9016 char *base_string;
252b5132 9017
47926f60 9018 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9019 char *displacement_string_start;
9020 char *displacement_string_end;
43234a1e 9021 char *vop_start;
252b5132 9022
24eab124 9023 do_memory_reference:
8325cc63
JB		 9024 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9025 return 0;
24eab124 9026 if ((i.mem_operands == 1
40fb9820 9027 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9028 || i.mem_operands == 2)
9029 {
9030 as_bad (_("too many memory references for `%s'"),
9031 current_templates->start->name);
9032 return 0;
9033 }
252b5132 9034
24eab124
AM		 9035 /* Check for base index form. We detect the base index form by
9036 looking for an ')' at the end of the operand, searching
9037 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9038 after the '('. */
af6bdddf 9039 base_string = op_string + strlen (op_string);
c3332e24 9040
43234a1e
L		 9041 /* Handle vector operations. */
9042 vop_start = strchr (op_string, '{');
9043 if (vop_start && vop_start < base_string)
9044 {
9045 if (check_VecOperations (vop_start, base_string) == NULL)
9046 return 0;
9047 base_string = vop_start;
9048 }
9049
af6bdddf
AM		 9050 --base_string;
9051 if (is_space_char (*base_string))
9052 --base_string;
252b5132 9053
47926f60 9054 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9055 displacement_string_start = op_string;
9056 displacement_string_end = base_string + 1;
252b5132 9057
24eab124
AM		 9058 if (*base_string == ')')
9059 {
af6bdddf 9060 char *temp_string;
24eab124
AM		 9061 unsigned int parens_balanced = 1;
9062 /* We've already checked that the number of left & right ()'s are
47926f60 9063 equal, so this loop will not be infinite. */
24eab124
AM		 9064 do
9065 {
9066 base_string--;
9067 if (*base_string == ')')
9068 parens_balanced++;
9069 if (*base_string == '(')
9070 parens_balanced--;
9071 }
9072 while (parens_balanced);
c3332e24 9073
af6bdddf 9074 temp_string = base_string;
c3332e24 9075
24eab124 9076 /* Skip past '(' and whitespace. */
252b5132
RH		 9077 ++base_string;
9078 if (is_space_char (*base_string))
24eab124 9079 ++base_string;
252b5132 9080
af6bdddf 9081 if (*base_string == ','
4eed87de
AM		 9082 || ((i.base_reg = parse_register (base_string, &end_op))
9083 != NULL))
252b5132 9084 {
af6bdddf 9085 displacement_string_end = temp_string;
252b5132 9086
40fb9820 9087 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9088
af6bdddf 9089 if (i.base_reg)
24eab124 9090 {
24eab124
AM		 9091 base_string = end_op;
9092 if (is_space_char (*base_string))
9093 ++base_string;
af6bdddf
AM		 9094 }
9095
9096 /* There may be an index reg or scale factor here. */
9097 if (*base_string == ',')
9098 {
9099 ++base_string;
9100 if (is_space_char (*base_string))
9101 ++base_string;
9102
4eed87de
AM		 9103 if ((i.index_reg = parse_register (base_string, &end_op))
9104 != NULL)
24eab124 9105 {
af6bdddf 9106 base_string = end_op;
24eab124
AM		 9107 if (is_space_char (*base_string))
9108 ++base_string;
af6bdddf
AM		 9109 if (*base_string == ',')
9110 {
9111 ++base_string;
9112 if (is_space_char (*base_string))
9113 ++base_string;
9114 }
e5cb08ac 9115 else if (*base_string != ')')
af6bdddf 9116 {
4eed87de
AM		 9117 as_bad (_("expecting `,' or `)' "
9118 "after index register in `%s'"),
af6bdddf
AM		 9119 operand_string);
9120 return 0;
9121 }
24eab124 9122 }
af6bdddf 9123 else if (*base_string == REGISTER_PREFIX)
24eab124 9124 {
f76bf5e0
L		 9125 end_op = strchr (base_string, ',');
9126 if (end_op)
9127 *end_op = '\0';
af6bdddf 9128 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9129 return 0;
9130 }
252b5132 9131
47926f60 9132 /* Check for scale factor. */
551c1ca1 9133 if (*base_string != ')')
af6bdddf 9134 {
551c1ca1
AM		 9135 char *end_scale = i386_scale (base_string);
9136
9137 if (!end_scale)
af6bdddf 9138 return 0;
24eab124 9139
551c1ca1 9140 base_string = end_scale;
af6bdddf
AM		 9141 if (is_space_char (*base_string))
9142 ++base_string;
9143 if (*base_string != ')')
9144 {
4eed87de
AM		 9145 as_bad (_("expecting `)' "
9146 "after scale factor in `%s'"),
af6bdddf
AM		 9147 operand_string);
9148 return 0;
9149 }
9150 }
9151 else if (!i.index_reg)
24eab124 9152 {
4eed87de
AM		 9153 as_bad (_("expecting index register or scale factor "
9154 "after `,'; got '%c'"),
af6bdddf 9155 *base_string);
24eab124
AM		 9156 return 0;
9157 }
9158 }
af6bdddf 9159 else if (*base_string != ')')
24eab124 9160 {
4eed87de
AM		 9161 as_bad (_("expecting `,' or `)' "
9162 "after base register in `%s'"),
af6bdddf 9163 operand_string);
24eab124
AM		 9164 return 0;
9165 }
c3332e24 9166 }
af6bdddf 9167 else if (*base_string == REGISTER_PREFIX)
c3332e24 9168 {
f76bf5e0
L		 9169 end_op = strchr (base_string, ',');
9170 if (end_op)
9171 *end_op = '\0';
af6bdddf 9172 as_bad (_("bad register name `%s'"), base_string);
24eab124 9173 return 0;
c3332e24 9174 }
24eab124
AM		 9175 }
9176
9177 /* If there's an expression beginning the operand, parse it,
9178 assuming displacement_string_start and
9179 displacement_string_end are meaningful. */
9180 if (displacement_string_start != displacement_string_end)
9181 {
9182 if (!i386_displacement (displacement_string_start,
9183 displacement_string_end))
9184 return 0;
9185 }
9186
9187 /* Special case for (%dx) while doing input/output op. */
9188 if (i.base_reg
0dfbf9d7
L		 9189 && operand_type_equal (&i.base_reg->reg_type,
9190 &reg16_inoutportreg)
24eab124
AM		 9191 && i.index_reg == 0
9192 && i.log2_scale_factor == 0
9193 && i.seg[i.mem_operands] == 0
40fb9820 9194 && !operand_type_check (i.types[this_operand], disp))
24eab124 9195 {
65da13b5 9196 i.types[this_operand] = inoutportreg;
24eab124
AM		 9197 return 1;
9198 }
9199
eecb386c
AM		 9200 if (i386_index_check (operand_string) == 0)
9201 return 0;
5c07affc 9202 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9203 if (i.mem_operands == 0)
9204 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9205 i.mem_operands++;
9206 }
9207 else
ce8a8b2f
AM		 9208 {
9209 /* It's not a memory operand; argh! */
24eab124
AM		 9210 as_bad (_("invalid char %s beginning operand %d `%s'"),
9211 output_invalid (*op_string),
9212 this_operand + 1,
9213 op_string);
9214 return 0;
9215 }
47926f60 9216 return 1; /* Normal return. */
252b5132
RH		 9217}
9218\f
fa94de6b
RM		 9219/* Calculate the maximum variable size (i.e., excluding fr_fix)
9220 that an rs_machine_dependent frag may reach. */
9221
9222unsigned int
9223i386_frag_max_var (fragS *frag)
9224{
9225 /* The only relaxable frags are for jumps.
9226 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9227 gas_assert (frag->fr_type == rs_machine_dependent);
9228 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9229}
9230
b084df0b
L		 9231#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9232static int
8dcea932 9233elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9234{
9235 /* STT_GNU_IFUNC symbol must go through PLT. */
9236 if ((symbol_get_bfdsym (fr_symbol)->flags
9237 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9238 return 0;
9239
9240 if (!S_IS_EXTERNAL (fr_symbol))
9241 /* Symbol may be weak or local. */
9242 return !S_IS_WEAK (fr_symbol);
9243
8dcea932
L		 9244 /* Global symbols with non-default visibility can't be preempted. */
9245 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9246 return 1;
9247
9248 if (fr_var != NO_RELOC)
9249 switch ((enum bfd_reloc_code_real) fr_var)
9250 {
9251 case BFD_RELOC_386_PLT32:
9252 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9253 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9254 return 0;
9255 default:
9256 abort ();
9257 }
9258
b084df0b
L		 9259 /* Global symbols with default visibility in a shared library may be
9260 preempted by another definition. */
8dcea932 9261 return !shared;
b084df0b
L		 9262}
9263#endif
9264
ee7fcc42
AM		 9265/* md_estimate_size_before_relax()
9266
9267 Called just before relax() for rs_machine_dependent frags. The x86
9268 assembler uses these frags to handle variable size jump
9269 instructions.
9270
9271 Any symbol that is now undefined will not become defined.
9272 Return the correct fr_subtype in the frag.
9273 Return the initial "guess for variable size of frag" to caller.
9274 The guess is actually the growth beyond the fixed part. Whatever
9275 we do to grow the fixed or variable part contributes to our
9276 returned value. */
9277
252b5132 9278int
7016a5d5 9279md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9280{
252b5132 9281 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9282 check for un-relaxable symbols. On an ELF system, we can't relax
9283 an externally visible symbol, because it may be overridden by a
9284 shared library. */
9285 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9286#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9287 || (IS_ELF
8dcea932
L		 9288 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9289 fragP->fr_var))
fbeb56a4
DK		 9290#endif
9291#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9292 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9293 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9294#endif
9295 )
252b5132 9296 {
b98ef147
AM		 9297 /* Symbol is undefined in this segment, or we need to keep a
9298 reloc so that weak symbols can be overridden. */
9299 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9300 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9301 unsigned char *opcode;
9302 int old_fr_fix;
f6af82bd 9303
ee7fcc42 9304 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9305 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9306 else if (size == 2)
f6af82bd
AM		 9307 reloc_type = BFD_RELOC_16_PCREL;
9308 else
9309 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9310
ee7fcc42
AM		 9311 old_fr_fix = fragP->fr_fix;
9312 opcode = (unsigned char *) fragP->fr_opcode;
9313
fddf5b5b 9314 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9315 {
fddf5b5b
AM		 9316 case UNCOND_JUMP:
9317 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9318 opcode[0] = 0xe9;
252b5132 9319 fragP->fr_fix += size;
062cd5e7
AS		 9320 fix_new (fragP, old_fr_fix, size,
9321 fragP->fr_symbol,
9322 fragP->fr_offset, 1,
9323 reloc_type);
252b5132
RH		 9324 break;
9325
fddf5b5b 9326 case COND_JUMP86:
412167cb
AM		 9327 if (size == 2
9328 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9329 {
9330 /* Negate the condition, and branch past an
9331 unconditional jump. */
9332 opcode[0] ^= 1;
9333 opcode[1] = 3;
9334 /* Insert an unconditional jump. */
9335 opcode[2] = 0xe9;
9336 /* We added two extra opcode bytes, and have a two byte
9337 offset. */
9338 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9339 fix_new (fragP, old_fr_fix + 2, 2,
9340 fragP->fr_symbol,
9341 fragP->fr_offset, 1,
9342 reloc_type);
fddf5b5b
AM		 9343 break;
9344 }
9345 /* Fall through. */
9346
9347 case COND_JUMP:
412167cb
AM		 9348 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9349 {
3e02c1cc
AM		 9350 fixS *fixP;
9351
412167cb 9352 fragP->fr_fix += 1;
3e02c1cc
AM		 9353 fixP = fix_new (fragP, old_fr_fix, 1,
9354 fragP->fr_symbol,
9355 fragP->fr_offset, 1,
9356 BFD_RELOC_8_PCREL);
9357 fixP->fx_signed = 1;
412167cb
AM		 9358 break;
9359 }
93c2a809 9360
24eab124 9361 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9362 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9363 opcode[1] = opcode[0] + 0x10;
f6af82bd 9364 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9365 /* We've added an opcode byte. */
9366 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9367 fix_new (fragP, old_fr_fix + 1, size,
9368 fragP->fr_symbol,
9369 fragP->fr_offset, 1,
9370 reloc_type);
252b5132 9371 break;
fddf5b5b
AM		 9372
9373 default:
9374 BAD_CASE (fragP->fr_subtype);
9375 break;
252b5132
RH		 9376 }
9377 frag_wane (fragP);
ee7fcc42 9378 return fragP->fr_fix - old_fr_fix;
252b5132 9379 }
93c2a809 9380
93c2a809
AM		 9381 /* Guess size depending on current relax state. Initially the relax
9382 state will correspond to a short jump and we return 1, because
9383 the variable part of the frag (the branch offset) is one byte
9384 long. However, we can relax a section more than once and in that
9385 case we must either set fr_subtype back to the unrelaxed state,
9386 or return the value for the appropriate branch. */
9387 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9388}
9389
47926f60
KH		 9390/* Called after relax() is finished.
9391
9392 In: Address of frag.
9393 fr_type == rs_machine_dependent.
9394 fr_subtype is what the address relaxed to.
9395
9396 Out: Any fixSs and constants are set up.
9397 Caller will turn frag into a ".space 0". */
9398
252b5132 9399void
7016a5d5
TG		 9400md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9401 fragS *fragP)
252b5132 9402{
29b0f896 9403 unsigned char *opcode;
252b5132 9404 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9405 offsetT target_address;
9406 offsetT opcode_address;
252b5132 9407 unsigned int extension = 0;
847f7ad4 9408 offsetT displacement_from_opcode_start;
252b5132
RH		 9409
9410 opcode = (unsigned char *) fragP->fr_opcode;
9411
47926f60 9412 /* Address we want to reach in file space. */
252b5132 9413 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9414
47926f60 9415 /* Address opcode resides at in file space. */
252b5132
RH		 9416 opcode_address = fragP->fr_address + fragP->fr_fix;
9417
47926f60 9418 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9419 displacement_from_opcode_start = target_address - opcode_address;
9420
fddf5b5b 9421 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9422 {
47926f60
KH		 9423 /* Don't have to change opcode. */
9424 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9425 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9426 }
9427 else
9428 {
9429 if (no_cond_jump_promotion
9430 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9431 as_warn_where (fragP->fr_file, fragP->fr_line,
9432 _("long jump required"));
252b5132 9433
fddf5b5b
AM		 9434 switch (fragP->fr_subtype)
9435 {
9436 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9437 extension = 4; /* 1 opcode + 4 displacement */
9438 opcode[0] = 0xe9;
9439 where_to_put_displacement = &opcode[1];
9440 break;
252b5132 9441
fddf5b5b
AM		 9442 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9443 extension = 2; /* 1 opcode + 2 displacement */
9444 opcode[0] = 0xe9;
9445 where_to_put_displacement = &opcode[1];
9446 break;
252b5132 9447
fddf5b5b
AM		 9448 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9449 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9450 extension = 5; /* 2 opcode + 4 displacement */
9451 opcode[1] = opcode[0] + 0x10;
9452 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9453 where_to_put_displacement = &opcode[2];
9454 break;
252b5132 9455
fddf5b5b
AM		 9456 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9457 extension = 3; /* 2 opcode + 2 displacement */
9458 opcode[1] = opcode[0] + 0x10;
9459 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9460 where_to_put_displacement = &opcode[2];
9461 break;
252b5132 9462
fddf5b5b
AM		 9463 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9464 extension = 4;
9465 opcode[0] ^= 1;
9466 opcode[1] = 3;
9467 opcode[2] = 0xe9;
9468 where_to_put_displacement = &opcode[3];
9469 break;
9470
9471 default:
9472 BAD_CASE (fragP->fr_subtype);
9473 break;
9474 }
252b5132 9475 }
fddf5b5b 9476
7b81dfbb
AJ		 9477 /* If size if less then four we are sure that the operand fits,
9478 but if it's 4, then it could be that the displacement is larger
9479 then -/+ 2GB. */
9480 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9481 && object_64bit
9482 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9483 + ((addressT) 1 << 31))
9484 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9485 {
9486 as_bad_where (fragP->fr_file, fragP->fr_line,
9487 _("jump target out of range"));
9488 /* Make us emit 0. */
9489 displacement_from_opcode_start = extension;
9490 }
47926f60 9491 /* Now put displacement after opcode. */
252b5132
RH		 9492 md_number_to_chars ((char *) where_to_put_displacement,
9493 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9494 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9495 fragP->fr_fix += extension;
9496}
9497\f
7016a5d5 9498/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9499 by our caller that we have all the info we need to fix it up.
9500
7016a5d5
TG		 9501 Parameter valP is the pointer to the value of the bits.
9502
252b5132
RH		 9503 On the 386, immediates, displacements, and data pointers are all in
9504 the same (little-endian) format, so we don't need to care about which
9505 we are handling. */
9506
94f592af 9507void
7016a5d5 9508md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9509{
94f592af 9510 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9511 valueT value = *valP;
252b5132 9512
f86103b7 9513#if !defined (TE_Mach)
93382f6d
AM		 9514 if (fixP->fx_pcrel)
9515 {
9516 switch (fixP->fx_r_type)
9517 {
5865bb77
ILT		 9518 default:
9519 break;
9520
d6ab8113
JB		 9521 case BFD_RELOC_64:
9522 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9523 break;
93382f6d 9524 case BFD_RELOC_32:
ae8887b5 9525 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9526 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9527 break;
9528 case BFD_RELOC_16:
9529 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9530 break;
9531 case BFD_RELOC_8:
9532 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9533 break;
9534 }
9535 }
252b5132 9536
a161fe53 9537 if (fixP->fx_addsy != NULL
31312f95 9538 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9539 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9540 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9541 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9542 && !use_rela_relocations)
252b5132 9543 {
31312f95
AM		 9544 /* This is a hack. There should be a better way to handle this.
9545 This covers for the fact that bfd_install_relocation will
9546 subtract the current location (for partial_inplace, PC relative
9547 relocations); see more below. */
252b5132 9548#ifndef OBJ_AOUT
718ddfc0 9549 if (IS_ELF
252b5132
RH		 9550#ifdef TE_PE
9551 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9552#endif
9553 )
9554 value += fixP->fx_where + fixP->fx_frag->fr_address;
9555#endif
9556#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9557 if (IS_ELF)
252b5132 9558 {
6539b54b 9559 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9560
6539b54b 9561 if ((sym_seg == seg
2f66722d 9562 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9563 && sym_seg != absolute_section))
af65af87 9564 && !generic_force_reloc (fixP))
2f66722d
AM		 9565 {
9566 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9567 bfd_install_relocation subtracts them out again. I think
9568 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9569 it. FIXME. */
9570 value += fixP->fx_where + fixP->fx_frag->fr_address;
9571 }
252b5132
RH		 9572 }
9573#endif
9574#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9575 /* For some reason, the PE format does not store a
9576 section address offset for a PC relative symbol. */
9577 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9578 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9579 value += md_pcrel_from (fixP);
9580#endif
9581 }
fbeb56a4 9582#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9583 if (fixP->fx_addsy != NULL
9584 && S_IS_WEAK (fixP->fx_addsy)
9585 /* PR 16858: Do not modify weak function references. */
9586 && ! fixP->fx_pcrel)
fbeb56a4 9587 {
296a8689
NC		 9588#if !defined (TE_PEP)
9589 /* For x86 PE weak function symbols are neither PC-relative
9590 nor do they set S_IS_FUNCTION. So the only reliable way
9591 to detect them is to check the flags of their containing
9592 section. */
9593 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9594 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9595 ;
9596 else
9597#endif
fbeb56a4
DK		 9598 value -= S_GET_VALUE (fixP->fx_addsy);
9599 }
9600#endif
252b5132
RH		 9601
9602 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9603 and we must not disappoint it. */
252b5132 9604#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9605 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9606 switch (fixP->fx_r_type)
9607 {
9608 case BFD_RELOC_386_PLT32:
3e73aa7c 9609 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9610 /* Make the jump instruction point to the address of the operand. At
9611 runtime we merely add the offset to the actual PLT entry. */
9612 value = -4;
9613 break;
31312f95 9614
13ae64f3
JJ		 9615 case BFD_RELOC_386_TLS_GD:
9616 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9617 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9618 case BFD_RELOC_386_TLS_IE:
9619 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9620 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9621 case BFD_RELOC_X86_64_TLSGD:
9622 case BFD_RELOC_X86_64_TLSLD:
9623 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9624 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9625 value = 0; /* Fully resolved at runtime. No addend. */
9626 /* Fallthrough */
9627 case BFD_RELOC_386_TLS_LE:
9628 case BFD_RELOC_386_TLS_LDO_32:
9629 case BFD_RELOC_386_TLS_LE_32:
9630 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9631 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9632 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9633 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9634 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9635 break;
9636
67a4f2b7
AO		 9637 case BFD_RELOC_386_TLS_DESC_CALL:
9638 case BFD_RELOC_X86_64_TLSDESC_CALL:
9639 value = 0; /* Fully resolved at runtime. No addend. */
9640 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9641 fixP->fx_done = 0;
9642 return;
9643
47926f60
KH		 9644 case BFD_RELOC_VTABLE_INHERIT:
9645 case BFD_RELOC_VTABLE_ENTRY:
9646 fixP->fx_done = 0;
94f592af 9647 return;
47926f60
KH		 9648
9649 default:
9650 break;
9651 }
9652#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9653 *valP = value;
f86103b7 9654#endif /* !defined (TE_Mach) */
3e73aa7c 9655
3e73aa7c 9656 /* Are we finished with this relocation now? */
c6682705 9657 if (fixP->fx_addsy == NULL)
3e73aa7c 9658 fixP->fx_done = 1;
fbeb56a4
DK		 9659#if defined (OBJ_COFF) && defined (TE_PE)
9660 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9661 {
9662 fixP->fx_done = 0;
9663 /* Remember value for tc_gen_reloc. */
9664 fixP->fx_addnumber = value;
9665 /* Clear out the frag for now. */
9666 value = 0;
9667 }
9668#endif
3e73aa7c
JH		 9669 else if (use_rela_relocations)
9670 {
9671 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9672 /* Remember value for tc_gen_reloc. */
9673 fixP->fx_addnumber = value;
3e73aa7c
JH		 9674 value = 0;
9675 }
f86103b7 9676
94f592af 9677 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9678}
252b5132 9679\f
6d4af3c2 9680const char *
499ac353 9681md_atof (int type, char *litP, int *sizeP)
252b5132 9682{
499ac353
NC		 9683 /* This outputs the LITTLENUMs in REVERSE order;
9684 in accord with the bigendian 386. */
9685 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9686}
9687\f
2d545b82 9688static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9689
252b5132 9690static char *
e3bb37b5 9691output_invalid (int c)
252b5132 9692{
3882b010 9693 if (ISPRINT (c))
f9f21a03
L		 9694 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9695 "'%c'", c);
252b5132 9696 else
f9f21a03 9697 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9698 "(0x%x)", (unsigned char) c);
252b5132
RH		 9699 return output_invalid_buf;
9700}
9701
af6bdddf 9702/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9703
9704static const reg_entry *
4d1bb795 9705parse_real_register (char *reg_string, char **end_op)
252b5132 9706{
af6bdddf
AM		 9707 char *s = reg_string;
9708 char *p;
252b5132
RH		 9709 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9710 const reg_entry *r;
9711
9712 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9713 if (*s == REGISTER_PREFIX)
9714 ++s;
9715
9716 if (is_space_char (*s))
9717 ++s;
9718
9719 p = reg_name_given;
af6bdddf 9720 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9721 {
9722 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9723 return (const reg_entry *) NULL;
9724 s++;
252b5132
RH		 9725 }
9726
6588847e
DN		 9727 /* For naked regs, make sure that we are not dealing with an identifier.
9728 This prevents confusing an identifier like `eax_var' with register
9729 `eax'. */
9730 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9731 return (const reg_entry *) NULL;
9732
af6bdddf 9733 *end_op = s;
252b5132
RH		 9734
9735 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9736
5f47d35b 9737 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9738 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9739 {
5f47d35b
AM		 9740 if (is_space_char (*s))
9741 ++s;
9742 if (*s == '(')
9743 {
af6bdddf 9744 ++s;
5f47d35b
AM		 9745 if (is_space_char (*s))
9746 ++s;
9747 if (*s >= '0' && *s <= '7')
9748 {
db557034 9749 int fpr = *s - '0';
af6bdddf 9750 ++s;
5f47d35b
AM		 9751 if (is_space_char (*s))
9752 ++s;
9753 if (*s == ')')
9754 {
9755 *end_op = s + 1;
1e9cc1c2 9756 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9757 know (r);
9758 return r + fpr;
5f47d35b 9759 }
5f47d35b 9760 }
47926f60 9761 /* We have "%st(" then garbage. */
5f47d35b
AM		 9762 return (const reg_entry *) NULL;
9763 }
9764 }
9765
a60de03c
JB		 9766 if (r == NULL || allow_pseudo_reg)
9767 return r;
9768
0dfbf9d7 9769 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9770 return (const reg_entry *) NULL;
9771
192dc9c6
JB		 9772 if ((r->reg_type.bitfield.reg32
9773 || r->reg_type.bitfield.sreg3
9774 || r->reg_type.bitfield.control
9775 || r->reg_type.bitfield.debug
9776 || r->reg_type.bitfield.test)
9777 && !cpu_arch_flags.bitfield.cpui386)
9778 return (const reg_entry *) NULL;
9779
309d3373
JB		 9780 if (r->reg_type.bitfield.floatreg
9781 && !cpu_arch_flags.bitfield.cpu8087
9782 && !cpu_arch_flags.bitfield.cpu287
9783 && !cpu_arch_flags.bitfield.cpu387)
9784 return (const reg_entry *) NULL;
9785
1848e567 9786 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9787 return (const reg_entry *) NULL;
9788
1848e567 9789 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9790 return (const reg_entry *) NULL;
9791
1848e567 9792 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9793 return (const reg_entry *) NULL;
9794
1848e567
L		 9795 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9796 return (const reg_entry *) NULL;
9797
9798 if (r->reg_type.bitfield.regmask
9799 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9800 return (const reg_entry *) NULL;
9801
db51cc60 9802 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9803 if (!allow_index_reg
db51cc60
L		 9804 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9805 return (const reg_entry *) NULL;
9806
43234a1e
L		 9807 /* Upper 16 vector register is only available with VREX in 64bit
9808 mode. */
9809 if ((r->reg_flags & RegVRex))
9810 {
86fa6981
L		 9811 if (i.vec_encoding == vex_encoding_default)
9812 i.vec_encoding = vex_encoding_evex;
9813
43234a1e 9814 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9815 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9816 || flag_code != CODE_64BIT)
9817 return (const reg_entry *) NULL;
43234a1e
L		 9818 }
9819
a60de03c
JB		 9820 if (((r->reg_flags & (RegRex64 | RegRex))
9821 || r->reg_type.bitfield.reg64)
40fb9820 9822 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9823 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9824 && flag_code != CODE_64BIT)
20f0a1fc 9825 return (const reg_entry *) NULL;
1ae00879 9826
b7240065
JB		 9827 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9828 return (const reg_entry *) NULL;
9829
252b5132
RH		 9830 return r;
9831}
4d1bb795
JB		 9832
9833/* REG_STRING starts *before* REGISTER_PREFIX. */
9834
9835static const reg_entry *
9836parse_register (char *reg_string, char **end_op)
9837{
9838 const reg_entry *r;
9839
9840 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9841 r = parse_real_register (reg_string, end_op);
9842 else
9843 r = NULL;
9844 if (!r)
9845 {
9846 char *save = input_line_pointer;
9847 char c;
9848 symbolS *symbolP;
9849
9850 input_line_pointer = reg_string;
d02603dc 9851 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9852 symbolP = symbol_find (reg_string);
9853 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9854 {
9855 const expressionS *e = symbol_get_value_expression (symbolP);
9856
0398aac5 9857 know (e->X_op == O_register);
4eed87de 9858 know (e->X_add_number >= 0
c3fe08fa 9859 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9860 r = i386_regtab + e->X_add_number;
d3bb6b49 9861 if ((r->reg_flags & RegVRex))
86fa6981 9862 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9863 *end_op = input_line_pointer;
9864 }
9865 *input_line_pointer = c;
9866 input_line_pointer = save;
9867 }
9868 return r;
9869}
9870
9871int
9872i386_parse_name (char *name, expressionS *e, char *nextcharP)
9873{
9874 const reg_entry *r;
9875 char *end = input_line_pointer;
9876
9877 *end = *nextcharP;
9878 r = parse_register (name, &input_line_pointer);
9879 if (r && end <= input_line_pointer)
9880 {
9881 *nextcharP = *input_line_pointer;
9882 *input_line_pointer = 0;
9883 e->X_op = O_register;
9884 e->X_add_number = r - i386_regtab;
9885 return 1;
9886 }
9887 input_line_pointer = end;
9888 *end = 0;
ee86248c 9889 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9890}
9891
9892void
9893md_operand (expressionS *e)
9894{
ee86248c
JB		 9895 char *end;
9896 const reg_entry *r;
4d1bb795 9897
ee86248c
JB		 9898 switch (*input_line_pointer)
9899 {
9900 case REGISTER_PREFIX:
9901 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9902 if (r)
9903 {
9904 e->X_op = O_register;
9905 e->X_add_number = r - i386_regtab;
9906 input_line_pointer = end;
9907 }
ee86248c
JB		 9908 break;
9909
9910 case '[':
9c2799c2 9911 gas_assert (intel_syntax);
ee86248c
JB		 9912 end = input_line_pointer++;
9913 expression (e);
9914 if (*input_line_pointer == ']')
9915 {
9916 ++input_line_pointer;
9917 e->X_op_symbol = make_expr_symbol (e);
9918 e->X_add_symbol = NULL;
9919 e->X_add_number = 0;
9920 e->X_op = O_index;
9921 }
9922 else
9923 {
9924 e->X_op = O_absent;
9925 input_line_pointer = end;
9926 }
9927 break;
4d1bb795
JB		 9928 }
9929}
9930
252b5132 9931\f
4cc782b5 9932#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9933const char *md_shortopts = "kVQ:sqn";
252b5132 9934#else
12b55ccc 9935const char *md_shortopts = "qn";
252b5132 9936#endif
6e0b89ee 9937
3e73aa7c 9938#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9939#define OPTION_64 (OPTION_MD_BASE + 1)
9940#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9941#define OPTION_MARCH (OPTION_MD_BASE + 3)
9942#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9943#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9944#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9945#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9946#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9947#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9948#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9949#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9950#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9951#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9952#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9953#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9954#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9955#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9956#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9957#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9958#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9959#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9960#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9961#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9962#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9963#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9964
99ad8390
NC		 9965struct option md_longopts[] =
9966{
3e73aa7c 9967 {"32", no_argument, NULL, OPTION_32},
321098a5 9968#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9969 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9970 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9971#endif
9972#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9973 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9974 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9975#endif
b3b91714 9976 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9977 {"march", required_argument, NULL, OPTION_MARCH},
9978 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9979 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9980 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9981 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9982 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9983 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9984 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9985 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9986 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9987 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9988 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9989 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9990 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9991# if defined (TE_PE) || defined (TE_PEP)
9992 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9993#endif
d1982f93 9994 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9995 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9996 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9997 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9998 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9999 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10000 {NULL, no_argument, NULL, 0}
10001};
10002size_t md_longopts_size = sizeof (md_longopts);
10003
10004int
17b9d67d 10005md_parse_option (int c, const char *arg)
252b5132 10006{
91d6fa6a 10007 unsigned int j;
293f5f65 10008 char *arch, *next, *saved;
9103f4f4 10009
252b5132
RH		 10010 switch (c)
10011 {
12b55ccc
L		 10012 case 'n':
10013 optimize_align_code = 0;
10014 break;
10015
a38cf1db
AM		 10016 case 'q':
10017 quiet_warnings = 1;
252b5132
RH		 10018 break;
10019
10020#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10021 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10022 should be emitted or not. FIXME: Not implemented. */
10023 case 'Q':
252b5132
RH		 10024 break;
10025
10026 /* -V: SVR4 argument to print version ID. */
10027 case 'V':
10028 print_version_id ();
10029 break;
10030
a38cf1db
AM		 10031 /* -k: Ignore for FreeBSD compatibility. */
10032 case 'k':
252b5132 10033 break;
4cc782b5
ILT		 10034
10035 case 's':
10036 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10037 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10038 break;
8dcea932
L		 10039
10040 case OPTION_MSHARED:
10041 shared = 1;
10042 break;
99ad8390 10043#endif
321098a5 10044#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10045 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10046 case OPTION_64:
10047 {
10048 const char **list, **l;
10049
3e73aa7c
JH		 10050 list = bfd_target_list ();
10051 for (l = list; *l != NULL; l++)
8620418b 10052 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10053 || strcmp (*l, "coff-x86-64") == 0
10054 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10055 || strcmp (*l, "pei-x86-64") == 0
10056 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10057 {
10058 default_arch = "x86_64";
10059 break;
10060 }
3e73aa7c 10061 if (*l == NULL)
2b5d6a91 10062 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10063 free (list);
10064 }
10065 break;
10066#endif
252b5132 10067
351f65ca 10068#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10069 case OPTION_X32:
351f65ca
L		 10070 if (IS_ELF)
10071 {
10072 const char **list, **l;
10073
10074 list = bfd_target_list ();
10075 for (l = list; *l != NULL; l++)
10076 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10077 {
10078 default_arch = "x86_64:32";
10079 break;
10080 }
10081 if (*l == NULL)
2b5d6a91 10082 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10083 free (list);
10084 }
10085 else
10086 as_fatal (_("32bit x86_64 is only supported for ELF"));
10087 break;
10088#endif
10089
6e0b89ee
AM		 10090 case OPTION_32:
10091 default_arch = "i386";
10092 break;
10093
b3b91714
AM		 10094 case OPTION_DIVIDE:
10095#ifdef SVR4_COMMENT_CHARS
10096 {
10097 char *n, *t;
10098 const char *s;
10099
add39d23 10100 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10101 t = n;
10102 for (s = i386_comment_chars; *s != '\0'; s++)
10103 if (*s != '/')
10104 *t++ = *s;
10105 *t = '\0';
10106 i386_comment_chars = n;
10107 }
10108#endif
10109 break;
10110
9103f4f4 10111 case OPTION_MARCH:
293f5f65
L		 10112 saved = xstrdup (arg);
10113 arch = saved;
10114 /* Allow -march=+nosse. */
10115 if (*arch == '+')
10116 arch++;
6305a203 10117 do
9103f4f4 10118 {
6305a203 10119 if (*arch == '.')
2b5d6a91 10120 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10121 next = strchr (arch, '+');
10122 if (next)
10123 *next++ = '\0';
91d6fa6a 10124 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10125 {
91d6fa6a 10126 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10127 {
6305a203 10128 /* Processor. */
1ded5609
JB		 10129 if (! cpu_arch[j].flags.bitfield.cpui386)
10130 continue;
10131
91d6fa6a 10132 cpu_arch_name = cpu_arch[j].name;
6305a203 10133 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10134 cpu_arch_flags = cpu_arch[j].flags;
10135 cpu_arch_isa = cpu_arch[j].type;
10136 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10137 if (!cpu_arch_tune_set)
10138 {
10139 cpu_arch_tune = cpu_arch_isa;
10140 cpu_arch_tune_flags = cpu_arch_isa_flags;
10141 }
10142 break;
10143 }
91d6fa6a
NC		 10144 else if (*cpu_arch [j].name == '.'
10145 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10146 {
33eaf5de 10147 /* ISA extension. */
6305a203 10148 i386_cpu_flags flags;
309d3373 10149
293f5f65
L		 10150 flags = cpu_flags_or (cpu_arch_flags,
10151 cpu_arch[j].flags);
81486035 10152
5b64d091 10153 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10154 {
10155 if (cpu_sub_arch_name)
10156 {
10157 char *name = cpu_sub_arch_name;
10158 cpu_sub_arch_name = concat (name,
91d6fa6a 10159 cpu_arch[j].name,
1bf57e9f 10160 (const char *) NULL);
6305a203
L		 10161 free (name);
10162 }
10163 else
91d6fa6a 10164 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10165 cpu_arch_flags = flags;
a586129e 10166 cpu_arch_isa_flags = flags;
6305a203
L		 10167 }
10168 break;
ccc9c027 10169 }
9103f4f4 10170 }
6305a203 10171
293f5f65
L		 10172 if (j >= ARRAY_SIZE (cpu_arch))
10173 {
33eaf5de 10174 /* Disable an ISA extension. */
293f5f65
L		 10175 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10176 if (strcmp (arch, cpu_noarch [j].name) == 0)
10177 {
10178 i386_cpu_flags flags;
10179
10180 flags = cpu_flags_and_not (cpu_arch_flags,
10181 cpu_noarch[j].flags);
10182 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10183 {
10184 if (cpu_sub_arch_name)
10185 {
10186 char *name = cpu_sub_arch_name;
10187 cpu_sub_arch_name = concat (arch,
10188 (const char *) NULL);
10189 free (name);
10190 }
10191 else
10192 cpu_sub_arch_name = xstrdup (arch);
10193 cpu_arch_flags = flags;
10194 cpu_arch_isa_flags = flags;
10195 }
10196 break;
10197 }
10198
10199 if (j >= ARRAY_SIZE (cpu_noarch))
10200 j = ARRAY_SIZE (cpu_arch);
10201 }
10202
91d6fa6a 10203 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10204 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10205
10206 arch = next;
9103f4f4 10207 }
293f5f65
L		 10208 while (next != NULL);
10209 free (saved);
9103f4f4
L		 10210 break;
10211
10212 case OPTION_MTUNE:
10213 if (*arg == '.')
2b5d6a91 10214 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10215 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10216 {
91d6fa6a 10217 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10218 {
ccc9c027 10219 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10220 cpu_arch_tune = cpu_arch [j].type;
10221 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10222 break;
10223 }
10224 }
91d6fa6a 10225 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10226 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10227 break;
10228
1efbbeb4
L		 10229 case OPTION_MMNEMONIC:
10230 if (strcasecmp (arg, "att") == 0)
10231 intel_mnemonic = 0;
10232 else if (strcasecmp (arg, "intel") == 0)
10233 intel_mnemonic = 1;
10234 else
2b5d6a91 10235 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10236 break;
10237
10238 case OPTION_MSYNTAX:
10239 if (strcasecmp (arg, "att") == 0)
10240 intel_syntax = 0;
10241 else if (strcasecmp (arg, "intel") == 0)
10242 intel_syntax = 1;
10243 else
2b5d6a91 10244 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10245 break;
10246
10247 case OPTION_MINDEX_REG:
10248 allow_index_reg = 1;
10249 break;
10250
10251 case OPTION_MNAKED_REG:
10252 allow_naked_reg = 1;
10253 break;
10254
10255 case OPTION_MOLD_GCC:
10256 old_gcc = 1;
1efbbeb4
L		 10257 break;
10258
c0f3af97
L		 10259 case OPTION_MSSE2AVX:
10260 sse2avx = 1;
10261 break;
10262
daf50ae7
L		 10263 case OPTION_MSSE_CHECK:
10264 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10265 sse_check = check_error;
daf50ae7 10266 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10267 sse_check = check_warning;
daf50ae7 10268 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10269 sse_check = check_none;
daf50ae7 10270 else
2b5d6a91 10271 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10272 break;
10273
7bab8ab5
JB		 10274 case OPTION_MOPERAND_CHECK:
10275 if (strcasecmp (arg, "error") == 0)
10276 operand_check = check_error;
10277 else if (strcasecmp (arg, "warning") == 0)
10278 operand_check = check_warning;
10279 else if (strcasecmp (arg, "none") == 0)
10280 operand_check = check_none;
10281 else
10282 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10283 break;
10284
539f890d
L		 10285 case OPTION_MAVXSCALAR:
10286 if (strcasecmp (arg, "128") == 0)
10287 avxscalar = vex128;
10288 else if (strcasecmp (arg, "256") == 0)
10289 avxscalar = vex256;
10290 else
2b5d6a91 10291 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10292 break;
10293
7e8b059b
L		 10294 case OPTION_MADD_BND_PREFIX:
10295 add_bnd_prefix = 1;
10296 break;
10297
43234a1e
L		 10298 case OPTION_MEVEXLIG:
10299 if (strcmp (arg, "128") == 0)
10300 evexlig = evexl128;
10301 else if (strcmp (arg, "256") == 0)
10302 evexlig = evexl256;
10303 else if (strcmp (arg, "512") == 0)
10304 evexlig = evexl512;
10305 else
10306 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10307 break;
10308
d3d3c6db
IT		 10309 case OPTION_MEVEXRCIG:
10310 if (strcmp (arg, "rne") == 0)
10311 evexrcig = rne;
10312 else if (strcmp (arg, "rd") == 0)
10313 evexrcig = rd;
10314 else if (strcmp (arg, "ru") == 0)
10315 evexrcig = ru;
10316 else if (strcmp (arg, "rz") == 0)
10317 evexrcig = rz;
10318 else
10319 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10320 break;
10321
43234a1e
L		 10322 case OPTION_MEVEXWIG:
10323 if (strcmp (arg, "0") == 0)
10324 evexwig = evexw0;
10325 else if (strcmp (arg, "1") == 0)
10326 evexwig = evexw1;
10327 else
10328 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10329 break;
10330
167ad85b
TG		 10331# if defined (TE_PE) || defined (TE_PEP)
10332 case OPTION_MBIG_OBJ:
10333 use_big_obj = 1;
10334 break;
10335#endif
10336
d1982f93 10337 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10338 if (strcasecmp (arg, "yes") == 0)
10339 omit_lock_prefix = 1;
10340 else if (strcasecmp (arg, "no") == 0)
10341 omit_lock_prefix = 0;
10342 else
10343 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10344 break;
10345
e4e00185
AS		 10346 case OPTION_MFENCE_AS_LOCK_ADD:
10347 if (strcasecmp (arg, "yes") == 0)
10348 avoid_fence = 1;
10349 else if (strcasecmp (arg, "no") == 0)
10350 avoid_fence = 0;
10351 else
10352 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10353 break;
10354
0cb4071e
L		 10355 case OPTION_MRELAX_RELOCATIONS:
10356 if (strcasecmp (arg, "yes") == 0)
10357 generate_relax_relocations = 1;
10358 else if (strcasecmp (arg, "no") == 0)
10359 generate_relax_relocations = 0;
10360 else
10361 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10362 break;
10363
5db04b09 10364 case OPTION_MAMD64:
e89c5eaa 10365 intel64 = 0;
5db04b09
L		 10366 break;
10367
10368 case OPTION_MINTEL64:
e89c5eaa 10369 intel64 = 1;
5db04b09
L		 10370 break;
10371
252b5132
RH		 10372 default:
10373 return 0;
10374 }
10375 return 1;
10376}
10377
8a2c8fef
L		 10378#define MESSAGE_TEMPLATE \
10379" "
10380
293f5f65
L		 10381static char *
10382output_message (FILE *stream, char *p, char *message, char *start,
10383 int *left_p, const char *name, int len)
10384{
10385 int size = sizeof (MESSAGE_TEMPLATE);
10386 int left = *left_p;
10387
10388 /* Reserve 2 spaces for ", " or ",\0" */
10389 left -= len + 2;
10390
10391 /* Check if there is any room. */
10392 if (left >= 0)
10393 {
10394 if (p != start)
10395 {
10396 *p++ = ',';
10397 *p++ = ' ';
10398 }
10399 p = mempcpy (p, name, len);
10400 }
10401 else
10402 {
10403 /* Output the current message now and start a new one. */
10404 *p++ = ',';
10405 *p = '\0';
10406 fprintf (stream, "%s\n", message);
10407 p = start;
10408 left = size - (start - message) - len - 2;
10409
10410 gas_assert (left >= 0);
10411
10412 p = mempcpy (p, name, len);
10413 }
10414
10415 *left_p = left;
10416 return p;
10417}
10418
8a2c8fef 10419static void
1ded5609 10420show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10421{
10422 static char message[] = MESSAGE_TEMPLATE;
10423 char *start = message + 27;
10424 char *p;
10425 int size = sizeof (MESSAGE_TEMPLATE);
10426 int left;
10427 const char *name;
10428 int len;
10429 unsigned int j;
10430
10431 p = start;
10432 left = size - (start - message);
10433 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10434 {
10435 /* Should it be skipped? */
10436 if (cpu_arch [j].skip)
10437 continue;
10438
10439 name = cpu_arch [j].name;
10440 len = cpu_arch [j].len;
10441 if (*name == '.')
10442 {
10443 /* It is an extension. Skip if we aren't asked to show it. */
10444 if (ext)
10445 {
10446 name++;
10447 len--;
10448 }
10449 else
10450 continue;
10451 }
10452 else if (ext)
10453 {
10454 /* It is an processor. Skip if we show only extension. */
10455 continue;
10456 }
1ded5609
JB		 10457 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10458 {
10459 /* It is an impossible processor - skip. */
10460 continue;
10461 }
8a2c8fef 10462
293f5f65 10463 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10464 }
10465
293f5f65
L		 10466 /* Display disabled extensions. */
10467 if (ext)
10468 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10469 {
10470 name = cpu_noarch [j].name;
10471 len = cpu_noarch [j].len;
10472 p = output_message (stream, p, message, start, &left, name,
10473 len);
10474 }
10475
8a2c8fef
L		 10476 *p = '\0';
10477 fprintf (stream, "%s\n", message);
10478}
10479
252b5132 10480void
8a2c8fef 10481md_show_usage (FILE *stream)
252b5132 10482{
4cc782b5
ILT		 10483#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10484 fprintf (stream, _("\
a38cf1db
AM		 10485 -Q ignored\n\
10486 -V print assembler version number\n\
b3b91714
AM		 10487 -k ignored\n"));
10488#endif
10489 fprintf (stream, _("\
12b55ccc 10490 -n Do not optimize code alignment\n\
b3b91714
AM		 10491 -q quieten some warnings\n"));
10492#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10493 fprintf (stream, _("\
a38cf1db 10494 -s ignored\n"));
b3b91714 10495#endif
321098a5
L		 10496#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10497 || defined (TE_PE) || defined (TE_PEP))
751d281c 10498 fprintf (stream, _("\
570561f7 10499 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10500#endif
b3b91714
AM		 10501#ifdef SVR4_COMMENT_CHARS
10502 fprintf (stream, _("\
10503 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10504#else
10505 fprintf (stream, _("\
b3b91714 10506 --divide ignored\n"));
4cc782b5 10507#endif
9103f4f4 10508 fprintf (stream, _("\
6305a203 10509 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10510 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10511 show_arch (stream, 0, 1);
8a2c8fef
L		 10512 fprintf (stream, _("\
10513 EXTENSION is combination of:\n"));
1ded5609 10514 show_arch (stream, 1, 0);
6305a203 10515 fprintf (stream, _("\
8a2c8fef 10516 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10517 show_arch (stream, 0, 0);
ba104c83 10518 fprintf (stream, _("\
c0f3af97
L		 10519 -msse2avx encode SSE instructions with VEX prefix\n"));
10520 fprintf (stream, _("\
daf50ae7
L		 10521 -msse-check=[none|error|warning]\n\
10522 check SSE instructions\n"));
10523 fprintf (stream, _("\
7bab8ab5
JB		 10524 -moperand-check=[none|error|warning]\n\
10525 check operand combinations for validity\n"));
10526 fprintf (stream, _("\
539f890d
L		 10527 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10528 length\n"));
10529 fprintf (stream, _("\
43234a1e
L		 10530 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10531 length\n"));
10532 fprintf (stream, _("\
10533 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10534 for EVEX.W bit ignored instructions\n"));
10535 fprintf (stream, _("\
d3d3c6db
IT		 10536 -mevexrcig=[rne|rd|ru|rz]\n\
10537 encode EVEX instructions with specific EVEX.RC value\n\
10538 for SAE-only ignored instructions\n"));
10539 fprintf (stream, _("\
ba104c83
L		 10540 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10541 fprintf (stream, _("\
10542 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10543 fprintf (stream, _("\
10544 -mindex-reg support pseudo index registers\n"));
10545 fprintf (stream, _("\
10546 -mnaked-reg don't require `%%' prefix for registers\n"));
10547 fprintf (stream, _("\
10548 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10549 fprintf (stream, _("\
10550 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10551 fprintf (stream, _("\
10552 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10553# if defined (TE_PE) || defined (TE_PEP)
10554 fprintf (stream, _("\
10555 -mbig-obj generate big object files\n"));
10556#endif
d022bddd
IT		 10557 fprintf (stream, _("\
10558 -momit-lock-prefix=[no|yes]\n\
10559 strip all lock prefixes\n"));
5db04b09 10560 fprintf (stream, _("\
e4e00185
AS		 10561 -mfence-as-lock-add=[no|yes]\n\
10562 encode lfence, mfence and sfence as\n\
10563 lock addl $0x0, (%%{re}sp)\n"));
10564 fprintf (stream, _("\
0cb4071e
L		 10565 -mrelax-relocations=[no|yes]\n\
10566 generate relax relocations\n"));
10567 fprintf (stream, _("\
5db04b09
L		 10568 -mamd64 accept only AMD64 ISA\n"));
10569 fprintf (stream, _("\
10570 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10571}
10572
3e73aa7c 10573#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10574 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10575 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10576
10577/* Pick the target format to use. */
10578
47926f60 10579const char *
e3bb37b5 10580i386_target_format (void)
252b5132 10581{
351f65ca
L		 10582 if (!strncmp (default_arch, "x86_64", 6))
10583 {
10584 update_code_flag (CODE_64BIT, 1);
10585 if (default_arch[6] == '\0')
7f56bc95 10586 x86_elf_abi = X86_64_ABI;
351f65ca 10587 else
7f56bc95 10588 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10589 }
3e73aa7c 10590 else if (!strcmp (default_arch, "i386"))
78f12dd3 10591 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10592 else if (!strcmp (default_arch, "iamcu"))
10593 {
10594 update_code_flag (CODE_32BIT, 1);
10595 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10596 {
10597 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10598 cpu_arch_name = "iamcu";
10599 cpu_sub_arch_name = NULL;
10600 cpu_arch_flags = iamcu_flags;
10601 cpu_arch_isa = PROCESSOR_IAMCU;
10602 cpu_arch_isa_flags = iamcu_flags;
10603 if (!cpu_arch_tune_set)
10604 {
10605 cpu_arch_tune = cpu_arch_isa;
10606 cpu_arch_tune_flags = cpu_arch_isa_flags;
10607 }
10608 }
8d471ec1 10609 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10610 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10611 cpu_arch_name);
10612 }
3e73aa7c 10613 else
2b5d6a91 10614 as_fatal (_("unknown architecture"));
89507696
JB		 10615
10616 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10617 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10618 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10619 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10620
252b5132
RH		 10621 switch (OUTPUT_FLAVOR)
10622 {
9384f2ff 10623#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10624 case bfd_target_aout_flavour:
47926f60 10625 return AOUT_TARGET_FORMAT;
4c63da97 10626#endif
9384f2ff
AM		 10627#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10628# if defined (TE_PE) || defined (TE_PEP)
10629 case bfd_target_coff_flavour:
167ad85b
TG		 10630 if (flag_code == CODE_64BIT)
10631 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10632 else
10633 return "pe-i386";
9384f2ff 10634# elif defined (TE_GO32)
0561d57c
JK		 10635 case bfd_target_coff_flavour:
10636 return "coff-go32";
9384f2ff 10637# else
252b5132
RH		 10638 case bfd_target_coff_flavour:
10639 return "coff-i386";
9384f2ff 10640# endif
4c63da97 10641#endif
3e73aa7c 10642#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10643 case bfd_target_elf_flavour:
3e73aa7c 10644 {
351f65ca
L		 10645 const char *format;
10646
10647 switch (x86_elf_abi)
4fa24527 10648 {
351f65ca
L		 10649 default:
10650 format = ELF_TARGET_FORMAT;
10651 break;
7f56bc95 10652 case X86_64_ABI:
351f65ca 10653 use_rela_relocations = 1;
4fa24527 10654 object_64bit = 1;
351f65ca
L		 10655 format = ELF_TARGET_FORMAT64;
10656 break;
7f56bc95 10657 case X86_64_X32_ABI:
4fa24527 10658 use_rela_relocations = 1;
351f65ca 10659 object_64bit = 1;
862be3fb 10660 disallow_64bit_reloc = 1;
351f65ca
L		 10661 format = ELF_TARGET_FORMAT32;
10662 break;
4fa24527 10663 }
3632d14b 10664 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10665 {
7f56bc95 10666 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10667 as_fatal (_("Intel L1OM is 64bit only"));
10668 return ELF_TARGET_L1OM_FORMAT;
10669 }
b49f93f6 10670 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10671 {
10672 if (x86_elf_abi != X86_64_ABI)
10673 as_fatal (_("Intel K1OM is 64bit only"));
10674 return ELF_TARGET_K1OM_FORMAT;
10675 }
81486035
L		 10676 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10677 {
10678 if (x86_elf_abi != I386_ABI)
10679 as_fatal (_("Intel MCU is 32bit only"));
10680 return ELF_TARGET_IAMCU_FORMAT;
10681 }
8a9036a4 10682 else
351f65ca 10683 return format;
3e73aa7c 10684 }
e57f8c65
TG		 10685#endif
10686#if defined (OBJ_MACH_O)
10687 case bfd_target_mach_o_flavour:
d382c579
TG		 10688 if (flag_code == CODE_64BIT)
10689 {
10690 use_rela_relocations = 1;
10691 object_64bit = 1;
10692 return "mach-o-x86-64";
10693 }
10694 else
10695 return "mach-o-i386";
4c63da97 10696#endif
252b5132
RH		 10697 default:
10698 abort ();
10699 return NULL;
10700 }
10701}
10702
47926f60 10703#endif /* OBJ_MAYBE_ more than one */
252b5132 10704\f
252b5132 10705symbolS *
7016a5d5 10706md_undefined_symbol (char *name)
252b5132 10707{
18dc2407
ILT		 10708 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10709 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10710 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10711 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10712 {
10713 if (!GOT_symbol)
10714 {
10715 if (symbol_find (name))
10716 as_bad (_("GOT already in symbol table"));
10717 GOT_symbol = symbol_new (name, undefined_section,
10718 (valueT) 0, &zero_address_frag);
10719 };
10720 return GOT_symbol;
10721 }
252b5132
RH		 10722 return 0;
10723}
10724
10725/* Round up a section size to the appropriate boundary. */
47926f60 10726
252b5132 10727valueT
7016a5d5 10728md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10729{
4c63da97
AM		 10730#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10731 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10732 {
10733 /* For a.out, force the section size to be aligned. If we don't do
10734 this, BFD will align it for us, but it will not write out the
10735 final bytes of the section. This may be a bug in BFD, but it is
10736 easier to fix it here since that is how the other a.out targets
10737 work. */
10738 int align;
10739
10740 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10741 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10742 }
252b5132
RH		 10743#endif
10744
10745 return size;
10746}
10747
10748/* On the i386, PC-relative offsets are relative to the start of the
10749 next instruction. That is, the address of the offset, plus its
10750 size, since the offset is always the last part of the insn. */
10751
10752long
e3bb37b5 10753md_pcrel_from (fixS *fixP)
252b5132
RH		 10754{
10755 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10756}
10757
10758#ifndef I386COFF
10759
10760static void
e3bb37b5 10761s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10762{
29b0f896 10763 int temp;
252b5132 10764
8a75718c
JB		 10765#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10766 if (IS_ELF)
10767 obj_elf_section_change_hook ();
10768#endif
252b5132
RH		 10769 temp = get_absolute_expression ();
10770 subseg_set (bss_section, (subsegT) temp);
10771 demand_empty_rest_of_line ();
10772}
10773
10774#endif
10775
252b5132 10776void
e3bb37b5 10777i386_validate_fix (fixS *fixp)
252b5132 10778{
02a86693 10779 if (fixp->fx_subsy)
252b5132 10780 {
02a86693 10781 if (fixp->fx_subsy == GOT_symbol)
23df1078 10782 {
02a86693
L		 10783 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10784 {
10785 if (!object_64bit)
10786 abort ();
10787#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10788 if (fixp->fx_tcbit2)
56ceb5b5
L		 10789 fixp->fx_r_type = (fixp->fx_tcbit
10790 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10791 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10792 else
10793#endif
10794 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10795 }
d6ab8113 10796 else
02a86693
L		 10797 {
10798 if (!object_64bit)
10799 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10800 else
10801 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10802 }
10803 fixp->fx_subsy = 0;
23df1078 10804 }
252b5132 10805 }
02a86693
L		 10806#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10807 else if (!object_64bit)
10808 {
10809 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10810 && fixp->fx_tcbit2)
10811 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10812 }
10813#endif
252b5132
RH		 10814}
10815
252b5132 10816arelent *
7016a5d5 10817tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10818{
10819 arelent *rel;
10820 bfd_reloc_code_real_type code;
10821
10822 switch (fixp->fx_r_type)
10823 {
8ce3d284 10824#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10825 case BFD_RELOC_SIZE32:
10826 case BFD_RELOC_SIZE64:
10827 if (S_IS_DEFINED (fixp->fx_addsy)
10828 && !S_IS_EXTERNAL (fixp->fx_addsy))
10829 {
10830 /* Resolve size relocation against local symbol to size of
10831 the symbol plus addend. */
10832 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10833 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10834 && !fits_in_unsigned_long (value))
10835 as_bad_where (fixp->fx_file, fixp->fx_line,
10836 _("symbol size computation overflow"));
10837 fixp->fx_addsy = NULL;
10838 fixp->fx_subsy = NULL;
10839 md_apply_fix (fixp, (valueT *) &value, NULL);
10840 return NULL;
10841 }
8ce3d284 10842#endif
1a0670f3 10843 /* Fall through. */
8fd4256d 10844
3e73aa7c
JH		 10845 case BFD_RELOC_X86_64_PLT32:
10846 case BFD_RELOC_X86_64_GOT32:
10847 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10848 case BFD_RELOC_X86_64_GOTPCRELX:
10849 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10850 case BFD_RELOC_386_PLT32:
10851 case BFD_RELOC_386_GOT32:
02a86693 10852 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10853 case BFD_RELOC_386_GOTOFF:
10854 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10855 case BFD_RELOC_386_TLS_GD:
10856 case BFD_RELOC_386_TLS_LDM:
10857 case BFD_RELOC_386_TLS_LDO_32:
10858 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10859 case BFD_RELOC_386_TLS_IE:
10860 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10861 case BFD_RELOC_386_TLS_LE_32:
10862 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10863 case BFD_RELOC_386_TLS_GOTDESC:
10864 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10865 case BFD_RELOC_X86_64_TLSGD:
10866 case BFD_RELOC_X86_64_TLSLD:
10867 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10868 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10869 case BFD_RELOC_X86_64_GOTTPOFF:
10870 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10871 case BFD_RELOC_X86_64_TPOFF64:
10872 case BFD_RELOC_X86_64_GOTOFF64:
10873 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10874 case BFD_RELOC_X86_64_GOT64:
10875 case BFD_RELOC_X86_64_GOTPCREL64:
10876 case BFD_RELOC_X86_64_GOTPC64:
10877 case BFD_RELOC_X86_64_GOTPLT64:
10878 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10879 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10880 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10881 case BFD_RELOC_RVA:
10882 case BFD_RELOC_VTABLE_ENTRY:
10883 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10884#ifdef TE_PE
10885 case BFD_RELOC_32_SECREL:
10886#endif
252b5132
RH		 10887 code = fixp->fx_r_type;
10888 break;
dbbaec26
L		 10889 case BFD_RELOC_X86_64_32S:
10890 if (!fixp->fx_pcrel)
10891 {
10892 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10893 code = fixp->fx_r_type;
10894 break;
10895 }
1a0670f3 10896 /* Fall through. */
252b5132 10897 default:
93382f6d 10898 if (fixp->fx_pcrel)
252b5132 10899 {
93382f6d
AM		 10900 switch (fixp->fx_size)
10901 {
10902 default:
b091f402
AM		 10903 as_bad_where (fixp->fx_file, fixp->fx_line,
10904 _("can not do %d byte pc-relative relocation"),
10905 fixp->fx_size);
93382f6d
AM		 10906 code = BFD_RELOC_32_PCREL;
10907 break;
10908 case 1: code = BFD_RELOC_8_PCREL; break;
10909 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10910 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10911#ifdef BFD64
10912 case 8: code = BFD_RELOC_64_PCREL; break;
10913#endif
93382f6d
AM		 10914 }
10915 }
10916 else
10917 {
10918 switch (fixp->fx_size)
10919 {
10920 default:
b091f402
AM		 10921 as_bad_where (fixp->fx_file, fixp->fx_line,
10922 _("can not do %d byte relocation"),
10923 fixp->fx_size);
93382f6d
AM		 10924 code = BFD_RELOC_32;
10925 break;
10926 case 1: code = BFD_RELOC_8; break;
10927 case 2: code = BFD_RELOC_16; break;
10928 case 4: code = BFD_RELOC_32; break;
937149dd 10929#ifdef BFD64
3e73aa7c 10930 case 8: code = BFD_RELOC_64; break;
937149dd 10931#endif
93382f6d 10932 }
252b5132
RH		 10933 }
10934 break;
10935 }
252b5132 10936
d182319b
JB		 10937 if ((code == BFD_RELOC_32
10938 || code == BFD_RELOC_32_PCREL
10939 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10940 && GOT_symbol
10941 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10942 {
4fa24527 10943 if (!object_64bit)
d6ab8113
JB		 10944 code = BFD_RELOC_386_GOTPC;
10945 else
10946 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10947 }
7b81dfbb
AJ		 10948 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10949 && GOT_symbol
10950 && fixp->fx_addsy == GOT_symbol)
10951 {
10952 code = BFD_RELOC_X86_64_GOTPC64;
10953 }
252b5132 10954
add39d23
TS		 10955 rel = XNEW (arelent);
10956 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10957 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10958
10959 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10960
3e73aa7c
JH		 10961 if (!use_rela_relocations)
10962 {
10963 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10964 vtable entry to be used in the relocation's section offset. */
10965 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10966 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10967#if defined (OBJ_COFF) && defined (TE_PE)
10968 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10969 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10970 else
10971#endif
c6682705 10972 rel->addend = 0;
3e73aa7c
JH		 10973 }
10974 /* Use the rela in 64bit mode. */
252b5132 10975 else
3e73aa7c 10976 {
862be3fb
L		 10977 if (disallow_64bit_reloc)
10978 switch (code)
10979 {
862be3fb
L		 10980 case BFD_RELOC_X86_64_DTPOFF64:
10981 case BFD_RELOC_X86_64_TPOFF64:
10982 case BFD_RELOC_64_PCREL:
10983 case BFD_RELOC_X86_64_GOTOFF64:
10984 case BFD_RELOC_X86_64_GOT64:
10985 case BFD_RELOC_X86_64_GOTPCREL64:
10986 case BFD_RELOC_X86_64_GOTPC64:
10987 case BFD_RELOC_X86_64_GOTPLT64:
10988 case BFD_RELOC_X86_64_PLTOFF64:
10989 as_bad_where (fixp->fx_file, fixp->fx_line,
10990 _("cannot represent relocation type %s in x32 mode"),
10991 bfd_get_reloc_code_name (code));
10992 break;
10993 default:
10994 break;
10995 }
10996
062cd5e7
AS		 10997 if (!fixp->fx_pcrel)
10998 rel->addend = fixp->fx_offset;
10999 else
11000 switch (code)
11001 {
11002 case BFD_RELOC_X86_64_PLT32:
11003 case BFD_RELOC_X86_64_GOT32:
11004 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11005 case BFD_RELOC_X86_64_GOTPCRELX:
11006 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11007 case BFD_RELOC_X86_64_TLSGD:
11008 case BFD_RELOC_X86_64_TLSLD:
11009 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11010 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11011 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11012 rel->addend = fixp->fx_offset - fixp->fx_size;
11013 break;
11014 default:
11015 rel->addend = (section->vma
11016 - fixp->fx_size
11017 + fixp->fx_addnumber
11018 + md_pcrel_from (fixp));
11019 break;
11020 }
3e73aa7c
JH		 11021 }
11022
252b5132
RH		 11023 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11024 if (rel->howto == NULL)
11025 {
11026 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11027 _("cannot represent relocation type %s"),
252b5132
RH		 11028 bfd_get_reloc_code_name (code));
11029 /* Set howto to a garbage value so that we can keep going. */
11030 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11031 gas_assert (rel->howto != NULL);
252b5132
RH		 11032 }
11033
11034 return rel;
11035}
11036
ee86248c 11037#include "tc-i386-intel.c"
54cfded0 11038
a60de03c
JB		 11039void
11040tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11041{
a60de03c
JB		 11042 int saved_naked_reg;
11043 char saved_register_dot;
54cfded0 11044
a60de03c
JB		 11045 saved_naked_reg = allow_naked_reg;
11046 allow_naked_reg = 1;
11047 saved_register_dot = register_chars['.'];
11048 register_chars['.'] = '.';
11049 allow_pseudo_reg = 1;
11050 expression_and_evaluate (exp);
11051 allow_pseudo_reg = 0;
11052 register_chars['.'] = saved_register_dot;
11053 allow_naked_reg = saved_naked_reg;
11054
e96d56a1 11055 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11056 {
a60de03c
JB		 11057 if ((addressT) exp->X_add_number < i386_regtab_size)
11058 {
11059 exp->X_op = O_constant;
11060 exp->X_add_number = i386_regtab[exp->X_add_number]
11061 .dw2_regnum[flag_code >> 1];
11062 }
11063 else
11064 exp->X_op = O_illegal;
54cfded0 11065 }
54cfded0
AM		 11066}
11067
11068void
11069tc_x86_frame_initial_instructions (void)
11070{
a60de03c
JB		 11071 static unsigned int sp_regno[2];
11072
11073 if (!sp_regno[flag_code >> 1])
11074 {
11075 char *saved_input = input_line_pointer;
11076 char sp[][4] = {"esp", "rsp"};
11077 expressionS exp;
a4447b93 11078
a60de03c
JB		 11079 input_line_pointer = sp[flag_code >> 1];
11080 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11081 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11082 sp_regno[flag_code >> 1] = exp.X_add_number;
11083 input_line_pointer = saved_input;
11084 }
a4447b93 11085
61ff971f
L		 11086 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11087 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11088}
d2b2c203 11089
d7921315
L		 11090int
11091x86_dwarf2_addr_size (void)
11092{
11093#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11094 if (x86_elf_abi == X86_64_X32_ABI)
11095 return 4;
11096#endif
11097 return bfd_arch_bits_per_address (stdoutput) / 8;
11098}
11099
d2b2c203
DJ		 11100int
11101i386_elf_section_type (const char *str, size_t len)
11102{
11103 if (flag_code == CODE_64BIT
11104 && len == sizeof ("unwind") - 1
11105 && strncmp (str, "unwind", 6) == 0)
11106 return SHT_X86_64_UNWIND;
11107
11108 return -1;
11109}
bb41ade5 11110
ad5fec3b
EB		 11111#ifdef TE_SOLARIS
11112void
11113i386_solaris_fix_up_eh_frame (segT sec)
11114{
11115 if (flag_code == CODE_64BIT)
11116 elf_section_type (sec) = SHT_X86_64_UNWIND;
11117}
11118#endif
11119
bb41ade5
AM		 11120#ifdef TE_PE
11121void
11122tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11123{
91d6fa6a 11124 expressionS exp;
bb41ade5 11125
91d6fa6a
NC		 11126 exp.X_op = O_secrel;
11127 exp.X_add_symbol = symbol;
11128 exp.X_add_number = 0;
11129 emit_expr (&exp, size);
bb41ade5
AM		 11130}
11131#endif
3b22753a
L		 11132
11133#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11134/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11135
01e1a5bc 11136bfd_vma
6d4af3c2 11137x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11138{
11139 if (flag_code == CODE_64BIT)
11140 {
11141 if (letter == 'l')
11142 return SHF_X86_64_LARGE;
11143
8f3bae45 11144 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11145 }
3b22753a 11146 else
8f3bae45 11147 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11148 return -1;
11149}
11150
01e1a5bc 11151bfd_vma
3b22753a
L		 11152x86_64_section_word (char *str, size_t len)
11153{
8620418b 11154 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11155 return SHF_X86_64_LARGE;
11156
11157 return -1;
11158}
11159
11160static void
11161handle_large_common (int small ATTRIBUTE_UNUSED)
11162{
11163 if (flag_code != CODE_64BIT)
11164 {
11165 s_comm_internal (0, elf_common_parse);
11166 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11167 }
11168 else
11169 {
11170 static segT lbss_section;
11171 asection *saved_com_section_ptr = elf_com_section_ptr;
11172 asection *saved_bss_section = bss_section;
11173
11174 if (lbss_section == NULL)
11175 {
11176 flagword applicable;
11177 segT seg = now_seg;
11178 subsegT subseg = now_subseg;
11179
11180 /* The .lbss section is for local .largecomm symbols. */
11181 lbss_section = subseg_new (".lbss", 0);
11182 applicable = bfd_applicable_section_flags (stdoutput);
11183 bfd_set_section_flags (stdoutput, lbss_section,
11184 applicable & SEC_ALLOC);
11185 seg_info (lbss_section)->bss = 1;
11186
11187 subseg_set (seg, subseg);
11188 }
11189
11190 elf_com_section_ptr = &_bfd_elf_large_com_section;
11191 bss_section = lbss_section;
11192
11193 s_comm_internal (0, elf_common_parse);
11194
11195 elf_com_section_ptr = saved_com_section_ptr;
11196 bss_section = saved_bss_section;
11197 }
11198}
11199#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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