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* configure: Regenerated.
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
1efbbeb4 61static void set_intel_mnemonic (int);
db51cc60 62static void set_allow_index_reg (int);
e3bb37b5 63static void set_cpu_arch (int);
6482c264 64#ifdef TE_PE
e3bb37b5 65static void pe_directive_secrel (int);
6482c264 66#endif
e3bb37b5
L		 67static void signed_cons (int);
68static char *output_invalid (int c);
69static int i386_operand (char *);
70static int i386_intel_operand (char *, int);
71static const reg_entry *parse_register (char *, char **);
72static char *parse_insn (char *, char *);
73static char *parse_operands (char *, const char *);
74static void swap_operands (void);
4d456e3d 75static void swap_2_operands (int, int);
e3bb37b5
L		 76static void optimize_imm (void);
77static void optimize_disp (void);
78static int match_template (void);
79static int check_string (void);
80static int process_suffix (void);
81static int check_byte_reg (void);
82static int check_long_reg (void);
83static int check_qword_reg (void);
84static int check_word_reg (void);
85static int finalize_imm (void);
85f10a01 86static void process_drex (void);
e3bb37b5
L		 87static int process_operands (void);
88static const seg_entry *build_modrm_byte (void);
89static void output_insn (void);
90static void output_imm (fragS *, offsetT);
91static void output_disp (fragS *, offsetT);
29b0f896 92#ifndef I386COFF
e3bb37b5 93static void s_bss (int);
252b5132 94#endif
17d4e2a2
L		 95#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96static void handle_large_common (int small ATTRIBUTE_UNUSED);
97#endif
252b5132 98
a847613f 99static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 100
252b5132 101/* 'md_assemble ()' gathers together information and puts it into a
47926f60 102 i386_insn. */
252b5132 103
520dc8e8
AM		 104union i386_op
105 {
106 expressionS *disps;
107 expressionS *imms;
108 const reg_entry *regs;
109 };
110
252b5132
RH		 111struct _i386_insn
112 {
47926f60 113 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 114 template tm;
115
116 /* SUFFIX holds the instruction mnemonic suffix if given.
117 (e.g. 'l' for 'movl') */
118 char suffix;
119
47926f60 120 /* OPERANDS gives the number of given operands. */
252b5132
RH		 121 unsigned int operands;
122
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
47926f60 125 operands. */
252b5132
RH		 126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
127
128 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 129 use OP[i] for the corresponding operand. */
40fb9820 130 i386_operand_type types[MAX_OPERANDS];
252b5132 131
520dc8e8
AM		 132 /* Displacement expression, immediate expression, or register for each
133 operand. */
134 union i386_op op[MAX_OPERANDS];
252b5132 135
3e73aa7c
JH		 136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138#define Operand_PCrel 1
139
252b5132 140 /* Relocation type for operand */
f86103b7 141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 142
252b5132
RH		 143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
148
149 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 150 explicit segment overrides are given. */
ce8a8b2f 151 const seg_entry *seg[2];
252b5132
RH		 152
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
157
158 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
252b5132
RH		 161
162 modrm_byte rm;
3e73aa7c 163 rex_byte rex;
252b5132 164 sib_byte sib;
85f10a01 165 drex_byte drex;
252b5132
RH		 166 };
167
168typedef struct _i386_insn i386_insn;
169
170/* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
32137342 172const char extra_symbol_chars[] = "*%-(["
252b5132 173#ifdef LEX_AT
32137342
NC		 174 "@"
175#endif
176#ifdef LEX_QM
177 "?"
252b5132 178#endif
32137342 179 ;
252b5132 180
29b0f896
AM		 181#if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 183 && !defined (TE_GNU) \
29b0f896 184 && !defined (TE_LINUX) \
32137342 185 && !defined (TE_NETWARE) \
29b0f896
AM		 186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
252b5132 188/* This array holds the chars that always start a comment. If the
b3b91714
AM		 189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191const char *i386_comment_chars = "#/";
192#define SVR4_COMMENT_CHARS 1
252b5132 193#define PREFIX_SEPARATOR '\\'
252b5132 194
b3b91714
AM		 195#else
196const char *i386_comment_chars = "#";
197#define PREFIX_SEPARATOR '/'
198#endif
199
252b5132
RH		 200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
b3b91714 208const char line_comment_chars[] = "#/";
252b5132 209
63a0b638 210const char line_separator_chars[] = ";";
252b5132 211
ce8a8b2f
AM		 212/* Chars that can be used to separate mant from exp in floating point
213 nums. */
252b5132
RH		 214const char EXP_CHARS[] = "eE";
215
ce8a8b2f
AM		 216/* Chars that mean this number is a floating point constant
217 As in 0f12.456
218 or 0d1.2345e12. */
252b5132
RH		 219const char FLT_CHARS[] = "fFdDxX";
220
ce8a8b2f 221/* Tables for lexical analysis. */
252b5132
RH		 222static char mnemonic_chars[256];
223static char register_chars[256];
224static char operand_chars[256];
225static char identifier_chars[256];
226static char digit_chars[256];
227
ce8a8b2f 228/* Lexical macros. */
252b5132
RH		 229#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230#define is_operand_char(x) (operand_chars[(unsigned char) x])
231#define is_register_char(x) (register_chars[(unsigned char) x])
232#define is_space_char(x) ((x) == ' ')
233#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234#define is_digit_char(x) (digit_chars[(unsigned char) x])
235
0234cb7c 236/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 237static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
238
239/* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
47926f60 242 assembler instruction). */
252b5132 243static char save_stack[32];
ce8a8b2f 244static char *save_stack_p;
252b5132
RH		 245#define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247#define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
249
47926f60 250/* The instruction we're assembling. */
252b5132
RH		 251static i386_insn i;
252
253/* Possible templates for current insn. */
254static const templates *current_templates;
255
31b2323c
L		 256/* Per instruction expressionS buffers: max displacements & immediates. */
257static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 259
47926f60
KH		 260/* Current operand we are working on. */
261static int this_operand;
252b5132 262
3e73aa7c
JH		 263/* We support four different modes. FLAG_CODE variable is used to distinguish
264 these. */
265
266enum flag_code {
267 CODE_32BIT,
268 CODE_16BIT,
269 CODE_64BIT };
270
271static enum flag_code flag_code;
4fa24527 272static unsigned int object_64bit;
3e73aa7c
JH		 273static int use_rela_relocations = 0;
274
275/* The names used to print error messages. */
b77a7acd 276static const char *flag_code_names[] =
3e73aa7c
JH		 277 {
278 "32",
279 "16",
280 "64"
281 };
252b5132 282
47926f60
KH		 283/* 1 for intel syntax,
284 0 if att syntax. */
285static int intel_syntax = 0;
252b5132 286
1efbbeb4
L		 287/* 1 for intel mnemonic,
288 0 if att mnemonic. */
289static int intel_mnemonic = !SYSV386_COMPAT;
290
5209009a 291/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 292static int old_gcc = OLDGCC_COMPAT;
293
47926f60
KH		 294/* 1 if register prefix % not required. */
295static int allow_naked_reg = 0;
252b5132 296
db51cc60
L		 297/* 1 if fake index register, eiz/riz, is allowed . */
298static int allow_index_reg = 0;
299
2ca3ace5
L		 300/* Register prefix used for error message. */
301static const char *register_prefix = "%";
302
47926f60
KH		 303/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306static char stackop_size = '\0';
eecb386c 307
12b55ccc
L		 308/* Non-zero to optimize code alignment. */
309int optimize_align_code = 1;
310
47926f60
KH		 311/* Non-zero to quieten some warnings. */
312static int quiet_warnings = 0;
a38cf1db 313
47926f60
KH		 314/* CPU name. */
315static const char *cpu_arch_name = NULL;
5c6af06e 316static const char *cpu_sub_arch_name = NULL;
a38cf1db 317
47926f60 318/* CPU feature flags. */
40fb9820
L		 319static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
320
321/* Bitwise NOT of cpu_arch_flags. */
322static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 323
ccc9c027
L		 324/* If we have selected a cpu we are generating instructions for. */
325static int cpu_arch_tune_set = 0;
326
9103f4f4
L		 327/* Cpu we are generating instructions for. */
328static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
329
330/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 331static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 332
ccc9c027
L		 333/* CPU instruction set architecture used. */
334static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
335
9103f4f4 336/* CPU feature flags of instruction set architecture used. */
40fb9820 337static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 338
fddf5b5b
AM		 339/* If set, conditional jumps are not automatically promoted to handle
340 larger than a byte offset. */
341static unsigned int no_cond_jump_promotion = 0;
342
29b0f896 343/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 344static symbolS *GOT_symbol;
29b0f896 345
a4447b93
RH		 346/* The dwarf2 return column, adjusted for 32 or 64 bit. */
347unsigned int x86_dwarf2_return_column;
348
349/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
350int x86_cie_data_alignment;
351
252b5132 352/* Interface to relax_segment.
fddf5b5b
AM		 353 There are 3 major relax states for 386 jump insns because the
354 different types of jumps add different sizes to frags when we're
355 figuring out what sort of jump to choose to reach a given label. */
252b5132 356
47926f60 357/* Types. */
93c2a809
AM		 358#define UNCOND_JUMP 0
359#define COND_JUMP 1
360#define COND_JUMP86 2
fddf5b5b 361
47926f60 362/* Sizes. */
252b5132
RH		 363#define CODE16 1
364#define SMALL 0
29b0f896 365#define SMALL16 (SMALL | CODE16)
252b5132 366#define BIG 2
29b0f896 367#define BIG16 (BIG | CODE16)
252b5132
RH		 368
369#ifndef INLINE
370#ifdef __GNUC__
371#define INLINE __inline__
372#else
373#define INLINE
374#endif
375#endif
376
fddf5b5b
AM		 377#define ENCODE_RELAX_STATE(type, size) \
378 ((relax_substateT) (((type) << 2) | (size)))
379#define TYPE_FROM_RELAX_STATE(s) \
380 ((s) >> 2)
381#define DISP_SIZE_FROM_RELAX_STATE(s) \
382 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 383
384/* This table is used by relax_frag to promote short jumps to long
385 ones where necessary. SMALL (short) jumps may be promoted to BIG
386 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
387 don't allow a short jump in a 32 bit code segment to be promoted to
388 a 16 bit offset jump because it's slower (requires data size
389 prefix), and doesn't work, unless the destination is in the bottom
390 64k of the code segment (The top 16 bits of eip are zeroed). */
391
392const relax_typeS md_relax_table[] =
393{
24eab124
AM		 394 /* The fields are:
395 1) most positive reach of this state,
396 2) most negative reach of this state,
93c2a809 397 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 398 4) which index into the table to try if we can't fit into this one. */
252b5132 399
fddf5b5b 400 /* UNCOND_JUMP states. */
93c2a809
AM		 401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
403 /* dword jmp adds 4 bytes to frag:
404 0 extra opcode bytes, 4 displacement bytes. */
252b5132 405 {0, 0, 4, 0},
93c2a809
AM		 406 /* word jmp adds 2 byte2 to frag:
407 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 408 {0, 0, 2, 0},
409
93c2a809
AM		 410 /* COND_JUMP states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
fddf5b5b 416 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 417 1 extra opcode byte, 2 displacement bytes. */
418 {0, 0, 3, 0},
419
420 /* COND_JUMP86 states. */
421 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
422 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
423 /* dword conditionals adds 5 bytes to frag:
424 1 extra opcode byte, 4 displacement bytes. */
425 {0, 0, 5, 0},
426 /* word conditionals add 4 bytes to frag:
427 1 displacement byte and a 3 byte long branch insn. */
428 {0, 0, 4, 0}
252b5132
RH		 429};
430
9103f4f4
L		 431static const arch_entry cpu_arch[] =
432{
433 {"generic32", PROCESSOR_GENERIC32,
40fb9820 434 CPU_GENERIC32_FLAGS },
9103f4f4 435 {"generic64", PROCESSOR_GENERIC64,
40fb9820 436 CPU_GENERIC64_FLAGS },
9103f4f4 437 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 438 CPU_NONE_FLAGS },
9103f4f4 439 {"i186", PROCESSOR_UNKNOWN,
40fb9820 440 CPU_I186_FLAGS },
9103f4f4 441 {"i286", PROCESSOR_UNKNOWN,
40fb9820 442 CPU_I286_FLAGS },
76bc74dc 443 {"i386", PROCESSOR_I386,
40fb9820 444 CPU_I386_FLAGS },
9103f4f4 445 {"i486", PROCESSOR_I486,
40fb9820 446 CPU_I486_FLAGS },
9103f4f4 447 {"i586", PROCESSOR_PENTIUM,
40fb9820 448 CPU_I586_FLAGS },
9103f4f4 449 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 450 CPU_I686_FLAGS },
9103f4f4 451 {"pentium", PROCESSOR_PENTIUM,
40fb9820 452 CPU_I586_FLAGS },
9103f4f4 453 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 454 CPU_I686_FLAGS },
9103f4f4 455 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 456 CPU_P2_FLAGS },
9103f4f4 457 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 458 CPU_P3_FLAGS },
9103f4f4 459 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 460 CPU_P4_FLAGS },
9103f4f4 461 {"prescott", PROCESSOR_NOCONA,
40fb9820 462 CPU_CORE_FLAGS },
9103f4f4 463 {"nocona", PROCESSOR_NOCONA,
40fb9820 464 CPU_NOCONA_FLAGS },
ef05d495 465 {"yonah", PROCESSOR_CORE,
40fb9820 466 CPU_CORE_FLAGS },
ef05d495 467 {"core", PROCESSOR_CORE,
40fb9820 468 CPU_CORE_FLAGS },
ef05d495 469 {"merom", PROCESSOR_CORE2,
40fb9820 470 CPU_CORE2_FLAGS },
ef05d495 471 {"core2", PROCESSOR_CORE2,
40fb9820 472 CPU_CORE2_FLAGS },
9103f4f4 473 {"k6", PROCESSOR_K6,
40fb9820 474 CPU_K6_FLAGS },
9103f4f4 475 {"k6_2", PROCESSOR_K6,
40fb9820 476 CPU_K6_2_FLAGS },
9103f4f4 477 {"athlon", PROCESSOR_ATHLON,
40fb9820 478 CPU_ATHLON_FLAGS },
9103f4f4 479 {"sledgehammer", PROCESSOR_K8,
40fb9820 480 CPU_K8_FLAGS },
9103f4f4 481 {"opteron", PROCESSOR_K8,
40fb9820 482 CPU_K8_FLAGS },
9103f4f4 483 {"k8", PROCESSOR_K8,
40fb9820 484 CPU_K8_FLAGS },
050dfa73 485 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 486 CPU_AMDFAM10_FLAGS },
9103f4f4 487 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 488 CPU_MMX_FLAGS },
9103f4f4 489 {".sse", PROCESSOR_UNKNOWN,
40fb9820 490 CPU_SSE_FLAGS },
9103f4f4 491 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 492 CPU_SSE2_FLAGS },
9103f4f4 493 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 494 CPU_SSE3_FLAGS },
ef05d495 495 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 496 CPU_SSSE3_FLAGS },
42903f7f 497 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 498 CPU_SSE4_1_FLAGS },
381d071f 499 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 500 CPU_SSE4_2_FLAGS },
381d071f 501 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 502 CPU_SSE4_2_FLAGS },
9103f4f4 503 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 504 CPU_3DNOW_FLAGS },
9103f4f4 505 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 506 CPU_3DNOWA_FLAGS },
9103f4f4 507 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 508 CPU_PADLOCK_FLAGS },
9103f4f4 509 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 510 CPU_SVME_FLAGS },
9103f4f4 511 {".svme", PROCESSOR_UNKNOWN,
40fb9820 512 CPU_SVME_FLAGS },
050dfa73 513 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 514 CPU_SSE4A_FLAGS },
050dfa73 515 {".abm", PROCESSOR_UNKNOWN,
40fb9820 516 CPU_ABM_FLAGS },
85f10a01
MM		 517 {".sse5", PROCESSOR_UNKNOWN,
518 CPU_SSE5_FLAGS },
e413e4e9
AM		 519};
520
29b0f896
AM		 521const pseudo_typeS md_pseudo_table[] =
522{
523#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
524 {"align", s_align_bytes, 0},
525#else
526 {"align", s_align_ptwo, 0},
527#endif
528 {"arch", set_cpu_arch, 0},
529#ifndef I386COFF
530 {"bss", s_bss, 0},
531#endif
532 {"ffloat", float_cons, 'f'},
533 {"dfloat", float_cons, 'd'},
534 {"tfloat", float_cons, 'x'},
535 {"value", cons, 2},
d182319b 536 {"slong", signed_cons, 4},
29b0f896
AM		 537 {"noopt", s_ignore, 0},
538 {"optim", s_ignore, 0},
539 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
540 {"code16", set_code_flag, CODE_16BIT},
541 {"code32", set_code_flag, CODE_32BIT},
542 {"code64", set_code_flag, CODE_64BIT},
543 {"intel_syntax", set_intel_syntax, 1},
544 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 545 {"intel_mnemonic", set_intel_mnemonic, 1},
546 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 547 {"allow_index_reg", set_allow_index_reg, 1},
548 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 549#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
550 {"largecomm", handle_large_common, 0},
07a53e5c 551#else
e3bb37b5 552 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 553 {"loc", dwarf2_directive_loc, 0},
554 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 555#endif
6482c264
NC		 556#ifdef TE_PE
557 {"secrel32", pe_directive_secrel, 0},
558#endif
29b0f896
AM		 559 {0, 0, 0}
560};
561
562/* For interface with expression (). */
563extern char *input_line_pointer;
564
565/* Hash table for instruction mnemonic lookup. */
566static struct hash_control *op_hash;
567
568/* Hash table for register lookup. */
569static struct hash_control *reg_hash;
570\f
252b5132 571void
e3bb37b5 572i386_align_code (fragS *fragP, int count)
252b5132 573{
ce8a8b2f
AM		 574 /* Various efficient no-op patterns for aligning code labels.
575 Note: Don't try to assemble the instructions in the comments.
576 0L and 0w are not legal. */
252b5132
RH		 577 static const char f32_1[] =
578 {0x90}; /* nop */
579 static const char f32_2[] =
ccc9c027 580 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 581 static const char f32_3[] =
582 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
583 static const char f32_4[] =
584 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_5[] =
586 {0x90, /* nop */
587 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
588 static const char f32_6[] =
589 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
590 static const char f32_7[] =
591 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_8[] =
593 {0x90, /* nop */
594 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
595 static const char f32_9[] =
596 {0x89,0xf6, /* movl %esi,%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_10[] =
599 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_11[] =
602 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
604 static const char f32_12[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
607 static const char f32_13[] =
608 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
610 static const char f32_14[] =
611 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
612 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 613 static const char f16_3[] =
614 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 615 static const char f16_4[] =
616 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_5[] =
618 {0x90, /* nop */
619 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
620 static const char f16_6[] =
621 {0x89,0xf6, /* mov %si,%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_7[] =
624 {0x8d,0x74,0x00, /* lea 0(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char f16_8[] =
627 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
628 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 629 static const char jump_31[] =
630 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
631 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
632 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
633 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 634 static const char *const f32_patt[] = {
635 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 636 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 637 };
638 static const char *const f16_patt[] = {
76bc74dc 639 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 640 };
ccc9c027
L		 641 /* nopl (%[re]ax) */
642 static const char alt_3[] =
643 {0x0f,0x1f,0x00};
644 /* nopl 0(%[re]ax) */
645 static const char alt_4[] =
646 {0x0f,0x1f,0x40,0x00};
647 /* nopl 0(%[re]ax,%[re]ax,1) */
648 static const char alt_5[] =
649 {0x0f,0x1f,0x44,0x00,0x00};
650 /* nopw 0(%[re]ax,%[re]ax,1) */
651 static const char alt_6[] =
652 {0x66,0x0f,0x1f,0x44,0x00,0x00};
653 /* nopl 0L(%[re]ax) */
654 static const char alt_7[] =
655 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
656 /* nopl 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_8[] =
658 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw 0L(%[re]ax,%[re]ax,1) */
660 static const char alt_9[] =
661 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
663 static const char alt_10[] =
664 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
665 /* data16
666 nopw %cs:0L(%[re]ax,%[re]ax,1) */
667 static const char alt_long_11[] =
668 {0x66,
669 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 /* data16
671 data16
672 nopw %cs:0L(%[re]ax,%[re]ax,1) */
673 static const char alt_long_12[] =
674 {0x66,
675 0x66,
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 /* data16
678 data16
679 data16
680 nopw %cs:0L(%[re]ax,%[re]ax,1) */
681 static const char alt_long_13[] =
682 {0x66,
683 0x66,
684 0x66,
685 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
686 /* data16
687 data16
688 data16
689 data16
690 nopw %cs:0L(%[re]ax,%[re]ax,1) */
691 static const char alt_long_14[] =
692 {0x66,
693 0x66,
694 0x66,
695 0x66,
696 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
697 /* data16
698 data16
699 data16
700 data16
701 data16
702 nopw %cs:0L(%[re]ax,%[re]ax,1) */
703 static const char alt_long_15[] =
704 {0x66,
705 0x66,
706 0x66,
707 0x66,
708 0x66,
709 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
710 /* nopl 0(%[re]ax,%[re]ax,1)
711 nopw 0(%[re]ax,%[re]ax,1) */
712 static const char alt_short_11[] =
713 {0x0f,0x1f,0x44,0x00,0x00,
714 0x66,0x0f,0x1f,0x44,0x00,0x00};
715 /* nopw 0(%[re]ax,%[re]ax,1)
716 nopw 0(%[re]ax,%[re]ax,1) */
717 static const char alt_short_12[] =
718 {0x66,0x0f,0x1f,0x44,0x00,0x00,
719 0x66,0x0f,0x1f,0x44,0x00,0x00};
720 /* nopw 0(%[re]ax,%[re]ax,1)
721 nopl 0L(%[re]ax) */
722 static const char alt_short_13[] =
723 {0x66,0x0f,0x1f,0x44,0x00,0x00,
724 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
725 /* nopl 0L(%[re]ax)
726 nopl 0L(%[re]ax) */
727 static const char alt_short_14[] =
728 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
729 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
730 /* nopl 0L(%[re]ax)
731 nopl 0L(%[re]ax,%[re]ax,1) */
732 static const char alt_short_15[] =
733 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
734 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
735 static const char *const alt_short_patt[] = {
736 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
737 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
738 alt_short_14, alt_short_15
739 };
740 static const char *const alt_long_patt[] = {
741 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
742 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
743 alt_long_14, alt_long_15
744 };
252b5132 745
76bc74dc
L		 746 /* Only align for at least a positive non-zero boundary. */
747 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 748 return;
3e73aa7c 749
ccc9c027
L		 750 /* We need to decide which NOP sequence to use for 32bit and
751 64bit. When -mtune= is used:
4eed87de 752
76bc74dc
L		 753 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
754 PROCESSOR_GENERIC32, f32_patt will be used.
755 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
756 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
757 alt_long_patt will be used.
758 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
759 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 760
76bc74dc
L		 761 When -mtune= isn't used, alt_long_patt will be used if
762 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
763 be used.
ccc9c027
L		 764
765 When -march= or .arch is used, we can't use anything beyond
766 cpu_arch_isa_flags. */
767
768 if (flag_code == CODE_16BIT)
769 {
ccc9c027 770 if (count > 8)
33fef721 771 {
76bc74dc
L		 772 memcpy (fragP->fr_literal + fragP->fr_fix,
773 jump_31, count);
774 /* Adjust jump offset. */
775 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 776 }
76bc74dc
L		 777 else
778 memcpy (fragP->fr_literal + fragP->fr_fix,
779 f16_patt[count - 1], count);
252b5132 780 }
33fef721 781 else
ccc9c027
L		 782 {
783 const char *const *patt = NULL;
784
785 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
786 {
787 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
788 switch (cpu_arch_tune)
789 {
790 case PROCESSOR_UNKNOWN:
791 /* We use cpu_arch_isa_flags to check if we SHOULD
792 optimize for Cpu686. */
40fb9820 793 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 794 patt = alt_long_patt;
ccc9c027
L		 795 else
796 patt = f32_patt;
797 break;
ccc9c027
L		 798 case PROCESSOR_PENTIUMPRO:
799 case PROCESSOR_PENTIUM4:
800 case PROCESSOR_NOCONA:
ef05d495 801 case PROCESSOR_CORE:
76bc74dc
L		 802 case PROCESSOR_CORE2:
803 case PROCESSOR_GENERIC64:
804 patt = alt_long_patt;
805 break;
ccc9c027
L		 806 case PROCESSOR_K6:
807 case PROCESSOR_ATHLON:
808 case PROCESSOR_K8:
4eed87de 809 case PROCESSOR_AMDFAM10:
ccc9c027
L		 810 patt = alt_short_patt;
811 break;
76bc74dc 812 case PROCESSOR_I386:
ccc9c027
L		 813 case PROCESSOR_I486:
814 case PROCESSOR_PENTIUM:
815 case PROCESSOR_GENERIC32:
816 patt = f32_patt;
817 break;
4eed87de 818 }
ccc9c027
L		 819 }
820 else
821 {
822 switch (cpu_arch_tune)
823 {
824 case PROCESSOR_UNKNOWN:
825 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
826 PROCESSOR_UNKNOWN. */
827 abort ();
828 break;
829
76bc74dc 830 case PROCESSOR_I386:
ccc9c027
L		 831 case PROCESSOR_I486:
832 case PROCESSOR_PENTIUM:
ccc9c027
L		 833 case PROCESSOR_K6:
834 case PROCESSOR_ATHLON:
835 case PROCESSOR_K8:
4eed87de 836 case PROCESSOR_AMDFAM10:
ccc9c027
L		 837 case PROCESSOR_GENERIC32:
838 /* We use cpu_arch_isa_flags to check if we CAN optimize
839 for Cpu686. */
40fb9820 840 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 841 patt = alt_short_patt;
842 else
843 patt = f32_patt;
844 break;
76bc74dc
L		 845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
848 case PROCESSOR_CORE:
ef05d495 849 case PROCESSOR_CORE2:
40fb9820 850 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 851 patt = alt_long_patt;
852 else
853 patt = f32_patt;
854 break;
855 case PROCESSOR_GENERIC64:
76bc74dc 856 patt = alt_long_patt;
ccc9c027 857 break;
4eed87de 858 }
ccc9c027
L		 859 }
860
76bc74dc
L		 861 if (patt == f32_patt)
862 {
863 /* If the padding is less than 15 bytes, we use the normal
864 ones. Otherwise, we use a jump instruction and adjust
865 its offset. */
866 if (count < 15)
867 memcpy (fragP->fr_literal + fragP->fr_fix,
868 patt[count - 1], count);
869 else
870 {
871 memcpy (fragP->fr_literal + fragP->fr_fix,
872 jump_31, count);
873 /* Adjust jump offset. */
874 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
875 }
876 }
877 else
878 {
879 /* Maximum length of an instruction is 15 byte. If the
880 padding is greater than 15 bytes and we don't use jump,
881 we have to break it into smaller pieces. */
882 int padding = count;
883 while (padding > 15)
884 {
885 padding -= 15;
886 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
887 patt [14], 15);
888 }
889
890 if (padding)
891 memcpy (fragP->fr_literal + fragP->fr_fix,
892 patt [padding - 1], padding);
893 }
ccc9c027 894 }
33fef721 895 fragP->fr_var = count;
252b5132
RH		 896}
897
c6fb90c8
L		 898static INLINE int
899uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 900{
c6fb90c8
L		 901 switch (size)
902 {
903 case 3:
904 if (x[2])
905 return 0;
906 case 2:
907 if (x[1])
908 return 0;
909 case 1:
910 return !x[0];
911 default:
912 abort ();
913 }
40fb9820
L		 914}
915
c6fb90c8
L		 916static INLINE void
917uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 918{
c6fb90c8
L		 919 switch (size)
920 {
921 case 3:
922 x[2] = v;
923 case 2:
924 x[1] = v;
925 case 1:
926 x[0] = v;
927 break;
928 default:
929 abort ();
930 }
931}
40fb9820 932
c6fb90c8
L		 933static INLINE int
934uints_equal (const unsigned int *x, const unsigned int *y,
935 unsigned int size)
936{
937 switch (size)
938 {
939 case 3:
940 if (x[2] != y [2])
941 return 0;
942 case 2:
943 if (x[1] != y [1])
944 return 0;
945 case 1:
946 return x[0] == y [0];
947 break;
948 default:
949 abort ();
950 }
951}
40fb9820 952
c6fb90c8
L		 953#define UINTS_ALL_ZERO(x) \
954 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
955#define UINTS_SET(x, v) \
956 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
957#define UINTS_CLEAR(x) \
958 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
959#define UINTS_EQUAL(x, y) \
960 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
961
962static INLINE int
963cpu_flags_check_cpu64 (i386_cpu_flags f)
964{
965 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
966 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 967}
968
c6fb90c8 969static INLINE i386_cpu_flags
40fb9820
L		 970cpu_flags_not (i386_cpu_flags x)
971{
c6fb90c8
L		 972 switch (ARRAY_SIZE (x.array))
973 {
974 case 3:
975 x.array [2] = ~x.array [2];
976 case 2:
977 x.array [1] = ~x.array [1];
978 case 1:
979 x.array [0] = ~x.array [0];
980 break;
981 default:
982 abort ();
983 }
40fb9820
L		 984
985#ifdef CpuUnused
986 x.bitfield.unused = 0;
987#endif
988
989 return x;
990}
991
c6fb90c8
L		 992static INLINE i386_cpu_flags
993cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 994{
c6fb90c8
L		 995 switch (ARRAY_SIZE (x.array))
996 {
997 case 3:
998 x.array [2] &= y.array [2];
999 case 2:
1000 x.array [1] &= y.array [1];
1001 case 1:
1002 x.array [0] &= y.array [0];
1003 break;
1004 default:
1005 abort ();
1006 }
1007 return x;
1008}
40fb9820 1009
c6fb90c8
L		 1010static INLINE i386_cpu_flags
1011cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1012{
c6fb90c8 1013 switch (ARRAY_SIZE (x.array))
40fb9820 1014 {
c6fb90c8
L		 1015 case 3:
1016 x.array [2] |= y.array [2];
1017 case 2:
1018 x.array [1] |= y.array [1];
1019 case 1:
1020 x.array [0] |= y.array [0];
40fb9820
L		 1021 break;
1022 default:
1023 abort ();
1024 }
40fb9820
L		 1025 return x;
1026}
1027
1028static int
1029cpu_flags_match (i386_cpu_flags x)
1030{
1031 i386_cpu_flags not = cpu_arch_flags_not;
1032
1033 not.bitfield.cpu64 = 1;
1034 not.bitfield.cpuno64 = 1;
1035
1036 x.bitfield.cpu64 = 0;
1037 x.bitfield.cpuno64 = 0;
1038
c6fb90c8
L		 1039 not = cpu_flags_and (x, not);
1040 return UINTS_ALL_ZERO (not);
40fb9820
L		 1041}
1042
c6fb90c8
L		 1043static INLINE i386_operand_type
1044operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1045{
c6fb90c8
L		 1046 switch (ARRAY_SIZE (x.array))
1047 {
1048 case 3:
1049 x.array [2] &= y.array [2];
1050 case 2:
1051 x.array [1] &= y.array [1];
1052 case 1:
1053 x.array [0] &= y.array [0];
1054 break;
1055 default:
1056 abort ();
1057 }
1058 return x;
40fb9820
L		 1059}
1060
c6fb90c8
L		 1061static INLINE i386_operand_type
1062operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1063{
c6fb90c8 1064 switch (ARRAY_SIZE (x.array))
40fb9820 1065 {
c6fb90c8
L		 1066 case 3:
1067 x.array [2] |= y.array [2];
1068 case 2:
1069 x.array [1] |= y.array [1];
1070 case 1:
1071 x.array [0] |= y.array [0];
40fb9820
L		 1072 break;
1073 default:
1074 abort ();
1075 }
c6fb90c8
L		 1076 return x;
1077}
40fb9820 1078
c6fb90c8
L		 1079static INLINE i386_operand_type
1080operand_type_xor (i386_operand_type x, i386_operand_type y)
1081{
1082 switch (ARRAY_SIZE (x.array))
1083 {
1084 case 3:
1085 x.array [2] ^= y.array [2];
1086 case 2:
1087 x.array [1] ^= y.array [1];
1088 case 1:
1089 x.array [0] ^= y.array [0];
1090 break;
1091 default:
1092 abort ();
1093 }
40fb9820
L		 1094 return x;
1095}
1096
1097static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1098static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1099static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1100static const i386_operand_type reg16_inoutportreg
1101 = OPERAND_TYPE_REG16_INOUTPORTREG;
1102static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1103static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1104static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1105static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1106static const i386_operand_type anydisp
1107 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1108static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1109static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1110static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1111static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1112static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1113static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1114static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1115static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1116static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1117static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1118
1119enum operand_type
1120{
1121 reg,
40fb9820
L		 1122 imm,
1123 disp,
1124 anymem
1125};
1126
c6fb90c8 1127static INLINE int
40fb9820
L		 1128operand_type_check (i386_operand_type t, enum operand_type c)
1129{
1130 switch (c)
1131 {
1132 case reg:
1133 return (t.bitfield.reg8
1134 || t.bitfield.reg16
1135 || t.bitfield.reg32
1136 || t.bitfield.reg64);
1137
40fb9820
L		 1138 case imm:
1139 return (t.bitfield.imm8
1140 || t.bitfield.imm8s
1141 || t.bitfield.imm16
1142 || t.bitfield.imm32
1143 || t.bitfield.imm32s
1144 || t.bitfield.imm64);
1145
1146 case disp:
1147 return (t.bitfield.disp8
1148 || t.bitfield.disp16
1149 || t.bitfield.disp32
1150 || t.bitfield.disp32s
1151 || t.bitfield.disp64);
1152
1153 case anymem:
1154 return (t.bitfield.disp8
1155 || t.bitfield.disp16
1156 || t.bitfield.disp32
1157 || t.bitfield.disp32s
1158 || t.bitfield.disp64
1159 || t.bitfield.baseindex);
1160
1161 default:
1162 abort ();
1163 }
1164}
1165
c6fb90c8 1166static INLINE int
40fb9820
L		 1167operand_type_match (i386_operand_type overlap,
1168 i386_operand_type given)
1169{
1170 i386_operand_type temp = overlap;
1171
1172 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1173 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1174 return 0;
1175
1176 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1177 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1178}
1179
1180/* If given types r0 and r1 are registers they must be of the same type
1181 unless the expected operand type register overlap is null.
1182 Note that Acc in a template matches every size of reg. */
1183
c6fb90c8 1184static INLINE int
40fb9820
L		 1185operand_type_register_match (i386_operand_type m0,
1186 i386_operand_type g0,
1187 i386_operand_type t0,
1188 i386_operand_type m1,
1189 i386_operand_type g1,
1190 i386_operand_type t1)
1191{
1192 if (!operand_type_check (g0, reg))
1193 return 1;
1194
1195 if (!operand_type_check (g1, reg))
1196 return 1;
1197
1198 if (g0.bitfield.reg8 == g1.bitfield.reg8
1199 && g0.bitfield.reg16 == g1.bitfield.reg16
1200 && g0.bitfield.reg32 == g1.bitfield.reg32
1201 && g0.bitfield.reg64 == g1.bitfield.reg64)
1202 return 1;
1203
1204 if (m0.bitfield.acc)
1205 {
1206 t0.bitfield.reg8 = 1;
1207 t0.bitfield.reg16 = 1;
1208 t0.bitfield.reg32 = 1;
1209 t0.bitfield.reg64 = 1;
1210 }
1211
1212 if (m1.bitfield.acc)
1213 {
1214 t1.bitfield.reg8 = 1;
1215 t1.bitfield.reg16 = 1;
1216 t1.bitfield.reg32 = 1;
1217 t1.bitfield.reg64 = 1;
1218 }
1219
1220 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1221 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1222 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1223 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1224}
1225
252b5132 1226static INLINE unsigned int
40fb9820 1227mode_from_disp_size (i386_operand_type t)
252b5132 1228{
40fb9820
L		 1229 if (t.bitfield.disp8)
1230 return 1;
1231 else if (t.bitfield.disp16
1232 || t.bitfield.disp32
1233 || t.bitfield.disp32s)
1234 return 2;
1235 else
1236 return 0;
252b5132
RH		 1237}
1238
1239static INLINE int
e3bb37b5 1240fits_in_signed_byte (offsetT num)
252b5132
RH		 1241{
1242 return (num >= -128) && (num <= 127);
47926f60 1243}
252b5132
RH		 1244
1245static INLINE int
e3bb37b5 1246fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1247{
1248 return (num & 0xff) == num;
47926f60 1249}
252b5132
RH		 1250
1251static INLINE int
e3bb37b5 1252fits_in_unsigned_word (offsetT num)
252b5132
RH		 1253{
1254 return (num & 0xffff) == num;
47926f60 1255}
252b5132
RH		 1256
1257static INLINE int
e3bb37b5 1258fits_in_signed_word (offsetT num)
252b5132
RH		 1259{
1260 return (-32768 <= num) && (num <= 32767);
47926f60 1261}
2a962e6d 1262
3e73aa7c 1263static INLINE int
e3bb37b5 1264fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1265{
1266#ifndef BFD64
1267 return 1;
1268#else
1269 return (!(((offsetT) -1 << 31) & num)
1270 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1271#endif
1272} /* fits_in_signed_long() */
2a962e6d 1273
3e73aa7c 1274static INLINE int
e3bb37b5 1275fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1276{
1277#ifndef BFD64
1278 return 1;
1279#else
1280 return (num & (((offsetT) 2 << 31) - 1)) == num;
1281#endif
1282} /* fits_in_unsigned_long() */
252b5132 1283
40fb9820 1284static i386_operand_type
e3bb37b5 1285smallest_imm_type (offsetT num)
252b5132 1286{
40fb9820
L		 1287 i386_operand_type t;
1288
c6fb90c8 1289 UINTS_CLEAR (t);
40fb9820
L		 1290 t.bitfield.imm64 = 1;
1291
1292 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1293 {
1294 /* This code is disabled on the 486 because all the Imm1 forms
1295 in the opcode table are slower on the i486. They're the
1296 versions with the implicitly specified single-position
1297 displacement, which has another syntax if you really want to
1298 use that form. */
40fb9820
L		 1299 t.bitfield.imm1 = 1;
1300 t.bitfield.imm8 = 1;
1301 t.bitfield.imm8s = 1;
1302 t.bitfield.imm16 = 1;
1303 t.bitfield.imm32 = 1;
1304 t.bitfield.imm32s = 1;
1305 }
1306 else if (fits_in_signed_byte (num))
1307 {
1308 t.bitfield.imm8 = 1;
1309 t.bitfield.imm8s = 1;
1310 t.bitfield.imm16 = 1;
1311 t.bitfield.imm32 = 1;
1312 t.bitfield.imm32s = 1;
1313 }
1314 else if (fits_in_unsigned_byte (num))
1315 {
1316 t.bitfield.imm8 = 1;
1317 t.bitfield.imm16 = 1;
1318 t.bitfield.imm32 = 1;
1319 t.bitfield.imm32s = 1;
1320 }
1321 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1322 {
1323 t.bitfield.imm16 = 1;
1324 t.bitfield.imm32 = 1;
1325 t.bitfield.imm32s = 1;
1326 }
1327 else if (fits_in_signed_long (num))
1328 {
1329 t.bitfield.imm32 = 1;
1330 t.bitfield.imm32s = 1;
1331 }
1332 else if (fits_in_unsigned_long (num))
1333 t.bitfield.imm32 = 1;
1334
1335 return t;
47926f60 1336}
252b5132 1337
847f7ad4 1338static offsetT
e3bb37b5 1339offset_in_range (offsetT val, int size)
847f7ad4 1340{
508866be 1341 addressT mask;
ba2adb93 1342
847f7ad4
AM		 1343 switch (size)
1344 {
508866be
L		 1345 case 1: mask = ((addressT) 1 << 8) - 1; break;
1346 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1347 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1348#ifdef BFD64
1349 case 8: mask = ((addressT) 2 << 63) - 1; break;
1350#endif
47926f60 1351 default: abort ();
847f7ad4
AM		 1352 }
1353
ba2adb93 1354 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1355 if (!use_rela_relocations)
1356 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1357 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1358
47926f60 1359 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1360 {
1361 char buf1[40], buf2[40];
1362
1363 sprint_value (buf1, val);
1364 sprint_value (buf2, val & mask);
1365 as_warn (_("%s shortened to %s"), buf1, buf2);
1366 }
1367 return val & mask;
1368}
1369
252b5132
RH		 1370/* Returns 0 if attempting to add a prefix where one from the same
1371 class already exists, 1 if non rep/repne added, 2 if rep/repne
1372 added. */
1373static int
e3bb37b5 1374add_prefix (unsigned int prefix)
252b5132
RH		 1375{
1376 int ret = 1;
b1905489 1377 unsigned int q;
252b5132 1378
29b0f896
AM		 1379 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1380 && flag_code == CODE_64BIT)
b1905489 1381 {
161a04f6
L		 1382 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1383 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1384 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1385 ret = 0;
1386 q = REX_PREFIX;
1387 }
3e73aa7c 1388 else
b1905489
JB		 1389 {
1390 switch (prefix)
1391 {
1392 default:
1393 abort ();
1394
1395 case CS_PREFIX_OPCODE:
1396 case DS_PREFIX_OPCODE:
1397 case ES_PREFIX_OPCODE:
1398 case FS_PREFIX_OPCODE:
1399 case GS_PREFIX_OPCODE:
1400 case SS_PREFIX_OPCODE:
1401 q = SEG_PREFIX;
1402 break;
1403
1404 case REPNE_PREFIX_OPCODE:
1405 case REPE_PREFIX_OPCODE:
1406 ret = 2;
1407 /* fall thru */
1408 case LOCK_PREFIX_OPCODE:
1409 q = LOCKREP_PREFIX;
1410 break;
1411
1412 case FWAIT_OPCODE:
1413 q = WAIT_PREFIX;
1414 break;
1415
1416 case ADDR_PREFIX_OPCODE:
1417 q = ADDR_PREFIX;
1418 break;
1419
1420 case DATA_PREFIX_OPCODE:
1421 q = DATA_PREFIX;
1422 break;
1423 }
1424 if (i.prefix[q] != 0)
1425 ret = 0;
1426 }
252b5132 1427
b1905489 1428 if (ret)
252b5132 1429 {
b1905489
JB		 1430 if (!i.prefix[q])
1431 ++i.prefixes;
1432 i.prefix[q] |= prefix;
252b5132 1433 }
b1905489
JB		 1434 else
1435 as_bad (_("same type of prefix used twice"));
252b5132 1436
252b5132
RH		 1437 return ret;
1438}
1439
1440static void
e3bb37b5 1441set_code_flag (int value)
eecb386c 1442{
3e73aa7c 1443 flag_code = value;
40fb9820
L		 1444 if (flag_code == CODE_64BIT)
1445 {
1446 cpu_arch_flags.bitfield.cpu64 = 1;
1447 cpu_arch_flags.bitfield.cpuno64 = 0;
1448 cpu_arch_flags_not.bitfield.cpu64 = 0;
1449 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1450 }
1451 else
1452 {
1453 cpu_arch_flags.bitfield.cpu64 = 0;
1454 cpu_arch_flags.bitfield.cpuno64 = 1;
1455 cpu_arch_flags_not.bitfield.cpu64 = 1;
1456 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1457 }
1458 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1459 {
1460 as_bad (_("64bit mode not supported on this CPU."));
1461 }
40fb9820 1462 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1463 {
1464 as_bad (_("32bit mode not supported on this CPU."));
1465 }
eecb386c
AM		 1466 stackop_size = '\0';
1467}
1468
1469static void
e3bb37b5 1470set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1471{
3e73aa7c 1472 flag_code = new_code_flag;
40fb9820
L		 1473 if (flag_code != CODE_16BIT)
1474 abort ();
1475 cpu_arch_flags.bitfield.cpu64 = 0;
1476 cpu_arch_flags.bitfield.cpuno64 = 1;
1477 cpu_arch_flags_not.bitfield.cpu64 = 1;
1478 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1479 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1480}
1481
1482static void
e3bb37b5 1483set_intel_syntax (int syntax_flag)
252b5132
RH		 1484{
1485 /* Find out if register prefixing is specified. */
1486 int ask_naked_reg = 0;
1487
1488 SKIP_WHITESPACE ();
29b0f896 1489 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1490 {
1491 char *string = input_line_pointer;
1492 int e = get_symbol_end ();
1493
47926f60 1494 if (strcmp (string, "prefix") == 0)
252b5132 1495 ask_naked_reg = 1;
47926f60 1496 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1497 ask_naked_reg = -1;
1498 else
d0b47220 1499 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1500 *input_line_pointer = e;
1501 }
1502 demand_empty_rest_of_line ();
c3332e24 1503
252b5132
RH		 1504 intel_syntax = syntax_flag;
1505
1506 if (ask_naked_reg == 0)
f86103b7
AM		 1507 allow_naked_reg = (intel_syntax
1508 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1509 else
1510 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1511
e4a3b5a4 1512 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1513 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1514 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1515}
1516
1efbbeb4
L		 1517static void
1518set_intel_mnemonic (int mnemonic_flag)
1519{
1520 /* Find out if register prefixing is specified. */
1521 int ask_naked_reg = 0;
1522
1523 SKIP_WHITESPACE ();
1524 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1525 {
1526 char *string = input_line_pointer;
1527 int e = get_symbol_end ();
1528
1529 if (strcmp (string, "prefix") == 0)
1530 ask_naked_reg = 1;
1531 else if (strcmp (string, "noprefix") == 0)
1532 ask_naked_reg = -1;
1533 else
1534 as_bad (_("bad argument to syntax directive."));
1535 *input_line_pointer = e;
1536 }
1537 demand_empty_rest_of_line ();
1538
1539 /* intel_mnemonic implies intel_syntax. */
1540 intel_mnemonic = intel_syntax = mnemonic_flag;
1541
1542 if (ask_naked_reg == 0)
1543 allow_naked_reg = (intel_mnemonic
1544 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1545 else
1546 allow_naked_reg = (ask_naked_reg < 0);
1547
1548 identifier_chars['%'] = intel_mnemonic && allow_naked_reg ? '%' : 0;
1549 identifier_chars['$'] = intel_mnemonic ? '$' : 0;
1550 register_prefix = allow_naked_reg ? "" : "%";
1551}
1552
db51cc60
L		 1553static void
1554set_allow_index_reg (int flag)
1555{
1556 allow_index_reg = flag;
1557}
1558
e413e4e9 1559static void
e3bb37b5 1560set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1561{
47926f60 1562 SKIP_WHITESPACE ();
e413e4e9 1563
29b0f896 1564 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1565 {
1566 char *string = input_line_pointer;
1567 int e = get_symbol_end ();
9103f4f4 1568 unsigned int i;
40fb9820 1569 i386_cpu_flags flags;
e413e4e9 1570
9103f4f4 1571 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1572 {
1573 if (strcmp (string, cpu_arch[i].name) == 0)
1574 {
5c6af06e
JB		 1575 if (*string != '.')
1576 {
1577 cpu_arch_name = cpu_arch[i].name;
1578 cpu_sub_arch_name = NULL;
40fb9820
L		 1579 cpu_arch_flags = cpu_arch[i].flags;
1580 if (flag_code == CODE_64BIT)
1581 {
1582 cpu_arch_flags.bitfield.cpu64 = 1;
1583 cpu_arch_flags.bitfield.cpuno64 = 0;
1584 }
1585 else
1586 {
1587 cpu_arch_flags.bitfield.cpu64 = 0;
1588 cpu_arch_flags.bitfield.cpuno64 = 1;
1589 }
1590 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1591 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1592 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1593 if (!cpu_arch_tune_set)
1594 {
1595 cpu_arch_tune = cpu_arch_isa;
1596 cpu_arch_tune_flags = cpu_arch_isa_flags;
1597 }
5c6af06e
JB		 1598 break;
1599 }
40fb9820 1600
c6fb90c8
L		 1601 flags = cpu_flags_or (cpu_arch_flags,
1602 cpu_arch[i].flags);
1603 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1604 {
1605 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1606 cpu_arch_flags = flags;
1607 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1608 }
1609 *input_line_pointer = e;
1610 demand_empty_rest_of_line ();
1611 return;
e413e4e9
AM		 1612 }
1613 }
9103f4f4 1614 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1615 as_bad (_("no such architecture: `%s'"), string);
1616
1617 *input_line_pointer = e;
1618 }
1619 else
1620 as_bad (_("missing cpu architecture"));
1621
fddf5b5b
AM		 1622 no_cond_jump_promotion = 0;
1623 if (*input_line_pointer == ','
29b0f896 1624 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1625 {
1626 char *string = ++input_line_pointer;
1627 int e = get_symbol_end ();
1628
1629 if (strcmp (string, "nojumps") == 0)
1630 no_cond_jump_promotion = 1;
1631 else if (strcmp (string, "jumps") == 0)
1632 ;
1633 else
1634 as_bad (_("no such architecture modifier: `%s'"), string);
1635
1636 *input_line_pointer = e;
1637 }
1638
e413e4e9
AM		 1639 demand_empty_rest_of_line ();
1640}
1641
b9d79e03
JH		 1642unsigned long
1643i386_mach ()
1644{
1645 if (!strcmp (default_arch, "x86_64"))
1646 return bfd_mach_x86_64;
1647 else if (!strcmp (default_arch, "i386"))
1648 return bfd_mach_i386_i386;
1649 else
1650 as_fatal (_("Unknown architecture"));
1651}
b9d79e03 1652\f
252b5132
RH		 1653void
1654md_begin ()
1655{
1656 const char *hash_err;
1657
40fb9820
L		 1658 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1659
47926f60 1660 /* Initialize op_hash hash table. */
252b5132
RH		 1661 op_hash = hash_new ();
1662
1663 {
29b0f896
AM		 1664 const template *optab;
1665 templates *core_optab;
252b5132 1666
47926f60
KH		 1667 /* Setup for loop. */
1668 optab = i386_optab;
252b5132
RH		 1669 core_optab = (templates *) xmalloc (sizeof (templates));
1670 core_optab->start = optab;
1671
1672 while (1)
1673 {
1674 ++optab;
1675 if (optab->name == NULL
1676 || strcmp (optab->name, (optab - 1)->name) != 0)
1677 {
1678 /* different name --> ship out current template list;
47926f60 1679 add to hash table; & begin anew. */
252b5132
RH		 1680 core_optab->end = optab;
1681 hash_err = hash_insert (op_hash,
1682 (optab - 1)->name,
1683 (PTR) core_optab);
1684 if (hash_err)
1685 {
252b5132
RH		 1686 as_fatal (_("Internal Error: Can't hash %s: %s"),
1687 (optab - 1)->name,
1688 hash_err);
1689 }
1690 if (optab->name == NULL)
1691 break;
1692 core_optab = (templates *) xmalloc (sizeof (templates));
1693 core_optab->start = optab;
1694 }
1695 }
1696 }
1697
47926f60 1698 /* Initialize reg_hash hash table. */
252b5132
RH		 1699 reg_hash = hash_new ();
1700 {
29b0f896 1701 const reg_entry *regtab;
c3fe08fa 1702 unsigned int regtab_size = i386_regtab_size;
252b5132 1703
c3fe08fa 1704 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1705 {
1706 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1707 if (hash_err)
3e73aa7c
JH		 1708 as_fatal (_("Internal Error: Can't hash %s: %s"),
1709 regtab->reg_name,
1710 hash_err);
252b5132
RH		 1711 }
1712 }
1713
47926f60 1714 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1715 {
29b0f896
AM		 1716 int c;
1717 char *p;
252b5132
RH		 1718
1719 for (c = 0; c < 256; c++)
1720 {
3882b010 1721 if (ISDIGIT (c))
252b5132
RH		 1722 {
1723 digit_chars[c] = c;
1724 mnemonic_chars[c] = c;
1725 register_chars[c] = c;
1726 operand_chars[c] = c;
1727 }
3882b010 1728 else if (ISLOWER (c))
252b5132
RH		 1729 {
1730 mnemonic_chars[c] = c;
1731 register_chars[c] = c;
1732 operand_chars[c] = c;
1733 }
3882b010 1734 else if (ISUPPER (c))
252b5132 1735 {
3882b010 1736 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1737 register_chars[c] = mnemonic_chars[c];
1738 operand_chars[c] = c;
1739 }
1740
3882b010 1741 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1742 identifier_chars[c] = c;
1743 else if (c >= 128)
1744 {
1745 identifier_chars[c] = c;
1746 operand_chars[c] = c;
1747 }
1748 }
1749
1750#ifdef LEX_AT
1751 identifier_chars['@'] = '@';
32137342
NC		 1752#endif
1753#ifdef LEX_QM
1754 identifier_chars['?'] = '?';
1755 operand_chars['?'] = '?';
252b5132 1756#endif
252b5132 1757 digit_chars['-'] = '-';
791fe849 1758 mnemonic_chars['-'] = '-';
0003779b 1759 mnemonic_chars['.'] = '.';
252b5132
RH		 1760 identifier_chars['_'] = '_';
1761 identifier_chars['.'] = '.';
1762
1763 for (p = operand_special_chars; *p != '\0'; p++)
1764 operand_chars[(unsigned char) *p] = *p;
1765 }
1766
1767#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1768 if (IS_ELF)
252b5132
RH		 1769 {
1770 record_alignment (text_section, 2);
1771 record_alignment (data_section, 2);
1772 record_alignment (bss_section, 2);
1773 }
1774#endif
a4447b93
RH		 1775
1776 if (flag_code == CODE_64BIT)
1777 {
1778 x86_dwarf2_return_column = 16;
1779 x86_cie_data_alignment = -8;
1780 }
1781 else
1782 {
1783 x86_dwarf2_return_column = 8;
1784 x86_cie_data_alignment = -4;
1785 }
252b5132
RH		 1786}
1787
1788void
e3bb37b5 1789i386_print_statistics (FILE *file)
252b5132
RH		 1790{
1791 hash_print_statistics (file, "i386 opcode", op_hash);
1792 hash_print_statistics (file, "i386 register", reg_hash);
1793}
1794\f
252b5132
RH		 1795#ifdef DEBUG386
1796
ce8a8b2f 1797/* Debugging routines for md_assemble. */
e3bb37b5 1798static void pte (template *);
40fb9820 1799static void pt (i386_operand_type);
e3bb37b5
L		 1800static void pe (expressionS *);
1801static void ps (symbolS *);
252b5132
RH		 1802
1803static void
e3bb37b5 1804pi (char *line, i386_insn *x)
252b5132 1805{
09f131f2 1806 unsigned int i;
252b5132
RH		 1807
1808 fprintf (stdout, "%s: template ", line);
1809 pte (&x->tm);
09f131f2
JH		 1810 fprintf (stdout, " address: base %s index %s scale %x\n",
1811 x->base_reg ? x->base_reg->reg_name : "none",
1812 x->index_reg ? x->index_reg->reg_name : "none",
1813 x->log2_scale_factor);
1814 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1815 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1816 fprintf (stdout, " sib: base %x index %x scale %x\n",
1817 x->sib.base, x->sib.index, x->sib.scale);
1818 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1819 (x->rex & REX_W) != 0,
1820 (x->rex & REX_R) != 0,
1821 (x->rex & REX_X) != 0,
1822 (x->rex & REX_B) != 0);
85f10a01
MM		 1823 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1824 x->drex.reg, x->drex.rex);
252b5132
RH		 1825 for (i = 0; i < x->operands; i++)
1826 {
1827 fprintf (stdout, " #%d: ", i + 1);
1828 pt (x->types[i]);
1829 fprintf (stdout, "\n");
40fb9820
L		 1830 if (x->types[i].bitfield.reg8
1831 || x->types[i].bitfield.reg16
1832 || x->types[i].bitfield.reg32
1833 || x->types[i].bitfield.reg64
1834 || x->types[i].bitfield.regmmx
1835 || x->types[i].bitfield.regxmm
1836 || x->types[i].bitfield.sreg2
1837 || x->types[i].bitfield.sreg3
1838 || x->types[i].bitfield.control
1839 || x->types[i].bitfield.debug
1840 || x->types[i].bitfield.test)
520dc8e8 1841 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1842 if (operand_type_check (x->types[i], imm))
520dc8e8 1843 pe (x->op[i].imms);
40fb9820 1844 if (operand_type_check (x->types[i], disp))
520dc8e8 1845 pe (x->op[i].disps);
252b5132
RH		 1846 }
1847}
1848
1849static void
e3bb37b5 1850pte (template *t)
252b5132 1851{
09f131f2 1852 unsigned int i;
252b5132 1853 fprintf (stdout, " %d operands ", t->operands);
47926f60 1854 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1855 if (t->extension_opcode != None)
1856 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1857 if (t->opcode_modifier.d)
252b5132 1858 fprintf (stdout, "D");
40fb9820 1859 if (t->opcode_modifier.w)
252b5132
RH		 1860 fprintf (stdout, "W");
1861 fprintf (stdout, "\n");
1862 for (i = 0; i < t->operands; i++)
1863 {
1864 fprintf (stdout, " #%d type ", i + 1);
1865 pt (t->operand_types[i]);
1866 fprintf (stdout, "\n");
1867 }
1868}
1869
1870static void
e3bb37b5 1871pe (expressionS *e)
252b5132 1872{
24eab124 1873 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1874 fprintf (stdout, " add_number %ld (%lx)\n",
1875 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1876 if (e->X_add_symbol)
1877 {
1878 fprintf (stdout, " add_symbol ");
1879 ps (e->X_add_symbol);
1880 fprintf (stdout, "\n");
1881 }
1882 if (e->X_op_symbol)
1883 {
1884 fprintf (stdout, " op_symbol ");
1885 ps (e->X_op_symbol);
1886 fprintf (stdout, "\n");
1887 }
1888}
1889
1890static void
e3bb37b5 1891ps (symbolS *s)
252b5132
RH		 1892{
1893 fprintf (stdout, "%s type %s%s",
1894 S_GET_NAME (s),
1895 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1896 segment_name (S_GET_SEGMENT (s)));
1897}
1898
7b81dfbb 1899static struct type_name
252b5132 1900 {
40fb9820
L		 1901 i386_operand_type mask;
1902 const char *name;
252b5132 1903 }
7b81dfbb 1904const type_names[] =
252b5132 1905{
40fb9820
L		 1906 { OPERAND_TYPE_REG8, "r8" },
1907 { OPERAND_TYPE_REG16, "r16" },
1908 { OPERAND_TYPE_REG32, "r32" },
1909 { OPERAND_TYPE_REG64, "r64" },
1910 { OPERAND_TYPE_IMM8, "i8" },
1911 { OPERAND_TYPE_IMM8, "i8s" },
1912 { OPERAND_TYPE_IMM16, "i16" },
1913 { OPERAND_TYPE_IMM32, "i32" },
1914 { OPERAND_TYPE_IMM32S, "i32s" },
1915 { OPERAND_TYPE_IMM64, "i64" },
1916 { OPERAND_TYPE_IMM1, "i1" },
1917 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1918 { OPERAND_TYPE_DISP8, "d8" },
1919 { OPERAND_TYPE_DISP16, "d16" },
1920 { OPERAND_TYPE_DISP32, "d32" },
1921 { OPERAND_TYPE_DISP32S, "d32s" },
1922 { OPERAND_TYPE_DISP64, "d64" },
1923 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1924 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1925 { OPERAND_TYPE_CONTROL, "control reg" },
1926 { OPERAND_TYPE_TEST, "test reg" },
1927 { OPERAND_TYPE_DEBUG, "debug reg" },
1928 { OPERAND_TYPE_FLOATREG, "FReg" },
1929 { OPERAND_TYPE_FLOATACC, "FAcc" },
1930 { OPERAND_TYPE_SREG2, "SReg2" },
1931 { OPERAND_TYPE_SREG3, "SReg3" },
1932 { OPERAND_TYPE_ACC, "Acc" },
1933 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1934 { OPERAND_TYPE_REGMMX, "rMMX" },
1935 { OPERAND_TYPE_REGXMM, "rXMM" },
1936 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1937};
1938
1939static void
40fb9820 1940pt (i386_operand_type t)
252b5132 1941{
40fb9820 1942 unsigned int j;
c6fb90c8 1943 i386_operand_type a;
252b5132 1944
40fb9820 1945 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1946 {
1947 a = operand_type_and (t, type_names[j].mask);
1948 if (!UINTS_ALL_ZERO (a))
1949 fprintf (stdout, "%s, ", type_names[j].name);
1950 }
252b5132
RH		 1951 fflush (stdout);
1952}
1953
1954#endif /* DEBUG386 */
1955\f
252b5132 1956static bfd_reloc_code_real_type
3956db08 1957reloc (unsigned int size,
64e74474
AM		 1958 int pcrel,
1959 int sign,
1960 bfd_reloc_code_real_type other)
252b5132 1961{
47926f60 1962 if (other != NO_RELOC)
3956db08
JB		 1963 {
1964 reloc_howto_type *reloc;
1965
1966 if (size == 8)
1967 switch (other)
1968 {
64e74474
AM		 1969 case BFD_RELOC_X86_64_GOT32:
1970 return BFD_RELOC_X86_64_GOT64;
1971 break;
1972 case BFD_RELOC_X86_64_PLTOFF64:
1973 return BFD_RELOC_X86_64_PLTOFF64;
1974 break;
1975 case BFD_RELOC_X86_64_GOTPC32:
1976 other = BFD_RELOC_X86_64_GOTPC64;
1977 break;
1978 case BFD_RELOC_X86_64_GOTPCREL:
1979 other = BFD_RELOC_X86_64_GOTPCREL64;
1980 break;
1981 case BFD_RELOC_X86_64_TPOFF32:
1982 other = BFD_RELOC_X86_64_TPOFF64;
1983 break;
1984 case BFD_RELOC_X86_64_DTPOFF32:
1985 other = BFD_RELOC_X86_64_DTPOFF64;
1986 break;
1987 default:
1988 break;
3956db08 1989 }
e05278af
JB		 1990
1991 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1992 if (size == 4 && flag_code != CODE_64BIT)
1993 sign = -1;
1994
3956db08
JB		 1995 reloc = bfd_reloc_type_lookup (stdoutput, other);
1996 if (!reloc)
1997 as_bad (_("unknown relocation (%u)"), other);
1998 else if (size != bfd_get_reloc_size (reloc))
1999 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2000 bfd_get_reloc_size (reloc),
2001 size);
2002 else if (pcrel && !reloc->pc_relative)
2003 as_bad (_("non-pc-relative relocation for pc-relative field"));
2004 else if ((reloc->complain_on_overflow == complain_overflow_signed
2005 && !sign)
2006 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2007 && sign > 0))
3956db08
JB		 2008 as_bad (_("relocated field and relocation type differ in signedness"));
2009 else
2010 return other;
2011 return NO_RELOC;
2012 }
252b5132
RH		 2013
2014 if (pcrel)
2015 {
3e73aa7c 2016 if (!sign)
3956db08 2017 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2018 switch (size)
2019 {
2020 case 1: return BFD_RELOC_8_PCREL;
2021 case 2: return BFD_RELOC_16_PCREL;
2022 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2023 case 8: return BFD_RELOC_64_PCREL;
252b5132 2024 }
3956db08 2025 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2026 }
2027 else
2028 {
3956db08 2029 if (sign > 0)
e5cb08ac 2030 switch (size)
3e73aa7c
JH		 2031 {
2032 case 4: return BFD_RELOC_X86_64_32S;
2033 }
2034 else
2035 switch (size)
2036 {
2037 case 1: return BFD_RELOC_8;
2038 case 2: return BFD_RELOC_16;
2039 case 4: return BFD_RELOC_32;
2040 case 8: return BFD_RELOC_64;
2041 }
3956db08
JB		 2042 as_bad (_("cannot do %s %u byte relocation"),
2043 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2044 }
2045
bfb32b52 2046 abort ();
252b5132
RH		 2047 return BFD_RELOC_NONE;
2048}
2049
47926f60
KH		 2050/* Here we decide which fixups can be adjusted to make them relative to
2051 the beginning of the section instead of the symbol. Basically we need
2052 to make sure that the dynamic relocations are done correctly, so in
2053 some cases we force the original symbol to be used. */
2054
252b5132 2055int
e3bb37b5 2056tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2057{
6d249963 2058#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2059 if (!IS_ELF)
31312f95
AM		 2060 return 1;
2061
a161fe53
AM		 2062 /* Don't adjust pc-relative references to merge sections in 64-bit
2063 mode. */
2064 if (use_rela_relocations
2065 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2066 && fixP->fx_pcrel)
252b5132 2067 return 0;
31312f95 2068
8d01d9a9
AJ		 2069 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2070 and changed later by validate_fix. */
2071 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2072 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2073 return 0;
2074
ce8a8b2f 2075 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2076 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2077 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2078 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2079 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2080 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2081 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2082 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2083 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2084 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2085 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2086 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2087 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2088 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2089 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2090 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2091 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2092 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2093 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2094 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2095 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2096 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2097 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2098 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2099 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2100 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2101 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2102 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2103 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2104 return 0;
31312f95 2105#endif
252b5132
RH		 2106 return 1;
2107}
252b5132 2108
b4cac588 2109static int
e3bb37b5 2110intel_float_operand (const char *mnemonic)
252b5132 2111{
9306ca4a
JB		 2112 /* Note that the value returned is meaningful only for opcodes with (memory)
2113 operands, hence the code here is free to improperly handle opcodes that
2114 have no operands (for better performance and smaller code). */
2115
2116 if (mnemonic[0] != 'f')
2117 return 0; /* non-math */
2118
2119 switch (mnemonic[1])
2120 {
2121 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2122 the fs segment override prefix not currently handled because no
2123 call path can make opcodes without operands get here */
2124 case 'i':
2125 return 2 /* integer op */;
2126 case 'l':
2127 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2128 return 3; /* fldcw/fldenv */
2129 break;
2130 case 'n':
2131 if (mnemonic[2] != 'o' /* fnop */)
2132 return 3; /* non-waiting control op */
2133 break;
2134 case 'r':
2135 if (mnemonic[2] == 's')
2136 return 3; /* frstor/frstpm */
2137 break;
2138 case 's':
2139 if (mnemonic[2] == 'a')
2140 return 3; /* fsave */
2141 if (mnemonic[2] == 't')
2142 {
2143 switch (mnemonic[3])
2144 {
2145 case 'c': /* fstcw */
2146 case 'd': /* fstdw */
2147 case 'e': /* fstenv */
2148 case 's': /* fsts[gw] */
2149 return 3;
2150 }
2151 }
2152 break;
2153 case 'x':
2154 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2155 return 0; /* fxsave/fxrstor are not really math ops */
2156 break;
2157 }
252b5132 2158
9306ca4a 2159 return 1;
252b5132
RH		 2160}
2161
2162/* This is the guts of the machine-dependent assembler. LINE points to a
2163 machine dependent instruction. This function is supposed to emit
2164 the frags/bytes it assembles to. */
2165
2166void
2167md_assemble (line)
2168 char *line;
2169{
40fb9820 2170 unsigned int j;
252b5132
RH		 2171 char mnemonic[MAX_MNEM_SIZE];
2172
47926f60 2173 /* Initialize globals. */
252b5132
RH		 2174 memset (&i, '\0', sizeof (i));
2175 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2176 i.reloc[j] = NO_RELOC;
252b5132
RH		 2177 memset (disp_expressions, '\0', sizeof (disp_expressions));
2178 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2179 save_stack_p = save_stack;
252b5132
RH		 2180
2181 /* First parse an instruction mnemonic & call i386_operand for the operands.
2182 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2183 start of a (possibly prefixed) mnemonic. */
252b5132 2184
29b0f896
AM		 2185 line = parse_insn (line, mnemonic);
2186 if (line == NULL)
2187 return;
252b5132 2188
29b0f896
AM		 2189 line = parse_operands (line, mnemonic);
2190 if (line == NULL)
2191 return;
252b5132 2192
29b0f896
AM		 2193 /* Now we've parsed the mnemonic into a set of templates, and have the
2194 operands at hand. */
2195
2196 /* All intel opcodes have reversed operands except for "bound" and
2197 "enter". We also don't reverse intersegment "jmp" and "call"
2198 instructions with 2 immediate operands so that the immediate segment
050dfa73 2199 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2200 if (intel_syntax
2201 && i.operands > 1
29b0f896 2202 && (strcmp (mnemonic, "bound") != 0)
30123838 2203 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2204 && !(operand_type_check (i.types[0], imm)
2205 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2206 swap_operands ();
2207
ec56d5c0
JB		 2208 /* The order of the immediates should be reversed
2209 for 2 immediates extrq and insertq instructions */
2210 if (i.imm_operands == 2
2211 && (strcmp (mnemonic, "extrq") == 0
2212 || strcmp (mnemonic, "insertq") == 0))
2213 swap_2_operands (0, 1);
2214
29b0f896
AM		 2215 if (i.imm_operands)
2216 optimize_imm ();
2217
b300c311
L		 2218 /* Don't optimize displacement for movabs since it only takes 64bit
2219 displacement. */
2220 if (i.disp_operands
2221 && (flag_code != CODE_64BIT
2222 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2223 optimize_disp ();
2224
2225 /* Next, we find a template that matches the given insn,
2226 making sure the overlap of the given operands types is consistent
2227 with the template operand types. */
252b5132 2228
29b0f896
AM		 2229 if (!match_template ())
2230 return;
252b5132 2231
cd61ebfe
AM		 2232 if (intel_syntax)
2233 {
2234 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2235 if (SYSV386_COMPAT
2236 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2237 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2238
2239 /* Zap movzx and movsx suffix. The suffix may have been set from
2240 "word ptr" or "byte ptr" on the source operand, but we'll use
2241 the suffix later to choose the destination register. */
2242 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2243 {
2244 if (i.reg_operands < 2
2245 && !i.suffix
40fb9820
L		 2246 && (!i.tm.opcode_modifier.no_bsuf
2247 || !i.tm.opcode_modifier.no_wsuf
2248 || !i.tm.opcode_modifier.no_lsuf
2249 || !i.tm.opcode_modifier.no_ssuf
7ce189b3 2250 || !i.tm.opcode_modifier.no_ldsuf
40fb9820 2251 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2252 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2253
2254 i.suffix = 0;
2255 }
cd61ebfe 2256 }
24eab124 2257
40fb9820 2258 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2259 if (!add_prefix (FWAIT_OPCODE))
2260 return;
252b5132 2261
29b0f896 2262 /* Check string instruction segment overrides. */
40fb9820 2263 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2264 {
2265 if (!check_string ())
5dd0794d 2266 return;
29b0f896 2267 }
5dd0794d 2268
29b0f896
AM		 2269 if (!process_suffix ())
2270 return;
e413e4e9 2271
29b0f896
AM		 2272 /* Make still unresolved immediate matches conform to size of immediate
2273 given in i.suffix. */
2274 if (!finalize_imm ())
2275 return;
252b5132 2276
40fb9820 2277 if (i.types[0].bitfield.imm1)
29b0f896 2278 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2279
40fb9820 2280 for (j = 0; j < 3; j++)
c6fb90c8
L		 2281 if (i.types[j].bitfield.inoutportreg
2282 || i.types[j].bitfield.shiftcount
2283 || i.types[j].bitfield.acc
2284 || i.types[j].bitfield.floatacc)
40fb9820
L		 2285 i.reg_operands--;
2286
2287 if (i.tm.opcode_modifier.immext)
29b0f896 2288 {
02fc3089
L		 2289 expressionS *exp;
2290
40fb9820 2291 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2292 {
b7d9ef37 2293 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2294 operands with an opcode suffix which is coded in the same
2295 place as an 8-bit immediate field would be. Here we check
2296 those operands and remove them afterwards. */
2297 unsigned int x;
2298
a4622f40 2299 for (x = 0; x < i.operands; x++)
ca164297 2300 if (i.op[x].regs->reg_num != x)
a540244d
L		 2301 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2302 register_prefix,
2303 i.op[x].regs->reg_name,
2304 x + 1,
2305 i.tm.name);
ca164297
L		 2306 i.operands = 0;
2307 }
2308
29b0f896
AM		 2309 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2310 opcode suffix which is coded in the same place as an 8-bit
2311 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2312 operand from the opcode suffix stored in tm.extension_opcode.
2313 SSE5 also uses this encoding, for some of its 3 argument
2314 instructions. */
252b5132 2315
85f10a01
MM		 2316 assert (i.imm_operands == 0
2317 && (i.operands <= 2
2318 || (i.tm.cpu_flags.bitfield.cpusse5
2319 && i.operands <= 3)));
252b5132 2320
29b0f896
AM		 2321 exp = &im_expressions[i.imm_operands++];
2322 i.op[i.operands].imms = exp;
c6fb90c8 2323 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2324 i.types[i.operands].bitfield.imm8 = 1;
2325 i.operands++;
29b0f896
AM		 2326 exp->X_op = O_constant;
2327 exp->X_add_number = i.tm.extension_opcode;
2328 i.tm.extension_opcode = None;
2329 }
252b5132 2330
29b0f896
AM		 2331 /* For insns with operands there are more diddles to do to the opcode. */
2332 if (i.operands)
2333 {
2334 if (!process_operands ())
2335 return;
2336 }
40fb9820 2337 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2338 {
2339 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2340 as_warn (_("translating to `%sp'"), i.tm.name);
2341 }
252b5132 2342
29b0f896
AM		 2343 /* Handle conversion of 'int $3' --> special int3 insn. */
2344 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2345 {
2346 i.tm.base_opcode = INT3_OPCODE;
2347 i.imm_operands = 0;
2348 }
252b5132 2349
40fb9820
L		 2350 if ((i.tm.opcode_modifier.jump
2351 || i.tm.opcode_modifier.jumpbyte
2352 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2353 && i.op[0].disps->X_op == O_constant)
2354 {
2355 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2356 the absolute address given by the constant. Since ix86 jumps and
2357 calls are pc relative, we need to generate a reloc. */
2358 i.op[0].disps->X_add_symbol = &abs_symbol;
2359 i.op[0].disps->X_op = O_symbol;
2360 }
252b5132 2361
40fb9820 2362 if (i.tm.opcode_modifier.rex64)
161a04f6 2363 i.rex |= REX_W;
252b5132 2364
29b0f896
AM		 2365 /* For 8 bit registers we need an empty rex prefix. Also if the
2366 instruction already has a prefix, we need to convert old
2367 registers to new ones. */
773f551c 2368
40fb9820 2369 if ((i.types[0].bitfield.reg8
29b0f896 2370 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2371 || (i.types[1].bitfield.reg8
29b0f896 2372 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2373 || ((i.types[0].bitfield.reg8
2374 || i.types[1].bitfield.reg8)
29b0f896
AM		 2375 && i.rex != 0))
2376 {
2377 int x;
726c5dcd 2378
29b0f896
AM		 2379 i.rex |= REX_OPCODE;
2380 for (x = 0; x < 2; x++)
2381 {
2382 /* Look for 8 bit operand that uses old registers. */
40fb9820 2383 if (i.types[x].bitfield.reg8
29b0f896 2384 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2385 {
29b0f896
AM		 2386 /* In case it is "hi" register, give up. */
2387 if (i.op[x].regs->reg_num > 3)
a540244d 2388 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2389 "instruction requiring REX prefix."),
a540244d 2390 register_prefix, i.op[x].regs->reg_name);
773f551c 2391
29b0f896
AM		 2392 /* Otherwise it is equivalent to the extended register.
2393 Since the encoding doesn't change this is merely
2394 cosmetic cleanup for debug output. */
2395
2396 i.op[x].regs = i.op[x].regs + 8;
773f551c 2397 }
29b0f896
AM		 2398 }
2399 }
773f551c 2400
85f10a01
MM		 2401 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2402 REX prefix. */
2403 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2404 {
2405 i.drex.rex = i.rex;
2406 i.rex = 0;
2407 }
2408 else if (i.rex != 0)
29b0f896
AM		 2409 add_prefix (REX_OPCODE | i.rex);
2410
2411 /* We are ready to output the insn. */
2412 output_insn ();
2413}
2414
2415static char *
e3bb37b5 2416parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2417{
2418 char *l = line;
2419 char *token_start = l;
2420 char *mnem_p;
5c6af06e
JB		 2421 int supported;
2422 const template *t;
29b0f896
AM		 2423
2424 /* Non-zero if we found a prefix only acceptable with string insns. */
2425 const char *expecting_string_instruction = NULL;
45288df1 2426
29b0f896
AM		 2427 while (1)
2428 {
2429 mnem_p = mnemonic;
2430 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2431 {
2432 mnem_p++;
2433 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2434 {
29b0f896
AM		 2435 as_bad (_("no such instruction: `%s'"), token_start);
2436 return NULL;
2437 }
2438 l++;
2439 }
2440 if (!is_space_char (*l)
2441 && *l != END_OF_INSN
e44823cf
JB		 2442 && (intel_syntax
2443 || (*l != PREFIX_SEPARATOR
2444 && *l != ',')))
29b0f896
AM		 2445 {
2446 as_bad (_("invalid character %s in mnemonic"),
2447 output_invalid (*l));
2448 return NULL;
2449 }
2450 if (token_start == l)
2451 {
e44823cf 2452 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2453 as_bad (_("expecting prefix; got nothing"));
2454 else
2455 as_bad (_("expecting mnemonic; got nothing"));
2456 return NULL;
2457 }
45288df1 2458
29b0f896
AM		 2459 /* Look up instruction (or prefix) via hash table. */
2460 current_templates = hash_find (op_hash, mnemonic);
47926f60 2461
29b0f896
AM		 2462 if (*l != END_OF_INSN
2463 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2464 && current_templates
40fb9820 2465 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2466 {
c6fb90c8 2467 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2468 {
2469 as_bad ((flag_code != CODE_64BIT
2470 ? _("`%s' is only supported in 64-bit mode")
2471 : _("`%s' is not supported in 64-bit mode")),
2472 current_templates->start->name);
2473 return NULL;
2474 }
29b0f896
AM		 2475 /* If we are in 16-bit mode, do not allow addr16 or data16.
2476 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2477 if ((current_templates->start->opcode_modifier.size16
2478 || current_templates->start->opcode_modifier.size32)
29b0f896 2479 && flag_code != CODE_64BIT
40fb9820 2480 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2481 ^ (flag_code == CODE_16BIT)))
2482 {
2483 as_bad (_("redundant %s prefix"),
2484 current_templates->start->name);
2485 return NULL;
45288df1 2486 }
29b0f896
AM		 2487 /* Add prefix, checking for repeated prefixes. */
2488 switch (add_prefix (current_templates->start->base_opcode))
2489 {
2490 case 0:
2491 return NULL;
2492 case 2:
2493 expecting_string_instruction = current_templates->start->name;
2494 break;
2495 }
2496 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2497 token_start = ++l;
2498 }
2499 else
2500 break;
2501 }
45288df1 2502
29b0f896
AM		 2503 if (!current_templates)
2504 {
2505 /* See if we can get a match by trimming off a suffix. */
2506 switch (mnem_p[-1])
2507 {
2508 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2509 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2510 i.suffix = SHORT_MNEM_SUFFIX;
2511 else
29b0f896
AM		 2512 case BYTE_MNEM_SUFFIX:
2513 case QWORD_MNEM_SUFFIX:
2514 i.suffix = mnem_p[-1];
2515 mnem_p[-1] = '\0';
2516 current_templates = hash_find (op_hash, mnemonic);
2517 break;
2518 case SHORT_MNEM_SUFFIX:
2519 case LONG_MNEM_SUFFIX:
2520 if (!intel_syntax)
2521 {
2522 i.suffix = mnem_p[-1];
2523 mnem_p[-1] = '\0';
2524 current_templates = hash_find (op_hash, mnemonic);
2525 }
2526 break;
252b5132 2527
29b0f896
AM		 2528 /* Intel Syntax. */
2529 case 'd':
2530 if (intel_syntax)
2531 {
9306ca4a 2532 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2533 i.suffix = SHORT_MNEM_SUFFIX;
2534 else
2535 i.suffix = LONG_MNEM_SUFFIX;
2536 mnem_p[-1] = '\0';
2537 current_templates = hash_find (op_hash, mnemonic);
2538 }
2539 break;
2540 }
2541 if (!current_templates)
2542 {
2543 as_bad (_("no such instruction: `%s'"), token_start);
2544 return NULL;
2545 }
2546 }
252b5132 2547
40fb9820
L		 2548 if (current_templates->start->opcode_modifier.jump
2549 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2550 {
2551 /* Check for a branch hint. We allow ",pt" and ",pn" for
2552 predict taken and predict not taken respectively.
2553 I'm not sure that branch hints actually do anything on loop
2554 and jcxz insns (JumpByte) for current Pentium4 chips. They
2555 may work in the future and it doesn't hurt to accept them
2556 now. */
2557 if (l[0] == ',' && l[1] == 'p')
2558 {
2559 if (l[2] == 't')
2560 {
2561 if (!add_prefix (DS_PREFIX_OPCODE))
2562 return NULL;
2563 l += 3;
2564 }
2565 else if (l[2] == 'n')
2566 {
2567 if (!add_prefix (CS_PREFIX_OPCODE))
2568 return NULL;
2569 l += 3;
2570 }
2571 }
2572 }
2573 /* Any other comma loses. */
2574 if (*l == ',')
2575 {
2576 as_bad (_("invalid character %s in mnemonic"),
2577 output_invalid (*l));
2578 return NULL;
2579 }
252b5132 2580
29b0f896 2581 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2582 supported = 0;
2583 for (t = current_templates->start; t < current_templates->end; ++t)
2584 {
40fb9820 2585 if (cpu_flags_match (t->cpu_flags))
64e74474 2586 supported |= 1;
c6fb90c8 2587 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2588 supported |= 2;
5c6af06e
JB		 2589 }
2590 if (!(supported & 2))
2591 {
2592 as_bad (flag_code == CODE_64BIT
2593 ? _("`%s' is not supported in 64-bit mode")
2594 : _("`%s' is only supported in 64-bit mode"),
2595 current_templates->start->name);
2596 return NULL;
2597 }
2598 if (!(supported & 1))
29b0f896 2599 {
5c6af06e
JB		 2600 as_warn (_("`%s' is not supported on `%s%s'"),
2601 current_templates->start->name,
2602 cpu_arch_name,
2603 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2604 }
40fb9820
L		 2605 else if (!cpu_arch_flags.bitfield.cpui386
2606 && (flag_code != CODE_16BIT))
29b0f896
AM		 2607 {
2608 as_warn (_("use .code16 to ensure correct addressing mode"));
2609 }
252b5132 2610
29b0f896 2611 /* Check for rep/repne without a string instruction. */
f41bbced 2612 if (expecting_string_instruction)
29b0f896 2613 {
f41bbced
JB		 2614 static templates override;
2615
2616 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2617 if (t->opcode_modifier.isstring)
f41bbced
JB		 2618 break;
2619 if (t >= current_templates->end)
2620 {
2621 as_bad (_("expecting string instruction after `%s'"),
64e74474 2622 expecting_string_instruction);
f41bbced
JB		 2623 return NULL;
2624 }
2625 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2626 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2627 break;
2628 override.end = t;
2629 current_templates = &override;
29b0f896 2630 }
252b5132 2631
29b0f896
AM		 2632 return l;
2633}
252b5132 2634
29b0f896 2635static char *
e3bb37b5 2636parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2637{
2638 char *token_start;
3138f287 2639
29b0f896
AM		 2640 /* 1 if operand is pending after ','. */
2641 unsigned int expecting_operand = 0;
252b5132 2642
29b0f896
AM		 2643 /* Non-zero if operand parens not balanced. */
2644 unsigned int paren_not_balanced;
2645
2646 while (*l != END_OF_INSN)
2647 {
2648 /* Skip optional white space before operand. */
2649 if (is_space_char (*l))
2650 ++l;
2651 if (!is_operand_char (*l) && *l != END_OF_INSN)
2652 {
2653 as_bad (_("invalid character %s before operand %d"),
2654 output_invalid (*l),
2655 i.operands + 1);
2656 return NULL;
2657 }
2658 token_start = l; /* after white space */
2659 paren_not_balanced = 0;
2660 while (paren_not_balanced || *l != ',')
2661 {
2662 if (*l == END_OF_INSN)
2663 {
2664 if (paren_not_balanced)
2665 {
2666 if (!intel_syntax)
2667 as_bad (_("unbalanced parenthesis in operand %d."),
2668 i.operands + 1);
2669 else
2670 as_bad (_("unbalanced brackets in operand %d."),
2671 i.operands + 1);
2672 return NULL;
2673 }
2674 else
2675 break; /* we are done */
2676 }
2677 else if (!is_operand_char (*l) && !is_space_char (*l))
2678 {
2679 as_bad (_("invalid character %s in operand %d"),
2680 output_invalid (*l),
2681 i.operands + 1);
2682 return NULL;
2683 }
2684 if (!intel_syntax)
2685 {
2686 if (*l == '(')
2687 ++paren_not_balanced;
2688 if (*l == ')')
2689 --paren_not_balanced;
2690 }
2691 else
2692 {
2693 if (*l == '[')
2694 ++paren_not_balanced;
2695 if (*l == ']')
2696 --paren_not_balanced;
2697 }
2698 l++;
2699 }
2700 if (l != token_start)
2701 { /* Yes, we've read in another operand. */
2702 unsigned int operand_ok;
2703 this_operand = i.operands++;
2704 if (i.operands > MAX_OPERANDS)
2705 {
2706 as_bad (_("spurious operands; (%d operands/instruction max)"),
2707 MAX_OPERANDS);
2708 return NULL;
2709 }
2710 /* Now parse operand adding info to 'i' as we go along. */
2711 END_STRING_AND_SAVE (l);
2712
2713 if (intel_syntax)
2714 operand_ok =
2715 i386_intel_operand (token_start,
2716 intel_float_operand (mnemonic));
2717 else
2718 operand_ok = i386_operand (token_start);
2719
2720 RESTORE_END_STRING (l);
2721 if (!operand_ok)
2722 return NULL;
2723 }
2724 else
2725 {
2726 if (expecting_operand)
2727 {
2728 expecting_operand_after_comma:
2729 as_bad (_("expecting operand after ','; got nothing"));
2730 return NULL;
2731 }
2732 if (*l == ',')
2733 {
2734 as_bad (_("expecting operand before ','; got nothing"));
2735 return NULL;
2736 }
2737 }
7f3f1ea2 2738
29b0f896
AM		 2739 /* Now *l must be either ',' or END_OF_INSN. */
2740 if (*l == ',')
2741 {
2742 if (*++l == END_OF_INSN)
2743 {
2744 /* Just skip it, if it's \n complain. */
2745 goto expecting_operand_after_comma;
2746 }
2747 expecting_operand = 1;
2748 }
2749 }
2750 return l;
2751}
7f3f1ea2 2752
050dfa73 2753static void
4d456e3d 2754swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2755{
2756 union i386_op temp_op;
40fb9820 2757 i386_operand_type temp_type;
050dfa73 2758 enum bfd_reloc_code_real temp_reloc;
4eed87de 2759
050dfa73
MM		 2760 temp_type = i.types[xchg2];
2761 i.types[xchg2] = i.types[xchg1];
2762 i.types[xchg1] = temp_type;
2763 temp_op = i.op[xchg2];
2764 i.op[xchg2] = i.op[xchg1];
2765 i.op[xchg1] = temp_op;
2766 temp_reloc = i.reloc[xchg2];
2767 i.reloc[xchg2] = i.reloc[xchg1];
2768 i.reloc[xchg1] = temp_reloc;
2769}
2770
29b0f896 2771static void
e3bb37b5 2772swap_operands (void)
29b0f896 2773{
b7c61d9a 2774 switch (i.operands)
050dfa73 2775 {
b7c61d9a 2776 case 4:
4d456e3d 2777 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2778 case 3:
2779 case 2:
4d456e3d 2780 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2781 break;
2782 default:
2783 abort ();
29b0f896 2784 }
29b0f896
AM		 2785
2786 if (i.mem_operands == 2)
2787 {
2788 const seg_entry *temp_seg;
2789 temp_seg = i.seg[0];
2790 i.seg[0] = i.seg[1];
2791 i.seg[1] = temp_seg;
2792 }
2793}
252b5132 2794
29b0f896
AM		 2795/* Try to ensure constant immediates are represented in the smallest
2796 opcode possible. */
2797static void
e3bb37b5 2798optimize_imm (void)
29b0f896
AM		 2799{
2800 char guess_suffix = 0;
2801 int op;
252b5132 2802
29b0f896
AM		 2803 if (i.suffix)
2804 guess_suffix = i.suffix;
2805 else if (i.reg_operands)
2806 {
2807 /* Figure out a suffix from the last register operand specified.
2808 We can't do this properly yet, ie. excluding InOutPortReg,
2809 but the following works for instructions with immediates.
2810 In any case, we can't set i.suffix yet. */
2811 for (op = i.operands; --op >= 0;)
40fb9820
L		 2812 if (i.types[op].bitfield.reg8)
2813 {
2814 guess_suffix = BYTE_MNEM_SUFFIX;
2815 break;
2816 }
2817 else if (i.types[op].bitfield.reg16)
252b5132 2818 {
40fb9820
L		 2819 guess_suffix = WORD_MNEM_SUFFIX;
2820 break;
2821 }
2822 else if (i.types[op].bitfield.reg32)
2823 {
2824 guess_suffix = LONG_MNEM_SUFFIX;
2825 break;
2826 }
2827 else if (i.types[op].bitfield.reg64)
2828 {
2829 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2830 break;
252b5132 2831 }
29b0f896
AM		 2832 }
2833 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2834 guess_suffix = WORD_MNEM_SUFFIX;
2835
2836 for (op = i.operands; --op >= 0;)
40fb9820 2837 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2838 {
2839 switch (i.op[op].imms->X_op)
252b5132 2840 {
29b0f896
AM		 2841 case O_constant:
2842 /* If a suffix is given, this operand may be shortened. */
2843 switch (guess_suffix)
252b5132 2844 {
29b0f896 2845 case LONG_MNEM_SUFFIX:
40fb9820
L		 2846 i.types[op].bitfield.imm32 = 1;
2847 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2848 break;
2849 case WORD_MNEM_SUFFIX:
40fb9820
L		 2850 i.types[op].bitfield.imm16 = 1;
2851 i.types[op].bitfield.imm32 = 1;
2852 i.types[op].bitfield.imm32s = 1;
2853 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2854 break;
2855 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2856 i.types[op].bitfield.imm8 = 1;
2857 i.types[op].bitfield.imm8s = 1;
2858 i.types[op].bitfield.imm16 = 1;
2859 i.types[op].bitfield.imm32 = 1;
2860 i.types[op].bitfield.imm32s = 1;
2861 i.types[op].bitfield.imm64 = 1;
29b0f896 2862 break;
252b5132 2863 }
252b5132 2864
29b0f896
AM		 2865 /* If this operand is at most 16 bits, convert it
2866 to a signed 16 bit number before trying to see
2867 whether it will fit in an even smaller size.
2868 This allows a 16-bit operand such as $0xffe0 to
2869 be recognised as within Imm8S range. */
40fb9820 2870 if ((i.types[op].bitfield.imm16)
29b0f896 2871 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2872 {
29b0f896
AM		 2873 i.op[op].imms->X_add_number =
2874 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2875 }
40fb9820 2876 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2877 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2878 == 0))
2879 {
2880 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2881 ^ ((offsetT) 1 << 31))
2882 - ((offsetT) 1 << 31));
2883 }
40fb9820 2884 i.types[op]
c6fb90c8
L		 2885 = operand_type_or (i.types[op],
2886 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2887
29b0f896
AM		 2888 /* We must avoid matching of Imm32 templates when 64bit
2889 only immediate is available. */
2890 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2891 i.types[op].bitfield.imm32 = 0;
29b0f896 2892 break;
252b5132 2893
29b0f896
AM		 2894 case O_absent:
2895 case O_register:
2896 abort ();
2897
2898 /* Symbols and expressions. */
2899 default:
9cd96992
JB		 2900 /* Convert symbolic operand to proper sizes for matching, but don't
2901 prevent matching a set of insns that only supports sizes other
2902 than those matching the insn suffix. */
2903 {
40fb9820 2904 i386_operand_type mask, allowed;
9cd96992
JB		 2905 const template *t;
2906
c6fb90c8
L		 2907 UINTS_CLEAR (mask);
2908 UINTS_CLEAR (allowed);
40fb9820 2909
4eed87de
AM		 2910 for (t = current_templates->start;
2911 t < current_templates->end;
2912 ++t)
c6fb90c8
L		 2913 allowed = operand_type_or (allowed,
2914 t->operand_types[op]);
9cd96992
JB		 2915 switch (guess_suffix)
2916 {
2917 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2918 mask.bitfield.imm64 = 1;
2919 mask.bitfield.imm32s = 1;
9cd96992
JB		 2920 break;
2921 case LONG_MNEM_SUFFIX:
40fb9820 2922 mask.bitfield.imm32 = 1;
9cd96992
JB		 2923 break;
2924 case WORD_MNEM_SUFFIX:
40fb9820 2925 mask.bitfield.imm16 = 1;
9cd96992
JB		 2926 break;
2927 case BYTE_MNEM_SUFFIX:
40fb9820 2928 mask.bitfield.imm8 = 1;
9cd96992
JB		 2929 break;
2930 default:
9cd96992
JB		 2931 break;
2932 }
c6fb90c8
L		 2933 allowed = operand_type_and (mask, allowed);
2934 if (!UINTS_ALL_ZERO (allowed))
2935 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2936 }
29b0f896 2937 break;
252b5132 2938 }
29b0f896
AM		 2939 }
2940}
47926f60 2941
29b0f896
AM		 2942/* Try to use the smallest displacement type too. */
2943static void
e3bb37b5 2944optimize_disp (void)
29b0f896
AM		 2945{
2946 int op;
3e73aa7c 2947
29b0f896 2948 for (op = i.operands; --op >= 0;)
40fb9820 2949 if (operand_type_check (i.types[op], disp))
252b5132 2950 {
b300c311 2951 if (i.op[op].disps->X_op == O_constant)
252b5132 2952 {
b300c311 2953 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2954
40fb9820 2955 if (i.types[op].bitfield.disp16
b300c311
L		 2956 && (disp & ~(offsetT) 0xffff) == 0)
2957 {
2958 /* If this operand is at most 16 bits, convert
2959 to a signed 16 bit number and don't use 64bit
2960 displacement. */
2961 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2962 i.types[op].bitfield.disp64 = 0;
b300c311 2963 }
40fb9820 2964 if (i.types[op].bitfield.disp32
b300c311
L		 2965 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2966 {
2967 /* If this operand is at most 32 bits, convert
2968 to a signed 32 bit number and don't use 64bit
2969 displacement. */
2970 disp &= (((offsetT) 2 << 31) - 1);
2971 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2972 i.types[op].bitfield.disp64 = 0;
b300c311 2973 }
40fb9820 2974 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2975 {
40fb9820
L		 2976 i.types[op].bitfield.disp8 = 0;
2977 i.types[op].bitfield.disp16 = 0;
2978 i.types[op].bitfield.disp32 = 0;
2979 i.types[op].bitfield.disp32s = 0;
2980 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2981 i.op[op].disps = 0;
2982 i.disp_operands--;
2983 }
2984 else if (flag_code == CODE_64BIT)
2985 {
2986 if (fits_in_signed_long (disp))
28a9d8f5 2987 {
40fb9820
L		 2988 i.types[op].bitfield.disp64 = 0;
2989 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2990 }
b300c311 2991 if (fits_in_unsigned_long (disp))
40fb9820 2992 i.types[op].bitfield.disp32 = 1;
b300c311 2993 }
40fb9820
L		 2994 if ((i.types[op].bitfield.disp32
2995 || i.types[op].bitfield.disp32s
2996 || i.types[op].bitfield.disp16)
b300c311 2997 && fits_in_signed_byte (disp))
40fb9820 2998 i.types[op].bitfield.disp8 = 1;
252b5132 2999 }
67a4f2b7
AO		 3000 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3001 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3002 {
3003 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3004 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3005 i.types[op].bitfield.disp8 = 0;
3006 i.types[op].bitfield.disp16 = 0;
3007 i.types[op].bitfield.disp32 = 0;
3008 i.types[op].bitfield.disp32s = 0;
3009 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3010 }
3011 else
b300c311 3012 /* We only support 64bit displacement on constants. */
40fb9820 3013 i.types[op].bitfield.disp64 = 0;
252b5132 3014 }
29b0f896
AM		 3015}
3016
3017static int
e3bb37b5 3018match_template (void)
29b0f896
AM		 3019{
3020 /* Points to template once we've found it. */
3021 const template *t;
40fb9820 3022 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 3023 unsigned int found_reverse_match;
40fb9820
L		 3024 i386_opcode_modifier suffix_check;
3025 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3026 int addr_prefix_disp;
a5c311ca 3027 unsigned int j;
c6fb90c8 3028 i386_cpu_flags overlap;
29b0f896 3029
f48ff2ae
L		 3030#if MAX_OPERANDS != 4
3031# error "MAX_OPERANDS must be 4."
3032#endif
3033
29b0f896 3034 found_reverse_match = 0;
539e75ad 3035 addr_prefix_disp = -1;
40fb9820
L		 3036
3037 memset (&suffix_check, 0, sizeof (suffix_check));
3038 if (i.suffix == BYTE_MNEM_SUFFIX)
3039 suffix_check.no_bsuf = 1;
3040 else if (i.suffix == WORD_MNEM_SUFFIX)
3041 suffix_check.no_wsuf = 1;
3042 else if (i.suffix == SHORT_MNEM_SUFFIX)
3043 suffix_check.no_ssuf = 1;
3044 else if (i.suffix == LONG_MNEM_SUFFIX)
3045 suffix_check.no_lsuf = 1;
3046 else if (i.suffix == QWORD_MNEM_SUFFIX)
3047 suffix_check.no_qsuf = 1;
3048 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3049 suffix_check.no_ldsuf = 1;
29b0f896 3050
45aa61fe 3051 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3052 {
539e75ad
L		 3053 addr_prefix_disp = -1;
3054
29b0f896
AM		 3055 /* Must have right number of operands. */
3056 if (i.operands != t->operands)
3057 continue;
3058
1efbbeb4
L		 3059 /* Check AT&T mnemonic and old gcc support. */
3060 if (t->opcode_modifier.attmnemonic
3061 && (intel_mnemonic
3062 || (!old_gcc
3063 && t->opcode_modifier.oldgcc)))
3064 continue;
3065
3066 /* Check Intel mnemonic. */
3067 if (!intel_mnemonic && t->opcode_modifier.intelmnemonic)
3068 continue;
3069
20592a94 3070 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3071 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3072 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3073 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3074 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3075 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3076 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3077 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3078 continue;
3079
a5c311ca
L		 3080 for (j = 0; j < MAX_OPERANDS; j++)
3081 operand_types [j] = t->operand_types [j];
539e75ad 3082
45aa61fe
AM		 3083 /* In general, don't allow 64-bit operands in 32-bit mode. */
3084 if (i.suffix == QWORD_MNEM_SUFFIX
3085 && flag_code != CODE_64BIT
3086 && (intel_syntax
40fb9820 3087 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3088 && !intel_float_operand (t->name))
3089 : intel_float_operand (t->name) != 2)
40fb9820
L		 3090 && ((!operand_types[0].bitfield.regmmx
3091 && !operand_types[0].bitfield.regxmm)
3092 || (!operand_types[t->operands > 1].bitfield.regmmx
3093 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3094 && (t->base_opcode != 0x0fc7
3095 || t->extension_opcode != 1 /* cmpxchg8b */))
3096 continue;
3097
29b0f896 3098 /* Do not verify operands when there are none. */
c6fb90c8 3099 else
29b0f896 3100 {
c6fb90c8
L		 3101 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3102 if (!t->operands)
3103 {
3104 if (!UINTS_ALL_ZERO (overlap))
3105 continue;
3106 /* We've found a match; break out of loop. */
3107 break;
3108 }
29b0f896 3109 }
252b5132 3110
539e75ad
L		 3111 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3112 into Disp32/Disp16/Disp32 operand. */
3113 if (i.prefix[ADDR_PREFIX] != 0)
3114 {
40fb9820 3115 /* There should be only one Disp operand. */
539e75ad
L		 3116 switch (flag_code)
3117 {
3118 case CODE_16BIT:
40fb9820
L		 3119 for (j = 0; j < MAX_OPERANDS; j++)
3120 {
3121 if (operand_types[j].bitfield.disp16)
3122 {
3123 addr_prefix_disp = j;
3124 operand_types[j].bitfield.disp32 = 1;
3125 operand_types[j].bitfield.disp16 = 0;
3126 break;
3127 }
3128 }
539e75ad
L		 3129 break;
3130 case CODE_32BIT:
40fb9820
L		 3131 for (j = 0; j < MAX_OPERANDS; j++)
3132 {
3133 if (operand_types[j].bitfield.disp32)
3134 {
3135 addr_prefix_disp = j;
3136 operand_types[j].bitfield.disp32 = 0;
3137 operand_types[j].bitfield.disp16 = 1;
3138 break;
3139 }
3140 }
539e75ad
L		 3141 break;
3142 case CODE_64BIT:
40fb9820
L		 3143 for (j = 0; j < MAX_OPERANDS; j++)
3144 {
3145 if (operand_types[j].bitfield.disp64)
3146 {
3147 addr_prefix_disp = j;
3148 operand_types[j].bitfield.disp64 = 0;
3149 operand_types[j].bitfield.disp32 = 1;
3150 break;
3151 }
3152 }
539e75ad
L		 3153 break;
3154 }
539e75ad
L		 3155 }
3156
c6fb90c8 3157 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3158 switch (t->operands)
3159 {
3160 case 1:
40fb9820 3161 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3162 continue;
3163 break;
3164 case 2:
8b38ad71
L		 3165 /* xchg %eax, %eax is a special case. It is an aliase for nop
3166 only in 32bit mode and we can use opcode 0x90. In 64bit
3167 mode, we can't use 0x90 for xchg %eax, %eax since it should
3168 zero-extend %eax to %rax. */
3169 if (flag_code == CODE_64BIT
3170 && t->base_opcode == 0x90
c6fb90c8
L		 3171 && UINTS_EQUAL (i.types [0], acc32)
3172 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3173 continue;
29b0f896 3174 case 3:
f48ff2ae 3175 case 4:
c6fb90c8 3176 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3177 if (!operand_type_match (overlap0, i.types[0])
3178 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3179 /* monitor in SSE3 is a very special case. The first
708587a4 3180 register and the second register may have different
26186d74
L		 3181 sizes. The same applies to crc32 in SSE4.2. It is
3182 also true for invlpga, vmload, vmrun and vmsave in
3183 SVME. */
cb712a9e 3184 || !((t->base_opcode == 0x0f01
26186d74
L		 3185 && (t->extension_opcode == 0xc8
3186 || t->extension_opcode == 0xd8
3187 || t->extension_opcode == 0xda
3188 || t->extension_opcode == 0xdb
3189 || t->extension_opcode == 0xdf))
381d071f 3190 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3191 || operand_type_register_match (overlap0, i.types[0],
3192 operand_types[0],
3193 overlap1, i.types[1],
3194 operand_types[1])))
29b0f896
AM		 3195 {
3196 /* Check if other direction is valid ... */
40fb9820 3197 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3198 continue;
3199
3200 /* Try reversing direction of operands. */
c6fb90c8
L		 3201 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3202 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3203 if (!operand_type_match (overlap0, i.types[0])
3204 || !operand_type_match (overlap1, i.types[1])
3205 || !operand_type_register_match (overlap0, i.types[0],
3206 operand_types[1],
3207 overlap1, i.types[1],
3208 operand_types[0]))
29b0f896
AM		 3209 {
3210 /* Does not match either direction. */
3211 continue;
3212 }
3213 /* found_reverse_match holds which of D or FloatDR
3214 we've found. */
40fb9820 3215 if (t->opcode_modifier.d)
8a2ed489 3216 found_reverse_match = Opcode_D;
40fb9820 3217 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3218 found_reverse_match = Opcode_FloatD;
3219 else
3220 found_reverse_match = 0;
40fb9820 3221 if (t->opcode_modifier.floatr)
8a2ed489 3222 found_reverse_match |= Opcode_FloatR;
29b0f896 3223 }
f48ff2ae 3224 else
29b0f896 3225 {
f48ff2ae 3226 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3227 switch (t->operands)
3228 {
3229 case 4:
c6fb90c8
L		 3230 overlap3 = operand_type_and (i.types[3],
3231 operand_types[3]);
d1cbb4db 3232 case 3:
c6fb90c8
L		 3233 overlap2 = operand_type_and (i.types[2],
3234 operand_types[2]);
d1cbb4db
L		 3235 break;
3236 }
29b0f896 3237
f48ff2ae
L		 3238 switch (t->operands)
3239 {
3240 case 4:
40fb9820
L		 3241 if (!operand_type_match (overlap3, i.types[3])
3242 || !operand_type_register_match (overlap2,
3243 i.types[2],
3244 operand_types[2],
3245 overlap3,
3246 i.types[3],
3247 operand_types[3]))
f48ff2ae
L		 3248 continue;
3249 case 3:
3250 /* Here we make use of the fact that there are no
3251 reverse match 3 operand instructions, and all 3
3252 operand instructions only need to be checked for
3253 register consistency between operands 2 and 3. */
40fb9820
L		 3254 if (!operand_type_match (overlap2, i.types[2])
3255 || !operand_type_register_match (overlap1,
3256 i.types[1],
3257 operand_types[1],
3258 overlap2,
3259 i.types[2],
3260 operand_types[2]))
f48ff2ae
L		 3261 continue;
3262 break;
3263 }
29b0f896 3264 }
f48ff2ae 3265 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3266 slip through to break. */
3267 }
c6fb90c8 3268 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3269 {
3270 found_reverse_match = 0;
3271 continue;
3272 }
3273 /* We've found a match; break out of loop. */
3274 break;
3275 }
3276
3277 if (t == current_templates->end)
3278 {
3279 /* We found no match. */
3280 as_bad (_("suffix or operands invalid for `%s'"),
3281 current_templates->start->name);
3282 return 0;
3283 }
252b5132 3284
29b0f896
AM		 3285 if (!quiet_warnings)
3286 {
3287 if (!intel_syntax
40fb9820
L		 3288 && (i.types[0].bitfield.jumpabsolute
3289 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3290 {
3291 as_warn (_("indirect %s without `*'"), t->name);
3292 }
3293
40fb9820
L		 3294 if (t->opcode_modifier.isprefix
3295 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3296 {
3297 /* Warn them that a data or address size prefix doesn't
3298 affect assembly of the next line of code. */
3299 as_warn (_("stand-alone `%s' prefix"), t->name);
3300 }
3301 }
3302
3303 /* Copy the template we found. */
3304 i.tm = *t;
539e75ad
L		 3305
3306 if (addr_prefix_disp != -1)
3307 i.tm.operand_types[addr_prefix_disp]
3308 = operand_types[addr_prefix_disp];
3309
29b0f896
AM		 3310 if (found_reverse_match)
3311 {
3312 /* If we found a reverse match we must alter the opcode
3313 direction bit. found_reverse_match holds bits to change
3314 (different for int & float insns). */
3315
3316 i.tm.base_opcode ^= found_reverse_match;
3317
539e75ad
L		 3318 i.tm.operand_types[0] = operand_types[1];
3319 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3320 }
3321
3322 return 1;
3323}
3324
3325static int
e3bb37b5 3326check_string (void)
29b0f896 3327{
40fb9820
L		 3328 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3329 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3330 {
3331 if (i.seg[0] != NULL && i.seg[0] != &es)
3332 {
3333 as_bad (_("`%s' operand %d must use `%%es' segment"),
3334 i.tm.name,
3335 mem_op + 1);
3336 return 0;
3337 }
3338 /* There's only ever one segment override allowed per instruction.
3339 This instruction possibly has a legal segment override on the
3340 second operand, so copy the segment to where non-string
3341 instructions store it, allowing common code. */
3342 i.seg[0] = i.seg[1];
3343 }
40fb9820 3344 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3345 {
3346 if (i.seg[1] != NULL && i.seg[1] != &es)
3347 {
3348 as_bad (_("`%s' operand %d must use `%%es' segment"),
3349 i.tm.name,
3350 mem_op + 2);
3351 return 0;
3352 }
3353 }
3354 return 1;
3355}
3356
3357static int
543613e9 3358process_suffix (void)
29b0f896
AM		 3359{
3360 /* If matched instruction specifies an explicit instruction mnemonic
3361 suffix, use it. */
40fb9820
L		 3362 if (i.tm.opcode_modifier.size16)
3363 i.suffix = WORD_MNEM_SUFFIX;
3364 else if (i.tm.opcode_modifier.size32)
3365 i.suffix = LONG_MNEM_SUFFIX;
3366 else if (i.tm.opcode_modifier.size64)
3367 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3368 else if (i.reg_operands)
3369 {
3370 /* If there's no instruction mnemonic suffix we try to invent one
3371 based on register operands. */
3372 if (!i.suffix)
3373 {
3374 /* We take i.suffix from the last register operand specified,
3375 Destination register type is more significant than source
381d071f
L		 3376 register type. crc32 in SSE4.2 prefers source register
3377 type. */
3378 if (i.tm.base_opcode == 0xf20f38f1)
3379 {
40fb9820
L		 3380 if (i.types[0].bitfield.reg16)
3381 i.suffix = WORD_MNEM_SUFFIX;
3382 else if (i.types[0].bitfield.reg32)
3383 i.suffix = LONG_MNEM_SUFFIX;
3384 else if (i.types[0].bitfield.reg64)
3385 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3386 }
9344ff29 3387 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3388 {
40fb9820 3389 if (i.types[0].bitfield.reg8)
20592a94
L		 3390 i.suffix = BYTE_MNEM_SUFFIX;
3391 }
381d071f
L		 3392
3393 if (!i.suffix)
3394 {
3395 int op;
3396
20592a94
L		 3397 if (i.tm.base_opcode == 0xf20f38f1
3398 || i.tm.base_opcode == 0xf20f38f0)
3399 {
3400 /* We have to know the operand size for crc32. */
3401 as_bad (_("ambiguous memory operand size for `%s`"),
3402 i.tm.name);
3403 return 0;
3404 }
3405
381d071f 3406 for (op = i.operands; --op >= 0;)
40fb9820 3407 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3408 {
40fb9820
L		 3409 if (i.types[op].bitfield.reg8)
3410 {
3411 i.suffix = BYTE_MNEM_SUFFIX;
3412 break;
3413 }
3414 else if (i.types[op].bitfield.reg16)
3415 {
3416 i.suffix = WORD_MNEM_SUFFIX;
3417 break;
3418 }
3419 else if (i.types[op].bitfield.reg32)
3420 {
3421 i.suffix = LONG_MNEM_SUFFIX;
3422 break;
3423 }
3424 else if (i.types[op].bitfield.reg64)
3425 {
3426 i.suffix = QWORD_MNEM_SUFFIX;
3427 break;
3428 }
381d071f
L		 3429 }
3430 }
29b0f896
AM		 3431 }
3432 else if (i.suffix == BYTE_MNEM_SUFFIX)
3433 {
3434 if (!check_byte_reg ())
3435 return 0;
3436 }
3437 else if (i.suffix == LONG_MNEM_SUFFIX)
3438 {
3439 if (!check_long_reg ())
3440 return 0;
3441 }
3442 else if (i.suffix == QWORD_MNEM_SUFFIX)
3443 {
955e1e6a
L		 3444 if (intel_syntax
3445 && i.tm.opcode_modifier.ignoresize
3446 && i.tm.opcode_modifier.no_qsuf)
3447 i.suffix = 0;
3448 else if (!check_qword_reg ())
29b0f896
AM		 3449 return 0;
3450 }
3451 else if (i.suffix == WORD_MNEM_SUFFIX)
3452 {
3453 if (!check_word_reg ())
3454 return 0;
3455 }
40fb9820 3456 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3457 /* Do nothing if the instruction is going to ignore the prefix. */
3458 ;
3459 else
3460 abort ();
3461 }
40fb9820 3462 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3463 && !i.suffix
3464 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3465 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3466 {
3467 i.suffix = stackop_size;
3468 }
9306ca4a
JB		 3469 else if (intel_syntax
3470 && !i.suffix
40fb9820
L		 3471 && (i.tm.operand_types[0].bitfield.jumpabsolute
3472 || i.tm.opcode_modifier.jumpbyte
3473 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3474 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3475 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3476 {
3477 switch (flag_code)
3478 {
3479 case CODE_64BIT:
40fb9820 3480 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3481 {
3482 i.suffix = QWORD_MNEM_SUFFIX;
3483 break;
3484 }
3485 case CODE_32BIT:
40fb9820 3486 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3487 i.suffix = LONG_MNEM_SUFFIX;
3488 break;
3489 case CODE_16BIT:
40fb9820 3490 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3491 i.suffix = WORD_MNEM_SUFFIX;
3492 break;
3493 }
3494 }
252b5132 3495
9306ca4a 3496 if (!i.suffix)
29b0f896 3497 {
9306ca4a
JB		 3498 if (!intel_syntax)
3499 {
40fb9820 3500 if (i.tm.opcode_modifier.w)
9306ca4a 3501 {
4eed87de
AM		 3502 as_bad (_("no instruction mnemonic suffix given and "
3503 "no register operands; can't size instruction"));
9306ca4a
JB		 3504 return 0;
3505 }
3506 }
3507 else
3508 {
40fb9820
L		 3509 unsigned int suffixes;
3510
3511 suffixes = !i.tm.opcode_modifier.no_bsuf;
3512 if (!i.tm.opcode_modifier.no_wsuf)
3513 suffixes |= 1 << 1;
3514 if (!i.tm.opcode_modifier.no_lsuf)
3515 suffixes |= 1 << 2;
3516 if (!i.tm.opcode_modifier.no_lsuf)
3517 suffixes |= 1 << 3;
3518 if (!i.tm.opcode_modifier.no_ssuf)
3519 suffixes |= 1 << 4;
3520 if (!i.tm.opcode_modifier.no_qsuf)
3521 suffixes |= 1 << 5;
3522
3523 /* There are more than suffix matches. */
3524 if (i.tm.opcode_modifier.w
9306ca4a 3525 || ((suffixes & (suffixes - 1))
40fb9820
L		 3526 && !i.tm.opcode_modifier.defaultsize
3527 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3528 {
3529 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3530 return 0;
3531 }
3532 }
29b0f896 3533 }
252b5132 3534
9306ca4a
JB		 3535 /* Change the opcode based on the operand size given by i.suffix;
3536 We don't need to change things for byte insns. */
3537
29b0f896
AM		 3538 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3539 {
3540 /* It's not a byte, select word/dword operation. */
40fb9820 3541 if (i.tm.opcode_modifier.w)
29b0f896 3542 {
40fb9820 3543 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3544 i.tm.base_opcode |= 8;
3545 else
3546 i.tm.base_opcode |= 1;
3547 }
0f3f3d8b 3548
29b0f896
AM		 3549 /* Now select between word & dword operations via the operand
3550 size prefix, except for instructions that will ignore this
3551 prefix anyway. */
ca61edf2 3552 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3553 {
ca61edf2
L		 3554 /* The address size override prefix changes the size of the
3555 first operand. */
40fb9820
L		 3556 if ((flag_code == CODE_32BIT
3557 && i.op->regs[0].reg_type.bitfield.reg16)
3558 || (flag_code != CODE_32BIT
3559 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3560 if (!add_prefix (ADDR_PREFIX_OPCODE))
3561 return 0;
3562 }
3563 else if (i.suffix != QWORD_MNEM_SUFFIX
3564 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3565 && !i.tm.opcode_modifier.ignoresize
3566 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3567 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3568 || (flag_code == CODE_64BIT
40fb9820 3569 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3570 {
3571 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3572
40fb9820 3573 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3574 prefix = ADDR_PREFIX_OPCODE;
252b5132 3575
29b0f896
AM		 3576 if (!add_prefix (prefix))
3577 return 0;
24eab124 3578 }
252b5132 3579
29b0f896
AM		 3580 /* Set mode64 for an operand. */
3581 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3582 && flag_code == CODE_64BIT
40fb9820 3583 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3584 {
3585 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3586 need rex64. cmpxchg8b is also a special case. */
3587 if (! (i.operands == 2
3588 && i.tm.base_opcode == 0x90
3589 && i.tm.extension_opcode == None
c6fb90c8
L		 3590 && UINTS_EQUAL (i.types [0], acc64)
3591 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3592 && ! (i.operands == 1
3593 && i.tm.base_opcode == 0xfc7
3594 && i.tm.extension_opcode == 1
40fb9820
L		 3595 && !operand_type_check (i.types [0], reg)
3596 && operand_type_check (i.types [0], anymem)))
f6bee062 3597 i.rex |= REX_W;
46e883c5 3598 }
3e73aa7c 3599
29b0f896
AM		 3600 /* Size floating point instruction. */
3601 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3602 if (i.tm.opcode_modifier.floatmf)
543613e9 3603 i.tm.base_opcode ^= 4;
29b0f896 3604 }
7ecd2f8b 3605
29b0f896
AM		 3606 return 1;
3607}
3e73aa7c 3608
29b0f896 3609static int
543613e9 3610check_byte_reg (void)
29b0f896
AM		 3611{
3612 int op;
543613e9 3613
29b0f896
AM		 3614 for (op = i.operands; --op >= 0;)
3615 {
3616 /* If this is an eight bit register, it's OK. If it's the 16 or
3617 32 bit version of an eight bit register, we will just use the
3618 low portion, and that's OK too. */
40fb9820 3619 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3620 continue;
3621
ca61edf2
L		 3622 /* Don't generate this warning if not needed. */
3623 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3624 continue;
3625
9344ff29
L		 3626 /* crc32 doesn't generate this warning. */
3627 if (i.tm.base_opcode == 0xf20f38f0)
3628 continue;
3629
40fb9820
L		 3630 if ((i.types[op].bitfield.reg16
3631 || i.types[op].bitfield.reg32
3632 || i.types[op].bitfield.reg64)
3633 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3634 {
3635 /* Prohibit these changes in the 64bit mode, since the
3636 lowering is more complicated. */
3637 if (flag_code == CODE_64BIT
40fb9820 3638 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3639 {
2ca3ace5
L		 3640 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3641 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3642 i.suffix);
3643 return 0;
3644 }
3645#if REGISTER_WARNINGS
3646 if (!quiet_warnings
40fb9820 3647 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3648 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3649 register_prefix,
40fb9820 3650 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3651 ? REGNAM_AL - REGNAM_AX
3652 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3653 register_prefix,
29b0f896
AM		 3654 i.op[op].regs->reg_name,
3655 i.suffix);
3656#endif
3657 continue;
3658 }
3659 /* Any other register is bad. */
40fb9820
L		 3660 if (i.types[op].bitfield.reg16
3661 || i.types[op].bitfield.reg32
3662 || i.types[op].bitfield.reg64
3663 || i.types[op].bitfield.regmmx
3664 || i.types[op].bitfield.regxmm
3665 || i.types[op].bitfield.sreg2
3666 || i.types[op].bitfield.sreg3
3667 || i.types[op].bitfield.control
3668 || i.types[op].bitfield.debug
3669 || i.types[op].bitfield.test
3670 || i.types[op].bitfield.floatreg
3671 || i.types[op].bitfield.floatacc)
29b0f896 3672 {
a540244d
L		 3673 as_bad (_("`%s%s' not allowed with `%s%c'"),
3674 register_prefix,
29b0f896
AM		 3675 i.op[op].regs->reg_name,
3676 i.tm.name,
3677 i.suffix);
3678 return 0;
3679 }
3680 }
3681 return 1;
3682}
3683
3684static int
e3bb37b5 3685check_long_reg (void)
29b0f896
AM		 3686{
3687 int op;
3688
3689 for (op = i.operands; --op >= 0;)
3690 /* Reject eight bit registers, except where the template requires
3691 them. (eg. movzb) */
40fb9820
L		 3692 if (i.types[op].bitfield.reg8
3693 && (i.tm.operand_types[op].bitfield.reg16
3694 || i.tm.operand_types[op].bitfield.reg32
3695 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3696 {
a540244d
L		 3697 as_bad (_("`%s%s' not allowed with `%s%c'"),
3698 register_prefix,
29b0f896
AM		 3699 i.op[op].regs->reg_name,
3700 i.tm.name,
3701 i.suffix);
3702 return 0;
3703 }
3704 /* Warn if the e prefix on a general reg is missing. */
3705 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3706 && i.types[op].bitfield.reg16
3707 && (i.tm.operand_types[op].bitfield.reg32
3708 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3709 {
3710 /* Prohibit these changes in the 64bit mode, since the
3711 lowering is more complicated. */
3712 if (flag_code == CODE_64BIT)
252b5132 3713 {
2ca3ace5
L		 3714 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3715 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3716 i.suffix);
3717 return 0;
252b5132 3718 }
29b0f896
AM		 3719#if REGISTER_WARNINGS
3720 else
a540244d
L		 3721 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3722 register_prefix,
29b0f896 3723 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3724 register_prefix,
29b0f896
AM		 3725 i.op[op].regs->reg_name,
3726 i.suffix);
3727#endif
252b5132 3728 }
29b0f896 3729 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3730 else if (i.types[op].bitfield.reg64
3731 && (i.tm.operand_types[op].bitfield.reg32
3732 || i.tm.operand_types[op].bitfield.acc))
252b5132 3733 {
34828aad 3734 if (intel_syntax
ca61edf2 3735 && i.tm.opcode_modifier.toqword
40fb9820 3736 && !i.types[0].bitfield.regxmm)
34828aad 3737 {
ca61edf2 3738 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3739 i.suffix = QWORD_MNEM_SUFFIX;
3740 }
3741 else
3742 {
3743 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3744 register_prefix, i.op[op].regs->reg_name,
3745 i.suffix);
3746 return 0;
3747 }
29b0f896
AM		 3748 }
3749 return 1;
3750}
252b5132 3751
29b0f896 3752static int
e3bb37b5 3753check_qword_reg (void)
29b0f896
AM		 3754{
3755 int op;
252b5132 3756
29b0f896
AM		 3757 for (op = i.operands; --op >= 0; )
3758 /* Reject eight bit registers, except where the template requires
3759 them. (eg. movzb) */
40fb9820
L		 3760 if (i.types[op].bitfield.reg8
3761 && (i.tm.operand_types[op].bitfield.reg16
3762 || i.tm.operand_types[op].bitfield.reg32
3763 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3764 {
a540244d
L		 3765 as_bad (_("`%s%s' not allowed with `%s%c'"),
3766 register_prefix,
29b0f896
AM		 3767 i.op[op].regs->reg_name,
3768 i.tm.name,
3769 i.suffix);
3770 return 0;
3771 }
3772 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3773 else if ((i.types[op].bitfield.reg16
3774 || i.types[op].bitfield.reg32)
3775 && (i.tm.operand_types[op].bitfield.reg32
3776 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3777 {
3778 /* Prohibit these changes in the 64bit mode, since the
3779 lowering is more complicated. */
34828aad 3780 if (intel_syntax
ca61edf2 3781 && i.tm.opcode_modifier.todword
40fb9820 3782 && !i.types[0].bitfield.regxmm)
34828aad 3783 {
ca61edf2 3784 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 3785 i.suffix = LONG_MNEM_SUFFIX;
3786 }
3787 else
3788 {
3789 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3790 register_prefix, i.op[op].regs->reg_name,
3791 i.suffix);
3792 return 0;
3793 }
252b5132 3794 }
29b0f896
AM		 3795 return 1;
3796}
252b5132 3797
29b0f896 3798static int
e3bb37b5 3799check_word_reg (void)
29b0f896
AM		 3800{
3801 int op;
3802 for (op = i.operands; --op >= 0;)
3803 /* Reject eight bit registers, except where the template requires
3804 them. (eg. movzb) */
40fb9820
L		 3805 if (i.types[op].bitfield.reg8
3806 && (i.tm.operand_types[op].bitfield.reg16
3807 || i.tm.operand_types[op].bitfield.reg32
3808 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3809 {
a540244d
L		 3810 as_bad (_("`%s%s' not allowed with `%s%c'"),
3811 register_prefix,
29b0f896
AM		 3812 i.op[op].regs->reg_name,
3813 i.tm.name,
3814 i.suffix);
3815 return 0;
3816 }
3817 /* Warn if the e prefix on a general reg is present. */
3818 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3819 && i.types[op].bitfield.reg32
3820 && (i.tm.operand_types[op].bitfield.reg16
3821 || i.tm.operand_types[op].bitfield.acc))
252b5132 3822 {
29b0f896
AM		 3823 /* Prohibit these changes in the 64bit mode, since the
3824 lowering is more complicated. */
3825 if (flag_code == CODE_64BIT)
252b5132 3826 {
2ca3ace5
L		 3827 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3828 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3829 i.suffix);
3830 return 0;
252b5132 3831 }
29b0f896
AM		 3832 else
3833#if REGISTER_WARNINGS
a540244d
L		 3834 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3835 register_prefix,
29b0f896 3836 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3837 register_prefix,
29b0f896
AM		 3838 i.op[op].regs->reg_name,
3839 i.suffix);
3840#endif
3841 }
3842 return 1;
3843}
252b5132 3844
29b0f896 3845static int
40fb9820 3846update_imm (unsigned int j)
29b0f896 3847{
40fb9820
L		 3848 i386_operand_type overlap;
3849
c6fb90c8 3850 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3851 if ((overlap.bitfield.imm8
3852 || overlap.bitfield.imm8s
3853 || overlap.bitfield.imm16
3854 || overlap.bitfield.imm32
3855 || overlap.bitfield.imm32s
3856 || overlap.bitfield.imm64)
c6fb90c8
L		 3857 && !UINTS_EQUAL (overlap, imm8)
3858 && !UINTS_EQUAL (overlap, imm8s)
3859 && !UINTS_EQUAL (overlap, imm16)
3860 && !UINTS_EQUAL (overlap, imm32)
3861 && !UINTS_EQUAL (overlap, imm32s)
3862 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3863 {
3864 if (i.suffix)
3865 {
40fb9820
L		 3866 i386_operand_type temp;
3867
c6fb90c8 3868 UINTS_CLEAR (temp);
40fb9820
L		 3869 if (i.suffix == BYTE_MNEM_SUFFIX)
3870 {
3871 temp.bitfield.imm8 = overlap.bitfield.imm8;
3872 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3873 }
3874 else if (i.suffix == WORD_MNEM_SUFFIX)
3875 temp.bitfield.imm16 = overlap.bitfield.imm16;
3876 else if (i.suffix == QWORD_MNEM_SUFFIX)
3877 {
3878 temp.bitfield.imm64 = overlap.bitfield.imm64;
3879 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3880 }
3881 else
3882 temp.bitfield.imm32 = overlap.bitfield.imm32;
3883 overlap = temp;
29b0f896 3884 }
c6fb90c8
L		 3885 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3886 || UINTS_EQUAL (overlap, imm16_32)
3887 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3888 {
c6fb90c8 3889 UINTS_CLEAR (overlap);
40fb9820
L		 3890 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3891 overlap.bitfield.imm16 = 1;
3892 else
3893 overlap.bitfield.imm32s = 1;
29b0f896 3894 }
c6fb90c8
L		 3895 if (!UINTS_EQUAL (overlap, imm8)
3896 && !UINTS_EQUAL (overlap, imm8s)
3897 && !UINTS_EQUAL (overlap, imm16)
3898 && !UINTS_EQUAL (overlap, imm32)
3899 && !UINTS_EQUAL (overlap, imm32s)
3900 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3901 {
4eed87de
AM		 3902 as_bad (_("no instruction mnemonic suffix given; "
3903 "can't determine immediate size"));
29b0f896
AM		 3904 return 0;
3905 }
3906 }
40fb9820 3907 i.types[j] = overlap;
29b0f896 3908
40fb9820
L		 3909 return 1;
3910}
3911
3912static int
3913finalize_imm (void)
3914{
3915 unsigned int j;
29b0f896 3916
40fb9820
L		 3917 for (j = 0; j < 2; j++)
3918 if (update_imm (j) == 0)
3919 return 0;
3920
c6fb90c8 3921 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3922 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3923
3924 return 1;
3925}
3926
85f10a01
MM		 3927static void
3928process_drex (void)
3929{
3930 i.drex.modrm_reg = None;
3931 i.drex.modrm_regmem = None;
3932
3933 /* SSE5 4 operand instructions must have the destination the same as
3934 one of the inputs. Figure out the destination register and cache
3935 it away in the drex field, and remember which fields to use for
3936 the modrm byte. */
3937 if (i.tm.opcode_modifier.drex
3938 && i.tm.opcode_modifier.drexv
3939 && i.operands == 4)
3940 {
3941 i.tm.extension_opcode = None;
3942
3943 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3944 if (i.types[0].bitfield.regxmm != 0
3945 && i.types[1].bitfield.regxmm != 0
3946 && i.types[2].bitfield.regxmm != 0
3947 && i.types[3].bitfield.regxmm != 0
3948 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3949 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3950 {
3951 /* Clear the arguments that are stored in drex. */
3952 UINTS_CLEAR (i.types[0]);
3953 UINTS_CLEAR (i.types[3]);
3954 i.reg_operands -= 2;
3955
3956 /* There are two different ways to encode a 4 operand
3957 instruction with all registers that uses OC1 set to
3958 0 or 1. Favor setting OC1 to 0 since this mimics the
3959 actions of other SSE5 assemblers. Use modrm encoding 2
3960 for register/register. Include the high order bit that
3961 is normally stored in the REX byte in the register
3962 field. */
3963 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3964 i.drex.modrm_reg = 2;
3965 i.drex.modrm_regmem = 1;
3966 i.drex.reg = (i.op[3].regs->reg_num
3967 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3968 }
3969
3970 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3971 else if (i.types[0].bitfield.regxmm != 0
3972 && i.types[1].bitfield.regxmm != 0
3973 && (i.types[2].bitfield.regxmm
3974 || operand_type_check (i.types[2], anymem))
3975 && i.types[3].bitfield.regxmm != 0
3976 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3977 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3978 {
3979 /* clear the arguments that are stored in drex */
3980 UINTS_CLEAR (i.types[0]);
3981 UINTS_CLEAR (i.types[3]);
3982 i.reg_operands -= 2;
3983
3984 /* Specify the modrm encoding for memory addressing. Include
3985 the high order bit that is normally stored in the REX byte
3986 in the register field. */
3987 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3988 i.drex.modrm_reg = 1;
3989 i.drex.modrm_regmem = 2;
3990 i.drex.reg = (i.op[3].regs->reg_num
3991 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3992 }
3993
3994 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3995 else if (i.types[0].bitfield.regxmm != 0
3996 && operand_type_check (i.types[1], anymem) != 0
3997 && i.types[2].bitfield.regxmm != 0
3998 && i.types[3].bitfield.regxmm != 0
3999 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4000 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4001 {
4002 /* Clear the arguments that are stored in drex. */
4003 UINTS_CLEAR (i.types[0]);
4004 UINTS_CLEAR (i.types[3]);
4005 i.reg_operands -= 2;
4006
4007 /* Specify the modrm encoding for memory addressing. Include
4008 the high order bit that is normally stored in the REX byte
4009 in the register field. */
4010 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4011 i.drex.modrm_reg = 2;
4012 i.drex.modrm_regmem = 1;
4013 i.drex.reg = (i.op[3].regs->reg_num
4014 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4015 }
4016
4017 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4018 else if (i.types[0].bitfield.regxmm != 0
4019 && i.types[1].bitfield.regxmm != 0
4020 && i.types[2].bitfield.regxmm != 0
4021 && i.types[3].bitfield.regxmm != 0
4022 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4023 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4024 {
4025 /* clear the arguments that are stored in drex */
4026 UINTS_CLEAR (i.types[2]);
4027 UINTS_CLEAR (i.types[3]);
4028 i.reg_operands -= 2;
4029
4030 /* There are two different ways to encode a 4 operand
4031 instruction with all registers that uses OC1 set to
4032 0 or 1. Favor setting OC1 to 0 since this mimics the
4033 actions of other SSE5 assemblers. Use modrm encoding
4034 2 for register/register. Include the high order bit that
4035 is normally stored in the REX byte in the register
4036 field. */
4037 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4038 i.drex.modrm_reg = 1;
4039 i.drex.modrm_regmem = 0;
4040
4041 /* Remember the register, including the upper bits */
4042 i.drex.reg = (i.op[3].regs->reg_num
4043 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4044 }
4045
4046 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4047 else if (i.types[0].bitfield.regxmm != 0
4048 && (i.types[1].bitfield.regxmm
4049 || operand_type_check (i.types[1], anymem))
4050 && i.types[2].bitfield.regxmm != 0
4051 && i.types[3].bitfield.regxmm != 0
4052 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4053 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4054 {
4055 /* Clear the arguments that are stored in drex. */
4056 UINTS_CLEAR (i.types[2]);
4057 UINTS_CLEAR (i.types[3]);
4058 i.reg_operands -= 2;
4059
4060 /* Specify the modrm encoding and remember the register
4061 including the bits normally stored in the REX byte. */
4062 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4063 i.drex.modrm_reg = 0;
4064 i.drex.modrm_regmem = 1;
4065 i.drex.reg = (i.op[3].regs->reg_num
4066 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4067 }
4068
4069 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4070 else if (operand_type_check (i.types[0], anymem) != 0
4071 && i.types[1].bitfield.regxmm != 0
4072 && i.types[2].bitfield.regxmm != 0
4073 && i.types[3].bitfield.regxmm != 0
4074 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4075 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4076 {
4077 /* clear the arguments that are stored in drex */
4078 UINTS_CLEAR (i.types[2]);
4079 UINTS_CLEAR (i.types[3]);
4080 i.reg_operands -= 2;
4081
4082 /* Specify the modrm encoding and remember the register
4083 including the bits normally stored in the REX byte. */
4084 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4085 i.drex.modrm_reg = 1;
4086 i.drex.modrm_regmem = 0;
4087 i.drex.reg = (i.op[3].regs->reg_num
4088 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4089 }
4090
4091 else
4092 as_bad (_("Incorrect operands for the '%s' instruction"),
4093 i.tm.name);
4094 }
4095
4096 /* SSE5 instructions with the DREX byte where the only memory operand
4097 is in the 2nd argument, and the first and last xmm register must
4098 match, and is encoded in the DREX byte. */
4099 else if (i.tm.opcode_modifier.drex
4100 && !i.tm.opcode_modifier.drexv
4101 && i.operands == 4)
4102 {
4103 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4104 if (i.types[0].bitfield.regxmm != 0
4105 && (i.types[1].bitfield.regxmm
4106 || operand_type_check(i.types[1], anymem))
4107 && i.types[2].bitfield.regxmm != 0
4108 && i.types[3].bitfield.regxmm != 0
4109 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4110 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4111 {
4112 /* clear the arguments that are stored in drex */
4113 UINTS_CLEAR (i.types[0]);
4114 UINTS_CLEAR (i.types[3]);
4115 i.reg_operands -= 2;
4116
4117 /* Specify the modrm encoding and remember the register
4118 including the high bit normally stored in the REX
4119 byte. */
4120 i.drex.modrm_reg = 2;
4121 i.drex.modrm_regmem = 1;
4122 i.drex.reg = (i.op[3].regs->reg_num
4123 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4124 }
4125
4126 else
4127 as_bad (_("Incorrect operands for the '%s' instruction"),
4128 i.tm.name);
4129 }
4130
4131 /* SSE5 3 operand instructions that the result is a register, being
4132 either operand can be a memory operand, using OC0 to note which
4133 one is the memory. */
4134 else if (i.tm.opcode_modifier.drex
4135 && i.tm.opcode_modifier.drexv
4136 && i.operands == 3)
4137 {
4138 i.tm.extension_opcode = None;
4139
4140 /* Case 1: 3 operand insn, src1 = register. */
4141 if (i.types[0].bitfield.regxmm != 0
4142 && i.types[1].bitfield.regxmm != 0
4143 && i.types[2].bitfield.regxmm != 0)
4144 {
4145 /* Clear the arguments that are stored in drex. */
4146 UINTS_CLEAR (i.types[2]);
4147 i.reg_operands--;
4148
4149 /* Specify the modrm encoding and remember the register
4150 including the high bit normally stored in the REX byte. */
4151 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4152 i.drex.modrm_reg = 1;
4153 i.drex.modrm_regmem = 0;
4154 i.drex.reg = (i.op[2].regs->reg_num
4155 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4156 }
4157
4158 /* Case 2: 3 operand insn, src1 = memory. */
4159 else if (operand_type_check (i.types[0], anymem) != 0
4160 && i.types[1].bitfield.regxmm != 0
4161 && i.types[2].bitfield.regxmm != 0)
4162 {
4163 /* Clear the arguments that are stored in drex. */
4164 UINTS_CLEAR (i.types[2]);
4165 i.reg_operands--;
4166
4167 /* Specify the modrm encoding and remember the register
4168 including the high bit normally stored in the REX
4169 byte. */
4170 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4171 i.drex.modrm_reg = 1;
4172 i.drex.modrm_regmem = 0;
4173 i.drex.reg = (i.op[2].regs->reg_num
4174 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4175 }
4176
4177 /* Case 3: 3 operand insn, src2 = memory. */
4178 else if (i.types[0].bitfield.regxmm != 0
4179 && operand_type_check (i.types[1], anymem) != 0
4180 && i.types[2].bitfield.regxmm != 0)
4181 {
4182 /* Clear the arguments that are stored in drex. */
4183 UINTS_CLEAR (i.types[2]);
4184 i.reg_operands--;
4185
4186 /* Specify the modrm encoding and remember the register
4187 including the high bit normally stored in the REX byte. */
4188 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4189 i.drex.modrm_reg = 0;
4190 i.drex.modrm_regmem = 1;
4191 i.drex.reg = (i.op[2].regs->reg_num
4192 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4193 }
4194
4195 else
4196 as_bad (_("Incorrect operands for the '%s' instruction"),
4197 i.tm.name);
4198 }
4199
4200 /* SSE5 4 operand instructions that are the comparison instructions
4201 where the first operand is the immediate value of the comparison
4202 to be done. */
4203 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4204 {
4205 /* Case 1: 4 operand insn, src1 = reg/memory. */
4206 if (operand_type_check (i.types[0], imm) != 0
4207 && (i.types[1].bitfield.regxmm
4208 || operand_type_check (i.types[1], anymem))
4209 && i.types[2].bitfield.regxmm != 0
4210 && i.types[3].bitfield.regxmm != 0)
4211 {
4212 /* clear the arguments that are stored in drex */
4213 UINTS_CLEAR (i.types[3]);
4214 i.reg_operands--;
4215
4216 /* Specify the modrm encoding and remember the register
4217 including the high bit normally stored in the REX byte. */
4218 i.drex.modrm_reg = 2;
4219 i.drex.modrm_regmem = 1;
4220 i.drex.reg = (i.op[3].regs->reg_num
4221 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4222 }
4223
4224 /* Case 2: 3 operand insn with ImmExt that places the
4225 opcode_extension as an immediate argument. This is used for
4226 all of the varients of comparison that supplies the appropriate
4227 value as part of the instruction. */
4228 else if ((i.types[0].bitfield.regxmm
4229 || operand_type_check (i.types[0], anymem))
4230 && i.types[1].bitfield.regxmm != 0
4231 && i.types[2].bitfield.regxmm != 0
4232 && operand_type_check (i.types[3], imm) != 0)
4233 {
4234 /* clear the arguments that are stored in drex */
4235 UINTS_CLEAR (i.types[2]);
4236 i.reg_operands--;
4237
4238 /* Specify the modrm encoding and remember the register
4239 including the high bit normally stored in the REX byte. */
4240 i.drex.modrm_reg = 1;
4241 i.drex.modrm_regmem = 0;
4242 i.drex.reg = (i.op[2].regs->reg_num
4243 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4244 }
4245
4246 else
4247 as_bad (_("Incorrect operands for the '%s' instruction"),
4248 i.tm.name);
4249 }
4250
4251 else if (i.tm.opcode_modifier.drex
4252 || i.tm.opcode_modifier.drexv
4253 || i.tm.opcode_modifier.drexc)
4254 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4255}
4256
29b0f896 4257static int
e3bb37b5 4258process_operands (void)
29b0f896
AM		 4259{
4260 /* Default segment register this instruction will use for memory
4261 accesses. 0 means unknown. This is only for optimizing out
4262 unnecessary segment overrides. */
4263 const seg_entry *default_seg = 0;
4264
85f10a01
MM		 4265 /* Handle all of the DREX munging that SSE5 needs. */
4266 if (i.tm.opcode_modifier.drex
4267 || i.tm.opcode_modifier.drexv
4268 || i.tm.opcode_modifier.drexc)
4269 process_drex ();
4270
e2ec9d29 4271 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4272 {
9fcfb3d7
L		 4273 unsigned int j;
4274
e2ec9d29
L		 4275 /* The first operand is implicit and must be xmm0. */
4276 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4277 if (i.op[0].regs->reg_num != 0)
4278 {
4279 if (intel_syntax)
4280 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4281 i.tm.name, register_prefix);
4282 else
4283 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4284 i.tm.name, register_prefix);
4285 return 0;
4286 }
9fcfb3d7
L		 4287
4288 for (j = 1; j < i.operands; j++)
4289 {
4290 i.op[j - 1] = i.op[j];
4291 i.types[j - 1] = i.types[j];
4292
4293 /* We need to adjust fields in i.tm since they are used by
4294 build_modrm_byte. */
4295 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4296 }
4297
e2ec9d29
L		 4298 i.operands--;
4299 i.reg_operands--;
e2ec9d29
L		 4300 i.tm.operands--;
4301 }
4302 else if (i.tm.opcode_modifier.regkludge)
4303 {
4304 /* The imul $imm, %reg instruction is converted into
4305 imul $imm, %reg, %reg, and the clr %reg instruction
4306 is converted into xor %reg, %reg. */
4307
4308 unsigned int first_reg_op;
4309
4310 if (operand_type_check (i.types[0], reg))
4311 first_reg_op = 0;
4312 else
4313 first_reg_op = 1;
4314 /* Pretend we saw the extra register operand. */
4315 assert (i.reg_operands == 1
4316 && i.op[first_reg_op + 1].regs == 0);
4317 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4318 i.types[first_reg_op + 1] = i.types[first_reg_op];
4319 i.operands++;
4320 i.reg_operands++;
29b0f896
AM		 4321 }
4322
40fb9820 4323 if (i.tm.opcode_modifier.shortform)
29b0f896 4324 {
40fb9820
L		 4325 if (i.types[0].bitfield.sreg2
4326 || i.types[0].bitfield.sreg3)
29b0f896 4327 {
4eed87de
AM		 4328 if (i.tm.base_opcode == POP_SEG_SHORT
4329 && i.op[0].regs->reg_num == 1)
29b0f896 4330 {
4eed87de
AM		 4331 as_bad (_("you can't `pop %%cs'"));
4332 return 0;
29b0f896 4333 }
4eed87de
AM		 4334 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4335 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4336 i.rex |= REX_B;
4eed87de
AM		 4337 }
4338 else
4339 {
85f10a01
MM		 4340 /* The register or float register operand is in operand
4341 0 or 1. */
40fb9820
L		 4342 unsigned int op;
4343
4344 if (i.types[0].bitfield.floatreg
4345 || operand_type_check (i.types[0], reg))
4346 op = 0;
4347 else
4348 op = 1;
4eed87de
AM		 4349 /* Register goes in low 3 bits of opcode. */
4350 i.tm.base_opcode |= i.op[op].regs->reg_num;
4351 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4352 i.rex |= REX_B;
40fb9820 4353 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4354 {
4eed87de
AM		 4355 /* Warn about some common errors, but press on regardless.
4356 The first case can be generated by gcc (<= 2.8.1). */
4357 if (i.operands == 2)
4358 {
4359 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4360 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4361 register_prefix, i.op[1].regs->reg_name,
4362 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4363 }
4364 else
4365 {
4366 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4367 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4368 register_prefix, i.op[0].regs->reg_name);
4eed87de 4369 }
29b0f896
AM		 4370 }
4371 }
4372 }
40fb9820 4373 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4374 {
4375 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4376 must be put into the modrm byte). Now, we make the modrm and
4377 index base bytes based on all the info we've collected. */
29b0f896
AM		 4378
4379 default_seg = build_modrm_byte ();
4380 }
8a2ed489 4381 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4382 {
4383 default_seg = &ds;
4384 }
40fb9820 4385 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4386 {
4387 /* For the string instructions that allow a segment override
4388 on one of their operands, the default segment is ds. */
4389 default_seg = &ds;
4390 }
4391
75178d9d
L		 4392 if (i.tm.base_opcode == 0x8d /* lea */
4393 && i.seg[0]
4394 && !quiet_warnings)
30123838 4395 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4396
4397 /* If a segment was explicitly specified, and the specified segment
4398 is not the default, use an opcode prefix to select it. If we
4399 never figured out what the default segment is, then default_seg
4400 will be zero at this point, and the specified segment prefix will
4401 always be used. */
29b0f896
AM		 4402 if ((i.seg[0]) && (i.seg[0] != default_seg))
4403 {
4404 if (!add_prefix (i.seg[0]->seg_prefix))
4405 return 0;
4406 }
4407 return 1;
4408}
4409
4410static const seg_entry *
e3bb37b5 4411build_modrm_byte (void)
29b0f896
AM		 4412{
4413 const seg_entry *default_seg = 0;
4414
85f10a01
MM		 4415 /* SSE5 4 operand instructions are encoded in such a way that one of
4416 the inputs must match the destination register. Process_drex hides
4417 the 3rd argument in the drex field, so that by the time we get
4418 here, it looks to GAS as if this is a 2 operand instruction. */
4419 if ((i.tm.opcode_modifier.drex
4420 || i.tm.opcode_modifier.drexv
b5016f89 4421 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4422 && i.reg_operands == 2)
4423 {
4424 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4425 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4426
4427 i.rm.reg = reg->reg_num;
4428 i.rm.regmem = regmem->reg_num;
4429 i.rm.mode = 3;
4430 if ((reg->reg_flags & RegRex) != 0)
4431 i.rex |= REX_R;
4432 if ((regmem->reg_flags & RegRex) != 0)
4433 i.rex |= REX_B;
4434 }
4435
29b0f896
AM		 4436 /* i.reg_operands MUST be the number of real register operands;
4437 implicit registers do not count. */
85f10a01 4438 else if (i.reg_operands == 2)
29b0f896
AM		 4439 {
4440 unsigned int source, dest;
cab737b9
L		 4441
4442 switch (i.operands)
4443 {
4444 case 2:
4445 source = 0;
4446 break;
4447 case 3:
c81128dc
L		 4448 /* When there are 3 operands, one of them may be immediate,
4449 which may be the first or the last operand. Otherwise,
4450 the first operand must be shift count register (cl). */
4451 assert (i.imm_operands == 1
4452 || (i.imm_operands == 0
40fb9820
L		 4453 && i.types[0].bitfield.shiftcount));
4454 if (operand_type_check (i.types[0], imm)
4455 || i.types[0].bitfield.shiftcount)
4456 source = 1;
4457 else
4458 source = 0;
cab737b9
L		 4459 break;
4460 case 4:
368d64cc
L		 4461 /* When there are 4 operands, the first two must be 8bit
4462 immediate operands. The source operand will be the 3rd
4463 one. */
cab737b9 4464 assert (i.imm_operands == 2
368d64cc
L		 4465 && i.types[0].bitfield.imm8
4466 && i.types[1].bitfield.imm8);
cab737b9
L		 4467 source = 2;
4468 break;
4469 default:
4470 abort ();
4471 }
4472
29b0f896
AM		 4473 dest = source + 1;
4474
4475 i.rm.mode = 3;
4476 /* One of the register operands will be encoded in the i.tm.reg
4477 field, the other in the combined i.tm.mode and i.tm.regmem
4478 fields. If no form of this instruction supports a memory
4479 destination operand, then we assume the source operand may
4480 sometimes be a memory operand and so we need to store the
4481 destination in the i.rm.reg field. */
40fb9820
L		 4482 if (!i.tm.operand_types[dest].bitfield.regmem
4483 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4484 {
4485 i.rm.reg = i.op[dest].regs->reg_num;
4486 i.rm.regmem = i.op[source].regs->reg_num;
4487 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4488 i.rex |= REX_R;
29b0f896 4489 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4490 i.rex |= REX_B;
29b0f896
AM		 4491 }
4492 else
4493 {
4494 i.rm.reg = i.op[source].regs->reg_num;
4495 i.rm.regmem = i.op[dest].regs->reg_num;
4496 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4497 i.rex |= REX_B;
29b0f896 4498 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4499 i.rex |= REX_R;
29b0f896 4500 }
161a04f6 4501 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4502 {
40fb9820
L		 4503 if (!i.types[0].bitfield.control
4504 && !i.types[1].bitfield.control)
c4a530c5 4505 abort ();
161a04f6 4506 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4507 add_prefix (LOCK_PREFIX_OPCODE);
4508 }
29b0f896
AM		 4509 }
4510 else
4511 { /* If it's not 2 reg operands... */
4512 if (i.mem_operands)
4513 {
4514 unsigned int fake_zero_displacement = 0;
99018f42 4515 unsigned int op;
4eed87de 4516
85f10a01
MM		 4517 /* This has been precalculated for SSE5 instructions
4518 that have a DREX field earlier in process_drex. */
b5016f89
L		 4519 if (i.tm.opcode_modifier.drex
4520 || i.tm.opcode_modifier.drexv
4521 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4522 op = i.drex.modrm_regmem;
4523 else
4524 {
c0209578
L		 4525 for (op = 0; op < i.operands; op++)
4526 if (operand_type_check (i.types[op], anymem))
4527 break;
4528 assert (op < i.operands);
85f10a01 4529 }
29b0f896
AM		 4530
4531 default_seg = &ds;
4532
4533 if (i.base_reg == 0)
4534 {
4535 i.rm.mode = 0;
4536 if (!i.disp_operands)
4537 fake_zero_displacement = 1;
4538 if (i.index_reg == 0)
4539 {
4540 /* Operand is just <disp> */
20f0a1fc 4541 if (flag_code == CODE_64BIT)
29b0f896
AM		 4542 {
4543 /* 64bit mode overwrites the 32bit absolute
4544 addressing by RIP relative addressing and
4545 absolute addressing is encoded by one of the
4546 redundant SIB forms. */
4547 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4548 i.sib.base = NO_BASE_REGISTER;
4549 i.sib.index = NO_INDEX_REGISTER;
fc225355 4550 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4551 ? disp32s : disp32);
20f0a1fc 4552 }
fc225355
L		 4553 else if ((flag_code == CODE_16BIT)
4554 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4555 {
4556 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4557 i.types[op] = disp16;
20f0a1fc
NC		 4558 }
4559 else
4560 {
4561 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4562 i.types[op] = disp32;
29b0f896
AM		 4563 }
4564 }
4565 else /* !i.base_reg && i.index_reg */
4566 {
db51cc60
L		 4567 if (i.index_reg->reg_num == RegEiz
4568 || i.index_reg->reg_num == RegRiz)
4569 i.sib.index = NO_INDEX_REGISTER;
4570 else
4571 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4572 i.sib.base = NO_BASE_REGISTER;
4573 i.sib.scale = i.log2_scale_factor;
4574 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4575 i.types[op].bitfield.disp8 = 0;
4576 i.types[op].bitfield.disp16 = 0;
4577 i.types[op].bitfield.disp64 = 0;
29b0f896 4578 if (flag_code != CODE_64BIT)
40fb9820
L		 4579 {
4580 /* Must be 32 bit */
4581 i.types[op].bitfield.disp32 = 1;
4582 i.types[op].bitfield.disp32s = 0;
4583 }
29b0f896 4584 else
40fb9820
L		 4585 {
4586 i.types[op].bitfield.disp32 = 0;
4587 i.types[op].bitfield.disp32s = 1;
4588 }
29b0f896 4589 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4590 i.rex |= REX_X;
29b0f896
AM		 4591 }
4592 }
4593 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4594 else if (i.base_reg->reg_num == RegRip ||
4595 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4596 {
4597 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4598 i.types[op].bitfield.disp8 = 0;
4599 i.types[op].bitfield.disp16 = 0;
4600 i.types[op].bitfield.disp32 = 0;
4601 i.types[op].bitfield.disp32s = 1;
4602 i.types[op].bitfield.disp64 = 0;
71903a11 4603 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4604 if (! i.disp_operands)
4605 fake_zero_displacement = 1;
29b0f896 4606 }
40fb9820 4607 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4608 {
4609 switch (i.base_reg->reg_num)
4610 {
4611 case 3: /* (%bx) */
4612 if (i.index_reg == 0)
4613 i.rm.regmem = 7;
4614 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4615 i.rm.regmem = i.index_reg->reg_num - 6;
4616 break;
4617 case 5: /* (%bp) */
4618 default_seg = &ss;
4619 if (i.index_reg == 0)
4620 {
4621 i.rm.regmem = 6;
40fb9820 4622 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4623 {
4624 /* fake (%bp) into 0(%bp) */
40fb9820 4625 i.types[op].bitfield.disp8 = 1;
252b5132 4626 fake_zero_displacement = 1;
29b0f896
AM		 4627 }
4628 }
4629 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4630 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4631 break;
4632 default: /* (%si) -> 4 or (%di) -> 5 */
4633 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4634 }
4635 i.rm.mode = mode_from_disp_size (i.types[op]);
4636 }
4637 else /* i.base_reg and 32/64 bit mode */
4638 {
4639 if (flag_code == CODE_64BIT
40fb9820
L		 4640 && operand_type_check (i.types[op], disp))
4641 {
4642 i386_operand_type temp;
c6fb90c8 4643 UINTS_CLEAR (temp);
40fb9820
L		 4644 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4645 i.types[op] = temp;
4646 if (i.prefix[ADDR_PREFIX] == 0)
4647 i.types[op].bitfield.disp32s = 1;
4648 else
4649 i.types[op].bitfield.disp32 = 1;
4650 }
20f0a1fc 4651
29b0f896
AM		 4652 i.rm.regmem = i.base_reg->reg_num;
4653 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4654 i.rex |= REX_B;
29b0f896
AM		 4655 i.sib.base = i.base_reg->reg_num;
4656 /* x86-64 ignores REX prefix bit here to avoid decoder
4657 complications. */
4658 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4659 {
4660 default_seg = &ss;
4661 if (i.disp_operands == 0)
4662 {
4663 fake_zero_displacement = 1;
40fb9820 4664 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4665 }
4666 }
4667 else if (i.base_reg->reg_num == ESP_REG_NUM)
4668 {
4669 default_seg = &ss;
4670 }
4671 i.sib.scale = i.log2_scale_factor;
4672 if (i.index_reg == 0)
4673 {
4674 /* <disp>(%esp) becomes two byte modrm with no index
4675 register. We've already stored the code for esp
4676 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4677 Any base register besides %esp will not use the
4678 extra modrm byte. */
4679 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4680 }
4681 else
4682 {
db51cc60
L		 4683 if (i.index_reg->reg_num == RegEiz
4684 || i.index_reg->reg_num == RegRiz)
4685 i.sib.index = NO_INDEX_REGISTER;
4686 else
4687 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4688 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4689 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4690 i.rex |= REX_X;
29b0f896 4691 }
67a4f2b7
AO		 4692
4693 if (i.disp_operands
4694 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4695 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4696 i.rm.mode = 0;
4697 else
4698 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4699 }
252b5132 4700
29b0f896
AM		 4701 if (fake_zero_displacement)
4702 {
4703 /* Fakes a zero displacement assuming that i.types[op]
4704 holds the correct displacement size. */
4705 expressionS *exp;
4706
4707 assert (i.op[op].disps == 0);
4708 exp = &disp_expressions[i.disp_operands++];
4709 i.op[op].disps = exp;
4710 exp->X_op = O_constant;
4711 exp->X_add_number = 0;
4712 exp->X_add_symbol = (symbolS *) 0;
4713 exp->X_op_symbol = (symbolS *) 0;
4714 }
4715 }
252b5132 4716
29b0f896
AM		 4717 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4718 (if any) based on i.tm.extension_opcode. Again, we must be
4719 careful to make sure that segment/control/debug/test/MMX
4720 registers are coded into the i.rm.reg field. */
4721 if (i.reg_operands)
4722 {
99018f42
L		 4723 unsigned int op;
4724
85f10a01
MM		 4725 /* This has been precalculated for SSE5 instructions
4726 that have a DREX field earlier in process_drex. */
b5016f89
L		 4727 if (i.tm.opcode_modifier.drex
4728 || i.tm.opcode_modifier.drexv
4729 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4730 {
4731 op = i.drex.modrm_reg;
4732 i.rm.reg = i.op[op].regs->reg_num;
4733 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4734 i.rex |= REX_R;
4735 }
4736 else
4737 {
c0209578
L		 4738 for (op = 0; op < i.operands; op++)
4739 if (i.types[op].bitfield.reg8
4740 || i.types[op].bitfield.reg16
4741 || i.types[op].bitfield.reg32
4742 || i.types[op].bitfield.reg64
4743 || i.types[op].bitfield.regmmx
4744 || i.types[op].bitfield.regxmm
4745 || i.types[op].bitfield.sreg2
4746 || i.types[op].bitfield.sreg3
4747 || i.types[op].bitfield.control
4748 || i.types[op].bitfield.debug
4749 || i.types[op].bitfield.test)
4750 break;
4751
4752 assert (op < i.operands);
99018f42 4753
85f10a01
MM		 4754 /* If there is an extension opcode to put here, the
4755 register number must be put into the regmem field. */
c0209578
L		 4756 if (i.tm.extension_opcode != None)
4757 {
4758 i.rm.regmem = i.op[op].regs->reg_num;
4759 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4760 i.rex |= REX_B;
4761 }
4762 else
4763 {
4764 i.rm.reg = i.op[op].regs->reg_num;
4765 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4766 i.rex |= REX_R;
4767 }
85f10a01 4768 }
252b5132 4769
29b0f896
AM		 4770 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4771 must set it to 3 to indicate this is a register operand
4772 in the regmem field. */
4773 if (!i.mem_operands)
4774 i.rm.mode = 3;
4775 }
252b5132 4776
29b0f896 4777 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4778 if (i.tm.extension_opcode != None
4779 && !(i.tm.opcode_modifier.drex
4780 || i.tm.opcode_modifier.drexv
4781 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4782 i.rm.reg = i.tm.extension_opcode;
4783 }
4784 return default_seg;
4785}
252b5132 4786
29b0f896 4787static void
e3bb37b5 4788output_branch (void)
29b0f896
AM		 4789{
4790 char *p;
4791 int code16;
4792 int prefix;
4793 relax_substateT subtype;
4794 symbolS *sym;
4795 offsetT off;
4796
4797 code16 = 0;
4798 if (flag_code == CODE_16BIT)
4799 code16 = CODE16;
4800
4801 prefix = 0;
4802 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4803 {
29b0f896
AM		 4804 prefix = 1;
4805 i.prefixes -= 1;
4806 code16 ^= CODE16;
252b5132 4807 }
29b0f896
AM		 4808 /* Pentium4 branch hints. */
4809 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4810 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4811 {
29b0f896
AM		 4812 prefix++;
4813 i.prefixes--;
4814 }
4815 if (i.prefix[REX_PREFIX] != 0)
4816 {
4817 prefix++;
4818 i.prefixes--;
2f66722d
AM		 4819 }
4820
29b0f896
AM		 4821 if (i.prefixes != 0 && !intel_syntax)
4822 as_warn (_("skipping prefixes on this instruction"));
4823
4824 /* It's always a symbol; End frag & setup for relax.
4825 Make sure there is enough room in this frag for the largest
4826 instruction we may generate in md_convert_frag. This is 2
4827 bytes for the opcode and room for the prefix and largest
4828 displacement. */
4829 frag_grow (prefix + 2 + 4);
4830 /* Prefix and 1 opcode byte go in fr_fix. */
4831 p = frag_more (prefix + 1);
4832 if (i.prefix[DATA_PREFIX] != 0)
4833 *p++ = DATA_PREFIX_OPCODE;
4834 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4835 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4836 *p++ = i.prefix[SEG_PREFIX];
4837 if (i.prefix[REX_PREFIX] != 0)
4838 *p++ = i.prefix[REX_PREFIX];
4839 *p = i.tm.base_opcode;
4840
4841 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4842 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4843 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4844 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4845 else
4846 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4847 subtype |= code16;
3e73aa7c 4848
29b0f896
AM		 4849 sym = i.op[0].disps->X_add_symbol;
4850 off = i.op[0].disps->X_add_number;
3e73aa7c 4851
29b0f896
AM		 4852 if (i.op[0].disps->X_op != O_constant
4853 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4854 {
29b0f896
AM		 4855 /* Handle complex expressions. */
4856 sym = make_expr_symbol (i.op[0].disps);
4857 off = 0;
4858 }
3e73aa7c 4859
29b0f896
AM		 4860 /* 1 possible extra opcode + 4 byte displacement go in var part.
4861 Pass reloc in fr_var. */
4862 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4863}
3e73aa7c 4864
29b0f896 4865static void
e3bb37b5 4866output_jump (void)
29b0f896
AM		 4867{
4868 char *p;
4869 int size;
3e02c1cc 4870 fixS *fixP;
29b0f896 4871
40fb9820 4872 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4873 {
4874 /* This is a loop or jecxz type instruction. */
4875 size = 1;
4876 if (i.prefix[ADDR_PREFIX] != 0)
4877 {
4878 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4879 i.prefixes -= 1;
4880 }
4881 /* Pentium4 branch hints. */
4882 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4883 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4884 {
4885 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4886 i.prefixes--;
3e73aa7c
JH		 4887 }
4888 }
29b0f896
AM		 4889 else
4890 {
4891 int code16;
3e73aa7c 4892
29b0f896
AM		 4893 code16 = 0;
4894 if (flag_code == CODE_16BIT)
4895 code16 = CODE16;
3e73aa7c 4896
29b0f896
AM		 4897 if (i.prefix[DATA_PREFIX] != 0)
4898 {
4899 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4900 i.prefixes -= 1;
4901 code16 ^= CODE16;
4902 }
252b5132 4903
29b0f896
AM		 4904 size = 4;
4905 if (code16)
4906 size = 2;
4907 }
9fcc94b6 4908
29b0f896
AM		 4909 if (i.prefix[REX_PREFIX] != 0)
4910 {
4911 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4912 i.prefixes -= 1;
4913 }
252b5132 4914
29b0f896
AM		 4915 if (i.prefixes != 0 && !intel_syntax)
4916 as_warn (_("skipping prefixes on this instruction"));
e0890092 4917
29b0f896
AM		 4918 p = frag_more (1 + size);
4919 *p++ = i.tm.base_opcode;
e0890092 4920
3e02c1cc
AM		 4921 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4922 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4923
4924 /* All jumps handled here are signed, but don't use a signed limit
4925 check for 32 and 16 bit jumps as we want to allow wrap around at
4926 4G and 64k respectively. */
4927 if (size == 1)
4928 fixP->fx_signed = 1;
29b0f896 4929}
e0890092 4930
29b0f896 4931static void
e3bb37b5 4932output_interseg_jump (void)
29b0f896
AM		 4933{
4934 char *p;
4935 int size;
4936 int prefix;
4937 int code16;
252b5132 4938
29b0f896
AM		 4939 code16 = 0;
4940 if (flag_code == CODE_16BIT)
4941 code16 = CODE16;
a217f122 4942
29b0f896
AM		 4943 prefix = 0;
4944 if (i.prefix[DATA_PREFIX] != 0)
4945 {
4946 prefix = 1;
4947 i.prefixes -= 1;
4948 code16 ^= CODE16;
4949 }
4950 if (i.prefix[REX_PREFIX] != 0)
4951 {
4952 prefix++;
4953 i.prefixes -= 1;
4954 }
252b5132 4955
29b0f896
AM		 4956 size = 4;
4957 if (code16)
4958 size = 2;
252b5132 4959
29b0f896
AM		 4960 if (i.prefixes != 0 && !intel_syntax)
4961 as_warn (_("skipping prefixes on this instruction"));
252b5132 4962
29b0f896
AM		 4963 /* 1 opcode; 2 segment; offset */
4964 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4965
29b0f896
AM		 4966 if (i.prefix[DATA_PREFIX] != 0)
4967 *p++ = DATA_PREFIX_OPCODE;
252b5132 4968
29b0f896
AM		 4969 if (i.prefix[REX_PREFIX] != 0)
4970 *p++ = i.prefix[REX_PREFIX];
252b5132 4971
29b0f896
AM		 4972 *p++ = i.tm.base_opcode;
4973 if (i.op[1].imms->X_op == O_constant)
4974 {
4975 offsetT n = i.op[1].imms->X_add_number;
252b5132 4976
29b0f896
AM		 4977 if (size == 2
4978 && !fits_in_unsigned_word (n)
4979 && !fits_in_signed_word (n))
4980 {
4981 as_bad (_("16-bit jump out of range"));
4982 return;
4983 }
4984 md_number_to_chars (p, n, size);
4985 }
4986 else
4987 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4988 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4989 if (i.op[0].imms->X_op != O_constant)
4990 as_bad (_("can't handle non absolute segment in `%s'"),
4991 i.tm.name);
4992 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4993}
a217f122 4994
29b0f896 4995static void
e3bb37b5 4996output_insn (void)
29b0f896 4997{
2bbd9c25
JJ		 4998 fragS *insn_start_frag;
4999 offsetT insn_start_off;
5000
29b0f896
AM		 5001 /* Tie dwarf2 debug info to the address at the start of the insn.
5002 We can't do this after the insn has been output as the current
5003 frag may have been closed off. eg. by frag_var. */
5004 dwarf2_emit_insn (0);
5005
2bbd9c25
JJ		 5006 insn_start_frag = frag_now;
5007 insn_start_off = frag_now_fix ();
5008
29b0f896 5009 /* Output jumps. */
40fb9820 5010 if (i.tm.opcode_modifier.jump)
29b0f896 5011 output_branch ();
40fb9820
L		 5012 else if (i.tm.opcode_modifier.jumpbyte
5013 || i.tm.opcode_modifier.jumpdword)
29b0f896 5014 output_jump ();
40fb9820 5015 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5016 output_interseg_jump ();
5017 else
5018 {
5019 /* Output normal instructions here. */
5020 char *p;
5021 unsigned char *q;
47465058 5022 unsigned int j;
331d2d0d 5023 unsigned int prefix;
4dffcebc
L		 5024
5025 switch (i.tm.opcode_length)
bc4bd9ab 5026 {
4dffcebc 5027 case 3:
331d2d0d
L		 5028 if (i.tm.base_opcode & 0xff000000)
5029 {
5030 prefix = (i.tm.base_opcode >> 24) & 0xff;
5031 goto check_prefix;
5032 }
4dffcebc
L		 5033 break;
5034 case 2:
5035 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5036 {
4dffcebc
L		 5037 prefix = (i.tm.base_opcode >> 16) & 0xff;
5038 if (i.tm.cpu_flags.bitfield.cpupadlock)
5039 {
5040check_prefix:
5041 if (prefix != REPE_PREFIX_OPCODE
5042 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5043 add_prefix (prefix);
5044 }
5045 else
bc4bd9ab
MK		 5046 add_prefix (prefix);
5047 }
4dffcebc
L		 5048 break;
5049 case 1:
5050 break;
5051 default:
5052 abort ();
0f10071e 5053 }
252b5132 5054
29b0f896 5055 /* The prefix bytes. */
47465058
L		 5056 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5057 if (*q)
5058 FRAG_APPEND_1_CHAR (*q);
252b5132 5059
29b0f896 5060 /* Now the opcode; be careful about word order here! */
4dffcebc 5061 if (i.tm.opcode_length == 1)
29b0f896
AM		 5062 {
5063 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5064 }
5065 else
5066 {
4dffcebc 5067 switch (i.tm.opcode_length)
331d2d0d 5068 {
4dffcebc 5069 case 3:
331d2d0d
L		 5070 p = frag_more (3);
5071 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5072 break;
5073 case 2:
5074 p = frag_more (2);
5075 break;
5076 default:
5077 abort ();
5078 break;
331d2d0d 5079 }
0f10071e 5080
29b0f896
AM		 5081 /* Put out high byte first: can't use md_number_to_chars! */
5082 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5083 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5084
5085 /* On SSE5, encode the OC1 bit in the DREX field if this
5086 encoding has multiple formats. */
5087 if (i.tm.opcode_modifier.drex
5088 && i.tm.opcode_modifier.drexv
5089 && DREX_OC1 (i.tm.extension_opcode))
5090 *p |= DREX_OC1_MASK;
29b0f896 5091 }
3e73aa7c 5092
29b0f896 5093 /* Now the modrm byte and sib byte (if present). */
40fb9820 5094 if (i.tm.opcode_modifier.modrm)
29b0f896 5095 {
4a3523fa
L		 5096 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5097 | i.rm.reg << 3
5098 | i.rm.mode << 6));
29b0f896
AM		 5099 /* If i.rm.regmem == ESP (4)
5100 && i.rm.mode != (Register mode)
5101 && not 16 bit
5102 ==> need second modrm byte. */
5103 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5104 && i.rm.mode != 3
40fb9820 5105 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5106 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5107 | i.sib.index << 3
5108 | i.sib.scale << 6));
29b0f896 5109 }
3e73aa7c 5110
85f10a01
MM		 5111 /* Write the DREX byte if needed. */
5112 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5113 {
5114 p = frag_more (1);
5115 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5116
5117 /* Encode the OC0 bit if this encoding has multiple
5118 formats. */
5119 if ((i.tm.opcode_modifier.drex
5120 || i.tm.opcode_modifier.drexv)
5121 && DREX_OC0 (i.tm.extension_opcode))
5122 *p |= DREX_OC0_MASK;
5123 }
5124
29b0f896 5125 if (i.disp_operands)
2bbd9c25 5126 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5127
29b0f896 5128 if (i.imm_operands)
2bbd9c25 5129 output_imm (insn_start_frag, insn_start_off);
29b0f896 5130 }
252b5132 5131
29b0f896
AM		 5132#ifdef DEBUG386
5133 if (flag_debug)
5134 {
7b81dfbb 5135 pi ("" /*line*/, &i);
29b0f896
AM		 5136 }
5137#endif /* DEBUG386 */
5138}
252b5132 5139
e205caa7
L		 5140/* Return the size of the displacement operand N. */
5141
5142static int
5143disp_size (unsigned int n)
5144{
5145 int size = 4;
40fb9820
L		 5146 if (i.types[n].bitfield.disp64)
5147 size = 8;
5148 else if (i.types[n].bitfield.disp8)
5149 size = 1;
5150 else if (i.types[n].bitfield.disp16)
5151 size = 2;
e205caa7
L		 5152 return size;
5153}
5154
5155/* Return the size of the immediate operand N. */
5156
5157static int
5158imm_size (unsigned int n)
5159{
5160 int size = 4;
40fb9820
L		 5161 if (i.types[n].bitfield.imm64)
5162 size = 8;
5163 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5164 size = 1;
5165 else if (i.types[n].bitfield.imm16)
5166 size = 2;
e205caa7
L		 5167 return size;
5168}
5169
29b0f896 5170static void
64e74474 5171output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5172{
5173 char *p;
5174 unsigned int n;
252b5132 5175
29b0f896
AM		 5176 for (n = 0; n < i.operands; n++)
5177 {
40fb9820 5178 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5179 {
5180 if (i.op[n].disps->X_op == O_constant)
5181 {
e205caa7 5182 int size = disp_size (n);
29b0f896 5183 offsetT val;
252b5132 5184
29b0f896
AM		 5185 val = offset_in_range (i.op[n].disps->X_add_number,
5186 size);
5187 p = frag_more (size);
5188 md_number_to_chars (p, val, size);
5189 }
5190 else
5191 {
f86103b7 5192 enum bfd_reloc_code_real reloc_type;
e205caa7 5193 int size = disp_size (n);
40fb9820 5194 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5195 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5196
e205caa7 5197 /* We can't have 8 bit displacement here. */
40fb9820 5198 assert (!i.types[n].bitfield.disp8);
e205caa7 5199
29b0f896
AM		 5200 /* The PC relative address is computed relative
5201 to the instruction boundary, so in case immediate
5202 fields follows, we need to adjust the value. */
5203 if (pcrel && i.imm_operands)
5204 {
29b0f896 5205 unsigned int n1;
e205caa7 5206 int sz = 0;
252b5132 5207
29b0f896 5208 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5209 if (operand_type_check (i.types[n1], imm))
252b5132 5210 {
e205caa7
L		 5211 /* Only one immediate is allowed for PC
5212 relative address. */
5213 assert (sz == 0);
5214 sz = imm_size (n1);
5215 i.op[n].disps->X_add_number -= sz;
252b5132 5216 }
29b0f896 5217 /* We should find the immediate. */
e205caa7 5218 assert (sz != 0);
29b0f896 5219 }
520dc8e8 5220
29b0f896 5221 p = frag_more (size);
2bbd9c25 5222 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5223 if (GOT_symbol
2bbd9c25 5224 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5225 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5226 || reloc_type == BFD_RELOC_X86_64_32S
5227 || (reloc_type == BFD_RELOC_64
5228 && object_64bit))
d6ab8113
JB		 5229 && (i.op[n].disps->X_op == O_symbol
5230 || (i.op[n].disps->X_op == O_add
5231 && ((symbol_get_value_expression
5232 (i.op[n].disps->X_op_symbol)->X_op)
5233 == O_subtract))))
5234 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5235 {
5236 offsetT add;
5237
5238 if (insn_start_frag == frag_now)
5239 add = (p - frag_now->fr_literal) - insn_start_off;
5240 else
5241 {
5242 fragS *fr;
5243
5244 add = insn_start_frag->fr_fix - insn_start_off;
5245 for (fr = insn_start_frag->fr_next;
5246 fr && fr != frag_now; fr = fr->fr_next)
5247 add += fr->fr_fix;
5248 add += p - frag_now->fr_literal;
5249 }
5250
4fa24527 5251 if (!object_64bit)
7b81dfbb
AJ		 5252 {
5253 reloc_type = BFD_RELOC_386_GOTPC;
5254 i.op[n].imms->X_add_number += add;
5255 }
5256 else if (reloc_type == BFD_RELOC_64)
5257 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5258 else
7b81dfbb
AJ		 5259 /* Don't do the adjustment for x86-64, as there
5260 the pcrel addressing is relative to the _next_
5261 insn, and that is taken care of in other code. */
d6ab8113 5262 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5263 }
062cd5e7 5264 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5265 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5266 }
5267 }
5268 }
5269}
252b5132 5270
29b0f896 5271static void
64e74474 5272output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5273{
5274 char *p;
5275 unsigned int n;
252b5132 5276
29b0f896
AM		 5277 for (n = 0; n < i.operands; n++)
5278 {
40fb9820 5279 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5280 {
5281 if (i.op[n].imms->X_op == O_constant)
5282 {
e205caa7 5283 int size = imm_size (n);
29b0f896 5284 offsetT val;
b4cac588 5285
29b0f896
AM		 5286 val = offset_in_range (i.op[n].imms->X_add_number,
5287 size);
5288 p = frag_more (size);
5289 md_number_to_chars (p, val, size);
5290 }
5291 else
5292 {
5293 /* Not absolute_section.
5294 Need a 32-bit fixup (don't support 8bit
5295 non-absolute imms). Try to support other
5296 sizes ... */
f86103b7 5297 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5298 int size = imm_size (n);
5299 int sign;
29b0f896 5300
40fb9820 5301 if (i.types[n].bitfield.imm32s
a7d61044 5302 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5303 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5304 sign = 1;
e205caa7
L		 5305 else
5306 sign = 0;
520dc8e8 5307
29b0f896
AM		 5308 p = frag_more (size);
5309 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5310
2bbd9c25
JJ		 5311 /* This is tough to explain. We end up with this one if we
5312 * have operands that look like
5313 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5314 * obtain the absolute address of the GOT, and it is strongly
5315 * preferable from a performance point of view to avoid using
5316 * a runtime relocation for this. The actual sequence of
5317 * instructions often look something like:
5318 *
5319 * call .L66
5320 * .L66:
5321 * popl %ebx
5322 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5323 *
5324 * The call and pop essentially return the absolute address
5325 * of the label .L66 and store it in %ebx. The linker itself
5326 * will ultimately change the first operand of the addl so
5327 * that %ebx points to the GOT, but to keep things simple, the
5328 * .o file must have this operand set so that it generates not
5329 * the absolute address of .L66, but the absolute address of
5330 * itself. This allows the linker itself simply treat a GOTPC
5331 * relocation as asking for a pcrel offset to the GOT to be
5332 * added in, and the addend of the relocation is stored in the
5333 * operand field for the instruction itself.
5334 *
5335 * Our job here is to fix the operand so that it would add
5336 * the correct offset so that %ebx would point to itself. The
5337 * thing that is tricky is that .-.L66 will point to the
5338 * beginning of the instruction, so we need to further modify
5339 * the operand so that it will point to itself. There are
5340 * other cases where you have something like:
5341 *
5342 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5343 *
5344 * and here no correction would be required. Internally in
5345 * the assembler we treat operands of this form as not being
5346 * pcrel since the '.' is explicitly mentioned, and I wonder
5347 * whether it would simplify matters to do it this way. Who
5348 * knows. In earlier versions of the PIC patches, the
5349 * pcrel_adjust field was used to store the correction, but
5350 * since the expression is not pcrel, I felt it would be
5351 * confusing to do it this way. */
5352
d6ab8113 5353 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5354 || reloc_type == BFD_RELOC_X86_64_32S
5355 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5356 && GOT_symbol
5357 && GOT_symbol == i.op[n].imms->X_add_symbol
5358 && (i.op[n].imms->X_op == O_symbol
5359 || (i.op[n].imms->X_op == O_add
5360 && ((symbol_get_value_expression
5361 (i.op[n].imms->X_op_symbol)->X_op)
5362 == O_subtract))))
5363 {
2bbd9c25
JJ		 5364 offsetT add;
5365
5366 if (insn_start_frag == frag_now)
5367 add = (p - frag_now->fr_literal) - insn_start_off;
5368 else
5369 {
5370 fragS *fr;
5371
5372 add = insn_start_frag->fr_fix - insn_start_off;
5373 for (fr = insn_start_frag->fr_next;
5374 fr && fr != frag_now; fr = fr->fr_next)
5375 add += fr->fr_fix;
5376 add += p - frag_now->fr_literal;
5377 }
5378
4fa24527 5379 if (!object_64bit)
d6ab8113 5380 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5381 else if (size == 4)
d6ab8113 5382 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5383 else if (size == 8)
5384 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5385 i.op[n].imms->X_add_number += add;
29b0f896 5386 }
29b0f896
AM		 5387 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5388 i.op[n].imms, 0, reloc_type);
5389 }
5390 }
5391 }
252b5132
RH		 5392}
5393\f
d182319b
JB		 5394/* x86_cons_fix_new is called via the expression parsing code when a
5395 reloc is needed. We use this hook to get the correct .got reloc. */
5396static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5397static int cons_sign = -1;
5398
5399void
e3bb37b5 5400x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5401 expressionS *exp)
d182319b
JB		 5402{
5403 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5404
5405 got_reloc = NO_RELOC;
5406
5407#ifdef TE_PE
5408 if (exp->X_op == O_secrel)
5409 {
5410 exp->X_op = O_symbol;
5411 r = BFD_RELOC_32_SECREL;
5412 }
5413#endif
5414
5415 fix_new_exp (frag, off, len, exp, 0, r);
5416}
5417
718ddfc0
JB		 5418#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5419# define lex_got(reloc, adjust, types) NULL
5420#else
f3c180ae
AM		 5421/* Parse operands of the form
5422 <symbol>@GOTOFF+<nnn>
5423 and similar .plt or .got references.
5424
5425 If we find one, set up the correct relocation in RELOC and copy the
5426 input string, minus the `@GOTOFF' into a malloc'd buffer for
5427 parsing by the calling routine. Return this buffer, and if ADJUST
5428 is non-null set it to the length of the string we removed from the
5429 input line. Otherwise return NULL. */
5430static char *
3956db08 5431lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5432 int *adjust,
40fb9820 5433 i386_operand_type *types)
f3c180ae 5434{
7b81dfbb
AJ		 5435 /* Some of the relocations depend on the size of what field is to
5436 be relocated. But in our callers i386_immediate and i386_displacement
5437 we don't yet know the operand size (this will be set by insn
5438 matching). Hence we record the word32 relocation here,
5439 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5440 static const struct {
5441 const char *str;
4fa24527 5442 const enum bfd_reloc_code_real rel[2];
40fb9820 5443 const i386_operand_type types64;
f3c180ae 5444 } gotrel[] = {
4eed87de
AM		 5445 { "PLTOFF", { 0,
5446 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5447 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5448 { "PLT", { BFD_RELOC_386_PLT32,
5449 BFD_RELOC_X86_64_PLT32 },
40fb9820 5450 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5451 { "GOTPLT", { 0,
5452 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5453 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5454 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5455 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5456 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5457 { "GOTPCREL", { 0,
5458 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5459 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5460 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5461 BFD_RELOC_X86_64_TLSGD },
40fb9820 5462 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5463 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5464 0 },
40fb9820 5465 OPERAND_TYPE_NONE },
4eed87de
AM		 5466 { "TLSLD", { 0,
5467 BFD_RELOC_X86_64_TLSLD },
40fb9820 5468 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5469 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5470 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5471 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5472 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5473 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5474 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5475 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5476 0 },
40fb9820 5477 OPERAND_TYPE_NONE },
4eed87de
AM		 5478 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5479 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5480
5481 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5482 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5483 0 },
40fb9820 5484 OPERAND_TYPE_NONE },
4eed87de
AM		 5485 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5486 0 },
40fb9820 5487 OPERAND_TYPE_NONE },
4eed87de
AM		 5488 { "GOT", { BFD_RELOC_386_GOT32,
5489 BFD_RELOC_X86_64_GOT32 },
40fb9820 5490 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5491 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5492 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5493 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5494 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5495 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5496 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5497 };
5498 char *cp;
5499 unsigned int j;
5500
718ddfc0
JB		 5501 if (!IS_ELF)
5502 return NULL;
5503
f3c180ae 5504 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5505 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5506 return NULL;
5507
47465058 5508 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5509 {
5510 int len;
5511
5512 len = strlen (gotrel[j].str);
28f81592 5513 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5514 {
4fa24527 5515 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5516 {
28f81592
AM		 5517 int first, second;
5518 char *tmpbuf, *past_reloc;
f3c180ae 5519
4fa24527 5520 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5521 if (adjust)
5522 *adjust = len;
f3c180ae 5523
3956db08
JB		 5524 if (types)
5525 {
5526 if (flag_code != CODE_64BIT)
40fb9820
L		 5527 {
5528 types->bitfield.imm32 = 1;
5529 types->bitfield.disp32 = 1;
5530 }
3956db08
JB		 5531 else
5532 *types = gotrel[j].types64;
5533 }
5534
f3c180ae
AM		 5535 if (GOT_symbol == NULL)
5536 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5537
28f81592 5538 /* The length of the first part of our input line. */
f3c180ae 5539 first = cp - input_line_pointer;
28f81592
AM		 5540
5541 /* The second part goes from after the reloc token until
67c11a9b 5542 (and including) an end_of_line char or comma. */
28f81592 5543 past_reloc = cp + 1 + len;
67c11a9b
AM		 5544 cp = past_reloc;
5545 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5546 ++cp;
5547 second = cp + 1 - past_reloc;
28f81592
AM		 5548
5549 /* Allocate and copy string. The trailing NUL shouldn't
5550 be necessary, but be safe. */
5551 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5552 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5553 if (second != 0 && *past_reloc != ' ')
5554 /* Replace the relocation token with ' ', so that
5555 errors like foo@GOTOFF1 will be detected. */
5556 tmpbuf[first++] = ' ';
5557 memcpy (tmpbuf + first, past_reloc, second);
5558 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5559 return tmpbuf;
5560 }
5561
4fa24527
JB		 5562 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5563 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5564 return NULL;
5565 }
5566 }
5567
5568 /* Might be a symbol version string. Don't as_bad here. */
5569 return NULL;
5570}
5571
f3c180ae 5572void
e3bb37b5 5573x86_cons (expressionS *exp, int size)
f3c180ae 5574{
4fa24527 5575 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5576 {
5577 /* Handle @GOTOFF and the like in an expression. */
5578 char *save;
5579 char *gotfree_input_line;
5580 int adjust;
5581
5582 save = input_line_pointer;
3956db08 5583 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5584 if (gotfree_input_line)
5585 input_line_pointer = gotfree_input_line;
5586
5587 expression (exp);
5588
5589 if (gotfree_input_line)
5590 {
5591 /* expression () has merrily parsed up to the end of line,
5592 or a comma - in the wrong buffer. Transfer how far
5593 input_line_pointer has moved to the right buffer. */
5594 input_line_pointer = (save
5595 + (input_line_pointer - gotfree_input_line)
5596 + adjust);
5597 free (gotfree_input_line);
3992d3b7
AM		 5598 if (exp->X_op == O_constant
5599 || exp->X_op == O_absent
5600 || exp->X_op == O_illegal
5601 || exp->X_op == O_register
5602 || exp->X_op == O_big)
5603 {
5604 char c = *input_line_pointer;
5605 *input_line_pointer = 0;
5606 as_bad (_("missing or invalid expression `%s'"), save);
5607 *input_line_pointer = c;
5608 }
f3c180ae
AM		 5609 }
5610 }
5611 else
5612 expression (exp);
5613}
5614#endif
5615
d182319b 5616static void signed_cons (int size)
6482c264 5617{
d182319b
JB		 5618 if (flag_code == CODE_64BIT)
5619 cons_sign = 1;
5620 cons (size);
5621 cons_sign = -1;
6482c264
NC		 5622}
5623
d182319b 5624#ifdef TE_PE
6482c264
NC		 5625static void
5626pe_directive_secrel (dummy)
5627 int dummy ATTRIBUTE_UNUSED;
5628{
5629 expressionS exp;
5630
5631 do
5632 {
5633 expression (&exp);
5634 if (exp.X_op == O_symbol)
5635 exp.X_op = O_secrel;
5636
5637 emit_expr (&exp, 4);
5638 }
5639 while (*input_line_pointer++ == ',');
5640
5641 input_line_pointer--;
5642 demand_empty_rest_of_line ();
5643}
6482c264
NC		 5644#endif
5645
252b5132 5646static int
70e41ade 5647i386_immediate (char *imm_start)
252b5132
RH		 5648{
5649 char *save_input_line_pointer;
f3c180ae 5650 char *gotfree_input_line;
252b5132 5651 segT exp_seg = 0;
47926f60 5652 expressionS *exp;
40fb9820
L		 5653 i386_operand_type types;
5654
c6fb90c8 5655 UINTS_SET (types, ~0);
252b5132
RH		 5656
5657 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5658 {
31b2323c
L		 5659 as_bad (_("at most %d immediate operands are allowed"),
5660 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5661 return 0;
5662 }
5663
5664 exp = &im_expressions[i.imm_operands++];
520dc8e8 5665 i.op[this_operand].imms = exp;
252b5132
RH		 5666
5667 if (is_space_char (*imm_start))
5668 ++imm_start;
5669
5670 save_input_line_pointer = input_line_pointer;
5671 input_line_pointer = imm_start;
5672
3956db08 5673 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5674 if (gotfree_input_line)
5675 input_line_pointer = gotfree_input_line;
252b5132
RH		 5676
5677 exp_seg = expression (exp);
5678
83183c0c 5679 SKIP_WHITESPACE ();
252b5132 5680 if (*input_line_pointer)
f3c180ae 5681 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5682
5683 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5684 if (gotfree_input_line)
5685 free (gotfree_input_line);
252b5132 5686
3992d3b7
AM		 5687 if (exp->X_op == O_absent
5688 || exp->X_op == O_illegal
5689 || exp->X_op == O_big
5690 || (gotfree_input_line
5691 && (exp->X_op == O_constant
5692 || exp->X_op == O_register)))
252b5132 5693 {
3992d3b7 5694 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5695 imm_start);
3992d3b7 5696 return 0;
252b5132 5697 }
3e73aa7c 5698 else if (exp->X_op == O_constant)
252b5132 5699 {
47926f60 5700 /* Size it properly later. */
40fb9820 5701 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5702 /* If BFD64, sign extend val. */
4eed87de
AM		 5703 if (!use_rela_relocations
5704 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5705 exp->X_add_number
5706 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5707 }
4c63da97 5708#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5709 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5710 && exp_seg != absolute_section
47926f60 5711 && exp_seg != text_section
24eab124
AM		 5712 && exp_seg != data_section
5713 && exp_seg != bss_section
5714 && exp_seg != undefined_section
f86103b7 5715 && !bfd_is_com_section (exp_seg))
252b5132 5716 {
d0b47220 5717 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5718 return 0;
5719 }
5720#endif
bb8f5920
L		 5721 else if (!intel_syntax && exp->X_op == O_register)
5722 {
5723 as_bad (_("illegal immediate register operand %s"), imm_start);
5724 return 0;
5725 }
252b5132
RH		 5726 else
5727 {
5728 /* This is an address. The size of the address will be
24eab124 5729 determined later, depending on destination register,
3e73aa7c 5730 suffix, or the default for the section. */
40fb9820
L		 5731 i.types[this_operand].bitfield.imm8 = 1;
5732 i.types[this_operand].bitfield.imm16 = 1;
5733 i.types[this_operand].bitfield.imm32 = 1;
5734 i.types[this_operand].bitfield.imm32s = 1;
5735 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5736 i.types[this_operand] = operand_type_and (i.types[this_operand],
5737 types);
252b5132
RH		 5738 }
5739
5740 return 1;
5741}
5742
551c1ca1 5743static char *
e3bb37b5 5744i386_scale (char *scale)
252b5132 5745{
551c1ca1
AM		 5746 offsetT val;
5747 char *save = input_line_pointer;
252b5132 5748
551c1ca1
AM		 5749 input_line_pointer = scale;
5750 val = get_absolute_expression ();
5751
5752 switch (val)
252b5132 5753 {
551c1ca1 5754 case 1:
252b5132
RH		 5755 i.log2_scale_factor = 0;
5756 break;
551c1ca1 5757 case 2:
252b5132
RH		 5758 i.log2_scale_factor = 1;
5759 break;
551c1ca1 5760 case 4:
252b5132
RH		 5761 i.log2_scale_factor = 2;
5762 break;
551c1ca1 5763 case 8:
252b5132
RH		 5764 i.log2_scale_factor = 3;
5765 break;
5766 default:
a724f0f4
JB		 5767 {
5768 char sep = *input_line_pointer;
5769
5770 *input_line_pointer = '\0';
5771 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5772 scale);
5773 *input_line_pointer = sep;
5774 input_line_pointer = save;
5775 return NULL;
5776 }
252b5132 5777 }
29b0f896 5778 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5779 {
5780 as_warn (_("scale factor of %d without an index register"),
24eab124 5781 1 << i.log2_scale_factor);
252b5132 5782 i.log2_scale_factor = 0;
252b5132 5783 }
551c1ca1
AM		 5784 scale = input_line_pointer;
5785 input_line_pointer = save;
5786 return scale;
252b5132
RH		 5787}
5788
252b5132 5789static int
e3bb37b5 5790i386_displacement (char *disp_start, char *disp_end)
252b5132 5791{
29b0f896 5792 expressionS *exp;
252b5132
RH		 5793 segT exp_seg = 0;
5794 char *save_input_line_pointer;
f3c180ae 5795 char *gotfree_input_line;
40fb9820
L		 5796 int override;
5797 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5798 int ret;
252b5132 5799
31b2323c
L		 5800 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5801 {
5802 as_bad (_("at most %d displacement operands are allowed"),
5803 MAX_MEMORY_OPERANDS);
5804 return 0;
5805 }
5806
c6fb90c8 5807 UINTS_CLEAR (bigdisp);
40fb9820
L		 5808 if ((i.types[this_operand].bitfield.jumpabsolute)
5809 || (!current_templates->start->opcode_modifier.jump
5810 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5811 {
40fb9820 5812 bigdisp.bitfield.disp32 = 1;
e05278af 5813 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5814 if (flag_code == CODE_64BIT)
5815 {
5816 if (!override)
5817 {
5818 bigdisp.bitfield.disp32s = 1;
5819 bigdisp.bitfield.disp64 = 1;
5820 }
5821 }
5822 else if ((flag_code == CODE_16BIT) ^ override)
5823 {
5824 bigdisp.bitfield.disp32 = 0;
5825 bigdisp.bitfield.disp16 = 1;
5826 }
e05278af
JB		 5827 }
5828 else
5829 {
5830 /* For PC-relative branches, the width of the displacement
5831 is dependent upon data size, not address size. */
e05278af 5832 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5833 if (flag_code == CODE_64BIT)
5834 {
5835 if (override || i.suffix == WORD_MNEM_SUFFIX)
5836 bigdisp.bitfield.disp16 = 1;
5837 else
5838 {
5839 bigdisp.bitfield.disp32 = 1;
5840 bigdisp.bitfield.disp32s = 1;
5841 }
5842 }
5843 else
e05278af
JB		 5844 {
5845 if (!override)
5846 override = (i.suffix == (flag_code != CODE_16BIT
5847 ? WORD_MNEM_SUFFIX
5848 : LONG_MNEM_SUFFIX));
40fb9820
L		 5849 bigdisp.bitfield.disp32 = 1;
5850 if ((flag_code == CODE_16BIT) ^ override)
5851 {
5852 bigdisp.bitfield.disp32 = 0;
5853 bigdisp.bitfield.disp16 = 1;
5854 }
e05278af 5855 }
e05278af 5856 }
c6fb90c8
L		 5857 i.types[this_operand] = operand_type_or (i.types[this_operand],
5858 bigdisp);
252b5132
RH		 5859
5860 exp = &disp_expressions[i.disp_operands];
520dc8e8 5861 i.op[this_operand].disps = exp;
252b5132
RH		 5862 i.disp_operands++;
5863 save_input_line_pointer = input_line_pointer;
5864 input_line_pointer = disp_start;
5865 END_STRING_AND_SAVE (disp_end);
5866
5867#ifndef GCC_ASM_O_HACK
5868#define GCC_ASM_O_HACK 0
5869#endif
5870#if GCC_ASM_O_HACK
5871 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5872 if (i.types[this_operand].bitfield.baseIndex
24eab124 5873 && displacement_string_end[-1] == '+')
252b5132
RH		 5874 {
5875 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5876 constraint within gcc asm statements.
5877 For instance:
5878
5879 #define _set_tssldt_desc(n,addr,limit,type) \
5880 __asm__ __volatile__ ( \
5881 "movw %w2,%0\n\t" \
5882 "movw %w1,2+%0\n\t" \
5883 "rorl $16,%1\n\t" \
5884 "movb %b1,4+%0\n\t" \
5885 "movb %4,5+%0\n\t" \
5886 "movb $0,6+%0\n\t" \
5887 "movb %h1,7+%0\n\t" \
5888 "rorl $16,%1" \
5889 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5890
5891 This works great except that the output assembler ends
5892 up looking a bit weird if it turns out that there is
5893 no offset. You end up producing code that looks like:
5894
5895 #APP
5896 movw $235,(%eax)
5897 movw %dx,2+(%eax)
5898 rorl $16,%edx
5899 movb %dl,4+(%eax)
5900 movb $137,5+(%eax)
5901 movb $0,6+(%eax)
5902 movb %dh,7+(%eax)
5903 rorl $16,%edx
5904 #NO_APP
5905
47926f60 5906 So here we provide the missing zero. */
24eab124
AM		 5907
5908 *displacement_string_end = '0';
252b5132
RH		 5909 }
5910#endif
3956db08 5911 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5912 if (gotfree_input_line)
5913 input_line_pointer = gotfree_input_line;
252b5132 5914
24eab124 5915 exp_seg = expression (exp);
252b5132 5916
636c26b0
AM		 5917 SKIP_WHITESPACE ();
5918 if (*input_line_pointer)
5919 as_bad (_("junk `%s' after expression"), input_line_pointer);
5920#if GCC_ASM_O_HACK
5921 RESTORE_END_STRING (disp_end + 1);
5922#endif
636c26b0 5923 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5924 if (gotfree_input_line)
5925 free (gotfree_input_line);
3992d3b7 5926 ret = 1;
636c26b0 5927
24eab124
AM		 5928 /* We do this to make sure that the section symbol is in
5929 the symbol table. We will ultimately change the relocation
47926f60 5930 to be relative to the beginning of the section. */
1ae12ab7 5931 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5932 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5933 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5934 {
636c26b0 5935 if (exp->X_op != O_symbol)
3992d3b7 5936 goto inv_disp;
636c26b0 5937
e5cb08ac 5938 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5939 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5940 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5941 exp->X_op = O_subtract;
5942 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5943 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5944 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5945 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5946 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5947 else
29b0f896 5948 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5949 }
252b5132 5950
3992d3b7
AM		 5951 else if (exp->X_op == O_absent
5952 || exp->X_op == O_illegal
5953 || exp->X_op == O_big
5954 || (gotfree_input_line
5955 && (exp->X_op == O_constant
5956 || exp->X_op == O_register)))
2daf4fd8 5957 {
3992d3b7
AM		 5958 inv_disp:
5959 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5960 disp_start);
3992d3b7 5961 ret = 0;
2daf4fd8
AM		 5962 }
5963
4c63da97 5964#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5965 else if (exp->X_op != O_constant
5966 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5967 && exp_seg != absolute_section
5968 && exp_seg != text_section
5969 && exp_seg != data_section
5970 && exp_seg != bss_section
5971 && exp_seg != undefined_section
5972 && !bfd_is_com_section (exp_seg))
24eab124 5973 {
d0b47220 5974 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5975 ret = 0;
24eab124 5976 }
252b5132 5977#endif
3956db08 5978
3992d3b7
AM		 5979 RESTORE_END_STRING (disp_end);
5980
40fb9820
L		 5981 /* Check if this is a displacement only operand. */
5982 bigdisp = i.types[this_operand];
5983 bigdisp.bitfield.disp8 = 0;
5984 bigdisp.bitfield.disp16 = 0;
5985 bigdisp.bitfield.disp32 = 0;
5986 bigdisp.bitfield.disp32s = 0;
5987 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5988 if (UINTS_ALL_ZERO (bigdisp))
5989 i.types[this_operand] = operand_type_and (i.types[this_operand],
5990 types);
3956db08 5991
3992d3b7 5992 return ret;
252b5132
RH		 5993}
5994
eecb386c 5995/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5996 Return 1 on success, 0 on a failure. */
5997
252b5132 5998static int
e3bb37b5 5999i386_index_check (const char *operand_string)
252b5132 6000{
3e73aa7c 6001 int ok;
24eab124 6002#if INFER_ADDR_PREFIX
eecb386c
AM		 6003 int fudged = 0;
6004
24eab124
AM		 6005 tryprefix:
6006#endif
3e73aa7c 6007 ok = 1;
75178d9d 6008 if (flag_code == CODE_64BIT)
64e74474 6009 {
64e74474 6010 if ((i.base_reg
40fb9820
L		 6011 && ((i.prefix[ADDR_PREFIX] == 0
6012 && !i.base_reg->reg_type.bitfield.reg64)
6013 || (i.prefix[ADDR_PREFIX]
6014 && !i.base_reg->reg_type.bitfield.reg32))
6015 && (i.index_reg
9a04903e
JB		 6016 || i.base_reg->reg_num !=
6017 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6018 || (i.index_reg
40fb9820
L		 6019 && (!i.index_reg->reg_type.bitfield.baseindex
6020 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6021 && i.index_reg->reg_num != RegRiz
6022 && !i.index_reg->reg_type.bitfield.reg64
6023 )
40fb9820 6024 || (i.prefix[ADDR_PREFIX]
db51cc60 6025 && i.index_reg->reg_num != RegEiz
40fb9820 6026 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6027 ok = 0;
3e73aa7c
JH		 6028 }
6029 else
6030 {
6031 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6032 {
6033 /* 16bit checks. */
6034 if ((i.base_reg
40fb9820
L		 6035 && (!i.base_reg->reg_type.bitfield.reg16
6036 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6037 || (i.index_reg
40fb9820
L		 6038 && (!i.index_reg->reg_type.bitfield.reg16
6039 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6040 || !(i.base_reg
6041 && i.base_reg->reg_num < 6
6042 && i.index_reg->reg_num >= 6
6043 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6044 ok = 0;
6045 }
6046 else
e5cb08ac 6047 {
3e73aa7c
JH		 6048 /* 32bit checks. */
6049 if ((i.base_reg
40fb9820 6050 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6051 || (i.index_reg
db51cc60
L		 6052 && ((!i.index_reg->reg_type.bitfield.reg32
6053 && i.index_reg->reg_num != RegEiz)
40fb9820 6054 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6055 ok = 0;
3e73aa7c
JH		 6056 }
6057 }
6058 if (!ok)
24eab124
AM		 6059 {
6060#if INFER_ADDR_PREFIX
20f0a1fc 6061 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6062 {
6063 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6064 i.prefixes += 1;
b23bac36
AM		 6065 /* Change the size of any displacement too. At most one of
6066 Disp16 or Disp32 is set.
6067 FIXME. There doesn't seem to be any real need for separate
6068 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6069 Removing them would probably clean up the code quite a lot. */
4eed87de 6070 if (flag_code != CODE_64BIT
40fb9820
L		 6071 && (i.types[this_operand].bitfield.disp16
6072 || i.types[this_operand].bitfield.disp32))
6073 i.types[this_operand]
c6fb90c8 6074 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6075 fudged = 1;
24eab124
AM		 6076 goto tryprefix;
6077 }
eecb386c
AM		 6078 if (fudged)
6079 as_bad (_("`%s' is not a valid base/index expression"),
6080 operand_string);
6081 else
c388dee8 6082#endif
eecb386c
AM		 6083 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6084 operand_string,
3e73aa7c 6085 flag_code_names[flag_code]);
24eab124 6086 }
20f0a1fc 6087 return ok;
24eab124 6088}
252b5132 6089
252b5132 6090/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6091 on error. */
252b5132 6092
252b5132 6093static int
e3bb37b5 6094i386_operand (char *operand_string)
252b5132 6095{
af6bdddf
AM		 6096 const reg_entry *r;
6097 char *end_op;
24eab124 6098 char *op_string = operand_string;
252b5132 6099
24eab124 6100 if (is_space_char (*op_string))
252b5132
RH		 6101 ++op_string;
6102
24eab124 6103 /* We check for an absolute prefix (differentiating,
47926f60 6104 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6105 if (*op_string == ABSOLUTE_PREFIX)
6106 {
6107 ++op_string;
6108 if (is_space_char (*op_string))
6109 ++op_string;
40fb9820 6110 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6111 }
252b5132 6112
47926f60 6113 /* Check if operand is a register. */
4d1bb795 6114 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6115 {
40fb9820
L		 6116 i386_operand_type temp;
6117
24eab124
AM		 6118 /* Check for a segment override by searching for ':' after a
6119 segment register. */
6120 op_string = end_op;
6121 if (is_space_char (*op_string))
6122 ++op_string;
40fb9820
L		 6123 if (*op_string == ':'
6124 && (r->reg_type.bitfield.sreg2
6125 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6126 {
6127 switch (r->reg_num)
6128 {
6129 case 0:
6130 i.seg[i.mem_operands] = &es;
6131 break;
6132 case 1:
6133 i.seg[i.mem_operands] = &cs;
6134 break;
6135 case 2:
6136 i.seg[i.mem_operands] = &ss;
6137 break;
6138 case 3:
6139 i.seg[i.mem_operands] = &ds;
6140 break;
6141 case 4:
6142 i.seg[i.mem_operands] = &fs;
6143 break;
6144 case 5:
6145 i.seg[i.mem_operands] = &gs;
6146 break;
6147 }
252b5132 6148
24eab124 6149 /* Skip the ':' and whitespace. */
252b5132
RH		 6150 ++op_string;
6151 if (is_space_char (*op_string))
24eab124 6152 ++op_string;
252b5132 6153
24eab124
AM		 6154 if (!is_digit_char (*op_string)
6155 && !is_identifier_char (*op_string)
6156 && *op_string != '('
6157 && *op_string != ABSOLUTE_PREFIX)
6158 {
6159 as_bad (_("bad memory operand `%s'"), op_string);
6160 return 0;
6161 }
47926f60 6162 /* Handle case of %es:*foo. */
24eab124
AM		 6163 if (*op_string == ABSOLUTE_PREFIX)
6164 {
6165 ++op_string;
6166 if (is_space_char (*op_string))
6167 ++op_string;
40fb9820 6168 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6169 }
6170 goto do_memory_reference;
6171 }
6172 if (*op_string)
6173 {
d0b47220 6174 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6175 return 0;
6176 }
40fb9820
L		 6177 temp = r->reg_type;
6178 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6179 i.types[this_operand] = operand_type_or (i.types[this_operand],
6180 temp);
520dc8e8 6181 i.op[this_operand].regs = r;
24eab124
AM		 6182 i.reg_operands++;
6183 }
af6bdddf
AM		 6184 else if (*op_string == REGISTER_PREFIX)
6185 {
6186 as_bad (_("bad register name `%s'"), op_string);
6187 return 0;
6188 }
24eab124 6189 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6190 {
24eab124 6191 ++op_string;
40fb9820 6192 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6193 {
d0b47220 6194 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6195 return 0;
6196 }
6197 if (!i386_immediate (op_string))
6198 return 0;
6199 }
6200 else if (is_digit_char (*op_string)
6201 || is_identifier_char (*op_string)
e5cb08ac 6202 || *op_string == '(')
24eab124 6203 {
47926f60 6204 /* This is a memory reference of some sort. */
af6bdddf 6205 char *base_string;
252b5132 6206
47926f60 6207 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6208 char *displacement_string_start;
6209 char *displacement_string_end;
252b5132 6210
24eab124 6211 do_memory_reference:
24eab124 6212 if ((i.mem_operands == 1
40fb9820 6213 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6214 || i.mem_operands == 2)
6215 {
6216 as_bad (_("too many memory references for `%s'"),
6217 current_templates->start->name);
6218 return 0;
6219 }
252b5132 6220
24eab124
AM		 6221 /* Check for base index form. We detect the base index form by
6222 looking for an ')' at the end of the operand, searching
6223 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6224 after the '('. */
af6bdddf 6225 base_string = op_string + strlen (op_string);
c3332e24 6226
af6bdddf
AM		 6227 --base_string;
6228 if (is_space_char (*base_string))
6229 --base_string;
252b5132 6230
47926f60 6231 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6232 displacement_string_start = op_string;
6233 displacement_string_end = base_string + 1;
252b5132 6234
24eab124
AM		 6235 if (*base_string == ')')
6236 {
af6bdddf 6237 char *temp_string;
24eab124
AM		 6238 unsigned int parens_balanced = 1;
6239 /* We've already checked that the number of left & right ()'s are
47926f60 6240 equal, so this loop will not be infinite. */
24eab124
AM		 6241 do
6242 {
6243 base_string--;
6244 if (*base_string == ')')
6245 parens_balanced++;
6246 if (*base_string == '(')
6247 parens_balanced--;
6248 }
6249 while (parens_balanced);
c3332e24 6250
af6bdddf 6251 temp_string = base_string;
c3332e24 6252
24eab124 6253 /* Skip past '(' and whitespace. */
252b5132
RH		 6254 ++base_string;
6255 if (is_space_char (*base_string))
24eab124 6256 ++base_string;
252b5132 6257
af6bdddf 6258 if (*base_string == ','
4eed87de
AM		 6259 || ((i.base_reg = parse_register (base_string, &end_op))
6260 != NULL))
252b5132 6261 {
af6bdddf 6262 displacement_string_end = temp_string;
252b5132 6263
40fb9820 6264 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6265
af6bdddf 6266 if (i.base_reg)
24eab124 6267 {
24eab124
AM		 6268 base_string = end_op;
6269 if (is_space_char (*base_string))
6270 ++base_string;
af6bdddf
AM		 6271 }
6272
6273 /* There may be an index reg or scale factor here. */
6274 if (*base_string == ',')
6275 {
6276 ++base_string;
6277 if (is_space_char (*base_string))
6278 ++base_string;
6279
4eed87de
AM		 6280 if ((i.index_reg = parse_register (base_string, &end_op))
6281 != NULL)
24eab124 6282 {
af6bdddf 6283 base_string = end_op;
24eab124
AM		 6284 if (is_space_char (*base_string))
6285 ++base_string;
af6bdddf
AM		 6286 if (*base_string == ',')
6287 {
6288 ++base_string;
6289 if (is_space_char (*base_string))
6290 ++base_string;
6291 }
e5cb08ac 6292 else if (*base_string != ')')
af6bdddf 6293 {
4eed87de
AM		 6294 as_bad (_("expecting `,' or `)' "
6295 "after index register in `%s'"),
af6bdddf
AM		 6296 operand_string);
6297 return 0;
6298 }
24eab124 6299 }
af6bdddf 6300 else if (*base_string == REGISTER_PREFIX)
24eab124 6301 {
af6bdddf 6302 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6303 return 0;
6304 }
252b5132 6305
47926f60 6306 /* Check for scale factor. */
551c1ca1 6307 if (*base_string != ')')
af6bdddf 6308 {
551c1ca1
AM		 6309 char *end_scale = i386_scale (base_string);
6310
6311 if (!end_scale)
af6bdddf 6312 return 0;
24eab124 6313
551c1ca1 6314 base_string = end_scale;
af6bdddf
AM		 6315 if (is_space_char (*base_string))
6316 ++base_string;
6317 if (*base_string != ')')
6318 {
4eed87de
AM		 6319 as_bad (_("expecting `)' "
6320 "after scale factor in `%s'"),
af6bdddf
AM		 6321 operand_string);
6322 return 0;
6323 }
6324 }
6325 else if (!i.index_reg)
24eab124 6326 {
4eed87de
AM		 6327 as_bad (_("expecting index register or scale factor "
6328 "after `,'; got '%c'"),
af6bdddf 6329 *base_string);
24eab124
AM		 6330 return 0;
6331 }
6332 }
af6bdddf 6333 else if (*base_string != ')')
24eab124 6334 {
4eed87de
AM		 6335 as_bad (_("expecting `,' or `)' "
6336 "after base register in `%s'"),
af6bdddf 6337 operand_string);
24eab124
AM		 6338 return 0;
6339 }
c3332e24 6340 }
af6bdddf 6341 else if (*base_string == REGISTER_PREFIX)
c3332e24 6342 {
af6bdddf 6343 as_bad (_("bad register name `%s'"), base_string);
24eab124 6344 return 0;
c3332e24 6345 }
24eab124
AM		 6346 }
6347
6348 /* If there's an expression beginning the operand, parse it,
6349 assuming displacement_string_start and
6350 displacement_string_end are meaningful. */
6351 if (displacement_string_start != displacement_string_end)
6352 {
6353 if (!i386_displacement (displacement_string_start,
6354 displacement_string_end))
6355 return 0;
6356 }
6357
6358 /* Special case for (%dx) while doing input/output op. */
6359 if (i.base_reg
c6fb90c8 6360 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6361 && i.index_reg == 0
6362 && i.log2_scale_factor == 0
6363 && i.seg[i.mem_operands] == 0
40fb9820 6364 && !operand_type_check (i.types[this_operand], disp))
24eab124 6365 {
c6fb90c8 6366 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6367 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6368 return 1;
6369 }
6370
eecb386c
AM		 6371 if (i386_index_check (operand_string) == 0)
6372 return 0;
24eab124
AM		 6373 i.mem_operands++;
6374 }
6375 else
ce8a8b2f
AM		 6376 {
6377 /* It's not a memory operand; argh! */
24eab124
AM		 6378 as_bad (_("invalid char %s beginning operand %d `%s'"),
6379 output_invalid (*op_string),
6380 this_operand + 1,
6381 op_string);
6382 return 0;
6383 }
47926f60 6384 return 1; /* Normal return. */
252b5132
RH		 6385}
6386\f
ee7fcc42
AM		 6387/* md_estimate_size_before_relax()
6388
6389 Called just before relax() for rs_machine_dependent frags. The x86
6390 assembler uses these frags to handle variable size jump
6391 instructions.
6392
6393 Any symbol that is now undefined will not become defined.
6394 Return the correct fr_subtype in the frag.
6395 Return the initial "guess for variable size of frag" to caller.
6396 The guess is actually the growth beyond the fixed part. Whatever
6397 we do to grow the fixed or variable part contributes to our
6398 returned value. */
6399
252b5132
RH		 6400int
6401md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6402 fragS *fragP;
6403 segT segment;
252b5132 6404{
252b5132 6405 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6406 check for un-relaxable symbols. On an ELF system, we can't relax
6407 an externally visible symbol, because it may be overridden by a
6408 shared library. */
6409 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6410#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6411 || (IS_ELF
31312f95
AM		 6412 && (S_IS_EXTERNAL (fragP->fr_symbol)
6413 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6414#endif
6415 )
252b5132 6416 {
b98ef147
AM		 6417 /* Symbol is undefined in this segment, or we need to keep a
6418 reloc so that weak symbols can be overridden. */
6419 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6420 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6421 unsigned char *opcode;
6422 int old_fr_fix;
f6af82bd 6423
ee7fcc42
AM		 6424 if (fragP->fr_var != NO_RELOC)
6425 reloc_type = fragP->fr_var;
b98ef147 6426 else if (size == 2)
f6af82bd
AM		 6427 reloc_type = BFD_RELOC_16_PCREL;
6428 else
6429 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6430
ee7fcc42
AM		 6431 old_fr_fix = fragP->fr_fix;
6432 opcode = (unsigned char *) fragP->fr_opcode;
6433
fddf5b5b 6434 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6435 {
fddf5b5b
AM		 6436 case UNCOND_JUMP:
6437 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6438 opcode[0] = 0xe9;
252b5132 6439 fragP->fr_fix += size;
062cd5e7
AS		 6440 fix_new (fragP, old_fr_fix, size,
6441 fragP->fr_symbol,
6442 fragP->fr_offset, 1,
6443 reloc_type);
252b5132
RH		 6444 break;
6445
fddf5b5b 6446 case COND_JUMP86:
412167cb
AM		 6447 if (size == 2
6448 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6449 {
6450 /* Negate the condition, and branch past an
6451 unconditional jump. */
6452 opcode[0] ^= 1;
6453 opcode[1] = 3;
6454 /* Insert an unconditional jump. */
6455 opcode[2] = 0xe9;
6456 /* We added two extra opcode bytes, and have a two byte
6457 offset. */
6458 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6459 fix_new (fragP, old_fr_fix + 2, 2,
6460 fragP->fr_symbol,
6461 fragP->fr_offset, 1,
6462 reloc_type);
fddf5b5b
AM		 6463 break;
6464 }
6465 /* Fall through. */
6466
6467 case COND_JUMP:
412167cb
AM		 6468 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6469 {
3e02c1cc
AM		 6470 fixS *fixP;
6471
412167cb 6472 fragP->fr_fix += 1;
3e02c1cc
AM		 6473 fixP = fix_new (fragP, old_fr_fix, 1,
6474 fragP->fr_symbol,
6475 fragP->fr_offset, 1,
6476 BFD_RELOC_8_PCREL);
6477 fixP->fx_signed = 1;
412167cb
AM		 6478 break;
6479 }
93c2a809 6480
24eab124 6481 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6482 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6483 opcode[1] = opcode[0] + 0x10;
f6af82bd 6484 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6485 /* We've added an opcode byte. */
6486 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6487 fix_new (fragP, old_fr_fix + 1, size,
6488 fragP->fr_symbol,
6489 fragP->fr_offset, 1,
6490 reloc_type);
252b5132 6491 break;
fddf5b5b
AM		 6492
6493 default:
6494 BAD_CASE (fragP->fr_subtype);
6495 break;
252b5132
RH		 6496 }
6497 frag_wane (fragP);
ee7fcc42 6498 return fragP->fr_fix - old_fr_fix;
252b5132 6499 }
93c2a809 6500
93c2a809
AM		 6501 /* Guess size depending on current relax state. Initially the relax
6502 state will correspond to a short jump and we return 1, because
6503 the variable part of the frag (the branch offset) is one byte
6504 long. However, we can relax a section more than once and in that
6505 case we must either set fr_subtype back to the unrelaxed state,
6506 or return the value for the appropriate branch. */
6507 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6508}
6509
47926f60
KH		 6510/* Called after relax() is finished.
6511
6512 In: Address of frag.
6513 fr_type == rs_machine_dependent.
6514 fr_subtype is what the address relaxed to.
6515
6516 Out: Any fixSs and constants are set up.
6517 Caller will turn frag into a ".space 0". */
6518
252b5132
RH		 6519void
6520md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6521 bfd *abfd ATTRIBUTE_UNUSED;
6522 segT sec ATTRIBUTE_UNUSED;
29b0f896 6523 fragS *fragP;
252b5132 6524{
29b0f896 6525 unsigned char *opcode;
252b5132 6526 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6527 offsetT target_address;
6528 offsetT opcode_address;
252b5132 6529 unsigned int extension = 0;
847f7ad4 6530 offsetT displacement_from_opcode_start;
252b5132
RH		 6531
6532 opcode = (unsigned char *) fragP->fr_opcode;
6533
47926f60 6534 /* Address we want to reach in file space. */
252b5132 6535 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6536
47926f60 6537 /* Address opcode resides at in file space. */
252b5132
RH		 6538 opcode_address = fragP->fr_address + fragP->fr_fix;
6539
47926f60 6540 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6541 displacement_from_opcode_start = target_address - opcode_address;
6542
fddf5b5b 6543 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6544 {
47926f60
KH		 6545 /* Don't have to change opcode. */
6546 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6547 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6548 }
6549 else
6550 {
6551 if (no_cond_jump_promotion
6552 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6553 as_warn_where (fragP->fr_file, fragP->fr_line,
6554 _("long jump required"));
252b5132 6555
fddf5b5b
AM		 6556 switch (fragP->fr_subtype)
6557 {
6558 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6559 extension = 4; /* 1 opcode + 4 displacement */
6560 opcode[0] = 0xe9;
6561 where_to_put_displacement = &opcode[1];
6562 break;
252b5132 6563
fddf5b5b
AM		 6564 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6565 extension = 2; /* 1 opcode + 2 displacement */
6566 opcode[0] = 0xe9;
6567 where_to_put_displacement = &opcode[1];
6568 break;
252b5132 6569
fddf5b5b
AM		 6570 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6571 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6572 extension = 5; /* 2 opcode + 4 displacement */
6573 opcode[1] = opcode[0] + 0x10;
6574 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6575 where_to_put_displacement = &opcode[2];
6576 break;
252b5132 6577
fddf5b5b
AM		 6578 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6579 extension = 3; /* 2 opcode + 2 displacement */
6580 opcode[1] = opcode[0] + 0x10;
6581 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6582 where_to_put_displacement = &opcode[2];
6583 break;
252b5132 6584
fddf5b5b
AM		 6585 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6586 extension = 4;
6587 opcode[0] ^= 1;
6588 opcode[1] = 3;
6589 opcode[2] = 0xe9;
6590 where_to_put_displacement = &opcode[3];
6591 break;
6592
6593 default:
6594 BAD_CASE (fragP->fr_subtype);
6595 break;
6596 }
252b5132 6597 }
fddf5b5b 6598
7b81dfbb
AJ		 6599 /* If size if less then four we are sure that the operand fits,
6600 but if it's 4, then it could be that the displacement is larger
6601 then -/+ 2GB. */
6602 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6603 && object_64bit
6604 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6605 + ((addressT) 1 << 31))
6606 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6607 {
6608 as_bad_where (fragP->fr_file, fragP->fr_line,
6609 _("jump target out of range"));
6610 /* Make us emit 0. */
6611 displacement_from_opcode_start = extension;
6612 }
47926f60 6613 /* Now put displacement after opcode. */
252b5132
RH		 6614 md_number_to_chars ((char *) where_to_put_displacement,
6615 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6616 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6617 fragP->fr_fix += extension;
6618}
6619\f
252b5132
RH		 6620/* Apply a fixup (fixS) to segment data, once it has been determined
6621 by our caller that we have all the info we need to fix it up.
6622
6623 On the 386, immediates, displacements, and data pointers are all in
6624 the same (little-endian) format, so we don't need to care about which
6625 we are handling. */
6626
94f592af 6627void
55cf6793 6628md_apply_fix (fixP, valP, seg)
47926f60
KH		 6629 /* The fix we're to put in. */
6630 fixS *fixP;
47926f60 6631 /* Pointer to the value of the bits. */
c6682705 6632 valueT *valP;
47926f60
KH		 6633 /* Segment fix is from. */
6634 segT seg ATTRIBUTE_UNUSED;
252b5132 6635{
94f592af 6636 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6637 valueT value = *valP;
252b5132 6638
f86103b7 6639#if !defined (TE_Mach)
93382f6d
AM		 6640 if (fixP->fx_pcrel)
6641 {
6642 switch (fixP->fx_r_type)
6643 {
5865bb77
ILT		 6644 default:
6645 break;
6646
d6ab8113
JB		 6647 case BFD_RELOC_64:
6648 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6649 break;
93382f6d 6650 case BFD_RELOC_32:
ae8887b5 6651 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6652 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6653 break;
6654 case BFD_RELOC_16:
6655 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6656 break;
6657 case BFD_RELOC_8:
6658 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6659 break;
6660 }
6661 }
252b5132 6662
a161fe53 6663 if (fixP->fx_addsy != NULL
31312f95 6664 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6665 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6666 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6667 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6668 && !use_rela_relocations)
252b5132 6669 {
31312f95
AM		 6670 /* This is a hack. There should be a better way to handle this.
6671 This covers for the fact that bfd_install_relocation will
6672 subtract the current location (for partial_inplace, PC relative
6673 relocations); see more below. */
252b5132 6674#ifndef OBJ_AOUT
718ddfc0 6675 if (IS_ELF
252b5132
RH		 6676#ifdef TE_PE
6677 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6678#endif
6679 )
6680 value += fixP->fx_where + fixP->fx_frag->fr_address;
6681#endif
6682#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6683 if (IS_ELF)
252b5132 6684 {
6539b54b 6685 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6686
6539b54b 6687 if ((sym_seg == seg
2f66722d 6688 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6689 && sym_seg != absolute_section))
ae6063d4 6690 && !generic_force_reloc (fixP))
2f66722d
AM		 6691 {
6692 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6693 bfd_install_relocation subtracts them out again. I think
6694 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6695 it. FIXME. */
6696 value += fixP->fx_where + fixP->fx_frag->fr_address;
6697 }
252b5132
RH		 6698 }
6699#endif
6700#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6701 /* For some reason, the PE format does not store a
6702 section address offset for a PC relative symbol. */
6703 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6704 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6705 value += md_pcrel_from (fixP);
6706#endif
6707 }
6708
6709 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6710 and we must not disappoint it. */
252b5132 6711#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6712 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6713 switch (fixP->fx_r_type)
6714 {
6715 case BFD_RELOC_386_PLT32:
3e73aa7c 6716 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6717 /* Make the jump instruction point to the address of the operand. At
6718 runtime we merely add the offset to the actual PLT entry. */
6719 value = -4;
6720 break;
31312f95 6721
13ae64f3
JJ		 6722 case BFD_RELOC_386_TLS_GD:
6723 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6724 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6725 case BFD_RELOC_386_TLS_IE:
6726 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6727 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6728 case BFD_RELOC_X86_64_TLSGD:
6729 case BFD_RELOC_X86_64_TLSLD:
6730 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6731 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6732 value = 0; /* Fully resolved at runtime. No addend. */
6733 /* Fallthrough */
6734 case BFD_RELOC_386_TLS_LE:
6735 case BFD_RELOC_386_TLS_LDO_32:
6736 case BFD_RELOC_386_TLS_LE_32:
6737 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6738 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6739 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6740 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6741 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6742 break;
6743
67a4f2b7
AO		 6744 case BFD_RELOC_386_TLS_DESC_CALL:
6745 case BFD_RELOC_X86_64_TLSDESC_CALL:
6746 value = 0; /* Fully resolved at runtime. No addend. */
6747 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6748 fixP->fx_done = 0;
6749 return;
6750
00f7efb6
JJ		 6751 case BFD_RELOC_386_GOT32:
6752 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6753 value = 0; /* Fully resolved at runtime. No addend. */
6754 break;
47926f60
KH		 6755
6756 case BFD_RELOC_VTABLE_INHERIT:
6757 case BFD_RELOC_VTABLE_ENTRY:
6758 fixP->fx_done = 0;
94f592af 6759 return;
47926f60
KH		 6760
6761 default:
6762 break;
6763 }
6764#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6765 *valP = value;
f86103b7 6766#endif /* !defined (TE_Mach) */
3e73aa7c 6767
3e73aa7c 6768 /* Are we finished with this relocation now? */
c6682705 6769 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6770 fixP->fx_done = 1;
6771 else if (use_rela_relocations)
6772 {
6773 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6774 /* Remember value for tc_gen_reloc. */
6775 fixP->fx_addnumber = value;
3e73aa7c
JH		 6776 value = 0;
6777 }
f86103b7 6778
94f592af 6779 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6780}
252b5132 6781\f
252b5132 6782char *
499ac353 6783md_atof (int type, char *litP, int *sizeP)
252b5132 6784{
499ac353
NC		 6785 /* This outputs the LITTLENUMs in REVERSE order;
6786 in accord with the bigendian 386. */
6787 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6788}
6789\f
2d545b82 6790static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6791
252b5132 6792static char *
e3bb37b5 6793output_invalid (int c)
252b5132 6794{
3882b010 6795 if (ISPRINT (c))
f9f21a03
L		 6796 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6797 "'%c'", c);
252b5132 6798 else
f9f21a03 6799 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6800 "(0x%x)", (unsigned char) c);
252b5132
RH		 6801 return output_invalid_buf;
6802}
6803
af6bdddf 6804/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6805
6806static const reg_entry *
4d1bb795 6807parse_real_register (char *reg_string, char **end_op)
252b5132 6808{
af6bdddf
AM		 6809 char *s = reg_string;
6810 char *p;
252b5132
RH		 6811 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6812 const reg_entry *r;
6813
6814 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6815 if (*s == REGISTER_PREFIX)
6816 ++s;
6817
6818 if (is_space_char (*s))
6819 ++s;
6820
6821 p = reg_name_given;
af6bdddf 6822 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6823 {
6824 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6825 return (const reg_entry *) NULL;
6826 s++;
252b5132
RH		 6827 }
6828
6588847e
DN		 6829 /* For naked regs, make sure that we are not dealing with an identifier.
6830 This prevents confusing an identifier like `eax_var' with register
6831 `eax'. */
6832 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6833 return (const reg_entry *) NULL;
6834
af6bdddf 6835 *end_op = s;
252b5132
RH		 6836
6837 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6838
5f47d35b 6839 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6840 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6841 {
5f47d35b
AM		 6842 if (is_space_char (*s))
6843 ++s;
6844 if (*s == '(')
6845 {
af6bdddf 6846 ++s;
5f47d35b
AM		 6847 if (is_space_char (*s))
6848 ++s;
6849 if (*s >= '0' && *s <= '7')
6850 {
db557034 6851 int fpr = *s - '0';
af6bdddf 6852 ++s;
5f47d35b
AM		 6853 if (is_space_char (*s))
6854 ++s;
6855 if (*s == ')')
6856 {
6857 *end_op = s + 1;
db557034
AM		 6858 r = hash_find (reg_hash, "st(0)");
6859 know (r);
6860 return r + fpr;
5f47d35b 6861 }
5f47d35b 6862 }
47926f60 6863 /* We have "%st(" then garbage. */
5f47d35b
AM		 6864 return (const reg_entry *) NULL;
6865 }
6866 }
6867
db51cc60
L		 6868 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6869 if (r != NULL
6870 && !allow_index_reg
6871 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6872 return (const reg_entry *) NULL;
6873
1ae00879 6874 if (r != NULL
d946b91f 6875 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6876 || r->reg_type.bitfield.reg64)
6877 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6878 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6879 && flag_code != CODE_64BIT)
20f0a1fc 6880 return (const reg_entry *) NULL;
1ae00879 6881
252b5132
RH		 6882 return r;
6883}
4d1bb795
JB		 6884
6885/* REG_STRING starts *before* REGISTER_PREFIX. */
6886
6887static const reg_entry *
6888parse_register (char *reg_string, char **end_op)
6889{
6890 const reg_entry *r;
6891
6892 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6893 r = parse_real_register (reg_string, end_op);
6894 else
6895 r = NULL;
6896 if (!r)
6897 {
6898 char *save = input_line_pointer;
6899 char c;
6900 symbolS *symbolP;
6901
6902 input_line_pointer = reg_string;
6903 c = get_symbol_end ();
6904 symbolP = symbol_find (reg_string);
6905 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6906 {
6907 const expressionS *e = symbol_get_value_expression (symbolP);
6908
6909 know (e->X_op == O_register);
4eed87de 6910 know (e->X_add_number >= 0
c3fe08fa 6911 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6912 r = i386_regtab + e->X_add_number;
6913 *end_op = input_line_pointer;
6914 }
6915 *input_line_pointer = c;
6916 input_line_pointer = save;
6917 }
6918 return r;
6919}
6920
6921int
6922i386_parse_name (char *name, expressionS *e, char *nextcharP)
6923{
6924 const reg_entry *r;
6925 char *end = input_line_pointer;
6926
6927 *end = *nextcharP;
6928 r = parse_register (name, &input_line_pointer);
6929 if (r && end <= input_line_pointer)
6930 {
6931 *nextcharP = *input_line_pointer;
6932 *input_line_pointer = 0;
6933 e->X_op = O_register;
6934 e->X_add_number = r - i386_regtab;
6935 return 1;
6936 }
6937 input_line_pointer = end;
6938 *end = 0;
6939 return 0;
6940}
6941
6942void
6943md_operand (expressionS *e)
6944{
6945 if (*input_line_pointer == REGISTER_PREFIX)
6946 {
6947 char *end;
6948 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6949
6950 if (r)
6951 {
6952 e->X_op = O_register;
6953 e->X_add_number = r - i386_regtab;
6954 input_line_pointer = end;
6955 }
6956 }
6957}
6958
252b5132 6959\f
4cc782b5 6960#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6961const char *md_shortopts = "kVQ:sqn";
252b5132 6962#else
12b55ccc 6963const char *md_shortopts = "qn";
252b5132 6964#endif
6e0b89ee 6965
3e73aa7c 6966#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6967#define OPTION_64 (OPTION_MD_BASE + 1)
6968#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6969#define OPTION_MARCH (OPTION_MD_BASE + 3)
6970#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 6971#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6972#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6973#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6974#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6975#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 6976
99ad8390
NC		 6977struct option md_longopts[] =
6978{
3e73aa7c 6979 {"32", no_argument, NULL, OPTION_32},
99ad8390 6980#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6981 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6982#endif
b3b91714 6983 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6984 {"march", required_argument, NULL, OPTION_MARCH},
6985 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 6986 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
6987 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
6988 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
6989 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
6990 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 6991 {NULL, no_argument, NULL, 0}
6992};
6993size_t md_longopts_size = sizeof (md_longopts);
6994
6995int
9103f4f4 6996md_parse_option (int c, char *arg)
252b5132 6997{
9103f4f4
L		 6998 unsigned int i;
6999
252b5132
RH		 7000 switch (c)
7001 {
12b55ccc
L		 7002 case 'n':
7003 optimize_align_code = 0;
7004 break;
7005
a38cf1db
AM		 7006 case 'q':
7007 quiet_warnings = 1;
252b5132
RH		 7008 break;
7009
7010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7011 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7012 should be emitted or not. FIXME: Not implemented. */
7013 case 'Q':
252b5132
RH		 7014 break;
7015
7016 /* -V: SVR4 argument to print version ID. */
7017 case 'V':
7018 print_version_id ();
7019 break;
7020
a38cf1db
AM		 7021 /* -k: Ignore for FreeBSD compatibility. */
7022 case 'k':
252b5132 7023 break;
4cc782b5
ILT		 7024
7025 case 's':
7026 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7027 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7028 break;
99ad8390
NC		 7029#endif
7030#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7031 case OPTION_64:
7032 {
7033 const char **list, **l;
7034
3e73aa7c
JH		 7035 list = bfd_target_list ();
7036 for (l = list; *l != NULL; l++)
8620418b 7037 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7038 || strcmp (*l, "coff-x86-64") == 0
7039 || strcmp (*l, "pe-x86-64") == 0
7040 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7041 {
7042 default_arch = "x86_64";
7043 break;
7044 }
3e73aa7c 7045 if (*l == NULL)
6e0b89ee 7046 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7047 free (list);
7048 }
7049 break;
7050#endif
252b5132 7051
6e0b89ee
AM		 7052 case OPTION_32:
7053 default_arch = "i386";
7054 break;
7055
b3b91714
AM		 7056 case OPTION_DIVIDE:
7057#ifdef SVR4_COMMENT_CHARS
7058 {
7059 char *n, *t;
7060 const char *s;
7061
7062 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7063 t = n;
7064 for (s = i386_comment_chars; *s != '\0'; s++)
7065 if (*s != '/')
7066 *t++ = *s;
7067 *t = '\0';
7068 i386_comment_chars = n;
7069 }
7070#endif
7071 break;
7072
9103f4f4
L		 7073 case OPTION_MARCH:
7074 if (*arg == '.')
7075 as_fatal (_("Invalid -march= option: `%s'"), arg);
7076 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7077 {
7078 if (strcmp (arg, cpu_arch [i].name) == 0)
7079 {
ccc9c027 7080 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7081 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7082 if (!cpu_arch_tune_set)
7083 {
7084 cpu_arch_tune = cpu_arch_isa;
7085 cpu_arch_tune_flags = cpu_arch_isa_flags;
7086 }
9103f4f4
L		 7087 break;
7088 }
7089 }
7090 if (i >= ARRAY_SIZE (cpu_arch))
7091 as_fatal (_("Invalid -march= option: `%s'"), arg);
7092 break;
7093
7094 case OPTION_MTUNE:
7095 if (*arg == '.')
7096 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7097 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7098 {
7099 if (strcmp (arg, cpu_arch [i].name) == 0)
7100 {
ccc9c027 7101 cpu_arch_tune_set = 1;
9103f4f4
L		 7102 cpu_arch_tune = cpu_arch [i].type;
7103 cpu_arch_tune_flags = cpu_arch[i].flags;
7104 break;
7105 }
7106 }
7107 if (i >= ARRAY_SIZE (cpu_arch))
7108 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7109 break;
7110
1efbbeb4
L		 7111 case OPTION_MMNEMONIC:
7112 if (strcasecmp (arg, "att") == 0)
7113 intel_mnemonic = 0;
7114 else if (strcasecmp (arg, "intel") == 0)
7115 intel_mnemonic = 1;
7116 else
7117 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7118 break;
7119
7120 case OPTION_MSYNTAX:
7121 if (strcasecmp (arg, "att") == 0)
7122 intel_syntax = 0;
7123 else if (strcasecmp (arg, "intel") == 0)
7124 intel_syntax = 1;
7125 else
7126 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7127 break;
7128
7129 case OPTION_MINDEX_REG:
7130 allow_index_reg = 1;
7131 break;
7132
7133 case OPTION_MNAKED_REG:
7134 allow_naked_reg = 1;
7135 break;
7136
7137 case OPTION_MOLD_GCC:
7138 old_gcc = 1;
7139 intel_mnemonic = 0;
7140 break;
7141
252b5132
RH		 7142 default:
7143 return 0;
7144 }
7145 return 1;
7146}
7147
7148void
7149md_show_usage (stream)
7150 FILE *stream;
7151{
4cc782b5
ILT		 7152#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7153 fprintf (stream, _("\
a38cf1db
AM		 7154 -Q ignored\n\
7155 -V print assembler version number\n\
b3b91714
AM		 7156 -k ignored\n"));
7157#endif
7158 fprintf (stream, _("\
12b55ccc 7159 -n Do not optimize code alignment\n\
b3b91714
AM		 7160 -q quieten some warnings\n"));
7161#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7162 fprintf (stream, _("\
a38cf1db 7163 -s ignored\n"));
b3b91714 7164#endif
751d281c
L		 7165#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7166 fprintf (stream, _("\
7167 --32/--64 generate 32bit/64bit code\n"));
7168#endif
b3b91714
AM		 7169#ifdef SVR4_COMMENT_CHARS
7170 fprintf (stream, _("\
7171 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7172#else
7173 fprintf (stream, _("\
b3b91714 7174 --divide ignored\n"));
4cc782b5 7175#endif
9103f4f4
L		 7176 fprintf (stream, _("\
7177 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7178 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7179 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 7180
252b5132
RH		 7181}
7182
3e73aa7c 7183#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7184 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7185
7186/* Pick the target format to use. */
7187
47926f60 7188const char *
e3bb37b5 7189i386_target_format (void)
252b5132 7190{
3e73aa7c 7191 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7192 {
7193 set_code_flag (CODE_64BIT);
c6fb90c8 7194 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7195 {
7196 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7197 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7198 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7199 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7200 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7201 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7202 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7203 cpu_arch_isa_flags.bitfield.cpummx= 1;
7204 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7205 cpu_arch_isa_flags.bitfield.cpusse = 1;
7206 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7207 }
c6fb90c8 7208 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7209 {
7210 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7211 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7212 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7213 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7214 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7215 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7216 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7217 cpu_arch_tune_flags.bitfield.cpummx= 1;
7218 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7219 cpu_arch_tune_flags.bitfield.cpusse = 1;
7220 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7221 }
9103f4f4 7222 }
3e73aa7c 7223 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7224 {
7225 set_code_flag (CODE_32BIT);
c6fb90c8 7226 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7227 {
7228 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7229 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7230 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7231 }
c6fb90c8 7232 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7233 {
7234 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7235 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7236 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7237 }
9103f4f4 7238 }
3e73aa7c
JH		 7239 else
7240 as_fatal (_("Unknown architecture"));
252b5132
RH		 7241 switch (OUTPUT_FLAVOR)
7242 {
872ce6ff
L		 7243#ifdef TE_PEP
7244 case bfd_target_coff_flavour:
7245 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7246 break;
7247#endif
4c63da97
AM		 7248#ifdef OBJ_MAYBE_AOUT
7249 case bfd_target_aout_flavour:
47926f60 7250 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7251#endif
7252#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7253 case bfd_target_coff_flavour:
7254 return "coff-i386";
4c63da97 7255#endif
3e73aa7c 7256#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7257 case bfd_target_elf_flavour:
3e73aa7c 7258 {
e5cb08ac 7259 if (flag_code == CODE_64BIT)
4fa24527
JB		 7260 {
7261 object_64bit = 1;
7262 use_rela_relocations = 1;
7263 }
9d7cbccd 7264 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7265 }
4c63da97 7266#endif
252b5132
RH		 7267 default:
7268 abort ();
7269 return NULL;
7270 }
7271}
7272
47926f60 7273#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7274
7275#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7276void
7277i386_elf_emit_arch_note (void)
a847613f 7278{
718ddfc0 7279 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7280 {
7281 char *p;
7282 asection *seg = now_seg;
7283 subsegT subseg = now_subseg;
7284 Elf_Internal_Note i_note;
7285 Elf_External_Note e_note;
7286 asection *note_secp;
7287 int len;
7288
7289 /* Create the .note section. */
7290 note_secp = subseg_new (".note", 0);
7291 bfd_set_section_flags (stdoutput,
7292 note_secp,
7293 SEC_HAS_CONTENTS | SEC_READONLY);
7294
7295 /* Process the arch string. */
7296 len = strlen (cpu_arch_name);
7297
7298 i_note.namesz = len + 1;
7299 i_note.descsz = 0;
7300 i_note.type = NT_ARCH;
7301 p = frag_more (sizeof (e_note.namesz));
7302 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7303 p = frag_more (sizeof (e_note.descsz));
7304 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7305 p = frag_more (sizeof (e_note.type));
7306 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7307 p = frag_more (len + 1);
7308 strcpy (p, cpu_arch_name);
7309
7310 frag_align (2, 0, 0);
7311
7312 subseg_set (seg, subseg);
7313 }
7314}
7315#endif
252b5132 7316\f
252b5132
RH		 7317symbolS *
7318md_undefined_symbol (name)
7319 char *name;
7320{
18dc2407
ILT		 7321 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7322 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7323 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7324 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7325 {
7326 if (!GOT_symbol)
7327 {
7328 if (symbol_find (name))
7329 as_bad (_("GOT already in symbol table"));
7330 GOT_symbol = symbol_new (name, undefined_section,
7331 (valueT) 0, &zero_address_frag);
7332 };
7333 return GOT_symbol;
7334 }
252b5132
RH		 7335 return 0;
7336}
7337
7338/* Round up a section size to the appropriate boundary. */
47926f60 7339
252b5132
RH		 7340valueT
7341md_section_align (segment, size)
ab9da554 7342 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7343 valueT size;
7344{
4c63da97
AM		 7345#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7346 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7347 {
7348 /* For a.out, force the section size to be aligned. If we don't do
7349 this, BFD will align it for us, but it will not write out the
7350 final bytes of the section. This may be a bug in BFD, but it is
7351 easier to fix it here since that is how the other a.out targets
7352 work. */
7353 int align;
7354
7355 align = bfd_get_section_alignment (stdoutput, segment);
7356 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7357 }
252b5132
RH		 7358#endif
7359
7360 return size;
7361}
7362
7363/* On the i386, PC-relative offsets are relative to the start of the
7364 next instruction. That is, the address of the offset, plus its
7365 size, since the offset is always the last part of the insn. */
7366
7367long
e3bb37b5 7368md_pcrel_from (fixS *fixP)
252b5132
RH		 7369{
7370 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7371}
7372
7373#ifndef I386COFF
7374
7375static void
e3bb37b5 7376s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7377{
29b0f896 7378 int temp;
252b5132 7379
8a75718c
JB		 7380#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7381 if (IS_ELF)
7382 obj_elf_section_change_hook ();
7383#endif
252b5132
RH		 7384 temp = get_absolute_expression ();
7385 subseg_set (bss_section, (subsegT) temp);
7386 demand_empty_rest_of_line ();
7387}
7388
7389#endif
7390
252b5132 7391void
e3bb37b5 7392i386_validate_fix (fixS *fixp)
252b5132
RH		 7393{
7394 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7395 {
23df1078
JH		 7396 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7397 {
4fa24527 7398 if (!object_64bit)
23df1078
JH		 7399 abort ();
7400 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7401 }
7402 else
7403 {
4fa24527 7404 if (!object_64bit)
d6ab8113
JB		 7405 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7406 else
7407 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7408 }
252b5132
RH		 7409 fixp->fx_subsy = 0;
7410 }
7411}
7412
252b5132
RH		 7413arelent *
7414tc_gen_reloc (section, fixp)
ab9da554 7415 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7416 fixS *fixp;
7417{
7418 arelent *rel;
7419 bfd_reloc_code_real_type code;
7420
7421 switch (fixp->fx_r_type)
7422 {
3e73aa7c
JH		 7423 case BFD_RELOC_X86_64_PLT32:
7424 case BFD_RELOC_X86_64_GOT32:
7425 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7426 case BFD_RELOC_386_PLT32:
7427 case BFD_RELOC_386_GOT32:
7428 case BFD_RELOC_386_GOTOFF:
7429 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7430 case BFD_RELOC_386_TLS_GD:
7431 case BFD_RELOC_386_TLS_LDM:
7432 case BFD_RELOC_386_TLS_LDO_32:
7433 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7434 case BFD_RELOC_386_TLS_IE:
7435 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7436 case BFD_RELOC_386_TLS_LE_32:
7437 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7438 case BFD_RELOC_386_TLS_GOTDESC:
7439 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7440 case BFD_RELOC_X86_64_TLSGD:
7441 case BFD_RELOC_X86_64_TLSLD:
7442 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7443 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7444 case BFD_RELOC_X86_64_GOTTPOFF:
7445 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7446 case BFD_RELOC_X86_64_TPOFF64:
7447 case BFD_RELOC_X86_64_GOTOFF64:
7448 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7449 case BFD_RELOC_X86_64_GOT64:
7450 case BFD_RELOC_X86_64_GOTPCREL64:
7451 case BFD_RELOC_X86_64_GOTPC64:
7452 case BFD_RELOC_X86_64_GOTPLT64:
7453 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7454 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7455 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7456 case BFD_RELOC_RVA:
7457 case BFD_RELOC_VTABLE_ENTRY:
7458 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7459#ifdef TE_PE
7460 case BFD_RELOC_32_SECREL:
7461#endif
252b5132
RH		 7462 code = fixp->fx_r_type;
7463 break;
dbbaec26
L		 7464 case BFD_RELOC_X86_64_32S:
7465 if (!fixp->fx_pcrel)
7466 {
7467 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7468 code = fixp->fx_r_type;
7469 break;
7470 }
252b5132 7471 default:
93382f6d 7472 if (fixp->fx_pcrel)
252b5132 7473 {
93382f6d
AM		 7474 switch (fixp->fx_size)
7475 {
7476 default:
b091f402
AM		 7477 as_bad_where (fixp->fx_file, fixp->fx_line,
7478 _("can not do %d byte pc-relative relocation"),
7479 fixp->fx_size);
93382f6d
AM		 7480 code = BFD_RELOC_32_PCREL;
7481 break;
7482 case 1: code = BFD_RELOC_8_PCREL; break;
7483 case 2: code = BFD_RELOC_16_PCREL; break;
7484 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7485#ifdef BFD64
7486 case 8: code = BFD_RELOC_64_PCREL; break;
7487#endif
93382f6d
AM		 7488 }
7489 }
7490 else
7491 {
7492 switch (fixp->fx_size)
7493 {
7494 default:
b091f402
AM		 7495 as_bad_where (fixp->fx_file, fixp->fx_line,
7496 _("can not do %d byte relocation"),
7497 fixp->fx_size);
93382f6d
AM		 7498 code = BFD_RELOC_32;
7499 break;
7500 case 1: code = BFD_RELOC_8; break;
7501 case 2: code = BFD_RELOC_16; break;
7502 case 4: code = BFD_RELOC_32; break;
937149dd 7503#ifdef BFD64
3e73aa7c 7504 case 8: code = BFD_RELOC_64; break;
937149dd 7505#endif
93382f6d 7506 }
252b5132
RH		 7507 }
7508 break;
7509 }
252b5132 7510
d182319b
JB		 7511 if ((code == BFD_RELOC_32
7512 || code == BFD_RELOC_32_PCREL
7513 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7514 && GOT_symbol
7515 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7516 {
4fa24527 7517 if (!object_64bit)
d6ab8113
JB		 7518 code = BFD_RELOC_386_GOTPC;
7519 else
7520 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7521 }
7b81dfbb
AJ		 7522 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7523 && GOT_symbol
7524 && fixp->fx_addsy == GOT_symbol)
7525 {
7526 code = BFD_RELOC_X86_64_GOTPC64;
7527 }
252b5132
RH		 7528
7529 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7530 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7531 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7532
7533 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7534
3e73aa7c
JH		 7535 if (!use_rela_relocations)
7536 {
7537 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7538 vtable entry to be used in the relocation's section offset. */
7539 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7540 rel->address = fixp->fx_offset;
252b5132 7541
c6682705 7542 rel->addend = 0;
3e73aa7c
JH		 7543 }
7544 /* Use the rela in 64bit mode. */
252b5132 7545 else
3e73aa7c 7546 {
062cd5e7
AS		 7547 if (!fixp->fx_pcrel)
7548 rel->addend = fixp->fx_offset;
7549 else
7550 switch (code)
7551 {
7552 case BFD_RELOC_X86_64_PLT32:
7553 case BFD_RELOC_X86_64_GOT32:
7554 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7555 case BFD_RELOC_X86_64_TLSGD:
7556 case BFD_RELOC_X86_64_TLSLD:
7557 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7558 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7559 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7560 rel->addend = fixp->fx_offset - fixp->fx_size;
7561 break;
7562 default:
7563 rel->addend = (section->vma
7564 - fixp->fx_size
7565 + fixp->fx_addnumber
7566 + md_pcrel_from (fixp));
7567 break;
7568 }
3e73aa7c
JH		 7569 }
7570
252b5132
RH		 7571 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7572 if (rel->howto == NULL)
7573 {
7574 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7575 _("cannot represent relocation type %s"),
252b5132
RH		 7576 bfd_get_reloc_code_name (code));
7577 /* Set howto to a garbage value so that we can keep going. */
7578 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7579 assert (rel->howto != NULL);
7580 }
7581
7582 return rel;
7583}
7584
64a0c779
DN		 7585\f
7586/* Parse operands using Intel syntax. This implements a recursive descent
7587 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7588 Programmer's Guide.
7589
7590 FIXME: We do not recognize the full operand grammar defined in the MASM
7591 documentation. In particular, all the structure/union and
7592 high-level macro operands are missing.
7593
7594 Uppercase words are terminals, lower case words are non-terminals.
7595 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7596 bars '|' denote choices. Most grammar productions are implemented in
7597 functions called 'intel_<production>'.
7598
7599 Initial production is 'expr'.
7600
9306ca4a 7601 addOp + | -
64a0c779
DN		 7602
7603 alpha [a-zA-Z]
7604
9306ca4a
JB		 7605 binOp & | AND | \| | OR | ^ | XOR
7606
64a0c779
DN		 7607 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7608
7609 constant digits [[ radixOverride ]]
7610
9306ca4a 7611 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7612
7613 digits decdigit
b77a7acd
AJ		 7614 | digits decdigit
7615 | digits hexdigit
64a0c779
DN		 7616
7617 decdigit [0-9]
7618
9306ca4a
JB		 7619 e04 e04 addOp e05
7620 | e05
7621
7622 e05 e05 binOp e06
b77a7acd 7623 | e06
64a0c779
DN		 7624
7625 e06 e06 mulOp e09
b77a7acd 7626 | e09
64a0c779
DN		 7627
7628 e09 OFFSET e10
a724f0f4
JB		 7629 | SHORT e10
7630 | + e10
7631 | - e10
9306ca4a
JB		 7632 | ~ e10
7633 | NOT e10
64a0c779
DN		 7634 | e09 PTR e10
7635 | e09 : e10
7636 | e10
7637
7638 e10 e10 [ expr ]
b77a7acd 7639 | e11
64a0c779
DN		 7640
7641 e11 ( expr )
b77a7acd 7642 | [ expr ]
64a0c779
DN		 7643 | constant
7644 | dataType
7645 | id
7646 | $
7647 | register
7648
a724f0f4 7649 => expr expr cmpOp e04
9306ca4a 7650 | e04
64a0c779
DN		 7651
7652 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7653 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7654
7655 hexdigit a | b | c | d | e | f
b77a7acd 7656 | A | B | C | D | E | F
64a0c779
DN		 7657
7658 id alpha
b77a7acd 7659 | id alpha
64a0c779
DN		 7660 | id decdigit
7661
9306ca4a 7662 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7663
7664 quote " | '
7665
7666 register specialRegister
b77a7acd 7667 | gpRegister
64a0c779
DN		 7668 | byteRegister
7669
7670 segmentRegister CS | DS | ES | FS | GS | SS
7671
9306ca4a 7672 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7673 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7674 | TR3 | TR4 | TR5 | TR6 | TR7
7675
64a0c779
DN		 7676 We simplify the grammar in obvious places (e.g., register parsing is
7677 done by calling parse_register) and eliminate immediate left recursion
7678 to implement a recursive-descent parser.
7679
a724f0f4
JB		 7680 expr e04 expr'
7681
7682 expr' cmpOp e04 expr'
7683 | Empty
9306ca4a
JB		 7684
7685 e04 e05 e04'
7686
7687 e04' addOp e05 e04'
7688 | Empty
64a0c779
DN		 7689
7690 e05 e06 e05'
7691
9306ca4a 7692 e05' binOp e06 e05'
b77a7acd 7693 | Empty
64a0c779
DN		 7694
7695 e06 e09 e06'
7696
7697 e06' mulOp e09 e06'
b77a7acd 7698 | Empty
64a0c779
DN		 7699
7700 e09 OFFSET e10 e09'
a724f0f4
JB		 7701 | SHORT e10'
7702 | + e10'
7703 | - e10'
7704 | ~ e10'
7705 | NOT e10'
b77a7acd 7706 | e10 e09'
64a0c779
DN		 7707
7708 e09' PTR e10 e09'
b77a7acd 7709 | : e10 e09'
64a0c779
DN		 7710 | Empty
7711
7712 e10 e11 e10'
7713
7714 e10' [ expr ] e10'
b77a7acd 7715 | Empty
64a0c779
DN		 7716
7717 e11 ( expr )
b77a7acd 7718 | [ expr ]
64a0c779
DN		 7719 | BYTE
7720 | WORD
7721 | DWORD
9306ca4a 7722 | FWORD
64a0c779 7723 | QWORD
9306ca4a
JB		 7724 | TBYTE
7725 | OWORD
7726 | XMMWORD
64a0c779
DN		 7727 | .
7728 | $
7729 | register
7730 | id
7731 | constant */
7732
7733/* Parsing structure for the intel syntax parser. Used to implement the
7734 semantic actions for the operand grammar. */
7735struct intel_parser_s
7736 {
7737 char *op_string; /* The string being parsed. */
7738 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7739 int op_modifier; /* Operand modifier. */
64a0c779 7740 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7741 int in_offset; /* >=1 if parsing operand of offset. */
7742 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7743 const reg_entry *reg; /* Last register reference found. */
7744 char *disp; /* Displacement string being built. */
a724f0f4 7745 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7746 };
7747
7748static struct intel_parser_s intel_parser;
7749
7750/* Token structure for parsing intel syntax. */
7751struct intel_token
7752 {
7753 int code; /* Token code. */
7754 const reg_entry *reg; /* Register entry for register tokens. */
7755 char *str; /* String representation. */
7756 };
7757
7758static struct intel_token cur_token, prev_token;
7759
50705ef4
AM		 7760/* Token codes for the intel parser. Since T_SHORT is already used
7761 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7762#define T_NIL -1
7763#define T_CONST 1
7764#define T_REG 2
7765#define T_BYTE 3
7766#define T_WORD 4
9306ca4a
JB		 7767#define T_DWORD 5
7768#define T_FWORD 6
7769#define T_QWORD 7
7770#define T_TBYTE 8
7771#define T_XMMWORD 9
50705ef4 7772#undef T_SHORT
9306ca4a
JB		 7773#define T_SHORT 10
7774#define T_OFFSET 11
7775#define T_PTR 12
7776#define T_ID 13
7777#define T_SHL 14
7778#define T_SHR 15
64a0c779
DN		 7779
7780/* Prototypes for intel parser functions. */
e3bb37b5
L		 7781static int intel_match_token (int);
7782static void intel_putback_token (void);
7783static void intel_get_token (void);
7784static int intel_expr (void);
7785static int intel_e04 (void);
7786static int intel_e05 (void);
7787static int intel_e06 (void);
7788static int intel_e09 (void);
7789static int intel_e10 (void);
7790static int intel_e11 (void);
64a0c779 7791
64a0c779 7792static int
e3bb37b5 7793i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7794{
7795 int ret;
7796 char *p;
7797
a724f0f4
JB		 7798 p = intel_parser.op_string = xstrdup (operand_string);
7799 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7800
7801 for (;;)
64a0c779 7802 {
a724f0f4
JB		 7803 /* Initialize token holders. */
7804 cur_token.code = prev_token.code = T_NIL;
7805 cur_token.reg = prev_token.reg = NULL;
7806 cur_token.str = prev_token.str = NULL;
7807
7808 /* Initialize parser structure. */
7809 intel_parser.got_a_float = got_a_float;
7810 intel_parser.op_modifier = 0;
7811 intel_parser.is_mem = 0;
7812 intel_parser.in_offset = 0;
7813 intel_parser.in_bracket = 0;
7814 intel_parser.reg = NULL;
7815 intel_parser.disp[0] = '\0';
7816 intel_parser.next_operand = NULL;
7817
7818 /* Read the first token and start the parser. */
7819 intel_get_token ();
7820 ret = intel_expr ();
7821
7822 if (!ret)
7823 break;
7824
9306ca4a
JB		 7825 if (cur_token.code != T_NIL)
7826 {
7827 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7828 current_templates->start->name, cur_token.str);
7829 ret = 0;
7830 }
64a0c779
DN		 7831 /* If we found a memory reference, hand it over to i386_displacement
7832 to fill in the rest of the operand fields. */
9306ca4a 7833 else if (intel_parser.is_mem)
64a0c779
DN		 7834 {
7835 if ((i.mem_operands == 1
40fb9820 7836 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7837 || i.mem_operands == 2)
7838 {
7839 as_bad (_("too many memory references for '%s'"),
7840 current_templates->start->name);
7841 ret = 0;
7842 }
7843 else
7844 {
7845 char *s = intel_parser.disp;
7846 i.mem_operands++;
7847
a724f0f4
JB		 7848 if (!quiet_warnings && intel_parser.is_mem < 0)
7849 /* See the comments in intel_bracket_expr. */
7850 as_warn (_("Treating `%s' as memory reference"), operand_string);
7851
64a0c779
DN		 7852 /* Add the displacement expression. */
7853 if (*s != '\0')
a4622f40
AM		 7854 ret = i386_displacement (s, s + strlen (s));
7855 if (ret)
a724f0f4
JB		 7856 {
7857 /* Swap base and index in 16-bit memory operands like
7858 [si+bx]. Since i386_index_check is also used in AT&T
7859 mode we have to do that here. */
7860 if (i.base_reg
7861 && i.index_reg
40fb9820
L		 7862 && i.base_reg->reg_type.bitfield.reg16
7863 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7864 && i.base_reg->reg_num >= 6
7865 && i.index_reg->reg_num < 6)
7866 {
7867 const reg_entry *base = i.index_reg;
7868
7869 i.index_reg = i.base_reg;
7870 i.base_reg = base;
7871 }
7872 ret = i386_index_check (operand_string);
7873 }
64a0c779
DN		 7874 }
7875 }
7876
7877 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7878 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7879 || intel_parser.reg == NULL)
7880 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7881
7882 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7883 ret = 0;
a724f0f4
JB		 7884 if (!ret || !intel_parser.next_operand)
7885 break;
7886 intel_parser.op_string = intel_parser.next_operand;
7887 this_operand = i.operands++;
64a0c779
DN		 7888 }
7889
7890 free (p);
7891 free (intel_parser.disp);
7892
7893 return ret;
7894}
7895
a724f0f4
JB		 7896#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7897
7898/* expr e04 expr'
7899
7900 expr' cmpOp e04 expr'
7901 | Empty */
64a0c779 7902static int
e3bb37b5 7903intel_expr (void)
64a0c779 7904{
a724f0f4
JB		 7905 /* XXX Implement the comparison operators. */
7906 return intel_e04 ();
9306ca4a
JB		 7907}
7908
a724f0f4 7909/* e04 e05 e04'
9306ca4a 7910
a724f0f4 7911 e04' addOp e05 e04'
9306ca4a
JB		 7912 | Empty */
7913static int
e3bb37b5 7914intel_e04 (void)
9306ca4a 7915{
a724f0f4 7916 int nregs = -1;
9306ca4a 7917
a724f0f4 7918 for (;;)
9306ca4a 7919 {
a724f0f4
JB		 7920 if (!intel_e05())
7921 return 0;
9306ca4a 7922
a724f0f4
JB		 7923 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7924 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7925
a724f0f4
JB		 7926 if (cur_token.code == '+')
7927 nregs = -1;
7928 else if (cur_token.code == '-')
7929 nregs = NUM_ADDRESS_REGS;
7930 else
7931 return 1;
64a0c779 7932
a724f0f4
JB		 7933 strcat (intel_parser.disp, cur_token.str);
7934 intel_match_token (cur_token.code);
7935 }
64a0c779
DN		 7936}
7937
64a0c779
DN		 7938/* e05 e06 e05'
7939
9306ca4a 7940 e05' binOp e06 e05'
64a0c779
DN		 7941 | Empty */
7942static int
e3bb37b5 7943intel_e05 (void)
64a0c779 7944{
a724f0f4 7945 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7946
a724f0f4 7947 for (;;)
64a0c779 7948 {
a724f0f4
JB		 7949 if (!intel_e06())
7950 return 0;
7951
4eed87de
AM		 7952 if (cur_token.code == '&'
7953 || cur_token.code == '|'
7954 || cur_token.code == '^')
a724f0f4
JB		 7955 {
7956 char str[2];
7957
7958 str[0] = cur_token.code;
7959 str[1] = 0;
7960 strcat (intel_parser.disp, str);
7961 }
7962 else
7963 break;
9306ca4a 7964
64a0c779
DN		 7965 intel_match_token (cur_token.code);
7966
a724f0f4
JB		 7967 if (nregs < 0)
7968 nregs = ~nregs;
64a0c779 7969 }
a724f0f4
JB		 7970 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7971 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7972 return 1;
4a1805b1 7973}
64a0c779
DN		 7974
7975/* e06 e09 e06'
7976
7977 e06' mulOp e09 e06'
b77a7acd 7978 | Empty */
64a0c779 7979static int
e3bb37b5 7980intel_e06 (void)
64a0c779 7981{
a724f0f4 7982 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7983
a724f0f4 7984 for (;;)
64a0c779 7985 {
a724f0f4
JB		 7986 if (!intel_e09())
7987 return 0;
9306ca4a 7988
4eed87de
AM		 7989 if (cur_token.code == '*'
7990 || cur_token.code == '/'
7991 || cur_token.code == '%')
a724f0f4
JB		 7992 {
7993 char str[2];
9306ca4a 7994
a724f0f4
JB		 7995 str[0] = cur_token.code;
7996 str[1] = 0;
7997 strcat (intel_parser.disp, str);
7998 }
7999 else if (cur_token.code == T_SHL)
8000 strcat (intel_parser.disp, "<<");
8001 else if (cur_token.code == T_SHR)
8002 strcat (intel_parser.disp, ">>");
8003 else
8004 break;
9306ca4a 8005
64e74474 8006 intel_match_token (cur_token.code);
64a0c779 8007
a724f0f4
JB		 8008 if (nregs < 0)
8009 nregs = ~nregs;
64a0c779 8010 }
a724f0f4
JB		 8011 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8012 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8013 return 1;
64a0c779
DN		 8014}
8015
a724f0f4
JB		 8016/* e09 OFFSET e09
8017 | SHORT e09
8018 | + e09
8019 | - e09
8020 | ~ e09
8021 | NOT e09
9306ca4a
JB		 8022 | e10 e09'
8023
64a0c779 8024 e09' PTR e10 e09'
b77a7acd 8025 | : e10 e09'
64a0c779
DN		 8026 | Empty */
8027static int
e3bb37b5 8028intel_e09 (void)
64a0c779 8029{
a724f0f4
JB		 8030 int nregs = ~NUM_ADDRESS_REGS;
8031 int in_offset = 0;
8032
8033 for (;;)
64a0c779 8034 {
a724f0f4
JB		 8035 /* Don't consume constants here. */
8036 if (cur_token.code == '+' || cur_token.code == '-')
8037 {
8038 /* Need to look one token ahead - if the next token
8039 is a constant, the current token is its sign. */
8040 int next_code;
8041
8042 intel_match_token (cur_token.code);
8043 next_code = cur_token.code;
8044 intel_putback_token ();
8045 if (next_code == T_CONST)
8046 break;
8047 }
8048
8049 /* e09 OFFSET e09 */
8050 if (cur_token.code == T_OFFSET)
8051 {
8052 if (!in_offset++)
8053 ++intel_parser.in_offset;
8054 }
8055
8056 /* e09 SHORT e09 */
8057 else if (cur_token.code == T_SHORT)
8058 intel_parser.op_modifier |= 1 << T_SHORT;
8059
8060 /* e09 + e09 */
8061 else if (cur_token.code == '+')
8062 strcat (intel_parser.disp, "+");
8063
8064 /* e09 - e09
8065 | ~ e09
8066 | NOT e09 */
8067 else if (cur_token.code == '-' || cur_token.code == '~')
8068 {
8069 char str[2];
64a0c779 8070
a724f0f4
JB		 8071 if (nregs < 0)
8072 nregs = ~nregs;
8073 str[0] = cur_token.code;
8074 str[1] = 0;
8075 strcat (intel_parser.disp, str);
8076 }
8077
8078 /* e09 e10 e09' */
8079 else
8080 break;
8081
8082 intel_match_token (cur_token.code);
64a0c779
DN		 8083 }
8084
a724f0f4 8085 for (;;)
9306ca4a 8086 {
a724f0f4
JB		 8087 if (!intel_e10 ())
8088 return 0;
9306ca4a 8089
a724f0f4
JB		 8090 /* e09' PTR e10 e09' */
8091 if (cur_token.code == T_PTR)
8092 {
8093 char suffix;
9306ca4a 8094
a724f0f4
JB		 8095 if (prev_token.code == T_BYTE)
8096 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 8097
a724f0f4
JB		 8098 else if (prev_token.code == T_WORD)
8099 {
8100 if (current_templates->start->name[0] == 'l'
8101 && current_templates->start->name[2] == 's'
8102 && current_templates->start->name[3] == 0)
8103 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8104 else if (intel_parser.got_a_float == 2) /* "fi..." */
8105 suffix = SHORT_MNEM_SUFFIX;
8106 else
8107 suffix = WORD_MNEM_SUFFIX;
8108 }
64a0c779 8109
a724f0f4
JB		 8110 else if (prev_token.code == T_DWORD)
8111 {
8112 if (current_templates->start->name[0] == 'l'
8113 && current_templates->start->name[2] == 's'
8114 && current_templates->start->name[3] == 0)
8115 suffix = WORD_MNEM_SUFFIX;
8116 else if (flag_code == CODE_16BIT
40fb9820
L		 8117 && (current_templates->start->opcode_modifier.jump
8118 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8119 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8120 else if (intel_parser.got_a_float == 1) /* "f..." */
8121 suffix = SHORT_MNEM_SUFFIX;
8122 else
8123 suffix = LONG_MNEM_SUFFIX;
8124 }
9306ca4a 8125
a724f0f4
JB		 8126 else if (prev_token.code == T_FWORD)
8127 {
8128 if (current_templates->start->name[0] == 'l'
8129 && current_templates->start->name[2] == 's'
8130 && current_templates->start->name[3] == 0)
8131 suffix = LONG_MNEM_SUFFIX;
8132 else if (!intel_parser.got_a_float)
8133 {
8134 if (flag_code == CODE_16BIT)
8135 add_prefix (DATA_PREFIX_OPCODE);
8136 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8137 }
8138 else
8139 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8140 }
64a0c779 8141
a724f0f4
JB		 8142 else if (prev_token.code == T_QWORD)
8143 {
8144 if (intel_parser.got_a_float == 1) /* "f..." */
8145 suffix = LONG_MNEM_SUFFIX;
8146 else
8147 suffix = QWORD_MNEM_SUFFIX;
8148 }
64a0c779 8149
a724f0f4
JB		 8150 else if (prev_token.code == T_TBYTE)
8151 {
8152 if (intel_parser.got_a_float == 1)
8153 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8154 else
8155 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8156 }
9306ca4a 8157
a724f0f4 8158 else if (prev_token.code == T_XMMWORD)
9306ca4a 8159 {
a724f0f4
JB		 8160 /* XXX ignored for now, but accepted since gcc uses it */
8161 suffix = 0;
9306ca4a 8162 }
64a0c779 8163
f16b83df 8164 else
a724f0f4
JB		 8165 {
8166 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8167 return 0;
8168 }
8169
435acd52
JB		 8170 /* Operands for jump/call using 'ptr' notation denote absolute
8171 addresses. */
40fb9820
L		 8172 if (current_templates->start->opcode_modifier.jump
8173 || current_templates->start->opcode_modifier.jumpdword)
8174 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8175
a724f0f4
JB		 8176 if (current_templates->start->base_opcode == 0x8d /* lea */)
8177 ;
8178 else if (!i.suffix)
8179 i.suffix = suffix;
8180 else if (i.suffix != suffix)
8181 {
8182 as_bad (_("Conflicting operand modifiers"));
8183 return 0;
8184 }
64a0c779 8185
9306ca4a
JB		 8186 }
8187
a724f0f4
JB		 8188 /* e09' : e10 e09' */
8189 else if (cur_token.code == ':')
9306ca4a 8190 {
a724f0f4
JB		 8191 if (prev_token.code != T_REG)
8192 {
8193 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8194 segment/group identifier (which we don't have), using comma
8195 as the operand separator there is even less consistent, since
8196 there all branches only have a single operand. */
8197 if (this_operand != 0
8198 || intel_parser.in_offset
8199 || intel_parser.in_bracket
40fb9820
L		 8200 || (!current_templates->start->opcode_modifier.jump
8201 && !current_templates->start->opcode_modifier.jumpdword
8202 && !current_templates->start->opcode_modifier.jumpintersegment
8203 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8204 return intel_match_token (T_NIL);
8205 /* Remember the start of the 2nd operand and terminate 1st
8206 operand here.
8207 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8208 another expression), but it gets at least the simplest case
8209 (a plain number or symbol on the left side) right. */
8210 intel_parser.next_operand = intel_parser.op_string;
8211 *--intel_parser.op_string = '\0';
8212 return intel_match_token (':');
8213 }
9306ca4a 8214 }
64a0c779 8215
a724f0f4 8216 /* e09' Empty */
64a0c779 8217 else
a724f0f4 8218 break;
64a0c779 8219
a724f0f4
JB		 8220 intel_match_token (cur_token.code);
8221
8222 }
8223
8224 if (in_offset)
8225 {
8226 --intel_parser.in_offset;
8227 if (nregs < 0)
8228 nregs = ~nregs;
8229 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8230 {
a724f0f4 8231 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8232 return 0;
8233 }
a724f0f4
JB		 8234 intel_parser.op_modifier |= 1 << T_OFFSET;
8235 }
9306ca4a 8236
a724f0f4
JB		 8237 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8238 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8239 return 1;
8240}
64a0c779 8241
a724f0f4 8242static int
e3bb37b5 8243intel_bracket_expr (void)
a724f0f4
JB		 8244{
8245 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8246 const char *start = intel_parser.op_string;
8247 int len;
8248
8249 if (i.op[this_operand].regs)
8250 return intel_match_token (T_NIL);
8251
8252 intel_match_token ('[');
8253
8254 /* Mark as a memory operand only if it's not already known to be an
8255 offset expression. If it's an offset expression, we need to keep
8256 the brace in. */
8257 if (!intel_parser.in_offset)
8258 {
8259 ++intel_parser.in_bracket;
435acd52
JB		 8260
8261 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8262 if (current_templates->start->opcode_modifier.jump
8263 || current_templates->start->opcode_modifier.jumpdword)
8264 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8265
a724f0f4
JB		 8266 /* Unfortunately gas always diverged from MASM in a respect that can't
8267 be easily fixed without risking to break code sequences likely to be
8268 encountered (the testsuite even check for this): MASM doesn't consider
8269 an expression inside brackets unconditionally as a memory reference.
8270 When that is e.g. a constant, an offset expression, or the sum of the
8271 two, this is still taken as a constant load. gas, however, always
8272 treated these as memory references. As a compromise, we'll try to make
8273 offset expressions inside brackets work the MASM way (since that's
8274 less likely to be found in real world code), but make constants alone
8275 continue to work the traditional gas way. In either case, issue a
8276 warning. */
8277 intel_parser.op_modifier &= ~was_offset;
64a0c779 8278 }
a724f0f4 8279 else
64e74474 8280 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8281
8282 /* Add a '+' to the displacement string if necessary. */
8283 if (*intel_parser.disp != '\0'
8284 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8285 strcat (intel_parser.disp, "+");
64a0c779 8286
a724f0f4
JB		 8287 if (intel_expr ()
8288 && (len = intel_parser.op_string - start - 1,
8289 intel_match_token (']')))
64a0c779 8290 {
a724f0f4
JB		 8291 /* Preserve brackets when the operand is an offset expression. */
8292 if (intel_parser.in_offset)
8293 strcat (intel_parser.disp, "]");
8294 else
8295 {
8296 --intel_parser.in_bracket;
8297 if (i.base_reg || i.index_reg)
8298 intel_parser.is_mem = 1;
8299 if (!intel_parser.is_mem)
8300 {
8301 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8302 /* Defer the warning until all of the operand was parsed. */
8303 intel_parser.is_mem = -1;
8304 else if (!quiet_warnings)
4eed87de
AM		 8305 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8306 len, start, len, start);
a724f0f4
JB		 8307 }
8308 }
8309 intel_parser.op_modifier |= was_offset;
64a0c779 8310
a724f0f4 8311 return 1;
64a0c779 8312 }
a724f0f4 8313 return 0;
64a0c779
DN		 8314}
8315
8316/* e10 e11 e10'
8317
8318 e10' [ expr ] e10'
b77a7acd 8319 | Empty */
64a0c779 8320static int
e3bb37b5 8321intel_e10 (void)
64a0c779 8322{
a724f0f4
JB		 8323 if (!intel_e11 ())
8324 return 0;
64a0c779 8325
a724f0f4 8326 while (cur_token.code == '[')
64a0c779 8327 {
a724f0f4 8328 if (!intel_bracket_expr ())
21d6c4af 8329 return 0;
64a0c779
DN		 8330 }
8331
a724f0f4 8332 return 1;
64a0c779
DN		 8333}
8334
64a0c779 8335/* e11 ( expr )
b77a7acd 8336 | [ expr ]
64a0c779
DN		 8337 | BYTE
8338 | WORD
8339 | DWORD
9306ca4a 8340 | FWORD
64a0c779 8341 | QWORD
9306ca4a
JB		 8342 | TBYTE
8343 | OWORD
8344 | XMMWORD
4a1805b1 8345 | $
64a0c779
DN		 8346 | .
8347 | register
8348 | id
8349 | constant */
8350static int
e3bb37b5 8351intel_e11 (void)
64a0c779 8352{
a724f0f4 8353 switch (cur_token.code)
64a0c779 8354 {
a724f0f4
JB		 8355 /* e11 ( expr ) */
8356 case '(':
64a0c779
DN		 8357 intel_match_token ('(');
8358 strcat (intel_parser.disp, "(");
8359
8360 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8361 {
8362 strcat (intel_parser.disp, ")");
8363 return 1;
8364 }
a724f0f4 8365 return 0;
4a1805b1 8366
a724f0f4
JB		 8367 /* e11 [ expr ] */
8368 case '[':
a724f0f4 8369 return intel_bracket_expr ();
64a0c779 8370
a724f0f4
JB		 8371 /* e11 $
8372 | . */
8373 case '.':
64a0c779
DN		 8374 strcat (intel_parser.disp, cur_token.str);
8375 intel_match_token (cur_token.code);
21d6c4af
DN		 8376
8377 /* Mark as a memory operand only if it's not already known to be an
8378 offset expression. */
a724f0f4 8379 if (!intel_parser.in_offset)
21d6c4af 8380 intel_parser.is_mem = 1;
64a0c779
DN		 8381
8382 return 1;
64a0c779 8383
a724f0f4
JB		 8384 /* e11 register */
8385 case T_REG:
8386 {
8387 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8388
a724f0f4 8389 intel_match_token (T_REG);
64a0c779 8390
a724f0f4
JB		 8391 /* Check for segment change. */
8392 if (cur_token.code == ':')
8393 {
40fb9820
L		 8394 if (!reg->reg_type.bitfield.sreg2
8395 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8396 {
4eed87de
AM		 8397 as_bad (_("`%s' is not a valid segment register"),
8398 reg->reg_name);
a724f0f4
JB		 8399 return 0;
8400 }
8401 else if (i.seg[i.mem_operands])
8402 as_warn (_("Extra segment override ignored"));
8403 else
8404 {
8405 if (!intel_parser.in_offset)
8406 intel_parser.is_mem = 1;
8407 switch (reg->reg_num)
8408 {
8409 case 0:
8410 i.seg[i.mem_operands] = &es;
8411 break;
8412 case 1:
8413 i.seg[i.mem_operands] = &cs;
8414 break;
8415 case 2:
8416 i.seg[i.mem_operands] = &ss;
8417 break;
8418 case 3:
8419 i.seg[i.mem_operands] = &ds;
8420 break;
8421 case 4:
8422 i.seg[i.mem_operands] = &fs;
8423 break;
8424 case 5:
8425 i.seg[i.mem_operands] = &gs;
8426 break;
8427 }
8428 }
8429 }
64a0c779 8430
a724f0f4
JB		 8431 /* Not a segment register. Check for register scaling. */
8432 else if (cur_token.code == '*')
8433 {
8434 if (!intel_parser.in_bracket)
8435 {
8436 as_bad (_("Register scaling only allowed in memory operands"));
8437 return 0;
8438 }
64a0c779 8439
40fb9820 8440 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8441 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8442 else if (i.index_reg)
8443 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8444
a724f0f4
JB		 8445 /* What follows must be a valid scale. */
8446 intel_match_token ('*');
8447 i.index_reg = reg;
40fb9820 8448 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8449
a724f0f4
JB		 8450 /* Set the scale after setting the register (otherwise,
8451 i386_scale will complain) */
8452 if (cur_token.code == '+' || cur_token.code == '-')
8453 {
8454 char *str, sign = cur_token.code;
8455 intel_match_token (cur_token.code);
8456 if (cur_token.code != T_CONST)
8457 {
8458 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8459 cur_token.str);
8460 return 0;
8461 }
8462 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8463 strcpy (str + 1, cur_token.str);
8464 *str = sign;
8465 if (!i386_scale (str))
8466 return 0;
8467 free (str);
8468 }
8469 else if (!i386_scale (cur_token.str))
64a0c779 8470 return 0;
a724f0f4
JB		 8471 intel_match_token (cur_token.code);
8472 }
64a0c779 8473
a724f0f4
JB		 8474 /* No scaling. If this is a memory operand, the register is either a
8475 base register (first occurrence) or an index register (second
8476 occurrence). */
7b0441f6 8477 else if (intel_parser.in_bracket)
a724f0f4 8478 {
64a0c779 8479
a724f0f4
JB		 8480 if (!i.base_reg)
8481 i.base_reg = reg;
8482 else if (!i.index_reg)
8483 i.index_reg = reg;
8484 else
8485 {
8486 as_bad (_("Too many register references in memory operand"));
8487 return 0;
8488 }
64a0c779 8489
40fb9820 8490 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8491 }
4a1805b1 8492
4d1bb795
JB		 8493 /* It's neither base nor index. */
8494 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8495 {
40fb9820
L		 8496 i386_operand_type temp = reg->reg_type;
8497 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8498 i.types[this_operand] = operand_type_or (i.types[this_operand],
8499 temp);
a724f0f4
JB		 8500 i.op[this_operand].regs = reg;
8501 i.reg_operands++;
8502 }
8503 else
8504 {
8505 as_bad (_("Invalid use of register"));
8506 return 0;
8507 }
64a0c779 8508
a724f0f4
JB		 8509 /* Since registers are not part of the displacement string (except
8510 when we're parsing offset operands), we may need to remove any
8511 preceding '+' from the displacement string. */
8512 if (*intel_parser.disp != '\0'
8513 && !intel_parser.in_offset)
8514 {
8515 char *s = intel_parser.disp;
8516 s += strlen (s) - 1;
8517 if (*s == '+')
8518 *s = '\0';
8519 }
4a1805b1 8520
a724f0f4
JB		 8521 return 1;
8522 }
8523
8524 /* e11 BYTE
8525 | WORD
8526 | DWORD
8527 | FWORD
8528 | QWORD
8529 | TBYTE
8530 | OWORD
8531 | XMMWORD */
8532 case T_BYTE:
8533 case T_WORD:
8534 case T_DWORD:
8535 case T_FWORD:
8536 case T_QWORD:
8537 case T_TBYTE:
8538 case T_XMMWORD:
8539 intel_match_token (cur_token.code);
64a0c779 8540
a724f0f4
JB		 8541 if (cur_token.code == T_PTR)
8542 return 1;
8543
8544 /* It must have been an identifier. */
8545 intel_putback_token ();
8546 cur_token.code = T_ID;
8547 /* FALLTHRU */
8548
8549 /* e11 id
8550 | constant */
8551 case T_ID:
8552 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8553 {
8554 symbolS *symbolP;
8555
a724f0f4
JB		 8556 /* The identifier represents a memory reference only if it's not
8557 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8558 symbolP = symbol_find(cur_token.str);
8559 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8560 intel_parser.is_mem = 1;
8561 }
a724f0f4 8562 /* FALLTHRU */
64a0c779 8563
a724f0f4
JB		 8564 case T_CONST:
8565 case '-':
8566 case '+':
8567 {
8568 char *save_str, sign = 0;
64a0c779 8569
a724f0f4
JB		 8570 /* Allow constants that start with `+' or `-'. */
8571 if (cur_token.code == '-' || cur_token.code == '+')
8572 {
8573 sign = cur_token.code;
8574 intel_match_token (cur_token.code);
8575 if (cur_token.code != T_CONST)
8576 {
8577 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8578 cur_token.str);
8579 return 0;
8580 }
8581 }
64a0c779 8582
a724f0f4
JB		 8583 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8584 strcpy (save_str + !!sign, cur_token.str);
8585 if (sign)
8586 *save_str = sign;
64a0c779 8587
a724f0f4
JB		 8588 /* Get the next token to check for register scaling. */
8589 intel_match_token (cur_token.code);
64a0c779 8590
4eed87de
AM		 8591 /* Check if this constant is a scaling factor for an
8592 index register. */
a724f0f4
JB		 8593 if (cur_token.code == '*')
8594 {
8595 if (intel_match_token ('*') && cur_token.code == T_REG)
8596 {
8597 const reg_entry *reg = cur_token.reg;
8598
8599 if (!intel_parser.in_bracket)
8600 {
4eed87de
AM		 8601 as_bad (_("Register scaling only allowed "
8602 "in memory operands"));
a724f0f4
JB		 8603 return 0;
8604 }
8605
4eed87de
AM		 8606 /* Disallow things like [1*si].
8607 sp and esp are invalid as index. */
40fb9820 8608 if (reg->reg_type.bitfield.reg16)
4eed87de 8609 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8610 else if (i.index_reg)
4eed87de 8611 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8612
8613 /* The constant is followed by `* reg', so it must be
8614 a valid scale. */
8615 i.index_reg = reg;
40fb9820 8616 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8617
8618 /* Set the scale after setting the register (otherwise,
8619 i386_scale will complain) */
8620 if (!i386_scale (save_str))
64a0c779 8621 return 0;
a724f0f4
JB		 8622 intel_match_token (T_REG);
8623
8624 /* Since registers are not part of the displacement
8625 string, we may need to remove any preceding '+' from
8626 the displacement string. */
8627 if (*intel_parser.disp != '\0')
8628 {
8629 char *s = intel_parser.disp;
8630 s += strlen (s) - 1;
8631 if (*s == '+')
8632 *s = '\0';
8633 }
8634
8635 free (save_str);
8636
8637 return 1;
8638 }
64a0c779 8639
a724f0f4
JB		 8640 /* The constant was not used for register scaling. Since we have
8641 already consumed the token following `*' we now need to put it
8642 back in the stream. */
64a0c779 8643 intel_putback_token ();
a724f0f4 8644 }
64a0c779 8645
a724f0f4
JB		 8646 /* Add the constant to the displacement string. */
8647 strcat (intel_parser.disp, save_str);
8648 free (save_str);
64a0c779 8649
a724f0f4
JB		 8650 return 1;
8651 }
64a0c779
DN		 8652 }
8653
64a0c779
DN		 8654 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8655 return 0;
8656}
8657
64a0c779
DN		 8658/* Match the given token against cur_token. If they match, read the next
8659 token from the operand string. */
8660static int
e3bb37b5 8661intel_match_token (int code)
64a0c779
DN		 8662{
8663 if (cur_token.code == code)
8664 {
8665 intel_get_token ();
8666 return 1;
8667 }
8668 else
8669 {
0477af35 8670 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8671 return 0;
8672 }
8673}
8674
64a0c779
DN		 8675/* Read a new token from intel_parser.op_string and store it in cur_token. */
8676static void
e3bb37b5 8677intel_get_token (void)
64a0c779
DN		 8678{
8679 char *end_op;
8680 const reg_entry *reg;
8681 struct intel_token new_token;
8682
8683 new_token.code = T_NIL;
8684 new_token.reg = NULL;
8685 new_token.str = NULL;
8686
4a1805b1 8687 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8688 cur_token to prev_token. */
8689 if (prev_token.str)
8690 free (prev_token.str);
8691
8692 prev_token = cur_token;
8693
8694 /* Skip whitespace. */
8695 while (is_space_char (*intel_parser.op_string))
8696 intel_parser.op_string++;
8697
8698 /* Return an empty token if we find nothing else on the line. */
8699 if (*intel_parser.op_string == '\0')
8700 {
8701 cur_token = new_token;
8702 return;
8703 }
8704
8705 /* The new token cannot be larger than the remainder of the operand
8706 string. */
a724f0f4 8707 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8708 new_token.str[0] = '\0';
8709
8710 if (strchr ("0123456789", *intel_parser.op_string))
8711 {
8712 char *p = new_token.str;
8713 char *q = intel_parser.op_string;
8714 new_token.code = T_CONST;
8715
8716 /* Allow any kind of identifier char to encompass floating point and
8717 hexadecimal numbers. */
8718 while (is_identifier_char (*q))
8719 *p++ = *q++;
8720 *p = '\0';
8721
8722 /* Recognize special symbol names [0-9][bf]. */
8723 if (strlen (intel_parser.op_string) == 2
4a1805b1 8724 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8725 || intel_parser.op_string[1] == 'f'))
8726 new_token.code = T_ID;
8727 }
8728
4d1bb795 8729 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8730 {
4d1bb795
JB		 8731 size_t len = end_op - intel_parser.op_string;
8732
64a0c779
DN		 8733 new_token.code = T_REG;
8734 new_token.reg = reg;
8735
4d1bb795
JB		 8736 memcpy (new_token.str, intel_parser.op_string, len);
8737 new_token.str[len] = '\0';
64a0c779
DN		 8738 }
8739
8740 else if (is_identifier_char (*intel_parser.op_string))
8741 {
8742 char *p = new_token.str;
8743 char *q = intel_parser.op_string;
8744
8745 /* A '.' or '$' followed by an identifier char is an identifier.
8746 Otherwise, it's operator '.' followed by an expression. */
8747 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8748 {
9306ca4a
JB		 8749 new_token.code = '.';
8750 new_token.str[0] = '.';
64a0c779
DN		 8751 new_token.str[1] = '\0';
8752 }
8753 else
8754 {
8755 while (is_identifier_char (*q) || *q == '@')
8756 *p++ = *q++;
8757 *p = '\0';
8758
9306ca4a
JB		 8759 if (strcasecmp (new_token.str, "NOT") == 0)
8760 new_token.code = '~';
8761
8762 else if (strcasecmp (new_token.str, "MOD") == 0)
8763 new_token.code = '%';
8764
8765 else if (strcasecmp (new_token.str, "AND") == 0)
8766 new_token.code = '&';
8767
8768 else if (strcasecmp (new_token.str, "OR") == 0)
8769 new_token.code = '|';
8770
8771 else if (strcasecmp (new_token.str, "XOR") == 0)
8772 new_token.code = '^';
8773
8774 else if (strcasecmp (new_token.str, "SHL") == 0)
8775 new_token.code = T_SHL;
8776
8777 else if (strcasecmp (new_token.str, "SHR") == 0)
8778 new_token.code = T_SHR;
8779
8780 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8781 new_token.code = T_BYTE;
8782
8783 else if (strcasecmp (new_token.str, "WORD") == 0)
8784 new_token.code = T_WORD;
8785
8786 else if (strcasecmp (new_token.str, "DWORD") == 0)
8787 new_token.code = T_DWORD;
8788
9306ca4a
JB		 8789 else if (strcasecmp (new_token.str, "FWORD") == 0)
8790 new_token.code = T_FWORD;
8791
64a0c779
DN		 8792 else if (strcasecmp (new_token.str, "QWORD") == 0)
8793 new_token.code = T_QWORD;
8794
9306ca4a
JB		 8795 else if (strcasecmp (new_token.str, "TBYTE") == 0
8796 /* XXX remove (gcc still uses it) */
8797 || strcasecmp (new_token.str, "XWORD") == 0)
8798 new_token.code = T_TBYTE;
8799
8800 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8801 || strcasecmp (new_token.str, "OWORD") == 0)
8802 new_token.code = T_XMMWORD;
64a0c779
DN		 8803
8804 else if (strcasecmp (new_token.str, "PTR") == 0)
8805 new_token.code = T_PTR;
8806
8807 else if (strcasecmp (new_token.str, "SHORT") == 0)
8808 new_token.code = T_SHORT;
8809
8810 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8811 {
8812 new_token.code = T_OFFSET;
8813
8814 /* ??? This is not mentioned in the MASM grammar but gcc
8815 makes use of it with -mintel-syntax. OFFSET may be
8816 followed by FLAT: */
8817 if (strncasecmp (q, " FLAT:", 6) == 0)
8818 strcat (new_token.str, " FLAT:");
8819 }
8820
8821 /* ??? This is not mentioned in the MASM grammar. */
8822 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8823 {
8824 new_token.code = T_OFFSET;
8825 if (*q == ':')
8826 strcat (new_token.str, ":");
8827 else
8828 as_bad (_("`:' expected"));
8829 }
64a0c779
DN		 8830
8831 else
8832 new_token.code = T_ID;
8833 }
8834 }
8835
9306ca4a
JB		 8836 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8837 {
8838 new_token.code = *intel_parser.op_string;
8839 new_token.str[0] = *intel_parser.op_string;
8840 new_token.str[1] = '\0';
8841 }
8842
8843 else if (strchr ("<>", *intel_parser.op_string)
8844 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8845 {
8846 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8847 new_token.str[0] = *intel_parser.op_string;
8848 new_token.str[1] = *intel_parser.op_string;
8849 new_token.str[2] = '\0';
8850 }
8851
64a0c779 8852 else
0477af35 8853 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8854
8855 intel_parser.op_string += strlen (new_token.str);
8856 cur_token = new_token;
8857}
8858
64a0c779
DN		 8859/* Put cur_token back into the token stream and make cur_token point to
8860 prev_token. */
8861static void
e3bb37b5 8862intel_putback_token (void)
64a0c779 8863{
a724f0f4
JB		 8864 if (cur_token.code != T_NIL)
8865 {
8866 intel_parser.op_string -= strlen (cur_token.str);
8867 free (cur_token.str);
8868 }
64a0c779 8869 cur_token = prev_token;
4a1805b1 8870
64a0c779
DN		 8871 /* Forget prev_token. */
8872 prev_token.code = T_NIL;
8873 prev_token.reg = NULL;
8874 prev_token.str = NULL;
8875}
54cfded0 8876
a4447b93 8877int
1df69f4f 8878tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8879{
8880 unsigned int regnum;
8881 unsigned int regnames_count;
089dfecd 8882 static const char *const regnames_32[] =
54cfded0 8883 {
a4447b93
RH		 8884 "eax", "ecx", "edx", "ebx",
8885 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8886 "eip", "eflags", NULL,
8887 "st0", "st1", "st2", "st3",
8888 "st4", "st5", "st6", "st7",
8889 NULL, NULL,
8890 "xmm0", "xmm1", "xmm2", "xmm3",
8891 "xmm4", "xmm5", "xmm6", "xmm7",
8892 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8893 "mm4", "mm5", "mm6", "mm7",
8894 "fcw", "fsw", "mxcsr",
8895 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8896 "tr", "ldtr"
54cfded0 8897 };
089dfecd 8898 static const char *const regnames_64[] =
54cfded0 8899 {
089dfecd
JB		 8900 "rax", "rdx", "rcx", "rbx",
8901 "rsi", "rdi", "rbp", "rsp",
8902 "r8", "r9", "r10", "r11",
54cfded0 8903 "r12", "r13", "r14", "r15",
089dfecd
JB		 8904 "rip",
8905 "xmm0", "xmm1", "xmm2", "xmm3",
8906 "xmm4", "xmm5", "xmm6", "xmm7",
8907 "xmm8", "xmm9", "xmm10", "xmm11",
8908 "xmm12", "xmm13", "xmm14", "xmm15",
8909 "st0", "st1", "st2", "st3",
8910 "st4", "st5", "st6", "st7",
8911 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8912 "mm4", "mm5", "mm6", "mm7",
8913 "rflags",
8914 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8915 "fs.base", "gs.base", NULL, NULL,
8916 "tr", "ldtr",
8917 "mxcsr", "fcw", "fsw"
54cfded0 8918 };
089dfecd 8919 const char *const *regnames;
54cfded0
AM		 8920
8921 if (flag_code == CODE_64BIT)
8922 {
8923 regnames = regnames_64;
0cea6190 8924 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8925 }
8926 else
8927 {
8928 regnames = regnames_32;
0cea6190 8929 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8930 }
8931
8932 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8933 if (regnames[regnum] != NULL
8934 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8935 return regnum;
8936
54cfded0
AM		 8937 return -1;
8938}
8939
8940void
8941tc_x86_frame_initial_instructions (void)
8942{
a4447b93
RH		 8943 static unsigned int sp_regno;
8944
8945 if (!sp_regno)
8946 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8947 ? "rsp" : "esp");
8948
8949 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8950 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8951}
d2b2c203
DJ		 8952
8953int
8954i386_elf_section_type (const char *str, size_t len)
8955{
8956 if (flag_code == CODE_64BIT
8957 && len == sizeof ("unwind") - 1
8958 && strncmp (str, "unwind", 6) == 0)
8959 return SHT_X86_64_UNWIND;
8960
8961 return -1;
8962}
bb41ade5
AM		 8963
8964#ifdef TE_PE
8965void
8966tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8967{
8968 expressionS expr;
8969
8970 expr.X_op = O_secrel;
8971 expr.X_add_symbol = symbol;
8972 expr.X_add_number = 0;
8973 emit_expr (&expr, size);
8974}
8975#endif
3b22753a
L		 8976
8977#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8978/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8979
8980int
8981x86_64_section_letter (int letter, char **ptr_msg)
8982{
8983 if (flag_code == CODE_64BIT)
8984 {
8985 if (letter == 'l')
8986 return SHF_X86_64_LARGE;
8987
8988 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8989 }
3b22753a 8990 else
64e74474 8991 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8992 return -1;
8993}
8994
8995int
8996x86_64_section_word (char *str, size_t len)
8997{
8620418b 8998 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8999 return SHF_X86_64_LARGE;
9000
9001 return -1;
9002}
9003
9004static void
9005handle_large_common (int small ATTRIBUTE_UNUSED)
9006{
9007 if (flag_code != CODE_64BIT)
9008 {
9009 s_comm_internal (0, elf_common_parse);
9010 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9011 }
9012 else
9013 {
9014 static segT lbss_section;
9015 asection *saved_com_section_ptr = elf_com_section_ptr;
9016 asection *saved_bss_section = bss_section;
9017
9018 if (lbss_section == NULL)
9019 {
9020 flagword applicable;
9021 segT seg = now_seg;
9022 subsegT subseg = now_subseg;
9023
9024 /* The .lbss section is for local .largecomm symbols. */
9025 lbss_section = subseg_new (".lbss", 0);
9026 applicable = bfd_applicable_section_flags (stdoutput);
9027 bfd_set_section_flags (stdoutput, lbss_section,
9028 applicable & SEC_ALLOC);
9029 seg_info (lbss_section)->bss = 1;
9030
9031 subseg_set (seg, subseg);
9032 }
9033
9034 elf_com_section_ptr = &_bfd_elf_large_com_section;
9035 bss_section = lbss_section;
9036
9037 s_comm_internal (0, elf_common_parse);
9038
9039 elf_com_section_ptr = saved_com_section_ptr;
9040 bss_section = saved_bss_section;
9041 }
9042}
9043#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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