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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
fd67aa11 | 2 | Copyright (C) 1989-2024 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
c7defc53 | 33 | #include "scfi.h" |
b52c4ee4 IB |
34 | #include "gen-sframe.h" |
35 | #include "sframe.h" | |
d2b2c203 | 36 | #include "elf/x86-64.h" |
40fb9820 | 37 | #include "opcodes/i386-init.h" |
5c139202 | 38 | #include "opcodes/i386-mnem.h" |
41fd2579 | 39 | #include <limits.h> |
41fd2579 | 40 | |
c3332e24 | 41 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 42 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
43 | #endif |
44 | ||
29b0f896 AM |
45 | #ifndef DEFAULT_ARCH |
46 | #define DEFAULT_ARCH "i386" | |
246fcdee | 47 | #endif |
252b5132 | 48 | |
edde18a5 AM |
49 | #ifndef INLINE |
50 | #if __GNUC__ >= 2 | |
51 | #define INLINE __inline__ | |
52 | #else | |
53 | #define INLINE | |
54 | #endif | |
55 | #endif | |
56 | ||
6305a203 L |
57 | /* Prefixes will be emitted in the order defined below. |
58 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
59 | instruction, and so must come before any prefixes. | |
60 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 61 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
62 | #define WAIT_PREFIX 0 |
63 | #define SEG_PREFIX 1 | |
64 | #define ADDR_PREFIX 2 | |
65 | #define DATA_PREFIX 3 | |
c32fa91d | 66 | #define REP_PREFIX 4 |
42164a71 | 67 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 68 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 69 | #define LOCK_PREFIX 5 |
4e9ac44a L |
70 | #define REX_PREFIX 6 /* must come last. */ |
71 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
72 | |
73 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
74 | #define REGISTER_PREFIX '%' | |
75 | #define IMMEDIATE_PREFIX '$' | |
76 | #define ABSOLUTE_PREFIX '*' | |
77 | ||
78 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
79 | memory operand size in Intel syntax. */ | |
80 | #define WORD_MNEM_SUFFIX 'w' | |
81 | #define BYTE_MNEM_SUFFIX 'b' | |
82 | #define SHORT_MNEM_SUFFIX 's' | |
83 | #define LONG_MNEM_SUFFIX 'l' | |
84 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
85 | |
86 | #define END_OF_INSN '\0' | |
87 | ||
05909f23 JB |
88 | #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } } |
89 | ||
79dec6b7 JB |
90 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
91 | #define commutative staticrounding | |
92 | ||
6305a203 L |
93 | /* |
94 | 'templates' is for grouping together 'template' structures for opcodes | |
95 | of the same name. This is only used for storing the insns in the grand | |
96 | ole hash table of insns. | |
97 | The templates themselves start at START and range up to (but not including) | |
98 | END. | |
99 | */ | |
100 | typedef struct | |
101 | { | |
d3ce72d0 NC |
102 | const insn_template *start; |
103 | const insn_template *end; | |
6305a203 L |
104 | } |
105 | templates; | |
106 | ||
107 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
108 | typedef struct | |
109 | { | |
110 | unsigned int regmem; /* codes register or memory operand */ | |
111 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
112 | unsigned int mode; /* how to interpret regmem & reg */ | |
113 | } | |
114 | modrm_byte; | |
115 | ||
116 | /* x86-64 extension prefix. */ | |
117 | typedef int rex_byte; | |
118 | ||
6305a203 L |
119 | /* 386 opcode byte to code indirect addressing. */ |
120 | typedef struct | |
121 | { | |
122 | unsigned base; | |
123 | unsigned index; | |
124 | unsigned scale; | |
125 | } | |
126 | sib_byte; | |
127 | ||
6305a203 L |
128 | /* x86 arch names, types and features */ |
129 | typedef struct | |
130 | { | |
131 | const char *name; /* arch name */ | |
6ceeed25 JB |
132 | unsigned int len:8; /* arch string length */ |
133 | bool skip:1; /* show_arch should skip this. */ | |
6305a203 | 134 | enum processor_type type; /* arch type */ |
4fc85f37 | 135 | enum { vsz_none, vsz_set, vsz_reset } vsz; /* vector size control */ |
ae89daec JB |
136 | i386_cpu_flags enable; /* cpu feature enable flags */ |
137 | i386_cpu_flags disable; /* cpu feature disable flags */ | |
6305a203 L |
138 | } |
139 | arch_entry; | |
140 | ||
78f12dd3 | 141 | static void update_code_flag (int, int); |
edd67638 | 142 | static void s_insn (int); |
1e7dd4a0 | 143 | static void s_noopt (int); |
e3bb37b5 L |
144 | static void set_code_flag (int); |
145 | static void set_16bit_gcc_code_flag (int); | |
146 | static void set_intel_syntax (int); | |
1efbbeb4 | 147 | static void set_intel_mnemonic (int); |
db51cc60 | 148 | static void set_allow_index_reg (int); |
7bab8ab5 | 149 | static void set_check (int); |
e3bb37b5 | 150 | static void set_cpu_arch (int); |
6482c264 | 151 | #ifdef TE_PE |
e3bb37b5 | 152 | static void pe_directive_secrel (int); |
145667f8 | 153 | static void pe_directive_secidx (int); |
6482c264 | 154 | #endif |
e3bb37b5 L |
155 | static void signed_cons (int); |
156 | static char *output_invalid (int c); | |
ee86248c JB |
157 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
158 | const char *); | |
159 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
160 | const char *); | |
a7619375 | 161 | static int i386_att_operand (char *); |
e3bb37b5 | 162 | static int i386_intel_operand (char *, int); |
ee86248c JB |
163 | static int i386_intel_simplify (expressionS *); |
164 | static int i386_intel_parse_name (const char *, expressionS *); | |
4f081312 | 165 | static const reg_entry *parse_register (const char *, char **); |
edd67638 | 166 | static const char *parse_insn (const char *, char *, bool); |
e3bb37b5 L |
167 | static char *parse_operands (char *, const char *); |
168 | static void swap_operands (void); | |
783c187b | 169 | static void swap_2_operands (unsigned int, unsigned int); |
ed719294 | 170 | static enum i386_flag_code i386_addressing_mode (void); |
e3bb37b5 | 171 | static void optimize_imm (void); |
0de704b9 | 172 | static bool optimize_disp (const insn_template *t); |
83b16ac6 | 173 | static const insn_template *match_template (char); |
e3bb37b5 | 174 | static int check_string (void); |
acd86c81 | 175 | static int process_suffix (const insn_template *); |
e3bb37b5 L |
176 | static int check_byte_reg (void); |
177 | static int check_long_reg (void); | |
178 | static int check_qword_reg (void); | |
179 | static int check_word_reg (void); | |
180 | static int finalize_imm (void); | |
181 | static int process_operands (void); | |
5e042380 | 182 | static const reg_entry *build_modrm_byte (void); |
b5482fe5 | 183 | static void output_insn (const struct last_insn *); |
e3bb37b5 L |
184 | static void output_imm (fragS *, offsetT); |
185 | static void output_disp (fragS *, offsetT); | |
d4064aad | 186 | #ifdef OBJ_AOUT |
e3bb37b5 | 187 | static void s_bss (int); |
252b5132 | 188 | #endif |
17d4e2a2 L |
189 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
190 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
191 | |
192 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
193 | static unsigned int x86_isa_1_used; | |
194 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
195 | static unsigned int x86_feature_2_used; | |
196 | /* Generate x86 used ISA and feature properties. */ | |
197 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 198 | #endif |
252b5132 | 199 | |
a847613f | 200 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 201 | |
8a6fb3f9 JB |
202 | /* parse_register() returns this when a register alias cannot be used. */ |
203 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
204 | { Dw2Inval, Dw2Inval } }; | |
205 | ||
34684862 | 206 | static const reg_entry *reg_eax; |
5e042380 JB |
207 | static const reg_entry *reg_ds; |
208 | static const reg_entry *reg_es; | |
209 | static const reg_entry *reg_ss; | |
6288d05f | 210 | static const reg_entry *reg_st0; |
6225c532 JB |
211 | static const reg_entry *reg_k0; |
212 | ||
c0f3af97 L |
213 | /* VEX prefix. */ |
214 | typedef struct | |
215 | { | |
43234a1e L |
216 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
217 | unsigned char bytes[4]; | |
c0f3af97 L |
218 | unsigned int length; |
219 | /* Destination or source register specifier. */ | |
220 | const reg_entry *register_specifier; | |
221 | } vex_prefix; | |
222 | ||
252b5132 | 223 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 224 | i386_insn. */ |
252b5132 | 225 | |
520dc8e8 AM |
226 | union i386_op |
227 | { | |
228 | expressionS *disps; | |
229 | expressionS *imms; | |
230 | const reg_entry *regs; | |
231 | }; | |
232 | ||
a65babc9 L |
233 | enum i386_error |
234 | { | |
b4d65f2d | 235 | no_error, /* Must be first. */ |
86e026a4 | 236 | operand_size_mismatch, |
a65babc9 L |
237 | operand_type_mismatch, |
238 | register_type_mismatch, | |
239 | number_of_operands_mismatch, | |
240 | invalid_instruction_suffix, | |
241 | bad_imm4, | |
a65babc9 L |
242 | unsupported_with_intel_mnemonic, |
243 | unsupported_syntax, | |
80d61d8d | 244 | unsupported_EGPR_for_addressing, |
dd74a603 | 245 | unsupported_nf, |
6c30d220 | 246 | unsupported, |
9db83a32 JB |
247 | unsupported_on_arch, |
248 | unsupported_64bit, | |
54294d73 JB |
249 | no_vex_encoding, |
250 | no_evex_encoding, | |
260cd341 | 251 | invalid_sib_address, |
6c30d220 | 252 | invalid_vsib_address, |
7bab8ab5 | 253 | invalid_vector_register_set, |
260cd341 | 254 | invalid_tmm_register_set, |
0cc78721 | 255 | invalid_dest_and_src_register_set, |
08a98d4c | 256 | invalid_dest_register_set, |
80d61d8d | 257 | invalid_pseudo_prefix, |
43234a1e L |
258 | unsupported_vector_index_register, |
259 | unsupported_broadcast, | |
43234a1e L |
260 | broadcast_needed, |
261 | unsupported_masking, | |
262 | mask_not_on_destination, | |
263 | no_default_mask, | |
264 | unsupported_rc_sae, | |
54294d73 | 265 | unsupported_vector_size, |
08a98d4c | 266 | unsupported_rsp_register, |
58bceb18 | 267 | internal_error, |
a65babc9 L |
268 | }; |
269 | ||
252b5132 RH |
270 | struct _i386_insn |
271 | { | |
47926f60 | 272 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 273 | insn_template tm; |
252b5132 | 274 | |
7d5e4556 L |
275 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
276 | or qword, if given. */ | |
252b5132 RH |
277 | char suffix; |
278 | ||
9a182d04 JB |
279 | /* OPCODE_LENGTH holds the number of base opcode bytes. */ |
280 | unsigned char opcode_length; | |
281 | ||
47926f60 | 282 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
283 | unsigned int operands; |
284 | ||
285 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
286 | of given register, displacement, memory operands and immediate | |
47926f60 | 287 | operands. */ |
252b5132 RH |
288 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
289 | ||
290 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 291 | use OP[i] for the corresponding operand. */ |
40fb9820 | 292 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 293 | |
520dc8e8 AM |
294 | /* Displacement expression, immediate expression, or register for each |
295 | operand. */ | |
296 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 297 | |
3e73aa7c JH |
298 | /* Flags for operands. */ |
299 | unsigned int flags[MAX_OPERANDS]; | |
300 | #define Operand_PCrel 1 | |
c48dadc9 | 301 | #define Operand_Mem 2 |
c032bc4f | 302 | #define Operand_Signed 4 /* .insn only */ |
3e73aa7c | 303 | |
252b5132 | 304 | /* Relocation type for operand */ |
f86103b7 | 305 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 306 | |
252b5132 RH |
307 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
308 | the base index byte below. */ | |
309 | const reg_entry *base_reg; | |
310 | const reg_entry *index_reg; | |
311 | unsigned int log2_scale_factor; | |
312 | ||
313 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 314 | explicit segment overrides are given. */ |
5e042380 | 315 | const reg_entry *seg[2]; |
252b5132 RH |
316 | |
317 | /* PREFIX holds all the given prefix opcodes (usually null). | |
318 | PREFIXES is the number of prefix opcodes. */ | |
319 | unsigned int prefixes; | |
320 | unsigned char prefix[MAX_PREFIXES]; | |
321 | ||
d0c2e3ec JB |
322 | /* .insn allows for reserved opcode spaces. */ |
323 | unsigned char insn_opcode_space; | |
324 | ||
c032bc4f JB |
325 | /* .insn also allows (requires) specifying immediate size. */ |
326 | unsigned char imm_bits[MAX_OPERANDS]; | |
327 | ||
50128d0c | 328 | /* Register is in low 3 bits of opcode. */ |
5b7c81bd | 329 | bool short_form; |
50128d0c | 330 | |
6f2f06be | 331 | /* The operand to a branch insn indicates an absolute branch. */ |
5b7c81bd | 332 | bool jumpabsolute; |
6f2f06be | 333 | |
a4d3acd2 JB |
334 | /* The operand to a branch insn indicates a far branch. */ |
335 | bool far_branch; | |
336 | ||
9373f275 L |
337 | /* There is a memory operand of (%dx) which should be only used |
338 | with input/output instructions. */ | |
339 | bool input_output_operand; | |
340 | ||
921eafea L |
341 | /* Extended states. */ |
342 | enum | |
343 | { | |
344 | /* Use MMX state. */ | |
345 | xstate_mmx = 1 << 0, | |
346 | /* Use XMM state. */ | |
347 | xstate_xmm = 1 << 1, | |
348 | /* Use YMM state. */ | |
349 | xstate_ymm = 1 << 2 | xstate_xmm, | |
350 | /* Use ZMM state. */ | |
351 | xstate_zmm = 1 << 3 | xstate_ymm, | |
352 | /* Use TMM state. */ | |
32930e4e L |
353 | xstate_tmm = 1 << 4, |
354 | /* Use MASK state. */ | |
355 | xstate_mask = 1 << 5 | |
921eafea | 356 | } xstate; |
260cd341 | 357 | |
e379e5f3 | 358 | /* Has GOTPC or TLS relocation. */ |
5b7c81bd | 359 | bool has_gotpc_tls_reloc; |
e379e5f3 | 360 | |
252b5132 | 361 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 362 | addressing modes of this insn are encoded. */ |
252b5132 | 363 | modrm_byte rm; |
3e73aa7c | 364 | rex_byte rex; |
43234a1e | 365 | rex_byte vrex; |
80d61d8d | 366 | rex_byte rex2; |
252b5132 | 367 | sib_byte sib; |
c0f3af97 | 368 | vex_prefix vex; |
b6169b20 | 369 | |
6225c532 JB |
370 | /* Masking attributes. |
371 | ||
372 | The struct describes masking, applied to OPERAND in the instruction. | |
373 | REG is a pointer to the corresponding mask register. ZEROING tells | |
374 | whether merging or zeroing mask is used. */ | |
375 | struct Mask_Operation | |
376 | { | |
377 | const reg_entry *reg; | |
378 | unsigned int zeroing; | |
379 | /* The operand where this operation is associated. */ | |
380 | unsigned int operand; | |
381 | } mask; | |
43234a1e L |
382 | |
383 | /* Rounding control and SAE attributes. */ | |
ca5312a2 JB |
384 | struct RC_Operation |
385 | { | |
386 | enum rc_type | |
387 | { | |
388 | rc_none = -1, | |
389 | rne, | |
390 | rd, | |
391 | ru, | |
392 | rz, | |
393 | saeonly | |
394 | } type; | |
7063667e JB |
395 | /* In Intel syntax the operand modifier form is supposed to be used, but |
396 | we continue to accept the immediate forms as well. */ | |
397 | bool modifier; | |
ca5312a2 | 398 | } rounding; |
43234a1e | 399 | |
5273a3cd JB |
400 | /* Broadcasting attributes. |
401 | ||
402 | The struct describes broadcasting, applied to OPERAND. TYPE is | |
403 | expresses the broadcast factor. */ | |
404 | struct Broadcast_Operation | |
405 | { | |
0cc78721 | 406 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */ |
5273a3cd JB |
407 | unsigned int type; |
408 | ||
409 | /* Index of broadcasted operand. */ | |
410 | unsigned int operand; | |
411 | ||
412 | /* Number of bytes to broadcast. */ | |
413 | unsigned int bytes; | |
414 | } broadcast; | |
43234a1e L |
415 | |
416 | /* Compressed disp8*N attribute. */ | |
417 | unsigned int memshift; | |
418 | ||
86fa6981 L |
419 | /* Prefer load or store in encoding. */ |
420 | enum | |
421 | { | |
422 | dir_encoding_default = 0, | |
423 | dir_encoding_load, | |
64c49ab3 JB |
424 | dir_encoding_store, |
425 | dir_encoding_swap | |
86fa6981 | 426 | } dir_encoding; |
891edac4 | 427 | |
41eb8e88 | 428 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
429 | enum |
430 | { | |
431 | disp_encoding_default = 0, | |
432 | disp_encoding_8bit, | |
41eb8e88 | 433 | disp_encoding_16bit, |
a501d77e L |
434 | disp_encoding_32bit |
435 | } disp_encoding; | |
f8a5c266 | 436 | |
6b6b6807 | 437 | /* Prefer the REX byte in encoding. */ |
5b7c81bd | 438 | bool rex_encoding; |
6b6b6807 | 439 | |
80d61d8d CL |
440 | /* Prefer the REX2 prefix in encoding. */ |
441 | bool rex2_encoding; | |
442 | ||
dd74a603 CL |
443 | /* No CSPAZO flags update. */ |
444 | bool has_nf; | |
445 | ||
b6f8c7c4 | 446 | /* Disable instruction size optimization. */ |
5b7c81bd | 447 | bool no_optimize; |
b6f8c7c4 | 448 | |
e346d50a | 449 | /* How to encode instructions. */ |
86fa6981 L |
450 | enum |
451 | { | |
e346d50a JB |
452 | encoding_default = 0, |
453 | encoding_vex, | |
454 | encoding_vex3, | |
eb3f3841 | 455 | encoding_egpr, /* REX2 or EVEX. */ |
e346d50a JB |
456 | encoding_evex, |
457 | encoding_evex512, | |
458 | encoding_error | |
459 | } encoding; | |
86fa6981 | 460 | |
d5de92cf L |
461 | /* REP prefix. */ |
462 | const char *rep_prefix; | |
463 | ||
165de32a L |
464 | /* HLE prefix. */ |
465 | const char *hle_prefix; | |
42164a71 | 466 | |
7e8b059b L |
467 | /* Have BND prefix. */ |
468 | const char *bnd_prefix; | |
469 | ||
04ef582a L |
470 | /* Have NOTRACK prefix. */ |
471 | const char *notrack_prefix; | |
472 | ||
891edac4 | 473 | /* Error message. */ |
a65babc9 | 474 | enum i386_error error; |
252b5132 RH |
475 | }; |
476 | ||
477 | typedef struct _i386_insn i386_insn; | |
478 | ||
43234a1e L |
479 | /* Link RC type with corresponding string, that'll be looked for in |
480 | asm. */ | |
481 | struct RC_name | |
482 | { | |
483 | enum rc_type type; | |
484 | const char *name; | |
485 | unsigned int len; | |
486 | }; | |
487 | ||
488 | static const struct RC_name RC_NamesTable[] = | |
489 | { | |
490 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
491 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
492 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
493 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
494 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
495 | }; | |
496 | ||
3bfea8ba L |
497 | /* To be indexed by segment register number. */ |
498 | static const unsigned char i386_seg_prefixes[] = { | |
499 | ES_PREFIX_OPCODE, | |
500 | CS_PREFIX_OPCODE, | |
501 | SS_PREFIX_OPCODE, | |
502 | DS_PREFIX_OPCODE, | |
503 | FS_PREFIX_OPCODE, | |
504 | GS_PREFIX_OPCODE | |
505 | }; | |
506 | ||
252b5132 RH |
507 | /* List of chars besides those in app.c:symbol_chars that can start an |
508 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 509 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 510 | #ifdef LEX_AT |
32137342 NC |
511 | "@" |
512 | #endif | |
513 | #ifdef LEX_QM | |
514 | "?" | |
252b5132 | 515 | #endif |
32137342 | 516 | ; |
252b5132 | 517 | |
b3983e5f JB |
518 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
519 | && !defined (TE_GNU) \ | |
520 | && !defined (TE_LINUX) \ | |
d85e70a3 | 521 | && !defined (TE_Haiku) \ |
b3983e5f JB |
522 | && !defined (TE_FreeBSD) \ |
523 | && !defined (TE_DragonFly) \ | |
524 | && !defined (TE_NetBSD)) | |
252b5132 | 525 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
526 | pre-processor is disabled, these aren't very useful. The option |
527 | --divide will remove '/' from this list. */ | |
528 | const char *i386_comment_chars = "#/"; | |
529 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 530 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 531 | |
b3b91714 AM |
532 | #else |
533 | const char *i386_comment_chars = "#"; | |
534 | #define PREFIX_SEPARATOR '/' | |
535 | #endif | |
536 | ||
252b5132 RH |
537 | /* This array holds the chars that only start a comment at the beginning of |
538 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
539 | .line and .file directives will appear in the pre-processed output. |
540 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 541 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
542 | #NO_APP at the beginning of its output. |
543 | Also note that comments started like this one will always work if | |
252b5132 | 544 | '/' isn't otherwise defined. */ |
b3b91714 | 545 | const char line_comment_chars[] = "#/"; |
252b5132 | 546 | |
63a0b638 | 547 | const char line_separator_chars[] = ";"; |
252b5132 | 548 | |
ce8a8b2f AM |
549 | /* Chars that can be used to separate mant from exp in floating point |
550 | nums. */ | |
252b5132 RH |
551 | const char EXP_CHARS[] = "eE"; |
552 | ||
ce8a8b2f AM |
553 | /* Chars that mean this number is a floating point constant |
554 | As in 0f12.456 | |
555 | or 0d1.2345e12. */ | |
de133cf9 | 556 | const char FLT_CHARS[] = "fFdDxXhHbB"; |
252b5132 | 557 | |
ce8a8b2f | 558 | /* Tables for lexical analysis. */ |
252b5132 RH |
559 | static char mnemonic_chars[256]; |
560 | static char register_chars[256]; | |
561 | static char operand_chars[256]; | |
252b5132 | 562 | |
ce8a8b2f | 563 | /* Lexical macros. */ |
252b5132 RH |
564 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
565 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
566 | #define is_space_char(x) ((x) == ' ') | |
252b5132 | 567 | |
d2b1a14d JB |
568 | /* All non-digit non-letter characters that may occur in an operand and |
569 | which aren't already in extra_symbol_chars[]. */ | |
570 | static const char operand_special_chars[] = "$+,)._~/<>|&^!=:@]"; | |
252b5132 RH |
571 | |
572 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
573 | effect this we maintain a stack of saved characters that we've smashed | |
574 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 575 | assembler instruction). */ |
252b5132 | 576 | static char save_stack[32]; |
ce8a8b2f | 577 | static char *save_stack_p; |
252b5132 RH |
578 | #define END_STRING_AND_SAVE(s) \ |
579 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
580 | #define RESTORE_END_STRING(s) \ | |
581 | do { *(s) = *--save_stack_p; } while (0) | |
582 | ||
47926f60 | 583 | /* The instruction we're assembling. */ |
252b5132 RH |
584 | static i386_insn i; |
585 | ||
586 | /* Possible templates for current insn. */ | |
d3b01414 | 587 | static templates current_templates; |
252b5132 | 588 | |
31b2323c L |
589 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
590 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
591 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 592 | |
47926f60 | 593 | /* Current operand we are working on. */ |
ee86248c | 594 | static int this_operand = -1; |
252b5132 | 595 | |
d0c2e3ec JB |
596 | /* Are we processing a .insn directive? */ |
597 | #define dot_insn() (i.tm.mnem_off == MN__insn) | |
598 | ||
ed719294 JB |
599 | enum i386_flag_code i386_flag_code; |
600 | #define flag_code i386_flag_code /* Permit to continue using original name. */ | |
4fa24527 | 601 | static unsigned int object_64bit; |
862be3fb | 602 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 603 | static int use_rela_relocations = 0; |
e379e5f3 L |
604 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
605 | static const char *tls_get_addr; | |
3e73aa7c | 606 | |
071c5d81 | 607 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7af8ed2d | 608 | |
351f65ca L |
609 | /* The ELF ABI to use. */ |
610 | enum x86_elf_abi | |
611 | { | |
612 | I386_ABI, | |
7f56bc95 L |
613 | X86_64_ABI, |
614 | X86_64_X32_ABI | |
351f65ca L |
615 | }; |
616 | ||
617 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 618 | #endif |
351f65ca | 619 | |
167ad85b TG |
620 | #if defined (TE_PE) || defined (TE_PEP) |
621 | /* Use big object file format. */ | |
622 | static int use_big_obj = 0; | |
623 | #endif | |
624 | ||
8dcea932 L |
625 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
626 | /* 1 if generating code for a shared library. */ | |
627 | static int shared = 0; | |
b52c4ee4 IB |
628 | |
629 | unsigned int x86_sframe_cfa_sp_reg; | |
3e3e792a | 630 | /* The other CFA base register for SFrame stack trace info. */ |
b52c4ee4 IB |
631 | unsigned int x86_sframe_cfa_fp_reg; |
632 | unsigned int x86_sframe_cfa_ra_reg; | |
633 | ||
8dcea932 L |
634 | #endif |
635 | ||
47926f60 KH |
636 | /* 1 for intel syntax, |
637 | 0 if att syntax. */ | |
638 | static int intel_syntax = 0; | |
252b5132 | 639 | |
4b5aaf5f L |
640 | static enum x86_64_isa |
641 | { | |
642 | amd64 = 1, /* AMD64 ISA. */ | |
643 | intel64 /* Intel64 ISA. */ | |
644 | } isa64; | |
e89c5eaa | 645 | |
1efbbeb4 L |
646 | /* 1 for intel mnemonic, |
647 | 0 if att mnemonic. */ | |
648 | static int intel_mnemonic = !SYSV386_COMPAT; | |
649 | ||
a60de03c JB |
650 | /* 1 if pseudo registers are permitted. */ |
651 | static int allow_pseudo_reg = 0; | |
652 | ||
47926f60 KH |
653 | /* 1 if register prefix % not required. */ |
654 | static int allow_naked_reg = 0; | |
252b5132 | 655 | |
33eaf5de | 656 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
657 | instructions supporting it, even if this prefix wasn't specified |
658 | explicitly. */ | |
659 | static int add_bnd_prefix = 0; | |
660 | ||
ba104c83 | 661 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
662 | static int allow_index_reg = 0; |
663 | ||
d022bddd IT |
664 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
665 | specified explicitly. */ | |
666 | static int omit_lock_prefix = 0; | |
667 | ||
e4e00185 AS |
668 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
669 | "lock addl $0, (%{re}sp)". */ | |
670 | static int avoid_fence = 0; | |
671 | ||
ae531041 L |
672 | /* 1 if lfence should be inserted after every load. */ |
673 | static int lfence_after_load = 0; | |
674 | ||
675 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
676 | static enum lfence_before_indirect_branch_kind | |
677 | { | |
678 | lfence_branch_none = 0, | |
679 | lfence_branch_register, | |
680 | lfence_branch_memory, | |
681 | lfence_branch_all | |
682 | } | |
683 | lfence_before_indirect_branch; | |
684 | ||
685 | /* Non-zero if lfence should be inserted before ret. */ | |
686 | static enum lfence_before_ret_kind | |
687 | { | |
688 | lfence_before_ret_none = 0, | |
689 | lfence_before_ret_not, | |
a09f656b | 690 | lfence_before_ret_or, |
691 | lfence_before_ret_shl | |
ae531041 L |
692 | } |
693 | lfence_before_ret; | |
694 | ||
0cb4071e L |
695 | /* 1 if the assembler should generate relax relocations. */ |
696 | ||
697 | static int generate_relax_relocations | |
698 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
699 | ||
7bab8ab5 | 700 | static enum check_kind |
daf50ae7 | 701 | { |
7bab8ab5 JB |
702 | check_none = 0, |
703 | check_warning, | |
704 | check_error | |
daf50ae7 | 705 | } |
7bab8ab5 | 706 | sse_check, operand_check = check_warning; |
daf50ae7 | 707 | |
e379e5f3 L |
708 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
709 | static int align_branch_power = 0; | |
710 | ||
711 | /* Types of branches to align. */ | |
712 | enum align_branch_kind | |
713 | { | |
714 | align_branch_none = 0, | |
715 | align_branch_jcc = 1, | |
716 | align_branch_fused = 2, | |
717 | align_branch_jmp = 3, | |
718 | align_branch_call = 4, | |
719 | align_branch_indirect = 5, | |
720 | align_branch_ret = 6 | |
721 | }; | |
722 | ||
723 | /* Type bits of branches to align. */ | |
724 | enum align_branch_bit | |
725 | { | |
726 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
727 | align_branch_fused_bit = 1 << align_branch_fused, | |
728 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
729 | align_branch_call_bit = 1 << align_branch_call, | |
730 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
731 | align_branch_ret_bit = 1 << align_branch_ret | |
732 | }; | |
733 | ||
734 | static unsigned int align_branch = (align_branch_jcc_bit | |
735 | | align_branch_fused_bit | |
736 | | align_branch_jmp_bit); | |
737 | ||
79d72f45 HL |
738 | /* Types of condition jump used by macro-fusion. */ |
739 | enum mf_jcc_kind | |
740 | { | |
741 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
742 | mf_jcc_jc, /* base opcode 0x72 */ | |
743 | mf_jcc_je, /* base opcode 0x74 */ | |
744 | mf_jcc_jna, /* base opcode 0x76 */ | |
745 | mf_jcc_js, /* base opcode 0x78 */ | |
746 | mf_jcc_jp, /* base opcode 0x7a */ | |
747 | mf_jcc_jl, /* base opcode 0x7c */ | |
748 | mf_jcc_jle, /* base opcode 0x7e */ | |
749 | }; | |
750 | ||
751 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
752 | enum mf_cmp_kind | |
753 | { | |
754 | mf_cmp_test_and, /* test/cmp */ | |
755 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
756 | mf_cmp_incdec /* inc/dec */ | |
757 | }; | |
758 | ||
e379e5f3 L |
759 | /* The maximum padding size for fused jcc. CMP like instruction can |
760 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
761 | prefixes. */ | |
762 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
763 | ||
764 | /* The maximum number of prefixes added for an instruction. */ | |
765 | static unsigned int align_branch_prefix_size = 5; | |
766 | ||
b6f8c7c4 L |
767 | /* Optimization: |
768 | 1. Clear the REX_W bit with register operand if possible. | |
769 | 2. Above plus use 128bit vector instruction to clear the full vector | |
770 | register. | |
771 | */ | |
772 | static int optimize = 0; | |
773 | ||
774 | /* Optimization: | |
775 | 1. Clear the REX_W bit with register operand if possible. | |
776 | 2. Above plus use 128bit vector instruction to clear the full vector | |
777 | register. | |
778 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
779 | "testb $imm7,%r8". | |
780 | */ | |
781 | static int optimize_for_space = 0; | |
782 | ||
2ca3ace5 L |
783 | /* Register prefix used for error message. */ |
784 | static const char *register_prefix = "%"; | |
785 | ||
47926f60 KH |
786 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
787 | leave, push, and pop instructions so that gcc has the same stack | |
788 | frame as in 32 bit mode. */ | |
789 | static char stackop_size = '\0'; | |
eecb386c | 790 | |
12b55ccc L |
791 | /* Non-zero to optimize code alignment. */ |
792 | int optimize_align_code = 1; | |
793 | ||
47926f60 KH |
794 | /* Non-zero to quieten some warnings. */ |
795 | static int quiet_warnings = 0; | |
a38cf1db | 796 | |
d59a54c2 JB |
797 | /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */ |
798 | static bool pre_386_16bit_warned; | |
799 | ||
47926f60 KH |
800 | /* CPU name. */ |
801 | static const char *cpu_arch_name = NULL; | |
6305a203 | 802 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 803 | |
47926f60 | 804 | /* CPU feature flags. */ |
cd75cd85 | 805 | i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
40fb9820 | 806 | |
3e624fa4 JB |
807 | /* ISA extensions available in 64-bit mode only. */ |
808 | static const i386_cpu_flags cpu_64_flags = CPU_ANY_64_FLAGS; | |
809 | ||
ccc9c027 L |
810 | /* If we have selected a cpu we are generating instructions for. */ |
811 | static int cpu_arch_tune_set = 0; | |
812 | ||
9103f4f4 | 813 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 814 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 | 815 | |
ccc9c027 | 816 | /* CPU instruction set architecture used. */ |
fbf3f584 | 817 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 818 | |
9103f4f4 | 819 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 820 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 821 | |
fddf5b5b AM |
822 | /* If set, conditional jumps are not automatically promoted to handle |
823 | larger than a byte offset. */ | |
f68697e8 | 824 | static bool no_cond_jump_promotion = false; |
fddf5b5b | 825 | |
5cc00775 JB |
826 | /* This will be set from an expression parser hook if there's any |
827 | applicable operator involved in an expression. */ | |
828 | static enum { | |
829 | expr_operator_none, | |
830 | expr_operator_present, | |
831 | expr_large_value, | |
832 | } expr_mode; | |
833 | ||
c0f3af97 L |
834 | /* Encode SSE instructions with VEX prefix. */ |
835 | static unsigned int sse2avx; | |
836 | ||
c8480b58 L |
837 | /* Encode aligned vector move as unaligned vector move. */ |
838 | static unsigned int use_unaligned_vector_move; | |
839 | ||
4fc85f37 | 840 | /* Maximum permitted vector size. */ |
fa88a361 HJ |
841 | #define VSZ128 0 |
842 | #define VSZ256 1 | |
843 | #define VSZ512 2 | |
4fc85f37 JB |
844 | #define VSZ_DEFAULT VSZ512 |
845 | static unsigned int vector_size = VSZ_DEFAULT; | |
846 | ||
539f890d L |
847 | /* Encode scalar AVX instructions with specific vector length. */ |
848 | static enum | |
849 | { | |
850 | vex128 = 0, | |
851 | vex256 | |
852 | } avxscalar; | |
853 | ||
03751133 L |
854 | /* Encode VEX WIG instructions with specific vex.w. */ |
855 | static enum | |
856 | { | |
857 | vexw0 = 0, | |
858 | vexw1 | |
859 | } vexwig; | |
860 | ||
43234a1e L |
861 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
862 | static enum | |
863 | { | |
864 | evexl128 = 0, | |
865 | evexl256, | |
866 | evexl512 | |
867 | } evexlig; | |
868 | ||
869 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
870 | static enum | |
871 | { | |
872 | evexw0 = 0, | |
873 | evexw1 | |
874 | } evexwig; | |
875 | ||
d3d3c6db IT |
876 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
877 | static enum rc_type evexrcig = rne; | |
878 | ||
29b0f896 | 879 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 880 | static symbolS *GOT_symbol; |
29b0f896 | 881 | |
a4447b93 RH |
882 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
883 | unsigned int x86_dwarf2_return_column; | |
884 | ||
885 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
886 | int x86_cie_data_alignment; | |
887 | ||
252b5132 | 888 | /* Interface to relax_segment. |
fddf5b5b AM |
889 | There are 3 major relax states for 386 jump insns because the |
890 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
891 | figuring out what sort of jump to choose to reach a given label. |
892 | ||
893 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
894 | branches which are handled by md_estimate_size_before_relax() and | |
895 | i386_generic_table_relax_frag(). */ | |
252b5132 | 896 | |
47926f60 | 897 | /* Types. */ |
93c2a809 AM |
898 | #define UNCOND_JUMP 0 |
899 | #define COND_JUMP 1 | |
900 | #define COND_JUMP86 2 | |
e379e5f3 L |
901 | #define BRANCH_PADDING 3 |
902 | #define BRANCH_PREFIX 4 | |
903 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 904 | |
47926f60 | 905 | /* Sizes. */ |
252b5132 RH |
906 | #define CODE16 1 |
907 | #define SMALL 0 | |
29b0f896 | 908 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 909 | #define BIG 2 |
29b0f896 | 910 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
911 | |
912 | #ifndef INLINE | |
913 | #ifdef __GNUC__ | |
914 | #define INLINE __inline__ | |
915 | #else | |
916 | #define INLINE | |
917 | #endif | |
918 | #endif | |
919 | ||
fddf5b5b AM |
920 | #define ENCODE_RELAX_STATE(type, size) \ |
921 | ((relax_substateT) (((type) << 2) | (size))) | |
922 | #define TYPE_FROM_RELAX_STATE(s) \ | |
923 | ((s) >> 2) | |
924 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
925 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
926 | |
927 | /* This table is used by relax_frag to promote short jumps to long | |
928 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
929 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
930 | don't allow a short jump in a 32 bit code segment to be promoted to | |
931 | a 16 bit offset jump because it's slower (requires data size | |
932 | prefix), and doesn't work, unless the destination is in the bottom | |
933 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
934 | ||
935 | const relax_typeS md_relax_table[] = | |
936 | { | |
24eab124 AM |
937 | /* The fields are: |
938 | 1) most positive reach of this state, | |
939 | 2) most negative reach of this state, | |
93c2a809 | 940 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 941 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 942 | |
fddf5b5b | 943 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
944 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
945 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
946 | /* dword jmp adds 4 bytes to frag: | |
947 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 948 | {0, 0, 4, 0}, |
93c2a809 AM |
949 | /* word jmp adds 2 byte2 to frag: |
950 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
951 | {0, 0, 2, 0}, |
952 | ||
93c2a809 AM |
953 | /* COND_JUMP states. */ |
954 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
955 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
956 | /* dword conditionals adds 5 bytes to frag: | |
957 | 1 extra opcode byte, 4 displacement bytes. */ | |
958 | {0, 0, 5, 0}, | |
fddf5b5b | 959 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
960 | 1 extra opcode byte, 2 displacement bytes. */ |
961 | {0, 0, 3, 0}, | |
962 | ||
963 | /* COND_JUMP86 states. */ | |
964 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
965 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
966 | /* dword conditionals adds 5 bytes to frag: | |
967 | 1 extra opcode byte, 4 displacement bytes. */ | |
968 | {0, 0, 5, 0}, | |
969 | /* word conditionals add 4 bytes to frag: | |
970 | 1 displacement byte and a 3 byte long branch insn. */ | |
971 | {0, 0, 4, 0} | |
252b5132 RH |
972 | }; |
973 | ||
6ceeed25 | 974 | #define ARCH(n, t, f, s) \ |
4fc85f37 | 975 | { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \ |
ae89daec JB |
976 | CPU_NONE_FLAGS } |
977 | #define SUBARCH(n, e, d, s) \ | |
4fc85f37 | 978 | { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \ |
ae89daec | 979 | CPU_ ## d ## _FLAGS } |
4fc85f37 JB |
980 | #define VECARCH(n, e, d, v) \ |
981 | { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \ | |
982 | CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS } | |
6ceeed25 | 983 | |
9103f4f4 L |
984 | static const arch_entry cpu_arch[] = |
985 | { | |
3ce2ebcf JB |
986 | /* Do not replace the first two entries - i386_target_format() and |
987 | set_cpu_arch() rely on them being there in this order. */ | |
6ceeed25 JB |
988 | ARCH (generic32, GENERIC32, GENERIC32, false), |
989 | ARCH (generic64, GENERIC64, GENERIC64, false), | |
990 | ARCH (i8086, UNKNOWN, NONE, false), | |
4d97c5c8 JB |
991 | ARCH (i186, UNKNOWN, 186, false), |
992 | ARCH (i286, UNKNOWN, 286, false), | |
993 | ARCH (i386, I386, 386, false), | |
994 | ARCH (i486, I486, 486, false), | |
995 | ARCH (i586, PENTIUM, 586, false), | |
4d97c5c8 | 996 | ARCH (pentium, PENTIUM, 586, false), |
c8be4b6f | 997 | ARCH (i686, I686, 686, false), |
6ceeed25 JB |
998 | ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false), |
999 | ARCH (pentiumii, PENTIUMPRO, P2, false), | |
1000 | ARCH (pentiumiii, PENTIUMPRO, P3, false), | |
1001 | ARCH (pentium4, PENTIUM4, P4, false), | |
1002 | ARCH (prescott, NOCONA, CORE, false), | |
1003 | ARCH (nocona, NOCONA, NOCONA, false), | |
1004 | ARCH (yonah, CORE, CORE, true), | |
1005 | ARCH (core, CORE, CORE, false), | |
1006 | ARCH (merom, CORE2, CORE2, true), | |
1007 | ARCH (core2, CORE2, CORE2, false), | |
1008 | ARCH (corei7, COREI7, COREI7, false), | |
1009 | ARCH (iamcu, IAMCU, IAMCU, false), | |
1010 | ARCH (k6, K6, K6, false), | |
1011 | ARCH (k6_2, K6, K6_2, false), | |
1012 | ARCH (athlon, ATHLON, ATHLON, false), | |
1013 | ARCH (sledgehammer, K8, K8, true), | |
1014 | ARCH (opteron, K8, K8, false), | |
1015 | ARCH (k8, K8, K8, false), | |
1016 | ARCH (amdfam10, AMDFAM10, AMDFAM10, false), | |
1017 | ARCH (bdver1, BD, BDVER1, false), | |
1018 | ARCH (bdver2, BD, BDVER2, false), | |
1019 | ARCH (bdver3, BD, BDVER3, false), | |
1020 | ARCH (bdver4, BD, BDVER4, false), | |
1021 | ARCH (znver1, ZNVER, ZNVER1, false), | |
1022 | ARCH (znver2, ZNVER, ZNVER2, false), | |
1023 | ARCH (znver3, ZNVER, ZNVER3, false), | |
b0e8fa7f | 1024 | ARCH (znver4, ZNVER, ZNVER4, false), |
b143c979 | 1025 | ARCH (znver5, ZNVER, ZNVER5, false), |
6ceeed25 JB |
1026 | ARCH (btver1, BT, BTVER1, false), |
1027 | ARCH (btver2, BT, BTVER2, false), | |
1028 | ||
4d97c5c8 JB |
1029 | SUBARCH (8087, 8087, ANY_8087, false), |
1030 | SUBARCH (87, NONE, ANY_8087, false), /* Disable only! */ | |
ae89daec JB |
1031 | SUBARCH (287, 287, ANY_287, false), |
1032 | SUBARCH (387, 387, ANY_387, false), | |
1033 | SUBARCH (687, 687, ANY_687, false), | |
4d97c5c8 | 1034 | SUBARCH (cmov, CMOV, CMOV, false), |
88bd2203 | 1035 | SUBARCH (fxsr, FXSR, ANY_FXSR, false), |
ae89daec JB |
1036 | SUBARCH (mmx, MMX, ANY_MMX, false), |
1037 | SUBARCH (sse, SSE, ANY_SSE, false), | |
1038 | SUBARCH (sse2, SSE2, ANY_SSE2, false), | |
1039 | SUBARCH (sse3, SSE3, ANY_SSE3, false), | |
1040 | SUBARCH (sse4a, SSE4A, ANY_SSE4A, false), | |
1041 | SUBARCH (ssse3, SSSE3, ANY_SSSE3, false), | |
1042 | SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false), | |
1043 | SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false), | |
1044 | SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false), | |
4fc85f37 JB |
1045 | VECARCH (avx, AVX, ANY_AVX, reset), |
1046 | VECARCH (avx2, AVX2, ANY_AVX2, reset), | |
1047 | VECARCH (avx512f, AVX512F, ANY_AVX512F, reset), | |
1048 | VECARCH (avx512cd, AVX512CD, ANY_AVX512CD, reset), | |
1049 | VECARCH (avx512er, AVX512ER, ANY_AVX512ER, reset), | |
1050 | VECARCH (avx512pf, AVX512PF, ANY_AVX512PF, reset), | |
1051 | VECARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, reset), | |
1052 | VECARCH (avx512bw, AVX512BW, ANY_AVX512BW, reset), | |
1053 | VECARCH (avx512vl, AVX512VL, ANY_AVX512VL, reset), | |
cafa5ef7 | 1054 | SUBARCH (monitor, MONITOR, MONITOR, false), |
25626f79 JB |
1055 | SUBARCH (vmx, VMX, ANY_VMX, false), |
1056 | SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false), | |
ae89daec | 1057 | SUBARCH (smx, SMX, SMX, false), |
5091b9ee JB |
1058 | SUBARCH (xsave, XSAVE, ANY_XSAVE, false), |
1059 | SUBARCH (xsaveopt, XSAVEOPT, ANY_XSAVEOPT, false), | |
1060 | SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false), | |
1061 | SUBARCH (xsaves, XSAVES, ANY_XSAVES, false), | |
1062 | SUBARCH (aes, AES, ANY_AES, false), | |
d54678eb JB |
1063 | SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false), |
1064 | SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true), | |
ae89daec JB |
1065 | SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false), |
1066 | SUBARCH (rdrnd, RDRND, RDRND, false), | |
5091b9ee | 1067 | SUBARCH (f16c, F16C, ANY_F16C, false), |
ae89daec | 1068 | SUBARCH (bmi2, BMI2, BMI2, false), |
5091b9ee JB |
1069 | SUBARCH (fma, FMA, ANY_FMA, false), |
1070 | SUBARCH (fma4, FMA4, ANY_FMA4, false), | |
1071 | SUBARCH (xop, XOP, ANY_XOP, false), | |
1072 | SUBARCH (lwp, LWP, ANY_LWP, false), | |
ae89daec JB |
1073 | SUBARCH (movbe, MOVBE, MOVBE, false), |
1074 | SUBARCH (cx16, CX16, CX16, false), | |
c3bb24f5 | 1075 | SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false), |
25626f79 | 1076 | SUBARCH (ept, EPT, ANY_EPT, false), |
ae89daec JB |
1077 | SUBARCH (lzcnt, LZCNT, LZCNT, false), |
1078 | SUBARCH (popcnt, POPCNT, POPCNT, false), | |
1079 | SUBARCH (hle, HLE, HLE, false), | |
760ab3d0 JB |
1080 | SUBARCH (rtm, RTM, ANY_RTM, false), |
1081 | SUBARCH (tsx, TSX, TSX, false), | |
ae89daec JB |
1082 | SUBARCH (invpcid, INVPCID, INVPCID, false), |
1083 | SUBARCH (clflush, CLFLUSH, CLFLUSH, false), | |
1084 | SUBARCH (nop, NOP, NOP, false), | |
1085 | SUBARCH (syscall, SYSCALL, SYSCALL, false), | |
1086 | SUBARCH (rdtscp, RDTSCP, RDTSCP, false), | |
5091b9ee JB |
1087 | SUBARCH (3dnow, 3DNOW, ANY_3DNOW, false), |
1088 | SUBARCH (3dnowa, 3DNOWA, ANY_3DNOWA, false), | |
ae89daec | 1089 | SUBARCH (padlock, PADLOCK, PADLOCK, false), |
0919e770 JB |
1090 | SUBARCH (pacifica, SVME, ANY_SVME, true), |
1091 | SUBARCH (svme, SVME, ANY_SVME, false), | |
ae89daec JB |
1092 | SUBARCH (abm, ABM, ABM, false), |
1093 | SUBARCH (bmi, BMI, BMI, false), | |
1094 | SUBARCH (tbm, TBM, TBM, false), | |
1095 | SUBARCH (adx, ADX, ADX, false), | |
1096 | SUBARCH (rdseed, RDSEED, RDSEED, false), | |
1097 | SUBARCH (prfchw, PRFCHW, PRFCHW, false), | |
1098 | SUBARCH (smap, SMAP, SMAP, false), | |
5091b9ee JB |
1099 | SUBARCH (mpx, MPX, ANY_MPX, false), |
1100 | SUBARCH (sha, SHA, ANY_SHA, false), | |
ae89daec JB |
1101 | SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false), |
1102 | SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false), | |
1103 | SUBARCH (se1, SE1, SE1, false), | |
1104 | SUBARCH (clwb, CLWB, CLWB, false), | |
4fc85f37 JB |
1105 | VECARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, reset), |
1106 | VECARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, reset), | |
1107 | VECARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, reset), | |
1108 | VECARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, reset), | |
1109 | VECARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, reset), | |
1110 | VECARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, reset), | |
1111 | VECARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, reset), | |
1112 | VECARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, reset), | |
1113 | VECARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, reset), | |
ae89daec JB |
1114 | SUBARCH (clzero, CLZERO, CLZERO, false), |
1115 | SUBARCH (mwaitx, MWAITX, MWAITX, false), | |
5091b9ee | 1116 | SUBARCH (ospke, OSPKE, ANY_OSPKE, false), |
ae89daec JB |
1117 | SUBARCH (rdpid, RDPID, RDPID, false), |
1118 | SUBARCH (ptwrite, PTWRITE, PTWRITE, false), | |
4d97c5c8 JB |
1119 | SUBARCH (ibt, IBT, IBT, false), |
1120 | SUBARCH (shstk, SHSTK, SHSTK, false), | |
88bd2203 | 1121 | SUBARCH (gfni, GFNI, ANY_GFNI, false), |
4fc85f37 JB |
1122 | VECARCH (vaes, VAES, ANY_VAES, reset), |
1123 | VECARCH (vpclmulqdq, VPCLMULQDQ, ANY_VPCLMULQDQ, reset), | |
ae89daec JB |
1124 | SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false), |
1125 | SUBARCH (pconfig, PCONFIG, PCONFIG, false), | |
1126 | SUBARCH (waitpkg, WAITPKG, WAITPKG, false), | |
1127 | SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false), | |
1128 | SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false), | |
1129 | SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false), | |
5091b9ee | 1130 | SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false), |
d100d8c1 | 1131 | SUBARCH (amx_complex, AMX_COMPLEX, ANY_AMX_COMPLEX, false), |
ae89daec | 1132 | SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false), |
4d97c5c8 JB |
1133 | SUBARCH (movdiri, MOVDIRI, MOVDIRI, false), |
1134 | SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false), | |
4fc85f37 JB |
1135 | VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset), |
1136 | VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT, | |
1137 | ANY_AVX512_VP2INTERSECT, reset), | |
4d97c5c8 JB |
1138 | SUBARCH (tdx, TDX, TDX, false), |
1139 | SUBARCH (enqcmd, ENQCMD, ENQCMD, false), | |
1140 | SUBARCH (serialize, SERIALIZE, SERIALIZE, false), | |
ae89daec JB |
1141 | SUBARCH (rdpru, RDPRU, RDPRU, false), |
1142 | SUBARCH (mcommit, MCOMMIT, MCOMMIT, false), | |
0919e770 | 1143 | SUBARCH (sev_es, SEV_ES, ANY_SEV_ES, false), |
760ab3d0 | 1144 | SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false), |
88bd2203 JB |
1145 | SUBARCH (kl, KL, ANY_KL, false), |
1146 | SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false), | |
4d97c5c8 JB |
1147 | SUBARCH (uintr, UINTR, UINTR, false), |
1148 | SUBARCH (hreset, HRESET, HRESET, false), | |
4fc85f37 | 1149 | VECARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, reset), |
ef07be45 | 1150 | SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false), |
4fc85f37 JB |
1151 | VECARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, reset), |
1152 | VECARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, reset), | |
4d97c5c8 JB |
1153 | SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false), |
1154 | SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), | |
1155 | SUBARCH (msrlist, MSRLIST, MSRLIST, false), | |
4fc85f37 | 1156 | VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset), |
4d97c5c8 | 1157 | SUBARCH (rao_int, RAO_INT, RAO_INT, false), |
0919e770 | 1158 | SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false), |
c88ed92f ZJ |
1159 | SUBARCH (fred, FRED, ANY_FRED, false), |
1160 | SUBARCH (lkgs, LKGS, ANY_LKGS, false), | |
4fc85f37 JB |
1161 | VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset), |
1162 | VECARCH (sha512, SHA512, ANY_SHA512, reset), | |
1163 | VECARCH (sm3, SM3, ANY_SM3, reset), | |
1164 | VECARCH (sm4, SM4, ANY_SM4, reset), | |
b5c37946 | 1165 | SUBARCH (pbndkb, PBNDKB, PBNDKB, false), |
4fc85f37 | 1166 | VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), |
8170af78 | 1167 | SUBARCH (user_msr, USER_MSR, USER_MSR, false), |
80d61d8d | 1168 | SUBARCH (apx_f, APX_F, APX_F, false), |
293f5f65 L |
1169 | }; |
1170 | ||
6ceeed25 JB |
1171 | #undef SUBARCH |
1172 | #undef ARCH | |
1173 | ||
704209c0 | 1174 | #ifdef I386COFF |
a6c24e68 NC |
1175 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1176 | is allowed to be optional. */ | |
1177 | ||
1178 | static symbolS * | |
1179 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1180 | { | |
1181 | addressT align = 0; | |
1182 | ||
1183 | SKIP_WHITESPACE (); | |
1184 | ||
7ab9ffdd | 1185 | if (needs_align |
a6c24e68 NC |
1186 | && *input_line_pointer == ',') |
1187 | { | |
1188 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1189 | |
a6c24e68 NC |
1190 | if (align == (addressT) -1) |
1191 | return NULL; | |
1192 | } | |
1193 | else | |
1194 | { | |
1195 | if (size >= 8) | |
1196 | align = 3; | |
1197 | else if (size >= 4) | |
1198 | align = 2; | |
1199 | else if (size >= 2) | |
1200 | align = 1; | |
1201 | else | |
1202 | align = 0; | |
1203 | } | |
1204 | ||
1205 | bss_alloc (symbolP, size, align); | |
1206 | return symbolP; | |
1207 | } | |
1208 | ||
704209c0 | 1209 | static void |
a6c24e68 NC |
1210 | pe_lcomm (int needs_align) |
1211 | { | |
1212 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1213 | } | |
704209c0 | 1214 | #endif |
a6c24e68 | 1215 | |
29b0f896 AM |
1216 | const pseudo_typeS md_pseudo_table[] = |
1217 | { | |
1218 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1219 | {"align", s_align_bytes, 0}, | |
1220 | #else | |
1221 | {"align", s_align_ptwo, 0}, | |
1222 | #endif | |
1223 | {"arch", set_cpu_arch, 0}, | |
d4064aad | 1224 | #ifdef OBJ_AOUT |
29b0f896 | 1225 | {"bss", s_bss, 0}, |
d4064aad JB |
1226 | #endif |
1227 | #ifdef I386COFF | |
a6c24e68 | 1228 | {"lcomm", pe_lcomm, 1}, |
29b0f896 AM |
1229 | #endif |
1230 | {"ffloat", float_cons, 'f'}, | |
1231 | {"dfloat", float_cons, 'd'}, | |
1232 | {"tfloat", float_cons, 'x'}, | |
7d19d096 | 1233 | {"hfloat", float_cons, 'h'}, |
de133cf9 | 1234 | {"bfloat16", float_cons, 'b'}, |
29b0f896 | 1235 | {"value", cons, 2}, |
d182319b | 1236 | {"slong", signed_cons, 4}, |
edd67638 | 1237 | {"insn", s_insn, 0}, |
1e7dd4a0 | 1238 | {"noopt", s_noopt, 0}, |
29b0f896 AM |
1239 | {"optim", s_ignore, 0}, |
1240 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1241 | {"code16", set_code_flag, CODE_16BIT}, | |
1242 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1243 | #ifdef BFD64 |
29b0f896 | 1244 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1245 | #endif |
29b0f896 AM |
1246 | {"intel_syntax", set_intel_syntax, 1}, |
1247 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1248 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1249 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1250 | {"allow_index_reg", set_allow_index_reg, 1}, |
1251 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1252 | {"sse_check", set_check, 0}, |
1253 | {"operand_check", set_check, 1}, | |
3b22753a L |
1254 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1255 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1256 | #else |
68d20676 | 1257 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1258 | {"loc", dwarf2_directive_loc, 0}, |
1259 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1260 | #endif |
6482c264 NC |
1261 | #ifdef TE_PE |
1262 | {"secrel32", pe_directive_secrel, 0}, | |
145667f8 | 1263 | {"secidx", pe_directive_secidx, 0}, |
6482c264 | 1264 | #endif |
29b0f896 AM |
1265 | {0, 0, 0} |
1266 | }; | |
1267 | ||
1268 | /* For interface with expression (). */ | |
1269 | extern char *input_line_pointer; | |
1270 | ||
1271 | /* Hash table for instruction mnemonic lookup. */ | |
629310ab | 1272 | static htab_t op_hash; |
29b0f896 AM |
1273 | |
1274 | /* Hash table for register lookup. */ | |
629310ab | 1275 | static htab_t reg_hash; |
29b0f896 | 1276 | \f |
ce8a8b2f AM |
1277 | /* Various efficient no-op patterns for aligning code labels. |
1278 | Note: Don't try to assemble the instructions in the comments. | |
1279 | 0L and 0w are not legal. */ | |
62a02d25 L |
1280 | static const unsigned char f32_1[] = |
1281 | {0x90}; /* nop */ | |
1282 | static const unsigned char f32_2[] = | |
1283 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1284 | static const unsigned char f32_3[] = | |
1285 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
ad9f3230 JB |
1286 | #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */ |
1287 | static const unsigned char f32_5[] = | |
1288 | {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */ | |
62a02d25 L |
1289 | static const unsigned char f32_6[] = |
1290 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
ad9f3230 JB |
1291 | #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */ |
1292 | static const unsigned char f32_8[] = | |
1293 | {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */ | |
d164359d JB |
1294 | static const unsigned char f64_3[] = |
1295 | {0x48,0x89,0xf6}; /* mov %rsi,%rsi */ | |
1296 | static const unsigned char f64_4[] = | |
1297 | {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */ | |
1298 | #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */ | |
1299 | static const unsigned char f64_6[] = | |
1300 | {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */ | |
1301 | static const unsigned char f64_7[] = | |
1302 | {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */ | |
1303 | #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */ | |
1304 | static const unsigned char f64_9[] = | |
1305 | {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */ | |
5e0729b6 | 1306 | #define f16_2 (f64_3 + 1) /* mov %si,%si */ |
62a02d25 | 1307 | static const unsigned char f16_3[] = |
3ae729d5 | 1308 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
ad9f3230 JB |
1309 | #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */ |
1310 | static const unsigned char f16_5[] = | |
1311 | {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */ | |
3ae729d5 L |
1312 | static const unsigned char jump_disp8[] = |
1313 | {0xeb}; /* jmp disp8 */ | |
1314 | static const unsigned char jump32_disp32[] = | |
1315 | {0xe9}; /* jmp disp32 */ | |
1316 | static const unsigned char jump16_disp32[] = | |
1317 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1318 | /* 32-bit NOPs patterns. */ |
1319 | static const unsigned char *const f32_patt[] = { | |
ad9f3230 | 1320 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8 |
62a02d25 | 1321 | }; |
d164359d JB |
1322 | /* 64-bit NOPs patterns. */ |
1323 | static const unsigned char *const f64_patt[] = { | |
1324 | f32_1, f32_2, f64_3, f64_4, f64_5, f64_6, f64_7, f64_8, f64_9 | |
1325 | }; | |
62a02d25 L |
1326 | /* 16-bit NOPs patterns. */ |
1327 | static const unsigned char *const f16_patt[] = { | |
ad9f3230 | 1328 | f32_1, f16_2, f16_3, f16_4, f16_5 |
62a02d25 L |
1329 | }; |
1330 | /* nopl (%[re]ax) */ | |
1331 | static const unsigned char alt_3[] = | |
1332 | {0x0f,0x1f,0x00}; | |
1333 | /* nopl 0(%[re]ax) */ | |
1334 | static const unsigned char alt_4[] = | |
1335 | {0x0f,0x1f,0x40,0x00}; | |
1336 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1337 | #define alt_5 (alt_6 + 1) |
62a02d25 L |
1338 | /* nopw 0(%[re]ax,%[re]ax,1) */ |
1339 | static const unsigned char alt_6[] = | |
1340 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1341 | /* nopl 0L(%[re]ax) */ | |
1342 | static const unsigned char alt_7[] = | |
1343 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1344 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1345 | #define alt_8 (alt_9 + 1) |
62a02d25 L |
1346 | /* nopw 0L(%[re]ax,%[re]ax,1) */ |
1347 | static const unsigned char alt_9[] = | |
1348 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1349 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1350 | #define alt_10 (alt_11 + 1) |
3ae729d5 L |
1351 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1352 | static const unsigned char alt_11[] = | |
1353 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1354 | /* 32-bit and 64-bit NOPs patterns. */ |
1355 | static const unsigned char *const alt_patt[] = { | |
1356 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1357 | alt_9, alt_10, alt_11 |
62a02d25 | 1358 | }; |
bf649e72 L |
1359 | #define alt64_9 (alt64_15 + 6) /* nopq 0L(%rax,%rax,1) */ |
1360 | #define alt64_10 (alt64_15 + 5) /* cs nopq 0L(%rax,%rax,1) */ | |
1361 | /* data16 cs nopq 0L(%rax,%rax,1) */ | |
1362 | #define alt64_11 (alt64_15 + 4) | |
1363 | /* data16 data16 cs nopq 0L(%rax,%rax,1) */ | |
1364 | #define alt64_12 (alt64_15 + 3) | |
1365 | /* data16 data16 data16 cs nopq 0L(%rax,%rax,1) */ | |
1366 | #define alt64_13 (alt64_15 + 2) | |
1367 | /* data16 data16 data16 data16 cs nopq 0L(%rax,%rax,1) */ | |
1368 | #define alt64_14 (alt64_15 + 1) | |
1369 | /* data16 data16 data16 data16 data16 cs nopq 0L(%rax,%rax,1) */ | |
1370 | static const unsigned char alt64_15[] = | |
1371 | {0x66,0x66,0x66,0x66,0x66,0x2e,0x48, | |
1372 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1373 | /* Long 64-bit NOPs patterns. */ | |
1374 | static const unsigned char *const alt64_patt[] = { | |
1375 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1376 | alt64_9, alt64_10, alt64_11,alt64_12, alt64_13, alt64_14, alt64_15 | |
1377 | }; | |
62a02d25 L |
1378 | |
1379 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1380 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1381 | ||
1382 | static void | |
1383 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1384 | int count, int max_single_nop_size) | |
1385 | ||
1386 | { | |
3ae729d5 L |
1387 | /* Place the longer NOP first. */ |
1388 | int last; | |
1389 | int offset; | |
3076e594 NC |
1390 | const unsigned char *nops; |
1391 | ||
1392 | if (max_single_nop_size < 1) | |
1393 | { | |
1394 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1395 | max_single_nop_size); | |
1396 | return; | |
1397 | } | |
1398 | ||
1399 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1400 | last = count % max_single_nop_size; |
1401 | ||
1402 | count -= last; | |
1403 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1404 | memcpy (where + offset, nops, max_single_nop_size); | |
1405 | ||
1406 | if (last) | |
1407 | { | |
1408 | nops = patt[last - 1]; | |
ad9f3230 | 1409 | memcpy (where + offset, nops, last); |
3ae729d5 | 1410 | } |
62a02d25 L |
1411 | } |
1412 | ||
3ae729d5 L |
1413 | static INLINE int |
1414 | fits_in_imm7 (offsetT num) | |
1415 | { | |
1416 | return (num & 0x7f) == num; | |
1417 | } | |
1418 | ||
1419 | static INLINE int | |
1420 | fits_in_imm31 (offsetT num) | |
1421 | { | |
1422 | return (num & 0x7fffffff) == num; | |
1423 | } | |
62a02d25 L |
1424 | |
1425 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1426 | single NOP instruction LIMIT. */ | |
1427 | ||
1428 | void | |
3ae729d5 | 1429 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1430 | { |
3ae729d5 | 1431 | const unsigned char *const *patt = NULL; |
62a02d25 | 1432 | int max_single_nop_size; |
3ae729d5 L |
1433 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1434 | int max_number_of_nops; | |
62a02d25 | 1435 | |
3ae729d5 | 1436 | switch (fragP->fr_type) |
62a02d25 | 1437 | { |
3ae729d5 L |
1438 | case rs_fill_nop: |
1439 | case rs_align_code: | |
1440 | break; | |
e379e5f3 L |
1441 | case rs_machine_dependent: |
1442 | /* Allow NOP padding for jumps and calls. */ | |
1443 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1444 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1445 | break; | |
1446 | /* Fall through. */ | |
3ae729d5 | 1447 | default: |
62a02d25 L |
1448 | return; |
1449 | } | |
1450 | ||
ccc9c027 L |
1451 | /* We need to decide which NOP sequence to use for 32bit and |
1452 | 64bit. When -mtune= is used: | |
4eed87de | 1453 | |
c8be4b6f | 1454 | 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and |
76bc74dc | 1455 | PROCESSOR_GENERIC32, f32_patt will be used. |
80b8656c L |
1456 | 2. For the rest, alt_patt will be used. |
1457 | ||
1458 | When -mtune= isn't used, alt_patt will be used if | |
d164359d | 1459 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will |
76bc74dc | 1460 | be used. |
ccc9c027 L |
1461 | |
1462 | When -march= or .arch is used, we can't use anything beyond | |
1463 | cpu_arch_isa_flags. */ | |
1464 | ||
d12c7ab8 | 1465 | if (fragP->tc_frag_data.code == CODE_16BIT) |
ccc9c027 | 1466 | { |
3ae729d5 L |
1467 | patt = f16_patt; |
1468 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1469 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1470 | max_number_of_nops = 2; | |
252b5132 | 1471 | } |
33fef721 | 1472 | else |
ccc9c027 | 1473 | { |
d164359d | 1474 | patt = fragP->tc_frag_data.code == CODE_64BIT ? f64_patt : f32_patt; |
fbf3f584 | 1475 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 | 1476 | { |
cd75cd85 JB |
1477 | /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless |
1478 | explicitly disabled. */ | |
d12c7ab8 | 1479 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1480 | { |
1481 | case PROCESSOR_UNKNOWN: | |
1482 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 | 1483 | optimize with nops. */ |
9f314ead | 1484 | if (fragP->tc_frag_data.isanop) |
80b8656c | 1485 | patt = alt_patt; |
ccc9c027 | 1486 | break; |
c8be4b6f | 1487 | |
ef05d495 | 1488 | case PROCESSOR_CORE: |
76bc74dc | 1489 | case PROCESSOR_CORE2: |
bd5295b2 | 1490 | case PROCESSOR_COREI7: |
bf649e72 L |
1491 | if (fragP->tc_frag_data.cpunop) |
1492 | { | |
1493 | if (fragP->tc_frag_data.code == CODE_64BIT) | |
1494 | patt = alt64_patt; | |
1495 | else | |
1496 | patt = alt_patt; | |
1497 | } | |
1498 | break; | |
1499 | ||
1500 | case PROCESSOR_PENTIUMPRO: | |
1501 | case PROCESSOR_PENTIUM4: | |
1502 | case PROCESSOR_NOCONA: | |
76bc74dc | 1503 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1504 | case PROCESSOR_K6: |
1505 | case PROCESSOR_ATHLON: | |
1506 | case PROCESSOR_K8: | |
4eed87de | 1507 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1508 | case PROCESSOR_BD: |
029f3522 | 1509 | case PROCESSOR_ZNVER: |
7b458c12 | 1510 | case PROCESSOR_BT: |
cd75cd85 JB |
1511 | if (fragP->tc_frag_data.cpunop) |
1512 | patt = alt_patt; | |
ccc9c027 | 1513 | break; |
cd75cd85 | 1514 | |
76bc74dc | 1515 | case PROCESSOR_I386: |
ccc9c027 L |
1516 | case PROCESSOR_I486: |
1517 | case PROCESSOR_PENTIUM: | |
c8be4b6f | 1518 | case PROCESSOR_I686: |
81486035 | 1519 | case PROCESSOR_IAMCU: |
ccc9c027 | 1520 | case PROCESSOR_GENERIC32: |
ccc9c027 | 1521 | break; |
c368d2a8 JB |
1522 | case PROCESSOR_NONE: |
1523 | abort (); | |
4eed87de | 1524 | } |
ccc9c027 L |
1525 | } |
1526 | else | |
1527 | { | |
fbf3f584 | 1528 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1529 | { |
1530 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1531 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1532 | PROCESSOR_UNKNOWN. */ |
1533 | abort (); | |
1534 | break; | |
1535 | ||
cd75cd85 | 1536 | default: |
ccc9c027 | 1537 | /* We use cpu_arch_isa_flags to check if we CAN optimize |
22109423 | 1538 | with nops. */ |
9f314ead | 1539 | if (fragP->tc_frag_data.isanop) |
80b8656c | 1540 | patt = alt_patt; |
ccc9c027 | 1541 | break; |
cd75cd85 | 1542 | |
c368d2a8 JB |
1543 | case PROCESSOR_NONE: |
1544 | abort (); | |
4eed87de | 1545 | } |
ccc9c027 L |
1546 | } |
1547 | ||
bf649e72 | 1548 | if (patt != alt_patt && patt != alt64_patt) |
76bc74dc | 1549 | { |
d164359d JB |
1550 | max_single_nop_size = patt == f32_patt ? ARRAY_SIZE (f32_patt) |
1551 | : ARRAY_SIZE (f64_patt); | |
3ae729d5 L |
1552 | /* Limit number of NOPs to 2 for older processors. */ |
1553 | max_number_of_nops = 2; | |
76bc74dc L |
1554 | } |
1555 | else | |
1556 | { | |
bf649e72 L |
1557 | max_single_nop_size = patt == alt_patt |
1558 | ? ARRAY_SIZE (alt_patt) | |
1559 | : ARRAY_SIZE (alt64_patt); | |
3ae729d5 L |
1560 | /* Limit number of NOPs to 7 for newer processors. */ |
1561 | max_number_of_nops = 7; | |
1562 | } | |
1563 | } | |
1564 | ||
1565 | if (limit == 0) | |
1566 | limit = max_single_nop_size; | |
1567 | ||
1568 | if (fragP->fr_type == rs_fill_nop) | |
1569 | { | |
1570 | /* Output NOPs for .nop directive. */ | |
1571 | if (limit > max_single_nop_size) | |
1572 | { | |
1573 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1574 | _("invalid single nop size: %d " | |
1575 | "(expect within [0, %d])"), | |
1576 | limit, max_single_nop_size); | |
1577 | return; | |
1578 | } | |
1579 | } | |
e379e5f3 | 1580 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1581 | fragP->fr_var = count; |
1582 | ||
0aa5d0c9 JB |
1583 | /* Emit a plain NOP first when the last thing we saw may not have been |
1584 | a proper instruction (e.g. a stand-alone prefix or .byte). */ | |
1585 | if (!fragP->tc_frag_data.last_insn_normal) | |
1586 | { | |
1587 | *where++ = 0x90; | |
1588 | --count; | |
1589 | } | |
1590 | ||
3ae729d5 L |
1591 | if ((count / max_single_nop_size) > max_number_of_nops) |
1592 | { | |
1593 | /* Generate jump over NOPs. */ | |
1594 | offsetT disp = count - 2; | |
1595 | if (fits_in_imm7 (disp)) | |
1596 | { | |
1597 | /* Use "jmp disp8" if possible. */ | |
1598 | count = disp; | |
1599 | where[0] = jump_disp8[0]; | |
1600 | where[1] = count; | |
1601 | where += 2; | |
1602 | } | |
1603 | else | |
1604 | { | |
1605 | unsigned int size_of_jump; | |
1606 | ||
1607 | if (flag_code == CODE_16BIT) | |
1608 | { | |
1609 | where[0] = jump16_disp32[0]; | |
1610 | where[1] = jump16_disp32[1]; | |
1611 | size_of_jump = 2; | |
1612 | } | |
1613 | else | |
1614 | { | |
1615 | where[0] = jump32_disp32[0]; | |
1616 | size_of_jump = 1; | |
1617 | } | |
1618 | ||
1619 | count -= size_of_jump + 4; | |
1620 | if (!fits_in_imm31 (count)) | |
1621 | { | |
1622 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1623 | _("jump over nop padding out of range")); | |
1624 | return; | |
1625 | } | |
1626 | ||
1627 | md_number_to_chars (where + size_of_jump, count, 4); | |
1628 | where += size_of_jump + 4; | |
76bc74dc | 1629 | } |
ccc9c027 | 1630 | } |
3ae729d5 L |
1631 | |
1632 | /* Generate multiple NOPs. */ | |
1633 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1634 | } |
1635 | ||
c6fb90c8 | 1636 | static INLINE int |
0dfbf9d7 | 1637 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1638 | { |
0dfbf9d7 | 1639 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1640 | { |
1641 | case 3: | |
0dfbf9d7 | 1642 | if (x->array[2]) |
c6fb90c8 | 1643 | return 0; |
1a0670f3 | 1644 | /* Fall through. */ |
c6fb90c8 | 1645 | case 2: |
0dfbf9d7 | 1646 | if (x->array[1]) |
c6fb90c8 | 1647 | return 0; |
1a0670f3 | 1648 | /* Fall through. */ |
c6fb90c8 | 1649 | case 1: |
0dfbf9d7 | 1650 | return !x->array[0]; |
c6fb90c8 L |
1651 | default: |
1652 | abort (); | |
1653 | } | |
40fb9820 L |
1654 | } |
1655 | ||
c6fb90c8 | 1656 | static INLINE void |
0dfbf9d7 | 1657 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1658 | { |
0dfbf9d7 | 1659 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1660 | { |
1661 | case 3: | |
0dfbf9d7 | 1662 | x->array[2] = v; |
1a0670f3 | 1663 | /* Fall through. */ |
c6fb90c8 | 1664 | case 2: |
0dfbf9d7 | 1665 | x->array[1] = v; |
1a0670f3 | 1666 | /* Fall through. */ |
c6fb90c8 | 1667 | case 1: |
0dfbf9d7 | 1668 | x->array[0] = v; |
1a0670f3 | 1669 | /* Fall through. */ |
c6fb90c8 L |
1670 | break; |
1671 | default: | |
1672 | abort (); | |
1673 | } | |
bab6aec1 JB |
1674 | |
1675 | x->bitfield.class = ClassNone; | |
75e5731b | 1676 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1677 | } |
40fb9820 | 1678 | |
c6fb90c8 | 1679 | static INLINE int |
0dfbf9d7 L |
1680 | operand_type_equal (const union i386_operand_type *x, |
1681 | const union i386_operand_type *y) | |
c6fb90c8 | 1682 | { |
0dfbf9d7 | 1683 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1684 | { |
1685 | case 3: | |
0dfbf9d7 | 1686 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1687 | return 0; |
1a0670f3 | 1688 | /* Fall through. */ |
c6fb90c8 | 1689 | case 2: |
0dfbf9d7 | 1690 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1691 | return 0; |
1a0670f3 | 1692 | /* Fall through. */ |
c6fb90c8 | 1693 | case 1: |
0dfbf9d7 | 1694 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1695 | break; |
1696 | default: | |
1697 | abort (); | |
1698 | } | |
1699 | } | |
40fb9820 | 1700 | |
734dfd1c | 1701 | static INLINE bool |
a5e91879 | 1702 | _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu) |
734dfd1c JB |
1703 | { |
1704 | switch (cpu) | |
1705 | { | |
a5e91879 JB |
1706 | case Cpu287: return a->bitfield.cpu287; |
1707 | case Cpu387: return a->bitfield.cpu387; | |
1708 | case Cpu3dnow: return a->bitfield.cpu3dnow; | |
1709 | case Cpu3dnowA: return a->bitfield.cpu3dnowa; | |
1710 | case CpuAVX: return a->bitfield.cpuavx; | |
1711 | case CpuHLE: return a->bitfield.cpuhle; | |
1712 | case CpuAVX512F: return a->bitfield.cpuavx512f; | |
1713 | case CpuAVX512VL: return a->bitfield.cpuavx512vl; | |
80d61d8d | 1714 | case CpuAPX_F: return a->bitfield.cpuapx_f; |
a5e91879 JB |
1715 | case Cpu64: return a->bitfield.cpu64; |
1716 | case CpuNo64: return a->bitfield.cpuno64; | |
734dfd1c JB |
1717 | default: |
1718 | gas_assert (cpu < CpuAttrEnums); | |
1719 | } | |
a5e91879 JB |
1720 | return a->bitfield.isa == cpu + 1u; |
1721 | } | |
1722 | ||
1723 | static INLINE bool | |
1724 | is_cpu (const insn_template *t, enum i386_cpu cpu) | |
1725 | { | |
1726 | return _is_cpu(&t->cpu, cpu); | |
1727 | } | |
1728 | ||
1729 | static INLINE bool | |
1730 | maybe_cpu (const insn_template *t, enum i386_cpu cpu) | |
1731 | { | |
1732 | return _is_cpu(&t->cpu_any, cpu); | |
734dfd1c JB |
1733 | } |
1734 | ||
1735 | static i386_cpu_flags cpu_flags_from_attr (i386_cpu_attr a) | |
1736 | { | |
1737 | const unsigned int bps = sizeof (a.array[0]) * CHAR_BIT; | |
1738 | i386_cpu_flags f = { .array[0] = 0 }; | |
1739 | ||
a12915cc | 1740 | switch (ARRAY_SIZE (a.array)) |
734dfd1c JB |
1741 | { |
1742 | case 1: | |
1743 | f.array[CpuAttrEnums / bps] | |
a12915cc JB |
1744 | #ifndef WORDS_BIGENDIAN |
1745 | |= (a.array[0] >> CpuIsaBits) << (CpuAttrEnums % bps); | |
1746 | #else | |
1747 | |= (a.array[0] << CpuIsaBits) >> (CpuAttrEnums % bps); | |
1748 | #endif | |
1749 | if (CpuMax / bps > CpuAttrEnums / bps) | |
734dfd1c | 1750 | f.array[CpuAttrEnums / bps + 1] |
a12915cc | 1751 | #ifndef WORDS_BIGENDIAN |
734dfd1c | 1752 | = (a.array[0] >> CpuIsaBits) >> (bps - CpuAttrEnums % bps); |
a12915cc JB |
1753 | #else |
1754 | = (a.array[0] << CpuIsaBits) << (bps - CpuAttrEnums % bps); | |
1755 | #endif | |
734dfd1c | 1756 | break; |
a12915cc | 1757 | |
734dfd1c JB |
1758 | default: |
1759 | abort (); | |
1760 | } | |
1761 | ||
1762 | if (a.bitfield.isa) | |
a12915cc | 1763 | #ifndef WORDS_BIGENDIAN |
734dfd1c | 1764 | f.array[(a.bitfield.isa - 1) / bps] |= 1u << ((a.bitfield.isa - 1) % bps); |
a12915cc JB |
1765 | #else |
1766 | f.array[(a.bitfield.isa - 1) / bps] |= 1u << (~(a.bitfield.isa - 1) % bps); | |
1767 | #endif | |
734dfd1c JB |
1768 | |
1769 | return f; | |
1770 | } | |
1771 | ||
0dfbf9d7 L |
1772 | static INLINE int |
1773 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1774 | { | |
1775 | switch (ARRAY_SIZE(x->array)) | |
1776 | { | |
75f8266a KL |
1777 | case 5: |
1778 | if (x->array[4]) | |
1779 | return 0; | |
1780 | /* Fall through. */ | |
53467f57 IT |
1781 | case 4: |
1782 | if (x->array[3]) | |
1783 | return 0; | |
1784 | /* Fall through. */ | |
0dfbf9d7 L |
1785 | case 3: |
1786 | if (x->array[2]) | |
1787 | return 0; | |
1a0670f3 | 1788 | /* Fall through. */ |
0dfbf9d7 L |
1789 | case 2: |
1790 | if (x->array[1]) | |
1791 | return 0; | |
1a0670f3 | 1792 | /* Fall through. */ |
0dfbf9d7 L |
1793 | case 1: |
1794 | return !x->array[0]; | |
1795 | default: | |
1796 | abort (); | |
1797 | } | |
1798 | } | |
1799 | ||
0dfbf9d7 L |
1800 | static INLINE int |
1801 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1802 | const union i386_cpu_flags *y) | |
1803 | { | |
1804 | switch (ARRAY_SIZE(x->array)) | |
1805 | { | |
75f8266a KL |
1806 | case 5: |
1807 | if (x->array[4] != y->array[4]) | |
1808 | return 0; | |
1809 | /* Fall through. */ | |
53467f57 IT |
1810 | case 4: |
1811 | if (x->array[3] != y->array[3]) | |
1812 | return 0; | |
1813 | /* Fall through. */ | |
0dfbf9d7 L |
1814 | case 3: |
1815 | if (x->array[2] != y->array[2]) | |
1816 | return 0; | |
1a0670f3 | 1817 | /* Fall through. */ |
0dfbf9d7 L |
1818 | case 2: |
1819 | if (x->array[1] != y->array[1]) | |
1820 | return 0; | |
1a0670f3 | 1821 | /* Fall through. */ |
0dfbf9d7 L |
1822 | case 1: |
1823 | return x->array[0] == y->array[0]; | |
1824 | break; | |
1825 | default: | |
1826 | abort (); | |
1827 | } | |
1828 | } | |
c6fb90c8 L |
1829 | |
1830 | static INLINE int | |
c0260ac6 | 1831 | cpu_flags_check_cpu64 (const insn_template *t) |
c6fb90c8 | 1832 | { |
c0260ac6 JB |
1833 | return flag_code == CODE_64BIT |
1834 | ? !t->cpu.bitfield.cpuno64 | |
1835 | : !t->cpu.bitfield.cpu64; | |
40fb9820 L |
1836 | } |
1837 | ||
c6fb90c8 L |
1838 | static INLINE i386_cpu_flags |
1839 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1840 | { |
c6fb90c8 L |
1841 | switch (ARRAY_SIZE (x.array)) |
1842 | { | |
75f8266a KL |
1843 | case 5: |
1844 | x.array [4] &= y.array [4]; | |
1845 | /* Fall through. */ | |
53467f57 IT |
1846 | case 4: |
1847 | x.array [3] &= y.array [3]; | |
1848 | /* Fall through. */ | |
c6fb90c8 L |
1849 | case 3: |
1850 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1851 | /* Fall through. */ |
c6fb90c8 L |
1852 | case 2: |
1853 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1854 | /* Fall through. */ |
c6fb90c8 L |
1855 | case 1: |
1856 | x.array [0] &= y.array [0]; | |
1857 | break; | |
1858 | default: | |
1859 | abort (); | |
1860 | } | |
1861 | return x; | |
1862 | } | |
40fb9820 | 1863 | |
c6fb90c8 L |
1864 | static INLINE i386_cpu_flags |
1865 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1866 | { |
c6fb90c8 | 1867 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1868 | { |
75f8266a KL |
1869 | case 5: |
1870 | x.array [4] |= y.array [4]; | |
1871 | /* Fall through. */ | |
53467f57 IT |
1872 | case 4: |
1873 | x.array [3] |= y.array [3]; | |
1874 | /* Fall through. */ | |
c6fb90c8 L |
1875 | case 3: |
1876 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1877 | /* Fall through. */ |
c6fb90c8 L |
1878 | case 2: |
1879 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1880 | /* Fall through. */ |
c6fb90c8 L |
1881 | case 1: |
1882 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1883 | break; |
1884 | default: | |
1885 | abort (); | |
1886 | } | |
40fb9820 L |
1887 | return x; |
1888 | } | |
1889 | ||
309d3373 JB |
1890 | static INLINE i386_cpu_flags |
1891 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1892 | { | |
1893 | switch (ARRAY_SIZE (x.array)) | |
1894 | { | |
75f8266a KL |
1895 | case 5: |
1896 | x.array [4] &= ~y.array [4]; | |
1897 | /* Fall through. */ | |
53467f57 IT |
1898 | case 4: |
1899 | x.array [3] &= ~y.array [3]; | |
1900 | /* Fall through. */ | |
309d3373 JB |
1901 | case 3: |
1902 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1903 | /* Fall through. */ |
309d3373 JB |
1904 | case 2: |
1905 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1906 | /* Fall through. */ |
309d3373 JB |
1907 | case 1: |
1908 | x.array [0] &= ~y.array [0]; | |
1909 | break; | |
1910 | default: | |
1911 | abort (); | |
1912 | } | |
1913 | return x; | |
1914 | } | |
1915 | ||
6c0946d0 JB |
1916 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1917 | ||
6177c84d | 1918 | static INLINE bool need_evex_encoding (const insn_template *t) |
a6f3add0 | 1919 | { |
e346d50a JB |
1920 | return i.encoding == encoding_evex |
1921 | || i.encoding == encoding_evex512 | |
eb3f3841 | 1922 | || (t->opcode_modifier.vex && i.encoding == encoding_egpr) |
a6f3add0 JB |
1923 | || i.mask.reg; |
1924 | } | |
1925 | ||
c0f3af97 L |
1926 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1927 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1928 | ||
c0f3af97 | 1929 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1930 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1931 | |
1932 | /* Return CPU flags match bits. */ | |
3629bb00 | 1933 | |
40fb9820 | 1934 | static int |
d3ce72d0 | 1935 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1936 | { |
a5e91879 JB |
1937 | i386_cpu_flags cpu, active, all = cpu_flags_from_attr (t->cpu); |
1938 | i386_cpu_flags any = cpu_flags_from_attr (t->cpu_any); | |
c0260ac6 | 1939 | int match = cpu_flags_check_cpu64 (t) ? CPU_FLAGS_64BIT_MATCH : 0; |
40fb9820 | 1940 | |
a5e91879 JB |
1941 | all.bitfield.cpu64 = 0; |
1942 | all.bitfield.cpuno64 = 0; | |
1943 | gas_assert (!any.bitfield.cpu64); | |
1944 | gas_assert (!any.bitfield.cpuno64); | |
40fb9820 | 1945 | |
a5e91879 | 1946 | if (cpu_flags_all_zero (&all) && cpu_flags_all_zero (&any)) |
c0f3af97 L |
1947 | { |
1948 | /* This instruction is available on all archs. */ | |
a5e91879 | 1949 | return match | CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1950 | } |
3e624fa4 | 1951 | |
a5e91879 | 1952 | /* This instruction is available only on some archs. */ |
3629bb00 | 1953 | |
a5e91879 JB |
1954 | /* Dual VEX/EVEX templates may need stripping of one of the flags. */ |
1955 | if (t->opcode_modifier.vex && t->opcode_modifier.evex) | |
1956 | { | |
1957 | /* Dual AVX/AVX512 templates need to retain AVX512* only if we already | |
1958 | know that EVEX encoding will be needed. */ | |
1959 | if ((any.bitfield.cpuavx || any.bitfield.cpuavx2 || any.bitfield.cpufma) | |
1960 | && (any.bitfield.cpuavx512f || any.bitfield.cpuavx512vl)) | |
a6f3add0 | 1961 | { |
6177c84d | 1962 | if (need_evex_encoding (t)) |
a6f3add0 | 1963 | { |
a5e91879 JB |
1964 | any.bitfield.cpuavx = 0; |
1965 | any.bitfield.cpuavx2 = 0; | |
1966 | any.bitfield.cpufma = 0; | |
1967 | } | |
6177c84d | 1968 | /* need_evex_encoding(t) isn't reliable before operands were |
a5e91879 JB |
1969 | parsed. */ |
1970 | else if (i.operands) | |
1971 | { | |
1972 | any.bitfield.cpuavx512f = 0; | |
1973 | any.bitfield.cpuavx512vl = 0; | |
a6f3add0 JB |
1974 | } |
1975 | } | |
7c3df3c6 JB |
1976 | |
1977 | /* Dual non-APX/APX templates need massaging from what APX_F() in the | |
1978 | opcode table has produced. While the direct transformation of the | |
1979 | incoming cpuid&(cpuid|APX_F) would be to cpuid&(cpuid) / cpuid&(APX_F) | |
1980 | respectively, it's cheaper to move to just cpuid / cpuid&APX_F | |
1981 | instead. */ | |
1982 | if (any.bitfield.cpuapx_f | |
1983 | && (any.bitfield.cpubmi || any.bitfield.cpubmi2 | |
1984 | || any.bitfield.cpuavx512f || any.bitfield.cpuavx512bw | |
1985 | || any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile | |
5190fa38 | 1986 | || any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr)) |
7c3df3c6 JB |
1987 | { |
1988 | /* These checks (verifying that APX_F() was properly used in the | |
1989 | opcode table entry) make sure there's no need for an "else" to | |
1990 | the "if()" below. */ | |
1991 | gas_assert (!cpu_flags_all_zero (&all)); | |
1992 | cpu = cpu_flags_and (all, any); | |
1993 | gas_assert (cpu_flags_equal (&cpu, &all)); | |
1994 | ||
1995 | if (need_evex_encoding (t)) | |
1996 | all = any; | |
1997 | ||
1998 | memset (&any, 0, sizeof (any)); | |
1999 | } | |
a5e91879 | 2000 | } |
a6f3add0 | 2001 | |
a5e91879 JB |
2002 | if (flag_code != CODE_64BIT) |
2003 | active = cpu_flags_and_not (cpu_arch_flags, cpu_64_flags); | |
2004 | else | |
2005 | active = cpu_arch_flags; | |
2006 | cpu = cpu_flags_and (all, active); | |
2007 | if (cpu_flags_equal (&cpu, &all)) | |
2008 | { | |
22c36940 JB |
2009 | /* AVX and AVX2 present at the same time express an operand size |
2010 | dependency - strip AVX2 for the purposes here. The operand size | |
2011 | dependent check occurs in check_vecOperands(). */ | |
a5e91879 JB |
2012 | if (any.bitfield.cpuavx && any.bitfield.cpuavx2) |
2013 | any.bitfield.cpuavx2 = 0; | |
22c36940 | 2014 | |
a5e91879 JB |
2015 | cpu = cpu_flags_and (any, active); |
2016 | if (cpu_flags_all_zero (&any) || !cpu_flags_all_zero (&cpu)) | |
b58829cd | 2017 | match |= CPU_FLAGS_ARCH_MATCH; |
3629bb00 | 2018 | } |
c0f3af97 | 2019 | return match; |
40fb9820 L |
2020 | } |
2021 | ||
c6fb90c8 L |
2022 | static INLINE i386_operand_type |
2023 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 2024 | { |
bab6aec1 JB |
2025 | if (x.bitfield.class != y.bitfield.class) |
2026 | x.bitfield.class = ClassNone; | |
75e5731b JB |
2027 | if (x.bitfield.instance != y.bitfield.instance) |
2028 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 2029 | |
c6fb90c8 L |
2030 | switch (ARRAY_SIZE (x.array)) |
2031 | { | |
2032 | case 3: | |
2033 | x.array [2] &= y.array [2]; | |
1a0670f3 | 2034 | /* Fall through. */ |
c6fb90c8 L |
2035 | case 2: |
2036 | x.array [1] &= y.array [1]; | |
1a0670f3 | 2037 | /* Fall through. */ |
c6fb90c8 L |
2038 | case 1: |
2039 | x.array [0] &= y.array [0]; | |
2040 | break; | |
2041 | default: | |
2042 | abort (); | |
2043 | } | |
2044 | return x; | |
40fb9820 L |
2045 | } |
2046 | ||
73053c1f JB |
2047 | static INLINE i386_operand_type |
2048 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
2049 | { | |
bab6aec1 | 2050 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2051 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2052 | |
73053c1f JB |
2053 | switch (ARRAY_SIZE (x.array)) |
2054 | { | |
2055 | case 3: | |
2056 | x.array [2] &= ~y.array [2]; | |
2057 | /* Fall through. */ | |
2058 | case 2: | |
2059 | x.array [1] &= ~y.array [1]; | |
2060 | /* Fall through. */ | |
2061 | case 1: | |
2062 | x.array [0] &= ~y.array [0]; | |
2063 | break; | |
2064 | default: | |
2065 | abort (); | |
2066 | } | |
2067 | return x; | |
2068 | } | |
2069 | ||
c6fb90c8 L |
2070 | static INLINE i386_operand_type |
2071 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 2072 | { |
bab6aec1 JB |
2073 | gas_assert (x.bitfield.class == ClassNone || |
2074 | y.bitfield.class == ClassNone || | |
2075 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
2076 | gas_assert (x.bitfield.instance == InstanceNone || |
2077 | y.bitfield.instance == InstanceNone || | |
2078 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 2079 | |
c6fb90c8 | 2080 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 2081 | { |
c6fb90c8 L |
2082 | case 3: |
2083 | x.array [2] |= y.array [2]; | |
1a0670f3 | 2084 | /* Fall through. */ |
c6fb90c8 L |
2085 | case 2: |
2086 | x.array [1] |= y.array [1]; | |
1a0670f3 | 2087 | /* Fall through. */ |
c6fb90c8 L |
2088 | case 1: |
2089 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2090 | break; |
2091 | default: | |
2092 | abort (); | |
2093 | } | |
c6fb90c8 L |
2094 | return x; |
2095 | } | |
40fb9820 | 2096 | |
c6fb90c8 L |
2097 | static INLINE i386_operand_type |
2098 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2099 | { | |
bab6aec1 | 2100 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2101 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2102 | |
c6fb90c8 L |
2103 | switch (ARRAY_SIZE (x.array)) |
2104 | { | |
2105 | case 3: | |
2106 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2107 | /* Fall through. */ |
c6fb90c8 L |
2108 | case 2: |
2109 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2110 | /* Fall through. */ |
c6fb90c8 L |
2111 | case 1: |
2112 | x.array [0] ^= y.array [0]; | |
2113 | break; | |
2114 | default: | |
2115 | abort (); | |
2116 | } | |
40fb9820 L |
2117 | return x; |
2118 | } | |
2119 | ||
05909f23 JB |
2120 | static const i386_operand_type anydisp = { |
2121 | .bitfield = { .disp8 = 1, .disp16 = 1, .disp32 = 1, .disp64 = 1 } | |
2122 | }; | |
40fb9820 L |
2123 | |
2124 | enum operand_type | |
2125 | { | |
2126 | reg, | |
40fb9820 L |
2127 | imm, |
2128 | disp, | |
2129 | anymem | |
2130 | }; | |
2131 | ||
c6fb90c8 | 2132 | static INLINE int |
40fb9820 L |
2133 | operand_type_check (i386_operand_type t, enum operand_type c) |
2134 | { | |
2135 | switch (c) | |
2136 | { | |
2137 | case reg: | |
bab6aec1 | 2138 | return t.bitfield.class == Reg; |
40fb9820 | 2139 | |
40fb9820 L |
2140 | case imm: |
2141 | return (t.bitfield.imm8 | |
2142 | || t.bitfield.imm8s | |
2143 | || t.bitfield.imm16 | |
2144 | || t.bitfield.imm32 | |
2145 | || t.bitfield.imm32s | |
2146 | || t.bitfield.imm64); | |
2147 | ||
2148 | case disp: | |
2149 | return (t.bitfield.disp8 | |
2150 | || t.bitfield.disp16 | |
2151 | || t.bitfield.disp32 | |
40fb9820 L |
2152 | || t.bitfield.disp64); |
2153 | ||
2154 | case anymem: | |
2155 | return (t.bitfield.disp8 | |
2156 | || t.bitfield.disp16 | |
2157 | || t.bitfield.disp32 | |
40fb9820 L |
2158 | || t.bitfield.disp64 |
2159 | || t.bitfield.baseindex); | |
2160 | ||
2161 | default: | |
2162 | abort (); | |
2163 | } | |
2cfe26b6 AM |
2164 | |
2165 | return 0; | |
40fb9820 L |
2166 | } |
2167 | ||
7a54636a L |
2168 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2169 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2170 | |
2171 | static INLINE int | |
7a54636a L |
2172 | match_operand_size (const insn_template *t, unsigned int wanted, |
2173 | unsigned int given) | |
5c07affc | 2174 | { |
3ac21baa JB |
2175 | return !((i.types[given].bitfield.byte |
2176 | && !t->operand_types[wanted].bitfield.byte) | |
2177 | || (i.types[given].bitfield.word | |
2178 | && !t->operand_types[wanted].bitfield.word) | |
2179 | || (i.types[given].bitfield.dword | |
2180 | && !t->operand_types[wanted].bitfield.dword) | |
2181 | || (i.types[given].bitfield.qword | |
9db83a32 JB |
2182 | && (!t->operand_types[wanted].bitfield.qword |
2183 | /* Don't allow 64-bit (memory) operands outside of 64-bit | |
2184 | mode, when they're used where a 64-bit GPR could also | |
2185 | be used. Checking is needed for Intel Syntax only. */ | |
2186 | || (intel_syntax | |
2187 | && flag_code != CODE_64BIT | |
2188 | && (t->operand_types[wanted].bitfield.class == Reg | |
2189 | || t->operand_types[wanted].bitfield.class == Accum | |
2190 | || t->opcode_modifier.isstring)))) | |
3ac21baa JB |
2191 | || (i.types[given].bitfield.tbyte |
2192 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2193 | } |
2194 | ||
dd40ce22 L |
2195 | /* Return 1 if there is no conflict in SIMD register between operand |
2196 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2197 | |
2198 | static INLINE int | |
dd40ce22 L |
2199 | match_simd_size (const insn_template *t, unsigned int wanted, |
2200 | unsigned int given) | |
1b54b8d7 | 2201 | { |
3ac21baa JB |
2202 | return !((i.types[given].bitfield.xmmword |
2203 | && !t->operand_types[wanted].bitfield.xmmword) | |
2204 | || (i.types[given].bitfield.ymmword | |
2205 | && !t->operand_types[wanted].bitfield.ymmword) | |
2206 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2207 | && !t->operand_types[wanted].bitfield.zmmword) |
2208 | || (i.types[given].bitfield.tmmword | |
2209 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2210 | } |
2211 | ||
7a54636a L |
2212 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2213 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2214 | |
2215 | static INLINE int | |
dd40ce22 L |
2216 | match_mem_size (const insn_template *t, unsigned int wanted, |
2217 | unsigned int given) | |
5c07affc | 2218 | { |
7a54636a | 2219 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2220 | && !((i.types[given].bitfield.unspecified |
5273a3cd | 2221 | && !i.broadcast.type |
a5748e0d | 2222 | && !i.broadcast.bytes |
3ac21baa JB |
2223 | && !t->operand_types[wanted].bitfield.unspecified) |
2224 | || (i.types[given].bitfield.fword | |
2225 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2226 | /* For scalar opcode templates to allow register and memory |
2227 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2228 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2229 | down-conversion vpmov*. */ | |
3528c362 | 2230 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2231 | && t->operand_types[wanted].bitfield.byte |
2232 | + t->operand_types[wanted].bitfield.word | |
2233 | + t->operand_types[wanted].bitfield.dword | |
2234 | + t->operand_types[wanted].bitfield.qword | |
2235 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2236 | ? (i.types[given].bitfield.xmmword |
2237 | || i.types[given].bitfield.ymmword | |
2238 | || i.types[given].bitfield.zmmword) | |
2239 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2240 | } |
2241 | ||
3ac21baa JB |
2242 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2243 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2244 | is no size conflict on any operands for the template with operands reversed | |
2245 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2246 | |
3ac21baa JB |
2247 | #define MATCH_STRAIGHT 1 |
2248 | #define MATCH_REVERSE 2 | |
2249 | ||
2250 | static INLINE unsigned int | |
d3ce72d0 | 2251 | operand_size_match (const insn_template *t) |
5c07affc | 2252 | { |
3ac21baa | 2253 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2254 | |
0cfa3eb3 | 2255 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2256 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2257 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2258 | return match; |
2259 | ||
2260 | /* Check memory and accumulator operand size. */ | |
2261 | for (j = 0; j < i.operands; j++) | |
2262 | { | |
3528c362 JB |
2263 | if (i.types[j].bitfield.class != Reg |
2264 | && i.types[j].bitfield.class != RegSIMD | |
255571cd | 2265 | && t->opcode_modifier.operandconstraint == ANY_SIZE) |
5c07affc L |
2266 | continue; |
2267 | ||
bab6aec1 | 2268 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2269 | && !match_operand_size (t, j, j)) |
5c07affc L |
2270 | { |
2271 | match = 0; | |
2272 | break; | |
2273 | } | |
2274 | ||
3528c362 | 2275 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2276 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2277 | { |
2278 | match = 0; | |
2279 | break; | |
2280 | } | |
2281 | ||
75e5731b | 2282 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2283 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2284 | { |
2285 | match = 0; | |
2286 | break; | |
2287 | } | |
2288 | ||
c48dadc9 | 2289 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2290 | { |
2291 | match = 0; | |
2292 | break; | |
2293 | } | |
2294 | } | |
2295 | ||
3ac21baa | 2296 | if (!t->opcode_modifier.d) |
7b94647a | 2297 | return match; |
5c07affc L |
2298 | |
2299 | /* Check reverse. */ | |
aa180741 | 2300 | gas_assert (i.operands >= 2); |
5c07affc | 2301 | |
f5eb1d70 | 2302 | for (j = 0; j < i.operands; j++) |
5c07affc | 2303 | { |
f5eb1d70 JB |
2304 | unsigned int given = i.operands - j - 1; |
2305 | ||
aa180741 | 2306 | /* For FMA4 and XOP insns VEX.W controls just the first two |
3083f376 | 2307 | register operands. And APX_F insns just swap the two source operands, |
2308 | with the 3rd one being the destination. */ | |
2309 | if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP) | |
2310 | || is_cpu (t, CpuAPX_F)) | |
8bd915b7 JB |
2311 | given = j < 2 ? 1 - j : j; |
2312 | ||
bab6aec1 | 2313 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2314 | && !match_operand_size (t, j, given)) |
7b94647a | 2315 | return match; |
5c07affc | 2316 | |
3528c362 | 2317 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2318 | && !match_simd_size (t, j, given)) |
7b94647a | 2319 | return match; |
dbbc8b7e | 2320 | |
75e5731b | 2321 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2322 | && (!match_operand_size (t, j, given) |
2323 | || !match_simd_size (t, j, given))) | |
7b94647a | 2324 | return match; |
dbbc8b7e | 2325 | |
f5eb1d70 | 2326 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
7b94647a | 2327 | return match; |
5c07affc L |
2328 | } |
2329 | ||
3ac21baa | 2330 | return match | MATCH_REVERSE; |
5c07affc L |
2331 | } |
2332 | ||
c6fb90c8 | 2333 | static INLINE int |
40fb9820 L |
2334 | operand_type_match (i386_operand_type overlap, |
2335 | i386_operand_type given) | |
2336 | { | |
2337 | i386_operand_type temp = overlap; | |
2338 | ||
7d5e4556 | 2339 | temp.bitfield.unspecified = 0; |
5c07affc L |
2340 | temp.bitfield.byte = 0; |
2341 | temp.bitfield.word = 0; | |
2342 | temp.bitfield.dword = 0; | |
2343 | temp.bitfield.fword = 0; | |
2344 | temp.bitfield.qword = 0; | |
2345 | temp.bitfield.tbyte = 0; | |
2346 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2347 | temp.bitfield.ymmword = 0; |
43234a1e | 2348 | temp.bitfield.zmmword = 0; |
260cd341 | 2349 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2350 | if (operand_type_all_zero (&temp)) |
891edac4 | 2351 | goto mismatch; |
40fb9820 | 2352 | |
6f2f06be | 2353 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2354 | return 1; |
2355 | ||
dc1e8a47 | 2356 | mismatch: |
a65babc9 | 2357 | i.error = operand_type_mismatch; |
891edac4 | 2358 | return 0; |
40fb9820 L |
2359 | } |
2360 | ||
7d5e4556 | 2361 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2362 | unless the expected operand type register overlap is null. |
8ee52bcf | 2363 | Intel syntax sized memory operands are also checked here. */ |
40fb9820 | 2364 | |
c6fb90c8 | 2365 | static INLINE int |
dc821c5f | 2366 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2367 | i386_operand_type t0, |
40fb9820 L |
2368 | i386_operand_type g1, |
2369 | i386_operand_type t1) | |
2370 | { | |
bab6aec1 | 2371 | if (g0.bitfield.class != Reg |
3528c362 | 2372 | && g0.bitfield.class != RegSIMD |
8ee52bcf JB |
2373 | && (g0.bitfield.unspecified |
2374 | || !operand_type_check (g0, anymem))) | |
40fb9820 L |
2375 | return 1; |
2376 | ||
bab6aec1 | 2377 | if (g1.bitfield.class != Reg |
3528c362 | 2378 | && g1.bitfield.class != RegSIMD |
8ee52bcf JB |
2379 | && (g1.bitfield.unspecified |
2380 | || !operand_type_check (g1, anymem))) | |
40fb9820 L |
2381 | return 1; |
2382 | ||
dc821c5f JB |
2383 | if (g0.bitfield.byte == g1.bitfield.byte |
2384 | && g0.bitfield.word == g1.bitfield.word | |
2385 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2386 | && g0.bitfield.qword == g1.bitfield.qword |
2387 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2388 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2389 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2390 | return 1; |
2391 | ||
c4d09633 JB |
2392 | /* If expectations overlap in no more than a single size, all is fine. */ |
2393 | g0 = operand_type_and (t0, t1); | |
2394 | if (g0.bitfield.byte | |
2395 | + g0.bitfield.word | |
2396 | + g0.bitfield.dword | |
2397 | + g0.bitfield.qword | |
2398 | + g0.bitfield.xmmword | |
2399 | + g0.bitfield.ymmword | |
2400 | + g0.bitfield.zmmword <= 1) | |
891edac4 L |
2401 | return 1; |
2402 | ||
a65babc9 | 2403 | i.error = register_type_mismatch; |
891edac4 L |
2404 | |
2405 | return 0; | |
40fb9820 L |
2406 | } |
2407 | ||
4c692bc7 JB |
2408 | static INLINE unsigned int |
2409 | register_number (const reg_entry *r) | |
2410 | { | |
2411 | unsigned int nr = r->reg_num; | |
2412 | ||
2413 | if (r->reg_flags & RegRex) | |
2414 | nr += 8; | |
2415 | ||
80d61d8d | 2416 | if (r->reg_flags & (RegVRex | RegRex2)) |
200cbe0f L |
2417 | nr += 16; |
2418 | ||
4c692bc7 JB |
2419 | return nr; |
2420 | } | |
2421 | ||
252b5132 | 2422 | static INLINE unsigned int |
40fb9820 | 2423 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2424 | { |
b5014f7a | 2425 | if (t.bitfield.disp8) |
40fb9820 L |
2426 | return 1; |
2427 | else if (t.bitfield.disp16 | |
a775efc8 | 2428 | || t.bitfield.disp32) |
40fb9820 L |
2429 | return 2; |
2430 | else | |
2431 | return 0; | |
252b5132 RH |
2432 | } |
2433 | ||
2434 | static INLINE int | |
65879393 | 2435 | fits_in_signed_byte (addressT num) |
252b5132 | 2436 | { |
65879393 | 2437 | return num + 0x80 <= 0xff; |
47926f60 | 2438 | } |
252b5132 RH |
2439 | |
2440 | static INLINE int | |
65879393 | 2441 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2442 | { |
65879393 | 2443 | return num <= 0xff; |
47926f60 | 2444 | } |
252b5132 RH |
2445 | |
2446 | static INLINE int | |
65879393 | 2447 | fits_in_unsigned_word (addressT num) |
252b5132 | 2448 | { |
65879393 | 2449 | return num <= 0xffff; |
47926f60 | 2450 | } |
252b5132 RH |
2451 | |
2452 | static INLINE int | |
65879393 | 2453 | fits_in_signed_word (addressT num) |
252b5132 | 2454 | { |
65879393 | 2455 | return num + 0x8000 <= 0xffff; |
47926f60 | 2456 | } |
2a962e6d | 2457 | |
3e73aa7c | 2458 | static INLINE int |
65879393 | 2459 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2460 | { |
2461 | #ifndef BFD64 | |
2462 | return 1; | |
2463 | #else | |
65879393 | 2464 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2465 | #endif |
2466 | } /* fits_in_signed_long() */ | |
2a962e6d | 2467 | |
3e73aa7c | 2468 | static INLINE int |
65879393 | 2469 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2470 | { |
2471 | #ifndef BFD64 | |
2472 | return 1; | |
2473 | #else | |
65879393 | 2474 | return num <= 0xffffffff; |
3e73aa7c JH |
2475 | #endif |
2476 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2477 | |
a442cac5 JB |
2478 | static INLINE valueT extend_to_32bit_address (addressT num) |
2479 | { | |
2480 | #ifdef BFD64 | |
2481 | if (fits_in_unsigned_long(num)) | |
2482 | return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
2483 | ||
2484 | if (!fits_in_signed_long (num)) | |
2485 | return num & 0xffffffff; | |
2486 | #endif | |
2487 | ||
2488 | return num; | |
2489 | } | |
2490 | ||
43234a1e | 2491 | static INLINE int |
b5014f7a | 2492 | fits_in_disp8 (offsetT num) |
43234a1e L |
2493 | { |
2494 | int shift = i.memshift; | |
2495 | unsigned int mask; | |
2496 | ||
2497 | if (shift == -1) | |
2498 | abort (); | |
2499 | ||
2500 | mask = (1 << shift) - 1; | |
2501 | ||
2502 | /* Return 0 if NUM isn't properly aligned. */ | |
2503 | if ((num & mask)) | |
2504 | return 0; | |
2505 | ||
2506 | /* Check if NUM will fit in 8bit after shift. */ | |
2507 | return fits_in_signed_byte (num >> shift); | |
2508 | } | |
2509 | ||
a683cc34 SP |
2510 | static INLINE int |
2511 | fits_in_imm4 (offsetT num) | |
2512 | { | |
0ff3b7d0 | 2513 | /* Despite the name, check for imm3 if we're dealing with EVEX. */ |
eb3f3841 JB |
2514 | return (num & (i.encoding != encoding_evex |
2515 | && i.encoding != encoding_egpr ? 0xf : 7)) == num; | |
a683cc34 SP |
2516 | } |
2517 | ||
40fb9820 | 2518 | static i386_operand_type |
e3bb37b5 | 2519 | smallest_imm_type (offsetT num) |
252b5132 | 2520 | { |
40fb9820 | 2521 | i386_operand_type t; |
7ab9ffdd | 2522 | |
0dfbf9d7 | 2523 | operand_type_set (&t, 0); |
40fb9820 L |
2524 | t.bitfield.imm64 = 1; |
2525 | ||
2526 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2527 | { |
2528 | /* This code is disabled on the 486 because all the Imm1 forms | |
2529 | in the opcode table are slower on the i486. They're the | |
2530 | versions with the implicitly specified single-position | |
2531 | displacement, which has another syntax if you really want to | |
2532 | use that form. */ | |
40fb9820 L |
2533 | t.bitfield.imm1 = 1; |
2534 | t.bitfield.imm8 = 1; | |
2535 | t.bitfield.imm8s = 1; | |
2536 | t.bitfield.imm16 = 1; | |
2537 | t.bitfield.imm32 = 1; | |
2538 | t.bitfield.imm32s = 1; | |
2539 | } | |
2540 | else if (fits_in_signed_byte (num)) | |
2541 | { | |
c34d1cc9 JB |
2542 | if (fits_in_unsigned_byte (num)) |
2543 | t.bitfield.imm8 = 1; | |
40fb9820 L |
2544 | t.bitfield.imm8s = 1; |
2545 | t.bitfield.imm16 = 1; | |
8170af78 HL |
2546 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2547 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2548 | t.bitfield.imm32s = 1; |
2549 | } | |
2550 | else if (fits_in_unsigned_byte (num)) | |
2551 | { | |
2552 | t.bitfield.imm8 = 1; | |
2553 | t.bitfield.imm16 = 1; | |
2554 | t.bitfield.imm32 = 1; | |
2555 | t.bitfield.imm32s = 1; | |
2556 | } | |
2557 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2558 | { | |
2559 | t.bitfield.imm16 = 1; | |
8170af78 HL |
2560 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2561 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2562 | t.bitfield.imm32s = 1; |
2563 | } | |
2564 | else if (fits_in_signed_long (num)) | |
2565 | { | |
8170af78 HL |
2566 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2567 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2568 | t.bitfield.imm32s = 1; |
2569 | } | |
2570 | else if (fits_in_unsigned_long (num)) | |
2571 | t.bitfield.imm32 = 1; | |
2572 | ||
2573 | return t; | |
47926f60 | 2574 | } |
252b5132 | 2575 | |
847f7ad4 | 2576 | static offsetT |
e3bb37b5 | 2577 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2578 | { |
508866be | 2579 | addressT mask; |
ba2adb93 | 2580 | |
847f7ad4 AM |
2581 | switch (size) |
2582 | { | |
508866be L |
2583 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2584 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3e73aa7c | 2585 | #ifdef BFD64 |
64965897 | 2586 | case 4: mask = ((addressT) 1 << 32) - 1; break; |
3e73aa7c | 2587 | #endif |
64965897 | 2588 | case sizeof (val): return val; |
47926f60 | 2589 | default: abort (); |
847f7ad4 AM |
2590 | } |
2591 | ||
4fe51f7d | 2592 | if ((val & ~mask) != 0 && (-val & ~mask) != 0) |
f493c217 AM |
2593 | as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64), |
2594 | (uint64_t) val, (uint64_t) (val & mask)); | |
847f7ad4 | 2595 | |
847f7ad4 AM |
2596 | return val & mask; |
2597 | } | |
2598 | ||
76d3f746 JB |
2599 | static INLINE const char *insn_name (const insn_template *t) |
2600 | { | |
5c139202 | 2601 | return &i386_mnemonics[t->mnem_off]; |
76d3f746 JB |
2602 | } |
2603 | ||
c32fa91d L |
2604 | enum PREFIX_GROUP |
2605 | { | |
2606 | PREFIX_EXIST = 0, | |
2607 | PREFIX_LOCK, | |
2608 | PREFIX_REP, | |
04ef582a | 2609 | PREFIX_DS, |
c32fa91d L |
2610 | PREFIX_OTHER |
2611 | }; | |
2612 | ||
2613 | /* Returns | |
2614 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2615 | same class already exists. | |
2616 | b. PREFIX_LOCK if lock prefix is added. | |
2617 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2618 | d. PREFIX_DS if ds prefix is added. |
2619 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2620 | */ |
2621 | ||
2622 | static enum PREFIX_GROUP | |
e3bb37b5 | 2623 | add_prefix (unsigned int prefix) |
252b5132 | 2624 | { |
c32fa91d | 2625 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2626 | unsigned int q; |
252b5132 | 2627 | |
29b0f896 AM |
2628 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2629 | && flag_code == CODE_64BIT) | |
b1905489 | 2630 | { |
161a04f6 | 2631 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2632 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2633 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2634 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2635 | ret = PREFIX_EXIST; |
b1905489 JB |
2636 | q = REX_PREFIX; |
2637 | } | |
3e73aa7c | 2638 | else |
b1905489 JB |
2639 | { |
2640 | switch (prefix) | |
2641 | { | |
2642 | default: | |
2643 | abort (); | |
2644 | ||
b1905489 | 2645 | case DS_PREFIX_OPCODE: |
04ef582a L |
2646 | ret = PREFIX_DS; |
2647 | /* Fall through. */ | |
2648 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2649 | case ES_PREFIX_OPCODE: |
2650 | case FS_PREFIX_OPCODE: | |
2651 | case GS_PREFIX_OPCODE: | |
2652 | case SS_PREFIX_OPCODE: | |
2653 | q = SEG_PREFIX; | |
2654 | break; | |
2655 | ||
2656 | case REPNE_PREFIX_OPCODE: | |
2657 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2658 | q = REP_PREFIX; |
2659 | ret = PREFIX_REP; | |
2660 | break; | |
2661 | ||
b1905489 | 2662 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2663 | q = LOCK_PREFIX; |
2664 | ret = PREFIX_LOCK; | |
b1905489 JB |
2665 | break; |
2666 | ||
2667 | case FWAIT_OPCODE: | |
2668 | q = WAIT_PREFIX; | |
2669 | break; | |
2670 | ||
2671 | case ADDR_PREFIX_OPCODE: | |
2672 | q = ADDR_PREFIX; | |
2673 | break; | |
2674 | ||
2675 | case DATA_PREFIX_OPCODE: | |
2676 | q = DATA_PREFIX; | |
2677 | break; | |
2678 | } | |
2679 | if (i.prefix[q] != 0) | |
c32fa91d | 2680 | ret = PREFIX_EXIST; |
b1905489 | 2681 | } |
252b5132 | 2682 | |
b1905489 | 2683 | if (ret) |
252b5132 | 2684 | { |
b1905489 JB |
2685 | if (!i.prefix[q]) |
2686 | ++i.prefixes; | |
2687 | i.prefix[q] |= prefix; | |
252b5132 | 2688 | } |
b1905489 JB |
2689 | else |
2690 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2691 | |
252b5132 RH |
2692 | return ret; |
2693 | } | |
2694 | ||
2695 | static void | |
78f12dd3 | 2696 | update_code_flag (int value, int check) |
eecb386c | 2697 | { |
b44fef84 JB |
2698 | PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad; |
2699 | ||
da5f9eb4 | 2700 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpu64 ) |
b44fef84 JB |
2701 | { |
2702 | as_error (_("64bit mode not supported on `%s'."), | |
2703 | cpu_arch_name ? cpu_arch_name : default_arch); | |
2704 | return; | |
2705 | } | |
2706 | ||
2707 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) | |
2708 | { | |
2709 | as_error (_("32bit mode not supported on `%s'."), | |
2710 | cpu_arch_name ? cpu_arch_name : default_arch); | |
2711 | return; | |
2712 | } | |
78f12dd3 | 2713 | |
1e9cc1c2 | 2714 | flag_code = (enum flag_code) value; |
b44fef84 | 2715 | |
eecb386c AM |
2716 | stackop_size = '\0'; |
2717 | } | |
2718 | ||
78f12dd3 L |
2719 | static void |
2720 | set_code_flag (int value) | |
2721 | { | |
2722 | update_code_flag (value, 0); | |
2723 | } | |
2724 | ||
eecb386c | 2725 | static void |
e3bb37b5 | 2726 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2727 | { |
1e9cc1c2 | 2728 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2729 | if (flag_code != CODE_16BIT) |
2730 | abort (); | |
9306ca4a | 2731 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2732 | } |
2733 | ||
213f15cf JB |
2734 | static void |
2735 | _set_intel_syntax (int syntax_flag) | |
2736 | { | |
2737 | intel_syntax = syntax_flag; | |
2738 | ||
2739 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); | |
2740 | ||
2741 | register_prefix = allow_naked_reg ? "" : "%"; | |
2742 | } | |
2743 | ||
252b5132 | 2744 | static void |
e3bb37b5 | 2745 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2746 | { |
2747 | /* Find out if register prefixing is specified. */ | |
2748 | int ask_naked_reg = 0; | |
2749 | ||
2750 | SKIP_WHITESPACE (); | |
29b0f896 | 2751 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2752 | { |
d02603dc NC |
2753 | char *string; |
2754 | int e = get_symbol_name (&string); | |
252b5132 | 2755 | |
47926f60 | 2756 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2757 | ask_naked_reg = 1; |
47926f60 | 2758 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2759 | ask_naked_reg = -1; |
2760 | else | |
d0b47220 | 2761 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2762 | (void) restore_line_pointer (e); |
252b5132 RH |
2763 | } |
2764 | demand_empty_rest_of_line (); | |
c3332e24 | 2765 | |
252b5132 | 2766 | if (ask_naked_reg == 0) |
213f15cf | 2767 | allow_naked_reg = (syntax_flag |
f86103b7 | 2768 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 RH |
2769 | else |
2770 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2771 | |
213f15cf | 2772 | _set_intel_syntax (syntax_flag); |
252b5132 RH |
2773 | } |
2774 | ||
1efbbeb4 L |
2775 | static void |
2776 | set_intel_mnemonic (int mnemonic_flag) | |
2777 | { | |
e1d4d893 | 2778 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2779 | } |
2780 | ||
db51cc60 L |
2781 | static void |
2782 | set_allow_index_reg (int flag) | |
2783 | { | |
2784 | allow_index_reg = flag; | |
2785 | } | |
2786 | ||
cb19c032 | 2787 | static void |
7bab8ab5 | 2788 | set_check (int what) |
cb19c032 | 2789 | { |
7bab8ab5 JB |
2790 | enum check_kind *kind; |
2791 | const char *str; | |
2792 | ||
2793 | if (what) | |
2794 | { | |
2795 | kind = &operand_check; | |
2796 | str = "operand"; | |
2797 | } | |
2798 | else | |
2799 | { | |
2800 | kind = &sse_check; | |
2801 | str = "sse"; | |
2802 | } | |
2803 | ||
cb19c032 L |
2804 | SKIP_WHITESPACE (); |
2805 | ||
2806 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2807 | { | |
d02603dc NC |
2808 | char *string; |
2809 | int e = get_symbol_name (&string); | |
cb19c032 L |
2810 | |
2811 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2812 | *kind = check_none; |
cb19c032 | 2813 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2814 | *kind = check_warning; |
cb19c032 | 2815 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2816 | *kind = check_error; |
cb19c032 | 2817 | else |
7bab8ab5 | 2818 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2819 | (void) restore_line_pointer (e); |
cb19c032 L |
2820 | } |
2821 | else | |
7bab8ab5 | 2822 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2823 | |
2824 | demand_empty_rest_of_line (); | |
2825 | } | |
2826 | ||
8a9036a4 L |
2827 | static void |
2828 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2829 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2830 | { |
2831 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2832 | static const char *arch; | |
2833 | ||
c085ab00 | 2834 | /* Intel MCU is only supported on ELF. */ |
8a9036a4 L |
2835 | if (!IS_ELF) |
2836 | return; | |
2837 | ||
2838 | if (!arch) | |
2839 | { | |
2840 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2841 | use default_arch. */ | |
2842 | arch = cpu_arch_name; | |
2843 | if (!arch) | |
2844 | arch = default_arch; | |
2845 | } | |
2846 | ||
81486035 | 2847 | /* If we are targeting Intel MCU, we must enable it. */ |
648d04db JB |
2848 | if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU) |
2849 | == new_flag.bitfield.cpuiamcu) | |
81486035 L |
2850 | return; |
2851 | ||
8a9036a4 L |
2852 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2853 | #endif | |
2854 | } | |
2855 | ||
8180707f | 2856 | static void |
bd483d21 | 2857 | extend_cpu_sub_arch_name (const char *pfx, const char *name) |
8180707f JB |
2858 | { |
2859 | if (cpu_sub_arch_name) | |
2860 | cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name, | |
bd483d21 | 2861 | pfx, name, (const char *) NULL); |
8180707f | 2862 | else |
bd483d21 JB |
2863 | cpu_sub_arch_name = concat (pfx, name, (const char *) NULL); |
2864 | } | |
2865 | ||
2866 | static void isa_enable (unsigned int idx) | |
2867 | { | |
2868 | i386_cpu_flags flags = cpu_flags_or (cpu_arch_flags, cpu_arch[idx].enable); | |
2869 | ||
2870 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2871 | { | |
2872 | extend_cpu_sub_arch_name (".", cpu_arch[idx].name); | |
2873 | cpu_arch_flags = flags; | |
2874 | } | |
2875 | ||
2876 | cpu_arch_isa_flags = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[idx].enable); | |
2877 | } | |
2878 | ||
2879 | static void isa_disable (unsigned int idx) | |
2880 | { | |
2881 | i386_cpu_flags flags | |
2882 | = cpu_flags_and_not (cpu_arch_flags, cpu_arch[idx].disable); | |
2883 | ||
2884 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2885 | { | |
2886 | extend_cpu_sub_arch_name (".no", cpu_arch[idx].name); | |
2887 | cpu_arch_flags = flags; | |
2888 | } | |
2889 | ||
2890 | cpu_arch_isa_flags | |
2891 | = cpu_flags_and_not (cpu_arch_isa_flags, cpu_arch[idx].disable); | |
8180707f JB |
2892 | } |
2893 | ||
e413e4e9 | 2894 | static void |
e3bb37b5 | 2895 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2896 | { |
f68697e8 JB |
2897 | typedef struct arch_stack_entry |
2898 | { | |
2899 | const struct arch_stack_entry *prev; | |
2900 | const char *name; | |
2901 | char *sub_name; | |
2902 | i386_cpu_flags flags; | |
2903 | i386_cpu_flags isa_flags; | |
2904 | enum processor_type isa; | |
2905 | enum flag_code flag_code; | |
4fc85f37 | 2906 | unsigned int vector_size; |
f68697e8 JB |
2907 | char stackop_size; |
2908 | bool no_cond_jump_promotion; | |
2909 | } arch_stack_entry; | |
2910 | static const arch_stack_entry *arch_stack_top; | |
dfab07b9 JB |
2911 | char *s; |
2912 | int e; | |
2913 | const char *string; | |
2914 | unsigned int j = 0; | |
f68697e8 | 2915 | |
47926f60 | 2916 | SKIP_WHITESPACE (); |
e413e4e9 | 2917 | |
dfab07b9 JB |
2918 | if (is_end_of_line[(unsigned char) *input_line_pointer]) |
2919 | { | |
2920 | as_bad (_("missing cpu architecture")); | |
2921 | input_line_pointer++; | |
2922 | return; | |
2923 | } | |
2924 | ||
2925 | e = get_symbol_name (&s); | |
2926 | string = s; | |
2927 | ||
2928 | if (strcmp (string, "push") == 0) | |
e413e4e9 | 2929 | { |
dfab07b9 | 2930 | arch_stack_entry *top = XNEW (arch_stack_entry); |
e413e4e9 | 2931 | |
dfab07b9 JB |
2932 | top->name = cpu_arch_name; |
2933 | if (cpu_sub_arch_name) | |
2934 | top->sub_name = xstrdup (cpu_sub_arch_name); | |
2935 | else | |
2936 | top->sub_name = NULL; | |
2937 | top->flags = cpu_arch_flags; | |
2938 | top->isa = cpu_arch_isa; | |
2939 | top->isa_flags = cpu_arch_isa_flags; | |
2940 | top->flag_code = flag_code; | |
4fc85f37 | 2941 | top->vector_size = vector_size; |
dfab07b9 JB |
2942 | top->stackop_size = stackop_size; |
2943 | top->no_cond_jump_promotion = no_cond_jump_promotion; | |
2944 | ||
2945 | top->prev = arch_stack_top; | |
2946 | arch_stack_top = top; | |
2947 | ||
2948 | (void) restore_line_pointer (e); | |
2949 | demand_empty_rest_of_line (); | |
2950 | return; | |
2951 | } | |
2952 | ||
2953 | if (strcmp (string, "pop") == 0) | |
2954 | { | |
2955 | const arch_stack_entry *top = arch_stack_top; | |
2956 | ||
2957 | if (!top) | |
2958 | as_bad (_(".arch stack is empty")); | |
2959 | else if (top->flag_code != flag_code | |
2960 | || top->stackop_size != stackop_size) | |
2961 | { | |
2962 | static const unsigned int bits[] = { | |
2963 | [CODE_16BIT] = 16, | |
2964 | [CODE_32BIT] = 32, | |
2965 | [CODE_64BIT] = 64, | |
2966 | }; | |
2967 | ||
2968 | as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"), | |
2969 | bits[top->flag_code], | |
2970 | top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : ""); | |
2971 | } | |
2972 | else | |
3ce2ebcf | 2973 | { |
dfab07b9 JB |
2974 | arch_stack_top = top->prev; |
2975 | ||
2976 | cpu_arch_name = top->name; | |
2977 | free (cpu_sub_arch_name); | |
2978 | cpu_sub_arch_name = top->sub_name; | |
2979 | cpu_arch_flags = top->flags; | |
2980 | cpu_arch_isa = top->isa; | |
2981 | cpu_arch_isa_flags = top->isa_flags; | |
4fc85f37 | 2982 | vector_size = top->vector_size; |
dfab07b9 JB |
2983 | no_cond_jump_promotion = top->no_cond_jump_promotion; |
2984 | ||
2985 | XDELETE (top); | |
2986 | } | |
2987 | ||
2988 | (void) restore_line_pointer (e); | |
2989 | demand_empty_rest_of_line (); | |
2990 | return; | |
2991 | } | |
2992 | ||
2993 | if (strcmp (string, "default") == 0) | |
2994 | { | |
2995 | if (strcmp (default_arch, "iamcu") == 0) | |
2996 | string = default_arch; | |
2997 | else | |
2998 | { | |
2999 | static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS; | |
3000 | ||
3001 | cpu_arch_name = NULL; | |
3002 | free (cpu_sub_arch_name); | |
3003 | cpu_sub_arch_name = NULL; | |
3004 | cpu_arch_flags = cpu_unknown_flags; | |
dfab07b9 JB |
3005 | cpu_arch_isa = PROCESSOR_UNKNOWN; |
3006 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; | |
3007 | if (!cpu_arch_tune_set) | |
fb263707 | 3008 | cpu_arch_tune = PROCESSOR_UNKNOWN; |
dfab07b9 | 3009 | |
4fc85f37 JB |
3010 | vector_size = VSZ_DEFAULT; |
3011 | ||
dfab07b9 JB |
3012 | j = ARRAY_SIZE (cpu_arch) + 1; |
3013 | } | |
3014 | } | |
3015 | ||
3016 | for (; j < ARRAY_SIZE (cpu_arch); j++) | |
3017 | { | |
3018 | if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0 | |
3019 | && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE)) | |
3020 | { | |
3021 | if (*string != '.') | |
3022 | { | |
3023 | check_cpu_arch_compatible (string, cpu_arch[j].enable); | |
3ce2ebcf | 3024 | |
da5f9eb4 | 3025 | if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 ) |
1d07cfb4 JB |
3026 | { |
3027 | as_bad (_("64bit mode not supported on `%s'."), | |
3028 | cpu_arch[j].name); | |
3029 | (void) restore_line_pointer (e); | |
3030 | ignore_rest_of_line (); | |
3031 | return; | |
3032 | } | |
3033 | ||
3034 | if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386) | |
3035 | { | |
3036 | as_bad (_("32bit mode not supported on `%s'."), | |
3037 | cpu_arch[j].name); | |
3038 | (void) restore_line_pointer (e); | |
3039 | ignore_rest_of_line (); | |
3040 | return; | |
3041 | } | |
3042 | ||
dfab07b9 | 3043 | cpu_arch_name = cpu_arch[j].name; |
3ce2ebcf JB |
3044 | free (cpu_sub_arch_name); |
3045 | cpu_sub_arch_name = NULL; | |
dfab07b9 | 3046 | cpu_arch_flags = cpu_arch[j].enable; |
dfab07b9 JB |
3047 | cpu_arch_isa = cpu_arch[j].type; |
3048 | cpu_arch_isa_flags = cpu_arch[j].enable; | |
3ce2ebcf | 3049 | if (!cpu_arch_tune_set) |
fb263707 | 3050 | cpu_arch_tune = cpu_arch_isa; |
4fc85f37 JB |
3051 | |
3052 | vector_size = VSZ_DEFAULT; | |
3053 | ||
dfab07b9 JB |
3054 | pre_386_16bit_warned = false; |
3055 | break; | |
3ce2ebcf | 3056 | } |
f68697e8 | 3057 | |
dfab07b9 JB |
3058 | if (cpu_flags_all_zero (&cpu_arch[j].enable)) |
3059 | continue; | |
f68697e8 | 3060 | |
bd483d21 | 3061 | isa_enable (j); |
f68697e8 JB |
3062 | |
3063 | (void) restore_line_pointer (e); | |
4fc85f37 JB |
3064 | |
3065 | switch (cpu_arch[j].vsz) | |
3066 | { | |
3067 | default: | |
3068 | break; | |
3069 | ||
3070 | case vsz_set: | |
3071 | #ifdef SVR4_COMMENT_CHARS | |
3072 | if (*input_line_pointer == ':' || *input_line_pointer == '/') | |
3073 | #else | |
3074 | if (*input_line_pointer == '/') | |
3075 | #endif | |
3076 | { | |
3077 | ++input_line_pointer; | |
3078 | switch (get_absolute_expression ()) | |
3079 | { | |
3080 | case 512: vector_size = VSZ512; break; | |
3081 | case 256: vector_size = VSZ256; break; | |
3082 | case 128: vector_size = VSZ128; break; | |
3083 | default: | |
3084 | as_bad (_("Unrecognized vector size specifier")); | |
3085 | ignore_rest_of_line (); | |
3086 | return; | |
3087 | } | |
3088 | break; | |
3089 | } | |
3090 | /* Fall through. */ | |
3091 | case vsz_reset: | |
3092 | vector_size = VSZ_DEFAULT; | |
3093 | break; | |
3094 | } | |
3095 | ||
f68697e8 JB |
3096 | demand_empty_rest_of_line (); |
3097 | return; | |
3098 | } | |
dfab07b9 | 3099 | } |
3ce2ebcf | 3100 | |
dfab07b9 JB |
3101 | if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch)) |
3102 | { | |
3103 | /* Disable an ISA extension. */ | |
3104 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
3105 | if (cpu_arch[j].type == PROCESSOR_NONE | |
3106 | && strcmp (string + 3, cpu_arch[j].name) == 0) | |
3107 | { | |
bd483d21 | 3108 | isa_disable (j); |
e413e4e9 | 3109 | |
4fc85f37 JB |
3110 | if (cpu_arch[j].vsz == vsz_set) |
3111 | vector_size = VSZ_DEFAULT; | |
3112 | ||
dfab07b9 JB |
3113 | (void) restore_line_pointer (e); |
3114 | demand_empty_rest_of_line (); | |
3115 | return; | |
3116 | } | |
e413e4e9 | 3117 | } |
dfab07b9 JB |
3118 | |
3119 | if (j == ARRAY_SIZE (cpu_arch)) | |
3120 | as_bad (_("no such architecture: `%s'"), string); | |
3121 | ||
3122 | *input_line_pointer = e; | |
e413e4e9 | 3123 | |
fddf5b5b AM |
3124 | no_cond_jump_promotion = 0; |
3125 | if (*input_line_pointer == ',' | |
29b0f896 | 3126 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 3127 | { |
d02603dc | 3128 | ++input_line_pointer; |
dfab07b9 JB |
3129 | e = get_symbol_name (&s); |
3130 | string = s; | |
fddf5b5b AM |
3131 | |
3132 | if (strcmp (string, "nojumps") == 0) | |
3133 | no_cond_jump_promotion = 1; | |
3134 | else if (strcmp (string, "jumps") == 0) | |
3135 | ; | |
3136 | else | |
3137 | as_bad (_("no such architecture modifier: `%s'"), string); | |
3138 | ||
d02603dc | 3139 | (void) restore_line_pointer (e); |
fddf5b5b AM |
3140 | } |
3141 | ||
e413e4e9 AM |
3142 | demand_empty_rest_of_line (); |
3143 | } | |
3144 | ||
8a9036a4 L |
3145 | enum bfd_architecture |
3146 | i386_arch (void) | |
3147 | { | |
c085ab00 | 3148 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 | 3149 | { |
ed049bd6 | 3150 | if (!IS_ELF || flag_code == CODE_64BIT) |
81486035 L |
3151 | as_fatal (_("Intel MCU is 32bit ELF only")); |
3152 | return bfd_arch_iamcu; | |
3153 | } | |
8a9036a4 L |
3154 | else |
3155 | return bfd_arch_i386; | |
3156 | } | |
3157 | ||
b9d79e03 | 3158 | unsigned long |
7016a5d5 | 3159 | i386_mach (void) |
b9d79e03 | 3160 | { |
d34049e8 | 3161 | if (startswith (default_arch, "x86_64")) |
8a9036a4 | 3162 | { |
c085ab00 | 3163 | if (default_arch[6] == '\0') |
8a9036a4 | 3164 | return bfd_mach_x86_64; |
351f65ca L |
3165 | else |
3166 | return bfd_mach_x64_32; | |
8a9036a4 | 3167 | } |
5197d474 L |
3168 | else if (!strcmp (default_arch, "i386") |
3169 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
3170 | { |
3171 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
3172 | { | |
ed049bd6 | 3173 | if (!IS_ELF) |
81486035 L |
3174 | as_fatal (_("Intel MCU is 32bit ELF only")); |
3175 | return bfd_mach_i386_iamcu; | |
3176 | } | |
3177 | else | |
3178 | return bfd_mach_i386_i386; | |
3179 | } | |
b9d79e03 | 3180 | else |
2b5d6a91 | 3181 | as_fatal (_("unknown architecture")); |
b9d79e03 | 3182 | } |
b9d79e03 | 3183 | \f |
99f0fb12 JB |
3184 | #include "opcodes/i386-tbl.h" |
3185 | ||
d3b01414 JB |
3186 | static void |
3187 | op_lookup (const char *mnemonic) | |
3188 | { | |
3189 | i386_op_off_t *pos = str_hash_find (op_hash, mnemonic); | |
3190 | ||
3191 | if (pos != NULL) | |
3192 | { | |
3193 | current_templates.start = &i386_optab[pos[0]]; | |
3194 | current_templates.end = &i386_optab[pos[1]]; | |
3195 | } | |
3196 | else | |
3197 | current_templates.end = current_templates.start = NULL; | |
3198 | } | |
3199 | ||
252b5132 | 3200 | void |
7016a5d5 | 3201 | md_begin (void) |
252b5132 | 3202 | { |
86fa6981 L |
3203 | /* Support pseudo prefixes like {disp32}. */ |
3204 | lex_type ['{'] = LEX_BEGIN_NAME; | |
3205 | ||
47926f60 | 3206 | /* Initialize op_hash hash table. */ |
629310ab | 3207 | op_hash = str_htab_create (); |
252b5132 RH |
3208 | |
3209 | { | |
d3b01414 JB |
3210 | const i386_op_off_t *cur = i386_op_sets; |
3211 | const i386_op_off_t *end = cur + ARRAY_SIZE (i386_op_sets) - 1; | |
3212 | ||
3213 | for (; cur < end; ++cur) | |
3214 | if (str_hash_insert (op_hash, insn_name (&i386_optab[*cur]), cur, 0)) | |
3215 | as_fatal (_("duplicate %s"), insn_name (&i386_optab[*cur])); | |
252b5132 RH |
3216 | } |
3217 | ||
47926f60 | 3218 | /* Initialize reg_hash hash table. */ |
629310ab | 3219 | reg_hash = str_htab_create (); |
252b5132 | 3220 | { |
29b0f896 | 3221 | const reg_entry *regtab; |
c3fe08fa | 3222 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3223 | |
c3fe08fa | 3224 | for (regtab = i386_regtab; regtab_size--; regtab++) |
6225c532 | 3225 | { |
6288d05f JB |
3226 | switch (regtab->reg_type.bitfield.class) |
3227 | { | |
3228 | case Reg: | |
34684862 JB |
3229 | if (regtab->reg_type.bitfield.dword) |
3230 | { | |
3231 | if (regtab->reg_type.bitfield.instance == Accum) | |
3232 | reg_eax = regtab; | |
3233 | } | |
3234 | else if (regtab->reg_type.bitfield.tbyte) | |
6288d05f JB |
3235 | { |
3236 | /* There's no point inserting st(<N>) in the hash table, as | |
3237 | parentheses aren't included in register_chars[] anyway. */ | |
3238 | if (regtab->reg_type.bitfield.instance != Accum) | |
3239 | continue; | |
3240 | reg_st0 = regtab; | |
3241 | } | |
3242 | break; | |
3243 | ||
5e042380 JB |
3244 | case SReg: |
3245 | switch (regtab->reg_num) | |
3246 | { | |
3247 | case 0: reg_es = regtab; break; | |
3248 | case 2: reg_ss = regtab; break; | |
3249 | case 3: reg_ds = regtab; break; | |
3250 | } | |
3251 | break; | |
3252 | ||
6288d05f JB |
3253 | case RegMask: |
3254 | if (!regtab->reg_num) | |
3255 | reg_k0 = regtab; | |
3256 | break; | |
3257 | } | |
3258 | ||
6225c532 JB |
3259 | if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL) |
3260 | as_fatal (_("duplicate %s"), regtab->reg_name); | |
6225c532 | 3261 | } |
252b5132 RH |
3262 | } |
3263 | ||
47926f60 | 3264 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3265 | { |
29b0f896 | 3266 | int c; |
d2b1a14d | 3267 | const char *p; |
252b5132 RH |
3268 | |
3269 | for (c = 0; c < 256; c++) | |
3270 | { | |
014fbcda | 3271 | if (ISDIGIT (c) || ISLOWER (c)) |
252b5132 RH |
3272 | { |
3273 | mnemonic_chars[c] = c; | |
3274 | register_chars[c] = c; | |
3275 | operand_chars[c] = c; | |
3276 | } | |
3882b010 | 3277 | else if (ISUPPER (c)) |
252b5132 | 3278 | { |
3882b010 | 3279 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3280 | register_chars[c] = mnemonic_chars[c]; |
3281 | operand_chars[c] = c; | |
3282 | } | |
b3983e5f JB |
3283 | #ifdef SVR4_COMMENT_CHARS |
3284 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3285 | operand_chars[c] = c; | |
3286 | #endif | |
252b5132 | 3287 | |
4795cd4a JB |
3288 | if (c >= 128) |
3289 | operand_chars[c] = c; | |
252b5132 RH |
3290 | } |
3291 | ||
c0f3af97 | 3292 | mnemonic_chars['_'] = '_'; |
791fe849 | 3293 | mnemonic_chars['-'] = '-'; |
0003779b | 3294 | mnemonic_chars['.'] = '.'; |
252b5132 | 3295 | |
d2b1a14d JB |
3296 | for (p = extra_symbol_chars; *p != '\0'; p++) |
3297 | operand_chars[(unsigned char) *p] = *p; | |
252b5132 RH |
3298 | for (p = operand_special_chars; *p != '\0'; p++) |
3299 | operand_chars[(unsigned char) *p] = *p; | |
3300 | } | |
3301 | ||
fabb73d1 | 3302 | if (object_64bit) |
a4447b93 | 3303 | { |
ca19b261 KT |
3304 | #if defined (OBJ_COFF) && defined (TE_PE) |
3305 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3306 | ? 32 : 16); | |
3307 | #else | |
a4447b93 | 3308 | x86_dwarf2_return_column = 16; |
ca19b261 | 3309 | #endif |
61ff971f | 3310 | x86_cie_data_alignment = -8; |
b52c4ee4 | 3311 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
788b11d9 JB |
3312 | x86_sframe_cfa_sp_reg = REG_SP; |
3313 | x86_sframe_cfa_fp_reg = REG_FP; | |
b52c4ee4 | 3314 | #endif |
a4447b93 RH |
3315 | } |
3316 | else | |
3317 | { | |
3318 | x86_dwarf2_return_column = 8; | |
3319 | x86_cie_data_alignment = -4; | |
3320 | } | |
e379e5f3 L |
3321 | |
3322 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3323 | can be turned into BRANCH_PREFIX frag. */ | |
3324 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3325 | abort (); | |
252b5132 RH |
3326 | } |
3327 | ||
3328 | void | |
e3bb37b5 | 3329 | i386_print_statistics (FILE *file) |
252b5132 | 3330 | { |
629310ab ML |
3331 | htab_print_statistics (file, "i386 opcode", op_hash); |
3332 | htab_print_statistics (file, "i386 register", reg_hash); | |
252b5132 | 3333 | } |
654d6f31 AM |
3334 | |
3335 | void | |
3336 | i386_md_end (void) | |
3337 | { | |
3338 | htab_delete (op_hash); | |
3339 | htab_delete (reg_hash); | |
3340 | } | |
252b5132 | 3341 | \f |
252b5132 RH |
3342 | #ifdef DEBUG386 |
3343 | ||
ce8a8b2f | 3344 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3345 | static void pte (insn_template *); |
40fb9820 | 3346 | static void pt (i386_operand_type); |
e3bb37b5 L |
3347 | static void pe (expressionS *); |
3348 | static void ps (symbolS *); | |
252b5132 RH |
3349 | |
3350 | static void | |
2c703856 | 3351 | pi (const char *line, i386_insn *x) |
252b5132 | 3352 | { |
09137c09 | 3353 | unsigned int j; |
252b5132 RH |
3354 | |
3355 | fprintf (stdout, "%s: template ", line); | |
3356 | pte (&x->tm); | |
09f131f2 JH |
3357 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3358 | x->base_reg ? x->base_reg->reg_name : "none", | |
3359 | x->index_reg ? x->index_reg->reg_name : "none", | |
3360 | x->log2_scale_factor); | |
3361 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3362 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3363 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3364 | x->sib.base, x->sib.index, x->sib.scale); | |
3365 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3366 | (x->rex & REX_W) != 0, |
3367 | (x->rex & REX_R) != 0, | |
3368 | (x->rex & REX_X) != 0, | |
3369 | (x->rex & REX_B) != 0); | |
09137c09 | 3370 | for (j = 0; j < x->operands; j++) |
252b5132 | 3371 | { |
09137c09 SP |
3372 | fprintf (stdout, " #%d: ", j + 1); |
3373 | pt (x->types[j]); | |
252b5132 | 3374 | fprintf (stdout, "\n"); |
bab6aec1 | 3375 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3376 | || x->types[j].bitfield.class == RegMMX |
3377 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3378 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3379 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3380 | || x->types[j].bitfield.class == RegCR |
3381 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3382 | || x->types[j].bitfield.class == RegTR |
3383 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3384 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3385 | if (operand_type_check (x->types[j], imm)) | |
3386 | pe (x->op[j].imms); | |
3387 | if (operand_type_check (x->types[j], disp)) | |
3388 | pe (x->op[j].disps); | |
252b5132 RH |
3389 | } |
3390 | } | |
3391 | ||
3392 | static void | |
d3ce72d0 | 3393 | pte (insn_template *t) |
252b5132 | 3394 | { |
b933fa4b | 3395 | static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; |
441f6aca | 3396 | static const char *const opc_spc[] = { |
0cc78721 | 3397 | NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL, |
441f6aca JB |
3398 | "XOP08", "XOP09", "XOP0A", |
3399 | }; | |
09137c09 | 3400 | unsigned int j; |
441f6aca | 3401 | |
252b5132 | 3402 | fprintf (stdout, " %d operands ", t->operands); |
441f6aca JB |
3403 | if (opc_pfx[t->opcode_modifier.opcodeprefix]) |
3404 | fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]); | |
ddb62495 JB |
3405 | if (opc_spc[t->opcode_space]) |
3406 | fprintf (stdout, "space %s ", opc_spc[t->opcode_space]); | |
47926f60 | 3407 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3408 | if (t->extension_opcode != None) |
3409 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3410 | if (t->opcode_modifier.d) |
252b5132 | 3411 | fprintf (stdout, "D"); |
40fb9820 | 3412 | if (t->opcode_modifier.w) |
252b5132 RH |
3413 | fprintf (stdout, "W"); |
3414 | fprintf (stdout, "\n"); | |
09137c09 | 3415 | for (j = 0; j < t->operands; j++) |
252b5132 | 3416 | { |
09137c09 SP |
3417 | fprintf (stdout, " #%d type ", j + 1); |
3418 | pt (t->operand_types[j]); | |
252b5132 RH |
3419 | fprintf (stdout, "\n"); |
3420 | } | |
3421 | } | |
3422 | ||
3423 | static void | |
e3bb37b5 | 3424 | pe (expressionS *e) |
252b5132 | 3425 | { |
24eab124 | 3426 | fprintf (stdout, " operation %d\n", e->X_op); |
b8281767 AM |
3427 | fprintf (stdout, " add_number %" PRId64 " (%" PRIx64 ")\n", |
3428 | (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number); | |
252b5132 RH |
3429 | if (e->X_add_symbol) |
3430 | { | |
3431 | fprintf (stdout, " add_symbol "); | |
3432 | ps (e->X_add_symbol); | |
3433 | fprintf (stdout, "\n"); | |
3434 | } | |
3435 | if (e->X_op_symbol) | |
3436 | { | |
3437 | fprintf (stdout, " op_symbol "); | |
3438 | ps (e->X_op_symbol); | |
3439 | fprintf (stdout, "\n"); | |
3440 | } | |
3441 | } | |
3442 | ||
3443 | static void | |
e3bb37b5 | 3444 | ps (symbolS *s) |
252b5132 RH |
3445 | { |
3446 | fprintf (stdout, "%s type %s%s", | |
3447 | S_GET_NAME (s), | |
3448 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3449 | segment_name (S_GET_SEGMENT (s))); | |
3450 | } | |
3451 | ||
7b81dfbb | 3452 | static struct type_name |
252b5132 | 3453 | { |
40fb9820 L |
3454 | i386_operand_type mask; |
3455 | const char *name; | |
252b5132 | 3456 | } |
7b81dfbb | 3457 | const type_names[] = |
252b5132 | 3458 | { |
05909f23 JB |
3459 | { { .bitfield = { .class = Reg, .byte = 1 } }, "r8" }, |
3460 | { { .bitfield = { .class = Reg, .word = 1 } }, "r16" }, | |
3461 | { { .bitfield = { .class = Reg, .dword = 1 } }, "r32" }, | |
3462 | { { .bitfield = { .class = Reg, .qword = 1 } }, "r64" }, | |
3463 | { { .bitfield = { .instance = Accum, .byte = 1 } }, "acc8" }, | |
3464 | { { .bitfield = { .instance = Accum, .word = 1 } }, "acc16" }, | |
3465 | { { .bitfield = { .instance = Accum, .dword = 1 } }, "acc32" }, | |
3466 | { { .bitfield = { .instance = Accum, .qword = 1 } }, "acc64" }, | |
3467 | { { .bitfield = { .imm8 = 1 } }, "i8" }, | |
3468 | { { .bitfield = { .imm8s = 1 } }, "i8s" }, | |
3469 | { { .bitfield = { .imm16 = 1 } }, "i16" }, | |
3470 | { { .bitfield = { .imm32 = 1 } }, "i32" }, | |
3471 | { { .bitfield = { .imm32s = 1 } }, "i32s" }, | |
3472 | { { .bitfield = { .imm64 = 1 } }, "i64" }, | |
3473 | { { .bitfield = { .imm1 = 1 } }, "i1" }, | |
3474 | { { .bitfield = { .baseindex = 1 } }, "BaseIndex" }, | |
3475 | { { .bitfield = { .disp8 = 1 } }, "d8" }, | |
3476 | { { .bitfield = { .disp16 = 1 } }, "d16" }, | |
3477 | { { .bitfield = { .disp32 = 1 } }, "d32" }, | |
3478 | { { .bitfield = { .disp64 = 1 } }, "d64" }, | |
3479 | { { .bitfield = { .instance = RegD, .word = 1 } }, "InOutPortReg" }, | |
3480 | { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" }, | |
3481 | { { .bitfield = { .class = RegCR } }, "control reg" }, | |
3482 | { { .bitfield = { .class = RegTR } }, "test reg" }, | |
3483 | { { .bitfield = { .class = RegDR } }, "debug reg" }, | |
3484 | { { .bitfield = { .class = Reg, .tbyte = 1 } }, "FReg" }, | |
3485 | { { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" }, | |
3486 | { { .bitfield = { .class = SReg } }, "SReg" }, | |
3487 | { { .bitfield = { .class = RegMMX } }, "rMMX" }, | |
3488 | { { .bitfield = { .class = RegSIMD, .xmmword = 1 } }, "rXMM" }, | |
3489 | { { .bitfield = { .class = RegSIMD, .ymmword = 1 } }, "rYMM" }, | |
3490 | { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" }, | |
3491 | { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" }, | |
3492 | { { .bitfield = { .class = RegMask } }, "Mask reg" }, | |
252b5132 RH |
3493 | }; |
3494 | ||
3495 | static void | |
40fb9820 | 3496 | pt (i386_operand_type t) |
252b5132 | 3497 | { |
40fb9820 | 3498 | unsigned int j; |
c6fb90c8 | 3499 | i386_operand_type a; |
252b5132 | 3500 | |
40fb9820 | 3501 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3502 | { |
3503 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3504 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3505 | fprintf (stdout, "%s, ", type_names[j].name); |
3506 | } | |
252b5132 RH |
3507 | fflush (stdout); |
3508 | } | |
3509 | ||
3510 | #endif /* DEBUG386 */ | |
3511 | \f | |
252b5132 | 3512 | static bfd_reloc_code_real_type |
3956db08 | 3513 | reloc (unsigned int size, |
64e74474 AM |
3514 | int pcrel, |
3515 | int sign, | |
3516 | bfd_reloc_code_real_type other) | |
252b5132 | 3517 | { |
47926f60 | 3518 | if (other != NO_RELOC) |
3956db08 | 3519 | { |
91d6fa6a | 3520 | reloc_howto_type *rel; |
3956db08 JB |
3521 | |
3522 | if (size == 8) | |
3523 | switch (other) | |
3524 | { | |
64e74474 AM |
3525 | case BFD_RELOC_X86_64_GOT32: |
3526 | return BFD_RELOC_X86_64_GOT64; | |
3527 | break; | |
553d1284 L |
3528 | case BFD_RELOC_X86_64_GOTPLT64: |
3529 | return BFD_RELOC_X86_64_GOTPLT64; | |
3530 | break; | |
64e74474 AM |
3531 | case BFD_RELOC_X86_64_PLTOFF64: |
3532 | return BFD_RELOC_X86_64_PLTOFF64; | |
3533 | break; | |
3534 | case BFD_RELOC_X86_64_GOTPC32: | |
3535 | other = BFD_RELOC_X86_64_GOTPC64; | |
3536 | break; | |
3537 | case BFD_RELOC_X86_64_GOTPCREL: | |
3538 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3539 | break; | |
3540 | case BFD_RELOC_X86_64_TPOFF32: | |
3541 | other = BFD_RELOC_X86_64_TPOFF64; | |
3542 | break; | |
3543 | case BFD_RELOC_X86_64_DTPOFF32: | |
3544 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3545 | break; | |
3546 | default: | |
3547 | break; | |
3956db08 | 3548 | } |
e05278af | 3549 | |
8ce3d284 | 3550 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3551 | if (other == BFD_RELOC_SIZE32) |
3552 | { | |
3553 | if (size == 8) | |
1ab668bf | 3554 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3555 | if (pcrel) |
1ab668bf AM |
3556 | { |
3557 | as_bad (_("there are no pc-relative size relocations")); | |
3558 | return NO_RELOC; | |
3559 | } | |
8fd4256d | 3560 | } |
8ce3d284 | 3561 | #endif |
8fd4256d | 3562 | |
e05278af | 3563 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3564 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3565 | sign = -1; |
3566 | ||
91d6fa6a NC |
3567 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3568 | if (!rel) | |
3956db08 | 3569 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3570 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3571 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3572 | bfd_get_reloc_size (rel), |
3956db08 | 3573 | size); |
91d6fa6a | 3574 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3575 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3576 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3577 | && !sign) |
91d6fa6a | 3578 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3579 | && sign > 0)) |
3956db08 JB |
3580 | as_bad (_("relocated field and relocation type differ in signedness")); |
3581 | else | |
3582 | return other; | |
3583 | return NO_RELOC; | |
3584 | } | |
252b5132 RH |
3585 | |
3586 | if (pcrel) | |
3587 | { | |
3e73aa7c | 3588 | if (!sign) |
3956db08 | 3589 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3590 | switch (size) |
3591 | { | |
3592 | case 1: return BFD_RELOC_8_PCREL; | |
3593 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3594 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3595 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3596 | } |
3956db08 | 3597 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3598 | } |
3599 | else | |
3600 | { | |
3956db08 | 3601 | if (sign > 0) |
e5cb08ac | 3602 | switch (size) |
3e73aa7c JH |
3603 | { |
3604 | case 4: return BFD_RELOC_X86_64_32S; | |
3605 | } | |
3606 | else | |
3607 | switch (size) | |
3608 | { | |
3609 | case 1: return BFD_RELOC_8; | |
3610 | case 2: return BFD_RELOC_16; | |
3611 | case 4: return BFD_RELOC_32; | |
3612 | case 8: return BFD_RELOC_64; | |
3613 | } | |
3956db08 JB |
3614 | as_bad (_("cannot do %s %u byte relocation"), |
3615 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3616 | } |
3617 | ||
0cc9e1d3 | 3618 | return NO_RELOC; |
252b5132 RH |
3619 | } |
3620 | ||
071c5d81 | 3621 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
47926f60 KH |
3622 | /* Here we decide which fixups can be adjusted to make them relative to |
3623 | the beginning of the section instead of the symbol. Basically we need | |
3624 | to make sure that the dynamic relocations are done correctly, so in | |
3625 | some cases we force the original symbol to be used. */ | |
3626 | ||
252b5132 | 3627 | int |
071c5d81 | 3628 | tc_i386_fix_adjustable (fixS *fixP) |
252b5132 | 3629 | { |
718ddfc0 | 3630 | if (!IS_ELF) |
31312f95 AM |
3631 | return 1; |
3632 | ||
a161fe53 AM |
3633 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3634 | mode. */ | |
3635 | if (use_rela_relocations | |
3636 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3637 | && fixP->fx_pcrel) | |
252b5132 | 3638 | return 0; |
31312f95 | 3639 | |
8d01d9a9 AJ |
3640 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3641 | and changed later by validate_fix. */ | |
3642 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3643 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3644 | return 0; | |
3645 | ||
8fd4256d L |
3646 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3647 | for size relocations. */ | |
3648 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3649 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3650 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3651 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3652 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3653 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3654 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3655 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3656 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3657 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3658 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3659 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3660 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3661 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3662 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3663 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3664 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3665 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3666 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
3d5a60de | 3667 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX |
bffbf940 JJ |
3668 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3669 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3670 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3671 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 | 3672 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
a533c8df | 3673 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTTPOFF |
5bc71c2a | 3674 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_6_GOTTPOFF |
bffbf940 | 3675 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 |
d6ab8113 JB |
3676 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3677 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 | 3678 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
a533c8df | 3679 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC |
67a4f2b7 | 3680 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL |
252b5132 RH |
3681 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3682 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3683 | return 0; | |
3684 | return 1; | |
3685 | } | |
071c5d81 | 3686 | #endif |
252b5132 | 3687 | |
a9aabc23 JB |
3688 | static INLINE bool |
3689 | want_disp32 (const insn_template *t) | |
3690 | { | |
3691 | return flag_code != CODE_64BIT | |
3692 | || i.prefix[ADDR_PREFIX] | |
7fc69528 | 3693 | || (t->mnem_off == MN_lea |
fe134c65 JB |
3694 | && (!i.types[1].bitfield.qword |
3695 | || t->opcode_modifier.size == SIZE32)); | |
a9aabc23 JB |
3696 | } |
3697 | ||
b4cac588 | 3698 | static int |
e3bb37b5 | 3699 | intel_float_operand (const char *mnemonic) |
252b5132 | 3700 | { |
9306ca4a JB |
3701 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3702 | operands, hence the code here is free to improperly handle opcodes that | |
3703 | have no operands (for better performance and smaller code). */ | |
3704 | ||
3705 | if (mnemonic[0] != 'f') | |
3706 | return 0; /* non-math */ | |
3707 | ||
3708 | switch (mnemonic[1]) | |
3709 | { | |
3710 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3711 | the fs segment override prefix not currently handled because no | |
3712 | call path can make opcodes without operands get here */ | |
3713 | case 'i': | |
3714 | return 2 /* integer op */; | |
3715 | case 'l': | |
3716 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3717 | return 3; /* fldcw/fldenv */ | |
3718 | break; | |
3719 | case 'n': | |
3720 | if (mnemonic[2] != 'o' /* fnop */) | |
3721 | return 3; /* non-waiting control op */ | |
3722 | break; | |
3723 | case 'r': | |
3724 | if (mnemonic[2] == 's') | |
3725 | return 3; /* frstor/frstpm */ | |
3726 | break; | |
3727 | case 's': | |
3728 | if (mnemonic[2] == 'a') | |
3729 | return 3; /* fsave */ | |
3730 | if (mnemonic[2] == 't') | |
3731 | { | |
3732 | switch (mnemonic[3]) | |
3733 | { | |
3734 | case 'c': /* fstcw */ | |
3735 | case 'd': /* fstdw */ | |
3736 | case 'e': /* fstenv */ | |
3737 | case 's': /* fsts[gw] */ | |
3738 | return 3; | |
3739 | } | |
3740 | } | |
3741 | break; | |
3742 | case 'x': | |
3743 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3744 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3745 | break; | |
3746 | } | |
252b5132 | 3747 | |
9306ca4a | 3748 | return 1; |
252b5132 RH |
3749 | } |
3750 | ||
9a182d04 JB |
3751 | static INLINE void |
3752 | install_template (const insn_template *t) | |
3753 | { | |
3754 | unsigned int l; | |
3755 | ||
3756 | i.tm = *t; | |
3757 | ||
a6f3add0 JB |
3758 | /* Dual VEX/EVEX templates need stripping one of the possible variants. */ |
3759 | if (t->opcode_modifier.vex && t->opcode_modifier.evex) | |
6177c84d | 3760 | { |
a5e91879 JB |
3761 | if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2) |
3762 | || maybe_cpu (t, CpuFMA)) | |
3763 | && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL))) | |
a6f3add0 | 3764 | { |
6177c84d | 3765 | if (need_evex_encoding (t)) |
a6f3add0 JB |
3766 | { |
3767 | i.tm.opcode_modifier.vex = 0; | |
a5e91879 JB |
3768 | i.tm.cpu.bitfield.cpuavx512f = i.tm.cpu_any.bitfield.cpuavx512f; |
3769 | i.tm.cpu.bitfield.cpuavx512vl = i.tm.cpu_any.bitfield.cpuavx512vl; | |
a6f3add0 JB |
3770 | } |
3771 | else | |
3772 | { | |
3773 | i.tm.opcode_modifier.evex = 0; | |
a5e91879 JB |
3774 | if (i.tm.cpu_any.bitfield.cpuavx) |
3775 | i.tm.cpu.bitfield.cpuavx = 1; | |
3776 | else if (!i.tm.cpu.bitfield.isa) | |
3777 | i.tm.cpu.bitfield.isa = i.tm.cpu_any.bitfield.isa; | |
3778 | else | |
3779 | gas_assert (i.tm.cpu.bitfield.isa == i.tm.cpu_any.bitfield.isa); | |
a6f3add0 JB |
3780 | } |
3781 | } | |
6177c84d CL |
3782 | |
3783 | if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE) | |
3784 | || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ) | |
3785 | || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI) | |
5190fa38 | 3786 | || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)) |
6177c84d CL |
3787 | && maybe_cpu (t, CpuAPX_F)) |
3788 | { | |
3789 | if (need_evex_encoding (t)) | |
3790 | i.tm.opcode_modifier.vex = 0; | |
3791 | else | |
3792 | i.tm.opcode_modifier.evex = 0; | |
3793 | } | |
3794 | } | |
a6f3add0 | 3795 | |
9a182d04 JB |
3796 | /* Note that for pseudo prefixes this produces a length of 1. But for them |
3797 | the length isn't interesting at all. */ | |
3798 | for (l = 1; l < 4; ++l) | |
3799 | if (!(t->base_opcode >> (8 * l))) | |
3800 | break; | |
3801 | ||
3802 | i.opcode_length = l; | |
3803 | } | |
3804 | ||
c0f3af97 L |
3805 | /* Build the VEX prefix. */ |
3806 | ||
3807 | static void | |
d3ce72d0 | 3808 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3809 | { |
3810 | unsigned int register_specifier; | |
c0f3af97 | 3811 | unsigned int vector_length; |
03751133 | 3812 | unsigned int w; |
c0f3af97 L |
3813 | |
3814 | /* Check register specifier. */ | |
3815 | if (i.vex.register_specifier) | |
43234a1e L |
3816 | { |
3817 | register_specifier = | |
3818 | ~register_number (i.vex.register_specifier) & 0xf; | |
3819 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3820 | } | |
c0f3af97 L |
3821 | else |
3822 | register_specifier = 0xf; | |
3823 | ||
79f0fa25 L |
3824 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3825 | if there are more than 1 register operand. */ | |
3826 | if (i.reg_operands > 1 | |
e346d50a | 3827 | && i.encoding != encoding_vex3 |
86fa6981 | 3828 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3829 | && i.operands == i.reg_operands |
dbbc8b7e | 3830 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
ddb62495 | 3831 | && i.tm.opcode_space == SPACE_0F |
dbbc8b7e | 3832 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3833 | && i.rex == REX_B) |
3834 | { | |
67748abf | 3835 | unsigned int xchg; |
fa99fab2 | 3836 | |
67748abf | 3837 | swap_2_operands (0, i.operands - 1); |
fa99fab2 | 3838 | |
9c2799c2 | 3839 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3840 | |
3841 | i.rex = REX_R; | |
3842 | xchg = i.rm.regmem; | |
3843 | i.rm.regmem = i.rm.reg; | |
3844 | i.rm.reg = xchg; | |
3845 | ||
dbbc8b7e JB |
3846 | if (i.tm.opcode_modifier.d) |
3847 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
2c735193 | 3848 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
dbbc8b7e | 3849 | else /* Use the next insn. */ |
9a182d04 | 3850 | install_template (&t[1]); |
fa99fab2 L |
3851 | } |
3852 | ||
79dec6b7 JB |
3853 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3854 | are no memory operands and at least 3 register ones. */ | |
3855 | if (i.reg_operands >= 3 | |
e346d50a | 3856 | && i.encoding != encoding_vex3 |
79dec6b7 JB |
3857 | && i.reg_operands == i.operands - i.imm_operands |
3858 | && i.tm.opcode_modifier.vex | |
3859 | && i.tm.opcode_modifier.commutative | |
7440781b JB |
3860 | /* .commutative aliases .staticrounding; disambiguate. */ |
3861 | && !i.tm.opcode_modifier.sae | |
33740f21 JB |
3862 | && (i.tm.opcode_modifier.sse2avx |
3863 | || (optimize > 1 && !i.no_optimize)) | |
79dec6b7 JB |
3864 | && i.rex == REX_B |
3865 | && i.vex.register_specifier | |
3866 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3867 | { | |
3868 | unsigned int xchg = i.operands - i.reg_operands; | |
79dec6b7 | 3869 | |
ddb62495 | 3870 | gas_assert (i.tm.opcode_space == SPACE_0F); |
79dec6b7 JB |
3871 | gas_assert (!i.tm.opcode_modifier.sae); |
3872 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3873 | &i.types[i.operands - 3])); | |
3874 | gas_assert (i.rm.mode == 3); | |
3875 | ||
67748abf | 3876 | swap_2_operands (xchg, xchg + 1); |
79dec6b7 JB |
3877 | |
3878 | i.rex = 0; | |
3879 | xchg = i.rm.regmem | 8; | |
3880 | i.rm.regmem = ~register_specifier & 0xf; | |
3881 | gas_assert (!(i.rm.regmem & 8)); | |
3882 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3883 | register_specifier = ~xchg & 0xf; | |
3884 | } | |
3885 | ||
539f890d L |
3886 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3887 | vector_length = avxscalar; | |
10c17abd JB |
3888 | else if (i.tm.opcode_modifier.vex == VEX256) |
3889 | vector_length = 1; | |
d0c2e3ec JB |
3890 | else if (dot_insn () && i.tm.opcode_modifier.vex == VEX128) |
3891 | vector_length = 0; | |
539f890d | 3892 | else |
10c17abd | 3893 | { |
56522fc5 | 3894 | unsigned int op; |
10c17abd | 3895 | |
c7213af9 L |
3896 | /* Determine vector length from the last multi-length vector |
3897 | operand. */ | |
10c17abd | 3898 | vector_length = 0; |
56522fc5 | 3899 | for (op = t->operands; op--;) |
10c17abd JB |
3900 | if (t->operand_types[op].bitfield.xmmword |
3901 | && t->operand_types[op].bitfield.ymmword | |
3902 | && i.types[op].bitfield.ymmword) | |
3903 | { | |
3904 | vector_length = 1; | |
3905 | break; | |
3906 | } | |
3907 | } | |
c0f3af97 | 3908 | |
03751133 L |
3909 | /* Check the REX.W bit and VEXW. */ |
3910 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3911 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
ebe82bfd | 3912 | else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W)) |
03751133 L |
3913 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; |
3914 | else | |
931d03b7 | 3915 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3916 | |
c0f3af97 | 3917 | /* Use 2-byte VEX prefix if possible. */ |
03751133 | 3918 | if (w == 0 |
e346d50a | 3919 | && i.encoding != encoding_vex3 |
ddb62495 | 3920 | && i.tm.opcode_space == SPACE_0F |
c0f3af97 L |
3921 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3922 | { | |
3923 | /* 2-byte VEX prefix. */ | |
3924 | unsigned int r; | |
3925 | ||
3926 | i.vex.length = 2; | |
3927 | i.vex.bytes[0] = 0xc5; | |
3928 | ||
3929 | /* Check the REX.R bit. */ | |
3930 | r = (i.rex & REX_R) ? 0 : 1; | |
3931 | i.vex.bytes[1] = (r << 7 | |
3932 | | register_specifier << 3 | |
3933 | | vector_length << 2 | |
35648716 | 3934 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3935 | } |
3936 | else | |
3937 | { | |
3938 | /* 3-byte VEX prefix. */ | |
f88c9eb0 | 3939 | i.vex.length = 3; |
f88c9eb0 | 3940 | |
ddb62495 | 3941 | switch (i.tm.opcode_space) |
5dd85c99 | 3942 | { |
441f6aca JB |
3943 | case SPACE_0F: |
3944 | case SPACE_0F38: | |
3945 | case SPACE_0F3A: | |
8170af78 | 3946 | case SPACE_VEXMAP7: |
80de6e00 | 3947 | i.vex.bytes[0] = 0xc4; |
7f399153 | 3948 | break; |
441f6aca JB |
3949 | case SPACE_XOP08: |
3950 | case SPACE_XOP09: | |
3951 | case SPACE_XOP0A: | |
f88c9eb0 | 3952 | i.vex.bytes[0] = 0x8f; |
7f399153 L |
3953 | break; |
3954 | default: | |
3955 | abort (); | |
f88c9eb0 | 3956 | } |
c0f3af97 | 3957 | |
c0f3af97 L |
3958 | /* The high 3 bits of the second VEX byte are 1's compliment |
3959 | of RXB bits from REX. */ | |
d0c2e3ec JB |
3960 | i.vex.bytes[1] = ((~i.rex & 7) << 5) |
3961 | | (!dot_insn () ? i.tm.opcode_space | |
3962 | : i.insn_opcode_space); | |
c0f3af97 | 3963 | |
c0f3af97 L |
3964 | i.vex.bytes[2] = (w << 7 |
3965 | | register_specifier << 3 | |
3966 | | vector_length << 2 | |
35648716 | 3967 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3968 | } |
3969 | } | |
3970 | ||
5b7c81bd | 3971 | static INLINE bool |
7a8655d2 JB |
3972 | is_any_vex_encoding (const insn_template *t) |
3973 | { | |
706ce984 | 3974 | return t->opcode_modifier.vex || t->opcode_modifier.evex; |
7a8655d2 JB |
3975 | } |
3976 | ||
6177c84d CL |
3977 | /* We can use this function only when the current encoding is evex. */ |
3978 | static INLINE bool | |
3979 | is_apx_evex_encoding (void) | |
3980 | { | |
dd74a603 | 3981 | return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4 || i.has_nf |
6177c84d CL |
3982 | || (i.vex.register_specifier |
3983 | && (i.vex.register_specifier->reg_flags & RegRex2)); | |
3984 | } | |
3985 | ||
80d61d8d CL |
3986 | static INLINE bool |
3987 | is_apx_rex2_encoding (void) | |
3988 | { | |
ac32c879 | 3989 | return i.rex2 || i.rex2_encoding |
3037cefe | 3990 | || i.tm.opcode_modifier.rex2; |
80d61d8d CL |
3991 | } |
3992 | ||
a5748e0d JB |
3993 | static unsigned int |
3994 | get_broadcast_bytes (const insn_template *t, bool diag) | |
3995 | { | |
3996 | unsigned int op, bytes; | |
3997 | const i386_operand_type *types; | |
3998 | ||
3999 | if (i.broadcast.type) | |
9b345ce8 | 4000 | return (1 << (t->opcode_modifier.broadcast - 1)) * i.broadcast.type; |
a5748e0d JB |
4001 | |
4002 | gas_assert (intel_syntax); | |
4003 | ||
4004 | for (op = 0; op < t->operands; ++op) | |
4005 | if (t->operand_types[op].bitfield.baseindex) | |
4006 | break; | |
4007 | ||
4008 | gas_assert (op < t->operands); | |
4009 | ||
706ce984 | 4010 | if (t->opcode_modifier.evex != EVEXDYN) |
a5748e0d JB |
4011 | switch (i.broadcast.bytes) |
4012 | { | |
4013 | case 1: | |
4014 | if (t->operand_types[op].bitfield.word) | |
4015 | return 2; | |
4016 | /* Fall through. */ | |
4017 | case 2: | |
4018 | if (t->operand_types[op].bitfield.dword) | |
4019 | return 4; | |
4020 | /* Fall through. */ | |
4021 | case 4: | |
4022 | if (t->operand_types[op].bitfield.qword) | |
4023 | return 8; | |
4024 | /* Fall through. */ | |
4025 | case 8: | |
4026 | if (t->operand_types[op].bitfield.xmmword) | |
4027 | return 16; | |
4028 | if (t->operand_types[op].bitfield.ymmword) | |
4029 | return 32; | |
4030 | if (t->operand_types[op].bitfield.zmmword) | |
4031 | return 64; | |
4032 | /* Fall through. */ | |
4033 | default: | |
4034 | abort (); | |
4035 | } | |
4036 | ||
4037 | gas_assert (op + 1 < t->operands); | |
4038 | ||
4039 | if (t->operand_types[op + 1].bitfield.xmmword | |
4040 | + t->operand_types[op + 1].bitfield.ymmword | |
4041 | + t->operand_types[op + 1].bitfield.zmmword > 1) | |
4042 | { | |
4043 | types = &i.types[op + 1]; | |
4044 | diag = false; | |
4045 | } | |
4046 | else /* Ambiguous - guess with a preference to non-AVX512VL forms. */ | |
4047 | types = &t->operand_types[op]; | |
4048 | ||
4049 | if (types->bitfield.zmmword) | |
4050 | bytes = 64; | |
4051 | else if (types->bitfield.ymmword) | |
4052 | bytes = 32; | |
4053 | else | |
4054 | bytes = 16; | |
4055 | ||
4056 | if (diag) | |
4057 | as_warn (_("ambiguous broadcast for `%s', using %u-bit form"), | |
76d3f746 | 4058 | insn_name (t), bytes * 8); |
a5748e0d JB |
4059 | |
4060 | return bytes; | |
4061 | } | |
4062 | ||
43234a1e L |
4063 | /* Build the EVEX prefix. */ |
4064 | ||
4065 | static void | |
4066 | build_evex_prefix (void) | |
4067 | { | |
35648716 | 4068 | unsigned int register_specifier, w; |
43234a1e L |
4069 | rex_byte vrex_used = 0; |
4070 | ||
4071 | /* Check register specifier. */ | |
4072 | if (i.vex.register_specifier) | |
4073 | { | |
4074 | gas_assert ((i.vrex & REX_X) == 0); | |
4075 | ||
4076 | register_specifier = i.vex.register_specifier->reg_num; | |
4077 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
4078 | register_specifier += 8; | |
4079 | /* The upper 16 registers are encoded in the fourth byte of the | |
4080 | EVEX prefix. */ | |
4081 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
4082 | i.vex.bytes[3] = 0x8; | |
4083 | register_specifier = ~register_specifier & 0xf; | |
4084 | } | |
4085 | else | |
4086 | { | |
4087 | register_specifier = 0xf; | |
4088 | ||
4089 | /* Encode upper 16 vector index register in the fourth byte of | |
4090 | the EVEX prefix. */ | |
4091 | if (!(i.vrex & REX_X)) | |
4092 | i.vex.bytes[3] = 0x8; | |
4093 | else | |
4094 | vrex_used |= REX_X; | |
4095 | } | |
4096 | ||
43234a1e L |
4097 | /* 4 byte EVEX prefix. */ |
4098 | i.vex.length = 4; | |
4099 | i.vex.bytes[0] = 0x62; | |
4100 | ||
43234a1e L |
4101 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
4102 | bits from REX. */ | |
ddb62495 | 4103 | gas_assert (i.tm.opcode_space >= SPACE_0F); |
5190fa38 | 4104 | gas_assert (i.tm.opcode_space <= SPACE_VEXMAP7); |
d0c2e3ec JB |
4105 | i.vex.bytes[1] = ((~i.rex & 7) << 5) |
4106 | | (!dot_insn () ? i.tm.opcode_space | |
4107 | : i.insn_opcode_space); | |
43234a1e L |
4108 | |
4109 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
4110 | REX_R bit in VREX. */ | |
4111 | if (!(i.vrex & REX_R)) | |
4112 | i.vex.bytes[1] |= 0x10; | |
4113 | else | |
4114 | vrex_used |= REX_R; | |
4115 | ||
4116 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
4117 | { | |
4118 | /* When all operands are registers, the REX_X bit in REX is not | |
4119 | used. We reuse it to encode the upper 16 registers, which is | |
4120 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
4121 | as 1's compliment. */ | |
4122 | if ((i.vrex & REX_B)) | |
4123 | { | |
4124 | vrex_used |= REX_B; | |
4125 | i.vex.bytes[1] &= ~0x40; | |
4126 | } | |
4127 | } | |
4128 | ||
4129 | /* EVEX instructions shouldn't need the REX prefix. */ | |
4130 | i.vrex &= ~vrex_used; | |
4131 | gas_assert (i.vrex == 0); | |
4132 | ||
6865c043 L |
4133 | /* Check the REX.W bit and VEXW. */ |
4134 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
4135 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
24187fb9 | 4136 | else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W)) |
6865c043 L |
4137 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; |
4138 | else | |
931d03b7 | 4139 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e | 4140 | |
43234a1e | 4141 | /* The third byte of the EVEX prefix. */ |
35648716 JB |
4142 | i.vex.bytes[2] = ((w << 7) |
4143 | | (register_specifier << 3) | |
4144 | | 4 /* Encode the U bit. */ | |
4145 | | i.tm.opcode_modifier.opcodeprefix); | |
43234a1e L |
4146 | |
4147 | /* The fourth byte of the EVEX prefix. */ | |
4148 | /* The zeroing-masking bit. */ | |
6225c532 | 4149 | if (i.mask.reg && i.mask.zeroing) |
43234a1e L |
4150 | i.vex.bytes[3] |= 0x80; |
4151 | ||
4152 | /* Don't always set the broadcast bit if there is no RC. */ | |
ca5312a2 | 4153 | if (i.rounding.type == rc_none) |
43234a1e L |
4154 | { |
4155 | /* Encode the vector length. */ | |
4156 | unsigned int vec_length; | |
4157 | ||
706ce984 | 4158 | if (i.tm.opcode_modifier.evex == EVEXDYN) |
e771e7c9 | 4159 | { |
56522fc5 | 4160 | unsigned int op; |
e771e7c9 | 4161 | |
c7213af9 L |
4162 | /* Determine vector length from the last multi-length vector |
4163 | operand. */ | |
56522fc5 | 4164 | for (op = i.operands; op--;) |
e771e7c9 JB |
4165 | if (i.tm.operand_types[op].bitfield.xmmword |
4166 | + i.tm.operand_types[op].bitfield.ymmword | |
4167 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
4168 | { | |
4169 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
4170 | { |
4171 | i.tm.opcode_modifier.evex = EVEX512; | |
4172 | break; | |
4173 | } | |
e771e7c9 | 4174 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
4175 | { |
4176 | i.tm.opcode_modifier.evex = EVEX256; | |
4177 | break; | |
4178 | } | |
e771e7c9 | 4179 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
4180 | { |
4181 | i.tm.opcode_modifier.evex = EVEX128; | |
4182 | break; | |
4183 | } | |
9b345ce8 JB |
4184 | else if ((i.broadcast.type || i.broadcast.bytes) |
4185 | && op == i.broadcast.operand) | |
625cbd7a | 4186 | { |
a5748e0d | 4187 | switch (get_broadcast_bytes (&i.tm, true)) |
625cbd7a JB |
4188 | { |
4189 | case 64: | |
4190 | i.tm.opcode_modifier.evex = EVEX512; | |
4191 | break; | |
4192 | case 32: | |
4193 | i.tm.opcode_modifier.evex = EVEX256; | |
4194 | break; | |
4195 | case 16: | |
4196 | i.tm.opcode_modifier.evex = EVEX128; | |
4197 | break; | |
4198 | default: | |
c7213af9 | 4199 | abort (); |
625cbd7a | 4200 | } |
c7213af9 | 4201 | break; |
625cbd7a | 4202 | } |
e771e7c9 | 4203 | } |
c7213af9 | 4204 | |
56522fc5 | 4205 | if (op >= MAX_OPERANDS) |
c7213af9 | 4206 | abort (); |
e771e7c9 JB |
4207 | } |
4208 | ||
43234a1e L |
4209 | switch (i.tm.opcode_modifier.evex) |
4210 | { | |
4211 | case EVEXLIG: /* LL' is ignored */ | |
4212 | vec_length = evexlig << 5; | |
4213 | break; | |
4214 | case EVEX128: | |
4215 | vec_length = 0 << 5; | |
4216 | break; | |
4217 | case EVEX256: | |
4218 | vec_length = 1 << 5; | |
4219 | break; | |
4220 | case EVEX512: | |
4221 | vec_length = 2 << 5; | |
4222 | break; | |
d0c2e3ec JB |
4223 | case EVEX_L3: |
4224 | if (dot_insn ()) | |
4225 | { | |
4226 | vec_length = 3 << 5; | |
4227 | break; | |
4228 | } | |
4229 | /* Fall through. */ | |
43234a1e L |
4230 | default: |
4231 | abort (); | |
4232 | break; | |
4233 | } | |
4234 | i.vex.bytes[3] |= vec_length; | |
4235 | /* Encode the broadcast bit. */ | |
9b345ce8 | 4236 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e L |
4237 | i.vex.bytes[3] |= 0x10; |
4238 | } | |
ca5312a2 JB |
4239 | else if (i.rounding.type != saeonly) |
4240 | i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5); | |
43234a1e | 4241 | else |
ca5312a2 | 4242 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e | 4243 | |
6225c532 JB |
4244 | if (i.mask.reg) |
4245 | i.vex.bytes[3] |= i.mask.reg->reg_num; | |
43234a1e L |
4246 | } |
4247 | ||
80d61d8d CL |
4248 | /* Build (2 bytes) rex2 prefix. |
4249 | | D5h | | |
4250 | | m | R4 X4 B4 | W R X B | | |
4251 | ||
4252 | Rex2 reuses i.vex as they both encode i.tm.opcode_space in their prefixes. | |
4253 | */ | |
4254 | static void | |
4255 | build_rex2_prefix (void) | |
4256 | { | |
4257 | i.vex.length = 2; | |
4258 | i.vex.bytes[0] = 0xd5; | |
4259 | /* For the W R X B bits, the variables of rex prefix will be reused. */ | |
4260 | i.vex.bytes[1] = ((i.tm.opcode_space << 7) | |
4261 | | (i.rex2 << 4) | i.rex); | |
4262 | } | |
4263 | ||
6177c84d CL |
4264 | /* Build the EVEX prefix (4-byte) for evex insn |
4265 | | 62h | | |
4266 | | `R`X`B`R' | B'mmm | | |
4267 | | W | v`v`v`v | `x' | pp | | |
4268 | | z| L'L | b | `v | aaa | | |
4269 | */ | |
4270 | static void | |
4271 | build_apx_evex_prefix (void) | |
4272 | { | |
4273 | build_evex_prefix (); | |
4274 | if (i.rex2 & REX_R) | |
4275 | i.vex.bytes[1] &= ~0x10; | |
4276 | if (i.rex2 & REX_B) | |
4277 | i.vex.bytes[1] |= 0x08; | |
4278 | if (i.rex2 & REX_X) | |
b5247082 CL |
4279 | { |
4280 | gas_assert (i.rm.mode != 3); | |
4281 | i.vex.bytes[2] &= ~0x04; | |
4282 | } | |
6177c84d CL |
4283 | if (i.vex.register_specifier |
4284 | && i.vex.register_specifier->reg_flags & RegRex2) | |
4285 | i.vex.bytes[3] &= ~0x08; | |
3083f376 | 4286 | |
4287 | /* Encode the NDD bit of the instruction promoted from the legacy | |
bbe8d019 CL |
4288 | space. ZU shares the same bit with NDD. */ |
4289 | if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4) | |
4290 | || i.tm.opcode_modifier.zu) | |
3083f376 | 4291 | i.vex.bytes[3] |= 0x10; |
dd74a603 CL |
4292 | |
4293 | /* Encode the NF bit. */ | |
4294 | if (i.has_nf) | |
4295 | i.vex.bytes[3] |= 0x04; | |
6177c84d CL |
4296 | } |
4297 | ||
ce705688 JB |
4298 | static void establish_rex (void) |
4299 | { | |
4300 | /* Note that legacy encodings have at most 2 non-immediate operands. */ | |
4301 | unsigned int first = i.imm_operands; | |
4302 | unsigned int last = i.operands > first ? i.operands - first - 1 : first; | |
4303 | ||
4304 | /* Respect a user-specified REX prefix. */ | |
4305 | i.rex |= i.prefix[REX_PREFIX] & REX_OPCODE; | |
4306 | ||
3a8ecbda CL |
4307 | /* For 8 bit RegRex64 registers without a prefix, we need an empty rex prefix. */ |
4308 | if (((i.types[first].bitfield.class == Reg && i.types[first].bitfield.byte | |
4309 | && (i.op[first].regs->reg_flags & RegRex64) != 0) | |
4310 | || (i.types[last].bitfield.class == Reg && i.types[last].bitfield.byte | |
4311 | && (i.op[last].regs->reg_flags & RegRex64) != 0)) | |
b757e3c1 | 4312 | && !is_apx_rex2_encoding () && !is_any_vex_encoding (&i.tm)) |
3a8ecbda CL |
4313 | i.rex |= REX_OPCODE; |
4314 | ||
4315 | /* For REX/REX2/EVEX prefix instructions, we need to convert old registers | |
4316 | (AL, CL, DL and BL) to new ones (AXL, CXL, DXL and BXL) and reject AH, | |
4317 | CH, DH and BH. */ | |
9f8b42c8 | 4318 | if (i.rex || i.rex2 || i.tm.opcode_modifier.evex) |
ce705688 | 4319 | { |
3a8ecbda | 4320 | for (unsigned int x = first; x <= last; x++) |
ce705688 JB |
4321 | { |
4322 | /* Look for 8 bit operand that uses old registers. */ | |
4323 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte | |
4324 | && (i.op[x].regs->reg_flags & RegRex64) == 0) | |
4325 | { | |
4326 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); | |
4327 | /* In case it is "hi" register, give up. */ | |
4328 | if (i.op[x].regs->reg_num > 3) | |
4329 | as_bad (_("can't encode register '%s%s' in an " | |
9f8b42c8 CL |
4330 | "instruction requiring %s prefix"), |
4331 | register_prefix, i.op[x].regs->reg_name, | |
4332 | i.tm.opcode_modifier.evex ? "EVEX" : "REX/REX2"); | |
ce705688 JB |
4333 | |
4334 | /* Otherwise it is equivalent to the extended register. | |
4335 | Since the encoding doesn't change this is merely | |
4336 | cosmetic cleanup for debug output. */ | |
4337 | i.op[x].regs += 8; | |
4338 | } | |
4339 | } | |
4340 | } | |
4341 | ||
192781a3 | 4342 | if (i.rex == 0 && i.rex2 == 0 && (i.rex_encoding || i.rex2_encoding)) |
ce705688 JB |
4343 | { |
4344 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4345 | that uses legacy register. If it is "hi" register, don't add | |
80d61d8d | 4346 | rex and rex2 prefix. */ |
ce705688 JB |
4347 | unsigned int x; |
4348 | ||
4349 | for (x = first; x <= last; x++) | |
4350 | if (i.types[x].bitfield.class == Reg | |
4351 | && i.types[x].bitfield.byte | |
4352 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4353 | && i.op[x].regs->reg_num > 3) | |
4354 | { | |
4355 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); | |
4356 | i.rex_encoding = false; | |
80d61d8d | 4357 | i.rex2_encoding = false; |
ce705688 JB |
4358 | break; |
4359 | } | |
4360 | ||
4361 | if (i.rex_encoding) | |
4362 | i.rex = REX_OPCODE; | |
4363 | } | |
4364 | ||
192781a3 CL |
4365 | if (is_apx_rex2_encoding ()) |
4366 | { | |
4367 | build_rex2_prefix (); | |
4368 | /* The individual REX.RXBW bits got consumed. */ | |
4369 | i.rex &= REX_OPCODE; | |
4370 | } | |
4371 | else if (i.rex != 0) | |
4372 | add_prefix (REX_OPCODE | i.rex); | |
ce705688 JB |
4373 | } |
4374 | ||
65da13b5 L |
4375 | static void |
4376 | process_immext (void) | |
4377 | { | |
4378 | expressionS *exp; | |
4379 | ||
c0f3af97 | 4380 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
4381 | which is coded in the same place as an 8-bit immediate field |
4382 | would be. Here we fake an 8-bit immediate operand from the | |
4383 | opcode suffix stored in tm.extension_opcode. | |
4384 | ||
c1e679ec | 4385 | AVX instructions also use this encoding, for some of |
c0f3af97 | 4386 | 3 argument instructions. */ |
65da13b5 | 4387 | |
43234a1e | 4388 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 4389 | && (i.operands <= 2 |
7a8655d2 | 4390 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 4391 | && i.operands <= 4))); |
65da13b5 L |
4392 | |
4393 | exp = &im_expressions[i.imm_operands++]; | |
4394 | i.op[i.operands].imms = exp; | |
be1643ff | 4395 | i.types[i.operands].bitfield.imm8 = 1; |
65da13b5 L |
4396 | i.operands++; |
4397 | exp->X_op = O_constant; | |
4398 | exp->X_add_number = i.tm.extension_opcode; | |
4399 | i.tm.extension_opcode = None; | |
4400 | } | |
4401 | ||
42164a71 L |
4402 | |
4403 | static int | |
4404 | check_hle (void) | |
4405 | { | |
742732c7 | 4406 | switch (i.tm.opcode_modifier.prefixok) |
42164a71 L |
4407 | { |
4408 | default: | |
4409 | abort (); | |
742732c7 JB |
4410 | case PrefixLock: |
4411 | case PrefixNone: | |
4412 | case PrefixNoTrack: | |
4413 | case PrefixRep: | |
165de32a | 4414 | as_bad (_("invalid instruction `%s' after `%s'"), |
76d3f746 | 4415 | insn_name (&i.tm), i.hle_prefix); |
42164a71 | 4416 | return 0; |
742732c7 | 4417 | case PrefixHLELock: |
42164a71 L |
4418 | if (i.prefix[LOCK_PREFIX]) |
4419 | return 1; | |
165de32a | 4420 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4421 | return 0; |
742732c7 | 4422 | case PrefixHLEAny: |
42164a71 | 4423 | return 1; |
742732c7 | 4424 | case PrefixHLERelease: |
42164a71 L |
4425 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4426 | { | |
4427 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
76d3f746 | 4428 | insn_name (&i.tm)); |
42164a71 L |
4429 | return 0; |
4430 | } | |
8dc0818e | 4431 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4432 | { |
4433 | as_bad (_("memory destination needed for instruction `%s'" | |
76d3f746 | 4434 | " after `xrelease'"), insn_name (&i.tm)); |
42164a71 L |
4435 | return 0; |
4436 | } | |
4437 | return 1; | |
4438 | } | |
4439 | } | |
4440 | ||
c8480b58 L |
4441 | /* Encode aligned vector move as unaligned vector move. */ |
4442 | ||
4443 | static void | |
4444 | encode_with_unaligned_vector_move (void) | |
4445 | { | |
4446 | switch (i.tm.base_opcode) | |
4447 | { | |
b3a9fe6f L |
4448 | case 0x28: /* Load instructions. */ |
4449 | case 0x29: /* Store instructions. */ | |
c8480b58 | 4450 | /* movaps/movapd/vmovaps/vmovapd. */ |
ddb62495 | 4451 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 | 4452 | && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66) |
b3a9fe6f | 4453 | i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1); |
c8480b58 | 4454 | break; |
b3a9fe6f L |
4455 | case 0x6f: /* Load instructions. */ |
4456 | case 0x7f: /* Store instructions. */ | |
c8480b58 | 4457 | /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */ |
ddb62495 | 4458 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 L |
4459 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66) |
4460 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
4461 | break; | |
4462 | default: | |
4463 | break; | |
4464 | } | |
4465 | } | |
4466 | ||
b6f8c7c4 L |
4467 | /* Try the shortest encoding by shortening operand size. */ |
4468 | ||
4469 | static void | |
4470 | optimize_encoding (void) | |
4471 | { | |
a0a1771e | 4472 | unsigned int j; |
b6f8c7c4 | 4473 | |
7fc69528 | 4474 | if (i.tm.mnem_off == MN_lea) |
fe134c65 JB |
4475 | { |
4476 | /* Optimize: -O: | |
4477 | lea symbol, %rN -> mov $symbol, %rN | |
4478 | lea (%rM), %rN -> mov %rM, %rN | |
4479 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4480 | ||
4481 | and in 32-bit mode for 16-bit addressing | |
4482 | ||
4483 | lea (%rM), %rN -> movzx %rM, %rN | |
4484 | ||
4485 | and in 64-bit mode zap 32-bit addressing in favor of using a | |
4486 | 32-bit (or less) destination. | |
4487 | */ | |
4488 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4489 | { | |
4490 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4491 | i.tm.opcode_modifier.size = SIZE32; | |
4492 | i.prefix[ADDR_PREFIX] = 0; | |
4493 | } | |
4494 | ||
4495 | if (!i.index_reg && !i.base_reg) | |
4496 | { | |
4497 | /* Handle: | |
4498 | lea symbol, %rN -> mov $symbol, %rN | |
4499 | */ | |
4500 | if (flag_code == CODE_64BIT) | |
4501 | { | |
4502 | /* Don't transform a relocation to a 16-bit one. */ | |
4503 | if (i.op[0].disps | |
4504 | && i.op[0].disps->X_op != O_constant | |
4505 | && i.op[1].regs->reg_type.bitfield.word) | |
4506 | return; | |
4507 | ||
4508 | if (!i.op[1].regs->reg_type.bitfield.qword | |
4509 | || i.tm.opcode_modifier.size == SIZE32) | |
4510 | { | |
4511 | i.tm.base_opcode = 0xb8; | |
4512 | i.tm.opcode_modifier.modrm = 0; | |
4513 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4514 | i.types[0].bitfield.imm32 = 1; | |
4515 | else | |
4516 | { | |
4517 | i.tm.opcode_modifier.size = SIZE16; | |
4518 | i.types[0].bitfield.imm16 = 1; | |
4519 | } | |
4520 | } | |
4521 | else | |
4522 | { | |
4523 | /* Subject to further optimization below. */ | |
4524 | i.tm.base_opcode = 0xc7; | |
4525 | i.tm.extension_opcode = 0; | |
4526 | i.types[0].bitfield.imm32s = 1; | |
4527 | i.types[0].bitfield.baseindex = 0; | |
4528 | } | |
4529 | } | |
4530 | /* Outside of 64-bit mode address and operand sizes have to match if | |
4531 | a relocation is involved, as otherwise we wouldn't (currently) or | |
4532 | even couldn't express the relocation correctly. */ | |
4533 | else if (i.op[0].disps | |
4534 | && i.op[0].disps->X_op != O_constant | |
4535 | && ((!i.prefix[ADDR_PREFIX]) | |
4536 | != (flag_code == CODE_32BIT | |
4537 | ? i.op[1].regs->reg_type.bitfield.dword | |
4538 | : i.op[1].regs->reg_type.bitfield.word))) | |
4539 | return; | |
7772f168 JB |
4540 | /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit |
4541 | destination is going to grow encoding size. */ | |
4542 | else if (flag_code == CODE_16BIT | |
4543 | && (optimize <= 1 || optimize_for_space) | |
4544 | && !i.prefix[ADDR_PREFIX] | |
4545 | && i.op[1].regs->reg_type.bitfield.dword) | |
4546 | return; | |
fe134c65 JB |
4547 | else |
4548 | { | |
4549 | i.tm.base_opcode = 0xb8; | |
4550 | i.tm.opcode_modifier.modrm = 0; | |
4551 | if (i.op[1].regs->reg_type.bitfield.dword) | |
4552 | i.types[0].bitfield.imm32 = 1; | |
4553 | else | |
4554 | i.types[0].bitfield.imm16 = 1; | |
4555 | ||
4556 | if (i.op[0].disps | |
4557 | && i.op[0].disps->X_op == O_constant | |
4558 | && i.op[1].regs->reg_type.bitfield.dword | |
60cfa10c L |
4559 | /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence |
4560 | GCC 5. */ | |
4561 | && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT)) | |
fe134c65 JB |
4562 | i.op[0].disps->X_add_number &= 0xffff; |
4563 | } | |
4564 | ||
4565 | i.tm.operand_types[0] = i.types[0]; | |
4566 | i.imm_operands = 1; | |
4567 | if (!i.op[0].imms) | |
4568 | { | |
4569 | i.op[0].imms = &im_expressions[0]; | |
4570 | i.op[0].imms->X_op = O_absent; | |
4571 | } | |
4572 | } | |
4573 | else if (i.op[0].disps | |
4574 | && (i.op[0].disps->X_op != O_constant | |
4575 | || i.op[0].disps->X_add_number)) | |
4576 | return; | |
4577 | else | |
4578 | { | |
4579 | /* Handle: | |
4580 | lea (%rM), %rN -> mov %rM, %rN | |
4581 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4582 | lea (%rM), %rN -> movzx %rM, %rN | |
4583 | */ | |
4584 | const reg_entry *addr_reg; | |
4585 | ||
4586 | if (!i.index_reg && i.base_reg->reg_num != RegIP) | |
4587 | addr_reg = i.base_reg; | |
4588 | else if (!i.base_reg | |
4589 | && i.index_reg->reg_num != RegIZ | |
4590 | && !i.log2_scale_factor) | |
4591 | addr_reg = i.index_reg; | |
4592 | else | |
4593 | return; | |
4594 | ||
4595 | if (addr_reg->reg_type.bitfield.word | |
4596 | && i.op[1].regs->reg_type.bitfield.dword) | |
4597 | { | |
4598 | if (flag_code != CODE_32BIT) | |
4599 | return; | |
ddb62495 | 4600 | i.tm.opcode_space = SPACE_0F; |
fe134c65 JB |
4601 | i.tm.base_opcode = 0xb7; |
4602 | } | |
4603 | else | |
4604 | i.tm.base_opcode = 0x8b; | |
4605 | ||
4606 | if (addr_reg->reg_type.bitfield.dword | |
4607 | && i.op[1].regs->reg_type.bitfield.qword) | |
4608 | i.tm.opcode_modifier.size = SIZE32; | |
4609 | ||
4610 | i.op[0].regs = addr_reg; | |
4611 | i.reg_operands = 2; | |
4612 | } | |
4613 | ||
4614 | i.mem_operands = 0; | |
4615 | i.disp_operands = 0; | |
4616 | i.prefix[ADDR_PREFIX] = 0; | |
4617 | i.prefix[SEG_PREFIX] = 0; | |
4618 | i.seg[0] = NULL; | |
4619 | } | |
4620 | ||
b6f8c7c4 | 4621 | if (optimize_for_space |
7fc69528 | 4622 | && i.tm.mnem_off == MN_test |
b6f8c7c4 L |
4623 | && i.reg_operands == 1 |
4624 | && i.imm_operands == 1 | |
4625 | && !i.types[1].bitfield.byte | |
4626 | && i.op[0].imms->X_op == O_constant | |
7fc69528 | 4627 | && fits_in_imm7 (i.op[0].imms->X_add_number)) |
b6f8c7c4 L |
4628 | { |
4629 | /* Optimize: -Os: | |
4630 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4631 | */ | |
4632 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4633 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4634 | { | |
4635 | i.types[1].bitfield.byte = 1; | |
4636 | /* Ignore the suffix. */ | |
4637 | i.suffix = 0; | |
80d61d8d CL |
4638 | /* Convert to byte registers. 8-bit registers are special, |
4639 | RegRex64 and non-RegRex64 each have 8 registers. */ | |
7697afb6 | 4640 | if (i.types[1].bitfield.word) |
80d61d8d | 4641 | /* 32 (or 40) 8-bit registers. */ |
7697afb6 | 4642 | j = 32; |
80d61d8d CL |
4643 | else if (i.types[1].bitfield.dword) |
4644 | /* 32 (or 40) 8-bit registers + 32 16-bit registers. */ | |
4645 | j = 64; | |
7697afb6 | 4646 | else |
80d61d8d CL |
4647 | /* 32 (or 40) 8-bit registers + 32 16-bit registers |
4648 | + 32 32-bit registers. */ | |
4649 | j = 96; | |
4650 | ||
4651 | /* In 64-bit mode, the following byte registers cannot be accessed | |
4652 | if using the Rex and Rex2 prefix: AH, BH, CH, DH */ | |
4653 | if (!(i.op[1].regs->reg_flags & (RegRex | RegRex2)) && base_regnum < 4) | |
7697afb6 JB |
4654 | j += 8; |
4655 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4656 | } |
4657 | } | |
4658 | else if (flag_code == CODE_64BIT | |
ddb62495 | 4659 | && i.tm.opcode_space == SPACE_BASE |
d3d50934 L |
4660 | && ((i.types[1].bitfield.qword |
4661 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4662 | && i.imm_operands == 1 |
4663 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4664 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4665 | && i.tm.extension_opcode == None |
4666 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4667 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
7fc69528 | 4668 | && (i.tm.base_opcode == 0x24 |
b6f8c7c4 L |
4669 | || (i.tm.base_opcode == 0x80 |
4670 | && i.tm.extension_opcode == 0x4) | |
7fc69528 JB |
4671 | || i.tm.mnem_off == MN_test |
4672 | || ((i.tm.base_opcode | 1) == 0xc7 | |
b8364fa7 JB |
4673 | && i.tm.extension_opcode == 0x0))) |
4674 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4675 | && i.tm.base_opcode == 0x83 | |
4676 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4677 | || (i.types[0].bitfield.qword |
4678 | && ((i.reg_operands == 2 | |
4679 | && i.op[0].regs == i.op[1].regs | |
7fc69528 JB |
4680 | && (i.tm.mnem_off == MN_xor |
4681 | || i.tm.mnem_off == MN_sub)) | |
4682 | || i.tm.mnem_off == MN_clr)))) | |
b6f8c7c4 L |
4683 | { |
4684 | /* Optimize: -O: | |
4685 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4686 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4687 | testq $imm31, %r64 -> testl $imm31, %r32 |
4688 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4689 | subq %r64, %r64 -> subl %r32, %r32 | |
4690 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4691 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4692 | */ | |
04784e33 JB |
4693 | i.tm.opcode_modifier.size = SIZE32; |
4694 | if (i.imm_operands) | |
4695 | { | |
4696 | i.types[0].bitfield.imm32 = 1; | |
4697 | i.types[0].bitfield.imm32s = 0; | |
4698 | i.types[0].bitfield.imm64 = 0; | |
4699 | } | |
4700 | else | |
4701 | { | |
4702 | i.types[0].bitfield.dword = 1; | |
4703 | i.types[0].bitfield.qword = 0; | |
4704 | } | |
4705 | i.types[1].bitfield.dword = 1; | |
4706 | i.types[1].bitfield.qword = 0; | |
7fc69528 | 4707 | if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea) |
b6f8c7c4 L |
4708 | { |
4709 | /* Handle | |
4710 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4711 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4712 | */ | |
4713 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4714 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4715 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
507916b8 | 4716 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4717 | { |
4718 | /* Handle | |
4719 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4720 | */ | |
507916b8 | 4721 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4722 | i.tm.extension_opcode = None; |
507916b8 | 4723 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4724 | i.tm.opcode_modifier.modrm = 0; |
4725 | } | |
4726 | } | |
4727 | } | |
c73a37b2 JB |
4728 | else if (i.reg_operands == 3 |
4729 | && i.op[0].regs == i.op[1].regs | |
4730 | && i.encoding != encoding_evex | |
4731 | && (i.tm.mnem_off == MN_xor | |
4732 | || i.tm.mnem_off == MN_sub)) | |
4733 | { | |
4734 | /* Optimize: -O: | |
4735 | xorb %rNb, %rNb, %rMb -> xorl %rMd, %rMd | |
4736 | xorw %rNw, %rNw, %rMw -> xorl %rMd, %rMd | |
4737 | xorl %rNd, %rNd, %rMd -> xorl %rMd, %rMd | |
4738 | xorq %rN, %rN, %rM -> xorl %rMd, %rMd | |
4739 | subb %rNb, %rNb, %rMb -> subl %rMd, %rMd | |
4740 | subw %rNw, %rNw, %rMw -> subl %rMd, %rMd | |
4741 | subl %rNd, %rNd, %rMd -> subl %rMd, %rMd | |
4742 | subq %rN, %rN, %rM -> subl %rMd, %rMd | |
4743 | */ | |
4744 | i.tm.opcode_space = SPACE_BASE; | |
4745 | i.tm.opcode_modifier.evex = 0; | |
4746 | i.tm.opcode_modifier.size = SIZE32; | |
4747 | i.types[0].bitfield.byte = 0; | |
4748 | i.types[0].bitfield.word = 0; | |
4749 | i.types[0].bitfield.dword = 1; | |
4750 | i.types[0].bitfield.qword = 0; | |
4751 | i.op[0].regs = i.op[2].regs; | |
4752 | i.types[1] = i.types[0]; | |
4753 | i.op[1].regs = i.op[2].regs; | |
4754 | i.reg_operands = 2; | |
4755 | } | |
5641ec01 JB |
4756 | else if (optimize > 1 |
4757 | && !optimize_for_space | |
4758 | && i.reg_operands == 2 | |
4759 | && i.op[0].regs == i.op[1].regs | |
7fc69528 | 4760 | && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or) |
5641ec01 JB |
4761 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) |
4762 | { | |
4763 | /* Optimize: -O2: | |
4764 | andb %rN, %rN -> testb %rN, %rN | |
4765 | andw %rN, %rN -> testw %rN, %rN | |
4766 | andq %rN, %rN -> testq %rN, %rN | |
4767 | orb %rN, %rN -> testb %rN, %rN | |
4768 | orw %rN, %rN -> testw %rN, %rN | |
4769 | orq %rN, %rN -> testq %rN, %rN | |
4770 | ||
4771 | and outside of 64-bit mode | |
4772 | ||
4773 | andl %rN, %rN -> testl %rN, %rN | |
4774 | orl %rN, %rN -> testl %rN, %rN | |
4775 | */ | |
4776 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4777 | } | |
ad2f4436 JB |
4778 | else if (i.tm.base_opcode == 0xba |
4779 | && i.tm.opcode_space == SPACE_0F | |
4780 | && i.reg_operands == 1 | |
4781 | && i.op[0].imms->X_op == O_constant | |
4782 | && i.op[0].imms->X_add_number >= 0) | |
4783 | { | |
4784 | /* Optimize: -O: | |
4785 | btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16) | |
4786 | btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8) | |
4787 | btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4788 | ||
4789 | With <BT> one of bts, btr, and bts also: | |
4790 | <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16) | |
4791 | <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4792 | */ | |
4793 | switch (flag_code) | |
4794 | { | |
4795 | case CODE_64BIT: | |
4796 | if (i.tm.extension_opcode != 4) | |
4797 | break; | |
4798 | if (i.types[1].bitfield.qword | |
4799 | && i.op[0].imms->X_add_number < 32 | |
4800 | && !(i.op[1].regs->reg_flags & RegRex)) | |
4801 | i.tm.opcode_modifier.size = SIZE32; | |
4802 | /* Fall through. */ | |
4803 | case CODE_32BIT: | |
4804 | if (i.types[1].bitfield.word | |
4805 | && i.op[0].imms->X_add_number < 16) | |
4806 | i.tm.opcode_modifier.size = SIZE32; | |
4807 | break; | |
4808 | case CODE_16BIT: | |
4809 | if (i.op[0].imms->X_add_number < 16) | |
4810 | i.tm.opcode_modifier.size = SIZE16; | |
4811 | break; | |
4812 | } | |
4813 | } | |
99112332 | 4814 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4815 | && i.op[0].regs == i.op[1].regs |
4816 | && !i.types[2].bitfield.xmmword | |
4817 | && (i.tm.opcode_modifier.vex | |
6225c532 | 4818 | || ((!i.mask.reg || i.mask.zeroing) |
706ce984 | 4819 | && i.tm.opcode_modifier.evex |
e346d50a | 4820 | && (i.encoding != encoding_evex |
dd22218c | 4821 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
734dfd1c | 4822 | || is_cpu (&i.tm, CpuAVX512VL) |
7091c612 | 4823 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4824 | && i.types[2].bitfield.ymmword)))) |
ddb62495 | 4825 | && i.tm.opcode_space == SPACE_0F |
5844ccaa JB |
4826 | && ((i.tm.base_opcode | 2) == 0x57 |
4827 | || i.tm.base_opcode == 0xdf | |
4828 | || i.tm.base_opcode == 0xef | |
4829 | || (i.tm.base_opcode | 3) == 0xfb | |
4830 | || i.tm.base_opcode == 0x42 | |
4831 | || i.tm.base_opcode == 0x47)) | |
b6f8c7c4 | 4832 | { |
99112332 | 4833 | /* Optimize: -O1: |
8305403a L |
4834 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4835 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4836 | EVEX VOP %zmmM, %zmmM, %zmmN |
4837 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4838 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4839 | EVEX VOP %ymmM, %ymmM, %ymmN |
4840 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4841 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4842 | VEX VOP %ymmM, %ymmM, %ymmN |
4843 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4844 | VOP, one of vpandn and vpxor: | |
4845 | VEX VOP %ymmM, %ymmM, %ymmN | |
4846 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4847 | VOP, one of vpandnd and vpandnq: | |
4848 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4849 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4850 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4851 | EVEX VOP %ymmM, %ymmM, %ymmN |
4852 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4853 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4854 | VOP, one of vpxord and vpxorq: |
4855 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4856 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4857 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4858 | EVEX VOP %ymmM, %ymmM, %ymmN |
4859 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4860 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4861 | VOP, one of kxord and kxorq: |
4862 | VEX VOP %kM, %kM, %kN | |
4863 | -> VEX kxorw %kM, %kM, %kN | |
4864 | VOP, one of kandnd and kandnq: | |
4865 | VEX VOP %kM, %kM, %kN | |
4866 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4867 | */ |
706ce984 | 4868 | if (i.tm.opcode_modifier.evex) |
b6f8c7c4 | 4869 | { |
e346d50a | 4870 | if (i.encoding != encoding_evex) |
b6f8c7c4 L |
4871 | { |
4872 | i.tm.opcode_modifier.vex = VEX128; | |
4873 | i.tm.opcode_modifier.vexw = VEXW0; | |
4874 | i.tm.opcode_modifier.evex = 0; | |
e346d50a | 4875 | i.encoding = encoding_vex; |
a6f3add0 | 4876 | i.mask.reg = NULL; |
b6f8c7c4 | 4877 | } |
7b1d7ca1 | 4878 | else if (optimize > 1) |
dd22218c L |
4879 | i.tm.opcode_modifier.evex = EVEX128; |
4880 | else | |
4881 | return; | |
b6f8c7c4 | 4882 | } |
f74a6307 | 4883 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 | 4884 | { |
35648716 | 4885 | i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; |
1424ad86 JB |
4886 | i.tm.opcode_modifier.vexw = VEXW0; |
4887 | } | |
b6f8c7c4 L |
4888 | else |
4889 | i.tm.opcode_modifier.vex = VEX128; | |
4890 | ||
4891 | if (i.tm.opcode_modifier.vex) | |
4892 | for (j = 0; j < 3; j++) | |
4893 | { | |
4894 | i.types[j].bitfield.xmmword = 1; | |
4895 | i.types[j].bitfield.ymmword = 0; | |
4896 | } | |
4897 | } | |
e346d50a | 4898 | else if (i.encoding != encoding_evex |
eb3f3841 | 4899 | && i.encoding != encoding_egpr |
97ed31ae | 4900 | && !i.types[0].bitfield.zmmword |
392a5972 | 4901 | && !i.types[1].bitfield.zmmword |
6225c532 | 4902 | && !i.mask.reg |
9b345ce8 | 4903 | && !i.broadcast.type |
a5748e0d | 4904 | && !i.broadcast.bytes |
706ce984 | 4905 | && i.tm.opcode_modifier.evex |
35648716 JB |
4906 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4907 | || (i.tm.base_opcode & ~4) == 0xdb | |
4908 | || (i.tm.base_opcode & ~4) == 0xeb) | |
97ed31ae L |
4909 | && i.tm.extension_opcode == None) |
4910 | { | |
4911 | /* Optimize: -O1: | |
4912 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4913 | vmovdqu32 and vmovdqu64: | |
4914 | EVEX VOP %xmmM, %xmmN | |
4915 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4916 | EVEX VOP %ymmM, %ymmN | |
4917 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4918 | EVEX VOP %xmmM, mem | |
4919 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4920 | EVEX VOP %ymmM, mem | |
4921 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4922 | EVEX VOP mem, %xmmN | |
4923 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4924 | EVEX VOP mem, %ymmN | |
4925 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4926 | VOP, one of vpand, vpandn, vpor, vpxor: |
4927 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4928 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4929 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4930 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4931 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4932 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4933 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4934 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4935 | */ |
a0a1771e | 4936 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4937 | if (operand_type_check (i.types[j], disp) |
4938 | && i.op[j].disps->X_op == O_constant) | |
4939 | { | |
4940 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4941 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4942 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4943 | int evex_disp8, vex_disp8; | |
4944 | unsigned int memshift = i.memshift; | |
4945 | offsetT n = i.op[j].disps->X_add_number; | |
4946 | ||
4947 | evex_disp8 = fits_in_disp8 (n); | |
4948 | i.memshift = 0; | |
4949 | vex_disp8 = fits_in_disp8 (n); | |
4950 | if (evex_disp8 != vex_disp8) | |
4951 | { | |
4952 | i.memshift = memshift; | |
4953 | return; | |
4954 | } | |
4955 | ||
4956 | i.types[j].bitfield.disp8 = vex_disp8; | |
4957 | break; | |
4958 | } | |
35648716 JB |
4959 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4960 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2) | |
4961 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
97ed31ae L |
4962 | i.tm.opcode_modifier.vex |
4963 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4964 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 | 4965 | /* VPAND, VPOR, and VPXOR are commutative. */ |
35648716 | 4966 | if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf) |
79dec6b7 | 4967 | i.tm.opcode_modifier.commutative = 1; |
97ed31ae L |
4968 | i.tm.opcode_modifier.evex = 0; |
4969 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4970 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4971 | i.tm.opcode_modifier.disp8memshift = 0; |
4972 | i.memshift = 0; | |
a0a1771e JB |
4973 | if (j < i.operands) |
4974 | i.types[j].bitfield.disp8 | |
4975 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4976 | } |
b5c37946 SJ |
4977 | else if (optimize_for_space |
4978 | && i.tm.base_opcode == 0x29 | |
4979 | && i.tm.opcode_space == SPACE_0F38 | |
4980 | && i.operands == i.reg_operands | |
4981 | && i.op[0].regs == i.op[1].regs | |
4982 | && (!i.tm.opcode_modifier.vex | |
4983 | || !(i.op[0].regs->reg_flags & RegRex)) | |
706ce984 | 4984 | && !i.tm.opcode_modifier.evex) |
b5c37946 SJ |
4985 | { |
4986 | /* Optimize: -Os: | |
4987 | pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN | |
4988 | vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8) | |
4989 | vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8) | |
4990 | */ | |
4991 | i.tm.opcode_space = SPACE_0F; | |
4992 | i.tm.base_opcode = 0x76; | |
4993 | } | |
4994 | else if (((i.tm.base_opcode >= 0x64 | |
4995 | && i.tm.base_opcode <= 0x66 | |
4996 | && i.tm.opcode_space == SPACE_0F) | |
4997 | || (i.tm.base_opcode == 0x37 | |
4998 | && i.tm.opcode_space == SPACE_0F38)) | |
4999 | && i.operands == i.reg_operands | |
5000 | && i.op[0].regs == i.op[1].regs | |
706ce984 | 5001 | && !i.tm.opcode_modifier.evex) |
b5c37946 SJ |
5002 | { |
5003 | /* Optimize: -O: | |
5004 | pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN | |
5005 | pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN | |
5006 | vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8) | |
5007 | vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7) | |
5008 | vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8) | |
5009 | vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7) | |
5010 | */ | |
5011 | i.tm.opcode_space = SPACE_0F; | |
5012 | i.tm.base_opcode = 0xef; | |
5013 | if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex)) | |
5014 | { | |
5015 | if (i.operands == 2) | |
5016 | { | |
5017 | gas_assert (i.tm.opcode_modifier.sse2avx); | |
5018 | ||
5019 | i.operands = 3; | |
5020 | i.reg_operands = 3; | |
5021 | i.tm.operands = 3; | |
5022 | ||
5023 | i.op[2].regs = i.op[0].regs; | |
5024 | i.types[2] = i.types[0]; | |
5025 | i.flags[2] = i.flags[0]; | |
5026 | i.tm.operand_types[2] = i.tm.operand_types[0]; | |
5027 | ||
5028 | i.tm.opcode_modifier.sse2avx = 0; | |
5029 | } | |
5030 | i.op[0].regs -= i.op[0].regs->reg_num + 8; | |
5031 | i.op[1].regs = i.op[0].regs; | |
5032 | } | |
5033 | } | |
5034 | else if (optimize_for_space | |
5035 | && i.tm.base_opcode == 0x59 | |
5036 | && i.tm.opcode_space == SPACE_0F38 | |
5037 | && i.operands == i.reg_operands | |
5038 | && i.tm.opcode_modifier.vex | |
5039 | && !(i.op[0].regs->reg_flags & RegRex) | |
5040 | && i.op[0].regs->reg_type.bitfield.xmmword | |
e346d50a | 5041 | && i.encoding != encoding_vex3) |
b5c37946 SJ |
5042 | { |
5043 | /* Optimize: -Os: | |
5044 | vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8) | |
5045 | */ | |
5046 | i.tm.opcode_space = SPACE_0F; | |
5047 | i.tm.base_opcode = 0x6c; | |
f2a3a881 | 5048 | i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1; |
b5c37946 SJ |
5049 | |
5050 | ++i.operands; | |
5051 | ++i.reg_operands; | |
5052 | ++i.tm.operands; | |
5053 | ||
5054 | i.op[2].regs = i.op[0].regs; | |
5055 | i.types[2] = i.types[0]; | |
5056 | i.flags[2] = i.flags[0]; | |
5057 | i.tm.operand_types[2] = i.tm.operand_types[0]; | |
5058 | ||
5059 | swap_2_operands (1, 2); | |
5060 | } | |
b6f8c7c4 L |
5061 | } |
5062 | ||
1e7dd4a0 JB |
5063 | static void |
5064 | s_noopt (int dummy ATTRIBUTE_UNUSED) | |
5065 | { | |
5066 | if (!is_it_end_of_statement ()) | |
5067 | as_warn (_("`.noopt' arguments ignored")); | |
5068 | ||
5069 | optimize = 0; | |
5070 | optimize_for_space = 0; | |
5071 | ||
5072 | ignore_rest_of_line (); | |
5073 | } | |
5074 | ||
ae531041 L |
5075 | /* Return non-zero for load instruction. */ |
5076 | ||
5077 | static int | |
5078 | load_insn_p (void) | |
5079 | { | |
5080 | unsigned int dest; | |
5081 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
5082 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
5083 | ||
5084 | if (!any_vex_p) | |
5085 | { | |
ef07be45 CL |
5086 | /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, |
5087 | bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ | |
255571cd | 5088 | if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE) |
ae531041 L |
5089 | return 0; |
5090 | ||
389d00a5 | 5091 | /* pop. */ |
6d86a545 | 5092 | if (i.tm.mnem_off == MN_pop) |
389d00a5 JB |
5093 | return 1; |
5094 | } | |
5095 | ||
ddb62495 | 5096 | if (i.tm.opcode_space == SPACE_BASE) |
389d00a5 JB |
5097 | { |
5098 | /* popf, popa. */ | |
5099 | if (i.tm.base_opcode == 0x9d | |
a09f656b | 5100 | || i.tm.base_opcode == 0x61) |
ae531041 L |
5101 | return 1; |
5102 | ||
5103 | /* movs, cmps, lods, scas. */ | |
5104 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
5105 | return 1; | |
5106 | ||
a09f656b | 5107 | /* outs, xlatb. */ |
5108 | if (base_opcode == 0x6f | |
5109 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 5110 | return 1; |
a09f656b | 5111 | /* NB: For AMD-specific insns with implicit memory operands, |
5112 | they're intentionally not covered. */ | |
ae531041 L |
5113 | } |
5114 | ||
5115 | /* No memory operand. */ | |
5116 | if (!i.mem_operands) | |
5117 | return 0; | |
5118 | ||
5119 | if (any_vex_p) | |
5120 | { | |
7fc69528 | 5121 | if (i.tm.mnem_off == MN_vldmxcsr) |
ae531041 L |
5122 | return 1; |
5123 | } | |
ddb62495 | 5124 | else if (i.tm.opcode_space == SPACE_BASE) |
ae531041 L |
5125 | { |
5126 | /* test, not, neg, mul, imul, div, idiv. */ | |
aa4c197d | 5127 | if (base_opcode == 0xf7 && i.tm.extension_opcode != 1) |
ae531041 L |
5128 | return 1; |
5129 | ||
5130 | /* inc, dec. */ | |
5131 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
5132 | return 1; | |
5133 | ||
5134 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
5135 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
5136 | return 1; | |
5137 | ||
ae531041 | 5138 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
aa4c197d | 5139 | if ((base_opcode == 0xc1 || (base_opcode | 2) == 0xd3) |
ae531041 L |
5140 | && i.tm.extension_opcode != 6) |
5141 | return 1; | |
5142 | ||
ae531041 | 5143 | /* Check for x87 instructions. */ |
aa4c197d | 5144 | if ((base_opcode | 6) == 0xdf) |
ae531041 L |
5145 | { |
5146 | /* Skip fst, fstp, fstenv, fstcw. */ | |
5147 | if (i.tm.base_opcode == 0xd9 | |
5148 | && (i.tm.extension_opcode == 2 | |
5149 | || i.tm.extension_opcode == 3 | |
5150 | || i.tm.extension_opcode == 6 | |
5151 | || i.tm.extension_opcode == 7)) | |
5152 | return 0; | |
5153 | ||
5154 | /* Skip fisttp, fist, fistp, fstp. */ | |
5155 | if (i.tm.base_opcode == 0xdb | |
5156 | && (i.tm.extension_opcode == 1 | |
5157 | || i.tm.extension_opcode == 2 | |
5158 | || i.tm.extension_opcode == 3 | |
5159 | || i.tm.extension_opcode == 7)) | |
5160 | return 0; | |
5161 | ||
5162 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
5163 | if (i.tm.base_opcode == 0xdd | |
5164 | && (i.tm.extension_opcode == 1 | |
5165 | || i.tm.extension_opcode == 2 | |
5166 | || i.tm.extension_opcode == 3 | |
5167 | || i.tm.extension_opcode == 6 | |
5168 | || i.tm.extension_opcode == 7)) | |
5169 | return 0; | |
5170 | ||
5171 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
5172 | if (i.tm.base_opcode == 0xdf | |
5173 | && (i.tm.extension_opcode == 1 | |
5174 | || i.tm.extension_opcode == 2 | |
5175 | || i.tm.extension_opcode == 3 | |
5176 | || i.tm.extension_opcode == 6 | |
5177 | || i.tm.extension_opcode == 7)) | |
5178 | return 0; | |
5179 | ||
5180 | return 1; | |
5181 | } | |
5182 | } | |
ddb62495 | 5183 | else if (i.tm.opcode_space == SPACE_0F) |
389d00a5 JB |
5184 | { |
5185 | /* bt, bts, btr, btc. */ | |
5186 | if (i.tm.base_opcode == 0xba | |
aa4c197d | 5187 | && (i.tm.extension_opcode | 3) == 7) |
389d00a5 JB |
5188 | return 1; |
5189 | ||
5190 | /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */ | |
5191 | if (i.tm.base_opcode == 0xc7 | |
5192 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE | |
5193 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3 | |
5194 | || i.tm.extension_opcode == 6)) | |
5195 | return 1; | |
5196 | ||
5197 | /* fxrstor, ldmxcsr, xrstor. */ | |
5198 | if (i.tm.base_opcode == 0xae | |
5199 | && (i.tm.extension_opcode == 1 | |
5200 | || i.tm.extension_opcode == 2 | |
5201 | || i.tm.extension_opcode == 5)) | |
5202 | return 1; | |
5203 | ||
5204 | /* lgdt, lidt, lmsw. */ | |
5205 | if (i.tm.base_opcode == 0x01 | |
5206 | && (i.tm.extension_opcode == 2 | |
5207 | || i.tm.extension_opcode == 3 | |
5208 | || i.tm.extension_opcode == 6)) | |
5209 | return 1; | |
5210 | } | |
ae531041 L |
5211 | |
5212 | dest = i.operands - 1; | |
5213 | ||
5214 | /* Check fake imm8 operand and 3 source operands. */ | |
5215 | if ((i.tm.opcode_modifier.immext | |
aa180741 | 5216 | || i.reg_operands + i.mem_operands == 4) |
ae531041 L |
5217 | && i.types[dest].bitfield.imm8) |
5218 | dest--; | |
5219 | ||
389d00a5 | 5220 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */ |
ddb62495 | 5221 | if (i.tm.opcode_space == SPACE_BASE |
aa4c197d | 5222 | && ((base_opcode | 0x38) == 0x39 |
389d00a5 JB |
5223 | || (base_opcode | 2) == 0x87)) |
5224 | return 1; | |
5225 | ||
7fc69528 | 5226 | if (i.tm.mnem_off == MN_xadd) |
ae531041 L |
5227 | return 1; |
5228 | ||
5229 | /* Check for load instruction. */ | |
5230 | return (i.types[dest].bitfield.class != ClassNone | |
5231 | || i.types[dest].bitfield.instance == Accum); | |
5232 | } | |
5233 | ||
5234 | /* Output lfence, 0xfaee8, after instruction. */ | |
5235 | ||
5236 | static void | |
5237 | insert_lfence_after (void) | |
5238 | { | |
5239 | if (lfence_after_load && load_insn_p ()) | |
5240 | { | |
a09f656b | 5241 | /* There are also two REP string instructions that require |
5242 | special treatment. Specifically, the compare string (CMPS) | |
5243 | and scan string (SCAS) instructions set EFLAGS in a manner | |
5244 | that depends on the data being compared/scanned. When used | |
5245 | with a REP prefix, the number of iterations may therefore | |
5246 | vary depending on this data. If the data is a program secret | |
5247 | chosen by the adversary using an LVI method, | |
5248 | then this data-dependent behavior may leak some aspect | |
5249 | of the secret. */ | |
aa4c197d | 5250 | if (((i.tm.base_opcode | 0x9) == 0xaf) |
a09f656b | 5251 | && i.prefix[REP_PREFIX]) |
5252 | { | |
5253 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
76d3f746 | 5254 | insn_name (&i.tm)); |
a09f656b | 5255 | } |
ae531041 L |
5256 | char *p = frag_more (3); |
5257 | *p++ = 0xf; | |
5258 | *p++ = 0xae; | |
5259 | *p = 0xe8; | |
5260 | } | |
5261 | } | |
5262 | ||
5263 | /* Output lfence, 0xfaee8, before instruction. */ | |
5264 | ||
5265 | static void | |
b5482fe5 | 5266 | insert_lfence_before (const struct last_insn *last_insn) |
ae531041 L |
5267 | { |
5268 | char *p; | |
5269 | ||
ddb62495 | 5270 | if (i.tm.opcode_space != SPACE_BASE) |
ae531041 L |
5271 | return; |
5272 | ||
5273 | if (i.tm.base_opcode == 0xff | |
5274 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
5275 | { | |
5276 | /* Insert lfence before indirect branch if needed. */ | |
5277 | ||
5278 | if (lfence_before_indirect_branch == lfence_branch_none) | |
5279 | return; | |
5280 | ||
5281 | if (i.operands != 1) | |
5282 | abort (); | |
5283 | ||
5284 | if (i.reg_operands == 1) | |
5285 | { | |
5286 | /* Indirect branch via register. Don't insert lfence with | |
5287 | -mlfence-after-load=yes. */ | |
5288 | if (lfence_after_load | |
5289 | || lfence_before_indirect_branch == lfence_branch_memory) | |
5290 | return; | |
5291 | } | |
5292 | else if (i.mem_operands == 1 | |
5293 | && lfence_before_indirect_branch != lfence_branch_register) | |
5294 | { | |
5295 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
76d3f746 | 5296 | insn_name (&i.tm)); |
ae531041 L |
5297 | return; |
5298 | } | |
5299 | else | |
5300 | return; | |
5301 | ||
b5482fe5 | 5302 | if (last_insn->kind != last_insn_other) |
ae531041 | 5303 | { |
b5482fe5 | 5304 | as_warn_where (last_insn->file, last_insn->line, |
ae531041 | 5305 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), |
b5482fe5 | 5306 | last_insn->name, insn_name (&i.tm)); |
ae531041 L |
5307 | return; |
5308 | } | |
5309 | ||
5310 | p = frag_more (3); | |
5311 | *p++ = 0xf; | |
5312 | *p++ = 0xae; | |
5313 | *p = 0xe8; | |
5314 | return; | |
5315 | } | |
5316 | ||
503648e4 | 5317 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 | 5318 | if (lfence_before_ret != lfence_before_ret_none |
aa4c197d | 5319 | && (i.tm.base_opcode | 1) == 0xc3) |
ae531041 | 5320 | { |
b5482fe5 | 5321 | if (last_insn->kind != last_insn_other) |
ae531041 | 5322 | { |
b5482fe5 | 5323 | as_warn_where (last_insn->file, last_insn->line, |
ae531041 | 5324 | _("`%s` skips -mlfence-before-ret on `%s`"), |
b5482fe5 | 5325 | last_insn->name, insn_name (&i.tm)); |
ae531041 L |
5326 | return; |
5327 | } | |
a09f656b | 5328 | |
a09f656b | 5329 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 5330 | char prefix = flag_code == CODE_64BIT |
5331 | ? 0x48 | |
5332 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 5333 | |
5334 | if (lfence_before_ret == lfence_before_ret_not) | |
5335 | { | |
5336 | /* not: 0xf71424, may add prefix | |
5337 | for operand size override or 64-bit code. */ | |
5338 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
5339 | if (prefix) | |
5340 | *p++ = prefix; | |
ae531041 L |
5341 | *p++ = 0xf7; |
5342 | *p++ = 0x14; | |
5343 | *p++ = 0x24; | |
a09f656b | 5344 | if (prefix) |
5345 | *p++ = prefix; | |
ae531041 L |
5346 | *p++ = 0xf7; |
5347 | *p++ = 0x14; | |
5348 | *p++ = 0x24; | |
5349 | } | |
a09f656b | 5350 | else |
5351 | { | |
5352 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
5353 | if (prefix) | |
5354 | *p++ = prefix; | |
5355 | if (lfence_before_ret == lfence_before_ret_or) | |
5356 | { | |
5357 | /* or: 0x830c2400, may add prefix | |
5358 | for operand size override or 64-bit code. */ | |
5359 | *p++ = 0x83; | |
5360 | *p++ = 0x0c; | |
5361 | } | |
5362 | else | |
5363 | { | |
5364 | /* shl: 0xc1242400, may add prefix | |
5365 | for operand size override or 64-bit code. */ | |
5366 | *p++ = 0xc1; | |
5367 | *p++ = 0x24; | |
5368 | } | |
5369 | ||
5370 | *p++ = 0x24; | |
5371 | *p++ = 0x0; | |
5372 | } | |
5373 | ||
ae531041 L |
5374 | *p++ = 0xf; |
5375 | *p++ = 0xae; | |
5376 | *p = 0xe8; | |
5377 | } | |
5378 | } | |
5379 | ||
edd67638 JB |
5380 | /* Shared helper for md_assemble() and s_insn(). */ |
5381 | static void init_globals (void) | |
5382 | { | |
5383 | unsigned int j; | |
5384 | ||
5385 | memset (&i, '\0', sizeof (i)); | |
5386 | i.rounding.type = rc_none; | |
5387 | for (j = 0; j < MAX_OPERANDS; j++) | |
5388 | i.reloc[j] = NO_RELOC; | |
5389 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
5390 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
5391 | save_stack_p = save_stack; | |
5392 | } | |
5393 | ||
04784e33 JB |
5394 | /* Helper for md_assemble() to decide whether to prepare for a possible 2nd |
5395 | parsing pass. Instead of introducing a rarely use new insn attribute this | |
5396 | utilizes a common pattern between affected templates. It is deemed | |
5397 | acceptable that this will lead to unnecessary pass 2 preparations in a | |
5398 | limited set of cases. */ | |
5399 | static INLINE bool may_need_pass2 (const insn_template *t) | |
5400 | { | |
5401 | return t->opcode_modifier.sse2avx | |
5402 | /* Note that all SSE2AVX templates have at least one operand. */ | |
a28fedbc | 5403 | ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD |
ddb62495 | 5404 | : (t->opcode_space == SPACE_0F |
a28fedbc | 5405 | && (t->base_opcode | 1) == 0xbf) |
ddb62495 | 5406 | || (t->opcode_space == SPACE_BASE |
a28fedbc | 5407 | && t->base_opcode == 0x63); |
04784e33 JB |
5408 | } |
5409 | ||
c7defc53 IB |
5410 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
5411 | ||
5412 | /* DWARF register number for EFLAGS. Used for pushf/popf insns. */ | |
5413 | #define GINSN_DW2_REGNUM_EFLAGS 49 | |
5414 | /* DWARF register number for RSI. Used as dummy value when RegIP/RegIZ. */ | |
5415 | #define GINSN_DW2_REGNUM_RSI_DUMMY 4 | |
5416 | ||
5417 | /* Identify the callee-saved registers in System V AMD64 ABI. */ | |
5418 | ||
5419 | bool | |
5420 | x86_scfi_callee_saved_p (unsigned int dw2reg_num) | |
5421 | { | |
5422 | if (dw2reg_num == 3 /* rbx. */ | |
5423 | || dw2reg_num == REG_FP /* rbp. */ | |
5424 | || dw2reg_num == REG_SP /* rsp. */ | |
5425 | || (dw2reg_num >= 12 && dw2reg_num <= 15) /* r12 - r15. */) | |
5426 | return true; | |
5427 | ||
5428 | return false; | |
5429 | } | |
5430 | ||
5431 | /* Check whether an instruction prefix which affects operation size | |
5432 | accompanies. For insns in the legacy space, setting REX.W takes precedence | |
5433 | over the operand-size prefix (66H) when both are used. | |
5434 | ||
5435 | The current users of this API are in the handlers for PUSH, POP or other | |
5436 | instructions which affect the stack pointer implicitly: the operation size | |
5437 | (16, 32, or 64 bits) determines the amount by which the stack pointer is | |
5438 | incremented / decremented (2, 4 or 8). */ | |
5439 | ||
5440 | static bool | |
5441 | ginsn_opsize_prefix_p (void) | |
5442 | { | |
5443 | return (!(i.prefix[REX_PREFIX] & REX_W) && i.prefix[DATA_PREFIX]); | |
5444 | } | |
5445 | ||
5446 | /* Get the DWARF register number for the given register entry. | |
5447 | For specific byte/word/dword register accesses like al, cl, ah, ch, r8d, | |
5448 | r20w etc., we need to identify the DWARF register number for the | |
5449 | corresponding 8-byte GPR. | |
5450 | ||
5451 | This function is a hack - it relies on relative ordering of reg entries in | |
5452 | the i386_regtab. FIXME - it will be good to allow a more direct way to get | |
5453 | this information. */ | |
5454 | ||
5455 | static unsigned int | |
5456 | ginsn_dw2_regnum (const reg_entry *ireg) | |
5457 | { | |
c7defc53 | 5458 | const reg_entry *temp = ireg; |
066673f6 | 5459 | unsigned int dwarf_reg = Dw2Inval, idx = 0; |
c7defc53 IB |
5460 | |
5461 | /* ginsn creation is available for AMD64 abi only ATM. Other flag_code | |
5462 | are not expected. */ | |
5463 | gas_assert (ireg && flag_code == CODE_64BIT); | |
5464 | ||
5465 | /* Watch out for RegIP, RegIZ. These are expected to appear only with | |
5466 | base/index addressing modes. Although creating inaccurate data | |
5467 | dependencies, using a dummy value (lets say volatile register rsi) will | |
5468 | not hurt SCFI. TBD_GINSN_GEN_NOT_SCFI. */ | |
5469 | if (ireg->reg_num == RegIP || ireg->reg_num == RegIZ) | |
5470 | return GINSN_DW2_REGNUM_RSI_DUMMY; | |
5471 | ||
fabb73d1 | 5472 | dwarf_reg = ireg->dw2_regnum[object_64bit]; |
c7defc53 IB |
5473 | |
5474 | if (dwarf_reg == Dw2Inval) | |
5475 | { | |
5476 | if (ireg <= &i386_regtab[3]) | |
5477 | /* For al, cl, dl, bl, bump over to axl, cxl, dxl, bxl respectively by | |
5478 | adding 8. */ | |
5479 | temp = ireg + 8; | |
5480 | else if (ireg <= &i386_regtab[7]) | |
5481 | /* For ah, ch, dh, bh, bump over to axl, cxl, dxl, bxl respectively by | |
5482 | adding 4. */ | |
5483 | temp = ireg + 4; | |
5484 | else | |
5485 | { | |
5486 | /* The code relies on the relative ordering of the reg entries in | |
5487 | i386_regtab. There are 32 register entries between axl-r31b, | |
5488 | ax-r31w etc. The assertions here ensures the code does not | |
5489 | recurse indefinitely. */ | |
5490 | gas_assert ((temp - &i386_regtab[0]) >= 0); | |
5491 | idx = temp - &i386_regtab[0]; | |
5492 | gas_assert (idx + 32 < i386_regtab_size - 1); | |
5493 | ||
5494 | temp = temp + 32; | |
5495 | } | |
5496 | ||
5497 | dwarf_reg = ginsn_dw2_regnum (temp); | |
5498 | } | |
5499 | ||
5500 | /* Sanity check - failure may indicate state corruption, bad ginsn or | |
5501 | perhaps the i386-reg table and the current function got out of sync. */ | |
066673f6 | 5502 | gas_assert (dwarf_reg < Dw2Inval); |
c7defc53 | 5503 | |
066673f6 | 5504 | return dwarf_reg; |
c7defc53 IB |
5505 | } |
5506 | ||
5507 | static ginsnS * | |
5508 | x86_ginsn_addsub_reg_mem (const symbolS *insn_end_sym) | |
5509 | { | |
5510 | unsigned int dw2_regnum; | |
5511 | unsigned int src1_dw2_regnum; | |
5512 | ginsnS *ginsn = NULL; | |
5513 | ginsnS * (*ginsn_func) (const symbolS *, bool, | |
5514 | enum ginsn_src_type, unsigned int, offsetT, | |
5515 | enum ginsn_src_type, unsigned int, offsetT, | |
5516 | enum ginsn_dst_type, unsigned int, offsetT); | |
5517 | uint16_t opcode = i.tm.base_opcode; | |
5518 | ||
5519 | gas_assert (i.tm.opcode_space == SPACE_BASE | |
5520 | && (opcode == 0x1 || opcode == 0x29)); | |
5521 | ginsn_func = (opcode == 0x1) ? ginsn_new_add : ginsn_new_sub; | |
5522 | ||
5523 | /* op %reg, symbol or even other cases where destination involves indirect | |
5524 | access are unnecessary for SCFI correctness. TBD_GINSN_GEN_NOT_SCFI. */ | |
5525 | if (i.mem_operands) | |
5526 | return ginsn; | |
5527 | ||
f8c50ae2 IB |
5528 | /* Skip detection of 8/16/32-bit op size; 'add/sub reg, reg/mem' ops always |
5529 | make the dest reg untraceable for SCFI. */ | |
5530 | ||
c7defc53 IB |
5531 | /* op reg, reg/mem. */ |
5532 | src1_dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
5533 | /* Of interest only when second opnd is not memory. */ | |
5534 | if (i.reg_operands == 2) | |
5535 | { | |
5536 | dw2_regnum = ginsn_dw2_regnum (i.op[1].regs); | |
5537 | ginsn = ginsn_func (insn_end_sym, true, | |
5538 | GINSN_SRC_REG, src1_dw2_regnum, 0, | |
5539 | GINSN_SRC_REG, dw2_regnum, 0, | |
5540 | GINSN_DST_REG, dw2_regnum, 0); | |
5541 | ginsn_set_where (ginsn); | |
5542 | } | |
5543 | ||
5544 | return ginsn; | |
5545 | } | |
5546 | ||
5547 | static ginsnS * | |
5548 | x86_ginsn_addsub_mem_reg (const symbolS *insn_end_sym) | |
5549 | { | |
5550 | unsigned int dw2_regnum; | |
5551 | unsigned int src1_dw2_regnum; | |
5552 | const reg_entry *mem_reg; | |
5553 | int32_t gdisp = 0; | |
5554 | ginsnS *ginsn = NULL; | |
5555 | ginsnS * (*ginsn_func) (const symbolS *, bool, | |
5556 | enum ginsn_src_type, unsigned int, offsetT, | |
5557 | enum ginsn_src_type, unsigned int, offsetT, | |
5558 | enum ginsn_dst_type, unsigned int, offsetT); | |
5559 | uint16_t opcode = i.tm.base_opcode; | |
5560 | ||
5561 | gas_assert (i.tm.opcode_space == SPACE_BASE | |
5562 | && (opcode == 0x3 || opcode == 0x2b)); | |
5563 | ginsn_func = (opcode == 0x3) ? ginsn_new_add : ginsn_new_sub; | |
5564 | ||
5565 | /* op symbol, %reg. */ | |
5566 | if (i.mem_operands && !i.base_reg && !i.index_reg) | |
5567 | return ginsn; | |
5568 | ||
f8c50ae2 IB |
5569 | /* Skip detection of 8/16/32-bit op size; 'add/sub reg/mem, reg' ops always |
5570 | make the dest reg untraceable for SCFI. */ | |
5571 | ||
c7defc53 IB |
5572 | /* op reg/mem, %reg. */ |
5573 | dw2_regnum = ginsn_dw2_regnum (i.op[1].regs); | |
5574 | ||
5575 | if (i.reg_operands == 2) | |
5576 | { | |
5577 | src1_dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
5578 | ginsn = ginsn_func (insn_end_sym, true, | |
5579 | GINSN_SRC_REG, src1_dw2_regnum, 0, | |
5580 | GINSN_SRC_REG, dw2_regnum, 0, | |
5581 | GINSN_DST_REG, dw2_regnum, 0); | |
5582 | ginsn_set_where (ginsn); | |
5583 | } | |
5584 | else if (i.mem_operands) | |
5585 | { | |
5586 | mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; | |
5587 | src1_dw2_regnum = ginsn_dw2_regnum (mem_reg); | |
5588 | if (i.disp_operands == 1) | |
5589 | gdisp = i.op[0].disps->X_add_number; | |
5590 | ginsn = ginsn_func (insn_end_sym, true, | |
5591 | GINSN_SRC_INDIRECT, src1_dw2_regnum, gdisp, | |
5592 | GINSN_SRC_REG, dw2_regnum, 0, | |
5593 | GINSN_DST_REG, dw2_regnum, 0); | |
5594 | ginsn_set_where (ginsn); | |
5595 | } | |
5596 | ||
5597 | return ginsn; | |
5598 | } | |
5599 | ||
5600 | static ginsnS * | |
5601 | x86_ginsn_alu_imm (const symbolS *insn_end_sym) | |
5602 | { | |
5603 | offsetT src_imm; | |
5604 | unsigned int dw2_regnum; | |
5605 | ginsnS *ginsn = NULL; | |
5606 | enum ginsn_src_type src_type = GINSN_SRC_REG; | |
5607 | enum ginsn_dst_type dst_type = GINSN_DST_REG; | |
5608 | ||
5609 | ginsnS * (*ginsn_func) (const symbolS *, bool, | |
5610 | enum ginsn_src_type, unsigned int, offsetT, | |
5611 | enum ginsn_src_type, unsigned int, offsetT, | |
5612 | enum ginsn_dst_type, unsigned int, offsetT); | |
5613 | ||
5614 | /* FIXME - create ginsn where dest is REG_SP / REG_FP only ? */ | |
5615 | /* Map for insn.tm.extension_opcode | |
5616 | 000 ADD 100 AND | |
5617 | 001 OR 101 SUB | |
5618 | 010 ADC 110 XOR | |
5619 | 011 SBB 111 CMP */ | |
5620 | ||
5621 | /* add/sub/and imm, %reg only at this time for SCFI. | |
5622 | Although all three ('and', 'or' , 'xor') make the destination reg | |
5623 | untraceable, 'and' op is handled but not 'or' / 'xor' because we will look | |
5624 | into supporting the DRAP pattern at some point. Other opcodes ('adc', | |
5625 | 'sbb' and 'cmp') are not generated here either. The ginsn representation | |
5626 | does not have support for the latter three opcodes; GINSN_TYPE_OTHER may | |
5627 | be added for these after x86_ginsn_unhandled () invocation if the | |
5628 | destination register is REG_SP or REG_FP. */ | |
5629 | if (i.tm.extension_opcode == 5) | |
5630 | ginsn_func = ginsn_new_sub; | |
5631 | else if (i.tm.extension_opcode == 4) | |
5632 | ginsn_func = ginsn_new_and; | |
5633 | else if (i.tm.extension_opcode == 0) | |
5634 | ginsn_func = ginsn_new_add; | |
5635 | else | |
5636 | return ginsn; | |
5637 | ||
5638 | /* TBD_GINSN_REPRESENTATION_LIMIT: There is no representation for when a | |
5639 | symbol is used as an operand, like so: | |
5640 | addq $simd_cmp_op+8, %rdx | |
5641 | Skip generating any ginsn for this. */ | |
5642 | if (i.imm_operands == 1 | |
5643 | && i.op[0].imms->X_op != O_constant) | |
5644 | return ginsn; | |
5645 | ||
5646 | /* addq $1, symbol | |
5647 | addq $1, -16(%rbp) | |
5648 | These are not of interest for SCFI. Also, TBD_GINSN_GEN_NOT_SCFI. */ | |
5649 | if (i.mem_operands == 1) | |
5650 | return ginsn; | |
5651 | ||
f8c50ae2 IB |
5652 | /* 8/16/32-bit op size makes the destination reg untraceable for SCFI. |
5653 | Deal with this via the x86_ginsn_unhandled () code path. */ | |
5654 | if (i.suffix != QWORD_MNEM_SUFFIX) | |
5655 | return ginsn; | |
5656 | ||
c7defc53 IB |
5657 | gas_assert (i.imm_operands == 1); |
5658 | src_imm = i.op[0].imms->X_add_number; | |
5659 | /* The second operand may be a register or indirect access. For SCFI, only | |
5660 | the case when the second opnd is a register is interesting. Revisit this | |
5661 | if generating ginsns for a different gen mode TBD_GINSN_GEN_NOT_SCFI. */ | |
5662 | if (i.reg_operands == 1) | |
5663 | { | |
5664 | dw2_regnum = ginsn_dw2_regnum (i.op[1].regs); | |
5665 | /* For ginsn, keep the imm as second src operand. */ | |
5666 | ginsn = ginsn_func (insn_end_sym, true, | |
5667 | src_type, dw2_regnum, 0, | |
5668 | GINSN_SRC_IMM, 0, src_imm, | |
5669 | dst_type, dw2_regnum, 0); | |
5670 | ||
5671 | ginsn_set_where (ginsn); | |
5672 | } | |
5673 | ||
5674 | return ginsn; | |
5675 | } | |
5676 | ||
5677 | /* Create ginsn(s) for MOV operations. | |
5678 | ||
5679 | The generated ginsns corresponding to mov with indirect access to memory | |
5680 | (src or dest) suffer with loss of information: when both index and base | |
5681 | registers are at play, only base register gets conveyed in ginsn. Note | |
5682 | this TBD_GINSN_GEN_NOT_SCFI. */ | |
5683 | ||
5684 | static ginsnS * | |
5685 | x86_ginsn_move (const symbolS *insn_end_sym) | |
5686 | { | |
5687 | ginsnS *ginsn = NULL; | |
5688 | unsigned int dst_reg; | |
5689 | unsigned int src_reg; | |
5690 | offsetT src_disp = 0; | |
5691 | offsetT dst_disp = 0; | |
5692 | const reg_entry *dst = NULL; | |
5693 | const reg_entry *src = NULL; | |
5694 | uint16_t opcode = i.tm.base_opcode; | |
5695 | enum ginsn_src_type src_type = GINSN_SRC_REG; | |
5696 | enum ginsn_dst_type dst_type = GINSN_DST_REG; | |
5697 | ||
5698 | /* mov %reg, symbol or mov symbol, %reg. | |
5699 | Not of interest for SCFI. Also, TBD_GINSN_GEN_NOT_SCFI. */ | |
5700 | if (i.mem_operands == 1 && !i.base_reg && !i.index_reg) | |
5701 | return ginsn; | |
5702 | ||
f8c50ae2 IB |
5703 | /* 8/16/32-bit op size makes the destination reg untraceable for SCFI. |
5704 | Handle mov reg, reg only. mov to or from a memory operand will make | |
5705 | dest reg, when present, untraceable, irrespective of the op size. */ | |
5706 | if (i.reg_operands == 2 && i.suffix != QWORD_MNEM_SUFFIX) | |
5707 | return ginsn; | |
5708 | ||
c7defc53 IB |
5709 | gas_assert (i.tm.opcode_space == SPACE_BASE); |
5710 | if (opcode == 0x8b || opcode == 0x8a) | |
5711 | { | |
5712 | /* mov disp(%reg), %reg. */ | |
5713 | if (i.mem_operands) | |
5714 | { | |
5715 | src = (i.base_reg) ? i.base_reg : i.index_reg; | |
5716 | if (i.disp_operands == 1) | |
5717 | src_disp = i.op[0].disps->X_add_number; | |
5718 | src_type = GINSN_SRC_INDIRECT; | |
5719 | } | |
5720 | else | |
5721 | src = i.op[0].regs; | |
5722 | ||
5723 | dst = i.op[1].regs; | |
5724 | } | |
5725 | else if (opcode == 0x89 || opcode == 0x88) | |
5726 | { | |
5727 | /* mov %reg, disp(%reg). */ | |
5728 | src = i.op[0].regs; | |
5729 | if (i.mem_operands) | |
5730 | { | |
5731 | dst = (i.base_reg) ? i.base_reg : i.index_reg; | |
5732 | if (i.disp_operands == 1) | |
5733 | dst_disp = i.op[1].disps->X_add_number; | |
5734 | dst_type = GINSN_DST_INDIRECT; | |
5735 | } | |
5736 | else | |
5737 | dst = i.op[1].regs; | |
5738 | } | |
5739 | ||
5740 | src_reg = ginsn_dw2_regnum (src); | |
5741 | dst_reg = ginsn_dw2_regnum (dst); | |
5742 | ||
5743 | ginsn = ginsn_new_mov (insn_end_sym, true, | |
5744 | src_type, src_reg, src_disp, | |
5745 | dst_type, dst_reg, dst_disp); | |
5746 | ginsn_set_where (ginsn); | |
5747 | ||
5748 | return ginsn; | |
5749 | } | |
5750 | ||
5751 | /* Generate appropriate ginsn for lea. | |
09812f08 IB |
5752 | |
5753 | Unhandled sub-cases (marked with TBD_GINSN_GEN_NOT_SCFI) also suffer with | |
5754 | some loss of information in the final ginsn chosen eventually (type | |
5755 | GINSN_TYPE_OTHER). But this is fine for now for GINSN_GEN_SCFI generation | |
c7defc53 IB |
5756 | mode. */ |
5757 | ||
5758 | static ginsnS * | |
5759 | x86_ginsn_lea (const symbolS *insn_end_sym) | |
5760 | { | |
5761 | offsetT src_disp = 0; | |
5762 | ginsnS *ginsn = NULL; | |
09812f08 IB |
5763 | unsigned int src1_reg; |
5764 | const reg_entry *src1; | |
c7defc53 IB |
5765 | offsetT index_scale; |
5766 | unsigned int dst_reg; | |
09812f08 | 5767 | bool index_regiz_p; |
c7defc53 | 5768 | |
03fa0c63 | 5769 | if ((!i.base_reg) != (!i.index_reg || i.index_reg->reg_num == RegIZ)) |
c7defc53 | 5770 | { |
09812f08 IB |
5771 | /* lea disp(%base), %dst or lea disp(,%index,imm), %dst. |
5772 | Either index_reg or base_reg exists, but not both. Further, as per | |
5773 | above, the case when just %index exists but is equal to RegIZ is | |
5774 | excluded. If not excluded, a GINSN_TYPE_MOV of %rsi | |
5775 | (GINSN_DW2_REGNUM_RSI_DUMMY) to %dst will be generated by this block. | |
5776 | Such a mov ginsn is imprecise; so, exclude now and generate | |
5777 | GINSN_TYPE_OTHER instead later via the x86_ginsn_unhandled (). | |
5778 | Excluding other cases is required due to | |
5779 | TBD_GINSN_REPRESENTATION_LIMIT. */ | |
c7defc53 | 5780 | |
c7defc53 | 5781 | index_scale = i.log2_scale_factor; |
09812f08 IB |
5782 | index_regiz_p = i.index_reg && i.index_reg->reg_num == RegIZ; |
5783 | src1 = i.base_reg ? i.base_reg : i.index_reg; | |
5784 | src1_reg = ginsn_dw2_regnum (src1); | |
c7defc53 | 5785 | dst_reg = ginsn_dw2_regnum (i.op[1].regs); |
09812f08 IB |
5786 | /* It makes sense to represent a scale factor of 1 precisely here |
5787 | (i.e., not using GINSN_TYPE_OTHER, but rather similar to the | |
5788 | base-without-index case). A non-zero scale factor is still OK if | |
5789 | the index reg is zero reg. | |
5790 | However, skip from here the case when disp has a symbol instead. | |
5791 | TBD_GINSN_REPRESENTATION_LIMIT. */ | |
5792 | if ((!index_scale || index_regiz_p) | |
5793 | && (!i.disp_operands || i.op[0].disps->X_op == O_constant)) | |
5794 | { | |
5795 | if (i.disp_operands) | |
5796 | src_disp = i.op[0].disps->X_add_number; | |
c7defc53 | 5797 | |
09812f08 IB |
5798 | if (src_disp) |
5799 | /* Generate an ADD ginsn. */ | |
5800 | ginsn = ginsn_new_add (insn_end_sym, true, | |
5801 | GINSN_SRC_REG, src1_reg, 0, | |
5802 | GINSN_SRC_IMM, 0, src_disp, | |
5803 | GINSN_DST_REG, dst_reg, 0); | |
5804 | else | |
5805 | /* Generate a MOV ginsn. */ | |
5806 | ginsn = ginsn_new_mov (insn_end_sym, true, | |
5807 | GINSN_SRC_REG, src1_reg, 0, | |
5808 | GINSN_DST_REG, dst_reg, 0); | |
5809 | ||
5810 | ginsn_set_where (ginsn); | |
5811 | } | |
5812 | } | |
5813 | /* Skip handling other cases here, | |
5814 | - when (i.index_reg && i.base_reg) is true, | |
5815 | e.g., lea disp(%base,%index,imm), %dst | |
5816 | We do not have a ginsn representation for multiply. | |
5817 | - or, when (!i.index_reg && !i.base_reg) is true, | |
5818 | e.g., lea symbol, %dst | |
5819 | Not a frequent pattern. If %dst is a register of interest, the user is | |
5820 | likely to use a MOV op anyway. | |
5821 | Deal with these via the x86_ginsn_unhandled () code path to generate | |
5822 | GINSN_TYPE_OTHER when necessary. TBD_GINSN_GEN_NOT_SCFI. */ | |
c7defc53 IB |
5823 | |
5824 | return ginsn; | |
5825 | } | |
5826 | ||
5827 | static ginsnS * | |
5828 | x86_ginsn_jump (const symbolS *insn_end_sym, bool cond_p) | |
5829 | { | |
5830 | ginsnS *ginsn = NULL; | |
5831 | const symbolS *src_symbol; | |
5832 | ginsnS * (*ginsn_func) (const symbolS *sym, bool real_p, | |
5833 | enum ginsn_src_type src_type, unsigned int src_reg, | |
5834 | const symbolS *src_ginsn_sym); | |
5835 | ||
5836 | gas_assert (i.disp_operands == 1); | |
5837 | ||
5838 | ginsn_func = cond_p ? ginsn_new_jump_cond : ginsn_new_jump; | |
5839 | if (i.op[0].disps->X_op == O_symbol && !i.op[0].disps->X_add_number) | |
5840 | { | |
5841 | src_symbol = i.op[0].disps->X_add_symbol; | |
5842 | ginsn = ginsn_func (insn_end_sym, true, | |
5843 | GINSN_SRC_SYMBOL, 0, src_symbol); | |
5844 | ||
5845 | ginsn_set_where (ginsn); | |
5846 | } | |
5847 | else | |
5848 | { | |
5849 | /* A non-zero addend in jump/JCC target makes control-flow tracking | |
5850 | difficult. Skip SCFI for now. */ | |
5851 | as_bad (_("SCFI: `%s' insn with non-zero addend to sym not supported"), | |
5852 | cond_p ? "JCC" : "jmp"); | |
5853 | return ginsn; | |
5854 | } | |
5855 | ||
5856 | return ginsn; | |
5857 | } | |
5858 | ||
5859 | static ginsnS * | |
5860 | x86_ginsn_enter (const symbolS *insn_end_sym) | |
5861 | { | |
5862 | ginsnS *ginsn = NULL; | |
5863 | ginsnS *ginsn_next = NULL; | |
5864 | ginsnS *ginsn_last = NULL; | |
5865 | /* In 64-bit mode, the default stack update size is 8 bytes. */ | |
5866 | int stack_opnd_size = 8; | |
5867 | ||
5868 | gas_assert (i.imm_operands == 2); | |
5869 | ||
5870 | /* For non-zero size operands, bail out as untraceable for SCFI. */ | |
5871 | if (i.op[0].imms->X_op != O_constant || i.op[0].imms->X_add_symbol != 0 | |
5872 | || i.op[1].imms->X_op != O_constant || i.op[1].imms->X_add_symbol != 0) | |
5873 | { | |
5874 | as_bad ("SCFI: enter insn with non-zero operand not supported"); | |
5875 | return ginsn; | |
5876 | } | |
5877 | ||
5878 | /* Check if this is a 16-bit op. */ | |
5879 | if (ginsn_opsize_prefix_p ()) | |
5880 | stack_opnd_size = 2; | |
5881 | ||
5882 | /* If the nesting level is 0, the processor pushes the frame pointer from | |
5883 | the BP/EBP/RBP register onto the stack, copies the current stack | |
5884 | pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and | |
5885 | loads the SP/ESP/RSP register with the current stack-pointer value | |
5886 | minus the value in the size operand. */ | |
5887 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
5888 | GINSN_SRC_REG, REG_SP, 0, | |
5889 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
5890 | GINSN_DST_REG, REG_SP, 0); | |
5891 | ginsn_set_where (ginsn); | |
5892 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
5893 | GINSN_SRC_REG, REG_FP, | |
5894 | GINSN_DST_INDIRECT, REG_SP, 0); | |
5895 | ginsn_set_where (ginsn_next); | |
5896 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
5897 | ginsn_last = ginsn_new_mov (insn_end_sym, false, | |
5898 | GINSN_SRC_REG, REG_SP, 0, | |
5899 | GINSN_DST_REG, REG_FP, 0); | |
5900 | ginsn_set_where (ginsn_last); | |
5901 | gas_assert (!ginsn_link_next (ginsn_next, ginsn_last)); | |
5902 | ||
5903 | return ginsn; | |
5904 | } | |
5905 | ||
5906 | static ginsnS * | |
5907 | x86_ginsn_leave (const symbolS *insn_end_sym) | |
5908 | { | |
5909 | ginsnS *ginsn = NULL; | |
5910 | ginsnS *ginsn_next = NULL; | |
5911 | ginsnS *ginsn_last = NULL; | |
5912 | /* In 64-bit mode, the default stack update size is 8 bytes. */ | |
5913 | int stack_opnd_size = 8; | |
5914 | ||
5915 | /* Check if this is a 16-bit op. */ | |
5916 | if (ginsn_opsize_prefix_p ()) | |
5917 | stack_opnd_size = 2; | |
5918 | ||
5919 | /* The 'leave' instruction copies the contents of the RBP register | |
5920 | into the RSP register to release all stack space allocated to the | |
5921 | procedure. */ | |
5922 | ginsn = ginsn_new_mov (insn_end_sym, false, | |
5923 | GINSN_SRC_REG, REG_FP, 0, | |
5924 | GINSN_DST_REG, REG_SP, 0); | |
5925 | ginsn_set_where (ginsn); | |
5926 | /* Then it restores the old value of the RBP register from the stack. */ | |
5927 | ginsn_next = ginsn_new_load (insn_end_sym, false, | |
5928 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
5929 | GINSN_DST_REG, REG_FP); | |
5930 | ginsn_set_where (ginsn_next); | |
5931 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
5932 | ginsn_last = ginsn_new_add (insn_end_sym, false, | |
5933 | GINSN_SRC_REG, REG_SP, 0, | |
5934 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
5935 | GINSN_DST_REG, REG_SP, 0); | |
5936 | ginsn_set_where (ginsn_next); | |
5937 | gas_assert (!ginsn_link_next (ginsn_next, ginsn_last)); | |
5938 | ||
5939 | return ginsn; | |
5940 | } | |
5941 | ||
5942 | /* Check if an instruction is whitelisted. | |
5943 | ||
5944 | Some instructions may appear with REG_SP or REG_FP as destination, because | |
5945 | which they are deemed 'interesting' for SCFI. Whitelist them here if they | |
5946 | do not affect SCFI correctness. */ | |
5947 | ||
5948 | static bool | |
5949 | x86_ginsn_safe_to_skip_p (void) | |
5950 | { | |
5951 | bool skip_p = false; | |
5952 | uint16_t opcode = i.tm.base_opcode; | |
5953 | ||
5954 | switch (opcode) | |
5955 | { | |
5956 | case 0x80: | |
5957 | case 0x81: | |
5958 | case 0x83: | |
5959 | if (i.tm.opcode_space != SPACE_BASE) | |
5960 | break; | |
5961 | /* cmp imm, reg/rem. */ | |
5962 | if (i.tm.extension_opcode == 7) | |
5963 | skip_p = true; | |
5964 | break; | |
5965 | ||
5966 | case 0x38: | |
5967 | case 0x39: | |
5968 | case 0x3a: | |
5969 | case 0x3b: | |
5970 | if (i.tm.opcode_space != SPACE_BASE) | |
5971 | break; | |
5972 | /* cmp imm/reg/mem, reg/rem. */ | |
5973 | skip_p = true; | |
5974 | break; | |
5975 | ||
5976 | case 0xf6: | |
5977 | case 0xf7: | |
5978 | case 0x84: | |
5979 | case 0x85: | |
5980 | /* test imm/reg/mem, reg/mem. */ | |
5981 | if (i.tm.opcode_space != SPACE_BASE) | |
5982 | break; | |
5983 | skip_p = true; | |
5984 | break; | |
5985 | ||
5986 | default: | |
5987 | break; | |
5988 | } | |
5989 | ||
5990 | return skip_p; | |
5991 | } | |
5992 | ||
5993 | #define X86_GINSN_UNHANDLED_NONE 0 | |
5994 | #define X86_GINSN_UNHANDLED_DEST_REG 1 | |
5995 | #define X86_GINSN_UNHANDLED_CFG 2 | |
5996 | #define X86_GINSN_UNHANDLED_STACKOP 3 | |
5997 | #define X86_GINSN_UNHANDLED_UNEXPECTED 4 | |
5998 | ||
5999 | /* Check the input insn for its impact on the correctness of the synthesized | |
6000 | CFI. Returns an error code to the caller. */ | |
6001 | ||
6002 | static int | |
6003 | x86_ginsn_unhandled (void) | |
6004 | { | |
6005 | int err = X86_GINSN_UNHANDLED_NONE; | |
6006 | const reg_entry *reg_op; | |
6007 | unsigned int dw2_regnum; | |
6008 | ||
6009 | /* Keep an eye out for instructions affecting control flow. */ | |
6010 | if (i.tm.opcode_modifier.jump) | |
6011 | err = X86_GINSN_UNHANDLED_CFG; | |
6012 | /* Also, for any instructions involving an implicit update to the stack | |
6013 | pointer. */ | |
6014 | else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_STACK_OP) | |
6015 | err = X86_GINSN_UNHANDLED_STACKOP; | |
6016 | /* Finally, also check if the missed instructions are affecting REG_SP or | |
6017 | REG_FP. The destination operand is the last at all stages of assembly | |
6018 | (due to following AT&T syntax layout in the internal representation). In | |
6019 | case of Intel syntax input, this still remains true as swap_operands () | |
6020 | is done by now. | |
6021 | PS: These checks do not involve index / base reg, as indirect memory | |
6022 | accesses via REG_SP or REG_FP do not affect SCFI correctness. | |
6023 | (Also note these instructions are candidates for other ginsn generation | |
6024 | modes in future. TBD_GINSN_GEN_NOT_SCFI.) */ | |
6025 | else if (i.operands && i.reg_operands | |
6026 | && !(i.flags[i.operands - 1] & Operand_Mem)) | |
6027 | { | |
6028 | reg_op = i.op[i.operands - 1].regs; | |
6029 | if (reg_op) | |
6030 | { | |
6031 | dw2_regnum = ginsn_dw2_regnum (reg_op); | |
6032 | if (dw2_regnum == REG_SP || dw2_regnum == REG_FP) | |
6033 | err = X86_GINSN_UNHANDLED_DEST_REG; | |
6034 | } | |
6035 | else | |
6036 | /* Something unexpected. Indicate to caller. */ | |
6037 | err = X86_GINSN_UNHANDLED_UNEXPECTED; | |
6038 | } | |
6039 | ||
6040 | return err; | |
6041 | } | |
6042 | ||
6043 | /* Generate one or more generic GAS instructions, a.k.a, ginsns for the current | |
6044 | machine instruction. | |
6045 | ||
6046 | Returns the head of linked list of ginsn(s) added, if success; Returns NULL | |
6047 | if failure. | |
6048 | ||
6049 | The input ginsn_gen_mode GMODE determines the set of minimal necessary | |
6050 | ginsns necessary for correctness of any passes applicable for that mode. | |
6051 | For supporting the GINSN_GEN_SCFI generation mode, following is the list of | |
6052 | machine instructions that must be translated into the corresponding ginsns | |
6053 | to ensure correctness of SCFI: | |
6054 | - All instructions affecting the two registers that could potentially | |
6055 | be used as the base register for CFA tracking. For SCFI, the base | |
6056 | register for CFA tracking is limited to REG_SP and REG_FP only for | |
6057 | now. | |
6058 | - All change of flow instructions: conditional and unconditional branches, | |
6059 | call and return from functions. | |
6060 | - All instructions that can potentially be a register save / restore | |
6061 | operation. | |
6062 | - All instructions that perform stack manipulation implicitly: the CALL, | |
6063 | RET, PUSH, POP, ENTER, and LEAVE instructions. | |
6064 | ||
6065 | The function currently supports GINSN_GEN_SCFI ginsn generation mode only. | |
6066 | To support other generation modes will require work on this target-specific | |
6067 | process of creation of ginsns: | |
6068 | - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as | |
6069 | possible starting points. | |
6070 | - Also note that ginsn representation may need enhancements. Specifically, | |
6071 | note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers. | |
6072 | */ | |
6073 | ||
6074 | static ginsnS * | |
6075 | x86_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode) | |
6076 | { | |
6077 | int err = 0; | |
6078 | uint16_t opcode; | |
6079 | unsigned int dw2_regnum; | |
6080 | const reg_entry *mem_reg; | |
6081 | ginsnS *ginsn = NULL; | |
6082 | ginsnS *ginsn_next = NULL; | |
6083 | /* In 64-bit mode, the default stack update size is 8 bytes. */ | |
6084 | int stack_opnd_size = 8; | |
6085 | ||
6086 | /* Currently supports generation of selected ginsns, sufficient for | |
6087 | the use-case of SCFI only. */ | |
6088 | if (gmode != GINSN_GEN_SCFI) | |
6089 | return ginsn; | |
6090 | ||
6091 | opcode = i.tm.base_opcode; | |
6092 | ||
6093 | /* Until it is clear how to handle APX NDD and other new opcodes, disallow | |
6094 | them from SCFI. */ | |
6095 | if (is_apx_rex2_encoding () | |
6096 | || (i.tm.opcode_modifier.evex && is_apx_evex_encoding ())) | |
6097 | { | |
6098 | as_bad (_("SCFI: unsupported APX op %#x may cause incorrect CFI"), | |
6099 | opcode); | |
6100 | return ginsn; | |
6101 | } | |
6102 | ||
6103 | switch (opcode) | |
6104 | { | |
f8c50ae2 IB |
6105 | |
6106 | /* Add opcodes 0x0/0x2 and sub opcodes 0x28/0x2a (with opcode_space | |
6107 | SPACE_BASE) are 8-bit ops. While they are relevant for SCFI | |
6108 | correctness, skip handling them here and use the x86_ginsn_unhandled | |
6109 | code path to generate GINSN_TYPE_OTHER when necessary. */ | |
6110 | ||
c7defc53 IB |
6111 | case 0x1: /* add reg, reg/mem. */ |
6112 | case 0x29: /* sub reg, reg/mem. */ | |
6113 | if (i.tm.opcode_space != SPACE_BASE) | |
6114 | break; | |
6115 | ginsn = x86_ginsn_addsub_reg_mem (insn_end_sym); | |
6116 | break; | |
6117 | ||
6118 | case 0x3: /* add reg/mem, reg. */ | |
6119 | case 0x2b: /* sub reg/mem, reg. */ | |
6120 | if (i.tm.opcode_space != SPACE_BASE) | |
6121 | break; | |
6122 | ginsn = x86_ginsn_addsub_mem_reg (insn_end_sym); | |
6123 | break; | |
6124 | ||
6125 | case 0xa0: /* push fs. */ | |
6126 | case 0xa8: /* push gs. */ | |
6127 | /* push fs / push gs have opcode_space == SPACE_0F. */ | |
6128 | if (i.tm.opcode_space != SPACE_0F) | |
6129 | break; | |
6130 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6131 | /* Check if operation size is 16-bit. */ | |
6132 | if (ginsn_opsize_prefix_p ()) | |
6133 | stack_opnd_size = 2; | |
6134 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6135 | GINSN_SRC_REG, REG_SP, 0, | |
6136 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6137 | GINSN_DST_REG, REG_SP, 0); | |
6138 | ginsn_set_where (ginsn); | |
6139 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6140 | GINSN_SRC_REG, dw2_regnum, | |
6141 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6142 | ginsn_set_where (ginsn_next); | |
6143 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6144 | break; | |
6145 | ||
6146 | case 0xa1: /* pop fs. */ | |
6147 | case 0xa9: /* pop gs. */ | |
6148 | /* pop fs / pop gs have opcode_space == SPACE_0F. */ | |
6149 | if (i.tm.opcode_space != SPACE_0F) | |
6150 | break; | |
6151 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6152 | /* Check if operation size is 16-bit. */ | |
6153 | if (ginsn_opsize_prefix_p ()) | |
6154 | stack_opnd_size = 2; | |
6155 | ginsn = ginsn_new_load (insn_end_sym, false, | |
6156 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
6157 | GINSN_DST_REG, dw2_regnum); | |
6158 | ginsn_set_where (ginsn); | |
6159 | ginsn_next = ginsn_new_add (insn_end_sym, false, | |
6160 | GINSN_SRC_REG, REG_SP, 0, | |
6161 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6162 | GINSN_DST_REG, REG_SP, 0); | |
6163 | ginsn_set_where (ginsn_next); | |
6164 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6165 | break; | |
6166 | ||
6167 | case 0x50 ... 0x57: | |
6168 | if (i.tm.opcode_space != SPACE_BASE) | |
6169 | break; | |
6170 | /* push reg. */ | |
6171 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6172 | /* Check if operation size is 16-bit. */ | |
6173 | if (ginsn_opsize_prefix_p ()) | |
6174 | stack_opnd_size = 2; | |
6175 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6176 | GINSN_SRC_REG, REG_SP, 0, | |
6177 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6178 | GINSN_DST_REG, REG_SP, 0); | |
6179 | ginsn_set_where (ginsn); | |
6180 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6181 | GINSN_SRC_REG, dw2_regnum, | |
6182 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6183 | ginsn_set_where (ginsn_next); | |
6184 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6185 | break; | |
6186 | ||
6187 | case 0x58 ... 0x5f: | |
6188 | if (i.tm.opcode_space != SPACE_BASE) | |
6189 | break; | |
6190 | /* pop reg. */ | |
6191 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6192 | ginsn = ginsn_new_load (insn_end_sym, false, | |
6193 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
6194 | GINSN_DST_REG, dw2_regnum); | |
6195 | ginsn_set_where (ginsn); | |
6196 | /* Check if operation size is 16-bit. */ | |
6197 | if (ginsn_opsize_prefix_p ()) | |
6198 | stack_opnd_size = 2; | |
6199 | ginsn_next = ginsn_new_add (insn_end_sym, false, | |
6200 | GINSN_SRC_REG, REG_SP, 0, | |
6201 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6202 | GINSN_DST_REG, REG_SP, 0); | |
6203 | ginsn_set_where (ginsn_next); | |
6204 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6205 | break; | |
6206 | ||
6207 | case 0x6a: /* push imm8. */ | |
6208 | case 0x68: /* push imm16/imm32. */ | |
6209 | if (i.tm.opcode_space != SPACE_BASE) | |
6210 | break; | |
6211 | /* Check if operation size is 16-bit. */ | |
6212 | if (ginsn_opsize_prefix_p ()) | |
6213 | stack_opnd_size = 2; | |
6214 | /* Skip getting the value of imm from machine instruction | |
6215 | because this is not important for SCFI. */ | |
6216 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6217 | GINSN_SRC_REG, REG_SP, 0, | |
6218 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6219 | GINSN_DST_REG, REG_SP, 0); | |
6220 | ginsn_set_where (ginsn); | |
6221 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6222 | GINSN_SRC_IMM, 0, | |
6223 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6224 | ginsn_set_where (ginsn_next); | |
6225 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6226 | break; | |
6227 | ||
6228 | /* PS: Opcodes 0x80 ... 0x8f with opcode_space SPACE_0F are present | |
6229 | only after relaxation. They do not need to be handled for ginsn | |
6230 | creation. */ | |
6231 | case 0x70 ... 0x7f: | |
6232 | if (i.tm.opcode_space != SPACE_BASE) | |
6233 | break; | |
6234 | ginsn = x86_ginsn_jump (insn_end_sym, true); | |
6235 | break; | |
6236 | ||
6237 | case 0x80: | |
6238 | case 0x81: | |
6239 | case 0x83: | |
6240 | if (i.tm.opcode_space != SPACE_BASE) | |
6241 | break; | |
6242 | ginsn = x86_ginsn_alu_imm (insn_end_sym); | |
6243 | break; | |
6244 | ||
6245 | case 0x8a: /* mov r/m8, r8. */ | |
6246 | case 0x8b: /* mov r/m(16/32/64), r(16/32/64). */ | |
6247 | case 0x88: /* mov r8, r/m8. */ | |
6248 | case 0x89: /* mov r(16/32/64), r/m(16/32/64). */ | |
6249 | if (i.tm.opcode_space != SPACE_BASE) | |
6250 | break; | |
6251 | ginsn = x86_ginsn_move (insn_end_sym); | |
6252 | break; | |
6253 | ||
6254 | case 0x8d: | |
6255 | if (i.tm.opcode_space != SPACE_BASE) | |
6256 | break; | |
09812f08 | 6257 | /* lea disp(%base,%index,imm), %dst. */ |
c7defc53 IB |
6258 | ginsn = x86_ginsn_lea (insn_end_sym); |
6259 | break; | |
6260 | ||
6261 | case 0x8f: | |
6262 | if (i.tm.opcode_space != SPACE_BASE) | |
6263 | break; | |
6264 | /* pop to reg/mem. */ | |
6265 | if (i.mem_operands) | |
6266 | { | |
6267 | mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; | |
6268 | /* Use dummy register if no base or index. Unlike other opcodes, | |
6269 | ginsns must be generated as this affect stack pointer. */ | |
6270 | dw2_regnum = (mem_reg | |
6271 | ? ginsn_dw2_regnum (mem_reg) | |
6272 | : GINSN_DW2_REGNUM_RSI_DUMMY); | |
6273 | } | |
6274 | else | |
6275 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6276 | ginsn = ginsn_new_load (insn_end_sym, false, | |
6277 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
6278 | GINSN_DST_INDIRECT, dw2_regnum); | |
6279 | ginsn_set_where (ginsn); | |
6280 | /* Check if operation size is 16-bit. */ | |
6281 | if (ginsn_opsize_prefix_p ()) | |
6282 | stack_opnd_size = 2; | |
6283 | ginsn_next = ginsn_new_add (insn_end_sym, false, | |
6284 | GINSN_SRC_REG, REG_SP, 0, | |
6285 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6286 | GINSN_DST_REG, REG_SP, 0); | |
6287 | ginsn_set_where (ginsn_next); | |
6288 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6289 | break; | |
6290 | ||
6291 | case 0x9c: | |
6292 | if (i.tm.opcode_space != SPACE_BASE) | |
6293 | break; | |
6294 | /* pushf / pushfq. */ | |
6295 | /* Check if operation size is 16-bit. */ | |
6296 | if (ginsn_opsize_prefix_p ()) | |
6297 | stack_opnd_size = 2; | |
6298 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6299 | GINSN_SRC_REG, REG_SP, 0, | |
6300 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6301 | GINSN_DST_REG, REG_SP, 0); | |
6302 | ginsn_set_where (ginsn); | |
6303 | /* FIXME - hardcode the actual DWARF reg number value. As for SCFI | |
6304 | correctness, although this behaves simply a placeholder value; its | |
6305 | just clearer if the value is correct. */ | |
6306 | dw2_regnum = GINSN_DW2_REGNUM_EFLAGS; | |
6307 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6308 | GINSN_SRC_REG, dw2_regnum, | |
6309 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6310 | ginsn_set_where (ginsn_next); | |
6311 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6312 | break; | |
6313 | ||
6314 | case 0x9d: | |
6315 | if (i.tm.opcode_space != SPACE_BASE) | |
6316 | break; | |
6317 | /* popf / popfq. */ | |
6318 | /* Check if operation size is 16-bit. */ | |
6319 | if (ginsn_opsize_prefix_p ()) | |
6320 | stack_opnd_size = 2; | |
6321 | /* FIXME - hardcode the actual DWARF reg number value. As for SCFI | |
6322 | correctness, although this behaves simply a placeholder value; its | |
6323 | just clearer if the value is correct. */ | |
6324 | dw2_regnum = GINSN_DW2_REGNUM_EFLAGS; | |
6325 | ginsn = ginsn_new_load (insn_end_sym, false, | |
6326 | GINSN_SRC_INDIRECT, REG_SP, 0, | |
6327 | GINSN_DST_REG, dw2_regnum); | |
6328 | ginsn_set_where (ginsn); | |
6329 | ginsn_next = ginsn_new_add (insn_end_sym, false, | |
6330 | GINSN_SRC_REG, REG_SP, 0, | |
6331 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6332 | GINSN_DST_REG, REG_SP, 0); | |
6333 | ginsn_set_where (ginsn_next); | |
6334 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6335 | break; | |
6336 | ||
6337 | case 0xff: | |
6338 | if (i.tm.opcode_space != SPACE_BASE) | |
6339 | break; | |
6340 | /* push from reg/mem. */ | |
6341 | if (i.tm.extension_opcode == 6) | |
6342 | { | |
6343 | /* Check if operation size is 16-bit. */ | |
6344 | if (ginsn_opsize_prefix_p ()) | |
6345 | stack_opnd_size = 2; | |
6346 | ginsn = ginsn_new_sub (insn_end_sym, false, | |
6347 | GINSN_SRC_REG, REG_SP, 0, | |
6348 | GINSN_SRC_IMM, 0, stack_opnd_size, | |
6349 | GINSN_DST_REG, REG_SP, 0); | |
6350 | ginsn_set_where (ginsn); | |
6351 | if (i.mem_operands) | |
6352 | { | |
6353 | mem_reg = (i.base_reg) ? i.base_reg : i.index_reg; | |
6354 | /* Use dummy register if no base or index. Unlike other opcodes, | |
6355 | ginsns must be generated as this affect stack pointer. */ | |
6356 | dw2_regnum = (mem_reg | |
6357 | ? ginsn_dw2_regnum (mem_reg) | |
6358 | : GINSN_DW2_REGNUM_RSI_DUMMY); | |
6359 | } | |
6360 | else | |
6361 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6362 | ginsn_next = ginsn_new_store (insn_end_sym, false, | |
6363 | GINSN_SRC_INDIRECT, dw2_regnum, | |
6364 | GINSN_DST_INDIRECT, REG_SP, 0); | |
6365 | ginsn_set_where (ginsn_next); | |
6366 | gas_assert (!ginsn_link_next (ginsn, ginsn_next)); | |
6367 | } | |
6368 | else if (i.tm.extension_opcode == 4) | |
6369 | { | |
6370 | /* jmp r/m. E.g., notrack jmp *%rax. */ | |
6371 | if (i.reg_operands) | |
6372 | { | |
6373 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6374 | ginsn = ginsn_new_jump (insn_end_sym, true, | |
6375 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6376 | ginsn_set_where (ginsn); | |
6377 | } | |
6378 | else if (i.mem_operands && i.index_reg) | |
6379 | { | |
6380 | /* jmp *0x0(,%rax,8). */ | |
6381 | dw2_regnum = ginsn_dw2_regnum (i.index_reg); | |
6382 | ginsn = ginsn_new_jump (insn_end_sym, true, | |
6383 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6384 | ginsn_set_where (ginsn); | |
6385 | } | |
6386 | else if (i.mem_operands && i.base_reg) | |
6387 | { | |
6388 | dw2_regnum = ginsn_dw2_regnum (i.base_reg); | |
6389 | ginsn = ginsn_new_jump (insn_end_sym, true, | |
6390 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6391 | ginsn_set_where (ginsn); | |
6392 | } | |
6393 | } | |
6394 | else if (i.tm.extension_opcode == 2) | |
6395 | { | |
6396 | /* 0xFF /2 (call). */ | |
6397 | if (i.reg_operands) | |
6398 | { | |
6399 | dw2_regnum = ginsn_dw2_regnum (i.op[0].regs); | |
6400 | ginsn = ginsn_new_call (insn_end_sym, true, | |
6401 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6402 | ginsn_set_where (ginsn); | |
6403 | } | |
6404 | else if (i.mem_operands && i.base_reg) | |
6405 | { | |
6406 | dw2_regnum = ginsn_dw2_regnum (i.base_reg); | |
6407 | ginsn = ginsn_new_call (insn_end_sym, true, | |
6408 | GINSN_SRC_REG, dw2_regnum, NULL); | |
6409 | ginsn_set_where (ginsn); | |
6410 | } | |
6411 | } | |
6412 | break; | |
6413 | ||
6414 | case 0xc2: /* ret imm16. */ | |
6415 | case 0xc3: /* ret. */ | |
6416 | if (i.tm.opcode_space != SPACE_BASE) | |
6417 | break; | |
6418 | /* Near ret. */ | |
6419 | ginsn = ginsn_new_return (insn_end_sym, true); | |
6420 | ginsn_set_where (ginsn); | |
6421 | break; | |
6422 | ||
6423 | case 0xc8: | |
6424 | if (i.tm.opcode_space != SPACE_BASE) | |
6425 | break; | |
6426 | /* enter. */ | |
6427 | ginsn = x86_ginsn_enter (insn_end_sym); | |
6428 | break; | |
6429 | ||
6430 | case 0xc9: | |
6431 | if (i.tm.opcode_space != SPACE_BASE) | |
6432 | break; | |
6433 | /* leave. */ | |
6434 | ginsn = x86_ginsn_leave (insn_end_sym); | |
6435 | break; | |
6436 | ||
6437 | case 0xe0 ... 0xe2: /* loop / loope / loopne. */ | |
6438 | case 0xe3: /* jecxz / jrcxz. */ | |
6439 | if (i.tm.opcode_space != SPACE_BASE) | |
6440 | break; | |
6441 | ginsn = x86_ginsn_jump (insn_end_sym, true); | |
6442 | ginsn_set_where (ginsn); | |
6443 | break; | |
6444 | ||
6445 | case 0xe8: | |
6446 | if (i.tm.opcode_space != SPACE_BASE) | |
6447 | break; | |
6448 | /* PS: SCFI machinery does not care about which func is being | |
6449 | called. OK to skip that info. */ | |
6450 | ginsn = ginsn_new_call (insn_end_sym, true, | |
6451 | GINSN_SRC_SYMBOL, 0, NULL); | |
6452 | ginsn_set_where (ginsn); | |
6453 | break; | |
6454 | ||
6455 | /* PS: opcode 0xe9 appears only after relaxation. Skip here. */ | |
6456 | case 0xeb: | |
6457 | /* If opcode_space != SPACE_BASE, this is not a jmp insn. Skip it | |
6458 | for GINSN_GEN_SCFI. */ | |
6459 | if (i.tm.opcode_space != SPACE_BASE) | |
6460 | break; | |
6461 | /* Unconditional jmp. */ | |
6462 | ginsn = x86_ginsn_jump (insn_end_sym, false); | |
6463 | ginsn_set_where (ginsn); | |
6464 | break; | |
6465 | ||
6466 | default: | |
6467 | /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for | |
6468 | GINSN_GEN_SCFI mode. */ | |
6469 | break; | |
6470 | } | |
6471 | ||
6472 | if (!ginsn && !x86_ginsn_safe_to_skip_p ()) | |
6473 | { | |
6474 | /* For all unhandled insns that are not whitelisted, check that they do | |
6475 | not impact SCFI correctness. */ | |
6476 | err = x86_ginsn_unhandled (); | |
6477 | switch (err) | |
6478 | { | |
6479 | case X86_GINSN_UNHANDLED_NONE: | |
6480 | break; | |
6481 | case X86_GINSN_UNHANDLED_DEST_REG: | |
6482 | /* Not all writes to REG_FP are harmful in context of SCFI. Simply | |
6483 | generate a GINSN_TYPE_OTHER with destination set to the | |
6484 | appropriate register. The SCFI machinery will bail out if this | |
6485 | ginsn affects SCFI correctness. */ | |
6486 | dw2_regnum = ginsn_dw2_regnum (i.op[i.operands - 1].regs); | |
6487 | ginsn = ginsn_new_other (insn_end_sym, true, | |
6488 | GINSN_SRC_IMM, 0, | |
6489 | GINSN_SRC_IMM, 0, | |
6490 | GINSN_DST_REG, dw2_regnum); | |
6491 | ginsn_set_where (ginsn); | |
6492 | break; | |
6493 | case X86_GINSN_UNHANDLED_CFG: | |
6494 | case X86_GINSN_UNHANDLED_STACKOP: | |
6495 | as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"), opcode); | |
6496 | break; | |
6497 | case X86_GINSN_UNHANDLED_UNEXPECTED: | |
6498 | as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"), | |
6499 | opcode); | |
6500 | break; | |
6501 | default: | |
6502 | abort (); | |
6503 | break; | |
6504 | } | |
6505 | } | |
6506 | ||
6507 | return ginsn; | |
6508 | } | |
6509 | ||
6510 | #endif | |
6511 | ||
252b5132 RH |
6512 | /* This is the guts of the machine-dependent assembler. LINE points to a |
6513 | machine dependent instruction. This function is supposed to emit | |
6514 | the frags/bytes it assembles to. */ | |
6515 | ||
6516 | void | |
65da13b5 | 6517 | md_assemble (char *line) |
252b5132 | 6518 | { |
40fb9820 | 6519 | unsigned int j; |
9db83a32 | 6520 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix = 0, *copy = NULL; |
2d4c39a8 | 6521 | char *xstrdup_copy = NULL; |
04784e33 JB |
6522 | const char *end, *pass1_mnem = NULL; |
6523 | enum i386_error pass1_err = 0; | |
d3ce72d0 | 6524 | const insn_template *t; |
b5482fe5 JB |
6525 | struct last_insn *last_insn |
6526 | = &seg_info(now_seg)->tc_segment_info_data.last_insn; | |
252b5132 | 6527 | |
47926f60 | 6528 | /* Initialize globals. */ |
d3b01414 | 6529 | current_templates.end = current_templates.start = NULL; |
04784e33 | 6530 | retry: |
edd67638 | 6531 | init_globals (); |
252b5132 | 6532 | |
175ce60f JB |
6533 | /* Suppress optimization when the last thing we saw may not have been |
6534 | a proper instruction (e.g. a stand-alone prefix or .byte). */ | |
6535 | if (last_insn->kind != last_insn_other) | |
6536 | i.no_optimize = true; | |
6537 | ||
252b5132 RH |
6538 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
6539 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 6540 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 6541 | |
edd67638 | 6542 | end = parse_insn (line, mnemonic, false); |
5317ad2c | 6543 | if (end == NULL) |
04784e33 JB |
6544 | { |
6545 | if (pass1_mnem != NULL) | |
6546 | goto match_error; | |
9db83a32 JB |
6547 | if (i.error != no_error) |
6548 | { | |
d3b01414 JB |
6549 | gas_assert (current_templates.start != NULL); |
6550 | if (may_need_pass2 (current_templates.start) && !i.suffix) | |
9db83a32 JB |
6551 | goto no_match; |
6552 | /* No point in trying a 2nd pass - it'll only find the same suffix | |
6553 | again. */ | |
6554 | mnem_suffix = i.suffix; | |
6555 | goto match_error; | |
6556 | } | |
04784e33 JB |
6557 | return; |
6558 | } | |
d3b01414 | 6559 | t = current_templates.start; |
2d4c39a8 L |
6560 | /* NB: LINE may be change to be the same as XSTRDUP_COPY. */ |
6561 | if (xstrdup_copy != line && may_need_pass2 (t)) | |
04784e33 JB |
6562 | { |
6563 | /* Make a copy of the full line in case we need to retry. */ | |
2d4c39a8 L |
6564 | xstrdup_copy = xstrdup (line); |
6565 | copy = xstrdup_copy; | |
04784e33 | 6566 | } |
5317ad2c | 6567 | line += end - line; |
83b16ac6 | 6568 | mnem_suffix = i.suffix; |
252b5132 | 6569 | |
29b0f896 | 6570 | line = parse_operands (line, mnemonic); |
ee86248c | 6571 | this_operand = -1; |
29b0f896 | 6572 | if (line == NULL) |
04784e33 | 6573 | { |
2d4c39a8 | 6574 | free (xstrdup_copy); |
04784e33 JB |
6575 | return; |
6576 | } | |
252b5132 | 6577 | |
29b0f896 AM |
6578 | /* Now we've parsed the mnemonic into a set of templates, and have the |
6579 | operands at hand. */ | |
6580 | ||
b630c145 | 6581 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
c0e54661 | 6582 | "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", |
b0e8fa7f TJ |
6583 | "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse |
6584 | intersegment "jmp" and "call" instructions with 2 immediate operands so | |
6585 | that the immediate segment precedes the offset consistently in Intel and | |
6586 | AT&T modes. */ | |
4d456e3d L |
6587 | if (intel_syntax |
6588 | && i.operands > 1 | |
6d86a545 JB |
6589 | && (t->mnem_off != MN_bound) |
6590 | && !startswith (mnemonic, "invlpg") | |
d34049e8 ML |
6591 | && !startswith (mnemonic, "monitor") |
6592 | && !startswith (mnemonic, "mwait") | |
6d86a545 | 6593 | && (t->mnem_off != MN_pvalidate) |
d34049e8 | 6594 | && !startswith (mnemonic, "rmp") |
6d86a545 JB |
6595 | && (t->mnem_off != MN_tpause) |
6596 | && (t->mnem_off != MN_umwait) | |
47c0279b JB |
6597 | && !(i.operands == 2 |
6598 | && operand_type_check (i.types[0], imm) | |
40fb9820 | 6599 | && operand_type_check (i.types[1], imm))) |
29b0f896 AM |
6600 | swap_operands (); |
6601 | ||
e7d74879 JB |
6602 | /* The order of the immediates should be reversed for 2-immediates EXTRQ |
6603 | and INSERTQ instructions. Also UWRMSR wants its immediate to be in the | |
6604 | "canonical" place (first), despite it appearing last (in AT&T syntax, or | |
6605 | because of the swapping above) in the incoming set of operands. */ | |
6606 | if ((i.imm_operands == 2 | |
6607 | && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) | |
6608 | || (t->mnem_off == MN_uwrmsr && i.imm_operands | |
6609 | && i.operands > i.imm_operands)) | |
ec56d5c0 JB |
6610 | swap_2_operands (0, 1); |
6611 | ||
29b0f896 | 6612 | if (i.imm_operands) |
8170af78 HL |
6613 | { |
6614 | /* For USER_MSR instructions, imm32 stands for the name of an model specific | |
6615 | register (MSR). That's an unsigned quantity, whereas all other insns with | |
6616 | 32-bit immediate and 64-bit operand size use sign-extended | |
6617 | immediates (imm32s). Therefore these insns are special-cased, bypassing | |
6618 | the normal handling of immediates here. */ | |
d3b01414 | 6619 | if (is_cpu(current_templates.start, CpuUSER_MSR)) |
8170af78 HL |
6620 | { |
6621 | for (j = 0; j < i.operands; j++) | |
6622 | { | |
6623 | if (operand_type_check(i.types[j], imm)) | |
6624 | i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number); | |
6625 | } | |
6626 | } | |
6627 | else | |
6628 | optimize_imm (); | |
6629 | } | |
29b0f896 | 6630 | |
0de704b9 JB |
6631 | if (i.disp_operands && !optimize_disp (t)) |
6632 | return; | |
29b0f896 AM |
6633 | |
6634 | /* Next, we find a template that matches the given insn, | |
6635 | making sure the overlap of the given operands types is consistent | |
6636 | with the template operand types. */ | |
252b5132 | 6637 | |
83b16ac6 | 6638 | if (!(t = match_template (mnem_suffix))) |
04784e33 JB |
6639 | { |
6640 | const char *err_msg; | |
6641 | ||
6642 | if (copy && !mnem_suffix) | |
6643 | { | |
6644 | line = copy; | |
6645 | copy = NULL; | |
9db83a32 | 6646 | no_match: |
04784e33 | 6647 | pass1_err = i.error; |
d3b01414 | 6648 | pass1_mnem = insn_name (current_templates.start); |
04784e33 JB |
6649 | goto retry; |
6650 | } | |
9db83a32 JB |
6651 | |
6652 | /* If a non-/only-64bit template (group) was found in pass 1, and if | |
6653 | _some_ template (group) was found in pass 2, squash pass 1's | |
6654 | error. */ | |
6655 | if (pass1_err == unsupported_64bit) | |
6656 | pass1_mnem = NULL; | |
6657 | ||
04784e33 | 6658 | match_error: |
2d4c39a8 | 6659 | free (xstrdup_copy); |
9db83a32 | 6660 | |
04784e33 JB |
6661 | switch (pass1_mnem ? pass1_err : i.error) |
6662 | { | |
6663 | default: | |
6664 | abort (); | |
6665 | case operand_size_mismatch: | |
6666 | err_msg = _("operand size mismatch"); | |
6667 | break; | |
6668 | case operand_type_mismatch: | |
6669 | err_msg = _("operand type mismatch"); | |
6670 | break; | |
6671 | case register_type_mismatch: | |
6672 | err_msg = _("register type mismatch"); | |
6673 | break; | |
6674 | case number_of_operands_mismatch: | |
6675 | err_msg = _("number of operands mismatch"); | |
6676 | break; | |
6677 | case invalid_instruction_suffix: | |
6678 | err_msg = _("invalid instruction suffix"); | |
6679 | break; | |
6680 | case bad_imm4: | |
6681 | err_msg = _("constant doesn't fit in 4 bits"); | |
6682 | break; | |
6683 | case unsupported_with_intel_mnemonic: | |
6684 | err_msg = _("unsupported with Intel mnemonic"); | |
6685 | break; | |
6686 | case unsupported_syntax: | |
6687 | err_msg = _("unsupported syntax"); | |
6688 | break; | |
80d61d8d CL |
6689 | case unsupported_EGPR_for_addressing: |
6690 | err_msg = _("extended GPR cannot be used as base/index"); | |
6691 | break; | |
dd74a603 CL |
6692 | case unsupported_nf: |
6693 | err_msg = _("{nf} unsupported"); | |
6694 | break; | |
04784e33 JB |
6695 | case unsupported: |
6696 | as_bad (_("unsupported instruction `%s'"), | |
d3b01414 | 6697 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
04784e33 | 6698 | return; |
9db83a32 JB |
6699 | case unsupported_on_arch: |
6700 | as_bad (_("`%s' is not supported on `%s%s'"), | |
d3b01414 | 6701 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
9db83a32 JB |
6702 | cpu_arch_name ? cpu_arch_name : default_arch, |
6703 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
6704 | return; | |
6705 | case unsupported_64bit: | |
6706 | if (ISLOWER (mnem_suffix)) | |
e8b4b7b2 NC |
6707 | { |
6708 | if (flag_code == CODE_64BIT) | |
6709 | as_bad (_("`%s%c' is not supported in 64-bit mode"), | |
d3b01414 | 6710 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
e8b4b7b2 NC |
6711 | mnem_suffix); |
6712 | else | |
6713 | as_bad (_("`%s%c' is only supported in 64-bit mode"), | |
d3b01414 | 6714 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
e8b4b7b2 NC |
6715 | mnem_suffix); |
6716 | } | |
9db83a32 | 6717 | else |
e8b4b7b2 NC |
6718 | { |
6719 | if (flag_code == CODE_64BIT) | |
6720 | as_bad (_("`%s' is not supported in 64-bit mode"), | |
d3b01414 | 6721 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
e8b4b7b2 NC |
6722 | else |
6723 | as_bad (_("`%s' is only supported in 64-bit mode"), | |
d3b01414 | 6724 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
e8b4b7b2 | 6725 | } |
9db83a32 | 6726 | return; |
54294d73 JB |
6727 | case no_vex_encoding: |
6728 | err_msg = _("no VEX/XOP encoding"); | |
6729 | break; | |
6730 | case no_evex_encoding: | |
6731 | err_msg = _("no EVEX encoding"); | |
6732 | break; | |
04784e33 JB |
6733 | case invalid_sib_address: |
6734 | err_msg = _("invalid SIB address"); | |
6735 | break; | |
6736 | case invalid_vsib_address: | |
6737 | err_msg = _("invalid VSIB address"); | |
6738 | break; | |
6739 | case invalid_vector_register_set: | |
6740 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6741 | break; | |
6742 | case invalid_tmm_register_set: | |
6743 | err_msg = _("all tmm registers must be distinct"); | |
6744 | break; | |
6745 | case invalid_dest_and_src_register_set: | |
6746 | err_msg = _("destination and source registers must be distinct"); | |
6747 | break; | |
08a98d4c MZ |
6748 | case invalid_dest_register_set: |
6749 | err_msg = _("two dest registers must be distinct"); | |
6750 | break; | |
80d61d8d CL |
6751 | case invalid_pseudo_prefix: |
6752 | err_msg = _("rex2 pseudo prefix cannot be used"); | |
6753 | break; | |
04784e33 JB |
6754 | case unsupported_vector_index_register: |
6755 | err_msg = _("unsupported vector index register"); | |
6756 | break; | |
6757 | case unsupported_broadcast: | |
6758 | err_msg = _("unsupported broadcast"); | |
6759 | break; | |
6760 | case broadcast_needed: | |
6761 | err_msg = _("broadcast is needed for operand of such type"); | |
6762 | break; | |
6763 | case unsupported_masking: | |
6764 | err_msg = _("unsupported masking"); | |
6765 | break; | |
6766 | case mask_not_on_destination: | |
6767 | err_msg = _("mask not on destination operand"); | |
6768 | break; | |
6769 | case no_default_mask: | |
6770 | err_msg = _("default mask isn't allowed"); | |
6771 | break; | |
6772 | case unsupported_rc_sae: | |
6773 | err_msg = _("unsupported static rounding/sae"); | |
6774 | break; | |
54294d73 JB |
6775 | case unsupported_vector_size: |
6776 | as_bad (_("vector size above %u required for `%s'"), 128u << vector_size, | |
d3b01414 | 6777 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
54294d73 | 6778 | return; |
08a98d4c MZ |
6779 | case unsupported_rsp_register: |
6780 | err_msg = _("'rsp' register cannot be used"); | |
6781 | break; | |
58bceb18 JB |
6782 | case internal_error: |
6783 | err_msg = _("internal error"); | |
6784 | break; | |
04784e33 JB |
6785 | } |
6786 | as_bad (_("%s for `%s'"), err_msg, | |
d3b01414 | 6787 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
04784e33 JB |
6788 | return; |
6789 | } | |
6790 | ||
2d4c39a8 | 6791 | free (xstrdup_copy); |
252b5132 | 6792 | |
7bab8ab5 | 6793 | if (sse_check != check_none |
ffb86450 JB |
6794 | /* The opcode space check isn't strictly needed; it's there only to |
6795 | bypass the logic below when easily possible. */ | |
ddb62495 JB |
6796 | && t->opcode_space >= SPACE_0F |
6797 | && t->opcode_space <= SPACE_0F3A | |
734dfd1c | 6798 | && !is_cpu (&i.tm, CpuSSE4a) |
ffb86450 | 6799 | && !is_any_vex_encoding (t)) |
daf50ae7 | 6800 | { |
06360a5c JB |
6801 | /* Some KL and all WideKL insns have only implicit %xmm operands. */ |
6802 | bool simd = is_cpu (t, CpuKL) || is_cpu (t, CpuWideKL); | |
ffb86450 JB |
6803 | |
6804 | for (j = 0; j < t->operands; ++j) | |
6805 | { | |
6806 | if (t->operand_types[j].bitfield.class == RegMMX) | |
6807 | break; | |
6808 | if (t->operand_types[j].bitfield.class == RegSIMD) | |
6809 | simd = true; | |
6810 | } | |
6811 | ||
6812 | if (j >= t->operands && simd) | |
6813 | (sse_check == check_warning | |
6814 | ? as_warn | |
76d3f746 | 6815 | : as_bad) (_("SSE instruction `%s' is used"), insn_name (&i.tm)); |
daf50ae7 L |
6816 | } |
6817 | ||
40fb9820 | 6818 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
6819 | if (!add_prefix (FWAIT_OPCODE)) |
6820 | return; | |
252b5132 | 6821 | |
d5de92cf | 6822 | /* Check if REP prefix is OK. */ |
742732c7 | 6823 | if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep) |
d5de92cf L |
6824 | { |
6825 | as_bad (_("invalid instruction `%s' after `%s'"), | |
76d3f746 | 6826 | insn_name (&i.tm), i.rep_prefix); |
d5de92cf L |
6827 | return; |
6828 | } | |
6829 | ||
c1ba0266 L |
6830 | /* Check for lock without a lockable instruction. Destination operand |
6831 | must be memory unless it is xchg (0x86). */ | |
9a4a4499 JB |
6832 | if (i.prefix[LOCK_PREFIX]) |
6833 | { | |
6834 | if (i.tm.opcode_modifier.prefixok < PrefixLock | |
c1ba0266 L |
6835 | || i.mem_operands == 0 |
6836 | || (i.tm.base_opcode != 0x86 | |
9a4a4499 JB |
6837 | && !(i.flags[i.operands - 1] & Operand_Mem))) |
6838 | { | |
6839 | as_bad (_("expecting lockable instruction after `lock'")); | |
6840 | return; | |
6841 | } | |
6842 | ||
6843 | /* Zap the redundant prefix from XCHG when optimizing. */ | |
6844 | if (i.tm.base_opcode == 0x86 && optimize && !i.no_optimize) | |
6845 | i.prefix[LOCK_PREFIX] = 0; | |
c32fa91d L |
6846 | } |
6847 | ||
e3669c7f JB |
6848 | if (is_any_vex_encoding (&i.tm) |
6849 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
6850 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX) | |
7a8655d2 | 6851 | { |
e3669c7f JB |
6852 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
6853 | if (i.prefix[DATA_PREFIX]) | |
6854 | { | |
76d3f746 | 6855 | as_bad (_("data size prefix invalid with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
6856 | return; |
6857 | } | |
6858 | ||
6859 | /* Don't allow e.g. KMOV in TLS code sequences. */ | |
6860 | for (j = i.imm_operands; j < i.operands; ++j) | |
6861 | switch (i.reloc[j]) | |
6862 | { | |
5bc71c2a L |
6863 | case BFD_RELOC_X86_64_GOTTPOFF: |
6864 | if (i.tm.mnem_off == MN_add | |
6865 | && i.tm.opcode_space == SPACE_EVEXMAP4 | |
6866 | && i.mem_operands == 1 | |
6867 | && i.base_reg | |
6868 | && i.base_reg->reg_num == RegIP | |
6869 | && i.tm.operand_types[0].bitfield.class == Reg | |
6870 | && i.tm.operand_types[2].bitfield.class == Reg) | |
6871 | /* Allow APX: add %reg1, foo@gottpoff(%rip), %reg2. */ | |
6872 | break; | |
6873 | /* Fall through. */ | |
e3669c7f JB |
6874 | case BFD_RELOC_386_TLS_GOTIE: |
6875 | case BFD_RELOC_386_TLS_LE_32: | |
e3669c7f | 6876 | case BFD_RELOC_X86_64_TLSLD: |
76d3f746 | 6877 | as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
6878 | return; |
6879 | default: | |
6880 | break; | |
6881 | } | |
7a8655d2 JB |
6882 | } |
6883 | ||
42164a71 | 6884 | /* Check if HLE prefix is OK. */ |
165de32a | 6885 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
6886 | return; |
6887 | ||
7e8b059b L |
6888 | /* Check BND prefix. */ |
6889 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
6890 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
6891 | ||
04ef582a | 6892 | /* Check NOTRACK prefix. */ |
742732c7 | 6893 | if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack) |
9fef80d6 | 6894 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
04ef582a | 6895 | |
734dfd1c | 6896 | if (is_cpu (&i.tm, CpuMPX)) |
327e8c42 JB |
6897 | { |
6898 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
6899 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
6900 | else if (flag_code != CODE_16BIT | |
6901 | ? i.prefix[ADDR_PREFIX] | |
6902 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
6903 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
6904 | } | |
7e8b059b L |
6905 | |
6906 | /* Insert BND prefix. */ | |
76d3a78a JB |
6907 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
6908 | { | |
6909 | if (!i.prefix[BND_PREFIX]) | |
6910 | add_prefix (BND_PREFIX_OPCODE); | |
6911 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
6912 | { | |
6913 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
6914 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
6915 | } | |
6916 | } | |
7e8b059b | 6917 | |
29b0f896 | 6918 | /* Check string instruction segment overrides. */ |
51c8edf6 | 6919 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 6920 | { |
51c8edf6 | 6921 | gas_assert (i.mem_operands); |
29b0f896 | 6922 | if (!check_string ()) |
5dd0794d | 6923 | return; |
fc0763e6 | 6924 | i.disp_operands = 0; |
29b0f896 | 6925 | } |
5dd0794d | 6926 | |
9373f275 L |
6927 | /* The memory operand of (%dx) should be only used with input/output |
6928 | instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */ | |
6929 | if (i.input_output_operand | |
6930 | && ((i.tm.base_opcode | 0x82) != 0xee | |
ddb62495 | 6931 | || i.tm.opcode_space != SPACE_BASE)) |
9373f275 L |
6932 | { |
6933 | as_bad (_("input/output port address isn't allowed with `%s'"), | |
76d3f746 | 6934 | insn_name (&i.tm)); |
9373f275 L |
6935 | return; |
6936 | } | |
6937 | ||
b6f8c7c4 L |
6938 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
6939 | optimize_encoding (); | |
6940 | ||
eb3f3841 JB |
6941 | /* Past optimization there's no need to distinguish encoding_evex, |
6942 | encoding_evex512, and encoding_egpr anymore. */ | |
e346d50a JB |
6943 | if (i.encoding == encoding_evex512) |
6944 | i.encoding = encoding_evex; | |
eb3f3841 JB |
6945 | else if (i.encoding == encoding_egpr) |
6946 | i.encoding = is_any_vex_encoding (&i.tm) ? encoding_evex | |
6947 | : encoding_default; | |
a6f3add0 | 6948 | |
c8480b58 L |
6949 | if (use_unaligned_vector_move) |
6950 | encode_with_unaligned_vector_move (); | |
6951 | ||
acd86c81 | 6952 | if (!process_suffix (t)) |
29b0f896 | 6953 | return; |
e413e4e9 | 6954 | |
ef07be45 | 6955 | /* Check if IP-relative addressing requirements can be satisfied. */ |
734dfd1c | 6956 | if (is_cpu (&i.tm, CpuPREFETCHI) |
ef07be45 | 6957 | && !(i.base_reg && i.base_reg->reg_num == RegIP)) |
76d3f746 | 6958 | as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i.tm)); |
ef07be45 | 6959 | |
921eafea | 6960 | /* Update operand types and check extended states. */ |
bc0844ae | 6961 | for (j = 0; j < i.operands; j++) |
921eafea L |
6962 | { |
6963 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3d70986f | 6964 | switch (i.tm.operand_types[j].bitfield.class) |
921eafea L |
6965 | { |
6966 | default: | |
6967 | break; | |
6968 | case RegMMX: | |
6969 | i.xstate |= xstate_mmx; | |
6970 | break; | |
6971 | case RegMask: | |
32930e4e | 6972 | i.xstate |= xstate_mask; |
921eafea L |
6973 | break; |
6974 | case RegSIMD: | |
3d70986f | 6975 | if (i.tm.operand_types[j].bitfield.tmmword) |
921eafea | 6976 | i.xstate |= xstate_tmm; |
4fc85f37 | 6977 | else if (i.tm.operand_types[j].bitfield.zmmword |
a6f3add0 | 6978 | && !i.tm.opcode_modifier.vex |
4fc85f37 | 6979 | && vector_size >= VSZ512) |
921eafea | 6980 | i.xstate |= xstate_zmm; |
4fc85f37 JB |
6981 | else if (i.tm.operand_types[j].bitfield.ymmword |
6982 | && vector_size >= VSZ256) | |
921eafea | 6983 | i.xstate |= xstate_ymm; |
3d70986f | 6984 | else if (i.tm.operand_types[j].bitfield.xmmword) |
921eafea L |
6985 | i.xstate |= xstate_xmm; |
6986 | break; | |
6987 | } | |
6988 | } | |
bc0844ae | 6989 | |
29b0f896 AM |
6990 | /* Make still unresolved immediate matches conform to size of immediate |
6991 | given in i.suffix. */ | |
6992 | if (!finalize_imm ()) | |
6993 | return; | |
252b5132 | 6994 | |
40fb9820 | 6995 | if (i.types[0].bitfield.imm1) |
29b0f896 | 6996 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 6997 | |
29b0f896 AM |
6998 | /* For insns with operands there are more diddles to do to the opcode. */ |
6999 | if (i.operands) | |
7000 | { | |
7001 | if (!process_operands ()) | |
7002 | return; | |
7003 | } | |
255571cd | 7004 | else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) |
29b0f896 AM |
7005 | { |
7006 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
76d3f746 | 7007 | as_warn (_("translating to `%sp'"), insn_name (&i.tm)); |
29b0f896 | 7008 | } |
252b5132 | 7009 | |
7a8655d2 | 7010 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 7011 | { |
c1dc7af5 | 7012 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 7013 | { |
c1dc7af5 | 7014 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
76d3f746 | 7015 | insn_name (&i.tm)); |
9e5e5283 L |
7016 | return; |
7017 | } | |
c0f3af97 | 7018 | |
0b9404fd JB |
7019 | /* Check for explicit REX prefix. */ |
7020 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
7021 | { | |
76d3f746 | 7022 | as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm)); |
0b9404fd JB |
7023 | return; |
7024 | } | |
7025 | ||
80d61d8d CL |
7026 | /* Check for explicit REX2 prefix. */ |
7027 | if (i.rex2_encoding) | |
7028 | { | |
7029 | as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm)); | |
7030 | return; | |
7031 | } | |
7032 | ||
6177c84d CL |
7033 | if (is_apx_evex_encoding ()) |
7034 | build_apx_evex_prefix (); | |
7035 | else if (i.tm.opcode_modifier.vex) | |
9e5e5283 L |
7036 | build_vex_prefix (t); |
7037 | else | |
7038 | build_evex_prefix (); | |
0b9404fd JB |
7039 | |
7040 | /* The individual REX.RXBW bits got consumed. */ | |
7041 | i.rex &= REX_OPCODE; | |
6177c84d CL |
7042 | |
7043 | /* The rex2 bits got consumed. */ | |
7044 | i.rex2 = 0; | |
9e5e5283 | 7045 | } |
43234a1e | 7046 | |
7fc69528 JB |
7047 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
7048 | if (i.tm.mnem_off == MN_int | |
a6461c02 | 7049 | && i.op[0].imms->X_add_number == 3) |
29b0f896 AM |
7050 | { |
7051 | i.tm.base_opcode = INT3_OPCODE; | |
7052 | i.imm_operands = 0; | |
7053 | } | |
252b5132 | 7054 | |
0cfa3eb3 JB |
7055 | if ((i.tm.opcode_modifier.jump == JUMP |
7056 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
7057 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
7058 | && i.op[0].disps->X_op == O_constant) |
7059 | { | |
7060 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
7061 | the absolute address given by the constant. Since ix86 jumps and | |
7062 | calls are pc relative, we need to generate a reloc. */ | |
7063 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
7064 | i.op[0].disps->X_op = O_symbol; | |
7065 | } | |
252b5132 | 7066 | |
ce705688 | 7067 | establish_rex (); |
29b0f896 | 7068 | |
b5482fe5 | 7069 | insert_lfence_before (last_insn); |
ae531041 | 7070 | |
29b0f896 | 7071 | /* We are ready to output the insn. */ |
b5482fe5 | 7072 | output_insn (last_insn); |
e379e5f3 | 7073 | |
c7defc53 IB |
7074 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
7075 | /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been | |
7076 | performed in i386_target_format. */ | |
7077 | if (IS_ELF && flag_synth_cfi) | |
7078 | { | |
7079 | ginsnS *ginsn; | |
7080 | ginsn = x86_ginsn_new (symbol_temp_new_now (), frch_ginsn_gen_mode ()); | |
7081 | frch_ginsn_data_append (ginsn); | |
7082 | } | |
7083 | #endif | |
7084 | ||
ae531041 L |
7085 | insert_lfence_after (); |
7086 | ||
e379e5f3 L |
7087 | if (i.tm.opcode_modifier.isprefix) |
7088 | { | |
b5482fe5 JB |
7089 | last_insn->kind = last_insn_prefix; |
7090 | last_insn->name = insn_name (&i.tm); | |
7091 | last_insn->file = as_where (&last_insn->line); | |
e379e5f3 L |
7092 | } |
7093 | else | |
b5482fe5 | 7094 | last_insn->kind = last_insn_other; |
29b0f896 AM |
7095 | } |
7096 | ||
9db83a32 JB |
7097 | /* The Q suffix is generally valid only in 64-bit mode, with very few |
7098 | exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild | |
7099 | and fisttp only one of their two templates is matched below: That's | |
7100 | sufficient since other relevant attributes are the same between both | |
7101 | respective templates. */ | |
7102 | static INLINE bool q_suffix_allowed(const insn_template *t) | |
7103 | { | |
7104 | return flag_code == CODE_64BIT | |
ddb62495 | 7105 | || (t->opcode_space == SPACE_BASE |
9db83a32 JB |
7106 | && t->base_opcode == 0xdf |
7107 | && (t->extension_opcode & 1)) /* fild / fistp / fisttp */ | |
7fc69528 | 7108 | || t->mnem_off == MN_cmpxchg8b; |
9db83a32 JB |
7109 | } |
7110 | ||
5317ad2c | 7111 | static const char * |
edd67638 | 7112 | parse_insn (const char *line, char *mnemonic, bool prefix_only) |
29b0f896 | 7113 | { |
5317ad2c | 7114 | const char *l = line, *token_start = l; |
29b0f896 | 7115 | char *mnem_p; |
d3b01414 | 7116 | bool pass1 = !current_templates.start; |
5c6af06e | 7117 | int supported; |
d3ce72d0 | 7118 | const insn_template *t; |
b6169b20 | 7119 | char *dot_p = NULL; |
29b0f896 | 7120 | |
29b0f896 AM |
7121 | while (1) |
7122 | { | |
7123 | mnem_p = mnemonic; | |
778415f5 JB |
7124 | /* Pseudo-prefixes start with an opening figure brace. */ |
7125 | if ((*mnem_p = *l) == '{') | |
7126 | { | |
7127 | ++mnem_p; | |
7128 | ++l; | |
7129 | } | |
29b0f896 AM |
7130 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
7131 | { | |
b6169b20 L |
7132 | if (*mnem_p == '.') |
7133 | dot_p = mnem_p; | |
29b0f896 AM |
7134 | mnem_p++; |
7135 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 7136 | { |
778415f5 | 7137 | too_long: |
29b0f896 AM |
7138 | as_bad (_("no such instruction: `%s'"), token_start); |
7139 | return NULL; | |
7140 | } | |
7141 | l++; | |
7142 | } | |
778415f5 JB |
7143 | /* Pseudo-prefixes end with a closing figure brace. */ |
7144 | if (*mnemonic == '{' && *l == '}') | |
7145 | { | |
7146 | *mnem_p++ = *l++; | |
7147 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
7148 | goto too_long; | |
7149 | *mnem_p = '\0'; | |
7150 | ||
7151 | /* Point l at the closing brace if there's no other separator. */ | |
7152 | if (*l != END_OF_INSN && !is_space_char (*l) | |
7153 | && *l != PREFIX_SEPARATOR) | |
7154 | --l; | |
7155 | } | |
7156 | else if (!is_space_char (*l) | |
7157 | && *l != END_OF_INSN | |
7158 | && (intel_syntax | |
7159 | || (*l != PREFIX_SEPARATOR && *l != ','))) | |
29b0f896 | 7160 | { |
edd67638 JB |
7161 | if (prefix_only) |
7162 | break; | |
29b0f896 AM |
7163 | as_bad (_("invalid character %s in mnemonic"), |
7164 | output_invalid (*l)); | |
7165 | return NULL; | |
7166 | } | |
7167 | if (token_start == l) | |
7168 | { | |
e44823cf | 7169 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
7170 | as_bad (_("expecting prefix; got nothing")); |
7171 | else | |
7172 | as_bad (_("expecting mnemonic; got nothing")); | |
7173 | return NULL; | |
7174 | } | |
45288df1 | 7175 | |
29b0f896 | 7176 | /* Look up instruction (or prefix) via hash table. */ |
d3b01414 | 7177 | op_lookup (mnemonic); |
47926f60 | 7178 | |
29b0f896 AM |
7179 | if (*l != END_OF_INSN |
7180 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
d3b01414 JB |
7181 | && current_templates.start |
7182 | && current_templates.start->opcode_modifier.isprefix) | |
29b0f896 | 7183 | { |
d3b01414 | 7184 | supported = cpu_flags_match (current_templates.start); |
3086ed9a | 7185 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
2dd88dca JB |
7186 | { |
7187 | as_bad ((flag_code != CODE_64BIT | |
7188 | ? _("`%s' is only supported in 64-bit mode") | |
7189 | : _("`%s' is not supported in 64-bit mode")), | |
d3b01414 | 7190 | insn_name (current_templates.start)); |
2dd88dca JB |
7191 | return NULL; |
7192 | } | |
3086ed9a JB |
7193 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
7194 | { | |
7195 | as_bad (_("`%s' is not supported on `%s%s'"), | |
d3b01414 | 7196 | insn_name (current_templates.start), |
3086ed9a JB |
7197 | cpu_arch_name ? cpu_arch_name : default_arch, |
7198 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
7199 | return NULL; | |
7200 | } | |
29b0f896 AM |
7201 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
7202 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
d3b01414 JB |
7203 | if ((current_templates.start->opcode_modifier.size == SIZE16 |
7204 | || current_templates.start->opcode_modifier.size == SIZE32) | |
29b0f896 | 7205 | && flag_code != CODE_64BIT |
d3b01414 | 7206 | && ((current_templates.start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
7207 | ^ (flag_code == CODE_16BIT))) |
7208 | { | |
7209 | as_bad (_("redundant %s prefix"), | |
d3b01414 | 7210 | insn_name (current_templates.start)); |
29b0f896 | 7211 | return NULL; |
45288df1 | 7212 | } |
31184569 | 7213 | |
d3b01414 | 7214 | if (current_templates.start->base_opcode == PSEUDO_PREFIX) |
29b0f896 | 7215 | { |
86fa6981 | 7216 | /* Handle pseudo prefixes. */ |
d3b01414 | 7217 | switch (current_templates.start->extension_opcode) |
86fa6981 | 7218 | { |
41eb8e88 | 7219 | case Prefix_Disp8: |
86fa6981 L |
7220 | /* {disp8} */ |
7221 | i.disp_encoding = disp_encoding_8bit; | |
7222 | break; | |
41eb8e88 L |
7223 | case Prefix_Disp16: |
7224 | /* {disp16} */ | |
7225 | i.disp_encoding = disp_encoding_16bit; | |
7226 | break; | |
7227 | case Prefix_Disp32: | |
86fa6981 L |
7228 | /* {disp32} */ |
7229 | i.disp_encoding = disp_encoding_32bit; | |
7230 | break; | |
41eb8e88 | 7231 | case Prefix_Load: |
86fa6981 L |
7232 | /* {load} */ |
7233 | i.dir_encoding = dir_encoding_load; | |
7234 | break; | |
41eb8e88 | 7235 | case Prefix_Store: |
86fa6981 L |
7236 | /* {store} */ |
7237 | i.dir_encoding = dir_encoding_store; | |
7238 | break; | |
41eb8e88 | 7239 | case Prefix_VEX: |
42e04b36 | 7240 | /* {vex} */ |
e346d50a | 7241 | i.encoding = encoding_vex; |
86fa6981 | 7242 | break; |
41eb8e88 | 7243 | case Prefix_VEX3: |
86fa6981 | 7244 | /* {vex3} */ |
e346d50a | 7245 | i.encoding = encoding_vex3; |
86fa6981 | 7246 | break; |
41eb8e88 | 7247 | case Prefix_EVEX: |
86fa6981 | 7248 | /* {evex} */ |
e346d50a | 7249 | i.encoding = encoding_evex; |
86fa6981 | 7250 | break; |
41eb8e88 | 7251 | case Prefix_REX: |
6b6b6807 | 7252 | /* {rex} */ |
5b7c81bd | 7253 | i.rex_encoding = true; |
6b6b6807 | 7254 | break; |
80d61d8d CL |
7255 | case Prefix_REX2: |
7256 | /* {rex2} */ | |
7257 | i.rex2_encoding = true; | |
7258 | break; | |
dd74a603 CL |
7259 | case Prefix_NF: |
7260 | /* {nf} */ | |
7261 | i.has_nf = true; | |
7262 | if (i.encoding == encoding_default) | |
7263 | i.encoding = encoding_evex; | |
7264 | break; | |
41eb8e88 | 7265 | case Prefix_NoOptimize: |
b6f8c7c4 | 7266 | /* {nooptimize} */ |
5b7c81bd | 7267 | i.no_optimize = true; |
b6f8c7c4 | 7268 | break; |
86fa6981 L |
7269 | default: |
7270 | abort (); | |
7271 | } | |
dd74a603 CL |
7272 | if (i.has_nf && i.encoding != encoding_evex) |
7273 | { | |
7274 | as_bad (_("{nf} cannot be combined with {vex}/{vex3}")); | |
7275 | return NULL; | |
7276 | } | |
86fa6981 L |
7277 | } |
7278 | else | |
7279 | { | |
7280 | /* Add prefix, checking for repeated prefixes. */ | |
d3b01414 | 7281 | switch (add_prefix (current_templates.start->base_opcode)) |
86fa6981 | 7282 | { |
4e9ac44a L |
7283 | case PREFIX_EXIST: |
7284 | return NULL; | |
7285 | case PREFIX_DS: | |
d3b01414 JB |
7286 | if (is_cpu (current_templates.start, CpuIBT)) |
7287 | i.notrack_prefix = insn_name (current_templates.start); | |
4e9ac44a L |
7288 | break; |
7289 | case PREFIX_REP: | |
d3b01414 JB |
7290 | if (is_cpu (current_templates.start, CpuHLE)) |
7291 | i.hle_prefix = insn_name (current_templates.start); | |
7292 | else if (is_cpu (current_templates.start, CpuMPX)) | |
7293 | i.bnd_prefix = insn_name (current_templates.start); | |
4e9ac44a | 7294 | else |
d3b01414 | 7295 | i.rep_prefix = insn_name (current_templates.start); |
4e9ac44a L |
7296 | break; |
7297 | default: | |
7298 | break; | |
86fa6981 | 7299 | } |
29b0f896 AM |
7300 | } |
7301 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
7302 | token_start = ++l; | |
7303 | } | |
7304 | else | |
7305 | break; | |
7306 | } | |
45288df1 | 7307 | |
edd67638 JB |
7308 | if (prefix_only) |
7309 | return token_start; | |
7310 | ||
d3b01414 | 7311 | if (!current_templates.start) |
b6169b20 | 7312 | { |
07d5e953 JB |
7313 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
7314 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 7315 | encoding. */ |
30a55f88 | 7316 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
97f31cb4 JB |
7317 | { |
7318 | if (i.dir_encoding == dir_encoding_default) | |
7319 | i.dir_encoding = dir_encoding_swap; | |
7320 | else | |
7321 | as_warn (_("ignoring `.s' suffix due to earlier `{%s}'"), | |
7322 | i.dir_encoding == dir_encoding_load ? "load" : "store"); | |
7323 | } | |
8d63c93e | 7324 | else if (mnem_p - 3 == dot_p |
a501d77e L |
7325 | && dot_p[1] == 'd' |
7326 | && dot_p[2] == '8') | |
97f31cb4 JB |
7327 | { |
7328 | if (i.disp_encoding == disp_encoding_default) | |
7329 | i.disp_encoding = disp_encoding_8bit; | |
7330 | else if (i.disp_encoding != disp_encoding_8bit) | |
7331 | as_warn (_("ignoring `.d8' suffix due to earlier `{disp<N>}'")); | |
7332 | } | |
8d63c93e | 7333 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
7334 | && dot_p[1] == 'd' |
7335 | && dot_p[2] == '3' | |
7336 | && dot_p[3] == '2') | |
97f31cb4 JB |
7337 | { |
7338 | if (i.disp_encoding == disp_encoding_default) | |
7339 | i.disp_encoding = disp_encoding_32bit; | |
7340 | else if (i.disp_encoding != disp_encoding_32bit) | |
7341 | as_warn (_("ignoring `.d32' suffix due to earlier `{disp<N>}'")); | |
7342 | } | |
30a55f88 L |
7343 | else |
7344 | goto check_suffix; | |
7345 | mnem_p = dot_p; | |
7346 | *dot_p = '\0'; | |
d3b01414 | 7347 | op_lookup (mnemonic); |
b6169b20 L |
7348 | } |
7349 | ||
d3b01414 | 7350 | if (!current_templates.start || !pass1) |
29b0f896 | 7351 | { |
d3b01414 | 7352 | current_templates.start = NULL; |
04784e33 | 7353 | |
dc1e8a47 | 7354 | check_suffix: |
1c529385 | 7355 | if (mnem_p > mnemonic) |
29b0f896 | 7356 | { |
1c529385 LH |
7357 | /* See if we can get a match by trimming off a suffix. */ |
7358 | switch (mnem_p[-1]) | |
29b0f896 | 7359 | { |
1c529385 LH |
7360 | case WORD_MNEM_SUFFIX: |
7361 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
7362 | i.suffix = SHORT_MNEM_SUFFIX; |
7363 | else | |
1c529385 LH |
7364 | /* Fall through. */ |
7365 | case BYTE_MNEM_SUFFIX: | |
7366 | case QWORD_MNEM_SUFFIX: | |
7367 | i.suffix = mnem_p[-1]; | |
29b0f896 | 7368 | mnem_p[-1] = '\0'; |
d3b01414 | 7369 | op_lookup (mnemonic); |
1c529385 LH |
7370 | break; |
7371 | case SHORT_MNEM_SUFFIX: | |
7372 | case LONG_MNEM_SUFFIX: | |
7373 | if (!intel_syntax) | |
7374 | { | |
7375 | i.suffix = mnem_p[-1]; | |
7376 | mnem_p[-1] = '\0'; | |
d3b01414 | 7377 | op_lookup (mnemonic); |
1c529385 LH |
7378 | } |
7379 | break; | |
7380 | ||
7381 | /* Intel Syntax. */ | |
7382 | case 'd': | |
7383 | if (intel_syntax) | |
7384 | { | |
7385 | if (intel_float_operand (mnemonic) == 1) | |
7386 | i.suffix = SHORT_MNEM_SUFFIX; | |
7387 | else | |
7388 | i.suffix = LONG_MNEM_SUFFIX; | |
7389 | mnem_p[-1] = '\0'; | |
d3b01414 | 7390 | op_lookup (mnemonic); |
1c529385 | 7391 | } |
04784e33 JB |
7392 | /* For compatibility reasons accept MOVSD and CMPSD without |
7393 | operands even in AT&T mode. */ | |
7394 | else if (*l == END_OF_INSN | |
7395 | || (is_space_char (*l) && l[1] == END_OF_INSN)) | |
7396 | { | |
7397 | mnem_p[-1] = '\0'; | |
d3b01414 JB |
7398 | op_lookup (mnemonic); |
7399 | if (current_templates.start != NULL | |
04784e33 | 7400 | /* MOVS or CMPS */ |
d3b01414 JB |
7401 | && (current_templates.start->base_opcode | 2) == 0xa6 |
7402 | && current_templates.start->opcode_space | |
04784e33 JB |
7403 | == SPACE_BASE |
7404 | && mnem_p[-2] == 's') | |
7405 | { | |
7406 | as_warn (_("found `%sd'; assuming `%sl' was meant"), | |
7407 | mnemonic, mnemonic); | |
7408 | i.suffix = LONG_MNEM_SUFFIX; | |
7409 | } | |
7410 | else | |
7411 | { | |
d3b01414 | 7412 | current_templates.start = NULL; |
04784e33 JB |
7413 | mnem_p[-1] = 'd'; |
7414 | } | |
7415 | } | |
1c529385 | 7416 | break; |
29b0f896 | 7417 | } |
29b0f896 | 7418 | } |
1c529385 | 7419 | |
d3b01414 | 7420 | if (!current_templates.start) |
29b0f896 | 7421 | { |
04784e33 JB |
7422 | if (pass1) |
7423 | as_bad (_("no such instruction: `%s'"), token_start); | |
29b0f896 AM |
7424 | return NULL; |
7425 | } | |
7426 | } | |
252b5132 | 7427 | |
d3b01414 JB |
7428 | if (current_templates.start->opcode_modifier.jump == JUMP |
7429 | || current_templates.start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
7430 | { |
7431 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
7432 | predict taken and predict not taken respectively. | |
7433 | I'm not sure that branch hints actually do anything on loop | |
7434 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
7435 | may work in the future and it doesn't hurt to accept them | |
7436 | now. */ | |
7437 | if (l[0] == ',' && l[1] == 'p') | |
7438 | { | |
7439 | if (l[2] == 't') | |
7440 | { | |
7441 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
7442 | return NULL; | |
7443 | l += 3; | |
7444 | } | |
7445 | else if (l[2] == 'n') | |
7446 | { | |
7447 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
7448 | return NULL; | |
7449 | l += 3; | |
7450 | } | |
7451 | } | |
7452 | } | |
7453 | /* Any other comma loses. */ | |
7454 | if (*l == ',') | |
7455 | { | |
7456 | as_bad (_("invalid character %s in mnemonic"), | |
7457 | output_invalid (*l)); | |
7458 | return NULL; | |
7459 | } | |
252b5132 | 7460 | |
29b0f896 | 7461 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e | 7462 | supported = 0; |
d3b01414 | 7463 | for (t = current_templates.start; t < current_templates.end; ++t) |
5c6af06e | 7464 | { |
c0f3af97 | 7465 | supported |= cpu_flags_match (t); |
9db83a32 JB |
7466 | |
7467 | if (i.suffix == QWORD_MNEM_SUFFIX && !q_suffix_allowed (t)) | |
7468 | supported &= ~CPU_FLAGS_64BIT_MATCH; | |
7469 | ||
c0f3af97 | 7470 | if (supported == CPU_FLAGS_PERFECT_MATCH) |
d59a54c2 | 7471 | return l; |
29b0f896 | 7472 | } |
3629bb00 | 7473 | |
9db83a32 JB |
7474 | if (pass1) |
7475 | { | |
7476 | if (supported & CPU_FLAGS_64BIT_MATCH) | |
7477 | i.error = unsupported_on_arch; | |
7478 | else | |
7479 | i.error = unsupported_64bit; | |
7480 | } | |
252b5132 | 7481 | |
548d0ee6 | 7482 | return NULL; |
29b0f896 | 7483 | } |
252b5132 | 7484 | |
29b0f896 | 7485 | static char * |
e3bb37b5 | 7486 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
7487 | { |
7488 | char *token_start; | |
3138f287 | 7489 | |
29b0f896 AM |
7490 | /* 1 if operand is pending after ','. */ |
7491 | unsigned int expecting_operand = 0; | |
252b5132 | 7492 | |
29b0f896 AM |
7493 | while (*l != END_OF_INSN) |
7494 | { | |
e68c3d59 JB |
7495 | /* Non-zero if operand parens not balanced. */ |
7496 | unsigned int paren_not_balanced = 0; | |
7497 | /* True if inside double quotes. */ | |
7498 | bool in_quotes = false; | |
7499 | ||
29b0f896 AM |
7500 | /* Skip optional white space before operand. */ |
7501 | if (is_space_char (*l)) | |
7502 | ++l; | |
d02603dc | 7503 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
7504 | { |
7505 | as_bad (_("invalid character %s before operand %d"), | |
7506 | output_invalid (*l), | |
7507 | i.operands + 1); | |
7508 | return NULL; | |
7509 | } | |
d02603dc | 7510 | token_start = l; /* After white space. */ |
e68c3d59 | 7511 | while (in_quotes || paren_not_balanced || *l != ',') |
29b0f896 AM |
7512 | { |
7513 | if (*l == END_OF_INSN) | |
7514 | { | |
e68c3d59 JB |
7515 | if (in_quotes) |
7516 | { | |
7517 | as_bad (_("unbalanced double quotes in operand %d."), | |
7518 | i.operands + 1); | |
7519 | return NULL; | |
7520 | } | |
29b0f896 AM |
7521 | if (paren_not_balanced) |
7522 | { | |
98ff9f1c JB |
7523 | know (!intel_syntax); |
7524 | as_bad (_("unbalanced parenthesis in operand %d."), | |
7525 | i.operands + 1); | |
29b0f896 AM |
7526 | return NULL; |
7527 | } | |
7528 | else | |
7529 | break; /* we are done */ | |
7530 | } | |
e68c3d59 JB |
7531 | else if (*l == '\\' && l[1] == '"') |
7532 | ++l; | |
7533 | else if (*l == '"') | |
7534 | in_quotes = !in_quotes; | |
7535 | else if (!in_quotes && !is_operand_char (*l) && !is_space_char (*l)) | |
29b0f896 AM |
7536 | { |
7537 | as_bad (_("invalid character %s in operand %d"), | |
7538 | output_invalid (*l), | |
7539 | i.operands + 1); | |
7540 | return NULL; | |
7541 | } | |
e68c3d59 | 7542 | if (!intel_syntax && !in_quotes) |
29b0f896 AM |
7543 | { |
7544 | if (*l == '(') | |
7545 | ++paren_not_balanced; | |
7546 | if (*l == ')') | |
7547 | --paren_not_balanced; | |
7548 | } | |
29b0f896 AM |
7549 | l++; |
7550 | } | |
7551 | if (l != token_start) | |
7552 | { /* Yes, we've read in another operand. */ | |
7553 | unsigned int operand_ok; | |
7554 | this_operand = i.operands++; | |
7555 | if (i.operands > MAX_OPERANDS) | |
7556 | { | |
7557 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
7558 | MAX_OPERANDS); | |
7559 | return NULL; | |
7560 | } | |
9d46ce34 | 7561 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
7562 | /* Now parse operand adding info to 'i' as we go along. */ |
7563 | END_STRING_AND_SAVE (l); | |
7564 | ||
1286ab78 L |
7565 | if (i.mem_operands > 1) |
7566 | { | |
7567 | as_bad (_("too many memory references for `%s'"), | |
7568 | mnemonic); | |
7569 | return 0; | |
7570 | } | |
7571 | ||
29b0f896 AM |
7572 | if (intel_syntax) |
7573 | operand_ok = | |
7574 | i386_intel_operand (token_start, | |
7575 | intel_float_operand (mnemonic)); | |
7576 | else | |
a7619375 | 7577 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
7578 | |
7579 | RESTORE_END_STRING (l); | |
7580 | if (!operand_ok) | |
7581 | return NULL; | |
7582 | } | |
7583 | else | |
7584 | { | |
7585 | if (expecting_operand) | |
7586 | { | |
7587 | expecting_operand_after_comma: | |
7588 | as_bad (_("expecting operand after ','; got nothing")); | |
7589 | return NULL; | |
7590 | } | |
7591 | if (*l == ',') | |
7592 | { | |
7593 | as_bad (_("expecting operand before ','; got nothing")); | |
7594 | return NULL; | |
7595 | } | |
7596 | } | |
7f3f1ea2 | 7597 | |
29b0f896 AM |
7598 | /* Now *l must be either ',' or END_OF_INSN. */ |
7599 | if (*l == ',') | |
7600 | { | |
7601 | if (*++l == END_OF_INSN) | |
7602 | { | |
7603 | /* Just skip it, if it's \n complain. */ | |
7604 | goto expecting_operand_after_comma; | |
7605 | } | |
7606 | expecting_operand = 1; | |
7607 | } | |
7608 | } | |
7609 | return l; | |
7610 | } | |
7f3f1ea2 | 7611 | |
050dfa73 | 7612 | static void |
783c187b | 7613 | swap_2_operands (unsigned int xchg1, unsigned int xchg2) |
050dfa73 MM |
7614 | { |
7615 | union i386_op temp_op; | |
40fb9820 | 7616 | i386_operand_type temp_type; |
c48dadc9 | 7617 | unsigned int temp_flags; |
050dfa73 | 7618 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 7619 | |
050dfa73 MM |
7620 | temp_type = i.types[xchg2]; |
7621 | i.types[xchg2] = i.types[xchg1]; | |
7622 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
7623 | |
7624 | temp_flags = i.flags[xchg2]; | |
7625 | i.flags[xchg2] = i.flags[xchg1]; | |
7626 | i.flags[xchg1] = temp_flags; | |
7627 | ||
050dfa73 MM |
7628 | temp_op = i.op[xchg2]; |
7629 | i.op[xchg2] = i.op[xchg1]; | |
7630 | i.op[xchg1] = temp_op; | |
c48dadc9 | 7631 | |
050dfa73 MM |
7632 | temp_reloc = i.reloc[xchg2]; |
7633 | i.reloc[xchg2] = i.reloc[xchg1]; | |
7634 | i.reloc[xchg1] = temp_reloc; | |
43234a1e | 7635 | |
c032bc4f JB |
7636 | temp_flags = i.imm_bits[xchg2]; |
7637 | i.imm_bits[xchg2] = i.imm_bits[xchg1]; | |
7638 | i.imm_bits[xchg1] = temp_flags; | |
7639 | ||
6225c532 | 7640 | if (i.mask.reg) |
43234a1e | 7641 | { |
6225c532 JB |
7642 | if (i.mask.operand == xchg1) |
7643 | i.mask.operand = xchg2; | |
7644 | else if (i.mask.operand == xchg2) | |
7645 | i.mask.operand = xchg1; | |
43234a1e | 7646 | } |
a5748e0d | 7647 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 7648 | { |
5273a3cd JB |
7649 | if (i.broadcast.operand == xchg1) |
7650 | i.broadcast.operand = xchg2; | |
7651 | else if (i.broadcast.operand == xchg2) | |
7652 | i.broadcast.operand = xchg1; | |
43234a1e | 7653 | } |
050dfa73 MM |
7654 | } |
7655 | ||
29b0f896 | 7656 | static void |
e3bb37b5 | 7657 | swap_operands (void) |
29b0f896 | 7658 | { |
b7c61d9a | 7659 | switch (i.operands) |
050dfa73 | 7660 | { |
c0f3af97 | 7661 | case 5: |
b7c61d9a | 7662 | case 4: |
4d456e3d | 7663 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 7664 | /* Fall through. */ |
b7c61d9a L |
7665 | case 3: |
7666 | case 2: | |
4d456e3d | 7667 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
7668 | break; |
7669 | default: | |
7670 | abort (); | |
29b0f896 | 7671 | } |
29b0f896 AM |
7672 | |
7673 | if (i.mem_operands == 2) | |
7674 | { | |
5e042380 | 7675 | const reg_entry *temp_seg; |
29b0f896 AM |
7676 | temp_seg = i.seg[0]; |
7677 | i.seg[0] = i.seg[1]; | |
7678 | i.seg[1] = temp_seg; | |
7679 | } | |
7680 | } | |
252b5132 | 7681 | |
29b0f896 AM |
7682 | /* Try to ensure constant immediates are represented in the smallest |
7683 | opcode possible. */ | |
7684 | static void | |
e3bb37b5 | 7685 | optimize_imm (void) |
29b0f896 AM |
7686 | { |
7687 | char guess_suffix = 0; | |
7688 | int op; | |
252b5132 | 7689 | |
29b0f896 AM |
7690 | if (i.suffix) |
7691 | guess_suffix = i.suffix; | |
7692 | else if (i.reg_operands) | |
7693 | { | |
7694 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
7695 | We can't do this properly yet, i.e. excluding special register |
7696 | instances, but the following works for instructions with | |
7697 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 7698 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
7699 | if (i.types[op].bitfield.class != Reg) |
7700 | continue; | |
7701 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 7702 | { |
40fb9820 L |
7703 | guess_suffix = BYTE_MNEM_SUFFIX; |
7704 | break; | |
7705 | } | |
bab6aec1 | 7706 | else if (i.types[op].bitfield.word) |
252b5132 | 7707 | { |
40fb9820 L |
7708 | guess_suffix = WORD_MNEM_SUFFIX; |
7709 | break; | |
7710 | } | |
bab6aec1 | 7711 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
7712 | { |
7713 | guess_suffix = LONG_MNEM_SUFFIX; | |
7714 | break; | |
7715 | } | |
bab6aec1 | 7716 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
7717 | { |
7718 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 7719 | break; |
252b5132 | 7720 | } |
29b0f896 | 7721 | } |
f79d55e1 JB |
7722 | else if ((flag_code == CODE_16BIT) |
7723 | ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W))) | |
29b0f896 | 7724 | guess_suffix = WORD_MNEM_SUFFIX; |
fb1c1058 JB |
7725 | else if (flag_code != CODE_64BIT |
7726 | || (!(i.prefix[REX_PREFIX] & REX_W) | |
7727 | /* A more generic (but also more involved) way of dealing | |
7728 | with the special case(s) would be to go look for | |
7729 | DefaultSize attributes on any of the templates. */ | |
d3b01414 | 7730 | && current_templates.start->mnem_off != MN_push)) |
5cc00775 | 7731 | guess_suffix = LONG_MNEM_SUFFIX; |
29b0f896 AM |
7732 | |
7733 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 7734 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
7735 | { |
7736 | switch (i.op[op].imms->X_op) | |
252b5132 | 7737 | { |
29b0f896 AM |
7738 | case O_constant: |
7739 | /* If a suffix is given, this operand may be shortened. */ | |
7740 | switch (guess_suffix) | |
252b5132 | 7741 | { |
29b0f896 | 7742 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
7743 | i.types[op].bitfield.imm32 = 1; |
7744 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
7745 | break; |
7746 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
7747 | i.types[op].bitfield.imm16 = 1; |
7748 | i.types[op].bitfield.imm32 = 1; | |
7749 | i.types[op].bitfield.imm32s = 1; | |
7750 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
7751 | break; |
7752 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
7753 | i.types[op].bitfield.imm8 = 1; |
7754 | i.types[op].bitfield.imm8s = 1; | |
7755 | i.types[op].bitfield.imm16 = 1; | |
7756 | i.types[op].bitfield.imm32 = 1; | |
7757 | i.types[op].bitfield.imm32s = 1; | |
7758 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 7759 | break; |
252b5132 | 7760 | } |
252b5132 | 7761 | |
29b0f896 AM |
7762 | /* If this operand is at most 16 bits, convert it |
7763 | to a signed 16 bit number before trying to see | |
7764 | whether it will fit in an even smaller size. | |
7765 | This allows a 16-bit operand such as $0xffe0 to | |
7766 | be recognised as within Imm8S range. */ | |
40fb9820 | 7767 | if ((i.types[op].bitfield.imm16) |
7e96fb68 | 7768 | && fits_in_unsigned_word (i.op[op].imms->X_add_number)) |
252b5132 | 7769 | { |
87ed972d JB |
7770 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
7771 | ^ 0x8000) - 0x8000); | |
29b0f896 | 7772 | } |
a28def75 L |
7773 | #ifdef BFD64 |
7774 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 7775 | if ((i.types[op].bitfield.imm32) |
7e96fb68 | 7776 | && fits_in_unsigned_long (i.op[op].imms->X_add_number)) |
29b0f896 AM |
7777 | { |
7778 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
7779 | ^ ((offsetT) 1 << 31)) | |
7780 | - ((offsetT) 1 << 31)); | |
7781 | } | |
a28def75 | 7782 | #endif |
40fb9820 | 7783 | i.types[op] |
c6fb90c8 L |
7784 | = operand_type_or (i.types[op], |
7785 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 7786 | |
29b0f896 AM |
7787 | /* We must avoid matching of Imm32 templates when 64bit |
7788 | only immediate is available. */ | |
7789 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 7790 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 7791 | break; |
252b5132 | 7792 | |
29b0f896 AM |
7793 | case O_absent: |
7794 | case O_register: | |
7795 | abort (); | |
7796 | ||
7797 | /* Symbols and expressions. */ | |
7798 | default: | |
9cd96992 JB |
7799 | /* Convert symbolic operand to proper sizes for matching, but don't |
7800 | prevent matching a set of insns that only supports sizes other | |
7801 | than those matching the insn suffix. */ | |
7802 | { | |
40fb9820 | 7803 | i386_operand_type mask, allowed; |
d3b01414 | 7804 | const insn_template *t = current_templates.start; |
9cd96992 | 7805 | |
0dfbf9d7 | 7806 | operand_type_set (&mask, 0); |
9cd96992 JB |
7807 | switch (guess_suffix) |
7808 | { | |
7809 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
7810 | mask.bitfield.imm64 = 1; |
7811 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
7812 | break; |
7813 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 7814 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
7815 | break; |
7816 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 7817 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
7818 | break; |
7819 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 7820 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
7821 | break; |
7822 | default: | |
9cd96992 JB |
7823 | break; |
7824 | } | |
8f0212ac JB |
7825 | |
7826 | allowed = operand_type_and (t->operand_types[op], mask); | |
d3b01414 | 7827 | while (++t < current_templates.end) |
8f0212ac JB |
7828 | { |
7829 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
7830 | allowed = operand_type_and (allowed, mask); | |
7831 | } | |
7832 | ||
0dfbf9d7 | 7833 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 7834 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 7835 | } |
29b0f896 | 7836 | break; |
252b5132 | 7837 | } |
29b0f896 AM |
7838 | } |
7839 | } | |
47926f60 | 7840 | |
29b0f896 | 7841 | /* Try to use the smallest displacement type too. */ |
0de704b9 JB |
7842 | static bool |
7843 | optimize_disp (const insn_template *t) | |
29b0f896 | 7844 | { |
0de704b9 | 7845 | unsigned int op; |
3e73aa7c | 7846 | |
0de704b9 JB |
7847 | if (!want_disp32 (t) |
7848 | && (!t->opcode_modifier.jump | |
7849 | || i.jumpabsolute || i.types[0].bitfield.baseindex)) | |
7850 | { | |
7851 | for (op = 0; op < i.operands; ++op) | |
7852 | { | |
7853 | const expressionS *exp = i.op[op].disps; | |
7854 | ||
7855 | if (!operand_type_check (i.types[op], disp)) | |
7856 | continue; | |
7857 | ||
7858 | if (exp->X_op != O_constant) | |
7859 | continue; | |
7860 | ||
7861 | /* Since displacement is signed extended to 64bit, don't allow | |
7862 | disp32 if it is out of range. */ | |
7863 | if (fits_in_signed_long (exp->X_add_number)) | |
7864 | continue; | |
7865 | ||
7866 | i.types[op].bitfield.disp32 = 0; | |
7867 | if (i.types[op].bitfield.baseindex) | |
7868 | { | |
7869 | as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"), | |
7870 | (uint64_t) exp->X_add_number); | |
7871 | return false; | |
7872 | } | |
7873 | } | |
7874 | } | |
7875 | ||
7876 | /* Don't optimize displacement for movabs since it only takes 64bit | |
7877 | displacement. */ | |
7878 | if (i.disp_encoding > disp_encoding_8bit | |
7879 | || (flag_code == CODE_64BIT && t->mnem_off == MN_movabs)) | |
7880 | return true; | |
7881 | ||
7882 | for (op = i.operands; op-- > 0;) | |
40fb9820 | 7883 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 7884 | { |
b300c311 | 7885 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 7886 | { |
91d6fa6a | 7887 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 7888 | |
91d6fa6a | 7889 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 7890 | { |
2f2be86b JB |
7891 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7892 | i.op[op].disps = NULL; | |
b300c311 | 7893 | i.disp_operands--; |
f185acdd JB |
7894 | continue; |
7895 | } | |
7896 | ||
7897 | if (i.types[op].bitfield.disp16 | |
cd613c1f | 7898 | && fits_in_unsigned_word (op_disp)) |
f185acdd JB |
7899 | { |
7900 | /* If this operand is at most 16 bits, convert | |
7901 | to a signed 16 bit number and don't use 64bit | |
7902 | displacement. */ | |
7903 | op_disp = ((op_disp ^ 0x8000) - 0x8000); | |
7904 | i.types[op].bitfield.disp64 = 0; | |
b300c311 | 7905 | } |
f185acdd | 7906 | |
28a167a4 | 7907 | #ifdef BFD64 |
a50187b2 | 7908 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ |
a775efc8 JB |
7909 | if ((flag_code != CODE_64BIT |
7910 | ? i.types[op].bitfield.disp32 | |
0de704b9 JB |
7911 | : want_disp32 (t) |
7912 | && (!t->opcode_modifier.jump | |
a775efc8 | 7913 | || i.jumpabsolute || i.types[op].bitfield.baseindex)) |
a50187b2 | 7914 | && fits_in_unsigned_long (op_disp)) |
b300c311 | 7915 | { |
a50187b2 JB |
7916 | /* If this operand is at most 32 bits, convert |
7917 | to a signed 32 bit number and don't use 64bit | |
7918 | displacement. */ | |
7919 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
7920 | i.types[op].bitfield.disp64 = 0; | |
7921 | i.types[op].bitfield.disp32 = 1; | |
7922 | } | |
28a167a4 | 7923 | |
a50187b2 JB |
7924 | if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp)) |
7925 | { | |
7926 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 7927 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 7928 | } |
28a167a4 | 7929 | #endif |
40fb9820 | 7930 | if ((i.types[op].bitfield.disp32 |
40fb9820 | 7931 | || i.types[op].bitfield.disp16) |
b5014f7a | 7932 | && fits_in_disp8 (op_disp)) |
40fb9820 | 7933 | i.types[op].bitfield.disp8 = 1; |
77c59789 JB |
7934 | |
7935 | i.op[op].disps->X_add_number = op_disp; | |
252b5132 | 7936 | } |
67a4f2b7 AO |
7937 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
7938 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
7939 | { | |
7940 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
7941 | i.op[op].disps, 0, i.reloc[op]); | |
2f2be86b | 7942 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
67a4f2b7 AO |
7943 | } |
7944 | else | |
b300c311 | 7945 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 7946 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 7947 | } |
0de704b9 JB |
7948 | |
7949 | return true; | |
29b0f896 AM |
7950 | } |
7951 | ||
4a1b91ea L |
7952 | /* Return 1 if there is a match in broadcast bytes between operand |
7953 | GIVEN and instruction template T. */ | |
7954 | ||
7955 | static INLINE int | |
7956 | match_broadcast_size (const insn_template *t, unsigned int given) | |
7957 | { | |
7958 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
7959 | && i.types[given].bitfield.byte) | |
7960 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
7961 | && i.types[given].bitfield.word) | |
7962 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
7963 | && i.types[given].bitfield.dword) | |
7964 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
7965 | && i.types[given].bitfield.qword)); | |
7966 | } | |
7967 | ||
6c30d220 L |
7968 | /* Check if operands are valid for the instruction. */ |
7969 | ||
7970 | static int | |
7971 | check_VecOperands (const insn_template *t) | |
7972 | { | |
43234a1e | 7973 | unsigned int op; |
e2195274 | 7974 | i386_cpu_flags cpu; |
e2195274 JB |
7975 | |
7976 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
7977 | any one operand are implicity requiring AVX512VL support if the actual | |
7978 | operand size is YMMword or XMMword. Since this function runs after | |
a61cb9db L |
7979 | template matching, there's no need to check for YMMword/XMMword in |
7980 | the template. */ | |
734dfd1c | 7981 | cpu = cpu_flags_and (cpu_flags_from_attr (t->cpu), avx512); |
e2195274 | 7982 | if (!cpu_flags_all_zero (&cpu) |
734dfd1c | 7983 | && !is_cpu (t, CpuAVX512VL) |
a6f3add0 | 7984 | && !cpu_arch_flags.bitfield.cpuavx512vl |
6177c84d | 7985 | && (!t->opcode_modifier.vex || need_evex_encoding (t))) |
e2195274 JB |
7986 | { |
7987 | for (op = 0; op < t->operands; ++op) | |
7988 | { | |
7989 | if (t->operand_types[op].bitfield.zmmword | |
7990 | && (i.types[op].bitfield.ymmword | |
7991 | || i.types[op].bitfield.xmmword)) | |
7992 | { | |
54294d73 | 7993 | i.error = operand_size_mismatch; |
e2195274 JB |
7994 | return 1; |
7995 | } | |
7996 | } | |
7997 | } | |
43234a1e | 7998 | |
22c36940 JB |
7999 | /* Somewhat similarly, templates specifying both AVX and AVX2 are |
8000 | requiring AVX2 support if the actual operand size is YMMword. */ | |
a5e91879 | 8001 | if (maybe_cpu (t, CpuAVX) && maybe_cpu (t, CpuAVX2) |
22c36940 JB |
8002 | && !cpu_arch_flags.bitfield.cpuavx2) |
8003 | { | |
8004 | for (op = 0; op < t->operands; ++op) | |
8005 | { | |
8006 | if (t->operand_types[op].bitfield.xmmword | |
8007 | && i.types[op].bitfield.ymmword) | |
8008 | { | |
54294d73 | 8009 | i.error = operand_size_mismatch; |
22c36940 JB |
8010 | return 1; |
8011 | } | |
8012 | } | |
8013 | } | |
8014 | ||
6c30d220 | 8015 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 8016 | if (!t->opcode_modifier.sib |
6c30d220 | 8017 | && i.index_reg |
1b54b8d7 JB |
8018 | && (i.index_reg->reg_type.bitfield.xmmword |
8019 | || i.index_reg->reg_type.bitfield.ymmword | |
8020 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
8021 | { |
8022 | i.error = unsupported_vector_index_register; | |
8023 | return 1; | |
8024 | } | |
8025 | ||
ad8ecc81 | 8026 | /* Check if default mask is allowed. */ |
255571cd | 8027 | if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK |
6225c532 | 8028 | && (!i.mask.reg || i.mask.reg->reg_num == 0)) |
ad8ecc81 MZ |
8029 | { |
8030 | i.error = no_default_mask; | |
8031 | return 1; | |
8032 | } | |
8033 | ||
7bab8ab5 JB |
8034 | /* For VSIB byte, we need a vector register for index, and all vector |
8035 | registers must be distinct. */ | |
260cd341 | 8036 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
8037 | { |
8038 | if (!i.index_reg | |
63112cd6 | 8039 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 8040 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 8041 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 8042 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 8043 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 8044 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
8045 | { |
8046 | i.error = invalid_vsib_address; | |
8047 | return 1; | |
8048 | } | |
8049 | ||
6225c532 JB |
8050 | gas_assert (i.reg_operands == 2 || i.mask.reg); |
8051 | if (i.reg_operands == 2 && !i.mask.reg) | |
43234a1e | 8052 | { |
3528c362 | 8053 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
8054 | gas_assert (i.types[0].bitfield.xmmword |
8055 | || i.types[0].bitfield.ymmword); | |
3528c362 | 8056 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
8057 | gas_assert (i.types[2].bitfield.xmmword |
8058 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
8059 | if (operand_check == check_none) |
8060 | return 0; | |
8061 | if (register_number (i.op[0].regs) | |
8062 | != register_number (i.index_reg) | |
8063 | && register_number (i.op[2].regs) | |
8064 | != register_number (i.index_reg) | |
8065 | && register_number (i.op[0].regs) | |
8066 | != register_number (i.op[2].regs)) | |
8067 | return 0; | |
8068 | if (operand_check == check_error) | |
8069 | { | |
8070 | i.error = invalid_vector_register_set; | |
8071 | return 1; | |
8072 | } | |
8073 | as_warn (_("mask, index, and destination registers should be distinct")); | |
8074 | } | |
6225c532 | 8075 | else if (i.reg_operands == 1 && i.mask.reg) |
8444f82a | 8076 | { |
3528c362 | 8077 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
8078 | && (i.types[1].bitfield.xmmword |
8079 | || i.types[1].bitfield.ymmword | |
8080 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
8081 | && (register_number (i.op[1].regs) |
8082 | == register_number (i.index_reg))) | |
8083 | { | |
8084 | if (operand_check == check_error) | |
8085 | { | |
8086 | i.error = invalid_vector_register_set; | |
8087 | return 1; | |
8088 | } | |
8089 | if (operand_check != check_none) | |
8090 | as_warn (_("index and destination registers should be distinct")); | |
8091 | } | |
8092 | } | |
43234a1e | 8093 | } |
7bab8ab5 | 8094 | |
fc141319 L |
8095 | /* For AMX instructions with 3 TMM register operands, all operands |
8096 | must be distinct. */ | |
8097 | if (i.reg_operands == 3 | |
8098 | && t->operand_types[0].bitfield.tmmword | |
8099 | && (i.op[0].regs == i.op[1].regs | |
8100 | || i.op[0].regs == i.op[2].regs | |
8101 | || i.op[1].regs == i.op[2].regs)) | |
8102 | { | |
8103 | i.error = invalid_tmm_register_set; | |
8104 | return 1; | |
260cd341 LC |
8105 | } |
8106 | ||
0cc78721 CL |
8107 | /* For some special instructions require that destination must be distinct |
8108 | from source registers. */ | |
255571cd | 8109 | if (t->opcode_modifier.operandconstraint == DISTINCT_DEST) |
0cc78721 CL |
8110 | { |
8111 | unsigned int dest_reg = i.operands - 1; | |
8112 | ||
8113 | know (i.operands >= 3); | |
8114 | ||
8115 | /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */ | |
8116 | if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs | |
8117 | || (i.reg_operands > 2 | |
8118 | && i.op[dest_reg - 2].regs == i.op[dest_reg].regs)) | |
8119 | { | |
8120 | i.error = invalid_dest_and_src_register_set; | |
8121 | return 1; | |
8122 | } | |
8123 | } | |
8124 | ||
43234a1e L |
8125 | /* Check if broadcast is supported by the instruction and is applied |
8126 | to the memory operand. */ | |
a5748e0d | 8127 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 8128 | { |
8e6e0792 | 8129 | i386_operand_type type, overlap; |
43234a1e L |
8130 | |
8131 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 8132 | and its broadcast bytes match the memory operand. */ |
5273a3cd | 8133 | op = i.broadcast.operand; |
8e6e0792 | 8134 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 8135 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 8136 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 8137 | && !match_broadcast_size (t, op))) |
43234a1e L |
8138 | { |
8139 | bad_broadcast: | |
8140 | i.error = unsupported_broadcast; | |
8141 | return 1; | |
8142 | } | |
8e6e0792 JB |
8143 | |
8144 | operand_type_set (&type, 0); | |
a5748e0d | 8145 | switch (get_broadcast_bytes (t, false)) |
8e6e0792 | 8146 | { |
4a1b91ea L |
8147 | case 2: |
8148 | type.bitfield.word = 1; | |
8149 | break; | |
8150 | case 4: | |
8151 | type.bitfield.dword = 1; | |
8152 | break; | |
8e6e0792 JB |
8153 | case 8: |
8154 | type.bitfield.qword = 1; | |
8155 | break; | |
8156 | case 16: | |
8157 | type.bitfield.xmmword = 1; | |
8158 | break; | |
8159 | case 32: | |
4fc85f37 JB |
8160 | if (vector_size < VSZ256) |
8161 | goto bad_broadcast; | |
8e6e0792 JB |
8162 | type.bitfield.ymmword = 1; |
8163 | break; | |
8164 | case 64: | |
4fc85f37 JB |
8165 | if (vector_size < VSZ512) |
8166 | goto bad_broadcast; | |
8e6e0792 JB |
8167 | type.bitfield.zmmword = 1; |
8168 | break; | |
8169 | default: | |
8170 | goto bad_broadcast; | |
8171 | } | |
8172 | ||
8173 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
8174 | if (t->operand_types[op].bitfield.class == RegSIMD |
8175 | && t->operand_types[op].bitfield.byte | |
8176 | + t->operand_types[op].bitfield.word | |
8177 | + t->operand_types[op].bitfield.dword | |
8178 | + t->operand_types[op].bitfield.qword > 1) | |
8179 | { | |
8180 | overlap.bitfield.xmmword = 0; | |
8181 | overlap.bitfield.ymmword = 0; | |
8182 | overlap.bitfield.zmmword = 0; | |
8183 | } | |
8e6e0792 JB |
8184 | if (operand_type_all_zero (&overlap)) |
8185 | goto bad_broadcast; | |
8186 | ||
9c19e9ec | 8187 | if (t->opcode_modifier.checkoperandsize) |
8e6e0792 JB |
8188 | { |
8189 | unsigned int j; | |
8190 | ||
e2195274 | 8191 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
8192 | for (j = 0; j < i.operands; ++j) |
8193 | { | |
8194 | if (j != op | |
8195 | && !operand_type_register_match(i.types[j], | |
8196 | t->operand_types[j], | |
8197 | type, | |
8198 | t->operand_types[op])) | |
8199 | goto bad_broadcast; | |
8200 | } | |
8201 | } | |
43234a1e L |
8202 | } |
8203 | /* If broadcast is supported in this instruction, we need to check if | |
8204 | operand of one-element size isn't specified without broadcast. */ | |
8205 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
8206 | { | |
8207 | /* Find memory operand. */ | |
8208 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 8209 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
8210 | break; |
8211 | gas_assert (op < i.operands); | |
8212 | /* Check size of the memory operand. */ | |
4a1b91ea | 8213 | if (match_broadcast_size (t, op)) |
43234a1e L |
8214 | { |
8215 | i.error = broadcast_needed; | |
8216 | return 1; | |
8217 | } | |
8218 | } | |
c39e5b26 JB |
8219 | else |
8220 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
8221 | |
8222 | /* Check if requested masking is supported. */ | |
6225c532 | 8223 | if (i.mask.reg) |
43234a1e | 8224 | { |
b1c79256 | 8225 | if (!t->opcode_modifier.masking) |
ae2387fe | 8226 | { |
b1c79256 JB |
8227 | i.error = unsupported_masking; |
8228 | return 1; | |
8229 | } | |
8230 | ||
8231 | /* Common rules for masking: | |
8232 | - mask register destinations permit only zeroing-masking, without | |
8233 | that actually being expressed by a {z} operand suffix or EVEX.z, | |
8234 | - memory destinations allow only merging-masking, | |
8235 | - scatter/gather insns (i.e. ones using vSIB) only allow merging- | |
8236 | masking. */ | |
8237 | if (i.mask.zeroing | |
8238 | && (t->operand_types[t->operands - 1].bitfield.class == RegMask | |
8239 | || (i.flags[t->operands - 1] & Operand_Mem) | |
8240 | || t->opcode_modifier.sib)) | |
8241 | { | |
8242 | i.error = unsupported_masking; | |
8243 | return 1; | |
ae2387fe | 8244 | } |
43234a1e L |
8245 | } |
8246 | ||
8247 | /* Check if masking is applied to dest operand. */ | |
6225c532 | 8248 | if (i.mask.reg && (i.mask.operand != i.operands - 1)) |
43234a1e L |
8249 | { |
8250 | i.error = mask_not_on_destination; | |
8251 | return 1; | |
8252 | } | |
8253 | ||
43234a1e | 8254 | /* Check RC/SAE. */ |
ca5312a2 | 8255 | if (i.rounding.type != rc_none) |
43234a1e | 8256 | { |
a80195f1 | 8257 | if (!t->opcode_modifier.sae |
cf665fee JB |
8258 | || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding) |
8259 | || i.mem_operands) | |
43234a1e L |
8260 | { |
8261 | i.error = unsupported_rc_sae; | |
8262 | return 1; | |
8263 | } | |
cf665fee JB |
8264 | |
8265 | /* Non-EVEX.LIG forms need to have a ZMM register as at least one | |
8266 | operand. */ | |
8267 | if (t->opcode_modifier.evex != EVEXLIG) | |
7bab8ab5 | 8268 | { |
cf665fee JB |
8269 | for (op = 0; op < t->operands; ++op) |
8270 | if (i.types[op].bitfield.zmmword) | |
8271 | break; | |
8272 | if (op >= t->operands) | |
8273 | { | |
8274 | i.error = operand_size_mismatch; | |
8275 | return 1; | |
8276 | } | |
7bab8ab5 | 8277 | } |
6c30d220 L |
8278 | } |
8279 | ||
da4977e0 | 8280 | /* Check the special Imm4 cases; must be the first operand. */ |
eea43579 | 8281 | if ((is_cpu (t, CpuXOP) && t->operands == 5) |
ec6b11e7 JB |
8282 | || (t->opcode_space == SPACE_0F3A |
8283 | && (t->base_opcode | 3) == 0x0b | |
24187fb9 JB |
8284 | && (is_cpu (t, CpuAPX_F) |
8285 | || (t->opcode_modifier.sse2avx && t->opcode_modifier.evex | |
8286 | && (!t->opcode_modifier.vex | |
8287 | || (i.encoding != encoding_default | |
8288 | && i.encoding != encoding_vex | |
8289 | && i.encoding != encoding_vex3)))))) | |
da4977e0 JB |
8290 | { |
8291 | if (i.op[0].imms->X_op != O_constant | |
8292 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
8293 | { | |
8294 | i.error = bad_imm4; | |
8295 | return 1; | |
8296 | } | |
8297 | ||
8298 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
eea43579 JB |
8299 | if (t->operands == 5) |
8300 | operand_type_set (&i.types[0], 0); | |
da4977e0 JB |
8301 | } |
8302 | ||
43234a1e | 8303 | /* Check vector Disp8 operand. */ |
b5014f7a | 8304 | if (t->opcode_modifier.disp8memshift |
a6f3add0 | 8305 | && (!t->opcode_modifier.vex |
6177c84d | 8306 | || need_evex_encoding (t)) |
1a42a9fe | 8307 | && i.disp_encoding <= disp_encoding_8bit) |
43234a1e | 8308 | { |
9b345ce8 | 8309 | if (i.broadcast.type || i.broadcast.bytes) |
4a1b91ea | 8310 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 8311 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 8312 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
8313 | else |
8314 | { | |
125ff819 | 8315 | const i386_operand_type *type = NULL, *fallback = NULL; |
7091c612 JB |
8316 | |
8317 | i.memshift = 0; | |
8318 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 8319 | if (i.flags[op] & Operand_Mem) |
7091c612 | 8320 | { |
4174bfff JB |
8321 | if (t->opcode_modifier.evex == EVEXLIG) |
8322 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
8323 | else if (t->operand_types[op].bitfield.xmmword | |
8324 | + t->operand_types[op].bitfield.ymmword | |
8325 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
8326 | type = &t->operand_types[op]; |
8327 | else if (!i.types[op].bitfield.unspecified) | |
8328 | type = &i.types[op]; | |
125ff819 JB |
8329 | else /* Ambiguities get resolved elsewhere. */ |
8330 | fallback = &t->operand_types[op]; | |
7091c612 | 8331 | } |
3528c362 | 8332 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 8333 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
8334 | { |
8335 | if (i.types[op].bitfield.zmmword) | |
8336 | i.memshift = 6; | |
8337 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
8338 | i.memshift = 5; | |
8339 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
8340 | i.memshift = 4; | |
8341 | } | |
8342 | ||
125ff819 JB |
8343 | if (!type && !i.memshift) |
8344 | type = fallback; | |
7091c612 JB |
8345 | if (type) |
8346 | { | |
8347 | if (type->bitfield.zmmword) | |
8348 | i.memshift = 6; | |
8349 | else if (type->bitfield.ymmword) | |
8350 | i.memshift = 5; | |
8351 | else if (type->bitfield.xmmword) | |
8352 | i.memshift = 4; | |
8353 | } | |
8354 | ||
8355 | /* For the check in fits_in_disp8(). */ | |
8356 | if (i.memshift == 0) | |
8357 | i.memshift = -1; | |
8358 | } | |
43234a1e L |
8359 | |
8360 | for (op = 0; op < i.operands; op++) | |
8361 | if (operand_type_check (i.types[op], disp) | |
8362 | && i.op[op].disps->X_op == O_constant) | |
8363 | { | |
acd86c81 JB |
8364 | /* Make sure to leave i.types[op].bitfield.disp8 alone upon |
8365 | secondary invocations of match_template(). */ | |
b5014f7a | 8366 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 8367 | { |
acd86c81 JB |
8368 | if (!i.tm.mnem_off) |
8369 | i.types[op].bitfield.disp8 = 1; | |
b5014f7a | 8370 | return 0; |
43234a1e | 8371 | } |
acd86c81 JB |
8372 | if (!i.tm.mnem_off) |
8373 | i.types[op].bitfield.disp8 = 0; | |
43234a1e L |
8374 | } |
8375 | } | |
b5014f7a JB |
8376 | |
8377 | i.memshift = 0; | |
43234a1e | 8378 | |
6c30d220 L |
8379 | return 0; |
8380 | } | |
8381 | ||
da4977e0 | 8382 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
8383 | |
8384 | static int | |
da4977e0 | 8385 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 8386 | { |
e346d50a | 8387 | if (i.encoding == encoding_error) |
da4977e0 JB |
8388 | { |
8389 | i.error = unsupported; | |
8390 | return 1; | |
8391 | } | |
8392 | ||
4fc85f37 JB |
8393 | /* Vector size restrictions. */ |
8394 | if ((vector_size < VSZ512 | |
fa88a361 | 8395 | && t->opcode_modifier.evex == EVEX512) |
4fc85f37 JB |
8396 | || (vector_size < VSZ256 |
8397 | && (t->opcode_modifier.evex == EVEX256 | |
fa88a361 | 8398 | || t->opcode_modifier.vex == VEX256))) |
4fc85f37 | 8399 | { |
54294d73 | 8400 | i.error = unsupported_vector_size; |
4fc85f37 JB |
8401 | return 1; |
8402 | } | |
8403 | ||
eb3f3841 | 8404 | switch (i.encoding) |
43234a1e | 8405 | { |
eb3f3841 JB |
8406 | case encoding_default: |
8407 | break; | |
8408 | ||
8409 | case encoding_vex: | |
8410 | case encoding_vex3: | |
8411 | /* This instruction must be encoded with VEX prefix. */ | |
8412 | if (!t->opcode_modifier.vex) | |
8413 | { | |
8414 | i.error = no_vex_encoding; | |
8415 | return 1; | |
8416 | } | |
8417 | break; | |
8418 | ||
8419 | case encoding_evex: | |
8420 | case encoding_evex512: | |
86fa6981 | 8421 | /* This instruction must be encoded with EVEX prefix. */ |
706ce984 | 8422 | if (!t->opcode_modifier.evex) |
86fa6981 | 8423 | { |
54294d73 | 8424 | i.error = no_evex_encoding; |
86fa6981 L |
8425 | return 1; |
8426 | } | |
eb3f3841 | 8427 | break; |
43234a1e | 8428 | |
eb3f3841 JB |
8429 | case encoding_egpr: |
8430 | /* This instruction must be encoded with REX2 or EVEX prefix. */ | |
8431 | if (t->opcode_modifier.vex && !t->opcode_modifier.evex) | |
86fa6981 | 8432 | { |
eb3f3841 | 8433 | i.error = no_evex_encoding; |
86fa6981 L |
8434 | return 1; |
8435 | } | |
eb3f3841 JB |
8436 | break; |
8437 | ||
8438 | default: | |
8439 | abort (); | |
86fa6981 | 8440 | } |
a683cc34 | 8441 | |
a683cc34 SP |
8442 | return 0; |
8443 | } | |
8444 | ||
80d61d8d CL |
8445 | /* Check if Egprs operands are valid for the instruction. */ |
8446 | ||
8447 | static bool | |
8448 | check_EgprOperands (const insn_template *t) | |
8449 | { | |
8450 | if (!t->opcode_modifier.noegpr) | |
192781a3 | 8451 | return false; |
80d61d8d CL |
8452 | |
8453 | for (unsigned int op = 0; op < i.operands; op++) | |
8454 | { | |
8455 | if (i.types[op].bitfield.class != Reg) | |
8456 | continue; | |
8457 | ||
8458 | if (i.op[op].regs->reg_flags & RegRex2) | |
8459 | { | |
8460 | i.error = register_type_mismatch; | |
192781a3 | 8461 | return true; |
80d61d8d CL |
8462 | } |
8463 | } | |
8464 | ||
8465 | if ((i.index_reg && (i.index_reg->reg_flags & RegRex2)) | |
8466 | || (i.base_reg && (i.base_reg->reg_flags & RegRex2))) | |
8467 | { | |
8468 | i.error = unsupported_EGPR_for_addressing; | |
192781a3 | 8469 | return true; |
80d61d8d CL |
8470 | } |
8471 | ||
8472 | /* Check if pseudo prefix {rex2} is valid. */ | |
ebe82bfd | 8473 | if (i.rex2_encoding && !t->opcode_modifier.sse2avx) |
80d61d8d CL |
8474 | { |
8475 | i.error = invalid_pseudo_prefix; | |
192781a3 | 8476 | return true; |
80d61d8d CL |
8477 | } |
8478 | ||
192781a3 | 8479 | return false; |
80d61d8d CL |
8480 | } |
8481 | ||
08a98d4c MZ |
8482 | /* Check if APX operands are valid for the instruction. */ |
8483 | static bool | |
8484 | check_APX_operands (const insn_template *t) | |
8485 | { | |
8486 | /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers. | |
8487 | */ | |
8488 | switch (t->mnem_off) | |
8489 | { | |
8490 | case MN_pop2: | |
8491 | case MN_pop2p: | |
8492 | if (register_number (i.op[0].regs) == register_number (i.op[1].regs)) | |
8493 | { | |
8494 | i.error = invalid_dest_register_set; | |
8495 | return 1; | |
8496 | } | |
8497 | /* fall through */ | |
8498 | case MN_push2: | |
8499 | case MN_push2p: | |
8500 | if (register_number (i.op[0].regs) == 4 | |
8501 | || register_number (i.op[1].regs) == 4) | |
8502 | { | |
8503 | i.error = unsupported_rsp_register; | |
8504 | return 1; | |
8505 | } | |
8506 | break; | |
8507 | } | |
8508 | return 0; | |
8509 | } | |
8510 | ||
6967f19d HL |
8511 | /* Check if the instruction use the REX registers or REX prefix. */ |
8512 | static bool | |
8513 | check_Rex_required (void) | |
8514 | { | |
8515 | for (unsigned int op = 0; op < i.operands; op++) | |
8516 | { | |
8517 | if (i.types[op].bitfield.class != Reg) | |
8518 | continue; | |
8519 | ||
8520 | if (i.op[op].regs->reg_flags & (RegRex | RegRex64)) | |
8521 | return true; | |
8522 | } | |
8523 | ||
8524 | if ((i.index_reg && (i.index_reg->reg_flags & (RegRex | RegRex64))) | |
8525 | || (i.base_reg && (i.base_reg->reg_flags & (RegRex | RegRex64)))) | |
8526 | return true; | |
8527 | ||
8528 | /* Check pseudo prefix {rex} are valid. */ | |
8529 | return i.rex_encoding; | |
8530 | } | |
8531 | ||
8532 | /* Optimize APX NDD insns to legacy insns. */ | |
8533 | static unsigned int | |
8534 | can_convert_NDD_to_legacy (const insn_template *t) | |
8535 | { | |
8536 | unsigned int match_dest_op = ~0; | |
8537 | ||
dd74a603 | 8538 | if (!i.has_nf && i.reg_operands >= 2) |
6967f19d HL |
8539 | { |
8540 | unsigned int dest = i.operands - 1; | |
8541 | unsigned int src1 = i.operands - 2; | |
8542 | unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0; | |
8543 | ||
8544 | if (i.types[src1].bitfield.class == Reg | |
8545 | && i.op[src1].regs == i.op[dest].regs) | |
8546 | match_dest_op = src1; | |
8547 | /* If the first operand is the same as the third operand, | |
8548 | these instructions need to support the ability to commutative | |
8549 | the first two operands and still not change the semantics in order | |
8550 | to be optimized. */ | |
8551 | else if (optimize > 1 | |
8552 | && t->opcode_modifier.commutative | |
8553 | && i.types[src2].bitfield.class == Reg | |
8554 | && i.op[src2].regs == i.op[dest].regs) | |
8555 | match_dest_op = src2; | |
8556 | } | |
8557 | return match_dest_op; | |
8558 | } | |
8559 | ||
7b94647a JB |
8560 | /* Helper function for the progress() macro in match_template(). */ |
8561 | static INLINE enum i386_error progress (enum i386_error new, | |
8562 | enum i386_error last, | |
8563 | unsigned int line, unsigned int *line_p) | |
8564 | { | |
8565 | if (line <= *line_p) | |
8566 | return last; | |
8567 | *line_p = line; | |
8568 | return new; | |
8569 | } | |
8570 | ||
d3ce72d0 | 8571 | static const insn_template * |
83b16ac6 | 8572 | match_template (char mnem_suffix) |
29b0f896 AM |
8573 | { |
8574 | /* Points to template once we've found it. */ | |
d3ce72d0 | 8575 | const insn_template *t; |
40fb9820 | 8576 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 8577 | i386_operand_type overlap4; |
29b0f896 | 8578 | unsigned int found_reverse_match; |
40fb9820 | 8579 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 8580 | int addr_prefix_disp; |
7b94647a JB |
8581 | unsigned int j, size_match, check_register, errline = __LINE__; |
8582 | enum i386_error specific_error = number_of_operands_mismatch; | |
8583 | #define progress(err) progress (err, specific_error, __LINE__, &errline) | |
29b0f896 | 8584 | |
c0f3af97 L |
8585 | #if MAX_OPERANDS != 5 |
8586 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
8587 | #endif |
8588 | ||
29b0f896 | 8589 | found_reverse_match = 0; |
539e75ad | 8590 | addr_prefix_disp = -1; |
40fb9820 | 8591 | |
d3b01414 | 8592 | for (t = current_templates.start; t < current_templates.end; t++) |
29b0f896 | 8593 | { |
539e75ad | 8594 | addr_prefix_disp = -1; |
dbbc8b7e | 8595 | found_reverse_match = 0; |
539e75ad | 8596 | |
7b94647a | 8597 | /* Must have right number of operands. */ |
29b0f896 AM |
8598 | if (i.operands != t->operands) |
8599 | continue; | |
8600 | ||
b58829cd JB |
8601 | /* Skip SSE2AVX templates when inapplicable. */ |
8602 | if (t->opcode_modifier.sse2avx | |
8603 | && (!sse2avx || i.prefix[DATA_PREFIX])) | |
8604 | { | |
8605 | /* Another non-SSE2AVX template has to follow. */ | |
8606 | gas_assert (t + 1 < current_templates.end); | |
8607 | continue; | |
8608 | } | |
8609 | ||
50aecf8c | 8610 | /* Check processor support. */ |
7b94647a | 8611 | specific_error = progress (unsupported); |
45a4bb20 | 8612 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
8613 | continue; |
8614 | ||
e1d4d893 | 8615 | /* Check AT&T mnemonic. */ |
7b94647a | 8616 | specific_error = progress (unsupported_with_intel_mnemonic); |
35266cb1 JB |
8617 | if (!intel_syntax && intel_mnemonic |
8618 | && t->opcode_modifier.dialect == ATT_MNEMONIC) | |
1efbbeb4 L |
8619 | continue; |
8620 | ||
4b5aaf5f | 8621 | /* Check AT&T/Intel syntax. */ |
7b94647a | 8622 | specific_error = progress (unsupported_syntax); |
7d3182d6 | 8623 | if (intel_syntax |
35266cb1 JB |
8624 | ? t->opcode_modifier.dialect >= ATT_SYNTAX |
8625 | : t->opcode_modifier.dialect == INTEL_SYNTAX) | |
1efbbeb4 L |
8626 | continue; |
8627 | ||
dd74a603 CL |
8628 | /* Check NF support. */ |
8629 | specific_error = progress (unsupported_nf); | |
8630 | if (i.has_nf && !t->opcode_modifier.nf) | |
8631 | continue; | |
8632 | ||
4b5aaf5f L |
8633 | /* Check Intel64/AMD64 ISA. */ |
8634 | switch (isa64) | |
8635 | { | |
8636 | default: | |
8637 | /* Default: Don't accept Intel64. */ | |
8638 | if (t->opcode_modifier.isa64 == INTEL64) | |
8639 | continue; | |
8640 | break; | |
8641 | case amd64: | |
8642 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
8643 | if (t->opcode_modifier.isa64 >= INTEL64) | |
8644 | continue; | |
8645 | break; | |
8646 | case intel64: | |
8647 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 8648 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
8649 | continue; |
8650 | break; | |
8651 | } | |
8652 | ||
dc2be329 | 8653 | /* Check the suffix. */ |
7b94647a | 8654 | specific_error = progress (invalid_instruction_suffix); |
7505bb03 JB |
8655 | if ((t->opcode_modifier.no_bsuf && mnem_suffix == BYTE_MNEM_SUFFIX) |
8656 | || (t->opcode_modifier.no_wsuf && mnem_suffix == WORD_MNEM_SUFFIX) | |
8657 | || (t->opcode_modifier.no_lsuf && mnem_suffix == LONG_MNEM_SUFFIX) | |
8658 | || (t->opcode_modifier.no_ssuf && mnem_suffix == SHORT_MNEM_SUFFIX) | |
8659 | || (t->opcode_modifier.no_qsuf && mnem_suffix == QWORD_MNEM_SUFFIX)) | |
83b16ac6 | 8660 | continue; |
29b0f896 | 8661 | |
7b94647a | 8662 | specific_error = progress (operand_size_mismatch); |
3ac21baa JB |
8663 | size_match = operand_size_match (t); |
8664 | if (!size_match) | |
7d5e4556 | 8665 | continue; |
539e75ad | 8666 | |
6f2f06be JB |
8667 | /* This is intentionally not |
8668 | ||
0cfa3eb3 | 8669 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
8670 | |
8671 | as the case of a missing * on the operand is accepted (perhaps with | |
8672 | a warning, issued further down). */ | |
7b94647a | 8673 | specific_error = progress (operand_type_mismatch); |
0cfa3eb3 | 8674 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
7b94647a | 8675 | continue; |
6f2f06be | 8676 | |
a4d3acd2 JB |
8677 | /* In Intel syntax, normally we can check for memory operand size when |
8678 | there is no mnemonic suffix. But jmp and call have 2 different | |
8679 | encodings with Dword memory operand size. Skip the "near" one | |
8680 | (permitting a register operand) when "far" was requested. */ | |
8681 | if (i.far_branch | |
8682 | && t->opcode_modifier.jump == JUMP_ABSOLUTE | |
8683 | && t->operand_types[0].bitfield.class == Reg) | |
8684 | continue; | |
8685 | ||
5c07affc L |
8686 | for (j = 0; j < MAX_OPERANDS; j++) |
8687 | operand_types[j] = t->operand_types[j]; | |
8688 | ||
9db83a32 | 8689 | /* In general, don't allow 32-bit operands on pre-386. */ |
7b94647a JB |
8690 | specific_error = progress (mnem_suffix ? invalid_instruction_suffix |
8691 | : operand_size_mismatch); | |
4873e243 | 8692 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
9db83a32 JB |
8693 | if (i.suffix == LONG_MNEM_SUFFIX |
8694 | && !cpu_arch_flags.bitfield.cpui386 | |
45aa61fe | 8695 | && (intel_syntax |
3cd7f3e3 | 8696 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
76d3f746 JB |
8697 | && !intel_float_operand (insn_name (t))) |
8698 | : intel_float_operand (insn_name (t)) != 2) | |
4873e243 JB |
8699 | && (t->operands == i.imm_operands |
8700 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
8701 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
8702 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
8703 | || (operand_types[j].bitfield.class != RegMMX | |
8704 | && operand_types[j].bitfield.class != RegSIMD | |
8705 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 8706 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
8707 | continue; |
8708 | ||
29b0f896 | 8709 | /* Do not verify operands when there are none. */ |
e365e234 | 8710 | if (!t->operands) |
da4977e0 JB |
8711 | { |
8712 | if (VEX_check_encoding (t)) | |
8713 | { | |
7b94647a | 8714 | specific_error = progress (i.error); |
da4977e0 JB |
8715 | continue; |
8716 | } | |
8717 | ||
80d61d8d CL |
8718 | /* Check if pseudo prefix {rex2} is valid. */ |
8719 | if (t->opcode_modifier.noegpr && i.rex2_encoding) | |
8720 | { | |
8721 | specific_error = progress (invalid_pseudo_prefix); | |
8722 | continue; | |
8723 | } | |
8724 | ||
da4977e0 JB |
8725 | /* We've found a match; break out of loop. */ |
8726 | break; | |
8727 | } | |
252b5132 | 8728 | |
48bcea9f JB |
8729 | if (!t->opcode_modifier.jump |
8730 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
8731 | { | |
8732 | /* There should be only one Disp operand. */ | |
8733 | for (j = 0; j < MAX_OPERANDS; j++) | |
8734 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 8735 | break; |
48bcea9f JB |
8736 | if (j < MAX_OPERANDS) |
8737 | { | |
5b7c81bd | 8738 | bool override = (i.prefix[ADDR_PREFIX] != 0); |
48bcea9f JB |
8739 | |
8740 | addr_prefix_disp = j; | |
8741 | ||
a775efc8 JB |
8742 | /* Address size prefix will turn Disp64 operand into Disp32 and |
8743 | Disp32/Disp16 one into Disp16/Disp32 respectively. */ | |
48bcea9f | 8744 | switch (flag_code) |
40fb9820 | 8745 | { |
48bcea9f JB |
8746 | case CODE_16BIT: |
8747 | override = !override; | |
8748 | /* Fall through. */ | |
8749 | case CODE_32BIT: | |
8750 | if (operand_types[j].bitfield.disp32 | |
8751 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 8752 | { |
48bcea9f JB |
8753 | operand_types[j].bitfield.disp16 = override; |
8754 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 8755 | } |
a775efc8 | 8756 | gas_assert (!operand_types[j].bitfield.disp64); |
48bcea9f JB |
8757 | break; |
8758 | ||
8759 | case CODE_64BIT: | |
a775efc8 | 8760 | if (operand_types[j].bitfield.disp64) |
40fb9820 | 8761 | { |
a775efc8 | 8762 | gas_assert (!operand_types[j].bitfield.disp32); |
48bcea9f | 8763 | operand_types[j].bitfield.disp32 = override; |
a775efc8 | 8764 | operand_types[j].bitfield.disp64 = !override; |
40fb9820 | 8765 | } |
48bcea9f JB |
8766 | operand_types[j].bitfield.disp16 = 0; |
8767 | break; | |
40fb9820 | 8768 | } |
539e75ad | 8769 | } |
48bcea9f | 8770 | } |
539e75ad | 8771 | |
56ffb741 | 8772 | /* We check register size if needed. */ |
9c19e9ec | 8773 | if (t->opcode_modifier.checkoperandsize) |
e2195274 JB |
8774 | { |
8775 | check_register = (1 << t->operands) - 1; | |
a5748e0d | 8776 | if (i.broadcast.type || i.broadcast.bytes) |
5273a3cd | 8777 | check_register &= ~(1 << i.broadcast.operand); |
e2195274 JB |
8778 | } |
8779 | else | |
8780 | check_register = 0; | |
8781 | ||
c6fb90c8 | 8782 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
8783 | switch (t->operands) |
8784 | { | |
8785 | case 1: | |
40fb9820 | 8786 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 | 8787 | continue; |
ae9a0a51 JB |
8788 | |
8789 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
8790 | {store} pseudo prefix on an applicable insn. */ | |
8791 | if (!t->opcode_modifier.modrm | |
8792 | && i.reg_operands == 1 | |
8793 | && ((i.dir_encoding == dir_encoding_load | |
8794 | && t->mnem_off != MN_pop) | |
8795 | || (i.dir_encoding == dir_encoding_store | |
8796 | && t->mnem_off != MN_push)) | |
8797 | /* Avoid BSWAP. */ | |
8798 | && t->mnem_off != MN_bswap) | |
8799 | continue; | |
29b0f896 | 8800 | break; |
ae9a0a51 | 8801 | |
29b0f896 | 8802 | case 2: |
33eaf5de | 8803 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
8804 | only in 32bit mode and we can use opcode 0x90. In 64bit |
8805 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
8806 | zero-extend %eax to %rax. */ | |
ae9a0a51 JB |
8807 | if (t->base_opcode == 0x90 |
8808 | && t->opcode_space == SPACE_BASE) | |
8809 | { | |
8810 | if (flag_code == CODE_64BIT | |
8811 | && i.types[0].bitfield.instance == Accum | |
8812 | && i.types[0].bitfield.dword | |
8813 | && i.types[1].bitfield.instance == Accum) | |
8814 | continue; | |
8815 | ||
8816 | /* Allow the ModR/M encoding to be requested by using the | |
8817 | {load} or {store} pseudo prefix. */ | |
8818 | if (i.dir_encoding == dir_encoding_load | |
8819 | || i.dir_encoding == dir_encoding_store) | |
8820 | continue; | |
8821 | } | |
e3669c7f JB |
8822 | |
8823 | if (t->base_opcode == MOV_AX_DISP32 | |
ddb62495 | 8824 | && t->opcode_space == SPACE_BASE |
69196391 | 8825 | && t->mnem_off != MN_movabs) |
e3669c7f JB |
8826 | { |
8827 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ | |
8828 | if (i.reloc[0] == BFD_RELOC_386_GOT32) | |
8829 | continue; | |
8830 | ||
8831 | /* xrelease mov %eax, <disp> is another special case. It must not | |
8832 | match the accumulator-only encoding of mov. */ | |
8833 | if (i.hle_prefix) | |
8834 | continue; | |
ae9a0a51 JB |
8835 | |
8836 | /* Allow the ModR/M encoding to be requested by using a suitable | |
8837 | {load} or {store} pseudo prefix. */ | |
8838 | if (i.dir_encoding == (i.types[0].bitfield.instance == Accum | |
8839 | ? dir_encoding_store | |
8840 | : dir_encoding_load) | |
8841 | && !i.types[0].bitfield.disp64 | |
8842 | && !i.types[1].bitfield.disp64) | |
8843 | continue; | |
8844 | } | |
8845 | ||
8846 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
8847 | {store} pseudo prefix on an applicable insn. */ | |
8848 | if (!t->opcode_modifier.modrm | |
8849 | && i.reg_operands == 1 | |
8850 | && i.imm_operands == 1 | |
8851 | && (i.dir_encoding == dir_encoding_load | |
8852 | || i.dir_encoding == dir_encoding_store) | |
8853 | && t->opcode_space == SPACE_BASE) | |
8854 | { | |
8855 | if (t->base_opcode == 0xb0 /* mov $imm, %reg */ | |
8856 | && i.dir_encoding == dir_encoding_store) | |
8857 | continue; | |
8858 | ||
8859 | if ((t->base_opcode | 0x38) == 0x3c /* <alu> $imm, %acc */ | |
8860 | && (t->base_opcode != 0x3c /* cmp $imm, %acc */ | |
8861 | || i.dir_encoding == dir_encoding_load)) | |
8862 | continue; | |
8863 | ||
8864 | if (t->base_opcode == 0xa8 /* test $imm, %acc */ | |
8865 | && i.dir_encoding == dir_encoding_load) | |
8866 | continue; | |
e3669c7f | 8867 | } |
f5eb1d70 JB |
8868 | /* Fall through. */ |
8869 | ||
8870 | case 3: | |
3ac21baa JB |
8871 | if (!(size_match & MATCH_STRAIGHT)) |
8872 | goto check_reverse; | |
64c49ab3 JB |
8873 | /* Reverse direction of operands if swapping is possible in the first |
8874 | place (operands need to be symmetric) and | |
8875 | - the load form is requested, and the template is a store form, | |
8876 | - the store form is requested, and the template is a load form, | |
8877 | - the non-default (swapped) form is requested. */ | |
8878 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
3083f376 | 8879 | |
8880 | j = i.operands - 1 - (t->opcode_space == SPACE_EVEXMAP4 | |
8881 | && t->opcode_modifier.vexvvvv); | |
8882 | ||
f5eb1d70 | 8883 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
8884 | && !operand_type_all_zero (&overlap1)) |
8885 | switch (i.dir_encoding) | |
8886 | { | |
8887 | case dir_encoding_load: | |
3083f376 | 8888 | if (operand_type_check (operand_types[j], anymem) |
dfd69174 | 8889 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
8890 | goto check_reverse; |
8891 | break; | |
8892 | ||
8893 | case dir_encoding_store: | |
3083f376 | 8894 | if (!operand_type_check (operand_types[j], anymem) |
dfd69174 | 8895 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
8896 | goto check_reverse; |
8897 | break; | |
8898 | ||
8899 | case dir_encoding_swap: | |
8900 | goto check_reverse; | |
8901 | ||
8902 | case dir_encoding_default: | |
8903 | break; | |
8904 | } | |
3083f376 | 8905 | |
86fa6981 | 8906 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
8907 | if ((i.dir_encoding == dir_encoding_store |
8908 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
8909 | && i.mem_operands == 0 |
8910 | && t->opcode_modifier.load) | |
fa99fab2 | 8911 | continue; |
1a0670f3 | 8912 | /* Fall through. */ |
f48ff2ae | 8913 | case 4: |
c0f3af97 | 8914 | case 5: |
c6fb90c8 | 8915 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
8916 | if (!operand_type_match (overlap0, i.types[0]) |
8917 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 8918 | || ((check_register & 3) == 3 |
dc821c5f | 8919 | && !operand_type_register_match (i.types[0], |
40fb9820 | 8920 | operand_types[0], |
dc821c5f | 8921 | i.types[1], |
40fb9820 | 8922 | operand_types[1]))) |
29b0f896 | 8923 | { |
7b94647a JB |
8924 | specific_error = progress (i.error); |
8925 | ||
29b0f896 | 8926 | /* Check if other direction is valid ... */ |
38e314eb | 8927 | if (!t->opcode_modifier.d) |
29b0f896 AM |
8928 | continue; |
8929 | ||
dc1e8a47 | 8930 | check_reverse: |
3ac21baa JB |
8931 | if (!(size_match & MATCH_REVERSE)) |
8932 | continue; | |
29b0f896 | 8933 | /* Try reversing direction of operands. */ |
734dfd1c | 8934 | j = is_cpu (t, CpuFMA4) |
3083f376 | 8935 | || is_cpu (t, CpuXOP) |
8936 | || is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1; | |
8bd915b7 JB |
8937 | overlap0 = operand_type_and (i.types[0], operand_types[j]); |
8938 | overlap1 = operand_type_and (i.types[j], operand_types[0]); | |
c975cec5 | 8939 | overlap2 = operand_type_and (i.types[1], operand_types[1]); |
3083f376 | 8940 | gas_assert (t->operands != 3 || !check_register |
8941 | || is_cpu (t, CpuAPX_F)); | |
40fb9820 | 8942 | if (!operand_type_match (overlap0, i.types[0]) |
8bd915b7 | 8943 | || !operand_type_match (overlap1, i.types[j]) |
c975cec5 JB |
8944 | || (t->operands == 3 |
8945 | && !operand_type_match (overlap2, i.types[1])) | |
45664ddb | 8946 | || (check_register |
dc821c5f | 8947 | && !operand_type_register_match (i.types[0], |
8bd915b7 JB |
8948 | operand_types[j], |
8949 | i.types[j], | |
45664ddb | 8950 | operand_types[0]))) |
29b0f896 AM |
8951 | { |
8952 | /* Does not match either direction. */ | |
7b94647a | 8953 | specific_error = progress (i.error); |
29b0f896 AM |
8954 | continue; |
8955 | } | |
ac9226cf | 8956 | /* found_reverse_match holds which variant of D |
29b0f896 | 8957 | we've found. */ |
38e314eb JB |
8958 | if (!t->opcode_modifier.d) |
8959 | found_reverse_match = 0; | |
8960 | else if (operand_types[0].bitfield.tbyte) | |
ac9226cf | 8961 | { |
4943d587 JB |
8962 | if (t->opcode_modifier.operandconstraint != UGH) |
8963 | found_reverse_match = Opcode_FloatD; | |
bd782808 JB |
8964 | else |
8965 | found_reverse_match = ~0; | |
ac9226cf | 8966 | /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */ |
bd782808 | 8967 | if ((t->extension_opcode & 4) |
ac9226cf JB |
8968 | && (intel_syntax || intel_mnemonic)) |
8969 | found_reverse_match |= Opcode_FloatR; | |
8970 | } | |
734dfd1c | 8971 | else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)) |
8bd915b7 JB |
8972 | { |
8973 | found_reverse_match = Opcode_VexW; | |
8974 | goto check_operands_345; | |
8975 | } | |
dd74a603 CL |
8976 | else if (t->opcode_space == SPACE_EVEXMAP4 |
8977 | && t->opcode_modifier.w) | |
3083f376 | 8978 | { |
8979 | found_reverse_match = Opcode_D; | |
8980 | goto check_operands_345; | |
8981 | } | |
ddb62495 JB |
8982 | else if (t->opcode_space != SPACE_BASE |
8983 | && (t->opcode_space != SPACE_0F | |
2c735193 JB |
8984 | /* MOV to/from CR/DR/TR, as an exception, follow |
8985 | the base opcode space encoding model. */ | |
8986 | || (t->base_opcode | 7) != 0x27)) | |
dbbc8b7e | 8987 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e |
2c735193 | 8988 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
a33ef3c2 | 8989 | else if (!t->opcode_modifier.commutative) |
38e314eb | 8990 | found_reverse_match = Opcode_D; |
a33ef3c2 JB |
8991 | else |
8992 | found_reverse_match = ~0; | |
29b0f896 | 8993 | } |
f48ff2ae | 8994 | else |
29b0f896 | 8995 | { |
f48ff2ae | 8996 | /* Found a forward 2 operand match here. */ |
8bd915b7 | 8997 | check_operands_345: |
d1cbb4db L |
8998 | switch (t->operands) |
8999 | { | |
c0f3af97 | 9000 | case 5: |
3d0738af | 9001 | overlap4 = operand_type_and (i.types[4], operand_types[4]); |
c0f3af97 | 9002 | if (!operand_type_match (overlap4, i.types[4]) |
dc821c5f | 9003 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 9004 | operand_types[3], |
c0f3af97 L |
9005 | i.types[4], |
9006 | operand_types[4])) | |
7b94647a JB |
9007 | { |
9008 | specific_error = progress (i.error); | |
9009 | continue; | |
9010 | } | |
1a0670f3 | 9011 | /* Fall through. */ |
f48ff2ae | 9012 | case 4: |
3d0738af | 9013 | overlap3 = operand_type_and (i.types[3], operand_types[3]); |
40fb9820 | 9014 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
9015 | || ((check_register & 0xa) == 0xa |
9016 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
9017 | operand_types[1], |
9018 | i.types[3], | |
e2195274 JB |
9019 | operand_types[3])) |
9020 | || ((check_register & 0xc) == 0xc | |
9021 | && !operand_type_register_match (i.types[2], | |
9022 | operand_types[2], | |
9023 | i.types[3], | |
9024 | operand_types[3]))) | |
7b94647a JB |
9025 | { |
9026 | specific_error = progress (i.error); | |
9027 | continue; | |
9028 | } | |
1a0670f3 | 9029 | /* Fall through. */ |
f48ff2ae | 9030 | case 3: |
3d0738af | 9031 | overlap2 = operand_type_and (i.types[2], operand_types[2]); |
40fb9820 | 9032 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
9033 | || ((check_register & 5) == 5 |
9034 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
9035 | operand_types[0], |
9036 | i.types[2], | |
e2195274 JB |
9037 | operand_types[2])) |
9038 | || ((check_register & 6) == 6 | |
9039 | && !operand_type_register_match (i.types[1], | |
9040 | operand_types[1], | |
9041 | i.types[2], | |
9042 | operand_types[2]))) | |
7b94647a JB |
9043 | { |
9044 | specific_error = progress (i.error); | |
9045 | continue; | |
9046 | } | |
f48ff2ae L |
9047 | break; |
9048 | } | |
29b0f896 | 9049 | } |
f48ff2ae | 9050 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
9051 | slip through to break. */ |
9052 | } | |
c0f3af97 | 9053 | |
9bb4d860 L |
9054 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ |
9055 | if (VEX_check_encoding (t)) | |
da4977e0 | 9056 | { |
7b94647a | 9057 | specific_error = progress (i.error); |
da4977e0 JB |
9058 | continue; |
9059 | } | |
9060 | ||
80d61d8d CL |
9061 | /* Check if EGPR operands(r16-r31) are valid. */ |
9062 | if (check_EgprOperands (t)) | |
9063 | { | |
9064 | specific_error = progress (i.error); | |
9065 | continue; | |
9066 | } | |
9067 | ||
9bb4d860 L |
9068 | /* Check if vector operands are valid. */ |
9069 | if (check_VecOperands (t)) | |
5614d22c | 9070 | { |
7b94647a | 9071 | specific_error = progress (i.error); |
5614d22c JB |
9072 | continue; |
9073 | } | |
a683cc34 | 9074 | |
08a98d4c MZ |
9075 | /* Check if APX operands are valid. */ |
9076 | if (check_APX_operands (t)) | |
9077 | { | |
9078 | specific_error = progress (i.error); | |
9079 | continue; | |
9080 | } | |
9081 | ||
58bceb18 | 9082 | /* Check whether to use the shorter VEX encoding for certain insns where |
39bb3ade JB |
9083 | the EVEX encoding comes first in the table. This requires the respective |
9084 | AVX-* feature to be explicitly enabled. | |
9085 | ||
9086 | Most of the respective insns have just a single EVEX and a single VEX | |
9087 | template. The one that's presently different is generated using the | |
9088 | Vxy / Exy constructs: There are 3 suffix-less EVEX forms, the latter | |
9089 | two of which may fall back to their two corresponding VEX forms. */ | |
9090 | j = t->mnem_off != MN_vcvtneps2bf16 ? 1 : 2; | |
d3b01414 | 9091 | if ((t == current_templates.start || j > 1) |
58bceb18 JB |
9092 | && t->opcode_modifier.disp8memshift |
9093 | && !t->opcode_modifier.vex | |
6177c84d | 9094 | && !need_evex_encoding (t) |
d3b01414 | 9095 | && t + j < current_templates.end |
39bb3ade | 9096 | && t[j].opcode_modifier.vex) |
58bceb18 JB |
9097 | { |
9098 | i386_cpu_flags cpu; | |
9099 | unsigned int memshift = i.memshift; | |
9100 | ||
9101 | i.memshift = 0; | |
39bb3ade JB |
9102 | cpu = cpu_flags_and (cpu_flags_from_attr (t[j].cpu), |
9103 | cpu_arch_isa_flags); | |
58bceb18 JB |
9104 | if (!cpu_flags_all_zero (&cpu) |
9105 | && (!i.types[0].bitfield.disp8 | |
9106 | || !operand_type_check (i.types[0], disp) | |
9107 | || i.op[0].disps->X_op != O_constant | |
9108 | || fits_in_disp8 (i.op[0].disps->X_add_number))) | |
9109 | { | |
9110 | specific_error = progress (internal_error); | |
39bb3ade | 9111 | t += j - 1; |
58bceb18 JB |
9112 | continue; |
9113 | } | |
9114 | i.memshift = memshift; | |
9115 | } | |
9116 | ||
6967f19d HL |
9117 | /* If we can optimize a NDD insn to legacy insn, like |
9118 | add %r16, %r8, %r8 -> add %r16, %r8, | |
9119 | add %r8, %r16, %r8 -> add %r16, %r8, then rematch template. | |
9120 | Note that the semantics have not been changed. */ | |
9121 | if (optimize | |
9122 | && !i.no_optimize | |
e346d50a | 9123 | && i.encoding != encoding_evex |
0ebcbb1b JB |
9124 | && ((t + 1 < current_templates.end |
9125 | && !t[1].opcode_modifier.evex | |
9126 | && t[1].opcode_space <= SPACE_0F38 | |
9127 | && t->opcode_modifier.vexvvvv == VexVVVV_DST) | |
9128 | || t->mnem_off == MN_movbe) | |
6967f19d HL |
9129 | && (i.types[i.operands - 1].bitfield.dword |
9130 | || i.types[i.operands - 1].bitfield.qword)) | |
9131 | { | |
9132 | unsigned int match_dest_op = can_convert_NDD_to_legacy (t); | |
9133 | ||
9134 | if (match_dest_op != (unsigned int) ~0) | |
9135 | { | |
9136 | size_match = true; | |
9137 | /* We ensure that the next template has the same input | |
9138 | operands as the original matching template by the first | |
9139 | opernd (ATT). To avoid someone support new NDD insns and | |
9140 | put it in the wrong position. */ | |
9141 | overlap0 = operand_type_and (i.types[0], | |
9142 | t[1].operand_types[0]); | |
9143 | if (t->opcode_modifier.d) | |
9144 | overlap1 = operand_type_and (i.types[0], | |
9145 | t[1].operand_types[1]); | |
9146 | if (!operand_type_match (overlap0, i.types[0]) | |
9147 | && (!t->opcode_modifier.d | |
9148 | || !operand_type_match (overlap1, i.types[0]))) | |
9149 | size_match = false; | |
9150 | ||
9151 | if (size_match | |
9152 | && (t[1].opcode_space <= SPACE_0F | |
9153 | /* Some non-legacy-map0/1 insns can be shorter when | |
9154 | legacy-encoded and when no REX prefix is required. */ | |
9155 | || (!check_EgprOperands (t + 1) | |
9156 | && !check_Rex_required () | |
9157 | && !i.op[i.operands - 1].regs->reg_type.bitfield.qword))) | |
9158 | { | |
9159 | if (i.operands > 2 && match_dest_op == i.operands - 3) | |
9160 | swap_2_operands (match_dest_op, i.operands - 2); | |
9161 | ||
9162 | --i.operands; | |
9163 | --i.reg_operands; | |
9164 | ||
0ebcbb1b JB |
9165 | if (t->mnem_off == MN_movbe) |
9166 | { | |
9167 | gas_assert (t[1].mnem_off == MN_bswap); | |
9168 | ++current_templates.end; | |
9169 | } | |
9170 | ||
6967f19d HL |
9171 | specific_error = progress (internal_error); |
9172 | continue; | |
9173 | } | |
9174 | ||
9175 | } | |
9176 | } | |
9177 | ||
29b0f896 AM |
9178 | /* We've found a match; break out of loop. */ |
9179 | break; | |
9180 | } | |
9181 | ||
7b94647a JB |
9182 | #undef progress |
9183 | ||
d3b01414 | 9184 | if (t == current_templates.end) |
29b0f896 AM |
9185 | { |
9186 | /* We found no match. */ | |
04784e33 | 9187 | i.error = specific_error; |
fa99fab2 | 9188 | return NULL; |
29b0f896 | 9189 | } |
252b5132 | 9190 | |
acd86c81 JB |
9191 | /* Don't emit diagnostics or install the template when one was already |
9192 | installed, i.e. when called from process_suffix(). */ | |
9193 | if (i.tm.mnem_off) | |
9194 | return t; | |
9195 | ||
29b0f896 AM |
9196 | if (!quiet_warnings) |
9197 | { | |
9198 | if (!intel_syntax | |
0cfa3eb3 | 9199 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
76d3f746 | 9200 | as_warn (_("indirect %s without `*'"), insn_name (t)); |
29b0f896 | 9201 | |
40fb9820 | 9202 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 9203 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
9204 | { |
9205 | /* Warn them that a data or address size prefix doesn't | |
9206 | affect assembly of the next line of code. */ | |
76d3f746 | 9207 | as_warn (_("stand-alone `%s' prefix"), insn_name (t)); |
29b0f896 AM |
9208 | } |
9209 | } | |
9210 | ||
9211 | /* Copy the template we found. */ | |
9a182d04 | 9212 | install_template (t); |
539e75ad L |
9213 | |
9214 | if (addr_prefix_disp != -1) | |
9215 | i.tm.operand_types[addr_prefix_disp] | |
9216 | = operand_types[addr_prefix_disp]; | |
9217 | ||
09de03fc JB |
9218 | /* APX insns acting on byte operands are WIG, yet that can't be expressed |
9219 | in the templates (they're also covering word/dword/qword operands). */ | |
9220 | if (t->opcode_space == SPACE_EVEXMAP4 && !t->opcode_modifier.vexw && | |
9221 | i.types[i.operands - 1].bitfield.byte) | |
9222 | { | |
9223 | gas_assert (t->opcode_modifier.w); | |
9224 | i.tm.opcode_modifier.vexw = VEXWIG; | |
9225 | } | |
9226 | ||
8bd915b7 | 9227 | switch (found_reverse_match) |
29b0f896 | 9228 | { |
8bd915b7 JB |
9229 | case 0: |
9230 | break; | |
9231 | ||
bd782808 JB |
9232 | case Opcode_FloatR: |
9233 | case Opcode_FloatR | Opcode_FloatD: | |
9234 | i.tm.extension_opcode ^= Opcode_FloatR >> 3; | |
9235 | found_reverse_match &= Opcode_FloatD; | |
9236 | ||
9237 | /* Fall through. */ | |
8bd915b7 | 9238 | default: |
dfd69174 JB |
9239 | /* If we found a reverse match we must alter the opcode direction |
9240 | bit and clear/flip the regmem modifier one. found_reverse_match | |
9241 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
9242 | |
9243 | i.tm.base_opcode ^= found_reverse_match; | |
9244 | ||
3083f376 | 9245 | if (i.tm.opcode_space == SPACE_EVEXMAP4) |
9246 | goto swap_first_2; | |
9247 | ||
dfd69174 JB |
9248 | /* Certain SIMD insns have their load forms specified in the opcode |
9249 | table, and hence we need to _set_ RegMem instead of clearing it. | |
9250 | We need to avoid setting the bit though on insns like KMOVW. */ | |
9251 | i.tm.opcode_modifier.regmem | |
9252 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
9253 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
9254 | && !i.tm.opcode_modifier.regmem; | |
a33ef3c2 JB |
9255 | |
9256 | /* Fall through. */ | |
9257 | case ~0: | |
9258 | i.tm.operand_types[0] = operand_types[i.operands - 1]; | |
9259 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
8bd915b7 JB |
9260 | break; |
9261 | ||
9262 | case Opcode_VexW: | |
9263 | /* Only the first two register operands need reversing, alongside | |
9264 | flipping VEX.W. */ | |
9265 | i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1; | |
9266 | ||
3083f376 | 9267 | swap_first_2: |
8bd915b7 JB |
9268 | j = i.tm.operand_types[0].bitfield.imm8; |
9269 | i.tm.operand_types[j] = operand_types[j + 1]; | |
9270 | i.tm.operand_types[j + 1] = operand_types[j]; | |
9271 | break; | |
29b0f896 AM |
9272 | } |
9273 | ||
fa99fab2 | 9274 | return t; |
29b0f896 AM |
9275 | } |
9276 | ||
9277 | static int | |
e3bb37b5 | 9278 | check_string (void) |
29b0f896 | 9279 | { |
51c8edf6 JB |
9280 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
9281 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 9282 | |
5e042380 | 9283 | if (i.seg[op] != NULL && i.seg[op] != reg_es) |
29b0f896 | 9284 | { |
51c8edf6 | 9285 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
76d3f746 | 9286 | insn_name (&i.tm), |
51c8edf6 JB |
9287 | intel_syntax ? i.tm.operands - es_op : es_op + 1, |
9288 | register_prefix); | |
9289 | return 0; | |
29b0f896 | 9290 | } |
51c8edf6 JB |
9291 | |
9292 | /* There's only ever one segment override allowed per instruction. | |
9293 | This instruction possibly has a legal segment override on the | |
9294 | second operand, so copy the segment to where non-string | |
9295 | instructions store it, allowing common code. */ | |
9296 | i.seg[op] = i.seg[1]; | |
9297 | ||
29b0f896 AM |
9298 | return 1; |
9299 | } | |
9300 | ||
9301 | static int | |
acd86c81 | 9302 | process_suffix (const insn_template *t) |
29b0f896 | 9303 | { |
7fc69528 | 9304 | bool is_movx = false; |
8b65b895 | 9305 | |
29b0f896 AM |
9306 | /* If matched instruction specifies an explicit instruction mnemonic |
9307 | suffix, use it. */ | |
673fe0f0 | 9308 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 9309 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 9310 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 9311 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 9312 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 9313 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 9314 | else if (i.reg_operands |
c8f8eebc | 9315 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
255571cd | 9316 | && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG) |
29b0f896 | 9317 | { |
65fca059 | 9318 | unsigned int numop = i.operands; |
389d00a5 JB |
9319 | |
9320 | /* MOVSX/MOVZX */ | |
ddb62495 | 9321 | is_movx = (i.tm.opcode_space == SPACE_0F |
389d00a5 | 9322 | && (i.tm.base_opcode | 8) == 0xbe) |
ddb62495 | 9323 | || (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 9324 | && i.tm.base_opcode == 0x63 |
734dfd1c | 9325 | && is_cpu (&i.tm, Cpu64)); |
389d00a5 | 9326 | |
65fca059 JB |
9327 | /* movsx/movzx want only their source operand considered here, for the |
9328 | ambiguity checking below. The suffix will be replaced afterwards | |
9329 | to represent the destination (register). */ | |
389d00a5 | 9330 | if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63)) |
65fca059 JB |
9331 | --i.operands; |
9332 | ||
643bb870 | 9333 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
7fc69528 | 9334 | if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword) |
643bb870 JB |
9335 | i.rex |= REX_W; |
9336 | ||
29b0f896 | 9337 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 9338 | based on GPR operands. */ |
29b0f896 AM |
9339 | if (!i.suffix) |
9340 | { | |
9341 | /* We take i.suffix from the last register operand specified, | |
9342 | Destination register type is more significant than source | |
381d071f L |
9343 | register type. crc32 in SSE4.2 prefers source register |
9344 | type. */ | |
7fc69528 | 9345 | unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands; |
20592a94 | 9346 | |
1a035124 JB |
9347 | while (op--) |
9348 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
9349 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
9350 | { | |
9351 | if (i.types[op].bitfield.class != Reg) | |
9352 | continue; | |
9353 | if (i.types[op].bitfield.byte) | |
9354 | i.suffix = BYTE_MNEM_SUFFIX; | |
9355 | else if (i.types[op].bitfield.word) | |
9356 | i.suffix = WORD_MNEM_SUFFIX; | |
9357 | else if (i.types[op].bitfield.dword) | |
9358 | i.suffix = LONG_MNEM_SUFFIX; | |
9359 | else if (i.types[op].bitfield.qword) | |
9360 | i.suffix = QWORD_MNEM_SUFFIX; | |
9361 | else | |
9362 | continue; | |
9363 | break; | |
9364 | } | |
65fca059 JB |
9365 | |
9366 | /* As an exception, movsx/movzx silently default to a byte source | |
9367 | in AT&T mode. */ | |
389d00a5 | 9368 | if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax) |
65fca059 | 9369 | i.suffix = BYTE_MNEM_SUFFIX; |
29b0f896 AM |
9370 | } |
9371 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
9372 | { | |
1cb0ab18 | 9373 | if (!check_byte_reg ()) |
29b0f896 AM |
9374 | return 0; |
9375 | } | |
9376 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
9377 | { | |
1cb0ab18 | 9378 | if (!check_long_reg ()) |
29b0f896 AM |
9379 | return 0; |
9380 | } | |
9381 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
9382 | { | |
1cb0ab18 | 9383 | if (!check_qword_reg ()) |
29b0f896 AM |
9384 | return 0; |
9385 | } | |
9386 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
9387 | { | |
1cb0ab18 | 9388 | if (!check_word_reg ()) |
29b0f896 AM |
9389 | return 0; |
9390 | } | |
3cd7f3e3 L |
9391 | else if (intel_syntax |
9392 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
9393 | /* Do nothing if the instruction is going to ignore the prefix. */ |
9394 | ; | |
9395 | else | |
9396 | abort (); | |
65fca059 JB |
9397 | |
9398 | /* Undo the movsx/movzx change done above. */ | |
9399 | i.operands = numop; | |
29b0f896 | 9400 | } |
3cd7f3e3 L |
9401 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
9402 | && !i.suffix) | |
29b0f896 | 9403 | { |
13e600d0 JB |
9404 | i.suffix = stackop_size; |
9405 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
9406 | { |
9407 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
9408 | .code16gcc directive to support 16-bit mode with | |
9409 | 32-bit address. For IRET without a suffix, generate | |
9410 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
9411 | handler. */ | |
13e600d0 JB |
9412 | if (i.tm.base_opcode == 0xcf) |
9413 | { | |
9414 | i.suffix = WORD_MNEM_SUFFIX; | |
9415 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
9416 | } | |
9417 | /* Warn about changed behavior for segment register push/pop. */ | |
9418 | else if ((i.tm.base_opcode | 1) == 0x07) | |
9419 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
76d3f746 | 9420 | insn_name (&i.tm)); |
06f74c5c | 9421 | } |
29b0f896 | 9422 | } |
c006a730 | 9423 | else if (!i.suffix |
0cfa3eb3 JB |
9424 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
9425 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
9426 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
ddb62495 | 9427 | || (i.tm.opcode_space == SPACE_0F |
389d00a5 | 9428 | && i.tm.base_opcode == 0x01 /* [ls][gi]dt */ |
64e74474 | 9429 | && i.tm.extension_opcode <= 3))) |
9306ca4a JB |
9430 | { |
9431 | switch (flag_code) | |
9432 | { | |
9433 | case CODE_64BIT: | |
40fb9820 | 9434 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 9435 | { |
828c2a25 JB |
9436 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9437 | || i.tm.opcode_modifier.no_lsuf) | |
9438 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
9439 | break; |
9440 | } | |
1a0670f3 | 9441 | /* Fall through. */ |
9306ca4a | 9442 | case CODE_32BIT: |
40fb9820 | 9443 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
9444 | i.suffix = LONG_MNEM_SUFFIX; |
9445 | break; | |
9446 | case CODE_16BIT: | |
40fb9820 | 9447 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
9448 | i.suffix = WORD_MNEM_SUFFIX; |
9449 | break; | |
9450 | } | |
9451 | } | |
252b5132 | 9452 | |
c006a730 | 9453 | if (!i.suffix |
3cd7f3e3 | 9454 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
9455 | /* Also cover lret/retf/iret in 64-bit mode. */ |
9456 | || (flag_code == CODE_64BIT | |
9457 | && !i.tm.opcode_modifier.no_lsuf | |
9458 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 9459 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
9460 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
9461 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
9462 | /* Accept FLDENV et al without suffix. */ |
9463 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 9464 | { |
6c0946d0 | 9465 | unsigned int suffixes, evex = 0; |
c006a730 JB |
9466 | |
9467 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
9468 | if (!i.tm.opcode_modifier.no_wsuf) | |
9469 | suffixes |= 1 << 1; | |
9470 | if (!i.tm.opcode_modifier.no_lsuf) | |
9471 | suffixes |= 1 << 2; | |
c006a730 JB |
9472 | if (!i.tm.opcode_modifier.no_ssuf) |
9473 | suffixes |= 1 << 4; | |
9474 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
9475 | suffixes |= 1 << 5; | |
9476 | ||
acd86c81 JB |
9477 | /* Operand size may be ambiguous only across multiple templates. Avoid |
9478 | the extra effort though if we already know that multiple suffixes / | |
9479 | operand sizes are allowed. Also limit this to non-SIMD operand sizes | |
9480 | (i.e. ones expressable via suffixes) for now. | |
9481 | There's one special case though that needs excluding: Insns taking | |
9482 | Disp<N> operands also match templates permitting BaseIndex. JMP in | |
9483 | particular would thus wrongly trigger the check further down. Cover | |
9484 | JUMP_DWORD insns here as well, just in case. */ | |
9485 | if (i.tm.opcode_modifier.jump != JUMP | |
9486 | && i.tm.opcode_modifier.jump != JUMP_DWORD) | |
9487 | while (!(suffixes & (suffixes - 1))) | |
9488 | { | |
9489 | /* Sadly check_VecOperands(), running ahead of install_template(), | |
9490 | may update i.memshift. Save and restore the value here. */ | |
9491 | unsigned int memshift = i.memshift; | |
9492 | ||
9493 | current_templates.start = t + 1; | |
9494 | t = match_template (0); | |
9495 | i.memshift = memshift; | |
9496 | if (t == NULL) | |
9497 | break; | |
9498 | if (!t->opcode_modifier.no_bsuf) | |
9499 | suffixes |= 1 << 0; | |
9500 | if (!t->opcode_modifier.no_wsuf) | |
9501 | suffixes |= 1 << 1; | |
9502 | if (!t->opcode_modifier.no_lsuf) | |
9503 | suffixes |= 1 << 2; | |
9504 | if (!t->opcode_modifier.no_ssuf) | |
9505 | suffixes |= 1 << 4; | |
9506 | if (flag_code == CODE_64BIT && !t->opcode_modifier.no_qsuf) | |
9507 | suffixes |= 1 << 5; | |
9508 | } | |
9509 | ||
6c0946d0 JB |
9510 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
9511 | also suitable for AT&T syntax mode, it was requested that this be | |
9512 | restricted to just Intel syntax. */ | |
a5748e0d JB |
9513 | if (intel_syntax && is_any_vex_encoding (&i.tm) |
9514 | && !i.broadcast.type && !i.broadcast.bytes) | |
6c0946d0 | 9515 | { |
b9915cbc | 9516 | unsigned int op; |
6c0946d0 | 9517 | |
b9915cbc | 9518 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 9519 | { |
4fc85f37 JB |
9520 | if (vector_size < VSZ512) |
9521 | { | |
9522 | i.tm.operand_types[op].bitfield.zmmword = 0; | |
9523 | if (vector_size < VSZ256) | |
9524 | { | |
9525 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
9526 | if (i.tm.operand_types[op].bitfield.xmmword | |
706ce984 | 9527 | && i.tm.opcode_modifier.evex == EVEXDYN) |
4fc85f37 JB |
9528 | i.tm.opcode_modifier.evex = EVEX128; |
9529 | } | |
9530 | else if (i.tm.operand_types[op].bitfield.ymmword | |
9531 | && !i.tm.operand_types[op].bitfield.xmmword | |
706ce984 | 9532 | && i.tm.opcode_modifier.evex == EVEXDYN) |
4fc85f37 JB |
9533 | i.tm.opcode_modifier.evex = EVEX256; |
9534 | } | |
706ce984 | 9535 | else if (i.tm.opcode_modifier.evex |
4fc85f37 | 9536 | && !cpu_arch_flags.bitfield.cpuavx512vl) |
6c0946d0 | 9537 | { |
b9915cbc JB |
9538 | if (i.tm.operand_types[op].bitfield.ymmword) |
9539 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
9540 | if (i.tm.operand_types[op].bitfield.zmmword) | |
9541 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
706ce984 | 9542 | if (i.tm.opcode_modifier.evex == EVEXDYN) |
b9915cbc JB |
9543 | i.tm.opcode_modifier.evex = EVEX512; |
9544 | } | |
6c0946d0 | 9545 | |
b9915cbc JB |
9546 | if (i.tm.operand_types[op].bitfield.xmmword |
9547 | + i.tm.operand_types[op].bitfield.ymmword | |
9548 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
9549 | continue; | |
6c0946d0 | 9550 | |
b9915cbc JB |
9551 | /* Any properly sized operand disambiguates the insn. */ |
9552 | if (i.types[op].bitfield.xmmword | |
9553 | || i.types[op].bitfield.ymmword | |
9554 | || i.types[op].bitfield.zmmword) | |
9555 | { | |
9556 | suffixes &= ~(7 << 6); | |
9557 | evex = 0; | |
9558 | break; | |
9559 | } | |
6c0946d0 | 9560 | |
b9915cbc JB |
9561 | if ((i.flags[op] & Operand_Mem) |
9562 | && i.tm.operand_types[op].bitfield.unspecified) | |
9563 | { | |
9564 | if (i.tm.operand_types[op].bitfield.xmmword) | |
9565 | suffixes |= 1 << 6; | |
9566 | if (i.tm.operand_types[op].bitfield.ymmword) | |
9567 | suffixes |= 1 << 7; | |
9568 | if (i.tm.operand_types[op].bitfield.zmmword) | |
9569 | suffixes |= 1 << 8; | |
706ce984 | 9570 | if (i.tm.opcode_modifier.evex) |
b9915cbc | 9571 | evex = EVEX512; |
6c0946d0 JB |
9572 | } |
9573 | } | |
9574 | } | |
9575 | ||
9576 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 9577 | if (suffixes & (suffixes - 1)) |
9306ca4a | 9578 | { |
873494c8 | 9579 | if (intel_syntax |
3cd7f3e3 | 9580 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 9581 | || operand_check == check_error)) |
9306ca4a | 9582 | { |
76d3f746 | 9583 | as_bad (_("ambiguous operand size for `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
9584 | return 0; |
9585 | } | |
c006a730 | 9586 | if (operand_check == check_error) |
9306ca4a | 9587 | { |
c006a730 | 9588 | as_bad (_("no instruction mnemonic suffix given and " |
76d3f746 | 9589 | "no register operands; can't size `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
9590 | return 0; |
9591 | } | |
c006a730 | 9592 | if (operand_check == check_warning) |
873494c8 JB |
9593 | as_warn (_("%s; using default for `%s'"), |
9594 | intel_syntax | |
9595 | ? _("ambiguous operand size") | |
9596 | : _("no instruction mnemonic suffix given and " | |
9597 | "no register operands"), | |
76d3f746 | 9598 | insn_name (&i.tm)); |
c006a730 JB |
9599 | |
9600 | if (i.tm.opcode_modifier.floatmf) | |
9601 | i.suffix = SHORT_MNEM_SUFFIX; | |
389d00a5 | 9602 | else if (is_movx) |
65fca059 | 9603 | /* handled below */; |
6c0946d0 JB |
9604 | else if (evex) |
9605 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
9606 | else if (flag_code == CODE_16BIT) |
9607 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 9608 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 9609 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
9610 | else |
9611 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 9612 | } |
29b0f896 | 9613 | } |
252b5132 | 9614 | |
389d00a5 | 9615 | if (is_movx) |
65fca059 JB |
9616 | { |
9617 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
9618 | In AT&T syntax, if there is no suffix (warned about above), the default | |
9619 | will be byte extension. */ | |
9620 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
9621 | i.tm.base_opcode |= 1; | |
9622 | ||
9623 | /* For further processing, the suffix should represent the destination | |
9624 | (register). This is already the case when one was used with | |
9625 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
9626 | no suffix to begin with. */ | |
9627 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
9628 | { | |
9629 | if (i.types[1].bitfield.word) | |
9630 | i.suffix = WORD_MNEM_SUFFIX; | |
9631 | else if (i.types[1].bitfield.qword) | |
9632 | i.suffix = QWORD_MNEM_SUFFIX; | |
9633 | else | |
9634 | i.suffix = LONG_MNEM_SUFFIX; | |
9635 | ||
9636 | i.tm.opcode_modifier.w = 0; | |
9637 | } | |
9638 | } | |
9639 | ||
50128d0c JB |
9640 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
9641 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
9642 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
9643 | ||
d2224064 JB |
9644 | /* Change the opcode based on the operand size given by i.suffix. */ |
9645 | switch (i.suffix) | |
29b0f896 | 9646 | { |
d2224064 JB |
9647 | /* Size floating point instruction. */ |
9648 | case LONG_MNEM_SUFFIX: | |
9649 | if (i.tm.opcode_modifier.floatmf) | |
9650 | { | |
9651 | i.tm.base_opcode ^= 4; | |
9652 | break; | |
9653 | } | |
9654 | /* fall through */ | |
9655 | case WORD_MNEM_SUFFIX: | |
9656 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 9657 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 9658 | if (i.tm.opcode_modifier.w) |
29b0f896 | 9659 | { |
50128d0c | 9660 | if (i.short_form) |
29b0f896 AM |
9661 | i.tm.base_opcode |= 8; |
9662 | else | |
9663 | i.tm.base_opcode |= 1; | |
9664 | } | |
4e3be89f JB |
9665 | |
9666 | /* Set mode64 for an operand. */ | |
9667 | if (i.suffix == QWORD_MNEM_SUFFIX) | |
9668 | { | |
9669 | if (flag_code == CODE_64BIT | |
9670 | && !i.tm.opcode_modifier.norex64 | |
9671 | && !i.tm.opcode_modifier.vexw | |
9672 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
9673 | need rex64. */ | |
9674 | && ! (i.operands == 2 | |
9675 | && i.tm.base_opcode == 0x90 | |
9676 | && i.tm.opcode_space == SPACE_BASE | |
9677 | && i.types[0].bitfield.instance == Accum | |
9678 | && i.types[1].bitfield.instance == Accum)) | |
9679 | i.rex |= REX_W; | |
9680 | ||
9681 | break; | |
9682 | } | |
9683 | ||
d2224064 JB |
9684 | /* fall through */ |
9685 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
9686 | /* Now select between word & dword operations via the operand |
9687 | size prefix, except for instructions that will ignore this | |
9688 | prefix anyway. */ | |
4e3be89f | 9689 | if (i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc | 9690 | && !i.tm.opcode_modifier.floatmf |
6177c84d CL |
9691 | && (!is_any_vex_encoding (&i.tm) |
9692 | || i.tm.opcode_space == SPACE_EVEXMAP4) | |
c8f8eebc JB |
9693 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
9694 | || (flag_code == CODE_64BIT | |
9695 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
9696 | { |
9697 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 9698 | |
0cfa3eb3 | 9699 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 9700 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 9701 | |
6177c84d CL |
9702 | /* The DATA PREFIX of EVEX promoted from legacy APX instructions |
9703 | needs to be adjusted. */ | |
9704 | if (i.tm.opcode_space == SPACE_EVEXMAP4) | |
9705 | { | |
9706 | gas_assert (!i.tm.opcode_modifier.opcodeprefix); | |
9707 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; | |
9708 | } | |
9709 | else if (!add_prefix (prefix)) | |
29b0f896 | 9710 | return 0; |
24eab124 | 9711 | } |
252b5132 | 9712 | |
d2224064 | 9713 | break; |
8bbb3ad8 JB |
9714 | |
9715 | case 0: | |
f9a6a8f0 | 9716 | /* Select word/dword/qword operation with explicit data sizing prefix |
8bbb3ad8 JB |
9717 | when there are no suitable register operands. */ |
9718 | if (i.tm.opcode_modifier.w | |
9719 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
9720 | && (!i.reg_operands | |
9721 | || (i.reg_operands == 1 | |
9722 | /* ShiftCount */ | |
9723 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
9724 | /* InOutPortReg */ | |
9725 | || i.tm.operand_types[0].bitfield.instance == RegD | |
9726 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7fc69528 | 9727 | || i.tm.mnem_off == MN_crc32)))) |
8bbb3ad8 JB |
9728 | i.tm.base_opcode |= 1; |
9729 | break; | |
29b0f896 | 9730 | } |
7ecd2f8b | 9731 | |
255571cd | 9732 | if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG) |
c0a30a9f | 9733 | { |
c8f8eebc JB |
9734 | gas_assert (!i.suffix); |
9735 | gas_assert (i.reg_operands); | |
c0a30a9f | 9736 | |
c8f8eebc JB |
9737 | if (i.tm.operand_types[0].bitfield.instance == Accum |
9738 | || i.operands == 1) | |
9739 | { | |
9740 | /* The address size override prefix changes the size of the | |
9741 | first operand. */ | |
9742 | if (flag_code == CODE_64BIT | |
9743 | && i.op[0].regs->reg_type.bitfield.word) | |
9744 | { | |
9745 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
76d3f746 | 9746 | insn_name (&i.tm)); |
c8f8eebc JB |
9747 | return 0; |
9748 | } | |
9749 | ||
9750 | if ((flag_code == CODE_32BIT | |
9751 | ? i.op[0].regs->reg_type.bitfield.word | |
9752 | : i.op[0].regs->reg_type.bitfield.dword) | |
9753 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
9754 | return 0; | |
9755 | } | |
c0a30a9f L |
9756 | else |
9757 | { | |
c8f8eebc JB |
9758 | /* Check invalid register operand when the address size override |
9759 | prefix changes the size of register operands. */ | |
9760 | unsigned int op; | |
9761 | enum { need_word, need_dword, need_qword } need; | |
9762 | ||
27f13469 | 9763 | /* Check the register operand for the address size prefix if |
b3a3496f | 9764 | the memory operand has no real registers, like symbol, DISP |
829f3fe1 | 9765 | or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */ |
27f13469 L |
9766 | if (i.mem_operands == 1 |
9767 | && i.reg_operands == 1 | |
9768 | && i.operands == 2 | |
27f13469 | 9769 | && i.types[1].bitfield.class == Reg |
b3a3496f L |
9770 | && (flag_code == CODE_32BIT |
9771 | ? i.op[1].regs->reg_type.bitfield.word | |
9772 | : i.op[1].regs->reg_type.bitfield.dword) | |
9773 | && ((i.base_reg == NULL && i.index_reg == NULL) | |
829f3fe1 JB |
9774 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
9775 | || (x86_elf_abi == X86_64_X32_ABI | |
9776 | && i.base_reg | |
b3a3496f L |
9777 | && i.base_reg->reg_num == RegIP |
9778 | && i.base_reg->reg_type.bitfield.qword)) | |
829f3fe1 JB |
9779 | #else |
9780 | || 0) | |
9781 | #endif | |
27f13469 L |
9782 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
9783 | return 0; | |
9784 | ||
c8f8eebc JB |
9785 | if (flag_code == CODE_32BIT) |
9786 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
9787 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
9788 | need = need_dword; |
9789 | else | |
9790 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 9791 | |
c8f8eebc JB |
9792 | for (op = 0; op < i.operands; op++) |
9793 | { | |
9794 | if (i.types[op].bitfield.class != Reg) | |
9795 | continue; | |
9796 | ||
9797 | switch (need) | |
9798 | { | |
9799 | case need_word: | |
9800 | if (i.op[op].regs->reg_type.bitfield.word) | |
9801 | continue; | |
9802 | break; | |
9803 | case need_dword: | |
9804 | if (i.op[op].regs->reg_type.bitfield.dword) | |
9805 | continue; | |
9806 | break; | |
9807 | case need_qword: | |
9808 | if (i.op[op].regs->reg_type.bitfield.qword) | |
9809 | continue; | |
9810 | break; | |
9811 | } | |
9812 | ||
9813 | as_bad (_("invalid register operand size for `%s'"), | |
76d3f746 | 9814 | insn_name (&i.tm)); |
c8f8eebc JB |
9815 | return 0; |
9816 | } | |
9817 | } | |
c0a30a9f L |
9818 | } |
9819 | ||
29b0f896 AM |
9820 | return 1; |
9821 | } | |
3e73aa7c | 9822 | |
29b0f896 | 9823 | static int |
543613e9 | 9824 | check_byte_reg (void) |
29b0f896 AM |
9825 | { |
9826 | int op; | |
543613e9 | 9827 | |
29b0f896 AM |
9828 | for (op = i.operands; --op >= 0;) |
9829 | { | |
dc821c5f | 9830 | /* Skip non-register operands. */ |
bab6aec1 | 9831 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
9832 | continue; |
9833 | ||
29b0f896 AM |
9834 | /* If this is an eight bit register, it's OK. If it's the 16 or |
9835 | 32 bit version of an eight bit register, we will just use the | |
9836 | low portion, and that's OK too. */ | |
dc821c5f | 9837 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
9838 | continue; |
9839 | ||
5a819eb9 | 9840 | /* I/O port address operands are OK too. */ |
75e5731b JB |
9841 | if (i.tm.operand_types[op].bitfield.instance == RegD |
9842 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
9843 | continue; |
9844 | ||
9706160a | 9845 | /* crc32 only wants its source operand checked here. */ |
7fc69528 | 9846 | if (i.tm.mnem_off == MN_crc32 && op != 0) |
9344ff29 L |
9847 | continue; |
9848 | ||
29b0f896 | 9849 | /* Any other register is bad. */ |
73c76375 JB |
9850 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
9851 | register_prefix, i.op[op].regs->reg_name, | |
76d3f746 | 9852 | insn_name (&i.tm), i.suffix); |
73c76375 | 9853 | return 0; |
29b0f896 AM |
9854 | } |
9855 | return 1; | |
9856 | } | |
9857 | ||
9858 | static int | |
e3bb37b5 | 9859 | check_long_reg (void) |
29b0f896 AM |
9860 | { |
9861 | int op; | |
9862 | ||
9863 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 9864 | /* Skip non-register operands. */ |
bab6aec1 | 9865 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 9866 | continue; |
29b0f896 AM |
9867 | /* Reject eight bit registers, except where the template requires |
9868 | them. (eg. movzb) */ | |
dc821c5f | 9869 | else if (i.types[op].bitfield.byte |
dc821c5f | 9870 | && (i.tm.operand_types[op].bitfield.word |
fb40ea39 JB |
9871 | || i.tm.operand_types[op].bitfield.dword |
9872 | || i.tm.operand_types[op].bitfield.qword)) | |
29b0f896 | 9873 | { |
a540244d L |
9874 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
9875 | register_prefix, | |
29b0f896 | 9876 | i.op[op].regs->reg_name, |
76d3f746 | 9877 | insn_name (&i.tm), |
29b0f896 AM |
9878 | i.suffix); |
9879 | return 0; | |
9880 | } | |
d9a1b711 JB |
9881 | /* Error if the e prefix on a general reg is missing, or if the r |
9882 | prefix on a general reg is present. */ | |
9883 | else if ((i.types[op].bitfield.word | |
9884 | || i.types[op].bitfield.qword) | |
dc821c5f | 9885 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 9886 | { |
be4c5e58 L |
9887 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
9888 | register_prefix, i.op[op].regs->reg_name, | |
9889 | i.suffix); | |
9890 | return 0; | |
252b5132 | 9891 | } |
29b0f896 AM |
9892 | return 1; |
9893 | } | |
252b5132 | 9894 | |
29b0f896 | 9895 | static int |
e3bb37b5 | 9896 | check_qword_reg (void) |
29b0f896 AM |
9897 | { |
9898 | int op; | |
252b5132 | 9899 | |
29b0f896 | 9900 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 9901 | /* Skip non-register operands. */ |
bab6aec1 | 9902 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 9903 | continue; |
29b0f896 AM |
9904 | /* Reject eight bit registers, except where the template requires |
9905 | them. (eg. movzb) */ | |
dc821c5f | 9906 | else if (i.types[op].bitfield.byte |
dc821c5f | 9907 | && (i.tm.operand_types[op].bitfield.word |
742b55c7 JB |
9908 | || i.tm.operand_types[op].bitfield.dword |
9909 | || i.tm.operand_types[op].bitfield.qword)) | |
29b0f896 | 9910 | { |
a540244d L |
9911 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
9912 | register_prefix, | |
29b0f896 | 9913 | i.op[op].regs->reg_name, |
76d3f746 | 9914 | insn_name (&i.tm), |
29b0f896 AM |
9915 | i.suffix); |
9916 | return 0; | |
9917 | } | |
d9a1b711 | 9918 | /* Error if the r prefix on a general reg is missing. */ |
dc821c5f JB |
9919 | else if ((i.types[op].bitfield.word |
9920 | || i.types[op].bitfield.dword) | |
dc821c5f | 9921 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 | 9922 | { |
1cb0ab18 JB |
9923 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
9924 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
9925 | return 0; | |
252b5132 | 9926 | } |
29b0f896 AM |
9927 | return 1; |
9928 | } | |
252b5132 | 9929 | |
29b0f896 | 9930 | static int |
e3bb37b5 | 9931 | check_word_reg (void) |
29b0f896 AM |
9932 | { |
9933 | int op; | |
9934 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 9935 | /* Skip non-register operands. */ |
bab6aec1 | 9936 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 9937 | continue; |
29b0f896 AM |
9938 | /* Reject eight bit registers, except where the template requires |
9939 | them. (eg. movzb) */ | |
dc821c5f | 9940 | else if (i.types[op].bitfield.byte |
dc821c5f | 9941 | && (i.tm.operand_types[op].bitfield.word |
fb40ea39 JB |
9942 | || i.tm.operand_types[op].bitfield.dword |
9943 | || i.tm.operand_types[op].bitfield.qword)) | |
29b0f896 | 9944 | { |
a540244d L |
9945 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
9946 | register_prefix, | |
29b0f896 | 9947 | i.op[op].regs->reg_name, |
76d3f746 | 9948 | insn_name (&i.tm), |
29b0f896 AM |
9949 | i.suffix); |
9950 | return 0; | |
9951 | } | |
9706160a JB |
9952 | /* Error if the e or r prefix on a general reg is present. */ |
9953 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 9954 | || i.types[op].bitfield.qword) |
dc821c5f | 9955 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 9956 | { |
9706160a JB |
9957 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
9958 | register_prefix, i.op[op].regs->reg_name, | |
9959 | i.suffix); | |
9960 | return 0; | |
29b0f896 AM |
9961 | } |
9962 | return 1; | |
9963 | } | |
252b5132 | 9964 | |
29b0f896 | 9965 | static int |
40fb9820 | 9966 | update_imm (unsigned int j) |
29b0f896 | 9967 | { |
bc0844ae | 9968 | i386_operand_type overlap = i.types[j]; |
c34d1cc9 JB |
9969 | |
9970 | if (i.tm.operand_types[j].bitfield.imm8 | |
9971 | && i.tm.operand_types[j].bitfield.imm8s | |
9972 | && overlap.bitfield.imm8 && overlap.bitfield.imm8s) | |
9973 | { | |
9974 | /* This combination is used on 8-bit immediates where e.g. $~0 is | |
9975 | desirable to permit. We're past operand type matching, so simply | |
9976 | put things back in the shape they were before introducing the | |
9977 | distinction between Imm8, Imm8S, and Imm8|Imm8S. */ | |
9978 | overlap.bitfield.imm8s = 0; | |
9979 | } | |
9980 | ||
be1643ff JB |
9981 | if (overlap.bitfield.imm8 |
9982 | + overlap.bitfield.imm8s | |
9983 | + overlap.bitfield.imm16 | |
9984 | + overlap.bitfield.imm32 | |
9985 | + overlap.bitfield.imm32s | |
9986 | + overlap.bitfield.imm64 > 1) | |
29b0f896 | 9987 | { |
05909f23 JB |
9988 | static const i386_operand_type imm16 = { .bitfield = { .imm16 = 1 } }; |
9989 | static const i386_operand_type imm32 = { .bitfield = { .imm32 = 1 } }; | |
9990 | static const i386_operand_type imm32s = { .bitfield = { .imm32s = 1 } }; | |
9991 | static const i386_operand_type imm16_32 = { .bitfield = | |
9992 | { .imm16 = 1, .imm32 = 1 } | |
9993 | }; | |
9994 | static const i386_operand_type imm16_32s = { .bitfield = | |
9995 | { .imm16 = 1, .imm32s = 1 } | |
9996 | }; | |
9997 | static const i386_operand_type imm16_32_32s = { .bitfield = | |
9998 | { .imm16 = 1, .imm32 = 1, .imm32s = 1 } | |
9999 | }; | |
10000 | ||
29b0f896 AM |
10001 | if (i.suffix) |
10002 | { | |
40fb9820 L |
10003 | i386_operand_type temp; |
10004 | ||
0dfbf9d7 | 10005 | operand_type_set (&temp, 0); |
7ab9ffdd | 10006 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
10007 | { |
10008 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
10009 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
10010 | } | |
10011 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
10012 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
10013 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
10014 | { | |
10015 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
10016 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
10017 | } | |
10018 | else | |
10019 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
10020 | overlap = temp; | |
29b0f896 | 10021 | } |
0dfbf9d7 L |
10022 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
10023 | || operand_type_equal (&overlap, &imm16_32) | |
10024 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 10025 | { |
f79d55e1 JB |
10026 | if ((flag_code == CODE_16BIT) |
10027 | ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W))) | |
65da13b5 | 10028 | overlap = imm16; |
40fb9820 | 10029 | else |
65da13b5 | 10030 | overlap = imm32s; |
29b0f896 | 10031 | } |
8bbb3ad8 JB |
10032 | else if (i.prefix[REX_PREFIX] & REX_W) |
10033 | overlap = operand_type_and (overlap, imm32s); | |
10034 | else if (i.prefix[DATA_PREFIX]) | |
10035 | overlap = operand_type_and (overlap, | |
10036 | flag_code != CODE_16BIT ? imm16 : imm32); | |
be1643ff JB |
10037 | if (overlap.bitfield.imm8 |
10038 | + overlap.bitfield.imm8s | |
10039 | + overlap.bitfield.imm16 | |
10040 | + overlap.bitfield.imm32 | |
10041 | + overlap.bitfield.imm32s | |
10042 | + overlap.bitfield.imm64 != 1) | |
29b0f896 | 10043 | { |
4eed87de AM |
10044 | as_bad (_("no instruction mnemonic suffix given; " |
10045 | "can't determine immediate size")); | |
29b0f896 AM |
10046 | return 0; |
10047 | } | |
10048 | } | |
40fb9820 | 10049 | i.types[j] = overlap; |
29b0f896 | 10050 | |
40fb9820 L |
10051 | return 1; |
10052 | } | |
10053 | ||
10054 | static int | |
10055 | finalize_imm (void) | |
10056 | { | |
bc0844ae | 10057 | unsigned int j, n; |
29b0f896 | 10058 | |
bc0844ae L |
10059 | /* Update the first 2 immediate operands. */ |
10060 | n = i.operands > 2 ? 2 : i.operands; | |
10061 | if (n) | |
10062 | { | |
10063 | for (j = 0; j < n; j++) | |
10064 | if (update_imm (j) == 0) | |
10065 | return 0; | |
40fb9820 | 10066 | |
bc0844ae L |
10067 | /* The 3rd operand can't be immediate operand. */ |
10068 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
10069 | } | |
29b0f896 AM |
10070 | |
10071 | return 1; | |
10072 | } | |
10073 | ||
0a3eba42 JB |
10074 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
10075 | bool do_sse2avx) | |
10076 | { | |
10077 | if (r->reg_flags & RegRex) | |
10078 | { | |
10079 | if (i.rex & rex_bit) | |
10080 | as_bad (_("same type of prefix used twice")); | |
10081 | i.rex |= rex_bit; | |
10082 | } | |
10083 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
10084 | { | |
10085 | gas_assert (i.vex.register_specifier == r); | |
10086 | i.vex.register_specifier += 8; | |
10087 | } | |
10088 | ||
10089 | if (r->reg_flags & RegVRex) | |
10090 | i.vrex |= rex_bit; | |
80d61d8d CL |
10091 | |
10092 | if (r->reg_flags & RegRex2) | |
10093 | i.rex2 |= rex_bit; | |
10094 | } | |
10095 | ||
10096 | static INLINE void | |
10097 | set_rex_rex2 (const reg_entry *r, unsigned int rex_bit) | |
10098 | { | |
10099 | if ((r->reg_flags & RegRex) != 0) | |
10100 | i.rex |= rex_bit; | |
10101 | if ((r->reg_flags & RegRex2) != 0) | |
10102 | i.rex2 |= rex_bit; | |
0a3eba42 JB |
10103 | } |
10104 | ||
29b0f896 | 10105 | static int |
e3bb37b5 | 10106 | process_operands (void) |
29b0f896 AM |
10107 | { |
10108 | /* Default segment register this instruction will use for memory | |
10109 | accesses. 0 means unknown. This is only for optimizing out | |
10110 | unnecessary segment overrides. */ | |
5e042380 | 10111 | const reg_entry *default_seg = NULL; |
29b0f896 | 10112 | |
3083f376 | 10113 | for (unsigned int j = 0; j < i.operands; j++) |
10114 | if (i.types[j].bitfield.instance != InstanceNone) | |
10115 | i.reg_operands--; | |
31b4cda3 | 10116 | |
a5aeccd9 JB |
10117 | if (i.tm.opcode_modifier.sse2avx) |
10118 | { | |
10119 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
10120 | need converting. */ | |
10121 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
10122 | i.prefix[REX_PREFIX] = 0; | |
10123 | i.rex_encoding = 0; | |
ebe82bfd | 10124 | i.rex2_encoding = 0; |
a5aeccd9 | 10125 | } |
c423d21a JB |
10126 | /* ImmExt should be processed after SSE2AVX. */ |
10127 | else if (i.tm.opcode_modifier.immext) | |
10128 | process_immext (); | |
a5aeccd9 | 10129 | |
ecb96e55 JB |
10130 | /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg, |
10131 | not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a | |
10132 | new destination operand here, while converting the source one to register | |
10133 | number 0. */ | |
10134 | if (i.tm.mnem_off == MN_tilezero) | |
10135 | { | |
10136 | i.op[1].regs = i.op[0].regs; | |
10137 | i.op[0].regs -= i.op[0].regs->reg_num; | |
10138 | i.types[1] = i.types[0]; | |
10139 | i.tm.operand_types[1] = i.tm.operand_types[0]; | |
10140 | i.flags[1] = i.flags[0]; | |
10141 | i.operands++; | |
10142 | i.reg_operands++; | |
10143 | i.tm.operands++; | |
10144 | } | |
10145 | ||
2426c15f | 10146 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 10147 | { |
05909f23 JB |
10148 | static const i386_operand_type regxmm = { |
10149 | .bitfield = { .class = RegSIMD, .xmmword = 1 } | |
10150 | }; | |
91d6fa6a NC |
10151 | unsigned int dupl = i.operands; |
10152 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
10153 | unsigned int j; |
10154 | ||
c0f3af97 | 10155 | /* The destination must be an xmm register. */ |
9c2799c2 | 10156 | gas_assert (i.reg_operands |
91d6fa6a | 10157 | && MAX_OPERANDS > dupl |
7ab9ffdd | 10158 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 10159 | |
75e5731b | 10160 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 10161 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 10162 | { |
95dfdd85 JB |
10163 | /* Keep xmm0 for instructions with VEX prefix and 3 |
10164 | sources. */ | |
10165 | i.tm.operand_types[0].bitfield.instance = InstanceNone; | |
10166 | i.tm.operand_types[0].bitfield.class = RegSIMD; | |
31b4cda3 | 10167 | i.reg_operands++; |
95dfdd85 | 10168 | goto duplicate; |
c0f3af97 | 10169 | } |
95dfdd85 JB |
10170 | |
10171 | if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0) | |
7ab9ffdd | 10172 | { |
aa180741 | 10173 | gas_assert ((MAX_OPERANDS - 1) > dupl); |
c0f3af97 L |
10174 | |
10175 | /* Add the implicit xmm0 for instructions with VEX prefix | |
10176 | and 3 sources. */ | |
10177 | for (j = i.operands; j > 0; j--) | |
10178 | { | |
10179 | i.op[j] = i.op[j - 1]; | |
10180 | i.types[j] = i.types[j - 1]; | |
10181 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 10182 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
10183 | } |
10184 | i.op[0].regs | |
629310ab | 10185 | = (const reg_entry *) str_hash_find (reg_hash, "xmm0"); |
7ab9ffdd | 10186 | i.types[0] = regxmm; |
c0f3af97 L |
10187 | i.tm.operand_types[0] = regxmm; |
10188 | ||
10189 | i.operands += 2; | |
10190 | i.reg_operands += 2; | |
10191 | i.tm.operands += 2; | |
10192 | ||
91d6fa6a | 10193 | dupl++; |
c0f3af97 | 10194 | dest++; |
91d6fa6a NC |
10195 | i.op[dupl] = i.op[dest]; |
10196 | i.types[dupl] = i.types[dest]; | |
10197 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 10198 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 10199 | } |
c0f3af97 L |
10200 | else |
10201 | { | |
dc1e8a47 | 10202 | duplicate: |
c0f3af97 L |
10203 | i.operands++; |
10204 | i.reg_operands++; | |
10205 | i.tm.operands++; | |
10206 | ||
91d6fa6a NC |
10207 | i.op[dupl] = i.op[dest]; |
10208 | i.types[dupl] = i.types[dest]; | |
10209 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 10210 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
10211 | } |
10212 | ||
10213 | if (i.tm.opcode_modifier.immext) | |
10214 | process_immext (); | |
10215 | } | |
75e5731b | 10216 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
bd782808 | 10217 | && i.tm.opcode_modifier.modrm) |
c0f3af97 L |
10218 | { |
10219 | unsigned int j; | |
10220 | ||
9fcfb3d7 L |
10221 | for (j = 1; j < i.operands; j++) |
10222 | { | |
10223 | i.op[j - 1] = i.op[j]; | |
10224 | i.types[j - 1] = i.types[j]; | |
10225 | ||
10226 | /* We need to adjust fields in i.tm since they are used by | |
10227 | build_modrm_byte. */ | |
10228 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
10229 | |
10230 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
10231 | } |
10232 | ||
31b4cda3 JB |
10233 | /* No adjustment to i.reg_operands: This was already done at the top |
10234 | of the function. */ | |
e2ec9d29 | 10235 | i.operands--; |
e2ec9d29 L |
10236 | i.tm.operands--; |
10237 | } | |
255571cd | 10238 | else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP) |
920d2ddc | 10239 | { |
a477a8c4 JB |
10240 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
10241 | ||
920d2ddc | 10242 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 10243 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
10244 | regnum = register_number (i.op[1].regs); |
10245 | first_reg_in_group = regnum & ~3; | |
10246 | last_reg_in_group = first_reg_in_group + 3; | |
10247 | if (regnum != first_reg_in_group) | |
10248 | as_warn (_("source register `%s%s' implicitly denotes" | |
10249 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
10250 | register_prefix, i.op[1].regs->reg_name, | |
10251 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
10252 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
76d3f746 | 10253 | insn_name (&i.tm)); |
a477a8c4 | 10254 | } |
255571cd | 10255 | else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE) |
e2ec9d29 L |
10256 | { |
10257 | /* The imul $imm, %reg instruction is converted into | |
10258 | imul $imm, %reg, %reg, and the clr %reg instruction | |
10259 | is converted into xor %reg, %reg. */ | |
10260 | ||
10261 | unsigned int first_reg_op; | |
10262 | ||
10263 | if (operand_type_check (i.types[0], reg)) | |
10264 | first_reg_op = 0; | |
10265 | else | |
10266 | first_reg_op = 1; | |
10267 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 10268 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 10269 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
10270 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
10271 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
10272 | i.operands++; | |
10273 | i.reg_operands++; | |
29b0f896 AM |
10274 | } |
10275 | ||
85b80b0f | 10276 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
10277 | { |
10278 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
10279 | must be put into the modrm byte). Now, we make the modrm and |
10280 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
10281 | |
10282 | default_seg = build_modrm_byte (); | |
bd782808 JB |
10283 | |
10284 | if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) | |
10285 | { | |
10286 | /* Warn about some common errors, but press on regardless. */ | |
10287 | if (i.operands == 2) | |
10288 | { | |
10289 | /* Reversed arguments on faddp or fmulp. */ | |
10290 | as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i.tm), | |
10291 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
10292 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
10293 | } | |
10294 | else if (i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
10295 | { | |
10296 | /* Extraneous `l' suffix on fp insn. */ | |
10297 | as_warn (_("translating to `%s %s%s'"), insn_name (&i.tm), | |
10298 | register_prefix, i.op[0].regs->reg_name); | |
10299 | } | |
10300 | } | |
29b0f896 | 10301 | } |
0ff3b7d0 | 10302 | else if (i.types[0].bitfield.class == SReg && !dot_insn ()) |
85b80b0f JB |
10303 | { |
10304 | if (flag_code != CODE_64BIT | |
10305 | ? i.tm.base_opcode == POP_SEG_SHORT | |
10306 | && i.op[0].regs->reg_num == 1 | |
389d00a5 | 10307 | : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff) |
85b80b0f JB |
10308 | && i.op[0].regs->reg_num < 4) |
10309 | { | |
10310 | as_bad (_("you can't `%s %s%s'"), | |
76d3f746 | 10311 | insn_name (&i.tm), register_prefix, i.op[0].regs->reg_name); |
85b80b0f JB |
10312 | return 0; |
10313 | } | |
389d00a5 | 10314 | if (i.op[0].regs->reg_num > 3 |
ddb62495 | 10315 | && i.tm.opcode_space == SPACE_BASE ) |
85b80b0f | 10316 | { |
389d00a5 | 10317 | i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff; |
ddb62495 | 10318 | i.tm.opcode_space = SPACE_0F; |
85b80b0f JB |
10319 | } |
10320 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
10321 | } | |
ddb62495 | 10322 | else if (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 10323 | && (i.tm.base_opcode & ~3) == MOV_AX_DISP32) |
29b0f896 | 10324 | { |
5e042380 | 10325 | default_seg = reg_ds; |
29b0f896 | 10326 | } |
40fb9820 | 10327 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
10328 | { |
10329 | /* For the string instructions that allow a segment override | |
10330 | on one of their operands, the default segment is ds. */ | |
5e042380 | 10331 | default_seg = reg_ds; |
29b0f896 | 10332 | } |
50128d0c | 10333 | else if (i.short_form) |
85b80b0f | 10334 | { |
0ff3b7d0 JB |
10335 | /* The register operand is in the 1st or 2nd non-immediate operand. */ |
10336 | const reg_entry *r = i.op[i.imm_operands].regs; | |
85b80b0f | 10337 | |
0ff3b7d0 JB |
10338 | if (!dot_insn () |
10339 | && r->reg_type.bitfield.instance == Accum | |
10340 | && i.op[i.imm_operands + 1].regs) | |
10341 | r = i.op[i.imm_operands + 1].regs; | |
85b80b0f | 10342 | /* Register goes in low 3 bits of opcode. */ |
4943d587 | 10343 | i.tm.base_opcode |= r->reg_num; |
0a3eba42 | 10344 | set_rex_vrex (r, REX_B, false); |
0ff3b7d0 JB |
10345 | |
10346 | if (dot_insn () && i.reg_operands == 2) | |
10347 | { | |
10348 | gas_assert (is_any_vex_encoding (&i.tm) | |
e346d50a | 10349 | || i.encoding != encoding_default); |
0ff3b7d0 JB |
10350 | i.vex.register_specifier = i.op[i.operands - 1].regs; |
10351 | } | |
10352 | } | |
10353 | else if (i.reg_operands == 1 | |
10354 | && !i.flags[i.operands - 1] | |
10355 | && i.tm.operand_types[i.operands - 1].bitfield.instance | |
10356 | == InstanceNone) | |
10357 | { | |
10358 | gas_assert (is_any_vex_encoding (&i.tm) | |
e346d50a | 10359 | || i.encoding != encoding_default); |
0ff3b7d0 | 10360 | i.vex.register_specifier = i.op[i.operands - 1].regs; |
85b80b0f | 10361 | } |
29b0f896 | 10362 | |
514a8bb0 | 10363 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
7fc69528 | 10364 | && i.tm.mnem_off == MN_lea) |
92334ad2 JB |
10365 | { |
10366 | if (!quiet_warnings) | |
76d3f746 | 10367 | as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm)); |
739d7649 | 10368 | if (optimize && !i.no_optimize) |
92334ad2 JB |
10369 | { |
10370 | i.seg[0] = NULL; | |
10371 | i.prefix[SEG_PREFIX] = 0; | |
10372 | } | |
10373 | } | |
52271982 AM |
10374 | |
10375 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
10376 | is neither the default nor the one already recorded from a prefix, |
10377 | use an opcode prefix to select it. If we never figured out what | |
10378 | the default segment is, then default_seg will be zero at this | |
10379 | point, and the specified segment prefix will always be used. */ | |
10380 | if (i.seg[0] | |
10381 | && i.seg[0] != default_seg | |
5e042380 | 10382 | && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX]) |
29b0f896 | 10383 | { |
5e042380 | 10384 | if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num])) |
29b0f896 AM |
10385 | return 0; |
10386 | } | |
10387 | return 1; | |
10388 | } | |
10389 | ||
5e042380 | 10390 | static const reg_entry * |
e3bb37b5 | 10391 | build_modrm_byte (void) |
29b0f896 | 10392 | { |
5e042380 | 10393 | const reg_entry *default_seg = NULL; |
ecb96e55 JB |
10394 | unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext |
10395 | /* Compensate for kludge in md_assemble(). */ | |
10396 | + i.tm.operand_types[0].bitfield.imm1; | |
10397 | unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext; | |
f2a3a881 | 10398 | unsigned int v, op, reg_slot; |
ecb96e55 JB |
10399 | |
10400 | /* Accumulator (in particular %st), shift count (%cl), and alike need | |
10401 | to be skipped just like immediate operands do. */ | |
10402 | if (i.tm.operand_types[source].bitfield.instance) | |
10403 | ++source; | |
10404 | while (i.tm.operand_types[dest].bitfield.instance) | |
10405 | --dest; | |
10406 | ||
10407 | for (op = source; op < i.operands; ++op) | |
10408 | if (i.tm.operand_types[op].bitfield.baseindex) | |
10409 | break; | |
c0f3af97 | 10410 | |
ecb96e55 | 10411 | if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4) |
c0f3af97 | 10412 | { |
4c2c6516 | 10413 | expressionS *exp; |
c0f3af97 | 10414 | |
a683cc34 | 10415 | /* There are 2 kinds of instructions: |
bed3d976 | 10416 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 10417 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 10418 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 10419 | ZMM register. |
bed3d976 | 10420 | 2. 4 operands: 4 register operands or 3 register operands |
0ff3b7d0 JB |
10421 | plus 1 memory operand, with VexXDS. |
10422 | 3. Other equivalent combinations when coming from s_insn(). */ | |
eea96d3f | 10423 | gas_assert (i.tm.opcode_modifier.vexvvvv |
0ff3b7d0 JB |
10424 | && i.tm.opcode_modifier.vexw); |
10425 | gas_assert (dot_insn () | |
10426 | || i.tm.operand_types[dest].bitfield.class == RegSIMD); | |
a683cc34 | 10427 | |
ecb96e55 JB |
10428 | /* Of the first two non-immediate operands the one with the template |
10429 | not allowing for a memory one is encoded in the immediate operand. */ | |
10430 | if (source == op) | |
10431 | reg_slot = source + 1; | |
48db9223 | 10432 | else |
ecb96e55 | 10433 | reg_slot = source++; |
48db9223 | 10434 | |
0ff3b7d0 JB |
10435 | if (!dot_insn ()) |
10436 | { | |
10437 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); | |
10438 | gas_assert (!(i.op[reg_slot].regs->reg_flags & RegVRex)); | |
10439 | } | |
10440 | else | |
10441 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class != ClassNone); | |
10442 | ||
a683cc34 | 10443 | if (i.imm_operands == 0) |
bed3d976 JB |
10444 | { |
10445 | /* When there is no immediate operand, generate an 8bit | |
10446 | immediate operand to encode the first operand. */ | |
10447 | exp = &im_expressions[i.imm_operands++]; | |
10448 | i.op[i.operands].imms = exp; | |
be1643ff | 10449 | i.types[i.operands].bitfield.imm8 = 1; |
bed3d976 JB |
10450 | i.operands++; |
10451 | ||
bed3d976 | 10452 | exp->X_op = O_constant; |
43234a1e | 10453 | } |
922d8de8 | 10454 | else |
bed3d976 | 10455 | { |
9d3bf266 JB |
10456 | gas_assert (i.imm_operands == 1); |
10457 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
10458 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 10459 | |
9d3bf266 JB |
10460 | /* Turn on Imm8 again so that output_imm will generate it. */ |
10461 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 10462 | |
0ff3b7d0 | 10463 | exp = i.op[0].imms; |
bed3d976 | 10464 | } |
0ff3b7d0 | 10465 | exp->X_add_number |= register_number (i.op[reg_slot].regs) |
706ce984 | 10466 | << (3 + !(i.tm.opcode_modifier.evex |
e346d50a | 10467 | || i.encoding == encoding_evex)); |
c0f3af97 | 10468 | } |
f12dc422 | 10469 | |
f2a3a881 | 10470 | switch (i.tm.opcode_modifier.vexvvvv) |
3083f376 | 10471 | { |
0820c9f5 CL |
10472 | /* VEX.vvvv encodes the last source register operand. */ |
10473 | case VexVVVV_SRC2: | |
10474 | if (source != op) | |
10475 | { | |
10476 | v = source++; | |
10477 | break; | |
10478 | } | |
10479 | /* For vprot*, vpshl*, and vpsha*, XOP.W controls the swapping of src1 | |
10480 | and src2, and it requires fall through when the operands are swapped. | |
10481 | */ | |
10482 | /* Fall through. */ | |
f2a3a881 CL |
10483 | /* VEX.vvvv encodes the first source register operand. */ |
10484 | case VexVVVV_SRC1: | |
10485 | v = dest - 1; | |
10486 | break; | |
10487 | /* VEX.vvvv encodes the destination register operand. */ | |
10488 | case VexVVVV_DST: | |
10489 | v = dest--; | |
10490 | break; | |
10491 | default: | |
10492 | v = ~0; | |
10493 | break; | |
10494 | } | |
10495 | ||
c8866e3e CL |
10496 | if (dest == source) |
10497 | dest = ~0; | |
10498 | ||
ecb96e55 | 10499 | gas_assert (source < dest); |
29b0f896 | 10500 | |
ecb96e55 JB |
10501 | if (v < MAX_OPERANDS) |
10502 | { | |
10503 | gas_assert (i.tm.opcode_modifier.vexvvvv); | |
10504 | i.vex.register_specifier = i.op[v].regs; | |
29b0f896 | 10505 | } |
c0f3af97 | 10506 | |
ecb96e55 JB |
10507 | if (op < i.operands) |
10508 | { | |
29b0f896 AM |
10509 | if (i.mem_operands) |
10510 | { | |
10511 | unsigned int fake_zero_displacement = 0; | |
4eed87de | 10512 | |
ecb96e55 | 10513 | gas_assert (i.flags[op] & Operand_Mem); |
29b0f896 | 10514 | |
63112cd6 | 10515 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 10516 | { |
260cd341 LC |
10517 | /* The index register of VSIB shouldn't be RegIZ. */ |
10518 | if (i.tm.opcode_modifier.sib != SIBMEM | |
10519 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
10520 | abort (); |
10521 | ||
10522 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
10523 | if (!i.base_reg) | |
10524 | { | |
10525 | i.sib.base = NO_BASE_REGISTER; | |
10526 | i.sib.scale = i.log2_scale_factor; | |
2f2be86b | 10527 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 10528 | i.types[op].bitfield.disp32 = 1; |
6c30d220 | 10529 | } |
260cd341 LC |
10530 | |
10531 | /* Since the mandatory SIB always has index register, so | |
10532 | the code logic remains unchanged. The non-mandatory SIB | |
10533 | without index register is allowed and will be handled | |
10534 | later. */ | |
10535 | if (i.index_reg) | |
10536 | { | |
10537 | if (i.index_reg->reg_num == RegIZ) | |
10538 | i.sib.index = NO_INDEX_REGISTER; | |
10539 | else | |
10540 | i.sib.index = i.index_reg->reg_num; | |
5b7c81bd | 10541 | set_rex_vrex (i.index_reg, REX_X, false); |
260cd341 | 10542 | } |
6c30d220 L |
10543 | } |
10544 | ||
5e042380 | 10545 | default_seg = reg_ds; |
29b0f896 AM |
10546 | |
10547 | if (i.base_reg == 0) | |
10548 | { | |
10549 | i.rm.mode = 0; | |
10550 | if (!i.disp_operands) | |
9bb129e8 | 10551 | fake_zero_displacement = 1; |
29b0f896 AM |
10552 | if (i.index_reg == 0) |
10553 | { | |
260cd341 LC |
10554 | /* Both check for VSIB and mandatory non-vector SIB. */ |
10555 | gas_assert (!i.tm.opcode_modifier.sib | |
10556 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 10557 | /* Operand is just <disp> */ |
2f2be86b | 10558 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
20f0a1fc | 10559 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
10560 | { |
10561 | /* 64bit mode overwrites the 32bit absolute | |
10562 | addressing by RIP relative addressing and | |
10563 | absolute addressing is encoded by one of the | |
10564 | redundant SIB forms. */ | |
10565 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
10566 | i.sib.base = NO_BASE_REGISTER; | |
10567 | i.sib.index = NO_INDEX_REGISTER; | |
a775efc8 | 10568 | i.types[op].bitfield.disp32 = 1; |
20f0a1fc | 10569 | } |
fc225355 L |
10570 | else if ((flag_code == CODE_16BIT) |
10571 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
10572 | { |
10573 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2f2be86b | 10574 | i.types[op].bitfield.disp16 = 1; |
20f0a1fc NC |
10575 | } |
10576 | else | |
10577 | { | |
10578 | i.rm.regmem = NO_BASE_REGISTER; | |
2f2be86b | 10579 | i.types[op].bitfield.disp32 = 1; |
29b0f896 AM |
10580 | } |
10581 | } | |
63112cd6 | 10582 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 10583 | { |
6c30d220 | 10584 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 10585 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
10586 | i.sib.index = NO_INDEX_REGISTER; |
10587 | else | |
10588 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
10589 | i.sib.base = NO_BASE_REGISTER; |
10590 | i.sib.scale = i.log2_scale_factor; | |
10591 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2f2be86b | 10592 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 10593 | i.types[op].bitfield.disp32 = 1; |
80d61d8d | 10594 | set_rex_rex2 (i.index_reg, REX_X); |
29b0f896 AM |
10595 | } |
10596 | } | |
10597 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 10598 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 10599 | { |
63112cd6 | 10600 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 10601 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
10602 | i.types[op].bitfield.disp8 = 0; |
10603 | i.types[op].bitfield.disp16 = 0; | |
a775efc8 | 10604 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 10605 | i.types[op].bitfield.disp64 = 0; |
71903a11 | 10606 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
10607 | if (! i.disp_operands) |
10608 | fake_zero_displacement = 1; | |
29b0f896 | 10609 | } |
dc821c5f | 10610 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 10611 | { |
63112cd6 | 10612 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
10613 | switch (i.base_reg->reg_num) |
10614 | { | |
10615 | case 3: /* (%bx) */ | |
10616 | if (i.index_reg == 0) | |
10617 | i.rm.regmem = 7; | |
10618 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
10619 | i.rm.regmem = i.index_reg->reg_num - 6; | |
10620 | break; | |
10621 | case 5: /* (%bp) */ | |
5e042380 | 10622 | default_seg = reg_ss; |
29b0f896 AM |
10623 | if (i.index_reg == 0) |
10624 | { | |
10625 | i.rm.regmem = 6; | |
40fb9820 | 10626 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
10627 | { |
10628 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 10629 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
10630 | i.types[op].bitfield.disp16 = 1; |
10631 | else | |
10632 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 10633 | fake_zero_displacement = 1; |
29b0f896 AM |
10634 | } |
10635 | } | |
10636 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
10637 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
10638 | break; | |
10639 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
10640 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
10641 | } | |
41eb8e88 L |
10642 | if (!fake_zero_displacement |
10643 | && !i.disp_operands | |
10644 | && i.disp_encoding) | |
10645 | { | |
10646 | fake_zero_displacement = 1; | |
10647 | if (i.disp_encoding == disp_encoding_8bit) | |
10648 | i.types[op].bitfield.disp8 = 1; | |
10649 | else | |
10650 | i.types[op].bitfield.disp16 = 1; | |
10651 | } | |
29b0f896 AM |
10652 | i.rm.mode = mode_from_disp_size (i.types[op]); |
10653 | } | |
10654 | else /* i.base_reg and 32/64 bit mode */ | |
10655 | { | |
a9aabc23 | 10656 | if (operand_type_check (i.types[op], disp)) |
40fb9820 | 10657 | { |
73053c1f JB |
10658 | i.types[op].bitfield.disp16 = 0; |
10659 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 10660 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 10661 | } |
20f0a1fc | 10662 | |
63112cd6 | 10663 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 10664 | i.rm.regmem = i.base_reg->reg_num; |
80d61d8d | 10665 | set_rex_rex2 (i.base_reg, REX_B); |
29b0f896 AM |
10666 | i.sib.base = i.base_reg->reg_num; |
10667 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
10668 | complications. */ | |
848930b2 JB |
10669 | if (!(i.base_reg->reg_flags & RegRex) |
10670 | && (i.base_reg->reg_num == EBP_REG_NUM | |
10671 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
5e042380 | 10672 | default_seg = reg_ss; |
848930b2 | 10673 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 10674 | { |
848930b2 | 10675 | fake_zero_displacement = 1; |
1a02d6b0 L |
10676 | if (i.disp_encoding == disp_encoding_32bit) |
10677 | i.types[op].bitfield.disp32 = 1; | |
10678 | else | |
10679 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
10680 | } |
10681 | i.sib.scale = i.log2_scale_factor; | |
10682 | if (i.index_reg == 0) | |
10683 | { | |
260cd341 LC |
10684 | /* Only check for VSIB. */ |
10685 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
10686 | && i.tm.opcode_modifier.sib != VECSIB256 | |
10687 | && i.tm.opcode_modifier.sib != VECSIB512); | |
10688 | ||
29b0f896 AM |
10689 | /* <disp>(%esp) becomes two byte modrm with no index |
10690 | register. We've already stored the code for esp | |
10691 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
10692 | Any base register besides %esp will not use the | |
10693 | extra modrm byte. */ | |
10694 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 10695 | } |
63112cd6 | 10696 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 10697 | { |
e968fc9b | 10698 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
10699 | i.sib.index = NO_INDEX_REGISTER; |
10700 | else | |
10701 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 | 10702 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
80d61d8d | 10703 | set_rex_rex2 (i.index_reg, REX_X); |
29b0f896 | 10704 | } |
67a4f2b7 AO |
10705 | |
10706 | if (i.disp_operands | |
10707 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
10708 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
10709 | i.rm.mode = 0; | |
10710 | else | |
a501d77e L |
10711 | { |
10712 | if (!fake_zero_displacement | |
10713 | && !i.disp_operands | |
10714 | && i.disp_encoding) | |
10715 | { | |
10716 | fake_zero_displacement = 1; | |
10717 | if (i.disp_encoding == disp_encoding_8bit) | |
10718 | i.types[op].bitfield.disp8 = 1; | |
10719 | else | |
10720 | i.types[op].bitfield.disp32 = 1; | |
10721 | } | |
10722 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
10723 | } | |
29b0f896 | 10724 | } |
252b5132 | 10725 | |
29b0f896 AM |
10726 | if (fake_zero_displacement) |
10727 | { | |
10728 | /* Fakes a zero displacement assuming that i.types[op] | |
10729 | holds the correct displacement size. */ | |
10730 | expressionS *exp; | |
10731 | ||
9c2799c2 | 10732 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
10733 | exp = &disp_expressions[i.disp_operands++]; |
10734 | i.op[op].disps = exp; | |
10735 | exp->X_op = O_constant; | |
10736 | exp->X_add_number = 0; | |
10737 | exp->X_add_symbol = (symbolS *) 0; | |
10738 | exp->X_op_symbol = (symbolS *) 0; | |
10739 | } | |
10740 | } | |
ecb96e55 JB |
10741 | else |
10742 | { | |
10743 | i.rm.mode = 3; | |
10744 | i.rm.regmem = i.op[op].regs->reg_num; | |
10745 | set_rex_vrex (i.op[op].regs, REX_B, false); | |
10746 | } | |
252b5132 | 10747 | |
ecb96e55 JB |
10748 | if (op == dest) |
10749 | dest = ~0; | |
10750 | if (op == source) | |
10751 | source = ~0; | |
10752 | } | |
10753 | else | |
10754 | { | |
10755 | i.rm.mode = 3; | |
10756 | if (!i.tm.opcode_modifier.regmem) | |
f88c9eb0 | 10757 | { |
ecb96e55 JB |
10758 | gas_assert (source < MAX_OPERANDS); |
10759 | i.rm.regmem = i.op[source].regs->reg_num; | |
10760 | set_rex_vrex (i.op[source].regs, REX_B, | |
10761 | dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx); | |
10762 | source = ~0; | |
f88c9eb0 | 10763 | } |
ecb96e55 | 10764 | else |
29b0f896 | 10765 | { |
ecb96e55 JB |
10766 | gas_assert (dest < MAX_OPERANDS); |
10767 | i.rm.regmem = i.op[dest].regs->reg_num; | |
10768 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); | |
10769 | dest = ~0; | |
29b0f896 | 10770 | } |
ecb96e55 | 10771 | } |
252b5132 | 10772 | |
ecb96e55 JB |
10773 | /* Fill in i.rm.reg field with extension opcode (if any) or the |
10774 | appropriate register. */ | |
10775 | if (i.tm.extension_opcode != None) | |
10776 | i.rm.reg = i.tm.extension_opcode; | |
10777 | else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS) | |
10778 | { | |
10779 | i.rm.reg = i.op[dest].regs->reg_num; | |
10780 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); | |
10781 | } | |
10782 | else | |
10783 | { | |
10784 | gas_assert (source < MAX_OPERANDS); | |
10785 | i.rm.reg = i.op[source].regs->reg_num; | |
10786 | set_rex_vrex (i.op[source].regs, REX_R, false); | |
29b0f896 | 10787 | } |
ecb96e55 JB |
10788 | |
10789 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) | |
10790 | { | |
10791 | gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR); | |
10792 | i.rex &= ~REX_R; | |
10793 | add_prefix (LOCK_PREFIX_OPCODE); | |
10794 | } | |
10795 | ||
29b0f896 AM |
10796 | return default_seg; |
10797 | } | |
252b5132 | 10798 | |
48ef937e JB |
10799 | static INLINE void |
10800 | frag_opcode_byte (unsigned char byte) | |
10801 | { | |
10802 | if (now_seg != absolute_section) | |
10803 | FRAG_APPEND_1_CHAR (byte); | |
10804 | else | |
10805 | ++abs_section_offset; | |
10806 | } | |
10807 | ||
376cd056 JB |
10808 | static unsigned int |
10809 | flip_code16 (unsigned int code16) | |
10810 | { | |
10811 | gas_assert (i.tm.operands == 1); | |
10812 | ||
10813 | return !(i.prefix[REX_PREFIX] & REX_W) | |
10814 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
376cd056 JB |
10815 | : i.tm.operand_types[0].bitfield.disp16) |
10816 | ? CODE16 : 0; | |
10817 | } | |
10818 | ||
29b0f896 | 10819 | static void |
e3bb37b5 | 10820 | output_branch (void) |
29b0f896 AM |
10821 | { |
10822 | char *p; | |
f8a5c266 | 10823 | int size; |
29b0f896 AM |
10824 | int code16; |
10825 | int prefix; | |
10826 | relax_substateT subtype; | |
10827 | symbolS *sym; | |
10828 | offsetT off; | |
10829 | ||
48ef937e JB |
10830 | if (now_seg == absolute_section) |
10831 | { | |
10832 | as_bad (_("relaxable branches not supported in absolute section")); | |
10833 | return; | |
10834 | } | |
10835 | ||
f8a5c266 | 10836 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
1a42a9fe | 10837 | size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL; |
29b0f896 AM |
10838 | |
10839 | prefix = 0; | |
10840 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 10841 | { |
29b0f896 AM |
10842 | prefix = 1; |
10843 | i.prefixes -= 1; | |
376cd056 | 10844 | code16 ^= flip_code16(code16); |
252b5132 | 10845 | } |
29b0f896 AM |
10846 | /* Pentium4 branch hints. */ |
10847 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
10848 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 10849 | { |
29b0f896 AM |
10850 | prefix++; |
10851 | i.prefixes--; | |
10852 | } | |
10853 | if (i.prefix[REX_PREFIX] != 0) | |
10854 | { | |
10855 | prefix++; | |
10856 | i.prefixes--; | |
2f66722d AM |
10857 | } |
10858 | ||
7e8b059b L |
10859 | /* BND prefixed jump. */ |
10860 | if (i.prefix[BND_PREFIX] != 0) | |
10861 | { | |
6cb0a70e JB |
10862 | prefix++; |
10863 | i.prefixes--; | |
7e8b059b L |
10864 | } |
10865 | ||
f2810fe0 | 10866 | if (i.prefixes != 0) |
76d3f746 | 10867 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
29b0f896 AM |
10868 | |
10869 | /* It's always a symbol; End frag & setup for relax. | |
10870 | Make sure there is enough room in this frag for the largest | |
10871 | instruction we may generate in md_convert_frag. This is 2 | |
10872 | bytes for the opcode and room for the prefix and largest | |
10873 | displacement. */ | |
10874 | frag_grow (prefix + 2 + 4); | |
10875 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
10876 | p = frag_more (prefix + 1); | |
10877 | if (i.prefix[DATA_PREFIX] != 0) | |
10878 | *p++ = DATA_PREFIX_OPCODE; | |
10879 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
10880 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
10881 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
10882 | if (i.prefix[BND_PREFIX] != 0) |
10883 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
10884 | if (i.prefix[REX_PREFIX] != 0) |
10885 | *p++ = i.prefix[REX_PREFIX]; | |
10886 | *p = i.tm.base_opcode; | |
10887 | ||
10888 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 10889 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 10890 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 10891 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 10892 | else |
f8a5c266 | 10893 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 10894 | subtype |= code16; |
3e73aa7c | 10895 | |
29b0f896 AM |
10896 | sym = i.op[0].disps->X_add_symbol; |
10897 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 10898 | |
29b0f896 AM |
10899 | if (i.op[0].disps->X_op != O_constant |
10900 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 10901 | { |
29b0f896 AM |
10902 | /* Handle complex expressions. */ |
10903 | sym = make_expr_symbol (i.op[0].disps); | |
10904 | off = 0; | |
10905 | } | |
3e73aa7c | 10906 | |
29b0f896 AM |
10907 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
10908 | Pass reloc in fr_var. */ | |
d258b828 | 10909 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 10910 | } |
3e73aa7c | 10911 | |
bd7ab16b L |
10912 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10913 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
10914 | symbol S. */ | |
10915 | ||
5b7c81bd | 10916 | static bool |
bd7ab16b L |
10917 | need_plt32_p (symbolS *s) |
10918 | { | |
10919 | /* PLT32 relocation is ELF only. */ | |
10920 | if (!IS_ELF) | |
5b7c81bd | 10921 | return false; |
bd7ab16b | 10922 | |
a5def729 RO |
10923 | #ifdef TE_SOLARIS |
10924 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
10925 | krtld support it. */ | |
5b7c81bd | 10926 | return false; |
a5def729 RO |
10927 | #endif |
10928 | ||
bd7ab16b L |
10929 | /* Since there is no need to prepare for PLT branch on x86-64, we |
10930 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
10931 | be used as a marker for 32-bit PC-relative branches. */ | |
10932 | if (!object_64bit) | |
5b7c81bd | 10933 | return false; |
bd7ab16b | 10934 | |
44365e88 | 10935 | if (s == NULL) |
5b7c81bd | 10936 | return false; |
44365e88 | 10937 | |
bd7ab16b L |
10938 | /* Weak or undefined symbol need PLT32 relocation. */ |
10939 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
5b7c81bd | 10940 | return true; |
bd7ab16b L |
10941 | |
10942 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
10943 | if (! S_IS_EXTERNAL (s)) | |
5b7c81bd | 10944 | return false; |
bd7ab16b L |
10945 | |
10946 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
10947 | non-default visibilities are treated as normal global symbol | |
10948 | so that PLT32 relocation can be used as a marker for 32-bit | |
10949 | PC-relative branches. It is useful for linker relaxation. */ | |
5b7c81bd | 10950 | return true; |
bd7ab16b L |
10951 | } |
10952 | #endif | |
10953 | ||
29b0f896 | 10954 | static void |
e3bb37b5 | 10955 | output_jump (void) |
29b0f896 AM |
10956 | { |
10957 | char *p; | |
10958 | int size; | |
3e02c1cc | 10959 | fixS *fixP; |
bd7ab16b | 10960 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 10961 | |
0cfa3eb3 | 10962 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
10963 | { |
10964 | /* This is a loop or jecxz type instruction. */ | |
10965 | size = 1; | |
10966 | if (i.prefix[ADDR_PREFIX] != 0) | |
10967 | { | |
48ef937e | 10968 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
10969 | i.prefixes -= 1; |
10970 | } | |
10971 | /* Pentium4 branch hints. */ | |
10972 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
10973 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
10974 | { | |
48ef937e | 10975 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 10976 | i.prefixes--; |
3e73aa7c JH |
10977 | } |
10978 | } | |
29b0f896 AM |
10979 | else |
10980 | { | |
10981 | int code16; | |
3e73aa7c | 10982 | |
29b0f896 AM |
10983 | code16 = 0; |
10984 | if (flag_code == CODE_16BIT) | |
10985 | code16 = CODE16; | |
3e73aa7c | 10986 | |
29b0f896 AM |
10987 | if (i.prefix[DATA_PREFIX] != 0) |
10988 | { | |
48ef937e | 10989 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 10990 | i.prefixes -= 1; |
376cd056 | 10991 | code16 ^= flip_code16(code16); |
29b0f896 | 10992 | } |
252b5132 | 10993 | |
29b0f896 AM |
10994 | size = 4; |
10995 | if (code16) | |
10996 | size = 2; | |
10997 | } | |
9fcc94b6 | 10998 | |
6cb0a70e JB |
10999 | /* BND prefixed jump. */ |
11000 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 11001 | { |
48ef937e | 11002 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
11003 | i.prefixes -= 1; |
11004 | } | |
252b5132 | 11005 | |
6cb0a70e | 11006 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 11007 | { |
48ef937e | 11008 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
11009 | i.prefixes -= 1; |
11010 | } | |
11011 | ||
f2810fe0 | 11012 | if (i.prefixes != 0) |
76d3f746 | 11013 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
e0890092 | 11014 | |
48ef937e JB |
11015 | if (now_seg == absolute_section) |
11016 | { | |
9a182d04 | 11017 | abs_section_offset += i.opcode_length + size; |
48ef937e JB |
11018 | return; |
11019 | } | |
11020 | ||
9a182d04 JB |
11021 | p = frag_more (i.opcode_length + size); |
11022 | switch (i.opcode_length) | |
42164a71 L |
11023 | { |
11024 | case 2: | |
11025 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 11026 | /* Fall through. */ |
42164a71 L |
11027 | case 1: |
11028 | *p++ = i.tm.base_opcode; | |
11029 | break; | |
11030 | default: | |
11031 | abort (); | |
11032 | } | |
e0890092 | 11033 | |
bd7ab16b | 11034 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
11035 | if (flag_code == CODE_64BIT && size == 4 |
11036 | && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0 | |
bd7ab16b L |
11037 | && need_plt32_p (i.op[0].disps->X_add_symbol)) |
11038 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
11039 | #endif | |
11040 | ||
11041 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
11042 | ||
3e02c1cc | 11043 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 11044 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc | 11045 | |
eb19308f JB |
11046 | /* All jumps handled here are signed, but don't unconditionally use a |
11047 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
11048 | around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN) | |
11049 | respectively. */ | |
11050 | switch (size) | |
11051 | { | |
11052 | case 1: | |
11053 | fixP->fx_signed = 1; | |
11054 | break; | |
11055 | ||
11056 | case 2: | |
7fc69528 | 11057 | if (i.tm.mnem_off == MN_xbegin) |
eb19308f JB |
11058 | fixP->fx_signed = 1; |
11059 | break; | |
11060 | ||
11061 | case 4: | |
11062 | if (flag_code == CODE_64BIT) | |
11063 | fixP->fx_signed = 1; | |
11064 | break; | |
11065 | } | |
29b0f896 | 11066 | } |
e0890092 | 11067 | |
29b0f896 | 11068 | static void |
e3bb37b5 | 11069 | output_interseg_jump (void) |
29b0f896 AM |
11070 | { |
11071 | char *p; | |
11072 | int size; | |
11073 | int prefix; | |
11074 | int code16; | |
252b5132 | 11075 | |
29b0f896 AM |
11076 | code16 = 0; |
11077 | if (flag_code == CODE_16BIT) | |
11078 | code16 = CODE16; | |
a217f122 | 11079 | |
29b0f896 AM |
11080 | prefix = 0; |
11081 | if (i.prefix[DATA_PREFIX] != 0) | |
11082 | { | |
11083 | prefix = 1; | |
11084 | i.prefixes -= 1; | |
11085 | code16 ^= CODE16; | |
11086 | } | |
6cb0a70e JB |
11087 | |
11088 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 11089 | |
29b0f896 AM |
11090 | size = 4; |
11091 | if (code16) | |
11092 | size = 2; | |
252b5132 | 11093 | |
f2810fe0 | 11094 | if (i.prefixes != 0) |
76d3f746 | 11095 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
252b5132 | 11096 | |
48ef937e JB |
11097 | if (now_seg == absolute_section) |
11098 | { | |
11099 | abs_section_offset += prefix + 1 + 2 + size; | |
11100 | return; | |
11101 | } | |
11102 | ||
29b0f896 AM |
11103 | /* 1 opcode; 2 segment; offset */ |
11104 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 11105 | |
29b0f896 AM |
11106 | if (i.prefix[DATA_PREFIX] != 0) |
11107 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 11108 | |
29b0f896 AM |
11109 | if (i.prefix[REX_PREFIX] != 0) |
11110 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 11111 | |
29b0f896 AM |
11112 | *p++ = i.tm.base_opcode; |
11113 | if (i.op[1].imms->X_op == O_constant) | |
11114 | { | |
11115 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 11116 | |
29b0f896 AM |
11117 | if (size == 2 |
11118 | && !fits_in_unsigned_word (n) | |
11119 | && !fits_in_signed_word (n)) | |
11120 | { | |
11121 | as_bad (_("16-bit jump out of range")); | |
11122 | return; | |
11123 | } | |
11124 | md_number_to_chars (p, n, size); | |
11125 | } | |
11126 | else | |
11127 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 11128 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
6d96a594 C |
11129 | |
11130 | p += size; | |
11131 | if (i.op[0].imms->X_op == O_constant) | |
11132 | md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2); | |
11133 | else | |
11134 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
11135 | i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0])); | |
29b0f896 | 11136 | } |
a217f122 | 11137 | |
b4a3a7b4 L |
11138 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11139 | void | |
11140 | x86_cleanup (void) | |
11141 | { | |
11142 | char *p; | |
11143 | asection *seg = now_seg; | |
11144 | subsegT subseg = now_subseg; | |
11145 | asection *sec; | |
11146 | unsigned int alignment, align_size_1; | |
11147 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
11148 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
11149 | unsigned int padding; | |
11150 | ||
1273b2f8 | 11151 | if (!IS_ELF || !x86_used_note) |
b4a3a7b4 L |
11152 | return; |
11153 | ||
b4a3a7b4 L |
11154 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
11155 | ||
11156 | /* The .note.gnu.property section layout: | |
11157 | ||
11158 | Field Length Contents | |
11159 | ---- ---- ---- | |
11160 | n_namsz 4 4 | |
11161 | n_descsz 4 The note descriptor size | |
11162 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
11163 | n_name 4 "GNU" | |
11164 | n_desc n_descsz The program property array | |
11165 | .... .... .... | |
11166 | */ | |
11167 | ||
11168 | /* Create the .note.gnu.property section. */ | |
11169 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 11170 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
11171 | (SEC_ALLOC |
11172 | | SEC_LOAD | |
11173 | | SEC_DATA | |
11174 | | SEC_HAS_CONTENTS | |
11175 | | SEC_READONLY)); | |
11176 | ||
11177 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
11178 | { | |
11179 | align_size_1 = 7; | |
11180 | alignment = 3; | |
11181 | } | |
11182 | else | |
11183 | { | |
11184 | align_size_1 = 3; | |
11185 | alignment = 2; | |
11186 | } | |
11187 | ||
fd361982 | 11188 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
11189 | elf_section_type (sec) = SHT_NOTE; |
11190 | ||
1273b2f8 L |
11191 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size |
11192 | + 4-byte data */ | |
11193 | isa_1_descsz_raw = 4 + 4 + 4; | |
11194 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
11195 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
b4a3a7b4 L |
11196 | |
11197 | feature_2_descsz_raw = isa_1_descsz; | |
11198 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
1273b2f8 | 11199 | + 4-byte data */ |
b4a3a7b4 L |
11200 | feature_2_descsz_raw += 4 + 4 + 4; |
11201 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
11202 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
11203 | & ~align_size_1); | |
11204 | ||
11205 | descsz = feature_2_descsz; | |
11206 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
11207 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
11208 | ||
11209 | /* Write n_namsz. */ | |
11210 | md_number_to_chars (p, (valueT) 4, 4); | |
11211 | ||
11212 | /* Write n_descsz. */ | |
11213 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
11214 | ||
11215 | /* Write n_type. */ | |
11216 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
11217 | ||
11218 | /* Write n_name. */ | |
11219 | memcpy (p + 4 * 3, "GNU", 4); | |
11220 | ||
1273b2f8 L |
11221 | /* Write 4-byte type. */ |
11222 | md_number_to_chars (p + 4 * 4, | |
11223 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
b4a3a7b4 | 11224 | |
1273b2f8 L |
11225 | /* Write 4-byte data size. */ |
11226 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
b4a3a7b4 | 11227 | |
1273b2f8 L |
11228 | /* Write 4-byte data. */ |
11229 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
b4a3a7b4 | 11230 | |
1273b2f8 L |
11231 | /* Zero out paddings. */ |
11232 | padding = isa_1_descsz - isa_1_descsz_raw; | |
11233 | if (padding) | |
11234 | memset (p + 4 * 7, 0, padding); | |
b4a3a7b4 L |
11235 | |
11236 | /* Write 4-byte type. */ | |
11237 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
11238 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
11239 | ||
11240 | /* Write 4-byte data size. */ | |
11241 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
11242 | ||
11243 | /* Write 4-byte data. */ | |
11244 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
11245 | (valueT) x86_feature_2_used, 4); | |
11246 | ||
11247 | /* Zero out paddings. */ | |
11248 | padding = feature_2_descsz - feature_2_descsz_raw; | |
11249 | if (padding) | |
11250 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
11251 | ||
11252 | /* We probably can't restore the current segment, for there likely | |
11253 | isn't one yet... */ | |
11254 | if (seg && subseg) | |
11255 | subseg_set (seg, subseg); | |
11256 | } | |
b52c4ee4 IB |
11257 | |
11258 | bool | |
11259 | x86_support_sframe_p (void) | |
11260 | { | |
3e3e792a | 11261 | /* At this time, SFrame stack trace is supported for AMD64 ABI only. */ |
b52c4ee4 IB |
11262 | return (x86_elf_abi == X86_64_ABI); |
11263 | } | |
11264 | ||
11265 | bool | |
11266 | x86_sframe_ra_tracking_p (void) | |
11267 | { | |
11268 | /* In AMD64, return address is always stored on the stack at a fixed offset | |
11269 | from the CFA (provided via x86_sframe_cfa_ra_offset ()). | |
11270 | Do not track explicitly via an SFrame Frame Row Entry. */ | |
11271 | return false; | |
11272 | } | |
11273 | ||
11274 | offsetT | |
11275 | x86_sframe_cfa_ra_offset (void) | |
11276 | { | |
11277 | gas_assert (x86_elf_abi == X86_64_ABI); | |
11278 | return (offsetT) -8; | |
11279 | } | |
11280 | ||
11281 | unsigned char | |
11282 | x86_sframe_get_abi_arch (void) | |
11283 | { | |
11284 | unsigned char sframe_abi_arch = 0; | |
11285 | ||
11286 | if (x86_support_sframe_p ()) | |
11287 | { | |
11288 | gas_assert (!target_big_endian); | |
11289 | sframe_abi_arch = SFRAME_ABI_AMD64_ENDIAN_LITTLE; | |
11290 | } | |
11291 | ||
11292 | return sframe_abi_arch; | |
11293 | } | |
11294 | ||
b4a3a7b4 L |
11295 | #endif |
11296 | ||
9c33702b JB |
11297 | static unsigned int |
11298 | encoding_length (const fragS *start_frag, offsetT start_off, | |
11299 | const char *frag_now_ptr) | |
11300 | { | |
11301 | unsigned int len = 0; | |
11302 | ||
11303 | if (start_frag != frag_now) | |
11304 | { | |
11305 | const fragS *fr = start_frag; | |
11306 | ||
11307 | do { | |
11308 | len += fr->fr_fix; | |
11309 | fr = fr->fr_next; | |
11310 | } while (fr && fr != frag_now); | |
11311 | } | |
11312 | ||
11313 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
11314 | } | |
11315 | ||
e379e5f3 | 11316 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
11317 | be macro-fused with conditional jumps. |
11318 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
11319 | or is one of the following format: | |
11320 | ||
11321 | cmp m, imm | |
11322 | add m, imm | |
11323 | sub m, imm | |
11324 | test m, imm | |
11325 | and m, imm | |
11326 | inc m | |
11327 | dec m | |
11328 | ||
11329 | it is unfusible. */ | |
e379e5f3 L |
11330 | |
11331 | static int | |
79d72f45 | 11332 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
11333 | { |
11334 | /* No RIP address. */ | |
11335 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
11336 | return 0; | |
11337 | ||
389d00a5 | 11338 | /* No opcodes outside of base encoding space. */ |
ddb62495 | 11339 | if (i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
11340 | return 0; |
11341 | ||
79d72f45 HL |
11342 | /* add, sub without add/sub m, imm. */ |
11343 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
11344 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
11345 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 11346 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 11347 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
11348 | { |
11349 | *mf_cmp_p = mf_cmp_alu_cmp; | |
11350 | return !(i.mem_operands && i.imm_operands); | |
11351 | } | |
e379e5f3 | 11352 | |
79d72f45 HL |
11353 | /* and without and m, imm. */ |
11354 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
11355 | || ((i.tm.base_opcode | 3) == 0x83 | |
11356 | && i.tm.extension_opcode == 0x4)) | |
11357 | { | |
11358 | *mf_cmp_p = mf_cmp_test_and; | |
11359 | return !(i.mem_operands && i.imm_operands); | |
11360 | } | |
11361 | ||
11362 | /* test without test m imm. */ | |
e379e5f3 L |
11363 | if ((i.tm.base_opcode | 1) == 0x85 |
11364 | || (i.tm.base_opcode | 1) == 0xa9 | |
11365 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
11366 | && i.tm.extension_opcode == 0)) |
11367 | { | |
11368 | *mf_cmp_p = mf_cmp_test_and; | |
11369 | return !(i.mem_operands && i.imm_operands); | |
11370 | } | |
11371 | ||
11372 | /* cmp without cmp m, imm. */ | |
11373 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
11374 | || ((i.tm.base_opcode | 3) == 0x83 |
11375 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
11376 | { |
11377 | *mf_cmp_p = mf_cmp_alu_cmp; | |
11378 | return !(i.mem_operands && i.imm_operands); | |
11379 | } | |
e379e5f3 | 11380 | |
79d72f45 | 11381 | /* inc, dec without inc/dec m. */ |
734dfd1c | 11382 | if ((is_cpu (&i.tm, CpuNo64) |
e379e5f3 L |
11383 | && (i.tm.base_opcode | 0xf) == 0x4f) |
11384 | || ((i.tm.base_opcode | 1) == 0xff | |
11385 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
11386 | { |
11387 | *mf_cmp_p = mf_cmp_incdec; | |
11388 | return !i.mem_operands; | |
11389 | } | |
e379e5f3 L |
11390 | |
11391 | return 0; | |
11392 | } | |
11393 | ||
11394 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
11395 | ||
11396 | static int | |
b5482fe5 JB |
11397 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind *mf_cmp_p, |
11398 | const struct last_insn *last_insn) | |
e379e5f3 L |
11399 | { |
11400 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
11401 | if (!align_branch_power | |
11402 | || now_seg == absolute_section | |
11403 | || !cpu_arch_flags.bitfield.cpui386 | |
11404 | || !(align_branch & align_branch_fused_bit)) | |
11405 | return 0; | |
11406 | ||
79d72f45 | 11407 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 | 11408 | { |
b5482fe5 | 11409 | if (last_insn->kind == last_insn_other) |
e379e5f3 L |
11410 | return 1; |
11411 | if (flag_debug) | |
b5482fe5 | 11412 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 11413 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 11414 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
11415 | } |
11416 | ||
11417 | return 0; | |
11418 | } | |
11419 | ||
11420 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
11421 | ||
11422 | static int | |
b5482fe5 | 11423 | add_branch_prefix_frag_p (const struct last_insn *last_insn) |
e379e5f3 L |
11424 | { |
11425 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
11426 | to PadLock instructions since they include prefixes in opcode. */ | |
11427 | if (!align_branch_power | |
11428 | || !align_branch_prefix_size | |
11429 | || now_seg == absolute_section | |
734dfd1c | 11430 | || is_cpu (&i.tm, CpuPadLock) |
e379e5f3 L |
11431 | || !cpu_arch_flags.bitfield.cpui386) |
11432 | return 0; | |
11433 | ||
11434 | /* Don't add prefix if it is a prefix or there is no operand in case | |
11435 | that segment prefix is special. */ | |
11436 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
11437 | return 0; | |
11438 | ||
b5482fe5 | 11439 | if (last_insn->kind == last_insn_other) |
e379e5f3 L |
11440 | return 1; |
11441 | ||
11442 | if (flag_debug) | |
b5482fe5 | 11443 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 11444 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 11445 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
11446 | |
11447 | return 0; | |
11448 | } | |
11449 | ||
11450 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
11451 | ||
11452 | static int | |
79d72f45 | 11453 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
b5482fe5 JB |
11454 | enum mf_jcc_kind *mf_jcc_p, |
11455 | const struct last_insn *last_insn) | |
e379e5f3 L |
11456 | { |
11457 | int add_padding; | |
11458 | ||
11459 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
11460 | if (!align_branch_power | |
11461 | || now_seg == absolute_section | |
389d00a5 | 11462 | || !cpu_arch_flags.bitfield.cpui386 |
ddb62495 | 11463 | || i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
11464 | return 0; |
11465 | ||
11466 | add_padding = 0; | |
11467 | ||
11468 | /* Check for jcc and direct jmp. */ | |
11469 | if (i.tm.opcode_modifier.jump == JUMP) | |
11470 | { | |
11471 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
11472 | { | |
11473 | *branch_p = align_branch_jmp; | |
11474 | add_padding = align_branch & align_branch_jmp_bit; | |
11475 | } | |
11476 | else | |
11477 | { | |
79d72f45 HL |
11478 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
11479 | igore the lowest bit. */ | |
11480 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
11481 | *branch_p = align_branch_jcc; |
11482 | if ((align_branch & align_branch_jcc_bit)) | |
11483 | add_padding = 1; | |
11484 | } | |
11485 | } | |
e379e5f3 L |
11486 | else if ((i.tm.base_opcode | 1) == 0xc3) |
11487 | { | |
11488 | /* Near ret. */ | |
11489 | *branch_p = align_branch_ret; | |
11490 | if ((align_branch & align_branch_ret_bit)) | |
11491 | add_padding = 1; | |
11492 | } | |
11493 | else | |
11494 | { | |
11495 | /* Check for indirect jmp, direct and indirect calls. */ | |
11496 | if (i.tm.base_opcode == 0xe8) | |
11497 | { | |
11498 | /* Direct call. */ | |
11499 | *branch_p = align_branch_call; | |
11500 | if ((align_branch & align_branch_call_bit)) | |
11501 | add_padding = 1; | |
11502 | } | |
11503 | else if (i.tm.base_opcode == 0xff | |
11504 | && (i.tm.extension_opcode == 2 | |
11505 | || i.tm.extension_opcode == 4)) | |
11506 | { | |
11507 | /* Indirect call and jmp. */ | |
11508 | *branch_p = align_branch_indirect; | |
11509 | if ((align_branch & align_branch_indirect_bit)) | |
11510 | add_padding = 1; | |
11511 | } | |
11512 | ||
11513 | if (add_padding | |
11514 | && i.disp_operands | |
11515 | && tls_get_addr | |
11516 | && (i.op[0].disps->X_op == O_symbol | |
11517 | || (i.op[0].disps->X_op == O_subtract | |
11518 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
11519 | { | |
11520 | symbolS *s = i.op[0].disps->X_add_symbol; | |
11521 | /* No padding to call to global or undefined tls_get_addr. */ | |
11522 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
11523 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
11524 | return 0; | |
11525 | } | |
11526 | } | |
11527 | ||
11528 | if (add_padding | |
b5482fe5 | 11529 | && last_insn->kind != last_insn_other) |
e379e5f3 L |
11530 | { |
11531 | if (flag_debug) | |
b5482fe5 | 11532 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 11533 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 11534 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
11535 | return 0; |
11536 | } | |
11537 | ||
11538 | return add_padding; | |
11539 | } | |
11540 | ||
29b0f896 | 11541 | static void |
b5482fe5 | 11542 | output_insn (const struct last_insn *last_insn) |
29b0f896 | 11543 | { |
2bbd9c25 JJ |
11544 | fragS *insn_start_frag; |
11545 | offsetT insn_start_off; | |
e379e5f3 L |
11546 | fragS *fragP = NULL; |
11547 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
11548 | /* The initializer is arbitrary just to avoid uninitialized error. |
11549 | it's actually either assigned in add_branch_padding_frag_p | |
11550 | or never be used. */ | |
11551 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 11552 | |
b4a3a7b4 | 11553 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 11554 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 | 11555 | { |
32930e4e | 11556 | if ((i.xstate & xstate_tmm) == xstate_tmm |
734dfd1c | 11557 | || is_cpu (&i.tm, CpuAMX_TILE)) |
32930e4e L |
11558 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; |
11559 | ||
734dfd1c JB |
11560 | if (is_cpu (&i.tm, Cpu8087) |
11561 | || is_cpu (&i.tm, Cpu287) | |
11562 | || is_cpu (&i.tm, Cpu387) | |
11563 | || is_cpu (&i.tm, Cpu687) | |
11564 | || is_cpu (&i.tm, CpuFISTTP)) | |
b4a3a7b4 | 11565 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; |
014d61ea | 11566 | |
921eafea | 11567 | if ((i.xstate & xstate_mmx) |
7fc69528 JB |
11568 | || i.tm.mnem_off == MN_emms |
11569 | || i.tm.mnem_off == MN_femms) | |
b4a3a7b4 | 11570 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
014d61ea | 11571 | |
32930e4e L |
11572 | if (i.index_reg) |
11573 | { | |
11574 | if (i.index_reg->reg_type.bitfield.zmmword) | |
11575 | i.xstate |= xstate_zmm; | |
11576 | else if (i.index_reg->reg_type.bitfield.ymmword) | |
11577 | i.xstate |= xstate_ymm; | |
11578 | else if (i.index_reg->reg_type.bitfield.xmmword) | |
11579 | i.xstate |= xstate_xmm; | |
11580 | } | |
014d61ea JB |
11581 | |
11582 | /* vzeroall / vzeroupper */ | |
734dfd1c | 11583 | if (i.tm.base_opcode == 0x77 && is_cpu (&i.tm, CpuAVX)) |
014d61ea JB |
11584 | i.xstate |= xstate_ymm; |
11585 | ||
c4694f17 | 11586 | if ((i.xstate & xstate_xmm) |
389d00a5 JB |
11587 | /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */ |
11588 | || (i.tm.base_opcode == 0xae | |
734dfd1c JB |
11589 | && (is_cpu (&i.tm, CpuSSE) |
11590 | || is_cpu (&i.tm, CpuAVX))) | |
11591 | || is_cpu (&i.tm, CpuWideKL) | |
11592 | || is_cpu (&i.tm, CpuKL)) | |
b4a3a7b4 | 11593 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
014d61ea | 11594 | |
921eafea | 11595 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 11596 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 11597 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 | 11598 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
6225c532 | 11599 | if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask) |
32930e4e | 11600 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK; |
734dfd1c | 11601 | if (is_cpu (&i.tm, CpuFXSR)) |
b4a3a7b4 | 11602 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; |
734dfd1c | 11603 | if (is_cpu (&i.tm, CpuXsave)) |
b4a3a7b4 | 11604 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; |
734dfd1c | 11605 | if (is_cpu (&i.tm, CpuXsaveopt)) |
b4a3a7b4 | 11606 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; |
734dfd1c | 11607 | if (is_cpu (&i.tm, CpuXSAVEC)) |
b4a3a7b4 | 11608 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; |
b0ab0693 L |
11609 | |
11610 | if (x86_feature_2_used | |
734dfd1c JB |
11611 | || is_cpu (&i.tm, CpuCMOV) |
11612 | || is_cpu (&i.tm, CpuSYSCALL) | |
7fc69528 | 11613 | || i.tm.mnem_off == MN_cmpxchg8b) |
b0ab0693 | 11614 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; |
734dfd1c JB |
11615 | if (is_cpu (&i.tm, CpuSSE3) |
11616 | || is_cpu (&i.tm, CpuSSSE3) | |
11617 | || is_cpu (&i.tm, CpuSSE4_1) | |
11618 | || is_cpu (&i.tm, CpuSSE4_2) | |
11619 | || is_cpu (&i.tm, CpuCX16) | |
11620 | || is_cpu (&i.tm, CpuPOPCNT) | |
b0ab0693 L |
11621 | /* LAHF-SAHF insns in 64-bit mode. */ |
11622 | || (flag_code == CODE_64BIT | |
35648716 | 11623 | && (i.tm.base_opcode | 1) == 0x9f |
ddb62495 | 11624 | && i.tm.opcode_space == SPACE_BASE)) |
b0ab0693 | 11625 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2; |
734dfd1c JB |
11626 | if (is_cpu (&i.tm, CpuAVX) |
11627 | || is_cpu (&i.tm, CpuAVX2) | |
a9860005 JB |
11628 | /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ, |
11629 | XOP, FMA4, LPW, TBM, and AMX. */ | |
b0ab0693 | 11630 | || (i.tm.opcode_modifier.vex |
734dfd1c JB |
11631 | && !is_cpu (&i.tm, CpuAVX512F) |
11632 | && !is_cpu (&i.tm, CpuAVX512BW) | |
11633 | && !is_cpu (&i.tm, CpuAVX512DQ) | |
11634 | && !is_cpu (&i.tm, CpuXOP) | |
11635 | && !is_cpu (&i.tm, CpuFMA4) | |
11636 | && !is_cpu (&i.tm, CpuLWP) | |
11637 | && !is_cpu (&i.tm, CpuTBM) | |
b0ab0693 | 11638 | && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM)) |
734dfd1c JB |
11639 | || is_cpu (&i.tm, CpuF16C) |
11640 | || is_cpu (&i.tm, CpuFMA) | |
11641 | || is_cpu (&i.tm, CpuLZCNT) | |
11642 | || is_cpu (&i.tm, CpuMovbe) | |
11643 | || is_cpu (&i.tm, CpuXSAVES) | |
b0ab0693 L |
11644 | || (x86_feature_2_used |
11645 | & (GNU_PROPERTY_X86_FEATURE_2_XSAVE | |
11646 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT | |
11647 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0) | |
11648 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3; | |
734dfd1c JB |
11649 | if (is_cpu (&i.tm, CpuAVX512F) |
11650 | || is_cpu (&i.tm, CpuAVX512BW) | |
11651 | || is_cpu (&i.tm, CpuAVX512DQ) | |
11652 | || is_cpu (&i.tm, CpuAVX512VL) | |
a9860005 JB |
11653 | /* Any EVEX encoded insns except for AVX512ER, AVX512PF, |
11654 | AVX512-4FMAPS, and AVX512-4VNNIW. */ | |
b0ab0693 | 11655 | || (i.tm.opcode_modifier.evex |
734dfd1c JB |
11656 | && !is_cpu (&i.tm, CpuAVX512ER) |
11657 | && !is_cpu (&i.tm, CpuAVX512PF) | |
11658 | && !is_cpu (&i.tm, CpuAVX512_4FMAPS) | |
11659 | && !is_cpu (&i.tm, CpuAVX512_4VNNIW))) | |
b0ab0693 | 11660 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4; |
b4a3a7b4 L |
11661 | } |
11662 | #endif | |
11663 | ||
29b0f896 AM |
11664 | /* Tie dwarf2 debug info to the address at the start of the insn. |
11665 | We can't do this after the insn has been output as the current | |
11666 | frag may have been closed off. eg. by frag_var. */ | |
11667 | dwarf2_emit_insn (0); | |
11668 | ||
2bbd9c25 JJ |
11669 | insn_start_frag = frag_now; |
11670 | insn_start_off = frag_now_fix (); | |
11671 | ||
b5482fe5 | 11672 | if (add_branch_padding_frag_p (&branch, &mf_jcc, last_insn)) |
e379e5f3 L |
11673 | { |
11674 | char *p; | |
11675 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
11676 | unsigned int max_branch_padding_size = 14; | |
11677 | ||
11678 | /* Align section to boundary. */ | |
11679 | record_alignment (now_seg, align_branch_power); | |
11680 | ||
11681 | /* Make room for padding. */ | |
11682 | frag_grow (max_branch_padding_size); | |
11683 | ||
11684 | /* Start of the padding. */ | |
11685 | p = frag_more (0); | |
11686 | ||
11687 | fragP = frag_now; | |
11688 | ||
11689 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
11690 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
11691 | NULL, 0, p); | |
11692 | ||
79d72f45 | 11693 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
11694 | fragP->tc_frag_data.branch_type = branch; |
11695 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
11696 | } | |
11697 | ||
d59a54c2 JB |
11698 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT) |
11699 | && !pre_386_16bit_warned) | |
11700 | { | |
11701 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
11702 | pre_386_16bit_warned = true; | |
11703 | } | |
11704 | ||
29b0f896 | 11705 | /* Output jumps. */ |
0cfa3eb3 | 11706 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 11707 | output_branch (); |
0cfa3eb3 JB |
11708 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
11709 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 11710 | output_jump (); |
0cfa3eb3 | 11711 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
11712 | output_interseg_jump (); |
11713 | else | |
11714 | { | |
11715 | /* Output normal instructions here. */ | |
11716 | char *p; | |
11717 | unsigned char *q; | |
47465058 | 11718 | unsigned int j; |
79d72f45 | 11719 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 11720 | |
e4e00185 | 11721 | if (avoid_fence |
389d00a5 JB |
11722 | && (i.tm.base_opcode == 0xaee8 |
11723 | || i.tm.base_opcode == 0xaef0 | |
11724 | || i.tm.base_opcode == 0xaef8)) | |
48ef937e JB |
11725 | { |
11726 | /* Encode lfence, mfence, and sfence as | |
11727 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
47f4115a | 11728 | if (flag_code == CODE_16BIT) |
76d3f746 | 11729 | as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i.tm)); |
47f4115a JB |
11730 | else if (omit_lock_prefix) |
11731 | as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"), | |
76d3f746 | 11732 | insn_name (&i.tm)); |
47f4115a | 11733 | else if (now_seg != absolute_section) |
48ef937e JB |
11734 | { |
11735 | offsetT val = 0x240483f0ULL; | |
11736 | ||
11737 | p = frag_more (5); | |
11738 | md_number_to_chars (p, val, 5); | |
11739 | } | |
11740 | else | |
11741 | abs_section_offset += 5; | |
11742 | return; | |
11743 | } | |
e4e00185 | 11744 | |
d022bddd IT |
11745 | /* Some processors fail on LOCK prefix. This options makes |
11746 | assembler ignore LOCK prefix and serves as a workaround. */ | |
11747 | if (omit_lock_prefix) | |
11748 | { | |
35648716 JB |
11749 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE |
11750 | && i.tm.opcode_modifier.isprefix) | |
d022bddd IT |
11751 | return; |
11752 | i.prefix[LOCK_PREFIX] = 0; | |
11753 | } | |
11754 | ||
e379e5f3 L |
11755 | if (branch) |
11756 | /* Skip if this is a branch. */ | |
11757 | ; | |
b5482fe5 | 11758 | else if (add_fused_jcc_padding_frag_p (&mf_cmp, last_insn)) |
e379e5f3 L |
11759 | { |
11760 | /* Make room for padding. */ | |
11761 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
11762 | p = frag_more (0); | |
11763 | ||
11764 | fragP = frag_now; | |
11765 | ||
11766 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
11767 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
11768 | NULL, 0, p); | |
11769 | ||
79d72f45 | 11770 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
11771 | fragP->tc_frag_data.branch_type = align_branch_fused; |
11772 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
11773 | } | |
b5482fe5 | 11774 | else if (add_branch_prefix_frag_p (last_insn)) |
e379e5f3 L |
11775 | { |
11776 | unsigned int max_prefix_size = align_branch_prefix_size; | |
11777 | ||
11778 | /* Make room for padding. */ | |
11779 | frag_grow (max_prefix_size); | |
11780 | p = frag_more (0); | |
11781 | ||
11782 | fragP = frag_now; | |
11783 | ||
11784 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
11785 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
11786 | NULL, 0, p); | |
11787 | ||
11788 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
11789 | } | |
11790 | ||
43234a1e L |
11791 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
11792 | don't need the explicit prefix. */ | |
cf665fee | 11793 | if (!is_any_vex_encoding (&i.tm)) |
bc4bd9ab | 11794 | { |
7b47a312 | 11795 | switch (i.tm.opcode_modifier.opcodeprefix) |
bc4bd9ab | 11796 | { |
7b47a312 L |
11797 | case PREFIX_0X66: |
11798 | add_prefix (0x66); | |
11799 | break; | |
11800 | case PREFIX_0XF2: | |
11801 | add_prefix (0xf2); | |
11802 | break; | |
11803 | case PREFIX_0XF3: | |
734dfd1c | 11804 | if (!is_cpu (&i.tm, CpuPadLock) |
8b65b895 L |
11805 | || (i.prefix[REP_PREFIX] != 0xf3)) |
11806 | add_prefix (0xf3); | |
c0f3af97 | 11807 | break; |
7b47a312 | 11808 | case PREFIX_NONE: |
9a182d04 | 11809 | switch (i.opcode_length) |
c0f3af97 | 11810 | { |
7b47a312 | 11811 | case 2: |
7b47a312 | 11812 | break; |
9a182d04 | 11813 | case 1: |
7b47a312 | 11814 | /* Check for pseudo prefixes. */ |
9a182d04 JB |
11815 | if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode) |
11816 | break; | |
7b47a312 L |
11817 | as_bad_where (insn_start_frag->fr_file, |
11818 | insn_start_frag->fr_line, | |
11819 | _("pseudo prefix without instruction")); | |
11820 | return; | |
11821 | default: | |
11822 | abort (); | |
4dffcebc | 11823 | } |
c0f3af97 | 11824 | break; |
c0f3af97 L |
11825 | default: |
11826 | abort (); | |
bc4bd9ab | 11827 | } |
c0f3af97 | 11828 | |
6d19a37a | 11829 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
11830 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
11831 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
11832 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
11833 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
11834 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 | 11835 | if (x86_elf_abi == X86_64_X32_ABI |
a533c8df | 11836 | && !is_apx_rex2_encoding () |
cf61b747 | 11837 | && i.operands == 2 |
14470f07 L |
11838 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
11839 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
11840 | && i.prefix[REX_PREFIX] == 0) |
11841 | add_prefix (REX_OPCODE); | |
6d19a37a | 11842 | #endif |
cf61b747 | 11843 | |
c0f3af97 L |
11844 | /* The prefix bytes. */ |
11845 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
11846 | if (*q) | |
48ef937e | 11847 | frag_opcode_byte (*q); |
80d61d8d CL |
11848 | |
11849 | if (is_apx_rex2_encoding ()) | |
11850 | { | |
11851 | frag_opcode_byte (i.vex.bytes[0]); | |
11852 | frag_opcode_byte (i.vex.bytes[1]); | |
11853 | } | |
0f10071e | 11854 | } |
ae5c1c7b | 11855 | else |
c0f3af97 L |
11856 | { |
11857 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
11858 | if (*q) | |
11859 | switch (j) | |
11860 | { | |
c0f3af97 L |
11861 | case SEG_PREFIX: |
11862 | case ADDR_PREFIX: | |
48ef937e | 11863 | frag_opcode_byte (*q); |
c0f3af97 L |
11864 | break; |
11865 | default: | |
11866 | /* There should be no other prefixes for instructions | |
11867 | with VEX prefix. */ | |
11868 | abort (); | |
11869 | } | |
11870 | ||
43234a1e L |
11871 | /* For EVEX instructions i.vrex should become 0 after |
11872 | build_evex_prefix. For VEX instructions upper 16 registers | |
11873 | aren't available, so VREX should be 0. */ | |
11874 | if (i.vrex) | |
11875 | abort (); | |
c0f3af97 | 11876 | /* Now the VEX prefix. */ |
48ef937e JB |
11877 | if (now_seg != absolute_section) |
11878 | { | |
11879 | p = frag_more (i.vex.length); | |
11880 | for (j = 0; j < i.vex.length; j++) | |
11881 | p[j] = i.vex.bytes[j]; | |
11882 | } | |
11883 | else | |
11884 | abs_section_offset += i.vex.length; | |
c0f3af97 | 11885 | } |
252b5132 | 11886 | |
29b0f896 | 11887 | /* Now the opcode; be careful about word order here! */ |
389d00a5 JB |
11888 | j = i.opcode_length; |
11889 | if (!i.vex.length) | |
ddb62495 | 11890 | switch (i.tm.opcode_space) |
389d00a5 JB |
11891 | { |
11892 | case SPACE_BASE: | |
11893 | break; | |
11894 | case SPACE_0F: | |
11895 | ++j; | |
11896 | break; | |
11897 | case SPACE_0F38: | |
11898 | case SPACE_0F3A: | |
11899 | j += 2; | |
11900 | break; | |
11901 | default: | |
11902 | abort (); | |
11903 | } | |
11904 | ||
48ef937e | 11905 | if (now_seg == absolute_section) |
389d00a5 JB |
11906 | abs_section_offset += j; |
11907 | else if (j == 1) | |
29b0f896 AM |
11908 | { |
11909 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
11910 | } | |
11911 | else | |
11912 | { | |
389d00a5 JB |
11913 | p = frag_more (j); |
11914 | if (!i.vex.length | |
ddb62495 | 11915 | && i.tm.opcode_space != SPACE_BASE) |
389d00a5 JB |
11916 | { |
11917 | *p++ = 0x0f; | |
ddb62495 JB |
11918 | if (i.tm.opcode_space != SPACE_0F) |
11919 | *p++ = i.tm.opcode_space == SPACE_0F38 | |
389d00a5 JB |
11920 | ? 0x38 : 0x3a; |
11921 | } | |
11922 | ||
9a182d04 | 11923 | switch (i.opcode_length) |
331d2d0d | 11924 | { |
4dffcebc | 11925 | case 2: |
389d00a5 JB |
11926 | /* Put out high byte first: can't use md_number_to_chars! */ |
11927 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
11928 | /* Fall through. */ | |
11929 | case 1: | |
11930 | *p = i.tm.base_opcode & 0xff; | |
4dffcebc L |
11931 | break; |
11932 | default: | |
11933 | abort (); | |
11934 | break; | |
331d2d0d | 11935 | } |
0f10071e | 11936 | |
29b0f896 | 11937 | } |
3e73aa7c | 11938 | |
29b0f896 | 11939 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 11940 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 11941 | { |
48ef937e JB |
11942 | frag_opcode_byte ((i.rm.regmem << 0) |
11943 | | (i.rm.reg << 3) | |
11944 | | (i.rm.mode << 6)); | |
29b0f896 AM |
11945 | /* If i.rm.regmem == ESP (4) |
11946 | && i.rm.mode != (Register mode) | |
11947 | && not 16 bit | |
11948 | ==> need second modrm byte. */ | |
11949 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
11950 | && i.rm.mode != 3 | |
dc821c5f | 11951 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
11952 | frag_opcode_byte ((i.sib.base << 0) |
11953 | | (i.sib.index << 3) | |
11954 | | (i.sib.scale << 6)); | |
29b0f896 | 11955 | } |
3e73aa7c | 11956 | |
29b0f896 | 11957 | if (i.disp_operands) |
2bbd9c25 | 11958 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 11959 | |
29b0f896 | 11960 | if (i.imm_operands) |
2bbd9c25 | 11961 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
11962 | |
11963 | /* | |
11964 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
11965 | * absolute section, and abs_section_offset not getting updated as data | |
11966 | * gets added to the frag breaks the logic below. | |
11967 | */ | |
11968 | if (now_seg != absolute_section) | |
11969 | { | |
11970 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
11971 | if (j > 15) | |
0afc614c L |
11972 | { |
11973 | if (dot_insn ()) | |
11974 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
11975 | j); | |
11976 | else | |
11977 | as_bad (_("instruction length of %u bytes exceeds the limit of 15"), | |
11978 | j); | |
11979 | } | |
e379e5f3 L |
11980 | else if (fragP) |
11981 | { | |
11982 | /* NB: Don't add prefix with GOTPC relocation since | |
11983 | output_disp() above depends on the fixed encoding | |
11984 | length. Can't add prefix with TLS relocation since | |
11985 | it breaks TLS linker optimization. */ | |
11986 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
11987 | /* Prefix count on the current instruction. */ | |
11988 | unsigned int count = i.vex.length; | |
11989 | unsigned int k; | |
11990 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
11991 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
11992 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
11993 | count++; | |
11994 | ||
11995 | /* Count prefixes for extended opcode maps. */ | |
11996 | if (!i.vex.length) | |
ddb62495 | 11997 | switch (i.tm.opcode_space) |
e379e5f3 | 11998 | { |
389d00a5 | 11999 | case SPACE_BASE: |
e379e5f3 | 12000 | break; |
389d00a5 JB |
12001 | case SPACE_0F: |
12002 | count++; | |
e379e5f3 | 12003 | break; |
389d00a5 JB |
12004 | case SPACE_0F38: |
12005 | case SPACE_0F3A: | |
12006 | count += 2; | |
e379e5f3 L |
12007 | break; |
12008 | default: | |
12009 | abort (); | |
12010 | } | |
12011 | ||
12012 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
12013 | == BRANCH_PREFIX) | |
12014 | { | |
12015 | /* Set the maximum prefix size in BRANCH_PREFIX | |
12016 | frag. */ | |
12017 | if (fragP->tc_frag_data.max_bytes > max) | |
12018 | fragP->tc_frag_data.max_bytes = max; | |
12019 | if (fragP->tc_frag_data.max_bytes > count) | |
12020 | fragP->tc_frag_data.max_bytes -= count; | |
12021 | else | |
12022 | fragP->tc_frag_data.max_bytes = 0; | |
12023 | } | |
12024 | else | |
12025 | { | |
12026 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
12027 | frag. */ | |
12028 | unsigned int max_prefix_size; | |
12029 | if (align_branch_prefix_size > max) | |
12030 | max_prefix_size = max; | |
12031 | else | |
12032 | max_prefix_size = align_branch_prefix_size; | |
12033 | if (max_prefix_size > count) | |
12034 | fragP->tc_frag_data.max_prefix_length | |
12035 | = max_prefix_size - count; | |
12036 | } | |
12037 | ||
12038 | /* Use existing segment prefix if possible. Use CS | |
12039 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
12040 | segment prefix with ESP/EBP base register and use DS | |
12041 | segment prefix without ESP/EBP base register. */ | |
12042 | if (i.prefix[SEG_PREFIX]) | |
12043 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
12044 | else if (flag_code == CODE_64BIT) | |
12045 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
12046 | else if (i.base_reg | |
12047 | && (i.base_reg->reg_num == 4 | |
12048 | || i.base_reg->reg_num == 5)) | |
12049 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
12050 | else | |
12051 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
12052 | } | |
9c33702b | 12053 | } |
29b0f896 | 12054 | } |
252b5132 | 12055 | |
e379e5f3 L |
12056 | /* NB: Don't work with COND_JUMP86 without i386. */ |
12057 | if (align_branch_power | |
12058 | && now_seg != absolute_section | |
12059 | && cpu_arch_flags.bitfield.cpui386) | |
12060 | { | |
12061 | /* Terminate each frag so that we can add prefix and check for | |
12062 | fused jcc. */ | |
12063 | frag_wane (frag_now); | |
12064 | frag_new (0); | |
12065 | } | |
12066 | ||
29b0f896 AM |
12067 | #ifdef DEBUG386 |
12068 | if (flag_debug) | |
12069 | { | |
7b81dfbb | 12070 | pi ("" /*line*/, &i); |
29b0f896 AM |
12071 | } |
12072 | #endif /* DEBUG386 */ | |
12073 | } | |
252b5132 | 12074 | |
e205caa7 L |
12075 | /* Return the size of the displacement operand N. */ |
12076 | ||
12077 | static int | |
12078 | disp_size (unsigned int n) | |
12079 | { | |
12080 | int size = 4; | |
43234a1e | 12081 | |
b5014f7a | 12082 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
12083 | size = 8; |
12084 | else if (i.types[n].bitfield.disp8) | |
12085 | size = 1; | |
12086 | else if (i.types[n].bitfield.disp16) | |
12087 | size = 2; | |
e205caa7 L |
12088 | return size; |
12089 | } | |
12090 | ||
12091 | /* Return the size of the immediate operand N. */ | |
12092 | ||
12093 | static int | |
12094 | imm_size (unsigned int n) | |
12095 | { | |
12096 | int size = 4; | |
40fb9820 L |
12097 | if (i.types[n].bitfield.imm64) |
12098 | size = 8; | |
12099 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
12100 | size = 1; | |
12101 | else if (i.types[n].bitfield.imm16) | |
12102 | size = 2; | |
e205caa7 L |
12103 | return size; |
12104 | } | |
12105 | ||
29b0f896 | 12106 | static void |
64e74474 | 12107 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
12108 | { |
12109 | char *p; | |
12110 | unsigned int n; | |
252b5132 | 12111 | |
29b0f896 AM |
12112 | for (n = 0; n < i.operands; n++) |
12113 | { | |
b5014f7a | 12114 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 12115 | { |
48ef937e JB |
12116 | int size = disp_size (n); |
12117 | ||
12118 | if (now_seg == absolute_section) | |
12119 | abs_section_offset += size; | |
12120 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 12121 | { |
43234a1e | 12122 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 12123 | |
629cfaf1 JB |
12124 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
12125 | size); | |
29b0f896 AM |
12126 | p = frag_more (size); |
12127 | md_number_to_chars (p, val, size); | |
12128 | } | |
12129 | else | |
12130 | { | |
f86103b7 | 12131 | enum bfd_reloc_code_real reloc_type; |
a775efc8 JB |
12132 | bool pcrel = (i.flags[n] & Operand_PCrel) != 0; |
12133 | bool sign = (flag_code == CODE_64BIT && size == 4 | |
12134 | && (!want_disp32 (&i.tm) | |
12135 | || (i.tm.opcode_modifier.jump && !i.jumpabsolute | |
12136 | && !i.types[n].bitfield.baseindex))) | |
12137 | || pcrel; | |
02a86693 | 12138 | fixS *fixP; |
29b0f896 | 12139 | |
e205caa7 | 12140 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 12141 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 12142 | |
29b0f896 AM |
12143 | /* The PC relative address is computed relative |
12144 | to the instruction boundary, so in case immediate | |
12145 | fields follows, we need to adjust the value. */ | |
12146 | if (pcrel && i.imm_operands) | |
12147 | { | |
29b0f896 | 12148 | unsigned int n1; |
e205caa7 | 12149 | int sz = 0; |
252b5132 | 12150 | |
29b0f896 | 12151 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 12152 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 12153 | { |
e205caa7 | 12154 | /* Only one immediate is allowed for PC |
e3bf0aad JB |
12155 | relative address, except with .insn. */ |
12156 | gas_assert (sz == 0 || dot_insn ()); | |
12157 | sz += imm_size (n1); | |
252b5132 | 12158 | } |
e3bf0aad | 12159 | /* We should find at least one immediate. */ |
9c2799c2 | 12160 | gas_assert (sz != 0); |
e3bf0aad | 12161 | i.op[n].disps->X_add_number -= sz; |
29b0f896 | 12162 | } |
520dc8e8 | 12163 | |
29b0f896 | 12164 | p = frag_more (size); |
d258b828 | 12165 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 12166 | if (GOT_symbol |
2bbd9c25 | 12167 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 12168 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
12169 | || reloc_type == BFD_RELOC_X86_64_32S |
12170 | || (reloc_type == BFD_RELOC_64 | |
12171 | && object_64bit)) | |
d6ab8113 JB |
12172 | && (i.op[n].disps->X_op == O_symbol |
12173 | || (i.op[n].disps->X_op == O_add | |
12174 | && ((symbol_get_value_expression | |
12175 | (i.op[n].disps->X_op_symbol)->X_op) | |
12176 | == O_subtract)))) | |
12177 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 12178 | { |
4fa24527 | 12179 | if (!object_64bit) |
7b81dfbb AJ |
12180 | { |
12181 | reloc_type = BFD_RELOC_386_GOTPC; | |
5b7c81bd | 12182 | i.has_gotpc_tls_reloc = true; |
98da05bf | 12183 | i.op[n].disps->X_add_number += |
d583596c | 12184 | encoding_length (insn_start_frag, insn_start_off, p); |
7b81dfbb AJ |
12185 | } |
12186 | else if (reloc_type == BFD_RELOC_64) | |
12187 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 12188 | else |
7b81dfbb AJ |
12189 | /* Don't do the adjustment for x86-64, as there |
12190 | the pcrel addressing is relative to the _next_ | |
12191 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 12192 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 12193 | } |
e379e5f3 L |
12194 | else if (align_branch_power) |
12195 | { | |
12196 | switch (reloc_type) | |
12197 | { | |
12198 | case BFD_RELOC_386_TLS_GD: | |
12199 | case BFD_RELOC_386_TLS_LDM: | |
12200 | case BFD_RELOC_386_TLS_IE: | |
12201 | case BFD_RELOC_386_TLS_IE_32: | |
12202 | case BFD_RELOC_386_TLS_GOTIE: | |
12203 | case BFD_RELOC_386_TLS_GOTDESC: | |
12204 | case BFD_RELOC_386_TLS_DESC_CALL: | |
12205 | case BFD_RELOC_X86_64_TLSGD: | |
12206 | case BFD_RELOC_X86_64_TLSLD: | |
12207 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 12208 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
5bc71c2a | 12209 | case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: |
e379e5f3 | 12210 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 12211 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
e379e5f3 | 12212 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
5b7c81bd | 12213 | i.has_gotpc_tls_reloc = true; |
e379e5f3 L |
12214 | default: |
12215 | break; | |
12216 | } | |
12217 | } | |
02a86693 L |
12218 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
12219 | size, i.op[n].disps, pcrel, | |
12220 | reloc_type); | |
eb19308f JB |
12221 | |
12222 | if (flag_code == CODE_64BIT && size == 4 && pcrel | |
12223 | && !i.prefix[ADDR_PREFIX]) | |
12224 | fixP->fx_signed = 1; | |
12225 | ||
5bc71c2a L |
12226 | if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF |
12227 | && i.tm.opcode_space == SPACE_EVEXMAP4) | |
12228 | { | |
12229 | /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is | |
12230 | allowed in md_assemble. Set fx_tcbit2 for EVEX | |
12231 | prefix. */ | |
12232 | fixP->fx_tcbit2 = 1; | |
12233 | continue; | |
12234 | } | |
12235 | ||
12236 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
12237 | { | |
12238 | if (reloc_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
12239 | { | |
12240 | /* Set fx_tcbit for REX2 prefix. */ | |
12241 | if (is_apx_rex2_encoding ()) | |
12242 | fixP->fx_tcbit = 1; | |
12243 | continue; | |
12244 | } | |
12245 | } | |
12246 | /* In 64-bit, i386_validate_fix updates only (%rip) | |
12247 | relocations. */ | |
12248 | else if (object_64bit) | |
12249 | continue; | |
3d5a60de | 12250 | |
02a86693 L |
12251 | /* Check for "call/jmp *mem", "mov mem, %reg", |
12252 | "test %reg, mem" and "binop mem, %reg" where binop | |
12253 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
12254 | instructions without data prefix. Always generate |
12255 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
12256 | if (i.prefix[DATA_PREFIX] == 0 | |
0cb4071e L |
12257 | && (i.rm.mode == 2 |
12258 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
ddb62495 | 12259 | && i.tm.opcode_space == SPACE_BASE |
02a86693 L |
12260 | && ((i.operands == 1 |
12261 | && i.tm.base_opcode == 0xff | |
12262 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
12263 | || (i.operands == 2 | |
12264 | && (i.tm.base_opcode == 0x8b | |
12265 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 12266 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
12267 | { |
12268 | if (object_64bit) | |
12269 | { | |
5bc71c2a L |
12270 | if (reloc_type == BFD_RELOC_X86_64_GOTTPOFF) |
12271 | { | |
12272 | /* Set fx_tcbit for REX2 prefix. */ | |
12273 | if (is_apx_rex2_encoding ()) | |
12274 | fixP->fx_tcbit = 1; | |
12275 | } | |
820a7755 | 12276 | else if (generate_relax_relocations) |
5bc71c2a L |
12277 | { |
12278 | /* Set fx_tcbit3 for REX2 prefix. */ | |
12279 | if (is_apx_rex2_encoding ()) | |
12280 | fixP->fx_tcbit3 = 1; | |
12281 | else if (i.rex) | |
12282 | fixP->fx_tcbit2 = 1; | |
12283 | else | |
12284 | fixP->fx_tcbit = 1; | |
12285 | } | |
02a86693 | 12286 | } |
820a7755 JB |
12287 | else if (generate_relax_relocations |
12288 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
12289 | fixP->fx_tcbit2 = 1; |
12290 | } | |
29b0f896 AM |
12291 | } |
12292 | } | |
12293 | } | |
12294 | } | |
252b5132 | 12295 | |
29b0f896 | 12296 | static void |
64e74474 | 12297 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
12298 | { |
12299 | char *p; | |
12300 | unsigned int n; | |
252b5132 | 12301 | |
29b0f896 AM |
12302 | for (n = 0; n < i.operands; n++) |
12303 | { | |
40fb9820 | 12304 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 12305 | { |
48ef937e JB |
12306 | int size = imm_size (n); |
12307 | ||
12308 | if (now_seg == absolute_section) | |
12309 | abs_section_offset += size; | |
12310 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 12311 | { |
29b0f896 | 12312 | offsetT val; |
b4cac588 | 12313 | |
29b0f896 AM |
12314 | val = offset_in_range (i.op[n].imms->X_add_number, |
12315 | size); | |
12316 | p = frag_more (size); | |
12317 | md_number_to_chars (p, val, size); | |
12318 | } | |
12319 | else | |
12320 | { | |
12321 | /* Not absolute_section. | |
12322 | Need a 32-bit fixup (don't support 8bit | |
12323 | non-absolute imms). Try to support other | |
12324 | sizes ... */ | |
f86103b7 | 12325 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 12326 | int sign; |
29b0f896 | 12327 | |
40fb9820 | 12328 | if (i.types[n].bitfield.imm32s |
a7d61044 | 12329 | && (i.suffix == QWORD_MNEM_SUFFIX |
c032bc4f | 12330 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf) |
f79d55e1 | 12331 | || (i.prefix[REX_PREFIX] & REX_W) |
c032bc4f | 12332 | || dot_insn ())) |
29b0f896 | 12333 | sign = 1; |
e205caa7 L |
12334 | else |
12335 | sign = 0; | |
520dc8e8 | 12336 | |
29b0f896 | 12337 | p = frag_more (size); |
d258b828 | 12338 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 12339 | |
2bbd9c25 JJ |
12340 | /* This is tough to explain. We end up with this one if we |
12341 | * have operands that look like | |
12342 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
12343 | * obtain the absolute address of the GOT, and it is strongly | |
12344 | * preferable from a performance point of view to avoid using | |
12345 | * a runtime relocation for this. The actual sequence of | |
12346 | * instructions often look something like: | |
12347 | * | |
12348 | * call .L66 | |
12349 | * .L66: | |
12350 | * popl %ebx | |
12351 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
12352 | * | |
12353 | * The call and pop essentially return the absolute address | |
12354 | * of the label .L66 and store it in %ebx. The linker itself | |
12355 | * will ultimately change the first operand of the addl so | |
12356 | * that %ebx points to the GOT, but to keep things simple, the | |
12357 | * .o file must have this operand set so that it generates not | |
12358 | * the absolute address of .L66, but the absolute address of | |
12359 | * itself. This allows the linker itself simply treat a GOTPC | |
12360 | * relocation as asking for a pcrel offset to the GOT to be | |
12361 | * added in, and the addend of the relocation is stored in the | |
12362 | * operand field for the instruction itself. | |
12363 | * | |
12364 | * Our job here is to fix the operand so that it would add | |
12365 | * the correct offset so that %ebx would point to itself. The | |
12366 | * thing that is tricky is that .-.L66 will point to the | |
12367 | * beginning of the instruction, so we need to further modify | |
12368 | * the operand so that it will point to itself. There are | |
12369 | * other cases where you have something like: | |
12370 | * | |
12371 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
12372 | * | |
12373 | * and here no correction would be required. Internally in | |
12374 | * the assembler we treat operands of this form as not being | |
12375 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
12376 | * whether it would simplify matters to do it this way. Who | |
12377 | * knows. In earlier versions of the PIC patches, the | |
12378 | * pcrel_adjust field was used to store the correction, but | |
12379 | * since the expression is not pcrel, I felt it would be | |
12380 | * confusing to do it this way. */ | |
12381 | ||
d6ab8113 | 12382 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
12383 | || reloc_type == BFD_RELOC_X86_64_32S |
12384 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
12385 | && GOT_symbol |
12386 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
12387 | && (i.op[n].imms->X_op == O_symbol | |
12388 | || (i.op[n].imms->X_op == O_add | |
12389 | && ((symbol_get_value_expression | |
12390 | (i.op[n].imms->X_op_symbol)->X_op) | |
12391 | == O_subtract)))) | |
12392 | { | |
4fa24527 | 12393 | if (!object_64bit) |
d6ab8113 | 12394 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 12395 | else if (size == 4) |
d6ab8113 | 12396 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
12397 | else if (size == 8) |
12398 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
5b7c81bd | 12399 | i.has_gotpc_tls_reloc = true; |
d583596c JB |
12400 | i.op[n].imms->X_add_number += |
12401 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 12402 | } |
29b0f896 AM |
12403 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
12404 | i.op[n].imms, 0, reloc_type); | |
12405 | } | |
12406 | } | |
12407 | } | |
252b5132 RH |
12408 | } |
12409 | \f | |
d182319b JB |
12410 | /* x86_cons_fix_new is called via the expression parsing code when a |
12411 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
12412 | static int cons_sign = -1; |
12413 | ||
12414 | void | |
e3bb37b5 | 12415 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 12416 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 12417 | { |
d258b828 | 12418 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
12419 | |
12420 | #ifdef TE_PE | |
12421 | if (exp->X_op == O_secrel) | |
12422 | { | |
12423 | exp->X_op = O_symbol; | |
12424 | r = BFD_RELOC_32_SECREL; | |
12425 | } | |
145667f8 MH |
12426 | else if (exp->X_op == O_secidx) |
12427 | r = BFD_RELOC_16_SECIDX; | |
d182319b JB |
12428 | #endif |
12429 | ||
12430 | fix_new_exp (frag, off, len, exp, 0, r); | |
12431 | } | |
12432 | ||
357d1bd8 L |
12433 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
12434 | purpose of the `.dc.a' internal pseudo-op. */ | |
12435 | ||
12436 | int | |
12437 | x86_address_bytes (void) | |
12438 | { | |
12439 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
12440 | return 4; | |
12441 | return stdoutput->arch_info->bits_per_address / 8; | |
12442 | } | |
12443 | ||
deea4973 JB |
12444 | #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
12445 | || defined (LEX_AT)) && !defined (TE_PE) | |
d258b828 | 12446 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 12447 | #else |
f3c180ae AM |
12448 | /* Parse operands of the form |
12449 | <symbol>@GOTOFF+<nnn> | |
12450 | and similar .plt or .got references. | |
12451 | ||
12452 | If we find one, set up the correct relocation in RELOC and copy the | |
12453 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
12454 | parsing by the calling routine. Return this buffer, and if ADJUST | |
12455 | is non-null set it to the length of the string we removed from the | |
12456 | input line. Otherwise return NULL. */ | |
12457 | static char * | |
91d6fa6a | 12458 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 12459 | int *adjust, |
d258b828 | 12460 | i386_operand_type *types) |
f3c180ae | 12461 | { |
7b81dfbb AJ |
12462 | /* Some of the relocations depend on the size of what field is to |
12463 | be relocated. But in our callers i386_immediate and i386_displacement | |
12464 | we don't yet know the operand size (this will be set by insn | |
12465 | matching). Hence we record the word32 relocation here, | |
12466 | and adjust the reloc according to the real size in reloc(). */ | |
145667f8 MH |
12467 | static const struct |
12468 | { | |
f3c180ae | 12469 | const char *str; |
cff8d58a | 12470 | int len; |
4fa24527 | 12471 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 12472 | const i386_operand_type types64; |
5b7c81bd | 12473 | bool need_GOT_symbol; |
145667f8 MH |
12474 | } |
12475 | gotrel[] = | |
12476 | { | |
05909f23 JB |
12477 | |
12478 | #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \ | |
12479 | { .imm32 = 1, .imm32s = 1, .disp32 = 1 } } | |
12480 | #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \ | |
12481 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } } | |
12482 | #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \ | |
12483 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } } | |
12484 | #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \ | |
12485 | { .imm64 = 1, .disp64 = 1 } } | |
12486 | ||
deea4973 | 12487 | #ifndef TE_PE |
8ce3d284 | 12488 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
12489 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
12490 | BFD_RELOC_SIZE32 }, | |
05909f23 | 12491 | { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false }, |
8ce3d284 | 12492 | #endif |
cff8d58a L |
12493 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
12494 | BFD_RELOC_X86_64_PLTOFF64 }, | |
05909f23 | 12495 | { .bitfield = { .imm64 = 1 } }, true }, |
cff8d58a L |
12496 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
12497 | BFD_RELOC_X86_64_PLT32 }, | |
a775efc8 | 12498 | OPERAND_TYPE_IMM32_32S_DISP32, false }, |
cff8d58a L |
12499 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
12500 | BFD_RELOC_X86_64_GOTPLT64 }, | |
5b7c81bd | 12501 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
12502 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
12503 | BFD_RELOC_X86_64_GOTOFF64 }, | |
5b7c81bd | 12504 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
12505 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
12506 | BFD_RELOC_X86_64_GOTPCREL }, | |
a775efc8 | 12507 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12508 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
12509 | BFD_RELOC_X86_64_TLSGD }, | |
a775efc8 | 12510 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12511 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
12512 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 12513 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
12514 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
12515 | BFD_RELOC_X86_64_TLSLD }, | |
a775efc8 | 12516 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12517 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
12518 | BFD_RELOC_X86_64_GOTTPOFF }, | |
a775efc8 | 12519 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12520 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
12521 | BFD_RELOC_X86_64_TPOFF32 }, | |
a775efc8 | 12522 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
12523 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
12524 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 12525 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
12526 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
12527 | BFD_RELOC_X86_64_DTPOFF32 }, | |
a775efc8 | 12528 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
12529 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
12530 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 12531 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
12532 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
12533 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 12534 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
12535 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
12536 | BFD_RELOC_X86_64_GOT32 }, | |
a775efc8 | 12537 | OPERAND_TYPE_IMM32_32S_64_DISP32, true }, |
cff8d58a L |
12538 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
12539 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
a775efc8 | 12540 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
12541 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
12542 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
a775efc8 | 12543 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
deea4973 JB |
12544 | #else /* TE_PE */ |
12545 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
12546 | BFD_RELOC_32_SECREL }, | |
a775efc8 | 12547 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, false }, |
deea4973 | 12548 | #endif |
05909f23 JB |
12549 | |
12550 | #undef OPERAND_TYPE_IMM32_32S_DISP32 | |
12551 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32 | |
12552 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64 | |
12553 | #undef OPERAND_TYPE_IMM64_DISP64 | |
12554 | ||
f3c180ae AM |
12555 | }; |
12556 | char *cp; | |
12557 | unsigned int j; | |
12558 | ||
deea4973 | 12559 | #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE) |
718ddfc0 JB |
12560 | if (!IS_ELF) |
12561 | return NULL; | |
d382c579 | 12562 | #endif |
718ddfc0 | 12563 | |
f3c180ae | 12564 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 12565 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
12566 | return NULL; |
12567 | ||
47465058 | 12568 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 12569 | { |
cff8d58a | 12570 | int len = gotrel[j].len; |
28f81592 | 12571 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 12572 | { |
4fa24527 | 12573 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 12574 | { |
28f81592 AM |
12575 | int first, second; |
12576 | char *tmpbuf, *past_reloc; | |
f3c180ae | 12577 | |
91d6fa6a | 12578 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 12579 | |
3956db08 JB |
12580 | if (types) |
12581 | { | |
12582 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
12583 | { |
12584 | types->bitfield.imm32 = 1; | |
12585 | types->bitfield.disp32 = 1; | |
12586 | } | |
3956db08 JB |
12587 | else |
12588 | *types = gotrel[j].types64; | |
12589 | } | |
12590 | ||
844bf810 | 12591 | if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL) |
f3c180ae AM |
12592 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
12593 | ||
28f81592 | 12594 | /* The length of the first part of our input line. */ |
f3c180ae | 12595 | first = cp - input_line_pointer; |
28f81592 AM |
12596 | |
12597 | /* The second part goes from after the reloc token until | |
67c11a9b | 12598 | (and including) an end_of_line char or comma. */ |
28f81592 | 12599 | past_reloc = cp + 1 + len; |
67c11a9b AM |
12600 | cp = past_reloc; |
12601 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
12602 | ++cp; | |
12603 | second = cp + 1 - past_reloc; | |
28f81592 AM |
12604 | |
12605 | /* Allocate and copy string. The trailing NUL shouldn't | |
12606 | be necessary, but be safe. */ | |
add39d23 | 12607 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 12608 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
12609 | if (second != 0 && *past_reloc != ' ') |
12610 | /* Replace the relocation token with ' ', so that | |
12611 | errors like foo@GOTOFF1 will be detected. */ | |
12612 | tmpbuf[first++] = ' '; | |
af89796a L |
12613 | else |
12614 | /* Increment length by 1 if the relocation token is | |
12615 | removed. */ | |
12616 | len++; | |
12617 | if (adjust) | |
12618 | *adjust = len; | |
0787a12d AM |
12619 | memcpy (tmpbuf + first, past_reloc, second); |
12620 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
12621 | return tmpbuf; |
12622 | } | |
12623 | ||
4fa24527 JB |
12624 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
12625 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
12626 | return NULL; |
12627 | } | |
12628 | } | |
12629 | ||
12630 | /* Might be a symbol version string. Don't as_bad here. */ | |
12631 | return NULL; | |
12632 | } | |
4e4f7c87 | 12633 | #endif |
f3c180ae | 12634 | |
62ebcb5c | 12635 | bfd_reloc_code_real_type |
e3bb37b5 | 12636 | x86_cons (expressionS *exp, int size) |
f3c180ae | 12637 | { |
62ebcb5c AM |
12638 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
12639 | ||
6b50f5f4 JB |
12640 | intel_syntax = -intel_syntax; |
12641 | exp->X_md = 0; | |
5cc00775 | 12642 | expr_mode = expr_operator_none; |
6b50f5f4 | 12643 | |
2748c1b1 L |
12644 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
12645 | && !defined (LEX_AT)) \ | |
12646 | || defined (TE_PE) | |
4fa24527 | 12647 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
12648 | { |
12649 | /* Handle @GOTOFF and the like in an expression. */ | |
12650 | char *save; | |
12651 | char *gotfree_input_line; | |
4a57f2cf | 12652 | int adjust = 0; |
f3c180ae AM |
12653 | |
12654 | save = input_line_pointer; | |
d258b828 | 12655 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
12656 | if (gotfree_input_line) |
12657 | input_line_pointer = gotfree_input_line; | |
12658 | ||
12659 | expression (exp); | |
12660 | ||
12661 | if (gotfree_input_line) | |
12662 | { | |
12663 | /* expression () has merrily parsed up to the end of line, | |
12664 | or a comma - in the wrong buffer. Transfer how far | |
12665 | input_line_pointer has moved to the right buffer. */ | |
12666 | input_line_pointer = (save | |
12667 | + (input_line_pointer - gotfree_input_line) | |
12668 | + adjust); | |
12669 | free (gotfree_input_line); | |
3992d3b7 AM |
12670 | if (exp->X_op == O_constant |
12671 | || exp->X_op == O_absent | |
12672 | || exp->X_op == O_illegal | |
0398aac5 | 12673 | || exp->X_op == O_register |
3992d3b7 AM |
12674 | || exp->X_op == O_big) |
12675 | { | |
12676 | char c = *input_line_pointer; | |
12677 | *input_line_pointer = 0; | |
12678 | as_bad (_("missing or invalid expression `%s'"), save); | |
12679 | *input_line_pointer = c; | |
12680 | } | |
b9519cfe L |
12681 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
12682 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
12683 | && exp->X_op != O_symbol) | |
12684 | { | |
12685 | char c = *input_line_pointer; | |
12686 | *input_line_pointer = 0; | |
12687 | as_bad (_("invalid PLT expression `%s'"), save); | |
12688 | *input_line_pointer = c; | |
12689 | } | |
f3c180ae AM |
12690 | } |
12691 | } | |
12692 | else | |
6b50f5f4 | 12693 | #endif |
f3c180ae | 12694 | expression (exp); |
ee86248c JB |
12695 | |
12696 | intel_syntax = -intel_syntax; | |
12697 | ||
12698 | if (intel_syntax) | |
12699 | i386_intel_simplify (exp); | |
62ebcb5c | 12700 | |
a442cac5 | 12701 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ |
5cc00775 JB |
12702 | if (size <= 4 && expr_mode == expr_operator_present |
12703 | && exp->X_op == O_constant && !object_64bit) | |
a442cac5 JB |
12704 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
12705 | ||
62ebcb5c | 12706 | return got_reloc; |
f3c180ae | 12707 | } |
f3c180ae | 12708 | |
9f32dd5b L |
12709 | static void |
12710 | signed_cons (int size) | |
6482c264 | 12711 | { |
a442cac5 | 12712 | if (object_64bit) |
d182319b JB |
12713 | cons_sign = 1; |
12714 | cons (size); | |
12715 | cons_sign = -1; | |
6482c264 NC |
12716 | } |
12717 | ||
edd67638 JB |
12718 | static void |
12719 | s_insn (int dummy ATTRIBUTE_UNUSED) | |
12720 | { | |
393fbe8d | 12721 | char mnemonic[MAX_MNEM_SIZE], *line = input_line_pointer, *ptr; |
edd67638 JB |
12722 | char *saved_ilp = find_end_of_line (line, false), saved_char; |
12723 | const char *end; | |
12724 | unsigned int j; | |
12725 | valueT val; | |
12726 | bool vex = false, xop = false, evex = false; | |
b5482fe5 | 12727 | struct last_insn *last_insn; |
edd67638 JB |
12728 | |
12729 | init_globals (); | |
12730 | ||
12731 | saved_char = *saved_ilp; | |
12732 | *saved_ilp = 0; | |
12733 | ||
12734 | end = parse_insn (line, mnemonic, true); | |
12735 | if (end == NULL) | |
12736 | { | |
12737 | bad: | |
12738 | *saved_ilp = saved_char; | |
12739 | ignore_rest_of_line (); | |
d0c2e3ec | 12740 | i.tm.mnem_off = 0; |
edd67638 JB |
12741 | return; |
12742 | } | |
12743 | line += end - line; | |
12744 | ||
d3b01414 JB |
12745 | current_templates.start = &i.tm; |
12746 | current_templates.end = &i.tm + 1; | |
edd67638 | 12747 | i.tm.mnem_off = MN__insn; |
393fbe8d | 12748 | i.tm.extension_opcode = None; |
edd67638 JB |
12749 | |
12750 | if (startswith (line, "VEX") | |
12751 | && (line[3] == '.' || is_space_char (line[3]))) | |
12752 | { | |
12753 | vex = true; | |
12754 | line += 3; | |
12755 | } | |
12756 | else if (startswith (line, "XOP") && ISDIGIT (line[3])) | |
12757 | { | |
12758 | char *e; | |
12759 | unsigned long n = strtoul (line + 3, &e, 16); | |
12760 | ||
12761 | if (e == line + 5 && n >= 0x08 && n <= 0x1f | |
12762 | && (*e == '.' || is_space_char (*e))) | |
12763 | { | |
12764 | xop = true; | |
d0c2e3ec JB |
12765 | /* Arrange for build_vex_prefix() to emit 0x8f. */ |
12766 | i.tm.opcode_space = SPACE_XOP08; | |
12767 | i.insn_opcode_space = n; | |
edd67638 JB |
12768 | line = e; |
12769 | } | |
12770 | } | |
12771 | else if (startswith (line, "EVEX") | |
12772 | && (line[4] == '.' || is_space_char (line[4]))) | |
12773 | { | |
12774 | evex = true; | |
12775 | line += 4; | |
12776 | } | |
12777 | ||
12778 | if (vex || xop | |
e346d50a | 12779 | ? i.encoding == encoding_evex |
edd67638 | 12780 | : evex |
e346d50a JB |
12781 | ? i.encoding == encoding_vex |
12782 | || i.encoding == encoding_vex3 | |
12783 | : i.encoding != encoding_default) | |
edd67638 JB |
12784 | { |
12785 | as_bad (_("pseudo-prefix conflicts with encoding specifier")); | |
12786 | goto bad; | |
12787 | } | |
12788 | ||
e346d50a JB |
12789 | if (line > end && i.encoding == encoding_default) |
12790 | i.encoding = evex ? encoding_evex : encoding_vex; | |
0ff3b7d0 | 12791 | |
e346d50a | 12792 | if (i.encoding != encoding_default) |
1adecddd JB |
12793 | { |
12794 | /* Only address size and segment override prefixes are permitted with | |
12795 | VEX/XOP/EVEX encodings. */ | |
12796 | const unsigned char *p = i.prefix; | |
12797 | ||
12798 | for (j = 0; j < ARRAY_SIZE (i.prefix); ++j, ++p) | |
12799 | { | |
12800 | if (!*p) | |
12801 | continue; | |
12802 | ||
12803 | switch (j) | |
12804 | { | |
12805 | case SEG_PREFIX: | |
12806 | case ADDR_PREFIX: | |
12807 | break; | |
12808 | default: | |
12809 | as_bad (_("illegal prefix used with VEX/XOP/EVEX")); | |
12810 | goto bad; | |
12811 | } | |
12812 | } | |
12813 | } | |
12814 | ||
edd67638 JB |
12815 | if (line > end && *line == '.') |
12816 | { | |
d0c2e3ec JB |
12817 | /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */ |
12818 | switch (line[1]) | |
12819 | { | |
12820 | case 'L': | |
12821 | switch (line[2]) | |
12822 | { | |
12823 | case '0': | |
12824 | if (evex) | |
12825 | i.tm.opcode_modifier.evex = EVEX128; | |
12826 | else | |
12827 | i.tm.opcode_modifier.vex = VEX128; | |
12828 | break; | |
12829 | ||
12830 | case '1': | |
12831 | if (evex) | |
12832 | i.tm.opcode_modifier.evex = EVEX256; | |
12833 | else | |
12834 | i.tm.opcode_modifier.vex = VEX256; | |
12835 | break; | |
12836 | ||
12837 | case '2': | |
12838 | if (evex) | |
12839 | i.tm.opcode_modifier.evex = EVEX512; | |
12840 | break; | |
12841 | ||
12842 | case '3': | |
12843 | if (evex) | |
12844 | i.tm.opcode_modifier.evex = EVEX_L3; | |
12845 | break; | |
12846 | ||
12847 | case 'I': | |
12848 | if (line[3] == 'G') | |
12849 | { | |
12850 | if (evex) | |
12851 | i.tm.opcode_modifier.evex = EVEXLIG; | |
12852 | else | |
12853 | i.tm.opcode_modifier.vex = VEXScalar; /* LIG */ | |
12854 | ++line; | |
12855 | } | |
12856 | break; | |
12857 | } | |
12858 | ||
12859 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) | |
12860 | line += 3; | |
12861 | break; | |
12862 | ||
12863 | case '1': | |
12864 | if (line[2] == '2' && line[3] == '8') | |
12865 | { | |
12866 | if (evex) | |
12867 | i.tm.opcode_modifier.evex = EVEX128; | |
12868 | else | |
12869 | i.tm.opcode_modifier.vex = VEX128; | |
12870 | line += 4; | |
12871 | } | |
12872 | break; | |
12873 | ||
12874 | case '2': | |
12875 | if (line[2] == '5' && line[3] == '6') | |
12876 | { | |
12877 | if (evex) | |
12878 | i.tm.opcode_modifier.evex = EVEX256; | |
12879 | else | |
12880 | i.tm.opcode_modifier.vex = VEX256; | |
12881 | line += 4; | |
12882 | } | |
12883 | break; | |
12884 | ||
12885 | case '5': | |
12886 | if (evex && line[2] == '1' && line[3] == '2') | |
12887 | { | |
12888 | i.tm.opcode_modifier.evex = EVEX512; | |
12889 | line += 4; | |
12890 | } | |
12891 | break; | |
12892 | } | |
12893 | } | |
12894 | ||
12895 | if (line > end && *line == '.') | |
12896 | { | |
12897 | /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */ | |
12898 | switch (line[1]) | |
12899 | { | |
12900 | case 'N': | |
12901 | if (line[2] == 'P') | |
12902 | line += 3; | |
12903 | break; | |
12904 | ||
12905 | case '6': | |
12906 | if (line[2] == '6') | |
12907 | { | |
12908 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; | |
12909 | line += 3; | |
12910 | } | |
12911 | break; | |
12912 | ||
12913 | case 'F': case 'f': | |
12914 | if (line[2] == '3') | |
12915 | { | |
12916 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
12917 | line += 3; | |
12918 | } | |
12919 | else if (line[2] == '2') | |
12920 | { | |
12921 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2; | |
12922 | line += 3; | |
12923 | } | |
12924 | break; | |
12925 | } | |
12926 | } | |
12927 | ||
12928 | if (line > end && !xop && *line == '.') | |
12929 | { | |
12930 | /* Encoding space (VEX.mmmmm, EVEX.mmmm). */ | |
12931 | switch (line[1]) | |
12932 | { | |
12933 | case '0': | |
12934 | if (TOUPPER (line[2]) != 'F') | |
12935 | break; | |
12936 | if (line[3] == '.' || is_space_char (line[3])) | |
12937 | { | |
12938 | i.insn_opcode_space = SPACE_0F; | |
12939 | line += 3; | |
12940 | } | |
12941 | else if (line[3] == '3' | |
12942 | && (line[4] == '8' || TOUPPER (line[4]) == 'A') | |
12943 | && (line[5] == '.' || is_space_char (line[5]))) | |
12944 | { | |
12945 | i.insn_opcode_space = line[4] == '8' ? SPACE_0F38 : SPACE_0F3A; | |
12946 | line += 5; | |
12947 | } | |
12948 | break; | |
12949 | ||
12950 | case 'M': | |
12951 | if (ISDIGIT (line[2]) && line[2] != '0') | |
12952 | { | |
12953 | char *e; | |
12954 | unsigned long n = strtoul (line + 2, &e, 10); | |
12955 | ||
12956 | if (n <= (evex ? 15 : 31) | |
12957 | && (*e == '.' || is_space_char (*e))) | |
12958 | { | |
12959 | i.insn_opcode_space = n; | |
12960 | line = e; | |
12961 | } | |
12962 | } | |
12963 | break; | |
12964 | } | |
12965 | } | |
12966 | ||
12967 | if (line > end && *line == '.' && line[1] == 'W') | |
12968 | { | |
12969 | /* VEX.W, XOP.W, EVEX.W */ | |
12970 | switch (line[2]) | |
12971 | { | |
12972 | case '0': | |
12973 | i.tm.opcode_modifier.vexw = VEXW0; | |
12974 | break; | |
12975 | ||
12976 | case '1': | |
12977 | i.tm.opcode_modifier.vexw = VEXW1; | |
12978 | break; | |
12979 | ||
12980 | case 'I': | |
12981 | if (line[3] == 'G') | |
12982 | { | |
12983 | i.tm.opcode_modifier.vexw = VEXWIG; | |
12984 | ++line; | |
12985 | } | |
12986 | break; | |
12987 | } | |
12988 | ||
12989 | if (i.tm.opcode_modifier.vexw) | |
12990 | line += 3; | |
12991 | } | |
12992 | ||
12993 | if (line > end && *line && !is_space_char (*line)) | |
12994 | { | |
12995 | /* Improve diagnostic a little. */ | |
12996 | if (*line == '.' && line[1] && !is_space_char (line[1])) | |
12997 | ++line; | |
12998 | goto done; | |
edd67638 JB |
12999 | } |
13000 | ||
393fbe8d JB |
13001 | /* Before processing the opcode expression, find trailing "+r" or |
13002 | "/<digit>" specifiers. */ | |
13003 | for (ptr = line; ; ++ptr) | |
13004 | { | |
13005 | unsigned long n; | |
13006 | char *e; | |
13007 | ||
13008 | ptr = strpbrk (ptr, "+/,"); | |
13009 | if (ptr == NULL || *ptr == ',') | |
13010 | break; | |
13011 | ||
13012 | if (*ptr == '+' && ptr[1] == 'r' | |
13013 | && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ','))) | |
13014 | { | |
13015 | *ptr = ' '; | |
13016 | ptr[1] = ' '; | |
13017 | i.short_form = true; | |
13018 | break; | |
13019 | } | |
13020 | ||
13021 | if (*ptr == '/' && ISDIGIT (ptr[1]) | |
13022 | && (n = strtoul (ptr + 1, &e, 8)) < 8 | |
13023 | && e == ptr + 2 | |
13024 | && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ','))) | |
13025 | { | |
13026 | *ptr = ' '; | |
13027 | ptr[1] = ' '; | |
13028 | i.tm.extension_opcode = n; | |
13029 | i.tm.opcode_modifier.modrm = 1; | |
13030 | break; | |
13031 | } | |
13032 | } | |
13033 | ||
edd67638 JB |
13034 | input_line_pointer = line; |
13035 | val = get_absolute_expression (); | |
13036 | line = input_line_pointer; | |
13037 | ||
393fbe8d JB |
13038 | if (i.short_form && (val & 7)) |
13039 | as_warn ("`+r' assumes low three opcode bits to be clear"); | |
13040 | ||
edd67638 JB |
13041 | for (j = 1; j < sizeof(val); ++j) |
13042 | if (!(val >> (j * 8))) | |
13043 | break; | |
13044 | ||
13045 | /* Trim off a prefix if present. */ | |
13046 | if (j > 1 && !vex && !xop && !evex) | |
13047 | { | |
13048 | uint8_t byte = val >> ((j - 1) * 8); | |
13049 | ||
13050 | switch (byte) | |
13051 | { | |
13052 | case DATA_PREFIX_OPCODE: | |
13053 | case REPE_PREFIX_OPCODE: | |
13054 | case REPNE_PREFIX_OPCODE: | |
13055 | if (!add_prefix (byte)) | |
13056 | goto bad; | |
13057 | val &= ((uint64_t)1 << (--j * 8)) - 1; | |
13058 | break; | |
13059 | } | |
13060 | } | |
13061 | ||
6804f42c JB |
13062 | /* Parse operands, if any, before evaluating encoding space. */ |
13063 | if (*line == ',') | |
13064 | { | |
13065 | i.memshift = -1; | |
13066 | ||
13067 | ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]); | |
13068 | this_operand = -1; | |
13069 | if (!ptr) | |
13070 | goto bad; | |
13071 | line = ptr; | |
13072 | ||
13073 | if (!i.operands) | |
13074 | { | |
13075 | as_bad (_("expecting operand after ','; got nothing")); | |
13076 | goto done; | |
13077 | } | |
13078 | ||
13079 | if (i.mem_operands > 1) | |
13080 | { | |
13081 | as_bad (_("too many memory references for `%s'"), | |
13082 | &i386_mnemonics[MN__insn]); | |
13083 | goto done; | |
13084 | } | |
13085 | ||
13086 | /* No need to distinguish encoding_evex and encoding_evex512. */ | |
13087 | if (i.encoding == encoding_evex512) | |
13088 | i.encoding = encoding_evex; | |
13089 | } | |
13090 | ||
edd67638 | 13091 | /* Trim off encoding space. */ |
d0c2e3ec | 13092 | if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f) |
edd67638 JB |
13093 | { |
13094 | uint8_t byte = val >> ((--j - 1) * 8); | |
13095 | ||
d0c2e3ec | 13096 | i.insn_opcode_space = SPACE_0F; |
6804f42c JB |
13097 | switch (byte & -(j > 1 && !i.rex2_encoding |
13098 | && (i.encoding != encoding_egpr || evex))) | |
edd67638 JB |
13099 | { |
13100 | case 0x38: | |
d0c2e3ec | 13101 | i.insn_opcode_space = SPACE_0F38; |
edd67638 JB |
13102 | --j; |
13103 | break; | |
13104 | case 0x3a: | |
d0c2e3ec | 13105 | i.insn_opcode_space = SPACE_0F3A; |
edd67638 JB |
13106 | --j; |
13107 | break; | |
13108 | } | |
d0c2e3ec | 13109 | i.tm.opcode_space = i.insn_opcode_space; |
edd67638 JB |
13110 | val &= ((uint64_t)1 << (j * 8)) - 1; |
13111 | } | |
d0c2e3ec JB |
13112 | if (!i.tm.opcode_space && (vex || evex)) |
13113 | /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5. | |
13114 | Also avoid hitting abort() there or in build_evex_prefix(). */ | |
13115 | i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F | |
13116 | : SPACE_0F38; | |
edd67638 JB |
13117 | |
13118 | if (j > 2) | |
13119 | { | |
13120 | as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val); | |
6804f42c | 13121 | goto done; |
edd67638 JB |
13122 | } |
13123 | i.opcode_length = j; | |
0ff3b7d0 JB |
13124 | |
13125 | /* Handle operands, if any. */ | |
6804f42c | 13126 | if (i.operands) |
0ff3b7d0 JB |
13127 | { |
13128 | i386_operand_type combined; | |
f7377a91 | 13129 | expressionS *disp_exp = NULL; |
0ff3b7d0 JB |
13130 | bool changed; |
13131 | ||
eb3f3841 JB |
13132 | if (i.encoding == encoding_egpr) |
13133 | { | |
13134 | if (vex || xop) | |
13135 | { | |
13136 | as_bad (_("eGPR use conflicts with encoding specifier")); | |
13137 | goto done; | |
13138 | } | |
13139 | if (evex) | |
13140 | i.encoding = encoding_evex; | |
13141 | else | |
13142 | i.encoding = encoding_default; | |
13143 | } | |
13144 | ||
0ff3b7d0 JB |
13145 | /* Are we to emit ModR/M encoding? */ |
13146 | if (!i.short_form | |
13147 | && (i.mem_operands | |
e346d50a | 13148 | || i.reg_operands > (i.encoding != encoding_default) |
0ff3b7d0 JB |
13149 | || i.tm.extension_opcode != None)) |
13150 | i.tm.opcode_modifier.modrm = 1; | |
13151 | ||
13152 | if (!i.tm.opcode_modifier.modrm | |
13153 | && (i.reg_operands | |
e346d50a | 13154 | > i.short_form + 0U + (i.encoding != encoding_default) |
0ff3b7d0 JB |
13155 | || i.mem_operands)) |
13156 | { | |
13157 | as_bad (_("too many register/memory operands")); | |
13158 | goto done; | |
13159 | } | |
13160 | ||
13161 | /* Enforce certain constraints on operands. */ | |
13162 | switch (i.reg_operands + i.mem_operands | |
13163 | + (i.tm.extension_opcode != None)) | |
13164 | { | |
13165 | case 0: | |
13166 | if (i.short_form) | |
13167 | { | |
13168 | as_bad (_("too few register/memory operands")); | |
13169 | goto done; | |
13170 | } | |
13171 | /* Fall through. */ | |
13172 | case 1: | |
13173 | if (i.tm.opcode_modifier.modrm) | |
13174 | { | |
13175 | as_bad (_("too few register/memory operands")); | |
13176 | goto done; | |
13177 | } | |
13178 | break; | |
13179 | ||
13180 | case 2: | |
13181 | break; | |
13182 | ||
13183 | case 4: | |
13184 | if (i.imm_operands | |
13185 | && (i.op[0].imms->X_op != O_constant | |
13186 | || !fits_in_imm4 (i.op[0].imms->X_add_number))) | |
13187 | { | |
13188 | as_bad (_("constant doesn't fit in %d bits"), evex ? 3 : 4); | |
13189 | goto done; | |
13190 | } | |
13191 | /* Fall through. */ | |
13192 | case 3: | |
e346d50a | 13193 | if (i.encoding != encoding_default) |
0ff3b7d0 | 13194 | { |
f2a3a881 | 13195 | i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1; |
0ff3b7d0 JB |
13196 | break; |
13197 | } | |
13198 | /* Fall through. */ | |
13199 | default: | |
13200 | as_bad (_("too many register/memory operands")); | |
13201 | goto done; | |
13202 | } | |
13203 | ||
13204 | /* Bring operands into canonical order (imm, mem, reg). */ | |
13205 | do | |
13206 | { | |
13207 | changed = false; | |
13208 | ||
13209 | for (j = 1; j < i.operands; ++j) | |
13210 | { | |
13211 | if ((!operand_type_check (i.types[j - 1], imm) | |
13212 | && operand_type_check (i.types[j], imm)) | |
13213 | || (i.types[j - 1].bitfield.class != ClassNone | |
13214 | && i.types[j].bitfield.class == ClassNone)) | |
13215 | { | |
13216 | swap_2_operands (j - 1, j); | |
13217 | changed = true; | |
13218 | } | |
13219 | } | |
13220 | } | |
13221 | while (changed); | |
13222 | ||
13223 | /* For Intel syntax swap the order of register operands. */ | |
13224 | if (intel_syntax) | |
13225 | switch (i.reg_operands) | |
13226 | { | |
13227 | case 0: | |
13228 | case 1: | |
13229 | break; | |
13230 | ||
13231 | case 4: | |
13232 | swap_2_operands (i.imm_operands + i.mem_operands + 1, i.operands - 2); | |
13233 | /* Fall through. */ | |
13234 | case 3: | |
13235 | case 2: | |
13236 | swap_2_operands (i.imm_operands + i.mem_operands, i.operands - 1); | |
13237 | break; | |
13238 | ||
13239 | default: | |
13240 | abort (); | |
13241 | } | |
13242 | ||
13243 | /* Enforce constraints when using VSIB. */ | |
13244 | if (i.index_reg | |
13245 | && (i.index_reg->reg_type.bitfield.xmmword | |
13246 | || i.index_reg->reg_type.bitfield.ymmword | |
13247 | || i.index_reg->reg_type.bitfield.zmmword)) | |
13248 | { | |
e346d50a | 13249 | if (i.encoding == encoding_default) |
0ff3b7d0 JB |
13250 | { |
13251 | as_bad (_("VSIB unavailable with legacy encoding")); | |
13252 | goto done; | |
13253 | } | |
13254 | ||
e346d50a | 13255 | if (i.encoding == encoding_evex |
0ff3b7d0 JB |
13256 | && i.reg_operands > 1) |
13257 | { | |
13258 | /* We could allow two register operands, encoding the 2nd one in | |
13259 | an 8-bit immediate like for 4-register-operand insns, but that | |
13260 | would require ugly fiddling with process_operands() and/or | |
13261 | build_modrm_byte(). */ | |
13262 | as_bad (_("too many register operands with VSIB")); | |
13263 | goto done; | |
13264 | } | |
13265 | ||
13266 | i.tm.opcode_modifier.sib = 1; | |
13267 | } | |
13268 | ||
13269 | /* Establish operand size encoding. */ | |
13270 | operand_type_set (&combined, 0); | |
f7377a91 | 13271 | |
0ff3b7d0 JB |
13272 | for (j = i.imm_operands; j < i.operands; ++j) |
13273 | { | |
3e4a511b | 13274 | /* Look for 8-bit operands that use old registers. */ |
e346d50a | 13275 | if (i.encoding != encoding_default |
3e4a511b JB |
13276 | && flag_code == CODE_64BIT |
13277 | && i.types[j].bitfield.class == Reg | |
13278 | && i.types[j].bitfield.byte | |
13279 | && !(i.op[j].regs->reg_flags & RegRex64) | |
13280 | && i.op[j].regs->reg_num > 3) | |
13281 | as_bad (_("can't encode register '%s%s' with VEX/XOP/EVEX"), | |
13282 | register_prefix, i.op[j].regs->reg_name); | |
13283 | ||
0ff3b7d0 JB |
13284 | i.types[j].bitfield.instance = InstanceNone; |
13285 | ||
13286 | if (operand_type_check (i.types[j], disp)) | |
f7377a91 JB |
13287 | { |
13288 | i.types[j].bitfield.baseindex = 1; | |
13289 | disp_exp = i.op[j].disps; | |
13290 | } | |
13291 | ||
13292 | if (evex && i.types[j].bitfield.baseindex) | |
13293 | { | |
13294 | unsigned int n = i.memshift; | |
13295 | ||
13296 | if (i.types[j].bitfield.byte) | |
13297 | n = 0; | |
13298 | else if (i.types[j].bitfield.word) | |
13299 | n = 1; | |
13300 | else if (i.types[j].bitfield.dword) | |
13301 | n = 2; | |
13302 | else if (i.types[j].bitfield.qword) | |
13303 | n = 3; | |
13304 | else if (i.types[j].bitfield.xmmword) | |
13305 | n = 4; | |
13306 | else if (i.types[j].bitfield.ymmword) | |
13307 | n = 5; | |
13308 | else if (i.types[j].bitfield.zmmword) | |
13309 | n = 6; | |
13310 | ||
13311 | if (i.memshift < 32 && n != i.memshift) | |
13312 | as_warn ("conflicting memory operand size specifiers"); | |
13313 | i.memshift = n; | |
13314 | } | |
0ff3b7d0 JB |
13315 | |
13316 | if ((i.broadcast.type || i.broadcast.bytes) | |
13317 | && j == i.broadcast.operand) | |
13318 | continue; | |
13319 | ||
13320 | combined = operand_type_or (combined, i.types[j]); | |
13321 | combined.bitfield.class = ClassNone; | |
13322 | } | |
13323 | ||
f7377a91 JB |
13324 | switch ((i.broadcast.type ? i.broadcast.type : 1) |
13325 | << (i.memshift < 32 ? i.memshift : 0)) | |
13326 | { | |
13327 | case 64: combined.bitfield.zmmword = 1; break; | |
13328 | case 32: combined.bitfield.ymmword = 1; break; | |
13329 | case 16: combined.bitfield.xmmword = 1; break; | |
13330 | case 8: combined.bitfield.qword = 1; break; | |
13331 | case 4: combined.bitfield.dword = 1; break; | |
13332 | } | |
13333 | ||
e346d50a | 13334 | if (i.encoding == encoding_default) |
0ff3b7d0 JB |
13335 | { |
13336 | if (flag_code == CODE_64BIT && combined.bitfield.qword) | |
13337 | i.rex |= REX_W; | |
13338 | else if ((flag_code == CODE_16BIT ? combined.bitfield.dword | |
13339 | : combined.bitfield.word) | |
13340 | && !add_prefix (DATA_PREFIX_OPCODE)) | |
13341 | goto done; | |
13342 | } | |
13343 | else if (!i.tm.opcode_modifier.vexw) | |
13344 | { | |
13345 | if (flag_code == CODE_64BIT) | |
13346 | { | |
13347 | if (combined.bitfield.qword) | |
13348 | i.tm.opcode_modifier.vexw = VEXW1; | |
13349 | else if (combined.bitfield.dword) | |
13350 | i.tm.opcode_modifier.vexw = VEXW0; | |
13351 | } | |
13352 | ||
13353 | if (!i.tm.opcode_modifier.vexw) | |
13354 | i.tm.opcode_modifier.vexw = VEXWIG; | |
13355 | } | |
13356 | ||
13357 | if (vex || xop) | |
13358 | { | |
13359 | if (!i.tm.opcode_modifier.vex) | |
13360 | { | |
13361 | if (combined.bitfield.ymmword) | |
13362 | i.tm.opcode_modifier.vex = VEX256; | |
13363 | else if (combined.bitfield.xmmword) | |
13364 | i.tm.opcode_modifier.vex = VEX128; | |
13365 | } | |
13366 | } | |
13367 | else if (evex) | |
13368 | { | |
13369 | if (!i.tm.opcode_modifier.evex) | |
13370 | { | |
13371 | /* Do _not_ consider AVX512VL here. */ | |
13372 | if (i.rounding.type != rc_none || combined.bitfield.zmmword) | |
13373 | i.tm.opcode_modifier.evex = EVEX512; | |
13374 | else if (combined.bitfield.ymmword) | |
13375 | i.tm.opcode_modifier.evex = EVEX256; | |
13376 | else if (combined.bitfield.xmmword) | |
13377 | i.tm.opcode_modifier.evex = EVEX128; | |
13378 | } | |
f7377a91 JB |
13379 | |
13380 | if (i.memshift >= 32) | |
13381 | { | |
13382 | unsigned int n = 0; | |
13383 | ||
13384 | switch (i.tm.opcode_modifier.evex) | |
13385 | { | |
13386 | case EVEX512: n = 64; break; | |
13387 | case EVEX256: n = 32; break; | |
13388 | case EVEX128: n = 16; break; | |
13389 | } | |
13390 | ||
13391 | if (i.broadcast.type) | |
13392 | n /= i.broadcast.type; | |
13393 | ||
13394 | if (n > 0) | |
13395 | for (i.memshift = 0; !(n & 1); n >>= 1) | |
13396 | ++i.memshift; | |
13397 | else if (disp_exp != NULL && disp_exp->X_op == O_constant | |
13398 | && disp_exp->X_add_number != 0 | |
13399 | && i.disp_encoding != disp_encoding_32bit) | |
13400 | { | |
13401 | if (!quiet_warnings) | |
13402 | as_warn ("cannot determine memory operand size"); | |
13403 | i.disp_encoding = disp_encoding_32bit; | |
13404 | } | |
13405 | } | |
0ff3b7d0 JB |
13406 | } |
13407 | ||
f7377a91 JB |
13408 | if (i.memshift >= 32) |
13409 | i.memshift = 0; | |
13410 | else if (!evex) | |
e346d50a | 13411 | i.encoding = encoding_error; |
f7377a91 | 13412 | |
0ff3b7d0 JB |
13413 | if (i.disp_operands && !optimize_disp (&i.tm)) |
13414 | goto done; | |
13415 | ||
c032bc4f JB |
13416 | /* Establish size for immediate operands. */ |
13417 | for (j = 0; j < i.imm_operands; ++j) | |
13418 | { | |
13419 | expressionS *expP = i.op[j].imms; | |
13420 | ||
13421 | gas_assert (operand_type_check (i.types[j], imm)); | |
13422 | operand_type_set (&i.types[j], 0); | |
13423 | ||
13424 | if (i.imm_bits[j] > 32) | |
13425 | i.types[j].bitfield.imm64 = 1; | |
13426 | else if (i.imm_bits[j] > 16) | |
13427 | { | |
13428 | if (flag_code == CODE_64BIT && (i.flags[j] & Operand_Signed)) | |
13429 | i.types[j].bitfield.imm32s = 1; | |
13430 | else | |
13431 | i.types[j].bitfield.imm32 = 1; | |
13432 | } | |
13433 | else if (i.imm_bits[j] > 8) | |
13434 | i.types[j].bitfield.imm16 = 1; | |
13435 | else if (i.imm_bits[j] > 0) | |
13436 | { | |
13437 | if (i.flags[j] & Operand_Signed) | |
13438 | i.types[j].bitfield.imm8s = 1; | |
13439 | else | |
13440 | i.types[j].bitfield.imm8 = 1; | |
13441 | } | |
13442 | else if (expP->X_op == O_constant) | |
13443 | { | |
13444 | i.types[j] = smallest_imm_type (expP->X_add_number); | |
13445 | i.types[j].bitfield.imm1 = 0; | |
13446 | /* Oddly enough imm_size() checks imm64 first, so the bit needs | |
13447 | zapping since smallest_imm_type() sets it unconditionally. */ | |
13448 | if (flag_code != CODE_64BIT) | |
13449 | { | |
13450 | i.types[j].bitfield.imm64 = 0; | |
13451 | i.types[j].bitfield.imm32s = 0; | |
13452 | i.types[j].bitfield.imm32 = 1; | |
13453 | } | |
13454 | else if (i.types[j].bitfield.imm32 || i.types[j].bitfield.imm32s) | |
13455 | i.types[j].bitfield.imm64 = 0; | |
13456 | } | |
13457 | else | |
13458 | /* Non-constant expressions are sized heuristically. */ | |
13459 | switch (flag_code) | |
13460 | { | |
13461 | case CODE_64BIT: i.types[j].bitfield.imm32s = 1; break; | |
13462 | case CODE_32BIT: i.types[j].bitfield.imm32 = 1; break; | |
13463 | case CODE_16BIT: i.types[j].bitfield.imm16 = 1; break; | |
13464 | } | |
13465 | } | |
13466 | ||
0ff3b7d0 JB |
13467 | for (j = 0; j < i.operands; ++j) |
13468 | i.tm.operand_types[j] = i.types[j]; | |
13469 | ||
13470 | process_operands (); | |
13471 | } | |
13472 | ||
13473 | /* Don't set opcode until after processing operands, to avoid any | |
13474 | potential special casing there. */ | |
13475 | i.tm.base_opcode |= val; | |
13476 | ||
e346d50a JB |
13477 | if (i.encoding == encoding_error |
13478 | || (i.encoding != encoding_evex | |
0ff3b7d0 JB |
13479 | ? i.broadcast.type || i.broadcast.bytes |
13480 | || i.rounding.type != rc_none | |
13481 | || i.mask.reg | |
f586e340 JB |
13482 | : (i.mem_operands && i.rounding.type != rc_none) |
13483 | || ((i.broadcast.type || i.broadcast.bytes) | |
13484 | && !(i.flags[i.broadcast.operand] & Operand_Mem)))) | |
0ff3b7d0 JB |
13485 | { |
13486 | as_bad (_("conflicting .insn operands")); | |
13487 | goto done; | |
13488 | } | |
edd67638 | 13489 | |
d0c2e3ec JB |
13490 | if (vex || xop) |
13491 | { | |
13492 | if (!i.tm.opcode_modifier.vex) | |
13493 | i.tm.opcode_modifier.vex = VEXScalar; /* LIG */ | |
13494 | ||
13495 | build_vex_prefix (NULL); | |
13496 | i.rex &= REX_OPCODE; | |
13497 | } | |
13498 | else if (evex) | |
13499 | { | |
13500 | if (!i.tm.opcode_modifier.evex) | |
13501 | i.tm.opcode_modifier.evex = EVEXLIG; | |
13502 | ||
13503 | build_evex_prefix (); | |
13504 | i.rex &= REX_OPCODE; | |
13505 | } | |
ce705688 JB |
13506 | else |
13507 | establish_rex (); | |
d0c2e3ec | 13508 | |
b5482fe5 JB |
13509 | last_insn = &seg_info(now_seg)->tc_segment_info_data.last_insn; |
13510 | output_insn (last_insn); | |
13511 | last_insn->kind = last_insn_directive; | |
13512 | last_insn->name = ".insn directive"; | |
13513 | last_insn->file = as_where (&last_insn->line); | |
edd67638 | 13514 | |
c7defc53 IB |
13515 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
13516 | /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been | |
13517 | performed in i386_target_format. */ | |
13518 | if (IS_ELF && flag_synth_cfi) | |
13519 | as_bad (_("SCFI: hand-crafting instructions not supported")); | |
13520 | #endif | |
13521 | ||
d0c2e3ec | 13522 | done: |
edd67638 JB |
13523 | *saved_ilp = saved_char; |
13524 | input_line_pointer = line; | |
13525 | ||
13526 | demand_empty_rest_of_line (); | |
d0c2e3ec JB |
13527 | |
13528 | /* Make sure dot_insn() won't yield "true" anymore. */ | |
13529 | i.tm.mnem_off = 0; | |
edd67638 JB |
13530 | } |
13531 | ||
d182319b | 13532 | #ifdef TE_PE |
6482c264 | 13533 | static void |
7016a5d5 | 13534 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
13535 | { |
13536 | expressionS exp; | |
13537 | ||
13538 | do | |
13539 | { | |
13540 | expression (&exp); | |
13541 | if (exp.X_op == O_symbol) | |
13542 | exp.X_op = O_secrel; | |
13543 | ||
13544 | emit_expr (&exp, 4); | |
13545 | } | |
13546 | while (*input_line_pointer++ == ','); | |
13547 | ||
13548 | input_line_pointer--; | |
13549 | demand_empty_rest_of_line (); | |
13550 | } | |
145667f8 MH |
13551 | |
13552 | static void | |
13553 | pe_directive_secidx (int dummy ATTRIBUTE_UNUSED) | |
13554 | { | |
13555 | expressionS exp; | |
13556 | ||
13557 | do | |
13558 | { | |
13559 | expression (&exp); | |
13560 | if (exp.X_op == O_symbol) | |
13561 | exp.X_op = O_secidx; | |
13562 | ||
13563 | emit_expr (&exp, 2); | |
13564 | } | |
13565 | while (*input_line_pointer++ == ','); | |
13566 | ||
13567 | input_line_pointer--; | |
13568 | demand_empty_rest_of_line (); | |
13569 | } | |
6482c264 NC |
13570 | #endif |
13571 | ||
7063667e JB |
13572 | /* Handle Rounding Control / SAE specifiers. */ |
13573 | ||
13574 | static char * | |
13575 | RC_SAE_specifier (const char *pstr) | |
13576 | { | |
13577 | unsigned int j; | |
13578 | ||
13579 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
13580 | { | |
13581 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
13582 | { | |
13583 | if (i.rounding.type != rc_none) | |
13584 | { | |
13585 | as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name); | |
13586 | return NULL; | |
13587 | } | |
13588 | ||
eb3f3841 JB |
13589 | switch (i.encoding) |
13590 | { | |
13591 | case encoding_default: | |
13592 | case encoding_egpr: | |
13593 | i.encoding = encoding_evex512; | |
13594 | break; | |
13595 | case encoding_evex: | |
13596 | case encoding_evex512: | |
13597 | break; | |
13598 | default: | |
13599 | return NULL; | |
13600 | } | |
a6f3add0 | 13601 | |
7063667e JB |
13602 | i.rounding.type = RC_NamesTable[j].type; |
13603 | ||
13604 | return (char *)(pstr + RC_NamesTable[j].len); | |
13605 | } | |
13606 | } | |
13607 | ||
13608 | return NULL; | |
13609 | } | |
13610 | ||
43234a1e L |
13611 | /* Handle Vector operations. */ |
13612 | ||
13613 | static char * | |
f70c6814 | 13614 | check_VecOperations (char *op_string) |
43234a1e L |
13615 | { |
13616 | const reg_entry *mask; | |
13617 | const char *saved; | |
13618 | char *end_op; | |
13619 | ||
f70c6814 | 13620 | while (*op_string) |
43234a1e L |
13621 | { |
13622 | saved = op_string; | |
13623 | if (*op_string == '{') | |
13624 | { | |
13625 | op_string++; | |
13626 | ||
13627 | /* Check broadcasts. */ | |
d34049e8 | 13628 | if (startswith (op_string, "1to")) |
43234a1e | 13629 | { |
5273a3cd | 13630 | unsigned int bcst_type; |
43234a1e | 13631 | |
5273a3cd | 13632 | if (i.broadcast.type) |
43234a1e L |
13633 | goto duplicated_vec_op; |
13634 | ||
13635 | op_string += 3; | |
13636 | if (*op_string == '8') | |
8e6e0792 | 13637 | bcst_type = 8; |
b28d1bda | 13638 | else if (*op_string == '4') |
8e6e0792 | 13639 | bcst_type = 4; |
b28d1bda | 13640 | else if (*op_string == '2') |
8e6e0792 | 13641 | bcst_type = 2; |
43234a1e L |
13642 | else if (*op_string == '1' |
13643 | && *(op_string+1) == '6') | |
13644 | { | |
8e6e0792 | 13645 | bcst_type = 16; |
43234a1e L |
13646 | op_string++; |
13647 | } | |
0cc78721 CL |
13648 | else if (*op_string == '3' |
13649 | && *(op_string+1) == '2') | |
13650 | { | |
13651 | bcst_type = 32; | |
13652 | op_string++; | |
13653 | } | |
43234a1e L |
13654 | else |
13655 | { | |
13656 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
13657 | return NULL; | |
13658 | } | |
13659 | op_string++; | |
13660 | ||
eb3f3841 JB |
13661 | switch (i.encoding) |
13662 | { | |
13663 | case encoding_default: | |
13664 | case encoding_egpr: | |
13665 | i.encoding = encoding_evex; | |
13666 | break; | |
13667 | case encoding_evex: | |
13668 | case encoding_evex512: | |
13669 | break; | |
13670 | default: | |
13671 | goto unknown_vec_op; | |
13672 | } | |
a6f3add0 | 13673 | |
5273a3cd JB |
13674 | i.broadcast.type = bcst_type; |
13675 | i.broadcast.operand = this_operand; | |
f7377a91 JB |
13676 | |
13677 | /* For .insn a data size specifier may be appended. */ | |
13678 | if (dot_insn () && *op_string == ':') | |
13679 | goto dot_insn_modifier; | |
13680 | } | |
13681 | /* Check .insn special cases. */ | |
13682 | else if (dot_insn () && *op_string == ':') | |
13683 | { | |
13684 | dot_insn_modifier: | |
c032bc4f | 13685 | switch (op_string[1]) |
f7377a91 JB |
13686 | { |
13687 | unsigned long n; | |
13688 | ||
c032bc4f | 13689 | case 'd': |
f7377a91 JB |
13690 | if (i.memshift < 32) |
13691 | goto duplicated_vec_op; | |
13692 | ||
13693 | n = strtoul (op_string + 2, &end_op, 0); | |
13694 | if (n) | |
13695 | for (i.memshift = 0; !(n & 1); n >>= 1) | |
13696 | ++i.memshift; | |
13697 | if (i.memshift < 32 && n == 1) | |
13698 | op_string = end_op; | |
c032bc4f JB |
13699 | break; |
13700 | ||
13701 | case 's': case 'u': | |
13702 | /* This isn't really a "vector" operation, but a sign/size | |
13703 | specifier for immediate operands of .insn. Note that AT&T | |
13704 | syntax handles the same in i386_immediate(). */ | |
13705 | if (!intel_syntax) | |
13706 | break; | |
13707 | ||
13708 | if (i.imm_bits[this_operand]) | |
13709 | goto duplicated_vec_op; | |
13710 | ||
13711 | n = strtoul (op_string + 2, &end_op, 0); | |
13712 | if (n && n <= (flag_code == CODE_64BIT ? 64 : 32)) | |
13713 | { | |
13714 | i.imm_bits[this_operand] = n; | |
13715 | if (op_string[1] == 's') | |
13716 | i.flags[this_operand] |= Operand_Signed; | |
13717 | op_string = end_op; | |
13718 | } | |
13719 | break; | |
f7377a91 | 13720 | } |
43234a1e L |
13721 | } |
13722 | /* Check masking operation. */ | |
13723 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
13724 | { | |
8a6fb3f9 JB |
13725 | if (mask == &bad_reg) |
13726 | return NULL; | |
13727 | ||
43234a1e | 13728 | /* k0 can't be used for write mask. */ |
f74a6307 | 13729 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 13730 | { |
6d2cd6b2 JB |
13731 | as_bad (_("`%s%s' can't be used for write mask"), |
13732 | register_prefix, mask->reg_name); | |
43234a1e L |
13733 | return NULL; |
13734 | } | |
13735 | ||
6225c532 | 13736 | if (!i.mask.reg) |
43234a1e | 13737 | { |
6225c532 JB |
13738 | i.mask.reg = mask; |
13739 | i.mask.operand = this_operand; | |
43234a1e | 13740 | } |
6225c532 JB |
13741 | else if (i.mask.reg->reg_num) |
13742 | goto duplicated_vec_op; | |
43234a1e L |
13743 | else |
13744 | { | |
6225c532 | 13745 | i.mask.reg = mask; |
43234a1e L |
13746 | |
13747 | /* Only "{z}" is allowed here. No need to check | |
13748 | zeroing mask explicitly. */ | |
6225c532 | 13749 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
13750 | { |
13751 | as_bad (_("invalid write mask `%s'"), saved); | |
13752 | return NULL; | |
13753 | } | |
13754 | } | |
13755 | ||
13756 | op_string = end_op; | |
13757 | } | |
13758 | /* Check zeroing-flag for masking operation. */ | |
13759 | else if (*op_string == 'z') | |
13760 | { | |
6225c532 | 13761 | if (!i.mask.reg) |
43234a1e | 13762 | { |
6225c532 JB |
13763 | i.mask.reg = reg_k0; |
13764 | i.mask.zeroing = 1; | |
13765 | i.mask.operand = this_operand; | |
43234a1e L |
13766 | } |
13767 | else | |
13768 | { | |
6225c532 | 13769 | if (i.mask.zeroing) |
43234a1e L |
13770 | { |
13771 | duplicated_vec_op: | |
13772 | as_bad (_("duplicated `%s'"), saved); | |
13773 | return NULL; | |
13774 | } | |
13775 | ||
6225c532 | 13776 | i.mask.zeroing = 1; |
43234a1e L |
13777 | |
13778 | /* Only "{%k}" is allowed here. No need to check mask | |
13779 | register explicitly. */ | |
6225c532 | 13780 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
13781 | { |
13782 | as_bad (_("invalid zeroing-masking `%s'"), | |
13783 | saved); | |
13784 | return NULL; | |
13785 | } | |
13786 | } | |
13787 | ||
13788 | op_string++; | |
13789 | } | |
7063667e JB |
13790 | else if (intel_syntax |
13791 | && (op_string = RC_SAE_specifier (op_string)) != NULL) | |
13792 | i.rounding.modifier = true; | |
43234a1e L |
13793 | else |
13794 | goto unknown_vec_op; | |
13795 | ||
13796 | if (*op_string != '}') | |
13797 | { | |
13798 | as_bad (_("missing `}' in `%s'"), saved); | |
13799 | return NULL; | |
13800 | } | |
13801 | op_string++; | |
0ba3a731 L |
13802 | |
13803 | /* Strip whitespace since the addition of pseudo prefixes | |
13804 | changed how the scrubber treats '{'. */ | |
13805 | if (is_space_char (*op_string)) | |
13806 | ++op_string; | |
13807 | ||
43234a1e L |
13808 | continue; |
13809 | } | |
13810 | unknown_vec_op: | |
13811 | /* We don't know this one. */ | |
13812 | as_bad (_("unknown vector operation: `%s'"), saved); | |
13813 | return NULL; | |
13814 | } | |
13815 | ||
6225c532 | 13816 | if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num) |
6d2cd6b2 JB |
13817 | { |
13818 | as_bad (_("zeroing-masking only allowed with write mask")); | |
13819 | return NULL; | |
13820 | } | |
13821 | ||
43234a1e L |
13822 | return op_string; |
13823 | } | |
13824 | ||
252b5132 | 13825 | static int |
70e41ade | 13826 | i386_immediate (char *imm_start) |
252b5132 RH |
13827 | { |
13828 | char *save_input_line_pointer; | |
f3c180ae | 13829 | char *gotfree_input_line; |
252b5132 | 13830 | segT exp_seg = 0; |
47926f60 | 13831 | expressionS *exp; |
40fb9820 L |
13832 | i386_operand_type types; |
13833 | ||
0dfbf9d7 | 13834 | operand_type_set (&types, ~0); |
252b5132 RH |
13835 | |
13836 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
13837 | { | |
31b2323c L |
13838 | as_bad (_("at most %d immediate operands are allowed"), |
13839 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
13840 | return 0; |
13841 | } | |
13842 | ||
13843 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 13844 | i.op[this_operand].imms = exp; |
252b5132 RH |
13845 | |
13846 | if (is_space_char (*imm_start)) | |
13847 | ++imm_start; | |
13848 | ||
13849 | save_input_line_pointer = input_line_pointer; | |
13850 | input_line_pointer = imm_start; | |
13851 | ||
d258b828 | 13852 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
13853 | if (gotfree_input_line) |
13854 | input_line_pointer = gotfree_input_line; | |
252b5132 | 13855 | |
5cc00775 | 13856 | expr_mode = expr_operator_none; |
252b5132 RH |
13857 | exp_seg = expression (exp); |
13858 | ||
c032bc4f JB |
13859 | /* For .insn immediates there may be a size specifier. */ |
13860 | if (dot_insn () && *input_line_pointer == '{' && input_line_pointer[1] == ':' | |
13861 | && (input_line_pointer[2] == 's' || input_line_pointer[2] == 'u')) | |
13862 | { | |
13863 | char *e; | |
13864 | unsigned long n = strtoul (input_line_pointer + 3, &e, 0); | |
13865 | ||
13866 | if (*e == '}' && n && n <= (flag_code == CODE_64BIT ? 64 : 32)) | |
13867 | { | |
13868 | i.imm_bits[this_operand] = n; | |
13869 | if (input_line_pointer[2] == 's') | |
13870 | i.flags[this_operand] |= Operand_Signed; | |
13871 | input_line_pointer = e + 1; | |
13872 | } | |
13873 | } | |
13874 | ||
83183c0c | 13875 | SKIP_WHITESPACE (); |
252b5132 | 13876 | if (*input_line_pointer) |
f3c180ae | 13877 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
13878 | |
13879 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 13880 | if (gotfree_input_line) |
ee86248c JB |
13881 | { |
13882 | free (gotfree_input_line); | |
13883 | ||
9aac24b1 | 13884 | if (exp->X_op == O_constant) |
ee86248c JB |
13885 | exp->X_op = O_illegal; |
13886 | } | |
13887 | ||
9aac24b1 JB |
13888 | if (exp_seg == reg_section) |
13889 | { | |
13890 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
13891 | return 0; | |
13892 | } | |
13893 | ||
ee86248c JB |
13894 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
13895 | } | |
252b5132 | 13896 | |
ee86248c JB |
13897 | static int |
13898 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
13899 | i386_operand_type types, const char *imm_start) | |
13900 | { | |
13901 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 13902 | { |
313c53d1 L |
13903 | if (imm_start) |
13904 | as_bad (_("missing or invalid immediate expression `%s'"), | |
13905 | imm_start); | |
3992d3b7 | 13906 | return 0; |
252b5132 | 13907 | } |
3e73aa7c | 13908 | else if (exp->X_op == O_constant) |
252b5132 | 13909 | { |
47926f60 | 13910 | /* Size it properly later. */ |
40fb9820 | 13911 | i.types[this_operand].bitfield.imm64 = 1; |
a442cac5 JB |
13912 | |
13913 | /* If not 64bit, sign/zero extend val, to account for wraparound | |
13914 | when !BFD64. */ | |
5cc00775 JB |
13915 | if (expr_mode == expr_operator_present |
13916 | && flag_code != CODE_64BIT && !object_64bit) | |
a442cac5 | 13917 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
252b5132 | 13918 | } |
4c63da97 | 13919 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 13920 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 13921 | && exp_seg != absolute_section |
47926f60 | 13922 | && exp_seg != text_section |
24eab124 AM |
13923 | && exp_seg != data_section |
13924 | && exp_seg != bss_section | |
13925 | && exp_seg != undefined_section | |
f86103b7 | 13926 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 13927 | { |
d0b47220 | 13928 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
13929 | return 0; |
13930 | } | |
13931 | #endif | |
13932 | else | |
13933 | { | |
13934 | /* This is an address. The size of the address will be | |
24eab124 | 13935 | determined later, depending on destination register, |
3e73aa7c | 13936 | suffix, or the default for the section. */ |
40fb9820 L |
13937 | i.types[this_operand].bitfield.imm8 = 1; |
13938 | i.types[this_operand].bitfield.imm16 = 1; | |
13939 | i.types[this_operand].bitfield.imm32 = 1; | |
13940 | i.types[this_operand].bitfield.imm32s = 1; | |
13941 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
13942 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
13943 | types); | |
252b5132 RH |
13944 | } |
13945 | ||
13946 | return 1; | |
13947 | } | |
13948 | ||
551c1ca1 | 13949 | static char * |
e3bb37b5 | 13950 | i386_scale (char *scale) |
252b5132 | 13951 | { |
551c1ca1 AM |
13952 | offsetT val; |
13953 | char *save = input_line_pointer; | |
252b5132 | 13954 | |
551c1ca1 AM |
13955 | input_line_pointer = scale; |
13956 | val = get_absolute_expression (); | |
13957 | ||
13958 | switch (val) | |
252b5132 | 13959 | { |
551c1ca1 | 13960 | case 1: |
252b5132 RH |
13961 | i.log2_scale_factor = 0; |
13962 | break; | |
551c1ca1 | 13963 | case 2: |
252b5132 RH |
13964 | i.log2_scale_factor = 1; |
13965 | break; | |
551c1ca1 | 13966 | case 4: |
252b5132 RH |
13967 | i.log2_scale_factor = 2; |
13968 | break; | |
551c1ca1 | 13969 | case 8: |
252b5132 RH |
13970 | i.log2_scale_factor = 3; |
13971 | break; | |
13972 | default: | |
a724f0f4 JB |
13973 | { |
13974 | char sep = *input_line_pointer; | |
13975 | ||
13976 | *input_line_pointer = '\0'; | |
13977 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
13978 | scale); | |
13979 | *input_line_pointer = sep; | |
13980 | input_line_pointer = save; | |
13981 | return NULL; | |
13982 | } | |
252b5132 | 13983 | } |
29b0f896 | 13984 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
13985 | { |
13986 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 13987 | 1 << i.log2_scale_factor); |
252b5132 | 13988 | i.log2_scale_factor = 0; |
252b5132 | 13989 | } |
551c1ca1 AM |
13990 | scale = input_line_pointer; |
13991 | input_line_pointer = save; | |
13992 | return scale; | |
252b5132 RH |
13993 | } |
13994 | ||
252b5132 | 13995 | static int |
e3bb37b5 | 13996 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 13997 | { |
29b0f896 | 13998 | expressionS *exp; |
252b5132 RH |
13999 | segT exp_seg = 0; |
14000 | char *save_input_line_pointer; | |
f3c180ae | 14001 | char *gotfree_input_line; |
40fb9820 L |
14002 | int override; |
14003 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 14004 | int ret; |
252b5132 | 14005 | |
31b2323c L |
14006 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
14007 | { | |
14008 | as_bad (_("at most %d displacement operands are allowed"), | |
14009 | MAX_MEMORY_OPERANDS); | |
14010 | return 0; | |
14011 | } | |
14012 | ||
0dfbf9d7 | 14013 | operand_type_set (&bigdisp, 0); |
6f2f06be | 14014 | if (i.jumpabsolute |
48bcea9f | 14015 | || i.types[this_operand].bitfield.baseindex |
d3b01414 JB |
14016 | || (current_templates.start->opcode_modifier.jump != JUMP |
14017 | && current_templates.start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 14018 | { |
48bcea9f | 14019 | i386_addressing_mode (); |
e05278af | 14020 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
14021 | if (flag_code == CODE_64BIT) |
14022 | { | |
a775efc8 | 14023 | bigdisp.bitfield.disp32 = 1; |
40fb9820 | 14024 | if (!override) |
a775efc8 | 14025 | bigdisp.bitfield.disp64 = 1; |
40fb9820 L |
14026 | } |
14027 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 14028 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
14029 | else |
14030 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
14031 | } |
14032 | else | |
14033 | { | |
376cd056 JB |
14034 | /* For PC-relative branches, the width of the displacement may be |
14035 | dependent upon data size, but is never dependent upon address size. | |
14036 | Also make sure to not unintentionally match against a non-PC-relative | |
14037 | branch template. */ | |
d3b01414 | 14038 | const insn_template *t = current_templates.start; |
5b7c81bd | 14039 | bool has_intel64 = false; |
376cd056 | 14040 | |
d3b01414 | 14041 | while (++t < current_templates.end) |
376cd056 JB |
14042 | { |
14043 | if (t->opcode_modifier.jump | |
d3b01414 | 14044 | != current_templates.start->opcode_modifier.jump) |
376cd056 | 14045 | break; |
4b5aaf5f | 14046 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
5b7c81bd | 14047 | has_intel64 = true; |
376cd056 | 14048 | } |
d3b01414 | 14049 | current_templates.end = t; |
376cd056 | 14050 | |
e05278af | 14051 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
14052 | if (flag_code == CODE_64BIT) |
14053 | { | |
376cd056 JB |
14054 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
14055 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
14056 | bigdisp.bitfield.disp16 = 1; |
14057 | else | |
a775efc8 | 14058 | bigdisp.bitfield.disp32 = 1; |
40fb9820 L |
14059 | } |
14060 | else | |
e05278af JB |
14061 | { |
14062 | if (!override) | |
14063 | override = (i.suffix == (flag_code != CODE_16BIT | |
14064 | ? WORD_MNEM_SUFFIX | |
14065 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
14066 | bigdisp.bitfield.disp32 = 1; |
14067 | if ((flag_code == CODE_16BIT) ^ override) | |
14068 | { | |
14069 | bigdisp.bitfield.disp32 = 0; | |
14070 | bigdisp.bitfield.disp16 = 1; | |
14071 | } | |
e05278af | 14072 | } |
e05278af | 14073 | } |
c6fb90c8 L |
14074 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
14075 | bigdisp); | |
252b5132 RH |
14076 | |
14077 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 14078 | i.op[this_operand].disps = exp; |
252b5132 RH |
14079 | i.disp_operands++; |
14080 | save_input_line_pointer = input_line_pointer; | |
14081 | input_line_pointer = disp_start; | |
14082 | END_STRING_AND_SAVE (disp_end); | |
14083 | ||
14084 | #ifndef GCC_ASM_O_HACK | |
14085 | #define GCC_ASM_O_HACK 0 | |
14086 | #endif | |
14087 | #if GCC_ASM_O_HACK | |
14088 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 14089 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 14090 | && displacement_string_end[-1] == '+') |
252b5132 RH |
14091 | { |
14092 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
14093 | constraint within gcc asm statements. |
14094 | For instance: | |
14095 | ||
14096 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
14097 | __asm__ __volatile__ ( \ | |
14098 | "movw %w2,%0\n\t" \ | |
14099 | "movw %w1,2+%0\n\t" \ | |
14100 | "rorl $16,%1\n\t" \ | |
14101 | "movb %b1,4+%0\n\t" \ | |
14102 | "movb %4,5+%0\n\t" \ | |
14103 | "movb $0,6+%0\n\t" \ | |
14104 | "movb %h1,7+%0\n\t" \ | |
14105 | "rorl $16,%1" \ | |
14106 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
14107 | ||
14108 | This works great except that the output assembler ends | |
14109 | up looking a bit weird if it turns out that there is | |
14110 | no offset. You end up producing code that looks like: | |
14111 | ||
14112 | #APP | |
14113 | movw $235,(%eax) | |
14114 | movw %dx,2+(%eax) | |
14115 | rorl $16,%edx | |
14116 | movb %dl,4+(%eax) | |
14117 | movb $137,5+(%eax) | |
14118 | movb $0,6+(%eax) | |
14119 | movb %dh,7+(%eax) | |
14120 | rorl $16,%edx | |
14121 | #NO_APP | |
14122 | ||
47926f60 | 14123 | So here we provide the missing zero. */ |
24eab124 AM |
14124 | |
14125 | *displacement_string_end = '0'; | |
252b5132 RH |
14126 | } |
14127 | #endif | |
d258b828 | 14128 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
14129 | if (gotfree_input_line) |
14130 | input_line_pointer = gotfree_input_line; | |
252b5132 | 14131 | |
5cc00775 | 14132 | expr_mode = expr_operator_none; |
24eab124 | 14133 | exp_seg = expression (exp); |
252b5132 | 14134 | |
636c26b0 AM |
14135 | SKIP_WHITESPACE (); |
14136 | if (*input_line_pointer) | |
14137 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
14138 | #if GCC_ASM_O_HACK | |
14139 | RESTORE_END_STRING (disp_end + 1); | |
14140 | #endif | |
636c26b0 | 14141 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 14142 | if (gotfree_input_line) |
ee86248c JB |
14143 | { |
14144 | free (gotfree_input_line); | |
14145 | ||
14146 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
14147 | exp->X_op = O_illegal; | |
14148 | } | |
14149 | ||
14150 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
14151 | ||
14152 | RESTORE_END_STRING (disp_end); | |
14153 | ||
14154 | return ret; | |
14155 | } | |
14156 | ||
14157 | static int | |
14158 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
14159 | i386_operand_type types, const char *disp_start) | |
14160 | { | |
ee86248c | 14161 | int ret = 1; |
636c26b0 | 14162 | |
24eab124 AM |
14163 | /* We do this to make sure that the section symbol is in |
14164 | the symbol table. We will ultimately change the relocation | |
47926f60 | 14165 | to be relative to the beginning of the section. */ |
1ae12ab7 | 14166 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
14167 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
14168 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 14169 | { |
636c26b0 | 14170 | if (exp->X_op != O_symbol) |
3992d3b7 | 14171 | goto inv_disp; |
636c26b0 | 14172 | |
e5cb08ac | 14173 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
14174 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
14175 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 14176 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
14177 | exp->X_op = O_subtract; |
14178 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 14179 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 14180 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
14181 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
14182 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 14183 | else |
29b0f896 | 14184 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 14185 | } |
252b5132 | 14186 | |
3992d3b7 AM |
14187 | else if (exp->X_op == O_absent |
14188 | || exp->X_op == O_illegal | |
ee86248c | 14189 | || exp->X_op == O_big) |
2daf4fd8 | 14190 | { |
3992d3b7 AM |
14191 | inv_disp: |
14192 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 14193 | disp_start); |
3992d3b7 | 14194 | ret = 0; |
2daf4fd8 AM |
14195 | } |
14196 | ||
a50187b2 JB |
14197 | else if (exp->X_op == O_constant) |
14198 | { | |
14199 | /* Sizing gets taken care of by optimize_disp(). | |
14200 | ||
14201 | If not 64bit, sign/zero extend val, to account for wraparound | |
14202 | when !BFD64. */ | |
5cc00775 JB |
14203 | if (expr_mode == expr_operator_present |
14204 | && flag_code != CODE_64BIT && !object_64bit) | |
a50187b2 JB |
14205 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
14206 | } | |
14207 | ||
4c63da97 | 14208 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
a50187b2 | 14209 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
3992d3b7 AM |
14210 | && exp_seg != absolute_section |
14211 | && exp_seg != text_section | |
14212 | && exp_seg != data_section | |
14213 | && exp_seg != bss_section | |
14214 | && exp_seg != undefined_section | |
14215 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 14216 | { |
d0b47220 | 14217 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 14218 | ret = 0; |
24eab124 | 14219 | } |
252b5132 | 14220 | #endif |
3956db08 | 14221 | |
d3b01414 | 14222 | else if (current_templates.start->opcode_modifier.jump == JUMP_BYTE) |
48bcea9f JB |
14223 | i.types[this_operand].bitfield.disp8 = 1; |
14224 | ||
40fb9820 | 14225 | /* Check if this is a displacement only operand. */ |
02b83698 JB |
14226 | if (!i.types[this_operand].bitfield.baseindex) |
14227 | i.types[this_operand] = | |
14228 | operand_type_or (operand_type_and_not (i.types[this_operand], anydisp), | |
14229 | operand_type_and (i.types[this_operand], types)); | |
3956db08 | 14230 | |
3992d3b7 | 14231 | return ret; |
252b5132 RH |
14232 | } |
14233 | ||
2abc2bec JB |
14234 | /* Return the active addressing mode, taking address override and |
14235 | registers forming the address into consideration. Update the | |
14236 | address override prefix if necessary. */ | |
47926f60 | 14237 | |
2abc2bec JB |
14238 | static enum flag_code |
14239 | i386_addressing_mode (void) | |
252b5132 | 14240 | { |
be05d201 L |
14241 | enum flag_code addr_mode; |
14242 | ||
14243 | if (i.prefix[ADDR_PREFIX]) | |
14244 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 | 14245 | else if (flag_code == CODE_16BIT |
d3b01414 | 14246 | && is_cpu (current_templates.start, CpuMPX) |
a23b33b3 JB |
14247 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic |
14248 | from md_assemble() by "is not a valid base/index expression" | |
14249 | when there is a base and/or index. */ | |
14250 | && !i.types[this_operand].bitfield.baseindex) | |
14251 | { | |
14252 | /* MPX insn memory operands with neither base nor index must be forced | |
14253 | to use 32-bit addressing in 16-bit mode. */ | |
14254 | addr_mode = CODE_32BIT; | |
14255 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
14256 | ++i.prefixes; | |
14257 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
14258 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
14259 | } | |
be05d201 L |
14260 | else |
14261 | { | |
14262 | addr_mode = flag_code; | |
14263 | ||
24eab124 | 14264 | #if INFER_ADDR_PREFIX |
be05d201 L |
14265 | if (i.mem_operands == 0) |
14266 | { | |
14267 | /* Infer address prefix from the first memory operand. */ | |
14268 | const reg_entry *addr_reg = i.base_reg; | |
14269 | ||
14270 | if (addr_reg == NULL) | |
14271 | addr_reg = i.index_reg; | |
eecb386c | 14272 | |
be05d201 L |
14273 | if (addr_reg) |
14274 | { | |
e968fc9b | 14275 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
14276 | addr_mode = CODE_32BIT; |
14277 | else if (flag_code != CODE_64BIT | |
dc821c5f | 14278 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
14279 | addr_mode = CODE_16BIT; |
14280 | ||
14281 | if (addr_mode != flag_code) | |
14282 | { | |
14283 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
14284 | i.prefixes += 1; | |
14285 | /* Change the size of any displacement too. At most one | |
14286 | of Disp16 or Disp32 is set. | |
14287 | FIXME. There doesn't seem to be any real need for | |
14288 | separate Disp16 and Disp32 flags. The same goes for | |
14289 | Imm16 and Imm32. Removing them would probably clean | |
14290 | up the code quite a lot. */ | |
14291 | if (flag_code != CODE_64BIT | |
14292 | && (i.types[this_operand].bitfield.disp16 | |
14293 | || i.types[this_operand].bitfield.disp32)) | |
05909f23 JB |
14294 | { |
14295 | static const i386_operand_type disp16_32 = { | |
14296 | .bitfield = { .disp16 = 1, .disp32 = 1 } | |
14297 | }; | |
14298 | ||
14299 | i.types[this_operand] | |
14300 | = operand_type_xor (i.types[this_operand], disp16_32); | |
14301 | } | |
be05d201 L |
14302 | } |
14303 | } | |
14304 | } | |
24eab124 | 14305 | #endif |
be05d201 L |
14306 | } |
14307 | ||
2abc2bec JB |
14308 | return addr_mode; |
14309 | } | |
14310 | ||
14311 | /* Make sure the memory operand we've been dealt is valid. | |
14312 | Return 1 on success, 0 on a failure. */ | |
14313 | ||
14314 | static int | |
14315 | i386_index_check (const char *operand_string) | |
14316 | { | |
14317 | const char *kind = "base/index"; | |
14318 | enum flag_code addr_mode = i386_addressing_mode (); | |
d3b01414 | 14319 | const insn_template *t = current_templates.end - 1; |
2abc2bec | 14320 | |
77a19f0e | 14321 | if (t->opcode_modifier.isstring) |
fc0763e6 JB |
14322 | { |
14323 | /* Memory operands of string insns are special in that they only allow | |
14324 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 | 14325 | const reg_entry *expected_reg; |
069a1561 | 14326 | static const char di_si[][2][4] = |
be05d201 L |
14327 | { |
14328 | { "esi", "edi" }, | |
14329 | { "si", "di" }, | |
14330 | { "rsi", "rdi" } | |
14331 | }; | |
069a1561 | 14332 | static const char bx[][4] = { "ebx", "bx", "rbx" }; |
fc0763e6 JB |
14333 | |
14334 | kind = "string address"; | |
14335 | ||
a152332d | 14336 | if (t->opcode_modifier.prefixok == PrefixRep) |
fc0763e6 | 14337 | { |
77a19f0e | 14338 | int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0; |
51c8edf6 | 14339 | int op = 0; |
fc0763e6 | 14340 | |
77a19f0e | 14341 | if (!t->operand_types[0].bitfield.baseindex |
fc0763e6 | 14342 | || ((!i.mem_operands != !intel_syntax) |
77a19f0e | 14343 | && t->operand_types[1].bitfield.baseindex)) |
51c8edf6 | 14344 | op = 1; |
fe0e921f AM |
14345 | expected_reg |
14346 | = (const reg_entry *) str_hash_find (reg_hash, | |
14347 | di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
14348 | } |
14349 | else | |
fe0e921f AM |
14350 | expected_reg |
14351 | = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); | |
fc0763e6 | 14352 | |
be05d201 L |
14353 | if (i.base_reg != expected_reg |
14354 | || i.index_reg | |
fc0763e6 | 14355 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 14356 | { |
be05d201 L |
14357 | /* The second memory operand must have the same size as |
14358 | the first one. */ | |
14359 | if (i.mem_operands | |
14360 | && i.base_reg | |
14361 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 14362 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 14363 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
14364 | ? i.base_reg->reg_type.bitfield.dword |
14365 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
14366 | goto bad_address; |
14367 | ||
fc0763e6 JB |
14368 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
14369 | operand_string, | |
14370 | intel_syntax ? '[' : '(', | |
14371 | register_prefix, | |
be05d201 | 14372 | expected_reg->reg_name, |
fc0763e6 | 14373 | intel_syntax ? ']' : ')'); |
be05d201 | 14374 | return 1; |
fc0763e6 | 14375 | } |
be05d201 L |
14376 | else |
14377 | return 1; | |
14378 | ||
dc1e8a47 | 14379 | bad_address: |
be05d201 L |
14380 | as_bad (_("`%s' is not a valid %s expression"), |
14381 | operand_string, kind); | |
14382 | return 0; | |
3e73aa7c JH |
14383 | } |
14384 | else | |
14385 | { | |
d3b01414 | 14386 | t = current_templates.start; |
77a19f0e | 14387 | |
be05d201 L |
14388 | if (addr_mode != CODE_16BIT) |
14389 | { | |
14390 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
14391 | if (i.disp_encoding == disp_encoding_16bit) |
14392 | { | |
14393 | bad_disp: | |
14394 | as_bad (_("invalid `%s' prefix"), | |
14395 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
14396 | return 0; | |
14397 | } | |
14398 | ||
be05d201 | 14399 | if ((i.base_reg |
e968fc9b JB |
14400 | && ((addr_mode == CODE_64BIT |
14401 | ? !i.base_reg->reg_type.bitfield.qword | |
14402 | : !i.base_reg->reg_type.bitfield.dword) | |
14403 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
14404 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 14405 | || (i.index_reg |
1b54b8d7 JB |
14406 | && !i.index_reg->reg_type.bitfield.xmmword |
14407 | && !i.index_reg->reg_type.bitfield.ymmword | |
14408 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 14409 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
14410 | ? !i.index_reg->reg_type.bitfield.qword |
14411 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
14412 | || !i.index_reg->reg_type.bitfield.baseindex))) |
14413 | goto bad_address; | |
8178be5b | 14414 | |
260cd341 | 14415 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
7fc69528 JB |
14416 | if (t->mnem_off == MN_bndmk |
14417 | || t->mnem_off == MN_bndldx | |
14418 | || t->mnem_off == MN_bndstx | |
a152332d | 14419 | || t->opcode_modifier.sib == SIBMEM) |
8178be5b JB |
14420 | { |
14421 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 14422 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
14423 | { |
14424 | as_bad (_("`%s' cannot be used here"), operand_string); | |
14425 | return 0; | |
14426 | } | |
14427 | ||
14428 | /* bndldx and bndstx ignore their scale factor. */ | |
7fc69528 | 14429 | if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx) |
8178be5b JB |
14430 | && i.log2_scale_factor) |
14431 | as_warn (_("register scaling is being ignored here")); | |
14432 | } | |
be05d201 L |
14433 | } |
14434 | else | |
3e73aa7c | 14435 | { |
be05d201 | 14436 | /* 16-bit checks. */ |
41eb8e88 L |
14437 | if (i.disp_encoding == disp_encoding_32bit) |
14438 | goto bad_disp; | |
14439 | ||
3e73aa7c | 14440 | if ((i.base_reg |
dc821c5f | 14441 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 14442 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 14443 | || (i.index_reg |
dc821c5f | 14444 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 14445 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
14446 | || !(i.base_reg |
14447 | && i.base_reg->reg_num < 6 | |
14448 | && i.index_reg->reg_num >= 6 | |
14449 | && i.log2_scale_factor == 0)))) | |
be05d201 | 14450 | goto bad_address; |
3e73aa7c JH |
14451 | } |
14452 | } | |
be05d201 | 14453 | return 1; |
24eab124 | 14454 | } |
252b5132 | 14455 | |
43234a1e L |
14456 | /* Handle vector immediates. */ |
14457 | ||
14458 | static int | |
14459 | RC_SAE_immediate (const char *imm_start) | |
14460 | { | |
43234a1e | 14461 | const char *pstr = imm_start; |
43234a1e L |
14462 | |
14463 | if (*pstr != '{') | |
14464 | return 0; | |
14465 | ||
7063667e JB |
14466 | pstr = RC_SAE_specifier (pstr + 1); |
14467 | if (pstr == NULL) | |
43234a1e L |
14468 | return 0; |
14469 | ||
14470 | if (*pstr++ != '}') | |
14471 | { | |
14472 | as_bad (_("Missing '}': '%s'"), imm_start); | |
14473 | return 0; | |
14474 | } | |
14475 | /* RC/SAE immediate string should contain nothing more. */; | |
14476 | if (*pstr != 0) | |
14477 | { | |
14478 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
14479 | return 0; | |
14480 | } | |
14481 | ||
cf665fee JB |
14482 | /* Internally this doesn't count as an operand. */ |
14483 | --i.operands; | |
43234a1e | 14484 | |
43234a1e L |
14485 | return 1; |
14486 | } | |
14487 | ||
9d299bea JB |
14488 | static INLINE bool starts_memory_operand (char c) |
14489 | { | |
014fbcda | 14490 | return ISDIGIT (c) |
4795cd4a | 14491 | || is_name_beginner (c) |
014fbcda | 14492 | || strchr ("([\"+-!~", c); |
9d299bea JB |
14493 | } |
14494 | ||
fc0763e6 | 14495 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 14496 | on error. */ |
252b5132 | 14497 | |
252b5132 | 14498 | static int |
a7619375 | 14499 | i386_att_operand (char *operand_string) |
252b5132 | 14500 | { |
af6bdddf AM |
14501 | const reg_entry *r; |
14502 | char *end_op; | |
24eab124 | 14503 | char *op_string = operand_string; |
252b5132 | 14504 | |
24eab124 | 14505 | if (is_space_char (*op_string)) |
252b5132 RH |
14506 | ++op_string; |
14507 | ||
24eab124 | 14508 | /* We check for an absolute prefix (differentiating, |
47926f60 | 14509 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
ccb05c9c | 14510 | if (*op_string == ABSOLUTE_PREFIX |
d3b01414 | 14511 | && current_templates.start->opcode_modifier.jump) |
24eab124 AM |
14512 | { |
14513 | ++op_string; | |
14514 | if (is_space_char (*op_string)) | |
14515 | ++op_string; | |
5b7c81bd | 14516 | i.jumpabsolute = true; |
24eab124 | 14517 | } |
252b5132 | 14518 | |
47926f60 | 14519 | /* Check if operand is a register. */ |
4d1bb795 | 14520 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 14521 | { |
40fb9820 L |
14522 | i386_operand_type temp; |
14523 | ||
8a6fb3f9 JB |
14524 | if (r == &bad_reg) |
14525 | return 0; | |
14526 | ||
24eab124 AM |
14527 | /* Check for a segment override by searching for ':' after a |
14528 | segment register. */ | |
14529 | op_string = end_op; | |
14530 | if (is_space_char (*op_string)) | |
14531 | ++op_string; | |
00cee14f | 14532 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 | 14533 | { |
5e042380 | 14534 | i.seg[i.mem_operands] = r; |
252b5132 | 14535 | |
24eab124 | 14536 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
14537 | ++op_string; |
14538 | if (is_space_char (*op_string)) | |
24eab124 | 14539 | ++op_string; |
252b5132 | 14540 | |
47926f60 | 14541 | /* Handle case of %es:*foo. */ |
ccb05c9c | 14542 | if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX |
d3b01414 | 14543 | && current_templates.start->opcode_modifier.jump) |
24eab124 AM |
14544 | { |
14545 | ++op_string; | |
14546 | if (is_space_char (*op_string)) | |
14547 | ++op_string; | |
5b7c81bd | 14548 | i.jumpabsolute = true; |
24eab124 | 14549 | } |
c8d541e2 | 14550 | |
9d299bea | 14551 | if (!starts_memory_operand (*op_string)) |
c8d541e2 JB |
14552 | { |
14553 | as_bad (_("bad memory operand `%s'"), op_string); | |
14554 | return 0; | |
14555 | } | |
24eab124 AM |
14556 | goto do_memory_reference; |
14557 | } | |
43234a1e L |
14558 | |
14559 | /* Handle vector operations. */ | |
14560 | if (*op_string == '{') | |
14561 | { | |
f70c6814 | 14562 | op_string = check_VecOperations (op_string); |
43234a1e L |
14563 | if (op_string == NULL) |
14564 | return 0; | |
14565 | } | |
14566 | ||
24eab124 AM |
14567 | if (*op_string) |
14568 | { | |
d0b47220 | 14569 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
14570 | return 0; |
14571 | } | |
0ff3b7d0 JB |
14572 | |
14573 | /* Reject pseudo registers for .insn. */ | |
14574 | if (dot_insn () && r->reg_type.bitfield.class == ClassNone) | |
14575 | { | |
14576 | as_bad (_("`%s%s' cannot be used here"), | |
14577 | register_prefix, r->reg_name); | |
14578 | return 0; | |
14579 | } | |
14580 | ||
40fb9820 L |
14581 | temp = r->reg_type; |
14582 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
14583 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
14584 | temp); | |
7d5e4556 | 14585 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 14586 | i.op[this_operand].regs = r; |
24eab124 | 14587 | i.reg_operands++; |
cf665fee JB |
14588 | |
14589 | /* A GPR may follow an RC or SAE immediate only if a (vector) register | |
14590 | operand was also present earlier on. */ | |
14591 | if (i.rounding.type != rc_none && temp.bitfield.class == Reg | |
14592 | && i.reg_operands == 1) | |
14593 | { | |
14594 | unsigned int j; | |
14595 | ||
14596 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j) | |
14597 | if (i.rounding.type == RC_NamesTable[j].type) | |
14598 | break; | |
14599 | as_bad (_("`%s': misplaced `{%s}'"), | |
d3b01414 | 14600 | insn_name (current_templates.start), RC_NamesTable[j].name); |
cf665fee JB |
14601 | return 0; |
14602 | } | |
24eab124 | 14603 | } |
af6bdddf AM |
14604 | else if (*op_string == REGISTER_PREFIX) |
14605 | { | |
14606 | as_bad (_("bad register name `%s'"), op_string); | |
14607 | return 0; | |
14608 | } | |
24eab124 | 14609 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 14610 | { |
24eab124 | 14611 | ++op_string; |
6f2f06be | 14612 | if (i.jumpabsolute) |
24eab124 | 14613 | { |
d0b47220 | 14614 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
14615 | return 0; |
14616 | } | |
14617 | if (!i386_immediate (op_string)) | |
14618 | return 0; | |
cf665fee JB |
14619 | if (i.rounding.type != rc_none) |
14620 | { | |
14621 | as_bad (_("`%s': RC/SAE operand must follow immediate operands"), | |
d3b01414 | 14622 | insn_name (current_templates.start)); |
cf665fee JB |
14623 | return 0; |
14624 | } | |
24eab124 | 14625 | } |
43234a1e L |
14626 | else if (RC_SAE_immediate (operand_string)) |
14627 | { | |
cf665fee JB |
14628 | /* If it is a RC or SAE immediate, do the necessary placement check: |
14629 | Only another immediate or a GPR may precede it. */ | |
14630 | if (i.mem_operands || i.reg_operands + i.imm_operands > 1 | |
14631 | || (i.reg_operands == 1 | |
14632 | && i.op[0].regs->reg_type.bitfield.class != Reg)) | |
14633 | { | |
14634 | as_bad (_("`%s': misplaced `%s'"), | |
d3b01414 | 14635 | insn_name (current_templates.start), operand_string); |
cf665fee JB |
14636 | return 0; |
14637 | } | |
43234a1e | 14638 | } |
9d299bea | 14639 | else if (starts_memory_operand (*op_string)) |
24eab124 | 14640 | { |
47926f60 | 14641 | /* This is a memory reference of some sort. */ |
af6bdddf | 14642 | char *base_string; |
252b5132 | 14643 | |
47926f60 | 14644 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
14645 | char *displacement_string_start; |
14646 | char *displacement_string_end; | |
252b5132 | 14647 | |
24eab124 | 14648 | do_memory_reference: |
24eab124 AM |
14649 | /* Check for base index form. We detect the base index form by |
14650 | looking for an ')' at the end of the operand, searching | |
14651 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
14652 | after the '('. */ | |
af6bdddf | 14653 | base_string = op_string + strlen (op_string); |
c3332e24 | 14654 | |
43234a1e | 14655 | /* Handle vector operations. */ |
6b5ba0d4 JB |
14656 | --base_string; |
14657 | if (is_space_char (*base_string)) | |
14658 | --base_string; | |
14659 | ||
14660 | if (*base_string == '}') | |
43234a1e | 14661 | { |
6b5ba0d4 JB |
14662 | char *vop_start = NULL; |
14663 | ||
14664 | while (base_string-- > op_string) | |
14665 | { | |
14666 | if (*base_string == '"') | |
14667 | break; | |
14668 | if (*base_string != '{') | |
14669 | continue; | |
14670 | ||
14671 | vop_start = base_string; | |
14672 | ||
14673 | --base_string; | |
14674 | if (is_space_char (*base_string)) | |
14675 | --base_string; | |
14676 | ||
14677 | if (*base_string != '}') | |
14678 | break; | |
14679 | ||
14680 | vop_start = NULL; | |
14681 | } | |
14682 | ||
14683 | if (!vop_start) | |
14684 | { | |
14685 | as_bad (_("unbalanced figure braces")); | |
14686 | return 0; | |
14687 | } | |
14688 | ||
f70c6814 | 14689 | if (check_VecOperations (vop_start) == NULL) |
43234a1e | 14690 | return 0; |
43234a1e L |
14691 | } |
14692 | ||
47926f60 | 14693 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
14694 | displacement_string_start = op_string; |
14695 | displacement_string_end = base_string + 1; | |
252b5132 | 14696 | |
24eab124 AM |
14697 | if (*base_string == ')') |
14698 | { | |
af6bdddf | 14699 | char *temp_string; |
e87fb6a6 JB |
14700 | unsigned int parens_not_balanced = 0; |
14701 | bool in_quotes = false; | |
e68c3d59 | 14702 | |
24eab124 | 14703 | /* We've already checked that the number of left & right ()'s are |
e87fb6a6 JB |
14704 | equal, and that there's a matching set of double quotes. */ |
14705 | end_op = base_string; | |
14706 | for (temp_string = op_string; temp_string < end_op; temp_string++) | |
24eab124 | 14707 | { |
e87fb6a6 JB |
14708 | if (*temp_string == '\\' && temp_string[1] == '"') |
14709 | ++temp_string; | |
14710 | else if (*temp_string == '"') | |
14711 | in_quotes = !in_quotes; | |
14712 | else if (!in_quotes) | |
14713 | { | |
14714 | if (*temp_string == '(' && !parens_not_balanced++) | |
14715 | base_string = temp_string; | |
14716 | if (*temp_string == ')') | |
14717 | --parens_not_balanced; | |
14718 | } | |
24eab124 | 14719 | } |
c3332e24 | 14720 | |
af6bdddf | 14721 | temp_string = base_string; |
c3332e24 | 14722 | |
24eab124 | 14723 | /* Skip past '(' and whitespace. */ |
4f081312 | 14724 | gas_assert (*base_string == '('); |
e87fb6a6 | 14725 | ++base_string; |
252b5132 | 14726 | if (is_space_char (*base_string)) |
24eab124 | 14727 | ++base_string; |
252b5132 | 14728 | |
af6bdddf | 14729 | if (*base_string == ',' |
4eed87de AM |
14730 | || ((i.base_reg = parse_register (base_string, &end_op)) |
14731 | != NULL)) | |
252b5132 | 14732 | { |
af6bdddf | 14733 | displacement_string_end = temp_string; |
252b5132 | 14734 | |
40fb9820 | 14735 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 14736 | |
af6bdddf | 14737 | if (i.base_reg) |
24eab124 | 14738 | { |
8a6fb3f9 JB |
14739 | if (i.base_reg == &bad_reg) |
14740 | return 0; | |
24eab124 AM |
14741 | base_string = end_op; |
14742 | if (is_space_char (*base_string)) | |
14743 | ++base_string; | |
af6bdddf AM |
14744 | } |
14745 | ||
14746 | /* There may be an index reg or scale factor here. */ | |
14747 | if (*base_string == ',') | |
14748 | { | |
14749 | ++base_string; | |
14750 | if (is_space_char (*base_string)) | |
14751 | ++base_string; | |
14752 | ||
4eed87de AM |
14753 | if ((i.index_reg = parse_register (base_string, &end_op)) |
14754 | != NULL) | |
24eab124 | 14755 | { |
8a6fb3f9 JB |
14756 | if (i.index_reg == &bad_reg) |
14757 | return 0; | |
af6bdddf | 14758 | base_string = end_op; |
24eab124 AM |
14759 | if (is_space_char (*base_string)) |
14760 | ++base_string; | |
af6bdddf AM |
14761 | if (*base_string == ',') |
14762 | { | |
14763 | ++base_string; | |
14764 | if (is_space_char (*base_string)) | |
14765 | ++base_string; | |
14766 | } | |
e5cb08ac | 14767 | else if (*base_string != ')') |
af6bdddf | 14768 | { |
4eed87de AM |
14769 | as_bad (_("expecting `,' or `)' " |
14770 | "after index register in `%s'"), | |
af6bdddf AM |
14771 | operand_string); |
14772 | return 0; | |
14773 | } | |
24eab124 | 14774 | } |
af6bdddf | 14775 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 14776 | { |
f76bf5e0 L |
14777 | end_op = strchr (base_string, ','); |
14778 | if (end_op) | |
14779 | *end_op = '\0'; | |
af6bdddf | 14780 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
14781 | return 0; |
14782 | } | |
252b5132 | 14783 | |
47926f60 | 14784 | /* Check for scale factor. */ |
551c1ca1 | 14785 | if (*base_string != ')') |
af6bdddf | 14786 | { |
551c1ca1 AM |
14787 | char *end_scale = i386_scale (base_string); |
14788 | ||
14789 | if (!end_scale) | |
af6bdddf | 14790 | return 0; |
24eab124 | 14791 | |
551c1ca1 | 14792 | base_string = end_scale; |
af6bdddf AM |
14793 | if (is_space_char (*base_string)) |
14794 | ++base_string; | |
14795 | if (*base_string != ')') | |
14796 | { | |
4eed87de AM |
14797 | as_bad (_("expecting `)' " |
14798 | "after scale factor in `%s'"), | |
af6bdddf AM |
14799 | operand_string); |
14800 | return 0; | |
14801 | } | |
14802 | } | |
14803 | else if (!i.index_reg) | |
24eab124 | 14804 | { |
4eed87de AM |
14805 | as_bad (_("expecting index register or scale factor " |
14806 | "after `,'; got '%c'"), | |
af6bdddf | 14807 | *base_string); |
24eab124 AM |
14808 | return 0; |
14809 | } | |
14810 | } | |
af6bdddf | 14811 | else if (*base_string != ')') |
24eab124 | 14812 | { |
4eed87de AM |
14813 | as_bad (_("expecting `,' or `)' " |
14814 | "after base register in `%s'"), | |
af6bdddf | 14815 | operand_string); |
24eab124 AM |
14816 | return 0; |
14817 | } | |
c3332e24 | 14818 | } |
af6bdddf | 14819 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 14820 | { |
f76bf5e0 L |
14821 | end_op = strchr (base_string, ','); |
14822 | if (end_op) | |
14823 | *end_op = '\0'; | |
af6bdddf | 14824 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 14825 | return 0; |
c3332e24 | 14826 | } |
24eab124 AM |
14827 | } |
14828 | ||
14829 | /* If there's an expression beginning the operand, parse it, | |
14830 | assuming displacement_string_start and | |
14831 | displacement_string_end are meaningful. */ | |
14832 | if (displacement_string_start != displacement_string_end) | |
14833 | { | |
14834 | if (!i386_displacement (displacement_string_start, | |
14835 | displacement_string_end)) | |
14836 | return 0; | |
14837 | } | |
14838 | ||
14839 | /* Special case for (%dx) while doing input/output op. */ | |
14840 | if (i.base_reg | |
75e5731b JB |
14841 | && i.base_reg->reg_type.bitfield.instance == RegD |
14842 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
14843 | && i.index_reg == 0 |
14844 | && i.log2_scale_factor == 0 | |
14845 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 14846 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 14847 | { |
2fb5be8d | 14848 | i.types[this_operand] = i.base_reg->reg_type; |
f0a4cb15 CL |
14849 | i.op[this_operand].regs = i.base_reg; |
14850 | i.base_reg = NULL; | |
9373f275 | 14851 | i.input_output_operand = true; |
24eab124 AM |
14852 | return 1; |
14853 | } | |
14854 | ||
eecb386c AM |
14855 | if (i386_index_check (operand_string) == 0) |
14856 | return 0; | |
c48dadc9 | 14857 | i.flags[this_operand] |= Operand_Mem; |
24eab124 AM |
14858 | i.mem_operands++; |
14859 | } | |
14860 | else | |
ce8a8b2f AM |
14861 | { |
14862 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
14863 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
14864 | output_invalid (*op_string), | |
14865 | this_operand + 1, | |
14866 | op_string); | |
14867 | return 0; | |
14868 | } | |
47926f60 | 14869 | return 1; /* Normal return. */ |
252b5132 RH |
14870 | } |
14871 | \f | |
fa94de6b RM |
14872 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
14873 | that an rs_machine_dependent frag may reach. */ | |
14874 | ||
14875 | unsigned int | |
14876 | i386_frag_max_var (fragS *frag) | |
14877 | { | |
14878 | /* The only relaxable frags are for jumps. | |
14879 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
14880 | gas_assert (frag->fr_type == rs_machine_dependent); | |
14881 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
14882 | } | |
14883 | ||
b084df0b L |
14884 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14885 | static int | |
8dcea932 | 14886 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
14887 | { |
14888 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
14889 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
14890 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
14891 | return 0; | |
14892 | ||
14893 | if (!S_IS_EXTERNAL (fr_symbol)) | |
14894 | /* Symbol may be weak or local. */ | |
14895 | return !S_IS_WEAK (fr_symbol); | |
14896 | ||
8dcea932 L |
14897 | /* Global symbols with non-default visibility can't be preempted. */ |
14898 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
14899 | return 1; | |
14900 | ||
14901 | if (fr_var != NO_RELOC) | |
14902 | switch ((enum bfd_reloc_code_real) fr_var) | |
14903 | { | |
14904 | case BFD_RELOC_386_PLT32: | |
14905 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 14906 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
14907 | return 0; |
14908 | default: | |
14909 | abort (); | |
14910 | } | |
14911 | ||
b084df0b L |
14912 | /* Global symbols with default visibility in a shared library may be |
14913 | preempted by another definition. */ | |
8dcea932 | 14914 | return !shared; |
b084df0b L |
14915 | } |
14916 | #endif | |
14917 | ||
79d72f45 HL |
14918 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
14919 | Note also work for Skylake and Cascadelake. | |
14920 | --------------------------------------------------------------------- | |
14921 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
14922 | | ------ | ----------- | ------- | -------- | | |
14923 | | Jo | N | N | Y | | |
14924 | | Jno | N | N | Y | | |
14925 | | Jc/Jb | Y | N | Y | | |
14926 | | Jae/Jnb | Y | N | Y | | |
14927 | | Je/Jz | Y | Y | Y | | |
14928 | | Jne/Jnz | Y | Y | Y | | |
14929 | | Jna/Jbe | Y | N | Y | | |
14930 | | Ja/Jnbe | Y | N | Y | | |
14931 | | Js | N | N | Y | | |
14932 | | Jns | N | N | Y | | |
14933 | | Jp/Jpe | N | N | Y | | |
14934 | | Jnp/Jpo | N | N | Y | | |
14935 | | Jl/Jnge | Y | Y | Y | | |
14936 | | Jge/Jnl | Y | Y | Y | | |
14937 | | Jle/Jng | Y | Y | Y | | |
14938 | | Jg/Jnle | Y | Y | Y | | |
14939 | --------------------------------------------------------------------- */ | |
14940 | static int | |
14941 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
14942 | { | |
14943 | if (mf_cmp == mf_cmp_alu_cmp) | |
14944 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
14945 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
14946 | if (mf_cmp == mf_cmp_incdec) | |
14947 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
14948 | || mf_jcc == mf_jcc_jle); | |
14949 | if (mf_cmp == mf_cmp_test_and) | |
14950 | return 1; | |
14951 | return 0; | |
14952 | } | |
14953 | ||
e379e5f3 L |
14954 | /* Return the next non-empty frag. */ |
14955 | ||
14956 | static fragS * | |
14957 | i386_next_non_empty_frag (fragS *fragP) | |
14958 | { | |
14959 | /* There may be a frag with a ".fill 0" when there is no room in | |
14960 | the current frag for frag_grow in output_insn. */ | |
14961 | for (fragP = fragP->fr_next; | |
14962 | (fragP != NULL | |
14963 | && fragP->fr_type == rs_fill | |
14964 | && fragP->fr_fix == 0); | |
14965 | fragP = fragP->fr_next) | |
14966 | ; | |
14967 | return fragP; | |
14968 | } | |
14969 | ||
14970 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
14971 | ||
14972 | static fragS * | |
79d72f45 | 14973 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 14974 | { |
79d72f45 HL |
14975 | fragS *branch_fragP; |
14976 | if (!pad_fragP) | |
e379e5f3 L |
14977 | return NULL; |
14978 | ||
79d72f45 HL |
14979 | if (pad_fragP->fr_type == rs_machine_dependent |
14980 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
14981 | == BRANCH_PADDING)) |
14982 | { | |
79d72f45 HL |
14983 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
14984 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 14985 | return NULL; |
79d72f45 HL |
14986 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
14987 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
14988 | pad_fragP->tc_frag_data.mf_type)) | |
14989 | return branch_fragP; | |
e379e5f3 L |
14990 | } |
14991 | ||
14992 | return NULL; | |
14993 | } | |
14994 | ||
14995 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
14996 | ||
14997 | static void | |
14998 | i386_classify_machine_dependent_frag (fragS *fragP) | |
14999 | { | |
15000 | fragS *cmp_fragP; | |
15001 | fragS *pad_fragP; | |
15002 | fragS *branch_fragP; | |
15003 | fragS *next_fragP; | |
15004 | unsigned int max_prefix_length; | |
15005 | ||
15006 | if (fragP->tc_frag_data.classified) | |
15007 | return; | |
15008 | ||
15009 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
15010 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
15011 | for (next_fragP = fragP; | |
15012 | next_fragP != NULL; | |
15013 | next_fragP = next_fragP->fr_next) | |
15014 | { | |
15015 | next_fragP->tc_frag_data.classified = 1; | |
15016 | if (next_fragP->fr_type == rs_machine_dependent) | |
15017 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
15018 | { | |
15019 | case BRANCH_PADDING: | |
15020 | /* The BRANCH_PADDING frag must be followed by a branch | |
15021 | frag. */ | |
15022 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
15023 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
15024 | break; | |
15025 | case FUSED_JCC_PADDING: | |
15026 | /* Check if this is a fused jcc: | |
15027 | FUSED_JCC_PADDING | |
15028 | CMP like instruction | |
15029 | BRANCH_PADDING | |
15030 | COND_JUMP | |
15031 | */ | |
15032 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
15033 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 15034 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
15035 | if (branch_fragP) |
15036 | { | |
15037 | /* The BRANCH_PADDING frag is merged with the | |
15038 | FUSED_JCC_PADDING frag. */ | |
15039 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
15040 | /* CMP like instruction size. */ | |
15041 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
15042 | frag_wane (pad_fragP); | |
15043 | /* Skip to branch_fragP. */ | |
15044 | next_fragP = branch_fragP; | |
15045 | } | |
15046 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
15047 | { | |
15048 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
15049 | a fused jcc. */ | |
15050 | next_fragP->fr_subtype | |
15051 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
15052 | next_fragP->tc_frag_data.max_bytes | |
15053 | = next_fragP->tc_frag_data.max_prefix_length; | |
15054 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
15055 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
15056 | } | |
15057 | else | |
15058 | frag_wane (next_fragP); | |
15059 | break; | |
15060 | } | |
15061 | } | |
15062 | ||
15063 | /* Stop if there is no BRANCH_PREFIX. */ | |
15064 | if (!align_branch_prefix_size) | |
15065 | return; | |
15066 | ||
15067 | /* Scan for BRANCH_PREFIX. */ | |
15068 | for (; fragP != NULL; fragP = fragP->fr_next) | |
15069 | { | |
15070 | if (fragP->fr_type != rs_machine_dependent | |
15071 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
15072 | != BRANCH_PREFIX)) | |
15073 | continue; | |
15074 | ||
15075 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
15076 | COND_JUMP_PREFIX. */ | |
15077 | max_prefix_length = 0; | |
15078 | for (next_fragP = fragP; | |
15079 | next_fragP != NULL; | |
15080 | next_fragP = next_fragP->fr_next) | |
15081 | { | |
15082 | if (next_fragP->fr_type == rs_fill) | |
15083 | /* Skip rs_fill frags. */ | |
15084 | continue; | |
15085 | else if (next_fragP->fr_type != rs_machine_dependent) | |
15086 | /* Stop for all other frags. */ | |
15087 | break; | |
15088 | ||
15089 | /* rs_machine_dependent frags. */ | |
15090 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15091 | == BRANCH_PREFIX) | |
15092 | { | |
15093 | /* Count BRANCH_PREFIX frags. */ | |
15094 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
15095 | { | |
15096 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
15097 | frag_wane (next_fragP); | |
15098 | } | |
15099 | else | |
15100 | max_prefix_length | |
15101 | += next_fragP->tc_frag_data.max_bytes; | |
15102 | } | |
15103 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15104 | == BRANCH_PADDING) | |
15105 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15106 | == FUSED_JCC_PADDING)) | |
15107 | { | |
15108 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
15109 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
15110 | break; | |
15111 | } | |
15112 | else | |
15113 | /* Stop for other rs_machine_dependent frags. */ | |
15114 | break; | |
15115 | } | |
15116 | ||
15117 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
15118 | ||
15119 | /* Skip to the next frag. */ | |
15120 | fragP = next_fragP; | |
15121 | } | |
15122 | } | |
15123 | ||
15124 | /* Compute padding size for | |
15125 | ||
15126 | FUSED_JCC_PADDING | |
15127 | CMP like instruction | |
15128 | BRANCH_PADDING | |
15129 | COND_JUMP/UNCOND_JUMP | |
15130 | ||
15131 | or | |
15132 | ||
15133 | BRANCH_PADDING | |
15134 | COND_JUMP/UNCOND_JUMP | |
15135 | */ | |
15136 | ||
15137 | static int | |
15138 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
15139 | { | |
15140 | unsigned int offset, size, padding_size; | |
15141 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
15142 | ||
15143 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
15144 | if (!address) | |
15145 | address = fragP->fr_address; | |
15146 | address += fragP->fr_fix; | |
15147 | ||
15148 | /* CMP like instrunction size. */ | |
15149 | size = fragP->tc_frag_data.cmp_size; | |
15150 | ||
15151 | /* The base size of the branch frag. */ | |
15152 | size += branch_fragP->fr_fix; | |
15153 | ||
15154 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
15155 | branch frag. */ | |
15156 | if (branch_fragP->fr_type == rs_machine_dependent) | |
15157 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
15158 | ||
15159 | /* Check if branch is within boundary and doesn't end at the last | |
15160 | byte. */ | |
15161 | offset = address & ((1U << align_branch_power) - 1); | |
15162 | if ((offset + size) >= (1U << align_branch_power)) | |
15163 | /* Padding needed to avoid crossing boundary. */ | |
15164 | padding_size = (1U << align_branch_power) - offset; | |
15165 | else | |
15166 | /* No padding needed. */ | |
15167 | padding_size = 0; | |
15168 | ||
15169 | /* The return value may be saved in tc_frag_data.length which is | |
15170 | unsigned byte. */ | |
15171 | if (!fits_in_unsigned_byte (padding_size)) | |
15172 | abort (); | |
15173 | ||
15174 | return padding_size; | |
15175 | } | |
15176 | ||
15177 | /* i386_generic_table_relax_frag() | |
15178 | ||
15179 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
15180 | grow/shrink padding to align branch frags. Hand others to | |
15181 | relax_frag(). */ | |
15182 | ||
15183 | long | |
15184 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
15185 | { | |
15186 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
15187 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
15188 | { | |
15189 | long padding_size = i386_branch_padding_size (fragP, 0); | |
15190 | long grow = padding_size - fragP->tc_frag_data.length; | |
15191 | ||
15192 | /* When the BRANCH_PREFIX frag is used, the computed address | |
15193 | must match the actual address and there should be no padding. */ | |
15194 | if (fragP->tc_frag_data.padding_address | |
15195 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
15196 | || padding_size)) | |
15197 | abort (); | |
15198 | ||
15199 | /* Update the padding size. */ | |
15200 | if (grow) | |
15201 | fragP->tc_frag_data.length = padding_size; | |
15202 | ||
15203 | return grow; | |
15204 | } | |
15205 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
15206 | { | |
15207 | fragS *padding_fragP, *next_fragP; | |
15208 | long padding_size, left_size, last_size; | |
15209 | ||
15210 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
15211 | if (!padding_fragP) | |
15212 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
15213 | return (fragP->tc_frag_data.length | |
15214 | - fragP->tc_frag_data.last_length); | |
15215 | ||
15216 | /* Compute the relative address of the padding frag in the very | |
15217 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
15218 | if (!fragP->tc_frag_data.padding_address) | |
15219 | fragP->tc_frag_data.padding_address | |
15220 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
15221 | ||
15222 | /* First update the last length from the previous interation. */ | |
15223 | left_size = fragP->tc_frag_data.prefix_length; | |
15224 | for (next_fragP = fragP; | |
15225 | next_fragP != padding_fragP; | |
15226 | next_fragP = next_fragP->fr_next) | |
15227 | if (next_fragP->fr_type == rs_machine_dependent | |
15228 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15229 | == BRANCH_PREFIX)) | |
15230 | { | |
15231 | if (left_size) | |
15232 | { | |
15233 | int max = next_fragP->tc_frag_data.max_bytes; | |
15234 | if (max) | |
15235 | { | |
15236 | int size; | |
15237 | if (max > left_size) | |
15238 | size = left_size; | |
15239 | else | |
15240 | size = max; | |
15241 | left_size -= size; | |
15242 | next_fragP->tc_frag_data.last_length = size; | |
15243 | } | |
15244 | } | |
15245 | else | |
15246 | next_fragP->tc_frag_data.last_length = 0; | |
15247 | } | |
15248 | ||
15249 | /* Check the padding size for the padding frag. */ | |
15250 | padding_size = i386_branch_padding_size | |
15251 | (padding_fragP, (fragP->fr_address | |
15252 | + fragP->tc_frag_data.padding_address)); | |
15253 | ||
15254 | last_size = fragP->tc_frag_data.prefix_length; | |
15255 | /* Check if there is change from the last interation. */ | |
15256 | if (padding_size == last_size) | |
15257 | { | |
15258 | /* Update the expected address of the padding frag. */ | |
15259 | padding_fragP->tc_frag_data.padding_address | |
15260 | = (fragP->fr_address + padding_size | |
15261 | + fragP->tc_frag_data.padding_address); | |
15262 | return 0; | |
15263 | } | |
15264 | ||
15265 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
15266 | { | |
15267 | /* No padding if there is no sufficient room. Clear the | |
15268 | expected address of the padding frag. */ | |
15269 | padding_fragP->tc_frag_data.padding_address = 0; | |
15270 | padding_size = 0; | |
15271 | } | |
15272 | else | |
15273 | /* Store the expected address of the padding frag. */ | |
15274 | padding_fragP->tc_frag_data.padding_address | |
15275 | = (fragP->fr_address + padding_size | |
15276 | + fragP->tc_frag_data.padding_address); | |
15277 | ||
15278 | fragP->tc_frag_data.prefix_length = padding_size; | |
15279 | ||
15280 | /* Update the length for the current interation. */ | |
15281 | left_size = padding_size; | |
15282 | for (next_fragP = fragP; | |
15283 | next_fragP != padding_fragP; | |
15284 | next_fragP = next_fragP->fr_next) | |
15285 | if (next_fragP->fr_type == rs_machine_dependent | |
15286 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
15287 | == BRANCH_PREFIX)) | |
15288 | { | |
15289 | if (left_size) | |
15290 | { | |
15291 | int max = next_fragP->tc_frag_data.max_bytes; | |
15292 | if (max) | |
15293 | { | |
15294 | int size; | |
15295 | if (max > left_size) | |
15296 | size = left_size; | |
15297 | else | |
15298 | size = max; | |
15299 | left_size -= size; | |
15300 | next_fragP->tc_frag_data.length = size; | |
15301 | } | |
15302 | } | |
15303 | else | |
15304 | next_fragP->tc_frag_data.length = 0; | |
15305 | } | |
15306 | ||
15307 | return (fragP->tc_frag_data.length | |
15308 | - fragP->tc_frag_data.last_length); | |
15309 | } | |
15310 | return relax_frag (segment, fragP, stretch); | |
15311 | } | |
15312 | ||
ee7fcc42 AM |
15313 | /* md_estimate_size_before_relax() |
15314 | ||
15315 | Called just before relax() for rs_machine_dependent frags. The x86 | |
15316 | assembler uses these frags to handle variable size jump | |
15317 | instructions. | |
15318 | ||
15319 | Any symbol that is now undefined will not become defined. | |
15320 | Return the correct fr_subtype in the frag. | |
15321 | Return the initial "guess for variable size of frag" to caller. | |
15322 | The guess is actually the growth beyond the fixed part. Whatever | |
15323 | we do to grow the fixed or variable part contributes to our | |
15324 | returned value. */ | |
15325 | ||
252b5132 | 15326 | int |
7016a5d5 | 15327 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 15328 | { |
e379e5f3 L |
15329 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
15330 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
15331 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
15332 | { | |
15333 | i386_classify_machine_dependent_frag (fragP); | |
15334 | return fragP->tc_frag_data.length; | |
15335 | } | |
15336 | ||
252b5132 | 15337 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
15338 | check for un-relaxable symbols. On an ELF system, we can't relax |
15339 | an externally visible symbol, because it may be overridden by a | |
15340 | shared library. */ | |
15341 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 15342 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 15343 | || (IS_ELF |
8dcea932 L |
15344 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
15345 | fragP->fr_var)) | |
fbeb56a4 DK |
15346 | #endif |
15347 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 15348 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 15349 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
15350 | #endif |
15351 | ) | |
252b5132 | 15352 | { |
b98ef147 AM |
15353 | /* Symbol is undefined in this segment, or we need to keep a |
15354 | reloc so that weak symbols can be overridden. */ | |
15355 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 15356 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
15357 | unsigned char *opcode; |
15358 | int old_fr_fix; | |
eb19308f | 15359 | fixS *fixP = NULL; |
f6af82bd | 15360 | |
ee7fcc42 | 15361 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 15362 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 15363 | else if (size == 2) |
f6af82bd | 15364 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b | 15365 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
ed719294 JB |
15366 | else if (fragP->tc_frag_data.code == CODE_64BIT |
15367 | && fragP->fr_offset == 0 | |
1ef3994a | 15368 | && need_plt32_p (fragP->fr_symbol)) |
bd7ab16b L |
15369 | reloc_type = BFD_RELOC_X86_64_PLT32; |
15370 | #endif | |
f6af82bd AM |
15371 | else |
15372 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 15373 | |
ee7fcc42 AM |
15374 | old_fr_fix = fragP->fr_fix; |
15375 | opcode = (unsigned char *) fragP->fr_opcode; | |
15376 | ||
fddf5b5b | 15377 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 15378 | { |
fddf5b5b AM |
15379 | case UNCOND_JUMP: |
15380 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 15381 | opcode[0] = 0xe9; |
252b5132 | 15382 | fragP->fr_fix += size; |
eb19308f JB |
15383 | fixP = fix_new (fragP, old_fr_fix, size, |
15384 | fragP->fr_symbol, | |
15385 | fragP->fr_offset, 1, | |
15386 | reloc_type); | |
252b5132 RH |
15387 | break; |
15388 | ||
fddf5b5b | 15389 | case COND_JUMP86: |
412167cb AM |
15390 | if (size == 2 |
15391 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
15392 | { |
15393 | /* Negate the condition, and branch past an | |
15394 | unconditional jump. */ | |
15395 | opcode[0] ^= 1; | |
15396 | opcode[1] = 3; | |
15397 | /* Insert an unconditional jump. */ | |
15398 | opcode[2] = 0xe9; | |
15399 | /* We added two extra opcode bytes, and have a two byte | |
15400 | offset. */ | |
15401 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
15402 | fix_new (fragP, old_fr_fix + 2, 2, |
15403 | fragP->fr_symbol, | |
15404 | fragP->fr_offset, 1, | |
15405 | reloc_type); | |
fddf5b5b AM |
15406 | break; |
15407 | } | |
15408 | /* Fall through. */ | |
15409 | ||
15410 | case COND_JUMP: | |
412167cb AM |
15411 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
15412 | { | |
15413 | fragP->fr_fix += 1; | |
3e02c1cc AM |
15414 | fixP = fix_new (fragP, old_fr_fix, 1, |
15415 | fragP->fr_symbol, | |
15416 | fragP->fr_offset, 1, | |
15417 | BFD_RELOC_8_PCREL); | |
15418 | fixP->fx_signed = 1; | |
412167cb AM |
15419 | break; |
15420 | } | |
93c2a809 | 15421 | |
24eab124 | 15422 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 15423 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 15424 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 15425 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
15426 | /* We've added an opcode byte. */ |
15427 | fragP->fr_fix += 1 + size; | |
eb19308f JB |
15428 | fixP = fix_new (fragP, old_fr_fix + 1, size, |
15429 | fragP->fr_symbol, | |
15430 | fragP->fr_offset, 1, | |
15431 | reloc_type); | |
252b5132 | 15432 | break; |
fddf5b5b AM |
15433 | |
15434 | default: | |
15435 | BAD_CASE (fragP->fr_subtype); | |
15436 | break; | |
252b5132 | 15437 | } |
eb19308f JB |
15438 | |
15439 | /* All jumps handled here are signed, but don't unconditionally use a | |
15440 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
15441 | around at 4G (outside of 64-bit mode) and 64k. */ | |
15442 | if (size == 4 && flag_code == CODE_64BIT) | |
15443 | fixP->fx_signed = 1; | |
15444 | ||
252b5132 | 15445 | frag_wane (fragP); |
ee7fcc42 | 15446 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 15447 | } |
93c2a809 | 15448 | |
93c2a809 AM |
15449 | /* Guess size depending on current relax state. Initially the relax |
15450 | state will correspond to a short jump and we return 1, because | |
15451 | the variable part of the frag (the branch offset) is one byte | |
15452 | long. However, we can relax a section more than once and in that | |
15453 | case we must either set fr_subtype back to the unrelaxed state, | |
15454 | or return the value for the appropriate branch. */ | |
15455 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
15456 | } |
15457 | ||
47926f60 KH |
15458 | /* Called after relax() is finished. |
15459 | ||
15460 | In: Address of frag. | |
15461 | fr_type == rs_machine_dependent. | |
15462 | fr_subtype is what the address relaxed to. | |
15463 | ||
15464 | Out: Any fixSs and constants are set up. | |
15465 | Caller will turn frag into a ".space 0". */ | |
15466 | ||
252b5132 | 15467 | void |
7016a5d5 TG |
15468 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
15469 | fragS *fragP) | |
252b5132 | 15470 | { |
29b0f896 | 15471 | unsigned char *opcode; |
252b5132 | 15472 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
15473 | offsetT target_address; |
15474 | offsetT opcode_address; | |
252b5132 | 15475 | unsigned int extension = 0; |
847f7ad4 | 15476 | offsetT displacement_from_opcode_start; |
252b5132 | 15477 | |
e379e5f3 L |
15478 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
15479 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
15480 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
15481 | { | |
15482 | /* Generate nop padding. */ | |
15483 | unsigned int size = fragP->tc_frag_data.length; | |
15484 | if (size) | |
15485 | { | |
15486 | if (size > fragP->tc_frag_data.max_bytes) | |
15487 | abort (); | |
15488 | ||
15489 | if (flag_debug) | |
15490 | { | |
15491 | const char *msg; | |
15492 | const char *branch = "branch"; | |
15493 | const char *prefix = ""; | |
15494 | fragS *padding_fragP; | |
15495 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
15496 | == BRANCH_PREFIX) | |
15497 | { | |
15498 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
15499 | switch (fragP->tc_frag_data.default_prefix) | |
15500 | { | |
15501 | default: | |
15502 | abort (); | |
15503 | break; | |
15504 | case CS_PREFIX_OPCODE: | |
15505 | prefix = " cs"; | |
15506 | break; | |
15507 | case DS_PREFIX_OPCODE: | |
15508 | prefix = " ds"; | |
15509 | break; | |
15510 | case ES_PREFIX_OPCODE: | |
15511 | prefix = " es"; | |
15512 | break; | |
15513 | case FS_PREFIX_OPCODE: | |
15514 | prefix = " fs"; | |
15515 | break; | |
15516 | case GS_PREFIX_OPCODE: | |
15517 | prefix = " gs"; | |
15518 | break; | |
15519 | case SS_PREFIX_OPCODE: | |
15520 | prefix = " ss"; | |
15521 | break; | |
15522 | } | |
15523 | if (padding_fragP) | |
15524 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
15525 | "%s within %d-byte boundary\n"); | |
15526 | else | |
15527 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
15528 | "align %s within %d-byte boundary\n"); | |
15529 | } | |
15530 | else | |
15531 | { | |
15532 | padding_fragP = fragP; | |
15533 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
15534 | "%s within %d-byte boundary\n"); | |
15535 | } | |
15536 | ||
15537 | if (padding_fragP) | |
15538 | switch (padding_fragP->tc_frag_data.branch_type) | |
15539 | { | |
15540 | case align_branch_jcc: | |
15541 | branch = "jcc"; | |
15542 | break; | |
15543 | case align_branch_fused: | |
15544 | branch = "fused jcc"; | |
15545 | break; | |
15546 | case align_branch_jmp: | |
15547 | branch = "jmp"; | |
15548 | break; | |
15549 | case align_branch_call: | |
15550 | branch = "call"; | |
15551 | break; | |
15552 | case align_branch_indirect: | |
15553 | branch = "indiret branch"; | |
15554 | break; | |
15555 | case align_branch_ret: | |
15556 | branch = "ret"; | |
15557 | break; | |
15558 | default: | |
15559 | break; | |
15560 | } | |
15561 | ||
15562 | fprintf (stdout, msg, | |
15563 | fragP->fr_file, fragP->fr_line, size, prefix, | |
15564 | (long long) fragP->fr_address, branch, | |
15565 | 1 << align_branch_power); | |
15566 | } | |
15567 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
15568 | memset (fragP->fr_opcode, | |
15569 | fragP->tc_frag_data.default_prefix, size); | |
15570 | else | |
15571 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
15572 | size, 0); | |
15573 | fragP->fr_fix += size; | |
15574 | } | |
15575 | return; | |
15576 | } | |
15577 | ||
252b5132 RH |
15578 | opcode = (unsigned char *) fragP->fr_opcode; |
15579 | ||
47926f60 | 15580 | /* Address we want to reach in file space. */ |
252b5132 | 15581 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 15582 | |
47926f60 | 15583 | /* Address opcode resides at in file space. */ |
252b5132 RH |
15584 | opcode_address = fragP->fr_address + fragP->fr_fix; |
15585 | ||
47926f60 | 15586 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
15587 | displacement_from_opcode_start = target_address - opcode_address; |
15588 | ||
fddf5b5b | 15589 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 15590 | { |
47926f60 KH |
15591 | /* Don't have to change opcode. */ |
15592 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 15593 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
15594 | } |
15595 | else | |
15596 | { | |
15597 | if (no_cond_jump_promotion | |
15598 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
15599 | as_warn_where (fragP->fr_file, fragP->fr_line, |
15600 | _("long jump required")); | |
252b5132 | 15601 | |
fddf5b5b AM |
15602 | switch (fragP->fr_subtype) |
15603 | { | |
15604 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
15605 | extension = 4; /* 1 opcode + 4 displacement */ | |
15606 | opcode[0] = 0xe9; | |
15607 | where_to_put_displacement = &opcode[1]; | |
15608 | break; | |
252b5132 | 15609 | |
fddf5b5b AM |
15610 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
15611 | extension = 2; /* 1 opcode + 2 displacement */ | |
15612 | opcode[0] = 0xe9; | |
15613 | where_to_put_displacement = &opcode[1]; | |
15614 | break; | |
252b5132 | 15615 | |
fddf5b5b AM |
15616 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
15617 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
15618 | extension = 5; /* 2 opcode + 4 displacement */ | |
15619 | opcode[1] = opcode[0] + 0x10; | |
15620 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
15621 | where_to_put_displacement = &opcode[2]; | |
15622 | break; | |
252b5132 | 15623 | |
fddf5b5b AM |
15624 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
15625 | extension = 3; /* 2 opcode + 2 displacement */ | |
15626 | opcode[1] = opcode[0] + 0x10; | |
15627 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
15628 | where_to_put_displacement = &opcode[2]; | |
15629 | break; | |
252b5132 | 15630 | |
fddf5b5b AM |
15631 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
15632 | extension = 4; | |
15633 | opcode[0] ^= 1; | |
15634 | opcode[1] = 3; | |
15635 | opcode[2] = 0xe9; | |
15636 | where_to_put_displacement = &opcode[3]; | |
15637 | break; | |
15638 | ||
15639 | default: | |
15640 | BAD_CASE (fragP->fr_subtype); | |
15641 | break; | |
15642 | } | |
252b5132 | 15643 | } |
fddf5b5b | 15644 | |
7b81dfbb AJ |
15645 | /* If size if less then four we are sure that the operand fits, |
15646 | but if it's 4, then it could be that the displacement is larger | |
15647 | then -/+ 2GB. */ | |
15648 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
15649 | && object_64bit | |
15650 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
15651 | + ((addressT) 1 << 31)) |
15652 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
15653 | { |
15654 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
15655 | _("jump target out of range")); | |
15656 | /* Make us emit 0. */ | |
15657 | displacement_from_opcode_start = extension; | |
15658 | } | |
47926f60 | 15659 | /* Now put displacement after opcode. */ |
252b5132 RH |
15660 | md_number_to_chars ((char *) where_to_put_displacement, |
15661 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 15662 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
15663 | fragP->fr_fix += extension; |
15664 | } | |
15665 | \f | |
7016a5d5 | 15666 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
15667 | by our caller that we have all the info we need to fix it up. |
15668 | ||
7016a5d5 TG |
15669 | Parameter valP is the pointer to the value of the bits. |
15670 | ||
252b5132 RH |
15671 | On the 386, immediates, displacements, and data pointers are all in |
15672 | the same (little-endian) format, so we don't need to care about which | |
15673 | we are handling. */ | |
15674 | ||
94f592af | 15675 | void |
7016a5d5 | 15676 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15677 | { |
94f592af | 15678 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 15679 | valueT value = *valP; |
252b5132 | 15680 | |
f86103b7 | 15681 | #if !defined (TE_Mach) |
93382f6d AM |
15682 | if (fixP->fx_pcrel) |
15683 | { | |
15684 | switch (fixP->fx_r_type) | |
15685 | { | |
5865bb77 ILT |
15686 | default: |
15687 | break; | |
15688 | ||
d6ab8113 JB |
15689 | case BFD_RELOC_64: |
15690 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
15691 | break; | |
93382f6d | 15692 | case BFD_RELOC_32: |
ae8887b5 | 15693 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
15694 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
15695 | break; | |
15696 | case BFD_RELOC_16: | |
15697 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
15698 | break; | |
15699 | case BFD_RELOC_8: | |
15700 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
15701 | break; | |
15702 | } | |
15703 | } | |
252b5132 | 15704 | |
a161fe53 | 15705 | if (fixP->fx_addsy != NULL |
31312f95 | 15706 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 15707 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 15708 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 15709 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 15710 | && !use_rela_relocations) |
252b5132 | 15711 | { |
31312f95 AM |
15712 | /* This is a hack. There should be a better way to handle this. |
15713 | This covers for the fact that bfd_install_relocation will | |
15714 | subtract the current location (for partial_inplace, PC relative | |
15715 | relocations); see more below. */ | |
252b5132 | 15716 | #ifndef OBJ_AOUT |
718ddfc0 | 15717 | if (IS_ELF |
252b5132 RH |
15718 | #ifdef TE_PE |
15719 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
15720 | #endif | |
15721 | ) | |
15722 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
15723 | #endif | |
15724 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 15725 | if (IS_ELF) |
252b5132 | 15726 | { |
6539b54b | 15727 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 15728 | |
6539b54b | 15729 | if ((sym_seg == seg |
2f66722d | 15730 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 15731 | && sym_seg != absolute_section)) |
af65af87 | 15732 | && !generic_force_reloc (fixP)) |
2f66722d AM |
15733 | { |
15734 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
15735 | bfd_install_relocation subtracts them out again. I think |
15736 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
15737 | it. FIXME. */ |
15738 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
15739 | } | |
252b5132 RH |
15740 | } |
15741 | #endif | |
15742 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
15743 | /* For some reason, the PE format does not store a |
15744 | section address offset for a PC relative symbol. */ | |
15745 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 15746 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
15747 | value += md_pcrel_from (fixP); |
15748 | #endif | |
15749 | } | |
fbeb56a4 | 15750 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
15751 | if (fixP->fx_addsy != NULL |
15752 | && S_IS_WEAK (fixP->fx_addsy) | |
15753 | /* PR 16858: Do not modify weak function references. */ | |
15754 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 15755 | { |
296a8689 NC |
15756 | #if !defined (TE_PEP) |
15757 | /* For x86 PE weak function symbols are neither PC-relative | |
15758 | nor do they set S_IS_FUNCTION. So the only reliable way | |
15759 | to detect them is to check the flags of their containing | |
15760 | section. */ | |
15761 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
15762 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
15763 | ; | |
15764 | else | |
15765 | #endif | |
fbeb56a4 DK |
15766 | value -= S_GET_VALUE (fixP->fx_addsy); |
15767 | } | |
15768 | #endif | |
252b5132 RH |
15769 | |
15770 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 15771 | and we must not disappoint it. */ |
252b5132 | 15772 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 15773 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
15774 | switch (fixP->fx_r_type) |
15775 | { | |
15776 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 15777 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
15778 | /* Make the jump instruction point to the address of the operand. |
15779 | At runtime we merely add the offset to the actual PLT entry. | |
15780 | NB: Subtract the offset size only for jump instructions. */ | |
15781 | if (fixP->fx_pcrel) | |
15782 | value = -4; | |
47926f60 | 15783 | break; |
31312f95 | 15784 | |
13ae64f3 JJ |
15785 | case BFD_RELOC_386_TLS_GD: |
15786 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 15787 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
15788 | case BFD_RELOC_386_TLS_IE: |
15789 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 15790 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
15791 | case BFD_RELOC_X86_64_TLSGD: |
15792 | case BFD_RELOC_X86_64_TLSLD: | |
15793 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 15794 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
5bc71c2a | 15795 | case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: |
67a4f2b7 | 15796 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 15797 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
00f7efb6 JJ |
15798 | value = 0; /* Fully resolved at runtime. No addend. */ |
15799 | /* Fallthrough */ | |
15800 | case BFD_RELOC_386_TLS_LE: | |
15801 | case BFD_RELOC_386_TLS_LDO_32: | |
15802 | case BFD_RELOC_386_TLS_LE_32: | |
15803 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 15804 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 15805 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 15806 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
15807 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15808 | break; | |
15809 | ||
67a4f2b7 AO |
15810 | case BFD_RELOC_386_TLS_DESC_CALL: |
15811 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
15812 | value = 0; /* Fully resolved at runtime. No addend. */ | |
15813 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15814 | fixP->fx_done = 0; | |
15815 | return; | |
15816 | ||
47926f60 KH |
15817 | case BFD_RELOC_VTABLE_INHERIT: |
15818 | case BFD_RELOC_VTABLE_ENTRY: | |
15819 | fixP->fx_done = 0; | |
94f592af | 15820 | return; |
47926f60 KH |
15821 | |
15822 | default: | |
15823 | break; | |
15824 | } | |
15825 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
a442cac5 JB |
15826 | |
15827 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ | |
15828 | if (!object_64bit) | |
15829 | value = extend_to_32bit_address (value); | |
15830 | ||
c6682705 | 15831 | *valP = value; |
f86103b7 | 15832 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 15833 | |
3e73aa7c | 15834 | /* Are we finished with this relocation now? */ |
c6682705 | 15835 | if (fixP->fx_addsy == NULL) |
b8188555 JB |
15836 | { |
15837 | fixP->fx_done = 1; | |
15838 | switch (fixP->fx_r_type) | |
15839 | { | |
15840 | case BFD_RELOC_X86_64_32S: | |
15841 | fixP->fx_signed = 1; | |
15842 | break; | |
15843 | ||
15844 | default: | |
15845 | break; | |
15846 | } | |
15847 | } | |
fbeb56a4 DK |
15848 | #if defined (OBJ_COFF) && defined (TE_PE) |
15849 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
15850 | { | |
15851 | fixP->fx_done = 0; | |
15852 | /* Remember value for tc_gen_reloc. */ | |
15853 | fixP->fx_addnumber = value; | |
15854 | /* Clear out the frag for now. */ | |
15855 | value = 0; | |
15856 | } | |
15857 | #endif | |
3e73aa7c JH |
15858 | else if (use_rela_relocations) |
15859 | { | |
46fb6d5a JB |
15860 | if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC) |
15861 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
15862 | /* Remember value for tc_gen_reloc. */ |
15863 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
15864 | value = 0; |
15865 | } | |
f86103b7 | 15866 | |
94f592af | 15867 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 15868 | } |
252b5132 | 15869 | \f |
6d4af3c2 | 15870 | const char * |
499ac353 | 15871 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 15872 | { |
499ac353 NC |
15873 | /* This outputs the LITTLENUMs in REVERSE order; |
15874 | in accord with the bigendian 386. */ | |
5b7c81bd | 15875 | return ieee_md_atof (type, litP, sizeP, false); |
252b5132 RH |
15876 | } |
15877 | \f | |
2d545b82 | 15878 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 15879 | |
252b5132 | 15880 | static char * |
e3bb37b5 | 15881 | output_invalid (int c) |
252b5132 | 15882 | { |
3882b010 | 15883 | if (ISPRINT (c)) |
f9f21a03 L |
15884 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
15885 | "'%c'", c); | |
252b5132 | 15886 | else |
f9f21a03 | 15887 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 15888 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
15889 | return output_invalid_buf; |
15890 | } | |
15891 | ||
8a6fb3f9 JB |
15892 | /* Verify that @r can be used in the current context. */ |
15893 | ||
5b7c81bd | 15894 | static bool check_register (const reg_entry *r) |
8a6fb3f9 JB |
15895 | { |
15896 | if (allow_pseudo_reg) | |
5b7c81bd | 15897 | return true; |
8a6fb3f9 JB |
15898 | |
15899 | if (operand_type_all_zero (&r->reg_type)) | |
5b7c81bd | 15900 | return false; |
8a6fb3f9 JB |
15901 | |
15902 | if ((r->reg_type.bitfield.dword | |
15903 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
15904 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 15905 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 | 15906 | && !cpu_arch_flags.bitfield.cpui386) |
5b7c81bd | 15907 | return false; |
8a6fb3f9 | 15908 | |
22e00a3f JB |
15909 | if (r->reg_type.bitfield.class == RegTR |
15910 | && (flag_code == CODE_64BIT | |
15911 | || !cpu_arch_flags.bitfield.cpui386 | |
15912 | || cpu_arch_isa_flags.bitfield.cpui586 | |
15913 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
5b7c81bd | 15914 | return false; |
22e00a3f | 15915 | |
8a6fb3f9 | 15916 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
5b7c81bd | 15917 | return false; |
8a6fb3f9 JB |
15918 | |
15919 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
15920 | { | |
15921 | if (r->reg_type.bitfield.zmmword | |
15922 | || r->reg_type.bitfield.class == RegMask) | |
5b7c81bd | 15923 | return false; |
8a6fb3f9 JB |
15924 | |
15925 | if (!cpu_arch_flags.bitfield.cpuavx) | |
15926 | { | |
15927 | if (r->reg_type.bitfield.ymmword) | |
5b7c81bd | 15928 | return false; |
8a6fb3f9 JB |
15929 | |
15930 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
5b7c81bd | 15931 | return false; |
8a6fb3f9 JB |
15932 | } |
15933 | } | |
15934 | ||
a6f3add0 JB |
15935 | if (r->reg_type.bitfield.zmmword) |
15936 | { | |
15937 | if (vector_size < VSZ512) | |
15938 | return false; | |
15939 | ||
eb3f3841 JB |
15940 | switch (i.encoding) |
15941 | { | |
15942 | case encoding_default: | |
15943 | case encoding_egpr: | |
15944 | i.encoding = encoding_evex512; | |
15945 | break; | |
15946 | case encoding_evex: | |
15947 | case encoding_evex512: | |
15948 | break; | |
15949 | default: | |
15950 | i.encoding = encoding_error; | |
15951 | break; | |
15952 | } | |
a6f3add0 | 15953 | } |
4fc85f37 JB |
15954 | |
15955 | if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword) | |
15956 | return false; | |
15957 | ||
260cd341 LC |
15958 | if (r->reg_type.bitfield.tmmword |
15959 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
15960 | || flag_code != CODE_64BIT)) | |
5b7c81bd | 15961 | return false; |
260cd341 | 15962 | |
8a6fb3f9 | 15963 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
5b7c81bd | 15964 | return false; |
8a6fb3f9 JB |
15965 | |
15966 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
15967 | if (!allow_index_reg && r->reg_num == RegIZ) | |
5b7c81bd | 15968 | return false; |
8a6fb3f9 JB |
15969 | |
15970 | /* Upper 16 vector registers are only available with VREX in 64bit | |
15971 | mode, and require EVEX encoding. */ | |
15972 | if (r->reg_flags & RegVRex) | |
15973 | { | |
15974 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
15975 | || flag_code != CODE_64BIT) | |
5b7c81bd | 15976 | return false; |
8a6fb3f9 | 15977 | |
eb3f3841 JB |
15978 | switch (i.encoding) |
15979 | { | |
15980 | case encoding_default: | |
15981 | case encoding_egpr: | |
15982 | case encoding_evex512: | |
15983 | i.encoding = encoding_evex; | |
15984 | break; | |
15985 | case encoding_evex: | |
15986 | break; | |
15987 | default: | |
15988 | i.encoding = encoding_error; | |
15989 | break; | |
15990 | } | |
8a6fb3f9 JB |
15991 | } |
15992 | ||
80d61d8d CL |
15993 | if (r->reg_flags & RegRex2) |
15994 | { | |
15995 | if (!cpu_arch_flags.bitfield.cpuapx_f | |
15996 | || flag_code != CODE_64BIT) | |
15997 | return false; | |
6177c84d | 15998 | |
eb3f3841 JB |
15999 | switch (i.encoding) |
16000 | { | |
16001 | case encoding_default: | |
16002 | i.encoding = encoding_egpr; | |
16003 | break; | |
16004 | case encoding_egpr: | |
16005 | case encoding_evex: | |
16006 | case encoding_evex512: | |
16007 | break; | |
16008 | default: | |
16009 | i.encoding = encoding_error; | |
16010 | break; | |
16011 | } | |
80d61d8d CL |
16012 | } |
16013 | ||
8a6fb3f9 | 16014 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
da5f9eb4 | 16015 | && (!cpu_arch_flags.bitfield.cpu64 |
0ff3b7d0 JB |
16016 | || r->reg_type.bitfield.class != RegCR |
16017 | || dot_insn ()) | |
8a6fb3f9 | 16018 | && flag_code != CODE_64BIT) |
5b7c81bd | 16019 | return false; |
8a6fb3f9 JB |
16020 | |
16021 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
16022 | && !intel_syntax) | |
5b7c81bd | 16023 | return false; |
8a6fb3f9 | 16024 | |
5b7c81bd | 16025 | return true; |
8a6fb3f9 JB |
16026 | } |
16027 | ||
af6bdddf | 16028 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
16029 | |
16030 | static const reg_entry * | |
74e05e01 | 16031 | parse_real_register (const char *reg_string, char **end_op) |
252b5132 | 16032 | { |
74e05e01 | 16033 | const char *s = reg_string; |
af6bdddf | 16034 | char *p; |
252b5132 RH |
16035 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
16036 | const reg_entry *r; | |
16037 | ||
16038 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
16039 | if (*s == REGISTER_PREFIX) | |
16040 | ++s; | |
16041 | ||
16042 | if (is_space_char (*s)) | |
16043 | ++s; | |
16044 | ||
16045 | p = reg_name_given; | |
af6bdddf | 16046 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
16047 | { |
16048 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
16049 | return (const reg_entry *) NULL; |
16050 | s++; | |
252b5132 RH |
16051 | } |
16052 | ||
4795cd4a | 16053 | if (is_part_of_name (*s)) |
6588847e DN |
16054 | return (const reg_entry *) NULL; |
16055 | ||
74e05e01 | 16056 | *end_op = (char *) s; |
252b5132 | 16057 | |
629310ab | 16058 | r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given); |
252b5132 | 16059 | |
5f47d35b | 16060 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
6288d05f | 16061 | if (r == reg_st0) |
5f47d35b | 16062 | { |
0e0eea78 JB |
16063 | if (!cpu_arch_flags.bitfield.cpu8087 |
16064 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
16065 | && !cpu_arch_flags.bitfield.cpu387 |
16066 | && !allow_pseudo_reg) | |
0e0eea78 JB |
16067 | return (const reg_entry *) NULL; |
16068 | ||
5f47d35b AM |
16069 | if (is_space_char (*s)) |
16070 | ++s; | |
16071 | if (*s == '(') | |
16072 | { | |
af6bdddf | 16073 | ++s; |
5f47d35b AM |
16074 | if (is_space_char (*s)) |
16075 | ++s; | |
16076 | if (*s >= '0' && *s <= '7') | |
16077 | { | |
db557034 | 16078 | int fpr = *s - '0'; |
af6bdddf | 16079 | ++s; |
5f47d35b AM |
16080 | if (is_space_char (*s)) |
16081 | ++s; | |
16082 | if (*s == ')') | |
16083 | { | |
74e05e01 | 16084 | *end_op = (char *) s + 1; |
6288d05f | 16085 | know (r[fpr].reg_num == fpr); |
db557034 | 16086 | return r + fpr; |
5f47d35b | 16087 | } |
5f47d35b | 16088 | } |
47926f60 | 16089 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
16090 | return (const reg_entry *) NULL; |
16091 | } | |
16092 | } | |
16093 | ||
8a6fb3f9 | 16094 | return r && check_register (r) ? r : NULL; |
252b5132 | 16095 | } |
4d1bb795 JB |
16096 | |
16097 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
16098 | ||
16099 | static const reg_entry * | |
4f081312 | 16100 | parse_register (const char *reg_string, char **end_op) |
4d1bb795 JB |
16101 | { |
16102 | const reg_entry *r; | |
16103 | ||
16104 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
16105 | r = parse_real_register (reg_string, end_op); | |
16106 | else | |
16107 | r = NULL; | |
16108 | if (!r) | |
16109 | { | |
16110 | char *save = input_line_pointer; | |
4f081312 | 16111 | char *buf = xstrdup (reg_string), *name; |
4d1bb795 JB |
16112 | symbolS *symbolP; |
16113 | ||
4f081312 JB |
16114 | input_line_pointer = buf; |
16115 | get_symbol_name (&name); | |
16116 | symbolP = symbol_find (name); | |
d50c498a | 16117 | while (symbolP && symbol_equated_p (symbolP)) |
64d23078 JB |
16118 | { |
16119 | const expressionS *e = symbol_get_value_expression(symbolP); | |
16120 | ||
d50c498a | 16121 | if (e->X_add_number) |
64d23078 JB |
16122 | break; |
16123 | symbolP = e->X_add_symbol; | |
16124 | } | |
4d1bb795 JB |
16125 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
16126 | { | |
16127 | const expressionS *e = symbol_get_value_expression (symbolP); | |
16128 | ||
0ccade1a JB |
16129 | if (e->X_op == O_register) |
16130 | { | |
16131 | know (e->X_add_number >= 0 | |
16132 | && (valueT) e->X_add_number < i386_regtab_size); | |
16133 | r = i386_regtab + e->X_add_number; | |
4f081312 | 16134 | *end_op = (char *) reg_string + (input_line_pointer - buf); |
0ccade1a JB |
16135 | } |
16136 | if (r && !check_register (r)) | |
8a6fb3f9 | 16137 | { |
3b55a1d0 JB |
16138 | as_bad (_("register '%s%s' cannot be used here"), |
16139 | register_prefix, r->reg_name); | |
16140 | r = &bad_reg; | |
8a6fb3f9 | 16141 | } |
4d1bb795 | 16142 | } |
4d1bb795 | 16143 | input_line_pointer = save; |
4f081312 | 16144 | free (buf); |
4d1bb795 JB |
16145 | } |
16146 | return r; | |
16147 | } | |
16148 | ||
16149 | int | |
16150 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
16151 | { | |
4faaa10f | 16152 | const reg_entry *r = NULL; |
4d1bb795 JB |
16153 | char *end = input_line_pointer; |
16154 | ||
6acf9130 JB |
16155 | /* We only know the terminating character here. It being double quote could |
16156 | be the closing one of a quoted symbol name, or an opening one from a | |
16157 | following string (or another quoted symbol name). Since the latter can't | |
16158 | be valid syntax for anything, bailing in either case is good enough. */ | |
16159 | if (*nextcharP == '"') | |
16160 | return 0; | |
16161 | ||
4d1bb795 | 16162 | *end = *nextcharP; |
4faaa10f JB |
16163 | if (*name == REGISTER_PREFIX || allow_naked_reg) |
16164 | r = parse_real_register (name, &input_line_pointer); | |
4d1bb795 JB |
16165 | if (r && end <= input_line_pointer) |
16166 | { | |
16167 | *nextcharP = *input_line_pointer; | |
16168 | *input_line_pointer = 0; | |
f847749a JB |
16169 | e->X_op = O_register; |
16170 | e->X_add_number = r - i386_regtab; | |
4d1bb795 JB |
16171 | return 1; |
16172 | } | |
16173 | input_line_pointer = end; | |
16174 | *end = 0; | |
ee86248c | 16175 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
16176 | } |
16177 | ||
16178 | void | |
16179 | md_operand (expressionS *e) | |
16180 | { | |
ee86248c JB |
16181 | char *end; |
16182 | const reg_entry *r; | |
4d1bb795 | 16183 | |
ee86248c JB |
16184 | switch (*input_line_pointer) |
16185 | { | |
16186 | case REGISTER_PREFIX: | |
16187 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
16188 | if (r) |
16189 | { | |
16190 | e->X_op = O_register; | |
16191 | e->X_add_number = r - i386_regtab; | |
16192 | input_line_pointer = end; | |
16193 | } | |
ee86248c JB |
16194 | break; |
16195 | ||
16196 | case '[': | |
9c2799c2 | 16197 | gas_assert (intel_syntax); |
ee86248c JB |
16198 | end = input_line_pointer++; |
16199 | expression (e); | |
16200 | if (*input_line_pointer == ']') | |
16201 | { | |
16202 | ++input_line_pointer; | |
16203 | e->X_op_symbol = make_expr_symbol (e); | |
16204 | e->X_add_symbol = NULL; | |
16205 | e->X_add_number = 0; | |
16206 | e->X_op = O_index; | |
16207 | } | |
16208 | else | |
16209 | { | |
16210 | e->X_op = O_absent; | |
16211 | input_line_pointer = end; | |
16212 | } | |
16213 | break; | |
4d1bb795 JB |
16214 | } |
16215 | } | |
16216 | ||
5cc00775 JB |
16217 | #ifdef BFD64 |
16218 | /* To maintain consistency with !BFD64 builds of gas record, whether any | |
16219 | (binary) operator was involved in an expression. As expressions are | |
16220 | evaluated in only 32 bits when !BFD64, we use this to decide whether to | |
16221 | truncate results. */ | |
16222 | bool i386_record_operator (operatorT op, | |
16223 | const expressionS *left, | |
16224 | const expressionS *right) | |
16225 | { | |
16226 | if (op == O_absent) | |
16227 | return false; | |
16228 | ||
16229 | if (!left) | |
16230 | { | |
16231 | /* Since the expression parser applies unary operators fine to bignum | |
16232 | operands, we don't need to be concerned of respective operands not | |
16233 | fitting in 32 bits. */ | |
16234 | if (right->X_op == O_constant && right->X_unsigned | |
16235 | && !fits_in_unsigned_long (right->X_add_number)) | |
16236 | return false; | |
16237 | } | |
16238 | /* This isn't entirely right: The pattern can also result when constant | |
16239 | expressions are folded (e.g. 0xffffffff + 1). */ | |
16240 | else if ((left->X_op == O_constant && left->X_unsigned | |
16241 | && !fits_in_unsigned_long (left->X_add_number)) | |
16242 | || (right->X_op == O_constant && right->X_unsigned | |
16243 | && !fits_in_unsigned_long (right->X_add_number))) | |
16244 | expr_mode = expr_large_value; | |
16245 | ||
16246 | if (expr_mode != expr_large_value) | |
16247 | expr_mode = expr_operator_present; | |
16248 | ||
16249 | return false; | |
16250 | } | |
16251 | #endif | |
252b5132 | 16252 | \f |
4cc782b5 | 16253 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 16254 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 16255 | #else |
b6f8c7c4 | 16256 | const char *md_shortopts = "qnO::"; |
252b5132 | 16257 | #endif |
6e0b89ee | 16258 | |
3e73aa7c | 16259 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
16260 | #define OPTION_64 (OPTION_MD_BASE + 1) |
16261 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
16262 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
16263 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
16264 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
16265 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
16266 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
16267 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 16268 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 16269 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 16270 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
16271 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
16272 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
16273 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 16274 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
16275 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
16276 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 16277 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 16278 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 16279 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 16280 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
16281 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
16282 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 16283 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 16284 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 16285 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
16286 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
16287 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
16288 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 16289 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
16290 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
16291 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
16292 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
c8480b58 | 16293 | #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34) |
b3b91714 | 16294 | |
99ad8390 NC |
16295 | struct option md_longopts[] = |
16296 | { | |
3e73aa7c | 16297 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 16298 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 16299 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 16300 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
16301 | #endif |
16302 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 16303 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 16304 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 16305 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 16306 | #endif |
b3b91714 | 16307 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
16308 | {"march", required_argument, NULL, OPTION_MARCH}, |
16309 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
16310 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
16311 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
16312 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
16313 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 16314 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
c8480b58 | 16315 | {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE}, |
daf50ae7 | 16316 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 16317 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 16318 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 16319 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 16320 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
16321 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
16322 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
16323 | # if defined (TE_PE) || defined (TE_PEP) |
16324 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
16325 | #endif | |
d1982f93 | 16326 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 16327 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 16328 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 16329 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
16330 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
16331 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
16332 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 16333 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
16334 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
16335 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
16336 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
16337 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
16338 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
16339 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
16340 | {NULL, no_argument, NULL, 0} |
16341 | }; | |
16342 | size_t md_longopts_size = sizeof (md_longopts); | |
16343 | ||
16344 | int | |
17b9d67d | 16345 | md_parse_option (int c, const char *arg) |
252b5132 | 16346 | { |
91d6fa6a | 16347 | unsigned int j; |
e379e5f3 | 16348 | char *arch, *next, *saved, *type; |
9103f4f4 | 16349 | |
252b5132 RH |
16350 | switch (c) |
16351 | { | |
12b55ccc L |
16352 | case 'n': |
16353 | optimize_align_code = 0; | |
16354 | break; | |
16355 | ||
a38cf1db AM |
16356 | case 'q': |
16357 | quiet_warnings = 1; | |
252b5132 RH |
16358 | break; |
16359 | ||
16360 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
16361 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
16362 | should be emitted or not. FIXME: Not implemented. */ | |
16363 | case 'Q': | |
d4693039 JB |
16364 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
16365 | return 0; | |
252b5132 RH |
16366 | break; |
16367 | ||
16368 | /* -V: SVR4 argument to print version ID. */ | |
16369 | case 'V': | |
16370 | print_version_id (); | |
16371 | break; | |
16372 | ||
a38cf1db AM |
16373 | /* -k: Ignore for FreeBSD compatibility. */ |
16374 | case 'k': | |
252b5132 | 16375 | break; |
4cc782b5 ILT |
16376 | |
16377 | case 's': | |
16378 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 16379 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 16380 | break; |
8dcea932 L |
16381 | |
16382 | case OPTION_MSHARED: | |
16383 | shared = 1; | |
16384 | break; | |
b4a3a7b4 L |
16385 | |
16386 | case OPTION_X86_USED_NOTE: | |
16387 | if (strcasecmp (arg, "yes") == 0) | |
16388 | x86_used_note = 1; | |
16389 | else if (strcasecmp (arg, "no") == 0) | |
16390 | x86_used_note = 0; | |
16391 | else | |
16392 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
16393 | break; | |
16394 | ||
16395 | ||
99ad8390 | 16396 | #endif |
321098a5 | 16397 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 16398 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
16399 | case OPTION_64: |
16400 | { | |
16401 | const char **list, **l; | |
16402 | ||
3e73aa7c JH |
16403 | list = bfd_target_list (); |
16404 | for (l = list; *l != NULL; l++) | |
08dedd66 | 16405 | if (startswith (*l, "elf64-x86-64") |
99ad8390 NC |
16406 | || strcmp (*l, "coff-x86-64") == 0 |
16407 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
16408 | || strcmp (*l, "pei-x86-64") == 0 |
16409 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
16410 | { |
16411 | default_arch = "x86_64"; | |
16412 | break; | |
16413 | } | |
3e73aa7c | 16414 | if (*l == NULL) |
2b5d6a91 | 16415 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
16416 | free (list); |
16417 | } | |
16418 | break; | |
16419 | #endif | |
252b5132 | 16420 | |
351f65ca | 16421 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 16422 | case OPTION_X32: |
351f65ca L |
16423 | if (IS_ELF) |
16424 | { | |
16425 | const char **list, **l; | |
16426 | ||
16427 | list = bfd_target_list (); | |
16428 | for (l = list; *l != NULL; l++) | |
08dedd66 | 16429 | if (startswith (*l, "elf32-x86-64")) |
351f65ca L |
16430 | { |
16431 | default_arch = "x86_64:32"; | |
16432 | break; | |
16433 | } | |
16434 | if (*l == NULL) | |
2b5d6a91 | 16435 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
16436 | free (list); |
16437 | } | |
16438 | else | |
16439 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
16440 | break; | |
16441 | #endif | |
16442 | ||
6e0b89ee | 16443 | case OPTION_32: |
590a0fed JB |
16444 | { |
16445 | const char **list, **l; | |
16446 | ||
16447 | list = bfd_target_list (); | |
16448 | for (l = list; *l != NULL; l++) | |
16449 | if (strstr (*l, "-i386") | |
16450 | || strstr (*l, "-go32")) | |
16451 | { | |
16452 | default_arch = "i386"; | |
16453 | break; | |
16454 | } | |
16455 | if (*l == NULL) | |
16456 | as_fatal (_("no compiled in support for ix86")); | |
16457 | free (list); | |
16458 | } | |
6e0b89ee AM |
16459 | break; |
16460 | ||
b3b91714 AM |
16461 | case OPTION_DIVIDE: |
16462 | #ifdef SVR4_COMMENT_CHARS | |
16463 | { | |
16464 | char *n, *t; | |
16465 | const char *s; | |
16466 | ||
add39d23 | 16467 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
16468 | t = n; |
16469 | for (s = i386_comment_chars; *s != '\0'; s++) | |
16470 | if (*s != '/') | |
16471 | *t++ = *s; | |
16472 | *t = '\0'; | |
16473 | i386_comment_chars = n; | |
16474 | } | |
16475 | #endif | |
16476 | break; | |
16477 | ||
9103f4f4 | 16478 | case OPTION_MARCH: |
293f5f65 L |
16479 | saved = xstrdup (arg); |
16480 | arch = saved; | |
16481 | /* Allow -march=+nosse. */ | |
16482 | if (*arch == '+') | |
16483 | arch++; | |
6305a203 | 16484 | do |
9103f4f4 | 16485 | { |
4fc85f37 JB |
16486 | char *vsz; |
16487 | ||
6305a203 | 16488 | if (*arch == '.') |
2b5d6a91 | 16489 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
16490 | next = strchr (arch, '+'); |
16491 | if (next) | |
16492 | *next++ = '\0'; | |
4fc85f37 JB |
16493 | vsz = strchr (arch, '/'); |
16494 | if (vsz) | |
16495 | *vsz++ = '\0'; | |
91d6fa6a | 16496 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 16497 | { |
4fc85f37 JB |
16498 | if (vsz && cpu_arch[j].vsz != vsz_set) |
16499 | continue; | |
16500 | ||
ae89daec JB |
16501 | if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE |
16502 | && strcmp (arch, cpu_arch[j].name) == 0) | |
ccc9c027 | 16503 | { |
6305a203 | 16504 | /* Processor. */ |
ae89daec | 16505 | if (! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
16506 | continue; |
16507 | ||
91d6fa6a | 16508 | cpu_arch_name = cpu_arch[j].name; |
d92c7521 | 16509 | free (cpu_sub_arch_name); |
6305a203 | 16510 | cpu_sub_arch_name = NULL; |
ae89daec | 16511 | cpu_arch_flags = cpu_arch[j].enable; |
91d6fa6a | 16512 | cpu_arch_isa = cpu_arch[j].type; |
ae89daec | 16513 | cpu_arch_isa_flags = cpu_arch[j].enable; |
6305a203 | 16514 | if (!cpu_arch_tune_set) |
fb263707 | 16515 | cpu_arch_tune = cpu_arch_isa; |
4fc85f37 | 16516 | vector_size = VSZ_DEFAULT; |
6305a203 L |
16517 | break; |
16518 | } | |
ae89daec JB |
16519 | else if (cpu_arch[j].type == PROCESSOR_NONE |
16520 | && strcmp (arch, cpu_arch[j].name) == 0 | |
16521 | && !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
6305a203 | 16522 | { |
33eaf5de | 16523 | /* ISA extension. */ |
bd483d21 | 16524 | isa_enable (j); |
4fc85f37 JB |
16525 | |
16526 | switch (cpu_arch[j].vsz) | |
16527 | { | |
16528 | default: | |
16529 | break; | |
16530 | ||
16531 | case vsz_set: | |
16532 | if (vsz) | |
16533 | { | |
16534 | char *end; | |
16535 | unsigned long val = strtoul (vsz, &end, 0); | |
16536 | ||
16537 | if (*end) | |
16538 | val = 0; | |
16539 | switch (val) | |
16540 | { | |
16541 | case 512: vector_size = VSZ512; break; | |
16542 | case 256: vector_size = VSZ256; break; | |
16543 | case 128: vector_size = VSZ128; break; | |
16544 | default: | |
16545 | as_warn (_("Unrecognized vector size specifier ignored")); | |
16546 | break; | |
16547 | } | |
16548 | break; | |
16549 | } | |
16550 | /* Fall through. */ | |
16551 | case vsz_reset: | |
16552 | vector_size = VSZ_DEFAULT; | |
16553 | break; | |
16554 | } | |
16555 | ||
6305a203 | 16556 | break; |
ccc9c027 | 16557 | } |
9103f4f4 | 16558 | } |
6305a203 | 16559 | |
ae89daec | 16560 | if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no")) |
293f5f65 | 16561 | { |
33eaf5de | 16562 | /* Disable an ISA extension. */ |
ae89daec JB |
16563 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
16564 | if (cpu_arch[j].type == PROCESSOR_NONE | |
16565 | && strcmp (arch + 2, cpu_arch[j].name) == 0) | |
293f5f65 | 16566 | { |
bd483d21 | 16567 | isa_disable (j); |
4fc85f37 JB |
16568 | if (cpu_arch[j].vsz == vsz_set) |
16569 | vector_size = VSZ_DEFAULT; | |
293f5f65 L |
16570 | break; |
16571 | } | |
293f5f65 L |
16572 | } |
16573 | ||
91d6fa6a | 16574 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 16575 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
16576 | |
16577 | arch = next; | |
9103f4f4 | 16578 | } |
293f5f65 L |
16579 | while (next != NULL); |
16580 | free (saved); | |
9103f4f4 L |
16581 | break; |
16582 | ||
16583 | case OPTION_MTUNE: | |
16584 | if (*arg == '.') | |
2b5d6a91 | 16585 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 16586 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 16587 | { |
ae89daec JB |
16588 | if (cpu_arch[j].type != PROCESSOR_NONE |
16589 | && strcmp (arg, cpu_arch[j].name) == 0) | |
9103f4f4 | 16590 | { |
ccc9c027 | 16591 | cpu_arch_tune_set = 1; |
91d6fa6a | 16592 | cpu_arch_tune = cpu_arch [j].type; |
9103f4f4 L |
16593 | break; |
16594 | } | |
16595 | } | |
91d6fa6a | 16596 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 16597 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
16598 | break; |
16599 | ||
1efbbeb4 L |
16600 | case OPTION_MMNEMONIC: |
16601 | if (strcasecmp (arg, "att") == 0) | |
16602 | intel_mnemonic = 0; | |
16603 | else if (strcasecmp (arg, "intel") == 0) | |
16604 | intel_mnemonic = 1; | |
16605 | else | |
2b5d6a91 | 16606 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
16607 | break; |
16608 | ||
16609 | case OPTION_MSYNTAX: | |
16610 | if (strcasecmp (arg, "att") == 0) | |
213f15cf | 16611 | _set_intel_syntax (0); |
1efbbeb4 | 16612 | else if (strcasecmp (arg, "intel") == 0) |
213f15cf | 16613 | _set_intel_syntax (1); |
1efbbeb4 | 16614 | else |
2b5d6a91 | 16615 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
16616 | break; |
16617 | ||
16618 | case OPTION_MINDEX_REG: | |
16619 | allow_index_reg = 1; | |
16620 | break; | |
16621 | ||
16622 | case OPTION_MNAKED_REG: | |
16623 | allow_naked_reg = 1; | |
213f15cf | 16624 | register_prefix = ""; |
1efbbeb4 L |
16625 | break; |
16626 | ||
c0f3af97 L |
16627 | case OPTION_MSSE2AVX: |
16628 | sse2avx = 1; | |
16629 | break; | |
16630 | ||
c8480b58 L |
16631 | case OPTION_MUSE_UNALIGNED_VECTOR_MOVE: |
16632 | use_unaligned_vector_move = 1; | |
16633 | break; | |
16634 | ||
daf50ae7 L |
16635 | case OPTION_MSSE_CHECK: |
16636 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 16637 | sse_check = check_error; |
daf50ae7 | 16638 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 16639 | sse_check = check_warning; |
daf50ae7 | 16640 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 16641 | sse_check = check_none; |
daf50ae7 | 16642 | else |
2b5d6a91 | 16643 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
16644 | break; |
16645 | ||
7bab8ab5 JB |
16646 | case OPTION_MOPERAND_CHECK: |
16647 | if (strcasecmp (arg, "error") == 0) | |
16648 | operand_check = check_error; | |
16649 | else if (strcasecmp (arg, "warning") == 0) | |
16650 | operand_check = check_warning; | |
16651 | else if (strcasecmp (arg, "none") == 0) | |
16652 | operand_check = check_none; | |
16653 | else | |
16654 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
16655 | break; | |
16656 | ||
539f890d L |
16657 | case OPTION_MAVXSCALAR: |
16658 | if (strcasecmp (arg, "128") == 0) | |
16659 | avxscalar = vex128; | |
16660 | else if (strcasecmp (arg, "256") == 0) | |
16661 | avxscalar = vex256; | |
16662 | else | |
2b5d6a91 | 16663 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
16664 | break; |
16665 | ||
03751133 L |
16666 | case OPTION_MVEXWIG: |
16667 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 16668 | vexwig = vexw0; |
03751133 | 16669 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 16670 | vexwig = vexw1; |
03751133 L |
16671 | else |
16672 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
16673 | break; | |
16674 | ||
7e8b059b L |
16675 | case OPTION_MADD_BND_PREFIX: |
16676 | add_bnd_prefix = 1; | |
16677 | break; | |
16678 | ||
43234a1e L |
16679 | case OPTION_MEVEXLIG: |
16680 | if (strcmp (arg, "128") == 0) | |
16681 | evexlig = evexl128; | |
16682 | else if (strcmp (arg, "256") == 0) | |
16683 | evexlig = evexl256; | |
16684 | else if (strcmp (arg, "512") == 0) | |
16685 | evexlig = evexl512; | |
16686 | else | |
16687 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
16688 | break; | |
16689 | ||
d3d3c6db IT |
16690 | case OPTION_MEVEXRCIG: |
16691 | if (strcmp (arg, "rne") == 0) | |
16692 | evexrcig = rne; | |
16693 | else if (strcmp (arg, "rd") == 0) | |
16694 | evexrcig = rd; | |
16695 | else if (strcmp (arg, "ru") == 0) | |
16696 | evexrcig = ru; | |
16697 | else if (strcmp (arg, "rz") == 0) | |
16698 | evexrcig = rz; | |
16699 | else | |
16700 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
16701 | break; | |
16702 | ||
43234a1e L |
16703 | case OPTION_MEVEXWIG: |
16704 | if (strcmp (arg, "0") == 0) | |
16705 | evexwig = evexw0; | |
16706 | else if (strcmp (arg, "1") == 0) | |
16707 | evexwig = evexw1; | |
16708 | else | |
16709 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
16710 | break; | |
16711 | ||
167ad85b TG |
16712 | # if defined (TE_PE) || defined (TE_PEP) |
16713 | case OPTION_MBIG_OBJ: | |
16714 | use_big_obj = 1; | |
16715 | break; | |
16716 | #endif | |
16717 | ||
d1982f93 | 16718 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
16719 | if (strcasecmp (arg, "yes") == 0) |
16720 | omit_lock_prefix = 1; | |
16721 | else if (strcasecmp (arg, "no") == 0) | |
16722 | omit_lock_prefix = 0; | |
16723 | else | |
16724 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
16725 | break; | |
16726 | ||
e4e00185 AS |
16727 | case OPTION_MFENCE_AS_LOCK_ADD: |
16728 | if (strcasecmp (arg, "yes") == 0) | |
16729 | avoid_fence = 1; | |
16730 | else if (strcasecmp (arg, "no") == 0) | |
16731 | avoid_fence = 0; | |
16732 | else | |
16733 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
16734 | break; | |
16735 | ||
ae531041 L |
16736 | case OPTION_MLFENCE_AFTER_LOAD: |
16737 | if (strcasecmp (arg, "yes") == 0) | |
16738 | lfence_after_load = 1; | |
16739 | else if (strcasecmp (arg, "no") == 0) | |
16740 | lfence_after_load = 0; | |
16741 | else | |
16742 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
16743 | break; | |
16744 | ||
16745 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
16746 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 16747 | { |
16748 | lfence_before_indirect_branch = lfence_branch_all; | |
16749 | if (lfence_before_ret == lfence_before_ret_none) | |
16750 | lfence_before_ret = lfence_before_ret_shl; | |
16751 | } | |
ae531041 L |
16752 | else if (strcasecmp (arg, "memory") == 0) |
16753 | lfence_before_indirect_branch = lfence_branch_memory; | |
16754 | else if (strcasecmp (arg, "register") == 0) | |
16755 | lfence_before_indirect_branch = lfence_branch_register; | |
16756 | else if (strcasecmp (arg, "none") == 0) | |
16757 | lfence_before_indirect_branch = lfence_branch_none; | |
16758 | else | |
16759 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
16760 | arg); | |
16761 | break; | |
16762 | ||
16763 | case OPTION_MLFENCE_BEFORE_RET: | |
16764 | if (strcasecmp (arg, "or") == 0) | |
16765 | lfence_before_ret = lfence_before_ret_or; | |
16766 | else if (strcasecmp (arg, "not") == 0) | |
16767 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 16768 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
16769 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
16770 | else if (strcasecmp (arg, "none") == 0) |
16771 | lfence_before_ret = lfence_before_ret_none; | |
16772 | else | |
16773 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
16774 | arg); | |
16775 | break; | |
16776 | ||
0cb4071e L |
16777 | case OPTION_MRELAX_RELOCATIONS: |
16778 | if (strcasecmp (arg, "yes") == 0) | |
16779 | generate_relax_relocations = 1; | |
16780 | else if (strcasecmp (arg, "no") == 0) | |
16781 | generate_relax_relocations = 0; | |
16782 | else | |
16783 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
16784 | break; | |
16785 | ||
e379e5f3 L |
16786 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
16787 | { | |
16788 | char *end; | |
16789 | long int align = strtoul (arg, &end, 0); | |
16790 | if (*end == '\0') | |
16791 | { | |
16792 | if (align == 0) | |
16793 | { | |
16794 | align_branch_power = 0; | |
16795 | break; | |
16796 | } | |
16797 | else if (align >= 16) | |
16798 | { | |
16799 | int align_power; | |
16800 | for (align_power = 0; | |
16801 | (align & 1) == 0; | |
16802 | align >>= 1, align_power++) | |
16803 | continue; | |
16804 | /* Limit alignment power to 31. */ | |
16805 | if (align == 1 && align_power < 32) | |
16806 | { | |
16807 | align_branch_power = align_power; | |
16808 | break; | |
16809 | } | |
16810 | } | |
16811 | } | |
16812 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
16813 | } | |
16814 | break; | |
16815 | ||
16816 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
16817 | { | |
16818 | char *end; | |
16819 | int align = strtoul (arg, &end, 0); | |
16820 | /* Some processors only support 5 prefixes. */ | |
16821 | if (*end == '\0' && align >= 0 && align < 6) | |
16822 | { | |
16823 | align_branch_prefix_size = align; | |
16824 | break; | |
16825 | } | |
16826 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
16827 | arg); | |
16828 | } | |
16829 | break; | |
16830 | ||
16831 | case OPTION_MALIGN_BRANCH: | |
16832 | align_branch = 0; | |
16833 | saved = xstrdup (arg); | |
16834 | type = saved; | |
16835 | do | |
16836 | { | |
16837 | next = strchr (type, '+'); | |
16838 | if (next) | |
16839 | *next++ = '\0'; | |
16840 | if (strcasecmp (type, "jcc") == 0) | |
16841 | align_branch |= align_branch_jcc_bit; | |
16842 | else if (strcasecmp (type, "fused") == 0) | |
16843 | align_branch |= align_branch_fused_bit; | |
16844 | else if (strcasecmp (type, "jmp") == 0) | |
16845 | align_branch |= align_branch_jmp_bit; | |
16846 | else if (strcasecmp (type, "call") == 0) | |
16847 | align_branch |= align_branch_call_bit; | |
16848 | else if (strcasecmp (type, "ret") == 0) | |
16849 | align_branch |= align_branch_ret_bit; | |
16850 | else if (strcasecmp (type, "indirect") == 0) | |
16851 | align_branch |= align_branch_indirect_bit; | |
16852 | else | |
16853 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
16854 | type = next; | |
16855 | } | |
16856 | while (next != NULL); | |
16857 | free (saved); | |
16858 | break; | |
16859 | ||
76cf450b L |
16860 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
16861 | align_branch_power = 5; | |
16862 | align_branch_prefix_size = 5; | |
16863 | align_branch = (align_branch_jcc_bit | |
16864 | | align_branch_fused_bit | |
16865 | | align_branch_jmp_bit); | |
16866 | break; | |
16867 | ||
5db04b09 | 16868 | case OPTION_MAMD64: |
4b5aaf5f | 16869 | isa64 = amd64; |
5db04b09 L |
16870 | break; |
16871 | ||
16872 | case OPTION_MINTEL64: | |
4b5aaf5f | 16873 | isa64 = intel64; |
5db04b09 L |
16874 | break; |
16875 | ||
b6f8c7c4 L |
16876 | case 'O': |
16877 | if (arg == NULL) | |
16878 | { | |
16879 | optimize = 1; | |
16880 | /* Turn off -Os. */ | |
16881 | optimize_for_space = 0; | |
16882 | } | |
16883 | else if (*arg == 's') | |
16884 | { | |
16885 | optimize_for_space = 1; | |
16886 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 16887 | optimize = INT_MAX; |
b6f8c7c4 L |
16888 | } |
16889 | else | |
16890 | { | |
16891 | optimize = atoi (arg); | |
16892 | /* Turn off -Os. */ | |
16893 | optimize_for_space = 0; | |
16894 | } | |
16895 | break; | |
16896 | ||
252b5132 RH |
16897 | default: |
16898 | return 0; | |
16899 | } | |
16900 | return 1; | |
16901 | } | |
16902 | ||
8a2c8fef L |
16903 | #define MESSAGE_TEMPLATE \ |
16904 | " " | |
16905 | ||
293f5f65 L |
16906 | static char * |
16907 | output_message (FILE *stream, char *p, char *message, char *start, | |
16908 | int *left_p, const char *name, int len) | |
16909 | { | |
16910 | int size = sizeof (MESSAGE_TEMPLATE); | |
16911 | int left = *left_p; | |
16912 | ||
16913 | /* Reserve 2 spaces for ", " or ",\0" */ | |
16914 | left -= len + 2; | |
16915 | ||
16916 | /* Check if there is any room. */ | |
16917 | if (left >= 0) | |
16918 | { | |
16919 | if (p != start) | |
16920 | { | |
16921 | *p++ = ','; | |
16922 | *p++ = ' '; | |
16923 | } | |
16924 | p = mempcpy (p, name, len); | |
16925 | } | |
16926 | else | |
16927 | { | |
16928 | /* Output the current message now and start a new one. */ | |
16929 | *p++ = ','; | |
16930 | *p = '\0'; | |
16931 | fprintf (stream, "%s\n", message); | |
16932 | p = start; | |
16933 | left = size - (start - message) - len - 2; | |
16934 | ||
16935 | gas_assert (left >= 0); | |
16936 | ||
16937 | p = mempcpy (p, name, len); | |
16938 | } | |
16939 | ||
16940 | *left_p = left; | |
16941 | return p; | |
16942 | } | |
16943 | ||
8a2c8fef | 16944 | static void |
1ded5609 | 16945 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
16946 | { |
16947 | static char message[] = MESSAGE_TEMPLATE; | |
16948 | char *start = message + 27; | |
16949 | char *p; | |
16950 | int size = sizeof (MESSAGE_TEMPLATE); | |
16951 | int left; | |
16952 | const char *name; | |
16953 | int len; | |
16954 | unsigned int j; | |
16955 | ||
16956 | p = start; | |
16957 | left = size - (start - message); | |
3ce2ebcf JB |
16958 | |
16959 | if (!ext && check) | |
16960 | { | |
16961 | p = output_message (stream, p, message, start, &left, | |
16962 | STRING_COMMA_LEN ("default")); | |
f68697e8 JB |
16963 | p = output_message (stream, p, message, start, &left, |
16964 | STRING_COMMA_LEN ("push")); | |
16965 | p = output_message (stream, p, message, start, &left, | |
16966 | STRING_COMMA_LEN ("pop")); | |
3ce2ebcf JB |
16967 | } |
16968 | ||
8a2c8fef L |
16969 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
16970 | { | |
16971 | /* Should it be skipped? */ | |
16972 | if (cpu_arch [j].skip) | |
16973 | continue; | |
16974 | ||
16975 | name = cpu_arch [j].name; | |
16976 | len = cpu_arch [j].len; | |
ae89daec | 16977 | if (cpu_arch[j].type == PROCESSOR_NONE) |
8a2c8fef L |
16978 | { |
16979 | /* It is an extension. Skip if we aren't asked to show it. */ | |
ae89daec | 16980 | if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable)) |
8a2c8fef L |
16981 | continue; |
16982 | } | |
16983 | else if (ext) | |
16984 | { | |
16985 | /* It is an processor. Skip if we show only extension. */ | |
16986 | continue; | |
16987 | } | |
ae89daec | 16988 | else if (check && ! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
16989 | { |
16990 | /* It is an impossible processor - skip. */ | |
16991 | continue; | |
16992 | } | |
8a2c8fef | 16993 | |
293f5f65 | 16994 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
16995 | } |
16996 | ||
293f5f65 L |
16997 | /* Display disabled extensions. */ |
16998 | if (ext) | |
ae89daec | 16999 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
293f5f65 | 17000 | { |
ae89daec JB |
17001 | char *str; |
17002 | ||
17003 | if (cpu_arch[j].type != PROCESSOR_NONE | |
17004 | || !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
17005 | continue; | |
17006 | str = xasprintf ("no%s", cpu_arch[j].name); | |
17007 | p = output_message (stream, p, message, start, &left, str, | |
17008 | strlen (str)); | |
17009 | free (str); | |
293f5f65 L |
17010 | } |
17011 | ||
8a2c8fef L |
17012 | *p = '\0'; |
17013 | fprintf (stream, "%s\n", message); | |
17014 | } | |
17015 | ||
252b5132 | 17016 | void |
8a2c8fef | 17017 | md_show_usage (FILE *stream) |
252b5132 | 17018 | { |
4cc782b5 ILT |
17019 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
17020 | fprintf (stream, _("\ | |
d4693039 | 17021 | -Qy, -Qn ignored\n\ |
a38cf1db | 17022 | -V print assembler version number\n\ |
b3b91714 AM |
17023 | -k ignored\n")); |
17024 | #endif | |
17025 | fprintf (stream, _("\ | |
7ebd68d1 NC |
17026 | -n do not optimize code alignment\n\ |
17027 | -O{012s} attempt some code optimizations\n\ | |
b3b91714 AM |
17028 | -q quieten some warnings\n")); |
17029 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
17030 | fprintf (stream, _("\ | |
a38cf1db | 17031 | -s ignored\n")); |
b3b91714 | 17032 | #endif |
b00af7c8 JB |
17033 | #ifdef BFD64 |
17034 | # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
17035 | fprintf (stream, _("\ | |
17036 | --32/--64/--x32 generate 32bit/64bit/x32 object\n")); | |
17037 | # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O) | |
751d281c | 17038 | fprintf (stream, _("\ |
b00af7c8 JB |
17039 | --32/--64 generate 32bit/64bit object\n")); |
17040 | # endif | |
751d281c | 17041 | #endif |
b3b91714 AM |
17042 | #ifdef SVR4_COMMENT_CHARS |
17043 | fprintf (stream, _("\ | |
17044 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
17045 | #else |
17046 | fprintf (stream, _("\ | |
b3b91714 | 17047 | --divide ignored\n")); |
4cc782b5 | 17048 | #endif |
9103f4f4 | 17049 | fprintf (stream, _("\ |
6305a203 | 17050 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 17051 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 17052 | show_arch (stream, 0, 1); |
8a2c8fef | 17053 | fprintf (stream, _("\ |
ae89daec | 17054 | EXTENSION is combination of (possibly \"no\"-prefixed):\n")); |
1ded5609 | 17055 | show_arch (stream, 1, 0); |
6305a203 | 17056 | fprintf (stream, _("\ |
8a2c8fef | 17057 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 17058 | show_arch (stream, 0, 0); |
ba104c83 | 17059 | fprintf (stream, _("\ |
c0f3af97 L |
17060 | -msse2avx encode SSE instructions with VEX prefix\n")); |
17061 | fprintf (stream, _("\ | |
c8480b58 L |
17062 | -muse-unaligned-vector-move\n\ |
17063 | encode aligned vector move as unaligned vector move\n")); | |
17064 | fprintf (stream, _("\ | |
7a6a03c4 | 17065 | -msse-check=[none|error|warning] (default: none)\n\ |
daf50ae7 L |
17066 | check SSE instructions\n")); |
17067 | fprintf (stream, _("\ | |
7c5c05ef | 17068 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
17069 | check operand combinations for validity\n")); |
17070 | fprintf (stream, _("\ | |
7c5c05ef L |
17071 | -mavxscalar=[128|256] (default: 128)\n\ |
17072 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
17073 | length\n")); |
17074 | fprintf (stream, _("\ | |
03751133 L |
17075 | -mvexwig=[0|1] (default: 0)\n\ |
17076 | encode VEX instructions with specific VEX.W value\n\ | |
17077 | for VEX.W bit ignored instructions\n")); | |
17078 | fprintf (stream, _("\ | |
7c5c05ef L |
17079 | -mevexlig=[128|256|512] (default: 128)\n\ |
17080 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
17081 | length\n")); |
17082 | fprintf (stream, _("\ | |
7c5c05ef L |
17083 | -mevexwig=[0|1] (default: 0)\n\ |
17084 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
17085 | for EVEX.W bit ignored instructions\n")); |
17086 | fprintf (stream, _("\ | |
7c5c05ef | 17087 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
17088 | encode EVEX instructions with specific EVEX.RC value\n\ |
17089 | for SAE-only ignored instructions\n")); | |
17090 | fprintf (stream, _("\ | |
7c5c05ef L |
17091 | -mmnemonic=[att|intel] ")); |
17092 | if (SYSV386_COMPAT) | |
17093 | fprintf (stream, _("(default: att)\n")); | |
17094 | else | |
17095 | fprintf (stream, _("(default: intel)\n")); | |
17096 | fprintf (stream, _("\ | |
7d3182d6 | 17097 | use AT&T/Intel mnemonic (AT&T syntax only)\n")); |
ba104c83 | 17098 | fprintf (stream, _("\ |
7c5c05ef L |
17099 | -msyntax=[att|intel] (default: att)\n\ |
17100 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
17101 | fprintf (stream, _("\ |
17102 | -mindex-reg support pseudo index registers\n")); | |
17103 | fprintf (stream, _("\ | |
17104 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
17105 | fprintf (stream, _("\ | |
7e8b059b | 17106 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 17107 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
17108 | fprintf (stream, _("\ |
17109 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
17110 | fprintf (stream, _("\ |
17111 | -mx86-used-note=[no|yes] ")); | |
17112 | if (DEFAULT_X86_USED_NOTE) | |
17113 | fprintf (stream, _("(default: yes)\n")); | |
17114 | else | |
17115 | fprintf (stream, _("(default: no)\n")); | |
17116 | fprintf (stream, _("\ | |
17117 | generate x86 used ISA and feature properties\n")); | |
17118 | #endif | |
17119 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
17120 | fprintf (stream, _("\ |
17121 | -mbig-obj generate big object files\n")); | |
17122 | #endif | |
d022bddd | 17123 | fprintf (stream, _("\ |
7c5c05ef | 17124 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 17125 | strip all lock prefixes\n")); |
5db04b09 | 17126 | fprintf (stream, _("\ |
7c5c05ef | 17127 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
17128 | encode lfence, mfence and sfence as\n\ |
17129 | lock addl $0x0, (%%{re}sp)\n")); | |
17130 | fprintf (stream, _("\ | |
7c5c05ef L |
17131 | -mrelax-relocations=[no|yes] ")); |
17132 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
17133 | fprintf (stream, _("(default: yes)\n")); | |
17134 | else | |
17135 | fprintf (stream, _("(default: no)\n")); | |
17136 | fprintf (stream, _("\ | |
0cb4071e L |
17137 | generate relax relocations\n")); |
17138 | fprintf (stream, _("\ | |
e379e5f3 L |
17139 | -malign-branch-boundary=NUM (default: 0)\n\ |
17140 | align branches within NUM byte boundary\n")); | |
17141 | fprintf (stream, _("\ | |
17142 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
17143 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
17144 | indirect\n\ | |
17145 | specify types of branches to align\n")); | |
17146 | fprintf (stream, _("\ | |
17147 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
17148 | align branches with NUM prefixes per instruction\n")); | |
17149 | fprintf (stream, _("\ | |
76cf450b L |
17150 | -mbranches-within-32B-boundaries\n\ |
17151 | align branches within 32 byte boundary\n")); | |
17152 | fprintf (stream, _("\ | |
ae531041 L |
17153 | -mlfence-after-load=[no|yes] (default: no)\n\ |
17154 | generate lfence after load\n")); | |
17155 | fprintf (stream, _("\ | |
17156 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
17157 | generate lfence before indirect near branch\n")); | |
17158 | fprintf (stream, _("\ | |
a09f656b | 17159 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
17160 | generate lfence before ret\n")); |
17161 | fprintf (stream, _("\ | |
7c5c05ef | 17162 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
17163 | fprintf (stream, _("\ |
17164 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
17165 | } |
17166 | ||
3e73aa7c | 17167 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 17168 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 17169 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
17170 | |
17171 | /* Pick the target format to use. */ | |
17172 | ||
47926f60 | 17173 | const char * |
e3bb37b5 | 17174 | i386_target_format (void) |
252b5132 | 17175 | { |
d34049e8 | 17176 | if (startswith (default_arch, "x86_64")) |
351f65ca L |
17177 | { |
17178 | update_code_flag (CODE_64BIT, 1); | |
071c5d81 | 17179 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
351f65ca | 17180 | if (default_arch[6] == '\0') |
7f56bc95 | 17181 | x86_elf_abi = X86_64_ABI; |
351f65ca | 17182 | else |
7f56bc95 | 17183 | x86_elf_abi = X86_64_X32_ABI; |
071c5d81 | 17184 | #endif |
351f65ca | 17185 | } |
3e73aa7c | 17186 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 17187 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
17188 | else if (!strcmp (default_arch, "iamcu")) |
17189 | { | |
17190 | update_code_flag (CODE_32BIT, 1); | |
17191 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
17192 | { | |
17193 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
17194 | cpu_arch_name = "iamcu"; | |
d92c7521 | 17195 | free (cpu_sub_arch_name); |
5197d474 L |
17196 | cpu_sub_arch_name = NULL; |
17197 | cpu_arch_flags = iamcu_flags; | |
17198 | cpu_arch_isa = PROCESSOR_IAMCU; | |
17199 | cpu_arch_isa_flags = iamcu_flags; | |
17200 | if (!cpu_arch_tune_set) | |
fb263707 | 17201 | cpu_arch_tune = PROCESSOR_IAMCU; |
5197d474 | 17202 | } |
8d471ec1 | 17203 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
17204 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
17205 | cpu_arch_name); | |
17206 | } | |
3e73aa7c | 17207 | else |
2b5d6a91 | 17208 | as_fatal (_("unknown architecture")); |
89507696 | 17209 | |
c7defc53 IB |
17210 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
17211 | if (IS_ELF && flag_synth_cfi && x86_elf_abi != X86_64_ABI) | |
17212 | as_fatal (_("SCFI is not supported for this ABI")); | |
17213 | #endif | |
17214 | ||
89507696 | 17215 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
ae89daec | 17216 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 17217 | |
252b5132 RH |
17218 | switch (OUTPUT_FLAVOR) |
17219 | { | |
9384f2ff | 17220 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 17221 | case bfd_target_aout_flavour: |
47926f60 | 17222 | return AOUT_TARGET_FORMAT; |
4c63da97 | 17223 | #endif |
9384f2ff AM |
17224 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
17225 | # if defined (TE_PE) || defined (TE_PEP) | |
17226 | case bfd_target_coff_flavour: | |
167ad85b | 17227 | if (flag_code == CODE_64BIT) |
eb19308f JB |
17228 | { |
17229 | object_64bit = 1; | |
17230 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
17231 | } | |
17232 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; | |
9384f2ff | 17233 | # elif defined (TE_GO32) |
0561d57c JK |
17234 | case bfd_target_coff_flavour: |
17235 | return "coff-go32"; | |
9384f2ff | 17236 | # else |
252b5132 RH |
17237 | case bfd_target_coff_flavour: |
17238 | return "coff-i386"; | |
9384f2ff | 17239 | # endif |
4c63da97 | 17240 | #endif |
3e73aa7c | 17241 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 17242 | case bfd_target_elf_flavour: |
3e73aa7c | 17243 | { |
351f65ca L |
17244 | const char *format; |
17245 | ||
17246 | switch (x86_elf_abi) | |
4fa24527 | 17247 | { |
351f65ca L |
17248 | default: |
17249 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
17250 | #ifndef TE_SOLARIS |
17251 | tls_get_addr = "___tls_get_addr"; | |
17252 | #endif | |
351f65ca | 17253 | break; |
7f56bc95 | 17254 | case X86_64_ABI: |
351f65ca | 17255 | use_rela_relocations = 1; |
4fa24527 | 17256 | object_64bit = 1; |
e379e5f3 L |
17257 | #ifndef TE_SOLARIS |
17258 | tls_get_addr = "__tls_get_addr"; | |
17259 | #endif | |
351f65ca L |
17260 | format = ELF_TARGET_FORMAT64; |
17261 | break; | |
7f56bc95 | 17262 | case X86_64_X32_ABI: |
4fa24527 | 17263 | use_rela_relocations = 1; |
351f65ca | 17264 | object_64bit = 1; |
e379e5f3 L |
17265 | #ifndef TE_SOLARIS |
17266 | tls_get_addr = "__tls_get_addr"; | |
17267 | #endif | |
862be3fb | 17268 | disallow_64bit_reloc = 1; |
351f65ca L |
17269 | format = ELF_TARGET_FORMAT32; |
17270 | break; | |
4fa24527 | 17271 | } |
c085ab00 | 17272 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
17273 | { |
17274 | if (x86_elf_abi != I386_ABI) | |
17275 | as_fatal (_("Intel MCU is 32bit only")); | |
17276 | return ELF_TARGET_IAMCU_FORMAT; | |
17277 | } | |
8a9036a4 | 17278 | else |
351f65ca | 17279 | return format; |
3e73aa7c | 17280 | } |
e57f8c65 TG |
17281 | #endif |
17282 | #if defined (OBJ_MACH_O) | |
17283 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
17284 | if (flag_code == CODE_64BIT) |
17285 | { | |
17286 | use_rela_relocations = 1; | |
17287 | object_64bit = 1; | |
17288 | return "mach-o-x86-64"; | |
17289 | } | |
17290 | else | |
17291 | return "mach-o-i386"; | |
4c63da97 | 17292 | #endif |
252b5132 RH |
17293 | default: |
17294 | abort (); | |
17295 | return NULL; | |
17296 | } | |
17297 | } | |
17298 | ||
47926f60 | 17299 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 17300 | \f |
252b5132 | 17301 | symbolS * |
7016a5d5 | 17302 | md_undefined_symbol (char *name) |
252b5132 | 17303 | { |
18dc2407 ILT |
17304 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
17305 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
17306 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
17307 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
17308 | { |
17309 | if (!GOT_symbol) | |
17310 | { | |
17311 | if (symbol_find (name)) | |
17312 | as_bad (_("GOT already in symbol table")); | |
17313 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 17314 | &zero_address_frag, 0); |
24eab124 AM |
17315 | }; |
17316 | return GOT_symbol; | |
17317 | } | |
252b5132 RH |
17318 | return 0; |
17319 | } | |
17320 | ||
071c5d81 | 17321 | #if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) |
252b5132 | 17322 | /* Round up a section size to the appropriate boundary. */ |
47926f60 | 17323 | |
252b5132 | 17324 | valueT |
071c5d81 | 17325 | md_section_align (segT segment, valueT size) |
252b5132 | 17326 | { |
4c63da97 AM |
17327 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) |
17328 | { | |
17329 | /* For a.out, force the section size to be aligned. If we don't do | |
17330 | this, BFD will align it for us, but it will not write out the | |
17331 | final bytes of the section. This may be a bug in BFD, but it is | |
17332 | easier to fix it here since that is how the other a.out targets | |
17333 | work. */ | |
17334 | int align; | |
17335 | ||
fd361982 | 17336 | align = bfd_section_alignment (segment); |
8d3842cd | 17337 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 17338 | } |
252b5132 RH |
17339 | |
17340 | return size; | |
17341 | } | |
071c5d81 | 17342 | #endif |
252b5132 RH |
17343 | |
17344 | /* On the i386, PC-relative offsets are relative to the start of the | |
17345 | next instruction. That is, the address of the offset, plus its | |
17346 | size, since the offset is always the last part of the insn. */ | |
17347 | ||
17348 | long | |
e3bb37b5 | 17349 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
17350 | { |
17351 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
17352 | } | |
17353 | ||
d4064aad | 17354 | #ifdef OBJ_AOUT |
252b5132 RH |
17355 | |
17356 | static void | |
e3bb37b5 | 17357 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17358 | { |
29b0f896 | 17359 | int temp; |
252b5132 RH |
17360 | |
17361 | temp = get_absolute_expression (); | |
17362 | subseg_set (bss_section, (subsegT) temp); | |
17363 | demand_empty_rest_of_line (); | |
17364 | } | |
17365 | ||
17366 | #endif | |
17367 | ||
e379e5f3 L |
17368 | /* Remember constant directive. */ |
17369 | ||
17370 | void | |
17371 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
17372 | { | |
b5482fe5 JB |
17373 | struct last_insn *last_insn |
17374 | = &seg_info(now_seg)->tc_segment_info_data.last_insn; | |
17375 | ||
ce69d081 | 17376 | if (bfd_section_flags (now_seg) & SEC_CODE) |
e379e5f3 | 17377 | { |
b5482fe5 JB |
17378 | last_insn->kind = last_insn_directive; |
17379 | last_insn->name = "constant directive"; | |
17380 | last_insn->file = as_where (&last_insn->line); | |
e379e5f3 L |
17381 | } |
17382 | } | |
17383 | ||
3abbafc2 | 17384 | int |
e3bb37b5 | 17385 | i386_validate_fix (fixS *fixp) |
252b5132 | 17386 | { |
e52a16f2 JB |
17387 | if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section) |
17388 | { | |
17389 | reloc_howto_type *howto; | |
17390 | ||
17391 | howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
17392 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17393 | _("invalid %s relocation against register"), | |
17394 | howto ? howto->name : "<unknown>"); | |
17395 | return 0; | |
17396 | } | |
17397 | ||
3abbafc2 JB |
17398 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
17399 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
17400 | || fixp->fx_r_type == BFD_RELOC_SIZE64) | |
17401 | return IS_ELF && fixp->fx_addsy | |
17402 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
17403 | || S_IS_EXTERNAL (fixp->fx_addsy)); | |
a533c8df | 17404 | |
5bc71c2a L |
17405 | /* BFD_RELOC_X86_64_GOTTPOFF: |
17406 | 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTTPOFF | |
17407 | 2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF | |
17408 | BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
17409 | 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC | |
17410 | BFD_RELOC_32_PCREL: | |
17411 | 1. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX | |
17412 | 2. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX | |
17413 | 3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX | |
17414 | 4. else -> BFD_RELOC_X86_64_GOTPCREL | |
17415 | */ | |
17416 | if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF) | |
a533c8df | 17417 | { |
5bc71c2a | 17418 | if (fixp->fx_tcbit) |
a533c8df | 17419 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTTPOFF; |
5bc71c2a L |
17420 | else if (fixp->fx_tcbit2) |
17421 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_6_GOTTPOFF; | |
a533c8df | 17422 | } |
5bc71c2a L |
17423 | else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
17424 | && fixp->fx_tcbit) | |
17425 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC; | |
3abbafc2 JB |
17426 | #endif |
17427 | ||
02a86693 | 17428 | if (fixp->fx_subsy) |
252b5132 | 17429 | { |
02a86693 | 17430 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 17431 | { |
02a86693 L |
17432 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
17433 | { | |
17434 | if (!object_64bit) | |
17435 | abort (); | |
17436 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
5bc71c2a L |
17437 | if (fixp->fx_tcbit) |
17438 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCRELX; | |
17439 | else if (fixp->fx_tcbit2) | |
17440 | fixp->fx_r_type = BFD_RELOC_X86_64_REX_GOTPCRELX; | |
17441 | else if (fixp->fx_tcbit3) | |
17442 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX; | |
02a86693 L |
17443 | else |
17444 | #endif | |
17445 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
17446 | } | |
d6ab8113 | 17447 | else |
02a86693 L |
17448 | { |
17449 | if (!object_64bit) | |
17450 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
17451 | else | |
17452 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
17453 | } | |
17454 | fixp->fx_subsy = 0; | |
23df1078 | 17455 | } |
252b5132 | 17456 | } |
02a86693 | 17457 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 17458 | else |
02a86693 | 17459 | { |
2585b7a5 L |
17460 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
17461 | to section. Since PLT32 relocation must be against symbols, | |
17462 | turn such PLT32 relocation into PC32 relocation. */ | |
17463 | if (fixp->fx_addsy | |
17464 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
17465 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
17466 | && symbol_section_p (fixp->fx_addsy)) | |
17467 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
17468 | if (!object_64bit) | |
17469 | { | |
17470 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
17471 | && fixp->fx_tcbit2) | |
17472 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
17473 | } | |
02a86693 L |
17474 | } |
17475 | #endif | |
3abbafc2 JB |
17476 | |
17477 | return 1; | |
252b5132 RH |
17478 | } |
17479 | ||
252b5132 | 17480 | arelent * |
7016a5d5 | 17481 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17482 | { |
17483 | arelent *rel; | |
17484 | bfd_reloc_code_real_type code; | |
17485 | ||
17486 | switch (fixp->fx_r_type) | |
17487 | { | |
8ce3d284 | 17488 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3abbafc2 JB |
17489 | symbolS *sym; |
17490 | ||
8fd4256d L |
17491 | case BFD_RELOC_SIZE32: |
17492 | case BFD_RELOC_SIZE64: | |
3abbafc2 JB |
17493 | if (fixp->fx_addsy |
17494 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)) | |
17495 | && (!fixp->fx_subsy | |
17496 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)))) | |
17497 | sym = fixp->fx_addsy; | |
17498 | else if (fixp->fx_subsy | |
17499 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)) | |
17500 | && (!fixp->fx_addsy | |
17501 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)))) | |
17502 | sym = fixp->fx_subsy; | |
17503 | else | |
17504 | sym = NULL; | |
17505 | if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym)) | |
8fd4256d L |
17506 | { |
17507 | /* Resolve size relocation against local symbol to size of | |
17508 | the symbol plus addend. */ | |
3abbafc2 | 17509 | valueT value = S_GET_SIZE (sym); |
44f87162 | 17510 | |
3abbafc2 JB |
17511 | if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) |
17512 | value = bfd_section_size (S_GET_SEGMENT (sym)); | |
17513 | if (sym == fixp->fx_subsy) | |
17514 | { | |
17515 | value = -value; | |
17516 | if (fixp->fx_addsy) | |
17517 | value += S_GET_VALUE (fixp->fx_addsy); | |
17518 | } | |
17519 | else if (fixp->fx_subsy) | |
17520 | value -= S_GET_VALUE (fixp->fx_subsy); | |
44f87162 | 17521 | value += fixp->fx_offset; |
8fd4256d | 17522 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
d965814f | 17523 | && object_64bit |
8fd4256d L |
17524 | && !fits_in_unsigned_long (value)) |
17525 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17526 | _("symbol size computation overflow")); | |
17527 | fixp->fx_addsy = NULL; | |
17528 | fixp->fx_subsy = NULL; | |
17529 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
17530 | return NULL; | |
17531 | } | |
3abbafc2 JB |
17532 | if (!fixp->fx_addsy || fixp->fx_subsy) |
17533 | { | |
17534 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17535 | "unsupported expression involving @size"); | |
17536 | return NULL; | |
17537 | } | |
8ce3d284 | 17538 | #endif |
1a0670f3 | 17539 | /* Fall through. */ |
8fd4256d | 17540 | |
3e73aa7c JH |
17541 | case BFD_RELOC_X86_64_PLT32: |
17542 | case BFD_RELOC_X86_64_GOT32: | |
17543 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
17544 | case BFD_RELOC_X86_64_GOTPCRELX: |
17545 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
3d5a60de | 17546 | case BFD_RELOC_X86_64_CODE_4_GOTPCRELX: |
252b5132 RH |
17547 | case BFD_RELOC_386_PLT32: |
17548 | case BFD_RELOC_386_GOT32: | |
02a86693 | 17549 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
17550 | case BFD_RELOC_386_GOTOFF: |
17551 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
17552 | case BFD_RELOC_386_TLS_GD: |
17553 | case BFD_RELOC_386_TLS_LDM: | |
17554 | case BFD_RELOC_386_TLS_LDO_32: | |
17555 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
17556 | case BFD_RELOC_386_TLS_IE: |
17557 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
17558 | case BFD_RELOC_386_TLS_LE_32: |
17559 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
17560 | case BFD_RELOC_386_TLS_GOTDESC: |
17561 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
17562 | case BFD_RELOC_X86_64_TLSGD: |
17563 | case BFD_RELOC_X86_64_TLSLD: | |
17564 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 17565 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 | 17566 | case BFD_RELOC_X86_64_GOTTPOFF: |
a533c8df | 17567 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
5bc71c2a | 17568 | case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: |
bffbf940 | 17569 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 JB |
17570 | case BFD_RELOC_X86_64_TPOFF64: |
17571 | case BFD_RELOC_X86_64_GOTOFF64: | |
17572 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
17573 | case BFD_RELOC_X86_64_GOT64: |
17574 | case BFD_RELOC_X86_64_GOTPCREL64: | |
17575 | case BFD_RELOC_X86_64_GOTPC64: | |
17576 | case BFD_RELOC_X86_64_GOTPLT64: | |
17577 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 | 17578 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 17579 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
67a4f2b7 | 17580 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
252b5132 RH |
17581 | case BFD_RELOC_RVA: |
17582 | case BFD_RELOC_VTABLE_ENTRY: | |
17583 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
17584 | #ifdef TE_PE |
17585 | case BFD_RELOC_32_SECREL: | |
145667f8 | 17586 | case BFD_RELOC_16_SECIDX: |
6482c264 | 17587 | #endif |
252b5132 RH |
17588 | code = fixp->fx_r_type; |
17589 | break; | |
dbbaec26 L |
17590 | case BFD_RELOC_X86_64_32S: |
17591 | if (!fixp->fx_pcrel) | |
17592 | { | |
17593 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
17594 | code = fixp->fx_r_type; | |
17595 | break; | |
17596 | } | |
1a0670f3 | 17597 | /* Fall through. */ |
252b5132 | 17598 | default: |
93382f6d | 17599 | if (fixp->fx_pcrel) |
252b5132 | 17600 | { |
93382f6d AM |
17601 | switch (fixp->fx_size) |
17602 | { | |
17603 | default: | |
b091f402 AM |
17604 | as_bad_where (fixp->fx_file, fixp->fx_line, |
17605 | _("can not do %d byte pc-relative relocation"), | |
17606 | fixp->fx_size); | |
93382f6d AM |
17607 | code = BFD_RELOC_32_PCREL; |
17608 | break; | |
17609 | case 1: code = BFD_RELOC_8_PCREL; break; | |
17610 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 17611 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
17612 | #ifdef BFD64 |
17613 | case 8: code = BFD_RELOC_64_PCREL; break; | |
17614 | #endif | |
93382f6d AM |
17615 | } |
17616 | } | |
17617 | else | |
17618 | { | |
17619 | switch (fixp->fx_size) | |
17620 | { | |
17621 | default: | |
b091f402 AM |
17622 | as_bad_where (fixp->fx_file, fixp->fx_line, |
17623 | _("can not do %d byte relocation"), | |
17624 | fixp->fx_size); | |
93382f6d AM |
17625 | code = BFD_RELOC_32; |
17626 | break; | |
17627 | case 1: code = BFD_RELOC_8; break; | |
17628 | case 2: code = BFD_RELOC_16; break; | |
17629 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 17630 | #ifdef BFD64 |
3e73aa7c | 17631 | case 8: code = BFD_RELOC_64; break; |
937149dd | 17632 | #endif |
93382f6d | 17633 | } |
252b5132 RH |
17634 | } |
17635 | break; | |
17636 | } | |
252b5132 | 17637 | |
d182319b JB |
17638 | if ((code == BFD_RELOC_32 |
17639 | || code == BFD_RELOC_32_PCREL | |
17640 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
17641 | && GOT_symbol |
17642 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 17643 | { |
4fa24527 | 17644 | if (!object_64bit) |
d6ab8113 JB |
17645 | code = BFD_RELOC_386_GOTPC; |
17646 | else | |
17647 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 17648 | } |
7b81dfbb AJ |
17649 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
17650 | && GOT_symbol | |
17651 | && fixp->fx_addsy == GOT_symbol) | |
17652 | { | |
17653 | code = BFD_RELOC_X86_64_GOTPC64; | |
17654 | } | |
252b5132 | 17655 | |
add39d23 TS |
17656 | rel = XNEW (arelent); |
17657 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 17658 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
17659 | |
17660 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 17661 | |
3e73aa7c JH |
17662 | if (!use_rela_relocations) |
17663 | { | |
17664 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
17665 | vtable entry to be used in the relocation's section offset. */ | |
17666 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17667 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
17668 | #if defined (OBJ_COFF) && defined (TE_PE) |
17669 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
17670 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
17671 | else | |
17672 | #endif | |
c6682705 | 17673 | rel->addend = 0; |
3e73aa7c JH |
17674 | } |
17675 | /* Use the rela in 64bit mode. */ | |
252b5132 | 17676 | else |
3e73aa7c | 17677 | { |
862be3fb L |
17678 | if (disallow_64bit_reloc) |
17679 | switch (code) | |
17680 | { | |
862be3fb L |
17681 | case BFD_RELOC_X86_64_DTPOFF64: |
17682 | case BFD_RELOC_X86_64_TPOFF64: | |
17683 | case BFD_RELOC_64_PCREL: | |
17684 | case BFD_RELOC_X86_64_GOTOFF64: | |
17685 | case BFD_RELOC_X86_64_GOT64: | |
17686 | case BFD_RELOC_X86_64_GOTPCREL64: | |
17687 | case BFD_RELOC_X86_64_GOTPC64: | |
17688 | case BFD_RELOC_X86_64_GOTPLT64: | |
17689 | case BFD_RELOC_X86_64_PLTOFF64: | |
17690 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17691 | _("cannot represent relocation type %s in x32 mode"), | |
17692 | bfd_get_reloc_code_name (code)); | |
17693 | break; | |
17694 | default: | |
17695 | break; | |
17696 | } | |
17697 | ||
062cd5e7 AS |
17698 | if (!fixp->fx_pcrel) |
17699 | rel->addend = fixp->fx_offset; | |
17700 | else | |
17701 | switch (code) | |
17702 | { | |
17703 | case BFD_RELOC_X86_64_PLT32: | |
17704 | case BFD_RELOC_X86_64_GOT32: | |
17705 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
17706 | case BFD_RELOC_X86_64_GOTPCRELX: |
17707 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
3d5a60de | 17708 | case BFD_RELOC_X86_64_CODE_4_GOTPCRELX: |
bffbf940 JJ |
17709 | case BFD_RELOC_X86_64_TLSGD: |
17710 | case BFD_RELOC_X86_64_TLSLD: | |
17711 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 17712 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
5bc71c2a | 17713 | case BFD_RELOC_X86_64_CODE_6_GOTTPOFF: |
67a4f2b7 | 17714 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 17715 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
67a4f2b7 | 17716 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
062cd5e7 AS |
17717 | rel->addend = fixp->fx_offset - fixp->fx_size; |
17718 | break; | |
17719 | default: | |
17720 | rel->addend = (section->vma | |
17721 | - fixp->fx_size | |
17722 | + fixp->fx_addnumber | |
17723 | + md_pcrel_from (fixp)); | |
17724 | break; | |
17725 | } | |
3e73aa7c JH |
17726 | } |
17727 | ||
252b5132 RH |
17728 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
17729 | if (rel->howto == NULL) | |
17730 | { | |
17731 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 17732 | _("cannot represent relocation type %s"), |
252b5132 RH |
17733 | bfd_get_reloc_code_name (code)); |
17734 | /* Set howto to a garbage value so that we can keep going. */ | |
17735 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 17736 | gas_assert (rel->howto != NULL); |
252b5132 RH |
17737 | } |
17738 | ||
17739 | return rel; | |
17740 | } | |
17741 | ||
ee86248c | 17742 | #include "tc-i386-intel.c" |
54cfded0 | 17743 | |
a60de03c JB |
17744 | void |
17745 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 17746 | { |
a60de03c JB |
17747 | int saved_naked_reg; |
17748 | char saved_register_dot; | |
54cfded0 | 17749 | |
a60de03c JB |
17750 | saved_naked_reg = allow_naked_reg; |
17751 | allow_naked_reg = 1; | |
17752 | saved_register_dot = register_chars['.']; | |
17753 | register_chars['.'] = '.'; | |
17754 | allow_pseudo_reg = 1; | |
17755 | expression_and_evaluate (exp); | |
17756 | allow_pseudo_reg = 0; | |
17757 | register_chars['.'] = saved_register_dot; | |
17758 | allow_naked_reg = saved_naked_reg; | |
17759 | ||
e96d56a1 | 17760 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 17761 | { |
066673f6 | 17762 | exp->X_op = O_illegal; |
a60de03c JB |
17763 | if ((addressT) exp->X_add_number < i386_regtab_size) |
17764 | { | |
a60de03c | 17765 | exp->X_add_number = i386_regtab[exp->X_add_number] |
fabb73d1 | 17766 | .dw2_regnum[object_64bit]; |
066673f6 JB |
17767 | if (exp->X_add_number != Dw2Inval) |
17768 | exp->X_op = O_constant; | |
a60de03c | 17769 | } |
54cfded0 | 17770 | } |
54cfded0 AM |
17771 | } |
17772 | ||
17773 | void | |
17774 | tc_x86_frame_initial_instructions (void) | |
17775 | { | |
fabb73d1 | 17776 | cfi_add_CFA_def_cfa (object_64bit ? REG_SP : 4, -x86_cie_data_alignment); |
61ff971f | 17777 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
54cfded0 | 17778 | } |
d2b2c203 | 17779 | |
d7921315 L |
17780 | int |
17781 | x86_dwarf2_addr_size (void) | |
17782 | { | |
17783 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
17784 | if (x86_elf_abi == X86_64_X32_ABI) | |
17785 | return 4; | |
17786 | #endif | |
17787 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
17788 | } | |
17789 | ||
071c5d81 JB |
17790 | #ifdef TE_PE |
17791 | void | |
17792 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
17793 | { | |
17794 | expressionS exp; | |
17795 | ||
17796 | exp.X_op = O_secrel; | |
17797 | exp.X_add_symbol = symbol; | |
17798 | exp.X_add_number = 0; | |
17799 | emit_expr (&exp, size); | |
17800 | } | |
17801 | #endif | |
17802 | ||
17803 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
d2b2c203 DJ |
17804 | int |
17805 | i386_elf_section_type (const char *str, size_t len) | |
17806 | { | |
17807 | if (flag_code == CODE_64BIT | |
17808 | && len == sizeof ("unwind") - 1 | |
d34049e8 | 17809 | && startswith (str, "unwind")) |
d2b2c203 DJ |
17810 | return SHT_X86_64_UNWIND; |
17811 | ||
17812 | return -1; | |
17813 | } | |
bb41ade5 | 17814 | |
da374e94 JB |
17815 | void |
17816 | i386_elf_section_change_hook (void) | |
17817 | { | |
17818 | struct i386_segment_info *info = &seg_info(now_seg)->tc_segment_info_data; | |
17819 | struct i386_segment_info *curr, *prev; | |
17820 | ||
17821 | if (info->subseg == now_subseg) | |
17822 | return; | |
17823 | ||
17824 | /* Find the (or make a) list entry to save state into. */ | |
17825 | for (prev = info; (curr = prev->next) != NULL; prev = curr) | |
17826 | if (curr->subseg == info->subseg) | |
17827 | break; | |
17828 | if (!curr) | |
17829 | { | |
fddee222 | 17830 | curr = notes_alloc (sizeof (*curr)); |
da374e94 JB |
17831 | curr->subseg = info->subseg; |
17832 | curr->next = NULL; | |
17833 | prev->next = curr; | |
17834 | } | |
17835 | curr->last_insn = info->last_insn; | |
17836 | ||
17837 | /* Find the list entry to load state from. */ | |
17838 | for (curr = info->next; curr; curr = curr->next) | |
17839 | if (curr->subseg == now_subseg) | |
17840 | break; | |
17841 | if (curr) | |
17842 | info->last_insn = curr->last_insn; | |
17843 | else | |
17844 | memset (&info->last_insn, 0, sizeof (info->last_insn)); | |
17845 | info->subseg = now_subseg; | |
17846 | } | |
17847 | ||
ad5fec3b EB |
17848 | #ifdef TE_SOLARIS |
17849 | void | |
17850 | i386_solaris_fix_up_eh_frame (segT sec) | |
17851 | { | |
17852 | if (flag_code == CODE_64BIT) | |
17853 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
17854 | } | |
17855 | #endif | |
17856 | ||
3b22753a L |
17857 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ |
17858 | ||
01e1a5bc | 17859 | bfd_vma |
6d4af3c2 | 17860 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
17861 | { |
17862 | if (flag_code == CODE_64BIT) | |
17863 | { | |
17864 | if (letter == 'l') | |
17865 | return SHF_X86_64_LARGE; | |
17866 | ||
8f3bae45 | 17867 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 17868 | } |
3b22753a | 17869 | else |
8f3bae45 | 17870 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
17871 | return -1; |
17872 | } | |
17873 | ||
3b22753a L |
17874 | static void |
17875 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
17876 | { | |
17877 | if (flag_code != CODE_64BIT) | |
17878 | { | |
17879 | s_comm_internal (0, elf_common_parse); | |
17880 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
17881 | } | |
17882 | else | |
17883 | { | |
17884 | static segT lbss_section; | |
17885 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
17886 | asection *saved_bss_section = bss_section; | |
17887 | ||
17888 | if (lbss_section == NULL) | |
17889 | { | |
17890 | flagword applicable; | |
17891 | segT seg = now_seg; | |
17892 | subsegT subseg = now_subseg; | |
17893 | ||
17894 | /* The .lbss section is for local .largecomm symbols. */ | |
17895 | lbss_section = subseg_new (".lbss", 0); | |
17896 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 17897 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
17898 | seg_info (lbss_section)->bss = 1; |
17899 | ||
17900 | subseg_set (seg, subseg); | |
17901 | } | |
17902 | ||
17903 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
17904 | bss_section = lbss_section; | |
17905 | ||
17906 | s_comm_internal (0, elf_common_parse); | |
17907 | ||
17908 | elf_com_section_ptr = saved_com_section_ptr; | |
17909 | bss_section = saved_bss_section; | |
17910 | } | |
17911 | } | |
17912 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |