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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
fd67aa11 | 2 | Copyright (C) 1989-2024 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
b52c4ee4 IB |
33 | #include "gen-sframe.h" |
34 | #include "sframe.h" | |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
5c139202 | 37 | #include "opcodes/i386-mnem.h" |
41fd2579 | 38 | #include <limits.h> |
41fd2579 | 39 | |
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
84 | |
85 | #define END_OF_INSN '\0' | |
86 | ||
05909f23 JB |
87 | #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } } |
88 | ||
79dec6b7 JB |
89 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
90 | #define commutative staticrounding | |
91 | ||
6305a203 L |
92 | /* |
93 | 'templates' is for grouping together 'template' structures for opcodes | |
94 | of the same name. This is only used for storing the insns in the grand | |
95 | ole hash table of insns. | |
96 | The templates themselves start at START and range up to (but not including) | |
97 | END. | |
98 | */ | |
99 | typedef struct | |
100 | { | |
d3ce72d0 NC |
101 | const insn_template *start; |
102 | const insn_template *end; | |
6305a203 L |
103 | } |
104 | templates; | |
105 | ||
106 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
107 | typedef struct | |
108 | { | |
109 | unsigned int regmem; /* codes register or memory operand */ | |
110 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
111 | unsigned int mode; /* how to interpret regmem & reg */ | |
112 | } | |
113 | modrm_byte; | |
114 | ||
115 | /* x86-64 extension prefix. */ | |
116 | typedef int rex_byte; | |
117 | ||
6305a203 L |
118 | /* 386 opcode byte to code indirect addressing. */ |
119 | typedef struct | |
120 | { | |
121 | unsigned base; | |
122 | unsigned index; | |
123 | unsigned scale; | |
124 | } | |
125 | sib_byte; | |
126 | ||
6305a203 L |
127 | /* x86 arch names, types and features */ |
128 | typedef struct | |
129 | { | |
130 | const char *name; /* arch name */ | |
6ceeed25 JB |
131 | unsigned int len:8; /* arch string length */ |
132 | bool skip:1; /* show_arch should skip this. */ | |
6305a203 | 133 | enum processor_type type; /* arch type */ |
4fc85f37 | 134 | enum { vsz_none, vsz_set, vsz_reset } vsz; /* vector size control */ |
ae89daec JB |
135 | i386_cpu_flags enable; /* cpu feature enable flags */ |
136 | i386_cpu_flags disable; /* cpu feature disable flags */ | |
6305a203 L |
137 | } |
138 | arch_entry; | |
139 | ||
78f12dd3 | 140 | static void update_code_flag (int, int); |
edd67638 | 141 | static void s_insn (int); |
e3bb37b5 L |
142 | static void set_code_flag (int); |
143 | static void set_16bit_gcc_code_flag (int); | |
144 | static void set_intel_syntax (int); | |
1efbbeb4 | 145 | static void set_intel_mnemonic (int); |
db51cc60 | 146 | static void set_allow_index_reg (int); |
7bab8ab5 | 147 | static void set_check (int); |
e3bb37b5 | 148 | static void set_cpu_arch (int); |
6482c264 | 149 | #ifdef TE_PE |
e3bb37b5 | 150 | static void pe_directive_secrel (int); |
145667f8 | 151 | static void pe_directive_secidx (int); |
6482c264 | 152 | #endif |
e3bb37b5 L |
153 | static void signed_cons (int); |
154 | static char *output_invalid (int c); | |
ee86248c JB |
155 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
156 | const char *); | |
157 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
158 | const char *); | |
a7619375 | 159 | static int i386_att_operand (char *); |
e3bb37b5 | 160 | static int i386_intel_operand (char *, int); |
ee86248c JB |
161 | static int i386_intel_simplify (expressionS *); |
162 | static int i386_intel_parse_name (const char *, expressionS *); | |
4f081312 | 163 | static const reg_entry *parse_register (const char *, char **); |
edd67638 | 164 | static const char *parse_insn (const char *, char *, bool); |
e3bb37b5 L |
165 | static char *parse_operands (char *, const char *); |
166 | static void swap_operands (void); | |
783c187b | 167 | static void swap_2_operands (unsigned int, unsigned int); |
ed719294 | 168 | static enum i386_flag_code i386_addressing_mode (void); |
e3bb37b5 | 169 | static void optimize_imm (void); |
0de704b9 | 170 | static bool optimize_disp (const insn_template *t); |
83b16ac6 | 171 | static const insn_template *match_template (char); |
e3bb37b5 L |
172 | static int check_string (void); |
173 | static int process_suffix (void); | |
174 | static int check_byte_reg (void); | |
175 | static int check_long_reg (void); | |
176 | static int check_qword_reg (void); | |
177 | static int check_word_reg (void); | |
178 | static int finalize_imm (void); | |
179 | static int process_operands (void); | |
5e042380 | 180 | static const reg_entry *build_modrm_byte (void); |
b5482fe5 | 181 | static void output_insn (const struct last_insn *); |
e3bb37b5 L |
182 | static void output_imm (fragS *, offsetT); |
183 | static void output_disp (fragS *, offsetT); | |
d4064aad | 184 | #ifdef OBJ_AOUT |
e3bb37b5 | 185 | static void s_bss (int); |
252b5132 | 186 | #endif |
17d4e2a2 L |
187 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
188 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
189 | |
190 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
191 | static unsigned int x86_isa_1_used; | |
192 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
193 | static unsigned int x86_feature_2_used; | |
194 | /* Generate x86 used ISA and feature properties. */ | |
195 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 196 | #endif |
252b5132 | 197 | |
a847613f | 198 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 199 | |
8a6fb3f9 JB |
200 | /* parse_register() returns this when a register alias cannot be used. */ |
201 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
202 | { Dw2Inval, Dw2Inval } }; | |
203 | ||
34684862 | 204 | static const reg_entry *reg_eax; |
5e042380 JB |
205 | static const reg_entry *reg_ds; |
206 | static const reg_entry *reg_es; | |
207 | static const reg_entry *reg_ss; | |
6288d05f | 208 | static const reg_entry *reg_st0; |
6225c532 JB |
209 | static const reg_entry *reg_k0; |
210 | ||
c0f3af97 L |
211 | /* VEX prefix. */ |
212 | typedef struct | |
213 | { | |
43234a1e L |
214 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
215 | unsigned char bytes[4]; | |
c0f3af97 L |
216 | unsigned int length; |
217 | /* Destination or source register specifier. */ | |
218 | const reg_entry *register_specifier; | |
219 | } vex_prefix; | |
220 | ||
252b5132 | 221 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 222 | i386_insn. */ |
252b5132 | 223 | |
520dc8e8 AM |
224 | union i386_op |
225 | { | |
226 | expressionS *disps; | |
227 | expressionS *imms; | |
228 | const reg_entry *regs; | |
229 | }; | |
230 | ||
a65babc9 L |
231 | enum i386_error |
232 | { | |
b4d65f2d | 233 | no_error, /* Must be first. */ |
86e026a4 | 234 | operand_size_mismatch, |
a65babc9 L |
235 | operand_type_mismatch, |
236 | register_type_mismatch, | |
237 | number_of_operands_mismatch, | |
238 | invalid_instruction_suffix, | |
239 | bad_imm4, | |
a65babc9 L |
240 | unsupported_with_intel_mnemonic, |
241 | unsupported_syntax, | |
80d61d8d | 242 | unsupported_EGPR_for_addressing, |
6c30d220 | 243 | unsupported, |
9db83a32 JB |
244 | unsupported_on_arch, |
245 | unsupported_64bit, | |
54294d73 JB |
246 | no_vex_encoding, |
247 | no_evex_encoding, | |
260cd341 | 248 | invalid_sib_address, |
6c30d220 | 249 | invalid_vsib_address, |
7bab8ab5 | 250 | invalid_vector_register_set, |
260cd341 | 251 | invalid_tmm_register_set, |
0cc78721 | 252 | invalid_dest_and_src_register_set, |
08a98d4c | 253 | invalid_dest_register_set, |
80d61d8d | 254 | invalid_pseudo_prefix, |
43234a1e L |
255 | unsupported_vector_index_register, |
256 | unsupported_broadcast, | |
43234a1e L |
257 | broadcast_needed, |
258 | unsupported_masking, | |
259 | mask_not_on_destination, | |
260 | no_default_mask, | |
261 | unsupported_rc_sae, | |
54294d73 | 262 | unsupported_vector_size, |
08a98d4c | 263 | unsupported_rsp_register, |
58bceb18 | 264 | internal_error, |
a65babc9 L |
265 | }; |
266 | ||
252b5132 RH |
267 | struct _i386_insn |
268 | { | |
47926f60 | 269 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 270 | insn_template tm; |
252b5132 | 271 | |
7d5e4556 L |
272 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
273 | or qword, if given. */ | |
252b5132 RH |
274 | char suffix; |
275 | ||
9a182d04 JB |
276 | /* OPCODE_LENGTH holds the number of base opcode bytes. */ |
277 | unsigned char opcode_length; | |
278 | ||
47926f60 | 279 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
280 | unsigned int operands; |
281 | ||
282 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
283 | of given register, displacement, memory operands and immediate | |
47926f60 | 284 | operands. */ |
252b5132 RH |
285 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
286 | ||
287 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 288 | use OP[i] for the corresponding operand. */ |
40fb9820 | 289 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 290 | |
520dc8e8 AM |
291 | /* Displacement expression, immediate expression, or register for each |
292 | operand. */ | |
293 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 294 | |
3e73aa7c JH |
295 | /* Flags for operands. */ |
296 | unsigned int flags[MAX_OPERANDS]; | |
297 | #define Operand_PCrel 1 | |
c48dadc9 | 298 | #define Operand_Mem 2 |
c032bc4f | 299 | #define Operand_Signed 4 /* .insn only */ |
3e73aa7c | 300 | |
252b5132 | 301 | /* Relocation type for operand */ |
f86103b7 | 302 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 303 | |
252b5132 RH |
304 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
305 | the base index byte below. */ | |
306 | const reg_entry *base_reg; | |
307 | const reg_entry *index_reg; | |
308 | unsigned int log2_scale_factor; | |
309 | ||
310 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 311 | explicit segment overrides are given. */ |
5e042380 | 312 | const reg_entry *seg[2]; |
252b5132 RH |
313 | |
314 | /* PREFIX holds all the given prefix opcodes (usually null). | |
315 | PREFIXES is the number of prefix opcodes. */ | |
316 | unsigned int prefixes; | |
317 | unsigned char prefix[MAX_PREFIXES]; | |
318 | ||
d0c2e3ec JB |
319 | /* .insn allows for reserved opcode spaces. */ |
320 | unsigned char insn_opcode_space; | |
321 | ||
c032bc4f JB |
322 | /* .insn also allows (requires) specifying immediate size. */ |
323 | unsigned char imm_bits[MAX_OPERANDS]; | |
324 | ||
50128d0c | 325 | /* Register is in low 3 bits of opcode. */ |
5b7c81bd | 326 | bool short_form; |
50128d0c | 327 | |
6f2f06be | 328 | /* The operand to a branch insn indicates an absolute branch. */ |
5b7c81bd | 329 | bool jumpabsolute; |
6f2f06be | 330 | |
a4d3acd2 JB |
331 | /* The operand to a branch insn indicates a far branch. */ |
332 | bool far_branch; | |
333 | ||
9373f275 L |
334 | /* There is a memory operand of (%dx) which should be only used |
335 | with input/output instructions. */ | |
336 | bool input_output_operand; | |
337 | ||
921eafea L |
338 | /* Extended states. */ |
339 | enum | |
340 | { | |
341 | /* Use MMX state. */ | |
342 | xstate_mmx = 1 << 0, | |
343 | /* Use XMM state. */ | |
344 | xstate_xmm = 1 << 1, | |
345 | /* Use YMM state. */ | |
346 | xstate_ymm = 1 << 2 | xstate_xmm, | |
347 | /* Use ZMM state. */ | |
348 | xstate_zmm = 1 << 3 | xstate_ymm, | |
349 | /* Use TMM state. */ | |
32930e4e L |
350 | xstate_tmm = 1 << 4, |
351 | /* Use MASK state. */ | |
352 | xstate_mask = 1 << 5 | |
921eafea | 353 | } xstate; |
260cd341 | 354 | |
e379e5f3 | 355 | /* Has GOTPC or TLS relocation. */ |
5b7c81bd | 356 | bool has_gotpc_tls_reloc; |
e379e5f3 | 357 | |
252b5132 | 358 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 359 | addressing modes of this insn are encoded. */ |
252b5132 | 360 | modrm_byte rm; |
3e73aa7c | 361 | rex_byte rex; |
43234a1e | 362 | rex_byte vrex; |
80d61d8d | 363 | rex_byte rex2; |
252b5132 | 364 | sib_byte sib; |
c0f3af97 | 365 | vex_prefix vex; |
b6169b20 | 366 | |
6225c532 JB |
367 | /* Masking attributes. |
368 | ||
369 | The struct describes masking, applied to OPERAND in the instruction. | |
370 | REG is a pointer to the corresponding mask register. ZEROING tells | |
371 | whether merging or zeroing mask is used. */ | |
372 | struct Mask_Operation | |
373 | { | |
374 | const reg_entry *reg; | |
375 | unsigned int zeroing; | |
376 | /* The operand where this operation is associated. */ | |
377 | unsigned int operand; | |
378 | } mask; | |
43234a1e L |
379 | |
380 | /* Rounding control and SAE attributes. */ | |
ca5312a2 JB |
381 | struct RC_Operation |
382 | { | |
383 | enum rc_type | |
384 | { | |
385 | rc_none = -1, | |
386 | rne, | |
387 | rd, | |
388 | ru, | |
389 | rz, | |
390 | saeonly | |
391 | } type; | |
7063667e JB |
392 | /* In Intel syntax the operand modifier form is supposed to be used, but |
393 | we continue to accept the immediate forms as well. */ | |
394 | bool modifier; | |
ca5312a2 | 395 | } rounding; |
43234a1e | 396 | |
5273a3cd JB |
397 | /* Broadcasting attributes. |
398 | ||
399 | The struct describes broadcasting, applied to OPERAND. TYPE is | |
400 | expresses the broadcast factor. */ | |
401 | struct Broadcast_Operation | |
402 | { | |
0cc78721 | 403 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */ |
5273a3cd JB |
404 | unsigned int type; |
405 | ||
406 | /* Index of broadcasted operand. */ | |
407 | unsigned int operand; | |
408 | ||
409 | /* Number of bytes to broadcast. */ | |
410 | unsigned int bytes; | |
411 | } broadcast; | |
43234a1e L |
412 | |
413 | /* Compressed disp8*N attribute. */ | |
414 | unsigned int memshift; | |
415 | ||
86fa6981 L |
416 | /* Prefer load or store in encoding. */ |
417 | enum | |
418 | { | |
419 | dir_encoding_default = 0, | |
420 | dir_encoding_load, | |
64c49ab3 JB |
421 | dir_encoding_store, |
422 | dir_encoding_swap | |
86fa6981 | 423 | } dir_encoding; |
891edac4 | 424 | |
41eb8e88 | 425 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
426 | enum |
427 | { | |
428 | disp_encoding_default = 0, | |
429 | disp_encoding_8bit, | |
41eb8e88 | 430 | disp_encoding_16bit, |
a501d77e L |
431 | disp_encoding_32bit |
432 | } disp_encoding; | |
f8a5c266 | 433 | |
6b6b6807 | 434 | /* Prefer the REX byte in encoding. */ |
5b7c81bd | 435 | bool rex_encoding; |
6b6b6807 | 436 | |
80d61d8d CL |
437 | /* Prefer the REX2 prefix in encoding. */ |
438 | bool rex2_encoding; | |
439 | ||
6177c84d CL |
440 | /* Need to use an Egpr capable encoding (REX2 or EVEX). */ |
441 | bool has_egpr; | |
442 | ||
b6f8c7c4 | 443 | /* Disable instruction size optimization. */ |
5b7c81bd | 444 | bool no_optimize; |
b6f8c7c4 | 445 | |
86fa6981 L |
446 | /* How to encode vector instructions. */ |
447 | enum | |
448 | { | |
449 | vex_encoding_default = 0, | |
42e04b36 | 450 | vex_encoding_vex, |
86fa6981 | 451 | vex_encoding_vex3, |
da4977e0 | 452 | vex_encoding_evex, |
a6f3add0 | 453 | vex_encoding_evex512, |
da4977e0 | 454 | vex_encoding_error |
86fa6981 L |
455 | } vec_encoding; |
456 | ||
d5de92cf L |
457 | /* REP prefix. */ |
458 | const char *rep_prefix; | |
459 | ||
165de32a L |
460 | /* HLE prefix. */ |
461 | const char *hle_prefix; | |
42164a71 | 462 | |
7e8b059b L |
463 | /* Have BND prefix. */ |
464 | const char *bnd_prefix; | |
465 | ||
04ef582a L |
466 | /* Have NOTRACK prefix. */ |
467 | const char *notrack_prefix; | |
468 | ||
891edac4 | 469 | /* Error message. */ |
a65babc9 | 470 | enum i386_error error; |
252b5132 RH |
471 | }; |
472 | ||
473 | typedef struct _i386_insn i386_insn; | |
474 | ||
43234a1e L |
475 | /* Link RC type with corresponding string, that'll be looked for in |
476 | asm. */ | |
477 | struct RC_name | |
478 | { | |
479 | enum rc_type type; | |
480 | const char *name; | |
481 | unsigned int len; | |
482 | }; | |
483 | ||
484 | static const struct RC_name RC_NamesTable[] = | |
485 | { | |
486 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
487 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
488 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
489 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
490 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
491 | }; | |
492 | ||
3bfea8ba L |
493 | /* To be indexed by segment register number. */ |
494 | static const unsigned char i386_seg_prefixes[] = { | |
495 | ES_PREFIX_OPCODE, | |
496 | CS_PREFIX_OPCODE, | |
497 | SS_PREFIX_OPCODE, | |
498 | DS_PREFIX_OPCODE, | |
499 | FS_PREFIX_OPCODE, | |
500 | GS_PREFIX_OPCODE | |
501 | }; | |
502 | ||
252b5132 RH |
503 | /* List of chars besides those in app.c:symbol_chars that can start an |
504 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 505 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 506 | #ifdef LEX_AT |
32137342 NC |
507 | "@" |
508 | #endif | |
509 | #ifdef LEX_QM | |
510 | "?" | |
252b5132 | 511 | #endif |
32137342 | 512 | ; |
252b5132 | 513 | |
b3983e5f JB |
514 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
515 | && !defined (TE_GNU) \ | |
516 | && !defined (TE_LINUX) \ | |
d85e70a3 | 517 | && !defined (TE_Haiku) \ |
b3983e5f JB |
518 | && !defined (TE_FreeBSD) \ |
519 | && !defined (TE_DragonFly) \ | |
520 | && !defined (TE_NetBSD)) | |
252b5132 | 521 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
522 | pre-processor is disabled, these aren't very useful. The option |
523 | --divide will remove '/' from this list. */ | |
524 | const char *i386_comment_chars = "#/"; | |
525 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 526 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 527 | |
b3b91714 AM |
528 | #else |
529 | const char *i386_comment_chars = "#"; | |
530 | #define PREFIX_SEPARATOR '/' | |
531 | #endif | |
532 | ||
252b5132 RH |
533 | /* This array holds the chars that only start a comment at the beginning of |
534 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
535 | .line and .file directives will appear in the pre-processed output. |
536 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 537 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
538 | #NO_APP at the beginning of its output. |
539 | Also note that comments started like this one will always work if | |
252b5132 | 540 | '/' isn't otherwise defined. */ |
b3b91714 | 541 | const char line_comment_chars[] = "#/"; |
252b5132 | 542 | |
63a0b638 | 543 | const char line_separator_chars[] = ";"; |
252b5132 | 544 | |
ce8a8b2f AM |
545 | /* Chars that can be used to separate mant from exp in floating point |
546 | nums. */ | |
252b5132 RH |
547 | const char EXP_CHARS[] = "eE"; |
548 | ||
ce8a8b2f AM |
549 | /* Chars that mean this number is a floating point constant |
550 | As in 0f12.456 | |
551 | or 0d1.2345e12. */ | |
de133cf9 | 552 | const char FLT_CHARS[] = "fFdDxXhHbB"; |
252b5132 | 553 | |
ce8a8b2f | 554 | /* Tables for lexical analysis. */ |
252b5132 RH |
555 | static char mnemonic_chars[256]; |
556 | static char register_chars[256]; | |
557 | static char operand_chars[256]; | |
252b5132 | 558 | |
ce8a8b2f | 559 | /* Lexical macros. */ |
252b5132 RH |
560 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
561 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
562 | #define is_space_char(x) ((x) == ' ') | |
252b5132 | 563 | |
d2b1a14d JB |
564 | /* All non-digit non-letter characters that may occur in an operand and |
565 | which aren't already in extra_symbol_chars[]. */ | |
566 | static const char operand_special_chars[] = "$+,)._~/<>|&^!=:@]"; | |
252b5132 RH |
567 | |
568 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
569 | effect this we maintain a stack of saved characters that we've smashed | |
570 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 571 | assembler instruction). */ |
252b5132 | 572 | static char save_stack[32]; |
ce8a8b2f | 573 | static char *save_stack_p; |
252b5132 RH |
574 | #define END_STRING_AND_SAVE(s) \ |
575 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
576 | #define RESTORE_END_STRING(s) \ | |
577 | do { *(s) = *--save_stack_p; } while (0) | |
578 | ||
47926f60 | 579 | /* The instruction we're assembling. */ |
252b5132 RH |
580 | static i386_insn i; |
581 | ||
582 | /* Possible templates for current insn. */ | |
d3b01414 | 583 | static templates current_templates; |
252b5132 | 584 | |
31b2323c L |
585 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
586 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
587 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 588 | |
47926f60 | 589 | /* Current operand we are working on. */ |
ee86248c | 590 | static int this_operand = -1; |
252b5132 | 591 | |
d0c2e3ec JB |
592 | /* Are we processing a .insn directive? */ |
593 | #define dot_insn() (i.tm.mnem_off == MN__insn) | |
594 | ||
ed719294 JB |
595 | enum i386_flag_code i386_flag_code; |
596 | #define flag_code i386_flag_code /* Permit to continue using original name. */ | |
4fa24527 | 597 | static unsigned int object_64bit; |
862be3fb | 598 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 599 | static int use_rela_relocations = 0; |
e379e5f3 L |
600 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
601 | static const char *tls_get_addr; | |
3e73aa7c | 602 | |
071c5d81 | 603 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7af8ed2d | 604 | |
351f65ca L |
605 | /* The ELF ABI to use. */ |
606 | enum x86_elf_abi | |
607 | { | |
608 | I386_ABI, | |
7f56bc95 L |
609 | X86_64_ABI, |
610 | X86_64_X32_ABI | |
351f65ca L |
611 | }; |
612 | ||
613 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 614 | #endif |
351f65ca | 615 | |
167ad85b TG |
616 | #if defined (TE_PE) || defined (TE_PEP) |
617 | /* Use big object file format. */ | |
618 | static int use_big_obj = 0; | |
619 | #endif | |
620 | ||
8dcea932 L |
621 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
622 | /* 1 if generating code for a shared library. */ | |
623 | static int shared = 0; | |
b52c4ee4 IB |
624 | |
625 | unsigned int x86_sframe_cfa_sp_reg; | |
3e3e792a | 626 | /* The other CFA base register for SFrame stack trace info. */ |
b52c4ee4 IB |
627 | unsigned int x86_sframe_cfa_fp_reg; |
628 | unsigned int x86_sframe_cfa_ra_reg; | |
629 | ||
8dcea932 L |
630 | #endif |
631 | ||
47926f60 KH |
632 | /* 1 for intel syntax, |
633 | 0 if att syntax. */ | |
634 | static int intel_syntax = 0; | |
252b5132 | 635 | |
4b5aaf5f L |
636 | static enum x86_64_isa |
637 | { | |
638 | amd64 = 1, /* AMD64 ISA. */ | |
639 | intel64 /* Intel64 ISA. */ | |
640 | } isa64; | |
e89c5eaa | 641 | |
1efbbeb4 L |
642 | /* 1 for intel mnemonic, |
643 | 0 if att mnemonic. */ | |
644 | static int intel_mnemonic = !SYSV386_COMPAT; | |
645 | ||
a60de03c JB |
646 | /* 1 if pseudo registers are permitted. */ |
647 | static int allow_pseudo_reg = 0; | |
648 | ||
47926f60 KH |
649 | /* 1 if register prefix % not required. */ |
650 | static int allow_naked_reg = 0; | |
252b5132 | 651 | |
33eaf5de | 652 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
653 | instructions supporting it, even if this prefix wasn't specified |
654 | explicitly. */ | |
655 | static int add_bnd_prefix = 0; | |
656 | ||
ba104c83 | 657 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
658 | static int allow_index_reg = 0; |
659 | ||
d022bddd IT |
660 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
661 | specified explicitly. */ | |
662 | static int omit_lock_prefix = 0; | |
663 | ||
e4e00185 AS |
664 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
665 | "lock addl $0, (%{re}sp)". */ | |
666 | static int avoid_fence = 0; | |
667 | ||
ae531041 L |
668 | /* 1 if lfence should be inserted after every load. */ |
669 | static int lfence_after_load = 0; | |
670 | ||
671 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
672 | static enum lfence_before_indirect_branch_kind | |
673 | { | |
674 | lfence_branch_none = 0, | |
675 | lfence_branch_register, | |
676 | lfence_branch_memory, | |
677 | lfence_branch_all | |
678 | } | |
679 | lfence_before_indirect_branch; | |
680 | ||
681 | /* Non-zero if lfence should be inserted before ret. */ | |
682 | static enum lfence_before_ret_kind | |
683 | { | |
684 | lfence_before_ret_none = 0, | |
685 | lfence_before_ret_not, | |
a09f656b | 686 | lfence_before_ret_or, |
687 | lfence_before_ret_shl | |
ae531041 L |
688 | } |
689 | lfence_before_ret; | |
690 | ||
0cb4071e L |
691 | /* 1 if the assembler should generate relax relocations. */ |
692 | ||
693 | static int generate_relax_relocations | |
694 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
695 | ||
7bab8ab5 | 696 | static enum check_kind |
daf50ae7 | 697 | { |
7bab8ab5 JB |
698 | check_none = 0, |
699 | check_warning, | |
700 | check_error | |
daf50ae7 | 701 | } |
7bab8ab5 | 702 | sse_check, operand_check = check_warning; |
daf50ae7 | 703 | |
e379e5f3 L |
704 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
705 | static int align_branch_power = 0; | |
706 | ||
707 | /* Types of branches to align. */ | |
708 | enum align_branch_kind | |
709 | { | |
710 | align_branch_none = 0, | |
711 | align_branch_jcc = 1, | |
712 | align_branch_fused = 2, | |
713 | align_branch_jmp = 3, | |
714 | align_branch_call = 4, | |
715 | align_branch_indirect = 5, | |
716 | align_branch_ret = 6 | |
717 | }; | |
718 | ||
719 | /* Type bits of branches to align. */ | |
720 | enum align_branch_bit | |
721 | { | |
722 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
723 | align_branch_fused_bit = 1 << align_branch_fused, | |
724 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
725 | align_branch_call_bit = 1 << align_branch_call, | |
726 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
727 | align_branch_ret_bit = 1 << align_branch_ret | |
728 | }; | |
729 | ||
730 | static unsigned int align_branch = (align_branch_jcc_bit | |
731 | | align_branch_fused_bit | |
732 | | align_branch_jmp_bit); | |
733 | ||
79d72f45 HL |
734 | /* Types of condition jump used by macro-fusion. */ |
735 | enum mf_jcc_kind | |
736 | { | |
737 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
738 | mf_jcc_jc, /* base opcode 0x72 */ | |
739 | mf_jcc_je, /* base opcode 0x74 */ | |
740 | mf_jcc_jna, /* base opcode 0x76 */ | |
741 | mf_jcc_js, /* base opcode 0x78 */ | |
742 | mf_jcc_jp, /* base opcode 0x7a */ | |
743 | mf_jcc_jl, /* base opcode 0x7c */ | |
744 | mf_jcc_jle, /* base opcode 0x7e */ | |
745 | }; | |
746 | ||
747 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
748 | enum mf_cmp_kind | |
749 | { | |
750 | mf_cmp_test_and, /* test/cmp */ | |
751 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
752 | mf_cmp_incdec /* inc/dec */ | |
753 | }; | |
754 | ||
e379e5f3 L |
755 | /* The maximum padding size for fused jcc. CMP like instruction can |
756 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
757 | prefixes. */ | |
758 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
759 | ||
760 | /* The maximum number of prefixes added for an instruction. */ | |
761 | static unsigned int align_branch_prefix_size = 5; | |
762 | ||
b6f8c7c4 L |
763 | /* Optimization: |
764 | 1. Clear the REX_W bit with register operand if possible. | |
765 | 2. Above plus use 128bit vector instruction to clear the full vector | |
766 | register. | |
767 | */ | |
768 | static int optimize = 0; | |
769 | ||
770 | /* Optimization: | |
771 | 1. Clear the REX_W bit with register operand if possible. | |
772 | 2. Above plus use 128bit vector instruction to clear the full vector | |
773 | register. | |
774 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
775 | "testb $imm7,%r8". | |
776 | */ | |
777 | static int optimize_for_space = 0; | |
778 | ||
2ca3ace5 L |
779 | /* Register prefix used for error message. */ |
780 | static const char *register_prefix = "%"; | |
781 | ||
47926f60 KH |
782 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
783 | leave, push, and pop instructions so that gcc has the same stack | |
784 | frame as in 32 bit mode. */ | |
785 | static char stackop_size = '\0'; | |
eecb386c | 786 | |
12b55ccc L |
787 | /* Non-zero to optimize code alignment. */ |
788 | int optimize_align_code = 1; | |
789 | ||
47926f60 KH |
790 | /* Non-zero to quieten some warnings. */ |
791 | static int quiet_warnings = 0; | |
a38cf1db | 792 | |
d59a54c2 JB |
793 | /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */ |
794 | static bool pre_386_16bit_warned; | |
795 | ||
47926f60 KH |
796 | /* CPU name. */ |
797 | static const char *cpu_arch_name = NULL; | |
6305a203 | 798 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 799 | |
47926f60 | 800 | /* CPU feature flags. */ |
cd75cd85 | 801 | i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
40fb9820 | 802 | |
3e624fa4 JB |
803 | /* ISA extensions available in 64-bit mode only. */ |
804 | static const i386_cpu_flags cpu_64_flags = CPU_ANY_64_FLAGS; | |
805 | ||
ccc9c027 L |
806 | /* If we have selected a cpu we are generating instructions for. */ |
807 | static int cpu_arch_tune_set = 0; | |
808 | ||
9103f4f4 | 809 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 810 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 | 811 | |
ccc9c027 | 812 | /* CPU instruction set architecture used. */ |
fbf3f584 | 813 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 814 | |
9103f4f4 | 815 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 816 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 817 | |
fddf5b5b AM |
818 | /* If set, conditional jumps are not automatically promoted to handle |
819 | larger than a byte offset. */ | |
f68697e8 | 820 | static bool no_cond_jump_promotion = false; |
fddf5b5b | 821 | |
5cc00775 JB |
822 | /* This will be set from an expression parser hook if there's any |
823 | applicable operator involved in an expression. */ | |
824 | static enum { | |
825 | expr_operator_none, | |
826 | expr_operator_present, | |
827 | expr_large_value, | |
828 | } expr_mode; | |
829 | ||
c0f3af97 L |
830 | /* Encode SSE instructions with VEX prefix. */ |
831 | static unsigned int sse2avx; | |
832 | ||
c8480b58 L |
833 | /* Encode aligned vector move as unaligned vector move. */ |
834 | static unsigned int use_unaligned_vector_move; | |
835 | ||
4fc85f37 | 836 | /* Maximum permitted vector size. */ |
fa88a361 HJ |
837 | #define VSZ128 0 |
838 | #define VSZ256 1 | |
839 | #define VSZ512 2 | |
4fc85f37 JB |
840 | #define VSZ_DEFAULT VSZ512 |
841 | static unsigned int vector_size = VSZ_DEFAULT; | |
842 | ||
539f890d L |
843 | /* Encode scalar AVX instructions with specific vector length. */ |
844 | static enum | |
845 | { | |
846 | vex128 = 0, | |
847 | vex256 | |
848 | } avxscalar; | |
849 | ||
03751133 L |
850 | /* Encode VEX WIG instructions with specific vex.w. */ |
851 | static enum | |
852 | { | |
853 | vexw0 = 0, | |
854 | vexw1 | |
855 | } vexwig; | |
856 | ||
43234a1e L |
857 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
858 | static enum | |
859 | { | |
860 | evexl128 = 0, | |
861 | evexl256, | |
862 | evexl512 | |
863 | } evexlig; | |
864 | ||
865 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
866 | static enum | |
867 | { | |
868 | evexw0 = 0, | |
869 | evexw1 | |
870 | } evexwig; | |
871 | ||
d3d3c6db IT |
872 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
873 | static enum rc_type evexrcig = rne; | |
874 | ||
29b0f896 | 875 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 876 | static symbolS *GOT_symbol; |
29b0f896 | 877 | |
a4447b93 RH |
878 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
879 | unsigned int x86_dwarf2_return_column; | |
880 | ||
881 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
882 | int x86_cie_data_alignment; | |
883 | ||
252b5132 | 884 | /* Interface to relax_segment. |
fddf5b5b AM |
885 | There are 3 major relax states for 386 jump insns because the |
886 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
887 | figuring out what sort of jump to choose to reach a given label. |
888 | ||
889 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
890 | branches which are handled by md_estimate_size_before_relax() and | |
891 | i386_generic_table_relax_frag(). */ | |
252b5132 | 892 | |
47926f60 | 893 | /* Types. */ |
93c2a809 AM |
894 | #define UNCOND_JUMP 0 |
895 | #define COND_JUMP 1 | |
896 | #define COND_JUMP86 2 | |
e379e5f3 L |
897 | #define BRANCH_PADDING 3 |
898 | #define BRANCH_PREFIX 4 | |
899 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 900 | |
47926f60 | 901 | /* Sizes. */ |
252b5132 RH |
902 | #define CODE16 1 |
903 | #define SMALL 0 | |
29b0f896 | 904 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 905 | #define BIG 2 |
29b0f896 | 906 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
907 | |
908 | #ifndef INLINE | |
909 | #ifdef __GNUC__ | |
910 | #define INLINE __inline__ | |
911 | #else | |
912 | #define INLINE | |
913 | #endif | |
914 | #endif | |
915 | ||
fddf5b5b AM |
916 | #define ENCODE_RELAX_STATE(type, size) \ |
917 | ((relax_substateT) (((type) << 2) | (size))) | |
918 | #define TYPE_FROM_RELAX_STATE(s) \ | |
919 | ((s) >> 2) | |
920 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
921 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
922 | |
923 | /* This table is used by relax_frag to promote short jumps to long | |
924 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
925 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
926 | don't allow a short jump in a 32 bit code segment to be promoted to | |
927 | a 16 bit offset jump because it's slower (requires data size | |
928 | prefix), and doesn't work, unless the destination is in the bottom | |
929 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
930 | ||
931 | const relax_typeS md_relax_table[] = | |
932 | { | |
24eab124 AM |
933 | /* The fields are: |
934 | 1) most positive reach of this state, | |
935 | 2) most negative reach of this state, | |
93c2a809 | 936 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 937 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 938 | |
fddf5b5b | 939 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
940 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
941 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
942 | /* dword jmp adds 4 bytes to frag: | |
943 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 944 | {0, 0, 4, 0}, |
93c2a809 AM |
945 | /* word jmp adds 2 byte2 to frag: |
946 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
947 | {0, 0, 2, 0}, |
948 | ||
93c2a809 AM |
949 | /* COND_JUMP states. */ |
950 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
951 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
952 | /* dword conditionals adds 5 bytes to frag: | |
953 | 1 extra opcode byte, 4 displacement bytes. */ | |
954 | {0, 0, 5, 0}, | |
fddf5b5b | 955 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
956 | 1 extra opcode byte, 2 displacement bytes. */ |
957 | {0, 0, 3, 0}, | |
958 | ||
959 | /* COND_JUMP86 states. */ | |
960 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
961 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
962 | /* dword conditionals adds 5 bytes to frag: | |
963 | 1 extra opcode byte, 4 displacement bytes. */ | |
964 | {0, 0, 5, 0}, | |
965 | /* word conditionals add 4 bytes to frag: | |
966 | 1 displacement byte and a 3 byte long branch insn. */ | |
967 | {0, 0, 4, 0} | |
252b5132 RH |
968 | }; |
969 | ||
6ceeed25 | 970 | #define ARCH(n, t, f, s) \ |
4fc85f37 | 971 | { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \ |
ae89daec JB |
972 | CPU_NONE_FLAGS } |
973 | #define SUBARCH(n, e, d, s) \ | |
4fc85f37 | 974 | { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \ |
ae89daec | 975 | CPU_ ## d ## _FLAGS } |
4fc85f37 JB |
976 | #define VECARCH(n, e, d, v) \ |
977 | { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \ | |
978 | CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS } | |
6ceeed25 | 979 | |
9103f4f4 L |
980 | static const arch_entry cpu_arch[] = |
981 | { | |
3ce2ebcf JB |
982 | /* Do not replace the first two entries - i386_target_format() and |
983 | set_cpu_arch() rely on them being there in this order. */ | |
6ceeed25 JB |
984 | ARCH (generic32, GENERIC32, GENERIC32, false), |
985 | ARCH (generic64, GENERIC64, GENERIC64, false), | |
986 | ARCH (i8086, UNKNOWN, NONE, false), | |
4d97c5c8 JB |
987 | ARCH (i186, UNKNOWN, 186, false), |
988 | ARCH (i286, UNKNOWN, 286, false), | |
989 | ARCH (i386, I386, 386, false), | |
990 | ARCH (i486, I486, 486, false), | |
991 | ARCH (i586, PENTIUM, 586, false), | |
4d97c5c8 | 992 | ARCH (pentium, PENTIUM, 586, false), |
c8be4b6f | 993 | ARCH (i686, I686, 686, false), |
6ceeed25 JB |
994 | ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false), |
995 | ARCH (pentiumii, PENTIUMPRO, P2, false), | |
996 | ARCH (pentiumiii, PENTIUMPRO, P3, false), | |
997 | ARCH (pentium4, PENTIUM4, P4, false), | |
998 | ARCH (prescott, NOCONA, CORE, false), | |
999 | ARCH (nocona, NOCONA, NOCONA, false), | |
1000 | ARCH (yonah, CORE, CORE, true), | |
1001 | ARCH (core, CORE, CORE, false), | |
1002 | ARCH (merom, CORE2, CORE2, true), | |
1003 | ARCH (core2, CORE2, CORE2, false), | |
1004 | ARCH (corei7, COREI7, COREI7, false), | |
1005 | ARCH (iamcu, IAMCU, IAMCU, false), | |
1006 | ARCH (k6, K6, K6, false), | |
1007 | ARCH (k6_2, K6, K6_2, false), | |
1008 | ARCH (athlon, ATHLON, ATHLON, false), | |
1009 | ARCH (sledgehammer, K8, K8, true), | |
1010 | ARCH (opteron, K8, K8, false), | |
1011 | ARCH (k8, K8, K8, false), | |
1012 | ARCH (amdfam10, AMDFAM10, AMDFAM10, false), | |
1013 | ARCH (bdver1, BD, BDVER1, false), | |
1014 | ARCH (bdver2, BD, BDVER2, false), | |
1015 | ARCH (bdver3, BD, BDVER3, false), | |
1016 | ARCH (bdver4, BD, BDVER4, false), | |
1017 | ARCH (znver1, ZNVER, ZNVER1, false), | |
1018 | ARCH (znver2, ZNVER, ZNVER2, false), | |
1019 | ARCH (znver3, ZNVER, ZNVER3, false), | |
b0e8fa7f | 1020 | ARCH (znver4, ZNVER, ZNVER4, false), |
6ceeed25 JB |
1021 | ARCH (btver1, BT, BTVER1, false), |
1022 | ARCH (btver2, BT, BTVER2, false), | |
1023 | ||
4d97c5c8 JB |
1024 | SUBARCH (8087, 8087, ANY_8087, false), |
1025 | SUBARCH (87, NONE, ANY_8087, false), /* Disable only! */ | |
ae89daec JB |
1026 | SUBARCH (287, 287, ANY_287, false), |
1027 | SUBARCH (387, 387, ANY_387, false), | |
1028 | SUBARCH (687, 687, ANY_687, false), | |
4d97c5c8 | 1029 | SUBARCH (cmov, CMOV, CMOV, false), |
88bd2203 | 1030 | SUBARCH (fxsr, FXSR, ANY_FXSR, false), |
ae89daec JB |
1031 | SUBARCH (mmx, MMX, ANY_MMX, false), |
1032 | SUBARCH (sse, SSE, ANY_SSE, false), | |
1033 | SUBARCH (sse2, SSE2, ANY_SSE2, false), | |
1034 | SUBARCH (sse3, SSE3, ANY_SSE3, false), | |
1035 | SUBARCH (sse4a, SSE4A, ANY_SSE4A, false), | |
1036 | SUBARCH (ssse3, SSSE3, ANY_SSSE3, false), | |
1037 | SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false), | |
1038 | SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false), | |
1039 | SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false), | |
4fc85f37 JB |
1040 | VECARCH (avx, AVX, ANY_AVX, reset), |
1041 | VECARCH (avx2, AVX2, ANY_AVX2, reset), | |
1042 | VECARCH (avx512f, AVX512F, ANY_AVX512F, reset), | |
1043 | VECARCH (avx512cd, AVX512CD, ANY_AVX512CD, reset), | |
1044 | VECARCH (avx512er, AVX512ER, ANY_AVX512ER, reset), | |
1045 | VECARCH (avx512pf, AVX512PF, ANY_AVX512PF, reset), | |
1046 | VECARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, reset), | |
1047 | VECARCH (avx512bw, AVX512BW, ANY_AVX512BW, reset), | |
1048 | VECARCH (avx512vl, AVX512VL, ANY_AVX512VL, reset), | |
cafa5ef7 | 1049 | SUBARCH (monitor, MONITOR, MONITOR, false), |
25626f79 JB |
1050 | SUBARCH (vmx, VMX, ANY_VMX, false), |
1051 | SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false), | |
ae89daec | 1052 | SUBARCH (smx, SMX, SMX, false), |
5091b9ee JB |
1053 | SUBARCH (xsave, XSAVE, ANY_XSAVE, false), |
1054 | SUBARCH (xsaveopt, XSAVEOPT, ANY_XSAVEOPT, false), | |
1055 | SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false), | |
1056 | SUBARCH (xsaves, XSAVES, ANY_XSAVES, false), | |
1057 | SUBARCH (aes, AES, ANY_AES, false), | |
d54678eb JB |
1058 | SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false), |
1059 | SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true), | |
ae89daec JB |
1060 | SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false), |
1061 | SUBARCH (rdrnd, RDRND, RDRND, false), | |
5091b9ee | 1062 | SUBARCH (f16c, F16C, ANY_F16C, false), |
ae89daec | 1063 | SUBARCH (bmi2, BMI2, BMI2, false), |
5091b9ee JB |
1064 | SUBARCH (fma, FMA, ANY_FMA, false), |
1065 | SUBARCH (fma4, FMA4, ANY_FMA4, false), | |
1066 | SUBARCH (xop, XOP, ANY_XOP, false), | |
1067 | SUBARCH (lwp, LWP, ANY_LWP, false), | |
ae89daec JB |
1068 | SUBARCH (movbe, MOVBE, MOVBE, false), |
1069 | SUBARCH (cx16, CX16, CX16, false), | |
c3bb24f5 | 1070 | SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false), |
25626f79 | 1071 | SUBARCH (ept, EPT, ANY_EPT, false), |
ae89daec JB |
1072 | SUBARCH (lzcnt, LZCNT, LZCNT, false), |
1073 | SUBARCH (popcnt, POPCNT, POPCNT, false), | |
1074 | SUBARCH (hle, HLE, HLE, false), | |
760ab3d0 JB |
1075 | SUBARCH (rtm, RTM, ANY_RTM, false), |
1076 | SUBARCH (tsx, TSX, TSX, false), | |
ae89daec JB |
1077 | SUBARCH (invpcid, INVPCID, INVPCID, false), |
1078 | SUBARCH (clflush, CLFLUSH, CLFLUSH, false), | |
1079 | SUBARCH (nop, NOP, NOP, false), | |
1080 | SUBARCH (syscall, SYSCALL, SYSCALL, false), | |
1081 | SUBARCH (rdtscp, RDTSCP, RDTSCP, false), | |
5091b9ee JB |
1082 | SUBARCH (3dnow, 3DNOW, ANY_3DNOW, false), |
1083 | SUBARCH (3dnowa, 3DNOWA, ANY_3DNOWA, false), | |
ae89daec | 1084 | SUBARCH (padlock, PADLOCK, PADLOCK, false), |
0919e770 JB |
1085 | SUBARCH (pacifica, SVME, ANY_SVME, true), |
1086 | SUBARCH (svme, SVME, ANY_SVME, false), | |
ae89daec JB |
1087 | SUBARCH (abm, ABM, ABM, false), |
1088 | SUBARCH (bmi, BMI, BMI, false), | |
1089 | SUBARCH (tbm, TBM, TBM, false), | |
1090 | SUBARCH (adx, ADX, ADX, false), | |
1091 | SUBARCH (rdseed, RDSEED, RDSEED, false), | |
1092 | SUBARCH (prfchw, PRFCHW, PRFCHW, false), | |
1093 | SUBARCH (smap, SMAP, SMAP, false), | |
5091b9ee JB |
1094 | SUBARCH (mpx, MPX, ANY_MPX, false), |
1095 | SUBARCH (sha, SHA, ANY_SHA, false), | |
ae89daec JB |
1096 | SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false), |
1097 | SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false), | |
1098 | SUBARCH (se1, SE1, SE1, false), | |
1099 | SUBARCH (clwb, CLWB, CLWB, false), | |
4fc85f37 JB |
1100 | VECARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, reset), |
1101 | VECARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, reset), | |
1102 | VECARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, reset), | |
1103 | VECARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, reset), | |
1104 | VECARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, reset), | |
1105 | VECARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, reset), | |
1106 | VECARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, reset), | |
1107 | VECARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, reset), | |
1108 | VECARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, reset), | |
ae89daec JB |
1109 | SUBARCH (clzero, CLZERO, CLZERO, false), |
1110 | SUBARCH (mwaitx, MWAITX, MWAITX, false), | |
5091b9ee | 1111 | SUBARCH (ospke, OSPKE, ANY_OSPKE, false), |
ae89daec JB |
1112 | SUBARCH (rdpid, RDPID, RDPID, false), |
1113 | SUBARCH (ptwrite, PTWRITE, PTWRITE, false), | |
4d97c5c8 JB |
1114 | SUBARCH (ibt, IBT, IBT, false), |
1115 | SUBARCH (shstk, SHSTK, SHSTK, false), | |
88bd2203 | 1116 | SUBARCH (gfni, GFNI, ANY_GFNI, false), |
4fc85f37 JB |
1117 | VECARCH (vaes, VAES, ANY_VAES, reset), |
1118 | VECARCH (vpclmulqdq, VPCLMULQDQ, ANY_VPCLMULQDQ, reset), | |
ae89daec JB |
1119 | SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false), |
1120 | SUBARCH (pconfig, PCONFIG, PCONFIG, false), | |
1121 | SUBARCH (waitpkg, WAITPKG, WAITPKG, false), | |
1122 | SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false), | |
1123 | SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false), | |
1124 | SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false), | |
5091b9ee | 1125 | SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false), |
d100d8c1 | 1126 | SUBARCH (amx_complex, AMX_COMPLEX, ANY_AMX_COMPLEX, false), |
ae89daec | 1127 | SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false), |
4d97c5c8 JB |
1128 | SUBARCH (movdiri, MOVDIRI, MOVDIRI, false), |
1129 | SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false), | |
4fc85f37 JB |
1130 | VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset), |
1131 | VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT, | |
1132 | ANY_AVX512_VP2INTERSECT, reset), | |
4d97c5c8 JB |
1133 | SUBARCH (tdx, TDX, TDX, false), |
1134 | SUBARCH (enqcmd, ENQCMD, ENQCMD, false), | |
1135 | SUBARCH (serialize, SERIALIZE, SERIALIZE, false), | |
ae89daec JB |
1136 | SUBARCH (rdpru, RDPRU, RDPRU, false), |
1137 | SUBARCH (mcommit, MCOMMIT, MCOMMIT, false), | |
0919e770 | 1138 | SUBARCH (sev_es, SEV_ES, ANY_SEV_ES, false), |
760ab3d0 | 1139 | SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false), |
88bd2203 JB |
1140 | SUBARCH (kl, KL, ANY_KL, false), |
1141 | SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false), | |
4d97c5c8 JB |
1142 | SUBARCH (uintr, UINTR, UINTR, false), |
1143 | SUBARCH (hreset, HRESET, HRESET, false), | |
4fc85f37 | 1144 | VECARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, reset), |
ef07be45 | 1145 | SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false), |
4fc85f37 JB |
1146 | VECARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, reset), |
1147 | VECARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, reset), | |
4d97c5c8 JB |
1148 | SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false), |
1149 | SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), | |
1150 | SUBARCH (msrlist, MSRLIST, MSRLIST, false), | |
4fc85f37 | 1151 | VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset), |
4d97c5c8 | 1152 | SUBARCH (rao_int, RAO_INT, RAO_INT, false), |
0919e770 | 1153 | SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false), |
c88ed92f ZJ |
1154 | SUBARCH (fred, FRED, ANY_FRED, false), |
1155 | SUBARCH (lkgs, LKGS, ANY_LKGS, false), | |
4fc85f37 JB |
1156 | VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset), |
1157 | VECARCH (sha512, SHA512, ANY_SHA512, reset), | |
1158 | VECARCH (sm3, SM3, ANY_SM3, reset), | |
1159 | VECARCH (sm4, SM4, ANY_SM4, reset), | |
b5c37946 | 1160 | SUBARCH (pbndkb, PBNDKB, PBNDKB, false), |
4fc85f37 | 1161 | VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), |
8170af78 | 1162 | SUBARCH (user_msr, USER_MSR, USER_MSR, false), |
80d61d8d | 1163 | SUBARCH (apx_f, APX_F, APX_F, false), |
293f5f65 L |
1164 | }; |
1165 | ||
6ceeed25 JB |
1166 | #undef SUBARCH |
1167 | #undef ARCH | |
1168 | ||
704209c0 | 1169 | #ifdef I386COFF |
a6c24e68 NC |
1170 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1171 | is allowed to be optional. */ | |
1172 | ||
1173 | static symbolS * | |
1174 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1175 | { | |
1176 | addressT align = 0; | |
1177 | ||
1178 | SKIP_WHITESPACE (); | |
1179 | ||
7ab9ffdd | 1180 | if (needs_align |
a6c24e68 NC |
1181 | && *input_line_pointer == ',') |
1182 | { | |
1183 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1184 | |
a6c24e68 NC |
1185 | if (align == (addressT) -1) |
1186 | return NULL; | |
1187 | } | |
1188 | else | |
1189 | { | |
1190 | if (size >= 8) | |
1191 | align = 3; | |
1192 | else if (size >= 4) | |
1193 | align = 2; | |
1194 | else if (size >= 2) | |
1195 | align = 1; | |
1196 | else | |
1197 | align = 0; | |
1198 | } | |
1199 | ||
1200 | bss_alloc (symbolP, size, align); | |
1201 | return symbolP; | |
1202 | } | |
1203 | ||
704209c0 | 1204 | static void |
a6c24e68 NC |
1205 | pe_lcomm (int needs_align) |
1206 | { | |
1207 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1208 | } | |
704209c0 | 1209 | #endif |
a6c24e68 | 1210 | |
29b0f896 AM |
1211 | const pseudo_typeS md_pseudo_table[] = |
1212 | { | |
1213 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1214 | {"align", s_align_bytes, 0}, | |
1215 | #else | |
1216 | {"align", s_align_ptwo, 0}, | |
1217 | #endif | |
1218 | {"arch", set_cpu_arch, 0}, | |
d4064aad | 1219 | #ifdef OBJ_AOUT |
29b0f896 | 1220 | {"bss", s_bss, 0}, |
d4064aad JB |
1221 | #endif |
1222 | #ifdef I386COFF | |
a6c24e68 | 1223 | {"lcomm", pe_lcomm, 1}, |
29b0f896 AM |
1224 | #endif |
1225 | {"ffloat", float_cons, 'f'}, | |
1226 | {"dfloat", float_cons, 'd'}, | |
1227 | {"tfloat", float_cons, 'x'}, | |
7d19d096 | 1228 | {"hfloat", float_cons, 'h'}, |
de133cf9 | 1229 | {"bfloat16", float_cons, 'b'}, |
29b0f896 | 1230 | {"value", cons, 2}, |
d182319b | 1231 | {"slong", signed_cons, 4}, |
edd67638 | 1232 | {"insn", s_insn, 0}, |
29b0f896 AM |
1233 | {"noopt", s_ignore, 0}, |
1234 | {"optim", s_ignore, 0}, | |
1235 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1236 | {"code16", set_code_flag, CODE_16BIT}, | |
1237 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1238 | #ifdef BFD64 |
29b0f896 | 1239 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1240 | #endif |
29b0f896 AM |
1241 | {"intel_syntax", set_intel_syntax, 1}, |
1242 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1243 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1244 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1245 | {"allow_index_reg", set_allow_index_reg, 1}, |
1246 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1247 | {"sse_check", set_check, 0}, |
1248 | {"operand_check", set_check, 1}, | |
3b22753a L |
1249 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1250 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1251 | #else |
68d20676 | 1252 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1253 | {"loc", dwarf2_directive_loc, 0}, |
1254 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1255 | #endif |
6482c264 NC |
1256 | #ifdef TE_PE |
1257 | {"secrel32", pe_directive_secrel, 0}, | |
145667f8 | 1258 | {"secidx", pe_directive_secidx, 0}, |
6482c264 | 1259 | #endif |
29b0f896 AM |
1260 | {0, 0, 0} |
1261 | }; | |
1262 | ||
1263 | /* For interface with expression (). */ | |
1264 | extern char *input_line_pointer; | |
1265 | ||
1266 | /* Hash table for instruction mnemonic lookup. */ | |
629310ab | 1267 | static htab_t op_hash; |
29b0f896 AM |
1268 | |
1269 | /* Hash table for register lookup. */ | |
629310ab | 1270 | static htab_t reg_hash; |
29b0f896 | 1271 | \f |
ce8a8b2f AM |
1272 | /* Various efficient no-op patterns for aligning code labels. |
1273 | Note: Don't try to assemble the instructions in the comments. | |
1274 | 0L and 0w are not legal. */ | |
62a02d25 L |
1275 | static const unsigned char f32_1[] = |
1276 | {0x90}; /* nop */ | |
1277 | static const unsigned char f32_2[] = | |
1278 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1279 | static const unsigned char f32_3[] = | |
1280 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
ad9f3230 JB |
1281 | #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */ |
1282 | static const unsigned char f32_5[] = | |
1283 | {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */ | |
62a02d25 L |
1284 | static const unsigned char f32_6[] = |
1285 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
ad9f3230 JB |
1286 | #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */ |
1287 | static const unsigned char f32_8[] = | |
1288 | {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */ | |
d164359d JB |
1289 | static const unsigned char f64_3[] = |
1290 | {0x48,0x89,0xf6}; /* mov %rsi,%rsi */ | |
1291 | static const unsigned char f64_4[] = | |
1292 | {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */ | |
1293 | #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */ | |
1294 | static const unsigned char f64_6[] = | |
1295 | {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */ | |
1296 | static const unsigned char f64_7[] = | |
1297 | {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */ | |
1298 | #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */ | |
1299 | static const unsigned char f64_9[] = | |
1300 | {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */ | |
5e0729b6 | 1301 | #define f16_2 (f64_3 + 1) /* mov %si,%si */ |
62a02d25 | 1302 | static const unsigned char f16_3[] = |
3ae729d5 | 1303 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
ad9f3230 JB |
1304 | #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */ |
1305 | static const unsigned char f16_5[] = | |
1306 | {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */ | |
3ae729d5 L |
1307 | static const unsigned char jump_disp8[] = |
1308 | {0xeb}; /* jmp disp8 */ | |
1309 | static const unsigned char jump32_disp32[] = | |
1310 | {0xe9}; /* jmp disp32 */ | |
1311 | static const unsigned char jump16_disp32[] = | |
1312 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1313 | /* 32-bit NOPs patterns. */ |
1314 | static const unsigned char *const f32_patt[] = { | |
ad9f3230 | 1315 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8 |
62a02d25 | 1316 | }; |
d164359d JB |
1317 | /* 64-bit NOPs patterns. */ |
1318 | static const unsigned char *const f64_patt[] = { | |
1319 | f32_1, f32_2, f64_3, f64_4, f64_5, f64_6, f64_7, f64_8, f64_9 | |
1320 | }; | |
62a02d25 L |
1321 | /* 16-bit NOPs patterns. */ |
1322 | static const unsigned char *const f16_patt[] = { | |
ad9f3230 | 1323 | f32_1, f16_2, f16_3, f16_4, f16_5 |
62a02d25 L |
1324 | }; |
1325 | /* nopl (%[re]ax) */ | |
1326 | static const unsigned char alt_3[] = | |
1327 | {0x0f,0x1f,0x00}; | |
1328 | /* nopl 0(%[re]ax) */ | |
1329 | static const unsigned char alt_4[] = | |
1330 | {0x0f,0x1f,0x40,0x00}; | |
1331 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1332 | #define alt_5 (alt_6 + 1) |
62a02d25 L |
1333 | /* nopw 0(%[re]ax,%[re]ax,1) */ |
1334 | static const unsigned char alt_6[] = | |
1335 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1336 | /* nopl 0L(%[re]ax) */ | |
1337 | static const unsigned char alt_7[] = | |
1338 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1339 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1340 | #define alt_8 (alt_9 + 1) |
62a02d25 L |
1341 | /* nopw 0L(%[re]ax,%[re]ax,1) */ |
1342 | static const unsigned char alt_9[] = | |
1343 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1344 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
ae7067fb | 1345 | #define alt_10 (alt_11 + 1) |
3ae729d5 L |
1346 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1347 | static const unsigned char alt_11[] = | |
1348 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1349 | /* 32-bit and 64-bit NOPs patterns. */ |
1350 | static const unsigned char *const alt_patt[] = { | |
1351 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1352 | alt_9, alt_10, alt_11 |
62a02d25 L |
1353 | }; |
1354 | ||
1355 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1356 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1357 | ||
1358 | static void | |
1359 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1360 | int count, int max_single_nop_size) | |
1361 | ||
1362 | { | |
3ae729d5 L |
1363 | /* Place the longer NOP first. */ |
1364 | int last; | |
1365 | int offset; | |
3076e594 NC |
1366 | const unsigned char *nops; |
1367 | ||
1368 | if (max_single_nop_size < 1) | |
1369 | { | |
1370 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1371 | max_single_nop_size); | |
1372 | return; | |
1373 | } | |
1374 | ||
1375 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1376 | last = count % max_single_nop_size; |
1377 | ||
1378 | count -= last; | |
1379 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1380 | memcpy (where + offset, nops, max_single_nop_size); | |
1381 | ||
1382 | if (last) | |
1383 | { | |
1384 | nops = patt[last - 1]; | |
ad9f3230 | 1385 | memcpy (where + offset, nops, last); |
3ae729d5 | 1386 | } |
62a02d25 L |
1387 | } |
1388 | ||
3ae729d5 L |
1389 | static INLINE int |
1390 | fits_in_imm7 (offsetT num) | |
1391 | { | |
1392 | return (num & 0x7f) == num; | |
1393 | } | |
1394 | ||
1395 | static INLINE int | |
1396 | fits_in_imm31 (offsetT num) | |
1397 | { | |
1398 | return (num & 0x7fffffff) == num; | |
1399 | } | |
62a02d25 L |
1400 | |
1401 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1402 | single NOP instruction LIMIT. */ | |
1403 | ||
1404 | void | |
3ae729d5 | 1405 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1406 | { |
3ae729d5 | 1407 | const unsigned char *const *patt = NULL; |
62a02d25 | 1408 | int max_single_nop_size; |
3ae729d5 L |
1409 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1410 | int max_number_of_nops; | |
62a02d25 | 1411 | |
3ae729d5 | 1412 | switch (fragP->fr_type) |
62a02d25 | 1413 | { |
3ae729d5 L |
1414 | case rs_fill_nop: |
1415 | case rs_align_code: | |
1416 | break; | |
e379e5f3 L |
1417 | case rs_machine_dependent: |
1418 | /* Allow NOP padding for jumps and calls. */ | |
1419 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1420 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1421 | break; | |
1422 | /* Fall through. */ | |
3ae729d5 | 1423 | default: |
62a02d25 L |
1424 | return; |
1425 | } | |
1426 | ||
ccc9c027 L |
1427 | /* We need to decide which NOP sequence to use for 32bit and |
1428 | 64bit. When -mtune= is used: | |
4eed87de | 1429 | |
c8be4b6f | 1430 | 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and |
76bc74dc | 1431 | PROCESSOR_GENERIC32, f32_patt will be used. |
80b8656c L |
1432 | 2. For the rest, alt_patt will be used. |
1433 | ||
1434 | When -mtune= isn't used, alt_patt will be used if | |
d164359d | 1435 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will |
76bc74dc | 1436 | be used. |
ccc9c027 L |
1437 | |
1438 | When -march= or .arch is used, we can't use anything beyond | |
1439 | cpu_arch_isa_flags. */ | |
1440 | ||
d12c7ab8 | 1441 | if (fragP->tc_frag_data.code == CODE_16BIT) |
ccc9c027 | 1442 | { |
3ae729d5 L |
1443 | patt = f16_patt; |
1444 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1445 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1446 | max_number_of_nops = 2; | |
252b5132 | 1447 | } |
33fef721 | 1448 | else |
ccc9c027 | 1449 | { |
d164359d | 1450 | patt = fragP->tc_frag_data.code == CODE_64BIT ? f64_patt : f32_patt; |
fbf3f584 | 1451 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 | 1452 | { |
cd75cd85 JB |
1453 | /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless |
1454 | explicitly disabled. */ | |
d12c7ab8 | 1455 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1456 | { |
1457 | case PROCESSOR_UNKNOWN: | |
1458 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 | 1459 | optimize with nops. */ |
9f314ead | 1460 | if (fragP->tc_frag_data.isanop) |
80b8656c | 1461 | patt = alt_patt; |
ccc9c027 | 1462 | break; |
c8be4b6f JB |
1463 | |
1464 | case PROCESSOR_PENTIUMPRO: | |
ccc9c027 L |
1465 | case PROCESSOR_PENTIUM4: |
1466 | case PROCESSOR_NOCONA: | |
ef05d495 | 1467 | case PROCESSOR_CORE: |
76bc74dc | 1468 | case PROCESSOR_CORE2: |
bd5295b2 | 1469 | case PROCESSOR_COREI7: |
76bc74dc | 1470 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1471 | case PROCESSOR_K6: |
1472 | case PROCESSOR_ATHLON: | |
1473 | case PROCESSOR_K8: | |
4eed87de | 1474 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1475 | case PROCESSOR_BD: |
029f3522 | 1476 | case PROCESSOR_ZNVER: |
7b458c12 | 1477 | case PROCESSOR_BT: |
cd75cd85 JB |
1478 | if (fragP->tc_frag_data.cpunop) |
1479 | patt = alt_patt; | |
ccc9c027 | 1480 | break; |
cd75cd85 | 1481 | |
76bc74dc | 1482 | case PROCESSOR_I386: |
ccc9c027 L |
1483 | case PROCESSOR_I486: |
1484 | case PROCESSOR_PENTIUM: | |
c8be4b6f | 1485 | case PROCESSOR_I686: |
81486035 | 1486 | case PROCESSOR_IAMCU: |
ccc9c027 | 1487 | case PROCESSOR_GENERIC32: |
ccc9c027 | 1488 | break; |
c368d2a8 JB |
1489 | case PROCESSOR_NONE: |
1490 | abort (); | |
4eed87de | 1491 | } |
ccc9c027 L |
1492 | } |
1493 | else | |
1494 | { | |
fbf3f584 | 1495 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1496 | { |
1497 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1498 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1499 | PROCESSOR_UNKNOWN. */ |
1500 | abort (); | |
1501 | break; | |
1502 | ||
cd75cd85 | 1503 | default: |
ccc9c027 | 1504 | /* We use cpu_arch_isa_flags to check if we CAN optimize |
22109423 | 1505 | with nops. */ |
9f314ead | 1506 | if (fragP->tc_frag_data.isanop) |
80b8656c | 1507 | patt = alt_patt; |
ccc9c027 | 1508 | break; |
cd75cd85 | 1509 | |
c368d2a8 JB |
1510 | case PROCESSOR_NONE: |
1511 | abort (); | |
4eed87de | 1512 | } |
ccc9c027 L |
1513 | } |
1514 | ||
d164359d | 1515 | if (patt != alt_patt) |
76bc74dc | 1516 | { |
d164359d JB |
1517 | max_single_nop_size = patt == f32_patt ? ARRAY_SIZE (f32_patt) |
1518 | : ARRAY_SIZE (f64_patt); | |
3ae729d5 L |
1519 | /* Limit number of NOPs to 2 for older processors. */ |
1520 | max_number_of_nops = 2; | |
76bc74dc L |
1521 | } |
1522 | else | |
1523 | { | |
3ae729d5 L |
1524 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1525 | /* Limit number of NOPs to 7 for newer processors. */ | |
1526 | max_number_of_nops = 7; | |
1527 | } | |
1528 | } | |
1529 | ||
1530 | if (limit == 0) | |
1531 | limit = max_single_nop_size; | |
1532 | ||
1533 | if (fragP->fr_type == rs_fill_nop) | |
1534 | { | |
1535 | /* Output NOPs for .nop directive. */ | |
1536 | if (limit > max_single_nop_size) | |
1537 | { | |
1538 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1539 | _("invalid single nop size: %d " | |
1540 | "(expect within [0, %d])"), | |
1541 | limit, max_single_nop_size); | |
1542 | return; | |
1543 | } | |
1544 | } | |
e379e5f3 | 1545 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1546 | fragP->fr_var = count; |
1547 | ||
0aa5d0c9 JB |
1548 | /* Emit a plain NOP first when the last thing we saw may not have been |
1549 | a proper instruction (e.g. a stand-alone prefix or .byte). */ | |
1550 | if (!fragP->tc_frag_data.last_insn_normal) | |
1551 | { | |
1552 | *where++ = 0x90; | |
1553 | --count; | |
1554 | } | |
1555 | ||
3ae729d5 L |
1556 | if ((count / max_single_nop_size) > max_number_of_nops) |
1557 | { | |
1558 | /* Generate jump over NOPs. */ | |
1559 | offsetT disp = count - 2; | |
1560 | if (fits_in_imm7 (disp)) | |
1561 | { | |
1562 | /* Use "jmp disp8" if possible. */ | |
1563 | count = disp; | |
1564 | where[0] = jump_disp8[0]; | |
1565 | where[1] = count; | |
1566 | where += 2; | |
1567 | } | |
1568 | else | |
1569 | { | |
1570 | unsigned int size_of_jump; | |
1571 | ||
1572 | if (flag_code == CODE_16BIT) | |
1573 | { | |
1574 | where[0] = jump16_disp32[0]; | |
1575 | where[1] = jump16_disp32[1]; | |
1576 | size_of_jump = 2; | |
1577 | } | |
1578 | else | |
1579 | { | |
1580 | where[0] = jump32_disp32[0]; | |
1581 | size_of_jump = 1; | |
1582 | } | |
1583 | ||
1584 | count -= size_of_jump + 4; | |
1585 | if (!fits_in_imm31 (count)) | |
1586 | { | |
1587 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1588 | _("jump over nop padding out of range")); | |
1589 | return; | |
1590 | } | |
1591 | ||
1592 | md_number_to_chars (where + size_of_jump, count, 4); | |
1593 | where += size_of_jump + 4; | |
76bc74dc | 1594 | } |
ccc9c027 | 1595 | } |
3ae729d5 L |
1596 | |
1597 | /* Generate multiple NOPs. */ | |
1598 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1599 | } |
1600 | ||
c6fb90c8 | 1601 | static INLINE int |
0dfbf9d7 | 1602 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1603 | { |
0dfbf9d7 | 1604 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1605 | { |
1606 | case 3: | |
0dfbf9d7 | 1607 | if (x->array[2]) |
c6fb90c8 | 1608 | return 0; |
1a0670f3 | 1609 | /* Fall through. */ |
c6fb90c8 | 1610 | case 2: |
0dfbf9d7 | 1611 | if (x->array[1]) |
c6fb90c8 | 1612 | return 0; |
1a0670f3 | 1613 | /* Fall through. */ |
c6fb90c8 | 1614 | case 1: |
0dfbf9d7 | 1615 | return !x->array[0]; |
c6fb90c8 L |
1616 | default: |
1617 | abort (); | |
1618 | } | |
40fb9820 L |
1619 | } |
1620 | ||
c6fb90c8 | 1621 | static INLINE void |
0dfbf9d7 | 1622 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1623 | { |
0dfbf9d7 | 1624 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1625 | { |
1626 | case 3: | |
0dfbf9d7 | 1627 | x->array[2] = v; |
1a0670f3 | 1628 | /* Fall through. */ |
c6fb90c8 | 1629 | case 2: |
0dfbf9d7 | 1630 | x->array[1] = v; |
1a0670f3 | 1631 | /* Fall through. */ |
c6fb90c8 | 1632 | case 1: |
0dfbf9d7 | 1633 | x->array[0] = v; |
1a0670f3 | 1634 | /* Fall through. */ |
c6fb90c8 L |
1635 | break; |
1636 | default: | |
1637 | abort (); | |
1638 | } | |
bab6aec1 JB |
1639 | |
1640 | x->bitfield.class = ClassNone; | |
75e5731b | 1641 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1642 | } |
40fb9820 | 1643 | |
c6fb90c8 | 1644 | static INLINE int |
0dfbf9d7 L |
1645 | operand_type_equal (const union i386_operand_type *x, |
1646 | const union i386_operand_type *y) | |
c6fb90c8 | 1647 | { |
0dfbf9d7 | 1648 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1649 | { |
1650 | case 3: | |
0dfbf9d7 | 1651 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1652 | return 0; |
1a0670f3 | 1653 | /* Fall through. */ |
c6fb90c8 | 1654 | case 2: |
0dfbf9d7 | 1655 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1656 | return 0; |
1a0670f3 | 1657 | /* Fall through. */ |
c6fb90c8 | 1658 | case 1: |
0dfbf9d7 | 1659 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1660 | break; |
1661 | default: | |
1662 | abort (); | |
1663 | } | |
1664 | } | |
40fb9820 | 1665 | |
734dfd1c | 1666 | static INLINE bool |
a5e91879 | 1667 | _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu) |
734dfd1c JB |
1668 | { |
1669 | switch (cpu) | |
1670 | { | |
a5e91879 JB |
1671 | case Cpu287: return a->bitfield.cpu287; |
1672 | case Cpu387: return a->bitfield.cpu387; | |
1673 | case Cpu3dnow: return a->bitfield.cpu3dnow; | |
1674 | case Cpu3dnowA: return a->bitfield.cpu3dnowa; | |
1675 | case CpuAVX: return a->bitfield.cpuavx; | |
1676 | case CpuHLE: return a->bitfield.cpuhle; | |
1677 | case CpuAVX512F: return a->bitfield.cpuavx512f; | |
1678 | case CpuAVX512VL: return a->bitfield.cpuavx512vl; | |
80d61d8d | 1679 | case CpuAPX_F: return a->bitfield.cpuapx_f; |
a5e91879 JB |
1680 | case Cpu64: return a->bitfield.cpu64; |
1681 | case CpuNo64: return a->bitfield.cpuno64; | |
734dfd1c JB |
1682 | default: |
1683 | gas_assert (cpu < CpuAttrEnums); | |
1684 | } | |
a5e91879 JB |
1685 | return a->bitfield.isa == cpu + 1u; |
1686 | } | |
1687 | ||
1688 | static INLINE bool | |
1689 | is_cpu (const insn_template *t, enum i386_cpu cpu) | |
1690 | { | |
1691 | return _is_cpu(&t->cpu, cpu); | |
1692 | } | |
1693 | ||
1694 | static INLINE bool | |
1695 | maybe_cpu (const insn_template *t, enum i386_cpu cpu) | |
1696 | { | |
1697 | return _is_cpu(&t->cpu_any, cpu); | |
734dfd1c JB |
1698 | } |
1699 | ||
1700 | static i386_cpu_flags cpu_flags_from_attr (i386_cpu_attr a) | |
1701 | { | |
1702 | const unsigned int bps = sizeof (a.array[0]) * CHAR_BIT; | |
1703 | i386_cpu_flags f = { .array[0] = 0 }; | |
1704 | ||
1705 | switch (ARRAY_SIZE(a.array)) | |
1706 | { | |
1707 | case 1: | |
1708 | f.array[CpuAttrEnums / bps] | |
1709 | |= (a.array[0] >> CpuIsaBits) << (CpuAttrEnums % bps); | |
1710 | if (CpuAttrEnums % bps > CpuIsaBits) | |
1711 | f.array[CpuAttrEnums / bps + 1] | |
1712 | = (a.array[0] >> CpuIsaBits) >> (bps - CpuAttrEnums % bps); | |
1713 | break; | |
1714 | default: | |
1715 | abort (); | |
1716 | } | |
1717 | ||
1718 | if (a.bitfield.isa) | |
1719 | f.array[(a.bitfield.isa - 1) / bps] |= 1u << ((a.bitfield.isa - 1) % bps); | |
1720 | ||
1721 | return f; | |
1722 | } | |
1723 | ||
0dfbf9d7 L |
1724 | static INLINE int |
1725 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1726 | { | |
1727 | switch (ARRAY_SIZE(x->array)) | |
1728 | { | |
75f8266a KL |
1729 | case 5: |
1730 | if (x->array[4]) | |
1731 | return 0; | |
1732 | /* Fall through. */ | |
53467f57 IT |
1733 | case 4: |
1734 | if (x->array[3]) | |
1735 | return 0; | |
1736 | /* Fall through. */ | |
0dfbf9d7 L |
1737 | case 3: |
1738 | if (x->array[2]) | |
1739 | return 0; | |
1a0670f3 | 1740 | /* Fall through. */ |
0dfbf9d7 L |
1741 | case 2: |
1742 | if (x->array[1]) | |
1743 | return 0; | |
1a0670f3 | 1744 | /* Fall through. */ |
0dfbf9d7 L |
1745 | case 1: |
1746 | return !x->array[0]; | |
1747 | default: | |
1748 | abort (); | |
1749 | } | |
1750 | } | |
1751 | ||
0dfbf9d7 L |
1752 | static INLINE int |
1753 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1754 | const union i386_cpu_flags *y) | |
1755 | { | |
1756 | switch (ARRAY_SIZE(x->array)) | |
1757 | { | |
75f8266a KL |
1758 | case 5: |
1759 | if (x->array[4] != y->array[4]) | |
1760 | return 0; | |
1761 | /* Fall through. */ | |
53467f57 IT |
1762 | case 4: |
1763 | if (x->array[3] != y->array[3]) | |
1764 | return 0; | |
1765 | /* Fall through. */ | |
0dfbf9d7 L |
1766 | case 3: |
1767 | if (x->array[2] != y->array[2]) | |
1768 | return 0; | |
1a0670f3 | 1769 | /* Fall through. */ |
0dfbf9d7 L |
1770 | case 2: |
1771 | if (x->array[1] != y->array[1]) | |
1772 | return 0; | |
1a0670f3 | 1773 | /* Fall through. */ |
0dfbf9d7 L |
1774 | case 1: |
1775 | return x->array[0] == y->array[0]; | |
1776 | break; | |
1777 | default: | |
1778 | abort (); | |
1779 | } | |
1780 | } | |
c6fb90c8 L |
1781 | |
1782 | static INLINE int | |
c0260ac6 | 1783 | cpu_flags_check_cpu64 (const insn_template *t) |
c6fb90c8 | 1784 | { |
c0260ac6 JB |
1785 | return flag_code == CODE_64BIT |
1786 | ? !t->cpu.bitfield.cpuno64 | |
1787 | : !t->cpu.bitfield.cpu64; | |
40fb9820 L |
1788 | } |
1789 | ||
c6fb90c8 L |
1790 | static INLINE i386_cpu_flags |
1791 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1792 | { |
c6fb90c8 L |
1793 | switch (ARRAY_SIZE (x.array)) |
1794 | { | |
75f8266a KL |
1795 | case 5: |
1796 | x.array [4] &= y.array [4]; | |
1797 | /* Fall through. */ | |
53467f57 IT |
1798 | case 4: |
1799 | x.array [3] &= y.array [3]; | |
1800 | /* Fall through. */ | |
c6fb90c8 L |
1801 | case 3: |
1802 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1803 | /* Fall through. */ |
c6fb90c8 L |
1804 | case 2: |
1805 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1806 | /* Fall through. */ |
c6fb90c8 L |
1807 | case 1: |
1808 | x.array [0] &= y.array [0]; | |
1809 | break; | |
1810 | default: | |
1811 | abort (); | |
1812 | } | |
1813 | return x; | |
1814 | } | |
40fb9820 | 1815 | |
c6fb90c8 L |
1816 | static INLINE i386_cpu_flags |
1817 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1818 | { |
c6fb90c8 | 1819 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1820 | { |
75f8266a KL |
1821 | case 5: |
1822 | x.array [4] |= y.array [4]; | |
1823 | /* Fall through. */ | |
53467f57 IT |
1824 | case 4: |
1825 | x.array [3] |= y.array [3]; | |
1826 | /* Fall through. */ | |
c6fb90c8 L |
1827 | case 3: |
1828 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1829 | /* Fall through. */ |
c6fb90c8 L |
1830 | case 2: |
1831 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1832 | /* Fall through. */ |
c6fb90c8 L |
1833 | case 1: |
1834 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1835 | break; |
1836 | default: | |
1837 | abort (); | |
1838 | } | |
40fb9820 L |
1839 | return x; |
1840 | } | |
1841 | ||
309d3373 JB |
1842 | static INLINE i386_cpu_flags |
1843 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1844 | { | |
1845 | switch (ARRAY_SIZE (x.array)) | |
1846 | { | |
75f8266a KL |
1847 | case 5: |
1848 | x.array [4] &= ~y.array [4]; | |
1849 | /* Fall through. */ | |
53467f57 IT |
1850 | case 4: |
1851 | x.array [3] &= ~y.array [3]; | |
1852 | /* Fall through. */ | |
309d3373 JB |
1853 | case 3: |
1854 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1855 | /* Fall through. */ |
309d3373 JB |
1856 | case 2: |
1857 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1858 | /* Fall through. */ |
309d3373 JB |
1859 | case 1: |
1860 | x.array [0] &= ~y.array [0]; | |
1861 | break; | |
1862 | default: | |
1863 | abort (); | |
1864 | } | |
1865 | return x; | |
1866 | } | |
1867 | ||
6c0946d0 JB |
1868 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1869 | ||
6177c84d | 1870 | static INLINE bool need_evex_encoding (const insn_template *t) |
a6f3add0 JB |
1871 | { |
1872 | return i.vec_encoding == vex_encoding_evex | |
1873 | || i.vec_encoding == vex_encoding_evex512 | |
6177c84d | 1874 | || (t->opcode_modifier.vex && i.has_egpr) |
a6f3add0 JB |
1875 | || i.mask.reg; |
1876 | } | |
1877 | ||
c0f3af97 L |
1878 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1879 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1880 | ||
c0f3af97 | 1881 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1882 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1883 | |
1884 | /* Return CPU flags match bits. */ | |
3629bb00 | 1885 | |
40fb9820 | 1886 | static int |
d3ce72d0 | 1887 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1888 | { |
a5e91879 JB |
1889 | i386_cpu_flags cpu, active, all = cpu_flags_from_attr (t->cpu); |
1890 | i386_cpu_flags any = cpu_flags_from_attr (t->cpu_any); | |
c0260ac6 | 1891 | int match = cpu_flags_check_cpu64 (t) ? CPU_FLAGS_64BIT_MATCH : 0; |
40fb9820 | 1892 | |
a5e91879 JB |
1893 | all.bitfield.cpu64 = 0; |
1894 | all.bitfield.cpuno64 = 0; | |
1895 | gas_assert (!any.bitfield.cpu64); | |
1896 | gas_assert (!any.bitfield.cpuno64); | |
40fb9820 | 1897 | |
a5e91879 | 1898 | if (cpu_flags_all_zero (&all) && cpu_flags_all_zero (&any)) |
c0f3af97 L |
1899 | { |
1900 | /* This instruction is available on all archs. */ | |
a5e91879 | 1901 | return match | CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1902 | } |
3e624fa4 | 1903 | |
a5e91879 | 1904 | /* This instruction is available only on some archs. */ |
3629bb00 | 1905 | |
a5e91879 JB |
1906 | /* Dual VEX/EVEX templates may need stripping of one of the flags. */ |
1907 | if (t->opcode_modifier.vex && t->opcode_modifier.evex) | |
1908 | { | |
1909 | /* Dual AVX/AVX512 templates need to retain AVX512* only if we already | |
1910 | know that EVEX encoding will be needed. */ | |
1911 | if ((any.bitfield.cpuavx || any.bitfield.cpuavx2 || any.bitfield.cpufma) | |
1912 | && (any.bitfield.cpuavx512f || any.bitfield.cpuavx512vl)) | |
a6f3add0 | 1913 | { |
6177c84d | 1914 | if (need_evex_encoding (t)) |
a6f3add0 | 1915 | { |
a5e91879 JB |
1916 | any.bitfield.cpuavx = 0; |
1917 | any.bitfield.cpuavx2 = 0; | |
1918 | any.bitfield.cpufma = 0; | |
1919 | } | |
6177c84d | 1920 | /* need_evex_encoding(t) isn't reliable before operands were |
a5e91879 JB |
1921 | parsed. */ |
1922 | else if (i.operands) | |
1923 | { | |
1924 | any.bitfield.cpuavx512f = 0; | |
1925 | any.bitfield.cpuavx512vl = 0; | |
a6f3add0 JB |
1926 | } |
1927 | } | |
a5e91879 | 1928 | } |
a6f3add0 | 1929 | |
a5e91879 JB |
1930 | if (flag_code != CODE_64BIT) |
1931 | active = cpu_flags_and_not (cpu_arch_flags, cpu_64_flags); | |
1932 | else | |
1933 | active = cpu_arch_flags; | |
1934 | cpu = cpu_flags_and (all, active); | |
1935 | if (cpu_flags_equal (&cpu, &all)) | |
1936 | { | |
22c36940 JB |
1937 | /* AVX and AVX2 present at the same time express an operand size |
1938 | dependency - strip AVX2 for the purposes here. The operand size | |
1939 | dependent check occurs in check_vecOperands(). */ | |
a5e91879 JB |
1940 | if (any.bitfield.cpuavx && any.bitfield.cpuavx2) |
1941 | any.bitfield.cpuavx2 = 0; | |
22c36940 | 1942 | |
a5e91879 JB |
1943 | cpu = cpu_flags_and (any, active); |
1944 | if (cpu_flags_all_zero (&any) || !cpu_flags_all_zero (&cpu)) | |
c0f3af97 | 1945 | { |
a5e91879 | 1946 | if (all.bitfield.cpuavx) |
f94f390e | 1947 | { |
a5e91879 JB |
1948 | /* We need to check SSE2AVX with AVX. */ |
1949 | if (!t->opcode_modifier.sse2avx | |
1950 | || (sse2avx && !i.prefix[DATA_PREFIX])) | |
929f69fa JB |
1951 | match |= CPU_FLAGS_ARCH_MATCH; |
1952 | } | |
a5ff0eb2 | 1953 | else |
db12e14e | 1954 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1955 | } |
3629bb00 | 1956 | } |
c0f3af97 | 1957 | return match; |
40fb9820 L |
1958 | } |
1959 | ||
c6fb90c8 L |
1960 | static INLINE i386_operand_type |
1961 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1962 | { |
bab6aec1 JB |
1963 | if (x.bitfield.class != y.bitfield.class) |
1964 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1965 | if (x.bitfield.instance != y.bitfield.instance) |
1966 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1967 | |
c6fb90c8 L |
1968 | switch (ARRAY_SIZE (x.array)) |
1969 | { | |
1970 | case 3: | |
1971 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1972 | /* Fall through. */ |
c6fb90c8 L |
1973 | case 2: |
1974 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1975 | /* Fall through. */ |
c6fb90c8 L |
1976 | case 1: |
1977 | x.array [0] &= y.array [0]; | |
1978 | break; | |
1979 | default: | |
1980 | abort (); | |
1981 | } | |
1982 | return x; | |
40fb9820 L |
1983 | } |
1984 | ||
73053c1f JB |
1985 | static INLINE i386_operand_type |
1986 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1987 | { | |
bab6aec1 | 1988 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1989 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1990 | |
73053c1f JB |
1991 | switch (ARRAY_SIZE (x.array)) |
1992 | { | |
1993 | case 3: | |
1994 | x.array [2] &= ~y.array [2]; | |
1995 | /* Fall through. */ | |
1996 | case 2: | |
1997 | x.array [1] &= ~y.array [1]; | |
1998 | /* Fall through. */ | |
1999 | case 1: | |
2000 | x.array [0] &= ~y.array [0]; | |
2001 | break; | |
2002 | default: | |
2003 | abort (); | |
2004 | } | |
2005 | return x; | |
2006 | } | |
2007 | ||
c6fb90c8 L |
2008 | static INLINE i386_operand_type |
2009 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 2010 | { |
bab6aec1 JB |
2011 | gas_assert (x.bitfield.class == ClassNone || |
2012 | y.bitfield.class == ClassNone || | |
2013 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
2014 | gas_assert (x.bitfield.instance == InstanceNone || |
2015 | y.bitfield.instance == InstanceNone || | |
2016 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 2017 | |
c6fb90c8 | 2018 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 2019 | { |
c6fb90c8 L |
2020 | case 3: |
2021 | x.array [2] |= y.array [2]; | |
1a0670f3 | 2022 | /* Fall through. */ |
c6fb90c8 L |
2023 | case 2: |
2024 | x.array [1] |= y.array [1]; | |
1a0670f3 | 2025 | /* Fall through. */ |
c6fb90c8 L |
2026 | case 1: |
2027 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2028 | break; |
2029 | default: | |
2030 | abort (); | |
2031 | } | |
c6fb90c8 L |
2032 | return x; |
2033 | } | |
40fb9820 | 2034 | |
c6fb90c8 L |
2035 | static INLINE i386_operand_type |
2036 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2037 | { | |
bab6aec1 | 2038 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2039 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2040 | |
c6fb90c8 L |
2041 | switch (ARRAY_SIZE (x.array)) |
2042 | { | |
2043 | case 3: | |
2044 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2045 | /* Fall through. */ |
c6fb90c8 L |
2046 | case 2: |
2047 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2048 | /* Fall through. */ |
c6fb90c8 L |
2049 | case 1: |
2050 | x.array [0] ^= y.array [0]; | |
2051 | break; | |
2052 | default: | |
2053 | abort (); | |
2054 | } | |
40fb9820 L |
2055 | return x; |
2056 | } | |
2057 | ||
05909f23 JB |
2058 | static const i386_operand_type anydisp = { |
2059 | .bitfield = { .disp8 = 1, .disp16 = 1, .disp32 = 1, .disp64 = 1 } | |
2060 | }; | |
40fb9820 L |
2061 | |
2062 | enum operand_type | |
2063 | { | |
2064 | reg, | |
40fb9820 L |
2065 | imm, |
2066 | disp, | |
2067 | anymem | |
2068 | }; | |
2069 | ||
c6fb90c8 | 2070 | static INLINE int |
40fb9820 L |
2071 | operand_type_check (i386_operand_type t, enum operand_type c) |
2072 | { | |
2073 | switch (c) | |
2074 | { | |
2075 | case reg: | |
bab6aec1 | 2076 | return t.bitfield.class == Reg; |
40fb9820 | 2077 | |
40fb9820 L |
2078 | case imm: |
2079 | return (t.bitfield.imm8 | |
2080 | || t.bitfield.imm8s | |
2081 | || t.bitfield.imm16 | |
2082 | || t.bitfield.imm32 | |
2083 | || t.bitfield.imm32s | |
2084 | || t.bitfield.imm64); | |
2085 | ||
2086 | case disp: | |
2087 | return (t.bitfield.disp8 | |
2088 | || t.bitfield.disp16 | |
2089 | || t.bitfield.disp32 | |
40fb9820 L |
2090 | || t.bitfield.disp64); |
2091 | ||
2092 | case anymem: | |
2093 | return (t.bitfield.disp8 | |
2094 | || t.bitfield.disp16 | |
2095 | || t.bitfield.disp32 | |
40fb9820 L |
2096 | || t.bitfield.disp64 |
2097 | || t.bitfield.baseindex); | |
2098 | ||
2099 | default: | |
2100 | abort (); | |
2101 | } | |
2cfe26b6 AM |
2102 | |
2103 | return 0; | |
40fb9820 L |
2104 | } |
2105 | ||
7a54636a L |
2106 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2107 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2108 | |
2109 | static INLINE int | |
7a54636a L |
2110 | match_operand_size (const insn_template *t, unsigned int wanted, |
2111 | unsigned int given) | |
5c07affc | 2112 | { |
3ac21baa JB |
2113 | return !((i.types[given].bitfield.byte |
2114 | && !t->operand_types[wanted].bitfield.byte) | |
2115 | || (i.types[given].bitfield.word | |
2116 | && !t->operand_types[wanted].bitfield.word) | |
2117 | || (i.types[given].bitfield.dword | |
2118 | && !t->operand_types[wanted].bitfield.dword) | |
2119 | || (i.types[given].bitfield.qword | |
9db83a32 JB |
2120 | && (!t->operand_types[wanted].bitfield.qword |
2121 | /* Don't allow 64-bit (memory) operands outside of 64-bit | |
2122 | mode, when they're used where a 64-bit GPR could also | |
2123 | be used. Checking is needed for Intel Syntax only. */ | |
2124 | || (intel_syntax | |
2125 | && flag_code != CODE_64BIT | |
2126 | && (t->operand_types[wanted].bitfield.class == Reg | |
2127 | || t->operand_types[wanted].bitfield.class == Accum | |
2128 | || t->opcode_modifier.isstring)))) | |
3ac21baa JB |
2129 | || (i.types[given].bitfield.tbyte |
2130 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2131 | } |
2132 | ||
dd40ce22 L |
2133 | /* Return 1 if there is no conflict in SIMD register between operand |
2134 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2135 | |
2136 | static INLINE int | |
dd40ce22 L |
2137 | match_simd_size (const insn_template *t, unsigned int wanted, |
2138 | unsigned int given) | |
1b54b8d7 | 2139 | { |
3ac21baa JB |
2140 | return !((i.types[given].bitfield.xmmword |
2141 | && !t->operand_types[wanted].bitfield.xmmword) | |
2142 | || (i.types[given].bitfield.ymmword | |
2143 | && !t->operand_types[wanted].bitfield.ymmword) | |
2144 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2145 | && !t->operand_types[wanted].bitfield.zmmword) |
2146 | || (i.types[given].bitfield.tmmword | |
2147 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2148 | } |
2149 | ||
7a54636a L |
2150 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2151 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2152 | |
2153 | static INLINE int | |
dd40ce22 L |
2154 | match_mem_size (const insn_template *t, unsigned int wanted, |
2155 | unsigned int given) | |
5c07affc | 2156 | { |
7a54636a | 2157 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2158 | && !((i.types[given].bitfield.unspecified |
5273a3cd | 2159 | && !i.broadcast.type |
a5748e0d | 2160 | && !i.broadcast.bytes |
3ac21baa JB |
2161 | && !t->operand_types[wanted].bitfield.unspecified) |
2162 | || (i.types[given].bitfield.fword | |
2163 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2164 | /* For scalar opcode templates to allow register and memory |
2165 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2166 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2167 | down-conversion vpmov*. */ | |
3528c362 | 2168 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2169 | && t->operand_types[wanted].bitfield.byte |
2170 | + t->operand_types[wanted].bitfield.word | |
2171 | + t->operand_types[wanted].bitfield.dword | |
2172 | + t->operand_types[wanted].bitfield.qword | |
2173 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2174 | ? (i.types[given].bitfield.xmmword |
2175 | || i.types[given].bitfield.ymmword | |
2176 | || i.types[given].bitfield.zmmword) | |
2177 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2178 | } |
2179 | ||
3ac21baa JB |
2180 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2181 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2182 | is no size conflict on any operands for the template with operands reversed | |
2183 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2184 | |
3ac21baa JB |
2185 | #define MATCH_STRAIGHT 1 |
2186 | #define MATCH_REVERSE 2 | |
2187 | ||
2188 | static INLINE unsigned int | |
d3ce72d0 | 2189 | operand_size_match (const insn_template *t) |
5c07affc | 2190 | { |
3ac21baa | 2191 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2192 | |
0cfa3eb3 | 2193 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2194 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2195 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2196 | return match; |
2197 | ||
2198 | /* Check memory and accumulator operand size. */ | |
2199 | for (j = 0; j < i.operands; j++) | |
2200 | { | |
3528c362 JB |
2201 | if (i.types[j].bitfield.class != Reg |
2202 | && i.types[j].bitfield.class != RegSIMD | |
255571cd | 2203 | && t->opcode_modifier.operandconstraint == ANY_SIZE) |
5c07affc L |
2204 | continue; |
2205 | ||
bab6aec1 | 2206 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2207 | && !match_operand_size (t, j, j)) |
5c07affc L |
2208 | { |
2209 | match = 0; | |
2210 | break; | |
2211 | } | |
2212 | ||
3528c362 | 2213 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2214 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2215 | { |
2216 | match = 0; | |
2217 | break; | |
2218 | } | |
2219 | ||
75e5731b | 2220 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2221 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2222 | { |
2223 | match = 0; | |
2224 | break; | |
2225 | } | |
2226 | ||
c48dadc9 | 2227 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2228 | { |
2229 | match = 0; | |
2230 | break; | |
2231 | } | |
2232 | } | |
2233 | ||
3ac21baa | 2234 | if (!t->opcode_modifier.d) |
7b94647a | 2235 | return match; |
5c07affc L |
2236 | |
2237 | /* Check reverse. */ | |
aa180741 | 2238 | gas_assert (i.operands >= 2); |
5c07affc | 2239 | |
f5eb1d70 | 2240 | for (j = 0; j < i.operands; j++) |
5c07affc | 2241 | { |
f5eb1d70 JB |
2242 | unsigned int given = i.operands - j - 1; |
2243 | ||
aa180741 | 2244 | /* For FMA4 and XOP insns VEX.W controls just the first two |
3083f376 | 2245 | register operands. And APX_F insns just swap the two source operands, |
2246 | with the 3rd one being the destination. */ | |
2247 | if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP) | |
2248 | || is_cpu (t, CpuAPX_F)) | |
8bd915b7 JB |
2249 | given = j < 2 ? 1 - j : j; |
2250 | ||
bab6aec1 | 2251 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2252 | && !match_operand_size (t, j, given)) |
7b94647a | 2253 | return match; |
5c07affc | 2254 | |
3528c362 | 2255 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2256 | && !match_simd_size (t, j, given)) |
7b94647a | 2257 | return match; |
dbbc8b7e | 2258 | |
75e5731b | 2259 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2260 | && (!match_operand_size (t, j, given) |
2261 | || !match_simd_size (t, j, given))) | |
7b94647a | 2262 | return match; |
dbbc8b7e | 2263 | |
f5eb1d70 | 2264 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
7b94647a | 2265 | return match; |
5c07affc L |
2266 | } |
2267 | ||
3ac21baa | 2268 | return match | MATCH_REVERSE; |
5c07affc L |
2269 | } |
2270 | ||
c6fb90c8 | 2271 | static INLINE int |
40fb9820 L |
2272 | operand_type_match (i386_operand_type overlap, |
2273 | i386_operand_type given) | |
2274 | { | |
2275 | i386_operand_type temp = overlap; | |
2276 | ||
7d5e4556 | 2277 | temp.bitfield.unspecified = 0; |
5c07affc L |
2278 | temp.bitfield.byte = 0; |
2279 | temp.bitfield.word = 0; | |
2280 | temp.bitfield.dword = 0; | |
2281 | temp.bitfield.fword = 0; | |
2282 | temp.bitfield.qword = 0; | |
2283 | temp.bitfield.tbyte = 0; | |
2284 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2285 | temp.bitfield.ymmword = 0; |
43234a1e | 2286 | temp.bitfield.zmmword = 0; |
260cd341 | 2287 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2288 | if (operand_type_all_zero (&temp)) |
891edac4 | 2289 | goto mismatch; |
40fb9820 | 2290 | |
6f2f06be | 2291 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2292 | return 1; |
2293 | ||
dc1e8a47 | 2294 | mismatch: |
a65babc9 | 2295 | i.error = operand_type_mismatch; |
891edac4 | 2296 | return 0; |
40fb9820 L |
2297 | } |
2298 | ||
7d5e4556 | 2299 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2300 | unless the expected operand type register overlap is null. |
8ee52bcf | 2301 | Intel syntax sized memory operands are also checked here. */ |
40fb9820 | 2302 | |
c6fb90c8 | 2303 | static INLINE int |
dc821c5f | 2304 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2305 | i386_operand_type t0, |
40fb9820 L |
2306 | i386_operand_type g1, |
2307 | i386_operand_type t1) | |
2308 | { | |
bab6aec1 | 2309 | if (g0.bitfield.class != Reg |
3528c362 | 2310 | && g0.bitfield.class != RegSIMD |
8ee52bcf JB |
2311 | && (g0.bitfield.unspecified |
2312 | || !operand_type_check (g0, anymem))) | |
40fb9820 L |
2313 | return 1; |
2314 | ||
bab6aec1 | 2315 | if (g1.bitfield.class != Reg |
3528c362 | 2316 | && g1.bitfield.class != RegSIMD |
8ee52bcf JB |
2317 | && (g1.bitfield.unspecified |
2318 | || !operand_type_check (g1, anymem))) | |
40fb9820 L |
2319 | return 1; |
2320 | ||
dc821c5f JB |
2321 | if (g0.bitfield.byte == g1.bitfield.byte |
2322 | && g0.bitfield.word == g1.bitfield.word | |
2323 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2324 | && g0.bitfield.qword == g1.bitfield.qword |
2325 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2326 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2327 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2328 | return 1; |
2329 | ||
c4d09633 JB |
2330 | /* If expectations overlap in no more than a single size, all is fine. */ |
2331 | g0 = operand_type_and (t0, t1); | |
2332 | if (g0.bitfield.byte | |
2333 | + g0.bitfield.word | |
2334 | + g0.bitfield.dword | |
2335 | + g0.bitfield.qword | |
2336 | + g0.bitfield.xmmword | |
2337 | + g0.bitfield.ymmword | |
2338 | + g0.bitfield.zmmword <= 1) | |
891edac4 L |
2339 | return 1; |
2340 | ||
a65babc9 | 2341 | i.error = register_type_mismatch; |
891edac4 L |
2342 | |
2343 | return 0; | |
40fb9820 L |
2344 | } |
2345 | ||
4c692bc7 JB |
2346 | static INLINE unsigned int |
2347 | register_number (const reg_entry *r) | |
2348 | { | |
2349 | unsigned int nr = r->reg_num; | |
2350 | ||
2351 | if (r->reg_flags & RegRex) | |
2352 | nr += 8; | |
2353 | ||
80d61d8d | 2354 | if (r->reg_flags & (RegVRex | RegRex2)) |
200cbe0f L |
2355 | nr += 16; |
2356 | ||
4c692bc7 JB |
2357 | return nr; |
2358 | } | |
2359 | ||
252b5132 | 2360 | static INLINE unsigned int |
40fb9820 | 2361 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2362 | { |
b5014f7a | 2363 | if (t.bitfield.disp8) |
40fb9820 L |
2364 | return 1; |
2365 | else if (t.bitfield.disp16 | |
a775efc8 | 2366 | || t.bitfield.disp32) |
40fb9820 L |
2367 | return 2; |
2368 | else | |
2369 | return 0; | |
252b5132 RH |
2370 | } |
2371 | ||
2372 | static INLINE int | |
65879393 | 2373 | fits_in_signed_byte (addressT num) |
252b5132 | 2374 | { |
65879393 | 2375 | return num + 0x80 <= 0xff; |
47926f60 | 2376 | } |
252b5132 RH |
2377 | |
2378 | static INLINE int | |
65879393 | 2379 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2380 | { |
65879393 | 2381 | return num <= 0xff; |
47926f60 | 2382 | } |
252b5132 RH |
2383 | |
2384 | static INLINE int | |
65879393 | 2385 | fits_in_unsigned_word (addressT num) |
252b5132 | 2386 | { |
65879393 | 2387 | return num <= 0xffff; |
47926f60 | 2388 | } |
252b5132 RH |
2389 | |
2390 | static INLINE int | |
65879393 | 2391 | fits_in_signed_word (addressT num) |
252b5132 | 2392 | { |
65879393 | 2393 | return num + 0x8000 <= 0xffff; |
47926f60 | 2394 | } |
2a962e6d | 2395 | |
3e73aa7c | 2396 | static INLINE int |
65879393 | 2397 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2398 | { |
2399 | #ifndef BFD64 | |
2400 | return 1; | |
2401 | #else | |
65879393 | 2402 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2403 | #endif |
2404 | } /* fits_in_signed_long() */ | |
2a962e6d | 2405 | |
3e73aa7c | 2406 | static INLINE int |
65879393 | 2407 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2408 | { |
2409 | #ifndef BFD64 | |
2410 | return 1; | |
2411 | #else | |
65879393 | 2412 | return num <= 0xffffffff; |
3e73aa7c JH |
2413 | #endif |
2414 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2415 | |
a442cac5 JB |
2416 | static INLINE valueT extend_to_32bit_address (addressT num) |
2417 | { | |
2418 | #ifdef BFD64 | |
2419 | if (fits_in_unsigned_long(num)) | |
2420 | return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
2421 | ||
2422 | if (!fits_in_signed_long (num)) | |
2423 | return num & 0xffffffff; | |
2424 | #endif | |
2425 | ||
2426 | return num; | |
2427 | } | |
2428 | ||
43234a1e | 2429 | static INLINE int |
b5014f7a | 2430 | fits_in_disp8 (offsetT num) |
43234a1e L |
2431 | { |
2432 | int shift = i.memshift; | |
2433 | unsigned int mask; | |
2434 | ||
2435 | if (shift == -1) | |
2436 | abort (); | |
2437 | ||
2438 | mask = (1 << shift) - 1; | |
2439 | ||
2440 | /* Return 0 if NUM isn't properly aligned. */ | |
2441 | if ((num & mask)) | |
2442 | return 0; | |
2443 | ||
2444 | /* Check if NUM will fit in 8bit after shift. */ | |
2445 | return fits_in_signed_byte (num >> shift); | |
2446 | } | |
2447 | ||
a683cc34 SP |
2448 | static INLINE int |
2449 | fits_in_imm4 (offsetT num) | |
2450 | { | |
0ff3b7d0 JB |
2451 | /* Despite the name, check for imm3 if we're dealing with EVEX. */ |
2452 | return (num & (i.vec_encoding != vex_encoding_evex ? 0xf : 7)) == num; | |
a683cc34 SP |
2453 | } |
2454 | ||
40fb9820 | 2455 | static i386_operand_type |
e3bb37b5 | 2456 | smallest_imm_type (offsetT num) |
252b5132 | 2457 | { |
40fb9820 | 2458 | i386_operand_type t; |
7ab9ffdd | 2459 | |
0dfbf9d7 | 2460 | operand_type_set (&t, 0); |
40fb9820 L |
2461 | t.bitfield.imm64 = 1; |
2462 | ||
2463 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2464 | { |
2465 | /* This code is disabled on the 486 because all the Imm1 forms | |
2466 | in the opcode table are slower on the i486. They're the | |
2467 | versions with the implicitly specified single-position | |
2468 | displacement, which has another syntax if you really want to | |
2469 | use that form. */ | |
40fb9820 L |
2470 | t.bitfield.imm1 = 1; |
2471 | t.bitfield.imm8 = 1; | |
2472 | t.bitfield.imm8s = 1; | |
2473 | t.bitfield.imm16 = 1; | |
2474 | t.bitfield.imm32 = 1; | |
2475 | t.bitfield.imm32s = 1; | |
2476 | } | |
2477 | else if (fits_in_signed_byte (num)) | |
2478 | { | |
c34d1cc9 JB |
2479 | if (fits_in_unsigned_byte (num)) |
2480 | t.bitfield.imm8 = 1; | |
40fb9820 L |
2481 | t.bitfield.imm8s = 1; |
2482 | t.bitfield.imm16 = 1; | |
8170af78 HL |
2483 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2484 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2485 | t.bitfield.imm32s = 1; |
2486 | } | |
2487 | else if (fits_in_unsigned_byte (num)) | |
2488 | { | |
2489 | t.bitfield.imm8 = 1; | |
2490 | t.bitfield.imm16 = 1; | |
2491 | t.bitfield.imm32 = 1; | |
2492 | t.bitfield.imm32s = 1; | |
2493 | } | |
2494 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2495 | { | |
2496 | t.bitfield.imm16 = 1; | |
8170af78 HL |
2497 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2498 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2499 | t.bitfield.imm32s = 1; |
2500 | } | |
2501 | else if (fits_in_signed_long (num)) | |
2502 | { | |
8170af78 HL |
2503 | if (flag_code != CODE_64BIT || fits_in_unsigned_long (num)) |
2504 | t.bitfield.imm32 = 1; | |
40fb9820 L |
2505 | t.bitfield.imm32s = 1; |
2506 | } | |
2507 | else if (fits_in_unsigned_long (num)) | |
2508 | t.bitfield.imm32 = 1; | |
2509 | ||
2510 | return t; | |
47926f60 | 2511 | } |
252b5132 | 2512 | |
847f7ad4 | 2513 | static offsetT |
e3bb37b5 | 2514 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2515 | { |
508866be | 2516 | addressT mask; |
ba2adb93 | 2517 | |
847f7ad4 AM |
2518 | switch (size) |
2519 | { | |
508866be L |
2520 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2521 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3e73aa7c | 2522 | #ifdef BFD64 |
64965897 | 2523 | case 4: mask = ((addressT) 1 << 32) - 1; break; |
3e73aa7c | 2524 | #endif |
64965897 | 2525 | case sizeof (val): return val; |
47926f60 | 2526 | default: abort (); |
847f7ad4 AM |
2527 | } |
2528 | ||
4fe51f7d | 2529 | if ((val & ~mask) != 0 && (-val & ~mask) != 0) |
f493c217 AM |
2530 | as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64), |
2531 | (uint64_t) val, (uint64_t) (val & mask)); | |
847f7ad4 | 2532 | |
847f7ad4 AM |
2533 | return val & mask; |
2534 | } | |
2535 | ||
76d3f746 JB |
2536 | static INLINE const char *insn_name (const insn_template *t) |
2537 | { | |
5c139202 | 2538 | return &i386_mnemonics[t->mnem_off]; |
76d3f746 JB |
2539 | } |
2540 | ||
c32fa91d L |
2541 | enum PREFIX_GROUP |
2542 | { | |
2543 | PREFIX_EXIST = 0, | |
2544 | PREFIX_LOCK, | |
2545 | PREFIX_REP, | |
04ef582a | 2546 | PREFIX_DS, |
c32fa91d L |
2547 | PREFIX_OTHER |
2548 | }; | |
2549 | ||
2550 | /* Returns | |
2551 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2552 | same class already exists. | |
2553 | b. PREFIX_LOCK if lock prefix is added. | |
2554 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2555 | d. PREFIX_DS if ds prefix is added. |
2556 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2557 | */ |
2558 | ||
2559 | static enum PREFIX_GROUP | |
e3bb37b5 | 2560 | add_prefix (unsigned int prefix) |
252b5132 | 2561 | { |
c32fa91d | 2562 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2563 | unsigned int q; |
252b5132 | 2564 | |
29b0f896 AM |
2565 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2566 | && flag_code == CODE_64BIT) | |
b1905489 | 2567 | { |
161a04f6 | 2568 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2569 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2570 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2571 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2572 | ret = PREFIX_EXIST; |
b1905489 JB |
2573 | q = REX_PREFIX; |
2574 | } | |
3e73aa7c | 2575 | else |
b1905489 JB |
2576 | { |
2577 | switch (prefix) | |
2578 | { | |
2579 | default: | |
2580 | abort (); | |
2581 | ||
b1905489 | 2582 | case DS_PREFIX_OPCODE: |
04ef582a L |
2583 | ret = PREFIX_DS; |
2584 | /* Fall through. */ | |
2585 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2586 | case ES_PREFIX_OPCODE: |
2587 | case FS_PREFIX_OPCODE: | |
2588 | case GS_PREFIX_OPCODE: | |
2589 | case SS_PREFIX_OPCODE: | |
2590 | q = SEG_PREFIX; | |
2591 | break; | |
2592 | ||
2593 | case REPNE_PREFIX_OPCODE: | |
2594 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2595 | q = REP_PREFIX; |
2596 | ret = PREFIX_REP; | |
2597 | break; | |
2598 | ||
b1905489 | 2599 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2600 | q = LOCK_PREFIX; |
2601 | ret = PREFIX_LOCK; | |
b1905489 JB |
2602 | break; |
2603 | ||
2604 | case FWAIT_OPCODE: | |
2605 | q = WAIT_PREFIX; | |
2606 | break; | |
2607 | ||
2608 | case ADDR_PREFIX_OPCODE: | |
2609 | q = ADDR_PREFIX; | |
2610 | break; | |
2611 | ||
2612 | case DATA_PREFIX_OPCODE: | |
2613 | q = DATA_PREFIX; | |
2614 | break; | |
2615 | } | |
2616 | if (i.prefix[q] != 0) | |
c32fa91d | 2617 | ret = PREFIX_EXIST; |
b1905489 | 2618 | } |
252b5132 | 2619 | |
b1905489 | 2620 | if (ret) |
252b5132 | 2621 | { |
b1905489 JB |
2622 | if (!i.prefix[q]) |
2623 | ++i.prefixes; | |
2624 | i.prefix[q] |= prefix; | |
252b5132 | 2625 | } |
b1905489 JB |
2626 | else |
2627 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2628 | |
252b5132 RH |
2629 | return ret; |
2630 | } | |
2631 | ||
2632 | static void | |
78f12dd3 | 2633 | update_code_flag (int value, int check) |
eecb386c | 2634 | { |
b44fef84 JB |
2635 | PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad; |
2636 | ||
da5f9eb4 | 2637 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpu64 ) |
b44fef84 JB |
2638 | { |
2639 | as_error (_("64bit mode not supported on `%s'."), | |
2640 | cpu_arch_name ? cpu_arch_name : default_arch); | |
2641 | return; | |
2642 | } | |
2643 | ||
2644 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) | |
2645 | { | |
2646 | as_error (_("32bit mode not supported on `%s'."), | |
2647 | cpu_arch_name ? cpu_arch_name : default_arch); | |
2648 | return; | |
2649 | } | |
78f12dd3 | 2650 | |
1e9cc1c2 | 2651 | flag_code = (enum flag_code) value; |
b44fef84 | 2652 | |
eecb386c AM |
2653 | stackop_size = '\0'; |
2654 | } | |
2655 | ||
78f12dd3 L |
2656 | static void |
2657 | set_code_flag (int value) | |
2658 | { | |
2659 | update_code_flag (value, 0); | |
2660 | } | |
2661 | ||
eecb386c | 2662 | static void |
e3bb37b5 | 2663 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2664 | { |
1e9cc1c2 | 2665 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2666 | if (flag_code != CODE_16BIT) |
2667 | abort (); | |
9306ca4a | 2668 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2669 | } |
2670 | ||
2671 | static void | |
e3bb37b5 | 2672 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2673 | { |
2674 | /* Find out if register prefixing is specified. */ | |
2675 | int ask_naked_reg = 0; | |
2676 | ||
2677 | SKIP_WHITESPACE (); | |
29b0f896 | 2678 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2679 | { |
d02603dc NC |
2680 | char *string; |
2681 | int e = get_symbol_name (&string); | |
252b5132 | 2682 | |
47926f60 | 2683 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2684 | ask_naked_reg = 1; |
47926f60 | 2685 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2686 | ask_naked_reg = -1; |
2687 | else | |
d0b47220 | 2688 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2689 | (void) restore_line_pointer (e); |
252b5132 RH |
2690 | } |
2691 | demand_empty_rest_of_line (); | |
c3332e24 | 2692 | |
252b5132 RH |
2693 | intel_syntax = syntax_flag; |
2694 | ||
2695 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2696 | allow_naked_reg = (intel_syntax |
2697 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2698 | else |
2699 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2700 | |
ee86248c | 2701 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2702 | |
e4a3b5a4 | 2703 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2704 | } |
2705 | ||
1efbbeb4 L |
2706 | static void |
2707 | set_intel_mnemonic (int mnemonic_flag) | |
2708 | { | |
e1d4d893 | 2709 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2710 | } |
2711 | ||
db51cc60 L |
2712 | static void |
2713 | set_allow_index_reg (int flag) | |
2714 | { | |
2715 | allow_index_reg = flag; | |
2716 | } | |
2717 | ||
cb19c032 | 2718 | static void |
7bab8ab5 | 2719 | set_check (int what) |
cb19c032 | 2720 | { |
7bab8ab5 JB |
2721 | enum check_kind *kind; |
2722 | const char *str; | |
2723 | ||
2724 | if (what) | |
2725 | { | |
2726 | kind = &operand_check; | |
2727 | str = "operand"; | |
2728 | } | |
2729 | else | |
2730 | { | |
2731 | kind = &sse_check; | |
2732 | str = "sse"; | |
2733 | } | |
2734 | ||
cb19c032 L |
2735 | SKIP_WHITESPACE (); |
2736 | ||
2737 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2738 | { | |
d02603dc NC |
2739 | char *string; |
2740 | int e = get_symbol_name (&string); | |
cb19c032 L |
2741 | |
2742 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2743 | *kind = check_none; |
cb19c032 | 2744 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2745 | *kind = check_warning; |
cb19c032 | 2746 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2747 | *kind = check_error; |
cb19c032 | 2748 | else |
7bab8ab5 | 2749 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2750 | (void) restore_line_pointer (e); |
cb19c032 L |
2751 | } |
2752 | else | |
7bab8ab5 | 2753 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2754 | |
2755 | demand_empty_rest_of_line (); | |
2756 | } | |
2757 | ||
8a9036a4 L |
2758 | static void |
2759 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2760 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2761 | { |
2762 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2763 | static const char *arch; | |
2764 | ||
c085ab00 | 2765 | /* Intel MCU is only supported on ELF. */ |
8a9036a4 L |
2766 | if (!IS_ELF) |
2767 | return; | |
2768 | ||
2769 | if (!arch) | |
2770 | { | |
2771 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2772 | use default_arch. */ | |
2773 | arch = cpu_arch_name; | |
2774 | if (!arch) | |
2775 | arch = default_arch; | |
2776 | } | |
2777 | ||
81486035 | 2778 | /* If we are targeting Intel MCU, we must enable it. */ |
648d04db JB |
2779 | if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU) |
2780 | == new_flag.bitfield.cpuiamcu) | |
81486035 L |
2781 | return; |
2782 | ||
8a9036a4 L |
2783 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2784 | #endif | |
2785 | } | |
2786 | ||
8180707f | 2787 | static void |
bd483d21 | 2788 | extend_cpu_sub_arch_name (const char *pfx, const char *name) |
8180707f JB |
2789 | { |
2790 | if (cpu_sub_arch_name) | |
2791 | cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name, | |
bd483d21 | 2792 | pfx, name, (const char *) NULL); |
8180707f | 2793 | else |
bd483d21 JB |
2794 | cpu_sub_arch_name = concat (pfx, name, (const char *) NULL); |
2795 | } | |
2796 | ||
2797 | static void isa_enable (unsigned int idx) | |
2798 | { | |
2799 | i386_cpu_flags flags = cpu_flags_or (cpu_arch_flags, cpu_arch[idx].enable); | |
2800 | ||
2801 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2802 | { | |
2803 | extend_cpu_sub_arch_name (".", cpu_arch[idx].name); | |
2804 | cpu_arch_flags = flags; | |
2805 | } | |
2806 | ||
2807 | cpu_arch_isa_flags = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[idx].enable); | |
2808 | } | |
2809 | ||
2810 | static void isa_disable (unsigned int idx) | |
2811 | { | |
2812 | i386_cpu_flags flags | |
2813 | = cpu_flags_and_not (cpu_arch_flags, cpu_arch[idx].disable); | |
2814 | ||
2815 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2816 | { | |
2817 | extend_cpu_sub_arch_name (".no", cpu_arch[idx].name); | |
2818 | cpu_arch_flags = flags; | |
2819 | } | |
2820 | ||
2821 | cpu_arch_isa_flags | |
2822 | = cpu_flags_and_not (cpu_arch_isa_flags, cpu_arch[idx].disable); | |
8180707f JB |
2823 | } |
2824 | ||
e413e4e9 | 2825 | static void |
e3bb37b5 | 2826 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2827 | { |
f68697e8 JB |
2828 | typedef struct arch_stack_entry |
2829 | { | |
2830 | const struct arch_stack_entry *prev; | |
2831 | const char *name; | |
2832 | char *sub_name; | |
2833 | i386_cpu_flags flags; | |
2834 | i386_cpu_flags isa_flags; | |
2835 | enum processor_type isa; | |
2836 | enum flag_code flag_code; | |
4fc85f37 | 2837 | unsigned int vector_size; |
f68697e8 JB |
2838 | char stackop_size; |
2839 | bool no_cond_jump_promotion; | |
2840 | } arch_stack_entry; | |
2841 | static const arch_stack_entry *arch_stack_top; | |
dfab07b9 JB |
2842 | char *s; |
2843 | int e; | |
2844 | const char *string; | |
2845 | unsigned int j = 0; | |
f68697e8 | 2846 | |
47926f60 | 2847 | SKIP_WHITESPACE (); |
e413e4e9 | 2848 | |
dfab07b9 JB |
2849 | if (is_end_of_line[(unsigned char) *input_line_pointer]) |
2850 | { | |
2851 | as_bad (_("missing cpu architecture")); | |
2852 | input_line_pointer++; | |
2853 | return; | |
2854 | } | |
2855 | ||
2856 | e = get_symbol_name (&s); | |
2857 | string = s; | |
2858 | ||
2859 | if (strcmp (string, "push") == 0) | |
e413e4e9 | 2860 | { |
dfab07b9 | 2861 | arch_stack_entry *top = XNEW (arch_stack_entry); |
e413e4e9 | 2862 | |
dfab07b9 JB |
2863 | top->name = cpu_arch_name; |
2864 | if (cpu_sub_arch_name) | |
2865 | top->sub_name = xstrdup (cpu_sub_arch_name); | |
2866 | else | |
2867 | top->sub_name = NULL; | |
2868 | top->flags = cpu_arch_flags; | |
2869 | top->isa = cpu_arch_isa; | |
2870 | top->isa_flags = cpu_arch_isa_flags; | |
2871 | top->flag_code = flag_code; | |
4fc85f37 | 2872 | top->vector_size = vector_size; |
dfab07b9 JB |
2873 | top->stackop_size = stackop_size; |
2874 | top->no_cond_jump_promotion = no_cond_jump_promotion; | |
2875 | ||
2876 | top->prev = arch_stack_top; | |
2877 | arch_stack_top = top; | |
2878 | ||
2879 | (void) restore_line_pointer (e); | |
2880 | demand_empty_rest_of_line (); | |
2881 | return; | |
2882 | } | |
2883 | ||
2884 | if (strcmp (string, "pop") == 0) | |
2885 | { | |
2886 | const arch_stack_entry *top = arch_stack_top; | |
2887 | ||
2888 | if (!top) | |
2889 | as_bad (_(".arch stack is empty")); | |
2890 | else if (top->flag_code != flag_code | |
2891 | || top->stackop_size != stackop_size) | |
2892 | { | |
2893 | static const unsigned int bits[] = { | |
2894 | [CODE_16BIT] = 16, | |
2895 | [CODE_32BIT] = 32, | |
2896 | [CODE_64BIT] = 64, | |
2897 | }; | |
2898 | ||
2899 | as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"), | |
2900 | bits[top->flag_code], | |
2901 | top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : ""); | |
2902 | } | |
2903 | else | |
3ce2ebcf | 2904 | { |
dfab07b9 JB |
2905 | arch_stack_top = top->prev; |
2906 | ||
2907 | cpu_arch_name = top->name; | |
2908 | free (cpu_sub_arch_name); | |
2909 | cpu_sub_arch_name = top->sub_name; | |
2910 | cpu_arch_flags = top->flags; | |
2911 | cpu_arch_isa = top->isa; | |
2912 | cpu_arch_isa_flags = top->isa_flags; | |
4fc85f37 | 2913 | vector_size = top->vector_size; |
dfab07b9 JB |
2914 | no_cond_jump_promotion = top->no_cond_jump_promotion; |
2915 | ||
2916 | XDELETE (top); | |
2917 | } | |
2918 | ||
2919 | (void) restore_line_pointer (e); | |
2920 | demand_empty_rest_of_line (); | |
2921 | return; | |
2922 | } | |
2923 | ||
2924 | if (strcmp (string, "default") == 0) | |
2925 | { | |
2926 | if (strcmp (default_arch, "iamcu") == 0) | |
2927 | string = default_arch; | |
2928 | else | |
2929 | { | |
2930 | static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS; | |
2931 | ||
2932 | cpu_arch_name = NULL; | |
2933 | free (cpu_sub_arch_name); | |
2934 | cpu_sub_arch_name = NULL; | |
2935 | cpu_arch_flags = cpu_unknown_flags; | |
dfab07b9 JB |
2936 | cpu_arch_isa = PROCESSOR_UNKNOWN; |
2937 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; | |
2938 | if (!cpu_arch_tune_set) | |
fb263707 | 2939 | cpu_arch_tune = PROCESSOR_UNKNOWN; |
dfab07b9 | 2940 | |
4fc85f37 JB |
2941 | vector_size = VSZ_DEFAULT; |
2942 | ||
dfab07b9 JB |
2943 | j = ARRAY_SIZE (cpu_arch) + 1; |
2944 | } | |
2945 | } | |
2946 | ||
2947 | for (; j < ARRAY_SIZE (cpu_arch); j++) | |
2948 | { | |
2949 | if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0 | |
2950 | && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE)) | |
2951 | { | |
2952 | if (*string != '.') | |
2953 | { | |
2954 | check_cpu_arch_compatible (string, cpu_arch[j].enable); | |
3ce2ebcf | 2955 | |
da5f9eb4 | 2956 | if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 ) |
1d07cfb4 JB |
2957 | { |
2958 | as_bad (_("64bit mode not supported on `%s'."), | |
2959 | cpu_arch[j].name); | |
2960 | (void) restore_line_pointer (e); | |
2961 | ignore_rest_of_line (); | |
2962 | return; | |
2963 | } | |
2964 | ||
2965 | if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386) | |
2966 | { | |
2967 | as_bad (_("32bit mode not supported on `%s'."), | |
2968 | cpu_arch[j].name); | |
2969 | (void) restore_line_pointer (e); | |
2970 | ignore_rest_of_line (); | |
2971 | return; | |
2972 | } | |
2973 | ||
dfab07b9 | 2974 | cpu_arch_name = cpu_arch[j].name; |
3ce2ebcf JB |
2975 | free (cpu_sub_arch_name); |
2976 | cpu_sub_arch_name = NULL; | |
dfab07b9 | 2977 | cpu_arch_flags = cpu_arch[j].enable; |
dfab07b9 JB |
2978 | cpu_arch_isa = cpu_arch[j].type; |
2979 | cpu_arch_isa_flags = cpu_arch[j].enable; | |
3ce2ebcf | 2980 | if (!cpu_arch_tune_set) |
fb263707 | 2981 | cpu_arch_tune = cpu_arch_isa; |
4fc85f37 JB |
2982 | |
2983 | vector_size = VSZ_DEFAULT; | |
2984 | ||
dfab07b9 JB |
2985 | pre_386_16bit_warned = false; |
2986 | break; | |
3ce2ebcf | 2987 | } |
f68697e8 | 2988 | |
dfab07b9 JB |
2989 | if (cpu_flags_all_zero (&cpu_arch[j].enable)) |
2990 | continue; | |
f68697e8 | 2991 | |
bd483d21 | 2992 | isa_enable (j); |
f68697e8 JB |
2993 | |
2994 | (void) restore_line_pointer (e); | |
4fc85f37 JB |
2995 | |
2996 | switch (cpu_arch[j].vsz) | |
2997 | { | |
2998 | default: | |
2999 | break; | |
3000 | ||
3001 | case vsz_set: | |
3002 | #ifdef SVR4_COMMENT_CHARS | |
3003 | if (*input_line_pointer == ':' || *input_line_pointer == '/') | |
3004 | #else | |
3005 | if (*input_line_pointer == '/') | |
3006 | #endif | |
3007 | { | |
3008 | ++input_line_pointer; | |
3009 | switch (get_absolute_expression ()) | |
3010 | { | |
3011 | case 512: vector_size = VSZ512; break; | |
3012 | case 256: vector_size = VSZ256; break; | |
3013 | case 128: vector_size = VSZ128; break; | |
3014 | default: | |
3015 | as_bad (_("Unrecognized vector size specifier")); | |
3016 | ignore_rest_of_line (); | |
3017 | return; | |
3018 | } | |
3019 | break; | |
3020 | } | |
3021 | /* Fall through. */ | |
3022 | case vsz_reset: | |
3023 | vector_size = VSZ_DEFAULT; | |
3024 | break; | |
3025 | } | |
3026 | ||
f68697e8 JB |
3027 | demand_empty_rest_of_line (); |
3028 | return; | |
3029 | } | |
dfab07b9 | 3030 | } |
3ce2ebcf | 3031 | |
dfab07b9 JB |
3032 | if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch)) |
3033 | { | |
3034 | /* Disable an ISA extension. */ | |
3035 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
3036 | if (cpu_arch[j].type == PROCESSOR_NONE | |
3037 | && strcmp (string + 3, cpu_arch[j].name) == 0) | |
3038 | { | |
bd483d21 | 3039 | isa_disable (j); |
e413e4e9 | 3040 | |
4fc85f37 JB |
3041 | if (cpu_arch[j].vsz == vsz_set) |
3042 | vector_size = VSZ_DEFAULT; | |
3043 | ||
dfab07b9 JB |
3044 | (void) restore_line_pointer (e); |
3045 | demand_empty_rest_of_line (); | |
3046 | return; | |
3047 | } | |
e413e4e9 | 3048 | } |
dfab07b9 JB |
3049 | |
3050 | if (j == ARRAY_SIZE (cpu_arch)) | |
3051 | as_bad (_("no such architecture: `%s'"), string); | |
3052 | ||
3053 | *input_line_pointer = e; | |
e413e4e9 | 3054 | |
fddf5b5b AM |
3055 | no_cond_jump_promotion = 0; |
3056 | if (*input_line_pointer == ',' | |
29b0f896 | 3057 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 3058 | { |
d02603dc | 3059 | ++input_line_pointer; |
dfab07b9 JB |
3060 | e = get_symbol_name (&s); |
3061 | string = s; | |
fddf5b5b AM |
3062 | |
3063 | if (strcmp (string, "nojumps") == 0) | |
3064 | no_cond_jump_promotion = 1; | |
3065 | else if (strcmp (string, "jumps") == 0) | |
3066 | ; | |
3067 | else | |
3068 | as_bad (_("no such architecture modifier: `%s'"), string); | |
3069 | ||
d02603dc | 3070 | (void) restore_line_pointer (e); |
fddf5b5b AM |
3071 | } |
3072 | ||
e413e4e9 AM |
3073 | demand_empty_rest_of_line (); |
3074 | } | |
3075 | ||
8a9036a4 L |
3076 | enum bfd_architecture |
3077 | i386_arch (void) | |
3078 | { | |
c085ab00 | 3079 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 | 3080 | { |
ed049bd6 | 3081 | if (!IS_ELF || flag_code == CODE_64BIT) |
81486035 L |
3082 | as_fatal (_("Intel MCU is 32bit ELF only")); |
3083 | return bfd_arch_iamcu; | |
3084 | } | |
8a9036a4 L |
3085 | else |
3086 | return bfd_arch_i386; | |
3087 | } | |
3088 | ||
b9d79e03 | 3089 | unsigned long |
7016a5d5 | 3090 | i386_mach (void) |
b9d79e03 | 3091 | { |
d34049e8 | 3092 | if (startswith (default_arch, "x86_64")) |
8a9036a4 | 3093 | { |
c085ab00 | 3094 | if (default_arch[6] == '\0') |
8a9036a4 | 3095 | return bfd_mach_x86_64; |
351f65ca L |
3096 | else |
3097 | return bfd_mach_x64_32; | |
8a9036a4 | 3098 | } |
5197d474 L |
3099 | else if (!strcmp (default_arch, "i386") |
3100 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
3101 | { |
3102 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
3103 | { | |
ed049bd6 | 3104 | if (!IS_ELF) |
81486035 L |
3105 | as_fatal (_("Intel MCU is 32bit ELF only")); |
3106 | return bfd_mach_i386_iamcu; | |
3107 | } | |
3108 | else | |
3109 | return bfd_mach_i386_i386; | |
3110 | } | |
b9d79e03 | 3111 | else |
2b5d6a91 | 3112 | as_fatal (_("unknown architecture")); |
b9d79e03 | 3113 | } |
b9d79e03 | 3114 | \f |
99f0fb12 JB |
3115 | #include "opcodes/i386-tbl.h" |
3116 | ||
d3b01414 JB |
3117 | static void |
3118 | op_lookup (const char *mnemonic) | |
3119 | { | |
3120 | i386_op_off_t *pos = str_hash_find (op_hash, mnemonic); | |
3121 | ||
3122 | if (pos != NULL) | |
3123 | { | |
3124 | current_templates.start = &i386_optab[pos[0]]; | |
3125 | current_templates.end = &i386_optab[pos[1]]; | |
3126 | } | |
3127 | else | |
3128 | current_templates.end = current_templates.start = NULL; | |
3129 | } | |
3130 | ||
252b5132 | 3131 | void |
7016a5d5 | 3132 | md_begin (void) |
252b5132 | 3133 | { |
86fa6981 L |
3134 | /* Support pseudo prefixes like {disp32}. */ |
3135 | lex_type ['{'] = LEX_BEGIN_NAME; | |
3136 | ||
47926f60 | 3137 | /* Initialize op_hash hash table. */ |
629310ab | 3138 | op_hash = str_htab_create (); |
252b5132 RH |
3139 | |
3140 | { | |
d3b01414 JB |
3141 | const i386_op_off_t *cur = i386_op_sets; |
3142 | const i386_op_off_t *end = cur + ARRAY_SIZE (i386_op_sets) - 1; | |
3143 | ||
3144 | for (; cur < end; ++cur) | |
3145 | if (str_hash_insert (op_hash, insn_name (&i386_optab[*cur]), cur, 0)) | |
3146 | as_fatal (_("duplicate %s"), insn_name (&i386_optab[*cur])); | |
252b5132 RH |
3147 | } |
3148 | ||
47926f60 | 3149 | /* Initialize reg_hash hash table. */ |
629310ab | 3150 | reg_hash = str_htab_create (); |
252b5132 | 3151 | { |
29b0f896 | 3152 | const reg_entry *regtab; |
c3fe08fa | 3153 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3154 | |
c3fe08fa | 3155 | for (regtab = i386_regtab; regtab_size--; regtab++) |
6225c532 | 3156 | { |
6288d05f JB |
3157 | switch (regtab->reg_type.bitfield.class) |
3158 | { | |
3159 | case Reg: | |
34684862 JB |
3160 | if (regtab->reg_type.bitfield.dword) |
3161 | { | |
3162 | if (regtab->reg_type.bitfield.instance == Accum) | |
3163 | reg_eax = regtab; | |
3164 | } | |
3165 | else if (regtab->reg_type.bitfield.tbyte) | |
6288d05f JB |
3166 | { |
3167 | /* There's no point inserting st(<N>) in the hash table, as | |
3168 | parentheses aren't included in register_chars[] anyway. */ | |
3169 | if (regtab->reg_type.bitfield.instance != Accum) | |
3170 | continue; | |
3171 | reg_st0 = regtab; | |
3172 | } | |
3173 | break; | |
3174 | ||
5e042380 JB |
3175 | case SReg: |
3176 | switch (regtab->reg_num) | |
3177 | { | |
3178 | case 0: reg_es = regtab; break; | |
3179 | case 2: reg_ss = regtab; break; | |
3180 | case 3: reg_ds = regtab; break; | |
3181 | } | |
3182 | break; | |
3183 | ||
6288d05f JB |
3184 | case RegMask: |
3185 | if (!regtab->reg_num) | |
3186 | reg_k0 = regtab; | |
3187 | break; | |
3188 | } | |
3189 | ||
6225c532 JB |
3190 | if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL) |
3191 | as_fatal (_("duplicate %s"), regtab->reg_name); | |
6225c532 | 3192 | } |
252b5132 RH |
3193 | } |
3194 | ||
47926f60 | 3195 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3196 | { |
29b0f896 | 3197 | int c; |
d2b1a14d | 3198 | const char *p; |
252b5132 RH |
3199 | |
3200 | for (c = 0; c < 256; c++) | |
3201 | { | |
014fbcda | 3202 | if (ISDIGIT (c) || ISLOWER (c)) |
252b5132 RH |
3203 | { |
3204 | mnemonic_chars[c] = c; | |
3205 | register_chars[c] = c; | |
3206 | operand_chars[c] = c; | |
3207 | } | |
3882b010 | 3208 | else if (ISUPPER (c)) |
252b5132 | 3209 | { |
3882b010 | 3210 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3211 | register_chars[c] = mnemonic_chars[c]; |
3212 | operand_chars[c] = c; | |
3213 | } | |
b3983e5f JB |
3214 | #ifdef SVR4_COMMENT_CHARS |
3215 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3216 | operand_chars[c] = c; | |
3217 | #endif | |
252b5132 | 3218 | |
4795cd4a JB |
3219 | if (c >= 128) |
3220 | operand_chars[c] = c; | |
252b5132 RH |
3221 | } |
3222 | ||
c0f3af97 | 3223 | mnemonic_chars['_'] = '_'; |
791fe849 | 3224 | mnemonic_chars['-'] = '-'; |
0003779b | 3225 | mnemonic_chars['.'] = '.'; |
252b5132 | 3226 | |
d2b1a14d JB |
3227 | for (p = extra_symbol_chars; *p != '\0'; p++) |
3228 | operand_chars[(unsigned char) *p] = *p; | |
252b5132 RH |
3229 | for (p = operand_special_chars; *p != '\0'; p++) |
3230 | operand_chars[(unsigned char) *p] = *p; | |
3231 | } | |
3232 | ||
a4447b93 RH |
3233 | if (flag_code == CODE_64BIT) |
3234 | { | |
ca19b261 KT |
3235 | #if defined (OBJ_COFF) && defined (TE_PE) |
3236 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3237 | ? 32 : 16); | |
3238 | #else | |
a4447b93 | 3239 | x86_dwarf2_return_column = 16; |
ca19b261 | 3240 | #endif |
61ff971f | 3241 | x86_cie_data_alignment = -8; |
b52c4ee4 IB |
3242 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3243 | x86_sframe_cfa_sp_reg = 7; | |
3244 | x86_sframe_cfa_fp_reg = 6; | |
3245 | #endif | |
a4447b93 RH |
3246 | } |
3247 | else | |
3248 | { | |
3249 | x86_dwarf2_return_column = 8; | |
3250 | x86_cie_data_alignment = -4; | |
3251 | } | |
e379e5f3 L |
3252 | |
3253 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3254 | can be turned into BRANCH_PREFIX frag. */ | |
3255 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3256 | abort (); | |
252b5132 RH |
3257 | } |
3258 | ||
3259 | void | |
e3bb37b5 | 3260 | i386_print_statistics (FILE *file) |
252b5132 | 3261 | { |
629310ab ML |
3262 | htab_print_statistics (file, "i386 opcode", op_hash); |
3263 | htab_print_statistics (file, "i386 register", reg_hash); | |
252b5132 | 3264 | } |
654d6f31 AM |
3265 | |
3266 | void | |
3267 | i386_md_end (void) | |
3268 | { | |
3269 | htab_delete (op_hash); | |
3270 | htab_delete (reg_hash); | |
3271 | } | |
252b5132 | 3272 | \f |
252b5132 RH |
3273 | #ifdef DEBUG386 |
3274 | ||
ce8a8b2f | 3275 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3276 | static void pte (insn_template *); |
40fb9820 | 3277 | static void pt (i386_operand_type); |
e3bb37b5 L |
3278 | static void pe (expressionS *); |
3279 | static void ps (symbolS *); | |
252b5132 RH |
3280 | |
3281 | static void | |
2c703856 | 3282 | pi (const char *line, i386_insn *x) |
252b5132 | 3283 | { |
09137c09 | 3284 | unsigned int j; |
252b5132 RH |
3285 | |
3286 | fprintf (stdout, "%s: template ", line); | |
3287 | pte (&x->tm); | |
09f131f2 JH |
3288 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3289 | x->base_reg ? x->base_reg->reg_name : "none", | |
3290 | x->index_reg ? x->index_reg->reg_name : "none", | |
3291 | x->log2_scale_factor); | |
3292 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3293 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3294 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3295 | x->sib.base, x->sib.index, x->sib.scale); | |
3296 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3297 | (x->rex & REX_W) != 0, |
3298 | (x->rex & REX_R) != 0, | |
3299 | (x->rex & REX_X) != 0, | |
3300 | (x->rex & REX_B) != 0); | |
09137c09 | 3301 | for (j = 0; j < x->operands; j++) |
252b5132 | 3302 | { |
09137c09 SP |
3303 | fprintf (stdout, " #%d: ", j + 1); |
3304 | pt (x->types[j]); | |
252b5132 | 3305 | fprintf (stdout, "\n"); |
bab6aec1 | 3306 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3307 | || x->types[j].bitfield.class == RegMMX |
3308 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3309 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3310 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3311 | || x->types[j].bitfield.class == RegCR |
3312 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3313 | || x->types[j].bitfield.class == RegTR |
3314 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3315 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3316 | if (operand_type_check (x->types[j], imm)) | |
3317 | pe (x->op[j].imms); | |
3318 | if (operand_type_check (x->types[j], disp)) | |
3319 | pe (x->op[j].disps); | |
252b5132 RH |
3320 | } |
3321 | } | |
3322 | ||
3323 | static void | |
d3ce72d0 | 3324 | pte (insn_template *t) |
252b5132 | 3325 | { |
b933fa4b | 3326 | static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; |
441f6aca | 3327 | static const char *const opc_spc[] = { |
0cc78721 | 3328 | NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL, |
441f6aca JB |
3329 | "XOP08", "XOP09", "XOP0A", |
3330 | }; | |
09137c09 | 3331 | unsigned int j; |
441f6aca | 3332 | |
252b5132 | 3333 | fprintf (stdout, " %d operands ", t->operands); |
441f6aca JB |
3334 | if (opc_pfx[t->opcode_modifier.opcodeprefix]) |
3335 | fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]); | |
ddb62495 JB |
3336 | if (opc_spc[t->opcode_space]) |
3337 | fprintf (stdout, "space %s ", opc_spc[t->opcode_space]); | |
47926f60 | 3338 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3339 | if (t->extension_opcode != None) |
3340 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3341 | if (t->opcode_modifier.d) |
252b5132 | 3342 | fprintf (stdout, "D"); |
40fb9820 | 3343 | if (t->opcode_modifier.w) |
252b5132 RH |
3344 | fprintf (stdout, "W"); |
3345 | fprintf (stdout, "\n"); | |
09137c09 | 3346 | for (j = 0; j < t->operands; j++) |
252b5132 | 3347 | { |
09137c09 SP |
3348 | fprintf (stdout, " #%d type ", j + 1); |
3349 | pt (t->operand_types[j]); | |
252b5132 RH |
3350 | fprintf (stdout, "\n"); |
3351 | } | |
3352 | } | |
3353 | ||
3354 | static void | |
e3bb37b5 | 3355 | pe (expressionS *e) |
252b5132 | 3356 | { |
24eab124 | 3357 | fprintf (stdout, " operation %d\n", e->X_op); |
b8281767 AM |
3358 | fprintf (stdout, " add_number %" PRId64 " (%" PRIx64 ")\n", |
3359 | (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number); | |
252b5132 RH |
3360 | if (e->X_add_symbol) |
3361 | { | |
3362 | fprintf (stdout, " add_symbol "); | |
3363 | ps (e->X_add_symbol); | |
3364 | fprintf (stdout, "\n"); | |
3365 | } | |
3366 | if (e->X_op_symbol) | |
3367 | { | |
3368 | fprintf (stdout, " op_symbol "); | |
3369 | ps (e->X_op_symbol); | |
3370 | fprintf (stdout, "\n"); | |
3371 | } | |
3372 | } | |
3373 | ||
3374 | static void | |
e3bb37b5 | 3375 | ps (symbolS *s) |
252b5132 RH |
3376 | { |
3377 | fprintf (stdout, "%s type %s%s", | |
3378 | S_GET_NAME (s), | |
3379 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3380 | segment_name (S_GET_SEGMENT (s))); | |
3381 | } | |
3382 | ||
7b81dfbb | 3383 | static struct type_name |
252b5132 | 3384 | { |
40fb9820 L |
3385 | i386_operand_type mask; |
3386 | const char *name; | |
252b5132 | 3387 | } |
7b81dfbb | 3388 | const type_names[] = |
252b5132 | 3389 | { |
05909f23 JB |
3390 | { { .bitfield = { .class = Reg, .byte = 1 } }, "r8" }, |
3391 | { { .bitfield = { .class = Reg, .word = 1 } }, "r16" }, | |
3392 | { { .bitfield = { .class = Reg, .dword = 1 } }, "r32" }, | |
3393 | { { .bitfield = { .class = Reg, .qword = 1 } }, "r64" }, | |
3394 | { { .bitfield = { .instance = Accum, .byte = 1 } }, "acc8" }, | |
3395 | { { .bitfield = { .instance = Accum, .word = 1 } }, "acc16" }, | |
3396 | { { .bitfield = { .instance = Accum, .dword = 1 } }, "acc32" }, | |
3397 | { { .bitfield = { .instance = Accum, .qword = 1 } }, "acc64" }, | |
3398 | { { .bitfield = { .imm8 = 1 } }, "i8" }, | |
3399 | { { .bitfield = { .imm8s = 1 } }, "i8s" }, | |
3400 | { { .bitfield = { .imm16 = 1 } }, "i16" }, | |
3401 | { { .bitfield = { .imm32 = 1 } }, "i32" }, | |
3402 | { { .bitfield = { .imm32s = 1 } }, "i32s" }, | |
3403 | { { .bitfield = { .imm64 = 1 } }, "i64" }, | |
3404 | { { .bitfield = { .imm1 = 1 } }, "i1" }, | |
3405 | { { .bitfield = { .baseindex = 1 } }, "BaseIndex" }, | |
3406 | { { .bitfield = { .disp8 = 1 } }, "d8" }, | |
3407 | { { .bitfield = { .disp16 = 1 } }, "d16" }, | |
3408 | { { .bitfield = { .disp32 = 1 } }, "d32" }, | |
3409 | { { .bitfield = { .disp64 = 1 } }, "d64" }, | |
3410 | { { .bitfield = { .instance = RegD, .word = 1 } }, "InOutPortReg" }, | |
3411 | { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" }, | |
3412 | { { .bitfield = { .class = RegCR } }, "control reg" }, | |
3413 | { { .bitfield = { .class = RegTR } }, "test reg" }, | |
3414 | { { .bitfield = { .class = RegDR } }, "debug reg" }, | |
3415 | { { .bitfield = { .class = Reg, .tbyte = 1 } }, "FReg" }, | |
3416 | { { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" }, | |
3417 | { { .bitfield = { .class = SReg } }, "SReg" }, | |
3418 | { { .bitfield = { .class = RegMMX } }, "rMMX" }, | |
3419 | { { .bitfield = { .class = RegSIMD, .xmmword = 1 } }, "rXMM" }, | |
3420 | { { .bitfield = { .class = RegSIMD, .ymmword = 1 } }, "rYMM" }, | |
3421 | { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" }, | |
3422 | { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" }, | |
3423 | { { .bitfield = { .class = RegMask } }, "Mask reg" }, | |
252b5132 RH |
3424 | }; |
3425 | ||
3426 | static void | |
40fb9820 | 3427 | pt (i386_operand_type t) |
252b5132 | 3428 | { |
40fb9820 | 3429 | unsigned int j; |
c6fb90c8 | 3430 | i386_operand_type a; |
252b5132 | 3431 | |
40fb9820 | 3432 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3433 | { |
3434 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3435 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3436 | fprintf (stdout, "%s, ", type_names[j].name); |
3437 | } | |
252b5132 RH |
3438 | fflush (stdout); |
3439 | } | |
3440 | ||
3441 | #endif /* DEBUG386 */ | |
3442 | \f | |
252b5132 | 3443 | static bfd_reloc_code_real_type |
3956db08 | 3444 | reloc (unsigned int size, |
64e74474 AM |
3445 | int pcrel, |
3446 | int sign, | |
3447 | bfd_reloc_code_real_type other) | |
252b5132 | 3448 | { |
47926f60 | 3449 | if (other != NO_RELOC) |
3956db08 | 3450 | { |
91d6fa6a | 3451 | reloc_howto_type *rel; |
3956db08 JB |
3452 | |
3453 | if (size == 8) | |
3454 | switch (other) | |
3455 | { | |
64e74474 AM |
3456 | case BFD_RELOC_X86_64_GOT32: |
3457 | return BFD_RELOC_X86_64_GOT64; | |
3458 | break; | |
553d1284 L |
3459 | case BFD_RELOC_X86_64_GOTPLT64: |
3460 | return BFD_RELOC_X86_64_GOTPLT64; | |
3461 | break; | |
64e74474 AM |
3462 | case BFD_RELOC_X86_64_PLTOFF64: |
3463 | return BFD_RELOC_X86_64_PLTOFF64; | |
3464 | break; | |
3465 | case BFD_RELOC_X86_64_GOTPC32: | |
3466 | other = BFD_RELOC_X86_64_GOTPC64; | |
3467 | break; | |
3468 | case BFD_RELOC_X86_64_GOTPCREL: | |
3469 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3470 | break; | |
3471 | case BFD_RELOC_X86_64_TPOFF32: | |
3472 | other = BFD_RELOC_X86_64_TPOFF64; | |
3473 | break; | |
3474 | case BFD_RELOC_X86_64_DTPOFF32: | |
3475 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3476 | break; | |
3477 | default: | |
3478 | break; | |
3956db08 | 3479 | } |
e05278af | 3480 | |
8ce3d284 | 3481 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3482 | if (other == BFD_RELOC_SIZE32) |
3483 | { | |
3484 | if (size == 8) | |
1ab668bf | 3485 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3486 | if (pcrel) |
1ab668bf AM |
3487 | { |
3488 | as_bad (_("there are no pc-relative size relocations")); | |
3489 | return NO_RELOC; | |
3490 | } | |
8fd4256d | 3491 | } |
8ce3d284 | 3492 | #endif |
8fd4256d | 3493 | |
e05278af | 3494 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3495 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3496 | sign = -1; |
3497 | ||
91d6fa6a NC |
3498 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3499 | if (!rel) | |
3956db08 | 3500 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3501 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3502 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3503 | bfd_get_reloc_size (rel), |
3956db08 | 3504 | size); |
91d6fa6a | 3505 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3506 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3507 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3508 | && !sign) |
91d6fa6a | 3509 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3510 | && sign > 0)) |
3956db08 JB |
3511 | as_bad (_("relocated field and relocation type differ in signedness")); |
3512 | else | |
3513 | return other; | |
3514 | return NO_RELOC; | |
3515 | } | |
252b5132 RH |
3516 | |
3517 | if (pcrel) | |
3518 | { | |
3e73aa7c | 3519 | if (!sign) |
3956db08 | 3520 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3521 | switch (size) |
3522 | { | |
3523 | case 1: return BFD_RELOC_8_PCREL; | |
3524 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3525 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3526 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3527 | } |
3956db08 | 3528 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3529 | } |
3530 | else | |
3531 | { | |
3956db08 | 3532 | if (sign > 0) |
e5cb08ac | 3533 | switch (size) |
3e73aa7c JH |
3534 | { |
3535 | case 4: return BFD_RELOC_X86_64_32S; | |
3536 | } | |
3537 | else | |
3538 | switch (size) | |
3539 | { | |
3540 | case 1: return BFD_RELOC_8; | |
3541 | case 2: return BFD_RELOC_16; | |
3542 | case 4: return BFD_RELOC_32; | |
3543 | case 8: return BFD_RELOC_64; | |
3544 | } | |
3956db08 JB |
3545 | as_bad (_("cannot do %s %u byte relocation"), |
3546 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3547 | } |
3548 | ||
0cc9e1d3 | 3549 | return NO_RELOC; |
252b5132 RH |
3550 | } |
3551 | ||
071c5d81 | 3552 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
47926f60 KH |
3553 | /* Here we decide which fixups can be adjusted to make them relative to |
3554 | the beginning of the section instead of the symbol. Basically we need | |
3555 | to make sure that the dynamic relocations are done correctly, so in | |
3556 | some cases we force the original symbol to be used. */ | |
3557 | ||
252b5132 | 3558 | int |
071c5d81 | 3559 | tc_i386_fix_adjustable (fixS *fixP) |
252b5132 | 3560 | { |
718ddfc0 | 3561 | if (!IS_ELF) |
31312f95 AM |
3562 | return 1; |
3563 | ||
a161fe53 AM |
3564 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3565 | mode. */ | |
3566 | if (use_rela_relocations | |
3567 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3568 | && fixP->fx_pcrel) | |
252b5132 | 3569 | return 0; |
31312f95 | 3570 | |
8d01d9a9 AJ |
3571 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3572 | and changed later by validate_fix. */ | |
3573 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3574 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3575 | return 0; | |
3576 | ||
8fd4256d L |
3577 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3578 | for size relocations. */ | |
3579 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3580 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3581 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3582 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3583 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3584 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3585 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3586 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3587 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3588 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3589 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3590 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3591 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3592 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3593 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3594 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3595 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3596 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3597 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
3d5a60de | 3598 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX |
bffbf940 JJ |
3599 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3600 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3601 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3602 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 | 3603 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
a533c8df | 3604 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTTPOFF |
bffbf940 | 3605 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 |
d6ab8113 JB |
3606 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3607 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 | 3608 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
a533c8df | 3609 | || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC |
67a4f2b7 | 3610 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL |
252b5132 RH |
3611 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3612 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3613 | return 0; | |
3614 | return 1; | |
3615 | } | |
071c5d81 | 3616 | #endif |
252b5132 | 3617 | |
a9aabc23 JB |
3618 | static INLINE bool |
3619 | want_disp32 (const insn_template *t) | |
3620 | { | |
3621 | return flag_code != CODE_64BIT | |
3622 | || i.prefix[ADDR_PREFIX] | |
7fc69528 | 3623 | || (t->mnem_off == MN_lea |
fe134c65 JB |
3624 | && (!i.types[1].bitfield.qword |
3625 | || t->opcode_modifier.size == SIZE32)); | |
a9aabc23 JB |
3626 | } |
3627 | ||
b4cac588 | 3628 | static int |
e3bb37b5 | 3629 | intel_float_operand (const char *mnemonic) |
252b5132 | 3630 | { |
9306ca4a JB |
3631 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3632 | operands, hence the code here is free to improperly handle opcodes that | |
3633 | have no operands (for better performance and smaller code). */ | |
3634 | ||
3635 | if (mnemonic[0] != 'f') | |
3636 | return 0; /* non-math */ | |
3637 | ||
3638 | switch (mnemonic[1]) | |
3639 | { | |
3640 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3641 | the fs segment override prefix not currently handled because no | |
3642 | call path can make opcodes without operands get here */ | |
3643 | case 'i': | |
3644 | return 2 /* integer op */; | |
3645 | case 'l': | |
3646 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3647 | return 3; /* fldcw/fldenv */ | |
3648 | break; | |
3649 | case 'n': | |
3650 | if (mnemonic[2] != 'o' /* fnop */) | |
3651 | return 3; /* non-waiting control op */ | |
3652 | break; | |
3653 | case 'r': | |
3654 | if (mnemonic[2] == 's') | |
3655 | return 3; /* frstor/frstpm */ | |
3656 | break; | |
3657 | case 's': | |
3658 | if (mnemonic[2] == 'a') | |
3659 | return 3; /* fsave */ | |
3660 | if (mnemonic[2] == 't') | |
3661 | { | |
3662 | switch (mnemonic[3]) | |
3663 | { | |
3664 | case 'c': /* fstcw */ | |
3665 | case 'd': /* fstdw */ | |
3666 | case 'e': /* fstenv */ | |
3667 | case 's': /* fsts[gw] */ | |
3668 | return 3; | |
3669 | } | |
3670 | } | |
3671 | break; | |
3672 | case 'x': | |
3673 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3674 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3675 | break; | |
3676 | } | |
252b5132 | 3677 | |
9306ca4a | 3678 | return 1; |
252b5132 RH |
3679 | } |
3680 | ||
9a182d04 JB |
3681 | static INLINE void |
3682 | install_template (const insn_template *t) | |
3683 | { | |
3684 | unsigned int l; | |
3685 | ||
3686 | i.tm = *t; | |
3687 | ||
a6f3add0 JB |
3688 | /* Dual VEX/EVEX templates need stripping one of the possible variants. */ |
3689 | if (t->opcode_modifier.vex && t->opcode_modifier.evex) | |
6177c84d | 3690 | { |
a5e91879 JB |
3691 | if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2) |
3692 | || maybe_cpu (t, CpuFMA)) | |
3693 | && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL))) | |
a6f3add0 | 3694 | { |
6177c84d | 3695 | if (need_evex_encoding (t)) |
a6f3add0 JB |
3696 | { |
3697 | i.tm.opcode_modifier.vex = 0; | |
a5e91879 JB |
3698 | i.tm.cpu.bitfield.cpuavx512f = i.tm.cpu_any.bitfield.cpuavx512f; |
3699 | i.tm.cpu.bitfield.cpuavx512vl = i.tm.cpu_any.bitfield.cpuavx512vl; | |
a6f3add0 JB |
3700 | } |
3701 | else | |
3702 | { | |
3703 | i.tm.opcode_modifier.evex = 0; | |
a5e91879 JB |
3704 | if (i.tm.cpu_any.bitfield.cpuavx) |
3705 | i.tm.cpu.bitfield.cpuavx = 1; | |
3706 | else if (!i.tm.cpu.bitfield.isa) | |
3707 | i.tm.cpu.bitfield.isa = i.tm.cpu_any.bitfield.isa; | |
3708 | else | |
3709 | gas_assert (i.tm.cpu.bitfield.isa == i.tm.cpu_any.bitfield.isa); | |
a6f3add0 JB |
3710 | } |
3711 | } | |
6177c84d CL |
3712 | |
3713 | if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE) | |
3714 | || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ) | |
3715 | || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI) | |
3716 | || maybe_cpu (t, CpuBMI2)) | |
3717 | && maybe_cpu (t, CpuAPX_F)) | |
3718 | { | |
3719 | if (need_evex_encoding (t)) | |
3720 | i.tm.opcode_modifier.vex = 0; | |
3721 | else | |
3722 | i.tm.opcode_modifier.evex = 0; | |
3723 | } | |
3724 | } | |
a6f3add0 | 3725 | |
9a182d04 JB |
3726 | /* Note that for pseudo prefixes this produces a length of 1. But for them |
3727 | the length isn't interesting at all. */ | |
3728 | for (l = 1; l < 4; ++l) | |
3729 | if (!(t->base_opcode >> (8 * l))) | |
3730 | break; | |
3731 | ||
3732 | i.opcode_length = l; | |
3733 | } | |
3734 | ||
c0f3af97 L |
3735 | /* Build the VEX prefix. */ |
3736 | ||
3737 | static void | |
d3ce72d0 | 3738 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3739 | { |
3740 | unsigned int register_specifier; | |
c0f3af97 | 3741 | unsigned int vector_length; |
03751133 | 3742 | unsigned int w; |
c0f3af97 L |
3743 | |
3744 | /* Check register specifier. */ | |
3745 | if (i.vex.register_specifier) | |
43234a1e L |
3746 | { |
3747 | register_specifier = | |
3748 | ~register_number (i.vex.register_specifier) & 0xf; | |
3749 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3750 | } | |
c0f3af97 L |
3751 | else |
3752 | register_specifier = 0xf; | |
3753 | ||
79f0fa25 L |
3754 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3755 | if there are more than 1 register operand. */ | |
3756 | if (i.reg_operands > 1 | |
3757 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3758 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3759 | && i.operands == i.reg_operands |
dbbc8b7e | 3760 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
ddb62495 | 3761 | && i.tm.opcode_space == SPACE_0F |
dbbc8b7e | 3762 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3763 | && i.rex == REX_B) |
3764 | { | |
67748abf | 3765 | unsigned int xchg; |
fa99fab2 | 3766 | |
67748abf | 3767 | swap_2_operands (0, i.operands - 1); |
fa99fab2 | 3768 | |
9c2799c2 | 3769 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3770 | |
3771 | i.rex = REX_R; | |
3772 | xchg = i.rm.regmem; | |
3773 | i.rm.regmem = i.rm.reg; | |
3774 | i.rm.reg = xchg; | |
3775 | ||
dbbc8b7e JB |
3776 | if (i.tm.opcode_modifier.d) |
3777 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
2c735193 | 3778 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
dbbc8b7e | 3779 | else /* Use the next insn. */ |
9a182d04 | 3780 | install_template (&t[1]); |
fa99fab2 L |
3781 | } |
3782 | ||
79dec6b7 JB |
3783 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3784 | are no memory operands and at least 3 register ones. */ | |
3785 | if (i.reg_operands >= 3 | |
3786 | && i.vec_encoding != vex_encoding_vex3 | |
3787 | && i.reg_operands == i.operands - i.imm_operands | |
3788 | && i.tm.opcode_modifier.vex | |
3789 | && i.tm.opcode_modifier.commutative | |
33740f21 JB |
3790 | && (i.tm.opcode_modifier.sse2avx |
3791 | || (optimize > 1 && !i.no_optimize)) | |
79dec6b7 JB |
3792 | && i.rex == REX_B |
3793 | && i.vex.register_specifier | |
3794 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3795 | { | |
3796 | unsigned int xchg = i.operands - i.reg_operands; | |
79dec6b7 | 3797 | |
ddb62495 | 3798 | gas_assert (i.tm.opcode_space == SPACE_0F); |
79dec6b7 JB |
3799 | gas_assert (!i.tm.opcode_modifier.sae); |
3800 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3801 | &i.types[i.operands - 3])); | |
3802 | gas_assert (i.rm.mode == 3); | |
3803 | ||
67748abf | 3804 | swap_2_operands (xchg, xchg + 1); |
79dec6b7 JB |
3805 | |
3806 | i.rex = 0; | |
3807 | xchg = i.rm.regmem | 8; | |
3808 | i.rm.regmem = ~register_specifier & 0xf; | |
3809 | gas_assert (!(i.rm.regmem & 8)); | |
3810 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3811 | register_specifier = ~xchg & 0xf; | |
3812 | } | |
3813 | ||
539f890d L |
3814 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3815 | vector_length = avxscalar; | |
10c17abd JB |
3816 | else if (i.tm.opcode_modifier.vex == VEX256) |
3817 | vector_length = 1; | |
d0c2e3ec JB |
3818 | else if (dot_insn () && i.tm.opcode_modifier.vex == VEX128) |
3819 | vector_length = 0; | |
539f890d | 3820 | else |
10c17abd | 3821 | { |
56522fc5 | 3822 | unsigned int op; |
10c17abd | 3823 | |
c7213af9 L |
3824 | /* Determine vector length from the last multi-length vector |
3825 | operand. */ | |
10c17abd | 3826 | vector_length = 0; |
56522fc5 | 3827 | for (op = t->operands; op--;) |
10c17abd JB |
3828 | if (t->operand_types[op].bitfield.xmmword |
3829 | && t->operand_types[op].bitfield.ymmword | |
3830 | && i.types[op].bitfield.ymmword) | |
3831 | { | |
3832 | vector_length = 1; | |
3833 | break; | |
3834 | } | |
3835 | } | |
c0f3af97 | 3836 | |
03751133 L |
3837 | /* Check the REX.W bit and VEXW. */ |
3838 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3839 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3840 | else if (i.tm.opcode_modifier.vexw) | |
3841 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3842 | else | |
931d03b7 | 3843 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3844 | |
c0f3af97 | 3845 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3846 | if (w == 0 |
3847 | && i.vec_encoding != vex_encoding_vex3 | |
ddb62495 | 3848 | && i.tm.opcode_space == SPACE_0F |
c0f3af97 L |
3849 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3850 | { | |
3851 | /* 2-byte VEX prefix. */ | |
3852 | unsigned int r; | |
3853 | ||
3854 | i.vex.length = 2; | |
3855 | i.vex.bytes[0] = 0xc5; | |
3856 | ||
3857 | /* Check the REX.R bit. */ | |
3858 | r = (i.rex & REX_R) ? 0 : 1; | |
3859 | i.vex.bytes[1] = (r << 7 | |
3860 | | register_specifier << 3 | |
3861 | | vector_length << 2 | |
35648716 | 3862 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3863 | } |
3864 | else | |
3865 | { | |
3866 | /* 3-byte VEX prefix. */ | |
f88c9eb0 | 3867 | i.vex.length = 3; |
f88c9eb0 | 3868 | |
ddb62495 | 3869 | switch (i.tm.opcode_space) |
5dd85c99 | 3870 | { |
441f6aca JB |
3871 | case SPACE_0F: |
3872 | case SPACE_0F38: | |
3873 | case SPACE_0F3A: | |
8170af78 | 3874 | case SPACE_VEXMAP7: |
80de6e00 | 3875 | i.vex.bytes[0] = 0xc4; |
7f399153 | 3876 | break; |
441f6aca JB |
3877 | case SPACE_XOP08: |
3878 | case SPACE_XOP09: | |
3879 | case SPACE_XOP0A: | |
f88c9eb0 | 3880 | i.vex.bytes[0] = 0x8f; |
7f399153 L |
3881 | break; |
3882 | default: | |
3883 | abort (); | |
f88c9eb0 | 3884 | } |
c0f3af97 | 3885 | |
c0f3af97 L |
3886 | /* The high 3 bits of the second VEX byte are 1's compliment |
3887 | of RXB bits from REX. */ | |
d0c2e3ec JB |
3888 | i.vex.bytes[1] = ((~i.rex & 7) << 5) |
3889 | | (!dot_insn () ? i.tm.opcode_space | |
3890 | : i.insn_opcode_space); | |
c0f3af97 | 3891 | |
c0f3af97 L |
3892 | i.vex.bytes[2] = (w << 7 |
3893 | | register_specifier << 3 | |
3894 | | vector_length << 2 | |
35648716 | 3895 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3896 | } |
3897 | } | |
3898 | ||
5b7c81bd | 3899 | static INLINE bool |
7a8655d2 JB |
3900 | is_any_vex_encoding (const insn_template *t) |
3901 | { | |
706ce984 | 3902 | return t->opcode_modifier.vex || t->opcode_modifier.evex; |
7a8655d2 JB |
3903 | } |
3904 | ||
6177c84d CL |
3905 | /* We can use this function only when the current encoding is evex. */ |
3906 | static INLINE bool | |
3907 | is_apx_evex_encoding (void) | |
3908 | { | |
3909 | return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4 | |
3910 | || (i.vex.register_specifier | |
3911 | && (i.vex.register_specifier->reg_flags & RegRex2)); | |
3912 | } | |
3913 | ||
80d61d8d CL |
3914 | static INLINE bool |
3915 | is_apx_rex2_encoding (void) | |
3916 | { | |
ac32c879 CL |
3917 | return i.rex2 || i.rex2_encoding |
3918 | || i.tm.opcode_modifier.operandconstraint == REX2_REQUIRED; | |
80d61d8d CL |
3919 | } |
3920 | ||
a5748e0d JB |
3921 | static unsigned int |
3922 | get_broadcast_bytes (const insn_template *t, bool diag) | |
3923 | { | |
3924 | unsigned int op, bytes; | |
3925 | const i386_operand_type *types; | |
3926 | ||
3927 | if (i.broadcast.type) | |
9b345ce8 | 3928 | return (1 << (t->opcode_modifier.broadcast - 1)) * i.broadcast.type; |
a5748e0d JB |
3929 | |
3930 | gas_assert (intel_syntax); | |
3931 | ||
3932 | for (op = 0; op < t->operands; ++op) | |
3933 | if (t->operand_types[op].bitfield.baseindex) | |
3934 | break; | |
3935 | ||
3936 | gas_assert (op < t->operands); | |
3937 | ||
706ce984 | 3938 | if (t->opcode_modifier.evex != EVEXDYN) |
a5748e0d JB |
3939 | switch (i.broadcast.bytes) |
3940 | { | |
3941 | case 1: | |
3942 | if (t->operand_types[op].bitfield.word) | |
3943 | return 2; | |
3944 | /* Fall through. */ | |
3945 | case 2: | |
3946 | if (t->operand_types[op].bitfield.dword) | |
3947 | return 4; | |
3948 | /* Fall through. */ | |
3949 | case 4: | |
3950 | if (t->operand_types[op].bitfield.qword) | |
3951 | return 8; | |
3952 | /* Fall through. */ | |
3953 | case 8: | |
3954 | if (t->operand_types[op].bitfield.xmmword) | |
3955 | return 16; | |
3956 | if (t->operand_types[op].bitfield.ymmword) | |
3957 | return 32; | |
3958 | if (t->operand_types[op].bitfield.zmmword) | |
3959 | return 64; | |
3960 | /* Fall through. */ | |
3961 | default: | |
3962 | abort (); | |
3963 | } | |
3964 | ||
3965 | gas_assert (op + 1 < t->operands); | |
3966 | ||
3967 | if (t->operand_types[op + 1].bitfield.xmmword | |
3968 | + t->operand_types[op + 1].bitfield.ymmword | |
3969 | + t->operand_types[op + 1].bitfield.zmmword > 1) | |
3970 | { | |
3971 | types = &i.types[op + 1]; | |
3972 | diag = false; | |
3973 | } | |
3974 | else /* Ambiguous - guess with a preference to non-AVX512VL forms. */ | |
3975 | types = &t->operand_types[op]; | |
3976 | ||
3977 | if (types->bitfield.zmmword) | |
3978 | bytes = 64; | |
3979 | else if (types->bitfield.ymmword) | |
3980 | bytes = 32; | |
3981 | else | |
3982 | bytes = 16; | |
3983 | ||
3984 | if (diag) | |
3985 | as_warn (_("ambiguous broadcast for `%s', using %u-bit form"), | |
76d3f746 | 3986 | insn_name (t), bytes * 8); |
a5748e0d JB |
3987 | |
3988 | return bytes; | |
3989 | } | |
3990 | ||
43234a1e L |
3991 | /* Build the EVEX prefix. */ |
3992 | ||
3993 | static void | |
3994 | build_evex_prefix (void) | |
3995 | { | |
35648716 | 3996 | unsigned int register_specifier, w; |
43234a1e L |
3997 | rex_byte vrex_used = 0; |
3998 | ||
3999 | /* Check register specifier. */ | |
4000 | if (i.vex.register_specifier) | |
4001 | { | |
4002 | gas_assert ((i.vrex & REX_X) == 0); | |
4003 | ||
4004 | register_specifier = i.vex.register_specifier->reg_num; | |
4005 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
4006 | register_specifier += 8; | |
4007 | /* The upper 16 registers are encoded in the fourth byte of the | |
4008 | EVEX prefix. */ | |
4009 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
4010 | i.vex.bytes[3] = 0x8; | |
4011 | register_specifier = ~register_specifier & 0xf; | |
4012 | } | |
4013 | else | |
4014 | { | |
4015 | register_specifier = 0xf; | |
4016 | ||
4017 | /* Encode upper 16 vector index register in the fourth byte of | |
4018 | the EVEX prefix. */ | |
4019 | if (!(i.vrex & REX_X)) | |
4020 | i.vex.bytes[3] = 0x8; | |
4021 | else | |
4022 | vrex_used |= REX_X; | |
4023 | } | |
4024 | ||
43234a1e L |
4025 | /* 4 byte EVEX prefix. */ |
4026 | i.vex.length = 4; | |
4027 | i.vex.bytes[0] = 0x62; | |
4028 | ||
43234a1e L |
4029 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
4030 | bits from REX. */ | |
ddb62495 JB |
4031 | gas_assert (i.tm.opcode_space >= SPACE_0F); |
4032 | gas_assert (i.tm.opcode_space <= SPACE_EVEXMAP6); | |
d0c2e3ec JB |
4033 | i.vex.bytes[1] = ((~i.rex & 7) << 5) |
4034 | | (!dot_insn () ? i.tm.opcode_space | |
4035 | : i.insn_opcode_space); | |
43234a1e L |
4036 | |
4037 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
4038 | REX_R bit in VREX. */ | |
4039 | if (!(i.vrex & REX_R)) | |
4040 | i.vex.bytes[1] |= 0x10; | |
4041 | else | |
4042 | vrex_used |= REX_R; | |
4043 | ||
4044 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
4045 | { | |
4046 | /* When all operands are registers, the REX_X bit in REX is not | |
4047 | used. We reuse it to encode the upper 16 registers, which is | |
4048 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
4049 | as 1's compliment. */ | |
4050 | if ((i.vrex & REX_B)) | |
4051 | { | |
4052 | vrex_used |= REX_B; | |
4053 | i.vex.bytes[1] &= ~0x40; | |
4054 | } | |
4055 | } | |
4056 | ||
4057 | /* EVEX instructions shouldn't need the REX prefix. */ | |
4058 | i.vrex &= ~vrex_used; | |
4059 | gas_assert (i.vrex == 0); | |
4060 | ||
6865c043 L |
4061 | /* Check the REX.W bit and VEXW. */ |
4062 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
4063 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
4064 | else if (i.tm.opcode_modifier.vexw) | |
4065 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
4066 | else | |
931d03b7 | 4067 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e | 4068 | |
43234a1e | 4069 | /* The third byte of the EVEX prefix. */ |
35648716 JB |
4070 | i.vex.bytes[2] = ((w << 7) |
4071 | | (register_specifier << 3) | |
4072 | | 4 /* Encode the U bit. */ | |
4073 | | i.tm.opcode_modifier.opcodeprefix); | |
43234a1e L |
4074 | |
4075 | /* The fourth byte of the EVEX prefix. */ | |
4076 | /* The zeroing-masking bit. */ | |
6225c532 | 4077 | if (i.mask.reg && i.mask.zeroing) |
43234a1e L |
4078 | i.vex.bytes[3] |= 0x80; |
4079 | ||
4080 | /* Don't always set the broadcast bit if there is no RC. */ | |
ca5312a2 | 4081 | if (i.rounding.type == rc_none) |
43234a1e L |
4082 | { |
4083 | /* Encode the vector length. */ | |
4084 | unsigned int vec_length; | |
4085 | ||
706ce984 | 4086 | if (i.tm.opcode_modifier.evex == EVEXDYN) |
e771e7c9 | 4087 | { |
56522fc5 | 4088 | unsigned int op; |
e771e7c9 | 4089 | |
c7213af9 L |
4090 | /* Determine vector length from the last multi-length vector |
4091 | operand. */ | |
56522fc5 | 4092 | for (op = i.operands; op--;) |
e771e7c9 JB |
4093 | if (i.tm.operand_types[op].bitfield.xmmword |
4094 | + i.tm.operand_types[op].bitfield.ymmword | |
4095 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
4096 | { | |
4097 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
4098 | { |
4099 | i.tm.opcode_modifier.evex = EVEX512; | |
4100 | break; | |
4101 | } | |
e771e7c9 | 4102 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
4103 | { |
4104 | i.tm.opcode_modifier.evex = EVEX256; | |
4105 | break; | |
4106 | } | |
e771e7c9 | 4107 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
4108 | { |
4109 | i.tm.opcode_modifier.evex = EVEX128; | |
4110 | break; | |
4111 | } | |
9b345ce8 JB |
4112 | else if ((i.broadcast.type || i.broadcast.bytes) |
4113 | && op == i.broadcast.operand) | |
625cbd7a | 4114 | { |
a5748e0d | 4115 | switch (get_broadcast_bytes (&i.tm, true)) |
625cbd7a JB |
4116 | { |
4117 | case 64: | |
4118 | i.tm.opcode_modifier.evex = EVEX512; | |
4119 | break; | |
4120 | case 32: | |
4121 | i.tm.opcode_modifier.evex = EVEX256; | |
4122 | break; | |
4123 | case 16: | |
4124 | i.tm.opcode_modifier.evex = EVEX128; | |
4125 | break; | |
4126 | default: | |
c7213af9 | 4127 | abort (); |
625cbd7a | 4128 | } |
c7213af9 | 4129 | break; |
625cbd7a | 4130 | } |
e771e7c9 | 4131 | } |
c7213af9 | 4132 | |
56522fc5 | 4133 | if (op >= MAX_OPERANDS) |
c7213af9 | 4134 | abort (); |
e771e7c9 JB |
4135 | } |
4136 | ||
43234a1e L |
4137 | switch (i.tm.opcode_modifier.evex) |
4138 | { | |
4139 | case EVEXLIG: /* LL' is ignored */ | |
4140 | vec_length = evexlig << 5; | |
4141 | break; | |
4142 | case EVEX128: | |
4143 | vec_length = 0 << 5; | |
4144 | break; | |
4145 | case EVEX256: | |
4146 | vec_length = 1 << 5; | |
4147 | break; | |
4148 | case EVEX512: | |
4149 | vec_length = 2 << 5; | |
4150 | break; | |
d0c2e3ec JB |
4151 | case EVEX_L3: |
4152 | if (dot_insn ()) | |
4153 | { | |
4154 | vec_length = 3 << 5; | |
4155 | break; | |
4156 | } | |
4157 | /* Fall through. */ | |
43234a1e L |
4158 | default: |
4159 | abort (); | |
4160 | break; | |
4161 | } | |
4162 | i.vex.bytes[3] |= vec_length; | |
4163 | /* Encode the broadcast bit. */ | |
9b345ce8 | 4164 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e L |
4165 | i.vex.bytes[3] |= 0x10; |
4166 | } | |
ca5312a2 JB |
4167 | else if (i.rounding.type != saeonly) |
4168 | i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5); | |
43234a1e | 4169 | else |
ca5312a2 | 4170 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e | 4171 | |
6225c532 JB |
4172 | if (i.mask.reg) |
4173 | i.vex.bytes[3] |= i.mask.reg->reg_num; | |
43234a1e L |
4174 | } |
4175 | ||
80d61d8d CL |
4176 | /* Build (2 bytes) rex2 prefix. |
4177 | | D5h | | |
4178 | | m | R4 X4 B4 | W R X B | | |
4179 | ||
4180 | Rex2 reuses i.vex as they both encode i.tm.opcode_space in their prefixes. | |
4181 | */ | |
4182 | static void | |
4183 | build_rex2_prefix (void) | |
4184 | { | |
4185 | i.vex.length = 2; | |
4186 | i.vex.bytes[0] = 0xd5; | |
4187 | /* For the W R X B bits, the variables of rex prefix will be reused. */ | |
4188 | i.vex.bytes[1] = ((i.tm.opcode_space << 7) | |
4189 | | (i.rex2 << 4) | i.rex); | |
4190 | } | |
4191 | ||
6177c84d CL |
4192 | /* Build the EVEX prefix (4-byte) for evex insn |
4193 | | 62h | | |
4194 | | `R`X`B`R' | B'mmm | | |
4195 | | W | v`v`v`v | `x' | pp | | |
4196 | | z| L'L | b | `v | aaa | | |
4197 | */ | |
4198 | static void | |
4199 | build_apx_evex_prefix (void) | |
4200 | { | |
4201 | build_evex_prefix (); | |
4202 | if (i.rex2 & REX_R) | |
4203 | i.vex.bytes[1] &= ~0x10; | |
4204 | if (i.rex2 & REX_B) | |
4205 | i.vex.bytes[1] |= 0x08; | |
4206 | if (i.rex2 & REX_X) | |
4207 | i.vex.bytes[2] &= ~0x04; | |
4208 | if (i.vex.register_specifier | |
4209 | && i.vex.register_specifier->reg_flags & RegRex2) | |
4210 | i.vex.bytes[3] &= ~0x08; | |
3083f376 | 4211 | |
4212 | /* Encode the NDD bit of the instruction promoted from the legacy | |
4213 | space. */ | |
4214 | if (i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4) | |
4215 | i.vex.bytes[3] |= 0x10; | |
6177c84d CL |
4216 | } |
4217 | ||
ce705688 JB |
4218 | static void establish_rex (void) |
4219 | { | |
4220 | /* Note that legacy encodings have at most 2 non-immediate operands. */ | |
4221 | unsigned int first = i.imm_operands; | |
4222 | unsigned int last = i.operands > first ? i.operands - first - 1 : first; | |
4223 | ||
4224 | /* Respect a user-specified REX prefix. */ | |
4225 | i.rex |= i.prefix[REX_PREFIX] & REX_OPCODE; | |
4226 | ||
4227 | /* For 8 bit registers we need an empty rex prefix. Also if the | |
4228 | instruction already has a prefix, we need to convert old | |
4229 | registers to new ones. */ | |
4230 | ||
4231 | if ((i.types[first].bitfield.class == Reg && i.types[first].bitfield.byte | |
80d61d8d CL |
4232 | && ((i.op[first].regs->reg_flags & RegRex64) != 0 || i.rex != 0 |
4233 | || i.rex2 != 0)) | |
ce705688 | 4234 | || (i.types[last].bitfield.class == Reg && i.types[last].bitfield.byte |
80d61d8d CL |
4235 | && ((i.op[last].regs->reg_flags & RegRex64) != 0 || i.rex != 0 |
4236 | || i.rex2 != 0))) | |
ce705688 JB |
4237 | { |
4238 | unsigned int x; | |
4239 | ||
80d61d8d CL |
4240 | if (!is_apx_rex2_encoding () && !is_any_vex_encoding(&i.tm)) |
4241 | i.rex |= REX_OPCODE; | |
ce705688 JB |
4242 | for (x = first; x <= last; x++) |
4243 | { | |
4244 | /* Look for 8 bit operand that uses old registers. */ | |
4245 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte | |
4246 | && (i.op[x].regs->reg_flags & RegRex64) == 0) | |
4247 | { | |
4248 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); | |
4249 | /* In case it is "hi" register, give up. */ | |
4250 | if (i.op[x].regs->reg_num > 3) | |
4251 | as_bad (_("can't encode register '%s%s' in an " | |
80d61d8d | 4252 | "instruction requiring REX/REX2 prefix"), |
ce705688 JB |
4253 | register_prefix, i.op[x].regs->reg_name); |
4254 | ||
4255 | /* Otherwise it is equivalent to the extended register. | |
4256 | Since the encoding doesn't change this is merely | |
4257 | cosmetic cleanup for debug output. */ | |
4258 | i.op[x].regs += 8; | |
4259 | } | |
4260 | } | |
4261 | } | |
4262 | ||
80d61d8d | 4263 | if (i.rex == 0 && i.rex2 == 0 && (i.rex_encoding || i.rex2_encoding)) |
ce705688 JB |
4264 | { |
4265 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4266 | that uses legacy register. If it is "hi" register, don't add | |
80d61d8d | 4267 | rex and rex2 prefix. */ |
ce705688 JB |
4268 | unsigned int x; |
4269 | ||
4270 | for (x = first; x <= last; x++) | |
4271 | if (i.types[x].bitfield.class == Reg | |
4272 | && i.types[x].bitfield.byte | |
4273 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4274 | && i.op[x].regs->reg_num > 3) | |
4275 | { | |
4276 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); | |
4277 | i.rex_encoding = false; | |
80d61d8d | 4278 | i.rex2_encoding = false; |
ce705688 JB |
4279 | break; |
4280 | } | |
4281 | ||
4282 | if (i.rex_encoding) | |
4283 | i.rex = REX_OPCODE; | |
4284 | } | |
4285 | ||
80d61d8d CL |
4286 | if (is_apx_rex2_encoding ()) |
4287 | { | |
4288 | build_rex2_prefix (); | |
4289 | /* The individual REX.RXBW bits got consumed. */ | |
4290 | i.rex &= REX_OPCODE; | |
4291 | } | |
4292 | else if (i.rex != 0) | |
4293 | add_prefix (REX_OPCODE | i.rex); | |
ce705688 JB |
4294 | } |
4295 | ||
65da13b5 L |
4296 | static void |
4297 | process_immext (void) | |
4298 | { | |
4299 | expressionS *exp; | |
4300 | ||
c0f3af97 | 4301 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
4302 | which is coded in the same place as an 8-bit immediate field |
4303 | would be. Here we fake an 8-bit immediate operand from the | |
4304 | opcode suffix stored in tm.extension_opcode. | |
4305 | ||
c1e679ec | 4306 | AVX instructions also use this encoding, for some of |
c0f3af97 | 4307 | 3 argument instructions. */ |
65da13b5 | 4308 | |
43234a1e | 4309 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 4310 | && (i.operands <= 2 |
7a8655d2 | 4311 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 4312 | && i.operands <= 4))); |
65da13b5 L |
4313 | |
4314 | exp = &im_expressions[i.imm_operands++]; | |
4315 | i.op[i.operands].imms = exp; | |
be1643ff | 4316 | i.types[i.operands].bitfield.imm8 = 1; |
65da13b5 L |
4317 | i.operands++; |
4318 | exp->X_op = O_constant; | |
4319 | exp->X_add_number = i.tm.extension_opcode; | |
4320 | i.tm.extension_opcode = None; | |
4321 | } | |
4322 | ||
42164a71 L |
4323 | |
4324 | static int | |
4325 | check_hle (void) | |
4326 | { | |
742732c7 | 4327 | switch (i.tm.opcode_modifier.prefixok) |
42164a71 L |
4328 | { |
4329 | default: | |
4330 | abort (); | |
742732c7 JB |
4331 | case PrefixLock: |
4332 | case PrefixNone: | |
4333 | case PrefixNoTrack: | |
4334 | case PrefixRep: | |
165de32a | 4335 | as_bad (_("invalid instruction `%s' after `%s'"), |
76d3f746 | 4336 | insn_name (&i.tm), i.hle_prefix); |
42164a71 | 4337 | return 0; |
742732c7 | 4338 | case PrefixHLELock: |
42164a71 L |
4339 | if (i.prefix[LOCK_PREFIX]) |
4340 | return 1; | |
165de32a | 4341 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4342 | return 0; |
742732c7 | 4343 | case PrefixHLEAny: |
42164a71 | 4344 | return 1; |
742732c7 | 4345 | case PrefixHLERelease: |
42164a71 L |
4346 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4347 | { | |
4348 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
76d3f746 | 4349 | insn_name (&i.tm)); |
42164a71 L |
4350 | return 0; |
4351 | } | |
8dc0818e | 4352 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4353 | { |
4354 | as_bad (_("memory destination needed for instruction `%s'" | |
76d3f746 | 4355 | " after `xrelease'"), insn_name (&i.tm)); |
42164a71 L |
4356 | return 0; |
4357 | } | |
4358 | return 1; | |
4359 | } | |
4360 | } | |
4361 | ||
c8480b58 L |
4362 | /* Encode aligned vector move as unaligned vector move. */ |
4363 | ||
4364 | static void | |
4365 | encode_with_unaligned_vector_move (void) | |
4366 | { | |
4367 | switch (i.tm.base_opcode) | |
4368 | { | |
b3a9fe6f L |
4369 | case 0x28: /* Load instructions. */ |
4370 | case 0x29: /* Store instructions. */ | |
c8480b58 | 4371 | /* movaps/movapd/vmovaps/vmovapd. */ |
ddb62495 | 4372 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 | 4373 | && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66) |
b3a9fe6f | 4374 | i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1); |
c8480b58 | 4375 | break; |
b3a9fe6f L |
4376 | case 0x6f: /* Load instructions. */ |
4377 | case 0x7f: /* Store instructions. */ | |
c8480b58 | 4378 | /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */ |
ddb62495 | 4379 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 L |
4380 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66) |
4381 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
4382 | break; | |
4383 | default: | |
4384 | break; | |
4385 | } | |
4386 | } | |
4387 | ||
b6f8c7c4 L |
4388 | /* Try the shortest encoding by shortening operand size. */ |
4389 | ||
4390 | static void | |
4391 | optimize_encoding (void) | |
4392 | { | |
a0a1771e | 4393 | unsigned int j; |
b6f8c7c4 | 4394 | |
7fc69528 | 4395 | if (i.tm.mnem_off == MN_lea) |
fe134c65 JB |
4396 | { |
4397 | /* Optimize: -O: | |
4398 | lea symbol, %rN -> mov $symbol, %rN | |
4399 | lea (%rM), %rN -> mov %rM, %rN | |
4400 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4401 | ||
4402 | and in 32-bit mode for 16-bit addressing | |
4403 | ||
4404 | lea (%rM), %rN -> movzx %rM, %rN | |
4405 | ||
4406 | and in 64-bit mode zap 32-bit addressing in favor of using a | |
4407 | 32-bit (or less) destination. | |
4408 | */ | |
4409 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4410 | { | |
4411 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4412 | i.tm.opcode_modifier.size = SIZE32; | |
4413 | i.prefix[ADDR_PREFIX] = 0; | |
4414 | } | |
4415 | ||
4416 | if (!i.index_reg && !i.base_reg) | |
4417 | { | |
4418 | /* Handle: | |
4419 | lea symbol, %rN -> mov $symbol, %rN | |
4420 | */ | |
4421 | if (flag_code == CODE_64BIT) | |
4422 | { | |
4423 | /* Don't transform a relocation to a 16-bit one. */ | |
4424 | if (i.op[0].disps | |
4425 | && i.op[0].disps->X_op != O_constant | |
4426 | && i.op[1].regs->reg_type.bitfield.word) | |
4427 | return; | |
4428 | ||
4429 | if (!i.op[1].regs->reg_type.bitfield.qword | |
4430 | || i.tm.opcode_modifier.size == SIZE32) | |
4431 | { | |
4432 | i.tm.base_opcode = 0xb8; | |
4433 | i.tm.opcode_modifier.modrm = 0; | |
4434 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4435 | i.types[0].bitfield.imm32 = 1; | |
4436 | else | |
4437 | { | |
4438 | i.tm.opcode_modifier.size = SIZE16; | |
4439 | i.types[0].bitfield.imm16 = 1; | |
4440 | } | |
4441 | } | |
4442 | else | |
4443 | { | |
4444 | /* Subject to further optimization below. */ | |
4445 | i.tm.base_opcode = 0xc7; | |
4446 | i.tm.extension_opcode = 0; | |
4447 | i.types[0].bitfield.imm32s = 1; | |
4448 | i.types[0].bitfield.baseindex = 0; | |
4449 | } | |
4450 | } | |
4451 | /* Outside of 64-bit mode address and operand sizes have to match if | |
4452 | a relocation is involved, as otherwise we wouldn't (currently) or | |
4453 | even couldn't express the relocation correctly. */ | |
4454 | else if (i.op[0].disps | |
4455 | && i.op[0].disps->X_op != O_constant | |
4456 | && ((!i.prefix[ADDR_PREFIX]) | |
4457 | != (flag_code == CODE_32BIT | |
4458 | ? i.op[1].regs->reg_type.bitfield.dword | |
4459 | : i.op[1].regs->reg_type.bitfield.word))) | |
4460 | return; | |
7772f168 JB |
4461 | /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit |
4462 | destination is going to grow encoding size. */ | |
4463 | else if (flag_code == CODE_16BIT | |
4464 | && (optimize <= 1 || optimize_for_space) | |
4465 | && !i.prefix[ADDR_PREFIX] | |
4466 | && i.op[1].regs->reg_type.bitfield.dword) | |
4467 | return; | |
fe134c65 JB |
4468 | else |
4469 | { | |
4470 | i.tm.base_opcode = 0xb8; | |
4471 | i.tm.opcode_modifier.modrm = 0; | |
4472 | if (i.op[1].regs->reg_type.bitfield.dword) | |
4473 | i.types[0].bitfield.imm32 = 1; | |
4474 | else | |
4475 | i.types[0].bitfield.imm16 = 1; | |
4476 | ||
4477 | if (i.op[0].disps | |
4478 | && i.op[0].disps->X_op == O_constant | |
4479 | && i.op[1].regs->reg_type.bitfield.dword | |
60cfa10c L |
4480 | /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence |
4481 | GCC 5. */ | |
4482 | && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT)) | |
fe134c65 JB |
4483 | i.op[0].disps->X_add_number &= 0xffff; |
4484 | } | |
4485 | ||
4486 | i.tm.operand_types[0] = i.types[0]; | |
4487 | i.imm_operands = 1; | |
4488 | if (!i.op[0].imms) | |
4489 | { | |
4490 | i.op[0].imms = &im_expressions[0]; | |
4491 | i.op[0].imms->X_op = O_absent; | |
4492 | } | |
4493 | } | |
4494 | else if (i.op[0].disps | |
4495 | && (i.op[0].disps->X_op != O_constant | |
4496 | || i.op[0].disps->X_add_number)) | |
4497 | return; | |
4498 | else | |
4499 | { | |
4500 | /* Handle: | |
4501 | lea (%rM), %rN -> mov %rM, %rN | |
4502 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4503 | lea (%rM), %rN -> movzx %rM, %rN | |
4504 | */ | |
4505 | const reg_entry *addr_reg; | |
4506 | ||
4507 | if (!i.index_reg && i.base_reg->reg_num != RegIP) | |
4508 | addr_reg = i.base_reg; | |
4509 | else if (!i.base_reg | |
4510 | && i.index_reg->reg_num != RegIZ | |
4511 | && !i.log2_scale_factor) | |
4512 | addr_reg = i.index_reg; | |
4513 | else | |
4514 | return; | |
4515 | ||
4516 | if (addr_reg->reg_type.bitfield.word | |
4517 | && i.op[1].regs->reg_type.bitfield.dword) | |
4518 | { | |
4519 | if (flag_code != CODE_32BIT) | |
4520 | return; | |
ddb62495 | 4521 | i.tm.opcode_space = SPACE_0F; |
fe134c65 JB |
4522 | i.tm.base_opcode = 0xb7; |
4523 | } | |
4524 | else | |
4525 | i.tm.base_opcode = 0x8b; | |
4526 | ||
4527 | if (addr_reg->reg_type.bitfield.dword | |
4528 | && i.op[1].regs->reg_type.bitfield.qword) | |
4529 | i.tm.opcode_modifier.size = SIZE32; | |
4530 | ||
4531 | i.op[0].regs = addr_reg; | |
4532 | i.reg_operands = 2; | |
4533 | } | |
4534 | ||
4535 | i.mem_operands = 0; | |
4536 | i.disp_operands = 0; | |
4537 | i.prefix[ADDR_PREFIX] = 0; | |
4538 | i.prefix[SEG_PREFIX] = 0; | |
4539 | i.seg[0] = NULL; | |
4540 | } | |
4541 | ||
b6f8c7c4 | 4542 | if (optimize_for_space |
7fc69528 | 4543 | && i.tm.mnem_off == MN_test |
b6f8c7c4 L |
4544 | && i.reg_operands == 1 |
4545 | && i.imm_operands == 1 | |
4546 | && !i.types[1].bitfield.byte | |
4547 | && i.op[0].imms->X_op == O_constant | |
7fc69528 | 4548 | && fits_in_imm7 (i.op[0].imms->X_add_number)) |
b6f8c7c4 L |
4549 | { |
4550 | /* Optimize: -Os: | |
4551 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4552 | */ | |
4553 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4554 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4555 | { | |
4556 | i.types[1].bitfield.byte = 1; | |
4557 | /* Ignore the suffix. */ | |
4558 | i.suffix = 0; | |
80d61d8d CL |
4559 | /* Convert to byte registers. 8-bit registers are special, |
4560 | RegRex64 and non-RegRex64 each have 8 registers. */ | |
7697afb6 | 4561 | if (i.types[1].bitfield.word) |
80d61d8d | 4562 | /* 32 (or 40) 8-bit registers. */ |
7697afb6 | 4563 | j = 32; |
80d61d8d CL |
4564 | else if (i.types[1].bitfield.dword) |
4565 | /* 32 (or 40) 8-bit registers + 32 16-bit registers. */ | |
4566 | j = 64; | |
7697afb6 | 4567 | else |
80d61d8d CL |
4568 | /* 32 (or 40) 8-bit registers + 32 16-bit registers |
4569 | + 32 32-bit registers. */ | |
4570 | j = 96; | |
4571 | ||
4572 | /* In 64-bit mode, the following byte registers cannot be accessed | |
4573 | if using the Rex and Rex2 prefix: AH, BH, CH, DH */ | |
4574 | if (!(i.op[1].regs->reg_flags & (RegRex | RegRex2)) && base_regnum < 4) | |
7697afb6 JB |
4575 | j += 8; |
4576 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4577 | } |
4578 | } | |
4579 | else if (flag_code == CODE_64BIT | |
ddb62495 | 4580 | && i.tm.opcode_space == SPACE_BASE |
d3d50934 L |
4581 | && ((i.types[1].bitfield.qword |
4582 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4583 | && i.imm_operands == 1 |
4584 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4585 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4586 | && i.tm.extension_opcode == None |
4587 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4588 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
7fc69528 | 4589 | && (i.tm.base_opcode == 0x24 |
b6f8c7c4 L |
4590 | || (i.tm.base_opcode == 0x80 |
4591 | && i.tm.extension_opcode == 0x4) | |
7fc69528 JB |
4592 | || i.tm.mnem_off == MN_test |
4593 | || ((i.tm.base_opcode | 1) == 0xc7 | |
b8364fa7 JB |
4594 | && i.tm.extension_opcode == 0x0))) |
4595 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4596 | && i.tm.base_opcode == 0x83 | |
4597 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4598 | || (i.types[0].bitfield.qword |
4599 | && ((i.reg_operands == 2 | |
4600 | && i.op[0].regs == i.op[1].regs | |
7fc69528 JB |
4601 | && (i.tm.mnem_off == MN_xor |
4602 | || i.tm.mnem_off == MN_sub)) | |
4603 | || i.tm.mnem_off == MN_clr)))) | |
b6f8c7c4 L |
4604 | { |
4605 | /* Optimize: -O: | |
4606 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4607 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4608 | testq $imm31, %r64 -> testl $imm31, %r32 |
4609 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4610 | subq %r64, %r64 -> subl %r32, %r32 | |
4611 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4612 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4613 | */ | |
04784e33 JB |
4614 | i.tm.opcode_modifier.size = SIZE32; |
4615 | if (i.imm_operands) | |
4616 | { | |
4617 | i.types[0].bitfield.imm32 = 1; | |
4618 | i.types[0].bitfield.imm32s = 0; | |
4619 | i.types[0].bitfield.imm64 = 0; | |
4620 | } | |
4621 | else | |
4622 | { | |
4623 | i.types[0].bitfield.dword = 1; | |
4624 | i.types[0].bitfield.qword = 0; | |
4625 | } | |
4626 | i.types[1].bitfield.dword = 1; | |
4627 | i.types[1].bitfield.qword = 0; | |
7fc69528 | 4628 | if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea) |
b6f8c7c4 L |
4629 | { |
4630 | /* Handle | |
4631 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4632 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4633 | */ | |
4634 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4635 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4636 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
507916b8 | 4637 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4638 | { |
4639 | /* Handle | |
4640 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4641 | */ | |
507916b8 | 4642 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4643 | i.tm.extension_opcode = None; |
507916b8 | 4644 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4645 | i.tm.opcode_modifier.modrm = 0; |
4646 | } | |
4647 | } | |
4648 | } | |
5641ec01 JB |
4649 | else if (optimize > 1 |
4650 | && !optimize_for_space | |
4651 | && i.reg_operands == 2 | |
4652 | && i.op[0].regs == i.op[1].regs | |
7fc69528 | 4653 | && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or) |
5641ec01 JB |
4654 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) |
4655 | { | |
4656 | /* Optimize: -O2: | |
4657 | andb %rN, %rN -> testb %rN, %rN | |
4658 | andw %rN, %rN -> testw %rN, %rN | |
4659 | andq %rN, %rN -> testq %rN, %rN | |
4660 | orb %rN, %rN -> testb %rN, %rN | |
4661 | orw %rN, %rN -> testw %rN, %rN | |
4662 | orq %rN, %rN -> testq %rN, %rN | |
4663 | ||
4664 | and outside of 64-bit mode | |
4665 | ||
4666 | andl %rN, %rN -> testl %rN, %rN | |
4667 | orl %rN, %rN -> testl %rN, %rN | |
4668 | */ | |
4669 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4670 | } | |
ad2f4436 JB |
4671 | else if (i.tm.base_opcode == 0xba |
4672 | && i.tm.opcode_space == SPACE_0F | |
4673 | && i.reg_operands == 1 | |
4674 | && i.op[0].imms->X_op == O_constant | |
4675 | && i.op[0].imms->X_add_number >= 0) | |
4676 | { | |
4677 | /* Optimize: -O: | |
4678 | btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16) | |
4679 | btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8) | |
4680 | btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4681 | ||
4682 | With <BT> one of bts, btr, and bts also: | |
4683 | <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16) | |
4684 | <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4685 | */ | |
4686 | switch (flag_code) | |
4687 | { | |
4688 | case CODE_64BIT: | |
4689 | if (i.tm.extension_opcode != 4) | |
4690 | break; | |
4691 | if (i.types[1].bitfield.qword | |
4692 | && i.op[0].imms->X_add_number < 32 | |
4693 | && !(i.op[1].regs->reg_flags & RegRex)) | |
4694 | i.tm.opcode_modifier.size = SIZE32; | |
4695 | /* Fall through. */ | |
4696 | case CODE_32BIT: | |
4697 | if (i.types[1].bitfield.word | |
4698 | && i.op[0].imms->X_add_number < 16) | |
4699 | i.tm.opcode_modifier.size = SIZE32; | |
4700 | break; | |
4701 | case CODE_16BIT: | |
4702 | if (i.op[0].imms->X_add_number < 16) | |
4703 | i.tm.opcode_modifier.size = SIZE16; | |
4704 | break; | |
4705 | } | |
4706 | } | |
99112332 | 4707 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4708 | && i.op[0].regs == i.op[1].regs |
4709 | && !i.types[2].bitfield.xmmword | |
4710 | && (i.tm.opcode_modifier.vex | |
6225c532 | 4711 | || ((!i.mask.reg || i.mask.zeroing) |
706ce984 | 4712 | && i.tm.opcode_modifier.evex |
80c34c38 | 4713 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4714 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
734dfd1c | 4715 | || is_cpu (&i.tm, CpuAVX512VL) |
7091c612 | 4716 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4717 | && i.types[2].bitfield.ymmword)))) |
ddb62495 | 4718 | && i.tm.opcode_space == SPACE_0F |
5844ccaa JB |
4719 | && ((i.tm.base_opcode | 2) == 0x57 |
4720 | || i.tm.base_opcode == 0xdf | |
4721 | || i.tm.base_opcode == 0xef | |
4722 | || (i.tm.base_opcode | 3) == 0xfb | |
4723 | || i.tm.base_opcode == 0x42 | |
4724 | || i.tm.base_opcode == 0x47)) | |
b6f8c7c4 | 4725 | { |
99112332 | 4726 | /* Optimize: -O1: |
8305403a L |
4727 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4728 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4729 | EVEX VOP %zmmM, %zmmM, %zmmN |
4730 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4731 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4732 | EVEX VOP %ymmM, %ymmM, %ymmN |
4733 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4734 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4735 | VEX VOP %ymmM, %ymmM, %ymmN |
4736 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4737 | VOP, one of vpandn and vpxor: | |
4738 | VEX VOP %ymmM, %ymmM, %ymmN | |
4739 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4740 | VOP, one of vpandnd and vpandnq: | |
4741 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4742 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4743 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4744 | EVEX VOP %ymmM, %ymmM, %ymmN |
4745 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4746 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4747 | VOP, one of vpxord and vpxorq: |
4748 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4749 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4750 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4751 | EVEX VOP %ymmM, %ymmM, %ymmN |
4752 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4753 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4754 | VOP, one of kxord and kxorq: |
4755 | VEX VOP %kM, %kM, %kN | |
4756 | -> VEX kxorw %kM, %kM, %kN | |
4757 | VOP, one of kandnd and kandnq: | |
4758 | VEX VOP %kM, %kM, %kN | |
4759 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4760 | */ |
706ce984 | 4761 | if (i.tm.opcode_modifier.evex) |
b6f8c7c4 | 4762 | { |
7b1d7ca1 | 4763 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4764 | { |
4765 | i.tm.opcode_modifier.vex = VEX128; | |
4766 | i.tm.opcode_modifier.vexw = VEXW0; | |
4767 | i.tm.opcode_modifier.evex = 0; | |
a6f3add0 JB |
4768 | i.vec_encoding = vex_encoding_vex; |
4769 | i.mask.reg = NULL; | |
b6f8c7c4 | 4770 | } |
7b1d7ca1 | 4771 | else if (optimize > 1) |
dd22218c L |
4772 | i.tm.opcode_modifier.evex = EVEX128; |
4773 | else | |
4774 | return; | |
b6f8c7c4 | 4775 | } |
f74a6307 | 4776 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 | 4777 | { |
35648716 | 4778 | i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; |
1424ad86 JB |
4779 | i.tm.opcode_modifier.vexw = VEXW0; |
4780 | } | |
b6f8c7c4 L |
4781 | else |
4782 | i.tm.opcode_modifier.vex = VEX128; | |
4783 | ||
4784 | if (i.tm.opcode_modifier.vex) | |
4785 | for (j = 0; j < 3; j++) | |
4786 | { | |
4787 | i.types[j].bitfield.xmmword = 1; | |
4788 | i.types[j].bitfield.ymmword = 0; | |
4789 | } | |
4790 | } | |
392a5972 | 4791 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4792 | && !i.types[0].bitfield.zmmword |
392a5972 | 4793 | && !i.types[1].bitfield.zmmword |
6225c532 | 4794 | && !i.mask.reg |
9b345ce8 | 4795 | && !i.broadcast.type |
a5748e0d | 4796 | && !i.broadcast.bytes |
706ce984 | 4797 | && i.tm.opcode_modifier.evex |
35648716 JB |
4798 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4799 | || (i.tm.base_opcode & ~4) == 0xdb | |
4800 | || (i.tm.base_opcode & ~4) == 0xeb) | |
97ed31ae L |
4801 | && i.tm.extension_opcode == None) |
4802 | { | |
4803 | /* Optimize: -O1: | |
4804 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4805 | vmovdqu32 and vmovdqu64: | |
4806 | EVEX VOP %xmmM, %xmmN | |
4807 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4808 | EVEX VOP %ymmM, %ymmN | |
4809 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4810 | EVEX VOP %xmmM, mem | |
4811 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4812 | EVEX VOP %ymmM, mem | |
4813 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4814 | EVEX VOP mem, %xmmN | |
4815 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4816 | EVEX VOP mem, %ymmN | |
4817 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4818 | VOP, one of vpand, vpandn, vpor, vpxor: |
4819 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4820 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4821 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4822 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4823 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4824 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4825 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4826 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4827 | */ |
a0a1771e | 4828 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4829 | if (operand_type_check (i.types[j], disp) |
4830 | && i.op[j].disps->X_op == O_constant) | |
4831 | { | |
4832 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4833 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4834 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4835 | int evex_disp8, vex_disp8; | |
4836 | unsigned int memshift = i.memshift; | |
4837 | offsetT n = i.op[j].disps->X_add_number; | |
4838 | ||
4839 | evex_disp8 = fits_in_disp8 (n); | |
4840 | i.memshift = 0; | |
4841 | vex_disp8 = fits_in_disp8 (n); | |
4842 | if (evex_disp8 != vex_disp8) | |
4843 | { | |
4844 | i.memshift = memshift; | |
4845 | return; | |
4846 | } | |
4847 | ||
4848 | i.types[j].bitfield.disp8 = vex_disp8; | |
4849 | break; | |
4850 | } | |
35648716 JB |
4851 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4852 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2) | |
4853 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
97ed31ae L |
4854 | i.tm.opcode_modifier.vex |
4855 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4856 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 | 4857 | /* VPAND, VPOR, and VPXOR are commutative. */ |
35648716 | 4858 | if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf) |
79dec6b7 | 4859 | i.tm.opcode_modifier.commutative = 1; |
97ed31ae L |
4860 | i.tm.opcode_modifier.evex = 0; |
4861 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4862 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4863 | i.tm.opcode_modifier.disp8memshift = 0; |
4864 | i.memshift = 0; | |
a0a1771e JB |
4865 | if (j < i.operands) |
4866 | i.types[j].bitfield.disp8 | |
4867 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4868 | } |
b5c37946 SJ |
4869 | else if (optimize_for_space |
4870 | && i.tm.base_opcode == 0x29 | |
4871 | && i.tm.opcode_space == SPACE_0F38 | |
4872 | && i.operands == i.reg_operands | |
4873 | && i.op[0].regs == i.op[1].regs | |
4874 | && (!i.tm.opcode_modifier.vex | |
4875 | || !(i.op[0].regs->reg_flags & RegRex)) | |
706ce984 | 4876 | && !i.tm.opcode_modifier.evex) |
b5c37946 SJ |
4877 | { |
4878 | /* Optimize: -Os: | |
4879 | pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN | |
4880 | vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8) | |
4881 | vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8) | |
4882 | */ | |
4883 | i.tm.opcode_space = SPACE_0F; | |
4884 | i.tm.base_opcode = 0x76; | |
4885 | } | |
4886 | else if (((i.tm.base_opcode >= 0x64 | |
4887 | && i.tm.base_opcode <= 0x66 | |
4888 | && i.tm.opcode_space == SPACE_0F) | |
4889 | || (i.tm.base_opcode == 0x37 | |
4890 | && i.tm.opcode_space == SPACE_0F38)) | |
4891 | && i.operands == i.reg_operands | |
4892 | && i.op[0].regs == i.op[1].regs | |
706ce984 | 4893 | && !i.tm.opcode_modifier.evex) |
b5c37946 SJ |
4894 | { |
4895 | /* Optimize: -O: | |
4896 | pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN | |
4897 | pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN | |
4898 | vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8) | |
4899 | vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7) | |
4900 | vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8) | |
4901 | vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7) | |
4902 | */ | |
4903 | i.tm.opcode_space = SPACE_0F; | |
4904 | i.tm.base_opcode = 0xef; | |
4905 | if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex)) | |
4906 | { | |
4907 | if (i.operands == 2) | |
4908 | { | |
4909 | gas_assert (i.tm.opcode_modifier.sse2avx); | |
4910 | ||
4911 | i.operands = 3; | |
4912 | i.reg_operands = 3; | |
4913 | i.tm.operands = 3; | |
4914 | ||
4915 | i.op[2].regs = i.op[0].regs; | |
4916 | i.types[2] = i.types[0]; | |
4917 | i.flags[2] = i.flags[0]; | |
4918 | i.tm.operand_types[2] = i.tm.operand_types[0]; | |
4919 | ||
4920 | i.tm.opcode_modifier.sse2avx = 0; | |
4921 | } | |
4922 | i.op[0].regs -= i.op[0].regs->reg_num + 8; | |
4923 | i.op[1].regs = i.op[0].regs; | |
4924 | } | |
4925 | } | |
4926 | else if (optimize_for_space | |
4927 | && i.tm.base_opcode == 0x59 | |
4928 | && i.tm.opcode_space == SPACE_0F38 | |
4929 | && i.operands == i.reg_operands | |
4930 | && i.tm.opcode_modifier.vex | |
4931 | && !(i.op[0].regs->reg_flags & RegRex) | |
4932 | && i.op[0].regs->reg_type.bitfield.xmmword | |
4933 | && i.vec_encoding != vex_encoding_vex3) | |
4934 | { | |
4935 | /* Optimize: -Os: | |
4936 | vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8) | |
4937 | */ | |
4938 | i.tm.opcode_space = SPACE_0F; | |
4939 | i.tm.base_opcode = 0x6c; | |
4940 | i.tm.opcode_modifier.vexvvvv = 1; | |
4941 | ||
4942 | ++i.operands; | |
4943 | ++i.reg_operands; | |
4944 | ++i.tm.operands; | |
4945 | ||
4946 | i.op[2].regs = i.op[0].regs; | |
4947 | i.types[2] = i.types[0]; | |
4948 | i.flags[2] = i.flags[0]; | |
4949 | i.tm.operand_types[2] = i.tm.operand_types[0]; | |
4950 | ||
4951 | swap_2_operands (1, 2); | |
4952 | } | |
b6f8c7c4 L |
4953 | } |
4954 | ||
ae531041 L |
4955 | /* Return non-zero for load instruction. */ |
4956 | ||
4957 | static int | |
4958 | load_insn_p (void) | |
4959 | { | |
4960 | unsigned int dest; | |
4961 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
4962 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
4963 | ||
4964 | if (!any_vex_p) | |
4965 | { | |
ef07be45 CL |
4966 | /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, |
4967 | bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ | |
255571cd | 4968 | if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE) |
ae531041 L |
4969 | return 0; |
4970 | ||
389d00a5 | 4971 | /* pop. */ |
6d86a545 | 4972 | if (i.tm.mnem_off == MN_pop) |
389d00a5 JB |
4973 | return 1; |
4974 | } | |
4975 | ||
ddb62495 | 4976 | if (i.tm.opcode_space == SPACE_BASE) |
389d00a5 JB |
4977 | { |
4978 | /* popf, popa. */ | |
4979 | if (i.tm.base_opcode == 0x9d | |
a09f656b | 4980 | || i.tm.base_opcode == 0x61) |
ae531041 L |
4981 | return 1; |
4982 | ||
4983 | /* movs, cmps, lods, scas. */ | |
4984 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
4985 | return 1; | |
4986 | ||
a09f656b | 4987 | /* outs, xlatb. */ |
4988 | if (base_opcode == 0x6f | |
4989 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 4990 | return 1; |
a09f656b | 4991 | /* NB: For AMD-specific insns with implicit memory operands, |
4992 | they're intentionally not covered. */ | |
ae531041 L |
4993 | } |
4994 | ||
4995 | /* No memory operand. */ | |
4996 | if (!i.mem_operands) | |
4997 | return 0; | |
4998 | ||
4999 | if (any_vex_p) | |
5000 | { | |
7fc69528 | 5001 | if (i.tm.mnem_off == MN_vldmxcsr) |
ae531041 L |
5002 | return 1; |
5003 | } | |
ddb62495 | 5004 | else if (i.tm.opcode_space == SPACE_BASE) |
ae531041 L |
5005 | { |
5006 | /* test, not, neg, mul, imul, div, idiv. */ | |
aa4c197d | 5007 | if (base_opcode == 0xf7 && i.tm.extension_opcode != 1) |
ae531041 L |
5008 | return 1; |
5009 | ||
5010 | /* inc, dec. */ | |
5011 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
5012 | return 1; | |
5013 | ||
5014 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
5015 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
5016 | return 1; | |
5017 | ||
ae531041 | 5018 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
aa4c197d | 5019 | if ((base_opcode == 0xc1 || (base_opcode | 2) == 0xd3) |
ae531041 L |
5020 | && i.tm.extension_opcode != 6) |
5021 | return 1; | |
5022 | ||
ae531041 | 5023 | /* Check for x87 instructions. */ |
aa4c197d | 5024 | if ((base_opcode | 6) == 0xdf) |
ae531041 L |
5025 | { |
5026 | /* Skip fst, fstp, fstenv, fstcw. */ | |
5027 | if (i.tm.base_opcode == 0xd9 | |
5028 | && (i.tm.extension_opcode == 2 | |
5029 | || i.tm.extension_opcode == 3 | |
5030 | || i.tm.extension_opcode == 6 | |
5031 | || i.tm.extension_opcode == 7)) | |
5032 | return 0; | |
5033 | ||
5034 | /* Skip fisttp, fist, fistp, fstp. */ | |
5035 | if (i.tm.base_opcode == 0xdb | |
5036 | && (i.tm.extension_opcode == 1 | |
5037 | || i.tm.extension_opcode == 2 | |
5038 | || i.tm.extension_opcode == 3 | |
5039 | || i.tm.extension_opcode == 7)) | |
5040 | return 0; | |
5041 | ||
5042 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
5043 | if (i.tm.base_opcode == 0xdd | |
5044 | && (i.tm.extension_opcode == 1 | |
5045 | || i.tm.extension_opcode == 2 | |
5046 | || i.tm.extension_opcode == 3 | |
5047 | || i.tm.extension_opcode == 6 | |
5048 | || i.tm.extension_opcode == 7)) | |
5049 | return 0; | |
5050 | ||
5051 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
5052 | if (i.tm.base_opcode == 0xdf | |
5053 | && (i.tm.extension_opcode == 1 | |
5054 | || i.tm.extension_opcode == 2 | |
5055 | || i.tm.extension_opcode == 3 | |
5056 | || i.tm.extension_opcode == 6 | |
5057 | || i.tm.extension_opcode == 7)) | |
5058 | return 0; | |
5059 | ||
5060 | return 1; | |
5061 | } | |
5062 | } | |
ddb62495 | 5063 | else if (i.tm.opcode_space == SPACE_0F) |
389d00a5 JB |
5064 | { |
5065 | /* bt, bts, btr, btc. */ | |
5066 | if (i.tm.base_opcode == 0xba | |
aa4c197d | 5067 | && (i.tm.extension_opcode | 3) == 7) |
389d00a5 JB |
5068 | return 1; |
5069 | ||
5070 | /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */ | |
5071 | if (i.tm.base_opcode == 0xc7 | |
5072 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE | |
5073 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3 | |
5074 | || i.tm.extension_opcode == 6)) | |
5075 | return 1; | |
5076 | ||
5077 | /* fxrstor, ldmxcsr, xrstor. */ | |
5078 | if (i.tm.base_opcode == 0xae | |
5079 | && (i.tm.extension_opcode == 1 | |
5080 | || i.tm.extension_opcode == 2 | |
5081 | || i.tm.extension_opcode == 5)) | |
5082 | return 1; | |
5083 | ||
5084 | /* lgdt, lidt, lmsw. */ | |
5085 | if (i.tm.base_opcode == 0x01 | |
5086 | && (i.tm.extension_opcode == 2 | |
5087 | || i.tm.extension_opcode == 3 | |
5088 | || i.tm.extension_opcode == 6)) | |
5089 | return 1; | |
5090 | } | |
ae531041 L |
5091 | |
5092 | dest = i.operands - 1; | |
5093 | ||
5094 | /* Check fake imm8 operand and 3 source operands. */ | |
5095 | if ((i.tm.opcode_modifier.immext | |
aa180741 | 5096 | || i.reg_operands + i.mem_operands == 4) |
ae531041 L |
5097 | && i.types[dest].bitfield.imm8) |
5098 | dest--; | |
5099 | ||
389d00a5 | 5100 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */ |
ddb62495 | 5101 | if (i.tm.opcode_space == SPACE_BASE |
aa4c197d | 5102 | && ((base_opcode | 0x38) == 0x39 |
389d00a5 JB |
5103 | || (base_opcode | 2) == 0x87)) |
5104 | return 1; | |
5105 | ||
7fc69528 | 5106 | if (i.tm.mnem_off == MN_xadd) |
ae531041 L |
5107 | return 1; |
5108 | ||
5109 | /* Check for load instruction. */ | |
5110 | return (i.types[dest].bitfield.class != ClassNone | |
5111 | || i.types[dest].bitfield.instance == Accum); | |
5112 | } | |
5113 | ||
5114 | /* Output lfence, 0xfaee8, after instruction. */ | |
5115 | ||
5116 | static void | |
5117 | insert_lfence_after (void) | |
5118 | { | |
5119 | if (lfence_after_load && load_insn_p ()) | |
5120 | { | |
a09f656b | 5121 | /* There are also two REP string instructions that require |
5122 | special treatment. Specifically, the compare string (CMPS) | |
5123 | and scan string (SCAS) instructions set EFLAGS in a manner | |
5124 | that depends on the data being compared/scanned. When used | |
5125 | with a REP prefix, the number of iterations may therefore | |
5126 | vary depending on this data. If the data is a program secret | |
5127 | chosen by the adversary using an LVI method, | |
5128 | then this data-dependent behavior may leak some aspect | |
5129 | of the secret. */ | |
aa4c197d | 5130 | if (((i.tm.base_opcode | 0x9) == 0xaf) |
a09f656b | 5131 | && i.prefix[REP_PREFIX]) |
5132 | { | |
5133 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
76d3f746 | 5134 | insn_name (&i.tm)); |
a09f656b | 5135 | } |
ae531041 L |
5136 | char *p = frag_more (3); |
5137 | *p++ = 0xf; | |
5138 | *p++ = 0xae; | |
5139 | *p = 0xe8; | |
5140 | } | |
5141 | } | |
5142 | ||
5143 | /* Output lfence, 0xfaee8, before instruction. */ | |
5144 | ||
5145 | static void | |
b5482fe5 | 5146 | insert_lfence_before (const struct last_insn *last_insn) |
ae531041 L |
5147 | { |
5148 | char *p; | |
5149 | ||
ddb62495 | 5150 | if (i.tm.opcode_space != SPACE_BASE) |
ae531041 L |
5151 | return; |
5152 | ||
5153 | if (i.tm.base_opcode == 0xff | |
5154 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
5155 | { | |
5156 | /* Insert lfence before indirect branch if needed. */ | |
5157 | ||
5158 | if (lfence_before_indirect_branch == lfence_branch_none) | |
5159 | return; | |
5160 | ||
5161 | if (i.operands != 1) | |
5162 | abort (); | |
5163 | ||
5164 | if (i.reg_operands == 1) | |
5165 | { | |
5166 | /* Indirect branch via register. Don't insert lfence with | |
5167 | -mlfence-after-load=yes. */ | |
5168 | if (lfence_after_load | |
5169 | || lfence_before_indirect_branch == lfence_branch_memory) | |
5170 | return; | |
5171 | } | |
5172 | else if (i.mem_operands == 1 | |
5173 | && lfence_before_indirect_branch != lfence_branch_register) | |
5174 | { | |
5175 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
76d3f746 | 5176 | insn_name (&i.tm)); |
ae531041 L |
5177 | return; |
5178 | } | |
5179 | else | |
5180 | return; | |
5181 | ||
b5482fe5 | 5182 | if (last_insn->kind != last_insn_other) |
ae531041 | 5183 | { |
b5482fe5 | 5184 | as_warn_where (last_insn->file, last_insn->line, |
ae531041 | 5185 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), |
b5482fe5 | 5186 | last_insn->name, insn_name (&i.tm)); |
ae531041 L |
5187 | return; |
5188 | } | |
5189 | ||
5190 | p = frag_more (3); | |
5191 | *p++ = 0xf; | |
5192 | *p++ = 0xae; | |
5193 | *p = 0xe8; | |
5194 | return; | |
5195 | } | |
5196 | ||
503648e4 | 5197 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 | 5198 | if (lfence_before_ret != lfence_before_ret_none |
aa4c197d | 5199 | && (i.tm.base_opcode | 1) == 0xc3) |
ae531041 | 5200 | { |
b5482fe5 | 5201 | if (last_insn->kind != last_insn_other) |
ae531041 | 5202 | { |
b5482fe5 | 5203 | as_warn_where (last_insn->file, last_insn->line, |
ae531041 | 5204 | _("`%s` skips -mlfence-before-ret on `%s`"), |
b5482fe5 | 5205 | last_insn->name, insn_name (&i.tm)); |
ae531041 L |
5206 | return; |
5207 | } | |
a09f656b | 5208 | |
a09f656b | 5209 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 5210 | char prefix = flag_code == CODE_64BIT |
5211 | ? 0x48 | |
5212 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 5213 | |
5214 | if (lfence_before_ret == lfence_before_ret_not) | |
5215 | { | |
5216 | /* not: 0xf71424, may add prefix | |
5217 | for operand size override or 64-bit code. */ | |
5218 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
5219 | if (prefix) | |
5220 | *p++ = prefix; | |
ae531041 L |
5221 | *p++ = 0xf7; |
5222 | *p++ = 0x14; | |
5223 | *p++ = 0x24; | |
a09f656b | 5224 | if (prefix) |
5225 | *p++ = prefix; | |
ae531041 L |
5226 | *p++ = 0xf7; |
5227 | *p++ = 0x14; | |
5228 | *p++ = 0x24; | |
5229 | } | |
a09f656b | 5230 | else |
5231 | { | |
5232 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
5233 | if (prefix) | |
5234 | *p++ = prefix; | |
5235 | if (lfence_before_ret == lfence_before_ret_or) | |
5236 | { | |
5237 | /* or: 0x830c2400, may add prefix | |
5238 | for operand size override or 64-bit code. */ | |
5239 | *p++ = 0x83; | |
5240 | *p++ = 0x0c; | |
5241 | } | |
5242 | else | |
5243 | { | |
5244 | /* shl: 0xc1242400, may add prefix | |
5245 | for operand size override or 64-bit code. */ | |
5246 | *p++ = 0xc1; | |
5247 | *p++ = 0x24; | |
5248 | } | |
5249 | ||
5250 | *p++ = 0x24; | |
5251 | *p++ = 0x0; | |
5252 | } | |
5253 | ||
ae531041 L |
5254 | *p++ = 0xf; |
5255 | *p++ = 0xae; | |
5256 | *p = 0xe8; | |
5257 | } | |
5258 | } | |
5259 | ||
edd67638 JB |
5260 | /* Shared helper for md_assemble() and s_insn(). */ |
5261 | static void init_globals (void) | |
5262 | { | |
5263 | unsigned int j; | |
5264 | ||
5265 | memset (&i, '\0', sizeof (i)); | |
5266 | i.rounding.type = rc_none; | |
5267 | for (j = 0; j < MAX_OPERANDS; j++) | |
5268 | i.reloc[j] = NO_RELOC; | |
5269 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
5270 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
5271 | save_stack_p = save_stack; | |
5272 | } | |
5273 | ||
04784e33 JB |
5274 | /* Helper for md_assemble() to decide whether to prepare for a possible 2nd |
5275 | parsing pass. Instead of introducing a rarely use new insn attribute this | |
5276 | utilizes a common pattern between affected templates. It is deemed | |
5277 | acceptable that this will lead to unnecessary pass 2 preparations in a | |
5278 | limited set of cases. */ | |
5279 | static INLINE bool may_need_pass2 (const insn_template *t) | |
5280 | { | |
5281 | return t->opcode_modifier.sse2avx | |
5282 | /* Note that all SSE2AVX templates have at least one operand. */ | |
a28fedbc | 5283 | ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD |
ddb62495 | 5284 | : (t->opcode_space == SPACE_0F |
a28fedbc | 5285 | && (t->base_opcode | 1) == 0xbf) |
ddb62495 | 5286 | || (t->opcode_space == SPACE_BASE |
a28fedbc | 5287 | && t->base_opcode == 0x63); |
04784e33 JB |
5288 | } |
5289 | ||
252b5132 RH |
5290 | /* This is the guts of the machine-dependent assembler. LINE points to a |
5291 | machine dependent instruction. This function is supposed to emit | |
5292 | the frags/bytes it assembles to. */ | |
5293 | ||
5294 | void | |
65da13b5 | 5295 | md_assemble (char *line) |
252b5132 | 5296 | { |
40fb9820 | 5297 | unsigned int j; |
9db83a32 | 5298 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix = 0, *copy = NULL; |
04784e33 JB |
5299 | const char *end, *pass1_mnem = NULL; |
5300 | enum i386_error pass1_err = 0; | |
d3ce72d0 | 5301 | const insn_template *t; |
b5482fe5 JB |
5302 | struct last_insn *last_insn |
5303 | = &seg_info(now_seg)->tc_segment_info_data.last_insn; | |
252b5132 | 5304 | |
47926f60 | 5305 | /* Initialize globals. */ |
d3b01414 | 5306 | current_templates.end = current_templates.start = NULL; |
04784e33 | 5307 | retry: |
edd67638 | 5308 | init_globals (); |
252b5132 | 5309 | |
175ce60f JB |
5310 | /* Suppress optimization when the last thing we saw may not have been |
5311 | a proper instruction (e.g. a stand-alone prefix or .byte). */ | |
5312 | if (last_insn->kind != last_insn_other) | |
5313 | i.no_optimize = true; | |
5314 | ||
252b5132 RH |
5315 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
5316 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 5317 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 5318 | |
edd67638 | 5319 | end = parse_insn (line, mnemonic, false); |
5317ad2c | 5320 | if (end == NULL) |
04784e33 JB |
5321 | { |
5322 | if (pass1_mnem != NULL) | |
5323 | goto match_error; | |
9db83a32 JB |
5324 | if (i.error != no_error) |
5325 | { | |
d3b01414 JB |
5326 | gas_assert (current_templates.start != NULL); |
5327 | if (may_need_pass2 (current_templates.start) && !i.suffix) | |
9db83a32 JB |
5328 | goto no_match; |
5329 | /* No point in trying a 2nd pass - it'll only find the same suffix | |
5330 | again. */ | |
5331 | mnem_suffix = i.suffix; | |
5332 | goto match_error; | |
5333 | } | |
04784e33 JB |
5334 | return; |
5335 | } | |
d3b01414 | 5336 | t = current_templates.start; |
6d86a545 | 5337 | if (may_need_pass2 (t)) |
04784e33 JB |
5338 | { |
5339 | /* Make a copy of the full line in case we need to retry. */ | |
5340 | copy = xstrdup (line); | |
5341 | } | |
5317ad2c | 5342 | line += end - line; |
83b16ac6 | 5343 | mnem_suffix = i.suffix; |
252b5132 | 5344 | |
29b0f896 | 5345 | line = parse_operands (line, mnemonic); |
ee86248c | 5346 | this_operand = -1; |
29b0f896 | 5347 | if (line == NULL) |
04784e33 JB |
5348 | { |
5349 | free (copy); | |
5350 | return; | |
5351 | } | |
252b5132 | 5352 | |
29b0f896 AM |
5353 | /* Now we've parsed the mnemonic into a set of templates, and have the |
5354 | operands at hand. */ | |
5355 | ||
b630c145 | 5356 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
c0e54661 | 5357 | "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", |
b0e8fa7f TJ |
5358 | "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse |
5359 | intersegment "jmp" and "call" instructions with 2 immediate operands so | |
5360 | that the immediate segment precedes the offset consistently in Intel and | |
5361 | AT&T modes. */ | |
4d456e3d L |
5362 | if (intel_syntax |
5363 | && i.operands > 1 | |
6d86a545 JB |
5364 | && (t->mnem_off != MN_bound) |
5365 | && !startswith (mnemonic, "invlpg") | |
d34049e8 ML |
5366 | && !startswith (mnemonic, "monitor") |
5367 | && !startswith (mnemonic, "mwait") | |
6d86a545 | 5368 | && (t->mnem_off != MN_pvalidate) |
d34049e8 | 5369 | && !startswith (mnemonic, "rmp") |
6d86a545 JB |
5370 | && (t->mnem_off != MN_tpause) |
5371 | && (t->mnem_off != MN_umwait) | |
47c0279b JB |
5372 | && !(i.operands == 2 |
5373 | && operand_type_check (i.types[0], imm) | |
40fb9820 | 5374 | && operand_type_check (i.types[1], imm))) |
29b0f896 AM |
5375 | swap_operands (); |
5376 | ||
e7d74879 JB |
5377 | /* The order of the immediates should be reversed for 2-immediates EXTRQ |
5378 | and INSERTQ instructions. Also UWRMSR wants its immediate to be in the | |
5379 | "canonical" place (first), despite it appearing last (in AT&T syntax, or | |
5380 | because of the swapping above) in the incoming set of operands. */ | |
5381 | if ((i.imm_operands == 2 | |
5382 | && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) | |
5383 | || (t->mnem_off == MN_uwrmsr && i.imm_operands | |
5384 | && i.operands > i.imm_operands)) | |
ec56d5c0 JB |
5385 | swap_2_operands (0, 1); |
5386 | ||
29b0f896 | 5387 | if (i.imm_operands) |
8170af78 HL |
5388 | { |
5389 | /* For USER_MSR instructions, imm32 stands for the name of an model specific | |
5390 | register (MSR). That's an unsigned quantity, whereas all other insns with | |
5391 | 32-bit immediate and 64-bit operand size use sign-extended | |
5392 | immediates (imm32s). Therefore these insns are special-cased, bypassing | |
5393 | the normal handling of immediates here. */ | |
d3b01414 | 5394 | if (is_cpu(current_templates.start, CpuUSER_MSR)) |
8170af78 HL |
5395 | { |
5396 | for (j = 0; j < i.operands; j++) | |
5397 | { | |
5398 | if (operand_type_check(i.types[j], imm)) | |
5399 | i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number); | |
5400 | } | |
5401 | } | |
5402 | else | |
5403 | optimize_imm (); | |
5404 | } | |
29b0f896 | 5405 | |
0de704b9 JB |
5406 | if (i.disp_operands && !optimize_disp (t)) |
5407 | return; | |
29b0f896 AM |
5408 | |
5409 | /* Next, we find a template that matches the given insn, | |
5410 | making sure the overlap of the given operands types is consistent | |
5411 | with the template operand types. */ | |
252b5132 | 5412 | |
83b16ac6 | 5413 | if (!(t = match_template (mnem_suffix))) |
04784e33 JB |
5414 | { |
5415 | const char *err_msg; | |
5416 | ||
5417 | if (copy && !mnem_suffix) | |
5418 | { | |
5419 | line = copy; | |
5420 | copy = NULL; | |
9db83a32 | 5421 | no_match: |
04784e33 | 5422 | pass1_err = i.error; |
d3b01414 | 5423 | pass1_mnem = insn_name (current_templates.start); |
04784e33 JB |
5424 | goto retry; |
5425 | } | |
9db83a32 JB |
5426 | |
5427 | /* If a non-/only-64bit template (group) was found in pass 1, and if | |
5428 | _some_ template (group) was found in pass 2, squash pass 1's | |
5429 | error. */ | |
5430 | if (pass1_err == unsupported_64bit) | |
5431 | pass1_mnem = NULL; | |
5432 | ||
04784e33 | 5433 | match_error: |
9db83a32 JB |
5434 | free (copy); |
5435 | ||
04784e33 JB |
5436 | switch (pass1_mnem ? pass1_err : i.error) |
5437 | { | |
5438 | default: | |
5439 | abort (); | |
5440 | case operand_size_mismatch: | |
5441 | err_msg = _("operand size mismatch"); | |
5442 | break; | |
5443 | case operand_type_mismatch: | |
5444 | err_msg = _("operand type mismatch"); | |
5445 | break; | |
5446 | case register_type_mismatch: | |
5447 | err_msg = _("register type mismatch"); | |
5448 | break; | |
5449 | case number_of_operands_mismatch: | |
5450 | err_msg = _("number of operands mismatch"); | |
5451 | break; | |
5452 | case invalid_instruction_suffix: | |
5453 | err_msg = _("invalid instruction suffix"); | |
5454 | break; | |
5455 | case bad_imm4: | |
5456 | err_msg = _("constant doesn't fit in 4 bits"); | |
5457 | break; | |
5458 | case unsupported_with_intel_mnemonic: | |
5459 | err_msg = _("unsupported with Intel mnemonic"); | |
5460 | break; | |
5461 | case unsupported_syntax: | |
5462 | err_msg = _("unsupported syntax"); | |
5463 | break; | |
80d61d8d CL |
5464 | case unsupported_EGPR_for_addressing: |
5465 | err_msg = _("extended GPR cannot be used as base/index"); | |
5466 | break; | |
04784e33 JB |
5467 | case unsupported: |
5468 | as_bad (_("unsupported instruction `%s'"), | |
d3b01414 | 5469 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
04784e33 | 5470 | return; |
9db83a32 JB |
5471 | case unsupported_on_arch: |
5472 | as_bad (_("`%s' is not supported on `%s%s'"), | |
d3b01414 | 5473 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
9db83a32 JB |
5474 | cpu_arch_name ? cpu_arch_name : default_arch, |
5475 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
5476 | return; | |
5477 | case unsupported_64bit: | |
5478 | if (ISLOWER (mnem_suffix)) | |
e8b4b7b2 NC |
5479 | { |
5480 | if (flag_code == CODE_64BIT) | |
5481 | as_bad (_("`%s%c' is not supported in 64-bit mode"), | |
d3b01414 | 5482 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
e8b4b7b2 NC |
5483 | mnem_suffix); |
5484 | else | |
5485 | as_bad (_("`%s%c' is only supported in 64-bit mode"), | |
d3b01414 | 5486 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start), |
e8b4b7b2 NC |
5487 | mnem_suffix); |
5488 | } | |
9db83a32 | 5489 | else |
e8b4b7b2 NC |
5490 | { |
5491 | if (flag_code == CODE_64BIT) | |
5492 | as_bad (_("`%s' is not supported in 64-bit mode"), | |
d3b01414 | 5493 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
e8b4b7b2 NC |
5494 | else |
5495 | as_bad (_("`%s' is only supported in 64-bit mode"), | |
d3b01414 | 5496 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
e8b4b7b2 | 5497 | } |
9db83a32 | 5498 | return; |
54294d73 JB |
5499 | case no_vex_encoding: |
5500 | err_msg = _("no VEX/XOP encoding"); | |
5501 | break; | |
5502 | case no_evex_encoding: | |
5503 | err_msg = _("no EVEX encoding"); | |
5504 | break; | |
04784e33 JB |
5505 | case invalid_sib_address: |
5506 | err_msg = _("invalid SIB address"); | |
5507 | break; | |
5508 | case invalid_vsib_address: | |
5509 | err_msg = _("invalid VSIB address"); | |
5510 | break; | |
5511 | case invalid_vector_register_set: | |
5512 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5513 | break; | |
5514 | case invalid_tmm_register_set: | |
5515 | err_msg = _("all tmm registers must be distinct"); | |
5516 | break; | |
5517 | case invalid_dest_and_src_register_set: | |
5518 | err_msg = _("destination and source registers must be distinct"); | |
5519 | break; | |
08a98d4c MZ |
5520 | case invalid_dest_register_set: |
5521 | err_msg = _("two dest registers must be distinct"); | |
5522 | break; | |
80d61d8d CL |
5523 | case invalid_pseudo_prefix: |
5524 | err_msg = _("rex2 pseudo prefix cannot be used"); | |
5525 | break; | |
04784e33 JB |
5526 | case unsupported_vector_index_register: |
5527 | err_msg = _("unsupported vector index register"); | |
5528 | break; | |
5529 | case unsupported_broadcast: | |
5530 | err_msg = _("unsupported broadcast"); | |
5531 | break; | |
5532 | case broadcast_needed: | |
5533 | err_msg = _("broadcast is needed for operand of such type"); | |
5534 | break; | |
5535 | case unsupported_masking: | |
5536 | err_msg = _("unsupported masking"); | |
5537 | break; | |
5538 | case mask_not_on_destination: | |
5539 | err_msg = _("mask not on destination operand"); | |
5540 | break; | |
5541 | case no_default_mask: | |
5542 | err_msg = _("default mask isn't allowed"); | |
5543 | break; | |
5544 | case unsupported_rc_sae: | |
5545 | err_msg = _("unsupported static rounding/sae"); | |
5546 | break; | |
54294d73 JB |
5547 | case unsupported_vector_size: |
5548 | as_bad (_("vector size above %u required for `%s'"), 128u << vector_size, | |
d3b01414 | 5549 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
54294d73 | 5550 | return; |
08a98d4c MZ |
5551 | case unsupported_rsp_register: |
5552 | err_msg = _("'rsp' register cannot be used"); | |
5553 | break; | |
58bceb18 JB |
5554 | case internal_error: |
5555 | err_msg = _("internal error"); | |
5556 | break; | |
04784e33 JB |
5557 | } |
5558 | as_bad (_("%s for `%s'"), err_msg, | |
d3b01414 | 5559 | pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); |
04784e33 JB |
5560 | return; |
5561 | } | |
5562 | ||
5563 | free (copy); | |
252b5132 | 5564 | |
7bab8ab5 | 5565 | if (sse_check != check_none |
ffb86450 JB |
5566 | /* The opcode space check isn't strictly needed; it's there only to |
5567 | bypass the logic below when easily possible. */ | |
ddb62495 JB |
5568 | && t->opcode_space >= SPACE_0F |
5569 | && t->opcode_space <= SPACE_0F3A | |
734dfd1c | 5570 | && !is_cpu (&i.tm, CpuSSE4a) |
ffb86450 | 5571 | && !is_any_vex_encoding (t)) |
daf50ae7 | 5572 | { |
ffb86450 JB |
5573 | bool simd = false; |
5574 | ||
5575 | for (j = 0; j < t->operands; ++j) | |
5576 | { | |
5577 | if (t->operand_types[j].bitfield.class == RegMMX) | |
5578 | break; | |
5579 | if (t->operand_types[j].bitfield.class == RegSIMD) | |
5580 | simd = true; | |
5581 | } | |
5582 | ||
5583 | if (j >= t->operands && simd) | |
5584 | (sse_check == check_warning | |
5585 | ? as_warn | |
76d3f746 | 5586 | : as_bad) (_("SSE instruction `%s' is used"), insn_name (&i.tm)); |
daf50ae7 L |
5587 | } |
5588 | ||
40fb9820 | 5589 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
5590 | if (!add_prefix (FWAIT_OPCODE)) |
5591 | return; | |
252b5132 | 5592 | |
d5de92cf | 5593 | /* Check if REP prefix is OK. */ |
742732c7 | 5594 | if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep) |
d5de92cf L |
5595 | { |
5596 | as_bad (_("invalid instruction `%s' after `%s'"), | |
76d3f746 | 5597 | insn_name (&i.tm), i.rep_prefix); |
d5de92cf L |
5598 | return; |
5599 | } | |
5600 | ||
c1ba0266 L |
5601 | /* Check for lock without a lockable instruction. Destination operand |
5602 | must be memory unless it is xchg (0x86). */ | |
9a4a4499 JB |
5603 | if (i.prefix[LOCK_PREFIX]) |
5604 | { | |
5605 | if (i.tm.opcode_modifier.prefixok < PrefixLock | |
c1ba0266 L |
5606 | || i.mem_operands == 0 |
5607 | || (i.tm.base_opcode != 0x86 | |
9a4a4499 JB |
5608 | && !(i.flags[i.operands - 1] & Operand_Mem))) |
5609 | { | |
5610 | as_bad (_("expecting lockable instruction after `lock'")); | |
5611 | return; | |
5612 | } | |
5613 | ||
5614 | /* Zap the redundant prefix from XCHG when optimizing. */ | |
5615 | if (i.tm.base_opcode == 0x86 && optimize && !i.no_optimize) | |
5616 | i.prefix[LOCK_PREFIX] = 0; | |
c32fa91d L |
5617 | } |
5618 | ||
e3669c7f JB |
5619 | if (is_any_vex_encoding (&i.tm) |
5620 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
5621 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX) | |
7a8655d2 | 5622 | { |
e3669c7f JB |
5623 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
5624 | if (i.prefix[DATA_PREFIX]) | |
5625 | { | |
76d3f746 | 5626 | as_bad (_("data size prefix invalid with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
5627 | return; |
5628 | } | |
5629 | ||
5630 | /* Don't allow e.g. KMOV in TLS code sequences. */ | |
5631 | for (j = i.imm_operands; j < i.operands; ++j) | |
5632 | switch (i.reloc[j]) | |
5633 | { | |
5634 | case BFD_RELOC_386_TLS_GOTIE: | |
5635 | case BFD_RELOC_386_TLS_LE_32: | |
5636 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 5637 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
e3669c7f | 5638 | case BFD_RELOC_X86_64_TLSLD: |
76d3f746 | 5639 | as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
5640 | return; |
5641 | default: | |
5642 | break; | |
5643 | } | |
7a8655d2 JB |
5644 | } |
5645 | ||
42164a71 | 5646 | /* Check if HLE prefix is OK. */ |
165de32a | 5647 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
5648 | return; |
5649 | ||
7e8b059b L |
5650 | /* Check BND prefix. */ |
5651 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
5652 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
5653 | ||
04ef582a | 5654 | /* Check NOTRACK prefix. */ |
742732c7 | 5655 | if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack) |
9fef80d6 | 5656 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
04ef582a | 5657 | |
734dfd1c | 5658 | if (is_cpu (&i.tm, CpuMPX)) |
327e8c42 JB |
5659 | { |
5660 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
5661 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
5662 | else if (flag_code != CODE_16BIT | |
5663 | ? i.prefix[ADDR_PREFIX] | |
5664 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
5665 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
5666 | } | |
7e8b059b L |
5667 | |
5668 | /* Insert BND prefix. */ | |
76d3a78a JB |
5669 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
5670 | { | |
5671 | if (!i.prefix[BND_PREFIX]) | |
5672 | add_prefix (BND_PREFIX_OPCODE); | |
5673 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
5674 | { | |
5675 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
5676 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
5677 | } | |
5678 | } | |
7e8b059b | 5679 | |
29b0f896 | 5680 | /* Check string instruction segment overrides. */ |
51c8edf6 | 5681 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 5682 | { |
51c8edf6 | 5683 | gas_assert (i.mem_operands); |
29b0f896 | 5684 | if (!check_string ()) |
5dd0794d | 5685 | return; |
fc0763e6 | 5686 | i.disp_operands = 0; |
29b0f896 | 5687 | } |
5dd0794d | 5688 | |
9373f275 L |
5689 | /* The memory operand of (%dx) should be only used with input/output |
5690 | instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */ | |
5691 | if (i.input_output_operand | |
5692 | && ((i.tm.base_opcode | 0x82) != 0xee | |
ddb62495 | 5693 | || i.tm.opcode_space != SPACE_BASE)) |
9373f275 L |
5694 | { |
5695 | as_bad (_("input/output port address isn't allowed with `%s'"), | |
76d3f746 | 5696 | insn_name (&i.tm)); |
9373f275 L |
5697 | return; |
5698 | } | |
5699 | ||
b6f8c7c4 L |
5700 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
5701 | optimize_encoding (); | |
5702 | ||
a6f3add0 JB |
5703 | /* Past optimization there's no need to distinguish vex_encoding_evex and |
5704 | vex_encoding_evex512 anymore. */ | |
5705 | if (i.vec_encoding == vex_encoding_evex512) | |
5706 | i.vec_encoding = vex_encoding_evex; | |
5707 | ||
c8480b58 L |
5708 | if (use_unaligned_vector_move) |
5709 | encode_with_unaligned_vector_move (); | |
5710 | ||
29b0f896 AM |
5711 | if (!process_suffix ()) |
5712 | return; | |
e413e4e9 | 5713 | |
ef07be45 | 5714 | /* Check if IP-relative addressing requirements can be satisfied. */ |
734dfd1c | 5715 | if (is_cpu (&i.tm, CpuPREFETCHI) |
ef07be45 | 5716 | && !(i.base_reg && i.base_reg->reg_num == RegIP)) |
76d3f746 | 5717 | as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i.tm)); |
ef07be45 | 5718 | |
921eafea | 5719 | /* Update operand types and check extended states. */ |
bc0844ae | 5720 | for (j = 0; j < i.operands; j++) |
921eafea L |
5721 | { |
5722 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3d70986f | 5723 | switch (i.tm.operand_types[j].bitfield.class) |
921eafea L |
5724 | { |
5725 | default: | |
5726 | break; | |
5727 | case RegMMX: | |
5728 | i.xstate |= xstate_mmx; | |
5729 | break; | |
5730 | case RegMask: | |
32930e4e | 5731 | i.xstate |= xstate_mask; |
921eafea L |
5732 | break; |
5733 | case RegSIMD: | |
3d70986f | 5734 | if (i.tm.operand_types[j].bitfield.tmmword) |
921eafea | 5735 | i.xstate |= xstate_tmm; |
4fc85f37 | 5736 | else if (i.tm.operand_types[j].bitfield.zmmword |
a6f3add0 | 5737 | && !i.tm.opcode_modifier.vex |
4fc85f37 | 5738 | && vector_size >= VSZ512) |
921eafea | 5739 | i.xstate |= xstate_zmm; |
4fc85f37 JB |
5740 | else if (i.tm.operand_types[j].bitfield.ymmword |
5741 | && vector_size >= VSZ256) | |
921eafea | 5742 | i.xstate |= xstate_ymm; |
3d70986f | 5743 | else if (i.tm.operand_types[j].bitfield.xmmword) |
921eafea L |
5744 | i.xstate |= xstate_xmm; |
5745 | break; | |
5746 | } | |
5747 | } | |
bc0844ae | 5748 | |
29b0f896 AM |
5749 | /* Make still unresolved immediate matches conform to size of immediate |
5750 | given in i.suffix. */ | |
5751 | if (!finalize_imm ()) | |
5752 | return; | |
252b5132 | 5753 | |
40fb9820 | 5754 | if (i.types[0].bitfield.imm1) |
29b0f896 | 5755 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 5756 | |
29b0f896 AM |
5757 | /* For insns with operands there are more diddles to do to the opcode. */ |
5758 | if (i.operands) | |
5759 | { | |
5760 | if (!process_operands ()) | |
5761 | return; | |
5762 | } | |
255571cd | 5763 | else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) |
29b0f896 AM |
5764 | { |
5765 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
76d3f746 | 5766 | as_warn (_("translating to `%sp'"), insn_name (&i.tm)); |
29b0f896 | 5767 | } |
252b5132 | 5768 | |
7a8655d2 | 5769 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 5770 | { |
c1dc7af5 | 5771 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 5772 | { |
c1dc7af5 | 5773 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
76d3f746 | 5774 | insn_name (&i.tm)); |
9e5e5283 L |
5775 | return; |
5776 | } | |
c0f3af97 | 5777 | |
0b9404fd JB |
5778 | /* Check for explicit REX prefix. */ |
5779 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
5780 | { | |
76d3f746 | 5781 | as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm)); |
0b9404fd JB |
5782 | return; |
5783 | } | |
5784 | ||
80d61d8d CL |
5785 | /* Check for explicit REX2 prefix. */ |
5786 | if (i.rex2_encoding) | |
5787 | { | |
5788 | as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm)); | |
5789 | return; | |
5790 | } | |
5791 | ||
6177c84d CL |
5792 | if (is_apx_evex_encoding ()) |
5793 | build_apx_evex_prefix (); | |
5794 | else if (i.tm.opcode_modifier.vex) | |
9e5e5283 L |
5795 | build_vex_prefix (t); |
5796 | else | |
5797 | build_evex_prefix (); | |
0b9404fd JB |
5798 | |
5799 | /* The individual REX.RXBW bits got consumed. */ | |
5800 | i.rex &= REX_OPCODE; | |
6177c84d CL |
5801 | |
5802 | /* The rex2 bits got consumed. */ | |
5803 | i.rex2 = 0; | |
9e5e5283 | 5804 | } |
43234a1e | 5805 | |
7fc69528 JB |
5806 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
5807 | if (i.tm.mnem_off == MN_int | |
a6461c02 | 5808 | && i.op[0].imms->X_add_number == 3) |
29b0f896 AM |
5809 | { |
5810 | i.tm.base_opcode = INT3_OPCODE; | |
5811 | i.imm_operands = 0; | |
5812 | } | |
252b5132 | 5813 | |
0cfa3eb3 JB |
5814 | if ((i.tm.opcode_modifier.jump == JUMP |
5815 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
5816 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
5817 | && i.op[0].disps->X_op == O_constant) |
5818 | { | |
5819 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
5820 | the absolute address given by the constant. Since ix86 jumps and | |
5821 | calls are pc relative, we need to generate a reloc. */ | |
5822 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
5823 | i.op[0].disps->X_op = O_symbol; | |
5824 | } | |
252b5132 | 5825 | |
ce705688 | 5826 | establish_rex (); |
29b0f896 | 5827 | |
b5482fe5 | 5828 | insert_lfence_before (last_insn); |
ae531041 | 5829 | |
29b0f896 | 5830 | /* We are ready to output the insn. */ |
b5482fe5 | 5831 | output_insn (last_insn); |
e379e5f3 | 5832 | |
ae531041 L |
5833 | insert_lfence_after (); |
5834 | ||
e379e5f3 L |
5835 | if (i.tm.opcode_modifier.isprefix) |
5836 | { | |
b5482fe5 JB |
5837 | last_insn->kind = last_insn_prefix; |
5838 | last_insn->name = insn_name (&i.tm); | |
5839 | last_insn->file = as_where (&last_insn->line); | |
e379e5f3 L |
5840 | } |
5841 | else | |
b5482fe5 | 5842 | last_insn->kind = last_insn_other; |
29b0f896 AM |
5843 | } |
5844 | ||
9db83a32 JB |
5845 | /* The Q suffix is generally valid only in 64-bit mode, with very few |
5846 | exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild | |
5847 | and fisttp only one of their two templates is matched below: That's | |
5848 | sufficient since other relevant attributes are the same between both | |
5849 | respective templates. */ | |
5850 | static INLINE bool q_suffix_allowed(const insn_template *t) | |
5851 | { | |
5852 | return flag_code == CODE_64BIT | |
ddb62495 | 5853 | || (t->opcode_space == SPACE_BASE |
9db83a32 JB |
5854 | && t->base_opcode == 0xdf |
5855 | && (t->extension_opcode & 1)) /* fild / fistp / fisttp */ | |
7fc69528 | 5856 | || t->mnem_off == MN_cmpxchg8b; |
9db83a32 JB |
5857 | } |
5858 | ||
5317ad2c | 5859 | static const char * |
edd67638 | 5860 | parse_insn (const char *line, char *mnemonic, bool prefix_only) |
29b0f896 | 5861 | { |
5317ad2c | 5862 | const char *l = line, *token_start = l; |
29b0f896 | 5863 | char *mnem_p; |
d3b01414 | 5864 | bool pass1 = !current_templates.start; |
5c6af06e | 5865 | int supported; |
d3ce72d0 | 5866 | const insn_template *t; |
b6169b20 | 5867 | char *dot_p = NULL; |
29b0f896 | 5868 | |
29b0f896 AM |
5869 | while (1) |
5870 | { | |
5871 | mnem_p = mnemonic; | |
778415f5 JB |
5872 | /* Pseudo-prefixes start with an opening figure brace. */ |
5873 | if ((*mnem_p = *l) == '{') | |
5874 | { | |
5875 | ++mnem_p; | |
5876 | ++l; | |
5877 | } | |
29b0f896 AM |
5878 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
5879 | { | |
b6169b20 L |
5880 | if (*mnem_p == '.') |
5881 | dot_p = mnem_p; | |
29b0f896 AM |
5882 | mnem_p++; |
5883 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 5884 | { |
778415f5 | 5885 | too_long: |
29b0f896 AM |
5886 | as_bad (_("no such instruction: `%s'"), token_start); |
5887 | return NULL; | |
5888 | } | |
5889 | l++; | |
5890 | } | |
778415f5 JB |
5891 | /* Pseudo-prefixes end with a closing figure brace. */ |
5892 | if (*mnemonic == '{' && *l == '}') | |
5893 | { | |
5894 | *mnem_p++ = *l++; | |
5895 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
5896 | goto too_long; | |
5897 | *mnem_p = '\0'; | |
5898 | ||
5899 | /* Point l at the closing brace if there's no other separator. */ | |
5900 | if (*l != END_OF_INSN && !is_space_char (*l) | |
5901 | && *l != PREFIX_SEPARATOR) | |
5902 | --l; | |
5903 | } | |
5904 | else if (!is_space_char (*l) | |
5905 | && *l != END_OF_INSN | |
5906 | && (intel_syntax | |
5907 | || (*l != PREFIX_SEPARATOR && *l != ','))) | |
29b0f896 | 5908 | { |
edd67638 JB |
5909 | if (prefix_only) |
5910 | break; | |
29b0f896 AM |
5911 | as_bad (_("invalid character %s in mnemonic"), |
5912 | output_invalid (*l)); | |
5913 | return NULL; | |
5914 | } | |
5915 | if (token_start == l) | |
5916 | { | |
e44823cf | 5917 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
5918 | as_bad (_("expecting prefix; got nothing")); |
5919 | else | |
5920 | as_bad (_("expecting mnemonic; got nothing")); | |
5921 | return NULL; | |
5922 | } | |
45288df1 | 5923 | |
29b0f896 | 5924 | /* Look up instruction (or prefix) via hash table. */ |
d3b01414 | 5925 | op_lookup (mnemonic); |
47926f60 | 5926 | |
29b0f896 AM |
5927 | if (*l != END_OF_INSN |
5928 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
d3b01414 JB |
5929 | && current_templates.start |
5930 | && current_templates.start->opcode_modifier.isprefix) | |
29b0f896 | 5931 | { |
d3b01414 | 5932 | supported = cpu_flags_match (current_templates.start); |
3086ed9a | 5933 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
2dd88dca JB |
5934 | { |
5935 | as_bad ((flag_code != CODE_64BIT | |
5936 | ? _("`%s' is only supported in 64-bit mode") | |
5937 | : _("`%s' is not supported in 64-bit mode")), | |
d3b01414 | 5938 | insn_name (current_templates.start)); |
2dd88dca JB |
5939 | return NULL; |
5940 | } | |
3086ed9a JB |
5941 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
5942 | { | |
5943 | as_bad (_("`%s' is not supported on `%s%s'"), | |
d3b01414 | 5944 | insn_name (current_templates.start), |
3086ed9a JB |
5945 | cpu_arch_name ? cpu_arch_name : default_arch, |
5946 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
5947 | return NULL; | |
5948 | } | |
29b0f896 AM |
5949 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
5950 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
d3b01414 JB |
5951 | if ((current_templates.start->opcode_modifier.size == SIZE16 |
5952 | || current_templates.start->opcode_modifier.size == SIZE32) | |
29b0f896 | 5953 | && flag_code != CODE_64BIT |
d3b01414 | 5954 | && ((current_templates.start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
5955 | ^ (flag_code == CODE_16BIT))) |
5956 | { | |
5957 | as_bad (_("redundant %s prefix"), | |
d3b01414 | 5958 | insn_name (current_templates.start)); |
29b0f896 | 5959 | return NULL; |
45288df1 | 5960 | } |
31184569 | 5961 | |
d3b01414 | 5962 | if (current_templates.start->base_opcode == PSEUDO_PREFIX) |
29b0f896 | 5963 | { |
86fa6981 | 5964 | /* Handle pseudo prefixes. */ |
d3b01414 | 5965 | switch (current_templates.start->extension_opcode) |
86fa6981 | 5966 | { |
41eb8e88 | 5967 | case Prefix_Disp8: |
86fa6981 L |
5968 | /* {disp8} */ |
5969 | i.disp_encoding = disp_encoding_8bit; | |
5970 | break; | |
41eb8e88 L |
5971 | case Prefix_Disp16: |
5972 | /* {disp16} */ | |
5973 | i.disp_encoding = disp_encoding_16bit; | |
5974 | break; | |
5975 | case Prefix_Disp32: | |
86fa6981 L |
5976 | /* {disp32} */ |
5977 | i.disp_encoding = disp_encoding_32bit; | |
5978 | break; | |
41eb8e88 | 5979 | case Prefix_Load: |
86fa6981 L |
5980 | /* {load} */ |
5981 | i.dir_encoding = dir_encoding_load; | |
5982 | break; | |
41eb8e88 | 5983 | case Prefix_Store: |
86fa6981 L |
5984 | /* {store} */ |
5985 | i.dir_encoding = dir_encoding_store; | |
5986 | break; | |
41eb8e88 | 5987 | case Prefix_VEX: |
42e04b36 L |
5988 | /* {vex} */ |
5989 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 | 5990 | break; |
41eb8e88 | 5991 | case Prefix_VEX3: |
86fa6981 L |
5992 | /* {vex3} */ |
5993 | i.vec_encoding = vex_encoding_vex3; | |
5994 | break; | |
41eb8e88 | 5995 | case Prefix_EVEX: |
86fa6981 L |
5996 | /* {evex} */ |
5997 | i.vec_encoding = vex_encoding_evex; | |
5998 | break; | |
41eb8e88 | 5999 | case Prefix_REX: |
6b6b6807 | 6000 | /* {rex} */ |
5b7c81bd | 6001 | i.rex_encoding = true; |
6b6b6807 | 6002 | break; |
80d61d8d CL |
6003 | case Prefix_REX2: |
6004 | /* {rex2} */ | |
6005 | i.rex2_encoding = true; | |
6006 | break; | |
41eb8e88 | 6007 | case Prefix_NoOptimize: |
b6f8c7c4 | 6008 | /* {nooptimize} */ |
5b7c81bd | 6009 | i.no_optimize = true; |
b6f8c7c4 | 6010 | break; |
86fa6981 L |
6011 | default: |
6012 | abort (); | |
6013 | } | |
6014 | } | |
6015 | else | |
6016 | { | |
6017 | /* Add prefix, checking for repeated prefixes. */ | |
d3b01414 | 6018 | switch (add_prefix (current_templates.start->base_opcode)) |
86fa6981 | 6019 | { |
4e9ac44a L |
6020 | case PREFIX_EXIST: |
6021 | return NULL; | |
6022 | case PREFIX_DS: | |
d3b01414 JB |
6023 | if (is_cpu (current_templates.start, CpuIBT)) |
6024 | i.notrack_prefix = insn_name (current_templates.start); | |
4e9ac44a L |
6025 | break; |
6026 | case PREFIX_REP: | |
d3b01414 JB |
6027 | if (is_cpu (current_templates.start, CpuHLE)) |
6028 | i.hle_prefix = insn_name (current_templates.start); | |
6029 | else if (is_cpu (current_templates.start, CpuMPX)) | |
6030 | i.bnd_prefix = insn_name (current_templates.start); | |
4e9ac44a | 6031 | else |
d3b01414 | 6032 | i.rep_prefix = insn_name (current_templates.start); |
4e9ac44a L |
6033 | break; |
6034 | default: | |
6035 | break; | |
86fa6981 | 6036 | } |
29b0f896 AM |
6037 | } |
6038 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
6039 | token_start = ++l; | |
6040 | } | |
6041 | else | |
6042 | break; | |
6043 | } | |
45288df1 | 6044 | |
edd67638 JB |
6045 | if (prefix_only) |
6046 | return token_start; | |
6047 | ||
d3b01414 | 6048 | if (!current_templates.start) |
b6169b20 | 6049 | { |
07d5e953 JB |
6050 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
6051 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 6052 | encoding. */ |
30a55f88 | 6053 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
97f31cb4 JB |
6054 | { |
6055 | if (i.dir_encoding == dir_encoding_default) | |
6056 | i.dir_encoding = dir_encoding_swap; | |
6057 | else | |
6058 | as_warn (_("ignoring `.s' suffix due to earlier `{%s}'"), | |
6059 | i.dir_encoding == dir_encoding_load ? "load" : "store"); | |
6060 | } | |
8d63c93e | 6061 | else if (mnem_p - 3 == dot_p |
a501d77e L |
6062 | && dot_p[1] == 'd' |
6063 | && dot_p[2] == '8') | |
97f31cb4 JB |
6064 | { |
6065 | if (i.disp_encoding == disp_encoding_default) | |
6066 | i.disp_encoding = disp_encoding_8bit; | |
6067 | else if (i.disp_encoding != disp_encoding_8bit) | |
6068 | as_warn (_("ignoring `.d8' suffix due to earlier `{disp<N>}'")); | |
6069 | } | |
8d63c93e | 6070 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
6071 | && dot_p[1] == 'd' |
6072 | && dot_p[2] == '3' | |
6073 | && dot_p[3] == '2') | |
97f31cb4 JB |
6074 | { |
6075 | if (i.disp_encoding == disp_encoding_default) | |
6076 | i.disp_encoding = disp_encoding_32bit; | |
6077 | else if (i.disp_encoding != disp_encoding_32bit) | |
6078 | as_warn (_("ignoring `.d32' suffix due to earlier `{disp<N>}'")); | |
6079 | } | |
30a55f88 L |
6080 | else |
6081 | goto check_suffix; | |
6082 | mnem_p = dot_p; | |
6083 | *dot_p = '\0'; | |
d3b01414 | 6084 | op_lookup (mnemonic); |
b6169b20 L |
6085 | } |
6086 | ||
d3b01414 | 6087 | if (!current_templates.start || !pass1) |
29b0f896 | 6088 | { |
d3b01414 | 6089 | current_templates.start = NULL; |
04784e33 | 6090 | |
dc1e8a47 | 6091 | check_suffix: |
1c529385 | 6092 | if (mnem_p > mnemonic) |
29b0f896 | 6093 | { |
1c529385 LH |
6094 | /* See if we can get a match by trimming off a suffix. */ |
6095 | switch (mnem_p[-1]) | |
29b0f896 | 6096 | { |
1c529385 LH |
6097 | case WORD_MNEM_SUFFIX: |
6098 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
6099 | i.suffix = SHORT_MNEM_SUFFIX; |
6100 | else | |
1c529385 LH |
6101 | /* Fall through. */ |
6102 | case BYTE_MNEM_SUFFIX: | |
6103 | case QWORD_MNEM_SUFFIX: | |
6104 | i.suffix = mnem_p[-1]; | |
29b0f896 | 6105 | mnem_p[-1] = '\0'; |
d3b01414 | 6106 | op_lookup (mnemonic); |
1c529385 LH |
6107 | break; |
6108 | case SHORT_MNEM_SUFFIX: | |
6109 | case LONG_MNEM_SUFFIX: | |
6110 | if (!intel_syntax) | |
6111 | { | |
6112 | i.suffix = mnem_p[-1]; | |
6113 | mnem_p[-1] = '\0'; | |
d3b01414 | 6114 | op_lookup (mnemonic); |
1c529385 LH |
6115 | } |
6116 | break; | |
6117 | ||
6118 | /* Intel Syntax. */ | |
6119 | case 'd': | |
6120 | if (intel_syntax) | |
6121 | { | |
6122 | if (intel_float_operand (mnemonic) == 1) | |
6123 | i.suffix = SHORT_MNEM_SUFFIX; | |
6124 | else | |
6125 | i.suffix = LONG_MNEM_SUFFIX; | |
6126 | mnem_p[-1] = '\0'; | |
d3b01414 | 6127 | op_lookup (mnemonic); |
1c529385 | 6128 | } |
04784e33 JB |
6129 | /* For compatibility reasons accept MOVSD and CMPSD without |
6130 | operands even in AT&T mode. */ | |
6131 | else if (*l == END_OF_INSN | |
6132 | || (is_space_char (*l) && l[1] == END_OF_INSN)) | |
6133 | { | |
6134 | mnem_p[-1] = '\0'; | |
d3b01414 JB |
6135 | op_lookup (mnemonic); |
6136 | if (current_templates.start != NULL | |
04784e33 | 6137 | /* MOVS or CMPS */ |
d3b01414 JB |
6138 | && (current_templates.start->base_opcode | 2) == 0xa6 |
6139 | && current_templates.start->opcode_space | |
04784e33 JB |
6140 | == SPACE_BASE |
6141 | && mnem_p[-2] == 's') | |
6142 | { | |
6143 | as_warn (_("found `%sd'; assuming `%sl' was meant"), | |
6144 | mnemonic, mnemonic); | |
6145 | i.suffix = LONG_MNEM_SUFFIX; | |
6146 | } | |
6147 | else | |
6148 | { | |
d3b01414 | 6149 | current_templates.start = NULL; |
04784e33 JB |
6150 | mnem_p[-1] = 'd'; |
6151 | } | |
6152 | } | |
1c529385 | 6153 | break; |
29b0f896 | 6154 | } |
29b0f896 | 6155 | } |
1c529385 | 6156 | |
d3b01414 | 6157 | if (!current_templates.start) |
29b0f896 | 6158 | { |
04784e33 JB |
6159 | if (pass1) |
6160 | as_bad (_("no such instruction: `%s'"), token_start); | |
29b0f896 AM |
6161 | return NULL; |
6162 | } | |
6163 | } | |
252b5132 | 6164 | |
d3b01414 JB |
6165 | if (current_templates.start->opcode_modifier.jump == JUMP |
6166 | || current_templates.start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
6167 | { |
6168 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
6169 | predict taken and predict not taken respectively. | |
6170 | I'm not sure that branch hints actually do anything on loop | |
6171 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
6172 | may work in the future and it doesn't hurt to accept them | |
6173 | now. */ | |
6174 | if (l[0] == ',' && l[1] == 'p') | |
6175 | { | |
6176 | if (l[2] == 't') | |
6177 | { | |
6178 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
6179 | return NULL; | |
6180 | l += 3; | |
6181 | } | |
6182 | else if (l[2] == 'n') | |
6183 | { | |
6184 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
6185 | return NULL; | |
6186 | l += 3; | |
6187 | } | |
6188 | } | |
6189 | } | |
6190 | /* Any other comma loses. */ | |
6191 | if (*l == ',') | |
6192 | { | |
6193 | as_bad (_("invalid character %s in mnemonic"), | |
6194 | output_invalid (*l)); | |
6195 | return NULL; | |
6196 | } | |
252b5132 | 6197 | |
29b0f896 | 6198 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e | 6199 | supported = 0; |
d3b01414 | 6200 | for (t = current_templates.start; t < current_templates.end; ++t) |
5c6af06e | 6201 | { |
c0f3af97 | 6202 | supported |= cpu_flags_match (t); |
9db83a32 JB |
6203 | |
6204 | if (i.suffix == QWORD_MNEM_SUFFIX && !q_suffix_allowed (t)) | |
6205 | supported &= ~CPU_FLAGS_64BIT_MATCH; | |
6206 | ||
c0f3af97 | 6207 | if (supported == CPU_FLAGS_PERFECT_MATCH) |
d59a54c2 | 6208 | return l; |
29b0f896 | 6209 | } |
3629bb00 | 6210 | |
9db83a32 JB |
6211 | if (pass1) |
6212 | { | |
6213 | if (supported & CPU_FLAGS_64BIT_MATCH) | |
6214 | i.error = unsupported_on_arch; | |
6215 | else | |
6216 | i.error = unsupported_64bit; | |
6217 | } | |
252b5132 | 6218 | |
548d0ee6 | 6219 | return NULL; |
29b0f896 | 6220 | } |
252b5132 | 6221 | |
29b0f896 | 6222 | static char * |
e3bb37b5 | 6223 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
6224 | { |
6225 | char *token_start; | |
3138f287 | 6226 | |
29b0f896 AM |
6227 | /* 1 if operand is pending after ','. */ |
6228 | unsigned int expecting_operand = 0; | |
252b5132 | 6229 | |
29b0f896 AM |
6230 | while (*l != END_OF_INSN) |
6231 | { | |
e68c3d59 JB |
6232 | /* Non-zero if operand parens not balanced. */ |
6233 | unsigned int paren_not_balanced = 0; | |
6234 | /* True if inside double quotes. */ | |
6235 | bool in_quotes = false; | |
6236 | ||
29b0f896 AM |
6237 | /* Skip optional white space before operand. */ |
6238 | if (is_space_char (*l)) | |
6239 | ++l; | |
d02603dc | 6240 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
6241 | { |
6242 | as_bad (_("invalid character %s before operand %d"), | |
6243 | output_invalid (*l), | |
6244 | i.operands + 1); | |
6245 | return NULL; | |
6246 | } | |
d02603dc | 6247 | token_start = l; /* After white space. */ |
e68c3d59 | 6248 | while (in_quotes || paren_not_balanced || *l != ',') |
29b0f896 AM |
6249 | { |
6250 | if (*l == END_OF_INSN) | |
6251 | { | |
e68c3d59 JB |
6252 | if (in_quotes) |
6253 | { | |
6254 | as_bad (_("unbalanced double quotes in operand %d."), | |
6255 | i.operands + 1); | |
6256 | return NULL; | |
6257 | } | |
29b0f896 AM |
6258 | if (paren_not_balanced) |
6259 | { | |
98ff9f1c JB |
6260 | know (!intel_syntax); |
6261 | as_bad (_("unbalanced parenthesis in operand %d."), | |
6262 | i.operands + 1); | |
29b0f896 AM |
6263 | return NULL; |
6264 | } | |
6265 | else | |
6266 | break; /* we are done */ | |
6267 | } | |
e68c3d59 JB |
6268 | else if (*l == '\\' && l[1] == '"') |
6269 | ++l; | |
6270 | else if (*l == '"') | |
6271 | in_quotes = !in_quotes; | |
6272 | else if (!in_quotes && !is_operand_char (*l) && !is_space_char (*l)) | |
29b0f896 AM |
6273 | { |
6274 | as_bad (_("invalid character %s in operand %d"), | |
6275 | output_invalid (*l), | |
6276 | i.operands + 1); | |
6277 | return NULL; | |
6278 | } | |
e68c3d59 | 6279 | if (!intel_syntax && !in_quotes) |
29b0f896 AM |
6280 | { |
6281 | if (*l == '(') | |
6282 | ++paren_not_balanced; | |
6283 | if (*l == ')') | |
6284 | --paren_not_balanced; | |
6285 | } | |
29b0f896 AM |
6286 | l++; |
6287 | } | |
6288 | if (l != token_start) | |
6289 | { /* Yes, we've read in another operand. */ | |
6290 | unsigned int operand_ok; | |
6291 | this_operand = i.operands++; | |
6292 | if (i.operands > MAX_OPERANDS) | |
6293 | { | |
6294 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
6295 | MAX_OPERANDS); | |
6296 | return NULL; | |
6297 | } | |
9d46ce34 | 6298 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
6299 | /* Now parse operand adding info to 'i' as we go along. */ |
6300 | END_STRING_AND_SAVE (l); | |
6301 | ||
1286ab78 L |
6302 | if (i.mem_operands > 1) |
6303 | { | |
6304 | as_bad (_("too many memory references for `%s'"), | |
6305 | mnemonic); | |
6306 | return 0; | |
6307 | } | |
6308 | ||
29b0f896 AM |
6309 | if (intel_syntax) |
6310 | operand_ok = | |
6311 | i386_intel_operand (token_start, | |
6312 | intel_float_operand (mnemonic)); | |
6313 | else | |
a7619375 | 6314 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
6315 | |
6316 | RESTORE_END_STRING (l); | |
6317 | if (!operand_ok) | |
6318 | return NULL; | |
6319 | } | |
6320 | else | |
6321 | { | |
6322 | if (expecting_operand) | |
6323 | { | |
6324 | expecting_operand_after_comma: | |
6325 | as_bad (_("expecting operand after ','; got nothing")); | |
6326 | return NULL; | |
6327 | } | |
6328 | if (*l == ',') | |
6329 | { | |
6330 | as_bad (_("expecting operand before ','; got nothing")); | |
6331 | return NULL; | |
6332 | } | |
6333 | } | |
7f3f1ea2 | 6334 | |
29b0f896 AM |
6335 | /* Now *l must be either ',' or END_OF_INSN. */ |
6336 | if (*l == ',') | |
6337 | { | |
6338 | if (*++l == END_OF_INSN) | |
6339 | { | |
6340 | /* Just skip it, if it's \n complain. */ | |
6341 | goto expecting_operand_after_comma; | |
6342 | } | |
6343 | expecting_operand = 1; | |
6344 | } | |
6345 | } | |
6346 | return l; | |
6347 | } | |
7f3f1ea2 | 6348 | |
050dfa73 | 6349 | static void |
783c187b | 6350 | swap_2_operands (unsigned int xchg1, unsigned int xchg2) |
050dfa73 MM |
6351 | { |
6352 | union i386_op temp_op; | |
40fb9820 | 6353 | i386_operand_type temp_type; |
c48dadc9 | 6354 | unsigned int temp_flags; |
050dfa73 | 6355 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 6356 | |
050dfa73 MM |
6357 | temp_type = i.types[xchg2]; |
6358 | i.types[xchg2] = i.types[xchg1]; | |
6359 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
6360 | |
6361 | temp_flags = i.flags[xchg2]; | |
6362 | i.flags[xchg2] = i.flags[xchg1]; | |
6363 | i.flags[xchg1] = temp_flags; | |
6364 | ||
050dfa73 MM |
6365 | temp_op = i.op[xchg2]; |
6366 | i.op[xchg2] = i.op[xchg1]; | |
6367 | i.op[xchg1] = temp_op; | |
c48dadc9 | 6368 | |
050dfa73 MM |
6369 | temp_reloc = i.reloc[xchg2]; |
6370 | i.reloc[xchg2] = i.reloc[xchg1]; | |
6371 | i.reloc[xchg1] = temp_reloc; | |
43234a1e | 6372 | |
c032bc4f JB |
6373 | temp_flags = i.imm_bits[xchg2]; |
6374 | i.imm_bits[xchg2] = i.imm_bits[xchg1]; | |
6375 | i.imm_bits[xchg1] = temp_flags; | |
6376 | ||
6225c532 | 6377 | if (i.mask.reg) |
43234a1e | 6378 | { |
6225c532 JB |
6379 | if (i.mask.operand == xchg1) |
6380 | i.mask.operand = xchg2; | |
6381 | else if (i.mask.operand == xchg2) | |
6382 | i.mask.operand = xchg1; | |
43234a1e | 6383 | } |
a5748e0d | 6384 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 6385 | { |
5273a3cd JB |
6386 | if (i.broadcast.operand == xchg1) |
6387 | i.broadcast.operand = xchg2; | |
6388 | else if (i.broadcast.operand == xchg2) | |
6389 | i.broadcast.operand = xchg1; | |
43234a1e | 6390 | } |
050dfa73 MM |
6391 | } |
6392 | ||
29b0f896 | 6393 | static void |
e3bb37b5 | 6394 | swap_operands (void) |
29b0f896 | 6395 | { |
b7c61d9a | 6396 | switch (i.operands) |
050dfa73 | 6397 | { |
c0f3af97 | 6398 | case 5: |
b7c61d9a | 6399 | case 4: |
4d456e3d | 6400 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 6401 | /* Fall through. */ |
b7c61d9a L |
6402 | case 3: |
6403 | case 2: | |
4d456e3d | 6404 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
6405 | break; |
6406 | default: | |
6407 | abort (); | |
29b0f896 | 6408 | } |
29b0f896 AM |
6409 | |
6410 | if (i.mem_operands == 2) | |
6411 | { | |
5e042380 | 6412 | const reg_entry *temp_seg; |
29b0f896 AM |
6413 | temp_seg = i.seg[0]; |
6414 | i.seg[0] = i.seg[1]; | |
6415 | i.seg[1] = temp_seg; | |
6416 | } | |
6417 | } | |
252b5132 | 6418 | |
29b0f896 AM |
6419 | /* Try to ensure constant immediates are represented in the smallest |
6420 | opcode possible. */ | |
6421 | static void | |
e3bb37b5 | 6422 | optimize_imm (void) |
29b0f896 AM |
6423 | { |
6424 | char guess_suffix = 0; | |
6425 | int op; | |
252b5132 | 6426 | |
29b0f896 AM |
6427 | if (i.suffix) |
6428 | guess_suffix = i.suffix; | |
6429 | else if (i.reg_operands) | |
6430 | { | |
6431 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
6432 | We can't do this properly yet, i.e. excluding special register |
6433 | instances, but the following works for instructions with | |
6434 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 6435 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
6436 | if (i.types[op].bitfield.class != Reg) |
6437 | continue; | |
6438 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 6439 | { |
40fb9820 L |
6440 | guess_suffix = BYTE_MNEM_SUFFIX; |
6441 | break; | |
6442 | } | |
bab6aec1 | 6443 | else if (i.types[op].bitfield.word) |
252b5132 | 6444 | { |
40fb9820 L |
6445 | guess_suffix = WORD_MNEM_SUFFIX; |
6446 | break; | |
6447 | } | |
bab6aec1 | 6448 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
6449 | { |
6450 | guess_suffix = LONG_MNEM_SUFFIX; | |
6451 | break; | |
6452 | } | |
bab6aec1 | 6453 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
6454 | { |
6455 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 6456 | break; |
252b5132 | 6457 | } |
29b0f896 | 6458 | } |
f79d55e1 JB |
6459 | else if ((flag_code == CODE_16BIT) |
6460 | ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W))) | |
29b0f896 | 6461 | guess_suffix = WORD_MNEM_SUFFIX; |
fb1c1058 JB |
6462 | else if (flag_code != CODE_64BIT |
6463 | || (!(i.prefix[REX_PREFIX] & REX_W) | |
6464 | /* A more generic (but also more involved) way of dealing | |
6465 | with the special case(s) would be to go look for | |
6466 | DefaultSize attributes on any of the templates. */ | |
d3b01414 | 6467 | && current_templates.start->mnem_off != MN_push)) |
5cc00775 | 6468 | guess_suffix = LONG_MNEM_SUFFIX; |
29b0f896 AM |
6469 | |
6470 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 6471 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
6472 | { |
6473 | switch (i.op[op].imms->X_op) | |
252b5132 | 6474 | { |
29b0f896 AM |
6475 | case O_constant: |
6476 | /* If a suffix is given, this operand may be shortened. */ | |
6477 | switch (guess_suffix) | |
252b5132 | 6478 | { |
29b0f896 | 6479 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
6480 | i.types[op].bitfield.imm32 = 1; |
6481 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
6482 | break; |
6483 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
6484 | i.types[op].bitfield.imm16 = 1; |
6485 | i.types[op].bitfield.imm32 = 1; | |
6486 | i.types[op].bitfield.imm32s = 1; | |
6487 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
6488 | break; |
6489 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
6490 | i.types[op].bitfield.imm8 = 1; |
6491 | i.types[op].bitfield.imm8s = 1; | |
6492 | i.types[op].bitfield.imm16 = 1; | |
6493 | i.types[op].bitfield.imm32 = 1; | |
6494 | i.types[op].bitfield.imm32s = 1; | |
6495 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 6496 | break; |
252b5132 | 6497 | } |
252b5132 | 6498 | |
29b0f896 AM |
6499 | /* If this operand is at most 16 bits, convert it |
6500 | to a signed 16 bit number before trying to see | |
6501 | whether it will fit in an even smaller size. | |
6502 | This allows a 16-bit operand such as $0xffe0 to | |
6503 | be recognised as within Imm8S range. */ | |
40fb9820 | 6504 | if ((i.types[op].bitfield.imm16) |
7e96fb68 | 6505 | && fits_in_unsigned_word (i.op[op].imms->X_add_number)) |
252b5132 | 6506 | { |
87ed972d JB |
6507 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
6508 | ^ 0x8000) - 0x8000); | |
29b0f896 | 6509 | } |
a28def75 L |
6510 | #ifdef BFD64 |
6511 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 6512 | if ((i.types[op].bitfield.imm32) |
7e96fb68 | 6513 | && fits_in_unsigned_long (i.op[op].imms->X_add_number)) |
29b0f896 AM |
6514 | { |
6515 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
6516 | ^ ((offsetT) 1 << 31)) | |
6517 | - ((offsetT) 1 << 31)); | |
6518 | } | |
a28def75 | 6519 | #endif |
40fb9820 | 6520 | i.types[op] |
c6fb90c8 L |
6521 | = operand_type_or (i.types[op], |
6522 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 6523 | |
29b0f896 AM |
6524 | /* We must avoid matching of Imm32 templates when 64bit |
6525 | only immediate is available. */ | |
6526 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 6527 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 6528 | break; |
252b5132 | 6529 | |
29b0f896 AM |
6530 | case O_absent: |
6531 | case O_register: | |
6532 | abort (); | |
6533 | ||
6534 | /* Symbols and expressions. */ | |
6535 | default: | |
9cd96992 JB |
6536 | /* Convert symbolic operand to proper sizes for matching, but don't |
6537 | prevent matching a set of insns that only supports sizes other | |
6538 | than those matching the insn suffix. */ | |
6539 | { | |
40fb9820 | 6540 | i386_operand_type mask, allowed; |
d3b01414 | 6541 | const insn_template *t = current_templates.start; |
9cd96992 | 6542 | |
0dfbf9d7 | 6543 | operand_type_set (&mask, 0); |
9cd96992 JB |
6544 | switch (guess_suffix) |
6545 | { | |
6546 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
6547 | mask.bitfield.imm64 = 1; |
6548 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
6549 | break; |
6550 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 6551 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
6552 | break; |
6553 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 6554 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
6555 | break; |
6556 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 6557 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
6558 | break; |
6559 | default: | |
9cd96992 JB |
6560 | break; |
6561 | } | |
8f0212ac JB |
6562 | |
6563 | allowed = operand_type_and (t->operand_types[op], mask); | |
d3b01414 | 6564 | while (++t < current_templates.end) |
8f0212ac JB |
6565 | { |
6566 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
6567 | allowed = operand_type_and (allowed, mask); | |
6568 | } | |
6569 | ||
0dfbf9d7 | 6570 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 6571 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 6572 | } |
29b0f896 | 6573 | break; |
252b5132 | 6574 | } |
29b0f896 AM |
6575 | } |
6576 | } | |
47926f60 | 6577 | |
29b0f896 | 6578 | /* Try to use the smallest displacement type too. */ |
0de704b9 JB |
6579 | static bool |
6580 | optimize_disp (const insn_template *t) | |
29b0f896 | 6581 | { |
0de704b9 | 6582 | unsigned int op; |
3e73aa7c | 6583 | |
0de704b9 JB |
6584 | if (!want_disp32 (t) |
6585 | && (!t->opcode_modifier.jump | |
6586 | || i.jumpabsolute || i.types[0].bitfield.baseindex)) | |
6587 | { | |
6588 | for (op = 0; op < i.operands; ++op) | |
6589 | { | |
6590 | const expressionS *exp = i.op[op].disps; | |
6591 | ||
6592 | if (!operand_type_check (i.types[op], disp)) | |
6593 | continue; | |
6594 | ||
6595 | if (exp->X_op != O_constant) | |
6596 | continue; | |
6597 | ||
6598 | /* Since displacement is signed extended to 64bit, don't allow | |
6599 | disp32 if it is out of range. */ | |
6600 | if (fits_in_signed_long (exp->X_add_number)) | |
6601 | continue; | |
6602 | ||
6603 | i.types[op].bitfield.disp32 = 0; | |
6604 | if (i.types[op].bitfield.baseindex) | |
6605 | { | |
6606 | as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"), | |
6607 | (uint64_t) exp->X_add_number); | |
6608 | return false; | |
6609 | } | |
6610 | } | |
6611 | } | |
6612 | ||
6613 | /* Don't optimize displacement for movabs since it only takes 64bit | |
6614 | displacement. */ | |
6615 | if (i.disp_encoding > disp_encoding_8bit | |
6616 | || (flag_code == CODE_64BIT && t->mnem_off == MN_movabs)) | |
6617 | return true; | |
6618 | ||
6619 | for (op = i.operands; op-- > 0;) | |
40fb9820 | 6620 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 6621 | { |
b300c311 | 6622 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 6623 | { |
91d6fa6a | 6624 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 6625 | |
91d6fa6a | 6626 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 6627 | { |
2f2be86b JB |
6628 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
6629 | i.op[op].disps = NULL; | |
b300c311 | 6630 | i.disp_operands--; |
f185acdd JB |
6631 | continue; |
6632 | } | |
6633 | ||
6634 | if (i.types[op].bitfield.disp16 | |
cd613c1f | 6635 | && fits_in_unsigned_word (op_disp)) |
f185acdd JB |
6636 | { |
6637 | /* If this operand is at most 16 bits, convert | |
6638 | to a signed 16 bit number and don't use 64bit | |
6639 | displacement. */ | |
6640 | op_disp = ((op_disp ^ 0x8000) - 0x8000); | |
6641 | i.types[op].bitfield.disp64 = 0; | |
b300c311 | 6642 | } |
f185acdd | 6643 | |
28a167a4 | 6644 | #ifdef BFD64 |
a50187b2 | 6645 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ |
a775efc8 JB |
6646 | if ((flag_code != CODE_64BIT |
6647 | ? i.types[op].bitfield.disp32 | |
0de704b9 JB |
6648 | : want_disp32 (t) |
6649 | && (!t->opcode_modifier.jump | |
a775efc8 | 6650 | || i.jumpabsolute || i.types[op].bitfield.baseindex)) |
a50187b2 | 6651 | && fits_in_unsigned_long (op_disp)) |
b300c311 | 6652 | { |
a50187b2 JB |
6653 | /* If this operand is at most 32 bits, convert |
6654 | to a signed 32 bit number and don't use 64bit | |
6655 | displacement. */ | |
6656 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
6657 | i.types[op].bitfield.disp64 = 0; | |
6658 | i.types[op].bitfield.disp32 = 1; | |
6659 | } | |
28a167a4 | 6660 | |
a50187b2 JB |
6661 | if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp)) |
6662 | { | |
6663 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 6664 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 6665 | } |
28a167a4 | 6666 | #endif |
40fb9820 | 6667 | if ((i.types[op].bitfield.disp32 |
40fb9820 | 6668 | || i.types[op].bitfield.disp16) |
b5014f7a | 6669 | && fits_in_disp8 (op_disp)) |
40fb9820 | 6670 | i.types[op].bitfield.disp8 = 1; |
77c59789 JB |
6671 | |
6672 | i.op[op].disps->X_add_number = op_disp; | |
252b5132 | 6673 | } |
67a4f2b7 AO |
6674 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
6675 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
6676 | { | |
6677 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
6678 | i.op[op].disps, 0, i.reloc[op]); | |
2f2be86b | 6679 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
67a4f2b7 AO |
6680 | } |
6681 | else | |
b300c311 | 6682 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 6683 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 6684 | } |
0de704b9 JB |
6685 | |
6686 | return true; | |
29b0f896 AM |
6687 | } |
6688 | ||
4a1b91ea L |
6689 | /* Return 1 if there is a match in broadcast bytes between operand |
6690 | GIVEN and instruction template T. */ | |
6691 | ||
6692 | static INLINE int | |
6693 | match_broadcast_size (const insn_template *t, unsigned int given) | |
6694 | { | |
6695 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
6696 | && i.types[given].bitfield.byte) | |
6697 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
6698 | && i.types[given].bitfield.word) | |
6699 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
6700 | && i.types[given].bitfield.dword) | |
6701 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
6702 | && i.types[given].bitfield.qword)); | |
6703 | } | |
6704 | ||
6c30d220 L |
6705 | /* Check if operands are valid for the instruction. */ |
6706 | ||
6707 | static int | |
6708 | check_VecOperands (const insn_template *t) | |
6709 | { | |
43234a1e | 6710 | unsigned int op; |
e2195274 | 6711 | i386_cpu_flags cpu; |
e2195274 JB |
6712 | |
6713 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
6714 | any one operand are implicity requiring AVX512VL support if the actual | |
6715 | operand size is YMMword or XMMword. Since this function runs after | |
a61cb9db L |
6716 | template matching, there's no need to check for YMMword/XMMword in |
6717 | the template. */ | |
734dfd1c | 6718 | cpu = cpu_flags_and (cpu_flags_from_attr (t->cpu), avx512); |
e2195274 | 6719 | if (!cpu_flags_all_zero (&cpu) |
734dfd1c | 6720 | && !is_cpu (t, CpuAVX512VL) |
a6f3add0 | 6721 | && !cpu_arch_flags.bitfield.cpuavx512vl |
6177c84d | 6722 | && (!t->opcode_modifier.vex || need_evex_encoding (t))) |
e2195274 JB |
6723 | { |
6724 | for (op = 0; op < t->operands; ++op) | |
6725 | { | |
6726 | if (t->operand_types[op].bitfield.zmmword | |
6727 | && (i.types[op].bitfield.ymmword | |
6728 | || i.types[op].bitfield.xmmword)) | |
6729 | { | |
54294d73 | 6730 | i.error = operand_size_mismatch; |
e2195274 JB |
6731 | return 1; |
6732 | } | |
6733 | } | |
6734 | } | |
43234a1e | 6735 | |
22c36940 JB |
6736 | /* Somewhat similarly, templates specifying both AVX and AVX2 are |
6737 | requiring AVX2 support if the actual operand size is YMMword. */ | |
a5e91879 | 6738 | if (maybe_cpu (t, CpuAVX) && maybe_cpu (t, CpuAVX2) |
22c36940 JB |
6739 | && !cpu_arch_flags.bitfield.cpuavx2) |
6740 | { | |
6741 | for (op = 0; op < t->operands; ++op) | |
6742 | { | |
6743 | if (t->operand_types[op].bitfield.xmmword | |
6744 | && i.types[op].bitfield.ymmword) | |
6745 | { | |
54294d73 | 6746 | i.error = operand_size_mismatch; |
22c36940 JB |
6747 | return 1; |
6748 | } | |
6749 | } | |
6750 | } | |
6751 | ||
6c30d220 | 6752 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 6753 | if (!t->opcode_modifier.sib |
6c30d220 | 6754 | && i.index_reg |
1b54b8d7 JB |
6755 | && (i.index_reg->reg_type.bitfield.xmmword |
6756 | || i.index_reg->reg_type.bitfield.ymmword | |
6757 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
6758 | { |
6759 | i.error = unsupported_vector_index_register; | |
6760 | return 1; | |
6761 | } | |
6762 | ||
ad8ecc81 | 6763 | /* Check if default mask is allowed. */ |
255571cd | 6764 | if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK |
6225c532 | 6765 | && (!i.mask.reg || i.mask.reg->reg_num == 0)) |
ad8ecc81 MZ |
6766 | { |
6767 | i.error = no_default_mask; | |
6768 | return 1; | |
6769 | } | |
6770 | ||
7bab8ab5 JB |
6771 | /* For VSIB byte, we need a vector register for index, and all vector |
6772 | registers must be distinct. */ | |
260cd341 | 6773 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
6774 | { |
6775 | if (!i.index_reg | |
63112cd6 | 6776 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 6777 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 6778 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 6779 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 6780 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 6781 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
6782 | { |
6783 | i.error = invalid_vsib_address; | |
6784 | return 1; | |
6785 | } | |
6786 | ||
6225c532 JB |
6787 | gas_assert (i.reg_operands == 2 || i.mask.reg); |
6788 | if (i.reg_operands == 2 && !i.mask.reg) | |
43234a1e | 6789 | { |
3528c362 | 6790 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6791 | gas_assert (i.types[0].bitfield.xmmword |
6792 | || i.types[0].bitfield.ymmword); | |
3528c362 | 6793 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6794 | gas_assert (i.types[2].bitfield.xmmword |
6795 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
6796 | if (operand_check == check_none) |
6797 | return 0; | |
6798 | if (register_number (i.op[0].regs) | |
6799 | != register_number (i.index_reg) | |
6800 | && register_number (i.op[2].regs) | |
6801 | != register_number (i.index_reg) | |
6802 | && register_number (i.op[0].regs) | |
6803 | != register_number (i.op[2].regs)) | |
6804 | return 0; | |
6805 | if (operand_check == check_error) | |
6806 | { | |
6807 | i.error = invalid_vector_register_set; | |
6808 | return 1; | |
6809 | } | |
6810 | as_warn (_("mask, index, and destination registers should be distinct")); | |
6811 | } | |
6225c532 | 6812 | else if (i.reg_operands == 1 && i.mask.reg) |
8444f82a | 6813 | { |
3528c362 | 6814 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
6815 | && (i.types[1].bitfield.xmmword |
6816 | || i.types[1].bitfield.ymmword | |
6817 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
6818 | && (register_number (i.op[1].regs) |
6819 | == register_number (i.index_reg))) | |
6820 | { | |
6821 | if (operand_check == check_error) | |
6822 | { | |
6823 | i.error = invalid_vector_register_set; | |
6824 | return 1; | |
6825 | } | |
6826 | if (operand_check != check_none) | |
6827 | as_warn (_("index and destination registers should be distinct")); | |
6828 | } | |
6829 | } | |
43234a1e | 6830 | } |
7bab8ab5 | 6831 | |
fc141319 L |
6832 | /* For AMX instructions with 3 TMM register operands, all operands |
6833 | must be distinct. */ | |
6834 | if (i.reg_operands == 3 | |
6835 | && t->operand_types[0].bitfield.tmmword | |
6836 | && (i.op[0].regs == i.op[1].regs | |
6837 | || i.op[0].regs == i.op[2].regs | |
6838 | || i.op[1].regs == i.op[2].regs)) | |
6839 | { | |
6840 | i.error = invalid_tmm_register_set; | |
6841 | return 1; | |
260cd341 LC |
6842 | } |
6843 | ||
0cc78721 CL |
6844 | /* For some special instructions require that destination must be distinct |
6845 | from source registers. */ | |
255571cd | 6846 | if (t->opcode_modifier.operandconstraint == DISTINCT_DEST) |
0cc78721 CL |
6847 | { |
6848 | unsigned int dest_reg = i.operands - 1; | |
6849 | ||
6850 | know (i.operands >= 3); | |
6851 | ||
6852 | /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */ | |
6853 | if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs | |
6854 | || (i.reg_operands > 2 | |
6855 | && i.op[dest_reg - 2].regs == i.op[dest_reg].regs)) | |
6856 | { | |
6857 | i.error = invalid_dest_and_src_register_set; | |
6858 | return 1; | |
6859 | } | |
6860 | } | |
6861 | ||
43234a1e L |
6862 | /* Check if broadcast is supported by the instruction and is applied |
6863 | to the memory operand. */ | |
a5748e0d | 6864 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 6865 | { |
8e6e0792 | 6866 | i386_operand_type type, overlap; |
43234a1e L |
6867 | |
6868 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 6869 | and its broadcast bytes match the memory operand. */ |
5273a3cd | 6870 | op = i.broadcast.operand; |
8e6e0792 | 6871 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 6872 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 6873 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 6874 | && !match_broadcast_size (t, op))) |
43234a1e L |
6875 | { |
6876 | bad_broadcast: | |
6877 | i.error = unsupported_broadcast; | |
6878 | return 1; | |
6879 | } | |
8e6e0792 JB |
6880 | |
6881 | operand_type_set (&type, 0); | |
a5748e0d | 6882 | switch (get_broadcast_bytes (t, false)) |
8e6e0792 | 6883 | { |
4a1b91ea L |
6884 | case 2: |
6885 | type.bitfield.word = 1; | |
6886 | break; | |
6887 | case 4: | |
6888 | type.bitfield.dword = 1; | |
6889 | break; | |
8e6e0792 JB |
6890 | case 8: |
6891 | type.bitfield.qword = 1; | |
6892 | break; | |
6893 | case 16: | |
6894 | type.bitfield.xmmword = 1; | |
6895 | break; | |
6896 | case 32: | |
4fc85f37 JB |
6897 | if (vector_size < VSZ256) |
6898 | goto bad_broadcast; | |
8e6e0792 JB |
6899 | type.bitfield.ymmword = 1; |
6900 | break; | |
6901 | case 64: | |
4fc85f37 JB |
6902 | if (vector_size < VSZ512) |
6903 | goto bad_broadcast; | |
8e6e0792 JB |
6904 | type.bitfield.zmmword = 1; |
6905 | break; | |
6906 | default: | |
6907 | goto bad_broadcast; | |
6908 | } | |
6909 | ||
6910 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
6911 | if (t->operand_types[op].bitfield.class == RegSIMD |
6912 | && t->operand_types[op].bitfield.byte | |
6913 | + t->operand_types[op].bitfield.word | |
6914 | + t->operand_types[op].bitfield.dword | |
6915 | + t->operand_types[op].bitfield.qword > 1) | |
6916 | { | |
6917 | overlap.bitfield.xmmword = 0; | |
6918 | overlap.bitfield.ymmword = 0; | |
6919 | overlap.bitfield.zmmword = 0; | |
6920 | } | |
8e6e0792 JB |
6921 | if (operand_type_all_zero (&overlap)) |
6922 | goto bad_broadcast; | |
6923 | ||
9c19e9ec | 6924 | if (t->opcode_modifier.checkoperandsize) |
8e6e0792 JB |
6925 | { |
6926 | unsigned int j; | |
6927 | ||
e2195274 | 6928 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
6929 | for (j = 0; j < i.operands; ++j) |
6930 | { | |
6931 | if (j != op | |
6932 | && !operand_type_register_match(i.types[j], | |
6933 | t->operand_types[j], | |
6934 | type, | |
6935 | t->operand_types[op])) | |
6936 | goto bad_broadcast; | |
6937 | } | |
6938 | } | |
43234a1e L |
6939 | } |
6940 | /* If broadcast is supported in this instruction, we need to check if | |
6941 | operand of one-element size isn't specified without broadcast. */ | |
6942 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
6943 | { | |
6944 | /* Find memory operand. */ | |
6945 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6946 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
6947 | break; |
6948 | gas_assert (op < i.operands); | |
6949 | /* Check size of the memory operand. */ | |
4a1b91ea | 6950 | if (match_broadcast_size (t, op)) |
43234a1e L |
6951 | { |
6952 | i.error = broadcast_needed; | |
6953 | return 1; | |
6954 | } | |
6955 | } | |
c39e5b26 JB |
6956 | else |
6957 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
6958 | |
6959 | /* Check if requested masking is supported. */ | |
6225c532 | 6960 | if (i.mask.reg) |
43234a1e | 6961 | { |
b1c79256 | 6962 | if (!t->opcode_modifier.masking) |
ae2387fe | 6963 | { |
b1c79256 JB |
6964 | i.error = unsupported_masking; |
6965 | return 1; | |
6966 | } | |
6967 | ||
6968 | /* Common rules for masking: | |
6969 | - mask register destinations permit only zeroing-masking, without | |
6970 | that actually being expressed by a {z} operand suffix or EVEX.z, | |
6971 | - memory destinations allow only merging-masking, | |
6972 | - scatter/gather insns (i.e. ones using vSIB) only allow merging- | |
6973 | masking. */ | |
6974 | if (i.mask.zeroing | |
6975 | && (t->operand_types[t->operands - 1].bitfield.class == RegMask | |
6976 | || (i.flags[t->operands - 1] & Operand_Mem) | |
6977 | || t->opcode_modifier.sib)) | |
6978 | { | |
6979 | i.error = unsupported_masking; | |
6980 | return 1; | |
ae2387fe | 6981 | } |
43234a1e L |
6982 | } |
6983 | ||
6984 | /* Check if masking is applied to dest operand. */ | |
6225c532 | 6985 | if (i.mask.reg && (i.mask.operand != i.operands - 1)) |
43234a1e L |
6986 | { |
6987 | i.error = mask_not_on_destination; | |
6988 | return 1; | |
6989 | } | |
6990 | ||
43234a1e | 6991 | /* Check RC/SAE. */ |
ca5312a2 | 6992 | if (i.rounding.type != rc_none) |
43234a1e | 6993 | { |
a80195f1 | 6994 | if (!t->opcode_modifier.sae |
cf665fee JB |
6995 | || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding) |
6996 | || i.mem_operands) | |
43234a1e L |
6997 | { |
6998 | i.error = unsupported_rc_sae; | |
6999 | return 1; | |
7000 | } | |
cf665fee JB |
7001 | |
7002 | /* Non-EVEX.LIG forms need to have a ZMM register as at least one | |
7003 | operand. */ | |
7004 | if (t->opcode_modifier.evex != EVEXLIG) | |
7bab8ab5 | 7005 | { |
cf665fee JB |
7006 | for (op = 0; op < t->operands; ++op) |
7007 | if (i.types[op].bitfield.zmmword) | |
7008 | break; | |
7009 | if (op >= t->operands) | |
7010 | { | |
7011 | i.error = operand_size_mismatch; | |
7012 | return 1; | |
7013 | } | |
7bab8ab5 | 7014 | } |
6c30d220 L |
7015 | } |
7016 | ||
da4977e0 | 7017 | /* Check the special Imm4 cases; must be the first operand. */ |
734dfd1c | 7018 | if (is_cpu (t, CpuXOP) && t->operands == 5) |
da4977e0 JB |
7019 | { |
7020 | if (i.op[0].imms->X_op != O_constant | |
7021 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
7022 | { | |
7023 | i.error = bad_imm4; | |
7024 | return 1; | |
7025 | } | |
7026 | ||
7027 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
7028 | operand_type_set (&i.types[0], 0); | |
7029 | } | |
7030 | ||
43234a1e | 7031 | /* Check vector Disp8 operand. */ |
b5014f7a | 7032 | if (t->opcode_modifier.disp8memshift |
a6f3add0 | 7033 | && (!t->opcode_modifier.vex |
6177c84d | 7034 | || need_evex_encoding (t)) |
1a42a9fe | 7035 | && i.disp_encoding <= disp_encoding_8bit) |
43234a1e | 7036 | { |
9b345ce8 | 7037 | if (i.broadcast.type || i.broadcast.bytes) |
4a1b91ea | 7038 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 7039 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 7040 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
7041 | else |
7042 | { | |
125ff819 | 7043 | const i386_operand_type *type = NULL, *fallback = NULL; |
7091c612 JB |
7044 | |
7045 | i.memshift = 0; | |
7046 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 7047 | if (i.flags[op] & Operand_Mem) |
7091c612 | 7048 | { |
4174bfff JB |
7049 | if (t->opcode_modifier.evex == EVEXLIG) |
7050 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
7051 | else if (t->operand_types[op].bitfield.xmmword | |
7052 | + t->operand_types[op].bitfield.ymmword | |
7053 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
7054 | type = &t->operand_types[op]; |
7055 | else if (!i.types[op].bitfield.unspecified) | |
7056 | type = &i.types[op]; | |
125ff819 JB |
7057 | else /* Ambiguities get resolved elsewhere. */ |
7058 | fallback = &t->operand_types[op]; | |
7091c612 | 7059 | } |
3528c362 | 7060 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 7061 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
7062 | { |
7063 | if (i.types[op].bitfield.zmmword) | |
7064 | i.memshift = 6; | |
7065 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
7066 | i.memshift = 5; | |
7067 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
7068 | i.memshift = 4; | |
7069 | } | |
7070 | ||
125ff819 JB |
7071 | if (!type && !i.memshift) |
7072 | type = fallback; | |
7091c612 JB |
7073 | if (type) |
7074 | { | |
7075 | if (type->bitfield.zmmword) | |
7076 | i.memshift = 6; | |
7077 | else if (type->bitfield.ymmword) | |
7078 | i.memshift = 5; | |
7079 | else if (type->bitfield.xmmword) | |
7080 | i.memshift = 4; | |
7081 | } | |
7082 | ||
7083 | /* For the check in fits_in_disp8(). */ | |
7084 | if (i.memshift == 0) | |
7085 | i.memshift = -1; | |
7086 | } | |
43234a1e L |
7087 | |
7088 | for (op = 0; op < i.operands; op++) | |
7089 | if (operand_type_check (i.types[op], disp) | |
7090 | && i.op[op].disps->X_op == O_constant) | |
7091 | { | |
b5014f7a | 7092 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 7093 | { |
b5014f7a JB |
7094 | i.types[op].bitfield.disp8 = 1; |
7095 | return 0; | |
43234a1e | 7096 | } |
b5014f7a | 7097 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
7098 | } |
7099 | } | |
b5014f7a JB |
7100 | |
7101 | i.memshift = 0; | |
43234a1e | 7102 | |
6c30d220 L |
7103 | return 0; |
7104 | } | |
7105 | ||
da4977e0 | 7106 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
7107 | |
7108 | static int | |
da4977e0 | 7109 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 7110 | { |
da4977e0 JB |
7111 | if (i.vec_encoding == vex_encoding_error) |
7112 | { | |
7113 | i.error = unsupported; | |
7114 | return 1; | |
7115 | } | |
7116 | ||
4fc85f37 JB |
7117 | /* Vector size restrictions. */ |
7118 | if ((vector_size < VSZ512 | |
fa88a361 | 7119 | && t->opcode_modifier.evex == EVEX512) |
4fc85f37 JB |
7120 | || (vector_size < VSZ256 |
7121 | && (t->opcode_modifier.evex == EVEX256 | |
fa88a361 | 7122 | || t->opcode_modifier.vex == VEX256))) |
4fc85f37 | 7123 | { |
54294d73 | 7124 | i.error = unsupported_vector_size; |
4fc85f37 JB |
7125 | return 1; |
7126 | } | |
7127 | ||
a6f3add0 JB |
7128 | if (i.vec_encoding == vex_encoding_evex |
7129 | || i.vec_encoding == vex_encoding_evex512) | |
43234a1e | 7130 | { |
86fa6981 | 7131 | /* This instruction must be encoded with EVEX prefix. */ |
706ce984 | 7132 | if (!t->opcode_modifier.evex) |
86fa6981 | 7133 | { |
54294d73 | 7134 | i.error = no_evex_encoding; |
86fa6981 L |
7135 | return 1; |
7136 | } | |
7137 | return 0; | |
43234a1e L |
7138 | } |
7139 | ||
a683cc34 | 7140 | if (!t->opcode_modifier.vex) |
86fa6981 L |
7141 | { |
7142 | /* This instruction template doesn't have VEX prefix. */ | |
7143 | if (i.vec_encoding != vex_encoding_default) | |
7144 | { | |
54294d73 | 7145 | i.error = no_vex_encoding; |
86fa6981 L |
7146 | return 1; |
7147 | } | |
7148 | return 0; | |
7149 | } | |
a683cc34 | 7150 | |
a683cc34 SP |
7151 | return 0; |
7152 | } | |
7153 | ||
80d61d8d CL |
7154 | /* Check if Egprs operands are valid for the instruction. */ |
7155 | ||
7156 | static bool | |
7157 | check_EgprOperands (const insn_template *t) | |
7158 | { | |
7159 | if (!t->opcode_modifier.noegpr) | |
7160 | return 0; | |
7161 | ||
7162 | for (unsigned int op = 0; op < i.operands; op++) | |
7163 | { | |
7164 | if (i.types[op].bitfield.class != Reg) | |
7165 | continue; | |
7166 | ||
7167 | if (i.op[op].regs->reg_flags & RegRex2) | |
7168 | { | |
7169 | i.error = register_type_mismatch; | |
7170 | return 1; | |
7171 | } | |
7172 | } | |
7173 | ||
7174 | if ((i.index_reg && (i.index_reg->reg_flags & RegRex2)) | |
7175 | || (i.base_reg && (i.base_reg->reg_flags & RegRex2))) | |
7176 | { | |
7177 | i.error = unsupported_EGPR_for_addressing; | |
7178 | return 1; | |
7179 | } | |
7180 | ||
7181 | /* Check if pseudo prefix {rex2} is valid. */ | |
7182 | if (i.rex2_encoding) | |
7183 | { | |
7184 | i.error = invalid_pseudo_prefix; | |
7185 | return 1; | |
7186 | } | |
7187 | ||
7188 | return 0; | |
7189 | } | |
7190 | ||
08a98d4c MZ |
7191 | /* Check if APX operands are valid for the instruction. */ |
7192 | static bool | |
7193 | check_APX_operands (const insn_template *t) | |
7194 | { | |
7195 | /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers. | |
7196 | */ | |
7197 | switch (t->mnem_off) | |
7198 | { | |
7199 | case MN_pop2: | |
7200 | case MN_pop2p: | |
7201 | if (register_number (i.op[0].regs) == register_number (i.op[1].regs)) | |
7202 | { | |
7203 | i.error = invalid_dest_register_set; | |
7204 | return 1; | |
7205 | } | |
7206 | /* fall through */ | |
7207 | case MN_push2: | |
7208 | case MN_push2p: | |
7209 | if (register_number (i.op[0].regs) == 4 | |
7210 | || register_number (i.op[1].regs) == 4) | |
7211 | { | |
7212 | i.error = unsupported_rsp_register; | |
7213 | return 1; | |
7214 | } | |
7215 | break; | |
7216 | } | |
7217 | return 0; | |
7218 | } | |
7219 | ||
6967f19d HL |
7220 | /* Check if the instruction use the REX registers or REX prefix. */ |
7221 | static bool | |
7222 | check_Rex_required (void) | |
7223 | { | |
7224 | for (unsigned int op = 0; op < i.operands; op++) | |
7225 | { | |
7226 | if (i.types[op].bitfield.class != Reg) | |
7227 | continue; | |
7228 | ||
7229 | if (i.op[op].regs->reg_flags & (RegRex | RegRex64)) | |
7230 | return true; | |
7231 | } | |
7232 | ||
7233 | if ((i.index_reg && (i.index_reg->reg_flags & (RegRex | RegRex64))) | |
7234 | || (i.base_reg && (i.base_reg->reg_flags & (RegRex | RegRex64)))) | |
7235 | return true; | |
7236 | ||
7237 | /* Check pseudo prefix {rex} are valid. */ | |
7238 | return i.rex_encoding; | |
7239 | } | |
7240 | ||
7241 | /* Optimize APX NDD insns to legacy insns. */ | |
7242 | static unsigned int | |
7243 | can_convert_NDD_to_legacy (const insn_template *t) | |
7244 | { | |
7245 | unsigned int match_dest_op = ~0; | |
7246 | ||
7247 | if (!i.tm.opcode_modifier.nf | |
7248 | && i.reg_operands >= 2) | |
7249 | { | |
7250 | unsigned int dest = i.operands - 1; | |
7251 | unsigned int src1 = i.operands - 2; | |
7252 | unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0; | |
7253 | ||
7254 | if (i.types[src1].bitfield.class == Reg | |
7255 | && i.op[src1].regs == i.op[dest].regs) | |
7256 | match_dest_op = src1; | |
7257 | /* If the first operand is the same as the third operand, | |
7258 | these instructions need to support the ability to commutative | |
7259 | the first two operands and still not change the semantics in order | |
7260 | to be optimized. */ | |
7261 | else if (optimize > 1 | |
7262 | && t->opcode_modifier.commutative | |
7263 | && i.types[src2].bitfield.class == Reg | |
7264 | && i.op[src2].regs == i.op[dest].regs) | |
7265 | match_dest_op = src2; | |
7266 | } | |
7267 | return match_dest_op; | |
7268 | } | |
7269 | ||
7b94647a JB |
7270 | /* Helper function for the progress() macro in match_template(). */ |
7271 | static INLINE enum i386_error progress (enum i386_error new, | |
7272 | enum i386_error last, | |
7273 | unsigned int line, unsigned int *line_p) | |
7274 | { | |
7275 | if (line <= *line_p) | |
7276 | return last; | |
7277 | *line_p = line; | |
7278 | return new; | |
7279 | } | |
7280 | ||
d3ce72d0 | 7281 | static const insn_template * |
83b16ac6 | 7282 | match_template (char mnem_suffix) |
29b0f896 AM |
7283 | { |
7284 | /* Points to template once we've found it. */ | |
d3ce72d0 | 7285 | const insn_template *t; |
40fb9820 | 7286 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 7287 | i386_operand_type overlap4; |
29b0f896 | 7288 | unsigned int found_reverse_match; |
40fb9820 | 7289 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 7290 | int addr_prefix_disp; |
7b94647a JB |
7291 | unsigned int j, size_match, check_register, errline = __LINE__; |
7292 | enum i386_error specific_error = number_of_operands_mismatch; | |
7293 | #define progress(err) progress (err, specific_error, __LINE__, &errline) | |
29b0f896 | 7294 | |
c0f3af97 L |
7295 | #if MAX_OPERANDS != 5 |
7296 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
7297 | #endif |
7298 | ||
29b0f896 | 7299 | found_reverse_match = 0; |
539e75ad | 7300 | addr_prefix_disp = -1; |
40fb9820 | 7301 | |
d3b01414 | 7302 | for (t = current_templates.start; t < current_templates.end; t++) |
29b0f896 | 7303 | { |
539e75ad | 7304 | addr_prefix_disp = -1; |
dbbc8b7e | 7305 | found_reverse_match = 0; |
539e75ad | 7306 | |
7b94647a | 7307 | /* Must have right number of operands. */ |
29b0f896 AM |
7308 | if (i.operands != t->operands) |
7309 | continue; | |
7310 | ||
50aecf8c | 7311 | /* Check processor support. */ |
7b94647a | 7312 | specific_error = progress (unsupported); |
45a4bb20 | 7313 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
7314 | continue; |
7315 | ||
e1d4d893 | 7316 | /* Check AT&T mnemonic. */ |
7b94647a | 7317 | specific_error = progress (unsupported_with_intel_mnemonic); |
35266cb1 JB |
7318 | if (!intel_syntax && intel_mnemonic |
7319 | && t->opcode_modifier.dialect == ATT_MNEMONIC) | |
1efbbeb4 L |
7320 | continue; |
7321 | ||
4b5aaf5f | 7322 | /* Check AT&T/Intel syntax. */ |
7b94647a | 7323 | specific_error = progress (unsupported_syntax); |
7d3182d6 | 7324 | if (intel_syntax |
35266cb1 JB |
7325 | ? t->opcode_modifier.dialect >= ATT_SYNTAX |
7326 | : t->opcode_modifier.dialect == INTEL_SYNTAX) | |
1efbbeb4 L |
7327 | continue; |
7328 | ||
4b5aaf5f L |
7329 | /* Check Intel64/AMD64 ISA. */ |
7330 | switch (isa64) | |
7331 | { | |
7332 | default: | |
7333 | /* Default: Don't accept Intel64. */ | |
7334 | if (t->opcode_modifier.isa64 == INTEL64) | |
7335 | continue; | |
7336 | break; | |
7337 | case amd64: | |
7338 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
7339 | if (t->opcode_modifier.isa64 >= INTEL64) | |
7340 | continue; | |
7341 | break; | |
7342 | case intel64: | |
7343 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 7344 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
7345 | continue; |
7346 | break; | |
7347 | } | |
7348 | ||
dc2be329 | 7349 | /* Check the suffix. */ |
7b94647a | 7350 | specific_error = progress (invalid_instruction_suffix); |
7505bb03 JB |
7351 | if ((t->opcode_modifier.no_bsuf && mnem_suffix == BYTE_MNEM_SUFFIX) |
7352 | || (t->opcode_modifier.no_wsuf && mnem_suffix == WORD_MNEM_SUFFIX) | |
7353 | || (t->opcode_modifier.no_lsuf && mnem_suffix == LONG_MNEM_SUFFIX) | |
7354 | || (t->opcode_modifier.no_ssuf && mnem_suffix == SHORT_MNEM_SUFFIX) | |
7355 | || (t->opcode_modifier.no_qsuf && mnem_suffix == QWORD_MNEM_SUFFIX)) | |
83b16ac6 | 7356 | continue; |
29b0f896 | 7357 | |
7b94647a | 7358 | specific_error = progress (operand_size_mismatch); |
3ac21baa JB |
7359 | size_match = operand_size_match (t); |
7360 | if (!size_match) | |
7d5e4556 | 7361 | continue; |
539e75ad | 7362 | |
6f2f06be JB |
7363 | /* This is intentionally not |
7364 | ||
0cfa3eb3 | 7365 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
7366 | |
7367 | as the case of a missing * on the operand is accepted (perhaps with | |
7368 | a warning, issued further down). */ | |
7b94647a | 7369 | specific_error = progress (operand_type_mismatch); |
0cfa3eb3 | 7370 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
7b94647a | 7371 | continue; |
6f2f06be | 7372 | |
a4d3acd2 JB |
7373 | /* In Intel syntax, normally we can check for memory operand size when |
7374 | there is no mnemonic suffix. But jmp and call have 2 different | |
7375 | encodings with Dword memory operand size. Skip the "near" one | |
7376 | (permitting a register operand) when "far" was requested. */ | |
7377 | if (i.far_branch | |
7378 | && t->opcode_modifier.jump == JUMP_ABSOLUTE | |
7379 | && t->operand_types[0].bitfield.class == Reg) | |
7380 | continue; | |
7381 | ||
5c07affc L |
7382 | for (j = 0; j < MAX_OPERANDS; j++) |
7383 | operand_types[j] = t->operand_types[j]; | |
7384 | ||
9db83a32 | 7385 | /* In general, don't allow 32-bit operands on pre-386. */ |
7b94647a JB |
7386 | specific_error = progress (mnem_suffix ? invalid_instruction_suffix |
7387 | : operand_size_mismatch); | |
4873e243 | 7388 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
9db83a32 JB |
7389 | if (i.suffix == LONG_MNEM_SUFFIX |
7390 | && !cpu_arch_flags.bitfield.cpui386 | |
45aa61fe | 7391 | && (intel_syntax |
3cd7f3e3 | 7392 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
76d3f746 JB |
7393 | && !intel_float_operand (insn_name (t))) |
7394 | : intel_float_operand (insn_name (t)) != 2) | |
4873e243 JB |
7395 | && (t->operands == i.imm_operands |
7396 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
7397 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
7398 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
7399 | || (operand_types[j].bitfield.class != RegMMX | |
7400 | && operand_types[j].bitfield.class != RegSIMD | |
7401 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 7402 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
7403 | continue; |
7404 | ||
29b0f896 | 7405 | /* Do not verify operands when there are none. */ |
e365e234 | 7406 | if (!t->operands) |
da4977e0 JB |
7407 | { |
7408 | if (VEX_check_encoding (t)) | |
7409 | { | |
7b94647a | 7410 | specific_error = progress (i.error); |
da4977e0 JB |
7411 | continue; |
7412 | } | |
7413 | ||
80d61d8d CL |
7414 | /* Check if pseudo prefix {rex2} is valid. */ |
7415 | if (t->opcode_modifier.noegpr && i.rex2_encoding) | |
7416 | { | |
7417 | specific_error = progress (invalid_pseudo_prefix); | |
7418 | continue; | |
7419 | } | |
7420 | ||
da4977e0 JB |
7421 | /* We've found a match; break out of loop. */ |
7422 | break; | |
7423 | } | |
252b5132 | 7424 | |
48bcea9f JB |
7425 | if (!t->opcode_modifier.jump |
7426 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
7427 | { | |
7428 | /* There should be only one Disp operand. */ | |
7429 | for (j = 0; j < MAX_OPERANDS; j++) | |
7430 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 7431 | break; |
48bcea9f JB |
7432 | if (j < MAX_OPERANDS) |
7433 | { | |
5b7c81bd | 7434 | bool override = (i.prefix[ADDR_PREFIX] != 0); |
48bcea9f JB |
7435 | |
7436 | addr_prefix_disp = j; | |
7437 | ||
a775efc8 JB |
7438 | /* Address size prefix will turn Disp64 operand into Disp32 and |
7439 | Disp32/Disp16 one into Disp16/Disp32 respectively. */ | |
48bcea9f | 7440 | switch (flag_code) |
40fb9820 | 7441 | { |
48bcea9f JB |
7442 | case CODE_16BIT: |
7443 | override = !override; | |
7444 | /* Fall through. */ | |
7445 | case CODE_32BIT: | |
7446 | if (operand_types[j].bitfield.disp32 | |
7447 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 7448 | { |
48bcea9f JB |
7449 | operand_types[j].bitfield.disp16 = override; |
7450 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 7451 | } |
a775efc8 | 7452 | gas_assert (!operand_types[j].bitfield.disp64); |
48bcea9f JB |
7453 | break; |
7454 | ||
7455 | case CODE_64BIT: | |
a775efc8 | 7456 | if (operand_types[j].bitfield.disp64) |
40fb9820 | 7457 | { |
a775efc8 | 7458 | gas_assert (!operand_types[j].bitfield.disp32); |
48bcea9f | 7459 | operand_types[j].bitfield.disp32 = override; |
a775efc8 | 7460 | operand_types[j].bitfield.disp64 = !override; |
40fb9820 | 7461 | } |
48bcea9f JB |
7462 | operand_types[j].bitfield.disp16 = 0; |
7463 | break; | |
40fb9820 | 7464 | } |
539e75ad | 7465 | } |
48bcea9f | 7466 | } |
539e75ad | 7467 | |
56ffb741 | 7468 | /* We check register size if needed. */ |
9c19e9ec | 7469 | if (t->opcode_modifier.checkoperandsize) |
e2195274 JB |
7470 | { |
7471 | check_register = (1 << t->operands) - 1; | |
a5748e0d | 7472 | if (i.broadcast.type || i.broadcast.bytes) |
5273a3cd | 7473 | check_register &= ~(1 << i.broadcast.operand); |
e2195274 JB |
7474 | } |
7475 | else | |
7476 | check_register = 0; | |
7477 | ||
c6fb90c8 | 7478 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
7479 | switch (t->operands) |
7480 | { | |
7481 | case 1: | |
40fb9820 | 7482 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 | 7483 | continue; |
ae9a0a51 JB |
7484 | |
7485 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
7486 | {store} pseudo prefix on an applicable insn. */ | |
7487 | if (!t->opcode_modifier.modrm | |
7488 | && i.reg_operands == 1 | |
7489 | && ((i.dir_encoding == dir_encoding_load | |
7490 | && t->mnem_off != MN_pop) | |
7491 | || (i.dir_encoding == dir_encoding_store | |
7492 | && t->mnem_off != MN_push)) | |
7493 | /* Avoid BSWAP. */ | |
7494 | && t->mnem_off != MN_bswap) | |
7495 | continue; | |
29b0f896 | 7496 | break; |
ae9a0a51 | 7497 | |
29b0f896 | 7498 | case 2: |
33eaf5de | 7499 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
7500 | only in 32bit mode and we can use opcode 0x90. In 64bit |
7501 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
7502 | zero-extend %eax to %rax. */ | |
ae9a0a51 JB |
7503 | if (t->base_opcode == 0x90 |
7504 | && t->opcode_space == SPACE_BASE) | |
7505 | { | |
7506 | if (flag_code == CODE_64BIT | |
7507 | && i.types[0].bitfield.instance == Accum | |
7508 | && i.types[0].bitfield.dword | |
7509 | && i.types[1].bitfield.instance == Accum) | |
7510 | continue; | |
7511 | ||
7512 | /* Allow the ModR/M encoding to be requested by using the | |
7513 | {load} or {store} pseudo prefix. */ | |
7514 | if (i.dir_encoding == dir_encoding_load | |
7515 | || i.dir_encoding == dir_encoding_store) | |
7516 | continue; | |
7517 | } | |
e3669c7f JB |
7518 | |
7519 | if (t->base_opcode == MOV_AX_DISP32 | |
ddb62495 | 7520 | && t->opcode_space == SPACE_BASE |
69196391 | 7521 | && t->mnem_off != MN_movabs) |
e3669c7f JB |
7522 | { |
7523 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ | |
7524 | if (i.reloc[0] == BFD_RELOC_386_GOT32) | |
7525 | continue; | |
7526 | ||
7527 | /* xrelease mov %eax, <disp> is another special case. It must not | |
7528 | match the accumulator-only encoding of mov. */ | |
7529 | if (i.hle_prefix) | |
7530 | continue; | |
ae9a0a51 JB |
7531 | |
7532 | /* Allow the ModR/M encoding to be requested by using a suitable | |
7533 | {load} or {store} pseudo prefix. */ | |
7534 | if (i.dir_encoding == (i.types[0].bitfield.instance == Accum | |
7535 | ? dir_encoding_store | |
7536 | : dir_encoding_load) | |
7537 | && !i.types[0].bitfield.disp64 | |
7538 | && !i.types[1].bitfield.disp64) | |
7539 | continue; | |
7540 | } | |
7541 | ||
7542 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
7543 | {store} pseudo prefix on an applicable insn. */ | |
7544 | if (!t->opcode_modifier.modrm | |
7545 | && i.reg_operands == 1 | |
7546 | && i.imm_operands == 1 | |
7547 | && (i.dir_encoding == dir_encoding_load | |
7548 | || i.dir_encoding == dir_encoding_store) | |
7549 | && t->opcode_space == SPACE_BASE) | |
7550 | { | |
7551 | if (t->base_opcode == 0xb0 /* mov $imm, %reg */ | |
7552 | && i.dir_encoding == dir_encoding_store) | |
7553 | continue; | |
7554 | ||
7555 | if ((t->base_opcode | 0x38) == 0x3c /* <alu> $imm, %acc */ | |
7556 | && (t->base_opcode != 0x3c /* cmp $imm, %acc */ | |
7557 | || i.dir_encoding == dir_encoding_load)) | |
7558 | continue; | |
7559 | ||
7560 | if (t->base_opcode == 0xa8 /* test $imm, %acc */ | |
7561 | && i.dir_encoding == dir_encoding_load) | |
7562 | continue; | |
e3669c7f | 7563 | } |
f5eb1d70 JB |
7564 | /* Fall through. */ |
7565 | ||
7566 | case 3: | |
3ac21baa JB |
7567 | if (!(size_match & MATCH_STRAIGHT)) |
7568 | goto check_reverse; | |
64c49ab3 JB |
7569 | /* Reverse direction of operands if swapping is possible in the first |
7570 | place (operands need to be symmetric) and | |
7571 | - the load form is requested, and the template is a store form, | |
7572 | - the store form is requested, and the template is a load form, | |
7573 | - the non-default (swapped) form is requested. */ | |
7574 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
3083f376 | 7575 | |
7576 | j = i.operands - 1 - (t->opcode_space == SPACE_EVEXMAP4 | |
7577 | && t->opcode_modifier.vexvvvv); | |
7578 | ||
f5eb1d70 | 7579 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
7580 | && !operand_type_all_zero (&overlap1)) |
7581 | switch (i.dir_encoding) | |
7582 | { | |
7583 | case dir_encoding_load: | |
3083f376 | 7584 | if (operand_type_check (operand_types[j], anymem) |
dfd69174 | 7585 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
7586 | goto check_reverse; |
7587 | break; | |
7588 | ||
7589 | case dir_encoding_store: | |
3083f376 | 7590 | if (!operand_type_check (operand_types[j], anymem) |
dfd69174 | 7591 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
7592 | goto check_reverse; |
7593 | break; | |
7594 | ||
7595 | case dir_encoding_swap: | |
7596 | goto check_reverse; | |
7597 | ||
7598 | case dir_encoding_default: | |
7599 | break; | |
7600 | } | |
3083f376 | 7601 | |
86fa6981 | 7602 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
7603 | if ((i.dir_encoding == dir_encoding_store |
7604 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
7605 | && i.mem_operands == 0 |
7606 | && t->opcode_modifier.load) | |
fa99fab2 | 7607 | continue; |
1a0670f3 | 7608 | /* Fall through. */ |
f48ff2ae | 7609 | case 4: |
c0f3af97 | 7610 | case 5: |
c6fb90c8 | 7611 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
7612 | if (!operand_type_match (overlap0, i.types[0]) |
7613 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 7614 | || ((check_register & 3) == 3 |
dc821c5f | 7615 | && !operand_type_register_match (i.types[0], |
40fb9820 | 7616 | operand_types[0], |
dc821c5f | 7617 | i.types[1], |
40fb9820 | 7618 | operand_types[1]))) |
29b0f896 | 7619 | { |
7b94647a JB |
7620 | specific_error = progress (i.error); |
7621 | ||
29b0f896 | 7622 | /* Check if other direction is valid ... */ |
38e314eb | 7623 | if (!t->opcode_modifier.d) |
29b0f896 AM |
7624 | continue; |
7625 | ||
dc1e8a47 | 7626 | check_reverse: |
3ac21baa JB |
7627 | if (!(size_match & MATCH_REVERSE)) |
7628 | continue; | |
29b0f896 | 7629 | /* Try reversing direction of operands. */ |
734dfd1c | 7630 | j = is_cpu (t, CpuFMA4) |
3083f376 | 7631 | || is_cpu (t, CpuXOP) |
7632 | || is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1; | |
8bd915b7 JB |
7633 | overlap0 = operand_type_and (i.types[0], operand_types[j]); |
7634 | overlap1 = operand_type_and (i.types[j], operand_types[0]); | |
c975cec5 | 7635 | overlap2 = operand_type_and (i.types[1], operand_types[1]); |
3083f376 | 7636 | gas_assert (t->operands != 3 || !check_register |
7637 | || is_cpu (t, CpuAPX_F)); | |
40fb9820 | 7638 | if (!operand_type_match (overlap0, i.types[0]) |
8bd915b7 | 7639 | || !operand_type_match (overlap1, i.types[j]) |
c975cec5 JB |
7640 | || (t->operands == 3 |
7641 | && !operand_type_match (overlap2, i.types[1])) | |
45664ddb | 7642 | || (check_register |
dc821c5f | 7643 | && !operand_type_register_match (i.types[0], |
8bd915b7 JB |
7644 | operand_types[j], |
7645 | i.types[j], | |
45664ddb | 7646 | operand_types[0]))) |
29b0f896 AM |
7647 | { |
7648 | /* Does not match either direction. */ | |
7b94647a | 7649 | specific_error = progress (i.error); |
29b0f896 AM |
7650 | continue; |
7651 | } | |
ac9226cf | 7652 | /* found_reverse_match holds which variant of D |
29b0f896 | 7653 | we've found. */ |
38e314eb JB |
7654 | if (!t->opcode_modifier.d) |
7655 | found_reverse_match = 0; | |
7656 | else if (operand_types[0].bitfield.tbyte) | |
ac9226cf | 7657 | { |
4943d587 JB |
7658 | if (t->opcode_modifier.operandconstraint != UGH) |
7659 | found_reverse_match = Opcode_FloatD; | |
bd782808 JB |
7660 | else |
7661 | found_reverse_match = ~0; | |
ac9226cf | 7662 | /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */ |
bd782808 | 7663 | if ((t->extension_opcode & 4) |
ac9226cf JB |
7664 | && (intel_syntax || intel_mnemonic)) |
7665 | found_reverse_match |= Opcode_FloatR; | |
7666 | } | |
734dfd1c | 7667 | else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)) |
8bd915b7 JB |
7668 | { |
7669 | found_reverse_match = Opcode_VexW; | |
7670 | goto check_operands_345; | |
7671 | } | |
3083f376 | 7672 | else if (is_cpu (t, CpuAPX_F) && i.operands == 3) |
7673 | { | |
7674 | found_reverse_match = Opcode_D; | |
7675 | goto check_operands_345; | |
7676 | } | |
ddb62495 JB |
7677 | else if (t->opcode_space != SPACE_BASE |
7678 | && (t->opcode_space != SPACE_0F | |
2c735193 JB |
7679 | /* MOV to/from CR/DR/TR, as an exception, follow |
7680 | the base opcode space encoding model. */ | |
7681 | || (t->base_opcode | 7) != 0x27)) | |
dbbc8b7e | 7682 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e |
2c735193 | 7683 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
a33ef3c2 | 7684 | else if (!t->opcode_modifier.commutative) |
38e314eb | 7685 | found_reverse_match = Opcode_D; |
a33ef3c2 JB |
7686 | else |
7687 | found_reverse_match = ~0; | |
29b0f896 | 7688 | } |
f48ff2ae | 7689 | else |
29b0f896 | 7690 | { |
f48ff2ae | 7691 | /* Found a forward 2 operand match here. */ |
8bd915b7 | 7692 | check_operands_345: |
d1cbb4db L |
7693 | switch (t->operands) |
7694 | { | |
c0f3af97 | 7695 | case 5: |
3d0738af | 7696 | overlap4 = operand_type_and (i.types[4], operand_types[4]); |
c0f3af97 | 7697 | if (!operand_type_match (overlap4, i.types[4]) |
dc821c5f | 7698 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 7699 | operand_types[3], |
c0f3af97 L |
7700 | i.types[4], |
7701 | operand_types[4])) | |
7b94647a JB |
7702 | { |
7703 | specific_error = progress (i.error); | |
7704 | continue; | |
7705 | } | |
1a0670f3 | 7706 | /* Fall through. */ |
f48ff2ae | 7707 | case 4: |
3d0738af | 7708 | overlap3 = operand_type_and (i.types[3], operand_types[3]); |
40fb9820 | 7709 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
7710 | || ((check_register & 0xa) == 0xa |
7711 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
7712 | operand_types[1], |
7713 | i.types[3], | |
e2195274 JB |
7714 | operand_types[3])) |
7715 | || ((check_register & 0xc) == 0xc | |
7716 | && !operand_type_register_match (i.types[2], | |
7717 | operand_types[2], | |
7718 | i.types[3], | |
7719 | operand_types[3]))) | |
7b94647a JB |
7720 | { |
7721 | specific_error = progress (i.error); | |
7722 | continue; | |
7723 | } | |
1a0670f3 | 7724 | /* Fall through. */ |
f48ff2ae | 7725 | case 3: |
3d0738af | 7726 | overlap2 = operand_type_and (i.types[2], operand_types[2]); |
40fb9820 | 7727 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
7728 | || ((check_register & 5) == 5 |
7729 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
7730 | operand_types[0], |
7731 | i.types[2], | |
e2195274 JB |
7732 | operand_types[2])) |
7733 | || ((check_register & 6) == 6 | |
7734 | && !operand_type_register_match (i.types[1], | |
7735 | operand_types[1], | |
7736 | i.types[2], | |
7737 | operand_types[2]))) | |
7b94647a JB |
7738 | { |
7739 | specific_error = progress (i.error); | |
7740 | continue; | |
7741 | } | |
f48ff2ae L |
7742 | break; |
7743 | } | |
29b0f896 | 7744 | } |
f48ff2ae | 7745 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
7746 | slip through to break. */ |
7747 | } | |
c0f3af97 | 7748 | |
9bb4d860 L |
7749 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ |
7750 | if (VEX_check_encoding (t)) | |
da4977e0 | 7751 | { |
7b94647a | 7752 | specific_error = progress (i.error); |
da4977e0 JB |
7753 | continue; |
7754 | } | |
7755 | ||
80d61d8d CL |
7756 | /* Check if EGPR operands(r16-r31) are valid. */ |
7757 | if (check_EgprOperands (t)) | |
7758 | { | |
7759 | specific_error = progress (i.error); | |
7760 | continue; | |
7761 | } | |
7762 | ||
9bb4d860 L |
7763 | /* Check if vector operands are valid. */ |
7764 | if (check_VecOperands (t)) | |
5614d22c | 7765 | { |
7b94647a | 7766 | specific_error = progress (i.error); |
5614d22c JB |
7767 | continue; |
7768 | } | |
a683cc34 | 7769 | |
08a98d4c MZ |
7770 | /* Check if APX operands are valid. */ |
7771 | if (check_APX_operands (t)) | |
7772 | { | |
7773 | specific_error = progress (i.error); | |
7774 | continue; | |
7775 | } | |
7776 | ||
58bceb18 | 7777 | /* Check whether to use the shorter VEX encoding for certain insns where |
39bb3ade JB |
7778 | the EVEX encoding comes first in the table. This requires the respective |
7779 | AVX-* feature to be explicitly enabled. | |
7780 | ||
7781 | Most of the respective insns have just a single EVEX and a single VEX | |
7782 | template. The one that's presently different is generated using the | |
7783 | Vxy / Exy constructs: There are 3 suffix-less EVEX forms, the latter | |
7784 | two of which may fall back to their two corresponding VEX forms. */ | |
7785 | j = t->mnem_off != MN_vcvtneps2bf16 ? 1 : 2; | |
d3b01414 | 7786 | if ((t == current_templates.start || j > 1) |
58bceb18 JB |
7787 | && t->opcode_modifier.disp8memshift |
7788 | && !t->opcode_modifier.vex | |
6177c84d | 7789 | && !need_evex_encoding (t) |
d3b01414 | 7790 | && t + j < current_templates.end |
39bb3ade | 7791 | && t[j].opcode_modifier.vex) |
58bceb18 JB |
7792 | { |
7793 | i386_cpu_flags cpu; | |
7794 | unsigned int memshift = i.memshift; | |
7795 | ||
7796 | i.memshift = 0; | |
39bb3ade JB |
7797 | cpu = cpu_flags_and (cpu_flags_from_attr (t[j].cpu), |
7798 | cpu_arch_isa_flags); | |
58bceb18 JB |
7799 | if (!cpu_flags_all_zero (&cpu) |
7800 | && (!i.types[0].bitfield.disp8 | |
7801 | || !operand_type_check (i.types[0], disp) | |
7802 | || i.op[0].disps->X_op != O_constant | |
7803 | || fits_in_disp8 (i.op[0].disps->X_add_number))) | |
7804 | { | |
7805 | specific_error = progress (internal_error); | |
39bb3ade | 7806 | t += j - 1; |
58bceb18 JB |
7807 | continue; |
7808 | } | |
7809 | i.memshift = memshift; | |
7810 | } | |
7811 | ||
6967f19d HL |
7812 | /* If we can optimize a NDD insn to legacy insn, like |
7813 | add %r16, %r8, %r8 -> add %r16, %r8, | |
7814 | add %r8, %r16, %r8 -> add %r16, %r8, then rematch template. | |
7815 | Note that the semantics have not been changed. */ | |
7816 | if (optimize | |
7817 | && !i.no_optimize | |
7818 | && i.vec_encoding != vex_encoding_evex | |
7819 | && t + 1 < current_templates.end | |
7820 | && !t[1].opcode_modifier.evex | |
7821 | && t[1].opcode_space <= SPACE_0F38 | |
7822 | && t->opcode_modifier.vexvvvv == VexVVVV_DST | |
7823 | && (i.types[i.operands - 1].bitfield.dword | |
7824 | || i.types[i.operands - 1].bitfield.qword)) | |
7825 | { | |
7826 | unsigned int match_dest_op = can_convert_NDD_to_legacy (t); | |
7827 | ||
7828 | if (match_dest_op != (unsigned int) ~0) | |
7829 | { | |
7830 | size_match = true; | |
7831 | /* We ensure that the next template has the same input | |
7832 | operands as the original matching template by the first | |
7833 | opernd (ATT). To avoid someone support new NDD insns and | |
7834 | put it in the wrong position. */ | |
7835 | overlap0 = operand_type_and (i.types[0], | |
7836 | t[1].operand_types[0]); | |
7837 | if (t->opcode_modifier.d) | |
7838 | overlap1 = operand_type_and (i.types[0], | |
7839 | t[1].operand_types[1]); | |
7840 | if (!operand_type_match (overlap0, i.types[0]) | |
7841 | && (!t->opcode_modifier.d | |
7842 | || !operand_type_match (overlap1, i.types[0]))) | |
7843 | size_match = false; | |
7844 | ||
7845 | if (size_match | |
7846 | && (t[1].opcode_space <= SPACE_0F | |
7847 | /* Some non-legacy-map0/1 insns can be shorter when | |
7848 | legacy-encoded and when no REX prefix is required. */ | |
7849 | || (!check_EgprOperands (t + 1) | |
7850 | && !check_Rex_required () | |
7851 | && !i.op[i.operands - 1].regs->reg_type.bitfield.qword))) | |
7852 | { | |
7853 | if (i.operands > 2 && match_dest_op == i.operands - 3) | |
7854 | swap_2_operands (match_dest_op, i.operands - 2); | |
7855 | ||
7856 | --i.operands; | |
7857 | --i.reg_operands; | |
7858 | ||
7859 | specific_error = progress (internal_error); | |
7860 | continue; | |
7861 | } | |
7862 | ||
7863 | } | |
7864 | } | |
7865 | ||
29b0f896 AM |
7866 | /* We've found a match; break out of loop. */ |
7867 | break; | |
7868 | } | |
7869 | ||
7b94647a JB |
7870 | #undef progress |
7871 | ||
d3b01414 | 7872 | if (t == current_templates.end) |
29b0f896 AM |
7873 | { |
7874 | /* We found no match. */ | |
04784e33 | 7875 | i.error = specific_error; |
fa99fab2 | 7876 | return NULL; |
29b0f896 | 7877 | } |
252b5132 | 7878 | |
29b0f896 AM |
7879 | if (!quiet_warnings) |
7880 | { | |
7881 | if (!intel_syntax | |
0cfa3eb3 | 7882 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
76d3f746 | 7883 | as_warn (_("indirect %s without `*'"), insn_name (t)); |
29b0f896 | 7884 | |
40fb9820 | 7885 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 7886 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
7887 | { |
7888 | /* Warn them that a data or address size prefix doesn't | |
7889 | affect assembly of the next line of code. */ | |
76d3f746 | 7890 | as_warn (_("stand-alone `%s' prefix"), insn_name (t)); |
29b0f896 AM |
7891 | } |
7892 | } | |
7893 | ||
7894 | /* Copy the template we found. */ | |
9a182d04 | 7895 | install_template (t); |
539e75ad L |
7896 | |
7897 | if (addr_prefix_disp != -1) | |
7898 | i.tm.operand_types[addr_prefix_disp] | |
7899 | = operand_types[addr_prefix_disp]; | |
7900 | ||
8bd915b7 | 7901 | switch (found_reverse_match) |
29b0f896 | 7902 | { |
8bd915b7 JB |
7903 | case 0: |
7904 | break; | |
7905 | ||
bd782808 JB |
7906 | case Opcode_FloatR: |
7907 | case Opcode_FloatR | Opcode_FloatD: | |
7908 | i.tm.extension_opcode ^= Opcode_FloatR >> 3; | |
7909 | found_reverse_match &= Opcode_FloatD; | |
7910 | ||
7911 | /* Fall through. */ | |
8bd915b7 | 7912 | default: |
dfd69174 JB |
7913 | /* If we found a reverse match we must alter the opcode direction |
7914 | bit and clear/flip the regmem modifier one. found_reverse_match | |
7915 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
7916 | |
7917 | i.tm.base_opcode ^= found_reverse_match; | |
7918 | ||
3083f376 | 7919 | if (i.tm.opcode_space == SPACE_EVEXMAP4) |
7920 | goto swap_first_2; | |
7921 | ||
dfd69174 JB |
7922 | /* Certain SIMD insns have their load forms specified in the opcode |
7923 | table, and hence we need to _set_ RegMem instead of clearing it. | |
7924 | We need to avoid setting the bit though on insns like KMOVW. */ | |
7925 | i.tm.opcode_modifier.regmem | |
7926 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
7927 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
7928 | && !i.tm.opcode_modifier.regmem; | |
a33ef3c2 JB |
7929 | |
7930 | /* Fall through. */ | |
7931 | case ~0: | |
7932 | i.tm.operand_types[0] = operand_types[i.operands - 1]; | |
7933 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
8bd915b7 JB |
7934 | break; |
7935 | ||
7936 | case Opcode_VexW: | |
7937 | /* Only the first two register operands need reversing, alongside | |
7938 | flipping VEX.W. */ | |
7939 | i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1; | |
7940 | ||
3083f376 | 7941 | swap_first_2: |
8bd915b7 JB |
7942 | j = i.tm.operand_types[0].bitfield.imm8; |
7943 | i.tm.operand_types[j] = operand_types[j + 1]; | |
7944 | i.tm.operand_types[j + 1] = operand_types[j]; | |
7945 | break; | |
29b0f896 AM |
7946 | } |
7947 | ||
fa99fab2 | 7948 | return t; |
29b0f896 AM |
7949 | } |
7950 | ||
7951 | static int | |
e3bb37b5 | 7952 | check_string (void) |
29b0f896 | 7953 | { |
51c8edf6 JB |
7954 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
7955 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 7956 | |
5e042380 | 7957 | if (i.seg[op] != NULL && i.seg[op] != reg_es) |
29b0f896 | 7958 | { |
51c8edf6 | 7959 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
76d3f746 | 7960 | insn_name (&i.tm), |
51c8edf6 JB |
7961 | intel_syntax ? i.tm.operands - es_op : es_op + 1, |
7962 | register_prefix); | |
7963 | return 0; | |
29b0f896 | 7964 | } |
51c8edf6 JB |
7965 | |
7966 | /* There's only ever one segment override allowed per instruction. | |
7967 | This instruction possibly has a legal segment override on the | |
7968 | second operand, so copy the segment to where non-string | |
7969 | instructions store it, allowing common code. */ | |
7970 | i.seg[op] = i.seg[1]; | |
7971 | ||
29b0f896 AM |
7972 | return 1; |
7973 | } | |
7974 | ||
7975 | static int | |
543613e9 | 7976 | process_suffix (void) |
29b0f896 | 7977 | { |
7fc69528 | 7978 | bool is_movx = false; |
8b65b895 | 7979 | |
29b0f896 AM |
7980 | /* If matched instruction specifies an explicit instruction mnemonic |
7981 | suffix, use it. */ | |
673fe0f0 | 7982 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 7983 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 7984 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 7985 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 7986 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 7987 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 7988 | else if (i.reg_operands |
c8f8eebc | 7989 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
255571cd | 7990 | && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG) |
29b0f896 | 7991 | { |
65fca059 | 7992 | unsigned int numop = i.operands; |
389d00a5 JB |
7993 | |
7994 | /* MOVSX/MOVZX */ | |
ddb62495 | 7995 | is_movx = (i.tm.opcode_space == SPACE_0F |
389d00a5 | 7996 | && (i.tm.base_opcode | 8) == 0xbe) |
ddb62495 | 7997 | || (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 7998 | && i.tm.base_opcode == 0x63 |
734dfd1c | 7999 | && is_cpu (&i.tm, Cpu64)); |
389d00a5 | 8000 | |
65fca059 JB |
8001 | /* movsx/movzx want only their source operand considered here, for the |
8002 | ambiguity checking below. The suffix will be replaced afterwards | |
8003 | to represent the destination (register). */ | |
389d00a5 | 8004 | if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63)) |
65fca059 JB |
8005 | --i.operands; |
8006 | ||
643bb870 | 8007 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
7fc69528 | 8008 | if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword) |
643bb870 JB |
8009 | i.rex |= REX_W; |
8010 | ||
29b0f896 | 8011 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 8012 | based on GPR operands. */ |
29b0f896 AM |
8013 | if (!i.suffix) |
8014 | { | |
8015 | /* We take i.suffix from the last register operand specified, | |
8016 | Destination register type is more significant than source | |
381d071f L |
8017 | register type. crc32 in SSE4.2 prefers source register |
8018 | type. */ | |
7fc69528 | 8019 | unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands; |
20592a94 | 8020 | |
1a035124 JB |
8021 | while (op--) |
8022 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
8023 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
8024 | { | |
8025 | if (i.types[op].bitfield.class != Reg) | |
8026 | continue; | |
8027 | if (i.types[op].bitfield.byte) | |
8028 | i.suffix = BYTE_MNEM_SUFFIX; | |
8029 | else if (i.types[op].bitfield.word) | |
8030 | i.suffix = WORD_MNEM_SUFFIX; | |
8031 | else if (i.types[op].bitfield.dword) | |
8032 | i.suffix = LONG_MNEM_SUFFIX; | |
8033 | else if (i.types[op].bitfield.qword) | |
8034 | i.suffix = QWORD_MNEM_SUFFIX; | |
8035 | else | |
8036 | continue; | |
8037 | break; | |
8038 | } | |
65fca059 JB |
8039 | |
8040 | /* As an exception, movsx/movzx silently default to a byte source | |
8041 | in AT&T mode. */ | |
389d00a5 | 8042 | if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax) |
65fca059 | 8043 | i.suffix = BYTE_MNEM_SUFFIX; |
29b0f896 AM |
8044 | } |
8045 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
8046 | { | |
1cb0ab18 | 8047 | if (!check_byte_reg ()) |
29b0f896 AM |
8048 | return 0; |
8049 | } | |
8050 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
8051 | { | |
1cb0ab18 | 8052 | if (!check_long_reg ()) |
29b0f896 AM |
8053 | return 0; |
8054 | } | |
8055 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
8056 | { | |
1cb0ab18 | 8057 | if (!check_qword_reg ()) |
29b0f896 AM |
8058 | return 0; |
8059 | } | |
8060 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
8061 | { | |
1cb0ab18 | 8062 | if (!check_word_reg ()) |
29b0f896 AM |
8063 | return 0; |
8064 | } | |
3cd7f3e3 L |
8065 | else if (intel_syntax |
8066 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
8067 | /* Do nothing if the instruction is going to ignore the prefix. */ |
8068 | ; | |
8069 | else | |
8070 | abort (); | |
65fca059 JB |
8071 | |
8072 | /* Undo the movsx/movzx change done above. */ | |
8073 | i.operands = numop; | |
29b0f896 | 8074 | } |
3cd7f3e3 L |
8075 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
8076 | && !i.suffix) | |
29b0f896 | 8077 | { |
13e600d0 JB |
8078 | i.suffix = stackop_size; |
8079 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
8080 | { |
8081 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
8082 | .code16gcc directive to support 16-bit mode with | |
8083 | 32-bit address. For IRET without a suffix, generate | |
8084 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
8085 | handler. */ | |
13e600d0 JB |
8086 | if (i.tm.base_opcode == 0xcf) |
8087 | { | |
8088 | i.suffix = WORD_MNEM_SUFFIX; | |
8089 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
8090 | } | |
8091 | /* Warn about changed behavior for segment register push/pop. */ | |
8092 | else if ((i.tm.base_opcode | 1) == 0x07) | |
8093 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
76d3f746 | 8094 | insn_name (&i.tm)); |
06f74c5c | 8095 | } |
29b0f896 | 8096 | } |
c006a730 | 8097 | else if (!i.suffix |
0cfa3eb3 JB |
8098 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
8099 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
8100 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
ddb62495 | 8101 | || (i.tm.opcode_space == SPACE_0F |
389d00a5 | 8102 | && i.tm.base_opcode == 0x01 /* [ls][gi]dt */ |
64e74474 | 8103 | && i.tm.extension_opcode <= 3))) |
9306ca4a JB |
8104 | { |
8105 | switch (flag_code) | |
8106 | { | |
8107 | case CODE_64BIT: | |
40fb9820 | 8108 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 8109 | { |
828c2a25 JB |
8110 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
8111 | || i.tm.opcode_modifier.no_lsuf) | |
8112 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
8113 | break; |
8114 | } | |
1a0670f3 | 8115 | /* Fall through. */ |
9306ca4a | 8116 | case CODE_32BIT: |
40fb9820 | 8117 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
8118 | i.suffix = LONG_MNEM_SUFFIX; |
8119 | break; | |
8120 | case CODE_16BIT: | |
40fb9820 | 8121 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
8122 | i.suffix = WORD_MNEM_SUFFIX; |
8123 | break; | |
8124 | } | |
8125 | } | |
252b5132 | 8126 | |
c006a730 | 8127 | if (!i.suffix |
3cd7f3e3 | 8128 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
8129 | /* Also cover lret/retf/iret in 64-bit mode. */ |
8130 | || (flag_code == CODE_64BIT | |
8131 | && !i.tm.opcode_modifier.no_lsuf | |
8132 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 8133 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
8134 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
8135 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
8136 | /* Accept FLDENV et al without suffix. */ |
8137 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 8138 | { |
6c0946d0 | 8139 | unsigned int suffixes, evex = 0; |
c006a730 JB |
8140 | |
8141 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
8142 | if (!i.tm.opcode_modifier.no_wsuf) | |
8143 | suffixes |= 1 << 1; | |
8144 | if (!i.tm.opcode_modifier.no_lsuf) | |
8145 | suffixes |= 1 << 2; | |
c006a730 JB |
8146 | if (!i.tm.opcode_modifier.no_ssuf) |
8147 | suffixes |= 1 << 4; | |
8148 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
8149 | suffixes |= 1 << 5; | |
8150 | ||
6c0946d0 JB |
8151 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
8152 | also suitable for AT&T syntax mode, it was requested that this be | |
8153 | restricted to just Intel syntax. */ | |
a5748e0d JB |
8154 | if (intel_syntax && is_any_vex_encoding (&i.tm) |
8155 | && !i.broadcast.type && !i.broadcast.bytes) | |
6c0946d0 | 8156 | { |
b9915cbc | 8157 | unsigned int op; |
6c0946d0 | 8158 | |
b9915cbc | 8159 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 8160 | { |
4fc85f37 JB |
8161 | if (vector_size < VSZ512) |
8162 | { | |
8163 | i.tm.operand_types[op].bitfield.zmmword = 0; | |
8164 | if (vector_size < VSZ256) | |
8165 | { | |
8166 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
8167 | if (i.tm.operand_types[op].bitfield.xmmword | |
706ce984 | 8168 | && i.tm.opcode_modifier.evex == EVEXDYN) |
4fc85f37 JB |
8169 | i.tm.opcode_modifier.evex = EVEX128; |
8170 | } | |
8171 | else if (i.tm.operand_types[op].bitfield.ymmword | |
8172 | && !i.tm.operand_types[op].bitfield.xmmword | |
706ce984 | 8173 | && i.tm.opcode_modifier.evex == EVEXDYN) |
4fc85f37 JB |
8174 | i.tm.opcode_modifier.evex = EVEX256; |
8175 | } | |
706ce984 | 8176 | else if (i.tm.opcode_modifier.evex |
4fc85f37 | 8177 | && !cpu_arch_flags.bitfield.cpuavx512vl) |
6c0946d0 | 8178 | { |
b9915cbc JB |
8179 | if (i.tm.operand_types[op].bitfield.ymmword) |
8180 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
8181 | if (i.tm.operand_types[op].bitfield.zmmword) | |
8182 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
706ce984 | 8183 | if (i.tm.opcode_modifier.evex == EVEXDYN) |
b9915cbc JB |
8184 | i.tm.opcode_modifier.evex = EVEX512; |
8185 | } | |
6c0946d0 | 8186 | |
b9915cbc JB |
8187 | if (i.tm.operand_types[op].bitfield.xmmword |
8188 | + i.tm.operand_types[op].bitfield.ymmword | |
8189 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
8190 | continue; | |
6c0946d0 | 8191 | |
b9915cbc JB |
8192 | /* Any properly sized operand disambiguates the insn. */ |
8193 | if (i.types[op].bitfield.xmmword | |
8194 | || i.types[op].bitfield.ymmword | |
8195 | || i.types[op].bitfield.zmmword) | |
8196 | { | |
8197 | suffixes &= ~(7 << 6); | |
8198 | evex = 0; | |
8199 | break; | |
8200 | } | |
6c0946d0 | 8201 | |
b9915cbc JB |
8202 | if ((i.flags[op] & Operand_Mem) |
8203 | && i.tm.operand_types[op].bitfield.unspecified) | |
8204 | { | |
8205 | if (i.tm.operand_types[op].bitfield.xmmword) | |
8206 | suffixes |= 1 << 6; | |
8207 | if (i.tm.operand_types[op].bitfield.ymmword) | |
8208 | suffixes |= 1 << 7; | |
8209 | if (i.tm.operand_types[op].bitfield.zmmword) | |
8210 | suffixes |= 1 << 8; | |
706ce984 | 8211 | if (i.tm.opcode_modifier.evex) |
b9915cbc | 8212 | evex = EVEX512; |
6c0946d0 JB |
8213 | } |
8214 | } | |
8215 | } | |
8216 | ||
8217 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 8218 | if (suffixes & (suffixes - 1)) |
9306ca4a | 8219 | { |
873494c8 | 8220 | if (intel_syntax |
3cd7f3e3 | 8221 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 8222 | || operand_check == check_error)) |
9306ca4a | 8223 | { |
76d3f746 | 8224 | as_bad (_("ambiguous operand size for `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
8225 | return 0; |
8226 | } | |
c006a730 | 8227 | if (operand_check == check_error) |
9306ca4a | 8228 | { |
c006a730 | 8229 | as_bad (_("no instruction mnemonic suffix given and " |
76d3f746 | 8230 | "no register operands; can't size `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
8231 | return 0; |
8232 | } | |
c006a730 | 8233 | if (operand_check == check_warning) |
873494c8 JB |
8234 | as_warn (_("%s; using default for `%s'"), |
8235 | intel_syntax | |
8236 | ? _("ambiguous operand size") | |
8237 | : _("no instruction mnemonic suffix given and " | |
8238 | "no register operands"), | |
76d3f746 | 8239 | insn_name (&i.tm)); |
c006a730 JB |
8240 | |
8241 | if (i.tm.opcode_modifier.floatmf) | |
8242 | i.suffix = SHORT_MNEM_SUFFIX; | |
389d00a5 | 8243 | else if (is_movx) |
65fca059 | 8244 | /* handled below */; |
6c0946d0 JB |
8245 | else if (evex) |
8246 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
8247 | else if (flag_code == CODE_16BIT) |
8248 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 8249 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 8250 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
8251 | else |
8252 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 8253 | } |
29b0f896 | 8254 | } |
252b5132 | 8255 | |
389d00a5 | 8256 | if (is_movx) |
65fca059 JB |
8257 | { |
8258 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
8259 | In AT&T syntax, if there is no suffix (warned about above), the default | |
8260 | will be byte extension. */ | |
8261 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
8262 | i.tm.base_opcode |= 1; | |
8263 | ||
8264 | /* For further processing, the suffix should represent the destination | |
8265 | (register). This is already the case when one was used with | |
8266 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
8267 | no suffix to begin with. */ | |
8268 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
8269 | { | |
8270 | if (i.types[1].bitfield.word) | |
8271 | i.suffix = WORD_MNEM_SUFFIX; | |
8272 | else if (i.types[1].bitfield.qword) | |
8273 | i.suffix = QWORD_MNEM_SUFFIX; | |
8274 | else | |
8275 | i.suffix = LONG_MNEM_SUFFIX; | |
8276 | ||
8277 | i.tm.opcode_modifier.w = 0; | |
8278 | } | |
8279 | } | |
8280 | ||
50128d0c JB |
8281 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
8282 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
8283 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
8284 | ||
d2224064 JB |
8285 | /* Change the opcode based on the operand size given by i.suffix. */ |
8286 | switch (i.suffix) | |
29b0f896 | 8287 | { |
d2224064 JB |
8288 | /* Size floating point instruction. */ |
8289 | case LONG_MNEM_SUFFIX: | |
8290 | if (i.tm.opcode_modifier.floatmf) | |
8291 | { | |
8292 | i.tm.base_opcode ^= 4; | |
8293 | break; | |
8294 | } | |
8295 | /* fall through */ | |
8296 | case WORD_MNEM_SUFFIX: | |
8297 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 8298 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 8299 | if (i.tm.opcode_modifier.w) |
29b0f896 | 8300 | { |
50128d0c | 8301 | if (i.short_form) |
29b0f896 AM |
8302 | i.tm.base_opcode |= 8; |
8303 | else | |
8304 | i.tm.base_opcode |= 1; | |
8305 | } | |
d2224064 JB |
8306 | /* fall through */ |
8307 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
8308 | /* Now select between word & dword operations via the operand |
8309 | size prefix, except for instructions that will ignore this | |
8310 | prefix anyway. */ | |
c8f8eebc | 8311 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 8312 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc | 8313 | && !i.tm.opcode_modifier.floatmf |
6177c84d CL |
8314 | && (!is_any_vex_encoding (&i.tm) |
8315 | || i.tm.opcode_space == SPACE_EVEXMAP4) | |
c8f8eebc JB |
8316 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
8317 | || (flag_code == CODE_64BIT | |
8318 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
8319 | { |
8320 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 8321 | |
0cfa3eb3 | 8322 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 8323 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 8324 | |
6177c84d CL |
8325 | /* The DATA PREFIX of EVEX promoted from legacy APX instructions |
8326 | needs to be adjusted. */ | |
8327 | if (i.tm.opcode_space == SPACE_EVEXMAP4) | |
8328 | { | |
8329 | gas_assert (!i.tm.opcode_modifier.opcodeprefix); | |
8330 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; | |
8331 | } | |
8332 | else if (!add_prefix (prefix)) | |
29b0f896 | 8333 | return 0; |
24eab124 | 8334 | } |
252b5132 | 8335 | |
29b0f896 AM |
8336 | /* Set mode64 for an operand. */ |
8337 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 8338 | && flag_code == CODE_64BIT |
d2224064 | 8339 | && !i.tm.opcode_modifier.norex64 |
4ed21b58 | 8340 | && !i.tm.opcode_modifier.vexw |
46e883c5 | 8341 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
8342 | need rex64. */ |
8343 | && ! (i.operands == 2 | |
8344 | && i.tm.base_opcode == 0x90 | |
ddb62495 | 8345 | && i.tm.opcode_space == SPACE_BASE |
75e5731b JB |
8346 | && i.types[0].bitfield.instance == Accum |
8347 | && i.types[0].bitfield.qword | |
44732014 | 8348 | && i.types[1].bitfield.instance == Accum)) |
d2224064 | 8349 | i.rex |= REX_W; |
3e73aa7c | 8350 | |
d2224064 | 8351 | break; |
8bbb3ad8 JB |
8352 | |
8353 | case 0: | |
f9a6a8f0 | 8354 | /* Select word/dword/qword operation with explicit data sizing prefix |
8bbb3ad8 JB |
8355 | when there are no suitable register operands. */ |
8356 | if (i.tm.opcode_modifier.w | |
8357 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
8358 | && (!i.reg_operands | |
8359 | || (i.reg_operands == 1 | |
8360 | /* ShiftCount */ | |
8361 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
8362 | /* InOutPortReg */ | |
8363 | || i.tm.operand_types[0].bitfield.instance == RegD | |
8364 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7fc69528 | 8365 | || i.tm.mnem_off == MN_crc32)))) |
8bbb3ad8 JB |
8366 | i.tm.base_opcode |= 1; |
8367 | break; | |
29b0f896 | 8368 | } |
7ecd2f8b | 8369 | |
255571cd | 8370 | if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG) |
c0a30a9f | 8371 | { |
c8f8eebc JB |
8372 | gas_assert (!i.suffix); |
8373 | gas_assert (i.reg_operands); | |
c0a30a9f | 8374 | |
c8f8eebc JB |
8375 | if (i.tm.operand_types[0].bitfield.instance == Accum |
8376 | || i.operands == 1) | |
8377 | { | |
8378 | /* The address size override prefix changes the size of the | |
8379 | first operand. */ | |
8380 | if (flag_code == CODE_64BIT | |
8381 | && i.op[0].regs->reg_type.bitfield.word) | |
8382 | { | |
8383 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
76d3f746 | 8384 | insn_name (&i.tm)); |
c8f8eebc JB |
8385 | return 0; |
8386 | } | |
8387 | ||
8388 | if ((flag_code == CODE_32BIT | |
8389 | ? i.op[0].regs->reg_type.bitfield.word | |
8390 | : i.op[0].regs->reg_type.bitfield.dword) | |
8391 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
8392 | return 0; | |
8393 | } | |
c0a30a9f L |
8394 | else |
8395 | { | |
c8f8eebc JB |
8396 | /* Check invalid register operand when the address size override |
8397 | prefix changes the size of register operands. */ | |
8398 | unsigned int op; | |
8399 | enum { need_word, need_dword, need_qword } need; | |
8400 | ||
27f13469 | 8401 | /* Check the register operand for the address size prefix if |
b3a3496f | 8402 | the memory operand has no real registers, like symbol, DISP |
829f3fe1 | 8403 | or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */ |
27f13469 L |
8404 | if (i.mem_operands == 1 |
8405 | && i.reg_operands == 1 | |
8406 | && i.operands == 2 | |
27f13469 | 8407 | && i.types[1].bitfield.class == Reg |
b3a3496f L |
8408 | && (flag_code == CODE_32BIT |
8409 | ? i.op[1].regs->reg_type.bitfield.word | |
8410 | : i.op[1].regs->reg_type.bitfield.dword) | |
8411 | && ((i.base_reg == NULL && i.index_reg == NULL) | |
829f3fe1 JB |
8412 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
8413 | || (x86_elf_abi == X86_64_X32_ABI | |
8414 | && i.base_reg | |
b3a3496f L |
8415 | && i.base_reg->reg_num == RegIP |
8416 | && i.base_reg->reg_type.bitfield.qword)) | |
829f3fe1 JB |
8417 | #else |
8418 | || 0) | |
8419 | #endif | |
27f13469 L |
8420 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
8421 | return 0; | |
8422 | ||
c8f8eebc JB |
8423 | if (flag_code == CODE_32BIT) |
8424 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
8425 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
8426 | need = need_dword; |
8427 | else | |
8428 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 8429 | |
c8f8eebc JB |
8430 | for (op = 0; op < i.operands; op++) |
8431 | { | |
8432 | if (i.types[op].bitfield.class != Reg) | |
8433 | continue; | |
8434 | ||
8435 | switch (need) | |
8436 | { | |
8437 | case need_word: | |
8438 | if (i.op[op].regs->reg_type.bitfield.word) | |
8439 | continue; | |
8440 | break; | |
8441 | case need_dword: | |
8442 | if (i.op[op].regs->reg_type.bitfield.dword) | |
8443 | continue; | |
8444 | break; | |
8445 | case need_qword: | |
8446 | if (i.op[op].regs->reg_type.bitfield.qword) | |
8447 | continue; | |
8448 | break; | |
8449 | } | |
8450 | ||
8451 | as_bad (_("invalid register operand size for `%s'"), | |
76d3f746 | 8452 | insn_name (&i.tm)); |
c8f8eebc JB |
8453 | return 0; |
8454 | } | |
8455 | } | |
c0a30a9f L |
8456 | } |
8457 | ||
29b0f896 AM |
8458 | return 1; |
8459 | } | |
3e73aa7c | 8460 | |
29b0f896 | 8461 | static int |
543613e9 | 8462 | check_byte_reg (void) |
29b0f896 AM |
8463 | { |
8464 | int op; | |
543613e9 | 8465 | |
29b0f896 AM |
8466 | for (op = i.operands; --op >= 0;) |
8467 | { | |
dc821c5f | 8468 | /* Skip non-register operands. */ |
bab6aec1 | 8469 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
8470 | continue; |
8471 | ||
29b0f896 AM |
8472 | /* If this is an eight bit register, it's OK. If it's the 16 or |
8473 | 32 bit version of an eight bit register, we will just use the | |
8474 | low portion, and that's OK too. */ | |
dc821c5f | 8475 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
8476 | continue; |
8477 | ||
5a819eb9 | 8478 | /* I/O port address operands are OK too. */ |
75e5731b JB |
8479 | if (i.tm.operand_types[op].bitfield.instance == RegD |
8480 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
8481 | continue; |
8482 | ||
9706160a | 8483 | /* crc32 only wants its source operand checked here. */ |
7fc69528 | 8484 | if (i.tm.mnem_off == MN_crc32 && op != 0) |
9344ff29 L |
8485 | continue; |
8486 | ||
29b0f896 | 8487 | /* Any other register is bad. */ |
73c76375 JB |
8488 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
8489 | register_prefix, i.op[op].regs->reg_name, | |
76d3f746 | 8490 | insn_name (&i.tm), i.suffix); |
73c76375 | 8491 | return 0; |
29b0f896 AM |
8492 | } |
8493 | return 1; | |
8494 | } | |
8495 | ||
8496 | static int | |
e3bb37b5 | 8497 | check_long_reg (void) |
29b0f896 AM |
8498 | { |
8499 | int op; | |
8500 | ||
8501 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 8502 | /* Skip non-register operands. */ |
bab6aec1 | 8503 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 8504 | continue; |
29b0f896 AM |
8505 | /* Reject eight bit registers, except where the template requires |
8506 | them. (eg. movzb) */ | |
dc821c5f | 8507 | else if (i.types[op].bitfield.byte |
bab6aec1 | 8508 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8509 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
8510 | && (i.tm.operand_types[op].bitfield.word |
8511 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 8512 | { |
a540244d L |
8513 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
8514 | register_prefix, | |
29b0f896 | 8515 | i.op[op].regs->reg_name, |
76d3f746 | 8516 | insn_name (&i.tm), |
29b0f896 AM |
8517 | i.suffix); |
8518 | return 0; | |
8519 | } | |
d9a1b711 JB |
8520 | /* Error if the e prefix on a general reg is missing, or if the r |
8521 | prefix on a general reg is present. */ | |
8522 | else if ((i.types[op].bitfield.word | |
8523 | || i.types[op].bitfield.qword) | |
bab6aec1 | 8524 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8525 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 8526 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 8527 | { |
be4c5e58 L |
8528 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
8529 | register_prefix, i.op[op].regs->reg_name, | |
8530 | i.suffix); | |
8531 | return 0; | |
252b5132 | 8532 | } |
29b0f896 AM |
8533 | return 1; |
8534 | } | |
252b5132 | 8535 | |
29b0f896 | 8536 | static int |
e3bb37b5 | 8537 | check_qword_reg (void) |
29b0f896 AM |
8538 | { |
8539 | int op; | |
252b5132 | 8540 | |
29b0f896 | 8541 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 8542 | /* Skip non-register operands. */ |
bab6aec1 | 8543 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 8544 | continue; |
29b0f896 AM |
8545 | /* Reject eight bit registers, except where the template requires |
8546 | them. (eg. movzb) */ | |
dc821c5f | 8547 | else if (i.types[op].bitfield.byte |
bab6aec1 | 8548 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8549 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 8550 | && (i.tm.operand_types[op].bitfield.word |
742b55c7 JB |
8551 | || i.tm.operand_types[op].bitfield.dword |
8552 | || i.tm.operand_types[op].bitfield.qword)) | |
29b0f896 | 8553 | { |
a540244d L |
8554 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
8555 | register_prefix, | |
29b0f896 | 8556 | i.op[op].regs->reg_name, |
76d3f746 | 8557 | insn_name (&i.tm), |
29b0f896 AM |
8558 | i.suffix); |
8559 | return 0; | |
8560 | } | |
d9a1b711 | 8561 | /* Error if the r prefix on a general reg is missing. */ |
dc821c5f JB |
8562 | else if ((i.types[op].bitfield.word |
8563 | || i.types[op].bitfield.dword) | |
bab6aec1 | 8564 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8565 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 8566 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
8567 | { |
8568 | /* Prohibit these changes in the 64bit mode, since the | |
8569 | lowering is more complicated. */ | |
1cb0ab18 JB |
8570 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
8571 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
8572 | return 0; | |
252b5132 | 8573 | } |
29b0f896 AM |
8574 | return 1; |
8575 | } | |
252b5132 | 8576 | |
29b0f896 | 8577 | static int |
e3bb37b5 | 8578 | check_word_reg (void) |
29b0f896 AM |
8579 | { |
8580 | int op; | |
8581 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 8582 | /* Skip non-register operands. */ |
bab6aec1 | 8583 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 8584 | continue; |
29b0f896 AM |
8585 | /* Reject eight bit registers, except where the template requires |
8586 | them. (eg. movzb) */ | |
dc821c5f | 8587 | else if (i.types[op].bitfield.byte |
bab6aec1 | 8588 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8589 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
8590 | && (i.tm.operand_types[op].bitfield.word |
8591 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 8592 | { |
a540244d L |
8593 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
8594 | register_prefix, | |
29b0f896 | 8595 | i.op[op].regs->reg_name, |
76d3f746 | 8596 | insn_name (&i.tm), |
29b0f896 AM |
8597 | i.suffix); |
8598 | return 0; | |
8599 | } | |
9706160a JB |
8600 | /* Error if the e or r prefix on a general reg is present. */ |
8601 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 8602 | || i.types[op].bitfield.qword) |
bab6aec1 | 8603 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8604 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 8605 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 8606 | { |
9706160a JB |
8607 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
8608 | register_prefix, i.op[op].regs->reg_name, | |
8609 | i.suffix); | |
8610 | return 0; | |
29b0f896 AM |
8611 | } |
8612 | return 1; | |
8613 | } | |
252b5132 | 8614 | |
29b0f896 | 8615 | static int |
40fb9820 | 8616 | update_imm (unsigned int j) |
29b0f896 | 8617 | { |
bc0844ae | 8618 | i386_operand_type overlap = i.types[j]; |
c34d1cc9 JB |
8619 | |
8620 | if (i.tm.operand_types[j].bitfield.imm8 | |
8621 | && i.tm.operand_types[j].bitfield.imm8s | |
8622 | && overlap.bitfield.imm8 && overlap.bitfield.imm8s) | |
8623 | { | |
8624 | /* This combination is used on 8-bit immediates where e.g. $~0 is | |
8625 | desirable to permit. We're past operand type matching, so simply | |
8626 | put things back in the shape they were before introducing the | |
8627 | distinction between Imm8, Imm8S, and Imm8|Imm8S. */ | |
8628 | overlap.bitfield.imm8s = 0; | |
8629 | } | |
8630 | ||
be1643ff JB |
8631 | if (overlap.bitfield.imm8 |
8632 | + overlap.bitfield.imm8s | |
8633 | + overlap.bitfield.imm16 | |
8634 | + overlap.bitfield.imm32 | |
8635 | + overlap.bitfield.imm32s | |
8636 | + overlap.bitfield.imm64 > 1) | |
29b0f896 | 8637 | { |
05909f23 JB |
8638 | static const i386_operand_type imm16 = { .bitfield = { .imm16 = 1 } }; |
8639 | static const i386_operand_type imm32 = { .bitfield = { .imm32 = 1 } }; | |
8640 | static const i386_operand_type imm32s = { .bitfield = { .imm32s = 1 } }; | |
8641 | static const i386_operand_type imm16_32 = { .bitfield = | |
8642 | { .imm16 = 1, .imm32 = 1 } | |
8643 | }; | |
8644 | static const i386_operand_type imm16_32s = { .bitfield = | |
8645 | { .imm16 = 1, .imm32s = 1 } | |
8646 | }; | |
8647 | static const i386_operand_type imm16_32_32s = { .bitfield = | |
8648 | { .imm16 = 1, .imm32 = 1, .imm32s = 1 } | |
8649 | }; | |
8650 | ||
29b0f896 AM |
8651 | if (i.suffix) |
8652 | { | |
40fb9820 L |
8653 | i386_operand_type temp; |
8654 | ||
0dfbf9d7 | 8655 | operand_type_set (&temp, 0); |
7ab9ffdd | 8656 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
8657 | { |
8658 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
8659 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
8660 | } | |
8661 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
8662 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
8663 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
8664 | { | |
8665 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
8666 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
8667 | } | |
8668 | else | |
8669 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
8670 | overlap = temp; | |
29b0f896 | 8671 | } |
0dfbf9d7 L |
8672 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
8673 | || operand_type_equal (&overlap, &imm16_32) | |
8674 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 8675 | { |
f79d55e1 JB |
8676 | if ((flag_code == CODE_16BIT) |
8677 | ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W))) | |
65da13b5 | 8678 | overlap = imm16; |
40fb9820 | 8679 | else |
65da13b5 | 8680 | overlap = imm32s; |
29b0f896 | 8681 | } |
8bbb3ad8 JB |
8682 | else if (i.prefix[REX_PREFIX] & REX_W) |
8683 | overlap = operand_type_and (overlap, imm32s); | |
8684 | else if (i.prefix[DATA_PREFIX]) | |
8685 | overlap = operand_type_and (overlap, | |
8686 | flag_code != CODE_16BIT ? imm16 : imm32); | |
be1643ff JB |
8687 | if (overlap.bitfield.imm8 |
8688 | + overlap.bitfield.imm8s | |
8689 | + overlap.bitfield.imm16 | |
8690 | + overlap.bitfield.imm32 | |
8691 | + overlap.bitfield.imm32s | |
8692 | + overlap.bitfield.imm64 != 1) | |
29b0f896 | 8693 | { |
4eed87de AM |
8694 | as_bad (_("no instruction mnemonic suffix given; " |
8695 | "can't determine immediate size")); | |
29b0f896 AM |
8696 | return 0; |
8697 | } | |
8698 | } | |
40fb9820 | 8699 | i.types[j] = overlap; |
29b0f896 | 8700 | |
40fb9820 L |
8701 | return 1; |
8702 | } | |
8703 | ||
8704 | static int | |
8705 | finalize_imm (void) | |
8706 | { | |
bc0844ae | 8707 | unsigned int j, n; |
29b0f896 | 8708 | |
bc0844ae L |
8709 | /* Update the first 2 immediate operands. */ |
8710 | n = i.operands > 2 ? 2 : i.operands; | |
8711 | if (n) | |
8712 | { | |
8713 | for (j = 0; j < n; j++) | |
8714 | if (update_imm (j) == 0) | |
8715 | return 0; | |
40fb9820 | 8716 | |
bc0844ae L |
8717 | /* The 3rd operand can't be immediate operand. */ |
8718 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
8719 | } | |
29b0f896 AM |
8720 | |
8721 | return 1; | |
8722 | } | |
8723 | ||
0a3eba42 JB |
8724 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
8725 | bool do_sse2avx) | |
8726 | { | |
8727 | if (r->reg_flags & RegRex) | |
8728 | { | |
8729 | if (i.rex & rex_bit) | |
8730 | as_bad (_("same type of prefix used twice")); | |
8731 | i.rex |= rex_bit; | |
8732 | } | |
8733 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
8734 | { | |
8735 | gas_assert (i.vex.register_specifier == r); | |
8736 | i.vex.register_specifier += 8; | |
8737 | } | |
8738 | ||
8739 | if (r->reg_flags & RegVRex) | |
8740 | i.vrex |= rex_bit; | |
80d61d8d CL |
8741 | |
8742 | if (r->reg_flags & RegRex2) | |
8743 | i.rex2 |= rex_bit; | |
8744 | } | |
8745 | ||
8746 | static INLINE void | |
8747 | set_rex_rex2 (const reg_entry *r, unsigned int rex_bit) | |
8748 | { | |
8749 | if ((r->reg_flags & RegRex) != 0) | |
8750 | i.rex |= rex_bit; | |
8751 | if ((r->reg_flags & RegRex2) != 0) | |
8752 | i.rex2 |= rex_bit; | |
0a3eba42 JB |
8753 | } |
8754 | ||
29b0f896 | 8755 | static int |
e3bb37b5 | 8756 | process_operands (void) |
29b0f896 AM |
8757 | { |
8758 | /* Default segment register this instruction will use for memory | |
8759 | accesses. 0 means unknown. This is only for optimizing out | |
8760 | unnecessary segment overrides. */ | |
5e042380 | 8761 | const reg_entry *default_seg = NULL; |
29b0f896 | 8762 | |
3083f376 | 8763 | for (unsigned int j = 0; j < i.operands; j++) |
8764 | if (i.types[j].bitfield.instance != InstanceNone) | |
8765 | i.reg_operands--; | |
31b4cda3 | 8766 | |
a5aeccd9 JB |
8767 | if (i.tm.opcode_modifier.sse2avx) |
8768 | { | |
8769 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
8770 | need converting. */ | |
8771 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
8772 | i.prefix[REX_PREFIX] = 0; | |
8773 | i.rex_encoding = 0; | |
8774 | } | |
c423d21a JB |
8775 | /* ImmExt should be processed after SSE2AVX. */ |
8776 | else if (i.tm.opcode_modifier.immext) | |
8777 | process_immext (); | |
a5aeccd9 | 8778 | |
ecb96e55 JB |
8779 | /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg, |
8780 | not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a | |
8781 | new destination operand here, while converting the source one to register | |
8782 | number 0. */ | |
8783 | if (i.tm.mnem_off == MN_tilezero) | |
8784 | { | |
8785 | i.op[1].regs = i.op[0].regs; | |
8786 | i.op[0].regs -= i.op[0].regs->reg_num; | |
8787 | i.types[1] = i.types[0]; | |
8788 | i.tm.operand_types[1] = i.tm.operand_types[0]; | |
8789 | i.flags[1] = i.flags[0]; | |
8790 | i.operands++; | |
8791 | i.reg_operands++; | |
8792 | i.tm.operands++; | |
8793 | } | |
8794 | ||
2426c15f | 8795 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 8796 | { |
05909f23 JB |
8797 | static const i386_operand_type regxmm = { |
8798 | .bitfield = { .class = RegSIMD, .xmmword = 1 } | |
8799 | }; | |
91d6fa6a NC |
8800 | unsigned int dupl = i.operands; |
8801 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
8802 | unsigned int j; |
8803 | ||
c0f3af97 | 8804 | /* The destination must be an xmm register. */ |
9c2799c2 | 8805 | gas_assert (i.reg_operands |
91d6fa6a | 8806 | && MAX_OPERANDS > dupl |
7ab9ffdd | 8807 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 8808 | |
75e5731b | 8809 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 8810 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 8811 | { |
95dfdd85 JB |
8812 | /* Keep xmm0 for instructions with VEX prefix and 3 |
8813 | sources. */ | |
8814 | i.tm.operand_types[0].bitfield.instance = InstanceNone; | |
8815 | i.tm.operand_types[0].bitfield.class = RegSIMD; | |
31b4cda3 | 8816 | i.reg_operands++; |
95dfdd85 | 8817 | goto duplicate; |
c0f3af97 | 8818 | } |
95dfdd85 JB |
8819 | |
8820 | if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0) | |
7ab9ffdd | 8821 | { |
aa180741 | 8822 | gas_assert ((MAX_OPERANDS - 1) > dupl); |
c0f3af97 L |
8823 | |
8824 | /* Add the implicit xmm0 for instructions with VEX prefix | |
8825 | and 3 sources. */ | |
8826 | for (j = i.operands; j > 0; j--) | |
8827 | { | |
8828 | i.op[j] = i.op[j - 1]; | |
8829 | i.types[j] = i.types[j - 1]; | |
8830 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 8831 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
8832 | } |
8833 | i.op[0].regs | |
629310ab | 8834 | = (const reg_entry *) str_hash_find (reg_hash, "xmm0"); |
7ab9ffdd | 8835 | i.types[0] = regxmm; |
c0f3af97 L |
8836 | i.tm.operand_types[0] = regxmm; |
8837 | ||
8838 | i.operands += 2; | |
8839 | i.reg_operands += 2; | |
8840 | i.tm.operands += 2; | |
8841 | ||
91d6fa6a | 8842 | dupl++; |
c0f3af97 | 8843 | dest++; |
91d6fa6a NC |
8844 | i.op[dupl] = i.op[dest]; |
8845 | i.types[dupl] = i.types[dest]; | |
8846 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 8847 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 8848 | } |
c0f3af97 L |
8849 | else |
8850 | { | |
dc1e8a47 | 8851 | duplicate: |
c0f3af97 L |
8852 | i.operands++; |
8853 | i.reg_operands++; | |
8854 | i.tm.operands++; | |
8855 | ||
91d6fa6a NC |
8856 | i.op[dupl] = i.op[dest]; |
8857 | i.types[dupl] = i.types[dest]; | |
8858 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 8859 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
8860 | } |
8861 | ||
8862 | if (i.tm.opcode_modifier.immext) | |
8863 | process_immext (); | |
8864 | } | |
75e5731b | 8865 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
bd782808 | 8866 | && i.tm.opcode_modifier.modrm) |
c0f3af97 L |
8867 | { |
8868 | unsigned int j; | |
8869 | ||
9fcfb3d7 L |
8870 | for (j = 1; j < i.operands; j++) |
8871 | { | |
8872 | i.op[j - 1] = i.op[j]; | |
8873 | i.types[j - 1] = i.types[j]; | |
8874 | ||
8875 | /* We need to adjust fields in i.tm since they are used by | |
8876 | build_modrm_byte. */ | |
8877 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
8878 | |
8879 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
8880 | } |
8881 | ||
31b4cda3 JB |
8882 | /* No adjustment to i.reg_operands: This was already done at the top |
8883 | of the function. */ | |
e2ec9d29 | 8884 | i.operands--; |
e2ec9d29 L |
8885 | i.tm.operands--; |
8886 | } | |
255571cd | 8887 | else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP) |
920d2ddc | 8888 | { |
a477a8c4 JB |
8889 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
8890 | ||
920d2ddc | 8891 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 8892 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
8893 | regnum = register_number (i.op[1].regs); |
8894 | first_reg_in_group = regnum & ~3; | |
8895 | last_reg_in_group = first_reg_in_group + 3; | |
8896 | if (regnum != first_reg_in_group) | |
8897 | as_warn (_("source register `%s%s' implicitly denotes" | |
8898 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
8899 | register_prefix, i.op[1].regs->reg_name, | |
8900 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
8901 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
76d3f746 | 8902 | insn_name (&i.tm)); |
a477a8c4 | 8903 | } |
255571cd | 8904 | else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE) |
e2ec9d29 L |
8905 | { |
8906 | /* The imul $imm, %reg instruction is converted into | |
8907 | imul $imm, %reg, %reg, and the clr %reg instruction | |
8908 | is converted into xor %reg, %reg. */ | |
8909 | ||
8910 | unsigned int first_reg_op; | |
8911 | ||
8912 | if (operand_type_check (i.types[0], reg)) | |
8913 | first_reg_op = 0; | |
8914 | else | |
8915 | first_reg_op = 1; | |
8916 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 8917 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 8918 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
8919 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
8920 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
8921 | i.operands++; | |
8922 | i.reg_operands++; | |
29b0f896 AM |
8923 | } |
8924 | ||
85b80b0f | 8925 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
8926 | { |
8927 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
8928 | must be put into the modrm byte). Now, we make the modrm and |
8929 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
8930 | |
8931 | default_seg = build_modrm_byte (); | |
bd782808 JB |
8932 | |
8933 | if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) | |
8934 | { | |
8935 | /* Warn about some common errors, but press on regardless. */ | |
8936 | if (i.operands == 2) | |
8937 | { | |
8938 | /* Reversed arguments on faddp or fmulp. */ | |
8939 | as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i.tm), | |
8940 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
8941 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
8942 | } | |
8943 | else if (i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
8944 | { | |
8945 | /* Extraneous `l' suffix on fp insn. */ | |
8946 | as_warn (_("translating to `%s %s%s'"), insn_name (&i.tm), | |
8947 | register_prefix, i.op[0].regs->reg_name); | |
8948 | } | |
8949 | } | |
29b0f896 | 8950 | } |
0ff3b7d0 | 8951 | else if (i.types[0].bitfield.class == SReg && !dot_insn ()) |
85b80b0f JB |
8952 | { |
8953 | if (flag_code != CODE_64BIT | |
8954 | ? i.tm.base_opcode == POP_SEG_SHORT | |
8955 | && i.op[0].regs->reg_num == 1 | |
389d00a5 | 8956 | : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff) |
85b80b0f JB |
8957 | && i.op[0].regs->reg_num < 4) |
8958 | { | |
8959 | as_bad (_("you can't `%s %s%s'"), | |
76d3f746 | 8960 | insn_name (&i.tm), register_prefix, i.op[0].regs->reg_name); |
85b80b0f JB |
8961 | return 0; |
8962 | } | |
389d00a5 | 8963 | if (i.op[0].regs->reg_num > 3 |
ddb62495 | 8964 | && i.tm.opcode_space == SPACE_BASE ) |
85b80b0f | 8965 | { |
389d00a5 | 8966 | i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff; |
ddb62495 | 8967 | i.tm.opcode_space = SPACE_0F; |
85b80b0f JB |
8968 | } |
8969 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
8970 | } | |
ddb62495 | 8971 | else if (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 8972 | && (i.tm.base_opcode & ~3) == MOV_AX_DISP32) |
29b0f896 | 8973 | { |
5e042380 | 8974 | default_seg = reg_ds; |
29b0f896 | 8975 | } |
40fb9820 | 8976 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
8977 | { |
8978 | /* For the string instructions that allow a segment override | |
8979 | on one of their operands, the default segment is ds. */ | |
5e042380 | 8980 | default_seg = reg_ds; |
29b0f896 | 8981 | } |
50128d0c | 8982 | else if (i.short_form) |
85b80b0f | 8983 | { |
0ff3b7d0 JB |
8984 | /* The register operand is in the 1st or 2nd non-immediate operand. */ |
8985 | const reg_entry *r = i.op[i.imm_operands].regs; | |
85b80b0f | 8986 | |
0ff3b7d0 JB |
8987 | if (!dot_insn () |
8988 | && r->reg_type.bitfield.instance == Accum | |
8989 | && i.op[i.imm_operands + 1].regs) | |
8990 | r = i.op[i.imm_operands + 1].regs; | |
85b80b0f | 8991 | /* Register goes in low 3 bits of opcode. */ |
4943d587 | 8992 | i.tm.base_opcode |= r->reg_num; |
0a3eba42 | 8993 | set_rex_vrex (r, REX_B, false); |
0ff3b7d0 JB |
8994 | |
8995 | if (dot_insn () && i.reg_operands == 2) | |
8996 | { | |
8997 | gas_assert (is_any_vex_encoding (&i.tm) | |
8998 | || i.vec_encoding != vex_encoding_default); | |
8999 | i.vex.register_specifier = i.op[i.operands - 1].regs; | |
9000 | } | |
9001 | } | |
9002 | else if (i.reg_operands == 1 | |
9003 | && !i.flags[i.operands - 1] | |
9004 | && i.tm.operand_types[i.operands - 1].bitfield.instance | |
9005 | == InstanceNone) | |
9006 | { | |
9007 | gas_assert (is_any_vex_encoding (&i.tm) | |
9008 | || i.vec_encoding != vex_encoding_default); | |
9009 | i.vex.register_specifier = i.op[i.operands - 1].regs; | |
85b80b0f | 9010 | } |
29b0f896 | 9011 | |
514a8bb0 | 9012 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
7fc69528 | 9013 | && i.tm.mnem_off == MN_lea) |
92334ad2 JB |
9014 | { |
9015 | if (!quiet_warnings) | |
76d3f746 | 9016 | as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm)); |
739d7649 | 9017 | if (optimize && !i.no_optimize) |
92334ad2 JB |
9018 | { |
9019 | i.seg[0] = NULL; | |
9020 | i.prefix[SEG_PREFIX] = 0; | |
9021 | } | |
9022 | } | |
52271982 AM |
9023 | |
9024 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
9025 | is neither the default nor the one already recorded from a prefix, |
9026 | use an opcode prefix to select it. If we never figured out what | |
9027 | the default segment is, then default_seg will be zero at this | |
9028 | point, and the specified segment prefix will always be used. */ | |
9029 | if (i.seg[0] | |
9030 | && i.seg[0] != default_seg | |
5e042380 | 9031 | && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX]) |
29b0f896 | 9032 | { |
5e042380 | 9033 | if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num])) |
29b0f896 AM |
9034 | return 0; |
9035 | } | |
9036 | return 1; | |
9037 | } | |
9038 | ||
5e042380 | 9039 | static const reg_entry * |
e3bb37b5 | 9040 | build_modrm_byte (void) |
29b0f896 | 9041 | { |
5e042380 | 9042 | const reg_entry *default_seg = NULL; |
ecb96e55 JB |
9043 | unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext |
9044 | /* Compensate for kludge in md_assemble(). */ | |
9045 | + i.tm.operand_types[0].bitfield.imm1; | |
9046 | unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext; | |
9047 | unsigned int v, op, reg_slot = ~0; | |
9048 | ||
9049 | /* Accumulator (in particular %st), shift count (%cl), and alike need | |
9050 | to be skipped just like immediate operands do. */ | |
9051 | if (i.tm.operand_types[source].bitfield.instance) | |
9052 | ++source; | |
9053 | while (i.tm.operand_types[dest].bitfield.instance) | |
9054 | --dest; | |
9055 | ||
9056 | for (op = source; op < i.operands; ++op) | |
9057 | if (i.tm.operand_types[op].bitfield.baseindex) | |
9058 | break; | |
c0f3af97 | 9059 | |
ecb96e55 | 9060 | if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4) |
c0f3af97 | 9061 | { |
4c2c6516 | 9062 | expressionS *exp; |
c0f3af97 | 9063 | |
a683cc34 | 9064 | /* There are 2 kinds of instructions: |
bed3d976 | 9065 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 9066 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 9067 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 9068 | ZMM register. |
bed3d976 | 9069 | 2. 4 operands: 4 register operands or 3 register operands |
0ff3b7d0 JB |
9070 | plus 1 memory operand, with VexXDS. |
9071 | 3. Other equivalent combinations when coming from s_insn(). */ | |
eea96d3f | 9072 | gas_assert (i.tm.opcode_modifier.vexvvvv |
0ff3b7d0 JB |
9073 | && i.tm.opcode_modifier.vexw); |
9074 | gas_assert (dot_insn () | |
9075 | || i.tm.operand_types[dest].bitfield.class == RegSIMD); | |
a683cc34 | 9076 | |
ecb96e55 JB |
9077 | /* Of the first two non-immediate operands the one with the template |
9078 | not allowing for a memory one is encoded in the immediate operand. */ | |
9079 | if (source == op) | |
9080 | reg_slot = source + 1; | |
48db9223 | 9081 | else |
ecb96e55 | 9082 | reg_slot = source++; |
48db9223 | 9083 | |
0ff3b7d0 JB |
9084 | if (!dot_insn ()) |
9085 | { | |
9086 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); | |
9087 | gas_assert (!(i.op[reg_slot].regs->reg_flags & RegVRex)); | |
9088 | } | |
9089 | else | |
9090 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class != ClassNone); | |
9091 | ||
a683cc34 | 9092 | if (i.imm_operands == 0) |
bed3d976 JB |
9093 | { |
9094 | /* When there is no immediate operand, generate an 8bit | |
9095 | immediate operand to encode the first operand. */ | |
9096 | exp = &im_expressions[i.imm_operands++]; | |
9097 | i.op[i.operands].imms = exp; | |
be1643ff | 9098 | i.types[i.operands].bitfield.imm8 = 1; |
bed3d976 JB |
9099 | i.operands++; |
9100 | ||
bed3d976 | 9101 | exp->X_op = O_constant; |
43234a1e | 9102 | } |
922d8de8 | 9103 | else |
bed3d976 | 9104 | { |
9d3bf266 JB |
9105 | gas_assert (i.imm_operands == 1); |
9106 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
9107 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 9108 | |
9d3bf266 JB |
9109 | /* Turn on Imm8 again so that output_imm will generate it. */ |
9110 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 9111 | |
0ff3b7d0 | 9112 | exp = i.op[0].imms; |
bed3d976 | 9113 | } |
0ff3b7d0 | 9114 | exp->X_add_number |= register_number (i.op[reg_slot].regs) |
706ce984 | 9115 | << (3 + !(i.tm.opcode_modifier.evex |
0ff3b7d0 | 9116 | || i.vec_encoding == vex_encoding_evex)); |
c0f3af97 | 9117 | } |
f12dc422 | 9118 | |
3083f376 | 9119 | if (i.tm.opcode_modifier.vexvvvv == VexVVVV_DST) |
9120 | { | |
9121 | v = dest; | |
9122 | dest-- ; | |
9123 | } | |
9124 | else | |
9125 | { | |
9126 | for (v = source + 1; v < dest; ++v) | |
9127 | if (v != reg_slot) | |
9128 | break; | |
9129 | if (v >= dest) | |
9130 | v = ~0; | |
9131 | } | |
ecb96e55 JB |
9132 | if (i.tm.extension_opcode != None) |
9133 | { | |
9134 | if (dest != source) | |
9135 | v = dest; | |
9136 | dest = ~0; | |
9137 | } | |
9138 | gas_assert (source < dest); | |
9139 | if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES | |
9140 | && source != op) | |
9141 | { | |
9142 | unsigned int tmp = source; | |
f12dc422 | 9143 | |
ecb96e55 JB |
9144 | source = v; |
9145 | v = tmp; | |
9146 | } | |
29b0f896 | 9147 | |
ecb96e55 JB |
9148 | if (v < MAX_OPERANDS) |
9149 | { | |
9150 | gas_assert (i.tm.opcode_modifier.vexvvvv); | |
9151 | i.vex.register_specifier = i.op[v].regs; | |
29b0f896 | 9152 | } |
c0f3af97 | 9153 | |
ecb96e55 JB |
9154 | if (op < i.operands) |
9155 | { | |
29b0f896 AM |
9156 | if (i.mem_operands) |
9157 | { | |
9158 | unsigned int fake_zero_displacement = 0; | |
4eed87de | 9159 | |
ecb96e55 | 9160 | gas_assert (i.flags[op] & Operand_Mem); |
29b0f896 | 9161 | |
63112cd6 | 9162 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 9163 | { |
260cd341 LC |
9164 | /* The index register of VSIB shouldn't be RegIZ. */ |
9165 | if (i.tm.opcode_modifier.sib != SIBMEM | |
9166 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
9167 | abort (); |
9168 | ||
9169 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
9170 | if (!i.base_reg) | |
9171 | { | |
9172 | i.sib.base = NO_BASE_REGISTER; | |
9173 | i.sib.scale = i.log2_scale_factor; | |
2f2be86b | 9174 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 9175 | i.types[op].bitfield.disp32 = 1; |
6c30d220 | 9176 | } |
260cd341 LC |
9177 | |
9178 | /* Since the mandatory SIB always has index register, so | |
9179 | the code logic remains unchanged. The non-mandatory SIB | |
9180 | without index register is allowed and will be handled | |
9181 | later. */ | |
9182 | if (i.index_reg) | |
9183 | { | |
9184 | if (i.index_reg->reg_num == RegIZ) | |
9185 | i.sib.index = NO_INDEX_REGISTER; | |
9186 | else | |
9187 | i.sib.index = i.index_reg->reg_num; | |
5b7c81bd | 9188 | set_rex_vrex (i.index_reg, REX_X, false); |
260cd341 | 9189 | } |
6c30d220 L |
9190 | } |
9191 | ||
5e042380 | 9192 | default_seg = reg_ds; |
29b0f896 AM |
9193 | |
9194 | if (i.base_reg == 0) | |
9195 | { | |
9196 | i.rm.mode = 0; | |
9197 | if (!i.disp_operands) | |
9bb129e8 | 9198 | fake_zero_displacement = 1; |
29b0f896 AM |
9199 | if (i.index_reg == 0) |
9200 | { | |
260cd341 LC |
9201 | /* Both check for VSIB and mandatory non-vector SIB. */ |
9202 | gas_assert (!i.tm.opcode_modifier.sib | |
9203 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 9204 | /* Operand is just <disp> */ |
2f2be86b | 9205 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
20f0a1fc | 9206 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
9207 | { |
9208 | /* 64bit mode overwrites the 32bit absolute | |
9209 | addressing by RIP relative addressing and | |
9210 | absolute addressing is encoded by one of the | |
9211 | redundant SIB forms. */ | |
9212 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
9213 | i.sib.base = NO_BASE_REGISTER; | |
9214 | i.sib.index = NO_INDEX_REGISTER; | |
a775efc8 | 9215 | i.types[op].bitfield.disp32 = 1; |
20f0a1fc | 9216 | } |
fc225355 L |
9217 | else if ((flag_code == CODE_16BIT) |
9218 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
9219 | { |
9220 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2f2be86b | 9221 | i.types[op].bitfield.disp16 = 1; |
20f0a1fc NC |
9222 | } |
9223 | else | |
9224 | { | |
9225 | i.rm.regmem = NO_BASE_REGISTER; | |
2f2be86b | 9226 | i.types[op].bitfield.disp32 = 1; |
29b0f896 AM |
9227 | } |
9228 | } | |
63112cd6 | 9229 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 9230 | { |
6c30d220 | 9231 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 9232 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
9233 | i.sib.index = NO_INDEX_REGISTER; |
9234 | else | |
9235 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
9236 | i.sib.base = NO_BASE_REGISTER; |
9237 | i.sib.scale = i.log2_scale_factor; | |
9238 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2f2be86b | 9239 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 9240 | i.types[op].bitfield.disp32 = 1; |
80d61d8d | 9241 | set_rex_rex2 (i.index_reg, REX_X); |
29b0f896 AM |
9242 | } |
9243 | } | |
9244 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 9245 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 9246 | { |
63112cd6 | 9247 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 9248 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
9249 | i.types[op].bitfield.disp8 = 0; |
9250 | i.types[op].bitfield.disp16 = 0; | |
a775efc8 | 9251 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 9252 | i.types[op].bitfield.disp64 = 0; |
71903a11 | 9253 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
9254 | if (! i.disp_operands) |
9255 | fake_zero_displacement = 1; | |
29b0f896 | 9256 | } |
dc821c5f | 9257 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 9258 | { |
63112cd6 | 9259 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
9260 | switch (i.base_reg->reg_num) |
9261 | { | |
9262 | case 3: /* (%bx) */ | |
9263 | if (i.index_reg == 0) | |
9264 | i.rm.regmem = 7; | |
9265 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
9266 | i.rm.regmem = i.index_reg->reg_num - 6; | |
9267 | break; | |
9268 | case 5: /* (%bp) */ | |
5e042380 | 9269 | default_seg = reg_ss; |
29b0f896 AM |
9270 | if (i.index_reg == 0) |
9271 | { | |
9272 | i.rm.regmem = 6; | |
40fb9820 | 9273 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
9274 | { |
9275 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 9276 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
9277 | i.types[op].bitfield.disp16 = 1; |
9278 | else | |
9279 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 9280 | fake_zero_displacement = 1; |
29b0f896 AM |
9281 | } |
9282 | } | |
9283 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
9284 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
9285 | break; | |
9286 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
9287 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
9288 | } | |
41eb8e88 L |
9289 | if (!fake_zero_displacement |
9290 | && !i.disp_operands | |
9291 | && i.disp_encoding) | |
9292 | { | |
9293 | fake_zero_displacement = 1; | |
9294 | if (i.disp_encoding == disp_encoding_8bit) | |
9295 | i.types[op].bitfield.disp8 = 1; | |
9296 | else | |
9297 | i.types[op].bitfield.disp16 = 1; | |
9298 | } | |
29b0f896 AM |
9299 | i.rm.mode = mode_from_disp_size (i.types[op]); |
9300 | } | |
9301 | else /* i.base_reg and 32/64 bit mode */ | |
9302 | { | |
a9aabc23 | 9303 | if (operand_type_check (i.types[op], disp)) |
40fb9820 | 9304 | { |
73053c1f JB |
9305 | i.types[op].bitfield.disp16 = 0; |
9306 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 9307 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 9308 | } |
20f0a1fc | 9309 | |
63112cd6 | 9310 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 9311 | i.rm.regmem = i.base_reg->reg_num; |
80d61d8d | 9312 | set_rex_rex2 (i.base_reg, REX_B); |
29b0f896 AM |
9313 | i.sib.base = i.base_reg->reg_num; |
9314 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
9315 | complications. */ | |
848930b2 JB |
9316 | if (!(i.base_reg->reg_flags & RegRex) |
9317 | && (i.base_reg->reg_num == EBP_REG_NUM | |
9318 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
5e042380 | 9319 | default_seg = reg_ss; |
848930b2 | 9320 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 9321 | { |
848930b2 | 9322 | fake_zero_displacement = 1; |
1a02d6b0 L |
9323 | if (i.disp_encoding == disp_encoding_32bit) |
9324 | i.types[op].bitfield.disp32 = 1; | |
9325 | else | |
9326 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
9327 | } |
9328 | i.sib.scale = i.log2_scale_factor; | |
9329 | if (i.index_reg == 0) | |
9330 | { | |
260cd341 LC |
9331 | /* Only check for VSIB. */ |
9332 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
9333 | && i.tm.opcode_modifier.sib != VECSIB256 | |
9334 | && i.tm.opcode_modifier.sib != VECSIB512); | |
9335 | ||
29b0f896 AM |
9336 | /* <disp>(%esp) becomes two byte modrm with no index |
9337 | register. We've already stored the code for esp | |
9338 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
9339 | Any base register besides %esp will not use the | |
9340 | extra modrm byte. */ | |
9341 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 9342 | } |
63112cd6 | 9343 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 9344 | { |
e968fc9b | 9345 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
9346 | i.sib.index = NO_INDEX_REGISTER; |
9347 | else | |
9348 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 | 9349 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
80d61d8d | 9350 | set_rex_rex2 (i.index_reg, REX_X); |
29b0f896 | 9351 | } |
67a4f2b7 AO |
9352 | |
9353 | if (i.disp_operands | |
9354 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
9355 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
9356 | i.rm.mode = 0; | |
9357 | else | |
a501d77e L |
9358 | { |
9359 | if (!fake_zero_displacement | |
9360 | && !i.disp_operands | |
9361 | && i.disp_encoding) | |
9362 | { | |
9363 | fake_zero_displacement = 1; | |
9364 | if (i.disp_encoding == disp_encoding_8bit) | |
9365 | i.types[op].bitfield.disp8 = 1; | |
9366 | else | |
9367 | i.types[op].bitfield.disp32 = 1; | |
9368 | } | |
9369 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
9370 | } | |
29b0f896 | 9371 | } |
252b5132 | 9372 | |
29b0f896 AM |
9373 | if (fake_zero_displacement) |
9374 | { | |
9375 | /* Fakes a zero displacement assuming that i.types[op] | |
9376 | holds the correct displacement size. */ | |
9377 | expressionS *exp; | |
9378 | ||
9c2799c2 | 9379 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
9380 | exp = &disp_expressions[i.disp_operands++]; |
9381 | i.op[op].disps = exp; | |
9382 | exp->X_op = O_constant; | |
9383 | exp->X_add_number = 0; | |
9384 | exp->X_add_symbol = (symbolS *) 0; | |
9385 | exp->X_op_symbol = (symbolS *) 0; | |
9386 | } | |
9387 | } | |
ecb96e55 JB |
9388 | else |
9389 | { | |
9390 | i.rm.mode = 3; | |
9391 | i.rm.regmem = i.op[op].regs->reg_num; | |
9392 | set_rex_vrex (i.op[op].regs, REX_B, false); | |
9393 | } | |
252b5132 | 9394 | |
ecb96e55 JB |
9395 | if (op == dest) |
9396 | dest = ~0; | |
9397 | if (op == source) | |
9398 | source = ~0; | |
9399 | } | |
9400 | else | |
9401 | { | |
9402 | i.rm.mode = 3; | |
9403 | if (!i.tm.opcode_modifier.regmem) | |
f88c9eb0 | 9404 | { |
ecb96e55 JB |
9405 | gas_assert (source < MAX_OPERANDS); |
9406 | i.rm.regmem = i.op[source].regs->reg_num; | |
9407 | set_rex_vrex (i.op[source].regs, REX_B, | |
9408 | dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx); | |
9409 | source = ~0; | |
f88c9eb0 | 9410 | } |
ecb96e55 | 9411 | else |
29b0f896 | 9412 | { |
ecb96e55 JB |
9413 | gas_assert (dest < MAX_OPERANDS); |
9414 | i.rm.regmem = i.op[dest].regs->reg_num; | |
9415 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); | |
9416 | dest = ~0; | |
29b0f896 | 9417 | } |
ecb96e55 | 9418 | } |
252b5132 | 9419 | |
ecb96e55 JB |
9420 | /* Fill in i.rm.reg field with extension opcode (if any) or the |
9421 | appropriate register. */ | |
9422 | if (i.tm.extension_opcode != None) | |
9423 | i.rm.reg = i.tm.extension_opcode; | |
9424 | else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS) | |
9425 | { | |
9426 | i.rm.reg = i.op[dest].regs->reg_num; | |
9427 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); | |
9428 | } | |
9429 | else | |
9430 | { | |
9431 | gas_assert (source < MAX_OPERANDS); | |
9432 | i.rm.reg = i.op[source].regs->reg_num; | |
9433 | set_rex_vrex (i.op[source].regs, REX_R, false); | |
29b0f896 | 9434 | } |
ecb96e55 JB |
9435 | |
9436 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) | |
9437 | { | |
9438 | gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR); | |
9439 | i.rex &= ~REX_R; | |
9440 | add_prefix (LOCK_PREFIX_OPCODE); | |
9441 | } | |
9442 | ||
29b0f896 AM |
9443 | return default_seg; |
9444 | } | |
252b5132 | 9445 | |
48ef937e JB |
9446 | static INLINE void |
9447 | frag_opcode_byte (unsigned char byte) | |
9448 | { | |
9449 | if (now_seg != absolute_section) | |
9450 | FRAG_APPEND_1_CHAR (byte); | |
9451 | else | |
9452 | ++abs_section_offset; | |
9453 | } | |
9454 | ||
376cd056 JB |
9455 | static unsigned int |
9456 | flip_code16 (unsigned int code16) | |
9457 | { | |
9458 | gas_assert (i.tm.operands == 1); | |
9459 | ||
9460 | return !(i.prefix[REX_PREFIX] & REX_W) | |
9461 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
376cd056 JB |
9462 | : i.tm.operand_types[0].bitfield.disp16) |
9463 | ? CODE16 : 0; | |
9464 | } | |
9465 | ||
29b0f896 | 9466 | static void |
e3bb37b5 | 9467 | output_branch (void) |
29b0f896 AM |
9468 | { |
9469 | char *p; | |
f8a5c266 | 9470 | int size; |
29b0f896 AM |
9471 | int code16; |
9472 | int prefix; | |
9473 | relax_substateT subtype; | |
9474 | symbolS *sym; | |
9475 | offsetT off; | |
9476 | ||
48ef937e JB |
9477 | if (now_seg == absolute_section) |
9478 | { | |
9479 | as_bad (_("relaxable branches not supported in absolute section")); | |
9480 | return; | |
9481 | } | |
9482 | ||
f8a5c266 | 9483 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
1a42a9fe | 9484 | size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL; |
29b0f896 AM |
9485 | |
9486 | prefix = 0; | |
9487 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 9488 | { |
29b0f896 AM |
9489 | prefix = 1; |
9490 | i.prefixes -= 1; | |
376cd056 | 9491 | code16 ^= flip_code16(code16); |
252b5132 | 9492 | } |
29b0f896 AM |
9493 | /* Pentium4 branch hints. */ |
9494 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
9495 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 9496 | { |
29b0f896 AM |
9497 | prefix++; |
9498 | i.prefixes--; | |
9499 | } | |
9500 | if (i.prefix[REX_PREFIX] != 0) | |
9501 | { | |
9502 | prefix++; | |
9503 | i.prefixes--; | |
2f66722d AM |
9504 | } |
9505 | ||
7e8b059b L |
9506 | /* BND prefixed jump. */ |
9507 | if (i.prefix[BND_PREFIX] != 0) | |
9508 | { | |
6cb0a70e JB |
9509 | prefix++; |
9510 | i.prefixes--; | |
7e8b059b L |
9511 | } |
9512 | ||
f2810fe0 | 9513 | if (i.prefixes != 0) |
76d3f746 | 9514 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
29b0f896 AM |
9515 | |
9516 | /* It's always a symbol; End frag & setup for relax. | |
9517 | Make sure there is enough room in this frag for the largest | |
9518 | instruction we may generate in md_convert_frag. This is 2 | |
9519 | bytes for the opcode and room for the prefix and largest | |
9520 | displacement. */ | |
9521 | frag_grow (prefix + 2 + 4); | |
9522 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
9523 | p = frag_more (prefix + 1); | |
9524 | if (i.prefix[DATA_PREFIX] != 0) | |
9525 | *p++ = DATA_PREFIX_OPCODE; | |
9526 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
9527 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
9528 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
9529 | if (i.prefix[BND_PREFIX] != 0) |
9530 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
9531 | if (i.prefix[REX_PREFIX] != 0) |
9532 | *p++ = i.prefix[REX_PREFIX]; | |
9533 | *p = i.tm.base_opcode; | |
9534 | ||
9535 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 9536 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 9537 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 9538 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 9539 | else |
f8a5c266 | 9540 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 9541 | subtype |= code16; |
3e73aa7c | 9542 | |
29b0f896 AM |
9543 | sym = i.op[0].disps->X_add_symbol; |
9544 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 9545 | |
29b0f896 AM |
9546 | if (i.op[0].disps->X_op != O_constant |
9547 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 9548 | { |
29b0f896 AM |
9549 | /* Handle complex expressions. */ |
9550 | sym = make_expr_symbol (i.op[0].disps); | |
9551 | off = 0; | |
9552 | } | |
3e73aa7c | 9553 | |
29b0f896 AM |
9554 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
9555 | Pass reloc in fr_var. */ | |
d258b828 | 9556 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 9557 | } |
3e73aa7c | 9558 | |
bd7ab16b L |
9559 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9560 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
9561 | symbol S. */ | |
9562 | ||
5b7c81bd | 9563 | static bool |
bd7ab16b L |
9564 | need_plt32_p (symbolS *s) |
9565 | { | |
9566 | /* PLT32 relocation is ELF only. */ | |
9567 | if (!IS_ELF) | |
5b7c81bd | 9568 | return false; |
bd7ab16b | 9569 | |
a5def729 RO |
9570 | #ifdef TE_SOLARIS |
9571 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
9572 | krtld support it. */ | |
5b7c81bd | 9573 | return false; |
a5def729 RO |
9574 | #endif |
9575 | ||
bd7ab16b L |
9576 | /* Since there is no need to prepare for PLT branch on x86-64, we |
9577 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
9578 | be used as a marker for 32-bit PC-relative branches. */ | |
9579 | if (!object_64bit) | |
5b7c81bd | 9580 | return false; |
bd7ab16b | 9581 | |
44365e88 | 9582 | if (s == NULL) |
5b7c81bd | 9583 | return false; |
44365e88 | 9584 | |
bd7ab16b L |
9585 | /* Weak or undefined symbol need PLT32 relocation. */ |
9586 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
5b7c81bd | 9587 | return true; |
bd7ab16b L |
9588 | |
9589 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
9590 | if (! S_IS_EXTERNAL (s)) | |
5b7c81bd | 9591 | return false; |
bd7ab16b L |
9592 | |
9593 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
9594 | non-default visibilities are treated as normal global symbol | |
9595 | so that PLT32 relocation can be used as a marker for 32-bit | |
9596 | PC-relative branches. It is useful for linker relaxation. */ | |
5b7c81bd | 9597 | return true; |
bd7ab16b L |
9598 | } |
9599 | #endif | |
9600 | ||
29b0f896 | 9601 | static void |
e3bb37b5 | 9602 | output_jump (void) |
29b0f896 AM |
9603 | { |
9604 | char *p; | |
9605 | int size; | |
3e02c1cc | 9606 | fixS *fixP; |
bd7ab16b | 9607 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 9608 | |
0cfa3eb3 | 9609 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
9610 | { |
9611 | /* This is a loop or jecxz type instruction. */ | |
9612 | size = 1; | |
9613 | if (i.prefix[ADDR_PREFIX] != 0) | |
9614 | { | |
48ef937e | 9615 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
9616 | i.prefixes -= 1; |
9617 | } | |
9618 | /* Pentium4 branch hints. */ | |
9619 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
9620 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
9621 | { | |
48ef937e | 9622 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 9623 | i.prefixes--; |
3e73aa7c JH |
9624 | } |
9625 | } | |
29b0f896 AM |
9626 | else |
9627 | { | |
9628 | int code16; | |
3e73aa7c | 9629 | |
29b0f896 AM |
9630 | code16 = 0; |
9631 | if (flag_code == CODE_16BIT) | |
9632 | code16 = CODE16; | |
3e73aa7c | 9633 | |
29b0f896 AM |
9634 | if (i.prefix[DATA_PREFIX] != 0) |
9635 | { | |
48ef937e | 9636 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 9637 | i.prefixes -= 1; |
376cd056 | 9638 | code16 ^= flip_code16(code16); |
29b0f896 | 9639 | } |
252b5132 | 9640 | |
29b0f896 AM |
9641 | size = 4; |
9642 | if (code16) | |
9643 | size = 2; | |
9644 | } | |
9fcc94b6 | 9645 | |
6cb0a70e JB |
9646 | /* BND prefixed jump. */ |
9647 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 9648 | { |
48ef937e | 9649 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
9650 | i.prefixes -= 1; |
9651 | } | |
252b5132 | 9652 | |
6cb0a70e | 9653 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 9654 | { |
48ef937e | 9655 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
9656 | i.prefixes -= 1; |
9657 | } | |
9658 | ||
f2810fe0 | 9659 | if (i.prefixes != 0) |
76d3f746 | 9660 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
e0890092 | 9661 | |
48ef937e JB |
9662 | if (now_seg == absolute_section) |
9663 | { | |
9a182d04 | 9664 | abs_section_offset += i.opcode_length + size; |
48ef937e JB |
9665 | return; |
9666 | } | |
9667 | ||
9a182d04 JB |
9668 | p = frag_more (i.opcode_length + size); |
9669 | switch (i.opcode_length) | |
42164a71 L |
9670 | { |
9671 | case 2: | |
9672 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 9673 | /* Fall through. */ |
42164a71 L |
9674 | case 1: |
9675 | *p++ = i.tm.base_opcode; | |
9676 | break; | |
9677 | default: | |
9678 | abort (); | |
9679 | } | |
e0890092 | 9680 | |
bd7ab16b | 9681 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
9682 | if (flag_code == CODE_64BIT && size == 4 |
9683 | && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0 | |
bd7ab16b L |
9684 | && need_plt32_p (i.op[0].disps->X_add_symbol)) |
9685 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
9686 | #endif | |
9687 | ||
9688 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
9689 | ||
3e02c1cc | 9690 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 9691 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc | 9692 | |
eb19308f JB |
9693 | /* All jumps handled here are signed, but don't unconditionally use a |
9694 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
9695 | around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN) | |
9696 | respectively. */ | |
9697 | switch (size) | |
9698 | { | |
9699 | case 1: | |
9700 | fixP->fx_signed = 1; | |
9701 | break; | |
9702 | ||
9703 | case 2: | |
7fc69528 | 9704 | if (i.tm.mnem_off == MN_xbegin) |
eb19308f JB |
9705 | fixP->fx_signed = 1; |
9706 | break; | |
9707 | ||
9708 | case 4: | |
9709 | if (flag_code == CODE_64BIT) | |
9710 | fixP->fx_signed = 1; | |
9711 | break; | |
9712 | } | |
29b0f896 | 9713 | } |
e0890092 | 9714 | |
29b0f896 | 9715 | static void |
e3bb37b5 | 9716 | output_interseg_jump (void) |
29b0f896 AM |
9717 | { |
9718 | char *p; | |
9719 | int size; | |
9720 | int prefix; | |
9721 | int code16; | |
252b5132 | 9722 | |
29b0f896 AM |
9723 | code16 = 0; |
9724 | if (flag_code == CODE_16BIT) | |
9725 | code16 = CODE16; | |
a217f122 | 9726 | |
29b0f896 AM |
9727 | prefix = 0; |
9728 | if (i.prefix[DATA_PREFIX] != 0) | |
9729 | { | |
9730 | prefix = 1; | |
9731 | i.prefixes -= 1; | |
9732 | code16 ^= CODE16; | |
9733 | } | |
6cb0a70e JB |
9734 | |
9735 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 9736 | |
29b0f896 AM |
9737 | size = 4; |
9738 | if (code16) | |
9739 | size = 2; | |
252b5132 | 9740 | |
f2810fe0 | 9741 | if (i.prefixes != 0) |
76d3f746 | 9742 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
252b5132 | 9743 | |
48ef937e JB |
9744 | if (now_seg == absolute_section) |
9745 | { | |
9746 | abs_section_offset += prefix + 1 + 2 + size; | |
9747 | return; | |
9748 | } | |
9749 | ||
29b0f896 AM |
9750 | /* 1 opcode; 2 segment; offset */ |
9751 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 9752 | |
29b0f896 AM |
9753 | if (i.prefix[DATA_PREFIX] != 0) |
9754 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 9755 | |
29b0f896 AM |
9756 | if (i.prefix[REX_PREFIX] != 0) |
9757 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 9758 | |
29b0f896 AM |
9759 | *p++ = i.tm.base_opcode; |
9760 | if (i.op[1].imms->X_op == O_constant) | |
9761 | { | |
9762 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 9763 | |
29b0f896 AM |
9764 | if (size == 2 |
9765 | && !fits_in_unsigned_word (n) | |
9766 | && !fits_in_signed_word (n)) | |
9767 | { | |
9768 | as_bad (_("16-bit jump out of range")); | |
9769 | return; | |
9770 | } | |
9771 | md_number_to_chars (p, n, size); | |
9772 | } | |
9773 | else | |
9774 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 9775 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
6d96a594 C |
9776 | |
9777 | p += size; | |
9778 | if (i.op[0].imms->X_op == O_constant) | |
9779 | md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2); | |
9780 | else | |
9781 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
9782 | i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0])); | |
29b0f896 | 9783 | } |
a217f122 | 9784 | |
b4a3a7b4 L |
9785 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9786 | void | |
9787 | x86_cleanup (void) | |
9788 | { | |
9789 | char *p; | |
9790 | asection *seg = now_seg; | |
9791 | subsegT subseg = now_subseg; | |
9792 | asection *sec; | |
9793 | unsigned int alignment, align_size_1; | |
9794 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
9795 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
9796 | unsigned int padding; | |
9797 | ||
1273b2f8 | 9798 | if (!IS_ELF || !x86_used_note) |
b4a3a7b4 L |
9799 | return; |
9800 | ||
b4a3a7b4 L |
9801 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
9802 | ||
9803 | /* The .note.gnu.property section layout: | |
9804 | ||
9805 | Field Length Contents | |
9806 | ---- ---- ---- | |
9807 | n_namsz 4 4 | |
9808 | n_descsz 4 The note descriptor size | |
9809 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
9810 | n_name 4 "GNU" | |
9811 | n_desc n_descsz The program property array | |
9812 | .... .... .... | |
9813 | */ | |
9814 | ||
9815 | /* Create the .note.gnu.property section. */ | |
9816 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 9817 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
9818 | (SEC_ALLOC |
9819 | | SEC_LOAD | |
9820 | | SEC_DATA | |
9821 | | SEC_HAS_CONTENTS | |
9822 | | SEC_READONLY)); | |
9823 | ||
9824 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
9825 | { | |
9826 | align_size_1 = 7; | |
9827 | alignment = 3; | |
9828 | } | |
9829 | else | |
9830 | { | |
9831 | align_size_1 = 3; | |
9832 | alignment = 2; | |
9833 | } | |
9834 | ||
fd361982 | 9835 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
9836 | elf_section_type (sec) = SHT_NOTE; |
9837 | ||
1273b2f8 L |
9838 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size |
9839 | + 4-byte data */ | |
9840 | isa_1_descsz_raw = 4 + 4 + 4; | |
9841 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
9842 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
b4a3a7b4 L |
9843 | |
9844 | feature_2_descsz_raw = isa_1_descsz; | |
9845 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
1273b2f8 | 9846 | + 4-byte data */ |
b4a3a7b4 L |
9847 | feature_2_descsz_raw += 4 + 4 + 4; |
9848 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
9849 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
9850 | & ~align_size_1); | |
9851 | ||
9852 | descsz = feature_2_descsz; | |
9853 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
9854 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
9855 | ||
9856 | /* Write n_namsz. */ | |
9857 | md_number_to_chars (p, (valueT) 4, 4); | |
9858 | ||
9859 | /* Write n_descsz. */ | |
9860 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
9861 | ||
9862 | /* Write n_type. */ | |
9863 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
9864 | ||
9865 | /* Write n_name. */ | |
9866 | memcpy (p + 4 * 3, "GNU", 4); | |
9867 | ||
1273b2f8 L |
9868 | /* Write 4-byte type. */ |
9869 | md_number_to_chars (p + 4 * 4, | |
9870 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
b4a3a7b4 | 9871 | |
1273b2f8 L |
9872 | /* Write 4-byte data size. */ |
9873 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
b4a3a7b4 | 9874 | |
1273b2f8 L |
9875 | /* Write 4-byte data. */ |
9876 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
b4a3a7b4 | 9877 | |
1273b2f8 L |
9878 | /* Zero out paddings. */ |
9879 | padding = isa_1_descsz - isa_1_descsz_raw; | |
9880 | if (padding) | |
9881 | memset (p + 4 * 7, 0, padding); | |
b4a3a7b4 L |
9882 | |
9883 | /* Write 4-byte type. */ | |
9884 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
9885 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
9886 | ||
9887 | /* Write 4-byte data size. */ | |
9888 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
9889 | ||
9890 | /* Write 4-byte data. */ | |
9891 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
9892 | (valueT) x86_feature_2_used, 4); | |
9893 | ||
9894 | /* Zero out paddings. */ | |
9895 | padding = feature_2_descsz - feature_2_descsz_raw; | |
9896 | if (padding) | |
9897 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
9898 | ||
9899 | /* We probably can't restore the current segment, for there likely | |
9900 | isn't one yet... */ | |
9901 | if (seg && subseg) | |
9902 | subseg_set (seg, subseg); | |
9903 | } | |
b52c4ee4 IB |
9904 | |
9905 | bool | |
9906 | x86_support_sframe_p (void) | |
9907 | { | |
3e3e792a | 9908 | /* At this time, SFrame stack trace is supported for AMD64 ABI only. */ |
b52c4ee4 IB |
9909 | return (x86_elf_abi == X86_64_ABI); |
9910 | } | |
9911 | ||
9912 | bool | |
9913 | x86_sframe_ra_tracking_p (void) | |
9914 | { | |
9915 | /* In AMD64, return address is always stored on the stack at a fixed offset | |
9916 | from the CFA (provided via x86_sframe_cfa_ra_offset ()). | |
9917 | Do not track explicitly via an SFrame Frame Row Entry. */ | |
9918 | return false; | |
9919 | } | |
9920 | ||
9921 | offsetT | |
9922 | x86_sframe_cfa_ra_offset (void) | |
9923 | { | |
9924 | gas_assert (x86_elf_abi == X86_64_ABI); | |
9925 | return (offsetT) -8; | |
9926 | } | |
9927 | ||
9928 | unsigned char | |
9929 | x86_sframe_get_abi_arch (void) | |
9930 | { | |
9931 | unsigned char sframe_abi_arch = 0; | |
9932 | ||
9933 | if (x86_support_sframe_p ()) | |
9934 | { | |
9935 | gas_assert (!target_big_endian); | |
9936 | sframe_abi_arch = SFRAME_ABI_AMD64_ENDIAN_LITTLE; | |
9937 | } | |
9938 | ||
9939 | return sframe_abi_arch; | |
9940 | } | |
9941 | ||
b4a3a7b4 L |
9942 | #endif |
9943 | ||
9c33702b JB |
9944 | static unsigned int |
9945 | encoding_length (const fragS *start_frag, offsetT start_off, | |
9946 | const char *frag_now_ptr) | |
9947 | { | |
9948 | unsigned int len = 0; | |
9949 | ||
9950 | if (start_frag != frag_now) | |
9951 | { | |
9952 | const fragS *fr = start_frag; | |
9953 | ||
9954 | do { | |
9955 | len += fr->fr_fix; | |
9956 | fr = fr->fr_next; | |
9957 | } while (fr && fr != frag_now); | |
9958 | } | |
9959 | ||
9960 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
9961 | } | |
9962 | ||
e379e5f3 | 9963 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
9964 | be macro-fused with conditional jumps. |
9965 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
9966 | or is one of the following format: | |
9967 | ||
9968 | cmp m, imm | |
9969 | add m, imm | |
9970 | sub m, imm | |
9971 | test m, imm | |
9972 | and m, imm | |
9973 | inc m | |
9974 | dec m | |
9975 | ||
9976 | it is unfusible. */ | |
e379e5f3 L |
9977 | |
9978 | static int | |
79d72f45 | 9979 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9980 | { |
9981 | /* No RIP address. */ | |
9982 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
9983 | return 0; | |
9984 | ||
389d00a5 | 9985 | /* No opcodes outside of base encoding space. */ |
ddb62495 | 9986 | if (i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
9987 | return 0; |
9988 | ||
79d72f45 HL |
9989 | /* add, sub without add/sub m, imm. */ |
9990 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
9991 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
9992 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 9993 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 9994 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
9995 | { |
9996 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9997 | return !(i.mem_operands && i.imm_operands); | |
9998 | } | |
e379e5f3 | 9999 | |
79d72f45 HL |
10000 | /* and without and m, imm. */ |
10001 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
10002 | || ((i.tm.base_opcode | 3) == 0x83 | |
10003 | && i.tm.extension_opcode == 0x4)) | |
10004 | { | |
10005 | *mf_cmp_p = mf_cmp_test_and; | |
10006 | return !(i.mem_operands && i.imm_operands); | |
10007 | } | |
10008 | ||
10009 | /* test without test m imm. */ | |
e379e5f3 L |
10010 | if ((i.tm.base_opcode | 1) == 0x85 |
10011 | || (i.tm.base_opcode | 1) == 0xa9 | |
10012 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
10013 | && i.tm.extension_opcode == 0)) |
10014 | { | |
10015 | *mf_cmp_p = mf_cmp_test_and; | |
10016 | return !(i.mem_operands && i.imm_operands); | |
10017 | } | |
10018 | ||
10019 | /* cmp without cmp m, imm. */ | |
10020 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
10021 | || ((i.tm.base_opcode | 3) == 0x83 |
10022 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
10023 | { |
10024 | *mf_cmp_p = mf_cmp_alu_cmp; | |
10025 | return !(i.mem_operands && i.imm_operands); | |
10026 | } | |
e379e5f3 | 10027 | |
79d72f45 | 10028 | /* inc, dec without inc/dec m. */ |
734dfd1c | 10029 | if ((is_cpu (&i.tm, CpuNo64) |
e379e5f3 L |
10030 | && (i.tm.base_opcode | 0xf) == 0x4f) |
10031 | || ((i.tm.base_opcode | 1) == 0xff | |
10032 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
10033 | { |
10034 | *mf_cmp_p = mf_cmp_incdec; | |
10035 | return !i.mem_operands; | |
10036 | } | |
e379e5f3 L |
10037 | |
10038 | return 0; | |
10039 | } | |
10040 | ||
10041 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
10042 | ||
10043 | static int | |
b5482fe5 JB |
10044 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind *mf_cmp_p, |
10045 | const struct last_insn *last_insn) | |
e379e5f3 L |
10046 | { |
10047 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
10048 | if (!align_branch_power | |
10049 | || now_seg == absolute_section | |
10050 | || !cpu_arch_flags.bitfield.cpui386 | |
10051 | || !(align_branch & align_branch_fused_bit)) | |
10052 | return 0; | |
10053 | ||
79d72f45 | 10054 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 | 10055 | { |
b5482fe5 | 10056 | if (last_insn->kind == last_insn_other) |
e379e5f3 L |
10057 | return 1; |
10058 | if (flag_debug) | |
b5482fe5 | 10059 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 10060 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 10061 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
10062 | } |
10063 | ||
10064 | return 0; | |
10065 | } | |
10066 | ||
10067 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
10068 | ||
10069 | static int | |
b5482fe5 | 10070 | add_branch_prefix_frag_p (const struct last_insn *last_insn) |
e379e5f3 L |
10071 | { |
10072 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
10073 | to PadLock instructions since they include prefixes in opcode. */ | |
10074 | if (!align_branch_power | |
10075 | || !align_branch_prefix_size | |
10076 | || now_seg == absolute_section | |
734dfd1c | 10077 | || is_cpu (&i.tm, CpuPadLock) |
e379e5f3 L |
10078 | || !cpu_arch_flags.bitfield.cpui386) |
10079 | return 0; | |
10080 | ||
10081 | /* Don't add prefix if it is a prefix or there is no operand in case | |
10082 | that segment prefix is special. */ | |
10083 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
10084 | return 0; | |
10085 | ||
b5482fe5 | 10086 | if (last_insn->kind == last_insn_other) |
e379e5f3 L |
10087 | return 1; |
10088 | ||
10089 | if (flag_debug) | |
b5482fe5 | 10090 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 10091 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 10092 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
10093 | |
10094 | return 0; | |
10095 | } | |
10096 | ||
10097 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
10098 | ||
10099 | static int | |
79d72f45 | 10100 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
b5482fe5 JB |
10101 | enum mf_jcc_kind *mf_jcc_p, |
10102 | const struct last_insn *last_insn) | |
e379e5f3 L |
10103 | { |
10104 | int add_padding; | |
10105 | ||
10106 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
10107 | if (!align_branch_power | |
10108 | || now_seg == absolute_section | |
389d00a5 | 10109 | || !cpu_arch_flags.bitfield.cpui386 |
ddb62495 | 10110 | || i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
10111 | return 0; |
10112 | ||
10113 | add_padding = 0; | |
10114 | ||
10115 | /* Check for jcc and direct jmp. */ | |
10116 | if (i.tm.opcode_modifier.jump == JUMP) | |
10117 | { | |
10118 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
10119 | { | |
10120 | *branch_p = align_branch_jmp; | |
10121 | add_padding = align_branch & align_branch_jmp_bit; | |
10122 | } | |
10123 | else | |
10124 | { | |
79d72f45 HL |
10125 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
10126 | igore the lowest bit. */ | |
10127 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
10128 | *branch_p = align_branch_jcc; |
10129 | if ((align_branch & align_branch_jcc_bit)) | |
10130 | add_padding = 1; | |
10131 | } | |
10132 | } | |
e379e5f3 L |
10133 | else if ((i.tm.base_opcode | 1) == 0xc3) |
10134 | { | |
10135 | /* Near ret. */ | |
10136 | *branch_p = align_branch_ret; | |
10137 | if ((align_branch & align_branch_ret_bit)) | |
10138 | add_padding = 1; | |
10139 | } | |
10140 | else | |
10141 | { | |
10142 | /* Check for indirect jmp, direct and indirect calls. */ | |
10143 | if (i.tm.base_opcode == 0xe8) | |
10144 | { | |
10145 | /* Direct call. */ | |
10146 | *branch_p = align_branch_call; | |
10147 | if ((align_branch & align_branch_call_bit)) | |
10148 | add_padding = 1; | |
10149 | } | |
10150 | else if (i.tm.base_opcode == 0xff | |
10151 | && (i.tm.extension_opcode == 2 | |
10152 | || i.tm.extension_opcode == 4)) | |
10153 | { | |
10154 | /* Indirect call and jmp. */ | |
10155 | *branch_p = align_branch_indirect; | |
10156 | if ((align_branch & align_branch_indirect_bit)) | |
10157 | add_padding = 1; | |
10158 | } | |
10159 | ||
10160 | if (add_padding | |
10161 | && i.disp_operands | |
10162 | && tls_get_addr | |
10163 | && (i.op[0].disps->X_op == O_symbol | |
10164 | || (i.op[0].disps->X_op == O_subtract | |
10165 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
10166 | { | |
10167 | symbolS *s = i.op[0].disps->X_add_symbol; | |
10168 | /* No padding to call to global or undefined tls_get_addr. */ | |
10169 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
10170 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
10171 | return 0; | |
10172 | } | |
10173 | } | |
10174 | ||
10175 | if (add_padding | |
b5482fe5 | 10176 | && last_insn->kind != last_insn_other) |
e379e5f3 L |
10177 | { |
10178 | if (flag_debug) | |
b5482fe5 | 10179 | as_warn_where (last_insn->file, last_insn->line, |
e379e5f3 | 10180 | _("`%s` skips -malign-branch-boundary on `%s`"), |
b5482fe5 | 10181 | last_insn->name, insn_name (&i.tm)); |
e379e5f3 L |
10182 | return 0; |
10183 | } | |
10184 | ||
10185 | return add_padding; | |
10186 | } | |
10187 | ||
29b0f896 | 10188 | static void |
b5482fe5 | 10189 | output_insn (const struct last_insn *last_insn) |
29b0f896 | 10190 | { |
2bbd9c25 JJ |
10191 | fragS *insn_start_frag; |
10192 | offsetT insn_start_off; | |
e379e5f3 L |
10193 | fragS *fragP = NULL; |
10194 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
10195 | /* The initializer is arbitrary just to avoid uninitialized error. |
10196 | it's actually either assigned in add_branch_padding_frag_p | |
10197 | or never be used. */ | |
10198 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 10199 | |
b4a3a7b4 | 10200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 10201 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 | 10202 | { |
32930e4e | 10203 | if ((i.xstate & xstate_tmm) == xstate_tmm |
734dfd1c | 10204 | || is_cpu (&i.tm, CpuAMX_TILE)) |
32930e4e L |
10205 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; |
10206 | ||
734dfd1c JB |
10207 | if (is_cpu (&i.tm, Cpu8087) |
10208 | || is_cpu (&i.tm, Cpu287) | |
10209 | || is_cpu (&i.tm, Cpu387) | |
10210 | || is_cpu (&i.tm, Cpu687) | |
10211 | || is_cpu (&i.tm, CpuFISTTP)) | |
b4a3a7b4 | 10212 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; |
014d61ea | 10213 | |
921eafea | 10214 | if ((i.xstate & xstate_mmx) |
7fc69528 JB |
10215 | || i.tm.mnem_off == MN_emms |
10216 | || i.tm.mnem_off == MN_femms) | |
b4a3a7b4 | 10217 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
014d61ea | 10218 | |
32930e4e L |
10219 | if (i.index_reg) |
10220 | { | |
10221 | if (i.index_reg->reg_type.bitfield.zmmword) | |
10222 | i.xstate |= xstate_zmm; | |
10223 | else if (i.index_reg->reg_type.bitfield.ymmword) | |
10224 | i.xstate |= xstate_ymm; | |
10225 | else if (i.index_reg->reg_type.bitfield.xmmword) | |
10226 | i.xstate |= xstate_xmm; | |
10227 | } | |
014d61ea JB |
10228 | |
10229 | /* vzeroall / vzeroupper */ | |
734dfd1c | 10230 | if (i.tm.base_opcode == 0x77 && is_cpu (&i.tm, CpuAVX)) |
014d61ea JB |
10231 | i.xstate |= xstate_ymm; |
10232 | ||
c4694f17 | 10233 | if ((i.xstate & xstate_xmm) |
389d00a5 JB |
10234 | /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */ |
10235 | || (i.tm.base_opcode == 0xae | |
734dfd1c JB |
10236 | && (is_cpu (&i.tm, CpuSSE) |
10237 | || is_cpu (&i.tm, CpuAVX))) | |
10238 | || is_cpu (&i.tm, CpuWideKL) | |
10239 | || is_cpu (&i.tm, CpuKL)) | |
b4a3a7b4 | 10240 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
014d61ea | 10241 | |
921eafea | 10242 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 10243 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 10244 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 | 10245 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
6225c532 | 10246 | if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask) |
32930e4e | 10247 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK; |
734dfd1c | 10248 | if (is_cpu (&i.tm, CpuFXSR)) |
b4a3a7b4 | 10249 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; |
734dfd1c | 10250 | if (is_cpu (&i.tm, CpuXsave)) |
b4a3a7b4 | 10251 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; |
734dfd1c | 10252 | if (is_cpu (&i.tm, CpuXsaveopt)) |
b4a3a7b4 | 10253 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; |
734dfd1c | 10254 | if (is_cpu (&i.tm, CpuXSAVEC)) |
b4a3a7b4 | 10255 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; |
b0ab0693 L |
10256 | |
10257 | if (x86_feature_2_used | |
734dfd1c JB |
10258 | || is_cpu (&i.tm, CpuCMOV) |
10259 | || is_cpu (&i.tm, CpuSYSCALL) | |
7fc69528 | 10260 | || i.tm.mnem_off == MN_cmpxchg8b) |
b0ab0693 | 10261 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; |
734dfd1c JB |
10262 | if (is_cpu (&i.tm, CpuSSE3) |
10263 | || is_cpu (&i.tm, CpuSSSE3) | |
10264 | || is_cpu (&i.tm, CpuSSE4_1) | |
10265 | || is_cpu (&i.tm, CpuSSE4_2) | |
10266 | || is_cpu (&i.tm, CpuCX16) | |
10267 | || is_cpu (&i.tm, CpuPOPCNT) | |
b0ab0693 L |
10268 | /* LAHF-SAHF insns in 64-bit mode. */ |
10269 | || (flag_code == CODE_64BIT | |
35648716 | 10270 | && (i.tm.base_opcode | 1) == 0x9f |
ddb62495 | 10271 | && i.tm.opcode_space == SPACE_BASE)) |
b0ab0693 | 10272 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2; |
734dfd1c JB |
10273 | if (is_cpu (&i.tm, CpuAVX) |
10274 | || is_cpu (&i.tm, CpuAVX2) | |
a9860005 JB |
10275 | /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ, |
10276 | XOP, FMA4, LPW, TBM, and AMX. */ | |
b0ab0693 | 10277 | || (i.tm.opcode_modifier.vex |
734dfd1c JB |
10278 | && !is_cpu (&i.tm, CpuAVX512F) |
10279 | && !is_cpu (&i.tm, CpuAVX512BW) | |
10280 | && !is_cpu (&i.tm, CpuAVX512DQ) | |
10281 | && !is_cpu (&i.tm, CpuXOP) | |
10282 | && !is_cpu (&i.tm, CpuFMA4) | |
10283 | && !is_cpu (&i.tm, CpuLWP) | |
10284 | && !is_cpu (&i.tm, CpuTBM) | |
b0ab0693 | 10285 | && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM)) |
734dfd1c JB |
10286 | || is_cpu (&i.tm, CpuF16C) |
10287 | || is_cpu (&i.tm, CpuFMA) | |
10288 | || is_cpu (&i.tm, CpuLZCNT) | |
10289 | || is_cpu (&i.tm, CpuMovbe) | |
10290 | || is_cpu (&i.tm, CpuXSAVES) | |
b0ab0693 L |
10291 | || (x86_feature_2_used |
10292 | & (GNU_PROPERTY_X86_FEATURE_2_XSAVE | |
10293 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT | |
10294 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0) | |
10295 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3; | |
734dfd1c JB |
10296 | if (is_cpu (&i.tm, CpuAVX512F) |
10297 | || is_cpu (&i.tm, CpuAVX512BW) | |
10298 | || is_cpu (&i.tm, CpuAVX512DQ) | |
10299 | || is_cpu (&i.tm, CpuAVX512VL) | |
a9860005 JB |
10300 | /* Any EVEX encoded insns except for AVX512ER, AVX512PF, |
10301 | AVX512-4FMAPS, and AVX512-4VNNIW. */ | |
b0ab0693 | 10302 | || (i.tm.opcode_modifier.evex |
734dfd1c JB |
10303 | && !is_cpu (&i.tm, CpuAVX512ER) |
10304 | && !is_cpu (&i.tm, CpuAVX512PF) | |
10305 | && !is_cpu (&i.tm, CpuAVX512_4FMAPS) | |
10306 | && !is_cpu (&i.tm, CpuAVX512_4VNNIW))) | |
b0ab0693 | 10307 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4; |
b4a3a7b4 L |
10308 | } |
10309 | #endif | |
10310 | ||
29b0f896 AM |
10311 | /* Tie dwarf2 debug info to the address at the start of the insn. |
10312 | We can't do this after the insn has been output as the current | |
10313 | frag may have been closed off. eg. by frag_var. */ | |
10314 | dwarf2_emit_insn (0); | |
10315 | ||
2bbd9c25 JJ |
10316 | insn_start_frag = frag_now; |
10317 | insn_start_off = frag_now_fix (); | |
10318 | ||
b5482fe5 | 10319 | if (add_branch_padding_frag_p (&branch, &mf_jcc, last_insn)) |
e379e5f3 L |
10320 | { |
10321 | char *p; | |
10322 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
10323 | unsigned int max_branch_padding_size = 14; | |
10324 | ||
10325 | /* Align section to boundary. */ | |
10326 | record_alignment (now_seg, align_branch_power); | |
10327 | ||
10328 | /* Make room for padding. */ | |
10329 | frag_grow (max_branch_padding_size); | |
10330 | ||
10331 | /* Start of the padding. */ | |
10332 | p = frag_more (0); | |
10333 | ||
10334 | fragP = frag_now; | |
10335 | ||
10336 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
10337 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
10338 | NULL, 0, p); | |
10339 | ||
79d72f45 | 10340 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
10341 | fragP->tc_frag_data.branch_type = branch; |
10342 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
10343 | } | |
10344 | ||
d59a54c2 JB |
10345 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT) |
10346 | && !pre_386_16bit_warned) | |
10347 | { | |
10348 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
10349 | pre_386_16bit_warned = true; | |
10350 | } | |
10351 | ||
29b0f896 | 10352 | /* Output jumps. */ |
0cfa3eb3 | 10353 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 10354 | output_branch (); |
0cfa3eb3 JB |
10355 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
10356 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 10357 | output_jump (); |
0cfa3eb3 | 10358 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
10359 | output_interseg_jump (); |
10360 | else | |
10361 | { | |
10362 | /* Output normal instructions here. */ | |
10363 | char *p; | |
10364 | unsigned char *q; | |
47465058 | 10365 | unsigned int j; |
79d72f45 | 10366 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 10367 | |
e4e00185 | 10368 | if (avoid_fence |
389d00a5 JB |
10369 | && (i.tm.base_opcode == 0xaee8 |
10370 | || i.tm.base_opcode == 0xaef0 | |
10371 | || i.tm.base_opcode == 0xaef8)) | |
48ef937e JB |
10372 | { |
10373 | /* Encode lfence, mfence, and sfence as | |
10374 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
47f4115a | 10375 | if (flag_code == CODE_16BIT) |
76d3f746 | 10376 | as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i.tm)); |
47f4115a JB |
10377 | else if (omit_lock_prefix) |
10378 | as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"), | |
76d3f746 | 10379 | insn_name (&i.tm)); |
47f4115a | 10380 | else if (now_seg != absolute_section) |
48ef937e JB |
10381 | { |
10382 | offsetT val = 0x240483f0ULL; | |
10383 | ||
10384 | p = frag_more (5); | |
10385 | md_number_to_chars (p, val, 5); | |
10386 | } | |
10387 | else | |
10388 | abs_section_offset += 5; | |
10389 | return; | |
10390 | } | |
e4e00185 | 10391 | |
d022bddd IT |
10392 | /* Some processors fail on LOCK prefix. This options makes |
10393 | assembler ignore LOCK prefix and serves as a workaround. */ | |
10394 | if (omit_lock_prefix) | |
10395 | { | |
35648716 JB |
10396 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE |
10397 | && i.tm.opcode_modifier.isprefix) | |
d022bddd IT |
10398 | return; |
10399 | i.prefix[LOCK_PREFIX] = 0; | |
10400 | } | |
10401 | ||
e379e5f3 L |
10402 | if (branch) |
10403 | /* Skip if this is a branch. */ | |
10404 | ; | |
b5482fe5 | 10405 | else if (add_fused_jcc_padding_frag_p (&mf_cmp, last_insn)) |
e379e5f3 L |
10406 | { |
10407 | /* Make room for padding. */ | |
10408 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
10409 | p = frag_more (0); | |
10410 | ||
10411 | fragP = frag_now; | |
10412 | ||
10413 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
10414 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
10415 | NULL, 0, p); | |
10416 | ||
79d72f45 | 10417 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
10418 | fragP->tc_frag_data.branch_type = align_branch_fused; |
10419 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
10420 | } | |
b5482fe5 | 10421 | else if (add_branch_prefix_frag_p (last_insn)) |
e379e5f3 L |
10422 | { |
10423 | unsigned int max_prefix_size = align_branch_prefix_size; | |
10424 | ||
10425 | /* Make room for padding. */ | |
10426 | frag_grow (max_prefix_size); | |
10427 | p = frag_more (0); | |
10428 | ||
10429 | fragP = frag_now; | |
10430 | ||
10431 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
10432 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
10433 | NULL, 0, p); | |
10434 | ||
10435 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
10436 | } | |
10437 | ||
43234a1e L |
10438 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
10439 | don't need the explicit prefix. */ | |
cf665fee | 10440 | if (!is_any_vex_encoding (&i.tm)) |
bc4bd9ab | 10441 | { |
7b47a312 | 10442 | switch (i.tm.opcode_modifier.opcodeprefix) |
bc4bd9ab | 10443 | { |
7b47a312 L |
10444 | case PREFIX_0X66: |
10445 | add_prefix (0x66); | |
10446 | break; | |
10447 | case PREFIX_0XF2: | |
10448 | add_prefix (0xf2); | |
10449 | break; | |
10450 | case PREFIX_0XF3: | |
734dfd1c | 10451 | if (!is_cpu (&i.tm, CpuPadLock) |
8b65b895 L |
10452 | || (i.prefix[REP_PREFIX] != 0xf3)) |
10453 | add_prefix (0xf3); | |
c0f3af97 | 10454 | break; |
7b47a312 | 10455 | case PREFIX_NONE: |
9a182d04 | 10456 | switch (i.opcode_length) |
c0f3af97 | 10457 | { |
7b47a312 | 10458 | case 2: |
7b47a312 | 10459 | break; |
9a182d04 | 10460 | case 1: |
7b47a312 | 10461 | /* Check for pseudo prefixes. */ |
9a182d04 JB |
10462 | if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode) |
10463 | break; | |
7b47a312 L |
10464 | as_bad_where (insn_start_frag->fr_file, |
10465 | insn_start_frag->fr_line, | |
10466 | _("pseudo prefix without instruction")); | |
10467 | return; | |
10468 | default: | |
10469 | abort (); | |
4dffcebc | 10470 | } |
c0f3af97 | 10471 | break; |
c0f3af97 L |
10472 | default: |
10473 | abort (); | |
bc4bd9ab | 10474 | } |
c0f3af97 | 10475 | |
6d19a37a | 10476 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
10477 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
10478 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
10479 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
10480 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
10481 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 | 10482 | if (x86_elf_abi == X86_64_X32_ABI |
a533c8df | 10483 | && !is_apx_rex2_encoding () |
cf61b747 | 10484 | && i.operands == 2 |
14470f07 L |
10485 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
10486 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
10487 | && i.prefix[REX_PREFIX] == 0) |
10488 | add_prefix (REX_OPCODE); | |
6d19a37a | 10489 | #endif |
cf61b747 | 10490 | |
c0f3af97 L |
10491 | /* The prefix bytes. */ |
10492 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
10493 | if (*q) | |
48ef937e | 10494 | frag_opcode_byte (*q); |
80d61d8d CL |
10495 | |
10496 | if (is_apx_rex2_encoding ()) | |
10497 | { | |
10498 | frag_opcode_byte (i.vex.bytes[0]); | |
10499 | frag_opcode_byte (i.vex.bytes[1]); | |
10500 | } | |
0f10071e | 10501 | } |
ae5c1c7b | 10502 | else |
c0f3af97 L |
10503 | { |
10504 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
10505 | if (*q) | |
10506 | switch (j) | |
10507 | { | |
c0f3af97 L |
10508 | case SEG_PREFIX: |
10509 | case ADDR_PREFIX: | |
48ef937e | 10510 | frag_opcode_byte (*q); |
c0f3af97 L |
10511 | break; |
10512 | default: | |
10513 | /* There should be no other prefixes for instructions | |
10514 | with VEX prefix. */ | |
10515 | abort (); | |
10516 | } | |
10517 | ||
43234a1e L |
10518 | /* For EVEX instructions i.vrex should become 0 after |
10519 | build_evex_prefix. For VEX instructions upper 16 registers | |
10520 | aren't available, so VREX should be 0. */ | |
10521 | if (i.vrex) | |
10522 | abort (); | |
c0f3af97 | 10523 | /* Now the VEX prefix. */ |
48ef937e JB |
10524 | if (now_seg != absolute_section) |
10525 | { | |
10526 | p = frag_more (i.vex.length); | |
10527 | for (j = 0; j < i.vex.length; j++) | |
10528 | p[j] = i.vex.bytes[j]; | |
10529 | } | |
10530 | else | |
10531 | abs_section_offset += i.vex.length; | |
c0f3af97 | 10532 | } |
252b5132 | 10533 | |
29b0f896 | 10534 | /* Now the opcode; be careful about word order here! */ |
389d00a5 JB |
10535 | j = i.opcode_length; |
10536 | if (!i.vex.length) | |
ddb62495 | 10537 | switch (i.tm.opcode_space) |
389d00a5 JB |
10538 | { |
10539 | case SPACE_BASE: | |
10540 | break; | |
10541 | case SPACE_0F: | |
10542 | ++j; | |
10543 | break; | |
10544 | case SPACE_0F38: | |
10545 | case SPACE_0F3A: | |
10546 | j += 2; | |
10547 | break; | |
10548 | default: | |
10549 | abort (); | |
10550 | } | |
10551 | ||
48ef937e | 10552 | if (now_seg == absolute_section) |
389d00a5 JB |
10553 | abs_section_offset += j; |
10554 | else if (j == 1) | |
29b0f896 AM |
10555 | { |
10556 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
10557 | } | |
10558 | else | |
10559 | { | |
389d00a5 JB |
10560 | p = frag_more (j); |
10561 | if (!i.vex.length | |
ddb62495 | 10562 | && i.tm.opcode_space != SPACE_BASE) |
389d00a5 JB |
10563 | { |
10564 | *p++ = 0x0f; | |
ddb62495 JB |
10565 | if (i.tm.opcode_space != SPACE_0F) |
10566 | *p++ = i.tm.opcode_space == SPACE_0F38 | |
389d00a5 JB |
10567 | ? 0x38 : 0x3a; |
10568 | } | |
10569 | ||
9a182d04 | 10570 | switch (i.opcode_length) |
331d2d0d | 10571 | { |
4dffcebc | 10572 | case 2: |
389d00a5 JB |
10573 | /* Put out high byte first: can't use md_number_to_chars! */ |
10574 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
10575 | /* Fall through. */ | |
10576 | case 1: | |
10577 | *p = i.tm.base_opcode & 0xff; | |
4dffcebc L |
10578 | break; |
10579 | default: | |
10580 | abort (); | |
10581 | break; | |
331d2d0d | 10582 | } |
0f10071e | 10583 | |
29b0f896 | 10584 | } |
3e73aa7c | 10585 | |
29b0f896 | 10586 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 10587 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 10588 | { |
48ef937e JB |
10589 | frag_opcode_byte ((i.rm.regmem << 0) |
10590 | | (i.rm.reg << 3) | |
10591 | | (i.rm.mode << 6)); | |
29b0f896 AM |
10592 | /* If i.rm.regmem == ESP (4) |
10593 | && i.rm.mode != (Register mode) | |
10594 | && not 16 bit | |
10595 | ==> need second modrm byte. */ | |
10596 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
10597 | && i.rm.mode != 3 | |
dc821c5f | 10598 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
10599 | frag_opcode_byte ((i.sib.base << 0) |
10600 | | (i.sib.index << 3) | |
10601 | | (i.sib.scale << 6)); | |
29b0f896 | 10602 | } |
3e73aa7c | 10603 | |
29b0f896 | 10604 | if (i.disp_operands) |
2bbd9c25 | 10605 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 10606 | |
29b0f896 | 10607 | if (i.imm_operands) |
2bbd9c25 | 10608 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
10609 | |
10610 | /* | |
10611 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
10612 | * absolute section, and abs_section_offset not getting updated as data | |
10613 | * gets added to the frag breaks the logic below. | |
10614 | */ | |
10615 | if (now_seg != absolute_section) | |
10616 | { | |
10617 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
10618 | if (j > 15) | |
10619 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
10620 | j); | |
e379e5f3 L |
10621 | else if (fragP) |
10622 | { | |
10623 | /* NB: Don't add prefix with GOTPC relocation since | |
10624 | output_disp() above depends on the fixed encoding | |
10625 | length. Can't add prefix with TLS relocation since | |
10626 | it breaks TLS linker optimization. */ | |
10627 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
10628 | /* Prefix count on the current instruction. */ | |
10629 | unsigned int count = i.vex.length; | |
10630 | unsigned int k; | |
10631 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
10632 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
10633 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
10634 | count++; | |
10635 | ||
10636 | /* Count prefixes for extended opcode maps. */ | |
10637 | if (!i.vex.length) | |
ddb62495 | 10638 | switch (i.tm.opcode_space) |
e379e5f3 | 10639 | { |
389d00a5 | 10640 | case SPACE_BASE: |
e379e5f3 | 10641 | break; |
389d00a5 JB |
10642 | case SPACE_0F: |
10643 | count++; | |
e379e5f3 | 10644 | break; |
389d00a5 JB |
10645 | case SPACE_0F38: |
10646 | case SPACE_0F3A: | |
10647 | count += 2; | |
e379e5f3 L |
10648 | break; |
10649 | default: | |
10650 | abort (); | |
10651 | } | |
10652 | ||
10653 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
10654 | == BRANCH_PREFIX) | |
10655 | { | |
10656 | /* Set the maximum prefix size in BRANCH_PREFIX | |
10657 | frag. */ | |
10658 | if (fragP->tc_frag_data.max_bytes > max) | |
10659 | fragP->tc_frag_data.max_bytes = max; | |
10660 | if (fragP->tc_frag_data.max_bytes > count) | |
10661 | fragP->tc_frag_data.max_bytes -= count; | |
10662 | else | |
10663 | fragP->tc_frag_data.max_bytes = 0; | |
10664 | } | |
10665 | else | |
10666 | { | |
10667 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
10668 | frag. */ | |
10669 | unsigned int max_prefix_size; | |
10670 | if (align_branch_prefix_size > max) | |
10671 | max_prefix_size = max; | |
10672 | else | |
10673 | max_prefix_size = align_branch_prefix_size; | |
10674 | if (max_prefix_size > count) | |
10675 | fragP->tc_frag_data.max_prefix_length | |
10676 | = max_prefix_size - count; | |
10677 | } | |
10678 | ||
10679 | /* Use existing segment prefix if possible. Use CS | |
10680 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
10681 | segment prefix with ESP/EBP base register and use DS | |
10682 | segment prefix without ESP/EBP base register. */ | |
10683 | if (i.prefix[SEG_PREFIX]) | |
10684 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
10685 | else if (flag_code == CODE_64BIT) | |
10686 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
10687 | else if (i.base_reg | |
10688 | && (i.base_reg->reg_num == 4 | |
10689 | || i.base_reg->reg_num == 5)) | |
10690 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
10691 | else | |
10692 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
10693 | } | |
9c33702b | 10694 | } |
29b0f896 | 10695 | } |
252b5132 | 10696 | |
e379e5f3 L |
10697 | /* NB: Don't work with COND_JUMP86 without i386. */ |
10698 | if (align_branch_power | |
10699 | && now_seg != absolute_section | |
10700 | && cpu_arch_flags.bitfield.cpui386) | |
10701 | { | |
10702 | /* Terminate each frag so that we can add prefix and check for | |
10703 | fused jcc. */ | |
10704 | frag_wane (frag_now); | |
10705 | frag_new (0); | |
10706 | } | |
10707 | ||
29b0f896 AM |
10708 | #ifdef DEBUG386 |
10709 | if (flag_debug) | |
10710 | { | |
7b81dfbb | 10711 | pi ("" /*line*/, &i); |
29b0f896 AM |
10712 | } |
10713 | #endif /* DEBUG386 */ | |
10714 | } | |
252b5132 | 10715 | |
e205caa7 L |
10716 | /* Return the size of the displacement operand N. */ |
10717 | ||
10718 | static int | |
10719 | disp_size (unsigned int n) | |
10720 | { | |
10721 | int size = 4; | |
43234a1e | 10722 | |
b5014f7a | 10723 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
10724 | size = 8; |
10725 | else if (i.types[n].bitfield.disp8) | |
10726 | size = 1; | |
10727 | else if (i.types[n].bitfield.disp16) | |
10728 | size = 2; | |
e205caa7 L |
10729 | return size; |
10730 | } | |
10731 | ||
10732 | /* Return the size of the immediate operand N. */ | |
10733 | ||
10734 | static int | |
10735 | imm_size (unsigned int n) | |
10736 | { | |
10737 | int size = 4; | |
40fb9820 L |
10738 | if (i.types[n].bitfield.imm64) |
10739 | size = 8; | |
10740 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
10741 | size = 1; | |
10742 | else if (i.types[n].bitfield.imm16) | |
10743 | size = 2; | |
e205caa7 L |
10744 | return size; |
10745 | } | |
10746 | ||
29b0f896 | 10747 | static void |
64e74474 | 10748 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10749 | { |
10750 | char *p; | |
10751 | unsigned int n; | |
252b5132 | 10752 | |
29b0f896 AM |
10753 | for (n = 0; n < i.operands; n++) |
10754 | { | |
b5014f7a | 10755 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 10756 | { |
48ef937e JB |
10757 | int size = disp_size (n); |
10758 | ||
10759 | if (now_seg == absolute_section) | |
10760 | abs_section_offset += size; | |
10761 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 10762 | { |
43234a1e | 10763 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 10764 | |
629cfaf1 JB |
10765 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
10766 | size); | |
29b0f896 AM |
10767 | p = frag_more (size); |
10768 | md_number_to_chars (p, val, size); | |
10769 | } | |
10770 | else | |
10771 | { | |
f86103b7 | 10772 | enum bfd_reloc_code_real reloc_type; |
a775efc8 JB |
10773 | bool pcrel = (i.flags[n] & Operand_PCrel) != 0; |
10774 | bool sign = (flag_code == CODE_64BIT && size == 4 | |
10775 | && (!want_disp32 (&i.tm) | |
10776 | || (i.tm.opcode_modifier.jump && !i.jumpabsolute | |
10777 | && !i.types[n].bitfield.baseindex))) | |
10778 | || pcrel; | |
02a86693 | 10779 | fixS *fixP; |
29b0f896 | 10780 | |
e205caa7 | 10781 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 10782 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 10783 | |
29b0f896 AM |
10784 | /* The PC relative address is computed relative |
10785 | to the instruction boundary, so in case immediate | |
10786 | fields follows, we need to adjust the value. */ | |
10787 | if (pcrel && i.imm_operands) | |
10788 | { | |
29b0f896 | 10789 | unsigned int n1; |
e205caa7 | 10790 | int sz = 0; |
252b5132 | 10791 | |
29b0f896 | 10792 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 10793 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 10794 | { |
e205caa7 | 10795 | /* Only one immediate is allowed for PC |
e3bf0aad JB |
10796 | relative address, except with .insn. */ |
10797 | gas_assert (sz == 0 || dot_insn ()); | |
10798 | sz += imm_size (n1); | |
252b5132 | 10799 | } |
e3bf0aad | 10800 | /* We should find at least one immediate. */ |
9c2799c2 | 10801 | gas_assert (sz != 0); |
e3bf0aad | 10802 | i.op[n].disps->X_add_number -= sz; |
29b0f896 | 10803 | } |
520dc8e8 | 10804 | |
29b0f896 | 10805 | p = frag_more (size); |
d258b828 | 10806 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 10807 | if (GOT_symbol |
2bbd9c25 | 10808 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 10809 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10810 | || reloc_type == BFD_RELOC_X86_64_32S |
10811 | || (reloc_type == BFD_RELOC_64 | |
10812 | && object_64bit)) | |
d6ab8113 JB |
10813 | && (i.op[n].disps->X_op == O_symbol |
10814 | || (i.op[n].disps->X_op == O_add | |
10815 | && ((symbol_get_value_expression | |
10816 | (i.op[n].disps->X_op_symbol)->X_op) | |
10817 | == O_subtract)))) | |
10818 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 10819 | { |
4fa24527 | 10820 | if (!object_64bit) |
7b81dfbb AJ |
10821 | { |
10822 | reloc_type = BFD_RELOC_386_GOTPC; | |
5b7c81bd | 10823 | i.has_gotpc_tls_reloc = true; |
98da05bf | 10824 | i.op[n].disps->X_add_number += |
d583596c | 10825 | encoding_length (insn_start_frag, insn_start_off, p); |
7b81dfbb AJ |
10826 | } |
10827 | else if (reloc_type == BFD_RELOC_64) | |
10828 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 10829 | else |
7b81dfbb AJ |
10830 | /* Don't do the adjustment for x86-64, as there |
10831 | the pcrel addressing is relative to the _next_ | |
10832 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 10833 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 10834 | } |
e379e5f3 L |
10835 | else if (align_branch_power) |
10836 | { | |
10837 | switch (reloc_type) | |
10838 | { | |
10839 | case BFD_RELOC_386_TLS_GD: | |
10840 | case BFD_RELOC_386_TLS_LDM: | |
10841 | case BFD_RELOC_386_TLS_IE: | |
10842 | case BFD_RELOC_386_TLS_IE_32: | |
10843 | case BFD_RELOC_386_TLS_GOTIE: | |
10844 | case BFD_RELOC_386_TLS_GOTDESC: | |
10845 | case BFD_RELOC_386_TLS_DESC_CALL: | |
10846 | case BFD_RELOC_X86_64_TLSGD: | |
10847 | case BFD_RELOC_X86_64_TLSLD: | |
10848 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 10849 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
e379e5f3 | 10850 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 10851 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
e379e5f3 | 10852 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
5b7c81bd | 10853 | i.has_gotpc_tls_reloc = true; |
e379e5f3 L |
10854 | default: |
10855 | break; | |
10856 | } | |
10857 | } | |
02a86693 L |
10858 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
10859 | size, i.op[n].disps, pcrel, | |
10860 | reloc_type); | |
eb19308f JB |
10861 | |
10862 | if (flag_code == CODE_64BIT && size == 4 && pcrel | |
10863 | && !i.prefix[ADDR_PREFIX]) | |
10864 | fixP->fx_signed = 1; | |
10865 | ||
3d5a60de L |
10866 | /* Set fx_tcbit3 for REX2 prefix. */ |
10867 | if (is_apx_rex2_encoding ()) | |
10868 | fixP->fx_tcbit3 = 1; | |
10869 | ||
02a86693 L |
10870 | /* Check for "call/jmp *mem", "mov mem, %reg", |
10871 | "test %reg, mem" and "binop mem, %reg" where binop | |
10872 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
10873 | instructions without data prefix. Always generate |
10874 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
10875 | if (i.prefix[DATA_PREFIX] == 0 | |
10876 | && (generate_relax_relocations | |
10877 | || (!object_64bit | |
10878 | && i.rm.mode == 0 | |
10879 | && i.rm.regmem == 5)) | |
0cb4071e L |
10880 | && (i.rm.mode == 2 |
10881 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
ddb62495 | 10882 | && i.tm.opcode_space == SPACE_BASE |
02a86693 L |
10883 | && ((i.operands == 1 |
10884 | && i.tm.base_opcode == 0xff | |
10885 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
10886 | || (i.operands == 2 | |
10887 | && (i.tm.base_opcode == 0x8b | |
10888 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 10889 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
10890 | { |
10891 | if (object_64bit) | |
10892 | { | |
10893 | fixP->fx_tcbit = i.rex != 0; | |
10894 | if (i.base_reg | |
e968fc9b | 10895 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
10896 | fixP->fx_tcbit2 = 1; |
10897 | } | |
10898 | else | |
10899 | fixP->fx_tcbit2 = 1; | |
10900 | } | |
29b0f896 AM |
10901 | } |
10902 | } | |
10903 | } | |
10904 | } | |
252b5132 | 10905 | |
29b0f896 | 10906 | static void |
64e74474 | 10907 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10908 | { |
10909 | char *p; | |
10910 | unsigned int n; | |
252b5132 | 10911 | |
29b0f896 AM |
10912 | for (n = 0; n < i.operands; n++) |
10913 | { | |
40fb9820 | 10914 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 10915 | { |
48ef937e JB |
10916 | int size = imm_size (n); |
10917 | ||
10918 | if (now_seg == absolute_section) | |
10919 | abs_section_offset += size; | |
10920 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 10921 | { |
29b0f896 | 10922 | offsetT val; |
b4cac588 | 10923 | |
29b0f896 AM |
10924 | val = offset_in_range (i.op[n].imms->X_add_number, |
10925 | size); | |
10926 | p = frag_more (size); | |
10927 | md_number_to_chars (p, val, size); | |
10928 | } | |
10929 | else | |
10930 | { | |
10931 | /* Not absolute_section. | |
10932 | Need a 32-bit fixup (don't support 8bit | |
10933 | non-absolute imms). Try to support other | |
10934 | sizes ... */ | |
f86103b7 | 10935 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 10936 | int sign; |
29b0f896 | 10937 | |
40fb9820 | 10938 | if (i.types[n].bitfield.imm32s |
a7d61044 | 10939 | && (i.suffix == QWORD_MNEM_SUFFIX |
c032bc4f | 10940 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf) |
f79d55e1 | 10941 | || (i.prefix[REX_PREFIX] & REX_W) |
c032bc4f | 10942 | || dot_insn ())) |
29b0f896 | 10943 | sign = 1; |
e205caa7 L |
10944 | else |
10945 | sign = 0; | |
520dc8e8 | 10946 | |
29b0f896 | 10947 | p = frag_more (size); |
d258b828 | 10948 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 10949 | |
2bbd9c25 JJ |
10950 | /* This is tough to explain. We end up with this one if we |
10951 | * have operands that look like | |
10952 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
10953 | * obtain the absolute address of the GOT, and it is strongly | |
10954 | * preferable from a performance point of view to avoid using | |
10955 | * a runtime relocation for this. The actual sequence of | |
10956 | * instructions often look something like: | |
10957 | * | |
10958 | * call .L66 | |
10959 | * .L66: | |
10960 | * popl %ebx | |
10961 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
10962 | * | |
10963 | * The call and pop essentially return the absolute address | |
10964 | * of the label .L66 and store it in %ebx. The linker itself | |
10965 | * will ultimately change the first operand of the addl so | |
10966 | * that %ebx points to the GOT, but to keep things simple, the | |
10967 | * .o file must have this operand set so that it generates not | |
10968 | * the absolute address of .L66, but the absolute address of | |
10969 | * itself. This allows the linker itself simply treat a GOTPC | |
10970 | * relocation as asking for a pcrel offset to the GOT to be | |
10971 | * added in, and the addend of the relocation is stored in the | |
10972 | * operand field for the instruction itself. | |
10973 | * | |
10974 | * Our job here is to fix the operand so that it would add | |
10975 | * the correct offset so that %ebx would point to itself. The | |
10976 | * thing that is tricky is that .-.L66 will point to the | |
10977 | * beginning of the instruction, so we need to further modify | |
10978 | * the operand so that it will point to itself. There are | |
10979 | * other cases where you have something like: | |
10980 | * | |
10981 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
10982 | * | |
10983 | * and here no correction would be required. Internally in | |
10984 | * the assembler we treat operands of this form as not being | |
10985 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
10986 | * whether it would simplify matters to do it this way. Who | |
10987 | * knows. In earlier versions of the PIC patches, the | |
10988 | * pcrel_adjust field was used to store the correction, but | |
10989 | * since the expression is not pcrel, I felt it would be | |
10990 | * confusing to do it this way. */ | |
10991 | ||
d6ab8113 | 10992 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10993 | || reloc_type == BFD_RELOC_X86_64_32S |
10994 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
10995 | && GOT_symbol |
10996 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
10997 | && (i.op[n].imms->X_op == O_symbol | |
10998 | || (i.op[n].imms->X_op == O_add | |
10999 | && ((symbol_get_value_expression | |
11000 | (i.op[n].imms->X_op_symbol)->X_op) | |
11001 | == O_subtract)))) | |
11002 | { | |
4fa24527 | 11003 | if (!object_64bit) |
d6ab8113 | 11004 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 11005 | else if (size == 4) |
d6ab8113 | 11006 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
11007 | else if (size == 8) |
11008 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
5b7c81bd | 11009 | i.has_gotpc_tls_reloc = true; |
d583596c JB |
11010 | i.op[n].imms->X_add_number += |
11011 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 11012 | } |
29b0f896 AM |
11013 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
11014 | i.op[n].imms, 0, reloc_type); | |
11015 | } | |
11016 | } | |
11017 | } | |
252b5132 RH |
11018 | } |
11019 | \f | |
d182319b JB |
11020 | /* x86_cons_fix_new is called via the expression parsing code when a |
11021 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
11022 | static int cons_sign = -1; |
11023 | ||
11024 | void | |
e3bb37b5 | 11025 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 11026 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 11027 | { |
d258b828 | 11028 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
11029 | |
11030 | #ifdef TE_PE | |
11031 | if (exp->X_op == O_secrel) | |
11032 | { | |
11033 | exp->X_op = O_symbol; | |
11034 | r = BFD_RELOC_32_SECREL; | |
11035 | } | |
145667f8 MH |
11036 | else if (exp->X_op == O_secidx) |
11037 | r = BFD_RELOC_16_SECIDX; | |
d182319b JB |
11038 | #endif |
11039 | ||
11040 | fix_new_exp (frag, off, len, exp, 0, r); | |
11041 | } | |
11042 | ||
357d1bd8 L |
11043 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
11044 | purpose of the `.dc.a' internal pseudo-op. */ | |
11045 | ||
11046 | int | |
11047 | x86_address_bytes (void) | |
11048 | { | |
11049 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
11050 | return 4; | |
11051 | return stdoutput->arch_info->bits_per_address / 8; | |
11052 | } | |
11053 | ||
deea4973 JB |
11054 | #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
11055 | || defined (LEX_AT)) && !defined (TE_PE) | |
d258b828 | 11056 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 11057 | #else |
f3c180ae AM |
11058 | /* Parse operands of the form |
11059 | <symbol>@GOTOFF+<nnn> | |
11060 | and similar .plt or .got references. | |
11061 | ||
11062 | If we find one, set up the correct relocation in RELOC and copy the | |
11063 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
11064 | parsing by the calling routine. Return this buffer, and if ADJUST | |
11065 | is non-null set it to the length of the string we removed from the | |
11066 | input line. Otherwise return NULL. */ | |
11067 | static char * | |
91d6fa6a | 11068 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 11069 | int *adjust, |
d258b828 | 11070 | i386_operand_type *types) |
f3c180ae | 11071 | { |
7b81dfbb AJ |
11072 | /* Some of the relocations depend on the size of what field is to |
11073 | be relocated. But in our callers i386_immediate and i386_displacement | |
11074 | we don't yet know the operand size (this will be set by insn | |
11075 | matching). Hence we record the word32 relocation here, | |
11076 | and adjust the reloc according to the real size in reloc(). */ | |
145667f8 MH |
11077 | static const struct |
11078 | { | |
f3c180ae | 11079 | const char *str; |
cff8d58a | 11080 | int len; |
4fa24527 | 11081 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 11082 | const i386_operand_type types64; |
5b7c81bd | 11083 | bool need_GOT_symbol; |
145667f8 MH |
11084 | } |
11085 | gotrel[] = | |
11086 | { | |
05909f23 JB |
11087 | |
11088 | #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \ | |
11089 | { .imm32 = 1, .imm32s = 1, .disp32 = 1 } } | |
11090 | #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \ | |
11091 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } } | |
11092 | #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \ | |
11093 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } } | |
11094 | #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \ | |
11095 | { .imm64 = 1, .disp64 = 1 } } | |
11096 | ||
deea4973 | 11097 | #ifndef TE_PE |
8ce3d284 | 11098 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
11099 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
11100 | BFD_RELOC_SIZE32 }, | |
05909f23 | 11101 | { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false }, |
8ce3d284 | 11102 | #endif |
cff8d58a L |
11103 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
11104 | BFD_RELOC_X86_64_PLTOFF64 }, | |
05909f23 | 11105 | { .bitfield = { .imm64 = 1 } }, true }, |
cff8d58a L |
11106 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
11107 | BFD_RELOC_X86_64_PLT32 }, | |
a775efc8 | 11108 | OPERAND_TYPE_IMM32_32S_DISP32, false }, |
cff8d58a L |
11109 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
11110 | BFD_RELOC_X86_64_GOTPLT64 }, | |
5b7c81bd | 11111 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
11112 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
11113 | BFD_RELOC_X86_64_GOTOFF64 }, | |
5b7c81bd | 11114 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
11115 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
11116 | BFD_RELOC_X86_64_GOTPCREL }, | |
a775efc8 | 11117 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
11118 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
11119 | BFD_RELOC_X86_64_TLSGD }, | |
a775efc8 | 11120 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
11121 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
11122 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 11123 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
11124 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
11125 | BFD_RELOC_X86_64_TLSLD }, | |
a775efc8 | 11126 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
11127 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
11128 | BFD_RELOC_X86_64_GOTTPOFF }, | |
a775efc8 | 11129 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
11130 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
11131 | BFD_RELOC_X86_64_TPOFF32 }, | |
a775efc8 | 11132 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
11133 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
11134 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 11135 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
11136 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
11137 | BFD_RELOC_X86_64_DTPOFF32 }, | |
a775efc8 | 11138 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
11139 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
11140 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 11141 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
11142 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
11143 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 11144 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
11145 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
11146 | BFD_RELOC_X86_64_GOT32 }, | |
a775efc8 | 11147 | OPERAND_TYPE_IMM32_32S_64_DISP32, true }, |
cff8d58a L |
11148 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
11149 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
a775efc8 | 11150 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
11151 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
11152 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
a775efc8 | 11153 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
deea4973 JB |
11154 | #else /* TE_PE */ |
11155 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
11156 | BFD_RELOC_32_SECREL }, | |
a775efc8 | 11157 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, false }, |
deea4973 | 11158 | #endif |
05909f23 JB |
11159 | |
11160 | #undef OPERAND_TYPE_IMM32_32S_DISP32 | |
11161 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32 | |
11162 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64 | |
11163 | #undef OPERAND_TYPE_IMM64_DISP64 | |
11164 | ||
f3c180ae AM |
11165 | }; |
11166 | char *cp; | |
11167 | unsigned int j; | |
11168 | ||
deea4973 | 11169 | #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE) |
718ddfc0 JB |
11170 | if (!IS_ELF) |
11171 | return NULL; | |
d382c579 | 11172 | #endif |
718ddfc0 | 11173 | |
f3c180ae | 11174 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 11175 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
11176 | return NULL; |
11177 | ||
47465058 | 11178 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 11179 | { |
cff8d58a | 11180 | int len = gotrel[j].len; |
28f81592 | 11181 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 11182 | { |
4fa24527 | 11183 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 11184 | { |
28f81592 AM |
11185 | int first, second; |
11186 | char *tmpbuf, *past_reloc; | |
f3c180ae | 11187 | |
91d6fa6a | 11188 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 11189 | |
3956db08 JB |
11190 | if (types) |
11191 | { | |
11192 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
11193 | { |
11194 | types->bitfield.imm32 = 1; | |
11195 | types->bitfield.disp32 = 1; | |
11196 | } | |
3956db08 JB |
11197 | else |
11198 | *types = gotrel[j].types64; | |
11199 | } | |
11200 | ||
844bf810 | 11201 | if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL) |
f3c180ae AM |
11202 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
11203 | ||
28f81592 | 11204 | /* The length of the first part of our input line. */ |
f3c180ae | 11205 | first = cp - input_line_pointer; |
28f81592 AM |
11206 | |
11207 | /* The second part goes from after the reloc token until | |
67c11a9b | 11208 | (and including) an end_of_line char or comma. */ |
28f81592 | 11209 | past_reloc = cp + 1 + len; |
67c11a9b AM |
11210 | cp = past_reloc; |
11211 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
11212 | ++cp; | |
11213 | second = cp + 1 - past_reloc; | |
28f81592 AM |
11214 | |
11215 | /* Allocate and copy string. The trailing NUL shouldn't | |
11216 | be necessary, but be safe. */ | |
add39d23 | 11217 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 11218 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
11219 | if (second != 0 && *past_reloc != ' ') |
11220 | /* Replace the relocation token with ' ', so that | |
11221 | errors like foo@GOTOFF1 will be detected. */ | |
11222 | tmpbuf[first++] = ' '; | |
af89796a L |
11223 | else |
11224 | /* Increment length by 1 if the relocation token is | |
11225 | removed. */ | |
11226 | len++; | |
11227 | if (adjust) | |
11228 | *adjust = len; | |
0787a12d AM |
11229 | memcpy (tmpbuf + first, past_reloc, second); |
11230 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
11231 | return tmpbuf; |
11232 | } | |
11233 | ||
4fa24527 JB |
11234 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
11235 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
11236 | return NULL; |
11237 | } | |
11238 | } | |
11239 | ||
11240 | /* Might be a symbol version string. Don't as_bad here. */ | |
11241 | return NULL; | |
11242 | } | |
4e4f7c87 | 11243 | #endif |
f3c180ae | 11244 | |
62ebcb5c | 11245 | bfd_reloc_code_real_type |
e3bb37b5 | 11246 | x86_cons (expressionS *exp, int size) |
f3c180ae | 11247 | { |
62ebcb5c AM |
11248 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
11249 | ||
6b50f5f4 JB |
11250 | intel_syntax = -intel_syntax; |
11251 | exp->X_md = 0; | |
5cc00775 | 11252 | expr_mode = expr_operator_none; |
6b50f5f4 | 11253 | |
2748c1b1 L |
11254 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
11255 | && !defined (LEX_AT)) \ | |
11256 | || defined (TE_PE) | |
4fa24527 | 11257 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
11258 | { |
11259 | /* Handle @GOTOFF and the like in an expression. */ | |
11260 | char *save; | |
11261 | char *gotfree_input_line; | |
4a57f2cf | 11262 | int adjust = 0; |
f3c180ae AM |
11263 | |
11264 | save = input_line_pointer; | |
d258b828 | 11265 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
11266 | if (gotfree_input_line) |
11267 | input_line_pointer = gotfree_input_line; | |
11268 | ||
11269 | expression (exp); | |
11270 | ||
11271 | if (gotfree_input_line) | |
11272 | { | |
11273 | /* expression () has merrily parsed up to the end of line, | |
11274 | or a comma - in the wrong buffer. Transfer how far | |
11275 | input_line_pointer has moved to the right buffer. */ | |
11276 | input_line_pointer = (save | |
11277 | + (input_line_pointer - gotfree_input_line) | |
11278 | + adjust); | |
11279 | free (gotfree_input_line); | |
3992d3b7 AM |
11280 | if (exp->X_op == O_constant |
11281 | || exp->X_op == O_absent | |
11282 | || exp->X_op == O_illegal | |
0398aac5 | 11283 | || exp->X_op == O_register |
3992d3b7 AM |
11284 | || exp->X_op == O_big) |
11285 | { | |
11286 | char c = *input_line_pointer; | |
11287 | *input_line_pointer = 0; | |
11288 | as_bad (_("missing or invalid expression `%s'"), save); | |
11289 | *input_line_pointer = c; | |
11290 | } | |
b9519cfe L |
11291 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
11292 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
11293 | && exp->X_op != O_symbol) | |
11294 | { | |
11295 | char c = *input_line_pointer; | |
11296 | *input_line_pointer = 0; | |
11297 | as_bad (_("invalid PLT expression `%s'"), save); | |
11298 | *input_line_pointer = c; | |
11299 | } | |
f3c180ae AM |
11300 | } |
11301 | } | |
11302 | else | |
6b50f5f4 | 11303 | #endif |
f3c180ae | 11304 | expression (exp); |
ee86248c JB |
11305 | |
11306 | intel_syntax = -intel_syntax; | |
11307 | ||
11308 | if (intel_syntax) | |
11309 | i386_intel_simplify (exp); | |
62ebcb5c | 11310 | |
a442cac5 | 11311 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ |
5cc00775 JB |
11312 | if (size <= 4 && expr_mode == expr_operator_present |
11313 | && exp->X_op == O_constant && !object_64bit) | |
a442cac5 JB |
11314 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
11315 | ||
62ebcb5c | 11316 | return got_reloc; |
f3c180ae | 11317 | } |
f3c180ae | 11318 | |
9f32dd5b L |
11319 | static void |
11320 | signed_cons (int size) | |
6482c264 | 11321 | { |
a442cac5 | 11322 | if (object_64bit) |
d182319b JB |
11323 | cons_sign = 1; |
11324 | cons (size); | |
11325 | cons_sign = -1; | |
6482c264 NC |
11326 | } |
11327 | ||
edd67638 JB |
11328 | static void |
11329 | s_insn (int dummy ATTRIBUTE_UNUSED) | |
11330 | { | |
393fbe8d | 11331 | char mnemonic[MAX_MNEM_SIZE], *line = input_line_pointer, *ptr; |
edd67638 JB |
11332 | char *saved_ilp = find_end_of_line (line, false), saved_char; |
11333 | const char *end; | |
11334 | unsigned int j; | |
11335 | valueT val; | |
11336 | bool vex = false, xop = false, evex = false; | |
b5482fe5 | 11337 | struct last_insn *last_insn; |
edd67638 JB |
11338 | |
11339 | init_globals (); | |
11340 | ||
11341 | saved_char = *saved_ilp; | |
11342 | *saved_ilp = 0; | |
11343 | ||
11344 | end = parse_insn (line, mnemonic, true); | |
11345 | if (end == NULL) | |
11346 | { | |
11347 | bad: | |
11348 | *saved_ilp = saved_char; | |
11349 | ignore_rest_of_line (); | |
d0c2e3ec | 11350 | i.tm.mnem_off = 0; |
edd67638 JB |
11351 | return; |
11352 | } | |
11353 | line += end - line; | |
11354 | ||
d3b01414 JB |
11355 | current_templates.start = &i.tm; |
11356 | current_templates.end = &i.tm + 1; | |
edd67638 | 11357 | i.tm.mnem_off = MN__insn; |
393fbe8d | 11358 | i.tm.extension_opcode = None; |
edd67638 JB |
11359 | |
11360 | if (startswith (line, "VEX") | |
11361 | && (line[3] == '.' || is_space_char (line[3]))) | |
11362 | { | |
11363 | vex = true; | |
11364 | line += 3; | |
11365 | } | |
11366 | else if (startswith (line, "XOP") && ISDIGIT (line[3])) | |
11367 | { | |
11368 | char *e; | |
11369 | unsigned long n = strtoul (line + 3, &e, 16); | |
11370 | ||
11371 | if (e == line + 5 && n >= 0x08 && n <= 0x1f | |
11372 | && (*e == '.' || is_space_char (*e))) | |
11373 | { | |
11374 | xop = true; | |
d0c2e3ec JB |
11375 | /* Arrange for build_vex_prefix() to emit 0x8f. */ |
11376 | i.tm.opcode_space = SPACE_XOP08; | |
11377 | i.insn_opcode_space = n; | |
edd67638 JB |
11378 | line = e; |
11379 | } | |
11380 | } | |
11381 | else if (startswith (line, "EVEX") | |
11382 | && (line[4] == '.' || is_space_char (line[4]))) | |
11383 | { | |
11384 | evex = true; | |
11385 | line += 4; | |
11386 | } | |
11387 | ||
11388 | if (vex || xop | |
11389 | ? i.vec_encoding == vex_encoding_evex | |
11390 | : evex | |
11391 | ? i.vec_encoding == vex_encoding_vex | |
11392 | || i.vec_encoding == vex_encoding_vex3 | |
11393 | : i.vec_encoding != vex_encoding_default) | |
11394 | { | |
11395 | as_bad (_("pseudo-prefix conflicts with encoding specifier")); | |
11396 | goto bad; | |
11397 | } | |
11398 | ||
0ff3b7d0 JB |
11399 | if (line > end && i.vec_encoding == vex_encoding_default) |
11400 | i.vec_encoding = evex ? vex_encoding_evex : vex_encoding_vex; | |
11401 | ||
1adecddd JB |
11402 | if (i.vec_encoding != vex_encoding_default) |
11403 | { | |
11404 | /* Only address size and segment override prefixes are permitted with | |
11405 | VEX/XOP/EVEX encodings. */ | |
11406 | const unsigned char *p = i.prefix; | |
11407 | ||
11408 | for (j = 0; j < ARRAY_SIZE (i.prefix); ++j, ++p) | |
11409 | { | |
11410 | if (!*p) | |
11411 | continue; | |
11412 | ||
11413 | switch (j) | |
11414 | { | |
11415 | case SEG_PREFIX: | |
11416 | case ADDR_PREFIX: | |
11417 | break; | |
11418 | default: | |
11419 | as_bad (_("illegal prefix used with VEX/XOP/EVEX")); | |
11420 | goto bad; | |
11421 | } | |
11422 | } | |
11423 | } | |
11424 | ||
edd67638 JB |
11425 | if (line > end && *line == '.') |
11426 | { | |
d0c2e3ec JB |
11427 | /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */ |
11428 | switch (line[1]) | |
11429 | { | |
11430 | case 'L': | |
11431 | switch (line[2]) | |
11432 | { | |
11433 | case '0': | |
11434 | if (evex) | |
11435 | i.tm.opcode_modifier.evex = EVEX128; | |
11436 | else | |
11437 | i.tm.opcode_modifier.vex = VEX128; | |
11438 | break; | |
11439 | ||
11440 | case '1': | |
11441 | if (evex) | |
11442 | i.tm.opcode_modifier.evex = EVEX256; | |
11443 | else | |
11444 | i.tm.opcode_modifier.vex = VEX256; | |
11445 | break; | |
11446 | ||
11447 | case '2': | |
11448 | if (evex) | |
11449 | i.tm.opcode_modifier.evex = EVEX512; | |
11450 | break; | |
11451 | ||
11452 | case '3': | |
11453 | if (evex) | |
11454 | i.tm.opcode_modifier.evex = EVEX_L3; | |
11455 | break; | |
11456 | ||
11457 | case 'I': | |
11458 | if (line[3] == 'G') | |
11459 | { | |
11460 | if (evex) | |
11461 | i.tm.opcode_modifier.evex = EVEXLIG; | |
11462 | else | |
11463 | i.tm.opcode_modifier.vex = VEXScalar; /* LIG */ | |
11464 | ++line; | |
11465 | } | |
11466 | break; | |
11467 | } | |
11468 | ||
11469 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) | |
11470 | line += 3; | |
11471 | break; | |
11472 | ||
11473 | case '1': | |
11474 | if (line[2] == '2' && line[3] == '8') | |
11475 | { | |
11476 | if (evex) | |
11477 | i.tm.opcode_modifier.evex = EVEX128; | |
11478 | else | |
11479 | i.tm.opcode_modifier.vex = VEX128; | |
11480 | line += 4; | |
11481 | } | |
11482 | break; | |
11483 | ||
11484 | case '2': | |
11485 | if (line[2] == '5' && line[3] == '6') | |
11486 | { | |
11487 | if (evex) | |
11488 | i.tm.opcode_modifier.evex = EVEX256; | |
11489 | else | |
11490 | i.tm.opcode_modifier.vex = VEX256; | |
11491 | line += 4; | |
11492 | } | |
11493 | break; | |
11494 | ||
11495 | case '5': | |
11496 | if (evex && line[2] == '1' && line[3] == '2') | |
11497 | { | |
11498 | i.tm.opcode_modifier.evex = EVEX512; | |
11499 | line += 4; | |
11500 | } | |
11501 | break; | |
11502 | } | |
11503 | } | |
11504 | ||
11505 | if (line > end && *line == '.') | |
11506 | { | |
11507 | /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */ | |
11508 | switch (line[1]) | |
11509 | { | |
11510 | case 'N': | |
11511 | if (line[2] == 'P') | |
11512 | line += 3; | |
11513 | break; | |
11514 | ||
11515 | case '6': | |
11516 | if (line[2] == '6') | |
11517 | { | |
11518 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; | |
11519 | line += 3; | |
11520 | } | |
11521 | break; | |
11522 | ||
11523 | case 'F': case 'f': | |
11524 | if (line[2] == '3') | |
11525 | { | |
11526 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
11527 | line += 3; | |
11528 | } | |
11529 | else if (line[2] == '2') | |
11530 | { | |
11531 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2; | |
11532 | line += 3; | |
11533 | } | |
11534 | break; | |
11535 | } | |
11536 | } | |
11537 | ||
11538 | if (line > end && !xop && *line == '.') | |
11539 | { | |
11540 | /* Encoding space (VEX.mmmmm, EVEX.mmmm). */ | |
11541 | switch (line[1]) | |
11542 | { | |
11543 | case '0': | |
11544 | if (TOUPPER (line[2]) != 'F') | |
11545 | break; | |
11546 | if (line[3] == '.' || is_space_char (line[3])) | |
11547 | { | |
11548 | i.insn_opcode_space = SPACE_0F; | |
11549 | line += 3; | |
11550 | } | |
11551 | else if (line[3] == '3' | |
11552 | && (line[4] == '8' || TOUPPER (line[4]) == 'A') | |
11553 | && (line[5] == '.' || is_space_char (line[5]))) | |
11554 | { | |
11555 | i.insn_opcode_space = line[4] == '8' ? SPACE_0F38 : SPACE_0F3A; | |
11556 | line += 5; | |
11557 | } | |
11558 | break; | |
11559 | ||
11560 | case 'M': | |
11561 | if (ISDIGIT (line[2]) && line[2] != '0') | |
11562 | { | |
11563 | char *e; | |
11564 | unsigned long n = strtoul (line + 2, &e, 10); | |
11565 | ||
11566 | if (n <= (evex ? 15 : 31) | |
11567 | && (*e == '.' || is_space_char (*e))) | |
11568 | { | |
11569 | i.insn_opcode_space = n; | |
11570 | line = e; | |
11571 | } | |
11572 | } | |
11573 | break; | |
11574 | } | |
11575 | } | |
11576 | ||
11577 | if (line > end && *line == '.' && line[1] == 'W') | |
11578 | { | |
11579 | /* VEX.W, XOP.W, EVEX.W */ | |
11580 | switch (line[2]) | |
11581 | { | |
11582 | case '0': | |
11583 | i.tm.opcode_modifier.vexw = VEXW0; | |
11584 | break; | |
11585 | ||
11586 | case '1': | |
11587 | i.tm.opcode_modifier.vexw = VEXW1; | |
11588 | break; | |
11589 | ||
11590 | case 'I': | |
11591 | if (line[3] == 'G') | |
11592 | { | |
11593 | i.tm.opcode_modifier.vexw = VEXWIG; | |
11594 | ++line; | |
11595 | } | |
11596 | break; | |
11597 | } | |
11598 | ||
11599 | if (i.tm.opcode_modifier.vexw) | |
11600 | line += 3; | |
11601 | } | |
11602 | ||
11603 | if (line > end && *line && !is_space_char (*line)) | |
11604 | { | |
11605 | /* Improve diagnostic a little. */ | |
11606 | if (*line == '.' && line[1] && !is_space_char (line[1])) | |
11607 | ++line; | |
11608 | goto done; | |
edd67638 JB |
11609 | } |
11610 | ||
393fbe8d JB |
11611 | /* Before processing the opcode expression, find trailing "+r" or |
11612 | "/<digit>" specifiers. */ | |
11613 | for (ptr = line; ; ++ptr) | |
11614 | { | |
11615 | unsigned long n; | |
11616 | char *e; | |
11617 | ||
11618 | ptr = strpbrk (ptr, "+/,"); | |
11619 | if (ptr == NULL || *ptr == ',') | |
11620 | break; | |
11621 | ||
11622 | if (*ptr == '+' && ptr[1] == 'r' | |
11623 | && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ','))) | |
11624 | { | |
11625 | *ptr = ' '; | |
11626 | ptr[1] = ' '; | |
11627 | i.short_form = true; | |
11628 | break; | |
11629 | } | |
11630 | ||
11631 | if (*ptr == '/' && ISDIGIT (ptr[1]) | |
11632 | && (n = strtoul (ptr + 1, &e, 8)) < 8 | |
11633 | && e == ptr + 2 | |
11634 | && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ','))) | |
11635 | { | |
11636 | *ptr = ' '; | |
11637 | ptr[1] = ' '; | |
11638 | i.tm.extension_opcode = n; | |
11639 | i.tm.opcode_modifier.modrm = 1; | |
11640 | break; | |
11641 | } | |
11642 | } | |
11643 | ||
edd67638 JB |
11644 | input_line_pointer = line; |
11645 | val = get_absolute_expression (); | |
11646 | line = input_line_pointer; | |
11647 | ||
393fbe8d JB |
11648 | if (i.short_form && (val & 7)) |
11649 | as_warn ("`+r' assumes low three opcode bits to be clear"); | |
11650 | ||
edd67638 JB |
11651 | for (j = 1; j < sizeof(val); ++j) |
11652 | if (!(val >> (j * 8))) | |
11653 | break; | |
11654 | ||
11655 | /* Trim off a prefix if present. */ | |
11656 | if (j > 1 && !vex && !xop && !evex) | |
11657 | { | |
11658 | uint8_t byte = val >> ((j - 1) * 8); | |
11659 | ||
11660 | switch (byte) | |
11661 | { | |
11662 | case DATA_PREFIX_OPCODE: | |
11663 | case REPE_PREFIX_OPCODE: | |
11664 | case REPNE_PREFIX_OPCODE: | |
11665 | if (!add_prefix (byte)) | |
11666 | goto bad; | |
11667 | val &= ((uint64_t)1 << (--j * 8)) - 1; | |
11668 | break; | |
11669 | } | |
11670 | } | |
11671 | ||
11672 | /* Trim off encoding space. */ | |
d0c2e3ec | 11673 | if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f) |
edd67638 JB |
11674 | { |
11675 | uint8_t byte = val >> ((--j - 1) * 8); | |
11676 | ||
d0c2e3ec | 11677 | i.insn_opcode_space = SPACE_0F; |
edd67638 JB |
11678 | switch (byte & -(j > 1)) |
11679 | { | |
11680 | case 0x38: | |
d0c2e3ec | 11681 | i.insn_opcode_space = SPACE_0F38; |
edd67638 JB |
11682 | --j; |
11683 | break; | |
11684 | case 0x3a: | |
d0c2e3ec | 11685 | i.insn_opcode_space = SPACE_0F3A; |
edd67638 JB |
11686 | --j; |
11687 | break; | |
11688 | } | |
d0c2e3ec | 11689 | i.tm.opcode_space = i.insn_opcode_space; |
edd67638 JB |
11690 | val &= ((uint64_t)1 << (j * 8)) - 1; |
11691 | } | |
d0c2e3ec JB |
11692 | if (!i.tm.opcode_space && (vex || evex)) |
11693 | /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5. | |
11694 | Also avoid hitting abort() there or in build_evex_prefix(). */ | |
11695 | i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F | |
11696 | : SPACE_0F38; | |
edd67638 JB |
11697 | |
11698 | if (j > 2) | |
11699 | { | |
11700 | as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val); | |
11701 | goto bad; | |
11702 | } | |
11703 | i.opcode_length = j; | |
0ff3b7d0 JB |
11704 | |
11705 | /* Handle operands, if any. */ | |
11706 | if (*line == ',') | |
11707 | { | |
11708 | i386_operand_type combined; | |
f7377a91 | 11709 | expressionS *disp_exp = NULL; |
0ff3b7d0 JB |
11710 | bool changed; |
11711 | ||
f7377a91 JB |
11712 | i.memshift = -1; |
11713 | ||
0ff3b7d0 JB |
11714 | ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]); |
11715 | this_operand = -1; | |
11716 | if (!ptr) | |
11717 | goto bad; | |
11718 | line = ptr; | |
11719 | ||
11720 | if (!i.operands) | |
11721 | { | |
11722 | as_bad (_("expecting operand after ','; got nothing")); | |
11723 | goto done; | |
11724 | } | |
11725 | ||
11726 | if (i.mem_operands > 1) | |
11727 | { | |
11728 | as_bad (_("too many memory references for `%s'"), | |
11729 | &i386_mnemonics[MN__insn]); | |
11730 | goto done; | |
11731 | } | |
11732 | ||
a6f3add0 JB |
11733 | /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */ |
11734 | if (i.vec_encoding == vex_encoding_evex512) | |
11735 | i.vec_encoding = vex_encoding_evex; | |
11736 | ||
0ff3b7d0 JB |
11737 | /* Are we to emit ModR/M encoding? */ |
11738 | if (!i.short_form | |
11739 | && (i.mem_operands | |
11740 | || i.reg_operands > (i.vec_encoding != vex_encoding_default) | |
11741 | || i.tm.extension_opcode != None)) | |
11742 | i.tm.opcode_modifier.modrm = 1; | |
11743 | ||
11744 | if (!i.tm.opcode_modifier.modrm | |
11745 | && (i.reg_operands | |
11746 | > i.short_form + 0U + (i.vec_encoding != vex_encoding_default) | |
11747 | || i.mem_operands)) | |
11748 | { | |
11749 | as_bad (_("too many register/memory operands")); | |
11750 | goto done; | |
11751 | } | |
11752 | ||
11753 | /* Enforce certain constraints on operands. */ | |
11754 | switch (i.reg_operands + i.mem_operands | |
11755 | + (i.tm.extension_opcode != None)) | |
11756 | { | |
11757 | case 0: | |
11758 | if (i.short_form) | |
11759 | { | |
11760 | as_bad (_("too few register/memory operands")); | |
11761 | goto done; | |
11762 | } | |
11763 | /* Fall through. */ | |
11764 | case 1: | |
11765 | if (i.tm.opcode_modifier.modrm) | |
11766 | { | |
11767 | as_bad (_("too few register/memory operands")); | |
11768 | goto done; | |
11769 | } | |
11770 | break; | |
11771 | ||
11772 | case 2: | |
11773 | break; | |
11774 | ||
11775 | case 4: | |
11776 | if (i.imm_operands | |
11777 | && (i.op[0].imms->X_op != O_constant | |
11778 | || !fits_in_imm4 (i.op[0].imms->X_add_number))) | |
11779 | { | |
11780 | as_bad (_("constant doesn't fit in %d bits"), evex ? 3 : 4); | |
11781 | goto done; | |
11782 | } | |
11783 | /* Fall through. */ | |
11784 | case 3: | |
11785 | if (i.vec_encoding != vex_encoding_default) | |
11786 | { | |
11787 | i.tm.opcode_modifier.vexvvvv = 1; | |
11788 | break; | |
11789 | } | |
11790 | /* Fall through. */ | |
11791 | default: | |
11792 | as_bad (_("too many register/memory operands")); | |
11793 | goto done; | |
11794 | } | |
11795 | ||
11796 | /* Bring operands into canonical order (imm, mem, reg). */ | |
11797 | do | |
11798 | { | |
11799 | changed = false; | |
11800 | ||
11801 | for (j = 1; j < i.operands; ++j) | |
11802 | { | |
11803 | if ((!operand_type_check (i.types[j - 1], imm) | |
11804 | && operand_type_check (i.types[j], imm)) | |
11805 | || (i.types[j - 1].bitfield.class != ClassNone | |
11806 | && i.types[j].bitfield.class == ClassNone)) | |
11807 | { | |
11808 | swap_2_operands (j - 1, j); | |
11809 | changed = true; | |
11810 | } | |
11811 | } | |
11812 | } | |
11813 | while (changed); | |
11814 | ||
11815 | /* For Intel syntax swap the order of register operands. */ | |
11816 | if (intel_syntax) | |
11817 | switch (i.reg_operands) | |
11818 | { | |
11819 | case 0: | |
11820 | case 1: | |
11821 | break; | |
11822 | ||
11823 | case 4: | |
11824 | swap_2_operands (i.imm_operands + i.mem_operands + 1, i.operands - 2); | |
11825 | /* Fall through. */ | |
11826 | case 3: | |
11827 | case 2: | |
11828 | swap_2_operands (i.imm_operands + i.mem_operands, i.operands - 1); | |
11829 | break; | |
11830 | ||
11831 | default: | |
11832 | abort (); | |
11833 | } | |
11834 | ||
11835 | /* Enforce constraints when using VSIB. */ | |
11836 | if (i.index_reg | |
11837 | && (i.index_reg->reg_type.bitfield.xmmword | |
11838 | || i.index_reg->reg_type.bitfield.ymmword | |
11839 | || i.index_reg->reg_type.bitfield.zmmword)) | |
11840 | { | |
11841 | if (i.vec_encoding == vex_encoding_default) | |
11842 | { | |
11843 | as_bad (_("VSIB unavailable with legacy encoding")); | |
11844 | goto done; | |
11845 | } | |
11846 | ||
11847 | if (i.vec_encoding == vex_encoding_evex | |
11848 | && i.reg_operands > 1) | |
11849 | { | |
11850 | /* We could allow two register operands, encoding the 2nd one in | |
11851 | an 8-bit immediate like for 4-register-operand insns, but that | |
11852 | would require ugly fiddling with process_operands() and/or | |
11853 | build_modrm_byte(). */ | |
11854 | as_bad (_("too many register operands with VSIB")); | |
11855 | goto done; | |
11856 | } | |
11857 | ||
11858 | i.tm.opcode_modifier.sib = 1; | |
11859 | } | |
11860 | ||
11861 | /* Establish operand size encoding. */ | |
11862 | operand_type_set (&combined, 0); | |
f7377a91 | 11863 | |
0ff3b7d0 JB |
11864 | for (j = i.imm_operands; j < i.operands; ++j) |
11865 | { | |
3e4a511b JB |
11866 | /* Look for 8-bit operands that use old registers. */ |
11867 | if (i.vec_encoding != vex_encoding_default | |
11868 | && flag_code == CODE_64BIT | |
11869 | && i.types[j].bitfield.class == Reg | |
11870 | && i.types[j].bitfield.byte | |
11871 | && !(i.op[j].regs->reg_flags & RegRex64) | |
11872 | && i.op[j].regs->reg_num > 3) | |
11873 | as_bad (_("can't encode register '%s%s' with VEX/XOP/EVEX"), | |
11874 | register_prefix, i.op[j].regs->reg_name); | |
11875 | ||
0ff3b7d0 JB |
11876 | i.types[j].bitfield.instance = InstanceNone; |
11877 | ||
11878 | if (operand_type_check (i.types[j], disp)) | |
f7377a91 JB |
11879 | { |
11880 | i.types[j].bitfield.baseindex = 1; | |
11881 | disp_exp = i.op[j].disps; | |
11882 | } | |
11883 | ||
11884 | if (evex && i.types[j].bitfield.baseindex) | |
11885 | { | |
11886 | unsigned int n = i.memshift; | |
11887 | ||
11888 | if (i.types[j].bitfield.byte) | |
11889 | n = 0; | |
11890 | else if (i.types[j].bitfield.word) | |
11891 | n = 1; | |
11892 | else if (i.types[j].bitfield.dword) | |
11893 | n = 2; | |
11894 | else if (i.types[j].bitfield.qword) | |
11895 | n = 3; | |
11896 | else if (i.types[j].bitfield.xmmword) | |
11897 | n = 4; | |
11898 | else if (i.types[j].bitfield.ymmword) | |
11899 | n = 5; | |
11900 | else if (i.types[j].bitfield.zmmword) | |
11901 | n = 6; | |
11902 | ||
11903 | if (i.memshift < 32 && n != i.memshift) | |
11904 | as_warn ("conflicting memory operand size specifiers"); | |
11905 | i.memshift = n; | |
11906 | } | |
0ff3b7d0 JB |
11907 | |
11908 | if ((i.broadcast.type || i.broadcast.bytes) | |
11909 | && j == i.broadcast.operand) | |
11910 | continue; | |
11911 | ||
11912 | combined = operand_type_or (combined, i.types[j]); | |
11913 | combined.bitfield.class = ClassNone; | |
11914 | } | |
11915 | ||
f7377a91 JB |
11916 | switch ((i.broadcast.type ? i.broadcast.type : 1) |
11917 | << (i.memshift < 32 ? i.memshift : 0)) | |
11918 | { | |
11919 | case 64: combined.bitfield.zmmword = 1; break; | |
11920 | case 32: combined.bitfield.ymmword = 1; break; | |
11921 | case 16: combined.bitfield.xmmword = 1; break; | |
11922 | case 8: combined.bitfield.qword = 1; break; | |
11923 | case 4: combined.bitfield.dword = 1; break; | |
11924 | } | |
11925 | ||
0ff3b7d0 JB |
11926 | if (i.vec_encoding == vex_encoding_default) |
11927 | { | |
11928 | if (flag_code == CODE_64BIT && combined.bitfield.qword) | |
11929 | i.rex |= REX_W; | |
11930 | else if ((flag_code == CODE_16BIT ? combined.bitfield.dword | |
11931 | : combined.bitfield.word) | |
11932 | && !add_prefix (DATA_PREFIX_OPCODE)) | |
11933 | goto done; | |
11934 | } | |
11935 | else if (!i.tm.opcode_modifier.vexw) | |
11936 | { | |
11937 | if (flag_code == CODE_64BIT) | |
11938 | { | |
11939 | if (combined.bitfield.qword) | |
11940 | i.tm.opcode_modifier.vexw = VEXW1; | |
11941 | else if (combined.bitfield.dword) | |
11942 | i.tm.opcode_modifier.vexw = VEXW0; | |
11943 | } | |
11944 | ||
11945 | if (!i.tm.opcode_modifier.vexw) | |
11946 | i.tm.opcode_modifier.vexw = VEXWIG; | |
11947 | } | |
11948 | ||
11949 | if (vex || xop) | |
11950 | { | |
11951 | if (!i.tm.opcode_modifier.vex) | |
11952 | { | |
11953 | if (combined.bitfield.ymmword) | |
11954 | i.tm.opcode_modifier.vex = VEX256; | |
11955 | else if (combined.bitfield.xmmword) | |
11956 | i.tm.opcode_modifier.vex = VEX128; | |
11957 | } | |
11958 | } | |
11959 | else if (evex) | |
11960 | { | |
11961 | if (!i.tm.opcode_modifier.evex) | |
11962 | { | |
11963 | /* Do _not_ consider AVX512VL here. */ | |
11964 | if (i.rounding.type != rc_none || combined.bitfield.zmmword) | |
11965 | i.tm.opcode_modifier.evex = EVEX512; | |
11966 | else if (combined.bitfield.ymmword) | |
11967 | i.tm.opcode_modifier.evex = EVEX256; | |
11968 | else if (combined.bitfield.xmmword) | |
11969 | i.tm.opcode_modifier.evex = EVEX128; | |
11970 | } | |
f7377a91 JB |
11971 | |
11972 | if (i.memshift >= 32) | |
11973 | { | |
11974 | unsigned int n = 0; | |
11975 | ||
11976 | switch (i.tm.opcode_modifier.evex) | |
11977 | { | |
11978 | case EVEX512: n = 64; break; | |
11979 | case EVEX256: n = 32; break; | |
11980 | case EVEX128: n = 16; break; | |
11981 | } | |
11982 | ||
11983 | if (i.broadcast.type) | |
11984 | n /= i.broadcast.type; | |
11985 | ||
11986 | if (n > 0) | |
11987 | for (i.memshift = 0; !(n & 1); n >>= 1) | |
11988 | ++i.memshift; | |
11989 | else if (disp_exp != NULL && disp_exp->X_op == O_constant | |
11990 | && disp_exp->X_add_number != 0 | |
11991 | && i.disp_encoding != disp_encoding_32bit) | |
11992 | { | |
11993 | if (!quiet_warnings) | |
11994 | as_warn ("cannot determine memory operand size"); | |
11995 | i.disp_encoding = disp_encoding_32bit; | |
11996 | } | |
11997 | } | |
0ff3b7d0 JB |
11998 | } |
11999 | ||
f7377a91 JB |
12000 | if (i.memshift >= 32) |
12001 | i.memshift = 0; | |
12002 | else if (!evex) | |
12003 | i.vec_encoding = vex_encoding_error; | |
12004 | ||
0ff3b7d0 JB |
12005 | if (i.disp_operands && !optimize_disp (&i.tm)) |
12006 | goto done; | |
12007 | ||
c032bc4f JB |
12008 | /* Establish size for immediate operands. */ |
12009 | for (j = 0; j < i.imm_operands; ++j) | |
12010 | { | |
12011 | expressionS *expP = i.op[j].imms; | |
12012 | ||
12013 | gas_assert (operand_type_check (i.types[j], imm)); | |
12014 | operand_type_set (&i.types[j], 0); | |
12015 | ||
12016 | if (i.imm_bits[j] > 32) | |
12017 | i.types[j].bitfield.imm64 = 1; | |
12018 | else if (i.imm_bits[j] > 16) | |
12019 | { | |
12020 | if (flag_code == CODE_64BIT && (i.flags[j] & Operand_Signed)) | |
12021 | i.types[j].bitfield.imm32s = 1; | |
12022 | else | |
12023 | i.types[j].bitfield.imm32 = 1; | |
12024 | } | |
12025 | else if (i.imm_bits[j] > 8) | |
12026 | i.types[j].bitfield.imm16 = 1; | |
12027 | else if (i.imm_bits[j] > 0) | |
12028 | { | |
12029 | if (i.flags[j] & Operand_Signed) | |
12030 | i.types[j].bitfield.imm8s = 1; | |
12031 | else | |
12032 | i.types[j].bitfield.imm8 = 1; | |
12033 | } | |
12034 | else if (expP->X_op == O_constant) | |
12035 | { | |
12036 | i.types[j] = smallest_imm_type (expP->X_add_number); | |
12037 | i.types[j].bitfield.imm1 = 0; | |
12038 | /* Oddly enough imm_size() checks imm64 first, so the bit needs | |
12039 | zapping since smallest_imm_type() sets it unconditionally. */ | |
12040 | if (flag_code != CODE_64BIT) | |
12041 | { | |
12042 | i.types[j].bitfield.imm64 = 0; | |
12043 | i.types[j].bitfield.imm32s = 0; | |
12044 | i.types[j].bitfield.imm32 = 1; | |
12045 | } | |
12046 | else if (i.types[j].bitfield.imm32 || i.types[j].bitfield.imm32s) | |
12047 | i.types[j].bitfield.imm64 = 0; | |
12048 | } | |
12049 | else | |
12050 | /* Non-constant expressions are sized heuristically. */ | |
12051 | switch (flag_code) | |
12052 | { | |
12053 | case CODE_64BIT: i.types[j].bitfield.imm32s = 1; break; | |
12054 | case CODE_32BIT: i.types[j].bitfield.imm32 = 1; break; | |
12055 | case CODE_16BIT: i.types[j].bitfield.imm16 = 1; break; | |
12056 | } | |
12057 | } | |
12058 | ||
0ff3b7d0 JB |
12059 | for (j = 0; j < i.operands; ++j) |
12060 | i.tm.operand_types[j] = i.types[j]; | |
12061 | ||
12062 | process_operands (); | |
12063 | } | |
12064 | ||
12065 | /* Don't set opcode until after processing operands, to avoid any | |
12066 | potential special casing there. */ | |
12067 | i.tm.base_opcode |= val; | |
12068 | ||
12069 | if (i.vec_encoding == vex_encoding_error | |
12070 | || (i.vec_encoding != vex_encoding_evex | |
12071 | ? i.broadcast.type || i.broadcast.bytes | |
12072 | || i.rounding.type != rc_none | |
12073 | || i.mask.reg | |
f586e340 JB |
12074 | : (i.mem_operands && i.rounding.type != rc_none) |
12075 | || ((i.broadcast.type || i.broadcast.bytes) | |
12076 | && !(i.flags[i.broadcast.operand] & Operand_Mem)))) | |
0ff3b7d0 JB |
12077 | { |
12078 | as_bad (_("conflicting .insn operands")); | |
12079 | goto done; | |
12080 | } | |
edd67638 | 12081 | |
d0c2e3ec JB |
12082 | if (vex || xop) |
12083 | { | |
12084 | if (!i.tm.opcode_modifier.vex) | |
12085 | i.tm.opcode_modifier.vex = VEXScalar; /* LIG */ | |
12086 | ||
12087 | build_vex_prefix (NULL); | |
12088 | i.rex &= REX_OPCODE; | |
12089 | } | |
12090 | else if (evex) | |
12091 | { | |
12092 | if (!i.tm.opcode_modifier.evex) | |
12093 | i.tm.opcode_modifier.evex = EVEXLIG; | |
12094 | ||
12095 | build_evex_prefix (); | |
12096 | i.rex &= REX_OPCODE; | |
12097 | } | |
ce705688 JB |
12098 | else |
12099 | establish_rex (); | |
d0c2e3ec | 12100 | |
b5482fe5 JB |
12101 | last_insn = &seg_info(now_seg)->tc_segment_info_data.last_insn; |
12102 | output_insn (last_insn); | |
12103 | last_insn->kind = last_insn_directive; | |
12104 | last_insn->name = ".insn directive"; | |
12105 | last_insn->file = as_where (&last_insn->line); | |
edd67638 | 12106 | |
d0c2e3ec | 12107 | done: |
edd67638 JB |
12108 | *saved_ilp = saved_char; |
12109 | input_line_pointer = line; | |
12110 | ||
12111 | demand_empty_rest_of_line (); | |
d0c2e3ec JB |
12112 | |
12113 | /* Make sure dot_insn() won't yield "true" anymore. */ | |
12114 | i.tm.mnem_off = 0; | |
edd67638 JB |
12115 | } |
12116 | ||
d182319b | 12117 | #ifdef TE_PE |
6482c264 | 12118 | static void |
7016a5d5 | 12119 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
12120 | { |
12121 | expressionS exp; | |
12122 | ||
12123 | do | |
12124 | { | |
12125 | expression (&exp); | |
12126 | if (exp.X_op == O_symbol) | |
12127 | exp.X_op = O_secrel; | |
12128 | ||
12129 | emit_expr (&exp, 4); | |
12130 | } | |
12131 | while (*input_line_pointer++ == ','); | |
12132 | ||
12133 | input_line_pointer--; | |
12134 | demand_empty_rest_of_line (); | |
12135 | } | |
145667f8 MH |
12136 | |
12137 | static void | |
12138 | pe_directive_secidx (int dummy ATTRIBUTE_UNUSED) | |
12139 | { | |
12140 | expressionS exp; | |
12141 | ||
12142 | do | |
12143 | { | |
12144 | expression (&exp); | |
12145 | if (exp.X_op == O_symbol) | |
12146 | exp.X_op = O_secidx; | |
12147 | ||
12148 | emit_expr (&exp, 2); | |
12149 | } | |
12150 | while (*input_line_pointer++ == ','); | |
12151 | ||
12152 | input_line_pointer--; | |
12153 | demand_empty_rest_of_line (); | |
12154 | } | |
6482c264 NC |
12155 | #endif |
12156 | ||
7063667e JB |
12157 | /* Handle Rounding Control / SAE specifiers. */ |
12158 | ||
12159 | static char * | |
12160 | RC_SAE_specifier (const char *pstr) | |
12161 | { | |
12162 | unsigned int j; | |
12163 | ||
12164 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
12165 | { | |
12166 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
12167 | { | |
12168 | if (i.rounding.type != rc_none) | |
12169 | { | |
12170 | as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name); | |
12171 | return NULL; | |
12172 | } | |
12173 | ||
a6f3add0 JB |
12174 | if (i.vec_encoding == vex_encoding_default) |
12175 | i.vec_encoding = vex_encoding_evex512; | |
12176 | else if (i.vec_encoding != vex_encoding_evex | |
12177 | && i.vec_encoding != vex_encoding_evex512) | |
12178 | return NULL; | |
12179 | ||
7063667e JB |
12180 | i.rounding.type = RC_NamesTable[j].type; |
12181 | ||
12182 | return (char *)(pstr + RC_NamesTable[j].len); | |
12183 | } | |
12184 | } | |
12185 | ||
12186 | return NULL; | |
12187 | } | |
12188 | ||
43234a1e L |
12189 | /* Handle Vector operations. */ |
12190 | ||
12191 | static char * | |
f70c6814 | 12192 | check_VecOperations (char *op_string) |
43234a1e L |
12193 | { |
12194 | const reg_entry *mask; | |
12195 | const char *saved; | |
12196 | char *end_op; | |
12197 | ||
f70c6814 | 12198 | while (*op_string) |
43234a1e L |
12199 | { |
12200 | saved = op_string; | |
12201 | if (*op_string == '{') | |
12202 | { | |
12203 | op_string++; | |
12204 | ||
12205 | /* Check broadcasts. */ | |
d34049e8 | 12206 | if (startswith (op_string, "1to")) |
43234a1e | 12207 | { |
5273a3cd | 12208 | unsigned int bcst_type; |
43234a1e | 12209 | |
5273a3cd | 12210 | if (i.broadcast.type) |
43234a1e L |
12211 | goto duplicated_vec_op; |
12212 | ||
12213 | op_string += 3; | |
12214 | if (*op_string == '8') | |
8e6e0792 | 12215 | bcst_type = 8; |
b28d1bda | 12216 | else if (*op_string == '4') |
8e6e0792 | 12217 | bcst_type = 4; |
b28d1bda | 12218 | else if (*op_string == '2') |
8e6e0792 | 12219 | bcst_type = 2; |
43234a1e L |
12220 | else if (*op_string == '1' |
12221 | && *(op_string+1) == '6') | |
12222 | { | |
8e6e0792 | 12223 | bcst_type = 16; |
43234a1e L |
12224 | op_string++; |
12225 | } | |
0cc78721 CL |
12226 | else if (*op_string == '3' |
12227 | && *(op_string+1) == '2') | |
12228 | { | |
12229 | bcst_type = 32; | |
12230 | op_string++; | |
12231 | } | |
43234a1e L |
12232 | else |
12233 | { | |
12234 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
12235 | return NULL; | |
12236 | } | |
12237 | op_string++; | |
12238 | ||
a6f3add0 JB |
12239 | if (i.vec_encoding == vex_encoding_default) |
12240 | i.vec_encoding = vex_encoding_evex; | |
12241 | else if (i.vec_encoding != vex_encoding_evex | |
12242 | && i.vec_encoding != vex_encoding_evex512) | |
12243 | goto unknown_vec_op; | |
12244 | ||
5273a3cd JB |
12245 | i.broadcast.type = bcst_type; |
12246 | i.broadcast.operand = this_operand; | |
f7377a91 JB |
12247 | |
12248 | /* For .insn a data size specifier may be appended. */ | |
12249 | if (dot_insn () && *op_string == ':') | |
12250 | goto dot_insn_modifier; | |
12251 | } | |
12252 | /* Check .insn special cases. */ | |
12253 | else if (dot_insn () && *op_string == ':') | |
12254 | { | |
12255 | dot_insn_modifier: | |
c032bc4f | 12256 | switch (op_string[1]) |
f7377a91 JB |
12257 | { |
12258 | unsigned long n; | |
12259 | ||
c032bc4f | 12260 | case 'd': |
f7377a91 JB |
12261 | if (i.memshift < 32) |
12262 | goto duplicated_vec_op; | |
12263 | ||
12264 | n = strtoul (op_string + 2, &end_op, 0); | |
12265 | if (n) | |
12266 | for (i.memshift = 0; !(n & 1); n >>= 1) | |
12267 | ++i.memshift; | |
12268 | if (i.memshift < 32 && n == 1) | |
12269 | op_string = end_op; | |
c032bc4f JB |
12270 | break; |
12271 | ||
12272 | case 's': case 'u': | |
12273 | /* This isn't really a "vector" operation, but a sign/size | |
12274 | specifier for immediate operands of .insn. Note that AT&T | |
12275 | syntax handles the same in i386_immediate(). */ | |
12276 | if (!intel_syntax) | |
12277 | break; | |
12278 | ||
12279 | if (i.imm_bits[this_operand]) | |
12280 | goto duplicated_vec_op; | |
12281 | ||
12282 | n = strtoul (op_string + 2, &end_op, 0); | |
12283 | if (n && n <= (flag_code == CODE_64BIT ? 64 : 32)) | |
12284 | { | |
12285 | i.imm_bits[this_operand] = n; | |
12286 | if (op_string[1] == 's') | |
12287 | i.flags[this_operand] |= Operand_Signed; | |
12288 | op_string = end_op; | |
12289 | } | |
12290 | break; | |
f7377a91 | 12291 | } |
43234a1e L |
12292 | } |
12293 | /* Check masking operation. */ | |
12294 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
12295 | { | |
8a6fb3f9 JB |
12296 | if (mask == &bad_reg) |
12297 | return NULL; | |
12298 | ||
43234a1e | 12299 | /* k0 can't be used for write mask. */ |
f74a6307 | 12300 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 12301 | { |
6d2cd6b2 JB |
12302 | as_bad (_("`%s%s' can't be used for write mask"), |
12303 | register_prefix, mask->reg_name); | |
43234a1e L |
12304 | return NULL; |
12305 | } | |
12306 | ||
6225c532 | 12307 | if (!i.mask.reg) |
43234a1e | 12308 | { |
6225c532 JB |
12309 | i.mask.reg = mask; |
12310 | i.mask.operand = this_operand; | |
43234a1e | 12311 | } |
6225c532 JB |
12312 | else if (i.mask.reg->reg_num) |
12313 | goto duplicated_vec_op; | |
43234a1e L |
12314 | else |
12315 | { | |
6225c532 | 12316 | i.mask.reg = mask; |
43234a1e L |
12317 | |
12318 | /* Only "{z}" is allowed here. No need to check | |
12319 | zeroing mask explicitly. */ | |
6225c532 | 12320 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
12321 | { |
12322 | as_bad (_("invalid write mask `%s'"), saved); | |
12323 | return NULL; | |
12324 | } | |
12325 | } | |
12326 | ||
12327 | op_string = end_op; | |
12328 | } | |
12329 | /* Check zeroing-flag for masking operation. */ | |
12330 | else if (*op_string == 'z') | |
12331 | { | |
6225c532 | 12332 | if (!i.mask.reg) |
43234a1e | 12333 | { |
6225c532 JB |
12334 | i.mask.reg = reg_k0; |
12335 | i.mask.zeroing = 1; | |
12336 | i.mask.operand = this_operand; | |
43234a1e L |
12337 | } |
12338 | else | |
12339 | { | |
6225c532 | 12340 | if (i.mask.zeroing) |
43234a1e L |
12341 | { |
12342 | duplicated_vec_op: | |
12343 | as_bad (_("duplicated `%s'"), saved); | |
12344 | return NULL; | |
12345 | } | |
12346 | ||
6225c532 | 12347 | i.mask.zeroing = 1; |
43234a1e L |
12348 | |
12349 | /* Only "{%k}" is allowed here. No need to check mask | |
12350 | register explicitly. */ | |
6225c532 | 12351 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
12352 | { |
12353 | as_bad (_("invalid zeroing-masking `%s'"), | |
12354 | saved); | |
12355 | return NULL; | |
12356 | } | |
12357 | } | |
12358 | ||
12359 | op_string++; | |
12360 | } | |
7063667e JB |
12361 | else if (intel_syntax |
12362 | && (op_string = RC_SAE_specifier (op_string)) != NULL) | |
12363 | i.rounding.modifier = true; | |
43234a1e L |
12364 | else |
12365 | goto unknown_vec_op; | |
12366 | ||
12367 | if (*op_string != '}') | |
12368 | { | |
12369 | as_bad (_("missing `}' in `%s'"), saved); | |
12370 | return NULL; | |
12371 | } | |
12372 | op_string++; | |
0ba3a731 L |
12373 | |
12374 | /* Strip whitespace since the addition of pseudo prefixes | |
12375 | changed how the scrubber treats '{'. */ | |
12376 | if (is_space_char (*op_string)) | |
12377 | ++op_string; | |
12378 | ||
43234a1e L |
12379 | continue; |
12380 | } | |
12381 | unknown_vec_op: | |
12382 | /* We don't know this one. */ | |
12383 | as_bad (_("unknown vector operation: `%s'"), saved); | |
12384 | return NULL; | |
12385 | } | |
12386 | ||
6225c532 | 12387 | if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num) |
6d2cd6b2 JB |
12388 | { |
12389 | as_bad (_("zeroing-masking only allowed with write mask")); | |
12390 | return NULL; | |
12391 | } | |
12392 | ||
43234a1e L |
12393 | return op_string; |
12394 | } | |
12395 | ||
252b5132 | 12396 | static int |
70e41ade | 12397 | i386_immediate (char *imm_start) |
252b5132 RH |
12398 | { |
12399 | char *save_input_line_pointer; | |
f3c180ae | 12400 | char *gotfree_input_line; |
252b5132 | 12401 | segT exp_seg = 0; |
47926f60 | 12402 | expressionS *exp; |
40fb9820 L |
12403 | i386_operand_type types; |
12404 | ||
0dfbf9d7 | 12405 | operand_type_set (&types, ~0); |
252b5132 RH |
12406 | |
12407 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
12408 | { | |
31b2323c L |
12409 | as_bad (_("at most %d immediate operands are allowed"), |
12410 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
12411 | return 0; |
12412 | } | |
12413 | ||
12414 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 12415 | i.op[this_operand].imms = exp; |
252b5132 RH |
12416 | |
12417 | if (is_space_char (*imm_start)) | |
12418 | ++imm_start; | |
12419 | ||
12420 | save_input_line_pointer = input_line_pointer; | |
12421 | input_line_pointer = imm_start; | |
12422 | ||
d258b828 | 12423 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
12424 | if (gotfree_input_line) |
12425 | input_line_pointer = gotfree_input_line; | |
252b5132 | 12426 | |
5cc00775 | 12427 | expr_mode = expr_operator_none; |
252b5132 RH |
12428 | exp_seg = expression (exp); |
12429 | ||
c032bc4f JB |
12430 | /* For .insn immediates there may be a size specifier. */ |
12431 | if (dot_insn () && *input_line_pointer == '{' && input_line_pointer[1] == ':' | |
12432 | && (input_line_pointer[2] == 's' || input_line_pointer[2] == 'u')) | |
12433 | { | |
12434 | char *e; | |
12435 | unsigned long n = strtoul (input_line_pointer + 3, &e, 0); | |
12436 | ||
12437 | if (*e == '}' && n && n <= (flag_code == CODE_64BIT ? 64 : 32)) | |
12438 | { | |
12439 | i.imm_bits[this_operand] = n; | |
12440 | if (input_line_pointer[2] == 's') | |
12441 | i.flags[this_operand] |= Operand_Signed; | |
12442 | input_line_pointer = e + 1; | |
12443 | } | |
12444 | } | |
12445 | ||
83183c0c | 12446 | SKIP_WHITESPACE (); |
252b5132 | 12447 | if (*input_line_pointer) |
f3c180ae | 12448 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
12449 | |
12450 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 12451 | if (gotfree_input_line) |
ee86248c JB |
12452 | { |
12453 | free (gotfree_input_line); | |
12454 | ||
9aac24b1 | 12455 | if (exp->X_op == O_constant) |
ee86248c JB |
12456 | exp->X_op = O_illegal; |
12457 | } | |
12458 | ||
9aac24b1 JB |
12459 | if (exp_seg == reg_section) |
12460 | { | |
12461 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
12462 | return 0; | |
12463 | } | |
12464 | ||
ee86248c JB |
12465 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
12466 | } | |
252b5132 | 12467 | |
ee86248c JB |
12468 | static int |
12469 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
12470 | i386_operand_type types, const char *imm_start) | |
12471 | { | |
12472 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 12473 | { |
313c53d1 L |
12474 | if (imm_start) |
12475 | as_bad (_("missing or invalid immediate expression `%s'"), | |
12476 | imm_start); | |
3992d3b7 | 12477 | return 0; |
252b5132 | 12478 | } |
3e73aa7c | 12479 | else if (exp->X_op == O_constant) |
252b5132 | 12480 | { |
47926f60 | 12481 | /* Size it properly later. */ |
40fb9820 | 12482 | i.types[this_operand].bitfield.imm64 = 1; |
a442cac5 JB |
12483 | |
12484 | /* If not 64bit, sign/zero extend val, to account for wraparound | |
12485 | when !BFD64. */ | |
5cc00775 JB |
12486 | if (expr_mode == expr_operator_present |
12487 | && flag_code != CODE_64BIT && !object_64bit) | |
a442cac5 | 12488 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
252b5132 | 12489 | } |
4c63da97 | 12490 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 12491 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 12492 | && exp_seg != absolute_section |
47926f60 | 12493 | && exp_seg != text_section |
24eab124 AM |
12494 | && exp_seg != data_section |
12495 | && exp_seg != bss_section | |
12496 | && exp_seg != undefined_section | |
f86103b7 | 12497 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 12498 | { |
d0b47220 | 12499 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
12500 | return 0; |
12501 | } | |
12502 | #endif | |
12503 | else | |
12504 | { | |
12505 | /* This is an address. The size of the address will be | |
24eab124 | 12506 | determined later, depending on destination register, |
3e73aa7c | 12507 | suffix, or the default for the section. */ |
40fb9820 L |
12508 | i.types[this_operand].bitfield.imm8 = 1; |
12509 | i.types[this_operand].bitfield.imm16 = 1; | |
12510 | i.types[this_operand].bitfield.imm32 = 1; | |
12511 | i.types[this_operand].bitfield.imm32s = 1; | |
12512 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
12513 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
12514 | types); | |
252b5132 RH |
12515 | } |
12516 | ||
12517 | return 1; | |
12518 | } | |
12519 | ||
551c1ca1 | 12520 | static char * |
e3bb37b5 | 12521 | i386_scale (char *scale) |
252b5132 | 12522 | { |
551c1ca1 AM |
12523 | offsetT val; |
12524 | char *save = input_line_pointer; | |
252b5132 | 12525 | |
551c1ca1 AM |
12526 | input_line_pointer = scale; |
12527 | val = get_absolute_expression (); | |
12528 | ||
12529 | switch (val) | |
252b5132 | 12530 | { |
551c1ca1 | 12531 | case 1: |
252b5132 RH |
12532 | i.log2_scale_factor = 0; |
12533 | break; | |
551c1ca1 | 12534 | case 2: |
252b5132 RH |
12535 | i.log2_scale_factor = 1; |
12536 | break; | |
551c1ca1 | 12537 | case 4: |
252b5132 RH |
12538 | i.log2_scale_factor = 2; |
12539 | break; | |
551c1ca1 | 12540 | case 8: |
252b5132 RH |
12541 | i.log2_scale_factor = 3; |
12542 | break; | |
12543 | default: | |
a724f0f4 JB |
12544 | { |
12545 | char sep = *input_line_pointer; | |
12546 | ||
12547 | *input_line_pointer = '\0'; | |
12548 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
12549 | scale); | |
12550 | *input_line_pointer = sep; | |
12551 | input_line_pointer = save; | |
12552 | return NULL; | |
12553 | } | |
252b5132 | 12554 | } |
29b0f896 | 12555 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
12556 | { |
12557 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 12558 | 1 << i.log2_scale_factor); |
252b5132 | 12559 | i.log2_scale_factor = 0; |
252b5132 | 12560 | } |
551c1ca1 AM |
12561 | scale = input_line_pointer; |
12562 | input_line_pointer = save; | |
12563 | return scale; | |
252b5132 RH |
12564 | } |
12565 | ||
252b5132 | 12566 | static int |
e3bb37b5 | 12567 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 12568 | { |
29b0f896 | 12569 | expressionS *exp; |
252b5132 RH |
12570 | segT exp_seg = 0; |
12571 | char *save_input_line_pointer; | |
f3c180ae | 12572 | char *gotfree_input_line; |
40fb9820 L |
12573 | int override; |
12574 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 12575 | int ret; |
252b5132 | 12576 | |
31b2323c L |
12577 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
12578 | { | |
12579 | as_bad (_("at most %d displacement operands are allowed"), | |
12580 | MAX_MEMORY_OPERANDS); | |
12581 | return 0; | |
12582 | } | |
12583 | ||
0dfbf9d7 | 12584 | operand_type_set (&bigdisp, 0); |
6f2f06be | 12585 | if (i.jumpabsolute |
48bcea9f | 12586 | || i.types[this_operand].bitfield.baseindex |
d3b01414 JB |
12587 | || (current_templates.start->opcode_modifier.jump != JUMP |
12588 | && current_templates.start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 12589 | { |
48bcea9f | 12590 | i386_addressing_mode (); |
e05278af | 12591 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
12592 | if (flag_code == CODE_64BIT) |
12593 | { | |
a775efc8 | 12594 | bigdisp.bitfield.disp32 = 1; |
40fb9820 | 12595 | if (!override) |
a775efc8 | 12596 | bigdisp.bitfield.disp64 = 1; |
40fb9820 L |
12597 | } |
12598 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 12599 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
12600 | else |
12601 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
12602 | } |
12603 | else | |
12604 | { | |
376cd056 JB |
12605 | /* For PC-relative branches, the width of the displacement may be |
12606 | dependent upon data size, but is never dependent upon address size. | |
12607 | Also make sure to not unintentionally match against a non-PC-relative | |
12608 | branch template. */ | |
d3b01414 | 12609 | const insn_template *t = current_templates.start; |
5b7c81bd | 12610 | bool has_intel64 = false; |
376cd056 | 12611 | |
d3b01414 | 12612 | while (++t < current_templates.end) |
376cd056 JB |
12613 | { |
12614 | if (t->opcode_modifier.jump | |
d3b01414 | 12615 | != current_templates.start->opcode_modifier.jump) |
376cd056 | 12616 | break; |
4b5aaf5f | 12617 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
5b7c81bd | 12618 | has_intel64 = true; |
376cd056 | 12619 | } |
d3b01414 | 12620 | current_templates.end = t; |
376cd056 | 12621 | |
e05278af | 12622 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
12623 | if (flag_code == CODE_64BIT) |
12624 | { | |
376cd056 JB |
12625 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
12626 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
12627 | bigdisp.bitfield.disp16 = 1; |
12628 | else | |
a775efc8 | 12629 | bigdisp.bitfield.disp32 = 1; |
40fb9820 L |
12630 | } |
12631 | else | |
e05278af JB |
12632 | { |
12633 | if (!override) | |
12634 | override = (i.suffix == (flag_code != CODE_16BIT | |
12635 | ? WORD_MNEM_SUFFIX | |
12636 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
12637 | bigdisp.bitfield.disp32 = 1; |
12638 | if ((flag_code == CODE_16BIT) ^ override) | |
12639 | { | |
12640 | bigdisp.bitfield.disp32 = 0; | |
12641 | bigdisp.bitfield.disp16 = 1; | |
12642 | } | |
e05278af | 12643 | } |
e05278af | 12644 | } |
c6fb90c8 L |
12645 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
12646 | bigdisp); | |
252b5132 RH |
12647 | |
12648 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 12649 | i.op[this_operand].disps = exp; |
252b5132 RH |
12650 | i.disp_operands++; |
12651 | save_input_line_pointer = input_line_pointer; | |
12652 | input_line_pointer = disp_start; | |
12653 | END_STRING_AND_SAVE (disp_end); | |
12654 | ||
12655 | #ifndef GCC_ASM_O_HACK | |
12656 | #define GCC_ASM_O_HACK 0 | |
12657 | #endif | |
12658 | #if GCC_ASM_O_HACK | |
12659 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 12660 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 12661 | && displacement_string_end[-1] == '+') |
252b5132 RH |
12662 | { |
12663 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
12664 | constraint within gcc asm statements. |
12665 | For instance: | |
12666 | ||
12667 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
12668 | __asm__ __volatile__ ( \ | |
12669 | "movw %w2,%0\n\t" \ | |
12670 | "movw %w1,2+%0\n\t" \ | |
12671 | "rorl $16,%1\n\t" \ | |
12672 | "movb %b1,4+%0\n\t" \ | |
12673 | "movb %4,5+%0\n\t" \ | |
12674 | "movb $0,6+%0\n\t" \ | |
12675 | "movb %h1,7+%0\n\t" \ | |
12676 | "rorl $16,%1" \ | |
12677 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
12678 | ||
12679 | This works great except that the output assembler ends | |
12680 | up looking a bit weird if it turns out that there is | |
12681 | no offset. You end up producing code that looks like: | |
12682 | ||
12683 | #APP | |
12684 | movw $235,(%eax) | |
12685 | movw %dx,2+(%eax) | |
12686 | rorl $16,%edx | |
12687 | movb %dl,4+(%eax) | |
12688 | movb $137,5+(%eax) | |
12689 | movb $0,6+(%eax) | |
12690 | movb %dh,7+(%eax) | |
12691 | rorl $16,%edx | |
12692 | #NO_APP | |
12693 | ||
47926f60 | 12694 | So here we provide the missing zero. */ |
24eab124 AM |
12695 | |
12696 | *displacement_string_end = '0'; | |
252b5132 RH |
12697 | } |
12698 | #endif | |
d258b828 | 12699 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
12700 | if (gotfree_input_line) |
12701 | input_line_pointer = gotfree_input_line; | |
252b5132 | 12702 | |
5cc00775 | 12703 | expr_mode = expr_operator_none; |
24eab124 | 12704 | exp_seg = expression (exp); |
252b5132 | 12705 | |
636c26b0 AM |
12706 | SKIP_WHITESPACE (); |
12707 | if (*input_line_pointer) | |
12708 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
12709 | #if GCC_ASM_O_HACK | |
12710 | RESTORE_END_STRING (disp_end + 1); | |
12711 | #endif | |
636c26b0 | 12712 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 12713 | if (gotfree_input_line) |
ee86248c JB |
12714 | { |
12715 | free (gotfree_input_line); | |
12716 | ||
12717 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
12718 | exp->X_op = O_illegal; | |
12719 | } | |
12720 | ||
12721 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
12722 | ||
12723 | RESTORE_END_STRING (disp_end); | |
12724 | ||
12725 | return ret; | |
12726 | } | |
12727 | ||
12728 | static int | |
12729 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
12730 | i386_operand_type types, const char *disp_start) | |
12731 | { | |
ee86248c | 12732 | int ret = 1; |
636c26b0 | 12733 | |
24eab124 AM |
12734 | /* We do this to make sure that the section symbol is in |
12735 | the symbol table. We will ultimately change the relocation | |
47926f60 | 12736 | to be relative to the beginning of the section. */ |
1ae12ab7 | 12737 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
12738 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
12739 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 12740 | { |
636c26b0 | 12741 | if (exp->X_op != O_symbol) |
3992d3b7 | 12742 | goto inv_disp; |
636c26b0 | 12743 | |
e5cb08ac | 12744 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
12745 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
12746 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 12747 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
12748 | exp->X_op = O_subtract; |
12749 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 12750 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 12751 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
12752 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
12753 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 12754 | else |
29b0f896 | 12755 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 12756 | } |
252b5132 | 12757 | |
3992d3b7 AM |
12758 | else if (exp->X_op == O_absent |
12759 | || exp->X_op == O_illegal | |
ee86248c | 12760 | || exp->X_op == O_big) |
2daf4fd8 | 12761 | { |
3992d3b7 AM |
12762 | inv_disp: |
12763 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 12764 | disp_start); |
3992d3b7 | 12765 | ret = 0; |
2daf4fd8 AM |
12766 | } |
12767 | ||
a50187b2 JB |
12768 | else if (exp->X_op == O_constant) |
12769 | { | |
12770 | /* Sizing gets taken care of by optimize_disp(). | |
12771 | ||
12772 | If not 64bit, sign/zero extend val, to account for wraparound | |
12773 | when !BFD64. */ | |
5cc00775 JB |
12774 | if (expr_mode == expr_operator_present |
12775 | && flag_code != CODE_64BIT && !object_64bit) | |
a50187b2 JB |
12776 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
12777 | } | |
12778 | ||
4c63da97 | 12779 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
a50187b2 | 12780 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
3992d3b7 AM |
12781 | && exp_seg != absolute_section |
12782 | && exp_seg != text_section | |
12783 | && exp_seg != data_section | |
12784 | && exp_seg != bss_section | |
12785 | && exp_seg != undefined_section | |
12786 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 12787 | { |
d0b47220 | 12788 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 12789 | ret = 0; |
24eab124 | 12790 | } |
252b5132 | 12791 | #endif |
3956db08 | 12792 | |
d3b01414 | 12793 | else if (current_templates.start->opcode_modifier.jump == JUMP_BYTE) |
48bcea9f JB |
12794 | i.types[this_operand].bitfield.disp8 = 1; |
12795 | ||
40fb9820 | 12796 | /* Check if this is a displacement only operand. */ |
02b83698 JB |
12797 | if (!i.types[this_operand].bitfield.baseindex) |
12798 | i.types[this_operand] = | |
12799 | operand_type_or (operand_type_and_not (i.types[this_operand], anydisp), | |
12800 | operand_type_and (i.types[this_operand], types)); | |
3956db08 | 12801 | |
3992d3b7 | 12802 | return ret; |
252b5132 RH |
12803 | } |
12804 | ||
2abc2bec JB |
12805 | /* Return the active addressing mode, taking address override and |
12806 | registers forming the address into consideration. Update the | |
12807 | address override prefix if necessary. */ | |
47926f60 | 12808 | |
2abc2bec JB |
12809 | static enum flag_code |
12810 | i386_addressing_mode (void) | |
252b5132 | 12811 | { |
be05d201 L |
12812 | enum flag_code addr_mode; |
12813 | ||
12814 | if (i.prefix[ADDR_PREFIX]) | |
12815 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 | 12816 | else if (flag_code == CODE_16BIT |
d3b01414 | 12817 | && is_cpu (current_templates.start, CpuMPX) |
a23b33b3 JB |
12818 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic |
12819 | from md_assemble() by "is not a valid base/index expression" | |
12820 | when there is a base and/or index. */ | |
12821 | && !i.types[this_operand].bitfield.baseindex) | |
12822 | { | |
12823 | /* MPX insn memory operands with neither base nor index must be forced | |
12824 | to use 32-bit addressing in 16-bit mode. */ | |
12825 | addr_mode = CODE_32BIT; | |
12826 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
12827 | ++i.prefixes; | |
12828 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
12829 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
12830 | } | |
be05d201 L |
12831 | else |
12832 | { | |
12833 | addr_mode = flag_code; | |
12834 | ||
24eab124 | 12835 | #if INFER_ADDR_PREFIX |
be05d201 L |
12836 | if (i.mem_operands == 0) |
12837 | { | |
12838 | /* Infer address prefix from the first memory operand. */ | |
12839 | const reg_entry *addr_reg = i.base_reg; | |
12840 | ||
12841 | if (addr_reg == NULL) | |
12842 | addr_reg = i.index_reg; | |
eecb386c | 12843 | |
be05d201 L |
12844 | if (addr_reg) |
12845 | { | |
e968fc9b | 12846 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
12847 | addr_mode = CODE_32BIT; |
12848 | else if (flag_code != CODE_64BIT | |
dc821c5f | 12849 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
12850 | addr_mode = CODE_16BIT; |
12851 | ||
12852 | if (addr_mode != flag_code) | |
12853 | { | |
12854 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
12855 | i.prefixes += 1; | |
12856 | /* Change the size of any displacement too. At most one | |
12857 | of Disp16 or Disp32 is set. | |
12858 | FIXME. There doesn't seem to be any real need for | |
12859 | separate Disp16 and Disp32 flags. The same goes for | |
12860 | Imm16 and Imm32. Removing them would probably clean | |
12861 | up the code quite a lot. */ | |
12862 | if (flag_code != CODE_64BIT | |
12863 | && (i.types[this_operand].bitfield.disp16 | |
12864 | || i.types[this_operand].bitfield.disp32)) | |
05909f23 JB |
12865 | { |
12866 | static const i386_operand_type disp16_32 = { | |
12867 | .bitfield = { .disp16 = 1, .disp32 = 1 } | |
12868 | }; | |
12869 | ||
12870 | i.types[this_operand] | |
12871 | = operand_type_xor (i.types[this_operand], disp16_32); | |
12872 | } | |
be05d201 L |
12873 | } |
12874 | } | |
12875 | } | |
24eab124 | 12876 | #endif |
be05d201 L |
12877 | } |
12878 | ||
2abc2bec JB |
12879 | return addr_mode; |
12880 | } | |
12881 | ||
12882 | /* Make sure the memory operand we've been dealt is valid. | |
12883 | Return 1 on success, 0 on a failure. */ | |
12884 | ||
12885 | static int | |
12886 | i386_index_check (const char *operand_string) | |
12887 | { | |
12888 | const char *kind = "base/index"; | |
12889 | enum flag_code addr_mode = i386_addressing_mode (); | |
d3b01414 | 12890 | const insn_template *t = current_templates.end - 1; |
2abc2bec | 12891 | |
77a19f0e | 12892 | if (t->opcode_modifier.isstring) |
fc0763e6 JB |
12893 | { |
12894 | /* Memory operands of string insns are special in that they only allow | |
12895 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 | 12896 | const reg_entry *expected_reg; |
069a1561 | 12897 | static const char di_si[][2][4] = |
be05d201 L |
12898 | { |
12899 | { "esi", "edi" }, | |
12900 | { "si", "di" }, | |
12901 | { "rsi", "rdi" } | |
12902 | }; | |
069a1561 | 12903 | static const char bx[][4] = { "ebx", "bx", "rbx" }; |
fc0763e6 JB |
12904 | |
12905 | kind = "string address"; | |
12906 | ||
a152332d | 12907 | if (t->opcode_modifier.prefixok == PrefixRep) |
fc0763e6 | 12908 | { |
77a19f0e | 12909 | int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0; |
51c8edf6 | 12910 | int op = 0; |
fc0763e6 | 12911 | |
77a19f0e | 12912 | if (!t->operand_types[0].bitfield.baseindex |
fc0763e6 | 12913 | || ((!i.mem_operands != !intel_syntax) |
77a19f0e | 12914 | && t->operand_types[1].bitfield.baseindex)) |
51c8edf6 | 12915 | op = 1; |
fe0e921f AM |
12916 | expected_reg |
12917 | = (const reg_entry *) str_hash_find (reg_hash, | |
12918 | di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
12919 | } |
12920 | else | |
fe0e921f AM |
12921 | expected_reg |
12922 | = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); | |
fc0763e6 | 12923 | |
be05d201 L |
12924 | if (i.base_reg != expected_reg |
12925 | || i.index_reg | |
fc0763e6 | 12926 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 12927 | { |
be05d201 L |
12928 | /* The second memory operand must have the same size as |
12929 | the first one. */ | |
12930 | if (i.mem_operands | |
12931 | && i.base_reg | |
12932 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 12933 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 12934 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
12935 | ? i.base_reg->reg_type.bitfield.dword |
12936 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
12937 | goto bad_address; |
12938 | ||
fc0763e6 JB |
12939 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
12940 | operand_string, | |
12941 | intel_syntax ? '[' : '(', | |
12942 | register_prefix, | |
be05d201 | 12943 | expected_reg->reg_name, |
fc0763e6 | 12944 | intel_syntax ? ']' : ')'); |
be05d201 | 12945 | return 1; |
fc0763e6 | 12946 | } |
be05d201 L |
12947 | else |
12948 | return 1; | |
12949 | ||
dc1e8a47 | 12950 | bad_address: |
be05d201 L |
12951 | as_bad (_("`%s' is not a valid %s expression"), |
12952 | operand_string, kind); | |
12953 | return 0; | |
3e73aa7c JH |
12954 | } |
12955 | else | |
12956 | { | |
d3b01414 | 12957 | t = current_templates.start; |
77a19f0e | 12958 | |
be05d201 L |
12959 | if (addr_mode != CODE_16BIT) |
12960 | { | |
12961 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
12962 | if (i.disp_encoding == disp_encoding_16bit) |
12963 | { | |
12964 | bad_disp: | |
12965 | as_bad (_("invalid `%s' prefix"), | |
12966 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
12967 | return 0; | |
12968 | } | |
12969 | ||
be05d201 | 12970 | if ((i.base_reg |
e968fc9b JB |
12971 | && ((addr_mode == CODE_64BIT |
12972 | ? !i.base_reg->reg_type.bitfield.qword | |
12973 | : !i.base_reg->reg_type.bitfield.dword) | |
12974 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
12975 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 12976 | || (i.index_reg |
1b54b8d7 JB |
12977 | && !i.index_reg->reg_type.bitfield.xmmword |
12978 | && !i.index_reg->reg_type.bitfield.ymmword | |
12979 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 12980 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
12981 | ? !i.index_reg->reg_type.bitfield.qword |
12982 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
12983 | || !i.index_reg->reg_type.bitfield.baseindex))) |
12984 | goto bad_address; | |
8178be5b | 12985 | |
260cd341 | 12986 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
7fc69528 JB |
12987 | if (t->mnem_off == MN_bndmk |
12988 | || t->mnem_off == MN_bndldx | |
12989 | || t->mnem_off == MN_bndstx | |
a152332d | 12990 | || t->opcode_modifier.sib == SIBMEM) |
8178be5b JB |
12991 | { |
12992 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 12993 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
12994 | { |
12995 | as_bad (_("`%s' cannot be used here"), operand_string); | |
12996 | return 0; | |
12997 | } | |
12998 | ||
12999 | /* bndldx and bndstx ignore their scale factor. */ | |
7fc69528 | 13000 | if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx) |
8178be5b JB |
13001 | && i.log2_scale_factor) |
13002 | as_warn (_("register scaling is being ignored here")); | |
13003 | } | |
be05d201 L |
13004 | } |
13005 | else | |
3e73aa7c | 13006 | { |
be05d201 | 13007 | /* 16-bit checks. */ |
41eb8e88 L |
13008 | if (i.disp_encoding == disp_encoding_32bit) |
13009 | goto bad_disp; | |
13010 | ||
3e73aa7c | 13011 | if ((i.base_reg |
dc821c5f | 13012 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 13013 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 13014 | || (i.index_reg |
dc821c5f | 13015 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 13016 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
13017 | || !(i.base_reg |
13018 | && i.base_reg->reg_num < 6 | |
13019 | && i.index_reg->reg_num >= 6 | |
13020 | && i.log2_scale_factor == 0)))) | |
be05d201 | 13021 | goto bad_address; |
3e73aa7c JH |
13022 | } |
13023 | } | |
be05d201 | 13024 | return 1; |
24eab124 | 13025 | } |
252b5132 | 13026 | |
43234a1e L |
13027 | /* Handle vector immediates. */ |
13028 | ||
13029 | static int | |
13030 | RC_SAE_immediate (const char *imm_start) | |
13031 | { | |
43234a1e | 13032 | const char *pstr = imm_start; |
43234a1e L |
13033 | |
13034 | if (*pstr != '{') | |
13035 | return 0; | |
13036 | ||
7063667e JB |
13037 | pstr = RC_SAE_specifier (pstr + 1); |
13038 | if (pstr == NULL) | |
43234a1e L |
13039 | return 0; |
13040 | ||
13041 | if (*pstr++ != '}') | |
13042 | { | |
13043 | as_bad (_("Missing '}': '%s'"), imm_start); | |
13044 | return 0; | |
13045 | } | |
13046 | /* RC/SAE immediate string should contain nothing more. */; | |
13047 | if (*pstr != 0) | |
13048 | { | |
13049 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
13050 | return 0; | |
13051 | } | |
13052 | ||
cf665fee JB |
13053 | /* Internally this doesn't count as an operand. */ |
13054 | --i.operands; | |
43234a1e | 13055 | |
43234a1e L |
13056 | return 1; |
13057 | } | |
13058 | ||
9d299bea JB |
13059 | static INLINE bool starts_memory_operand (char c) |
13060 | { | |
014fbcda | 13061 | return ISDIGIT (c) |
4795cd4a | 13062 | || is_name_beginner (c) |
014fbcda | 13063 | || strchr ("([\"+-!~", c); |
9d299bea JB |
13064 | } |
13065 | ||
fc0763e6 | 13066 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 13067 | on error. */ |
252b5132 | 13068 | |
252b5132 | 13069 | static int |
a7619375 | 13070 | i386_att_operand (char *operand_string) |
252b5132 | 13071 | { |
af6bdddf AM |
13072 | const reg_entry *r; |
13073 | char *end_op; | |
24eab124 | 13074 | char *op_string = operand_string; |
252b5132 | 13075 | |
24eab124 | 13076 | if (is_space_char (*op_string)) |
252b5132 RH |
13077 | ++op_string; |
13078 | ||
24eab124 | 13079 | /* We check for an absolute prefix (differentiating, |
47926f60 | 13080 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
ccb05c9c | 13081 | if (*op_string == ABSOLUTE_PREFIX |
d3b01414 | 13082 | && current_templates.start->opcode_modifier.jump) |
24eab124 AM |
13083 | { |
13084 | ++op_string; | |
13085 | if (is_space_char (*op_string)) | |
13086 | ++op_string; | |
5b7c81bd | 13087 | i.jumpabsolute = true; |
24eab124 | 13088 | } |
252b5132 | 13089 | |
47926f60 | 13090 | /* Check if operand is a register. */ |
4d1bb795 | 13091 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 13092 | { |
40fb9820 L |
13093 | i386_operand_type temp; |
13094 | ||
8a6fb3f9 JB |
13095 | if (r == &bad_reg) |
13096 | return 0; | |
13097 | ||
24eab124 AM |
13098 | /* Check for a segment override by searching for ':' after a |
13099 | segment register. */ | |
13100 | op_string = end_op; | |
13101 | if (is_space_char (*op_string)) | |
13102 | ++op_string; | |
00cee14f | 13103 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 | 13104 | { |
5e042380 | 13105 | i.seg[i.mem_operands] = r; |
252b5132 | 13106 | |
24eab124 | 13107 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
13108 | ++op_string; |
13109 | if (is_space_char (*op_string)) | |
24eab124 | 13110 | ++op_string; |
252b5132 | 13111 | |
47926f60 | 13112 | /* Handle case of %es:*foo. */ |
ccb05c9c | 13113 | if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX |
d3b01414 | 13114 | && current_templates.start->opcode_modifier.jump) |
24eab124 AM |
13115 | { |
13116 | ++op_string; | |
13117 | if (is_space_char (*op_string)) | |
13118 | ++op_string; | |
5b7c81bd | 13119 | i.jumpabsolute = true; |
24eab124 | 13120 | } |
c8d541e2 | 13121 | |
9d299bea | 13122 | if (!starts_memory_operand (*op_string)) |
c8d541e2 JB |
13123 | { |
13124 | as_bad (_("bad memory operand `%s'"), op_string); | |
13125 | return 0; | |
13126 | } | |
24eab124 AM |
13127 | goto do_memory_reference; |
13128 | } | |
43234a1e L |
13129 | |
13130 | /* Handle vector operations. */ | |
13131 | if (*op_string == '{') | |
13132 | { | |
f70c6814 | 13133 | op_string = check_VecOperations (op_string); |
43234a1e L |
13134 | if (op_string == NULL) |
13135 | return 0; | |
13136 | } | |
13137 | ||
24eab124 AM |
13138 | if (*op_string) |
13139 | { | |
d0b47220 | 13140 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
13141 | return 0; |
13142 | } | |
0ff3b7d0 JB |
13143 | |
13144 | /* Reject pseudo registers for .insn. */ | |
13145 | if (dot_insn () && r->reg_type.bitfield.class == ClassNone) | |
13146 | { | |
13147 | as_bad (_("`%s%s' cannot be used here"), | |
13148 | register_prefix, r->reg_name); | |
13149 | return 0; | |
13150 | } | |
13151 | ||
40fb9820 L |
13152 | temp = r->reg_type; |
13153 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
13154 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
13155 | temp); | |
7d5e4556 | 13156 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 13157 | i.op[this_operand].regs = r; |
24eab124 | 13158 | i.reg_operands++; |
cf665fee JB |
13159 | |
13160 | /* A GPR may follow an RC or SAE immediate only if a (vector) register | |
13161 | operand was also present earlier on. */ | |
13162 | if (i.rounding.type != rc_none && temp.bitfield.class == Reg | |
13163 | && i.reg_operands == 1) | |
13164 | { | |
13165 | unsigned int j; | |
13166 | ||
13167 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j) | |
13168 | if (i.rounding.type == RC_NamesTable[j].type) | |
13169 | break; | |
13170 | as_bad (_("`%s': misplaced `{%s}'"), | |
d3b01414 | 13171 | insn_name (current_templates.start), RC_NamesTable[j].name); |
cf665fee JB |
13172 | return 0; |
13173 | } | |
24eab124 | 13174 | } |
af6bdddf AM |
13175 | else if (*op_string == REGISTER_PREFIX) |
13176 | { | |
13177 | as_bad (_("bad register name `%s'"), op_string); | |
13178 | return 0; | |
13179 | } | |
24eab124 | 13180 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 13181 | { |
24eab124 | 13182 | ++op_string; |
6f2f06be | 13183 | if (i.jumpabsolute) |
24eab124 | 13184 | { |
d0b47220 | 13185 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
13186 | return 0; |
13187 | } | |
13188 | if (!i386_immediate (op_string)) | |
13189 | return 0; | |
cf665fee JB |
13190 | if (i.rounding.type != rc_none) |
13191 | { | |
13192 | as_bad (_("`%s': RC/SAE operand must follow immediate operands"), | |
d3b01414 | 13193 | insn_name (current_templates.start)); |
cf665fee JB |
13194 | return 0; |
13195 | } | |
24eab124 | 13196 | } |
43234a1e L |
13197 | else if (RC_SAE_immediate (operand_string)) |
13198 | { | |
cf665fee JB |
13199 | /* If it is a RC or SAE immediate, do the necessary placement check: |
13200 | Only another immediate or a GPR may precede it. */ | |
13201 | if (i.mem_operands || i.reg_operands + i.imm_operands > 1 | |
13202 | || (i.reg_operands == 1 | |
13203 | && i.op[0].regs->reg_type.bitfield.class != Reg)) | |
13204 | { | |
13205 | as_bad (_("`%s': misplaced `%s'"), | |
d3b01414 | 13206 | insn_name (current_templates.start), operand_string); |
cf665fee JB |
13207 | return 0; |
13208 | } | |
43234a1e | 13209 | } |
9d299bea | 13210 | else if (starts_memory_operand (*op_string)) |
24eab124 | 13211 | { |
47926f60 | 13212 | /* This is a memory reference of some sort. */ |
af6bdddf | 13213 | char *base_string; |
252b5132 | 13214 | |
47926f60 | 13215 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
13216 | char *displacement_string_start; |
13217 | char *displacement_string_end; | |
252b5132 | 13218 | |
24eab124 | 13219 | do_memory_reference: |
24eab124 AM |
13220 | /* Check for base index form. We detect the base index form by |
13221 | looking for an ')' at the end of the operand, searching | |
13222 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
13223 | after the '('. */ | |
af6bdddf | 13224 | base_string = op_string + strlen (op_string); |
c3332e24 | 13225 | |
43234a1e | 13226 | /* Handle vector operations. */ |
6b5ba0d4 JB |
13227 | --base_string; |
13228 | if (is_space_char (*base_string)) | |
13229 | --base_string; | |
13230 | ||
13231 | if (*base_string == '}') | |
43234a1e | 13232 | { |
6b5ba0d4 JB |
13233 | char *vop_start = NULL; |
13234 | ||
13235 | while (base_string-- > op_string) | |
13236 | { | |
13237 | if (*base_string == '"') | |
13238 | break; | |
13239 | if (*base_string != '{') | |
13240 | continue; | |
13241 | ||
13242 | vop_start = base_string; | |
13243 | ||
13244 | --base_string; | |
13245 | if (is_space_char (*base_string)) | |
13246 | --base_string; | |
13247 | ||
13248 | if (*base_string != '}') | |
13249 | break; | |
13250 | ||
13251 | vop_start = NULL; | |
13252 | } | |
13253 | ||
13254 | if (!vop_start) | |
13255 | { | |
13256 | as_bad (_("unbalanced figure braces")); | |
13257 | return 0; | |
13258 | } | |
13259 | ||
f70c6814 | 13260 | if (check_VecOperations (vop_start) == NULL) |
43234a1e | 13261 | return 0; |
43234a1e L |
13262 | } |
13263 | ||
47926f60 | 13264 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
13265 | displacement_string_start = op_string; |
13266 | displacement_string_end = base_string + 1; | |
252b5132 | 13267 | |
24eab124 AM |
13268 | if (*base_string == ')') |
13269 | { | |
af6bdddf | 13270 | char *temp_string; |
e87fb6a6 JB |
13271 | unsigned int parens_not_balanced = 0; |
13272 | bool in_quotes = false; | |
e68c3d59 | 13273 | |
24eab124 | 13274 | /* We've already checked that the number of left & right ()'s are |
e87fb6a6 JB |
13275 | equal, and that there's a matching set of double quotes. */ |
13276 | end_op = base_string; | |
13277 | for (temp_string = op_string; temp_string < end_op; temp_string++) | |
24eab124 | 13278 | { |
e87fb6a6 JB |
13279 | if (*temp_string == '\\' && temp_string[1] == '"') |
13280 | ++temp_string; | |
13281 | else if (*temp_string == '"') | |
13282 | in_quotes = !in_quotes; | |
13283 | else if (!in_quotes) | |
13284 | { | |
13285 | if (*temp_string == '(' && !parens_not_balanced++) | |
13286 | base_string = temp_string; | |
13287 | if (*temp_string == ')') | |
13288 | --parens_not_balanced; | |
13289 | } | |
24eab124 | 13290 | } |
c3332e24 | 13291 | |
af6bdddf | 13292 | temp_string = base_string; |
c3332e24 | 13293 | |
24eab124 | 13294 | /* Skip past '(' and whitespace. */ |
4f081312 | 13295 | gas_assert (*base_string == '('); |
e87fb6a6 | 13296 | ++base_string; |
252b5132 | 13297 | if (is_space_char (*base_string)) |
24eab124 | 13298 | ++base_string; |
252b5132 | 13299 | |
af6bdddf | 13300 | if (*base_string == ',' |
4eed87de AM |
13301 | || ((i.base_reg = parse_register (base_string, &end_op)) |
13302 | != NULL)) | |
252b5132 | 13303 | { |
af6bdddf | 13304 | displacement_string_end = temp_string; |
252b5132 | 13305 | |
40fb9820 | 13306 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 13307 | |
af6bdddf | 13308 | if (i.base_reg) |
24eab124 | 13309 | { |
8a6fb3f9 JB |
13310 | if (i.base_reg == &bad_reg) |
13311 | return 0; | |
24eab124 AM |
13312 | base_string = end_op; |
13313 | if (is_space_char (*base_string)) | |
13314 | ++base_string; | |
af6bdddf AM |
13315 | } |
13316 | ||
13317 | /* There may be an index reg or scale factor here. */ | |
13318 | if (*base_string == ',') | |
13319 | { | |
13320 | ++base_string; | |
13321 | if (is_space_char (*base_string)) | |
13322 | ++base_string; | |
13323 | ||
4eed87de AM |
13324 | if ((i.index_reg = parse_register (base_string, &end_op)) |
13325 | != NULL) | |
24eab124 | 13326 | { |
8a6fb3f9 JB |
13327 | if (i.index_reg == &bad_reg) |
13328 | return 0; | |
af6bdddf | 13329 | base_string = end_op; |
24eab124 AM |
13330 | if (is_space_char (*base_string)) |
13331 | ++base_string; | |
af6bdddf AM |
13332 | if (*base_string == ',') |
13333 | { | |
13334 | ++base_string; | |
13335 | if (is_space_char (*base_string)) | |
13336 | ++base_string; | |
13337 | } | |
e5cb08ac | 13338 | else if (*base_string != ')') |
af6bdddf | 13339 | { |
4eed87de AM |
13340 | as_bad (_("expecting `,' or `)' " |
13341 | "after index register in `%s'"), | |
af6bdddf AM |
13342 | operand_string); |
13343 | return 0; | |
13344 | } | |
24eab124 | 13345 | } |
af6bdddf | 13346 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 13347 | { |
f76bf5e0 L |
13348 | end_op = strchr (base_string, ','); |
13349 | if (end_op) | |
13350 | *end_op = '\0'; | |
af6bdddf | 13351 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
13352 | return 0; |
13353 | } | |
252b5132 | 13354 | |
47926f60 | 13355 | /* Check for scale factor. */ |
551c1ca1 | 13356 | if (*base_string != ')') |
af6bdddf | 13357 | { |
551c1ca1 AM |
13358 | char *end_scale = i386_scale (base_string); |
13359 | ||
13360 | if (!end_scale) | |
af6bdddf | 13361 | return 0; |
24eab124 | 13362 | |
551c1ca1 | 13363 | base_string = end_scale; |
af6bdddf AM |
13364 | if (is_space_char (*base_string)) |
13365 | ++base_string; | |
13366 | if (*base_string != ')') | |
13367 | { | |
4eed87de AM |
13368 | as_bad (_("expecting `)' " |
13369 | "after scale factor in `%s'"), | |
af6bdddf AM |
13370 | operand_string); |
13371 | return 0; | |
13372 | } | |
13373 | } | |
13374 | else if (!i.index_reg) | |
24eab124 | 13375 | { |
4eed87de AM |
13376 | as_bad (_("expecting index register or scale factor " |
13377 | "after `,'; got '%c'"), | |
af6bdddf | 13378 | *base_string); |
24eab124 AM |
13379 | return 0; |
13380 | } | |
13381 | } | |
af6bdddf | 13382 | else if (*base_string != ')') |
24eab124 | 13383 | { |
4eed87de AM |
13384 | as_bad (_("expecting `,' or `)' " |
13385 | "after base register in `%s'"), | |
af6bdddf | 13386 | operand_string); |
24eab124 AM |
13387 | return 0; |
13388 | } | |
c3332e24 | 13389 | } |
af6bdddf | 13390 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 13391 | { |
f76bf5e0 L |
13392 | end_op = strchr (base_string, ','); |
13393 | if (end_op) | |
13394 | *end_op = '\0'; | |
af6bdddf | 13395 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 13396 | return 0; |
c3332e24 | 13397 | } |
24eab124 AM |
13398 | } |
13399 | ||
13400 | /* If there's an expression beginning the operand, parse it, | |
13401 | assuming displacement_string_start and | |
13402 | displacement_string_end are meaningful. */ | |
13403 | if (displacement_string_start != displacement_string_end) | |
13404 | { | |
13405 | if (!i386_displacement (displacement_string_start, | |
13406 | displacement_string_end)) | |
13407 | return 0; | |
13408 | } | |
13409 | ||
13410 | /* Special case for (%dx) while doing input/output op. */ | |
13411 | if (i.base_reg | |
75e5731b JB |
13412 | && i.base_reg->reg_type.bitfield.instance == RegD |
13413 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
13414 | && i.index_reg == 0 |
13415 | && i.log2_scale_factor == 0 | |
13416 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 13417 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 13418 | { |
2fb5be8d | 13419 | i.types[this_operand] = i.base_reg->reg_type; |
f0a4cb15 CL |
13420 | i.op[this_operand].regs = i.base_reg; |
13421 | i.base_reg = NULL; | |
9373f275 | 13422 | i.input_output_operand = true; |
24eab124 AM |
13423 | return 1; |
13424 | } | |
13425 | ||
eecb386c AM |
13426 | if (i386_index_check (operand_string) == 0) |
13427 | return 0; | |
c48dadc9 | 13428 | i.flags[this_operand] |= Operand_Mem; |
24eab124 AM |
13429 | i.mem_operands++; |
13430 | } | |
13431 | else | |
ce8a8b2f AM |
13432 | { |
13433 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
13434 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
13435 | output_invalid (*op_string), | |
13436 | this_operand + 1, | |
13437 | op_string); | |
13438 | return 0; | |
13439 | } | |
47926f60 | 13440 | return 1; /* Normal return. */ |
252b5132 RH |
13441 | } |
13442 | \f | |
fa94de6b RM |
13443 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
13444 | that an rs_machine_dependent frag may reach. */ | |
13445 | ||
13446 | unsigned int | |
13447 | i386_frag_max_var (fragS *frag) | |
13448 | { | |
13449 | /* The only relaxable frags are for jumps. | |
13450 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
13451 | gas_assert (frag->fr_type == rs_machine_dependent); | |
13452 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
13453 | } | |
13454 | ||
b084df0b L |
13455 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13456 | static int | |
8dcea932 | 13457 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
13458 | { |
13459 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
13460 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
13461 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
13462 | return 0; | |
13463 | ||
13464 | if (!S_IS_EXTERNAL (fr_symbol)) | |
13465 | /* Symbol may be weak or local. */ | |
13466 | return !S_IS_WEAK (fr_symbol); | |
13467 | ||
8dcea932 L |
13468 | /* Global symbols with non-default visibility can't be preempted. */ |
13469 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
13470 | return 1; | |
13471 | ||
13472 | if (fr_var != NO_RELOC) | |
13473 | switch ((enum bfd_reloc_code_real) fr_var) | |
13474 | { | |
13475 | case BFD_RELOC_386_PLT32: | |
13476 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 13477 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
13478 | return 0; |
13479 | default: | |
13480 | abort (); | |
13481 | } | |
13482 | ||
b084df0b L |
13483 | /* Global symbols with default visibility in a shared library may be |
13484 | preempted by another definition. */ | |
8dcea932 | 13485 | return !shared; |
b084df0b L |
13486 | } |
13487 | #endif | |
13488 | ||
79d72f45 HL |
13489 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
13490 | Note also work for Skylake and Cascadelake. | |
13491 | --------------------------------------------------------------------- | |
13492 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
13493 | | ------ | ----------- | ------- | -------- | | |
13494 | | Jo | N | N | Y | | |
13495 | | Jno | N | N | Y | | |
13496 | | Jc/Jb | Y | N | Y | | |
13497 | | Jae/Jnb | Y | N | Y | | |
13498 | | Je/Jz | Y | Y | Y | | |
13499 | | Jne/Jnz | Y | Y | Y | | |
13500 | | Jna/Jbe | Y | N | Y | | |
13501 | | Ja/Jnbe | Y | N | Y | | |
13502 | | Js | N | N | Y | | |
13503 | | Jns | N | N | Y | | |
13504 | | Jp/Jpe | N | N | Y | | |
13505 | | Jnp/Jpo | N | N | Y | | |
13506 | | Jl/Jnge | Y | Y | Y | | |
13507 | | Jge/Jnl | Y | Y | Y | | |
13508 | | Jle/Jng | Y | Y | Y | | |
13509 | | Jg/Jnle | Y | Y | Y | | |
13510 | --------------------------------------------------------------------- */ | |
13511 | static int | |
13512 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
13513 | { | |
13514 | if (mf_cmp == mf_cmp_alu_cmp) | |
13515 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
13516 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
13517 | if (mf_cmp == mf_cmp_incdec) | |
13518 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
13519 | || mf_jcc == mf_jcc_jle); | |
13520 | if (mf_cmp == mf_cmp_test_and) | |
13521 | return 1; | |
13522 | return 0; | |
13523 | } | |
13524 | ||
e379e5f3 L |
13525 | /* Return the next non-empty frag. */ |
13526 | ||
13527 | static fragS * | |
13528 | i386_next_non_empty_frag (fragS *fragP) | |
13529 | { | |
13530 | /* There may be a frag with a ".fill 0" when there is no room in | |
13531 | the current frag for frag_grow in output_insn. */ | |
13532 | for (fragP = fragP->fr_next; | |
13533 | (fragP != NULL | |
13534 | && fragP->fr_type == rs_fill | |
13535 | && fragP->fr_fix == 0); | |
13536 | fragP = fragP->fr_next) | |
13537 | ; | |
13538 | return fragP; | |
13539 | } | |
13540 | ||
13541 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
13542 | ||
13543 | static fragS * | |
79d72f45 | 13544 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 13545 | { |
79d72f45 HL |
13546 | fragS *branch_fragP; |
13547 | if (!pad_fragP) | |
e379e5f3 L |
13548 | return NULL; |
13549 | ||
79d72f45 HL |
13550 | if (pad_fragP->fr_type == rs_machine_dependent |
13551 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
13552 | == BRANCH_PADDING)) |
13553 | { | |
79d72f45 HL |
13554 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
13555 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 13556 | return NULL; |
79d72f45 HL |
13557 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
13558 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
13559 | pad_fragP->tc_frag_data.mf_type)) | |
13560 | return branch_fragP; | |
e379e5f3 L |
13561 | } |
13562 | ||
13563 | return NULL; | |
13564 | } | |
13565 | ||
13566 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
13567 | ||
13568 | static void | |
13569 | i386_classify_machine_dependent_frag (fragS *fragP) | |
13570 | { | |
13571 | fragS *cmp_fragP; | |
13572 | fragS *pad_fragP; | |
13573 | fragS *branch_fragP; | |
13574 | fragS *next_fragP; | |
13575 | unsigned int max_prefix_length; | |
13576 | ||
13577 | if (fragP->tc_frag_data.classified) | |
13578 | return; | |
13579 | ||
13580 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
13581 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
13582 | for (next_fragP = fragP; | |
13583 | next_fragP != NULL; | |
13584 | next_fragP = next_fragP->fr_next) | |
13585 | { | |
13586 | next_fragP->tc_frag_data.classified = 1; | |
13587 | if (next_fragP->fr_type == rs_machine_dependent) | |
13588 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
13589 | { | |
13590 | case BRANCH_PADDING: | |
13591 | /* The BRANCH_PADDING frag must be followed by a branch | |
13592 | frag. */ | |
13593 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
13594 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
13595 | break; | |
13596 | case FUSED_JCC_PADDING: | |
13597 | /* Check if this is a fused jcc: | |
13598 | FUSED_JCC_PADDING | |
13599 | CMP like instruction | |
13600 | BRANCH_PADDING | |
13601 | COND_JUMP | |
13602 | */ | |
13603 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
13604 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 13605 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
13606 | if (branch_fragP) |
13607 | { | |
13608 | /* The BRANCH_PADDING frag is merged with the | |
13609 | FUSED_JCC_PADDING frag. */ | |
13610 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
13611 | /* CMP like instruction size. */ | |
13612 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
13613 | frag_wane (pad_fragP); | |
13614 | /* Skip to branch_fragP. */ | |
13615 | next_fragP = branch_fragP; | |
13616 | } | |
13617 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
13618 | { | |
13619 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
13620 | a fused jcc. */ | |
13621 | next_fragP->fr_subtype | |
13622 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
13623 | next_fragP->tc_frag_data.max_bytes | |
13624 | = next_fragP->tc_frag_data.max_prefix_length; | |
13625 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
13626 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
13627 | } | |
13628 | else | |
13629 | frag_wane (next_fragP); | |
13630 | break; | |
13631 | } | |
13632 | } | |
13633 | ||
13634 | /* Stop if there is no BRANCH_PREFIX. */ | |
13635 | if (!align_branch_prefix_size) | |
13636 | return; | |
13637 | ||
13638 | /* Scan for BRANCH_PREFIX. */ | |
13639 | for (; fragP != NULL; fragP = fragP->fr_next) | |
13640 | { | |
13641 | if (fragP->fr_type != rs_machine_dependent | |
13642 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
13643 | != BRANCH_PREFIX)) | |
13644 | continue; | |
13645 | ||
13646 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
13647 | COND_JUMP_PREFIX. */ | |
13648 | max_prefix_length = 0; | |
13649 | for (next_fragP = fragP; | |
13650 | next_fragP != NULL; | |
13651 | next_fragP = next_fragP->fr_next) | |
13652 | { | |
13653 | if (next_fragP->fr_type == rs_fill) | |
13654 | /* Skip rs_fill frags. */ | |
13655 | continue; | |
13656 | else if (next_fragP->fr_type != rs_machine_dependent) | |
13657 | /* Stop for all other frags. */ | |
13658 | break; | |
13659 | ||
13660 | /* rs_machine_dependent frags. */ | |
13661 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13662 | == BRANCH_PREFIX) | |
13663 | { | |
13664 | /* Count BRANCH_PREFIX frags. */ | |
13665 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
13666 | { | |
13667 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
13668 | frag_wane (next_fragP); | |
13669 | } | |
13670 | else | |
13671 | max_prefix_length | |
13672 | += next_fragP->tc_frag_data.max_bytes; | |
13673 | } | |
13674 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13675 | == BRANCH_PADDING) | |
13676 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13677 | == FUSED_JCC_PADDING)) | |
13678 | { | |
13679 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
13680 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
13681 | break; | |
13682 | } | |
13683 | else | |
13684 | /* Stop for other rs_machine_dependent frags. */ | |
13685 | break; | |
13686 | } | |
13687 | ||
13688 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
13689 | ||
13690 | /* Skip to the next frag. */ | |
13691 | fragP = next_fragP; | |
13692 | } | |
13693 | } | |
13694 | ||
13695 | /* Compute padding size for | |
13696 | ||
13697 | FUSED_JCC_PADDING | |
13698 | CMP like instruction | |
13699 | BRANCH_PADDING | |
13700 | COND_JUMP/UNCOND_JUMP | |
13701 | ||
13702 | or | |
13703 | ||
13704 | BRANCH_PADDING | |
13705 | COND_JUMP/UNCOND_JUMP | |
13706 | */ | |
13707 | ||
13708 | static int | |
13709 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
13710 | { | |
13711 | unsigned int offset, size, padding_size; | |
13712 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
13713 | ||
13714 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
13715 | if (!address) | |
13716 | address = fragP->fr_address; | |
13717 | address += fragP->fr_fix; | |
13718 | ||
13719 | /* CMP like instrunction size. */ | |
13720 | size = fragP->tc_frag_data.cmp_size; | |
13721 | ||
13722 | /* The base size of the branch frag. */ | |
13723 | size += branch_fragP->fr_fix; | |
13724 | ||
13725 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
13726 | branch frag. */ | |
13727 | if (branch_fragP->fr_type == rs_machine_dependent) | |
13728 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
13729 | ||
13730 | /* Check if branch is within boundary and doesn't end at the last | |
13731 | byte. */ | |
13732 | offset = address & ((1U << align_branch_power) - 1); | |
13733 | if ((offset + size) >= (1U << align_branch_power)) | |
13734 | /* Padding needed to avoid crossing boundary. */ | |
13735 | padding_size = (1U << align_branch_power) - offset; | |
13736 | else | |
13737 | /* No padding needed. */ | |
13738 | padding_size = 0; | |
13739 | ||
13740 | /* The return value may be saved in tc_frag_data.length which is | |
13741 | unsigned byte. */ | |
13742 | if (!fits_in_unsigned_byte (padding_size)) | |
13743 | abort (); | |
13744 | ||
13745 | return padding_size; | |
13746 | } | |
13747 | ||
13748 | /* i386_generic_table_relax_frag() | |
13749 | ||
13750 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
13751 | grow/shrink padding to align branch frags. Hand others to | |
13752 | relax_frag(). */ | |
13753 | ||
13754 | long | |
13755 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
13756 | { | |
13757 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
13758 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
13759 | { | |
13760 | long padding_size = i386_branch_padding_size (fragP, 0); | |
13761 | long grow = padding_size - fragP->tc_frag_data.length; | |
13762 | ||
13763 | /* When the BRANCH_PREFIX frag is used, the computed address | |
13764 | must match the actual address and there should be no padding. */ | |
13765 | if (fragP->tc_frag_data.padding_address | |
13766 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
13767 | || padding_size)) | |
13768 | abort (); | |
13769 | ||
13770 | /* Update the padding size. */ | |
13771 | if (grow) | |
13772 | fragP->tc_frag_data.length = padding_size; | |
13773 | ||
13774 | return grow; | |
13775 | } | |
13776 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
13777 | { | |
13778 | fragS *padding_fragP, *next_fragP; | |
13779 | long padding_size, left_size, last_size; | |
13780 | ||
13781 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
13782 | if (!padding_fragP) | |
13783 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
13784 | return (fragP->tc_frag_data.length | |
13785 | - fragP->tc_frag_data.last_length); | |
13786 | ||
13787 | /* Compute the relative address of the padding frag in the very | |
13788 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
13789 | if (!fragP->tc_frag_data.padding_address) | |
13790 | fragP->tc_frag_data.padding_address | |
13791 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
13792 | ||
13793 | /* First update the last length from the previous interation. */ | |
13794 | left_size = fragP->tc_frag_data.prefix_length; | |
13795 | for (next_fragP = fragP; | |
13796 | next_fragP != padding_fragP; | |
13797 | next_fragP = next_fragP->fr_next) | |
13798 | if (next_fragP->fr_type == rs_machine_dependent | |
13799 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13800 | == BRANCH_PREFIX)) | |
13801 | { | |
13802 | if (left_size) | |
13803 | { | |
13804 | int max = next_fragP->tc_frag_data.max_bytes; | |
13805 | if (max) | |
13806 | { | |
13807 | int size; | |
13808 | if (max > left_size) | |
13809 | size = left_size; | |
13810 | else | |
13811 | size = max; | |
13812 | left_size -= size; | |
13813 | next_fragP->tc_frag_data.last_length = size; | |
13814 | } | |
13815 | } | |
13816 | else | |
13817 | next_fragP->tc_frag_data.last_length = 0; | |
13818 | } | |
13819 | ||
13820 | /* Check the padding size for the padding frag. */ | |
13821 | padding_size = i386_branch_padding_size | |
13822 | (padding_fragP, (fragP->fr_address | |
13823 | + fragP->tc_frag_data.padding_address)); | |
13824 | ||
13825 | last_size = fragP->tc_frag_data.prefix_length; | |
13826 | /* Check if there is change from the last interation. */ | |
13827 | if (padding_size == last_size) | |
13828 | { | |
13829 | /* Update the expected address of the padding frag. */ | |
13830 | padding_fragP->tc_frag_data.padding_address | |
13831 | = (fragP->fr_address + padding_size | |
13832 | + fragP->tc_frag_data.padding_address); | |
13833 | return 0; | |
13834 | } | |
13835 | ||
13836 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
13837 | { | |
13838 | /* No padding if there is no sufficient room. Clear the | |
13839 | expected address of the padding frag. */ | |
13840 | padding_fragP->tc_frag_data.padding_address = 0; | |
13841 | padding_size = 0; | |
13842 | } | |
13843 | else | |
13844 | /* Store the expected address of the padding frag. */ | |
13845 | padding_fragP->tc_frag_data.padding_address | |
13846 | = (fragP->fr_address + padding_size | |
13847 | + fragP->tc_frag_data.padding_address); | |
13848 | ||
13849 | fragP->tc_frag_data.prefix_length = padding_size; | |
13850 | ||
13851 | /* Update the length for the current interation. */ | |
13852 | left_size = padding_size; | |
13853 | for (next_fragP = fragP; | |
13854 | next_fragP != padding_fragP; | |
13855 | next_fragP = next_fragP->fr_next) | |
13856 | if (next_fragP->fr_type == rs_machine_dependent | |
13857 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13858 | == BRANCH_PREFIX)) | |
13859 | { | |
13860 | if (left_size) | |
13861 | { | |
13862 | int max = next_fragP->tc_frag_data.max_bytes; | |
13863 | if (max) | |
13864 | { | |
13865 | int size; | |
13866 | if (max > left_size) | |
13867 | size = left_size; | |
13868 | else | |
13869 | size = max; | |
13870 | left_size -= size; | |
13871 | next_fragP->tc_frag_data.length = size; | |
13872 | } | |
13873 | } | |
13874 | else | |
13875 | next_fragP->tc_frag_data.length = 0; | |
13876 | } | |
13877 | ||
13878 | return (fragP->tc_frag_data.length | |
13879 | - fragP->tc_frag_data.last_length); | |
13880 | } | |
13881 | return relax_frag (segment, fragP, stretch); | |
13882 | } | |
13883 | ||
ee7fcc42 AM |
13884 | /* md_estimate_size_before_relax() |
13885 | ||
13886 | Called just before relax() for rs_machine_dependent frags. The x86 | |
13887 | assembler uses these frags to handle variable size jump | |
13888 | instructions. | |
13889 | ||
13890 | Any symbol that is now undefined will not become defined. | |
13891 | Return the correct fr_subtype in the frag. | |
13892 | Return the initial "guess for variable size of frag" to caller. | |
13893 | The guess is actually the growth beyond the fixed part. Whatever | |
13894 | we do to grow the fixed or variable part contributes to our | |
13895 | returned value. */ | |
13896 | ||
252b5132 | 13897 | int |
7016a5d5 | 13898 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 13899 | { |
e379e5f3 L |
13900 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
13901 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
13902 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
13903 | { | |
13904 | i386_classify_machine_dependent_frag (fragP); | |
13905 | return fragP->tc_frag_data.length; | |
13906 | } | |
13907 | ||
252b5132 | 13908 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
13909 | check for un-relaxable symbols. On an ELF system, we can't relax |
13910 | an externally visible symbol, because it may be overridden by a | |
13911 | shared library. */ | |
13912 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 13913 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 13914 | || (IS_ELF |
8dcea932 L |
13915 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
13916 | fragP->fr_var)) | |
fbeb56a4 DK |
13917 | #endif |
13918 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 13919 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 13920 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
13921 | #endif |
13922 | ) | |
252b5132 | 13923 | { |
b98ef147 AM |
13924 | /* Symbol is undefined in this segment, or we need to keep a |
13925 | reloc so that weak symbols can be overridden. */ | |
13926 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 13927 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
13928 | unsigned char *opcode; |
13929 | int old_fr_fix; | |
eb19308f | 13930 | fixS *fixP = NULL; |
f6af82bd | 13931 | |
ee7fcc42 | 13932 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 13933 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 13934 | else if (size == 2) |
f6af82bd | 13935 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b | 13936 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
ed719294 JB |
13937 | else if (fragP->tc_frag_data.code == CODE_64BIT |
13938 | && fragP->fr_offset == 0 | |
1ef3994a | 13939 | && need_plt32_p (fragP->fr_symbol)) |
bd7ab16b L |
13940 | reloc_type = BFD_RELOC_X86_64_PLT32; |
13941 | #endif | |
f6af82bd AM |
13942 | else |
13943 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 13944 | |
ee7fcc42 AM |
13945 | old_fr_fix = fragP->fr_fix; |
13946 | opcode = (unsigned char *) fragP->fr_opcode; | |
13947 | ||
fddf5b5b | 13948 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 13949 | { |
fddf5b5b AM |
13950 | case UNCOND_JUMP: |
13951 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 13952 | opcode[0] = 0xe9; |
252b5132 | 13953 | fragP->fr_fix += size; |
eb19308f JB |
13954 | fixP = fix_new (fragP, old_fr_fix, size, |
13955 | fragP->fr_symbol, | |
13956 | fragP->fr_offset, 1, | |
13957 | reloc_type); | |
252b5132 RH |
13958 | break; |
13959 | ||
fddf5b5b | 13960 | case COND_JUMP86: |
412167cb AM |
13961 | if (size == 2 |
13962 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
13963 | { |
13964 | /* Negate the condition, and branch past an | |
13965 | unconditional jump. */ | |
13966 | opcode[0] ^= 1; | |
13967 | opcode[1] = 3; | |
13968 | /* Insert an unconditional jump. */ | |
13969 | opcode[2] = 0xe9; | |
13970 | /* We added two extra opcode bytes, and have a two byte | |
13971 | offset. */ | |
13972 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
13973 | fix_new (fragP, old_fr_fix + 2, 2, |
13974 | fragP->fr_symbol, | |
13975 | fragP->fr_offset, 1, | |
13976 | reloc_type); | |
fddf5b5b AM |
13977 | break; |
13978 | } | |
13979 | /* Fall through. */ | |
13980 | ||
13981 | case COND_JUMP: | |
412167cb AM |
13982 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
13983 | { | |
13984 | fragP->fr_fix += 1; | |
3e02c1cc AM |
13985 | fixP = fix_new (fragP, old_fr_fix, 1, |
13986 | fragP->fr_symbol, | |
13987 | fragP->fr_offset, 1, | |
13988 | BFD_RELOC_8_PCREL); | |
13989 | fixP->fx_signed = 1; | |
412167cb AM |
13990 | break; |
13991 | } | |
93c2a809 | 13992 | |
24eab124 | 13993 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 13994 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 13995 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 13996 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
13997 | /* We've added an opcode byte. */ |
13998 | fragP->fr_fix += 1 + size; | |
eb19308f JB |
13999 | fixP = fix_new (fragP, old_fr_fix + 1, size, |
14000 | fragP->fr_symbol, | |
14001 | fragP->fr_offset, 1, | |
14002 | reloc_type); | |
252b5132 | 14003 | break; |
fddf5b5b AM |
14004 | |
14005 | default: | |
14006 | BAD_CASE (fragP->fr_subtype); | |
14007 | break; | |
252b5132 | 14008 | } |
eb19308f JB |
14009 | |
14010 | /* All jumps handled here are signed, but don't unconditionally use a | |
14011 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
14012 | around at 4G (outside of 64-bit mode) and 64k. */ | |
14013 | if (size == 4 && flag_code == CODE_64BIT) | |
14014 | fixP->fx_signed = 1; | |
14015 | ||
252b5132 | 14016 | frag_wane (fragP); |
ee7fcc42 | 14017 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 14018 | } |
93c2a809 | 14019 | |
93c2a809 AM |
14020 | /* Guess size depending on current relax state. Initially the relax |
14021 | state will correspond to a short jump and we return 1, because | |
14022 | the variable part of the frag (the branch offset) is one byte | |
14023 | long. However, we can relax a section more than once and in that | |
14024 | case we must either set fr_subtype back to the unrelaxed state, | |
14025 | or return the value for the appropriate branch. */ | |
14026 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
14027 | } |
14028 | ||
47926f60 KH |
14029 | /* Called after relax() is finished. |
14030 | ||
14031 | In: Address of frag. | |
14032 | fr_type == rs_machine_dependent. | |
14033 | fr_subtype is what the address relaxed to. | |
14034 | ||
14035 | Out: Any fixSs and constants are set up. | |
14036 | Caller will turn frag into a ".space 0". */ | |
14037 | ||
252b5132 | 14038 | void |
7016a5d5 TG |
14039 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
14040 | fragS *fragP) | |
252b5132 | 14041 | { |
29b0f896 | 14042 | unsigned char *opcode; |
252b5132 | 14043 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
14044 | offsetT target_address; |
14045 | offsetT opcode_address; | |
252b5132 | 14046 | unsigned int extension = 0; |
847f7ad4 | 14047 | offsetT displacement_from_opcode_start; |
252b5132 | 14048 | |
e379e5f3 L |
14049 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
14050 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
14051 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
14052 | { | |
14053 | /* Generate nop padding. */ | |
14054 | unsigned int size = fragP->tc_frag_data.length; | |
14055 | if (size) | |
14056 | { | |
14057 | if (size > fragP->tc_frag_data.max_bytes) | |
14058 | abort (); | |
14059 | ||
14060 | if (flag_debug) | |
14061 | { | |
14062 | const char *msg; | |
14063 | const char *branch = "branch"; | |
14064 | const char *prefix = ""; | |
14065 | fragS *padding_fragP; | |
14066 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
14067 | == BRANCH_PREFIX) | |
14068 | { | |
14069 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
14070 | switch (fragP->tc_frag_data.default_prefix) | |
14071 | { | |
14072 | default: | |
14073 | abort (); | |
14074 | break; | |
14075 | case CS_PREFIX_OPCODE: | |
14076 | prefix = " cs"; | |
14077 | break; | |
14078 | case DS_PREFIX_OPCODE: | |
14079 | prefix = " ds"; | |
14080 | break; | |
14081 | case ES_PREFIX_OPCODE: | |
14082 | prefix = " es"; | |
14083 | break; | |
14084 | case FS_PREFIX_OPCODE: | |
14085 | prefix = " fs"; | |
14086 | break; | |
14087 | case GS_PREFIX_OPCODE: | |
14088 | prefix = " gs"; | |
14089 | break; | |
14090 | case SS_PREFIX_OPCODE: | |
14091 | prefix = " ss"; | |
14092 | break; | |
14093 | } | |
14094 | if (padding_fragP) | |
14095 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
14096 | "%s within %d-byte boundary\n"); | |
14097 | else | |
14098 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
14099 | "align %s within %d-byte boundary\n"); | |
14100 | } | |
14101 | else | |
14102 | { | |
14103 | padding_fragP = fragP; | |
14104 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
14105 | "%s within %d-byte boundary\n"); | |
14106 | } | |
14107 | ||
14108 | if (padding_fragP) | |
14109 | switch (padding_fragP->tc_frag_data.branch_type) | |
14110 | { | |
14111 | case align_branch_jcc: | |
14112 | branch = "jcc"; | |
14113 | break; | |
14114 | case align_branch_fused: | |
14115 | branch = "fused jcc"; | |
14116 | break; | |
14117 | case align_branch_jmp: | |
14118 | branch = "jmp"; | |
14119 | break; | |
14120 | case align_branch_call: | |
14121 | branch = "call"; | |
14122 | break; | |
14123 | case align_branch_indirect: | |
14124 | branch = "indiret branch"; | |
14125 | break; | |
14126 | case align_branch_ret: | |
14127 | branch = "ret"; | |
14128 | break; | |
14129 | default: | |
14130 | break; | |
14131 | } | |
14132 | ||
14133 | fprintf (stdout, msg, | |
14134 | fragP->fr_file, fragP->fr_line, size, prefix, | |
14135 | (long long) fragP->fr_address, branch, | |
14136 | 1 << align_branch_power); | |
14137 | } | |
14138 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
14139 | memset (fragP->fr_opcode, | |
14140 | fragP->tc_frag_data.default_prefix, size); | |
14141 | else | |
14142 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
14143 | size, 0); | |
14144 | fragP->fr_fix += size; | |
14145 | } | |
14146 | return; | |
14147 | } | |
14148 | ||
252b5132 RH |
14149 | opcode = (unsigned char *) fragP->fr_opcode; |
14150 | ||
47926f60 | 14151 | /* Address we want to reach in file space. */ |
252b5132 | 14152 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 14153 | |
47926f60 | 14154 | /* Address opcode resides at in file space. */ |
252b5132 RH |
14155 | opcode_address = fragP->fr_address + fragP->fr_fix; |
14156 | ||
47926f60 | 14157 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
14158 | displacement_from_opcode_start = target_address - opcode_address; |
14159 | ||
fddf5b5b | 14160 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 14161 | { |
47926f60 KH |
14162 | /* Don't have to change opcode. */ |
14163 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 14164 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
14165 | } |
14166 | else | |
14167 | { | |
14168 | if (no_cond_jump_promotion | |
14169 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
14170 | as_warn_where (fragP->fr_file, fragP->fr_line, |
14171 | _("long jump required")); | |
252b5132 | 14172 | |
fddf5b5b AM |
14173 | switch (fragP->fr_subtype) |
14174 | { | |
14175 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
14176 | extension = 4; /* 1 opcode + 4 displacement */ | |
14177 | opcode[0] = 0xe9; | |
14178 | where_to_put_displacement = &opcode[1]; | |
14179 | break; | |
252b5132 | 14180 | |
fddf5b5b AM |
14181 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
14182 | extension = 2; /* 1 opcode + 2 displacement */ | |
14183 | opcode[0] = 0xe9; | |
14184 | where_to_put_displacement = &opcode[1]; | |
14185 | break; | |
252b5132 | 14186 | |
fddf5b5b AM |
14187 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
14188 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
14189 | extension = 5; /* 2 opcode + 4 displacement */ | |
14190 | opcode[1] = opcode[0] + 0x10; | |
14191 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
14192 | where_to_put_displacement = &opcode[2]; | |
14193 | break; | |
252b5132 | 14194 | |
fddf5b5b AM |
14195 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
14196 | extension = 3; /* 2 opcode + 2 displacement */ | |
14197 | opcode[1] = opcode[0] + 0x10; | |
14198 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
14199 | where_to_put_displacement = &opcode[2]; | |
14200 | break; | |
252b5132 | 14201 | |
fddf5b5b AM |
14202 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
14203 | extension = 4; | |
14204 | opcode[0] ^= 1; | |
14205 | opcode[1] = 3; | |
14206 | opcode[2] = 0xe9; | |
14207 | where_to_put_displacement = &opcode[3]; | |
14208 | break; | |
14209 | ||
14210 | default: | |
14211 | BAD_CASE (fragP->fr_subtype); | |
14212 | break; | |
14213 | } | |
252b5132 | 14214 | } |
fddf5b5b | 14215 | |
7b81dfbb AJ |
14216 | /* If size if less then four we are sure that the operand fits, |
14217 | but if it's 4, then it could be that the displacement is larger | |
14218 | then -/+ 2GB. */ | |
14219 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
14220 | && object_64bit | |
14221 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
14222 | + ((addressT) 1 << 31)) |
14223 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
14224 | { |
14225 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
14226 | _("jump target out of range")); | |
14227 | /* Make us emit 0. */ | |
14228 | displacement_from_opcode_start = extension; | |
14229 | } | |
47926f60 | 14230 | /* Now put displacement after opcode. */ |
252b5132 RH |
14231 | md_number_to_chars ((char *) where_to_put_displacement, |
14232 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 14233 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
14234 | fragP->fr_fix += extension; |
14235 | } | |
14236 | \f | |
7016a5d5 | 14237 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
14238 | by our caller that we have all the info we need to fix it up. |
14239 | ||
7016a5d5 TG |
14240 | Parameter valP is the pointer to the value of the bits. |
14241 | ||
252b5132 RH |
14242 | On the 386, immediates, displacements, and data pointers are all in |
14243 | the same (little-endian) format, so we don't need to care about which | |
14244 | we are handling. */ | |
14245 | ||
94f592af | 14246 | void |
7016a5d5 | 14247 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 14248 | { |
94f592af | 14249 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 14250 | valueT value = *valP; |
252b5132 | 14251 | |
f86103b7 | 14252 | #if !defined (TE_Mach) |
93382f6d AM |
14253 | if (fixP->fx_pcrel) |
14254 | { | |
14255 | switch (fixP->fx_r_type) | |
14256 | { | |
5865bb77 ILT |
14257 | default: |
14258 | break; | |
14259 | ||
d6ab8113 JB |
14260 | case BFD_RELOC_64: |
14261 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
14262 | break; | |
93382f6d | 14263 | case BFD_RELOC_32: |
ae8887b5 | 14264 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
14265 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
14266 | break; | |
14267 | case BFD_RELOC_16: | |
14268 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
14269 | break; | |
14270 | case BFD_RELOC_8: | |
14271 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
14272 | break; | |
14273 | } | |
14274 | } | |
252b5132 | 14275 | |
a161fe53 | 14276 | if (fixP->fx_addsy != NULL |
31312f95 | 14277 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 14278 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 14279 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 14280 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 14281 | && !use_rela_relocations) |
252b5132 | 14282 | { |
31312f95 AM |
14283 | /* This is a hack. There should be a better way to handle this. |
14284 | This covers for the fact that bfd_install_relocation will | |
14285 | subtract the current location (for partial_inplace, PC relative | |
14286 | relocations); see more below. */ | |
252b5132 | 14287 | #ifndef OBJ_AOUT |
718ddfc0 | 14288 | if (IS_ELF |
252b5132 RH |
14289 | #ifdef TE_PE |
14290 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
14291 | #endif | |
14292 | ) | |
14293 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
14294 | #endif | |
14295 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 14296 | if (IS_ELF) |
252b5132 | 14297 | { |
6539b54b | 14298 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 14299 | |
6539b54b | 14300 | if ((sym_seg == seg |
2f66722d | 14301 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 14302 | && sym_seg != absolute_section)) |
af65af87 | 14303 | && !generic_force_reloc (fixP)) |
2f66722d AM |
14304 | { |
14305 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
14306 | bfd_install_relocation subtracts them out again. I think |
14307 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
14308 | it. FIXME. */ |
14309 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
14310 | } | |
252b5132 RH |
14311 | } |
14312 | #endif | |
14313 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
14314 | /* For some reason, the PE format does not store a |
14315 | section address offset for a PC relative symbol. */ | |
14316 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 14317 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
14318 | value += md_pcrel_from (fixP); |
14319 | #endif | |
14320 | } | |
fbeb56a4 | 14321 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
14322 | if (fixP->fx_addsy != NULL |
14323 | && S_IS_WEAK (fixP->fx_addsy) | |
14324 | /* PR 16858: Do not modify weak function references. */ | |
14325 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 14326 | { |
296a8689 NC |
14327 | #if !defined (TE_PEP) |
14328 | /* For x86 PE weak function symbols are neither PC-relative | |
14329 | nor do they set S_IS_FUNCTION. So the only reliable way | |
14330 | to detect them is to check the flags of their containing | |
14331 | section. */ | |
14332 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
14333 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
14334 | ; | |
14335 | else | |
14336 | #endif | |
fbeb56a4 DK |
14337 | value -= S_GET_VALUE (fixP->fx_addsy); |
14338 | } | |
14339 | #endif | |
252b5132 RH |
14340 | |
14341 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 14342 | and we must not disappoint it. */ |
252b5132 | 14343 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 14344 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
14345 | switch (fixP->fx_r_type) |
14346 | { | |
14347 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 14348 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
14349 | /* Make the jump instruction point to the address of the operand. |
14350 | At runtime we merely add the offset to the actual PLT entry. | |
14351 | NB: Subtract the offset size only for jump instructions. */ | |
14352 | if (fixP->fx_pcrel) | |
14353 | value = -4; | |
47926f60 | 14354 | break; |
31312f95 | 14355 | |
13ae64f3 JJ |
14356 | case BFD_RELOC_386_TLS_GD: |
14357 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 14358 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
14359 | case BFD_RELOC_386_TLS_IE: |
14360 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 14361 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
14362 | case BFD_RELOC_X86_64_TLSGD: |
14363 | case BFD_RELOC_X86_64_TLSLD: | |
14364 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 14365 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
67a4f2b7 | 14366 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 14367 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
00f7efb6 JJ |
14368 | value = 0; /* Fully resolved at runtime. No addend. */ |
14369 | /* Fallthrough */ | |
14370 | case BFD_RELOC_386_TLS_LE: | |
14371 | case BFD_RELOC_386_TLS_LDO_32: | |
14372 | case BFD_RELOC_386_TLS_LE_32: | |
14373 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 14374 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 14375 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 14376 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
14377 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
14378 | break; | |
14379 | ||
67a4f2b7 AO |
14380 | case BFD_RELOC_386_TLS_DESC_CALL: |
14381 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
14382 | value = 0; /* Fully resolved at runtime. No addend. */ | |
14383 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
14384 | fixP->fx_done = 0; | |
14385 | return; | |
14386 | ||
47926f60 KH |
14387 | case BFD_RELOC_VTABLE_INHERIT: |
14388 | case BFD_RELOC_VTABLE_ENTRY: | |
14389 | fixP->fx_done = 0; | |
94f592af | 14390 | return; |
47926f60 KH |
14391 | |
14392 | default: | |
14393 | break; | |
14394 | } | |
14395 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
a442cac5 JB |
14396 | |
14397 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ | |
14398 | if (!object_64bit) | |
14399 | value = extend_to_32bit_address (value); | |
14400 | ||
c6682705 | 14401 | *valP = value; |
f86103b7 | 14402 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 14403 | |
3e73aa7c | 14404 | /* Are we finished with this relocation now? */ |
c6682705 | 14405 | if (fixP->fx_addsy == NULL) |
b8188555 JB |
14406 | { |
14407 | fixP->fx_done = 1; | |
14408 | switch (fixP->fx_r_type) | |
14409 | { | |
14410 | case BFD_RELOC_X86_64_32S: | |
14411 | fixP->fx_signed = 1; | |
14412 | break; | |
14413 | ||
14414 | default: | |
14415 | break; | |
14416 | } | |
14417 | } | |
fbeb56a4 DK |
14418 | #if defined (OBJ_COFF) && defined (TE_PE) |
14419 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
14420 | { | |
14421 | fixP->fx_done = 0; | |
14422 | /* Remember value for tc_gen_reloc. */ | |
14423 | fixP->fx_addnumber = value; | |
14424 | /* Clear out the frag for now. */ | |
14425 | value = 0; | |
14426 | } | |
14427 | #endif | |
3e73aa7c JH |
14428 | else if (use_rela_relocations) |
14429 | { | |
46fb6d5a JB |
14430 | if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC) |
14431 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
14432 | /* Remember value for tc_gen_reloc. */ |
14433 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
14434 | value = 0; |
14435 | } | |
f86103b7 | 14436 | |
94f592af | 14437 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 14438 | } |
252b5132 | 14439 | \f |
6d4af3c2 | 14440 | const char * |
499ac353 | 14441 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14442 | { |
499ac353 NC |
14443 | /* This outputs the LITTLENUMs in REVERSE order; |
14444 | in accord with the bigendian 386. */ | |
5b7c81bd | 14445 | return ieee_md_atof (type, litP, sizeP, false); |
252b5132 RH |
14446 | } |
14447 | \f | |
2d545b82 | 14448 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 14449 | |
252b5132 | 14450 | static char * |
e3bb37b5 | 14451 | output_invalid (int c) |
252b5132 | 14452 | { |
3882b010 | 14453 | if (ISPRINT (c)) |
f9f21a03 L |
14454 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
14455 | "'%c'", c); | |
252b5132 | 14456 | else |
f9f21a03 | 14457 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 14458 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
14459 | return output_invalid_buf; |
14460 | } | |
14461 | ||
8a6fb3f9 JB |
14462 | /* Verify that @r can be used in the current context. */ |
14463 | ||
5b7c81bd | 14464 | static bool check_register (const reg_entry *r) |
8a6fb3f9 JB |
14465 | { |
14466 | if (allow_pseudo_reg) | |
5b7c81bd | 14467 | return true; |
8a6fb3f9 JB |
14468 | |
14469 | if (operand_type_all_zero (&r->reg_type)) | |
5b7c81bd | 14470 | return false; |
8a6fb3f9 JB |
14471 | |
14472 | if ((r->reg_type.bitfield.dword | |
14473 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
14474 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 14475 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 | 14476 | && !cpu_arch_flags.bitfield.cpui386) |
5b7c81bd | 14477 | return false; |
8a6fb3f9 | 14478 | |
22e00a3f JB |
14479 | if (r->reg_type.bitfield.class == RegTR |
14480 | && (flag_code == CODE_64BIT | |
14481 | || !cpu_arch_flags.bitfield.cpui386 | |
14482 | || cpu_arch_isa_flags.bitfield.cpui586 | |
14483 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
5b7c81bd | 14484 | return false; |
22e00a3f | 14485 | |
8a6fb3f9 | 14486 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
5b7c81bd | 14487 | return false; |
8a6fb3f9 JB |
14488 | |
14489 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
14490 | { | |
14491 | if (r->reg_type.bitfield.zmmword | |
14492 | || r->reg_type.bitfield.class == RegMask) | |
5b7c81bd | 14493 | return false; |
8a6fb3f9 JB |
14494 | |
14495 | if (!cpu_arch_flags.bitfield.cpuavx) | |
14496 | { | |
14497 | if (r->reg_type.bitfield.ymmword) | |
5b7c81bd | 14498 | return false; |
8a6fb3f9 JB |
14499 | |
14500 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
5b7c81bd | 14501 | return false; |
8a6fb3f9 JB |
14502 | } |
14503 | } | |
14504 | ||
a6f3add0 JB |
14505 | if (r->reg_type.bitfield.zmmword) |
14506 | { | |
14507 | if (vector_size < VSZ512) | |
14508 | return false; | |
14509 | ||
14510 | if (i.vec_encoding == vex_encoding_default) | |
14511 | i.vec_encoding = vex_encoding_evex512; | |
14512 | else if (i.vec_encoding != vex_encoding_evex | |
14513 | && i.vec_encoding != vex_encoding_evex512) | |
14514 | i.vec_encoding = vex_encoding_error; | |
14515 | } | |
4fc85f37 JB |
14516 | |
14517 | if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword) | |
14518 | return false; | |
14519 | ||
260cd341 LC |
14520 | if (r->reg_type.bitfield.tmmword |
14521 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
14522 | || flag_code != CODE_64BIT)) | |
5b7c81bd | 14523 | return false; |
260cd341 | 14524 | |
8a6fb3f9 | 14525 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
5b7c81bd | 14526 | return false; |
8a6fb3f9 JB |
14527 | |
14528 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
14529 | if (!allow_index_reg && r->reg_num == RegIZ) | |
5b7c81bd | 14530 | return false; |
8a6fb3f9 JB |
14531 | |
14532 | /* Upper 16 vector registers are only available with VREX in 64bit | |
14533 | mode, and require EVEX encoding. */ | |
14534 | if (r->reg_flags & RegVRex) | |
14535 | { | |
14536 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
14537 | || flag_code != CODE_64BIT) | |
5b7c81bd | 14538 | return false; |
8a6fb3f9 | 14539 | |
a6f3add0 JB |
14540 | if (i.vec_encoding == vex_encoding_default |
14541 | || i.vec_encoding == vex_encoding_evex512) | |
da4977e0 JB |
14542 | i.vec_encoding = vex_encoding_evex; |
14543 | else if (i.vec_encoding != vex_encoding_evex) | |
14544 | i.vec_encoding = vex_encoding_error; | |
8a6fb3f9 JB |
14545 | } |
14546 | ||
80d61d8d CL |
14547 | if (r->reg_flags & RegRex2) |
14548 | { | |
14549 | if (!cpu_arch_flags.bitfield.cpuapx_f | |
14550 | || flag_code != CODE_64BIT) | |
14551 | return false; | |
6177c84d CL |
14552 | |
14553 | i.has_egpr = true; | |
80d61d8d CL |
14554 | } |
14555 | ||
8a6fb3f9 | 14556 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
da5f9eb4 | 14557 | && (!cpu_arch_flags.bitfield.cpu64 |
0ff3b7d0 JB |
14558 | || r->reg_type.bitfield.class != RegCR |
14559 | || dot_insn ()) | |
8a6fb3f9 | 14560 | && flag_code != CODE_64BIT) |
5b7c81bd | 14561 | return false; |
8a6fb3f9 JB |
14562 | |
14563 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
14564 | && !intel_syntax) | |
5b7c81bd | 14565 | return false; |
8a6fb3f9 | 14566 | |
5b7c81bd | 14567 | return true; |
8a6fb3f9 JB |
14568 | } |
14569 | ||
af6bdddf | 14570 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
14571 | |
14572 | static const reg_entry * | |
74e05e01 | 14573 | parse_real_register (const char *reg_string, char **end_op) |
252b5132 | 14574 | { |
74e05e01 | 14575 | const char *s = reg_string; |
af6bdddf | 14576 | char *p; |
252b5132 RH |
14577 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
14578 | const reg_entry *r; | |
14579 | ||
14580 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
14581 | if (*s == REGISTER_PREFIX) | |
14582 | ++s; | |
14583 | ||
14584 | if (is_space_char (*s)) | |
14585 | ++s; | |
14586 | ||
14587 | p = reg_name_given; | |
af6bdddf | 14588 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
14589 | { |
14590 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
14591 | return (const reg_entry *) NULL; |
14592 | s++; | |
252b5132 RH |
14593 | } |
14594 | ||
4795cd4a | 14595 | if (is_part_of_name (*s)) |
6588847e DN |
14596 | return (const reg_entry *) NULL; |
14597 | ||
74e05e01 | 14598 | *end_op = (char *) s; |
252b5132 | 14599 | |
629310ab | 14600 | r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given); |
252b5132 | 14601 | |
5f47d35b | 14602 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
6288d05f | 14603 | if (r == reg_st0) |
5f47d35b | 14604 | { |
0e0eea78 JB |
14605 | if (!cpu_arch_flags.bitfield.cpu8087 |
14606 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
14607 | && !cpu_arch_flags.bitfield.cpu387 |
14608 | && !allow_pseudo_reg) | |
0e0eea78 JB |
14609 | return (const reg_entry *) NULL; |
14610 | ||
5f47d35b AM |
14611 | if (is_space_char (*s)) |
14612 | ++s; | |
14613 | if (*s == '(') | |
14614 | { | |
af6bdddf | 14615 | ++s; |
5f47d35b AM |
14616 | if (is_space_char (*s)) |
14617 | ++s; | |
14618 | if (*s >= '0' && *s <= '7') | |
14619 | { | |
db557034 | 14620 | int fpr = *s - '0'; |
af6bdddf | 14621 | ++s; |
5f47d35b AM |
14622 | if (is_space_char (*s)) |
14623 | ++s; | |
14624 | if (*s == ')') | |
14625 | { | |
74e05e01 | 14626 | *end_op = (char *) s + 1; |
6288d05f | 14627 | know (r[fpr].reg_num == fpr); |
db557034 | 14628 | return r + fpr; |
5f47d35b | 14629 | } |
5f47d35b | 14630 | } |
47926f60 | 14631 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
14632 | return (const reg_entry *) NULL; |
14633 | } | |
14634 | } | |
14635 | ||
8a6fb3f9 | 14636 | return r && check_register (r) ? r : NULL; |
252b5132 | 14637 | } |
4d1bb795 JB |
14638 | |
14639 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
14640 | ||
14641 | static const reg_entry * | |
4f081312 | 14642 | parse_register (const char *reg_string, char **end_op) |
4d1bb795 JB |
14643 | { |
14644 | const reg_entry *r; | |
14645 | ||
14646 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
14647 | r = parse_real_register (reg_string, end_op); | |
14648 | else | |
14649 | r = NULL; | |
14650 | if (!r) | |
14651 | { | |
14652 | char *save = input_line_pointer; | |
4f081312 | 14653 | char *buf = xstrdup (reg_string), *name; |
4d1bb795 JB |
14654 | symbolS *symbolP; |
14655 | ||
4f081312 JB |
14656 | input_line_pointer = buf; |
14657 | get_symbol_name (&name); | |
14658 | symbolP = symbol_find (name); | |
d50c498a | 14659 | while (symbolP && symbol_equated_p (symbolP)) |
64d23078 JB |
14660 | { |
14661 | const expressionS *e = symbol_get_value_expression(symbolP); | |
14662 | ||
d50c498a | 14663 | if (e->X_add_number) |
64d23078 JB |
14664 | break; |
14665 | symbolP = e->X_add_symbol; | |
14666 | } | |
4d1bb795 JB |
14667 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
14668 | { | |
14669 | const expressionS *e = symbol_get_value_expression (symbolP); | |
14670 | ||
0ccade1a JB |
14671 | if (e->X_op == O_register) |
14672 | { | |
14673 | know (e->X_add_number >= 0 | |
14674 | && (valueT) e->X_add_number < i386_regtab_size); | |
14675 | r = i386_regtab + e->X_add_number; | |
4f081312 | 14676 | *end_op = (char *) reg_string + (input_line_pointer - buf); |
0ccade1a JB |
14677 | } |
14678 | if (r && !check_register (r)) | |
8a6fb3f9 | 14679 | { |
3b55a1d0 JB |
14680 | as_bad (_("register '%s%s' cannot be used here"), |
14681 | register_prefix, r->reg_name); | |
14682 | r = &bad_reg; | |
8a6fb3f9 | 14683 | } |
4d1bb795 | 14684 | } |
4d1bb795 | 14685 | input_line_pointer = save; |
4f081312 | 14686 | free (buf); |
4d1bb795 JB |
14687 | } |
14688 | return r; | |
14689 | } | |
14690 | ||
14691 | int | |
14692 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
14693 | { | |
4faaa10f | 14694 | const reg_entry *r = NULL; |
4d1bb795 JB |
14695 | char *end = input_line_pointer; |
14696 | ||
6acf9130 JB |
14697 | /* We only know the terminating character here. It being double quote could |
14698 | be the closing one of a quoted symbol name, or an opening one from a | |
14699 | following string (or another quoted symbol name). Since the latter can't | |
14700 | be valid syntax for anything, bailing in either case is good enough. */ | |
14701 | if (*nextcharP == '"') | |
14702 | return 0; | |
14703 | ||
4d1bb795 | 14704 | *end = *nextcharP; |
4faaa10f JB |
14705 | if (*name == REGISTER_PREFIX || allow_naked_reg) |
14706 | r = parse_real_register (name, &input_line_pointer); | |
4d1bb795 JB |
14707 | if (r && end <= input_line_pointer) |
14708 | { | |
14709 | *nextcharP = *input_line_pointer; | |
14710 | *input_line_pointer = 0; | |
f847749a JB |
14711 | e->X_op = O_register; |
14712 | e->X_add_number = r - i386_regtab; | |
4d1bb795 JB |
14713 | return 1; |
14714 | } | |
14715 | input_line_pointer = end; | |
14716 | *end = 0; | |
ee86248c | 14717 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
14718 | } |
14719 | ||
14720 | void | |
14721 | md_operand (expressionS *e) | |
14722 | { | |
ee86248c JB |
14723 | char *end; |
14724 | const reg_entry *r; | |
4d1bb795 | 14725 | |
ee86248c JB |
14726 | switch (*input_line_pointer) |
14727 | { | |
14728 | case REGISTER_PREFIX: | |
14729 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
14730 | if (r) |
14731 | { | |
14732 | e->X_op = O_register; | |
14733 | e->X_add_number = r - i386_regtab; | |
14734 | input_line_pointer = end; | |
14735 | } | |
ee86248c JB |
14736 | break; |
14737 | ||
14738 | case '[': | |
9c2799c2 | 14739 | gas_assert (intel_syntax); |
ee86248c JB |
14740 | end = input_line_pointer++; |
14741 | expression (e); | |
14742 | if (*input_line_pointer == ']') | |
14743 | { | |
14744 | ++input_line_pointer; | |
14745 | e->X_op_symbol = make_expr_symbol (e); | |
14746 | e->X_add_symbol = NULL; | |
14747 | e->X_add_number = 0; | |
14748 | e->X_op = O_index; | |
14749 | } | |
14750 | else | |
14751 | { | |
14752 | e->X_op = O_absent; | |
14753 | input_line_pointer = end; | |
14754 | } | |
14755 | break; | |
4d1bb795 JB |
14756 | } |
14757 | } | |
14758 | ||
5cc00775 JB |
14759 | #ifdef BFD64 |
14760 | /* To maintain consistency with !BFD64 builds of gas record, whether any | |
14761 | (binary) operator was involved in an expression. As expressions are | |
14762 | evaluated in only 32 bits when !BFD64, we use this to decide whether to | |
14763 | truncate results. */ | |
14764 | bool i386_record_operator (operatorT op, | |
14765 | const expressionS *left, | |
14766 | const expressionS *right) | |
14767 | { | |
14768 | if (op == O_absent) | |
14769 | return false; | |
14770 | ||
14771 | if (!left) | |
14772 | { | |
14773 | /* Since the expression parser applies unary operators fine to bignum | |
14774 | operands, we don't need to be concerned of respective operands not | |
14775 | fitting in 32 bits. */ | |
14776 | if (right->X_op == O_constant && right->X_unsigned | |
14777 | && !fits_in_unsigned_long (right->X_add_number)) | |
14778 | return false; | |
14779 | } | |
14780 | /* This isn't entirely right: The pattern can also result when constant | |
14781 | expressions are folded (e.g. 0xffffffff + 1). */ | |
14782 | else if ((left->X_op == O_constant && left->X_unsigned | |
14783 | && !fits_in_unsigned_long (left->X_add_number)) | |
14784 | || (right->X_op == O_constant && right->X_unsigned | |
14785 | && !fits_in_unsigned_long (right->X_add_number))) | |
14786 | expr_mode = expr_large_value; | |
14787 | ||
14788 | if (expr_mode != expr_large_value) | |
14789 | expr_mode = expr_operator_present; | |
14790 | ||
14791 | return false; | |
14792 | } | |
14793 | #endif | |
252b5132 | 14794 | \f |
4cc782b5 | 14795 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 14796 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 14797 | #else |
b6f8c7c4 | 14798 | const char *md_shortopts = "qnO::"; |
252b5132 | 14799 | #endif |
6e0b89ee | 14800 | |
3e73aa7c | 14801 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
14802 | #define OPTION_64 (OPTION_MD_BASE + 1) |
14803 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
14804 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
14805 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
14806 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
14807 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
14808 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
14809 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 14810 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 14811 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 14812 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
14813 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
14814 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
14815 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 14816 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
14817 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
14818 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 14819 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 14820 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 14821 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 14822 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
14823 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
14824 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 14825 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 14826 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 14827 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
14828 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
14829 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
14830 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 14831 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
14832 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
14833 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
14834 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
c8480b58 | 14835 | #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34) |
b3b91714 | 14836 | |
99ad8390 NC |
14837 | struct option md_longopts[] = |
14838 | { | |
3e73aa7c | 14839 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 14840 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 14841 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 14842 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
14843 | #endif |
14844 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 14845 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 14846 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 14847 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 14848 | #endif |
b3b91714 | 14849 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
14850 | {"march", required_argument, NULL, OPTION_MARCH}, |
14851 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
14852 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
14853 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
14854 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
14855 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 14856 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
c8480b58 | 14857 | {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE}, |
daf50ae7 | 14858 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 14859 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 14860 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 14861 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 14862 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
14863 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
14864 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
14865 | # if defined (TE_PE) || defined (TE_PEP) |
14866 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
14867 | #endif | |
d1982f93 | 14868 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 14869 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 14870 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 14871 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
14872 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
14873 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
14874 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 14875 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
14876 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
14877 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
14878 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
14879 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
14880 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
14881 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
14882 | {NULL, no_argument, NULL, 0} |
14883 | }; | |
14884 | size_t md_longopts_size = sizeof (md_longopts); | |
14885 | ||
14886 | int | |
17b9d67d | 14887 | md_parse_option (int c, const char *arg) |
252b5132 | 14888 | { |
91d6fa6a | 14889 | unsigned int j; |
e379e5f3 | 14890 | char *arch, *next, *saved, *type; |
9103f4f4 | 14891 | |
252b5132 RH |
14892 | switch (c) |
14893 | { | |
12b55ccc L |
14894 | case 'n': |
14895 | optimize_align_code = 0; | |
14896 | break; | |
14897 | ||
a38cf1db AM |
14898 | case 'q': |
14899 | quiet_warnings = 1; | |
252b5132 RH |
14900 | break; |
14901 | ||
14902 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
14903 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
14904 | should be emitted or not. FIXME: Not implemented. */ | |
14905 | case 'Q': | |
d4693039 JB |
14906 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
14907 | return 0; | |
252b5132 RH |
14908 | break; |
14909 | ||
14910 | /* -V: SVR4 argument to print version ID. */ | |
14911 | case 'V': | |
14912 | print_version_id (); | |
14913 | break; | |
14914 | ||
a38cf1db AM |
14915 | /* -k: Ignore for FreeBSD compatibility. */ |
14916 | case 'k': | |
252b5132 | 14917 | break; |
4cc782b5 ILT |
14918 | |
14919 | case 's': | |
14920 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 14921 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 14922 | break; |
8dcea932 L |
14923 | |
14924 | case OPTION_MSHARED: | |
14925 | shared = 1; | |
14926 | break; | |
b4a3a7b4 L |
14927 | |
14928 | case OPTION_X86_USED_NOTE: | |
14929 | if (strcasecmp (arg, "yes") == 0) | |
14930 | x86_used_note = 1; | |
14931 | else if (strcasecmp (arg, "no") == 0) | |
14932 | x86_used_note = 0; | |
14933 | else | |
14934 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
14935 | break; | |
14936 | ||
14937 | ||
99ad8390 | 14938 | #endif |
321098a5 | 14939 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 14940 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
14941 | case OPTION_64: |
14942 | { | |
14943 | const char **list, **l; | |
14944 | ||
3e73aa7c JH |
14945 | list = bfd_target_list (); |
14946 | for (l = list; *l != NULL; l++) | |
08dedd66 | 14947 | if (startswith (*l, "elf64-x86-64") |
99ad8390 NC |
14948 | || strcmp (*l, "coff-x86-64") == 0 |
14949 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
14950 | || strcmp (*l, "pei-x86-64") == 0 |
14951 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
14952 | { |
14953 | default_arch = "x86_64"; | |
14954 | break; | |
14955 | } | |
3e73aa7c | 14956 | if (*l == NULL) |
2b5d6a91 | 14957 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
14958 | free (list); |
14959 | } | |
14960 | break; | |
14961 | #endif | |
252b5132 | 14962 | |
351f65ca | 14963 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 14964 | case OPTION_X32: |
351f65ca L |
14965 | if (IS_ELF) |
14966 | { | |
14967 | const char **list, **l; | |
14968 | ||
14969 | list = bfd_target_list (); | |
14970 | for (l = list; *l != NULL; l++) | |
08dedd66 | 14971 | if (startswith (*l, "elf32-x86-64")) |
351f65ca L |
14972 | { |
14973 | default_arch = "x86_64:32"; | |
14974 | break; | |
14975 | } | |
14976 | if (*l == NULL) | |
2b5d6a91 | 14977 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
14978 | free (list); |
14979 | } | |
14980 | else | |
14981 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
14982 | break; | |
14983 | #endif | |
14984 | ||
6e0b89ee | 14985 | case OPTION_32: |
590a0fed JB |
14986 | { |
14987 | const char **list, **l; | |
14988 | ||
14989 | list = bfd_target_list (); | |
14990 | for (l = list; *l != NULL; l++) | |
14991 | if (strstr (*l, "-i386") | |
14992 | || strstr (*l, "-go32")) | |
14993 | { | |
14994 | default_arch = "i386"; | |
14995 | break; | |
14996 | } | |
14997 | if (*l == NULL) | |
14998 | as_fatal (_("no compiled in support for ix86")); | |
14999 | free (list); | |
15000 | } | |
6e0b89ee AM |
15001 | break; |
15002 | ||
b3b91714 AM |
15003 | case OPTION_DIVIDE: |
15004 | #ifdef SVR4_COMMENT_CHARS | |
15005 | { | |
15006 | char *n, *t; | |
15007 | const char *s; | |
15008 | ||
add39d23 | 15009 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
15010 | t = n; |
15011 | for (s = i386_comment_chars; *s != '\0'; s++) | |
15012 | if (*s != '/') | |
15013 | *t++ = *s; | |
15014 | *t = '\0'; | |
15015 | i386_comment_chars = n; | |
15016 | } | |
15017 | #endif | |
15018 | break; | |
15019 | ||
9103f4f4 | 15020 | case OPTION_MARCH: |
293f5f65 L |
15021 | saved = xstrdup (arg); |
15022 | arch = saved; | |
15023 | /* Allow -march=+nosse. */ | |
15024 | if (*arch == '+') | |
15025 | arch++; | |
6305a203 | 15026 | do |
9103f4f4 | 15027 | { |
4fc85f37 JB |
15028 | char *vsz; |
15029 | ||
6305a203 | 15030 | if (*arch == '.') |
2b5d6a91 | 15031 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
15032 | next = strchr (arch, '+'); |
15033 | if (next) | |
15034 | *next++ = '\0'; | |
4fc85f37 JB |
15035 | vsz = strchr (arch, '/'); |
15036 | if (vsz) | |
15037 | *vsz++ = '\0'; | |
91d6fa6a | 15038 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 15039 | { |
4fc85f37 JB |
15040 | if (vsz && cpu_arch[j].vsz != vsz_set) |
15041 | continue; | |
15042 | ||
ae89daec JB |
15043 | if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE |
15044 | && strcmp (arch, cpu_arch[j].name) == 0) | |
ccc9c027 | 15045 | { |
6305a203 | 15046 | /* Processor. */ |
ae89daec | 15047 | if (! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
15048 | continue; |
15049 | ||
91d6fa6a | 15050 | cpu_arch_name = cpu_arch[j].name; |
d92c7521 | 15051 | free (cpu_sub_arch_name); |
6305a203 | 15052 | cpu_sub_arch_name = NULL; |
ae89daec | 15053 | cpu_arch_flags = cpu_arch[j].enable; |
91d6fa6a | 15054 | cpu_arch_isa = cpu_arch[j].type; |
ae89daec | 15055 | cpu_arch_isa_flags = cpu_arch[j].enable; |
6305a203 | 15056 | if (!cpu_arch_tune_set) |
fb263707 | 15057 | cpu_arch_tune = cpu_arch_isa; |
4fc85f37 | 15058 | vector_size = VSZ_DEFAULT; |
6305a203 L |
15059 | break; |
15060 | } | |
ae89daec JB |
15061 | else if (cpu_arch[j].type == PROCESSOR_NONE |
15062 | && strcmp (arch, cpu_arch[j].name) == 0 | |
15063 | && !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
6305a203 | 15064 | { |
33eaf5de | 15065 | /* ISA extension. */ |
bd483d21 | 15066 | isa_enable (j); |
4fc85f37 JB |
15067 | |
15068 | switch (cpu_arch[j].vsz) | |
15069 | { | |
15070 | default: | |
15071 | break; | |
15072 | ||
15073 | case vsz_set: | |
15074 | if (vsz) | |
15075 | { | |
15076 | char *end; | |
15077 | unsigned long val = strtoul (vsz, &end, 0); | |
15078 | ||
15079 | if (*end) | |
15080 | val = 0; | |
15081 | switch (val) | |
15082 | { | |
15083 | case 512: vector_size = VSZ512; break; | |
15084 | case 256: vector_size = VSZ256; break; | |
15085 | case 128: vector_size = VSZ128; break; | |
15086 | default: | |
15087 | as_warn (_("Unrecognized vector size specifier ignored")); | |
15088 | break; | |
15089 | } | |
15090 | break; | |
15091 | } | |
15092 | /* Fall through. */ | |
15093 | case vsz_reset: | |
15094 | vector_size = VSZ_DEFAULT; | |
15095 | break; | |
15096 | } | |
15097 | ||
6305a203 | 15098 | break; |
ccc9c027 | 15099 | } |
9103f4f4 | 15100 | } |
6305a203 | 15101 | |
ae89daec | 15102 | if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no")) |
293f5f65 | 15103 | { |
33eaf5de | 15104 | /* Disable an ISA extension. */ |
ae89daec JB |
15105 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
15106 | if (cpu_arch[j].type == PROCESSOR_NONE | |
15107 | && strcmp (arch + 2, cpu_arch[j].name) == 0) | |
293f5f65 | 15108 | { |
bd483d21 | 15109 | isa_disable (j); |
4fc85f37 JB |
15110 | if (cpu_arch[j].vsz == vsz_set) |
15111 | vector_size = VSZ_DEFAULT; | |
293f5f65 L |
15112 | break; |
15113 | } | |
293f5f65 L |
15114 | } |
15115 | ||
91d6fa6a | 15116 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 15117 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
15118 | |
15119 | arch = next; | |
9103f4f4 | 15120 | } |
293f5f65 L |
15121 | while (next != NULL); |
15122 | free (saved); | |
9103f4f4 L |
15123 | break; |
15124 | ||
15125 | case OPTION_MTUNE: | |
15126 | if (*arg == '.') | |
2b5d6a91 | 15127 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 15128 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 15129 | { |
ae89daec JB |
15130 | if (cpu_arch[j].type != PROCESSOR_NONE |
15131 | && strcmp (arg, cpu_arch[j].name) == 0) | |
9103f4f4 | 15132 | { |
ccc9c027 | 15133 | cpu_arch_tune_set = 1; |
91d6fa6a | 15134 | cpu_arch_tune = cpu_arch [j].type; |
9103f4f4 L |
15135 | break; |
15136 | } | |
15137 | } | |
91d6fa6a | 15138 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 15139 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
15140 | break; |
15141 | ||
1efbbeb4 L |
15142 | case OPTION_MMNEMONIC: |
15143 | if (strcasecmp (arg, "att") == 0) | |
15144 | intel_mnemonic = 0; | |
15145 | else if (strcasecmp (arg, "intel") == 0) | |
15146 | intel_mnemonic = 1; | |
15147 | else | |
2b5d6a91 | 15148 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
15149 | break; |
15150 | ||
15151 | case OPTION_MSYNTAX: | |
15152 | if (strcasecmp (arg, "att") == 0) | |
15153 | intel_syntax = 0; | |
15154 | else if (strcasecmp (arg, "intel") == 0) | |
15155 | intel_syntax = 1; | |
15156 | else | |
2b5d6a91 | 15157 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
15158 | break; |
15159 | ||
15160 | case OPTION_MINDEX_REG: | |
15161 | allow_index_reg = 1; | |
15162 | break; | |
15163 | ||
15164 | case OPTION_MNAKED_REG: | |
15165 | allow_naked_reg = 1; | |
15166 | break; | |
15167 | ||
c0f3af97 L |
15168 | case OPTION_MSSE2AVX: |
15169 | sse2avx = 1; | |
15170 | break; | |
15171 | ||
c8480b58 L |
15172 | case OPTION_MUSE_UNALIGNED_VECTOR_MOVE: |
15173 | use_unaligned_vector_move = 1; | |
15174 | break; | |
15175 | ||
daf50ae7 L |
15176 | case OPTION_MSSE_CHECK: |
15177 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 15178 | sse_check = check_error; |
daf50ae7 | 15179 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 15180 | sse_check = check_warning; |
daf50ae7 | 15181 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 15182 | sse_check = check_none; |
daf50ae7 | 15183 | else |
2b5d6a91 | 15184 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
15185 | break; |
15186 | ||
7bab8ab5 JB |
15187 | case OPTION_MOPERAND_CHECK: |
15188 | if (strcasecmp (arg, "error") == 0) | |
15189 | operand_check = check_error; | |
15190 | else if (strcasecmp (arg, "warning") == 0) | |
15191 | operand_check = check_warning; | |
15192 | else if (strcasecmp (arg, "none") == 0) | |
15193 | operand_check = check_none; | |
15194 | else | |
15195 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
15196 | break; | |
15197 | ||
539f890d L |
15198 | case OPTION_MAVXSCALAR: |
15199 | if (strcasecmp (arg, "128") == 0) | |
15200 | avxscalar = vex128; | |
15201 | else if (strcasecmp (arg, "256") == 0) | |
15202 | avxscalar = vex256; | |
15203 | else | |
2b5d6a91 | 15204 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
15205 | break; |
15206 | ||
03751133 L |
15207 | case OPTION_MVEXWIG: |
15208 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 15209 | vexwig = vexw0; |
03751133 | 15210 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 15211 | vexwig = vexw1; |
03751133 L |
15212 | else |
15213 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
15214 | break; | |
15215 | ||
7e8b059b L |
15216 | case OPTION_MADD_BND_PREFIX: |
15217 | add_bnd_prefix = 1; | |
15218 | break; | |
15219 | ||
43234a1e L |
15220 | case OPTION_MEVEXLIG: |
15221 | if (strcmp (arg, "128") == 0) | |
15222 | evexlig = evexl128; | |
15223 | else if (strcmp (arg, "256") == 0) | |
15224 | evexlig = evexl256; | |
15225 | else if (strcmp (arg, "512") == 0) | |
15226 | evexlig = evexl512; | |
15227 | else | |
15228 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
15229 | break; | |
15230 | ||
d3d3c6db IT |
15231 | case OPTION_MEVEXRCIG: |
15232 | if (strcmp (arg, "rne") == 0) | |
15233 | evexrcig = rne; | |
15234 | else if (strcmp (arg, "rd") == 0) | |
15235 | evexrcig = rd; | |
15236 | else if (strcmp (arg, "ru") == 0) | |
15237 | evexrcig = ru; | |
15238 | else if (strcmp (arg, "rz") == 0) | |
15239 | evexrcig = rz; | |
15240 | else | |
15241 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
15242 | break; | |
15243 | ||
43234a1e L |
15244 | case OPTION_MEVEXWIG: |
15245 | if (strcmp (arg, "0") == 0) | |
15246 | evexwig = evexw0; | |
15247 | else if (strcmp (arg, "1") == 0) | |
15248 | evexwig = evexw1; | |
15249 | else | |
15250 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
15251 | break; | |
15252 | ||
167ad85b TG |
15253 | # if defined (TE_PE) || defined (TE_PEP) |
15254 | case OPTION_MBIG_OBJ: | |
15255 | use_big_obj = 1; | |
15256 | break; | |
15257 | #endif | |
15258 | ||
d1982f93 | 15259 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
15260 | if (strcasecmp (arg, "yes") == 0) |
15261 | omit_lock_prefix = 1; | |
15262 | else if (strcasecmp (arg, "no") == 0) | |
15263 | omit_lock_prefix = 0; | |
15264 | else | |
15265 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
15266 | break; | |
15267 | ||
e4e00185 AS |
15268 | case OPTION_MFENCE_AS_LOCK_ADD: |
15269 | if (strcasecmp (arg, "yes") == 0) | |
15270 | avoid_fence = 1; | |
15271 | else if (strcasecmp (arg, "no") == 0) | |
15272 | avoid_fence = 0; | |
15273 | else | |
15274 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
15275 | break; | |
15276 | ||
ae531041 L |
15277 | case OPTION_MLFENCE_AFTER_LOAD: |
15278 | if (strcasecmp (arg, "yes") == 0) | |
15279 | lfence_after_load = 1; | |
15280 | else if (strcasecmp (arg, "no") == 0) | |
15281 | lfence_after_load = 0; | |
15282 | else | |
15283 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
15284 | break; | |
15285 | ||
15286 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
15287 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 15288 | { |
15289 | lfence_before_indirect_branch = lfence_branch_all; | |
15290 | if (lfence_before_ret == lfence_before_ret_none) | |
15291 | lfence_before_ret = lfence_before_ret_shl; | |
15292 | } | |
ae531041 L |
15293 | else if (strcasecmp (arg, "memory") == 0) |
15294 | lfence_before_indirect_branch = lfence_branch_memory; | |
15295 | else if (strcasecmp (arg, "register") == 0) | |
15296 | lfence_before_indirect_branch = lfence_branch_register; | |
15297 | else if (strcasecmp (arg, "none") == 0) | |
15298 | lfence_before_indirect_branch = lfence_branch_none; | |
15299 | else | |
15300 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
15301 | arg); | |
15302 | break; | |
15303 | ||
15304 | case OPTION_MLFENCE_BEFORE_RET: | |
15305 | if (strcasecmp (arg, "or") == 0) | |
15306 | lfence_before_ret = lfence_before_ret_or; | |
15307 | else if (strcasecmp (arg, "not") == 0) | |
15308 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 15309 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
15310 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
15311 | else if (strcasecmp (arg, "none") == 0) |
15312 | lfence_before_ret = lfence_before_ret_none; | |
15313 | else | |
15314 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
15315 | arg); | |
15316 | break; | |
15317 | ||
0cb4071e L |
15318 | case OPTION_MRELAX_RELOCATIONS: |
15319 | if (strcasecmp (arg, "yes") == 0) | |
15320 | generate_relax_relocations = 1; | |
15321 | else if (strcasecmp (arg, "no") == 0) | |
15322 | generate_relax_relocations = 0; | |
15323 | else | |
15324 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
15325 | break; | |
15326 | ||
e379e5f3 L |
15327 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
15328 | { | |
15329 | char *end; | |
15330 | long int align = strtoul (arg, &end, 0); | |
15331 | if (*end == '\0') | |
15332 | { | |
15333 | if (align == 0) | |
15334 | { | |
15335 | align_branch_power = 0; | |
15336 | break; | |
15337 | } | |
15338 | else if (align >= 16) | |
15339 | { | |
15340 | int align_power; | |
15341 | for (align_power = 0; | |
15342 | (align & 1) == 0; | |
15343 | align >>= 1, align_power++) | |
15344 | continue; | |
15345 | /* Limit alignment power to 31. */ | |
15346 | if (align == 1 && align_power < 32) | |
15347 | { | |
15348 | align_branch_power = align_power; | |
15349 | break; | |
15350 | } | |
15351 | } | |
15352 | } | |
15353 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
15354 | } | |
15355 | break; | |
15356 | ||
15357 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
15358 | { | |
15359 | char *end; | |
15360 | int align = strtoul (arg, &end, 0); | |
15361 | /* Some processors only support 5 prefixes. */ | |
15362 | if (*end == '\0' && align >= 0 && align < 6) | |
15363 | { | |
15364 | align_branch_prefix_size = align; | |
15365 | break; | |
15366 | } | |
15367 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
15368 | arg); | |
15369 | } | |
15370 | break; | |
15371 | ||
15372 | case OPTION_MALIGN_BRANCH: | |
15373 | align_branch = 0; | |
15374 | saved = xstrdup (arg); | |
15375 | type = saved; | |
15376 | do | |
15377 | { | |
15378 | next = strchr (type, '+'); | |
15379 | if (next) | |
15380 | *next++ = '\0'; | |
15381 | if (strcasecmp (type, "jcc") == 0) | |
15382 | align_branch |= align_branch_jcc_bit; | |
15383 | else if (strcasecmp (type, "fused") == 0) | |
15384 | align_branch |= align_branch_fused_bit; | |
15385 | else if (strcasecmp (type, "jmp") == 0) | |
15386 | align_branch |= align_branch_jmp_bit; | |
15387 | else if (strcasecmp (type, "call") == 0) | |
15388 | align_branch |= align_branch_call_bit; | |
15389 | else if (strcasecmp (type, "ret") == 0) | |
15390 | align_branch |= align_branch_ret_bit; | |
15391 | else if (strcasecmp (type, "indirect") == 0) | |
15392 | align_branch |= align_branch_indirect_bit; | |
15393 | else | |
15394 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
15395 | type = next; | |
15396 | } | |
15397 | while (next != NULL); | |
15398 | free (saved); | |
15399 | break; | |
15400 | ||
76cf450b L |
15401 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
15402 | align_branch_power = 5; | |
15403 | align_branch_prefix_size = 5; | |
15404 | align_branch = (align_branch_jcc_bit | |
15405 | | align_branch_fused_bit | |
15406 | | align_branch_jmp_bit); | |
15407 | break; | |
15408 | ||
5db04b09 | 15409 | case OPTION_MAMD64: |
4b5aaf5f | 15410 | isa64 = amd64; |
5db04b09 L |
15411 | break; |
15412 | ||
15413 | case OPTION_MINTEL64: | |
4b5aaf5f | 15414 | isa64 = intel64; |
5db04b09 L |
15415 | break; |
15416 | ||
b6f8c7c4 L |
15417 | case 'O': |
15418 | if (arg == NULL) | |
15419 | { | |
15420 | optimize = 1; | |
15421 | /* Turn off -Os. */ | |
15422 | optimize_for_space = 0; | |
15423 | } | |
15424 | else if (*arg == 's') | |
15425 | { | |
15426 | optimize_for_space = 1; | |
15427 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 15428 | optimize = INT_MAX; |
b6f8c7c4 L |
15429 | } |
15430 | else | |
15431 | { | |
15432 | optimize = atoi (arg); | |
15433 | /* Turn off -Os. */ | |
15434 | optimize_for_space = 0; | |
15435 | } | |
15436 | break; | |
15437 | ||
252b5132 RH |
15438 | default: |
15439 | return 0; | |
15440 | } | |
15441 | return 1; | |
15442 | } | |
15443 | ||
8a2c8fef L |
15444 | #define MESSAGE_TEMPLATE \ |
15445 | " " | |
15446 | ||
293f5f65 L |
15447 | static char * |
15448 | output_message (FILE *stream, char *p, char *message, char *start, | |
15449 | int *left_p, const char *name, int len) | |
15450 | { | |
15451 | int size = sizeof (MESSAGE_TEMPLATE); | |
15452 | int left = *left_p; | |
15453 | ||
15454 | /* Reserve 2 spaces for ", " or ",\0" */ | |
15455 | left -= len + 2; | |
15456 | ||
15457 | /* Check if there is any room. */ | |
15458 | if (left >= 0) | |
15459 | { | |
15460 | if (p != start) | |
15461 | { | |
15462 | *p++ = ','; | |
15463 | *p++ = ' '; | |
15464 | } | |
15465 | p = mempcpy (p, name, len); | |
15466 | } | |
15467 | else | |
15468 | { | |
15469 | /* Output the current message now and start a new one. */ | |
15470 | *p++ = ','; | |
15471 | *p = '\0'; | |
15472 | fprintf (stream, "%s\n", message); | |
15473 | p = start; | |
15474 | left = size - (start - message) - len - 2; | |
15475 | ||
15476 | gas_assert (left >= 0); | |
15477 | ||
15478 | p = mempcpy (p, name, len); | |
15479 | } | |
15480 | ||
15481 | *left_p = left; | |
15482 | return p; | |
15483 | } | |
15484 | ||
8a2c8fef | 15485 | static void |
1ded5609 | 15486 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
15487 | { |
15488 | static char message[] = MESSAGE_TEMPLATE; | |
15489 | char *start = message + 27; | |
15490 | char *p; | |
15491 | int size = sizeof (MESSAGE_TEMPLATE); | |
15492 | int left; | |
15493 | const char *name; | |
15494 | int len; | |
15495 | unsigned int j; | |
15496 | ||
15497 | p = start; | |
15498 | left = size - (start - message); | |
3ce2ebcf JB |
15499 | |
15500 | if (!ext && check) | |
15501 | { | |
15502 | p = output_message (stream, p, message, start, &left, | |
15503 | STRING_COMMA_LEN ("default")); | |
f68697e8 JB |
15504 | p = output_message (stream, p, message, start, &left, |
15505 | STRING_COMMA_LEN ("push")); | |
15506 | p = output_message (stream, p, message, start, &left, | |
15507 | STRING_COMMA_LEN ("pop")); | |
3ce2ebcf JB |
15508 | } |
15509 | ||
8a2c8fef L |
15510 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
15511 | { | |
15512 | /* Should it be skipped? */ | |
15513 | if (cpu_arch [j].skip) | |
15514 | continue; | |
15515 | ||
15516 | name = cpu_arch [j].name; | |
15517 | len = cpu_arch [j].len; | |
ae89daec | 15518 | if (cpu_arch[j].type == PROCESSOR_NONE) |
8a2c8fef L |
15519 | { |
15520 | /* It is an extension. Skip if we aren't asked to show it. */ | |
ae89daec | 15521 | if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable)) |
8a2c8fef L |
15522 | continue; |
15523 | } | |
15524 | else if (ext) | |
15525 | { | |
15526 | /* It is an processor. Skip if we show only extension. */ | |
15527 | continue; | |
15528 | } | |
ae89daec | 15529 | else if (check && ! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
15530 | { |
15531 | /* It is an impossible processor - skip. */ | |
15532 | continue; | |
15533 | } | |
8a2c8fef | 15534 | |
293f5f65 | 15535 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
15536 | } |
15537 | ||
293f5f65 L |
15538 | /* Display disabled extensions. */ |
15539 | if (ext) | |
ae89daec | 15540 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
293f5f65 | 15541 | { |
ae89daec JB |
15542 | char *str; |
15543 | ||
15544 | if (cpu_arch[j].type != PROCESSOR_NONE | |
15545 | || !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
15546 | continue; | |
15547 | str = xasprintf ("no%s", cpu_arch[j].name); | |
15548 | p = output_message (stream, p, message, start, &left, str, | |
15549 | strlen (str)); | |
15550 | free (str); | |
293f5f65 L |
15551 | } |
15552 | ||
8a2c8fef L |
15553 | *p = '\0'; |
15554 | fprintf (stream, "%s\n", message); | |
15555 | } | |
15556 | ||
252b5132 | 15557 | void |
8a2c8fef | 15558 | md_show_usage (FILE *stream) |
252b5132 | 15559 | { |
4cc782b5 ILT |
15560 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
15561 | fprintf (stream, _("\ | |
d4693039 | 15562 | -Qy, -Qn ignored\n\ |
a38cf1db | 15563 | -V print assembler version number\n\ |
b3b91714 AM |
15564 | -k ignored\n")); |
15565 | #endif | |
15566 | fprintf (stream, _("\ | |
7ebd68d1 NC |
15567 | -n do not optimize code alignment\n\ |
15568 | -O{012s} attempt some code optimizations\n\ | |
b3b91714 AM |
15569 | -q quieten some warnings\n")); |
15570 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15571 | fprintf (stream, _("\ | |
a38cf1db | 15572 | -s ignored\n")); |
b3b91714 | 15573 | #endif |
b00af7c8 JB |
15574 | #ifdef BFD64 |
15575 | # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15576 | fprintf (stream, _("\ | |
15577 | --32/--64/--x32 generate 32bit/64bit/x32 object\n")); | |
15578 | # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O) | |
751d281c | 15579 | fprintf (stream, _("\ |
b00af7c8 JB |
15580 | --32/--64 generate 32bit/64bit object\n")); |
15581 | # endif | |
751d281c | 15582 | #endif |
b3b91714 AM |
15583 | #ifdef SVR4_COMMENT_CHARS |
15584 | fprintf (stream, _("\ | |
15585 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
15586 | #else |
15587 | fprintf (stream, _("\ | |
b3b91714 | 15588 | --divide ignored\n")); |
4cc782b5 | 15589 | #endif |
9103f4f4 | 15590 | fprintf (stream, _("\ |
6305a203 | 15591 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 15592 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 15593 | show_arch (stream, 0, 1); |
8a2c8fef | 15594 | fprintf (stream, _("\ |
ae89daec | 15595 | EXTENSION is combination of (possibly \"no\"-prefixed):\n")); |
1ded5609 | 15596 | show_arch (stream, 1, 0); |
6305a203 | 15597 | fprintf (stream, _("\ |
8a2c8fef | 15598 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 15599 | show_arch (stream, 0, 0); |
ba104c83 | 15600 | fprintf (stream, _("\ |
c0f3af97 L |
15601 | -msse2avx encode SSE instructions with VEX prefix\n")); |
15602 | fprintf (stream, _("\ | |
c8480b58 L |
15603 | -muse-unaligned-vector-move\n\ |
15604 | encode aligned vector move as unaligned vector move\n")); | |
15605 | fprintf (stream, _("\ | |
7c5c05ef | 15606 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
15607 | check SSE instructions\n")); |
15608 | fprintf (stream, _("\ | |
7c5c05ef | 15609 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
15610 | check operand combinations for validity\n")); |
15611 | fprintf (stream, _("\ | |
7c5c05ef L |
15612 | -mavxscalar=[128|256] (default: 128)\n\ |
15613 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
15614 | length\n")); |
15615 | fprintf (stream, _("\ | |
03751133 L |
15616 | -mvexwig=[0|1] (default: 0)\n\ |
15617 | encode VEX instructions with specific VEX.W value\n\ | |
15618 | for VEX.W bit ignored instructions\n")); | |
15619 | fprintf (stream, _("\ | |
7c5c05ef L |
15620 | -mevexlig=[128|256|512] (default: 128)\n\ |
15621 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
15622 | length\n")); |
15623 | fprintf (stream, _("\ | |
7c5c05ef L |
15624 | -mevexwig=[0|1] (default: 0)\n\ |
15625 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
15626 | for EVEX.W bit ignored instructions\n")); |
15627 | fprintf (stream, _("\ | |
7c5c05ef | 15628 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
15629 | encode EVEX instructions with specific EVEX.RC value\n\ |
15630 | for SAE-only ignored instructions\n")); | |
15631 | fprintf (stream, _("\ | |
7c5c05ef L |
15632 | -mmnemonic=[att|intel] ")); |
15633 | if (SYSV386_COMPAT) | |
15634 | fprintf (stream, _("(default: att)\n")); | |
15635 | else | |
15636 | fprintf (stream, _("(default: intel)\n")); | |
15637 | fprintf (stream, _("\ | |
7d3182d6 | 15638 | use AT&T/Intel mnemonic (AT&T syntax only)\n")); |
ba104c83 | 15639 | fprintf (stream, _("\ |
7c5c05ef L |
15640 | -msyntax=[att|intel] (default: att)\n\ |
15641 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
15642 | fprintf (stream, _("\ |
15643 | -mindex-reg support pseudo index registers\n")); | |
15644 | fprintf (stream, _("\ | |
15645 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
15646 | fprintf (stream, _("\ | |
7e8b059b | 15647 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 15648 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
15649 | fprintf (stream, _("\ |
15650 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
15651 | fprintf (stream, _("\ |
15652 | -mx86-used-note=[no|yes] ")); | |
15653 | if (DEFAULT_X86_USED_NOTE) | |
15654 | fprintf (stream, _("(default: yes)\n")); | |
15655 | else | |
15656 | fprintf (stream, _("(default: no)\n")); | |
15657 | fprintf (stream, _("\ | |
15658 | generate x86 used ISA and feature properties\n")); | |
15659 | #endif | |
15660 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
15661 | fprintf (stream, _("\ |
15662 | -mbig-obj generate big object files\n")); | |
15663 | #endif | |
d022bddd | 15664 | fprintf (stream, _("\ |
7c5c05ef | 15665 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 15666 | strip all lock prefixes\n")); |
5db04b09 | 15667 | fprintf (stream, _("\ |
7c5c05ef | 15668 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
15669 | encode lfence, mfence and sfence as\n\ |
15670 | lock addl $0x0, (%%{re}sp)\n")); | |
15671 | fprintf (stream, _("\ | |
7c5c05ef L |
15672 | -mrelax-relocations=[no|yes] ")); |
15673 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
15674 | fprintf (stream, _("(default: yes)\n")); | |
15675 | else | |
15676 | fprintf (stream, _("(default: no)\n")); | |
15677 | fprintf (stream, _("\ | |
0cb4071e L |
15678 | generate relax relocations\n")); |
15679 | fprintf (stream, _("\ | |
e379e5f3 L |
15680 | -malign-branch-boundary=NUM (default: 0)\n\ |
15681 | align branches within NUM byte boundary\n")); | |
15682 | fprintf (stream, _("\ | |
15683 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
15684 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
15685 | indirect\n\ | |
15686 | specify types of branches to align\n")); | |
15687 | fprintf (stream, _("\ | |
15688 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
15689 | align branches with NUM prefixes per instruction\n")); | |
15690 | fprintf (stream, _("\ | |
76cf450b L |
15691 | -mbranches-within-32B-boundaries\n\ |
15692 | align branches within 32 byte boundary\n")); | |
15693 | fprintf (stream, _("\ | |
ae531041 L |
15694 | -mlfence-after-load=[no|yes] (default: no)\n\ |
15695 | generate lfence after load\n")); | |
15696 | fprintf (stream, _("\ | |
15697 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
15698 | generate lfence before indirect near branch\n")); | |
15699 | fprintf (stream, _("\ | |
a09f656b | 15700 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
15701 | generate lfence before ret\n")); |
15702 | fprintf (stream, _("\ | |
7c5c05ef | 15703 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
15704 | fprintf (stream, _("\ |
15705 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
15706 | } |
15707 | ||
3e73aa7c | 15708 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 15709 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 15710 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
15711 | |
15712 | /* Pick the target format to use. */ | |
15713 | ||
47926f60 | 15714 | const char * |
e3bb37b5 | 15715 | i386_target_format (void) |
252b5132 | 15716 | { |
d34049e8 | 15717 | if (startswith (default_arch, "x86_64")) |
351f65ca L |
15718 | { |
15719 | update_code_flag (CODE_64BIT, 1); | |
071c5d81 | 15720 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
351f65ca | 15721 | if (default_arch[6] == '\0') |
7f56bc95 | 15722 | x86_elf_abi = X86_64_ABI; |
351f65ca | 15723 | else |
7f56bc95 | 15724 | x86_elf_abi = X86_64_X32_ABI; |
071c5d81 | 15725 | #endif |
351f65ca | 15726 | } |
3e73aa7c | 15727 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 15728 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
15729 | else if (!strcmp (default_arch, "iamcu")) |
15730 | { | |
15731 | update_code_flag (CODE_32BIT, 1); | |
15732 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
15733 | { | |
15734 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
15735 | cpu_arch_name = "iamcu"; | |
d92c7521 | 15736 | free (cpu_sub_arch_name); |
5197d474 L |
15737 | cpu_sub_arch_name = NULL; |
15738 | cpu_arch_flags = iamcu_flags; | |
15739 | cpu_arch_isa = PROCESSOR_IAMCU; | |
15740 | cpu_arch_isa_flags = iamcu_flags; | |
15741 | if (!cpu_arch_tune_set) | |
fb263707 | 15742 | cpu_arch_tune = PROCESSOR_IAMCU; |
5197d474 | 15743 | } |
8d471ec1 | 15744 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
15745 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
15746 | cpu_arch_name); | |
15747 | } | |
3e73aa7c | 15748 | else |
2b5d6a91 | 15749 | as_fatal (_("unknown architecture")); |
89507696 JB |
15750 | |
15751 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
ae89daec | 15752 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 15753 | |
252b5132 RH |
15754 | switch (OUTPUT_FLAVOR) |
15755 | { | |
9384f2ff | 15756 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 15757 | case bfd_target_aout_flavour: |
47926f60 | 15758 | return AOUT_TARGET_FORMAT; |
4c63da97 | 15759 | #endif |
9384f2ff AM |
15760 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
15761 | # if defined (TE_PE) || defined (TE_PEP) | |
15762 | case bfd_target_coff_flavour: | |
167ad85b | 15763 | if (flag_code == CODE_64BIT) |
eb19308f JB |
15764 | { |
15765 | object_64bit = 1; | |
15766 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
15767 | } | |
15768 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; | |
9384f2ff | 15769 | # elif defined (TE_GO32) |
0561d57c JK |
15770 | case bfd_target_coff_flavour: |
15771 | return "coff-go32"; | |
9384f2ff | 15772 | # else |
252b5132 RH |
15773 | case bfd_target_coff_flavour: |
15774 | return "coff-i386"; | |
9384f2ff | 15775 | # endif |
4c63da97 | 15776 | #endif |
3e73aa7c | 15777 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 15778 | case bfd_target_elf_flavour: |
3e73aa7c | 15779 | { |
351f65ca L |
15780 | const char *format; |
15781 | ||
15782 | switch (x86_elf_abi) | |
4fa24527 | 15783 | { |
351f65ca L |
15784 | default: |
15785 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
15786 | #ifndef TE_SOLARIS |
15787 | tls_get_addr = "___tls_get_addr"; | |
15788 | #endif | |
351f65ca | 15789 | break; |
7f56bc95 | 15790 | case X86_64_ABI: |
351f65ca | 15791 | use_rela_relocations = 1; |
4fa24527 | 15792 | object_64bit = 1; |
e379e5f3 L |
15793 | #ifndef TE_SOLARIS |
15794 | tls_get_addr = "__tls_get_addr"; | |
15795 | #endif | |
351f65ca L |
15796 | format = ELF_TARGET_FORMAT64; |
15797 | break; | |
7f56bc95 | 15798 | case X86_64_X32_ABI: |
4fa24527 | 15799 | use_rela_relocations = 1; |
351f65ca | 15800 | object_64bit = 1; |
e379e5f3 L |
15801 | #ifndef TE_SOLARIS |
15802 | tls_get_addr = "__tls_get_addr"; | |
15803 | #endif | |
862be3fb | 15804 | disallow_64bit_reloc = 1; |
351f65ca L |
15805 | format = ELF_TARGET_FORMAT32; |
15806 | break; | |
4fa24527 | 15807 | } |
c085ab00 | 15808 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
15809 | { |
15810 | if (x86_elf_abi != I386_ABI) | |
15811 | as_fatal (_("Intel MCU is 32bit only")); | |
15812 | return ELF_TARGET_IAMCU_FORMAT; | |
15813 | } | |
8a9036a4 | 15814 | else |
351f65ca | 15815 | return format; |
3e73aa7c | 15816 | } |
e57f8c65 TG |
15817 | #endif |
15818 | #if defined (OBJ_MACH_O) | |
15819 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
15820 | if (flag_code == CODE_64BIT) |
15821 | { | |
15822 | use_rela_relocations = 1; | |
15823 | object_64bit = 1; | |
15824 | return "mach-o-x86-64"; | |
15825 | } | |
15826 | else | |
15827 | return "mach-o-i386"; | |
4c63da97 | 15828 | #endif |
252b5132 RH |
15829 | default: |
15830 | abort (); | |
15831 | return NULL; | |
15832 | } | |
15833 | } | |
15834 | ||
47926f60 | 15835 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 15836 | \f |
252b5132 | 15837 | symbolS * |
7016a5d5 | 15838 | md_undefined_symbol (char *name) |
252b5132 | 15839 | { |
18dc2407 ILT |
15840 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
15841 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
15842 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
15843 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
15844 | { |
15845 | if (!GOT_symbol) | |
15846 | { | |
15847 | if (symbol_find (name)) | |
15848 | as_bad (_("GOT already in symbol table")); | |
15849 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 15850 | &zero_address_frag, 0); |
24eab124 AM |
15851 | }; |
15852 | return GOT_symbol; | |
15853 | } | |
252b5132 RH |
15854 | return 0; |
15855 | } | |
15856 | ||
071c5d81 | 15857 | #if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) |
252b5132 | 15858 | /* Round up a section size to the appropriate boundary. */ |
47926f60 | 15859 | |
252b5132 | 15860 | valueT |
071c5d81 | 15861 | md_section_align (segT segment, valueT size) |
252b5132 | 15862 | { |
4c63da97 AM |
15863 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) |
15864 | { | |
15865 | /* For a.out, force the section size to be aligned. If we don't do | |
15866 | this, BFD will align it for us, but it will not write out the | |
15867 | final bytes of the section. This may be a bug in BFD, but it is | |
15868 | easier to fix it here since that is how the other a.out targets | |
15869 | work. */ | |
15870 | int align; | |
15871 | ||
fd361982 | 15872 | align = bfd_section_alignment (segment); |
8d3842cd | 15873 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 15874 | } |
252b5132 RH |
15875 | |
15876 | return size; | |
15877 | } | |
071c5d81 | 15878 | #endif |
252b5132 RH |
15879 | |
15880 | /* On the i386, PC-relative offsets are relative to the start of the | |
15881 | next instruction. That is, the address of the offset, plus its | |
15882 | size, since the offset is always the last part of the insn. */ | |
15883 | ||
15884 | long | |
e3bb37b5 | 15885 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
15886 | { |
15887 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
15888 | } | |
15889 | ||
d4064aad | 15890 | #ifdef OBJ_AOUT |
252b5132 RH |
15891 | |
15892 | static void | |
e3bb37b5 | 15893 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15894 | { |
29b0f896 | 15895 | int temp; |
252b5132 RH |
15896 | |
15897 | temp = get_absolute_expression (); | |
15898 | subseg_set (bss_section, (subsegT) temp); | |
15899 | demand_empty_rest_of_line (); | |
15900 | } | |
15901 | ||
15902 | #endif | |
15903 | ||
e379e5f3 L |
15904 | /* Remember constant directive. */ |
15905 | ||
15906 | void | |
15907 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
15908 | { | |
b5482fe5 JB |
15909 | struct last_insn *last_insn |
15910 | = &seg_info(now_seg)->tc_segment_info_data.last_insn; | |
15911 | ||
ce69d081 | 15912 | if (bfd_section_flags (now_seg) & SEC_CODE) |
e379e5f3 | 15913 | { |
b5482fe5 JB |
15914 | last_insn->kind = last_insn_directive; |
15915 | last_insn->name = "constant directive"; | |
15916 | last_insn->file = as_where (&last_insn->line); | |
e379e5f3 L |
15917 | } |
15918 | } | |
15919 | ||
3abbafc2 | 15920 | int |
e3bb37b5 | 15921 | i386_validate_fix (fixS *fixp) |
252b5132 | 15922 | { |
e52a16f2 JB |
15923 | if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section) |
15924 | { | |
15925 | reloc_howto_type *howto; | |
15926 | ||
15927 | howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
15928 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
15929 | _("invalid %s relocation against register"), | |
15930 | howto ? howto->name : "<unknown>"); | |
15931 | return 0; | |
15932 | } | |
15933 | ||
3abbafc2 JB |
15934 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
15935 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
15936 | || fixp->fx_r_type == BFD_RELOC_SIZE64) | |
15937 | return IS_ELF && fixp->fx_addsy | |
15938 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
15939 | || S_IS_EXTERNAL (fixp->fx_addsy)); | |
a533c8df L |
15940 | |
15941 | if (fixp->fx_tcbit3) | |
15942 | { | |
15943 | if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF) | |
15944 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTTPOFF; | |
15945 | else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
15946 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC; | |
15947 | } | |
3abbafc2 JB |
15948 | #endif |
15949 | ||
02a86693 | 15950 | if (fixp->fx_subsy) |
252b5132 | 15951 | { |
02a86693 | 15952 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 15953 | { |
02a86693 L |
15954 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
15955 | { | |
15956 | if (!object_64bit) | |
15957 | abort (); | |
15958 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15959 | if (fixp->fx_tcbit2) | |
3d5a60de L |
15960 | { |
15961 | if (fixp->fx_tcbit3) | |
15962 | fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX; | |
15963 | else | |
15964 | fixp->fx_r_type = (fixp->fx_tcbit | |
15965 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
15966 | : BFD_RELOC_X86_64_GOTPCRELX); | |
15967 | } | |
02a86693 L |
15968 | else |
15969 | #endif | |
15970 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
15971 | } | |
d6ab8113 | 15972 | else |
02a86693 L |
15973 | { |
15974 | if (!object_64bit) | |
15975 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
15976 | else | |
15977 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
15978 | } | |
15979 | fixp->fx_subsy = 0; | |
23df1078 | 15980 | } |
252b5132 | 15981 | } |
02a86693 | 15982 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 15983 | else |
02a86693 | 15984 | { |
2585b7a5 L |
15985 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
15986 | to section. Since PLT32 relocation must be against symbols, | |
15987 | turn such PLT32 relocation into PC32 relocation. */ | |
15988 | if (fixp->fx_addsy | |
15989 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
15990 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
15991 | && symbol_section_p (fixp->fx_addsy)) | |
15992 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
15993 | if (!object_64bit) | |
15994 | { | |
15995 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
15996 | && fixp->fx_tcbit2) | |
15997 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
15998 | } | |
02a86693 L |
15999 | } |
16000 | #endif | |
3abbafc2 JB |
16001 | |
16002 | return 1; | |
252b5132 RH |
16003 | } |
16004 | ||
252b5132 | 16005 | arelent * |
7016a5d5 | 16006 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
16007 | { |
16008 | arelent *rel; | |
16009 | bfd_reloc_code_real_type code; | |
16010 | ||
16011 | switch (fixp->fx_r_type) | |
16012 | { | |
8ce3d284 | 16013 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3abbafc2 JB |
16014 | symbolS *sym; |
16015 | ||
8fd4256d L |
16016 | case BFD_RELOC_SIZE32: |
16017 | case BFD_RELOC_SIZE64: | |
3abbafc2 JB |
16018 | if (fixp->fx_addsy |
16019 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)) | |
16020 | && (!fixp->fx_subsy | |
16021 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)))) | |
16022 | sym = fixp->fx_addsy; | |
16023 | else if (fixp->fx_subsy | |
16024 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)) | |
16025 | && (!fixp->fx_addsy | |
16026 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)))) | |
16027 | sym = fixp->fx_subsy; | |
16028 | else | |
16029 | sym = NULL; | |
16030 | if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym)) | |
8fd4256d L |
16031 | { |
16032 | /* Resolve size relocation against local symbol to size of | |
16033 | the symbol plus addend. */ | |
3abbafc2 | 16034 | valueT value = S_GET_SIZE (sym); |
44f87162 | 16035 | |
3abbafc2 JB |
16036 | if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) |
16037 | value = bfd_section_size (S_GET_SEGMENT (sym)); | |
16038 | if (sym == fixp->fx_subsy) | |
16039 | { | |
16040 | value = -value; | |
16041 | if (fixp->fx_addsy) | |
16042 | value += S_GET_VALUE (fixp->fx_addsy); | |
16043 | } | |
16044 | else if (fixp->fx_subsy) | |
16045 | value -= S_GET_VALUE (fixp->fx_subsy); | |
44f87162 | 16046 | value += fixp->fx_offset; |
8fd4256d | 16047 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
d965814f | 16048 | && object_64bit |
8fd4256d L |
16049 | && !fits_in_unsigned_long (value)) |
16050 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
16051 | _("symbol size computation overflow")); | |
16052 | fixp->fx_addsy = NULL; | |
16053 | fixp->fx_subsy = NULL; | |
16054 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
16055 | return NULL; | |
16056 | } | |
3abbafc2 JB |
16057 | if (!fixp->fx_addsy || fixp->fx_subsy) |
16058 | { | |
16059 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
16060 | "unsupported expression involving @size"); | |
16061 | return NULL; | |
16062 | } | |
8ce3d284 | 16063 | #endif |
1a0670f3 | 16064 | /* Fall through. */ |
8fd4256d | 16065 | |
3e73aa7c JH |
16066 | case BFD_RELOC_X86_64_PLT32: |
16067 | case BFD_RELOC_X86_64_GOT32: | |
16068 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
16069 | case BFD_RELOC_X86_64_GOTPCRELX: |
16070 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
3d5a60de | 16071 | case BFD_RELOC_X86_64_CODE_4_GOTPCRELX: |
252b5132 RH |
16072 | case BFD_RELOC_386_PLT32: |
16073 | case BFD_RELOC_386_GOT32: | |
02a86693 | 16074 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
16075 | case BFD_RELOC_386_GOTOFF: |
16076 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
16077 | case BFD_RELOC_386_TLS_GD: |
16078 | case BFD_RELOC_386_TLS_LDM: | |
16079 | case BFD_RELOC_386_TLS_LDO_32: | |
16080 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
16081 | case BFD_RELOC_386_TLS_IE: |
16082 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
16083 | case BFD_RELOC_386_TLS_LE_32: |
16084 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
16085 | case BFD_RELOC_386_TLS_GOTDESC: |
16086 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
16087 | case BFD_RELOC_X86_64_TLSGD: |
16088 | case BFD_RELOC_X86_64_TLSLD: | |
16089 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 16090 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 | 16091 | case BFD_RELOC_X86_64_GOTTPOFF: |
a533c8df | 16092 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
bffbf940 | 16093 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 JB |
16094 | case BFD_RELOC_X86_64_TPOFF64: |
16095 | case BFD_RELOC_X86_64_GOTOFF64: | |
16096 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
16097 | case BFD_RELOC_X86_64_GOT64: |
16098 | case BFD_RELOC_X86_64_GOTPCREL64: | |
16099 | case BFD_RELOC_X86_64_GOTPC64: | |
16100 | case BFD_RELOC_X86_64_GOTPLT64: | |
16101 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 | 16102 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 16103 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
67a4f2b7 | 16104 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
252b5132 RH |
16105 | case BFD_RELOC_RVA: |
16106 | case BFD_RELOC_VTABLE_ENTRY: | |
16107 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
16108 | #ifdef TE_PE |
16109 | case BFD_RELOC_32_SECREL: | |
145667f8 | 16110 | case BFD_RELOC_16_SECIDX: |
6482c264 | 16111 | #endif |
252b5132 RH |
16112 | code = fixp->fx_r_type; |
16113 | break; | |
dbbaec26 L |
16114 | case BFD_RELOC_X86_64_32S: |
16115 | if (!fixp->fx_pcrel) | |
16116 | { | |
16117 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
16118 | code = fixp->fx_r_type; | |
16119 | break; | |
16120 | } | |
1a0670f3 | 16121 | /* Fall through. */ |
252b5132 | 16122 | default: |
93382f6d | 16123 | if (fixp->fx_pcrel) |
252b5132 | 16124 | { |
93382f6d AM |
16125 | switch (fixp->fx_size) |
16126 | { | |
16127 | default: | |
b091f402 AM |
16128 | as_bad_where (fixp->fx_file, fixp->fx_line, |
16129 | _("can not do %d byte pc-relative relocation"), | |
16130 | fixp->fx_size); | |
93382f6d AM |
16131 | code = BFD_RELOC_32_PCREL; |
16132 | break; | |
16133 | case 1: code = BFD_RELOC_8_PCREL; break; | |
16134 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 16135 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
16136 | #ifdef BFD64 |
16137 | case 8: code = BFD_RELOC_64_PCREL; break; | |
16138 | #endif | |
93382f6d AM |
16139 | } |
16140 | } | |
16141 | else | |
16142 | { | |
16143 | switch (fixp->fx_size) | |
16144 | { | |
16145 | default: | |
b091f402 AM |
16146 | as_bad_where (fixp->fx_file, fixp->fx_line, |
16147 | _("can not do %d byte relocation"), | |
16148 | fixp->fx_size); | |
93382f6d AM |
16149 | code = BFD_RELOC_32; |
16150 | break; | |
16151 | case 1: code = BFD_RELOC_8; break; | |
16152 | case 2: code = BFD_RELOC_16; break; | |
16153 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 16154 | #ifdef BFD64 |
3e73aa7c | 16155 | case 8: code = BFD_RELOC_64; break; |
937149dd | 16156 | #endif |
93382f6d | 16157 | } |
252b5132 RH |
16158 | } |
16159 | break; | |
16160 | } | |
252b5132 | 16161 | |
d182319b JB |
16162 | if ((code == BFD_RELOC_32 |
16163 | || code == BFD_RELOC_32_PCREL | |
16164 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
16165 | && GOT_symbol |
16166 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 16167 | { |
4fa24527 | 16168 | if (!object_64bit) |
d6ab8113 JB |
16169 | code = BFD_RELOC_386_GOTPC; |
16170 | else | |
16171 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 16172 | } |
7b81dfbb AJ |
16173 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
16174 | && GOT_symbol | |
16175 | && fixp->fx_addsy == GOT_symbol) | |
16176 | { | |
16177 | code = BFD_RELOC_X86_64_GOTPC64; | |
16178 | } | |
252b5132 | 16179 | |
add39d23 TS |
16180 | rel = XNEW (arelent); |
16181 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 16182 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
16183 | |
16184 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 16185 | |
3e73aa7c JH |
16186 | if (!use_rela_relocations) |
16187 | { | |
16188 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
16189 | vtable entry to be used in the relocation's section offset. */ | |
16190 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
16191 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
16192 | #if defined (OBJ_COFF) && defined (TE_PE) |
16193 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
16194 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
16195 | else | |
16196 | #endif | |
c6682705 | 16197 | rel->addend = 0; |
3e73aa7c JH |
16198 | } |
16199 | /* Use the rela in 64bit mode. */ | |
252b5132 | 16200 | else |
3e73aa7c | 16201 | { |
862be3fb L |
16202 | if (disallow_64bit_reloc) |
16203 | switch (code) | |
16204 | { | |
862be3fb L |
16205 | case BFD_RELOC_X86_64_DTPOFF64: |
16206 | case BFD_RELOC_X86_64_TPOFF64: | |
16207 | case BFD_RELOC_64_PCREL: | |
16208 | case BFD_RELOC_X86_64_GOTOFF64: | |
16209 | case BFD_RELOC_X86_64_GOT64: | |
16210 | case BFD_RELOC_X86_64_GOTPCREL64: | |
16211 | case BFD_RELOC_X86_64_GOTPC64: | |
16212 | case BFD_RELOC_X86_64_GOTPLT64: | |
16213 | case BFD_RELOC_X86_64_PLTOFF64: | |
16214 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
16215 | _("cannot represent relocation type %s in x32 mode"), | |
16216 | bfd_get_reloc_code_name (code)); | |
16217 | break; | |
16218 | default: | |
16219 | break; | |
16220 | } | |
16221 | ||
062cd5e7 AS |
16222 | if (!fixp->fx_pcrel) |
16223 | rel->addend = fixp->fx_offset; | |
16224 | else | |
16225 | switch (code) | |
16226 | { | |
16227 | case BFD_RELOC_X86_64_PLT32: | |
16228 | case BFD_RELOC_X86_64_GOT32: | |
16229 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
16230 | case BFD_RELOC_X86_64_GOTPCRELX: |
16231 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
3d5a60de | 16232 | case BFD_RELOC_X86_64_CODE_4_GOTPCRELX: |
bffbf940 JJ |
16233 | case BFD_RELOC_X86_64_TLSGD: |
16234 | case BFD_RELOC_X86_64_TLSLD: | |
16235 | case BFD_RELOC_X86_64_GOTTPOFF: | |
a533c8df | 16236 | case BFD_RELOC_X86_64_CODE_4_GOTTPOFF: |
67a4f2b7 | 16237 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
a533c8df | 16238 | case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC: |
67a4f2b7 | 16239 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
062cd5e7 AS |
16240 | rel->addend = fixp->fx_offset - fixp->fx_size; |
16241 | break; | |
16242 | default: | |
16243 | rel->addend = (section->vma | |
16244 | - fixp->fx_size | |
16245 | + fixp->fx_addnumber | |
16246 | + md_pcrel_from (fixp)); | |
16247 | break; | |
16248 | } | |
3e73aa7c JH |
16249 | } |
16250 | ||
252b5132 RH |
16251 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
16252 | if (rel->howto == NULL) | |
16253 | { | |
16254 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 16255 | _("cannot represent relocation type %s"), |
252b5132 RH |
16256 | bfd_get_reloc_code_name (code)); |
16257 | /* Set howto to a garbage value so that we can keep going. */ | |
16258 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 16259 | gas_assert (rel->howto != NULL); |
252b5132 RH |
16260 | } |
16261 | ||
16262 | return rel; | |
16263 | } | |
16264 | ||
ee86248c | 16265 | #include "tc-i386-intel.c" |
54cfded0 | 16266 | |
a60de03c JB |
16267 | void |
16268 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 16269 | { |
a60de03c JB |
16270 | int saved_naked_reg; |
16271 | char saved_register_dot; | |
54cfded0 | 16272 | |
a60de03c JB |
16273 | saved_naked_reg = allow_naked_reg; |
16274 | allow_naked_reg = 1; | |
16275 | saved_register_dot = register_chars['.']; | |
16276 | register_chars['.'] = '.'; | |
16277 | allow_pseudo_reg = 1; | |
16278 | expression_and_evaluate (exp); | |
16279 | allow_pseudo_reg = 0; | |
16280 | register_chars['.'] = saved_register_dot; | |
16281 | allow_naked_reg = saved_naked_reg; | |
16282 | ||
e96d56a1 | 16283 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 16284 | { |
a60de03c JB |
16285 | if ((addressT) exp->X_add_number < i386_regtab_size) |
16286 | { | |
16287 | exp->X_op = O_constant; | |
16288 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
16289 | .dw2_regnum[flag_code >> 1]; | |
16290 | } | |
16291 | else | |
16292 | exp->X_op = O_illegal; | |
54cfded0 | 16293 | } |
54cfded0 AM |
16294 | } |
16295 | ||
16296 | void | |
16297 | tc_x86_frame_initial_instructions (void) | |
16298 | { | |
a60de03c JB |
16299 | static unsigned int sp_regno[2]; |
16300 | ||
16301 | if (!sp_regno[flag_code >> 1]) | |
16302 | { | |
16303 | char *saved_input = input_line_pointer; | |
16304 | char sp[][4] = {"esp", "rsp"}; | |
16305 | expressionS exp; | |
a4447b93 | 16306 | |
a60de03c JB |
16307 | input_line_pointer = sp[flag_code >> 1]; |
16308 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 16309 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
16310 | sp_regno[flag_code >> 1] = exp.X_add_number; |
16311 | input_line_pointer = saved_input; | |
16312 | } | |
a4447b93 | 16313 | |
61ff971f L |
16314 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
16315 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 16316 | } |
d2b2c203 | 16317 | |
d7921315 L |
16318 | int |
16319 | x86_dwarf2_addr_size (void) | |
16320 | { | |
16321 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
16322 | if (x86_elf_abi == X86_64_X32_ABI) | |
16323 | return 4; | |
16324 | #endif | |
16325 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
16326 | } | |
16327 | ||
071c5d81 JB |
16328 | #ifdef TE_PE |
16329 | void | |
16330 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
16331 | { | |
16332 | expressionS exp; | |
16333 | ||
16334 | exp.X_op = O_secrel; | |
16335 | exp.X_add_symbol = symbol; | |
16336 | exp.X_add_number = 0; | |
16337 | emit_expr (&exp, size); | |
16338 | } | |
16339 | #endif | |
16340 | ||
16341 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
d2b2c203 DJ |
16342 | int |
16343 | i386_elf_section_type (const char *str, size_t len) | |
16344 | { | |
16345 | if (flag_code == CODE_64BIT | |
16346 | && len == sizeof ("unwind") - 1 | |
d34049e8 | 16347 | && startswith (str, "unwind")) |
d2b2c203 DJ |
16348 | return SHT_X86_64_UNWIND; |
16349 | ||
16350 | return -1; | |
16351 | } | |
bb41ade5 | 16352 | |
da374e94 JB |
16353 | void |
16354 | i386_elf_section_change_hook (void) | |
16355 | { | |
16356 | struct i386_segment_info *info = &seg_info(now_seg)->tc_segment_info_data; | |
16357 | struct i386_segment_info *curr, *prev; | |
16358 | ||
16359 | if (info->subseg == now_subseg) | |
16360 | return; | |
16361 | ||
16362 | /* Find the (or make a) list entry to save state into. */ | |
16363 | for (prev = info; (curr = prev->next) != NULL; prev = curr) | |
16364 | if (curr->subseg == info->subseg) | |
16365 | break; | |
16366 | if (!curr) | |
16367 | { | |
16368 | curr = XNEW (struct i386_segment_info); | |
16369 | curr->subseg = info->subseg; | |
16370 | curr->next = NULL; | |
16371 | prev->next = curr; | |
16372 | } | |
16373 | curr->last_insn = info->last_insn; | |
16374 | ||
16375 | /* Find the list entry to load state from. */ | |
16376 | for (curr = info->next; curr; curr = curr->next) | |
16377 | if (curr->subseg == now_subseg) | |
16378 | break; | |
16379 | if (curr) | |
16380 | info->last_insn = curr->last_insn; | |
16381 | else | |
16382 | memset (&info->last_insn, 0, sizeof (info->last_insn)); | |
16383 | info->subseg = now_subseg; | |
16384 | } | |
16385 | ||
ad5fec3b EB |
16386 | #ifdef TE_SOLARIS |
16387 | void | |
16388 | i386_solaris_fix_up_eh_frame (segT sec) | |
16389 | { | |
16390 | if (flag_code == CODE_64BIT) | |
16391 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
16392 | } | |
16393 | #endif | |
16394 | ||
3b22753a L |
16395 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ |
16396 | ||
01e1a5bc | 16397 | bfd_vma |
6d4af3c2 | 16398 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
16399 | { |
16400 | if (flag_code == CODE_64BIT) | |
16401 | { | |
16402 | if (letter == 'l') | |
16403 | return SHF_X86_64_LARGE; | |
16404 | ||
8f3bae45 | 16405 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 16406 | } |
3b22753a | 16407 | else |
8f3bae45 | 16408 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
16409 | return -1; |
16410 | } | |
16411 | ||
3b22753a L |
16412 | static void |
16413 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
16414 | { | |
16415 | if (flag_code != CODE_64BIT) | |
16416 | { | |
16417 | s_comm_internal (0, elf_common_parse); | |
16418 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
16419 | } | |
16420 | else | |
16421 | { | |
16422 | static segT lbss_section; | |
16423 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
16424 | asection *saved_bss_section = bss_section; | |
16425 | ||
16426 | if (lbss_section == NULL) | |
16427 | { | |
16428 | flagword applicable; | |
16429 | segT seg = now_seg; | |
16430 | subsegT subseg = now_subseg; | |
16431 | ||
16432 | /* The .lbss section is for local .largecomm symbols. */ | |
16433 | lbss_section = subseg_new (".lbss", 0); | |
16434 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 16435 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
16436 | seg_info (lbss_section)->bss = 1; |
16437 | ||
16438 | subseg_set (seg, subseg); | |
16439 | } | |
16440 | ||
16441 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
16442 | bss_section = lbss_section; | |
16443 | ||
16444 | s_comm_internal (0, elf_common_parse); | |
16445 | ||
16446 | elf_com_section_ptr = saved_com_section_ptr; | |
16447 | bss_section = saved_bss_section; | |
16448 | } | |
16449 | } | |
16450 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |