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Increase minor version number (to 2.10.91) to help tools detect the new
[thirdparty/binutils-gdb.git] / gas / config / tc-ia64.c
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800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
e0c9811a 2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
800eeca4
JW		 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
800eeca4
JW		 35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
42
43 */
44
45#include "as.h"
46#include "dwarf2dbg.h"
47#include "subsegs.h"
48
49#include "opcode/ia64.h"
50
51#include "elf/ia64.h"
52
53#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54#define MIN(a,b) ((a) < (b) ? (a) : (b))
55
56#define NUM_SLOTS 4
57#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58#define CURR_SLOT md.slot[md.curr_slot]
59
60#define O_pseudo_fixup (O_max + 1)
61
62enum special_section
63 {
64 SPECIAL_SECTION_BSS = 0,
65 SPECIAL_SECTION_SBSS,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
71 };
72
73enum reloc_func
74 {
75 FUNC_FPTR_RELATIVE,
76 FUNC_GP_RELATIVE,
77 FUNC_LT_RELATIVE,
c67e42c9 78 FUNC_PC_RELATIVE,
800eeca4
JW		 79 FUNC_PLT_RELATIVE,
80 FUNC_SEC_RELATIVE,
81 FUNC_SEG_RELATIVE,
82 FUNC_LTV_RELATIVE,
83 FUNC_LT_FPTR_RELATIVE,
84 };
85
86enum reg_symbol
87 {
88 REG_GR = 0,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
95 REG_CFM,
96 REG_PR,
97 REG_PR_ROT,
98 REG_PSR,
99 REG_PSR_L,
100 REG_PSR_UM,
101 /* The following are pseudo-registers for use by gas only. */
102 IND_CPUID,
103 IND_DBR,
104 IND_DTR,
105 IND_ITR,
106 IND_IBR,
107 IND_MEM,
108 IND_MSR,
109 IND_PKR,
110 IND_PMC,
111 IND_PMD,
112 IND_RR,
e0c9811a
JW		 113 /* The following pseudo-registers are used for unwind directives only: */
114 REG_PSP,
115 REG_PRIUNAT,
800eeca4
JW		 116 REG_NUM
117 };
118
119enum dynreg_type
120 {
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
124 DYNREG_NUM_TYPES
125 };
126
127/* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
130 instruction. */
131struct label_fix
132 {
133 struct label_fix *next;
134 struct symbol *sym;
135 };
136
137extern int target_big_endian;
138
139/* Characters which always start a comment. */
140const char comment_chars[] = "";
141
142/* Characters which start a comment at the beginning of a line. */
143const char line_comment_chars[] = "#";
144
145/* Characters which may be used to separate multiple commands on a
146 single line. */
147const char line_separator_chars[] = ";";
148
149/* Characters which are used to indicate an exponent in a floating
150 point number. */
151const char EXP_CHARS[] = "eE";
152
153/* Characters which mean that a number is a floating point constant,
154 as in 0d1.0. */
155const char FLT_CHARS[] = "rRsSfFdDxXpP";
156
157/* ia64-specific option processing: */
158
159const char *md_shortopts = "M:N:x::";
160
161struct option md_longopts[] =
162 {
c43c2cc5
JW		 163#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
165#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
800eeca4
JW		 167 };
168
169size_t md_longopts_size = sizeof (md_longopts);
170
171static struct
172 {
173 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
174 struct hash_control *reg_hash; /* register name hash table */
175 struct hash_control *dynreg_hash; /* dynamic register hash table */
176 struct hash_control *const_hash; /* constant hash table */
177 struct hash_control *entry_hash; /* code entry hint hash table */
178
179 symbolS *regsym[REG_NUM];
180
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
184 expressionS qp;
185
186 unsigned int
187 manual_bundling : 1,
188 debug_dv: 1,
189 detect_dv: 1,
190 explicit_mode : 1, /* which mode we're in */
191 default_explicit_mode : 1, /* which mode is the default */
192 mode_explicitly_set : 1, /* was the current mode explicitly set? */
193 auto_align : 1;
194
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
198 int curr_slot;
199 int num_slots_in_use;
200 struct slot
201 {
202 unsigned int
203 end_of_insn_group : 1,
204 manual_bundling_on : 1,
205 manual_bundling_off : 1;
206 signed char user_template; /* user-selected template, if any */
207 unsigned char qp_regno; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
211 int num_fixups;
212 struct insn_fix
213 {
214 bfd_reloc_code_real_type code;
215 enum ia64_opnd opnd; /* type of operand in need of fix */
216 unsigned int is_pcrel : 1; /* is operand pc-relative? */
217 expressionS expr; /* the value to be inserted */
218 }
219 fixup[2]; /* at most two fixups per insn */
220 struct ia64_opcode *idesc;
221 struct label_fix *label_fixups;
222 struct unw_rec_list *unwind_record; /* Unwind directive. */
223 expressionS opnd[6];
224 char *src_file;
225 unsigned int src_line;
226 struct dwarf2_line_info debug_line;
227 }
228 slot[NUM_SLOTS];
229
230 segT last_text_seg;
231
232 struct dynreg
233 {
234 struct dynreg *next; /* next dynamic register */
235 const char *name;
236 unsigned short base; /* the base register number */
237 unsigned short num_regs; /* # of registers in this set */
238 }
239 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
240
241 flagword flags; /* ELF-header flags */
242
243 struct mem_offset {
244 unsigned hint:1; /* is this hint currently valid? */
245 bfd_vma offset; /* mem.offset offset */
246 bfd_vma base; /* mem.offset base */
247 } mem_offset;
248
249 int path; /* number of alt. entry points seen */
250 const char **entry_labels; /* labels of all alternate paths in
251 the current DV-checking block. */
252 int maxpaths; /* size currently allocated for
253 entry_labels */
254 }
255md;
256
257/* application registers: */
258
e0c9811a
JW		 259#define AR_K0 0
260#define AR_K7 7
261#define AR_RSC 16
262#define AR_BSP 17
263#define AR_BSPSTORE 18
264#define AR_RNAT 19
265#define AR_UNAT 36
266#define AR_FPSR 40
267#define AR_ITC 44
268#define AR_PFS 64
269#define AR_LC 65
800eeca4
JW		 270
271static const struct
272 {
273 const char *name;
274 int regnum;
275 }
276ar[] =
277 {
278 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
279 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
280 {"ar.rsc", 16}, {"ar.bsp", 17},
281 {"ar.bspstore", 18}, {"ar.rnat", 19},
282 {"ar.fcr", 21}, {"ar.eflag", 24},
283 {"ar.csd", 25}, {"ar.ssd", 26},
284 {"ar.cflg", 27}, {"ar.fsr", 28},
285 {"ar.fir", 29}, {"ar.fdr", 30},
286 {"ar.ccv", 32}, {"ar.unat", 36},
287 {"ar.fpsr", 40}, {"ar.itc", 44},
288 {"ar.pfs", 64}, {"ar.lc", 65},
289 {"ar.ec", 66},
290 };
291
292#define CR_IPSR 16
293#define CR_ISR 17
294#define CR_IIP 19
295#define CR_IFA 20
296#define CR_ITIR 21
297#define CR_IIPA 22
298#define CR_IFS 23
299#define CR_IIM 24
300#define CR_IHA 25
301#define CR_IVR 65
302#define CR_TPR 66
303#define CR_EOI 67
304#define CR_IRR0 68
305#define CR_IRR3 71
306#define CR_LRR0 80
307#define CR_LRR1 81
308
309/* control registers: */
310static const struct
311 {
312 const char *name;
313 int regnum;
314 }
315cr[] =
316 {
317 {"cr.dcr", 0},
318 {"cr.itm", 1},
319 {"cr.iva", 2},
320 {"cr.pta", 8},
321 {"cr.gpta", 9},
322 {"cr.ipsr", 16},
323 {"cr.isr", 17},
324 {"cr.iip", 19},
325 {"cr.ifa", 20},
326 {"cr.itir", 21},
327 {"cr.iipa", 22},
328 {"cr.ifs", 23},
329 {"cr.iim", 24},
330 {"cr.iha", 25},
331 {"cr.lid", 64},
332 {"cr.ivr", 65},
333 {"cr.tpr", 66},
334 {"cr.eoi", 67},
335 {"cr.irr0", 68},
336 {"cr.irr1", 69},
337 {"cr.irr2", 70},
338 {"cr.irr3", 71},
339 {"cr.itv", 72},
340 {"cr.pmv", 73},
341 {"cr.cmcv", 74},
342 {"cr.lrr0", 80},
343 {"cr.lrr1", 81}
344 };
345
346#define PSR_MFL 4
347#define PSR_IC 13
348#define PSR_DFL 18
349#define PSR_CPL 32
350
351static const struct const_desc
352 {
353 const char *name;
354 valueT value;
355 }
356const_bits[] =
357 {
358 /* PSR constant masks: */
359
360 /* 0: reserved */
361 {"psr.be", ((valueT) 1) << 1},
362 {"psr.up", ((valueT) 1) << 2},
363 {"psr.ac", ((valueT) 1) << 3},
364 {"psr.mfl", ((valueT) 1) << 4},
365 {"psr.mfh", ((valueT) 1) << 5},
366 /* 6-12: reserved */
367 {"psr.ic", ((valueT) 1) << 13},
368 {"psr.i", ((valueT) 1) << 14},
369 {"psr.pk", ((valueT) 1) << 15},
370 /* 16: reserved */
371 {"psr.dt", ((valueT) 1) << 17},
372 {"psr.dfl", ((valueT) 1) << 18},
373 {"psr.dfh", ((valueT) 1) << 19},
374 {"psr.sp", ((valueT) 1) << 20},
375 {"psr.pp", ((valueT) 1) << 21},
376 {"psr.di", ((valueT) 1) << 22},
377 {"psr.si", ((valueT) 1) << 23},
378 {"psr.db", ((valueT) 1) << 24},
379 {"psr.lp", ((valueT) 1) << 25},
380 {"psr.tb", ((valueT) 1) << 26},
381 {"psr.rt", ((valueT) 1) << 27},
382 /* 28-31: reserved */
383 /* 32-33: cpl (current privilege level) */
384 {"psr.is", ((valueT) 1) << 34},
385 {"psr.mc", ((valueT) 1) << 35},
386 {"psr.it", ((valueT) 1) << 36},
387 {"psr.id", ((valueT) 1) << 37},
388 {"psr.da", ((valueT) 1) << 38},
389 {"psr.dd", ((valueT) 1) << 39},
390 {"psr.ss", ((valueT) 1) << 40},
391 /* 41-42: ri (restart instruction) */
392 {"psr.ed", ((valueT) 1) << 43},
393 {"psr.bn", ((valueT) 1) << 44},
394 };
395
396/* indirect register-sets/memory: */
397
398static const struct
399 {
400 const char *name;
401 int regnum;
402 }
403indirect_reg[] =
404 {
405 { "CPUID", IND_CPUID },
406 { "cpuid", IND_CPUID },
407 { "dbr", IND_DBR },
408 { "dtr", IND_DTR },
409 { "itr", IND_ITR },
410 { "ibr", IND_IBR },
411 { "msr", IND_MSR },
412 { "pkr", IND_PKR },
413 { "pmc", IND_PMC },
414 { "pmd", IND_PMD },
415 { "rr", IND_RR },
416 };
417
418/* Pseudo functions used to indicate relocation types (these functions
419 start with an at sign (@). */
420static struct
421 {
422 const char *name;
423 enum pseudo_type
424 {
425 PSEUDO_FUNC_NONE,
426 PSEUDO_FUNC_RELOC,
427 PSEUDO_FUNC_CONST,
e0c9811a 428 PSEUDO_FUNC_REG,
800eeca4
JW		 429 PSEUDO_FUNC_FLOAT
430 }
431 type;
432 union
433 {
434 unsigned long ival;
435 symbolS *sym;
436 }
437 u;
438 }
439pseudo_func[] =
440 {
441 /* reloc pseudo functions (these must come first!): */
442 { "fptr", PSEUDO_FUNC_RELOC },
443 { "gprel", PSEUDO_FUNC_RELOC },
444 { "ltoff", PSEUDO_FUNC_RELOC },
c67e42c9 445 { "pcrel", PSEUDO_FUNC_RELOC },
800eeca4
JW		 446 { "pltoff", PSEUDO_FUNC_RELOC },
447 { "secrel", PSEUDO_FUNC_RELOC },
448 { "segrel", PSEUDO_FUNC_RELOC },
449 { "ltv", PSEUDO_FUNC_RELOC },
450 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
451
452 /* mbtype4 constants: */
453 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
454 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
455 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
456 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
457 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
458
459 /* fclass constants: */
bf3ca999 460 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
800eeca4
JW		 461 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
462 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
463 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
464 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
465 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
466 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
467 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
468 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
TW		 469
470 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a
JW		 471
472 /* unwind-related constants: */
473 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
474 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
475 { "nt", PSEUDO_FUNC_CONST, { 2 } },
476
477 /* unwind-related registers: */
478 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
800eeca4
JW		 479 };
480
481/* 41-bit nop opcodes (one per unit): */
482static const bfd_vma nop[IA64_NUM_UNITS] =
483 {
484 0x0000000000LL, /* NIL => break 0 */
485 0x0008000000LL, /* I-unit nop */
486 0x0008000000LL, /* M-unit nop */
487 0x4000000000LL, /* B-unit nop */
488 0x0008000000LL, /* F-unit nop */
489 0x0008000000LL, /* L-"unit" nop */
490 0x0008000000LL, /* X-unit nop */
491 };
492
493/* Can't be `const' as it's passed to input routines (which have the
494 habit of setting temporary sentinels. */
495static char special_section_name[][20] =
496 {
497 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
498 {".IA_64.unwind"}, {".IA_64.unwind_info"}
499 };
500
501/* The best template for a particular sequence of up to three
502 instructions: */
503#define N IA64_NUM_TYPES
504static unsigned char best_template[N][N][N];
505#undef N
506
507/* Resource dependencies currently in effect */
508static struct rsrc {
509 int depind; /* dependency index */
510 const struct ia64_dependency *dependency; /* actual dependency */
511 unsigned specific:1, /* is this a specific bit/regno? */
512 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
513 int index; /* specific regno/bit within dependency */
514 int note; /* optional qualifying note (0 if none) */
515#define STATE_NONE 0
516#define STATE_STOP 1
517#define STATE_SRLZ 2
518 int insn_srlz; /* current insn serialization state */
519 int data_srlz; /* current data serialization state */
520 int qp_regno; /* qualifying predicate for this usage */
521 char *file; /* what file marked this dependency */
522 int line; /* what line marked this dependency */
523 struct mem_offset mem_offset; /* optional memory offset hint */
524 int path; /* corresponding code entry index */
525} *regdeps = NULL;
526static int regdepslen = 0;
527static int regdepstotlen = 0;
528static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
529static const char *dv_sem[] = { "none", "implied", "impliedf",
530 "data", "instr", "specific", "other" };
531
532/* Current state of PR mutexation */
533static struct qpmutex {
534 valueT prmask;
535 int path;
536} *qp_mutexes = NULL; /* QP mutex bitmasks */
537static int qp_mutexeslen = 0;
538static int qp_mutexestotlen = 0;
539static valueT qp_safe_across_calls = 0;
540
541/* Current state of PR implications */
542static struct qp_imply {
543 unsigned p1:6;
544 unsigned p2:6;
545 unsigned p2_branched:1;
546 int path;
547} *qp_implies = NULL;
548static int qp_implieslen = 0;
549static int qp_impliestotlen = 0;
550
551/* Keep track of static GR values so that indirect register usage can
552 sometimes be tracked. */
553static struct gr {
554 unsigned known:1;
555 int path;
556 valueT value;
557} gr_values[128] = {{ 1, 0 }};
558
559/* These are the routines required to output the various types of
560 unwind records. */
561
562typedef struct unw_rec_list {
563 unwind_record r;
e0c9811a 564 unsigned long slot_number;
800eeca4
JW		 565 struct unw_rec_list *next;
566} unw_rec_list;
567
568#define SLOT_NUM_NOT_SET -1
569
e0c9811a
JW		 570static struct
571{
572 unsigned long next_slot_number;
573
574 /* Maintain a list of unwind entries for the current function. */
575 unw_rec_list *list;
576 unw_rec_list *tail;
800eeca4 577
e0c9811a
JW		 578 /* Any unwind entires that should be attached to the current slot
579 that an insn is being constructed for. */
580 unw_rec_list *current_entry;
800eeca4 581
e0c9811a
JW		 582 /* These are used to create the unwind table entry for this function. */
583 symbolS *proc_start;
584 symbolS *proc_end;
585 symbolS *info; /* pointer to unwind info */
586 symbolS *personality_routine;
800eeca4 587
e0c9811a
JW		 588 /* TRUE if processing unwind directives in a prologue region. */
589 int prologue;
30d25259 590 int prologue_mask;
e0c9811a 591} unwind;
800eeca4
JW		 592
593typedef void (*vbyte_func) PARAMS ((int, char *, char *));
594
595/* Forward delarations: */
596static int ar_is_in_integer_unit PARAMS ((int regnum));
597static void set_section PARAMS ((char *name));
598static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
599 unsigned int, unsigned int));
600static void dot_radix PARAMS ((int));
601static void dot_special_section PARAMS ((int));
602static void dot_proc PARAMS ((int));
603static void dot_fframe PARAMS ((int));
604static void dot_vframe PARAMS ((int));
150f24a2
JW		 605static void dot_vframesp PARAMS ((int));
606static void dot_vframepsp PARAMS ((int));
800eeca4
JW		 607static void dot_save PARAMS ((int));
608static void dot_restore PARAMS ((int));
150f24a2
JW		 609static void dot_restorereg PARAMS ((int));
610static void dot_restorereg_p PARAMS ((int));
800eeca4
JW		 611static void dot_handlerdata PARAMS ((int));
612static void dot_unwentry PARAMS ((int));
613static void dot_altrp PARAMS ((int));
e0c9811a 614static void dot_savemem PARAMS ((int));
800eeca4
JW		 615static void dot_saveg PARAMS ((int));
616static void dot_savef PARAMS ((int));
617static void dot_saveb PARAMS ((int));
618static void dot_savegf PARAMS ((int));
619static void dot_spill PARAMS ((int));
150f24a2
JW		 620static void dot_spillreg PARAMS ((int));
621static void dot_spillmem PARAMS ((int));
622static void dot_spillreg_p PARAMS ((int));
623static void dot_spillmem_p PARAMS ((int));
624static void dot_label_state PARAMS ((int));
625static void dot_copy_state PARAMS ((int));
800eeca4
JW		 626static void dot_unwabi PARAMS ((int));
627static void dot_personality PARAMS ((int));
628static void dot_body PARAMS ((int));
629static void dot_prologue PARAMS ((int));
630static void dot_endp PARAMS ((int));
631static void dot_template PARAMS ((int));
632static void dot_regstk PARAMS ((int));
633static void dot_rot PARAMS ((int));
634static void dot_byteorder PARAMS ((int));
635static void dot_psr PARAMS ((int));
636static void dot_alias PARAMS ((int));
637static void dot_ln PARAMS ((int));
638static char *parse_section_name PARAMS ((void));
639static void dot_xdata PARAMS ((int));
640static void stmt_float_cons PARAMS ((int));
641static void stmt_cons_ua PARAMS ((int));
642static void dot_xfloat_cons PARAMS ((int));
643static void dot_xstringer PARAMS ((int));
644static void dot_xdata_ua PARAMS ((int));
645static void dot_xfloat_cons_ua PARAMS ((int));
150f24a2 646static void print_prmask PARAMS ((valueT mask));
800eeca4
JW		 647static void dot_pred_rel PARAMS ((int));
648static void dot_reg_val PARAMS ((int));
649static void dot_dv_mode PARAMS ((int));
650static void dot_entry PARAMS ((int));
651static void dot_mem_offset PARAMS ((int));
e0c9811a 652static void add_unwind_entry PARAMS((unw_rec_list *ptr));
800eeca4
JW		 653static symbolS* declare_register PARAMS ((const char *name, int regnum));
654static void declare_register_set PARAMS ((const char *, int, int));
655static unsigned int operand_width PARAMS ((enum ia64_opnd));
656static int operand_match PARAMS ((const struct ia64_opcode *idesc,
657 int index, expressionS *e));
658static int parse_operand PARAMS ((expressionS *e));
659static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
660static void build_insn PARAMS ((struct slot *, bfd_vma *));
661static void emit_one_bundle PARAMS ((void));
662static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
663static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
664 bfd_reloc_code_real_type r_type));
665static void insn_group_break PARAMS ((int, int, int));
150f24a2
JW		 666static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
667 struct rsrc *, int depind, int path));
800eeca4
JW		 668static void add_qp_mutex PARAMS((valueT mask));
669static void add_qp_imply PARAMS((int p1, int p2));
670static void clear_qp_branch_flag PARAMS((valueT mask));
671static void clear_qp_mutex PARAMS((valueT mask));
672static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
673static void clear_register_values PARAMS ((void));
674static void print_dependency PARAMS ((const char *action, int depind));
150f24a2
JW		 675static void instruction_serialization PARAMS ((void));
676static void data_serialization PARAMS ((void));
677static void remove_marked_resource PARAMS ((struct rsrc *));
800eeca4 678static int is_conditional_branch PARAMS ((struct ia64_opcode *));
150f24a2 679static int is_taken_branch PARAMS ((struct ia64_opcode *));
800eeca4 680static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
150f24a2
JW		 681static int depends_on PARAMS ((int, struct ia64_opcode *));
682static int specify_resource PARAMS ((const struct ia64_dependency *,
683 struct ia64_opcode *, int, struct rsrc [], int, int));
800eeca4
JW		 684static int check_dv PARAMS((struct ia64_opcode *idesc));
685static void check_dependencies PARAMS((struct ia64_opcode *));
686static void mark_resources PARAMS((struct ia64_opcode *));
687static void update_dependencies PARAMS((struct ia64_opcode *));
688static void note_register_values PARAMS((struct ia64_opcode *));
150f24a2
JW		 689static int qp_mutex PARAMS ((int, int, int));
690static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
691static void output_vbyte_mem PARAMS ((int, char *, char *));
692static void count_output PARAMS ((int, char *, char *));
693static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
694static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
800eeca4 695static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 696static void output_P1_format PARAMS ((vbyte_func, int));
697static void output_P2_format PARAMS ((vbyte_func, int, int));
698static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
699static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
700static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
701static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
702static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
703static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
704static void output_P9_format PARAMS ((vbyte_func, int, int));
705static void output_P10_format PARAMS ((vbyte_func, int, int));
706static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
707static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800eeca4
JW		 708static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
709static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 710static char format_ab_reg PARAMS ((int, int));
711static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
712 unsigned long));
713static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
714static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
715 unsigned long));
716static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
717static void free_list_records PARAMS ((unw_rec_list *));
718static unw_rec_list *output_prologue PARAMS ((void));
719static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
720static unw_rec_list *output_body PARAMS ((void));
721static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
722static unw_rec_list *output_mem_stack_v PARAMS ((void));
723static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
724static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
725static unw_rec_list *output_rp_when PARAMS ((void));
726static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
727static unw_rec_list *output_rp_br PARAMS ((unsigned int));
728static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
729static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
730static unw_rec_list *output_pfs_when PARAMS ((void));
731static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
732static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
733static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
734static unw_rec_list *output_preds_when PARAMS ((void));
735static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
736static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
737static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
738static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
739static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
740static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
741static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
742static unw_rec_list *output_br_mem PARAMS ((unsigned int));
743static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
744static unw_rec_list *output_spill_base PARAMS ((unsigned int));
745static unw_rec_list *output_unat_when PARAMS ((void));
746static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
747static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
748static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
749static unw_rec_list *output_lc_when PARAMS ((void));
750static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
751static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
752static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
753static unw_rec_list *output_fpsr_when PARAMS ((void));
754static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
755static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
756static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
757static unw_rec_list *output_priunat_when_gr PARAMS ((void));
758static unw_rec_list *output_priunat_when_mem PARAMS ((void));
759static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
760static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
761static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
762static unw_rec_list *output_bsp_when PARAMS ((void));
763static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
764static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
765static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
766static unw_rec_list *output_bspstore_when PARAMS ((void));
767static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
768static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
769static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
770static unw_rec_list *output_rnat_when PARAMS ((void));
771static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
772static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
773static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
774static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
775static unw_rec_list *output_epilogue PARAMS ((unsigned long));
776static unw_rec_list *output_label_state PARAMS ((unsigned long));
777static unw_rec_list *output_copy_state PARAMS ((unsigned long));
778static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
779static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
780static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
781 unsigned int));
782static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
783 unsigned int));
784static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
785 unsigned int));
786static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
787 unsigned int, unsigned int));
788static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
789static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
790static int calc_record_size PARAMS ((unw_rec_list *));
791static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
792static int count_bits PARAMS ((unsigned long));
793static unsigned long slot_index PARAMS ((unsigned long, unsigned long));
794static void fixup_unw_records PARAMS ((unw_rec_list *));
795static int output_unw_records PARAMS ((unw_rec_list *, void **));
796static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
797static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
798static int generate_unwind_image PARAMS ((void));
800eeca4
JW		 799
800/* Determine if application register REGNUM resides in the integer
801 unit (as opposed to the memory unit). */
802static int
803ar_is_in_integer_unit (reg)
804 int reg;
805{
806 reg -= REG_AR;
807
808 return (reg == 64 /* pfs */
809 || reg == 65 /* lc */
810 || reg == 66 /* ec */
811 /* ??? ias accepts and puts these in the integer unit. */
812 || (reg >= 112 && reg <= 127));
813}
814
815/* Switch to section NAME and create section if necessary. It's
816 rather ugly that we have to manipulate input_line_pointer but I
817 don't see any other way to accomplish the same thing without
818 changing obj-elf.c (which may be the Right Thing, in the end). */
819static void
820set_section (name)
821 char *name;
822{
823 char *saved_input_line_pointer;
824
825 saved_input_line_pointer = input_line_pointer;
826 input_line_pointer = name;
827 obj_elf_section (0);
828 input_line_pointer = saved_input_line_pointer;
829}
830
831/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
832
833flagword
834ia64_elf_section_flags (flags, attr, type)
835 flagword flags;
836 int attr, type;
837{
838 if (attr & SHF_IA_64_SHORT)
839 flags |= SEC_SMALL_DATA;
840 return flags;
841}
842
843static unsigned int
844set_regstack (ins, locs, outs, rots)
845 unsigned int ins, locs, outs, rots;
846{
847 unsigned int sof; /* size of frame */
848
849 sof = ins + locs + outs;
850 if (sof > 96)
851 {
852 as_bad ("Size of frame exceeds maximum of 96 registers");
853 return 0;
854 }
855 if (rots > sof)
856 {
857 as_warn ("Size of rotating registers exceeds frame size");
858 return 0;
859 }
860 md.in.base = REG_GR + 32;
861 md.loc.base = md.in.base + ins;
862 md.out.base = md.loc.base + locs;
863
864 md.in.num_regs = ins;
865 md.loc.num_regs = locs;
866 md.out.num_regs = outs;
867 md.rot.num_regs = rots;
868 return sof;
869}
870
871void
872ia64_flush_insns ()
873{
874 struct label_fix *lfix;
875 segT saved_seg;
876 subsegT saved_subseg;
877
878 if (!md.last_text_seg)
879 return;
880
881 saved_seg = now_seg;
882 saved_subseg = now_subseg;
883
884 subseg_set (md.last_text_seg, 0);
885
886 while (md.num_slots_in_use > 0)
887 emit_one_bundle (); /* force out queued instructions */
888
889 /* In case there are labels following the last instruction, resolve
890 those now: */
891 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
892 {
893 S_SET_VALUE (lfix->sym, frag_now_fix ());
894 symbol_set_frag (lfix->sym, frag_now);
895 }
896 CURR_SLOT.label_fixups = 0;
897
898 subseg_set (saved_seg, saved_subseg);
899}
900
901void
902ia64_do_align (nbytes)
903 int nbytes;
904{
905 char *saved_input_line_pointer = input_line_pointer;
906
907 input_line_pointer = "";
908 s_align_bytes (nbytes);
909 input_line_pointer = saved_input_line_pointer;
910}
911
912void
913ia64_cons_align (nbytes)
914 int nbytes;
915{
916 if (md.auto_align)
917 {
918 char *saved_input_line_pointer = input_line_pointer;
919 input_line_pointer = "";
920 s_align_bytes (nbytes);
921 input_line_pointer = saved_input_line_pointer;
922 }
923}
924
925/* Output COUNT bytes to a memory location. */
926static unsigned char *vbyte_mem_ptr = NULL;
927
928void
929output_vbyte_mem (count, ptr, comment)
930 int count;
931 char *ptr;
932 char *comment;
933{
934 int x;
935 if (vbyte_mem_ptr == NULL)
936 abort ();
937
938 if (count == 0)
939 return;
940 for (x = 0; x < count; x++)
941 *(vbyte_mem_ptr++) = ptr[x];
942}
943
944/* Count the number of bytes required for records. */
945static int vbyte_count = 0;
946void
947count_output (count, ptr, comment)
948 int count;
949 char *ptr;
950 char *comment;
951{
952 vbyte_count += count;
953}
954
955static void
956output_R1_format (f, rtype, rlen)
957 vbyte_func f;
958 unw_record_type rtype;
959 int rlen;
960{
e0c9811a 961 int r = 0;
800eeca4
JW		 962 char byte;
963 if (rlen > 0x1f)
964 {
965 output_R3_format (f, rtype, rlen);
966 return;
967 }
800eeca4 968
e0c9811a
JW		 969 if (rtype == body)
970 r = 1;
971 else if (rtype != prologue)
972 as_bad ("record type is not valid");
973
800eeca4
JW		 974 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
975 (*f) (1, &byte, NULL);
976}
977
978static void
979output_R2_format (f, mask, grsave, rlen)
980 vbyte_func f;
981 int mask, grsave;
982 unsigned long rlen;
983{
984 char bytes[20];
985 int count = 2;
986 mask = (mask & 0x0f);
987 grsave = (grsave & 0x7f);
988
989 bytes[0] = (UNW_R2 | (mask >> 1));
990 bytes[1] = (((mask & 0x01) << 7) | grsave);
991 count += output_leb128 (bytes + 2, rlen, 0);
992 (*f) (count, bytes, NULL);
993}
994
995static void
996output_R3_format (f, rtype, rlen)
997 vbyte_func f;
998 unw_record_type rtype;
999 unsigned long rlen;
1000{
e0c9811a 1001 int r = 0, count;
800eeca4
JW		 1002 char bytes[20];
1003 if (rlen <= 0x1f)
1004 {
1005 output_R1_format (f, rtype, rlen);
1006 return;
1007 }
e0c9811a
JW		 1008
1009 if (rtype == body)
1010 r = 1;
1011 else if (rtype != prologue)
1012 as_bad ("record type is not valid");
800eeca4
JW		 1013 bytes[0] = (UNW_R3 | r);
1014 count = output_leb128 (bytes + 1, rlen, 0);
1015 (*f) (count + 1, bytes, NULL);
1016}
1017
1018static void
1019output_P1_format (f, brmask)
1020 vbyte_func f;
1021 int brmask;
1022{
1023 char byte;
1024 byte = UNW_P1 | (brmask & 0x1f);
1025 (*f) (1, &byte, NULL);
1026}
1027
1028static void
1029output_P2_format (f, brmask, gr)
1030 vbyte_func f;
1031 int brmask;
1032 int gr;
1033{
1034 char bytes[2];
1035 brmask = (brmask & 0x1f);
1036 bytes[0] = UNW_P2 | (brmask >> 1);
1037 bytes[1] = (((brmask & 1) << 7) | gr);
1038 (*f) (2, bytes, NULL);
1039}
1040
1041static void
1042output_P3_format (f, rtype, reg)
1043 vbyte_func f;
1044 unw_record_type rtype;
1045 int reg;
1046{
1047 char bytes[2];
e0c9811a 1048 int r = 0;
800eeca4
JW		 1049 reg = (reg & 0x7f);
1050 switch (rtype)
1051 {
1052 case psp_gr:
1053 r = 0;
1054 break;
1055 case rp_gr:
1056 r = 1;
1057 break;
1058 case pfs_gr:
1059 r = 2;
1060 break;
1061 case preds_gr:
1062 r = 3;
1063 break;
1064 case unat_gr:
1065 r = 4;
1066 break;
1067 case lc_gr:
1068 r = 5;
1069 break;
1070 case rp_br:
1071 r = 6;
1072 break;
1073 case rnat_gr:
1074 r = 7;
1075 break;
1076 case bsp_gr:
1077 r = 8;
1078 break;
1079 case bspstore_gr:
1080 r = 9;
1081 break;
1082 case fpsr_gr:
1083 r = 10;
1084 break;
1085 case priunat_gr:
1086 r = 11;
1087 break;
1088 default:
1089 as_bad ("Invalid record type for P3 format.");
1090 }
1091 bytes[0] = (UNW_P3 | (r >> 1));
1092 bytes[1] = (((r & 1) << 7) | reg);
1093 (*f) (2, bytes, NULL);
1094}
1095
1096
1097static void
e0c9811a 1098output_P4_format (f, imask, imask_size)
800eeca4 1099 vbyte_func f;
e0c9811a
JW		 1100 unsigned char *imask;
1101 unsigned long imask_size;
800eeca4 1102{
e0c9811a
JW		 1103 imask[0] = UNW_P4;
1104 (*f) (imask_size, imask, NULL);
800eeca4
JW		 1105}
1106
1107static void
1108output_P5_format (f, grmask, frmask)
1109 vbyte_func f;
1110 int grmask;
1111 unsigned long frmask;
1112{
1113 char bytes[4];
1114 grmask = (grmask & 0x0f);
1115
1116 bytes[0] = UNW_P5;
1117 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1118 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1119 bytes[3] = (frmask & 0x000000ff);
1120 (*f) (4, bytes, NULL);
1121}
1122
1123static void
1124output_P6_format (f, rtype, rmask)
1125 vbyte_func f;
1126 unw_record_type rtype;
1127 int rmask;
1128{
1129 char byte;
e0c9811a
JW		 1130 int r = 0;
1131
1132 if (rtype == gr_mem)
1133 r = 1;
1134 else if (rtype != fr_mem)
1135 as_bad ("Invalid record type for format P6");
800eeca4
JW		 1136 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1137 (*f) (1, &byte, NULL);
1138}
1139
1140static void
1141output_P7_format (f, rtype, w1, w2)
1142 vbyte_func f;
1143 unw_record_type rtype;
1144 unsigned long w1;
1145 unsigned long w2;
1146{
1147 char bytes[20];
1148 int count = 1;
e0c9811a 1149 int r = 0;
800eeca4
JW		 1150 count += output_leb128 (bytes + 1, w1, 0);
1151 switch (rtype)
1152 {
1153 case mem_stack_f:
e4c58b25
JW		 1154 r = 0;
1155 count += output_leb128 (bytes + count, w2 >> 4, 0);
800eeca4
JW		 1156 break;
1157 case mem_stack_v:
1158 r = 1;
1159 break;
1160 case spill_base:
1161 r = 2;
1162 break;
1163 case psp_sprel:
1164 r = 3;
1165 break;
1166 case rp_when:
1167 r = 4;
1168 break;
1169 case rp_psprel:
1170 r = 5;
1171 break;
1172 case pfs_when:
1173 r = 6;
1174 break;
1175 case pfs_psprel:
1176 r = 7;
1177 break;
1178 case preds_when:
1179 r = 8;
1180 break;
1181 case preds_psprel:
1182 r = 9;
1183 break;
1184 case lc_when:
1185 r = 10;
1186 break;
1187 case lc_psprel:
1188 r = 11;
1189 break;
1190 case unat_when:
1191 r = 12;
1192 break;
1193 case unat_psprel:
1194 r = 13;
1195 break;
1196 case fpsr_when:
1197 r = 14;
1198 break;
1199 case fpsr_psprel:
1200 r = 15;
1201 break;
e0c9811a
JW		 1202 default:
1203 break;
800eeca4
JW		 1204 }
1205 bytes[0] = (UNW_P7 | r);
1206 (*f) (count, bytes, NULL);
1207}
1208
1209static void
1210output_P8_format (f, rtype, t)
1211 vbyte_func f;
1212 unw_record_type rtype;
1213 unsigned long t;
1214{
1215 char bytes[20];
e0c9811a 1216 int r = 0;
800eeca4
JW		 1217 int count = 2;
1218 bytes[0] = UNW_P8;
1219 switch (rtype)
1220 {
1221 case rp_sprel:
1222 r = 1;
1223 break;
1224 case pfs_sprel:
1225 r = 2;
1226 break;
1227 case preds_sprel:
1228 r = 3;
1229 break;
1230 case lc_sprel:
1231 r = 4;
1232 break;
1233 case unat_sprel:
1234 r = 5;
1235 break;
1236 case fpsr_sprel:
1237 r = 6;
1238 break;
1239 case bsp_when:
1240 r = 7;
1241 break;
1242 case bsp_psprel:
1243 r = 8;
1244 break;
1245 case bsp_sprel:
1246 r = 9;
1247 break;
1248 case bspstore_when:
1249 r = 10;
1250 break;
1251 case bspstore_psprel:
1252 r = 11;
1253 break;
1254 case bspstore_sprel:
1255 r = 12;
1256 break;
1257 case rnat_when:
1258 r = 13;
1259 break;
1260 case rnat_psprel:
1261 r = 14;
1262 break;
1263 case rnat_sprel:
1264 r = 15;
1265 break;
1266 case priunat_when_gr:
1267 r = 16;
1268 break;
1269 case priunat_psprel:
1270 r = 17;
1271 break;
1272 case priunat_sprel:
1273 r = 18;
1274 break;
1275 case priunat_when_mem:
1276 r = 19;
1277 break;
e0c9811a
JW		 1278 default:
1279 break;
800eeca4
JW		 1280 }
1281 bytes[1] = r;
1282 count += output_leb128 (bytes + 2, t, 0);
1283 (*f) (count, bytes, NULL);
1284}
1285
1286static void
1287output_P9_format (f, grmask, gr)
1288 vbyte_func f;
1289 int grmask;
1290 int gr;
1291{
1292 char bytes[3];
1293 bytes[0] = UNW_P9;
1294 bytes[1] = (grmask & 0x0f);
1295 bytes[2] = (gr & 0x7f);
1296 (*f) (3, bytes, NULL);
1297}
1298
1299static void
1300output_P10_format (f, abi, context)
1301 vbyte_func f;
1302 int abi;
1303 int context;
1304{
1305 char bytes[3];
1306 bytes[0] = UNW_P10;
1307 bytes[1] = (abi & 0xff);
1308 bytes[2] = (context & 0xff);
1309 (*f) (3, bytes, NULL);
1310}
1311
1312static void
1313output_B1_format (f, rtype, label)
1314 vbyte_func f;
1315 unw_record_type rtype;
1316 unsigned long label;
1317{
1318 char byte;
e0c9811a 1319 int r = 0;
800eeca4
JW		 1320 if (label > 0x1f)
1321 {
1322 output_B4_format (f, rtype, label);
1323 return;
1324 }
e0c9811a
JW		 1325 if (rtype == copy_state)
1326 r = 1;
1327 else if (rtype != label_state)
1328 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1329
1330 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1331 (*f) (1, &byte, NULL);
1332}
1333
1334static void
1335output_B2_format (f, ecount, t)
1336 vbyte_func f;
1337 unsigned long ecount;
1338 unsigned long t;
1339{
1340 char bytes[20];
1341 int count = 1;
1342 if (ecount > 0x1f)
1343 {
1344 output_B3_format (f, ecount, t);
1345 return;
1346 }
1347 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1348 count += output_leb128 (bytes + 1, t, 0);
1349 (*f) (count, bytes, NULL);
1350}
1351
1352static void
1353output_B3_format (f, ecount, t)
1354 vbyte_func f;
1355 unsigned long ecount;
1356 unsigned long t;
1357{
1358 char bytes[20];
1359 int count = 1;
1360 if (ecount <= 0x1f)
1361 {
1362 output_B2_format (f, ecount, t);
1363 return;
1364 }
1365 bytes[0] = UNW_B3;
1366 count += output_leb128 (bytes + 1, t, 0);
1367 count += output_leb128 (bytes + count, ecount, 0);
1368 (*f) (count, bytes, NULL);
1369}
1370
1371static void
1372output_B4_format (f, rtype, label)
1373 vbyte_func f;
1374 unw_record_type rtype;
1375 unsigned long label;
1376{
1377 char bytes[20];
e0c9811a 1378 int r = 0;
800eeca4
JW		 1379 int count = 1;
1380 if (label <= 0x1f)
1381 {
1382 output_B1_format (f, rtype, label);
1383 return;
1384 }
e0c9811a
JW		 1385
1386 if (rtype == copy_state)
1387 r = 1;
1388 else if (rtype != label_state)
1389 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1390
1391 bytes[0] = (UNW_B4 | (r << 3));
1392 count += output_leb128 (bytes + 1, label, 0);
1393 (*f) (count, bytes, NULL);
1394}
1395
1396static char
e0c9811a
JW		 1397format_ab_reg (ab, reg)
1398 int ab;
800eeca4
JW		 1399 int reg;
1400{
1401 int ret;
e0c9811a 1402 ab = (ab & 3);
800eeca4 1403 reg = (reg & 0x1f);
e0c9811a 1404 ret = (ab << 5) | reg;
800eeca4
JW		 1405 return ret;
1406}
1407
1408static void
e0c9811a 1409output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW		 1410 vbyte_func f;
1411 unw_record_type rtype;
e0c9811a 1412 int ab, reg;
800eeca4
JW		 1413 unsigned long t;
1414 unsigned long w1;
1415{
1416 char bytes[20];
e0c9811a 1417 int r = 0;
800eeca4
JW		 1418 int count = 2;
1419 bytes[0] = UNW_X1;
e0c9811a
JW		 1420
1421 if (rtype == spill_sprel)
1422 r = 1;
1423 else if (rtype != spill_psprel)
1424 as_bad ("Invalid record type for format X1");
1425 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1426 count += output_leb128 (bytes + 2, t, 0);
1427 count += output_leb128 (bytes + count, w1, 0);
1428 (*f) (count, bytes, NULL);
1429}
1430
1431static void
e0c9811a 1432output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1433 vbyte_func f;
e0c9811a 1434 int ab, reg;
800eeca4
JW		 1435 int x, y, treg;
1436 unsigned long t;
1437{
1438 char bytes[20];
800eeca4
JW		 1439 int count = 3;
1440 bytes[0] = UNW_X2;
e0c9811a 1441 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1442 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1443 count += output_leb128 (bytes + 3, t, 0);
1444 (*f) (count, bytes, NULL);
1445}
1446
1447static void
e0c9811a 1448output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW		 1449 vbyte_func f;
1450 unw_record_type rtype;
1451 int qp;
e0c9811a 1452 int ab, reg;
800eeca4
JW		 1453 unsigned long t;
1454 unsigned long w1;
1455{
1456 char bytes[20];
e0c9811a 1457 int r = 0;
800eeca4 1458 int count = 3;
e0c9811a
JW		 1459 bytes[0] = UNW_X3;
1460
1461 if (rtype == spill_sprel_p)
1462 r = 1;
1463 else if (rtype != spill_psprel_p)
1464 as_bad ("Invalid record type for format X3");
800eeca4 1465 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1466 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW		 1467 count += output_leb128 (bytes + 3, t, 0);
1468 count += output_leb128 (bytes + count, w1, 0);
1469 (*f) (count, bytes, NULL);
1470}
1471
1472static void
e0c9811a 1473output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW		 1474 vbyte_func f;
1475 int qp;
e0c9811a 1476 int ab, reg;
800eeca4
JW		 1477 int x, y, treg;
1478 unsigned long t;
1479{
1480 char bytes[20];
800eeca4 1481 int count = 4;
e0c9811a 1482 bytes[0] = UNW_X4;
800eeca4 1483 bytes[1] = (qp & 0x3f);
e0c9811a 1484 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1485 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1486 count += output_leb128 (bytes + 4, t, 0);
1487 (*f) (count, bytes, NULL);
1488}
1489
1490/* This function allocates a record list structure, and initializes fields. */
1491static unw_rec_list *
1492alloc_record (unw_record_type t)
1493{
1494 unw_rec_list *ptr;
1495 ptr = xmalloc (sizeof (*ptr));
1496 ptr->next = NULL;
1497 ptr->slot_number = SLOT_NUM_NOT_SET;
1498 ptr->r.type = t;
1499 return ptr;
1500}
1501
800eeca4
JW		 1502/* This function frees an entire list of record structures. */
1503void
1504free_list_records (unw_rec_list *first)
1505{
1506 unw_rec_list *ptr;
1507 for (ptr = first; ptr != NULL; )
1508 {
1509 unw_rec_list *tmp = ptr;
e0c9811a
JW		 1510
1511 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1512 && tmp->r.record.r.mask.i)
1513 free (tmp->r.record.r.mask.i);
1514
800eeca4
JW		 1515 ptr = ptr->next;
1516 free (tmp);
1517 }
1518}
1519
1520static unw_rec_list *
1521output_prologue ()
1522{
1523 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1524 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW		 1525 return ptr;
1526}
1527
1528static unw_rec_list *
1529output_prologue_gr (saved_mask, reg)
1530 unsigned int saved_mask;
1531 unsigned int reg;
1532{
1533 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW		 1534 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1535 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW		 1536 ptr->r.record.r.grsave = reg;
1537 return ptr;
1538}
1539
1540static unw_rec_list *
1541output_body ()
1542{
1543 unw_rec_list *ptr = alloc_record (body);
1544 return ptr;
1545}
1546
1547static unw_rec_list *
1548output_mem_stack_f (size)
1549 unsigned int size;
1550{
1551 unw_rec_list *ptr = alloc_record (mem_stack_f);
1552 ptr->r.record.p.size = size;
1553 return ptr;
1554}
1555
1556static unw_rec_list *
1557output_mem_stack_v ()
1558{
1559 unw_rec_list *ptr = alloc_record (mem_stack_v);
1560 return ptr;
1561}
1562
1563static unw_rec_list *
1564output_psp_gr (gr)
1565 unsigned int gr;
1566{
1567 unw_rec_list *ptr = alloc_record (psp_gr);
1568 ptr->r.record.p.gr = gr;
1569 return ptr;
1570}
1571
1572static unw_rec_list *
1573output_psp_sprel (offset)
1574 unsigned int offset;
1575{
1576 unw_rec_list *ptr = alloc_record (psp_sprel);
e0c9811a 1577 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1578 return ptr;
1579}
1580
1581static unw_rec_list *
1582output_rp_when ()
1583{
1584 unw_rec_list *ptr = alloc_record (rp_when);
1585 return ptr;
1586}
1587
1588static unw_rec_list *
1589output_rp_gr (gr)
1590 unsigned int gr;
1591{
1592 unw_rec_list *ptr = alloc_record (rp_gr);
1593 ptr->r.record.p.gr = gr;
1594 return ptr;
1595}
1596
1597static unw_rec_list *
1598output_rp_br (br)
1599 unsigned int br;
1600{
1601 unw_rec_list *ptr = alloc_record (rp_br);
1602 ptr->r.record.p.br = br;
1603 return ptr;
1604}
1605
1606static unw_rec_list *
1607output_rp_psprel (offset)
1608 unsigned int offset;
1609{
1610 unw_rec_list *ptr = alloc_record (rp_psprel);
e0c9811a 1611 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1612 return ptr;
1613}
1614
1615static unw_rec_list *
1616output_rp_sprel (offset)
1617 unsigned int offset;
1618{
1619 unw_rec_list *ptr = alloc_record (rp_sprel);
e0c9811a 1620 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1621 return ptr;
1622}
1623
1624static unw_rec_list *
1625output_pfs_when ()
1626{
1627 unw_rec_list *ptr = alloc_record (pfs_when);
1628 return ptr;
1629}
1630
1631static unw_rec_list *
1632output_pfs_gr (gr)
1633 unsigned int gr;
1634{
1635 unw_rec_list *ptr = alloc_record (pfs_gr);
1636 ptr->r.record.p.gr = gr;
1637 return ptr;
1638}
1639
1640static unw_rec_list *
1641output_pfs_psprel (offset)
1642 unsigned int offset;
1643{
1644 unw_rec_list *ptr = alloc_record (pfs_psprel);
e0c9811a 1645 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1646 return ptr;
1647}
1648
1649static unw_rec_list *
1650output_pfs_sprel (offset)
1651 unsigned int offset;
1652{
1653 unw_rec_list *ptr = alloc_record (pfs_sprel);
e0c9811a 1654 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1655 return ptr;
1656}
1657
1658static unw_rec_list *
1659output_preds_when ()
1660{
1661 unw_rec_list *ptr = alloc_record (preds_when);
1662 return ptr;
1663}
1664
1665static unw_rec_list *
1666output_preds_gr (gr)
1667 unsigned int gr;
1668{
1669 unw_rec_list *ptr = alloc_record (preds_gr);
1670 ptr->r.record.p.gr = gr;
1671 return ptr;
1672}
1673
1674static unw_rec_list *
1675output_preds_psprel (offset)
1676 unsigned int offset;
1677{
1678 unw_rec_list *ptr = alloc_record (preds_psprel);
e0c9811a 1679 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1680 return ptr;
1681}
1682
1683static unw_rec_list *
1684output_preds_sprel (offset)
1685 unsigned int offset;
1686{
1687 unw_rec_list *ptr = alloc_record (preds_sprel);
e0c9811a 1688 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1689 return ptr;
1690}
1691
1692static unw_rec_list *
1693output_fr_mem (mask)
1694 unsigned int mask;
1695{
1696 unw_rec_list *ptr = alloc_record (fr_mem);
1697 ptr->r.record.p.rmask = mask;
1698 return ptr;
1699}
1700
1701static unw_rec_list *
1702output_frgr_mem (gr_mask, fr_mask)
1703 unsigned int gr_mask;
1704 unsigned int fr_mask;
1705{
1706 unw_rec_list *ptr = alloc_record (frgr_mem);
1707 ptr->r.record.p.grmask = gr_mask;
1708 ptr->r.record.p.frmask = fr_mask;
1709 return ptr;
1710}
1711
1712static unw_rec_list *
1713output_gr_gr (mask, reg)
1714 unsigned int mask;
1715 unsigned int reg;
1716{
1717 unw_rec_list *ptr = alloc_record (gr_gr);
1718 ptr->r.record.p.grmask = mask;
1719 ptr->r.record.p.gr = reg;
1720 return ptr;
1721}
1722
1723static unw_rec_list *
1724output_gr_mem (mask)
1725 unsigned int mask;
1726{
1727 unw_rec_list *ptr = alloc_record (gr_mem);
1728 ptr->r.record.p.rmask = mask;
1729 return ptr;
1730}
1731
1732static unw_rec_list *
1733output_br_mem (unsigned int mask)
1734{
1735 unw_rec_list *ptr = alloc_record (br_mem);
1736 ptr->r.record.p.brmask = mask;
1737 return ptr;
1738}
1739
1740static unw_rec_list *
1741output_br_gr (save_mask, reg)
1742 unsigned int save_mask;
1743 unsigned int reg;
1744{
1745 unw_rec_list *ptr = alloc_record (br_gr);
1746 ptr->r.record.p.brmask = save_mask;
1747 ptr->r.record.p.gr = reg;
1748 return ptr;
1749}
1750
1751static unw_rec_list *
1752output_spill_base (offset)
1753 unsigned int offset;
1754{
1755 unw_rec_list *ptr = alloc_record (spill_base);
e0c9811a 1756 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1757 return ptr;
1758}
1759
1760static unw_rec_list *
1761output_unat_when ()
1762{
1763 unw_rec_list *ptr = alloc_record (unat_when);
1764 return ptr;
1765}
1766
1767static unw_rec_list *
1768output_unat_gr (gr)
1769 unsigned int gr;
1770{
1771 unw_rec_list *ptr = alloc_record (unat_gr);
1772 ptr->r.record.p.gr = gr;
1773 return ptr;
1774}
1775
1776static unw_rec_list *
1777output_unat_psprel (offset)
1778 unsigned int offset;
1779{
1780 unw_rec_list *ptr = alloc_record (unat_psprel);
e0c9811a 1781 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1782 return ptr;
1783}
1784
1785static unw_rec_list *
1786output_unat_sprel (offset)
1787 unsigned int offset;
1788{
1789 unw_rec_list *ptr = alloc_record (unat_sprel);
e0c9811a 1790 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1791 return ptr;
1792}
1793
1794static unw_rec_list *
1795output_lc_when ()
1796{
1797 unw_rec_list *ptr = alloc_record (lc_when);
1798 return ptr;
1799}
1800
1801static unw_rec_list *
1802output_lc_gr (gr)
1803 unsigned int gr;
1804{
1805 unw_rec_list *ptr = alloc_record (lc_gr);
1806 ptr->r.record.p.gr = gr;
1807 return ptr;
1808}
1809
1810static unw_rec_list *
1811output_lc_psprel (offset)
1812 unsigned int offset;
1813{
1814 unw_rec_list *ptr = alloc_record (lc_psprel);
e0c9811a 1815 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1816 return ptr;
1817}
1818
1819static unw_rec_list *
1820output_lc_sprel (offset)
1821 unsigned int offset;
1822{
1823 unw_rec_list *ptr = alloc_record (lc_sprel);
e0c9811a 1824 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1825 return ptr;
1826}
1827
1828static unw_rec_list *
1829output_fpsr_when ()
1830{
1831 unw_rec_list *ptr = alloc_record (fpsr_when);
1832 return ptr;
1833}
1834
1835static unw_rec_list *
1836output_fpsr_gr (gr)
1837 unsigned int gr;
1838{
1839 unw_rec_list *ptr = alloc_record (fpsr_gr);
1840 ptr->r.record.p.gr = gr;
1841 return ptr;
1842}
1843
1844static unw_rec_list *
1845output_fpsr_psprel (offset)
1846 unsigned int offset;
1847{
1848 unw_rec_list *ptr = alloc_record (fpsr_psprel);
e0c9811a 1849 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1850 return ptr;
1851}
1852
1853static unw_rec_list *
1854output_fpsr_sprel (offset)
1855 unsigned int offset;
1856{
1857 unw_rec_list *ptr = alloc_record (fpsr_sprel);
e0c9811a 1858 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1859 return ptr;
1860}
1861
1862static unw_rec_list *
1863output_priunat_when_gr ()
1864{
1865 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1866 return ptr;
1867}
1868
1869static unw_rec_list *
1870output_priunat_when_mem ()
1871{
1872 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1873 return ptr;
1874}
1875
1876static unw_rec_list *
1877output_priunat_gr (gr)
1878 unsigned int gr;
1879{
1880 unw_rec_list *ptr = alloc_record (priunat_gr);
1881 ptr->r.record.p.gr = gr;
1882 return ptr;
1883}
1884
1885static unw_rec_list *
1886output_priunat_psprel (offset)
1887 unsigned int offset;
1888{
1889 unw_rec_list *ptr = alloc_record (priunat_psprel);
e0c9811a 1890 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1891 return ptr;
1892}
1893
1894static unw_rec_list *
1895output_priunat_sprel (offset)
1896 unsigned int offset;
1897{
1898 unw_rec_list *ptr = alloc_record (priunat_sprel);
e0c9811a 1899 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1900 return ptr;
1901}
1902
1903static unw_rec_list *
1904output_bsp_when ()
1905{
1906 unw_rec_list *ptr = alloc_record (bsp_when);
1907 return ptr;
1908}
1909
1910static unw_rec_list *
1911output_bsp_gr (gr)
1912 unsigned int gr;
1913{
1914 unw_rec_list *ptr = alloc_record (bsp_gr);
1915 ptr->r.record.p.gr = gr;
1916 return ptr;
1917}
1918
1919static unw_rec_list *
1920output_bsp_psprel (offset)
1921 unsigned int offset;
1922{
1923 unw_rec_list *ptr = alloc_record (bsp_psprel);
e0c9811a 1924 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1925 return ptr;
1926}
1927
1928static unw_rec_list *
1929output_bsp_sprel (offset)
1930 unsigned int offset;
1931{
1932 unw_rec_list *ptr = alloc_record (bsp_sprel);
e0c9811a 1933 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1934 return ptr;
1935}
1936
1937static unw_rec_list *
1938output_bspstore_when ()
1939{
1940 unw_rec_list *ptr = alloc_record (bspstore_when);
1941 return ptr;
1942}
1943
1944static unw_rec_list *
1945output_bspstore_gr (gr)
1946 unsigned int gr;
1947{
1948 unw_rec_list *ptr = alloc_record (bspstore_gr);
1949 ptr->r.record.p.gr = gr;
1950 return ptr;
1951}
1952
1953static unw_rec_list *
1954output_bspstore_psprel (offset)
1955 unsigned int offset;
1956{
1957 unw_rec_list *ptr = alloc_record (bspstore_psprel);
e0c9811a 1958 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1959 return ptr;
1960}
1961
1962static unw_rec_list *
1963output_bspstore_sprel (offset)
1964 unsigned int offset;
1965{
1966 unw_rec_list *ptr = alloc_record (bspstore_sprel);
e0c9811a 1967 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1968 return ptr;
1969}
1970
1971static unw_rec_list *
1972output_rnat_when ()
1973{
1974 unw_rec_list *ptr = alloc_record (rnat_when);
1975 return ptr;
1976}
1977
1978static unw_rec_list *
1979output_rnat_gr (gr)
1980 unsigned int gr;
1981{
1982 unw_rec_list *ptr = alloc_record (rnat_gr);
1983 ptr->r.record.p.gr = gr;
1984 return ptr;
1985}
1986
1987static unw_rec_list *
1988output_rnat_psprel (offset)
1989 unsigned int offset;
1990{
1991 unw_rec_list *ptr = alloc_record (rnat_psprel);
e0c9811a 1992 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1993 return ptr;
1994}
1995
1996static unw_rec_list *
1997output_rnat_sprel (offset)
1998 unsigned int offset;
1999{
2000 unw_rec_list *ptr = alloc_record (rnat_sprel);
e0c9811a 2001 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 2002 return ptr;
2003}
2004
2005static unw_rec_list *
e0c9811a
JW		 2006output_unwabi (abi, context)
2007 unsigned long abi;
2008 unsigned long context;
800eeca4 2009{
e0c9811a
JW		 2010 unw_rec_list *ptr = alloc_record (unwabi);
2011 ptr->r.record.p.abi = abi;
2012 ptr->r.record.p.context = context;
800eeca4
JW		 2013 return ptr;
2014}
2015
2016static unw_rec_list *
e0c9811a 2017output_epilogue (unsigned long ecount)
800eeca4 2018{
e0c9811a
JW		 2019 unw_rec_list *ptr = alloc_record (epilogue);
2020 ptr->r.record.b.ecount = ecount;
800eeca4
JW		 2021 return ptr;
2022}
2023
2024static unw_rec_list *
e0c9811a 2025output_label_state (unsigned long label)
800eeca4 2026{
e0c9811a
JW		 2027 unw_rec_list *ptr = alloc_record (label_state);
2028 ptr->r.record.b.label = label;
800eeca4
JW		 2029 return ptr;
2030}
2031
2032static unw_rec_list *
e0c9811a
JW		 2033output_copy_state (unsigned long label)
2034{
2035 unw_rec_list *ptr = alloc_record (copy_state);
2036 ptr->r.record.b.label = label;
2037 return ptr;
2038}
2039
2040static unw_rec_list *
2041output_spill_psprel (ab, reg, offset)
2042 unsigned int ab;
800eeca4
JW		 2043 unsigned int reg;
2044 unsigned int offset;
2045{
2046 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 2047 ptr->r.record.x.ab = ab;
800eeca4 2048 ptr->r.record.x.reg = reg;
e0c9811a 2049 ptr->r.record.x.pspoff = offset/4;
800eeca4
JW		 2050 return ptr;
2051}
2052
2053static unw_rec_list *
e0c9811a
JW		 2054output_spill_sprel (ab, reg, offset)
2055 unsigned int ab;
800eeca4
JW		 2056 unsigned int reg;
2057 unsigned int offset;
2058{
2059 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 2060 ptr->r.record.x.ab = ab;
800eeca4 2061 ptr->r.record.x.reg = reg;
e0c9811a 2062 ptr->r.record.x.spoff = offset/4;
800eeca4
JW		 2063 return ptr;
2064}
2065
2066static unw_rec_list *
e0c9811a
JW		 2067output_spill_psprel_p (ab, reg, offset, predicate)
2068 unsigned int ab;
800eeca4
JW		 2069 unsigned int reg;
2070 unsigned int offset;
2071 unsigned int predicate;
2072{
2073 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 2074 ptr->r.record.x.ab = ab;
800eeca4 2075 ptr->r.record.x.reg = reg;
e0c9811a 2076 ptr->r.record.x.pspoff = offset/4;
800eeca4
JW		 2077 ptr->r.record.x.qp = predicate;
2078 return ptr;
2079}
2080
2081static unw_rec_list *
e0c9811a
JW		 2082output_spill_sprel_p (ab, reg, offset, predicate)
2083 unsigned int ab;
800eeca4
JW		 2084 unsigned int reg;
2085 unsigned int offset;
2086 unsigned int predicate;
2087{
2088 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 2089 ptr->r.record.x.ab = ab;
800eeca4 2090 ptr->r.record.x.reg = reg;
e0c9811a 2091 ptr->r.record.x.spoff = offset/4;
800eeca4
JW		 2092 ptr->r.record.x.qp = predicate;
2093 return ptr;
2094}
2095
2096static unw_rec_list *
e0c9811a
JW		 2097output_spill_reg (ab, reg, targ_reg, xy)
2098 unsigned int ab;
800eeca4
JW		 2099 unsigned int reg;
2100 unsigned int targ_reg;
2101 unsigned int xy;
2102{
2103 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 2104 ptr->r.record.x.ab = ab;
800eeca4
JW		 2105 ptr->r.record.x.reg = reg;
2106 ptr->r.record.x.treg = targ_reg;
2107 ptr->r.record.x.xy = xy;
2108 return ptr;
2109}
2110
2111static unw_rec_list *
e0c9811a
JW		 2112output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2113 unsigned int ab;
800eeca4
JW		 2114 unsigned int reg;
2115 unsigned int targ_reg;
2116 unsigned int xy;
2117 unsigned int predicate;
2118{
2119 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 2120 ptr->r.record.x.ab = ab;
800eeca4
JW		 2121 ptr->r.record.x.reg = reg;
2122 ptr->r.record.x.treg = targ_reg;
2123 ptr->r.record.x.xy = xy;
2124 ptr->r.record.x.qp = predicate;
2125 return ptr;
2126}
2127
2128/* Given a unw_rec_list process the correct format with the
2129 specified function. */
2130static void
2131process_one_record (ptr, f)
2132 unw_rec_list *ptr;
2133 vbyte_func f;
2134{
e0c9811a
JW		 2135 unsigned long fr_mask, gr_mask;
2136
800eeca4
JW		 2137 switch (ptr->r.type)
2138 {
e0c9811a
JW		 2139 case gr_mem:
2140 case fr_mem:
2141 case br_mem:
2142 case frgr_mem:
2143 /* these are taken care of by prologue/prologue_gr */
2144 break;
2145
2146 case prologue_gr:
800eeca4 2147 case prologue:
e0c9811a
JW		 2148 if (ptr->r.type == prologue_gr)
2149 output_R2_format (f, ptr->r.record.r.grmask,
2150 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2151 else
2152 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2153
2154 /* output descriptor(s) for union of register spills (if any): */
2155 gr_mask = ptr->r.record.r.mask.gr_mem;
2156 fr_mask = ptr->r.record.r.mask.fr_mem;
2157 if (fr_mask)
2158 {
2159 if ((fr_mask & ~0xfUL) == 0)
2160 output_P6_format (f, fr_mem, fr_mask);
2161 else
2162 {
2163 output_P5_format (f, gr_mask, fr_mask);
2164 gr_mask = 0;
2165 }
2166 }
2167 if (gr_mask)
2168 output_P6_format (f, gr_mem, gr_mask);
2169 if (ptr->r.record.r.mask.br_mem)
2170 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2171
2172 /* output imask descriptor if necessary: */
2173 if (ptr->r.record.r.mask.i)
2174 output_P4_format (f, ptr->r.record.r.mask.i,
2175 ptr->r.record.r.imask_size);
2176 break;
2177
800eeca4
JW		 2178 case body:
2179 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2180 break;
800eeca4
JW		 2181 case mem_stack_f:
2182 case mem_stack_v:
2183 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2184 ptr->r.record.p.size);
2185 break;
2186 case psp_gr:
2187 case rp_gr:
2188 case pfs_gr:
2189 case preds_gr:
2190 case unat_gr:
2191 case lc_gr:
2192 case fpsr_gr:
2193 case priunat_gr:
2194 case bsp_gr:
2195 case bspstore_gr:
2196 case rnat_gr:
2197 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2198 break;
2199 case rp_br:
2200 output_P3_format (f, rp_br, ptr->r.record.p.br);
2201 break;
2202 case psp_sprel:
2203 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2204 break;
2205 case rp_when:
2206 case pfs_when:
2207 case preds_when:
2208 case unat_when:
2209 case lc_when:
2210 case fpsr_when:
2211 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2212 break;
2213 case rp_psprel:
2214 case pfs_psprel:
2215 case preds_psprel:
2216 case unat_psprel:
2217 case lc_psprel:
2218 case fpsr_psprel:
2219 case spill_base:
2220 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2221 break;
2222 case rp_sprel:
2223 case pfs_sprel:
2224 case preds_sprel:
2225 case unat_sprel:
2226 case lc_sprel:
2227 case fpsr_sprel:
2228 case priunat_sprel:
2229 case bsp_sprel:
2230 case bspstore_sprel:
2231 case rnat_sprel:
2232 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2233 break;
800eeca4
JW		 2234 case gr_gr:
2235 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2236 break;
800eeca4
JW		 2237 case br_gr:
2238 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2239 break;
2240 case spill_mask:
2241 as_bad ("spill_mask record unimplemented.");
2242 break;
2243 case priunat_when_gr:
2244 case priunat_when_mem:
2245 case bsp_when:
2246 case bspstore_when:
2247 case rnat_when:
2248 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2249 break;
2250 case priunat_psprel:
2251 case bsp_psprel:
2252 case bspstore_psprel:
2253 case rnat_psprel:
2254 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2255 break;
e0c9811a
JW		 2256 case unwabi:
2257 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2258 break;
800eeca4 2259 case epilogue:
e0c9811a 2260 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
800eeca4
JW		 2261 break;
2262 case label_state:
800eeca4 2263 case copy_state:
e0c9811a 2264 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
800eeca4
JW		 2265 break;
2266 case spill_psprel:
e0c9811a
JW		 2267 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2268 ptr->r.record.x.reg, ptr->r.record.x.t,
2269 ptr->r.record.x.pspoff);
2270 break;
800eeca4 2271 case spill_sprel:
e0c9811a
JW		 2272 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2273 ptr->r.record.x.reg, ptr->r.record.x.t,
2274 ptr->r.record.x.spoff);
2275 break;
800eeca4 2276 case spill_reg:
e0c9811a
JW		 2277 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2278 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2279 ptr->r.record.x.treg, ptr->r.record.x.t);
2280 break;
800eeca4 2281 case spill_psprel_p:
e0c9811a
JW		 2282 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2283 ptr->r.record.x.ab, ptr->r.record.x.reg,
2284 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2285 break;
800eeca4 2286 case spill_sprel_p:
e0c9811a
JW		 2287 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2288 ptr->r.record.x.ab, ptr->r.record.x.reg,
2289 ptr->r.record.x.t, ptr->r.record.x.spoff);
2290 break;
800eeca4 2291 case spill_reg_p:
e0c9811a
JW		 2292 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2293 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2294 ptr->r.record.x.xy, ptr->r.record.x.treg,
2295 ptr->r.record.x.t);
800eeca4
JW		 2296 break;
2297 default:
2298 as_bad ("record_type_not_valid");
2299 break;
2300 }
2301}
2302
2303/* Given a unw_rec_list list, process all the records with
2304 the specified function. */
2305static void
2306process_unw_records (list, f)
2307 unw_rec_list *list;
2308 vbyte_func f;
2309{
2310 unw_rec_list *ptr;
2311 for (ptr = list; ptr; ptr = ptr->next)
2312 process_one_record (ptr, f);
2313}
2314
2315/* Determine the size of a record list in bytes. */
2316static int
2317calc_record_size (list)
2318 unw_rec_list *list;
2319{
2320 vbyte_count = 0;
2321 process_unw_records (list, count_output);
2322 return vbyte_count;
2323}
2324
e0c9811a
JW		 2325/* Update IMASK bitmask to reflect the fact that one or more registers
2326 of type TYPE are saved starting at instruction with index T. If N
2327 bits are set in REGMASK, it is assumed that instructions T through
2328 T+N-1 save these registers.
2329
2330 TYPE values:
2331 0: no save
2332 1: instruction saves next fp reg
2333 2: instruction saves next general reg
2334 3: instruction saves next branch reg */
2335static void
2336set_imask (region, regmask, t, type)
2337 unw_rec_list *region;
2338 unsigned long regmask;
2339 unsigned long t;
2340 unsigned int type;
2341{
2342 unsigned char *imask;
2343 unsigned long imask_size;
2344 unsigned int i;
2345 int pos;
2346
2347 imask = region->r.record.r.mask.i;
2348 imask_size = region->r.record.r.imask_size;
2349 if (!imask)
2350 {
2351 imask_size = (region->r.record.r.rlen*2 + 7)/8 + 1;
2352 imask = xmalloc (imask_size);
2353 memset (imask, 0, imask_size);
2354
2355 region->r.record.r.imask_size = imask_size;
2356 region->r.record.r.mask.i = imask;
2357 }
2358
2359 i = (t/4) + 1;
2360 pos = 2*(3 - t%4);
2361 while (regmask)
2362 {
2363 if (i >= imask_size)
2364 {
2365 as_bad ("Ignoring attempt to spill beyond end of region");
2366 return;
2367 }
2368
2369 imask[i] |= (type & 0x3) << pos;
2370
2371 regmask &= (regmask - 1);
2372 pos -= 2;
2373 if (pos < 0)
2374 {
2375 pos = 0;
2376 ++i;
2377 }
2378 }
2379}
2380
2381static int
2382count_bits (unsigned long mask)
2383{
2384 int n = 0;
2385
2386 while (mask)
2387 {
2388 mask &= mask - 1;
2389 ++n;
2390 }
2391 return n;
2392}
2393
2394unsigned long
2395slot_index (unsigned long slot_addr, unsigned long first_addr)
2396{
2397 return (3*((slot_addr >> 4) - (first_addr >> 4))
2398 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2399}
2400
800eeca4
JW		 2401/* Given a complete record list, process any records which have
2402 unresolved fields, (ie length counts for a prologue). After
2403 this has been run, all neccessary information should be available
2404 within each record to generate an image. */
2405static void
2406fixup_unw_records (list)
2407 unw_rec_list *list;
2408{
e0c9811a
JW		 2409 unw_rec_list *ptr, *region = 0;
2410 unsigned long first_addr = 0, rlen = 0, t;
2411
800eeca4
JW		 2412 for (ptr = list; ptr; ptr = ptr->next)
2413 {
2414 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2415 as_bad (" Insn slot not set in unwind record.");
e0c9811a 2416 t = slot_index (ptr->slot_number, first_addr);
800eeca4
JW		 2417 switch (ptr->r.type)
2418 {
2419 case prologue:
2420 case prologue_gr:
2421 case body:
2422 {
2423 unw_rec_list *last;
e0c9811a 2424 int size, dir_len = 0;
800eeca4 2425 unsigned long last_addr;
e0c9811a 2426
800eeca4
JW		 2427 first_addr = ptr->slot_number;
2428 ptr->slot_number = 0;
2429 /* Find either the next body/prologue start, or the end of
2430 the list, and determine the size of the region. */
e0c9811a
JW		 2431 last_addr = unwind.next_slot_number;
2432 for (last = ptr->next; last != NULL; last = last->next)
2433 if (last->r.type == prologue || last->r.type == prologue_gr
2434 || last->r.type == body)
800eeca4 2435 {
e0c9811a 2436 last_addr = last->slot_number;
800eeca4
JW		 2437 break;
2438 }
e0c9811a
JW		 2439 else if (!last->next)
2440 {
2441 /* In the absence of an explicit .body directive,
2442 the prologue ends after the last instruction
2443 covered by an unwind directive. */
2444 if (ptr->r.type != body)
2445 {
2446 last_addr = last->slot_number;
2447 switch (last->r.type)
2448 {
2449 case frgr_mem:
2450 dir_len = (count_bits (last->r.record.p.frmask)
2451 + count_bits (last->r.record.p.grmask));
2452 break;
2453 case fr_mem:
2454 case gr_mem:
2455 dir_len += count_bits (last->r.record.p.rmask);
2456 break;
2457 case br_mem:
2458 case br_gr:
2459 dir_len += count_bits (last->r.record.p.brmask);
2460 break;
2461 case gr_gr:
2462 dir_len += count_bits (last->r.record.p.grmask);
2463 break;
2464 default:
2465 dir_len = 1;
2466 break;
2467 }
2468 }
2469 break;
2470 }
2471 size = slot_index (last_addr, first_addr) + dir_len;
2472 rlen = ptr->r.record.r.rlen = size;
2473 region = ptr;
800eeca4
JW		 2474 break;
2475 }
e0c9811a
JW		 2476 case epilogue:
2477 ptr->r.record.b.t = rlen - 1 - t;
2478 break;
2479
800eeca4
JW		 2480 case mem_stack_f:
2481 case mem_stack_v:
2482 case rp_when:
2483 case pfs_when:
2484 case preds_when:
2485 case unat_when:
2486 case lc_when:
2487 case fpsr_when:
2488 case priunat_when_gr:
2489 case priunat_when_mem:
2490 case bsp_when:
2491 case bspstore_when:
2492 case rnat_when:
e0c9811a
JW		 2493 ptr->r.record.p.t = t;
2494 break;
2495
2496 case spill_reg:
2497 case spill_sprel:
2498 case spill_psprel:
2499 case spill_reg_p:
2500 case spill_sprel_p:
2501 case spill_psprel_p:
2502 ptr->r.record.x.t = t;
2503 break;
2504
2505 case frgr_mem:
2506 if (!region)
2507 {
2508 as_bad ("frgr_mem record before region record!\n");
2509 return;
2510 }
2511 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2512 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2513 set_imask (region, ptr->r.record.p.frmask, t, 1);
2514 set_imask (region, ptr->r.record.p.grmask, t, 2);
2515 break;
2516 case fr_mem:
2517 if (!region)
2518 {
2519 as_bad ("fr_mem record before region record!\n");
2520 return;
2521 }
2522 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2523 set_imask (region, ptr->r.record.p.rmask, t, 1);
2524 break;
2525 case gr_mem:
2526 if (!region)
2527 {
2528 as_bad ("gr_mem record before region record!\n");
2529 return;
2530 }
2531 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2532 set_imask (region, ptr->r.record.p.rmask, t, 2);
2533 break;
2534 case br_mem:
2535 if (!region)
2536 {
2537 as_bad ("br_mem record before region record!\n");
2538 return;
2539 }
2540 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2541 set_imask (region, ptr->r.record.p.brmask, t, 3);
2542 break;
2543
2544 case gr_gr:
2545 if (!region)
2546 {
2547 as_bad ("gr_gr record before region record!\n");
2548 return;
2549 }
2550 set_imask (region, ptr->r.record.p.grmask, t, 2);
2551 break;
2552 case br_gr:
2553 if (!region)
2554 {
2555 as_bad ("br_gr record before region record!\n");
2556 return;
2557 }
2558 set_imask (region, ptr->r.record.p.brmask, t, 3);
2559 break;
2560
2561 default:
2562 break;
800eeca4
JW		 2563 }
2564 }
2565}
2566
2567/* Generate an unwind image from a record list. Returns the number of
2568 bytes in the resulting image. The memory image itselof is returned
2569 in the 'ptr' parameter. */
2570static int
2571output_unw_records (list, ptr)
2572 unw_rec_list *list;
2573 void **ptr;
2574{
2575 int size, x, extra = 0;
2576 unsigned char *mem;
2577
2578 fixup_unw_records (list);
2579 size = calc_record_size (list);
2580
2581 /* pad to 8 byte boundry. */
2582 x = size % 8;
2583 if (x != 0)
2584 extra = 8 - x;
2585 /* Add 8 for the header + 8 more bytes for the personality offset. */
2586 mem = xmalloc (size + extra + 16);
2587
2588 vbyte_mem_ptr = mem + 8;
2589 /* Clear the padding area and personality. */
2590 memset (mem + 8 + size, 0 , extra + 8);
2591 /* Initialize the header area. */
efcc5914
JW		 2592 md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
2593 | (unwind.personality_routine
2594 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2595 : 0)
e4c58b25
JW		 2596 | ((size + extra) / 8)), /* length (dwords) */
2597 8);
800eeca4
JW		 2598
2599 process_unw_records (list, output_vbyte_mem);
2600
2601 *ptr = mem;
2602 return size + extra + 16;
2603}
2604
e0c9811a
JW		 2605static int
2606convert_expr_to_ab_reg (e, ab, regp)
2607 expressionS *e;
2608 unsigned int *ab;
2609 unsigned int *regp;
2610{
2611 unsigned int reg;
2612
2613 if (e->X_op != O_register)
2614 return 0;
2615
2616 reg = e->X_add_number;
2617 if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
2618 {
2619 *ab = 0;
2620 *regp = reg - REG_GR;
2621 }
2622 else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
2623 || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
2624 {
2625 *ab = 1;
2626 *regp = reg - REG_FR;
2627 }
2628 else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
2629 {
2630 *ab = 2;
2631 *regp = reg - REG_BR;
2632 }
2633 else
2634 {
2635 *ab = 3;
2636 switch (reg)
2637 {
2638 case REG_PR: *regp = 0; break;
2639 case REG_PSP: *regp = 1; break;
2640 case REG_PRIUNAT: *regp = 2; break;
2641 case REG_BR + 0: *regp = 3; break;
2642 case REG_AR + AR_BSP: *regp = 4; break;
2643 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2644 case REG_AR + AR_RNAT: *regp = 6; break;
2645 case REG_AR + AR_UNAT: *regp = 7; break;
2646 case REG_AR + AR_FPSR: *regp = 8; break;
2647 case REG_AR + AR_PFS: *regp = 9; break;
2648 case REG_AR + AR_LC: *regp = 10; break;
2649
2650 default:
2651 return 0;
2652 }
2653 }
2654 return 1;
2655}
2656
2657static int
2658convert_expr_to_xy_reg (e, xy, regp)
2659 expressionS *e;
2660 unsigned int *xy;
2661 unsigned int *regp;
2662{
2663 unsigned int reg;
2664
2665 if (e->X_op != O_register)
2666 return 0;
2667
2668 reg = e->X_add_number;
2669
2670 if (reg >= REG_GR && reg <= REG_GR + 127)
2671 {
2672 *xy = 0;
2673 *regp = reg - REG_GR;
2674 }
2675 else if (reg >= REG_FR && reg <= REG_FR + 127)
2676 {
2677 *xy = 1;
2678 *regp = reg - REG_FR;
2679 }
2680 else if (reg >= REG_BR && reg <= REG_BR + 7)
2681 {
2682 *xy = 2;
2683 *regp = reg - REG_BR;
2684 }
2685 else
2686 return -1;
2687 return 1;
2688}
2689
800eeca4
JW		 2690static void
2691dot_radix (dummy)
2692 int dummy;
2693{
2694 int radix;
2695
2696 SKIP_WHITESPACE ();
2697 radix = *input_line_pointer++;
2698
2699 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2700 {
2701 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2702 ignore_rest_of_line ();
2703 return;
2704 }
2705}
2706
2707/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2708static void
2709dot_special_section (which)
2710 int which;
2711{
2712 set_section ((char *) special_section_name[which]);
2713}
2714
2715static void
2716add_unwind_entry (ptr)
2717 unw_rec_list *ptr;
2718{
e0c9811a
JW		 2719 if (unwind.tail)
2720 unwind.tail->next = ptr;
800eeca4 2721 else
e0c9811a
JW		 2722 unwind.list = ptr;
2723 unwind.tail = ptr;
800eeca4
JW		 2724
2725 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW		 2726 if (unwind.current_entry == NULL)
2727 unwind.current_entry = ptr;
800eeca4
JW		 2728}
2729
2730static void
2731dot_fframe (dummy)
2732 int dummy;
2733{
2734 expressionS e;
e0c9811a 2735
800eeca4
JW		 2736 parse_operand (&e);
2737
2738 if (e.X_op != O_constant)
2739 as_bad ("Operand to .fframe must be a constant");
2740 else
e0c9811a
JW		 2741 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2742}
2743
2744static void
2745dot_vframe (dummy)
2746 int dummy;
2747{
2748 expressionS e;
2749 unsigned reg;
2750
2751 parse_operand (&e);
2752 reg = e.X_add_number - REG_GR;
2753 if (e.X_op == O_register && reg < 128)
800eeca4 2754 {
e0c9811a 2755 add_unwind_entry (output_mem_stack_v ());
30d25259
RH		 2756 if (! (unwind.prologue_mask & 2))
2757 add_unwind_entry (output_psp_gr (reg));
800eeca4 2758 }
e0c9811a
JW		 2759 else
2760 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW		 2761}
2762
2763static void
e0c9811a 2764dot_vframesp (dummy)
800eeca4
JW		 2765 int dummy;
2766{
e0c9811a
JW		 2767 expressionS e;
2768
2769 parse_operand (&e);
2770 if (e.X_op == O_constant)
2771 {
2772 add_unwind_entry (output_mem_stack_v ());
2773 add_unwind_entry (output_psp_sprel (e.X_add_number));
2774 }
2775 else
2776 as_bad ("First operand to .vframesp must be a general register");
2777}
2778
2779static void
2780dot_vframepsp (dummy)
2781 int dummy;
2782{
2783 expressionS e;
2784
2785 parse_operand (&e);
2786 if (e.X_op == O_constant)
2787 {
2788 add_unwind_entry (output_mem_stack_v ());
2789 add_unwind_entry (output_psp_sprel (e.X_add_number));
2790 }
2791 else
2792 as_bad ("First operand to .vframepsp must be a general register");
800eeca4
JW		 2793}
2794
2795static void
2796dot_save (dummy)
2797 int dummy;
2798{
2799 expressionS e1, e2;
2800 int sep;
2801 int reg1, reg2;
2802
2803 sep = parse_operand (&e1);
2804 if (sep != ',')
2805 as_bad ("No second operand to .save");
2806 sep = parse_operand (&e2);
2807
e0c9811a 2808 reg1 = e1.X_add_number;
800eeca4
JW		 2809 reg2 = e2.X_add_number - REG_GR;
2810
2811 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 2812 if (e1.X_op == O_register)
800eeca4
JW		 2813 {
2814 if (e2.X_op == O_register && reg2 >=0 && reg2 < 128)
2815 {
2816 switch (reg1)
2817 {
e0c9811a 2818 case REG_AR + AR_BSP:
800eeca4
JW		 2819 add_unwind_entry (output_bsp_when ());
2820 add_unwind_entry (output_bsp_gr (reg2));
2821 break;
e0c9811a 2822 case REG_AR + AR_BSPSTORE:
800eeca4
JW		 2823 add_unwind_entry (output_bspstore_when ());
2824 add_unwind_entry (output_bspstore_gr (reg2));
2825 break;
e0c9811a 2826 case REG_AR + AR_RNAT:
800eeca4
JW		 2827 add_unwind_entry (output_rnat_when ());
2828 add_unwind_entry (output_rnat_gr (reg2));
2829 break;
e0c9811a 2830 case REG_AR+AR_UNAT:
800eeca4
JW		 2831 add_unwind_entry (output_unat_when ());
2832 add_unwind_entry (output_unat_gr (reg2));
2833 break;
e0c9811a 2834 case REG_AR+AR_FPSR:
800eeca4
JW		 2835 add_unwind_entry (output_fpsr_when ());
2836 add_unwind_entry (output_fpsr_gr (reg2));
2837 break;
e0c9811a 2838 case REG_AR+AR_PFS:
800eeca4 2839 add_unwind_entry (output_pfs_when ());
30d25259
RH		 2840 if (! (unwind.prologue_mask & 4))
2841 add_unwind_entry (output_pfs_gr (reg2));
800eeca4 2842 break;
e0c9811a 2843 case REG_AR+AR_LC:
800eeca4
JW		 2844 add_unwind_entry (output_lc_when ());
2845 add_unwind_entry (output_lc_gr (reg2));
2846 break;
e0c9811a 2847 case REG_BR:
800eeca4 2848 add_unwind_entry (output_rp_when ());
30d25259
RH		 2849 if (! (unwind.prologue_mask & 8))
2850 add_unwind_entry (output_rp_gr (reg2));
800eeca4 2851 break;
e0c9811a
JW		 2852 case REG_PR:
2853 add_unwind_entry (output_preds_when ());
30d25259
RH		 2854 if (! (unwind.prologue_mask & 1))
2855 add_unwind_entry (output_preds_gr (reg2));
e0c9811a
JW		 2856 break;
2857 case REG_PRIUNAT:
2858 add_unwind_entry (output_priunat_when_gr ());
2859 add_unwind_entry (output_priunat_gr (reg2));
2860 break;
800eeca4 2861 default:
e0c9811a 2862 as_bad ("First operand not a valid register");
800eeca4
JW		 2863 }
2864 }
2865 else
2866 as_bad (" Second operand not a valid register");
2867 }
2868 else
e0c9811a 2869 as_bad ("First operand not a register");
800eeca4
JW		 2870}
2871
2872static void
2873dot_restore (dummy)
2874 int dummy;
2875{
e0c9811a
JW		 2876 expressionS e1, e2;
2877 unsigned long ecount = 0;
2878 int sep;
2879
2880 sep = parse_operand (&e1);
2881 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2882 {
2883 as_bad ("First operand to .restore must be stack pointer (sp)");
2884 return;
2885 }
2886
2887 if (sep == ',')
2888 {
2889 parse_operand (&e2);
2890 if (e1.X_op != O_constant)
2891 {
2892 as_bad ("Second operand to .restore must be constant");
2893 return;
2894 }
2895 ecount = e1.X_op;
2896 }
2897 add_unwind_entry (output_epilogue (ecount));
2898}
2899
2900static void
2901dot_restorereg (dummy)
2902 int dummy;
2903{
2904 unsigned int ab, reg;
2905 expressionS e;
2906
2907 parse_operand (&e);
2908
2909 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
2910 {
2911 as_bad ("First operand to .restorereg must be a preserved register");
2912 return;
2913 }
2914 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
2915}
2916
2917static void
2918dot_restorereg_p (dummy)
2919 int dummy;
2920{
2921 unsigned int qp, ab, reg;
2922 expressionS e1, e2;
2923 int sep;
2924
2925 sep = parse_operand (&e1);
2926 if (sep != ',')
2927 {
2928 as_bad ("No second operand to .restorereg.p");
2929 return;
2930 }
2931
2932 parse_operand (&e2);
2933
2934 qp = e1.X_add_number - REG_P;
2935 if (e1.X_op != O_register || qp > 63)
2936 {
2937 as_bad ("First operand to .restorereg.p must be a predicate");
2938 return;
2939 }
2940
2941 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
2942 {
2943 as_bad ("Second operand to .restorereg.p must be a preserved register");
2944 return;
2945 }
2946 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW		 2947}
2948
2949static int
2950generate_unwind_image ()
2951{
2952 int size;
2953 unsigned char *unw_rec;
800eeca4 2954
10850f29
JW		 2955 /* Force out pending instructions, to make sure all unwind records have
2956 a valid slot_number field. */
2957 ia64_flush_insns ();
2958
800eeca4 2959 /* Generate the unwind record. */
150f24a2 2960 size = output_unw_records (unwind.list, (void **) &unw_rec);
e0c9811a
JW		 2961 if (size % 8 != 0)
2962 as_bad ("Unwind record is not a multiple of 8 bytes.");
800eeca4
JW		 2963
2964 /* If there are unwind records, switch sections, and output the info. */
2965 if (size != 0)
2966 {
800eeca4 2967 unsigned char *where;
800eeca4 2968 expressionS exp;
800eeca4
JW		 2969 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
2970
2971 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 2972 unwind.info = expr_build_dot ();
800eeca4
JW		 2973
2974 where = (unsigned char *)frag_more (size);
2975
2976 /* Issue a label for this address, and keep track of it to put it
2977 in the unwind section. */
2978
2979 /* Copy the information from the unwind record into this section. The
2980 data is already in the correct byte order. */
2981 memcpy (where, unw_rec, size);
2982 /* Add the personality address to the image. */
e0c9811a 2983 if (unwind.personality_routine != 0)
800eeca4
JW		 2984 {
2985 exp.X_op = O_symbol;
e0c9811a 2986 exp.X_add_symbol = unwind.personality_routine;
800eeca4
JW		 2987 exp.X_add_number = 0;
2988 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
2989 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
e0c9811a 2990 unwind.personality_routine = 0;
800eeca4
JW		 2991 }
2992 obj_elf_previous (0);
2993 }
2994
e0c9811a
JW		 2995 free_list_records (unwind.list);
2996 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW		 2997
2998 return size;
2999}
3000
3001static void
3002dot_handlerdata (dummy)
3003 int dummy;
3004{
3005 generate_unwind_image ();
e0c9811a 3006 demand_empty_rest_of_line ();
800eeca4
JW		 3007}
3008
3009static void
3010dot_unwentry (dummy)
3011 int dummy;
3012{
e0c9811a 3013 demand_empty_rest_of_line ();
800eeca4
JW		 3014}
3015
3016static void
3017dot_altrp (dummy)
3018 int dummy;
3019{
e0c9811a
JW		 3020 expressionS e;
3021 unsigned reg;
3022
3023 parse_operand (&e);
3024 reg = e.X_add_number - REG_BR;
3025 if (e.X_op == O_register && reg < 8)
3026 add_unwind_entry (output_rp_br (reg));
3027 else
3028 as_bad ("First operand not a valid branch register");
800eeca4
JW		 3029}
3030
3031static void
e0c9811a
JW		 3032dot_savemem (psprel)
3033 int psprel;
800eeca4
JW		 3034{
3035 expressionS e1, e2;
3036 int sep;
3037 int reg1, val;
3038
3039 sep = parse_operand (&e1);
3040 if (sep != ',')
e0c9811a 3041 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW		 3042 sep = parse_operand (&e2);
3043
e0c9811a 3044 reg1 = e1.X_add_number;
800eeca4
JW		 3045 val = e2.X_add_number;
3046
3047 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3048 if (e1.X_op == O_register)
800eeca4
JW		 3049 {
3050 if (e2.X_op == O_constant)
3051 {
3052 switch (reg1)
3053 {
e0c9811a 3054 case REG_AR + AR_BSP:
800eeca4 3055 add_unwind_entry (output_bsp_when ());
e0c9811a
JW		 3056 add_unwind_entry ((psprel
3057 ? output_bsp_psprel
3058 : output_bsp_sprel) (val));
800eeca4 3059 break;
e0c9811a 3060 case REG_AR + AR_BSPSTORE:
800eeca4 3061 add_unwind_entry (output_bspstore_when ());
e0c9811a
JW		 3062 add_unwind_entry ((psprel
3063 ? output_bspstore_psprel
3064 : output_bspstore_sprel) (val));
800eeca4 3065 break;
e0c9811a 3066 case REG_AR + AR_RNAT:
800eeca4 3067 add_unwind_entry (output_rnat_when ());
e0c9811a
JW		 3068 add_unwind_entry ((psprel
3069 ? output_rnat_psprel
3070 : output_rnat_sprel) (val));
800eeca4 3071 break;
e0c9811a 3072 case REG_AR + AR_UNAT:
800eeca4 3073 add_unwind_entry (output_unat_when ());
e0c9811a
JW		 3074 add_unwind_entry ((psprel
3075 ? output_unat_psprel
3076 : output_unat_sprel) (val));
800eeca4 3077 break;
e0c9811a 3078 case REG_AR + AR_FPSR:
800eeca4 3079 add_unwind_entry (output_fpsr_when ());
e0c9811a
JW		 3080 add_unwind_entry ((psprel
3081 ? output_fpsr_psprel
3082 : output_fpsr_sprel) (val));
800eeca4 3083 break;
e0c9811a 3084 case REG_AR + AR_PFS:
800eeca4 3085 add_unwind_entry (output_pfs_when ());
e0c9811a
JW		 3086 add_unwind_entry ((psprel
3087 ? output_pfs_psprel
3088 : output_pfs_sprel) (val));
800eeca4 3089 break;
e0c9811a 3090 case REG_AR + AR_LC:
800eeca4 3091 add_unwind_entry (output_lc_when ());
e0c9811a
JW		 3092 add_unwind_entry ((psprel
3093 ? output_lc_psprel
3094 : output_lc_sprel) (val));
800eeca4 3095 break;
e0c9811a 3096 case REG_BR:
800eeca4 3097 add_unwind_entry (output_rp_when ());
e0c9811a
JW		 3098 add_unwind_entry ((psprel
3099 ? output_rp_psprel
3100 : output_rp_sprel) (val));
800eeca4 3101 break;
e0c9811a 3102 case REG_PR:
800eeca4 3103 add_unwind_entry (output_preds_when ());
e0c9811a
JW		 3104 add_unwind_entry ((psprel
3105 ? output_preds_psprel
3106 : output_preds_sprel) (val));
3107 break;
3108 case REG_PRIUNAT:
3109 add_unwind_entry (output_priunat_when_mem ());
3110 add_unwind_entry ((psprel
3111 ? output_priunat_psprel
3112 : output_priunat_sprel) (val));
800eeca4
JW		 3113 break;
3114 default:
e0c9811a 3115 as_bad ("First operand not a valid register");
800eeca4
JW		 3116 }
3117 }
3118 else
3119 as_bad (" Second operand not a valid constant");
3120 }
3121 else
e0c9811a 3122 as_bad ("First operand not a register");
800eeca4
JW		 3123}
3124
3125static void
3126dot_saveg (dummy)
3127 int dummy;
3128{
3129 expressionS e1, e2;
3130 int sep;
3131 sep = parse_operand (&e1);
3132 if (sep == ',')
3133 parse_operand (&e2);
3134
3135 if (e1.X_op != O_constant)
3136 as_bad ("First operand to .save.g must be a constant.");
3137 else
3138 {
3139 int grmask = e1.X_add_number;
3140 if (sep != ',')
3141 add_unwind_entry (output_gr_mem (grmask));
3142 else
3143 {
3144 int reg = e2.X_add_number - REG_GR;
3145 if (e2.X_op == O_register && reg >=0 && reg < 128)
3146 add_unwind_entry (output_gr_gr (grmask, reg));
3147 else
3148 as_bad ("Second operand is an invalid register.");
3149 }
3150 }
3151}
3152
3153static void
3154dot_savef (dummy)
3155 int dummy;
3156{
e0c9811a 3157 expressionS e1;
800eeca4
JW		 3158 int sep;
3159 sep = parse_operand (&e1);
3160
3161 if (e1.X_op != O_constant)
3162 as_bad ("Operand to .save.f must be a constant.");
3163 else
e0c9811a 3164 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW		 3165}
3166
3167static void
3168dot_saveb (dummy)
3169 int dummy;
3170{
e0c9811a
JW		 3171 expressionS e1, e2;
3172 unsigned int reg;
3173 unsigned char sep;
3174 int brmask;
3175
800eeca4 3176 sep = parse_operand (&e1);
800eeca4 3177 if (e1.X_op != O_constant)
800eeca4 3178 {
e0c9811a
JW		 3179 as_bad ("First operand to .save.b must be a constant.");
3180 return;
800eeca4 3181 }
e0c9811a
JW		 3182 brmask = e1.X_add_number;
3183
3184 if (sep == ',')
3185 {
3186 sep = parse_operand (&e2);
3187 reg = e2.X_add_number - REG_GR;
3188 if (e2.X_op != O_register || reg > 127)
3189 {
3190 as_bad ("Second operand to .save.b must be a general register.");
3191 return;
3192 }
3193 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3194 }
3195 else
3196 add_unwind_entry (output_br_mem (brmask));
3197
3198 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3199 ignore_rest_of_line ();
800eeca4
JW		 3200}
3201
3202static void
3203dot_savegf (dummy)
3204 int dummy;
3205{
3206 expressionS e1, e2;
3207 int sep;
3208 sep = parse_operand (&e1);
3209 if (sep == ',')
3210 parse_operand (&e2);
3211
3212 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3213 as_bad ("Both operands of .save.gf must be constants.");
3214 else
3215 {
3216 int grmask = e1.X_add_number;
3217 int frmask = e2.X_add_number;
3218 add_unwind_entry (output_frgr_mem (grmask, frmask));
3219 }
3220}
3221
3222static void
3223dot_spill (dummy)
3224 int dummy;
3225{
3226 expressionS e;
e0c9811a
JW		 3227 unsigned char sep;
3228
3229 sep = parse_operand (&e);
3230 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3231 ignore_rest_of_line ();
800eeca4
JW		 3232
3233 if (e.X_op != O_constant)
3234 as_bad ("Operand to .spill must be a constant");
3235 else
e0c9811a
JW		 3236 add_unwind_entry (output_spill_base (e.X_add_number));
3237}
3238
3239static void
3240dot_spillreg (dummy)
3241 int dummy;
3242{
3243 int sep, ab, xy, reg, treg;
3244 expressionS e1, e2;
3245
3246 sep = parse_operand (&e1);
3247 if (sep != ',')
3248 {
3249 as_bad ("No second operand to .spillreg");
3250 return;
3251 }
3252
3253 parse_operand (&e2);
3254
3255 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3256 {
e0c9811a
JW		 3257 as_bad ("First operand to .spillreg must be a preserved register");
3258 return;
800eeca4 3259 }
e0c9811a
JW		 3260
3261 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3262 {
3263 as_bad ("Second operand to .spillreg must be a register");
3264 return;
3265 }
3266
3267 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3268}
3269
3270static void
3271dot_spillmem (psprel)
3272 int psprel;
3273{
3274 expressionS e1, e2;
3275 int sep, ab, reg;
3276
3277 sep = parse_operand (&e1);
3278 if (sep != ',')
3279 {
3280 as_bad ("Second operand missing");
3281 return;
3282 }
3283
3284 parse_operand (&e2);
3285
3286 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3287 {
3288 as_bad ("First operand to .spill%s must be a preserved register",
3289 psprel ? "psp" : "sp");
3290 return;
3291 }
3292
3293 if (e2.X_op != O_constant)
3294 {
3295 as_bad ("Second operand to .spill%s must be a constant",
3296 psprel ? "psp" : "sp");
3297 return;
3298 }
3299
3300 if (psprel)
3301 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3302 else
3303 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3304}
3305
3306static void
3307dot_spillreg_p (dummy)
3308 int dummy;
3309{
3310 int sep, ab, xy, reg, treg;
3311 expressionS e1, e2, e3;
3312 unsigned int qp;
3313
3314 sep = parse_operand (&e1);
3315 if (sep != ',')
3316 {
3317 as_bad ("No second and third operand to .spillreg.p");
3318 return;
3319 }
3320
3321 sep = parse_operand (&e2);
3322 if (sep != ',')
3323 {
3324 as_bad ("No third operand to .spillreg.p");
3325 return;
3326 }
3327
3328 parse_operand (&e3);
3329
3330 qp = e1.X_add_number - REG_P;
3331
3332 if (e1.X_op != O_register || qp > 63)
3333 {
3334 as_bad ("First operand to .spillreg.p must be a predicate");
3335 return;
3336 }
3337
3338 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3339 {
3340 as_bad ("Second operand to .spillreg.p must be a preserved register");
3341 return;
3342 }
3343
3344 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3345 {
3346 as_bad ("Third operand to .spillreg.p must be a register");
3347 return;
3348 }
3349
3350 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3351}
3352
3353static void
3354dot_spillmem_p (psprel)
3355 int psprel;
3356{
3357 expressionS e1, e2, e3;
3358 int sep, ab, reg;
3359 unsigned int qp;
3360
3361 sep = parse_operand (&e1);
3362 if (sep != ',')
3363 {
3364 as_bad ("Second operand missing");
3365 return;
3366 }
3367
3368 parse_operand (&e2);
3369 if (sep != ',')
3370 {
3371 as_bad ("Second operand missing");
3372 return;
3373 }
3374
3375 parse_operand (&e3);
3376
3377 qp = e1.X_add_number - REG_P;
3378 if (e1.X_op != O_register || qp > 63)
3379 {
3380 as_bad ("First operand to .spill%s_p must be a predicate",
3381 psprel ? "psp" : "sp");
3382 return;
3383 }
3384
3385 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3386 {
3387 as_bad ("Second operand to .spill%s_p must be a preserved register",
3388 psprel ? "psp" : "sp");
3389 return;
3390 }
3391
3392 if (e3.X_op != O_constant)
3393 {
3394 as_bad ("Third operand to .spill%s_p must be a constant",
3395 psprel ? "psp" : "sp");
3396 return;
3397 }
3398
3399 if (psprel)
3400 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3401 else
3402 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3403}
3404
3405static void
3406dot_label_state (dummy)
3407 int dummy;
3408{
3409 expressionS e;
3410
3411 parse_operand (&e);
3412 if (e.X_op != O_constant)
3413 {
3414 as_bad ("Operand to .label_state must be a constant");
3415 return;
3416 }
3417 add_unwind_entry (output_label_state (e.X_add_number));
3418}
3419
3420static void
3421dot_copy_state (dummy)
3422 int dummy;
3423{
3424 expressionS e;
3425
3426 parse_operand (&e);
3427 if (e.X_op != O_constant)
3428 {
3429 as_bad ("Operand to .copy_state must be a constant");
3430 return;
3431 }
3432 add_unwind_entry (output_copy_state (e.X_add_number));
800eeca4
JW		 3433}
3434
3435static void
3436dot_unwabi (dummy)
3437 int dummy;
3438{
e0c9811a
JW		 3439 expressionS e1, e2;
3440 unsigned char sep;
3441
3442 sep = parse_operand (&e1);
3443 if (sep != ',')
3444 {
3445 as_bad ("Second operand to .unwabi missing");
3446 return;
3447 }
3448 sep = parse_operand (&e2);
3449 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3450 ignore_rest_of_line ();
3451
3452 if (e1.X_op != O_constant)
3453 {
3454 as_bad ("First operand to .unwabi must be a constant");
3455 return;
3456 }
3457
3458 if (e2.X_op != O_constant)
3459 {
3460 as_bad ("Second operand to .unwabi must be a constant");
3461 return;
3462 }
3463
3464 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW		 3465}
3466
3467static void
3468dot_personality (dummy)
3469 int dummy;
3470{
3471 char *name, *p, c;
3472 SKIP_WHITESPACE ();
3473 name = input_line_pointer;
3474 c = get_symbol_end ();
3475 p = input_line_pointer;
e0c9811a 3476 unwind.personality_routine = symbol_find_or_make (name);
800eeca4
JW		 3477 *p = c;
3478 SKIP_WHITESPACE ();
3479 demand_empty_rest_of_line ();
3480}
3481
3482static void
3483dot_proc (dummy)
3484 int dummy;
3485{
3486 char *name, *p, c;
3487 symbolS *sym;
3488
e0c9811a
JW		 3489 unwind.proc_start = expr_build_dot ();
3490 /* Parse names of main and alternate entry points and mark them as
800eeca4
JW		 3491 function symbols: */
3492 while (1)
3493 {
3494 SKIP_WHITESPACE ();
3495 name = input_line_pointer;
3496 c = get_symbol_end ();
3497 p = input_line_pointer;
3498 sym = symbol_find_or_make (name);
e0c9811a 3499 if (unwind.proc_start == 0)
800eeca4 3500 {
e0c9811a 3501 unwind.proc_start = sym;
800eeca4
JW		 3502 }
3503 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3504 *p = c;
3505 SKIP_WHITESPACE ();
3506 if (*input_line_pointer != ',')
3507 break;
3508 ++input_line_pointer;
3509 }
3510 demand_empty_rest_of_line ();
3511 ia64_do_align (16);
3512
e0c9811a
JW		 3513 unwind.list = unwind.tail = unwind.current_entry = NULL;
3514 unwind.personality_routine = 0;
800eeca4
JW		 3515}
3516
3517static void
3518dot_body (dummy)
3519 int dummy;
3520{
e0c9811a 3521 unwind.prologue = 0;
30d25259
RH		 3522 unwind.prologue_mask = 0;
3523
800eeca4 3524 add_unwind_entry (output_body ());
e0c9811a 3525 demand_empty_rest_of_line ();
800eeca4
JW		 3526}
3527
3528static void
3529dot_prologue (dummy)
3530 int dummy;
3531{
e0c9811a 3532 unsigned char sep;
30d25259 3533 int mask = 0, grsave;
e0c9811a 3534
e0c9811a 3535 if (!is_it_end_of_statement ())
800eeca4
JW		 3536 {
3537 expressionS e1, e2;
800eeca4
JW		 3538 sep = parse_operand (&e1);
3539 if (sep != ',')
3540 as_bad ("No second operand to .prologue");
3541 sep = parse_operand (&e2);
e0c9811a
JW		 3542 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3543 ignore_rest_of_line ();
800eeca4
JW		 3544
3545 if (e1.X_op == O_constant)
3546 {
30d25259
RH		 3547 mask = e1.X_add_number;
3548
800eeca4 3549 if (e2.X_op == O_constant)
30d25259
RH		 3550 grsave = e2.X_add_number;
3551 else if (e2.X_op == O_register
3552 && (grsave = e2.X_add_number - REG_GR) < 128)
3553 ;
800eeca4 3554 else
30d25259
RH		 3555 as_bad ("Second operand not a constant or general register");
3556
3557 add_unwind_entry (output_prologue_gr (mask, grsave));
800eeca4
JW		 3558 }
3559 else
3560 as_bad ("First operand not a constant");
3561 }
3562 else
3563 add_unwind_entry (output_prologue ());
30d25259
RH		 3564
3565 unwind.prologue = 1;
3566 unwind.prologue_mask = mask;
800eeca4
JW		 3567}
3568
3569static void
3570dot_endp (dummy)
3571 int dummy;
3572{
3573 expressionS e;
3574 unsigned char *ptr;
800eeca4
JW		 3575 long where;
3576 segT saved_seg;
3577 subsegT saved_subseg;
3578
3579 saved_seg = now_seg;
3580 saved_subseg = now_subseg;
3581
3582 expression (&e);
3583 demand_empty_rest_of_line ();
3584
3585 insn_group_break (1, 0, 0);
800eeca4
JW		 3586
3587 /* If there was a .handlerdata, we haven't generated an image yet. */
e0c9811a 3588 if (unwind.info == 0)
800eeca4
JW		 3589 {
3590 generate_unwind_image ();
3591 }
3592
3593 subseg_set (md.last_text_seg, 0);
e0c9811a 3594 unwind.proc_end = expr_build_dot ();
800eeca4
JW		 3595
3596 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3597 ptr = frag_more (24);
3598 where = frag_now_fix () - 24;
3599
3600 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3601 e.X_op = O_pseudo_fixup;
3602 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3603 e.X_add_number = 0;
e0c9811a 3604 e.X_add_symbol = unwind.proc_start;
800eeca4
JW		 3605 ia64_cons_fix_new (frag_now, where, 8, &e);
3606
3607 e.X_op = O_pseudo_fixup;
3608 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3609 e.X_add_number = 0;
e0c9811a 3610 e.X_add_symbol = unwind.proc_end;
800eeca4
JW		 3611 ia64_cons_fix_new (frag_now, where + 8, 8, &e);
3612
e0c9811a 3613 if (unwind.info != 0)
800eeca4
JW		 3614 {
3615 e.X_op = O_pseudo_fixup;
3616 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3617 e.X_add_number = 0;
e0c9811a 3618 e.X_add_symbol = unwind.info;
800eeca4
JW		 3619 ia64_cons_fix_new (frag_now, where + 16, 8, &e);
3620 }
3621 else
3622 md_number_to_chars (ptr + 16, 0, 8);
3623
3624 subseg_set (saved_seg, saved_subseg);
e0c9811a 3625 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW		 3626}
3627
3628static void
3629dot_template (template)
3630 int template;
3631{
3632 CURR_SLOT.user_template = template;
3633}
3634
3635static void
3636dot_regstk (dummy)
3637 int dummy;
3638{
3639 int ins, locs, outs, rots;
3640
3641 if (is_it_end_of_statement ())
3642 ins = locs = outs = rots = 0;
3643 else
3644 {
3645 ins = get_absolute_expression ();
3646 if (*input_line_pointer++ != ',')
3647 goto err;
3648 locs = get_absolute_expression ();
3649 if (*input_line_pointer++ != ',')
3650 goto err;
3651 outs = get_absolute_expression ();
3652 if (*input_line_pointer++ != ',')
3653 goto err;
3654 rots = get_absolute_expression ();
3655 }
3656 set_regstack (ins, locs, outs, rots);
3657 return;
3658
3659 err:
3660 as_bad ("Comma expected");
3661 ignore_rest_of_line ();
3662}
3663
3664static void
3665dot_rot (type)
3666 int type;
3667{
3668 unsigned num_regs, num_alloced = 0;
3669 struct dynreg **drpp, *dr;
3670 int ch, base_reg = 0;
3671 char *name, *start;
3672 size_t len;
3673
3674 switch (type)
3675 {
3676 case DYNREG_GR: base_reg = REG_GR + 32; break;
3677 case DYNREG_FR: base_reg = REG_FR + 32; break;
3678 case DYNREG_PR: base_reg = REG_P + 16; break;
3679 default: break;
3680 }
3681
3682 /* first, remove existing names from hash table: */
3683 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3684 {
3685 hash_delete (md.dynreg_hash, dr->name);
3686 dr->num_regs = 0;
3687 }
3688
3689 drpp = &md.dynreg[type];
3690 while (1)
3691 {
3692 start = input_line_pointer;
3693 ch = get_symbol_end ();
3694 *input_line_pointer = ch;
3695 len = (input_line_pointer - start);
3696
3697 SKIP_WHITESPACE ();
3698 if (*input_line_pointer != '[')
3699 {
3700 as_bad ("Expected '['");
3701 goto err;
3702 }
3703 ++input_line_pointer; /* skip '[' */
3704
3705 num_regs = get_absolute_expression ();
3706
3707 if (*input_line_pointer++ != ']')
3708 {
3709 as_bad ("Expected ']'");
3710 goto err;
3711 }
3712 SKIP_WHITESPACE ();
3713
3714 num_alloced += num_regs;
3715 switch (type)
3716 {
3717 case DYNREG_GR:
3718 if (num_alloced > md.rot.num_regs)
3719 {
3720 as_bad ("Used more than the declared %d rotating registers",
3721 md.rot.num_regs);
3722 goto err;
3723 }
3724 break;
3725 case DYNREG_FR:
3726 if (num_alloced > 96)
3727 {
3728 as_bad ("Used more than the available 96 rotating registers");
3729 goto err;
3730 }
3731 break;
3732 case DYNREG_PR:
3733 if (num_alloced > 48)
3734 {
3735 as_bad ("Used more than the available 48 rotating registers");
3736 goto err;
3737 }
3738 break;
3739
3740 default:
3741 break;
3742 }
3743
3744 name = obstack_alloc (&notes, len + 1);
3745 memcpy (name, start, len);
3746 name[len] = '\0';
3747
3748 if (!*drpp)
3749 {
3750 *drpp = obstack_alloc (&notes, sizeof (*dr));
3751 memset (*drpp, 0, sizeof (*dr));
3752 }
3753
3754 dr = *drpp;
3755 dr->name = name;
3756 dr->num_regs = num_regs;
3757 dr->base = base_reg;
3758 drpp = &dr->next;
3759 base_reg += num_regs;
3760
3761 if (hash_insert (md.dynreg_hash, name, dr))
3762 {
3763 as_bad ("Attempt to redefine register set `%s'", name);
3764 goto err;
3765 }
3766
3767 if (*input_line_pointer != ',')
3768 break;
3769 ++input_line_pointer; /* skip comma */
3770 SKIP_WHITESPACE ();
3771 }
3772 demand_empty_rest_of_line ();
3773 return;
3774
3775 err:
3776 ignore_rest_of_line ();
3777}
3778
3779static void
3780dot_byteorder (byteorder)
3781 int byteorder;
3782{
3783 target_big_endian = byteorder;
3784}
3785
3786static void
3787dot_psr (dummy)
3788 int dummy;
3789{
3790 char *option;
3791 int ch;
3792
3793 while (1)
3794 {
3795 option = input_line_pointer;
3796 ch = get_symbol_end ();
3797 if (strcmp (option, "lsb") == 0)
3798 md.flags &= ~EF_IA_64_BE;
3799 else if (strcmp (option, "msb") == 0)
3800 md.flags |= EF_IA_64_BE;
3801 else if (strcmp (option, "abi32") == 0)
3802 md.flags &= ~EF_IA_64_ABI64;
3803 else if (strcmp (option, "abi64") == 0)
3804 md.flags |= EF_IA_64_ABI64;
3805 else
3806 as_bad ("Unknown psr option `%s'", option);
3807 *input_line_pointer = ch;
3808
3809 SKIP_WHITESPACE ();
3810 if (*input_line_pointer != ',')
3811 break;
3812
3813 ++input_line_pointer;
3814 SKIP_WHITESPACE ();
3815 }
3816 demand_empty_rest_of_line ();
3817}
3818
3819static void
3820dot_alias (dummy)
3821 int dummy;
3822{
3823 as_bad (".alias not implemented yet");
3824}
3825
3826static void
3827dot_ln (dummy)
3828 int dummy;
3829{
3830 new_logical_line (0, get_absolute_expression ());
3831 demand_empty_rest_of_line ();
3832}
3833
3834static char*
3835parse_section_name ()
3836{
3837 char *name;
3838 int len;
3839
3840 SKIP_WHITESPACE ();
3841 if (*input_line_pointer != '"')
3842 {
3843 as_bad ("Missing section name");
3844 ignore_rest_of_line ();
3845 return 0;
3846 }
3847 name = demand_copy_C_string (&len);
3848 if (!name)
3849 {
3850 ignore_rest_of_line ();
3851 return 0;
3852 }
3853 SKIP_WHITESPACE ();
3854 if (*input_line_pointer != ',')
3855 {
3856 as_bad ("Comma expected after section name");
3857 ignore_rest_of_line ();
3858 return 0;
3859 }
3860 ++input_line_pointer; /* skip comma */
3861 return name;
3862}
3863
3864static void
3865dot_xdata (size)
3866 int size;
3867{
3868 char *name = parse_section_name ();
3869 if (!name)
3870 return;
3871
3872 set_section (name);
3873 cons (size);
3874 obj_elf_previous (0);
3875}
3876
3877/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3878static void
3879stmt_float_cons (kind)
3880 int kind;
3881{
3882 size_t size;
3883
3884 switch (kind)
3885 {
3886 case 'd': size = 8; break;
3887 case 'x': size = 10; break;
3888
3889 case 'f':
3890 default:
3891 size = 4;
3892 break;
3893 }
3894 ia64_do_align (size);
3895 float_cons (kind);
3896}
3897
3898static void
3899stmt_cons_ua (size)
3900 int size;
3901{
3902 int saved_auto_align = md.auto_align;
3903
3904 md.auto_align = 0;
3905 cons (size);
3906 md.auto_align = saved_auto_align;
3907}
3908
3909static void
3910dot_xfloat_cons (kind)
3911 int kind;
3912{
3913 char *name = parse_section_name ();
3914 if (!name)
3915 return;
3916
3917 set_section (name);
3918 stmt_float_cons (kind);
3919 obj_elf_previous (0);
3920}
3921
3922static void
3923dot_xstringer (zero)
3924 int zero;
3925{
3926 char *name = parse_section_name ();
3927 if (!name)
3928 return;
3929
3930 set_section (name);
3931 stringer (zero);
3932 obj_elf_previous (0);
3933}
3934
3935static void
3936dot_xdata_ua (size)
3937 int size;
3938{
3939 int saved_auto_align = md.auto_align;
3940 char *name = parse_section_name ();
3941 if (!name)
3942 return;
3943
3944 set_section (name);
3945 md.auto_align = 0;
3946 cons (size);
3947 md.auto_align = saved_auto_align;
3948 obj_elf_previous (0);
3949}
3950
3951static void
3952dot_xfloat_cons_ua (kind)
3953 int kind;
3954{
3955 int saved_auto_align = md.auto_align;
3956 char *name = parse_section_name ();
3957 if (!name)
3958 return;
3959
3960 set_section (name);
3961 md.auto_align = 0;
3962 stmt_float_cons (kind);
3963 md.auto_align = saved_auto_align;
3964 obj_elf_previous (0);
3965}
3966
3967/* .reg.val <regname>,value */
3968static void
3969dot_reg_val (dummy)
3970 int dummy;
3971{
3972 expressionS reg;
3973
3974 expression (&reg);
3975 if (reg.X_op != O_register)
3976 {
3977 as_bad (_("Register name expected"));
3978 ignore_rest_of_line ();
3979 }
3980 else if (*input_line_pointer++ != ',')
3981 {
3982 as_bad (_("Comma expected"));
3983 ignore_rest_of_line ();
3984 }
3985 else
3986 {
3987 valueT value = get_absolute_expression ();
3988 int regno = reg.X_add_number;
3989 if (regno < REG_GR || regno > REG_GR+128)
3990 as_warn (_("Register value annotation ignored"));
3991 else
3992 {
3993 gr_values[regno-REG_GR].known = 1;
3994 gr_values[regno-REG_GR].value = value;
3995 gr_values[regno-REG_GR].path = md.path;
3996 }
3997 }
3998 demand_empty_rest_of_line ();
3999}
4000
4001/* select dv checking mode
4002 .auto
4003 .explicit
4004 .default
4005
4006 A stop is inserted when changing modes
4007 */
4008static void
4009dot_dv_mode (type)
4010 int type;
4011{
4012 if (md.manual_bundling)
4013 as_warn (_("Directive invalid within a bundle"));
4014
4015 if (type == 'E' || type == 'A')
4016 md.mode_explicitly_set = 0;
4017 else
4018 md.mode_explicitly_set = 1;
4019
4020 md.detect_dv = 1;
4021 switch (type)
4022 {
4023 case 'A':
4024 case 'a':
4025 if (md.explicit_mode)
4026 insn_group_break (1, 0, 0);
4027 md.explicit_mode = 0;
4028 break;
4029 case 'E':
4030 case 'e':
4031 if (!md.explicit_mode)
4032 insn_group_break (1, 0, 0);
4033 md.explicit_mode = 1;
4034 break;
4035 default:
4036 case 'd':
4037 if (md.explicit_mode != md.default_explicit_mode)
4038 insn_group_break (1, 0, 0);
4039 md.explicit_mode = md.default_explicit_mode;
4040 md.mode_explicitly_set = 0;
4041 break;
4042 }
4043}
4044
4045static void
4046print_prmask (mask)
4047 valueT mask;
4048{
4049 int regno;
4050 char *comma = "";
4051 for (regno = 0;regno < 64;regno++)
4052 {
4053 if (mask & ((valueT)1<<regno))
4054 {
4055 fprintf (stderr, "%s p%d", comma, regno);
4056 comma = ",";
4057 }
4058 }
4059}
4060
4061/*
4062 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4063 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4064 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4065 .pred.safe_across_calls p1 [, p2 [,...]]
4066 */
4067static void
4068dot_pred_rel (type)
4069 int type;
4070{
4071 valueT mask = 0;
4072 int count = 0;
4073 int p1 = -1, p2 = -1;
4074
4075 if (type == 0)
4076 {
4077 if (*input_line_pointer != '"')
4078 {
4079 as_bad (_("Missing predicate relation type"));
4080 ignore_rest_of_line ();
4081 return;
4082 }
4083 else
4084 {
4085 int len;
4086 char *form = demand_copy_C_string (&len);
4087 if (strcmp (form, "mutex") == 0)
4088 type = 'm';
4089 else if (strcmp (form, "clear") == 0)
4090 type = 'c';
4091 else if (strcmp (form, "imply") == 0)
4092 type = 'i';
4093 else
4094 {
4095 as_bad (_("Unrecognized predicate relation type"));
4096 ignore_rest_of_line ();
4097 return;
4098 }
4099 }
4100 if (*input_line_pointer == ',')
4101 ++input_line_pointer;
4102 SKIP_WHITESPACE ();
4103 }
4104
4105 SKIP_WHITESPACE ();
4106 while (1)
4107 {
4108 valueT bit = 1;
4109 int regno;
4110
4111 if (toupper (*input_line_pointer) != 'P'
4112 || (regno = atoi (++input_line_pointer)) < 0
4113 || regno > 63)
4114 {
4115 as_bad (_("Predicate register expected"));
4116 ignore_rest_of_line ();
4117 return;
4118 }
4119 while (isdigit (*input_line_pointer))
4120 ++input_line_pointer;
4121 if (p1 == -1)
4122 p1 = regno;
4123 else if (p2 == -1)
4124 p2 = regno;
4125 bit <<= regno;
4126 if (mask & bit)
4127 as_warn (_("Duplicate predicate register ignored"));
4128 mask |= bit; count++;
4129 /* see if it's a range */
4130 if (*input_line_pointer == '-')
4131 {
4132 valueT stop = 1;
4133 ++input_line_pointer;
4134
4135 if (toupper (*input_line_pointer) != 'P'
4136 || (regno = atoi (++input_line_pointer)) < 0
4137 || regno > 63)
4138 {
4139 as_bad (_("Predicate register expected"));
4140 ignore_rest_of_line ();
4141 return;
4142 }
4143 while (isdigit (*input_line_pointer))
4144 ++input_line_pointer;
4145 stop <<= regno;
4146 if (bit >= stop)
4147 {
4148 as_bad (_("Bad register range"));
4149 ignore_rest_of_line ();
4150 return;
4151 }
4152 while (bit < stop)
4153 {
4154 bit <<= 1;
4155 mask |= bit; count++;
4156 }
4157 SKIP_WHITESPACE ();
4158 }
4159 if (*input_line_pointer != ',')
4160 break;
4161 ++input_line_pointer;
4162 SKIP_WHITESPACE ();
4163 }
4164
4165 switch (type)
4166 {
4167 case 'c':
4168 if (count == 0)
4169 mask = ~(valueT)0;
4170 clear_qp_mutex (mask);
4171 clear_qp_implies (mask, (valueT)0);
4172 break;
4173 case 'i':
4174 if (count != 2 || p1 == -1 || p2 == -1)
4175 as_bad (_("Predicate source and target required"));
4176 else if (p1 == 0 || p2 == 0)
4177 as_bad (_("Use of p0 is not valid in this context"));
4178 else
4179 add_qp_imply (p1, p2);
4180 break;
4181 case 'm':
4182 if (count < 2)
4183 {
4184 as_bad (_("At least two PR arguments expected"));
4185 break;
4186 }
4187 else if (mask & 1)
4188 {
4189 as_bad (_("Use of p0 is not valid in this context"));
4190 break;
4191 }
4192 add_qp_mutex (mask);
4193 break;
4194 case 's':
4195 /* note that we don't override any existing relations */
4196 if (count == 0)
4197 {
4198 as_bad (_("At least one PR argument expected"));
4199 break;
4200 }
4201 if (md.debug_dv)
4202 {
4203 fprintf (stderr, "Safe across calls: ");
4204 print_prmask (mask);
4205 fprintf (stderr, "\n");
4206 }
4207 qp_safe_across_calls = mask;
4208 break;
4209 }
4210 demand_empty_rest_of_line ();
4211}
4212
4213/* .entry label [, label [, ...]]
4214 Hint to DV code that the given labels are to be considered entry points.
4215 Otherwise, only global labels are considered entry points.
4216 */
4217static void
4218dot_entry (dummy)
4219 int dummy;
4220{
4221 const char *err;
4222 char *name;
4223 int c;
4224 symbolS *symbolP;
4225
4226 do
4227 {
4228 name = input_line_pointer;
4229 c = get_symbol_end ();
4230 symbolP = symbol_find_or_make (name);
4231
4232 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4233 if (err)
4234 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4235 name, err);
4236
4237 *input_line_pointer = c;
4238 SKIP_WHITESPACE ();
4239 c = *input_line_pointer;
4240 if (c == ',')
4241 {
4242 input_line_pointer++;
4243 SKIP_WHITESPACE ();
4244 if (*input_line_pointer == '\n')
4245 c = '\n';
4246 }
4247 }
4248 while (c == ',');
4249
4250 demand_empty_rest_of_line ();
4251}
4252
4253/* .mem.offset offset, base
4254 "base" is used to distinguish between offsets from a different base.
4255 */
4256static void
4257dot_mem_offset (dummy)
4258 int dummy;
4259{
4260 md.mem_offset.hint = 1;
4261 md.mem_offset.offset = get_absolute_expression ();
4262 if (*input_line_pointer != ',')
4263 {
4264 as_bad (_("Comma expected"));
4265 ignore_rest_of_line ();
4266 return;
4267 }
4268 ++input_line_pointer;
4269 md.mem_offset.base = get_absolute_expression ();
4270 demand_empty_rest_of_line ();
4271}
4272
4273/* ia64-specific pseudo-ops: */
4274const pseudo_typeS md_pseudo_table[] =
4275 {
4276 { "radix", dot_radix, 0 },
4277 { "lcomm", s_lcomm_bytes, 1 },
4278 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4279 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4280 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4281 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4282 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4283 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4284 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4285 { "proc", dot_proc, 0 },
4286 { "body", dot_body, 0 },
4287 { "prologue", dot_prologue, 0 },
4288 { "endp", dot_endp },
4289 { "file", dwarf2_directive_file },
4290 { "loc", dwarf2_directive_loc },
4291
4292 { "fframe", dot_fframe },
4293 { "vframe", dot_vframe },
e0c9811a
JW		 4294 { "vframesp", dot_vframesp },
4295 { "vframepsp", dot_vframepsp },
800eeca4
JW		 4296 { "save", dot_save },
4297 { "restore", dot_restore },
e0c9811a
JW		 4298 { "restorereg", dot_restorereg },
4299 { "restorereg.p", dot_restorereg_p },
800eeca4
JW		 4300 { "handlerdata", dot_handlerdata },
4301 { "unwentry", dot_unwentry },
e0c9811a
JW		 4302 { "altrp", dot_altrp },
4303 { "savesp", dot_savemem, 0 },
4304 { "savepsp", dot_savemem, 1 },
800eeca4
JW		 4305 { "save.g", dot_saveg },
4306 { "save.f", dot_savef },
4307 { "save.b", dot_saveb },
4308 { "save.gf", dot_savegf },
4309 { "spill", dot_spill },
e0c9811a
JW		 4310 { "spillreg", dot_spillreg },
4311 { "spillsp", dot_spillmem, 0 },
4312 { "spillpsp", dot_spillmem, 1 },
4313 { "spillreg.p", dot_spillreg_p },
4314 { "spillsp.p", dot_spillmem_p, 0 },
4315 { "spillpsp.p", dot_spillmem_p, 1 },
4316 { "label_state", dot_label_state },
4317 { "copy_state", dot_copy_state },
800eeca4
JW		 4318 { "unwabi", dot_unwabi },
4319 { "personality", dot_personality },
4320#if 0
4321 { "estate", dot_estate },
4322#endif
4323 { "mii", dot_template, 0x0 },
4324 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4325 { "mlx", dot_template, 0x2 },
4326 { "mmi", dot_template, 0x4 },
4327 { "mfi", dot_template, 0x6 },
4328 { "mmf", dot_template, 0x7 },
4329 { "mib", dot_template, 0x8 },
4330 { "mbb", dot_template, 0x9 },
4331 { "bbb", dot_template, 0xb },
4332 { "mmb", dot_template, 0xc },
4333 { "mfb", dot_template, 0xe },
4334#if 0
4335 { "lb", dot_scope, 0 },
4336 { "le", dot_scope, 1 },
4337#endif
4338 { "align", s_align_bytes, 0 },
4339 { "regstk", dot_regstk, 0 },
4340 { "rotr", dot_rot, DYNREG_GR },
4341 { "rotf", dot_rot, DYNREG_FR },
4342 { "rotp", dot_rot, DYNREG_PR },
4343 { "lsb", dot_byteorder, 0 },
4344 { "msb", dot_byteorder, 1 },
4345 { "psr", dot_psr, 0 },
4346 { "alias", dot_alias, 0 },
4347 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4348
4349 { "xdata1", dot_xdata, 1 },
4350 { "xdata2", dot_xdata, 2 },
4351 { "xdata4", dot_xdata, 4 },
4352 { "xdata8", dot_xdata, 8 },
4353 { "xreal4", dot_xfloat_cons, 'f' },
4354 { "xreal8", dot_xfloat_cons, 'd' },
4355 { "xreal10", dot_xfloat_cons, 'x' },
4356 { "xstring", dot_xstringer, 0 },
4357 { "xstringz", dot_xstringer, 1 },
4358
4359 /* unaligned versions: */
4360 { "xdata2.ua", dot_xdata_ua, 2 },
4361 { "xdata4.ua", dot_xdata_ua, 4 },
4362 { "xdata8.ua", dot_xdata_ua, 8 },
4363 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4364 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4365 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4366
4367 /* annotations/DV checking support */
4368 { "entry", dot_entry, 0 },
4369 { "mem.offset", dot_mem_offset },
4370 { "pred.rel", dot_pred_rel, 0 },
4371 { "pred.rel.clear", dot_pred_rel, 'c' },
4372 { "pred.rel.imply", dot_pred_rel, 'i' },
4373 { "pred.rel.mutex", dot_pred_rel, 'm' },
4374 { "pred.safe_across_calls", dot_pred_rel, 's' },
4375 { "reg.val", dot_reg_val },
4376 { "auto", dot_dv_mode, 'a' },
4377 { "explicit", dot_dv_mode, 'e' },
4378 { "default", dot_dv_mode, 'd' },
4379
4380 { NULL, 0, 0 }
4381 };
4382
4383static const struct pseudo_opcode
4384 {
4385 const char *name;
4386 void (*handler) (int);
4387 int arg;
4388 }
4389pseudo_opcode[] =
4390 {
4391 /* these are more like pseudo-ops, but don't start with a dot */
4392 { "data1", cons, 1 },
4393 { "data2", cons, 2 },
4394 { "data4", cons, 4 },
4395 { "data8", cons, 8 },
4396 { "real4", stmt_float_cons, 'f' },
4397 { "real8", stmt_float_cons, 'd' },
4398 { "real10", stmt_float_cons, 'x' },
4399 { "string", stringer, 0 },
4400 { "stringz", stringer, 1 },
4401
4402 /* unaligned versions: */
4403 { "data2.ua", stmt_cons_ua, 2 },
4404 { "data4.ua", stmt_cons_ua, 4 },
4405 { "data8.ua", stmt_cons_ua, 8 },
4406 { "real4.ua", float_cons, 'f' },
4407 { "real8.ua", float_cons, 'd' },
4408 { "real10.ua", float_cons, 'x' },
4409 };
4410
4411/* Declare a register by creating a symbol for it and entering it in
4412 the symbol table. */
4413static symbolS*
4414declare_register (name, regnum)
4415 const char *name;
4416 int regnum;
4417{
4418 const char *err;
4419 symbolS *sym;
4420
4421 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4422
4423 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4424 if (err)
4425 as_fatal ("Inserting \"%s\" into register table failed: %s",
4426 name, err);
4427
4428 return sym;
4429}
4430
4431static void
4432declare_register_set (prefix, num_regs, base_regnum)
4433 const char *prefix;
4434 int num_regs;
4435 int base_regnum;
4436{
4437 char name[8];
4438 int i;
4439
4440 for (i = 0; i < num_regs; ++i)
4441 {
4442 sprintf (name, "%s%u", prefix, i);
4443 declare_register (name, base_regnum + i);
4444 }
4445}
4446
4447static unsigned int
4448operand_width (opnd)
4449 enum ia64_opnd opnd;
4450{
4451 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4452 unsigned int bits = 0;
4453 int i;
4454
4455 bits = 0;
4456 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4457 bits += odesc->field[i].bits;
4458
4459 return bits;
4460}
4461
4462static int
4463operand_match (idesc, index, e)
4464 const struct ia64_opcode *idesc;
4465 int index;
4466 expressionS *e;
4467{
4468 enum ia64_opnd opnd = idesc->operands[index];
4469 int bits, relocatable = 0;
4470 struct insn_fix *fix;
4471 bfd_signed_vma val;
4472
4473 switch (opnd)
4474 {
4475 /* constants: */
4476
4477 case IA64_OPND_AR_CCV:
4478 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4479 return 1;
4480 break;
4481
4482 case IA64_OPND_AR_PFS:
4483 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4484 return 1;
4485 break;
4486
4487 case IA64_OPND_GR0:
4488 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4489 return 1;
4490 break;
4491
4492 case IA64_OPND_IP:
4493 if (e->X_op == O_register && e->X_add_number == REG_IP)
4494 return 1;
4495 break;
4496
4497 case IA64_OPND_PR:
4498 if (e->X_op == O_register && e->X_add_number == REG_PR)
4499 return 1;
4500 break;
4501
4502 case IA64_OPND_PR_ROT:
4503 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4504 return 1;
4505 break;
4506
4507 case IA64_OPND_PSR:
4508 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4509 return 1;
4510 break;
4511
4512 case IA64_OPND_PSR_L:
4513 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4514 return 1;
4515 break;
4516
4517 case IA64_OPND_PSR_UM:
4518 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4519 return 1;
4520 break;
4521
4522 case IA64_OPND_C1:
4523 if (e->X_op == O_constant && e->X_add_number == 1)
4524 return 1;
4525 break;
4526
4527 case IA64_OPND_C8:
4528 if (e->X_op == O_constant && e->X_add_number == 8)
4529 return 1;
4530 break;
4531
4532 case IA64_OPND_C16:
4533 if (e->X_op == O_constant && e->X_add_number == 16)
4534 return 1;
4535 break;
4536
4537 /* register operands: */
4538
4539 case IA64_OPND_AR3:
4540 if (e->X_op == O_register && e->X_add_number >= REG_AR
4541 && e->X_add_number < REG_AR + 128)
4542 return 1;
4543 break;
4544
4545 case IA64_OPND_B1:
4546 case IA64_OPND_B2:
4547 if (e->X_op == O_register && e->X_add_number >= REG_BR
4548 && e->X_add_number < REG_BR + 8)
4549 return 1;
4550 break;
4551
4552 case IA64_OPND_CR3:
4553 if (e->X_op == O_register && e->X_add_number >= REG_CR
4554 && e->X_add_number < REG_CR + 128)
4555 return 1;
4556 break;
4557
4558 case IA64_OPND_F1:
4559 case IA64_OPND_F2:
4560 case IA64_OPND_F3:
4561 case IA64_OPND_F4:
4562 if (e->X_op == O_register && e->X_add_number >= REG_FR
4563 && e->X_add_number < REG_FR + 128)
4564 return 1;
4565 break;
4566
4567 case IA64_OPND_P1:
4568 case IA64_OPND_P2:
4569 if (e->X_op == O_register && e->X_add_number >= REG_P
4570 && e->X_add_number < REG_P + 64)
4571 return 1;
4572 break;
4573
4574 case IA64_OPND_R1:
4575 case IA64_OPND_R2:
4576 case IA64_OPND_R3:
4577 if (e->X_op == O_register && e->X_add_number >= REG_GR
4578 && e->X_add_number < REG_GR + 128)
4579 return 1;
4580 break;
4581
4582 case IA64_OPND_R3_2:
4583 if (e->X_op == O_register && e->X_add_number >= REG_GR
4584 && e->X_add_number < REG_GR + 4)
4585 return 1;
4586 break;
4587
4588 /* indirect operands: */
4589 case IA64_OPND_CPUID_R3:
4590 case IA64_OPND_DBR_R3:
4591 case IA64_OPND_DTR_R3:
4592 case IA64_OPND_ITR_R3:
4593 case IA64_OPND_IBR_R3:
4594 case IA64_OPND_MSR_R3:
4595 case IA64_OPND_PKR_R3:
4596 case IA64_OPND_PMC_R3:
4597 case IA64_OPND_PMD_R3:
4598 case IA64_OPND_RR_R3:
4599 if (e->X_op == O_index && e->X_op_symbol
4600 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4601 == opnd - IA64_OPND_CPUID_R3))
4602 return 1;
4603 break;
4604
4605 case IA64_OPND_MR3:
4606 if (e->X_op == O_index && !e->X_op_symbol)
4607 return 1;
4608 break;
4609
4610 /* immediate operands: */
4611 case IA64_OPND_CNT2a:
4612 case IA64_OPND_LEN4:
4613 case IA64_OPND_LEN6:
4614 bits = operand_width (idesc->operands[index]);
4615 if (e->X_op == O_constant
4616 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4617 return 1;
4618 break;
4619
4620 case IA64_OPND_CNT2b:
4621 if (e->X_op == O_constant
4622 && (bfd_vma) (e->X_add_number - 1) < 3)
4623 return 1;
4624 break;
4625
4626 case IA64_OPND_CNT2c:
4627 val = e->X_add_number;
4628 if (e->X_op == O_constant
4629 && (val == 0 || val == 7 || val == 15 || val == 16))
4630 return 1;
4631 break;
4632
4633 case IA64_OPND_SOR:
4634 /* SOR must be an integer multiple of 8 */
4635 if (e->X_add_number & 0x7)
4636 break;
4637 case IA64_OPND_SOF:
4638 case IA64_OPND_SOL:
4639 if (e->X_op == O_constant &&
4640 (bfd_vma) e->X_add_number <= 96)
4641 return 1;
4642 break;
4643
4644 case IA64_OPND_IMMU62:
4645 if (e->X_op == O_constant)
4646 {
4647 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
4648 return 1;
4649 }
4650 else
4651 {
4652 /* FIXME -- need 62-bit relocation type */
4653 as_bad (_("62-bit relocation not yet implemented"));
4654 }
4655 break;
4656
4657 case IA64_OPND_IMMU64:
4658 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4659 || e->X_op == O_subtract)
4660 {
4661 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4662 fix->code = BFD_RELOC_IA64_IMM64;
4663 if (e->X_op != O_subtract)
4664 {
4665 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4666 if (e->X_op == O_pseudo_fixup)
4667 e->X_op = O_symbol;
4668 }
4669
4670 fix->opnd = idesc->operands[index];
4671 fix->expr = *e;
4672 fix->is_pcrel = 0;
4673 ++CURR_SLOT.num_fixups;
4674 return 1;
4675 }
4676 else if (e->X_op == O_constant)
4677 return 1;
4678 break;
4679
4680 case IA64_OPND_CCNT5:
4681 case IA64_OPND_CNT5:
4682 case IA64_OPND_CNT6:
4683 case IA64_OPND_CPOS6a:
4684 case IA64_OPND_CPOS6b:
4685 case IA64_OPND_CPOS6c:
4686 case IA64_OPND_IMMU2:
4687 case IA64_OPND_IMMU7a:
4688 case IA64_OPND_IMMU7b:
800eeca4
JW		 4689 case IA64_OPND_IMMU21:
4690 case IA64_OPND_IMMU24:
4691 case IA64_OPND_MBTYPE4:
4692 case IA64_OPND_MHTYPE8:
4693 case IA64_OPND_POS6:
4694 bits = operand_width (idesc->operands[index]);
4695 if (e->X_op == O_constant
4696 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4697 return 1;
4698 break;
4699
bf3ca999
TW		 4700 case IA64_OPND_IMMU9:
4701 bits = operand_width (idesc->operands[index]);
4702 if (e->X_op == O_constant
4703 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4704 {
4705 int lobits = e->X_add_number & 0x3;
4706 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
4707 e->X_add_number |= (bfd_vma)0x3;
4708 return 1;
4709 }
4710 break;
4711
800eeca4
JW		 4712 case IA64_OPND_IMM44:
4713 /* least 16 bits must be zero */
4714 if ((e->X_add_number & 0xffff) != 0)
4715 as_warn (_("lower 16 bits of mask ignored"));
4716
4717 if (e->X_op == O_constant
4718 && ((e->X_add_number >= 0
4719 && e->X_add_number < ((bfd_vma) 1 << 44))
4720 || (e->X_add_number < 0
4721 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
4722 {
4723 /* sign-extend */
4724 if (e->X_add_number >= 0
4725 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4726 {
4727 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4728 }
4729 return 1;
4730 }
4731 break;
4732
4733 case IA64_OPND_IMM17:
4734 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4735 if (e->X_op == O_constant
4736 && ((e->X_add_number >= 0
4737 && e->X_add_number < ((bfd_vma) 1 << 17))
4738 || (e->X_add_number < 0
4739 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
4740 {
4741 /* sign-extend */
4742 if (e->X_add_number >= 0
4743 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4744 {
4745 e->X_add_number |= ~(((bfd_vma)1 << 17) - 1);
4746 }
4747 return 1;
4748 }
4749 break;
4750
4751 case IA64_OPND_IMM14:
4752 case IA64_OPND_IMM22:
4753 relocatable = 1;
4754 case IA64_OPND_IMM1:
4755 case IA64_OPND_IMM8:
4756 case IA64_OPND_IMM8U4:
4757 case IA64_OPND_IMM8M1:
4758 case IA64_OPND_IMM8M1U4:
4759 case IA64_OPND_IMM8M1U8:
4760 case IA64_OPND_IMM9a:
4761 case IA64_OPND_IMM9b:
4762 bits = operand_width (idesc->operands[index]);
4763 if (relocatable && (e->X_op == O_symbol
4764 || e->X_op == O_subtract
4765 || e->X_op == O_pseudo_fixup))
4766 {
4767 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4768
4769 if (idesc->operands[index] == IA64_OPND_IMM14)
4770 fix->code = BFD_RELOC_IA64_IMM14;
4771 else
4772 fix->code = BFD_RELOC_IA64_IMM22;
4773
4774 if (e->X_op != O_subtract)
4775 {
4776 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4777 if (e->X_op == O_pseudo_fixup)
4778 e->X_op = O_symbol;
4779 }
4780
4781 fix->opnd = idesc->operands[index];
4782 fix->expr = *e;
4783 fix->is_pcrel = 0;
4784 ++CURR_SLOT.num_fixups;
4785 return 1;
4786 }
4787 else if (e->X_op != O_constant
4788 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4789 return 0;
4790
4791 if (opnd == IA64_OPND_IMM8M1U4)
4792 {
4793 /* Zero is not valid for unsigned compares that take an adjusted
4794 constant immediate range. */
4795 if (e->X_add_number == 0)
4796 return 0;
4797
4798 /* Sign-extend 32-bit unsigned numbers, so that the following range
4799 checks will work. */
4800 val = e->X_add_number;
4801 if (((val & (~(bfd_vma)0 << 32)) == 0)
4802 && ((val & ((bfd_vma)1 << 31)) != 0))
4803 val = ((val << 32) >> 32);
4804
4805 /* Check for 0x100000000. This is valid because
4806 0x100000000-1 is the same as ((uint32_t) -1). */
4807 if (val == ((bfd_signed_vma) 1 << 32))
4808 return 1;
4809
4810 val = val - 1;
4811 }
4812 else if (opnd == IA64_OPND_IMM8M1U8)
4813 {
4814 /* Zero is not valid for unsigned compares that take an adjusted
4815 constant immediate range. */
4816 if (e->X_add_number == 0)
4817 return 0;
4818
4819 /* Check for 0x10000000000000000. */
4820 if (e->X_op == O_big)
4821 {
4822 if (generic_bignum[0] == 0
4823 && generic_bignum[1] == 0
4824 && generic_bignum[2] == 0
4825 && generic_bignum[3] == 0
4826 && generic_bignum[4] == 1)
4827 return 1;
4828 else
4829 return 0;
4830 }
4831 else
4832 val = e->X_add_number - 1;
4833 }
4834 else if (opnd == IA64_OPND_IMM8M1)
4835 val = e->X_add_number - 1;
4836 else if (opnd == IA64_OPND_IMM8U4)
4837 {
4838 /* Sign-extend 32-bit unsigned numbers, so that the following range
4839 checks will work. */
4840 val = e->X_add_number;
4841 if (((val & (~(bfd_vma)0 << 32)) == 0)
4842 && ((val & ((bfd_vma)1 << 31)) != 0))
4843 val = ((val << 32) >> 32);
4844 }
4845 else
4846 val = e->X_add_number;
4847
4848 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
4849 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
4850 return 1;
4851 break;
4852
4853 case IA64_OPND_INC3:
4854 /* +/- 1, 4, 8, 16 */
4855 val = e->X_add_number;
4856 if (val < 0)
4857 val = -val;
4858 if (e->X_op == O_constant
4859 && (val == 1 || val == 4 || val == 8 || val == 16))
4860 return 1;
4861 break;
4862
4863 case IA64_OPND_TGT25:
4864 case IA64_OPND_TGT25b:
4865 case IA64_OPND_TGT25c:
4866 case IA64_OPND_TGT64:
4867 if (e->X_op == O_symbol)
4868 {
4869 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4870 if (opnd == IA64_OPND_TGT25)
4871 fix->code = BFD_RELOC_IA64_PCREL21F;
4872 else if (opnd == IA64_OPND_TGT25b)
4873 fix->code = BFD_RELOC_IA64_PCREL21M;
4874 else if (opnd == IA64_OPND_TGT25c)
4875 fix->code = BFD_RELOC_IA64_PCREL21B;
c67e42c9
RH		 4876 else if (opnd == IA64_OPND_TGT64)
4877 fix->code = BFD_RELOC_IA64_PCREL60B;
4878 else
4879 abort ();
4880
800eeca4
JW		 4881 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4882 fix->opnd = idesc->operands[index];
4883 fix->expr = *e;
4884 fix->is_pcrel = 1;
4885 ++CURR_SLOT.num_fixups;
4886 return 1;
4887 }
4888 case IA64_OPND_TAG13:
4889 case IA64_OPND_TAG13b:
4890 switch (e->X_op)
4891 {
4892 case O_constant:
4893 return 1;
4894
4895 case O_symbol:
4896 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4897 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4898 fix->opnd = idesc->operands[index];
4899 fix->expr = *e;
4900 fix->is_pcrel = 1;
4901 ++CURR_SLOT.num_fixups;
4902 return 1;
4903
4904 default:
4905 break;
4906 }
4907 break;
4908
4909 default:
4910 break;
4911 }
4912 return 0;
4913}
4914
4915static int
4916parse_operand (e)
4917 expressionS *e;
4918{
4919 int sep = '\0';
4920
4921 memset (e, 0, sizeof (*e));
4922 e->X_op = O_absent;
4923 SKIP_WHITESPACE ();
4924 if (*input_line_pointer != '}')
4925 expression (e);
4926 sep = *input_line_pointer++;
4927
4928 if (sep == '}')
4929 {
4930 if (!md.manual_bundling)
4931 as_warn ("Found '}' when manual bundling is off");
4932 else
4933 CURR_SLOT.manual_bundling_off = 1;
4934 md.manual_bundling = 0;
4935 sep = '\0';
4936 }
4937 return sep;
4938}
4939
4940/* Returns the next entry in the opcode table that matches the one in
4941 IDESC, and frees the entry in IDESC. If no matching entry is
4942 found, NULL is returned instead. */
4943
4944static struct ia64_opcode *
4945get_next_opcode (struct ia64_opcode *idesc)
4946{
4947 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
4948 ia64_free_opcode (idesc);
4949 return next;
4950}
4951
4952/* Parse the operands for the opcode and find the opcode variant that
4953 matches the specified operands, or NULL if no match is possible. */
4954static struct ia64_opcode*
4955parse_operands (idesc)
4956 struct ia64_opcode *idesc;
4957{
4958 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
4959 int sep = 0;
4960 enum ia64_opnd expected_operand = IA64_OPND_NIL;
4961 char mnemonic[129];
4962 char *first_arg = 0, *end, *saved_input_pointer;
4963 unsigned int sof;
4964
4965 assert (strlen (idesc->name) <= 128);
4966
4967 strcpy (mnemonic, idesc->name);
4968 if (idesc->operands[2] == IA64_OPND_SOF)
4969 {
4970 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4971 can't parse the first operand until we have parsed the
4972 remaining operands of the "alloc" instruction. */
4973 SKIP_WHITESPACE ();
4974 first_arg = input_line_pointer;
4975 end = strchr (input_line_pointer, '=');
4976 if (!end)
4977 {
4978 as_bad ("Expected separator `='");
4979 return 0;
4980 }
4981 input_line_pointer = end + 1;
4982 ++i;
4983 ++num_outputs;
4984 }
4985
4986 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
4987 {
4988 sep = parse_operand (CURR_SLOT.opnd + i);
4989 if (CURR_SLOT.opnd[i].X_op == O_absent)
4990 break;
4991
4992 ++num_operands;
4993
4994 if (sep != '=' && sep != ',')
4995 break;
4996
4997 if (sep == '=')
4998 {
4999 if (num_outputs > 0)
5000 as_bad ("Duplicate equal sign (=) in instruction");
5001 else
5002 num_outputs = i + 1;
5003 }
5004 }
5005 if (sep != '\0')
5006 {
5007 as_bad ("Illegal operand separator `%c'", sep);
5008 return 0;
5009 }
5010
5011 if (idesc->operands[2] == IA64_OPND_SOF)
5012 {
5013 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5014 know (strcmp (idesc->name, "alloc") == 0);
5015 if (num_operands == 5 /* first_arg not included in this count! */
5016 && CURR_SLOT.opnd[2].X_op == O_constant
5017 && CURR_SLOT.opnd[3].X_op == O_constant
5018 && CURR_SLOT.opnd[4].X_op == O_constant
5019 && CURR_SLOT.opnd[5].X_op == O_constant)
5020 {
5021 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5022 CURR_SLOT.opnd[3].X_add_number,
5023 CURR_SLOT.opnd[4].X_add_number,
5024 CURR_SLOT.opnd[5].X_add_number);
5025
5026 /* now we can parse the first arg: */
5027 saved_input_pointer = input_line_pointer;
5028 input_line_pointer = first_arg;
5029 sep = parse_operand (CURR_SLOT.opnd + 0);
5030 if (sep != '=')
5031 --num_outputs; /* force error */
5032 input_line_pointer = saved_input_pointer;
5033
5034 CURR_SLOT.opnd[2].X_add_number = sof;
5035 CURR_SLOT.opnd[3].X_add_number
5036 = sof - CURR_SLOT.opnd[4].X_add_number;
5037 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5038 }
5039 }
5040
5041 highest_unmatched_operand = 0;
5042 expected_operand = idesc->operands[0];
5043 for (; idesc; idesc = get_next_opcode (idesc))
5044 {
5045 if (num_outputs != idesc->num_outputs)
5046 continue; /* mismatch in # of outputs */
5047
5048 CURR_SLOT.num_fixups = 0;
5049 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5050 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
5051 break;
5052
5053 if (i != num_operands)
5054 {
5055 if (i > highest_unmatched_operand)
5056 {
5057 highest_unmatched_operand = i;
5058 expected_operand = idesc->operands[i];
5059 }
5060 continue;
5061 }
5062
5063 if (num_operands < NELEMS (idesc->operands)
5064 && idesc->operands[num_operands])
5065 continue; /* mismatch in number of arguments */
5066
5067 break;
5068 }
5069 if (!idesc)
5070 {
5071 if (expected_operand)
5072 as_bad ("Operand %u of `%s' should be %s",
5073 highest_unmatched_operand + 1, mnemonic,
5074 elf64_ia64_operands[expected_operand].desc);
5075 else
5076 as_bad ("Operand mismatch");
5077 return 0;
5078 }
5079 return idesc;
5080}
5081
5082static void
5083build_insn (slot, insnp)
5084 struct slot *slot;
5085 bfd_vma *insnp;
5086{
5087 const struct ia64_operand *odesc, *o2desc;
5088 struct ia64_opcode *idesc = slot->idesc;
5089 bfd_signed_vma insn, val;
5090 const char *err;
5091 int i;
5092
5093 insn = idesc->opcode | slot->qp_regno;
5094
5095 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5096 {
c67e42c9
RH		 5097 if (slot->opnd[i].X_op == O_register
5098 || slot->opnd[i].X_op == O_constant
5099 || slot->opnd[i].X_op == O_index)
5100 val = slot->opnd[i].X_add_number;
5101 else if (slot->opnd[i].X_op == O_big)
800eeca4 5102 {
c67e42c9
RH		 5103 /* This must be the value 0x10000000000000000. */
5104 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5105 val = 0;
5106 }
5107 else
5108 val = 0;
5109
5110 switch (idesc->operands[i])
5111 {
5112 case IA64_OPND_IMMU64:
800eeca4
JW		 5113 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5114 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5115 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5116 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH		 5117 continue;
5118
5119 case IA64_OPND_IMMU62:
5120 val &= 0x3fffffffffffffffULL;
800eeca4
JW		 5121 if (val != slot->opnd[i].X_add_number)
5122 as_warn (_("Value truncated to 62 bits"));
5123 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5124 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 5125 continue;
800eeca4 5126
c67e42c9
RH		 5127 case IA64_OPND_TGT64:
5128 val >>= 4;
5129 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5130 insn |= ((((val >> 59) & 0x1) << 36)
5131 | (((val >> 0) & 0xfffff) << 13));
5132 continue;
800eeca4 5133
c67e42c9
RH		 5134 case IA64_OPND_AR3:
5135 val -= REG_AR;
5136 break;
5137
5138 case IA64_OPND_B1:
5139 case IA64_OPND_B2:
5140 val -= REG_BR;
5141 break;
5142
5143 case IA64_OPND_CR3:
5144 val -= REG_CR;
5145 break;
5146
5147 case IA64_OPND_F1:
5148 case IA64_OPND_F2:
5149 case IA64_OPND_F3:
5150 case IA64_OPND_F4:
5151 val -= REG_FR;
5152 break;
5153
5154 case IA64_OPND_P1:
5155 case IA64_OPND_P2:
5156 val -= REG_P;
5157 break;
5158
5159 case IA64_OPND_R1:
5160 case IA64_OPND_R2:
5161 case IA64_OPND_R3:
5162 case IA64_OPND_R3_2:
5163 case IA64_OPND_CPUID_R3:
5164 case IA64_OPND_DBR_R3:
5165 case IA64_OPND_DTR_R3:
5166 case IA64_OPND_ITR_R3:
5167 case IA64_OPND_IBR_R3:
5168 case IA64_OPND_MR3:
5169 case IA64_OPND_MSR_R3:
5170 case IA64_OPND_PKR_R3:
5171 case IA64_OPND_PMC_R3:
5172 case IA64_OPND_PMD_R3:
5173 case IA64_OPND_RR_R3:
5174 val -= REG_GR;
5175 break;
5176
5177 default:
5178 break;
5179 }
5180
5181 odesc = elf64_ia64_operands + idesc->operands[i];
5182 err = (*odesc->insert) (odesc, val, &insn);
5183 if (err)
5184 as_bad_where (slot->src_file, slot->src_line,
5185 "Bad operand value: %s", err);
5186 if (idesc->flags & IA64_OPCODE_PSEUDO)
5187 {
5188 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5189 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5190 {
5191 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5192 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5193 }
c67e42c9
RH		 5194 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5195 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5196 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5197 {
c67e42c9
RH		 5198 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5199 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW		 5200 }
5201 }
5202 }
5203 *insnp = insn;
5204}
5205
5206static void
5207emit_one_bundle ()
5208{
5209 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5210 unsigned int manual_bundling = 0;
5211 enum ia64_unit required_unit, insn_unit = 0;
5212 enum ia64_insn_type type[3], insn_type;
5213 unsigned int template, orig_template;
5214 bfd_vma insn[3] = {-1, -1, -1};
5215 struct ia64_opcode *idesc;
5216 int end_of_insn_group = 0, user_template = -1;
5217 int n, i, j, first, curr;
e0c9811a 5218 unw_rec_list *ptr, *prev;
800eeca4
JW		 5219 bfd_vma t0 = 0, t1 = 0;
5220 struct label_fix *lfix;
5221 struct insn_fix *ifix;
5222 char mnemonic[16];
5223 fixS *fix;
5224 char *f;
5225
5226 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5227 know (first >= 0 & first < NUM_SLOTS);
5228 n = MIN (3, md.num_slots_in_use);
5229
5230 /* Determine template: user user_template if specified, best match
5231 otherwise: */
5232
5233 if (md.slot[first].user_template >= 0)
5234 user_template = template = md.slot[first].user_template;
5235 else
5236 {
5237 /* auto select appropriate template */
5238 memset (type, 0, sizeof (type));
5239 curr = first;
5240 for (i = 0; i < n; ++i)
5241 {
5242 type[i] = md.slot[curr].idesc->type;
5243 curr = (curr + 1) % NUM_SLOTS;
5244 }
5245 template = best_template[type[0]][type[1]][type[2]];
5246 }
5247
5248 /* initialize instructions with appropriate nops: */
5249 for (i = 0; i < 3; ++i)
5250 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5251
5252 f = frag_more (16);
5253
5254 /* now fill in slots with as many insns as possible: */
5255 curr = first;
5256 idesc = md.slot[curr].idesc;
5257 end_of_insn_group = 0;
5258 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5259 {
e0c9811a
JW		 5260 /* Set the slot number for prologue/body records now as those
5261 refer to the current point, not the point after the
5262 instruction has been issued: */
10850f29
JW		 5263 /* Don't try to delete prologue/body records here, as that will cause
5264 them to also be deleted from the master list of unwind records. */
e0c9811a 5265 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
10850f29
JW		 5266 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5267 || ptr->r.type == body)
5268 ptr->slot_number = (unsigned long) f + i;
e0c9811a 5269
800eeca4
JW		 5270 if (idesc->flags & IA64_OPCODE_SLOT2)
5271 {
5272 if (manual_bundling && i != 2)
5273 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5274 "`%s' must be last in bundle", idesc->name);
5275 else
5276 i = 2;
5277 }
5278 if (idesc->flags & IA64_OPCODE_LAST)
5279 {
5280 int required_slot, required_template;
5281
5282 /* If we need a stop bit after an M slot, our only choice is
5283 template 5 (M;;MI). If we need a stop bit after a B
5284 slot, our only choice is to place it at the end of the
5285 bundle, because the only available templates are MIB,
5286 MBB, BBB, MMB, and MFB. We don't handle anything other
5287 than M and B slots because these are the only kind of
5288 instructions that can have the IA64_OPCODE_LAST bit set. */
5289 required_template = template;
5290 switch (idesc->type)
5291 {
5292 case IA64_TYPE_M:
5293 required_slot = 0;
5294 required_template = 5;
5295 break;
5296
5297 case IA64_TYPE_B:
5298 required_slot = 2;
5299 break;
5300
5301 default:
5302 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5303 "Internal error: don't know how to force %s to end"
5304 "of instruction group", idesc->name);
5305 required_slot = i;
5306 break;
5307 }
5308 if (manual_bundling && i != required_slot)
5309 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5310 "`%s' must be last in instruction group",
5311 idesc->name);
5312 if (required_slot < i)
5313 /* Can't fit this instruction. */
5314 break;
5315
5316 i = required_slot;
5317 if (required_template != template)
5318 {
5319 /* If we switch the template, we need to reset the NOPs
5320 after slot i. The slot-types of the instructions ahead
5321 of i never change, so we don't need to worry about
5322 changing NOPs in front of this slot. */
5323 for (j = i; j < 3; ++j)
5324 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5325 }
5326 template = required_template;
5327 }
5328 if (curr != first && md.slot[curr].label_fixups)
5329 {
5330 if (manual_bundling_on)
5331 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5332 "Label must be first in a bundle");
5333 /* This insn must go into the first slot of a bundle. */
5334 break;
5335 }
5336
5337 manual_bundling_on = md.slot[curr].manual_bundling_on;
5338 manual_bundling_off = md.slot[curr].manual_bundling_off;
5339
5340 if (manual_bundling_on)
5341 {
5342 if (curr == first)
5343 manual_bundling = 1;
5344 else
5345 break; /* need to start a new bundle */
5346 }
5347
5348 if (end_of_insn_group && md.num_slots_in_use >= 1)
5349 {
5350 /* We need an instruction group boundary in the middle of a
5351 bundle. See if we can switch to an other template with
5352 an appropriate boundary. */
5353
5354 orig_template = template;
5355 if (i == 1 && (user_template == 4
5356 || (user_template < 0
5357 && (ia64_templ_desc[template].exec_unit[0]
5358 == IA64_UNIT_M))))
5359 {
5360 template = 5;
5361 end_of_insn_group = 0;
5362 }
5363 else if (i == 2 && (user_template == 0
5364 || (user_template < 0
5365 && (ia64_templ_desc[template].exec_unit[1]
5366 == IA64_UNIT_I)))
5367 /* This test makes sure we don't switch the template if
5368 the next instruction is one that needs to be first in
5369 an instruction group. Since all those instructions are
5370 in the M group, there is no way such an instruction can
5371 fit in this bundle even if we switch the template. The
5372 reason we have to check for this is that otherwise we
5373 may end up generating "MI;;I M.." which has the deadly
5374 effect that the second M instruction is no longer the
5375 first in the bundle! --davidm 99/12/16 */
5376 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5377 {
5378 template = 1;
5379 end_of_insn_group = 0;
5380 }
5381 else if (curr != first)
5382 /* can't fit this insn */
5383 break;
5384
5385 if (template != orig_template)
5386 /* if we switch the template, we need to reset the NOPs
5387 after slot i. The slot-types of the instructions ahead
5388 of i never change, so we don't need to worry about
5389 changing NOPs in front of this slot. */
5390 for (j = i; j < 3; ++j)
5391 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5392 }
5393 required_unit = ia64_templ_desc[template].exec_unit[i];
5394
5395 /* resolve dynamic opcodes such as "break" and "nop": */
5396 if (idesc->type == IA64_TYPE_DYN)
5397 {
5398 if ((strcmp (idesc->name, "nop") == 0)
5399 || (strcmp (idesc->name, "break") == 0))
5400 insn_unit = required_unit;
5401 else if (strcmp (idesc->name, "chk.s") == 0)
5402 {
5403 insn_unit = IA64_UNIT_M;
5404 if (required_unit == IA64_UNIT_I)
5405 insn_unit = IA64_UNIT_I;
5406 }
5407 else
5408 as_fatal ("emit_one_bundle: unexpected dynamic op");
5409
5410 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
3d56ab85 5411 ia64_free_opcode (idesc);
800eeca4
JW		 5412 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5413#if 0
5414 know (!idesc->next); /* no resolved dynamic ops have collisions */
5415#endif
5416 }
5417 else
5418 {
5419 insn_type = idesc->type;
5420 insn_unit = IA64_UNIT_NIL;
5421 switch (insn_type)
5422 {
5423 case IA64_TYPE_A:
5424 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5425 insn_unit = required_unit;
5426 break;
5427 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
5428 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5429 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5430 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5431 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5432 default: break;
5433 }
5434 }
5435
5436 if (insn_unit != required_unit)
5437 {
5438 if (required_unit == IA64_UNIT_L
5439 && insn_unit == IA64_UNIT_I
5440 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5441 {
5442 /* we got ourselves an MLX template but the current
5443 instruction isn't an X-unit, or an I-unit instruction
5444 that can go into the X slot of an MLX template. Duh. */
5445 if (md.num_slots_in_use >= NUM_SLOTS)
5446 {
5447 as_bad_where (md.slot[curr].src_file,
5448 md.slot[curr].src_line,
5449 "`%s' can't go in X slot of "
5450 "MLX template", idesc->name);
5451 /* drop this insn so we don't livelock: */
5452 --md.num_slots_in_use;
5453 }
5454 break;
5455 }
5456 continue; /* try next slot */
5457 }
5458
5459 if (debug_type == DEBUG_DWARF2)
5460 {
5461 bfd_vma addr;
5462
5463 addr = frag_now->fr_address + frag_now_fix () - 16 + 1*i;
5464 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5465 }
5466
5467 build_insn (md.slot + curr, insn + i);
5468
10850f29
JW		 5469 /* Set slot counts for non prologue/body unwind records. */
5470 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5471 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5472 && ptr->r.type != body)
5473 ptr->slot_number = (unsigned long) f + i;
5474 md.slot[curr].unwind_record = NULL;
e0c9811a 5475 unwind.next_slot_number = (unsigned long) f + i + ((i == 2)?(0x10-2):1);
10850f29 5476
800eeca4
JW		 5477 if (required_unit == IA64_UNIT_L)
5478 {
5479 know (i == 1);
5480 /* skip one slot for long/X-unit instructions */
5481 ++i;
5482 }
5483 --md.num_slots_in_use;
5484
5485 /* now is a good time to fix up the labels for this insn: */
5486 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5487 {
5488 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5489 symbol_set_frag (lfix->sym, frag_now);
5490 }
5491
5492 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5493 {
5494 ifix = md.slot[curr].fixup + j;
5495 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
5496 &ifix->expr, ifix->is_pcrel, ifix->code);
5497 fix->tc_fix_data.opnd = ifix->opnd;
5498 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5499 fix->fx_file = md.slot[curr].src_file;
5500 fix->fx_line = md.slot[curr].src_line;
5501 }
5502
5503 end_of_insn_group = md.slot[curr].end_of_insn_group;
5504
5505 /* clear slot: */
5506 ia64_free_opcode (md.slot[curr].idesc);
5507 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5508 md.slot[curr].user_template = -1;
5509
5510 if (manual_bundling_off)
5511 {
5512 manual_bundling = 0;
5513 break;
5514 }
5515 curr = (curr + 1) % NUM_SLOTS;
5516 idesc = md.slot[curr].idesc;
5517 }
5518 if (manual_bundling)
5519 {
5520 if (md.num_slots_in_use > 0)
5521 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5522 "`%s' does not fit into %s template",
5523 idesc->name, ia64_templ_desc[template].name);
5524 else
5525 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5526 "Missing '}' at end of file");
5527 }
5528 know (md.num_slots_in_use < NUM_SLOTS);
5529
5530 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5531 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5532
5533 md_number_to_chars (f + 0, t0, 8);
5534 md_number_to_chars (f + 8, t1, 8);
5535}
5536
5537int
5538md_parse_option (c, arg)
5539 int c;
5540 char *arg;
5541{
800eeca4
JW		 5542 switch (c)
5543 {
c43c2cc5 5544 /* Switches from the Intel assembler. */
800eeca4
JW		 5545 case 'M':
5546 if (strcmp (arg, "ilp64") == 0
5547 || strcmp (arg, "lp64") == 0
5548 || strcmp (arg, "p64") == 0)
5549 {
5550 md.flags |= EF_IA_64_ABI64;
5551 }
5552 else if (strcmp (arg, "ilp32") == 0)
5553 {
5554 md.flags &= ~EF_IA_64_ABI64;
5555 }
5556 else if (strcmp (arg, "le") == 0)
5557 {
5558 md.flags &= ~EF_IA_64_BE;
5559 }
5560 else if (strcmp (arg, "be") == 0)
5561 {
5562 md.flags |= EF_IA_64_BE;
5563 }
5564 else
5565 return 0;
5566 break;
5567
5568 case 'N':
5569 if (strcmp (arg, "so") == 0)
5570 {
5571 /* Suppress signon message. */
5572 }
5573 else if (strcmp (arg, "pi") == 0)
5574 {
5575 /* Reject privileged instructions. FIXME */
5576 }
5577 else if (strcmp (arg, "us") == 0)
5578 {
5579 /* Allow union of signed and unsigned range. FIXME */
5580 }
5581 else if (strcmp (arg, "close_fcalls") == 0)
5582 {
5583 /* Do not resolve global function calls. */
5584 }
5585 else
5586 return 0;
5587 break;
5588
5589 case 'C':
5590 /* temp[="prefix"] Insert temporary labels into the object file
5591 symbol table prefixed by "prefix".
5592 Default prefix is ":temp:".
5593 */
5594 break;
5595
5596 case 'a':
5597 /* ??? Conflicts with gas' listing option. */
5598 /* indirect=<tgt> Assume unannotated indirect branches behavior
5599 according to <tgt> --
5600 exit: branch out from the current context (default)
5601 labels: all labels in context may be branch targets
5602 */
5603 break;
5604
5605 case 'x':
5606 /* -X conflicts with an ignored option, use -x instead */
5607 md.detect_dv = 1;
5608 if (!arg || strcmp (arg, "explicit") == 0)
5609 {
5610 /* set default mode to explicit */
5611 md.default_explicit_mode = 1;
5612 break;
5613 }
5614 else if (strcmp (arg, "auto") == 0)
5615 {
5616 md.default_explicit_mode = 0;
5617 }
5618 else if (strcmp (arg, "debug") == 0)
5619 {
5620 md.debug_dv = 1;
5621 }
5622 else if (strcmp (arg, "debugx") == 0)
5623 {
5624 md.default_explicit_mode = 1;
5625 md.debug_dv = 1;
5626 }
5627 else
5628 {
5629 as_bad (_("Unrecognized option '-x%s'"), arg);
5630 }
5631 break;
5632
5633 case 'S':
5634 /* nops Print nops statistics. */
5635 break;
5636
c43c2cc5
JW		 5637 /* GNU specific switches for gcc. */
5638 case OPTION_MCONSTANT_GP:
5639 md.flags |= EF_IA_64_CONS_GP;
5640 break;
5641
5642 case OPTION_MAUTO_PIC:
5643 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
5644 break;
5645
800eeca4
JW		 5646 default:
5647 return 0;
5648 }
5649
5650 return 1;
5651}
5652
5653void
5654md_show_usage (stream)
5655 FILE *stream;
5656{
5657 fputs(_("\
5658IA-64 options:\n\
5659 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5660 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5661 -x | -xexplicit turn on dependency violation checking (default)\n\
5662 -xauto automagically remove dependency violations\n\
5663 -xdebug debug dependency violation checker\n"),
5664 stream);
5665}
5666
44576e1f
RH		 5667/* Return true if TYPE fits in TEMPL at SLOT. */
5668
5669static int
800eeca4
JW		 5670match (int templ, int type, int slot)
5671{
5672 enum ia64_unit unit;
5673 int result;
5674
5675 unit = ia64_templ_desc[templ].exec_unit[slot];
5676 switch (type)
5677 {
5678 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5679 case IA64_TYPE_A:
5680 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5681 break;
5682 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5683 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5684 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5685 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5686 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5687 default: result = 0; break;
5688 }
5689 return result;
5690}
5691
44576e1f
RH		 5692/* Add a bit of extra goodness if a nop of type F or B would fit
5693 in TEMPL at SLOT. */
5694
5695static inline int
5696extra_goodness (int templ, int slot)
5697{
5698 if (match (templ, IA64_TYPE_F, slot))
5699 return 2;
5700 if (match (templ, IA64_TYPE_B, slot))
5701 return 1;
5702 return 0;
5703}
5704
800eeca4
JW		 5705/* This function is called once, at assembler startup time. It sets
5706 up all the tables, etc. that the MD part of the assembler will need
5707 that can be determined before arguments are parsed. */
5708void
5709md_begin ()
5710{
5711 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
5712 const char *err;
5713 char name[8];
5714
5715 md.auto_align = 1;
5716 md.explicit_mode = md.default_explicit_mode;
5717
5718 bfd_set_section_alignment (stdoutput, text_section, 4);
5719
5720 target_big_endian = 0;
5721 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
5722 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5723 &zero_address_frag);
5724
5725 pseudo_func[FUNC_GP_RELATIVE].u.sym =
5726 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5727 &zero_address_frag);
5728
5729 pseudo_func[FUNC_LT_RELATIVE].u.sym =
5730 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5731 &zero_address_frag);
5732
c67e42c9
RH		 5733 pseudo_func[FUNC_PC_RELATIVE].u.sym =
5734 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5735 &zero_address_frag);
5736
800eeca4
JW		 5737 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
5738 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5739 &zero_address_frag);
5740
5741 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
5742 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5743 &zero_address_frag);
5744
5745 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
5746 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5747 &zero_address_frag);
5748
5749 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
5750 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5751 &zero_address_frag);
5752
5753 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
5754 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5755 &zero_address_frag);
5756
44576e1f
RH		 5757 /* Compute the table of best templates. We compute goodness as a
5758 base 4 value, in which each match counts for 3, each F counts
5759 for 2, each B counts for 1. This should maximize the number of
5760 F and B nops in the chosen bundles, which is good because these
5761 pipelines are least likely to be overcommitted. */
800eeca4
JW		 5762 for (i = 0; i < IA64_NUM_TYPES; ++i)
5763 for (j = 0; j < IA64_NUM_TYPES; ++j)
5764 for (k = 0; k < IA64_NUM_TYPES; ++k)
5765 {
5766 best = 0;
5767 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
5768 {
5769 goodness = 0;
5770 if (match (t, i, 0))
5771 {
5772 if (match (t, j, 1))
5773 {
5774 if (match (t, k, 2))
44576e1f 5775 goodness = 3 + 3 + 3;
800eeca4 5776 else
44576e1f 5777 goodness = 3 + 3 + extra_goodness (t, 2);
800eeca4
JW		 5778 }
5779 else if (match (t, j, 2))
44576e1f 5780 goodness = 3 + 3 + extra_goodness (t, 1);
800eeca4 5781 else
44576e1f
RH		 5782 {
5783 goodness = 3;
5784 goodness += extra_goodness (t, 1);
5785 goodness += extra_goodness (t, 2);
5786 }
800eeca4
JW		 5787 }
5788 else if (match (t, i, 1))
5789 {
5790 if (match (t, j, 2))
44576e1f 5791 goodness = 3 + 3;
800eeca4 5792 else
44576e1f 5793 goodness = 3 + extra_goodness (t, 2);
800eeca4
JW		 5794 }
5795 else if (match (t, i, 2))
44576e1f 5796 goodness = 3 + extra_goodness (t, 1);
800eeca4
JW		 5797
5798 if (goodness > best)
5799 {
5800 best = goodness;
5801 best_template[i][j][k] = t;
5802 }
5803 }
5804 }
5805
5806 for (i = 0; i < NUM_SLOTS; ++i)
5807 md.slot[i].user_template = -1;
5808
5809 md.pseudo_hash = hash_new ();
5810 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
5811 {
5812 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
5813 (void *) (pseudo_opcode + i));
5814 if (err)
5815 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5816 pseudo_opcode[i].name, err);
5817 }
5818
5819 md.reg_hash = hash_new ();
5820 md.dynreg_hash = hash_new ();
5821 md.const_hash = hash_new ();
5822 md.entry_hash = hash_new ();
5823
5824 /* general registers: */
5825
5826 total = 128;
5827 for (i = 0; i < total; ++i)
5828 {
5829 sprintf (name, "r%d", i - REG_GR);
5830 md.regsym[i] = declare_register (name, i);
5831 }
5832
5833 /* floating point registers: */
5834 total += 128;
5835 for (; i < total; ++i)
5836 {
5837 sprintf (name, "f%d", i - REG_FR);
5838 md.regsym[i] = declare_register (name, i);
5839 }
5840
5841 /* application registers: */
5842 total += 128;
5843 ar_base = i;
5844 for (; i < total; ++i)
5845 {
5846 sprintf (name, "ar%d", i - REG_AR);
5847 md.regsym[i] = declare_register (name, i);
5848 }
5849
5850 /* control registers: */
5851 total += 128;
5852 cr_base = i;
5853 for (; i < total; ++i)
5854 {
5855 sprintf (name, "cr%d", i - REG_CR);
5856 md.regsym[i] = declare_register (name, i);
5857 }
5858
5859 /* predicate registers: */
5860 total += 64;
5861 for (; i < total; ++i)
5862 {
5863 sprintf (name, "p%d", i - REG_P);
5864 md.regsym[i] = declare_register (name, i);
5865 }
5866
5867 /* branch registers: */
5868 total += 8;
5869 for (; i < total; ++i)
5870 {
5871 sprintf (name, "b%d", i - REG_BR);
5872 md.regsym[i] = declare_register (name, i);
5873 }
5874
5875 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
5876 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
5877 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
5878 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
5879 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
5880 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
5881 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
5882
5883 for (i = 0; i < NELEMS (indirect_reg); ++i)
5884 {
5885 regnum = indirect_reg[i].regnum;
5886 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
5887 }
5888
5889 /* define synonyms for application registers: */
5890 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
5891 md.regsym[i] = declare_register (ar[i - REG_AR].name,
5892 REG_AR + ar[i - REG_AR].regnum);
5893
5894 /* define synonyms for control registers: */
5895 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
5896 md.regsym[i] = declare_register (cr[i - REG_CR].name,
5897 REG_CR + cr[i - REG_CR].regnum);
5898
5899 declare_register ("gp", REG_GR + 1);
5900 declare_register ("sp", REG_GR + 12);
5901 declare_register ("rp", REG_BR + 0);
5902
e0c9811a
JW		 5903 /* pseudo-registers used to specify unwind info: */
5904 declare_register ("psp", REG_PSP);
5905
800eeca4
JW		 5906 declare_register_set ("ret", 4, REG_GR + 8);
5907 declare_register_set ("farg", 8, REG_FR + 8);
5908 declare_register_set ("fret", 8, REG_FR + 8);
5909
5910 for (i = 0; i < NELEMS (const_bits); ++i)
5911 {
5912 err = hash_insert (md.const_hash, const_bits[i].name,
5913 (PTR) (const_bits + i));
5914 if (err)
5915 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5916 name, err);
5917 }
5918
5919 /* Default to 64-bit mode. */
c43c2cc5
JW		 5920 /* ??? This overrides the -M options, but they aren't working anyways. */
5921 md.flags |= EF_IA_64_ABI64;
800eeca4
JW		 5922
5923 md.mem_offset.hint = 0;
5924 md.path = 0;
5925 md.maxpaths = 0;
5926 md.entry_labels = NULL;
5927}
5928
5929void
5930ia64_end_of_source ()
5931{
5932 /* terminate insn group upon reaching end of file: */
5933 insn_group_break (1, 0, 0);
5934
5935 /* emits slots we haven't written yet: */
5936 ia64_flush_insns ();
5937
5938 bfd_set_private_flags (stdoutput, md.flags);
5939
5940 if (debug_type == DEBUG_DWARF2)
5941 dwarf2_finish ();
5942
5943 md.mem_offset.hint = 0;
5944}
5945
5946void
5947ia64_start_line ()
5948{
5949 md.qp.X_op = O_absent;
5950
5951 if (ignore_input ())
5952 return;
5953
5954 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
5955 {
5956 if (md.detect_dv && !md.explicit_mode)
5957 as_warn (_("Explicit stops are ignored in auto mode"));
5958 else
5959 insn_group_break (1, 0, 0);
5960 }
5961}
5962
5963int
5964ia64_unrecognized_line (ch)
5965 int ch;
5966{
5967 switch (ch)
5968 {
5969 case '(':
5970 expression (&md.qp);
5971 if (*input_line_pointer++ != ')')
5972 {
5973 as_bad ("Expected ')'");
5974 return 0;
5975 }
5976 if (md.qp.X_op != O_register)
5977 {
5978 as_bad ("Qualifying predicate expected");
5979 return 0;
5980 }
5981 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
5982 {
5983 as_bad ("Predicate register expected");
5984 return 0;
5985 }
5986 return 1;
5987
5988 case '{':
5989 if (md.manual_bundling)
5990 as_warn ("Found '{' when manual bundling is already turned on");
5991 else
5992 CURR_SLOT.manual_bundling_on = 1;
5993 md.manual_bundling = 1;
5994
5995 /* bundling is only acceptable in explicit mode
5996 or when in default automatic mode */
5997 if (md.detect_dv && !md.explicit_mode)
5998 {
5999 if (!md.mode_explicitly_set
6000 && !md.default_explicit_mode)
6001 dot_dv_mode ('E');
6002 else
6003 as_warn (_("Found '{' after explicit switch to automatic mode"));
6004 }
6005 return 1;
6006
6007 case '}':
6008 if (!md.manual_bundling)
6009 as_warn ("Found '}' when manual bundling is off");
6010 else
6011 PREV_SLOT.manual_bundling_off = 1;
6012 md.manual_bundling = 0;
6013
6014 /* switch back to automatic mode, if applicable */
6015 if (md.detect_dv
6016 && md.explicit_mode
6017 && !md.mode_explicitly_set
6018 && !md.default_explicit_mode)
6019 dot_dv_mode ('A');
6020
6021 /* Allow '{' to follow on the same line. We also allow ";;", but that
6022 happens automatically because ';' is an end of line marker. */
6023 SKIP_WHITESPACE ();
6024 if (input_line_pointer[0] == '{')
6025 {
6026 input_line_pointer++;
6027 return ia64_unrecognized_line ('{');
6028 }
6029
6030 demand_empty_rest_of_line ();
6031 return 1;
6032
6033 default:
6034 break;
6035 }
6036 return 0; /* not a valid line */
6037}
6038
6039void
6040ia64_frob_label (sym)
6041 struct symbol *sym;
6042{
6043 struct label_fix *fix;
6044
6045 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6046 {
6047 md.last_text_seg = now_seg;
6048 fix = obstack_alloc (&notes, sizeof (*fix));
6049 fix->sym = sym;
6050 fix->next = CURR_SLOT.label_fixups;
6051 CURR_SLOT.label_fixups = fix;
6052
6053 /* keep track of how many code entry points we've seen */
6054 if (md.path == md.maxpaths)
6055 {
6056 md.maxpaths += 20;
6057 md.entry_labels = (const char **)
6058 xrealloc ((void *)md.entry_labels, md.maxpaths * sizeof (char *));
6059 }
6060 md.entry_labels[md.path++] = S_GET_NAME (sym);
6061 }
6062}
6063
6064void
6065ia64_flush_pending_output ()
6066{
6067 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6068 {
6069 /* ??? This causes many unnecessary stop bits to be emitted.
6070 Unfortunately, it isn't clear if it is safe to remove this. */
6071 insn_group_break (1, 0, 0);
6072 ia64_flush_insns ();
6073 }
6074}
6075
6076/* Do ia64-specific expression optimization. All that's done here is
6077 to transform index expressions that are either due to the indexing
6078 of rotating registers or due to the indexing of indirect register
6079 sets. */
6080int
6081ia64_optimize_expr (l, op, r)
6082 expressionS *l;
6083 operatorT op;
6084 expressionS *r;
6085{
6086 unsigned num_regs;
6087
6088 if (op == O_index)
6089 {
6090 if (l->X_op == O_register && r->X_op == O_constant)
6091 {
6092 num_regs = (l->X_add_number >> 16);
6093 if ((unsigned) r->X_add_number >= num_regs)
6094 {
6095 if (!num_regs)
6096 as_bad ("No current frame");
6097 else
6098 as_bad ("Index out of range 0..%u", num_regs - 1);
6099 r->X_add_number = 0;
6100 }
6101 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6102 return 1;
6103 }
6104 else if (l->X_op == O_register && r->X_op == O_register)
6105 {
6106 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6107 || l->X_add_number == IND_MEM)
6108 {
6109 as_bad ("Indirect register set name expected");
6110 l->X_add_number = IND_CPUID;
6111 }
6112 l->X_op = O_index;
6113 l->X_op_symbol = md.regsym[l->X_add_number];
6114 l->X_add_number = r->X_add_number;
6115 return 1;
6116 }
6117 }
6118 return 0;
6119}
6120
6121int
6122ia64_parse_name (name, e)
6123 char *name;
6124 expressionS *e;
6125{
6126 struct const_desc *cdesc;
6127 struct dynreg *dr = 0;
6128 unsigned int regnum;
6129 struct symbol *sym;
6130 char *end;
6131
6132 /* first see if NAME is a known register name: */
6133 sym = hash_find (md.reg_hash, name);
6134 if (sym)
6135 {
6136 e->X_op = O_register;
6137 e->X_add_number = S_GET_VALUE (sym);
6138 return 1;
6139 }
6140
6141 cdesc = hash_find (md.const_hash, name);
6142 if (cdesc)
6143 {
6144 e->X_op = O_constant;
6145 e->X_add_number = cdesc->value;
6146 return 1;
6147 }
6148
6149 /* check for inN, locN, or outN: */
6150 switch (name[0])
6151 {
6152 case 'i':
6153 if (name[1] == 'n' && isdigit (name[2]))
6154 {
6155 dr = &md.in;
6156 name += 2;
6157 }
6158 break;
6159
6160 case 'l':
6161 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6162 {
6163 dr = &md.loc;
6164 name += 3;
6165 }
6166 break;
6167
6168 case 'o':
6169 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6170 {
6171 dr = &md.out;
6172 name += 3;
6173 }
6174 break;
6175
6176 default:
6177 break;
6178 }
6179
6180 if (dr)
6181 {
6182 /* the name is inN, locN, or outN; parse the register number: */
6183 regnum = strtoul (name, &end, 10);
6184 if (end > name && *end == '\0')
6185 {
6186 if ((unsigned) regnum >= dr->num_regs)
6187 {
6188 if (!dr->num_regs)
6189 as_bad ("No current frame");
6190 else
6191 as_bad ("Register number out of range 0..%u", dr->num_regs-1);
6192 regnum = 0;
6193 }
6194 e->X_op = O_register;
6195 e->X_add_number = dr->base + regnum;
6196 return 1;
6197 }
6198 }
6199
6200 if ((dr = hash_find (md.dynreg_hash, name)))
6201 {
6202 /* We've got ourselves the name of a rotating register set.
6203 Store the base register number in the low 16 bits of
6204 X_add_number and the size of the register set in the top 16
6205 bits. */
6206 e->X_op = O_register;
6207 e->X_add_number = dr->base | (dr->num_regs << 16);
6208 return 1;
6209 }
6210 return 0;
6211}
6212
6213/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6214
6215char *
6216ia64_canonicalize_symbol_name (name)
6217 char *name;
6218{
6219 size_t len = strlen(name);
6220 if (len > 1 && name[len-1] == '#')
6221 name[len-1] = '\0';
6222 return name;
6223}
6224
6225static int
6226is_conditional_branch (idesc)
6227 struct ia64_opcode *idesc;
6228{
6229 return (strncmp (idesc->name, "br", 2) == 0
6230 && (strcmp (idesc->name, "br") == 0
6231 || strncmp (idesc->name, "br.cond", 7) == 0
6232 || strncmp (idesc->name, "br.call", 7) == 0
6233 || strncmp (idesc->name, "br.ret", 6) == 0
6234 || strcmp (idesc->name, "brl") == 0
6235 || strncmp (idesc->name, "brl.cond", 7) == 0
6236 || strncmp (idesc->name, "brl.call", 7) == 0
6237 || strncmp (idesc->name, "brl.ret", 6) == 0));
6238}
6239
6240/* Return whether the given opcode is a taken branch. If there's any doubt,
6241 returns zero */
6242static int
6243is_taken_branch (idesc)
6244 struct ia64_opcode *idesc;
6245{
6246 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
6247 || strncmp (idesc->name, "br.ia", 5) == 0);
6248}
6249
6250/* Return whether the given opcode is an interruption or rfi. If there's any
6251 doubt, returns zero */
6252static int
6253is_interruption_or_rfi (idesc)
6254 struct ia64_opcode *idesc;
6255{
6256 if (strcmp (idesc->name, "rfi") == 0)
6257 return 1;
6258 return 0;
6259}
6260
6261/* Returns the index of the given dependency in the opcode's list of chks, or
6262 -1 if there is no dependency. */
6263static int
6264depends_on (depind, idesc)
6265 int depind;
6266 struct ia64_opcode *idesc;
6267{
6268 int i;
6269 const struct ia64_opcode_dependency *dep = idesc->dependencies;
6270 for (i = 0;i < dep->nchks; i++)
6271 {
6272 if (depind == DEP(dep->chks[i]))
6273 return i;
6274 }
6275 return -1;
6276}
6277
6278/* Determine a set of specific resources used for a particular resource
6279 class. Returns the number of specific resources identified For those
6280 cases which are not determinable statically, the resource returned is
6281 marked nonspecific.
6282
6283 Meanings of value in 'NOTE':
6284 1) only read/write when the register number is explicitly encoded in the
6285 insn.
6286 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6287 accesses CFM when qualifying predicate is in the rotating region.
6288 3) general register value is used to specify an indirect register; not
6289 determinable statically.
6290 4) only read the given resource when bits 7:0 of the indirect index
6291 register value does not match the register number of the resource; not
6292 determinable statically.
6293 5) all rules are implementation specific.
6294 6) only when both the index specified by the reader and the index specified
6295 by the writer have the same value in bits 63:61; not determinable
6296 statically.
6297 7) only access the specified resource when the corresponding mask bit is
6298 set
6299 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6300 only read when these insns reference FR2-31
6301 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6302 written when these insns write FR32-127
6303 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6304 instruction
6305 11) The target predicates are written independently of PR[qp], but source
6306 registers are only read if PR[qp] is true. Since the state of PR[qp]
6307 cannot statically be determined, all source registers are marked used.
6308 12) This insn only reads the specified predicate register when that
6309 register is the PR[qp].
6310 13) This reference to ld-c only applies to teh GR whose value is loaded
6311 with data returned from memory, not the post-incremented address register.
6312 14) The RSE resource includes the implementation-specific RSE internal
6313 state resources. At least one (and possibly more) of these resources are
6314 read by each instruction listed in IC:rse-readers. At least one (and
6315 possibly more) of these resources are written by each insn listed in
6316 IC:rse-writers.
6317 15+16) Represents reserved instructions, which the assembler does not
6318 generate.
6319
6320 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6321 this code; there are no dependency violations based on memory access.
6322
6323*/
6324
6325#define MAX_SPECS 256
6326#define DV_CHK 1
6327#define DV_REG 0
6328
6329static int
6330specify_resource (dep, idesc, type, specs, note, path)
6331 const struct ia64_dependency *dep;
6332 struct ia64_opcode *idesc;
6333 int type; /* is this a DV chk or a DV reg? */
6334 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6335 int note; /* resource note for this insn's usage */
6336 int path; /* which execution path to examine */
6337{
6338 int count = 0;
6339 int i;
6340 int rsrc_write = 0;
6341 struct rsrc tmpl;
6342
6343 if (dep->mode == IA64_DV_WAW
6344 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6345 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6346 rsrc_write = 1;
6347
6348 /* template for any resources we identify */
6349 tmpl.dependency = dep;
6350 tmpl.note = note;
6351 tmpl.insn_srlz = tmpl.data_srlz = 0;
6352 tmpl.qp_regno = CURR_SLOT.qp_regno;
6353 tmpl.link_to_qp_branch = 1;
6354 tmpl.mem_offset.hint = 0;
6355 tmpl.specific = 1;
6356 tmpl.index = 0;
6357
6358#define UNHANDLED \
6359as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6360dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6361#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6362
6363 /* we don't need to track these */
6364 if (dep->semantics == IA64_DVS_NONE)
6365 return 0;
6366
6367 switch (dep->specifier)
6368 {
6369 case IA64_RS_AR_K:
6370 if (note == 1)
6371 {
6372 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6373 {
6374 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6375 if (regno >= 0 && regno <= 7)
6376 {
6377 specs[count] = tmpl;
6378 specs[count++].index = regno;
6379 }
6380 }
6381 }
6382 else if (note == 0)
6383 {
6384 for(i=0;i < 8;i++)
6385 {
6386 specs[count] = tmpl;
6387 specs[count++].index = i;
6388 }
6389 }
6390 else
6391 {
6392 UNHANDLED;
6393 }
6394 break;
6395
6396 case IA64_RS_AR_UNAT:
6397 /* This is a mov =AR or mov AR= instruction. */
6398 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6399 {
6400 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6401 if (regno == AR_UNAT)
6402 {
6403 specs[count++] = tmpl;
6404 }
6405 }
6406 else
6407 {
6408 /* This is a spill/fill, or other instruction that modifies the
6409 unat register. */
6410
6411 /* Unless we can determine the specific bits used, mark the whole
6412 thing; bits 8:3 of the memory address indicate the bit used in
6413 UNAT. The .mem.offset hint may be used to eliminate a small
6414 subset of conflicts. */
6415 specs[count] = tmpl;
6416 if (md.mem_offset.hint)
6417 {
6418 if (md.debug_dv)
6419 fprintf (stderr, " Using hint for spill/fill\n");
6420 /* the index isn't actually used, just set it to something
6421 approximating the bit index */
6422 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6423 specs[count].mem_offset.hint = 1;
6424 specs[count].mem_offset.offset = md.mem_offset.offset;
6425 specs[count++].mem_offset.base = md.mem_offset.base;
6426 }
6427 else
6428 {
6429 specs[count++].specific = 0;
6430 }
6431 }
6432 break;
6433
6434 case IA64_RS_AR:
6435 if (note == 1)
6436 {
6437 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6438 {
6439 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6440 if ((regno >= 8 && regno <= 15)
6441 || (regno >= 20 && regno <= 23)
6442 || (regno >= 31 && regno <= 39)
6443 || (regno >= 41 && regno <= 47)
6444 || (regno >= 67 && regno <= 111))
6445 {
6446 specs[count] = tmpl;
6447 specs[count++].index = regno;
6448 }
6449 }
6450 }
6451 else
6452 {
6453 UNHANDLED;
6454 }
6455 break;
6456
6457 case IA64_RS_ARb:
6458 if (note == 1)
6459 {
6460 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6461 {
6462 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6463 if ((regno >= 48 && regno <= 63)
6464 || (regno >= 112 && regno <= 127))
6465 {
6466 specs[count] = tmpl;
6467 specs[count++].index = regno;
6468 }
6469 }
6470 }
6471 else if (note == 0)
6472 {
6473 for (i=48;i < 64;i++)
6474 {
6475 specs[count] = tmpl;
6476 specs[count++].index = i;
6477 }
6478 for (i=112;i < 128;i++)
6479 {
6480 specs[count] = tmpl;
6481 specs[count++].index = i;
6482 }
6483 }
6484 else
6485 {
6486 UNHANDLED;
6487 }
6488 break;
6489
6490 case IA64_RS_BR:
6491 if (note != 1)
6492 {
6493 UNHANDLED;
6494 }
6495 else
6496 {
6497 if (rsrc_write)
6498 {
6499 for (i=0;i < idesc->num_outputs;i++)
6500 if (idesc->operands[i] == IA64_OPND_B1
6501 || idesc->operands[i] == IA64_OPND_B2)
6502 {
6503 specs[count] = tmpl;
6504 specs[count++].index =
6505 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6506 }
6507 }
6508 else
6509 {
6510 for (i = idesc->num_outputs;i < NELEMS(idesc->operands);i++)
6511 if (idesc->operands[i] == IA64_OPND_B1
6512 || idesc->operands[i] == IA64_OPND_B2)
6513 {
6514 specs[count] = tmpl;
6515 specs[count++].index =
6516 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6517 }
6518 }
6519 }
6520 break;
6521
6522 case IA64_RS_CPUID: /* four or more registers */
6523 if (note == 3)
6524 {
6525 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6526 {
6527 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6528 if (regno >= 0 && regno < NELEMS(gr_values)
6529 && KNOWN(regno))
6530 {
6531 specs[count] = tmpl;
6532 specs[count++].index = gr_values[regno].value & 0xFF;
6533 }
6534 else
6535 {
6536 specs[count] = tmpl;
6537 specs[count++].specific = 0;
6538 }
6539 }
6540 }
6541 else
6542 {
6543 UNHANDLED;
6544 }
6545 break;
6546
6547 case IA64_RS_DBR: /* four or more registers */
6548 if (note == 3)
6549 {
6550 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6551 {
6552 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6553 if (regno >= 0 && regno < NELEMS(gr_values)
6554 && KNOWN(regno))
6555 {
6556 specs[count] = tmpl;
6557 specs[count++].index = gr_values[regno].value & 0xFF;
6558 }
6559 else
6560 {
6561 specs[count] = tmpl;
6562 specs[count++].specific = 0;
6563 }
6564 }
6565 }
6566 else if (note == 0 && !rsrc_write)
6567 {
6568 specs[count] = tmpl;
6569 specs[count++].specific = 0;
6570 }
6571 else
6572 {
6573 UNHANDLED;
6574 }
6575 break;
6576
6577 case IA64_RS_IBR: /* four or more registers */
6578 if (note == 3)
6579 {
6580 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6581 {
6582 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6583 if (regno >= 0 && regno < NELEMS(gr_values)
6584 && KNOWN(regno))
6585 {
6586 specs[count] = tmpl;
6587 specs[count++].index = gr_values[regno].value & 0xFF;
6588 }
6589 else
6590 {
6591 specs[count] = tmpl;
6592 specs[count++].specific = 0;
6593 }
6594 }
6595 }
6596 else
6597 {
6598 UNHANDLED;
6599 }
6600 break;
6601
6602 case IA64_RS_MSR:
6603 if (note == 5)
6604 {
6605 /* These are implementation specific. Force all references to
6606 conflict with all other references. */
6607 specs[count] = tmpl;
6608 specs[count++].specific = 0;
6609 }
6610 else
6611 {
6612 UNHANDLED;
6613 }
6614 break;
6615
6616 case IA64_RS_PKR: /* 16 or more registers */
6617 if (note == 3 || note == 4)
6618 {
6619 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6620 {
6621 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6622 if (regno >= 0 && regno < NELEMS(gr_values)
6623 && KNOWN(regno))
6624 {
6625 if (note == 3)
6626 {
6627 specs[count] = tmpl;
6628 specs[count++].index = gr_values[regno].value & 0xFF;
6629 }
6630 else for (i=0;i < NELEMS(gr_values);i++)
6631 {
6632 /* uses all registers *except* the one in R3 */
6633 if (i != (gr_values[regno].value & 0xFF))
6634 {
6635 specs[count] = tmpl;
6636 specs[count++].index = i;
6637 }
6638 }
6639 }
6640 else
6641 {
6642 specs[count] = tmpl;
6643 specs[count++].specific = 0;
6644 }
6645 }
6646 }
6647 else if (note == 0)
6648 {
6649 /* probe et al. */
6650 specs[count] = tmpl;
6651 specs[count++].specific = 0;
6652 }
6653 break;
6654
6655 case IA64_RS_PMC: /* four or more registers */
6656 if (note == 3)
6657 {
6658 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
6659 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
6660
6661 {
6662 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
6663 ? 1 : !rsrc_write);
6664 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
6665 if (regno >= 0 && regno < NELEMS(gr_values)
6666 && KNOWN(regno))
6667 {
6668 specs[count] = tmpl;
6669 specs[count++].index = gr_values[regno].value & 0xFF;
6670 }
6671 else
6672 {
6673 specs[count] = tmpl;
6674 specs[count++].specific = 0;
6675 }
6676 }
6677 }
6678 else
6679 {
6680 UNHANDLED;
6681 }
6682 break;
6683
6684 case IA64_RS_PMD: /* four or more registers */
6685 if (note == 3)
6686 {
6687 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
6688 {
6689 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6690 if (regno >= 0 && regno < NELEMS(gr_values)
6691 && KNOWN(regno))
6692 {
6693 specs[count] = tmpl;
6694 specs[count++].index = gr_values[regno].value & 0xFF;
6695 }
6696 else
6697 {
6698 specs[count] = tmpl;
6699 specs[count++].specific = 0;
6700 }
6701 }
6702 }
6703 else
6704 {
6705 UNHANDLED;
6706 }
6707 break;
6708
6709 case IA64_RS_RR: /* eight registers */
6710 if (note == 6)
6711 {
6712 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
6713 {
6714 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6715 if (regno >= 0 && regno < NELEMS(gr_values)
6716 && KNOWN(regno))
6717 {
6718 specs[count] = tmpl;
6719 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
6720 }
6721 else
6722 {
6723 specs[count] = tmpl;
6724 specs[count++].specific = 0;
6725 }
6726 }
6727 }
6728 else if (note == 0 && !rsrc_write)
6729 {
6730 specs[count] = tmpl;
6731 specs[count++].specific = 0;
6732 }
6733 else
6734 {
6735 UNHANDLED;
6736 }
6737 break;
6738
6739 case IA64_RS_CR_IRR:
6740 if (note == 0)
6741 {
6742 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6743 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
6744 if (rsrc_write
6745 && idesc->operands[1] == IA64_OPND_CR3
6746 && regno == CR_IVR)
6747 {
6748 for(i=0;i < 4;i++)
6749 {
6750 specs[count] = tmpl;
6751 specs[count++].index = CR_IRR0 + i;
6752 }
6753 }
6754 }
6755 else if (note == 1)
6756 {
6757 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6758 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6759 && regno >= CR_IRR0
6760 && regno <= CR_IRR3)
6761 {
6762 specs[count] = tmpl;
6763 specs[count++].index = regno;
6764 }
6765 }
6766 else
6767 {
6768 UNHANDLED;
6769 }
6770 break;
6771
6772 case IA64_RS_CR_LRR:
6773 if (note != 1)
6774 {
6775 UNHANDLED;
6776 }
6777 else
6778 {
6779 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6780 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6781 && (regno == CR_LRR0 || regno == CR_LRR1))
6782 {
6783 specs[count] = tmpl;
6784 specs[count++].index = regno;
6785 }
6786 }
6787 break;
6788
6789 case IA64_RS_CR:
6790 if (note == 1)
6791 {
6792 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
6793 {
6794 specs[count] = tmpl;
6795 specs[count++].index =
6796 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6797 }
6798 }
6799 else
6800 {
6801 UNHANDLED;
6802 }
6803 break;
6804
6805 case IA64_RS_FR:
6806 case IA64_RS_FRb:
6807 if (note != 1)
6808 {
6809 UNHANDLED;
6810 }
6811 else if (rsrc_write)
6812 {
6813 if (dep->specifier == IA64_RS_FRb
6814 && idesc->operands[0] == IA64_OPND_F1)
6815 {
6816 specs[count] = tmpl;
6817 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
6818 }
6819 }
6820 else
6821 {
6822 for (i=idesc->num_outputs;i < NELEMS(idesc->operands);i++)
6823 {
6824 if (idesc->operands[i] == IA64_OPND_F2
6825 || idesc->operands[i] == IA64_OPND_F3
6826 || idesc->operands[i] == IA64_OPND_F4)
6827 {
6828 specs[count] = tmpl;
6829 specs[count++].index =
6830 CURR_SLOT.opnd[i].X_add_number - REG_FR;
6831 }
6832 }
6833 }
6834 break;
6835
6836 case IA64_RS_GR:
6837 if (note == 13)
6838 {
6839 /* This reference applies only to the GR whose value is loaded with
6840 data returned from memory */
6841 specs[count] = tmpl;
6842 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
6843 }
6844 else if (note == 1)
6845 {
6846 if (rsrc_write)
6847 {
50b81f19
JW		 6848 for (i= 0; i < idesc->num_outputs; i++)
6849 if (idesc->operands[i] == IA64_OPND_R1
6850 || idesc->operands[i] == IA64_OPND_R2
6851 || idesc->operands[i] == IA64_OPND_R3)
6852 {
6853 specs[count] = tmpl;
6854 specs[count++].index =
6855 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6856 }
6857 if (idesc->flags & IA64_OPCODE_POSTINC)
6858 for (i = 0; i < NELEMS (idesc->operands); i++)
6859 if (idesc->operands[i] == IA64_OPND_MR3)
6860 {
6861 specs[count] = tmpl;
6862 specs[count++].index =
6863 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6864 }
800eeca4
JW		 6865 }
6866 else
6867 {
6868 /* Look for anything that reads a GR */
6869 for (i=0;i < NELEMS(idesc->operands);i++)
6870 {
6871 if (idesc->operands[i] == IA64_OPND_MR3
6872 || idesc->operands[i] == IA64_OPND_CPUID_R3
6873 || idesc->operands[i] == IA64_OPND_DBR_R3
6874 || idesc->operands[i] == IA64_OPND_IBR_R3
6875 || idesc->operands[i] == IA64_OPND_MSR_R3
6876 || idesc->operands[i] == IA64_OPND_PKR_R3
6877 || idesc->operands[i] == IA64_OPND_PMC_R3
6878 || idesc->operands[i] == IA64_OPND_PMD_R3
6879 || idesc->operands[i] == IA64_OPND_RR_R3
6880 || ((i >= idesc->num_outputs)
6881 && (idesc->operands[i] == IA64_OPND_R1
6882 || idesc->operands[i] == IA64_OPND_R2
50b81f19
JW		 6883 || idesc->operands[i] == IA64_OPND_R3
6884 /* addl source register. */
6885 || idesc->operands[i] == IA64_OPND_R3_2)))
800eeca4
JW		 6886 {
6887 specs[count] = tmpl;
6888 specs[count++].index =
6889 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6890 }
6891 }
6892 }
6893 }
6894 else
6895 {
6896 UNHANDLED;
6897 }
6898 break;
6899
6900 case IA64_RS_PR:
6901 if (note == 0)
6902 {
6903 if (idesc->operands[0] == IA64_OPND_PR_ROT)
6904 {
6905 for (i=16;i < 63;i++)
6906 {
6907 specs[count] = tmpl;
6908 specs[count++].index = i;
6909 }
6910 }
6911 else
6912 {
6913 for (i=1;i < 63;i++)
6914 {
6915 specs[count] = tmpl;
6916 specs[count++].index = i;
6917 }
6918 }
6919 }
6920 else if (note == 7)
6921 {
6922 valueT mask = 0;
6923 /* mark only those registers indicated by the mask */
6924 if (rsrc_write
6925 && idesc->operands[0] == IA64_OPND_PR)
6926 {
6927 mask = CURR_SLOT.opnd[2].X_add_number;
6928 if (mask & ((valueT)1<<16))
6929 mask |= ~(valueT)0xffff;
6930 for (i=1;i < 63;i++)
6931 {
6932 if (mask & ((valueT)1<<i))
6933 {
6934 specs[count] = tmpl;
6935 specs[count++].index = i;
6936 }
6937 }
6938 }
6939 else if (rsrc_write
6940 && idesc->operands[0] == IA64_OPND_PR_ROT)
6941 {
6942 for (i=16;i < 63;i++)
6943 {
6944 specs[count] = tmpl;
6945 specs[count++].index = i;
6946 }
6947 }
6948 else
6949 {
6950 UNHANDLED;
6951 }
6952 }
6953 else if (note == 11) /* note 11 implies note 1 as well */
6954 {
6955 if (rsrc_write)
6956 {
6957 for (i=0;i < idesc->num_outputs;i++)
6958 {
6959 if (idesc->operands[i] == IA64_OPND_P1
6960 || idesc->operands[i] == IA64_OPND_P2)
6961 {
6962 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
6963 if (regno != 0)
6964 {
6965 specs[count] = tmpl;
6966 specs[count++].index = regno;
6967 }
6968 }
6969 }
6970 }
6971 else
6972 {
6973 UNHANDLED;
6974 }
6975 }
6976 else if (note == 12)
6977 {
6978 if (CURR_SLOT.qp_regno != 0)
6979 {
6980 specs[count] = tmpl;
6981 specs[count++].index = CURR_SLOT.qp_regno;
6982 }
6983 }
6984 else if (note == 1)
6985 {
6986 if (rsrc_write)
6987 {
6988 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
6989 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
6990 if ((idesc->operands[0] == IA64_OPND_P1
6991 || idesc->operands[0] == IA64_OPND_P2)
6992 && p1 != 0 && p1 != 63)
6993 {
6994 specs[count] = tmpl;
6995 specs[count++].index = p1;
6996 }
6997 if ((idesc->operands[1] == IA64_OPND_P1
6998 || idesc->operands[1] == IA64_OPND_P2)
6999 && p2 != 0 && p2 != 63)
7000 {
7001 specs[count] = tmpl;
7002 specs[count++].index = p2;
7003 }
7004 }
7005 else
7006 {
7007 if (CURR_SLOT.qp_regno != 0)
7008 {
7009 specs[count] = tmpl;
7010 specs[count++].index = CURR_SLOT.qp_regno;
7011 }
7012 if (idesc->operands[1] == IA64_OPND_PR)
7013 {
7014 for (i=1;i < 63;i++)
7015 {
7016 specs[count] = tmpl;
7017 specs[count++].index = i;
7018 }
7019 }
7020 }
7021 }
7022 else
7023 {
7024 UNHANDLED;
7025 }
7026 break;
7027
7028 case IA64_RS_PSR:
7029 /* Verify that the instruction is using the PSR bit indicated in
7030 dep->regindex */
7031 if (note == 0)
7032 {
7033 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7034 {
7035 if (dep->regindex < 6)
7036 {
7037 specs[count++] = tmpl;
7038 }
7039 }
7040 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7041 {
7042 if (dep->regindex < 32
7043 || dep->regindex == 35
7044 || dep->regindex == 36
7045 || (!rsrc_write && dep->regindex == PSR_CPL))
7046 {
7047 specs[count++] = tmpl;
7048 }
7049 }
7050 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7051 {
7052 if (dep->regindex < 32
7053 || dep->regindex == 35
7054 || dep->regindex == 36
7055 || (rsrc_write && dep->regindex == PSR_CPL))
7056 {
7057 specs[count++] = tmpl;
7058 }
7059 }
7060 else
7061 {
7062 /* Several PSR bits have very specific dependencies. */
7063 switch (dep->regindex)
7064 {
7065 default:
7066 specs[count++] = tmpl;
7067 break;
7068 case PSR_IC:
7069 if (rsrc_write)
7070 {
7071 specs[count++] = tmpl;
7072 }
7073 else
7074 {
7075 /* Only certain CR accesses use PSR.ic */
7076 if (idesc->operands[0] == IA64_OPND_CR3
7077 || idesc->operands[1] == IA64_OPND_CR3)
7078 {
7079 int index =
7080 ((idesc->operands[0] == IA64_OPND_CR3)
7081 ? 0 : 1);
7082 int regno =
7083 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7084
7085 switch (regno)
7086 {
7087 default:
7088 break;
7089 case CR_ITIR:
7090 case CR_IFS:
7091 case CR_IIM:
7092 case CR_IIP:
7093 case CR_IPSR:
7094 case CR_ISR:
7095 case CR_IFA:
7096 case CR_IHA:
7097 case CR_IIPA:
7098 specs[count++] = tmpl;
7099 break;
7100 }
7101 }
7102 }
7103 break;
7104 case PSR_CPL:
7105 if (rsrc_write)
7106 {
7107 specs[count++] = tmpl;
7108 }
7109 else
7110 {
7111 /* Only some AR accesses use cpl */
7112 if (idesc->operands[0] == IA64_OPND_AR3
7113 || idesc->operands[1] == IA64_OPND_AR3)
7114 {
7115 int index =
7116 ((idesc->operands[0] == IA64_OPND_AR3)
7117 ? 0 : 1);
7118 int regno =
7119 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7120
7121 if (regno == AR_ITC
7122 || (index == 0
7123 && (regno == AR_ITC
7124 || regno == AR_RSC
7125 || (regno >= AR_K0
7126 && regno <= AR_K7))))
7127 {
7128 specs[count++] = tmpl;
7129 }
7130 }
7131 else
7132 {
7133 specs[count++] = tmpl;
7134 }
7135 break;
7136 }
7137 }
7138 }
7139 }
7140 else if (note == 7)
7141 {
7142 valueT mask = 0;
7143 if (idesc->operands[0] == IA64_OPND_IMMU24)
7144 {
7145 mask = CURR_SLOT.opnd[0].X_add_number;
7146 }
7147 else
7148 {
7149 UNHANDLED;
7150 }
7151 if (mask & ((valueT)1<<dep->regindex))
7152 {
7153 specs[count++] = tmpl;
7154 }
7155 }
7156 else if (note == 8)
7157 {
7158 int min = dep->regindex == PSR_DFL ? 2 : 32;
7159 int max = dep->regindex == PSR_DFL ? 31 : 127;
7160 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7161 for (i=0;i < NELEMS(idesc->operands);i++)
7162 {
7163 if (idesc->operands[i] == IA64_OPND_F1
7164 || idesc->operands[i] == IA64_OPND_F2
7165 || idesc->operands[i] == IA64_OPND_F3
7166 || idesc->operands[i] == IA64_OPND_F4)
7167 {
7168 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7169 if (reg >= min && reg <= max)
7170 {
7171 specs[count++] = tmpl;
7172 }
7173 }
7174 }
7175 }
7176 else if (note == 9)
7177 {
7178 int min = dep->regindex == PSR_MFL ? 2 : 32;
7179 int max = dep->regindex == PSR_MFL ? 31 : 127;
7180 /* mfh is read on writes to FR32-127; mfl is read on writes to
7181 FR2-31 */
7182 for (i=0;i < idesc->num_outputs;i++)
7183 {
7184 if (idesc->operands[i] == IA64_OPND_F1)
7185 {
7186 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7187 if (reg >= min && reg <= max)
7188 {
7189 specs[count++] = tmpl;
7190 }
7191 }
7192 }
7193 }
7194 else if (note == 10)
7195 {
7196 for (i=0;i < NELEMS(idesc->operands);i++)
7197 {
7198 if (idesc->operands[i] == IA64_OPND_R1
7199 || idesc->operands[i] == IA64_OPND_R2
7200 || idesc->operands[i] == IA64_OPND_R3)
7201 {
7202 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7203 if (regno >= 16 && regno <= 31)
7204 {
7205 specs[count++] = tmpl;
7206 }
7207 }
7208 }
7209 }
7210 else
7211 {
7212 UNHANDLED;
7213 }
7214 break;
7215
7216 case IA64_RS_AR_FPSR:
7217 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7218 {
7219 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7220 if (regno == AR_FPSR)
7221 {
7222 specs[count++] = tmpl;
7223 }
7224 }
7225 else
7226 {
7227 specs[count++] = tmpl;
7228 }
7229 break;
7230
7231 case IA64_RS_ARX:
7232 /* Handle all AR[REG] resources */
7233 if (note == 0 || note == 1)
7234 {
7235 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7236 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7237 && regno == dep->regindex)
7238 {
7239 specs[count++] = tmpl;
7240 }
7241 /* other AR[REG] resources may be affected by AR accesses */
7242 else if (idesc->operands[0] == IA64_OPND_AR3)
7243 {
7244 /* AR[] writes */
7245 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7246 switch (dep->regindex)
7247 {
7248 default:
7249 break;
7250 case AR_BSP:
7251 case AR_RNAT:
7252 if (regno == AR_BSPSTORE)
7253 {
7254 specs[count++] = tmpl;
7255 }
7256 case AR_RSC:
7257 if (!rsrc_write &&
7258 (regno == AR_BSPSTORE
7259 || regno == AR_RNAT))
7260 {
7261 specs[count++] = tmpl;
7262 }
7263 break;
7264 }
7265 }
7266 else if (idesc->operands[1] == IA64_OPND_AR3)
7267 {
7268 /* AR[] reads */
7269 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7270 switch (dep->regindex)
7271 {
7272 default:
7273 break;
7274 case AR_RSC:
7275 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7276 {
7277 specs[count++] = tmpl;
7278 }
7279 break;
7280 }
7281 }
7282 else
7283 {
7284 specs[count++] = tmpl;
7285 }
7286 }
7287 else
7288 {
7289 UNHANDLED;
7290 }
7291 break;
7292
7293 case IA64_RS_CRX:
7294 /* Handle all CR[REG] resources */
7295 if (note == 0 || note == 1)
7296 {
7297 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7298 {
7299 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7300 if (regno == dep->regindex)
7301 {
7302 specs[count++] = tmpl;
7303 }
7304 else if (!rsrc_write)
7305 {
7306 /* Reads from CR[IVR] affect other resources. */
7307 if (regno == CR_IVR)
7308 {
7309 if ((dep->regindex >= CR_IRR0
7310 && dep->regindex <= CR_IRR3)
7311 || dep->regindex == CR_TPR)
7312 {
7313 specs[count++] = tmpl;
7314 }
7315 }
7316 }
7317 }
7318 else
7319 {
7320 specs[count++] = tmpl;
7321 }
7322 }
7323 else
7324 {
7325 UNHANDLED;
7326 }
7327 break;
7328
7329 case IA64_RS_INSERVICE:
7330 /* look for write of EOI (67) or read of IVR (65) */
7331 if ((idesc->operands[0] == IA64_OPND_CR3
7332 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7333 || (idesc->operands[1] == IA64_OPND_CR3
7334 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7335 {
7336 specs[count++] = tmpl;
7337 }
7338 break;
7339
7340 case IA64_RS_GR0:
7341 if (note == 1)
7342 {
7343 specs[count++] = tmpl;
7344 }
7345 else
7346 {
7347 UNHANDLED;
7348 }
7349 break;
7350
7351 case IA64_RS_CFM:
7352 if (note != 2)
7353 {
7354 specs[count++] = tmpl;
7355 }
7356 else
7357 {
7358 /* Check if any of the registers accessed are in the rotating region.
7359 mov to/from pr accesses CFM only when qp_regno is in the rotating
7360 region */
7361 for (i=0;i < NELEMS(idesc->operands);i++)
7362 {
7363 if (idesc->operands[i] == IA64_OPND_R1
7364 || idesc->operands[i] == IA64_OPND_R2
7365 || idesc->operands[i] == IA64_OPND_R3)
7366 {
7367 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7368 /* Assumes that md.rot.num_regs is always valid */
7369 if (md.rot.num_regs > 0
7370 && num > 31
7371 && num < 31 + md.rot.num_regs)
7372 {
7373 specs[count] = tmpl;
7374 specs[count++].specific = 0;
7375 }
7376 }
7377 else if (idesc->operands[i] == IA64_OPND_F1
7378 || idesc->operands[i] == IA64_OPND_F2
7379 || idesc->operands[i] == IA64_OPND_F3
7380 || idesc->operands[i] == IA64_OPND_F4)
7381 {
7382 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7383 if (num > 31)
7384 {
7385 specs[count] = tmpl;
7386 specs[count++].specific = 0;
7387 }
7388 }
7389 else if (idesc->operands[i] == IA64_OPND_P1
7390 || idesc->operands[i] == IA64_OPND_P2)
7391 {
7392 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7393 if (num > 15)
7394 {
7395 specs[count] = tmpl;
7396 specs[count++].specific = 0;
7397 }
7398 }
7399 }
7400 if (CURR_SLOT.qp_regno > 15)
7401 {
7402 specs[count] = tmpl;
7403 specs[count++].specific = 0;
7404 }
7405 }
7406 break;
7407
7408 case IA64_RS_PR63:
7409 if (note == 0)
7410 {
7411 specs[count++] = tmpl;
7412 }
7413 else if (note == 11)
7414 {
7415 if ((idesc->operands[0] == IA64_OPND_P1
7416 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7417 || (idesc->operands[1] == IA64_OPND_P2
7418 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7419 {
7420 specs[count++] = tmpl;
7421 }
7422 }
7423 else if (note == 12)
7424 {
7425 if (CURR_SLOT.qp_regno == 63)
7426 {
7427 specs[count++] = tmpl;
7428 }
7429 }
7430 else if (note == 7)
7431 {
7432 valueT mask = 0;
7433 if (idesc->operands[2] == IA64_OPND_IMM17)
7434 mask = CURR_SLOT.opnd[2].X_add_number;
7435 if (mask & ((valueT)1<<63))
7436 {
7437 specs[count++] = tmpl;
7438 }
7439 }
7440 else if (note == 1)
7441 {
7442 if (rsrc_write)
7443 {
7444 for (i=0;i < idesc->num_outputs;i++)
7445 if ((idesc->operands[i] == IA64_OPND_P1
7446 || idesc->operands[i] == IA64_OPND_P2)
7447 && CURR_SLOT.opnd[i].X_add_number - REG_P == 63)
7448 {
7449 specs[count++] = tmpl;
7450 }
7451 }
7452 else
7453 {
7454 if (CURR_SLOT.qp_regno == 63)
7455 {
7456 specs[count++] = tmpl;
7457 }
7458 }
7459 }
7460 else
7461 {
7462 UNHANDLED;
7463 }
7464 break;
7465
7466 case IA64_RS_RSE:
7467 /* FIXME we can identify some individual RSE written resources, but RSE
7468 read resources have not yet been completely identified, so for now
7469 treat RSE as a single resource */
7470 if (strncmp (idesc->name, "mov", 3) == 0)
7471 {
7472 if (rsrc_write)
7473 {
7474 if (idesc->operands[0] == IA64_OPND_AR3
7475 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7476 {
7477 specs[count] = tmpl;
7478 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7479 }
7480 }
7481 else
7482 {
7483 if (idesc->operands[0] == IA64_OPND_AR3)
7484 {
7485 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7486 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7487 {
7488 specs[count++] = tmpl;
7489 }
7490 }
7491 else if (idesc->operands[1] == IA64_OPND_AR3)
7492 {
7493 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7494 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7495 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7496 {
7497 specs[count++] = tmpl;
7498 }
7499 }
7500 }
7501 }
7502 else
7503 {
7504 specs[count++] = tmpl;
7505 }
7506 break;
7507
7508 case IA64_RS_ANY:
7509 /* FIXME -- do any of these need to be non-specific? */
7510 specs[count++] = tmpl;
7511 break;
7512
7513 default:
7514 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7515 break;
7516 }
7517
7518 return count;
7519}
7520
7521/* Clear branch flags on marked resources. This breaks the link between the
7522 QP of the marking instruction and a subsequent branch on the same QP.
7523*/
7524static void
7525clear_qp_branch_flag (mask)
7526 valueT mask;
7527{
7528 int i;
7529 for (i = 0;i < regdepslen;i++)
7530 {
7531 valueT bit = ((valueT)1 << regdeps[i].qp_regno);
7532 if ((bit & mask) != 0)
7533 {
7534 regdeps[i].link_to_qp_branch = 0;
7535 }
7536 }
7537}
7538
7539/* Remove any mutexes which contain any of the PRs indicated in the mask.
7540
7541 Any changes to a PR clears the mutex relations which include that PR.
7542*/
7543static void
7544clear_qp_mutex (mask)
7545 valueT mask;
7546{
7547 int i;
7548
7549 i = 0;
7550 while (i < qp_mutexeslen)
7551 {
7552 if ((qp_mutexes[i].prmask & mask) != 0)
7553 {
7554 if (md.debug_dv)
7555 {
7556 fprintf (stderr, " Clearing mutex relation");
7557 print_prmask (qp_mutexes[i].prmask);
7558 fprintf (stderr, "\n");
7559 }
7560 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
7561 }
7562 else
7563 ++i;
7564 }
7565}
7566
7567/* Clear implies relations which contain PRs in the given masks.
7568 P1_MASK indicates the source of the implies relation, while P2_MASK
7569 indicates the implied PR.
7570*/
7571static void
7572clear_qp_implies (p1_mask, p2_mask)
7573 valueT p1_mask;
7574 valueT p2_mask;
7575{
7576 int i;
7577
7578 i = 0;
7579 while (i < qp_implieslen)
7580 {
7581 if ((((valueT)1 << qp_implies[i].p1) & p1_mask) != 0
7582 || (((valueT)1 << qp_implies[i].p2) & p2_mask) != 0)
7583 {
7584 if (md.debug_dv)
7585 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
7586 qp_implies[i].p1, qp_implies[i].p2);
7587 qp_implies[i] = qp_implies[--qp_implieslen];
7588 }
7589 else
7590 ++i;
7591 }
7592}
7593
7594/* add the PRs specified to the list of implied relations */
7595static void
7596add_qp_imply (p1, p2)
7597 int p1, p2;
7598{
7599 valueT mask;
7600 valueT bit;
7601 int i;
7602
7603 /* p0 is not meaningful here */
7604 if (p1 == 0 || p2 == 0)
7605 abort ();
7606
7607 if (p1 == p2)
7608 return;
7609
7610 /* if it exists already, ignore it */
7611 for (i=0;i < qp_implieslen;i++)
7612 {
7613 if (qp_implies[i].p1 == p1
7614 && qp_implies[i].p2 == p2
7615 && qp_implies[i].path == md.path
7616 && !qp_implies[i].p2_branched)
7617 return;
7618 }
7619
7620 if (qp_implieslen == qp_impliestotlen)
7621 {
7622 qp_impliestotlen += 20;
7623 qp_implies = (struct qp_imply *)
7624 xrealloc ((void *)qp_implies,
7625 qp_impliestotlen * sizeof (struct qp_imply));
7626 }
7627 if (md.debug_dv)
7628 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
7629 qp_implies[qp_implieslen].p1 = p1;
7630 qp_implies[qp_implieslen].p2 = p2;
7631 qp_implies[qp_implieslen].path = md.path;
7632 qp_implies[qp_implieslen++].p2_branched = 0;
7633
7634 /* Add in the implied transitive relations; for everything that p2 implies,
7635 make p1 imply that, too; for everything that implies p1, make it imply p2
7636 as well. */
7637 for (i=0;i < qp_implieslen;i++)
7638 {
7639 if (qp_implies[i].p1 == p2)
7640 add_qp_imply (p1, qp_implies[i].p2);
7641 if (qp_implies[i].p2 == p1)
7642 add_qp_imply (qp_implies[i].p1, p2);
7643 }
7644 /* Add in mutex relations implied by this implies relation; for each mutex
7645 relation containing p2, duplicate it and replace p2 with p1. */
7646 bit = (valueT)1 << p1;
7647 mask = (valueT)1 << p2;
7648 for (i=0;i < qp_mutexeslen;i++)
7649 {
7650 if (qp_mutexes[i].prmask & mask)
7651 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
7652 }
7653}
7654
7655
7656/* Add the PRs specified in the mask to the mutex list; this means that only
7657 one of the PRs can be true at any time. PR0 should never be included in
7658 the mask. */
7659static void
7660add_qp_mutex (mask)
7661 valueT mask;
7662{
7663 if (mask & 0x1)
7664 abort ();
7665
7666 if (qp_mutexeslen == qp_mutexestotlen)
7667 {
7668 qp_mutexestotlen += 20;
7669 qp_mutexes = (struct qpmutex *)
7670 xrealloc ((void *)qp_mutexes,
7671 qp_mutexestotlen * sizeof (struct qpmutex));
7672 }
7673 if (md.debug_dv)
7674 {
7675 fprintf (stderr, " Registering mutex on");
7676 print_prmask (mask);
7677 fprintf (stderr, "\n");
7678 }
7679 qp_mutexes[qp_mutexeslen].path = md.path;
7680 qp_mutexes[qp_mutexeslen++].prmask = mask;
7681}
7682
7683static void
7684clear_register_values ()
7685{
7686 int i;
7687 if (md.debug_dv)
7688 fprintf (stderr, " Clearing register values\n");
7689 for (i=1;i < NELEMS(gr_values);i++)
7690 gr_values[i].known = 0;
7691}
7692
7693/* Keep track of register values/changes which affect DV tracking.
7694
7695 optimization note: should add a flag to classes of insns where otherwise we
7696 have to examine a group of strings to identify them.
7697
7698 */
7699static void
7700note_register_values (idesc)
7701 struct ia64_opcode *idesc;
7702{
7703 valueT qp_changemask = 0;
7704 int i;
7705
7706 /* invalidate values for registers being written to */
7707 for (i=0;i < idesc->num_outputs;i++)
7708 {
7709 if (idesc->operands[i] == IA64_OPND_R1
7710 || idesc->operands[i] == IA64_OPND_R2
7711 || idesc->operands[i] == IA64_OPND_R3)
7712 {
7713 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7714 if (regno > 0 && regno < NELEMS(gr_values))
7715 gr_values[regno].known = 0;
7716 }
50b81f19
JW		 7717 else if (idesc->operands[i] == IA64_OPND_R3_2)
7718 {
7719 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7720 if (regno > 0 && regno < 4)
7721 gr_values[regno].known = 0;
7722 }
800eeca4
JW		 7723 else if (idesc->operands[i] == IA64_OPND_P1
7724 || idesc->operands[i] == IA64_OPND_P2)
7725 {
7726 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7727 qp_changemask |= (valueT)1 << regno;
7728 }
7729 else if (idesc->operands[i] == IA64_OPND_PR)
7730 {
7731 if (idesc->operands[2] & (valueT)0x10000)
7732 qp_changemask = ~(valueT)0x1FFFF | idesc->operands[2];
7733 else
7734 qp_changemask = idesc->operands[2];
7735 break;
7736 }
7737 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
7738 {
7739 if (idesc->operands[1] & ((valueT)1 << 43))
7740 qp_changemask = ~(valueT)0xFFFFFFFFFFF | idesc->operands[1];
7741 else
7742 qp_changemask = idesc->operands[1];
7743 qp_changemask &= ~(valueT)0xFFFF;
7744 break;
7745 }
7746 }
7747
7748 /* Always clear qp branch flags on any PR change */
7749 /* FIXME there may be exceptions for certain compares */
7750 clear_qp_branch_flag (qp_changemask);
7751
7752 /* invalidate rotating registers on insns which affect RRBs in CFM */
7753 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
7754 {
7755 qp_changemask |= ~(valueT)0xFFFF;
7756 if (strcmp (idesc->name, "clrrrb.pr") != 0)
7757 {
7758 for (i=32;i < 32+md.rot.num_regs;i++)
7759 gr_values[i].known = 0;
7760 }
7761 clear_qp_mutex (qp_changemask);
7762 clear_qp_implies (qp_changemask, qp_changemask);
7763 }
7764 /* after a call, all register values are undefined, except those marked
7765 as "safe" */
7766 else if (strncmp (idesc->name, "br.call", 6) == 0
7767 || strncmp (idesc->name, "brl.call", 7) == 0)
7768 {
7769 // FIXME keep GR values which are marked as "safe_across_calls"
7770 clear_register_values ();
7771 clear_qp_mutex (~qp_safe_across_calls);
7772 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
7773 clear_qp_branch_flag (~qp_safe_across_calls);
7774 }
e9718fe1
TW		 7775 else if (is_interruption_or_rfi (idesc)
7776 || is_taken_branch (idesc))
7777 {
7778 clear_register_values ();
7779 clear_qp_mutex (~(valueT)0);
7780 clear_qp_implies (~(valueT)0, ~(valueT)0);
7781 }
800eeca4
JW		 7782 /* Look for mutex and implies relations */
7783 else if ((idesc->operands[0] == IA64_OPND_P1
7784 || idesc->operands[0] == IA64_OPND_P2)
7785 && (idesc->operands[1] == IA64_OPND_P1
7786 || idesc->operands[1] == IA64_OPND_P2))
7787 {
7788 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7789 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7790 valueT p1mask = (valueT)1 << p1;
7791 valueT p2mask = (valueT)1 << p2;
7792
7793 /* if one of the PRs is PR0, we can't really do anything */
7794 if (p1 == 0 || p2 == 0)
7795 {
7796 if (md.debug_dv)
7797 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
7798 }
7799 /* In general, clear mutexes and implies which include P1 or P2,
7800 with the following exceptions */
7801 else if (strstr (idesc->name, ".or.andcm") != NULL)
7802 {
7803 add_qp_mutex (p1mask | p2mask);
7804 clear_qp_implies (p2mask, p1mask);
7805 }
7806 else if (strstr (idesc->name, ".and.orcm") != NULL)
7807 {
7808 add_qp_mutex (p1mask | p2mask);
7809 clear_qp_implies (p1mask, p2mask);
7810 }
7811 else if (strstr (idesc->name, ".and") != NULL)
7812 {
7813 clear_qp_implies (0, p1mask | p2mask);
7814 }
7815 else if (strstr (idesc->name, ".or") != NULL)
7816 {
7817 clear_qp_mutex (p1mask | p2mask);
7818 clear_qp_implies (p1mask | p2mask, 0);
7819 }
7820 else
7821 {
7822 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
7823 if (strstr (idesc->name, ".unc") != NULL)
7824 {
7825 add_qp_mutex (p1mask | p2mask);
7826 if (CURR_SLOT.qp_regno != 0)
7827 {
7828 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
7829 CURR_SLOT.qp_regno);
7830 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
7831 CURR_SLOT.qp_regno);
7832 }
7833 }
7834 else if (CURR_SLOT.qp_regno == 0)
7835 {
7836 add_qp_mutex (p1mask | p2mask);
7837 }
7838 else
7839 {
7840 clear_qp_mutex (p1mask | p2mask);
7841 }
7842 }
7843 }
7844 /* Look for mov imm insns into GRs */
7845 else if (idesc->operands[0] == IA64_OPND_R1
7846 && (idesc->operands[1] == IA64_OPND_IMM22
7847 || idesc->operands[1] == IA64_OPND_IMMU64)
7848 && (strcmp(idesc->name, "mov") == 0
7849 || strcmp(idesc->name, "movl") == 0))
7850 {
7851 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7852 if (regno > 0 && regno < NELEMS(gr_values))
7853 {
7854 gr_values[regno].known = 1;
7855 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
7856 gr_values[regno].path = md.path;
7857 if (md.debug_dv)
7858 fprintf (stderr, " Know gr%d = 0x%llx\n",
7859 regno, gr_values[regno].value);
7860 }
7861 }
7862 else
7863 {
7864 clear_qp_mutex (qp_changemask);
7865 clear_qp_implies (qp_changemask, qp_changemask);
7866 }
7867}
7868
7869/* Return whether the given predicate registers are currently mutex */
7870static int
7871qp_mutex (p1, p2, path)
7872 int p1;
7873 int p2;
7874 int path;
7875{
7876 int i;
7877 valueT mask;
7878
7879 if (p1 != p2)
7880 {
7881 mask = ((valueT)1<<p1) | (valueT)1<<p2;
7882 for (i=0;i < qp_mutexeslen;i++)
7883 {
7884 if (qp_mutexes[i].path >= path
7885 && (qp_mutexes[i].prmask & mask) == mask)
7886 return 1;
7887 }
7888 }
7889 return 0;
7890}
7891
7892/* Return whether the given resource is in the given insn's list of chks
7893 Return 1 if the conflict is absolutely determined, 2 if it's a potential
7894 conflict.
7895 */
7896static int
7897resources_match (rs, idesc, note, qp_regno, path)
7898 struct rsrc *rs;
7899 struct ia64_opcode *idesc;
7900 int note;
7901 int qp_regno;
7902 int path;
7903{
7904 struct rsrc specs[MAX_SPECS];
7905 int count;
7906
7907 /* If the marked resource's qp_regno and the given qp_regno are mutex,
7908 we don't need to check. One exception is note 11, which indicates that
7909 target predicates are written regardless of PR[qp]. */
7910 if (qp_mutex (rs->qp_regno, qp_regno, path)
7911 && note != 11)
7912 return 0;
7913
7914 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
7915 while (count-- > 0)
7916 {
7917 /* UNAT checking is a bit more specific than other resources */
7918 if (rs->dependency->specifier == IA64_RS_AR_UNAT
7919 && specs[count].mem_offset.hint
7920 && rs->mem_offset.hint)
7921 {
7922 if (rs->mem_offset.base == specs[count].mem_offset.base)
7923 {
7924 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
7925 ((specs[count].mem_offset.offset >> 3) & 0x3F))
7926 return 1;
7927 else
7928 continue;
7929 }
7930 }
7931
7932 /* If either resource is not specific, conservatively assume a conflict
7933 */
7934 if (!specs[count].specific || !rs->specific)
7935 return 2;
7936 else if (specs[count].index == rs->index)
7937 return 1;
7938 }
7939#if 0
7940 if (md.debug_dv)
7941 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
7942#endif
7943
7944 return 0;
7945}
7946
7947/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
7948 insert a stop to create the break. Update all resource dependencies
7949 appropriately. If QP_REGNO is non-zero, only apply the break to resources
7950 which use the same QP_REGNO and have the link_to_qp_branch flag set.
7951 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
7952 instruction.
7953*/
7954
7955static void
7956insn_group_break (insert_stop, qp_regno, save_current)
7957 int insert_stop;
7958 int qp_regno;
7959 int save_current;
7960{
7961 int i;
7962
7963 if (insert_stop && md.num_slots_in_use > 0)
7964 PREV_SLOT.end_of_insn_group = 1;
7965
7966 if (md.debug_dv)
7967 {
7968 fprintf (stderr, " Insn group break%s",
7969 (insert_stop ? " (w/stop)" : ""));
7970 if (qp_regno != 0)
7971 fprintf (stderr, " effective for QP=%d", qp_regno);
7972 fprintf (stderr, "\n");
7973 }
7974
7975 i = 0;
7976 while (i < regdepslen)
7977 {
7978 const struct ia64_dependency *dep = regdeps[i].dependency;
7979
7980 if (qp_regno != 0
7981 && regdeps[i].qp_regno != qp_regno)
7982 {
7983 ++i;
7984 continue;
7985 }
7986
7987 if (save_current
7988 && CURR_SLOT.src_file == regdeps[i].file
7989 && CURR_SLOT.src_line == regdeps[i].line)
7990 {
7991 ++i;
7992 continue;
7993 }
7994
7995 /* clear dependencies which are automatically cleared by a stop, or
7996 those that have reached the appropriate state of insn serialization */
7997 if (dep->semantics == IA64_DVS_IMPLIED
7998 || dep->semantics == IA64_DVS_IMPLIEDF
7999 || regdeps[i].insn_srlz == STATE_SRLZ)
8000 {
8001 print_dependency ("Removing", i);
8002 regdeps[i] = regdeps[--regdepslen];
8003 }
8004 else
8005 {
8006 if (dep->semantics == IA64_DVS_DATA
8007 || dep->semantics == IA64_DVS_INSTR
8008 || dep->semantics == IA64_DVS_SPECIFIC)
8009 {
8010 if (regdeps[i].insn_srlz == STATE_NONE)
8011 regdeps[i].insn_srlz = STATE_STOP;
8012 if (regdeps[i].data_srlz == STATE_NONE)
8013 regdeps[i].data_srlz = STATE_STOP;
8014 }
8015 ++i;
8016 }
8017 }
8018}
8019
8020/* Add the given resource usage spec to the list of active dependencies */
8021static void
8022mark_resource (idesc, dep, spec, depind, path)
8023 struct ia64_opcode *idesc;
8024 const struct ia64_dependency *dep;
8025 struct rsrc *spec;
8026 int depind;
8027 int path;
8028{
8029 if (regdepslen == regdepstotlen)
8030 {
8031 regdepstotlen += 20;
8032 regdeps = (struct rsrc *)
8033 xrealloc ((void *)regdeps,
8034 regdepstotlen * sizeof(struct rsrc));
8035 }
8036
8037 regdeps[regdepslen] = *spec;
8038 regdeps[regdepslen].depind = depind;
8039 regdeps[regdepslen].path = path;
8040 regdeps[regdepslen].file = CURR_SLOT.src_file;
8041 regdeps[regdepslen].line = CURR_SLOT.src_line;
8042
8043 print_dependency ("Adding", regdepslen);
8044
8045 ++regdepslen;
8046}
8047
8048static void
8049print_dependency (action, depind)
8050 const char *action;
8051 int depind;
8052{
8053 if (md.debug_dv)
8054 {
8055 fprintf (stderr, " %s %s '%s'",
8056 action, dv_mode[(regdeps[depind].dependency)->mode],
8057 (regdeps[depind].dependency)->name);
8058 if (regdeps[depind].specific && regdeps[depind].index != 0)
8059 fprintf (stderr, " (%d)", regdeps[depind].index);
8060 if (regdeps[depind].mem_offset.hint)
8061 fprintf (stderr, " 0x%llx+0x%llx",
8062 regdeps[depind].mem_offset.base,
8063 regdeps[depind].mem_offset.offset);
8064 fprintf (stderr, "\n");
8065 }
8066}
8067
8068static void
8069instruction_serialization ()
8070{
8071 int i;
8072 if (md.debug_dv)
8073 fprintf (stderr, " Instruction serialization\n");
8074 for (i=0;i < regdepslen;i++)
8075 if (regdeps[i].insn_srlz == STATE_STOP)
8076 regdeps[i].insn_srlz = STATE_SRLZ;
8077}
8078
8079static void
8080data_serialization ()
8081{
8082 int i = 0;
8083 if (md.debug_dv)
8084 fprintf (stderr, " Data serialization\n");
8085 while (i < regdepslen)
8086 {
8087 if (regdeps[i].data_srlz == STATE_STOP
8088 /* Note: as of 991210, all "other" dependencies are cleared by a
8089 data serialization. This might change with new tables */
8090 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8091 {
8092 print_dependency ("Removing", i);
8093 regdeps[i] = regdeps[--regdepslen];
8094 }
8095 else
8096 ++i;
8097 }
8098}
8099
8100/* Insert stops and serializations as needed to avoid DVs */
8101static void
8102remove_marked_resource (rs)
8103 struct rsrc *rs;
8104{
8105 switch (rs->dependency->semantics)
8106 {
8107 case IA64_DVS_SPECIFIC:
8108 if (md.debug_dv)
8109 fprintf (stderr, "Implementation-specific, assume worst case...\n");
8110 /* ...fall through... */
8111 case IA64_DVS_INSTR:
8112 if (md.debug_dv)
8113 fprintf (stderr, "Inserting instr serialization\n");
8114 if (rs->insn_srlz < STATE_STOP)
8115 insn_group_break (1, 0, 0);
8116 if (rs->insn_srlz < STATE_SRLZ)
8117 {
8118 int oldqp = CURR_SLOT.qp_regno;
8119 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8120 /* Manually jam a srlz.i insn into the stream */
8121 CURR_SLOT.qp_regno = 0;
8122 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8123 instruction_serialization ();
8124 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8125 if (++md.num_slots_in_use >= NUM_SLOTS)
8126 emit_one_bundle ();
8127 CURR_SLOT.qp_regno = oldqp;
8128 CURR_SLOT.idesc = oldidesc;
8129 }
8130 insn_group_break (1, 0, 0);
8131 break;
8132 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
8133 "other" types of DV are eliminated
8134 by a data serialization */
8135 case IA64_DVS_DATA:
8136 if (md.debug_dv)
8137 fprintf (stderr, "Inserting data serialization\n");
8138 if (rs->data_srlz < STATE_STOP)
8139 insn_group_break (1, 0, 0);
8140 {
8141 int oldqp = CURR_SLOT.qp_regno;
8142 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8143 /* Manually jam a srlz.d insn into the stream */
8144 CURR_SLOT.qp_regno = 0;
8145 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8146 data_serialization ();
8147 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8148 if (++md.num_slots_in_use >= NUM_SLOTS)
8149 emit_one_bundle ();
8150 CURR_SLOT.qp_regno = oldqp;
8151 CURR_SLOT.idesc = oldidesc;
8152 }
8153 break;
8154 case IA64_DVS_IMPLIED:
8155 case IA64_DVS_IMPLIEDF:
8156 if (md.debug_dv)
8157 fprintf (stderr, "Inserting stop\n");
8158 insn_group_break (1, 0, 0);
8159 break;
8160 default:
8161 break;
8162 }
8163}
8164
8165/* Check the resources used by the given opcode against the current dependency
8166 list.
8167
8168 The check is run once for each execution path encountered. In this case,
8169 a unique execution path is the sequence of instructions following a code
8170 entry point, e.g. the following has three execution paths, one starting
8171 at L0, one at L1, and one at L2.
8172
8173 L0: nop
8174 L1: add
8175 L2: add
8176 br.ret
8177*/
8178static void
8179check_dependencies (idesc)
8180 struct ia64_opcode *idesc;
8181{
8182 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8183 int path;
8184 int i;
8185
8186 /* Note that the number of marked resources may change within the
8187 loop if in auto mode. */
8188 i = 0;
8189 while (i < regdepslen)
8190 {
8191 struct rsrc *rs = &regdeps[i];
8192 const struct ia64_dependency *dep = rs->dependency;
8193 int chkind;
8194 int note;
8195 int start_over = 0;
8196
8197 if (dep->semantics == IA64_DVS_NONE
8198 || (chkind = depends_on (rs->depind, idesc)) == -1)
8199 {
8200 ++i; continue;
8201 }
8202
8203 note = NOTE(opdeps->chks[chkind]);
8204
8205 /* Check this resource against each execution path seen thus far */
8206 for (path=0;path <= md.path;path++)
8207 {
8208 int matchtype;
8209
8210 /* If the dependency wasn't on the path being checked, ignore it */
8211 if (rs->path < path)
8212 continue;
8213
8214 /* If the QP for this insn implies a QP which has branched, don't
8215 bother checking. Ed. NOTE: I don't think this check is terribly
8216 useful; what's the point of generating code which will only be
8217 reached if its QP is zero?
8218 This code was specifically inserted to handle the following code,
8219 based on notes from Intel's DV checking code, where p1 implies p2.
8220
8221 mov r4 = 2
8222 (p2) br.cond L
8223 (p1) mov r4 = 7
8224
8225 */
8226 if (CURR_SLOT.qp_regno != 0)
8227 {
8228 int skip = 0;
8229 int implies;
8230 for (implies=0;implies < qp_implieslen;implies++)
8231 {
8232 if (qp_implies[implies].path >= path
8233 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8234 && qp_implies[implies].p2_branched)
8235 {
8236 skip = 1;
8237 break;
8238 }
8239 }
8240 if (skip)
8241 continue;
8242 }
8243
8244 if ((matchtype = resources_match (rs, idesc, note,
8245 CURR_SLOT.qp_regno, path)) != 0)
8246 {
8247 char msg[1024];
8248 char pathmsg[256] = "";
8249 char indexmsg[256] = "";
8250 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8251
8252 if (path != 0)
8253 sprintf (pathmsg, " when entry is at label '%s'",
8254 md.entry_labels[path-1]);
8255 if (rs->specific && rs->index != 0)
8256 sprintf (indexmsg, ", specific resource number is %d",
8257 rs->index);
8258 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8259 idesc->name,
8260 (certain ? "violates" : "may violate"),
8261 dv_mode[dep->mode], dep->name,
8262 dv_sem[dep->semantics],
8263 pathmsg, indexmsg);
8264
8265 if (md.explicit_mode)
8266 {
8267 as_warn ("%s", msg);
8268 if (path < md.path)
8269 as_warn (_("Only the first path encountering the conflict "
8270 "is reported"));
8271 as_warn_where (rs->file, rs->line,
8272 _("This is the location of the "
8273 "conflicting usage"));
8274 /* Don't bother checking other paths, to avoid duplicating
8275 the same warning */
8276 break;
8277 }
8278 else
8279 {
8280 if (md.debug_dv)
8281 fprintf(stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
8282
8283 remove_marked_resource (rs);
8284
8285 /* since the set of dependencies has changed, start over */
8286 /* FIXME -- since we're removing dvs as we go, we
8287 probably don't really need to start over... */
8288 start_over = 1;
8289 break;
8290 }
8291 }
8292 }
8293 if (start_over)
8294 i = 0;
8295 else
8296 ++i;
8297 }
8298}
8299
8300/* register new dependencies based on the given opcode */
8301static void
8302mark_resources (idesc)
8303 struct ia64_opcode *idesc;
8304{
8305 int i;
8306 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8307 int add_only_qp_reads = 0;
8308
8309 /* A conditional branch only uses its resources if it is taken; if it is
8310 taken, we stop following that path. The other branch types effectively
8311 *always* write their resources. If it's not taken, register only QP
8312 reads. */
8313 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8314 {
8315 add_only_qp_reads = 1;
8316 }
8317
8318 if (md.debug_dv)
8319 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8320
8321 for (i=0;i < opdeps->nregs;i++)
8322 {
8323 const struct ia64_dependency *dep;
8324 struct rsrc specs[MAX_SPECS];
8325 int note;
8326 int path;
8327 int count;
8328
8329 dep = ia64_find_dependency (opdeps->regs[i]);
8330 note = NOTE(opdeps->regs[i]);
8331
8332 if (add_only_qp_reads
8333 && !(dep->mode == IA64_DV_WAR
8334 && (dep->specifier == IA64_RS_PR
8335 || dep->specifier == IA64_RS_PR63)))
8336 continue;
8337
8338 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8339
8340#if 0
8341 if (md.debug_dv && !count)
8342 fprintf (stderr, " No %s %s usage found (path %d)\n",
8343 dv_mode[dep->mode], dep->name, md.path);
8344#endif
8345
8346 while (count-- > 0)
8347 {
8348 mark_resource (idesc, dep, &specs[count],
8349 DEP(opdeps->regs[i]), md.path);
8350 }
8351
8352 /* The execution path may affect register values, which may in turn
8353 affect which indirect-access resources are accessed. */
8354 switch (dep->specifier)
8355 {
8356 default:
8357 break;
8358 case IA64_RS_CPUID:
8359 case IA64_RS_DBR:
8360 case IA64_RS_IBR:
8361 case IA64_RS_MSR:
8362 case IA64_RS_PKR:
8363 case IA64_RS_PMC:
8364 case IA64_RS_PMD:
8365 case IA64_RS_RR:
8366 for (path=0;path < md.path;path++)
8367 {
8368 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8369 while (count-- > 0)
8370 mark_resource (idesc, dep, &specs[count],
8371 DEP(opdeps->regs[i]), path);
8372 }
8373 break;
8374 }
8375 }
8376}
8377
8378/* remove dependencies when they no longer apply */
8379static void
8380update_dependencies (idesc)
8381 struct ia64_opcode *idesc;
8382{
8383 int i;
8384
8385 if (strcmp (idesc->name, "srlz.i") == 0)
8386 {
8387 instruction_serialization ();
8388 }
8389 else if (strcmp (idesc->name, "srlz.d") == 0)
8390 {
8391 data_serialization ();
8392 }
8393 else if (is_interruption_or_rfi (idesc)
8394 || is_taken_branch (idesc))
8395 {
8396 /* although technically the taken branch doesn't clear dependencies
8397 which require a srlz.[id], we don't follow the branch; the next
8398 instruction is assumed to start with a clean slate */
8399 regdepslen = 0;
800eeca4
JW		 8400 md.path = 0;
8401 }
8402 else if (is_conditional_branch (idesc)
8403 && CURR_SLOT.qp_regno != 0)
8404 {
8405 int is_call = strstr (idesc->name, ".call") != NULL;
8406
8407 for (i=0;i < qp_implieslen;i++)
8408 {
8409 /* if the conditional branch's predicate is implied by the predicate
8410 in an existing dependency, remove that dependency */
8411 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8412 {
8413 int depind = 0;
8414 /* note that this implied predicate takes a branch so that if
8415 a later insn generates a DV but its predicate implies this
8416 one, we can avoid the false DV warning */
8417 qp_implies[i].p2_branched = 1;
8418 while (depind < regdepslen)
8419 {
8420 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8421 {
8422 print_dependency ("Removing", depind);
8423 regdeps[depind] = regdeps[--regdepslen];
8424 }
8425 else
8426 ++depind;
8427 }
8428 }
8429 }
8430 /* Any marked resources which have this same predicate should be
8431 cleared, provided that the QP hasn't been modified between the
8432 marking instruction and the branch.
8433 */
8434 if (is_call)
8435 {
8436 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8437 }
8438 else
8439 {
8440 i = 0;
8441 while (i < regdepslen)
8442 {
8443 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8444 && regdeps[i].link_to_qp_branch
8445 && (regdeps[i].file != CURR_SLOT.src_file
8446 || regdeps[i].line != CURR_SLOT.src_line))
8447 {
8448 /* Treat like a taken branch */
8449 print_dependency ("Removing", i);
8450 regdeps[i] = regdeps[--regdepslen];
8451 }
8452 else
8453 ++i;
8454 }
8455 }
8456 }
8457}
8458
8459/* Examine the current instruction for dependency violations. */
8460static int
8461check_dv (idesc)
8462 struct ia64_opcode *idesc;
8463{
8464 if (md.debug_dv)
8465 {
8466 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
8467 idesc->name, CURR_SLOT.src_line,
8468 idesc->dependencies->nchks,
8469 idesc->dependencies->nregs);
8470 }
8471
8472 /* Look through the list of currently marked resources; if the current
8473 instruction has the dependency in its chks list which uses that resource,
8474 check against the specific resources used.
8475 */
8476 check_dependencies (idesc);
8477
8478 /*
8479 Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8480 then add them to the list of marked resources.
8481 */
8482 mark_resources (idesc);
8483
8484 /* There are several types of dependency semantics, and each has its own
8485 requirements for being cleared
8486
8487 Instruction serialization (insns separated by interruption, rfi, or
8488 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8489
8490 Data serialization (instruction serialization, or writer + srlz.d +
8491 reader, where writer and srlz.d are in separate groups) clears
8492 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8493 always be the case).
8494
8495 Instruction group break (groups separated by stop, taken branch,
8496 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8497 */
8498 update_dependencies (idesc);
8499
8500 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8501 warning. Keep track of as many as possible that are useful. */
8502 note_register_values (idesc);
8503
8504 /* We don't need or want this anymore. */
8505 md.mem_offset.hint = 0;
8506
8507 return 0;
8508}
8509
8510/* Translate one line of assembly. Pseudo ops and labels do not show
8511 here. */
8512void
8513md_assemble (str)
8514 char *str;
8515{
8516 char *saved_input_line_pointer, *mnemonic;
8517 const struct pseudo_opcode *pdesc;
8518 struct ia64_opcode *idesc;
8519 unsigned char qp_regno;
8520 unsigned int flags;
8521 int ch;
8522
8523 saved_input_line_pointer = input_line_pointer;
8524 input_line_pointer = str;
8525
8526 /* extract the opcode (mnemonic): */
8527
8528 mnemonic = input_line_pointer;
8529 ch = get_symbol_end ();
8530 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
8531 if (pdesc)
8532 {
8533 *input_line_pointer = ch;
8534 (*pdesc->handler) (pdesc->arg);
8535 goto done;
8536 }
8537
8538 /* find the instruction descriptor matching the arguments: */
8539
8540 idesc = ia64_find_opcode (mnemonic);
8541 *input_line_pointer = ch;
8542 if (!idesc)
8543 {
8544 as_bad ("Unknown opcode `%s'", mnemonic);
8545 goto done;
8546 }
8547
8548 idesc = parse_operands (idesc);
8549 if (!idesc)
8550 goto done;
8551
8552 /* Handle the dynamic ops we can handle now: */
8553 if (idesc->type == IA64_TYPE_DYN)
8554 {
8555 if (strcmp (idesc->name, "add") == 0)
8556 {
8557 if (CURR_SLOT.opnd[2].X_op == O_register
8558 && CURR_SLOT.opnd[2].X_add_number < 4)
8559 mnemonic = "addl";
8560 else
8561 mnemonic = "adds";
3d56ab85 8562 ia64_free_opcode (idesc);
800eeca4
JW		 8563 idesc = ia64_find_opcode (mnemonic);
8564#if 0
8565 know (!idesc->next);
8566#endif
8567 }
8568 else if (strcmp (idesc->name, "mov") == 0)
8569 {
8570 enum ia64_opnd opnd1, opnd2;
8571 int rop;
8572
8573 opnd1 = idesc->operands[0];
8574 opnd2 = idesc->operands[1];
8575 if (opnd1 == IA64_OPND_AR3)
8576 rop = 0;
8577 else if (opnd2 == IA64_OPND_AR3)
8578 rop = 1;
8579 else
8580 abort ();
8581 if (CURR_SLOT.opnd[rop].X_op == O_register
8582 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
8583 mnemonic = "mov.i";
8584 else
8585 mnemonic = "mov.m";
3d56ab85 8586 ia64_free_opcode (idesc);
800eeca4
JW		 8587 idesc = ia64_find_opcode (mnemonic);
8588 while (idesc != NULL
8589 && (idesc->operands[0] != opnd1
8590 || idesc->operands[1] != opnd2))
8591 idesc = get_next_opcode (idesc);
8592 }
8593 }
8594
8595 qp_regno = 0;
8596 if (md.qp.X_op == O_register)
8597 qp_regno = md.qp.X_add_number - REG_P;
8598
8599 flags = idesc->flags;
8600
8601 if ((flags & IA64_OPCODE_FIRST) != 0)
8602 insn_group_break (1, 0, 0);
8603
8604 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
8605 {
8606 as_bad ("`%s' cannot be predicated", idesc->name);
8607 goto done;
8608 }
8609
8610 /* build the instruction: */
8611 CURR_SLOT.qp_regno = qp_regno;
8612 CURR_SLOT.idesc = idesc;
8613 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
8614 if (debug_type == DEBUG_DWARF2)
8615 dwarf2_where (&CURR_SLOT.debug_line);
8616
8617 /* Add unwind entry, if there is one. */
e0c9811a 8618 if (unwind.current_entry)
800eeca4 8619 {
e0c9811a
JW		 8620 CURR_SLOT.unwind_record = unwind.current_entry;
8621 unwind.current_entry = NULL;
800eeca4
JW		 8622 }
8623
8624 /* check for dependency violations */
8625 if (md.detect_dv)
8626 check_dv(idesc);
8627
8628 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8629 if (++md.num_slots_in_use >= NUM_SLOTS)
8630 emit_one_bundle ();
8631
8632 if ((flags & IA64_OPCODE_LAST) != 0)
8633 insn_group_break (1, 0, 0);
8634
8635 md.last_text_seg = now_seg;
8636
8637 done:
8638 input_line_pointer = saved_input_line_pointer;
8639}
8640
8641/* Called when symbol NAME cannot be found in the symbol table.
8642 Should be used for dynamic valued symbols only. */
8643symbolS*
8644md_undefined_symbol (name)
8645 char *name;
8646{
8647 return 0;
8648}
8649
8650/* Called for any expression that can not be recognized. When the
8651 function is called, `input_line_pointer' will point to the start of
8652 the expression. */
8653void
8654md_operand (e)
8655 expressionS *e;
8656{
8657 enum pseudo_type pseudo_type;
e0c9811a 8658 const char *name;
800eeca4
JW		 8659 size_t len;
8660 int ch, i;
8661
8662 switch (*input_line_pointer)
8663 {
8664 case '@':
8665 /* find what relocation pseudo-function we're dealing with: */
8666 pseudo_type = 0;
8667 ch = *++input_line_pointer;
8668 for (i = 0; i < NELEMS (pseudo_func); ++i)
8669 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
8670 {
8671 len = strlen (pseudo_func[i].name);
8672 if (strncmp (pseudo_func[i].name + 1,
8673 input_line_pointer + 1, len - 1) == 0
8674 && !is_part_of_name (input_line_pointer[len]))
8675 {
8676 input_line_pointer += len;
8677 pseudo_type = pseudo_func[i].type;
8678 break;
8679 }
8680 }
8681 switch (pseudo_type)
8682 {
8683 case PSEUDO_FUNC_RELOC:
8684 SKIP_WHITESPACE ();
8685 if (*input_line_pointer != '(')
8686 {
8687 as_bad ("Expected '('");
8688 goto err;
8689 }
8690 ++input_line_pointer; /* skip '(' */
8691 expression (e);
8692 if (*input_line_pointer++ != ')')
8693 {
8694 as_bad ("Missing ')'");
8695 goto err;
8696 }
8697 if (e->X_op != O_symbol)
8698 {
8699 if (e->X_op != O_pseudo_fixup)
8700 {
8701 as_bad ("Not a symbolic expression");
8702 goto err;
8703 }
8704 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
8705 && i == FUNC_LT_RELATIVE)
8706 i = FUNC_LT_FPTR_RELATIVE;
8707 else
8708 {
8709 as_bad ("Illegal combination of relocation functions");
8710 goto err;
8711 }
8712 }
8713 /* make sure gas doesn't get rid of local symbols that are used
8714 in relocs: */
8715 e->X_op = O_pseudo_fixup;
8716 e->X_op_symbol = pseudo_func[i].u.sym;
8717 break;
8718
8719 case PSEUDO_FUNC_CONST:
8720 e->X_op = O_constant;
8721 e->X_add_number = pseudo_func[i].u.ival;
8722 break;
8723
e0c9811a
JW		 8724 case PSEUDO_FUNC_REG:
8725 e->X_op = O_register;
8726 e->X_add_number = pseudo_func[i].u.ival;
8727 break;
8728
800eeca4 8729 default:
e0c9811a
JW		 8730 name = input_line_pointer - 1;
8731 get_symbol_end ();
8732 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW		 8733 goto err;
8734 }
8735 break;
8736
8737 case '[':
8738 ++input_line_pointer;
8739 expression (e);
8740 if (*input_line_pointer != ']')
8741 {
8742 as_bad ("Closing bracket misssing");
8743 goto err;
8744 }
8745 else
8746 {
8747 if (e->X_op != O_register)
8748 as_bad ("Register expected as index");
8749
8750 ++input_line_pointer;
8751 e->X_op = O_index;
8752 }
8753 break;
8754
8755 default:
8756 break;
8757 }
8758 return;
8759
8760 err:
8761 ignore_rest_of_line ();
8762}
8763
8764/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8765 a section symbol plus some offset. For relocs involving @fptr(),
8766 directives we don't want such adjustments since we need to have the
8767 original symbol's name in the reloc. */
8768int
8769ia64_fix_adjustable (fix)
8770 fixS *fix;
8771{
8772 /* Prevent all adjustments to global symbols */
8773 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
8774 return 0;
8775
8776 switch (fix->fx_r_type)
8777 {
8778 case BFD_RELOC_IA64_FPTR64I:
8779 case BFD_RELOC_IA64_FPTR32MSB:
8780 case BFD_RELOC_IA64_FPTR32LSB:
8781 case BFD_RELOC_IA64_FPTR64MSB:
8782 case BFD_RELOC_IA64_FPTR64LSB:
8783 case BFD_RELOC_IA64_LTOFF_FPTR22:
8784 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8785 return 0;
8786 default:
8787 break;
8788 }
8789
8790 return 1;
8791}
8792
8793int
8794ia64_force_relocation (fix)
8795 fixS *fix;
8796{
8797 switch (fix->fx_r_type)
8798 {
8799 case BFD_RELOC_IA64_FPTR64I:
8800 case BFD_RELOC_IA64_FPTR32MSB:
8801 case BFD_RELOC_IA64_FPTR32LSB:
8802 case BFD_RELOC_IA64_FPTR64MSB:
8803 case BFD_RELOC_IA64_FPTR64LSB:
8804
8805 case BFD_RELOC_IA64_LTOFF22:
8806 case BFD_RELOC_IA64_LTOFF64I:
8807 case BFD_RELOC_IA64_LTOFF_FPTR22:
8808 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8809 case BFD_RELOC_IA64_PLTOFF22:
8810 case BFD_RELOC_IA64_PLTOFF64I:
8811 case BFD_RELOC_IA64_PLTOFF64MSB:
8812 case BFD_RELOC_IA64_PLTOFF64LSB:
8813 return 1;
8814
8815 default:
8816 return 0;
8817 }
8818 return 0;
8819}
8820
8821/* Decide from what point a pc-relative relocation is relative to,
8822 relative to the pc-relative fixup. Er, relatively speaking. */
8823long
8824ia64_pcrel_from_section (fix, sec)
8825 fixS *fix;
8826 segT sec;
8827{
8828 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
8829
8830 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
8831 off &= ~0xfUL;
8832
8833 return off;
8834}
8835
8836/* This is called whenever some data item (not an instruction) needs a
8837 fixup. We pick the right reloc code depending on the byteorder
8838 currently in effect. */
8839void
8840ia64_cons_fix_new (f, where, nbytes, exp)
8841 fragS *f;
8842 int where;
8843 int nbytes;
8844 expressionS *exp;
8845{
8846 bfd_reloc_code_real_type code;
8847 fixS *fix;
8848
8849 switch (nbytes)
8850 {
8851 /* There are no reloc for 8 and 16 bit quantities, but we allow
8852 them here since they will work fine as long as the expression
8853 is fully defined at the end of the pass over the source file. */
8854 case 1: code = BFD_RELOC_8; break;
8855 case 2: code = BFD_RELOC_16; break;
8856 case 4:
8857 if (target_big_endian)
8858 code = BFD_RELOC_IA64_DIR32MSB;
8859 else
8860 code = BFD_RELOC_IA64_DIR32LSB;
8861 break;
8862
8863 case 8:
8864 if (target_big_endian)
8865 code = BFD_RELOC_IA64_DIR64MSB;
8866 else
8867 code = BFD_RELOC_IA64_DIR64LSB;
8868 break;
8869
8870 default:
8871 as_bad ("Unsupported fixup size %d", nbytes);
8872 ignore_rest_of_line ();
8873 return;
8874 }
8875 if (exp->X_op == O_pseudo_fixup)
8876 {
8877 /* ??? */
8878 exp->X_op = O_symbol;
8879 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
8880 }
8881 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
8882 /* We need to store the byte order in effect in case we're going
8883 to fix an 8 or 16 bit relocation (for which there no real
8884 relocs available). See md_apply_fix(). */
8885 fix->tc_fix_data.bigendian = target_big_endian;
8886}
8887
8888/* Return the actual relocation we wish to associate with the pseudo
8889 reloc described by SYM and R_TYPE. SYM should be one of the
8890 symbols in the pseudo_func array, or NULL. */
8891
8892static bfd_reloc_code_real_type
8893ia64_gen_real_reloc_type (sym, r_type)
8894 struct symbol *sym;
8895 bfd_reloc_code_real_type r_type;
8896{
8897 bfd_reloc_code_real_type new = 0;
8898
8899 if (sym == NULL)
8900 {
8901 return r_type;
8902 }
8903
8904 switch (S_GET_VALUE (sym))
8905 {
8906 case FUNC_FPTR_RELATIVE:
8907 switch (r_type)
8908 {
8909 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
8910 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
8911 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
8912 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
8913 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
8914 default: break;
8915 }
8916 break;
8917
8918 case FUNC_GP_RELATIVE:
8919 switch (r_type)
8920 {
8921 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
8922 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
8923 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
8924 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
8925 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
8926 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
8927 default: break;
8928 }
8929 break;
8930
8931 case FUNC_LT_RELATIVE:
8932 switch (r_type)
8933 {
8934 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
8935 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
8936 default: break;
8937 }
8938 break;
8939
c67e42c9
RH		 8940 case FUNC_PC_RELATIVE:
8941 switch (r_type)
8942 {
8943 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
8944 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
8945 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
8946 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
8947 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
8948 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
8949 default: break;
8950 }
8951 break;
8952
800eeca4
JW		 8953 case FUNC_PLT_RELATIVE:
8954 switch (r_type)
8955 {
8956 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
8957 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
8958 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
8959 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
8960 default: break;
8961 }
8962 break;
8963
8964 case FUNC_SEC_RELATIVE:
8965 switch (r_type)
8966 {
8967 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
8968 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
8969 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
8970 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
8971 default: break;
8972 }
8973 break;
8974
8975 case FUNC_SEG_RELATIVE:
8976 switch (r_type)
8977 {
8978 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
8979 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
8980 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
8981 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
8982 default: break;
8983 }
8984 break;
8985
8986 case FUNC_LTV_RELATIVE:
8987 switch (r_type)
8988 {
8989 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
8990 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
8991 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
8992 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
8993 default: break;
8994 }
8995 break;
8996
8997 case FUNC_LT_FPTR_RELATIVE:
8998 switch (r_type)
8999 {
9000 case BFD_RELOC_IA64_IMM22:
9001 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9002 case BFD_RELOC_IA64_IMM64:
9003 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9004 default:
9005 break;
9006 }
9007 break;
9008 default:
9009 abort ();
9010 }
9011 /* Hmmmm. Should this ever occur? */
9012 if (new)
9013 return new;
9014 else
9015 return r_type;
9016}
9017
9018/* Here is where generate the appropriate reloc for pseudo relocation
9019 functions. */
9020void
9021ia64_validate_fix (fix)
9022 fixS *fix;
9023{
9024 switch (fix->fx_r_type)
9025 {
9026 case BFD_RELOC_IA64_FPTR64I:
9027 case BFD_RELOC_IA64_FPTR32MSB:
9028 case BFD_RELOC_IA64_FPTR64LSB:
9029 case BFD_RELOC_IA64_LTOFF_FPTR22:
9030 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9031 if (fix->fx_offset != 0)
9032 as_bad_where (fix->fx_file, fix->fx_line,
9033 "No addend allowed in @fptr() relocation");
9034 break;
9035 default:
9036 break;
9037 }
9038
9039 return;
9040}
9041
9042static void
9043fix_insn (fix, odesc, value)
9044 fixS *fix;
9045 const struct ia64_operand *odesc;
9046 valueT value;
9047{
9048 bfd_vma insn[3], t0, t1, control_bits;
9049 const char *err;
9050 char *fixpos;
9051 long slot;
9052
9053 slot = fix->fx_where & 0x3;
9054 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9055
c67e42c9 9056 /* Bundles are always in little-endian byte order */
800eeca4
JW		 9057 t0 = bfd_getl64 (fixpos);
9058 t1 = bfd_getl64 (fixpos + 8);
9059 control_bits = t0 & 0x1f;
9060 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9061 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9062 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9063
c67e42c9
RH		 9064 err = NULL;
9065 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 9066 {
c67e42c9
RH		 9067 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9068 insn[2] |= (((value & 0x7f) << 13)
9069 | (((value >> 7) & 0x1ff) << 27)
9070 | (((value >> 16) & 0x1f) << 22)
9071 | (((value >> 21) & 0x1) << 21)
9072 | (((value >> 63) & 0x1) << 36));
800eeca4 9073 }
c67e42c9
RH		 9074 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9075 {
9076 if (value & ~0x3fffffffffffffffULL)
9077 err = "integer operand out of range";
9078 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9079 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9080 }
9081 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9082 {
9083 value >>= 4;
9084 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9085 insn[2] |= ((((value >> 59) & 0x1) << 36)
9086 | (((value >> 0) & 0xfffff) << 13));
9087 }
9088 else
9089 err = (*odesc->insert) (odesc, value, insn + slot);
9090
9091 if (err)
9092 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW		 9093
9094 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9095 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9096 md_number_to_chars (fixpos + 0, t0, 8);
9097 md_number_to_chars (fixpos + 8, t1, 8);
800eeca4
JW		 9098}
9099
9100/* Attempt to simplify or even eliminate a fixup. The return value is
9101 ignored; perhaps it was once meaningful, but now it is historical.
9102 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9103
9104 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9105 (if possible). */
9106int
9107md_apply_fix3 (fix, valuep, seg)
9108 fixS *fix;
9109 valueT *valuep;
9110 segT seg;
9111{
9112 char *fixpos;
9113 valueT value = *valuep;
9114 int adjust = 0;
9115
9116 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9117
9118 if (fix->fx_pcrel)
9119 {
9120 switch (fix->fx_r_type)
9121 {
9122 case BFD_RELOC_IA64_DIR32MSB:
9123 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9124 adjust = 1;
9125 break;
9126
9127 case BFD_RELOC_IA64_DIR32LSB:
9128 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9129 adjust = 1;
9130 break;
9131
9132 case BFD_RELOC_IA64_DIR64MSB:
9133 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9134 adjust = 1;
9135 break;
9136
9137 case BFD_RELOC_IA64_DIR64LSB:
9138 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9139 adjust = 1;
9140 break;
9141
9142 default:
9143 break;
9144 }
9145 }
9146 if (fix->fx_addsy)
9147 {
9148 switch (fix->fx_r_type)
9149 {
9150 case 0:
9151 as_bad_where (fix->fx_file, fix->fx_line,
9152 "%s must have a constant value",
9153 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9154 break;
9155
9156 default:
9157 break;
9158 }
9159
9160 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9161 work. There should be a better way to handle this. */
9162 if (adjust)
9163 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9164 }
9165 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9166 {
9167 if (fix->tc_fix_data.bigendian)
9168 number_to_chars_bigendian (fixpos, value, fix->fx_size);
9169 else
9170 number_to_chars_littleendian (fixpos, value, fix->fx_size);
9171 fix->fx_done = 1;
9172 return 1;
9173 }
9174 else
9175 {
9176 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
9177 fix->fx_done = 1;
9178 return 1;
9179 }
9180 return 1;
9181}
9182
9183/* Generate the BFD reloc to be stuck in the object file from the
9184 fixup used internally in the assembler. */
9185arelent*
9186tc_gen_reloc (sec, fixp)
9187 asection *sec;
9188 fixS *fixp;
9189{
9190 arelent *reloc;
9191
9192 reloc = xmalloc (sizeof (*reloc));
9193 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9194 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9195 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9196 reloc->addend = fixp->fx_offset;
9197 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9198
9199 if (!reloc->howto)
9200 {
9201 as_bad_where (fixp->fx_file, fixp->fx_line,
9202 "Cannot represent %s relocation in object file",
9203 bfd_get_reloc_code_name (fixp->fx_r_type));
9204 }
9205 return reloc;
9206}
9207
9208/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 9209 of type TYPE, and store the appropriate bytes in *LIT. The number
9210 of LITTLENUMS emitted is stored in *SIZE. An error message is
800eeca4
JW		 9211 returned, or NULL on OK. */
9212
9213#define MAX_LITTLENUMS 5
9214
9215char*
9216md_atof (type, lit, size)
9217 int type;
9218 char *lit;
9219 int *size;
9220{
9221 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9222 LITTLENUM_TYPE *word;
9223 char *t;
9224 int prec;
9225
9226 switch (type)
9227 {
9228 /* IEEE floats */
9229 case 'f':
9230 case 'F':
9231 case 's':
9232 case 'S':
9233 prec = 2;
9234 break;
9235
9236 case 'd':
9237 case 'D':
9238 case 'r':
9239 case 'R':
9240 prec = 4;
9241 break;
9242
9243 case 'x':
9244 case 'X':
9245 case 'p':
9246 case 'P':
9247 prec = 5;
9248 break;
9249
9250 default:
9251 *size = 0;
9252 return "Bad call to MD_ATOF()";
9253 }
9254 t = atof_ieee (input_line_pointer, type, words);
9255 if (t)
9256 input_line_pointer = t;
9257 *size = prec * sizeof (LITTLENUM_TYPE);
9258
9259 for (word = words + prec - 1; prec--;)
9260 {
9261 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9262 lit += sizeof (LITTLENUM_TYPE);
9263 }
9264 return 0;
9265}
9266
9267/* Round up a section's size to the appropriate boundary. */
9268valueT
9269md_section_align (seg, size)
9270 segT seg;
9271 valueT size;
9272{
9273 int align = bfd_get_section_alignment (stdoutput, seg);
9274 valueT mask = ((valueT)1 << align) - 1;
9275
9276 return (size + mask) & ~mask;
9277}
9278
9279/* Handle ia64 specific semantics of the align directive. */
9280
9281int
9282ia64_md_do_align (n, fill, len, max)
9283 int n;
9284 const char *fill;
9285 int len;
9286 int max;
9287{
9288 /* Fill any pending bundle with nops. */
9289 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
9290 ia64_flush_insns ();
9291
9292 /* When we align code in a text section, emit a bundle of 3 nops instead of
9293 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9294 N is log base 2 of the requested alignment. */
9295 if (fill == NULL
9296 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
9297 && n > 4)
9298 {
9299 /* Use mfi bundle of nops with no stop bits. */
9300 static const unsigned char be_nop[]
9301 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9302 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9303 static const unsigned char le_nop[]
9304 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9305 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9306
9307 /* Make sure we are on a 16-byte boundary, in case someone has been
9308 putting data into a text section. */
9309 frag_align (4, 0, 0);
9310
9311 if (target_big_endian)
9312 frag_align_pattern (n, be_nop, 16, max);
9313 else
9314 frag_align_pattern (n, le_nop, 16, max);
9315 return 1;
9316 }
9317
9318 return 0;
9319}
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