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Add support for backtracing through signal handlers on Linux/ARM. Also,
[thirdparty/binutils-gdb.git] / gas / config / tc-ia64.c
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800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
e0c9811a 2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
800eeca4
JW		 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
800eeca4
JW		 35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
197865e8 41 notes)
800eeca4
JW		 42
43 */
44
45#include "as.h"
46#include "dwarf2dbg.h"
47#include "subsegs.h"
48
49#include "opcode/ia64.h"
50
51#include "elf/ia64.h"
52
53#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54#define MIN(a,b) ((a) < (b) ? (a) : (b))
55
56#define NUM_SLOTS 4
57#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58#define CURR_SLOT md.slot[md.curr_slot]
59
60#define O_pseudo_fixup (O_max + 1)
61
62enum special_section
63 {
64 SPECIAL_SECTION_BSS = 0,
65 SPECIAL_SECTION_SBSS,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
71 };
72
73enum reloc_func
74 {
75 FUNC_FPTR_RELATIVE,
76 FUNC_GP_RELATIVE,
77 FUNC_LT_RELATIVE,
c67e42c9 78 FUNC_PC_RELATIVE,
800eeca4
JW		 79 FUNC_PLT_RELATIVE,
80 FUNC_SEC_RELATIVE,
81 FUNC_SEG_RELATIVE,
82 FUNC_LTV_RELATIVE,
83 FUNC_LT_FPTR_RELATIVE,
84 };
85
86enum reg_symbol
87 {
88 REG_GR = 0,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
95 REG_CFM,
96 REG_PR,
97 REG_PR_ROT,
98 REG_PSR,
99 REG_PSR_L,
100 REG_PSR_UM,
101 /* The following are pseudo-registers for use by gas only. */
102 IND_CPUID,
103 IND_DBR,
104 IND_DTR,
105 IND_ITR,
106 IND_IBR,
107 IND_MEM,
108 IND_MSR,
109 IND_PKR,
110 IND_PMC,
111 IND_PMD,
112 IND_RR,
e0c9811a
JW		 113 /* The following pseudo-registers are used for unwind directives only: */
114 REG_PSP,
115 REG_PRIUNAT,
800eeca4
JW		 116 REG_NUM
117 };
118
119enum dynreg_type
120 {
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
124 DYNREG_NUM_TYPES
125 };
126
127/* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
130 instruction. */
131struct label_fix
132 {
133 struct label_fix *next;
134 struct symbol *sym;
135 };
136
137extern int target_big_endian;
138
139/* Characters which always start a comment. */
140const char comment_chars[] = "";
141
142/* Characters which start a comment at the beginning of a line. */
143const char line_comment_chars[] = "#";
144
145/* Characters which may be used to separate multiple commands on a
146 single line. */
147const char line_separator_chars[] = ";";
148
149/* Characters which are used to indicate an exponent in a floating
150 point number. */
151const char EXP_CHARS[] = "eE";
152
153/* Characters which mean that a number is a floating point constant,
154 as in 0d1.0. */
155const char FLT_CHARS[] = "rRsSfFdDxXpP";
156
157/* ia64-specific option processing: */
158
159const char *md_shortopts = "M:N:x::";
160
161struct option md_longopts[] =
162 {
c43c2cc5
JW		 163#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
165#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
800eeca4
JW		 167 };
168
169size_t md_longopts_size = sizeof (md_longopts);
170
171static struct
172 {
173 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
174 struct hash_control *reg_hash; /* register name hash table */
175 struct hash_control *dynreg_hash; /* dynamic register hash table */
176 struct hash_control *const_hash; /* constant hash table */
177 struct hash_control *entry_hash; /* code entry hint hash table */
178
179 symbolS *regsym[REG_NUM];
180
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
184 expressionS qp;
185
186 unsigned int
197865e8 187 manual_bundling : 1,
800eeca4
JW		 188 debug_dv: 1,
189 detect_dv: 1,
190 explicit_mode : 1, /* which mode we're in */
191 default_explicit_mode : 1, /* which mode is the default */
192 mode_explicitly_set : 1, /* was the current mode explicitly set? */
193 auto_align : 1;
194
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197865e8 197 the end_of_insn_group for the last instruction in a bundle. */
800eeca4
JW		 198 int curr_slot;
199 int num_slots_in_use;
200 struct slot
201 {
202 unsigned int
203 end_of_insn_group : 1,
204 manual_bundling_on : 1,
205 manual_bundling_off : 1;
206 signed char user_template; /* user-selected template, if any */
207 unsigned char qp_regno; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
211 int num_fixups;
212 struct insn_fix
213 {
214 bfd_reloc_code_real_type code;
215 enum ia64_opnd opnd; /* type of operand in need of fix */
216 unsigned int is_pcrel : 1; /* is operand pc-relative? */
217 expressionS expr; /* the value to be inserted */
218 }
219 fixup[2]; /* at most two fixups per insn */
220 struct ia64_opcode *idesc;
221 struct label_fix *label_fixups;
222 struct unw_rec_list *unwind_record; /* Unwind directive. */
223 expressionS opnd[6];
224 char *src_file;
225 unsigned int src_line;
226 struct dwarf2_line_info debug_line;
227 }
228 slot[NUM_SLOTS];
229
230 segT last_text_seg;
231
232 struct dynreg
233 {
234 struct dynreg *next; /* next dynamic register */
235 const char *name;
236 unsigned short base; /* the base register number */
237 unsigned short num_regs; /* # of registers in this set */
238 }
239 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
240
241 flagword flags; /* ELF-header flags */
242
243 struct mem_offset {
244 unsigned hint:1; /* is this hint currently valid? */
245 bfd_vma offset; /* mem.offset offset */
246 bfd_vma base; /* mem.offset base */
247 } mem_offset;
248
249 int path; /* number of alt. entry points seen */
250 const char **entry_labels; /* labels of all alternate paths in
197865e8 251 the current DV-checking block. */
800eeca4
JW		 252 int maxpaths; /* size currently allocated for
253 entry_labels */
254 }
255md;
256
257/* application registers: */
258
e0c9811a
JW		 259#define AR_K0 0
260#define AR_K7 7
261#define AR_RSC 16
262#define AR_BSP 17
263#define AR_BSPSTORE 18
264#define AR_RNAT 19
265#define AR_UNAT 36
266#define AR_FPSR 40
267#define AR_ITC 44
268#define AR_PFS 64
269#define AR_LC 65
800eeca4
JW		 270
271static const struct
272 {
273 const char *name;
274 int regnum;
275 }
276ar[] =
277 {
278 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
279 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
280 {"ar.rsc", 16}, {"ar.bsp", 17},
281 {"ar.bspstore", 18}, {"ar.rnat", 19},
282 {"ar.fcr", 21}, {"ar.eflag", 24},
283 {"ar.csd", 25}, {"ar.ssd", 26},
284 {"ar.cflg", 27}, {"ar.fsr", 28},
285 {"ar.fir", 29}, {"ar.fdr", 30},
286 {"ar.ccv", 32}, {"ar.unat", 36},
287 {"ar.fpsr", 40}, {"ar.itc", 44},
288 {"ar.pfs", 64}, {"ar.lc", 65},
197865e8 289 {"ar.ec", 66},
800eeca4
JW		 290 };
291
292#define CR_IPSR 16
293#define CR_ISR 17
294#define CR_IIP 19
295#define CR_IFA 20
296#define CR_ITIR 21
297#define CR_IIPA 22
298#define CR_IFS 23
299#define CR_IIM 24
300#define CR_IHA 25
301#define CR_IVR 65
302#define CR_TPR 66
303#define CR_EOI 67
304#define CR_IRR0 68
305#define CR_IRR3 71
306#define CR_LRR0 80
307#define CR_LRR1 81
308
309/* control registers: */
310static const struct
311 {
312 const char *name;
313 int regnum;
314 }
315cr[] =
316 {
317 {"cr.dcr", 0},
318 {"cr.itm", 1},
319 {"cr.iva", 2},
320 {"cr.pta", 8},
321 {"cr.gpta", 9},
322 {"cr.ipsr", 16},
323 {"cr.isr", 17},
324 {"cr.iip", 19},
325 {"cr.ifa", 20},
326 {"cr.itir", 21},
327 {"cr.iipa", 22},
328 {"cr.ifs", 23},
329 {"cr.iim", 24},
330 {"cr.iha", 25},
331 {"cr.lid", 64},
332 {"cr.ivr", 65},
333 {"cr.tpr", 66},
334 {"cr.eoi", 67},
335 {"cr.irr0", 68},
336 {"cr.irr1", 69},
337 {"cr.irr2", 70},
338 {"cr.irr3", 71},
339 {"cr.itv", 72},
340 {"cr.pmv", 73},
341 {"cr.cmcv", 74},
342 {"cr.lrr0", 80},
343 {"cr.lrr1", 81}
344 };
345
346#define PSR_MFL 4
347#define PSR_IC 13
348#define PSR_DFL 18
349#define PSR_CPL 32
350
351static const struct const_desc
352 {
353 const char *name;
354 valueT value;
355 }
356const_bits[] =
357 {
358 /* PSR constant masks: */
359
360 /* 0: reserved */
361 {"psr.be", ((valueT) 1) << 1},
362 {"psr.up", ((valueT) 1) << 2},
363 {"psr.ac", ((valueT) 1) << 3},
364 {"psr.mfl", ((valueT) 1) << 4},
365 {"psr.mfh", ((valueT) 1) << 5},
366 /* 6-12: reserved */
367 {"psr.ic", ((valueT) 1) << 13},
368 {"psr.i", ((valueT) 1) << 14},
369 {"psr.pk", ((valueT) 1) << 15},
370 /* 16: reserved */
371 {"psr.dt", ((valueT) 1) << 17},
372 {"psr.dfl", ((valueT) 1) << 18},
373 {"psr.dfh", ((valueT) 1) << 19},
374 {"psr.sp", ((valueT) 1) << 20},
375 {"psr.pp", ((valueT) 1) << 21},
376 {"psr.di", ((valueT) 1) << 22},
377 {"psr.si", ((valueT) 1) << 23},
378 {"psr.db", ((valueT) 1) << 24},
379 {"psr.lp", ((valueT) 1) << 25},
380 {"psr.tb", ((valueT) 1) << 26},
381 {"psr.rt", ((valueT) 1) << 27},
382 /* 28-31: reserved */
383 /* 32-33: cpl (current privilege level) */
384 {"psr.is", ((valueT) 1) << 34},
385 {"psr.mc", ((valueT) 1) << 35},
386 {"psr.it", ((valueT) 1) << 36},
387 {"psr.id", ((valueT) 1) << 37},
388 {"psr.da", ((valueT) 1) << 38},
389 {"psr.dd", ((valueT) 1) << 39},
390 {"psr.ss", ((valueT) 1) << 40},
391 /* 41-42: ri (restart instruction) */
392 {"psr.ed", ((valueT) 1) << 43},
393 {"psr.bn", ((valueT) 1) << 44},
394 };
395
396/* indirect register-sets/memory: */
397
398static const struct
399 {
400 const char *name;
401 int regnum;
402 }
403indirect_reg[] =
404 {
405 { "CPUID", IND_CPUID },
406 { "cpuid", IND_CPUID },
407 { "dbr", IND_DBR },
408 { "dtr", IND_DTR },
409 { "itr", IND_ITR },
410 { "ibr", IND_IBR },
411 { "msr", IND_MSR },
412 { "pkr", IND_PKR },
413 { "pmc", IND_PMC },
414 { "pmd", IND_PMD },
415 { "rr", IND_RR },
416 };
417
418/* Pseudo functions used to indicate relocation types (these functions
419 start with an at sign (@). */
420static struct
421 {
422 const char *name;
423 enum pseudo_type
424 {
425 PSEUDO_FUNC_NONE,
426 PSEUDO_FUNC_RELOC,
427 PSEUDO_FUNC_CONST,
e0c9811a 428 PSEUDO_FUNC_REG,
800eeca4
JW		 429 PSEUDO_FUNC_FLOAT
430 }
431 type;
432 union
433 {
434 unsigned long ival;
435 symbolS *sym;
436 }
437 u;
438 }
439pseudo_func[] =
440 {
441 /* reloc pseudo functions (these must come first!): */
442 { "fptr", PSEUDO_FUNC_RELOC },
443 { "gprel", PSEUDO_FUNC_RELOC },
444 { "ltoff", PSEUDO_FUNC_RELOC },
c67e42c9 445 { "pcrel", PSEUDO_FUNC_RELOC },
800eeca4
JW		 446 { "pltoff", PSEUDO_FUNC_RELOC },
447 { "secrel", PSEUDO_FUNC_RELOC },
448 { "segrel", PSEUDO_FUNC_RELOC },
449 { "ltv", PSEUDO_FUNC_RELOC },
450 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
451
452 /* mbtype4 constants: */
453 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
454 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
455 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
456 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
457 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
458
459 /* fclass constants: */
bf3ca999 460 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
800eeca4
JW		 461 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
462 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
463 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
464 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
465 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
466 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
467 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
468 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
TW		 469
470 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a
JW		 471
472 /* unwind-related constants: */
473 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
474 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
475 { "nt", PSEUDO_FUNC_CONST, { 2 } },
476
477 /* unwind-related registers: */
478 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
800eeca4
JW		 479 };
480
481/* 41-bit nop opcodes (one per unit): */
482static const bfd_vma nop[IA64_NUM_UNITS] =
483 {
484 0x0000000000LL, /* NIL => break 0 */
485 0x0008000000LL, /* I-unit nop */
486 0x0008000000LL, /* M-unit nop */
487 0x4000000000LL, /* B-unit nop */
488 0x0008000000LL, /* F-unit nop */
489 0x0008000000LL, /* L-"unit" nop */
490 0x0008000000LL, /* X-unit nop */
491 };
492
493/* Can't be `const' as it's passed to input routines (which have the
494 habit of setting temporary sentinels. */
495static char special_section_name[][20] =
496 {
497 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
498 {".IA_64.unwind"}, {".IA_64.unwind_info"}
499 };
500
501/* The best template for a particular sequence of up to three
502 instructions: */
503#define N IA64_NUM_TYPES
504static unsigned char best_template[N][N][N];
505#undef N
506
507/* Resource dependencies currently in effect */
508static struct rsrc {
509 int depind; /* dependency index */
510 const struct ia64_dependency *dependency; /* actual dependency */
511 unsigned specific:1, /* is this a specific bit/regno? */
512 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
513 int index; /* specific regno/bit within dependency */
514 int note; /* optional qualifying note (0 if none) */
515#define STATE_NONE 0
516#define STATE_STOP 1
517#define STATE_SRLZ 2
518 int insn_srlz; /* current insn serialization state */
519 int data_srlz; /* current data serialization state */
520 int qp_regno; /* qualifying predicate for this usage */
521 char *file; /* what file marked this dependency */
522 int line; /* what line marked this dependency */
523 struct mem_offset mem_offset; /* optional memory offset hint */
524 int path; /* corresponding code entry index */
525} *regdeps = NULL;
526static int regdepslen = 0;
527static int regdepstotlen = 0;
528static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
529static const char *dv_sem[] = { "none", "implied", "impliedf",
530 "data", "instr", "specific", "other" };
531
532/* Current state of PR mutexation */
533static struct qpmutex {
534 valueT prmask;
535 int path;
536} *qp_mutexes = NULL; /* QP mutex bitmasks */
537static int qp_mutexeslen = 0;
538static int qp_mutexestotlen = 0;
197865e8 539static valueT qp_safe_across_calls = 0;
800eeca4
JW		 540
541/* Current state of PR implications */
542static struct qp_imply {
543 unsigned p1:6;
544 unsigned p2:6;
545 unsigned p2_branched:1;
546 int path;
547} *qp_implies = NULL;
548static int qp_implieslen = 0;
549static int qp_impliestotlen = 0;
550
197865e8
KH		 551/* Keep track of static GR values so that indirect register usage can
552 sometimes be tracked. */
800eeca4
JW		 553static struct gr {
554 unsigned known:1;
555 int path;
556 valueT value;
557} gr_values[128] = {{ 1, 0 }};
558
559/* These are the routines required to output the various types of
560 unwind records. */
561
562typedef struct unw_rec_list {
563 unwind_record r;
e0c9811a 564 unsigned long slot_number;
800eeca4
JW		 565 struct unw_rec_list *next;
566} unw_rec_list;
567
568#define SLOT_NUM_NOT_SET -1
569
e0c9811a
JW		 570static struct
571{
572 unsigned long next_slot_number;
573
574 /* Maintain a list of unwind entries for the current function. */
575 unw_rec_list *list;
576 unw_rec_list *tail;
800eeca4 577
e0c9811a
JW		 578 /* Any unwind entires that should be attached to the current slot
579 that an insn is being constructed for. */
580 unw_rec_list *current_entry;
800eeca4 581
e0c9811a
JW		 582 /* These are used to create the unwind table entry for this function. */
583 symbolS *proc_start;
584 symbolS *proc_end;
585 symbolS *info; /* pointer to unwind info */
586 symbolS *personality_routine;
800eeca4 587
e0c9811a
JW		 588 /* TRUE if processing unwind directives in a prologue region. */
589 int prologue;
30d25259 590 int prologue_mask;
e0c9811a 591} unwind;
800eeca4
JW		 592
593typedef void (*vbyte_func) PARAMS ((int, char *, char *));
594
595/* Forward delarations: */
596static int ar_is_in_integer_unit PARAMS ((int regnum));
597static void set_section PARAMS ((char *name));
598static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
599 unsigned int, unsigned int));
600static void dot_radix PARAMS ((int));
601static void dot_special_section PARAMS ((int));
602static void dot_proc PARAMS ((int));
603static void dot_fframe PARAMS ((int));
604static void dot_vframe PARAMS ((int));
150f24a2
JW		 605static void dot_vframesp PARAMS ((int));
606static void dot_vframepsp PARAMS ((int));
800eeca4
JW		 607static void dot_save PARAMS ((int));
608static void dot_restore PARAMS ((int));
150f24a2
JW		 609static void dot_restorereg PARAMS ((int));
610static void dot_restorereg_p PARAMS ((int));
800eeca4
JW		 611static void dot_handlerdata PARAMS ((int));
612static void dot_unwentry PARAMS ((int));
613static void dot_altrp PARAMS ((int));
e0c9811a 614static void dot_savemem PARAMS ((int));
800eeca4
JW		 615static void dot_saveg PARAMS ((int));
616static void dot_savef PARAMS ((int));
617static void dot_saveb PARAMS ((int));
618static void dot_savegf PARAMS ((int));
619static void dot_spill PARAMS ((int));
150f24a2
JW		 620static void dot_spillreg PARAMS ((int));
621static void dot_spillmem PARAMS ((int));
622static void dot_spillreg_p PARAMS ((int));
623static void dot_spillmem_p PARAMS ((int));
624static void dot_label_state PARAMS ((int));
625static void dot_copy_state PARAMS ((int));
800eeca4
JW		 626static void dot_unwabi PARAMS ((int));
627static void dot_personality PARAMS ((int));
628static void dot_body PARAMS ((int));
629static void dot_prologue PARAMS ((int));
630static void dot_endp PARAMS ((int));
631static void dot_template PARAMS ((int));
632static void dot_regstk PARAMS ((int));
633static void dot_rot PARAMS ((int));
634static void dot_byteorder PARAMS ((int));
635static void dot_psr PARAMS ((int));
636static void dot_alias PARAMS ((int));
637static void dot_ln PARAMS ((int));
638static char *parse_section_name PARAMS ((void));
639static void dot_xdata PARAMS ((int));
640static void stmt_float_cons PARAMS ((int));
641static void stmt_cons_ua PARAMS ((int));
642static void dot_xfloat_cons PARAMS ((int));
643static void dot_xstringer PARAMS ((int));
644static void dot_xdata_ua PARAMS ((int));
645static void dot_xfloat_cons_ua PARAMS ((int));
150f24a2 646static void print_prmask PARAMS ((valueT mask));
800eeca4
JW		 647static void dot_pred_rel PARAMS ((int));
648static void dot_reg_val PARAMS ((int));
649static void dot_dv_mode PARAMS ((int));
650static void dot_entry PARAMS ((int));
651static void dot_mem_offset PARAMS ((int));
e0c9811a 652static void add_unwind_entry PARAMS((unw_rec_list *ptr));
800eeca4
JW		 653static symbolS* declare_register PARAMS ((const char *name, int regnum));
654static void declare_register_set PARAMS ((const char *, int, int));
655static unsigned int operand_width PARAMS ((enum ia64_opnd));
656static int operand_match PARAMS ((const struct ia64_opcode *idesc,
657 int index, expressionS *e));
658static int parse_operand PARAMS ((expressionS *e));
659static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
660static void build_insn PARAMS ((struct slot *, bfd_vma *));
661static void emit_one_bundle PARAMS ((void));
662static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
197865e8 663static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
800eeca4
JW		 664 bfd_reloc_code_real_type r_type));
665static void insn_group_break PARAMS ((int, int, int));
150f24a2
JW		 666static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
667 struct rsrc *, int depind, int path));
800eeca4
JW		 668static void add_qp_mutex PARAMS((valueT mask));
669static void add_qp_imply PARAMS((int p1, int p2));
670static void clear_qp_branch_flag PARAMS((valueT mask));
671static void clear_qp_mutex PARAMS((valueT mask));
672static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
673static void clear_register_values PARAMS ((void));
674static void print_dependency PARAMS ((const char *action, int depind));
150f24a2
JW		 675static void instruction_serialization PARAMS ((void));
676static void data_serialization PARAMS ((void));
677static void remove_marked_resource PARAMS ((struct rsrc *));
800eeca4 678static int is_conditional_branch PARAMS ((struct ia64_opcode *));
150f24a2 679static int is_taken_branch PARAMS ((struct ia64_opcode *));
800eeca4 680static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
150f24a2
JW		 681static int depends_on PARAMS ((int, struct ia64_opcode *));
682static int specify_resource PARAMS ((const struct ia64_dependency *,
683 struct ia64_opcode *, int, struct rsrc [], int, int));
800eeca4
JW		 684static int check_dv PARAMS((struct ia64_opcode *idesc));
685static void check_dependencies PARAMS((struct ia64_opcode *));
686static void mark_resources PARAMS((struct ia64_opcode *));
687static void update_dependencies PARAMS((struct ia64_opcode *));
688static void note_register_values PARAMS((struct ia64_opcode *));
150f24a2
JW		 689static int qp_mutex PARAMS ((int, int, int));
690static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
691static void output_vbyte_mem PARAMS ((int, char *, char *));
692static void count_output PARAMS ((int, char *, char *));
693static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
694static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
800eeca4 695static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 696static void output_P1_format PARAMS ((vbyte_func, int));
697static void output_P2_format PARAMS ((vbyte_func, int, int));
698static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
699static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
700static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
701static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
702static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
703static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
704static void output_P9_format PARAMS ((vbyte_func, int, int));
705static void output_P10_format PARAMS ((vbyte_func, int, int));
706static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
707static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800eeca4
JW		 708static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
709static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 710static char format_ab_reg PARAMS ((int, int));
711static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
712 unsigned long));
713static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
714static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
715 unsigned long));
716static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
717static void free_list_records PARAMS ((unw_rec_list *));
718static unw_rec_list *output_prologue PARAMS ((void));
719static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
720static unw_rec_list *output_body PARAMS ((void));
721static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
722static unw_rec_list *output_mem_stack_v PARAMS ((void));
723static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
724static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
725static unw_rec_list *output_rp_when PARAMS ((void));
726static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
727static unw_rec_list *output_rp_br PARAMS ((unsigned int));
728static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
729static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
730static unw_rec_list *output_pfs_when PARAMS ((void));
731static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
732static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
733static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
734static unw_rec_list *output_preds_when PARAMS ((void));
735static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
736static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
737static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
738static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
739static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
740static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
741static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
742static unw_rec_list *output_br_mem PARAMS ((unsigned int));
743static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
744static unw_rec_list *output_spill_base PARAMS ((unsigned int));
745static unw_rec_list *output_unat_when PARAMS ((void));
746static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
747static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
748static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
749static unw_rec_list *output_lc_when PARAMS ((void));
750static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
751static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
752static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
753static unw_rec_list *output_fpsr_when PARAMS ((void));
754static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
755static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
756static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
757static unw_rec_list *output_priunat_when_gr PARAMS ((void));
758static unw_rec_list *output_priunat_when_mem PARAMS ((void));
759static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
760static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
761static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
762static unw_rec_list *output_bsp_when PARAMS ((void));
763static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
764static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
765static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
766static unw_rec_list *output_bspstore_when PARAMS ((void));
767static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
768static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
769static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
770static unw_rec_list *output_rnat_when PARAMS ((void));
771static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
772static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
773static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
774static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
775static unw_rec_list *output_epilogue PARAMS ((unsigned long));
776static unw_rec_list *output_label_state PARAMS ((unsigned long));
777static unw_rec_list *output_copy_state PARAMS ((unsigned long));
778static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
779static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
780static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
781 unsigned int));
782static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
783 unsigned int));
784static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
785 unsigned int));
786static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
787 unsigned int, unsigned int));
788static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
789static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
790static int calc_record_size PARAMS ((unw_rec_list *));
791static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
792static int count_bits PARAMS ((unsigned long));
793static unsigned long slot_index PARAMS ((unsigned long, unsigned long));
794static void fixup_unw_records PARAMS ((unw_rec_list *));
795static int output_unw_records PARAMS ((unw_rec_list *, void **));
796static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
797static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
798static int generate_unwind_image PARAMS ((void));
800eeca4
JW		 799
800/* Determine if application register REGNUM resides in the integer
801 unit (as opposed to the memory unit). */
802static int
803ar_is_in_integer_unit (reg)
804 int reg;
805{
806 reg -= REG_AR;
807
808 return (reg == 64 /* pfs */
809 || reg == 65 /* lc */
810 || reg == 66 /* ec */
811 /* ??? ias accepts and puts these in the integer unit. */
812 || (reg >= 112 && reg <= 127));
813}
814
815/* Switch to section NAME and create section if necessary. It's
816 rather ugly that we have to manipulate input_line_pointer but I
817 don't see any other way to accomplish the same thing without
818 changing obj-elf.c (which may be the Right Thing, in the end). */
819static void
820set_section (name)
821 char *name;
822{
823 char *saved_input_line_pointer;
824
825 saved_input_line_pointer = input_line_pointer;
826 input_line_pointer = name;
827 obj_elf_section (0);
828 input_line_pointer = saved_input_line_pointer;
829}
830
831/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
832
833flagword
834ia64_elf_section_flags (flags, attr, type)
835 flagword flags;
836 int attr, type;
837{
838 if (attr & SHF_IA_64_SHORT)
839 flags |= SEC_SMALL_DATA;
840 return flags;
841}
842
843static unsigned int
844set_regstack (ins, locs, outs, rots)
845 unsigned int ins, locs, outs, rots;
846{
847 unsigned int sof; /* size of frame */
848
849 sof = ins + locs + outs;
850 if (sof > 96)
851 {
852 as_bad ("Size of frame exceeds maximum of 96 registers");
853 return 0;
854 }
855 if (rots > sof)
856 {
857 as_warn ("Size of rotating registers exceeds frame size");
858 return 0;
859 }
860 md.in.base = REG_GR + 32;
861 md.loc.base = md.in.base + ins;
862 md.out.base = md.loc.base + locs;
863
864 md.in.num_regs = ins;
865 md.loc.num_regs = locs;
866 md.out.num_regs = outs;
867 md.rot.num_regs = rots;
868 return sof;
869}
870
871void
872ia64_flush_insns ()
873{
874 struct label_fix *lfix;
875 segT saved_seg;
876 subsegT saved_subseg;
877
878 if (!md.last_text_seg)
879 return;
880
881 saved_seg = now_seg;
882 saved_subseg = now_subseg;
883
884 subseg_set (md.last_text_seg, 0);
885
886 while (md.num_slots_in_use > 0)
887 emit_one_bundle (); /* force out queued instructions */
888
889 /* In case there are labels following the last instruction, resolve
890 those now: */
891 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
892 {
893 S_SET_VALUE (lfix->sym, frag_now_fix ());
894 symbol_set_frag (lfix->sym, frag_now);
895 }
896 CURR_SLOT.label_fixups = 0;
897
898 subseg_set (saved_seg, saved_subseg);
899}
900
901void
902ia64_do_align (nbytes)
903 int nbytes;
904{
905 char *saved_input_line_pointer = input_line_pointer;
906
907 input_line_pointer = "";
908 s_align_bytes (nbytes);
909 input_line_pointer = saved_input_line_pointer;
910}
911
912void
913ia64_cons_align (nbytes)
914 int nbytes;
915{
916 if (md.auto_align)
917 {
918 char *saved_input_line_pointer = input_line_pointer;
919 input_line_pointer = "";
920 s_align_bytes (nbytes);
921 input_line_pointer = saved_input_line_pointer;
922 }
923}
924
925/* Output COUNT bytes to a memory location. */
926static unsigned char *vbyte_mem_ptr = NULL;
927
197865e8 928void
800eeca4
JW		 929output_vbyte_mem (count, ptr, comment)
930 int count;
931 char *ptr;
932 char *comment;
933{
934 int x;
935 if (vbyte_mem_ptr == NULL)
936 abort ();
937
938 if (count == 0)
939 return;
940 for (x = 0; x < count; x++)
941 *(vbyte_mem_ptr++) = ptr[x];
942}
943
944/* Count the number of bytes required for records. */
945static int vbyte_count = 0;
197865e8 946void
800eeca4
JW		 947count_output (count, ptr, comment)
948 int count;
949 char *ptr;
950 char *comment;
951{
952 vbyte_count += count;
953}
954
955static void
956output_R1_format (f, rtype, rlen)
957 vbyte_func f;
958 unw_record_type rtype;
959 int rlen;
960{
e0c9811a 961 int r = 0;
800eeca4
JW		 962 char byte;
963 if (rlen > 0x1f)
964 {
965 output_R3_format (f, rtype, rlen);
966 return;
967 }
197865e8 968
e0c9811a
JW		 969 if (rtype == body)
970 r = 1;
971 else if (rtype != prologue)
972 as_bad ("record type is not valid");
973
800eeca4
JW		 974 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
975 (*f) (1, &byte, NULL);
976}
977
978static void
979output_R2_format (f, mask, grsave, rlen)
980 vbyte_func f;
981 int mask, grsave;
982 unsigned long rlen;
983{
984 char bytes[20];
985 int count = 2;
986 mask = (mask & 0x0f);
987 grsave = (grsave & 0x7f);
988
989 bytes[0] = (UNW_R2 | (mask >> 1));
990 bytes[1] = (((mask & 0x01) << 7) | grsave);
991 count += output_leb128 (bytes + 2, rlen, 0);
992 (*f) (count, bytes, NULL);
993}
994
995static void
996output_R3_format (f, rtype, rlen)
997 vbyte_func f;
998 unw_record_type rtype;
999 unsigned long rlen;
1000{
e0c9811a 1001 int r = 0, count;
800eeca4
JW		 1002 char bytes[20];
1003 if (rlen <= 0x1f)
1004 {
1005 output_R1_format (f, rtype, rlen);
1006 return;
1007 }
197865e8 1008
e0c9811a
JW		 1009 if (rtype == body)
1010 r = 1;
1011 else if (rtype != prologue)
1012 as_bad ("record type is not valid");
800eeca4
JW		 1013 bytes[0] = (UNW_R3 | r);
1014 count = output_leb128 (bytes + 1, rlen, 0);
1015 (*f) (count + 1, bytes, NULL);
1016}
1017
1018static void
1019output_P1_format (f, brmask)
1020 vbyte_func f;
1021 int brmask;
1022{
1023 char byte;
1024 byte = UNW_P1 | (brmask & 0x1f);
1025 (*f) (1, &byte, NULL);
1026}
1027
1028static void
1029output_P2_format (f, brmask, gr)
1030 vbyte_func f;
1031 int brmask;
1032 int gr;
1033{
1034 char bytes[2];
1035 brmask = (brmask & 0x1f);
1036 bytes[0] = UNW_P2 | (brmask >> 1);
1037 bytes[1] = (((brmask & 1) << 7) | gr);
1038 (*f) (2, bytes, NULL);
1039}
1040
1041static void
1042output_P3_format (f, rtype, reg)
1043 vbyte_func f;
1044 unw_record_type rtype;
1045 int reg;
1046{
1047 char bytes[2];
e0c9811a 1048 int r = 0;
800eeca4
JW		 1049 reg = (reg & 0x7f);
1050 switch (rtype)
1051 {
1052 case psp_gr:
1053 r = 0;
1054 break;
1055 case rp_gr:
1056 r = 1;
1057 break;
1058 case pfs_gr:
1059 r = 2;
1060 break;
1061 case preds_gr:
1062 r = 3;
1063 break;
1064 case unat_gr:
1065 r = 4;
1066 break;
1067 case lc_gr:
1068 r = 5;
1069 break;
1070 case rp_br:
1071 r = 6;
1072 break;
1073 case rnat_gr:
1074 r = 7;
1075 break;
1076 case bsp_gr:
1077 r = 8;
1078 break;
1079 case bspstore_gr:
1080 r = 9;
1081 break;
1082 case fpsr_gr:
1083 r = 10;
1084 break;
1085 case priunat_gr:
1086 r = 11;
1087 break;
1088 default:
1089 as_bad ("Invalid record type for P3 format.");
1090 }
1091 bytes[0] = (UNW_P3 | (r >> 1));
1092 bytes[1] = (((r & 1) << 7) | reg);
1093 (*f) (2, bytes, NULL);
1094}
1095
800eeca4 1096static void
e0c9811a 1097output_P4_format (f, imask, imask_size)
800eeca4 1098 vbyte_func f;
e0c9811a
JW		 1099 unsigned char *imask;
1100 unsigned long imask_size;
800eeca4 1101{
e0c9811a
JW		 1102 imask[0] = UNW_P4;
1103 (*f) (imask_size, imask, NULL);
800eeca4
JW		 1104}
1105
1106static void
1107output_P5_format (f, grmask, frmask)
1108 vbyte_func f;
1109 int grmask;
1110 unsigned long frmask;
1111{
1112 char bytes[4];
1113 grmask = (grmask & 0x0f);
1114
1115 bytes[0] = UNW_P5;
1116 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1117 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1118 bytes[3] = (frmask & 0x000000ff);
1119 (*f) (4, bytes, NULL);
1120}
1121
1122static void
1123output_P6_format (f, rtype, rmask)
1124 vbyte_func f;
1125 unw_record_type rtype;
1126 int rmask;
1127{
1128 char byte;
e0c9811a 1129 int r = 0;
197865e8 1130
e0c9811a
JW		 1131 if (rtype == gr_mem)
1132 r = 1;
1133 else if (rtype != fr_mem)
1134 as_bad ("Invalid record type for format P6");
800eeca4
JW		 1135 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1136 (*f) (1, &byte, NULL);
1137}
1138
1139static void
1140output_P7_format (f, rtype, w1, w2)
1141 vbyte_func f;
1142 unw_record_type rtype;
1143 unsigned long w1;
1144 unsigned long w2;
1145{
1146 char bytes[20];
1147 int count = 1;
e0c9811a 1148 int r = 0;
800eeca4
JW		 1149 count += output_leb128 (bytes + 1, w1, 0);
1150 switch (rtype)
1151 {
1152 case mem_stack_f:
e4c58b25
JW		 1153 r = 0;
1154 count += output_leb128 (bytes + count, w2 >> 4, 0);
800eeca4
JW		 1155 break;
1156 case mem_stack_v:
1157 r = 1;
1158 break;
1159 case spill_base:
1160 r = 2;
1161 break;
1162 case psp_sprel:
1163 r = 3;
1164 break;
1165 case rp_when:
1166 r = 4;
1167 break;
1168 case rp_psprel:
1169 r = 5;
1170 break;
1171 case pfs_when:
1172 r = 6;
1173 break;
1174 case pfs_psprel:
1175 r = 7;
1176 break;
1177 case preds_when:
1178 r = 8;
1179 break;
1180 case preds_psprel:
1181 r = 9;
1182 break;
1183 case lc_when:
1184 r = 10;
1185 break;
1186 case lc_psprel:
1187 r = 11;
1188 break;
1189 case unat_when:
1190 r = 12;
1191 break;
1192 case unat_psprel:
1193 r = 13;
1194 break;
1195 case fpsr_when:
1196 r = 14;
1197 break;
1198 case fpsr_psprel:
1199 r = 15;
1200 break;
e0c9811a
JW		 1201 default:
1202 break;
800eeca4
JW		 1203 }
1204 bytes[0] = (UNW_P7 | r);
1205 (*f) (count, bytes, NULL);
1206}
1207
1208static void
1209output_P8_format (f, rtype, t)
1210 vbyte_func f;
1211 unw_record_type rtype;
1212 unsigned long t;
1213{
1214 char bytes[20];
e0c9811a 1215 int r = 0;
800eeca4
JW		 1216 int count = 2;
1217 bytes[0] = UNW_P8;
1218 switch (rtype)
1219 {
1220 case rp_sprel:
1221 r = 1;
1222 break;
1223 case pfs_sprel:
1224 r = 2;
1225 break;
1226 case preds_sprel:
1227 r = 3;
1228 break;
1229 case lc_sprel:
1230 r = 4;
1231 break;
1232 case unat_sprel:
1233 r = 5;
1234 break;
1235 case fpsr_sprel:
1236 r = 6;
1237 break;
1238 case bsp_when:
1239 r = 7;
1240 break;
1241 case bsp_psprel:
1242 r = 8;
1243 break;
1244 case bsp_sprel:
1245 r = 9;
1246 break;
1247 case bspstore_when:
1248 r = 10;
1249 break;
1250 case bspstore_psprel:
1251 r = 11;
1252 break;
1253 case bspstore_sprel:
1254 r = 12;
1255 break;
1256 case rnat_when:
1257 r = 13;
1258 break;
1259 case rnat_psprel:
1260 r = 14;
1261 break;
1262 case rnat_sprel:
1263 r = 15;
1264 break;
1265 case priunat_when_gr:
1266 r = 16;
1267 break;
1268 case priunat_psprel:
1269 r = 17;
1270 break;
1271 case priunat_sprel:
1272 r = 18;
1273 break;
1274 case priunat_when_mem:
1275 r = 19;
1276 break;
e0c9811a
JW		 1277 default:
1278 break;
800eeca4
JW		 1279 }
1280 bytes[1] = r;
1281 count += output_leb128 (bytes + 2, t, 0);
1282 (*f) (count, bytes, NULL);
1283}
1284
1285static void
1286output_P9_format (f, grmask, gr)
1287 vbyte_func f;
1288 int grmask;
1289 int gr;
1290{
1291 char bytes[3];
1292 bytes[0] = UNW_P9;
1293 bytes[1] = (grmask & 0x0f);
1294 bytes[2] = (gr & 0x7f);
1295 (*f) (3, bytes, NULL);
1296}
1297
1298static void
1299output_P10_format (f, abi, context)
1300 vbyte_func f;
1301 int abi;
1302 int context;
1303{
1304 char bytes[3];
1305 bytes[0] = UNW_P10;
1306 bytes[1] = (abi & 0xff);
1307 bytes[2] = (context & 0xff);
1308 (*f) (3, bytes, NULL);
1309}
1310
1311static void
1312output_B1_format (f, rtype, label)
1313 vbyte_func f;
1314 unw_record_type rtype;
1315 unsigned long label;
1316{
1317 char byte;
e0c9811a 1318 int r = 0;
197865e8 1319 if (label > 0x1f)
800eeca4
JW		 1320 {
1321 output_B4_format (f, rtype, label);
1322 return;
1323 }
e0c9811a
JW		 1324 if (rtype == copy_state)
1325 r = 1;
1326 else if (rtype != label_state)
1327 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1328
1329 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1330 (*f) (1, &byte, NULL);
1331}
1332
1333static void
1334output_B2_format (f, ecount, t)
1335 vbyte_func f;
1336 unsigned long ecount;
1337 unsigned long t;
1338{
1339 char bytes[20];
1340 int count = 1;
1341 if (ecount > 0x1f)
1342 {
1343 output_B3_format (f, ecount, t);
1344 return;
1345 }
1346 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1347 count += output_leb128 (bytes + 1, t, 0);
1348 (*f) (count, bytes, NULL);
1349}
1350
1351static void
1352output_B3_format (f, ecount, t)
1353 vbyte_func f;
1354 unsigned long ecount;
1355 unsigned long t;
1356{
1357 char bytes[20];
1358 int count = 1;
1359 if (ecount <= 0x1f)
1360 {
1361 output_B2_format (f, ecount, t);
1362 return;
1363 }
1364 bytes[0] = UNW_B3;
1365 count += output_leb128 (bytes + 1, t, 0);
1366 count += output_leb128 (bytes + count, ecount, 0);
1367 (*f) (count, bytes, NULL);
1368}
1369
1370static void
1371output_B4_format (f, rtype, label)
1372 vbyte_func f;
1373 unw_record_type rtype;
1374 unsigned long label;
1375{
1376 char bytes[20];
e0c9811a 1377 int r = 0;
800eeca4 1378 int count = 1;
197865e8 1379 if (label <= 0x1f)
800eeca4
JW		 1380 {
1381 output_B1_format (f, rtype, label);
1382 return;
1383 }
197865e8 1384
e0c9811a
JW		 1385 if (rtype == copy_state)
1386 r = 1;
1387 else if (rtype != label_state)
1388 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1389
1390 bytes[0] = (UNW_B4 | (r << 3));
1391 count += output_leb128 (bytes + 1, label, 0);
1392 (*f) (count, bytes, NULL);
1393}
1394
1395static char
e0c9811a
JW		 1396format_ab_reg (ab, reg)
1397 int ab;
800eeca4
JW		 1398 int reg;
1399{
1400 int ret;
e0c9811a 1401 ab = (ab & 3);
800eeca4 1402 reg = (reg & 0x1f);
e0c9811a 1403 ret = (ab << 5) | reg;
800eeca4
JW		 1404 return ret;
1405}
1406
1407static void
e0c9811a 1408output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW		 1409 vbyte_func f;
1410 unw_record_type rtype;
e0c9811a 1411 int ab, reg;
800eeca4
JW		 1412 unsigned long t;
1413 unsigned long w1;
1414{
1415 char bytes[20];
e0c9811a 1416 int r = 0;
800eeca4
JW		 1417 int count = 2;
1418 bytes[0] = UNW_X1;
197865e8 1419
e0c9811a
JW		 1420 if (rtype == spill_sprel)
1421 r = 1;
1422 else if (rtype != spill_psprel)
1423 as_bad ("Invalid record type for format X1");
1424 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1425 count += output_leb128 (bytes + 2, t, 0);
1426 count += output_leb128 (bytes + count, w1, 0);
1427 (*f) (count, bytes, NULL);
1428}
1429
1430static void
e0c9811a 1431output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1432 vbyte_func f;
e0c9811a 1433 int ab, reg;
800eeca4
JW		 1434 int x, y, treg;
1435 unsigned long t;
1436{
1437 char bytes[20];
800eeca4
JW		 1438 int count = 3;
1439 bytes[0] = UNW_X2;
e0c9811a 1440 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1441 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1442 count += output_leb128 (bytes + 3, t, 0);
1443 (*f) (count, bytes, NULL);
1444}
1445
1446static void
e0c9811a 1447output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW		 1448 vbyte_func f;
1449 unw_record_type rtype;
1450 int qp;
e0c9811a 1451 int ab, reg;
800eeca4
JW		 1452 unsigned long t;
1453 unsigned long w1;
1454{
1455 char bytes[20];
e0c9811a 1456 int r = 0;
800eeca4 1457 int count = 3;
e0c9811a
JW		 1458 bytes[0] = UNW_X3;
1459
1460 if (rtype == spill_sprel_p)
1461 r = 1;
1462 else if (rtype != spill_psprel_p)
1463 as_bad ("Invalid record type for format X3");
800eeca4 1464 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1465 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW		 1466 count += output_leb128 (bytes + 3, t, 0);
1467 count += output_leb128 (bytes + count, w1, 0);
1468 (*f) (count, bytes, NULL);
1469}
1470
1471static void
e0c9811a 1472output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW		 1473 vbyte_func f;
1474 int qp;
e0c9811a 1475 int ab, reg;
800eeca4
JW		 1476 int x, y, treg;
1477 unsigned long t;
1478{
1479 char bytes[20];
800eeca4 1480 int count = 4;
e0c9811a 1481 bytes[0] = UNW_X4;
800eeca4 1482 bytes[1] = (qp & 0x3f);
e0c9811a 1483 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1484 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1485 count += output_leb128 (bytes + 4, t, 0);
1486 (*f) (count, bytes, NULL);
1487}
1488
1489/* This function allocates a record list structure, and initializes fields. */
1490static unw_rec_list *
197865e8 1491alloc_record (unw_record_type t)
800eeca4
JW		 1492{
1493 unw_rec_list *ptr;
1494 ptr = xmalloc (sizeof (*ptr));
1495 ptr->next = NULL;
1496 ptr->slot_number = SLOT_NUM_NOT_SET;
1497 ptr->r.type = t;
1498 return ptr;
1499}
1500
800eeca4
JW		 1501/* This function frees an entire list of record structures. */
1502void
1503free_list_records (unw_rec_list *first)
1504{
1505 unw_rec_list *ptr;
1506 for (ptr = first; ptr != NULL; )
1507 {
1508 unw_rec_list *tmp = ptr;
e0c9811a
JW		 1509
1510 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1511 && tmp->r.record.r.mask.i)
1512 free (tmp->r.record.r.mask.i);
1513
800eeca4
JW		 1514 ptr = ptr->next;
1515 free (tmp);
1516 }
1517}
1518
1519static unw_rec_list *
1520output_prologue ()
1521{
1522 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1523 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW		 1524 return ptr;
1525}
1526
1527static unw_rec_list *
1528output_prologue_gr (saved_mask, reg)
1529 unsigned int saved_mask;
1530 unsigned int reg;
1531{
1532 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW		 1533 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1534 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW		 1535 ptr->r.record.r.grsave = reg;
1536 return ptr;
1537}
1538
1539static unw_rec_list *
1540output_body ()
1541{
1542 unw_rec_list *ptr = alloc_record (body);
1543 return ptr;
1544}
1545
1546static unw_rec_list *
1547output_mem_stack_f (size)
1548 unsigned int size;
1549{
1550 unw_rec_list *ptr = alloc_record (mem_stack_f);
1551 ptr->r.record.p.size = size;
1552 return ptr;
1553}
1554
1555static unw_rec_list *
1556output_mem_stack_v ()
1557{
1558 unw_rec_list *ptr = alloc_record (mem_stack_v);
1559 return ptr;
1560}
1561
1562static unw_rec_list *
1563output_psp_gr (gr)
1564 unsigned int gr;
1565{
1566 unw_rec_list *ptr = alloc_record (psp_gr);
1567 ptr->r.record.p.gr = gr;
1568 return ptr;
1569}
1570
1571static unw_rec_list *
1572output_psp_sprel (offset)
1573 unsigned int offset;
1574{
1575 unw_rec_list *ptr = alloc_record (psp_sprel);
e0c9811a 1576 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1577 return ptr;
1578}
1579
1580static unw_rec_list *
1581output_rp_when ()
1582{
1583 unw_rec_list *ptr = alloc_record (rp_when);
1584 return ptr;
1585}
1586
1587static unw_rec_list *
1588output_rp_gr (gr)
1589 unsigned int gr;
1590{
1591 unw_rec_list *ptr = alloc_record (rp_gr);
1592 ptr->r.record.p.gr = gr;
1593 return ptr;
1594}
1595
1596static unw_rec_list *
1597output_rp_br (br)
1598 unsigned int br;
1599{
1600 unw_rec_list *ptr = alloc_record (rp_br);
1601 ptr->r.record.p.br = br;
1602 return ptr;
1603}
1604
1605static unw_rec_list *
1606output_rp_psprel (offset)
1607 unsigned int offset;
1608{
1609 unw_rec_list *ptr = alloc_record (rp_psprel);
e0c9811a 1610 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1611 return ptr;
1612}
1613
1614static unw_rec_list *
1615output_rp_sprel (offset)
1616 unsigned int offset;
1617{
1618 unw_rec_list *ptr = alloc_record (rp_sprel);
e0c9811a 1619 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1620 return ptr;
1621}
1622
1623static unw_rec_list *
1624output_pfs_when ()
1625{
1626 unw_rec_list *ptr = alloc_record (pfs_when);
1627 return ptr;
1628}
1629
1630static unw_rec_list *
1631output_pfs_gr (gr)
1632 unsigned int gr;
1633{
1634 unw_rec_list *ptr = alloc_record (pfs_gr);
1635 ptr->r.record.p.gr = gr;
1636 return ptr;
1637}
1638
1639static unw_rec_list *
1640output_pfs_psprel (offset)
1641 unsigned int offset;
1642{
1643 unw_rec_list *ptr = alloc_record (pfs_psprel);
e0c9811a 1644 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1645 return ptr;
1646}
1647
1648static unw_rec_list *
1649output_pfs_sprel (offset)
1650 unsigned int offset;
1651{
1652 unw_rec_list *ptr = alloc_record (pfs_sprel);
e0c9811a 1653 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1654 return ptr;
1655}
1656
1657static unw_rec_list *
1658output_preds_when ()
1659{
1660 unw_rec_list *ptr = alloc_record (preds_when);
1661 return ptr;
1662}
1663
1664static unw_rec_list *
1665output_preds_gr (gr)
1666 unsigned int gr;
1667{
1668 unw_rec_list *ptr = alloc_record (preds_gr);
1669 ptr->r.record.p.gr = gr;
1670 return ptr;
1671}
1672
1673static unw_rec_list *
1674output_preds_psprel (offset)
1675 unsigned int offset;
1676{
1677 unw_rec_list *ptr = alloc_record (preds_psprel);
e0c9811a 1678 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1679 return ptr;
1680}
1681
1682static unw_rec_list *
1683output_preds_sprel (offset)
1684 unsigned int offset;
1685{
1686 unw_rec_list *ptr = alloc_record (preds_sprel);
e0c9811a 1687 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1688 return ptr;
1689}
1690
1691static unw_rec_list *
1692output_fr_mem (mask)
1693 unsigned int mask;
1694{
1695 unw_rec_list *ptr = alloc_record (fr_mem);
1696 ptr->r.record.p.rmask = mask;
1697 return ptr;
1698}
1699
1700static unw_rec_list *
1701output_frgr_mem (gr_mask, fr_mask)
1702 unsigned int gr_mask;
1703 unsigned int fr_mask;
1704{
1705 unw_rec_list *ptr = alloc_record (frgr_mem);
1706 ptr->r.record.p.grmask = gr_mask;
1707 ptr->r.record.p.frmask = fr_mask;
1708 return ptr;
1709}
1710
1711static unw_rec_list *
1712output_gr_gr (mask, reg)
1713 unsigned int mask;
1714 unsigned int reg;
1715{
1716 unw_rec_list *ptr = alloc_record (gr_gr);
1717 ptr->r.record.p.grmask = mask;
1718 ptr->r.record.p.gr = reg;
1719 return ptr;
1720}
1721
1722static unw_rec_list *
1723output_gr_mem (mask)
1724 unsigned int mask;
1725{
1726 unw_rec_list *ptr = alloc_record (gr_mem);
1727 ptr->r.record.p.rmask = mask;
1728 return ptr;
1729}
1730
1731static unw_rec_list *
1732output_br_mem (unsigned int mask)
1733{
1734 unw_rec_list *ptr = alloc_record (br_mem);
1735 ptr->r.record.p.brmask = mask;
1736 return ptr;
1737}
1738
1739static unw_rec_list *
1740output_br_gr (save_mask, reg)
1741 unsigned int save_mask;
1742 unsigned int reg;
1743{
1744 unw_rec_list *ptr = alloc_record (br_gr);
1745 ptr->r.record.p.brmask = save_mask;
1746 ptr->r.record.p.gr = reg;
1747 return ptr;
1748}
1749
1750static unw_rec_list *
1751output_spill_base (offset)
1752 unsigned int offset;
1753{
1754 unw_rec_list *ptr = alloc_record (spill_base);
e0c9811a 1755 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1756 return ptr;
1757}
1758
1759static unw_rec_list *
1760output_unat_when ()
1761{
1762 unw_rec_list *ptr = alloc_record (unat_when);
1763 return ptr;
1764}
1765
1766static unw_rec_list *
1767output_unat_gr (gr)
1768 unsigned int gr;
1769{
1770 unw_rec_list *ptr = alloc_record (unat_gr);
1771 ptr->r.record.p.gr = gr;
1772 return ptr;
1773}
1774
1775static unw_rec_list *
1776output_unat_psprel (offset)
1777 unsigned int offset;
1778{
1779 unw_rec_list *ptr = alloc_record (unat_psprel);
e0c9811a 1780 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1781 return ptr;
1782}
1783
1784static unw_rec_list *
1785output_unat_sprel (offset)
1786 unsigned int offset;
1787{
1788 unw_rec_list *ptr = alloc_record (unat_sprel);
e0c9811a 1789 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1790 return ptr;
1791}
1792
1793static unw_rec_list *
1794output_lc_when ()
1795{
1796 unw_rec_list *ptr = alloc_record (lc_when);
1797 return ptr;
1798}
1799
1800static unw_rec_list *
1801output_lc_gr (gr)
1802 unsigned int gr;
1803{
1804 unw_rec_list *ptr = alloc_record (lc_gr);
1805 ptr->r.record.p.gr = gr;
1806 return ptr;
1807}
1808
1809static unw_rec_list *
1810output_lc_psprel (offset)
1811 unsigned int offset;
1812{
1813 unw_rec_list *ptr = alloc_record (lc_psprel);
e0c9811a 1814 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1815 return ptr;
1816}
1817
1818static unw_rec_list *
1819output_lc_sprel (offset)
1820 unsigned int offset;
1821{
1822 unw_rec_list *ptr = alloc_record (lc_sprel);
e0c9811a 1823 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1824 return ptr;
1825}
1826
1827static unw_rec_list *
1828output_fpsr_when ()
1829{
1830 unw_rec_list *ptr = alloc_record (fpsr_when);
1831 return ptr;
1832}
1833
1834static unw_rec_list *
1835output_fpsr_gr (gr)
1836 unsigned int gr;
1837{
1838 unw_rec_list *ptr = alloc_record (fpsr_gr);
1839 ptr->r.record.p.gr = gr;
1840 return ptr;
1841}
1842
1843static unw_rec_list *
1844output_fpsr_psprel (offset)
1845 unsigned int offset;
1846{
1847 unw_rec_list *ptr = alloc_record (fpsr_psprel);
e0c9811a 1848 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1849 return ptr;
1850}
1851
1852static unw_rec_list *
1853output_fpsr_sprel (offset)
1854 unsigned int offset;
1855{
1856 unw_rec_list *ptr = alloc_record (fpsr_sprel);
e0c9811a 1857 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1858 return ptr;
1859}
1860
1861static unw_rec_list *
1862output_priunat_when_gr ()
1863{
1864 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1865 return ptr;
1866}
1867
1868static unw_rec_list *
1869output_priunat_when_mem ()
1870{
1871 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1872 return ptr;
1873}
1874
1875static unw_rec_list *
1876output_priunat_gr (gr)
1877 unsigned int gr;
1878{
1879 unw_rec_list *ptr = alloc_record (priunat_gr);
1880 ptr->r.record.p.gr = gr;
1881 return ptr;
1882}
1883
1884static unw_rec_list *
1885output_priunat_psprel (offset)
1886 unsigned int offset;
1887{
1888 unw_rec_list *ptr = alloc_record (priunat_psprel);
e0c9811a 1889 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1890 return ptr;
1891}
1892
1893static unw_rec_list *
1894output_priunat_sprel (offset)
1895 unsigned int offset;
1896{
1897 unw_rec_list *ptr = alloc_record (priunat_sprel);
e0c9811a 1898 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1899 return ptr;
1900}
1901
1902static unw_rec_list *
1903output_bsp_when ()
1904{
1905 unw_rec_list *ptr = alloc_record (bsp_when);
1906 return ptr;
1907}
1908
1909static unw_rec_list *
1910output_bsp_gr (gr)
1911 unsigned int gr;
1912{
1913 unw_rec_list *ptr = alloc_record (bsp_gr);
1914 ptr->r.record.p.gr = gr;
1915 return ptr;
1916}
1917
1918static unw_rec_list *
1919output_bsp_psprel (offset)
1920 unsigned int offset;
1921{
1922 unw_rec_list *ptr = alloc_record (bsp_psprel);
e0c9811a 1923 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1924 return ptr;
1925}
1926
1927static unw_rec_list *
1928output_bsp_sprel (offset)
1929 unsigned int offset;
1930{
1931 unw_rec_list *ptr = alloc_record (bsp_sprel);
e0c9811a 1932 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1933 return ptr;
1934}
1935
1936static unw_rec_list *
1937output_bspstore_when ()
1938{
1939 unw_rec_list *ptr = alloc_record (bspstore_when);
1940 return ptr;
1941}
1942
1943static unw_rec_list *
1944output_bspstore_gr (gr)
1945 unsigned int gr;
1946{
1947 unw_rec_list *ptr = alloc_record (bspstore_gr);
1948 ptr->r.record.p.gr = gr;
1949 return ptr;
1950}
1951
1952static unw_rec_list *
1953output_bspstore_psprel (offset)
1954 unsigned int offset;
1955{
1956 unw_rec_list *ptr = alloc_record (bspstore_psprel);
e0c9811a 1957 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1958 return ptr;
1959}
1960
1961static unw_rec_list *
1962output_bspstore_sprel (offset)
1963 unsigned int offset;
1964{
1965 unw_rec_list *ptr = alloc_record (bspstore_sprel);
e0c9811a 1966 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 1967 return ptr;
1968}
1969
1970static unw_rec_list *
1971output_rnat_when ()
1972{
1973 unw_rec_list *ptr = alloc_record (rnat_when);
1974 return ptr;
1975}
1976
1977static unw_rec_list *
1978output_rnat_gr (gr)
1979 unsigned int gr;
1980{
1981 unw_rec_list *ptr = alloc_record (rnat_gr);
1982 ptr->r.record.p.gr = gr;
1983 return ptr;
1984}
1985
1986static unw_rec_list *
1987output_rnat_psprel (offset)
1988 unsigned int offset;
1989{
1990 unw_rec_list *ptr = alloc_record (rnat_psprel);
e0c9811a 1991 ptr->r.record.p.pspoff = offset/4;
800eeca4
JW		 1992 return ptr;
1993}
1994
1995static unw_rec_list *
1996output_rnat_sprel (offset)
1997 unsigned int offset;
1998{
1999 unw_rec_list *ptr = alloc_record (rnat_sprel);
e0c9811a 2000 ptr->r.record.p.spoff = offset/4;
800eeca4
JW		 2001 return ptr;
2002}
2003
2004static unw_rec_list *
e0c9811a
JW		 2005output_unwabi (abi, context)
2006 unsigned long abi;
2007 unsigned long context;
800eeca4 2008{
e0c9811a
JW		 2009 unw_rec_list *ptr = alloc_record (unwabi);
2010 ptr->r.record.p.abi = abi;
2011 ptr->r.record.p.context = context;
800eeca4
JW		 2012 return ptr;
2013}
2014
2015static unw_rec_list *
e0c9811a 2016output_epilogue (unsigned long ecount)
800eeca4 2017{
e0c9811a
JW		 2018 unw_rec_list *ptr = alloc_record (epilogue);
2019 ptr->r.record.b.ecount = ecount;
800eeca4
JW		 2020 return ptr;
2021}
2022
2023static unw_rec_list *
e0c9811a 2024output_label_state (unsigned long label)
800eeca4 2025{
e0c9811a
JW		 2026 unw_rec_list *ptr = alloc_record (label_state);
2027 ptr->r.record.b.label = label;
800eeca4
JW		 2028 return ptr;
2029}
2030
2031static unw_rec_list *
e0c9811a
JW		 2032output_copy_state (unsigned long label)
2033{
2034 unw_rec_list *ptr = alloc_record (copy_state);
2035 ptr->r.record.b.label = label;
2036 return ptr;
2037}
2038
2039static unw_rec_list *
2040output_spill_psprel (ab, reg, offset)
2041 unsigned int ab;
800eeca4
JW		 2042 unsigned int reg;
2043 unsigned int offset;
2044{
2045 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 2046 ptr->r.record.x.ab = ab;
800eeca4 2047 ptr->r.record.x.reg = reg;
e0c9811a 2048 ptr->r.record.x.pspoff = offset/4;
800eeca4
JW		 2049 return ptr;
2050}
2051
2052static unw_rec_list *
e0c9811a
JW		 2053output_spill_sprel (ab, reg, offset)
2054 unsigned int ab;
800eeca4
JW		 2055 unsigned int reg;
2056 unsigned int offset;
2057{
2058 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 2059 ptr->r.record.x.ab = ab;
800eeca4 2060 ptr->r.record.x.reg = reg;
e0c9811a 2061 ptr->r.record.x.spoff = offset/4;
800eeca4
JW		 2062 return ptr;
2063}
2064
2065static unw_rec_list *
e0c9811a
JW		 2066output_spill_psprel_p (ab, reg, offset, predicate)
2067 unsigned int ab;
800eeca4
JW		 2068 unsigned int reg;
2069 unsigned int offset;
2070 unsigned int predicate;
2071{
2072 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 2073 ptr->r.record.x.ab = ab;
800eeca4 2074 ptr->r.record.x.reg = reg;
e0c9811a 2075 ptr->r.record.x.pspoff = offset/4;
800eeca4
JW		 2076 ptr->r.record.x.qp = predicate;
2077 return ptr;
2078}
2079
2080static unw_rec_list *
e0c9811a
JW		 2081output_spill_sprel_p (ab, reg, offset, predicate)
2082 unsigned int ab;
800eeca4
JW		 2083 unsigned int reg;
2084 unsigned int offset;
2085 unsigned int predicate;
2086{
2087 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 2088 ptr->r.record.x.ab = ab;
800eeca4 2089 ptr->r.record.x.reg = reg;
e0c9811a 2090 ptr->r.record.x.spoff = offset/4;
800eeca4
JW		 2091 ptr->r.record.x.qp = predicate;
2092 return ptr;
2093}
2094
2095static unw_rec_list *
e0c9811a
JW		 2096output_spill_reg (ab, reg, targ_reg, xy)
2097 unsigned int ab;
800eeca4
JW		 2098 unsigned int reg;
2099 unsigned int targ_reg;
2100 unsigned int xy;
2101{
2102 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 2103 ptr->r.record.x.ab = ab;
800eeca4
JW		 2104 ptr->r.record.x.reg = reg;
2105 ptr->r.record.x.treg = targ_reg;
2106 ptr->r.record.x.xy = xy;
2107 return ptr;
2108}
2109
2110static unw_rec_list *
e0c9811a
JW		 2111output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2112 unsigned int ab;
800eeca4
JW		 2113 unsigned int reg;
2114 unsigned int targ_reg;
2115 unsigned int xy;
2116 unsigned int predicate;
2117{
2118 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 2119 ptr->r.record.x.ab = ab;
800eeca4
JW		 2120 ptr->r.record.x.reg = reg;
2121 ptr->r.record.x.treg = targ_reg;
2122 ptr->r.record.x.xy = xy;
2123 ptr->r.record.x.qp = predicate;
2124 return ptr;
2125}
2126
197865e8 2127/* Given a unw_rec_list process the correct format with the
800eeca4
JW		 2128 specified function. */
2129static void
2130process_one_record (ptr, f)
2131 unw_rec_list *ptr;
2132 vbyte_func f;
2133{
e0c9811a
JW		 2134 unsigned long fr_mask, gr_mask;
2135
197865e8 2136 switch (ptr->r.type)
800eeca4 2137 {
e0c9811a
JW		 2138 case gr_mem:
2139 case fr_mem:
2140 case br_mem:
2141 case frgr_mem:
2142 /* these are taken care of by prologue/prologue_gr */
2143 break;
2144
2145 case prologue_gr:
800eeca4 2146 case prologue:
e0c9811a
JW		 2147 if (ptr->r.type == prologue_gr)
2148 output_R2_format (f, ptr->r.record.r.grmask,
2149 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2150 else
2151 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2152
2153 /* output descriptor(s) for union of register spills (if any): */
2154 gr_mask = ptr->r.record.r.mask.gr_mem;
2155 fr_mask = ptr->r.record.r.mask.fr_mem;
2156 if (fr_mask)
2157 {
2158 if ((fr_mask & ~0xfUL) == 0)
2159 output_P6_format (f, fr_mem, fr_mask);
2160 else
2161 {
2162 output_P5_format (f, gr_mask, fr_mask);
2163 gr_mask = 0;
2164 }
2165 }
2166 if (gr_mask)
2167 output_P6_format (f, gr_mem, gr_mask);
2168 if (ptr->r.record.r.mask.br_mem)
2169 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2170
2171 /* output imask descriptor if necessary: */
2172 if (ptr->r.record.r.mask.i)
2173 output_P4_format (f, ptr->r.record.r.mask.i,
2174 ptr->r.record.r.imask_size);
2175 break;
2176
800eeca4
JW		 2177 case body:
2178 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2179 break;
800eeca4
JW		 2180 case mem_stack_f:
2181 case mem_stack_v:
197865e8 2182 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
800eeca4
JW		 2183 ptr->r.record.p.size);
2184 break;
2185 case psp_gr:
2186 case rp_gr:
2187 case pfs_gr:
2188 case preds_gr:
2189 case unat_gr:
2190 case lc_gr:
2191 case fpsr_gr:
2192 case priunat_gr:
2193 case bsp_gr:
2194 case bspstore_gr:
2195 case rnat_gr:
2196 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2197 break;
2198 case rp_br:
2199 output_P3_format (f, rp_br, ptr->r.record.p.br);
2200 break;
2201 case psp_sprel:
2202 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2203 break;
2204 case rp_when:
2205 case pfs_when:
2206 case preds_when:
2207 case unat_when:
2208 case lc_when:
2209 case fpsr_when:
2210 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2211 break;
2212 case rp_psprel:
2213 case pfs_psprel:
2214 case preds_psprel:
2215 case unat_psprel:
2216 case lc_psprel:
2217 case fpsr_psprel:
2218 case spill_base:
2219 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2220 break;
2221 case rp_sprel:
2222 case pfs_sprel:
2223 case preds_sprel:
2224 case unat_sprel:
2225 case lc_sprel:
2226 case fpsr_sprel:
2227 case priunat_sprel:
2228 case bsp_sprel:
2229 case bspstore_sprel:
2230 case rnat_sprel:
2231 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2232 break;
800eeca4
JW		 2233 case gr_gr:
2234 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2235 break;
800eeca4
JW		 2236 case br_gr:
2237 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2238 break;
2239 case spill_mask:
2240 as_bad ("spill_mask record unimplemented.");
2241 break;
2242 case priunat_when_gr:
2243 case priunat_when_mem:
2244 case bsp_when:
2245 case bspstore_when:
2246 case rnat_when:
2247 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2248 break;
2249 case priunat_psprel:
2250 case bsp_psprel:
2251 case bspstore_psprel:
2252 case rnat_psprel:
2253 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2254 break;
e0c9811a
JW		 2255 case unwabi:
2256 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2257 break;
800eeca4 2258 case epilogue:
e0c9811a 2259 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
800eeca4
JW		 2260 break;
2261 case label_state:
800eeca4 2262 case copy_state:
e0c9811a 2263 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
800eeca4
JW		 2264 break;
2265 case spill_psprel:
e0c9811a
JW		 2266 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2267 ptr->r.record.x.reg, ptr->r.record.x.t,
2268 ptr->r.record.x.pspoff);
2269 break;
800eeca4 2270 case spill_sprel:
e0c9811a
JW		 2271 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2272 ptr->r.record.x.reg, ptr->r.record.x.t,
2273 ptr->r.record.x.spoff);
2274 break;
800eeca4 2275 case spill_reg:
e0c9811a
JW		 2276 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2277 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2278 ptr->r.record.x.treg, ptr->r.record.x.t);
2279 break;
800eeca4 2280 case spill_psprel_p:
e0c9811a
JW		 2281 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2282 ptr->r.record.x.ab, ptr->r.record.x.reg,
2283 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2284 break;
800eeca4 2285 case spill_sprel_p:
e0c9811a
JW		 2286 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2287 ptr->r.record.x.ab, ptr->r.record.x.reg,
2288 ptr->r.record.x.t, ptr->r.record.x.spoff);
2289 break;
800eeca4 2290 case spill_reg_p:
e0c9811a
JW		 2291 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2292 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2293 ptr->r.record.x.xy, ptr->r.record.x.treg,
2294 ptr->r.record.x.t);
800eeca4
JW		 2295 break;
2296 default:
2297 as_bad ("record_type_not_valid");
2298 break;
2299 }
2300}
2301
197865e8 2302/* Given a unw_rec_list list, process all the records with
800eeca4
JW		 2303 the specified function. */
2304static void
2305process_unw_records (list, f)
2306 unw_rec_list *list;
2307 vbyte_func f;
2308{
2309 unw_rec_list *ptr;
2310 for (ptr = list; ptr; ptr = ptr->next)
2311 process_one_record (ptr, f);
2312}
2313
2314/* Determine the size of a record list in bytes. */
2315static int
2316calc_record_size (list)
2317 unw_rec_list *list;
2318{
2319 vbyte_count = 0;
2320 process_unw_records (list, count_output);
2321 return vbyte_count;
2322}
2323
e0c9811a
JW		 2324/* Update IMASK bitmask to reflect the fact that one or more registers
2325 of type TYPE are saved starting at instruction with index T. If N
2326 bits are set in REGMASK, it is assumed that instructions T through
2327 T+N-1 save these registers.
2328
2329 TYPE values:
2330 0: no save
2331 1: instruction saves next fp reg
2332 2: instruction saves next general reg
2333 3: instruction saves next branch reg */
2334static void
2335set_imask (region, regmask, t, type)
2336 unw_rec_list *region;
2337 unsigned long regmask;
2338 unsigned long t;
2339 unsigned int type;
2340{
2341 unsigned char *imask;
2342 unsigned long imask_size;
2343 unsigned int i;
2344 int pos;
2345
2346 imask = region->r.record.r.mask.i;
2347 imask_size = region->r.record.r.imask_size;
2348 if (!imask)
2349 {
2350 imask_size = (region->r.record.r.rlen*2 + 7)/8 + 1;
2351 imask = xmalloc (imask_size);
2352 memset (imask, 0, imask_size);
2353
2354 region->r.record.r.imask_size = imask_size;
2355 region->r.record.r.mask.i = imask;
2356 }
2357
2358 i = (t/4) + 1;
2359 pos = 2*(3 - t%4);
2360 while (regmask)
2361 {
2362 if (i >= imask_size)
2363 {
2364 as_bad ("Ignoring attempt to spill beyond end of region");
2365 return;
2366 }
2367
2368 imask[i] |= (type & 0x3) << pos;
197865e8 2369
e0c9811a
JW		 2370 regmask &= (regmask - 1);
2371 pos -= 2;
2372 if (pos < 0)
2373 {
2374 pos = 0;
2375 ++i;
2376 }
2377 }
2378}
2379
2380static int
2381count_bits (unsigned long mask)
2382{
2383 int n = 0;
2384
2385 while (mask)
2386 {
2387 mask &= mask - 1;
2388 ++n;
2389 }
2390 return n;
2391}
2392
2393unsigned long
2394slot_index (unsigned long slot_addr, unsigned long first_addr)
2395{
2396 return (3*((slot_addr >> 4) - (first_addr >> 4))
2397 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2398}
2399
800eeca4
JW		 2400/* Given a complete record list, process any records which have
2401 unresolved fields, (ie length counts for a prologue). After
197865e8 2402 this has been run, all neccessary information should be available
800eeca4
JW		 2403 within each record to generate an image. */
2404static void
2405fixup_unw_records (list)
2406 unw_rec_list *list;
2407{
e0c9811a
JW		 2408 unw_rec_list *ptr, *region = 0;
2409 unsigned long first_addr = 0, rlen = 0, t;
2410
800eeca4
JW		 2411 for (ptr = list; ptr; ptr = ptr->next)
2412 {
2413 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2414 as_bad (" Insn slot not set in unwind record.");
e0c9811a 2415 t = slot_index (ptr->slot_number, first_addr);
800eeca4
JW		 2416 switch (ptr->r.type)
2417 {
2418 case prologue:
2419 case prologue_gr:
2420 case body:
2421 {
2422 unw_rec_list *last;
e0c9811a 2423 int size, dir_len = 0;
800eeca4 2424 unsigned long last_addr;
e0c9811a 2425
800eeca4
JW		 2426 first_addr = ptr->slot_number;
2427 ptr->slot_number = 0;
197865e8 2428 /* Find either the next body/prologue start, or the end of
800eeca4 2429 the list, and determine the size of the region. */
e0c9811a
JW		 2430 last_addr = unwind.next_slot_number;
2431 for (last = ptr->next; last != NULL; last = last->next)
2432 if (last->r.type == prologue || last->r.type == prologue_gr
2433 || last->r.type == body)
800eeca4 2434 {
e0c9811a 2435 last_addr = last->slot_number;
800eeca4
JW		 2436 break;
2437 }
e0c9811a
JW		 2438 else if (!last->next)
2439 {
2440 /* In the absence of an explicit .body directive,
2441 the prologue ends after the last instruction
197865e8 2442 covered by an unwind directive. */
e0c9811a
JW		 2443 if (ptr->r.type != body)
2444 {
2445 last_addr = last->slot_number;
2446 switch (last->r.type)
2447 {
2448 case frgr_mem:
2449 dir_len = (count_bits (last->r.record.p.frmask)
2450 + count_bits (last->r.record.p.grmask));
2451 break;
2452 case fr_mem:
2453 case gr_mem:
2454 dir_len += count_bits (last->r.record.p.rmask);
2455 break;
2456 case br_mem:
2457 case br_gr:
2458 dir_len += count_bits (last->r.record.p.brmask);
2459 break;
2460 case gr_gr:
2461 dir_len += count_bits (last->r.record.p.grmask);
2462 break;
2463 default:
2464 dir_len = 1;
2465 break;
2466 }
2467 }
2468 break;
2469 }
2470 size = slot_index (last_addr, first_addr) + dir_len;
2471 rlen = ptr->r.record.r.rlen = size;
2472 region = ptr;
800eeca4
JW		 2473 break;
2474 }
e0c9811a
JW		 2475 case epilogue:
2476 ptr->r.record.b.t = rlen - 1 - t;
2477 break;
2478
800eeca4
JW		 2479 case mem_stack_f:
2480 case mem_stack_v:
2481 case rp_when:
2482 case pfs_when:
2483 case preds_when:
2484 case unat_when:
2485 case lc_when:
2486 case fpsr_when:
2487 case priunat_when_gr:
2488 case priunat_when_mem:
2489 case bsp_when:
2490 case bspstore_when:
2491 case rnat_when:
e0c9811a
JW		 2492 ptr->r.record.p.t = t;
2493 break;
2494
2495 case spill_reg:
2496 case spill_sprel:
2497 case spill_psprel:
2498 case spill_reg_p:
2499 case spill_sprel_p:
2500 case spill_psprel_p:
2501 ptr->r.record.x.t = t;
2502 break;
2503
2504 case frgr_mem:
2505 if (!region)
2506 {
2507 as_bad ("frgr_mem record before region record!\n");
2508 return;
2509 }
2510 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2511 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2512 set_imask (region, ptr->r.record.p.frmask, t, 1);
2513 set_imask (region, ptr->r.record.p.grmask, t, 2);
2514 break;
2515 case fr_mem:
2516 if (!region)
2517 {
2518 as_bad ("fr_mem record before region record!\n");
2519 return;
2520 }
2521 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2522 set_imask (region, ptr->r.record.p.rmask, t, 1);
2523 break;
2524 case gr_mem:
2525 if (!region)
2526 {
2527 as_bad ("gr_mem record before region record!\n");
2528 return;
2529 }
2530 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2531 set_imask (region, ptr->r.record.p.rmask, t, 2);
2532 break;
2533 case br_mem:
2534 if (!region)
2535 {
2536 as_bad ("br_mem record before region record!\n");
2537 return;
2538 }
2539 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2540 set_imask (region, ptr->r.record.p.brmask, t, 3);
2541 break;
2542
2543 case gr_gr:
2544 if (!region)
2545 {
2546 as_bad ("gr_gr record before region record!\n");
2547 return;
2548 }
197865e8 2549 set_imask (region, ptr->r.record.p.grmask, t, 2);
e0c9811a
JW		 2550 break;
2551 case br_gr:
2552 if (!region)
2553 {
2554 as_bad ("br_gr record before region record!\n");
2555 return;
2556 }
197865e8 2557 set_imask (region, ptr->r.record.p.brmask, t, 3);
e0c9811a
JW		 2558 break;
2559
2560 default:
2561 break;
800eeca4
JW		 2562 }
2563 }
2564}
2565
2566/* Generate an unwind image from a record list. Returns the number of
2567 bytes in the resulting image. The memory image itselof is returned
2568 in the 'ptr' parameter. */
2569static int
2570output_unw_records (list, ptr)
2571 unw_rec_list *list;
2572 void **ptr;
2573{
2574 int size, x, extra = 0;
2575 unsigned char *mem;
2576
2577 fixup_unw_records (list);
2578 size = calc_record_size (list);
2579
2580 /* pad to 8 byte boundry. */
2581 x = size % 8;
2582 if (x != 0)
2583 extra = 8 - x;
2584 /* Add 8 for the header + 8 more bytes for the personality offset. */
2585 mem = xmalloc (size + extra + 16);
2586
2587 vbyte_mem_ptr = mem + 8;
2588 /* Clear the padding area and personality. */
2589 memset (mem + 8 + size, 0 , extra + 8);
2590 /* Initialize the header area. */
efcc5914
JW		 2591 md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
2592 | (unwind.personality_routine
2593 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2594 : 0)
e4c58b25
JW		 2595 | ((size + extra) / 8)), /* length (dwords) */
2596 8);
800eeca4
JW		 2597
2598 process_unw_records (list, output_vbyte_mem);
2599
2600 *ptr = mem;
2601 return size + extra + 16;
2602}
2603
e0c9811a
JW		 2604static int
2605convert_expr_to_ab_reg (e, ab, regp)
2606 expressionS *e;
2607 unsigned int *ab;
2608 unsigned int *regp;
2609{
2610 unsigned int reg;
2611
2612 if (e->X_op != O_register)
2613 return 0;
2614
2615 reg = e->X_add_number;
2616 if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
2617 {
2618 *ab = 0;
2619 *regp = reg - REG_GR;
2620 }
2621 else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
2622 || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
2623 {
2624 *ab = 1;
2625 *regp = reg - REG_FR;
2626 }
2627 else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
2628 {
2629 *ab = 2;
2630 *regp = reg - REG_BR;
2631 }
2632 else
2633 {
2634 *ab = 3;
2635 switch (reg)
2636 {
2637 case REG_PR: *regp = 0; break;
2638 case REG_PSP: *regp = 1; break;
2639 case REG_PRIUNAT: *regp = 2; break;
2640 case REG_BR + 0: *regp = 3; break;
2641 case REG_AR + AR_BSP: *regp = 4; break;
2642 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2643 case REG_AR + AR_RNAT: *regp = 6; break;
2644 case REG_AR + AR_UNAT: *regp = 7; break;
2645 case REG_AR + AR_FPSR: *regp = 8; break;
2646 case REG_AR + AR_PFS: *regp = 9; break;
2647 case REG_AR + AR_LC: *regp = 10; break;
2648
2649 default:
2650 return 0;
2651 }
2652 }
2653 return 1;
197865e8 2654}
e0c9811a
JW		 2655
2656static int
2657convert_expr_to_xy_reg (e, xy, regp)
2658 expressionS *e;
2659 unsigned int *xy;
2660 unsigned int *regp;
2661{
2662 unsigned int reg;
2663
2664 if (e->X_op != O_register)
2665 return 0;
2666
2667 reg = e->X_add_number;
2668
2669 if (reg >= REG_GR && reg <= REG_GR + 127)
2670 {
2671 *xy = 0;
2672 *regp = reg - REG_GR;
2673 }
2674 else if (reg >= REG_FR && reg <= REG_FR + 127)
2675 {
2676 *xy = 1;
2677 *regp = reg - REG_FR;
2678 }
2679 else if (reg >= REG_BR && reg <= REG_BR + 7)
2680 {
2681 *xy = 2;
2682 *regp = reg - REG_BR;
2683 }
2684 else
2685 return -1;
2686 return 1;
197865e8 2687}
e0c9811a 2688
800eeca4
JW		 2689static void
2690dot_radix (dummy)
2691 int dummy;
2692{
2693 int radix;
2694
2695 SKIP_WHITESPACE ();
2696 radix = *input_line_pointer++;
2697
2698 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2699 {
2700 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2701 ignore_rest_of_line ();
2702 return;
2703 }
2704}
2705
2706/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2707static void
2708dot_special_section (which)
2709 int which;
2710{
2711 set_section ((char *) special_section_name[which]);
2712}
2713
2714static void
2715add_unwind_entry (ptr)
2716 unw_rec_list *ptr;
2717{
e0c9811a
JW		 2718 if (unwind.tail)
2719 unwind.tail->next = ptr;
800eeca4 2720 else
e0c9811a
JW		 2721 unwind.list = ptr;
2722 unwind.tail = ptr;
800eeca4
JW		 2723
2724 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW		 2725 if (unwind.current_entry == NULL)
2726 unwind.current_entry = ptr;
800eeca4
JW		 2727}
2728
197865e8 2729static void
800eeca4
JW		 2730dot_fframe (dummy)
2731 int dummy;
2732{
2733 expressionS e;
e0c9811a 2734
800eeca4 2735 parse_operand (&e);
197865e8 2736
800eeca4
JW		 2737 if (e.X_op != O_constant)
2738 as_bad ("Operand to .fframe must be a constant");
2739 else
e0c9811a
JW		 2740 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2741}
2742
197865e8 2743static void
e0c9811a
JW		 2744dot_vframe (dummy)
2745 int dummy;
2746{
2747 expressionS e;
2748 unsigned reg;
2749
2750 parse_operand (&e);
2751 reg = e.X_add_number - REG_GR;
2752 if (e.X_op == O_register && reg < 128)
800eeca4 2753 {
e0c9811a 2754 add_unwind_entry (output_mem_stack_v ());
30d25259
RH		 2755 if (! (unwind.prologue_mask & 2))
2756 add_unwind_entry (output_psp_gr (reg));
800eeca4 2757 }
e0c9811a
JW		 2758 else
2759 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW		 2760}
2761
197865e8 2762static void
e0c9811a 2763dot_vframesp (dummy)
800eeca4
JW		 2764 int dummy;
2765{
e0c9811a
JW		 2766 expressionS e;
2767
2768 parse_operand (&e);
2769 if (e.X_op == O_constant)
2770 {
2771 add_unwind_entry (output_mem_stack_v ());
2772 add_unwind_entry (output_psp_sprel (e.X_add_number));
2773 }
2774 else
2775 as_bad ("First operand to .vframesp must be a general register");
2776}
2777
197865e8 2778static void
e0c9811a
JW		 2779dot_vframepsp (dummy)
2780 int dummy;
2781{
2782 expressionS e;
2783
2784 parse_operand (&e);
2785 if (e.X_op == O_constant)
2786 {
2787 add_unwind_entry (output_mem_stack_v ());
2788 add_unwind_entry (output_psp_sprel (e.X_add_number));
2789 }
2790 else
2791 as_bad ("First operand to .vframepsp must be a general register");
800eeca4
JW		 2792}
2793
197865e8 2794static void
800eeca4
JW		 2795dot_save (dummy)
2796 int dummy;
2797{
2798 expressionS e1, e2;
2799 int sep;
2800 int reg1, reg2;
2801
2802 sep = parse_operand (&e1);
2803 if (sep != ',')
2804 as_bad ("No second operand to .save");
2805 sep = parse_operand (&e2);
2806
e0c9811a 2807 reg1 = e1.X_add_number;
800eeca4 2808 reg2 = e2.X_add_number - REG_GR;
197865e8 2809
800eeca4 2810 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 2811 if (e1.X_op == O_register)
800eeca4
JW		 2812 {
2813 if (e2.X_op == O_register && reg2 >=0 && reg2 < 128)
2814 {
2815 switch (reg1)
2816 {
e0c9811a 2817 case REG_AR + AR_BSP:
800eeca4
JW		 2818 add_unwind_entry (output_bsp_when ());
2819 add_unwind_entry (output_bsp_gr (reg2));
2820 break;
e0c9811a 2821 case REG_AR + AR_BSPSTORE:
800eeca4
JW		 2822 add_unwind_entry (output_bspstore_when ());
2823 add_unwind_entry (output_bspstore_gr (reg2));
2824 break;
e0c9811a 2825 case REG_AR + AR_RNAT:
800eeca4
JW		 2826 add_unwind_entry (output_rnat_when ());
2827 add_unwind_entry (output_rnat_gr (reg2));
2828 break;
e0c9811a 2829 case REG_AR+AR_UNAT:
800eeca4
JW		 2830 add_unwind_entry (output_unat_when ());
2831 add_unwind_entry (output_unat_gr (reg2));
2832 break;
e0c9811a 2833 case REG_AR+AR_FPSR:
800eeca4
JW		 2834 add_unwind_entry (output_fpsr_when ());
2835 add_unwind_entry (output_fpsr_gr (reg2));
2836 break;
e0c9811a 2837 case REG_AR+AR_PFS:
800eeca4 2838 add_unwind_entry (output_pfs_when ());
30d25259
RH		 2839 if (! (unwind.prologue_mask & 4))
2840 add_unwind_entry (output_pfs_gr (reg2));
800eeca4 2841 break;
e0c9811a 2842 case REG_AR+AR_LC:
800eeca4
JW		 2843 add_unwind_entry (output_lc_when ());
2844 add_unwind_entry (output_lc_gr (reg2));
2845 break;
e0c9811a 2846 case REG_BR:
800eeca4 2847 add_unwind_entry (output_rp_when ());
30d25259
RH		 2848 if (! (unwind.prologue_mask & 8))
2849 add_unwind_entry (output_rp_gr (reg2));
800eeca4 2850 break;
e0c9811a
JW		 2851 case REG_PR:
2852 add_unwind_entry (output_preds_when ());
30d25259
RH		 2853 if (! (unwind.prologue_mask & 1))
2854 add_unwind_entry (output_preds_gr (reg2));
e0c9811a
JW		 2855 break;
2856 case REG_PRIUNAT:
2857 add_unwind_entry (output_priunat_when_gr ());
2858 add_unwind_entry (output_priunat_gr (reg2));
2859 break;
800eeca4 2860 default:
e0c9811a 2861 as_bad ("First operand not a valid register");
800eeca4
JW		 2862 }
2863 }
2864 else
2865 as_bad (" Second operand not a valid register");
2866 }
2867 else
e0c9811a 2868 as_bad ("First operand not a register");
800eeca4
JW		 2869}
2870
197865e8 2871static void
800eeca4
JW		 2872dot_restore (dummy)
2873 int dummy;
2874{
e0c9811a
JW		 2875 expressionS e1, e2;
2876 unsigned long ecount = 0;
2877 int sep;
2878
2879 sep = parse_operand (&e1);
2880 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2881 {
2882 as_bad ("First operand to .restore must be stack pointer (sp)");
2883 return;
2884 }
2885
2886 if (sep == ',')
2887 {
2888 parse_operand (&e2);
2889 if (e1.X_op != O_constant)
2890 {
2891 as_bad ("Second operand to .restore must be constant");
2892 return;
2893 }
2894 ecount = e1.X_op;
2895 }
2896 add_unwind_entry (output_epilogue (ecount));
2897}
2898
197865e8 2899static void
e0c9811a
JW		 2900dot_restorereg (dummy)
2901 int dummy;
2902{
2903 unsigned int ab, reg;
2904 expressionS e;
2905
2906 parse_operand (&e);
2907
2908 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
2909 {
2910 as_bad ("First operand to .restorereg must be a preserved register");
2911 return;
2912 }
2913 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
2914}
2915
197865e8 2916static void
e0c9811a
JW		 2917dot_restorereg_p (dummy)
2918 int dummy;
2919{
2920 unsigned int qp, ab, reg;
2921 expressionS e1, e2;
2922 int sep;
2923
2924 sep = parse_operand (&e1);
2925 if (sep != ',')
2926 {
2927 as_bad ("No second operand to .restorereg.p");
2928 return;
2929 }
2930
2931 parse_operand (&e2);
2932
2933 qp = e1.X_add_number - REG_P;
2934 if (e1.X_op != O_register || qp > 63)
2935 {
2936 as_bad ("First operand to .restorereg.p must be a predicate");
2937 return;
2938 }
2939
2940 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
2941 {
2942 as_bad ("Second operand to .restorereg.p must be a preserved register");
2943 return;
2944 }
2945 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW		 2946}
2947
2948static int
2949generate_unwind_image ()
2950{
2951 int size;
2952 unsigned char *unw_rec;
800eeca4 2953
10850f29
JW		 2954 /* Force out pending instructions, to make sure all unwind records have
2955 a valid slot_number field. */
2956 ia64_flush_insns ();
2957
800eeca4 2958 /* Generate the unwind record. */
150f24a2 2959 size = output_unw_records (unwind.list, (void **) &unw_rec);
e0c9811a
JW		 2960 if (size % 8 != 0)
2961 as_bad ("Unwind record is not a multiple of 8 bytes.");
800eeca4
JW		 2962
2963 /* If there are unwind records, switch sections, and output the info. */
2964 if (size != 0)
2965 {
800eeca4 2966 unsigned char *where;
800eeca4 2967 expressionS exp;
800eeca4
JW		 2968 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
2969
2970 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 2971 unwind.info = expr_build_dot ();
800eeca4
JW		 2972
2973 where = (unsigned char *)frag_more (size);
2974
2975 /* Issue a label for this address, and keep track of it to put it
2976 in the unwind section. */
2977
2978 /* Copy the information from the unwind record into this section. The
2979 data is already in the correct byte order. */
2980 memcpy (where, unw_rec, size);
2981 /* Add the personality address to the image. */
e0c9811a 2982 if (unwind.personality_routine != 0)
800eeca4
JW		 2983 {
2984 exp.X_op = O_symbol;
e0c9811a 2985 exp.X_add_symbol = unwind.personality_routine;
800eeca4
JW		 2986 exp.X_add_number = 0;
2987 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
2988 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
e0c9811a 2989 unwind.personality_routine = 0;
800eeca4
JW		 2990 }
2991 obj_elf_previous (0);
2992 }
2993
e0c9811a
JW		 2994 free_list_records (unwind.list);
2995 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW		 2996
2997 return size;
2998}
2999
197865e8 3000static void
800eeca4
JW		 3001dot_handlerdata (dummy)
3002 int dummy;
3003{
3004 generate_unwind_image ();
e0c9811a 3005 demand_empty_rest_of_line ();
800eeca4
JW		 3006}
3007
197865e8 3008static void
800eeca4
JW		 3009dot_unwentry (dummy)
3010 int dummy;
3011{
e0c9811a 3012 demand_empty_rest_of_line ();
800eeca4
JW		 3013}
3014
197865e8 3015static void
800eeca4
JW		 3016dot_altrp (dummy)
3017 int dummy;
3018{
e0c9811a
JW		 3019 expressionS e;
3020 unsigned reg;
3021
3022 parse_operand (&e);
3023 reg = e.X_add_number - REG_BR;
3024 if (e.X_op == O_register && reg < 8)
3025 add_unwind_entry (output_rp_br (reg));
3026 else
3027 as_bad ("First operand not a valid branch register");
800eeca4
JW		 3028}
3029
197865e8 3030static void
e0c9811a
JW		 3031dot_savemem (psprel)
3032 int psprel;
800eeca4
JW		 3033{
3034 expressionS e1, e2;
3035 int sep;
3036 int reg1, val;
3037
3038 sep = parse_operand (&e1);
3039 if (sep != ',')
e0c9811a 3040 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW		 3041 sep = parse_operand (&e2);
3042
e0c9811a 3043 reg1 = e1.X_add_number;
800eeca4 3044 val = e2.X_add_number;
197865e8 3045
800eeca4 3046 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3047 if (e1.X_op == O_register)
800eeca4
JW		 3048 {
3049 if (e2.X_op == O_constant)
3050 {
3051 switch (reg1)
3052 {
e0c9811a 3053 case REG_AR + AR_BSP:
800eeca4 3054 add_unwind_entry (output_bsp_when ());
e0c9811a
JW		 3055 add_unwind_entry ((psprel
3056 ? output_bsp_psprel
3057 : output_bsp_sprel) (val));
800eeca4 3058 break;
e0c9811a 3059 case REG_AR + AR_BSPSTORE:
800eeca4 3060 add_unwind_entry (output_bspstore_when ());
e0c9811a
JW		 3061 add_unwind_entry ((psprel
3062 ? output_bspstore_psprel
3063 : output_bspstore_sprel) (val));
800eeca4 3064 break;
e0c9811a 3065 case REG_AR + AR_RNAT:
800eeca4 3066 add_unwind_entry (output_rnat_when ());
e0c9811a
JW		 3067 add_unwind_entry ((psprel
3068 ? output_rnat_psprel
3069 : output_rnat_sprel) (val));
800eeca4 3070 break;
e0c9811a 3071 case REG_AR + AR_UNAT:
800eeca4 3072 add_unwind_entry (output_unat_when ());
e0c9811a
JW		 3073 add_unwind_entry ((psprel
3074 ? output_unat_psprel
3075 : output_unat_sprel) (val));
800eeca4 3076 break;
e0c9811a 3077 case REG_AR + AR_FPSR:
800eeca4 3078 add_unwind_entry (output_fpsr_when ());
e0c9811a
JW		 3079 add_unwind_entry ((psprel
3080 ? output_fpsr_psprel
3081 : output_fpsr_sprel) (val));
800eeca4 3082 break;
e0c9811a 3083 case REG_AR + AR_PFS:
800eeca4 3084 add_unwind_entry (output_pfs_when ());
e0c9811a
JW		 3085 add_unwind_entry ((psprel
3086 ? output_pfs_psprel
3087 : output_pfs_sprel) (val));
800eeca4 3088 break;
e0c9811a 3089 case REG_AR + AR_LC:
800eeca4 3090 add_unwind_entry (output_lc_when ());
e0c9811a
JW		 3091 add_unwind_entry ((psprel
3092 ? output_lc_psprel
3093 : output_lc_sprel) (val));
800eeca4 3094 break;
e0c9811a 3095 case REG_BR:
800eeca4 3096 add_unwind_entry (output_rp_when ());
e0c9811a
JW		 3097 add_unwind_entry ((psprel
3098 ? output_rp_psprel
3099 : output_rp_sprel) (val));
800eeca4 3100 break;
e0c9811a 3101 case REG_PR:
800eeca4 3102 add_unwind_entry (output_preds_when ());
e0c9811a
JW		 3103 add_unwind_entry ((psprel
3104 ? output_preds_psprel
3105 : output_preds_sprel) (val));
3106 break;
3107 case REG_PRIUNAT:
3108 add_unwind_entry (output_priunat_when_mem ());
3109 add_unwind_entry ((psprel
3110 ? output_priunat_psprel
3111 : output_priunat_sprel) (val));
800eeca4
JW		 3112 break;
3113 default:
e0c9811a 3114 as_bad ("First operand not a valid register");
800eeca4
JW		 3115 }
3116 }
3117 else
3118 as_bad (" Second operand not a valid constant");
3119 }
3120 else
e0c9811a 3121 as_bad ("First operand not a register");
800eeca4
JW		 3122}
3123
197865e8 3124static void
800eeca4
JW		 3125dot_saveg (dummy)
3126 int dummy;
3127{
3128 expressionS e1, e2;
3129 int sep;
3130 sep = parse_operand (&e1);
3131 if (sep == ',')
3132 parse_operand (&e2);
197865e8 3133
800eeca4
JW		 3134 if (e1.X_op != O_constant)
3135 as_bad ("First operand to .save.g must be a constant.");
3136 else
3137 {
3138 int grmask = e1.X_add_number;
3139 if (sep != ',')
3140 add_unwind_entry (output_gr_mem (grmask));
3141 else
3142 {
3143 int reg = e2.X_add_number - REG_GR;
3144 if (e2.X_op == O_register && reg >=0 && reg < 128)
3145 add_unwind_entry (output_gr_gr (grmask, reg));
3146 else
3147 as_bad ("Second operand is an invalid register.");
3148 }
3149 }
3150}
3151
197865e8 3152static void
800eeca4
JW		 3153dot_savef (dummy)
3154 int dummy;
3155{
e0c9811a 3156 expressionS e1;
800eeca4
JW		 3157 int sep;
3158 sep = parse_operand (&e1);
197865e8 3159
800eeca4
JW		 3160 if (e1.X_op != O_constant)
3161 as_bad ("Operand to .save.f must be a constant.");
3162 else
e0c9811a 3163 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW		 3164}
3165
197865e8 3166static void
800eeca4
JW		 3167dot_saveb (dummy)
3168 int dummy;
3169{
e0c9811a
JW		 3170 expressionS e1, e2;
3171 unsigned int reg;
3172 unsigned char sep;
3173 int brmask;
3174
800eeca4 3175 sep = parse_operand (&e1);
800eeca4 3176 if (e1.X_op != O_constant)
800eeca4 3177 {
e0c9811a
JW		 3178 as_bad ("First operand to .save.b must be a constant.");
3179 return;
800eeca4 3180 }
e0c9811a
JW		 3181 brmask = e1.X_add_number;
3182
3183 if (sep == ',')
3184 {
3185 sep = parse_operand (&e2);
3186 reg = e2.X_add_number - REG_GR;
3187 if (e2.X_op != O_register || reg > 127)
3188 {
3189 as_bad ("Second operand to .save.b must be a general register.");
3190 return;
3191 }
3192 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3193 }
3194 else
3195 add_unwind_entry (output_br_mem (brmask));
3196
3197 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3198 ignore_rest_of_line ();
800eeca4
JW		 3199}
3200
197865e8 3201static void
800eeca4
JW		 3202dot_savegf (dummy)
3203 int dummy;
3204{
3205 expressionS e1, e2;
3206 int sep;
3207 sep = parse_operand (&e1);
3208 if (sep == ',')
3209 parse_operand (&e2);
197865e8 3210
800eeca4
JW		 3211 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3212 as_bad ("Both operands of .save.gf must be constants.");
3213 else
3214 {
3215 int grmask = e1.X_add_number;
3216 int frmask = e2.X_add_number;
3217 add_unwind_entry (output_frgr_mem (grmask, frmask));
3218 }
3219}
3220
197865e8 3221static void
800eeca4
JW		 3222dot_spill (dummy)
3223 int dummy;
3224{
3225 expressionS e;
e0c9811a
JW		 3226 unsigned char sep;
3227
3228 sep = parse_operand (&e);
3229 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3230 ignore_rest_of_line ();
197865e8 3231
800eeca4
JW		 3232 if (e.X_op != O_constant)
3233 as_bad ("Operand to .spill must be a constant");
3234 else
e0c9811a
JW		 3235 add_unwind_entry (output_spill_base (e.X_add_number));
3236}
3237
3238static void
3239dot_spillreg (dummy)
3240 int dummy;
3241{
3242 int sep, ab, xy, reg, treg;
3243 expressionS e1, e2;
3244
3245 sep = parse_operand (&e1);
3246 if (sep != ',')
3247 {
3248 as_bad ("No second operand to .spillreg");
3249 return;
3250 }
3251
3252 parse_operand (&e2);
3253
3254 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3255 {
e0c9811a
JW		 3256 as_bad ("First operand to .spillreg must be a preserved register");
3257 return;
800eeca4 3258 }
e0c9811a
JW		 3259
3260 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3261 {
3262 as_bad ("Second operand to .spillreg must be a register");
3263 return;
3264 }
3265
3266 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3267}
3268
3269static void
3270dot_spillmem (psprel)
3271 int psprel;
3272{
3273 expressionS e1, e2;
3274 int sep, ab, reg;
3275
3276 sep = parse_operand (&e1);
3277 if (sep != ',')
3278 {
3279 as_bad ("Second operand missing");
3280 return;
3281 }
3282
3283 parse_operand (&e2);
3284
3285 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3286 {
3287 as_bad ("First operand to .spill%s must be a preserved register",
3288 psprel ? "psp" : "sp");
3289 return;
3290 }
3291
3292 if (e2.X_op != O_constant)
3293 {
3294 as_bad ("Second operand to .spill%s must be a constant",
3295 psprel ? "psp" : "sp");
3296 return;
3297 }
3298
3299 if (psprel)
3300 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3301 else
3302 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3303}
3304
3305static void
3306dot_spillreg_p (dummy)
3307 int dummy;
3308{
3309 int sep, ab, xy, reg, treg;
3310 expressionS e1, e2, e3;
3311 unsigned int qp;
3312
3313 sep = parse_operand (&e1);
3314 if (sep != ',')
3315 {
3316 as_bad ("No second and third operand to .spillreg.p");
3317 return;
3318 }
3319
3320 sep = parse_operand (&e2);
3321 if (sep != ',')
3322 {
3323 as_bad ("No third operand to .spillreg.p");
3324 return;
3325 }
3326
3327 parse_operand (&e3);
3328
3329 qp = e1.X_add_number - REG_P;
3330
3331 if (e1.X_op != O_register || qp > 63)
3332 {
3333 as_bad ("First operand to .spillreg.p must be a predicate");
3334 return;
3335 }
3336
3337 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3338 {
3339 as_bad ("Second operand to .spillreg.p must be a preserved register");
3340 return;
3341 }
3342
3343 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3344 {
3345 as_bad ("Third operand to .spillreg.p must be a register");
3346 return;
3347 }
3348
3349 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3350}
3351
3352static void
3353dot_spillmem_p (psprel)
3354 int psprel;
3355{
3356 expressionS e1, e2, e3;
3357 int sep, ab, reg;
3358 unsigned int qp;
3359
3360 sep = parse_operand (&e1);
3361 if (sep != ',')
3362 {
3363 as_bad ("Second operand missing");
3364 return;
3365 }
3366
3367 parse_operand (&e2);
3368 if (sep != ',')
3369 {
3370 as_bad ("Second operand missing");
3371 return;
3372 }
3373
3374 parse_operand (&e3);
3375
3376 qp = e1.X_add_number - REG_P;
3377 if (e1.X_op != O_register || qp > 63)
3378 {
3379 as_bad ("First operand to .spill%s_p must be a predicate",
3380 psprel ? "psp" : "sp");
3381 return;
3382 }
3383
3384 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3385 {
3386 as_bad ("Second operand to .spill%s_p must be a preserved register",
3387 psprel ? "psp" : "sp");
3388 return;
3389 }
3390
3391 if (e3.X_op != O_constant)
3392 {
3393 as_bad ("Third operand to .spill%s_p must be a constant",
3394 psprel ? "psp" : "sp");
3395 return;
3396 }
3397
3398 if (psprel)
3399 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3400 else
3401 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3402}
3403
3404static void
3405dot_label_state (dummy)
3406 int dummy;
3407{
3408 expressionS e;
3409
3410 parse_operand (&e);
3411 if (e.X_op != O_constant)
3412 {
3413 as_bad ("Operand to .label_state must be a constant");
3414 return;
3415 }
3416 add_unwind_entry (output_label_state (e.X_add_number));
3417}
3418
3419static void
3420dot_copy_state (dummy)
3421 int dummy;
3422{
3423 expressionS e;
3424
3425 parse_operand (&e);
3426 if (e.X_op != O_constant)
3427 {
3428 as_bad ("Operand to .copy_state must be a constant");
3429 return;
3430 }
3431 add_unwind_entry (output_copy_state (e.X_add_number));
800eeca4
JW		 3432}
3433
197865e8 3434static void
800eeca4
JW		 3435dot_unwabi (dummy)
3436 int dummy;
3437{
e0c9811a
JW		 3438 expressionS e1, e2;
3439 unsigned char sep;
3440
3441 sep = parse_operand (&e1);
3442 if (sep != ',')
3443 {
3444 as_bad ("Second operand to .unwabi missing");
3445 return;
3446 }
3447 sep = parse_operand (&e2);
3448 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3449 ignore_rest_of_line ();
3450
3451 if (e1.X_op != O_constant)
3452 {
3453 as_bad ("First operand to .unwabi must be a constant");
3454 return;
3455 }
3456
3457 if (e2.X_op != O_constant)
3458 {
3459 as_bad ("Second operand to .unwabi must be a constant");
3460 return;
3461 }
3462
3463 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW		 3464}
3465
197865e8 3466static void
800eeca4
JW		 3467dot_personality (dummy)
3468 int dummy;
3469{
3470 char *name, *p, c;
3471 SKIP_WHITESPACE ();
3472 name = input_line_pointer;
3473 c = get_symbol_end ();
3474 p = input_line_pointer;
e0c9811a 3475 unwind.personality_routine = symbol_find_or_make (name);
800eeca4
JW		 3476 *p = c;
3477 SKIP_WHITESPACE ();
3478 demand_empty_rest_of_line ();
3479}
3480
3481static void
3482dot_proc (dummy)
3483 int dummy;
3484{
3485 char *name, *p, c;
3486 symbolS *sym;
3487
e0c9811a
JW		 3488 unwind.proc_start = expr_build_dot ();
3489 /* Parse names of main and alternate entry points and mark them as
800eeca4
JW		 3490 function symbols: */
3491 while (1)
3492 {
3493 SKIP_WHITESPACE ();
3494 name = input_line_pointer;
3495 c = get_symbol_end ();
3496 p = input_line_pointer;
3497 sym = symbol_find_or_make (name);
e0c9811a 3498 if (unwind.proc_start == 0)
800eeca4 3499 {
e0c9811a 3500 unwind.proc_start = sym;
800eeca4
JW		 3501 }
3502 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3503 *p = c;
3504 SKIP_WHITESPACE ();
3505 if (*input_line_pointer != ',')
3506 break;
3507 ++input_line_pointer;
3508 }
3509 demand_empty_rest_of_line ();
3510 ia64_do_align (16);
3511
e0c9811a
JW		 3512 unwind.list = unwind.tail = unwind.current_entry = NULL;
3513 unwind.personality_routine = 0;
800eeca4
JW		 3514}
3515
3516static void
3517dot_body (dummy)
3518 int dummy;
3519{
e0c9811a 3520 unwind.prologue = 0;
30d25259
RH		 3521 unwind.prologue_mask = 0;
3522
800eeca4 3523 add_unwind_entry (output_body ());
e0c9811a 3524 demand_empty_rest_of_line ();
800eeca4
JW		 3525}
3526
3527static void
3528dot_prologue (dummy)
3529 int dummy;
3530{
e0c9811a 3531 unsigned char sep;
30d25259 3532 int mask = 0, grsave;
e0c9811a 3533
e0c9811a 3534 if (!is_it_end_of_statement ())
800eeca4
JW		 3535 {
3536 expressionS e1, e2;
800eeca4
JW		 3537 sep = parse_operand (&e1);
3538 if (sep != ',')
3539 as_bad ("No second operand to .prologue");
3540 sep = parse_operand (&e2);
e0c9811a
JW		 3541 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3542 ignore_rest_of_line ();
800eeca4
JW		 3543
3544 if (e1.X_op == O_constant)
3545 {
30d25259
RH		 3546 mask = e1.X_add_number;
3547
800eeca4 3548 if (e2.X_op == O_constant)
30d25259
RH		 3549 grsave = e2.X_add_number;
3550 else if (e2.X_op == O_register
3551 && (grsave = e2.X_add_number - REG_GR) < 128)
3552 ;
800eeca4 3553 else
30d25259
RH		 3554 as_bad ("Second operand not a constant or general register");
3555
3556 add_unwind_entry (output_prologue_gr (mask, grsave));
800eeca4
JW		 3557 }
3558 else
3559 as_bad ("First operand not a constant");
3560 }
3561 else
3562 add_unwind_entry (output_prologue ());
30d25259
RH		 3563
3564 unwind.prologue = 1;
3565 unwind.prologue_mask = mask;
800eeca4
JW		 3566}
3567
3568static void
3569dot_endp (dummy)
3570 int dummy;
3571{
3572 expressionS e;
3573 unsigned char *ptr;
800eeca4
JW		 3574 long where;
3575 segT saved_seg;
3576 subsegT saved_subseg;
3577
3578 saved_seg = now_seg;
3579 saved_subseg = now_subseg;
3580
3581 expression (&e);
3582 demand_empty_rest_of_line ();
3583
3584 insn_group_break (1, 0, 0);
800eeca4
JW		 3585
3586 /* If there was a .handlerdata, we haven't generated an image yet. */
e0c9811a 3587 if (unwind.info == 0)
800eeca4
JW		 3588 {
3589 generate_unwind_image ();
3590 }
3591
3592 subseg_set (md.last_text_seg, 0);
e0c9811a 3593 unwind.proc_end = expr_build_dot ();
800eeca4
JW		 3594
3595 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3596 ptr = frag_more (24);
3597 where = frag_now_fix () - 24;
3598
3599 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3600 e.X_op = O_pseudo_fixup;
3601 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3602 e.X_add_number = 0;
e0c9811a 3603 e.X_add_symbol = unwind.proc_start;
800eeca4
JW		 3604 ia64_cons_fix_new (frag_now, where, 8, &e);
3605
3606 e.X_op = O_pseudo_fixup;
3607 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3608 e.X_add_number = 0;
e0c9811a 3609 e.X_add_symbol = unwind.proc_end;
800eeca4
JW		 3610 ia64_cons_fix_new (frag_now, where + 8, 8, &e);
3611
e0c9811a 3612 if (unwind.info != 0)
800eeca4
JW		 3613 {
3614 e.X_op = O_pseudo_fixup;
3615 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3616 e.X_add_number = 0;
e0c9811a 3617 e.X_add_symbol = unwind.info;
800eeca4
JW		 3618 ia64_cons_fix_new (frag_now, where + 16, 8, &e);
3619 }
3620 else
3621 md_number_to_chars (ptr + 16, 0, 8);
3622
3623 subseg_set (saved_seg, saved_subseg);
e0c9811a 3624 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW		 3625}
3626
3627static void
3628dot_template (template)
3629 int template;
3630{
3631 CURR_SLOT.user_template = template;
3632}
3633
3634static void
3635dot_regstk (dummy)
3636 int dummy;
3637{
3638 int ins, locs, outs, rots;
3639
3640 if (is_it_end_of_statement ())
3641 ins = locs = outs = rots = 0;
3642 else
3643 {
3644 ins = get_absolute_expression ();
3645 if (*input_line_pointer++ != ',')
3646 goto err;
3647 locs = get_absolute_expression ();
3648 if (*input_line_pointer++ != ',')
3649 goto err;
3650 outs = get_absolute_expression ();
3651 if (*input_line_pointer++ != ',')
3652 goto err;
3653 rots = get_absolute_expression ();
3654 }
3655 set_regstack (ins, locs, outs, rots);
3656 return;
3657
3658 err:
3659 as_bad ("Comma expected");
3660 ignore_rest_of_line ();
3661}
3662
3663static void
3664dot_rot (type)
3665 int type;
3666{
3667 unsigned num_regs, num_alloced = 0;
3668 struct dynreg **drpp, *dr;
3669 int ch, base_reg = 0;
3670 char *name, *start;
3671 size_t len;
3672
3673 switch (type)
3674 {
3675 case DYNREG_GR: base_reg = REG_GR + 32; break;
3676 case DYNREG_FR: base_reg = REG_FR + 32; break;
3677 case DYNREG_PR: base_reg = REG_P + 16; break;
3678 default: break;
3679 }
3680
3681 /* first, remove existing names from hash table: */
3682 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3683 {
3684 hash_delete (md.dynreg_hash, dr->name);
3685 dr->num_regs = 0;
3686 }
3687
3688 drpp = &md.dynreg[type];
3689 while (1)
3690 {
3691 start = input_line_pointer;
3692 ch = get_symbol_end ();
3693 *input_line_pointer = ch;
3694 len = (input_line_pointer - start);
3695
3696 SKIP_WHITESPACE ();
3697 if (*input_line_pointer != '[')
3698 {
3699 as_bad ("Expected '['");
3700 goto err;
3701 }
3702 ++input_line_pointer; /* skip '[' */
3703
3704 num_regs = get_absolute_expression ();
3705
3706 if (*input_line_pointer++ != ']')
3707 {
3708 as_bad ("Expected ']'");
3709 goto err;
3710 }
3711 SKIP_WHITESPACE ();
3712
3713 num_alloced += num_regs;
3714 switch (type)
3715 {
3716 case DYNREG_GR:
3717 if (num_alloced > md.rot.num_regs)
3718 {
3719 as_bad ("Used more than the declared %d rotating registers",
3720 md.rot.num_regs);
3721 goto err;
3722 }
3723 break;
3724 case DYNREG_FR:
3725 if (num_alloced > 96)
3726 {
3727 as_bad ("Used more than the available 96 rotating registers");
3728 goto err;
3729 }
3730 break;
3731 case DYNREG_PR:
3732 if (num_alloced > 48)
3733 {
3734 as_bad ("Used more than the available 48 rotating registers");
3735 goto err;
3736 }
3737 break;
3738
3739 default:
3740 break;
3741 }
3742
3743 name = obstack_alloc (&notes, len + 1);
3744 memcpy (name, start, len);
3745 name[len] = '\0';
3746
3747 if (!*drpp)
3748 {
3749 *drpp = obstack_alloc (&notes, sizeof (*dr));
3750 memset (*drpp, 0, sizeof (*dr));
3751 }
3752
3753 dr = *drpp;
3754 dr->name = name;
3755 dr->num_regs = num_regs;
3756 dr->base = base_reg;
3757 drpp = &dr->next;
3758 base_reg += num_regs;
3759
3760 if (hash_insert (md.dynreg_hash, name, dr))
3761 {
3762 as_bad ("Attempt to redefine register set `%s'", name);
3763 goto err;
3764 }
3765
3766 if (*input_line_pointer != ',')
3767 break;
3768 ++input_line_pointer; /* skip comma */
3769 SKIP_WHITESPACE ();
3770 }
3771 demand_empty_rest_of_line ();
3772 return;
3773
3774 err:
3775 ignore_rest_of_line ();
3776}
3777
3778static void
3779dot_byteorder (byteorder)
3780 int byteorder;
3781{
3782 target_big_endian = byteorder;
3783}
3784
3785static void
3786dot_psr (dummy)
3787 int dummy;
3788{
3789 char *option;
3790 int ch;
3791
3792 while (1)
3793 {
3794 option = input_line_pointer;
3795 ch = get_symbol_end ();
3796 if (strcmp (option, "lsb") == 0)
3797 md.flags &= ~EF_IA_64_BE;
3798 else if (strcmp (option, "msb") == 0)
3799 md.flags |= EF_IA_64_BE;
3800 else if (strcmp (option, "abi32") == 0)
3801 md.flags &= ~EF_IA_64_ABI64;
3802 else if (strcmp (option, "abi64") == 0)
3803 md.flags |= EF_IA_64_ABI64;
3804 else
3805 as_bad ("Unknown psr option `%s'", option);
3806 *input_line_pointer = ch;
3807
3808 SKIP_WHITESPACE ();
3809 if (*input_line_pointer != ',')
3810 break;
3811
3812 ++input_line_pointer;
3813 SKIP_WHITESPACE ();
3814 }
3815 demand_empty_rest_of_line ();
3816}
3817
3818static void
3819dot_alias (dummy)
3820 int dummy;
3821{
3822 as_bad (".alias not implemented yet");
3823}
3824
3825static void
3826dot_ln (dummy)
3827 int dummy;
3828{
3829 new_logical_line (0, get_absolute_expression ());
3830 demand_empty_rest_of_line ();
3831}
3832
3833static char*
3834parse_section_name ()
3835{
3836 char *name;
3837 int len;
3838
3839 SKIP_WHITESPACE ();
3840 if (*input_line_pointer != '"')
3841 {
3842 as_bad ("Missing section name");
3843 ignore_rest_of_line ();
3844 return 0;
3845 }
3846 name = demand_copy_C_string (&len);
3847 if (!name)
3848 {
3849 ignore_rest_of_line ();
3850 return 0;
3851 }
3852 SKIP_WHITESPACE ();
3853 if (*input_line_pointer != ',')
3854 {
3855 as_bad ("Comma expected after section name");
3856 ignore_rest_of_line ();
3857 return 0;
3858 }
3859 ++input_line_pointer; /* skip comma */
3860 return name;
3861}
3862
3863static void
3864dot_xdata (size)
3865 int size;
3866{
3867 char *name = parse_section_name ();
3868 if (!name)
3869 return;
3870
3871 set_section (name);
3872 cons (size);
3873 obj_elf_previous (0);
3874}
3875
3876/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3877static void
3878stmt_float_cons (kind)
3879 int kind;
3880{
3881 size_t size;
3882
3883 switch (kind)
3884 {
3885 case 'd': size = 8; break;
3886 case 'x': size = 10; break;
3887
3888 case 'f':
3889 default:
3890 size = 4;
3891 break;
3892 }
3893 ia64_do_align (size);
3894 float_cons (kind);
3895}
3896
3897static void
3898stmt_cons_ua (size)
3899 int size;
3900{
3901 int saved_auto_align = md.auto_align;
3902
3903 md.auto_align = 0;
3904 cons (size);
3905 md.auto_align = saved_auto_align;
3906}
3907
3908static void
3909dot_xfloat_cons (kind)
3910 int kind;
3911{
3912 char *name = parse_section_name ();
3913 if (!name)
3914 return;
3915
3916 set_section (name);
3917 stmt_float_cons (kind);
3918 obj_elf_previous (0);
3919}
3920
3921static void
3922dot_xstringer (zero)
3923 int zero;
3924{
3925 char *name = parse_section_name ();
3926 if (!name)
3927 return;
3928
3929 set_section (name);
3930 stringer (zero);
3931 obj_elf_previous (0);
3932}
3933
3934static void
3935dot_xdata_ua (size)
3936 int size;
3937{
3938 int saved_auto_align = md.auto_align;
3939 char *name = parse_section_name ();
3940 if (!name)
3941 return;
3942
3943 set_section (name);
3944 md.auto_align = 0;
3945 cons (size);
3946 md.auto_align = saved_auto_align;
3947 obj_elf_previous (0);
3948}
3949
3950static void
3951dot_xfloat_cons_ua (kind)
3952 int kind;
3953{
3954 int saved_auto_align = md.auto_align;
3955 char *name = parse_section_name ();
3956 if (!name)
3957 return;
3958
3959 set_section (name);
3960 md.auto_align = 0;
3961 stmt_float_cons (kind);
3962 md.auto_align = saved_auto_align;
3963 obj_elf_previous (0);
3964}
3965
3966/* .reg.val <regname>,value */
3967static void
3968dot_reg_val (dummy)
3969 int dummy;
3970{
3971 expressionS reg;
3972
3973 expression (&reg);
3974 if (reg.X_op != O_register)
3975 {
3976 as_bad (_("Register name expected"));
3977 ignore_rest_of_line ();
3978 }
3979 else if (*input_line_pointer++ != ',')
3980 {
3981 as_bad (_("Comma expected"));
3982 ignore_rest_of_line ();
3983 }
197865e8 3984 else
800eeca4
JW		 3985 {
3986 valueT value = get_absolute_expression ();
3987 int regno = reg.X_add_number;
3988 if (regno < REG_GR || regno > REG_GR+128)
3989 as_warn (_("Register value annotation ignored"));
3990 else
3991 {
3992 gr_values[regno-REG_GR].known = 1;
3993 gr_values[regno-REG_GR].value = value;
3994 gr_values[regno-REG_GR].path = md.path;
3995 }
3996 }
3997 demand_empty_rest_of_line ();
3998}
3999
197865e8 4000/* select dv checking mode
800eeca4
JW		 4001 .auto
4002 .explicit
4003 .default
4004
197865e8 4005 A stop is inserted when changing modes
800eeca4
JW		 4006 */
4007static void
4008dot_dv_mode (type)
4009 int type;
4010{
4011 if (md.manual_bundling)
4012 as_warn (_("Directive invalid within a bundle"));
4013
4014 if (type == 'E' || type == 'A')
4015 md.mode_explicitly_set = 0;
4016 else
4017 md.mode_explicitly_set = 1;
4018
4019 md.detect_dv = 1;
4020 switch (type)
4021 {
4022 case 'A':
4023 case 'a':
4024 if (md.explicit_mode)
4025 insn_group_break (1, 0, 0);
4026 md.explicit_mode = 0;
4027 break;
4028 case 'E':
4029 case 'e':
4030 if (!md.explicit_mode)
4031 insn_group_break (1, 0, 0);
4032 md.explicit_mode = 1;
4033 break;
4034 default:
4035 case 'd':
4036 if (md.explicit_mode != md.default_explicit_mode)
4037 insn_group_break (1, 0, 0);
4038 md.explicit_mode = md.default_explicit_mode;
4039 md.mode_explicitly_set = 0;
4040 break;
4041 }
4042}
4043
4044static void
4045print_prmask (mask)
4046 valueT mask;
4047{
4048 int regno;
4049 char *comma = "";
4050 for (regno = 0;regno < 64;regno++)
4051 {
197865e8 4052 if (mask & ((valueT) 1<<regno))
800eeca4
JW		 4053 {
4054 fprintf (stderr, "%s p%d", comma, regno);
4055 comma = ",";
4056 }
4057 }
4058}
4059
4060/*
4061 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4062 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4063 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4064 .pred.safe_across_calls p1 [, p2 [,...]]
4065 */
4066static void
4067dot_pred_rel (type)
4068 int type;
4069{
4070 valueT mask = 0;
4071 int count = 0;
4072 int p1 = -1, p2 = -1;
4073
4074 if (type == 0)
4075 {
4076 if (*input_line_pointer != '"')
4077 {
4078 as_bad (_("Missing predicate relation type"));
4079 ignore_rest_of_line ();
4080 return;
4081 }
197865e8 4082 else
800eeca4
JW		 4083 {
4084 int len;
4085 char *form = demand_copy_C_string (&len);
197865e8 4086 if (strcmp (form, "mutex") == 0)
800eeca4
JW		 4087 type = 'm';
4088 else if (strcmp (form, "clear") == 0)
4089 type = 'c';
4090 else if (strcmp (form, "imply") == 0)
4091 type = 'i';
197865e8 4092 else
800eeca4
JW		 4093 {
4094 as_bad (_("Unrecognized predicate relation type"));
4095 ignore_rest_of_line ();
4096 return;
4097 }
4098 }
4099 if (*input_line_pointer == ',')
4100 ++input_line_pointer;
4101 SKIP_WHITESPACE ();
4102 }
4103
4104 SKIP_WHITESPACE ();
4105 while (1)
4106 {
4107 valueT bit = 1;
4108 int regno;
197865e8 4109
800eeca4
JW		 4110 if (toupper (*input_line_pointer) != 'P'
4111 || (regno = atoi (++input_line_pointer)) < 0
4112 || regno > 63)
4113 {
4114 as_bad (_("Predicate register expected"));
4115 ignore_rest_of_line ();
4116 return;
4117 }
4118 while (isdigit (*input_line_pointer))
4119 ++input_line_pointer;
4120 if (p1 == -1)
4121 p1 = regno;
4122 else if (p2 == -1)
4123 p2 = regno;
4124 bit <<= regno;
4125 if (mask & bit)
4126 as_warn (_("Duplicate predicate register ignored"));
4127 mask |= bit; count++;
4128 /* see if it's a range */
4129 if (*input_line_pointer == '-')
4130 {
4131 valueT stop = 1;
4132 ++input_line_pointer;
4133
4134 if (toupper (*input_line_pointer) != 'P'
4135 || (regno = atoi (++input_line_pointer)) < 0
4136 || regno > 63)
4137 {
4138 as_bad (_("Predicate register expected"));
4139 ignore_rest_of_line ();
4140 return;
4141 }
4142 while (isdigit (*input_line_pointer))
4143 ++input_line_pointer;
4144 stop <<= regno;
4145 if (bit >= stop)
4146 {
4147 as_bad (_("Bad register range"));
4148 ignore_rest_of_line ();
4149 return;
4150 }
4151 while (bit < stop)
4152 {
4153 bit <<= 1;
4154 mask |= bit; count++;
4155 }
4156 SKIP_WHITESPACE ();
4157 }
4158 if (*input_line_pointer != ',')
4159 break;
4160 ++input_line_pointer;
4161 SKIP_WHITESPACE ();
4162 }
4163
4164 switch (type)
4165 {
4166 case 'c':
4167 if (count == 0)
197865e8 4168 mask = ~(valueT) 0;
800eeca4 4169 clear_qp_mutex (mask);
197865e8 4170 clear_qp_implies (mask, (valueT) 0);
800eeca4
JW		 4171 break;
4172 case 'i':
4173 if (count != 2 || p1 == -1 || p2 == -1)
4174 as_bad (_("Predicate source and target required"));
4175 else if (p1 == 0 || p2 == 0)
4176 as_bad (_("Use of p0 is not valid in this context"));
4177 else
4178 add_qp_imply (p1, p2);
4179 break;
4180 case 'm':
4181 if (count < 2)
4182 {
4183 as_bad (_("At least two PR arguments expected"));
4184 break;
4185 }
4186 else if (mask & 1)
4187 {
4188 as_bad (_("Use of p0 is not valid in this context"));
4189 break;
4190 }
4191 add_qp_mutex (mask);
4192 break;
4193 case 's':
4194 /* note that we don't override any existing relations */
4195 if (count == 0)
4196 {
4197 as_bad (_("At least one PR argument expected"));
4198 break;
4199 }
4200 if (md.debug_dv)
4201 {
4202 fprintf (stderr, "Safe across calls: ");
4203 print_prmask (mask);
4204 fprintf (stderr, "\n");
4205 }
4206 qp_safe_across_calls = mask;
4207 break;
4208 }
4209 demand_empty_rest_of_line ();
4210}
4211
4212/* .entry label [, label [, ...]]
4213 Hint to DV code that the given labels are to be considered entry points.
4214 Otherwise, only global labels are considered entry points.
4215 */
4216static void
4217dot_entry (dummy)
4218 int dummy;
4219{
4220 const char *err;
4221 char *name;
4222 int c;
4223 symbolS *symbolP;
4224
4225 do
4226 {
4227 name = input_line_pointer;
4228 c = get_symbol_end ();
4229 symbolP = symbol_find_or_make (name);
4230
4231 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4232 if (err)
4233 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4234 name, err);
4235
4236 *input_line_pointer = c;
4237 SKIP_WHITESPACE ();
4238 c = *input_line_pointer;
4239 if (c == ',')
4240 {
4241 input_line_pointer++;
4242 SKIP_WHITESPACE ();
4243 if (*input_line_pointer == '\n')
4244 c = '\n';
4245 }
4246 }
4247 while (c == ',');
4248
4249 demand_empty_rest_of_line ();
4250}
4251
197865e8 4252/* .mem.offset offset, base
800eeca4
JW		 4253 "base" is used to distinguish between offsets from a different base.
4254 */
4255static void
4256dot_mem_offset (dummy)
4257 int dummy;
4258{
4259 md.mem_offset.hint = 1;
4260 md.mem_offset.offset = get_absolute_expression ();
4261 if (*input_line_pointer != ',')
4262 {
4263 as_bad (_("Comma expected"));
4264 ignore_rest_of_line ();
4265 return;
4266 }
4267 ++input_line_pointer;
4268 md.mem_offset.base = get_absolute_expression ();
4269 demand_empty_rest_of_line ();
4270}
4271
4272/* ia64-specific pseudo-ops: */
4273const pseudo_typeS md_pseudo_table[] =
4274 {
4275 { "radix", dot_radix, 0 },
4276 { "lcomm", s_lcomm_bytes, 1 },
4277 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4278 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4279 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4280 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4281 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4282 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4283 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4284 { "proc", dot_proc, 0 },
4285 { "body", dot_body, 0 },
4286 { "prologue", dot_prologue, 0 },
4287 { "endp", dot_endp },
4288 { "file", dwarf2_directive_file },
4289 { "loc", dwarf2_directive_loc },
4290
4291 { "fframe", dot_fframe },
4292 { "vframe", dot_vframe },
e0c9811a
JW		 4293 { "vframesp", dot_vframesp },
4294 { "vframepsp", dot_vframepsp },
800eeca4
JW		 4295 { "save", dot_save },
4296 { "restore", dot_restore },
e0c9811a
JW		 4297 { "restorereg", dot_restorereg },
4298 { "restorereg.p", dot_restorereg_p },
800eeca4
JW		 4299 { "handlerdata", dot_handlerdata },
4300 { "unwentry", dot_unwentry },
e0c9811a
JW		 4301 { "altrp", dot_altrp },
4302 { "savesp", dot_savemem, 0 },
4303 { "savepsp", dot_savemem, 1 },
800eeca4
JW		 4304 { "save.g", dot_saveg },
4305 { "save.f", dot_savef },
4306 { "save.b", dot_saveb },
4307 { "save.gf", dot_savegf },
4308 { "spill", dot_spill },
e0c9811a
JW		 4309 { "spillreg", dot_spillreg },
4310 { "spillsp", dot_spillmem, 0 },
4311 { "spillpsp", dot_spillmem, 1 },
4312 { "spillreg.p", dot_spillreg_p },
4313 { "spillsp.p", dot_spillmem_p, 0 },
4314 { "spillpsp.p", dot_spillmem_p, 1 },
197865e8
KH		 4315 { "label_state", dot_label_state },
4316 { "copy_state", dot_copy_state },
800eeca4
JW		 4317 { "unwabi", dot_unwabi },
4318 { "personality", dot_personality },
4319#if 0
4320 { "estate", dot_estate },
4321#endif
4322 { "mii", dot_template, 0x0 },
4323 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4324 { "mlx", dot_template, 0x2 },
4325 { "mmi", dot_template, 0x4 },
4326 { "mfi", dot_template, 0x6 },
4327 { "mmf", dot_template, 0x7 },
4328 { "mib", dot_template, 0x8 },
4329 { "mbb", dot_template, 0x9 },
4330 { "bbb", dot_template, 0xb },
4331 { "mmb", dot_template, 0xc },
4332 { "mfb", dot_template, 0xe },
4333#if 0
4334 { "lb", dot_scope, 0 },
4335 { "le", dot_scope, 1 },
4336#endif
4337 { "align", s_align_bytes, 0 },
4338 { "regstk", dot_regstk, 0 },
4339 { "rotr", dot_rot, DYNREG_GR },
4340 { "rotf", dot_rot, DYNREG_FR },
4341 { "rotp", dot_rot, DYNREG_PR },
4342 { "lsb", dot_byteorder, 0 },
4343 { "msb", dot_byteorder, 1 },
4344 { "psr", dot_psr, 0 },
4345 { "alias", dot_alias, 0 },
4346 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4347
4348 { "xdata1", dot_xdata, 1 },
4349 { "xdata2", dot_xdata, 2 },
4350 { "xdata4", dot_xdata, 4 },
4351 { "xdata8", dot_xdata, 8 },
4352 { "xreal4", dot_xfloat_cons, 'f' },
4353 { "xreal8", dot_xfloat_cons, 'd' },
4354 { "xreal10", dot_xfloat_cons, 'x' },
4355 { "xstring", dot_xstringer, 0 },
4356 { "xstringz", dot_xstringer, 1 },
4357
4358 /* unaligned versions: */
4359 { "xdata2.ua", dot_xdata_ua, 2 },
4360 { "xdata4.ua", dot_xdata_ua, 4 },
4361 { "xdata8.ua", dot_xdata_ua, 8 },
4362 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4363 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4364 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4365
4366 /* annotations/DV checking support */
4367 { "entry", dot_entry, 0 },
4368 { "mem.offset", dot_mem_offset },
4369 { "pred.rel", dot_pred_rel, 0 },
4370 { "pred.rel.clear", dot_pred_rel, 'c' },
4371 { "pred.rel.imply", dot_pred_rel, 'i' },
4372 { "pred.rel.mutex", dot_pred_rel, 'm' },
4373 { "pred.safe_across_calls", dot_pred_rel, 's' },
4374 { "reg.val", dot_reg_val },
4375 { "auto", dot_dv_mode, 'a' },
4376 { "explicit", dot_dv_mode, 'e' },
4377 { "default", dot_dv_mode, 'd' },
4378
4379 { NULL, 0, 0 }
4380 };
4381
4382static const struct pseudo_opcode
4383 {
4384 const char *name;
4385 void (*handler) (int);
4386 int arg;
4387 }
4388pseudo_opcode[] =
4389 {
4390 /* these are more like pseudo-ops, but don't start with a dot */
4391 { "data1", cons, 1 },
4392 { "data2", cons, 2 },
4393 { "data4", cons, 4 },
4394 { "data8", cons, 8 },
4395 { "real4", stmt_float_cons, 'f' },
4396 { "real8", stmt_float_cons, 'd' },
4397 { "real10", stmt_float_cons, 'x' },
4398 { "string", stringer, 0 },
4399 { "stringz", stringer, 1 },
4400
4401 /* unaligned versions: */
4402 { "data2.ua", stmt_cons_ua, 2 },
4403 { "data4.ua", stmt_cons_ua, 4 },
4404 { "data8.ua", stmt_cons_ua, 8 },
4405 { "real4.ua", float_cons, 'f' },
4406 { "real8.ua", float_cons, 'd' },
4407 { "real10.ua", float_cons, 'x' },
4408 };
4409
4410/* Declare a register by creating a symbol for it and entering it in
4411 the symbol table. */
4412static symbolS*
4413declare_register (name, regnum)
4414 const char *name;
4415 int regnum;
4416{
4417 const char *err;
4418 symbolS *sym;
4419
4420 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4421
4422 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4423 if (err)
4424 as_fatal ("Inserting \"%s\" into register table failed: %s",
4425 name, err);
4426
4427 return sym;
4428}
4429
4430static void
4431declare_register_set (prefix, num_regs, base_regnum)
4432 const char *prefix;
4433 int num_regs;
4434 int base_regnum;
4435{
4436 char name[8];
4437 int i;
4438
4439 for (i = 0; i < num_regs; ++i)
4440 {
4441 sprintf (name, "%s%u", prefix, i);
4442 declare_register (name, base_regnum + i);
4443 }
4444}
4445
4446static unsigned int
4447operand_width (opnd)
4448 enum ia64_opnd opnd;
4449{
4450 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4451 unsigned int bits = 0;
4452 int i;
4453
4454 bits = 0;
4455 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4456 bits += odesc->field[i].bits;
4457
4458 return bits;
4459}
4460
4461static int
4462operand_match (idesc, index, e)
4463 const struct ia64_opcode *idesc;
4464 int index;
4465 expressionS *e;
4466{
4467 enum ia64_opnd opnd = idesc->operands[index];
4468 int bits, relocatable = 0;
4469 struct insn_fix *fix;
4470 bfd_signed_vma val;
4471
4472 switch (opnd)
4473 {
4474 /* constants: */
4475
4476 case IA64_OPND_AR_CCV:
4477 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4478 return 1;
4479 break;
4480
4481 case IA64_OPND_AR_PFS:
4482 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4483 return 1;
4484 break;
4485
4486 case IA64_OPND_GR0:
4487 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4488 return 1;
4489 break;
4490
4491 case IA64_OPND_IP:
4492 if (e->X_op == O_register && e->X_add_number == REG_IP)
4493 return 1;
4494 break;
4495
4496 case IA64_OPND_PR:
4497 if (e->X_op == O_register && e->X_add_number == REG_PR)
4498 return 1;
4499 break;
4500
4501 case IA64_OPND_PR_ROT:
4502 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4503 return 1;
4504 break;
4505
4506 case IA64_OPND_PSR:
4507 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4508 return 1;
4509 break;
4510
4511 case IA64_OPND_PSR_L:
4512 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4513 return 1;
4514 break;
4515
4516 case IA64_OPND_PSR_UM:
4517 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4518 return 1;
4519 break;
4520
4521 case IA64_OPND_C1:
4522 if (e->X_op == O_constant && e->X_add_number == 1)
4523 return 1;
4524 break;
4525
4526 case IA64_OPND_C8:
4527 if (e->X_op == O_constant && e->X_add_number == 8)
4528 return 1;
4529 break;
4530
4531 case IA64_OPND_C16:
4532 if (e->X_op == O_constant && e->X_add_number == 16)
4533 return 1;
4534 break;
4535
4536 /* register operands: */
4537
4538 case IA64_OPND_AR3:
4539 if (e->X_op == O_register && e->X_add_number >= REG_AR
4540 && e->X_add_number < REG_AR + 128)
4541 return 1;
4542 break;
4543
4544 case IA64_OPND_B1:
4545 case IA64_OPND_B2:
4546 if (e->X_op == O_register && e->X_add_number >= REG_BR
4547 && e->X_add_number < REG_BR + 8)
4548 return 1;
4549 break;
4550
4551 case IA64_OPND_CR3:
4552 if (e->X_op == O_register && e->X_add_number >= REG_CR
4553 && e->X_add_number < REG_CR + 128)
4554 return 1;
4555 break;
4556
4557 case IA64_OPND_F1:
4558 case IA64_OPND_F2:
4559 case IA64_OPND_F3:
4560 case IA64_OPND_F4:
4561 if (e->X_op == O_register && e->X_add_number >= REG_FR
4562 && e->X_add_number < REG_FR + 128)
4563 return 1;
4564 break;
4565
4566 case IA64_OPND_P1:
4567 case IA64_OPND_P2:
4568 if (e->X_op == O_register && e->X_add_number >= REG_P
4569 && e->X_add_number < REG_P + 64)
4570 return 1;
4571 break;
4572
4573 case IA64_OPND_R1:
4574 case IA64_OPND_R2:
4575 case IA64_OPND_R3:
4576 if (e->X_op == O_register && e->X_add_number >= REG_GR
4577 && e->X_add_number < REG_GR + 128)
4578 return 1;
4579 break;
4580
4581 case IA64_OPND_R3_2:
4582 if (e->X_op == O_register && e->X_add_number >= REG_GR
4583 && e->X_add_number < REG_GR + 4)
4584 return 1;
4585 break;
4586
4587 /* indirect operands: */
4588 case IA64_OPND_CPUID_R3:
4589 case IA64_OPND_DBR_R3:
4590 case IA64_OPND_DTR_R3:
4591 case IA64_OPND_ITR_R3:
4592 case IA64_OPND_IBR_R3:
4593 case IA64_OPND_MSR_R3:
4594 case IA64_OPND_PKR_R3:
4595 case IA64_OPND_PMC_R3:
4596 case IA64_OPND_PMD_R3:
4597 case IA64_OPND_RR_R3:
4598 if (e->X_op == O_index && e->X_op_symbol
4599 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4600 == opnd - IA64_OPND_CPUID_R3))
4601 return 1;
4602 break;
4603
4604 case IA64_OPND_MR3:
4605 if (e->X_op == O_index && !e->X_op_symbol)
4606 return 1;
4607 break;
4608
4609 /* immediate operands: */
4610 case IA64_OPND_CNT2a:
4611 case IA64_OPND_LEN4:
4612 case IA64_OPND_LEN6:
4613 bits = operand_width (idesc->operands[index]);
4614 if (e->X_op == O_constant
4615 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4616 return 1;
4617 break;
4618
4619 case IA64_OPND_CNT2b:
4620 if (e->X_op == O_constant
4621 && (bfd_vma) (e->X_add_number - 1) < 3)
4622 return 1;
4623 break;
4624
4625 case IA64_OPND_CNT2c:
4626 val = e->X_add_number;
4627 if (e->X_op == O_constant
4628 && (val == 0 || val == 7 || val == 15 || val == 16))
4629 return 1;
4630 break;
4631
4632 case IA64_OPND_SOR:
4633 /* SOR must be an integer multiple of 8 */
4634 if (e->X_add_number & 0x7)
4635 break;
4636 case IA64_OPND_SOF:
4637 case IA64_OPND_SOL:
4638 if (e->X_op == O_constant &&
4639 (bfd_vma) e->X_add_number <= 96)
4640 return 1;
4641 break;
4642
4643 case IA64_OPND_IMMU62:
4644 if (e->X_op == O_constant)
4645 {
4646 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
4647 return 1;
4648 }
197865e8 4649 else
800eeca4
JW		 4650 {
4651 /* FIXME -- need 62-bit relocation type */
4652 as_bad (_("62-bit relocation not yet implemented"));
4653 }
4654 break;
4655
4656 case IA64_OPND_IMMU64:
4657 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4658 || e->X_op == O_subtract)
4659 {
4660 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4661 fix->code = BFD_RELOC_IA64_IMM64;
4662 if (e->X_op != O_subtract)
4663 {
4664 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4665 if (e->X_op == O_pseudo_fixup)
4666 e->X_op = O_symbol;
4667 }
4668
4669 fix->opnd = idesc->operands[index];
4670 fix->expr = *e;
4671 fix->is_pcrel = 0;
4672 ++CURR_SLOT.num_fixups;
4673 return 1;
4674 }
4675 else if (e->X_op == O_constant)
4676 return 1;
4677 break;
4678
4679 case IA64_OPND_CCNT5:
4680 case IA64_OPND_CNT5:
4681 case IA64_OPND_CNT6:
4682 case IA64_OPND_CPOS6a:
4683 case IA64_OPND_CPOS6b:
4684 case IA64_OPND_CPOS6c:
4685 case IA64_OPND_IMMU2:
4686 case IA64_OPND_IMMU7a:
4687 case IA64_OPND_IMMU7b:
800eeca4
JW		 4688 case IA64_OPND_IMMU21:
4689 case IA64_OPND_IMMU24:
4690 case IA64_OPND_MBTYPE4:
4691 case IA64_OPND_MHTYPE8:
4692 case IA64_OPND_POS6:
4693 bits = operand_width (idesc->operands[index]);
4694 if (e->X_op == O_constant
4695 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4696 return 1;
4697 break;
4698
bf3ca999
TW		 4699 case IA64_OPND_IMMU9:
4700 bits = operand_width (idesc->operands[index]);
4701 if (e->X_op == O_constant
4702 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4703 {
4704 int lobits = e->X_add_number & 0x3;
4705 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
197865e8 4706 e->X_add_number |= (bfd_vma) 0x3;
bf3ca999
TW		 4707 return 1;
4708 }
4709 break;
4710
800eeca4
JW		 4711 case IA64_OPND_IMM44:
4712 /* least 16 bits must be zero */
4713 if ((e->X_add_number & 0xffff) != 0)
4714 as_warn (_("lower 16 bits of mask ignored"));
4715
4716 if (e->X_op == O_constant
4717 && ((e->X_add_number >= 0
4718 && e->X_add_number < ((bfd_vma) 1 << 44))
4719 || (e->X_add_number < 0
4720 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
4721 {
4722 /* sign-extend */
4723 if (e->X_add_number >= 0
4724 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4725 {
4726 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4727 }
4728 return 1;
4729 }
4730 break;
4731
4732 case IA64_OPND_IMM17:
4733 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4734 if (e->X_op == O_constant
4735 && ((e->X_add_number >= 0
4736 && e->X_add_number < ((bfd_vma) 1 << 17))
4737 || (e->X_add_number < 0
4738 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
4739 {
4740 /* sign-extend */
4741 if (e->X_add_number >= 0
4742 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4743 {
197865e8 4744 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
800eeca4
JW		 4745 }
4746 return 1;
4747 }
4748 break;
4749
4750 case IA64_OPND_IMM14:
4751 case IA64_OPND_IMM22:
4752 relocatable = 1;
4753 case IA64_OPND_IMM1:
4754 case IA64_OPND_IMM8:
4755 case IA64_OPND_IMM8U4:
4756 case IA64_OPND_IMM8M1:
4757 case IA64_OPND_IMM8M1U4:
4758 case IA64_OPND_IMM8M1U8:
4759 case IA64_OPND_IMM9a:
4760 case IA64_OPND_IMM9b:
4761 bits = operand_width (idesc->operands[index]);
4762 if (relocatable && (e->X_op == O_symbol
4763 || e->X_op == O_subtract
4764 || e->X_op == O_pseudo_fixup))
4765 {
4766 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4767
4768 if (idesc->operands[index] == IA64_OPND_IMM14)
4769 fix->code = BFD_RELOC_IA64_IMM14;
4770 else
4771 fix->code = BFD_RELOC_IA64_IMM22;
4772
4773 if (e->X_op != O_subtract)
4774 {
4775 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4776 if (e->X_op == O_pseudo_fixup)
4777 e->X_op = O_symbol;
4778 }
4779
4780 fix->opnd = idesc->operands[index];
4781 fix->expr = *e;
4782 fix->is_pcrel = 0;
4783 ++CURR_SLOT.num_fixups;
4784 return 1;
4785 }
4786 else if (e->X_op != O_constant
4787 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4788 return 0;
4789
4790 if (opnd == IA64_OPND_IMM8M1U4)
4791 {
4792 /* Zero is not valid for unsigned compares that take an adjusted
4793 constant immediate range. */
4794 if (e->X_add_number == 0)
4795 return 0;
4796
4797 /* Sign-extend 32-bit unsigned numbers, so that the following range
4798 checks will work. */
4799 val = e->X_add_number;
197865e8
KH		 4800 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4801 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 4802 val = ((val << 32) >> 32);
4803
4804 /* Check for 0x100000000. This is valid because
4805 0x100000000-1 is the same as ((uint32_t) -1). */
4806 if (val == ((bfd_signed_vma) 1 << 32))
4807 return 1;
4808
4809 val = val - 1;
4810 }
4811 else if (opnd == IA64_OPND_IMM8M1U8)
4812 {
4813 /* Zero is not valid for unsigned compares that take an adjusted
4814 constant immediate range. */
4815 if (e->X_add_number == 0)
4816 return 0;
4817
4818 /* Check for 0x10000000000000000. */
4819 if (e->X_op == O_big)
4820 {
4821 if (generic_bignum[0] == 0
4822 && generic_bignum[1] == 0
4823 && generic_bignum[2] == 0
4824 && generic_bignum[3] == 0
4825 && generic_bignum[4] == 1)
4826 return 1;
4827 else
4828 return 0;
4829 }
4830 else
4831 val = e->X_add_number - 1;
4832 }
4833 else if (opnd == IA64_OPND_IMM8M1)
4834 val = e->X_add_number - 1;
4835 else if (opnd == IA64_OPND_IMM8U4)
4836 {
4837 /* Sign-extend 32-bit unsigned numbers, so that the following range
4838 checks will work. */
4839 val = e->X_add_number;
197865e8
KH		 4840 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4841 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 4842 val = ((val << 32) >> 32);
4843 }
4844 else
4845 val = e->X_add_number;
4846
4847 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
4848 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
4849 return 1;
4850 break;
4851
4852 case IA64_OPND_INC3:
4853 /* +/- 1, 4, 8, 16 */
4854 val = e->X_add_number;
4855 if (val < 0)
4856 val = -val;
4857 if (e->X_op == O_constant
4858 && (val == 1 || val == 4 || val == 8 || val == 16))
4859 return 1;
4860 break;
4861
4862 case IA64_OPND_TGT25:
4863 case IA64_OPND_TGT25b:
4864 case IA64_OPND_TGT25c:
4865 case IA64_OPND_TGT64:
4866 if (e->X_op == O_symbol)
4867 {
4868 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4869 if (opnd == IA64_OPND_TGT25)
4870 fix->code = BFD_RELOC_IA64_PCREL21F;
4871 else if (opnd == IA64_OPND_TGT25b)
4872 fix->code = BFD_RELOC_IA64_PCREL21M;
4873 else if (opnd == IA64_OPND_TGT25c)
4874 fix->code = BFD_RELOC_IA64_PCREL21B;
c67e42c9
RH		 4875 else if (opnd == IA64_OPND_TGT64)
4876 fix->code = BFD_RELOC_IA64_PCREL60B;
4877 else
4878 abort ();
4879
800eeca4
JW		 4880 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4881 fix->opnd = idesc->operands[index];
4882 fix->expr = *e;
4883 fix->is_pcrel = 1;
4884 ++CURR_SLOT.num_fixups;
4885 return 1;
4886 }
4887 case IA64_OPND_TAG13:
4888 case IA64_OPND_TAG13b:
4889 switch (e->X_op)
4890 {
4891 case O_constant:
4892 return 1;
4893
4894 case O_symbol:
4895 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4896 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4897 fix->opnd = idesc->operands[index];
4898 fix->expr = *e;
4899 fix->is_pcrel = 1;
4900 ++CURR_SLOT.num_fixups;
4901 return 1;
4902
4903 default:
4904 break;
4905 }
4906 break;
4907
4908 default:
4909 break;
4910 }
4911 return 0;
4912}
4913
4914static int
4915parse_operand (e)
4916 expressionS *e;
4917{
4918 int sep = '\0';
4919
4920 memset (e, 0, sizeof (*e));
4921 e->X_op = O_absent;
4922 SKIP_WHITESPACE ();
4923 if (*input_line_pointer != '}')
4924 expression (e);
4925 sep = *input_line_pointer++;
4926
4927 if (sep == '}')
4928 {
4929 if (!md.manual_bundling)
4930 as_warn ("Found '}' when manual bundling is off");
4931 else
4932 CURR_SLOT.manual_bundling_off = 1;
4933 md.manual_bundling = 0;
4934 sep = '\0';
4935 }
4936 return sep;
4937}
4938
4939/* Returns the next entry in the opcode table that matches the one in
4940 IDESC, and frees the entry in IDESC. If no matching entry is
197865e8 4941 found, NULL is returned instead. */
800eeca4
JW		 4942
4943static struct ia64_opcode *
4944get_next_opcode (struct ia64_opcode *idesc)
4945{
4946 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
4947 ia64_free_opcode (idesc);
4948 return next;
4949}
4950
4951/* Parse the operands for the opcode and find the opcode variant that
4952 matches the specified operands, or NULL if no match is possible. */
4953static struct ia64_opcode*
4954parse_operands (idesc)
4955 struct ia64_opcode *idesc;
4956{
4957 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
4958 int sep = 0;
4959 enum ia64_opnd expected_operand = IA64_OPND_NIL;
4960 char mnemonic[129];
4961 char *first_arg = 0, *end, *saved_input_pointer;
4962 unsigned int sof;
4963
4964 assert (strlen (idesc->name) <= 128);
4965
4966 strcpy (mnemonic, idesc->name);
4967 if (idesc->operands[2] == IA64_OPND_SOF)
4968 {
4969 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4970 can't parse the first operand until we have parsed the
4971 remaining operands of the "alloc" instruction. */
4972 SKIP_WHITESPACE ();
4973 first_arg = input_line_pointer;
4974 end = strchr (input_line_pointer, '=');
4975 if (!end)
4976 {
4977 as_bad ("Expected separator `='");
4978 return 0;
4979 }
4980 input_line_pointer = end + 1;
4981 ++i;
4982 ++num_outputs;
4983 }
4984
4985 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
4986 {
4987 sep = parse_operand (CURR_SLOT.opnd + i);
4988 if (CURR_SLOT.opnd[i].X_op == O_absent)
4989 break;
4990
4991 ++num_operands;
4992
4993 if (sep != '=' && sep != ',')
4994 break;
4995
4996 if (sep == '=')
4997 {
4998 if (num_outputs > 0)
4999 as_bad ("Duplicate equal sign (=) in instruction");
5000 else
5001 num_outputs = i + 1;
5002 }
5003 }
5004 if (sep != '\0')
5005 {
5006 as_bad ("Illegal operand separator `%c'", sep);
5007 return 0;
5008 }
197865e8 5009
800eeca4
JW		 5010 if (idesc->operands[2] == IA64_OPND_SOF)
5011 {
5012 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5013 know (strcmp (idesc->name, "alloc") == 0);
5014 if (num_operands == 5 /* first_arg not included in this count! */
5015 && CURR_SLOT.opnd[2].X_op == O_constant
5016 && CURR_SLOT.opnd[3].X_op == O_constant
5017 && CURR_SLOT.opnd[4].X_op == O_constant
5018 && CURR_SLOT.opnd[5].X_op == O_constant)
5019 {
5020 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5021 CURR_SLOT.opnd[3].X_add_number,
5022 CURR_SLOT.opnd[4].X_add_number,
5023 CURR_SLOT.opnd[5].X_add_number);
5024
5025 /* now we can parse the first arg: */
5026 saved_input_pointer = input_line_pointer;
5027 input_line_pointer = first_arg;
5028 sep = parse_operand (CURR_SLOT.opnd + 0);
5029 if (sep != '=')
5030 --num_outputs; /* force error */
5031 input_line_pointer = saved_input_pointer;
5032
5033 CURR_SLOT.opnd[2].X_add_number = sof;
5034 CURR_SLOT.opnd[3].X_add_number
5035 = sof - CURR_SLOT.opnd[4].X_add_number;
5036 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5037 }
5038 }
5039
5040 highest_unmatched_operand = 0;
5041 expected_operand = idesc->operands[0];
5042 for (; idesc; idesc = get_next_opcode (idesc))
5043 {
5044 if (num_outputs != idesc->num_outputs)
5045 continue; /* mismatch in # of outputs */
5046
5047 CURR_SLOT.num_fixups = 0;
5048 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5049 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
5050 break;
5051
5052 if (i != num_operands)
5053 {
5054 if (i > highest_unmatched_operand)
5055 {
5056 highest_unmatched_operand = i;
5057 expected_operand = idesc->operands[i];
5058 }
5059 continue;
5060 }
5061
5062 if (num_operands < NELEMS (idesc->operands)
5063 && idesc->operands[num_operands])
5064 continue; /* mismatch in number of arguments */
5065
5066 break;
5067 }
5068 if (!idesc)
5069 {
5070 if (expected_operand)
5071 as_bad ("Operand %u of `%s' should be %s",
5072 highest_unmatched_operand + 1, mnemonic,
5073 elf64_ia64_operands[expected_operand].desc);
5074 else
5075 as_bad ("Operand mismatch");
5076 return 0;
5077 }
5078 return idesc;
5079}
5080
5081static void
5082build_insn (slot, insnp)
5083 struct slot *slot;
5084 bfd_vma *insnp;
5085{
5086 const struct ia64_operand *odesc, *o2desc;
5087 struct ia64_opcode *idesc = slot->idesc;
5088 bfd_signed_vma insn, val;
5089 const char *err;
5090 int i;
5091
5092 insn = idesc->opcode | slot->qp_regno;
5093
5094 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5095 {
c67e42c9
RH		 5096 if (slot->opnd[i].X_op == O_register
5097 || slot->opnd[i].X_op == O_constant
5098 || slot->opnd[i].X_op == O_index)
5099 val = slot->opnd[i].X_add_number;
5100 else if (slot->opnd[i].X_op == O_big)
800eeca4 5101 {
c67e42c9
RH		 5102 /* This must be the value 0x10000000000000000. */
5103 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5104 val = 0;
5105 }
5106 else
5107 val = 0;
5108
5109 switch (idesc->operands[i])
5110 {
5111 case IA64_OPND_IMMU64:
800eeca4
JW		 5112 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5113 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5114 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5115 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH		 5116 continue;
5117
5118 case IA64_OPND_IMMU62:
5119 val &= 0x3fffffffffffffffULL;
800eeca4
JW		 5120 if (val != slot->opnd[i].X_add_number)
5121 as_warn (_("Value truncated to 62 bits"));
5122 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5123 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 5124 continue;
800eeca4 5125
c67e42c9
RH		 5126 case IA64_OPND_TGT64:
5127 val >>= 4;
5128 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5129 insn |= ((((val >> 59) & 0x1) << 36)
5130 | (((val >> 0) & 0xfffff) << 13));
5131 continue;
800eeca4 5132
c67e42c9
RH		 5133 case IA64_OPND_AR3:
5134 val -= REG_AR;
5135 break;
5136
5137 case IA64_OPND_B1:
5138 case IA64_OPND_B2:
5139 val -= REG_BR;
5140 break;
5141
5142 case IA64_OPND_CR3:
5143 val -= REG_CR;
5144 break;
5145
5146 case IA64_OPND_F1:
5147 case IA64_OPND_F2:
5148 case IA64_OPND_F3:
5149 case IA64_OPND_F4:
5150 val -= REG_FR;
5151 break;
5152
5153 case IA64_OPND_P1:
5154 case IA64_OPND_P2:
5155 val -= REG_P;
5156 break;
5157
5158 case IA64_OPND_R1:
5159 case IA64_OPND_R2:
5160 case IA64_OPND_R3:
5161 case IA64_OPND_R3_2:
5162 case IA64_OPND_CPUID_R3:
5163 case IA64_OPND_DBR_R3:
5164 case IA64_OPND_DTR_R3:
5165 case IA64_OPND_ITR_R3:
5166 case IA64_OPND_IBR_R3:
5167 case IA64_OPND_MR3:
5168 case IA64_OPND_MSR_R3:
5169 case IA64_OPND_PKR_R3:
5170 case IA64_OPND_PMC_R3:
5171 case IA64_OPND_PMD_R3:
197865e8 5172 case IA64_OPND_RR_R3:
c67e42c9
RH		 5173 val -= REG_GR;
5174 break;
5175
5176 default:
5177 break;
5178 }
5179
5180 odesc = elf64_ia64_operands + idesc->operands[i];
5181 err = (*odesc->insert) (odesc, val, &insn);
5182 if (err)
5183 as_bad_where (slot->src_file, slot->src_line,
5184 "Bad operand value: %s", err);
5185 if (idesc->flags & IA64_OPCODE_PSEUDO)
5186 {
5187 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5188 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5189 {
5190 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5191 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5192 }
c67e42c9
RH		 5193 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5194 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5195 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5196 {
c67e42c9
RH		 5197 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5198 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW		 5199 }
5200 }
5201 }
5202 *insnp = insn;
5203}
5204
5205static void
5206emit_one_bundle ()
5207{
5208 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5209 unsigned int manual_bundling = 0;
5210 enum ia64_unit required_unit, insn_unit = 0;
5211 enum ia64_insn_type type[3], insn_type;
5212 unsigned int template, orig_template;
5213 bfd_vma insn[3] = {-1, -1, -1};
5214 struct ia64_opcode *idesc;
5215 int end_of_insn_group = 0, user_template = -1;
5216 int n, i, j, first, curr;
e0c9811a 5217 unw_rec_list *ptr, *prev;
800eeca4
JW		 5218 bfd_vma t0 = 0, t1 = 0;
5219 struct label_fix *lfix;
5220 struct insn_fix *ifix;
5221 char mnemonic[16];
5222 fixS *fix;
5223 char *f;
5224
5225 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5226 know (first >= 0 & first < NUM_SLOTS);
5227 n = MIN (3, md.num_slots_in_use);
5228
5229 /* Determine template: user user_template if specified, best match
5230 otherwise: */
5231
5232 if (md.slot[first].user_template >= 0)
5233 user_template = template = md.slot[first].user_template;
5234 else
5235 {
032efc85 5236 /* Auto select appropriate template. */
800eeca4
JW		 5237 memset (type, 0, sizeof (type));
5238 curr = first;
5239 for (i = 0; i < n; ++i)
5240 {
032efc85
RH		 5241 if (md.slot[curr].label_fixups && i != 0)
5242 break;
800eeca4
JW		 5243 type[i] = md.slot[curr].idesc->type;
5244 curr = (curr + 1) % NUM_SLOTS;
5245 }
5246 template = best_template[type[0]][type[1]][type[2]];
5247 }
5248
5249 /* initialize instructions with appropriate nops: */
5250 for (i = 0; i < 3; ++i)
5251 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5252
5253 f = frag_more (16);
5254
5255 /* now fill in slots with as many insns as possible: */
5256 curr = first;
5257 idesc = md.slot[curr].idesc;
5258 end_of_insn_group = 0;
5259 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5260 {
e0c9811a
JW		 5261 /* Set the slot number for prologue/body records now as those
5262 refer to the current point, not the point after the
5263 instruction has been issued: */
10850f29
JW		 5264 /* Don't try to delete prologue/body records here, as that will cause
5265 them to also be deleted from the master list of unwind records. */
e0c9811a 5266 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
10850f29
JW		 5267 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5268 || ptr->r.type == body)
5269 ptr->slot_number = (unsigned long) f + i;
e0c9811a 5270
800eeca4
JW		 5271 if (idesc->flags & IA64_OPCODE_SLOT2)
5272 {
5273 if (manual_bundling && i != 2)
5274 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5275 "`%s' must be last in bundle", idesc->name);
5276 else
5277 i = 2;
5278 }
5279 if (idesc->flags & IA64_OPCODE_LAST)
5280 {
5281 int required_slot, required_template;
5282
5283 /* If we need a stop bit after an M slot, our only choice is
5284 template 5 (M;;MI). If we need a stop bit after a B
5285 slot, our only choice is to place it at the end of the
5286 bundle, because the only available templates are MIB,
5287 MBB, BBB, MMB, and MFB. We don't handle anything other
5288 than M and B slots because these are the only kind of
5289 instructions that can have the IA64_OPCODE_LAST bit set. */
5290 required_template = template;
5291 switch (idesc->type)
5292 {
5293 case IA64_TYPE_M:
5294 required_slot = 0;
5295 required_template = 5;
5296 break;
5297
5298 case IA64_TYPE_B:
5299 required_slot = 2;
5300 break;
5301
5302 default:
5303 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5304 "Internal error: don't know how to force %s to end"
5305 "of instruction group", idesc->name);
5306 required_slot = i;
5307 break;
5308 }
5309 if (manual_bundling && i != required_slot)
5310 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5311 "`%s' must be last in instruction group",
5312 idesc->name);
5313 if (required_slot < i)
5314 /* Can't fit this instruction. */
5315 break;
5316
5317 i = required_slot;
5318 if (required_template != template)
5319 {
5320 /* If we switch the template, we need to reset the NOPs
5321 after slot i. The slot-types of the instructions ahead
5322 of i never change, so we don't need to worry about
5323 changing NOPs in front of this slot. */
5324 for (j = i; j < 3; ++j)
5325 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5326 }
5327 template = required_template;
5328 }
5329 if (curr != first && md.slot[curr].label_fixups)
5330 {
5331 if (manual_bundling_on)
5332 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5333 "Label must be first in a bundle");
5334 /* This insn must go into the first slot of a bundle. */
5335 break;
5336 }
5337
5338 manual_bundling_on = md.slot[curr].manual_bundling_on;
5339 manual_bundling_off = md.slot[curr].manual_bundling_off;
5340
5341 if (manual_bundling_on)
5342 {
5343 if (curr == first)
5344 manual_bundling = 1;
5345 else
5346 break; /* need to start a new bundle */
5347 }
5348
5349 if (end_of_insn_group && md.num_slots_in_use >= 1)
5350 {
5351 /* We need an instruction group boundary in the middle of a
5352 bundle. See if we can switch to an other template with
5353 an appropriate boundary. */
5354
5355 orig_template = template;
5356 if (i == 1 && (user_template == 4
5357 || (user_template < 0
5358 && (ia64_templ_desc[template].exec_unit[0]
5359 == IA64_UNIT_M))))
5360 {
5361 template = 5;
5362 end_of_insn_group = 0;
5363 }
5364 else if (i == 2 && (user_template == 0
5365 || (user_template < 0
5366 && (ia64_templ_desc[template].exec_unit[1]
5367 == IA64_UNIT_I)))
5368 /* This test makes sure we don't switch the template if
5369 the next instruction is one that needs to be first in
5370 an instruction group. Since all those instructions are
5371 in the M group, there is no way such an instruction can
5372 fit in this bundle even if we switch the template. The
5373 reason we have to check for this is that otherwise we
5374 may end up generating "MI;;I M.." which has the deadly
5375 effect that the second M instruction is no longer the
5376 first in the bundle! --davidm 99/12/16 */
5377 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5378 {
5379 template = 1;
5380 end_of_insn_group = 0;
5381 }
5382 else if (curr != first)
5383 /* can't fit this insn */
5384 break;
5385
5386 if (template != orig_template)
5387 /* if we switch the template, we need to reset the NOPs
5388 after slot i. The slot-types of the instructions ahead
5389 of i never change, so we don't need to worry about
5390 changing NOPs in front of this slot. */
5391 for (j = i; j < 3; ++j)
5392 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5393 }
5394 required_unit = ia64_templ_desc[template].exec_unit[i];
5395
5396 /* resolve dynamic opcodes such as "break" and "nop": */
5397 if (idesc->type == IA64_TYPE_DYN)
5398 {
5399 if ((strcmp (idesc->name, "nop") == 0)
5400 || (strcmp (idesc->name, "break") == 0))
5401 insn_unit = required_unit;
5402 else if (strcmp (idesc->name, "chk.s") == 0)
5403 {
5404 insn_unit = IA64_UNIT_M;
5405 if (required_unit == IA64_UNIT_I)
5406 insn_unit = IA64_UNIT_I;
5407 }
5408 else
5409 as_fatal ("emit_one_bundle: unexpected dynamic op");
5410
5411 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
3d56ab85 5412 ia64_free_opcode (idesc);
800eeca4
JW		 5413 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5414#if 0
5415 know (!idesc->next); /* no resolved dynamic ops have collisions */
5416#endif
5417 }
5418 else
5419 {
5420 insn_type = idesc->type;
5421 insn_unit = IA64_UNIT_NIL;
5422 switch (insn_type)
5423 {
5424 case IA64_TYPE_A:
5425 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5426 insn_unit = required_unit;
5427 break;
5428 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
5429 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5430 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5431 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5432 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5433 default: break;
5434 }
5435 }
5436
5437 if (insn_unit != required_unit)
5438 {
5439 if (required_unit == IA64_UNIT_L
5440 && insn_unit == IA64_UNIT_I
5441 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5442 {
5443 /* we got ourselves an MLX template but the current
197865e8 5444 instruction isn't an X-unit, or an I-unit instruction
800eeca4
JW		 5445 that can go into the X slot of an MLX template. Duh. */
5446 if (md.num_slots_in_use >= NUM_SLOTS)
5447 {
5448 as_bad_where (md.slot[curr].src_file,
5449 md.slot[curr].src_line,
5450 "`%s' can't go in X slot of "
5451 "MLX template", idesc->name);
5452 /* drop this insn so we don't livelock: */
5453 --md.num_slots_in_use;
5454 }
5455 break;
5456 }
5457 continue; /* try next slot */
5458 }
5459
5460 if (debug_type == DEBUG_DWARF2)
5461 {
5462 bfd_vma addr;
5463
5464 addr = frag_now->fr_address + frag_now_fix () - 16 + 1*i;
5465 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5466 }
5467
5468 build_insn (md.slot + curr, insn + i);
5469
10850f29
JW		 5470 /* Set slot counts for non prologue/body unwind records. */
5471 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5472 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5473 && ptr->r.type != body)
5474 ptr->slot_number = (unsigned long) f + i;
5475 md.slot[curr].unwind_record = NULL;
e0c9811a 5476 unwind.next_slot_number = (unsigned long) f + i + ((i == 2)?(0x10-2):1);
10850f29 5477
800eeca4
JW		 5478 if (required_unit == IA64_UNIT_L)
5479 {
5480 know (i == 1);
5481 /* skip one slot for long/X-unit instructions */
5482 ++i;
5483 }
5484 --md.num_slots_in_use;
5485
5486 /* now is a good time to fix up the labels for this insn: */
5487 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5488 {
5489 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5490 symbol_set_frag (lfix->sym, frag_now);
5491 }
5492
5493 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5494 {
5495 ifix = md.slot[curr].fixup + j;
5496 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
5497 &ifix->expr, ifix->is_pcrel, ifix->code);
5498 fix->tc_fix_data.opnd = ifix->opnd;
5499 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5500 fix->fx_file = md.slot[curr].src_file;
5501 fix->fx_line = md.slot[curr].src_line;
5502 }
5503
5504 end_of_insn_group = md.slot[curr].end_of_insn_group;
5505
5506 /* clear slot: */
5507 ia64_free_opcode (md.slot[curr].idesc);
5508 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5509 md.slot[curr].user_template = -1;
5510
5511 if (manual_bundling_off)
5512 {
5513 manual_bundling = 0;
5514 break;
5515 }
5516 curr = (curr + 1) % NUM_SLOTS;
5517 idesc = md.slot[curr].idesc;
5518 }
5519 if (manual_bundling)
5520 {
5521 if (md.num_slots_in_use > 0)
5522 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5523 "`%s' does not fit into %s template",
5524 idesc->name, ia64_templ_desc[template].name);
5525 else
5526 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5527 "Missing '}' at end of file");
5528 }
5529 know (md.num_slots_in_use < NUM_SLOTS);
5530
5531 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5532 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5533
5534 md_number_to_chars (f + 0, t0, 8);
5535 md_number_to_chars (f + 8, t1, 8);
5536}
5537
5538int
5539md_parse_option (c, arg)
5540 int c;
5541 char *arg;
5542{
800eeca4
JW		 5543 switch (c)
5544 {
c43c2cc5 5545 /* Switches from the Intel assembler. */
800eeca4
JW		 5546 case 'M':
5547 if (strcmp (arg, "ilp64") == 0
5548 || strcmp (arg, "lp64") == 0
5549 || strcmp (arg, "p64") == 0)
5550 {
5551 md.flags |= EF_IA_64_ABI64;
5552 }
5553 else if (strcmp (arg, "ilp32") == 0)
5554 {
5555 md.flags &= ~EF_IA_64_ABI64;
5556 }
5557 else if (strcmp (arg, "le") == 0)
5558 {
5559 md.flags &= ~EF_IA_64_BE;
5560 }
5561 else if (strcmp (arg, "be") == 0)
5562 {
5563 md.flags |= EF_IA_64_BE;
5564 }
5565 else
5566 return 0;
5567 break;
5568
5569 case 'N':
5570 if (strcmp (arg, "so") == 0)
5571 {
197865e8 5572 /* Suppress signon message. */
800eeca4
JW		 5573 }
5574 else if (strcmp (arg, "pi") == 0)
5575 {
5576 /* Reject privileged instructions. FIXME */
5577 }
5578 else if (strcmp (arg, "us") == 0)
5579 {
5580 /* Allow union of signed and unsigned range. FIXME */
5581 }
5582 else if (strcmp (arg, "close_fcalls") == 0)
5583 {
5584 /* Do not resolve global function calls. */
5585 }
5586 else
5587 return 0;
5588 break;
5589
5590 case 'C':
5591 /* temp[="prefix"] Insert temporary labels into the object file
5592 symbol table prefixed by "prefix".
5593 Default prefix is ":temp:".
5594 */
5595 break;
5596
5597 case 'a':
5598 /* ??? Conflicts with gas' listing option. */
5599 /* indirect=<tgt> Assume unannotated indirect branches behavior
5600 according to <tgt> --
5601 exit: branch out from the current context (default)
5602 labels: all labels in context may be branch targets
5603 */
5604 break;
5605
5606 case 'x':
5607 /* -X conflicts with an ignored option, use -x instead */
5608 md.detect_dv = 1;
5609 if (!arg || strcmp (arg, "explicit") == 0)
5610 {
5611 /* set default mode to explicit */
5612 md.default_explicit_mode = 1;
5613 break;
5614 }
5615 else if (strcmp (arg, "auto") == 0)
5616 {
5617 md.default_explicit_mode = 0;
5618 }
5619 else if (strcmp (arg, "debug") == 0)
5620 {
5621 md.debug_dv = 1;
5622 }
5623 else if (strcmp (arg, "debugx") == 0)
5624 {
5625 md.default_explicit_mode = 1;
5626 md.debug_dv = 1;
5627 }
5628 else
5629 {
5630 as_bad (_("Unrecognized option '-x%s'"), arg);
5631 }
5632 break;
5633
5634 case 'S':
5635 /* nops Print nops statistics. */
5636 break;
5637
c43c2cc5
JW		 5638 /* GNU specific switches for gcc. */
5639 case OPTION_MCONSTANT_GP:
5640 md.flags |= EF_IA_64_CONS_GP;
5641 break;
5642
5643 case OPTION_MAUTO_PIC:
5644 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
5645 break;
5646
800eeca4
JW		 5647 default:
5648 return 0;
5649 }
5650
5651 return 1;
5652}
5653
5654void
5655md_show_usage (stream)
5656 FILE *stream;
5657{
5658 fputs(_("\
5659IA-64 options:\n\
5660 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5661 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5662 -x | -xexplicit turn on dependency violation checking (default)\n\
5663 -xauto automagically remove dependency violations\n\
5664 -xdebug debug dependency violation checker\n"),
5665 stream);
5666}
5667
44576e1f
RH		 5668/* Return true if TYPE fits in TEMPL at SLOT. */
5669
5670static int
800eeca4
JW		 5671match (int templ, int type, int slot)
5672{
5673 enum ia64_unit unit;
5674 int result;
5675
5676 unit = ia64_templ_desc[templ].exec_unit[slot];
5677 switch (type)
5678 {
5679 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5680 case IA64_TYPE_A:
5681 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5682 break;
5683 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5684 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5685 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5686 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5687 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5688 default: result = 0; break;
5689 }
5690 return result;
5691}
5692
44576e1f
RH		 5693/* Add a bit of extra goodness if a nop of type F or B would fit
5694 in TEMPL at SLOT. */
5695
5696static inline int
5697extra_goodness (int templ, int slot)
5698{
5699 if (match (templ, IA64_TYPE_F, slot))
5700 return 2;
5701 if (match (templ, IA64_TYPE_B, slot))
5702 return 1;
5703 return 0;
5704}
5705
800eeca4
JW		 5706/* This function is called once, at assembler startup time. It sets
5707 up all the tables, etc. that the MD part of the assembler will need
5708 that can be determined before arguments are parsed. */
5709void
5710md_begin ()
5711{
5712 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
5713 const char *err;
5714 char name[8];
5715
5716 md.auto_align = 1;
5717 md.explicit_mode = md.default_explicit_mode;
5718
5719 bfd_set_section_alignment (stdoutput, text_section, 4);
5720
5721 target_big_endian = 0;
5722 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
5723 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5724 &zero_address_frag);
5725
5726 pseudo_func[FUNC_GP_RELATIVE].u.sym =
5727 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5728 &zero_address_frag);
5729
5730 pseudo_func[FUNC_LT_RELATIVE].u.sym =
5731 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5732 &zero_address_frag);
5733
c67e42c9
RH		 5734 pseudo_func[FUNC_PC_RELATIVE].u.sym =
5735 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5736 &zero_address_frag);
5737
800eeca4
JW		 5738 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
5739 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5740 &zero_address_frag);
5741
5742 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
5743 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5744 &zero_address_frag);
5745
5746 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
5747 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5748 &zero_address_frag);
5749
5750 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
5751 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5752 &zero_address_frag);
5753
5754 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
5755 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5756 &zero_address_frag);
5757
197865e8 5758 /* Compute the table of best templates. We compute goodness as a
44576e1f
RH		 5759 base 4 value, in which each match counts for 3, each F counts
5760 for 2, each B counts for 1. This should maximize the number of
5761 F and B nops in the chosen bundles, which is good because these
5762 pipelines are least likely to be overcommitted. */
800eeca4
JW		 5763 for (i = 0; i < IA64_NUM_TYPES; ++i)
5764 for (j = 0; j < IA64_NUM_TYPES; ++j)
5765 for (k = 0; k < IA64_NUM_TYPES; ++k)
5766 {
5767 best = 0;
5768 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
5769 {
5770 goodness = 0;
5771 if (match (t, i, 0))
5772 {
5773 if (match (t, j, 1))
5774 {
5775 if (match (t, k, 2))
44576e1f 5776 goodness = 3 + 3 + 3;
800eeca4 5777 else
44576e1f 5778 goodness = 3 + 3 + extra_goodness (t, 2);
800eeca4
JW		 5779 }
5780 else if (match (t, j, 2))
44576e1f 5781 goodness = 3 + 3 + extra_goodness (t, 1);
800eeca4 5782 else
44576e1f
RH		 5783 {
5784 goodness = 3;
5785 goodness += extra_goodness (t, 1);
5786 goodness += extra_goodness (t, 2);
5787 }
800eeca4
JW		 5788 }
5789 else if (match (t, i, 1))
5790 {
5791 if (match (t, j, 2))
44576e1f 5792 goodness = 3 + 3;
800eeca4 5793 else
44576e1f 5794 goodness = 3 + extra_goodness (t, 2);
800eeca4
JW		 5795 }
5796 else if (match (t, i, 2))
44576e1f 5797 goodness = 3 + extra_goodness (t, 1);
800eeca4
JW		 5798
5799 if (goodness > best)
5800 {
5801 best = goodness;
5802 best_template[i][j][k] = t;
5803 }
5804 }
5805 }
5806
5807 for (i = 0; i < NUM_SLOTS; ++i)
5808 md.slot[i].user_template = -1;
5809
5810 md.pseudo_hash = hash_new ();
5811 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
5812 {
5813 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
5814 (void *) (pseudo_opcode + i));
5815 if (err)
5816 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5817 pseudo_opcode[i].name, err);
5818 }
5819
5820 md.reg_hash = hash_new ();
5821 md.dynreg_hash = hash_new ();
5822 md.const_hash = hash_new ();
5823 md.entry_hash = hash_new ();
5824
5825 /* general registers: */
5826
5827 total = 128;
5828 for (i = 0; i < total; ++i)
5829 {
5830 sprintf (name, "r%d", i - REG_GR);
5831 md.regsym[i] = declare_register (name, i);
5832 }
5833
5834 /* floating point registers: */
5835 total += 128;
5836 for (; i < total; ++i)
5837 {
5838 sprintf (name, "f%d", i - REG_FR);
5839 md.regsym[i] = declare_register (name, i);
5840 }
5841
5842 /* application registers: */
5843 total += 128;
5844 ar_base = i;
5845 for (; i < total; ++i)
5846 {
5847 sprintf (name, "ar%d", i - REG_AR);
5848 md.regsym[i] = declare_register (name, i);
5849 }
5850
5851 /* control registers: */
5852 total += 128;
5853 cr_base = i;
5854 for (; i < total; ++i)
5855 {
5856 sprintf (name, "cr%d", i - REG_CR);
5857 md.regsym[i] = declare_register (name, i);
5858 }
5859
5860 /* predicate registers: */
5861 total += 64;
5862 for (; i < total; ++i)
5863 {
5864 sprintf (name, "p%d", i - REG_P);
5865 md.regsym[i] = declare_register (name, i);
5866 }
5867
5868 /* branch registers: */
5869 total += 8;
5870 for (; i < total; ++i)
5871 {
5872 sprintf (name, "b%d", i - REG_BR);
5873 md.regsym[i] = declare_register (name, i);
5874 }
5875
5876 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
5877 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
5878 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
5879 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
5880 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
5881 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
5882 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
5883
5884 for (i = 0; i < NELEMS (indirect_reg); ++i)
5885 {
5886 regnum = indirect_reg[i].regnum;
5887 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
5888 }
5889
5890 /* define synonyms for application registers: */
5891 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
5892 md.regsym[i] = declare_register (ar[i - REG_AR].name,
5893 REG_AR + ar[i - REG_AR].regnum);
5894
5895 /* define synonyms for control registers: */
5896 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
5897 md.regsym[i] = declare_register (cr[i - REG_CR].name,
5898 REG_CR + cr[i - REG_CR].regnum);
5899
5900 declare_register ("gp", REG_GR + 1);
5901 declare_register ("sp", REG_GR + 12);
5902 declare_register ("rp", REG_BR + 0);
5903
e0c9811a
JW		 5904 /* pseudo-registers used to specify unwind info: */
5905 declare_register ("psp", REG_PSP);
5906
800eeca4
JW		 5907 declare_register_set ("ret", 4, REG_GR + 8);
5908 declare_register_set ("farg", 8, REG_FR + 8);
5909 declare_register_set ("fret", 8, REG_FR + 8);
5910
5911 for (i = 0; i < NELEMS (const_bits); ++i)
5912 {
5913 err = hash_insert (md.const_hash, const_bits[i].name,
5914 (PTR) (const_bits + i));
5915 if (err)
5916 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5917 name, err);
5918 }
5919
5920 /* Default to 64-bit mode. */
c43c2cc5
JW		 5921 /* ??? This overrides the -M options, but they aren't working anyways. */
5922 md.flags |= EF_IA_64_ABI64;
800eeca4
JW		 5923
5924 md.mem_offset.hint = 0;
5925 md.path = 0;
5926 md.maxpaths = 0;
5927 md.entry_labels = NULL;
5928}
5929
5930void
5931ia64_end_of_source ()
5932{
5933 /* terminate insn group upon reaching end of file: */
5934 insn_group_break (1, 0, 0);
5935
5936 /* emits slots we haven't written yet: */
5937 ia64_flush_insns ();
5938
5939 bfd_set_private_flags (stdoutput, md.flags);
5940
5941 if (debug_type == DEBUG_DWARF2)
5942 dwarf2_finish ();
5943
5944 md.mem_offset.hint = 0;
5945}
5946
5947void
5948ia64_start_line ()
5949{
5950 md.qp.X_op = O_absent;
5951
5952 if (ignore_input ())
5953 return;
5954
5955 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
5956 {
5957 if (md.detect_dv && !md.explicit_mode)
5958 as_warn (_("Explicit stops are ignored in auto mode"));
5959 else
5960 insn_group_break (1, 0, 0);
5961 }
5962}
5963
5964int
5965ia64_unrecognized_line (ch)
5966 int ch;
5967{
5968 switch (ch)
5969 {
5970 case '(':
5971 expression (&md.qp);
5972 if (*input_line_pointer++ != ')')
5973 {
5974 as_bad ("Expected ')'");
5975 return 0;
5976 }
5977 if (md.qp.X_op != O_register)
5978 {
5979 as_bad ("Qualifying predicate expected");
5980 return 0;
5981 }
5982 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
5983 {
5984 as_bad ("Predicate register expected");
5985 return 0;
5986 }
5987 return 1;
5988
5989 case '{':
5990 if (md.manual_bundling)
5991 as_warn ("Found '{' when manual bundling is already turned on");
5992 else
5993 CURR_SLOT.manual_bundling_on = 1;
5994 md.manual_bundling = 1;
5995
5996 /* bundling is only acceptable in explicit mode
5997 or when in default automatic mode */
5998 if (md.detect_dv && !md.explicit_mode)
5999 {
6000 if (!md.mode_explicitly_set
6001 && !md.default_explicit_mode)
6002 dot_dv_mode ('E');
6003 else
6004 as_warn (_("Found '{' after explicit switch to automatic mode"));
6005 }
6006 return 1;
6007
6008 case '}':
6009 if (!md.manual_bundling)
6010 as_warn ("Found '}' when manual bundling is off");
6011 else
6012 PREV_SLOT.manual_bundling_off = 1;
6013 md.manual_bundling = 0;
6014
6015 /* switch back to automatic mode, if applicable */
197865e8 6016 if (md.detect_dv
800eeca4
JW		 6017 && md.explicit_mode
6018 && !md.mode_explicitly_set
6019 && !md.default_explicit_mode)
6020 dot_dv_mode ('A');
6021
6022 /* Allow '{' to follow on the same line. We also allow ";;", but that
6023 happens automatically because ';' is an end of line marker. */
6024 SKIP_WHITESPACE ();
6025 if (input_line_pointer[0] == '{')
6026 {
6027 input_line_pointer++;
6028 return ia64_unrecognized_line ('{');
6029 }
6030
6031 demand_empty_rest_of_line ();
6032 return 1;
6033
6034 default:
6035 break;
6036 }
6037 return 0; /* not a valid line */
6038}
6039
6040void
6041ia64_frob_label (sym)
6042 struct symbol *sym;
6043{
6044 struct label_fix *fix;
6045
6046 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6047 {
6048 md.last_text_seg = now_seg;
6049 fix = obstack_alloc (&notes, sizeof (*fix));
6050 fix->sym = sym;
6051 fix->next = CURR_SLOT.label_fixups;
6052 CURR_SLOT.label_fixups = fix;
6053
6054 /* keep track of how many code entry points we've seen */
6055 if (md.path == md.maxpaths)
6056 {
6057 md.maxpaths += 20;
6058 md.entry_labels = (const char **)
6059 xrealloc ((void *)md.entry_labels, md.maxpaths * sizeof (char *));
6060 }
6061 md.entry_labels[md.path++] = S_GET_NAME (sym);
6062 }
6063}
6064
6065void
6066ia64_flush_pending_output ()
6067{
6068 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6069 {
6070 /* ??? This causes many unnecessary stop bits to be emitted.
6071 Unfortunately, it isn't clear if it is safe to remove this. */
6072 insn_group_break (1, 0, 0);
6073 ia64_flush_insns ();
6074 }
6075}
6076
6077/* Do ia64-specific expression optimization. All that's done here is
6078 to transform index expressions that are either due to the indexing
6079 of rotating registers or due to the indexing of indirect register
6080 sets. */
6081int
6082ia64_optimize_expr (l, op, r)
6083 expressionS *l;
6084 operatorT op;
6085 expressionS *r;
6086{
6087 unsigned num_regs;
6088
6089 if (op == O_index)
6090 {
6091 if (l->X_op == O_register && r->X_op == O_constant)
6092 {
6093 num_regs = (l->X_add_number >> 16);
6094 if ((unsigned) r->X_add_number >= num_regs)
6095 {
6096 if (!num_regs)
6097 as_bad ("No current frame");
6098 else
6099 as_bad ("Index out of range 0..%u", num_regs - 1);
6100 r->X_add_number = 0;
6101 }
6102 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6103 return 1;
6104 }
6105 else if (l->X_op == O_register && r->X_op == O_register)
6106 {
6107 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6108 || l->X_add_number == IND_MEM)
6109 {
6110 as_bad ("Indirect register set name expected");
6111 l->X_add_number = IND_CPUID;
6112 }
6113 l->X_op = O_index;
6114 l->X_op_symbol = md.regsym[l->X_add_number];
6115 l->X_add_number = r->X_add_number;
6116 return 1;
6117 }
6118 }
6119 return 0;
6120}
6121
6122int
6123ia64_parse_name (name, e)
6124 char *name;
6125 expressionS *e;
6126{
6127 struct const_desc *cdesc;
6128 struct dynreg *dr = 0;
6129 unsigned int regnum;
6130 struct symbol *sym;
6131 char *end;
6132
6133 /* first see if NAME is a known register name: */
6134 sym = hash_find (md.reg_hash, name);
6135 if (sym)
6136 {
6137 e->X_op = O_register;
6138 e->X_add_number = S_GET_VALUE (sym);
6139 return 1;
6140 }
6141
6142 cdesc = hash_find (md.const_hash, name);
6143 if (cdesc)
6144 {
6145 e->X_op = O_constant;
6146 e->X_add_number = cdesc->value;
6147 return 1;
6148 }
6149
6150 /* check for inN, locN, or outN: */
6151 switch (name[0])
6152 {
6153 case 'i':
6154 if (name[1] == 'n' && isdigit (name[2]))
6155 {
6156 dr = &md.in;
6157 name += 2;
6158 }
6159 break;
6160
6161 case 'l':
6162 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6163 {
6164 dr = &md.loc;
6165 name += 3;
6166 }
6167 break;
6168
6169 case 'o':
6170 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6171 {
6172 dr = &md.out;
6173 name += 3;
6174 }
6175 break;
6176
6177 default:
6178 break;
6179 }
6180
6181 if (dr)
6182 {
6183 /* the name is inN, locN, or outN; parse the register number: */
6184 regnum = strtoul (name, &end, 10);
6185 if (end > name && *end == '\0')
6186 {
6187 if ((unsigned) regnum >= dr->num_regs)
6188 {
6189 if (!dr->num_regs)
6190 as_bad ("No current frame");
6191 else
6192 as_bad ("Register number out of range 0..%u", dr->num_regs-1);
6193 regnum = 0;
6194 }
6195 e->X_op = O_register;
6196 e->X_add_number = dr->base + regnum;
6197 return 1;
6198 }
6199 }
6200
6201 if ((dr = hash_find (md.dynreg_hash, name)))
6202 {
6203 /* We've got ourselves the name of a rotating register set.
6204 Store the base register number in the low 16 bits of
6205 X_add_number and the size of the register set in the top 16
6206 bits. */
6207 e->X_op = O_register;
6208 e->X_add_number = dr->base | (dr->num_regs << 16);
6209 return 1;
6210 }
6211 return 0;
6212}
6213
6214/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6215
6216char *
6217ia64_canonicalize_symbol_name (name)
6218 char *name;
6219{
6220 size_t len = strlen(name);
6221 if (len > 1 && name[len-1] == '#')
6222 name[len-1] = '\0';
6223 return name;
6224}
6225
6226static int
6227is_conditional_branch (idesc)
6228 struct ia64_opcode *idesc;
6229{
6230 return (strncmp (idesc->name, "br", 2) == 0
197865e8 6231 && (strcmp (idesc->name, "br") == 0
800eeca4
JW		 6232 || strncmp (idesc->name, "br.cond", 7) == 0
6233 || strncmp (idesc->name, "br.call", 7) == 0
6234 || strncmp (idesc->name, "br.ret", 6) == 0
6235 || strcmp (idesc->name, "brl") == 0
6236 || strncmp (idesc->name, "brl.cond", 7) == 0
6237 || strncmp (idesc->name, "brl.call", 7) == 0
6238 || strncmp (idesc->name, "brl.ret", 6) == 0));
6239}
6240
6241/* Return whether the given opcode is a taken branch. If there's any doubt,
6242 returns zero */
6243static int
6244is_taken_branch (idesc)
6245 struct ia64_opcode *idesc;
6246{
6247 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
6248 || strncmp (idesc->name, "br.ia", 5) == 0);
6249}
6250
6251/* Return whether the given opcode is an interruption or rfi. If there's any
6252 doubt, returns zero */
6253static int
6254is_interruption_or_rfi (idesc)
6255 struct ia64_opcode *idesc;
6256{
6257 if (strcmp (idesc->name, "rfi") == 0)
6258 return 1;
6259 return 0;
6260}
6261
6262/* Returns the index of the given dependency in the opcode's list of chks, or
6263 -1 if there is no dependency. */
6264static int
6265depends_on (depind, idesc)
6266 int depind;
6267 struct ia64_opcode *idesc;
6268{
6269 int i;
6270 const struct ia64_opcode_dependency *dep = idesc->dependencies;
6271 for (i = 0;i < dep->nchks; i++)
6272 {
6273 if (depind == DEP(dep->chks[i]))
6274 return i;
6275 }
6276 return -1;
6277}
6278
6279/* Determine a set of specific resources used for a particular resource
6280 class. Returns the number of specific resources identified For those
6281 cases which are not determinable statically, the resource returned is
197865e8 6282 marked nonspecific.
800eeca4
JW		 6283
6284 Meanings of value in 'NOTE':
6285 1) only read/write when the register number is explicitly encoded in the
6286 insn.
6287 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
197865e8 6288 accesses CFM when qualifying predicate is in the rotating region.
800eeca4
JW		 6289 3) general register value is used to specify an indirect register; not
6290 determinable statically.
6291 4) only read the given resource when bits 7:0 of the indirect index
6292 register value does not match the register number of the resource; not
6293 determinable statically.
6294 5) all rules are implementation specific.
6295 6) only when both the index specified by the reader and the index specified
6296 by the writer have the same value in bits 63:61; not determinable
197865e8 6297 statically.
800eeca4 6298 7) only access the specified resource when the corresponding mask bit is
197865e8 6299 set
800eeca4
JW		 6300 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6301 only read when these insns reference FR2-31
6302 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6303 written when these insns write FR32-127
6304 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6305 instruction
6306 11) The target predicates are written independently of PR[qp], but source
6307 registers are only read if PR[qp] is true. Since the state of PR[qp]
6308 cannot statically be determined, all source registers are marked used.
6309 12) This insn only reads the specified predicate register when that
6310 register is the PR[qp].
6311 13) This reference to ld-c only applies to teh GR whose value is loaded
197865e8 6312 with data returned from memory, not the post-incremented address register.
800eeca4
JW		 6313 14) The RSE resource includes the implementation-specific RSE internal
6314 state resources. At least one (and possibly more) of these resources are
6315 read by each instruction listed in IC:rse-readers. At least one (and
6316 possibly more) of these resources are written by each insn listed in
197865e8 6317 IC:rse-writers.
800eeca4 6318 15+16) Represents reserved instructions, which the assembler does not
197865e8 6319 generate.
800eeca4
JW		 6320
6321 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6322 this code; there are no dependency violations based on memory access.
6323
6324*/
6325
6326#define MAX_SPECS 256
6327#define DV_CHK 1
6328#define DV_REG 0
6329
6330static int
6331specify_resource (dep, idesc, type, specs, note, path)
6332 const struct ia64_dependency *dep;
6333 struct ia64_opcode *idesc;
6334 int type; /* is this a DV chk or a DV reg? */
6335 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6336 int note; /* resource note for this insn's usage */
6337 int path; /* which execution path to examine */
6338{
6339 int count = 0;
6340 int i;
6341 int rsrc_write = 0;
6342 struct rsrc tmpl;
197865e8 6343
800eeca4
JW		 6344 if (dep->mode == IA64_DV_WAW
6345 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6346 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6347 rsrc_write = 1;
6348
6349 /* template for any resources we identify */
6350 tmpl.dependency = dep;
6351 tmpl.note = note;
6352 tmpl.insn_srlz = tmpl.data_srlz = 0;
6353 tmpl.qp_regno = CURR_SLOT.qp_regno;
6354 tmpl.link_to_qp_branch = 1;
6355 tmpl.mem_offset.hint = 0;
6356 tmpl.specific = 1;
6357 tmpl.index = 0;
6358
6359#define UNHANDLED \
6360as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6361dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6362#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6363
6364 /* we don't need to track these */
6365 if (dep->semantics == IA64_DVS_NONE)
6366 return 0;
6367
6368 switch (dep->specifier)
6369 {
6370 case IA64_RS_AR_K:
6371 if (note == 1)
6372 {
6373 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6374 {
6375 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6376 if (regno >= 0 && regno <= 7)
6377 {
6378 specs[count] = tmpl;
6379 specs[count++].index = regno;
6380 }
6381 }
6382 }
6383 else if (note == 0)
6384 {
6385 for(i=0;i < 8;i++)
6386 {
6387 specs[count] = tmpl;
6388 specs[count++].index = i;
6389 }
6390 }
6391 else
6392 {
6393 UNHANDLED;
6394 }
6395 break;
6396
6397 case IA64_RS_AR_UNAT:
6398 /* This is a mov =AR or mov AR= instruction. */
6399 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6400 {
6401 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6402 if (regno == AR_UNAT)
6403 {
6404 specs[count++] = tmpl;
6405 }
6406 }
6407 else
6408 {
6409 /* This is a spill/fill, or other instruction that modifies the
6410 unat register. */
6411
6412 /* Unless we can determine the specific bits used, mark the whole
6413 thing; bits 8:3 of the memory address indicate the bit used in
6414 UNAT. The .mem.offset hint may be used to eliminate a small
6415 subset of conflicts. */
6416 specs[count] = tmpl;
6417 if (md.mem_offset.hint)
6418 {
6419 if (md.debug_dv)
6420 fprintf (stderr, " Using hint for spill/fill\n");
6421 /* the index isn't actually used, just set it to something
6422 approximating the bit index */
6423 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6424 specs[count].mem_offset.hint = 1;
6425 specs[count].mem_offset.offset = md.mem_offset.offset;
6426 specs[count++].mem_offset.base = md.mem_offset.base;
6427 }
6428 else
6429 {
6430 specs[count++].specific = 0;
6431 }
6432 }
6433 break;
6434
6435 case IA64_RS_AR:
6436 if (note == 1)
197865e8 6437 {
800eeca4
JW		 6438 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6439 {
6440 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6441 if ((regno >= 8 && regno <= 15)
6442 || (regno >= 20 && regno <= 23)
6443 || (regno >= 31 && regno <= 39)
6444 || (regno >= 41 && regno <= 47)
6445 || (regno >= 67 && regno <= 111))
6446 {
6447 specs[count] = tmpl;
6448 specs[count++].index = regno;
6449 }
6450 }
6451 }
6452 else
6453 {
6454 UNHANDLED;
6455 }
6456 break;
6457
6458 case IA64_RS_ARb:
6459 if (note == 1)
6460 {
6461 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6462 {
6463 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6464 if ((regno >= 48 && regno <= 63)
6465 || (regno >= 112 && regno <= 127))
6466 {
6467 specs[count] = tmpl;
6468 specs[count++].index = regno;
6469 }
6470 }
6471 }
6472 else if (note == 0)
6473 {
6474 for (i=48;i < 64;i++)
6475 {
6476 specs[count] = tmpl;
6477 specs[count++].index = i;
6478 }
6479 for (i=112;i < 128;i++)
6480 {
6481 specs[count] = tmpl;
6482 specs[count++].index = i;
6483 }
6484 }
197865e8 6485 else
800eeca4
JW		 6486 {
6487 UNHANDLED;
6488 }
6489 break;
6490
6491 case IA64_RS_BR:
6492 if (note != 1)
6493 {
6494 UNHANDLED;
6495 }
6496 else
6497 {
6498 if (rsrc_write)
6499 {
6500 for (i=0;i < idesc->num_outputs;i++)
6501 if (idesc->operands[i] == IA64_OPND_B1
6502 || idesc->operands[i] == IA64_OPND_B2)
6503 {
6504 specs[count] = tmpl;
197865e8 6505 specs[count++].index =
800eeca4
JW		 6506 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6507 }
6508 }
6509 else
6510 {
6511 for (i = idesc->num_outputs;i < NELEMS(idesc->operands);i++)
6512 if (idesc->operands[i] == IA64_OPND_B1
6513 || idesc->operands[i] == IA64_OPND_B2)
6514 {
6515 specs[count] = tmpl;
197865e8 6516 specs[count++].index =
800eeca4
JW		 6517 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6518 }
6519 }
6520 }
6521 break;
6522
6523 case IA64_RS_CPUID: /* four or more registers */
6524 if (note == 3)
6525 {
6526 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6527 {
6528 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6529 if (regno >= 0 && regno < NELEMS(gr_values)
6530 && KNOWN(regno))
6531 {
6532 specs[count] = tmpl;
6533 specs[count++].index = gr_values[regno].value & 0xFF;
6534 }
6535 else
6536 {
6537 specs[count] = tmpl;
6538 specs[count++].specific = 0;
6539 }
6540 }
6541 }
6542 else
6543 {
6544 UNHANDLED;
6545 }
6546 break;
6547
6548 case IA64_RS_DBR: /* four or more registers */
6549 if (note == 3)
6550 {
6551 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6552 {
6553 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6554 if (regno >= 0 && regno < NELEMS(gr_values)
6555 && KNOWN(regno))
6556 {
6557 specs[count] = tmpl;
6558 specs[count++].index = gr_values[regno].value & 0xFF;
6559 }
6560 else
6561 {
6562 specs[count] = tmpl;
6563 specs[count++].specific = 0;
6564 }
6565 }
6566 }
6567 else if (note == 0 && !rsrc_write)
6568 {
6569 specs[count] = tmpl;
6570 specs[count++].specific = 0;
6571 }
6572 else
6573 {
6574 UNHANDLED;
6575 }
6576 break;
6577
6578 case IA64_RS_IBR: /* four or more registers */
6579 if (note == 3)
6580 {
6581 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6582 {
6583 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6584 if (regno >= 0 && regno < NELEMS(gr_values)
6585 && KNOWN(regno))
6586 {
6587 specs[count] = tmpl;
6588 specs[count++].index = gr_values[regno].value & 0xFF;
6589 }
6590 else
6591 {
6592 specs[count] = tmpl;
6593 specs[count++].specific = 0;
6594 }
6595 }
6596 }
6597 else
6598 {
6599 UNHANDLED;
6600 }
6601 break;
6602
6603 case IA64_RS_MSR:
6604 if (note == 5)
6605 {
6606 /* These are implementation specific. Force all references to
6607 conflict with all other references. */
6608 specs[count] = tmpl;
6609 specs[count++].specific = 0;
6610 }
6611 else
6612 {
6613 UNHANDLED;
6614 }
6615 break;
6616
6617 case IA64_RS_PKR: /* 16 or more registers */
6618 if (note == 3 || note == 4)
6619 {
6620 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6621 {
6622 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6623 if (regno >= 0 && regno < NELEMS(gr_values)
6624 && KNOWN(regno))
6625 {
6626 if (note == 3)
6627 {
6628 specs[count] = tmpl;
6629 specs[count++].index = gr_values[regno].value & 0xFF;
6630 }
6631 else for (i=0;i < NELEMS(gr_values);i++)
6632 {
6633 /* uses all registers *except* the one in R3 */
6634 if (i != (gr_values[regno].value & 0xFF))
6635 {
6636 specs[count] = tmpl;
6637 specs[count++].index = i;
6638 }
6639 }
6640 }
6641 else
6642 {
6643 specs[count] = tmpl;
6644 specs[count++].specific = 0;
6645 }
6646 }
6647 }
6648 else if (note == 0)
6649 {
197865e8 6650 /* probe et al. */
800eeca4
JW		 6651 specs[count] = tmpl;
6652 specs[count++].specific = 0;
6653 }
6654 break;
6655
6656 case IA64_RS_PMC: /* four or more registers */
6657 if (note == 3)
6658 {
6659 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
6660 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
197865e8 6661
800eeca4
JW		 6662 {
6663 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
6664 ? 1 : !rsrc_write);
6665 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
6666 if (regno >= 0 && regno < NELEMS(gr_values)
6667 && KNOWN(regno))
6668 {
6669 specs[count] = tmpl;
6670 specs[count++].index = gr_values[regno].value & 0xFF;
6671 }
6672 else
6673 {
6674 specs[count] = tmpl;
6675 specs[count++].specific = 0;
6676 }
6677 }
6678 }
6679 else
6680 {
6681 UNHANDLED;
6682 }
6683 break;
6684
6685 case IA64_RS_PMD: /* four or more registers */
6686 if (note == 3)
6687 {
6688 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
6689 {
6690 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6691 if (regno >= 0 && regno < NELEMS(gr_values)
6692 && KNOWN(regno))
6693 {
6694 specs[count] = tmpl;
6695 specs[count++].index = gr_values[regno].value & 0xFF;
6696 }
6697 else
6698 {
6699 specs[count] = tmpl;
6700 specs[count++].specific = 0;
6701 }
6702 }
6703 }
6704 else
6705 {
6706 UNHANDLED;
6707 }
6708 break;
6709
6710 case IA64_RS_RR: /* eight registers */
6711 if (note == 6)
6712 {
6713 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
6714 {
6715 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6716 if (regno >= 0 && regno < NELEMS(gr_values)
6717 && KNOWN(regno))
6718 {
6719 specs[count] = tmpl;
6720 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
6721 }
6722 else
6723 {
6724 specs[count] = tmpl;
6725 specs[count++].specific = 0;
6726 }
6727 }
6728 }
6729 else if (note == 0 && !rsrc_write)
6730 {
6731 specs[count] = tmpl;
6732 specs[count++].specific = 0;
6733 }
197865e8 6734 else
800eeca4
JW		 6735 {
6736 UNHANDLED;
6737 }
6738 break;
6739
6740 case IA64_RS_CR_IRR:
197865e8 6741 if (note == 0)
800eeca4
JW		 6742 {
6743 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6744 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
197865e8 6745 if (rsrc_write
800eeca4
JW		 6746 && idesc->operands[1] == IA64_OPND_CR3
6747 && regno == CR_IVR)
6748 {
6749 for(i=0;i < 4;i++)
6750 {
6751 specs[count] = tmpl;
6752 specs[count++].index = CR_IRR0 + i;
6753 }
6754 }
6755 }
6756 else if (note == 1)
6757 {
6758 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6759 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6760 && regno >= CR_IRR0
6761 && regno <= CR_IRR3)
6762 {
6763 specs[count] = tmpl;
6764 specs[count++].index = regno;
6765 }
6766 }
6767 else
6768 {
6769 UNHANDLED;
6770 }
6771 break;
6772
6773 case IA64_RS_CR_LRR:
6774 if (note != 1)
6775 {
6776 UNHANDLED;
6777 }
197865e8 6778 else
800eeca4
JW		 6779 {
6780 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6781 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6782 && (regno == CR_LRR0 || regno == CR_LRR1))
6783 {
6784 specs[count] = tmpl;
6785 specs[count++].index = regno;
6786 }
6787 }
6788 break;
6789
6790 case IA64_RS_CR:
6791 if (note == 1)
6792 {
6793 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
6794 {
6795 specs[count] = tmpl;
197865e8 6796 specs[count++].index =
800eeca4
JW		 6797 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6798 }
6799 }
6800 else
6801 {
6802 UNHANDLED;
6803 }
6804 break;
6805
6806 case IA64_RS_FR:
6807 case IA64_RS_FRb:
6808 if (note != 1)
6809 {
6810 UNHANDLED;
6811 }
6812 else if (rsrc_write)
6813 {
6814 if (dep->specifier == IA64_RS_FRb
6815 && idesc->operands[0] == IA64_OPND_F1)
6816 {
6817 specs[count] = tmpl;
6818 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
6819 }
6820 }
6821 else
6822 {
6823 for (i=idesc->num_outputs;i < NELEMS(idesc->operands);i++)
6824 {
6825 if (idesc->operands[i] == IA64_OPND_F2
6826 || idesc->operands[i] == IA64_OPND_F3
6827 || idesc->operands[i] == IA64_OPND_F4)
6828 {
6829 specs[count] = tmpl;
197865e8 6830 specs[count++].index =
800eeca4
JW		 6831 CURR_SLOT.opnd[i].X_add_number - REG_FR;
6832 }
6833 }
6834 }
6835 break;
6836
6837 case IA64_RS_GR:
6838 if (note == 13)
6839 {
6840 /* This reference applies only to the GR whose value is loaded with
6841 data returned from memory */
6842 specs[count] = tmpl;
6843 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
6844 }
6845 else if (note == 1)
6846 {
6847 if (rsrc_write)
6848 {
50b81f19
JW		 6849 for (i= 0; i < idesc->num_outputs; i++)
6850 if (idesc->operands[i] == IA64_OPND_R1
6851 || idesc->operands[i] == IA64_OPND_R2
6852 || idesc->operands[i] == IA64_OPND_R3)
6853 {
6854 specs[count] = tmpl;
197865e8 6855 specs[count++].index =
50b81f19
JW		 6856 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6857 }
6858 if (idesc->flags & IA64_OPCODE_POSTINC)
6859 for (i = 0; i < NELEMS (idesc->operands); i++)
6860 if (idesc->operands[i] == IA64_OPND_MR3)
6861 {
6862 specs[count] = tmpl;
6863 specs[count++].index =
6864 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6865 }
800eeca4 6866 }
197865e8 6867 else
800eeca4
JW		 6868 {
6869 /* Look for anything that reads a GR */
6870 for (i=0;i < NELEMS(idesc->operands);i++)
6871 {
6872 if (idesc->operands[i] == IA64_OPND_MR3
6873 || idesc->operands[i] == IA64_OPND_CPUID_R3
6874 || idesc->operands[i] == IA64_OPND_DBR_R3
6875 || idesc->operands[i] == IA64_OPND_IBR_R3
6876 || idesc->operands[i] == IA64_OPND_MSR_R3
6877 || idesc->operands[i] == IA64_OPND_PKR_R3
6878 || idesc->operands[i] == IA64_OPND_PMC_R3
6879 || idesc->operands[i] == IA64_OPND_PMD_R3
6880 || idesc->operands[i] == IA64_OPND_RR_R3
6881 || ((i >= idesc->num_outputs)
6882 && (idesc->operands[i] == IA64_OPND_R1
6883 || idesc->operands[i] == IA64_OPND_R2
50b81f19
JW		 6884 || idesc->operands[i] == IA64_OPND_R3
6885 /* addl source register. */
6886 || idesc->operands[i] == IA64_OPND_R3_2)))
800eeca4
JW		 6887 {
6888 specs[count] = tmpl;
197865e8 6889 specs[count++].index =
800eeca4
JW		 6890 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6891 }
6892 }
6893 }
6894 }
197865e8 6895 else
800eeca4
JW		 6896 {
6897 UNHANDLED;
6898 }
6899 break;
6900
6901 case IA64_RS_PR:
6902 if (note == 0)
6903 {
6904 if (idesc->operands[0] == IA64_OPND_PR_ROT)
6905 {
6906 for (i=16;i < 63;i++)
6907 {
6908 specs[count] = tmpl;
6909 specs[count++].index = i;
6910 }
6911 }
6912 else
6913 {
6914 for (i=1;i < 63;i++)
6915 {
6916 specs[count] = tmpl;
6917 specs[count++].index = i;
6918 }
6919 }
6920 }
6921 else if (note == 7)
6922 {
6923 valueT mask = 0;
6924 /* mark only those registers indicated by the mask */
6925 if (rsrc_write
6926 && idesc->operands[0] == IA64_OPND_PR)
6927 {
6928 mask = CURR_SLOT.opnd[2].X_add_number;
197865e8
KH		 6929 if (mask & ((valueT) 1<<16))
6930 mask |= ~(valueT) 0xffff;
800eeca4
JW		 6931 for (i=1;i < 63;i++)
6932 {
197865e8 6933 if (mask & ((valueT) 1<<i))
800eeca4
JW		 6934 {
6935 specs[count] = tmpl;
6936 specs[count++].index = i;
6937 }
6938 }
6939 }
6940 else if (rsrc_write
6941 && idesc->operands[0] == IA64_OPND_PR_ROT)
6942 {
6943 for (i=16;i < 63;i++)
6944 {
6945 specs[count] = tmpl;
6946 specs[count++].index = i;
6947 }
6948 }
6949 else
6950 {
6951 UNHANDLED;
6952 }
6953 }
6954 else if (note == 11) /* note 11 implies note 1 as well */
6955 {
6956 if (rsrc_write)
6957 {
6958 for (i=0;i < idesc->num_outputs;i++)
6959 {
6960 if (idesc->operands[i] == IA64_OPND_P1
6961 || idesc->operands[i] == IA64_OPND_P2)
6962 {
6963 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
6964 if (regno != 0)
6965 {
6966 specs[count] = tmpl;
6967 specs[count++].index = regno;
6968 }
6969 }
6970 }
6971 }
6972 else
6973 {
6974 UNHANDLED;
6975 }
6976 }
6977 else if (note == 12)
6978 {
6979 if (CURR_SLOT.qp_regno != 0)
6980 {
6981 specs[count] = tmpl;
6982 specs[count++].index = CURR_SLOT.qp_regno;
6983 }
6984 }
6985 else if (note == 1)
6986 {
6987 if (rsrc_write)
6988 {
6989 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
6990 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
6991 if ((idesc->operands[0] == IA64_OPND_P1
6992 || idesc->operands[0] == IA64_OPND_P2)
6993 && p1 != 0 && p1 != 63)
6994 {
6995 specs[count] = tmpl;
6996 specs[count++].index = p1;
6997 }
6998 if ((idesc->operands[1] == IA64_OPND_P1
6999 || idesc->operands[1] == IA64_OPND_P2)
7000 && p2 != 0 && p2 != 63)
7001 {
7002 specs[count] = tmpl;
7003 specs[count++].index = p2;
7004 }
7005 }
7006 else
7007 {
7008 if (CURR_SLOT.qp_regno != 0)
7009 {
7010 specs[count] = tmpl;
7011 specs[count++].index = CURR_SLOT.qp_regno;
7012 }
7013 if (idesc->operands[1] == IA64_OPND_PR)
7014 {
7015 for (i=1;i < 63;i++)
7016 {
7017 specs[count] = tmpl;
7018 specs[count++].index = i;
7019 }
7020 }
7021 }
7022 }
197865e8 7023 else
800eeca4
JW		 7024 {
7025 UNHANDLED;
7026 }
7027 break;
7028
7029 case IA64_RS_PSR:
197865e8 7030 /* Verify that the instruction is using the PSR bit indicated in
800eeca4
JW		 7031 dep->regindex */
7032 if (note == 0)
7033 {
7034 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7035 {
7036 if (dep->regindex < 6)
7037 {
7038 specs[count++] = tmpl;
7039 }
7040 }
7041 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7042 {
7043 if (dep->regindex < 32
7044 || dep->regindex == 35
7045 || dep->regindex == 36
7046 || (!rsrc_write && dep->regindex == PSR_CPL))
7047 {
7048 specs[count++] = tmpl;
7049 }
7050 }
7051 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7052 {
7053 if (dep->regindex < 32
7054 || dep->regindex == 35
7055 || dep->regindex == 36
7056 || (rsrc_write && dep->regindex == PSR_CPL))
7057 {
7058 specs[count++] = tmpl;
7059 }
7060 }
197865e8 7061 else
800eeca4 7062 {
197865e8 7063 /* Several PSR bits have very specific dependencies. */
800eeca4
JW		 7064 switch (dep->regindex)
7065 {
7066 default:
7067 specs[count++] = tmpl;
7068 break;
7069 case PSR_IC:
7070 if (rsrc_write)
7071 {
7072 specs[count++] = tmpl;
7073 }
7074 else
7075 {
7076 /* Only certain CR accesses use PSR.ic */
7077 if (idesc->operands[0] == IA64_OPND_CR3
7078 || idesc->operands[1] == IA64_OPND_CR3)
7079 {
197865e8 7080 int index =
800eeca4
JW		 7081 ((idesc->operands[0] == IA64_OPND_CR3)
7082 ? 0 : 1);
197865e8 7083 int regno =
800eeca4
JW		 7084 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7085
7086 switch (regno)
7087 {
7088 default:
7089 break;
7090 case CR_ITIR:
7091 case CR_IFS:
7092 case CR_IIM:
7093 case CR_IIP:
7094 case CR_IPSR:
7095 case CR_ISR:
7096 case CR_IFA:
7097 case CR_IHA:
7098 case CR_IIPA:
7099 specs[count++] = tmpl;
7100 break;
7101 }
7102 }
7103 }
7104 break;
7105 case PSR_CPL:
7106 if (rsrc_write)
7107 {
7108 specs[count++] = tmpl;
7109 }
197865e8 7110 else
800eeca4
JW		 7111 {
7112 /* Only some AR accesses use cpl */
7113 if (idesc->operands[0] == IA64_OPND_AR3
7114 || idesc->operands[1] == IA64_OPND_AR3)
7115 {
197865e8 7116 int index =
800eeca4
JW		 7117 ((idesc->operands[0] == IA64_OPND_AR3)
7118 ? 0 : 1);
197865e8 7119 int regno =
800eeca4 7120 CURR_SLOT.opnd[index].X_add_number - REG_AR;
197865e8 7121
800eeca4
JW		 7122 if (regno == AR_ITC
7123 || (index == 0
197865e8
KH		 7124 && (regno == AR_ITC
7125 || regno == AR_RSC
800eeca4
JW		 7126 || (regno >= AR_K0
7127 && regno <= AR_K7))))
7128 {
7129 specs[count++] = tmpl;
197865e8 7130 }
800eeca4
JW		 7131 }
7132 else
7133 {
7134 specs[count++] = tmpl;
7135 }
7136 break;
7137 }
7138 }
7139 }
7140 }
7141 else if (note == 7)
7142 {
7143 valueT mask = 0;
7144 if (idesc->operands[0] == IA64_OPND_IMMU24)
7145 {
7146 mask = CURR_SLOT.opnd[0].X_add_number;
7147 }
197865e8 7148 else
800eeca4
JW		 7149 {
7150 UNHANDLED;
7151 }
197865e8 7152 if (mask & ((valueT) 1<<dep->regindex))
800eeca4
JW		 7153 {
7154 specs[count++] = tmpl;
7155 }
7156 }
7157 else if (note == 8)
7158 {
7159 int min = dep->regindex == PSR_DFL ? 2 : 32;
7160 int max = dep->regindex == PSR_DFL ? 31 : 127;
7161 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7162 for (i=0;i < NELEMS(idesc->operands);i++)
7163 {
7164 if (idesc->operands[i] == IA64_OPND_F1
7165 || idesc->operands[i] == IA64_OPND_F2
7166 || idesc->operands[i] == IA64_OPND_F3
7167 || idesc->operands[i] == IA64_OPND_F4)
7168 {
7169 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7170 if (reg >= min && reg <= max)
7171 {
7172 specs[count++] = tmpl;
7173 }
7174 }
7175 }
7176 }
7177 else if (note == 9)
7178 {
7179 int min = dep->regindex == PSR_MFL ? 2 : 32;
7180 int max = dep->regindex == PSR_MFL ? 31 : 127;
7181 /* mfh is read on writes to FR32-127; mfl is read on writes to
197865e8 7182 FR2-31 */
800eeca4
JW		 7183 for (i=0;i < idesc->num_outputs;i++)
7184 {
7185 if (idesc->operands[i] == IA64_OPND_F1)
7186 {
7187 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7188 if (reg >= min && reg <= max)
7189 {
7190 specs[count++] = tmpl;
7191 }
7192 }
7193 }
7194 }
7195 else if (note == 10)
7196 {
7197 for (i=0;i < NELEMS(idesc->operands);i++)
7198 {
7199 if (idesc->operands[i] == IA64_OPND_R1
7200 || idesc->operands[i] == IA64_OPND_R2
7201 || idesc->operands[i] == IA64_OPND_R3)
7202 {
7203 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7204 if (regno >= 16 && regno <= 31)
7205 {
7206 specs[count++] = tmpl;
7207 }
7208 }
7209 }
7210 }
7211 else
7212 {
7213 UNHANDLED;
7214 }
7215 break;
7216
7217 case IA64_RS_AR_FPSR:
7218 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7219 {
7220 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7221 if (regno == AR_FPSR)
7222 {
7223 specs[count++] = tmpl;
7224 }
7225 }
7226 else
7227 {
7228 specs[count++] = tmpl;
7229 }
7230 break;
7231
197865e8 7232 case IA64_RS_ARX:
800eeca4
JW		 7233 /* Handle all AR[REG] resources */
7234 if (note == 0 || note == 1)
7235 {
7236 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7237 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7238 && regno == dep->regindex)
7239 {
7240 specs[count++] = tmpl;
7241 }
7242 /* other AR[REG] resources may be affected by AR accesses */
7243 else if (idesc->operands[0] == IA64_OPND_AR3)
7244 {
7245 /* AR[] writes */
7246 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7247 switch (dep->regindex)
7248 {
7249 default:
7250 break;
7251 case AR_BSP:
7252 case AR_RNAT:
7253 if (regno == AR_BSPSTORE)
7254 {
7255 specs[count++] = tmpl;
7256 }
7257 case AR_RSC:
7258 if (!rsrc_write &&
197865e8 7259 (regno == AR_BSPSTORE
800eeca4
JW		 7260 || regno == AR_RNAT))
7261 {
7262 specs[count++] = tmpl;
7263 }
7264 break;
7265 }
7266 }
7267 else if (idesc->operands[1] == IA64_OPND_AR3)
7268 {
7269 /* AR[] reads */
7270 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7271 switch (dep->regindex)
7272 {
7273 default:
7274 break;
7275 case AR_RSC:
7276 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7277 {
7278 specs[count++] = tmpl;
7279 }
7280 break;
7281 }
7282 }
197865e8 7283 else
800eeca4
JW		 7284 {
7285 specs[count++] = tmpl;
7286 }
7287 }
7288 else
7289 {
7290 UNHANDLED;
7291 }
7292 break;
7293
7294 case IA64_RS_CRX:
7295 /* Handle all CR[REG] resources */
7296 if (note == 0 || note == 1)
7297 {
7298 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7299 {
7300 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7301 if (regno == dep->regindex)
7302 {
7303 specs[count++] = tmpl;
7304 }
7305 else if (!rsrc_write)
7306 {
197865e8 7307 /* Reads from CR[IVR] affect other resources. */
800eeca4
JW		 7308 if (regno == CR_IVR)
7309 {
7310 if ((dep->regindex >= CR_IRR0
7311 && dep->regindex <= CR_IRR3)
7312 || dep->regindex == CR_TPR)
7313 {
7314 specs[count++] = tmpl;
7315 }
7316 }
7317 }
7318 }
7319 else
7320 {
7321 specs[count++] = tmpl;
7322 }
7323 }
7324 else
7325 {
7326 UNHANDLED;
7327 }
7328 break;
7329
7330 case IA64_RS_INSERVICE:
7331 /* look for write of EOI (67) or read of IVR (65) */
7332 if ((idesc->operands[0] == IA64_OPND_CR3
7333 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7334 || (idesc->operands[1] == IA64_OPND_CR3
7335 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7336 {
7337 specs[count++] = tmpl;
7338 }
7339 break;
7340
7341 case IA64_RS_GR0:
7342 if (note == 1)
7343 {
7344 specs[count++] = tmpl;
7345 }
7346 else
7347 {
7348 UNHANDLED;
7349 }
7350 break;
7351
7352 case IA64_RS_CFM:
7353 if (note != 2)
7354 {
7355 specs[count++] = tmpl;
7356 }
7357 else
7358 {
7359 /* Check if any of the registers accessed are in the rotating region.
7360 mov to/from pr accesses CFM only when qp_regno is in the rotating
7361 region */
7362 for (i=0;i < NELEMS(idesc->operands);i++)
7363 {
7364 if (idesc->operands[i] == IA64_OPND_R1
7365 || idesc->operands[i] == IA64_OPND_R2
7366 || idesc->operands[i] == IA64_OPND_R3)
7367 {
7368 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7369 /* Assumes that md.rot.num_regs is always valid */
7370 if (md.rot.num_regs > 0
7371 && num > 31
7372 && num < 31 + md.rot.num_regs)
7373 {
7374 specs[count] = tmpl;
7375 specs[count++].specific = 0;
7376 }
7377 }
7378 else if (idesc->operands[i] == IA64_OPND_F1
7379 || idesc->operands[i] == IA64_OPND_F2
7380 || idesc->operands[i] == IA64_OPND_F3
7381 || idesc->operands[i] == IA64_OPND_F4)
7382 {
7383 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7384 if (num > 31)
7385 {
7386 specs[count] = tmpl;
7387 specs[count++].specific = 0;
7388 }
7389 }
7390 else if (idesc->operands[i] == IA64_OPND_P1
7391 || idesc->operands[i] == IA64_OPND_P2)
7392 {
7393 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7394 if (num > 15)
7395 {
7396 specs[count] = tmpl;
7397 specs[count++].specific = 0;
7398 }
7399 }
7400 }
7401 if (CURR_SLOT.qp_regno > 15)
7402 {
7403 specs[count] = tmpl;
7404 specs[count++].specific = 0;
7405 }
7406 }
7407 break;
7408
7409 case IA64_RS_PR63:
7410 if (note == 0)
7411 {
7412 specs[count++] = tmpl;
7413 }
7414 else if (note == 11)
7415 {
7416 if ((idesc->operands[0] == IA64_OPND_P1
7417 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7418 || (idesc->operands[1] == IA64_OPND_P2
7419 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7420 {
7421 specs[count++] = tmpl;
7422 }
7423 }
7424 else if (note == 12)
7425 {
7426 if (CURR_SLOT.qp_regno == 63)
7427 {
7428 specs[count++] = tmpl;
7429 }
7430 }
7431 else if (note == 7)
7432 {
7433 valueT mask = 0;
7434 if (idesc->operands[2] == IA64_OPND_IMM17)
7435 mask = CURR_SLOT.opnd[2].X_add_number;
197865e8 7436 if (mask & ((valueT) 1<<63))
800eeca4
JW		 7437 {
7438 specs[count++] = tmpl;
7439 }
7440 }
7441 else if (note == 1)
7442 {
7443 if (rsrc_write)
7444 {
7445 for (i=0;i < idesc->num_outputs;i++)
7446 if ((idesc->operands[i] == IA64_OPND_P1
7447 || idesc->operands[i] == IA64_OPND_P2)
7448 && CURR_SLOT.opnd[i].X_add_number - REG_P == 63)
7449 {
7450 specs[count++] = tmpl;
7451 }
7452 }
7453 else
7454 {
7455 if (CURR_SLOT.qp_regno == 63)
7456 {
7457 specs[count++] = tmpl;
7458 }
7459 }
7460 }
7461 else
7462 {
7463 UNHANDLED;
7464 }
7465 break;
7466
7467 case IA64_RS_RSE:
7468 /* FIXME we can identify some individual RSE written resources, but RSE
7469 read resources have not yet been completely identified, so for now
7470 treat RSE as a single resource */
7471 if (strncmp (idesc->name, "mov", 3) == 0)
7472 {
7473 if (rsrc_write)
7474 {
7475 if (idesc->operands[0] == IA64_OPND_AR3
7476 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7477 {
7478 specs[count] = tmpl;
7479 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7480 }
7481 }
7482 else
7483 {
7484 if (idesc->operands[0] == IA64_OPND_AR3)
7485 {
7486 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7487 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7488 {
7489 specs[count++] = tmpl;
7490 }
7491 }
7492 else if (idesc->operands[1] == IA64_OPND_AR3)
7493 {
7494 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7495 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7496 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7497 {
7498 specs[count++] = tmpl;
7499 }
7500 }
7501 }
7502 }
197865e8 7503 else
800eeca4
JW		 7504 {
7505 specs[count++] = tmpl;
7506 }
7507 break;
7508
7509 case IA64_RS_ANY:
7510 /* FIXME -- do any of these need to be non-specific? */
7511 specs[count++] = tmpl;
7512 break;
7513
7514 default:
7515 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7516 break;
7517 }
7518
7519 return count;
7520}
7521
7522/* Clear branch flags on marked resources. This breaks the link between the
197865e8 7523 QP of the marking instruction and a subsequent branch on the same QP.
800eeca4
JW		 7524*/
7525static void
7526clear_qp_branch_flag (mask)
7527 valueT mask;
7528{
7529 int i;
7530 for (i = 0;i < regdepslen;i++)
7531 {
197865e8 7532 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
800eeca4
JW		 7533 if ((bit & mask) != 0)
7534 {
7535 regdeps[i].link_to_qp_branch = 0;
7536 }
7537 }
7538}
7539
197865e8 7540/* Remove any mutexes which contain any of the PRs indicated in the mask.
800eeca4
JW		 7541
7542 Any changes to a PR clears the mutex relations which include that PR.
197865e8 7543*/
800eeca4
JW		 7544static void
7545clear_qp_mutex (mask)
7546 valueT mask;
7547{
7548 int i;
7549
7550 i = 0;
7551 while (i < qp_mutexeslen)
7552 {
7553 if ((qp_mutexes[i].prmask & mask) != 0)
7554 {
7555 if (md.debug_dv)
7556 {
7557 fprintf (stderr, " Clearing mutex relation");
7558 print_prmask (qp_mutexes[i].prmask);
7559 fprintf (stderr, "\n");
7560 }
7561 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
7562 }
7563 else
7564 ++i;
7565 }
7566}
7567
7568/* Clear implies relations which contain PRs in the given masks.
7569 P1_MASK indicates the source of the implies relation, while P2_MASK
7570 indicates the implied PR.
7571*/
7572static void
7573clear_qp_implies (p1_mask, p2_mask)
7574 valueT p1_mask;
7575 valueT p2_mask;
7576{
7577 int i;
7578
7579 i = 0;
7580 while (i < qp_implieslen)
7581 {
197865e8
KH		 7582 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
7583 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
800eeca4
JW		 7584 {
7585 if (md.debug_dv)
197865e8 7586 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
800eeca4
JW		 7587 qp_implies[i].p1, qp_implies[i].p2);
7588 qp_implies[i] = qp_implies[--qp_implieslen];
7589 }
197865e8 7590 else
800eeca4
JW		 7591 ++i;
7592 }
7593}
7594
7595/* add the PRs specified to the list of implied relations */
7596static void
7597add_qp_imply (p1, p2)
7598 int p1, p2;
7599{
7600 valueT mask;
7601 valueT bit;
7602 int i;
7603
7604 /* p0 is not meaningful here */
7605 if (p1 == 0 || p2 == 0)
7606 abort ();
7607
7608 if (p1 == p2)
7609 return;
7610
7611 /* if it exists already, ignore it */
7612 for (i=0;i < qp_implieslen;i++)
7613 {
197865e8 7614 if (qp_implies[i].p1 == p1
800eeca4
JW		 7615 && qp_implies[i].p2 == p2
7616 && qp_implies[i].path == md.path
7617 && !qp_implies[i].p2_branched)
7618 return;
7619 }
7620
7621 if (qp_implieslen == qp_impliestotlen)
7622 {
7623 qp_impliestotlen += 20;
7624 qp_implies = (struct qp_imply *)
197865e8 7625 xrealloc ((void *)qp_implies,
800eeca4
JW		 7626 qp_impliestotlen * sizeof (struct qp_imply));
7627 }
7628 if (md.debug_dv)
7629 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
7630 qp_implies[qp_implieslen].p1 = p1;
7631 qp_implies[qp_implieslen].p2 = p2;
7632 qp_implies[qp_implieslen].path = md.path;
7633 qp_implies[qp_implieslen++].p2_branched = 0;
7634
7635 /* Add in the implied transitive relations; for everything that p2 implies,
7636 make p1 imply that, too; for everything that implies p1, make it imply p2
197865e8 7637 as well. */
800eeca4
JW		 7638 for (i=0;i < qp_implieslen;i++)
7639 {
7640 if (qp_implies[i].p1 == p2)
7641 add_qp_imply (p1, qp_implies[i].p2);
7642 if (qp_implies[i].p2 == p1)
7643 add_qp_imply (qp_implies[i].p1, p2);
7644 }
7645 /* Add in mutex relations implied by this implies relation; for each mutex
197865e8
KH		 7646 relation containing p2, duplicate it and replace p2 with p1. */
7647 bit = (valueT) 1 << p1;
7648 mask = (valueT) 1 << p2;
800eeca4
JW		 7649 for (i=0;i < qp_mutexeslen;i++)
7650 {
7651 if (qp_mutexes[i].prmask & mask)
7652 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
7653 }
7654}
7655
800eeca4
JW		 7656/* Add the PRs specified in the mask to the mutex list; this means that only
7657 one of the PRs can be true at any time. PR0 should never be included in
7658 the mask. */
7659static void
7660add_qp_mutex (mask)
7661 valueT mask;
7662{
7663 if (mask & 0x1)
7664 abort ();
7665
7666 if (qp_mutexeslen == qp_mutexestotlen)
7667 {
7668 qp_mutexestotlen += 20;
7669 qp_mutexes = (struct qpmutex *)
197865e8 7670 xrealloc ((void *)qp_mutexes,
800eeca4
JW		 7671 qp_mutexestotlen * sizeof (struct qpmutex));
7672 }
7673 if (md.debug_dv)
7674 {
7675 fprintf (stderr, " Registering mutex on");
7676 print_prmask (mask);
7677 fprintf (stderr, "\n");
7678 }
7679 qp_mutexes[qp_mutexeslen].path = md.path;
7680 qp_mutexes[qp_mutexeslen++].prmask = mask;
7681}
7682
7683static void
7684clear_register_values ()
7685{
7686 int i;
7687 if (md.debug_dv)
7688 fprintf (stderr, " Clearing register values\n");
7689 for (i=1;i < NELEMS(gr_values);i++)
7690 gr_values[i].known = 0;
7691}
7692
7693/* Keep track of register values/changes which affect DV tracking.
7694
7695 optimization note: should add a flag to classes of insns where otherwise we
7696 have to examine a group of strings to identify them.
7697
7698 */
7699static void
7700note_register_values (idesc)
7701 struct ia64_opcode *idesc;
7702{
7703 valueT qp_changemask = 0;
7704 int i;
7705
7706 /* invalidate values for registers being written to */
7707 for (i=0;i < idesc->num_outputs;i++)
7708 {
197865e8 7709 if (idesc->operands[i] == IA64_OPND_R1
800eeca4
JW		 7710 || idesc->operands[i] == IA64_OPND_R2
7711 || idesc->operands[i] == IA64_OPND_R3)
7712 {
7713 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7714 if (regno > 0 && regno < NELEMS(gr_values))
7715 gr_values[regno].known = 0;
7716 }
50b81f19
JW		 7717 else if (idesc->operands[i] == IA64_OPND_R3_2)
7718 {
7719 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7720 if (regno > 0 && regno < 4)
7721 gr_values[regno].known = 0;
7722 }
197865e8 7723 else if (idesc->operands[i] == IA64_OPND_P1
800eeca4
JW		 7724 || idesc->operands[i] == IA64_OPND_P2)
7725 {
7726 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
197865e8 7727 qp_changemask |= (valueT) 1 << regno;
800eeca4
JW		 7728 }
7729 else if (idesc->operands[i] == IA64_OPND_PR)
7730 {
197865e8
KH		 7731 if (idesc->operands[2] & (valueT) 0x10000)
7732 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
7733 else
800eeca4
JW		 7734 qp_changemask = idesc->operands[2];
7735 break;
7736 }
7737 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
7738 {
197865e8
KH		 7739 if (idesc->operands[1] & ((valueT) 1 << 43))
7740 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
800eeca4
JW		 7741 else
7742 qp_changemask = idesc->operands[1];
197865e8 7743 qp_changemask &= ~(valueT) 0xFFFF;
800eeca4
JW		 7744 break;
7745 }
7746 }
7747
7748 /* Always clear qp branch flags on any PR change */
7749 /* FIXME there may be exceptions for certain compares */
7750 clear_qp_branch_flag (qp_changemask);
7751
7752 /* invalidate rotating registers on insns which affect RRBs in CFM */
7753 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
7754 {
197865e8 7755 qp_changemask |= ~(valueT) 0xFFFF;
800eeca4
JW		 7756 if (strcmp (idesc->name, "clrrrb.pr") != 0)
7757 {
7758 for (i=32;i < 32+md.rot.num_regs;i++)
7759 gr_values[i].known = 0;
7760 }
7761 clear_qp_mutex (qp_changemask);
7762 clear_qp_implies (qp_changemask, qp_changemask);
7763 }
7764 /* after a call, all register values are undefined, except those marked
7765 as "safe" */
7766 else if (strncmp (idesc->name, "br.call", 6) == 0
7767 || strncmp (idesc->name, "brl.call", 7) == 0)
7768 {
7769 // FIXME keep GR values which are marked as "safe_across_calls"
7770 clear_register_values ();
7771 clear_qp_mutex (~qp_safe_across_calls);
7772 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
7773 clear_qp_branch_flag (~qp_safe_across_calls);
7774 }
e9718fe1
TW		 7775 else if (is_interruption_or_rfi (idesc)
7776 || is_taken_branch (idesc))
7777 {
7778 clear_register_values ();
197865e8
KH		 7779 clear_qp_mutex (~(valueT) 0);
7780 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
e9718fe1 7781 }
800eeca4 7782 /* Look for mutex and implies relations */
197865e8 7783 else if ((idesc->operands[0] == IA64_OPND_P1
800eeca4
JW		 7784 || idesc->operands[0] == IA64_OPND_P2)
7785 && (idesc->operands[1] == IA64_OPND_P1
7786 || idesc->operands[1] == IA64_OPND_P2))
7787 {
7788 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
197865e8
KH		 7789 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7790 valueT p1mask = (valueT) 1 << p1;
7791 valueT p2mask = (valueT) 1 << p2;
800eeca4
JW		 7792
7793 /* if one of the PRs is PR0, we can't really do anything */
7794 if (p1 == 0 || p2 == 0)
7795 {
7796 if (md.debug_dv)
7797 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
7798 }
7799 /* In general, clear mutexes and implies which include P1 or P2,
7800 with the following exceptions */
7801 else if (strstr (idesc->name, ".or.andcm") != NULL)
7802 {
7803 add_qp_mutex (p1mask | p2mask);
7804 clear_qp_implies (p2mask, p1mask);
7805 }
7806 else if (strstr (idesc->name, ".and.orcm") != NULL)
7807 {
7808 add_qp_mutex (p1mask | p2mask);
7809 clear_qp_implies (p1mask, p2mask);
7810 }
7811 else if (strstr (idesc->name, ".and") != NULL)
7812 {
7813 clear_qp_implies (0, p1mask | p2mask);
7814 }
7815 else if (strstr (idesc->name, ".or") != NULL)
7816 {
7817 clear_qp_mutex (p1mask | p2mask);
7818 clear_qp_implies (p1mask | p2mask, 0);
7819 }
7820 else
7821 {
7822 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
7823 if (strstr (idesc->name, ".unc") != NULL)
7824 {
7825 add_qp_mutex (p1mask | p2mask);
7826 if (CURR_SLOT.qp_regno != 0)
7827 {
197865e8 7828 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
800eeca4 7829 CURR_SLOT.qp_regno);
197865e8 7830 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
800eeca4
JW		 7831 CURR_SLOT.qp_regno);
7832 }
7833 }
7834 else if (CURR_SLOT.qp_regno == 0)
7835 {
7836 add_qp_mutex (p1mask | p2mask);
7837 }
197865e8 7838 else
800eeca4
JW		 7839 {
7840 clear_qp_mutex (p1mask | p2mask);
7841 }
7842 }
7843 }
7844 /* Look for mov imm insns into GRs */
7845 else if (idesc->operands[0] == IA64_OPND_R1
7846 && (idesc->operands[1] == IA64_OPND_IMM22
7847 || idesc->operands[1] == IA64_OPND_IMMU64)
7848 && (strcmp(idesc->name, "mov") == 0
7849 || strcmp(idesc->name, "movl") == 0))
7850 {
7851 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7852 if (regno > 0 && regno < NELEMS(gr_values))
7853 {
7854 gr_values[regno].known = 1;
7855 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
7856 gr_values[regno].path = md.path;
7857 if (md.debug_dv)
197865e8 7858 fprintf (stderr, " Know gr%d = 0x%llx\n",
800eeca4
JW		 7859 regno, gr_values[regno].value);
7860 }
7861 }
197865e8 7862 else
800eeca4
JW		 7863 {
7864 clear_qp_mutex (qp_changemask);
7865 clear_qp_implies (qp_changemask, qp_changemask);
7866 }
7867}
7868
7869/* Return whether the given predicate registers are currently mutex */
7870static int
7871qp_mutex (p1, p2, path)
7872 int p1;
7873 int p2;
7874 int path;
7875{
7876 int i;
7877 valueT mask;
7878
7879 if (p1 != p2)
7880 {
197865e8 7881 mask = ((valueT) 1<<p1) | (valueT) 1<<p2;
800eeca4
JW		 7882 for (i=0;i < qp_mutexeslen;i++)
7883 {
7884 if (qp_mutexes[i].path >= path
7885 && (qp_mutexes[i].prmask & mask) == mask)
7886 return 1;
7887 }
7888 }
7889 return 0;
7890}
7891
7892/* Return whether the given resource is in the given insn's list of chks
7893 Return 1 if the conflict is absolutely determined, 2 if it's a potential
197865e8
KH		 7894 conflict.
7895 */
800eeca4
JW		 7896static int
7897resources_match (rs, idesc, note, qp_regno, path)
7898 struct rsrc *rs;
7899 struct ia64_opcode *idesc;
7900 int note;
7901 int qp_regno;
7902 int path;
7903{
7904 struct rsrc specs[MAX_SPECS];
7905 int count;
7906
7907 /* If the marked resource's qp_regno and the given qp_regno are mutex,
7908 we don't need to check. One exception is note 11, which indicates that
7909 target predicates are written regardless of PR[qp]. */
197865e8 7910 if (qp_mutex (rs->qp_regno, qp_regno, path)
800eeca4
JW		 7911 && note != 11)
7912 return 0;
7913
7914 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
7915 while (count-- > 0)
7916 {
7917 /* UNAT checking is a bit more specific than other resources */
7918 if (rs->dependency->specifier == IA64_RS_AR_UNAT
7919 && specs[count].mem_offset.hint
7920 && rs->mem_offset.hint)
7921 {
7922 if (rs->mem_offset.base == specs[count].mem_offset.base)
7923 {
197865e8 7924 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
800eeca4
JW		 7925 ((specs[count].mem_offset.offset >> 3) & 0x3F))
7926 return 1;
7927 else
7928 continue;
7929 }
7930 }
7931
7932 /* If either resource is not specific, conservatively assume a conflict
197865e8 7933 */
800eeca4
JW		 7934 if (!specs[count].specific || !rs->specific)
7935 return 2;
7936 else if (specs[count].index == rs->index)
7937 return 1;
7938 }
7939#if 0
7940 if (md.debug_dv)
7941 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
7942#endif
7943
7944 return 0;
7945}
7946
7947/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
7948 insert a stop to create the break. Update all resource dependencies
7949 appropriately. If QP_REGNO is non-zero, only apply the break to resources
7950 which use the same QP_REGNO and have the link_to_qp_branch flag set.
7951 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
197865e8
KH		 7952 instruction.
7953*/
800eeca4
JW		 7954
7955static void
7956insn_group_break (insert_stop, qp_regno, save_current)
7957 int insert_stop;
7958 int qp_regno;
7959 int save_current;
7960{
7961 int i;
7962
7963 if (insert_stop && md.num_slots_in_use > 0)
7964 PREV_SLOT.end_of_insn_group = 1;
7965
7966 if (md.debug_dv)
7967 {
197865e8 7968 fprintf (stderr, " Insn group break%s",
800eeca4
JW		 7969 (insert_stop ? " (w/stop)" : ""));
7970 if (qp_regno != 0)
7971 fprintf (stderr, " effective for QP=%d", qp_regno);
7972 fprintf (stderr, "\n");
7973 }
7974
7975 i = 0;
7976 while (i < regdepslen)
7977 {
7978 const struct ia64_dependency *dep = regdeps[i].dependency;
7979
7980 if (qp_regno != 0
7981 && regdeps[i].qp_regno != qp_regno)
7982 {
7983 ++i;
7984 continue;
7985 }
7986
7987 if (save_current
7988 && CURR_SLOT.src_file == regdeps[i].file
7989 && CURR_SLOT.src_line == regdeps[i].line)
7990 {
7991 ++i;
7992 continue;
7993 }
7994
7995 /* clear dependencies which are automatically cleared by a stop, or
7996 those that have reached the appropriate state of insn serialization */
7997 if (dep->semantics == IA64_DVS_IMPLIED
7998 || dep->semantics == IA64_DVS_IMPLIEDF
7999 || regdeps[i].insn_srlz == STATE_SRLZ)
8000 {
8001 print_dependency ("Removing", i);
8002 regdeps[i] = regdeps[--regdepslen];
8003 }
8004 else
8005 {
8006 if (dep->semantics == IA64_DVS_DATA
8007 || dep->semantics == IA64_DVS_INSTR
8008 || dep->semantics == IA64_DVS_SPECIFIC)
8009 {
8010 if (regdeps[i].insn_srlz == STATE_NONE)
8011 regdeps[i].insn_srlz = STATE_STOP;
8012 if (regdeps[i].data_srlz == STATE_NONE)
8013 regdeps[i].data_srlz = STATE_STOP;
8014 }
8015 ++i;
8016 }
8017 }
8018}
8019
8020/* Add the given resource usage spec to the list of active dependencies */
197865e8 8021static void
800eeca4
JW		 8022mark_resource (idesc, dep, spec, depind, path)
8023 struct ia64_opcode *idesc;
8024 const struct ia64_dependency *dep;
8025 struct rsrc *spec;
8026 int depind;
8027 int path;
8028{
8029 if (regdepslen == regdepstotlen)
8030 {
8031 regdepstotlen += 20;
8032 regdeps = (struct rsrc *)
197865e8 8033 xrealloc ((void *)regdeps,
800eeca4
JW		 8034 regdepstotlen * sizeof(struct rsrc));
8035 }
8036
8037 regdeps[regdepslen] = *spec;
8038 regdeps[regdepslen].depind = depind;
8039 regdeps[regdepslen].path = path;
8040 regdeps[regdepslen].file = CURR_SLOT.src_file;
8041 regdeps[regdepslen].line = CURR_SLOT.src_line;
8042
8043 print_dependency ("Adding", regdepslen);
8044
8045 ++regdepslen;
8046}
8047
8048static void
8049print_dependency (action, depind)
8050 const char *action;
8051 int depind;
8052{
8053 if (md.debug_dv)
8054 {
197865e8 8055 fprintf (stderr, " %s %s '%s'",
800eeca4
JW		 8056 action, dv_mode[(regdeps[depind].dependency)->mode],
8057 (regdeps[depind].dependency)->name);
8058 if (regdeps[depind].specific && regdeps[depind].index != 0)
8059 fprintf (stderr, " (%d)", regdeps[depind].index);
8060 if (regdeps[depind].mem_offset.hint)
8061 fprintf (stderr, " 0x%llx+0x%llx",
8062 regdeps[depind].mem_offset.base,
8063 regdeps[depind].mem_offset.offset);
8064 fprintf (stderr, "\n");
8065 }
8066}
8067
8068static void
8069instruction_serialization ()
8070{
8071 int i;
8072 if (md.debug_dv)
8073 fprintf (stderr, " Instruction serialization\n");
8074 for (i=0;i < regdepslen;i++)
8075 if (regdeps[i].insn_srlz == STATE_STOP)
8076 regdeps[i].insn_srlz = STATE_SRLZ;
8077}
8078
8079static void
8080data_serialization ()
8081{
8082 int i = 0;
8083 if (md.debug_dv)
8084 fprintf (stderr, " Data serialization\n");
8085 while (i < regdepslen)
8086 {
8087 if (regdeps[i].data_srlz == STATE_STOP
8088 /* Note: as of 991210, all "other" dependencies are cleared by a
8089 data serialization. This might change with new tables */
8090 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8091 {
8092 print_dependency ("Removing", i);
8093 regdeps[i] = regdeps[--regdepslen];
8094 }
8095 else
8096 ++i;
8097 }
8098}
8099
8100/* Insert stops and serializations as needed to avoid DVs */
8101static void
8102remove_marked_resource (rs)
8103 struct rsrc *rs;
8104{
8105 switch (rs->dependency->semantics)
8106 {
8107 case IA64_DVS_SPECIFIC:
8108 if (md.debug_dv)
8109 fprintf (stderr, "Implementation-specific, assume worst case...\n");
197865e8 8110 /* ...fall through... */
800eeca4
JW		 8111 case IA64_DVS_INSTR:
8112 if (md.debug_dv)
8113 fprintf (stderr, "Inserting instr serialization\n");
8114 if (rs->insn_srlz < STATE_STOP)
8115 insn_group_break (1, 0, 0);
8116 if (rs->insn_srlz < STATE_SRLZ)
8117 {
8118 int oldqp = CURR_SLOT.qp_regno;
8119 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8120 /* Manually jam a srlz.i insn into the stream */
8121 CURR_SLOT.qp_regno = 0;
8122 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8123 instruction_serialization ();
8124 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8125 if (++md.num_slots_in_use >= NUM_SLOTS)
8126 emit_one_bundle ();
8127 CURR_SLOT.qp_regno = oldqp;
8128 CURR_SLOT.idesc = oldidesc;
8129 }
8130 insn_group_break (1, 0, 0);
8131 break;
8132 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
8133 "other" types of DV are eliminated
8134 by a data serialization */
8135 case IA64_DVS_DATA:
8136 if (md.debug_dv)
8137 fprintf (stderr, "Inserting data serialization\n");
8138 if (rs->data_srlz < STATE_STOP)
8139 insn_group_break (1, 0, 0);
8140 {
8141 int oldqp = CURR_SLOT.qp_regno;
8142 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8143 /* Manually jam a srlz.d insn into the stream */
8144 CURR_SLOT.qp_regno = 0;
8145 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8146 data_serialization ();
8147 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8148 if (++md.num_slots_in_use >= NUM_SLOTS)
8149 emit_one_bundle ();
8150 CURR_SLOT.qp_regno = oldqp;
8151 CURR_SLOT.idesc = oldidesc;
8152 }
8153 break;
8154 case IA64_DVS_IMPLIED:
8155 case IA64_DVS_IMPLIEDF:
8156 if (md.debug_dv)
8157 fprintf (stderr, "Inserting stop\n");
8158 insn_group_break (1, 0, 0);
8159 break;
8160 default:
8161 break;
8162 }
8163}
8164
8165/* Check the resources used by the given opcode against the current dependency
197865e8 8166 list.
800eeca4
JW		 8167
8168 The check is run once for each execution path encountered. In this case,
8169 a unique execution path is the sequence of instructions following a code
8170 entry point, e.g. the following has three execution paths, one starting
8171 at L0, one at L1, and one at L2.
197865e8 8172
800eeca4
JW		 8173 L0: nop
8174 L1: add
8175 L2: add
197865e8 8176 br.ret
800eeca4
JW		 8177*/
8178static void
8179check_dependencies (idesc)
8180 struct ia64_opcode *idesc;
8181{
8182 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8183 int path;
8184 int i;
8185
8186 /* Note that the number of marked resources may change within the
197865e8 8187 loop if in auto mode. */
800eeca4
JW		 8188 i = 0;
8189 while (i < regdepslen)
8190 {
8191 struct rsrc *rs = &regdeps[i];
8192 const struct ia64_dependency *dep = rs->dependency;
8193 int chkind;
8194 int note;
8195 int start_over = 0;
8196
8197 if (dep->semantics == IA64_DVS_NONE
8198 || (chkind = depends_on (rs->depind, idesc)) == -1)
8199 {
8200 ++i; continue;
8201 }
8202
8203 note = NOTE(opdeps->chks[chkind]);
8204
8205 /* Check this resource against each execution path seen thus far */
8206 for (path=0;path <= md.path;path++)
8207 {
8208 int matchtype;
8209
8210 /* If the dependency wasn't on the path being checked, ignore it */
8211 if (rs->path < path)
8212 continue;
8213
8214 /* If the QP for this insn implies a QP which has branched, don't
8215 bother checking. Ed. NOTE: I don't think this check is terribly
8216 useful; what's the point of generating code which will only be
197865e8 8217 reached if its QP is zero?
800eeca4
JW		 8218 This code was specifically inserted to handle the following code,
8219 based on notes from Intel's DV checking code, where p1 implies p2.
8220
8221 mov r4 = 2
8222 (p2) br.cond L
8223 (p1) mov r4 = 7
8224
197865e8
KH		 8225 */
8226 if (CURR_SLOT.qp_regno != 0)
800eeca4
JW		 8227 {
8228 int skip = 0;
8229 int implies;
8230 for (implies=0;implies < qp_implieslen;implies++)
8231 {
8232 if (qp_implies[implies].path >= path
8233 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8234 && qp_implies[implies].p2_branched)
8235 {
8236 skip = 1;
8237 break;
8238 }
8239 }
8240 if (skip)
8241 continue;
8242 }
8243
197865e8 8244 if ((matchtype = resources_match (rs, idesc, note,
800eeca4
JW		 8245 CURR_SLOT.qp_regno, path)) != 0)
8246 {
8247 char msg[1024];
8248 char pathmsg[256] = "";
8249 char indexmsg[256] = "";
8250 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8251
8252 if (path != 0)
8253 sprintf (pathmsg, " when entry is at label '%s'",
8254 md.entry_labels[path-1]);
8255 if (rs->specific && rs->index != 0)
197865e8 8256 sprintf (indexmsg, ", specific resource number is %d",
800eeca4
JW		 8257 rs->index);
8258 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
197865e8 8259 idesc->name,
800eeca4 8260 (certain ? "violates" : "may violate"),
197865e8 8261 dv_mode[dep->mode], dep->name,
800eeca4
JW		 8262 dv_sem[dep->semantics],
8263 pathmsg, indexmsg);
8264
8265 if (md.explicit_mode)
8266 {
8267 as_warn ("%s", msg);
8268 if (path < md.path)
8269 as_warn (_("Only the first path encountering the conflict "
8270 "is reported"));
8271 as_warn_where (rs->file, rs->line,
8272 _("This is the location of the "
8273 "conflicting usage"));
8274 /* Don't bother checking other paths, to avoid duplicating
8275 the same warning */
8276 break;
8277 }
8278 else
8279 {
8280 if (md.debug_dv)
8281 fprintf(stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
197865e8 8282
800eeca4 8283 remove_marked_resource (rs);
197865e8 8284
800eeca4
JW		 8285 /* since the set of dependencies has changed, start over */
8286 /* FIXME -- since we're removing dvs as we go, we
197865e8 8287 probably don't really need to start over... */
800eeca4
JW		 8288 start_over = 1;
8289 break;
8290 }
8291 }
8292 }
8293 if (start_over)
8294 i = 0;
8295 else
8296 ++i;
8297 }
8298}
8299
8300/* register new dependencies based on the given opcode */
8301static void
8302mark_resources (idesc)
8303 struct ia64_opcode *idesc;
8304{
8305 int i;
8306 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8307 int add_only_qp_reads = 0;
8308
8309 /* A conditional branch only uses its resources if it is taken; if it is
8310 taken, we stop following that path. The other branch types effectively
8311 *always* write their resources. If it's not taken, register only QP
197865e8 8312 reads. */
800eeca4
JW		 8313 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8314 {
8315 add_only_qp_reads = 1;
8316 }
8317
8318 if (md.debug_dv)
8319 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8320
8321 for (i=0;i < opdeps->nregs;i++)
8322 {
8323 const struct ia64_dependency *dep;
8324 struct rsrc specs[MAX_SPECS];
8325 int note;
8326 int path;
8327 int count;
197865e8 8328
800eeca4
JW		 8329 dep = ia64_find_dependency (opdeps->regs[i]);
8330 note = NOTE(opdeps->regs[i]);
8331
8332 if (add_only_qp_reads
8333 && !(dep->mode == IA64_DV_WAR
8334 && (dep->specifier == IA64_RS_PR
8335 || dep->specifier == IA64_RS_PR63)))
8336 continue;
8337
8338 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8339
8340#if 0
8341 if (md.debug_dv && !count)
197865e8 8342 fprintf (stderr, " No %s %s usage found (path %d)\n",
800eeca4
JW		 8343 dv_mode[dep->mode], dep->name, md.path);
8344#endif
197865e8 8345
800eeca4
JW		 8346 while (count-- > 0)
8347 {
197865e8 8348 mark_resource (idesc, dep, &specs[count],
800eeca4
JW		 8349 DEP(opdeps->regs[i]), md.path);
8350 }
8351
8352 /* The execution path may affect register values, which may in turn
197865e8 8353 affect which indirect-access resources are accessed. */
800eeca4
JW		 8354 switch (dep->specifier)
8355 {
8356 default:
8357 break;
8358 case IA64_RS_CPUID:
8359 case IA64_RS_DBR:
8360 case IA64_RS_IBR:
8361 case IA64_RS_MSR:
8362 case IA64_RS_PKR:
8363 case IA64_RS_PMC:
8364 case IA64_RS_PMD:
8365 case IA64_RS_RR:
8366 for (path=0;path < md.path;path++)
8367 {
8368 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8369 while (count-- > 0)
197865e8 8370 mark_resource (idesc, dep, &specs[count],
800eeca4
JW		 8371 DEP(opdeps->regs[i]), path);
8372 }
8373 break;
8374 }
8375 }
8376}
8377
8378/* remove dependencies when they no longer apply */
8379static void
8380update_dependencies (idesc)
8381 struct ia64_opcode *idesc;
8382{
8383 int i;
8384
8385 if (strcmp (idesc->name, "srlz.i") == 0)
8386 {
8387 instruction_serialization ();
8388 }
8389 else if (strcmp (idesc->name, "srlz.d") == 0)
8390 {
8391 data_serialization ();
8392 }
8393 else if (is_interruption_or_rfi (idesc)
8394 || is_taken_branch (idesc))
8395 {
8396 /* although technically the taken branch doesn't clear dependencies
8397 which require a srlz.[id], we don't follow the branch; the next
8398 instruction is assumed to start with a clean slate */
8399 regdepslen = 0;
800eeca4
JW		 8400 md.path = 0;
8401 }
8402 else if (is_conditional_branch (idesc)
8403 && CURR_SLOT.qp_regno != 0)
8404 {
8405 int is_call = strstr (idesc->name, ".call") != NULL;
8406
8407 for (i=0;i < qp_implieslen;i++)
8408 {
8409 /* if the conditional branch's predicate is implied by the predicate
8410 in an existing dependency, remove that dependency */
8411 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8412 {
8413 int depind = 0;
8414 /* note that this implied predicate takes a branch so that if
8415 a later insn generates a DV but its predicate implies this
8416 one, we can avoid the false DV warning */
8417 qp_implies[i].p2_branched = 1;
8418 while (depind < regdepslen)
8419 {
8420 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8421 {
8422 print_dependency ("Removing", depind);
8423 regdeps[depind] = regdeps[--regdepslen];
8424 }
8425 else
8426 ++depind;
8427 }
8428 }
8429 }
8430 /* Any marked resources which have this same predicate should be
8431 cleared, provided that the QP hasn't been modified between the
197865e8 8432 marking instruction and the branch.
800eeca4
JW		 8433 */
8434 if (is_call)
8435 {
8436 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8437 }
8438 else
8439 {
8440 i = 0;
8441 while (i < regdepslen)
8442 {
8443 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8444 && regdeps[i].link_to_qp_branch
197865e8 8445 && (regdeps[i].file != CURR_SLOT.src_file
800eeca4
JW		 8446 || regdeps[i].line != CURR_SLOT.src_line))
8447 {
8448 /* Treat like a taken branch */
8449 print_dependency ("Removing", i);
8450 regdeps[i] = regdeps[--regdepslen];
8451 }
8452 else
8453 ++i;
8454 }
8455 }
8456 }
8457}
8458
8459/* Examine the current instruction for dependency violations. */
8460static int
8461check_dv (idesc)
8462 struct ia64_opcode *idesc;
8463{
8464 if (md.debug_dv)
8465 {
197865e8
KH		 8466 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
8467 idesc->name, CURR_SLOT.src_line,
8468 idesc->dependencies->nchks,
800eeca4
JW		 8469 idesc->dependencies->nregs);
8470 }
8471
197865e8 8472 /* Look through the list of currently marked resources; if the current
800eeca4 8473 instruction has the dependency in its chks list which uses that resource,
197865e8 8474 check against the specific resources used.
800eeca4
JW		 8475 */
8476 check_dependencies (idesc);
8477
8478 /*
8479 Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8480 then add them to the list of marked resources.
8481 */
8482 mark_resources (idesc);
8483
8484 /* There are several types of dependency semantics, and each has its own
197865e8
KH		 8485 requirements for being cleared
8486
800eeca4
JW		 8487 Instruction serialization (insns separated by interruption, rfi, or
8488 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8489
8490 Data serialization (instruction serialization, or writer + srlz.d +
8491 reader, where writer and srlz.d are in separate groups) clears
8492 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8493 always be the case).
8494
8495 Instruction group break (groups separated by stop, taken branch,
8496 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8497 */
8498 update_dependencies (idesc);
8499
8500 /* Sometimes, knowing a register value allows us to avoid giving a false DV
197865e8 8501 warning. Keep track of as many as possible that are useful. */
800eeca4
JW		 8502 note_register_values (idesc);
8503
197865e8 8504 /* We don't need or want this anymore. */
800eeca4
JW		 8505 md.mem_offset.hint = 0;
8506
8507 return 0;
8508}
8509
8510/* Translate one line of assembly. Pseudo ops and labels do not show
8511 here. */
8512void
8513md_assemble (str)
8514 char *str;
8515{
8516 char *saved_input_line_pointer, *mnemonic;
8517 const struct pseudo_opcode *pdesc;
8518 struct ia64_opcode *idesc;
8519 unsigned char qp_regno;
8520 unsigned int flags;
8521 int ch;
8522
8523 saved_input_line_pointer = input_line_pointer;
8524 input_line_pointer = str;
8525
8526 /* extract the opcode (mnemonic): */
8527
8528 mnemonic = input_line_pointer;
8529 ch = get_symbol_end ();
8530 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
8531 if (pdesc)
8532 {
8533 *input_line_pointer = ch;
8534 (*pdesc->handler) (pdesc->arg);
8535 goto done;
8536 }
8537
8538 /* find the instruction descriptor matching the arguments: */
8539
8540 idesc = ia64_find_opcode (mnemonic);
8541 *input_line_pointer = ch;
8542 if (!idesc)
8543 {
8544 as_bad ("Unknown opcode `%s'", mnemonic);
8545 goto done;
8546 }
8547
8548 idesc = parse_operands (idesc);
8549 if (!idesc)
8550 goto done;
8551
8552 /* Handle the dynamic ops we can handle now: */
8553 if (idesc->type == IA64_TYPE_DYN)
8554 {
8555 if (strcmp (idesc->name, "add") == 0)
8556 {
8557 if (CURR_SLOT.opnd[2].X_op == O_register
8558 && CURR_SLOT.opnd[2].X_add_number < 4)
8559 mnemonic = "addl";
8560 else
8561 mnemonic = "adds";
3d56ab85 8562 ia64_free_opcode (idesc);
800eeca4
JW		 8563 idesc = ia64_find_opcode (mnemonic);
8564#if 0
8565 know (!idesc->next);
8566#endif
8567 }
8568 else if (strcmp (idesc->name, "mov") == 0)
8569 {
8570 enum ia64_opnd opnd1, opnd2;
8571 int rop;
8572
8573 opnd1 = idesc->operands[0];
8574 opnd2 = idesc->operands[1];
8575 if (opnd1 == IA64_OPND_AR3)
8576 rop = 0;
8577 else if (opnd2 == IA64_OPND_AR3)
8578 rop = 1;
8579 else
8580 abort ();
8581 if (CURR_SLOT.opnd[rop].X_op == O_register
8582 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
8583 mnemonic = "mov.i";
8584 else
8585 mnemonic = "mov.m";
3d56ab85 8586 ia64_free_opcode (idesc);
800eeca4
JW		 8587 idesc = ia64_find_opcode (mnemonic);
8588 while (idesc != NULL
8589 && (idesc->operands[0] != opnd1
8590 || idesc->operands[1] != opnd2))
8591 idesc = get_next_opcode (idesc);
8592 }
8593 }
8594
8595 qp_regno = 0;
8596 if (md.qp.X_op == O_register)
8597 qp_regno = md.qp.X_add_number - REG_P;
8598
8599 flags = idesc->flags;
8600
8601 if ((flags & IA64_OPCODE_FIRST) != 0)
8602 insn_group_break (1, 0, 0);
8603
8604 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
8605 {
8606 as_bad ("`%s' cannot be predicated", idesc->name);
8607 goto done;
8608 }
8609
8610 /* build the instruction: */
8611 CURR_SLOT.qp_regno = qp_regno;
8612 CURR_SLOT.idesc = idesc;
8613 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
8614 if (debug_type == DEBUG_DWARF2)
8615 dwarf2_where (&CURR_SLOT.debug_line);
8616
8617 /* Add unwind entry, if there is one. */
e0c9811a 8618 if (unwind.current_entry)
800eeca4 8619 {
e0c9811a
JW		 8620 CURR_SLOT.unwind_record = unwind.current_entry;
8621 unwind.current_entry = NULL;
800eeca4
JW		 8622 }
8623
8624 /* check for dependency violations */
8625 if (md.detect_dv)
8626 check_dv(idesc);
8627
8628 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8629 if (++md.num_slots_in_use >= NUM_SLOTS)
8630 emit_one_bundle ();
8631
8632 if ((flags & IA64_OPCODE_LAST) != 0)
8633 insn_group_break (1, 0, 0);
8634
8635 md.last_text_seg = now_seg;
8636
8637 done:
8638 input_line_pointer = saved_input_line_pointer;
8639}
8640
8641/* Called when symbol NAME cannot be found in the symbol table.
8642 Should be used for dynamic valued symbols only. */
8643symbolS*
8644md_undefined_symbol (name)
8645 char *name;
8646{
8647 return 0;
8648}
8649
8650/* Called for any expression that can not be recognized. When the
8651 function is called, `input_line_pointer' will point to the start of
8652 the expression. */
8653void
8654md_operand (e)
8655 expressionS *e;
8656{
8657 enum pseudo_type pseudo_type;
e0c9811a 8658 const char *name;
800eeca4
JW		 8659 size_t len;
8660 int ch, i;
8661
8662 switch (*input_line_pointer)
8663 {
8664 case '@':
8665 /* find what relocation pseudo-function we're dealing with: */
8666 pseudo_type = 0;
8667 ch = *++input_line_pointer;
8668 for (i = 0; i < NELEMS (pseudo_func); ++i)
8669 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
8670 {
8671 len = strlen (pseudo_func[i].name);
8672 if (strncmp (pseudo_func[i].name + 1,
8673 input_line_pointer + 1, len - 1) == 0
8674 && !is_part_of_name (input_line_pointer[len]))
8675 {
8676 input_line_pointer += len;
8677 pseudo_type = pseudo_func[i].type;
8678 break;
8679 }
8680 }
8681 switch (pseudo_type)
8682 {
8683 case PSEUDO_FUNC_RELOC:
8684 SKIP_WHITESPACE ();
8685 if (*input_line_pointer != '(')
8686 {
8687 as_bad ("Expected '('");
8688 goto err;
8689 }
8690 ++input_line_pointer; /* skip '(' */
8691 expression (e);
8692 if (*input_line_pointer++ != ')')
8693 {
8694 as_bad ("Missing ')'");
8695 goto err;
8696 }
8697 if (e->X_op != O_symbol)
8698 {
8699 if (e->X_op != O_pseudo_fixup)
8700 {
8701 as_bad ("Not a symbolic expression");
8702 goto err;
8703 }
8704 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
8705 && i == FUNC_LT_RELATIVE)
8706 i = FUNC_LT_FPTR_RELATIVE;
8707 else
8708 {
8709 as_bad ("Illegal combination of relocation functions");
8710 goto err;
8711 }
8712 }
8713 /* make sure gas doesn't get rid of local symbols that are used
8714 in relocs: */
8715 e->X_op = O_pseudo_fixup;
8716 e->X_op_symbol = pseudo_func[i].u.sym;
8717 break;
8718
8719 case PSEUDO_FUNC_CONST:
8720 e->X_op = O_constant;
8721 e->X_add_number = pseudo_func[i].u.ival;
8722 break;
8723
e0c9811a
JW		 8724 case PSEUDO_FUNC_REG:
8725 e->X_op = O_register;
8726 e->X_add_number = pseudo_func[i].u.ival;
8727 break;
8728
800eeca4 8729 default:
e0c9811a
JW		 8730 name = input_line_pointer - 1;
8731 get_symbol_end ();
8732 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW		 8733 goto err;
8734 }
8735 break;
8736
8737 case '[':
8738 ++input_line_pointer;
8739 expression (e);
8740 if (*input_line_pointer != ']')
8741 {
8742 as_bad ("Closing bracket misssing");
8743 goto err;
8744 }
8745 else
8746 {
8747 if (e->X_op != O_register)
8748 as_bad ("Register expected as index");
8749
8750 ++input_line_pointer;
8751 e->X_op = O_index;
8752 }
8753 break;
8754
8755 default:
8756 break;
8757 }
8758 return;
8759
8760 err:
8761 ignore_rest_of_line ();
8762}
8763
8764/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8765 a section symbol plus some offset. For relocs involving @fptr(),
8766 directives we don't want such adjustments since we need to have the
8767 original symbol's name in the reloc. */
8768int
8769ia64_fix_adjustable (fix)
8770 fixS *fix;
8771{
8772 /* Prevent all adjustments to global symbols */
8773 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
8774 return 0;
8775
8776 switch (fix->fx_r_type)
8777 {
8778 case BFD_RELOC_IA64_FPTR64I:
8779 case BFD_RELOC_IA64_FPTR32MSB:
8780 case BFD_RELOC_IA64_FPTR32LSB:
8781 case BFD_RELOC_IA64_FPTR64MSB:
8782 case BFD_RELOC_IA64_FPTR64LSB:
8783 case BFD_RELOC_IA64_LTOFF_FPTR22:
8784 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8785 return 0;
8786 default:
8787 break;
8788 }
8789
8790 return 1;
8791}
8792
8793int
8794ia64_force_relocation (fix)
8795 fixS *fix;
8796{
8797 switch (fix->fx_r_type)
8798 {
8799 case BFD_RELOC_IA64_FPTR64I:
8800 case BFD_RELOC_IA64_FPTR32MSB:
8801 case BFD_RELOC_IA64_FPTR32LSB:
8802 case BFD_RELOC_IA64_FPTR64MSB:
8803 case BFD_RELOC_IA64_FPTR64LSB:
8804
8805 case BFD_RELOC_IA64_LTOFF22:
8806 case BFD_RELOC_IA64_LTOFF64I:
8807 case BFD_RELOC_IA64_LTOFF_FPTR22:
8808 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8809 case BFD_RELOC_IA64_PLTOFF22:
8810 case BFD_RELOC_IA64_PLTOFF64I:
8811 case BFD_RELOC_IA64_PLTOFF64MSB:
8812 case BFD_RELOC_IA64_PLTOFF64LSB:
8813 return 1;
8814
8815 default:
8816 return 0;
8817 }
8818 return 0;
8819}
8820
8821/* Decide from what point a pc-relative relocation is relative to,
8822 relative to the pc-relative fixup. Er, relatively speaking. */
8823long
8824ia64_pcrel_from_section (fix, sec)
8825 fixS *fix;
8826 segT sec;
8827{
8828 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
197865e8 8829
800eeca4
JW		 8830 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
8831 off &= ~0xfUL;
8832
8833 return off;
8834}
8835
8836/* This is called whenever some data item (not an instruction) needs a
8837 fixup. We pick the right reloc code depending on the byteorder
8838 currently in effect. */
8839void
8840ia64_cons_fix_new (f, where, nbytes, exp)
8841 fragS *f;
8842 int where;
8843 int nbytes;
8844 expressionS *exp;
8845{
8846 bfd_reloc_code_real_type code;
8847 fixS *fix;
8848
8849 switch (nbytes)
8850 {
8851 /* There are no reloc for 8 and 16 bit quantities, but we allow
8852 them here since they will work fine as long as the expression
8853 is fully defined at the end of the pass over the source file. */
8854 case 1: code = BFD_RELOC_8; break;
8855 case 2: code = BFD_RELOC_16; break;
8856 case 4:
8857 if (target_big_endian)
8858 code = BFD_RELOC_IA64_DIR32MSB;
8859 else
8860 code = BFD_RELOC_IA64_DIR32LSB;
8861 break;
8862
8863 case 8:
8864 if (target_big_endian)
8865 code = BFD_RELOC_IA64_DIR64MSB;
8866 else
8867 code = BFD_RELOC_IA64_DIR64LSB;
8868 break;
8869
8870 default:
8871 as_bad ("Unsupported fixup size %d", nbytes);
8872 ignore_rest_of_line ();
8873 return;
8874 }
8875 if (exp->X_op == O_pseudo_fixup)
8876 {
8877 /* ??? */
8878 exp->X_op = O_symbol;
8879 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
8880 }
8881 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
8882 /* We need to store the byte order in effect in case we're going
8883 to fix an 8 or 16 bit relocation (for which there no real
8884 relocs available). See md_apply_fix(). */
8885 fix->tc_fix_data.bigendian = target_big_endian;
8886}
8887
8888/* Return the actual relocation we wish to associate with the pseudo
8889 reloc described by SYM and R_TYPE. SYM should be one of the
197865e8 8890 symbols in the pseudo_func array, or NULL. */
800eeca4
JW		 8891
8892static bfd_reloc_code_real_type
8893ia64_gen_real_reloc_type (sym, r_type)
8894 struct symbol *sym;
8895 bfd_reloc_code_real_type r_type;
8896{
8897 bfd_reloc_code_real_type new = 0;
8898
8899 if (sym == NULL)
8900 {
8901 return r_type;
8902 }
8903
8904 switch (S_GET_VALUE (sym))
8905 {
8906 case FUNC_FPTR_RELATIVE:
8907 switch (r_type)
8908 {
8909 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
8910 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
8911 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
8912 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
8913 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
8914 default: break;
8915 }
8916 break;
8917
8918 case FUNC_GP_RELATIVE:
8919 switch (r_type)
8920 {
8921 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
8922 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
8923 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
8924 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
8925 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
8926 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
8927 default: break;
8928 }
8929 break;
8930
8931 case FUNC_LT_RELATIVE:
8932 switch (r_type)
8933 {
8934 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
8935 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
8936 default: break;
8937 }
8938 break;
8939
c67e42c9
RH		 8940 case FUNC_PC_RELATIVE:
8941 switch (r_type)
8942 {
8943 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
8944 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
8945 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
8946 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
8947 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
8948 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
8949 default: break;
8950 }
8951 break;
8952
800eeca4
JW		 8953 case FUNC_PLT_RELATIVE:
8954 switch (r_type)
8955 {
8956 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
8957 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
8958 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
8959 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
8960 default: break;
8961 }
8962 break;
8963
8964 case FUNC_SEC_RELATIVE:
8965 switch (r_type)
8966 {
8967 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
8968 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
8969 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
8970 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
8971 default: break;
8972 }
8973 break;
8974
8975 case FUNC_SEG_RELATIVE:
8976 switch (r_type)
8977 {
8978 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
8979 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
8980 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
8981 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
8982 default: break;
8983 }
8984 break;
8985
8986 case FUNC_LTV_RELATIVE:
8987 switch (r_type)
8988 {
8989 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
8990 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
8991 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
8992 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
8993 default: break;
8994 }
8995 break;
8996
8997 case FUNC_LT_FPTR_RELATIVE:
8998 switch (r_type)
8999 {
9000 case BFD_RELOC_IA64_IMM22:
9001 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9002 case BFD_RELOC_IA64_IMM64:
9003 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9004 default:
9005 break;
9006 }
9007 break;
9008 default:
9009 abort ();
9010 }
9011 /* Hmmmm. Should this ever occur? */
9012 if (new)
9013 return new;
9014 else
9015 return r_type;
9016}
9017
9018/* Here is where generate the appropriate reloc for pseudo relocation
9019 functions. */
9020void
9021ia64_validate_fix (fix)
9022 fixS *fix;
9023{
9024 switch (fix->fx_r_type)
9025 {
9026 case BFD_RELOC_IA64_FPTR64I:
9027 case BFD_RELOC_IA64_FPTR32MSB:
9028 case BFD_RELOC_IA64_FPTR64LSB:
9029 case BFD_RELOC_IA64_LTOFF_FPTR22:
9030 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9031 if (fix->fx_offset != 0)
9032 as_bad_where (fix->fx_file, fix->fx_line,
9033 "No addend allowed in @fptr() relocation");
9034 break;
9035 default:
9036 break;
9037 }
9038
9039 return;
9040}
9041
9042static void
9043fix_insn (fix, odesc, value)
9044 fixS *fix;
9045 const struct ia64_operand *odesc;
9046 valueT value;
9047{
9048 bfd_vma insn[3], t0, t1, control_bits;
9049 const char *err;
9050 char *fixpos;
9051 long slot;
9052
9053 slot = fix->fx_where & 0x3;
9054 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9055
c67e42c9 9056 /* Bundles are always in little-endian byte order */
800eeca4
JW		 9057 t0 = bfd_getl64 (fixpos);
9058 t1 = bfd_getl64 (fixpos + 8);
9059 control_bits = t0 & 0x1f;
9060 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9061 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9062 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9063
c67e42c9
RH		 9064 err = NULL;
9065 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 9066 {
c67e42c9
RH		 9067 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9068 insn[2] |= (((value & 0x7f) << 13)
9069 | (((value >> 7) & 0x1ff) << 27)
9070 | (((value >> 16) & 0x1f) << 22)
9071 | (((value >> 21) & 0x1) << 21)
9072 | (((value >> 63) & 0x1) << 36));
800eeca4 9073 }
c67e42c9
RH		 9074 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9075 {
9076 if (value & ~0x3fffffffffffffffULL)
9077 err = "integer operand out of range";
9078 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9079 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9080 }
9081 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9082 {
9083 value >>= 4;
9084 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9085 insn[2] |= ((((value >> 59) & 0x1) << 36)
9086 | (((value >> 0) & 0xfffff) << 13));
9087 }
9088 else
9089 err = (*odesc->insert) (odesc, value, insn + slot);
9090
9091 if (err)
9092 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW		 9093
9094 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9095 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9096 md_number_to_chars (fixpos + 0, t0, 8);
9097 md_number_to_chars (fixpos + 8, t1, 8);
800eeca4
JW		 9098}
9099
9100/* Attempt to simplify or even eliminate a fixup. The return value is
9101 ignored; perhaps it was once meaningful, but now it is historical.
9102 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9103
9104 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
197865e8 9105 (if possible). */
800eeca4
JW		 9106int
9107md_apply_fix3 (fix, valuep, seg)
9108 fixS *fix;
9109 valueT *valuep;
9110 segT seg;
9111{
9112 char *fixpos;
9113 valueT value = *valuep;
9114 int adjust = 0;
9115
9116 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9117
9118 if (fix->fx_pcrel)
9119 {
9120 switch (fix->fx_r_type)
9121 {
9122 case BFD_RELOC_IA64_DIR32MSB:
9123 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9124 adjust = 1;
9125 break;
9126
9127 case BFD_RELOC_IA64_DIR32LSB:
9128 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9129 adjust = 1;
9130 break;
9131
9132 case BFD_RELOC_IA64_DIR64MSB:
9133 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9134 adjust = 1;
9135 break;
9136
9137 case BFD_RELOC_IA64_DIR64LSB:
9138 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9139 adjust = 1;
9140 break;
9141
9142 default:
9143 break;
9144 }
9145 }
9146 if (fix->fx_addsy)
9147 {
9148 switch (fix->fx_r_type)
9149 {
9150 case 0:
9151 as_bad_where (fix->fx_file, fix->fx_line,
9152 "%s must have a constant value",
9153 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9154 break;
9155
9156 default:
9157 break;
9158 }
9159
9160 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9161 work. There should be a better way to handle this. */
9162 if (adjust)
9163 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9164 }
9165 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9166 {
9167 if (fix->tc_fix_data.bigendian)
9168 number_to_chars_bigendian (fixpos, value, fix->fx_size);
9169 else
9170 number_to_chars_littleendian (fixpos, value, fix->fx_size);
9171 fix->fx_done = 1;
9172 return 1;
9173 }
9174 else
9175 {
9176 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
9177 fix->fx_done = 1;
9178 return 1;
9179 }
9180 return 1;
9181}
9182
9183/* Generate the BFD reloc to be stuck in the object file from the
9184 fixup used internally in the assembler. */
9185arelent*
9186tc_gen_reloc (sec, fixp)
9187 asection *sec;
9188 fixS *fixp;
9189{
9190 arelent *reloc;
9191
9192 reloc = xmalloc (sizeof (*reloc));
9193 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9194 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9195 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9196 reloc->addend = fixp->fx_offset;
9197 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9198
9199 if (!reloc->howto)
9200 {
9201 as_bad_where (fixp->fx_file, fixp->fx_line,
9202 "Cannot represent %s relocation in object file",
9203 bfd_get_reloc_code_name (fixp->fx_r_type));
9204 }
9205 return reloc;
9206}
9207
9208/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 9209 of type TYPE, and store the appropriate bytes in *LIT. The number
9210 of LITTLENUMS emitted is stored in *SIZE. An error message is
800eeca4
JW		 9211 returned, or NULL on OK. */
9212
9213#define MAX_LITTLENUMS 5
9214
9215char*
9216md_atof (type, lit, size)
9217 int type;
9218 char *lit;
9219 int *size;
9220{
9221 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9222 LITTLENUM_TYPE *word;
9223 char *t;
9224 int prec;
9225
9226 switch (type)
9227 {
9228 /* IEEE floats */
9229 case 'f':
9230 case 'F':
9231 case 's':
9232 case 'S':
9233 prec = 2;
9234 break;
9235
9236 case 'd':
9237 case 'D':
9238 case 'r':
9239 case 'R':
9240 prec = 4;
9241 break;
9242
9243 case 'x':
9244 case 'X':
9245 case 'p':
9246 case 'P':
9247 prec = 5;
9248 break;
9249
9250 default:
9251 *size = 0;
9252 return "Bad call to MD_ATOF()";
9253 }
9254 t = atof_ieee (input_line_pointer, type, words);
9255 if (t)
9256 input_line_pointer = t;
9257 *size = prec * sizeof (LITTLENUM_TYPE);
9258
9259 for (word = words + prec - 1; prec--;)
9260 {
9261 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9262 lit += sizeof (LITTLENUM_TYPE);
9263 }
9264 return 0;
9265}
9266
9267/* Round up a section's size to the appropriate boundary. */
9268valueT
9269md_section_align (seg, size)
9270 segT seg;
9271 valueT size;
9272{
9273 int align = bfd_get_section_alignment (stdoutput, seg);
197865e8 9274 valueT mask = ((valueT) 1 << align) - 1;
800eeca4
JW		 9275
9276 return (size + mask) & ~mask;
9277}
9278
9279/* Handle ia64 specific semantics of the align directive. */
9280
9281int
9282ia64_md_do_align (n, fill, len, max)
9283 int n;
9284 const char *fill;
9285 int len;
9286 int max;
9287{
9288 /* Fill any pending bundle with nops. */
9289 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
9290 ia64_flush_insns ();
9291
9292 /* When we align code in a text section, emit a bundle of 3 nops instead of
9293 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9294 N is log base 2 of the requested alignment. */
9295 if (fill == NULL
9296 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
9297 && n > 4)
9298 {
9299 /* Use mfi bundle of nops with no stop bits. */
9300 static const unsigned char be_nop[]
9301 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9302 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9303 static const unsigned char le_nop[]
9304 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9305 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
197865e8 9306
800eeca4
JW		 9307 /* Make sure we are on a 16-byte boundary, in case someone has been
9308 putting data into a text section. */
9309 frag_align (4, 0, 0);
9310
9311 if (target_big_endian)
9312 frag_align_pattern (n, be_nop, 16, max);
9313 else
9314 frag_align_pattern (n, le_nop, 16, max);
9315 return 1;
9316 }
9317
9318 return 0;
9319}
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