]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - gas/config/tc-ia64.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Lots of bug fixes. .plt entries for DT_INIT, DT_FINI, and any
[thirdparty/binutils-gdb.git] / gas / config / tc-ia64.c
CommitLineData
800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
e0c9811a 2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
800eeca4
JW		 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
800eeca4
JW		 35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
542d6675
KH		 38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
800eeca4
JW		 42
43 */
44
45#include "as.h"
46#include "dwarf2dbg.h"
47#include "subsegs.h"
48
49#include "opcode/ia64.h"
50
51#include "elf/ia64.h"
52
53#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54#define MIN(a,b) ((a) < (b) ? (a) : (b))
55
56#define NUM_SLOTS 4
57#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58#define CURR_SLOT md.slot[md.curr_slot]
59
60#define O_pseudo_fixup (O_max + 1)
61
62enum special_section
63 {
64 SPECIAL_SECTION_BSS = 0,
65 SPECIAL_SECTION_SBSS,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
71 };
72
73enum reloc_func
74 {
75 FUNC_FPTR_RELATIVE,
76 FUNC_GP_RELATIVE,
77 FUNC_LT_RELATIVE,
c67e42c9 78 FUNC_PC_RELATIVE,
800eeca4
JW		 79 FUNC_PLT_RELATIVE,
80 FUNC_SEC_RELATIVE,
81 FUNC_SEG_RELATIVE,
82 FUNC_LTV_RELATIVE,
83 FUNC_LT_FPTR_RELATIVE,
84 };
85
86enum reg_symbol
87 {
88 REG_GR = 0,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
95 REG_CFM,
96 REG_PR,
97 REG_PR_ROT,
98 REG_PSR,
99 REG_PSR_L,
100 REG_PSR_UM,
101 /* The following are pseudo-registers for use by gas only. */
102 IND_CPUID,
103 IND_DBR,
104 IND_DTR,
105 IND_ITR,
106 IND_IBR,
107 IND_MEM,
108 IND_MSR,
109 IND_PKR,
110 IND_PMC,
111 IND_PMD,
112 IND_RR,
542d6675 113 /* The following pseudo-registers are used for unwind directives only: */
e0c9811a
JW		 114 REG_PSP,
115 REG_PRIUNAT,
800eeca4
JW		 116 REG_NUM
117 };
118
119enum dynreg_type
120 {
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
124 DYNREG_NUM_TYPES
125 };
126
127/* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
130 instruction. */
131struct label_fix
542d6675
KH		 132{
133 struct label_fix *next;
134 struct symbol *sym;
135};
800eeca4
JW		 136
137extern int target_big_endian;
138
139/* Characters which always start a comment. */
140const char comment_chars[] = "";
141
142/* Characters which start a comment at the beginning of a line. */
143const char line_comment_chars[] = "#";
144
145/* Characters which may be used to separate multiple commands on a
146 single line. */
147const char line_separator_chars[] = ";";
148
149/* Characters which are used to indicate an exponent in a floating
150 point number. */
151const char EXP_CHARS[] = "eE";
152
153/* Characters which mean that a number is a floating point constant,
154 as in 0d1.0. */
155const char FLT_CHARS[] = "rRsSfFdDxXpP";
156
542d6675 157/* ia64-specific option processing: */
800eeca4
JW		 158
159const char *md_shortopts = "M:N:x::";
160
161struct option md_longopts[] =
162 {
c43c2cc5
JW		 163#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
165#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
800eeca4
JW		 167 };
168
169size_t md_longopts_size = sizeof (md_longopts);
170
171static struct
172 {
173 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
174 struct hash_control *reg_hash; /* register name hash table */
175 struct hash_control *dynreg_hash; /* dynamic register hash table */
176 struct hash_control *const_hash; /* constant hash table */
177 struct hash_control *entry_hash; /* code entry hint hash table */
178
179 symbolS *regsym[REG_NUM];
180
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
184 expressionS qp;
185
186 unsigned int
197865e8 187 manual_bundling : 1,
800eeca4
JW		 188 debug_dv: 1,
189 detect_dv: 1,
190 explicit_mode : 1, /* which mode we're in */
191 default_explicit_mode : 1, /* which mode is the default */
192 mode_explicitly_set : 1, /* was the current mode explicitly set? */
193 auto_align : 1;
194
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197865e8 197 the end_of_insn_group for the last instruction in a bundle. */
800eeca4
JW		 198 int curr_slot;
199 int num_slots_in_use;
200 struct slot
201 {
202 unsigned int
203 end_of_insn_group : 1,
204 manual_bundling_on : 1,
205 manual_bundling_off : 1;
206 signed char user_template; /* user-selected template, if any */
207 unsigned char qp_regno; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
211 int num_fixups;
212 struct insn_fix
213 {
214 bfd_reloc_code_real_type code;
215 enum ia64_opnd opnd; /* type of operand in need of fix */
216 unsigned int is_pcrel : 1; /* is operand pc-relative? */
217 expressionS expr; /* the value to be inserted */
218 }
219 fixup[2]; /* at most two fixups per insn */
220 struct ia64_opcode *idesc;
221 struct label_fix *label_fixups;
222 struct unw_rec_list *unwind_record; /* Unwind directive. */
223 expressionS opnd[6];
224 char *src_file;
225 unsigned int src_line;
226 struct dwarf2_line_info debug_line;
227 }
228 slot[NUM_SLOTS];
229
230 segT last_text_seg;
231
232 struct dynreg
233 {
234 struct dynreg *next; /* next dynamic register */
235 const char *name;
236 unsigned short base; /* the base register number */
237 unsigned short num_regs; /* # of registers in this set */
238 }
239 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
240
241 flagword flags; /* ELF-header flags */
242
243 struct mem_offset {
244 unsigned hint:1; /* is this hint currently valid? */
245 bfd_vma offset; /* mem.offset offset */
246 bfd_vma base; /* mem.offset base */
247 } mem_offset;
248
249 int path; /* number of alt. entry points seen */
250 const char **entry_labels; /* labels of all alternate paths in
542d6675 251 the current DV-checking block. */
800eeca4 252 int maxpaths; /* size currently allocated for
542d6675 253 entry_labels */
800eeca4
JW		 254 }
255md;
256
542d6675 257/* application registers: */
800eeca4 258
e0c9811a
JW		 259#define AR_K0 0
260#define AR_K7 7
261#define AR_RSC 16
262#define AR_BSP 17
263#define AR_BSPSTORE 18
264#define AR_RNAT 19
265#define AR_UNAT 36
266#define AR_FPSR 40
267#define AR_ITC 44
268#define AR_PFS 64
269#define AR_LC 65
800eeca4
JW		 270
271static const struct
272 {
273 const char *name;
274 int regnum;
275 }
276ar[] =
277 {
278 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
279 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
280 {"ar.rsc", 16}, {"ar.bsp", 17},
281 {"ar.bspstore", 18}, {"ar.rnat", 19},
282 {"ar.fcr", 21}, {"ar.eflag", 24},
283 {"ar.csd", 25}, {"ar.ssd", 26},
284 {"ar.cflg", 27}, {"ar.fsr", 28},
285 {"ar.fir", 29}, {"ar.fdr", 30},
286 {"ar.ccv", 32}, {"ar.unat", 36},
287 {"ar.fpsr", 40}, {"ar.itc", 44},
288 {"ar.pfs", 64}, {"ar.lc", 65},
197865e8 289 {"ar.ec", 66},
800eeca4
JW		 290 };
291
292#define CR_IPSR 16
293#define CR_ISR 17
294#define CR_IIP 19
295#define CR_IFA 20
296#define CR_ITIR 21
297#define CR_IIPA 22
298#define CR_IFS 23
299#define CR_IIM 24
300#define CR_IHA 25
301#define CR_IVR 65
302#define CR_TPR 66
303#define CR_EOI 67
304#define CR_IRR0 68
305#define CR_IRR3 71
306#define CR_LRR0 80
307#define CR_LRR1 81
308
542d6675 309/* control registers: */
800eeca4
JW		 310static const struct
311 {
312 const char *name;
313 int regnum;
314 }
315cr[] =
316 {
317 {"cr.dcr", 0},
318 {"cr.itm", 1},
319 {"cr.iva", 2},
320 {"cr.pta", 8},
321 {"cr.gpta", 9},
322 {"cr.ipsr", 16},
323 {"cr.isr", 17},
324 {"cr.iip", 19},
325 {"cr.ifa", 20},
326 {"cr.itir", 21},
327 {"cr.iipa", 22},
328 {"cr.ifs", 23},
329 {"cr.iim", 24},
330 {"cr.iha", 25},
331 {"cr.lid", 64},
332 {"cr.ivr", 65},
333 {"cr.tpr", 66},
334 {"cr.eoi", 67},
335 {"cr.irr0", 68},
336 {"cr.irr1", 69},
337 {"cr.irr2", 70},
338 {"cr.irr3", 71},
339 {"cr.itv", 72},
340 {"cr.pmv", 73},
341 {"cr.cmcv", 74},
342 {"cr.lrr0", 80},
343 {"cr.lrr1", 81}
344 };
345
346#define PSR_MFL 4
347#define PSR_IC 13
348#define PSR_DFL 18
349#define PSR_CPL 32
350
351static const struct const_desc
352 {
353 const char *name;
354 valueT value;
355 }
356const_bits[] =
357 {
542d6675 358 /* PSR constant masks: */
800eeca4
JW		 359
360 /* 0: reserved */
361 {"psr.be", ((valueT) 1) << 1},
362 {"psr.up", ((valueT) 1) << 2},
363 {"psr.ac", ((valueT) 1) << 3},
364 {"psr.mfl", ((valueT) 1) << 4},
365 {"psr.mfh", ((valueT) 1) << 5},
366 /* 6-12: reserved */
367 {"psr.ic", ((valueT) 1) << 13},
368 {"psr.i", ((valueT) 1) << 14},
369 {"psr.pk", ((valueT) 1) << 15},
370 /* 16: reserved */
371 {"psr.dt", ((valueT) 1) << 17},
372 {"psr.dfl", ((valueT) 1) << 18},
373 {"psr.dfh", ((valueT) 1) << 19},
374 {"psr.sp", ((valueT) 1) << 20},
375 {"psr.pp", ((valueT) 1) << 21},
376 {"psr.di", ((valueT) 1) << 22},
377 {"psr.si", ((valueT) 1) << 23},
378 {"psr.db", ((valueT) 1) << 24},
379 {"psr.lp", ((valueT) 1) << 25},
380 {"psr.tb", ((valueT) 1) << 26},
381 {"psr.rt", ((valueT) 1) << 27},
382 /* 28-31: reserved */
383 /* 32-33: cpl (current privilege level) */
384 {"psr.is", ((valueT) 1) << 34},
385 {"psr.mc", ((valueT) 1) << 35},
386 {"psr.it", ((valueT) 1) << 36},
387 {"psr.id", ((valueT) 1) << 37},
388 {"psr.da", ((valueT) 1) << 38},
389 {"psr.dd", ((valueT) 1) << 39},
390 {"psr.ss", ((valueT) 1) << 40},
391 /* 41-42: ri (restart instruction) */
392 {"psr.ed", ((valueT) 1) << 43},
393 {"psr.bn", ((valueT) 1) << 44},
394 };
395
542d6675 396/* indirect register-sets/memory: */
800eeca4
JW		 397
398static const struct
399 {
400 const char *name;
401 int regnum;
402 }
403indirect_reg[] =
404 {
405 { "CPUID", IND_CPUID },
406 { "cpuid", IND_CPUID },
407 { "dbr", IND_DBR },
408 { "dtr", IND_DTR },
409 { "itr", IND_ITR },
410 { "ibr", IND_IBR },
411 { "msr", IND_MSR },
412 { "pkr", IND_PKR },
413 { "pmc", IND_PMC },
414 { "pmd", IND_PMD },
415 { "rr", IND_RR },
416 };
417
418/* Pseudo functions used to indicate relocation types (these functions
419 start with an at sign (@). */
420static struct
421 {
422 const char *name;
423 enum pseudo_type
424 {
425 PSEUDO_FUNC_NONE,
426 PSEUDO_FUNC_RELOC,
427 PSEUDO_FUNC_CONST,
e0c9811a 428 PSEUDO_FUNC_REG,
800eeca4
JW		 429 PSEUDO_FUNC_FLOAT
430 }
431 type;
432 union
433 {
434 unsigned long ival;
435 symbolS *sym;
436 }
437 u;
438 }
439pseudo_func[] =
440 {
542d6675 441 /* reloc pseudo functions (these must come first!): */
800eeca4
JW		 442 { "fptr", PSEUDO_FUNC_RELOC },
443 { "gprel", PSEUDO_FUNC_RELOC },
444 { "ltoff", PSEUDO_FUNC_RELOC },
c67e42c9 445 { "pcrel", PSEUDO_FUNC_RELOC },
800eeca4
JW		 446 { "pltoff", PSEUDO_FUNC_RELOC },
447 { "secrel", PSEUDO_FUNC_RELOC },
448 { "segrel", PSEUDO_FUNC_RELOC },
449 { "ltv", PSEUDO_FUNC_RELOC },
450 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
451
542d6675 452 /* mbtype4 constants: */
800eeca4
JW		 453 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
454 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
455 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
456 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
457 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
458
542d6675 459 /* fclass constants: */
bf3ca999 460 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
800eeca4
JW		 461 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
462 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
463 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
464 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
465 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
466 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
467 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
468 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
TW		 469
470 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a 471
542d6675 472 /* unwind-related constants: */
e0c9811a
JW		 473 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
474 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
475 { "nt", PSEUDO_FUNC_CONST, { 2 } },
476
542d6675 477 /* unwind-related registers: */
e0c9811a 478 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
800eeca4
JW		 479 };
480
542d6675 481/* 41-bit nop opcodes (one per unit): */
800eeca4
JW		 482static const bfd_vma nop[IA64_NUM_UNITS] =
483 {
484 0x0000000000LL, /* NIL => break 0 */
485 0x0008000000LL, /* I-unit nop */
486 0x0008000000LL, /* M-unit nop */
487 0x4000000000LL, /* B-unit nop */
488 0x0008000000LL, /* F-unit nop */
489 0x0008000000LL, /* L-"unit" nop */
490 0x0008000000LL, /* X-unit nop */
491 };
492
493/* Can't be `const' as it's passed to input routines (which have the
494 habit of setting temporary sentinels. */
495static char special_section_name[][20] =
496 {
497 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
498 {".IA_64.unwind"}, {".IA_64.unwind_info"}
499 };
500
501/* The best template for a particular sequence of up to three
502 instructions: */
503#define N IA64_NUM_TYPES
504static unsigned char best_template[N][N][N];
505#undef N
506
507/* Resource dependencies currently in effect */
508static struct rsrc {
509 int depind; /* dependency index */
510 const struct ia64_dependency *dependency; /* actual dependency */
511 unsigned specific:1, /* is this a specific bit/regno? */
512 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
513 int index; /* specific regno/bit within dependency */
514 int note; /* optional qualifying note (0 if none) */
515#define STATE_NONE 0
516#define STATE_STOP 1
517#define STATE_SRLZ 2
518 int insn_srlz; /* current insn serialization state */
519 int data_srlz; /* current data serialization state */
520 int qp_regno; /* qualifying predicate for this usage */
521 char *file; /* what file marked this dependency */
522 int line; /* what line marked this dependency */
523 struct mem_offset mem_offset; /* optional memory offset hint */
524 int path; /* corresponding code entry index */
525} *regdeps = NULL;
526static int regdepslen = 0;
527static int regdepstotlen = 0;
528static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
529static const char *dv_sem[] = { "none", "implied", "impliedf",
542d6675 530 "data", "instr", "specific", "other" };
800eeca4
JW		 531
532/* Current state of PR mutexation */
533static struct qpmutex {
534 valueT prmask;
535 int path;
536} *qp_mutexes = NULL; /* QP mutex bitmasks */
537static int qp_mutexeslen = 0;
538static int qp_mutexestotlen = 0;
197865e8 539static valueT qp_safe_across_calls = 0;
800eeca4
JW		 540
541/* Current state of PR implications */
542static struct qp_imply {
543 unsigned p1:6;
544 unsigned p2:6;
545 unsigned p2_branched:1;
546 int path;
547} *qp_implies = NULL;
548static int qp_implieslen = 0;
549static int qp_impliestotlen = 0;
550
197865e8
KH		 551/* Keep track of static GR values so that indirect register usage can
552 sometimes be tracked. */
800eeca4
JW		 553static struct gr {
554 unsigned known:1;
555 int path;
556 valueT value;
557} gr_values[128] = {{ 1, 0 }};
558
559/* These are the routines required to output the various types of
560 unwind records. */
561
562typedef struct unw_rec_list {
563 unwind_record r;
e0c9811a 564 unsigned long slot_number;
800eeca4
JW		 565 struct unw_rec_list *next;
566} unw_rec_list;
567
568#define SLOT_NUM_NOT_SET -1
569
e0c9811a
JW		 570static struct
571{
572 unsigned long next_slot_number;
573
574 /* Maintain a list of unwind entries for the current function. */
575 unw_rec_list *list;
576 unw_rec_list *tail;
800eeca4 577
e0c9811a
JW		 578 /* Any unwind entires that should be attached to the current slot
579 that an insn is being constructed for. */
580 unw_rec_list *current_entry;
800eeca4 581
e0c9811a
JW		 582 /* These are used to create the unwind table entry for this function. */
583 symbolS *proc_start;
584 symbolS *proc_end;
585 symbolS *info; /* pointer to unwind info */
586 symbolS *personality_routine;
800eeca4 587
e0c9811a
JW		 588 /* TRUE if processing unwind directives in a prologue region. */
589 int prologue;
30d25259 590 int prologue_mask;
e0c9811a 591} unwind;
800eeca4
JW		 592
593typedef void (*vbyte_func) PARAMS ((int, char *, char *));
594
542d6675 595/* Forward delarations: */
800eeca4
JW		 596static int ar_is_in_integer_unit PARAMS ((int regnum));
597static void set_section PARAMS ((char *name));
598static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
599 unsigned int, unsigned int));
600static void dot_radix PARAMS ((int));
601static void dot_special_section PARAMS ((int));
602static void dot_proc PARAMS ((int));
603static void dot_fframe PARAMS ((int));
604static void dot_vframe PARAMS ((int));
150f24a2
JW		 605static void dot_vframesp PARAMS ((int));
606static void dot_vframepsp PARAMS ((int));
800eeca4
JW		 607static void dot_save PARAMS ((int));
608static void dot_restore PARAMS ((int));
150f24a2
JW		 609static void dot_restorereg PARAMS ((int));
610static void dot_restorereg_p PARAMS ((int));
800eeca4
JW		 611static void dot_handlerdata PARAMS ((int));
612static void dot_unwentry PARAMS ((int));
613static void dot_altrp PARAMS ((int));
e0c9811a 614static void dot_savemem PARAMS ((int));
800eeca4
JW		 615static void dot_saveg PARAMS ((int));
616static void dot_savef PARAMS ((int));
617static void dot_saveb PARAMS ((int));
618static void dot_savegf PARAMS ((int));
619static void dot_spill PARAMS ((int));
150f24a2
JW		 620static void dot_spillreg PARAMS ((int));
621static void dot_spillmem PARAMS ((int));
622static void dot_spillreg_p PARAMS ((int));
623static void dot_spillmem_p PARAMS ((int));
624static void dot_label_state PARAMS ((int));
625static void dot_copy_state PARAMS ((int));
800eeca4
JW		 626static void dot_unwabi PARAMS ((int));
627static void dot_personality PARAMS ((int));
628static void dot_body PARAMS ((int));
629static void dot_prologue PARAMS ((int));
630static void dot_endp PARAMS ((int));
631static void dot_template PARAMS ((int));
632static void dot_regstk PARAMS ((int));
633static void dot_rot PARAMS ((int));
634static void dot_byteorder PARAMS ((int));
635static void dot_psr PARAMS ((int));
636static void dot_alias PARAMS ((int));
637static void dot_ln PARAMS ((int));
638static char *parse_section_name PARAMS ((void));
639static void dot_xdata PARAMS ((int));
640static void stmt_float_cons PARAMS ((int));
641static void stmt_cons_ua PARAMS ((int));
642static void dot_xfloat_cons PARAMS ((int));
643static void dot_xstringer PARAMS ((int));
644static void dot_xdata_ua PARAMS ((int));
645static void dot_xfloat_cons_ua PARAMS ((int));
150f24a2 646static void print_prmask PARAMS ((valueT mask));
800eeca4
JW		 647static void dot_pred_rel PARAMS ((int));
648static void dot_reg_val PARAMS ((int));
649static void dot_dv_mode PARAMS ((int));
650static void dot_entry PARAMS ((int));
651static void dot_mem_offset PARAMS ((int));
e0c9811a 652static void add_unwind_entry PARAMS((unw_rec_list *ptr));
542d6675 653static symbolS *declare_register PARAMS ((const char *name, int regnum));
800eeca4
JW		 654static void declare_register_set PARAMS ((const char *, int, int));
655static unsigned int operand_width PARAMS ((enum ia64_opnd));
656static int operand_match PARAMS ((const struct ia64_opcode *idesc,
657 int index, expressionS *e));
658static int parse_operand PARAMS ((expressionS *e));
659static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
660static void build_insn PARAMS ((struct slot *, bfd_vma *));
661static void emit_one_bundle PARAMS ((void));
662static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
197865e8 663static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
800eeca4
JW		 664 bfd_reloc_code_real_type r_type));
665static void insn_group_break PARAMS ((int, int, int));
150f24a2
JW		 666static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
667 struct rsrc *, int depind, int path));
800eeca4
JW		 668static void add_qp_mutex PARAMS((valueT mask));
669static void add_qp_imply PARAMS((int p1, int p2));
670static void clear_qp_branch_flag PARAMS((valueT mask));
671static void clear_qp_mutex PARAMS((valueT mask));
672static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
673static void clear_register_values PARAMS ((void));
674static void print_dependency PARAMS ((const char *action, int depind));
150f24a2
JW		 675static void instruction_serialization PARAMS ((void));
676static void data_serialization PARAMS ((void));
677static void remove_marked_resource PARAMS ((struct rsrc *));
800eeca4 678static int is_conditional_branch PARAMS ((struct ia64_opcode *));
150f24a2 679static int is_taken_branch PARAMS ((struct ia64_opcode *));
800eeca4 680static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
150f24a2
JW		 681static int depends_on PARAMS ((int, struct ia64_opcode *));
682static int specify_resource PARAMS ((const struct ia64_dependency *,
683 struct ia64_opcode *, int, struct rsrc [], int, int));
800eeca4
JW		 684static int check_dv PARAMS((struct ia64_opcode *idesc));
685static void check_dependencies PARAMS((struct ia64_opcode *));
686static void mark_resources PARAMS((struct ia64_opcode *));
687static void update_dependencies PARAMS((struct ia64_opcode *));
688static void note_register_values PARAMS((struct ia64_opcode *));
150f24a2
JW		 689static int qp_mutex PARAMS ((int, int, int));
690static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
691static void output_vbyte_mem PARAMS ((int, char *, char *));
692static void count_output PARAMS ((int, char *, char *));
693static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
694static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
800eeca4 695static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 696static void output_P1_format PARAMS ((vbyte_func, int));
697static void output_P2_format PARAMS ((vbyte_func, int, int));
698static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
699static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
700static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
701static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
702static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
703static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
704static void output_P9_format PARAMS ((vbyte_func, int, int));
705static void output_P10_format PARAMS ((vbyte_func, int, int));
706static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
707static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800eeca4
JW		 708static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
709static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 710static char format_ab_reg PARAMS ((int, int));
711static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
712 unsigned long));
713static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
714static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
715 unsigned long));
716static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
717static void free_list_records PARAMS ((unw_rec_list *));
718static unw_rec_list *output_prologue PARAMS ((void));
719static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
720static unw_rec_list *output_body PARAMS ((void));
721static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
722static unw_rec_list *output_mem_stack_v PARAMS ((void));
723static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
724static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
725static unw_rec_list *output_rp_when PARAMS ((void));
726static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
727static unw_rec_list *output_rp_br PARAMS ((unsigned int));
728static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
729static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
730static unw_rec_list *output_pfs_when PARAMS ((void));
731static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
732static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
733static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
734static unw_rec_list *output_preds_when PARAMS ((void));
735static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
736static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
737static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
738static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
739static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
740static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
741static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
742static unw_rec_list *output_br_mem PARAMS ((unsigned int));
743static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
744static unw_rec_list *output_spill_base PARAMS ((unsigned int));
745static unw_rec_list *output_unat_when PARAMS ((void));
746static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
747static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
748static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
749static unw_rec_list *output_lc_when PARAMS ((void));
750static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
751static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
752static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
753static unw_rec_list *output_fpsr_when PARAMS ((void));
754static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
755static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
756static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
757static unw_rec_list *output_priunat_when_gr PARAMS ((void));
758static unw_rec_list *output_priunat_when_mem PARAMS ((void));
759static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
760static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
761static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
762static unw_rec_list *output_bsp_when PARAMS ((void));
763static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
764static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
765static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
766static unw_rec_list *output_bspstore_when PARAMS ((void));
767static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
768static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
769static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
770static unw_rec_list *output_rnat_when PARAMS ((void));
771static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
772static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
773static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
774static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
775static unw_rec_list *output_epilogue PARAMS ((unsigned long));
776static unw_rec_list *output_label_state PARAMS ((unsigned long));
777static unw_rec_list *output_copy_state PARAMS ((unsigned long));
778static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
779static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
780static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
781 unsigned int));
782static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
783 unsigned int));
784static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
785 unsigned int));
786static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
787 unsigned int, unsigned int));
788static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
789static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
790static int calc_record_size PARAMS ((unw_rec_list *));
791static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
792static int count_bits PARAMS ((unsigned long));
793static unsigned long slot_index PARAMS ((unsigned long, unsigned long));
794static void fixup_unw_records PARAMS ((unw_rec_list *));
795static int output_unw_records PARAMS ((unw_rec_list *, void **));
796static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
797static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
798static int generate_unwind_image PARAMS ((void));
800eeca4
JW		 799
800/* Determine if application register REGNUM resides in the integer
801 unit (as opposed to the memory unit). */
802static int
803ar_is_in_integer_unit (reg)
804 int reg;
805{
806 reg -= REG_AR;
807
808 return (reg == 64 /* pfs */
809 || reg == 65 /* lc */
810 || reg == 66 /* ec */
811 /* ??? ias accepts and puts these in the integer unit. */
812 || (reg >= 112 && reg <= 127));
813}
814
815/* Switch to section NAME and create section if necessary. It's
816 rather ugly that we have to manipulate input_line_pointer but I
817 don't see any other way to accomplish the same thing without
818 changing obj-elf.c (which may be the Right Thing, in the end). */
819static void
820set_section (name)
821 char *name;
822{
823 char *saved_input_line_pointer;
824
825 saved_input_line_pointer = input_line_pointer;
826 input_line_pointer = name;
827 obj_elf_section (0);
828 input_line_pointer = saved_input_line_pointer;
829}
830
831/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
832
833flagword
834ia64_elf_section_flags (flags, attr, type)
835 flagword flags;
836 int attr, type;
837{
838 if (attr & SHF_IA_64_SHORT)
839 flags |= SEC_SMALL_DATA;
840 return flags;
841}
842
843static unsigned int
844set_regstack (ins, locs, outs, rots)
845 unsigned int ins, locs, outs, rots;
846{
542d6675
KH		 847 /* Size of frame. */
848 unsigned int sof;
800eeca4
JW		 849
850 sof = ins + locs + outs;
851 if (sof > 96)
852 {
853 as_bad ("Size of frame exceeds maximum of 96 registers");
854 return 0;
855 }
856 if (rots > sof)
857 {
858 as_warn ("Size of rotating registers exceeds frame size");
859 return 0;
860 }
861 md.in.base = REG_GR + 32;
862 md.loc.base = md.in.base + ins;
863 md.out.base = md.loc.base + locs;
864
865 md.in.num_regs = ins;
866 md.loc.num_regs = locs;
867 md.out.num_regs = outs;
868 md.rot.num_regs = rots;
869 return sof;
870}
871
872void
873ia64_flush_insns ()
874{
875 struct label_fix *lfix;
876 segT saved_seg;
877 subsegT saved_subseg;
878
879 if (!md.last_text_seg)
880 return;
881
882 saved_seg = now_seg;
883 saved_subseg = now_subseg;
884
885 subseg_set (md.last_text_seg, 0);
886
887 while (md.num_slots_in_use > 0)
888 emit_one_bundle (); /* force out queued instructions */
889
890 /* In case there are labels following the last instruction, resolve
542d6675 891 those now: */
800eeca4
JW		 892 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
893 {
894 S_SET_VALUE (lfix->sym, frag_now_fix ());
895 symbol_set_frag (lfix->sym, frag_now);
896 }
897 CURR_SLOT.label_fixups = 0;
898
899 subseg_set (saved_seg, saved_subseg);
900}
901
902void
903ia64_do_align (nbytes)
904 int nbytes;
905{
906 char *saved_input_line_pointer = input_line_pointer;
907
908 input_line_pointer = "";
909 s_align_bytes (nbytes);
910 input_line_pointer = saved_input_line_pointer;
911}
912
913void
914ia64_cons_align (nbytes)
915 int nbytes;
916{
917 if (md.auto_align)
918 {
919 char *saved_input_line_pointer = input_line_pointer;
920 input_line_pointer = "";
921 s_align_bytes (nbytes);
922 input_line_pointer = saved_input_line_pointer;
923 }
924}
925
926/* Output COUNT bytes to a memory location. */
927static unsigned char *vbyte_mem_ptr = NULL;
928
197865e8 929void
800eeca4
JW		 930output_vbyte_mem (count, ptr, comment)
931 int count;
932 char *ptr;
933 char *comment;
934{
935 int x;
936 if (vbyte_mem_ptr == NULL)
937 abort ();
938
939 if (count == 0)
940 return;
941 for (x = 0; x < count; x++)
942 *(vbyte_mem_ptr++) = ptr[x];
943}
944
945/* Count the number of bytes required for records. */
946static int vbyte_count = 0;
197865e8 947void
800eeca4
JW		 948count_output (count, ptr, comment)
949 int count;
950 char *ptr;
951 char *comment;
952{
953 vbyte_count += count;
954}
955
956static void
957output_R1_format (f, rtype, rlen)
958 vbyte_func f;
959 unw_record_type rtype;
960 int rlen;
961{
e0c9811a 962 int r = 0;
800eeca4
JW		 963 char byte;
964 if (rlen > 0x1f)
965 {
966 output_R3_format (f, rtype, rlen);
967 return;
968 }
197865e8 969
e0c9811a
JW		 970 if (rtype == body)
971 r = 1;
972 else if (rtype != prologue)
973 as_bad ("record type is not valid");
974
800eeca4
JW		 975 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
976 (*f) (1, &byte, NULL);
977}
978
979static void
980output_R2_format (f, mask, grsave, rlen)
981 vbyte_func f;
982 int mask, grsave;
983 unsigned long rlen;
984{
985 char bytes[20];
986 int count = 2;
987 mask = (mask & 0x0f);
988 grsave = (grsave & 0x7f);
989
990 bytes[0] = (UNW_R2 | (mask >> 1));
991 bytes[1] = (((mask & 0x01) << 7) | grsave);
992 count += output_leb128 (bytes + 2, rlen, 0);
993 (*f) (count, bytes, NULL);
994}
995
996static void
997output_R3_format (f, rtype, rlen)
998 vbyte_func f;
999 unw_record_type rtype;
1000 unsigned long rlen;
1001{
e0c9811a 1002 int r = 0, count;
800eeca4
JW		 1003 char bytes[20];
1004 if (rlen <= 0x1f)
1005 {
1006 output_R1_format (f, rtype, rlen);
1007 return;
1008 }
197865e8 1009
e0c9811a
JW		 1010 if (rtype == body)
1011 r = 1;
1012 else if (rtype != prologue)
1013 as_bad ("record type is not valid");
800eeca4
JW		 1014 bytes[0] = (UNW_R3 | r);
1015 count = output_leb128 (bytes + 1, rlen, 0);
1016 (*f) (count + 1, bytes, NULL);
1017}
1018
1019static void
1020output_P1_format (f, brmask)
1021 vbyte_func f;
1022 int brmask;
1023{
1024 char byte;
1025 byte = UNW_P1 | (brmask & 0x1f);
1026 (*f) (1, &byte, NULL);
1027}
1028
1029static void
1030output_P2_format (f, brmask, gr)
1031 vbyte_func f;
1032 int brmask;
1033 int gr;
1034{
1035 char bytes[2];
1036 brmask = (brmask & 0x1f);
1037 bytes[0] = UNW_P2 | (brmask >> 1);
1038 bytes[1] = (((brmask & 1) << 7) | gr);
1039 (*f) (2, bytes, NULL);
1040}
1041
1042static void
1043output_P3_format (f, rtype, reg)
1044 vbyte_func f;
1045 unw_record_type rtype;
1046 int reg;
1047{
1048 char bytes[2];
e0c9811a 1049 int r = 0;
800eeca4
JW		 1050 reg = (reg & 0x7f);
1051 switch (rtype)
542d6675 1052 {
800eeca4
JW		 1053 case psp_gr:
1054 r = 0;
1055 break;
1056 case rp_gr:
1057 r = 1;
1058 break;
1059 case pfs_gr:
1060 r = 2;
1061 break;
1062 case preds_gr:
1063 r = 3;
1064 break;
1065 case unat_gr:
1066 r = 4;
1067 break;
1068 case lc_gr:
1069 r = 5;
1070 break;
1071 case rp_br:
1072 r = 6;
1073 break;
1074 case rnat_gr:
1075 r = 7;
1076 break;
1077 case bsp_gr:
1078 r = 8;
1079 break;
1080 case bspstore_gr:
1081 r = 9;
1082 break;
1083 case fpsr_gr:
1084 r = 10;
1085 break;
1086 case priunat_gr:
1087 r = 11;
1088 break;
1089 default:
1090 as_bad ("Invalid record type for P3 format.");
542d6675 1091 }
800eeca4
JW		 1092 bytes[0] = (UNW_P3 | (r >> 1));
1093 bytes[1] = (((r & 1) << 7) | reg);
1094 (*f) (2, bytes, NULL);
1095}
1096
800eeca4 1097static void
e0c9811a 1098output_P4_format (f, imask, imask_size)
800eeca4 1099 vbyte_func f;
e0c9811a
JW		 1100 unsigned char *imask;
1101 unsigned long imask_size;
800eeca4 1102{
e0c9811a
JW		 1103 imask[0] = UNW_P4;
1104 (*f) (imask_size, imask, NULL);
800eeca4
JW		 1105}
1106
1107static void
1108output_P5_format (f, grmask, frmask)
1109 vbyte_func f;
1110 int grmask;
1111 unsigned long frmask;
1112{
1113 char bytes[4];
1114 grmask = (grmask & 0x0f);
1115
1116 bytes[0] = UNW_P5;
1117 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1118 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1119 bytes[3] = (frmask & 0x000000ff);
1120 (*f) (4, bytes, NULL);
1121}
1122
1123static void
1124output_P6_format (f, rtype, rmask)
1125 vbyte_func f;
1126 unw_record_type rtype;
1127 int rmask;
1128{
1129 char byte;
e0c9811a 1130 int r = 0;
197865e8 1131
e0c9811a
JW		 1132 if (rtype == gr_mem)
1133 r = 1;
1134 else if (rtype != fr_mem)
1135 as_bad ("Invalid record type for format P6");
800eeca4
JW		 1136 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1137 (*f) (1, &byte, NULL);
1138}
1139
1140static void
1141output_P7_format (f, rtype, w1, w2)
1142 vbyte_func f;
1143 unw_record_type rtype;
1144 unsigned long w1;
1145 unsigned long w2;
1146{
1147 char bytes[20];
1148 int count = 1;
e0c9811a 1149 int r = 0;
800eeca4
JW		 1150 count += output_leb128 (bytes + 1, w1, 0);
1151 switch (rtype)
1152 {
542d6675
KH		 1153 case mem_stack_f:
1154 r = 0;
1155 count += output_leb128 (bytes + count, w2 >> 4, 0);
1156 break;
1157 case mem_stack_v:
1158 r = 1;
1159 break;
1160 case spill_base:
1161 r = 2;
1162 break;
1163 case psp_sprel:
1164 r = 3;
1165 break;
1166 case rp_when:
1167 r = 4;
1168 break;
1169 case rp_psprel:
1170 r = 5;
1171 break;
1172 case pfs_when:
1173 r = 6;
1174 break;
1175 case pfs_psprel:
1176 r = 7;
1177 break;
1178 case preds_when:
1179 r = 8;
1180 break;
1181 case preds_psprel:
1182 r = 9;
1183 break;
1184 case lc_when:
1185 r = 10;
1186 break;
1187 case lc_psprel:
1188 r = 11;
1189 break;
1190 case unat_when:
1191 r = 12;
1192 break;
1193 case unat_psprel:
1194 r = 13;
1195 break;
1196 case fpsr_when:
1197 r = 14;
1198 break;
1199 case fpsr_psprel:
1200 r = 15;
1201 break;
1202 default:
1203 break;
800eeca4
JW		 1204 }
1205 bytes[0] = (UNW_P7 | r);
1206 (*f) (count, bytes, NULL);
1207}
1208
1209static void
1210output_P8_format (f, rtype, t)
1211 vbyte_func f;
1212 unw_record_type rtype;
1213 unsigned long t;
1214{
1215 char bytes[20];
e0c9811a 1216 int r = 0;
800eeca4
JW		 1217 int count = 2;
1218 bytes[0] = UNW_P8;
1219 switch (rtype)
1220 {
542d6675
KH		 1221 case rp_sprel:
1222 r = 1;
1223 break;
1224 case pfs_sprel:
1225 r = 2;
1226 break;
1227 case preds_sprel:
1228 r = 3;
1229 break;
1230 case lc_sprel:
1231 r = 4;
1232 break;
1233 case unat_sprel:
1234 r = 5;
1235 break;
1236 case fpsr_sprel:
1237 r = 6;
1238 break;
1239 case bsp_when:
1240 r = 7;
1241 break;
1242 case bsp_psprel:
1243 r = 8;
1244 break;
1245 case bsp_sprel:
1246 r = 9;
1247 break;
1248 case bspstore_when:
1249 r = 10;
1250 break;
1251 case bspstore_psprel:
1252 r = 11;
1253 break;
1254 case bspstore_sprel:
1255 r = 12;
1256 break;
1257 case rnat_when:
1258 r = 13;
1259 break;
1260 case rnat_psprel:
1261 r = 14;
1262 break;
1263 case rnat_sprel:
1264 r = 15;
1265 break;
1266 case priunat_when_gr:
1267 r = 16;
1268 break;
1269 case priunat_psprel:
1270 r = 17;
1271 break;
1272 case priunat_sprel:
1273 r = 18;
1274 break;
1275 case priunat_when_mem:
1276 r = 19;
1277 break;
1278 default:
1279 break;
800eeca4
JW		 1280 }
1281 bytes[1] = r;
1282 count += output_leb128 (bytes + 2, t, 0);
1283 (*f) (count, bytes, NULL);
1284}
1285
1286static void
1287output_P9_format (f, grmask, gr)
1288 vbyte_func f;
1289 int grmask;
1290 int gr;
1291{
1292 char bytes[3];
1293 bytes[0] = UNW_P9;
1294 bytes[1] = (grmask & 0x0f);
1295 bytes[2] = (gr & 0x7f);
1296 (*f) (3, bytes, NULL);
1297}
1298
1299static void
1300output_P10_format (f, abi, context)
1301 vbyte_func f;
1302 int abi;
1303 int context;
1304{
1305 char bytes[3];
1306 bytes[0] = UNW_P10;
1307 bytes[1] = (abi & 0xff);
1308 bytes[2] = (context & 0xff);
1309 (*f) (3, bytes, NULL);
1310}
1311
1312static void
1313output_B1_format (f, rtype, label)
1314 vbyte_func f;
1315 unw_record_type rtype;
1316 unsigned long label;
1317{
1318 char byte;
e0c9811a 1319 int r = 0;
197865e8 1320 if (label > 0x1f)
800eeca4
JW		 1321 {
1322 output_B4_format (f, rtype, label);
1323 return;
1324 }
e0c9811a
JW		 1325 if (rtype == copy_state)
1326 r = 1;
1327 else if (rtype != label_state)
1328 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1329
1330 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1331 (*f) (1, &byte, NULL);
1332}
1333
1334static void
1335output_B2_format (f, ecount, t)
1336 vbyte_func f;
1337 unsigned long ecount;
1338 unsigned long t;
1339{
1340 char bytes[20];
1341 int count = 1;
1342 if (ecount > 0x1f)
1343 {
1344 output_B3_format (f, ecount, t);
1345 return;
1346 }
1347 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1348 count += output_leb128 (bytes + 1, t, 0);
1349 (*f) (count, bytes, NULL);
1350}
1351
1352static void
1353output_B3_format (f, ecount, t)
1354 vbyte_func f;
1355 unsigned long ecount;
1356 unsigned long t;
1357{
1358 char bytes[20];
1359 int count = 1;
1360 if (ecount <= 0x1f)
1361 {
1362 output_B2_format (f, ecount, t);
1363 return;
1364 }
1365 bytes[0] = UNW_B3;
1366 count += output_leb128 (bytes + 1, t, 0);
1367 count += output_leb128 (bytes + count, ecount, 0);
1368 (*f) (count, bytes, NULL);
1369}
1370
1371static void
1372output_B4_format (f, rtype, label)
1373 vbyte_func f;
1374 unw_record_type rtype;
1375 unsigned long label;
1376{
1377 char bytes[20];
e0c9811a 1378 int r = 0;
800eeca4 1379 int count = 1;
197865e8 1380 if (label <= 0x1f)
800eeca4
JW		 1381 {
1382 output_B1_format (f, rtype, label);
1383 return;
1384 }
197865e8 1385
e0c9811a
JW		 1386 if (rtype == copy_state)
1387 r = 1;
1388 else if (rtype != label_state)
1389 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1390
1391 bytes[0] = (UNW_B4 | (r << 3));
1392 count += output_leb128 (bytes + 1, label, 0);
1393 (*f) (count, bytes, NULL);
1394}
1395
1396static char
e0c9811a 1397format_ab_reg (ab, reg)
542d6675
KH		 1398 int ab;
1399 int reg;
800eeca4
JW		 1400{
1401 int ret;
e0c9811a 1402 ab = (ab & 3);
800eeca4 1403 reg = (reg & 0x1f);
e0c9811a 1404 ret = (ab << 5) | reg;
800eeca4
JW		 1405 return ret;
1406}
1407
1408static void
e0c9811a 1409output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW		 1410 vbyte_func f;
1411 unw_record_type rtype;
e0c9811a 1412 int ab, reg;
800eeca4
JW		 1413 unsigned long t;
1414 unsigned long w1;
1415{
1416 char bytes[20];
e0c9811a 1417 int r = 0;
800eeca4
JW		 1418 int count = 2;
1419 bytes[0] = UNW_X1;
197865e8 1420
e0c9811a
JW		 1421 if (rtype == spill_sprel)
1422 r = 1;
1423 else if (rtype != spill_psprel)
1424 as_bad ("Invalid record type for format X1");
1425 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1426 count += output_leb128 (bytes + 2, t, 0);
1427 count += output_leb128 (bytes + count, w1, 0);
1428 (*f) (count, bytes, NULL);
1429}
1430
1431static void
e0c9811a 1432output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1433 vbyte_func f;
e0c9811a 1434 int ab, reg;
800eeca4
JW		 1435 int x, y, treg;
1436 unsigned long t;
1437{
1438 char bytes[20];
800eeca4
JW		 1439 int count = 3;
1440 bytes[0] = UNW_X2;
e0c9811a 1441 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1442 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1443 count += output_leb128 (bytes + 3, t, 0);
1444 (*f) (count, bytes, NULL);
1445}
1446
1447static void
e0c9811a 1448output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW		 1449 vbyte_func f;
1450 unw_record_type rtype;
1451 int qp;
e0c9811a 1452 int ab, reg;
800eeca4
JW		 1453 unsigned long t;
1454 unsigned long w1;
1455{
1456 char bytes[20];
e0c9811a 1457 int r = 0;
800eeca4 1458 int count = 3;
e0c9811a
JW		 1459 bytes[0] = UNW_X3;
1460
1461 if (rtype == spill_sprel_p)
1462 r = 1;
1463 else if (rtype != spill_psprel_p)
1464 as_bad ("Invalid record type for format X3");
800eeca4 1465 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1466 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW		 1467 count += output_leb128 (bytes + 3, t, 0);
1468 count += output_leb128 (bytes + count, w1, 0);
1469 (*f) (count, bytes, NULL);
1470}
1471
1472static void
e0c9811a 1473output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW		 1474 vbyte_func f;
1475 int qp;
e0c9811a 1476 int ab, reg;
800eeca4
JW		 1477 int x, y, treg;
1478 unsigned long t;
1479{
1480 char bytes[20];
800eeca4 1481 int count = 4;
e0c9811a 1482 bytes[0] = UNW_X4;
800eeca4 1483 bytes[1] = (qp & 0x3f);
e0c9811a 1484 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1485 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1486 count += output_leb128 (bytes + 4, t, 0);
1487 (*f) (count, bytes, NULL);
1488}
1489
1490/* This function allocates a record list structure, and initializes fields. */
542d6675 1491
800eeca4 1492static unw_rec_list *
197865e8 1493alloc_record (unw_record_type t)
800eeca4
JW		 1494{
1495 unw_rec_list *ptr;
1496 ptr = xmalloc (sizeof (*ptr));
1497 ptr->next = NULL;
1498 ptr->slot_number = SLOT_NUM_NOT_SET;
1499 ptr->r.type = t;
1500 return ptr;
1501}
1502
800eeca4 1503/* This function frees an entire list of record structures. */
542d6675 1504
800eeca4
JW		 1505void
1506free_list_records (unw_rec_list *first)
1507{
1508 unw_rec_list *ptr;
542d6675 1509 for (ptr = first; ptr != NULL;)
800eeca4
JW		 1510 {
1511 unw_rec_list *tmp = ptr;
e0c9811a
JW		 1512
1513 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1514 && tmp->r.record.r.mask.i)
1515 free (tmp->r.record.r.mask.i);
1516
800eeca4
JW		 1517 ptr = ptr->next;
1518 free (tmp);
1519 }
1520}
1521
1522static unw_rec_list *
1523output_prologue ()
1524{
1525 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1526 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW		 1527 return ptr;
1528}
1529
1530static unw_rec_list *
1531output_prologue_gr (saved_mask, reg)
1532 unsigned int saved_mask;
1533 unsigned int reg;
1534{
1535 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW		 1536 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1537 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW		 1538 ptr->r.record.r.grsave = reg;
1539 return ptr;
1540}
1541
1542static unw_rec_list *
1543output_body ()
1544{
1545 unw_rec_list *ptr = alloc_record (body);
1546 return ptr;
1547}
1548
1549static unw_rec_list *
1550output_mem_stack_f (size)
1551 unsigned int size;
1552{
1553 unw_rec_list *ptr = alloc_record (mem_stack_f);
1554 ptr->r.record.p.size = size;
1555 return ptr;
1556}
1557
1558static unw_rec_list *
1559output_mem_stack_v ()
1560{
1561 unw_rec_list *ptr = alloc_record (mem_stack_v);
1562 return ptr;
1563}
1564
1565static unw_rec_list *
1566output_psp_gr (gr)
1567 unsigned int gr;
1568{
1569 unw_rec_list *ptr = alloc_record (psp_gr);
1570 ptr->r.record.p.gr = gr;
1571 return ptr;
1572}
1573
1574static unw_rec_list *
1575output_psp_sprel (offset)
1576 unsigned int offset;
1577{
1578 unw_rec_list *ptr = alloc_record (psp_sprel);
542d6675 1579 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1580 return ptr;
1581}
1582
1583static unw_rec_list *
1584output_rp_when ()
1585{
1586 unw_rec_list *ptr = alloc_record (rp_when);
1587 return ptr;
1588}
1589
1590static unw_rec_list *
1591output_rp_gr (gr)
1592 unsigned int gr;
1593{
1594 unw_rec_list *ptr = alloc_record (rp_gr);
1595 ptr->r.record.p.gr = gr;
1596 return ptr;
1597}
1598
1599static unw_rec_list *
1600output_rp_br (br)
1601 unsigned int br;
1602{
1603 unw_rec_list *ptr = alloc_record (rp_br);
1604 ptr->r.record.p.br = br;
1605 return ptr;
1606}
1607
1608static unw_rec_list *
1609output_rp_psprel (offset)
1610 unsigned int offset;
1611{
1612 unw_rec_list *ptr = alloc_record (rp_psprel);
542d6675 1613 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1614 return ptr;
1615}
1616
1617static unw_rec_list *
1618output_rp_sprel (offset)
1619 unsigned int offset;
1620{
1621 unw_rec_list *ptr = alloc_record (rp_sprel);
542d6675 1622 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1623 return ptr;
1624}
1625
1626static unw_rec_list *
1627output_pfs_when ()
1628{
1629 unw_rec_list *ptr = alloc_record (pfs_when);
1630 return ptr;
1631}
1632
1633static unw_rec_list *
1634output_pfs_gr (gr)
1635 unsigned int gr;
1636{
1637 unw_rec_list *ptr = alloc_record (pfs_gr);
1638 ptr->r.record.p.gr = gr;
1639 return ptr;
1640}
1641
1642static unw_rec_list *
1643output_pfs_psprel (offset)
1644 unsigned int offset;
1645{
1646 unw_rec_list *ptr = alloc_record (pfs_psprel);
542d6675 1647 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1648 return ptr;
1649}
1650
1651static unw_rec_list *
1652output_pfs_sprel (offset)
1653 unsigned int offset;
1654{
1655 unw_rec_list *ptr = alloc_record (pfs_sprel);
542d6675 1656 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1657 return ptr;
1658}
1659
1660static unw_rec_list *
1661output_preds_when ()
1662{
1663 unw_rec_list *ptr = alloc_record (preds_when);
1664 return ptr;
1665}
1666
1667static unw_rec_list *
1668output_preds_gr (gr)
1669 unsigned int gr;
1670{
1671 unw_rec_list *ptr = alloc_record (preds_gr);
1672 ptr->r.record.p.gr = gr;
1673 return ptr;
1674}
1675
1676static unw_rec_list *
1677output_preds_psprel (offset)
1678 unsigned int offset;
1679{
1680 unw_rec_list *ptr = alloc_record (preds_psprel);
542d6675 1681 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1682 return ptr;
1683}
1684
1685static unw_rec_list *
1686output_preds_sprel (offset)
1687 unsigned int offset;
1688{
1689 unw_rec_list *ptr = alloc_record (preds_sprel);
542d6675 1690 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1691 return ptr;
1692}
1693
1694static unw_rec_list *
1695output_fr_mem (mask)
1696 unsigned int mask;
1697{
1698 unw_rec_list *ptr = alloc_record (fr_mem);
1699 ptr->r.record.p.rmask = mask;
1700 return ptr;
1701}
1702
1703static unw_rec_list *
1704output_frgr_mem (gr_mask, fr_mask)
1705 unsigned int gr_mask;
1706 unsigned int fr_mask;
1707{
1708 unw_rec_list *ptr = alloc_record (frgr_mem);
1709 ptr->r.record.p.grmask = gr_mask;
1710 ptr->r.record.p.frmask = fr_mask;
1711 return ptr;
1712}
1713
1714static unw_rec_list *
1715output_gr_gr (mask, reg)
1716 unsigned int mask;
1717 unsigned int reg;
1718{
1719 unw_rec_list *ptr = alloc_record (gr_gr);
1720 ptr->r.record.p.grmask = mask;
1721 ptr->r.record.p.gr = reg;
1722 return ptr;
1723}
1724
1725static unw_rec_list *
1726output_gr_mem (mask)
1727 unsigned int mask;
1728{
1729 unw_rec_list *ptr = alloc_record (gr_mem);
1730 ptr->r.record.p.rmask = mask;
1731 return ptr;
1732}
1733
1734static unw_rec_list *
1735output_br_mem (unsigned int mask)
1736{
1737 unw_rec_list *ptr = alloc_record (br_mem);
1738 ptr->r.record.p.brmask = mask;
1739 return ptr;
1740}
1741
1742static unw_rec_list *
1743output_br_gr (save_mask, reg)
1744 unsigned int save_mask;
1745 unsigned int reg;
1746{
1747 unw_rec_list *ptr = alloc_record (br_gr);
1748 ptr->r.record.p.brmask = save_mask;
1749 ptr->r.record.p.gr = reg;
1750 return ptr;
1751}
1752
1753static unw_rec_list *
1754output_spill_base (offset)
1755 unsigned int offset;
1756{
1757 unw_rec_list *ptr = alloc_record (spill_base);
542d6675 1758 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1759 return ptr;
1760}
1761
1762static unw_rec_list *
1763output_unat_when ()
1764{
1765 unw_rec_list *ptr = alloc_record (unat_when);
1766 return ptr;
1767}
1768
1769static unw_rec_list *
1770output_unat_gr (gr)
1771 unsigned int gr;
1772{
1773 unw_rec_list *ptr = alloc_record (unat_gr);
1774 ptr->r.record.p.gr = gr;
1775 return ptr;
1776}
1777
1778static unw_rec_list *
1779output_unat_psprel (offset)
1780 unsigned int offset;
1781{
1782 unw_rec_list *ptr = alloc_record (unat_psprel);
542d6675 1783 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1784 return ptr;
1785}
1786
1787static unw_rec_list *
1788output_unat_sprel (offset)
1789 unsigned int offset;
1790{
1791 unw_rec_list *ptr = alloc_record (unat_sprel);
542d6675 1792 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1793 return ptr;
1794}
1795
1796static unw_rec_list *
1797output_lc_when ()
1798{
1799 unw_rec_list *ptr = alloc_record (lc_when);
1800 return ptr;
1801}
1802
1803static unw_rec_list *
1804output_lc_gr (gr)
1805 unsigned int gr;
1806{
1807 unw_rec_list *ptr = alloc_record (lc_gr);
1808 ptr->r.record.p.gr = gr;
1809 return ptr;
1810}
1811
1812static unw_rec_list *
1813output_lc_psprel (offset)
1814 unsigned int offset;
1815{
1816 unw_rec_list *ptr = alloc_record (lc_psprel);
542d6675 1817 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1818 return ptr;
1819}
1820
1821static unw_rec_list *
1822output_lc_sprel (offset)
1823 unsigned int offset;
1824{
1825 unw_rec_list *ptr = alloc_record (lc_sprel);
542d6675 1826 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1827 return ptr;
1828}
1829
1830static unw_rec_list *
1831output_fpsr_when ()
1832{
1833 unw_rec_list *ptr = alloc_record (fpsr_when);
1834 return ptr;
1835}
1836
1837static unw_rec_list *
1838output_fpsr_gr (gr)
1839 unsigned int gr;
1840{
1841 unw_rec_list *ptr = alloc_record (fpsr_gr);
1842 ptr->r.record.p.gr = gr;
1843 return ptr;
1844}
1845
1846static unw_rec_list *
1847output_fpsr_psprel (offset)
1848 unsigned int offset;
1849{
1850 unw_rec_list *ptr = alloc_record (fpsr_psprel);
542d6675 1851 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1852 return ptr;
1853}
1854
1855static unw_rec_list *
1856output_fpsr_sprel (offset)
1857 unsigned int offset;
1858{
1859 unw_rec_list *ptr = alloc_record (fpsr_sprel);
542d6675 1860 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1861 return ptr;
1862}
1863
1864static unw_rec_list *
1865output_priunat_when_gr ()
1866{
1867 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1868 return ptr;
1869}
1870
1871static unw_rec_list *
1872output_priunat_when_mem ()
1873{
1874 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1875 return ptr;
1876}
1877
1878static unw_rec_list *
1879output_priunat_gr (gr)
1880 unsigned int gr;
1881{
1882 unw_rec_list *ptr = alloc_record (priunat_gr);
1883 ptr->r.record.p.gr = gr;
1884 return ptr;
1885}
1886
1887static unw_rec_list *
1888output_priunat_psprel (offset)
1889 unsigned int offset;
1890{
1891 unw_rec_list *ptr = alloc_record (priunat_psprel);
542d6675 1892 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1893 return ptr;
1894}
1895
1896static unw_rec_list *
1897output_priunat_sprel (offset)
1898 unsigned int offset;
1899{
1900 unw_rec_list *ptr = alloc_record (priunat_sprel);
542d6675 1901 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1902 return ptr;
1903}
1904
1905static unw_rec_list *
1906output_bsp_when ()
1907{
1908 unw_rec_list *ptr = alloc_record (bsp_when);
1909 return ptr;
1910}
1911
1912static unw_rec_list *
1913output_bsp_gr (gr)
1914 unsigned int gr;
1915{
1916 unw_rec_list *ptr = alloc_record (bsp_gr);
1917 ptr->r.record.p.gr = gr;
1918 return ptr;
1919}
1920
1921static unw_rec_list *
1922output_bsp_psprel (offset)
1923 unsigned int offset;
1924{
1925 unw_rec_list *ptr = alloc_record (bsp_psprel);
542d6675 1926 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1927 return ptr;
1928}
1929
1930static unw_rec_list *
1931output_bsp_sprel (offset)
1932 unsigned int offset;
1933{
1934 unw_rec_list *ptr = alloc_record (bsp_sprel);
542d6675 1935 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1936 return ptr;
1937}
1938
1939static unw_rec_list *
1940output_bspstore_when ()
1941{
1942 unw_rec_list *ptr = alloc_record (bspstore_when);
1943 return ptr;
1944}
1945
1946static unw_rec_list *
1947output_bspstore_gr (gr)
1948 unsigned int gr;
1949{
1950 unw_rec_list *ptr = alloc_record (bspstore_gr);
1951 ptr->r.record.p.gr = gr;
1952 return ptr;
1953}
1954
1955static unw_rec_list *
1956output_bspstore_psprel (offset)
1957 unsigned int offset;
1958{
1959 unw_rec_list *ptr = alloc_record (bspstore_psprel);
542d6675 1960 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1961 return ptr;
1962}
1963
1964static unw_rec_list *
1965output_bspstore_sprel (offset)
1966 unsigned int offset;
1967{
1968 unw_rec_list *ptr = alloc_record (bspstore_sprel);
542d6675 1969 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1970 return ptr;
1971}
1972
1973static unw_rec_list *
1974output_rnat_when ()
1975{
1976 unw_rec_list *ptr = alloc_record (rnat_when);
1977 return ptr;
1978}
1979
1980static unw_rec_list *
1981output_rnat_gr (gr)
1982 unsigned int gr;
1983{
1984 unw_rec_list *ptr = alloc_record (rnat_gr);
1985 ptr->r.record.p.gr = gr;
1986 return ptr;
1987}
1988
1989static unw_rec_list *
1990output_rnat_psprel (offset)
1991 unsigned int offset;
1992{
1993 unw_rec_list *ptr = alloc_record (rnat_psprel);
542d6675 1994 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1995 return ptr;
1996}
1997
1998static unw_rec_list *
1999output_rnat_sprel (offset)
2000 unsigned int offset;
2001{
2002 unw_rec_list *ptr = alloc_record (rnat_sprel);
542d6675 2003 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2004 return ptr;
2005}
2006
2007static unw_rec_list *
e0c9811a
JW		 2008output_unwabi (abi, context)
2009 unsigned long abi;
2010 unsigned long context;
800eeca4 2011{
e0c9811a
JW		 2012 unw_rec_list *ptr = alloc_record (unwabi);
2013 ptr->r.record.p.abi = abi;
2014 ptr->r.record.p.context = context;
800eeca4
JW		 2015 return ptr;
2016}
2017
2018static unw_rec_list *
e0c9811a 2019output_epilogue (unsigned long ecount)
800eeca4 2020{
e0c9811a
JW		 2021 unw_rec_list *ptr = alloc_record (epilogue);
2022 ptr->r.record.b.ecount = ecount;
800eeca4
JW		 2023 return ptr;
2024}
2025
2026static unw_rec_list *
e0c9811a 2027output_label_state (unsigned long label)
800eeca4 2028{
e0c9811a
JW		 2029 unw_rec_list *ptr = alloc_record (label_state);
2030 ptr->r.record.b.label = label;
800eeca4
JW		 2031 return ptr;
2032}
2033
2034static unw_rec_list *
e0c9811a
JW		 2035output_copy_state (unsigned long label)
2036{
2037 unw_rec_list *ptr = alloc_record (copy_state);
2038 ptr->r.record.b.label = label;
2039 return ptr;
2040}
2041
2042static unw_rec_list *
2043output_spill_psprel (ab, reg, offset)
2044 unsigned int ab;
800eeca4
JW		 2045 unsigned int reg;
2046 unsigned int offset;
2047{
2048 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 2049 ptr->r.record.x.ab = ab;
800eeca4 2050 ptr->r.record.x.reg = reg;
542d6675 2051 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2052 return ptr;
2053}
2054
2055static unw_rec_list *
e0c9811a
JW		 2056output_spill_sprel (ab, reg, offset)
2057 unsigned int ab;
800eeca4
JW		 2058 unsigned int reg;
2059 unsigned int offset;
2060{
2061 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 2062 ptr->r.record.x.ab = ab;
800eeca4 2063 ptr->r.record.x.reg = reg;
542d6675 2064 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2065 return ptr;
2066}
2067
2068static unw_rec_list *
e0c9811a
JW		 2069output_spill_psprel_p (ab, reg, offset, predicate)
2070 unsigned int ab;
800eeca4
JW		 2071 unsigned int reg;
2072 unsigned int offset;
2073 unsigned int predicate;
2074{
2075 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 2076 ptr->r.record.x.ab = ab;
800eeca4 2077 ptr->r.record.x.reg = reg;
542d6675 2078 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2079 ptr->r.record.x.qp = predicate;
2080 return ptr;
2081}
2082
2083static unw_rec_list *
e0c9811a
JW		 2084output_spill_sprel_p (ab, reg, offset, predicate)
2085 unsigned int ab;
800eeca4
JW		 2086 unsigned int reg;
2087 unsigned int offset;
2088 unsigned int predicate;
2089{
2090 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 2091 ptr->r.record.x.ab = ab;
800eeca4 2092 ptr->r.record.x.reg = reg;
542d6675 2093 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2094 ptr->r.record.x.qp = predicate;
2095 return ptr;
2096}
2097
2098static unw_rec_list *
e0c9811a
JW		 2099output_spill_reg (ab, reg, targ_reg, xy)
2100 unsigned int ab;
800eeca4
JW		 2101 unsigned int reg;
2102 unsigned int targ_reg;
2103 unsigned int xy;
2104{
2105 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 2106 ptr->r.record.x.ab = ab;
800eeca4
JW		 2107 ptr->r.record.x.reg = reg;
2108 ptr->r.record.x.treg = targ_reg;
2109 ptr->r.record.x.xy = xy;
2110 return ptr;
2111}
2112
2113static unw_rec_list *
e0c9811a
JW		 2114output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2115 unsigned int ab;
800eeca4
JW		 2116 unsigned int reg;
2117 unsigned int targ_reg;
2118 unsigned int xy;
2119 unsigned int predicate;
2120{
2121 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 2122 ptr->r.record.x.ab = ab;
800eeca4
JW		 2123 ptr->r.record.x.reg = reg;
2124 ptr->r.record.x.treg = targ_reg;
2125 ptr->r.record.x.xy = xy;
2126 ptr->r.record.x.qp = predicate;
2127 return ptr;
2128}
2129
197865e8 2130/* Given a unw_rec_list process the correct format with the
800eeca4 2131 specified function. */
542d6675 2132
800eeca4
JW		 2133static void
2134process_one_record (ptr, f)
2135 unw_rec_list *ptr;
2136 vbyte_func f;
2137{
e0c9811a
JW		 2138 unsigned long fr_mask, gr_mask;
2139
197865e8 2140 switch (ptr->r.type)
800eeca4 2141 {
542d6675
KH		 2142 case gr_mem:
2143 case fr_mem:
2144 case br_mem:
2145 case frgr_mem:
2146 /* These are taken care of by prologue/prologue_gr. */
2147 break;
e0c9811a 2148
542d6675
KH		 2149 case prologue_gr:
2150 case prologue:
2151 if (ptr->r.type == prologue_gr)
2152 output_R2_format (f, ptr->r.record.r.grmask,
2153 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2154 else
800eeca4 2155 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
542d6675
KH		 2156
2157 /* Output descriptor(s) for union of register spills (if any). */
2158 gr_mask = ptr->r.record.r.mask.gr_mem;
2159 fr_mask = ptr->r.record.r.mask.fr_mem;
2160 if (fr_mask)
2161 {
2162 if ((fr_mask & ~0xfUL) == 0)
2163 output_P6_format (f, fr_mem, fr_mask);
2164 else
2165 {
2166 output_P5_format (f, gr_mask, fr_mask);
2167 gr_mask = 0;
2168 }
2169 }
2170 if (gr_mask)
2171 output_P6_format (f, gr_mem, gr_mask);
2172 if (ptr->r.record.r.mask.br_mem)
2173 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2174
2175 /* output imask descriptor if necessary: */
2176 if (ptr->r.record.r.mask.i)
2177 output_P4_format (f, ptr->r.record.r.mask.i,
2178 ptr->r.record.r.imask_size);
2179 break;
2180
2181 case body:
2182 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2183 break;
2184 case mem_stack_f:
2185 case mem_stack_v:
2186 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2187 ptr->r.record.p.size);
2188 break;
2189 case psp_gr:
2190 case rp_gr:
2191 case pfs_gr:
2192 case preds_gr:
2193 case unat_gr:
2194 case lc_gr:
2195 case fpsr_gr:
2196 case priunat_gr:
2197 case bsp_gr:
2198 case bspstore_gr:
2199 case rnat_gr:
2200 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2201 break;
2202 case rp_br:
2203 output_P3_format (f, rp_br, ptr->r.record.p.br);
2204 break;
2205 case psp_sprel:
2206 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2207 break;
2208 case rp_when:
2209 case pfs_when:
2210 case preds_when:
2211 case unat_when:
2212 case lc_when:
2213 case fpsr_when:
2214 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2215 break;
2216 case rp_psprel:
2217 case pfs_psprel:
2218 case preds_psprel:
2219 case unat_psprel:
2220 case lc_psprel:
2221 case fpsr_psprel:
2222 case spill_base:
2223 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2224 break;
2225 case rp_sprel:
2226 case pfs_sprel:
2227 case preds_sprel:
2228 case unat_sprel:
2229 case lc_sprel:
2230 case fpsr_sprel:
2231 case priunat_sprel:
2232 case bsp_sprel:
2233 case bspstore_sprel:
2234 case rnat_sprel:
2235 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2236 break;
2237 case gr_gr:
2238 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2239 break;
2240 case br_gr:
2241 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2242 break;
2243 case spill_mask:
2244 as_bad ("spill_mask record unimplemented.");
2245 break;
2246 case priunat_when_gr:
2247 case priunat_when_mem:
2248 case bsp_when:
2249 case bspstore_when:
2250 case rnat_when:
2251 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2252 break;
2253 case priunat_psprel:
2254 case bsp_psprel:
2255 case bspstore_psprel:
2256 case rnat_psprel:
2257 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2258 break;
2259 case unwabi:
2260 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2261 break;
2262 case epilogue:
2263 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2264 break;
2265 case label_state:
2266 case copy_state:
2267 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2268 break;
2269 case spill_psprel:
2270 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2271 ptr->r.record.x.reg, ptr->r.record.x.t,
2272 ptr->r.record.x.pspoff);
2273 break;
2274 case spill_sprel:
2275 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2276 ptr->r.record.x.reg, ptr->r.record.x.t,
2277 ptr->r.record.x.spoff);
2278 break;
2279 case spill_reg:
2280 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2281 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2282 ptr->r.record.x.treg, ptr->r.record.x.t);
2283 break;
2284 case spill_psprel_p:
2285 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2286 ptr->r.record.x.ab, ptr->r.record.x.reg,
2287 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2288 break;
2289 case spill_sprel_p:
2290 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2291 ptr->r.record.x.ab, ptr->r.record.x.reg,
2292 ptr->r.record.x.t, ptr->r.record.x.spoff);
2293 break;
2294 case spill_reg_p:
2295 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2296 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2297 ptr->r.record.x.xy, ptr->r.record.x.treg,
2298 ptr->r.record.x.t);
2299 break;
2300 default:
2301 as_bad ("record_type_not_valid");
2302 break;
800eeca4
JW		 2303 }
2304}
2305
197865e8 2306/* Given a unw_rec_list list, process all the records with
800eeca4
JW		 2307 the specified function. */
2308static void
2309process_unw_records (list, f)
2310 unw_rec_list *list;
2311 vbyte_func f;
2312{
2313 unw_rec_list *ptr;
2314 for (ptr = list; ptr; ptr = ptr->next)
2315 process_one_record (ptr, f);
2316}
2317
2318/* Determine the size of a record list in bytes. */
2319static int
2320calc_record_size (list)
2321 unw_rec_list *list;
2322{
2323 vbyte_count = 0;
2324 process_unw_records (list, count_output);
2325 return vbyte_count;
2326}
2327
e0c9811a
JW		 2328/* Update IMASK bitmask to reflect the fact that one or more registers
2329 of type TYPE are saved starting at instruction with index T. If N
2330 bits are set in REGMASK, it is assumed that instructions T through
2331 T+N-1 save these registers.
2332
2333 TYPE values:
2334 0: no save
2335 1: instruction saves next fp reg
2336 2: instruction saves next general reg
2337 3: instruction saves next branch reg */
2338static void
2339set_imask (region, regmask, t, type)
2340 unw_rec_list *region;
2341 unsigned long regmask;
2342 unsigned long t;
2343 unsigned int type;
2344{
2345 unsigned char *imask;
2346 unsigned long imask_size;
2347 unsigned int i;
2348 int pos;
2349
2350 imask = region->r.record.r.mask.i;
2351 imask_size = region->r.record.r.imask_size;
2352 if (!imask)
2353 {
542d6675 2354 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
e0c9811a
JW		 2355 imask = xmalloc (imask_size);
2356 memset (imask, 0, imask_size);
2357
2358 region->r.record.r.imask_size = imask_size;
2359 region->r.record.r.mask.i = imask;
2360 }
2361
542d6675
KH		 2362 i = (t / 4) + 1;
2363 pos = 2 * (3 - t % 4);
e0c9811a
JW		 2364 while (regmask)
2365 {
2366 if (i >= imask_size)
2367 {
2368 as_bad ("Ignoring attempt to spill beyond end of region");
2369 return;
2370 }
2371
2372 imask[i] |= (type & 0x3) << pos;
197865e8 2373
e0c9811a
JW		 2374 regmask &= (regmask - 1);
2375 pos -= 2;
2376 if (pos < 0)
2377 {
2378 pos = 0;
2379 ++i;
2380 }
2381 }
2382}
2383
2384static int
2385count_bits (unsigned long mask)
2386{
2387 int n = 0;
2388
2389 while (mask)
2390 {
2391 mask &= mask - 1;
2392 ++n;
2393 }
2394 return n;
2395}
2396
2397unsigned long
2398slot_index (unsigned long slot_addr, unsigned long first_addr)
2399{
542d6675 2400 return (3 * ((slot_addr >> 4) - (first_addr >> 4))
e0c9811a
JW		 2401 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2402}
2403
800eeca4
JW		 2404/* Given a complete record list, process any records which have
2405 unresolved fields, (ie length counts for a prologue). After
197865e8 2406 this has been run, all neccessary information should be available
800eeca4 2407 within each record to generate an image. */
542d6675 2408
800eeca4
JW		 2409static void
2410fixup_unw_records (list)
2411 unw_rec_list *list;
2412{
e0c9811a
JW		 2413 unw_rec_list *ptr, *region = 0;
2414 unsigned long first_addr = 0, rlen = 0, t;
2415
800eeca4
JW		 2416 for (ptr = list; ptr; ptr = ptr->next)
2417 {
2418 if (ptr->slot_number == SLOT_NUM_NOT_SET)
542d6675 2419 as_bad (" Insn slot not set in unwind record.");
e0c9811a 2420 t = slot_index (ptr->slot_number, first_addr);
800eeca4
JW		 2421 switch (ptr->r.type)
2422 {
542d6675
KH		 2423 case prologue:
2424 case prologue_gr:
2425 case body:
2426 {
2427 unw_rec_list *last;
2428 int size, dir_len = 0;
2429 unsigned long last_addr;
2430
2431 first_addr = ptr->slot_number;
2432 ptr->slot_number = 0;
2433 /* Find either the next body/prologue start, or the end of
2434 the list, and determine the size of the region. */
2435 last_addr = unwind.next_slot_number;
2436 for (last = ptr->next; last != NULL; last = last->next)
2437 if (last->r.type == prologue || last->r.type == prologue_gr
2438 || last->r.type == body)
2439 {
2440 last_addr = last->slot_number;
2441 break;
2442 }
2443 else if (!last->next)
2444 {
2445 /* In the absence of an explicit .body directive,
2446 the prologue ends after the last instruction
2447 covered by an unwind directive. */
2448 if (ptr->r.type != body)
2449 {
2450 last_addr = last->slot_number;
2451 switch (last->r.type)
2452 {
2453 case frgr_mem:
2454 dir_len = (count_bits (last->r.record.p.frmask)
2455 + count_bits (last->r.record.p.grmask));
2456 break;
2457 case fr_mem:
2458 case gr_mem:
2459 dir_len += count_bits (last->r.record.p.rmask);
2460 break;
2461 case br_mem:
2462 case br_gr:
2463 dir_len += count_bits (last->r.record.p.brmask);
2464 break;
2465 case gr_gr:
2466 dir_len += count_bits (last->r.record.p.grmask);
2467 break;
2468 default:
2469 dir_len = 1;
2470 break;
2471 }
2472 }
2473 break;
2474 }
2475 size = slot_index (last_addr, first_addr) + dir_len;
2476 rlen = ptr->r.record.r.rlen = size;
2477 region = ptr;
e0c9811a 2478 break;
542d6675
KH		 2479 }
2480 case epilogue:
2481 ptr->r.record.b.t = rlen - 1 - t;
2482 break;
e0c9811a 2483
542d6675
KH		 2484 case mem_stack_f:
2485 case mem_stack_v:
2486 case rp_when:
2487 case pfs_when:
2488 case preds_when:
2489 case unat_when:
2490 case lc_when:
2491 case fpsr_when:
2492 case priunat_when_gr:
2493 case priunat_when_mem:
2494 case bsp_when:
2495 case bspstore_when:
2496 case rnat_when:
2497 ptr->r.record.p.t = t;
2498 break;
e0c9811a 2499
542d6675
KH		 2500 case spill_reg:
2501 case spill_sprel:
2502 case spill_psprel:
2503 case spill_reg_p:
2504 case spill_sprel_p:
2505 case spill_psprel_p:
2506 ptr->r.record.x.t = t;
2507 break;
e0c9811a 2508
542d6675
KH		 2509 case frgr_mem:
2510 if (!region)
2511 {
2512 as_bad ("frgr_mem record before region record!\n");
2513 return;
2514 }
2515 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2516 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2517 set_imask (region, ptr->r.record.p.frmask, t, 1);
2518 set_imask (region, ptr->r.record.p.grmask, t, 2);
2519 break;
2520 case fr_mem:
2521 if (!region)
2522 {
2523 as_bad ("fr_mem record before region record!\n");
2524 return;
2525 }
2526 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2527 set_imask (region, ptr->r.record.p.rmask, t, 1);
2528 break;
2529 case gr_mem:
2530 if (!region)
2531 {
2532 as_bad ("gr_mem record before region record!\n");
2533 return;
2534 }
2535 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2536 set_imask (region, ptr->r.record.p.rmask, t, 2);
2537 break;
2538 case br_mem:
2539 if (!region)
2540 {
2541 as_bad ("br_mem record before region record!\n");
2542 return;
2543 }
2544 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2545 set_imask (region, ptr->r.record.p.brmask, t, 3);
2546 break;
e0c9811a 2547
542d6675
KH		 2548 case gr_gr:
2549 if (!region)
2550 {
2551 as_bad ("gr_gr record before region record!\n");
2552 return;
2553 }
2554 set_imask (region, ptr->r.record.p.grmask, t, 2);
2555 break;
2556 case br_gr:
2557 if (!region)
2558 {
2559 as_bad ("br_gr record before region record!\n");
2560 return;
2561 }
2562 set_imask (region, ptr->r.record.p.brmask, t, 3);
2563 break;
e0c9811a 2564
542d6675
KH		 2565 default:
2566 break;
800eeca4
JW		 2567 }
2568 }
2569}
2570
2571/* Generate an unwind image from a record list. Returns the number of
2572 bytes in the resulting image. The memory image itselof is returned
2573 in the 'ptr' parameter. */
2574static int
2575output_unw_records (list, ptr)
2576 unw_rec_list *list;
2577 void **ptr;
2578{
2579 int size, x, extra = 0;
2580 unsigned char *mem;
2581
2582 fixup_unw_records (list);
2583 size = calc_record_size (list);
2584
2585 /* pad to 8 byte boundry. */
2586 x = size % 8;
2587 if (x != 0)
2588 extra = 8 - x;
2589 /* Add 8 for the header + 8 more bytes for the personality offset. */
2590 mem = xmalloc (size + extra + 16);
2591
2592 vbyte_mem_ptr = mem + 8;
2593 /* Clear the padding area and personality. */
2594 memset (mem + 8 + size, 0 , extra + 8);
2595 /* Initialize the header area. */
efcc5914
JW		 2596 md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
2597 | (unwind.personality_routine
2598 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2599 : 0)
e4c58b25
JW		 2600 | ((size + extra) / 8)), /* length (dwords) */
2601 8);
800eeca4
JW		 2602
2603 process_unw_records (list, output_vbyte_mem);
2604
2605 *ptr = mem;
2606 return size + extra + 16;
2607}
2608
e0c9811a
JW		 2609static int
2610convert_expr_to_ab_reg (e, ab, regp)
2611 expressionS *e;
2612 unsigned int *ab;
2613 unsigned int *regp;
2614{
2615 unsigned int reg;
2616
2617 if (e->X_op != O_register)
2618 return 0;
2619
2620 reg = e->X_add_number;
2621 if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
2622 {
2623 *ab = 0;
2624 *regp = reg - REG_GR;
2625 }
2626 else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
2627 || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
2628 {
2629 *ab = 1;
2630 *regp = reg - REG_FR;
2631 }
2632 else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
2633 {
2634 *ab = 2;
2635 *regp = reg - REG_BR;
2636 }
2637 else
2638 {
2639 *ab = 3;
2640 switch (reg)
2641 {
2642 case REG_PR: *regp = 0; break;
2643 case REG_PSP: *regp = 1; break;
2644 case REG_PRIUNAT: *regp = 2; break;
2645 case REG_BR + 0: *regp = 3; break;
2646 case REG_AR + AR_BSP: *regp = 4; break;
2647 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2648 case REG_AR + AR_RNAT: *regp = 6; break;
2649 case REG_AR + AR_UNAT: *regp = 7; break;
2650 case REG_AR + AR_FPSR: *regp = 8; break;
2651 case REG_AR + AR_PFS: *regp = 9; break;
2652 case REG_AR + AR_LC: *regp = 10; break;
2653
2654 default:
2655 return 0;
2656 }
2657 }
2658 return 1;
197865e8 2659}
e0c9811a
JW		 2660
2661static int
2662convert_expr_to_xy_reg (e, xy, regp)
2663 expressionS *e;
2664 unsigned int *xy;
2665 unsigned int *regp;
2666{
2667 unsigned int reg;
2668
2669 if (e->X_op != O_register)
2670 return 0;
2671
2672 reg = e->X_add_number;
2673
2674 if (reg >= REG_GR && reg <= REG_GR + 127)
2675 {
2676 *xy = 0;
2677 *regp = reg - REG_GR;
2678 }
2679 else if (reg >= REG_FR && reg <= REG_FR + 127)
2680 {
2681 *xy = 1;
2682 *regp = reg - REG_FR;
2683 }
2684 else if (reg >= REG_BR && reg <= REG_BR + 7)
2685 {
2686 *xy = 2;
2687 *regp = reg - REG_BR;
2688 }
2689 else
2690 return -1;
2691 return 1;
197865e8 2692}
e0c9811a 2693
800eeca4
JW		 2694static void
2695dot_radix (dummy)
2696 int dummy;
2697{
2698 int radix;
2699
2700 SKIP_WHITESPACE ();
2701 radix = *input_line_pointer++;
2702
2703 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2704 {
2705 as_bad ("Radix `%c' unsupported", *input_line_pointer);
542d6675 2706 ignore_rest_of_line ();
800eeca4
JW		 2707 return;
2708 }
2709}
2710
2711/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2712static void
2713dot_special_section (which)
2714 int which;
2715{
2716 set_section ((char *) special_section_name[which]);
2717}
2718
2719static void
2720add_unwind_entry (ptr)
2721 unw_rec_list *ptr;
2722{
e0c9811a
JW		 2723 if (unwind.tail)
2724 unwind.tail->next = ptr;
800eeca4 2725 else
e0c9811a
JW		 2726 unwind.list = ptr;
2727 unwind.tail = ptr;
800eeca4
JW		 2728
2729 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW		 2730 if (unwind.current_entry == NULL)
2731 unwind.current_entry = ptr;
800eeca4
JW		 2732}
2733
197865e8 2734static void
800eeca4
JW		 2735dot_fframe (dummy)
2736 int dummy;
2737{
2738 expressionS e;
e0c9811a 2739
800eeca4 2740 parse_operand (&e);
197865e8 2741
800eeca4
JW		 2742 if (e.X_op != O_constant)
2743 as_bad ("Operand to .fframe must be a constant");
2744 else
e0c9811a
JW		 2745 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2746}
2747
197865e8 2748static void
e0c9811a
JW		 2749dot_vframe (dummy)
2750 int dummy;
2751{
2752 expressionS e;
2753 unsigned reg;
2754
2755 parse_operand (&e);
2756 reg = e.X_add_number - REG_GR;
2757 if (e.X_op == O_register && reg < 128)
800eeca4 2758 {
e0c9811a 2759 add_unwind_entry (output_mem_stack_v ());
30d25259
RH		 2760 if (! (unwind.prologue_mask & 2))
2761 add_unwind_entry (output_psp_gr (reg));
800eeca4 2762 }
e0c9811a
JW		 2763 else
2764 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW		 2765}
2766
197865e8 2767static void
e0c9811a 2768dot_vframesp (dummy)
800eeca4
JW		 2769 int dummy;
2770{
e0c9811a
JW		 2771 expressionS e;
2772
2773 parse_operand (&e);
2774 if (e.X_op == O_constant)
2775 {
2776 add_unwind_entry (output_mem_stack_v ());
2777 add_unwind_entry (output_psp_sprel (e.X_add_number));
2778 }
2779 else
2780 as_bad ("First operand to .vframesp must be a general register");
2781}
2782
197865e8 2783static void
e0c9811a
JW		 2784dot_vframepsp (dummy)
2785 int dummy;
2786{
2787 expressionS e;
2788
2789 parse_operand (&e);
2790 if (e.X_op == O_constant)
2791 {
2792 add_unwind_entry (output_mem_stack_v ());
2793 add_unwind_entry (output_psp_sprel (e.X_add_number));
2794 }
2795 else
2796 as_bad ("First operand to .vframepsp must be a general register");
800eeca4
JW		 2797}
2798
197865e8 2799static void
800eeca4
JW		 2800dot_save (dummy)
2801 int dummy;
2802{
2803 expressionS e1, e2;
2804 int sep;
2805 int reg1, reg2;
2806
2807 sep = parse_operand (&e1);
2808 if (sep != ',')
2809 as_bad ("No second operand to .save");
2810 sep = parse_operand (&e2);
2811
e0c9811a 2812 reg1 = e1.X_add_number;
800eeca4 2813 reg2 = e2.X_add_number - REG_GR;
197865e8 2814
800eeca4 2815 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 2816 if (e1.X_op == O_register)
800eeca4 2817 {
542d6675 2818 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
800eeca4
JW		 2819 {
2820 switch (reg1)
2821 {
542d6675
KH		 2822 case REG_AR + AR_BSP:
2823 add_unwind_entry (output_bsp_when ());
2824 add_unwind_entry (output_bsp_gr (reg2));
2825 break;
2826 case REG_AR + AR_BSPSTORE:
2827 add_unwind_entry (output_bspstore_when ());
2828 add_unwind_entry (output_bspstore_gr (reg2));
2829 break;
2830 case REG_AR + AR_RNAT:
2831 add_unwind_entry (output_rnat_when ());
2832 add_unwind_entry (output_rnat_gr (reg2));
2833 break;
2834 case REG_AR + AR_UNAT:
2835 add_unwind_entry (output_unat_when ());
2836 add_unwind_entry (output_unat_gr (reg2));
2837 break;
2838 case REG_AR + AR_FPSR:
2839 add_unwind_entry (output_fpsr_when ());
2840 add_unwind_entry (output_fpsr_gr (reg2));
2841 break;
2842 case REG_AR + AR_PFS:
2843 add_unwind_entry (output_pfs_when ());
2844 if (! (unwind.prologue_mask & 4))
2845 add_unwind_entry (output_pfs_gr (reg2));
2846 break;
2847 case REG_AR + AR_LC:
2848 add_unwind_entry (output_lc_when ());
2849 add_unwind_entry (output_lc_gr (reg2));
2850 break;
2851 case REG_BR:
2852 add_unwind_entry (output_rp_when ());
2853 if (! (unwind.prologue_mask & 8))
2854 add_unwind_entry (output_rp_gr (reg2));
2855 break;
2856 case REG_PR:
2857 add_unwind_entry (output_preds_when ());
2858 if (! (unwind.prologue_mask & 1))
2859 add_unwind_entry (output_preds_gr (reg2));
2860 break;
2861 case REG_PRIUNAT:
2862 add_unwind_entry (output_priunat_when_gr ());
2863 add_unwind_entry (output_priunat_gr (reg2));
2864 break;
2865 default:
2866 as_bad ("First operand not a valid register");
800eeca4
JW		 2867 }
2868 }
2869 else
2870 as_bad (" Second operand not a valid register");
2871 }
2872 else
e0c9811a 2873 as_bad ("First operand not a register");
800eeca4
JW		 2874}
2875
197865e8 2876static void
800eeca4
JW		 2877dot_restore (dummy)
2878 int dummy;
2879{
e0c9811a
JW		 2880 expressionS e1, e2;
2881 unsigned long ecount = 0;
2882 int sep;
2883
2884 sep = parse_operand (&e1);
2885 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2886 {
2887 as_bad ("First operand to .restore must be stack pointer (sp)");
2888 return;
2889 }
2890
2891 if (sep == ',')
2892 {
2893 parse_operand (&e2);
2894 if (e1.X_op != O_constant)
2895 {
2896 as_bad ("Second operand to .restore must be constant");
2897 return;
2898 }
2899 ecount = e1.X_op;
2900 }
2901 add_unwind_entry (output_epilogue (ecount));
2902}
2903
197865e8 2904static void
e0c9811a
JW		 2905dot_restorereg (dummy)
2906 int dummy;
2907{
2908 unsigned int ab, reg;
2909 expressionS e;
2910
2911 parse_operand (&e);
2912
2913 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
2914 {
2915 as_bad ("First operand to .restorereg must be a preserved register");
2916 return;
2917 }
2918 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
2919}
2920
197865e8 2921static void
e0c9811a
JW		 2922dot_restorereg_p (dummy)
2923 int dummy;
2924{
2925 unsigned int qp, ab, reg;
2926 expressionS e1, e2;
2927 int sep;
2928
2929 sep = parse_operand (&e1);
2930 if (sep != ',')
2931 {
2932 as_bad ("No second operand to .restorereg.p");
2933 return;
2934 }
2935
2936 parse_operand (&e2);
2937
2938 qp = e1.X_add_number - REG_P;
2939 if (e1.X_op != O_register || qp > 63)
2940 {
2941 as_bad ("First operand to .restorereg.p must be a predicate");
2942 return;
2943 }
2944
2945 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
2946 {
2947 as_bad ("Second operand to .restorereg.p must be a preserved register");
2948 return;
2949 }
2950 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW		 2951}
2952
2953static int
2954generate_unwind_image ()
2955{
2956 int size;
2957 unsigned char *unw_rec;
800eeca4 2958
10850f29
JW		 2959 /* Force out pending instructions, to make sure all unwind records have
2960 a valid slot_number field. */
2961 ia64_flush_insns ();
2962
800eeca4 2963 /* Generate the unwind record. */
150f24a2 2964 size = output_unw_records (unwind.list, (void **) &unw_rec);
e0c9811a
JW		 2965 if (size % 8 != 0)
2966 as_bad ("Unwind record is not a multiple of 8 bytes.");
800eeca4
JW		 2967
2968 /* If there are unwind records, switch sections, and output the info. */
2969 if (size != 0)
2970 {
800eeca4 2971 unsigned char *where;
800eeca4 2972 expressionS exp;
800eeca4
JW		 2973 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
2974
2975 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 2976 unwind.info = expr_build_dot ();
800eeca4 2977
542d6675 2978 where = (unsigned char *) frag_more (size);
800eeca4
JW		 2979
2980 /* Issue a label for this address, and keep track of it to put it
2981 in the unwind section. */
2982
2983 /* Copy the information from the unwind record into this section. The
2984 data is already in the correct byte order. */
2985 memcpy (where, unw_rec, size);
2986 /* Add the personality address to the image. */
e0c9811a 2987 if (unwind.personality_routine != 0)
542d6675 2988 {
800eeca4 2989 exp.X_op = O_symbol;
e0c9811a 2990 exp.X_add_symbol = unwind.personality_routine;
800eeca4
JW		 2991 exp.X_add_number = 0;
2992 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
2993 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
e0c9811a 2994 unwind.personality_routine = 0;
542d6675 2995 }
800eeca4
JW		 2996 obj_elf_previous (0);
2997 }
2998
e0c9811a
JW		 2999 free_list_records (unwind.list);
3000 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW		 3001
3002 return size;
3003}
3004
197865e8 3005static void
542d6675 3006dot_handlerdata (dummy)
800eeca4
JW		 3007 int dummy;
3008{
3009 generate_unwind_image ();
e0c9811a 3010 demand_empty_rest_of_line ();
800eeca4
JW		 3011}
3012
197865e8 3013static void
800eeca4
JW		 3014dot_unwentry (dummy)
3015 int dummy;
3016{
e0c9811a 3017 demand_empty_rest_of_line ();
800eeca4
JW		 3018}
3019
197865e8 3020static void
800eeca4
JW		 3021dot_altrp (dummy)
3022 int dummy;
3023{
e0c9811a
JW		 3024 expressionS e;
3025 unsigned reg;
3026
3027 parse_operand (&e);
3028 reg = e.X_add_number - REG_BR;
3029 if (e.X_op == O_register && reg < 8)
3030 add_unwind_entry (output_rp_br (reg));
3031 else
3032 as_bad ("First operand not a valid branch register");
800eeca4
JW		 3033}
3034
197865e8 3035static void
e0c9811a
JW		 3036dot_savemem (psprel)
3037 int psprel;
800eeca4
JW		 3038{
3039 expressionS e1, e2;
3040 int sep;
3041 int reg1, val;
3042
3043 sep = parse_operand (&e1);
3044 if (sep != ',')
e0c9811a 3045 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW		 3046 sep = parse_operand (&e2);
3047
e0c9811a 3048 reg1 = e1.X_add_number;
800eeca4 3049 val = e2.X_add_number;
197865e8 3050
800eeca4 3051 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3052 if (e1.X_op == O_register)
800eeca4
JW		 3053 {
3054 if (e2.X_op == O_constant)
3055 {
3056 switch (reg1)
3057 {
542d6675
KH		 3058 case REG_AR + AR_BSP:
3059 add_unwind_entry (output_bsp_when ());
3060 add_unwind_entry ((psprel
3061 ? output_bsp_psprel
3062 : output_bsp_sprel) (val));
3063 break;
3064 case REG_AR + AR_BSPSTORE:
3065 add_unwind_entry (output_bspstore_when ());
3066 add_unwind_entry ((psprel
3067 ? output_bspstore_psprel
3068 : output_bspstore_sprel) (val));
3069 break;
3070 case REG_AR + AR_RNAT:
3071 add_unwind_entry (output_rnat_when ());
3072 add_unwind_entry ((psprel
3073 ? output_rnat_psprel
3074 : output_rnat_sprel) (val));
3075 break;
3076 case REG_AR + AR_UNAT:
3077 add_unwind_entry (output_unat_when ());
3078 add_unwind_entry ((psprel
3079 ? output_unat_psprel
3080 : output_unat_sprel) (val));
3081 break;
3082 case REG_AR + AR_FPSR:
3083 add_unwind_entry (output_fpsr_when ());
3084 add_unwind_entry ((psprel
3085 ? output_fpsr_psprel
3086 : output_fpsr_sprel) (val));
3087 break;
3088 case REG_AR + AR_PFS:
3089 add_unwind_entry (output_pfs_when ());
3090 add_unwind_entry ((psprel
3091 ? output_pfs_psprel
3092 : output_pfs_sprel) (val));
3093 break;
3094 case REG_AR + AR_LC:
3095 add_unwind_entry (output_lc_when ());
3096 add_unwind_entry ((psprel
3097 ? output_lc_psprel
3098 : output_lc_sprel) (val));
3099 break;
3100 case REG_BR:
3101 add_unwind_entry (output_rp_when ());
3102 add_unwind_entry ((psprel
3103 ? output_rp_psprel
3104 : output_rp_sprel) (val));
3105 break;
3106 case REG_PR:
3107 add_unwind_entry (output_preds_when ());
3108 add_unwind_entry ((psprel
3109 ? output_preds_psprel
3110 : output_preds_sprel) (val));
3111 break;
3112 case REG_PRIUNAT:
3113 add_unwind_entry (output_priunat_when_mem ());
3114 add_unwind_entry ((psprel
3115 ? output_priunat_psprel
3116 : output_priunat_sprel) (val));
3117 break;
3118 default:
3119 as_bad ("First operand not a valid register");
800eeca4
JW		 3120 }
3121 }
3122 else
3123 as_bad (" Second operand not a valid constant");
3124 }
3125 else
e0c9811a 3126 as_bad ("First operand not a register");
800eeca4
JW		 3127}
3128
197865e8 3129static void
800eeca4
JW		 3130dot_saveg (dummy)
3131 int dummy;
3132{
3133 expressionS e1, e2;
3134 int sep;
3135 sep = parse_operand (&e1);
3136 if (sep == ',')
3137 parse_operand (&e2);
197865e8 3138
800eeca4
JW		 3139 if (e1.X_op != O_constant)
3140 as_bad ("First operand to .save.g must be a constant.");
3141 else
3142 {
3143 int grmask = e1.X_add_number;
3144 if (sep != ',')
3145 add_unwind_entry (output_gr_mem (grmask));
3146 else
542d6675 3147 {
800eeca4 3148 int reg = e2.X_add_number - REG_GR;
542d6675 3149 if (e2.X_op == O_register && reg >= 0 && reg < 128)
800eeca4
JW		 3150 add_unwind_entry (output_gr_gr (grmask, reg));
3151 else
3152 as_bad ("Second operand is an invalid register.");
3153 }
3154 }
3155}
3156
197865e8 3157static void
800eeca4
JW		 3158dot_savef (dummy)
3159 int dummy;
3160{
e0c9811a 3161 expressionS e1;
800eeca4
JW		 3162 int sep;
3163 sep = parse_operand (&e1);
197865e8 3164
800eeca4
JW		 3165 if (e1.X_op != O_constant)
3166 as_bad ("Operand to .save.f must be a constant.");
3167 else
e0c9811a 3168 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW		 3169}
3170
197865e8 3171static void
800eeca4
JW		 3172dot_saveb (dummy)
3173 int dummy;
3174{
e0c9811a
JW		 3175 expressionS e1, e2;
3176 unsigned int reg;
3177 unsigned char sep;
3178 int brmask;
3179
800eeca4 3180 sep = parse_operand (&e1);
800eeca4 3181 if (e1.X_op != O_constant)
800eeca4 3182 {
e0c9811a
JW		 3183 as_bad ("First operand to .save.b must be a constant.");
3184 return;
800eeca4 3185 }
e0c9811a
JW		 3186 brmask = e1.X_add_number;
3187
3188 if (sep == ',')
3189 {
3190 sep = parse_operand (&e2);
3191 reg = e2.X_add_number - REG_GR;
3192 if (e2.X_op != O_register || reg > 127)
3193 {
3194 as_bad ("Second operand to .save.b must be a general register.");
3195 return;
3196 }
3197 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3198 }
3199 else
3200 add_unwind_entry (output_br_mem (brmask));
3201
3202 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3203 ignore_rest_of_line ();
800eeca4
JW		 3204}
3205
197865e8 3206static void
800eeca4
JW		 3207dot_savegf (dummy)
3208 int dummy;
3209{
3210 expressionS e1, e2;
3211 int sep;
3212 sep = parse_operand (&e1);
3213 if (sep == ',')
3214 parse_operand (&e2);
197865e8 3215
800eeca4
JW		 3216 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3217 as_bad ("Both operands of .save.gf must be constants.");
3218 else
3219 {
3220 int grmask = e1.X_add_number;
3221 int frmask = e2.X_add_number;
3222 add_unwind_entry (output_frgr_mem (grmask, frmask));
3223 }
3224}
3225
197865e8 3226static void
800eeca4
JW		 3227dot_spill (dummy)
3228 int dummy;
3229{
3230 expressionS e;
e0c9811a
JW		 3231 unsigned char sep;
3232
3233 sep = parse_operand (&e);
3234 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3235 ignore_rest_of_line ();
197865e8 3236
800eeca4
JW		 3237 if (e.X_op != O_constant)
3238 as_bad ("Operand to .spill must be a constant");
3239 else
e0c9811a
JW		 3240 add_unwind_entry (output_spill_base (e.X_add_number));
3241}
3242
3243static void
3244dot_spillreg (dummy)
3245 int dummy;
3246{
3247 int sep, ab, xy, reg, treg;
3248 expressionS e1, e2;
3249
3250 sep = parse_operand (&e1);
3251 if (sep != ',')
3252 {
3253 as_bad ("No second operand to .spillreg");
3254 return;
3255 }
3256
3257 parse_operand (&e2);
3258
3259 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3260 {
e0c9811a
JW		 3261 as_bad ("First operand to .spillreg must be a preserved register");
3262 return;
800eeca4 3263 }
e0c9811a
JW		 3264
3265 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3266 {
3267 as_bad ("Second operand to .spillreg must be a register");
3268 return;
3269 }
3270
3271 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3272}
3273
3274static void
3275dot_spillmem (psprel)
3276 int psprel;
3277{
3278 expressionS e1, e2;
3279 int sep, ab, reg;
3280
3281 sep = parse_operand (&e1);
3282 if (sep != ',')
3283 {
3284 as_bad ("Second operand missing");
3285 return;
3286 }
3287
3288 parse_operand (&e2);
3289
3290 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3291 {
3292 as_bad ("First operand to .spill%s must be a preserved register",
3293 psprel ? "psp" : "sp");
3294 return;
3295 }
3296
3297 if (e2.X_op != O_constant)
3298 {
3299 as_bad ("Second operand to .spill%s must be a constant",
3300 psprel ? "psp" : "sp");
3301 return;
3302 }
3303
3304 if (psprel)
3305 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3306 else
3307 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3308}
3309
3310static void
3311dot_spillreg_p (dummy)
3312 int dummy;
3313{
3314 int sep, ab, xy, reg, treg;
3315 expressionS e1, e2, e3;
3316 unsigned int qp;
3317
3318 sep = parse_operand (&e1);
3319 if (sep != ',')
3320 {
3321 as_bad ("No second and third operand to .spillreg.p");
3322 return;
3323 }
3324
3325 sep = parse_operand (&e2);
3326 if (sep != ',')
3327 {
3328 as_bad ("No third operand to .spillreg.p");
3329 return;
3330 }
3331
3332 parse_operand (&e3);
3333
3334 qp = e1.X_add_number - REG_P;
3335
3336 if (e1.X_op != O_register || qp > 63)
3337 {
3338 as_bad ("First operand to .spillreg.p must be a predicate");
3339 return;
3340 }
3341
3342 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3343 {
3344 as_bad ("Second operand to .spillreg.p must be a preserved register");
3345 return;
3346 }
3347
3348 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3349 {
3350 as_bad ("Third operand to .spillreg.p must be a register");
3351 return;
3352 }
3353
3354 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3355}
3356
3357static void
3358dot_spillmem_p (psprel)
3359 int psprel;
3360{
3361 expressionS e1, e2, e3;
3362 int sep, ab, reg;
3363 unsigned int qp;
3364
3365 sep = parse_operand (&e1);
3366 if (sep != ',')
3367 {
3368 as_bad ("Second operand missing");
3369 return;
3370 }
3371
3372 parse_operand (&e2);
3373 if (sep != ',')
3374 {
3375 as_bad ("Second operand missing");
3376 return;
3377 }
3378
3379 parse_operand (&e3);
3380
3381 qp = e1.X_add_number - REG_P;
3382 if (e1.X_op != O_register || qp > 63)
3383 {
3384 as_bad ("First operand to .spill%s_p must be a predicate",
3385 psprel ? "psp" : "sp");
3386 return;
3387 }
3388
3389 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3390 {
3391 as_bad ("Second operand to .spill%s_p must be a preserved register",
3392 psprel ? "psp" : "sp");
3393 return;
3394 }
3395
3396 if (e3.X_op != O_constant)
3397 {
3398 as_bad ("Third operand to .spill%s_p must be a constant",
3399 psprel ? "psp" : "sp");
3400 return;
3401 }
3402
3403 if (psprel)
3404 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3405 else
3406 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3407}
3408
3409static void
3410dot_label_state (dummy)
3411 int dummy;
3412{
3413 expressionS e;
3414
3415 parse_operand (&e);
3416 if (e.X_op != O_constant)
3417 {
3418 as_bad ("Operand to .label_state must be a constant");
3419 return;
3420 }
3421 add_unwind_entry (output_label_state (e.X_add_number));
3422}
3423
3424static void
3425dot_copy_state (dummy)
3426 int dummy;
3427{
3428 expressionS e;
3429
3430 parse_operand (&e);
3431 if (e.X_op != O_constant)
3432 {
3433 as_bad ("Operand to .copy_state must be a constant");
3434 return;
3435 }
3436 add_unwind_entry (output_copy_state (e.X_add_number));
800eeca4
JW		 3437}
3438
197865e8 3439static void
800eeca4
JW		 3440dot_unwabi (dummy)
3441 int dummy;
3442{
e0c9811a
JW		 3443 expressionS e1, e2;
3444 unsigned char sep;
3445
3446 sep = parse_operand (&e1);
3447 if (sep != ',')
3448 {
3449 as_bad ("Second operand to .unwabi missing");
3450 return;
3451 }
3452 sep = parse_operand (&e2);
3453 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3454 ignore_rest_of_line ();
3455
3456 if (e1.X_op != O_constant)
3457 {
3458 as_bad ("First operand to .unwabi must be a constant");
3459 return;
3460 }
3461
3462 if (e2.X_op != O_constant)
3463 {
3464 as_bad ("Second operand to .unwabi must be a constant");
3465 return;
3466 }
3467
3468 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW		 3469}
3470
197865e8 3471static void
800eeca4
JW		 3472dot_personality (dummy)
3473 int dummy;
3474{
3475 char *name, *p, c;
3476 SKIP_WHITESPACE ();
3477 name = input_line_pointer;
3478 c = get_symbol_end ();
3479 p = input_line_pointer;
e0c9811a 3480 unwind.personality_routine = symbol_find_or_make (name);
800eeca4
JW		 3481 *p = c;
3482 SKIP_WHITESPACE ();
3483 demand_empty_rest_of_line ();
3484}
3485
3486static void
3487dot_proc (dummy)
3488 int dummy;
3489{
3490 char *name, *p, c;
3491 symbolS *sym;
3492
e0c9811a
JW		 3493 unwind.proc_start = expr_build_dot ();
3494 /* Parse names of main and alternate entry points and mark them as
542d6675 3495 function symbols: */
800eeca4
JW		 3496 while (1)
3497 {
3498 SKIP_WHITESPACE ();
3499 name = input_line_pointer;
3500 c = get_symbol_end ();
3501 p = input_line_pointer;
3502 sym = symbol_find_or_make (name);
e0c9811a 3503 if (unwind.proc_start == 0)
542d6675 3504 {
e0c9811a 3505 unwind.proc_start = sym;
800eeca4
JW		 3506 }
3507 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3508 *p = c;
3509 SKIP_WHITESPACE ();
3510 if (*input_line_pointer != ',')
3511 break;
3512 ++input_line_pointer;
3513 }
3514 demand_empty_rest_of_line ();
3515 ia64_do_align (16);
3516
e0c9811a
JW		 3517 unwind.list = unwind.tail = unwind.current_entry = NULL;
3518 unwind.personality_routine = 0;
800eeca4
JW		 3519}
3520
3521static void
3522dot_body (dummy)
3523 int dummy;
3524{
e0c9811a 3525 unwind.prologue = 0;
30d25259
RH		 3526 unwind.prologue_mask = 0;
3527
800eeca4 3528 add_unwind_entry (output_body ());
e0c9811a 3529 demand_empty_rest_of_line ();
800eeca4
JW		 3530}
3531
3532static void
3533dot_prologue (dummy)
3534 int dummy;
3535{
e0c9811a 3536 unsigned char sep;
30d25259 3537 int mask = 0, grsave;
e0c9811a 3538
e0c9811a 3539 if (!is_it_end_of_statement ())
800eeca4
JW		 3540 {
3541 expressionS e1, e2;
800eeca4
JW		 3542 sep = parse_operand (&e1);
3543 if (sep != ',')
3544 as_bad ("No second operand to .prologue");
3545 sep = parse_operand (&e2);
e0c9811a 3546 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
542d6675 3547 ignore_rest_of_line ();
800eeca4
JW		 3548
3549 if (e1.X_op == O_constant)
542d6675 3550 {
30d25259
RH		 3551 mask = e1.X_add_number;
3552
800eeca4 3553 if (e2.X_op == O_constant)
30d25259
RH		 3554 grsave = e2.X_add_number;
3555 else if (e2.X_op == O_register
3556 && (grsave = e2.X_add_number - REG_GR) < 128)
3557 ;
800eeca4 3558 else
30d25259
RH		 3559 as_bad ("Second operand not a constant or general register");
3560
3561 add_unwind_entry (output_prologue_gr (mask, grsave));
800eeca4
JW		 3562 }
3563 else
3564 as_bad ("First operand not a constant");
3565 }
3566 else
3567 add_unwind_entry (output_prologue ());
30d25259
RH		 3568
3569 unwind.prologue = 1;
3570 unwind.prologue_mask = mask;
800eeca4
JW		 3571}
3572
3573static void
3574dot_endp (dummy)
3575 int dummy;
3576{
3577 expressionS e;
3578 unsigned char *ptr;
800eeca4
JW		 3579 long where;
3580 segT saved_seg;
3581 subsegT saved_subseg;
3582
3583 saved_seg = now_seg;
3584 saved_subseg = now_subseg;
3585
3586 expression (&e);
3587 demand_empty_rest_of_line ();
3588
3589 insn_group_break (1, 0, 0);
800eeca4
JW		 3590
3591 /* If there was a .handlerdata, we haven't generated an image yet. */
e0c9811a 3592 if (unwind.info == 0)
800eeca4
JW		 3593 {
3594 generate_unwind_image ();
3595 }
3596
3597 subseg_set (md.last_text_seg, 0);
e0c9811a 3598 unwind.proc_end = expr_build_dot ();
800eeca4
JW		 3599
3600 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3601 ptr = frag_more (24);
3602 where = frag_now_fix () - 24;
3603
3604 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3605 e.X_op = O_pseudo_fixup;
3606 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3607 e.X_add_number = 0;
e0c9811a 3608 e.X_add_symbol = unwind.proc_start;
800eeca4
JW		 3609 ia64_cons_fix_new (frag_now, where, 8, &e);
3610
3611 e.X_op = O_pseudo_fixup;
3612 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3613 e.X_add_number = 0;
e0c9811a 3614 e.X_add_symbol = unwind.proc_end;
800eeca4
JW		 3615 ia64_cons_fix_new (frag_now, where + 8, 8, &e);
3616
e0c9811a 3617 if (unwind.info != 0)
800eeca4
JW		 3618 {
3619 e.X_op = O_pseudo_fixup;
3620 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3621 e.X_add_number = 0;
e0c9811a 3622 e.X_add_symbol = unwind.info;
800eeca4
JW		 3623 ia64_cons_fix_new (frag_now, where + 16, 8, &e);
3624 }
3625 else
3626 md_number_to_chars (ptr + 16, 0, 8);
3627
3628 subseg_set (saved_seg, saved_subseg);
e0c9811a 3629 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW		 3630}
3631
3632static void
3633dot_template (template)
3634 int template;
3635{
3636 CURR_SLOT.user_template = template;
3637}
3638
3639static void
3640dot_regstk (dummy)
3641 int dummy;
3642{
3643 int ins, locs, outs, rots;
3644
3645 if (is_it_end_of_statement ())
3646 ins = locs = outs = rots = 0;
3647 else
3648 {
3649 ins = get_absolute_expression ();
3650 if (*input_line_pointer++ != ',')
3651 goto err;
3652 locs = get_absolute_expression ();
3653 if (*input_line_pointer++ != ',')
3654 goto err;
3655 outs = get_absolute_expression ();
3656 if (*input_line_pointer++ != ',')
3657 goto err;
3658 rots = get_absolute_expression ();
3659 }
3660 set_regstack (ins, locs, outs, rots);
3661 return;
3662
3663 err:
3664 as_bad ("Comma expected");
3665 ignore_rest_of_line ();
3666}
3667
3668static void
3669dot_rot (type)
3670 int type;
3671{
3672 unsigned num_regs, num_alloced = 0;
3673 struct dynreg **drpp, *dr;
3674 int ch, base_reg = 0;
3675 char *name, *start;
3676 size_t len;
3677
3678 switch (type)
3679 {
3680 case DYNREG_GR: base_reg = REG_GR + 32; break;
3681 case DYNREG_FR: base_reg = REG_FR + 32; break;
3682 case DYNREG_PR: base_reg = REG_P + 16; break;
3683 default: break;
3684 }
3685
542d6675 3686 /* First, remove existing names from hash table. */
800eeca4
JW		 3687 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3688 {
3689 hash_delete (md.dynreg_hash, dr->name);
3690 dr->num_regs = 0;
3691 }
3692
3693 drpp = &md.dynreg[type];
3694 while (1)
3695 {
3696 start = input_line_pointer;
3697 ch = get_symbol_end ();
3698 *input_line_pointer = ch;
3699 len = (input_line_pointer - start);
3700
3701 SKIP_WHITESPACE ();
3702 if (*input_line_pointer != '[')
3703 {
3704 as_bad ("Expected '['");
3705 goto err;
3706 }
3707 ++input_line_pointer; /* skip '[' */
3708
3709 num_regs = get_absolute_expression ();
3710
3711 if (*input_line_pointer++ != ']')
3712 {
3713 as_bad ("Expected ']'");
3714 goto err;
3715 }
3716 SKIP_WHITESPACE ();
3717
3718 num_alloced += num_regs;
3719 switch (type)
3720 {
3721 case DYNREG_GR:
3722 if (num_alloced > md.rot.num_regs)
3723 {
3724 as_bad ("Used more than the declared %d rotating registers",
3725 md.rot.num_regs);
3726 goto err;
3727 }
3728 break;
3729 case DYNREG_FR:
3730 if (num_alloced > 96)
3731 {
3732 as_bad ("Used more than the available 96 rotating registers");
3733 goto err;
3734 }
3735 break;
3736 case DYNREG_PR:
3737 if (num_alloced > 48)
3738 {
3739 as_bad ("Used more than the available 48 rotating registers");
3740 goto err;
3741 }
3742 break;
3743
3744 default:
3745 break;
3746 }
3747
3748 name = obstack_alloc (&notes, len + 1);
3749 memcpy (name, start, len);
3750 name[len] = '\0';
3751
3752 if (!*drpp)
3753 {
3754 *drpp = obstack_alloc (&notes, sizeof (*dr));
3755 memset (*drpp, 0, sizeof (*dr));
3756 }
3757
3758 dr = *drpp;
3759 dr->name = name;
3760 dr->num_regs = num_regs;
3761 dr->base = base_reg;
3762 drpp = &dr->next;
3763 base_reg += num_regs;
3764
3765 if (hash_insert (md.dynreg_hash, name, dr))
3766 {
3767 as_bad ("Attempt to redefine register set `%s'", name);
3768 goto err;
3769 }
3770
3771 if (*input_line_pointer != ',')
3772 break;
3773 ++input_line_pointer; /* skip comma */
3774 SKIP_WHITESPACE ();
3775 }
3776 demand_empty_rest_of_line ();
3777 return;
3778
3779 err:
3780 ignore_rest_of_line ();
3781}
3782
3783static void
3784dot_byteorder (byteorder)
3785 int byteorder;
3786{
3787 target_big_endian = byteorder;
3788}
3789
3790static void
3791dot_psr (dummy)
3792 int dummy;
3793{
3794 char *option;
3795 int ch;
3796
3797 while (1)
3798 {
3799 option = input_line_pointer;
3800 ch = get_symbol_end ();
3801 if (strcmp (option, "lsb") == 0)
3802 md.flags &= ~EF_IA_64_BE;
3803 else if (strcmp (option, "msb") == 0)
3804 md.flags |= EF_IA_64_BE;
3805 else if (strcmp (option, "abi32") == 0)
3806 md.flags &= ~EF_IA_64_ABI64;
3807 else if (strcmp (option, "abi64") == 0)
3808 md.flags |= EF_IA_64_ABI64;
3809 else
3810 as_bad ("Unknown psr option `%s'", option);
3811 *input_line_pointer = ch;
3812
3813 SKIP_WHITESPACE ();
3814 if (*input_line_pointer != ',')
3815 break;
3816
3817 ++input_line_pointer;
3818 SKIP_WHITESPACE ();
3819 }
3820 demand_empty_rest_of_line ();
3821}
3822
3823static void
3824dot_alias (dummy)
3825 int dummy;
3826{
3827 as_bad (".alias not implemented yet");
3828}
3829
3830static void
3831dot_ln (dummy)
3832 int dummy;
3833{
3834 new_logical_line (0, get_absolute_expression ());
3835 demand_empty_rest_of_line ();
3836}
3837
542d6675 3838static char *
800eeca4
JW		 3839parse_section_name ()
3840{
3841 char *name;
3842 int len;
3843
3844 SKIP_WHITESPACE ();
3845 if (*input_line_pointer != '"')
3846 {
3847 as_bad ("Missing section name");
3848 ignore_rest_of_line ();
3849 return 0;
3850 }
3851 name = demand_copy_C_string (&len);
3852 if (!name)
3853 {
3854 ignore_rest_of_line ();
3855 return 0;
3856 }
3857 SKIP_WHITESPACE ();
3858 if (*input_line_pointer != ',')
3859 {
3860 as_bad ("Comma expected after section name");
3861 ignore_rest_of_line ();
3862 return 0;
3863 }
3864 ++input_line_pointer; /* skip comma */
3865 return name;
3866}
3867
3868static void
3869dot_xdata (size)
3870 int size;
3871{
3872 char *name = parse_section_name ();
3873 if (!name)
3874 return;
3875
3876 set_section (name);
3877 cons (size);
3878 obj_elf_previous (0);
3879}
3880
3881/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
542d6675 3882
800eeca4
JW		 3883static void
3884stmt_float_cons (kind)
3885 int kind;
3886{
3887 size_t size;
3888
3889 switch (kind)
3890 {
3891 case 'd': size = 8; break;
3892 case 'x': size = 10; break;
3893
3894 case 'f':
3895 default:
3896 size = 4;
3897 break;
3898 }
3899 ia64_do_align (size);
3900 float_cons (kind);
3901}
3902
3903static void
3904stmt_cons_ua (size)
3905 int size;
3906{
3907 int saved_auto_align = md.auto_align;
3908
3909 md.auto_align = 0;
3910 cons (size);
3911 md.auto_align = saved_auto_align;
3912}
3913
3914static void
3915dot_xfloat_cons (kind)
3916 int kind;
3917{
3918 char *name = parse_section_name ();
3919 if (!name)
3920 return;
3921
3922 set_section (name);
3923 stmt_float_cons (kind);
3924 obj_elf_previous (0);
3925}
3926
3927static void
3928dot_xstringer (zero)
3929 int zero;
3930{
3931 char *name = parse_section_name ();
3932 if (!name)
3933 return;
3934
3935 set_section (name);
3936 stringer (zero);
3937 obj_elf_previous (0);
3938}
3939
3940static void
3941dot_xdata_ua (size)
3942 int size;
3943{
3944 int saved_auto_align = md.auto_align;
3945 char *name = parse_section_name ();
3946 if (!name)
3947 return;
3948
3949 set_section (name);
3950 md.auto_align = 0;
3951 cons (size);
3952 md.auto_align = saved_auto_align;
3953 obj_elf_previous (0);
3954}
3955
3956static void
3957dot_xfloat_cons_ua (kind)
3958 int kind;
3959{
3960 int saved_auto_align = md.auto_align;
3961 char *name = parse_section_name ();
3962 if (!name)
3963 return;
3964
3965 set_section (name);
3966 md.auto_align = 0;
3967 stmt_float_cons (kind);
3968 md.auto_align = saved_auto_align;
3969 obj_elf_previous (0);
3970}
3971
3972/* .reg.val <regname>,value */
542d6675 3973
800eeca4
JW		 3974static void
3975dot_reg_val (dummy)
542d6675 3976 int dummy;
800eeca4
JW		 3977{
3978 expressionS reg;
3979
3980 expression (&reg);
3981 if (reg.X_op != O_register)
3982 {
3983 as_bad (_("Register name expected"));
3984 ignore_rest_of_line ();
3985 }
3986 else if (*input_line_pointer++ != ',')
3987 {
3988 as_bad (_("Comma expected"));
3989 ignore_rest_of_line ();
3990 }
197865e8 3991 else
800eeca4
JW		 3992 {
3993 valueT value = get_absolute_expression ();
3994 int regno = reg.X_add_number;
542d6675
KH		 3995 if (regno < REG_GR || regno > REG_GR + 128)
3996 as_warn (_("Register value annotation ignored"));
800eeca4 3997 else
542d6675
KH		 3998 {
3999 gr_values[regno - REG_GR].known = 1;
4000 gr_values[regno - REG_GR].value = value;
4001 gr_values[regno - REG_GR].path = md.path;
4002 }
800eeca4
JW		 4003 }
4004 demand_empty_rest_of_line ();
4005}
4006
197865e8 4007/* select dv checking mode
800eeca4
JW		 4008 .auto
4009 .explicit
4010 .default
4011
197865e8 4012 A stop is inserted when changing modes
800eeca4 4013 */
542d6675 4014
800eeca4
JW		 4015static void
4016dot_dv_mode (type)
542d6675 4017 int type;
800eeca4
JW		 4018{
4019 if (md.manual_bundling)
4020 as_warn (_("Directive invalid within a bundle"));
4021
4022 if (type == 'E' || type == 'A')
4023 md.mode_explicitly_set = 0;
4024 else
4025 md.mode_explicitly_set = 1;
4026
4027 md.detect_dv = 1;
4028 switch (type)
4029 {
4030 case 'A':
4031 case 'a':
4032 if (md.explicit_mode)
542d6675 4033 insn_group_break (1, 0, 0);
800eeca4
JW		 4034 md.explicit_mode = 0;
4035 break;
4036 case 'E':
4037 case 'e':
4038 if (!md.explicit_mode)
542d6675 4039 insn_group_break (1, 0, 0);
800eeca4
JW		 4040 md.explicit_mode = 1;
4041 break;
4042 default:
4043 case 'd':
4044 if (md.explicit_mode != md.default_explicit_mode)
542d6675 4045 insn_group_break (1, 0, 0);
800eeca4
JW		 4046 md.explicit_mode = md.default_explicit_mode;
4047 md.mode_explicitly_set = 0;
4048 break;
4049 }
4050}
4051
4052static void
4053print_prmask (mask)
542d6675 4054 valueT mask;
800eeca4
JW		 4055{
4056 int regno;
4057 char *comma = "";
542d6675 4058 for (regno = 0; regno < 64; regno++)
800eeca4 4059 {
542d6675
KH		 4060 if (mask & ((valueT) 1 << regno))
4061 {
4062 fprintf (stderr, "%s p%d", comma, regno);
4063 comma = ",";
4064 }
800eeca4
JW		 4065 }
4066}
4067
4068/*
4069 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4070 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4071 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4072 .pred.safe_across_calls p1 [, p2 [,...]]
4073 */
542d6675 4074
800eeca4
JW		 4075static void
4076dot_pred_rel (type)
542d6675 4077 int type;
800eeca4
JW		 4078{
4079 valueT mask = 0;
4080 int count = 0;
4081 int p1 = -1, p2 = -1;
4082
4083 if (type == 0)
4084 {
4085 if (*input_line_pointer != '"')
542d6675
KH		 4086 {
4087 as_bad (_("Missing predicate relation type"));
4088 ignore_rest_of_line ();
4089 return;
4090 }
197865e8 4091 else
542d6675
KH		 4092 {
4093 int len;
4094 char *form = demand_copy_C_string (&len);
4095 if (strcmp (form, "mutex") == 0)
4096 type = 'm';
4097 else if (strcmp (form, "clear") == 0)
4098 type = 'c';
4099 else if (strcmp (form, "imply") == 0)
4100 type = 'i';
4101 else
4102 {
4103 as_bad (_("Unrecognized predicate relation type"));
4104 ignore_rest_of_line ();
4105 return;
4106 }
4107 }
800eeca4 4108 if (*input_line_pointer == ',')
542d6675 4109 ++input_line_pointer;
800eeca4
JW		 4110 SKIP_WHITESPACE ();
4111 }
4112
4113 SKIP_WHITESPACE ();
4114 while (1)
4115 {
4116 valueT bit = 1;
4117 int regno;
197865e8 4118
800eeca4 4119 if (toupper (*input_line_pointer) != 'P'
542d6675
KH		 4120 || (regno = atoi (++input_line_pointer)) < 0
4121 || regno > 63)
4122 {
4123 as_bad (_("Predicate register expected"));
4124 ignore_rest_of_line ();
4125 return;
4126 }
800eeca4 4127 while (isdigit (*input_line_pointer))
542d6675 4128 ++input_line_pointer;
800eeca4 4129 if (p1 == -1)
542d6675 4130 p1 = regno;
800eeca4 4131 else if (p2 == -1)
542d6675 4132 p2 = regno;
800eeca4
JW		 4133 bit <<= regno;
4134 if (mask & bit)
542d6675
KH		 4135 as_warn (_("Duplicate predicate register ignored"));
4136 mask |= bit;
4137 count++;
4138 /* See if it's a range. */
800eeca4 4139 if (*input_line_pointer == '-')
542d6675
KH		 4140 {
4141 valueT stop = 1;
4142 ++input_line_pointer;
4143
4144 if (toupper (*input_line_pointer) != 'P'
4145 || (regno = atoi (++input_line_pointer)) < 0
4146 || regno > 63)
4147 {
4148 as_bad (_("Predicate register expected"));
4149 ignore_rest_of_line ();
4150 return;
4151 }
4152 while (isdigit (*input_line_pointer))
4153 ++input_line_pointer;
4154 stop <<= regno;
4155 if (bit >= stop)
4156 {
4157 as_bad (_("Bad register range"));
4158 ignore_rest_of_line ();
4159 return;
4160 }
4161 while (bit < stop)
4162 {
4163 bit <<= 1;
4164 mask |= bit;
4165 count++;
4166 }
4167 SKIP_WHITESPACE ();
4168 }
800eeca4 4169 if (*input_line_pointer != ',')
542d6675 4170 break;
800eeca4
JW		 4171 ++input_line_pointer;
4172 SKIP_WHITESPACE ();
4173 }
4174
4175 switch (type)
4176 {
4177 case 'c':
4178 if (count == 0)
542d6675 4179 mask = ~(valueT) 0;
800eeca4 4180 clear_qp_mutex (mask);
197865e8 4181 clear_qp_implies (mask, (valueT) 0);
800eeca4
JW		 4182 break;
4183 case 'i':
4184 if (count != 2 || p1 == -1 || p2 == -1)
542d6675 4185 as_bad (_("Predicate source and target required"));
800eeca4 4186 else if (p1 == 0 || p2 == 0)
542d6675 4187 as_bad (_("Use of p0 is not valid in this context"));
800eeca4 4188 else
542d6675 4189 add_qp_imply (p1, p2);
800eeca4
JW		 4190 break;
4191 case 'm':
4192 if (count < 2)
542d6675
KH		 4193 {
4194 as_bad (_("At least two PR arguments expected"));
4195 break;
4196 }
800eeca4 4197 else if (mask & 1)
542d6675
KH		 4198 {
4199 as_bad (_("Use of p0 is not valid in this context"));
4200 break;
4201 }
800eeca4
JW		 4202 add_qp_mutex (mask);
4203 break;
4204 case 's':
4205 /* note that we don't override any existing relations */
4206 if (count == 0)
542d6675
KH		 4207 {
4208 as_bad (_("At least one PR argument expected"));
4209 break;
4210 }
800eeca4 4211 if (md.debug_dv)
542d6675
KH		 4212 {
4213 fprintf (stderr, "Safe across calls: ");
4214 print_prmask (mask);
4215 fprintf (stderr, "\n");
4216 }
800eeca4
JW		 4217 qp_safe_across_calls = mask;
4218 break;
4219 }
4220 demand_empty_rest_of_line ();
4221}
4222
4223/* .entry label [, label [, ...]]
4224 Hint to DV code that the given labels are to be considered entry points.
542d6675
KH		 4225 Otherwise, only global labels are considered entry points. */
4226
800eeca4
JW		 4227static void
4228dot_entry (dummy)
542d6675 4229 int dummy;
800eeca4
JW		 4230{
4231 const char *err;
4232 char *name;
4233 int c;
4234 symbolS *symbolP;
4235
4236 do
4237 {
4238 name = input_line_pointer;
4239 c = get_symbol_end ();
4240 symbolP = symbol_find_or_make (name);
4241
4242 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4243 if (err)
542d6675
KH		 4244 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4245 name, err);
800eeca4
JW		 4246
4247 *input_line_pointer = c;
4248 SKIP_WHITESPACE ();
4249 c = *input_line_pointer;
4250 if (c == ',')
4251 {
4252 input_line_pointer++;
4253 SKIP_WHITESPACE ();
4254 if (*input_line_pointer == '\n')
4255 c = '\n';
4256 }
4257 }
4258 while (c == ',');
4259
4260 demand_empty_rest_of_line ();
4261}
4262
197865e8 4263/* .mem.offset offset, base
542d6675
KH		 4264 "base" is used to distinguish between offsets from a different base. */
4265
800eeca4
JW		 4266static void
4267dot_mem_offset (dummy)
4268 int dummy;
4269{
4270 md.mem_offset.hint = 1;
4271 md.mem_offset.offset = get_absolute_expression ();
4272 if (*input_line_pointer != ',')
4273 {
4274 as_bad (_("Comma expected"));
4275 ignore_rest_of_line ();
4276 return;
4277 }
4278 ++input_line_pointer;
4279 md.mem_offset.base = get_absolute_expression ();
4280 demand_empty_rest_of_line ();
4281}
4282
542d6675 4283/* ia64-specific pseudo-ops: */
800eeca4
JW		 4284const pseudo_typeS md_pseudo_table[] =
4285 {
4286 { "radix", dot_radix, 0 },
4287 { "lcomm", s_lcomm_bytes, 1 },
4288 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4289 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4290 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4291 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4292 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4293 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4294 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4295 { "proc", dot_proc, 0 },
4296 { "body", dot_body, 0 },
4297 { "prologue", dot_prologue, 0 },
4298 { "endp", dot_endp },
4299 { "file", dwarf2_directive_file },
4300 { "loc", dwarf2_directive_loc },
4301
4302 { "fframe", dot_fframe },
4303 { "vframe", dot_vframe },
e0c9811a
JW		 4304 { "vframesp", dot_vframesp },
4305 { "vframepsp", dot_vframepsp },
800eeca4
JW		 4306 { "save", dot_save },
4307 { "restore", dot_restore },
e0c9811a
JW		 4308 { "restorereg", dot_restorereg },
4309 { "restorereg.p", dot_restorereg_p },
800eeca4
JW		 4310 { "handlerdata", dot_handlerdata },
4311 { "unwentry", dot_unwentry },
e0c9811a
JW		 4312 { "altrp", dot_altrp },
4313 { "savesp", dot_savemem, 0 },
4314 { "savepsp", dot_savemem, 1 },
800eeca4
JW		 4315 { "save.g", dot_saveg },
4316 { "save.f", dot_savef },
4317 { "save.b", dot_saveb },
4318 { "save.gf", dot_savegf },
4319 { "spill", dot_spill },
e0c9811a
JW		 4320 { "spillreg", dot_spillreg },
4321 { "spillsp", dot_spillmem, 0 },
4322 { "spillpsp", dot_spillmem, 1 },
4323 { "spillreg.p", dot_spillreg_p },
4324 { "spillsp.p", dot_spillmem_p, 0 },
4325 { "spillpsp.p", dot_spillmem_p, 1 },
197865e8
KH		 4326 { "label_state", dot_label_state },
4327 { "copy_state", dot_copy_state },
800eeca4
JW		 4328 { "unwabi", dot_unwabi },
4329 { "personality", dot_personality },
4330#if 0
4331 { "estate", dot_estate },
4332#endif
4333 { "mii", dot_template, 0x0 },
4334 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4335 { "mlx", dot_template, 0x2 },
4336 { "mmi", dot_template, 0x4 },
4337 { "mfi", dot_template, 0x6 },
4338 { "mmf", dot_template, 0x7 },
4339 { "mib", dot_template, 0x8 },
4340 { "mbb", dot_template, 0x9 },
4341 { "bbb", dot_template, 0xb },
4342 { "mmb", dot_template, 0xc },
4343 { "mfb", dot_template, 0xe },
4344#if 0
4345 { "lb", dot_scope, 0 },
4346 { "le", dot_scope, 1 },
4347#endif
4348 { "align", s_align_bytes, 0 },
4349 { "regstk", dot_regstk, 0 },
4350 { "rotr", dot_rot, DYNREG_GR },
4351 { "rotf", dot_rot, DYNREG_FR },
4352 { "rotp", dot_rot, DYNREG_PR },
4353 { "lsb", dot_byteorder, 0 },
4354 { "msb", dot_byteorder, 1 },
4355 { "psr", dot_psr, 0 },
4356 { "alias", dot_alias, 0 },
4357 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4358
4359 { "xdata1", dot_xdata, 1 },
4360 { "xdata2", dot_xdata, 2 },
4361 { "xdata4", dot_xdata, 4 },
4362 { "xdata8", dot_xdata, 8 },
4363 { "xreal4", dot_xfloat_cons, 'f' },
4364 { "xreal8", dot_xfloat_cons, 'd' },
4365 { "xreal10", dot_xfloat_cons, 'x' },
4366 { "xstring", dot_xstringer, 0 },
4367 { "xstringz", dot_xstringer, 1 },
4368
542d6675 4369 /* unaligned versions: */
800eeca4
JW		 4370 { "xdata2.ua", dot_xdata_ua, 2 },
4371 { "xdata4.ua", dot_xdata_ua, 4 },
4372 { "xdata8.ua", dot_xdata_ua, 8 },
4373 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4374 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4375 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4376
4377 /* annotations/DV checking support */
4378 { "entry", dot_entry, 0 },
4379 { "mem.offset", dot_mem_offset },
4380 { "pred.rel", dot_pred_rel, 0 },
4381 { "pred.rel.clear", dot_pred_rel, 'c' },
4382 { "pred.rel.imply", dot_pred_rel, 'i' },
4383 { "pred.rel.mutex", dot_pred_rel, 'm' },
4384 { "pred.safe_across_calls", dot_pred_rel, 's' },
4385 { "reg.val", dot_reg_val },
4386 { "auto", dot_dv_mode, 'a' },
4387 { "explicit", dot_dv_mode, 'e' },
4388 { "default", dot_dv_mode, 'd' },
4389
4390 { NULL, 0, 0 }
4391 };
4392
4393static const struct pseudo_opcode
4394 {
4395 const char *name;
4396 void (*handler) (int);
4397 int arg;
4398 }
4399pseudo_opcode[] =
4400 {
4401 /* these are more like pseudo-ops, but don't start with a dot */
4402 { "data1", cons, 1 },
4403 { "data2", cons, 2 },
4404 { "data4", cons, 4 },
4405 { "data8", cons, 8 },
4406 { "real4", stmt_float_cons, 'f' },
4407 { "real8", stmt_float_cons, 'd' },
4408 { "real10", stmt_float_cons, 'x' },
4409 { "string", stringer, 0 },
4410 { "stringz", stringer, 1 },
4411
542d6675 4412 /* unaligned versions: */
800eeca4
JW		 4413 { "data2.ua", stmt_cons_ua, 2 },
4414 { "data4.ua", stmt_cons_ua, 4 },
4415 { "data8.ua", stmt_cons_ua, 8 },
4416 { "real4.ua", float_cons, 'f' },
4417 { "real8.ua", float_cons, 'd' },
4418 { "real10.ua", float_cons, 'x' },
4419 };
4420
4421/* Declare a register by creating a symbol for it and entering it in
4422 the symbol table. */
542d6675
KH		 4423
4424static symbolS *
800eeca4
JW		 4425declare_register (name, regnum)
4426 const char *name;
4427 int regnum;
4428{
4429 const char *err;
4430 symbolS *sym;
4431
4432 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4433
4434 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4435 if (err)
4436 as_fatal ("Inserting \"%s\" into register table failed: %s",
4437 name, err);
4438
4439 return sym;
4440}
4441
4442static void
4443declare_register_set (prefix, num_regs, base_regnum)
4444 const char *prefix;
4445 int num_regs;
4446 int base_regnum;
4447{
4448 char name[8];
4449 int i;
4450
4451 for (i = 0; i < num_regs; ++i)
4452 {
4453 sprintf (name, "%s%u", prefix, i);
4454 declare_register (name, base_regnum + i);
4455 }
4456}
4457
4458static unsigned int
4459operand_width (opnd)
4460 enum ia64_opnd opnd;
4461{
4462 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4463 unsigned int bits = 0;
4464 int i;
4465
4466 bits = 0;
4467 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4468 bits += odesc->field[i].bits;
4469
4470 return bits;
4471}
4472
4473static int
4474operand_match (idesc, index, e)
4475 const struct ia64_opcode *idesc;
4476 int index;
4477 expressionS *e;
4478{
4479 enum ia64_opnd opnd = idesc->operands[index];
4480 int bits, relocatable = 0;
4481 struct insn_fix *fix;
4482 bfd_signed_vma val;
4483
4484 switch (opnd)
4485 {
542d6675 4486 /* constants: */
800eeca4
JW		 4487
4488 case IA64_OPND_AR_CCV:
4489 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4490 return 1;
4491 break;
4492
4493 case IA64_OPND_AR_PFS:
4494 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4495 return 1;
4496 break;
4497
4498 case IA64_OPND_GR0:
4499 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4500 return 1;
4501 break;
4502
4503 case IA64_OPND_IP:
4504 if (e->X_op == O_register && e->X_add_number == REG_IP)
4505 return 1;
4506 break;
4507
4508 case IA64_OPND_PR:
4509 if (e->X_op == O_register && e->X_add_number == REG_PR)
4510 return 1;
4511 break;
4512
4513 case IA64_OPND_PR_ROT:
4514 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4515 return 1;
4516 break;
4517
4518 case IA64_OPND_PSR:
4519 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4520 return 1;
4521 break;
4522
4523 case IA64_OPND_PSR_L:
4524 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4525 return 1;
4526 break;
4527
4528 case IA64_OPND_PSR_UM:
4529 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4530 return 1;
4531 break;
4532
4533 case IA64_OPND_C1:
4534 if (e->X_op == O_constant && e->X_add_number == 1)
4535 return 1;
4536 break;
4537
4538 case IA64_OPND_C8:
4539 if (e->X_op == O_constant && e->X_add_number == 8)
4540 return 1;
4541 break;
4542
4543 case IA64_OPND_C16:
4544 if (e->X_op == O_constant && e->X_add_number == 16)
4545 return 1;
4546 break;
4547
542d6675 4548 /* register operands: */
800eeca4
JW		 4549
4550 case IA64_OPND_AR3:
4551 if (e->X_op == O_register && e->X_add_number >= REG_AR
4552 && e->X_add_number < REG_AR + 128)
4553 return 1;
4554 break;
4555
4556 case IA64_OPND_B1:
4557 case IA64_OPND_B2:
4558 if (e->X_op == O_register && e->X_add_number >= REG_BR
4559 && e->X_add_number < REG_BR + 8)
4560 return 1;
4561 break;
4562
4563 case IA64_OPND_CR3:
4564 if (e->X_op == O_register && e->X_add_number >= REG_CR
4565 && e->X_add_number < REG_CR + 128)
4566 return 1;
4567 break;
4568
4569 case IA64_OPND_F1:
4570 case IA64_OPND_F2:
4571 case IA64_OPND_F3:
4572 case IA64_OPND_F4:
4573 if (e->X_op == O_register && e->X_add_number >= REG_FR
4574 && e->X_add_number < REG_FR + 128)
4575 return 1;
4576 break;
4577
4578 case IA64_OPND_P1:
4579 case IA64_OPND_P2:
4580 if (e->X_op == O_register && e->X_add_number >= REG_P
4581 && e->X_add_number < REG_P + 64)
4582 return 1;
4583 break;
4584
4585 case IA64_OPND_R1:
4586 case IA64_OPND_R2:
4587 case IA64_OPND_R3:
4588 if (e->X_op == O_register && e->X_add_number >= REG_GR
4589 && e->X_add_number < REG_GR + 128)
4590 return 1;
4591 break;
4592
4593 case IA64_OPND_R3_2:
4594 if (e->X_op == O_register && e->X_add_number >= REG_GR
4595 && e->X_add_number < REG_GR + 4)
4596 return 1;
4597 break;
4598
542d6675 4599 /* indirect operands: */
800eeca4
JW		 4600 case IA64_OPND_CPUID_R3:
4601 case IA64_OPND_DBR_R3:
4602 case IA64_OPND_DTR_R3:
4603 case IA64_OPND_ITR_R3:
4604 case IA64_OPND_IBR_R3:
4605 case IA64_OPND_MSR_R3:
4606 case IA64_OPND_PKR_R3:
4607 case IA64_OPND_PMC_R3:
4608 case IA64_OPND_PMD_R3:
4609 case IA64_OPND_RR_R3:
4610 if (e->X_op == O_index && e->X_op_symbol
4611 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4612 == opnd - IA64_OPND_CPUID_R3))
4613 return 1;
4614 break;
4615
4616 case IA64_OPND_MR3:
4617 if (e->X_op == O_index && !e->X_op_symbol)
4618 return 1;
4619 break;
4620
542d6675 4621 /* immediate operands: */
800eeca4
JW		 4622 case IA64_OPND_CNT2a:
4623 case IA64_OPND_LEN4:
4624 case IA64_OPND_LEN6:
4625 bits = operand_width (idesc->operands[index]);
4626 if (e->X_op == O_constant
4627 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4628 return 1;
4629 break;
4630
4631 case IA64_OPND_CNT2b:
4632 if (e->X_op == O_constant
4633 && (bfd_vma) (e->X_add_number - 1) < 3)
4634 return 1;
4635 break;
4636
4637 case IA64_OPND_CNT2c:
4638 val = e->X_add_number;
4639 if (e->X_op == O_constant
4640 && (val == 0 || val == 7 || val == 15 || val == 16))
4641 return 1;
4642 break;
4643
4644 case IA64_OPND_SOR:
4645 /* SOR must be an integer multiple of 8 */
4646 if (e->X_add_number & 0x7)
4647 break;
4648 case IA64_OPND_SOF:
4649 case IA64_OPND_SOL:
4650 if (e->X_op == O_constant &&
4651 (bfd_vma) e->X_add_number <= 96)
4652 return 1;
4653 break;
4654
4655 case IA64_OPND_IMMU62:
4656 if (e->X_op == O_constant)
542d6675 4657 {
800eeca4 4658 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
542d6675
KH		 4659 return 1;
4660 }
197865e8 4661 else
542d6675
KH		 4662 {
4663 /* FIXME -- need 62-bit relocation type */
4664 as_bad (_("62-bit relocation not yet implemented"));
4665 }
800eeca4
JW		 4666 break;
4667
4668 case IA64_OPND_IMMU64:
4669 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4670 || e->X_op == O_subtract)
4671 {
4672 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4673 fix->code = BFD_RELOC_IA64_IMM64;
4674 if (e->X_op != O_subtract)
4675 {
4676 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4677 if (e->X_op == O_pseudo_fixup)
4678 e->X_op = O_symbol;
4679 }
4680
4681 fix->opnd = idesc->operands[index];
4682 fix->expr = *e;
4683 fix->is_pcrel = 0;
4684 ++CURR_SLOT.num_fixups;
4685 return 1;
4686 }
4687 else if (e->X_op == O_constant)
4688 return 1;
4689 break;
4690
4691 case IA64_OPND_CCNT5:
4692 case IA64_OPND_CNT5:
4693 case IA64_OPND_CNT6:
4694 case IA64_OPND_CPOS6a:
4695 case IA64_OPND_CPOS6b:
4696 case IA64_OPND_CPOS6c:
4697 case IA64_OPND_IMMU2:
4698 case IA64_OPND_IMMU7a:
4699 case IA64_OPND_IMMU7b:
800eeca4
JW		 4700 case IA64_OPND_IMMU21:
4701 case IA64_OPND_IMMU24:
4702 case IA64_OPND_MBTYPE4:
4703 case IA64_OPND_MHTYPE8:
4704 case IA64_OPND_POS6:
4705 bits = operand_width (idesc->operands[index]);
4706 if (e->X_op == O_constant
4707 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4708 return 1;
4709 break;
4710
bf3ca999
TW		 4711 case IA64_OPND_IMMU9:
4712 bits = operand_width (idesc->operands[index]);
4713 if (e->X_op == O_constant
4714 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
542d6675
KH		 4715 {
4716 int lobits = e->X_add_number & 0x3;
4717 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
4718 e->X_add_number |= (bfd_vma) 0x3;
4719 return 1;
4720 }
bf3ca999
TW		 4721 break;
4722
800eeca4
JW		 4723 case IA64_OPND_IMM44:
4724 /* least 16 bits must be zero */
4725 if ((e->X_add_number & 0xffff) != 0)
542d6675 4726 as_warn (_("lower 16 bits of mask ignored"));
800eeca4
JW		 4727
4728 if (e->X_op == O_constant
4729 && ((e->X_add_number >= 0
4730 && e->X_add_number < ((bfd_vma) 1 << 44))
4731 || (e->X_add_number < 0
4732 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
542d6675
KH		 4733 {
4734 /* sign-extend */
4735 if (e->X_add_number >= 0
4736 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4737 {
4738 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4739 }
4740 return 1;
4741 }
800eeca4
JW		 4742 break;
4743
4744 case IA64_OPND_IMM17:
4745 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4746 if (e->X_op == O_constant
4747 && ((e->X_add_number >= 0
4748 && e->X_add_number < ((bfd_vma) 1 << 17))
4749 || (e->X_add_number < 0
4750 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
542d6675
KH		 4751 {
4752 /* sign-extend */
4753 if (e->X_add_number >= 0
4754 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4755 {
4756 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
4757 }
4758 return 1;
4759 }
800eeca4
JW		 4760 break;
4761
4762 case IA64_OPND_IMM14:
4763 case IA64_OPND_IMM22:
4764 relocatable = 1;
4765 case IA64_OPND_IMM1:
4766 case IA64_OPND_IMM8:
4767 case IA64_OPND_IMM8U4:
4768 case IA64_OPND_IMM8M1:
4769 case IA64_OPND_IMM8M1U4:
4770 case IA64_OPND_IMM8M1U8:
4771 case IA64_OPND_IMM9a:
4772 case IA64_OPND_IMM9b:
4773 bits = operand_width (idesc->operands[index]);
4774 if (relocatable && (e->X_op == O_symbol
4775 || e->X_op == O_subtract
4776 || e->X_op == O_pseudo_fixup))
4777 {
4778 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4779
4780 if (idesc->operands[index] == IA64_OPND_IMM14)
4781 fix->code = BFD_RELOC_IA64_IMM14;
4782 else
4783 fix->code = BFD_RELOC_IA64_IMM22;
4784
4785 if (e->X_op != O_subtract)
4786 {
4787 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4788 if (e->X_op == O_pseudo_fixup)
4789 e->X_op = O_symbol;
4790 }
4791
4792 fix->opnd = idesc->operands[index];
4793 fix->expr = *e;
4794 fix->is_pcrel = 0;
4795 ++CURR_SLOT.num_fixups;
4796 return 1;
4797 }
4798 else if (e->X_op != O_constant
4799 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4800 return 0;
4801
4802 if (opnd == IA64_OPND_IMM8M1U4)
4803 {
4804 /* Zero is not valid for unsigned compares that take an adjusted
4805 constant immediate range. */
4806 if (e->X_add_number == 0)
4807 return 0;
4808
4809 /* Sign-extend 32-bit unsigned numbers, so that the following range
4810 checks will work. */
4811 val = e->X_add_number;
197865e8
KH		 4812 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4813 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 4814 val = ((val << 32) >> 32);
4815
4816 /* Check for 0x100000000. This is valid because
4817 0x100000000-1 is the same as ((uint32_t) -1). */
4818 if (val == ((bfd_signed_vma) 1 << 32))
4819 return 1;
4820
4821 val = val - 1;
4822 }
4823 else if (opnd == IA64_OPND_IMM8M1U8)
4824 {
4825 /* Zero is not valid for unsigned compares that take an adjusted
4826 constant immediate range. */
4827 if (e->X_add_number == 0)
4828 return 0;
4829
4830 /* Check for 0x10000000000000000. */
4831 if (e->X_op == O_big)
4832 {
4833 if (generic_bignum[0] == 0
4834 && generic_bignum[1] == 0
4835 && generic_bignum[2] == 0
4836 && generic_bignum[3] == 0
4837 && generic_bignum[4] == 1)
4838 return 1;
4839 else
4840 return 0;
4841 }
4842 else
4843 val = e->X_add_number - 1;
4844 }
4845 else if (opnd == IA64_OPND_IMM8M1)
4846 val = e->X_add_number - 1;
4847 else if (opnd == IA64_OPND_IMM8U4)
4848 {
4849 /* Sign-extend 32-bit unsigned numbers, so that the following range
4850 checks will work. */
4851 val = e->X_add_number;
197865e8
KH		 4852 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4853 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 4854 val = ((val << 32) >> 32);
4855 }
4856 else
4857 val = e->X_add_number;
4858
4859 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
4860 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
4861 return 1;
4862 break;
4863
4864 case IA64_OPND_INC3:
4865 /* +/- 1, 4, 8, 16 */
4866 val = e->X_add_number;
4867 if (val < 0)
4868 val = -val;
4869 if (e->X_op == O_constant
4870 && (val == 1 || val == 4 || val == 8 || val == 16))
4871 return 1;
4872 break;
4873
4874 case IA64_OPND_TGT25:
4875 case IA64_OPND_TGT25b:
4876 case IA64_OPND_TGT25c:
4877 case IA64_OPND_TGT64:
4878 if (e->X_op == O_symbol)
4879 {
4880 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4881 if (opnd == IA64_OPND_TGT25)
4882 fix->code = BFD_RELOC_IA64_PCREL21F;
4883 else if (opnd == IA64_OPND_TGT25b)
4884 fix->code = BFD_RELOC_IA64_PCREL21M;
4885 else if (opnd == IA64_OPND_TGT25c)
4886 fix->code = BFD_RELOC_IA64_PCREL21B;
542d6675 4887 else if (opnd == IA64_OPND_TGT64)
c67e42c9
RH		 4888 fix->code = BFD_RELOC_IA64_PCREL60B;
4889 else
4890 abort ();
4891
800eeca4
JW		 4892 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4893 fix->opnd = idesc->operands[index];
4894 fix->expr = *e;
4895 fix->is_pcrel = 1;
4896 ++CURR_SLOT.num_fixups;
4897 return 1;
4898 }
4899 case IA64_OPND_TAG13:
4900 case IA64_OPND_TAG13b:
4901 switch (e->X_op)
4902 {
4903 case O_constant:
4904 return 1;
4905
4906 case O_symbol:
4907 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4908 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4909 fix->opnd = idesc->operands[index];
4910 fix->expr = *e;
4911 fix->is_pcrel = 1;
4912 ++CURR_SLOT.num_fixups;
4913 return 1;
4914
4915 default:
4916 break;
4917 }
4918 break;
4919
4920 default:
4921 break;
4922 }
4923 return 0;
4924}
4925
4926static int
4927parse_operand (e)
4928 expressionS *e;
4929{
4930 int sep = '\0';
4931
4932 memset (e, 0, sizeof (*e));
4933 e->X_op = O_absent;
4934 SKIP_WHITESPACE ();
4935 if (*input_line_pointer != '}')
4936 expression (e);
4937 sep = *input_line_pointer++;
4938
4939 if (sep == '}')
4940 {
4941 if (!md.manual_bundling)
4942 as_warn ("Found '}' when manual bundling is off");
4943 else
4944 CURR_SLOT.manual_bundling_off = 1;
4945 md.manual_bundling = 0;
4946 sep = '\0';
4947 }
4948 return sep;
4949}
4950
4951/* Returns the next entry in the opcode table that matches the one in
4952 IDESC, and frees the entry in IDESC. If no matching entry is
197865e8 4953 found, NULL is returned instead. */
800eeca4
JW		 4954
4955static struct ia64_opcode *
4956get_next_opcode (struct ia64_opcode *idesc)
4957{
4958 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
4959 ia64_free_opcode (idesc);
4960 return next;
4961}
4962
4963/* Parse the operands for the opcode and find the opcode variant that
4964 matches the specified operands, or NULL if no match is possible. */
542d6675
KH		 4965
4966static struct ia64_opcode *
800eeca4
JW		 4967parse_operands (idesc)
4968 struct ia64_opcode *idesc;
4969{
4970 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
4971 int sep = 0;
4972 enum ia64_opnd expected_operand = IA64_OPND_NIL;
4973 char mnemonic[129];
4974 char *first_arg = 0, *end, *saved_input_pointer;
4975 unsigned int sof;
4976
4977 assert (strlen (idesc->name) <= 128);
4978
4979 strcpy (mnemonic, idesc->name);
4980 if (idesc->operands[2] == IA64_OPND_SOF)
4981 {
4982 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4983 can't parse the first operand until we have parsed the
4984 remaining operands of the "alloc" instruction. */
4985 SKIP_WHITESPACE ();
4986 first_arg = input_line_pointer;
4987 end = strchr (input_line_pointer, '=');
4988 if (!end)
4989 {
4990 as_bad ("Expected separator `='");
4991 return 0;
4992 }
4993 input_line_pointer = end + 1;
4994 ++i;
4995 ++num_outputs;
4996 }
4997
4998 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
4999 {
5000 sep = parse_operand (CURR_SLOT.opnd + i);
5001 if (CURR_SLOT.opnd[i].X_op == O_absent)
5002 break;
5003
5004 ++num_operands;
5005
5006 if (sep != '=' && sep != ',')
5007 break;
5008
5009 if (sep == '=')
5010 {
5011 if (num_outputs > 0)
5012 as_bad ("Duplicate equal sign (=) in instruction");
5013 else
5014 num_outputs = i + 1;
5015 }
5016 }
5017 if (sep != '\0')
5018 {
5019 as_bad ("Illegal operand separator `%c'", sep);
5020 return 0;
5021 }
197865e8 5022
800eeca4
JW		 5023 if (idesc->operands[2] == IA64_OPND_SOF)
5024 {
5025 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5026 know (strcmp (idesc->name, "alloc") == 0);
5027 if (num_operands == 5 /* first_arg not included in this count! */
5028 && CURR_SLOT.opnd[2].X_op == O_constant
5029 && CURR_SLOT.opnd[3].X_op == O_constant
5030 && CURR_SLOT.opnd[4].X_op == O_constant
5031 && CURR_SLOT.opnd[5].X_op == O_constant)
5032 {
5033 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5034 CURR_SLOT.opnd[3].X_add_number,
5035 CURR_SLOT.opnd[4].X_add_number,
5036 CURR_SLOT.opnd[5].X_add_number);
5037
542d6675 5038 /* now we can parse the first arg: */
800eeca4
JW		 5039 saved_input_pointer = input_line_pointer;
5040 input_line_pointer = first_arg;
5041 sep = parse_operand (CURR_SLOT.opnd + 0);
5042 if (sep != '=')
5043 --num_outputs; /* force error */
5044 input_line_pointer = saved_input_pointer;
5045
5046 CURR_SLOT.opnd[2].X_add_number = sof;
5047 CURR_SLOT.opnd[3].X_add_number
5048 = sof - CURR_SLOT.opnd[4].X_add_number;
5049 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5050 }
5051 }
5052
5053 highest_unmatched_operand = 0;
5054 expected_operand = idesc->operands[0];
5055 for (; idesc; idesc = get_next_opcode (idesc))
5056 {
5057 if (num_outputs != idesc->num_outputs)
5058 continue; /* mismatch in # of outputs */
5059
5060 CURR_SLOT.num_fixups = 0;
5061 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5062 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
5063 break;
5064
5065 if (i != num_operands)
5066 {
5067 if (i > highest_unmatched_operand)
5068 {
5069 highest_unmatched_operand = i;
5070 expected_operand = idesc->operands[i];
5071 }
5072 continue;
5073 }
5074
5075 if (num_operands < NELEMS (idesc->operands)
5076 && idesc->operands[num_operands])
5077 continue; /* mismatch in number of arguments */
5078
5079 break;
5080 }
5081 if (!idesc)
5082 {
5083 if (expected_operand)
5084 as_bad ("Operand %u of `%s' should be %s",
5085 highest_unmatched_operand + 1, mnemonic,
5086 elf64_ia64_operands[expected_operand].desc);
5087 else
5088 as_bad ("Operand mismatch");
5089 return 0;
5090 }
5091 return idesc;
5092}
5093
5094static void
5095build_insn (slot, insnp)
5096 struct slot *slot;
5097 bfd_vma *insnp;
5098{
5099 const struct ia64_operand *odesc, *o2desc;
5100 struct ia64_opcode *idesc = slot->idesc;
5101 bfd_signed_vma insn, val;
5102 const char *err;
5103 int i;
5104
5105 insn = idesc->opcode | slot->qp_regno;
5106
5107 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5108 {
c67e42c9
RH		 5109 if (slot->opnd[i].X_op == O_register
5110 || slot->opnd[i].X_op == O_constant
5111 || slot->opnd[i].X_op == O_index)
5112 val = slot->opnd[i].X_add_number;
5113 else if (slot->opnd[i].X_op == O_big)
800eeca4 5114 {
c67e42c9
RH		 5115 /* This must be the value 0x10000000000000000. */
5116 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5117 val = 0;
5118 }
5119 else
5120 val = 0;
5121
5122 switch (idesc->operands[i])
5123 {
5124 case IA64_OPND_IMMU64:
800eeca4
JW		 5125 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5126 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5127 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5128 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH		 5129 continue;
5130
5131 case IA64_OPND_IMMU62:
542d6675
KH		 5132 val &= 0x3fffffffffffffffULL;
5133 if (val != slot->opnd[i].X_add_number)
5134 as_warn (_("Value truncated to 62 bits"));
5135 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5136 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 5137 continue;
800eeca4 5138
c67e42c9
RH		 5139 case IA64_OPND_TGT64:
5140 val >>= 4;
5141 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5142 insn |= ((((val >> 59) & 0x1) << 36)
5143 | (((val >> 0) & 0xfffff) << 13));
5144 continue;
800eeca4 5145
c67e42c9
RH		 5146 case IA64_OPND_AR3:
5147 val -= REG_AR;
5148 break;
5149
5150 case IA64_OPND_B1:
5151 case IA64_OPND_B2:
5152 val -= REG_BR;
5153 break;
5154
5155 case IA64_OPND_CR3:
5156 val -= REG_CR;
5157 break;
5158
5159 case IA64_OPND_F1:
5160 case IA64_OPND_F2:
5161 case IA64_OPND_F3:
5162 case IA64_OPND_F4:
5163 val -= REG_FR;
5164 break;
5165
5166 case IA64_OPND_P1:
5167 case IA64_OPND_P2:
5168 val -= REG_P;
5169 break;
5170
5171 case IA64_OPND_R1:
5172 case IA64_OPND_R2:
5173 case IA64_OPND_R3:
5174 case IA64_OPND_R3_2:
5175 case IA64_OPND_CPUID_R3:
5176 case IA64_OPND_DBR_R3:
5177 case IA64_OPND_DTR_R3:
5178 case IA64_OPND_ITR_R3:
5179 case IA64_OPND_IBR_R3:
5180 case IA64_OPND_MR3:
5181 case IA64_OPND_MSR_R3:
5182 case IA64_OPND_PKR_R3:
5183 case IA64_OPND_PMC_R3:
5184 case IA64_OPND_PMD_R3:
197865e8 5185 case IA64_OPND_RR_R3:
c67e42c9
RH		 5186 val -= REG_GR;
5187 break;
5188
5189 default:
5190 break;
5191 }
5192
5193 odesc = elf64_ia64_operands + idesc->operands[i];
5194 err = (*odesc->insert) (odesc, val, &insn);
5195 if (err)
5196 as_bad_where (slot->src_file, slot->src_line,
5197 "Bad operand value: %s", err);
5198 if (idesc->flags & IA64_OPCODE_PSEUDO)
5199 {
5200 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5201 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5202 {
5203 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5204 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5205 }
c67e42c9
RH		 5206 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5207 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5208 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5209 {
c67e42c9
RH		 5210 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5211 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW		 5212 }
5213 }
5214 }
5215 *insnp = insn;
5216}
5217
5218static void
5219emit_one_bundle ()
5220{
5221 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5222 unsigned int manual_bundling = 0;
5223 enum ia64_unit required_unit, insn_unit = 0;
5224 enum ia64_insn_type type[3], insn_type;
5225 unsigned int template, orig_template;
542d6675 5226 bfd_vma insn[3] = { -1, -1, -1 };
800eeca4
JW		 5227 struct ia64_opcode *idesc;
5228 int end_of_insn_group = 0, user_template = -1;
5229 int n, i, j, first, curr;
e0c9811a 5230 unw_rec_list *ptr, *prev;
800eeca4
JW		 5231 bfd_vma t0 = 0, t1 = 0;
5232 struct label_fix *lfix;
5233 struct insn_fix *ifix;
5234 char mnemonic[16];
5235 fixS *fix;
5236 char *f;
5237
5238 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5239 know (first >= 0 & first < NUM_SLOTS);
5240 n = MIN (3, md.num_slots_in_use);
5241
5242 /* Determine template: user user_template if specified, best match
542d6675 5243 otherwise: */
800eeca4
JW		 5244
5245 if (md.slot[first].user_template >= 0)
5246 user_template = template = md.slot[first].user_template;
5247 else
5248 {
032efc85 5249 /* Auto select appropriate template. */
800eeca4
JW		 5250 memset (type, 0, sizeof (type));
5251 curr = first;
5252 for (i = 0; i < n; ++i)
5253 {
032efc85
RH		 5254 if (md.slot[curr].label_fixups && i != 0)
5255 break;
800eeca4
JW		 5256 type[i] = md.slot[curr].idesc->type;
5257 curr = (curr + 1) % NUM_SLOTS;
5258 }
5259 template = best_template[type[0]][type[1]][type[2]];
5260 }
5261
542d6675 5262 /* initialize instructions with appropriate nops: */
800eeca4
JW		 5263 for (i = 0; i < 3; ++i)
5264 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5265
5266 f = frag_more (16);
5267
542d6675 5268 /* now fill in slots with as many insns as possible: */
800eeca4
JW		 5269 curr = first;
5270 idesc = md.slot[curr].idesc;
5271 end_of_insn_group = 0;
5272 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5273 {
e0c9811a
JW		 5274 /* Set the slot number for prologue/body records now as those
5275 refer to the current point, not the point after the
542d6675 5276 instruction has been issued: */
10850f29
JW		 5277 /* Don't try to delete prologue/body records here, as that will cause
5278 them to also be deleted from the master list of unwind records. */
e0c9811a 5279 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
10850f29
JW		 5280 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5281 || ptr->r.type == body)
5282 ptr->slot_number = (unsigned long) f + i;
e0c9811a 5283
800eeca4
JW		 5284 if (idesc->flags & IA64_OPCODE_SLOT2)
5285 {
5286 if (manual_bundling && i != 2)
5287 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5288 "`%s' must be last in bundle", idesc->name);
5289 else
5290 i = 2;
5291 }
5292 if (idesc->flags & IA64_OPCODE_LAST)
5293 {
5294 int required_slot, required_template;
5295
5296 /* If we need a stop bit after an M slot, our only choice is
5297 template 5 (M;;MI). If we need a stop bit after a B
5298 slot, our only choice is to place it at the end of the
5299 bundle, because the only available templates are MIB,
5300 MBB, BBB, MMB, and MFB. We don't handle anything other
5301 than M and B slots because these are the only kind of
5302 instructions that can have the IA64_OPCODE_LAST bit set. */
5303 required_template = template;
5304 switch (idesc->type)
5305 {
5306 case IA64_TYPE_M:
5307 required_slot = 0;
5308 required_template = 5;
5309 break;
5310
5311 case IA64_TYPE_B:
5312 required_slot = 2;
5313 break;
5314
5315 default:
5316 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5317 "Internal error: don't know how to force %s to end"
5318 "of instruction group", idesc->name);
5319 required_slot = i;
5320 break;
5321 }
5322 if (manual_bundling && i != required_slot)
5323 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5324 "`%s' must be last in instruction group",
5325 idesc->name);
5326 if (required_slot < i)
5327 /* Can't fit this instruction. */
5328 break;
5329
5330 i = required_slot;
5331 if (required_template != template)
5332 {
5333 /* If we switch the template, we need to reset the NOPs
5334 after slot i. The slot-types of the instructions ahead
5335 of i never change, so we don't need to worry about
5336 changing NOPs in front of this slot. */
5337 for (j = i; j < 3; ++j)
5338 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5339 }
5340 template = required_template;
5341 }
5342 if (curr != first && md.slot[curr].label_fixups)
5343 {
5344 if (manual_bundling_on)
5345 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5346 "Label must be first in a bundle");
5347 /* This insn must go into the first slot of a bundle. */
5348 break;
5349 }
5350
5351 manual_bundling_on = md.slot[curr].manual_bundling_on;
5352 manual_bundling_off = md.slot[curr].manual_bundling_off;
5353
5354 if (manual_bundling_on)
5355 {
5356 if (curr == first)
5357 manual_bundling = 1;
5358 else
5359 break; /* need to start a new bundle */
5360 }
5361
5362 if (end_of_insn_group && md.num_slots_in_use >= 1)
5363 {
5364 /* We need an instruction group boundary in the middle of a
5365 bundle. See if we can switch to an other template with
5366 an appropriate boundary. */
5367
5368 orig_template = template;
5369 if (i == 1 && (user_template == 4
5370 || (user_template < 0
5371 && (ia64_templ_desc[template].exec_unit[0]
5372 == IA64_UNIT_M))))
5373 {
5374 template = 5;
5375 end_of_insn_group = 0;
5376 }
5377 else if (i == 2 && (user_template == 0
5378 || (user_template < 0
5379 && (ia64_templ_desc[template].exec_unit[1]
5380 == IA64_UNIT_I)))
5381 /* This test makes sure we don't switch the template if
5382 the next instruction is one that needs to be first in
5383 an instruction group. Since all those instructions are
5384 in the M group, there is no way such an instruction can
5385 fit in this bundle even if we switch the template. The
5386 reason we have to check for this is that otherwise we
5387 may end up generating "MI;;I M.." which has the deadly
5388 effect that the second M instruction is no longer the
5389 first in the bundle! --davidm 99/12/16 */
5390 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5391 {
5392 template = 1;
5393 end_of_insn_group = 0;
5394 }
5395 else if (curr != first)
5396 /* can't fit this insn */
5397 break;
5398
5399 if (template != orig_template)
5400 /* if we switch the template, we need to reset the NOPs
5401 after slot i. The slot-types of the instructions ahead
5402 of i never change, so we don't need to worry about
5403 changing NOPs in front of this slot. */
5404 for (j = i; j < 3; ++j)
5405 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5406 }
5407 required_unit = ia64_templ_desc[template].exec_unit[i];
5408
542d6675 5409 /* resolve dynamic opcodes such as "break" and "nop": */
800eeca4
JW		 5410 if (idesc->type == IA64_TYPE_DYN)
5411 {
5412 if ((strcmp (idesc->name, "nop") == 0)
5413 || (strcmp (idesc->name, "break") == 0))
5414 insn_unit = required_unit;
5415 else if (strcmp (idesc->name, "chk.s") == 0)
5416 {
5417 insn_unit = IA64_UNIT_M;
5418 if (required_unit == IA64_UNIT_I)
5419 insn_unit = IA64_UNIT_I;
5420 }
5421 else
5422 as_fatal ("emit_one_bundle: unexpected dynamic op");
5423
5424 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
3d56ab85 5425 ia64_free_opcode (idesc);
800eeca4
JW		 5426 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5427#if 0
5428 know (!idesc->next); /* no resolved dynamic ops have collisions */
5429#endif
5430 }
5431 else
5432 {
5433 insn_type = idesc->type;
5434 insn_unit = IA64_UNIT_NIL;
5435 switch (insn_type)
5436 {
5437 case IA64_TYPE_A:
5438 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5439 insn_unit = required_unit;
5440 break;
542d6675 5441 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
800eeca4
JW		 5442 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5443 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5444 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5445 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5446 default: break;
5447 }
5448 }
5449
5450 if (insn_unit != required_unit)
5451 {
5452 if (required_unit == IA64_UNIT_L
542d6675 5453 && insn_unit == IA64_UNIT_I
800eeca4
JW		 5454 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5455 {
5456 /* we got ourselves an MLX template but the current
197865e8 5457 instruction isn't an X-unit, or an I-unit instruction
800eeca4
JW		 5458 that can go into the X slot of an MLX template. Duh. */
5459 if (md.num_slots_in_use >= NUM_SLOTS)
5460 {
5461 as_bad_where (md.slot[curr].src_file,
5462 md.slot[curr].src_line,
5463 "`%s' can't go in X slot of "
5464 "MLX template", idesc->name);
542d6675 5465 /* drop this insn so we don't livelock: */
800eeca4
JW		 5466 --md.num_slots_in_use;
5467 }
5468 break;
5469 }
5470 continue; /* try next slot */
5471 }
5472
5473 if (debug_type == DEBUG_DWARF2)
5474 {
5475 bfd_vma addr;
5476
542d6675 5477 addr = frag_now->fr_address + frag_now_fix () - 16 + 1 * i;
800eeca4
JW		 5478 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5479 }
5480
5481 build_insn (md.slot + curr, insn + i);
5482
10850f29
JW		 5483 /* Set slot counts for non prologue/body unwind records. */
5484 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5485 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5486 && ptr->r.type != body)
5487 ptr->slot_number = (unsigned long) f + i;
5488 md.slot[curr].unwind_record = NULL;
e0c9811a 5489 unwind.next_slot_number = (unsigned long) f + i + ((i == 2)?(0x10-2):1);
10850f29 5490
800eeca4
JW		 5491 if (required_unit == IA64_UNIT_L)
5492 {
5493 know (i == 1);
5494 /* skip one slot for long/X-unit instructions */
5495 ++i;
5496 }
5497 --md.num_slots_in_use;
5498
542d6675 5499 /* now is a good time to fix up the labels for this insn: */
800eeca4
JW		 5500 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5501 {
5502 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5503 symbol_set_frag (lfix->sym, frag_now);
5504 }
5505
5506 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5507 {
5508 ifix = md.slot[curr].fixup + j;
5509 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
5510 &ifix->expr, ifix->is_pcrel, ifix->code);
5511 fix->tc_fix_data.opnd = ifix->opnd;
5512 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5513 fix->fx_file = md.slot[curr].src_file;
5514 fix->fx_line = md.slot[curr].src_line;
5515 }
5516
5517 end_of_insn_group = md.slot[curr].end_of_insn_group;
5518
542d6675 5519 /* clear slot: */
800eeca4
JW		 5520 ia64_free_opcode (md.slot[curr].idesc);
5521 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5522 md.slot[curr].user_template = -1;
5523
5524 if (manual_bundling_off)
5525 {
5526 manual_bundling = 0;
5527 break;
5528 }
5529 curr = (curr + 1) % NUM_SLOTS;
5530 idesc = md.slot[curr].idesc;
5531 }
5532 if (manual_bundling)
5533 {
5534 if (md.num_slots_in_use > 0)
5535 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5536 "`%s' does not fit into %s template",
5537 idesc->name, ia64_templ_desc[template].name);
5538 else
5539 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5540 "Missing '}' at end of file");
5541 }
5542 know (md.num_slots_in_use < NUM_SLOTS);
5543
5544 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5545 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5546
5547 md_number_to_chars (f + 0, t0, 8);
5548 md_number_to_chars (f + 8, t1, 8);
5549}
5550
5551int
5552md_parse_option (c, arg)
5553 int c;
5554 char *arg;
5555{
800eeca4
JW		 5556 switch (c)
5557 {
c43c2cc5 5558 /* Switches from the Intel assembler. */
800eeca4
JW		 5559 case 'M':
5560 if (strcmp (arg, "ilp64") == 0
5561 || strcmp (arg, "lp64") == 0
5562 || strcmp (arg, "p64") == 0)
5563 {
5564 md.flags |= EF_IA_64_ABI64;
5565 }
5566 else if (strcmp (arg, "ilp32") == 0)
5567 {
5568 md.flags &= ~EF_IA_64_ABI64;
5569 }
5570 else if (strcmp (arg, "le") == 0)
5571 {
5572 md.flags &= ~EF_IA_64_BE;
5573 }
5574 else if (strcmp (arg, "be") == 0)
5575 {
5576 md.flags |= EF_IA_64_BE;
5577 }
5578 else
5579 return 0;
5580 break;
5581
5582 case 'N':
5583 if (strcmp (arg, "so") == 0)
5584 {
542d6675 5585 /* Suppress signon message. */
800eeca4
JW		 5586 }
5587 else if (strcmp (arg, "pi") == 0)
5588 {
5589 /* Reject privileged instructions. FIXME */
5590 }
5591 else if (strcmp (arg, "us") == 0)
5592 {
5593 /* Allow union of signed and unsigned range. FIXME */
5594 }
5595 else if (strcmp (arg, "close_fcalls") == 0)
5596 {
5597 /* Do not resolve global function calls. */
5598 }
5599 else
5600 return 0;
5601 break;
5602
5603 case 'C':
5604 /* temp[="prefix"] Insert temporary labels into the object file
5605 symbol table prefixed by "prefix".
5606 Default prefix is ":temp:".
5607 */
5608 break;
5609
5610 case 'a':
5611 /* ??? Conflicts with gas' listing option. */
5612 /* indirect=<tgt> Assume unannotated indirect branches behavior
5613 according to <tgt> --
5614 exit: branch out from the current context (default)
5615 labels: all labels in context may be branch targets
5616 */
5617 break;
5618
5619 case 'x':
5620 /* -X conflicts with an ignored option, use -x instead */
5621 md.detect_dv = 1;
5622 if (!arg || strcmp (arg, "explicit") == 0)
542d6675
KH		 5623 {
5624 /* set default mode to explicit */
5625 md.default_explicit_mode = 1;
5626 break;
5627 }
800eeca4 5628 else if (strcmp (arg, "auto") == 0)
542d6675
KH		 5629 {
5630 md.default_explicit_mode = 0;
5631 }
800eeca4 5632 else if (strcmp (arg, "debug") == 0)
542d6675
KH		 5633 {
5634 md.debug_dv = 1;
5635 }
800eeca4 5636 else if (strcmp (arg, "debugx") == 0)
542d6675
KH		 5637 {
5638 md.default_explicit_mode = 1;
5639 md.debug_dv = 1;
5640 }
800eeca4 5641 else
542d6675
KH		 5642 {
5643 as_bad (_("Unrecognized option '-x%s'"), arg);
5644 }
800eeca4
JW		 5645 break;
5646
5647 case 'S':
5648 /* nops Print nops statistics. */
5649 break;
5650
c43c2cc5
JW		 5651 /* GNU specific switches for gcc. */
5652 case OPTION_MCONSTANT_GP:
5653 md.flags |= EF_IA_64_CONS_GP;
5654 break;
5655
5656 case OPTION_MAUTO_PIC:
5657 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
5658 break;
5659
800eeca4
JW		 5660 default:
5661 return 0;
5662 }
5663
5664 return 1;
5665}
5666
5667void
5668md_show_usage (stream)
5669 FILE *stream;
5670{
542d6675 5671 fputs (_("\
800eeca4
JW		 5672IA-64 options:\n\
5673 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5674 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5675 -x | -xexplicit turn on dependency violation checking (default)\n\
5676 -xauto automagically remove dependency violations\n\
5677 -xdebug debug dependency violation checker\n"),
5678 stream);
5679}
5680
44576e1f
RH		 5681/* Return true if TYPE fits in TEMPL at SLOT. */
5682
5683static int
800eeca4
JW		 5684match (int templ, int type, int slot)
5685{
5686 enum ia64_unit unit;
5687 int result;
5688
5689 unit = ia64_templ_desc[templ].exec_unit[slot];
5690 switch (type)
5691 {
5692 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5693 case IA64_TYPE_A:
5694 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5695 break;
5696 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5697 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5698 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5699 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5700 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5701 default: result = 0; break;
5702 }
5703 return result;
5704}
5705
44576e1f
RH		 5706/* Add a bit of extra goodness if a nop of type F or B would fit
5707 in TEMPL at SLOT. */
5708
5709static inline int
5710extra_goodness (int templ, int slot)
5711{
5712 if (match (templ, IA64_TYPE_F, slot))
5713 return 2;
5714 if (match (templ, IA64_TYPE_B, slot))
5715 return 1;
5716 return 0;
5717}
5718
800eeca4
JW		 5719/* This function is called once, at assembler startup time. It sets
5720 up all the tables, etc. that the MD part of the assembler will need
5721 that can be determined before arguments are parsed. */
5722void
5723md_begin ()
5724{
5725 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
5726 const char *err;
5727 char name[8];
5728
5729 md.auto_align = 1;
5730 md.explicit_mode = md.default_explicit_mode;
5731
5732 bfd_set_section_alignment (stdoutput, text_section, 4);
5733
5734 target_big_endian = 0;
5735 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
542d6675
KH		 5736 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5737 &zero_address_frag);
800eeca4
JW		 5738
5739 pseudo_func[FUNC_GP_RELATIVE].u.sym =
542d6675
KH		 5740 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5741 &zero_address_frag);
800eeca4
JW		 5742
5743 pseudo_func[FUNC_LT_RELATIVE].u.sym =
542d6675
KH		 5744 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5745 &zero_address_frag);
800eeca4 5746
c67e42c9 5747 pseudo_func[FUNC_PC_RELATIVE].u.sym =
542d6675
KH		 5748 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5749 &zero_address_frag);
c67e42c9 5750
800eeca4 5751 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
542d6675
KH		 5752 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5753 &zero_address_frag);
800eeca4
JW		 5754
5755 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
542d6675
KH		 5756 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5757 &zero_address_frag);
800eeca4
JW		 5758
5759 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
542d6675
KH		 5760 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5761 &zero_address_frag);
800eeca4
JW		 5762
5763 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
542d6675
KH		 5764 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5765 &zero_address_frag);
800eeca4
JW		 5766
5767 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
542d6675
KH		 5768 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5769 &zero_address_frag);
800eeca4 5770
197865e8 5771 /* Compute the table of best templates. We compute goodness as a
44576e1f
RH		 5772 base 4 value, in which each match counts for 3, each F counts
5773 for 2, each B counts for 1. This should maximize the number of
5774 F and B nops in the chosen bundles, which is good because these
5775 pipelines are least likely to be overcommitted. */
800eeca4
JW		 5776 for (i = 0; i < IA64_NUM_TYPES; ++i)
5777 for (j = 0; j < IA64_NUM_TYPES; ++j)
5778 for (k = 0; k < IA64_NUM_TYPES; ++k)
5779 {
5780 best = 0;
5781 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
5782 {
5783 goodness = 0;
5784 if (match (t, i, 0))
5785 {
5786 if (match (t, j, 1))
5787 {
5788 if (match (t, k, 2))
44576e1f 5789 goodness = 3 + 3 + 3;
800eeca4 5790 else
44576e1f 5791 goodness = 3 + 3 + extra_goodness (t, 2);
800eeca4
JW		 5792 }
5793 else if (match (t, j, 2))
44576e1f 5794 goodness = 3 + 3 + extra_goodness (t, 1);
800eeca4 5795 else
44576e1f
RH		 5796 {
5797 goodness = 3;
5798 goodness += extra_goodness (t, 1);
5799 goodness += extra_goodness (t, 2);
5800 }
800eeca4
JW		 5801 }
5802 else if (match (t, i, 1))
5803 {
5804 if (match (t, j, 2))
44576e1f 5805 goodness = 3 + 3;
800eeca4 5806 else
44576e1f 5807 goodness = 3 + extra_goodness (t, 2);
800eeca4
JW		 5808 }
5809 else if (match (t, i, 2))
44576e1f 5810 goodness = 3 + extra_goodness (t, 1);
800eeca4
JW		 5811
5812 if (goodness > best)
5813 {
5814 best = goodness;
5815 best_template[i][j][k] = t;
5816 }
5817 }
5818 }
5819
5820 for (i = 0; i < NUM_SLOTS; ++i)
5821 md.slot[i].user_template = -1;
5822
5823 md.pseudo_hash = hash_new ();
5824 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
5825 {
5826 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
5827 (void *) (pseudo_opcode + i));
5828 if (err)
5829 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5830 pseudo_opcode[i].name, err);
5831 }
5832
5833 md.reg_hash = hash_new ();
5834 md.dynreg_hash = hash_new ();
5835 md.const_hash = hash_new ();
5836 md.entry_hash = hash_new ();
5837
542d6675 5838 /* general registers: */
800eeca4
JW		 5839
5840 total = 128;
5841 for (i = 0; i < total; ++i)
5842 {
5843 sprintf (name, "r%d", i - REG_GR);
5844 md.regsym[i] = declare_register (name, i);
5845 }
5846
542d6675 5847 /* floating point registers: */
800eeca4
JW		 5848 total += 128;
5849 for (; i < total; ++i)
5850 {
5851 sprintf (name, "f%d", i - REG_FR);
5852 md.regsym[i] = declare_register (name, i);
5853 }
5854
542d6675 5855 /* application registers: */
800eeca4
JW		 5856 total += 128;
5857 ar_base = i;
5858 for (; i < total; ++i)
5859 {
5860 sprintf (name, "ar%d", i - REG_AR);
5861 md.regsym[i] = declare_register (name, i);
5862 }
5863
542d6675 5864 /* control registers: */
800eeca4
JW		 5865 total += 128;
5866 cr_base = i;
5867 for (; i < total; ++i)
5868 {
5869 sprintf (name, "cr%d", i - REG_CR);
5870 md.regsym[i] = declare_register (name, i);
5871 }
5872
542d6675 5873 /* predicate registers: */
800eeca4
JW		 5874 total += 64;
5875 for (; i < total; ++i)
5876 {
5877 sprintf (name, "p%d", i - REG_P);
5878 md.regsym[i] = declare_register (name, i);
5879 }
5880
542d6675 5881 /* branch registers: */
800eeca4
JW		 5882 total += 8;
5883 for (; i < total; ++i)
5884 {
5885 sprintf (name, "b%d", i - REG_BR);
5886 md.regsym[i] = declare_register (name, i);
5887 }
5888
5889 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
5890 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
5891 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
5892 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
5893 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
5894 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
5895 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
5896
5897 for (i = 0; i < NELEMS (indirect_reg); ++i)
5898 {
5899 regnum = indirect_reg[i].regnum;
5900 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
5901 }
5902
542d6675 5903 /* define synonyms for application registers: */
800eeca4
JW		 5904 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
5905 md.regsym[i] = declare_register (ar[i - REG_AR].name,
5906 REG_AR + ar[i - REG_AR].regnum);
5907
542d6675 5908 /* define synonyms for control registers: */
800eeca4
JW		 5909 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
5910 md.regsym[i] = declare_register (cr[i - REG_CR].name,
5911 REG_CR + cr[i - REG_CR].regnum);
5912
5913 declare_register ("gp", REG_GR + 1);
5914 declare_register ("sp", REG_GR + 12);
5915 declare_register ("rp", REG_BR + 0);
5916
542d6675 5917 /* pseudo-registers used to specify unwind info: */
e0c9811a
JW		 5918 declare_register ("psp", REG_PSP);
5919
800eeca4
JW		 5920 declare_register_set ("ret", 4, REG_GR + 8);
5921 declare_register_set ("farg", 8, REG_FR + 8);
5922 declare_register_set ("fret", 8, REG_FR + 8);
5923
5924 for (i = 0; i < NELEMS (const_bits); ++i)
5925 {
5926 err = hash_insert (md.const_hash, const_bits[i].name,
5927 (PTR) (const_bits + i));
5928 if (err)
5929 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5930 name, err);
5931 }
5932
5933 /* Default to 64-bit mode. */
c43c2cc5
JW		 5934 /* ??? This overrides the -M options, but they aren't working anyways. */
5935 md.flags |= EF_IA_64_ABI64;
800eeca4
JW		 5936
5937 md.mem_offset.hint = 0;
5938 md.path = 0;
5939 md.maxpaths = 0;
5940 md.entry_labels = NULL;
5941}
5942
5943void
5944ia64_end_of_source ()
5945{
542d6675 5946 /* terminate insn group upon reaching end of file: */
800eeca4
JW		 5947 insn_group_break (1, 0, 0);
5948
542d6675 5949 /* emits slots we haven't written yet: */
800eeca4
JW		 5950 ia64_flush_insns ();
5951
5952 bfd_set_private_flags (stdoutput, md.flags);
5953
5954 if (debug_type == DEBUG_DWARF2)
5955 dwarf2_finish ();
5956
5957 md.mem_offset.hint = 0;
5958}
5959
5960void
5961ia64_start_line ()
5962{
5963 md.qp.X_op = O_absent;
5964
5965 if (ignore_input ())
5966 return;
5967
5968 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
5969 {
5970 if (md.detect_dv && !md.explicit_mode)
542d6675 5971 as_warn (_("Explicit stops are ignored in auto mode"));
800eeca4 5972 else
542d6675 5973 insn_group_break (1, 0, 0);
800eeca4
JW		 5974 }
5975}
5976
5977int
5978ia64_unrecognized_line (ch)
5979 int ch;
5980{
5981 switch (ch)
5982 {
5983 case '(':
5984 expression (&md.qp);
5985 if (*input_line_pointer++ != ')')
5986 {
5987 as_bad ("Expected ')'");
5988 return 0;
5989 }
5990 if (md.qp.X_op != O_register)
5991 {
5992 as_bad ("Qualifying predicate expected");
5993 return 0;
5994 }
5995 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
5996 {
5997 as_bad ("Predicate register expected");
5998 return 0;
5999 }
6000 return 1;
6001
6002 case '{':
6003 if (md.manual_bundling)
6004 as_warn ("Found '{' when manual bundling is already turned on");
6005 else
6006 CURR_SLOT.manual_bundling_on = 1;
6007 md.manual_bundling = 1;
6008
542d6675
KH		 6009 /* Bundling is only acceptable in explicit mode
6010 or when in default automatic mode. */
800eeca4 6011 if (md.detect_dv && !md.explicit_mode)
542d6675
KH		 6012 {
6013 if (!md.mode_explicitly_set
6014 && !md.default_explicit_mode)
6015 dot_dv_mode ('E');
6016 else
6017 as_warn (_("Found '{' after explicit switch to automatic mode"));
6018 }
800eeca4
JW		 6019 return 1;
6020
6021 case '}':
6022 if (!md.manual_bundling)
6023 as_warn ("Found '}' when manual bundling is off");
6024 else
6025 PREV_SLOT.manual_bundling_off = 1;
6026 md.manual_bundling = 0;
6027
6028 /* switch back to automatic mode, if applicable */
197865e8 6029 if (md.detect_dv
542d6675
KH		 6030 && md.explicit_mode
6031 && !md.mode_explicitly_set
6032 && !md.default_explicit_mode)
6033 dot_dv_mode ('A');
800eeca4
JW		 6034
6035 /* Allow '{' to follow on the same line. We also allow ";;", but that
6036 happens automatically because ';' is an end of line marker. */
6037 SKIP_WHITESPACE ();
6038 if (input_line_pointer[0] == '{')
6039 {
6040 input_line_pointer++;
6041 return ia64_unrecognized_line ('{');
6042 }
6043
6044 demand_empty_rest_of_line ();
6045 return 1;
6046
6047 default:
6048 break;
6049 }
542d6675
KH		 6050
6051 /* Not a valid line. */
6052 return 0;
800eeca4
JW		 6053}
6054
6055void
6056ia64_frob_label (sym)
6057 struct symbol *sym;
6058{
6059 struct label_fix *fix;
6060
6061 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6062 {
6063 md.last_text_seg = now_seg;
6064 fix = obstack_alloc (&notes, sizeof (*fix));
6065 fix->sym = sym;
6066 fix->next = CURR_SLOT.label_fixups;
6067 CURR_SLOT.label_fixups = fix;
6068
542d6675 6069 /* Keep track of how many code entry points we've seen. */
800eeca4 6070 if (md.path == md.maxpaths)
542d6675
KH		 6071 {
6072 md.maxpaths += 20;
6073 md.entry_labels = (const char **)
6074 xrealloc ((void *) md.entry_labels,
6075 md.maxpaths * sizeof (char *));
6076 }
800eeca4
JW		 6077 md.entry_labels[md.path++] = S_GET_NAME (sym);
6078 }
6079}
6080
6081void
6082ia64_flush_pending_output ()
6083{
6084 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6085 {
6086 /* ??? This causes many unnecessary stop bits to be emitted.
6087 Unfortunately, it isn't clear if it is safe to remove this. */
6088 insn_group_break (1, 0, 0);
6089 ia64_flush_insns ();
6090 }
6091}
6092
6093/* Do ia64-specific expression optimization. All that's done here is
6094 to transform index expressions that are either due to the indexing
6095 of rotating registers or due to the indexing of indirect register
6096 sets. */
6097int
6098ia64_optimize_expr (l, op, r)
6099 expressionS *l;
6100 operatorT op;
6101 expressionS *r;
6102{
6103 unsigned num_regs;
6104
6105 if (op == O_index)
6106 {
6107 if (l->X_op == O_register && r->X_op == O_constant)
6108 {
6109 num_regs = (l->X_add_number >> 16);
6110 if ((unsigned) r->X_add_number >= num_regs)
6111 {
6112 if (!num_regs)
6113 as_bad ("No current frame");
6114 else
6115 as_bad ("Index out of range 0..%u", num_regs - 1);
6116 r->X_add_number = 0;
6117 }
6118 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6119 return 1;
6120 }
6121 else if (l->X_op == O_register && r->X_op == O_register)
6122 {
6123 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6124 || l->X_add_number == IND_MEM)
6125 {
6126 as_bad ("Indirect register set name expected");
6127 l->X_add_number = IND_CPUID;
6128 }
6129 l->X_op = O_index;
6130 l->X_op_symbol = md.regsym[l->X_add_number];
6131 l->X_add_number = r->X_add_number;
6132 return 1;
6133 }
6134 }
6135 return 0;
6136}
6137
6138int
6139ia64_parse_name (name, e)
6140 char *name;
6141 expressionS *e;
6142{
6143 struct const_desc *cdesc;
6144 struct dynreg *dr = 0;
6145 unsigned int regnum;
6146 struct symbol *sym;
6147 char *end;
6148
542d6675 6149 /* first see if NAME is a known register name: */
800eeca4
JW		 6150 sym = hash_find (md.reg_hash, name);
6151 if (sym)
6152 {
6153 e->X_op = O_register;
6154 e->X_add_number = S_GET_VALUE (sym);
6155 return 1;
6156 }
6157
6158 cdesc = hash_find (md.const_hash, name);
6159 if (cdesc)
6160 {
6161 e->X_op = O_constant;
6162 e->X_add_number = cdesc->value;
6163 return 1;
6164 }
6165
542d6675 6166 /* check for inN, locN, or outN: */
800eeca4
JW		 6167 switch (name[0])
6168 {
6169 case 'i':
6170 if (name[1] == 'n' && isdigit (name[2]))
6171 {
6172 dr = &md.in;
6173 name += 2;
6174 }
6175 break;
6176
6177 case 'l':
6178 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6179 {
6180 dr = &md.loc;
6181 name += 3;
6182 }
6183 break;
6184
6185 case 'o':
6186 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6187 {
6188 dr = &md.out;
6189 name += 3;
6190 }
6191 break;
6192
6193 default:
6194 break;
6195 }
6196
6197 if (dr)
6198 {
542d6675 6199 /* The name is inN, locN, or outN; parse the register number. */
800eeca4
JW		 6200 regnum = strtoul (name, &end, 10);
6201 if (end > name && *end == '\0')
6202 {
6203 if ((unsigned) regnum >= dr->num_regs)
6204 {
6205 if (!dr->num_regs)
6206 as_bad ("No current frame");
6207 else
542d6675
KH		 6208 as_bad ("Register number out of range 0..%u",
6209 dr->num_regs - 1);
800eeca4
JW		 6210 regnum = 0;
6211 }
6212 e->X_op = O_register;
6213 e->X_add_number = dr->base + regnum;
6214 return 1;
6215 }
6216 }
6217
6218 if ((dr = hash_find (md.dynreg_hash, name)))
6219 {
6220 /* We've got ourselves the name of a rotating register set.
542d6675
KH		 6221 Store the base register number in the low 16 bits of
6222 X_add_number and the size of the register set in the top 16
6223 bits. */
800eeca4
JW		 6224 e->X_op = O_register;
6225 e->X_add_number = dr->base | (dr->num_regs << 16);
6226 return 1;
6227 }
6228 return 0;
6229}
6230
6231/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6232
6233char *
6234ia64_canonicalize_symbol_name (name)
6235 char *name;
6236{
542d6675
KH		 6237 size_t len = strlen (name);
6238 if (len > 1 && name[len - 1] == '#')
6239 name[len - 1] = '\0';
800eeca4
JW		 6240 return name;
6241}
6242
6243static int
6244is_conditional_branch (idesc)
542d6675 6245 struct ia64_opcode *idesc;
800eeca4
JW		 6246{
6247 return (strncmp (idesc->name, "br", 2) == 0
542d6675
KH		 6248 && (strcmp (idesc->name, "br") == 0
6249 || strncmp (idesc->name, "br.cond", 7) == 0
6250 || strncmp (idesc->name, "br.call", 7) == 0
6251 || strncmp (idesc->name, "br.ret", 6) == 0
6252 || strcmp (idesc->name, "brl") == 0
6253 || strncmp (idesc->name, "brl.cond", 7) == 0
6254 || strncmp (idesc->name, "brl.call", 7) == 0
6255 || strncmp (idesc->name, "brl.ret", 6) == 0));
800eeca4
JW		 6256}
6257
6258/* Return whether the given opcode is a taken branch. If there's any doubt,
542d6675
KH		 6259 returns zero. */
6260
800eeca4
JW		 6261static int
6262is_taken_branch (idesc)
542d6675 6263 struct ia64_opcode *idesc;
800eeca4
JW		 6264{
6265 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
542d6675 6266 || strncmp (idesc->name, "br.ia", 5) == 0);
800eeca4
JW		 6267}
6268
6269/* Return whether the given opcode is an interruption or rfi. If there's any
542d6675
KH		 6270 doubt, returns zero. */
6271
800eeca4
JW		 6272static int
6273is_interruption_or_rfi (idesc)
542d6675 6274 struct ia64_opcode *idesc;
800eeca4
JW		 6275{
6276 if (strcmp (idesc->name, "rfi") == 0)
6277 return 1;
6278 return 0;
6279}
6280
6281/* Returns the index of the given dependency in the opcode's list of chks, or
6282 -1 if there is no dependency. */
542d6675 6283
800eeca4
JW		 6284static int
6285depends_on (depind, idesc)
542d6675
KH		 6286 int depind;
6287 struct ia64_opcode *idesc;
800eeca4
JW		 6288{
6289 int i;
6290 const struct ia64_opcode_dependency *dep = idesc->dependencies;
542d6675 6291 for (i = 0; i < dep->nchks; i++)
800eeca4 6292 {
542d6675
KH		 6293 if (depind == DEP (dep->chks[i]))
6294 return i;
800eeca4
JW		 6295 }
6296 return -1;
6297}
6298
6299/* Determine a set of specific resources used for a particular resource
6300 class. Returns the number of specific resources identified For those
6301 cases which are not determinable statically, the resource returned is
197865e8 6302 marked nonspecific.
800eeca4
JW		 6303
6304 Meanings of value in 'NOTE':
6305 1) only read/write when the register number is explicitly encoded in the
6306 insn.
6307 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
197865e8 6308 accesses CFM when qualifying predicate is in the rotating region.
800eeca4
JW		 6309 3) general register value is used to specify an indirect register; not
6310 determinable statically.
6311 4) only read the given resource when bits 7:0 of the indirect index
6312 register value does not match the register number of the resource; not
6313 determinable statically.
6314 5) all rules are implementation specific.
6315 6) only when both the index specified by the reader and the index specified
6316 by the writer have the same value in bits 63:61; not determinable
197865e8 6317 statically.
800eeca4 6318 7) only access the specified resource when the corresponding mask bit is
197865e8 6319 set
800eeca4
JW		 6320 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6321 only read when these insns reference FR2-31
6322 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6323 written when these insns write FR32-127
6324 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6325 instruction
6326 11) The target predicates are written independently of PR[qp], but source
6327 registers are only read if PR[qp] is true. Since the state of PR[qp]
6328 cannot statically be determined, all source registers are marked used.
6329 12) This insn only reads the specified predicate register when that
6330 register is the PR[qp].
6331 13) This reference to ld-c only applies to teh GR whose value is loaded
197865e8 6332 with data returned from memory, not the post-incremented address register.
800eeca4
JW		 6333 14) The RSE resource includes the implementation-specific RSE internal
6334 state resources. At least one (and possibly more) of these resources are
6335 read by each instruction listed in IC:rse-readers. At least one (and
6336 possibly more) of these resources are written by each insn listed in
197865e8 6337 IC:rse-writers.
800eeca4 6338 15+16) Represents reserved instructions, which the assembler does not
197865e8 6339 generate.
800eeca4
JW		 6340
6341 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6342 this code; there are no dependency violations based on memory access.
800eeca4
JW		 6343*/
6344
6345#define MAX_SPECS 256
6346#define DV_CHK 1
6347#define DV_REG 0
6348
6349static int
6350specify_resource (dep, idesc, type, specs, note, path)
542d6675
KH		 6351 const struct ia64_dependency *dep;
6352 struct ia64_opcode *idesc;
6353 int type; /* is this a DV chk or a DV reg? */
6354 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6355 int note; /* resource note for this insn's usage */
6356 int path; /* which execution path to examine */
800eeca4
JW		 6357{
6358 int count = 0;
6359 int i;
6360 int rsrc_write = 0;
6361 struct rsrc tmpl;
197865e8 6362
800eeca4
JW		 6363 if (dep->mode == IA64_DV_WAW
6364 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6365 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6366 rsrc_write = 1;
6367
6368 /* template for any resources we identify */
6369 tmpl.dependency = dep;
6370 tmpl.note = note;
6371 tmpl.insn_srlz = tmpl.data_srlz = 0;
6372 tmpl.qp_regno = CURR_SLOT.qp_regno;
6373 tmpl.link_to_qp_branch = 1;
6374 tmpl.mem_offset.hint = 0;
6375 tmpl.specific = 1;
6376 tmpl.index = 0;
6377
6378#define UNHANDLED \
6379as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6380dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6381#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6382
6383 /* we don't need to track these */
6384 if (dep->semantics == IA64_DVS_NONE)
6385 return 0;
6386
6387 switch (dep->specifier)
6388 {
6389 case IA64_RS_AR_K:
6390 if (note == 1)
542d6675
KH		 6391 {
6392 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6393 {
6394 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6395 if (regno >= 0 && regno <= 7)
6396 {
6397 specs[count] = tmpl;
6398 specs[count++].index = regno;
6399 }
6400 }
6401 }
800eeca4 6402 else if (note == 0)
542d6675
KH		 6403 {
6404 for (i = 0; i < 8; i++)
6405 {
6406 specs[count] = tmpl;
6407 specs[count++].index = i;
6408 }
6409 }
800eeca4 6410 else
542d6675
KH		 6411 {
6412 UNHANDLED;
6413 }
800eeca4
JW		 6414 break;
6415
6416 case IA64_RS_AR_UNAT:
6417 /* This is a mov =AR or mov AR= instruction. */
6418 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6419 {
6420 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6421 if (regno == AR_UNAT)
6422 {
6423 specs[count++] = tmpl;
6424 }
6425 }
6426 else
6427 {
6428 /* This is a spill/fill, or other instruction that modifies the
6429 unat register. */
6430
6431 /* Unless we can determine the specific bits used, mark the whole
6432 thing; bits 8:3 of the memory address indicate the bit used in
6433 UNAT. The .mem.offset hint may be used to eliminate a small
6434 subset of conflicts. */
6435 specs[count] = tmpl;
6436 if (md.mem_offset.hint)
6437 {
542d6675
KH		 6438 if (md.debug_dv)
6439 fprintf (stderr, " Using hint for spill/fill\n");
6440 /* The index isn't actually used, just set it to something
6441 approximating the bit index. */
800eeca4
JW		 6442 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6443 specs[count].mem_offset.hint = 1;
6444 specs[count].mem_offset.offset = md.mem_offset.offset;
6445 specs[count++].mem_offset.base = md.mem_offset.base;
6446 }
6447 else
6448 {
6449 specs[count++].specific = 0;
6450 }
6451 }
6452 break;
6453
6454 case IA64_RS_AR:
6455 if (note == 1)
542d6675
KH		 6456 {
6457 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6458 {
6459 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6460 if ((regno >= 8 && regno <= 15)
6461 || (regno >= 20 && regno <= 23)
6462 || (regno >= 31 && regno <= 39)
6463 || (regno >= 41 && regno <= 47)
6464 || (regno >= 67 && regno <= 111))
6465 {
6466 specs[count] = tmpl;
6467 specs[count++].index = regno;
6468 }
6469 }
6470 }
800eeca4 6471 else
542d6675
KH		 6472 {
6473 UNHANDLED;
6474 }
800eeca4
JW		 6475 break;
6476
6477 case IA64_RS_ARb:
6478 if (note == 1)
542d6675
KH		 6479 {
6480 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6481 {
6482 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6483 if ((regno >= 48 && regno <= 63)
6484 || (regno >= 112 && regno <= 127))
6485 {
6486 specs[count] = tmpl;
6487 specs[count++].index = regno;
6488 }
6489 }
6490 }
800eeca4 6491 else if (note == 0)
542d6675
KH		 6492 {
6493 for (i = 48; i < 64; i++)
6494 {
6495 specs[count] = tmpl;
6496 specs[count++].index = i;
6497 }
6498 for (i = 112; i < 128; i++)
6499 {
6500 specs[count] = tmpl;
6501 specs[count++].index = i;
6502 }
6503 }
197865e8 6504 else
542d6675
KH		 6505 {
6506 UNHANDLED;
6507 }
800eeca4
JW		 6508 break;
6509
6510 case IA64_RS_BR:
6511 if (note != 1)
542d6675
KH		 6512 {
6513 UNHANDLED;
6514 }
800eeca4 6515 else
542d6675
KH		 6516 {
6517 if (rsrc_write)
6518 {
6519 for (i = 0; i < idesc->num_outputs; i++)
6520 if (idesc->operands[i] == IA64_OPND_B1
6521 || idesc->operands[i] == IA64_OPND_B2)
6522 {
6523 specs[count] = tmpl;
6524 specs[count++].index =
6525 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6526 }
6527 }
6528 else
6529 {
6530 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
6531 if (idesc->operands[i] == IA64_OPND_B1
6532 || idesc->operands[i] == IA64_OPND_B2)
6533 {
6534 specs[count] = tmpl;
6535 specs[count++].index =
6536 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6537 }
6538 }
6539 }
800eeca4
JW		 6540 break;
6541
6542 case IA64_RS_CPUID: /* four or more registers */
6543 if (note == 3)
542d6675
KH		 6544 {
6545 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6546 {
6547 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6548 if (regno >= 0 && regno < NELEMS (gr_values)
6549 && KNOWN (regno))
6550 {
6551 specs[count] = tmpl;
6552 specs[count++].index = gr_values[regno].value & 0xFF;
6553 }
6554 else
6555 {
6556 specs[count] = tmpl;
6557 specs[count++].specific = 0;
6558 }
6559 }
6560 }
800eeca4 6561 else
542d6675
KH		 6562 {
6563 UNHANDLED;
6564 }
800eeca4
JW		 6565 break;
6566
6567 case IA64_RS_DBR: /* four or more registers */
6568 if (note == 3)
542d6675
KH		 6569 {
6570 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6571 {
6572 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6573 if (regno >= 0 && regno < NELEMS (gr_values)
6574 && KNOWN (regno))
6575 {
6576 specs[count] = tmpl;
6577 specs[count++].index = gr_values[regno].value & 0xFF;
6578 }
6579 else
6580 {
6581 specs[count] = tmpl;
6582 specs[count++].specific = 0;
6583 }
6584 }
6585 }
800eeca4 6586 else if (note == 0 && !rsrc_write)
542d6675
KH		 6587 {
6588 specs[count] = tmpl;
6589 specs[count++].specific = 0;
6590 }
800eeca4 6591 else
542d6675
KH		 6592 {
6593 UNHANDLED;
6594 }
800eeca4
JW		 6595 break;
6596
6597 case IA64_RS_IBR: /* four or more registers */
6598 if (note == 3)
542d6675
KH		 6599 {
6600 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6601 {
6602 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6603 if (regno >= 0 && regno < NELEMS (gr_values)
6604 && KNOWN (regno))
6605 {
6606 specs[count] = tmpl;
6607 specs[count++].index = gr_values[regno].value & 0xFF;
6608 }
6609 else
6610 {
6611 specs[count] = tmpl;
6612 specs[count++].specific = 0;
6613 }
6614 }
6615 }
800eeca4 6616 else
542d6675
KH		 6617 {
6618 UNHANDLED;
6619 }
800eeca4
JW		 6620 break;
6621
6622 case IA64_RS_MSR:
6623 if (note == 5)
6624 {
6625 /* These are implementation specific. Force all references to
6626 conflict with all other references. */
6627 specs[count] = tmpl;
6628 specs[count++].specific = 0;
6629 }
6630 else
6631 {
6632 UNHANDLED;
6633 }
6634 break;
6635
6636 case IA64_RS_PKR: /* 16 or more registers */
6637 if (note == 3 || note == 4)
542d6675
KH		 6638 {
6639 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6640 {
6641 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6642 if (regno >= 0 && regno < NELEMS (gr_values)
6643 && KNOWN (regno))
6644 {
6645 if (note == 3)
6646 {
6647 specs[count] = tmpl;
6648 specs[count++].index = gr_values[regno].value & 0xFF;
6649 }
6650 else
6651 for (i = 0; i < NELEMS (gr_values); i++)
6652 {
6653 /* Uses all registers *except* the one in R3. */
6654 if (i != (gr_values[regno].value & 0xFF))
6655 {
6656 specs[count] = tmpl;
6657 specs[count++].index = i;
6658 }
6659 }
6660 }
6661 else
6662 {
6663 specs[count] = tmpl;
6664 specs[count++].specific = 0;
6665 }
6666 }
6667 }
6668 else if (note == 0)
6669 {
6670 /* probe et al. */
6671 specs[count] = tmpl;
6672 specs[count++].specific = 0;
6673 }
6674 break;
6675
6676 case IA64_RS_PMC: /* four or more registers */
6677 if (note == 3)
6678 {
6679 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
6680 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
6681
6682 {
6683 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
6684 ? 1 : !rsrc_write);
6685 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
6686 if (regno >= 0 && regno < NELEMS (gr_values)
6687 && KNOWN (regno))
6688 {
6689 specs[count] = tmpl;
6690 specs[count++].index = gr_values[regno].value & 0xFF;
6691 }
6692 else
6693 {
6694 specs[count] = tmpl;
6695 specs[count++].specific = 0;
6696 }
6697 }
6698 }
6699 else
6700 {
6701 UNHANDLED;
6702 }
800eeca4
JW		 6703 break;
6704
6705 case IA64_RS_PMD: /* four or more registers */
6706 if (note == 3)
542d6675
KH		 6707 {
6708 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
6709 {
6710 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6711 if (regno >= 0 && regno < NELEMS (gr_values)
6712 && KNOWN (regno))
6713 {
6714 specs[count] = tmpl;
6715 specs[count++].index = gr_values[regno].value & 0xFF;
6716 }
6717 else
6718 {
6719 specs[count] = tmpl;
6720 specs[count++].specific = 0;
6721 }
6722 }
6723 }
800eeca4 6724 else
542d6675
KH		 6725 {
6726 UNHANDLED;
6727 }
800eeca4
JW		 6728 break;
6729
6730 case IA64_RS_RR: /* eight registers */
6731 if (note == 6)
542d6675
KH		 6732 {
6733 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
6734 {
6735 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6736 if (regno >= 0 && regno < NELEMS (gr_values)
6737 && KNOWN (regno))
6738 {
6739 specs[count] = tmpl;
6740 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
6741 }
6742 else
6743 {
6744 specs[count] = tmpl;
6745 specs[count++].specific = 0;
6746 }
6747 }
6748 }
800eeca4 6749 else if (note == 0 && !rsrc_write)
542d6675
KH		 6750 {
6751 specs[count] = tmpl;
6752 specs[count++].specific = 0;
6753 }
197865e8 6754 else
542d6675
KH		 6755 {
6756 UNHANDLED;
6757 }
800eeca4
JW		 6758 break;
6759
6760 case IA64_RS_CR_IRR:
197865e8 6761 if (note == 0)
542d6675
KH		 6762 {
6763 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6764 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
6765 if (rsrc_write
6766 && idesc->operands[1] == IA64_OPND_CR3
6767 && regno == CR_IVR)
6768 {
6769 for (i = 0; i < 4; i++)
6770 {
6771 specs[count] = tmpl;
6772 specs[count++].index = CR_IRR0 + i;
6773 }
6774 }
6775 }
800eeca4 6776 else if (note == 1)
542d6675
KH		 6777 {
6778 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6779 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6780 && regno >= CR_IRR0
6781 && regno <= CR_IRR3)
6782 {
6783 specs[count] = tmpl;
6784 specs[count++].index = regno;
6785 }
6786 }
800eeca4 6787 else
542d6675
KH		 6788 {
6789 UNHANDLED;
6790 }
800eeca4
JW		 6791 break;
6792
6793 case IA64_RS_CR_LRR:
6794 if (note != 1)
542d6675
KH		 6795 {
6796 UNHANDLED;
6797 }
197865e8 6798 else
542d6675
KH		 6799 {
6800 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6801 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6802 && (regno == CR_LRR0 || regno == CR_LRR1))
6803 {
6804 specs[count] = tmpl;
6805 specs[count++].index = regno;
6806 }
6807 }
800eeca4
JW		 6808 break;
6809
6810 case IA64_RS_CR:
6811 if (note == 1)
542d6675
KH		 6812 {
6813 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
6814 {
6815 specs[count] = tmpl;
6816 specs[count++].index =
6817 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6818 }
6819 }
800eeca4 6820 else
542d6675
KH		 6821 {
6822 UNHANDLED;
6823 }
800eeca4
JW		 6824 break;
6825
6826 case IA64_RS_FR:
6827 case IA64_RS_FRb:
6828 if (note != 1)
542d6675
KH		 6829 {
6830 UNHANDLED;
6831 }
800eeca4 6832 else if (rsrc_write)
542d6675
KH		 6833 {
6834 if (dep->specifier == IA64_RS_FRb
6835 && idesc->operands[0] == IA64_OPND_F1)
6836 {
6837 specs[count] = tmpl;
6838 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
6839 }
6840 }
800eeca4 6841 else
542d6675
KH		 6842 {
6843 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
6844 {
6845 if (idesc->operands[i] == IA64_OPND_F2
6846 || idesc->operands[i] == IA64_OPND_F3
6847 || idesc->operands[i] == IA64_OPND_F4)
6848 {
6849 specs[count] = tmpl;
6850 specs[count++].index =
6851 CURR_SLOT.opnd[i].X_add_number - REG_FR;
6852 }
6853 }
6854 }
800eeca4
JW		 6855 break;
6856
6857 case IA64_RS_GR:
6858 if (note == 13)
542d6675
KH		 6859 {
6860 /* This reference applies only to the GR whose value is loaded with
6861 data returned from memory. */
6862 specs[count] = tmpl;
6863 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
6864 }
800eeca4 6865 else if (note == 1)
542d6675
KH		 6866 {
6867 if (rsrc_write)
6868 {
6869 for (i = 0; i < idesc->num_outputs; i++)
50b81f19
JW		 6870 if (idesc->operands[i] == IA64_OPND_R1
6871 || idesc->operands[i] == IA64_OPND_R2
6872 || idesc->operands[i] == IA64_OPND_R3)
6873 {
6874 specs[count] = tmpl;
197865e8 6875 specs[count++].index =
50b81f19
JW		 6876 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6877 }
6878 if (idesc->flags & IA64_OPCODE_POSTINC)
6879 for (i = 0; i < NELEMS (idesc->operands); i++)
6880 if (idesc->operands[i] == IA64_OPND_MR3)
6881 {
6882 specs[count] = tmpl;
6883 specs[count++].index =
6884 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6885 }
542d6675
KH		 6886 }
6887 else
6888 {
6889 /* Look for anything that reads a GR. */
6890 for (i = 0; i < NELEMS (idesc->operands); i++)
6891 {
6892 if (idesc->operands[i] == IA64_OPND_MR3
6893 || idesc->operands[i] == IA64_OPND_CPUID_R3
6894 || idesc->operands[i] == IA64_OPND_DBR_R3
6895 || idesc->operands[i] == IA64_OPND_IBR_R3
800eeca4 6896 || idesc->operands[i] == IA64_OPND_MSR_R3
542d6675
KH		 6897 || idesc->operands[i] == IA64_OPND_PKR_R3
6898 || idesc->operands[i] == IA64_OPND_PMC_R3
6899 || idesc->operands[i] == IA64_OPND_PMD_R3
6900 || idesc->operands[i] == IA64_OPND_RR_R3
6901 || ((i >= idesc->num_outputs)
6902 && (idesc->operands[i] == IA64_OPND_R1
6903 || idesc->operands[i] == IA64_OPND_R2
6904 || idesc->operands[i] == IA64_OPND_R3
50b81f19
JW		 6905 /* addl source register. */
6906 || idesc->operands[i] == IA64_OPND_R3_2)))
542d6675
KH		 6907 {
6908 specs[count] = tmpl;
6909 specs[count++].index =
6910 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6911 }
6912 }
6913 }
6914 }
197865e8 6915 else
542d6675
KH		 6916 {
6917 UNHANDLED;
6918 }
800eeca4
JW		 6919 break;
6920
6921 case IA64_RS_PR:
6922 if (note == 0)
542d6675
KH		 6923 {
6924 if (idesc->operands[0] == IA64_OPND_PR_ROT)
6925 {
6926 for (i = 16; i < 63; i++)
6927 {
6928 specs[count] = tmpl;
6929 specs[count++].index = i;
6930 }
6931 }
6932 else
6933 {
6934 for (i = 1; i < 63; i++)
6935 {
6936 specs[count] = tmpl;
6937 specs[count++].index = i;
6938 }
6939 }
6940 }
800eeca4 6941 else if (note == 7)
542d6675
KH		 6942 {
6943 valueT mask = 0;
6944 /* Mark only those registers indicated by the mask. */
6945 if (rsrc_write
6946 && idesc->operands[0] == IA64_OPND_PR)
6947 {
6948 mask = CURR_SLOT.opnd[2].X_add_number;
6949 if (mask & ((valueT) 1 << 16))
6950 mask |= ~(valueT) 0xffff;
6951 for (i = 1; i < 63; i++)
6952 {
6953 if (mask & ((valueT) 1 << i))
6954 {
6955 specs[count] = tmpl;
6956 specs[count++].index = i;
6957 }
6958 }
6959 }
6960 else if (rsrc_write
6961 && idesc->operands[0] == IA64_OPND_PR_ROT)
6962 {
6963 for (i = 16; i < 63; i++)
6964 {
6965 specs[count] = tmpl;
6966 specs[count++].index = i;
6967 }
6968 }
6969 else
6970 {
6971 UNHANDLED;
6972 }
6973 }
800eeca4 6974 else if (note == 11) /* note 11 implies note 1 as well */
542d6675
KH		 6975 {
6976 if (rsrc_write)
6977 {
6978 for (i = 0; i < idesc->num_outputs; i++)
6979 {
6980 if (idesc->operands[i] == IA64_OPND_P1
6981 || idesc->operands[i] == IA64_OPND_P2)
6982 {
6983 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
6984 if (regno != 0)
6985 {
6986 specs[count] = tmpl;
6987 specs[count++].index = regno;
6988 }
6989 }
6990 }
6991 }
6992 else
6993 {
6994 UNHANDLED;
6995 }
6996 }
800eeca4 6997 else if (note == 12)
542d6675
KH		 6998 {
6999 if (CURR_SLOT.qp_regno != 0)
7000 {
7001 specs[count] = tmpl;
7002 specs[count++].index = CURR_SLOT.qp_regno;
7003 }
7004 }
800eeca4 7005 else if (note == 1)
542d6675
KH		 7006 {
7007 if (rsrc_write)
7008 {
7009 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7010 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7011 if ((idesc->operands[0] == IA64_OPND_P1
7012 || idesc->operands[0] == IA64_OPND_P2)
7013 && p1 != 0 && p1 != 63)
7014 {
7015 specs[count] = tmpl;
7016 specs[count++].index = p1;
7017 }
7018 if ((idesc->operands[1] == IA64_OPND_P1
7019 || idesc->operands[1] == IA64_OPND_P2)
7020 && p2 != 0 && p2 != 63)
7021 {
7022 specs[count] = tmpl;
7023 specs[count++].index = p2;
7024 }
7025 }
7026 else
7027 {
7028 if (CURR_SLOT.qp_regno != 0)
7029 {
7030 specs[count] = tmpl;
7031 specs[count++].index = CURR_SLOT.qp_regno;
7032 }
7033 if (idesc->operands[1] == IA64_OPND_PR)
7034 {
7035 for (i = 1; i < 63; i++)
7036 {
7037 specs[count] = tmpl;
7038 specs[count++].index = i;
7039 }
7040 }
7041 }
7042 }
197865e8 7043 else
542d6675
KH		 7044 {
7045 UNHANDLED;
7046 }
800eeca4
JW		 7047 break;
7048
7049 case IA64_RS_PSR:
197865e8 7050 /* Verify that the instruction is using the PSR bit indicated in
542d6675 7051 dep->regindex. */
800eeca4 7052 if (note == 0)
542d6675
KH		 7053 {
7054 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7055 {
7056 if (dep->regindex < 6)
7057 {
7058 specs[count++] = tmpl;
7059 }
7060 }
7061 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7062 {
7063 if (dep->regindex < 32
7064 || dep->regindex == 35
7065 || dep->regindex == 36
7066 || (!rsrc_write && dep->regindex == PSR_CPL))
7067 {
7068 specs[count++] = tmpl;
7069 }
7070 }
7071 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7072 {
7073 if (dep->regindex < 32
7074 || dep->regindex == 35
7075 || dep->regindex == 36
7076 || (rsrc_write && dep->regindex == PSR_CPL))
7077 {
7078 specs[count++] = tmpl;
7079 }
7080 }
7081 else
7082 {
7083 /* Several PSR bits have very specific dependencies. */
7084 switch (dep->regindex)
7085 {
7086 default:
7087 specs[count++] = tmpl;
7088 break;
7089 case PSR_IC:
7090 if (rsrc_write)
7091 {
7092 specs[count++] = tmpl;
7093 }
7094 else
7095 {
7096 /* Only certain CR accesses use PSR.ic */
7097 if (idesc->operands[0] == IA64_OPND_CR3
7098 || idesc->operands[1] == IA64_OPND_CR3)
7099 {
7100 int index =
7101 ((idesc->operands[0] == IA64_OPND_CR3)
7102 ? 0 : 1);
7103 int regno =
7104 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7105
7106 switch (regno)
7107 {
7108 default:
7109 break;
7110 case CR_ITIR:
7111 case CR_IFS:
7112 case CR_IIM:
7113 case CR_IIP:
7114 case CR_IPSR:
7115 case CR_ISR:
7116 case CR_IFA:
7117 case CR_IHA:
7118 case CR_IIPA:
7119 specs[count++] = tmpl;
7120 break;
7121 }
7122 }
7123 }
7124 break;
7125 case PSR_CPL:
7126 if (rsrc_write)
7127 {
7128 specs[count++] = tmpl;
7129 }
7130 else
7131 {
7132 /* Only some AR accesses use cpl */
7133 if (idesc->operands[0] == IA64_OPND_AR3
7134 || idesc->operands[1] == IA64_OPND_AR3)
7135 {
7136 int index =
7137 ((idesc->operands[0] == IA64_OPND_AR3)
7138 ? 0 : 1);
7139 int regno =
7140 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7141
7142 if (regno == AR_ITC
7143 || (index == 0
7144 && (regno == AR_ITC
7145 || regno == AR_RSC
7146 || (regno >= AR_K0
7147 && regno <= AR_K7))))
7148 {
7149 specs[count++] = tmpl;
7150 }
7151 }
7152 else
7153 {
7154 specs[count++] = tmpl;
7155 }
7156 break;
7157 }
7158 }
7159 }
7160 }
800eeca4 7161 else if (note == 7)
542d6675
KH		 7162 {
7163 valueT mask = 0;
7164 if (idesc->operands[0] == IA64_OPND_IMMU24)
7165 {
7166 mask = CURR_SLOT.opnd[0].X_add_number;
7167 }
7168 else
7169 {
7170 UNHANDLED;
7171 }
7172 if (mask & ((valueT) 1 << dep->regindex))
7173 {
7174 specs[count++] = tmpl;
7175 }
7176 }
800eeca4 7177 else if (note == 8)
542d6675
KH		 7178 {
7179 int min = dep->regindex == PSR_DFL ? 2 : 32;
7180 int max = dep->regindex == PSR_DFL ? 31 : 127;
7181 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7182 for (i = 0; i < NELEMS (idesc->operands); i++)
7183 {
7184 if (idesc->operands[i] == IA64_OPND_F1
7185 || idesc->operands[i] == IA64_OPND_F2
7186 || idesc->operands[i] == IA64_OPND_F3
7187 || idesc->operands[i] == IA64_OPND_F4)
7188 {
7189 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7190 if (reg >= min && reg <= max)
7191 {
7192 specs[count++] = tmpl;
7193 }
7194 }
7195 }
7196 }
800eeca4 7197 else if (note == 9)
542d6675
KH		 7198 {
7199 int min = dep->regindex == PSR_MFL ? 2 : 32;
7200 int max = dep->regindex == PSR_MFL ? 31 : 127;
7201 /* mfh is read on writes to FR32-127; mfl is read on writes to
7202 FR2-31 */
7203 for (i = 0; i < idesc->num_outputs; i++)
7204 {
7205 if (idesc->operands[i] == IA64_OPND_F1)
7206 {
7207 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7208 if (reg >= min && reg <= max)
7209 {
7210 specs[count++] = tmpl;
7211 }
7212 }
7213 }
7214 }
800eeca4 7215 else if (note == 10)
542d6675
KH		 7216 {
7217 for (i = 0; i < NELEMS (idesc->operands); i++)
7218 {
7219 if (idesc->operands[i] == IA64_OPND_R1
7220 || idesc->operands[i] == IA64_OPND_R2
7221 || idesc->operands[i] == IA64_OPND_R3)
7222 {
7223 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7224 if (regno >= 16 && regno <= 31)
7225 {
7226 specs[count++] = tmpl;
7227 }
7228 }
7229 }
7230 }
800eeca4 7231 else
542d6675
KH		 7232 {
7233 UNHANDLED;
7234 }
800eeca4
JW		 7235 break;
7236
7237 case IA64_RS_AR_FPSR:
7238 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
542d6675
KH		 7239 {
7240 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7241 if (regno == AR_FPSR)
7242 {
7243 specs[count++] = tmpl;
7244 }
7245 }
800eeca4 7246 else
542d6675
KH		 7247 {
7248 specs[count++] = tmpl;
7249 }
800eeca4
JW		 7250 break;
7251
197865e8 7252 case IA64_RS_ARX:
800eeca4
JW		 7253 /* Handle all AR[REG] resources */
7254 if (note == 0 || note == 1)
542d6675
KH		 7255 {
7256 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7257 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7258 && regno == dep->regindex)
7259 {
7260 specs[count++] = tmpl;
7261 }
7262 /* other AR[REG] resources may be affected by AR accesses */
7263 else if (idesc->operands[0] == IA64_OPND_AR3)
7264 {
7265 /* AR[] writes */
7266 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7267 switch (dep->regindex)
7268 {
7269 default:
7270 break;
7271 case AR_BSP:
7272 case AR_RNAT:
7273 if (regno == AR_BSPSTORE)
7274 {
7275 specs[count++] = tmpl;
7276 }
7277 case AR_RSC:
7278 if (!rsrc_write &&
7279 (regno == AR_BSPSTORE
7280 || regno == AR_RNAT))
7281 {
7282 specs[count++] = tmpl;
7283 }
7284 break;
7285 }
7286 }
7287 else if (idesc->operands[1] == IA64_OPND_AR3)
7288 {
7289 /* AR[] reads */
7290 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7291 switch (dep->regindex)
7292 {
7293 default:
7294 break;
7295 case AR_RSC:
7296 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7297 {
7298 specs[count++] = tmpl;
7299 }
7300 break;
7301 }
7302 }
7303 else
7304 {
7305 specs[count++] = tmpl;
7306 }
7307 }
800eeca4 7308 else
542d6675
KH		 7309 {
7310 UNHANDLED;
7311 }
800eeca4
JW		 7312 break;
7313
7314 case IA64_RS_CRX:
7315 /* Handle all CR[REG] resources */
7316 if (note == 0 || note == 1)
542d6675
KH		 7317 {
7318 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7319 {
7320 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7321 if (regno == dep->regindex)
7322 {
7323 specs[count++] = tmpl;
7324 }
7325 else if (!rsrc_write)
7326 {
7327 /* Reads from CR[IVR] affect other resources. */
7328 if (regno == CR_IVR)
7329 {
7330 if ((dep->regindex >= CR_IRR0
7331 && dep->regindex <= CR_IRR3)
7332 || dep->regindex == CR_TPR)
7333 {
7334 specs[count++] = tmpl;
7335 }
7336 }
7337 }
7338 }
7339 else
7340 {
7341 specs[count++] = tmpl;
7342 }
7343 }
800eeca4 7344 else
542d6675
KH		 7345 {
7346 UNHANDLED;
7347 }
800eeca4
JW		 7348 break;
7349
7350 case IA64_RS_INSERVICE:
7351 /* look for write of EOI (67) or read of IVR (65) */
7352 if ((idesc->operands[0] == IA64_OPND_CR3
542d6675
KH		 7353 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7354 || (idesc->operands[1] == IA64_OPND_CR3
7355 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7356 {
7357 specs[count++] = tmpl;
7358 }
800eeca4
JW		 7359 break;
7360
7361 case IA64_RS_GR0:
7362 if (note == 1)
542d6675
KH		 7363 {
7364 specs[count++] = tmpl;
7365 }
800eeca4 7366 else
542d6675
KH		 7367 {
7368 UNHANDLED;
7369 }
800eeca4
JW		 7370 break;
7371
7372 case IA64_RS_CFM:
7373 if (note != 2)
542d6675
KH		 7374 {
7375 specs[count++] = tmpl;
7376 }
800eeca4 7377 else
542d6675
KH		 7378 {
7379 /* Check if any of the registers accessed are in the rotating region.
7380 mov to/from pr accesses CFM only when qp_regno is in the rotating
7381 region */
7382 for (i = 0; i < NELEMS (idesc->operands); i++)
7383 {
7384 if (idesc->operands[i] == IA64_OPND_R1
7385 || idesc->operands[i] == IA64_OPND_R2
7386 || idesc->operands[i] == IA64_OPND_R3)
7387 {
7388 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7389 /* Assumes that md.rot.num_regs is always valid */
7390 if (md.rot.num_regs > 0
7391 && num > 31
7392 && num < 31 + md.rot.num_regs)
7393 {
7394 specs[count] = tmpl;
7395 specs[count++].specific = 0;
7396 }
7397 }
7398 else if (idesc->operands[i] == IA64_OPND_F1
7399 || idesc->operands[i] == IA64_OPND_F2
7400 || idesc->operands[i] == IA64_OPND_F3
7401 || idesc->operands[i] == IA64_OPND_F4)
7402 {
7403 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7404 if (num > 31)
7405 {
7406 specs[count] = tmpl;
7407 specs[count++].specific = 0;
7408 }
7409 }
7410 else if (idesc->operands[i] == IA64_OPND_P1
7411 || idesc->operands[i] == IA64_OPND_P2)
7412 {
7413 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7414 if (num > 15)
7415 {
7416 specs[count] = tmpl;
7417 specs[count++].specific = 0;
7418 }
7419 }
7420 }
7421 if (CURR_SLOT.qp_regno > 15)
7422 {
7423 specs[count] = tmpl;
7424 specs[count++].specific = 0;
7425 }
7426 }
800eeca4
JW		 7427 break;
7428
7429 case IA64_RS_PR63:
7430 if (note == 0)
542d6675
KH		 7431 {
7432 specs[count++] = tmpl;
7433 }
800eeca4 7434 else if (note == 11)
542d6675
KH		 7435 {
7436 if ((idesc->operands[0] == IA64_OPND_P1
7437 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7438 || (idesc->operands[1] == IA64_OPND_P2
7439 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7440 {
7441 specs[count++] = tmpl;
7442 }
7443 }
800eeca4 7444 else if (note == 12)
542d6675
KH		 7445 {
7446 if (CURR_SLOT.qp_regno == 63)
7447 {
7448 specs[count++] = tmpl;
7449 }
7450 }
800eeca4 7451 else if (note == 7)
542d6675
KH		 7452 {
7453 valueT mask = 0;
7454 if (idesc->operands[2] == IA64_OPND_IMM17)
7455 mask = CURR_SLOT.opnd[2].X_add_number;
7456 if (mask & ((valueT) 1 << 63))
7457 {
7458 specs[count++] = tmpl;
7459 }
7460 }
800eeca4 7461 else if (note == 1)
542d6675
KH		 7462 {
7463 if (rsrc_write)
7464 {
7465 for (i = 0; i < idesc->num_outputs; i++)
7466 if ((idesc->operands[i] == IA64_OPND_P1
7467 || idesc->operands[i] == IA64_OPND_P2)
7468 && CURR_SLOT.opnd[i].X_add_number - REG_P == 63)
7469 {
7470 specs[count++] = tmpl;
7471 }
7472 }
7473 else
7474 {
7475 if (CURR_SLOT.qp_regno == 63)
7476 {
7477 specs[count++] = tmpl;
7478 }
7479 }
7480 }
800eeca4 7481 else
542d6675
KH		 7482 {
7483 UNHANDLED;
7484 }
800eeca4
JW		 7485 break;
7486
7487 case IA64_RS_RSE:
7488 /* FIXME we can identify some individual RSE written resources, but RSE
542d6675
KH		 7489 read resources have not yet been completely identified, so for now
7490 treat RSE as a single resource */
800eeca4 7491 if (strncmp (idesc->name, "mov", 3) == 0)
542d6675
KH		 7492 {
7493 if (rsrc_write)
7494 {
7495 if (idesc->operands[0] == IA64_OPND_AR3
7496 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7497 {
7498 specs[count] = tmpl;
7499 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7500 }
7501 }
7502 else
7503 {
7504 if (idesc->operands[0] == IA64_OPND_AR3)
7505 {
7506 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7507 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7508 {
7509 specs[count++] = tmpl;
7510 }
7511 }
7512 else if (idesc->operands[1] == IA64_OPND_AR3)
7513 {
7514 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7515 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7516 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7517 {
7518 specs[count++] = tmpl;
7519 }
7520 }
7521 }
7522 }
197865e8 7523 else
542d6675
KH		 7524 {
7525 specs[count++] = tmpl;
7526 }
800eeca4
JW		 7527 break;
7528
7529 case IA64_RS_ANY:
7530 /* FIXME -- do any of these need to be non-specific? */
7531 specs[count++] = tmpl;
7532 break;
7533
7534 default:
7535 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7536 break;
7537 }
7538
7539 return count;
7540}
7541
7542/* Clear branch flags on marked resources. This breaks the link between the
542d6675
KH		 7543 QP of the marking instruction and a subsequent branch on the same QP. */
7544
800eeca4
JW		 7545static void
7546clear_qp_branch_flag (mask)
542d6675 7547 valueT mask;
800eeca4
JW		 7548{
7549 int i;
542d6675 7550 for (i = 0; i < regdepslen; i++)
800eeca4 7551 {
197865e8 7552 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
800eeca4 7553 if ((bit & mask) != 0)
542d6675
KH		 7554 {
7555 regdeps[i].link_to_qp_branch = 0;
7556 }
800eeca4
JW		 7557 }
7558}
7559
197865e8 7560/* Remove any mutexes which contain any of the PRs indicated in the mask.
800eeca4 7561
542d6675
KH		 7562 Any changes to a PR clears the mutex relations which include that PR. */
7563
800eeca4
JW		 7564static void
7565clear_qp_mutex (mask)
542d6675 7566 valueT mask;
800eeca4
JW		 7567{
7568 int i;
7569
7570 i = 0;
7571 while (i < qp_mutexeslen)
7572 {
7573 if ((qp_mutexes[i].prmask & mask) != 0)
542d6675
KH		 7574 {
7575 if (md.debug_dv)
7576 {
7577 fprintf (stderr, " Clearing mutex relation");
7578 print_prmask (qp_mutexes[i].prmask);
7579 fprintf (stderr, "\n");
7580 }
7581 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
7582 }
800eeca4 7583 else
542d6675 7584 ++i;
800eeca4
JW		 7585 }
7586}
7587
7588/* Clear implies relations which contain PRs in the given masks.
7589 P1_MASK indicates the source of the implies relation, while P2_MASK
542d6675
KH		 7590 indicates the implied PR. */
7591
800eeca4
JW		 7592static void
7593clear_qp_implies (p1_mask, p2_mask)
542d6675
KH		 7594 valueT p1_mask;
7595 valueT p2_mask;
800eeca4
JW		 7596{
7597 int i;
7598
7599 i = 0;
7600 while (i < qp_implieslen)
7601 {
197865e8 7602 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
542d6675
KH		 7603 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
7604 {
7605 if (md.debug_dv)
7606 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
7607 qp_implies[i].p1, qp_implies[i].p2);
7608 qp_implies[i] = qp_implies[--qp_implieslen];
7609 }
197865e8 7610 else
542d6675 7611 ++i;
800eeca4
JW		 7612 }
7613}
7614
542d6675
KH		 7615/* Add the PRs specified to the list of implied relations. */
7616
800eeca4
JW		 7617static void
7618add_qp_imply (p1, p2)
542d6675 7619 int p1, p2;
800eeca4
JW		 7620{
7621 valueT mask;
7622 valueT bit;
7623 int i;
7624
542d6675 7625 /* p0 is not meaningful here. */
800eeca4
JW		 7626 if (p1 == 0 || p2 == 0)
7627 abort ();
7628
7629 if (p1 == p2)
7630 return;
7631
542d6675
KH		 7632 /* If it exists already, ignore it. */
7633 for (i = 0; i < qp_implieslen; i++)
800eeca4 7634 {
197865e8 7635 if (qp_implies[i].p1 == p1
542d6675
KH		 7636 && qp_implies[i].p2 == p2
7637 && qp_implies[i].path == md.path
7638 && !qp_implies[i].p2_branched)
7639 return;
800eeca4
JW		 7640 }
7641
7642 if (qp_implieslen == qp_impliestotlen)
7643 {
7644 qp_impliestotlen += 20;
7645 qp_implies = (struct qp_imply *)
542d6675
KH		 7646 xrealloc ((void *) qp_implies,
7647 qp_impliestotlen * sizeof (struct qp_imply));
800eeca4
JW		 7648 }
7649 if (md.debug_dv)
7650 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
7651 qp_implies[qp_implieslen].p1 = p1;
7652 qp_implies[qp_implieslen].p2 = p2;
7653 qp_implies[qp_implieslen].path = md.path;
7654 qp_implies[qp_implieslen++].p2_branched = 0;
7655
7656 /* Add in the implied transitive relations; for everything that p2 implies,
7657 make p1 imply that, too; for everything that implies p1, make it imply p2
197865e8 7658 as well. */
542d6675 7659 for (i = 0; i < qp_implieslen; i++)
800eeca4
JW		 7660 {
7661 if (qp_implies[i].p1 == p2)
542d6675 7662 add_qp_imply (p1, qp_implies[i].p2);
800eeca4 7663 if (qp_implies[i].p2 == p1)
542d6675 7664 add_qp_imply (qp_implies[i].p1, p2);
800eeca4
JW		 7665 }
7666 /* Add in mutex relations implied by this implies relation; for each mutex
197865e8
KH		 7667 relation containing p2, duplicate it and replace p2 with p1. */
7668 bit = (valueT) 1 << p1;
7669 mask = (valueT) 1 << p2;
542d6675 7670 for (i = 0; i < qp_mutexeslen; i++)
800eeca4
JW		 7671 {
7672 if (qp_mutexes[i].prmask & mask)
542d6675 7673 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
800eeca4
JW		 7674 }
7675}
7676
800eeca4
JW		 7677/* Add the PRs specified in the mask to the mutex list; this means that only
7678 one of the PRs can be true at any time. PR0 should never be included in
7679 the mask. */
542d6675 7680
800eeca4
JW		 7681static void
7682add_qp_mutex (mask)
542d6675 7683 valueT mask;
800eeca4
JW		 7684{
7685 if (mask & 0x1)
7686 abort ();
7687
7688 if (qp_mutexeslen == qp_mutexestotlen)
7689 {
7690 qp_mutexestotlen += 20;
7691 qp_mutexes = (struct qpmutex *)
542d6675
KH		 7692 xrealloc ((void *) qp_mutexes,
7693 qp_mutexestotlen * sizeof (struct qpmutex));
800eeca4
JW		 7694 }
7695 if (md.debug_dv)
7696 {
7697 fprintf (stderr, " Registering mutex on");
7698 print_prmask (mask);
7699 fprintf (stderr, "\n");
7700 }
7701 qp_mutexes[qp_mutexeslen].path = md.path;
7702 qp_mutexes[qp_mutexeslen++].prmask = mask;
7703}
7704
7705static void
7706clear_register_values ()
7707{
7708 int i;
7709 if (md.debug_dv)
7710 fprintf (stderr, " Clearing register values\n");
542d6675 7711 for (i = 1; i < NELEMS (gr_values); i++)
800eeca4
JW		 7712 gr_values[i].known = 0;
7713}
7714
7715/* Keep track of register values/changes which affect DV tracking.
7716
7717 optimization note: should add a flag to classes of insns where otherwise we
542d6675 7718 have to examine a group of strings to identify them. */
800eeca4 7719
800eeca4
JW		 7720static void
7721note_register_values (idesc)
542d6675 7722 struct ia64_opcode *idesc;
800eeca4
JW		 7723{
7724 valueT qp_changemask = 0;
7725 int i;
7726
542d6675
KH		 7727 /* Invalidate values for registers being written to. */
7728 for (i = 0; i < idesc->num_outputs; i++)
800eeca4 7729 {
197865e8 7730 if (idesc->operands[i] == IA64_OPND_R1
542d6675
KH		 7731 || idesc->operands[i] == IA64_OPND_R2
7732 || idesc->operands[i] == IA64_OPND_R3)
7733 {
7734 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7735 if (regno > 0 && regno < NELEMS (gr_values))
7736 gr_values[regno].known = 0;
7737 }
50b81f19
JW		 7738 else if (idesc->operands[i] == IA64_OPND_R3_2)
7739 {
7740 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7741 if (regno > 0 && regno < 4)
7742 gr_values[regno].known = 0;
7743 }
197865e8 7744 else if (idesc->operands[i] == IA64_OPND_P1
542d6675
KH		 7745 || idesc->operands[i] == IA64_OPND_P2)
7746 {
7747 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7748 qp_changemask |= (valueT) 1 << regno;
7749 }
800eeca4 7750 else if (idesc->operands[i] == IA64_OPND_PR)
542d6675
KH		 7751 {
7752 if (idesc->operands[2] & (valueT) 0x10000)
7753 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
7754 else
7755 qp_changemask = idesc->operands[2];
7756 break;
7757 }
800eeca4 7758 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
542d6675
KH		 7759 {
7760 if (idesc->operands[1] & ((valueT) 1 << 43))
7761 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
7762 else
7763 qp_changemask = idesc->operands[1];
7764 qp_changemask &= ~(valueT) 0xFFFF;
7765 break;
7766 }
7767 }
7768
7769 /* Always clear qp branch flags on any PR change. */
7770 /* FIXME there may be exceptions for certain compares. */
800eeca4
JW		 7771 clear_qp_branch_flag (qp_changemask);
7772
542d6675 7773 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
800eeca4
JW		 7774 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
7775 {
197865e8 7776 qp_changemask |= ~(valueT) 0xFFFF;
800eeca4 7777 if (strcmp (idesc->name, "clrrrb.pr") != 0)
542d6675
KH		 7778 {
7779 for (i = 32; i < 32 + md.rot.num_regs; i++)
7780 gr_values[i].known = 0;
7781 }
800eeca4
JW		 7782 clear_qp_mutex (qp_changemask);
7783 clear_qp_implies (qp_changemask, qp_changemask);
7784 }
542d6675
KH		 7785 /* After a call, all register values are undefined, except those marked
7786 as "safe". */
800eeca4 7787 else if (strncmp (idesc->name, "br.call", 6) == 0
542d6675 7788 || strncmp (idesc->name, "brl.call", 7) == 0)
800eeca4
JW		 7789 {
7790 // FIXME keep GR values which are marked as "safe_across_calls"
7791 clear_register_values ();
7792 clear_qp_mutex (~qp_safe_across_calls);
7793 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
7794 clear_qp_branch_flag (~qp_safe_across_calls);
7795 }
e9718fe1 7796 else if (is_interruption_or_rfi (idesc)
542d6675 7797 || is_taken_branch (idesc))
e9718fe1
TW		 7798 {
7799 clear_register_values ();
197865e8
KH		 7800 clear_qp_mutex (~(valueT) 0);
7801 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
e9718fe1 7802 }
542d6675 7803 /* Look for mutex and implies relations. */
197865e8 7804 else if ((idesc->operands[0] == IA64_OPND_P1
542d6675
KH		 7805 || idesc->operands[0] == IA64_OPND_P2)
7806 && (idesc->operands[1] == IA64_OPND_P1
7807 || idesc->operands[1] == IA64_OPND_P2))
800eeca4
JW		 7808 {
7809 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
197865e8
KH		 7810 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7811 valueT p1mask = (valueT) 1 << p1;
7812 valueT p2mask = (valueT) 1 << p2;
800eeca4 7813
542d6675 7814 /* If one of the PRs is PR0, we can't really do anything. */
800eeca4 7815 if (p1 == 0 || p2 == 0)
542d6675
KH		 7816 {
7817 if (md.debug_dv)
7818 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
7819 }
800eeca4 7820 /* In general, clear mutexes and implies which include P1 or P2,
542d6675 7821 with the following exceptions. */
800eeca4 7822 else if (strstr (idesc->name, ".or.andcm") != NULL)
542d6675
KH		 7823 {
7824 add_qp_mutex (p1mask | p2mask);
7825 clear_qp_implies (p2mask, p1mask);
7826 }
800eeca4 7827 else if (strstr (idesc->name, ".and.orcm") != NULL)
542d6675
KH		 7828 {
7829 add_qp_mutex (p1mask | p2mask);
7830 clear_qp_implies (p1mask, p2mask);
7831 }
800eeca4 7832 else if (strstr (idesc->name, ".and") != NULL)
542d6675
KH		 7833 {
7834 clear_qp_implies (0, p1mask | p2mask);
7835 }
800eeca4 7836 else if (strstr (idesc->name, ".or") != NULL)
542d6675
KH		 7837 {
7838 clear_qp_mutex (p1mask | p2mask);
7839 clear_qp_implies (p1mask | p2mask, 0);
7840 }
800eeca4 7841 else
542d6675
KH		 7842 {
7843 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
7844 if (strstr (idesc->name, ".unc") != NULL)
7845 {
7846 add_qp_mutex (p1mask | p2mask);
7847 if (CURR_SLOT.qp_regno != 0)
7848 {
7849 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
7850 CURR_SLOT.qp_regno);
7851 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
7852 CURR_SLOT.qp_regno);
7853 }
7854 }
7855 else if (CURR_SLOT.qp_regno == 0)
7856 {
7857 add_qp_mutex (p1mask | p2mask);
7858 }
7859 else
7860 {
7861 clear_qp_mutex (p1mask | p2mask);
7862 }
7863 }
7864 }
7865 /* Look for mov imm insns into GRs. */
800eeca4 7866 else if (idesc->operands[0] == IA64_OPND_R1
542d6675
KH		 7867 && (idesc->operands[1] == IA64_OPND_IMM22
7868 || idesc->operands[1] == IA64_OPND_IMMU64)
7869 && (strcmp (idesc->name, "mov") == 0
7870 || strcmp (idesc->name, "movl") == 0))
800eeca4
JW		 7871 {
7872 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
542d6675
KH		 7873 if (regno > 0 && regno < NELEMS (gr_values))
7874 {
7875 gr_values[regno].known = 1;
7876 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
7877 gr_values[regno].path = md.path;
7878 if (md.debug_dv)
7879 fprintf (stderr, " Know gr%d = 0x%llx\n",
7880 regno, gr_values[regno].value);
7881 }
800eeca4 7882 }
197865e8 7883 else
800eeca4
JW		 7884 {
7885 clear_qp_mutex (qp_changemask);
7886 clear_qp_implies (qp_changemask, qp_changemask);
7887 }
7888}
7889
542d6675
KH		 7890/* Return whether the given predicate registers are currently mutex. */
7891
800eeca4
JW		 7892static int
7893qp_mutex (p1, p2, path)
542d6675
KH		 7894 int p1;
7895 int p2;
7896 int path;
800eeca4
JW		 7897{
7898 int i;
7899 valueT mask;
7900
7901 if (p1 != p2)
7902 {
542d6675
KH		 7903 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
7904 for (i = 0; i < qp_mutexeslen; i++)
7905 {
7906 if (qp_mutexes[i].path >= path
7907 && (qp_mutexes[i].prmask & mask) == mask)
7908 return 1;
7909 }
800eeca4
JW		 7910 }
7911 return 0;
7912}
7913
7914/* Return whether the given resource is in the given insn's list of chks
7915 Return 1 if the conflict is absolutely determined, 2 if it's a potential
542d6675
KH		 7916 conflict. */
7917
800eeca4
JW		 7918static int
7919resources_match (rs, idesc, note, qp_regno, path)
542d6675
KH		 7920 struct rsrc *rs;
7921 struct ia64_opcode *idesc;
7922 int note;
7923 int qp_regno;
7924 int path;
800eeca4
JW		 7925{
7926 struct rsrc specs[MAX_SPECS];
7927 int count;
7928
7929 /* If the marked resource's qp_regno and the given qp_regno are mutex,
7930 we don't need to check. One exception is note 11, which indicates that
7931 target predicates are written regardless of PR[qp]. */
197865e8 7932 if (qp_mutex (rs->qp_regno, qp_regno, path)
800eeca4
JW		 7933 && note != 11)
7934 return 0;
7935
7936 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
7937 while (count-- > 0)
7938 {
7939 /* UNAT checking is a bit more specific than other resources */
7940 if (rs->dependency->specifier == IA64_RS_AR_UNAT
542d6675
KH		 7941 && specs[count].mem_offset.hint
7942 && rs->mem_offset.hint)
7943 {
7944 if (rs->mem_offset.base == specs[count].mem_offset.base)
7945 {
7946 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
7947 ((specs[count].mem_offset.offset >> 3) & 0x3F))
7948 return 1;
7949 else
7950 continue;
7951 }
7952 }
800eeca4
JW		 7953
7954 /* If either resource is not specific, conservatively assume a conflict
197865e8 7955 */
800eeca4 7956 if (!specs[count].specific || !rs->specific)
542d6675 7957 return 2;
800eeca4 7958 else if (specs[count].index == rs->index)
542d6675 7959 return 1;
800eeca4
JW		 7960 }
7961#if 0
7962 if (md.debug_dv)
7963 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
7964#endif
7965
7966 return 0;
7967}
7968
7969/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
7970 insert a stop to create the break. Update all resource dependencies
7971 appropriately. If QP_REGNO is non-zero, only apply the break to resources
7972 which use the same QP_REGNO and have the link_to_qp_branch flag set.
7973 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
542d6675 7974 instruction. */
800eeca4
JW		 7975
7976static void
7977insn_group_break (insert_stop, qp_regno, save_current)
542d6675
KH		 7978 int insert_stop;
7979 int qp_regno;
7980 int save_current;
800eeca4
JW		 7981{
7982 int i;
7983
7984 if (insert_stop && md.num_slots_in_use > 0)
7985 PREV_SLOT.end_of_insn_group = 1;
7986
7987 if (md.debug_dv)
7988 {
197865e8 7989 fprintf (stderr, " Insn group break%s",
542d6675 7990 (insert_stop ? " (w/stop)" : ""));
800eeca4 7991 if (qp_regno != 0)
542d6675 7992 fprintf (stderr, " effective for QP=%d", qp_regno);
800eeca4
JW		 7993 fprintf (stderr, "\n");
7994 }
7995
7996 i = 0;
7997 while (i < regdepslen)
7998 {
7999 const struct ia64_dependency *dep = regdeps[i].dependency;
8000
8001 if (qp_regno != 0
542d6675
KH		 8002 && regdeps[i].qp_regno != qp_regno)
8003 {
8004 ++i;
8005 continue;
8006 }
800eeca4
JW		 8007
8008 if (save_current
542d6675
KH		 8009 && CURR_SLOT.src_file == regdeps[i].file
8010 && CURR_SLOT.src_line == regdeps[i].line)
8011 {
8012 ++i;
8013 continue;
8014 }
800eeca4
JW		 8015
8016 /* clear dependencies which are automatically cleared by a stop, or
542d6675 8017 those that have reached the appropriate state of insn serialization */
800eeca4 8018 if (dep->semantics == IA64_DVS_IMPLIED
542d6675
KH		 8019 || dep->semantics == IA64_DVS_IMPLIEDF
8020 || regdeps[i].insn_srlz == STATE_SRLZ)
8021 {
8022 print_dependency ("Removing", i);
8023 regdeps[i] = regdeps[--regdepslen];
8024 }
800eeca4 8025 else
542d6675
KH		 8026 {
8027 if (dep->semantics == IA64_DVS_DATA
8028 || dep->semantics == IA64_DVS_INSTR
800eeca4 8029 || dep->semantics == IA64_DVS_SPECIFIC)
542d6675
KH		 8030 {
8031 if (regdeps[i].insn_srlz == STATE_NONE)
8032 regdeps[i].insn_srlz = STATE_STOP;
8033 if (regdeps[i].data_srlz == STATE_NONE)
8034 regdeps[i].data_srlz = STATE_STOP;
8035 }
8036 ++i;
8037 }
800eeca4
JW		 8038 }
8039}
8040
542d6675
KH		 8041/* Add the given resource usage spec to the list of active dependencies. */
8042
197865e8 8043static void
800eeca4 8044mark_resource (idesc, dep, spec, depind, path)
542d6675
KH		 8045 struct ia64_opcode *idesc;
8046 const struct ia64_dependency *dep;
8047 struct rsrc *spec;
8048 int depind;
8049 int path;
800eeca4
JW		 8050{
8051 if (regdepslen == regdepstotlen)
8052 {
8053 regdepstotlen += 20;
8054 regdeps = (struct rsrc *)
542d6675
KH		 8055 xrealloc ((void *) regdeps,
8056 regdepstotlen * sizeof(struct rsrc));
800eeca4
JW		 8057 }
8058
8059 regdeps[regdepslen] = *spec;
8060 regdeps[regdepslen].depind = depind;
8061 regdeps[regdepslen].path = path;
8062 regdeps[regdepslen].file = CURR_SLOT.src_file;
8063 regdeps[regdepslen].line = CURR_SLOT.src_line;
8064
8065 print_dependency ("Adding", regdepslen);
8066
8067 ++regdepslen;
8068}
8069
8070static void
8071print_dependency (action, depind)
542d6675
KH		 8072 const char *action;
8073 int depind;
800eeca4
JW		 8074{
8075 if (md.debug_dv)
8076 {
197865e8 8077 fprintf (stderr, " %s %s '%s'",
542d6675
KH		 8078 action, dv_mode[(regdeps[depind].dependency)->mode],
8079 (regdeps[depind].dependency)->name);
800eeca4 8080 if (regdeps[depind].specific && regdeps[depind].index != 0)
542d6675 8081 fprintf (stderr, " (%d)", regdeps[depind].index);
800eeca4 8082 if (regdeps[depind].mem_offset.hint)
542d6675
KH		 8083 fprintf (stderr, " 0x%llx+0x%llx",
8084 regdeps[depind].mem_offset.base,
8085 regdeps[depind].mem_offset.offset);
800eeca4
JW		 8086 fprintf (stderr, "\n");
8087 }
8088}
8089
8090static void
8091instruction_serialization ()
8092{
8093 int i;
8094 if (md.debug_dv)
8095 fprintf (stderr, " Instruction serialization\n");
542d6675 8096 for (i = 0; i < regdepslen; i++)
800eeca4
JW		 8097 if (regdeps[i].insn_srlz == STATE_STOP)
8098 regdeps[i].insn_srlz = STATE_SRLZ;
8099}
8100
8101static void
8102data_serialization ()
8103{
8104 int i = 0;
8105 if (md.debug_dv)
8106 fprintf (stderr, " Data serialization\n");
8107 while (i < regdepslen)
8108 {
8109 if (regdeps[i].data_srlz == STATE_STOP
542d6675
KH		 8110 /* Note: as of 991210, all "other" dependencies are cleared by a
8111 data serialization. This might change with new tables */
8112 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8113 {
8114 print_dependency ("Removing", i);
8115 regdeps[i] = regdeps[--regdepslen];
8116 }
800eeca4 8117 else
542d6675 8118 ++i;
800eeca4
JW		 8119 }
8120}
8121
542d6675
KH		 8122/* Insert stops and serializations as needed to avoid DVs. */
8123
800eeca4
JW		 8124static void
8125remove_marked_resource (rs)
542d6675 8126 struct rsrc *rs;
800eeca4
JW		 8127{
8128 switch (rs->dependency->semantics)
8129 {
8130 case IA64_DVS_SPECIFIC:
8131 if (md.debug_dv)
8132 fprintf (stderr, "Implementation-specific, assume worst case...\n");
197865e8 8133 /* ...fall through... */
800eeca4
JW		 8134 case IA64_DVS_INSTR:
8135 if (md.debug_dv)
542d6675 8136 fprintf (stderr, "Inserting instr serialization\n");
800eeca4 8137 if (rs->insn_srlz < STATE_STOP)
542d6675 8138 insn_group_break (1, 0, 0);
800eeca4 8139 if (rs->insn_srlz < STATE_SRLZ)
542d6675
KH		 8140 {
8141 int oldqp = CURR_SLOT.qp_regno;
8142 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8143 /* Manually jam a srlz.i insn into the stream */
8144 CURR_SLOT.qp_regno = 0;
8145 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8146 instruction_serialization ();
8147 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8148 if (++md.num_slots_in_use >= NUM_SLOTS)
8149 emit_one_bundle ();
8150 CURR_SLOT.qp_regno = oldqp;
8151 CURR_SLOT.idesc = oldidesc;
8152 }
800eeca4
JW		 8153 insn_group_break (1, 0, 0);
8154 break;
8155 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
542d6675
KH		 8156 "other" types of DV are eliminated
8157 by a data serialization */
800eeca4
JW		 8158 case IA64_DVS_DATA:
8159 if (md.debug_dv)
542d6675 8160 fprintf (stderr, "Inserting data serialization\n");
800eeca4 8161 if (rs->data_srlz < STATE_STOP)
542d6675 8162 insn_group_break (1, 0, 0);
800eeca4 8163 {
542d6675
KH		 8164 int oldqp = CURR_SLOT.qp_regno;
8165 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8166 /* Manually jam a srlz.d insn into the stream */
8167 CURR_SLOT.qp_regno = 0;
8168 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8169 data_serialization ();
8170 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8171 if (++md.num_slots_in_use >= NUM_SLOTS)
8172 emit_one_bundle ();
8173 CURR_SLOT.qp_regno = oldqp;
8174 CURR_SLOT.idesc = oldidesc;
800eeca4
JW		 8175 }
8176 break;
8177 case IA64_DVS_IMPLIED:
8178 case IA64_DVS_IMPLIEDF:
8179 if (md.debug_dv)
542d6675 8180 fprintf (stderr, "Inserting stop\n");
800eeca4
JW		 8181 insn_group_break (1, 0, 0);
8182 break;
8183 default:
8184 break;
8185 }
8186}
8187
8188/* Check the resources used by the given opcode against the current dependency
197865e8 8189 list.
800eeca4
JW		 8190
8191 The check is run once for each execution path encountered. In this case,
8192 a unique execution path is the sequence of instructions following a code
8193 entry point, e.g. the following has three execution paths, one starting
8194 at L0, one at L1, and one at L2.
197865e8 8195
800eeca4
JW		 8196 L0: nop
8197 L1: add
8198 L2: add
197865e8 8199 br.ret
800eeca4 8200*/
542d6675 8201
800eeca4
JW		 8202static void
8203check_dependencies (idesc)
542d6675 8204 struct ia64_opcode *idesc;
800eeca4
JW		 8205{
8206 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8207 int path;
8208 int i;
8209
8210 /* Note that the number of marked resources may change within the
197865e8 8211 loop if in auto mode. */
800eeca4
JW		 8212 i = 0;
8213 while (i < regdepslen)
8214 {
8215 struct rsrc *rs = &regdeps[i];
8216 const struct ia64_dependency *dep = rs->dependency;
8217 int chkind;
8218 int note;
8219 int start_over = 0;
8220
8221 if (dep->semantics == IA64_DVS_NONE
542d6675
KH		 8222 || (chkind = depends_on (rs->depind, idesc)) == -1)
8223 {
8224 ++i;
8225 continue;
8226 }
8227
8228 note = NOTE (opdeps->chks[chkind]);
8229
8230 /* Check this resource against each execution path seen thus far. */
8231 for (path = 0; path <= md.path; path++)
8232 {
8233 int matchtype;
8234
8235 /* If the dependency wasn't on the path being checked, ignore it. */
8236 if (rs->path < path)
8237 continue;
8238
8239 /* If the QP for this insn implies a QP which has branched, don't
8240 bother checking. Ed. NOTE: I don't think this check is terribly
8241 useful; what's the point of generating code which will only be
8242 reached if its QP is zero?
8243 This code was specifically inserted to handle the following code,
8244 based on notes from Intel's DV checking code, where p1 implies p2.
8245
8246 mov r4 = 2
8247 (p2) br.cond L
8248 (p1) mov r4 = 7
8249 */
8250 if (CURR_SLOT.qp_regno != 0)
8251 {
8252 int skip = 0;
8253 int implies;
8254 for (implies = 0; implies < qp_implieslen; implies++)
8255 {
8256 if (qp_implies[implies].path >= path
8257 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8258 && qp_implies[implies].p2_branched)
8259 {
8260 skip = 1;
8261 break;
8262 }
8263 }
8264 if (skip)
8265 continue;
8266 }
8267
8268 if ((matchtype = resources_match (rs, idesc, note,
8269 CURR_SLOT.qp_regno, path)) != 0)
8270 {
8271 char msg[1024];
8272 char pathmsg[256] = "";
8273 char indexmsg[256] = "";
8274 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8275
8276 if (path != 0)
8277 sprintf (pathmsg, " when entry is at label '%s'",
8278 md.entry_labels[path - 1]);
8279 if (rs->specific && rs->index != 0)
8280 sprintf (indexmsg, ", specific resource number is %d",
8281 rs->index);
8282 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8283 idesc->name,
8284 (certain ? "violates" : "may violate"),
8285 dv_mode[dep->mode], dep->name,
8286 dv_sem[dep->semantics],
8287 pathmsg, indexmsg);
8288
8289 if (md.explicit_mode)
8290 {
8291 as_warn ("%s", msg);
8292 if (path < md.path)
8293 as_warn (_("Only the first path encountering the conflict "
8294 "is reported"));
8295 as_warn_where (rs->file, rs->line,
8296 _("This is the location of the "
8297 "conflicting usage"));
8298 /* Don't bother checking other paths, to avoid duplicating
8299 the same warning */
8300 break;
8301 }
8302 else
8303 {
8304 if (md.debug_dv)
8305 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
8306
8307 remove_marked_resource (rs);
8308
8309 /* since the set of dependencies has changed, start over */
8310 /* FIXME -- since we're removing dvs as we go, we
8311 probably don't really need to start over... */
8312 start_over = 1;
8313 break;
8314 }
8315 }
8316 }
800eeca4 8317 if (start_over)
542d6675 8318 i = 0;
800eeca4 8319 else
542d6675 8320 ++i;
800eeca4
JW		 8321 }
8322}
8323
542d6675
KH		 8324/* Register new dependencies based on the given opcode. */
8325
800eeca4
JW		 8326static void
8327mark_resources (idesc)
542d6675 8328 struct ia64_opcode *idesc;
800eeca4
JW		 8329{
8330 int i;
8331 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8332 int add_only_qp_reads = 0;
8333
8334 /* A conditional branch only uses its resources if it is taken; if it is
8335 taken, we stop following that path. The other branch types effectively
8336 *always* write their resources. If it's not taken, register only QP
197865e8 8337 reads. */
800eeca4
JW		 8338 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8339 {
8340 add_only_qp_reads = 1;
8341 }
8342
8343 if (md.debug_dv)
8344 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8345
542d6675 8346 for (i = 0; i < opdeps->nregs; i++)
800eeca4
JW		 8347 {
8348 const struct ia64_dependency *dep;
8349 struct rsrc specs[MAX_SPECS];
8350 int note;
8351 int path;
8352 int count;
197865e8 8353
800eeca4 8354 dep = ia64_find_dependency (opdeps->regs[i]);
542d6675 8355 note = NOTE (opdeps->regs[i]);
800eeca4
JW		 8356
8357 if (add_only_qp_reads
542d6675
KH		 8358 && !(dep->mode == IA64_DV_WAR
8359 && (dep->specifier == IA64_RS_PR
8360 || dep->specifier == IA64_RS_PR63)))
8361 continue;
800eeca4
JW		 8362
8363 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8364
8365#if 0
8366 if (md.debug_dv && !count)
542d6675
KH		 8367 fprintf (stderr, " No %s %s usage found (path %d)\n",
8368 dv_mode[dep->mode], dep->name, md.path);
800eeca4 8369#endif
197865e8 8370
800eeca4 8371 while (count-- > 0)
542d6675
KH		 8372 {
8373 mark_resource (idesc, dep, &specs[count],
8374 DEP (opdeps->regs[i]), md.path);
8375 }
800eeca4
JW		 8376
8377 /* The execution path may affect register values, which may in turn
542d6675 8378 affect which indirect-access resources are accessed. */
800eeca4 8379 switch (dep->specifier)
542d6675
KH		 8380 {
8381 default:
8382 break;
8383 case IA64_RS_CPUID:
8384 case IA64_RS_DBR:
8385 case IA64_RS_IBR:
800eeca4 8386 case IA64_RS_MSR:
542d6675
KH		 8387 case IA64_RS_PKR:
8388 case IA64_RS_PMC:
8389 case IA64_RS_PMD:
8390 case IA64_RS_RR:
8391 for (path = 0; path < md.path; path++)
8392 {
8393 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8394 while (count-- > 0)
8395 mark_resource (idesc, dep, &specs[count],
8396 DEP (opdeps->regs[i]), path);
8397 }
8398 break;
8399 }
8400 }
8401}
8402
8403/* Remove dependencies when they no longer apply. */
8404
800eeca4
JW		 8405static void
8406update_dependencies (idesc)
542d6675 8407 struct ia64_opcode *idesc;
800eeca4
JW		 8408{
8409 int i;
8410
8411 if (strcmp (idesc->name, "srlz.i") == 0)
8412 {
8413 instruction_serialization ();
8414 }
8415 else if (strcmp (idesc->name, "srlz.d") == 0)
8416 {
8417 data_serialization ();
8418 }
8419 else if (is_interruption_or_rfi (idesc)
542d6675 8420 || is_taken_branch (idesc))
800eeca4 8421 {
542d6675
KH		 8422 /* Although technically the taken branch doesn't clear dependencies
8423 which require a srlz.[id], we don't follow the branch; the next
8424 instruction is assumed to start with a clean slate. */
800eeca4 8425 regdepslen = 0;
800eeca4
JW		 8426 md.path = 0;
8427 }
8428 else if (is_conditional_branch (idesc)
542d6675 8429 && CURR_SLOT.qp_regno != 0)
800eeca4
JW		 8430 {
8431 int is_call = strstr (idesc->name, ".call") != NULL;
8432
542d6675
KH		 8433 for (i = 0; i < qp_implieslen; i++)
8434 {
8435 /* If the conditional branch's predicate is implied by the predicate
8436 in an existing dependency, remove that dependency. */
8437 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8438 {
8439 int depind = 0;
8440 /* Note that this implied predicate takes a branch so that if
8441 a later insn generates a DV but its predicate implies this
8442 one, we can avoid the false DV warning. */
8443 qp_implies[i].p2_branched = 1;
8444 while (depind < regdepslen)
8445 {
8446 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8447 {
8448 print_dependency ("Removing", depind);
8449 regdeps[depind] = regdeps[--regdepslen];
8450 }
8451 else
8452 ++depind;
8453 }
8454 }
8455 }
800eeca4 8456 /* Any marked resources which have this same predicate should be
542d6675
KH		 8457 cleared, provided that the QP hasn't been modified between the
8458 marking instruction and the branch. */
800eeca4 8459 if (is_call)
542d6675
KH		 8460 {
8461 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8462 }
800eeca4 8463 else
542d6675
KH		 8464 {
8465 i = 0;
8466 while (i < regdepslen)
8467 {
8468 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8469 && regdeps[i].link_to_qp_branch
8470 && (regdeps[i].file != CURR_SLOT.src_file
8471 || regdeps[i].line != CURR_SLOT.src_line))
8472 {
8473 /* Treat like a taken branch */
8474 print_dependency ("Removing", i);
8475 regdeps[i] = regdeps[--regdepslen];
8476 }
8477 else
8478 ++i;
8479 }
8480 }
800eeca4
JW		 8481 }
8482}
8483
8484/* Examine the current instruction for dependency violations. */
542d6675 8485
800eeca4
JW		 8486static int
8487check_dv (idesc)
542d6675 8488 struct ia64_opcode *idesc;
800eeca4
JW		 8489{
8490 if (md.debug_dv)
8491 {
197865e8 8492 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
542d6675
KH		 8493 idesc->name, CURR_SLOT.src_line,
8494 idesc->dependencies->nchks,
8495 idesc->dependencies->nregs);
800eeca4
JW		 8496 }
8497
197865e8 8498 /* Look through the list of currently marked resources; if the current
800eeca4 8499 instruction has the dependency in its chks list which uses that resource,
542d6675 8500 check against the specific resources used. */
800eeca4
JW		 8501 check_dependencies (idesc);
8502
542d6675
KH		 8503 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8504 then add them to the list of marked resources. */
800eeca4
JW		 8505 mark_resources (idesc);
8506
8507 /* There are several types of dependency semantics, and each has its own
197865e8
KH		 8508 requirements for being cleared
8509
800eeca4
JW		 8510 Instruction serialization (insns separated by interruption, rfi, or
8511 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8512
8513 Data serialization (instruction serialization, or writer + srlz.d +
8514 reader, where writer and srlz.d are in separate groups) clears
8515 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8516 always be the case).
8517
8518 Instruction group break (groups separated by stop, taken branch,
8519 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8520 */
8521 update_dependencies (idesc);
8522
8523 /* Sometimes, knowing a register value allows us to avoid giving a false DV
197865e8 8524 warning. Keep track of as many as possible that are useful. */
800eeca4
JW		 8525 note_register_values (idesc);
8526
197865e8 8527 /* We don't need or want this anymore. */
800eeca4
JW		 8528 md.mem_offset.hint = 0;
8529
8530 return 0;
8531}
8532
8533/* Translate one line of assembly. Pseudo ops and labels do not show
8534 here. */
8535void
8536md_assemble (str)
8537 char *str;
8538{
8539 char *saved_input_line_pointer, *mnemonic;
8540 const struct pseudo_opcode *pdesc;
8541 struct ia64_opcode *idesc;
8542 unsigned char qp_regno;
8543 unsigned int flags;
8544 int ch;
8545
8546 saved_input_line_pointer = input_line_pointer;
8547 input_line_pointer = str;
8548
542d6675 8549 /* extract the opcode (mnemonic): */
800eeca4
JW		 8550
8551 mnemonic = input_line_pointer;
8552 ch = get_symbol_end ();
8553 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
8554 if (pdesc)
8555 {
8556 *input_line_pointer = ch;
8557 (*pdesc->handler) (pdesc->arg);
8558 goto done;
8559 }
8560
542d6675 8561 /* Find the instruction descriptor matching the arguments. */
800eeca4
JW		 8562
8563 idesc = ia64_find_opcode (mnemonic);
8564 *input_line_pointer = ch;
8565 if (!idesc)
8566 {
8567 as_bad ("Unknown opcode `%s'", mnemonic);
8568 goto done;
8569 }
8570
8571 idesc = parse_operands (idesc);
8572 if (!idesc)
8573 goto done;
8574
542d6675 8575 /* Handle the dynamic ops we can handle now: */
800eeca4
JW		 8576 if (idesc->type == IA64_TYPE_DYN)
8577 {
8578 if (strcmp (idesc->name, "add") == 0)
8579 {
8580 if (CURR_SLOT.opnd[2].X_op == O_register
8581 && CURR_SLOT.opnd[2].X_add_number < 4)
8582 mnemonic = "addl";
8583 else
8584 mnemonic = "adds";
3d56ab85 8585 ia64_free_opcode (idesc);
800eeca4
JW		 8586 idesc = ia64_find_opcode (mnemonic);
8587#if 0
8588 know (!idesc->next);
8589#endif
8590 }
8591 else if (strcmp (idesc->name, "mov") == 0)
8592 {
8593 enum ia64_opnd opnd1, opnd2;
8594 int rop;
8595
8596 opnd1 = idesc->operands[0];
8597 opnd2 = idesc->operands[1];
8598 if (opnd1 == IA64_OPND_AR3)
8599 rop = 0;
8600 else if (opnd2 == IA64_OPND_AR3)
8601 rop = 1;
8602 else
8603 abort ();
8604 if (CURR_SLOT.opnd[rop].X_op == O_register
8605 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
8606 mnemonic = "mov.i";
8607 else
8608 mnemonic = "mov.m";
3d56ab85 8609 ia64_free_opcode (idesc);
800eeca4
JW		 8610 idesc = ia64_find_opcode (mnemonic);
8611 while (idesc != NULL
8612 && (idesc->operands[0] != opnd1
8613 || idesc->operands[1] != opnd2))
8614 idesc = get_next_opcode (idesc);
8615 }
8616 }
8617
8618 qp_regno = 0;
8619 if (md.qp.X_op == O_register)
8620 qp_regno = md.qp.X_add_number - REG_P;
8621
8622 flags = idesc->flags;
8623
8624 if ((flags & IA64_OPCODE_FIRST) != 0)
8625 insn_group_break (1, 0, 0);
8626
8627 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
8628 {
8629 as_bad ("`%s' cannot be predicated", idesc->name);
8630 goto done;
8631 }
8632
542d6675 8633 /* Build the instruction. */
800eeca4
JW		 8634 CURR_SLOT.qp_regno = qp_regno;
8635 CURR_SLOT.idesc = idesc;
8636 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
8637 if (debug_type == DEBUG_DWARF2)
8638 dwarf2_where (&CURR_SLOT.debug_line);
8639
8640 /* Add unwind entry, if there is one. */
e0c9811a 8641 if (unwind.current_entry)
800eeca4 8642 {
e0c9811a
JW		 8643 CURR_SLOT.unwind_record = unwind.current_entry;
8644 unwind.current_entry = NULL;
800eeca4
JW		 8645 }
8646
542d6675 8647 /* Check for dependency violations. */
800eeca4 8648 if (md.detect_dv)
542d6675 8649 check_dv (idesc);
800eeca4
JW		 8650
8651 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8652 if (++md.num_slots_in_use >= NUM_SLOTS)
8653 emit_one_bundle ();
8654
8655 if ((flags & IA64_OPCODE_LAST) != 0)
8656 insn_group_break (1, 0, 0);
8657
8658 md.last_text_seg = now_seg;
8659
8660 done:
8661 input_line_pointer = saved_input_line_pointer;
8662}
8663
8664/* Called when symbol NAME cannot be found in the symbol table.
8665 Should be used for dynamic valued symbols only. */
542d6675
KH		 8666
8667symbolS *
800eeca4
JW		 8668md_undefined_symbol (name)
8669 char *name;
8670{
8671 return 0;
8672}
8673
8674/* Called for any expression that can not be recognized. When the
8675 function is called, `input_line_pointer' will point to the start of
8676 the expression. */
542d6675 8677
800eeca4
JW		 8678void
8679md_operand (e)
8680 expressionS *e;
8681{
8682 enum pseudo_type pseudo_type;
e0c9811a 8683 const char *name;
800eeca4
JW		 8684 size_t len;
8685 int ch, i;
8686
8687 switch (*input_line_pointer)
8688 {
8689 case '@':
542d6675 8690 /* Find what relocation pseudo-function we're dealing with. */
800eeca4
JW		 8691 pseudo_type = 0;
8692 ch = *++input_line_pointer;
8693 for (i = 0; i < NELEMS (pseudo_func); ++i)
8694 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
8695 {
8696 len = strlen (pseudo_func[i].name);
8697 if (strncmp (pseudo_func[i].name + 1,
8698 input_line_pointer + 1, len - 1) == 0
8699 && !is_part_of_name (input_line_pointer[len]))
8700 {
8701 input_line_pointer += len;
8702 pseudo_type = pseudo_func[i].type;
8703 break;
8704 }
8705 }
8706 switch (pseudo_type)
8707 {
8708 case PSEUDO_FUNC_RELOC:
8709 SKIP_WHITESPACE ();
8710 if (*input_line_pointer != '(')
8711 {
8712 as_bad ("Expected '('");
8713 goto err;
8714 }
542d6675
KH		 8715 /* Skip '('. */
8716 ++input_line_pointer;
800eeca4
JW		 8717 expression (e);
8718 if (*input_line_pointer++ != ')')
8719 {
8720 as_bad ("Missing ')'");
8721 goto err;
8722 }
8723 if (e->X_op != O_symbol)
8724 {
8725 if (e->X_op != O_pseudo_fixup)
8726 {
8727 as_bad ("Not a symbolic expression");
8728 goto err;
8729 }
8730 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
8731 && i == FUNC_LT_RELATIVE)
8732 i = FUNC_LT_FPTR_RELATIVE;
8733 else
8734 {
8735 as_bad ("Illegal combination of relocation functions");
8736 goto err;
8737 }
8738 }
542d6675
KH		 8739 /* Make sure gas doesn't get rid of local symbols that are used
8740 in relocs. */
800eeca4
JW		 8741 e->X_op = O_pseudo_fixup;
8742 e->X_op_symbol = pseudo_func[i].u.sym;
8743 break;
8744
8745 case PSEUDO_FUNC_CONST:
8746 e->X_op = O_constant;
8747 e->X_add_number = pseudo_func[i].u.ival;
8748 break;
8749
e0c9811a
JW		 8750 case PSEUDO_FUNC_REG:
8751 e->X_op = O_register;
8752 e->X_add_number = pseudo_func[i].u.ival;
8753 break;
8754
800eeca4 8755 default:
e0c9811a
JW		 8756 name = input_line_pointer - 1;
8757 get_symbol_end ();
8758 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW		 8759 goto err;
8760 }
8761 break;
8762
8763 case '[':
8764 ++input_line_pointer;
8765 expression (e);
8766 if (*input_line_pointer != ']')
8767 {
8768 as_bad ("Closing bracket misssing");
8769 goto err;
8770 }
8771 else
8772 {
8773 if (e->X_op != O_register)
8774 as_bad ("Register expected as index");
8775
8776 ++input_line_pointer;
8777 e->X_op = O_index;
8778 }
8779 break;
8780
8781 default:
8782 break;
8783 }
8784 return;
8785
8786 err:
8787 ignore_rest_of_line ();
8788}
8789
8790/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8791 a section symbol plus some offset. For relocs involving @fptr(),
8792 directives we don't want such adjustments since we need to have the
8793 original symbol's name in the reloc. */
8794int
8795ia64_fix_adjustable (fix)
8796 fixS *fix;
8797{
8798 /* Prevent all adjustments to global symbols */
8799 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
8800 return 0;
8801
8802 switch (fix->fx_r_type)
8803 {
8804 case BFD_RELOC_IA64_FPTR64I:
8805 case BFD_RELOC_IA64_FPTR32MSB:
8806 case BFD_RELOC_IA64_FPTR32LSB:
8807 case BFD_RELOC_IA64_FPTR64MSB:
8808 case BFD_RELOC_IA64_FPTR64LSB:
8809 case BFD_RELOC_IA64_LTOFF_FPTR22:
8810 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8811 return 0;
8812 default:
8813 break;
8814 }
8815
8816 return 1;
8817}
8818
8819int
8820ia64_force_relocation (fix)
8821 fixS *fix;
8822{
8823 switch (fix->fx_r_type)
8824 {
8825 case BFD_RELOC_IA64_FPTR64I:
8826 case BFD_RELOC_IA64_FPTR32MSB:
8827 case BFD_RELOC_IA64_FPTR32LSB:
8828 case BFD_RELOC_IA64_FPTR64MSB:
8829 case BFD_RELOC_IA64_FPTR64LSB:
8830
8831 case BFD_RELOC_IA64_LTOFF22:
8832 case BFD_RELOC_IA64_LTOFF64I:
8833 case BFD_RELOC_IA64_LTOFF_FPTR22:
8834 case BFD_RELOC_IA64_LTOFF_FPTR64I:
8835 case BFD_RELOC_IA64_PLTOFF22:
8836 case BFD_RELOC_IA64_PLTOFF64I:
8837 case BFD_RELOC_IA64_PLTOFF64MSB:
8838 case BFD_RELOC_IA64_PLTOFF64LSB:
8839 return 1;
8840
8841 default:
8842 return 0;
8843 }
8844 return 0;
8845}
8846
8847/* Decide from what point a pc-relative relocation is relative to,
8848 relative to the pc-relative fixup. Er, relatively speaking. */
8849long
8850ia64_pcrel_from_section (fix, sec)
8851 fixS *fix;
8852 segT sec;
8853{
8854 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
197865e8 8855
800eeca4
JW		 8856 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
8857 off &= ~0xfUL;
8858
8859 return off;
8860}
8861
8862/* This is called whenever some data item (not an instruction) needs a
8863 fixup. We pick the right reloc code depending on the byteorder
8864 currently in effect. */
8865void
8866ia64_cons_fix_new (f, where, nbytes, exp)
8867 fragS *f;
8868 int where;
8869 int nbytes;
8870 expressionS *exp;
8871{
8872 bfd_reloc_code_real_type code;
8873 fixS *fix;
8874
8875 switch (nbytes)
8876 {
8877 /* There are no reloc for 8 and 16 bit quantities, but we allow
8878 them here since they will work fine as long as the expression
8879 is fully defined at the end of the pass over the source file. */
8880 case 1: code = BFD_RELOC_8; break;
8881 case 2: code = BFD_RELOC_16; break;
8882 case 4:
8883 if (target_big_endian)
8884 code = BFD_RELOC_IA64_DIR32MSB;
8885 else
8886 code = BFD_RELOC_IA64_DIR32LSB;
8887 break;
8888
8889 case 8:
8890 if (target_big_endian)
8891 code = BFD_RELOC_IA64_DIR64MSB;
8892 else
8893 code = BFD_RELOC_IA64_DIR64LSB;
8894 break;
8895
8896 default:
8897 as_bad ("Unsupported fixup size %d", nbytes);
8898 ignore_rest_of_line ();
8899 return;
8900 }
8901 if (exp->X_op == O_pseudo_fixup)
8902 {
8903 /* ??? */
8904 exp->X_op = O_symbol;
8905 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
8906 }
8907 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
8908 /* We need to store the byte order in effect in case we're going
8909 to fix an 8 or 16 bit relocation (for which there no real
8910 relocs available). See md_apply_fix(). */
8911 fix->tc_fix_data.bigendian = target_big_endian;
8912}
8913
8914/* Return the actual relocation we wish to associate with the pseudo
8915 reloc described by SYM and R_TYPE. SYM should be one of the
197865e8 8916 symbols in the pseudo_func array, or NULL. */
800eeca4
JW		 8917
8918static bfd_reloc_code_real_type
8919ia64_gen_real_reloc_type (sym, r_type)
8920 struct symbol *sym;
8921 bfd_reloc_code_real_type r_type;
8922{
8923 bfd_reloc_code_real_type new = 0;
8924
8925 if (sym == NULL)
8926 {
8927 return r_type;
8928 }
8929
8930 switch (S_GET_VALUE (sym))
8931 {
8932 case FUNC_FPTR_RELATIVE:
8933 switch (r_type)
8934 {
8935 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
8936 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
8937 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
8938 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
8939 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
8940 default: break;
8941 }
8942 break;
8943
8944 case FUNC_GP_RELATIVE:
8945 switch (r_type)
8946 {
8947 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
8948 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
8949 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
8950 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
8951 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
8952 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
8953 default: break;
8954 }
8955 break;
8956
8957 case FUNC_LT_RELATIVE:
8958 switch (r_type)
8959 {
8960 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
8961 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
8962 default: break;
8963 }
8964 break;
8965
c67e42c9
RH		 8966 case FUNC_PC_RELATIVE:
8967 switch (r_type)
8968 {
8969 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
8970 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
8971 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
8972 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
8973 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
8974 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
8975 default: break;
8976 }
8977 break;
8978
800eeca4
JW		 8979 case FUNC_PLT_RELATIVE:
8980 switch (r_type)
8981 {
8982 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
8983 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
8984 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
8985 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
8986 default: break;
8987 }
8988 break;
8989
8990 case FUNC_SEC_RELATIVE:
8991 switch (r_type)
8992 {
8993 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
8994 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
8995 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
8996 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
8997 default: break;
8998 }
8999 break;
9000
9001 case FUNC_SEG_RELATIVE:
9002 switch (r_type)
9003 {
9004 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
9005 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
9006 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
9007 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
9008 default: break;
9009 }
9010 break;
9011
9012 case FUNC_LTV_RELATIVE:
9013 switch (r_type)
9014 {
9015 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
9016 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
9017 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
9018 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
9019 default: break;
9020 }
9021 break;
9022
9023 case FUNC_LT_FPTR_RELATIVE:
9024 switch (r_type)
9025 {
9026 case BFD_RELOC_IA64_IMM22:
9027 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9028 case BFD_RELOC_IA64_IMM64:
9029 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9030 default:
9031 break;
9032 }
9033 break;
9034 default:
9035 abort ();
9036 }
9037 /* Hmmmm. Should this ever occur? */
9038 if (new)
9039 return new;
9040 else
9041 return r_type;
9042}
9043
9044/* Here is where generate the appropriate reloc for pseudo relocation
9045 functions. */
9046void
9047ia64_validate_fix (fix)
9048 fixS *fix;
9049{
9050 switch (fix->fx_r_type)
9051 {
9052 case BFD_RELOC_IA64_FPTR64I:
9053 case BFD_RELOC_IA64_FPTR32MSB:
9054 case BFD_RELOC_IA64_FPTR64LSB:
9055 case BFD_RELOC_IA64_LTOFF_FPTR22:
9056 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9057 if (fix->fx_offset != 0)
9058 as_bad_where (fix->fx_file, fix->fx_line,
9059 "No addend allowed in @fptr() relocation");
9060 break;
9061 default:
9062 break;
9063 }
9064
9065 return;
9066}
9067
9068static void
9069fix_insn (fix, odesc, value)
9070 fixS *fix;
9071 const struct ia64_operand *odesc;
9072 valueT value;
9073{
9074 bfd_vma insn[3], t0, t1, control_bits;
9075 const char *err;
9076 char *fixpos;
9077 long slot;
9078
9079 slot = fix->fx_where & 0x3;
9080 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9081
c67e42c9 9082 /* Bundles are always in little-endian byte order */
800eeca4
JW		 9083 t0 = bfd_getl64 (fixpos);
9084 t1 = bfd_getl64 (fixpos + 8);
9085 control_bits = t0 & 0x1f;
9086 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9087 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9088 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9089
c67e42c9
RH		 9090 err = NULL;
9091 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 9092 {
c67e42c9
RH		 9093 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9094 insn[2] |= (((value & 0x7f) << 13)
9095 | (((value >> 7) & 0x1ff) << 27)
9096 | (((value >> 16) & 0x1f) << 22)
9097 | (((value >> 21) & 0x1) << 21)
9098 | (((value >> 63) & 0x1) << 36));
800eeca4 9099 }
c67e42c9
RH		 9100 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9101 {
9102 if (value & ~0x3fffffffffffffffULL)
9103 err = "integer operand out of range";
9104 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9105 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9106 }
9107 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9108 {
9109 value >>= 4;
9110 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9111 insn[2] |= ((((value >> 59) & 0x1) << 36)
9112 | (((value >> 0) & 0xfffff) << 13));
9113 }
9114 else
9115 err = (*odesc->insert) (odesc, value, insn + slot);
9116
9117 if (err)
9118 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW		 9119
9120 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9121 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9122 md_number_to_chars (fixpos + 0, t0, 8);
9123 md_number_to_chars (fixpos + 8, t1, 8);
800eeca4
JW		 9124}
9125
9126/* Attempt to simplify or even eliminate a fixup. The return value is
9127 ignored; perhaps it was once meaningful, but now it is historical.
9128 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9129
9130 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
197865e8 9131 (if possible). */
800eeca4
JW		 9132int
9133md_apply_fix3 (fix, valuep, seg)
9134 fixS *fix;
9135 valueT *valuep;
9136 segT seg;
9137{
9138 char *fixpos;
9139 valueT value = *valuep;
9140 int adjust = 0;
9141
9142 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9143
9144 if (fix->fx_pcrel)
9145 {
9146 switch (fix->fx_r_type)
9147 {
9148 case BFD_RELOC_IA64_DIR32MSB:
9149 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9150 adjust = 1;
9151 break;
9152
9153 case BFD_RELOC_IA64_DIR32LSB:
9154 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9155 adjust = 1;
9156 break;
9157
9158 case BFD_RELOC_IA64_DIR64MSB:
9159 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9160 adjust = 1;
9161 break;
9162
9163 case BFD_RELOC_IA64_DIR64LSB:
9164 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9165 adjust = 1;
9166 break;
9167
9168 default:
9169 break;
9170 }
9171 }
9172 if (fix->fx_addsy)
9173 {
9174 switch (fix->fx_r_type)
9175 {
9176 case 0:
9177 as_bad_where (fix->fx_file, fix->fx_line,
9178 "%s must have a constant value",
9179 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9180 break;
9181
9182 default:
9183 break;
9184 }
9185
9186 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
542d6675 9187 work. There should be a better way to handle this. */
800eeca4
JW		 9188 if (adjust)
9189 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9190 }
9191 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9192 {
9193 if (fix->tc_fix_data.bigendian)
9194 number_to_chars_bigendian (fixpos, value, fix->fx_size);
9195 else
9196 number_to_chars_littleendian (fixpos, value, fix->fx_size);
9197 fix->fx_done = 1;
9198 return 1;
9199 }
9200 else
9201 {
9202 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
9203 fix->fx_done = 1;
9204 return 1;
9205 }
9206 return 1;
9207}
9208
9209/* Generate the BFD reloc to be stuck in the object file from the
9210 fixup used internally in the assembler. */
542d6675
KH		 9211
9212arelent *
800eeca4
JW		 9213tc_gen_reloc (sec, fixp)
9214 asection *sec;
9215 fixS *fixp;
9216{
9217 arelent *reloc;
9218
9219 reloc = xmalloc (sizeof (*reloc));
9220 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9221 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9222 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9223 reloc->addend = fixp->fx_offset;
9224 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9225
9226 if (!reloc->howto)
9227 {
9228 as_bad_where (fixp->fx_file, fixp->fx_line,
9229 "Cannot represent %s relocation in object file",
9230 bfd_get_reloc_code_name (fixp->fx_r_type));
9231 }
9232 return reloc;
9233}
9234
9235/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 9236 of type TYPE, and store the appropriate bytes in *LIT. The number
9237 of LITTLENUMS emitted is stored in *SIZE. An error message is
800eeca4
JW		 9238 returned, or NULL on OK. */
9239
9240#define MAX_LITTLENUMS 5
9241
542d6675 9242char *
800eeca4
JW		 9243md_atof (type, lit, size)
9244 int type;
9245 char *lit;
9246 int *size;
9247{
9248 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9249 LITTLENUM_TYPE *word;
9250 char *t;
9251 int prec;
9252
9253 switch (type)
9254 {
9255 /* IEEE floats */
9256 case 'f':
9257 case 'F':
9258 case 's':
9259 case 'S':
9260 prec = 2;
9261 break;
9262
9263 case 'd':
9264 case 'D':
9265 case 'r':
9266 case 'R':
9267 prec = 4;
9268 break;
9269
9270 case 'x':
9271 case 'X':
9272 case 'p':
9273 case 'P':
9274 prec = 5;
9275 break;
9276
9277 default:
9278 *size = 0;
9279 return "Bad call to MD_ATOF()";
9280 }
9281 t = atof_ieee (input_line_pointer, type, words);
9282 if (t)
9283 input_line_pointer = t;
9284 *size = prec * sizeof (LITTLENUM_TYPE);
9285
9286 for (word = words + prec - 1; prec--;)
9287 {
9288 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9289 lit += sizeof (LITTLENUM_TYPE);
9290 }
9291 return 0;
9292}
9293
9294/* Round up a section's size to the appropriate boundary. */
9295valueT
9296md_section_align (seg, size)
9297 segT seg;
9298 valueT size;
9299{
9300 int align = bfd_get_section_alignment (stdoutput, seg);
197865e8 9301 valueT mask = ((valueT) 1 << align) - 1;
800eeca4
JW		 9302
9303 return (size + mask) & ~mask;
9304}
9305
9306/* Handle ia64 specific semantics of the align directive. */
9307
9308int
9309ia64_md_do_align (n, fill, len, max)
9310 int n;
9311 const char *fill;
9312 int len;
9313 int max;
9314{
9315 /* Fill any pending bundle with nops. */
9316 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
9317 ia64_flush_insns ();
9318
9319 /* When we align code in a text section, emit a bundle of 3 nops instead of
9320 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9321 N is log base 2 of the requested alignment. */
9322 if (fill == NULL
9323 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
9324 && n > 4)
9325 {
9326 /* Use mfi bundle of nops with no stop bits. */
9327 static const unsigned char be_nop[]
9328 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9329 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9330 static const unsigned char le_nop[]
9331 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9332 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
197865e8 9333
800eeca4
JW		 9334 /* Make sure we are on a 16-byte boundary, in case someone has been
9335 putting data into a text section. */
9336 frag_align (4, 0, 0);
9337
9338 if (target_big_endian)
9339 frag_align_pattern (n, be_nop, 16, max);
9340 else
9341 frag_align_pattern (n, le_nop, 16, max);
9342 return 1;
9343 }
9344
9345 return 0;
9346}
A mirror of the official binutils-gdb repository