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800eeca4 | 1 | /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. |
f7e42eb4 | 2 | Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
800eeca4 JW |
3 | Contributed by David Mosberger-Tang <davidm@hpl.hp.com> |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | /* | |
23 | TODO: | |
24 | ||
25 | - optional operands | |
26 | - directives: | |
27 | .alias | |
28 | .eb | |
29 | .estate | |
30 | .lb | |
31 | .popsection | |
32 | .previous | |
33 | .psr | |
34 | .pushsection | |
800eeca4 JW |
35 | - labels are wrong if automatic alignment is introduced |
36 | (e.g., checkout the second real10 definition in test-data.s) | |
37 | - DV-related stuff: | |
542d6675 KH |
38 | <reg>.safe_across_calls and any other DV-related directives I don't |
39 | have documentation for. | |
40 | verify mod-sched-brs reads/writes are checked/marked (and other | |
41 | notes) | |
800eeca4 JW |
42 | |
43 | */ | |
44 | ||
45 | #include "as.h" | |
46 | #include "dwarf2dbg.h" | |
47 | #include "subsegs.h" | |
48 | ||
49 | #include "opcode/ia64.h" | |
50 | ||
51 | #include "elf/ia64.h" | |
52 | ||
53 | #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) | |
54 | #define MIN(a,b) ((a) < (b) ? (a) : (b)) | |
55 | ||
56 | #define NUM_SLOTS 4 | |
57 | #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] | |
58 | #define CURR_SLOT md.slot[md.curr_slot] | |
59 | ||
60 | #define O_pseudo_fixup (O_max + 1) | |
61 | ||
62 | enum special_section | |
63 | { | |
64 | SPECIAL_SECTION_BSS = 0, | |
65 | SPECIAL_SECTION_SBSS, | |
66 | SPECIAL_SECTION_SDATA, | |
67 | SPECIAL_SECTION_RODATA, | |
68 | SPECIAL_SECTION_COMMENT, | |
69 | SPECIAL_SECTION_UNWIND, | |
70 | SPECIAL_SECTION_UNWIND_INFO | |
71 | }; | |
72 | ||
73 | enum reloc_func | |
74 | { | |
75 | FUNC_FPTR_RELATIVE, | |
76 | FUNC_GP_RELATIVE, | |
77 | FUNC_LT_RELATIVE, | |
c67e42c9 | 78 | FUNC_PC_RELATIVE, |
800eeca4 JW |
79 | FUNC_PLT_RELATIVE, |
80 | FUNC_SEC_RELATIVE, | |
81 | FUNC_SEG_RELATIVE, | |
82 | FUNC_LTV_RELATIVE, | |
83 | FUNC_LT_FPTR_RELATIVE, | |
84 | }; | |
85 | ||
86 | enum reg_symbol | |
87 | { | |
88 | REG_GR = 0, | |
89 | REG_FR = (REG_GR + 128), | |
90 | REG_AR = (REG_FR + 128), | |
91 | REG_CR = (REG_AR + 128), | |
92 | REG_P = (REG_CR + 128), | |
93 | REG_BR = (REG_P + 64), | |
94 | REG_IP = (REG_BR + 8), | |
95 | REG_CFM, | |
96 | REG_PR, | |
97 | REG_PR_ROT, | |
98 | REG_PSR, | |
99 | REG_PSR_L, | |
100 | REG_PSR_UM, | |
101 | /* The following are pseudo-registers for use by gas only. */ | |
102 | IND_CPUID, | |
103 | IND_DBR, | |
104 | IND_DTR, | |
105 | IND_ITR, | |
106 | IND_IBR, | |
107 | IND_MEM, | |
108 | IND_MSR, | |
109 | IND_PKR, | |
110 | IND_PMC, | |
111 | IND_PMD, | |
112 | IND_RR, | |
542d6675 | 113 | /* The following pseudo-registers are used for unwind directives only: */ |
e0c9811a JW |
114 | REG_PSP, |
115 | REG_PRIUNAT, | |
800eeca4 JW |
116 | REG_NUM |
117 | }; | |
118 | ||
119 | enum dynreg_type | |
120 | { | |
121 | DYNREG_GR = 0, /* dynamic general purpose register */ | |
122 | DYNREG_FR, /* dynamic floating point register */ | |
123 | DYNREG_PR, /* dynamic predicate register */ | |
124 | DYNREG_NUM_TYPES | |
125 | }; | |
126 | ||
87f8eb97 JW |
127 | enum operand_match_result |
128 | { | |
129 | OPERAND_MATCH, | |
130 | OPERAND_OUT_OF_RANGE, | |
131 | OPERAND_MISMATCH | |
132 | }; | |
133 | ||
800eeca4 JW |
134 | /* On the ia64, we can't know the address of a text label until the |
135 | instructions are packed into a bundle. To handle this, we keep | |
136 | track of the list of labels that appear in front of each | |
137 | instruction. */ | |
138 | struct label_fix | |
542d6675 KH |
139 | { |
140 | struct label_fix *next; | |
141 | struct symbol *sym; | |
142 | }; | |
800eeca4 JW |
143 | |
144 | extern int target_big_endian; | |
145 | ||
146 | /* Characters which always start a comment. */ | |
147 | const char comment_chars[] = ""; | |
148 | ||
149 | /* Characters which start a comment at the beginning of a line. */ | |
150 | const char line_comment_chars[] = "#"; | |
151 | ||
152 | /* Characters which may be used to separate multiple commands on a | |
153 | single line. */ | |
154 | const char line_separator_chars[] = ";"; | |
155 | ||
156 | /* Characters which are used to indicate an exponent in a floating | |
157 | point number. */ | |
158 | const char EXP_CHARS[] = "eE"; | |
159 | ||
160 | /* Characters which mean that a number is a floating point constant, | |
161 | as in 0d1.0. */ | |
162 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
163 | ||
542d6675 | 164 | /* ia64-specific option processing: */ |
800eeca4 | 165 | |
44f5c83a | 166 | const char *md_shortopts = "m:N:x::"; |
800eeca4 JW |
167 | |
168 | struct option md_longopts[] = | |
169 | { | |
c43c2cc5 JW |
170 | #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) |
171 | {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, | |
172 | #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) | |
173 | {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} | |
800eeca4 JW |
174 | }; |
175 | ||
176 | size_t md_longopts_size = sizeof (md_longopts); | |
177 | ||
178 | static struct | |
179 | { | |
180 | struct hash_control *pseudo_hash; /* pseudo opcode hash table */ | |
181 | struct hash_control *reg_hash; /* register name hash table */ | |
182 | struct hash_control *dynreg_hash; /* dynamic register hash table */ | |
183 | struct hash_control *const_hash; /* constant hash table */ | |
184 | struct hash_control *entry_hash; /* code entry hint hash table */ | |
185 | ||
186 | symbolS *regsym[REG_NUM]; | |
187 | ||
188 | /* If X_op is != O_absent, the registername for the instruction's | |
189 | qualifying predicate. If NULL, p0 is assumed for instructions | |
190 | that are predicatable. */ | |
191 | expressionS qp; | |
192 | ||
193 | unsigned int | |
197865e8 | 194 | manual_bundling : 1, |
800eeca4 JW |
195 | debug_dv: 1, |
196 | detect_dv: 1, | |
197 | explicit_mode : 1, /* which mode we're in */ | |
198 | default_explicit_mode : 1, /* which mode is the default */ | |
199 | mode_explicitly_set : 1, /* was the current mode explicitly set? */ | |
4d5a53ff JW |
200 | auto_align : 1, |
201 | keep_pending_output : 1; | |
800eeca4 JW |
202 | |
203 | /* Each bundle consists of up to three instructions. We keep | |
204 | track of four most recent instructions so we can correctly set | |
197865e8 | 205 | the end_of_insn_group for the last instruction in a bundle. */ |
800eeca4 JW |
206 | int curr_slot; |
207 | int num_slots_in_use; | |
208 | struct slot | |
209 | { | |
210 | unsigned int | |
211 | end_of_insn_group : 1, | |
212 | manual_bundling_on : 1, | |
213 | manual_bundling_off : 1; | |
214 | signed char user_template; /* user-selected template, if any */ | |
215 | unsigned char qp_regno; /* qualifying predicate */ | |
216 | /* This duplicates a good fraction of "struct fix" but we | |
217 | can't use a "struct fix" instead since we can't call | |
218 | fix_new_exp() until we know the address of the instruction. */ | |
219 | int num_fixups; | |
220 | struct insn_fix | |
221 | { | |
222 | bfd_reloc_code_real_type code; | |
223 | enum ia64_opnd opnd; /* type of operand in need of fix */ | |
224 | unsigned int is_pcrel : 1; /* is operand pc-relative? */ | |
225 | expressionS expr; /* the value to be inserted */ | |
226 | } | |
227 | fixup[2]; /* at most two fixups per insn */ | |
228 | struct ia64_opcode *idesc; | |
229 | struct label_fix *label_fixups; | |
f1bcba5b | 230 | struct label_fix *tag_fixups; |
800eeca4 JW |
231 | struct unw_rec_list *unwind_record; /* Unwind directive. */ |
232 | expressionS opnd[6]; | |
233 | char *src_file; | |
234 | unsigned int src_line; | |
235 | struct dwarf2_line_info debug_line; | |
236 | } | |
237 | slot[NUM_SLOTS]; | |
238 | ||
239 | segT last_text_seg; | |
240 | ||
241 | struct dynreg | |
242 | { | |
243 | struct dynreg *next; /* next dynamic register */ | |
244 | const char *name; | |
245 | unsigned short base; /* the base register number */ | |
246 | unsigned short num_regs; /* # of registers in this set */ | |
247 | } | |
248 | *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; | |
249 | ||
250 | flagword flags; /* ELF-header flags */ | |
251 | ||
252 | struct mem_offset { | |
253 | unsigned hint:1; /* is this hint currently valid? */ | |
254 | bfd_vma offset; /* mem.offset offset */ | |
255 | bfd_vma base; /* mem.offset base */ | |
256 | } mem_offset; | |
257 | ||
258 | int path; /* number of alt. entry points seen */ | |
259 | const char **entry_labels; /* labels of all alternate paths in | |
542d6675 | 260 | the current DV-checking block. */ |
800eeca4 | 261 | int maxpaths; /* size currently allocated for |
542d6675 | 262 | entry_labels */ |
88be23ec BS |
263 | /* Support for hardware errata workarounds. */ |
264 | ||
265 | /* Record data about the last three insn groups. */ | |
266 | struct group | |
267 | { | |
268 | /* B-step workaround. | |
269 | For each predicate register, this is set if the corresponding insn | |
270 | group conditionally sets this register with one of the affected | |
271 | instructions. */ | |
272 | int p_reg_set[64]; | |
273 | /* B-step workaround. | |
274 | For each general register, this is set if the corresponding insn | |
275 | a) is conditional one one of the predicate registers for which | |
276 | P_REG_SET is 1 in the corresponding entry of the previous group, | |
277 | b) sets this general register with one of the affected | |
278 | instructions. */ | |
279 | int g_reg_set_conditionally[128]; | |
280 | } last_groups[3]; | |
281 | int group_idx; | |
800eeca4 JW |
282 | } |
283 | md; | |
284 | ||
542d6675 | 285 | /* application registers: */ |
800eeca4 | 286 | |
e0c9811a JW |
287 | #define AR_K0 0 |
288 | #define AR_K7 7 | |
289 | #define AR_RSC 16 | |
290 | #define AR_BSP 17 | |
291 | #define AR_BSPSTORE 18 | |
292 | #define AR_RNAT 19 | |
293 | #define AR_UNAT 36 | |
294 | #define AR_FPSR 40 | |
295 | #define AR_ITC 44 | |
296 | #define AR_PFS 64 | |
297 | #define AR_LC 65 | |
800eeca4 JW |
298 | |
299 | static const struct | |
300 | { | |
301 | const char *name; | |
302 | int regnum; | |
303 | } | |
304 | ar[] = | |
305 | { | |
306 | {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, | |
307 | {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, | |
308 | {"ar.rsc", 16}, {"ar.bsp", 17}, | |
309 | {"ar.bspstore", 18}, {"ar.rnat", 19}, | |
310 | {"ar.fcr", 21}, {"ar.eflag", 24}, | |
311 | {"ar.csd", 25}, {"ar.ssd", 26}, | |
312 | {"ar.cflg", 27}, {"ar.fsr", 28}, | |
313 | {"ar.fir", 29}, {"ar.fdr", 30}, | |
314 | {"ar.ccv", 32}, {"ar.unat", 36}, | |
315 | {"ar.fpsr", 40}, {"ar.itc", 44}, | |
316 | {"ar.pfs", 64}, {"ar.lc", 65}, | |
197865e8 | 317 | {"ar.ec", 66}, |
800eeca4 JW |
318 | }; |
319 | ||
320 | #define CR_IPSR 16 | |
321 | #define CR_ISR 17 | |
322 | #define CR_IIP 19 | |
323 | #define CR_IFA 20 | |
324 | #define CR_ITIR 21 | |
325 | #define CR_IIPA 22 | |
326 | #define CR_IFS 23 | |
327 | #define CR_IIM 24 | |
328 | #define CR_IHA 25 | |
329 | #define CR_IVR 65 | |
330 | #define CR_TPR 66 | |
331 | #define CR_EOI 67 | |
332 | #define CR_IRR0 68 | |
333 | #define CR_IRR3 71 | |
334 | #define CR_LRR0 80 | |
335 | #define CR_LRR1 81 | |
336 | ||
542d6675 | 337 | /* control registers: */ |
800eeca4 JW |
338 | static const struct |
339 | { | |
340 | const char *name; | |
341 | int regnum; | |
342 | } | |
343 | cr[] = | |
344 | { | |
345 | {"cr.dcr", 0}, | |
346 | {"cr.itm", 1}, | |
347 | {"cr.iva", 2}, | |
348 | {"cr.pta", 8}, | |
349 | {"cr.gpta", 9}, | |
350 | {"cr.ipsr", 16}, | |
351 | {"cr.isr", 17}, | |
352 | {"cr.iip", 19}, | |
353 | {"cr.ifa", 20}, | |
354 | {"cr.itir", 21}, | |
355 | {"cr.iipa", 22}, | |
356 | {"cr.ifs", 23}, | |
357 | {"cr.iim", 24}, | |
358 | {"cr.iha", 25}, | |
359 | {"cr.lid", 64}, | |
360 | {"cr.ivr", 65}, | |
361 | {"cr.tpr", 66}, | |
362 | {"cr.eoi", 67}, | |
363 | {"cr.irr0", 68}, | |
364 | {"cr.irr1", 69}, | |
365 | {"cr.irr2", 70}, | |
366 | {"cr.irr3", 71}, | |
367 | {"cr.itv", 72}, | |
368 | {"cr.pmv", 73}, | |
369 | {"cr.cmcv", 74}, | |
370 | {"cr.lrr0", 80}, | |
371 | {"cr.lrr1", 81} | |
372 | }; | |
373 | ||
374 | #define PSR_MFL 4 | |
375 | #define PSR_IC 13 | |
376 | #define PSR_DFL 18 | |
377 | #define PSR_CPL 32 | |
378 | ||
379 | static const struct const_desc | |
380 | { | |
381 | const char *name; | |
382 | valueT value; | |
383 | } | |
384 | const_bits[] = | |
385 | { | |
542d6675 | 386 | /* PSR constant masks: */ |
800eeca4 JW |
387 | |
388 | /* 0: reserved */ | |
389 | {"psr.be", ((valueT) 1) << 1}, | |
390 | {"psr.up", ((valueT) 1) << 2}, | |
391 | {"psr.ac", ((valueT) 1) << 3}, | |
392 | {"psr.mfl", ((valueT) 1) << 4}, | |
393 | {"psr.mfh", ((valueT) 1) << 5}, | |
394 | /* 6-12: reserved */ | |
395 | {"psr.ic", ((valueT) 1) << 13}, | |
396 | {"psr.i", ((valueT) 1) << 14}, | |
397 | {"psr.pk", ((valueT) 1) << 15}, | |
398 | /* 16: reserved */ | |
399 | {"psr.dt", ((valueT) 1) << 17}, | |
400 | {"psr.dfl", ((valueT) 1) << 18}, | |
401 | {"psr.dfh", ((valueT) 1) << 19}, | |
402 | {"psr.sp", ((valueT) 1) << 20}, | |
403 | {"psr.pp", ((valueT) 1) << 21}, | |
404 | {"psr.di", ((valueT) 1) << 22}, | |
405 | {"psr.si", ((valueT) 1) << 23}, | |
406 | {"psr.db", ((valueT) 1) << 24}, | |
407 | {"psr.lp", ((valueT) 1) << 25}, | |
408 | {"psr.tb", ((valueT) 1) << 26}, | |
409 | {"psr.rt", ((valueT) 1) << 27}, | |
410 | /* 28-31: reserved */ | |
411 | /* 32-33: cpl (current privilege level) */ | |
412 | {"psr.is", ((valueT) 1) << 34}, | |
413 | {"psr.mc", ((valueT) 1) << 35}, | |
414 | {"psr.it", ((valueT) 1) << 36}, | |
415 | {"psr.id", ((valueT) 1) << 37}, | |
416 | {"psr.da", ((valueT) 1) << 38}, | |
417 | {"psr.dd", ((valueT) 1) << 39}, | |
418 | {"psr.ss", ((valueT) 1) << 40}, | |
419 | /* 41-42: ri (restart instruction) */ | |
420 | {"psr.ed", ((valueT) 1) << 43}, | |
421 | {"psr.bn", ((valueT) 1) << 44}, | |
422 | }; | |
423 | ||
542d6675 | 424 | /* indirect register-sets/memory: */ |
800eeca4 JW |
425 | |
426 | static const struct | |
427 | { | |
428 | const char *name; | |
429 | int regnum; | |
430 | } | |
431 | indirect_reg[] = | |
432 | { | |
433 | { "CPUID", IND_CPUID }, | |
434 | { "cpuid", IND_CPUID }, | |
435 | { "dbr", IND_DBR }, | |
436 | { "dtr", IND_DTR }, | |
437 | { "itr", IND_ITR }, | |
438 | { "ibr", IND_IBR }, | |
439 | { "msr", IND_MSR }, | |
440 | { "pkr", IND_PKR }, | |
441 | { "pmc", IND_PMC }, | |
442 | { "pmd", IND_PMD }, | |
443 | { "rr", IND_RR }, | |
444 | }; | |
445 | ||
446 | /* Pseudo functions used to indicate relocation types (these functions | |
447 | start with an at sign (@). */ | |
448 | static struct | |
449 | { | |
450 | const char *name; | |
451 | enum pseudo_type | |
452 | { | |
453 | PSEUDO_FUNC_NONE, | |
454 | PSEUDO_FUNC_RELOC, | |
455 | PSEUDO_FUNC_CONST, | |
e0c9811a | 456 | PSEUDO_FUNC_REG, |
800eeca4 JW |
457 | PSEUDO_FUNC_FLOAT |
458 | } | |
459 | type; | |
460 | union | |
461 | { | |
462 | unsigned long ival; | |
463 | symbolS *sym; | |
464 | } | |
465 | u; | |
466 | } | |
467 | pseudo_func[] = | |
468 | { | |
542d6675 | 469 | /* reloc pseudo functions (these must come first!): */ |
2434f565 JW |
470 | { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, |
471 | { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, | |
472 | { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, | |
473 | { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
474 | { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, | |
475 | { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
476 | { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
477 | { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, | |
478 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ | |
800eeca4 | 479 | |
542d6675 | 480 | /* mbtype4 constants: */ |
800eeca4 JW |
481 | { "alt", PSEUDO_FUNC_CONST, { 0xa } }, |
482 | { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, | |
483 | { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, | |
484 | { "rev", PSEUDO_FUNC_CONST, { 0xb } }, | |
485 | { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, | |
486 | ||
542d6675 | 487 | /* fclass constants: */ |
bf3ca999 | 488 | { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, |
800eeca4 JW |
489 | { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, |
490 | { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, | |
491 | { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, | |
492 | { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, | |
493 | { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, | |
494 | { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, | |
495 | { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, | |
496 | { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, | |
bf3ca999 TW |
497 | |
498 | { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ | |
e0c9811a | 499 | |
542d6675 | 500 | /* unwind-related constants: */ |
e0c9811a JW |
501 | { "svr4", PSEUDO_FUNC_CONST, { 0 } }, |
502 | { "hpux", PSEUDO_FUNC_CONST, { 1 } }, | |
503 | { "nt", PSEUDO_FUNC_CONST, { 2 } }, | |
504 | ||
542d6675 | 505 | /* unwind-related registers: */ |
e0c9811a | 506 | { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } |
800eeca4 JW |
507 | }; |
508 | ||
542d6675 | 509 | /* 41-bit nop opcodes (one per unit): */ |
800eeca4 JW |
510 | static const bfd_vma nop[IA64_NUM_UNITS] = |
511 | { | |
512 | 0x0000000000LL, /* NIL => break 0 */ | |
513 | 0x0008000000LL, /* I-unit nop */ | |
514 | 0x0008000000LL, /* M-unit nop */ | |
515 | 0x4000000000LL, /* B-unit nop */ | |
516 | 0x0008000000LL, /* F-unit nop */ | |
517 | 0x0008000000LL, /* L-"unit" nop */ | |
518 | 0x0008000000LL, /* X-unit nop */ | |
519 | }; | |
520 | ||
521 | /* Can't be `const' as it's passed to input routines (which have the | |
522 | habit of setting temporary sentinels. */ | |
523 | static char special_section_name[][20] = | |
524 | { | |
525 | {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, | |
526 | {".IA_64.unwind"}, {".IA_64.unwind_info"} | |
527 | }; | |
528 | ||
529 | /* The best template for a particular sequence of up to three | |
530 | instructions: */ | |
531 | #define N IA64_NUM_TYPES | |
532 | static unsigned char best_template[N][N][N]; | |
533 | #undef N | |
534 | ||
535 | /* Resource dependencies currently in effect */ | |
536 | static struct rsrc { | |
537 | int depind; /* dependency index */ | |
538 | const struct ia64_dependency *dependency; /* actual dependency */ | |
539 | unsigned specific:1, /* is this a specific bit/regno? */ | |
540 | link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ | |
541 | int index; /* specific regno/bit within dependency */ | |
542 | int note; /* optional qualifying note (0 if none) */ | |
543 | #define STATE_NONE 0 | |
544 | #define STATE_STOP 1 | |
545 | #define STATE_SRLZ 2 | |
546 | int insn_srlz; /* current insn serialization state */ | |
547 | int data_srlz; /* current data serialization state */ | |
548 | int qp_regno; /* qualifying predicate for this usage */ | |
549 | char *file; /* what file marked this dependency */ | |
2434f565 | 550 | unsigned int line; /* what line marked this dependency */ |
800eeca4 | 551 | struct mem_offset mem_offset; /* optional memory offset hint */ |
7484b8e6 | 552 | enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ |
800eeca4 JW |
553 | int path; /* corresponding code entry index */ |
554 | } *regdeps = NULL; | |
555 | static int regdepslen = 0; | |
556 | static int regdepstotlen = 0; | |
557 | static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; | |
558 | static const char *dv_sem[] = { "none", "implied", "impliedf", | |
139368c9 | 559 | "data", "instr", "specific", "stop", "other" }; |
7484b8e6 | 560 | static const char *dv_cmp_type[] = { "none", "OR", "AND" }; |
800eeca4 JW |
561 | |
562 | /* Current state of PR mutexation */ | |
563 | static struct qpmutex { | |
564 | valueT prmask; | |
565 | int path; | |
566 | } *qp_mutexes = NULL; /* QP mutex bitmasks */ | |
567 | static int qp_mutexeslen = 0; | |
568 | static int qp_mutexestotlen = 0; | |
197865e8 | 569 | static valueT qp_safe_across_calls = 0; |
800eeca4 JW |
570 | |
571 | /* Current state of PR implications */ | |
572 | static struct qp_imply { | |
573 | unsigned p1:6; | |
574 | unsigned p2:6; | |
575 | unsigned p2_branched:1; | |
576 | int path; | |
577 | } *qp_implies = NULL; | |
578 | static int qp_implieslen = 0; | |
579 | static int qp_impliestotlen = 0; | |
580 | ||
197865e8 KH |
581 | /* Keep track of static GR values so that indirect register usage can |
582 | sometimes be tracked. */ | |
800eeca4 JW |
583 | static struct gr { |
584 | unsigned known:1; | |
585 | int path; | |
586 | valueT value; | |
2434f565 | 587 | } gr_values[128] = {{ 1, 0, 0 }}; |
800eeca4 JW |
588 | |
589 | /* These are the routines required to output the various types of | |
590 | unwind records. */ | |
591 | ||
f5a30c2e JW |
592 | /* A slot_number is a frag address plus the slot index (0-2). We use the |
593 | frag address here so that if there is a section switch in the middle of | |
594 | a function, then instructions emitted to a different section are not | |
595 | counted. Since there may be more than one frag for a function, this | |
596 | means we also need to keep track of which frag this address belongs to | |
597 | so we can compute inter-frag distances. This also nicely solves the | |
598 | problem with nops emitted for align directives, which can't easily be | |
599 | counted, but can easily be derived from frag sizes. */ | |
600 | ||
800eeca4 JW |
601 | typedef struct unw_rec_list { |
602 | unwind_record r; | |
e0c9811a | 603 | unsigned long slot_number; |
f5a30c2e | 604 | fragS *slot_frag; |
800eeca4 JW |
605 | struct unw_rec_list *next; |
606 | } unw_rec_list; | |
607 | ||
2434f565 | 608 | #define SLOT_NUM_NOT_SET (unsigned)-1 |
800eeca4 | 609 | |
e0c9811a JW |
610 | static struct |
611 | { | |
612 | unsigned long next_slot_number; | |
f5a30c2e | 613 | fragS *next_slot_frag; |
e0c9811a JW |
614 | |
615 | /* Maintain a list of unwind entries for the current function. */ | |
616 | unw_rec_list *list; | |
617 | unw_rec_list *tail; | |
800eeca4 | 618 | |
e0c9811a JW |
619 | /* Any unwind entires that should be attached to the current slot |
620 | that an insn is being constructed for. */ | |
621 | unw_rec_list *current_entry; | |
800eeca4 | 622 | |
e0c9811a JW |
623 | /* These are used to create the unwind table entry for this function. */ |
624 | symbolS *proc_start; | |
625 | symbolS *proc_end; | |
626 | symbolS *info; /* pointer to unwind info */ | |
627 | symbolS *personality_routine; | |
91a2ae2a RH |
628 | segT saved_text_seg; |
629 | subsegT saved_text_subseg; | |
630 | unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ | |
800eeca4 | 631 | |
e0c9811a JW |
632 | /* TRUE if processing unwind directives in a prologue region. */ |
633 | int prologue; | |
30d25259 | 634 | int prologue_mask; |
33d01f33 | 635 | unsigned int prologue_count; /* number of .prologues seen so far */ |
e0c9811a | 636 | } unwind; |
800eeca4 JW |
637 | |
638 | typedef void (*vbyte_func) PARAMS ((int, char *, char *)); | |
639 | ||
542d6675 | 640 | /* Forward delarations: */ |
800eeca4 JW |
641 | static int ar_is_in_integer_unit PARAMS ((int regnum)); |
642 | static void set_section PARAMS ((char *name)); | |
643 | static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, | |
644 | unsigned int, unsigned int)); | |
645 | static void dot_radix PARAMS ((int)); | |
646 | static void dot_special_section PARAMS ((int)); | |
647 | static void dot_proc PARAMS ((int)); | |
648 | static void dot_fframe PARAMS ((int)); | |
649 | static void dot_vframe PARAMS ((int)); | |
150f24a2 JW |
650 | static void dot_vframesp PARAMS ((int)); |
651 | static void dot_vframepsp PARAMS ((int)); | |
800eeca4 JW |
652 | static void dot_save PARAMS ((int)); |
653 | static void dot_restore PARAMS ((int)); | |
150f24a2 JW |
654 | static void dot_restorereg PARAMS ((int)); |
655 | static void dot_restorereg_p PARAMS ((int)); | |
800eeca4 JW |
656 | static void dot_handlerdata PARAMS ((int)); |
657 | static void dot_unwentry PARAMS ((int)); | |
658 | static void dot_altrp PARAMS ((int)); | |
e0c9811a | 659 | static void dot_savemem PARAMS ((int)); |
800eeca4 JW |
660 | static void dot_saveg PARAMS ((int)); |
661 | static void dot_savef PARAMS ((int)); | |
662 | static void dot_saveb PARAMS ((int)); | |
663 | static void dot_savegf PARAMS ((int)); | |
664 | static void dot_spill PARAMS ((int)); | |
150f24a2 JW |
665 | static void dot_spillreg PARAMS ((int)); |
666 | static void dot_spillmem PARAMS ((int)); | |
667 | static void dot_spillreg_p PARAMS ((int)); | |
668 | static void dot_spillmem_p PARAMS ((int)); | |
669 | static void dot_label_state PARAMS ((int)); | |
670 | static void dot_copy_state PARAMS ((int)); | |
800eeca4 JW |
671 | static void dot_unwabi PARAMS ((int)); |
672 | static void dot_personality PARAMS ((int)); | |
673 | static void dot_body PARAMS ((int)); | |
674 | static void dot_prologue PARAMS ((int)); | |
675 | static void dot_endp PARAMS ((int)); | |
676 | static void dot_template PARAMS ((int)); | |
677 | static void dot_regstk PARAMS ((int)); | |
678 | static void dot_rot PARAMS ((int)); | |
679 | static void dot_byteorder PARAMS ((int)); | |
680 | static void dot_psr PARAMS ((int)); | |
681 | static void dot_alias PARAMS ((int)); | |
682 | static void dot_ln PARAMS ((int)); | |
683 | static char *parse_section_name PARAMS ((void)); | |
684 | static void dot_xdata PARAMS ((int)); | |
685 | static void stmt_float_cons PARAMS ((int)); | |
686 | static void stmt_cons_ua PARAMS ((int)); | |
687 | static void dot_xfloat_cons PARAMS ((int)); | |
688 | static void dot_xstringer PARAMS ((int)); | |
689 | static void dot_xdata_ua PARAMS ((int)); | |
690 | static void dot_xfloat_cons_ua PARAMS ((int)); | |
150f24a2 | 691 | static void print_prmask PARAMS ((valueT mask)); |
800eeca4 JW |
692 | static void dot_pred_rel PARAMS ((int)); |
693 | static void dot_reg_val PARAMS ((int)); | |
694 | static void dot_dv_mode PARAMS ((int)); | |
695 | static void dot_entry PARAMS ((int)); | |
696 | static void dot_mem_offset PARAMS ((int)); | |
e0c9811a | 697 | static void add_unwind_entry PARAMS((unw_rec_list *ptr)); |
542d6675 | 698 | static symbolS *declare_register PARAMS ((const char *name, int regnum)); |
800eeca4 JW |
699 | static void declare_register_set PARAMS ((const char *, int, int)); |
700 | static unsigned int operand_width PARAMS ((enum ia64_opnd)); | |
87f8eb97 JW |
701 | static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, |
702 | int index, | |
703 | expressionS *e)); | |
800eeca4 JW |
704 | static int parse_operand PARAMS ((expressionS *e)); |
705 | static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); | |
706 | static void build_insn PARAMS ((struct slot *, bfd_vma *)); | |
707 | static void emit_one_bundle PARAMS ((void)); | |
708 | static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); | |
197865e8 | 709 | static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, |
800eeca4 JW |
710 | bfd_reloc_code_real_type r_type)); |
711 | static void insn_group_break PARAMS ((int, int, int)); | |
150f24a2 JW |
712 | static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, |
713 | struct rsrc *, int depind, int path)); | |
800eeca4 JW |
714 | static void add_qp_mutex PARAMS((valueT mask)); |
715 | static void add_qp_imply PARAMS((int p1, int p2)); | |
716 | static void clear_qp_branch_flag PARAMS((valueT mask)); | |
717 | static void clear_qp_mutex PARAMS((valueT mask)); | |
718 | static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); | |
719 | static void clear_register_values PARAMS ((void)); | |
720 | static void print_dependency PARAMS ((const char *action, int depind)); | |
150f24a2 JW |
721 | static void instruction_serialization PARAMS ((void)); |
722 | static void data_serialization PARAMS ((void)); | |
723 | static void remove_marked_resource PARAMS ((struct rsrc *)); | |
800eeca4 | 724 | static int is_conditional_branch PARAMS ((struct ia64_opcode *)); |
150f24a2 | 725 | static int is_taken_branch PARAMS ((struct ia64_opcode *)); |
800eeca4 | 726 | static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); |
150f24a2 JW |
727 | static int depends_on PARAMS ((int, struct ia64_opcode *)); |
728 | static int specify_resource PARAMS ((const struct ia64_dependency *, | |
729 | struct ia64_opcode *, int, struct rsrc [], int, int)); | |
800eeca4 JW |
730 | static int check_dv PARAMS((struct ia64_opcode *idesc)); |
731 | static void check_dependencies PARAMS((struct ia64_opcode *)); | |
732 | static void mark_resources PARAMS((struct ia64_opcode *)); | |
733 | static void update_dependencies PARAMS((struct ia64_opcode *)); | |
734 | static void note_register_values PARAMS((struct ia64_opcode *)); | |
150f24a2 JW |
735 | static int qp_mutex PARAMS ((int, int, int)); |
736 | static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); | |
737 | static void output_vbyte_mem PARAMS ((int, char *, char *)); | |
738 | static void count_output PARAMS ((int, char *, char *)); | |
739 | static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); | |
740 | static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); | |
800eeca4 | 741 | static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
150f24a2 JW |
742 | static void output_P1_format PARAMS ((vbyte_func, int)); |
743 | static void output_P2_format PARAMS ((vbyte_func, int, int)); | |
744 | static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); | |
745 | static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); | |
746 | static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); | |
747 | static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); | |
748 | static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); | |
749 | static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
750 | static void output_P9_format PARAMS ((vbyte_func, int, int)); | |
751 | static void output_P10_format PARAMS ((vbyte_func, int, int)); | |
752 | static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
753 | static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); | |
800eeca4 JW |
754 | static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
755 | static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
150f24a2 JW |
756 | static char format_ab_reg PARAMS ((int, int)); |
757 | static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, | |
758 | unsigned long)); | |
759 | static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); | |
760 | static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, | |
761 | unsigned long)); | |
762 | static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); | |
763 | static void free_list_records PARAMS ((unw_rec_list *)); | |
764 | static unw_rec_list *output_prologue PARAMS ((void)); | |
765 | static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); | |
766 | static unw_rec_list *output_body PARAMS ((void)); | |
767 | static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); | |
768 | static unw_rec_list *output_mem_stack_v PARAMS ((void)); | |
769 | static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); | |
770 | static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); | |
771 | static unw_rec_list *output_rp_when PARAMS ((void)); | |
772 | static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); | |
773 | static unw_rec_list *output_rp_br PARAMS ((unsigned int)); | |
774 | static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); | |
775 | static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); | |
776 | static unw_rec_list *output_pfs_when PARAMS ((void)); | |
777 | static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); | |
778 | static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); | |
779 | static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); | |
780 | static unw_rec_list *output_preds_when PARAMS ((void)); | |
781 | static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); | |
782 | static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); | |
783 | static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); | |
784 | static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); | |
785 | static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); | |
786 | static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); | |
787 | static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); | |
788 | static unw_rec_list *output_br_mem PARAMS ((unsigned int)); | |
789 | static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); | |
790 | static unw_rec_list *output_spill_base PARAMS ((unsigned int)); | |
791 | static unw_rec_list *output_unat_when PARAMS ((void)); | |
792 | static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); | |
793 | static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); | |
794 | static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); | |
795 | static unw_rec_list *output_lc_when PARAMS ((void)); | |
796 | static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); | |
797 | static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); | |
798 | static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); | |
799 | static unw_rec_list *output_fpsr_when PARAMS ((void)); | |
800 | static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); | |
801 | static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); | |
802 | static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); | |
803 | static unw_rec_list *output_priunat_when_gr PARAMS ((void)); | |
804 | static unw_rec_list *output_priunat_when_mem PARAMS ((void)); | |
805 | static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); | |
806 | static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); | |
807 | static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); | |
808 | static unw_rec_list *output_bsp_when PARAMS ((void)); | |
809 | static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); | |
810 | static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); | |
811 | static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); | |
812 | static unw_rec_list *output_bspstore_when PARAMS ((void)); | |
813 | static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); | |
814 | static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); | |
815 | static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); | |
816 | static unw_rec_list *output_rnat_when PARAMS ((void)); | |
817 | static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); | |
818 | static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); | |
819 | static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); | |
820 | static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); | |
821 | static unw_rec_list *output_epilogue PARAMS ((unsigned long)); | |
822 | static unw_rec_list *output_label_state PARAMS ((unsigned long)); | |
823 | static unw_rec_list *output_copy_state PARAMS ((unsigned long)); | |
824 | static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
825 | static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
826 | static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
827 | unsigned int)); | |
828 | static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
829 | unsigned int)); | |
830 | static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, | |
831 | unsigned int)); | |
832 | static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
833 | unsigned int, unsigned int)); | |
834 | static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); | |
835 | static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); | |
836 | static int calc_record_size PARAMS ((unw_rec_list *)); | |
837 | static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); | |
838 | static int count_bits PARAMS ((unsigned long)); | |
f5a30c2e JW |
839 | static unsigned long slot_index PARAMS ((unsigned long, fragS *, |
840 | unsigned long, fragS *)); | |
91a2ae2a | 841 | static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); |
150f24a2 JW |
842 | static void fixup_unw_records PARAMS ((unw_rec_list *)); |
843 | static int output_unw_records PARAMS ((unw_rec_list *, void **)); | |
844 | static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
845 | static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
91a2ae2a RH |
846 | static int generate_unwind_image PARAMS ((const char *)); |
847 | ||
848 | /* Build the unwind section name by appending the (possibly stripped) | |
849 | text section NAME to the unwind PREFIX. The resulting string | |
850 | pointer is assigned to RESULT. The string is allocated on the | |
851 | stack, so this must be a macro... */ | |
852 | #define make_unw_section_name(special, text_name, result) \ | |
853 | { \ | |
854 | char *_prefix = special_section_name[special]; \ | |
855 | size_t _prefix_len = strlen (_prefix), _text_len = strlen (text_name); \ | |
856 | char *_result = alloca (_prefix_len + _text_len + 1); \ | |
857 | memcpy(_result, _prefix, _prefix_len); \ | |
858 | memcpy(_result + _prefix_len, text_name, _text_len); \ | |
859 | _result[_prefix_len + _text_len] = '\0'; \ | |
860 | result = _result; \ | |
861 | } \ | |
862 | while (0) | |
800eeca4 JW |
863 | |
864 | /* Determine if application register REGNUM resides in the integer | |
865 | unit (as opposed to the memory unit). */ | |
866 | static int | |
867 | ar_is_in_integer_unit (reg) | |
868 | int reg; | |
869 | { | |
870 | reg -= REG_AR; | |
871 | ||
872 | return (reg == 64 /* pfs */ | |
873 | || reg == 65 /* lc */ | |
874 | || reg == 66 /* ec */ | |
875 | /* ??? ias accepts and puts these in the integer unit. */ | |
876 | || (reg >= 112 && reg <= 127)); | |
877 | } | |
878 | ||
879 | /* Switch to section NAME and create section if necessary. It's | |
880 | rather ugly that we have to manipulate input_line_pointer but I | |
881 | don't see any other way to accomplish the same thing without | |
882 | changing obj-elf.c (which may be the Right Thing, in the end). */ | |
883 | static void | |
884 | set_section (name) | |
885 | char *name; | |
886 | { | |
887 | char *saved_input_line_pointer; | |
888 | ||
889 | saved_input_line_pointer = input_line_pointer; | |
890 | input_line_pointer = name; | |
891 | obj_elf_section (0); | |
892 | input_line_pointer = saved_input_line_pointer; | |
893 | } | |
894 | ||
895 | /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ | |
896 | ||
897 | flagword | |
898 | ia64_elf_section_flags (flags, attr, type) | |
899 | flagword flags; | |
2434f565 | 900 | int attr, type ATTRIBUTE_UNUSED; |
800eeca4 JW |
901 | { |
902 | if (attr & SHF_IA_64_SHORT) | |
903 | flags |= SEC_SMALL_DATA; | |
904 | return flags; | |
905 | } | |
906 | ||
91a2ae2a RH |
907 | int |
908 | ia64_elf_section_type (str, len) | |
909 | const char *str; | |
910 | size_t len; | |
911 | { | |
912 | len = sizeof (ELF_STRING_ia64_unwind_info) - 1; | |
913 | if (strncmp (str, ELF_STRING_ia64_unwind_info, len) == 0) | |
914 | return SHT_PROGBITS; | |
915 | ||
916 | len = sizeof (ELF_STRING_ia64_unwind) - 1; | |
917 | if (strncmp (str, ELF_STRING_ia64_unwind, len) == 0) | |
918 | return SHT_IA_64_UNWIND; | |
919 | ||
920 | return -1; | |
921 | } | |
922 | ||
800eeca4 JW |
923 | static unsigned int |
924 | set_regstack (ins, locs, outs, rots) | |
925 | unsigned int ins, locs, outs, rots; | |
926 | { | |
542d6675 KH |
927 | /* Size of frame. */ |
928 | unsigned int sof; | |
800eeca4 JW |
929 | |
930 | sof = ins + locs + outs; | |
931 | if (sof > 96) | |
932 | { | |
933 | as_bad ("Size of frame exceeds maximum of 96 registers"); | |
934 | return 0; | |
935 | } | |
936 | if (rots > sof) | |
937 | { | |
938 | as_warn ("Size of rotating registers exceeds frame size"); | |
939 | return 0; | |
940 | } | |
941 | md.in.base = REG_GR + 32; | |
942 | md.loc.base = md.in.base + ins; | |
943 | md.out.base = md.loc.base + locs; | |
944 | ||
945 | md.in.num_regs = ins; | |
946 | md.loc.num_regs = locs; | |
947 | md.out.num_regs = outs; | |
948 | md.rot.num_regs = rots; | |
949 | return sof; | |
950 | } | |
951 | ||
952 | void | |
953 | ia64_flush_insns () | |
954 | { | |
955 | struct label_fix *lfix; | |
956 | segT saved_seg; | |
957 | subsegT saved_subseg; | |
b44b1b85 | 958 | unw_rec_list *ptr; |
800eeca4 JW |
959 | |
960 | if (!md.last_text_seg) | |
961 | return; | |
962 | ||
963 | saved_seg = now_seg; | |
964 | saved_subseg = now_subseg; | |
965 | ||
966 | subseg_set (md.last_text_seg, 0); | |
967 | ||
968 | while (md.num_slots_in_use > 0) | |
969 | emit_one_bundle (); /* force out queued instructions */ | |
970 | ||
971 | /* In case there are labels following the last instruction, resolve | |
542d6675 | 972 | those now: */ |
800eeca4 JW |
973 | for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) |
974 | { | |
975 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
976 | symbol_set_frag (lfix->sym, frag_now); | |
977 | } | |
978 | CURR_SLOT.label_fixups = 0; | |
f1bcba5b JW |
979 | for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) |
980 | { | |
981 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
982 | symbol_set_frag (lfix->sym, frag_now); | |
983 | } | |
984 | CURR_SLOT.tag_fixups = 0; | |
800eeca4 | 985 | |
b44b1b85 JW |
986 | /* In case there are unwind directives following the last instruction, |
987 | resolve those now. We only handle body and prologue directives here. | |
988 | Give an error for others. */ | |
989 | for (ptr = unwind.current_entry; ptr; ptr = ptr->next) | |
990 | { | |
991 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr | |
992 | || ptr->r.type == body) | |
993 | { | |
994 | ptr->slot_number = (unsigned long) frag_more (0); | |
995 | ptr->slot_frag = frag_now; | |
996 | } | |
997 | else | |
998 | as_bad (_("Unwind directive not followed by an instruction.")); | |
999 | } | |
1000 | unwind.current_entry = NULL; | |
1001 | ||
800eeca4 | 1002 | subseg_set (saved_seg, saved_subseg); |
f1bcba5b JW |
1003 | |
1004 | if (md.qp.X_op == O_register) | |
1005 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
1006 | } |
1007 | ||
1008 | void | |
1009 | ia64_do_align (nbytes) | |
1010 | int nbytes; | |
1011 | { | |
1012 | char *saved_input_line_pointer = input_line_pointer; | |
1013 | ||
1014 | input_line_pointer = ""; | |
1015 | s_align_bytes (nbytes); | |
1016 | input_line_pointer = saved_input_line_pointer; | |
1017 | } | |
1018 | ||
1019 | void | |
1020 | ia64_cons_align (nbytes) | |
1021 | int nbytes; | |
1022 | { | |
1023 | if (md.auto_align) | |
1024 | { | |
1025 | char *saved_input_line_pointer = input_line_pointer; | |
1026 | input_line_pointer = ""; | |
1027 | s_align_bytes (nbytes); | |
1028 | input_line_pointer = saved_input_line_pointer; | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | /* Output COUNT bytes to a memory location. */ | |
1033 | static unsigned char *vbyte_mem_ptr = NULL; | |
1034 | ||
197865e8 | 1035 | void |
800eeca4 JW |
1036 | output_vbyte_mem (count, ptr, comment) |
1037 | int count; | |
1038 | char *ptr; | |
2434f565 | 1039 | char *comment ATTRIBUTE_UNUSED; |
800eeca4 JW |
1040 | { |
1041 | int x; | |
1042 | if (vbyte_mem_ptr == NULL) | |
1043 | abort (); | |
1044 | ||
1045 | if (count == 0) | |
1046 | return; | |
1047 | for (x = 0; x < count; x++) | |
1048 | *(vbyte_mem_ptr++) = ptr[x]; | |
1049 | } | |
1050 | ||
1051 | /* Count the number of bytes required for records. */ | |
1052 | static int vbyte_count = 0; | |
197865e8 | 1053 | void |
800eeca4 JW |
1054 | count_output (count, ptr, comment) |
1055 | int count; | |
2434f565 JW |
1056 | char *ptr ATTRIBUTE_UNUSED; |
1057 | char *comment ATTRIBUTE_UNUSED; | |
800eeca4 JW |
1058 | { |
1059 | vbyte_count += count; | |
1060 | } | |
1061 | ||
1062 | static void | |
1063 | output_R1_format (f, rtype, rlen) | |
1064 | vbyte_func f; | |
1065 | unw_record_type rtype; | |
1066 | int rlen; | |
1067 | { | |
e0c9811a | 1068 | int r = 0; |
800eeca4 JW |
1069 | char byte; |
1070 | if (rlen > 0x1f) | |
1071 | { | |
1072 | output_R3_format (f, rtype, rlen); | |
1073 | return; | |
1074 | } | |
197865e8 | 1075 | |
e0c9811a JW |
1076 | if (rtype == body) |
1077 | r = 1; | |
1078 | else if (rtype != prologue) | |
1079 | as_bad ("record type is not valid"); | |
1080 | ||
800eeca4 JW |
1081 | byte = UNW_R1 | (r << 5) | (rlen & 0x1f); |
1082 | (*f) (1, &byte, NULL); | |
1083 | } | |
1084 | ||
1085 | static void | |
1086 | output_R2_format (f, mask, grsave, rlen) | |
1087 | vbyte_func f; | |
1088 | int mask, grsave; | |
1089 | unsigned long rlen; | |
1090 | { | |
1091 | char bytes[20]; | |
1092 | int count = 2; | |
1093 | mask = (mask & 0x0f); | |
1094 | grsave = (grsave & 0x7f); | |
1095 | ||
1096 | bytes[0] = (UNW_R2 | (mask >> 1)); | |
1097 | bytes[1] = (((mask & 0x01) << 7) | grsave); | |
1098 | count += output_leb128 (bytes + 2, rlen, 0); | |
1099 | (*f) (count, bytes, NULL); | |
1100 | } | |
1101 | ||
1102 | static void | |
1103 | output_R3_format (f, rtype, rlen) | |
1104 | vbyte_func f; | |
1105 | unw_record_type rtype; | |
1106 | unsigned long rlen; | |
1107 | { | |
e0c9811a | 1108 | int r = 0, count; |
800eeca4 JW |
1109 | char bytes[20]; |
1110 | if (rlen <= 0x1f) | |
1111 | { | |
1112 | output_R1_format (f, rtype, rlen); | |
1113 | return; | |
1114 | } | |
197865e8 | 1115 | |
e0c9811a JW |
1116 | if (rtype == body) |
1117 | r = 1; | |
1118 | else if (rtype != prologue) | |
1119 | as_bad ("record type is not valid"); | |
800eeca4 JW |
1120 | bytes[0] = (UNW_R3 | r); |
1121 | count = output_leb128 (bytes + 1, rlen, 0); | |
1122 | (*f) (count + 1, bytes, NULL); | |
1123 | } | |
1124 | ||
1125 | static void | |
1126 | output_P1_format (f, brmask) | |
1127 | vbyte_func f; | |
1128 | int brmask; | |
1129 | { | |
1130 | char byte; | |
1131 | byte = UNW_P1 | (brmask & 0x1f); | |
1132 | (*f) (1, &byte, NULL); | |
1133 | } | |
1134 | ||
1135 | static void | |
1136 | output_P2_format (f, brmask, gr) | |
1137 | vbyte_func f; | |
1138 | int brmask; | |
1139 | int gr; | |
1140 | { | |
1141 | char bytes[2]; | |
1142 | brmask = (brmask & 0x1f); | |
1143 | bytes[0] = UNW_P2 | (brmask >> 1); | |
1144 | bytes[1] = (((brmask & 1) << 7) | gr); | |
1145 | (*f) (2, bytes, NULL); | |
1146 | } | |
1147 | ||
1148 | static void | |
1149 | output_P3_format (f, rtype, reg) | |
1150 | vbyte_func f; | |
1151 | unw_record_type rtype; | |
1152 | int reg; | |
1153 | { | |
1154 | char bytes[2]; | |
e0c9811a | 1155 | int r = 0; |
800eeca4 JW |
1156 | reg = (reg & 0x7f); |
1157 | switch (rtype) | |
542d6675 | 1158 | { |
800eeca4 JW |
1159 | case psp_gr: |
1160 | r = 0; | |
1161 | break; | |
1162 | case rp_gr: | |
1163 | r = 1; | |
1164 | break; | |
1165 | case pfs_gr: | |
1166 | r = 2; | |
1167 | break; | |
1168 | case preds_gr: | |
1169 | r = 3; | |
1170 | break; | |
1171 | case unat_gr: | |
1172 | r = 4; | |
1173 | break; | |
1174 | case lc_gr: | |
1175 | r = 5; | |
1176 | break; | |
1177 | case rp_br: | |
1178 | r = 6; | |
1179 | break; | |
1180 | case rnat_gr: | |
1181 | r = 7; | |
1182 | break; | |
1183 | case bsp_gr: | |
1184 | r = 8; | |
1185 | break; | |
1186 | case bspstore_gr: | |
1187 | r = 9; | |
1188 | break; | |
1189 | case fpsr_gr: | |
1190 | r = 10; | |
1191 | break; | |
1192 | case priunat_gr: | |
1193 | r = 11; | |
1194 | break; | |
1195 | default: | |
1196 | as_bad ("Invalid record type for P3 format."); | |
542d6675 | 1197 | } |
800eeca4 JW |
1198 | bytes[0] = (UNW_P3 | (r >> 1)); |
1199 | bytes[1] = (((r & 1) << 7) | reg); | |
1200 | (*f) (2, bytes, NULL); | |
1201 | } | |
1202 | ||
800eeca4 | 1203 | static void |
e0c9811a | 1204 | output_P4_format (f, imask, imask_size) |
800eeca4 | 1205 | vbyte_func f; |
e0c9811a JW |
1206 | unsigned char *imask; |
1207 | unsigned long imask_size; | |
800eeca4 | 1208 | { |
e0c9811a JW |
1209 | imask[0] = UNW_P4; |
1210 | (*f) (imask_size, imask, NULL); | |
800eeca4 JW |
1211 | } |
1212 | ||
1213 | static void | |
1214 | output_P5_format (f, grmask, frmask) | |
1215 | vbyte_func f; | |
1216 | int grmask; | |
1217 | unsigned long frmask; | |
1218 | { | |
1219 | char bytes[4]; | |
1220 | grmask = (grmask & 0x0f); | |
1221 | ||
1222 | bytes[0] = UNW_P5; | |
1223 | bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); | |
1224 | bytes[2] = ((frmask & 0x0000ff00) >> 8); | |
1225 | bytes[3] = (frmask & 0x000000ff); | |
1226 | (*f) (4, bytes, NULL); | |
1227 | } | |
1228 | ||
1229 | static void | |
1230 | output_P6_format (f, rtype, rmask) | |
1231 | vbyte_func f; | |
1232 | unw_record_type rtype; | |
1233 | int rmask; | |
1234 | { | |
1235 | char byte; | |
e0c9811a | 1236 | int r = 0; |
197865e8 | 1237 | |
e0c9811a JW |
1238 | if (rtype == gr_mem) |
1239 | r = 1; | |
1240 | else if (rtype != fr_mem) | |
1241 | as_bad ("Invalid record type for format P6"); | |
800eeca4 JW |
1242 | byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); |
1243 | (*f) (1, &byte, NULL); | |
1244 | } | |
1245 | ||
1246 | static void | |
1247 | output_P7_format (f, rtype, w1, w2) | |
1248 | vbyte_func f; | |
1249 | unw_record_type rtype; | |
1250 | unsigned long w1; | |
1251 | unsigned long w2; | |
1252 | { | |
1253 | char bytes[20]; | |
1254 | int count = 1; | |
e0c9811a | 1255 | int r = 0; |
800eeca4 JW |
1256 | count += output_leb128 (bytes + 1, w1, 0); |
1257 | switch (rtype) | |
1258 | { | |
542d6675 KH |
1259 | case mem_stack_f: |
1260 | r = 0; | |
1261 | count += output_leb128 (bytes + count, w2 >> 4, 0); | |
1262 | break; | |
1263 | case mem_stack_v: | |
1264 | r = 1; | |
1265 | break; | |
1266 | case spill_base: | |
1267 | r = 2; | |
1268 | break; | |
1269 | case psp_sprel: | |
1270 | r = 3; | |
1271 | break; | |
1272 | case rp_when: | |
1273 | r = 4; | |
1274 | break; | |
1275 | case rp_psprel: | |
1276 | r = 5; | |
1277 | break; | |
1278 | case pfs_when: | |
1279 | r = 6; | |
1280 | break; | |
1281 | case pfs_psprel: | |
1282 | r = 7; | |
1283 | break; | |
1284 | case preds_when: | |
1285 | r = 8; | |
1286 | break; | |
1287 | case preds_psprel: | |
1288 | r = 9; | |
1289 | break; | |
1290 | case lc_when: | |
1291 | r = 10; | |
1292 | break; | |
1293 | case lc_psprel: | |
1294 | r = 11; | |
1295 | break; | |
1296 | case unat_when: | |
1297 | r = 12; | |
1298 | break; | |
1299 | case unat_psprel: | |
1300 | r = 13; | |
1301 | break; | |
1302 | case fpsr_when: | |
1303 | r = 14; | |
1304 | break; | |
1305 | case fpsr_psprel: | |
1306 | r = 15; | |
1307 | break; | |
1308 | default: | |
1309 | break; | |
800eeca4 JW |
1310 | } |
1311 | bytes[0] = (UNW_P7 | r); | |
1312 | (*f) (count, bytes, NULL); | |
1313 | } | |
1314 | ||
1315 | static void | |
1316 | output_P8_format (f, rtype, t) | |
1317 | vbyte_func f; | |
1318 | unw_record_type rtype; | |
1319 | unsigned long t; | |
1320 | { | |
1321 | char bytes[20]; | |
e0c9811a | 1322 | int r = 0; |
800eeca4 JW |
1323 | int count = 2; |
1324 | bytes[0] = UNW_P8; | |
1325 | switch (rtype) | |
1326 | { | |
542d6675 KH |
1327 | case rp_sprel: |
1328 | r = 1; | |
1329 | break; | |
1330 | case pfs_sprel: | |
1331 | r = 2; | |
1332 | break; | |
1333 | case preds_sprel: | |
1334 | r = 3; | |
1335 | break; | |
1336 | case lc_sprel: | |
1337 | r = 4; | |
1338 | break; | |
1339 | case unat_sprel: | |
1340 | r = 5; | |
1341 | break; | |
1342 | case fpsr_sprel: | |
1343 | r = 6; | |
1344 | break; | |
1345 | case bsp_when: | |
1346 | r = 7; | |
1347 | break; | |
1348 | case bsp_psprel: | |
1349 | r = 8; | |
1350 | break; | |
1351 | case bsp_sprel: | |
1352 | r = 9; | |
1353 | break; | |
1354 | case bspstore_when: | |
1355 | r = 10; | |
1356 | break; | |
1357 | case bspstore_psprel: | |
1358 | r = 11; | |
1359 | break; | |
1360 | case bspstore_sprel: | |
1361 | r = 12; | |
1362 | break; | |
1363 | case rnat_when: | |
1364 | r = 13; | |
1365 | break; | |
1366 | case rnat_psprel: | |
1367 | r = 14; | |
1368 | break; | |
1369 | case rnat_sprel: | |
1370 | r = 15; | |
1371 | break; | |
1372 | case priunat_when_gr: | |
1373 | r = 16; | |
1374 | break; | |
1375 | case priunat_psprel: | |
1376 | r = 17; | |
1377 | break; | |
1378 | case priunat_sprel: | |
1379 | r = 18; | |
1380 | break; | |
1381 | case priunat_when_mem: | |
1382 | r = 19; | |
1383 | break; | |
1384 | default: | |
1385 | break; | |
800eeca4 JW |
1386 | } |
1387 | bytes[1] = r; | |
1388 | count += output_leb128 (bytes + 2, t, 0); | |
1389 | (*f) (count, bytes, NULL); | |
1390 | } | |
1391 | ||
1392 | static void | |
1393 | output_P9_format (f, grmask, gr) | |
1394 | vbyte_func f; | |
1395 | int grmask; | |
1396 | int gr; | |
1397 | { | |
1398 | char bytes[3]; | |
1399 | bytes[0] = UNW_P9; | |
1400 | bytes[1] = (grmask & 0x0f); | |
1401 | bytes[2] = (gr & 0x7f); | |
1402 | (*f) (3, bytes, NULL); | |
1403 | } | |
1404 | ||
1405 | static void | |
1406 | output_P10_format (f, abi, context) | |
1407 | vbyte_func f; | |
1408 | int abi; | |
1409 | int context; | |
1410 | { | |
1411 | char bytes[3]; | |
1412 | bytes[0] = UNW_P10; | |
1413 | bytes[1] = (abi & 0xff); | |
1414 | bytes[2] = (context & 0xff); | |
1415 | (*f) (3, bytes, NULL); | |
1416 | } | |
1417 | ||
1418 | static void | |
1419 | output_B1_format (f, rtype, label) | |
1420 | vbyte_func f; | |
1421 | unw_record_type rtype; | |
1422 | unsigned long label; | |
1423 | { | |
1424 | char byte; | |
e0c9811a | 1425 | int r = 0; |
197865e8 | 1426 | if (label > 0x1f) |
800eeca4 JW |
1427 | { |
1428 | output_B4_format (f, rtype, label); | |
1429 | return; | |
1430 | } | |
e0c9811a JW |
1431 | if (rtype == copy_state) |
1432 | r = 1; | |
1433 | else if (rtype != label_state) | |
1434 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1435 | |
1436 | byte = (UNW_B1 | (r << 5) | (label & 0x1f)); | |
1437 | (*f) (1, &byte, NULL); | |
1438 | } | |
1439 | ||
1440 | static void | |
1441 | output_B2_format (f, ecount, t) | |
1442 | vbyte_func f; | |
1443 | unsigned long ecount; | |
1444 | unsigned long t; | |
1445 | { | |
1446 | char bytes[20]; | |
1447 | int count = 1; | |
1448 | if (ecount > 0x1f) | |
1449 | { | |
1450 | output_B3_format (f, ecount, t); | |
1451 | return; | |
1452 | } | |
1453 | bytes[0] = (UNW_B2 | (ecount & 0x1f)); | |
1454 | count += output_leb128 (bytes + 1, t, 0); | |
1455 | (*f) (count, bytes, NULL); | |
1456 | } | |
1457 | ||
1458 | static void | |
1459 | output_B3_format (f, ecount, t) | |
1460 | vbyte_func f; | |
1461 | unsigned long ecount; | |
1462 | unsigned long t; | |
1463 | { | |
1464 | char bytes[20]; | |
1465 | int count = 1; | |
1466 | if (ecount <= 0x1f) | |
1467 | { | |
1468 | output_B2_format (f, ecount, t); | |
1469 | return; | |
1470 | } | |
1471 | bytes[0] = UNW_B3; | |
1472 | count += output_leb128 (bytes + 1, t, 0); | |
1473 | count += output_leb128 (bytes + count, ecount, 0); | |
1474 | (*f) (count, bytes, NULL); | |
1475 | } | |
1476 | ||
1477 | static void | |
1478 | output_B4_format (f, rtype, label) | |
1479 | vbyte_func f; | |
1480 | unw_record_type rtype; | |
1481 | unsigned long label; | |
1482 | { | |
1483 | char bytes[20]; | |
e0c9811a | 1484 | int r = 0; |
800eeca4 | 1485 | int count = 1; |
197865e8 | 1486 | if (label <= 0x1f) |
800eeca4 JW |
1487 | { |
1488 | output_B1_format (f, rtype, label); | |
1489 | return; | |
1490 | } | |
197865e8 | 1491 | |
e0c9811a JW |
1492 | if (rtype == copy_state) |
1493 | r = 1; | |
1494 | else if (rtype != label_state) | |
1495 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1496 | |
1497 | bytes[0] = (UNW_B4 | (r << 3)); | |
1498 | count += output_leb128 (bytes + 1, label, 0); | |
1499 | (*f) (count, bytes, NULL); | |
1500 | } | |
1501 | ||
1502 | static char | |
e0c9811a | 1503 | format_ab_reg (ab, reg) |
542d6675 KH |
1504 | int ab; |
1505 | int reg; | |
800eeca4 JW |
1506 | { |
1507 | int ret; | |
e0c9811a | 1508 | ab = (ab & 3); |
800eeca4 | 1509 | reg = (reg & 0x1f); |
e0c9811a | 1510 | ret = (ab << 5) | reg; |
800eeca4 JW |
1511 | return ret; |
1512 | } | |
1513 | ||
1514 | static void | |
e0c9811a | 1515 | output_X1_format (f, rtype, ab, reg, t, w1) |
800eeca4 JW |
1516 | vbyte_func f; |
1517 | unw_record_type rtype; | |
e0c9811a | 1518 | int ab, reg; |
800eeca4 JW |
1519 | unsigned long t; |
1520 | unsigned long w1; | |
1521 | { | |
1522 | char bytes[20]; | |
e0c9811a | 1523 | int r = 0; |
800eeca4 JW |
1524 | int count = 2; |
1525 | bytes[0] = UNW_X1; | |
197865e8 | 1526 | |
e0c9811a JW |
1527 | if (rtype == spill_sprel) |
1528 | r = 1; | |
1529 | else if (rtype != spill_psprel) | |
1530 | as_bad ("Invalid record type for format X1"); | |
1531 | bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); | |
800eeca4 JW |
1532 | count += output_leb128 (bytes + 2, t, 0); |
1533 | count += output_leb128 (bytes + count, w1, 0); | |
1534 | (*f) (count, bytes, NULL); | |
1535 | } | |
1536 | ||
1537 | static void | |
e0c9811a | 1538 | output_X2_format (f, ab, reg, x, y, treg, t) |
800eeca4 | 1539 | vbyte_func f; |
e0c9811a | 1540 | int ab, reg; |
800eeca4 JW |
1541 | int x, y, treg; |
1542 | unsigned long t; | |
1543 | { | |
1544 | char bytes[20]; | |
800eeca4 JW |
1545 | int count = 3; |
1546 | bytes[0] = UNW_X2; | |
e0c9811a | 1547 | bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1548 | bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); |
1549 | count += output_leb128 (bytes + 3, t, 0); | |
1550 | (*f) (count, bytes, NULL); | |
1551 | } | |
1552 | ||
1553 | static void | |
e0c9811a | 1554 | output_X3_format (f, rtype, qp, ab, reg, t, w1) |
800eeca4 JW |
1555 | vbyte_func f; |
1556 | unw_record_type rtype; | |
1557 | int qp; | |
e0c9811a | 1558 | int ab, reg; |
800eeca4 JW |
1559 | unsigned long t; |
1560 | unsigned long w1; | |
1561 | { | |
1562 | char bytes[20]; | |
e0c9811a | 1563 | int r = 0; |
800eeca4 | 1564 | int count = 3; |
e0c9811a JW |
1565 | bytes[0] = UNW_X3; |
1566 | ||
1567 | if (rtype == spill_sprel_p) | |
1568 | r = 1; | |
1569 | else if (rtype != spill_psprel_p) | |
1570 | as_bad ("Invalid record type for format X3"); | |
800eeca4 | 1571 | bytes[1] = ((r << 7) | (qp & 0x3f)); |
e0c9811a | 1572 | bytes[2] = format_ab_reg (ab, reg); |
800eeca4 JW |
1573 | count += output_leb128 (bytes + 3, t, 0); |
1574 | count += output_leb128 (bytes + count, w1, 0); | |
1575 | (*f) (count, bytes, NULL); | |
1576 | } | |
1577 | ||
1578 | static void | |
e0c9811a | 1579 | output_X4_format (f, qp, ab, reg, x, y, treg, t) |
800eeca4 JW |
1580 | vbyte_func f; |
1581 | int qp; | |
e0c9811a | 1582 | int ab, reg; |
800eeca4 JW |
1583 | int x, y, treg; |
1584 | unsigned long t; | |
1585 | { | |
1586 | char bytes[20]; | |
800eeca4 | 1587 | int count = 4; |
e0c9811a | 1588 | bytes[0] = UNW_X4; |
800eeca4 | 1589 | bytes[1] = (qp & 0x3f); |
e0c9811a | 1590 | bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1591 | bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); |
1592 | count += output_leb128 (bytes + 4, t, 0); | |
1593 | (*f) (count, bytes, NULL); | |
1594 | } | |
1595 | ||
1596 | /* This function allocates a record list structure, and initializes fields. */ | |
542d6675 | 1597 | |
800eeca4 | 1598 | static unw_rec_list * |
197865e8 | 1599 | alloc_record (unw_record_type t) |
800eeca4 JW |
1600 | { |
1601 | unw_rec_list *ptr; | |
1602 | ptr = xmalloc (sizeof (*ptr)); | |
1603 | ptr->next = NULL; | |
1604 | ptr->slot_number = SLOT_NUM_NOT_SET; | |
1605 | ptr->r.type = t; | |
1606 | return ptr; | |
1607 | } | |
1608 | ||
800eeca4 | 1609 | /* This function frees an entire list of record structures. */ |
542d6675 | 1610 | |
800eeca4 JW |
1611 | void |
1612 | free_list_records (unw_rec_list *first) | |
1613 | { | |
1614 | unw_rec_list *ptr; | |
542d6675 | 1615 | for (ptr = first; ptr != NULL;) |
800eeca4 JW |
1616 | { |
1617 | unw_rec_list *tmp = ptr; | |
e0c9811a JW |
1618 | |
1619 | if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) | |
1620 | && tmp->r.record.r.mask.i) | |
1621 | free (tmp->r.record.r.mask.i); | |
1622 | ||
800eeca4 JW |
1623 | ptr = ptr->next; |
1624 | free (tmp); | |
1625 | } | |
1626 | } | |
1627 | ||
1628 | static unw_rec_list * | |
1629 | output_prologue () | |
1630 | { | |
1631 | unw_rec_list *ptr = alloc_record (prologue); | |
e0c9811a | 1632 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
800eeca4 JW |
1633 | return ptr; |
1634 | } | |
1635 | ||
1636 | static unw_rec_list * | |
1637 | output_prologue_gr (saved_mask, reg) | |
1638 | unsigned int saved_mask; | |
1639 | unsigned int reg; | |
1640 | { | |
1641 | unw_rec_list *ptr = alloc_record (prologue_gr); | |
e0c9811a JW |
1642 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
1643 | ptr->r.record.r.grmask = saved_mask; | |
800eeca4 JW |
1644 | ptr->r.record.r.grsave = reg; |
1645 | return ptr; | |
1646 | } | |
1647 | ||
1648 | static unw_rec_list * | |
1649 | output_body () | |
1650 | { | |
1651 | unw_rec_list *ptr = alloc_record (body); | |
1652 | return ptr; | |
1653 | } | |
1654 | ||
1655 | static unw_rec_list * | |
1656 | output_mem_stack_f (size) | |
1657 | unsigned int size; | |
1658 | { | |
1659 | unw_rec_list *ptr = alloc_record (mem_stack_f); | |
1660 | ptr->r.record.p.size = size; | |
1661 | return ptr; | |
1662 | } | |
1663 | ||
1664 | static unw_rec_list * | |
1665 | output_mem_stack_v () | |
1666 | { | |
1667 | unw_rec_list *ptr = alloc_record (mem_stack_v); | |
1668 | return ptr; | |
1669 | } | |
1670 | ||
1671 | static unw_rec_list * | |
1672 | output_psp_gr (gr) | |
1673 | unsigned int gr; | |
1674 | { | |
1675 | unw_rec_list *ptr = alloc_record (psp_gr); | |
1676 | ptr->r.record.p.gr = gr; | |
1677 | return ptr; | |
1678 | } | |
1679 | ||
1680 | static unw_rec_list * | |
1681 | output_psp_sprel (offset) | |
1682 | unsigned int offset; | |
1683 | { | |
1684 | unw_rec_list *ptr = alloc_record (psp_sprel); | |
542d6675 | 1685 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1686 | return ptr; |
1687 | } | |
1688 | ||
1689 | static unw_rec_list * | |
1690 | output_rp_when () | |
1691 | { | |
1692 | unw_rec_list *ptr = alloc_record (rp_when); | |
1693 | return ptr; | |
1694 | } | |
1695 | ||
1696 | static unw_rec_list * | |
1697 | output_rp_gr (gr) | |
1698 | unsigned int gr; | |
1699 | { | |
1700 | unw_rec_list *ptr = alloc_record (rp_gr); | |
1701 | ptr->r.record.p.gr = gr; | |
1702 | return ptr; | |
1703 | } | |
1704 | ||
1705 | static unw_rec_list * | |
1706 | output_rp_br (br) | |
1707 | unsigned int br; | |
1708 | { | |
1709 | unw_rec_list *ptr = alloc_record (rp_br); | |
1710 | ptr->r.record.p.br = br; | |
1711 | return ptr; | |
1712 | } | |
1713 | ||
1714 | static unw_rec_list * | |
1715 | output_rp_psprel (offset) | |
1716 | unsigned int offset; | |
1717 | { | |
1718 | unw_rec_list *ptr = alloc_record (rp_psprel); | |
542d6675 | 1719 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1720 | return ptr; |
1721 | } | |
1722 | ||
1723 | static unw_rec_list * | |
1724 | output_rp_sprel (offset) | |
1725 | unsigned int offset; | |
1726 | { | |
1727 | unw_rec_list *ptr = alloc_record (rp_sprel); | |
542d6675 | 1728 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1729 | return ptr; |
1730 | } | |
1731 | ||
1732 | static unw_rec_list * | |
1733 | output_pfs_when () | |
1734 | { | |
1735 | unw_rec_list *ptr = alloc_record (pfs_when); | |
1736 | return ptr; | |
1737 | } | |
1738 | ||
1739 | static unw_rec_list * | |
1740 | output_pfs_gr (gr) | |
1741 | unsigned int gr; | |
1742 | { | |
1743 | unw_rec_list *ptr = alloc_record (pfs_gr); | |
1744 | ptr->r.record.p.gr = gr; | |
1745 | return ptr; | |
1746 | } | |
1747 | ||
1748 | static unw_rec_list * | |
1749 | output_pfs_psprel (offset) | |
1750 | unsigned int offset; | |
1751 | { | |
1752 | unw_rec_list *ptr = alloc_record (pfs_psprel); | |
542d6675 | 1753 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1754 | return ptr; |
1755 | } | |
1756 | ||
1757 | static unw_rec_list * | |
1758 | output_pfs_sprel (offset) | |
1759 | unsigned int offset; | |
1760 | { | |
1761 | unw_rec_list *ptr = alloc_record (pfs_sprel); | |
542d6675 | 1762 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1763 | return ptr; |
1764 | } | |
1765 | ||
1766 | static unw_rec_list * | |
1767 | output_preds_when () | |
1768 | { | |
1769 | unw_rec_list *ptr = alloc_record (preds_when); | |
1770 | return ptr; | |
1771 | } | |
1772 | ||
1773 | static unw_rec_list * | |
1774 | output_preds_gr (gr) | |
1775 | unsigned int gr; | |
1776 | { | |
1777 | unw_rec_list *ptr = alloc_record (preds_gr); | |
1778 | ptr->r.record.p.gr = gr; | |
1779 | return ptr; | |
1780 | } | |
1781 | ||
1782 | static unw_rec_list * | |
1783 | output_preds_psprel (offset) | |
1784 | unsigned int offset; | |
1785 | { | |
1786 | unw_rec_list *ptr = alloc_record (preds_psprel); | |
542d6675 | 1787 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1788 | return ptr; |
1789 | } | |
1790 | ||
1791 | static unw_rec_list * | |
1792 | output_preds_sprel (offset) | |
1793 | unsigned int offset; | |
1794 | { | |
1795 | unw_rec_list *ptr = alloc_record (preds_sprel); | |
542d6675 | 1796 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1797 | return ptr; |
1798 | } | |
1799 | ||
1800 | static unw_rec_list * | |
1801 | output_fr_mem (mask) | |
1802 | unsigned int mask; | |
1803 | { | |
1804 | unw_rec_list *ptr = alloc_record (fr_mem); | |
1805 | ptr->r.record.p.rmask = mask; | |
1806 | return ptr; | |
1807 | } | |
1808 | ||
1809 | static unw_rec_list * | |
1810 | output_frgr_mem (gr_mask, fr_mask) | |
1811 | unsigned int gr_mask; | |
1812 | unsigned int fr_mask; | |
1813 | { | |
1814 | unw_rec_list *ptr = alloc_record (frgr_mem); | |
1815 | ptr->r.record.p.grmask = gr_mask; | |
1816 | ptr->r.record.p.frmask = fr_mask; | |
1817 | return ptr; | |
1818 | } | |
1819 | ||
1820 | static unw_rec_list * | |
1821 | output_gr_gr (mask, reg) | |
1822 | unsigned int mask; | |
1823 | unsigned int reg; | |
1824 | { | |
1825 | unw_rec_list *ptr = alloc_record (gr_gr); | |
1826 | ptr->r.record.p.grmask = mask; | |
1827 | ptr->r.record.p.gr = reg; | |
1828 | return ptr; | |
1829 | } | |
1830 | ||
1831 | static unw_rec_list * | |
1832 | output_gr_mem (mask) | |
1833 | unsigned int mask; | |
1834 | { | |
1835 | unw_rec_list *ptr = alloc_record (gr_mem); | |
1836 | ptr->r.record.p.rmask = mask; | |
1837 | return ptr; | |
1838 | } | |
1839 | ||
1840 | static unw_rec_list * | |
1841 | output_br_mem (unsigned int mask) | |
1842 | { | |
1843 | unw_rec_list *ptr = alloc_record (br_mem); | |
1844 | ptr->r.record.p.brmask = mask; | |
1845 | return ptr; | |
1846 | } | |
1847 | ||
1848 | static unw_rec_list * | |
1849 | output_br_gr (save_mask, reg) | |
1850 | unsigned int save_mask; | |
1851 | unsigned int reg; | |
1852 | { | |
1853 | unw_rec_list *ptr = alloc_record (br_gr); | |
1854 | ptr->r.record.p.brmask = save_mask; | |
1855 | ptr->r.record.p.gr = reg; | |
1856 | return ptr; | |
1857 | } | |
1858 | ||
1859 | static unw_rec_list * | |
1860 | output_spill_base (offset) | |
1861 | unsigned int offset; | |
1862 | { | |
1863 | unw_rec_list *ptr = alloc_record (spill_base); | |
542d6675 | 1864 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1865 | return ptr; |
1866 | } | |
1867 | ||
1868 | static unw_rec_list * | |
1869 | output_unat_when () | |
1870 | { | |
1871 | unw_rec_list *ptr = alloc_record (unat_when); | |
1872 | return ptr; | |
1873 | } | |
1874 | ||
1875 | static unw_rec_list * | |
1876 | output_unat_gr (gr) | |
1877 | unsigned int gr; | |
1878 | { | |
1879 | unw_rec_list *ptr = alloc_record (unat_gr); | |
1880 | ptr->r.record.p.gr = gr; | |
1881 | return ptr; | |
1882 | } | |
1883 | ||
1884 | static unw_rec_list * | |
1885 | output_unat_psprel (offset) | |
1886 | unsigned int offset; | |
1887 | { | |
1888 | unw_rec_list *ptr = alloc_record (unat_psprel); | |
542d6675 | 1889 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1890 | return ptr; |
1891 | } | |
1892 | ||
1893 | static unw_rec_list * | |
1894 | output_unat_sprel (offset) | |
1895 | unsigned int offset; | |
1896 | { | |
1897 | unw_rec_list *ptr = alloc_record (unat_sprel); | |
542d6675 | 1898 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1899 | return ptr; |
1900 | } | |
1901 | ||
1902 | static unw_rec_list * | |
1903 | output_lc_when () | |
1904 | { | |
1905 | unw_rec_list *ptr = alloc_record (lc_when); | |
1906 | return ptr; | |
1907 | } | |
1908 | ||
1909 | static unw_rec_list * | |
1910 | output_lc_gr (gr) | |
1911 | unsigned int gr; | |
1912 | { | |
1913 | unw_rec_list *ptr = alloc_record (lc_gr); | |
1914 | ptr->r.record.p.gr = gr; | |
1915 | return ptr; | |
1916 | } | |
1917 | ||
1918 | static unw_rec_list * | |
1919 | output_lc_psprel (offset) | |
1920 | unsigned int offset; | |
1921 | { | |
1922 | unw_rec_list *ptr = alloc_record (lc_psprel); | |
542d6675 | 1923 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1924 | return ptr; |
1925 | } | |
1926 | ||
1927 | static unw_rec_list * | |
1928 | output_lc_sprel (offset) | |
1929 | unsigned int offset; | |
1930 | { | |
1931 | unw_rec_list *ptr = alloc_record (lc_sprel); | |
542d6675 | 1932 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1933 | return ptr; |
1934 | } | |
1935 | ||
1936 | static unw_rec_list * | |
1937 | output_fpsr_when () | |
1938 | { | |
1939 | unw_rec_list *ptr = alloc_record (fpsr_when); | |
1940 | return ptr; | |
1941 | } | |
1942 | ||
1943 | static unw_rec_list * | |
1944 | output_fpsr_gr (gr) | |
1945 | unsigned int gr; | |
1946 | { | |
1947 | unw_rec_list *ptr = alloc_record (fpsr_gr); | |
1948 | ptr->r.record.p.gr = gr; | |
1949 | return ptr; | |
1950 | } | |
1951 | ||
1952 | static unw_rec_list * | |
1953 | output_fpsr_psprel (offset) | |
1954 | unsigned int offset; | |
1955 | { | |
1956 | unw_rec_list *ptr = alloc_record (fpsr_psprel); | |
542d6675 | 1957 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1958 | return ptr; |
1959 | } | |
1960 | ||
1961 | static unw_rec_list * | |
1962 | output_fpsr_sprel (offset) | |
1963 | unsigned int offset; | |
1964 | { | |
1965 | unw_rec_list *ptr = alloc_record (fpsr_sprel); | |
542d6675 | 1966 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1967 | return ptr; |
1968 | } | |
1969 | ||
1970 | static unw_rec_list * | |
1971 | output_priunat_when_gr () | |
1972 | { | |
1973 | unw_rec_list *ptr = alloc_record (priunat_when_gr); | |
1974 | return ptr; | |
1975 | } | |
1976 | ||
1977 | static unw_rec_list * | |
1978 | output_priunat_when_mem () | |
1979 | { | |
1980 | unw_rec_list *ptr = alloc_record (priunat_when_mem); | |
1981 | return ptr; | |
1982 | } | |
1983 | ||
1984 | static unw_rec_list * | |
1985 | output_priunat_gr (gr) | |
1986 | unsigned int gr; | |
1987 | { | |
1988 | unw_rec_list *ptr = alloc_record (priunat_gr); | |
1989 | ptr->r.record.p.gr = gr; | |
1990 | return ptr; | |
1991 | } | |
1992 | ||
1993 | static unw_rec_list * | |
1994 | output_priunat_psprel (offset) | |
1995 | unsigned int offset; | |
1996 | { | |
1997 | unw_rec_list *ptr = alloc_record (priunat_psprel); | |
542d6675 | 1998 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1999 | return ptr; |
2000 | } | |
2001 | ||
2002 | static unw_rec_list * | |
2003 | output_priunat_sprel (offset) | |
2004 | unsigned int offset; | |
2005 | { | |
2006 | unw_rec_list *ptr = alloc_record (priunat_sprel); | |
542d6675 | 2007 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2008 | return ptr; |
2009 | } | |
2010 | ||
2011 | static unw_rec_list * | |
2012 | output_bsp_when () | |
2013 | { | |
2014 | unw_rec_list *ptr = alloc_record (bsp_when); | |
2015 | return ptr; | |
2016 | } | |
2017 | ||
2018 | static unw_rec_list * | |
2019 | output_bsp_gr (gr) | |
2020 | unsigned int gr; | |
2021 | { | |
2022 | unw_rec_list *ptr = alloc_record (bsp_gr); | |
2023 | ptr->r.record.p.gr = gr; | |
2024 | return ptr; | |
2025 | } | |
2026 | ||
2027 | static unw_rec_list * | |
2028 | output_bsp_psprel (offset) | |
2029 | unsigned int offset; | |
2030 | { | |
2031 | unw_rec_list *ptr = alloc_record (bsp_psprel); | |
542d6675 | 2032 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2033 | return ptr; |
2034 | } | |
2035 | ||
2036 | static unw_rec_list * | |
2037 | output_bsp_sprel (offset) | |
2038 | unsigned int offset; | |
2039 | { | |
2040 | unw_rec_list *ptr = alloc_record (bsp_sprel); | |
542d6675 | 2041 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2042 | return ptr; |
2043 | } | |
2044 | ||
2045 | static unw_rec_list * | |
2046 | output_bspstore_when () | |
2047 | { | |
2048 | unw_rec_list *ptr = alloc_record (bspstore_when); | |
2049 | return ptr; | |
2050 | } | |
2051 | ||
2052 | static unw_rec_list * | |
2053 | output_bspstore_gr (gr) | |
2054 | unsigned int gr; | |
2055 | { | |
2056 | unw_rec_list *ptr = alloc_record (bspstore_gr); | |
2057 | ptr->r.record.p.gr = gr; | |
2058 | return ptr; | |
2059 | } | |
2060 | ||
2061 | static unw_rec_list * | |
2062 | output_bspstore_psprel (offset) | |
2063 | unsigned int offset; | |
2064 | { | |
2065 | unw_rec_list *ptr = alloc_record (bspstore_psprel); | |
542d6675 | 2066 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2067 | return ptr; |
2068 | } | |
2069 | ||
2070 | static unw_rec_list * | |
2071 | output_bspstore_sprel (offset) | |
2072 | unsigned int offset; | |
2073 | { | |
2074 | unw_rec_list *ptr = alloc_record (bspstore_sprel); | |
542d6675 | 2075 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2076 | return ptr; |
2077 | } | |
2078 | ||
2079 | static unw_rec_list * | |
2080 | output_rnat_when () | |
2081 | { | |
2082 | unw_rec_list *ptr = alloc_record (rnat_when); | |
2083 | return ptr; | |
2084 | } | |
2085 | ||
2086 | static unw_rec_list * | |
2087 | output_rnat_gr (gr) | |
2088 | unsigned int gr; | |
2089 | { | |
2090 | unw_rec_list *ptr = alloc_record (rnat_gr); | |
2091 | ptr->r.record.p.gr = gr; | |
2092 | return ptr; | |
2093 | } | |
2094 | ||
2095 | static unw_rec_list * | |
2096 | output_rnat_psprel (offset) | |
2097 | unsigned int offset; | |
2098 | { | |
2099 | unw_rec_list *ptr = alloc_record (rnat_psprel); | |
542d6675 | 2100 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2101 | return ptr; |
2102 | } | |
2103 | ||
2104 | static unw_rec_list * | |
2105 | output_rnat_sprel (offset) | |
2106 | unsigned int offset; | |
2107 | { | |
2108 | unw_rec_list *ptr = alloc_record (rnat_sprel); | |
542d6675 | 2109 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2110 | return ptr; |
2111 | } | |
2112 | ||
2113 | static unw_rec_list * | |
e0c9811a JW |
2114 | output_unwabi (abi, context) |
2115 | unsigned long abi; | |
2116 | unsigned long context; | |
800eeca4 | 2117 | { |
e0c9811a JW |
2118 | unw_rec_list *ptr = alloc_record (unwabi); |
2119 | ptr->r.record.p.abi = abi; | |
2120 | ptr->r.record.p.context = context; | |
800eeca4 JW |
2121 | return ptr; |
2122 | } | |
2123 | ||
2124 | static unw_rec_list * | |
e0c9811a | 2125 | output_epilogue (unsigned long ecount) |
800eeca4 | 2126 | { |
e0c9811a JW |
2127 | unw_rec_list *ptr = alloc_record (epilogue); |
2128 | ptr->r.record.b.ecount = ecount; | |
800eeca4 JW |
2129 | return ptr; |
2130 | } | |
2131 | ||
2132 | static unw_rec_list * | |
e0c9811a | 2133 | output_label_state (unsigned long label) |
800eeca4 | 2134 | { |
e0c9811a JW |
2135 | unw_rec_list *ptr = alloc_record (label_state); |
2136 | ptr->r.record.b.label = label; | |
800eeca4 JW |
2137 | return ptr; |
2138 | } | |
2139 | ||
2140 | static unw_rec_list * | |
e0c9811a JW |
2141 | output_copy_state (unsigned long label) |
2142 | { | |
2143 | unw_rec_list *ptr = alloc_record (copy_state); | |
2144 | ptr->r.record.b.label = label; | |
2145 | return ptr; | |
2146 | } | |
2147 | ||
2148 | static unw_rec_list * | |
2149 | output_spill_psprel (ab, reg, offset) | |
2150 | unsigned int ab; | |
800eeca4 JW |
2151 | unsigned int reg; |
2152 | unsigned int offset; | |
2153 | { | |
2154 | unw_rec_list *ptr = alloc_record (spill_psprel); | |
e0c9811a | 2155 | ptr->r.record.x.ab = ab; |
800eeca4 | 2156 | ptr->r.record.x.reg = reg; |
542d6675 | 2157 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2158 | return ptr; |
2159 | } | |
2160 | ||
2161 | static unw_rec_list * | |
e0c9811a JW |
2162 | output_spill_sprel (ab, reg, offset) |
2163 | unsigned int ab; | |
800eeca4 JW |
2164 | unsigned int reg; |
2165 | unsigned int offset; | |
2166 | { | |
2167 | unw_rec_list *ptr = alloc_record (spill_sprel); | |
e0c9811a | 2168 | ptr->r.record.x.ab = ab; |
800eeca4 | 2169 | ptr->r.record.x.reg = reg; |
542d6675 | 2170 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2171 | return ptr; |
2172 | } | |
2173 | ||
2174 | static unw_rec_list * | |
e0c9811a JW |
2175 | output_spill_psprel_p (ab, reg, offset, predicate) |
2176 | unsigned int ab; | |
800eeca4 JW |
2177 | unsigned int reg; |
2178 | unsigned int offset; | |
2179 | unsigned int predicate; | |
2180 | { | |
2181 | unw_rec_list *ptr = alloc_record (spill_psprel_p); | |
e0c9811a | 2182 | ptr->r.record.x.ab = ab; |
800eeca4 | 2183 | ptr->r.record.x.reg = reg; |
542d6675 | 2184 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2185 | ptr->r.record.x.qp = predicate; |
2186 | return ptr; | |
2187 | } | |
2188 | ||
2189 | static unw_rec_list * | |
e0c9811a JW |
2190 | output_spill_sprel_p (ab, reg, offset, predicate) |
2191 | unsigned int ab; | |
800eeca4 JW |
2192 | unsigned int reg; |
2193 | unsigned int offset; | |
2194 | unsigned int predicate; | |
2195 | { | |
2196 | unw_rec_list *ptr = alloc_record (spill_sprel_p); | |
e0c9811a | 2197 | ptr->r.record.x.ab = ab; |
800eeca4 | 2198 | ptr->r.record.x.reg = reg; |
542d6675 | 2199 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2200 | ptr->r.record.x.qp = predicate; |
2201 | return ptr; | |
2202 | } | |
2203 | ||
2204 | static unw_rec_list * | |
e0c9811a JW |
2205 | output_spill_reg (ab, reg, targ_reg, xy) |
2206 | unsigned int ab; | |
800eeca4 JW |
2207 | unsigned int reg; |
2208 | unsigned int targ_reg; | |
2209 | unsigned int xy; | |
2210 | { | |
2211 | unw_rec_list *ptr = alloc_record (spill_reg); | |
e0c9811a | 2212 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2213 | ptr->r.record.x.reg = reg; |
2214 | ptr->r.record.x.treg = targ_reg; | |
2215 | ptr->r.record.x.xy = xy; | |
2216 | return ptr; | |
2217 | } | |
2218 | ||
2219 | static unw_rec_list * | |
e0c9811a JW |
2220 | output_spill_reg_p (ab, reg, targ_reg, xy, predicate) |
2221 | unsigned int ab; | |
800eeca4 JW |
2222 | unsigned int reg; |
2223 | unsigned int targ_reg; | |
2224 | unsigned int xy; | |
2225 | unsigned int predicate; | |
2226 | { | |
2227 | unw_rec_list *ptr = alloc_record (spill_reg_p); | |
e0c9811a | 2228 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2229 | ptr->r.record.x.reg = reg; |
2230 | ptr->r.record.x.treg = targ_reg; | |
2231 | ptr->r.record.x.xy = xy; | |
2232 | ptr->r.record.x.qp = predicate; | |
2233 | return ptr; | |
2234 | } | |
2235 | ||
197865e8 | 2236 | /* Given a unw_rec_list process the correct format with the |
800eeca4 | 2237 | specified function. */ |
542d6675 | 2238 | |
800eeca4 JW |
2239 | static void |
2240 | process_one_record (ptr, f) | |
2241 | unw_rec_list *ptr; | |
2242 | vbyte_func f; | |
2243 | { | |
e0c9811a JW |
2244 | unsigned long fr_mask, gr_mask; |
2245 | ||
197865e8 | 2246 | switch (ptr->r.type) |
800eeca4 | 2247 | { |
542d6675 KH |
2248 | case gr_mem: |
2249 | case fr_mem: | |
2250 | case br_mem: | |
2251 | case frgr_mem: | |
2252 | /* These are taken care of by prologue/prologue_gr. */ | |
2253 | break; | |
e0c9811a | 2254 | |
542d6675 KH |
2255 | case prologue_gr: |
2256 | case prologue: | |
2257 | if (ptr->r.type == prologue_gr) | |
2258 | output_R2_format (f, ptr->r.record.r.grmask, | |
2259 | ptr->r.record.r.grsave, ptr->r.record.r.rlen); | |
2260 | else | |
800eeca4 | 2261 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
542d6675 KH |
2262 | |
2263 | /* Output descriptor(s) for union of register spills (if any). */ | |
2264 | gr_mask = ptr->r.record.r.mask.gr_mem; | |
2265 | fr_mask = ptr->r.record.r.mask.fr_mem; | |
2266 | if (fr_mask) | |
2267 | { | |
2268 | if ((fr_mask & ~0xfUL) == 0) | |
2269 | output_P6_format (f, fr_mem, fr_mask); | |
2270 | else | |
2271 | { | |
2272 | output_P5_format (f, gr_mask, fr_mask); | |
2273 | gr_mask = 0; | |
2274 | } | |
2275 | } | |
2276 | if (gr_mask) | |
2277 | output_P6_format (f, gr_mem, gr_mask); | |
2278 | if (ptr->r.record.r.mask.br_mem) | |
2279 | output_P1_format (f, ptr->r.record.r.mask.br_mem); | |
2280 | ||
2281 | /* output imask descriptor if necessary: */ | |
2282 | if (ptr->r.record.r.mask.i) | |
2283 | output_P4_format (f, ptr->r.record.r.mask.i, | |
2284 | ptr->r.record.r.imask_size); | |
2285 | break; | |
2286 | ||
2287 | case body: | |
2288 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); | |
2289 | break; | |
2290 | case mem_stack_f: | |
2291 | case mem_stack_v: | |
2292 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, | |
2293 | ptr->r.record.p.size); | |
2294 | break; | |
2295 | case psp_gr: | |
2296 | case rp_gr: | |
2297 | case pfs_gr: | |
2298 | case preds_gr: | |
2299 | case unat_gr: | |
2300 | case lc_gr: | |
2301 | case fpsr_gr: | |
2302 | case priunat_gr: | |
2303 | case bsp_gr: | |
2304 | case bspstore_gr: | |
2305 | case rnat_gr: | |
2306 | output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); | |
2307 | break; | |
2308 | case rp_br: | |
2309 | output_P3_format (f, rp_br, ptr->r.record.p.br); | |
2310 | break; | |
2311 | case psp_sprel: | |
2312 | output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); | |
2313 | break; | |
2314 | case rp_when: | |
2315 | case pfs_when: | |
2316 | case preds_when: | |
2317 | case unat_when: | |
2318 | case lc_when: | |
2319 | case fpsr_when: | |
2320 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); | |
2321 | break; | |
2322 | case rp_psprel: | |
2323 | case pfs_psprel: | |
2324 | case preds_psprel: | |
2325 | case unat_psprel: | |
2326 | case lc_psprel: | |
2327 | case fpsr_psprel: | |
2328 | case spill_base: | |
2329 | output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); | |
2330 | break; | |
2331 | case rp_sprel: | |
2332 | case pfs_sprel: | |
2333 | case preds_sprel: | |
2334 | case unat_sprel: | |
2335 | case lc_sprel: | |
2336 | case fpsr_sprel: | |
2337 | case priunat_sprel: | |
2338 | case bsp_sprel: | |
2339 | case bspstore_sprel: | |
2340 | case rnat_sprel: | |
2341 | output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); | |
2342 | break; | |
2343 | case gr_gr: | |
2344 | output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); | |
2345 | break; | |
2346 | case br_gr: | |
2347 | output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); | |
2348 | break; | |
2349 | case spill_mask: | |
2350 | as_bad ("spill_mask record unimplemented."); | |
2351 | break; | |
2352 | case priunat_when_gr: | |
2353 | case priunat_when_mem: | |
2354 | case bsp_when: | |
2355 | case bspstore_when: | |
2356 | case rnat_when: | |
2357 | output_P8_format (f, ptr->r.type, ptr->r.record.p.t); | |
2358 | break; | |
2359 | case priunat_psprel: | |
2360 | case bsp_psprel: | |
2361 | case bspstore_psprel: | |
2362 | case rnat_psprel: | |
2363 | output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); | |
2364 | break; | |
2365 | case unwabi: | |
2366 | output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); | |
2367 | break; | |
2368 | case epilogue: | |
2369 | output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); | |
2370 | break; | |
2371 | case label_state: | |
2372 | case copy_state: | |
2373 | output_B4_format (f, ptr->r.type, ptr->r.record.b.label); | |
2374 | break; | |
2375 | case spill_psprel: | |
2376 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2377 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2378 | ptr->r.record.x.pspoff); | |
2379 | break; | |
2380 | case spill_sprel: | |
2381 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2382 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2383 | ptr->r.record.x.spoff); | |
2384 | break; | |
2385 | case spill_reg: | |
2386 | output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2387 | ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, | |
2388 | ptr->r.record.x.treg, ptr->r.record.x.t); | |
2389 | break; | |
2390 | case spill_psprel_p: | |
2391 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2392 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2393 | ptr->r.record.x.t, ptr->r.record.x.pspoff); | |
2394 | break; | |
2395 | case spill_sprel_p: | |
2396 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2397 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2398 | ptr->r.record.x.t, ptr->r.record.x.spoff); | |
2399 | break; | |
2400 | case spill_reg_p: | |
2401 | output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, | |
2402 | ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, | |
2403 | ptr->r.record.x.xy, ptr->r.record.x.treg, | |
2404 | ptr->r.record.x.t); | |
2405 | break; | |
2406 | default: | |
2407 | as_bad ("record_type_not_valid"); | |
2408 | break; | |
800eeca4 JW |
2409 | } |
2410 | } | |
2411 | ||
197865e8 | 2412 | /* Given a unw_rec_list list, process all the records with |
800eeca4 JW |
2413 | the specified function. */ |
2414 | static void | |
2415 | process_unw_records (list, f) | |
2416 | unw_rec_list *list; | |
2417 | vbyte_func f; | |
2418 | { | |
2419 | unw_rec_list *ptr; | |
2420 | for (ptr = list; ptr; ptr = ptr->next) | |
2421 | process_one_record (ptr, f); | |
2422 | } | |
2423 | ||
2424 | /* Determine the size of a record list in bytes. */ | |
2425 | static int | |
2426 | calc_record_size (list) | |
2427 | unw_rec_list *list; | |
2428 | { | |
2429 | vbyte_count = 0; | |
2430 | process_unw_records (list, count_output); | |
2431 | return vbyte_count; | |
2432 | } | |
2433 | ||
e0c9811a JW |
2434 | /* Update IMASK bitmask to reflect the fact that one or more registers |
2435 | of type TYPE are saved starting at instruction with index T. If N | |
2436 | bits are set in REGMASK, it is assumed that instructions T through | |
2437 | T+N-1 save these registers. | |
2438 | ||
2439 | TYPE values: | |
2440 | 0: no save | |
2441 | 1: instruction saves next fp reg | |
2442 | 2: instruction saves next general reg | |
2443 | 3: instruction saves next branch reg */ | |
2444 | static void | |
2445 | set_imask (region, regmask, t, type) | |
2446 | unw_rec_list *region; | |
2447 | unsigned long regmask; | |
2448 | unsigned long t; | |
2449 | unsigned int type; | |
2450 | { | |
2451 | unsigned char *imask; | |
2452 | unsigned long imask_size; | |
2453 | unsigned int i; | |
2454 | int pos; | |
2455 | ||
2456 | imask = region->r.record.r.mask.i; | |
2457 | imask_size = region->r.record.r.imask_size; | |
2458 | if (!imask) | |
2459 | { | |
542d6675 | 2460 | imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; |
e0c9811a JW |
2461 | imask = xmalloc (imask_size); |
2462 | memset (imask, 0, imask_size); | |
2463 | ||
2464 | region->r.record.r.imask_size = imask_size; | |
2465 | region->r.record.r.mask.i = imask; | |
2466 | } | |
2467 | ||
542d6675 KH |
2468 | i = (t / 4) + 1; |
2469 | pos = 2 * (3 - t % 4); | |
e0c9811a JW |
2470 | while (regmask) |
2471 | { | |
2472 | if (i >= imask_size) | |
2473 | { | |
2474 | as_bad ("Ignoring attempt to spill beyond end of region"); | |
2475 | return; | |
2476 | } | |
2477 | ||
2478 | imask[i] |= (type & 0x3) << pos; | |
197865e8 | 2479 | |
e0c9811a JW |
2480 | regmask &= (regmask - 1); |
2481 | pos -= 2; | |
2482 | if (pos < 0) | |
2483 | { | |
2484 | pos = 0; | |
2485 | ++i; | |
2486 | } | |
2487 | } | |
2488 | } | |
2489 | ||
2490 | static int | |
2491 | count_bits (unsigned long mask) | |
2492 | { | |
2493 | int n = 0; | |
2494 | ||
2495 | while (mask) | |
2496 | { | |
2497 | mask &= mask - 1; | |
2498 | ++n; | |
2499 | } | |
2500 | return n; | |
2501 | } | |
2502 | ||
f5a30c2e JW |
2503 | /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. |
2504 | SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag | |
2505 | containing FIRST_ADDR. */ | |
2506 | ||
e0c9811a | 2507 | unsigned long |
f5a30c2e JW |
2508 | slot_index (slot_addr, slot_frag, first_addr, first_frag) |
2509 | unsigned long slot_addr; | |
2510 | fragS *slot_frag; | |
2511 | unsigned long first_addr; | |
2512 | fragS *first_frag; | |
e0c9811a | 2513 | { |
f5a30c2e JW |
2514 | unsigned long index = 0; |
2515 | ||
2516 | /* First time we are called, the initial address and frag are invalid. */ | |
2517 | if (first_addr == 0) | |
2518 | return 0; | |
2519 | ||
2520 | /* If the two addresses are in different frags, then we need to add in | |
2521 | the remaining size of this frag, and then the entire size of intermediate | |
2522 | frags. */ | |
2523 | while (slot_frag != first_frag) | |
2524 | { | |
2525 | unsigned long start_addr = (unsigned long) &first_frag->fr_literal; | |
2526 | ||
2527 | /* Add in the full size of the frag converted to instruction slots. */ | |
2528 | index += 3 * (first_frag->fr_fix >> 4); | |
2529 | /* Subtract away the initial part before first_addr. */ | |
2530 | index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) | |
2531 | + ((first_addr & 0x3) - (start_addr & 0x3))); | |
e0c9811a | 2532 | |
f5a30c2e JW |
2533 | /* Move to the beginning of the next frag. */ |
2534 | first_frag = first_frag->fr_next; | |
2535 | first_addr = (unsigned long) &first_frag->fr_literal; | |
2536 | } | |
2537 | ||
2538 | /* Add in the used part of the last frag. */ | |
2539 | index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) | |
2540 | + ((slot_addr & 0x3) - (first_addr & 0x3))); | |
2541 | return index; | |
2542 | } | |
4a1805b1 | 2543 | |
91a2ae2a RH |
2544 | /* Optimize unwind record directives. */ |
2545 | ||
2546 | static unw_rec_list * | |
2547 | optimize_unw_records (list) | |
2548 | unw_rec_list *list; | |
2549 | { | |
2550 | if (!list) | |
2551 | return NULL; | |
2552 | ||
2553 | /* If the only unwind record is ".prologue" or ".prologue" followed | |
2554 | by ".body", then we can optimize the unwind directives away. */ | |
2555 | if (list->r.type == prologue | |
2556 | && (list->next == NULL | |
2557 | || (list->next->r.type == body && list->next->next == NULL))) | |
2558 | return NULL; | |
2559 | ||
2560 | return list; | |
2561 | } | |
2562 | ||
800eeca4 JW |
2563 | /* Given a complete record list, process any records which have |
2564 | unresolved fields, (ie length counts for a prologue). After | |
197865e8 | 2565 | this has been run, all neccessary information should be available |
800eeca4 | 2566 | within each record to generate an image. */ |
542d6675 | 2567 | |
800eeca4 JW |
2568 | static void |
2569 | fixup_unw_records (list) | |
2570 | unw_rec_list *list; | |
2571 | { | |
e0c9811a JW |
2572 | unw_rec_list *ptr, *region = 0; |
2573 | unsigned long first_addr = 0, rlen = 0, t; | |
f5a30c2e | 2574 | fragS *first_frag = 0; |
e0c9811a | 2575 | |
800eeca4 JW |
2576 | for (ptr = list; ptr; ptr = ptr->next) |
2577 | { | |
2578 | if (ptr->slot_number == SLOT_NUM_NOT_SET) | |
542d6675 | 2579 | as_bad (" Insn slot not set in unwind record."); |
f5a30c2e JW |
2580 | t = slot_index (ptr->slot_number, ptr->slot_frag, |
2581 | first_addr, first_frag); | |
800eeca4 JW |
2582 | switch (ptr->r.type) |
2583 | { | |
542d6675 KH |
2584 | case prologue: |
2585 | case prologue_gr: | |
2586 | case body: | |
2587 | { | |
2588 | unw_rec_list *last; | |
2589 | int size, dir_len = 0; | |
2590 | unsigned long last_addr; | |
f5a30c2e | 2591 | fragS *last_frag; |
542d6675 KH |
2592 | |
2593 | first_addr = ptr->slot_number; | |
f5a30c2e | 2594 | first_frag = ptr->slot_frag; |
542d6675 KH |
2595 | ptr->slot_number = 0; |
2596 | /* Find either the next body/prologue start, or the end of | |
2597 | the list, and determine the size of the region. */ | |
2598 | last_addr = unwind.next_slot_number; | |
f5a30c2e | 2599 | last_frag = unwind.next_slot_frag; |
542d6675 KH |
2600 | for (last = ptr->next; last != NULL; last = last->next) |
2601 | if (last->r.type == prologue || last->r.type == prologue_gr | |
2602 | || last->r.type == body) | |
2603 | { | |
2604 | last_addr = last->slot_number; | |
f5a30c2e | 2605 | last_frag = last->slot_frag; |
542d6675 KH |
2606 | break; |
2607 | } | |
2608 | else if (!last->next) | |
2609 | { | |
2610 | /* In the absence of an explicit .body directive, | |
2611 | the prologue ends after the last instruction | |
2612 | covered by an unwind directive. */ | |
2613 | if (ptr->r.type != body) | |
2614 | { | |
2615 | last_addr = last->slot_number; | |
f5a30c2e | 2616 | last_frag = last->slot_frag; |
542d6675 KH |
2617 | switch (last->r.type) |
2618 | { | |
2619 | case frgr_mem: | |
2620 | dir_len = (count_bits (last->r.record.p.frmask) | |
2621 | + count_bits (last->r.record.p.grmask)); | |
2622 | break; | |
2623 | case fr_mem: | |
2624 | case gr_mem: | |
2625 | dir_len += count_bits (last->r.record.p.rmask); | |
2626 | break; | |
2627 | case br_mem: | |
2628 | case br_gr: | |
2629 | dir_len += count_bits (last->r.record.p.brmask); | |
2630 | break; | |
2631 | case gr_gr: | |
2632 | dir_len += count_bits (last->r.record.p.grmask); | |
2633 | break; | |
2634 | default: | |
2635 | dir_len = 1; | |
2636 | break; | |
2637 | } | |
2638 | } | |
2639 | break; | |
2640 | } | |
f5a30c2e JW |
2641 | size = (slot_index (last_addr, last_frag, first_addr, first_frag) |
2642 | + dir_len); | |
542d6675 KH |
2643 | rlen = ptr->r.record.r.rlen = size; |
2644 | region = ptr; | |
e0c9811a | 2645 | break; |
542d6675 KH |
2646 | } |
2647 | case epilogue: | |
2648 | ptr->r.record.b.t = rlen - 1 - t; | |
2649 | break; | |
e0c9811a | 2650 | |
542d6675 KH |
2651 | case mem_stack_f: |
2652 | case mem_stack_v: | |
2653 | case rp_when: | |
2654 | case pfs_when: | |
2655 | case preds_when: | |
2656 | case unat_when: | |
2657 | case lc_when: | |
2658 | case fpsr_when: | |
2659 | case priunat_when_gr: | |
2660 | case priunat_when_mem: | |
2661 | case bsp_when: | |
2662 | case bspstore_when: | |
2663 | case rnat_when: | |
2664 | ptr->r.record.p.t = t; | |
2665 | break; | |
e0c9811a | 2666 | |
542d6675 KH |
2667 | case spill_reg: |
2668 | case spill_sprel: | |
2669 | case spill_psprel: | |
2670 | case spill_reg_p: | |
2671 | case spill_sprel_p: | |
2672 | case spill_psprel_p: | |
2673 | ptr->r.record.x.t = t; | |
2674 | break; | |
e0c9811a | 2675 | |
542d6675 KH |
2676 | case frgr_mem: |
2677 | if (!region) | |
2678 | { | |
2679 | as_bad ("frgr_mem record before region record!\n"); | |
2680 | return; | |
2681 | } | |
2682 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; | |
2683 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; | |
2684 | set_imask (region, ptr->r.record.p.frmask, t, 1); | |
2685 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2686 | break; | |
2687 | case fr_mem: | |
2688 | if (!region) | |
2689 | { | |
2690 | as_bad ("fr_mem record before region record!\n"); | |
2691 | return; | |
2692 | } | |
2693 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; | |
2694 | set_imask (region, ptr->r.record.p.rmask, t, 1); | |
2695 | break; | |
2696 | case gr_mem: | |
2697 | if (!region) | |
2698 | { | |
2699 | as_bad ("gr_mem record before region record!\n"); | |
2700 | return; | |
2701 | } | |
2702 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; | |
2703 | set_imask (region, ptr->r.record.p.rmask, t, 2); | |
2704 | break; | |
2705 | case br_mem: | |
2706 | if (!region) | |
2707 | { | |
2708 | as_bad ("br_mem record before region record!\n"); | |
2709 | return; | |
2710 | } | |
2711 | region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; | |
2712 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2713 | break; | |
e0c9811a | 2714 | |
542d6675 KH |
2715 | case gr_gr: |
2716 | if (!region) | |
2717 | { | |
2718 | as_bad ("gr_gr record before region record!\n"); | |
2719 | return; | |
2720 | } | |
2721 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2722 | break; | |
2723 | case br_gr: | |
2724 | if (!region) | |
2725 | { | |
2726 | as_bad ("br_gr record before region record!\n"); | |
2727 | return; | |
2728 | } | |
2729 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2730 | break; | |
e0c9811a | 2731 | |
542d6675 KH |
2732 | default: |
2733 | break; | |
800eeca4 JW |
2734 | } |
2735 | } | |
2736 | } | |
2737 | ||
2738 | /* Generate an unwind image from a record list. Returns the number of | |
2739 | bytes in the resulting image. The memory image itselof is returned | |
2740 | in the 'ptr' parameter. */ | |
2741 | static int | |
2742 | output_unw_records (list, ptr) | |
2743 | unw_rec_list *list; | |
2744 | void **ptr; | |
2745 | { | |
2746 | int size, x, extra = 0; | |
2747 | unsigned char *mem; | |
2748 | ||
91a2ae2a RH |
2749 | *ptr = NULL; |
2750 | ||
2751 | list = optimize_unw_records (list); | |
800eeca4 JW |
2752 | fixup_unw_records (list); |
2753 | size = calc_record_size (list); | |
2754 | ||
2755 | /* pad to 8 byte boundry. */ | |
2756 | x = size % 8; | |
2757 | if (x != 0) | |
2758 | extra = 8 - x; | |
800eeca4 | 2759 | |
91a2ae2a RH |
2760 | if (size > 0 || unwind.force_unwind_entry) |
2761 | { | |
2762 | unwind.force_unwind_entry = 0; | |
2763 | ||
2764 | /* Add 8 for the header + 8 more bytes for the personality offset. */ | |
2765 | mem = xmalloc (size + extra + 16); | |
800eeca4 | 2766 | |
91a2ae2a RH |
2767 | vbyte_mem_ptr = mem + 8; |
2768 | /* Clear the padding area and personality. */ | |
2769 | memset (mem + 8 + size, 0 , extra + 8); | |
2770 | /* Initialize the header area. */ | |
2771 | md_number_to_chars (mem, | |
2772 | (((bfd_vma) 1 << 48) /* version */ | |
2773 | | (unwind.personality_routine | |
2774 | ? ((bfd_vma) 3 << 32) /* U & E handler flags */ | |
2775 | : 0) | |
2776 | | ((size + extra) / 8)), /* length (dwords) */ | |
2777 | 8); | |
800eeca4 | 2778 | |
91a2ae2a RH |
2779 | process_unw_records (list, output_vbyte_mem); |
2780 | ||
2781 | *ptr = mem; | |
2782 | ||
2783 | size += extra + 16; | |
2784 | } | |
2785 | return size; | |
800eeca4 JW |
2786 | } |
2787 | ||
e0c9811a JW |
2788 | static int |
2789 | convert_expr_to_ab_reg (e, ab, regp) | |
2790 | expressionS *e; | |
2791 | unsigned int *ab; | |
2792 | unsigned int *regp; | |
2793 | { | |
2794 | unsigned int reg; | |
2795 | ||
2796 | if (e->X_op != O_register) | |
2797 | return 0; | |
2798 | ||
2799 | reg = e->X_add_number; | |
2434f565 | 2800 | if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) |
e0c9811a JW |
2801 | { |
2802 | *ab = 0; | |
2803 | *regp = reg - REG_GR; | |
2804 | } | |
2434f565 JW |
2805 | else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) |
2806 | || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) | |
e0c9811a JW |
2807 | { |
2808 | *ab = 1; | |
2809 | *regp = reg - REG_FR; | |
2810 | } | |
2434f565 | 2811 | else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) |
e0c9811a JW |
2812 | { |
2813 | *ab = 2; | |
2814 | *regp = reg - REG_BR; | |
2815 | } | |
2816 | else | |
2817 | { | |
2818 | *ab = 3; | |
2819 | switch (reg) | |
2820 | { | |
2821 | case REG_PR: *regp = 0; break; | |
2822 | case REG_PSP: *regp = 1; break; | |
2823 | case REG_PRIUNAT: *regp = 2; break; | |
2824 | case REG_BR + 0: *regp = 3; break; | |
2825 | case REG_AR + AR_BSP: *regp = 4; break; | |
2826 | case REG_AR + AR_BSPSTORE: *regp = 5; break; | |
2827 | case REG_AR + AR_RNAT: *regp = 6; break; | |
2828 | case REG_AR + AR_UNAT: *regp = 7; break; | |
2829 | case REG_AR + AR_FPSR: *regp = 8; break; | |
2830 | case REG_AR + AR_PFS: *regp = 9; break; | |
2831 | case REG_AR + AR_LC: *regp = 10; break; | |
2832 | ||
2833 | default: | |
2834 | return 0; | |
2835 | } | |
2836 | } | |
2837 | return 1; | |
197865e8 | 2838 | } |
e0c9811a JW |
2839 | |
2840 | static int | |
2841 | convert_expr_to_xy_reg (e, xy, regp) | |
2842 | expressionS *e; | |
2843 | unsigned int *xy; | |
2844 | unsigned int *regp; | |
2845 | { | |
2846 | unsigned int reg; | |
2847 | ||
2848 | if (e->X_op != O_register) | |
2849 | return 0; | |
2850 | ||
2851 | reg = e->X_add_number; | |
2852 | ||
2434f565 | 2853 | if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) |
e0c9811a JW |
2854 | { |
2855 | *xy = 0; | |
2856 | *regp = reg - REG_GR; | |
2857 | } | |
2434f565 | 2858 | else if (reg >= REG_FR && reg <= (REG_FR + 127)) |
e0c9811a JW |
2859 | { |
2860 | *xy = 1; | |
2861 | *regp = reg - REG_FR; | |
2862 | } | |
2434f565 | 2863 | else if (reg >= REG_BR && reg <= (REG_BR + 7)) |
e0c9811a JW |
2864 | { |
2865 | *xy = 2; | |
2866 | *regp = reg - REG_BR; | |
2867 | } | |
2868 | else | |
2869 | return -1; | |
2870 | return 1; | |
197865e8 | 2871 | } |
e0c9811a | 2872 | |
800eeca4 JW |
2873 | static void |
2874 | dot_radix (dummy) | |
2434f565 | 2875 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
2876 | { |
2877 | int radix; | |
2878 | ||
2879 | SKIP_WHITESPACE (); | |
2880 | radix = *input_line_pointer++; | |
2881 | ||
2882 | if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) | |
2883 | { | |
2884 | as_bad ("Radix `%c' unsupported", *input_line_pointer); | |
542d6675 | 2885 | ignore_rest_of_line (); |
800eeca4 JW |
2886 | return; |
2887 | } | |
2888 | } | |
2889 | ||
2890 | /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ | |
2891 | static void | |
2892 | dot_special_section (which) | |
2893 | int which; | |
2894 | { | |
2895 | set_section ((char *) special_section_name[which]); | |
2896 | } | |
2897 | ||
2898 | static void | |
2899 | add_unwind_entry (ptr) | |
2900 | unw_rec_list *ptr; | |
2901 | { | |
e0c9811a JW |
2902 | if (unwind.tail) |
2903 | unwind.tail->next = ptr; | |
800eeca4 | 2904 | else |
e0c9811a JW |
2905 | unwind.list = ptr; |
2906 | unwind.tail = ptr; | |
800eeca4 JW |
2907 | |
2908 | /* The current entry can in fact be a chain of unwind entries. */ | |
e0c9811a JW |
2909 | if (unwind.current_entry == NULL) |
2910 | unwind.current_entry = ptr; | |
800eeca4 JW |
2911 | } |
2912 | ||
197865e8 | 2913 | static void |
800eeca4 | 2914 | dot_fframe (dummy) |
2434f565 | 2915 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
2916 | { |
2917 | expressionS e; | |
e0c9811a | 2918 | |
800eeca4 | 2919 | parse_operand (&e); |
197865e8 | 2920 | |
800eeca4 JW |
2921 | if (e.X_op != O_constant) |
2922 | as_bad ("Operand to .fframe must be a constant"); | |
2923 | else | |
e0c9811a JW |
2924 | add_unwind_entry (output_mem_stack_f (e.X_add_number)); |
2925 | } | |
2926 | ||
197865e8 | 2927 | static void |
e0c9811a | 2928 | dot_vframe (dummy) |
2434f565 | 2929 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
2930 | { |
2931 | expressionS e; | |
2932 | unsigned reg; | |
2933 | ||
2934 | parse_operand (&e); | |
2935 | reg = e.X_add_number - REG_GR; | |
2936 | if (e.X_op == O_register && reg < 128) | |
800eeca4 | 2937 | { |
e0c9811a | 2938 | add_unwind_entry (output_mem_stack_v ()); |
30d25259 RH |
2939 | if (! (unwind.prologue_mask & 2)) |
2940 | add_unwind_entry (output_psp_gr (reg)); | |
800eeca4 | 2941 | } |
e0c9811a JW |
2942 | else |
2943 | as_bad ("First operand to .vframe must be a general register"); | |
800eeca4 JW |
2944 | } |
2945 | ||
197865e8 | 2946 | static void |
e0c9811a | 2947 | dot_vframesp (dummy) |
2434f565 | 2948 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 2949 | { |
e0c9811a JW |
2950 | expressionS e; |
2951 | ||
2952 | parse_operand (&e); | |
2953 | if (e.X_op == O_constant) | |
2954 | { | |
2955 | add_unwind_entry (output_mem_stack_v ()); | |
2956 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
2957 | } | |
2958 | else | |
2959 | as_bad ("First operand to .vframesp must be a general register"); | |
2960 | } | |
2961 | ||
197865e8 | 2962 | static void |
e0c9811a | 2963 | dot_vframepsp (dummy) |
2434f565 | 2964 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
2965 | { |
2966 | expressionS e; | |
2967 | ||
2968 | parse_operand (&e); | |
2969 | if (e.X_op == O_constant) | |
2970 | { | |
2971 | add_unwind_entry (output_mem_stack_v ()); | |
2972 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
2973 | } | |
2974 | else | |
2975 | as_bad ("First operand to .vframepsp must be a general register"); | |
800eeca4 JW |
2976 | } |
2977 | ||
197865e8 | 2978 | static void |
800eeca4 | 2979 | dot_save (dummy) |
2434f565 | 2980 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
2981 | { |
2982 | expressionS e1, e2; | |
2983 | int sep; | |
2984 | int reg1, reg2; | |
2985 | ||
2986 | sep = parse_operand (&e1); | |
2987 | if (sep != ',') | |
2988 | as_bad ("No second operand to .save"); | |
2989 | sep = parse_operand (&e2); | |
2990 | ||
e0c9811a | 2991 | reg1 = e1.X_add_number; |
800eeca4 | 2992 | reg2 = e2.X_add_number - REG_GR; |
197865e8 | 2993 | |
800eeca4 | 2994 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 2995 | if (e1.X_op == O_register) |
800eeca4 | 2996 | { |
542d6675 | 2997 | if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) |
800eeca4 JW |
2998 | { |
2999 | switch (reg1) | |
3000 | { | |
542d6675 KH |
3001 | case REG_AR + AR_BSP: |
3002 | add_unwind_entry (output_bsp_when ()); | |
3003 | add_unwind_entry (output_bsp_gr (reg2)); | |
3004 | break; | |
3005 | case REG_AR + AR_BSPSTORE: | |
3006 | add_unwind_entry (output_bspstore_when ()); | |
3007 | add_unwind_entry (output_bspstore_gr (reg2)); | |
3008 | break; | |
3009 | case REG_AR + AR_RNAT: | |
3010 | add_unwind_entry (output_rnat_when ()); | |
3011 | add_unwind_entry (output_rnat_gr (reg2)); | |
3012 | break; | |
3013 | case REG_AR + AR_UNAT: | |
3014 | add_unwind_entry (output_unat_when ()); | |
3015 | add_unwind_entry (output_unat_gr (reg2)); | |
3016 | break; | |
3017 | case REG_AR + AR_FPSR: | |
3018 | add_unwind_entry (output_fpsr_when ()); | |
3019 | add_unwind_entry (output_fpsr_gr (reg2)); | |
3020 | break; | |
3021 | case REG_AR + AR_PFS: | |
3022 | add_unwind_entry (output_pfs_when ()); | |
3023 | if (! (unwind.prologue_mask & 4)) | |
3024 | add_unwind_entry (output_pfs_gr (reg2)); | |
3025 | break; | |
3026 | case REG_AR + AR_LC: | |
3027 | add_unwind_entry (output_lc_when ()); | |
3028 | add_unwind_entry (output_lc_gr (reg2)); | |
3029 | break; | |
3030 | case REG_BR: | |
3031 | add_unwind_entry (output_rp_when ()); | |
3032 | if (! (unwind.prologue_mask & 8)) | |
3033 | add_unwind_entry (output_rp_gr (reg2)); | |
3034 | break; | |
3035 | case REG_PR: | |
3036 | add_unwind_entry (output_preds_when ()); | |
3037 | if (! (unwind.prologue_mask & 1)) | |
3038 | add_unwind_entry (output_preds_gr (reg2)); | |
3039 | break; | |
3040 | case REG_PRIUNAT: | |
3041 | add_unwind_entry (output_priunat_when_gr ()); | |
3042 | add_unwind_entry (output_priunat_gr (reg2)); | |
3043 | break; | |
3044 | default: | |
3045 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
3046 | } |
3047 | } | |
3048 | else | |
3049 | as_bad (" Second operand not a valid register"); | |
3050 | } | |
3051 | else | |
e0c9811a | 3052 | as_bad ("First operand not a register"); |
800eeca4 JW |
3053 | } |
3054 | ||
197865e8 | 3055 | static void |
800eeca4 | 3056 | dot_restore (dummy) |
2434f565 | 3057 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3058 | { |
e0c9811a | 3059 | expressionS e1, e2; |
33d01f33 | 3060 | unsigned long ecount; /* # of _additional_ regions to pop */ |
e0c9811a JW |
3061 | int sep; |
3062 | ||
3063 | sep = parse_operand (&e1); | |
3064 | if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) | |
3065 | { | |
3066 | as_bad ("First operand to .restore must be stack pointer (sp)"); | |
3067 | return; | |
3068 | } | |
3069 | ||
3070 | if (sep == ',') | |
3071 | { | |
3072 | parse_operand (&e2); | |
33d01f33 | 3073 | if (e2.X_op != O_constant || e2.X_add_number < 0) |
e0c9811a | 3074 | { |
33d01f33 | 3075 | as_bad ("Second operand to .restore must be a constant >= 0"); |
e0c9811a JW |
3076 | return; |
3077 | } | |
33d01f33 | 3078 | ecount = e2.X_add_number; |
e0c9811a | 3079 | } |
33d01f33 JW |
3080 | else |
3081 | ecount = unwind.prologue_count - 1; | |
e0c9811a | 3082 | add_unwind_entry (output_epilogue (ecount)); |
33d01f33 JW |
3083 | |
3084 | if (ecount < unwind.prologue_count) | |
3085 | unwind.prologue_count -= ecount + 1; | |
3086 | else | |
3087 | unwind.prologue_count = 0; | |
e0c9811a JW |
3088 | } |
3089 | ||
197865e8 | 3090 | static void |
e0c9811a | 3091 | dot_restorereg (dummy) |
2434f565 | 3092 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3093 | { |
3094 | unsigned int ab, reg; | |
3095 | expressionS e; | |
3096 | ||
3097 | parse_operand (&e); | |
3098 | ||
3099 | if (!convert_expr_to_ab_reg (&e, &ab, ®)) | |
3100 | { | |
3101 | as_bad ("First operand to .restorereg must be a preserved register"); | |
3102 | return; | |
3103 | } | |
3104 | add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); | |
3105 | } | |
3106 | ||
197865e8 | 3107 | static void |
e0c9811a | 3108 | dot_restorereg_p (dummy) |
2434f565 | 3109 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3110 | { |
3111 | unsigned int qp, ab, reg; | |
3112 | expressionS e1, e2; | |
3113 | int sep; | |
3114 | ||
3115 | sep = parse_operand (&e1); | |
3116 | if (sep != ',') | |
3117 | { | |
3118 | as_bad ("No second operand to .restorereg.p"); | |
3119 | return; | |
3120 | } | |
3121 | ||
3122 | parse_operand (&e2); | |
3123 | ||
3124 | qp = e1.X_add_number - REG_P; | |
3125 | if (e1.X_op != O_register || qp > 63) | |
3126 | { | |
3127 | as_bad ("First operand to .restorereg.p must be a predicate"); | |
3128 | return; | |
3129 | } | |
3130 | ||
3131 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3132 | { | |
3133 | as_bad ("Second operand to .restorereg.p must be a preserved register"); | |
3134 | return; | |
3135 | } | |
3136 | add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); | |
800eeca4 JW |
3137 | } |
3138 | ||
3139 | static int | |
91a2ae2a RH |
3140 | generate_unwind_image (text_name) |
3141 | const char *text_name; | |
800eeca4 JW |
3142 | { |
3143 | int size; | |
3144 | unsigned char *unw_rec; | |
800eeca4 | 3145 | |
10850f29 JW |
3146 | /* Force out pending instructions, to make sure all unwind records have |
3147 | a valid slot_number field. */ | |
3148 | ia64_flush_insns (); | |
3149 | ||
800eeca4 | 3150 | /* Generate the unwind record. */ |
150f24a2 | 3151 | size = output_unw_records (unwind.list, (void **) &unw_rec); |
e0c9811a JW |
3152 | if (size % 8 != 0) |
3153 | as_bad ("Unwind record is not a multiple of 8 bytes."); | |
800eeca4 JW |
3154 | |
3155 | /* If there are unwind records, switch sections, and output the info. */ | |
3156 | if (size != 0) | |
3157 | { | |
800eeca4 | 3158 | unsigned char *where; |
91a2ae2a | 3159 | char *sec_name; |
800eeca4 | 3160 | expressionS exp; |
91a2ae2a RH |
3161 | |
3162 | make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name); | |
3163 | set_section (sec_name); | |
3164 | bfd_set_section_flags (stdoutput, now_seg, | |
3165 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); | |
800eeca4 | 3166 | |
5e7474a7 JW |
3167 | /* Make sure the section has 8 byte alignment. */ |
3168 | record_alignment (now_seg, 3); | |
3169 | ||
800eeca4 | 3170 | /* Set expression which points to start of unwind descriptor area. */ |
e0c9811a | 3171 | unwind.info = expr_build_dot (); |
800eeca4 | 3172 | |
542d6675 | 3173 | where = (unsigned char *) frag_more (size); |
800eeca4 JW |
3174 | |
3175 | /* Issue a label for this address, and keep track of it to put it | |
3176 | in the unwind section. */ | |
3177 | ||
3178 | /* Copy the information from the unwind record into this section. The | |
3179 | data is already in the correct byte order. */ | |
3180 | memcpy (where, unw_rec, size); | |
91a2ae2a | 3181 | |
800eeca4 | 3182 | /* Add the personality address to the image. */ |
e0c9811a | 3183 | if (unwind.personality_routine != 0) |
542d6675 | 3184 | { |
800eeca4 | 3185 | exp.X_op = O_symbol; |
e0c9811a | 3186 | exp.X_add_symbol = unwind.personality_routine; |
800eeca4 JW |
3187 | exp.X_add_number = 0; |
3188 | fix_new_exp (frag_now, frag_now_fix () - 8, 8, | |
3189 | &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB); | |
e0c9811a | 3190 | unwind.personality_routine = 0; |
542d6675 | 3191 | } |
800eeca4 JW |
3192 | } |
3193 | ||
e0c9811a JW |
3194 | free_list_records (unwind.list); |
3195 | unwind.list = unwind.tail = unwind.current_entry = NULL; | |
800eeca4 JW |
3196 | |
3197 | return size; | |
3198 | } | |
3199 | ||
197865e8 | 3200 | static void |
542d6675 | 3201 | dot_handlerdata (dummy) |
2434f565 | 3202 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3203 | { |
91a2ae2a RH |
3204 | const char *text_name = segment_name (now_seg); |
3205 | ||
3206 | /* If text section name starts with ".text" (which it should), | |
3207 | strip this prefix off. */ | |
3208 | if (strcmp (text_name, ".text") == 0) | |
3209 | text_name = ""; | |
3210 | ||
3211 | unwind.force_unwind_entry = 1; | |
3212 | ||
3213 | /* Remember which segment we're in so we can switch back after .endp */ | |
3214 | unwind.saved_text_seg = now_seg; | |
3215 | unwind.saved_text_subseg = now_subseg; | |
3216 | ||
3217 | /* Generate unwind info into unwind-info section and then leave that | |
3218 | section as the currently active one so dataXX directives go into | |
3219 | the language specific data area of the unwind info block. */ | |
3220 | generate_unwind_image (text_name); | |
e0c9811a | 3221 | demand_empty_rest_of_line (); |
800eeca4 JW |
3222 | } |
3223 | ||
197865e8 | 3224 | static void |
800eeca4 | 3225 | dot_unwentry (dummy) |
2434f565 | 3226 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3227 | { |
91a2ae2a | 3228 | unwind.force_unwind_entry = 1; |
e0c9811a | 3229 | demand_empty_rest_of_line (); |
800eeca4 JW |
3230 | } |
3231 | ||
197865e8 | 3232 | static void |
800eeca4 | 3233 | dot_altrp (dummy) |
2434f565 | 3234 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3235 | { |
e0c9811a JW |
3236 | expressionS e; |
3237 | unsigned reg; | |
3238 | ||
3239 | parse_operand (&e); | |
3240 | reg = e.X_add_number - REG_BR; | |
3241 | if (e.X_op == O_register && reg < 8) | |
3242 | add_unwind_entry (output_rp_br (reg)); | |
3243 | else | |
3244 | as_bad ("First operand not a valid branch register"); | |
800eeca4 JW |
3245 | } |
3246 | ||
197865e8 | 3247 | static void |
e0c9811a JW |
3248 | dot_savemem (psprel) |
3249 | int psprel; | |
800eeca4 JW |
3250 | { |
3251 | expressionS e1, e2; | |
3252 | int sep; | |
3253 | int reg1, val; | |
3254 | ||
3255 | sep = parse_operand (&e1); | |
3256 | if (sep != ',') | |
e0c9811a | 3257 | as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); |
800eeca4 JW |
3258 | sep = parse_operand (&e2); |
3259 | ||
e0c9811a | 3260 | reg1 = e1.X_add_number; |
800eeca4 | 3261 | val = e2.X_add_number; |
197865e8 | 3262 | |
800eeca4 | 3263 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 3264 | if (e1.X_op == O_register) |
800eeca4 JW |
3265 | { |
3266 | if (e2.X_op == O_constant) | |
3267 | { | |
3268 | switch (reg1) | |
3269 | { | |
542d6675 KH |
3270 | case REG_AR + AR_BSP: |
3271 | add_unwind_entry (output_bsp_when ()); | |
3272 | add_unwind_entry ((psprel | |
3273 | ? output_bsp_psprel | |
3274 | : output_bsp_sprel) (val)); | |
3275 | break; | |
3276 | case REG_AR + AR_BSPSTORE: | |
3277 | add_unwind_entry (output_bspstore_when ()); | |
3278 | add_unwind_entry ((psprel | |
3279 | ? output_bspstore_psprel | |
3280 | : output_bspstore_sprel) (val)); | |
3281 | break; | |
3282 | case REG_AR + AR_RNAT: | |
3283 | add_unwind_entry (output_rnat_when ()); | |
3284 | add_unwind_entry ((psprel | |
3285 | ? output_rnat_psprel | |
3286 | : output_rnat_sprel) (val)); | |
3287 | break; | |
3288 | case REG_AR + AR_UNAT: | |
3289 | add_unwind_entry (output_unat_when ()); | |
3290 | add_unwind_entry ((psprel | |
3291 | ? output_unat_psprel | |
3292 | : output_unat_sprel) (val)); | |
3293 | break; | |
3294 | case REG_AR + AR_FPSR: | |
3295 | add_unwind_entry (output_fpsr_when ()); | |
3296 | add_unwind_entry ((psprel | |
3297 | ? output_fpsr_psprel | |
3298 | : output_fpsr_sprel) (val)); | |
3299 | break; | |
3300 | case REG_AR + AR_PFS: | |
3301 | add_unwind_entry (output_pfs_when ()); | |
3302 | add_unwind_entry ((psprel | |
3303 | ? output_pfs_psprel | |
3304 | : output_pfs_sprel) (val)); | |
3305 | break; | |
3306 | case REG_AR + AR_LC: | |
3307 | add_unwind_entry (output_lc_when ()); | |
3308 | add_unwind_entry ((psprel | |
3309 | ? output_lc_psprel | |
3310 | : output_lc_sprel) (val)); | |
3311 | break; | |
3312 | case REG_BR: | |
3313 | add_unwind_entry (output_rp_when ()); | |
3314 | add_unwind_entry ((psprel | |
3315 | ? output_rp_psprel | |
3316 | : output_rp_sprel) (val)); | |
3317 | break; | |
3318 | case REG_PR: | |
3319 | add_unwind_entry (output_preds_when ()); | |
3320 | add_unwind_entry ((psprel | |
3321 | ? output_preds_psprel | |
3322 | : output_preds_sprel) (val)); | |
3323 | break; | |
3324 | case REG_PRIUNAT: | |
3325 | add_unwind_entry (output_priunat_when_mem ()); | |
3326 | add_unwind_entry ((psprel | |
3327 | ? output_priunat_psprel | |
3328 | : output_priunat_sprel) (val)); | |
3329 | break; | |
3330 | default: | |
3331 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
3332 | } |
3333 | } | |
3334 | else | |
3335 | as_bad (" Second operand not a valid constant"); | |
3336 | } | |
3337 | else | |
e0c9811a | 3338 | as_bad ("First operand not a register"); |
800eeca4 JW |
3339 | } |
3340 | ||
197865e8 | 3341 | static void |
800eeca4 | 3342 | dot_saveg (dummy) |
2434f565 | 3343 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3344 | { |
3345 | expressionS e1, e2; | |
3346 | int sep; | |
3347 | sep = parse_operand (&e1); | |
3348 | if (sep == ',') | |
3349 | parse_operand (&e2); | |
197865e8 | 3350 | |
800eeca4 JW |
3351 | if (e1.X_op != O_constant) |
3352 | as_bad ("First operand to .save.g must be a constant."); | |
3353 | else | |
3354 | { | |
3355 | int grmask = e1.X_add_number; | |
3356 | if (sep != ',') | |
3357 | add_unwind_entry (output_gr_mem (grmask)); | |
3358 | else | |
542d6675 | 3359 | { |
800eeca4 | 3360 | int reg = e2.X_add_number - REG_GR; |
542d6675 | 3361 | if (e2.X_op == O_register && reg >= 0 && reg < 128) |
800eeca4 JW |
3362 | add_unwind_entry (output_gr_gr (grmask, reg)); |
3363 | else | |
3364 | as_bad ("Second operand is an invalid register."); | |
3365 | } | |
3366 | } | |
3367 | } | |
3368 | ||
197865e8 | 3369 | static void |
800eeca4 | 3370 | dot_savef (dummy) |
2434f565 | 3371 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3372 | { |
e0c9811a | 3373 | expressionS e1; |
800eeca4 JW |
3374 | int sep; |
3375 | sep = parse_operand (&e1); | |
197865e8 | 3376 | |
800eeca4 JW |
3377 | if (e1.X_op != O_constant) |
3378 | as_bad ("Operand to .save.f must be a constant."); | |
3379 | else | |
e0c9811a | 3380 | add_unwind_entry (output_fr_mem (e1.X_add_number)); |
800eeca4 JW |
3381 | } |
3382 | ||
197865e8 | 3383 | static void |
800eeca4 | 3384 | dot_saveb (dummy) |
2434f565 | 3385 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3386 | { |
e0c9811a JW |
3387 | expressionS e1, e2; |
3388 | unsigned int reg; | |
3389 | unsigned char sep; | |
3390 | int brmask; | |
3391 | ||
800eeca4 | 3392 | sep = parse_operand (&e1); |
800eeca4 | 3393 | if (e1.X_op != O_constant) |
800eeca4 | 3394 | { |
e0c9811a JW |
3395 | as_bad ("First operand to .save.b must be a constant."); |
3396 | return; | |
800eeca4 | 3397 | } |
e0c9811a JW |
3398 | brmask = e1.X_add_number; |
3399 | ||
3400 | if (sep == ',') | |
3401 | { | |
3402 | sep = parse_operand (&e2); | |
3403 | reg = e2.X_add_number - REG_GR; | |
3404 | if (e2.X_op != O_register || reg > 127) | |
3405 | { | |
3406 | as_bad ("Second operand to .save.b must be a general register."); | |
3407 | return; | |
3408 | } | |
3409 | add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); | |
3410 | } | |
3411 | else | |
3412 | add_unwind_entry (output_br_mem (brmask)); | |
3413 | ||
3414 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3415 | ignore_rest_of_line (); | |
800eeca4 JW |
3416 | } |
3417 | ||
197865e8 | 3418 | static void |
800eeca4 | 3419 | dot_savegf (dummy) |
2434f565 | 3420 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3421 | { |
3422 | expressionS e1, e2; | |
3423 | int sep; | |
3424 | sep = parse_operand (&e1); | |
3425 | if (sep == ',') | |
3426 | parse_operand (&e2); | |
197865e8 | 3427 | |
800eeca4 JW |
3428 | if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) |
3429 | as_bad ("Both operands of .save.gf must be constants."); | |
3430 | else | |
3431 | { | |
3432 | int grmask = e1.X_add_number; | |
3433 | int frmask = e2.X_add_number; | |
3434 | add_unwind_entry (output_frgr_mem (grmask, frmask)); | |
3435 | } | |
3436 | } | |
3437 | ||
197865e8 | 3438 | static void |
800eeca4 | 3439 | dot_spill (dummy) |
2434f565 | 3440 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3441 | { |
3442 | expressionS e; | |
e0c9811a JW |
3443 | unsigned char sep; |
3444 | ||
3445 | sep = parse_operand (&e); | |
3446 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3447 | ignore_rest_of_line (); | |
197865e8 | 3448 | |
800eeca4 JW |
3449 | if (e.X_op != O_constant) |
3450 | as_bad ("Operand to .spill must be a constant"); | |
3451 | else | |
e0c9811a JW |
3452 | add_unwind_entry (output_spill_base (e.X_add_number)); |
3453 | } | |
3454 | ||
3455 | static void | |
3456 | dot_spillreg (dummy) | |
2434f565 | 3457 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3458 | { |
3459 | int sep, ab, xy, reg, treg; | |
3460 | expressionS e1, e2; | |
3461 | ||
3462 | sep = parse_operand (&e1); | |
3463 | if (sep != ',') | |
3464 | { | |
3465 | as_bad ("No second operand to .spillreg"); | |
3466 | return; | |
3467 | } | |
3468 | ||
3469 | parse_operand (&e2); | |
3470 | ||
3471 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
800eeca4 | 3472 | { |
e0c9811a JW |
3473 | as_bad ("First operand to .spillreg must be a preserved register"); |
3474 | return; | |
800eeca4 | 3475 | } |
e0c9811a JW |
3476 | |
3477 | if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) | |
3478 | { | |
3479 | as_bad ("Second operand to .spillreg must be a register"); | |
3480 | return; | |
3481 | } | |
3482 | ||
3483 | add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); | |
3484 | } | |
3485 | ||
3486 | static void | |
3487 | dot_spillmem (psprel) | |
3488 | int psprel; | |
3489 | { | |
3490 | expressionS e1, e2; | |
3491 | int sep, ab, reg; | |
3492 | ||
3493 | sep = parse_operand (&e1); | |
3494 | if (sep != ',') | |
3495 | { | |
3496 | as_bad ("Second operand missing"); | |
3497 | return; | |
3498 | } | |
3499 | ||
3500 | parse_operand (&e2); | |
3501 | ||
3502 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
3503 | { | |
3504 | as_bad ("First operand to .spill%s must be a preserved register", | |
3505 | psprel ? "psp" : "sp"); | |
3506 | return; | |
3507 | } | |
3508 | ||
3509 | if (e2.X_op != O_constant) | |
3510 | { | |
3511 | as_bad ("Second operand to .spill%s must be a constant", | |
3512 | psprel ? "psp" : "sp"); | |
3513 | return; | |
3514 | } | |
3515 | ||
3516 | if (psprel) | |
3517 | add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); | |
3518 | else | |
3519 | add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); | |
3520 | } | |
3521 | ||
3522 | static void | |
3523 | dot_spillreg_p (dummy) | |
2434f565 | 3524 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3525 | { |
3526 | int sep, ab, xy, reg, treg; | |
3527 | expressionS e1, e2, e3; | |
3528 | unsigned int qp; | |
3529 | ||
3530 | sep = parse_operand (&e1); | |
3531 | if (sep != ',') | |
3532 | { | |
3533 | as_bad ("No second and third operand to .spillreg.p"); | |
3534 | return; | |
3535 | } | |
3536 | ||
3537 | sep = parse_operand (&e2); | |
3538 | if (sep != ',') | |
3539 | { | |
3540 | as_bad ("No third operand to .spillreg.p"); | |
3541 | return; | |
3542 | } | |
3543 | ||
3544 | parse_operand (&e3); | |
3545 | ||
3546 | qp = e1.X_add_number - REG_P; | |
3547 | ||
3548 | if (e1.X_op != O_register || qp > 63) | |
3549 | { | |
3550 | as_bad ("First operand to .spillreg.p must be a predicate"); | |
3551 | return; | |
3552 | } | |
3553 | ||
3554 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3555 | { | |
3556 | as_bad ("Second operand to .spillreg.p must be a preserved register"); | |
3557 | return; | |
3558 | } | |
3559 | ||
3560 | if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) | |
3561 | { | |
3562 | as_bad ("Third operand to .spillreg.p must be a register"); | |
3563 | return; | |
3564 | } | |
3565 | ||
3566 | add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); | |
3567 | } | |
3568 | ||
3569 | static void | |
3570 | dot_spillmem_p (psprel) | |
3571 | int psprel; | |
3572 | { | |
3573 | expressionS e1, e2, e3; | |
3574 | int sep, ab, reg; | |
3575 | unsigned int qp; | |
3576 | ||
3577 | sep = parse_operand (&e1); | |
3578 | if (sep != ',') | |
3579 | { | |
3580 | as_bad ("Second operand missing"); | |
3581 | return; | |
3582 | } | |
3583 | ||
3584 | parse_operand (&e2); | |
3585 | if (sep != ',') | |
3586 | { | |
3587 | as_bad ("Second operand missing"); | |
3588 | return; | |
3589 | } | |
3590 | ||
3591 | parse_operand (&e3); | |
3592 | ||
3593 | qp = e1.X_add_number - REG_P; | |
3594 | if (e1.X_op != O_register || qp > 63) | |
3595 | { | |
3596 | as_bad ("First operand to .spill%s_p must be a predicate", | |
3597 | psprel ? "psp" : "sp"); | |
3598 | return; | |
3599 | } | |
3600 | ||
3601 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3602 | { | |
3603 | as_bad ("Second operand to .spill%s_p must be a preserved register", | |
3604 | psprel ? "psp" : "sp"); | |
3605 | return; | |
3606 | } | |
3607 | ||
3608 | if (e3.X_op != O_constant) | |
3609 | { | |
3610 | as_bad ("Third operand to .spill%s_p must be a constant", | |
3611 | psprel ? "psp" : "sp"); | |
3612 | return; | |
3613 | } | |
3614 | ||
3615 | if (psprel) | |
3616 | add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number)); | |
3617 | else | |
3618 | add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number)); | |
3619 | } | |
3620 | ||
3621 | static void | |
3622 | dot_label_state (dummy) | |
2434f565 | 3623 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3624 | { |
3625 | expressionS e; | |
3626 | ||
3627 | parse_operand (&e); | |
3628 | if (e.X_op != O_constant) | |
3629 | { | |
3630 | as_bad ("Operand to .label_state must be a constant"); | |
3631 | return; | |
3632 | } | |
3633 | add_unwind_entry (output_label_state (e.X_add_number)); | |
3634 | } | |
3635 | ||
3636 | static void | |
3637 | dot_copy_state (dummy) | |
2434f565 | 3638 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3639 | { |
3640 | expressionS e; | |
3641 | ||
3642 | parse_operand (&e); | |
3643 | if (e.X_op != O_constant) | |
3644 | { | |
3645 | as_bad ("Operand to .copy_state must be a constant"); | |
3646 | return; | |
3647 | } | |
3648 | add_unwind_entry (output_copy_state (e.X_add_number)); | |
800eeca4 JW |
3649 | } |
3650 | ||
197865e8 | 3651 | static void |
800eeca4 | 3652 | dot_unwabi (dummy) |
2434f565 | 3653 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3654 | { |
e0c9811a JW |
3655 | expressionS e1, e2; |
3656 | unsigned char sep; | |
3657 | ||
3658 | sep = parse_operand (&e1); | |
3659 | if (sep != ',') | |
3660 | { | |
3661 | as_bad ("Second operand to .unwabi missing"); | |
3662 | return; | |
3663 | } | |
3664 | sep = parse_operand (&e2); | |
3665 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3666 | ignore_rest_of_line (); | |
3667 | ||
3668 | if (e1.X_op != O_constant) | |
3669 | { | |
3670 | as_bad ("First operand to .unwabi must be a constant"); | |
3671 | return; | |
3672 | } | |
3673 | ||
3674 | if (e2.X_op != O_constant) | |
3675 | { | |
3676 | as_bad ("Second operand to .unwabi must be a constant"); | |
3677 | return; | |
3678 | } | |
3679 | ||
3680 | add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); | |
800eeca4 JW |
3681 | } |
3682 | ||
197865e8 | 3683 | static void |
800eeca4 | 3684 | dot_personality (dummy) |
2434f565 | 3685 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3686 | { |
3687 | char *name, *p, c; | |
3688 | SKIP_WHITESPACE (); | |
3689 | name = input_line_pointer; | |
3690 | c = get_symbol_end (); | |
3691 | p = input_line_pointer; | |
e0c9811a | 3692 | unwind.personality_routine = symbol_find_or_make (name); |
91a2ae2a | 3693 | unwind.force_unwind_entry = 1; |
800eeca4 JW |
3694 | *p = c; |
3695 | SKIP_WHITESPACE (); | |
3696 | demand_empty_rest_of_line (); | |
3697 | } | |
3698 | ||
3699 | static void | |
3700 | dot_proc (dummy) | |
2434f565 | 3701 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3702 | { |
3703 | char *name, *p, c; | |
3704 | symbolS *sym; | |
3705 | ||
e0c9811a JW |
3706 | unwind.proc_start = expr_build_dot (); |
3707 | /* Parse names of main and alternate entry points and mark them as | |
542d6675 | 3708 | function symbols: */ |
800eeca4 JW |
3709 | while (1) |
3710 | { | |
3711 | SKIP_WHITESPACE (); | |
3712 | name = input_line_pointer; | |
3713 | c = get_symbol_end (); | |
3714 | p = input_line_pointer; | |
3715 | sym = symbol_find_or_make (name); | |
e0c9811a | 3716 | if (unwind.proc_start == 0) |
542d6675 | 3717 | { |
e0c9811a | 3718 | unwind.proc_start = sym; |
800eeca4 JW |
3719 | } |
3720 | symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; | |
3721 | *p = c; | |
3722 | SKIP_WHITESPACE (); | |
3723 | if (*input_line_pointer != ',') | |
3724 | break; | |
3725 | ++input_line_pointer; | |
3726 | } | |
3727 | demand_empty_rest_of_line (); | |
3728 | ia64_do_align (16); | |
3729 | ||
33d01f33 | 3730 | unwind.prologue_count = 0; |
e0c9811a JW |
3731 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
3732 | unwind.personality_routine = 0; | |
800eeca4 JW |
3733 | } |
3734 | ||
3735 | static void | |
3736 | dot_body (dummy) | |
2434f565 | 3737 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3738 | { |
e0c9811a | 3739 | unwind.prologue = 0; |
30d25259 RH |
3740 | unwind.prologue_mask = 0; |
3741 | ||
800eeca4 | 3742 | add_unwind_entry (output_body ()); |
e0c9811a | 3743 | demand_empty_rest_of_line (); |
800eeca4 JW |
3744 | } |
3745 | ||
3746 | static void | |
3747 | dot_prologue (dummy) | |
2434f565 | 3748 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3749 | { |
e0c9811a | 3750 | unsigned char sep; |
2434f565 | 3751 | int mask = 0, grsave = 0; |
e0c9811a | 3752 | |
e0c9811a | 3753 | if (!is_it_end_of_statement ()) |
800eeca4 JW |
3754 | { |
3755 | expressionS e1, e2; | |
800eeca4 JW |
3756 | sep = parse_operand (&e1); |
3757 | if (sep != ',') | |
3758 | as_bad ("No second operand to .prologue"); | |
3759 | sep = parse_operand (&e2); | |
e0c9811a | 3760 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
542d6675 | 3761 | ignore_rest_of_line (); |
800eeca4 JW |
3762 | |
3763 | if (e1.X_op == O_constant) | |
542d6675 | 3764 | { |
30d25259 RH |
3765 | mask = e1.X_add_number; |
3766 | ||
800eeca4 | 3767 | if (e2.X_op == O_constant) |
30d25259 RH |
3768 | grsave = e2.X_add_number; |
3769 | else if (e2.X_op == O_register | |
3770 | && (grsave = e2.X_add_number - REG_GR) < 128) | |
3771 | ; | |
800eeca4 | 3772 | else |
30d25259 RH |
3773 | as_bad ("Second operand not a constant or general register"); |
3774 | ||
3775 | add_unwind_entry (output_prologue_gr (mask, grsave)); | |
800eeca4 JW |
3776 | } |
3777 | else | |
3778 | as_bad ("First operand not a constant"); | |
3779 | } | |
3780 | else | |
3781 | add_unwind_entry (output_prologue ()); | |
30d25259 RH |
3782 | |
3783 | unwind.prologue = 1; | |
3784 | unwind.prologue_mask = mask; | |
33d01f33 | 3785 | ++unwind.prologue_count; |
800eeca4 JW |
3786 | } |
3787 | ||
3788 | static void | |
3789 | dot_endp (dummy) | |
2434f565 | 3790 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3791 | { |
3792 | expressionS e; | |
3793 | unsigned char *ptr; | |
44f5c83a | 3794 | int bytes_per_address; |
800eeca4 JW |
3795 | long where; |
3796 | segT saved_seg; | |
3797 | subsegT saved_subseg; | |
91a2ae2a | 3798 | const char *sec_name, *text_name; |
800eeca4 | 3799 | |
91a2ae2a RH |
3800 | if (unwind.saved_text_seg) |
3801 | { | |
3802 | saved_seg = unwind.saved_text_seg; | |
3803 | saved_subseg = unwind.saved_text_subseg; | |
3804 | unwind.saved_text_seg = NULL; | |
3805 | } | |
3806 | else | |
3807 | { | |
3808 | saved_seg = now_seg; | |
3809 | saved_subseg = now_subseg; | |
3810 | } | |
3811 | ||
3812 | /* | |
3813 | Use a slightly ugly scheme to derive the unwind section names from | |
3814 | the text section name: | |
3815 | ||
3816 | text sect. unwind table sect. | |
3817 | name: name: comments: | |
3818 | ---------- ----------------- -------------------------------- | |
3819 | .text .IA_64.unwind | |
3820 | .text.foo .IA_64.unwind.text.foo | |
3821 | .foo .IA_64.unwind.foo | |
3822 | _info .IA_64.unwind_info gas issues error message (ditto) | |
3823 | _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) | |
3824 | ||
3825 | This mapping is done so that: | |
3826 | ||
3827 | (a) An object file with unwind info only in .text will use | |
3828 | unwind section names .IA_64.unwind and .IA_64.unwind_info. | |
3829 | This follows the letter of the ABI and also ensures backwards | |
3830 | compatibility with older toolchains. | |
3831 | ||
3832 | (b) An object file with unwind info in multiple text sections | |
3833 | will use separate unwind sections for each text section. | |
3834 | This allows us to properly set the "sh_info" and "sh_link" | |
3835 | fields in SHT_IA_64_UNWIND as required by the ABI and also | |
3836 | lets GNU ld support programs with multiple segments | |
3837 | containing unwind info (as might be the case for certain | |
3838 | embedded applications). | |
3839 | ||
3840 | (c) An error is issued if there would be a name clash. | |
3841 | */ | |
3842 | text_name = segment_name (saved_seg); | |
3843 | if (strncmp (text_name, "_info", 5) == 0) | |
3844 | { | |
3845 | as_bad ("Illegal section name `%s' (causes unwind section name clash)", | |
3846 | text_name); | |
3847 | ignore_rest_of_line (); | |
3848 | return; | |
3849 | } | |
3850 | if (strcmp (text_name, ".text") == 0) | |
3851 | text_name = ""; | |
800eeca4 JW |
3852 | |
3853 | expression (&e); | |
3854 | demand_empty_rest_of_line (); | |
3855 | ||
3856 | insn_group_break (1, 0, 0); | |
800eeca4 | 3857 | |
91a2ae2a RH |
3858 | /* If there wasn't a .handlerdata, we haven't generated an image yet. */ |
3859 | if (!unwind.info) | |
3860 | generate_unwind_image (text_name); | |
800eeca4 | 3861 | |
91a2ae2a RH |
3862 | if (unwind.info || unwind.force_unwind_entry) |
3863 | { | |
3864 | subseg_set (md.last_text_seg, 0); | |
3865 | unwind.proc_end = expr_build_dot (); | |
5e7474a7 | 3866 | |
91a2ae2a RH |
3867 | make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name); |
3868 | set_section ((char *) sec_name); | |
3869 | bfd_set_section_flags (stdoutput, now_seg, | |
3870 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); | |
5e7474a7 | 3871 | |
91a2ae2a RH |
3872 | /* Make sure the section has 8 byte alignment. */ |
3873 | record_alignment (now_seg, 3); | |
800eeca4 | 3874 | |
91a2ae2a RH |
3875 | ptr = frag_more (24); |
3876 | where = frag_now_fix () - 24; | |
3877 | bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; | |
800eeca4 | 3878 | |
91a2ae2a RH |
3879 | /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ |
3880 | e.X_op = O_pseudo_fixup; | |
3881 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3882 | e.X_add_number = 0; | |
3883 | e.X_add_symbol = unwind.proc_start; | |
3884 | ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); | |
800eeca4 | 3885 | |
800eeca4 JW |
3886 | e.X_op = O_pseudo_fixup; |
3887 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3888 | e.X_add_number = 0; | |
91a2ae2a RH |
3889 | e.X_add_symbol = unwind.proc_end; |
3890 | ia64_cons_fix_new (frag_now, where + bytes_per_address, | |
3891 | bytes_per_address, &e); | |
3892 | ||
3893 | if (unwind.info) | |
3894 | { | |
3895 | e.X_op = O_pseudo_fixup; | |
3896 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3897 | e.X_add_number = 0; | |
3898 | e.X_add_symbol = unwind.info; | |
3899 | ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), | |
3900 | bytes_per_address, &e); | |
3901 | } | |
3902 | else | |
3903 | md_number_to_chars (ptr + (bytes_per_address * 2), 0, | |
3904 | bytes_per_address); | |
800eeca4 | 3905 | |
91a2ae2a | 3906 | } |
800eeca4 | 3907 | subseg_set (saved_seg, saved_subseg); |
e0c9811a | 3908 | unwind.proc_start = unwind.proc_end = unwind.info = 0; |
800eeca4 JW |
3909 | } |
3910 | ||
3911 | static void | |
3912 | dot_template (template) | |
3913 | int template; | |
3914 | { | |
3915 | CURR_SLOT.user_template = template; | |
3916 | } | |
3917 | ||
3918 | static void | |
3919 | dot_regstk (dummy) | |
2434f565 | 3920 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3921 | { |
3922 | int ins, locs, outs, rots; | |
3923 | ||
3924 | if (is_it_end_of_statement ()) | |
3925 | ins = locs = outs = rots = 0; | |
3926 | else | |
3927 | { | |
3928 | ins = get_absolute_expression (); | |
3929 | if (*input_line_pointer++ != ',') | |
3930 | goto err; | |
3931 | locs = get_absolute_expression (); | |
3932 | if (*input_line_pointer++ != ',') | |
3933 | goto err; | |
3934 | outs = get_absolute_expression (); | |
3935 | if (*input_line_pointer++ != ',') | |
3936 | goto err; | |
3937 | rots = get_absolute_expression (); | |
3938 | } | |
3939 | set_regstack (ins, locs, outs, rots); | |
3940 | return; | |
3941 | ||
3942 | err: | |
3943 | as_bad ("Comma expected"); | |
3944 | ignore_rest_of_line (); | |
3945 | } | |
3946 | ||
3947 | static void | |
3948 | dot_rot (type) | |
3949 | int type; | |
3950 | { | |
3951 | unsigned num_regs, num_alloced = 0; | |
3952 | struct dynreg **drpp, *dr; | |
3953 | int ch, base_reg = 0; | |
3954 | char *name, *start; | |
3955 | size_t len; | |
3956 | ||
3957 | switch (type) | |
3958 | { | |
3959 | case DYNREG_GR: base_reg = REG_GR + 32; break; | |
3960 | case DYNREG_FR: base_reg = REG_FR + 32; break; | |
3961 | case DYNREG_PR: base_reg = REG_P + 16; break; | |
3962 | default: break; | |
3963 | } | |
3964 | ||
542d6675 | 3965 | /* First, remove existing names from hash table. */ |
800eeca4 JW |
3966 | for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) |
3967 | { | |
3968 | hash_delete (md.dynreg_hash, dr->name); | |
3969 | dr->num_regs = 0; | |
3970 | } | |
3971 | ||
3972 | drpp = &md.dynreg[type]; | |
3973 | while (1) | |
3974 | { | |
3975 | start = input_line_pointer; | |
3976 | ch = get_symbol_end (); | |
3977 | *input_line_pointer = ch; | |
3978 | len = (input_line_pointer - start); | |
3979 | ||
3980 | SKIP_WHITESPACE (); | |
3981 | if (*input_line_pointer != '[') | |
3982 | { | |
3983 | as_bad ("Expected '['"); | |
3984 | goto err; | |
3985 | } | |
3986 | ++input_line_pointer; /* skip '[' */ | |
3987 | ||
3988 | num_regs = get_absolute_expression (); | |
3989 | ||
3990 | if (*input_line_pointer++ != ']') | |
3991 | { | |
3992 | as_bad ("Expected ']'"); | |
3993 | goto err; | |
3994 | } | |
3995 | SKIP_WHITESPACE (); | |
3996 | ||
3997 | num_alloced += num_regs; | |
3998 | switch (type) | |
3999 | { | |
4000 | case DYNREG_GR: | |
4001 | if (num_alloced > md.rot.num_regs) | |
4002 | { | |
4003 | as_bad ("Used more than the declared %d rotating registers", | |
4004 | md.rot.num_regs); | |
4005 | goto err; | |
4006 | } | |
4007 | break; | |
4008 | case DYNREG_FR: | |
4009 | if (num_alloced > 96) | |
4010 | { | |
4011 | as_bad ("Used more than the available 96 rotating registers"); | |
4012 | goto err; | |
4013 | } | |
4014 | break; | |
4015 | case DYNREG_PR: | |
4016 | if (num_alloced > 48) | |
4017 | { | |
4018 | as_bad ("Used more than the available 48 rotating registers"); | |
4019 | goto err; | |
4020 | } | |
4021 | break; | |
4022 | ||
4023 | default: | |
4024 | break; | |
4025 | } | |
4026 | ||
4027 | name = obstack_alloc (¬es, len + 1); | |
4028 | memcpy (name, start, len); | |
4029 | name[len] = '\0'; | |
4030 | ||
4031 | if (!*drpp) | |
4032 | { | |
4033 | *drpp = obstack_alloc (¬es, sizeof (*dr)); | |
4034 | memset (*drpp, 0, sizeof (*dr)); | |
4035 | } | |
4036 | ||
4037 | dr = *drpp; | |
4038 | dr->name = name; | |
4039 | dr->num_regs = num_regs; | |
4040 | dr->base = base_reg; | |
4041 | drpp = &dr->next; | |
4042 | base_reg += num_regs; | |
4043 | ||
4044 | if (hash_insert (md.dynreg_hash, name, dr)) | |
4045 | { | |
4046 | as_bad ("Attempt to redefine register set `%s'", name); | |
4047 | goto err; | |
4048 | } | |
4049 | ||
4050 | if (*input_line_pointer != ',') | |
4051 | break; | |
4052 | ++input_line_pointer; /* skip comma */ | |
4053 | SKIP_WHITESPACE (); | |
4054 | } | |
4055 | demand_empty_rest_of_line (); | |
4056 | return; | |
4057 | ||
4058 | err: | |
4059 | ignore_rest_of_line (); | |
4060 | } | |
4061 | ||
4062 | static void | |
4063 | dot_byteorder (byteorder) | |
4064 | int byteorder; | |
4065 | { | |
4066 | target_big_endian = byteorder; | |
4067 | } | |
4068 | ||
4069 | static void | |
4070 | dot_psr (dummy) | |
2434f565 | 4071 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4072 | { |
4073 | char *option; | |
4074 | int ch; | |
4075 | ||
4076 | while (1) | |
4077 | { | |
4078 | option = input_line_pointer; | |
4079 | ch = get_symbol_end (); | |
4080 | if (strcmp (option, "lsb") == 0) | |
4081 | md.flags &= ~EF_IA_64_BE; | |
4082 | else if (strcmp (option, "msb") == 0) | |
4083 | md.flags |= EF_IA_64_BE; | |
4084 | else if (strcmp (option, "abi32") == 0) | |
4085 | md.flags &= ~EF_IA_64_ABI64; | |
4086 | else if (strcmp (option, "abi64") == 0) | |
4087 | md.flags |= EF_IA_64_ABI64; | |
4088 | else | |
4089 | as_bad ("Unknown psr option `%s'", option); | |
4090 | *input_line_pointer = ch; | |
4091 | ||
4092 | SKIP_WHITESPACE (); | |
4093 | if (*input_line_pointer != ',') | |
4094 | break; | |
4095 | ||
4096 | ++input_line_pointer; | |
4097 | SKIP_WHITESPACE (); | |
4098 | } | |
4099 | demand_empty_rest_of_line (); | |
4100 | } | |
4101 | ||
4102 | static void | |
4103 | dot_alias (dummy) | |
2434f565 | 4104 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4105 | { |
4106 | as_bad (".alias not implemented yet"); | |
4107 | } | |
4108 | ||
4109 | static void | |
4110 | dot_ln (dummy) | |
2434f565 | 4111 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4112 | { |
4113 | new_logical_line (0, get_absolute_expression ()); | |
4114 | demand_empty_rest_of_line (); | |
4115 | } | |
4116 | ||
542d6675 | 4117 | static char * |
800eeca4 JW |
4118 | parse_section_name () |
4119 | { | |
4120 | char *name; | |
4121 | int len; | |
4122 | ||
4123 | SKIP_WHITESPACE (); | |
4124 | if (*input_line_pointer != '"') | |
4125 | { | |
4126 | as_bad ("Missing section name"); | |
4127 | ignore_rest_of_line (); | |
4128 | return 0; | |
4129 | } | |
4130 | name = demand_copy_C_string (&len); | |
4131 | if (!name) | |
4132 | { | |
4133 | ignore_rest_of_line (); | |
4134 | return 0; | |
4135 | } | |
4136 | SKIP_WHITESPACE (); | |
4137 | if (*input_line_pointer != ',') | |
4138 | { | |
4139 | as_bad ("Comma expected after section name"); | |
4140 | ignore_rest_of_line (); | |
4141 | return 0; | |
4142 | } | |
4143 | ++input_line_pointer; /* skip comma */ | |
4144 | return name; | |
4145 | } | |
4146 | ||
4147 | static void | |
4148 | dot_xdata (size) | |
4149 | int size; | |
4150 | { | |
4151 | char *name = parse_section_name (); | |
4152 | if (!name) | |
4153 | return; | |
4154 | ||
4d5a53ff | 4155 | md.keep_pending_output = 1; |
800eeca4 JW |
4156 | set_section (name); |
4157 | cons (size); | |
4158 | obj_elf_previous (0); | |
4d5a53ff | 4159 | md.keep_pending_output = 0; |
800eeca4 JW |
4160 | } |
4161 | ||
4162 | /* Why doesn't float_cons() call md_cons_align() the way cons() does? */ | |
542d6675 | 4163 | |
800eeca4 JW |
4164 | static void |
4165 | stmt_float_cons (kind) | |
4166 | int kind; | |
4167 | { | |
4168 | size_t size; | |
4169 | ||
4170 | switch (kind) | |
4171 | { | |
4172 | case 'd': size = 8; break; | |
4173 | case 'x': size = 10; break; | |
4174 | ||
4175 | case 'f': | |
4176 | default: | |
4177 | size = 4; | |
4178 | break; | |
4179 | } | |
4180 | ia64_do_align (size); | |
4181 | float_cons (kind); | |
4182 | } | |
4183 | ||
4184 | static void | |
4185 | stmt_cons_ua (size) | |
4186 | int size; | |
4187 | { | |
4188 | int saved_auto_align = md.auto_align; | |
4189 | ||
4190 | md.auto_align = 0; | |
4191 | cons (size); | |
4192 | md.auto_align = saved_auto_align; | |
4193 | } | |
4194 | ||
4195 | static void | |
4196 | dot_xfloat_cons (kind) | |
4197 | int kind; | |
4198 | { | |
4199 | char *name = parse_section_name (); | |
4200 | if (!name) | |
4201 | return; | |
4202 | ||
4d5a53ff | 4203 | md.keep_pending_output = 1; |
800eeca4 JW |
4204 | set_section (name); |
4205 | stmt_float_cons (kind); | |
4206 | obj_elf_previous (0); | |
4d5a53ff | 4207 | md.keep_pending_output = 0; |
800eeca4 JW |
4208 | } |
4209 | ||
4210 | static void | |
4211 | dot_xstringer (zero) | |
4212 | int zero; | |
4213 | { | |
4214 | char *name = parse_section_name (); | |
4215 | if (!name) | |
4216 | return; | |
4217 | ||
4d5a53ff | 4218 | md.keep_pending_output = 1; |
800eeca4 JW |
4219 | set_section (name); |
4220 | stringer (zero); | |
4221 | obj_elf_previous (0); | |
4d5a53ff | 4222 | md.keep_pending_output = 0; |
800eeca4 JW |
4223 | } |
4224 | ||
4225 | static void | |
4226 | dot_xdata_ua (size) | |
4227 | int size; | |
4228 | { | |
4229 | int saved_auto_align = md.auto_align; | |
4230 | char *name = parse_section_name (); | |
4231 | if (!name) | |
4232 | return; | |
4233 | ||
4d5a53ff | 4234 | md.keep_pending_output = 1; |
800eeca4 JW |
4235 | set_section (name); |
4236 | md.auto_align = 0; | |
4237 | cons (size); | |
4238 | md.auto_align = saved_auto_align; | |
4239 | obj_elf_previous (0); | |
4d5a53ff | 4240 | md.keep_pending_output = 0; |
800eeca4 JW |
4241 | } |
4242 | ||
4243 | static void | |
4244 | dot_xfloat_cons_ua (kind) | |
4245 | int kind; | |
4246 | { | |
4247 | int saved_auto_align = md.auto_align; | |
4248 | char *name = parse_section_name (); | |
4249 | if (!name) | |
4250 | return; | |
4251 | ||
4d5a53ff | 4252 | md.keep_pending_output = 1; |
800eeca4 JW |
4253 | set_section (name); |
4254 | md.auto_align = 0; | |
4255 | stmt_float_cons (kind); | |
4256 | md.auto_align = saved_auto_align; | |
4257 | obj_elf_previous (0); | |
4d5a53ff | 4258 | md.keep_pending_output = 0; |
800eeca4 JW |
4259 | } |
4260 | ||
4261 | /* .reg.val <regname>,value */ | |
542d6675 | 4262 | |
800eeca4 JW |
4263 | static void |
4264 | dot_reg_val (dummy) | |
2434f565 | 4265 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4266 | { |
4267 | expressionS reg; | |
4268 | ||
4269 | expression (®); | |
4270 | if (reg.X_op != O_register) | |
4271 | { | |
4272 | as_bad (_("Register name expected")); | |
4273 | ignore_rest_of_line (); | |
4274 | } | |
4275 | else if (*input_line_pointer++ != ',') | |
4276 | { | |
4277 | as_bad (_("Comma expected")); | |
4278 | ignore_rest_of_line (); | |
4279 | } | |
197865e8 | 4280 | else |
800eeca4 JW |
4281 | { |
4282 | valueT value = get_absolute_expression (); | |
4283 | int regno = reg.X_add_number; | |
542d6675 KH |
4284 | if (regno < REG_GR || regno > REG_GR + 128) |
4285 | as_warn (_("Register value annotation ignored")); | |
800eeca4 | 4286 | else |
542d6675 KH |
4287 | { |
4288 | gr_values[regno - REG_GR].known = 1; | |
4289 | gr_values[regno - REG_GR].value = value; | |
4290 | gr_values[regno - REG_GR].path = md.path; | |
4291 | } | |
800eeca4 JW |
4292 | } |
4293 | demand_empty_rest_of_line (); | |
4294 | } | |
4295 | ||
197865e8 | 4296 | /* select dv checking mode |
800eeca4 JW |
4297 | .auto |
4298 | .explicit | |
4299 | .default | |
4300 | ||
197865e8 | 4301 | A stop is inserted when changing modes |
800eeca4 | 4302 | */ |
542d6675 | 4303 | |
800eeca4 JW |
4304 | static void |
4305 | dot_dv_mode (type) | |
542d6675 | 4306 | int type; |
800eeca4 JW |
4307 | { |
4308 | if (md.manual_bundling) | |
4309 | as_warn (_("Directive invalid within a bundle")); | |
4310 | ||
4311 | if (type == 'E' || type == 'A') | |
4312 | md.mode_explicitly_set = 0; | |
4313 | else | |
4314 | md.mode_explicitly_set = 1; | |
4315 | ||
4316 | md.detect_dv = 1; | |
4317 | switch (type) | |
4318 | { | |
4319 | case 'A': | |
4320 | case 'a': | |
4321 | if (md.explicit_mode) | |
542d6675 | 4322 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4323 | md.explicit_mode = 0; |
4324 | break; | |
4325 | case 'E': | |
4326 | case 'e': | |
4327 | if (!md.explicit_mode) | |
542d6675 | 4328 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4329 | md.explicit_mode = 1; |
4330 | break; | |
4331 | default: | |
4332 | case 'd': | |
4333 | if (md.explicit_mode != md.default_explicit_mode) | |
542d6675 | 4334 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4335 | md.explicit_mode = md.default_explicit_mode; |
4336 | md.mode_explicitly_set = 0; | |
4337 | break; | |
4338 | } | |
4339 | } | |
4340 | ||
4341 | static void | |
4342 | print_prmask (mask) | |
542d6675 | 4343 | valueT mask; |
800eeca4 JW |
4344 | { |
4345 | int regno; | |
4346 | char *comma = ""; | |
542d6675 | 4347 | for (regno = 0; regno < 64; regno++) |
800eeca4 | 4348 | { |
542d6675 KH |
4349 | if (mask & ((valueT) 1 << regno)) |
4350 | { | |
4351 | fprintf (stderr, "%s p%d", comma, regno); | |
4352 | comma = ","; | |
4353 | } | |
800eeca4 JW |
4354 | } |
4355 | } | |
4356 | ||
4357 | /* | |
4358 | .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") | |
4359 | .pred.rel.imply p1, p2 (also .pred.rel "imply") | |
4360 | .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") | |
4361 | .pred.safe_across_calls p1 [, p2 [,...]] | |
4362 | */ | |
542d6675 | 4363 | |
800eeca4 JW |
4364 | static void |
4365 | dot_pred_rel (type) | |
542d6675 | 4366 | int type; |
800eeca4 JW |
4367 | { |
4368 | valueT mask = 0; | |
4369 | int count = 0; | |
4370 | int p1 = -1, p2 = -1; | |
4371 | ||
4372 | if (type == 0) | |
4373 | { | |
4374 | if (*input_line_pointer != '"') | |
542d6675 KH |
4375 | { |
4376 | as_bad (_("Missing predicate relation type")); | |
4377 | ignore_rest_of_line (); | |
4378 | return; | |
4379 | } | |
197865e8 | 4380 | else |
542d6675 KH |
4381 | { |
4382 | int len; | |
4383 | char *form = demand_copy_C_string (&len); | |
4384 | if (strcmp (form, "mutex") == 0) | |
4385 | type = 'm'; | |
4386 | else if (strcmp (form, "clear") == 0) | |
4387 | type = 'c'; | |
4388 | else if (strcmp (form, "imply") == 0) | |
4389 | type = 'i'; | |
4390 | else | |
4391 | { | |
4392 | as_bad (_("Unrecognized predicate relation type")); | |
4393 | ignore_rest_of_line (); | |
4394 | return; | |
4395 | } | |
4396 | } | |
800eeca4 | 4397 | if (*input_line_pointer == ',') |
542d6675 | 4398 | ++input_line_pointer; |
800eeca4 JW |
4399 | SKIP_WHITESPACE (); |
4400 | } | |
4401 | ||
4402 | SKIP_WHITESPACE (); | |
4403 | while (1) | |
4404 | { | |
4405 | valueT bit = 1; | |
4406 | int regno; | |
197865e8 | 4407 | |
800eeca4 | 4408 | if (toupper (*input_line_pointer) != 'P' |
542d6675 KH |
4409 | || (regno = atoi (++input_line_pointer)) < 0 |
4410 | || regno > 63) | |
4411 | { | |
4412 | as_bad (_("Predicate register expected")); | |
4413 | ignore_rest_of_line (); | |
4414 | return; | |
4415 | } | |
800eeca4 | 4416 | while (isdigit (*input_line_pointer)) |
542d6675 | 4417 | ++input_line_pointer; |
800eeca4 | 4418 | if (p1 == -1) |
542d6675 | 4419 | p1 = regno; |
800eeca4 | 4420 | else if (p2 == -1) |
542d6675 | 4421 | p2 = regno; |
800eeca4 JW |
4422 | bit <<= regno; |
4423 | if (mask & bit) | |
542d6675 KH |
4424 | as_warn (_("Duplicate predicate register ignored")); |
4425 | mask |= bit; | |
4426 | count++; | |
4427 | /* See if it's a range. */ | |
800eeca4 | 4428 | if (*input_line_pointer == '-') |
542d6675 KH |
4429 | { |
4430 | valueT stop = 1; | |
4431 | ++input_line_pointer; | |
4432 | ||
4433 | if (toupper (*input_line_pointer) != 'P' | |
4434 | || (regno = atoi (++input_line_pointer)) < 0 | |
4435 | || regno > 63) | |
4436 | { | |
4437 | as_bad (_("Predicate register expected")); | |
4438 | ignore_rest_of_line (); | |
4439 | return; | |
4440 | } | |
4441 | while (isdigit (*input_line_pointer)) | |
4442 | ++input_line_pointer; | |
4443 | stop <<= regno; | |
4444 | if (bit >= stop) | |
4445 | { | |
4446 | as_bad (_("Bad register range")); | |
4447 | ignore_rest_of_line (); | |
4448 | return; | |
4449 | } | |
4450 | while (bit < stop) | |
4451 | { | |
4452 | bit <<= 1; | |
4453 | mask |= bit; | |
4454 | count++; | |
4455 | } | |
4456 | SKIP_WHITESPACE (); | |
4457 | } | |
800eeca4 | 4458 | if (*input_line_pointer != ',') |
542d6675 | 4459 | break; |
800eeca4 JW |
4460 | ++input_line_pointer; |
4461 | SKIP_WHITESPACE (); | |
4462 | } | |
4463 | ||
4464 | switch (type) | |
4465 | { | |
4466 | case 'c': | |
4467 | if (count == 0) | |
542d6675 | 4468 | mask = ~(valueT) 0; |
800eeca4 | 4469 | clear_qp_mutex (mask); |
197865e8 | 4470 | clear_qp_implies (mask, (valueT) 0); |
800eeca4 JW |
4471 | break; |
4472 | case 'i': | |
4473 | if (count != 2 || p1 == -1 || p2 == -1) | |
542d6675 | 4474 | as_bad (_("Predicate source and target required")); |
800eeca4 | 4475 | else if (p1 == 0 || p2 == 0) |
542d6675 | 4476 | as_bad (_("Use of p0 is not valid in this context")); |
800eeca4 | 4477 | else |
542d6675 | 4478 | add_qp_imply (p1, p2); |
800eeca4 JW |
4479 | break; |
4480 | case 'm': | |
4481 | if (count < 2) | |
542d6675 KH |
4482 | { |
4483 | as_bad (_("At least two PR arguments expected")); | |
4484 | break; | |
4485 | } | |
800eeca4 | 4486 | else if (mask & 1) |
542d6675 KH |
4487 | { |
4488 | as_bad (_("Use of p0 is not valid in this context")); | |
4489 | break; | |
4490 | } | |
800eeca4 JW |
4491 | add_qp_mutex (mask); |
4492 | break; | |
4493 | case 's': | |
4494 | /* note that we don't override any existing relations */ | |
4495 | if (count == 0) | |
542d6675 KH |
4496 | { |
4497 | as_bad (_("At least one PR argument expected")); | |
4498 | break; | |
4499 | } | |
800eeca4 | 4500 | if (md.debug_dv) |
542d6675 KH |
4501 | { |
4502 | fprintf (stderr, "Safe across calls: "); | |
4503 | print_prmask (mask); | |
4504 | fprintf (stderr, "\n"); | |
4505 | } | |
800eeca4 JW |
4506 | qp_safe_across_calls = mask; |
4507 | break; | |
4508 | } | |
4509 | demand_empty_rest_of_line (); | |
4510 | } | |
4511 | ||
4512 | /* .entry label [, label [, ...]] | |
4513 | Hint to DV code that the given labels are to be considered entry points. | |
542d6675 KH |
4514 | Otherwise, only global labels are considered entry points. */ |
4515 | ||
800eeca4 JW |
4516 | static void |
4517 | dot_entry (dummy) | |
2434f565 | 4518 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4519 | { |
4520 | const char *err; | |
4521 | char *name; | |
4522 | int c; | |
4523 | symbolS *symbolP; | |
4524 | ||
4525 | do | |
4526 | { | |
4527 | name = input_line_pointer; | |
4528 | c = get_symbol_end (); | |
4529 | symbolP = symbol_find_or_make (name); | |
4530 | ||
4531 | err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); | |
4532 | if (err) | |
542d6675 KH |
4533 | as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), |
4534 | name, err); | |
800eeca4 JW |
4535 | |
4536 | *input_line_pointer = c; | |
4537 | SKIP_WHITESPACE (); | |
4538 | c = *input_line_pointer; | |
4539 | if (c == ',') | |
4540 | { | |
4541 | input_line_pointer++; | |
4542 | SKIP_WHITESPACE (); | |
4543 | if (*input_line_pointer == '\n') | |
4544 | c = '\n'; | |
4545 | } | |
4546 | } | |
4547 | while (c == ','); | |
4548 | ||
4549 | demand_empty_rest_of_line (); | |
4550 | } | |
4551 | ||
197865e8 | 4552 | /* .mem.offset offset, base |
542d6675 KH |
4553 | "base" is used to distinguish between offsets from a different base. */ |
4554 | ||
800eeca4 JW |
4555 | static void |
4556 | dot_mem_offset (dummy) | |
2434f565 | 4557 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4558 | { |
4559 | md.mem_offset.hint = 1; | |
4560 | md.mem_offset.offset = get_absolute_expression (); | |
4561 | if (*input_line_pointer != ',') | |
4562 | { | |
4563 | as_bad (_("Comma expected")); | |
4564 | ignore_rest_of_line (); | |
4565 | return; | |
4566 | } | |
4567 | ++input_line_pointer; | |
4568 | md.mem_offset.base = get_absolute_expression (); | |
4569 | demand_empty_rest_of_line (); | |
4570 | } | |
4571 | ||
542d6675 | 4572 | /* ia64-specific pseudo-ops: */ |
800eeca4 JW |
4573 | const pseudo_typeS md_pseudo_table[] = |
4574 | { | |
4575 | { "radix", dot_radix, 0 }, | |
4576 | { "lcomm", s_lcomm_bytes, 1 }, | |
4577 | { "bss", dot_special_section, SPECIAL_SECTION_BSS }, | |
4578 | { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, | |
4579 | { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, | |
4580 | { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, | |
4581 | { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, | |
4582 | { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, | |
4583 | { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, | |
4584 | { "proc", dot_proc, 0 }, | |
4585 | { "body", dot_body, 0 }, | |
4586 | { "prologue", dot_prologue, 0 }, | |
2434f565 JW |
4587 | { "endp", dot_endp, 0 }, |
4588 | { "file", dwarf2_directive_file, 0 }, | |
4589 | { "loc", dwarf2_directive_loc, 0 }, | |
4590 | ||
4591 | { "fframe", dot_fframe, 0 }, | |
4592 | { "vframe", dot_vframe, 0 }, | |
4593 | { "vframesp", dot_vframesp, 0 }, | |
4594 | { "vframepsp", dot_vframepsp, 0 }, | |
4595 | { "save", dot_save, 0 }, | |
4596 | { "restore", dot_restore, 0 }, | |
4597 | { "restorereg", dot_restorereg, 0 }, | |
4598 | { "restorereg.p", dot_restorereg_p, 0 }, | |
4599 | { "handlerdata", dot_handlerdata, 0 }, | |
4600 | { "unwentry", dot_unwentry, 0 }, | |
4601 | { "altrp", dot_altrp, 0 }, | |
e0c9811a JW |
4602 | { "savesp", dot_savemem, 0 }, |
4603 | { "savepsp", dot_savemem, 1 }, | |
2434f565 JW |
4604 | { "save.g", dot_saveg, 0 }, |
4605 | { "save.f", dot_savef, 0 }, | |
4606 | { "save.b", dot_saveb, 0 }, | |
4607 | { "save.gf", dot_savegf, 0 }, | |
4608 | { "spill", dot_spill, 0 }, | |
4609 | { "spillreg", dot_spillreg, 0 }, | |
e0c9811a JW |
4610 | { "spillsp", dot_spillmem, 0 }, |
4611 | { "spillpsp", dot_spillmem, 1 }, | |
2434f565 | 4612 | { "spillreg.p", dot_spillreg_p, 0 }, |
e0c9811a JW |
4613 | { "spillsp.p", dot_spillmem_p, 0 }, |
4614 | { "spillpsp.p", dot_spillmem_p, 1 }, | |
2434f565 JW |
4615 | { "label_state", dot_label_state, 0 }, |
4616 | { "copy_state", dot_copy_state, 0 }, | |
4617 | { "unwabi", dot_unwabi, 0 }, | |
4618 | { "personality", dot_personality, 0 }, | |
800eeca4 | 4619 | #if 0 |
2434f565 | 4620 | { "estate", dot_estate, 0 }, |
800eeca4 JW |
4621 | #endif |
4622 | { "mii", dot_template, 0x0 }, | |
4623 | { "mli", dot_template, 0x2 }, /* old format, for compatibility */ | |
4624 | { "mlx", dot_template, 0x2 }, | |
4625 | { "mmi", dot_template, 0x4 }, | |
4626 | { "mfi", dot_template, 0x6 }, | |
4627 | { "mmf", dot_template, 0x7 }, | |
4628 | { "mib", dot_template, 0x8 }, | |
4629 | { "mbb", dot_template, 0x9 }, | |
4630 | { "bbb", dot_template, 0xb }, | |
4631 | { "mmb", dot_template, 0xc }, | |
4632 | { "mfb", dot_template, 0xe }, | |
4633 | #if 0 | |
4634 | { "lb", dot_scope, 0 }, | |
4635 | { "le", dot_scope, 1 }, | |
4636 | #endif | |
4637 | { "align", s_align_bytes, 0 }, | |
4638 | { "regstk", dot_regstk, 0 }, | |
4639 | { "rotr", dot_rot, DYNREG_GR }, | |
4640 | { "rotf", dot_rot, DYNREG_FR }, | |
4641 | { "rotp", dot_rot, DYNREG_PR }, | |
4642 | { "lsb", dot_byteorder, 0 }, | |
4643 | { "msb", dot_byteorder, 1 }, | |
4644 | { "psr", dot_psr, 0 }, | |
4645 | { "alias", dot_alias, 0 }, | |
4646 | { "ln", dot_ln, 0 }, /* source line info (for debugging) */ | |
4647 | ||
4648 | { "xdata1", dot_xdata, 1 }, | |
4649 | { "xdata2", dot_xdata, 2 }, | |
4650 | { "xdata4", dot_xdata, 4 }, | |
4651 | { "xdata8", dot_xdata, 8 }, | |
4652 | { "xreal4", dot_xfloat_cons, 'f' }, | |
4653 | { "xreal8", dot_xfloat_cons, 'd' }, | |
4654 | { "xreal10", dot_xfloat_cons, 'x' }, | |
4655 | { "xstring", dot_xstringer, 0 }, | |
4656 | { "xstringz", dot_xstringer, 1 }, | |
4657 | ||
542d6675 | 4658 | /* unaligned versions: */ |
800eeca4 JW |
4659 | { "xdata2.ua", dot_xdata_ua, 2 }, |
4660 | { "xdata4.ua", dot_xdata_ua, 4 }, | |
4661 | { "xdata8.ua", dot_xdata_ua, 8 }, | |
4662 | { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, | |
4663 | { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, | |
4664 | { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, | |
4665 | ||
4666 | /* annotations/DV checking support */ | |
4667 | { "entry", dot_entry, 0 }, | |
2434f565 | 4668 | { "mem.offset", dot_mem_offset, 0 }, |
800eeca4 JW |
4669 | { "pred.rel", dot_pred_rel, 0 }, |
4670 | { "pred.rel.clear", dot_pred_rel, 'c' }, | |
4671 | { "pred.rel.imply", dot_pred_rel, 'i' }, | |
4672 | { "pred.rel.mutex", dot_pred_rel, 'm' }, | |
4673 | { "pred.safe_across_calls", dot_pred_rel, 's' }, | |
2434f565 | 4674 | { "reg.val", dot_reg_val, 0 }, |
800eeca4 JW |
4675 | { "auto", dot_dv_mode, 'a' }, |
4676 | { "explicit", dot_dv_mode, 'e' }, | |
4677 | { "default", dot_dv_mode, 'd' }, | |
4678 | ||
4679 | { NULL, 0, 0 } | |
4680 | }; | |
4681 | ||
4682 | static const struct pseudo_opcode | |
4683 | { | |
4684 | const char *name; | |
4685 | void (*handler) (int); | |
4686 | int arg; | |
4687 | } | |
4688 | pseudo_opcode[] = | |
4689 | { | |
4690 | /* these are more like pseudo-ops, but don't start with a dot */ | |
4691 | { "data1", cons, 1 }, | |
4692 | { "data2", cons, 2 }, | |
4693 | { "data4", cons, 4 }, | |
4694 | { "data8", cons, 8 }, | |
4695 | { "real4", stmt_float_cons, 'f' }, | |
4696 | { "real8", stmt_float_cons, 'd' }, | |
4697 | { "real10", stmt_float_cons, 'x' }, | |
4698 | { "string", stringer, 0 }, | |
4699 | { "stringz", stringer, 1 }, | |
4700 | ||
542d6675 | 4701 | /* unaligned versions: */ |
800eeca4 JW |
4702 | { "data2.ua", stmt_cons_ua, 2 }, |
4703 | { "data4.ua", stmt_cons_ua, 4 }, | |
4704 | { "data8.ua", stmt_cons_ua, 8 }, | |
4705 | { "real4.ua", float_cons, 'f' }, | |
4706 | { "real8.ua", float_cons, 'd' }, | |
4707 | { "real10.ua", float_cons, 'x' }, | |
4708 | }; | |
4709 | ||
4710 | /* Declare a register by creating a symbol for it and entering it in | |
4711 | the symbol table. */ | |
542d6675 KH |
4712 | |
4713 | static symbolS * | |
800eeca4 JW |
4714 | declare_register (name, regnum) |
4715 | const char *name; | |
4716 | int regnum; | |
4717 | { | |
4718 | const char *err; | |
4719 | symbolS *sym; | |
4720 | ||
4721 | sym = symbol_new (name, reg_section, regnum, &zero_address_frag); | |
4722 | ||
4723 | err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); | |
4724 | if (err) | |
4725 | as_fatal ("Inserting \"%s\" into register table failed: %s", | |
4726 | name, err); | |
4727 | ||
4728 | return sym; | |
4729 | } | |
4730 | ||
4731 | static void | |
4732 | declare_register_set (prefix, num_regs, base_regnum) | |
4733 | const char *prefix; | |
4734 | int num_regs; | |
4735 | int base_regnum; | |
4736 | { | |
4737 | char name[8]; | |
4738 | int i; | |
4739 | ||
4740 | for (i = 0; i < num_regs; ++i) | |
4741 | { | |
4742 | sprintf (name, "%s%u", prefix, i); | |
4743 | declare_register (name, base_regnum + i); | |
4744 | } | |
4745 | } | |
4746 | ||
4747 | static unsigned int | |
4748 | operand_width (opnd) | |
4749 | enum ia64_opnd opnd; | |
4750 | { | |
4751 | const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; | |
4752 | unsigned int bits = 0; | |
4753 | int i; | |
4754 | ||
4755 | bits = 0; | |
4756 | for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) | |
4757 | bits += odesc->field[i].bits; | |
4758 | ||
4759 | return bits; | |
4760 | } | |
4761 | ||
87f8eb97 | 4762 | static enum operand_match_result |
800eeca4 JW |
4763 | operand_match (idesc, index, e) |
4764 | const struct ia64_opcode *idesc; | |
4765 | int index; | |
4766 | expressionS *e; | |
4767 | { | |
4768 | enum ia64_opnd opnd = idesc->operands[index]; | |
4769 | int bits, relocatable = 0; | |
4770 | struct insn_fix *fix; | |
4771 | bfd_signed_vma val; | |
4772 | ||
4773 | switch (opnd) | |
4774 | { | |
542d6675 | 4775 | /* constants: */ |
800eeca4 JW |
4776 | |
4777 | case IA64_OPND_AR_CCV: | |
4778 | if (e->X_op == O_register && e->X_add_number == REG_AR + 32) | |
87f8eb97 | 4779 | return OPERAND_MATCH; |
800eeca4 JW |
4780 | break; |
4781 | ||
4782 | case IA64_OPND_AR_PFS: | |
4783 | if (e->X_op == O_register && e->X_add_number == REG_AR + 64) | |
87f8eb97 | 4784 | return OPERAND_MATCH; |
800eeca4 JW |
4785 | break; |
4786 | ||
4787 | case IA64_OPND_GR0: | |
4788 | if (e->X_op == O_register && e->X_add_number == REG_GR + 0) | |
87f8eb97 | 4789 | return OPERAND_MATCH; |
800eeca4 JW |
4790 | break; |
4791 | ||
4792 | case IA64_OPND_IP: | |
4793 | if (e->X_op == O_register && e->X_add_number == REG_IP) | |
87f8eb97 | 4794 | return OPERAND_MATCH; |
800eeca4 JW |
4795 | break; |
4796 | ||
4797 | case IA64_OPND_PR: | |
4798 | if (e->X_op == O_register && e->X_add_number == REG_PR) | |
87f8eb97 | 4799 | return OPERAND_MATCH; |
800eeca4 JW |
4800 | break; |
4801 | ||
4802 | case IA64_OPND_PR_ROT: | |
4803 | if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) | |
87f8eb97 | 4804 | return OPERAND_MATCH; |
800eeca4 JW |
4805 | break; |
4806 | ||
4807 | case IA64_OPND_PSR: | |
4808 | if (e->X_op == O_register && e->X_add_number == REG_PSR) | |
87f8eb97 | 4809 | return OPERAND_MATCH; |
800eeca4 JW |
4810 | break; |
4811 | ||
4812 | case IA64_OPND_PSR_L: | |
4813 | if (e->X_op == O_register && e->X_add_number == REG_PSR_L) | |
87f8eb97 | 4814 | return OPERAND_MATCH; |
800eeca4 JW |
4815 | break; |
4816 | ||
4817 | case IA64_OPND_PSR_UM: | |
4818 | if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) | |
87f8eb97 | 4819 | return OPERAND_MATCH; |
800eeca4 JW |
4820 | break; |
4821 | ||
4822 | case IA64_OPND_C1: | |
87f8eb97 JW |
4823 | if (e->X_op == O_constant) |
4824 | { | |
4825 | if (e->X_add_number == 1) | |
4826 | return OPERAND_MATCH; | |
4827 | else | |
4828 | return OPERAND_OUT_OF_RANGE; | |
4829 | } | |
800eeca4 JW |
4830 | break; |
4831 | ||
4832 | case IA64_OPND_C8: | |
87f8eb97 JW |
4833 | if (e->X_op == O_constant) |
4834 | { | |
4835 | if (e->X_add_number == 8) | |
4836 | return OPERAND_MATCH; | |
4837 | else | |
4838 | return OPERAND_OUT_OF_RANGE; | |
4839 | } | |
800eeca4 JW |
4840 | break; |
4841 | ||
4842 | case IA64_OPND_C16: | |
87f8eb97 JW |
4843 | if (e->X_op == O_constant) |
4844 | { | |
4845 | if (e->X_add_number == 16) | |
4846 | return OPERAND_MATCH; | |
4847 | else | |
4848 | return OPERAND_OUT_OF_RANGE; | |
4849 | } | |
800eeca4 JW |
4850 | break; |
4851 | ||
542d6675 | 4852 | /* register operands: */ |
800eeca4 JW |
4853 | |
4854 | case IA64_OPND_AR3: | |
4855 | if (e->X_op == O_register && e->X_add_number >= REG_AR | |
4856 | && e->X_add_number < REG_AR + 128) | |
87f8eb97 | 4857 | return OPERAND_MATCH; |
800eeca4 JW |
4858 | break; |
4859 | ||
4860 | case IA64_OPND_B1: | |
4861 | case IA64_OPND_B2: | |
4862 | if (e->X_op == O_register && e->X_add_number >= REG_BR | |
4863 | && e->X_add_number < REG_BR + 8) | |
87f8eb97 | 4864 | return OPERAND_MATCH; |
800eeca4 JW |
4865 | break; |
4866 | ||
4867 | case IA64_OPND_CR3: | |
4868 | if (e->X_op == O_register && e->X_add_number >= REG_CR | |
4869 | && e->X_add_number < REG_CR + 128) | |
87f8eb97 | 4870 | return OPERAND_MATCH; |
800eeca4 JW |
4871 | break; |
4872 | ||
4873 | case IA64_OPND_F1: | |
4874 | case IA64_OPND_F2: | |
4875 | case IA64_OPND_F3: | |
4876 | case IA64_OPND_F4: | |
4877 | if (e->X_op == O_register && e->X_add_number >= REG_FR | |
4878 | && e->X_add_number < REG_FR + 128) | |
87f8eb97 | 4879 | return OPERAND_MATCH; |
800eeca4 JW |
4880 | break; |
4881 | ||
4882 | case IA64_OPND_P1: | |
4883 | case IA64_OPND_P2: | |
4884 | if (e->X_op == O_register && e->X_add_number >= REG_P | |
4885 | && e->X_add_number < REG_P + 64) | |
87f8eb97 | 4886 | return OPERAND_MATCH; |
800eeca4 JW |
4887 | break; |
4888 | ||
4889 | case IA64_OPND_R1: | |
4890 | case IA64_OPND_R2: | |
4891 | case IA64_OPND_R3: | |
4892 | if (e->X_op == O_register && e->X_add_number >= REG_GR | |
4893 | && e->X_add_number < REG_GR + 128) | |
87f8eb97 | 4894 | return OPERAND_MATCH; |
800eeca4 JW |
4895 | break; |
4896 | ||
4897 | case IA64_OPND_R3_2: | |
87f8eb97 JW |
4898 | if (e->X_op == O_register && e->X_add_number >= REG_GR) |
4899 | { | |
4900 | if (e->X_add_number < REG_GR + 4) | |
4901 | return OPERAND_MATCH; | |
4902 | else if (e->X_add_number < REG_GR + 128) | |
4903 | return OPERAND_OUT_OF_RANGE; | |
4904 | } | |
800eeca4 JW |
4905 | break; |
4906 | ||
542d6675 | 4907 | /* indirect operands: */ |
800eeca4 JW |
4908 | case IA64_OPND_CPUID_R3: |
4909 | case IA64_OPND_DBR_R3: | |
4910 | case IA64_OPND_DTR_R3: | |
4911 | case IA64_OPND_ITR_R3: | |
4912 | case IA64_OPND_IBR_R3: | |
4913 | case IA64_OPND_MSR_R3: | |
4914 | case IA64_OPND_PKR_R3: | |
4915 | case IA64_OPND_PMC_R3: | |
4916 | case IA64_OPND_PMD_R3: | |
4917 | case IA64_OPND_RR_R3: | |
4918 | if (e->X_op == O_index && e->X_op_symbol | |
4919 | && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID | |
4920 | == opnd - IA64_OPND_CPUID_R3)) | |
87f8eb97 | 4921 | return OPERAND_MATCH; |
800eeca4 JW |
4922 | break; |
4923 | ||
4924 | case IA64_OPND_MR3: | |
4925 | if (e->X_op == O_index && !e->X_op_symbol) | |
87f8eb97 | 4926 | return OPERAND_MATCH; |
800eeca4 JW |
4927 | break; |
4928 | ||
542d6675 | 4929 | /* immediate operands: */ |
800eeca4 JW |
4930 | case IA64_OPND_CNT2a: |
4931 | case IA64_OPND_LEN4: | |
4932 | case IA64_OPND_LEN6: | |
4933 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 JW |
4934 | if (e->X_op == O_constant) |
4935 | { | |
4936 | if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) | |
4937 | return OPERAND_MATCH; | |
4938 | else | |
4939 | return OPERAND_OUT_OF_RANGE; | |
4940 | } | |
800eeca4 JW |
4941 | break; |
4942 | ||
4943 | case IA64_OPND_CNT2b: | |
87f8eb97 JW |
4944 | if (e->X_op == O_constant) |
4945 | { | |
4946 | if ((bfd_vma) (e->X_add_number - 1) < 3) | |
4947 | return OPERAND_MATCH; | |
4948 | else | |
4949 | return OPERAND_OUT_OF_RANGE; | |
4950 | } | |
800eeca4 JW |
4951 | break; |
4952 | ||
4953 | case IA64_OPND_CNT2c: | |
4954 | val = e->X_add_number; | |
87f8eb97 JW |
4955 | if (e->X_op == O_constant) |
4956 | { | |
4957 | if ((val == 0 || val == 7 || val == 15 || val == 16)) | |
4958 | return OPERAND_MATCH; | |
4959 | else | |
4960 | return OPERAND_OUT_OF_RANGE; | |
4961 | } | |
800eeca4 JW |
4962 | break; |
4963 | ||
4964 | case IA64_OPND_SOR: | |
4965 | /* SOR must be an integer multiple of 8 */ | |
87f8eb97 JW |
4966 | if (e->X_op == O_constant && e->X_add_number & 0x7) |
4967 | return OPERAND_OUT_OF_RANGE; | |
800eeca4 JW |
4968 | case IA64_OPND_SOF: |
4969 | case IA64_OPND_SOL: | |
87f8eb97 JW |
4970 | if (e->X_op == O_constant) |
4971 | { | |
4972 | if ((bfd_vma) e->X_add_number <= 96) | |
4973 | return OPERAND_MATCH; | |
4974 | else | |
4975 | return OPERAND_OUT_OF_RANGE; | |
4976 | } | |
800eeca4 JW |
4977 | break; |
4978 | ||
4979 | case IA64_OPND_IMMU62: | |
4980 | if (e->X_op == O_constant) | |
542d6675 | 4981 | { |
800eeca4 | 4982 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) |
87f8eb97 JW |
4983 | return OPERAND_MATCH; |
4984 | else | |
4985 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 4986 | } |
197865e8 | 4987 | else |
542d6675 KH |
4988 | { |
4989 | /* FIXME -- need 62-bit relocation type */ | |
4990 | as_bad (_("62-bit relocation not yet implemented")); | |
4991 | } | |
800eeca4 JW |
4992 | break; |
4993 | ||
4994 | case IA64_OPND_IMMU64: | |
4995 | if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup | |
4996 | || e->X_op == O_subtract) | |
4997 | { | |
4998 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
4999 | fix->code = BFD_RELOC_IA64_IMM64; | |
5000 | if (e->X_op != O_subtract) | |
5001 | { | |
5002 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
5003 | if (e->X_op == O_pseudo_fixup) | |
5004 | e->X_op = O_symbol; | |
5005 | } | |
5006 | ||
5007 | fix->opnd = idesc->operands[index]; | |
5008 | fix->expr = *e; | |
5009 | fix->is_pcrel = 0; | |
5010 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5011 | return OPERAND_MATCH; |
800eeca4 JW |
5012 | } |
5013 | else if (e->X_op == O_constant) | |
87f8eb97 | 5014 | return OPERAND_MATCH; |
800eeca4 JW |
5015 | break; |
5016 | ||
5017 | case IA64_OPND_CCNT5: | |
5018 | case IA64_OPND_CNT5: | |
5019 | case IA64_OPND_CNT6: | |
5020 | case IA64_OPND_CPOS6a: | |
5021 | case IA64_OPND_CPOS6b: | |
5022 | case IA64_OPND_CPOS6c: | |
5023 | case IA64_OPND_IMMU2: | |
5024 | case IA64_OPND_IMMU7a: | |
5025 | case IA64_OPND_IMMU7b: | |
800eeca4 JW |
5026 | case IA64_OPND_IMMU21: |
5027 | case IA64_OPND_IMMU24: | |
5028 | case IA64_OPND_MBTYPE4: | |
5029 | case IA64_OPND_MHTYPE8: | |
5030 | case IA64_OPND_POS6: | |
5031 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 JW |
5032 | if (e->X_op == O_constant) |
5033 | { | |
5034 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) | |
5035 | return OPERAND_MATCH; | |
5036 | else | |
5037 | return OPERAND_OUT_OF_RANGE; | |
5038 | } | |
800eeca4 JW |
5039 | break; |
5040 | ||
bf3ca999 TW |
5041 | case IA64_OPND_IMMU9: |
5042 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 | 5043 | if (e->X_op == O_constant) |
542d6675 | 5044 | { |
87f8eb97 JW |
5045 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) |
5046 | { | |
5047 | int lobits = e->X_add_number & 0x3; | |
5048 | if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) | |
5049 | e->X_add_number |= (bfd_vma) 0x3; | |
5050 | return OPERAND_MATCH; | |
5051 | } | |
5052 | else | |
5053 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5054 | } |
bf3ca999 TW |
5055 | break; |
5056 | ||
800eeca4 JW |
5057 | case IA64_OPND_IMM44: |
5058 | /* least 16 bits must be zero */ | |
5059 | if ((e->X_add_number & 0xffff) != 0) | |
87f8eb97 JW |
5060 | /* XXX technically, this is wrong: we should not be issuing warning |
5061 | messages until we're sure this instruction pattern is going to | |
5062 | be used! */ | |
542d6675 | 5063 | as_warn (_("lower 16 bits of mask ignored")); |
800eeca4 | 5064 | |
87f8eb97 | 5065 | if (e->X_op == O_constant) |
542d6675 | 5066 | { |
87f8eb97 JW |
5067 | if (((e->X_add_number >= 0 |
5068 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) | |
5069 | || (e->X_add_number < 0 | |
5070 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) | |
542d6675 | 5071 | { |
87f8eb97 JW |
5072 | /* sign-extend */ |
5073 | if (e->X_add_number >= 0 | |
5074 | && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) | |
5075 | { | |
5076 | e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); | |
5077 | } | |
5078 | return OPERAND_MATCH; | |
542d6675 | 5079 | } |
87f8eb97 JW |
5080 | else |
5081 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5082 | } |
800eeca4 JW |
5083 | break; |
5084 | ||
5085 | case IA64_OPND_IMM17: | |
5086 | /* bit 0 is a don't care (pr0 is hardwired to 1) */ | |
87f8eb97 | 5087 | if (e->X_op == O_constant) |
542d6675 | 5088 | { |
87f8eb97 JW |
5089 | if (((e->X_add_number >= 0 |
5090 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) | |
5091 | || (e->X_add_number < 0 | |
5092 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) | |
542d6675 | 5093 | { |
87f8eb97 JW |
5094 | /* sign-extend */ |
5095 | if (e->X_add_number >= 0 | |
5096 | && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) | |
5097 | { | |
5098 | e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); | |
5099 | } | |
5100 | return OPERAND_MATCH; | |
542d6675 | 5101 | } |
87f8eb97 JW |
5102 | else |
5103 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5104 | } |
800eeca4 JW |
5105 | break; |
5106 | ||
5107 | case IA64_OPND_IMM14: | |
5108 | case IA64_OPND_IMM22: | |
5109 | relocatable = 1; | |
5110 | case IA64_OPND_IMM1: | |
5111 | case IA64_OPND_IMM8: | |
5112 | case IA64_OPND_IMM8U4: | |
5113 | case IA64_OPND_IMM8M1: | |
5114 | case IA64_OPND_IMM8M1U4: | |
5115 | case IA64_OPND_IMM8M1U8: | |
5116 | case IA64_OPND_IMM9a: | |
5117 | case IA64_OPND_IMM9b: | |
5118 | bits = operand_width (idesc->operands[index]); | |
5119 | if (relocatable && (e->X_op == O_symbol | |
5120 | || e->X_op == O_subtract | |
5121 | || e->X_op == O_pseudo_fixup)) | |
5122 | { | |
5123 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5124 | ||
5125 | if (idesc->operands[index] == IA64_OPND_IMM14) | |
5126 | fix->code = BFD_RELOC_IA64_IMM14; | |
5127 | else | |
5128 | fix->code = BFD_RELOC_IA64_IMM22; | |
5129 | ||
5130 | if (e->X_op != O_subtract) | |
5131 | { | |
5132 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
5133 | if (e->X_op == O_pseudo_fixup) | |
5134 | e->X_op = O_symbol; | |
5135 | } | |
5136 | ||
5137 | fix->opnd = idesc->operands[index]; | |
5138 | fix->expr = *e; | |
5139 | fix->is_pcrel = 0; | |
5140 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5141 | return OPERAND_MATCH; |
800eeca4 JW |
5142 | } |
5143 | else if (e->X_op != O_constant | |
5144 | && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) | |
87f8eb97 | 5145 | return OPERAND_MISMATCH; |
800eeca4 JW |
5146 | |
5147 | if (opnd == IA64_OPND_IMM8M1U4) | |
5148 | { | |
5149 | /* Zero is not valid for unsigned compares that take an adjusted | |
5150 | constant immediate range. */ | |
5151 | if (e->X_add_number == 0) | |
87f8eb97 | 5152 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5153 | |
5154 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
5155 | checks will work. */ | |
5156 | val = e->X_add_number; | |
197865e8 KH |
5157 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
5158 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
5159 | val = ((val << 32) >> 32); |
5160 | ||
5161 | /* Check for 0x100000000. This is valid because | |
5162 | 0x100000000-1 is the same as ((uint32_t) -1). */ | |
5163 | if (val == ((bfd_signed_vma) 1 << 32)) | |
87f8eb97 | 5164 | return OPERAND_MATCH; |
800eeca4 JW |
5165 | |
5166 | val = val - 1; | |
5167 | } | |
5168 | else if (opnd == IA64_OPND_IMM8M1U8) | |
5169 | { | |
5170 | /* Zero is not valid for unsigned compares that take an adjusted | |
5171 | constant immediate range. */ | |
5172 | if (e->X_add_number == 0) | |
87f8eb97 | 5173 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5174 | |
5175 | /* Check for 0x10000000000000000. */ | |
5176 | if (e->X_op == O_big) | |
5177 | { | |
5178 | if (generic_bignum[0] == 0 | |
5179 | && generic_bignum[1] == 0 | |
5180 | && generic_bignum[2] == 0 | |
5181 | && generic_bignum[3] == 0 | |
5182 | && generic_bignum[4] == 1) | |
87f8eb97 | 5183 | return OPERAND_MATCH; |
800eeca4 | 5184 | else |
87f8eb97 | 5185 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5186 | } |
5187 | else | |
5188 | val = e->X_add_number - 1; | |
5189 | } | |
5190 | else if (opnd == IA64_OPND_IMM8M1) | |
5191 | val = e->X_add_number - 1; | |
5192 | else if (opnd == IA64_OPND_IMM8U4) | |
5193 | { | |
5194 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
5195 | checks will work. */ | |
5196 | val = e->X_add_number; | |
197865e8 KH |
5197 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
5198 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
5199 | val = ((val << 32) >> 32); |
5200 | } | |
5201 | else | |
5202 | val = e->X_add_number; | |
5203 | ||
2434f565 JW |
5204 | if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) |
5205 | || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) | |
87f8eb97 JW |
5206 | return OPERAND_MATCH; |
5207 | else | |
5208 | return OPERAND_OUT_OF_RANGE; | |
800eeca4 JW |
5209 | |
5210 | case IA64_OPND_INC3: | |
5211 | /* +/- 1, 4, 8, 16 */ | |
5212 | val = e->X_add_number; | |
5213 | if (val < 0) | |
5214 | val = -val; | |
87f8eb97 JW |
5215 | if (e->X_op == O_constant) |
5216 | { | |
5217 | if ((val == 1 || val == 4 || val == 8 || val == 16)) | |
5218 | return OPERAND_MATCH; | |
5219 | else | |
5220 | return OPERAND_OUT_OF_RANGE; | |
5221 | } | |
800eeca4 JW |
5222 | break; |
5223 | ||
5224 | case IA64_OPND_TGT25: | |
5225 | case IA64_OPND_TGT25b: | |
5226 | case IA64_OPND_TGT25c: | |
5227 | case IA64_OPND_TGT64: | |
5228 | if (e->X_op == O_symbol) | |
5229 | { | |
5230 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5231 | if (opnd == IA64_OPND_TGT25) | |
5232 | fix->code = BFD_RELOC_IA64_PCREL21F; | |
5233 | else if (opnd == IA64_OPND_TGT25b) | |
5234 | fix->code = BFD_RELOC_IA64_PCREL21M; | |
5235 | else if (opnd == IA64_OPND_TGT25c) | |
5236 | fix->code = BFD_RELOC_IA64_PCREL21B; | |
542d6675 | 5237 | else if (opnd == IA64_OPND_TGT64) |
c67e42c9 RH |
5238 | fix->code = BFD_RELOC_IA64_PCREL60B; |
5239 | else | |
5240 | abort (); | |
5241 | ||
800eeca4 JW |
5242 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
5243 | fix->opnd = idesc->operands[index]; | |
5244 | fix->expr = *e; | |
5245 | fix->is_pcrel = 1; | |
5246 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5247 | return OPERAND_MATCH; |
800eeca4 JW |
5248 | } |
5249 | case IA64_OPND_TAG13: | |
5250 | case IA64_OPND_TAG13b: | |
5251 | switch (e->X_op) | |
5252 | { | |
5253 | case O_constant: | |
87f8eb97 | 5254 | return OPERAND_MATCH; |
800eeca4 JW |
5255 | |
5256 | case O_symbol: | |
5257 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
fa1cb89c JW |
5258 | /* There are no external relocs for TAG13/TAG13b fields, so we |
5259 | create a dummy reloc. This will not live past md_apply_fix3. */ | |
5260 | fix->code = BFD_RELOC_UNUSED; | |
5261 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
800eeca4 JW |
5262 | fix->opnd = idesc->operands[index]; |
5263 | fix->expr = *e; | |
5264 | fix->is_pcrel = 1; | |
5265 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5266 | return OPERAND_MATCH; |
800eeca4 JW |
5267 | |
5268 | default: | |
5269 | break; | |
5270 | } | |
5271 | break; | |
5272 | ||
5273 | default: | |
5274 | break; | |
5275 | } | |
87f8eb97 | 5276 | return OPERAND_MISMATCH; |
800eeca4 JW |
5277 | } |
5278 | ||
5279 | static int | |
5280 | parse_operand (e) | |
5281 | expressionS *e; | |
5282 | { | |
5283 | int sep = '\0'; | |
5284 | ||
5285 | memset (e, 0, sizeof (*e)); | |
5286 | e->X_op = O_absent; | |
5287 | SKIP_WHITESPACE (); | |
5288 | if (*input_line_pointer != '}') | |
5289 | expression (e); | |
5290 | sep = *input_line_pointer++; | |
5291 | ||
5292 | if (sep == '}') | |
5293 | { | |
5294 | if (!md.manual_bundling) | |
5295 | as_warn ("Found '}' when manual bundling is off"); | |
5296 | else | |
5297 | CURR_SLOT.manual_bundling_off = 1; | |
5298 | md.manual_bundling = 0; | |
5299 | sep = '\0'; | |
5300 | } | |
5301 | return sep; | |
5302 | } | |
5303 | ||
5304 | /* Returns the next entry in the opcode table that matches the one in | |
5305 | IDESC, and frees the entry in IDESC. If no matching entry is | |
197865e8 | 5306 | found, NULL is returned instead. */ |
800eeca4 JW |
5307 | |
5308 | static struct ia64_opcode * | |
5309 | get_next_opcode (struct ia64_opcode *idesc) | |
5310 | { | |
5311 | struct ia64_opcode *next = ia64_find_next_opcode (idesc); | |
5312 | ia64_free_opcode (idesc); | |
5313 | return next; | |
5314 | } | |
5315 | ||
5316 | /* Parse the operands for the opcode and find the opcode variant that | |
5317 | matches the specified operands, or NULL if no match is possible. */ | |
542d6675 KH |
5318 | |
5319 | static struct ia64_opcode * | |
800eeca4 JW |
5320 | parse_operands (idesc) |
5321 | struct ia64_opcode *idesc; | |
5322 | { | |
5323 | int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; | |
87f8eb97 | 5324 | int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; |
800eeca4 | 5325 | enum ia64_opnd expected_operand = IA64_OPND_NIL; |
87f8eb97 | 5326 | enum operand_match_result result; |
800eeca4 JW |
5327 | char mnemonic[129]; |
5328 | char *first_arg = 0, *end, *saved_input_pointer; | |
5329 | unsigned int sof; | |
5330 | ||
5331 | assert (strlen (idesc->name) <= 128); | |
5332 | ||
5333 | strcpy (mnemonic, idesc->name); | |
5334 | if (idesc->operands[2] == IA64_OPND_SOF) | |
5335 | { | |
5336 | /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we | |
5337 | can't parse the first operand until we have parsed the | |
5338 | remaining operands of the "alloc" instruction. */ | |
5339 | SKIP_WHITESPACE (); | |
5340 | first_arg = input_line_pointer; | |
5341 | end = strchr (input_line_pointer, '='); | |
5342 | if (!end) | |
5343 | { | |
5344 | as_bad ("Expected separator `='"); | |
5345 | return 0; | |
5346 | } | |
5347 | input_line_pointer = end + 1; | |
5348 | ++i; | |
5349 | ++num_outputs; | |
5350 | } | |
5351 | ||
5352 | for (; i < NELEMS (CURR_SLOT.opnd); ++i) | |
5353 | { | |
5354 | sep = parse_operand (CURR_SLOT.opnd + i); | |
5355 | if (CURR_SLOT.opnd[i].X_op == O_absent) | |
5356 | break; | |
5357 | ||
5358 | ++num_operands; | |
5359 | ||
5360 | if (sep != '=' && sep != ',') | |
5361 | break; | |
5362 | ||
5363 | if (sep == '=') | |
5364 | { | |
5365 | if (num_outputs > 0) | |
5366 | as_bad ("Duplicate equal sign (=) in instruction"); | |
5367 | else | |
5368 | num_outputs = i + 1; | |
5369 | } | |
5370 | } | |
5371 | if (sep != '\0') | |
5372 | { | |
5373 | as_bad ("Illegal operand separator `%c'", sep); | |
5374 | return 0; | |
5375 | } | |
197865e8 | 5376 | |
800eeca4 JW |
5377 | if (idesc->operands[2] == IA64_OPND_SOF) |
5378 | { | |
5379 | /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ | |
5380 | know (strcmp (idesc->name, "alloc") == 0); | |
5381 | if (num_operands == 5 /* first_arg not included in this count! */ | |
5382 | && CURR_SLOT.opnd[2].X_op == O_constant | |
5383 | && CURR_SLOT.opnd[3].X_op == O_constant | |
5384 | && CURR_SLOT.opnd[4].X_op == O_constant | |
5385 | && CURR_SLOT.opnd[5].X_op == O_constant) | |
5386 | { | |
5387 | sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, | |
5388 | CURR_SLOT.opnd[3].X_add_number, | |
5389 | CURR_SLOT.opnd[4].X_add_number, | |
5390 | CURR_SLOT.opnd[5].X_add_number); | |
5391 | ||
542d6675 | 5392 | /* now we can parse the first arg: */ |
800eeca4 JW |
5393 | saved_input_pointer = input_line_pointer; |
5394 | input_line_pointer = first_arg; | |
5395 | sep = parse_operand (CURR_SLOT.opnd + 0); | |
5396 | if (sep != '=') | |
5397 | --num_outputs; /* force error */ | |
5398 | input_line_pointer = saved_input_pointer; | |
5399 | ||
5400 | CURR_SLOT.opnd[2].X_add_number = sof; | |
5401 | CURR_SLOT.opnd[3].X_add_number | |
5402 | = sof - CURR_SLOT.opnd[4].X_add_number; | |
5403 | CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; | |
5404 | } | |
5405 | } | |
5406 | ||
5407 | highest_unmatched_operand = 0; | |
87f8eb97 JW |
5408 | curr_out_of_range_pos = -1; |
5409 | error_pos = 0; | |
800eeca4 JW |
5410 | expected_operand = idesc->operands[0]; |
5411 | for (; idesc; idesc = get_next_opcode (idesc)) | |
5412 | { | |
5413 | if (num_outputs != idesc->num_outputs) | |
5414 | continue; /* mismatch in # of outputs */ | |
5415 | ||
5416 | CURR_SLOT.num_fixups = 0; | |
87f8eb97 JW |
5417 | |
5418 | /* Try to match all operands. If we see an out-of-range operand, | |
5419 | then continue trying to match the rest of the operands, since if | |
5420 | the rest match, then this idesc will give the best error message. */ | |
5421 | ||
5422 | out_of_range_pos = -1; | |
800eeca4 | 5423 | for (i = 0; i < num_operands && idesc->operands[i]; ++i) |
87f8eb97 JW |
5424 | { |
5425 | result = operand_match (idesc, i, CURR_SLOT.opnd + i); | |
5426 | if (result != OPERAND_MATCH) | |
5427 | { | |
5428 | if (result != OPERAND_OUT_OF_RANGE) | |
5429 | break; | |
5430 | if (out_of_range_pos < 0) | |
5431 | /* remember position of the first out-of-range operand: */ | |
5432 | out_of_range_pos = i; | |
5433 | } | |
5434 | } | |
800eeca4 | 5435 | |
87f8eb97 JW |
5436 | /* If we did not match all operands, or if at least one operand was |
5437 | out-of-range, then this idesc does not match. Keep track of which | |
5438 | idesc matched the most operands before failing. If we have two | |
5439 | idescs that failed at the same position, and one had an out-of-range | |
5440 | operand, then prefer the out-of-range operand. Thus if we have | |
5441 | "add r0=0x1000000,r1" we get an error saying the constant is out | |
5442 | of range instead of an error saying that the constant should have been | |
5443 | a register. */ | |
5444 | ||
5445 | if (i != num_operands || out_of_range_pos >= 0) | |
800eeca4 | 5446 | { |
87f8eb97 JW |
5447 | if (i > highest_unmatched_operand |
5448 | || (i == highest_unmatched_operand | |
5449 | && out_of_range_pos > curr_out_of_range_pos)) | |
800eeca4 JW |
5450 | { |
5451 | highest_unmatched_operand = i; | |
87f8eb97 JW |
5452 | if (out_of_range_pos >= 0) |
5453 | { | |
5454 | expected_operand = idesc->operands[out_of_range_pos]; | |
5455 | error_pos = out_of_range_pos; | |
5456 | } | |
5457 | else | |
5458 | { | |
5459 | expected_operand = idesc->operands[i]; | |
5460 | error_pos = i; | |
5461 | } | |
5462 | curr_out_of_range_pos = out_of_range_pos; | |
800eeca4 JW |
5463 | } |
5464 | continue; | |
5465 | } | |
5466 | ||
5467 | if (num_operands < NELEMS (idesc->operands) | |
5468 | && idesc->operands[num_operands]) | |
5469 | continue; /* mismatch in number of arguments */ | |
5470 | ||
5471 | break; | |
5472 | } | |
5473 | if (!idesc) | |
5474 | { | |
5475 | if (expected_operand) | |
5476 | as_bad ("Operand %u of `%s' should be %s", | |
87f8eb97 | 5477 | error_pos + 1, mnemonic, |
800eeca4 JW |
5478 | elf64_ia64_operands[expected_operand].desc); |
5479 | else | |
5480 | as_bad ("Operand mismatch"); | |
5481 | return 0; | |
5482 | } | |
5483 | return idesc; | |
5484 | } | |
5485 | ||
88be23ec BS |
5486 | /* Keep track of state necessary to determine whether a NOP is necessary |
5487 | to avoid an erratum in A and B step Itanium chips, and return 1 if we | |
5488 | detect a case where additional NOPs may be necessary. */ | |
5489 | static int | |
5490 | errata_nop_necessary_p (slot, insn_unit) | |
5491 | struct slot *slot; | |
5492 | enum ia64_unit insn_unit; | |
5493 | { | |
5494 | int i; | |
5495 | struct group *this_group = md.last_groups + md.group_idx; | |
5496 | struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; | |
5497 | struct ia64_opcode *idesc = slot->idesc; | |
5498 | ||
5499 | /* Test whether this could be the first insn in a problematic sequence. */ | |
5500 | if (insn_unit == IA64_UNIT_F) | |
5501 | { | |
5502 | for (i = 0; i < idesc->num_outputs; i++) | |
5503 | if (idesc->operands[i] == IA64_OPND_P1 | |
5504 | || idesc->operands[i] == IA64_OPND_P2) | |
5505 | { | |
5506 | int regno = slot->opnd[i].X_add_number - REG_P; | |
3557da92 | 5507 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5508 | if (regno >= 64) |
3557da92 | 5509 | return 0; |
88be23ec BS |
5510 | this_group->p_reg_set[regno] = 1; |
5511 | } | |
5512 | } | |
5513 | ||
5514 | /* Test whether this could be the second insn in a problematic sequence. */ | |
5515 | if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 | |
5516 | && prev_group->p_reg_set[slot->qp_regno]) | |
5517 | { | |
5518 | for (i = 0; i < idesc->num_outputs; i++) | |
5519 | if (idesc->operands[i] == IA64_OPND_R1 | |
5520 | || idesc->operands[i] == IA64_OPND_R2 | |
5521 | || idesc->operands[i] == IA64_OPND_R3) | |
5522 | { | |
5523 | int regno = slot->opnd[i].X_add_number - REG_GR; | |
3557da92 | 5524 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5525 | if (regno >= 128) |
3557da92 | 5526 | return 0; |
88be23ec BS |
5527 | if (strncmp (idesc->name, "add", 3) != 0 |
5528 | && strncmp (idesc->name, "sub", 3) != 0 | |
5529 | && strncmp (idesc->name, "shladd", 6) != 0 | |
5530 | && (idesc->flags & IA64_OPCODE_POSTINC) == 0) | |
5531 | this_group->g_reg_set_conditionally[regno] = 1; | |
5532 | } | |
5533 | } | |
5534 | ||
5535 | /* Test whether this could be the third insn in a problematic sequence. */ | |
5536 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) | |
5537 | { | |
5538 | if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ | |
5539 | idesc->operands[i] == IA64_OPND_R3 | |
5540 | /* For mov indirect. */ | |
5541 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
5542 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
5543 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
5544 | || idesc->operands[i] == IA64_OPND_PKR_R3 | |
5545 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
5546 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
5547 | || idesc->operands[i] == IA64_OPND_MSR_R3 | |
5548 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
5549 | /* For itr. */ | |
5550 | || idesc->operands[i] == IA64_OPND_ITR_R3 | |
5551 | || idesc->operands[i] == IA64_OPND_DTR_R3 | |
5552 | /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ | |
5553 | || idesc->operands[i] == IA64_OPND_MR3) | |
5554 | { | |
5555 | int regno = slot->opnd[i].X_add_number - REG_GR; | |
3557da92 | 5556 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5557 | if (regno >= 128) |
3557da92 | 5558 | return 0; |
88be23ec BS |
5559 | if (idesc->operands[i] == IA64_OPND_R3) |
5560 | { | |
5561 | if (strcmp (idesc->name, "fc") != 0 | |
5562 | && strcmp (idesc->name, "tak") != 0 | |
5563 | && strcmp (idesc->name, "thash") != 0 | |
5564 | && strcmp (idesc->name, "tpa") != 0 | |
5565 | && strcmp (idesc->name, "ttag") != 0 | |
5566 | && strncmp (idesc->name, "ptr", 3) != 0 | |
5567 | && strncmp (idesc->name, "ptc", 3) != 0 | |
5568 | && strncmp (idesc->name, "probe", 5) != 0) | |
5569 | return 0; | |
5570 | } | |
bc805888 | 5571 | if (prev_group->g_reg_set_conditionally[regno]) |
88be23ec BS |
5572 | return 1; |
5573 | } | |
5574 | } | |
5575 | return 0; | |
5576 | } | |
5577 | ||
800eeca4 JW |
5578 | static void |
5579 | build_insn (slot, insnp) | |
5580 | struct slot *slot; | |
5581 | bfd_vma *insnp; | |
5582 | { | |
5583 | const struct ia64_operand *odesc, *o2desc; | |
5584 | struct ia64_opcode *idesc = slot->idesc; | |
5585 | bfd_signed_vma insn, val; | |
5586 | const char *err; | |
5587 | int i; | |
5588 | ||
5589 | insn = idesc->opcode | slot->qp_regno; | |
5590 | ||
5591 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) | |
5592 | { | |
c67e42c9 RH |
5593 | if (slot->opnd[i].X_op == O_register |
5594 | || slot->opnd[i].X_op == O_constant | |
5595 | || slot->opnd[i].X_op == O_index) | |
5596 | val = slot->opnd[i].X_add_number; | |
5597 | else if (slot->opnd[i].X_op == O_big) | |
800eeca4 | 5598 | { |
c67e42c9 RH |
5599 | /* This must be the value 0x10000000000000000. */ |
5600 | assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); | |
5601 | val = 0; | |
5602 | } | |
5603 | else | |
5604 | val = 0; | |
5605 | ||
5606 | switch (idesc->operands[i]) | |
5607 | { | |
5608 | case IA64_OPND_IMMU64: | |
800eeca4 JW |
5609 | *insnp++ = (val >> 22) & 0x1ffffffffffLL; |
5610 | insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) | |
5611 | | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) | |
5612 | | (((val >> 63) & 0x1) << 36)); | |
c67e42c9 RH |
5613 | continue; |
5614 | ||
5615 | case IA64_OPND_IMMU62: | |
542d6675 KH |
5616 | val &= 0x3fffffffffffffffULL; |
5617 | if (val != slot->opnd[i].X_add_number) | |
5618 | as_warn (_("Value truncated to 62 bits")); | |
5619 | *insnp++ = (val >> 21) & 0x1ffffffffffLL; | |
5620 | insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); | |
c67e42c9 | 5621 | continue; |
800eeca4 | 5622 | |
c67e42c9 RH |
5623 | case IA64_OPND_TGT64: |
5624 | val >>= 4; | |
5625 | *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; | |
5626 | insn |= ((((val >> 59) & 0x1) << 36) | |
5627 | | (((val >> 0) & 0xfffff) << 13)); | |
5628 | continue; | |
800eeca4 | 5629 | |
c67e42c9 RH |
5630 | case IA64_OPND_AR3: |
5631 | val -= REG_AR; | |
5632 | break; | |
5633 | ||
5634 | case IA64_OPND_B1: | |
5635 | case IA64_OPND_B2: | |
5636 | val -= REG_BR; | |
5637 | break; | |
5638 | ||
5639 | case IA64_OPND_CR3: | |
5640 | val -= REG_CR; | |
5641 | break; | |
5642 | ||
5643 | case IA64_OPND_F1: | |
5644 | case IA64_OPND_F2: | |
5645 | case IA64_OPND_F3: | |
5646 | case IA64_OPND_F4: | |
5647 | val -= REG_FR; | |
5648 | break; | |
5649 | ||
5650 | case IA64_OPND_P1: | |
5651 | case IA64_OPND_P2: | |
5652 | val -= REG_P; | |
5653 | break; | |
5654 | ||
5655 | case IA64_OPND_R1: | |
5656 | case IA64_OPND_R2: | |
5657 | case IA64_OPND_R3: | |
5658 | case IA64_OPND_R3_2: | |
5659 | case IA64_OPND_CPUID_R3: | |
5660 | case IA64_OPND_DBR_R3: | |
5661 | case IA64_OPND_DTR_R3: | |
5662 | case IA64_OPND_ITR_R3: | |
5663 | case IA64_OPND_IBR_R3: | |
5664 | case IA64_OPND_MR3: | |
5665 | case IA64_OPND_MSR_R3: | |
5666 | case IA64_OPND_PKR_R3: | |
5667 | case IA64_OPND_PMC_R3: | |
5668 | case IA64_OPND_PMD_R3: | |
197865e8 | 5669 | case IA64_OPND_RR_R3: |
c67e42c9 RH |
5670 | val -= REG_GR; |
5671 | break; | |
5672 | ||
5673 | default: | |
5674 | break; | |
5675 | } | |
5676 | ||
5677 | odesc = elf64_ia64_operands + idesc->operands[i]; | |
5678 | err = (*odesc->insert) (odesc, val, &insn); | |
5679 | if (err) | |
5680 | as_bad_where (slot->src_file, slot->src_line, | |
5681 | "Bad operand value: %s", err); | |
5682 | if (idesc->flags & IA64_OPCODE_PSEUDO) | |
5683 | { | |
5684 | if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) | |
5685 | && odesc == elf64_ia64_operands + IA64_OPND_F3) | |
5686 | { | |
5687 | o2desc = elf64_ia64_operands + IA64_OPND_F2; | |
5688 | (*o2desc->insert) (o2desc, val, &insn); | |
800eeca4 | 5689 | } |
c67e42c9 RH |
5690 | if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) |
5691 | && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a | |
5692 | || odesc == elf64_ia64_operands + IA64_OPND_POS6)) | |
800eeca4 | 5693 | { |
c67e42c9 RH |
5694 | o2desc = elf64_ia64_operands + IA64_OPND_LEN6; |
5695 | (*o2desc->insert) (o2desc, 64 - val, &insn); | |
800eeca4 JW |
5696 | } |
5697 | } | |
5698 | } | |
5699 | *insnp = insn; | |
5700 | } | |
5701 | ||
5702 | static void | |
5703 | emit_one_bundle () | |
5704 | { | |
5705 | unsigned int manual_bundling_on = 0, manual_bundling_off = 0; | |
5706 | unsigned int manual_bundling = 0; | |
5707 | enum ia64_unit required_unit, insn_unit = 0; | |
5708 | enum ia64_insn_type type[3], insn_type; | |
5709 | unsigned int template, orig_template; | |
542d6675 | 5710 | bfd_vma insn[3] = { -1, -1, -1 }; |
800eeca4 JW |
5711 | struct ia64_opcode *idesc; |
5712 | int end_of_insn_group = 0, user_template = -1; | |
5713 | int n, i, j, first, curr; | |
2434f565 | 5714 | unw_rec_list *ptr; |
800eeca4 JW |
5715 | bfd_vma t0 = 0, t1 = 0; |
5716 | struct label_fix *lfix; | |
5717 | struct insn_fix *ifix; | |
5718 | char mnemonic[16]; | |
5719 | fixS *fix; | |
5720 | char *f; | |
5721 | ||
5722 | first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; | |
5723 | know (first >= 0 & first < NUM_SLOTS); | |
5724 | n = MIN (3, md.num_slots_in_use); | |
5725 | ||
5726 | /* Determine template: user user_template if specified, best match | |
542d6675 | 5727 | otherwise: */ |
800eeca4 JW |
5728 | |
5729 | if (md.slot[first].user_template >= 0) | |
5730 | user_template = template = md.slot[first].user_template; | |
5731 | else | |
5732 | { | |
032efc85 | 5733 | /* Auto select appropriate template. */ |
800eeca4 JW |
5734 | memset (type, 0, sizeof (type)); |
5735 | curr = first; | |
5736 | for (i = 0; i < n; ++i) | |
5737 | { | |
032efc85 RH |
5738 | if (md.slot[curr].label_fixups && i != 0) |
5739 | break; | |
800eeca4 JW |
5740 | type[i] = md.slot[curr].idesc->type; |
5741 | curr = (curr + 1) % NUM_SLOTS; | |
5742 | } | |
5743 | template = best_template[type[0]][type[1]][type[2]]; | |
5744 | } | |
5745 | ||
542d6675 | 5746 | /* initialize instructions with appropriate nops: */ |
800eeca4 JW |
5747 | for (i = 0; i < 3; ++i) |
5748 | insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; | |
5749 | ||
5750 | f = frag_more (16); | |
5751 | ||
542d6675 | 5752 | /* now fill in slots with as many insns as possible: */ |
800eeca4 JW |
5753 | curr = first; |
5754 | idesc = md.slot[curr].idesc; | |
5755 | end_of_insn_group = 0; | |
5756 | for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) | |
5757 | { | |
e0c9811a JW |
5758 | /* Set the slot number for prologue/body records now as those |
5759 | refer to the current point, not the point after the | |
542d6675 | 5760 | instruction has been issued: */ |
10850f29 JW |
5761 | /* Don't try to delete prologue/body records here, as that will cause |
5762 | them to also be deleted from the master list of unwind records. */ | |
e0c9811a | 5763 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
10850f29 JW |
5764 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
5765 | || ptr->r.type == body) | |
f5a30c2e JW |
5766 | { |
5767 | ptr->slot_number = (unsigned long) f + i; | |
5768 | ptr->slot_frag = frag_now; | |
5769 | } | |
e0c9811a | 5770 | |
800eeca4 JW |
5771 | if (idesc->flags & IA64_OPCODE_SLOT2) |
5772 | { | |
5773 | if (manual_bundling && i != 2) | |
5774 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5775 | "`%s' must be last in bundle", idesc->name); | |
5776 | else | |
5777 | i = 2; | |
5778 | } | |
5779 | if (idesc->flags & IA64_OPCODE_LAST) | |
5780 | { | |
2434f565 JW |
5781 | int required_slot; |
5782 | unsigned int required_template; | |
800eeca4 JW |
5783 | |
5784 | /* If we need a stop bit after an M slot, our only choice is | |
5785 | template 5 (M;;MI). If we need a stop bit after a B | |
5786 | slot, our only choice is to place it at the end of the | |
5787 | bundle, because the only available templates are MIB, | |
5788 | MBB, BBB, MMB, and MFB. We don't handle anything other | |
5789 | than M and B slots because these are the only kind of | |
5790 | instructions that can have the IA64_OPCODE_LAST bit set. */ | |
5791 | required_template = template; | |
5792 | switch (idesc->type) | |
5793 | { | |
5794 | case IA64_TYPE_M: | |
5795 | required_slot = 0; | |
5796 | required_template = 5; | |
5797 | break; | |
5798 | ||
5799 | case IA64_TYPE_B: | |
5800 | required_slot = 2; | |
5801 | break; | |
5802 | ||
5803 | default: | |
5804 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5805 | "Internal error: don't know how to force %s to end" | |
5806 | "of instruction group", idesc->name); | |
5807 | required_slot = i; | |
5808 | break; | |
5809 | } | |
5810 | if (manual_bundling && i != required_slot) | |
5811 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5812 | "`%s' must be last in instruction group", | |
5813 | idesc->name); | |
5814 | if (required_slot < i) | |
5815 | /* Can't fit this instruction. */ | |
5816 | break; | |
5817 | ||
5818 | i = required_slot; | |
5819 | if (required_template != template) | |
5820 | { | |
5821 | /* If we switch the template, we need to reset the NOPs | |
5822 | after slot i. The slot-types of the instructions ahead | |
5823 | of i never change, so we don't need to worry about | |
5824 | changing NOPs in front of this slot. */ | |
5825 | for (j = i; j < 3; ++j) | |
5826 | insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; | |
5827 | } | |
5828 | template = required_template; | |
5829 | } | |
5830 | if (curr != first && md.slot[curr].label_fixups) | |
5831 | { | |
5832 | if (manual_bundling_on) | |
5833 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5834 | "Label must be first in a bundle"); | |
5835 | /* This insn must go into the first slot of a bundle. */ | |
5836 | break; | |
5837 | } | |
5838 | ||
5839 | manual_bundling_on = md.slot[curr].manual_bundling_on; | |
5840 | manual_bundling_off = md.slot[curr].manual_bundling_off; | |
5841 | ||
5842 | if (manual_bundling_on) | |
5843 | { | |
5844 | if (curr == first) | |
5845 | manual_bundling = 1; | |
5846 | else | |
5847 | break; /* need to start a new bundle */ | |
5848 | } | |
5849 | ||
5850 | if (end_of_insn_group && md.num_slots_in_use >= 1) | |
5851 | { | |
5852 | /* We need an instruction group boundary in the middle of a | |
5853 | bundle. See if we can switch to an other template with | |
5854 | an appropriate boundary. */ | |
5855 | ||
5856 | orig_template = template; | |
5857 | if (i == 1 && (user_template == 4 | |
5858 | || (user_template < 0 | |
5859 | && (ia64_templ_desc[template].exec_unit[0] | |
5860 | == IA64_UNIT_M)))) | |
5861 | { | |
5862 | template = 5; | |
5863 | end_of_insn_group = 0; | |
5864 | } | |
5865 | else if (i == 2 && (user_template == 0 | |
5866 | || (user_template < 0 | |
5867 | && (ia64_templ_desc[template].exec_unit[1] | |
5868 | == IA64_UNIT_I))) | |
5869 | /* This test makes sure we don't switch the template if | |
5870 | the next instruction is one that needs to be first in | |
5871 | an instruction group. Since all those instructions are | |
5872 | in the M group, there is no way such an instruction can | |
5873 | fit in this bundle even if we switch the template. The | |
5874 | reason we have to check for this is that otherwise we | |
5875 | may end up generating "MI;;I M.." which has the deadly | |
5876 | effect that the second M instruction is no longer the | |
5877 | first in the bundle! --davidm 99/12/16 */ | |
5878 | && (idesc->flags & IA64_OPCODE_FIRST) == 0) | |
5879 | { | |
5880 | template = 1; | |
5881 | end_of_insn_group = 0; | |
5882 | } | |
5883 | else if (curr != first) | |
5884 | /* can't fit this insn */ | |
5885 | break; | |
5886 | ||
5887 | if (template != orig_template) | |
5888 | /* if we switch the template, we need to reset the NOPs | |
5889 | after slot i. The slot-types of the instructions ahead | |
5890 | of i never change, so we don't need to worry about | |
5891 | changing NOPs in front of this slot. */ | |
5892 | for (j = i; j < 3; ++j) | |
5893 | insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; | |
5894 | } | |
5895 | required_unit = ia64_templ_desc[template].exec_unit[i]; | |
5896 | ||
542d6675 | 5897 | /* resolve dynamic opcodes such as "break" and "nop": */ |
800eeca4 JW |
5898 | if (idesc->type == IA64_TYPE_DYN) |
5899 | { | |
5900 | if ((strcmp (idesc->name, "nop") == 0) | |
5901 | || (strcmp (idesc->name, "break") == 0)) | |
5902 | insn_unit = required_unit; | |
5903 | else if (strcmp (idesc->name, "chk.s") == 0) | |
5904 | { | |
5905 | insn_unit = IA64_UNIT_M; | |
5906 | if (required_unit == IA64_UNIT_I) | |
5907 | insn_unit = IA64_UNIT_I; | |
5908 | } | |
5909 | else | |
5910 | as_fatal ("emit_one_bundle: unexpected dynamic op"); | |
5911 | ||
5912 | sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); | |
3d56ab85 | 5913 | ia64_free_opcode (idesc); |
800eeca4 JW |
5914 | md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); |
5915 | #if 0 | |
5916 | know (!idesc->next); /* no resolved dynamic ops have collisions */ | |
5917 | #endif | |
5918 | } | |
5919 | else | |
5920 | { | |
5921 | insn_type = idesc->type; | |
5922 | insn_unit = IA64_UNIT_NIL; | |
5923 | switch (insn_type) | |
5924 | { | |
5925 | case IA64_TYPE_A: | |
5926 | if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) | |
5927 | insn_unit = required_unit; | |
5928 | break; | |
542d6675 | 5929 | case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; |
800eeca4 JW |
5930 | case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; |
5931 | case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; | |
5932 | case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; | |
5933 | case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; | |
5934 | default: break; | |
5935 | } | |
5936 | } | |
5937 | ||
5938 | if (insn_unit != required_unit) | |
5939 | { | |
5940 | if (required_unit == IA64_UNIT_L | |
542d6675 | 5941 | && insn_unit == IA64_UNIT_I |
800eeca4 JW |
5942 | && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) |
5943 | { | |
5944 | /* we got ourselves an MLX template but the current | |
197865e8 | 5945 | instruction isn't an X-unit, or an I-unit instruction |
800eeca4 JW |
5946 | that can go into the X slot of an MLX template. Duh. */ |
5947 | if (md.num_slots_in_use >= NUM_SLOTS) | |
5948 | { | |
5949 | as_bad_where (md.slot[curr].src_file, | |
5950 | md.slot[curr].src_line, | |
5951 | "`%s' can't go in X slot of " | |
5952 | "MLX template", idesc->name); | |
542d6675 | 5953 | /* drop this insn so we don't livelock: */ |
800eeca4 JW |
5954 | --md.num_slots_in_use; |
5955 | } | |
5956 | break; | |
5957 | } | |
5958 | continue; /* try next slot */ | |
5959 | } | |
5960 | ||
800eeca4 JW |
5961 | { |
5962 | bfd_vma addr; | |
5963 | ||
f1bcba5b | 5964 | addr = frag_now->fr_address + frag_now_fix () - 16 + i; |
800eeca4 JW |
5965 | dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); |
5966 | } | |
5967 | ||
88be23ec BS |
5968 | if (errata_nop_necessary_p (md.slot + curr, insn_unit)) |
5969 | as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); | |
5970 | ||
800eeca4 JW |
5971 | build_insn (md.slot + curr, insn + i); |
5972 | ||
10850f29 JW |
5973 | /* Set slot counts for non prologue/body unwind records. */ |
5974 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) | |
5975 | if (ptr->r.type != prologue && ptr->r.type != prologue_gr | |
5976 | && ptr->r.type != body) | |
f5a30c2e JW |
5977 | { |
5978 | ptr->slot_number = (unsigned long) f + i; | |
5979 | ptr->slot_frag = frag_now; | |
5980 | } | |
10850f29 | 5981 | md.slot[curr].unwind_record = NULL; |
10850f29 | 5982 | |
800eeca4 JW |
5983 | if (required_unit == IA64_UNIT_L) |
5984 | { | |
5985 | know (i == 1); | |
5986 | /* skip one slot for long/X-unit instructions */ | |
5987 | ++i; | |
5988 | } | |
5989 | --md.num_slots_in_use; | |
5990 | ||
542d6675 | 5991 | /* now is a good time to fix up the labels for this insn: */ |
800eeca4 JW |
5992 | for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) |
5993 | { | |
5994 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16); | |
5995 | symbol_set_frag (lfix->sym, frag_now); | |
5996 | } | |
f1bcba5b JW |
5997 | /* and fix up the tags also. */ |
5998 | for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) | |
5999 | { | |
6000 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); | |
6001 | symbol_set_frag (lfix->sym, frag_now); | |
6002 | } | |
800eeca4 JW |
6003 | |
6004 | for (j = 0; j < md.slot[curr].num_fixups; ++j) | |
6005 | { | |
6006 | ifix = md.slot[curr].fixup + j; | |
5a080f89 | 6007 | fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, |
800eeca4 JW |
6008 | &ifix->expr, ifix->is_pcrel, ifix->code); |
6009 | fix->tc_fix_data.opnd = ifix->opnd; | |
6010 | fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); | |
6011 | fix->fx_file = md.slot[curr].src_file; | |
6012 | fix->fx_line = md.slot[curr].src_line; | |
6013 | } | |
6014 | ||
6015 | end_of_insn_group = md.slot[curr].end_of_insn_group; | |
6016 | ||
88be23ec BS |
6017 | if (end_of_insn_group) |
6018 | { | |
6019 | md.group_idx = (md.group_idx + 1) % 3; | |
6020 | memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); | |
6021 | } | |
6022 | ||
542d6675 | 6023 | /* clear slot: */ |
800eeca4 JW |
6024 | ia64_free_opcode (md.slot[curr].idesc); |
6025 | memset (md.slot + curr, 0, sizeof (md.slot[curr])); | |
6026 | md.slot[curr].user_template = -1; | |
6027 | ||
6028 | if (manual_bundling_off) | |
6029 | { | |
6030 | manual_bundling = 0; | |
6031 | break; | |
6032 | } | |
6033 | curr = (curr + 1) % NUM_SLOTS; | |
6034 | idesc = md.slot[curr].idesc; | |
6035 | } | |
6036 | if (manual_bundling) | |
6037 | { | |
6038 | if (md.num_slots_in_use > 0) | |
6039 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6040 | "`%s' does not fit into %s template", | |
6041 | idesc->name, ia64_templ_desc[template].name); | |
6042 | else | |
6043 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6044 | "Missing '}' at end of file"); | |
6045 | } | |
6046 | know (md.num_slots_in_use < NUM_SLOTS); | |
6047 | ||
6048 | t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); | |
6049 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
6050 | ||
44f5c83a JW |
6051 | number_to_chars_littleendian (f + 0, t0, 8); |
6052 | number_to_chars_littleendian (f + 8, t1, 8); | |
f5a30c2e JW |
6053 | |
6054 | unwind.next_slot_number = (unsigned long) f + 16; | |
6055 | unwind.next_slot_frag = frag_now; | |
800eeca4 JW |
6056 | } |
6057 | ||
6058 | int | |
6059 | md_parse_option (c, arg) | |
6060 | int c; | |
6061 | char *arg; | |
6062 | { | |
7463c317 | 6063 | |
800eeca4 JW |
6064 | switch (c) |
6065 | { | |
c43c2cc5 | 6066 | /* Switches from the Intel assembler. */ |
44f5c83a | 6067 | case 'm': |
800eeca4 JW |
6068 | if (strcmp (arg, "ilp64") == 0 |
6069 | || strcmp (arg, "lp64") == 0 | |
6070 | || strcmp (arg, "p64") == 0) | |
6071 | { | |
6072 | md.flags |= EF_IA_64_ABI64; | |
6073 | } | |
6074 | else if (strcmp (arg, "ilp32") == 0) | |
6075 | { | |
6076 | md.flags &= ~EF_IA_64_ABI64; | |
6077 | } | |
6078 | else if (strcmp (arg, "le") == 0) | |
6079 | { | |
6080 | md.flags &= ~EF_IA_64_BE; | |
6081 | } | |
6082 | else if (strcmp (arg, "be") == 0) | |
6083 | { | |
6084 | md.flags |= EF_IA_64_BE; | |
6085 | } | |
6086 | else | |
6087 | return 0; | |
6088 | break; | |
6089 | ||
6090 | case 'N': | |
6091 | if (strcmp (arg, "so") == 0) | |
6092 | { | |
542d6675 | 6093 | /* Suppress signon message. */ |
800eeca4 JW |
6094 | } |
6095 | else if (strcmp (arg, "pi") == 0) | |
6096 | { | |
6097 | /* Reject privileged instructions. FIXME */ | |
6098 | } | |
6099 | else if (strcmp (arg, "us") == 0) | |
6100 | { | |
6101 | /* Allow union of signed and unsigned range. FIXME */ | |
6102 | } | |
6103 | else if (strcmp (arg, "close_fcalls") == 0) | |
6104 | { | |
6105 | /* Do not resolve global function calls. */ | |
6106 | } | |
6107 | else | |
6108 | return 0; | |
6109 | break; | |
6110 | ||
6111 | case 'C': | |
6112 | /* temp[="prefix"] Insert temporary labels into the object file | |
6113 | symbol table prefixed by "prefix". | |
6114 | Default prefix is ":temp:". | |
6115 | */ | |
6116 | break; | |
6117 | ||
6118 | case 'a': | |
800eeca4 JW |
6119 | /* indirect=<tgt> Assume unannotated indirect branches behavior |
6120 | according to <tgt> -- | |
6121 | exit: branch out from the current context (default) | |
6122 | labels: all labels in context may be branch targets | |
6123 | */ | |
85b40035 L |
6124 | if (strncmp (arg, "indirect=", 9) != 0) |
6125 | return 0; | |
800eeca4 JW |
6126 | break; |
6127 | ||
6128 | case 'x': | |
6129 | /* -X conflicts with an ignored option, use -x instead */ | |
6130 | md.detect_dv = 1; | |
6131 | if (!arg || strcmp (arg, "explicit") == 0) | |
542d6675 KH |
6132 | { |
6133 | /* set default mode to explicit */ | |
6134 | md.default_explicit_mode = 1; | |
6135 | break; | |
6136 | } | |
800eeca4 | 6137 | else if (strcmp (arg, "auto") == 0) |
542d6675 KH |
6138 | { |
6139 | md.default_explicit_mode = 0; | |
6140 | } | |
800eeca4 | 6141 | else if (strcmp (arg, "debug") == 0) |
542d6675 KH |
6142 | { |
6143 | md.debug_dv = 1; | |
6144 | } | |
800eeca4 | 6145 | else if (strcmp (arg, "debugx") == 0) |
542d6675 KH |
6146 | { |
6147 | md.default_explicit_mode = 1; | |
6148 | md.debug_dv = 1; | |
6149 | } | |
800eeca4 | 6150 | else |
542d6675 KH |
6151 | { |
6152 | as_bad (_("Unrecognized option '-x%s'"), arg); | |
6153 | } | |
800eeca4 JW |
6154 | break; |
6155 | ||
6156 | case 'S': | |
6157 | /* nops Print nops statistics. */ | |
6158 | break; | |
6159 | ||
c43c2cc5 JW |
6160 | /* GNU specific switches for gcc. */ |
6161 | case OPTION_MCONSTANT_GP: | |
6162 | md.flags |= EF_IA_64_CONS_GP; | |
6163 | break; | |
6164 | ||
6165 | case OPTION_MAUTO_PIC: | |
6166 | md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; | |
6167 | break; | |
6168 | ||
800eeca4 JW |
6169 | default: |
6170 | return 0; | |
6171 | } | |
6172 | ||
6173 | return 1; | |
6174 | } | |
6175 | ||
6176 | void | |
6177 | md_show_usage (stream) | |
6178 | FILE *stream; | |
6179 | { | |
542d6675 | 6180 | fputs (_("\ |
800eeca4 | 6181 | IA-64 options:\n\ |
44f5c83a JW |
6182 | -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ |
6183 | -mle | -mbe select little- or big-endian byte order (default -mle)\n\ | |
800eeca4 JW |
6184 | -x | -xexplicit turn on dependency violation checking (default)\n\ |
6185 | -xauto automagically remove dependency violations\n\ | |
6186 | -xdebug debug dependency violation checker\n"), | |
6187 | stream); | |
6188 | } | |
6189 | ||
44576e1f RH |
6190 | /* Return true if TYPE fits in TEMPL at SLOT. */ |
6191 | ||
6192 | static int | |
800eeca4 JW |
6193 | match (int templ, int type, int slot) |
6194 | { | |
6195 | enum ia64_unit unit; | |
6196 | int result; | |
6197 | ||
6198 | unit = ia64_templ_desc[templ].exec_unit[slot]; | |
6199 | switch (type) | |
6200 | { | |
6201 | case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ | |
6202 | case IA64_TYPE_A: | |
6203 | result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); | |
6204 | break; | |
6205 | case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; | |
6206 | case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; | |
6207 | case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; | |
6208 | case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; | |
6209 | case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; | |
6210 | default: result = 0; break; | |
6211 | } | |
6212 | return result; | |
6213 | } | |
6214 | ||
44576e1f RH |
6215 | /* Add a bit of extra goodness if a nop of type F or B would fit |
6216 | in TEMPL at SLOT. */ | |
6217 | ||
6218 | static inline int | |
6219 | extra_goodness (int templ, int slot) | |
6220 | { | |
ebeeafe6 | 6221 | if (slot == 1 && match (templ, IA64_TYPE_F, slot)) |
44576e1f | 6222 | return 2; |
ebeeafe6 | 6223 | if (slot == 2 && match (templ, IA64_TYPE_B, slot)) |
44576e1f RH |
6224 | return 1; |
6225 | return 0; | |
6226 | } | |
6227 | ||
800eeca4 JW |
6228 | /* This function is called once, at assembler startup time. It sets |
6229 | up all the tables, etc. that the MD part of the assembler will need | |
6230 | that can be determined before arguments are parsed. */ | |
6231 | void | |
6232 | md_begin () | |
6233 | { | |
44f5c83a | 6234 | int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; |
800eeca4 JW |
6235 | const char *err; |
6236 | char name[8]; | |
6237 | ||
6238 | md.auto_align = 1; | |
6239 | md.explicit_mode = md.default_explicit_mode; | |
6240 | ||
6241 | bfd_set_section_alignment (stdoutput, text_section, 4); | |
6242 | ||
44f5c83a | 6243 | target_big_endian = TARGET_BYTES_BIG_ENDIAN; |
800eeca4 | 6244 | pseudo_func[FUNC_FPTR_RELATIVE].u.sym = |
542d6675 KH |
6245 | symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, |
6246 | &zero_address_frag); | |
800eeca4 JW |
6247 | |
6248 | pseudo_func[FUNC_GP_RELATIVE].u.sym = | |
542d6675 KH |
6249 | symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, |
6250 | &zero_address_frag); | |
800eeca4 JW |
6251 | |
6252 | pseudo_func[FUNC_LT_RELATIVE].u.sym = | |
542d6675 KH |
6253 | symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, |
6254 | &zero_address_frag); | |
800eeca4 | 6255 | |
c67e42c9 | 6256 | pseudo_func[FUNC_PC_RELATIVE].u.sym = |
542d6675 KH |
6257 | symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, |
6258 | &zero_address_frag); | |
c67e42c9 | 6259 | |
800eeca4 | 6260 | pseudo_func[FUNC_PLT_RELATIVE].u.sym = |
542d6675 KH |
6261 | symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, |
6262 | &zero_address_frag); | |
800eeca4 JW |
6263 | |
6264 | pseudo_func[FUNC_SEC_RELATIVE].u.sym = | |
542d6675 KH |
6265 | symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, |
6266 | &zero_address_frag); | |
800eeca4 JW |
6267 | |
6268 | pseudo_func[FUNC_SEG_RELATIVE].u.sym = | |
542d6675 KH |
6269 | symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, |
6270 | &zero_address_frag); | |
800eeca4 JW |
6271 | |
6272 | pseudo_func[FUNC_LTV_RELATIVE].u.sym = | |
542d6675 KH |
6273 | symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, |
6274 | &zero_address_frag); | |
800eeca4 JW |
6275 | |
6276 | pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = | |
542d6675 KH |
6277 | symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, |
6278 | &zero_address_frag); | |
800eeca4 | 6279 | |
197865e8 | 6280 | /* Compute the table of best templates. We compute goodness as a |
44576e1f RH |
6281 | base 4 value, in which each match counts for 3, each F counts |
6282 | for 2, each B counts for 1. This should maximize the number of | |
6283 | F and B nops in the chosen bundles, which is good because these | |
6284 | pipelines are least likely to be overcommitted. */ | |
800eeca4 JW |
6285 | for (i = 0; i < IA64_NUM_TYPES; ++i) |
6286 | for (j = 0; j < IA64_NUM_TYPES; ++j) | |
6287 | for (k = 0; k < IA64_NUM_TYPES; ++k) | |
6288 | { | |
6289 | best = 0; | |
6290 | for (t = 0; t < NELEMS (ia64_templ_desc); ++t) | |
6291 | { | |
6292 | goodness = 0; | |
6293 | if (match (t, i, 0)) | |
6294 | { | |
6295 | if (match (t, j, 1)) | |
6296 | { | |
6297 | if (match (t, k, 2)) | |
44576e1f | 6298 | goodness = 3 + 3 + 3; |
800eeca4 | 6299 | else |
44576e1f | 6300 | goodness = 3 + 3 + extra_goodness (t, 2); |
800eeca4 JW |
6301 | } |
6302 | else if (match (t, j, 2)) | |
44576e1f | 6303 | goodness = 3 + 3 + extra_goodness (t, 1); |
800eeca4 | 6304 | else |
44576e1f RH |
6305 | { |
6306 | goodness = 3; | |
6307 | goodness += extra_goodness (t, 1); | |
6308 | goodness += extra_goodness (t, 2); | |
6309 | } | |
800eeca4 JW |
6310 | } |
6311 | else if (match (t, i, 1)) | |
6312 | { | |
6313 | if (match (t, j, 2)) | |
44576e1f | 6314 | goodness = 3 + 3; |
800eeca4 | 6315 | else |
44576e1f | 6316 | goodness = 3 + extra_goodness (t, 2); |
800eeca4 JW |
6317 | } |
6318 | else if (match (t, i, 2)) | |
44576e1f | 6319 | goodness = 3 + extra_goodness (t, 1); |
800eeca4 JW |
6320 | |
6321 | if (goodness > best) | |
6322 | { | |
6323 | best = goodness; | |
6324 | best_template[i][j][k] = t; | |
6325 | } | |
6326 | } | |
6327 | } | |
6328 | ||
6329 | for (i = 0; i < NUM_SLOTS; ++i) | |
6330 | md.slot[i].user_template = -1; | |
6331 | ||
6332 | md.pseudo_hash = hash_new (); | |
6333 | for (i = 0; i < NELEMS (pseudo_opcode); ++i) | |
6334 | { | |
6335 | err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, | |
6336 | (void *) (pseudo_opcode + i)); | |
6337 | if (err) | |
6338 | as_fatal ("ia64.md_begin: can't hash `%s': %s", | |
6339 | pseudo_opcode[i].name, err); | |
6340 | } | |
6341 | ||
6342 | md.reg_hash = hash_new (); | |
6343 | md.dynreg_hash = hash_new (); | |
6344 | md.const_hash = hash_new (); | |
6345 | md.entry_hash = hash_new (); | |
6346 | ||
542d6675 | 6347 | /* general registers: */ |
800eeca4 JW |
6348 | |
6349 | total = 128; | |
6350 | for (i = 0; i < total; ++i) | |
6351 | { | |
6352 | sprintf (name, "r%d", i - REG_GR); | |
6353 | md.regsym[i] = declare_register (name, i); | |
6354 | } | |
6355 | ||
542d6675 | 6356 | /* floating point registers: */ |
800eeca4 JW |
6357 | total += 128; |
6358 | for (; i < total; ++i) | |
6359 | { | |
6360 | sprintf (name, "f%d", i - REG_FR); | |
6361 | md.regsym[i] = declare_register (name, i); | |
6362 | } | |
6363 | ||
542d6675 | 6364 | /* application registers: */ |
800eeca4 JW |
6365 | total += 128; |
6366 | ar_base = i; | |
6367 | for (; i < total; ++i) | |
6368 | { | |
6369 | sprintf (name, "ar%d", i - REG_AR); | |
6370 | md.regsym[i] = declare_register (name, i); | |
6371 | } | |
6372 | ||
542d6675 | 6373 | /* control registers: */ |
800eeca4 JW |
6374 | total += 128; |
6375 | cr_base = i; | |
6376 | for (; i < total; ++i) | |
6377 | { | |
6378 | sprintf (name, "cr%d", i - REG_CR); | |
6379 | md.regsym[i] = declare_register (name, i); | |
6380 | } | |
6381 | ||
542d6675 | 6382 | /* predicate registers: */ |
800eeca4 JW |
6383 | total += 64; |
6384 | for (; i < total; ++i) | |
6385 | { | |
6386 | sprintf (name, "p%d", i - REG_P); | |
6387 | md.regsym[i] = declare_register (name, i); | |
6388 | } | |
6389 | ||
542d6675 | 6390 | /* branch registers: */ |
800eeca4 JW |
6391 | total += 8; |
6392 | for (; i < total; ++i) | |
6393 | { | |
6394 | sprintf (name, "b%d", i - REG_BR); | |
6395 | md.regsym[i] = declare_register (name, i); | |
6396 | } | |
6397 | ||
6398 | md.regsym[REG_IP] = declare_register ("ip", REG_IP); | |
6399 | md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); | |
6400 | md.regsym[REG_PR] = declare_register ("pr", REG_PR); | |
6401 | md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); | |
6402 | md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); | |
6403 | md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); | |
6404 | md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); | |
6405 | ||
6406 | for (i = 0; i < NELEMS (indirect_reg); ++i) | |
6407 | { | |
6408 | regnum = indirect_reg[i].regnum; | |
6409 | md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); | |
6410 | } | |
6411 | ||
542d6675 | 6412 | /* define synonyms for application registers: */ |
800eeca4 JW |
6413 | for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) |
6414 | md.regsym[i] = declare_register (ar[i - REG_AR].name, | |
6415 | REG_AR + ar[i - REG_AR].regnum); | |
6416 | ||
542d6675 | 6417 | /* define synonyms for control registers: */ |
800eeca4 JW |
6418 | for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) |
6419 | md.regsym[i] = declare_register (cr[i - REG_CR].name, | |
6420 | REG_CR + cr[i - REG_CR].regnum); | |
6421 | ||
6422 | declare_register ("gp", REG_GR + 1); | |
6423 | declare_register ("sp", REG_GR + 12); | |
6424 | declare_register ("rp", REG_BR + 0); | |
6425 | ||
542d6675 | 6426 | /* pseudo-registers used to specify unwind info: */ |
e0c9811a JW |
6427 | declare_register ("psp", REG_PSP); |
6428 | ||
800eeca4 JW |
6429 | declare_register_set ("ret", 4, REG_GR + 8); |
6430 | declare_register_set ("farg", 8, REG_FR + 8); | |
6431 | declare_register_set ("fret", 8, REG_FR + 8); | |
6432 | ||
6433 | for (i = 0; i < NELEMS (const_bits); ++i) | |
6434 | { | |
6435 | err = hash_insert (md.const_hash, const_bits[i].name, | |
6436 | (PTR) (const_bits + i)); | |
6437 | if (err) | |
6438 | as_fatal ("Inserting \"%s\" into constant hash table failed: %s", | |
6439 | name, err); | |
6440 | } | |
6441 | ||
44f5c83a JW |
6442 | /* Set the architecture and machine depending on defaults and command line |
6443 | options. */ | |
6444 | if (md.flags & EF_IA_64_ABI64) | |
6445 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); | |
6446 | else | |
6447 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); | |
6448 | ||
6449 | if (! ok) | |
6450 | as_warn (_("Could not set architecture and machine")); | |
800eeca4 JW |
6451 | |
6452 | md.mem_offset.hint = 0; | |
6453 | md.path = 0; | |
6454 | md.maxpaths = 0; | |
6455 | md.entry_labels = NULL; | |
6456 | } | |
6457 | ||
44f5c83a JW |
6458 | /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin |
6459 | because that is called after md_parse_option which is where we do the | |
6460 | dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the | |
6461 | default endianness. */ | |
6462 | ||
6463 | void | |
6464 | ia64_init (argc, argv) | |
2434f565 JW |
6465 | int argc ATTRIBUTE_UNUSED; |
6466 | char **argv ATTRIBUTE_UNUSED; | |
44f5c83a JW |
6467 | { |
6468 | md.flags = EF_IA_64_ABI64; | |
6469 | if (TARGET_BYTES_BIG_ENDIAN) | |
6470 | md.flags |= EF_IA_64_BE; | |
6471 | } | |
6472 | ||
6473 | /* Return a string for the target object file format. */ | |
6474 | ||
6475 | const char * | |
6476 | ia64_target_format () | |
6477 | { | |
6478 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
6479 | { | |
72a76794 JW |
6480 | if (md.flags & EF_IA_64_BE) |
6481 | { | |
6482 | if (md.flags & EF_IA_64_ABI64) | |
7463c317 TW |
6483 | #ifdef TE_AIX50 |
6484 | return "elf64-ia64-aix-big"; | |
6485 | #else | |
72a76794 | 6486 | return "elf64-ia64-big"; |
7463c317 | 6487 | #endif |
72a76794 | 6488 | else |
7463c317 TW |
6489 | #ifdef TE_AIX50 |
6490 | return "elf32-ia64-aix-big"; | |
6491 | #else | |
72a76794 | 6492 | return "elf32-ia64-big"; |
7463c317 | 6493 | #endif |
72a76794 | 6494 | } |
44f5c83a | 6495 | else |
72a76794 JW |
6496 | { |
6497 | if (md.flags & EF_IA_64_ABI64) | |
7463c317 TW |
6498 | #ifdef TE_AIX50 |
6499 | return "elf64-ia64-aix-little"; | |
6500 | #else | |
72a76794 | 6501 | return "elf64-ia64-little"; |
7463c317 | 6502 | #endif |
72a76794 | 6503 | else |
7463c317 TW |
6504 | #ifdef TE_AIX50 |
6505 | return "elf32-ia64-aix-little"; | |
6506 | #else | |
72a76794 | 6507 | return "elf32-ia64-little"; |
7463c317 | 6508 | #endif |
72a76794 | 6509 | } |
44f5c83a JW |
6510 | } |
6511 | else | |
6512 | return "unknown-format"; | |
6513 | } | |
6514 | ||
800eeca4 JW |
6515 | void |
6516 | ia64_end_of_source () | |
6517 | { | |
542d6675 | 6518 | /* terminate insn group upon reaching end of file: */ |
800eeca4 JW |
6519 | insn_group_break (1, 0, 0); |
6520 | ||
542d6675 | 6521 | /* emits slots we haven't written yet: */ |
800eeca4 JW |
6522 | ia64_flush_insns (); |
6523 | ||
6524 | bfd_set_private_flags (stdoutput, md.flags); | |
6525 | ||
800eeca4 JW |
6526 | md.mem_offset.hint = 0; |
6527 | } | |
6528 | ||
6529 | void | |
6530 | ia64_start_line () | |
6531 | { | |
f1bcba5b JW |
6532 | if (md.qp.X_op == O_register) |
6533 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
6534 | md.qp.X_op = O_absent; |
6535 | ||
6536 | if (ignore_input ()) | |
6537 | return; | |
6538 | ||
6539 | if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') | |
6540 | { | |
6541 | if (md.detect_dv && !md.explicit_mode) | |
542d6675 | 6542 | as_warn (_("Explicit stops are ignored in auto mode")); |
800eeca4 | 6543 | else |
542d6675 | 6544 | insn_group_break (1, 0, 0); |
800eeca4 JW |
6545 | } |
6546 | } | |
6547 | ||
f1bcba5b JW |
6548 | /* This is a hook for ia64_frob_label, so that it can distinguish tags from |
6549 | labels. */ | |
6550 | static int defining_tag = 0; | |
6551 | ||
800eeca4 JW |
6552 | int |
6553 | ia64_unrecognized_line (ch) | |
6554 | int ch; | |
6555 | { | |
6556 | switch (ch) | |
6557 | { | |
6558 | case '(': | |
6559 | expression (&md.qp); | |
6560 | if (*input_line_pointer++ != ')') | |
6561 | { | |
6562 | as_bad ("Expected ')'"); | |
6563 | return 0; | |
6564 | } | |
6565 | if (md.qp.X_op != O_register) | |
6566 | { | |
6567 | as_bad ("Qualifying predicate expected"); | |
6568 | return 0; | |
6569 | } | |
6570 | if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) | |
6571 | { | |
6572 | as_bad ("Predicate register expected"); | |
6573 | return 0; | |
6574 | } | |
6575 | return 1; | |
6576 | ||
6577 | case '{': | |
6578 | if (md.manual_bundling) | |
6579 | as_warn ("Found '{' when manual bundling is already turned on"); | |
6580 | else | |
6581 | CURR_SLOT.manual_bundling_on = 1; | |
6582 | md.manual_bundling = 1; | |
6583 | ||
542d6675 KH |
6584 | /* Bundling is only acceptable in explicit mode |
6585 | or when in default automatic mode. */ | |
800eeca4 | 6586 | if (md.detect_dv && !md.explicit_mode) |
542d6675 KH |
6587 | { |
6588 | if (!md.mode_explicitly_set | |
6589 | && !md.default_explicit_mode) | |
6590 | dot_dv_mode ('E'); | |
6591 | else | |
6592 | as_warn (_("Found '{' after explicit switch to automatic mode")); | |
6593 | } | |
800eeca4 JW |
6594 | return 1; |
6595 | ||
6596 | case '}': | |
6597 | if (!md.manual_bundling) | |
6598 | as_warn ("Found '}' when manual bundling is off"); | |
6599 | else | |
6600 | PREV_SLOT.manual_bundling_off = 1; | |
6601 | md.manual_bundling = 0; | |
6602 | ||
6603 | /* switch back to automatic mode, if applicable */ | |
197865e8 | 6604 | if (md.detect_dv |
542d6675 KH |
6605 | && md.explicit_mode |
6606 | && !md.mode_explicitly_set | |
6607 | && !md.default_explicit_mode) | |
6608 | dot_dv_mode ('A'); | |
800eeca4 JW |
6609 | |
6610 | /* Allow '{' to follow on the same line. We also allow ";;", but that | |
6611 | happens automatically because ';' is an end of line marker. */ | |
6612 | SKIP_WHITESPACE (); | |
6613 | if (input_line_pointer[0] == '{') | |
6614 | { | |
6615 | input_line_pointer++; | |
6616 | return ia64_unrecognized_line ('{'); | |
6617 | } | |
6618 | ||
6619 | demand_empty_rest_of_line (); | |
6620 | return 1; | |
6621 | ||
f1bcba5b JW |
6622 | case '[': |
6623 | { | |
6624 | char *s; | |
6625 | char c; | |
6626 | symbolS *tag; | |
4d5a53ff | 6627 | int temp; |
f1bcba5b JW |
6628 | |
6629 | if (md.qp.X_op == O_register) | |
6630 | { | |
6631 | as_bad ("Tag must come before qualifying predicate."); | |
6632 | return 0; | |
6633 | } | |
4d5a53ff JW |
6634 | |
6635 | /* This implements just enough of read_a_source_file in read.c to | |
6636 | recognize labels. */ | |
6637 | if (is_name_beginner (*input_line_pointer)) | |
6638 | { | |
6639 | s = input_line_pointer; | |
6640 | c = get_symbol_end (); | |
6641 | } | |
6642 | else if (LOCAL_LABELS_FB | |
6643 | && isdigit ((unsigned char) *input_line_pointer)) | |
6644 | { | |
6645 | temp = 0; | |
6646 | while (isdigit ((unsigned char) *input_line_pointer)) | |
6647 | temp = (temp * 10) + *input_line_pointer++ - '0'; | |
6648 | fb_label_instance_inc (temp); | |
6649 | s = fb_label_name (temp, 0); | |
6650 | c = *input_line_pointer; | |
6651 | } | |
6652 | else | |
6653 | { | |
6654 | s = NULL; | |
6655 | c = '\0'; | |
6656 | } | |
f1bcba5b JW |
6657 | if (c != ':') |
6658 | { | |
6659 | /* Put ':' back for error messages' sake. */ | |
6660 | *input_line_pointer++ = ':'; | |
6661 | as_bad ("Expected ':'"); | |
6662 | return 0; | |
6663 | } | |
4d5a53ff | 6664 | |
f1bcba5b JW |
6665 | defining_tag = 1; |
6666 | tag = colon (s); | |
6667 | defining_tag = 0; | |
6668 | /* Put ':' back for error messages' sake. */ | |
6669 | *input_line_pointer++ = ':'; | |
6670 | if (*input_line_pointer++ != ']') | |
6671 | { | |
6672 | as_bad ("Expected ']'"); | |
6673 | return 0; | |
6674 | } | |
6675 | if (! tag) | |
6676 | { | |
6677 | as_bad ("Tag name expected"); | |
6678 | return 0; | |
6679 | } | |
6680 | return 1; | |
6681 | } | |
6682 | ||
800eeca4 JW |
6683 | default: |
6684 | break; | |
6685 | } | |
542d6675 KH |
6686 | |
6687 | /* Not a valid line. */ | |
6688 | return 0; | |
800eeca4 JW |
6689 | } |
6690 | ||
6691 | void | |
6692 | ia64_frob_label (sym) | |
6693 | struct symbol *sym; | |
6694 | { | |
6695 | struct label_fix *fix; | |
6696 | ||
f1bcba5b JW |
6697 | /* Tags need special handling since they are not bundle breaks like |
6698 | labels. */ | |
6699 | if (defining_tag) | |
6700 | { | |
6701 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
6702 | fix->sym = sym; | |
6703 | fix->next = CURR_SLOT.tag_fixups; | |
6704 | CURR_SLOT.tag_fixups = fix; | |
6705 | ||
6706 | return; | |
6707 | } | |
6708 | ||
800eeca4 JW |
6709 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
6710 | { | |
6711 | md.last_text_seg = now_seg; | |
6712 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
6713 | fix->sym = sym; | |
6714 | fix->next = CURR_SLOT.label_fixups; | |
6715 | CURR_SLOT.label_fixups = fix; | |
6716 | ||
542d6675 | 6717 | /* Keep track of how many code entry points we've seen. */ |
800eeca4 | 6718 | if (md.path == md.maxpaths) |
542d6675 KH |
6719 | { |
6720 | md.maxpaths += 20; | |
6721 | md.entry_labels = (const char **) | |
6722 | xrealloc ((void *) md.entry_labels, | |
6723 | md.maxpaths * sizeof (char *)); | |
6724 | } | |
800eeca4 JW |
6725 | md.entry_labels[md.path++] = S_GET_NAME (sym); |
6726 | } | |
6727 | } | |
6728 | ||
6729 | void | |
6730 | ia64_flush_pending_output () | |
6731 | { | |
4d5a53ff JW |
6732 | if (!md.keep_pending_output |
6733 | && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) | |
800eeca4 JW |
6734 | { |
6735 | /* ??? This causes many unnecessary stop bits to be emitted. | |
6736 | Unfortunately, it isn't clear if it is safe to remove this. */ | |
6737 | insn_group_break (1, 0, 0); | |
6738 | ia64_flush_insns (); | |
6739 | } | |
6740 | } | |
6741 | ||
6742 | /* Do ia64-specific expression optimization. All that's done here is | |
6743 | to transform index expressions that are either due to the indexing | |
6744 | of rotating registers or due to the indexing of indirect register | |
6745 | sets. */ | |
6746 | int | |
6747 | ia64_optimize_expr (l, op, r) | |
6748 | expressionS *l; | |
6749 | operatorT op; | |
6750 | expressionS *r; | |
6751 | { | |
6752 | unsigned num_regs; | |
6753 | ||
6754 | if (op == O_index) | |
6755 | { | |
6756 | if (l->X_op == O_register && r->X_op == O_constant) | |
6757 | { | |
6758 | num_regs = (l->X_add_number >> 16); | |
6759 | if ((unsigned) r->X_add_number >= num_regs) | |
6760 | { | |
6761 | if (!num_regs) | |
6762 | as_bad ("No current frame"); | |
6763 | else | |
6764 | as_bad ("Index out of range 0..%u", num_regs - 1); | |
6765 | r->X_add_number = 0; | |
6766 | } | |
6767 | l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; | |
6768 | return 1; | |
6769 | } | |
6770 | else if (l->X_op == O_register && r->X_op == O_register) | |
6771 | { | |
6772 | if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR | |
6773 | || l->X_add_number == IND_MEM) | |
6774 | { | |
6775 | as_bad ("Indirect register set name expected"); | |
6776 | l->X_add_number = IND_CPUID; | |
6777 | } | |
6778 | l->X_op = O_index; | |
6779 | l->X_op_symbol = md.regsym[l->X_add_number]; | |
6780 | l->X_add_number = r->X_add_number; | |
6781 | return 1; | |
6782 | } | |
6783 | } | |
6784 | return 0; | |
6785 | } | |
6786 | ||
6787 | int | |
6788 | ia64_parse_name (name, e) | |
6789 | char *name; | |
6790 | expressionS *e; | |
6791 | { | |
6792 | struct const_desc *cdesc; | |
6793 | struct dynreg *dr = 0; | |
6794 | unsigned int regnum; | |
6795 | struct symbol *sym; | |
6796 | char *end; | |
6797 | ||
542d6675 | 6798 | /* first see if NAME is a known register name: */ |
800eeca4 JW |
6799 | sym = hash_find (md.reg_hash, name); |
6800 | if (sym) | |
6801 | { | |
6802 | e->X_op = O_register; | |
6803 | e->X_add_number = S_GET_VALUE (sym); | |
6804 | return 1; | |
6805 | } | |
6806 | ||
6807 | cdesc = hash_find (md.const_hash, name); | |
6808 | if (cdesc) | |
6809 | { | |
6810 | e->X_op = O_constant; | |
6811 | e->X_add_number = cdesc->value; | |
6812 | return 1; | |
6813 | } | |
6814 | ||
542d6675 | 6815 | /* check for inN, locN, or outN: */ |
800eeca4 JW |
6816 | switch (name[0]) |
6817 | { | |
6818 | case 'i': | |
6819 | if (name[1] == 'n' && isdigit (name[2])) | |
6820 | { | |
6821 | dr = &md.in; | |
6822 | name += 2; | |
6823 | } | |
6824 | break; | |
6825 | ||
6826 | case 'l': | |
6827 | if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3])) | |
6828 | { | |
6829 | dr = &md.loc; | |
6830 | name += 3; | |
6831 | } | |
6832 | break; | |
6833 | ||
6834 | case 'o': | |
6835 | if (name[1] == 'u' && name[2] == 't' && isdigit (name[3])) | |
6836 | { | |
6837 | dr = &md.out; | |
6838 | name += 3; | |
6839 | } | |
6840 | break; | |
6841 | ||
6842 | default: | |
6843 | break; | |
6844 | } | |
6845 | ||
6846 | if (dr) | |
6847 | { | |
542d6675 | 6848 | /* The name is inN, locN, or outN; parse the register number. */ |
800eeca4 JW |
6849 | regnum = strtoul (name, &end, 10); |
6850 | if (end > name && *end == '\0') | |
6851 | { | |
6852 | if ((unsigned) regnum >= dr->num_regs) | |
6853 | { | |
6854 | if (!dr->num_regs) | |
6855 | as_bad ("No current frame"); | |
6856 | else | |
542d6675 KH |
6857 | as_bad ("Register number out of range 0..%u", |
6858 | dr->num_regs - 1); | |
800eeca4 JW |
6859 | regnum = 0; |
6860 | } | |
6861 | e->X_op = O_register; | |
6862 | e->X_add_number = dr->base + regnum; | |
6863 | return 1; | |
6864 | } | |
6865 | } | |
6866 | ||
6867 | if ((dr = hash_find (md.dynreg_hash, name))) | |
6868 | { | |
6869 | /* We've got ourselves the name of a rotating register set. | |
542d6675 KH |
6870 | Store the base register number in the low 16 bits of |
6871 | X_add_number and the size of the register set in the top 16 | |
6872 | bits. */ | |
800eeca4 JW |
6873 | e->X_op = O_register; |
6874 | e->X_add_number = dr->base | (dr->num_regs << 16); | |
6875 | return 1; | |
6876 | } | |
6877 | return 0; | |
6878 | } | |
6879 | ||
6880 | /* Remove the '#' suffix that indicates a symbol as opposed to a register. */ | |
6881 | ||
6882 | char * | |
6883 | ia64_canonicalize_symbol_name (name) | |
6884 | char *name; | |
6885 | { | |
542d6675 KH |
6886 | size_t len = strlen (name); |
6887 | if (len > 1 && name[len - 1] == '#') | |
6888 | name[len - 1] = '\0'; | |
800eeca4 JW |
6889 | return name; |
6890 | } | |
6891 | ||
6892 | static int | |
6893 | is_conditional_branch (idesc) | |
542d6675 | 6894 | struct ia64_opcode *idesc; |
800eeca4 JW |
6895 | { |
6896 | return (strncmp (idesc->name, "br", 2) == 0 | |
542d6675 KH |
6897 | && (strcmp (idesc->name, "br") == 0 |
6898 | || strncmp (idesc->name, "br.cond", 7) == 0 | |
6899 | || strncmp (idesc->name, "br.call", 7) == 0 | |
6900 | || strncmp (idesc->name, "br.ret", 6) == 0 | |
6901 | || strcmp (idesc->name, "brl") == 0 | |
6902 | || strncmp (idesc->name, "brl.cond", 7) == 0 | |
6903 | || strncmp (idesc->name, "brl.call", 7) == 0 | |
6904 | || strncmp (idesc->name, "brl.ret", 6) == 0)); | |
800eeca4 JW |
6905 | } |
6906 | ||
6907 | /* Return whether the given opcode is a taken branch. If there's any doubt, | |
542d6675 KH |
6908 | returns zero. */ |
6909 | ||
800eeca4 JW |
6910 | static int |
6911 | is_taken_branch (idesc) | |
542d6675 | 6912 | struct ia64_opcode *idesc; |
800eeca4 JW |
6913 | { |
6914 | return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) | |
542d6675 | 6915 | || strncmp (idesc->name, "br.ia", 5) == 0); |
800eeca4 JW |
6916 | } |
6917 | ||
6918 | /* Return whether the given opcode is an interruption or rfi. If there's any | |
542d6675 KH |
6919 | doubt, returns zero. */ |
6920 | ||
800eeca4 JW |
6921 | static int |
6922 | is_interruption_or_rfi (idesc) | |
542d6675 | 6923 | struct ia64_opcode *idesc; |
800eeca4 JW |
6924 | { |
6925 | if (strcmp (idesc->name, "rfi") == 0) | |
6926 | return 1; | |
6927 | return 0; | |
6928 | } | |
6929 | ||
6930 | /* Returns the index of the given dependency in the opcode's list of chks, or | |
6931 | -1 if there is no dependency. */ | |
542d6675 | 6932 | |
800eeca4 JW |
6933 | static int |
6934 | depends_on (depind, idesc) | |
542d6675 KH |
6935 | int depind; |
6936 | struct ia64_opcode *idesc; | |
800eeca4 JW |
6937 | { |
6938 | int i; | |
6939 | const struct ia64_opcode_dependency *dep = idesc->dependencies; | |
542d6675 | 6940 | for (i = 0; i < dep->nchks; i++) |
800eeca4 | 6941 | { |
542d6675 KH |
6942 | if (depind == DEP (dep->chks[i])) |
6943 | return i; | |
800eeca4 JW |
6944 | } |
6945 | return -1; | |
6946 | } | |
6947 | ||
6948 | /* Determine a set of specific resources used for a particular resource | |
6949 | class. Returns the number of specific resources identified For those | |
6950 | cases which are not determinable statically, the resource returned is | |
197865e8 | 6951 | marked nonspecific. |
800eeca4 JW |
6952 | |
6953 | Meanings of value in 'NOTE': | |
6954 | 1) only read/write when the register number is explicitly encoded in the | |
6955 | insn. | |
6956 | 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only | |
197865e8 | 6957 | accesses CFM when qualifying predicate is in the rotating region. |
800eeca4 JW |
6958 | 3) general register value is used to specify an indirect register; not |
6959 | determinable statically. | |
6960 | 4) only read the given resource when bits 7:0 of the indirect index | |
6961 | register value does not match the register number of the resource; not | |
6962 | determinable statically. | |
6963 | 5) all rules are implementation specific. | |
6964 | 6) only when both the index specified by the reader and the index specified | |
6965 | by the writer have the same value in bits 63:61; not determinable | |
197865e8 | 6966 | statically. |
800eeca4 | 6967 | 7) only access the specified resource when the corresponding mask bit is |
197865e8 | 6968 | set |
800eeca4 JW |
6969 | 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is |
6970 | only read when these insns reference FR2-31 | |
6971 | 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only | |
6972 | written when these insns write FR32-127 | |
6973 | 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the | |
6974 | instruction | |
6975 | 11) The target predicates are written independently of PR[qp], but source | |
6976 | registers are only read if PR[qp] is true. Since the state of PR[qp] | |
6977 | cannot statically be determined, all source registers are marked used. | |
6978 | 12) This insn only reads the specified predicate register when that | |
6979 | register is the PR[qp]. | |
6980 | 13) This reference to ld-c only applies to teh GR whose value is loaded | |
197865e8 | 6981 | with data returned from memory, not the post-incremented address register. |
800eeca4 JW |
6982 | 14) The RSE resource includes the implementation-specific RSE internal |
6983 | state resources. At least one (and possibly more) of these resources are | |
6984 | read by each instruction listed in IC:rse-readers. At least one (and | |
6985 | possibly more) of these resources are written by each insn listed in | |
197865e8 | 6986 | IC:rse-writers. |
800eeca4 | 6987 | 15+16) Represents reserved instructions, which the assembler does not |
197865e8 | 6988 | generate. |
800eeca4 JW |
6989 | |
6990 | Memory resources (i.e. locations in memory) are *not* marked or tracked by | |
6991 | this code; there are no dependency violations based on memory access. | |
800eeca4 JW |
6992 | */ |
6993 | ||
6994 | #define MAX_SPECS 256 | |
6995 | #define DV_CHK 1 | |
6996 | #define DV_REG 0 | |
6997 | ||
6998 | static int | |
6999 | specify_resource (dep, idesc, type, specs, note, path) | |
542d6675 KH |
7000 | const struct ia64_dependency *dep; |
7001 | struct ia64_opcode *idesc; | |
7002 | int type; /* is this a DV chk or a DV reg? */ | |
7003 | struct rsrc specs[MAX_SPECS]; /* returned specific resources */ | |
7004 | int note; /* resource note for this insn's usage */ | |
7005 | int path; /* which execution path to examine */ | |
800eeca4 JW |
7006 | { |
7007 | int count = 0; | |
7008 | int i; | |
7009 | int rsrc_write = 0; | |
7010 | struct rsrc tmpl; | |
197865e8 | 7011 | |
800eeca4 JW |
7012 | if (dep->mode == IA64_DV_WAW |
7013 | || (dep->mode == IA64_DV_RAW && type == DV_REG) | |
7014 | || (dep->mode == IA64_DV_WAR && type == DV_CHK)) | |
7015 | rsrc_write = 1; | |
7016 | ||
7017 | /* template for any resources we identify */ | |
7018 | tmpl.dependency = dep; | |
7019 | tmpl.note = note; | |
7020 | tmpl.insn_srlz = tmpl.data_srlz = 0; | |
7021 | tmpl.qp_regno = CURR_SLOT.qp_regno; | |
7022 | tmpl.link_to_qp_branch = 1; | |
7023 | tmpl.mem_offset.hint = 0; | |
7024 | tmpl.specific = 1; | |
7025 | tmpl.index = 0; | |
7484b8e6 | 7026 | tmpl.cmp_type = CMP_NONE; |
800eeca4 JW |
7027 | |
7028 | #define UNHANDLED \ | |
7029 | as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ | |
7030 | dep->name, idesc->name, (rsrc_write?"write":"read"), note) | |
7031 | #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) | |
7032 | ||
7033 | /* we don't need to track these */ | |
7034 | if (dep->semantics == IA64_DVS_NONE) | |
7035 | return 0; | |
7036 | ||
7037 | switch (dep->specifier) | |
7038 | { | |
7039 | case IA64_RS_AR_K: | |
7040 | if (note == 1) | |
542d6675 KH |
7041 | { |
7042 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7043 | { | |
7044 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7045 | if (regno >= 0 && regno <= 7) | |
7046 | { | |
7047 | specs[count] = tmpl; | |
7048 | specs[count++].index = regno; | |
7049 | } | |
7050 | } | |
7051 | } | |
800eeca4 | 7052 | else if (note == 0) |
542d6675 KH |
7053 | { |
7054 | for (i = 0; i < 8; i++) | |
7055 | { | |
7056 | specs[count] = tmpl; | |
7057 | specs[count++].index = i; | |
7058 | } | |
7059 | } | |
800eeca4 | 7060 | else |
542d6675 KH |
7061 | { |
7062 | UNHANDLED; | |
7063 | } | |
800eeca4 JW |
7064 | break; |
7065 | ||
7066 | case IA64_RS_AR_UNAT: | |
7067 | /* This is a mov =AR or mov AR= instruction. */ | |
7068 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7069 | { | |
7070 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7071 | if (regno == AR_UNAT) | |
7072 | { | |
7073 | specs[count++] = tmpl; | |
7074 | } | |
7075 | } | |
7076 | else | |
7077 | { | |
7078 | /* This is a spill/fill, or other instruction that modifies the | |
7079 | unat register. */ | |
7080 | ||
7081 | /* Unless we can determine the specific bits used, mark the whole | |
7082 | thing; bits 8:3 of the memory address indicate the bit used in | |
7083 | UNAT. The .mem.offset hint may be used to eliminate a small | |
7084 | subset of conflicts. */ | |
7085 | specs[count] = tmpl; | |
7086 | if (md.mem_offset.hint) | |
7087 | { | |
542d6675 KH |
7088 | if (md.debug_dv) |
7089 | fprintf (stderr, " Using hint for spill/fill\n"); | |
7090 | /* The index isn't actually used, just set it to something | |
7091 | approximating the bit index. */ | |
800eeca4 JW |
7092 | specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; |
7093 | specs[count].mem_offset.hint = 1; | |
7094 | specs[count].mem_offset.offset = md.mem_offset.offset; | |
7095 | specs[count++].mem_offset.base = md.mem_offset.base; | |
7096 | } | |
7097 | else | |
7098 | { | |
7099 | specs[count++].specific = 0; | |
7100 | } | |
7101 | } | |
7102 | break; | |
7103 | ||
7104 | case IA64_RS_AR: | |
7105 | if (note == 1) | |
542d6675 KH |
7106 | { |
7107 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7108 | { | |
7109 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7110 | if ((regno >= 8 && regno <= 15) | |
7111 | || (regno >= 20 && regno <= 23) | |
7112 | || (regno >= 31 && regno <= 39) | |
7113 | || (regno >= 41 && regno <= 47) | |
7114 | || (regno >= 67 && regno <= 111)) | |
7115 | { | |
7116 | specs[count] = tmpl; | |
7117 | specs[count++].index = regno; | |
7118 | } | |
7119 | } | |
7120 | } | |
800eeca4 | 7121 | else |
542d6675 KH |
7122 | { |
7123 | UNHANDLED; | |
7124 | } | |
800eeca4 JW |
7125 | break; |
7126 | ||
7127 | case IA64_RS_ARb: | |
7128 | if (note == 1) | |
542d6675 KH |
7129 | { |
7130 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7131 | { | |
7132 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7133 | if ((regno >= 48 && regno <= 63) | |
7134 | || (regno >= 112 && regno <= 127)) | |
7135 | { | |
7136 | specs[count] = tmpl; | |
7137 | specs[count++].index = regno; | |
7138 | } | |
7139 | } | |
7140 | } | |
800eeca4 | 7141 | else if (note == 0) |
542d6675 KH |
7142 | { |
7143 | for (i = 48; i < 64; i++) | |
7144 | { | |
7145 | specs[count] = tmpl; | |
7146 | specs[count++].index = i; | |
7147 | } | |
7148 | for (i = 112; i < 128; i++) | |
7149 | { | |
7150 | specs[count] = tmpl; | |
7151 | specs[count++].index = i; | |
7152 | } | |
7153 | } | |
197865e8 | 7154 | else |
542d6675 KH |
7155 | { |
7156 | UNHANDLED; | |
7157 | } | |
800eeca4 JW |
7158 | break; |
7159 | ||
7160 | case IA64_RS_BR: | |
7161 | if (note != 1) | |
542d6675 KH |
7162 | { |
7163 | UNHANDLED; | |
7164 | } | |
800eeca4 | 7165 | else |
542d6675 KH |
7166 | { |
7167 | if (rsrc_write) | |
7168 | { | |
7169 | for (i = 0; i < idesc->num_outputs; i++) | |
7170 | if (idesc->operands[i] == IA64_OPND_B1 | |
7171 | || idesc->operands[i] == IA64_OPND_B2) | |
7172 | { | |
7173 | specs[count] = tmpl; | |
7174 | specs[count++].index = | |
7175 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
7176 | } | |
7177 | } | |
7178 | else | |
7179 | { | |
7180 | for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++) | |
7181 | if (idesc->operands[i] == IA64_OPND_B1 | |
7182 | || idesc->operands[i] == IA64_OPND_B2) | |
7183 | { | |
7184 | specs[count] = tmpl; | |
7185 | specs[count++].index = | |
7186 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
7187 | } | |
7188 | } | |
7189 | } | |
800eeca4 JW |
7190 | break; |
7191 | ||
7192 | case IA64_RS_CPUID: /* four or more registers */ | |
7193 | if (note == 3) | |
542d6675 KH |
7194 | { |
7195 | if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) | |
7196 | { | |
7197 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7198 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7199 | && KNOWN (regno)) | |
7200 | { | |
7201 | specs[count] = tmpl; | |
7202 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7203 | } | |
7204 | else | |
7205 | { | |
7206 | specs[count] = tmpl; | |
7207 | specs[count++].specific = 0; | |
7208 | } | |
7209 | } | |
7210 | } | |
800eeca4 | 7211 | else |
542d6675 KH |
7212 | { |
7213 | UNHANDLED; | |
7214 | } | |
800eeca4 JW |
7215 | break; |
7216 | ||
7217 | case IA64_RS_DBR: /* four or more registers */ | |
7218 | if (note == 3) | |
542d6675 KH |
7219 | { |
7220 | if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) | |
7221 | { | |
7222 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7223 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7224 | && KNOWN (regno)) | |
7225 | { | |
7226 | specs[count] = tmpl; | |
7227 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7228 | } | |
7229 | else | |
7230 | { | |
7231 | specs[count] = tmpl; | |
7232 | specs[count++].specific = 0; | |
7233 | } | |
7234 | } | |
7235 | } | |
800eeca4 | 7236 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
7237 | { |
7238 | specs[count] = tmpl; | |
7239 | specs[count++].specific = 0; | |
7240 | } | |
800eeca4 | 7241 | else |
542d6675 KH |
7242 | { |
7243 | UNHANDLED; | |
7244 | } | |
800eeca4 JW |
7245 | break; |
7246 | ||
7247 | case IA64_RS_IBR: /* four or more registers */ | |
7248 | if (note == 3) | |
542d6675 KH |
7249 | { |
7250 | if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) | |
7251 | { | |
7252 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7253 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7254 | && KNOWN (regno)) | |
7255 | { | |
7256 | specs[count] = tmpl; | |
7257 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7258 | } | |
7259 | else | |
7260 | { | |
7261 | specs[count] = tmpl; | |
7262 | specs[count++].specific = 0; | |
7263 | } | |
7264 | } | |
7265 | } | |
800eeca4 | 7266 | else |
542d6675 KH |
7267 | { |
7268 | UNHANDLED; | |
7269 | } | |
800eeca4 JW |
7270 | break; |
7271 | ||
7272 | case IA64_RS_MSR: | |
7273 | if (note == 5) | |
7274 | { | |
7275 | /* These are implementation specific. Force all references to | |
7276 | conflict with all other references. */ | |
7277 | specs[count] = tmpl; | |
7278 | specs[count++].specific = 0; | |
7279 | } | |
7280 | else | |
7281 | { | |
7282 | UNHANDLED; | |
7283 | } | |
7284 | break; | |
7285 | ||
7286 | case IA64_RS_PKR: /* 16 or more registers */ | |
7287 | if (note == 3 || note == 4) | |
542d6675 KH |
7288 | { |
7289 | if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) | |
7290 | { | |
7291 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7292 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7293 | && KNOWN (regno)) | |
7294 | { | |
7295 | if (note == 3) | |
7296 | { | |
7297 | specs[count] = tmpl; | |
7298 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7299 | } | |
7300 | else | |
7301 | for (i = 0; i < NELEMS (gr_values); i++) | |
7302 | { | |
7303 | /* Uses all registers *except* the one in R3. */ | |
2434f565 | 7304 | if ((unsigned)i != (gr_values[regno].value & 0xFF)) |
542d6675 KH |
7305 | { |
7306 | specs[count] = tmpl; | |
7307 | specs[count++].index = i; | |
7308 | } | |
7309 | } | |
7310 | } | |
7311 | else | |
7312 | { | |
7313 | specs[count] = tmpl; | |
7314 | specs[count++].specific = 0; | |
7315 | } | |
7316 | } | |
7317 | } | |
7318 | else if (note == 0) | |
7319 | { | |
7320 | /* probe et al. */ | |
7321 | specs[count] = tmpl; | |
7322 | specs[count++].specific = 0; | |
7323 | } | |
7324 | break; | |
7325 | ||
7326 | case IA64_RS_PMC: /* four or more registers */ | |
7327 | if (note == 3) | |
7328 | { | |
7329 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 | |
7330 | || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) | |
7331 | ||
7332 | { | |
7333 | int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) | |
7334 | ? 1 : !rsrc_write); | |
7335 | int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; | |
7336 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7337 | && KNOWN (regno)) | |
7338 | { | |
7339 | specs[count] = tmpl; | |
7340 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7341 | } | |
7342 | else | |
7343 | { | |
7344 | specs[count] = tmpl; | |
7345 | specs[count++].specific = 0; | |
7346 | } | |
7347 | } | |
7348 | } | |
7349 | else | |
7350 | { | |
7351 | UNHANDLED; | |
7352 | } | |
800eeca4 JW |
7353 | break; |
7354 | ||
7355 | case IA64_RS_PMD: /* four or more registers */ | |
7356 | if (note == 3) | |
542d6675 KH |
7357 | { |
7358 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) | |
7359 | { | |
7360 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7361 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7362 | && KNOWN (regno)) | |
7363 | { | |
7364 | specs[count] = tmpl; | |
7365 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7366 | } | |
7367 | else | |
7368 | { | |
7369 | specs[count] = tmpl; | |
7370 | specs[count++].specific = 0; | |
7371 | } | |
7372 | } | |
7373 | } | |
800eeca4 | 7374 | else |
542d6675 KH |
7375 | { |
7376 | UNHANDLED; | |
7377 | } | |
800eeca4 JW |
7378 | break; |
7379 | ||
7380 | case IA64_RS_RR: /* eight registers */ | |
7381 | if (note == 6) | |
542d6675 KH |
7382 | { |
7383 | if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) | |
7384 | { | |
7385 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7386 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7387 | && KNOWN (regno)) | |
7388 | { | |
7389 | specs[count] = tmpl; | |
7390 | specs[count++].index = (gr_values[regno].value >> 61) & 0x7; | |
7391 | } | |
7392 | else | |
7393 | { | |
7394 | specs[count] = tmpl; | |
7395 | specs[count++].specific = 0; | |
7396 | } | |
7397 | } | |
7398 | } | |
800eeca4 | 7399 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
7400 | { |
7401 | specs[count] = tmpl; | |
7402 | specs[count++].specific = 0; | |
7403 | } | |
197865e8 | 7404 | else |
542d6675 KH |
7405 | { |
7406 | UNHANDLED; | |
7407 | } | |
800eeca4 JW |
7408 | break; |
7409 | ||
7410 | case IA64_RS_CR_IRR: | |
197865e8 | 7411 | if (note == 0) |
542d6675 KH |
7412 | { |
7413 | /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ | |
7414 | int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; | |
7415 | if (rsrc_write | |
7416 | && idesc->operands[1] == IA64_OPND_CR3 | |
7417 | && regno == CR_IVR) | |
7418 | { | |
7419 | for (i = 0; i < 4; i++) | |
7420 | { | |
7421 | specs[count] = tmpl; | |
7422 | specs[count++].index = CR_IRR0 + i; | |
7423 | } | |
7424 | } | |
7425 | } | |
800eeca4 | 7426 | else if (note == 1) |
542d6675 KH |
7427 | { |
7428 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7429 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
7430 | && regno >= CR_IRR0 | |
7431 | && regno <= CR_IRR3) | |
7432 | { | |
7433 | specs[count] = tmpl; | |
7434 | specs[count++].index = regno; | |
7435 | } | |
7436 | } | |
800eeca4 | 7437 | else |
542d6675 KH |
7438 | { |
7439 | UNHANDLED; | |
7440 | } | |
800eeca4 JW |
7441 | break; |
7442 | ||
7443 | case IA64_RS_CR_LRR: | |
7444 | if (note != 1) | |
542d6675 KH |
7445 | { |
7446 | UNHANDLED; | |
7447 | } | |
197865e8 | 7448 | else |
542d6675 KH |
7449 | { |
7450 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7451 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
7452 | && (regno == CR_LRR0 || regno == CR_LRR1)) | |
7453 | { | |
7454 | specs[count] = tmpl; | |
7455 | specs[count++].index = regno; | |
7456 | } | |
7457 | } | |
800eeca4 JW |
7458 | break; |
7459 | ||
7460 | case IA64_RS_CR: | |
7461 | if (note == 1) | |
542d6675 KH |
7462 | { |
7463 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
7464 | { | |
7465 | specs[count] = tmpl; | |
7466 | specs[count++].index = | |
7467 | CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7468 | } | |
7469 | } | |
800eeca4 | 7470 | else |
542d6675 KH |
7471 | { |
7472 | UNHANDLED; | |
7473 | } | |
800eeca4 JW |
7474 | break; |
7475 | ||
7476 | case IA64_RS_FR: | |
7477 | case IA64_RS_FRb: | |
7478 | if (note != 1) | |
542d6675 KH |
7479 | { |
7480 | UNHANDLED; | |
7481 | } | |
800eeca4 | 7482 | else if (rsrc_write) |
542d6675 KH |
7483 | { |
7484 | if (dep->specifier == IA64_RS_FRb | |
7485 | && idesc->operands[0] == IA64_OPND_F1) | |
7486 | { | |
7487 | specs[count] = tmpl; | |
7488 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; | |
7489 | } | |
7490 | } | |
800eeca4 | 7491 | else |
542d6675 KH |
7492 | { |
7493 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) | |
7494 | { | |
7495 | if (idesc->operands[i] == IA64_OPND_F2 | |
7496 | || idesc->operands[i] == IA64_OPND_F3 | |
7497 | || idesc->operands[i] == IA64_OPND_F4) | |
7498 | { | |
7499 | specs[count] = tmpl; | |
7500 | specs[count++].index = | |
7501 | CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7502 | } | |
7503 | } | |
7504 | } | |
800eeca4 JW |
7505 | break; |
7506 | ||
7507 | case IA64_RS_GR: | |
7508 | if (note == 13) | |
542d6675 KH |
7509 | { |
7510 | /* This reference applies only to the GR whose value is loaded with | |
7511 | data returned from memory. */ | |
7512 | specs[count] = tmpl; | |
7513 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
7514 | } | |
800eeca4 | 7515 | else if (note == 1) |
542d6675 KH |
7516 | { |
7517 | if (rsrc_write) | |
7518 | { | |
7519 | for (i = 0; i < idesc->num_outputs; i++) | |
50b81f19 JW |
7520 | if (idesc->operands[i] == IA64_OPND_R1 |
7521 | || idesc->operands[i] == IA64_OPND_R2 | |
7522 | || idesc->operands[i] == IA64_OPND_R3) | |
7523 | { | |
7524 | specs[count] = tmpl; | |
197865e8 | 7525 | specs[count++].index = |
50b81f19 JW |
7526 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
7527 | } | |
7528 | if (idesc->flags & IA64_OPCODE_POSTINC) | |
7529 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7530 | if (idesc->operands[i] == IA64_OPND_MR3) | |
7531 | { | |
7532 | specs[count] = tmpl; | |
7533 | specs[count++].index = | |
7534 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7535 | } | |
542d6675 KH |
7536 | } |
7537 | else | |
7538 | { | |
7539 | /* Look for anything that reads a GR. */ | |
7540 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7541 | { | |
7542 | if (idesc->operands[i] == IA64_OPND_MR3 | |
7543 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
7544 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
7545 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
800eeca4 | 7546 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
542d6675 KH |
7547 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
7548 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
7549 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
7550 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
7551 | || ((i >= idesc->num_outputs) | |
7552 | && (idesc->operands[i] == IA64_OPND_R1 | |
7553 | || idesc->operands[i] == IA64_OPND_R2 | |
7554 | || idesc->operands[i] == IA64_OPND_R3 | |
50b81f19 JW |
7555 | /* addl source register. */ |
7556 | || idesc->operands[i] == IA64_OPND_R3_2))) | |
542d6675 KH |
7557 | { |
7558 | specs[count] = tmpl; | |
7559 | specs[count++].index = | |
7560 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7561 | } | |
7562 | } | |
7563 | } | |
7564 | } | |
197865e8 | 7565 | else |
542d6675 KH |
7566 | { |
7567 | UNHANDLED; | |
7568 | } | |
800eeca4 JW |
7569 | break; |
7570 | ||
139368c9 JW |
7571 | /* This is the same as IA64_RS_PRr, except that the register range is |
7572 | from 1 - 15, and there are no rotating register reads/writes here. */ | |
800eeca4 JW |
7573 | case IA64_RS_PR: |
7574 | if (note == 0) | |
542d6675 | 7575 | { |
139368c9 | 7576 | for (i = 1; i < 16; i++) |
542d6675 | 7577 | { |
139368c9 JW |
7578 | specs[count] = tmpl; |
7579 | specs[count++].index = i; | |
7580 | } | |
7581 | } | |
7582 | else if (note == 7) | |
7583 | { | |
7584 | valueT mask = 0; | |
7585 | /* Mark only those registers indicated by the mask. */ | |
7586 | if (rsrc_write) | |
7587 | { | |
7588 | mask = CURR_SLOT.opnd[2].X_add_number; | |
7589 | for (i = 1; i < 16; i++) | |
7590 | if (mask & ((valueT) 1 << i)) | |
7591 | { | |
7592 | specs[count] = tmpl; | |
7593 | specs[count++].index = i; | |
7594 | } | |
7595 | } | |
7596 | else | |
7597 | { | |
7598 | UNHANDLED; | |
7599 | } | |
7600 | } | |
7601 | else if (note == 11) /* note 11 implies note 1 as well */ | |
7602 | { | |
7603 | if (rsrc_write) | |
7604 | { | |
7605 | for (i = 0; i < idesc->num_outputs; i++) | |
7606 | { | |
7607 | if (idesc->operands[i] == IA64_OPND_P1 | |
7608 | || idesc->operands[i] == IA64_OPND_P2) | |
7609 | { | |
7610 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
7611 | if (regno >= 1 && regno < 16) | |
7612 | { | |
7613 | specs[count] = tmpl; | |
7614 | specs[count++].index = regno; | |
7615 | } | |
7616 | } | |
7617 | } | |
7618 | } | |
7619 | else | |
7620 | { | |
7621 | UNHANDLED; | |
7622 | } | |
7623 | } | |
7624 | else if (note == 12) | |
7625 | { | |
7626 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) | |
7627 | { | |
7628 | specs[count] = tmpl; | |
7629 | specs[count++].index = CURR_SLOT.qp_regno; | |
7630 | } | |
7631 | } | |
7632 | else if (note == 1) | |
7633 | { | |
7634 | if (rsrc_write) | |
7635 | { | |
7636 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
7637 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
7638 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; | |
7639 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
7640 | ||
7641 | if ((idesc->operands[0] == IA64_OPND_P1 | |
7642 | || idesc->operands[0] == IA64_OPND_P2) | |
7643 | && p1 >= 1 && p1 < 16) | |
542d6675 KH |
7644 | { |
7645 | specs[count] = tmpl; | |
139368c9 JW |
7646 | specs[count].cmp_type = |
7647 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); | |
7648 | specs[count++].index = p1; | |
7649 | } | |
7650 | if ((idesc->operands[1] == IA64_OPND_P1 | |
7651 | || idesc->operands[1] == IA64_OPND_P2) | |
7652 | && p2 >= 1 && p2 < 16) | |
7653 | { | |
7654 | specs[count] = tmpl; | |
7655 | specs[count].cmp_type = | |
7656 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); | |
7657 | specs[count++].index = p2; | |
542d6675 KH |
7658 | } |
7659 | } | |
7660 | else | |
7661 | { | |
139368c9 | 7662 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
542d6675 KH |
7663 | { |
7664 | specs[count] = tmpl; | |
139368c9 JW |
7665 | specs[count++].index = CURR_SLOT.qp_regno; |
7666 | } | |
7667 | if (idesc->operands[1] == IA64_OPND_PR) | |
7668 | { | |
7669 | for (i = 1; i < 16; i++) | |
7670 | { | |
7671 | specs[count] = tmpl; | |
7672 | specs[count++].index = i; | |
7673 | } | |
542d6675 KH |
7674 | } |
7675 | } | |
7676 | } | |
139368c9 JW |
7677 | else |
7678 | { | |
7679 | UNHANDLED; | |
7680 | } | |
7681 | break; | |
7682 | ||
7683 | /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are | |
7684 | simplified cases of this. */ | |
7685 | case IA64_RS_PRr: | |
7686 | if (note == 0) | |
7687 | { | |
7688 | for (i = 16; i < 63; i++) | |
7689 | { | |
7690 | specs[count] = tmpl; | |
7691 | specs[count++].index = i; | |
7692 | } | |
7693 | } | |
800eeca4 | 7694 | else if (note == 7) |
542d6675 KH |
7695 | { |
7696 | valueT mask = 0; | |
7697 | /* Mark only those registers indicated by the mask. */ | |
7698 | if (rsrc_write | |
7699 | && idesc->operands[0] == IA64_OPND_PR) | |
7700 | { | |
7701 | mask = CURR_SLOT.opnd[2].X_add_number; | |
139368c9 JW |
7702 | if (mask & ((valueT) 1<<16)) |
7703 | for (i = 16; i < 63; i++) | |
7704 | { | |
7705 | specs[count] = tmpl; | |
7706 | specs[count++].index = i; | |
7707 | } | |
542d6675 KH |
7708 | } |
7709 | else if (rsrc_write | |
7710 | && idesc->operands[0] == IA64_OPND_PR_ROT) | |
7711 | { | |
7712 | for (i = 16; i < 63; i++) | |
7713 | { | |
7714 | specs[count] = tmpl; | |
7715 | specs[count++].index = i; | |
7716 | } | |
7717 | } | |
7718 | else | |
7719 | { | |
7720 | UNHANDLED; | |
7721 | } | |
7722 | } | |
800eeca4 | 7723 | else if (note == 11) /* note 11 implies note 1 as well */ |
542d6675 KH |
7724 | { |
7725 | if (rsrc_write) | |
7726 | { | |
7727 | for (i = 0; i < idesc->num_outputs; i++) | |
7728 | { | |
7729 | if (idesc->operands[i] == IA64_OPND_P1 | |
7730 | || idesc->operands[i] == IA64_OPND_P2) | |
7731 | { | |
7732 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
139368c9 | 7733 | if (regno >= 16 && regno < 63) |
542d6675 KH |
7734 | { |
7735 | specs[count] = tmpl; | |
7736 | specs[count++].index = regno; | |
7737 | } | |
7738 | } | |
7739 | } | |
7740 | } | |
7741 | else | |
7742 | { | |
7743 | UNHANDLED; | |
7744 | } | |
7745 | } | |
800eeca4 | 7746 | else if (note == 12) |
542d6675 | 7747 | { |
139368c9 | 7748 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
7749 | { |
7750 | specs[count] = tmpl; | |
7751 | specs[count++].index = CURR_SLOT.qp_regno; | |
7752 | } | |
7753 | } | |
800eeca4 | 7754 | else if (note == 1) |
542d6675 KH |
7755 | { |
7756 | if (rsrc_write) | |
7757 | { | |
7758 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
7759 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
7484b8e6 TW |
7760 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; |
7761 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
7762 | ||
542d6675 KH |
7763 | if ((idesc->operands[0] == IA64_OPND_P1 |
7764 | || idesc->operands[0] == IA64_OPND_P2) | |
139368c9 | 7765 | && p1 >= 16 && p1 < 63) |
542d6675 KH |
7766 | { |
7767 | specs[count] = tmpl; | |
4a4f25cf | 7768 | specs[count].cmp_type = |
7484b8e6 | 7769 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
542d6675 KH |
7770 | specs[count++].index = p1; |
7771 | } | |
7772 | if ((idesc->operands[1] == IA64_OPND_P1 | |
7773 | || idesc->operands[1] == IA64_OPND_P2) | |
139368c9 | 7774 | && p2 >= 16 && p2 < 63) |
542d6675 KH |
7775 | { |
7776 | specs[count] = tmpl; | |
4a4f25cf | 7777 | specs[count].cmp_type = |
7484b8e6 | 7778 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
542d6675 KH |
7779 | specs[count++].index = p2; |
7780 | } | |
7781 | } | |
7782 | else | |
7783 | { | |
139368c9 | 7784 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
7785 | { |
7786 | specs[count] = tmpl; | |
7787 | specs[count++].index = CURR_SLOT.qp_regno; | |
7788 | } | |
7789 | if (idesc->operands[1] == IA64_OPND_PR) | |
7790 | { | |
139368c9 | 7791 | for (i = 16; i < 63; i++) |
542d6675 KH |
7792 | { |
7793 | specs[count] = tmpl; | |
7794 | specs[count++].index = i; | |
7795 | } | |
7796 | } | |
7797 | } | |
7798 | } | |
197865e8 | 7799 | else |
542d6675 KH |
7800 | { |
7801 | UNHANDLED; | |
7802 | } | |
800eeca4 JW |
7803 | break; |
7804 | ||
7805 | case IA64_RS_PSR: | |
197865e8 | 7806 | /* Verify that the instruction is using the PSR bit indicated in |
542d6675 | 7807 | dep->regindex. */ |
800eeca4 | 7808 | if (note == 0) |
542d6675 KH |
7809 | { |
7810 | if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) | |
7811 | { | |
7812 | if (dep->regindex < 6) | |
7813 | { | |
7814 | specs[count++] = tmpl; | |
7815 | } | |
7816 | } | |
7817 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) | |
7818 | { | |
7819 | if (dep->regindex < 32 | |
7820 | || dep->regindex == 35 | |
7821 | || dep->regindex == 36 | |
7822 | || (!rsrc_write && dep->regindex == PSR_CPL)) | |
7823 | { | |
7824 | specs[count++] = tmpl; | |
7825 | } | |
7826 | } | |
7827 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) | |
7828 | { | |
7829 | if (dep->regindex < 32 | |
7830 | || dep->regindex == 35 | |
7831 | || dep->regindex == 36 | |
7832 | || (rsrc_write && dep->regindex == PSR_CPL)) | |
7833 | { | |
7834 | specs[count++] = tmpl; | |
7835 | } | |
7836 | } | |
7837 | else | |
7838 | { | |
7839 | /* Several PSR bits have very specific dependencies. */ | |
7840 | switch (dep->regindex) | |
7841 | { | |
7842 | default: | |
7843 | specs[count++] = tmpl; | |
7844 | break; | |
7845 | case PSR_IC: | |
7846 | if (rsrc_write) | |
7847 | { | |
7848 | specs[count++] = tmpl; | |
7849 | } | |
7850 | else | |
7851 | { | |
7852 | /* Only certain CR accesses use PSR.ic */ | |
7853 | if (idesc->operands[0] == IA64_OPND_CR3 | |
7854 | || idesc->operands[1] == IA64_OPND_CR3) | |
7855 | { | |
7856 | int index = | |
7857 | ((idesc->operands[0] == IA64_OPND_CR3) | |
7858 | ? 0 : 1); | |
7859 | int regno = | |
7860 | CURR_SLOT.opnd[index].X_add_number - REG_CR; | |
7861 | ||
7862 | switch (regno) | |
7863 | { | |
7864 | default: | |
7865 | break; | |
7866 | case CR_ITIR: | |
7867 | case CR_IFS: | |
7868 | case CR_IIM: | |
7869 | case CR_IIP: | |
7870 | case CR_IPSR: | |
7871 | case CR_ISR: | |
7872 | case CR_IFA: | |
7873 | case CR_IHA: | |
7874 | case CR_IIPA: | |
7875 | specs[count++] = tmpl; | |
7876 | break; | |
7877 | } | |
7878 | } | |
7879 | } | |
7880 | break; | |
7881 | case PSR_CPL: | |
7882 | if (rsrc_write) | |
7883 | { | |
7884 | specs[count++] = tmpl; | |
7885 | } | |
7886 | else | |
7887 | { | |
7888 | /* Only some AR accesses use cpl */ | |
7889 | if (idesc->operands[0] == IA64_OPND_AR3 | |
7890 | || idesc->operands[1] == IA64_OPND_AR3) | |
7891 | { | |
7892 | int index = | |
7893 | ((idesc->operands[0] == IA64_OPND_AR3) | |
7894 | ? 0 : 1); | |
7895 | int regno = | |
7896 | CURR_SLOT.opnd[index].X_add_number - REG_AR; | |
7897 | ||
7898 | if (regno == AR_ITC | |
7899 | || (index == 0 | |
7900 | && (regno == AR_ITC | |
7901 | || regno == AR_RSC | |
7902 | || (regno >= AR_K0 | |
7903 | && regno <= AR_K7)))) | |
7904 | { | |
7905 | specs[count++] = tmpl; | |
7906 | } | |
7907 | } | |
7908 | else | |
7909 | { | |
7910 | specs[count++] = tmpl; | |
7911 | } | |
7912 | break; | |
7913 | } | |
7914 | } | |
7915 | } | |
7916 | } | |
800eeca4 | 7917 | else if (note == 7) |
542d6675 KH |
7918 | { |
7919 | valueT mask = 0; | |
7920 | if (idesc->operands[0] == IA64_OPND_IMMU24) | |
7921 | { | |
7922 | mask = CURR_SLOT.opnd[0].X_add_number; | |
7923 | } | |
7924 | else | |
7925 | { | |
7926 | UNHANDLED; | |
7927 | } | |
7928 | if (mask & ((valueT) 1 << dep->regindex)) | |
7929 | { | |
7930 | specs[count++] = tmpl; | |
7931 | } | |
7932 | } | |
800eeca4 | 7933 | else if (note == 8) |
542d6675 KH |
7934 | { |
7935 | int min = dep->regindex == PSR_DFL ? 2 : 32; | |
7936 | int max = dep->regindex == PSR_DFL ? 31 : 127; | |
7937 | /* dfh is read on FR32-127; dfl is read on FR2-31 */ | |
7938 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7939 | { | |
7940 | if (idesc->operands[i] == IA64_OPND_F1 | |
7941 | || idesc->operands[i] == IA64_OPND_F2 | |
7942 | || idesc->operands[i] == IA64_OPND_F3 | |
7943 | || idesc->operands[i] == IA64_OPND_F4) | |
7944 | { | |
7945 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7946 | if (reg >= min && reg <= max) | |
7947 | { | |
7948 | specs[count++] = tmpl; | |
7949 | } | |
7950 | } | |
7951 | } | |
7952 | } | |
800eeca4 | 7953 | else if (note == 9) |
542d6675 KH |
7954 | { |
7955 | int min = dep->regindex == PSR_MFL ? 2 : 32; | |
7956 | int max = dep->regindex == PSR_MFL ? 31 : 127; | |
7957 | /* mfh is read on writes to FR32-127; mfl is read on writes to | |
7958 | FR2-31 */ | |
7959 | for (i = 0; i < idesc->num_outputs; i++) | |
7960 | { | |
7961 | if (idesc->operands[i] == IA64_OPND_F1) | |
7962 | { | |
7963 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7964 | if (reg >= min && reg <= max) | |
7965 | { | |
7966 | specs[count++] = tmpl; | |
7967 | } | |
7968 | } | |
7969 | } | |
7970 | } | |
800eeca4 | 7971 | else if (note == 10) |
542d6675 KH |
7972 | { |
7973 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7974 | { | |
7975 | if (idesc->operands[i] == IA64_OPND_R1 | |
7976 | || idesc->operands[i] == IA64_OPND_R2 | |
7977 | || idesc->operands[i] == IA64_OPND_R3) | |
7978 | { | |
7979 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7980 | if (regno >= 16 && regno <= 31) | |
7981 | { | |
7982 | specs[count++] = tmpl; | |
7983 | } | |
7984 | } | |
7985 | } | |
7986 | } | |
800eeca4 | 7987 | else |
542d6675 KH |
7988 | { |
7989 | UNHANDLED; | |
7990 | } | |
800eeca4 JW |
7991 | break; |
7992 | ||
7993 | case IA64_RS_AR_FPSR: | |
7994 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
542d6675 KH |
7995 | { |
7996 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7997 | if (regno == AR_FPSR) | |
7998 | { | |
7999 | specs[count++] = tmpl; | |
8000 | } | |
8001 | } | |
800eeca4 | 8002 | else |
542d6675 KH |
8003 | { |
8004 | specs[count++] = tmpl; | |
8005 | } | |
800eeca4 JW |
8006 | break; |
8007 | ||
197865e8 | 8008 | case IA64_RS_ARX: |
800eeca4 JW |
8009 | /* Handle all AR[REG] resources */ |
8010 | if (note == 0 || note == 1) | |
542d6675 KH |
8011 | { |
8012 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
8013 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 | |
8014 | && regno == dep->regindex) | |
8015 | { | |
8016 | specs[count++] = tmpl; | |
8017 | } | |
8018 | /* other AR[REG] resources may be affected by AR accesses */ | |
8019 | else if (idesc->operands[0] == IA64_OPND_AR3) | |
8020 | { | |
8021 | /* AR[] writes */ | |
8022 | regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; | |
8023 | switch (dep->regindex) | |
8024 | { | |
8025 | default: | |
8026 | break; | |
8027 | case AR_BSP: | |
8028 | case AR_RNAT: | |
8029 | if (regno == AR_BSPSTORE) | |
8030 | { | |
8031 | specs[count++] = tmpl; | |
8032 | } | |
8033 | case AR_RSC: | |
8034 | if (!rsrc_write && | |
8035 | (regno == AR_BSPSTORE | |
8036 | || regno == AR_RNAT)) | |
8037 | { | |
8038 | specs[count++] = tmpl; | |
8039 | } | |
8040 | break; | |
8041 | } | |
8042 | } | |
8043 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
8044 | { | |
8045 | /* AR[] reads */ | |
8046 | regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; | |
8047 | switch (dep->regindex) | |
8048 | { | |
8049 | default: | |
8050 | break; | |
8051 | case AR_RSC: | |
8052 | if (regno == AR_BSPSTORE || regno == AR_RNAT) | |
8053 | { | |
8054 | specs[count++] = tmpl; | |
8055 | } | |
8056 | break; | |
8057 | } | |
8058 | } | |
8059 | else | |
8060 | { | |
8061 | specs[count++] = tmpl; | |
8062 | } | |
8063 | } | |
800eeca4 | 8064 | else |
542d6675 KH |
8065 | { |
8066 | UNHANDLED; | |
8067 | } | |
800eeca4 JW |
8068 | break; |
8069 | ||
8070 | case IA64_RS_CRX: | |
8071 | /* Handle all CR[REG] resources */ | |
8072 | if (note == 0 || note == 1) | |
542d6675 KH |
8073 | { |
8074 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
8075 | { | |
8076 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
8077 | if (regno == dep->regindex) | |
8078 | { | |
8079 | specs[count++] = tmpl; | |
8080 | } | |
8081 | else if (!rsrc_write) | |
8082 | { | |
8083 | /* Reads from CR[IVR] affect other resources. */ | |
8084 | if (regno == CR_IVR) | |
8085 | { | |
8086 | if ((dep->regindex >= CR_IRR0 | |
8087 | && dep->regindex <= CR_IRR3) | |
8088 | || dep->regindex == CR_TPR) | |
8089 | { | |
8090 | specs[count++] = tmpl; | |
8091 | } | |
8092 | } | |
8093 | } | |
8094 | } | |
8095 | else | |
8096 | { | |
8097 | specs[count++] = tmpl; | |
8098 | } | |
8099 | } | |
800eeca4 | 8100 | else |
542d6675 KH |
8101 | { |
8102 | UNHANDLED; | |
8103 | } | |
800eeca4 JW |
8104 | break; |
8105 | ||
8106 | case IA64_RS_INSERVICE: | |
8107 | /* look for write of EOI (67) or read of IVR (65) */ | |
8108 | if ((idesc->operands[0] == IA64_OPND_CR3 | |
542d6675 KH |
8109 | && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) |
8110 | || (idesc->operands[1] == IA64_OPND_CR3 | |
8111 | && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) | |
8112 | { | |
8113 | specs[count++] = tmpl; | |
8114 | } | |
800eeca4 JW |
8115 | break; |
8116 | ||
8117 | case IA64_RS_GR0: | |
8118 | if (note == 1) | |
542d6675 KH |
8119 | { |
8120 | specs[count++] = tmpl; | |
8121 | } | |
800eeca4 | 8122 | else |
542d6675 KH |
8123 | { |
8124 | UNHANDLED; | |
8125 | } | |
800eeca4 JW |
8126 | break; |
8127 | ||
8128 | case IA64_RS_CFM: | |
8129 | if (note != 2) | |
542d6675 KH |
8130 | { |
8131 | specs[count++] = tmpl; | |
8132 | } | |
800eeca4 | 8133 | else |
542d6675 KH |
8134 | { |
8135 | /* Check if any of the registers accessed are in the rotating region. | |
8136 | mov to/from pr accesses CFM only when qp_regno is in the rotating | |
8137 | region */ | |
8138 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
8139 | { | |
8140 | if (idesc->operands[i] == IA64_OPND_R1 | |
8141 | || idesc->operands[i] == IA64_OPND_R2 | |
8142 | || idesc->operands[i] == IA64_OPND_R3) | |
8143 | { | |
8144 | int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8145 | /* Assumes that md.rot.num_regs is always valid */ | |
8146 | if (md.rot.num_regs > 0 | |
8147 | && num > 31 | |
8148 | && num < 31 + md.rot.num_regs) | |
8149 | { | |
8150 | specs[count] = tmpl; | |
8151 | specs[count++].specific = 0; | |
8152 | } | |
8153 | } | |
8154 | else if (idesc->operands[i] == IA64_OPND_F1 | |
8155 | || idesc->operands[i] == IA64_OPND_F2 | |
8156 | || idesc->operands[i] == IA64_OPND_F3 | |
8157 | || idesc->operands[i] == IA64_OPND_F4) | |
8158 | { | |
8159 | int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
8160 | if (num > 31) | |
8161 | { | |
8162 | specs[count] = tmpl; | |
8163 | specs[count++].specific = 0; | |
8164 | } | |
8165 | } | |
8166 | else if (idesc->operands[i] == IA64_OPND_P1 | |
8167 | || idesc->operands[i] == IA64_OPND_P2) | |
8168 | { | |
8169 | int num = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8170 | if (num > 15) | |
8171 | { | |
8172 | specs[count] = tmpl; | |
8173 | specs[count++].specific = 0; | |
8174 | } | |
8175 | } | |
8176 | } | |
8177 | if (CURR_SLOT.qp_regno > 15) | |
8178 | { | |
8179 | specs[count] = tmpl; | |
8180 | specs[count++].specific = 0; | |
8181 | } | |
8182 | } | |
800eeca4 JW |
8183 | break; |
8184 | ||
139368c9 JW |
8185 | /* This is the same as IA64_RS_PRr, except simplified to account for |
8186 | the fact that there is only one register. */ | |
800eeca4 JW |
8187 | case IA64_RS_PR63: |
8188 | if (note == 0) | |
542d6675 KH |
8189 | { |
8190 | specs[count++] = tmpl; | |
8191 | } | |
139368c9 JW |
8192 | else if (note == 7) |
8193 | { | |
8194 | valueT mask = 0; | |
8195 | if (idesc->operands[2] == IA64_OPND_IMM17) | |
8196 | mask = CURR_SLOT.opnd[2].X_add_number; | |
8197 | if (mask & ((valueT) 1 << 63)) | |
8198 | specs[count++] = tmpl; | |
8199 | } | |
800eeca4 | 8200 | else if (note == 11) |
542d6675 KH |
8201 | { |
8202 | if ((idesc->operands[0] == IA64_OPND_P1 | |
8203 | && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) | |
8204 | || (idesc->operands[1] == IA64_OPND_P2 | |
8205 | && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) | |
8206 | { | |
8207 | specs[count++] = tmpl; | |
8208 | } | |
8209 | } | |
800eeca4 | 8210 | else if (note == 12) |
542d6675 KH |
8211 | { |
8212 | if (CURR_SLOT.qp_regno == 63) | |
8213 | { | |
8214 | specs[count++] = tmpl; | |
8215 | } | |
8216 | } | |
800eeca4 | 8217 | else if (note == 1) |
542d6675 KH |
8218 | { |
8219 | if (rsrc_write) | |
8220 | { | |
7484b8e6 TW |
8221 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
8222 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
8223 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; | |
8224 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
8225 | ||
4a4f25cf | 8226 | if (p1 == 63 |
7484b8e6 TW |
8227 | && (idesc->operands[0] == IA64_OPND_P1 |
8228 | || idesc->operands[0] == IA64_OPND_P2)) | |
8229 | { | |
8230 | specs[count] = tmpl; | |
4a4f25cf | 8231 | specs[count++].cmp_type = |
7484b8e6 TW |
8232 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
8233 | } | |
8234 | if (p2 == 63 | |
8235 | && (idesc->operands[1] == IA64_OPND_P1 | |
8236 | || idesc->operands[1] == IA64_OPND_P2)) | |
8237 | { | |
8238 | specs[count] = tmpl; | |
4a4f25cf | 8239 | specs[count++].cmp_type = |
7484b8e6 TW |
8240 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
8241 | } | |
542d6675 KH |
8242 | } |
8243 | else | |
8244 | { | |
8245 | if (CURR_SLOT.qp_regno == 63) | |
8246 | { | |
8247 | specs[count++] = tmpl; | |
8248 | } | |
8249 | } | |
8250 | } | |
800eeca4 | 8251 | else |
542d6675 KH |
8252 | { |
8253 | UNHANDLED; | |
8254 | } | |
800eeca4 JW |
8255 | break; |
8256 | ||
8257 | case IA64_RS_RSE: | |
8258 | /* FIXME we can identify some individual RSE written resources, but RSE | |
542d6675 KH |
8259 | read resources have not yet been completely identified, so for now |
8260 | treat RSE as a single resource */ | |
800eeca4 | 8261 | if (strncmp (idesc->name, "mov", 3) == 0) |
542d6675 KH |
8262 | { |
8263 | if (rsrc_write) | |
8264 | { | |
8265 | if (idesc->operands[0] == IA64_OPND_AR3 | |
8266 | && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) | |
8267 | { | |
8268 | specs[count] = tmpl; | |
8269 | specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ | |
8270 | } | |
8271 | } | |
8272 | else | |
8273 | { | |
8274 | if (idesc->operands[0] == IA64_OPND_AR3) | |
8275 | { | |
8276 | if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE | |
8277 | || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) | |
8278 | { | |
8279 | specs[count++] = tmpl; | |
8280 | } | |
8281 | } | |
8282 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
8283 | { | |
8284 | if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP | |
8285 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE | |
8286 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) | |
8287 | { | |
8288 | specs[count++] = tmpl; | |
8289 | } | |
8290 | } | |
8291 | } | |
8292 | } | |
197865e8 | 8293 | else |
542d6675 KH |
8294 | { |
8295 | specs[count++] = tmpl; | |
8296 | } | |
800eeca4 JW |
8297 | break; |
8298 | ||
8299 | case IA64_RS_ANY: | |
8300 | /* FIXME -- do any of these need to be non-specific? */ | |
8301 | specs[count++] = tmpl; | |
8302 | break; | |
8303 | ||
8304 | default: | |
8305 | as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); | |
8306 | break; | |
8307 | } | |
8308 | ||
8309 | return count; | |
8310 | } | |
8311 | ||
8312 | /* Clear branch flags on marked resources. This breaks the link between the | |
542d6675 KH |
8313 | QP of the marking instruction and a subsequent branch on the same QP. */ |
8314 | ||
800eeca4 JW |
8315 | static void |
8316 | clear_qp_branch_flag (mask) | |
542d6675 | 8317 | valueT mask; |
800eeca4 JW |
8318 | { |
8319 | int i; | |
542d6675 | 8320 | for (i = 0; i < regdepslen; i++) |
800eeca4 | 8321 | { |
197865e8 | 8322 | valueT bit = ((valueT) 1 << regdeps[i].qp_regno); |
800eeca4 | 8323 | if ((bit & mask) != 0) |
542d6675 KH |
8324 | { |
8325 | regdeps[i].link_to_qp_branch = 0; | |
8326 | } | |
800eeca4 JW |
8327 | } |
8328 | } | |
8329 | ||
197865e8 | 8330 | /* Remove any mutexes which contain any of the PRs indicated in the mask. |
800eeca4 | 8331 | |
542d6675 KH |
8332 | Any changes to a PR clears the mutex relations which include that PR. */ |
8333 | ||
800eeca4 JW |
8334 | static void |
8335 | clear_qp_mutex (mask) | |
542d6675 | 8336 | valueT mask; |
800eeca4 JW |
8337 | { |
8338 | int i; | |
8339 | ||
8340 | i = 0; | |
8341 | while (i < qp_mutexeslen) | |
8342 | { | |
8343 | if ((qp_mutexes[i].prmask & mask) != 0) | |
542d6675 KH |
8344 | { |
8345 | if (md.debug_dv) | |
8346 | { | |
8347 | fprintf (stderr, " Clearing mutex relation"); | |
8348 | print_prmask (qp_mutexes[i].prmask); | |
8349 | fprintf (stderr, "\n"); | |
8350 | } | |
8351 | qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; | |
8352 | } | |
800eeca4 | 8353 | else |
542d6675 | 8354 | ++i; |
800eeca4 JW |
8355 | } |
8356 | } | |
8357 | ||
8358 | /* Clear implies relations which contain PRs in the given masks. | |
8359 | P1_MASK indicates the source of the implies relation, while P2_MASK | |
542d6675 KH |
8360 | indicates the implied PR. */ |
8361 | ||
800eeca4 JW |
8362 | static void |
8363 | clear_qp_implies (p1_mask, p2_mask) | |
542d6675 KH |
8364 | valueT p1_mask; |
8365 | valueT p2_mask; | |
800eeca4 JW |
8366 | { |
8367 | int i; | |
8368 | ||
8369 | i = 0; | |
8370 | while (i < qp_implieslen) | |
8371 | { | |
197865e8 | 8372 | if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 |
542d6675 KH |
8373 | || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) |
8374 | { | |
8375 | if (md.debug_dv) | |
8376 | fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", | |
8377 | qp_implies[i].p1, qp_implies[i].p2); | |
8378 | qp_implies[i] = qp_implies[--qp_implieslen]; | |
8379 | } | |
197865e8 | 8380 | else |
542d6675 | 8381 | ++i; |
800eeca4 JW |
8382 | } |
8383 | } | |
8384 | ||
542d6675 KH |
8385 | /* Add the PRs specified to the list of implied relations. */ |
8386 | ||
800eeca4 JW |
8387 | static void |
8388 | add_qp_imply (p1, p2) | |
542d6675 | 8389 | int p1, p2; |
800eeca4 JW |
8390 | { |
8391 | valueT mask; | |
8392 | valueT bit; | |
8393 | int i; | |
8394 | ||
542d6675 | 8395 | /* p0 is not meaningful here. */ |
800eeca4 JW |
8396 | if (p1 == 0 || p2 == 0) |
8397 | abort (); | |
8398 | ||
8399 | if (p1 == p2) | |
8400 | return; | |
8401 | ||
542d6675 KH |
8402 | /* If it exists already, ignore it. */ |
8403 | for (i = 0; i < qp_implieslen; i++) | |
800eeca4 | 8404 | { |
197865e8 | 8405 | if (qp_implies[i].p1 == p1 |
542d6675 KH |
8406 | && qp_implies[i].p2 == p2 |
8407 | && qp_implies[i].path == md.path | |
8408 | && !qp_implies[i].p2_branched) | |
8409 | return; | |
800eeca4 JW |
8410 | } |
8411 | ||
8412 | if (qp_implieslen == qp_impliestotlen) | |
8413 | { | |
8414 | qp_impliestotlen += 20; | |
8415 | qp_implies = (struct qp_imply *) | |
542d6675 KH |
8416 | xrealloc ((void *) qp_implies, |
8417 | qp_impliestotlen * sizeof (struct qp_imply)); | |
800eeca4 JW |
8418 | } |
8419 | if (md.debug_dv) | |
8420 | fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); | |
8421 | qp_implies[qp_implieslen].p1 = p1; | |
8422 | qp_implies[qp_implieslen].p2 = p2; | |
8423 | qp_implies[qp_implieslen].path = md.path; | |
8424 | qp_implies[qp_implieslen++].p2_branched = 0; | |
8425 | ||
8426 | /* Add in the implied transitive relations; for everything that p2 implies, | |
8427 | make p1 imply that, too; for everything that implies p1, make it imply p2 | |
197865e8 | 8428 | as well. */ |
542d6675 | 8429 | for (i = 0; i < qp_implieslen; i++) |
800eeca4 JW |
8430 | { |
8431 | if (qp_implies[i].p1 == p2) | |
542d6675 | 8432 | add_qp_imply (p1, qp_implies[i].p2); |
800eeca4 | 8433 | if (qp_implies[i].p2 == p1) |
542d6675 | 8434 | add_qp_imply (qp_implies[i].p1, p2); |
800eeca4 JW |
8435 | } |
8436 | /* Add in mutex relations implied by this implies relation; for each mutex | |
197865e8 KH |
8437 | relation containing p2, duplicate it and replace p2 with p1. */ |
8438 | bit = (valueT) 1 << p1; | |
8439 | mask = (valueT) 1 << p2; | |
542d6675 | 8440 | for (i = 0; i < qp_mutexeslen; i++) |
800eeca4 JW |
8441 | { |
8442 | if (qp_mutexes[i].prmask & mask) | |
542d6675 | 8443 | add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); |
800eeca4 JW |
8444 | } |
8445 | } | |
8446 | ||
800eeca4 JW |
8447 | /* Add the PRs specified in the mask to the mutex list; this means that only |
8448 | one of the PRs can be true at any time. PR0 should never be included in | |
8449 | the mask. */ | |
542d6675 | 8450 | |
800eeca4 JW |
8451 | static void |
8452 | add_qp_mutex (mask) | |
542d6675 | 8453 | valueT mask; |
800eeca4 JW |
8454 | { |
8455 | if (mask & 0x1) | |
8456 | abort (); | |
8457 | ||
8458 | if (qp_mutexeslen == qp_mutexestotlen) | |
8459 | { | |
8460 | qp_mutexestotlen += 20; | |
8461 | qp_mutexes = (struct qpmutex *) | |
542d6675 KH |
8462 | xrealloc ((void *) qp_mutexes, |
8463 | qp_mutexestotlen * sizeof (struct qpmutex)); | |
800eeca4 JW |
8464 | } |
8465 | if (md.debug_dv) | |
8466 | { | |
8467 | fprintf (stderr, " Registering mutex on"); | |
8468 | print_prmask (mask); | |
8469 | fprintf (stderr, "\n"); | |
8470 | } | |
8471 | qp_mutexes[qp_mutexeslen].path = md.path; | |
8472 | qp_mutexes[qp_mutexeslen++].prmask = mask; | |
8473 | } | |
8474 | ||
8475 | static void | |
8476 | clear_register_values () | |
8477 | { | |
8478 | int i; | |
8479 | if (md.debug_dv) | |
8480 | fprintf (stderr, " Clearing register values\n"); | |
542d6675 | 8481 | for (i = 1; i < NELEMS (gr_values); i++) |
800eeca4 JW |
8482 | gr_values[i].known = 0; |
8483 | } | |
8484 | ||
8485 | /* Keep track of register values/changes which affect DV tracking. | |
8486 | ||
8487 | optimization note: should add a flag to classes of insns where otherwise we | |
542d6675 | 8488 | have to examine a group of strings to identify them. */ |
800eeca4 | 8489 | |
800eeca4 JW |
8490 | static void |
8491 | note_register_values (idesc) | |
542d6675 | 8492 | struct ia64_opcode *idesc; |
800eeca4 JW |
8493 | { |
8494 | valueT qp_changemask = 0; | |
8495 | int i; | |
8496 | ||
542d6675 KH |
8497 | /* Invalidate values for registers being written to. */ |
8498 | for (i = 0; i < idesc->num_outputs; i++) | |
800eeca4 | 8499 | { |
197865e8 | 8500 | if (idesc->operands[i] == IA64_OPND_R1 |
542d6675 KH |
8501 | || idesc->operands[i] == IA64_OPND_R2 |
8502 | || idesc->operands[i] == IA64_OPND_R3) | |
8503 | { | |
8504 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8505 | if (regno > 0 && regno < NELEMS (gr_values)) | |
8506 | gr_values[regno].known = 0; | |
8507 | } | |
50b81f19 JW |
8508 | else if (idesc->operands[i] == IA64_OPND_R3_2) |
8509 | { | |
8510 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8511 | if (regno > 0 && regno < 4) | |
8512 | gr_values[regno].known = 0; | |
8513 | } | |
197865e8 | 8514 | else if (idesc->operands[i] == IA64_OPND_P1 |
542d6675 KH |
8515 | || idesc->operands[i] == IA64_OPND_P2) |
8516 | { | |
8517 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8518 | qp_changemask |= (valueT) 1 << regno; | |
8519 | } | |
800eeca4 | 8520 | else if (idesc->operands[i] == IA64_OPND_PR) |
542d6675 KH |
8521 | { |
8522 | if (idesc->operands[2] & (valueT) 0x10000) | |
8523 | qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; | |
8524 | else | |
8525 | qp_changemask = idesc->operands[2]; | |
8526 | break; | |
8527 | } | |
800eeca4 | 8528 | else if (idesc->operands[i] == IA64_OPND_PR_ROT) |
542d6675 KH |
8529 | { |
8530 | if (idesc->operands[1] & ((valueT) 1 << 43)) | |
8531 | qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; | |
8532 | else | |
8533 | qp_changemask = idesc->operands[1]; | |
8534 | qp_changemask &= ~(valueT) 0xFFFF; | |
8535 | break; | |
8536 | } | |
8537 | } | |
8538 | ||
8539 | /* Always clear qp branch flags on any PR change. */ | |
8540 | /* FIXME there may be exceptions for certain compares. */ | |
800eeca4 JW |
8541 | clear_qp_branch_flag (qp_changemask); |
8542 | ||
542d6675 | 8543 | /* Invalidate rotating registers on insns which affect RRBs in CFM. */ |
800eeca4 JW |
8544 | if (idesc->flags & IA64_OPCODE_MOD_RRBS) |
8545 | { | |
197865e8 | 8546 | qp_changemask |= ~(valueT) 0xFFFF; |
800eeca4 | 8547 | if (strcmp (idesc->name, "clrrrb.pr") != 0) |
542d6675 KH |
8548 | { |
8549 | for (i = 32; i < 32 + md.rot.num_regs; i++) | |
8550 | gr_values[i].known = 0; | |
8551 | } | |
800eeca4 JW |
8552 | clear_qp_mutex (qp_changemask); |
8553 | clear_qp_implies (qp_changemask, qp_changemask); | |
8554 | } | |
542d6675 KH |
8555 | /* After a call, all register values are undefined, except those marked |
8556 | as "safe". */ | |
800eeca4 | 8557 | else if (strncmp (idesc->name, "br.call", 6) == 0 |
542d6675 | 8558 | || strncmp (idesc->name, "brl.call", 7) == 0) |
800eeca4 | 8559 | { |
56d27c17 | 8560 | /* FIXME keep GR values which are marked as "safe_across_calls" */ |
800eeca4 JW |
8561 | clear_register_values (); |
8562 | clear_qp_mutex (~qp_safe_across_calls); | |
8563 | clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); | |
8564 | clear_qp_branch_flag (~qp_safe_across_calls); | |
8565 | } | |
e9718fe1 | 8566 | else if (is_interruption_or_rfi (idesc) |
542d6675 | 8567 | || is_taken_branch (idesc)) |
e9718fe1 TW |
8568 | { |
8569 | clear_register_values (); | |
197865e8 KH |
8570 | clear_qp_mutex (~(valueT) 0); |
8571 | clear_qp_implies (~(valueT) 0, ~(valueT) 0); | |
e9718fe1 | 8572 | } |
542d6675 | 8573 | /* Look for mutex and implies relations. */ |
197865e8 | 8574 | else if ((idesc->operands[0] == IA64_OPND_P1 |
542d6675 KH |
8575 | || idesc->operands[0] == IA64_OPND_P2) |
8576 | && (idesc->operands[1] == IA64_OPND_P1 | |
8577 | || idesc->operands[1] == IA64_OPND_P2)) | |
800eeca4 JW |
8578 | { |
8579 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
197865e8 KH |
8580 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
8581 | valueT p1mask = (valueT) 1 << p1; | |
8582 | valueT p2mask = (valueT) 1 << p2; | |
800eeca4 | 8583 | |
542d6675 | 8584 | /* If one of the PRs is PR0, we can't really do anything. */ |
800eeca4 | 8585 | if (p1 == 0 || p2 == 0) |
542d6675 KH |
8586 | { |
8587 | if (md.debug_dv) | |
8588 | fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); | |
8589 | } | |
800eeca4 | 8590 | /* In general, clear mutexes and implies which include P1 or P2, |
542d6675 | 8591 | with the following exceptions. */ |
800eeca4 | 8592 | else if (strstr (idesc->name, ".or.andcm") != NULL) |
542d6675 KH |
8593 | { |
8594 | add_qp_mutex (p1mask | p2mask); | |
8595 | clear_qp_implies (p2mask, p1mask); | |
8596 | } | |
800eeca4 | 8597 | else if (strstr (idesc->name, ".and.orcm") != NULL) |
542d6675 KH |
8598 | { |
8599 | add_qp_mutex (p1mask | p2mask); | |
8600 | clear_qp_implies (p1mask, p2mask); | |
8601 | } | |
800eeca4 | 8602 | else if (strstr (idesc->name, ".and") != NULL) |
542d6675 KH |
8603 | { |
8604 | clear_qp_implies (0, p1mask | p2mask); | |
8605 | } | |
800eeca4 | 8606 | else if (strstr (idesc->name, ".or") != NULL) |
542d6675 KH |
8607 | { |
8608 | clear_qp_mutex (p1mask | p2mask); | |
8609 | clear_qp_implies (p1mask | p2mask, 0); | |
8610 | } | |
800eeca4 | 8611 | else |
542d6675 KH |
8612 | { |
8613 | clear_qp_implies (p1mask | p2mask, p1mask | p2mask); | |
8614 | if (strstr (idesc->name, ".unc") != NULL) | |
8615 | { | |
8616 | add_qp_mutex (p1mask | p2mask); | |
8617 | if (CURR_SLOT.qp_regno != 0) | |
8618 | { | |
8619 | add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, | |
8620 | CURR_SLOT.qp_regno); | |
8621 | add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, | |
8622 | CURR_SLOT.qp_regno); | |
8623 | } | |
8624 | } | |
8625 | else if (CURR_SLOT.qp_regno == 0) | |
8626 | { | |
8627 | add_qp_mutex (p1mask | p2mask); | |
8628 | } | |
8629 | else | |
8630 | { | |
8631 | clear_qp_mutex (p1mask | p2mask); | |
8632 | } | |
8633 | } | |
8634 | } | |
8635 | /* Look for mov imm insns into GRs. */ | |
800eeca4 | 8636 | else if (idesc->operands[0] == IA64_OPND_R1 |
542d6675 KH |
8637 | && (idesc->operands[1] == IA64_OPND_IMM22 |
8638 | || idesc->operands[1] == IA64_OPND_IMMU64) | |
8639 | && (strcmp (idesc->name, "mov") == 0 | |
8640 | || strcmp (idesc->name, "movl") == 0)) | |
800eeca4 JW |
8641 | { |
8642 | int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
542d6675 KH |
8643 | if (regno > 0 && regno < NELEMS (gr_values)) |
8644 | { | |
8645 | gr_values[regno].known = 1; | |
8646 | gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; | |
8647 | gr_values[regno].path = md.path; | |
8648 | if (md.debug_dv) | |
2434f565 JW |
8649 | { |
8650 | fprintf (stderr, " Know gr%d = ", regno); | |
8651 | fprintf_vma (stderr, gr_values[regno].value); | |
8652 | fputs ("\n", stderr); | |
8653 | } | |
542d6675 | 8654 | } |
800eeca4 | 8655 | } |
197865e8 | 8656 | else |
800eeca4 JW |
8657 | { |
8658 | clear_qp_mutex (qp_changemask); | |
8659 | clear_qp_implies (qp_changemask, qp_changemask); | |
8660 | } | |
8661 | } | |
8662 | ||
542d6675 KH |
8663 | /* Return whether the given predicate registers are currently mutex. */ |
8664 | ||
800eeca4 JW |
8665 | static int |
8666 | qp_mutex (p1, p2, path) | |
542d6675 KH |
8667 | int p1; |
8668 | int p2; | |
8669 | int path; | |
800eeca4 JW |
8670 | { |
8671 | int i; | |
8672 | valueT mask; | |
8673 | ||
8674 | if (p1 != p2) | |
8675 | { | |
542d6675 KH |
8676 | mask = ((valueT) 1 << p1) | (valueT) 1 << p2; |
8677 | for (i = 0; i < qp_mutexeslen; i++) | |
8678 | { | |
8679 | if (qp_mutexes[i].path >= path | |
8680 | && (qp_mutexes[i].prmask & mask) == mask) | |
8681 | return 1; | |
8682 | } | |
800eeca4 JW |
8683 | } |
8684 | return 0; | |
8685 | } | |
8686 | ||
8687 | /* Return whether the given resource is in the given insn's list of chks | |
8688 | Return 1 if the conflict is absolutely determined, 2 if it's a potential | |
542d6675 KH |
8689 | conflict. */ |
8690 | ||
800eeca4 JW |
8691 | static int |
8692 | resources_match (rs, idesc, note, qp_regno, path) | |
542d6675 KH |
8693 | struct rsrc *rs; |
8694 | struct ia64_opcode *idesc; | |
8695 | int note; | |
8696 | int qp_regno; | |
8697 | int path; | |
800eeca4 JW |
8698 | { |
8699 | struct rsrc specs[MAX_SPECS]; | |
8700 | int count; | |
8701 | ||
8702 | /* If the marked resource's qp_regno and the given qp_regno are mutex, | |
8703 | we don't need to check. One exception is note 11, which indicates that | |
8704 | target predicates are written regardless of PR[qp]. */ | |
197865e8 | 8705 | if (qp_mutex (rs->qp_regno, qp_regno, path) |
800eeca4 JW |
8706 | && note != 11) |
8707 | return 0; | |
8708 | ||
8709 | count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); | |
8710 | while (count-- > 0) | |
8711 | { | |
8712 | /* UNAT checking is a bit more specific than other resources */ | |
8713 | if (rs->dependency->specifier == IA64_RS_AR_UNAT | |
542d6675 KH |
8714 | && specs[count].mem_offset.hint |
8715 | && rs->mem_offset.hint) | |
8716 | { | |
8717 | if (rs->mem_offset.base == specs[count].mem_offset.base) | |
8718 | { | |
8719 | if (((rs->mem_offset.offset >> 3) & 0x3F) == | |
8720 | ((specs[count].mem_offset.offset >> 3) & 0x3F)) | |
8721 | return 1; | |
8722 | else | |
8723 | continue; | |
8724 | } | |
8725 | } | |
800eeca4 | 8726 | |
7484b8e6 | 8727 | /* Skip apparent PR write conflicts where both writes are an AND or both |
4a4f25cf | 8728 | writes are an OR. */ |
7484b8e6 | 8729 | if (rs->dependency->specifier == IA64_RS_PR |
afa680f8 | 8730 | || rs->dependency->specifier == IA64_RS_PRr |
7484b8e6 TW |
8731 | || rs->dependency->specifier == IA64_RS_PR63) |
8732 | { | |
8733 | if (specs[count].cmp_type != CMP_NONE | |
8734 | && specs[count].cmp_type == rs->cmp_type) | |
8735 | { | |
8736 | if (md.debug_dv) | |
8737 | fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", | |
8738 | dv_mode[rs->dependency->mode], | |
afa680f8 | 8739 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 TW |
8740 | specs[count].index : 63); |
8741 | continue; | |
8742 | } | |
8743 | if (md.debug_dv) | |
4a4f25cf | 8744 | fprintf (stderr, |
7484b8e6 TW |
8745 | " %s on parallel compare conflict %s vs %s on PR%d\n", |
8746 | dv_mode[rs->dependency->mode], | |
4a4f25cf | 8747 | dv_cmp_type[rs->cmp_type], |
7484b8e6 | 8748 | dv_cmp_type[specs[count].cmp_type], |
afa680f8 | 8749 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 | 8750 | specs[count].index : 63); |
4a4f25cf | 8751 | |
7484b8e6 TW |
8752 | } |
8753 | ||
800eeca4 | 8754 | /* If either resource is not specific, conservatively assume a conflict |
197865e8 | 8755 | */ |
800eeca4 | 8756 | if (!specs[count].specific || !rs->specific) |
542d6675 | 8757 | return 2; |
800eeca4 | 8758 | else if (specs[count].index == rs->index) |
542d6675 | 8759 | return 1; |
800eeca4 JW |
8760 | } |
8761 | #if 0 | |
8762 | if (md.debug_dv) | |
8763 | fprintf (stderr, " No %s conflicts\n", rs->dependency->name); | |
8764 | #endif | |
8765 | ||
8766 | return 0; | |
8767 | } | |
8768 | ||
8769 | /* Indicate an instruction group break; if INSERT_STOP is non-zero, then | |
8770 | insert a stop to create the break. Update all resource dependencies | |
8771 | appropriately. If QP_REGNO is non-zero, only apply the break to resources | |
8772 | which use the same QP_REGNO and have the link_to_qp_branch flag set. | |
8773 | If SAVE_CURRENT is non-zero, don't affect resources marked by the current | |
542d6675 | 8774 | instruction. */ |
800eeca4 JW |
8775 | |
8776 | static void | |
8777 | insn_group_break (insert_stop, qp_regno, save_current) | |
542d6675 KH |
8778 | int insert_stop; |
8779 | int qp_regno; | |
8780 | int save_current; | |
800eeca4 JW |
8781 | { |
8782 | int i; | |
8783 | ||
8784 | if (insert_stop && md.num_slots_in_use > 0) | |
8785 | PREV_SLOT.end_of_insn_group = 1; | |
8786 | ||
8787 | if (md.debug_dv) | |
8788 | { | |
197865e8 | 8789 | fprintf (stderr, " Insn group break%s", |
542d6675 | 8790 | (insert_stop ? " (w/stop)" : "")); |
800eeca4 | 8791 | if (qp_regno != 0) |
542d6675 | 8792 | fprintf (stderr, " effective for QP=%d", qp_regno); |
800eeca4 JW |
8793 | fprintf (stderr, "\n"); |
8794 | } | |
8795 | ||
8796 | i = 0; | |
8797 | while (i < regdepslen) | |
8798 | { | |
8799 | const struct ia64_dependency *dep = regdeps[i].dependency; | |
8800 | ||
8801 | if (qp_regno != 0 | |
542d6675 KH |
8802 | && regdeps[i].qp_regno != qp_regno) |
8803 | { | |
8804 | ++i; | |
8805 | continue; | |
8806 | } | |
800eeca4 JW |
8807 | |
8808 | if (save_current | |
542d6675 KH |
8809 | && CURR_SLOT.src_file == regdeps[i].file |
8810 | && CURR_SLOT.src_line == regdeps[i].line) | |
8811 | { | |
8812 | ++i; | |
8813 | continue; | |
8814 | } | |
800eeca4 JW |
8815 | |
8816 | /* clear dependencies which are automatically cleared by a stop, or | |
542d6675 | 8817 | those that have reached the appropriate state of insn serialization */ |
800eeca4 | 8818 | if (dep->semantics == IA64_DVS_IMPLIED |
542d6675 KH |
8819 | || dep->semantics == IA64_DVS_IMPLIEDF |
8820 | || regdeps[i].insn_srlz == STATE_SRLZ) | |
8821 | { | |
8822 | print_dependency ("Removing", i); | |
8823 | regdeps[i] = regdeps[--regdepslen]; | |
8824 | } | |
800eeca4 | 8825 | else |
542d6675 KH |
8826 | { |
8827 | if (dep->semantics == IA64_DVS_DATA | |
8828 | || dep->semantics == IA64_DVS_INSTR | |
800eeca4 | 8829 | || dep->semantics == IA64_DVS_SPECIFIC) |
542d6675 KH |
8830 | { |
8831 | if (regdeps[i].insn_srlz == STATE_NONE) | |
8832 | regdeps[i].insn_srlz = STATE_STOP; | |
8833 | if (regdeps[i].data_srlz == STATE_NONE) | |
8834 | regdeps[i].data_srlz = STATE_STOP; | |
8835 | } | |
8836 | ++i; | |
8837 | } | |
800eeca4 JW |
8838 | } |
8839 | } | |
8840 | ||
542d6675 KH |
8841 | /* Add the given resource usage spec to the list of active dependencies. */ |
8842 | ||
197865e8 | 8843 | static void |
800eeca4 | 8844 | mark_resource (idesc, dep, spec, depind, path) |
2434f565 JW |
8845 | struct ia64_opcode *idesc ATTRIBUTE_UNUSED; |
8846 | const struct ia64_dependency *dep ATTRIBUTE_UNUSED; | |
542d6675 KH |
8847 | struct rsrc *spec; |
8848 | int depind; | |
8849 | int path; | |
800eeca4 JW |
8850 | { |
8851 | if (regdepslen == regdepstotlen) | |
8852 | { | |
8853 | regdepstotlen += 20; | |
8854 | regdeps = (struct rsrc *) | |
542d6675 | 8855 | xrealloc ((void *) regdeps, |
bc805888 | 8856 | regdepstotlen * sizeof (struct rsrc)); |
800eeca4 JW |
8857 | } |
8858 | ||
8859 | regdeps[regdepslen] = *spec; | |
8860 | regdeps[regdepslen].depind = depind; | |
8861 | regdeps[regdepslen].path = path; | |
8862 | regdeps[regdepslen].file = CURR_SLOT.src_file; | |
8863 | regdeps[regdepslen].line = CURR_SLOT.src_line; | |
8864 | ||
8865 | print_dependency ("Adding", regdepslen); | |
8866 | ||
8867 | ++regdepslen; | |
8868 | } | |
8869 | ||
8870 | static void | |
8871 | print_dependency (action, depind) | |
542d6675 KH |
8872 | const char *action; |
8873 | int depind; | |
800eeca4 JW |
8874 | { |
8875 | if (md.debug_dv) | |
8876 | { | |
197865e8 | 8877 | fprintf (stderr, " %s %s '%s'", |
542d6675 KH |
8878 | action, dv_mode[(regdeps[depind].dependency)->mode], |
8879 | (regdeps[depind].dependency)->name); | |
800eeca4 | 8880 | if (regdeps[depind].specific && regdeps[depind].index != 0) |
542d6675 | 8881 | fprintf (stderr, " (%d)", regdeps[depind].index); |
800eeca4 | 8882 | if (regdeps[depind].mem_offset.hint) |
2434f565 JW |
8883 | { |
8884 | fputs (" ", stderr); | |
8885 | fprintf_vma (stderr, regdeps[depind].mem_offset.base); | |
8886 | fputs ("+", stderr); | |
8887 | fprintf_vma (stderr, regdeps[depind].mem_offset.offset); | |
8888 | } | |
800eeca4 JW |
8889 | fprintf (stderr, "\n"); |
8890 | } | |
8891 | } | |
8892 | ||
8893 | static void | |
8894 | instruction_serialization () | |
8895 | { | |
8896 | int i; | |
8897 | if (md.debug_dv) | |
8898 | fprintf (stderr, " Instruction serialization\n"); | |
542d6675 | 8899 | for (i = 0; i < regdepslen; i++) |
800eeca4 JW |
8900 | if (regdeps[i].insn_srlz == STATE_STOP) |
8901 | regdeps[i].insn_srlz = STATE_SRLZ; | |
8902 | } | |
8903 | ||
8904 | static void | |
8905 | data_serialization () | |
8906 | { | |
8907 | int i = 0; | |
8908 | if (md.debug_dv) | |
8909 | fprintf (stderr, " Data serialization\n"); | |
8910 | while (i < regdepslen) | |
8911 | { | |
8912 | if (regdeps[i].data_srlz == STATE_STOP | |
542d6675 KH |
8913 | /* Note: as of 991210, all "other" dependencies are cleared by a |
8914 | data serialization. This might change with new tables */ | |
8915 | || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) | |
8916 | { | |
8917 | print_dependency ("Removing", i); | |
8918 | regdeps[i] = regdeps[--regdepslen]; | |
8919 | } | |
800eeca4 | 8920 | else |
542d6675 | 8921 | ++i; |
800eeca4 JW |
8922 | } |
8923 | } | |
8924 | ||
542d6675 KH |
8925 | /* Insert stops and serializations as needed to avoid DVs. */ |
8926 | ||
800eeca4 JW |
8927 | static void |
8928 | remove_marked_resource (rs) | |
542d6675 | 8929 | struct rsrc *rs; |
800eeca4 JW |
8930 | { |
8931 | switch (rs->dependency->semantics) | |
8932 | { | |
8933 | case IA64_DVS_SPECIFIC: | |
8934 | if (md.debug_dv) | |
8935 | fprintf (stderr, "Implementation-specific, assume worst case...\n"); | |
197865e8 | 8936 | /* ...fall through... */ |
800eeca4 JW |
8937 | case IA64_DVS_INSTR: |
8938 | if (md.debug_dv) | |
542d6675 | 8939 | fprintf (stderr, "Inserting instr serialization\n"); |
800eeca4 | 8940 | if (rs->insn_srlz < STATE_STOP) |
542d6675 | 8941 | insn_group_break (1, 0, 0); |
800eeca4 | 8942 | if (rs->insn_srlz < STATE_SRLZ) |
542d6675 KH |
8943 | { |
8944 | int oldqp = CURR_SLOT.qp_regno; | |
8945 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
8946 | /* Manually jam a srlz.i insn into the stream */ | |
8947 | CURR_SLOT.qp_regno = 0; | |
8948 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); | |
8949 | instruction_serialization (); | |
8950 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
8951 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
8952 | emit_one_bundle (); | |
8953 | CURR_SLOT.qp_regno = oldqp; | |
8954 | CURR_SLOT.idesc = oldidesc; | |
8955 | } | |
800eeca4 JW |
8956 | insn_group_break (1, 0, 0); |
8957 | break; | |
8958 | case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all | |
542d6675 KH |
8959 | "other" types of DV are eliminated |
8960 | by a data serialization */ | |
800eeca4 JW |
8961 | case IA64_DVS_DATA: |
8962 | if (md.debug_dv) | |
542d6675 | 8963 | fprintf (stderr, "Inserting data serialization\n"); |
800eeca4 | 8964 | if (rs->data_srlz < STATE_STOP) |
542d6675 | 8965 | insn_group_break (1, 0, 0); |
800eeca4 | 8966 | { |
542d6675 KH |
8967 | int oldqp = CURR_SLOT.qp_regno; |
8968 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
8969 | /* Manually jam a srlz.d insn into the stream */ | |
8970 | CURR_SLOT.qp_regno = 0; | |
8971 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); | |
8972 | data_serialization (); | |
8973 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
8974 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
8975 | emit_one_bundle (); | |
8976 | CURR_SLOT.qp_regno = oldqp; | |
8977 | CURR_SLOT.idesc = oldidesc; | |
800eeca4 JW |
8978 | } |
8979 | break; | |
8980 | case IA64_DVS_IMPLIED: | |
8981 | case IA64_DVS_IMPLIEDF: | |
8982 | if (md.debug_dv) | |
542d6675 | 8983 | fprintf (stderr, "Inserting stop\n"); |
800eeca4 JW |
8984 | insn_group_break (1, 0, 0); |
8985 | break; | |
8986 | default: | |
8987 | break; | |
8988 | } | |
8989 | } | |
8990 | ||
8991 | /* Check the resources used by the given opcode against the current dependency | |
197865e8 | 8992 | list. |
800eeca4 JW |
8993 | |
8994 | The check is run once for each execution path encountered. In this case, | |
8995 | a unique execution path is the sequence of instructions following a code | |
8996 | entry point, e.g. the following has three execution paths, one starting | |
8997 | at L0, one at L1, and one at L2. | |
197865e8 | 8998 | |
800eeca4 JW |
8999 | L0: nop |
9000 | L1: add | |
9001 | L2: add | |
197865e8 | 9002 | br.ret |
800eeca4 | 9003 | */ |
542d6675 | 9004 | |
800eeca4 JW |
9005 | static void |
9006 | check_dependencies (idesc) | |
542d6675 | 9007 | struct ia64_opcode *idesc; |
800eeca4 JW |
9008 | { |
9009 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
9010 | int path; | |
9011 | int i; | |
9012 | ||
9013 | /* Note that the number of marked resources may change within the | |
197865e8 | 9014 | loop if in auto mode. */ |
800eeca4 JW |
9015 | i = 0; |
9016 | while (i < regdepslen) | |
9017 | { | |
9018 | struct rsrc *rs = ®deps[i]; | |
9019 | const struct ia64_dependency *dep = rs->dependency; | |
9020 | int chkind; | |
9021 | int note; | |
9022 | int start_over = 0; | |
9023 | ||
9024 | if (dep->semantics == IA64_DVS_NONE | |
542d6675 KH |
9025 | || (chkind = depends_on (rs->depind, idesc)) == -1) |
9026 | { | |
9027 | ++i; | |
9028 | continue; | |
9029 | } | |
9030 | ||
9031 | note = NOTE (opdeps->chks[chkind]); | |
9032 | ||
9033 | /* Check this resource against each execution path seen thus far. */ | |
9034 | for (path = 0; path <= md.path; path++) | |
9035 | { | |
9036 | int matchtype; | |
9037 | ||
9038 | /* If the dependency wasn't on the path being checked, ignore it. */ | |
9039 | if (rs->path < path) | |
9040 | continue; | |
9041 | ||
9042 | /* If the QP for this insn implies a QP which has branched, don't | |
9043 | bother checking. Ed. NOTE: I don't think this check is terribly | |
9044 | useful; what's the point of generating code which will only be | |
9045 | reached if its QP is zero? | |
9046 | This code was specifically inserted to handle the following code, | |
9047 | based on notes from Intel's DV checking code, where p1 implies p2. | |
9048 | ||
9049 | mov r4 = 2 | |
9050 | (p2) br.cond L | |
9051 | (p1) mov r4 = 7 | |
9052 | */ | |
9053 | if (CURR_SLOT.qp_regno != 0) | |
9054 | { | |
9055 | int skip = 0; | |
9056 | int implies; | |
9057 | for (implies = 0; implies < qp_implieslen; implies++) | |
9058 | { | |
9059 | if (qp_implies[implies].path >= path | |
9060 | && qp_implies[implies].p1 == CURR_SLOT.qp_regno | |
9061 | && qp_implies[implies].p2_branched) | |
9062 | { | |
9063 | skip = 1; | |
9064 | break; | |
9065 | } | |
9066 | } | |
9067 | if (skip) | |
9068 | continue; | |
9069 | } | |
9070 | ||
9071 | if ((matchtype = resources_match (rs, idesc, note, | |
9072 | CURR_SLOT.qp_regno, path)) != 0) | |
9073 | { | |
9074 | char msg[1024]; | |
9075 | char pathmsg[256] = ""; | |
9076 | char indexmsg[256] = ""; | |
9077 | int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); | |
9078 | ||
9079 | if (path != 0) | |
9080 | sprintf (pathmsg, " when entry is at label '%s'", | |
9081 | md.entry_labels[path - 1]); | |
9082 | if (rs->specific && rs->index != 0) | |
9083 | sprintf (indexmsg, ", specific resource number is %d", | |
9084 | rs->index); | |
9085 | sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", | |
9086 | idesc->name, | |
9087 | (certain ? "violates" : "may violate"), | |
9088 | dv_mode[dep->mode], dep->name, | |
9089 | dv_sem[dep->semantics], | |
9090 | pathmsg, indexmsg); | |
9091 | ||
9092 | if (md.explicit_mode) | |
9093 | { | |
9094 | as_warn ("%s", msg); | |
9095 | if (path < md.path) | |
9096 | as_warn (_("Only the first path encountering the conflict " | |
9097 | "is reported")); | |
9098 | as_warn_where (rs->file, rs->line, | |
9099 | _("This is the location of the " | |
9100 | "conflicting usage")); | |
9101 | /* Don't bother checking other paths, to avoid duplicating | |
9102 | the same warning */ | |
9103 | break; | |
9104 | } | |
9105 | else | |
9106 | { | |
9107 | if (md.debug_dv) | |
9108 | fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); | |
9109 | ||
9110 | remove_marked_resource (rs); | |
9111 | ||
9112 | /* since the set of dependencies has changed, start over */ | |
9113 | /* FIXME -- since we're removing dvs as we go, we | |
9114 | probably don't really need to start over... */ | |
9115 | start_over = 1; | |
9116 | break; | |
9117 | } | |
9118 | } | |
9119 | } | |
800eeca4 | 9120 | if (start_over) |
542d6675 | 9121 | i = 0; |
800eeca4 | 9122 | else |
542d6675 | 9123 | ++i; |
800eeca4 JW |
9124 | } |
9125 | } | |
9126 | ||
542d6675 KH |
9127 | /* Register new dependencies based on the given opcode. */ |
9128 | ||
800eeca4 JW |
9129 | static void |
9130 | mark_resources (idesc) | |
542d6675 | 9131 | struct ia64_opcode *idesc; |
800eeca4 JW |
9132 | { |
9133 | int i; | |
9134 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
9135 | int add_only_qp_reads = 0; | |
9136 | ||
9137 | /* A conditional branch only uses its resources if it is taken; if it is | |
9138 | taken, we stop following that path. The other branch types effectively | |
9139 | *always* write their resources. If it's not taken, register only QP | |
197865e8 | 9140 | reads. */ |
800eeca4 JW |
9141 | if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) |
9142 | { | |
9143 | add_only_qp_reads = 1; | |
9144 | } | |
9145 | ||
9146 | if (md.debug_dv) | |
9147 | fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); | |
9148 | ||
542d6675 | 9149 | for (i = 0; i < opdeps->nregs; i++) |
800eeca4 JW |
9150 | { |
9151 | const struct ia64_dependency *dep; | |
9152 | struct rsrc specs[MAX_SPECS]; | |
9153 | int note; | |
9154 | int path; | |
9155 | int count; | |
197865e8 | 9156 | |
800eeca4 | 9157 | dep = ia64_find_dependency (opdeps->regs[i]); |
542d6675 | 9158 | note = NOTE (opdeps->regs[i]); |
800eeca4 JW |
9159 | |
9160 | if (add_only_qp_reads | |
542d6675 KH |
9161 | && !(dep->mode == IA64_DV_WAR |
9162 | && (dep->specifier == IA64_RS_PR | |
139368c9 | 9163 | || dep->specifier == IA64_RS_PRr |
542d6675 KH |
9164 | || dep->specifier == IA64_RS_PR63))) |
9165 | continue; | |
800eeca4 JW |
9166 | |
9167 | count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); | |
9168 | ||
9169 | #if 0 | |
9170 | if (md.debug_dv && !count) | |
542d6675 KH |
9171 | fprintf (stderr, " No %s %s usage found (path %d)\n", |
9172 | dv_mode[dep->mode], dep->name, md.path); | |
800eeca4 | 9173 | #endif |
197865e8 | 9174 | |
800eeca4 | 9175 | while (count-- > 0) |
542d6675 KH |
9176 | { |
9177 | mark_resource (idesc, dep, &specs[count], | |
9178 | DEP (opdeps->regs[i]), md.path); | |
9179 | } | |
800eeca4 JW |
9180 | |
9181 | /* The execution path may affect register values, which may in turn | |
542d6675 | 9182 | affect which indirect-access resources are accessed. */ |
800eeca4 | 9183 | switch (dep->specifier) |
542d6675 KH |
9184 | { |
9185 | default: | |
9186 | break; | |
9187 | case IA64_RS_CPUID: | |
9188 | case IA64_RS_DBR: | |
9189 | case IA64_RS_IBR: | |
800eeca4 | 9190 | case IA64_RS_MSR: |
542d6675 KH |
9191 | case IA64_RS_PKR: |
9192 | case IA64_RS_PMC: | |
9193 | case IA64_RS_PMD: | |
9194 | case IA64_RS_RR: | |
9195 | for (path = 0; path < md.path; path++) | |
9196 | { | |
9197 | count = specify_resource (dep, idesc, DV_REG, specs, note, path); | |
9198 | while (count-- > 0) | |
9199 | mark_resource (idesc, dep, &specs[count], | |
9200 | DEP (opdeps->regs[i]), path); | |
9201 | } | |
9202 | break; | |
9203 | } | |
9204 | } | |
9205 | } | |
9206 | ||
9207 | /* Remove dependencies when they no longer apply. */ | |
9208 | ||
800eeca4 JW |
9209 | static void |
9210 | update_dependencies (idesc) | |
542d6675 | 9211 | struct ia64_opcode *idesc; |
800eeca4 JW |
9212 | { |
9213 | int i; | |
9214 | ||
9215 | if (strcmp (idesc->name, "srlz.i") == 0) | |
9216 | { | |
9217 | instruction_serialization (); | |
9218 | } | |
9219 | else if (strcmp (idesc->name, "srlz.d") == 0) | |
9220 | { | |
9221 | data_serialization (); | |
9222 | } | |
9223 | else if (is_interruption_or_rfi (idesc) | |
542d6675 | 9224 | || is_taken_branch (idesc)) |
800eeca4 | 9225 | { |
542d6675 KH |
9226 | /* Although technically the taken branch doesn't clear dependencies |
9227 | which require a srlz.[id], we don't follow the branch; the next | |
9228 | instruction is assumed to start with a clean slate. */ | |
800eeca4 | 9229 | regdepslen = 0; |
800eeca4 JW |
9230 | md.path = 0; |
9231 | } | |
9232 | else if (is_conditional_branch (idesc) | |
542d6675 | 9233 | && CURR_SLOT.qp_regno != 0) |
800eeca4 JW |
9234 | { |
9235 | int is_call = strstr (idesc->name, ".call") != NULL; | |
9236 | ||
542d6675 KH |
9237 | for (i = 0; i < qp_implieslen; i++) |
9238 | { | |
9239 | /* If the conditional branch's predicate is implied by the predicate | |
9240 | in an existing dependency, remove that dependency. */ | |
9241 | if (qp_implies[i].p2 == CURR_SLOT.qp_regno) | |
9242 | { | |
9243 | int depind = 0; | |
9244 | /* Note that this implied predicate takes a branch so that if | |
9245 | a later insn generates a DV but its predicate implies this | |
9246 | one, we can avoid the false DV warning. */ | |
9247 | qp_implies[i].p2_branched = 1; | |
9248 | while (depind < regdepslen) | |
9249 | { | |
9250 | if (regdeps[depind].qp_regno == qp_implies[i].p1) | |
9251 | { | |
9252 | print_dependency ("Removing", depind); | |
9253 | regdeps[depind] = regdeps[--regdepslen]; | |
9254 | } | |
9255 | else | |
9256 | ++depind; | |
9257 | } | |
9258 | } | |
9259 | } | |
800eeca4 | 9260 | /* Any marked resources which have this same predicate should be |
542d6675 KH |
9261 | cleared, provided that the QP hasn't been modified between the |
9262 | marking instruction and the branch. */ | |
800eeca4 | 9263 | if (is_call) |
542d6675 KH |
9264 | { |
9265 | insn_group_break (0, CURR_SLOT.qp_regno, 1); | |
9266 | } | |
800eeca4 | 9267 | else |
542d6675 KH |
9268 | { |
9269 | i = 0; | |
9270 | while (i < regdepslen) | |
9271 | { | |
9272 | if (regdeps[i].qp_regno == CURR_SLOT.qp_regno | |
9273 | && regdeps[i].link_to_qp_branch | |
9274 | && (regdeps[i].file != CURR_SLOT.src_file | |
9275 | || regdeps[i].line != CURR_SLOT.src_line)) | |
9276 | { | |
9277 | /* Treat like a taken branch */ | |
9278 | print_dependency ("Removing", i); | |
9279 | regdeps[i] = regdeps[--regdepslen]; | |
9280 | } | |
9281 | else | |
9282 | ++i; | |
9283 | } | |
9284 | } | |
800eeca4 JW |
9285 | } |
9286 | } | |
9287 | ||
9288 | /* Examine the current instruction for dependency violations. */ | |
542d6675 | 9289 | |
800eeca4 JW |
9290 | static int |
9291 | check_dv (idesc) | |
542d6675 | 9292 | struct ia64_opcode *idesc; |
800eeca4 JW |
9293 | { |
9294 | if (md.debug_dv) | |
9295 | { | |
197865e8 | 9296 | fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", |
542d6675 KH |
9297 | idesc->name, CURR_SLOT.src_line, |
9298 | idesc->dependencies->nchks, | |
9299 | idesc->dependencies->nregs); | |
800eeca4 JW |
9300 | } |
9301 | ||
197865e8 | 9302 | /* Look through the list of currently marked resources; if the current |
800eeca4 | 9303 | instruction has the dependency in its chks list which uses that resource, |
542d6675 | 9304 | check against the specific resources used. */ |
800eeca4 JW |
9305 | check_dependencies (idesc); |
9306 | ||
542d6675 KH |
9307 | /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), |
9308 | then add them to the list of marked resources. */ | |
800eeca4 JW |
9309 | mark_resources (idesc); |
9310 | ||
9311 | /* There are several types of dependency semantics, and each has its own | |
197865e8 KH |
9312 | requirements for being cleared |
9313 | ||
800eeca4 JW |
9314 | Instruction serialization (insns separated by interruption, rfi, or |
9315 | writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. | |
9316 | ||
9317 | Data serialization (instruction serialization, or writer + srlz.d + | |
9318 | reader, where writer and srlz.d are in separate groups) clears | |
9319 | DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to | |
9320 | always be the case). | |
9321 | ||
9322 | Instruction group break (groups separated by stop, taken branch, | |
9323 | interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. | |
9324 | */ | |
9325 | update_dependencies (idesc); | |
9326 | ||
9327 | /* Sometimes, knowing a register value allows us to avoid giving a false DV | |
197865e8 | 9328 | warning. Keep track of as many as possible that are useful. */ |
800eeca4 JW |
9329 | note_register_values (idesc); |
9330 | ||
197865e8 | 9331 | /* We don't need or want this anymore. */ |
800eeca4 JW |
9332 | md.mem_offset.hint = 0; |
9333 | ||
9334 | return 0; | |
9335 | } | |
9336 | ||
9337 | /* Translate one line of assembly. Pseudo ops and labels do not show | |
9338 | here. */ | |
9339 | void | |
9340 | md_assemble (str) | |
9341 | char *str; | |
9342 | { | |
9343 | char *saved_input_line_pointer, *mnemonic; | |
9344 | const struct pseudo_opcode *pdesc; | |
9345 | struct ia64_opcode *idesc; | |
9346 | unsigned char qp_regno; | |
9347 | unsigned int flags; | |
9348 | int ch; | |
9349 | ||
9350 | saved_input_line_pointer = input_line_pointer; | |
9351 | input_line_pointer = str; | |
9352 | ||
542d6675 | 9353 | /* extract the opcode (mnemonic): */ |
800eeca4 JW |
9354 | |
9355 | mnemonic = input_line_pointer; | |
9356 | ch = get_symbol_end (); | |
9357 | pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); | |
9358 | if (pdesc) | |
9359 | { | |
9360 | *input_line_pointer = ch; | |
9361 | (*pdesc->handler) (pdesc->arg); | |
9362 | goto done; | |
9363 | } | |
9364 | ||
542d6675 | 9365 | /* Find the instruction descriptor matching the arguments. */ |
800eeca4 JW |
9366 | |
9367 | idesc = ia64_find_opcode (mnemonic); | |
9368 | *input_line_pointer = ch; | |
9369 | if (!idesc) | |
9370 | { | |
9371 | as_bad ("Unknown opcode `%s'", mnemonic); | |
9372 | goto done; | |
9373 | } | |
9374 | ||
9375 | idesc = parse_operands (idesc); | |
9376 | if (!idesc) | |
9377 | goto done; | |
9378 | ||
542d6675 | 9379 | /* Handle the dynamic ops we can handle now: */ |
800eeca4 JW |
9380 | if (idesc->type == IA64_TYPE_DYN) |
9381 | { | |
9382 | if (strcmp (idesc->name, "add") == 0) | |
9383 | { | |
9384 | if (CURR_SLOT.opnd[2].X_op == O_register | |
9385 | && CURR_SLOT.opnd[2].X_add_number < 4) | |
9386 | mnemonic = "addl"; | |
9387 | else | |
9388 | mnemonic = "adds"; | |
3d56ab85 | 9389 | ia64_free_opcode (idesc); |
800eeca4 JW |
9390 | idesc = ia64_find_opcode (mnemonic); |
9391 | #if 0 | |
9392 | know (!idesc->next); | |
9393 | #endif | |
9394 | } | |
9395 | else if (strcmp (idesc->name, "mov") == 0) | |
9396 | { | |
9397 | enum ia64_opnd opnd1, opnd2; | |
9398 | int rop; | |
9399 | ||
9400 | opnd1 = idesc->operands[0]; | |
9401 | opnd2 = idesc->operands[1]; | |
9402 | if (opnd1 == IA64_OPND_AR3) | |
9403 | rop = 0; | |
9404 | else if (opnd2 == IA64_OPND_AR3) | |
9405 | rop = 1; | |
9406 | else | |
9407 | abort (); | |
9408 | if (CURR_SLOT.opnd[rop].X_op == O_register | |
9409 | && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) | |
9410 | mnemonic = "mov.i"; | |
9411 | else | |
9412 | mnemonic = "mov.m"; | |
3d56ab85 | 9413 | ia64_free_opcode (idesc); |
800eeca4 JW |
9414 | idesc = ia64_find_opcode (mnemonic); |
9415 | while (idesc != NULL | |
9416 | && (idesc->operands[0] != opnd1 | |
9417 | || idesc->operands[1] != opnd2)) | |
9418 | idesc = get_next_opcode (idesc); | |
9419 | } | |
9420 | } | |
9421 | ||
9422 | qp_regno = 0; | |
9423 | if (md.qp.X_op == O_register) | |
f1bcba5b JW |
9424 | { |
9425 | qp_regno = md.qp.X_add_number - REG_P; | |
9426 | md.qp.X_op = O_absent; | |
9427 | } | |
800eeca4 JW |
9428 | |
9429 | flags = idesc->flags; | |
9430 | ||
9431 | if ((flags & IA64_OPCODE_FIRST) != 0) | |
9432 | insn_group_break (1, 0, 0); | |
9433 | ||
9434 | if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) | |
9435 | { | |
9436 | as_bad ("`%s' cannot be predicated", idesc->name); | |
9437 | goto done; | |
9438 | } | |
9439 | ||
542d6675 | 9440 | /* Build the instruction. */ |
800eeca4 JW |
9441 | CURR_SLOT.qp_regno = qp_regno; |
9442 | CURR_SLOT.idesc = idesc; | |
9443 | as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); | |
4dc7ead9 | 9444 | dwarf2_where (&CURR_SLOT.debug_line); |
800eeca4 JW |
9445 | |
9446 | /* Add unwind entry, if there is one. */ | |
e0c9811a | 9447 | if (unwind.current_entry) |
800eeca4 | 9448 | { |
e0c9811a JW |
9449 | CURR_SLOT.unwind_record = unwind.current_entry; |
9450 | unwind.current_entry = NULL; | |
800eeca4 JW |
9451 | } |
9452 | ||
542d6675 | 9453 | /* Check for dependency violations. */ |
800eeca4 | 9454 | if (md.detect_dv) |
542d6675 | 9455 | check_dv (idesc); |
800eeca4 JW |
9456 | |
9457 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
9458 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
9459 | emit_one_bundle (); | |
9460 | ||
9461 | if ((flags & IA64_OPCODE_LAST) != 0) | |
9462 | insn_group_break (1, 0, 0); | |
9463 | ||
9464 | md.last_text_seg = now_seg; | |
9465 | ||
9466 | done: | |
9467 | input_line_pointer = saved_input_line_pointer; | |
9468 | } | |
9469 | ||
9470 | /* Called when symbol NAME cannot be found in the symbol table. | |
9471 | Should be used for dynamic valued symbols only. */ | |
542d6675 KH |
9472 | |
9473 | symbolS * | |
800eeca4 | 9474 | md_undefined_symbol (name) |
2434f565 | 9475 | char *name ATTRIBUTE_UNUSED; |
800eeca4 JW |
9476 | { |
9477 | return 0; | |
9478 | } | |
9479 | ||
9480 | /* Called for any expression that can not be recognized. When the | |
9481 | function is called, `input_line_pointer' will point to the start of | |
9482 | the expression. */ | |
542d6675 | 9483 | |
800eeca4 JW |
9484 | void |
9485 | md_operand (e) | |
9486 | expressionS *e; | |
9487 | { | |
9488 | enum pseudo_type pseudo_type; | |
e0c9811a | 9489 | const char *name; |
800eeca4 JW |
9490 | size_t len; |
9491 | int ch, i; | |
9492 | ||
9493 | switch (*input_line_pointer) | |
9494 | { | |
9495 | case '@': | |
542d6675 | 9496 | /* Find what relocation pseudo-function we're dealing with. */ |
800eeca4 JW |
9497 | pseudo_type = 0; |
9498 | ch = *++input_line_pointer; | |
9499 | for (i = 0; i < NELEMS (pseudo_func); ++i) | |
9500 | if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) | |
9501 | { | |
9502 | len = strlen (pseudo_func[i].name); | |
9503 | if (strncmp (pseudo_func[i].name + 1, | |
9504 | input_line_pointer + 1, len - 1) == 0 | |
9505 | && !is_part_of_name (input_line_pointer[len])) | |
9506 | { | |
9507 | input_line_pointer += len; | |
9508 | pseudo_type = pseudo_func[i].type; | |
9509 | break; | |
9510 | } | |
9511 | } | |
9512 | switch (pseudo_type) | |
9513 | { | |
9514 | case PSEUDO_FUNC_RELOC: | |
9515 | SKIP_WHITESPACE (); | |
9516 | if (*input_line_pointer != '(') | |
9517 | { | |
9518 | as_bad ("Expected '('"); | |
9519 | goto err; | |
9520 | } | |
542d6675 KH |
9521 | /* Skip '('. */ |
9522 | ++input_line_pointer; | |
800eeca4 JW |
9523 | expression (e); |
9524 | if (*input_line_pointer++ != ')') | |
9525 | { | |
9526 | as_bad ("Missing ')'"); | |
9527 | goto err; | |
9528 | } | |
9529 | if (e->X_op != O_symbol) | |
9530 | { | |
9531 | if (e->X_op != O_pseudo_fixup) | |
9532 | { | |
9533 | as_bad ("Not a symbolic expression"); | |
9534 | goto err; | |
9535 | } | |
9536 | if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE | |
9537 | && i == FUNC_LT_RELATIVE) | |
9538 | i = FUNC_LT_FPTR_RELATIVE; | |
9539 | else | |
9540 | { | |
9541 | as_bad ("Illegal combination of relocation functions"); | |
9542 | goto err; | |
9543 | } | |
9544 | } | |
542d6675 KH |
9545 | /* Make sure gas doesn't get rid of local symbols that are used |
9546 | in relocs. */ | |
800eeca4 JW |
9547 | e->X_op = O_pseudo_fixup; |
9548 | e->X_op_symbol = pseudo_func[i].u.sym; | |
9549 | break; | |
9550 | ||
9551 | case PSEUDO_FUNC_CONST: | |
9552 | e->X_op = O_constant; | |
9553 | e->X_add_number = pseudo_func[i].u.ival; | |
9554 | break; | |
9555 | ||
e0c9811a JW |
9556 | case PSEUDO_FUNC_REG: |
9557 | e->X_op = O_register; | |
9558 | e->X_add_number = pseudo_func[i].u.ival; | |
9559 | break; | |
9560 | ||
800eeca4 | 9561 | default: |
e0c9811a JW |
9562 | name = input_line_pointer - 1; |
9563 | get_symbol_end (); | |
9564 | as_bad ("Unknown pseudo function `%s'", name); | |
800eeca4 JW |
9565 | goto err; |
9566 | } | |
9567 | break; | |
9568 | ||
9569 | case '[': | |
9570 | ++input_line_pointer; | |
9571 | expression (e); | |
9572 | if (*input_line_pointer != ']') | |
9573 | { | |
9574 | as_bad ("Closing bracket misssing"); | |
9575 | goto err; | |
9576 | } | |
9577 | else | |
9578 | { | |
9579 | if (e->X_op != O_register) | |
9580 | as_bad ("Register expected as index"); | |
9581 | ||
9582 | ++input_line_pointer; | |
9583 | e->X_op = O_index; | |
9584 | } | |
9585 | break; | |
9586 | ||
9587 | default: | |
9588 | break; | |
9589 | } | |
9590 | return; | |
9591 | ||
9592 | err: | |
9593 | ignore_rest_of_line (); | |
9594 | } | |
9595 | ||
9596 | /* Return 1 if it's OK to adjust a reloc by replacing the symbol with | |
9597 | a section symbol plus some offset. For relocs involving @fptr(), | |
9598 | directives we don't want such adjustments since we need to have the | |
9599 | original symbol's name in the reloc. */ | |
9600 | int | |
9601 | ia64_fix_adjustable (fix) | |
9602 | fixS *fix; | |
9603 | { | |
9604 | /* Prevent all adjustments to global symbols */ | |
9605 | if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) | |
9606 | return 0; | |
9607 | ||
9608 | switch (fix->fx_r_type) | |
9609 | { | |
9610 | case BFD_RELOC_IA64_FPTR64I: | |
9611 | case BFD_RELOC_IA64_FPTR32MSB: | |
9612 | case BFD_RELOC_IA64_FPTR32LSB: | |
9613 | case BFD_RELOC_IA64_FPTR64MSB: | |
9614 | case BFD_RELOC_IA64_FPTR64LSB: | |
9615 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9616 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9617 | return 0; | |
9618 | default: | |
9619 | break; | |
9620 | } | |
9621 | ||
9622 | return 1; | |
9623 | } | |
9624 | ||
9625 | int | |
9626 | ia64_force_relocation (fix) | |
9627 | fixS *fix; | |
9628 | { | |
9629 | switch (fix->fx_r_type) | |
9630 | { | |
9631 | case BFD_RELOC_IA64_FPTR64I: | |
9632 | case BFD_RELOC_IA64_FPTR32MSB: | |
9633 | case BFD_RELOC_IA64_FPTR32LSB: | |
9634 | case BFD_RELOC_IA64_FPTR64MSB: | |
9635 | case BFD_RELOC_IA64_FPTR64LSB: | |
9636 | ||
9637 | case BFD_RELOC_IA64_LTOFF22: | |
9638 | case BFD_RELOC_IA64_LTOFF64I: | |
9639 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9640 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9641 | case BFD_RELOC_IA64_PLTOFF22: | |
9642 | case BFD_RELOC_IA64_PLTOFF64I: | |
9643 | case BFD_RELOC_IA64_PLTOFF64MSB: | |
9644 | case BFD_RELOC_IA64_PLTOFF64LSB: | |
9645 | return 1; | |
9646 | ||
9647 | default: | |
9648 | return 0; | |
9649 | } | |
9650 | return 0; | |
9651 | } | |
9652 | ||
9653 | /* Decide from what point a pc-relative relocation is relative to, | |
9654 | relative to the pc-relative fixup. Er, relatively speaking. */ | |
9655 | long | |
9656 | ia64_pcrel_from_section (fix, sec) | |
9657 | fixS *fix; | |
9658 | segT sec; | |
9659 | { | |
9660 | unsigned long off = fix->fx_frag->fr_address + fix->fx_where; | |
197865e8 | 9661 | |
800eeca4 JW |
9662 | if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) |
9663 | off &= ~0xfUL; | |
9664 | ||
9665 | return off; | |
9666 | } | |
9667 | ||
9668 | /* This is called whenever some data item (not an instruction) needs a | |
9669 | fixup. We pick the right reloc code depending on the byteorder | |
9670 | currently in effect. */ | |
9671 | void | |
9672 | ia64_cons_fix_new (f, where, nbytes, exp) | |
9673 | fragS *f; | |
9674 | int where; | |
9675 | int nbytes; | |
9676 | expressionS *exp; | |
9677 | { | |
9678 | bfd_reloc_code_real_type code; | |
9679 | fixS *fix; | |
9680 | ||
9681 | switch (nbytes) | |
9682 | { | |
9683 | /* There are no reloc for 8 and 16 bit quantities, but we allow | |
9684 | them here since they will work fine as long as the expression | |
9685 | is fully defined at the end of the pass over the source file. */ | |
9686 | case 1: code = BFD_RELOC_8; break; | |
9687 | case 2: code = BFD_RELOC_16; break; | |
9688 | case 4: | |
9689 | if (target_big_endian) | |
9690 | code = BFD_RELOC_IA64_DIR32MSB; | |
9691 | else | |
9692 | code = BFD_RELOC_IA64_DIR32LSB; | |
9693 | break; | |
9694 | ||
9695 | case 8: | |
9696 | if (target_big_endian) | |
9697 | code = BFD_RELOC_IA64_DIR64MSB; | |
9698 | else | |
9699 | code = BFD_RELOC_IA64_DIR64LSB; | |
9700 | break; | |
9701 | ||
9702 | default: | |
9703 | as_bad ("Unsupported fixup size %d", nbytes); | |
9704 | ignore_rest_of_line (); | |
9705 | return; | |
9706 | } | |
9707 | if (exp->X_op == O_pseudo_fixup) | |
9708 | { | |
9709 | /* ??? */ | |
9710 | exp->X_op = O_symbol; | |
9711 | code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); | |
9712 | } | |
9713 | fix = fix_new_exp (f, where, nbytes, exp, 0, code); | |
9714 | /* We need to store the byte order in effect in case we're going | |
9715 | to fix an 8 or 16 bit relocation (for which there no real | |
9716 | relocs available). See md_apply_fix(). */ | |
9717 | fix->tc_fix_data.bigendian = target_big_endian; | |
9718 | } | |
9719 | ||
9720 | /* Return the actual relocation we wish to associate with the pseudo | |
9721 | reloc described by SYM and R_TYPE. SYM should be one of the | |
197865e8 | 9722 | symbols in the pseudo_func array, or NULL. */ |
800eeca4 JW |
9723 | |
9724 | static bfd_reloc_code_real_type | |
9725 | ia64_gen_real_reloc_type (sym, r_type) | |
9726 | struct symbol *sym; | |
9727 | bfd_reloc_code_real_type r_type; | |
9728 | { | |
9729 | bfd_reloc_code_real_type new = 0; | |
9730 | ||
9731 | if (sym == NULL) | |
9732 | { | |
9733 | return r_type; | |
9734 | } | |
9735 | ||
9736 | switch (S_GET_VALUE (sym)) | |
9737 | { | |
9738 | case FUNC_FPTR_RELATIVE: | |
9739 | switch (r_type) | |
9740 | { | |
9741 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; | |
9742 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; | |
9743 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; | |
9744 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; | |
9745 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; | |
9746 | default: break; | |
9747 | } | |
9748 | break; | |
9749 | ||
9750 | case FUNC_GP_RELATIVE: | |
9751 | switch (r_type) | |
9752 | { | |
9753 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; | |
9754 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; | |
9755 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; | |
9756 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; | |
9757 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; | |
9758 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; | |
9759 | default: break; | |
9760 | } | |
9761 | break; | |
9762 | ||
9763 | case FUNC_LT_RELATIVE: | |
9764 | switch (r_type) | |
9765 | { | |
9766 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; | |
9767 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; | |
9768 | default: break; | |
9769 | } | |
9770 | break; | |
9771 | ||
c67e42c9 RH |
9772 | case FUNC_PC_RELATIVE: |
9773 | switch (r_type) | |
9774 | { | |
9775 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; | |
9776 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; | |
9777 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; | |
9778 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; | |
9779 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; | |
9780 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; | |
9781 | default: break; | |
9782 | } | |
9783 | break; | |
9784 | ||
800eeca4 JW |
9785 | case FUNC_PLT_RELATIVE: |
9786 | switch (r_type) | |
9787 | { | |
9788 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; | |
9789 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; | |
9790 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; | |
9791 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; | |
9792 | default: break; | |
9793 | } | |
9794 | break; | |
9795 | ||
9796 | case FUNC_SEC_RELATIVE: | |
9797 | switch (r_type) | |
9798 | { | |
9799 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; | |
9800 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; | |
9801 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; | |
9802 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; | |
9803 | default: break; | |
9804 | } | |
9805 | break; | |
9806 | ||
9807 | case FUNC_SEG_RELATIVE: | |
9808 | switch (r_type) | |
9809 | { | |
9810 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; | |
9811 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; | |
9812 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; | |
9813 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; | |
9814 | default: break; | |
9815 | } | |
9816 | break; | |
9817 | ||
9818 | case FUNC_LTV_RELATIVE: | |
9819 | switch (r_type) | |
9820 | { | |
9821 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; | |
9822 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; | |
9823 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; | |
9824 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; | |
9825 | default: break; | |
9826 | } | |
9827 | break; | |
9828 | ||
9829 | case FUNC_LT_FPTR_RELATIVE: | |
9830 | switch (r_type) | |
9831 | { | |
9832 | case BFD_RELOC_IA64_IMM22: | |
9833 | new = BFD_RELOC_IA64_LTOFF_FPTR22; break; | |
9834 | case BFD_RELOC_IA64_IMM64: | |
9835 | new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; | |
9836 | default: | |
9837 | break; | |
9838 | } | |
9839 | break; | |
9840 | default: | |
9841 | abort (); | |
9842 | } | |
9843 | /* Hmmmm. Should this ever occur? */ | |
9844 | if (new) | |
9845 | return new; | |
9846 | else | |
9847 | return r_type; | |
9848 | } | |
9849 | ||
9850 | /* Here is where generate the appropriate reloc for pseudo relocation | |
9851 | functions. */ | |
9852 | void | |
9853 | ia64_validate_fix (fix) | |
9854 | fixS *fix; | |
9855 | { | |
9856 | switch (fix->fx_r_type) | |
9857 | { | |
9858 | case BFD_RELOC_IA64_FPTR64I: | |
9859 | case BFD_RELOC_IA64_FPTR32MSB: | |
9860 | case BFD_RELOC_IA64_FPTR64LSB: | |
9861 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9862 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9863 | if (fix->fx_offset != 0) | |
9864 | as_bad_where (fix->fx_file, fix->fx_line, | |
9865 | "No addend allowed in @fptr() relocation"); | |
9866 | break; | |
9867 | default: | |
9868 | break; | |
9869 | } | |
9870 | ||
9871 | return; | |
9872 | } | |
9873 | ||
9874 | static void | |
9875 | fix_insn (fix, odesc, value) | |
9876 | fixS *fix; | |
9877 | const struct ia64_operand *odesc; | |
9878 | valueT value; | |
9879 | { | |
9880 | bfd_vma insn[3], t0, t1, control_bits; | |
9881 | const char *err; | |
9882 | char *fixpos; | |
9883 | long slot; | |
9884 | ||
9885 | slot = fix->fx_where & 0x3; | |
9886 | fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); | |
9887 | ||
c67e42c9 | 9888 | /* Bundles are always in little-endian byte order */ |
800eeca4 JW |
9889 | t0 = bfd_getl64 (fixpos); |
9890 | t1 = bfd_getl64 (fixpos + 8); | |
9891 | control_bits = t0 & 0x1f; | |
9892 | insn[0] = (t0 >> 5) & 0x1ffffffffffLL; | |
9893 | insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); | |
9894 | insn[2] = (t1 >> 23) & 0x1ffffffffffLL; | |
9895 | ||
c67e42c9 RH |
9896 | err = NULL; |
9897 | if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) | |
800eeca4 | 9898 | { |
c67e42c9 RH |
9899 | insn[1] = (value >> 22) & 0x1ffffffffffLL; |
9900 | insn[2] |= (((value & 0x7f) << 13) | |
9901 | | (((value >> 7) & 0x1ff) << 27) | |
9902 | | (((value >> 16) & 0x1f) << 22) | |
9903 | | (((value >> 21) & 0x1) << 21) | |
9904 | | (((value >> 63) & 0x1) << 36)); | |
800eeca4 | 9905 | } |
c67e42c9 RH |
9906 | else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) |
9907 | { | |
9908 | if (value & ~0x3fffffffffffffffULL) | |
9909 | err = "integer operand out of range"; | |
9910 | insn[1] = (value >> 21) & 0x1ffffffffffLL; | |
9911 | insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); | |
9912 | } | |
9913 | else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) | |
9914 | { | |
9915 | value >>= 4; | |
9916 | insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; | |
9917 | insn[2] |= ((((value >> 59) & 0x1) << 36) | |
9918 | | (((value >> 0) & 0xfffff) << 13)); | |
9919 | } | |
9920 | else | |
9921 | err = (*odesc->insert) (odesc, value, insn + slot); | |
9922 | ||
9923 | if (err) | |
9924 | as_bad_where (fix->fx_file, fix->fx_line, err); | |
800eeca4 JW |
9925 | |
9926 | t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); | |
9927 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
44f5c83a JW |
9928 | number_to_chars_littleendian (fixpos + 0, t0, 8); |
9929 | number_to_chars_littleendian (fixpos + 8, t1, 8); | |
800eeca4 JW |
9930 | } |
9931 | ||
9932 | /* Attempt to simplify or even eliminate a fixup. The return value is | |
9933 | ignored; perhaps it was once meaningful, but now it is historical. | |
9934 | To indicate that a fixup has been eliminated, set FIXP->FX_DONE. | |
9935 | ||
9936 | If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry | |
197865e8 | 9937 | (if possible). */ |
800eeca4 JW |
9938 | int |
9939 | md_apply_fix3 (fix, valuep, seg) | |
9940 | fixS *fix; | |
9941 | valueT *valuep; | |
2434f565 | 9942 | segT seg ATTRIBUTE_UNUSED; |
800eeca4 JW |
9943 | { |
9944 | char *fixpos; | |
9945 | valueT value = *valuep; | |
9946 | int adjust = 0; | |
9947 | ||
9948 | fixpos = fix->fx_frag->fr_literal + fix->fx_where; | |
9949 | ||
9950 | if (fix->fx_pcrel) | |
9951 | { | |
9952 | switch (fix->fx_r_type) | |
9953 | { | |
9954 | case BFD_RELOC_IA64_DIR32MSB: | |
9955 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; | |
9956 | adjust = 1; | |
9957 | break; | |
9958 | ||
9959 | case BFD_RELOC_IA64_DIR32LSB: | |
9960 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; | |
9961 | adjust = 1; | |
9962 | break; | |
9963 | ||
9964 | case BFD_RELOC_IA64_DIR64MSB: | |
9965 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; | |
9966 | adjust = 1; | |
9967 | break; | |
9968 | ||
9969 | case BFD_RELOC_IA64_DIR64LSB: | |
9970 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; | |
9971 | adjust = 1; | |
9972 | break; | |
9973 | ||
9974 | default: | |
9975 | break; | |
9976 | } | |
9977 | } | |
9978 | if (fix->fx_addsy) | |
9979 | { | |
fa1cb89c | 9980 | if (fix->fx_r_type == (int) BFD_RELOC_UNUSED) |
800eeca4 | 9981 | { |
fa1cb89c JW |
9982 | /* This must be a TAG13 or TAG13b operand. There are no external |
9983 | relocs defined for them, so we must give an error. */ | |
800eeca4 JW |
9984 | as_bad_where (fix->fx_file, fix->fx_line, |
9985 | "%s must have a constant value", | |
9986 | elf64_ia64_operands[fix->tc_fix_data.opnd].desc); | |
fa1cb89c JW |
9987 | fix->fx_done = 1; |
9988 | return 1; | |
800eeca4 JW |
9989 | } |
9990 | ||
9991 | /* ??? This is a hack copied from tc-i386.c to make PCREL relocs | |
542d6675 | 9992 | work. There should be a better way to handle this. */ |
800eeca4 JW |
9993 | if (adjust) |
9994 | fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; | |
9995 | } | |
9996 | else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) | |
9997 | { | |
9998 | if (fix->tc_fix_data.bigendian) | |
9999 | number_to_chars_bigendian (fixpos, value, fix->fx_size); | |
10000 | else | |
10001 | number_to_chars_littleendian (fixpos, value, fix->fx_size); | |
10002 | fix->fx_done = 1; | |
10003 | return 1; | |
10004 | } | |
10005 | else | |
10006 | { | |
10007 | fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); | |
10008 | fix->fx_done = 1; | |
10009 | return 1; | |
10010 | } | |
10011 | return 1; | |
10012 | } | |
10013 | ||
10014 | /* Generate the BFD reloc to be stuck in the object file from the | |
10015 | fixup used internally in the assembler. */ | |
542d6675 KH |
10016 | |
10017 | arelent * | |
800eeca4 | 10018 | tc_gen_reloc (sec, fixp) |
2434f565 | 10019 | asection *sec ATTRIBUTE_UNUSED; |
800eeca4 JW |
10020 | fixS *fixp; |
10021 | { | |
10022 | arelent *reloc; | |
10023 | ||
10024 | reloc = xmalloc (sizeof (*reloc)); | |
10025 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
10026 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
10027 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10028 | reloc->addend = fixp->fx_offset; | |
10029 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
10030 | ||
10031 | if (!reloc->howto) | |
10032 | { | |
10033 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10034 | "Cannot represent %s relocation in object file", | |
10035 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
10036 | } | |
10037 | return reloc; | |
10038 | } | |
10039 | ||
10040 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10041 | of type TYPE, and store the appropriate bytes in *LIT. The number |
10042 | of LITTLENUMS emitted is stored in *SIZE. An error message is | |
800eeca4 JW |
10043 | returned, or NULL on OK. */ |
10044 | ||
10045 | #define MAX_LITTLENUMS 5 | |
10046 | ||
542d6675 | 10047 | char * |
800eeca4 JW |
10048 | md_atof (type, lit, size) |
10049 | int type; | |
10050 | char *lit; | |
10051 | int *size; | |
10052 | { | |
10053 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
10054 | LITTLENUM_TYPE *word; | |
10055 | char *t; | |
10056 | int prec; | |
10057 | ||
10058 | switch (type) | |
10059 | { | |
10060 | /* IEEE floats */ | |
10061 | case 'f': | |
10062 | case 'F': | |
10063 | case 's': | |
10064 | case 'S': | |
10065 | prec = 2; | |
10066 | break; | |
10067 | ||
10068 | case 'd': | |
10069 | case 'D': | |
10070 | case 'r': | |
10071 | case 'R': | |
10072 | prec = 4; | |
10073 | break; | |
10074 | ||
10075 | case 'x': | |
10076 | case 'X': | |
10077 | case 'p': | |
10078 | case 'P': | |
10079 | prec = 5; | |
10080 | break; | |
10081 | ||
10082 | default: | |
10083 | *size = 0; | |
10084 | return "Bad call to MD_ATOF()"; | |
10085 | } | |
10086 | t = atof_ieee (input_line_pointer, type, words); | |
10087 | if (t) | |
10088 | input_line_pointer = t; | |
10089 | *size = prec * sizeof (LITTLENUM_TYPE); | |
10090 | ||
10091 | for (word = words + prec - 1; prec--;) | |
10092 | { | |
10093 | md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); | |
10094 | lit += sizeof (LITTLENUM_TYPE); | |
10095 | } | |
10096 | return 0; | |
10097 | } | |
10098 | ||
10099 | /* Round up a section's size to the appropriate boundary. */ | |
10100 | valueT | |
10101 | md_section_align (seg, size) | |
10102 | segT seg; | |
10103 | valueT size; | |
10104 | { | |
10105 | int align = bfd_get_section_alignment (stdoutput, seg); | |
197865e8 | 10106 | valueT mask = ((valueT) 1 << align) - 1; |
800eeca4 JW |
10107 | |
10108 | return (size + mask) & ~mask; | |
10109 | } | |
10110 | ||
10111 | /* Handle ia64 specific semantics of the align directive. */ | |
10112 | ||
0a9ef439 | 10113 | void |
800eeca4 | 10114 | ia64_md_do_align (n, fill, len, max) |
91a2ae2a RH |
10115 | int n ATTRIBUTE_UNUSED; |
10116 | const char *fill ATTRIBUTE_UNUSED; | |
2434f565 | 10117 | int len ATTRIBUTE_UNUSED; |
91a2ae2a | 10118 | int max ATTRIBUTE_UNUSED; |
800eeca4 | 10119 | { |
0a9ef439 | 10120 | if (subseg_text_p (now_seg)) |
800eeca4 | 10121 | ia64_flush_insns (); |
0a9ef439 | 10122 | } |
800eeca4 | 10123 | |
0a9ef439 RH |
10124 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
10125 | of an rs_align_code fragment. */ | |
800eeca4 | 10126 | |
0a9ef439 RH |
10127 | void |
10128 | ia64_handle_align (fragp) | |
10129 | fragS *fragp; | |
10130 | { | |
10131 | /* Use mfi bundle of nops with no stop bits. */ | |
10132 | static const unsigned char be_nop[] | |
10133 | = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, | |
10134 | 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; | |
10135 | static const unsigned char le_nop[] | |
10136 | = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, | |
10137 | 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; | |
10138 | ||
10139 | int bytes; | |
10140 | char *p; | |
10141 | ||
10142 | if (fragp->fr_type != rs_align_code) | |
10143 | return; | |
10144 | ||
10145 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
10146 | p = fragp->fr_literal + fragp->fr_fix; | |
10147 | ||
10148 | /* Make sure we are on a 16-byte boundary, in case someone has been | |
10149 | putting data into a text section. */ | |
10150 | if (bytes & 15) | |
10151 | { | |
10152 | int fix = bytes & 15; | |
10153 | memset (p, 0, fix); | |
10154 | p += fix; | |
10155 | bytes -= fix; | |
10156 | fragp->fr_fix += fix; | |
800eeca4 JW |
10157 | } |
10158 | ||
0a9ef439 RH |
10159 | memcpy (p, (target_big_endian ? be_nop : le_nop), 16); |
10160 | fragp->fr_var = 16; | |
800eeca4 | 10161 | } |