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800eeca4 | 1 | /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. |
e0c9811a | 2 | Copyright (C) 1998, 1999, 2000 Free Software Foundation. |
800eeca4 JW |
3 | Contributed by David Mosberger-Tang <davidm@hpl.hp.com> |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | /* | |
23 | TODO: | |
24 | ||
25 | - optional operands | |
26 | - directives: | |
27 | .alias | |
28 | .eb | |
29 | .estate | |
30 | .lb | |
31 | .popsection | |
32 | .previous | |
33 | .psr | |
34 | .pushsection | |
800eeca4 JW |
35 | - labels are wrong if automatic alignment is introduced |
36 | (e.g., checkout the second real10 definition in test-data.s) | |
37 | - DV-related stuff: | |
542d6675 KH |
38 | <reg>.safe_across_calls and any other DV-related directives I don't |
39 | have documentation for. | |
40 | verify mod-sched-brs reads/writes are checked/marked (and other | |
41 | notes) | |
800eeca4 JW |
42 | |
43 | */ | |
44 | ||
45 | #include "as.h" | |
46 | #include "dwarf2dbg.h" | |
47 | #include "subsegs.h" | |
48 | ||
49 | #include "opcode/ia64.h" | |
50 | ||
51 | #include "elf/ia64.h" | |
52 | ||
53 | #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) | |
54 | #define MIN(a,b) ((a) < (b) ? (a) : (b)) | |
55 | ||
56 | #define NUM_SLOTS 4 | |
57 | #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] | |
58 | #define CURR_SLOT md.slot[md.curr_slot] | |
59 | ||
60 | #define O_pseudo_fixup (O_max + 1) | |
61 | ||
62 | enum special_section | |
63 | { | |
64 | SPECIAL_SECTION_BSS = 0, | |
65 | SPECIAL_SECTION_SBSS, | |
66 | SPECIAL_SECTION_SDATA, | |
67 | SPECIAL_SECTION_RODATA, | |
68 | SPECIAL_SECTION_COMMENT, | |
69 | SPECIAL_SECTION_UNWIND, | |
70 | SPECIAL_SECTION_UNWIND_INFO | |
71 | }; | |
72 | ||
73 | enum reloc_func | |
74 | { | |
75 | FUNC_FPTR_RELATIVE, | |
76 | FUNC_GP_RELATIVE, | |
77 | FUNC_LT_RELATIVE, | |
c67e42c9 | 78 | FUNC_PC_RELATIVE, |
800eeca4 JW |
79 | FUNC_PLT_RELATIVE, |
80 | FUNC_SEC_RELATIVE, | |
81 | FUNC_SEG_RELATIVE, | |
82 | FUNC_LTV_RELATIVE, | |
83 | FUNC_LT_FPTR_RELATIVE, | |
84 | }; | |
85 | ||
86 | enum reg_symbol | |
87 | { | |
88 | REG_GR = 0, | |
89 | REG_FR = (REG_GR + 128), | |
90 | REG_AR = (REG_FR + 128), | |
91 | REG_CR = (REG_AR + 128), | |
92 | REG_P = (REG_CR + 128), | |
93 | REG_BR = (REG_P + 64), | |
94 | REG_IP = (REG_BR + 8), | |
95 | REG_CFM, | |
96 | REG_PR, | |
97 | REG_PR_ROT, | |
98 | REG_PSR, | |
99 | REG_PSR_L, | |
100 | REG_PSR_UM, | |
101 | /* The following are pseudo-registers for use by gas only. */ | |
102 | IND_CPUID, | |
103 | IND_DBR, | |
104 | IND_DTR, | |
105 | IND_ITR, | |
106 | IND_IBR, | |
107 | IND_MEM, | |
108 | IND_MSR, | |
109 | IND_PKR, | |
110 | IND_PMC, | |
111 | IND_PMD, | |
112 | IND_RR, | |
542d6675 | 113 | /* The following pseudo-registers are used for unwind directives only: */ |
e0c9811a JW |
114 | REG_PSP, |
115 | REG_PRIUNAT, | |
800eeca4 JW |
116 | REG_NUM |
117 | }; | |
118 | ||
119 | enum dynreg_type | |
120 | { | |
121 | DYNREG_GR = 0, /* dynamic general purpose register */ | |
122 | DYNREG_FR, /* dynamic floating point register */ | |
123 | DYNREG_PR, /* dynamic predicate register */ | |
124 | DYNREG_NUM_TYPES | |
125 | }; | |
126 | ||
127 | /* On the ia64, we can't know the address of a text label until the | |
128 | instructions are packed into a bundle. To handle this, we keep | |
129 | track of the list of labels that appear in front of each | |
130 | instruction. */ | |
131 | struct label_fix | |
542d6675 KH |
132 | { |
133 | struct label_fix *next; | |
134 | struct symbol *sym; | |
135 | }; | |
800eeca4 JW |
136 | |
137 | extern int target_big_endian; | |
138 | ||
139 | /* Characters which always start a comment. */ | |
140 | const char comment_chars[] = ""; | |
141 | ||
142 | /* Characters which start a comment at the beginning of a line. */ | |
143 | const char line_comment_chars[] = "#"; | |
144 | ||
145 | /* Characters which may be used to separate multiple commands on a | |
146 | single line. */ | |
147 | const char line_separator_chars[] = ";"; | |
148 | ||
149 | /* Characters which are used to indicate an exponent in a floating | |
150 | point number. */ | |
151 | const char EXP_CHARS[] = "eE"; | |
152 | ||
153 | /* Characters which mean that a number is a floating point constant, | |
154 | as in 0d1.0. */ | |
155 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
156 | ||
542d6675 | 157 | /* ia64-specific option processing: */ |
800eeca4 | 158 | |
44f5c83a | 159 | const char *md_shortopts = "m:N:x::"; |
800eeca4 JW |
160 | |
161 | struct option md_longopts[] = | |
162 | { | |
c43c2cc5 JW |
163 | #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) |
164 | {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, | |
165 | #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) | |
166 | {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} | |
800eeca4 JW |
167 | }; |
168 | ||
169 | size_t md_longopts_size = sizeof (md_longopts); | |
170 | ||
171 | static struct | |
172 | { | |
173 | struct hash_control *pseudo_hash; /* pseudo opcode hash table */ | |
174 | struct hash_control *reg_hash; /* register name hash table */ | |
175 | struct hash_control *dynreg_hash; /* dynamic register hash table */ | |
176 | struct hash_control *const_hash; /* constant hash table */ | |
177 | struct hash_control *entry_hash; /* code entry hint hash table */ | |
178 | ||
179 | symbolS *regsym[REG_NUM]; | |
180 | ||
181 | /* If X_op is != O_absent, the registername for the instruction's | |
182 | qualifying predicate. If NULL, p0 is assumed for instructions | |
183 | that are predicatable. */ | |
184 | expressionS qp; | |
185 | ||
186 | unsigned int | |
197865e8 | 187 | manual_bundling : 1, |
800eeca4 JW |
188 | debug_dv: 1, |
189 | detect_dv: 1, | |
190 | explicit_mode : 1, /* which mode we're in */ | |
191 | default_explicit_mode : 1, /* which mode is the default */ | |
192 | mode_explicitly_set : 1, /* was the current mode explicitly set? */ | |
193 | auto_align : 1; | |
194 | ||
195 | /* Each bundle consists of up to three instructions. We keep | |
196 | track of four most recent instructions so we can correctly set | |
197865e8 | 197 | the end_of_insn_group for the last instruction in a bundle. */ |
800eeca4 JW |
198 | int curr_slot; |
199 | int num_slots_in_use; | |
200 | struct slot | |
201 | { | |
202 | unsigned int | |
203 | end_of_insn_group : 1, | |
204 | manual_bundling_on : 1, | |
205 | manual_bundling_off : 1; | |
206 | signed char user_template; /* user-selected template, if any */ | |
207 | unsigned char qp_regno; /* qualifying predicate */ | |
208 | /* This duplicates a good fraction of "struct fix" but we | |
209 | can't use a "struct fix" instead since we can't call | |
210 | fix_new_exp() until we know the address of the instruction. */ | |
211 | int num_fixups; | |
212 | struct insn_fix | |
213 | { | |
214 | bfd_reloc_code_real_type code; | |
215 | enum ia64_opnd opnd; /* type of operand in need of fix */ | |
216 | unsigned int is_pcrel : 1; /* is operand pc-relative? */ | |
217 | expressionS expr; /* the value to be inserted */ | |
218 | } | |
219 | fixup[2]; /* at most two fixups per insn */ | |
220 | struct ia64_opcode *idesc; | |
221 | struct label_fix *label_fixups; | |
f1bcba5b | 222 | struct label_fix *tag_fixups; |
800eeca4 JW |
223 | struct unw_rec_list *unwind_record; /* Unwind directive. */ |
224 | expressionS opnd[6]; | |
225 | char *src_file; | |
226 | unsigned int src_line; | |
227 | struct dwarf2_line_info debug_line; | |
228 | } | |
229 | slot[NUM_SLOTS]; | |
230 | ||
231 | segT last_text_seg; | |
232 | ||
233 | struct dynreg | |
234 | { | |
235 | struct dynreg *next; /* next dynamic register */ | |
236 | const char *name; | |
237 | unsigned short base; /* the base register number */ | |
238 | unsigned short num_regs; /* # of registers in this set */ | |
239 | } | |
240 | *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; | |
241 | ||
242 | flagword flags; /* ELF-header flags */ | |
243 | ||
244 | struct mem_offset { | |
245 | unsigned hint:1; /* is this hint currently valid? */ | |
246 | bfd_vma offset; /* mem.offset offset */ | |
247 | bfd_vma base; /* mem.offset base */ | |
248 | } mem_offset; | |
249 | ||
250 | int path; /* number of alt. entry points seen */ | |
251 | const char **entry_labels; /* labels of all alternate paths in | |
542d6675 | 252 | the current DV-checking block. */ |
800eeca4 | 253 | int maxpaths; /* size currently allocated for |
542d6675 | 254 | entry_labels */ |
800eeca4 JW |
255 | } |
256 | md; | |
257 | ||
542d6675 | 258 | /* application registers: */ |
800eeca4 | 259 | |
e0c9811a JW |
260 | #define AR_K0 0 |
261 | #define AR_K7 7 | |
262 | #define AR_RSC 16 | |
263 | #define AR_BSP 17 | |
264 | #define AR_BSPSTORE 18 | |
265 | #define AR_RNAT 19 | |
266 | #define AR_UNAT 36 | |
267 | #define AR_FPSR 40 | |
268 | #define AR_ITC 44 | |
269 | #define AR_PFS 64 | |
270 | #define AR_LC 65 | |
800eeca4 JW |
271 | |
272 | static const struct | |
273 | { | |
274 | const char *name; | |
275 | int regnum; | |
276 | } | |
277 | ar[] = | |
278 | { | |
279 | {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, | |
280 | {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, | |
281 | {"ar.rsc", 16}, {"ar.bsp", 17}, | |
282 | {"ar.bspstore", 18}, {"ar.rnat", 19}, | |
283 | {"ar.fcr", 21}, {"ar.eflag", 24}, | |
284 | {"ar.csd", 25}, {"ar.ssd", 26}, | |
285 | {"ar.cflg", 27}, {"ar.fsr", 28}, | |
286 | {"ar.fir", 29}, {"ar.fdr", 30}, | |
287 | {"ar.ccv", 32}, {"ar.unat", 36}, | |
288 | {"ar.fpsr", 40}, {"ar.itc", 44}, | |
289 | {"ar.pfs", 64}, {"ar.lc", 65}, | |
197865e8 | 290 | {"ar.ec", 66}, |
800eeca4 JW |
291 | }; |
292 | ||
293 | #define CR_IPSR 16 | |
294 | #define CR_ISR 17 | |
295 | #define CR_IIP 19 | |
296 | #define CR_IFA 20 | |
297 | #define CR_ITIR 21 | |
298 | #define CR_IIPA 22 | |
299 | #define CR_IFS 23 | |
300 | #define CR_IIM 24 | |
301 | #define CR_IHA 25 | |
302 | #define CR_IVR 65 | |
303 | #define CR_TPR 66 | |
304 | #define CR_EOI 67 | |
305 | #define CR_IRR0 68 | |
306 | #define CR_IRR3 71 | |
307 | #define CR_LRR0 80 | |
308 | #define CR_LRR1 81 | |
309 | ||
542d6675 | 310 | /* control registers: */ |
800eeca4 JW |
311 | static const struct |
312 | { | |
313 | const char *name; | |
314 | int regnum; | |
315 | } | |
316 | cr[] = | |
317 | { | |
318 | {"cr.dcr", 0}, | |
319 | {"cr.itm", 1}, | |
320 | {"cr.iva", 2}, | |
321 | {"cr.pta", 8}, | |
322 | {"cr.gpta", 9}, | |
323 | {"cr.ipsr", 16}, | |
324 | {"cr.isr", 17}, | |
325 | {"cr.iip", 19}, | |
326 | {"cr.ifa", 20}, | |
327 | {"cr.itir", 21}, | |
328 | {"cr.iipa", 22}, | |
329 | {"cr.ifs", 23}, | |
330 | {"cr.iim", 24}, | |
331 | {"cr.iha", 25}, | |
332 | {"cr.lid", 64}, | |
333 | {"cr.ivr", 65}, | |
334 | {"cr.tpr", 66}, | |
335 | {"cr.eoi", 67}, | |
336 | {"cr.irr0", 68}, | |
337 | {"cr.irr1", 69}, | |
338 | {"cr.irr2", 70}, | |
339 | {"cr.irr3", 71}, | |
340 | {"cr.itv", 72}, | |
341 | {"cr.pmv", 73}, | |
342 | {"cr.cmcv", 74}, | |
343 | {"cr.lrr0", 80}, | |
344 | {"cr.lrr1", 81} | |
345 | }; | |
346 | ||
347 | #define PSR_MFL 4 | |
348 | #define PSR_IC 13 | |
349 | #define PSR_DFL 18 | |
350 | #define PSR_CPL 32 | |
351 | ||
352 | static const struct const_desc | |
353 | { | |
354 | const char *name; | |
355 | valueT value; | |
356 | } | |
357 | const_bits[] = | |
358 | { | |
542d6675 | 359 | /* PSR constant masks: */ |
800eeca4 JW |
360 | |
361 | /* 0: reserved */ | |
362 | {"psr.be", ((valueT) 1) << 1}, | |
363 | {"psr.up", ((valueT) 1) << 2}, | |
364 | {"psr.ac", ((valueT) 1) << 3}, | |
365 | {"psr.mfl", ((valueT) 1) << 4}, | |
366 | {"psr.mfh", ((valueT) 1) << 5}, | |
367 | /* 6-12: reserved */ | |
368 | {"psr.ic", ((valueT) 1) << 13}, | |
369 | {"psr.i", ((valueT) 1) << 14}, | |
370 | {"psr.pk", ((valueT) 1) << 15}, | |
371 | /* 16: reserved */ | |
372 | {"psr.dt", ((valueT) 1) << 17}, | |
373 | {"psr.dfl", ((valueT) 1) << 18}, | |
374 | {"psr.dfh", ((valueT) 1) << 19}, | |
375 | {"psr.sp", ((valueT) 1) << 20}, | |
376 | {"psr.pp", ((valueT) 1) << 21}, | |
377 | {"psr.di", ((valueT) 1) << 22}, | |
378 | {"psr.si", ((valueT) 1) << 23}, | |
379 | {"psr.db", ((valueT) 1) << 24}, | |
380 | {"psr.lp", ((valueT) 1) << 25}, | |
381 | {"psr.tb", ((valueT) 1) << 26}, | |
382 | {"psr.rt", ((valueT) 1) << 27}, | |
383 | /* 28-31: reserved */ | |
384 | /* 32-33: cpl (current privilege level) */ | |
385 | {"psr.is", ((valueT) 1) << 34}, | |
386 | {"psr.mc", ((valueT) 1) << 35}, | |
387 | {"psr.it", ((valueT) 1) << 36}, | |
388 | {"psr.id", ((valueT) 1) << 37}, | |
389 | {"psr.da", ((valueT) 1) << 38}, | |
390 | {"psr.dd", ((valueT) 1) << 39}, | |
391 | {"psr.ss", ((valueT) 1) << 40}, | |
392 | /* 41-42: ri (restart instruction) */ | |
393 | {"psr.ed", ((valueT) 1) << 43}, | |
394 | {"psr.bn", ((valueT) 1) << 44}, | |
395 | }; | |
396 | ||
542d6675 | 397 | /* indirect register-sets/memory: */ |
800eeca4 JW |
398 | |
399 | static const struct | |
400 | { | |
401 | const char *name; | |
402 | int regnum; | |
403 | } | |
404 | indirect_reg[] = | |
405 | { | |
406 | { "CPUID", IND_CPUID }, | |
407 | { "cpuid", IND_CPUID }, | |
408 | { "dbr", IND_DBR }, | |
409 | { "dtr", IND_DTR }, | |
410 | { "itr", IND_ITR }, | |
411 | { "ibr", IND_IBR }, | |
412 | { "msr", IND_MSR }, | |
413 | { "pkr", IND_PKR }, | |
414 | { "pmc", IND_PMC }, | |
415 | { "pmd", IND_PMD }, | |
416 | { "rr", IND_RR }, | |
417 | }; | |
418 | ||
419 | /* Pseudo functions used to indicate relocation types (these functions | |
420 | start with an at sign (@). */ | |
421 | static struct | |
422 | { | |
423 | const char *name; | |
424 | enum pseudo_type | |
425 | { | |
426 | PSEUDO_FUNC_NONE, | |
427 | PSEUDO_FUNC_RELOC, | |
428 | PSEUDO_FUNC_CONST, | |
e0c9811a | 429 | PSEUDO_FUNC_REG, |
800eeca4 JW |
430 | PSEUDO_FUNC_FLOAT |
431 | } | |
432 | type; | |
433 | union | |
434 | { | |
435 | unsigned long ival; | |
436 | symbolS *sym; | |
437 | } | |
438 | u; | |
439 | } | |
440 | pseudo_func[] = | |
441 | { | |
542d6675 | 442 | /* reloc pseudo functions (these must come first!): */ |
800eeca4 JW |
443 | { "fptr", PSEUDO_FUNC_RELOC }, |
444 | { "gprel", PSEUDO_FUNC_RELOC }, | |
445 | { "ltoff", PSEUDO_FUNC_RELOC }, | |
c67e42c9 | 446 | { "pcrel", PSEUDO_FUNC_RELOC }, |
800eeca4 JW |
447 | { "pltoff", PSEUDO_FUNC_RELOC }, |
448 | { "secrel", PSEUDO_FUNC_RELOC }, | |
449 | { "segrel", PSEUDO_FUNC_RELOC }, | |
450 | { "ltv", PSEUDO_FUNC_RELOC }, | |
451 | { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ | |
452 | ||
542d6675 | 453 | /* mbtype4 constants: */ |
800eeca4 JW |
454 | { "alt", PSEUDO_FUNC_CONST, { 0xa } }, |
455 | { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, | |
456 | { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, | |
457 | { "rev", PSEUDO_FUNC_CONST, { 0xb } }, | |
458 | { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, | |
459 | ||
542d6675 | 460 | /* fclass constants: */ |
bf3ca999 | 461 | { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, |
800eeca4 JW |
462 | { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, |
463 | { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, | |
464 | { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, | |
465 | { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, | |
466 | { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, | |
467 | { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, | |
468 | { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, | |
469 | { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, | |
bf3ca999 TW |
470 | |
471 | { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ | |
e0c9811a | 472 | |
542d6675 | 473 | /* unwind-related constants: */ |
e0c9811a JW |
474 | { "svr4", PSEUDO_FUNC_CONST, { 0 } }, |
475 | { "hpux", PSEUDO_FUNC_CONST, { 1 } }, | |
476 | { "nt", PSEUDO_FUNC_CONST, { 2 } }, | |
477 | ||
542d6675 | 478 | /* unwind-related registers: */ |
e0c9811a | 479 | { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } |
800eeca4 JW |
480 | }; |
481 | ||
542d6675 | 482 | /* 41-bit nop opcodes (one per unit): */ |
800eeca4 JW |
483 | static const bfd_vma nop[IA64_NUM_UNITS] = |
484 | { | |
485 | 0x0000000000LL, /* NIL => break 0 */ | |
486 | 0x0008000000LL, /* I-unit nop */ | |
487 | 0x0008000000LL, /* M-unit nop */ | |
488 | 0x4000000000LL, /* B-unit nop */ | |
489 | 0x0008000000LL, /* F-unit nop */ | |
490 | 0x0008000000LL, /* L-"unit" nop */ | |
491 | 0x0008000000LL, /* X-unit nop */ | |
492 | }; | |
493 | ||
494 | /* Can't be `const' as it's passed to input routines (which have the | |
495 | habit of setting temporary sentinels. */ | |
496 | static char special_section_name[][20] = | |
497 | { | |
498 | {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, | |
499 | {".IA_64.unwind"}, {".IA_64.unwind_info"} | |
500 | }; | |
501 | ||
502 | /* The best template for a particular sequence of up to three | |
503 | instructions: */ | |
504 | #define N IA64_NUM_TYPES | |
505 | static unsigned char best_template[N][N][N]; | |
506 | #undef N | |
507 | ||
508 | /* Resource dependencies currently in effect */ | |
509 | static struct rsrc { | |
510 | int depind; /* dependency index */ | |
511 | const struct ia64_dependency *dependency; /* actual dependency */ | |
512 | unsigned specific:1, /* is this a specific bit/regno? */ | |
513 | link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ | |
514 | int index; /* specific regno/bit within dependency */ | |
515 | int note; /* optional qualifying note (0 if none) */ | |
516 | #define STATE_NONE 0 | |
517 | #define STATE_STOP 1 | |
518 | #define STATE_SRLZ 2 | |
519 | int insn_srlz; /* current insn serialization state */ | |
520 | int data_srlz; /* current data serialization state */ | |
521 | int qp_regno; /* qualifying predicate for this usage */ | |
522 | char *file; /* what file marked this dependency */ | |
523 | int line; /* what line marked this dependency */ | |
524 | struct mem_offset mem_offset; /* optional memory offset hint */ | |
7484b8e6 | 525 | enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ |
800eeca4 JW |
526 | int path; /* corresponding code entry index */ |
527 | } *regdeps = NULL; | |
528 | static int regdepslen = 0; | |
529 | static int regdepstotlen = 0; | |
530 | static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; | |
531 | static const char *dv_sem[] = { "none", "implied", "impliedf", | |
139368c9 | 532 | "data", "instr", "specific", "stop", "other" }; |
7484b8e6 | 533 | static const char *dv_cmp_type[] = { "none", "OR", "AND" }; |
800eeca4 JW |
534 | |
535 | /* Current state of PR mutexation */ | |
536 | static struct qpmutex { | |
537 | valueT prmask; | |
538 | int path; | |
539 | } *qp_mutexes = NULL; /* QP mutex bitmasks */ | |
540 | static int qp_mutexeslen = 0; | |
541 | static int qp_mutexestotlen = 0; | |
197865e8 | 542 | static valueT qp_safe_across_calls = 0; |
800eeca4 JW |
543 | |
544 | /* Current state of PR implications */ | |
545 | static struct qp_imply { | |
546 | unsigned p1:6; | |
547 | unsigned p2:6; | |
548 | unsigned p2_branched:1; | |
549 | int path; | |
550 | } *qp_implies = NULL; | |
551 | static int qp_implieslen = 0; | |
552 | static int qp_impliestotlen = 0; | |
553 | ||
197865e8 KH |
554 | /* Keep track of static GR values so that indirect register usage can |
555 | sometimes be tracked. */ | |
800eeca4 JW |
556 | static struct gr { |
557 | unsigned known:1; | |
558 | int path; | |
559 | valueT value; | |
560 | } gr_values[128] = {{ 1, 0 }}; | |
561 | ||
562 | /* These are the routines required to output the various types of | |
563 | unwind records. */ | |
564 | ||
f5a30c2e JW |
565 | /* A slot_number is a frag address plus the slot index (0-2). We use the |
566 | frag address here so that if there is a section switch in the middle of | |
567 | a function, then instructions emitted to a different section are not | |
568 | counted. Since there may be more than one frag for a function, this | |
569 | means we also need to keep track of which frag this address belongs to | |
570 | so we can compute inter-frag distances. This also nicely solves the | |
571 | problem with nops emitted for align directives, which can't easily be | |
572 | counted, but can easily be derived from frag sizes. */ | |
573 | ||
800eeca4 JW |
574 | typedef struct unw_rec_list { |
575 | unwind_record r; | |
e0c9811a | 576 | unsigned long slot_number; |
f5a30c2e | 577 | fragS *slot_frag; |
800eeca4 JW |
578 | struct unw_rec_list *next; |
579 | } unw_rec_list; | |
580 | ||
581 | #define SLOT_NUM_NOT_SET -1 | |
582 | ||
e0c9811a JW |
583 | static struct |
584 | { | |
585 | unsigned long next_slot_number; | |
f5a30c2e | 586 | fragS *next_slot_frag; |
e0c9811a JW |
587 | |
588 | /* Maintain a list of unwind entries for the current function. */ | |
589 | unw_rec_list *list; | |
590 | unw_rec_list *tail; | |
800eeca4 | 591 | |
e0c9811a JW |
592 | /* Any unwind entires that should be attached to the current slot |
593 | that an insn is being constructed for. */ | |
594 | unw_rec_list *current_entry; | |
800eeca4 | 595 | |
e0c9811a JW |
596 | /* These are used to create the unwind table entry for this function. */ |
597 | symbolS *proc_start; | |
598 | symbolS *proc_end; | |
599 | symbolS *info; /* pointer to unwind info */ | |
600 | symbolS *personality_routine; | |
800eeca4 | 601 | |
e0c9811a JW |
602 | /* TRUE if processing unwind directives in a prologue region. */ |
603 | int prologue; | |
30d25259 | 604 | int prologue_mask; |
e0c9811a | 605 | } unwind; |
800eeca4 JW |
606 | |
607 | typedef void (*vbyte_func) PARAMS ((int, char *, char *)); | |
608 | ||
542d6675 | 609 | /* Forward delarations: */ |
800eeca4 JW |
610 | static int ar_is_in_integer_unit PARAMS ((int regnum)); |
611 | static void set_section PARAMS ((char *name)); | |
612 | static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, | |
613 | unsigned int, unsigned int)); | |
614 | static void dot_radix PARAMS ((int)); | |
615 | static void dot_special_section PARAMS ((int)); | |
616 | static void dot_proc PARAMS ((int)); | |
617 | static void dot_fframe PARAMS ((int)); | |
618 | static void dot_vframe PARAMS ((int)); | |
150f24a2 JW |
619 | static void dot_vframesp PARAMS ((int)); |
620 | static void dot_vframepsp PARAMS ((int)); | |
800eeca4 JW |
621 | static void dot_save PARAMS ((int)); |
622 | static void dot_restore PARAMS ((int)); | |
150f24a2 JW |
623 | static void dot_restorereg PARAMS ((int)); |
624 | static void dot_restorereg_p PARAMS ((int)); | |
800eeca4 JW |
625 | static void dot_handlerdata PARAMS ((int)); |
626 | static void dot_unwentry PARAMS ((int)); | |
627 | static void dot_altrp PARAMS ((int)); | |
e0c9811a | 628 | static void dot_savemem PARAMS ((int)); |
800eeca4 JW |
629 | static void dot_saveg PARAMS ((int)); |
630 | static void dot_savef PARAMS ((int)); | |
631 | static void dot_saveb PARAMS ((int)); | |
632 | static void dot_savegf PARAMS ((int)); | |
633 | static void dot_spill PARAMS ((int)); | |
150f24a2 JW |
634 | static void dot_spillreg PARAMS ((int)); |
635 | static void dot_spillmem PARAMS ((int)); | |
636 | static void dot_spillreg_p PARAMS ((int)); | |
637 | static void dot_spillmem_p PARAMS ((int)); | |
638 | static void dot_label_state PARAMS ((int)); | |
639 | static void dot_copy_state PARAMS ((int)); | |
800eeca4 JW |
640 | static void dot_unwabi PARAMS ((int)); |
641 | static void dot_personality PARAMS ((int)); | |
642 | static void dot_body PARAMS ((int)); | |
643 | static void dot_prologue PARAMS ((int)); | |
644 | static void dot_endp PARAMS ((int)); | |
645 | static void dot_template PARAMS ((int)); | |
646 | static void dot_regstk PARAMS ((int)); | |
647 | static void dot_rot PARAMS ((int)); | |
648 | static void dot_byteorder PARAMS ((int)); | |
649 | static void dot_psr PARAMS ((int)); | |
650 | static void dot_alias PARAMS ((int)); | |
651 | static void dot_ln PARAMS ((int)); | |
652 | static char *parse_section_name PARAMS ((void)); | |
653 | static void dot_xdata PARAMS ((int)); | |
654 | static void stmt_float_cons PARAMS ((int)); | |
655 | static void stmt_cons_ua PARAMS ((int)); | |
656 | static void dot_xfloat_cons PARAMS ((int)); | |
657 | static void dot_xstringer PARAMS ((int)); | |
658 | static void dot_xdata_ua PARAMS ((int)); | |
659 | static void dot_xfloat_cons_ua PARAMS ((int)); | |
150f24a2 | 660 | static void print_prmask PARAMS ((valueT mask)); |
800eeca4 JW |
661 | static void dot_pred_rel PARAMS ((int)); |
662 | static void dot_reg_val PARAMS ((int)); | |
663 | static void dot_dv_mode PARAMS ((int)); | |
664 | static void dot_entry PARAMS ((int)); | |
665 | static void dot_mem_offset PARAMS ((int)); | |
e0c9811a | 666 | static void add_unwind_entry PARAMS((unw_rec_list *ptr)); |
542d6675 | 667 | static symbolS *declare_register PARAMS ((const char *name, int regnum)); |
800eeca4 JW |
668 | static void declare_register_set PARAMS ((const char *, int, int)); |
669 | static unsigned int operand_width PARAMS ((enum ia64_opnd)); | |
670 | static int operand_match PARAMS ((const struct ia64_opcode *idesc, | |
671 | int index, expressionS *e)); | |
672 | static int parse_operand PARAMS ((expressionS *e)); | |
673 | static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); | |
674 | static void build_insn PARAMS ((struct slot *, bfd_vma *)); | |
675 | static void emit_one_bundle PARAMS ((void)); | |
676 | static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); | |
197865e8 | 677 | static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, |
800eeca4 JW |
678 | bfd_reloc_code_real_type r_type)); |
679 | static void insn_group_break PARAMS ((int, int, int)); | |
150f24a2 JW |
680 | static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, |
681 | struct rsrc *, int depind, int path)); | |
800eeca4 JW |
682 | static void add_qp_mutex PARAMS((valueT mask)); |
683 | static void add_qp_imply PARAMS((int p1, int p2)); | |
684 | static void clear_qp_branch_flag PARAMS((valueT mask)); | |
685 | static void clear_qp_mutex PARAMS((valueT mask)); | |
686 | static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); | |
687 | static void clear_register_values PARAMS ((void)); | |
688 | static void print_dependency PARAMS ((const char *action, int depind)); | |
150f24a2 JW |
689 | static void instruction_serialization PARAMS ((void)); |
690 | static void data_serialization PARAMS ((void)); | |
691 | static void remove_marked_resource PARAMS ((struct rsrc *)); | |
800eeca4 | 692 | static int is_conditional_branch PARAMS ((struct ia64_opcode *)); |
150f24a2 | 693 | static int is_taken_branch PARAMS ((struct ia64_opcode *)); |
800eeca4 | 694 | static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); |
150f24a2 JW |
695 | static int depends_on PARAMS ((int, struct ia64_opcode *)); |
696 | static int specify_resource PARAMS ((const struct ia64_dependency *, | |
697 | struct ia64_opcode *, int, struct rsrc [], int, int)); | |
800eeca4 JW |
698 | static int check_dv PARAMS((struct ia64_opcode *idesc)); |
699 | static void check_dependencies PARAMS((struct ia64_opcode *)); | |
700 | static void mark_resources PARAMS((struct ia64_opcode *)); | |
701 | static void update_dependencies PARAMS((struct ia64_opcode *)); | |
702 | static void note_register_values PARAMS((struct ia64_opcode *)); | |
150f24a2 JW |
703 | static int qp_mutex PARAMS ((int, int, int)); |
704 | static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); | |
705 | static void output_vbyte_mem PARAMS ((int, char *, char *)); | |
706 | static void count_output PARAMS ((int, char *, char *)); | |
707 | static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); | |
708 | static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); | |
800eeca4 | 709 | static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
150f24a2 JW |
710 | static void output_P1_format PARAMS ((vbyte_func, int)); |
711 | static void output_P2_format PARAMS ((vbyte_func, int, int)); | |
712 | static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); | |
713 | static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); | |
714 | static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); | |
715 | static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); | |
716 | static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); | |
717 | static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
718 | static void output_P9_format PARAMS ((vbyte_func, int, int)); | |
719 | static void output_P10_format PARAMS ((vbyte_func, int, int)); | |
720 | static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
721 | static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); | |
800eeca4 JW |
722 | static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
723 | static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
150f24a2 JW |
724 | static char format_ab_reg PARAMS ((int, int)); |
725 | static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, | |
726 | unsigned long)); | |
727 | static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); | |
728 | static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, | |
729 | unsigned long)); | |
730 | static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); | |
731 | static void free_list_records PARAMS ((unw_rec_list *)); | |
732 | static unw_rec_list *output_prologue PARAMS ((void)); | |
733 | static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); | |
734 | static unw_rec_list *output_body PARAMS ((void)); | |
735 | static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); | |
736 | static unw_rec_list *output_mem_stack_v PARAMS ((void)); | |
737 | static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); | |
738 | static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); | |
739 | static unw_rec_list *output_rp_when PARAMS ((void)); | |
740 | static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); | |
741 | static unw_rec_list *output_rp_br PARAMS ((unsigned int)); | |
742 | static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); | |
743 | static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); | |
744 | static unw_rec_list *output_pfs_when PARAMS ((void)); | |
745 | static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); | |
746 | static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); | |
747 | static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); | |
748 | static unw_rec_list *output_preds_when PARAMS ((void)); | |
749 | static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); | |
750 | static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); | |
751 | static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); | |
752 | static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); | |
753 | static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); | |
754 | static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); | |
755 | static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); | |
756 | static unw_rec_list *output_br_mem PARAMS ((unsigned int)); | |
757 | static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); | |
758 | static unw_rec_list *output_spill_base PARAMS ((unsigned int)); | |
759 | static unw_rec_list *output_unat_when PARAMS ((void)); | |
760 | static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); | |
761 | static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); | |
762 | static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); | |
763 | static unw_rec_list *output_lc_when PARAMS ((void)); | |
764 | static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); | |
765 | static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); | |
766 | static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); | |
767 | static unw_rec_list *output_fpsr_when PARAMS ((void)); | |
768 | static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); | |
769 | static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); | |
770 | static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); | |
771 | static unw_rec_list *output_priunat_when_gr PARAMS ((void)); | |
772 | static unw_rec_list *output_priunat_when_mem PARAMS ((void)); | |
773 | static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); | |
774 | static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); | |
775 | static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); | |
776 | static unw_rec_list *output_bsp_when PARAMS ((void)); | |
777 | static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); | |
778 | static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); | |
779 | static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); | |
780 | static unw_rec_list *output_bspstore_when PARAMS ((void)); | |
781 | static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); | |
782 | static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); | |
783 | static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); | |
784 | static unw_rec_list *output_rnat_when PARAMS ((void)); | |
785 | static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); | |
786 | static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); | |
787 | static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); | |
788 | static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); | |
789 | static unw_rec_list *output_epilogue PARAMS ((unsigned long)); | |
790 | static unw_rec_list *output_label_state PARAMS ((unsigned long)); | |
791 | static unw_rec_list *output_copy_state PARAMS ((unsigned long)); | |
792 | static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
793 | static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
794 | static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
795 | unsigned int)); | |
796 | static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
797 | unsigned int)); | |
798 | static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, | |
799 | unsigned int)); | |
800 | static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
801 | unsigned int, unsigned int)); | |
802 | static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); | |
803 | static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); | |
804 | static int calc_record_size PARAMS ((unw_rec_list *)); | |
805 | static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); | |
806 | static int count_bits PARAMS ((unsigned long)); | |
f5a30c2e JW |
807 | static unsigned long slot_index PARAMS ((unsigned long, fragS *, |
808 | unsigned long, fragS *)); | |
150f24a2 JW |
809 | static void fixup_unw_records PARAMS ((unw_rec_list *)); |
810 | static int output_unw_records PARAMS ((unw_rec_list *, void **)); | |
811 | static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
812 | static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
813 | static int generate_unwind_image PARAMS ((void)); | |
800eeca4 JW |
814 | |
815 | /* Determine if application register REGNUM resides in the integer | |
816 | unit (as opposed to the memory unit). */ | |
817 | static int | |
818 | ar_is_in_integer_unit (reg) | |
819 | int reg; | |
820 | { | |
821 | reg -= REG_AR; | |
822 | ||
823 | return (reg == 64 /* pfs */ | |
824 | || reg == 65 /* lc */ | |
825 | || reg == 66 /* ec */ | |
826 | /* ??? ias accepts and puts these in the integer unit. */ | |
827 | || (reg >= 112 && reg <= 127)); | |
828 | } | |
829 | ||
830 | /* Switch to section NAME and create section if necessary. It's | |
831 | rather ugly that we have to manipulate input_line_pointer but I | |
832 | don't see any other way to accomplish the same thing without | |
833 | changing obj-elf.c (which may be the Right Thing, in the end). */ | |
834 | static void | |
835 | set_section (name) | |
836 | char *name; | |
837 | { | |
838 | char *saved_input_line_pointer; | |
839 | ||
840 | saved_input_line_pointer = input_line_pointer; | |
841 | input_line_pointer = name; | |
842 | obj_elf_section (0); | |
843 | input_line_pointer = saved_input_line_pointer; | |
844 | } | |
845 | ||
846 | /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ | |
847 | ||
848 | flagword | |
849 | ia64_elf_section_flags (flags, attr, type) | |
850 | flagword flags; | |
851 | int attr, type; | |
852 | { | |
853 | if (attr & SHF_IA_64_SHORT) | |
854 | flags |= SEC_SMALL_DATA; | |
855 | return flags; | |
856 | } | |
857 | ||
858 | static unsigned int | |
859 | set_regstack (ins, locs, outs, rots) | |
860 | unsigned int ins, locs, outs, rots; | |
861 | { | |
542d6675 KH |
862 | /* Size of frame. */ |
863 | unsigned int sof; | |
800eeca4 JW |
864 | |
865 | sof = ins + locs + outs; | |
866 | if (sof > 96) | |
867 | { | |
868 | as_bad ("Size of frame exceeds maximum of 96 registers"); | |
869 | return 0; | |
870 | } | |
871 | if (rots > sof) | |
872 | { | |
873 | as_warn ("Size of rotating registers exceeds frame size"); | |
874 | return 0; | |
875 | } | |
876 | md.in.base = REG_GR + 32; | |
877 | md.loc.base = md.in.base + ins; | |
878 | md.out.base = md.loc.base + locs; | |
879 | ||
880 | md.in.num_regs = ins; | |
881 | md.loc.num_regs = locs; | |
882 | md.out.num_regs = outs; | |
883 | md.rot.num_regs = rots; | |
884 | return sof; | |
885 | } | |
886 | ||
887 | void | |
888 | ia64_flush_insns () | |
889 | { | |
890 | struct label_fix *lfix; | |
891 | segT saved_seg; | |
892 | subsegT saved_subseg; | |
893 | ||
894 | if (!md.last_text_seg) | |
895 | return; | |
896 | ||
897 | saved_seg = now_seg; | |
898 | saved_subseg = now_subseg; | |
899 | ||
900 | subseg_set (md.last_text_seg, 0); | |
901 | ||
902 | while (md.num_slots_in_use > 0) | |
903 | emit_one_bundle (); /* force out queued instructions */ | |
904 | ||
905 | /* In case there are labels following the last instruction, resolve | |
542d6675 | 906 | those now: */ |
800eeca4 JW |
907 | for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) |
908 | { | |
909 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
910 | symbol_set_frag (lfix->sym, frag_now); | |
911 | } | |
912 | CURR_SLOT.label_fixups = 0; | |
f1bcba5b JW |
913 | for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) |
914 | { | |
915 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
916 | symbol_set_frag (lfix->sym, frag_now); | |
917 | } | |
918 | CURR_SLOT.tag_fixups = 0; | |
800eeca4 JW |
919 | |
920 | subseg_set (saved_seg, saved_subseg); | |
f1bcba5b JW |
921 | |
922 | if (md.qp.X_op == O_register) | |
923 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
924 | } |
925 | ||
926 | void | |
927 | ia64_do_align (nbytes) | |
928 | int nbytes; | |
929 | { | |
930 | char *saved_input_line_pointer = input_line_pointer; | |
931 | ||
932 | input_line_pointer = ""; | |
933 | s_align_bytes (nbytes); | |
934 | input_line_pointer = saved_input_line_pointer; | |
935 | } | |
936 | ||
937 | void | |
938 | ia64_cons_align (nbytes) | |
939 | int nbytes; | |
940 | { | |
941 | if (md.auto_align) | |
942 | { | |
943 | char *saved_input_line_pointer = input_line_pointer; | |
944 | input_line_pointer = ""; | |
945 | s_align_bytes (nbytes); | |
946 | input_line_pointer = saved_input_line_pointer; | |
947 | } | |
948 | } | |
949 | ||
950 | /* Output COUNT bytes to a memory location. */ | |
951 | static unsigned char *vbyte_mem_ptr = NULL; | |
952 | ||
197865e8 | 953 | void |
800eeca4 JW |
954 | output_vbyte_mem (count, ptr, comment) |
955 | int count; | |
956 | char *ptr; | |
957 | char *comment; | |
958 | { | |
959 | int x; | |
960 | if (vbyte_mem_ptr == NULL) | |
961 | abort (); | |
962 | ||
963 | if (count == 0) | |
964 | return; | |
965 | for (x = 0; x < count; x++) | |
966 | *(vbyte_mem_ptr++) = ptr[x]; | |
967 | } | |
968 | ||
969 | /* Count the number of bytes required for records. */ | |
970 | static int vbyte_count = 0; | |
197865e8 | 971 | void |
800eeca4 JW |
972 | count_output (count, ptr, comment) |
973 | int count; | |
974 | char *ptr; | |
975 | char *comment; | |
976 | { | |
977 | vbyte_count += count; | |
978 | } | |
979 | ||
980 | static void | |
981 | output_R1_format (f, rtype, rlen) | |
982 | vbyte_func f; | |
983 | unw_record_type rtype; | |
984 | int rlen; | |
985 | { | |
e0c9811a | 986 | int r = 0; |
800eeca4 JW |
987 | char byte; |
988 | if (rlen > 0x1f) | |
989 | { | |
990 | output_R3_format (f, rtype, rlen); | |
991 | return; | |
992 | } | |
197865e8 | 993 | |
e0c9811a JW |
994 | if (rtype == body) |
995 | r = 1; | |
996 | else if (rtype != prologue) | |
997 | as_bad ("record type is not valid"); | |
998 | ||
800eeca4 JW |
999 | byte = UNW_R1 | (r << 5) | (rlen & 0x1f); |
1000 | (*f) (1, &byte, NULL); | |
1001 | } | |
1002 | ||
1003 | static void | |
1004 | output_R2_format (f, mask, grsave, rlen) | |
1005 | vbyte_func f; | |
1006 | int mask, grsave; | |
1007 | unsigned long rlen; | |
1008 | { | |
1009 | char bytes[20]; | |
1010 | int count = 2; | |
1011 | mask = (mask & 0x0f); | |
1012 | grsave = (grsave & 0x7f); | |
1013 | ||
1014 | bytes[0] = (UNW_R2 | (mask >> 1)); | |
1015 | bytes[1] = (((mask & 0x01) << 7) | grsave); | |
1016 | count += output_leb128 (bytes + 2, rlen, 0); | |
1017 | (*f) (count, bytes, NULL); | |
1018 | } | |
1019 | ||
1020 | static void | |
1021 | output_R3_format (f, rtype, rlen) | |
1022 | vbyte_func f; | |
1023 | unw_record_type rtype; | |
1024 | unsigned long rlen; | |
1025 | { | |
e0c9811a | 1026 | int r = 0, count; |
800eeca4 JW |
1027 | char bytes[20]; |
1028 | if (rlen <= 0x1f) | |
1029 | { | |
1030 | output_R1_format (f, rtype, rlen); | |
1031 | return; | |
1032 | } | |
197865e8 | 1033 | |
e0c9811a JW |
1034 | if (rtype == body) |
1035 | r = 1; | |
1036 | else if (rtype != prologue) | |
1037 | as_bad ("record type is not valid"); | |
800eeca4 JW |
1038 | bytes[0] = (UNW_R3 | r); |
1039 | count = output_leb128 (bytes + 1, rlen, 0); | |
1040 | (*f) (count + 1, bytes, NULL); | |
1041 | } | |
1042 | ||
1043 | static void | |
1044 | output_P1_format (f, brmask) | |
1045 | vbyte_func f; | |
1046 | int brmask; | |
1047 | { | |
1048 | char byte; | |
1049 | byte = UNW_P1 | (brmask & 0x1f); | |
1050 | (*f) (1, &byte, NULL); | |
1051 | } | |
1052 | ||
1053 | static void | |
1054 | output_P2_format (f, brmask, gr) | |
1055 | vbyte_func f; | |
1056 | int brmask; | |
1057 | int gr; | |
1058 | { | |
1059 | char bytes[2]; | |
1060 | brmask = (brmask & 0x1f); | |
1061 | bytes[0] = UNW_P2 | (brmask >> 1); | |
1062 | bytes[1] = (((brmask & 1) << 7) | gr); | |
1063 | (*f) (2, bytes, NULL); | |
1064 | } | |
1065 | ||
1066 | static void | |
1067 | output_P3_format (f, rtype, reg) | |
1068 | vbyte_func f; | |
1069 | unw_record_type rtype; | |
1070 | int reg; | |
1071 | { | |
1072 | char bytes[2]; | |
e0c9811a | 1073 | int r = 0; |
800eeca4 JW |
1074 | reg = (reg & 0x7f); |
1075 | switch (rtype) | |
542d6675 | 1076 | { |
800eeca4 JW |
1077 | case psp_gr: |
1078 | r = 0; | |
1079 | break; | |
1080 | case rp_gr: | |
1081 | r = 1; | |
1082 | break; | |
1083 | case pfs_gr: | |
1084 | r = 2; | |
1085 | break; | |
1086 | case preds_gr: | |
1087 | r = 3; | |
1088 | break; | |
1089 | case unat_gr: | |
1090 | r = 4; | |
1091 | break; | |
1092 | case lc_gr: | |
1093 | r = 5; | |
1094 | break; | |
1095 | case rp_br: | |
1096 | r = 6; | |
1097 | break; | |
1098 | case rnat_gr: | |
1099 | r = 7; | |
1100 | break; | |
1101 | case bsp_gr: | |
1102 | r = 8; | |
1103 | break; | |
1104 | case bspstore_gr: | |
1105 | r = 9; | |
1106 | break; | |
1107 | case fpsr_gr: | |
1108 | r = 10; | |
1109 | break; | |
1110 | case priunat_gr: | |
1111 | r = 11; | |
1112 | break; | |
1113 | default: | |
1114 | as_bad ("Invalid record type for P3 format."); | |
542d6675 | 1115 | } |
800eeca4 JW |
1116 | bytes[0] = (UNW_P3 | (r >> 1)); |
1117 | bytes[1] = (((r & 1) << 7) | reg); | |
1118 | (*f) (2, bytes, NULL); | |
1119 | } | |
1120 | ||
800eeca4 | 1121 | static void |
e0c9811a | 1122 | output_P4_format (f, imask, imask_size) |
800eeca4 | 1123 | vbyte_func f; |
e0c9811a JW |
1124 | unsigned char *imask; |
1125 | unsigned long imask_size; | |
800eeca4 | 1126 | { |
e0c9811a JW |
1127 | imask[0] = UNW_P4; |
1128 | (*f) (imask_size, imask, NULL); | |
800eeca4 JW |
1129 | } |
1130 | ||
1131 | static void | |
1132 | output_P5_format (f, grmask, frmask) | |
1133 | vbyte_func f; | |
1134 | int grmask; | |
1135 | unsigned long frmask; | |
1136 | { | |
1137 | char bytes[4]; | |
1138 | grmask = (grmask & 0x0f); | |
1139 | ||
1140 | bytes[0] = UNW_P5; | |
1141 | bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); | |
1142 | bytes[2] = ((frmask & 0x0000ff00) >> 8); | |
1143 | bytes[3] = (frmask & 0x000000ff); | |
1144 | (*f) (4, bytes, NULL); | |
1145 | } | |
1146 | ||
1147 | static void | |
1148 | output_P6_format (f, rtype, rmask) | |
1149 | vbyte_func f; | |
1150 | unw_record_type rtype; | |
1151 | int rmask; | |
1152 | { | |
1153 | char byte; | |
e0c9811a | 1154 | int r = 0; |
197865e8 | 1155 | |
e0c9811a JW |
1156 | if (rtype == gr_mem) |
1157 | r = 1; | |
1158 | else if (rtype != fr_mem) | |
1159 | as_bad ("Invalid record type for format P6"); | |
800eeca4 JW |
1160 | byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); |
1161 | (*f) (1, &byte, NULL); | |
1162 | } | |
1163 | ||
1164 | static void | |
1165 | output_P7_format (f, rtype, w1, w2) | |
1166 | vbyte_func f; | |
1167 | unw_record_type rtype; | |
1168 | unsigned long w1; | |
1169 | unsigned long w2; | |
1170 | { | |
1171 | char bytes[20]; | |
1172 | int count = 1; | |
e0c9811a | 1173 | int r = 0; |
800eeca4 JW |
1174 | count += output_leb128 (bytes + 1, w1, 0); |
1175 | switch (rtype) | |
1176 | { | |
542d6675 KH |
1177 | case mem_stack_f: |
1178 | r = 0; | |
1179 | count += output_leb128 (bytes + count, w2 >> 4, 0); | |
1180 | break; | |
1181 | case mem_stack_v: | |
1182 | r = 1; | |
1183 | break; | |
1184 | case spill_base: | |
1185 | r = 2; | |
1186 | break; | |
1187 | case psp_sprel: | |
1188 | r = 3; | |
1189 | break; | |
1190 | case rp_when: | |
1191 | r = 4; | |
1192 | break; | |
1193 | case rp_psprel: | |
1194 | r = 5; | |
1195 | break; | |
1196 | case pfs_when: | |
1197 | r = 6; | |
1198 | break; | |
1199 | case pfs_psprel: | |
1200 | r = 7; | |
1201 | break; | |
1202 | case preds_when: | |
1203 | r = 8; | |
1204 | break; | |
1205 | case preds_psprel: | |
1206 | r = 9; | |
1207 | break; | |
1208 | case lc_when: | |
1209 | r = 10; | |
1210 | break; | |
1211 | case lc_psprel: | |
1212 | r = 11; | |
1213 | break; | |
1214 | case unat_when: | |
1215 | r = 12; | |
1216 | break; | |
1217 | case unat_psprel: | |
1218 | r = 13; | |
1219 | break; | |
1220 | case fpsr_when: | |
1221 | r = 14; | |
1222 | break; | |
1223 | case fpsr_psprel: | |
1224 | r = 15; | |
1225 | break; | |
1226 | default: | |
1227 | break; | |
800eeca4 JW |
1228 | } |
1229 | bytes[0] = (UNW_P7 | r); | |
1230 | (*f) (count, bytes, NULL); | |
1231 | } | |
1232 | ||
1233 | static void | |
1234 | output_P8_format (f, rtype, t) | |
1235 | vbyte_func f; | |
1236 | unw_record_type rtype; | |
1237 | unsigned long t; | |
1238 | { | |
1239 | char bytes[20]; | |
e0c9811a | 1240 | int r = 0; |
800eeca4 JW |
1241 | int count = 2; |
1242 | bytes[0] = UNW_P8; | |
1243 | switch (rtype) | |
1244 | { | |
542d6675 KH |
1245 | case rp_sprel: |
1246 | r = 1; | |
1247 | break; | |
1248 | case pfs_sprel: | |
1249 | r = 2; | |
1250 | break; | |
1251 | case preds_sprel: | |
1252 | r = 3; | |
1253 | break; | |
1254 | case lc_sprel: | |
1255 | r = 4; | |
1256 | break; | |
1257 | case unat_sprel: | |
1258 | r = 5; | |
1259 | break; | |
1260 | case fpsr_sprel: | |
1261 | r = 6; | |
1262 | break; | |
1263 | case bsp_when: | |
1264 | r = 7; | |
1265 | break; | |
1266 | case bsp_psprel: | |
1267 | r = 8; | |
1268 | break; | |
1269 | case bsp_sprel: | |
1270 | r = 9; | |
1271 | break; | |
1272 | case bspstore_when: | |
1273 | r = 10; | |
1274 | break; | |
1275 | case bspstore_psprel: | |
1276 | r = 11; | |
1277 | break; | |
1278 | case bspstore_sprel: | |
1279 | r = 12; | |
1280 | break; | |
1281 | case rnat_when: | |
1282 | r = 13; | |
1283 | break; | |
1284 | case rnat_psprel: | |
1285 | r = 14; | |
1286 | break; | |
1287 | case rnat_sprel: | |
1288 | r = 15; | |
1289 | break; | |
1290 | case priunat_when_gr: | |
1291 | r = 16; | |
1292 | break; | |
1293 | case priunat_psprel: | |
1294 | r = 17; | |
1295 | break; | |
1296 | case priunat_sprel: | |
1297 | r = 18; | |
1298 | break; | |
1299 | case priunat_when_mem: | |
1300 | r = 19; | |
1301 | break; | |
1302 | default: | |
1303 | break; | |
800eeca4 JW |
1304 | } |
1305 | bytes[1] = r; | |
1306 | count += output_leb128 (bytes + 2, t, 0); | |
1307 | (*f) (count, bytes, NULL); | |
1308 | } | |
1309 | ||
1310 | static void | |
1311 | output_P9_format (f, grmask, gr) | |
1312 | vbyte_func f; | |
1313 | int grmask; | |
1314 | int gr; | |
1315 | { | |
1316 | char bytes[3]; | |
1317 | bytes[0] = UNW_P9; | |
1318 | bytes[1] = (grmask & 0x0f); | |
1319 | bytes[2] = (gr & 0x7f); | |
1320 | (*f) (3, bytes, NULL); | |
1321 | } | |
1322 | ||
1323 | static void | |
1324 | output_P10_format (f, abi, context) | |
1325 | vbyte_func f; | |
1326 | int abi; | |
1327 | int context; | |
1328 | { | |
1329 | char bytes[3]; | |
1330 | bytes[0] = UNW_P10; | |
1331 | bytes[1] = (abi & 0xff); | |
1332 | bytes[2] = (context & 0xff); | |
1333 | (*f) (3, bytes, NULL); | |
1334 | } | |
1335 | ||
1336 | static void | |
1337 | output_B1_format (f, rtype, label) | |
1338 | vbyte_func f; | |
1339 | unw_record_type rtype; | |
1340 | unsigned long label; | |
1341 | { | |
1342 | char byte; | |
e0c9811a | 1343 | int r = 0; |
197865e8 | 1344 | if (label > 0x1f) |
800eeca4 JW |
1345 | { |
1346 | output_B4_format (f, rtype, label); | |
1347 | return; | |
1348 | } | |
e0c9811a JW |
1349 | if (rtype == copy_state) |
1350 | r = 1; | |
1351 | else if (rtype != label_state) | |
1352 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1353 | |
1354 | byte = (UNW_B1 | (r << 5) | (label & 0x1f)); | |
1355 | (*f) (1, &byte, NULL); | |
1356 | } | |
1357 | ||
1358 | static void | |
1359 | output_B2_format (f, ecount, t) | |
1360 | vbyte_func f; | |
1361 | unsigned long ecount; | |
1362 | unsigned long t; | |
1363 | { | |
1364 | char bytes[20]; | |
1365 | int count = 1; | |
1366 | if (ecount > 0x1f) | |
1367 | { | |
1368 | output_B3_format (f, ecount, t); | |
1369 | return; | |
1370 | } | |
1371 | bytes[0] = (UNW_B2 | (ecount & 0x1f)); | |
1372 | count += output_leb128 (bytes + 1, t, 0); | |
1373 | (*f) (count, bytes, NULL); | |
1374 | } | |
1375 | ||
1376 | static void | |
1377 | output_B3_format (f, ecount, t) | |
1378 | vbyte_func f; | |
1379 | unsigned long ecount; | |
1380 | unsigned long t; | |
1381 | { | |
1382 | char bytes[20]; | |
1383 | int count = 1; | |
1384 | if (ecount <= 0x1f) | |
1385 | { | |
1386 | output_B2_format (f, ecount, t); | |
1387 | return; | |
1388 | } | |
1389 | bytes[0] = UNW_B3; | |
1390 | count += output_leb128 (bytes + 1, t, 0); | |
1391 | count += output_leb128 (bytes + count, ecount, 0); | |
1392 | (*f) (count, bytes, NULL); | |
1393 | } | |
1394 | ||
1395 | static void | |
1396 | output_B4_format (f, rtype, label) | |
1397 | vbyte_func f; | |
1398 | unw_record_type rtype; | |
1399 | unsigned long label; | |
1400 | { | |
1401 | char bytes[20]; | |
e0c9811a | 1402 | int r = 0; |
800eeca4 | 1403 | int count = 1; |
197865e8 | 1404 | if (label <= 0x1f) |
800eeca4 JW |
1405 | { |
1406 | output_B1_format (f, rtype, label); | |
1407 | return; | |
1408 | } | |
197865e8 | 1409 | |
e0c9811a JW |
1410 | if (rtype == copy_state) |
1411 | r = 1; | |
1412 | else if (rtype != label_state) | |
1413 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1414 | |
1415 | bytes[0] = (UNW_B4 | (r << 3)); | |
1416 | count += output_leb128 (bytes + 1, label, 0); | |
1417 | (*f) (count, bytes, NULL); | |
1418 | } | |
1419 | ||
1420 | static char | |
e0c9811a | 1421 | format_ab_reg (ab, reg) |
542d6675 KH |
1422 | int ab; |
1423 | int reg; | |
800eeca4 JW |
1424 | { |
1425 | int ret; | |
e0c9811a | 1426 | ab = (ab & 3); |
800eeca4 | 1427 | reg = (reg & 0x1f); |
e0c9811a | 1428 | ret = (ab << 5) | reg; |
800eeca4 JW |
1429 | return ret; |
1430 | } | |
1431 | ||
1432 | static void | |
e0c9811a | 1433 | output_X1_format (f, rtype, ab, reg, t, w1) |
800eeca4 JW |
1434 | vbyte_func f; |
1435 | unw_record_type rtype; | |
e0c9811a | 1436 | int ab, reg; |
800eeca4 JW |
1437 | unsigned long t; |
1438 | unsigned long w1; | |
1439 | { | |
1440 | char bytes[20]; | |
e0c9811a | 1441 | int r = 0; |
800eeca4 JW |
1442 | int count = 2; |
1443 | bytes[0] = UNW_X1; | |
197865e8 | 1444 | |
e0c9811a JW |
1445 | if (rtype == spill_sprel) |
1446 | r = 1; | |
1447 | else if (rtype != spill_psprel) | |
1448 | as_bad ("Invalid record type for format X1"); | |
1449 | bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); | |
800eeca4 JW |
1450 | count += output_leb128 (bytes + 2, t, 0); |
1451 | count += output_leb128 (bytes + count, w1, 0); | |
1452 | (*f) (count, bytes, NULL); | |
1453 | } | |
1454 | ||
1455 | static void | |
e0c9811a | 1456 | output_X2_format (f, ab, reg, x, y, treg, t) |
800eeca4 | 1457 | vbyte_func f; |
e0c9811a | 1458 | int ab, reg; |
800eeca4 JW |
1459 | int x, y, treg; |
1460 | unsigned long t; | |
1461 | { | |
1462 | char bytes[20]; | |
800eeca4 JW |
1463 | int count = 3; |
1464 | bytes[0] = UNW_X2; | |
e0c9811a | 1465 | bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1466 | bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); |
1467 | count += output_leb128 (bytes + 3, t, 0); | |
1468 | (*f) (count, bytes, NULL); | |
1469 | } | |
1470 | ||
1471 | static void | |
e0c9811a | 1472 | output_X3_format (f, rtype, qp, ab, reg, t, w1) |
800eeca4 JW |
1473 | vbyte_func f; |
1474 | unw_record_type rtype; | |
1475 | int qp; | |
e0c9811a | 1476 | int ab, reg; |
800eeca4 JW |
1477 | unsigned long t; |
1478 | unsigned long w1; | |
1479 | { | |
1480 | char bytes[20]; | |
e0c9811a | 1481 | int r = 0; |
800eeca4 | 1482 | int count = 3; |
e0c9811a JW |
1483 | bytes[0] = UNW_X3; |
1484 | ||
1485 | if (rtype == spill_sprel_p) | |
1486 | r = 1; | |
1487 | else if (rtype != spill_psprel_p) | |
1488 | as_bad ("Invalid record type for format X3"); | |
800eeca4 | 1489 | bytes[1] = ((r << 7) | (qp & 0x3f)); |
e0c9811a | 1490 | bytes[2] = format_ab_reg (ab, reg); |
800eeca4 JW |
1491 | count += output_leb128 (bytes + 3, t, 0); |
1492 | count += output_leb128 (bytes + count, w1, 0); | |
1493 | (*f) (count, bytes, NULL); | |
1494 | } | |
1495 | ||
1496 | static void | |
e0c9811a | 1497 | output_X4_format (f, qp, ab, reg, x, y, treg, t) |
800eeca4 JW |
1498 | vbyte_func f; |
1499 | int qp; | |
e0c9811a | 1500 | int ab, reg; |
800eeca4 JW |
1501 | int x, y, treg; |
1502 | unsigned long t; | |
1503 | { | |
1504 | char bytes[20]; | |
800eeca4 | 1505 | int count = 4; |
e0c9811a | 1506 | bytes[0] = UNW_X4; |
800eeca4 | 1507 | bytes[1] = (qp & 0x3f); |
e0c9811a | 1508 | bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1509 | bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); |
1510 | count += output_leb128 (bytes + 4, t, 0); | |
1511 | (*f) (count, bytes, NULL); | |
1512 | } | |
1513 | ||
1514 | /* This function allocates a record list structure, and initializes fields. */ | |
542d6675 | 1515 | |
800eeca4 | 1516 | static unw_rec_list * |
197865e8 | 1517 | alloc_record (unw_record_type t) |
800eeca4 JW |
1518 | { |
1519 | unw_rec_list *ptr; | |
1520 | ptr = xmalloc (sizeof (*ptr)); | |
1521 | ptr->next = NULL; | |
1522 | ptr->slot_number = SLOT_NUM_NOT_SET; | |
1523 | ptr->r.type = t; | |
1524 | return ptr; | |
1525 | } | |
1526 | ||
800eeca4 | 1527 | /* This function frees an entire list of record structures. */ |
542d6675 | 1528 | |
800eeca4 JW |
1529 | void |
1530 | free_list_records (unw_rec_list *first) | |
1531 | { | |
1532 | unw_rec_list *ptr; | |
542d6675 | 1533 | for (ptr = first; ptr != NULL;) |
800eeca4 JW |
1534 | { |
1535 | unw_rec_list *tmp = ptr; | |
e0c9811a JW |
1536 | |
1537 | if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) | |
1538 | && tmp->r.record.r.mask.i) | |
1539 | free (tmp->r.record.r.mask.i); | |
1540 | ||
800eeca4 JW |
1541 | ptr = ptr->next; |
1542 | free (tmp); | |
1543 | } | |
1544 | } | |
1545 | ||
1546 | static unw_rec_list * | |
1547 | output_prologue () | |
1548 | { | |
1549 | unw_rec_list *ptr = alloc_record (prologue); | |
e0c9811a | 1550 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
800eeca4 JW |
1551 | return ptr; |
1552 | } | |
1553 | ||
1554 | static unw_rec_list * | |
1555 | output_prologue_gr (saved_mask, reg) | |
1556 | unsigned int saved_mask; | |
1557 | unsigned int reg; | |
1558 | { | |
1559 | unw_rec_list *ptr = alloc_record (prologue_gr); | |
e0c9811a JW |
1560 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
1561 | ptr->r.record.r.grmask = saved_mask; | |
800eeca4 JW |
1562 | ptr->r.record.r.grsave = reg; |
1563 | return ptr; | |
1564 | } | |
1565 | ||
1566 | static unw_rec_list * | |
1567 | output_body () | |
1568 | { | |
1569 | unw_rec_list *ptr = alloc_record (body); | |
1570 | return ptr; | |
1571 | } | |
1572 | ||
1573 | static unw_rec_list * | |
1574 | output_mem_stack_f (size) | |
1575 | unsigned int size; | |
1576 | { | |
1577 | unw_rec_list *ptr = alloc_record (mem_stack_f); | |
1578 | ptr->r.record.p.size = size; | |
1579 | return ptr; | |
1580 | } | |
1581 | ||
1582 | static unw_rec_list * | |
1583 | output_mem_stack_v () | |
1584 | { | |
1585 | unw_rec_list *ptr = alloc_record (mem_stack_v); | |
1586 | return ptr; | |
1587 | } | |
1588 | ||
1589 | static unw_rec_list * | |
1590 | output_psp_gr (gr) | |
1591 | unsigned int gr; | |
1592 | { | |
1593 | unw_rec_list *ptr = alloc_record (psp_gr); | |
1594 | ptr->r.record.p.gr = gr; | |
1595 | return ptr; | |
1596 | } | |
1597 | ||
1598 | static unw_rec_list * | |
1599 | output_psp_sprel (offset) | |
1600 | unsigned int offset; | |
1601 | { | |
1602 | unw_rec_list *ptr = alloc_record (psp_sprel); | |
542d6675 | 1603 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1604 | return ptr; |
1605 | } | |
1606 | ||
1607 | static unw_rec_list * | |
1608 | output_rp_when () | |
1609 | { | |
1610 | unw_rec_list *ptr = alloc_record (rp_when); | |
1611 | return ptr; | |
1612 | } | |
1613 | ||
1614 | static unw_rec_list * | |
1615 | output_rp_gr (gr) | |
1616 | unsigned int gr; | |
1617 | { | |
1618 | unw_rec_list *ptr = alloc_record (rp_gr); | |
1619 | ptr->r.record.p.gr = gr; | |
1620 | return ptr; | |
1621 | } | |
1622 | ||
1623 | static unw_rec_list * | |
1624 | output_rp_br (br) | |
1625 | unsigned int br; | |
1626 | { | |
1627 | unw_rec_list *ptr = alloc_record (rp_br); | |
1628 | ptr->r.record.p.br = br; | |
1629 | return ptr; | |
1630 | } | |
1631 | ||
1632 | static unw_rec_list * | |
1633 | output_rp_psprel (offset) | |
1634 | unsigned int offset; | |
1635 | { | |
1636 | unw_rec_list *ptr = alloc_record (rp_psprel); | |
542d6675 | 1637 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1638 | return ptr; |
1639 | } | |
1640 | ||
1641 | static unw_rec_list * | |
1642 | output_rp_sprel (offset) | |
1643 | unsigned int offset; | |
1644 | { | |
1645 | unw_rec_list *ptr = alloc_record (rp_sprel); | |
542d6675 | 1646 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1647 | return ptr; |
1648 | } | |
1649 | ||
1650 | static unw_rec_list * | |
1651 | output_pfs_when () | |
1652 | { | |
1653 | unw_rec_list *ptr = alloc_record (pfs_when); | |
1654 | return ptr; | |
1655 | } | |
1656 | ||
1657 | static unw_rec_list * | |
1658 | output_pfs_gr (gr) | |
1659 | unsigned int gr; | |
1660 | { | |
1661 | unw_rec_list *ptr = alloc_record (pfs_gr); | |
1662 | ptr->r.record.p.gr = gr; | |
1663 | return ptr; | |
1664 | } | |
1665 | ||
1666 | static unw_rec_list * | |
1667 | output_pfs_psprel (offset) | |
1668 | unsigned int offset; | |
1669 | { | |
1670 | unw_rec_list *ptr = alloc_record (pfs_psprel); | |
542d6675 | 1671 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1672 | return ptr; |
1673 | } | |
1674 | ||
1675 | static unw_rec_list * | |
1676 | output_pfs_sprel (offset) | |
1677 | unsigned int offset; | |
1678 | { | |
1679 | unw_rec_list *ptr = alloc_record (pfs_sprel); | |
542d6675 | 1680 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1681 | return ptr; |
1682 | } | |
1683 | ||
1684 | static unw_rec_list * | |
1685 | output_preds_when () | |
1686 | { | |
1687 | unw_rec_list *ptr = alloc_record (preds_when); | |
1688 | return ptr; | |
1689 | } | |
1690 | ||
1691 | static unw_rec_list * | |
1692 | output_preds_gr (gr) | |
1693 | unsigned int gr; | |
1694 | { | |
1695 | unw_rec_list *ptr = alloc_record (preds_gr); | |
1696 | ptr->r.record.p.gr = gr; | |
1697 | return ptr; | |
1698 | } | |
1699 | ||
1700 | static unw_rec_list * | |
1701 | output_preds_psprel (offset) | |
1702 | unsigned int offset; | |
1703 | { | |
1704 | unw_rec_list *ptr = alloc_record (preds_psprel); | |
542d6675 | 1705 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1706 | return ptr; |
1707 | } | |
1708 | ||
1709 | static unw_rec_list * | |
1710 | output_preds_sprel (offset) | |
1711 | unsigned int offset; | |
1712 | { | |
1713 | unw_rec_list *ptr = alloc_record (preds_sprel); | |
542d6675 | 1714 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1715 | return ptr; |
1716 | } | |
1717 | ||
1718 | static unw_rec_list * | |
1719 | output_fr_mem (mask) | |
1720 | unsigned int mask; | |
1721 | { | |
1722 | unw_rec_list *ptr = alloc_record (fr_mem); | |
1723 | ptr->r.record.p.rmask = mask; | |
1724 | return ptr; | |
1725 | } | |
1726 | ||
1727 | static unw_rec_list * | |
1728 | output_frgr_mem (gr_mask, fr_mask) | |
1729 | unsigned int gr_mask; | |
1730 | unsigned int fr_mask; | |
1731 | { | |
1732 | unw_rec_list *ptr = alloc_record (frgr_mem); | |
1733 | ptr->r.record.p.grmask = gr_mask; | |
1734 | ptr->r.record.p.frmask = fr_mask; | |
1735 | return ptr; | |
1736 | } | |
1737 | ||
1738 | static unw_rec_list * | |
1739 | output_gr_gr (mask, reg) | |
1740 | unsigned int mask; | |
1741 | unsigned int reg; | |
1742 | { | |
1743 | unw_rec_list *ptr = alloc_record (gr_gr); | |
1744 | ptr->r.record.p.grmask = mask; | |
1745 | ptr->r.record.p.gr = reg; | |
1746 | return ptr; | |
1747 | } | |
1748 | ||
1749 | static unw_rec_list * | |
1750 | output_gr_mem (mask) | |
1751 | unsigned int mask; | |
1752 | { | |
1753 | unw_rec_list *ptr = alloc_record (gr_mem); | |
1754 | ptr->r.record.p.rmask = mask; | |
1755 | return ptr; | |
1756 | } | |
1757 | ||
1758 | static unw_rec_list * | |
1759 | output_br_mem (unsigned int mask) | |
1760 | { | |
1761 | unw_rec_list *ptr = alloc_record (br_mem); | |
1762 | ptr->r.record.p.brmask = mask; | |
1763 | return ptr; | |
1764 | } | |
1765 | ||
1766 | static unw_rec_list * | |
1767 | output_br_gr (save_mask, reg) | |
1768 | unsigned int save_mask; | |
1769 | unsigned int reg; | |
1770 | { | |
1771 | unw_rec_list *ptr = alloc_record (br_gr); | |
1772 | ptr->r.record.p.brmask = save_mask; | |
1773 | ptr->r.record.p.gr = reg; | |
1774 | return ptr; | |
1775 | } | |
1776 | ||
1777 | static unw_rec_list * | |
1778 | output_spill_base (offset) | |
1779 | unsigned int offset; | |
1780 | { | |
1781 | unw_rec_list *ptr = alloc_record (spill_base); | |
542d6675 | 1782 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1783 | return ptr; |
1784 | } | |
1785 | ||
1786 | static unw_rec_list * | |
1787 | output_unat_when () | |
1788 | { | |
1789 | unw_rec_list *ptr = alloc_record (unat_when); | |
1790 | return ptr; | |
1791 | } | |
1792 | ||
1793 | static unw_rec_list * | |
1794 | output_unat_gr (gr) | |
1795 | unsigned int gr; | |
1796 | { | |
1797 | unw_rec_list *ptr = alloc_record (unat_gr); | |
1798 | ptr->r.record.p.gr = gr; | |
1799 | return ptr; | |
1800 | } | |
1801 | ||
1802 | static unw_rec_list * | |
1803 | output_unat_psprel (offset) | |
1804 | unsigned int offset; | |
1805 | { | |
1806 | unw_rec_list *ptr = alloc_record (unat_psprel); | |
542d6675 | 1807 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1808 | return ptr; |
1809 | } | |
1810 | ||
1811 | static unw_rec_list * | |
1812 | output_unat_sprel (offset) | |
1813 | unsigned int offset; | |
1814 | { | |
1815 | unw_rec_list *ptr = alloc_record (unat_sprel); | |
542d6675 | 1816 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1817 | return ptr; |
1818 | } | |
1819 | ||
1820 | static unw_rec_list * | |
1821 | output_lc_when () | |
1822 | { | |
1823 | unw_rec_list *ptr = alloc_record (lc_when); | |
1824 | return ptr; | |
1825 | } | |
1826 | ||
1827 | static unw_rec_list * | |
1828 | output_lc_gr (gr) | |
1829 | unsigned int gr; | |
1830 | { | |
1831 | unw_rec_list *ptr = alloc_record (lc_gr); | |
1832 | ptr->r.record.p.gr = gr; | |
1833 | return ptr; | |
1834 | } | |
1835 | ||
1836 | static unw_rec_list * | |
1837 | output_lc_psprel (offset) | |
1838 | unsigned int offset; | |
1839 | { | |
1840 | unw_rec_list *ptr = alloc_record (lc_psprel); | |
542d6675 | 1841 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1842 | return ptr; |
1843 | } | |
1844 | ||
1845 | static unw_rec_list * | |
1846 | output_lc_sprel (offset) | |
1847 | unsigned int offset; | |
1848 | { | |
1849 | unw_rec_list *ptr = alloc_record (lc_sprel); | |
542d6675 | 1850 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1851 | return ptr; |
1852 | } | |
1853 | ||
1854 | static unw_rec_list * | |
1855 | output_fpsr_when () | |
1856 | { | |
1857 | unw_rec_list *ptr = alloc_record (fpsr_when); | |
1858 | return ptr; | |
1859 | } | |
1860 | ||
1861 | static unw_rec_list * | |
1862 | output_fpsr_gr (gr) | |
1863 | unsigned int gr; | |
1864 | { | |
1865 | unw_rec_list *ptr = alloc_record (fpsr_gr); | |
1866 | ptr->r.record.p.gr = gr; | |
1867 | return ptr; | |
1868 | } | |
1869 | ||
1870 | static unw_rec_list * | |
1871 | output_fpsr_psprel (offset) | |
1872 | unsigned int offset; | |
1873 | { | |
1874 | unw_rec_list *ptr = alloc_record (fpsr_psprel); | |
542d6675 | 1875 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1876 | return ptr; |
1877 | } | |
1878 | ||
1879 | static unw_rec_list * | |
1880 | output_fpsr_sprel (offset) | |
1881 | unsigned int offset; | |
1882 | { | |
1883 | unw_rec_list *ptr = alloc_record (fpsr_sprel); | |
542d6675 | 1884 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1885 | return ptr; |
1886 | } | |
1887 | ||
1888 | static unw_rec_list * | |
1889 | output_priunat_when_gr () | |
1890 | { | |
1891 | unw_rec_list *ptr = alloc_record (priunat_when_gr); | |
1892 | return ptr; | |
1893 | } | |
1894 | ||
1895 | static unw_rec_list * | |
1896 | output_priunat_when_mem () | |
1897 | { | |
1898 | unw_rec_list *ptr = alloc_record (priunat_when_mem); | |
1899 | return ptr; | |
1900 | } | |
1901 | ||
1902 | static unw_rec_list * | |
1903 | output_priunat_gr (gr) | |
1904 | unsigned int gr; | |
1905 | { | |
1906 | unw_rec_list *ptr = alloc_record (priunat_gr); | |
1907 | ptr->r.record.p.gr = gr; | |
1908 | return ptr; | |
1909 | } | |
1910 | ||
1911 | static unw_rec_list * | |
1912 | output_priunat_psprel (offset) | |
1913 | unsigned int offset; | |
1914 | { | |
1915 | unw_rec_list *ptr = alloc_record (priunat_psprel); | |
542d6675 | 1916 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1917 | return ptr; |
1918 | } | |
1919 | ||
1920 | static unw_rec_list * | |
1921 | output_priunat_sprel (offset) | |
1922 | unsigned int offset; | |
1923 | { | |
1924 | unw_rec_list *ptr = alloc_record (priunat_sprel); | |
542d6675 | 1925 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1926 | return ptr; |
1927 | } | |
1928 | ||
1929 | static unw_rec_list * | |
1930 | output_bsp_when () | |
1931 | { | |
1932 | unw_rec_list *ptr = alloc_record (bsp_when); | |
1933 | return ptr; | |
1934 | } | |
1935 | ||
1936 | static unw_rec_list * | |
1937 | output_bsp_gr (gr) | |
1938 | unsigned int gr; | |
1939 | { | |
1940 | unw_rec_list *ptr = alloc_record (bsp_gr); | |
1941 | ptr->r.record.p.gr = gr; | |
1942 | return ptr; | |
1943 | } | |
1944 | ||
1945 | static unw_rec_list * | |
1946 | output_bsp_psprel (offset) | |
1947 | unsigned int offset; | |
1948 | { | |
1949 | unw_rec_list *ptr = alloc_record (bsp_psprel); | |
542d6675 | 1950 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1951 | return ptr; |
1952 | } | |
1953 | ||
1954 | static unw_rec_list * | |
1955 | output_bsp_sprel (offset) | |
1956 | unsigned int offset; | |
1957 | { | |
1958 | unw_rec_list *ptr = alloc_record (bsp_sprel); | |
542d6675 | 1959 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1960 | return ptr; |
1961 | } | |
1962 | ||
1963 | static unw_rec_list * | |
1964 | output_bspstore_when () | |
1965 | { | |
1966 | unw_rec_list *ptr = alloc_record (bspstore_when); | |
1967 | return ptr; | |
1968 | } | |
1969 | ||
1970 | static unw_rec_list * | |
1971 | output_bspstore_gr (gr) | |
1972 | unsigned int gr; | |
1973 | { | |
1974 | unw_rec_list *ptr = alloc_record (bspstore_gr); | |
1975 | ptr->r.record.p.gr = gr; | |
1976 | return ptr; | |
1977 | } | |
1978 | ||
1979 | static unw_rec_list * | |
1980 | output_bspstore_psprel (offset) | |
1981 | unsigned int offset; | |
1982 | { | |
1983 | unw_rec_list *ptr = alloc_record (bspstore_psprel); | |
542d6675 | 1984 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1985 | return ptr; |
1986 | } | |
1987 | ||
1988 | static unw_rec_list * | |
1989 | output_bspstore_sprel (offset) | |
1990 | unsigned int offset; | |
1991 | { | |
1992 | unw_rec_list *ptr = alloc_record (bspstore_sprel); | |
542d6675 | 1993 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1994 | return ptr; |
1995 | } | |
1996 | ||
1997 | static unw_rec_list * | |
1998 | output_rnat_when () | |
1999 | { | |
2000 | unw_rec_list *ptr = alloc_record (rnat_when); | |
2001 | return ptr; | |
2002 | } | |
2003 | ||
2004 | static unw_rec_list * | |
2005 | output_rnat_gr (gr) | |
2006 | unsigned int gr; | |
2007 | { | |
2008 | unw_rec_list *ptr = alloc_record (rnat_gr); | |
2009 | ptr->r.record.p.gr = gr; | |
2010 | return ptr; | |
2011 | } | |
2012 | ||
2013 | static unw_rec_list * | |
2014 | output_rnat_psprel (offset) | |
2015 | unsigned int offset; | |
2016 | { | |
2017 | unw_rec_list *ptr = alloc_record (rnat_psprel); | |
542d6675 | 2018 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2019 | return ptr; |
2020 | } | |
2021 | ||
2022 | static unw_rec_list * | |
2023 | output_rnat_sprel (offset) | |
2024 | unsigned int offset; | |
2025 | { | |
2026 | unw_rec_list *ptr = alloc_record (rnat_sprel); | |
542d6675 | 2027 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2028 | return ptr; |
2029 | } | |
2030 | ||
2031 | static unw_rec_list * | |
e0c9811a JW |
2032 | output_unwabi (abi, context) |
2033 | unsigned long abi; | |
2034 | unsigned long context; | |
800eeca4 | 2035 | { |
e0c9811a JW |
2036 | unw_rec_list *ptr = alloc_record (unwabi); |
2037 | ptr->r.record.p.abi = abi; | |
2038 | ptr->r.record.p.context = context; | |
800eeca4 JW |
2039 | return ptr; |
2040 | } | |
2041 | ||
2042 | static unw_rec_list * | |
e0c9811a | 2043 | output_epilogue (unsigned long ecount) |
800eeca4 | 2044 | { |
e0c9811a JW |
2045 | unw_rec_list *ptr = alloc_record (epilogue); |
2046 | ptr->r.record.b.ecount = ecount; | |
800eeca4 JW |
2047 | return ptr; |
2048 | } | |
2049 | ||
2050 | static unw_rec_list * | |
e0c9811a | 2051 | output_label_state (unsigned long label) |
800eeca4 | 2052 | { |
e0c9811a JW |
2053 | unw_rec_list *ptr = alloc_record (label_state); |
2054 | ptr->r.record.b.label = label; | |
800eeca4 JW |
2055 | return ptr; |
2056 | } | |
2057 | ||
2058 | static unw_rec_list * | |
e0c9811a JW |
2059 | output_copy_state (unsigned long label) |
2060 | { | |
2061 | unw_rec_list *ptr = alloc_record (copy_state); | |
2062 | ptr->r.record.b.label = label; | |
2063 | return ptr; | |
2064 | } | |
2065 | ||
2066 | static unw_rec_list * | |
2067 | output_spill_psprel (ab, reg, offset) | |
2068 | unsigned int ab; | |
800eeca4 JW |
2069 | unsigned int reg; |
2070 | unsigned int offset; | |
2071 | { | |
2072 | unw_rec_list *ptr = alloc_record (spill_psprel); | |
e0c9811a | 2073 | ptr->r.record.x.ab = ab; |
800eeca4 | 2074 | ptr->r.record.x.reg = reg; |
542d6675 | 2075 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2076 | return ptr; |
2077 | } | |
2078 | ||
2079 | static unw_rec_list * | |
e0c9811a JW |
2080 | output_spill_sprel (ab, reg, offset) |
2081 | unsigned int ab; | |
800eeca4 JW |
2082 | unsigned int reg; |
2083 | unsigned int offset; | |
2084 | { | |
2085 | unw_rec_list *ptr = alloc_record (spill_sprel); | |
e0c9811a | 2086 | ptr->r.record.x.ab = ab; |
800eeca4 | 2087 | ptr->r.record.x.reg = reg; |
542d6675 | 2088 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2089 | return ptr; |
2090 | } | |
2091 | ||
2092 | static unw_rec_list * | |
e0c9811a JW |
2093 | output_spill_psprel_p (ab, reg, offset, predicate) |
2094 | unsigned int ab; | |
800eeca4 JW |
2095 | unsigned int reg; |
2096 | unsigned int offset; | |
2097 | unsigned int predicate; | |
2098 | { | |
2099 | unw_rec_list *ptr = alloc_record (spill_psprel_p); | |
e0c9811a | 2100 | ptr->r.record.x.ab = ab; |
800eeca4 | 2101 | ptr->r.record.x.reg = reg; |
542d6675 | 2102 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2103 | ptr->r.record.x.qp = predicate; |
2104 | return ptr; | |
2105 | } | |
2106 | ||
2107 | static unw_rec_list * | |
e0c9811a JW |
2108 | output_spill_sprel_p (ab, reg, offset, predicate) |
2109 | unsigned int ab; | |
800eeca4 JW |
2110 | unsigned int reg; |
2111 | unsigned int offset; | |
2112 | unsigned int predicate; | |
2113 | { | |
2114 | unw_rec_list *ptr = alloc_record (spill_sprel_p); | |
e0c9811a | 2115 | ptr->r.record.x.ab = ab; |
800eeca4 | 2116 | ptr->r.record.x.reg = reg; |
542d6675 | 2117 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2118 | ptr->r.record.x.qp = predicate; |
2119 | return ptr; | |
2120 | } | |
2121 | ||
2122 | static unw_rec_list * | |
e0c9811a JW |
2123 | output_spill_reg (ab, reg, targ_reg, xy) |
2124 | unsigned int ab; | |
800eeca4 JW |
2125 | unsigned int reg; |
2126 | unsigned int targ_reg; | |
2127 | unsigned int xy; | |
2128 | { | |
2129 | unw_rec_list *ptr = alloc_record (spill_reg); | |
e0c9811a | 2130 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2131 | ptr->r.record.x.reg = reg; |
2132 | ptr->r.record.x.treg = targ_reg; | |
2133 | ptr->r.record.x.xy = xy; | |
2134 | return ptr; | |
2135 | } | |
2136 | ||
2137 | static unw_rec_list * | |
e0c9811a JW |
2138 | output_spill_reg_p (ab, reg, targ_reg, xy, predicate) |
2139 | unsigned int ab; | |
800eeca4 JW |
2140 | unsigned int reg; |
2141 | unsigned int targ_reg; | |
2142 | unsigned int xy; | |
2143 | unsigned int predicate; | |
2144 | { | |
2145 | unw_rec_list *ptr = alloc_record (spill_reg_p); | |
e0c9811a | 2146 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2147 | ptr->r.record.x.reg = reg; |
2148 | ptr->r.record.x.treg = targ_reg; | |
2149 | ptr->r.record.x.xy = xy; | |
2150 | ptr->r.record.x.qp = predicate; | |
2151 | return ptr; | |
2152 | } | |
2153 | ||
197865e8 | 2154 | /* Given a unw_rec_list process the correct format with the |
800eeca4 | 2155 | specified function. */ |
542d6675 | 2156 | |
800eeca4 JW |
2157 | static void |
2158 | process_one_record (ptr, f) | |
2159 | unw_rec_list *ptr; | |
2160 | vbyte_func f; | |
2161 | { | |
e0c9811a JW |
2162 | unsigned long fr_mask, gr_mask; |
2163 | ||
197865e8 | 2164 | switch (ptr->r.type) |
800eeca4 | 2165 | { |
542d6675 KH |
2166 | case gr_mem: |
2167 | case fr_mem: | |
2168 | case br_mem: | |
2169 | case frgr_mem: | |
2170 | /* These are taken care of by prologue/prologue_gr. */ | |
2171 | break; | |
e0c9811a | 2172 | |
542d6675 KH |
2173 | case prologue_gr: |
2174 | case prologue: | |
2175 | if (ptr->r.type == prologue_gr) | |
2176 | output_R2_format (f, ptr->r.record.r.grmask, | |
2177 | ptr->r.record.r.grsave, ptr->r.record.r.rlen); | |
2178 | else | |
800eeca4 | 2179 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
542d6675 KH |
2180 | |
2181 | /* Output descriptor(s) for union of register spills (if any). */ | |
2182 | gr_mask = ptr->r.record.r.mask.gr_mem; | |
2183 | fr_mask = ptr->r.record.r.mask.fr_mem; | |
2184 | if (fr_mask) | |
2185 | { | |
2186 | if ((fr_mask & ~0xfUL) == 0) | |
2187 | output_P6_format (f, fr_mem, fr_mask); | |
2188 | else | |
2189 | { | |
2190 | output_P5_format (f, gr_mask, fr_mask); | |
2191 | gr_mask = 0; | |
2192 | } | |
2193 | } | |
2194 | if (gr_mask) | |
2195 | output_P6_format (f, gr_mem, gr_mask); | |
2196 | if (ptr->r.record.r.mask.br_mem) | |
2197 | output_P1_format (f, ptr->r.record.r.mask.br_mem); | |
2198 | ||
2199 | /* output imask descriptor if necessary: */ | |
2200 | if (ptr->r.record.r.mask.i) | |
2201 | output_P4_format (f, ptr->r.record.r.mask.i, | |
2202 | ptr->r.record.r.imask_size); | |
2203 | break; | |
2204 | ||
2205 | case body: | |
2206 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); | |
2207 | break; | |
2208 | case mem_stack_f: | |
2209 | case mem_stack_v: | |
2210 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, | |
2211 | ptr->r.record.p.size); | |
2212 | break; | |
2213 | case psp_gr: | |
2214 | case rp_gr: | |
2215 | case pfs_gr: | |
2216 | case preds_gr: | |
2217 | case unat_gr: | |
2218 | case lc_gr: | |
2219 | case fpsr_gr: | |
2220 | case priunat_gr: | |
2221 | case bsp_gr: | |
2222 | case bspstore_gr: | |
2223 | case rnat_gr: | |
2224 | output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); | |
2225 | break; | |
2226 | case rp_br: | |
2227 | output_P3_format (f, rp_br, ptr->r.record.p.br); | |
2228 | break; | |
2229 | case psp_sprel: | |
2230 | output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); | |
2231 | break; | |
2232 | case rp_when: | |
2233 | case pfs_when: | |
2234 | case preds_when: | |
2235 | case unat_when: | |
2236 | case lc_when: | |
2237 | case fpsr_when: | |
2238 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); | |
2239 | break; | |
2240 | case rp_psprel: | |
2241 | case pfs_psprel: | |
2242 | case preds_psprel: | |
2243 | case unat_psprel: | |
2244 | case lc_psprel: | |
2245 | case fpsr_psprel: | |
2246 | case spill_base: | |
2247 | output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); | |
2248 | break; | |
2249 | case rp_sprel: | |
2250 | case pfs_sprel: | |
2251 | case preds_sprel: | |
2252 | case unat_sprel: | |
2253 | case lc_sprel: | |
2254 | case fpsr_sprel: | |
2255 | case priunat_sprel: | |
2256 | case bsp_sprel: | |
2257 | case bspstore_sprel: | |
2258 | case rnat_sprel: | |
2259 | output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); | |
2260 | break; | |
2261 | case gr_gr: | |
2262 | output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); | |
2263 | break; | |
2264 | case br_gr: | |
2265 | output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); | |
2266 | break; | |
2267 | case spill_mask: | |
2268 | as_bad ("spill_mask record unimplemented."); | |
2269 | break; | |
2270 | case priunat_when_gr: | |
2271 | case priunat_when_mem: | |
2272 | case bsp_when: | |
2273 | case bspstore_when: | |
2274 | case rnat_when: | |
2275 | output_P8_format (f, ptr->r.type, ptr->r.record.p.t); | |
2276 | break; | |
2277 | case priunat_psprel: | |
2278 | case bsp_psprel: | |
2279 | case bspstore_psprel: | |
2280 | case rnat_psprel: | |
2281 | output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); | |
2282 | break; | |
2283 | case unwabi: | |
2284 | output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); | |
2285 | break; | |
2286 | case epilogue: | |
2287 | output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); | |
2288 | break; | |
2289 | case label_state: | |
2290 | case copy_state: | |
2291 | output_B4_format (f, ptr->r.type, ptr->r.record.b.label); | |
2292 | break; | |
2293 | case spill_psprel: | |
2294 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2295 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2296 | ptr->r.record.x.pspoff); | |
2297 | break; | |
2298 | case spill_sprel: | |
2299 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2300 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2301 | ptr->r.record.x.spoff); | |
2302 | break; | |
2303 | case spill_reg: | |
2304 | output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2305 | ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, | |
2306 | ptr->r.record.x.treg, ptr->r.record.x.t); | |
2307 | break; | |
2308 | case spill_psprel_p: | |
2309 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2310 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2311 | ptr->r.record.x.t, ptr->r.record.x.pspoff); | |
2312 | break; | |
2313 | case spill_sprel_p: | |
2314 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2315 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2316 | ptr->r.record.x.t, ptr->r.record.x.spoff); | |
2317 | break; | |
2318 | case spill_reg_p: | |
2319 | output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, | |
2320 | ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, | |
2321 | ptr->r.record.x.xy, ptr->r.record.x.treg, | |
2322 | ptr->r.record.x.t); | |
2323 | break; | |
2324 | default: | |
2325 | as_bad ("record_type_not_valid"); | |
2326 | break; | |
800eeca4 JW |
2327 | } |
2328 | } | |
2329 | ||
197865e8 | 2330 | /* Given a unw_rec_list list, process all the records with |
800eeca4 JW |
2331 | the specified function. */ |
2332 | static void | |
2333 | process_unw_records (list, f) | |
2334 | unw_rec_list *list; | |
2335 | vbyte_func f; | |
2336 | { | |
2337 | unw_rec_list *ptr; | |
2338 | for (ptr = list; ptr; ptr = ptr->next) | |
2339 | process_one_record (ptr, f); | |
2340 | } | |
2341 | ||
2342 | /* Determine the size of a record list in bytes. */ | |
2343 | static int | |
2344 | calc_record_size (list) | |
2345 | unw_rec_list *list; | |
2346 | { | |
2347 | vbyte_count = 0; | |
2348 | process_unw_records (list, count_output); | |
2349 | return vbyte_count; | |
2350 | } | |
2351 | ||
e0c9811a JW |
2352 | /* Update IMASK bitmask to reflect the fact that one or more registers |
2353 | of type TYPE are saved starting at instruction with index T. If N | |
2354 | bits are set in REGMASK, it is assumed that instructions T through | |
2355 | T+N-1 save these registers. | |
2356 | ||
2357 | TYPE values: | |
2358 | 0: no save | |
2359 | 1: instruction saves next fp reg | |
2360 | 2: instruction saves next general reg | |
2361 | 3: instruction saves next branch reg */ | |
2362 | static void | |
2363 | set_imask (region, regmask, t, type) | |
2364 | unw_rec_list *region; | |
2365 | unsigned long regmask; | |
2366 | unsigned long t; | |
2367 | unsigned int type; | |
2368 | { | |
2369 | unsigned char *imask; | |
2370 | unsigned long imask_size; | |
2371 | unsigned int i; | |
2372 | int pos; | |
2373 | ||
2374 | imask = region->r.record.r.mask.i; | |
2375 | imask_size = region->r.record.r.imask_size; | |
2376 | if (!imask) | |
2377 | { | |
542d6675 | 2378 | imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; |
e0c9811a JW |
2379 | imask = xmalloc (imask_size); |
2380 | memset (imask, 0, imask_size); | |
2381 | ||
2382 | region->r.record.r.imask_size = imask_size; | |
2383 | region->r.record.r.mask.i = imask; | |
2384 | } | |
2385 | ||
542d6675 KH |
2386 | i = (t / 4) + 1; |
2387 | pos = 2 * (3 - t % 4); | |
e0c9811a JW |
2388 | while (regmask) |
2389 | { | |
2390 | if (i >= imask_size) | |
2391 | { | |
2392 | as_bad ("Ignoring attempt to spill beyond end of region"); | |
2393 | return; | |
2394 | } | |
2395 | ||
2396 | imask[i] |= (type & 0x3) << pos; | |
197865e8 | 2397 | |
e0c9811a JW |
2398 | regmask &= (regmask - 1); |
2399 | pos -= 2; | |
2400 | if (pos < 0) | |
2401 | { | |
2402 | pos = 0; | |
2403 | ++i; | |
2404 | } | |
2405 | } | |
2406 | } | |
2407 | ||
2408 | static int | |
2409 | count_bits (unsigned long mask) | |
2410 | { | |
2411 | int n = 0; | |
2412 | ||
2413 | while (mask) | |
2414 | { | |
2415 | mask &= mask - 1; | |
2416 | ++n; | |
2417 | } | |
2418 | return n; | |
2419 | } | |
2420 | ||
f5a30c2e JW |
2421 | /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. |
2422 | SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag | |
2423 | containing FIRST_ADDR. */ | |
2424 | ||
e0c9811a | 2425 | unsigned long |
f5a30c2e JW |
2426 | slot_index (slot_addr, slot_frag, first_addr, first_frag) |
2427 | unsigned long slot_addr; | |
2428 | fragS *slot_frag; | |
2429 | unsigned long first_addr; | |
2430 | fragS *first_frag; | |
e0c9811a | 2431 | { |
f5a30c2e JW |
2432 | unsigned long index = 0; |
2433 | ||
2434 | /* First time we are called, the initial address and frag are invalid. */ | |
2435 | if (first_addr == 0) | |
2436 | return 0; | |
2437 | ||
2438 | /* If the two addresses are in different frags, then we need to add in | |
2439 | the remaining size of this frag, and then the entire size of intermediate | |
2440 | frags. */ | |
2441 | while (slot_frag != first_frag) | |
2442 | { | |
2443 | unsigned long start_addr = (unsigned long) &first_frag->fr_literal; | |
2444 | ||
2445 | /* Add in the full size of the frag converted to instruction slots. */ | |
2446 | index += 3 * (first_frag->fr_fix >> 4); | |
2447 | /* Subtract away the initial part before first_addr. */ | |
2448 | index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) | |
2449 | + ((first_addr & 0x3) - (start_addr & 0x3))); | |
e0c9811a | 2450 | |
f5a30c2e JW |
2451 | /* Move to the beginning of the next frag. */ |
2452 | first_frag = first_frag->fr_next; | |
2453 | first_addr = (unsigned long) &first_frag->fr_literal; | |
2454 | } | |
2455 | ||
2456 | /* Add in the used part of the last frag. */ | |
2457 | index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) | |
2458 | + ((slot_addr & 0x3) - (first_addr & 0x3))); | |
2459 | return index; | |
2460 | } | |
2461 | ||
800eeca4 JW |
2462 | /* Given a complete record list, process any records which have |
2463 | unresolved fields, (ie length counts for a prologue). After | |
197865e8 | 2464 | this has been run, all neccessary information should be available |
800eeca4 | 2465 | within each record to generate an image. */ |
542d6675 | 2466 | |
800eeca4 JW |
2467 | static void |
2468 | fixup_unw_records (list) | |
2469 | unw_rec_list *list; | |
2470 | { | |
e0c9811a JW |
2471 | unw_rec_list *ptr, *region = 0; |
2472 | unsigned long first_addr = 0, rlen = 0, t; | |
f5a30c2e | 2473 | fragS *first_frag = 0; |
e0c9811a | 2474 | |
800eeca4 JW |
2475 | for (ptr = list; ptr; ptr = ptr->next) |
2476 | { | |
2477 | if (ptr->slot_number == SLOT_NUM_NOT_SET) | |
542d6675 | 2478 | as_bad (" Insn slot not set in unwind record."); |
f5a30c2e JW |
2479 | t = slot_index (ptr->slot_number, ptr->slot_frag, |
2480 | first_addr, first_frag); | |
800eeca4 JW |
2481 | switch (ptr->r.type) |
2482 | { | |
542d6675 KH |
2483 | case prologue: |
2484 | case prologue_gr: | |
2485 | case body: | |
2486 | { | |
2487 | unw_rec_list *last; | |
2488 | int size, dir_len = 0; | |
2489 | unsigned long last_addr; | |
f5a30c2e | 2490 | fragS *last_frag; |
542d6675 KH |
2491 | |
2492 | first_addr = ptr->slot_number; | |
f5a30c2e | 2493 | first_frag = ptr->slot_frag; |
542d6675 KH |
2494 | ptr->slot_number = 0; |
2495 | /* Find either the next body/prologue start, or the end of | |
2496 | the list, and determine the size of the region. */ | |
2497 | last_addr = unwind.next_slot_number; | |
f5a30c2e | 2498 | last_frag = unwind.next_slot_frag; |
542d6675 KH |
2499 | for (last = ptr->next; last != NULL; last = last->next) |
2500 | if (last->r.type == prologue || last->r.type == prologue_gr | |
2501 | || last->r.type == body) | |
2502 | { | |
2503 | last_addr = last->slot_number; | |
f5a30c2e | 2504 | last_frag = last->slot_frag; |
542d6675 KH |
2505 | break; |
2506 | } | |
2507 | else if (!last->next) | |
2508 | { | |
2509 | /* In the absence of an explicit .body directive, | |
2510 | the prologue ends after the last instruction | |
2511 | covered by an unwind directive. */ | |
2512 | if (ptr->r.type != body) | |
2513 | { | |
2514 | last_addr = last->slot_number; | |
f5a30c2e | 2515 | last_frag = last->slot_frag; |
542d6675 KH |
2516 | switch (last->r.type) |
2517 | { | |
2518 | case frgr_mem: | |
2519 | dir_len = (count_bits (last->r.record.p.frmask) | |
2520 | + count_bits (last->r.record.p.grmask)); | |
2521 | break; | |
2522 | case fr_mem: | |
2523 | case gr_mem: | |
2524 | dir_len += count_bits (last->r.record.p.rmask); | |
2525 | break; | |
2526 | case br_mem: | |
2527 | case br_gr: | |
2528 | dir_len += count_bits (last->r.record.p.brmask); | |
2529 | break; | |
2530 | case gr_gr: | |
2531 | dir_len += count_bits (last->r.record.p.grmask); | |
2532 | break; | |
2533 | default: | |
2534 | dir_len = 1; | |
2535 | break; | |
2536 | } | |
2537 | } | |
2538 | break; | |
2539 | } | |
f5a30c2e JW |
2540 | size = (slot_index (last_addr, last_frag, first_addr, first_frag) |
2541 | + dir_len); | |
542d6675 KH |
2542 | rlen = ptr->r.record.r.rlen = size; |
2543 | region = ptr; | |
e0c9811a | 2544 | break; |
542d6675 KH |
2545 | } |
2546 | case epilogue: | |
2547 | ptr->r.record.b.t = rlen - 1 - t; | |
2548 | break; | |
e0c9811a | 2549 | |
542d6675 KH |
2550 | case mem_stack_f: |
2551 | case mem_stack_v: | |
2552 | case rp_when: | |
2553 | case pfs_when: | |
2554 | case preds_when: | |
2555 | case unat_when: | |
2556 | case lc_when: | |
2557 | case fpsr_when: | |
2558 | case priunat_when_gr: | |
2559 | case priunat_when_mem: | |
2560 | case bsp_when: | |
2561 | case bspstore_when: | |
2562 | case rnat_when: | |
2563 | ptr->r.record.p.t = t; | |
2564 | break; | |
e0c9811a | 2565 | |
542d6675 KH |
2566 | case spill_reg: |
2567 | case spill_sprel: | |
2568 | case spill_psprel: | |
2569 | case spill_reg_p: | |
2570 | case spill_sprel_p: | |
2571 | case spill_psprel_p: | |
2572 | ptr->r.record.x.t = t; | |
2573 | break; | |
e0c9811a | 2574 | |
542d6675 KH |
2575 | case frgr_mem: |
2576 | if (!region) | |
2577 | { | |
2578 | as_bad ("frgr_mem record before region record!\n"); | |
2579 | return; | |
2580 | } | |
2581 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; | |
2582 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; | |
2583 | set_imask (region, ptr->r.record.p.frmask, t, 1); | |
2584 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2585 | break; | |
2586 | case fr_mem: | |
2587 | if (!region) | |
2588 | { | |
2589 | as_bad ("fr_mem record before region record!\n"); | |
2590 | return; | |
2591 | } | |
2592 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; | |
2593 | set_imask (region, ptr->r.record.p.rmask, t, 1); | |
2594 | break; | |
2595 | case gr_mem: | |
2596 | if (!region) | |
2597 | { | |
2598 | as_bad ("gr_mem record before region record!\n"); | |
2599 | return; | |
2600 | } | |
2601 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; | |
2602 | set_imask (region, ptr->r.record.p.rmask, t, 2); | |
2603 | break; | |
2604 | case br_mem: | |
2605 | if (!region) | |
2606 | { | |
2607 | as_bad ("br_mem record before region record!\n"); | |
2608 | return; | |
2609 | } | |
2610 | region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; | |
2611 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2612 | break; | |
e0c9811a | 2613 | |
542d6675 KH |
2614 | case gr_gr: |
2615 | if (!region) | |
2616 | { | |
2617 | as_bad ("gr_gr record before region record!\n"); | |
2618 | return; | |
2619 | } | |
2620 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2621 | break; | |
2622 | case br_gr: | |
2623 | if (!region) | |
2624 | { | |
2625 | as_bad ("br_gr record before region record!\n"); | |
2626 | return; | |
2627 | } | |
2628 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2629 | break; | |
e0c9811a | 2630 | |
542d6675 KH |
2631 | default: |
2632 | break; | |
800eeca4 JW |
2633 | } |
2634 | } | |
2635 | } | |
2636 | ||
2637 | /* Generate an unwind image from a record list. Returns the number of | |
2638 | bytes in the resulting image. The memory image itselof is returned | |
2639 | in the 'ptr' parameter. */ | |
2640 | static int | |
2641 | output_unw_records (list, ptr) | |
2642 | unw_rec_list *list; | |
2643 | void **ptr; | |
2644 | { | |
2645 | int size, x, extra = 0; | |
2646 | unsigned char *mem; | |
2647 | ||
2648 | fixup_unw_records (list); | |
2649 | size = calc_record_size (list); | |
2650 | ||
2651 | /* pad to 8 byte boundry. */ | |
2652 | x = size % 8; | |
2653 | if (x != 0) | |
2654 | extra = 8 - x; | |
2655 | /* Add 8 for the header + 8 more bytes for the personality offset. */ | |
2656 | mem = xmalloc (size + extra + 16); | |
2657 | ||
2658 | vbyte_mem_ptr = mem + 8; | |
2659 | /* Clear the padding area and personality. */ | |
2660 | memset (mem + 8 + size, 0 , extra + 8); | |
2661 | /* Initialize the header area. */ | |
efcc5914 JW |
2662 | md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */ |
2663 | | (unwind.personality_routine | |
2664 | ? ((bfd_vma) 3 << 32) /* U & E handler flags */ | |
2665 | : 0) | |
e4c58b25 JW |
2666 | | ((size + extra) / 8)), /* length (dwords) */ |
2667 | 8); | |
800eeca4 JW |
2668 | |
2669 | process_unw_records (list, output_vbyte_mem); | |
2670 | ||
2671 | *ptr = mem; | |
2672 | return size + extra + 16; | |
2673 | } | |
2674 | ||
e0c9811a JW |
2675 | static int |
2676 | convert_expr_to_ab_reg (e, ab, regp) | |
2677 | expressionS *e; | |
2678 | unsigned int *ab; | |
2679 | unsigned int *regp; | |
2680 | { | |
2681 | unsigned int reg; | |
2682 | ||
2683 | if (e->X_op != O_register) | |
2684 | return 0; | |
2685 | ||
2686 | reg = e->X_add_number; | |
2687 | if (reg >= REG_GR + 4 && reg <= REG_GR + 7) | |
2688 | { | |
2689 | *ab = 0; | |
2690 | *regp = reg - REG_GR; | |
2691 | } | |
2692 | else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5) | |
2693 | || (reg >= REG_FR + 16 && reg <= REG_FR + 31)) | |
2694 | { | |
2695 | *ab = 1; | |
2696 | *regp = reg - REG_FR; | |
2697 | } | |
2698 | else if (reg >= REG_BR + 1 && reg <= REG_BR + 5) | |
2699 | { | |
2700 | *ab = 2; | |
2701 | *regp = reg - REG_BR; | |
2702 | } | |
2703 | else | |
2704 | { | |
2705 | *ab = 3; | |
2706 | switch (reg) | |
2707 | { | |
2708 | case REG_PR: *regp = 0; break; | |
2709 | case REG_PSP: *regp = 1; break; | |
2710 | case REG_PRIUNAT: *regp = 2; break; | |
2711 | case REG_BR + 0: *regp = 3; break; | |
2712 | case REG_AR + AR_BSP: *regp = 4; break; | |
2713 | case REG_AR + AR_BSPSTORE: *regp = 5; break; | |
2714 | case REG_AR + AR_RNAT: *regp = 6; break; | |
2715 | case REG_AR + AR_UNAT: *regp = 7; break; | |
2716 | case REG_AR + AR_FPSR: *regp = 8; break; | |
2717 | case REG_AR + AR_PFS: *regp = 9; break; | |
2718 | case REG_AR + AR_LC: *regp = 10; break; | |
2719 | ||
2720 | default: | |
2721 | return 0; | |
2722 | } | |
2723 | } | |
2724 | return 1; | |
197865e8 | 2725 | } |
e0c9811a JW |
2726 | |
2727 | static int | |
2728 | convert_expr_to_xy_reg (e, xy, regp) | |
2729 | expressionS *e; | |
2730 | unsigned int *xy; | |
2731 | unsigned int *regp; | |
2732 | { | |
2733 | unsigned int reg; | |
2734 | ||
2735 | if (e->X_op != O_register) | |
2736 | return 0; | |
2737 | ||
2738 | reg = e->X_add_number; | |
2739 | ||
2740 | if (reg >= REG_GR && reg <= REG_GR + 127) | |
2741 | { | |
2742 | *xy = 0; | |
2743 | *regp = reg - REG_GR; | |
2744 | } | |
2745 | else if (reg >= REG_FR && reg <= REG_FR + 127) | |
2746 | { | |
2747 | *xy = 1; | |
2748 | *regp = reg - REG_FR; | |
2749 | } | |
2750 | else if (reg >= REG_BR && reg <= REG_BR + 7) | |
2751 | { | |
2752 | *xy = 2; | |
2753 | *regp = reg - REG_BR; | |
2754 | } | |
2755 | else | |
2756 | return -1; | |
2757 | return 1; | |
197865e8 | 2758 | } |
e0c9811a | 2759 | |
800eeca4 JW |
2760 | static void |
2761 | dot_radix (dummy) | |
2762 | int dummy; | |
2763 | { | |
2764 | int radix; | |
2765 | ||
2766 | SKIP_WHITESPACE (); | |
2767 | radix = *input_line_pointer++; | |
2768 | ||
2769 | if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) | |
2770 | { | |
2771 | as_bad ("Radix `%c' unsupported", *input_line_pointer); | |
542d6675 | 2772 | ignore_rest_of_line (); |
800eeca4 JW |
2773 | return; |
2774 | } | |
2775 | } | |
2776 | ||
2777 | /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ | |
2778 | static void | |
2779 | dot_special_section (which) | |
2780 | int which; | |
2781 | { | |
2782 | set_section ((char *) special_section_name[which]); | |
2783 | } | |
2784 | ||
2785 | static void | |
2786 | add_unwind_entry (ptr) | |
2787 | unw_rec_list *ptr; | |
2788 | { | |
e0c9811a JW |
2789 | if (unwind.tail) |
2790 | unwind.tail->next = ptr; | |
800eeca4 | 2791 | else |
e0c9811a JW |
2792 | unwind.list = ptr; |
2793 | unwind.tail = ptr; | |
800eeca4 JW |
2794 | |
2795 | /* The current entry can in fact be a chain of unwind entries. */ | |
e0c9811a JW |
2796 | if (unwind.current_entry == NULL) |
2797 | unwind.current_entry = ptr; | |
800eeca4 JW |
2798 | } |
2799 | ||
197865e8 | 2800 | static void |
800eeca4 JW |
2801 | dot_fframe (dummy) |
2802 | int dummy; | |
2803 | { | |
2804 | expressionS e; | |
e0c9811a | 2805 | |
800eeca4 | 2806 | parse_operand (&e); |
197865e8 | 2807 | |
800eeca4 JW |
2808 | if (e.X_op != O_constant) |
2809 | as_bad ("Operand to .fframe must be a constant"); | |
2810 | else | |
e0c9811a JW |
2811 | add_unwind_entry (output_mem_stack_f (e.X_add_number)); |
2812 | } | |
2813 | ||
197865e8 | 2814 | static void |
e0c9811a JW |
2815 | dot_vframe (dummy) |
2816 | int dummy; | |
2817 | { | |
2818 | expressionS e; | |
2819 | unsigned reg; | |
2820 | ||
2821 | parse_operand (&e); | |
2822 | reg = e.X_add_number - REG_GR; | |
2823 | if (e.X_op == O_register && reg < 128) | |
800eeca4 | 2824 | { |
e0c9811a | 2825 | add_unwind_entry (output_mem_stack_v ()); |
30d25259 RH |
2826 | if (! (unwind.prologue_mask & 2)) |
2827 | add_unwind_entry (output_psp_gr (reg)); | |
800eeca4 | 2828 | } |
e0c9811a JW |
2829 | else |
2830 | as_bad ("First operand to .vframe must be a general register"); | |
800eeca4 JW |
2831 | } |
2832 | ||
197865e8 | 2833 | static void |
e0c9811a | 2834 | dot_vframesp (dummy) |
800eeca4 JW |
2835 | int dummy; |
2836 | { | |
e0c9811a JW |
2837 | expressionS e; |
2838 | ||
2839 | parse_operand (&e); | |
2840 | if (e.X_op == O_constant) | |
2841 | { | |
2842 | add_unwind_entry (output_mem_stack_v ()); | |
2843 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
2844 | } | |
2845 | else | |
2846 | as_bad ("First operand to .vframesp must be a general register"); | |
2847 | } | |
2848 | ||
197865e8 | 2849 | static void |
e0c9811a JW |
2850 | dot_vframepsp (dummy) |
2851 | int dummy; | |
2852 | { | |
2853 | expressionS e; | |
2854 | ||
2855 | parse_operand (&e); | |
2856 | if (e.X_op == O_constant) | |
2857 | { | |
2858 | add_unwind_entry (output_mem_stack_v ()); | |
2859 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
2860 | } | |
2861 | else | |
2862 | as_bad ("First operand to .vframepsp must be a general register"); | |
800eeca4 JW |
2863 | } |
2864 | ||
197865e8 | 2865 | static void |
800eeca4 JW |
2866 | dot_save (dummy) |
2867 | int dummy; | |
2868 | { | |
2869 | expressionS e1, e2; | |
2870 | int sep; | |
2871 | int reg1, reg2; | |
2872 | ||
2873 | sep = parse_operand (&e1); | |
2874 | if (sep != ',') | |
2875 | as_bad ("No second operand to .save"); | |
2876 | sep = parse_operand (&e2); | |
2877 | ||
e0c9811a | 2878 | reg1 = e1.X_add_number; |
800eeca4 | 2879 | reg2 = e2.X_add_number - REG_GR; |
197865e8 | 2880 | |
800eeca4 | 2881 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 2882 | if (e1.X_op == O_register) |
800eeca4 | 2883 | { |
542d6675 | 2884 | if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) |
800eeca4 JW |
2885 | { |
2886 | switch (reg1) | |
2887 | { | |
542d6675 KH |
2888 | case REG_AR + AR_BSP: |
2889 | add_unwind_entry (output_bsp_when ()); | |
2890 | add_unwind_entry (output_bsp_gr (reg2)); | |
2891 | break; | |
2892 | case REG_AR + AR_BSPSTORE: | |
2893 | add_unwind_entry (output_bspstore_when ()); | |
2894 | add_unwind_entry (output_bspstore_gr (reg2)); | |
2895 | break; | |
2896 | case REG_AR + AR_RNAT: | |
2897 | add_unwind_entry (output_rnat_when ()); | |
2898 | add_unwind_entry (output_rnat_gr (reg2)); | |
2899 | break; | |
2900 | case REG_AR + AR_UNAT: | |
2901 | add_unwind_entry (output_unat_when ()); | |
2902 | add_unwind_entry (output_unat_gr (reg2)); | |
2903 | break; | |
2904 | case REG_AR + AR_FPSR: | |
2905 | add_unwind_entry (output_fpsr_when ()); | |
2906 | add_unwind_entry (output_fpsr_gr (reg2)); | |
2907 | break; | |
2908 | case REG_AR + AR_PFS: | |
2909 | add_unwind_entry (output_pfs_when ()); | |
2910 | if (! (unwind.prologue_mask & 4)) | |
2911 | add_unwind_entry (output_pfs_gr (reg2)); | |
2912 | break; | |
2913 | case REG_AR + AR_LC: | |
2914 | add_unwind_entry (output_lc_when ()); | |
2915 | add_unwind_entry (output_lc_gr (reg2)); | |
2916 | break; | |
2917 | case REG_BR: | |
2918 | add_unwind_entry (output_rp_when ()); | |
2919 | if (! (unwind.prologue_mask & 8)) | |
2920 | add_unwind_entry (output_rp_gr (reg2)); | |
2921 | break; | |
2922 | case REG_PR: | |
2923 | add_unwind_entry (output_preds_when ()); | |
2924 | if (! (unwind.prologue_mask & 1)) | |
2925 | add_unwind_entry (output_preds_gr (reg2)); | |
2926 | break; | |
2927 | case REG_PRIUNAT: | |
2928 | add_unwind_entry (output_priunat_when_gr ()); | |
2929 | add_unwind_entry (output_priunat_gr (reg2)); | |
2930 | break; | |
2931 | default: | |
2932 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
2933 | } |
2934 | } | |
2935 | else | |
2936 | as_bad (" Second operand not a valid register"); | |
2937 | } | |
2938 | else | |
e0c9811a | 2939 | as_bad ("First operand not a register"); |
800eeca4 JW |
2940 | } |
2941 | ||
197865e8 | 2942 | static void |
800eeca4 JW |
2943 | dot_restore (dummy) |
2944 | int dummy; | |
2945 | { | |
e0c9811a JW |
2946 | expressionS e1, e2; |
2947 | unsigned long ecount = 0; | |
2948 | int sep; | |
2949 | ||
2950 | sep = parse_operand (&e1); | |
2951 | if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) | |
2952 | { | |
2953 | as_bad ("First operand to .restore must be stack pointer (sp)"); | |
2954 | return; | |
2955 | } | |
2956 | ||
2957 | if (sep == ',') | |
2958 | { | |
2959 | parse_operand (&e2); | |
2960 | if (e1.X_op != O_constant) | |
2961 | { | |
2962 | as_bad ("Second operand to .restore must be constant"); | |
2963 | return; | |
2964 | } | |
2965 | ecount = e1.X_op; | |
2966 | } | |
2967 | add_unwind_entry (output_epilogue (ecount)); | |
2968 | } | |
2969 | ||
197865e8 | 2970 | static void |
e0c9811a JW |
2971 | dot_restorereg (dummy) |
2972 | int dummy; | |
2973 | { | |
2974 | unsigned int ab, reg; | |
2975 | expressionS e; | |
2976 | ||
2977 | parse_operand (&e); | |
2978 | ||
2979 | if (!convert_expr_to_ab_reg (&e, &ab, ®)) | |
2980 | { | |
2981 | as_bad ("First operand to .restorereg must be a preserved register"); | |
2982 | return; | |
2983 | } | |
2984 | add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); | |
2985 | } | |
2986 | ||
197865e8 | 2987 | static void |
e0c9811a JW |
2988 | dot_restorereg_p (dummy) |
2989 | int dummy; | |
2990 | { | |
2991 | unsigned int qp, ab, reg; | |
2992 | expressionS e1, e2; | |
2993 | int sep; | |
2994 | ||
2995 | sep = parse_operand (&e1); | |
2996 | if (sep != ',') | |
2997 | { | |
2998 | as_bad ("No second operand to .restorereg.p"); | |
2999 | return; | |
3000 | } | |
3001 | ||
3002 | parse_operand (&e2); | |
3003 | ||
3004 | qp = e1.X_add_number - REG_P; | |
3005 | if (e1.X_op != O_register || qp > 63) | |
3006 | { | |
3007 | as_bad ("First operand to .restorereg.p must be a predicate"); | |
3008 | return; | |
3009 | } | |
3010 | ||
3011 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3012 | { | |
3013 | as_bad ("Second operand to .restorereg.p must be a preserved register"); | |
3014 | return; | |
3015 | } | |
3016 | add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); | |
800eeca4 JW |
3017 | } |
3018 | ||
3019 | static int | |
3020 | generate_unwind_image () | |
3021 | { | |
3022 | int size; | |
3023 | unsigned char *unw_rec; | |
800eeca4 | 3024 | |
10850f29 JW |
3025 | /* Force out pending instructions, to make sure all unwind records have |
3026 | a valid slot_number field. */ | |
3027 | ia64_flush_insns (); | |
3028 | ||
800eeca4 | 3029 | /* Generate the unwind record. */ |
150f24a2 | 3030 | size = output_unw_records (unwind.list, (void **) &unw_rec); |
e0c9811a JW |
3031 | if (size % 8 != 0) |
3032 | as_bad ("Unwind record is not a multiple of 8 bytes."); | |
800eeca4 JW |
3033 | |
3034 | /* If there are unwind records, switch sections, and output the info. */ | |
3035 | if (size != 0) | |
3036 | { | |
800eeca4 | 3037 | unsigned char *where; |
800eeca4 | 3038 | expressionS exp; |
800eeca4 JW |
3039 | set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]); |
3040 | ||
3041 | /* Set expression which points to start of unwind descriptor area. */ | |
e0c9811a | 3042 | unwind.info = expr_build_dot (); |
800eeca4 | 3043 | |
542d6675 | 3044 | where = (unsigned char *) frag_more (size); |
800eeca4 JW |
3045 | |
3046 | /* Issue a label for this address, and keep track of it to put it | |
3047 | in the unwind section. */ | |
3048 | ||
3049 | /* Copy the information from the unwind record into this section. The | |
3050 | data is already in the correct byte order. */ | |
3051 | memcpy (where, unw_rec, size); | |
3052 | /* Add the personality address to the image. */ | |
e0c9811a | 3053 | if (unwind.personality_routine != 0) |
542d6675 | 3054 | { |
800eeca4 | 3055 | exp.X_op = O_symbol; |
e0c9811a | 3056 | exp.X_add_symbol = unwind.personality_routine; |
800eeca4 JW |
3057 | exp.X_add_number = 0; |
3058 | fix_new_exp (frag_now, frag_now_fix () - 8, 8, | |
3059 | &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB); | |
e0c9811a | 3060 | unwind.personality_routine = 0; |
542d6675 | 3061 | } |
800eeca4 JW |
3062 | obj_elf_previous (0); |
3063 | } | |
3064 | ||
e0c9811a JW |
3065 | free_list_records (unwind.list); |
3066 | unwind.list = unwind.tail = unwind.current_entry = NULL; | |
800eeca4 JW |
3067 | |
3068 | return size; | |
3069 | } | |
3070 | ||
197865e8 | 3071 | static void |
542d6675 | 3072 | dot_handlerdata (dummy) |
800eeca4 JW |
3073 | int dummy; |
3074 | { | |
3075 | generate_unwind_image (); | |
e0c9811a | 3076 | demand_empty_rest_of_line (); |
800eeca4 JW |
3077 | } |
3078 | ||
197865e8 | 3079 | static void |
800eeca4 JW |
3080 | dot_unwentry (dummy) |
3081 | int dummy; | |
3082 | { | |
e0c9811a | 3083 | demand_empty_rest_of_line (); |
800eeca4 JW |
3084 | } |
3085 | ||
197865e8 | 3086 | static void |
800eeca4 JW |
3087 | dot_altrp (dummy) |
3088 | int dummy; | |
3089 | { | |
e0c9811a JW |
3090 | expressionS e; |
3091 | unsigned reg; | |
3092 | ||
3093 | parse_operand (&e); | |
3094 | reg = e.X_add_number - REG_BR; | |
3095 | if (e.X_op == O_register && reg < 8) | |
3096 | add_unwind_entry (output_rp_br (reg)); | |
3097 | else | |
3098 | as_bad ("First operand not a valid branch register"); | |
800eeca4 JW |
3099 | } |
3100 | ||
197865e8 | 3101 | static void |
e0c9811a JW |
3102 | dot_savemem (psprel) |
3103 | int psprel; | |
800eeca4 JW |
3104 | { |
3105 | expressionS e1, e2; | |
3106 | int sep; | |
3107 | int reg1, val; | |
3108 | ||
3109 | sep = parse_operand (&e1); | |
3110 | if (sep != ',') | |
e0c9811a | 3111 | as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); |
800eeca4 JW |
3112 | sep = parse_operand (&e2); |
3113 | ||
e0c9811a | 3114 | reg1 = e1.X_add_number; |
800eeca4 | 3115 | val = e2.X_add_number; |
197865e8 | 3116 | |
800eeca4 | 3117 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 3118 | if (e1.X_op == O_register) |
800eeca4 JW |
3119 | { |
3120 | if (e2.X_op == O_constant) | |
3121 | { | |
3122 | switch (reg1) | |
3123 | { | |
542d6675 KH |
3124 | case REG_AR + AR_BSP: |
3125 | add_unwind_entry (output_bsp_when ()); | |
3126 | add_unwind_entry ((psprel | |
3127 | ? output_bsp_psprel | |
3128 | : output_bsp_sprel) (val)); | |
3129 | break; | |
3130 | case REG_AR + AR_BSPSTORE: | |
3131 | add_unwind_entry (output_bspstore_when ()); | |
3132 | add_unwind_entry ((psprel | |
3133 | ? output_bspstore_psprel | |
3134 | : output_bspstore_sprel) (val)); | |
3135 | break; | |
3136 | case REG_AR + AR_RNAT: | |
3137 | add_unwind_entry (output_rnat_when ()); | |
3138 | add_unwind_entry ((psprel | |
3139 | ? output_rnat_psprel | |
3140 | : output_rnat_sprel) (val)); | |
3141 | break; | |
3142 | case REG_AR + AR_UNAT: | |
3143 | add_unwind_entry (output_unat_when ()); | |
3144 | add_unwind_entry ((psprel | |
3145 | ? output_unat_psprel | |
3146 | : output_unat_sprel) (val)); | |
3147 | break; | |
3148 | case REG_AR + AR_FPSR: | |
3149 | add_unwind_entry (output_fpsr_when ()); | |
3150 | add_unwind_entry ((psprel | |
3151 | ? output_fpsr_psprel | |
3152 | : output_fpsr_sprel) (val)); | |
3153 | break; | |
3154 | case REG_AR + AR_PFS: | |
3155 | add_unwind_entry (output_pfs_when ()); | |
3156 | add_unwind_entry ((psprel | |
3157 | ? output_pfs_psprel | |
3158 | : output_pfs_sprel) (val)); | |
3159 | break; | |
3160 | case REG_AR + AR_LC: | |
3161 | add_unwind_entry (output_lc_when ()); | |
3162 | add_unwind_entry ((psprel | |
3163 | ? output_lc_psprel | |
3164 | : output_lc_sprel) (val)); | |
3165 | break; | |
3166 | case REG_BR: | |
3167 | add_unwind_entry (output_rp_when ()); | |
3168 | add_unwind_entry ((psprel | |
3169 | ? output_rp_psprel | |
3170 | : output_rp_sprel) (val)); | |
3171 | break; | |
3172 | case REG_PR: | |
3173 | add_unwind_entry (output_preds_when ()); | |
3174 | add_unwind_entry ((psprel | |
3175 | ? output_preds_psprel | |
3176 | : output_preds_sprel) (val)); | |
3177 | break; | |
3178 | case REG_PRIUNAT: | |
3179 | add_unwind_entry (output_priunat_when_mem ()); | |
3180 | add_unwind_entry ((psprel | |
3181 | ? output_priunat_psprel | |
3182 | : output_priunat_sprel) (val)); | |
3183 | break; | |
3184 | default: | |
3185 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
3186 | } |
3187 | } | |
3188 | else | |
3189 | as_bad (" Second operand not a valid constant"); | |
3190 | } | |
3191 | else | |
e0c9811a | 3192 | as_bad ("First operand not a register"); |
800eeca4 JW |
3193 | } |
3194 | ||
197865e8 | 3195 | static void |
800eeca4 JW |
3196 | dot_saveg (dummy) |
3197 | int dummy; | |
3198 | { | |
3199 | expressionS e1, e2; | |
3200 | int sep; | |
3201 | sep = parse_operand (&e1); | |
3202 | if (sep == ',') | |
3203 | parse_operand (&e2); | |
197865e8 | 3204 | |
800eeca4 JW |
3205 | if (e1.X_op != O_constant) |
3206 | as_bad ("First operand to .save.g must be a constant."); | |
3207 | else | |
3208 | { | |
3209 | int grmask = e1.X_add_number; | |
3210 | if (sep != ',') | |
3211 | add_unwind_entry (output_gr_mem (grmask)); | |
3212 | else | |
542d6675 | 3213 | { |
800eeca4 | 3214 | int reg = e2.X_add_number - REG_GR; |
542d6675 | 3215 | if (e2.X_op == O_register && reg >= 0 && reg < 128) |
800eeca4 JW |
3216 | add_unwind_entry (output_gr_gr (grmask, reg)); |
3217 | else | |
3218 | as_bad ("Second operand is an invalid register."); | |
3219 | } | |
3220 | } | |
3221 | } | |
3222 | ||
197865e8 | 3223 | static void |
800eeca4 JW |
3224 | dot_savef (dummy) |
3225 | int dummy; | |
3226 | { | |
e0c9811a | 3227 | expressionS e1; |
800eeca4 JW |
3228 | int sep; |
3229 | sep = parse_operand (&e1); | |
197865e8 | 3230 | |
800eeca4 JW |
3231 | if (e1.X_op != O_constant) |
3232 | as_bad ("Operand to .save.f must be a constant."); | |
3233 | else | |
e0c9811a | 3234 | add_unwind_entry (output_fr_mem (e1.X_add_number)); |
800eeca4 JW |
3235 | } |
3236 | ||
197865e8 | 3237 | static void |
800eeca4 JW |
3238 | dot_saveb (dummy) |
3239 | int dummy; | |
3240 | { | |
e0c9811a JW |
3241 | expressionS e1, e2; |
3242 | unsigned int reg; | |
3243 | unsigned char sep; | |
3244 | int brmask; | |
3245 | ||
800eeca4 | 3246 | sep = parse_operand (&e1); |
800eeca4 | 3247 | if (e1.X_op != O_constant) |
800eeca4 | 3248 | { |
e0c9811a JW |
3249 | as_bad ("First operand to .save.b must be a constant."); |
3250 | return; | |
800eeca4 | 3251 | } |
e0c9811a JW |
3252 | brmask = e1.X_add_number; |
3253 | ||
3254 | if (sep == ',') | |
3255 | { | |
3256 | sep = parse_operand (&e2); | |
3257 | reg = e2.X_add_number - REG_GR; | |
3258 | if (e2.X_op != O_register || reg > 127) | |
3259 | { | |
3260 | as_bad ("Second operand to .save.b must be a general register."); | |
3261 | return; | |
3262 | } | |
3263 | add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); | |
3264 | } | |
3265 | else | |
3266 | add_unwind_entry (output_br_mem (brmask)); | |
3267 | ||
3268 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3269 | ignore_rest_of_line (); | |
800eeca4 JW |
3270 | } |
3271 | ||
197865e8 | 3272 | static void |
800eeca4 JW |
3273 | dot_savegf (dummy) |
3274 | int dummy; | |
3275 | { | |
3276 | expressionS e1, e2; | |
3277 | int sep; | |
3278 | sep = parse_operand (&e1); | |
3279 | if (sep == ',') | |
3280 | parse_operand (&e2); | |
197865e8 | 3281 | |
800eeca4 JW |
3282 | if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) |
3283 | as_bad ("Both operands of .save.gf must be constants."); | |
3284 | else | |
3285 | { | |
3286 | int grmask = e1.X_add_number; | |
3287 | int frmask = e2.X_add_number; | |
3288 | add_unwind_entry (output_frgr_mem (grmask, frmask)); | |
3289 | } | |
3290 | } | |
3291 | ||
197865e8 | 3292 | static void |
800eeca4 JW |
3293 | dot_spill (dummy) |
3294 | int dummy; | |
3295 | { | |
3296 | expressionS e; | |
e0c9811a JW |
3297 | unsigned char sep; |
3298 | ||
3299 | sep = parse_operand (&e); | |
3300 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3301 | ignore_rest_of_line (); | |
197865e8 | 3302 | |
800eeca4 JW |
3303 | if (e.X_op != O_constant) |
3304 | as_bad ("Operand to .spill must be a constant"); | |
3305 | else | |
e0c9811a JW |
3306 | add_unwind_entry (output_spill_base (e.X_add_number)); |
3307 | } | |
3308 | ||
3309 | static void | |
3310 | dot_spillreg (dummy) | |
3311 | int dummy; | |
3312 | { | |
3313 | int sep, ab, xy, reg, treg; | |
3314 | expressionS e1, e2; | |
3315 | ||
3316 | sep = parse_operand (&e1); | |
3317 | if (sep != ',') | |
3318 | { | |
3319 | as_bad ("No second operand to .spillreg"); | |
3320 | return; | |
3321 | } | |
3322 | ||
3323 | parse_operand (&e2); | |
3324 | ||
3325 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
800eeca4 | 3326 | { |
e0c9811a JW |
3327 | as_bad ("First operand to .spillreg must be a preserved register"); |
3328 | return; | |
800eeca4 | 3329 | } |
e0c9811a JW |
3330 | |
3331 | if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) | |
3332 | { | |
3333 | as_bad ("Second operand to .spillreg must be a register"); | |
3334 | return; | |
3335 | } | |
3336 | ||
3337 | add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); | |
3338 | } | |
3339 | ||
3340 | static void | |
3341 | dot_spillmem (psprel) | |
3342 | int psprel; | |
3343 | { | |
3344 | expressionS e1, e2; | |
3345 | int sep, ab, reg; | |
3346 | ||
3347 | sep = parse_operand (&e1); | |
3348 | if (sep != ',') | |
3349 | { | |
3350 | as_bad ("Second operand missing"); | |
3351 | return; | |
3352 | } | |
3353 | ||
3354 | parse_operand (&e2); | |
3355 | ||
3356 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
3357 | { | |
3358 | as_bad ("First operand to .spill%s must be a preserved register", | |
3359 | psprel ? "psp" : "sp"); | |
3360 | return; | |
3361 | } | |
3362 | ||
3363 | if (e2.X_op != O_constant) | |
3364 | { | |
3365 | as_bad ("Second operand to .spill%s must be a constant", | |
3366 | psprel ? "psp" : "sp"); | |
3367 | return; | |
3368 | } | |
3369 | ||
3370 | if (psprel) | |
3371 | add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); | |
3372 | else | |
3373 | add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); | |
3374 | } | |
3375 | ||
3376 | static void | |
3377 | dot_spillreg_p (dummy) | |
3378 | int dummy; | |
3379 | { | |
3380 | int sep, ab, xy, reg, treg; | |
3381 | expressionS e1, e2, e3; | |
3382 | unsigned int qp; | |
3383 | ||
3384 | sep = parse_operand (&e1); | |
3385 | if (sep != ',') | |
3386 | { | |
3387 | as_bad ("No second and third operand to .spillreg.p"); | |
3388 | return; | |
3389 | } | |
3390 | ||
3391 | sep = parse_operand (&e2); | |
3392 | if (sep != ',') | |
3393 | { | |
3394 | as_bad ("No third operand to .spillreg.p"); | |
3395 | return; | |
3396 | } | |
3397 | ||
3398 | parse_operand (&e3); | |
3399 | ||
3400 | qp = e1.X_add_number - REG_P; | |
3401 | ||
3402 | if (e1.X_op != O_register || qp > 63) | |
3403 | { | |
3404 | as_bad ("First operand to .spillreg.p must be a predicate"); | |
3405 | return; | |
3406 | } | |
3407 | ||
3408 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3409 | { | |
3410 | as_bad ("Second operand to .spillreg.p must be a preserved register"); | |
3411 | return; | |
3412 | } | |
3413 | ||
3414 | if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) | |
3415 | { | |
3416 | as_bad ("Third operand to .spillreg.p must be a register"); | |
3417 | return; | |
3418 | } | |
3419 | ||
3420 | add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); | |
3421 | } | |
3422 | ||
3423 | static void | |
3424 | dot_spillmem_p (psprel) | |
3425 | int psprel; | |
3426 | { | |
3427 | expressionS e1, e2, e3; | |
3428 | int sep, ab, reg; | |
3429 | unsigned int qp; | |
3430 | ||
3431 | sep = parse_operand (&e1); | |
3432 | if (sep != ',') | |
3433 | { | |
3434 | as_bad ("Second operand missing"); | |
3435 | return; | |
3436 | } | |
3437 | ||
3438 | parse_operand (&e2); | |
3439 | if (sep != ',') | |
3440 | { | |
3441 | as_bad ("Second operand missing"); | |
3442 | return; | |
3443 | } | |
3444 | ||
3445 | parse_operand (&e3); | |
3446 | ||
3447 | qp = e1.X_add_number - REG_P; | |
3448 | if (e1.X_op != O_register || qp > 63) | |
3449 | { | |
3450 | as_bad ("First operand to .spill%s_p must be a predicate", | |
3451 | psprel ? "psp" : "sp"); | |
3452 | return; | |
3453 | } | |
3454 | ||
3455 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3456 | { | |
3457 | as_bad ("Second operand to .spill%s_p must be a preserved register", | |
3458 | psprel ? "psp" : "sp"); | |
3459 | return; | |
3460 | } | |
3461 | ||
3462 | if (e3.X_op != O_constant) | |
3463 | { | |
3464 | as_bad ("Third operand to .spill%s_p must be a constant", | |
3465 | psprel ? "psp" : "sp"); | |
3466 | return; | |
3467 | } | |
3468 | ||
3469 | if (psprel) | |
3470 | add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number)); | |
3471 | else | |
3472 | add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number)); | |
3473 | } | |
3474 | ||
3475 | static void | |
3476 | dot_label_state (dummy) | |
3477 | int dummy; | |
3478 | { | |
3479 | expressionS e; | |
3480 | ||
3481 | parse_operand (&e); | |
3482 | if (e.X_op != O_constant) | |
3483 | { | |
3484 | as_bad ("Operand to .label_state must be a constant"); | |
3485 | return; | |
3486 | } | |
3487 | add_unwind_entry (output_label_state (e.X_add_number)); | |
3488 | } | |
3489 | ||
3490 | static void | |
3491 | dot_copy_state (dummy) | |
3492 | int dummy; | |
3493 | { | |
3494 | expressionS e; | |
3495 | ||
3496 | parse_operand (&e); | |
3497 | if (e.X_op != O_constant) | |
3498 | { | |
3499 | as_bad ("Operand to .copy_state must be a constant"); | |
3500 | return; | |
3501 | } | |
3502 | add_unwind_entry (output_copy_state (e.X_add_number)); | |
800eeca4 JW |
3503 | } |
3504 | ||
197865e8 | 3505 | static void |
800eeca4 JW |
3506 | dot_unwabi (dummy) |
3507 | int dummy; | |
3508 | { | |
e0c9811a JW |
3509 | expressionS e1, e2; |
3510 | unsigned char sep; | |
3511 | ||
3512 | sep = parse_operand (&e1); | |
3513 | if (sep != ',') | |
3514 | { | |
3515 | as_bad ("Second operand to .unwabi missing"); | |
3516 | return; | |
3517 | } | |
3518 | sep = parse_operand (&e2); | |
3519 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3520 | ignore_rest_of_line (); | |
3521 | ||
3522 | if (e1.X_op != O_constant) | |
3523 | { | |
3524 | as_bad ("First operand to .unwabi must be a constant"); | |
3525 | return; | |
3526 | } | |
3527 | ||
3528 | if (e2.X_op != O_constant) | |
3529 | { | |
3530 | as_bad ("Second operand to .unwabi must be a constant"); | |
3531 | return; | |
3532 | } | |
3533 | ||
3534 | add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); | |
800eeca4 JW |
3535 | } |
3536 | ||
197865e8 | 3537 | static void |
800eeca4 JW |
3538 | dot_personality (dummy) |
3539 | int dummy; | |
3540 | { | |
3541 | char *name, *p, c; | |
3542 | SKIP_WHITESPACE (); | |
3543 | name = input_line_pointer; | |
3544 | c = get_symbol_end (); | |
3545 | p = input_line_pointer; | |
e0c9811a | 3546 | unwind.personality_routine = symbol_find_or_make (name); |
800eeca4 JW |
3547 | *p = c; |
3548 | SKIP_WHITESPACE (); | |
3549 | demand_empty_rest_of_line (); | |
3550 | } | |
3551 | ||
3552 | static void | |
3553 | dot_proc (dummy) | |
3554 | int dummy; | |
3555 | { | |
3556 | char *name, *p, c; | |
3557 | symbolS *sym; | |
3558 | ||
e0c9811a JW |
3559 | unwind.proc_start = expr_build_dot (); |
3560 | /* Parse names of main and alternate entry points and mark them as | |
542d6675 | 3561 | function symbols: */ |
800eeca4 JW |
3562 | while (1) |
3563 | { | |
3564 | SKIP_WHITESPACE (); | |
3565 | name = input_line_pointer; | |
3566 | c = get_symbol_end (); | |
3567 | p = input_line_pointer; | |
3568 | sym = symbol_find_or_make (name); | |
e0c9811a | 3569 | if (unwind.proc_start == 0) |
542d6675 | 3570 | { |
e0c9811a | 3571 | unwind.proc_start = sym; |
800eeca4 JW |
3572 | } |
3573 | symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; | |
3574 | *p = c; | |
3575 | SKIP_WHITESPACE (); | |
3576 | if (*input_line_pointer != ',') | |
3577 | break; | |
3578 | ++input_line_pointer; | |
3579 | } | |
3580 | demand_empty_rest_of_line (); | |
3581 | ia64_do_align (16); | |
3582 | ||
e0c9811a JW |
3583 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
3584 | unwind.personality_routine = 0; | |
800eeca4 JW |
3585 | } |
3586 | ||
3587 | static void | |
3588 | dot_body (dummy) | |
3589 | int dummy; | |
3590 | { | |
e0c9811a | 3591 | unwind.prologue = 0; |
30d25259 RH |
3592 | unwind.prologue_mask = 0; |
3593 | ||
800eeca4 | 3594 | add_unwind_entry (output_body ()); |
e0c9811a | 3595 | demand_empty_rest_of_line (); |
800eeca4 JW |
3596 | } |
3597 | ||
3598 | static void | |
3599 | dot_prologue (dummy) | |
3600 | int dummy; | |
3601 | { | |
e0c9811a | 3602 | unsigned char sep; |
30d25259 | 3603 | int mask = 0, grsave; |
e0c9811a | 3604 | |
e0c9811a | 3605 | if (!is_it_end_of_statement ()) |
800eeca4 JW |
3606 | { |
3607 | expressionS e1, e2; | |
800eeca4 JW |
3608 | sep = parse_operand (&e1); |
3609 | if (sep != ',') | |
3610 | as_bad ("No second operand to .prologue"); | |
3611 | sep = parse_operand (&e2); | |
e0c9811a | 3612 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
542d6675 | 3613 | ignore_rest_of_line (); |
800eeca4 JW |
3614 | |
3615 | if (e1.X_op == O_constant) | |
542d6675 | 3616 | { |
30d25259 RH |
3617 | mask = e1.X_add_number; |
3618 | ||
800eeca4 | 3619 | if (e2.X_op == O_constant) |
30d25259 RH |
3620 | grsave = e2.X_add_number; |
3621 | else if (e2.X_op == O_register | |
3622 | && (grsave = e2.X_add_number - REG_GR) < 128) | |
3623 | ; | |
800eeca4 | 3624 | else |
30d25259 RH |
3625 | as_bad ("Second operand not a constant or general register"); |
3626 | ||
3627 | add_unwind_entry (output_prologue_gr (mask, grsave)); | |
800eeca4 JW |
3628 | } |
3629 | else | |
3630 | as_bad ("First operand not a constant"); | |
3631 | } | |
3632 | else | |
3633 | add_unwind_entry (output_prologue ()); | |
30d25259 RH |
3634 | |
3635 | unwind.prologue = 1; | |
3636 | unwind.prologue_mask = mask; | |
800eeca4 JW |
3637 | } |
3638 | ||
3639 | static void | |
3640 | dot_endp (dummy) | |
3641 | int dummy; | |
3642 | { | |
3643 | expressionS e; | |
3644 | unsigned char *ptr; | |
44f5c83a | 3645 | int bytes_per_address; |
800eeca4 JW |
3646 | long where; |
3647 | segT saved_seg; | |
3648 | subsegT saved_subseg; | |
3649 | ||
3650 | saved_seg = now_seg; | |
3651 | saved_subseg = now_subseg; | |
3652 | ||
3653 | expression (&e); | |
3654 | demand_empty_rest_of_line (); | |
3655 | ||
3656 | insn_group_break (1, 0, 0); | |
800eeca4 JW |
3657 | |
3658 | /* If there was a .handlerdata, we haven't generated an image yet. */ | |
e0c9811a | 3659 | if (unwind.info == 0) |
800eeca4 JW |
3660 | { |
3661 | generate_unwind_image (); | |
3662 | } | |
3663 | ||
3664 | subseg_set (md.last_text_seg, 0); | |
e0c9811a | 3665 | unwind.proc_end = expr_build_dot (); |
800eeca4 JW |
3666 | |
3667 | set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]); | |
3668 | ptr = frag_more (24); | |
3669 | where = frag_now_fix () - 24; | |
44f5c83a | 3670 | bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; |
800eeca4 JW |
3671 | |
3672 | /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ | |
3673 | e.X_op = O_pseudo_fixup; | |
3674 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3675 | e.X_add_number = 0; | |
e0c9811a | 3676 | e.X_add_symbol = unwind.proc_start; |
44f5c83a | 3677 | ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); |
800eeca4 JW |
3678 | |
3679 | e.X_op = O_pseudo_fixup; | |
3680 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3681 | e.X_add_number = 0; | |
e0c9811a | 3682 | e.X_add_symbol = unwind.proc_end; |
44f5c83a | 3683 | ia64_cons_fix_new (frag_now, where + bytes_per_address, bytes_per_address, &e); |
800eeca4 | 3684 | |
e0c9811a | 3685 | if (unwind.info != 0) |
800eeca4 JW |
3686 | { |
3687 | e.X_op = O_pseudo_fixup; | |
3688 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
3689 | e.X_add_number = 0; | |
e0c9811a | 3690 | e.X_add_symbol = unwind.info; |
44f5c83a | 3691 | ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), bytes_per_address, &e); |
800eeca4 JW |
3692 | } |
3693 | else | |
44f5c83a | 3694 | md_number_to_chars (ptr + (bytes_per_address * 2), 0, bytes_per_address); |
800eeca4 JW |
3695 | |
3696 | subseg_set (saved_seg, saved_subseg); | |
e0c9811a | 3697 | unwind.proc_start = unwind.proc_end = unwind.info = 0; |
800eeca4 JW |
3698 | } |
3699 | ||
3700 | static void | |
3701 | dot_template (template) | |
3702 | int template; | |
3703 | { | |
3704 | CURR_SLOT.user_template = template; | |
3705 | } | |
3706 | ||
3707 | static void | |
3708 | dot_regstk (dummy) | |
3709 | int dummy; | |
3710 | { | |
3711 | int ins, locs, outs, rots; | |
3712 | ||
3713 | if (is_it_end_of_statement ()) | |
3714 | ins = locs = outs = rots = 0; | |
3715 | else | |
3716 | { | |
3717 | ins = get_absolute_expression (); | |
3718 | if (*input_line_pointer++ != ',') | |
3719 | goto err; | |
3720 | locs = get_absolute_expression (); | |
3721 | if (*input_line_pointer++ != ',') | |
3722 | goto err; | |
3723 | outs = get_absolute_expression (); | |
3724 | if (*input_line_pointer++ != ',') | |
3725 | goto err; | |
3726 | rots = get_absolute_expression (); | |
3727 | } | |
3728 | set_regstack (ins, locs, outs, rots); | |
3729 | return; | |
3730 | ||
3731 | err: | |
3732 | as_bad ("Comma expected"); | |
3733 | ignore_rest_of_line (); | |
3734 | } | |
3735 | ||
3736 | static void | |
3737 | dot_rot (type) | |
3738 | int type; | |
3739 | { | |
3740 | unsigned num_regs, num_alloced = 0; | |
3741 | struct dynreg **drpp, *dr; | |
3742 | int ch, base_reg = 0; | |
3743 | char *name, *start; | |
3744 | size_t len; | |
3745 | ||
3746 | switch (type) | |
3747 | { | |
3748 | case DYNREG_GR: base_reg = REG_GR + 32; break; | |
3749 | case DYNREG_FR: base_reg = REG_FR + 32; break; | |
3750 | case DYNREG_PR: base_reg = REG_P + 16; break; | |
3751 | default: break; | |
3752 | } | |
3753 | ||
542d6675 | 3754 | /* First, remove existing names from hash table. */ |
800eeca4 JW |
3755 | for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) |
3756 | { | |
3757 | hash_delete (md.dynreg_hash, dr->name); | |
3758 | dr->num_regs = 0; | |
3759 | } | |
3760 | ||
3761 | drpp = &md.dynreg[type]; | |
3762 | while (1) | |
3763 | { | |
3764 | start = input_line_pointer; | |
3765 | ch = get_symbol_end (); | |
3766 | *input_line_pointer = ch; | |
3767 | len = (input_line_pointer - start); | |
3768 | ||
3769 | SKIP_WHITESPACE (); | |
3770 | if (*input_line_pointer != '[') | |
3771 | { | |
3772 | as_bad ("Expected '['"); | |
3773 | goto err; | |
3774 | } | |
3775 | ++input_line_pointer; /* skip '[' */ | |
3776 | ||
3777 | num_regs = get_absolute_expression (); | |
3778 | ||
3779 | if (*input_line_pointer++ != ']') | |
3780 | { | |
3781 | as_bad ("Expected ']'"); | |
3782 | goto err; | |
3783 | } | |
3784 | SKIP_WHITESPACE (); | |
3785 | ||
3786 | num_alloced += num_regs; | |
3787 | switch (type) | |
3788 | { | |
3789 | case DYNREG_GR: | |
3790 | if (num_alloced > md.rot.num_regs) | |
3791 | { | |
3792 | as_bad ("Used more than the declared %d rotating registers", | |
3793 | md.rot.num_regs); | |
3794 | goto err; | |
3795 | } | |
3796 | break; | |
3797 | case DYNREG_FR: | |
3798 | if (num_alloced > 96) | |
3799 | { | |
3800 | as_bad ("Used more than the available 96 rotating registers"); | |
3801 | goto err; | |
3802 | } | |
3803 | break; | |
3804 | case DYNREG_PR: | |
3805 | if (num_alloced > 48) | |
3806 | { | |
3807 | as_bad ("Used more than the available 48 rotating registers"); | |
3808 | goto err; | |
3809 | } | |
3810 | break; | |
3811 | ||
3812 | default: | |
3813 | break; | |
3814 | } | |
3815 | ||
3816 | name = obstack_alloc (¬es, len + 1); | |
3817 | memcpy (name, start, len); | |
3818 | name[len] = '\0'; | |
3819 | ||
3820 | if (!*drpp) | |
3821 | { | |
3822 | *drpp = obstack_alloc (¬es, sizeof (*dr)); | |
3823 | memset (*drpp, 0, sizeof (*dr)); | |
3824 | } | |
3825 | ||
3826 | dr = *drpp; | |
3827 | dr->name = name; | |
3828 | dr->num_regs = num_regs; | |
3829 | dr->base = base_reg; | |
3830 | drpp = &dr->next; | |
3831 | base_reg += num_regs; | |
3832 | ||
3833 | if (hash_insert (md.dynreg_hash, name, dr)) | |
3834 | { | |
3835 | as_bad ("Attempt to redefine register set `%s'", name); | |
3836 | goto err; | |
3837 | } | |
3838 | ||
3839 | if (*input_line_pointer != ',') | |
3840 | break; | |
3841 | ++input_line_pointer; /* skip comma */ | |
3842 | SKIP_WHITESPACE (); | |
3843 | } | |
3844 | demand_empty_rest_of_line (); | |
3845 | return; | |
3846 | ||
3847 | err: | |
3848 | ignore_rest_of_line (); | |
3849 | } | |
3850 | ||
3851 | static void | |
3852 | dot_byteorder (byteorder) | |
3853 | int byteorder; | |
3854 | { | |
3855 | target_big_endian = byteorder; | |
3856 | } | |
3857 | ||
3858 | static void | |
3859 | dot_psr (dummy) | |
3860 | int dummy; | |
3861 | { | |
3862 | char *option; | |
3863 | int ch; | |
3864 | ||
3865 | while (1) | |
3866 | { | |
3867 | option = input_line_pointer; | |
3868 | ch = get_symbol_end (); | |
3869 | if (strcmp (option, "lsb") == 0) | |
3870 | md.flags &= ~EF_IA_64_BE; | |
3871 | else if (strcmp (option, "msb") == 0) | |
3872 | md.flags |= EF_IA_64_BE; | |
3873 | else if (strcmp (option, "abi32") == 0) | |
3874 | md.flags &= ~EF_IA_64_ABI64; | |
3875 | else if (strcmp (option, "abi64") == 0) | |
3876 | md.flags |= EF_IA_64_ABI64; | |
3877 | else | |
3878 | as_bad ("Unknown psr option `%s'", option); | |
3879 | *input_line_pointer = ch; | |
3880 | ||
3881 | SKIP_WHITESPACE (); | |
3882 | if (*input_line_pointer != ',') | |
3883 | break; | |
3884 | ||
3885 | ++input_line_pointer; | |
3886 | SKIP_WHITESPACE (); | |
3887 | } | |
3888 | demand_empty_rest_of_line (); | |
3889 | } | |
3890 | ||
3891 | static void | |
3892 | dot_alias (dummy) | |
3893 | int dummy; | |
3894 | { | |
3895 | as_bad (".alias not implemented yet"); | |
3896 | } | |
3897 | ||
3898 | static void | |
3899 | dot_ln (dummy) | |
3900 | int dummy; | |
3901 | { | |
3902 | new_logical_line (0, get_absolute_expression ()); | |
3903 | demand_empty_rest_of_line (); | |
3904 | } | |
3905 | ||
542d6675 | 3906 | static char * |
800eeca4 JW |
3907 | parse_section_name () |
3908 | { | |
3909 | char *name; | |
3910 | int len; | |
3911 | ||
3912 | SKIP_WHITESPACE (); | |
3913 | if (*input_line_pointer != '"') | |
3914 | { | |
3915 | as_bad ("Missing section name"); | |
3916 | ignore_rest_of_line (); | |
3917 | return 0; | |
3918 | } | |
3919 | name = demand_copy_C_string (&len); | |
3920 | if (!name) | |
3921 | { | |
3922 | ignore_rest_of_line (); | |
3923 | return 0; | |
3924 | } | |
3925 | SKIP_WHITESPACE (); | |
3926 | if (*input_line_pointer != ',') | |
3927 | { | |
3928 | as_bad ("Comma expected after section name"); | |
3929 | ignore_rest_of_line (); | |
3930 | return 0; | |
3931 | } | |
3932 | ++input_line_pointer; /* skip comma */ | |
3933 | return name; | |
3934 | } | |
3935 | ||
3936 | static void | |
3937 | dot_xdata (size) | |
3938 | int size; | |
3939 | { | |
3940 | char *name = parse_section_name (); | |
3941 | if (!name) | |
3942 | return; | |
3943 | ||
3944 | set_section (name); | |
3945 | cons (size); | |
3946 | obj_elf_previous (0); | |
3947 | } | |
3948 | ||
3949 | /* Why doesn't float_cons() call md_cons_align() the way cons() does? */ | |
542d6675 | 3950 | |
800eeca4 JW |
3951 | static void |
3952 | stmt_float_cons (kind) | |
3953 | int kind; | |
3954 | { | |
3955 | size_t size; | |
3956 | ||
3957 | switch (kind) | |
3958 | { | |
3959 | case 'd': size = 8; break; | |
3960 | case 'x': size = 10; break; | |
3961 | ||
3962 | case 'f': | |
3963 | default: | |
3964 | size = 4; | |
3965 | break; | |
3966 | } | |
3967 | ia64_do_align (size); | |
3968 | float_cons (kind); | |
3969 | } | |
3970 | ||
3971 | static void | |
3972 | stmt_cons_ua (size) | |
3973 | int size; | |
3974 | { | |
3975 | int saved_auto_align = md.auto_align; | |
3976 | ||
3977 | md.auto_align = 0; | |
3978 | cons (size); | |
3979 | md.auto_align = saved_auto_align; | |
3980 | } | |
3981 | ||
3982 | static void | |
3983 | dot_xfloat_cons (kind) | |
3984 | int kind; | |
3985 | { | |
3986 | char *name = parse_section_name (); | |
3987 | if (!name) | |
3988 | return; | |
3989 | ||
3990 | set_section (name); | |
3991 | stmt_float_cons (kind); | |
3992 | obj_elf_previous (0); | |
3993 | } | |
3994 | ||
3995 | static void | |
3996 | dot_xstringer (zero) | |
3997 | int zero; | |
3998 | { | |
3999 | char *name = parse_section_name (); | |
4000 | if (!name) | |
4001 | return; | |
4002 | ||
4003 | set_section (name); | |
4004 | stringer (zero); | |
4005 | obj_elf_previous (0); | |
4006 | } | |
4007 | ||
4008 | static void | |
4009 | dot_xdata_ua (size) | |
4010 | int size; | |
4011 | { | |
4012 | int saved_auto_align = md.auto_align; | |
4013 | char *name = parse_section_name (); | |
4014 | if (!name) | |
4015 | return; | |
4016 | ||
4017 | set_section (name); | |
4018 | md.auto_align = 0; | |
4019 | cons (size); | |
4020 | md.auto_align = saved_auto_align; | |
4021 | obj_elf_previous (0); | |
4022 | } | |
4023 | ||
4024 | static void | |
4025 | dot_xfloat_cons_ua (kind) | |
4026 | int kind; | |
4027 | { | |
4028 | int saved_auto_align = md.auto_align; | |
4029 | char *name = parse_section_name (); | |
4030 | if (!name) | |
4031 | return; | |
4032 | ||
4033 | set_section (name); | |
4034 | md.auto_align = 0; | |
4035 | stmt_float_cons (kind); | |
4036 | md.auto_align = saved_auto_align; | |
4037 | obj_elf_previous (0); | |
4038 | } | |
4039 | ||
4040 | /* .reg.val <regname>,value */ | |
542d6675 | 4041 | |
800eeca4 JW |
4042 | static void |
4043 | dot_reg_val (dummy) | |
542d6675 | 4044 | int dummy; |
800eeca4 JW |
4045 | { |
4046 | expressionS reg; | |
4047 | ||
4048 | expression (®); | |
4049 | if (reg.X_op != O_register) | |
4050 | { | |
4051 | as_bad (_("Register name expected")); | |
4052 | ignore_rest_of_line (); | |
4053 | } | |
4054 | else if (*input_line_pointer++ != ',') | |
4055 | { | |
4056 | as_bad (_("Comma expected")); | |
4057 | ignore_rest_of_line (); | |
4058 | } | |
197865e8 | 4059 | else |
800eeca4 JW |
4060 | { |
4061 | valueT value = get_absolute_expression (); | |
4062 | int regno = reg.X_add_number; | |
542d6675 KH |
4063 | if (regno < REG_GR || regno > REG_GR + 128) |
4064 | as_warn (_("Register value annotation ignored")); | |
800eeca4 | 4065 | else |
542d6675 KH |
4066 | { |
4067 | gr_values[regno - REG_GR].known = 1; | |
4068 | gr_values[regno - REG_GR].value = value; | |
4069 | gr_values[regno - REG_GR].path = md.path; | |
4070 | } | |
800eeca4 JW |
4071 | } |
4072 | demand_empty_rest_of_line (); | |
4073 | } | |
4074 | ||
197865e8 | 4075 | /* select dv checking mode |
800eeca4 JW |
4076 | .auto |
4077 | .explicit | |
4078 | .default | |
4079 | ||
197865e8 | 4080 | A stop is inserted when changing modes |
800eeca4 | 4081 | */ |
542d6675 | 4082 | |
800eeca4 JW |
4083 | static void |
4084 | dot_dv_mode (type) | |
542d6675 | 4085 | int type; |
800eeca4 JW |
4086 | { |
4087 | if (md.manual_bundling) | |
4088 | as_warn (_("Directive invalid within a bundle")); | |
4089 | ||
4090 | if (type == 'E' || type == 'A') | |
4091 | md.mode_explicitly_set = 0; | |
4092 | else | |
4093 | md.mode_explicitly_set = 1; | |
4094 | ||
4095 | md.detect_dv = 1; | |
4096 | switch (type) | |
4097 | { | |
4098 | case 'A': | |
4099 | case 'a': | |
4100 | if (md.explicit_mode) | |
542d6675 | 4101 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4102 | md.explicit_mode = 0; |
4103 | break; | |
4104 | case 'E': | |
4105 | case 'e': | |
4106 | if (!md.explicit_mode) | |
542d6675 | 4107 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4108 | md.explicit_mode = 1; |
4109 | break; | |
4110 | default: | |
4111 | case 'd': | |
4112 | if (md.explicit_mode != md.default_explicit_mode) | |
542d6675 | 4113 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4114 | md.explicit_mode = md.default_explicit_mode; |
4115 | md.mode_explicitly_set = 0; | |
4116 | break; | |
4117 | } | |
4118 | } | |
4119 | ||
4120 | static void | |
4121 | print_prmask (mask) | |
542d6675 | 4122 | valueT mask; |
800eeca4 JW |
4123 | { |
4124 | int regno; | |
4125 | char *comma = ""; | |
542d6675 | 4126 | for (regno = 0; regno < 64; regno++) |
800eeca4 | 4127 | { |
542d6675 KH |
4128 | if (mask & ((valueT) 1 << regno)) |
4129 | { | |
4130 | fprintf (stderr, "%s p%d", comma, regno); | |
4131 | comma = ","; | |
4132 | } | |
800eeca4 JW |
4133 | } |
4134 | } | |
4135 | ||
4136 | /* | |
4137 | .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") | |
4138 | .pred.rel.imply p1, p2 (also .pred.rel "imply") | |
4139 | .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") | |
4140 | .pred.safe_across_calls p1 [, p2 [,...]] | |
4141 | */ | |
542d6675 | 4142 | |
800eeca4 JW |
4143 | static void |
4144 | dot_pred_rel (type) | |
542d6675 | 4145 | int type; |
800eeca4 JW |
4146 | { |
4147 | valueT mask = 0; | |
4148 | int count = 0; | |
4149 | int p1 = -1, p2 = -1; | |
4150 | ||
4151 | if (type == 0) | |
4152 | { | |
4153 | if (*input_line_pointer != '"') | |
542d6675 KH |
4154 | { |
4155 | as_bad (_("Missing predicate relation type")); | |
4156 | ignore_rest_of_line (); | |
4157 | return; | |
4158 | } | |
197865e8 | 4159 | else |
542d6675 KH |
4160 | { |
4161 | int len; | |
4162 | char *form = demand_copy_C_string (&len); | |
4163 | if (strcmp (form, "mutex") == 0) | |
4164 | type = 'm'; | |
4165 | else if (strcmp (form, "clear") == 0) | |
4166 | type = 'c'; | |
4167 | else if (strcmp (form, "imply") == 0) | |
4168 | type = 'i'; | |
4169 | else | |
4170 | { | |
4171 | as_bad (_("Unrecognized predicate relation type")); | |
4172 | ignore_rest_of_line (); | |
4173 | return; | |
4174 | } | |
4175 | } | |
800eeca4 | 4176 | if (*input_line_pointer == ',') |
542d6675 | 4177 | ++input_line_pointer; |
800eeca4 JW |
4178 | SKIP_WHITESPACE (); |
4179 | } | |
4180 | ||
4181 | SKIP_WHITESPACE (); | |
4182 | while (1) | |
4183 | { | |
4184 | valueT bit = 1; | |
4185 | int regno; | |
197865e8 | 4186 | |
800eeca4 | 4187 | if (toupper (*input_line_pointer) != 'P' |
542d6675 KH |
4188 | || (regno = atoi (++input_line_pointer)) < 0 |
4189 | || regno > 63) | |
4190 | { | |
4191 | as_bad (_("Predicate register expected")); | |
4192 | ignore_rest_of_line (); | |
4193 | return; | |
4194 | } | |
800eeca4 | 4195 | while (isdigit (*input_line_pointer)) |
542d6675 | 4196 | ++input_line_pointer; |
800eeca4 | 4197 | if (p1 == -1) |
542d6675 | 4198 | p1 = regno; |
800eeca4 | 4199 | else if (p2 == -1) |
542d6675 | 4200 | p2 = regno; |
800eeca4 JW |
4201 | bit <<= regno; |
4202 | if (mask & bit) | |
542d6675 KH |
4203 | as_warn (_("Duplicate predicate register ignored")); |
4204 | mask |= bit; | |
4205 | count++; | |
4206 | /* See if it's a range. */ | |
800eeca4 | 4207 | if (*input_line_pointer == '-') |
542d6675 KH |
4208 | { |
4209 | valueT stop = 1; | |
4210 | ++input_line_pointer; | |
4211 | ||
4212 | if (toupper (*input_line_pointer) != 'P' | |
4213 | || (regno = atoi (++input_line_pointer)) < 0 | |
4214 | || regno > 63) | |
4215 | { | |
4216 | as_bad (_("Predicate register expected")); | |
4217 | ignore_rest_of_line (); | |
4218 | return; | |
4219 | } | |
4220 | while (isdigit (*input_line_pointer)) | |
4221 | ++input_line_pointer; | |
4222 | stop <<= regno; | |
4223 | if (bit >= stop) | |
4224 | { | |
4225 | as_bad (_("Bad register range")); | |
4226 | ignore_rest_of_line (); | |
4227 | return; | |
4228 | } | |
4229 | while (bit < stop) | |
4230 | { | |
4231 | bit <<= 1; | |
4232 | mask |= bit; | |
4233 | count++; | |
4234 | } | |
4235 | SKIP_WHITESPACE (); | |
4236 | } | |
800eeca4 | 4237 | if (*input_line_pointer != ',') |
542d6675 | 4238 | break; |
800eeca4 JW |
4239 | ++input_line_pointer; |
4240 | SKIP_WHITESPACE (); | |
4241 | } | |
4242 | ||
4243 | switch (type) | |
4244 | { | |
4245 | case 'c': | |
4246 | if (count == 0) | |
542d6675 | 4247 | mask = ~(valueT) 0; |
800eeca4 | 4248 | clear_qp_mutex (mask); |
197865e8 | 4249 | clear_qp_implies (mask, (valueT) 0); |
800eeca4 JW |
4250 | break; |
4251 | case 'i': | |
4252 | if (count != 2 || p1 == -1 || p2 == -1) | |
542d6675 | 4253 | as_bad (_("Predicate source and target required")); |
800eeca4 | 4254 | else if (p1 == 0 || p2 == 0) |
542d6675 | 4255 | as_bad (_("Use of p0 is not valid in this context")); |
800eeca4 | 4256 | else |
542d6675 | 4257 | add_qp_imply (p1, p2); |
800eeca4 JW |
4258 | break; |
4259 | case 'm': | |
4260 | if (count < 2) | |
542d6675 KH |
4261 | { |
4262 | as_bad (_("At least two PR arguments expected")); | |
4263 | break; | |
4264 | } | |
800eeca4 | 4265 | else if (mask & 1) |
542d6675 KH |
4266 | { |
4267 | as_bad (_("Use of p0 is not valid in this context")); | |
4268 | break; | |
4269 | } | |
800eeca4 JW |
4270 | add_qp_mutex (mask); |
4271 | break; | |
4272 | case 's': | |
4273 | /* note that we don't override any existing relations */ | |
4274 | if (count == 0) | |
542d6675 KH |
4275 | { |
4276 | as_bad (_("At least one PR argument expected")); | |
4277 | break; | |
4278 | } | |
800eeca4 | 4279 | if (md.debug_dv) |
542d6675 KH |
4280 | { |
4281 | fprintf (stderr, "Safe across calls: "); | |
4282 | print_prmask (mask); | |
4283 | fprintf (stderr, "\n"); | |
4284 | } | |
800eeca4 JW |
4285 | qp_safe_across_calls = mask; |
4286 | break; | |
4287 | } | |
4288 | demand_empty_rest_of_line (); | |
4289 | } | |
4290 | ||
4291 | /* .entry label [, label [, ...]] | |
4292 | Hint to DV code that the given labels are to be considered entry points. | |
542d6675 KH |
4293 | Otherwise, only global labels are considered entry points. */ |
4294 | ||
800eeca4 JW |
4295 | static void |
4296 | dot_entry (dummy) | |
542d6675 | 4297 | int dummy; |
800eeca4 JW |
4298 | { |
4299 | const char *err; | |
4300 | char *name; | |
4301 | int c; | |
4302 | symbolS *symbolP; | |
4303 | ||
4304 | do | |
4305 | { | |
4306 | name = input_line_pointer; | |
4307 | c = get_symbol_end (); | |
4308 | symbolP = symbol_find_or_make (name); | |
4309 | ||
4310 | err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); | |
4311 | if (err) | |
542d6675 KH |
4312 | as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), |
4313 | name, err); | |
800eeca4 JW |
4314 | |
4315 | *input_line_pointer = c; | |
4316 | SKIP_WHITESPACE (); | |
4317 | c = *input_line_pointer; | |
4318 | if (c == ',') | |
4319 | { | |
4320 | input_line_pointer++; | |
4321 | SKIP_WHITESPACE (); | |
4322 | if (*input_line_pointer == '\n') | |
4323 | c = '\n'; | |
4324 | } | |
4325 | } | |
4326 | while (c == ','); | |
4327 | ||
4328 | demand_empty_rest_of_line (); | |
4329 | } | |
4330 | ||
197865e8 | 4331 | /* .mem.offset offset, base |
542d6675 KH |
4332 | "base" is used to distinguish between offsets from a different base. */ |
4333 | ||
800eeca4 JW |
4334 | static void |
4335 | dot_mem_offset (dummy) | |
4336 | int dummy; | |
4337 | { | |
4338 | md.mem_offset.hint = 1; | |
4339 | md.mem_offset.offset = get_absolute_expression (); | |
4340 | if (*input_line_pointer != ',') | |
4341 | { | |
4342 | as_bad (_("Comma expected")); | |
4343 | ignore_rest_of_line (); | |
4344 | return; | |
4345 | } | |
4346 | ++input_line_pointer; | |
4347 | md.mem_offset.base = get_absolute_expression (); | |
4348 | demand_empty_rest_of_line (); | |
4349 | } | |
4350 | ||
542d6675 | 4351 | /* ia64-specific pseudo-ops: */ |
800eeca4 JW |
4352 | const pseudo_typeS md_pseudo_table[] = |
4353 | { | |
4354 | { "radix", dot_radix, 0 }, | |
4355 | { "lcomm", s_lcomm_bytes, 1 }, | |
4356 | { "bss", dot_special_section, SPECIAL_SECTION_BSS }, | |
4357 | { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, | |
4358 | { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, | |
4359 | { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, | |
4360 | { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, | |
4361 | { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, | |
4362 | { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, | |
4363 | { "proc", dot_proc, 0 }, | |
4364 | { "body", dot_body, 0 }, | |
4365 | { "prologue", dot_prologue, 0 }, | |
4366 | { "endp", dot_endp }, | |
4367 | { "file", dwarf2_directive_file }, | |
4368 | { "loc", dwarf2_directive_loc }, | |
4369 | ||
4370 | { "fframe", dot_fframe }, | |
4371 | { "vframe", dot_vframe }, | |
e0c9811a JW |
4372 | { "vframesp", dot_vframesp }, |
4373 | { "vframepsp", dot_vframepsp }, | |
800eeca4 JW |
4374 | { "save", dot_save }, |
4375 | { "restore", dot_restore }, | |
e0c9811a JW |
4376 | { "restorereg", dot_restorereg }, |
4377 | { "restorereg.p", dot_restorereg_p }, | |
800eeca4 JW |
4378 | { "handlerdata", dot_handlerdata }, |
4379 | { "unwentry", dot_unwentry }, | |
e0c9811a JW |
4380 | { "altrp", dot_altrp }, |
4381 | { "savesp", dot_savemem, 0 }, | |
4382 | { "savepsp", dot_savemem, 1 }, | |
800eeca4 JW |
4383 | { "save.g", dot_saveg }, |
4384 | { "save.f", dot_savef }, | |
4385 | { "save.b", dot_saveb }, | |
4386 | { "save.gf", dot_savegf }, | |
4387 | { "spill", dot_spill }, | |
e0c9811a JW |
4388 | { "spillreg", dot_spillreg }, |
4389 | { "spillsp", dot_spillmem, 0 }, | |
4390 | { "spillpsp", dot_spillmem, 1 }, | |
4391 | { "spillreg.p", dot_spillreg_p }, | |
4392 | { "spillsp.p", dot_spillmem_p, 0 }, | |
4393 | { "spillpsp.p", dot_spillmem_p, 1 }, | |
197865e8 KH |
4394 | { "label_state", dot_label_state }, |
4395 | { "copy_state", dot_copy_state }, | |
800eeca4 JW |
4396 | { "unwabi", dot_unwabi }, |
4397 | { "personality", dot_personality }, | |
4398 | #if 0 | |
4399 | { "estate", dot_estate }, | |
4400 | #endif | |
4401 | { "mii", dot_template, 0x0 }, | |
4402 | { "mli", dot_template, 0x2 }, /* old format, for compatibility */ | |
4403 | { "mlx", dot_template, 0x2 }, | |
4404 | { "mmi", dot_template, 0x4 }, | |
4405 | { "mfi", dot_template, 0x6 }, | |
4406 | { "mmf", dot_template, 0x7 }, | |
4407 | { "mib", dot_template, 0x8 }, | |
4408 | { "mbb", dot_template, 0x9 }, | |
4409 | { "bbb", dot_template, 0xb }, | |
4410 | { "mmb", dot_template, 0xc }, | |
4411 | { "mfb", dot_template, 0xe }, | |
4412 | #if 0 | |
4413 | { "lb", dot_scope, 0 }, | |
4414 | { "le", dot_scope, 1 }, | |
4415 | #endif | |
4416 | { "align", s_align_bytes, 0 }, | |
4417 | { "regstk", dot_regstk, 0 }, | |
4418 | { "rotr", dot_rot, DYNREG_GR }, | |
4419 | { "rotf", dot_rot, DYNREG_FR }, | |
4420 | { "rotp", dot_rot, DYNREG_PR }, | |
4421 | { "lsb", dot_byteorder, 0 }, | |
4422 | { "msb", dot_byteorder, 1 }, | |
4423 | { "psr", dot_psr, 0 }, | |
4424 | { "alias", dot_alias, 0 }, | |
4425 | { "ln", dot_ln, 0 }, /* source line info (for debugging) */ | |
4426 | ||
4427 | { "xdata1", dot_xdata, 1 }, | |
4428 | { "xdata2", dot_xdata, 2 }, | |
4429 | { "xdata4", dot_xdata, 4 }, | |
4430 | { "xdata8", dot_xdata, 8 }, | |
4431 | { "xreal4", dot_xfloat_cons, 'f' }, | |
4432 | { "xreal8", dot_xfloat_cons, 'd' }, | |
4433 | { "xreal10", dot_xfloat_cons, 'x' }, | |
4434 | { "xstring", dot_xstringer, 0 }, | |
4435 | { "xstringz", dot_xstringer, 1 }, | |
4436 | ||
542d6675 | 4437 | /* unaligned versions: */ |
800eeca4 JW |
4438 | { "xdata2.ua", dot_xdata_ua, 2 }, |
4439 | { "xdata4.ua", dot_xdata_ua, 4 }, | |
4440 | { "xdata8.ua", dot_xdata_ua, 8 }, | |
4441 | { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, | |
4442 | { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, | |
4443 | { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, | |
4444 | ||
4445 | /* annotations/DV checking support */ | |
4446 | { "entry", dot_entry, 0 }, | |
4447 | { "mem.offset", dot_mem_offset }, | |
4448 | { "pred.rel", dot_pred_rel, 0 }, | |
4449 | { "pred.rel.clear", dot_pred_rel, 'c' }, | |
4450 | { "pred.rel.imply", dot_pred_rel, 'i' }, | |
4451 | { "pred.rel.mutex", dot_pred_rel, 'm' }, | |
4452 | { "pred.safe_across_calls", dot_pred_rel, 's' }, | |
4453 | { "reg.val", dot_reg_val }, | |
4454 | { "auto", dot_dv_mode, 'a' }, | |
4455 | { "explicit", dot_dv_mode, 'e' }, | |
4456 | { "default", dot_dv_mode, 'd' }, | |
4457 | ||
4458 | { NULL, 0, 0 } | |
4459 | }; | |
4460 | ||
4461 | static const struct pseudo_opcode | |
4462 | { | |
4463 | const char *name; | |
4464 | void (*handler) (int); | |
4465 | int arg; | |
4466 | } | |
4467 | pseudo_opcode[] = | |
4468 | { | |
4469 | /* these are more like pseudo-ops, but don't start with a dot */ | |
4470 | { "data1", cons, 1 }, | |
4471 | { "data2", cons, 2 }, | |
4472 | { "data4", cons, 4 }, | |
4473 | { "data8", cons, 8 }, | |
4474 | { "real4", stmt_float_cons, 'f' }, | |
4475 | { "real8", stmt_float_cons, 'd' }, | |
4476 | { "real10", stmt_float_cons, 'x' }, | |
4477 | { "string", stringer, 0 }, | |
4478 | { "stringz", stringer, 1 }, | |
4479 | ||
542d6675 | 4480 | /* unaligned versions: */ |
800eeca4 JW |
4481 | { "data2.ua", stmt_cons_ua, 2 }, |
4482 | { "data4.ua", stmt_cons_ua, 4 }, | |
4483 | { "data8.ua", stmt_cons_ua, 8 }, | |
4484 | { "real4.ua", float_cons, 'f' }, | |
4485 | { "real8.ua", float_cons, 'd' }, | |
4486 | { "real10.ua", float_cons, 'x' }, | |
4487 | }; | |
4488 | ||
4489 | /* Declare a register by creating a symbol for it and entering it in | |
4490 | the symbol table. */ | |
542d6675 KH |
4491 | |
4492 | static symbolS * | |
800eeca4 JW |
4493 | declare_register (name, regnum) |
4494 | const char *name; | |
4495 | int regnum; | |
4496 | { | |
4497 | const char *err; | |
4498 | symbolS *sym; | |
4499 | ||
4500 | sym = symbol_new (name, reg_section, regnum, &zero_address_frag); | |
4501 | ||
4502 | err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); | |
4503 | if (err) | |
4504 | as_fatal ("Inserting \"%s\" into register table failed: %s", | |
4505 | name, err); | |
4506 | ||
4507 | return sym; | |
4508 | } | |
4509 | ||
4510 | static void | |
4511 | declare_register_set (prefix, num_regs, base_regnum) | |
4512 | const char *prefix; | |
4513 | int num_regs; | |
4514 | int base_regnum; | |
4515 | { | |
4516 | char name[8]; | |
4517 | int i; | |
4518 | ||
4519 | for (i = 0; i < num_regs; ++i) | |
4520 | { | |
4521 | sprintf (name, "%s%u", prefix, i); | |
4522 | declare_register (name, base_regnum + i); | |
4523 | } | |
4524 | } | |
4525 | ||
4526 | static unsigned int | |
4527 | operand_width (opnd) | |
4528 | enum ia64_opnd opnd; | |
4529 | { | |
4530 | const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; | |
4531 | unsigned int bits = 0; | |
4532 | int i; | |
4533 | ||
4534 | bits = 0; | |
4535 | for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) | |
4536 | bits += odesc->field[i].bits; | |
4537 | ||
4538 | return bits; | |
4539 | } | |
4540 | ||
4541 | static int | |
4542 | operand_match (idesc, index, e) | |
4543 | const struct ia64_opcode *idesc; | |
4544 | int index; | |
4545 | expressionS *e; | |
4546 | { | |
4547 | enum ia64_opnd opnd = idesc->operands[index]; | |
4548 | int bits, relocatable = 0; | |
4549 | struct insn_fix *fix; | |
4550 | bfd_signed_vma val; | |
4551 | ||
4552 | switch (opnd) | |
4553 | { | |
542d6675 | 4554 | /* constants: */ |
800eeca4 JW |
4555 | |
4556 | case IA64_OPND_AR_CCV: | |
4557 | if (e->X_op == O_register && e->X_add_number == REG_AR + 32) | |
4558 | return 1; | |
4559 | break; | |
4560 | ||
4561 | case IA64_OPND_AR_PFS: | |
4562 | if (e->X_op == O_register && e->X_add_number == REG_AR + 64) | |
4563 | return 1; | |
4564 | break; | |
4565 | ||
4566 | case IA64_OPND_GR0: | |
4567 | if (e->X_op == O_register && e->X_add_number == REG_GR + 0) | |
4568 | return 1; | |
4569 | break; | |
4570 | ||
4571 | case IA64_OPND_IP: | |
4572 | if (e->X_op == O_register && e->X_add_number == REG_IP) | |
4573 | return 1; | |
4574 | break; | |
4575 | ||
4576 | case IA64_OPND_PR: | |
4577 | if (e->X_op == O_register && e->X_add_number == REG_PR) | |
4578 | return 1; | |
4579 | break; | |
4580 | ||
4581 | case IA64_OPND_PR_ROT: | |
4582 | if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) | |
4583 | return 1; | |
4584 | break; | |
4585 | ||
4586 | case IA64_OPND_PSR: | |
4587 | if (e->X_op == O_register && e->X_add_number == REG_PSR) | |
4588 | return 1; | |
4589 | break; | |
4590 | ||
4591 | case IA64_OPND_PSR_L: | |
4592 | if (e->X_op == O_register && e->X_add_number == REG_PSR_L) | |
4593 | return 1; | |
4594 | break; | |
4595 | ||
4596 | case IA64_OPND_PSR_UM: | |
4597 | if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) | |
4598 | return 1; | |
4599 | break; | |
4600 | ||
4601 | case IA64_OPND_C1: | |
4602 | if (e->X_op == O_constant && e->X_add_number == 1) | |
4603 | return 1; | |
4604 | break; | |
4605 | ||
4606 | case IA64_OPND_C8: | |
4607 | if (e->X_op == O_constant && e->X_add_number == 8) | |
4608 | return 1; | |
4609 | break; | |
4610 | ||
4611 | case IA64_OPND_C16: | |
4612 | if (e->X_op == O_constant && e->X_add_number == 16) | |
4613 | return 1; | |
4614 | break; | |
4615 | ||
542d6675 | 4616 | /* register operands: */ |
800eeca4 JW |
4617 | |
4618 | case IA64_OPND_AR3: | |
4619 | if (e->X_op == O_register && e->X_add_number >= REG_AR | |
4620 | && e->X_add_number < REG_AR + 128) | |
4621 | return 1; | |
4622 | break; | |
4623 | ||
4624 | case IA64_OPND_B1: | |
4625 | case IA64_OPND_B2: | |
4626 | if (e->X_op == O_register && e->X_add_number >= REG_BR | |
4627 | && e->X_add_number < REG_BR + 8) | |
4628 | return 1; | |
4629 | break; | |
4630 | ||
4631 | case IA64_OPND_CR3: | |
4632 | if (e->X_op == O_register && e->X_add_number >= REG_CR | |
4633 | && e->X_add_number < REG_CR + 128) | |
4634 | return 1; | |
4635 | break; | |
4636 | ||
4637 | case IA64_OPND_F1: | |
4638 | case IA64_OPND_F2: | |
4639 | case IA64_OPND_F3: | |
4640 | case IA64_OPND_F4: | |
4641 | if (e->X_op == O_register && e->X_add_number >= REG_FR | |
4642 | && e->X_add_number < REG_FR + 128) | |
4643 | return 1; | |
4644 | break; | |
4645 | ||
4646 | case IA64_OPND_P1: | |
4647 | case IA64_OPND_P2: | |
4648 | if (e->X_op == O_register && e->X_add_number >= REG_P | |
4649 | && e->X_add_number < REG_P + 64) | |
4650 | return 1; | |
4651 | break; | |
4652 | ||
4653 | case IA64_OPND_R1: | |
4654 | case IA64_OPND_R2: | |
4655 | case IA64_OPND_R3: | |
4656 | if (e->X_op == O_register && e->X_add_number >= REG_GR | |
4657 | && e->X_add_number < REG_GR + 128) | |
4658 | return 1; | |
4659 | break; | |
4660 | ||
4661 | case IA64_OPND_R3_2: | |
4662 | if (e->X_op == O_register && e->X_add_number >= REG_GR | |
4663 | && e->X_add_number < REG_GR + 4) | |
4664 | return 1; | |
4665 | break; | |
4666 | ||
542d6675 | 4667 | /* indirect operands: */ |
800eeca4 JW |
4668 | case IA64_OPND_CPUID_R3: |
4669 | case IA64_OPND_DBR_R3: | |
4670 | case IA64_OPND_DTR_R3: | |
4671 | case IA64_OPND_ITR_R3: | |
4672 | case IA64_OPND_IBR_R3: | |
4673 | case IA64_OPND_MSR_R3: | |
4674 | case IA64_OPND_PKR_R3: | |
4675 | case IA64_OPND_PMC_R3: | |
4676 | case IA64_OPND_PMD_R3: | |
4677 | case IA64_OPND_RR_R3: | |
4678 | if (e->X_op == O_index && e->X_op_symbol | |
4679 | && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID | |
4680 | == opnd - IA64_OPND_CPUID_R3)) | |
4681 | return 1; | |
4682 | break; | |
4683 | ||
4684 | case IA64_OPND_MR3: | |
4685 | if (e->X_op == O_index && !e->X_op_symbol) | |
4686 | return 1; | |
4687 | break; | |
4688 | ||
542d6675 | 4689 | /* immediate operands: */ |
800eeca4 JW |
4690 | case IA64_OPND_CNT2a: |
4691 | case IA64_OPND_LEN4: | |
4692 | case IA64_OPND_LEN6: | |
4693 | bits = operand_width (idesc->operands[index]); | |
4694 | if (e->X_op == O_constant | |
4695 | && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) | |
4696 | return 1; | |
4697 | break; | |
4698 | ||
4699 | case IA64_OPND_CNT2b: | |
4700 | if (e->X_op == O_constant | |
4701 | && (bfd_vma) (e->X_add_number - 1) < 3) | |
4702 | return 1; | |
4703 | break; | |
4704 | ||
4705 | case IA64_OPND_CNT2c: | |
4706 | val = e->X_add_number; | |
4707 | if (e->X_op == O_constant | |
4708 | && (val == 0 || val == 7 || val == 15 || val == 16)) | |
4709 | return 1; | |
4710 | break; | |
4711 | ||
4712 | case IA64_OPND_SOR: | |
4713 | /* SOR must be an integer multiple of 8 */ | |
4714 | if (e->X_add_number & 0x7) | |
4715 | break; | |
4716 | case IA64_OPND_SOF: | |
4717 | case IA64_OPND_SOL: | |
4718 | if (e->X_op == O_constant && | |
4719 | (bfd_vma) e->X_add_number <= 96) | |
4720 | return 1; | |
4721 | break; | |
4722 | ||
4723 | case IA64_OPND_IMMU62: | |
4724 | if (e->X_op == O_constant) | |
542d6675 | 4725 | { |
800eeca4 | 4726 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) |
542d6675 KH |
4727 | return 1; |
4728 | } | |
197865e8 | 4729 | else |
542d6675 KH |
4730 | { |
4731 | /* FIXME -- need 62-bit relocation type */ | |
4732 | as_bad (_("62-bit relocation not yet implemented")); | |
4733 | } | |
800eeca4 JW |
4734 | break; |
4735 | ||
4736 | case IA64_OPND_IMMU64: | |
4737 | if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup | |
4738 | || e->X_op == O_subtract) | |
4739 | { | |
4740 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
4741 | fix->code = BFD_RELOC_IA64_IMM64; | |
4742 | if (e->X_op != O_subtract) | |
4743 | { | |
4744 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
4745 | if (e->X_op == O_pseudo_fixup) | |
4746 | e->X_op = O_symbol; | |
4747 | } | |
4748 | ||
4749 | fix->opnd = idesc->operands[index]; | |
4750 | fix->expr = *e; | |
4751 | fix->is_pcrel = 0; | |
4752 | ++CURR_SLOT.num_fixups; | |
4753 | return 1; | |
4754 | } | |
4755 | else if (e->X_op == O_constant) | |
4756 | return 1; | |
4757 | break; | |
4758 | ||
4759 | case IA64_OPND_CCNT5: | |
4760 | case IA64_OPND_CNT5: | |
4761 | case IA64_OPND_CNT6: | |
4762 | case IA64_OPND_CPOS6a: | |
4763 | case IA64_OPND_CPOS6b: | |
4764 | case IA64_OPND_CPOS6c: | |
4765 | case IA64_OPND_IMMU2: | |
4766 | case IA64_OPND_IMMU7a: | |
4767 | case IA64_OPND_IMMU7b: | |
800eeca4 JW |
4768 | case IA64_OPND_IMMU21: |
4769 | case IA64_OPND_IMMU24: | |
4770 | case IA64_OPND_MBTYPE4: | |
4771 | case IA64_OPND_MHTYPE8: | |
4772 | case IA64_OPND_POS6: | |
4773 | bits = operand_width (idesc->operands[index]); | |
4774 | if (e->X_op == O_constant | |
4775 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) | |
4776 | return 1; | |
4777 | break; | |
4778 | ||
bf3ca999 TW |
4779 | case IA64_OPND_IMMU9: |
4780 | bits = operand_width (idesc->operands[index]); | |
4781 | if (e->X_op == O_constant | |
4782 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) | |
542d6675 KH |
4783 | { |
4784 | int lobits = e->X_add_number & 0x3; | |
4785 | if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) | |
4786 | e->X_add_number |= (bfd_vma) 0x3; | |
4787 | return 1; | |
4788 | } | |
bf3ca999 TW |
4789 | break; |
4790 | ||
800eeca4 JW |
4791 | case IA64_OPND_IMM44: |
4792 | /* least 16 bits must be zero */ | |
4793 | if ((e->X_add_number & 0xffff) != 0) | |
542d6675 | 4794 | as_warn (_("lower 16 bits of mask ignored")); |
800eeca4 JW |
4795 | |
4796 | if (e->X_op == O_constant | |
4797 | && ((e->X_add_number >= 0 | |
4798 | && e->X_add_number < ((bfd_vma) 1 << 44)) | |
4799 | || (e->X_add_number < 0 | |
4800 | && -e->X_add_number <= ((bfd_vma) 1 << 44)))) | |
542d6675 KH |
4801 | { |
4802 | /* sign-extend */ | |
4803 | if (e->X_add_number >= 0 | |
4804 | && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) | |
4805 | { | |
4806 | e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); | |
4807 | } | |
4808 | return 1; | |
4809 | } | |
800eeca4 JW |
4810 | break; |
4811 | ||
4812 | case IA64_OPND_IMM17: | |
4813 | /* bit 0 is a don't care (pr0 is hardwired to 1) */ | |
4814 | if (e->X_op == O_constant | |
4815 | && ((e->X_add_number >= 0 | |
4816 | && e->X_add_number < ((bfd_vma) 1 << 17)) | |
4817 | || (e->X_add_number < 0 | |
4818 | && -e->X_add_number <= ((bfd_vma) 1 << 17)))) | |
542d6675 KH |
4819 | { |
4820 | /* sign-extend */ | |
4821 | if (e->X_add_number >= 0 | |
4822 | && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) | |
4823 | { | |
4824 | e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); | |
4825 | } | |
4826 | return 1; | |
4827 | } | |
800eeca4 JW |
4828 | break; |
4829 | ||
4830 | case IA64_OPND_IMM14: | |
4831 | case IA64_OPND_IMM22: | |
4832 | relocatable = 1; | |
4833 | case IA64_OPND_IMM1: | |
4834 | case IA64_OPND_IMM8: | |
4835 | case IA64_OPND_IMM8U4: | |
4836 | case IA64_OPND_IMM8M1: | |
4837 | case IA64_OPND_IMM8M1U4: | |
4838 | case IA64_OPND_IMM8M1U8: | |
4839 | case IA64_OPND_IMM9a: | |
4840 | case IA64_OPND_IMM9b: | |
4841 | bits = operand_width (idesc->operands[index]); | |
4842 | if (relocatable && (e->X_op == O_symbol | |
4843 | || e->X_op == O_subtract | |
4844 | || e->X_op == O_pseudo_fixup)) | |
4845 | { | |
4846 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
4847 | ||
4848 | if (idesc->operands[index] == IA64_OPND_IMM14) | |
4849 | fix->code = BFD_RELOC_IA64_IMM14; | |
4850 | else | |
4851 | fix->code = BFD_RELOC_IA64_IMM22; | |
4852 | ||
4853 | if (e->X_op != O_subtract) | |
4854 | { | |
4855 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
4856 | if (e->X_op == O_pseudo_fixup) | |
4857 | e->X_op = O_symbol; | |
4858 | } | |
4859 | ||
4860 | fix->opnd = idesc->operands[index]; | |
4861 | fix->expr = *e; | |
4862 | fix->is_pcrel = 0; | |
4863 | ++CURR_SLOT.num_fixups; | |
4864 | return 1; | |
4865 | } | |
4866 | else if (e->X_op != O_constant | |
4867 | && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) | |
4868 | return 0; | |
4869 | ||
4870 | if (opnd == IA64_OPND_IMM8M1U4) | |
4871 | { | |
4872 | /* Zero is not valid for unsigned compares that take an adjusted | |
4873 | constant immediate range. */ | |
4874 | if (e->X_add_number == 0) | |
4875 | return 0; | |
4876 | ||
4877 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
4878 | checks will work. */ | |
4879 | val = e->X_add_number; | |
197865e8 KH |
4880 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
4881 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
4882 | val = ((val << 32) >> 32); |
4883 | ||
4884 | /* Check for 0x100000000. This is valid because | |
4885 | 0x100000000-1 is the same as ((uint32_t) -1). */ | |
4886 | if (val == ((bfd_signed_vma) 1 << 32)) | |
4887 | return 1; | |
4888 | ||
4889 | val = val - 1; | |
4890 | } | |
4891 | else if (opnd == IA64_OPND_IMM8M1U8) | |
4892 | { | |
4893 | /* Zero is not valid for unsigned compares that take an adjusted | |
4894 | constant immediate range. */ | |
4895 | if (e->X_add_number == 0) | |
4896 | return 0; | |
4897 | ||
4898 | /* Check for 0x10000000000000000. */ | |
4899 | if (e->X_op == O_big) | |
4900 | { | |
4901 | if (generic_bignum[0] == 0 | |
4902 | && generic_bignum[1] == 0 | |
4903 | && generic_bignum[2] == 0 | |
4904 | && generic_bignum[3] == 0 | |
4905 | && generic_bignum[4] == 1) | |
4906 | return 1; | |
4907 | else | |
4908 | return 0; | |
4909 | } | |
4910 | else | |
4911 | val = e->X_add_number - 1; | |
4912 | } | |
4913 | else if (opnd == IA64_OPND_IMM8M1) | |
4914 | val = e->X_add_number - 1; | |
4915 | else if (opnd == IA64_OPND_IMM8U4) | |
4916 | { | |
4917 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
4918 | checks will work. */ | |
4919 | val = e->X_add_number; | |
197865e8 KH |
4920 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
4921 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
4922 | val = ((val << 32) >> 32); |
4923 | } | |
4924 | else | |
4925 | val = e->X_add_number; | |
4926 | ||
4927 | if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1))) | |
4928 | || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1)))) | |
4929 | return 1; | |
4930 | break; | |
4931 | ||
4932 | case IA64_OPND_INC3: | |
4933 | /* +/- 1, 4, 8, 16 */ | |
4934 | val = e->X_add_number; | |
4935 | if (val < 0) | |
4936 | val = -val; | |
4937 | if (e->X_op == O_constant | |
4938 | && (val == 1 || val == 4 || val == 8 || val == 16)) | |
4939 | return 1; | |
4940 | break; | |
4941 | ||
4942 | case IA64_OPND_TGT25: | |
4943 | case IA64_OPND_TGT25b: | |
4944 | case IA64_OPND_TGT25c: | |
4945 | case IA64_OPND_TGT64: | |
4946 | if (e->X_op == O_symbol) | |
4947 | { | |
4948 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
4949 | if (opnd == IA64_OPND_TGT25) | |
4950 | fix->code = BFD_RELOC_IA64_PCREL21F; | |
4951 | else if (opnd == IA64_OPND_TGT25b) | |
4952 | fix->code = BFD_RELOC_IA64_PCREL21M; | |
4953 | else if (opnd == IA64_OPND_TGT25c) | |
4954 | fix->code = BFD_RELOC_IA64_PCREL21B; | |
542d6675 | 4955 | else if (opnd == IA64_OPND_TGT64) |
c67e42c9 RH |
4956 | fix->code = BFD_RELOC_IA64_PCREL60B; |
4957 | else | |
4958 | abort (); | |
4959 | ||
800eeca4 JW |
4960 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
4961 | fix->opnd = idesc->operands[index]; | |
4962 | fix->expr = *e; | |
4963 | fix->is_pcrel = 1; | |
4964 | ++CURR_SLOT.num_fixups; | |
4965 | return 1; | |
4966 | } | |
4967 | case IA64_OPND_TAG13: | |
4968 | case IA64_OPND_TAG13b: | |
4969 | switch (e->X_op) | |
4970 | { | |
4971 | case O_constant: | |
4972 | return 1; | |
4973 | ||
4974 | case O_symbol: | |
4975 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
4976 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0); | |
4977 | fix->opnd = idesc->operands[index]; | |
4978 | fix->expr = *e; | |
4979 | fix->is_pcrel = 1; | |
4980 | ++CURR_SLOT.num_fixups; | |
4981 | return 1; | |
4982 | ||
4983 | default: | |
4984 | break; | |
4985 | } | |
4986 | break; | |
4987 | ||
4988 | default: | |
4989 | break; | |
4990 | } | |
4991 | return 0; | |
4992 | } | |
4993 | ||
4994 | static int | |
4995 | parse_operand (e) | |
4996 | expressionS *e; | |
4997 | { | |
4998 | int sep = '\0'; | |
4999 | ||
5000 | memset (e, 0, sizeof (*e)); | |
5001 | e->X_op = O_absent; | |
5002 | SKIP_WHITESPACE (); | |
5003 | if (*input_line_pointer != '}') | |
5004 | expression (e); | |
5005 | sep = *input_line_pointer++; | |
5006 | ||
5007 | if (sep == '}') | |
5008 | { | |
5009 | if (!md.manual_bundling) | |
5010 | as_warn ("Found '}' when manual bundling is off"); | |
5011 | else | |
5012 | CURR_SLOT.manual_bundling_off = 1; | |
5013 | md.manual_bundling = 0; | |
5014 | sep = '\0'; | |
5015 | } | |
5016 | return sep; | |
5017 | } | |
5018 | ||
5019 | /* Returns the next entry in the opcode table that matches the one in | |
5020 | IDESC, and frees the entry in IDESC. If no matching entry is | |
197865e8 | 5021 | found, NULL is returned instead. */ |
800eeca4 JW |
5022 | |
5023 | static struct ia64_opcode * | |
5024 | get_next_opcode (struct ia64_opcode *idesc) | |
5025 | { | |
5026 | struct ia64_opcode *next = ia64_find_next_opcode (idesc); | |
5027 | ia64_free_opcode (idesc); | |
5028 | return next; | |
5029 | } | |
5030 | ||
5031 | /* Parse the operands for the opcode and find the opcode variant that | |
5032 | matches the specified operands, or NULL if no match is possible. */ | |
542d6675 KH |
5033 | |
5034 | static struct ia64_opcode * | |
800eeca4 JW |
5035 | parse_operands (idesc) |
5036 | struct ia64_opcode *idesc; | |
5037 | { | |
5038 | int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; | |
5039 | int sep = 0; | |
5040 | enum ia64_opnd expected_operand = IA64_OPND_NIL; | |
5041 | char mnemonic[129]; | |
5042 | char *first_arg = 0, *end, *saved_input_pointer; | |
5043 | unsigned int sof; | |
5044 | ||
5045 | assert (strlen (idesc->name) <= 128); | |
5046 | ||
5047 | strcpy (mnemonic, idesc->name); | |
5048 | if (idesc->operands[2] == IA64_OPND_SOF) | |
5049 | { | |
5050 | /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we | |
5051 | can't parse the first operand until we have parsed the | |
5052 | remaining operands of the "alloc" instruction. */ | |
5053 | SKIP_WHITESPACE (); | |
5054 | first_arg = input_line_pointer; | |
5055 | end = strchr (input_line_pointer, '='); | |
5056 | if (!end) | |
5057 | { | |
5058 | as_bad ("Expected separator `='"); | |
5059 | return 0; | |
5060 | } | |
5061 | input_line_pointer = end + 1; | |
5062 | ++i; | |
5063 | ++num_outputs; | |
5064 | } | |
5065 | ||
5066 | for (; i < NELEMS (CURR_SLOT.opnd); ++i) | |
5067 | { | |
5068 | sep = parse_operand (CURR_SLOT.opnd + i); | |
5069 | if (CURR_SLOT.opnd[i].X_op == O_absent) | |
5070 | break; | |
5071 | ||
5072 | ++num_operands; | |
5073 | ||
5074 | if (sep != '=' && sep != ',') | |
5075 | break; | |
5076 | ||
5077 | if (sep == '=') | |
5078 | { | |
5079 | if (num_outputs > 0) | |
5080 | as_bad ("Duplicate equal sign (=) in instruction"); | |
5081 | else | |
5082 | num_outputs = i + 1; | |
5083 | } | |
5084 | } | |
5085 | if (sep != '\0') | |
5086 | { | |
5087 | as_bad ("Illegal operand separator `%c'", sep); | |
5088 | return 0; | |
5089 | } | |
197865e8 | 5090 | |
800eeca4 JW |
5091 | if (idesc->operands[2] == IA64_OPND_SOF) |
5092 | { | |
5093 | /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ | |
5094 | know (strcmp (idesc->name, "alloc") == 0); | |
5095 | if (num_operands == 5 /* first_arg not included in this count! */ | |
5096 | && CURR_SLOT.opnd[2].X_op == O_constant | |
5097 | && CURR_SLOT.opnd[3].X_op == O_constant | |
5098 | && CURR_SLOT.opnd[4].X_op == O_constant | |
5099 | && CURR_SLOT.opnd[5].X_op == O_constant) | |
5100 | { | |
5101 | sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, | |
5102 | CURR_SLOT.opnd[3].X_add_number, | |
5103 | CURR_SLOT.opnd[4].X_add_number, | |
5104 | CURR_SLOT.opnd[5].X_add_number); | |
5105 | ||
542d6675 | 5106 | /* now we can parse the first arg: */ |
800eeca4 JW |
5107 | saved_input_pointer = input_line_pointer; |
5108 | input_line_pointer = first_arg; | |
5109 | sep = parse_operand (CURR_SLOT.opnd + 0); | |
5110 | if (sep != '=') | |
5111 | --num_outputs; /* force error */ | |
5112 | input_line_pointer = saved_input_pointer; | |
5113 | ||
5114 | CURR_SLOT.opnd[2].X_add_number = sof; | |
5115 | CURR_SLOT.opnd[3].X_add_number | |
5116 | = sof - CURR_SLOT.opnd[4].X_add_number; | |
5117 | CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; | |
5118 | } | |
5119 | } | |
5120 | ||
5121 | highest_unmatched_operand = 0; | |
5122 | expected_operand = idesc->operands[0]; | |
5123 | for (; idesc; idesc = get_next_opcode (idesc)) | |
5124 | { | |
5125 | if (num_outputs != idesc->num_outputs) | |
5126 | continue; /* mismatch in # of outputs */ | |
5127 | ||
5128 | CURR_SLOT.num_fixups = 0; | |
5129 | for (i = 0; i < num_operands && idesc->operands[i]; ++i) | |
5130 | if (!operand_match (idesc, i, CURR_SLOT.opnd + i)) | |
5131 | break; | |
5132 | ||
5133 | if (i != num_operands) | |
5134 | { | |
5135 | if (i > highest_unmatched_operand) | |
5136 | { | |
5137 | highest_unmatched_operand = i; | |
5138 | expected_operand = idesc->operands[i]; | |
5139 | } | |
5140 | continue; | |
5141 | } | |
5142 | ||
5143 | if (num_operands < NELEMS (idesc->operands) | |
5144 | && idesc->operands[num_operands]) | |
5145 | continue; /* mismatch in number of arguments */ | |
5146 | ||
5147 | break; | |
5148 | } | |
5149 | if (!idesc) | |
5150 | { | |
5151 | if (expected_operand) | |
5152 | as_bad ("Operand %u of `%s' should be %s", | |
5153 | highest_unmatched_operand + 1, mnemonic, | |
5154 | elf64_ia64_operands[expected_operand].desc); | |
5155 | else | |
5156 | as_bad ("Operand mismatch"); | |
5157 | return 0; | |
5158 | } | |
5159 | return idesc; | |
5160 | } | |
5161 | ||
5162 | static void | |
5163 | build_insn (slot, insnp) | |
5164 | struct slot *slot; | |
5165 | bfd_vma *insnp; | |
5166 | { | |
5167 | const struct ia64_operand *odesc, *o2desc; | |
5168 | struct ia64_opcode *idesc = slot->idesc; | |
5169 | bfd_signed_vma insn, val; | |
5170 | const char *err; | |
5171 | int i; | |
5172 | ||
5173 | insn = idesc->opcode | slot->qp_regno; | |
5174 | ||
5175 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) | |
5176 | { | |
c67e42c9 RH |
5177 | if (slot->opnd[i].X_op == O_register |
5178 | || slot->opnd[i].X_op == O_constant | |
5179 | || slot->opnd[i].X_op == O_index) | |
5180 | val = slot->opnd[i].X_add_number; | |
5181 | else if (slot->opnd[i].X_op == O_big) | |
800eeca4 | 5182 | { |
c67e42c9 RH |
5183 | /* This must be the value 0x10000000000000000. */ |
5184 | assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); | |
5185 | val = 0; | |
5186 | } | |
5187 | else | |
5188 | val = 0; | |
5189 | ||
5190 | switch (idesc->operands[i]) | |
5191 | { | |
5192 | case IA64_OPND_IMMU64: | |
800eeca4 JW |
5193 | *insnp++ = (val >> 22) & 0x1ffffffffffLL; |
5194 | insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) | |
5195 | | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) | |
5196 | | (((val >> 63) & 0x1) << 36)); | |
c67e42c9 RH |
5197 | continue; |
5198 | ||
5199 | case IA64_OPND_IMMU62: | |
542d6675 KH |
5200 | val &= 0x3fffffffffffffffULL; |
5201 | if (val != slot->opnd[i].X_add_number) | |
5202 | as_warn (_("Value truncated to 62 bits")); | |
5203 | *insnp++ = (val >> 21) & 0x1ffffffffffLL; | |
5204 | insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); | |
c67e42c9 | 5205 | continue; |
800eeca4 | 5206 | |
c67e42c9 RH |
5207 | case IA64_OPND_TGT64: |
5208 | val >>= 4; | |
5209 | *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; | |
5210 | insn |= ((((val >> 59) & 0x1) << 36) | |
5211 | | (((val >> 0) & 0xfffff) << 13)); | |
5212 | continue; | |
800eeca4 | 5213 | |
c67e42c9 RH |
5214 | case IA64_OPND_AR3: |
5215 | val -= REG_AR; | |
5216 | break; | |
5217 | ||
5218 | case IA64_OPND_B1: | |
5219 | case IA64_OPND_B2: | |
5220 | val -= REG_BR; | |
5221 | break; | |
5222 | ||
5223 | case IA64_OPND_CR3: | |
5224 | val -= REG_CR; | |
5225 | break; | |
5226 | ||
5227 | case IA64_OPND_F1: | |
5228 | case IA64_OPND_F2: | |
5229 | case IA64_OPND_F3: | |
5230 | case IA64_OPND_F4: | |
5231 | val -= REG_FR; | |
5232 | break; | |
5233 | ||
5234 | case IA64_OPND_P1: | |
5235 | case IA64_OPND_P2: | |
5236 | val -= REG_P; | |
5237 | break; | |
5238 | ||
5239 | case IA64_OPND_R1: | |
5240 | case IA64_OPND_R2: | |
5241 | case IA64_OPND_R3: | |
5242 | case IA64_OPND_R3_2: | |
5243 | case IA64_OPND_CPUID_R3: | |
5244 | case IA64_OPND_DBR_R3: | |
5245 | case IA64_OPND_DTR_R3: | |
5246 | case IA64_OPND_ITR_R3: | |
5247 | case IA64_OPND_IBR_R3: | |
5248 | case IA64_OPND_MR3: | |
5249 | case IA64_OPND_MSR_R3: | |
5250 | case IA64_OPND_PKR_R3: | |
5251 | case IA64_OPND_PMC_R3: | |
5252 | case IA64_OPND_PMD_R3: | |
197865e8 | 5253 | case IA64_OPND_RR_R3: |
c67e42c9 RH |
5254 | val -= REG_GR; |
5255 | break; | |
5256 | ||
5257 | default: | |
5258 | break; | |
5259 | } | |
5260 | ||
5261 | odesc = elf64_ia64_operands + idesc->operands[i]; | |
5262 | err = (*odesc->insert) (odesc, val, &insn); | |
5263 | if (err) | |
5264 | as_bad_where (slot->src_file, slot->src_line, | |
5265 | "Bad operand value: %s", err); | |
5266 | if (idesc->flags & IA64_OPCODE_PSEUDO) | |
5267 | { | |
5268 | if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) | |
5269 | && odesc == elf64_ia64_operands + IA64_OPND_F3) | |
5270 | { | |
5271 | o2desc = elf64_ia64_operands + IA64_OPND_F2; | |
5272 | (*o2desc->insert) (o2desc, val, &insn); | |
800eeca4 | 5273 | } |
c67e42c9 RH |
5274 | if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) |
5275 | && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a | |
5276 | || odesc == elf64_ia64_operands + IA64_OPND_POS6)) | |
800eeca4 | 5277 | { |
c67e42c9 RH |
5278 | o2desc = elf64_ia64_operands + IA64_OPND_LEN6; |
5279 | (*o2desc->insert) (o2desc, 64 - val, &insn); | |
800eeca4 JW |
5280 | } |
5281 | } | |
5282 | } | |
5283 | *insnp = insn; | |
5284 | } | |
5285 | ||
5286 | static void | |
5287 | emit_one_bundle () | |
5288 | { | |
5289 | unsigned int manual_bundling_on = 0, manual_bundling_off = 0; | |
5290 | unsigned int manual_bundling = 0; | |
5291 | enum ia64_unit required_unit, insn_unit = 0; | |
5292 | enum ia64_insn_type type[3], insn_type; | |
5293 | unsigned int template, orig_template; | |
542d6675 | 5294 | bfd_vma insn[3] = { -1, -1, -1 }; |
800eeca4 JW |
5295 | struct ia64_opcode *idesc; |
5296 | int end_of_insn_group = 0, user_template = -1; | |
5297 | int n, i, j, first, curr; | |
e0c9811a | 5298 | unw_rec_list *ptr, *prev; |
800eeca4 JW |
5299 | bfd_vma t0 = 0, t1 = 0; |
5300 | struct label_fix *lfix; | |
5301 | struct insn_fix *ifix; | |
5302 | char mnemonic[16]; | |
5303 | fixS *fix; | |
5304 | char *f; | |
5305 | ||
5306 | first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; | |
5307 | know (first >= 0 & first < NUM_SLOTS); | |
5308 | n = MIN (3, md.num_slots_in_use); | |
5309 | ||
5310 | /* Determine template: user user_template if specified, best match | |
542d6675 | 5311 | otherwise: */ |
800eeca4 JW |
5312 | |
5313 | if (md.slot[first].user_template >= 0) | |
5314 | user_template = template = md.slot[first].user_template; | |
5315 | else | |
5316 | { | |
032efc85 | 5317 | /* Auto select appropriate template. */ |
800eeca4 JW |
5318 | memset (type, 0, sizeof (type)); |
5319 | curr = first; | |
5320 | for (i = 0; i < n; ++i) | |
5321 | { | |
032efc85 RH |
5322 | if (md.slot[curr].label_fixups && i != 0) |
5323 | break; | |
800eeca4 JW |
5324 | type[i] = md.slot[curr].idesc->type; |
5325 | curr = (curr + 1) % NUM_SLOTS; | |
5326 | } | |
5327 | template = best_template[type[0]][type[1]][type[2]]; | |
5328 | } | |
5329 | ||
542d6675 | 5330 | /* initialize instructions with appropriate nops: */ |
800eeca4 JW |
5331 | for (i = 0; i < 3; ++i) |
5332 | insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; | |
5333 | ||
5334 | f = frag_more (16); | |
5335 | ||
542d6675 | 5336 | /* now fill in slots with as many insns as possible: */ |
800eeca4 JW |
5337 | curr = first; |
5338 | idesc = md.slot[curr].idesc; | |
5339 | end_of_insn_group = 0; | |
5340 | for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) | |
5341 | { | |
e0c9811a JW |
5342 | /* Set the slot number for prologue/body records now as those |
5343 | refer to the current point, not the point after the | |
542d6675 | 5344 | instruction has been issued: */ |
10850f29 JW |
5345 | /* Don't try to delete prologue/body records here, as that will cause |
5346 | them to also be deleted from the master list of unwind records. */ | |
e0c9811a | 5347 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
10850f29 JW |
5348 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
5349 | || ptr->r.type == body) | |
f5a30c2e JW |
5350 | { |
5351 | ptr->slot_number = (unsigned long) f + i; | |
5352 | ptr->slot_frag = frag_now; | |
5353 | } | |
e0c9811a | 5354 | |
800eeca4 JW |
5355 | if (idesc->flags & IA64_OPCODE_SLOT2) |
5356 | { | |
5357 | if (manual_bundling && i != 2) | |
5358 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5359 | "`%s' must be last in bundle", idesc->name); | |
5360 | else | |
5361 | i = 2; | |
5362 | } | |
5363 | if (idesc->flags & IA64_OPCODE_LAST) | |
5364 | { | |
5365 | int required_slot, required_template; | |
5366 | ||
5367 | /* If we need a stop bit after an M slot, our only choice is | |
5368 | template 5 (M;;MI). If we need a stop bit after a B | |
5369 | slot, our only choice is to place it at the end of the | |
5370 | bundle, because the only available templates are MIB, | |
5371 | MBB, BBB, MMB, and MFB. We don't handle anything other | |
5372 | than M and B slots because these are the only kind of | |
5373 | instructions that can have the IA64_OPCODE_LAST bit set. */ | |
5374 | required_template = template; | |
5375 | switch (idesc->type) | |
5376 | { | |
5377 | case IA64_TYPE_M: | |
5378 | required_slot = 0; | |
5379 | required_template = 5; | |
5380 | break; | |
5381 | ||
5382 | case IA64_TYPE_B: | |
5383 | required_slot = 2; | |
5384 | break; | |
5385 | ||
5386 | default: | |
5387 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5388 | "Internal error: don't know how to force %s to end" | |
5389 | "of instruction group", idesc->name); | |
5390 | required_slot = i; | |
5391 | break; | |
5392 | } | |
5393 | if (manual_bundling && i != required_slot) | |
5394 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5395 | "`%s' must be last in instruction group", | |
5396 | idesc->name); | |
5397 | if (required_slot < i) | |
5398 | /* Can't fit this instruction. */ | |
5399 | break; | |
5400 | ||
5401 | i = required_slot; | |
5402 | if (required_template != template) | |
5403 | { | |
5404 | /* If we switch the template, we need to reset the NOPs | |
5405 | after slot i. The slot-types of the instructions ahead | |
5406 | of i never change, so we don't need to worry about | |
5407 | changing NOPs in front of this slot. */ | |
5408 | for (j = i; j < 3; ++j) | |
5409 | insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; | |
5410 | } | |
5411 | template = required_template; | |
5412 | } | |
5413 | if (curr != first && md.slot[curr].label_fixups) | |
5414 | { | |
5415 | if (manual_bundling_on) | |
5416 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5417 | "Label must be first in a bundle"); | |
5418 | /* This insn must go into the first slot of a bundle. */ | |
5419 | break; | |
5420 | } | |
5421 | ||
5422 | manual_bundling_on = md.slot[curr].manual_bundling_on; | |
5423 | manual_bundling_off = md.slot[curr].manual_bundling_off; | |
5424 | ||
5425 | if (manual_bundling_on) | |
5426 | { | |
5427 | if (curr == first) | |
5428 | manual_bundling = 1; | |
5429 | else | |
5430 | break; /* need to start a new bundle */ | |
5431 | } | |
5432 | ||
5433 | if (end_of_insn_group && md.num_slots_in_use >= 1) | |
5434 | { | |
5435 | /* We need an instruction group boundary in the middle of a | |
5436 | bundle. See if we can switch to an other template with | |
5437 | an appropriate boundary. */ | |
5438 | ||
5439 | orig_template = template; | |
5440 | if (i == 1 && (user_template == 4 | |
5441 | || (user_template < 0 | |
5442 | && (ia64_templ_desc[template].exec_unit[0] | |
5443 | == IA64_UNIT_M)))) | |
5444 | { | |
5445 | template = 5; | |
5446 | end_of_insn_group = 0; | |
5447 | } | |
5448 | else if (i == 2 && (user_template == 0 | |
5449 | || (user_template < 0 | |
5450 | && (ia64_templ_desc[template].exec_unit[1] | |
5451 | == IA64_UNIT_I))) | |
5452 | /* This test makes sure we don't switch the template if | |
5453 | the next instruction is one that needs to be first in | |
5454 | an instruction group. Since all those instructions are | |
5455 | in the M group, there is no way such an instruction can | |
5456 | fit in this bundle even if we switch the template. The | |
5457 | reason we have to check for this is that otherwise we | |
5458 | may end up generating "MI;;I M.." which has the deadly | |
5459 | effect that the second M instruction is no longer the | |
5460 | first in the bundle! --davidm 99/12/16 */ | |
5461 | && (idesc->flags & IA64_OPCODE_FIRST) == 0) | |
5462 | { | |
5463 | template = 1; | |
5464 | end_of_insn_group = 0; | |
5465 | } | |
5466 | else if (curr != first) | |
5467 | /* can't fit this insn */ | |
5468 | break; | |
5469 | ||
5470 | if (template != orig_template) | |
5471 | /* if we switch the template, we need to reset the NOPs | |
5472 | after slot i. The slot-types of the instructions ahead | |
5473 | of i never change, so we don't need to worry about | |
5474 | changing NOPs in front of this slot. */ | |
5475 | for (j = i; j < 3; ++j) | |
5476 | insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; | |
5477 | } | |
5478 | required_unit = ia64_templ_desc[template].exec_unit[i]; | |
5479 | ||
542d6675 | 5480 | /* resolve dynamic opcodes such as "break" and "nop": */ |
800eeca4 JW |
5481 | if (idesc->type == IA64_TYPE_DYN) |
5482 | { | |
5483 | if ((strcmp (idesc->name, "nop") == 0) | |
5484 | || (strcmp (idesc->name, "break") == 0)) | |
5485 | insn_unit = required_unit; | |
5486 | else if (strcmp (idesc->name, "chk.s") == 0) | |
5487 | { | |
5488 | insn_unit = IA64_UNIT_M; | |
5489 | if (required_unit == IA64_UNIT_I) | |
5490 | insn_unit = IA64_UNIT_I; | |
5491 | } | |
5492 | else | |
5493 | as_fatal ("emit_one_bundle: unexpected dynamic op"); | |
5494 | ||
5495 | sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); | |
3d56ab85 | 5496 | ia64_free_opcode (idesc); |
800eeca4 JW |
5497 | md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); |
5498 | #if 0 | |
5499 | know (!idesc->next); /* no resolved dynamic ops have collisions */ | |
5500 | #endif | |
5501 | } | |
5502 | else | |
5503 | { | |
5504 | insn_type = idesc->type; | |
5505 | insn_unit = IA64_UNIT_NIL; | |
5506 | switch (insn_type) | |
5507 | { | |
5508 | case IA64_TYPE_A: | |
5509 | if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) | |
5510 | insn_unit = required_unit; | |
5511 | break; | |
542d6675 | 5512 | case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; |
800eeca4 JW |
5513 | case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; |
5514 | case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; | |
5515 | case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; | |
5516 | case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; | |
5517 | default: break; | |
5518 | } | |
5519 | } | |
5520 | ||
5521 | if (insn_unit != required_unit) | |
5522 | { | |
5523 | if (required_unit == IA64_UNIT_L | |
542d6675 | 5524 | && insn_unit == IA64_UNIT_I |
800eeca4 JW |
5525 | && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) |
5526 | { | |
5527 | /* we got ourselves an MLX template but the current | |
197865e8 | 5528 | instruction isn't an X-unit, or an I-unit instruction |
800eeca4 JW |
5529 | that can go into the X slot of an MLX template. Duh. */ |
5530 | if (md.num_slots_in_use >= NUM_SLOTS) | |
5531 | { | |
5532 | as_bad_where (md.slot[curr].src_file, | |
5533 | md.slot[curr].src_line, | |
5534 | "`%s' can't go in X slot of " | |
5535 | "MLX template", idesc->name); | |
542d6675 | 5536 | /* drop this insn so we don't livelock: */ |
800eeca4 JW |
5537 | --md.num_slots_in_use; |
5538 | } | |
5539 | break; | |
5540 | } | |
5541 | continue; /* try next slot */ | |
5542 | } | |
5543 | ||
5544 | if (debug_type == DEBUG_DWARF2) | |
5545 | { | |
5546 | bfd_vma addr; | |
5547 | ||
f1bcba5b | 5548 | addr = frag_now->fr_address + frag_now_fix () - 16 + i; |
800eeca4 JW |
5549 | dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); |
5550 | } | |
5551 | ||
5552 | build_insn (md.slot + curr, insn + i); | |
5553 | ||
10850f29 JW |
5554 | /* Set slot counts for non prologue/body unwind records. */ |
5555 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) | |
5556 | if (ptr->r.type != prologue && ptr->r.type != prologue_gr | |
5557 | && ptr->r.type != body) | |
f5a30c2e JW |
5558 | { |
5559 | ptr->slot_number = (unsigned long) f + i; | |
5560 | ptr->slot_frag = frag_now; | |
5561 | } | |
10850f29 | 5562 | md.slot[curr].unwind_record = NULL; |
10850f29 | 5563 | |
800eeca4 JW |
5564 | if (required_unit == IA64_UNIT_L) |
5565 | { | |
5566 | know (i == 1); | |
5567 | /* skip one slot for long/X-unit instructions */ | |
5568 | ++i; | |
5569 | } | |
5570 | --md.num_slots_in_use; | |
5571 | ||
542d6675 | 5572 | /* now is a good time to fix up the labels for this insn: */ |
800eeca4 JW |
5573 | for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) |
5574 | { | |
5575 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16); | |
5576 | symbol_set_frag (lfix->sym, frag_now); | |
5577 | } | |
f1bcba5b JW |
5578 | /* and fix up the tags also. */ |
5579 | for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) | |
5580 | { | |
5581 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); | |
5582 | symbol_set_frag (lfix->sym, frag_now); | |
5583 | } | |
800eeca4 JW |
5584 | |
5585 | for (j = 0; j < md.slot[curr].num_fixups; ++j) | |
5586 | { | |
5587 | ifix = md.slot[curr].fixup + j; | |
5588 | fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4, | |
5589 | &ifix->expr, ifix->is_pcrel, ifix->code); | |
5590 | fix->tc_fix_data.opnd = ifix->opnd; | |
5591 | fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); | |
5592 | fix->fx_file = md.slot[curr].src_file; | |
5593 | fix->fx_line = md.slot[curr].src_line; | |
5594 | } | |
5595 | ||
5596 | end_of_insn_group = md.slot[curr].end_of_insn_group; | |
5597 | ||
542d6675 | 5598 | /* clear slot: */ |
800eeca4 JW |
5599 | ia64_free_opcode (md.slot[curr].idesc); |
5600 | memset (md.slot + curr, 0, sizeof (md.slot[curr])); | |
5601 | md.slot[curr].user_template = -1; | |
5602 | ||
5603 | if (manual_bundling_off) | |
5604 | { | |
5605 | manual_bundling = 0; | |
5606 | break; | |
5607 | } | |
5608 | curr = (curr + 1) % NUM_SLOTS; | |
5609 | idesc = md.slot[curr].idesc; | |
5610 | } | |
5611 | if (manual_bundling) | |
5612 | { | |
5613 | if (md.num_slots_in_use > 0) | |
5614 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5615 | "`%s' does not fit into %s template", | |
5616 | idesc->name, ia64_templ_desc[template].name); | |
5617 | else | |
5618 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
5619 | "Missing '}' at end of file"); | |
5620 | } | |
5621 | know (md.num_slots_in_use < NUM_SLOTS); | |
5622 | ||
5623 | t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); | |
5624 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
5625 | ||
44f5c83a JW |
5626 | number_to_chars_littleendian (f + 0, t0, 8); |
5627 | number_to_chars_littleendian (f + 8, t1, 8); | |
f5a30c2e JW |
5628 | |
5629 | unwind.next_slot_number = (unsigned long) f + 16; | |
5630 | unwind.next_slot_frag = frag_now; | |
800eeca4 JW |
5631 | } |
5632 | ||
5633 | int | |
5634 | md_parse_option (c, arg) | |
5635 | int c; | |
5636 | char *arg; | |
5637 | { | |
800eeca4 JW |
5638 | switch (c) |
5639 | { | |
c43c2cc5 | 5640 | /* Switches from the Intel assembler. */ |
44f5c83a | 5641 | case 'm': |
800eeca4 JW |
5642 | if (strcmp (arg, "ilp64") == 0 |
5643 | || strcmp (arg, "lp64") == 0 | |
5644 | || strcmp (arg, "p64") == 0) | |
5645 | { | |
5646 | md.flags |= EF_IA_64_ABI64; | |
5647 | } | |
5648 | else if (strcmp (arg, "ilp32") == 0) | |
5649 | { | |
5650 | md.flags &= ~EF_IA_64_ABI64; | |
5651 | } | |
5652 | else if (strcmp (arg, "le") == 0) | |
5653 | { | |
5654 | md.flags &= ~EF_IA_64_BE; | |
5655 | } | |
5656 | else if (strcmp (arg, "be") == 0) | |
5657 | { | |
5658 | md.flags |= EF_IA_64_BE; | |
5659 | } | |
5660 | else | |
5661 | return 0; | |
5662 | break; | |
5663 | ||
5664 | case 'N': | |
5665 | if (strcmp (arg, "so") == 0) | |
5666 | { | |
542d6675 | 5667 | /* Suppress signon message. */ |
800eeca4 JW |
5668 | } |
5669 | else if (strcmp (arg, "pi") == 0) | |
5670 | { | |
5671 | /* Reject privileged instructions. FIXME */ | |
5672 | } | |
5673 | else if (strcmp (arg, "us") == 0) | |
5674 | { | |
5675 | /* Allow union of signed and unsigned range. FIXME */ | |
5676 | } | |
5677 | else if (strcmp (arg, "close_fcalls") == 0) | |
5678 | { | |
5679 | /* Do not resolve global function calls. */ | |
5680 | } | |
5681 | else | |
5682 | return 0; | |
5683 | break; | |
5684 | ||
5685 | case 'C': | |
5686 | /* temp[="prefix"] Insert temporary labels into the object file | |
5687 | symbol table prefixed by "prefix". | |
5688 | Default prefix is ":temp:". | |
5689 | */ | |
5690 | break; | |
5691 | ||
5692 | case 'a': | |
5693 | /* ??? Conflicts with gas' listing option. */ | |
5694 | /* indirect=<tgt> Assume unannotated indirect branches behavior | |
5695 | according to <tgt> -- | |
5696 | exit: branch out from the current context (default) | |
5697 | labels: all labels in context may be branch targets | |
5698 | */ | |
5699 | break; | |
5700 | ||
5701 | case 'x': | |
5702 | /* -X conflicts with an ignored option, use -x instead */ | |
5703 | md.detect_dv = 1; | |
5704 | if (!arg || strcmp (arg, "explicit") == 0) | |
542d6675 KH |
5705 | { |
5706 | /* set default mode to explicit */ | |
5707 | md.default_explicit_mode = 1; | |
5708 | break; | |
5709 | } | |
800eeca4 | 5710 | else if (strcmp (arg, "auto") == 0) |
542d6675 KH |
5711 | { |
5712 | md.default_explicit_mode = 0; | |
5713 | } | |
800eeca4 | 5714 | else if (strcmp (arg, "debug") == 0) |
542d6675 KH |
5715 | { |
5716 | md.debug_dv = 1; | |
5717 | } | |
800eeca4 | 5718 | else if (strcmp (arg, "debugx") == 0) |
542d6675 KH |
5719 | { |
5720 | md.default_explicit_mode = 1; | |
5721 | md.debug_dv = 1; | |
5722 | } | |
800eeca4 | 5723 | else |
542d6675 KH |
5724 | { |
5725 | as_bad (_("Unrecognized option '-x%s'"), arg); | |
5726 | } | |
800eeca4 JW |
5727 | break; |
5728 | ||
5729 | case 'S': | |
5730 | /* nops Print nops statistics. */ | |
5731 | break; | |
5732 | ||
c43c2cc5 JW |
5733 | /* GNU specific switches for gcc. */ |
5734 | case OPTION_MCONSTANT_GP: | |
5735 | md.flags |= EF_IA_64_CONS_GP; | |
5736 | break; | |
5737 | ||
5738 | case OPTION_MAUTO_PIC: | |
5739 | md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; | |
5740 | break; | |
5741 | ||
800eeca4 JW |
5742 | default: |
5743 | return 0; | |
5744 | } | |
5745 | ||
5746 | return 1; | |
5747 | } | |
5748 | ||
5749 | void | |
5750 | md_show_usage (stream) | |
5751 | FILE *stream; | |
5752 | { | |
542d6675 | 5753 | fputs (_("\ |
800eeca4 | 5754 | IA-64 options:\n\ |
44f5c83a JW |
5755 | -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ |
5756 | -mle | -mbe select little- or big-endian byte order (default -mle)\n\ | |
800eeca4 JW |
5757 | -x | -xexplicit turn on dependency violation checking (default)\n\ |
5758 | -xauto automagically remove dependency violations\n\ | |
5759 | -xdebug debug dependency violation checker\n"), | |
5760 | stream); | |
5761 | } | |
5762 | ||
44576e1f RH |
5763 | /* Return true if TYPE fits in TEMPL at SLOT. */ |
5764 | ||
5765 | static int | |
800eeca4 JW |
5766 | match (int templ, int type, int slot) |
5767 | { | |
5768 | enum ia64_unit unit; | |
5769 | int result; | |
5770 | ||
5771 | unit = ia64_templ_desc[templ].exec_unit[slot]; | |
5772 | switch (type) | |
5773 | { | |
5774 | case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ | |
5775 | case IA64_TYPE_A: | |
5776 | result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); | |
5777 | break; | |
5778 | case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; | |
5779 | case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; | |
5780 | case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; | |
5781 | case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; | |
5782 | case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; | |
5783 | default: result = 0; break; | |
5784 | } | |
5785 | return result; | |
5786 | } | |
5787 | ||
44576e1f RH |
5788 | /* Add a bit of extra goodness if a nop of type F or B would fit |
5789 | in TEMPL at SLOT. */ | |
5790 | ||
5791 | static inline int | |
5792 | extra_goodness (int templ, int slot) | |
5793 | { | |
ebeeafe6 | 5794 | if (slot == 1 && match (templ, IA64_TYPE_F, slot)) |
44576e1f | 5795 | return 2; |
ebeeafe6 | 5796 | if (slot == 2 && match (templ, IA64_TYPE_B, slot)) |
44576e1f RH |
5797 | return 1; |
5798 | return 0; | |
5799 | } | |
5800 | ||
800eeca4 JW |
5801 | /* This function is called once, at assembler startup time. It sets |
5802 | up all the tables, etc. that the MD part of the assembler will need | |
5803 | that can be determined before arguments are parsed. */ | |
5804 | void | |
5805 | md_begin () | |
5806 | { | |
44f5c83a | 5807 | int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; |
800eeca4 JW |
5808 | const char *err; |
5809 | char name[8]; | |
5810 | ||
5811 | md.auto_align = 1; | |
5812 | md.explicit_mode = md.default_explicit_mode; | |
5813 | ||
5814 | bfd_set_section_alignment (stdoutput, text_section, 4); | |
5815 | ||
44f5c83a | 5816 | target_big_endian = TARGET_BYTES_BIG_ENDIAN; |
800eeca4 | 5817 | pseudo_func[FUNC_FPTR_RELATIVE].u.sym = |
542d6675 KH |
5818 | symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, |
5819 | &zero_address_frag); | |
800eeca4 JW |
5820 | |
5821 | pseudo_func[FUNC_GP_RELATIVE].u.sym = | |
542d6675 KH |
5822 | symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, |
5823 | &zero_address_frag); | |
800eeca4 JW |
5824 | |
5825 | pseudo_func[FUNC_LT_RELATIVE].u.sym = | |
542d6675 KH |
5826 | symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, |
5827 | &zero_address_frag); | |
800eeca4 | 5828 | |
c67e42c9 | 5829 | pseudo_func[FUNC_PC_RELATIVE].u.sym = |
542d6675 KH |
5830 | symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, |
5831 | &zero_address_frag); | |
c67e42c9 | 5832 | |
800eeca4 | 5833 | pseudo_func[FUNC_PLT_RELATIVE].u.sym = |
542d6675 KH |
5834 | symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, |
5835 | &zero_address_frag); | |
800eeca4 JW |
5836 | |
5837 | pseudo_func[FUNC_SEC_RELATIVE].u.sym = | |
542d6675 KH |
5838 | symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, |
5839 | &zero_address_frag); | |
800eeca4 JW |
5840 | |
5841 | pseudo_func[FUNC_SEG_RELATIVE].u.sym = | |
542d6675 KH |
5842 | symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, |
5843 | &zero_address_frag); | |
800eeca4 JW |
5844 | |
5845 | pseudo_func[FUNC_LTV_RELATIVE].u.sym = | |
542d6675 KH |
5846 | symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, |
5847 | &zero_address_frag); | |
800eeca4 JW |
5848 | |
5849 | pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = | |
542d6675 KH |
5850 | symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, |
5851 | &zero_address_frag); | |
800eeca4 | 5852 | |
197865e8 | 5853 | /* Compute the table of best templates. We compute goodness as a |
44576e1f RH |
5854 | base 4 value, in which each match counts for 3, each F counts |
5855 | for 2, each B counts for 1. This should maximize the number of | |
5856 | F and B nops in the chosen bundles, which is good because these | |
5857 | pipelines are least likely to be overcommitted. */ | |
800eeca4 JW |
5858 | for (i = 0; i < IA64_NUM_TYPES; ++i) |
5859 | for (j = 0; j < IA64_NUM_TYPES; ++j) | |
5860 | for (k = 0; k < IA64_NUM_TYPES; ++k) | |
5861 | { | |
5862 | best = 0; | |
5863 | for (t = 0; t < NELEMS (ia64_templ_desc); ++t) | |
5864 | { | |
5865 | goodness = 0; | |
5866 | if (match (t, i, 0)) | |
5867 | { | |
5868 | if (match (t, j, 1)) | |
5869 | { | |
5870 | if (match (t, k, 2)) | |
44576e1f | 5871 | goodness = 3 + 3 + 3; |
800eeca4 | 5872 | else |
44576e1f | 5873 | goodness = 3 + 3 + extra_goodness (t, 2); |
800eeca4 JW |
5874 | } |
5875 | else if (match (t, j, 2)) | |
44576e1f | 5876 | goodness = 3 + 3 + extra_goodness (t, 1); |
800eeca4 | 5877 | else |
44576e1f RH |
5878 | { |
5879 | goodness = 3; | |
5880 | goodness += extra_goodness (t, 1); | |
5881 | goodness += extra_goodness (t, 2); | |
5882 | } | |
800eeca4 JW |
5883 | } |
5884 | else if (match (t, i, 1)) | |
5885 | { | |
5886 | if (match (t, j, 2)) | |
44576e1f | 5887 | goodness = 3 + 3; |
800eeca4 | 5888 | else |
44576e1f | 5889 | goodness = 3 + extra_goodness (t, 2); |
800eeca4 JW |
5890 | } |
5891 | else if (match (t, i, 2)) | |
44576e1f | 5892 | goodness = 3 + extra_goodness (t, 1); |
800eeca4 JW |
5893 | |
5894 | if (goodness > best) | |
5895 | { | |
5896 | best = goodness; | |
5897 | best_template[i][j][k] = t; | |
5898 | } | |
5899 | } | |
5900 | } | |
5901 | ||
5902 | for (i = 0; i < NUM_SLOTS; ++i) | |
5903 | md.slot[i].user_template = -1; | |
5904 | ||
5905 | md.pseudo_hash = hash_new (); | |
5906 | for (i = 0; i < NELEMS (pseudo_opcode); ++i) | |
5907 | { | |
5908 | err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, | |
5909 | (void *) (pseudo_opcode + i)); | |
5910 | if (err) | |
5911 | as_fatal ("ia64.md_begin: can't hash `%s': %s", | |
5912 | pseudo_opcode[i].name, err); | |
5913 | } | |
5914 | ||
5915 | md.reg_hash = hash_new (); | |
5916 | md.dynreg_hash = hash_new (); | |
5917 | md.const_hash = hash_new (); | |
5918 | md.entry_hash = hash_new (); | |
5919 | ||
542d6675 | 5920 | /* general registers: */ |
800eeca4 JW |
5921 | |
5922 | total = 128; | |
5923 | for (i = 0; i < total; ++i) | |
5924 | { | |
5925 | sprintf (name, "r%d", i - REG_GR); | |
5926 | md.regsym[i] = declare_register (name, i); | |
5927 | } | |
5928 | ||
542d6675 | 5929 | /* floating point registers: */ |
800eeca4 JW |
5930 | total += 128; |
5931 | for (; i < total; ++i) | |
5932 | { | |
5933 | sprintf (name, "f%d", i - REG_FR); | |
5934 | md.regsym[i] = declare_register (name, i); | |
5935 | } | |
5936 | ||
542d6675 | 5937 | /* application registers: */ |
800eeca4 JW |
5938 | total += 128; |
5939 | ar_base = i; | |
5940 | for (; i < total; ++i) | |
5941 | { | |
5942 | sprintf (name, "ar%d", i - REG_AR); | |
5943 | md.regsym[i] = declare_register (name, i); | |
5944 | } | |
5945 | ||
542d6675 | 5946 | /* control registers: */ |
800eeca4 JW |
5947 | total += 128; |
5948 | cr_base = i; | |
5949 | for (; i < total; ++i) | |
5950 | { | |
5951 | sprintf (name, "cr%d", i - REG_CR); | |
5952 | md.regsym[i] = declare_register (name, i); | |
5953 | } | |
5954 | ||
542d6675 | 5955 | /* predicate registers: */ |
800eeca4 JW |
5956 | total += 64; |
5957 | for (; i < total; ++i) | |
5958 | { | |
5959 | sprintf (name, "p%d", i - REG_P); | |
5960 | md.regsym[i] = declare_register (name, i); | |
5961 | } | |
5962 | ||
542d6675 | 5963 | /* branch registers: */ |
800eeca4 JW |
5964 | total += 8; |
5965 | for (; i < total; ++i) | |
5966 | { | |
5967 | sprintf (name, "b%d", i - REG_BR); | |
5968 | md.regsym[i] = declare_register (name, i); | |
5969 | } | |
5970 | ||
5971 | md.regsym[REG_IP] = declare_register ("ip", REG_IP); | |
5972 | md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); | |
5973 | md.regsym[REG_PR] = declare_register ("pr", REG_PR); | |
5974 | md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); | |
5975 | md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); | |
5976 | md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); | |
5977 | md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); | |
5978 | ||
5979 | for (i = 0; i < NELEMS (indirect_reg); ++i) | |
5980 | { | |
5981 | regnum = indirect_reg[i].regnum; | |
5982 | md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); | |
5983 | } | |
5984 | ||
542d6675 | 5985 | /* define synonyms for application registers: */ |
800eeca4 JW |
5986 | for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) |
5987 | md.regsym[i] = declare_register (ar[i - REG_AR].name, | |
5988 | REG_AR + ar[i - REG_AR].regnum); | |
5989 | ||
542d6675 | 5990 | /* define synonyms for control registers: */ |
800eeca4 JW |
5991 | for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) |
5992 | md.regsym[i] = declare_register (cr[i - REG_CR].name, | |
5993 | REG_CR + cr[i - REG_CR].regnum); | |
5994 | ||
5995 | declare_register ("gp", REG_GR + 1); | |
5996 | declare_register ("sp", REG_GR + 12); | |
5997 | declare_register ("rp", REG_BR + 0); | |
5998 | ||
542d6675 | 5999 | /* pseudo-registers used to specify unwind info: */ |
e0c9811a JW |
6000 | declare_register ("psp", REG_PSP); |
6001 | ||
800eeca4 JW |
6002 | declare_register_set ("ret", 4, REG_GR + 8); |
6003 | declare_register_set ("farg", 8, REG_FR + 8); | |
6004 | declare_register_set ("fret", 8, REG_FR + 8); | |
6005 | ||
6006 | for (i = 0; i < NELEMS (const_bits); ++i) | |
6007 | { | |
6008 | err = hash_insert (md.const_hash, const_bits[i].name, | |
6009 | (PTR) (const_bits + i)); | |
6010 | if (err) | |
6011 | as_fatal ("Inserting \"%s\" into constant hash table failed: %s", | |
6012 | name, err); | |
6013 | } | |
6014 | ||
44f5c83a JW |
6015 | /* Set the architecture and machine depending on defaults and command line |
6016 | options. */ | |
6017 | if (md.flags & EF_IA_64_ABI64) | |
6018 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); | |
6019 | else | |
6020 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); | |
6021 | ||
6022 | if (! ok) | |
6023 | as_warn (_("Could not set architecture and machine")); | |
800eeca4 JW |
6024 | |
6025 | md.mem_offset.hint = 0; | |
6026 | md.path = 0; | |
6027 | md.maxpaths = 0; | |
6028 | md.entry_labels = NULL; | |
6029 | } | |
6030 | ||
44f5c83a JW |
6031 | /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin |
6032 | because that is called after md_parse_option which is where we do the | |
6033 | dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the | |
6034 | default endianness. */ | |
6035 | ||
6036 | void | |
6037 | ia64_init (argc, argv) | |
6038 | int argc; | |
6039 | char **argv; | |
6040 | { | |
6041 | md.flags = EF_IA_64_ABI64; | |
6042 | if (TARGET_BYTES_BIG_ENDIAN) | |
6043 | md.flags |= EF_IA_64_BE; | |
6044 | } | |
6045 | ||
6046 | /* Return a string for the target object file format. */ | |
6047 | ||
6048 | const char * | |
6049 | ia64_target_format () | |
6050 | { | |
6051 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
6052 | { | |
6053 | if (md.flags & EF_IA_64_ABI64) | |
6054 | return "elf64-ia64-big"; | |
6055 | else | |
6056 | return "elf32-ia64-big"; | |
6057 | } | |
6058 | else | |
6059 | return "unknown-format"; | |
6060 | } | |
6061 | ||
800eeca4 JW |
6062 | void |
6063 | ia64_end_of_source () | |
6064 | { | |
542d6675 | 6065 | /* terminate insn group upon reaching end of file: */ |
800eeca4 JW |
6066 | insn_group_break (1, 0, 0); |
6067 | ||
542d6675 | 6068 | /* emits slots we haven't written yet: */ |
800eeca4 JW |
6069 | ia64_flush_insns (); |
6070 | ||
6071 | bfd_set_private_flags (stdoutput, md.flags); | |
6072 | ||
6073 | if (debug_type == DEBUG_DWARF2) | |
6074 | dwarf2_finish (); | |
6075 | ||
6076 | md.mem_offset.hint = 0; | |
6077 | } | |
6078 | ||
6079 | void | |
6080 | ia64_start_line () | |
6081 | { | |
f1bcba5b JW |
6082 | if (md.qp.X_op == O_register) |
6083 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
6084 | md.qp.X_op = O_absent; |
6085 | ||
6086 | if (ignore_input ()) | |
6087 | return; | |
6088 | ||
6089 | if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') | |
6090 | { | |
6091 | if (md.detect_dv && !md.explicit_mode) | |
542d6675 | 6092 | as_warn (_("Explicit stops are ignored in auto mode")); |
800eeca4 | 6093 | else |
542d6675 | 6094 | insn_group_break (1, 0, 0); |
800eeca4 JW |
6095 | } |
6096 | } | |
6097 | ||
f1bcba5b JW |
6098 | /* This is a hook for ia64_frob_label, so that it can distinguish tags from |
6099 | labels. */ | |
6100 | static int defining_tag = 0; | |
6101 | ||
800eeca4 JW |
6102 | int |
6103 | ia64_unrecognized_line (ch) | |
6104 | int ch; | |
6105 | { | |
6106 | switch (ch) | |
6107 | { | |
6108 | case '(': | |
6109 | expression (&md.qp); | |
6110 | if (*input_line_pointer++ != ')') | |
6111 | { | |
6112 | as_bad ("Expected ')'"); | |
6113 | return 0; | |
6114 | } | |
6115 | if (md.qp.X_op != O_register) | |
6116 | { | |
6117 | as_bad ("Qualifying predicate expected"); | |
6118 | return 0; | |
6119 | } | |
6120 | if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) | |
6121 | { | |
6122 | as_bad ("Predicate register expected"); | |
6123 | return 0; | |
6124 | } | |
6125 | return 1; | |
6126 | ||
6127 | case '{': | |
6128 | if (md.manual_bundling) | |
6129 | as_warn ("Found '{' when manual bundling is already turned on"); | |
6130 | else | |
6131 | CURR_SLOT.manual_bundling_on = 1; | |
6132 | md.manual_bundling = 1; | |
6133 | ||
542d6675 KH |
6134 | /* Bundling is only acceptable in explicit mode |
6135 | or when in default automatic mode. */ | |
800eeca4 | 6136 | if (md.detect_dv && !md.explicit_mode) |
542d6675 KH |
6137 | { |
6138 | if (!md.mode_explicitly_set | |
6139 | && !md.default_explicit_mode) | |
6140 | dot_dv_mode ('E'); | |
6141 | else | |
6142 | as_warn (_("Found '{' after explicit switch to automatic mode")); | |
6143 | } | |
800eeca4 JW |
6144 | return 1; |
6145 | ||
6146 | case '}': | |
6147 | if (!md.manual_bundling) | |
6148 | as_warn ("Found '}' when manual bundling is off"); | |
6149 | else | |
6150 | PREV_SLOT.manual_bundling_off = 1; | |
6151 | md.manual_bundling = 0; | |
6152 | ||
6153 | /* switch back to automatic mode, if applicable */ | |
197865e8 | 6154 | if (md.detect_dv |
542d6675 KH |
6155 | && md.explicit_mode |
6156 | && !md.mode_explicitly_set | |
6157 | && !md.default_explicit_mode) | |
6158 | dot_dv_mode ('A'); | |
800eeca4 JW |
6159 | |
6160 | /* Allow '{' to follow on the same line. We also allow ";;", but that | |
6161 | happens automatically because ';' is an end of line marker. */ | |
6162 | SKIP_WHITESPACE (); | |
6163 | if (input_line_pointer[0] == '{') | |
6164 | { | |
6165 | input_line_pointer++; | |
6166 | return ia64_unrecognized_line ('{'); | |
6167 | } | |
6168 | ||
6169 | demand_empty_rest_of_line (); | |
6170 | return 1; | |
6171 | ||
f1bcba5b JW |
6172 | case '[': |
6173 | { | |
6174 | char *s; | |
6175 | char c; | |
6176 | symbolS *tag; | |
6177 | ||
6178 | if (md.qp.X_op == O_register) | |
6179 | { | |
6180 | as_bad ("Tag must come before qualifying predicate."); | |
6181 | return 0; | |
6182 | } | |
6183 | s = input_line_pointer; | |
6184 | c = get_symbol_end (); | |
6185 | if (c != ':') | |
6186 | { | |
6187 | /* Put ':' back for error messages' sake. */ | |
6188 | *input_line_pointer++ = ':'; | |
6189 | as_bad ("Expected ':'"); | |
6190 | return 0; | |
6191 | } | |
6192 | defining_tag = 1; | |
6193 | tag = colon (s); | |
6194 | defining_tag = 0; | |
6195 | /* Put ':' back for error messages' sake. */ | |
6196 | *input_line_pointer++ = ':'; | |
6197 | if (*input_line_pointer++ != ']') | |
6198 | { | |
6199 | as_bad ("Expected ']'"); | |
6200 | return 0; | |
6201 | } | |
6202 | if (! tag) | |
6203 | { | |
6204 | as_bad ("Tag name expected"); | |
6205 | return 0; | |
6206 | } | |
6207 | return 1; | |
6208 | } | |
6209 | ||
800eeca4 JW |
6210 | default: |
6211 | break; | |
6212 | } | |
542d6675 KH |
6213 | |
6214 | /* Not a valid line. */ | |
6215 | return 0; | |
800eeca4 JW |
6216 | } |
6217 | ||
6218 | void | |
6219 | ia64_frob_label (sym) | |
6220 | struct symbol *sym; | |
6221 | { | |
6222 | struct label_fix *fix; | |
6223 | ||
f1bcba5b JW |
6224 | /* Tags need special handling since they are not bundle breaks like |
6225 | labels. */ | |
6226 | if (defining_tag) | |
6227 | { | |
6228 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
6229 | fix->sym = sym; | |
6230 | fix->next = CURR_SLOT.tag_fixups; | |
6231 | CURR_SLOT.tag_fixups = fix; | |
6232 | ||
6233 | return; | |
6234 | } | |
6235 | ||
800eeca4 JW |
6236 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
6237 | { | |
6238 | md.last_text_seg = now_seg; | |
6239 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
6240 | fix->sym = sym; | |
6241 | fix->next = CURR_SLOT.label_fixups; | |
6242 | CURR_SLOT.label_fixups = fix; | |
6243 | ||
542d6675 | 6244 | /* Keep track of how many code entry points we've seen. */ |
800eeca4 | 6245 | if (md.path == md.maxpaths) |
542d6675 KH |
6246 | { |
6247 | md.maxpaths += 20; | |
6248 | md.entry_labels = (const char **) | |
6249 | xrealloc ((void *) md.entry_labels, | |
6250 | md.maxpaths * sizeof (char *)); | |
6251 | } | |
800eeca4 JW |
6252 | md.entry_labels[md.path++] = S_GET_NAME (sym); |
6253 | } | |
6254 | } | |
6255 | ||
6256 | void | |
6257 | ia64_flush_pending_output () | |
6258 | { | |
6259 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) | |
6260 | { | |
6261 | /* ??? This causes many unnecessary stop bits to be emitted. | |
6262 | Unfortunately, it isn't clear if it is safe to remove this. */ | |
6263 | insn_group_break (1, 0, 0); | |
6264 | ia64_flush_insns (); | |
6265 | } | |
6266 | } | |
6267 | ||
6268 | /* Do ia64-specific expression optimization. All that's done here is | |
6269 | to transform index expressions that are either due to the indexing | |
6270 | of rotating registers or due to the indexing of indirect register | |
6271 | sets. */ | |
6272 | int | |
6273 | ia64_optimize_expr (l, op, r) | |
6274 | expressionS *l; | |
6275 | operatorT op; | |
6276 | expressionS *r; | |
6277 | { | |
6278 | unsigned num_regs; | |
6279 | ||
6280 | if (op == O_index) | |
6281 | { | |
6282 | if (l->X_op == O_register && r->X_op == O_constant) | |
6283 | { | |
6284 | num_regs = (l->X_add_number >> 16); | |
6285 | if ((unsigned) r->X_add_number >= num_regs) | |
6286 | { | |
6287 | if (!num_regs) | |
6288 | as_bad ("No current frame"); | |
6289 | else | |
6290 | as_bad ("Index out of range 0..%u", num_regs - 1); | |
6291 | r->X_add_number = 0; | |
6292 | } | |
6293 | l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; | |
6294 | return 1; | |
6295 | } | |
6296 | else if (l->X_op == O_register && r->X_op == O_register) | |
6297 | { | |
6298 | if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR | |
6299 | || l->X_add_number == IND_MEM) | |
6300 | { | |
6301 | as_bad ("Indirect register set name expected"); | |
6302 | l->X_add_number = IND_CPUID; | |
6303 | } | |
6304 | l->X_op = O_index; | |
6305 | l->X_op_symbol = md.regsym[l->X_add_number]; | |
6306 | l->X_add_number = r->X_add_number; | |
6307 | return 1; | |
6308 | } | |
6309 | } | |
6310 | return 0; | |
6311 | } | |
6312 | ||
6313 | int | |
6314 | ia64_parse_name (name, e) | |
6315 | char *name; | |
6316 | expressionS *e; | |
6317 | { | |
6318 | struct const_desc *cdesc; | |
6319 | struct dynreg *dr = 0; | |
6320 | unsigned int regnum; | |
6321 | struct symbol *sym; | |
6322 | char *end; | |
6323 | ||
542d6675 | 6324 | /* first see if NAME is a known register name: */ |
800eeca4 JW |
6325 | sym = hash_find (md.reg_hash, name); |
6326 | if (sym) | |
6327 | { | |
6328 | e->X_op = O_register; | |
6329 | e->X_add_number = S_GET_VALUE (sym); | |
6330 | return 1; | |
6331 | } | |
6332 | ||
6333 | cdesc = hash_find (md.const_hash, name); | |
6334 | if (cdesc) | |
6335 | { | |
6336 | e->X_op = O_constant; | |
6337 | e->X_add_number = cdesc->value; | |
6338 | return 1; | |
6339 | } | |
6340 | ||
542d6675 | 6341 | /* check for inN, locN, or outN: */ |
800eeca4 JW |
6342 | switch (name[0]) |
6343 | { | |
6344 | case 'i': | |
6345 | if (name[1] == 'n' && isdigit (name[2])) | |
6346 | { | |
6347 | dr = &md.in; | |
6348 | name += 2; | |
6349 | } | |
6350 | break; | |
6351 | ||
6352 | case 'l': | |
6353 | if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3])) | |
6354 | { | |
6355 | dr = &md.loc; | |
6356 | name += 3; | |
6357 | } | |
6358 | break; | |
6359 | ||
6360 | case 'o': | |
6361 | if (name[1] == 'u' && name[2] == 't' && isdigit (name[3])) | |
6362 | { | |
6363 | dr = &md.out; | |
6364 | name += 3; | |
6365 | } | |
6366 | break; | |
6367 | ||
6368 | default: | |
6369 | break; | |
6370 | } | |
6371 | ||
6372 | if (dr) | |
6373 | { | |
542d6675 | 6374 | /* The name is inN, locN, or outN; parse the register number. */ |
800eeca4 JW |
6375 | regnum = strtoul (name, &end, 10); |
6376 | if (end > name && *end == '\0') | |
6377 | { | |
6378 | if ((unsigned) regnum >= dr->num_regs) | |
6379 | { | |
6380 | if (!dr->num_regs) | |
6381 | as_bad ("No current frame"); | |
6382 | else | |
542d6675 KH |
6383 | as_bad ("Register number out of range 0..%u", |
6384 | dr->num_regs - 1); | |
800eeca4 JW |
6385 | regnum = 0; |
6386 | } | |
6387 | e->X_op = O_register; | |
6388 | e->X_add_number = dr->base + regnum; | |
6389 | return 1; | |
6390 | } | |
6391 | } | |
6392 | ||
6393 | if ((dr = hash_find (md.dynreg_hash, name))) | |
6394 | { | |
6395 | /* We've got ourselves the name of a rotating register set. | |
542d6675 KH |
6396 | Store the base register number in the low 16 bits of |
6397 | X_add_number and the size of the register set in the top 16 | |
6398 | bits. */ | |
800eeca4 JW |
6399 | e->X_op = O_register; |
6400 | e->X_add_number = dr->base | (dr->num_regs << 16); | |
6401 | return 1; | |
6402 | } | |
6403 | return 0; | |
6404 | } | |
6405 | ||
6406 | /* Remove the '#' suffix that indicates a symbol as opposed to a register. */ | |
6407 | ||
6408 | char * | |
6409 | ia64_canonicalize_symbol_name (name) | |
6410 | char *name; | |
6411 | { | |
542d6675 KH |
6412 | size_t len = strlen (name); |
6413 | if (len > 1 && name[len - 1] == '#') | |
6414 | name[len - 1] = '\0'; | |
800eeca4 JW |
6415 | return name; |
6416 | } | |
6417 | ||
6418 | static int | |
6419 | is_conditional_branch (idesc) | |
542d6675 | 6420 | struct ia64_opcode *idesc; |
800eeca4 JW |
6421 | { |
6422 | return (strncmp (idesc->name, "br", 2) == 0 | |
542d6675 KH |
6423 | && (strcmp (idesc->name, "br") == 0 |
6424 | || strncmp (idesc->name, "br.cond", 7) == 0 | |
6425 | || strncmp (idesc->name, "br.call", 7) == 0 | |
6426 | || strncmp (idesc->name, "br.ret", 6) == 0 | |
6427 | || strcmp (idesc->name, "brl") == 0 | |
6428 | || strncmp (idesc->name, "brl.cond", 7) == 0 | |
6429 | || strncmp (idesc->name, "brl.call", 7) == 0 | |
6430 | || strncmp (idesc->name, "brl.ret", 6) == 0)); | |
800eeca4 JW |
6431 | } |
6432 | ||
6433 | /* Return whether the given opcode is a taken branch. If there's any doubt, | |
542d6675 KH |
6434 | returns zero. */ |
6435 | ||
800eeca4 JW |
6436 | static int |
6437 | is_taken_branch (idesc) | |
542d6675 | 6438 | struct ia64_opcode *idesc; |
800eeca4 JW |
6439 | { |
6440 | return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) | |
542d6675 | 6441 | || strncmp (idesc->name, "br.ia", 5) == 0); |
800eeca4 JW |
6442 | } |
6443 | ||
6444 | /* Return whether the given opcode is an interruption or rfi. If there's any | |
542d6675 KH |
6445 | doubt, returns zero. */ |
6446 | ||
800eeca4 JW |
6447 | static int |
6448 | is_interruption_or_rfi (idesc) | |
542d6675 | 6449 | struct ia64_opcode *idesc; |
800eeca4 JW |
6450 | { |
6451 | if (strcmp (idesc->name, "rfi") == 0) | |
6452 | return 1; | |
6453 | return 0; | |
6454 | } | |
6455 | ||
6456 | /* Returns the index of the given dependency in the opcode's list of chks, or | |
6457 | -1 if there is no dependency. */ | |
542d6675 | 6458 | |
800eeca4 JW |
6459 | static int |
6460 | depends_on (depind, idesc) | |
542d6675 KH |
6461 | int depind; |
6462 | struct ia64_opcode *idesc; | |
800eeca4 JW |
6463 | { |
6464 | int i; | |
6465 | const struct ia64_opcode_dependency *dep = idesc->dependencies; | |
542d6675 | 6466 | for (i = 0; i < dep->nchks; i++) |
800eeca4 | 6467 | { |
542d6675 KH |
6468 | if (depind == DEP (dep->chks[i])) |
6469 | return i; | |
800eeca4 JW |
6470 | } |
6471 | return -1; | |
6472 | } | |
6473 | ||
6474 | /* Determine a set of specific resources used for a particular resource | |
6475 | class. Returns the number of specific resources identified For those | |
6476 | cases which are not determinable statically, the resource returned is | |
197865e8 | 6477 | marked nonspecific. |
800eeca4 JW |
6478 | |
6479 | Meanings of value in 'NOTE': | |
6480 | 1) only read/write when the register number is explicitly encoded in the | |
6481 | insn. | |
6482 | 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only | |
197865e8 | 6483 | accesses CFM when qualifying predicate is in the rotating region. |
800eeca4 JW |
6484 | 3) general register value is used to specify an indirect register; not |
6485 | determinable statically. | |
6486 | 4) only read the given resource when bits 7:0 of the indirect index | |
6487 | register value does not match the register number of the resource; not | |
6488 | determinable statically. | |
6489 | 5) all rules are implementation specific. | |
6490 | 6) only when both the index specified by the reader and the index specified | |
6491 | by the writer have the same value in bits 63:61; not determinable | |
197865e8 | 6492 | statically. |
800eeca4 | 6493 | 7) only access the specified resource when the corresponding mask bit is |
197865e8 | 6494 | set |
800eeca4 JW |
6495 | 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is |
6496 | only read when these insns reference FR2-31 | |
6497 | 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only | |
6498 | written when these insns write FR32-127 | |
6499 | 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the | |
6500 | instruction | |
6501 | 11) The target predicates are written independently of PR[qp], but source | |
6502 | registers are only read if PR[qp] is true. Since the state of PR[qp] | |
6503 | cannot statically be determined, all source registers are marked used. | |
6504 | 12) This insn only reads the specified predicate register when that | |
6505 | register is the PR[qp]. | |
6506 | 13) This reference to ld-c only applies to teh GR whose value is loaded | |
197865e8 | 6507 | with data returned from memory, not the post-incremented address register. |
800eeca4 JW |
6508 | 14) The RSE resource includes the implementation-specific RSE internal |
6509 | state resources. At least one (and possibly more) of these resources are | |
6510 | read by each instruction listed in IC:rse-readers. At least one (and | |
6511 | possibly more) of these resources are written by each insn listed in | |
197865e8 | 6512 | IC:rse-writers. |
800eeca4 | 6513 | 15+16) Represents reserved instructions, which the assembler does not |
197865e8 | 6514 | generate. |
800eeca4 JW |
6515 | |
6516 | Memory resources (i.e. locations in memory) are *not* marked or tracked by | |
6517 | this code; there are no dependency violations based on memory access. | |
800eeca4 JW |
6518 | */ |
6519 | ||
6520 | #define MAX_SPECS 256 | |
6521 | #define DV_CHK 1 | |
6522 | #define DV_REG 0 | |
6523 | ||
6524 | static int | |
6525 | specify_resource (dep, idesc, type, specs, note, path) | |
542d6675 KH |
6526 | const struct ia64_dependency *dep; |
6527 | struct ia64_opcode *idesc; | |
6528 | int type; /* is this a DV chk or a DV reg? */ | |
6529 | struct rsrc specs[MAX_SPECS]; /* returned specific resources */ | |
6530 | int note; /* resource note for this insn's usage */ | |
6531 | int path; /* which execution path to examine */ | |
800eeca4 JW |
6532 | { |
6533 | int count = 0; | |
6534 | int i; | |
6535 | int rsrc_write = 0; | |
6536 | struct rsrc tmpl; | |
197865e8 | 6537 | |
800eeca4 JW |
6538 | if (dep->mode == IA64_DV_WAW |
6539 | || (dep->mode == IA64_DV_RAW && type == DV_REG) | |
6540 | || (dep->mode == IA64_DV_WAR && type == DV_CHK)) | |
6541 | rsrc_write = 1; | |
6542 | ||
6543 | /* template for any resources we identify */ | |
6544 | tmpl.dependency = dep; | |
6545 | tmpl.note = note; | |
6546 | tmpl.insn_srlz = tmpl.data_srlz = 0; | |
6547 | tmpl.qp_regno = CURR_SLOT.qp_regno; | |
6548 | tmpl.link_to_qp_branch = 1; | |
6549 | tmpl.mem_offset.hint = 0; | |
6550 | tmpl.specific = 1; | |
6551 | tmpl.index = 0; | |
7484b8e6 | 6552 | tmpl.cmp_type = CMP_NONE; |
800eeca4 JW |
6553 | |
6554 | #define UNHANDLED \ | |
6555 | as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ | |
6556 | dep->name, idesc->name, (rsrc_write?"write":"read"), note) | |
6557 | #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) | |
6558 | ||
6559 | /* we don't need to track these */ | |
6560 | if (dep->semantics == IA64_DVS_NONE) | |
6561 | return 0; | |
6562 | ||
6563 | switch (dep->specifier) | |
6564 | { | |
6565 | case IA64_RS_AR_K: | |
6566 | if (note == 1) | |
542d6675 KH |
6567 | { |
6568 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
6569 | { | |
6570 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
6571 | if (regno >= 0 && regno <= 7) | |
6572 | { | |
6573 | specs[count] = tmpl; | |
6574 | specs[count++].index = regno; | |
6575 | } | |
6576 | } | |
6577 | } | |
800eeca4 | 6578 | else if (note == 0) |
542d6675 KH |
6579 | { |
6580 | for (i = 0; i < 8; i++) | |
6581 | { | |
6582 | specs[count] = tmpl; | |
6583 | specs[count++].index = i; | |
6584 | } | |
6585 | } | |
800eeca4 | 6586 | else |
542d6675 KH |
6587 | { |
6588 | UNHANDLED; | |
6589 | } | |
800eeca4 JW |
6590 | break; |
6591 | ||
6592 | case IA64_RS_AR_UNAT: | |
6593 | /* This is a mov =AR or mov AR= instruction. */ | |
6594 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
6595 | { | |
6596 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
6597 | if (regno == AR_UNAT) | |
6598 | { | |
6599 | specs[count++] = tmpl; | |
6600 | } | |
6601 | } | |
6602 | else | |
6603 | { | |
6604 | /* This is a spill/fill, or other instruction that modifies the | |
6605 | unat register. */ | |
6606 | ||
6607 | /* Unless we can determine the specific bits used, mark the whole | |
6608 | thing; bits 8:3 of the memory address indicate the bit used in | |
6609 | UNAT. The .mem.offset hint may be used to eliminate a small | |
6610 | subset of conflicts. */ | |
6611 | specs[count] = tmpl; | |
6612 | if (md.mem_offset.hint) | |
6613 | { | |
542d6675 KH |
6614 | if (md.debug_dv) |
6615 | fprintf (stderr, " Using hint for spill/fill\n"); | |
6616 | /* The index isn't actually used, just set it to something | |
6617 | approximating the bit index. */ | |
800eeca4 JW |
6618 | specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; |
6619 | specs[count].mem_offset.hint = 1; | |
6620 | specs[count].mem_offset.offset = md.mem_offset.offset; | |
6621 | specs[count++].mem_offset.base = md.mem_offset.base; | |
6622 | } | |
6623 | else | |
6624 | { | |
6625 | specs[count++].specific = 0; | |
6626 | } | |
6627 | } | |
6628 | break; | |
6629 | ||
6630 | case IA64_RS_AR: | |
6631 | if (note == 1) | |
542d6675 KH |
6632 | { |
6633 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
6634 | { | |
6635 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
6636 | if ((regno >= 8 && regno <= 15) | |
6637 | || (regno >= 20 && regno <= 23) | |
6638 | || (regno >= 31 && regno <= 39) | |
6639 | || (regno >= 41 && regno <= 47) | |
6640 | || (regno >= 67 && regno <= 111)) | |
6641 | { | |
6642 | specs[count] = tmpl; | |
6643 | specs[count++].index = regno; | |
6644 | } | |
6645 | } | |
6646 | } | |
800eeca4 | 6647 | else |
542d6675 KH |
6648 | { |
6649 | UNHANDLED; | |
6650 | } | |
800eeca4 JW |
6651 | break; |
6652 | ||
6653 | case IA64_RS_ARb: | |
6654 | if (note == 1) | |
542d6675 KH |
6655 | { |
6656 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
6657 | { | |
6658 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
6659 | if ((regno >= 48 && regno <= 63) | |
6660 | || (regno >= 112 && regno <= 127)) | |
6661 | { | |
6662 | specs[count] = tmpl; | |
6663 | specs[count++].index = regno; | |
6664 | } | |
6665 | } | |
6666 | } | |
800eeca4 | 6667 | else if (note == 0) |
542d6675 KH |
6668 | { |
6669 | for (i = 48; i < 64; i++) | |
6670 | { | |
6671 | specs[count] = tmpl; | |
6672 | specs[count++].index = i; | |
6673 | } | |
6674 | for (i = 112; i < 128; i++) | |
6675 | { | |
6676 | specs[count] = tmpl; | |
6677 | specs[count++].index = i; | |
6678 | } | |
6679 | } | |
197865e8 | 6680 | else |
542d6675 KH |
6681 | { |
6682 | UNHANDLED; | |
6683 | } | |
800eeca4 JW |
6684 | break; |
6685 | ||
6686 | case IA64_RS_BR: | |
6687 | if (note != 1) | |
542d6675 KH |
6688 | { |
6689 | UNHANDLED; | |
6690 | } | |
800eeca4 | 6691 | else |
542d6675 KH |
6692 | { |
6693 | if (rsrc_write) | |
6694 | { | |
6695 | for (i = 0; i < idesc->num_outputs; i++) | |
6696 | if (idesc->operands[i] == IA64_OPND_B1 | |
6697 | || idesc->operands[i] == IA64_OPND_B2) | |
6698 | { | |
6699 | specs[count] = tmpl; | |
6700 | specs[count++].index = | |
6701 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
6702 | } | |
6703 | } | |
6704 | else | |
6705 | { | |
6706 | for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++) | |
6707 | if (idesc->operands[i] == IA64_OPND_B1 | |
6708 | || idesc->operands[i] == IA64_OPND_B2) | |
6709 | { | |
6710 | specs[count] = tmpl; | |
6711 | specs[count++].index = | |
6712 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
6713 | } | |
6714 | } | |
6715 | } | |
800eeca4 JW |
6716 | break; |
6717 | ||
6718 | case IA64_RS_CPUID: /* four or more registers */ | |
6719 | if (note == 3) | |
542d6675 KH |
6720 | { |
6721 | if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) | |
6722 | { | |
6723 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6724 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6725 | && KNOWN (regno)) | |
6726 | { | |
6727 | specs[count] = tmpl; | |
6728 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6729 | } | |
6730 | else | |
6731 | { | |
6732 | specs[count] = tmpl; | |
6733 | specs[count++].specific = 0; | |
6734 | } | |
6735 | } | |
6736 | } | |
800eeca4 | 6737 | else |
542d6675 KH |
6738 | { |
6739 | UNHANDLED; | |
6740 | } | |
800eeca4 JW |
6741 | break; |
6742 | ||
6743 | case IA64_RS_DBR: /* four or more registers */ | |
6744 | if (note == 3) | |
542d6675 KH |
6745 | { |
6746 | if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) | |
6747 | { | |
6748 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6749 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6750 | && KNOWN (regno)) | |
6751 | { | |
6752 | specs[count] = tmpl; | |
6753 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6754 | } | |
6755 | else | |
6756 | { | |
6757 | specs[count] = tmpl; | |
6758 | specs[count++].specific = 0; | |
6759 | } | |
6760 | } | |
6761 | } | |
800eeca4 | 6762 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
6763 | { |
6764 | specs[count] = tmpl; | |
6765 | specs[count++].specific = 0; | |
6766 | } | |
800eeca4 | 6767 | else |
542d6675 KH |
6768 | { |
6769 | UNHANDLED; | |
6770 | } | |
800eeca4 JW |
6771 | break; |
6772 | ||
6773 | case IA64_RS_IBR: /* four or more registers */ | |
6774 | if (note == 3) | |
542d6675 KH |
6775 | { |
6776 | if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) | |
6777 | { | |
6778 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6779 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6780 | && KNOWN (regno)) | |
6781 | { | |
6782 | specs[count] = tmpl; | |
6783 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6784 | } | |
6785 | else | |
6786 | { | |
6787 | specs[count] = tmpl; | |
6788 | specs[count++].specific = 0; | |
6789 | } | |
6790 | } | |
6791 | } | |
800eeca4 | 6792 | else |
542d6675 KH |
6793 | { |
6794 | UNHANDLED; | |
6795 | } | |
800eeca4 JW |
6796 | break; |
6797 | ||
6798 | case IA64_RS_MSR: | |
6799 | if (note == 5) | |
6800 | { | |
6801 | /* These are implementation specific. Force all references to | |
6802 | conflict with all other references. */ | |
6803 | specs[count] = tmpl; | |
6804 | specs[count++].specific = 0; | |
6805 | } | |
6806 | else | |
6807 | { | |
6808 | UNHANDLED; | |
6809 | } | |
6810 | break; | |
6811 | ||
6812 | case IA64_RS_PKR: /* 16 or more registers */ | |
6813 | if (note == 3 || note == 4) | |
542d6675 KH |
6814 | { |
6815 | if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) | |
6816 | { | |
6817 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6818 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6819 | && KNOWN (regno)) | |
6820 | { | |
6821 | if (note == 3) | |
6822 | { | |
6823 | specs[count] = tmpl; | |
6824 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6825 | } | |
6826 | else | |
6827 | for (i = 0; i < NELEMS (gr_values); i++) | |
6828 | { | |
6829 | /* Uses all registers *except* the one in R3. */ | |
6830 | if (i != (gr_values[regno].value & 0xFF)) | |
6831 | { | |
6832 | specs[count] = tmpl; | |
6833 | specs[count++].index = i; | |
6834 | } | |
6835 | } | |
6836 | } | |
6837 | else | |
6838 | { | |
6839 | specs[count] = tmpl; | |
6840 | specs[count++].specific = 0; | |
6841 | } | |
6842 | } | |
6843 | } | |
6844 | else if (note == 0) | |
6845 | { | |
6846 | /* probe et al. */ | |
6847 | specs[count] = tmpl; | |
6848 | specs[count++].specific = 0; | |
6849 | } | |
6850 | break; | |
6851 | ||
6852 | case IA64_RS_PMC: /* four or more registers */ | |
6853 | if (note == 3) | |
6854 | { | |
6855 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 | |
6856 | || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) | |
6857 | ||
6858 | { | |
6859 | int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) | |
6860 | ? 1 : !rsrc_write); | |
6861 | int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; | |
6862 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6863 | && KNOWN (regno)) | |
6864 | { | |
6865 | specs[count] = tmpl; | |
6866 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6867 | } | |
6868 | else | |
6869 | { | |
6870 | specs[count] = tmpl; | |
6871 | specs[count++].specific = 0; | |
6872 | } | |
6873 | } | |
6874 | } | |
6875 | else | |
6876 | { | |
6877 | UNHANDLED; | |
6878 | } | |
800eeca4 JW |
6879 | break; |
6880 | ||
6881 | case IA64_RS_PMD: /* four or more registers */ | |
6882 | if (note == 3) | |
542d6675 KH |
6883 | { |
6884 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) | |
6885 | { | |
6886 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6887 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6888 | && KNOWN (regno)) | |
6889 | { | |
6890 | specs[count] = tmpl; | |
6891 | specs[count++].index = gr_values[regno].value & 0xFF; | |
6892 | } | |
6893 | else | |
6894 | { | |
6895 | specs[count] = tmpl; | |
6896 | specs[count++].specific = 0; | |
6897 | } | |
6898 | } | |
6899 | } | |
800eeca4 | 6900 | else |
542d6675 KH |
6901 | { |
6902 | UNHANDLED; | |
6903 | } | |
800eeca4 JW |
6904 | break; |
6905 | ||
6906 | case IA64_RS_RR: /* eight registers */ | |
6907 | if (note == 6) | |
542d6675 KH |
6908 | { |
6909 | if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) | |
6910 | { | |
6911 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
6912 | if (regno >= 0 && regno < NELEMS (gr_values) | |
6913 | && KNOWN (regno)) | |
6914 | { | |
6915 | specs[count] = tmpl; | |
6916 | specs[count++].index = (gr_values[regno].value >> 61) & 0x7; | |
6917 | } | |
6918 | else | |
6919 | { | |
6920 | specs[count] = tmpl; | |
6921 | specs[count++].specific = 0; | |
6922 | } | |
6923 | } | |
6924 | } | |
800eeca4 | 6925 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
6926 | { |
6927 | specs[count] = tmpl; | |
6928 | specs[count++].specific = 0; | |
6929 | } | |
197865e8 | 6930 | else |
542d6675 KH |
6931 | { |
6932 | UNHANDLED; | |
6933 | } | |
800eeca4 JW |
6934 | break; |
6935 | ||
6936 | case IA64_RS_CR_IRR: | |
197865e8 | 6937 | if (note == 0) |
542d6675 KH |
6938 | { |
6939 | /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ | |
6940 | int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; | |
6941 | if (rsrc_write | |
6942 | && idesc->operands[1] == IA64_OPND_CR3 | |
6943 | && regno == CR_IVR) | |
6944 | { | |
6945 | for (i = 0; i < 4; i++) | |
6946 | { | |
6947 | specs[count] = tmpl; | |
6948 | specs[count++].index = CR_IRR0 + i; | |
6949 | } | |
6950 | } | |
6951 | } | |
800eeca4 | 6952 | else if (note == 1) |
542d6675 KH |
6953 | { |
6954 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
6955 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
6956 | && regno >= CR_IRR0 | |
6957 | && regno <= CR_IRR3) | |
6958 | { | |
6959 | specs[count] = tmpl; | |
6960 | specs[count++].index = regno; | |
6961 | } | |
6962 | } | |
800eeca4 | 6963 | else |
542d6675 KH |
6964 | { |
6965 | UNHANDLED; | |
6966 | } | |
800eeca4 JW |
6967 | break; |
6968 | ||
6969 | case IA64_RS_CR_LRR: | |
6970 | if (note != 1) | |
542d6675 KH |
6971 | { |
6972 | UNHANDLED; | |
6973 | } | |
197865e8 | 6974 | else |
542d6675 KH |
6975 | { |
6976 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
6977 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
6978 | && (regno == CR_LRR0 || regno == CR_LRR1)) | |
6979 | { | |
6980 | specs[count] = tmpl; | |
6981 | specs[count++].index = regno; | |
6982 | } | |
6983 | } | |
800eeca4 JW |
6984 | break; |
6985 | ||
6986 | case IA64_RS_CR: | |
6987 | if (note == 1) | |
542d6675 KH |
6988 | { |
6989 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
6990 | { | |
6991 | specs[count] = tmpl; | |
6992 | specs[count++].index = | |
6993 | CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
6994 | } | |
6995 | } | |
800eeca4 | 6996 | else |
542d6675 KH |
6997 | { |
6998 | UNHANDLED; | |
6999 | } | |
800eeca4 JW |
7000 | break; |
7001 | ||
7002 | case IA64_RS_FR: | |
7003 | case IA64_RS_FRb: | |
7004 | if (note != 1) | |
542d6675 KH |
7005 | { |
7006 | UNHANDLED; | |
7007 | } | |
800eeca4 | 7008 | else if (rsrc_write) |
542d6675 KH |
7009 | { |
7010 | if (dep->specifier == IA64_RS_FRb | |
7011 | && idesc->operands[0] == IA64_OPND_F1) | |
7012 | { | |
7013 | specs[count] = tmpl; | |
7014 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; | |
7015 | } | |
7016 | } | |
800eeca4 | 7017 | else |
542d6675 KH |
7018 | { |
7019 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) | |
7020 | { | |
7021 | if (idesc->operands[i] == IA64_OPND_F2 | |
7022 | || idesc->operands[i] == IA64_OPND_F3 | |
7023 | || idesc->operands[i] == IA64_OPND_F4) | |
7024 | { | |
7025 | specs[count] = tmpl; | |
7026 | specs[count++].index = | |
7027 | CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7028 | } | |
7029 | } | |
7030 | } | |
800eeca4 JW |
7031 | break; |
7032 | ||
7033 | case IA64_RS_GR: | |
7034 | if (note == 13) | |
542d6675 KH |
7035 | { |
7036 | /* This reference applies only to the GR whose value is loaded with | |
7037 | data returned from memory. */ | |
7038 | specs[count] = tmpl; | |
7039 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
7040 | } | |
800eeca4 | 7041 | else if (note == 1) |
542d6675 KH |
7042 | { |
7043 | if (rsrc_write) | |
7044 | { | |
7045 | for (i = 0; i < idesc->num_outputs; i++) | |
50b81f19 JW |
7046 | if (idesc->operands[i] == IA64_OPND_R1 |
7047 | || idesc->operands[i] == IA64_OPND_R2 | |
7048 | || idesc->operands[i] == IA64_OPND_R3) | |
7049 | { | |
7050 | specs[count] = tmpl; | |
197865e8 | 7051 | specs[count++].index = |
50b81f19 JW |
7052 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
7053 | } | |
7054 | if (idesc->flags & IA64_OPCODE_POSTINC) | |
7055 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7056 | if (idesc->operands[i] == IA64_OPND_MR3) | |
7057 | { | |
7058 | specs[count] = tmpl; | |
7059 | specs[count++].index = | |
7060 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7061 | } | |
542d6675 KH |
7062 | } |
7063 | else | |
7064 | { | |
7065 | /* Look for anything that reads a GR. */ | |
7066 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7067 | { | |
7068 | if (idesc->operands[i] == IA64_OPND_MR3 | |
7069 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
7070 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
7071 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
800eeca4 | 7072 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
542d6675 KH |
7073 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
7074 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
7075 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
7076 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
7077 | || ((i >= idesc->num_outputs) | |
7078 | && (idesc->operands[i] == IA64_OPND_R1 | |
7079 | || idesc->operands[i] == IA64_OPND_R2 | |
7080 | || idesc->operands[i] == IA64_OPND_R3 | |
50b81f19 JW |
7081 | /* addl source register. */ |
7082 | || idesc->operands[i] == IA64_OPND_R3_2))) | |
542d6675 KH |
7083 | { |
7084 | specs[count] = tmpl; | |
7085 | specs[count++].index = | |
7086 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7087 | } | |
7088 | } | |
7089 | } | |
7090 | } | |
197865e8 | 7091 | else |
542d6675 KH |
7092 | { |
7093 | UNHANDLED; | |
7094 | } | |
800eeca4 JW |
7095 | break; |
7096 | ||
139368c9 JW |
7097 | /* This is the same as IA64_RS_PRr, except that the register range is |
7098 | from 1 - 15, and there are no rotating register reads/writes here. */ | |
800eeca4 JW |
7099 | case IA64_RS_PR: |
7100 | if (note == 0) | |
542d6675 | 7101 | { |
139368c9 | 7102 | for (i = 1; i < 16; i++) |
542d6675 | 7103 | { |
139368c9 JW |
7104 | specs[count] = tmpl; |
7105 | specs[count++].index = i; | |
7106 | } | |
7107 | } | |
7108 | else if (note == 7) | |
7109 | { | |
7110 | valueT mask = 0; | |
7111 | /* Mark only those registers indicated by the mask. */ | |
7112 | if (rsrc_write) | |
7113 | { | |
7114 | mask = CURR_SLOT.opnd[2].X_add_number; | |
7115 | for (i = 1; i < 16; i++) | |
7116 | if (mask & ((valueT) 1 << i)) | |
7117 | { | |
7118 | specs[count] = tmpl; | |
7119 | specs[count++].index = i; | |
7120 | } | |
7121 | } | |
7122 | else | |
7123 | { | |
7124 | UNHANDLED; | |
7125 | } | |
7126 | } | |
7127 | else if (note == 11) /* note 11 implies note 1 as well */ | |
7128 | { | |
7129 | if (rsrc_write) | |
7130 | { | |
7131 | for (i = 0; i < idesc->num_outputs; i++) | |
7132 | { | |
7133 | if (idesc->operands[i] == IA64_OPND_P1 | |
7134 | || idesc->operands[i] == IA64_OPND_P2) | |
7135 | { | |
7136 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
7137 | if (regno >= 1 && regno < 16) | |
7138 | { | |
7139 | specs[count] = tmpl; | |
7140 | specs[count++].index = regno; | |
7141 | } | |
7142 | } | |
7143 | } | |
7144 | } | |
7145 | else | |
7146 | { | |
7147 | UNHANDLED; | |
7148 | } | |
7149 | } | |
7150 | else if (note == 12) | |
7151 | { | |
7152 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) | |
7153 | { | |
7154 | specs[count] = tmpl; | |
7155 | specs[count++].index = CURR_SLOT.qp_regno; | |
7156 | } | |
7157 | } | |
7158 | else if (note == 1) | |
7159 | { | |
7160 | if (rsrc_write) | |
7161 | { | |
7162 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
7163 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
7164 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; | |
7165 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
7166 | ||
7167 | if ((idesc->operands[0] == IA64_OPND_P1 | |
7168 | || idesc->operands[0] == IA64_OPND_P2) | |
7169 | && p1 >= 1 && p1 < 16) | |
542d6675 KH |
7170 | { |
7171 | specs[count] = tmpl; | |
139368c9 JW |
7172 | specs[count].cmp_type = |
7173 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); | |
7174 | specs[count++].index = p1; | |
7175 | } | |
7176 | if ((idesc->operands[1] == IA64_OPND_P1 | |
7177 | || idesc->operands[1] == IA64_OPND_P2) | |
7178 | && p2 >= 1 && p2 < 16) | |
7179 | { | |
7180 | specs[count] = tmpl; | |
7181 | specs[count].cmp_type = | |
7182 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); | |
7183 | specs[count++].index = p2; | |
542d6675 KH |
7184 | } |
7185 | } | |
7186 | else | |
7187 | { | |
139368c9 | 7188 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
542d6675 KH |
7189 | { |
7190 | specs[count] = tmpl; | |
139368c9 JW |
7191 | specs[count++].index = CURR_SLOT.qp_regno; |
7192 | } | |
7193 | if (idesc->operands[1] == IA64_OPND_PR) | |
7194 | { | |
7195 | for (i = 1; i < 16; i++) | |
7196 | { | |
7197 | specs[count] = tmpl; | |
7198 | specs[count++].index = i; | |
7199 | } | |
542d6675 KH |
7200 | } |
7201 | } | |
7202 | } | |
139368c9 JW |
7203 | else |
7204 | { | |
7205 | UNHANDLED; | |
7206 | } | |
7207 | break; | |
7208 | ||
7209 | /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are | |
7210 | simplified cases of this. */ | |
7211 | case IA64_RS_PRr: | |
7212 | if (note == 0) | |
7213 | { | |
7214 | for (i = 16; i < 63; i++) | |
7215 | { | |
7216 | specs[count] = tmpl; | |
7217 | specs[count++].index = i; | |
7218 | } | |
7219 | } | |
800eeca4 | 7220 | else if (note == 7) |
542d6675 KH |
7221 | { |
7222 | valueT mask = 0; | |
7223 | /* Mark only those registers indicated by the mask. */ | |
7224 | if (rsrc_write | |
7225 | && idesc->operands[0] == IA64_OPND_PR) | |
7226 | { | |
7227 | mask = CURR_SLOT.opnd[2].X_add_number; | |
139368c9 JW |
7228 | if (mask & ((valueT) 1<<16)) |
7229 | for (i = 16; i < 63; i++) | |
7230 | { | |
7231 | specs[count] = tmpl; | |
7232 | specs[count++].index = i; | |
7233 | } | |
542d6675 KH |
7234 | } |
7235 | else if (rsrc_write | |
7236 | && idesc->operands[0] == IA64_OPND_PR_ROT) | |
7237 | { | |
7238 | for (i = 16; i < 63; i++) | |
7239 | { | |
7240 | specs[count] = tmpl; | |
7241 | specs[count++].index = i; | |
7242 | } | |
7243 | } | |
7244 | else | |
7245 | { | |
7246 | UNHANDLED; | |
7247 | } | |
7248 | } | |
800eeca4 | 7249 | else if (note == 11) /* note 11 implies note 1 as well */ |
542d6675 KH |
7250 | { |
7251 | if (rsrc_write) | |
7252 | { | |
7253 | for (i = 0; i < idesc->num_outputs; i++) | |
7254 | { | |
7255 | if (idesc->operands[i] == IA64_OPND_P1 | |
7256 | || idesc->operands[i] == IA64_OPND_P2) | |
7257 | { | |
7258 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
139368c9 | 7259 | if (regno >= 16 && regno < 63) |
542d6675 KH |
7260 | { |
7261 | specs[count] = tmpl; | |
7262 | specs[count++].index = regno; | |
7263 | } | |
7264 | } | |
7265 | } | |
7266 | } | |
7267 | else | |
7268 | { | |
7269 | UNHANDLED; | |
7270 | } | |
7271 | } | |
800eeca4 | 7272 | else if (note == 12) |
542d6675 | 7273 | { |
139368c9 | 7274 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
7275 | { |
7276 | specs[count] = tmpl; | |
7277 | specs[count++].index = CURR_SLOT.qp_regno; | |
7278 | } | |
7279 | } | |
800eeca4 | 7280 | else if (note == 1) |
542d6675 KH |
7281 | { |
7282 | if (rsrc_write) | |
7283 | { | |
7284 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
7285 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
7484b8e6 TW |
7286 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; |
7287 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
7288 | ||
542d6675 KH |
7289 | if ((idesc->operands[0] == IA64_OPND_P1 |
7290 | || idesc->operands[0] == IA64_OPND_P2) | |
139368c9 | 7291 | && p1 >= 16 && p1 < 63) |
542d6675 KH |
7292 | { |
7293 | specs[count] = tmpl; | |
4a4f25cf | 7294 | specs[count].cmp_type = |
7484b8e6 | 7295 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
542d6675 KH |
7296 | specs[count++].index = p1; |
7297 | } | |
7298 | if ((idesc->operands[1] == IA64_OPND_P1 | |
7299 | || idesc->operands[1] == IA64_OPND_P2) | |
139368c9 | 7300 | && p2 >= 16 && p2 < 63) |
542d6675 KH |
7301 | { |
7302 | specs[count] = tmpl; | |
4a4f25cf | 7303 | specs[count].cmp_type = |
7484b8e6 | 7304 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
542d6675 KH |
7305 | specs[count++].index = p2; |
7306 | } | |
7307 | } | |
7308 | else | |
7309 | { | |
139368c9 | 7310 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
7311 | { |
7312 | specs[count] = tmpl; | |
7313 | specs[count++].index = CURR_SLOT.qp_regno; | |
7314 | } | |
7315 | if (idesc->operands[1] == IA64_OPND_PR) | |
7316 | { | |
139368c9 | 7317 | for (i = 16; i < 63; i++) |
542d6675 KH |
7318 | { |
7319 | specs[count] = tmpl; | |
7320 | specs[count++].index = i; | |
7321 | } | |
7322 | } | |
7323 | } | |
7324 | } | |
197865e8 | 7325 | else |
542d6675 KH |
7326 | { |
7327 | UNHANDLED; | |
7328 | } | |
800eeca4 JW |
7329 | break; |
7330 | ||
7331 | case IA64_RS_PSR: | |
197865e8 | 7332 | /* Verify that the instruction is using the PSR bit indicated in |
542d6675 | 7333 | dep->regindex. */ |
800eeca4 | 7334 | if (note == 0) |
542d6675 KH |
7335 | { |
7336 | if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) | |
7337 | { | |
7338 | if (dep->regindex < 6) | |
7339 | { | |
7340 | specs[count++] = tmpl; | |
7341 | } | |
7342 | } | |
7343 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) | |
7344 | { | |
7345 | if (dep->regindex < 32 | |
7346 | || dep->regindex == 35 | |
7347 | || dep->regindex == 36 | |
7348 | || (!rsrc_write && dep->regindex == PSR_CPL)) | |
7349 | { | |
7350 | specs[count++] = tmpl; | |
7351 | } | |
7352 | } | |
7353 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) | |
7354 | { | |
7355 | if (dep->regindex < 32 | |
7356 | || dep->regindex == 35 | |
7357 | || dep->regindex == 36 | |
7358 | || (rsrc_write && dep->regindex == PSR_CPL)) | |
7359 | { | |
7360 | specs[count++] = tmpl; | |
7361 | } | |
7362 | } | |
7363 | else | |
7364 | { | |
7365 | /* Several PSR bits have very specific dependencies. */ | |
7366 | switch (dep->regindex) | |
7367 | { | |
7368 | default: | |
7369 | specs[count++] = tmpl; | |
7370 | break; | |
7371 | case PSR_IC: | |
7372 | if (rsrc_write) | |
7373 | { | |
7374 | specs[count++] = tmpl; | |
7375 | } | |
7376 | else | |
7377 | { | |
7378 | /* Only certain CR accesses use PSR.ic */ | |
7379 | if (idesc->operands[0] == IA64_OPND_CR3 | |
7380 | || idesc->operands[1] == IA64_OPND_CR3) | |
7381 | { | |
7382 | int index = | |
7383 | ((idesc->operands[0] == IA64_OPND_CR3) | |
7384 | ? 0 : 1); | |
7385 | int regno = | |
7386 | CURR_SLOT.opnd[index].X_add_number - REG_CR; | |
7387 | ||
7388 | switch (regno) | |
7389 | { | |
7390 | default: | |
7391 | break; | |
7392 | case CR_ITIR: | |
7393 | case CR_IFS: | |
7394 | case CR_IIM: | |
7395 | case CR_IIP: | |
7396 | case CR_IPSR: | |
7397 | case CR_ISR: | |
7398 | case CR_IFA: | |
7399 | case CR_IHA: | |
7400 | case CR_IIPA: | |
7401 | specs[count++] = tmpl; | |
7402 | break; | |
7403 | } | |
7404 | } | |
7405 | } | |
7406 | break; | |
7407 | case PSR_CPL: | |
7408 | if (rsrc_write) | |
7409 | { | |
7410 | specs[count++] = tmpl; | |
7411 | } | |
7412 | else | |
7413 | { | |
7414 | /* Only some AR accesses use cpl */ | |
7415 | if (idesc->operands[0] == IA64_OPND_AR3 | |
7416 | || idesc->operands[1] == IA64_OPND_AR3) | |
7417 | { | |
7418 | int index = | |
7419 | ((idesc->operands[0] == IA64_OPND_AR3) | |
7420 | ? 0 : 1); | |
7421 | int regno = | |
7422 | CURR_SLOT.opnd[index].X_add_number - REG_AR; | |
7423 | ||
7424 | if (regno == AR_ITC | |
7425 | || (index == 0 | |
7426 | && (regno == AR_ITC | |
7427 | || regno == AR_RSC | |
7428 | || (regno >= AR_K0 | |
7429 | && regno <= AR_K7)))) | |
7430 | { | |
7431 | specs[count++] = tmpl; | |
7432 | } | |
7433 | } | |
7434 | else | |
7435 | { | |
7436 | specs[count++] = tmpl; | |
7437 | } | |
7438 | break; | |
7439 | } | |
7440 | } | |
7441 | } | |
7442 | } | |
800eeca4 | 7443 | else if (note == 7) |
542d6675 KH |
7444 | { |
7445 | valueT mask = 0; | |
7446 | if (idesc->operands[0] == IA64_OPND_IMMU24) | |
7447 | { | |
7448 | mask = CURR_SLOT.opnd[0].X_add_number; | |
7449 | } | |
7450 | else | |
7451 | { | |
7452 | UNHANDLED; | |
7453 | } | |
7454 | if (mask & ((valueT) 1 << dep->regindex)) | |
7455 | { | |
7456 | specs[count++] = tmpl; | |
7457 | } | |
7458 | } | |
800eeca4 | 7459 | else if (note == 8) |
542d6675 KH |
7460 | { |
7461 | int min = dep->regindex == PSR_DFL ? 2 : 32; | |
7462 | int max = dep->regindex == PSR_DFL ? 31 : 127; | |
7463 | /* dfh is read on FR32-127; dfl is read on FR2-31 */ | |
7464 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7465 | { | |
7466 | if (idesc->operands[i] == IA64_OPND_F1 | |
7467 | || idesc->operands[i] == IA64_OPND_F2 | |
7468 | || idesc->operands[i] == IA64_OPND_F3 | |
7469 | || idesc->operands[i] == IA64_OPND_F4) | |
7470 | { | |
7471 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7472 | if (reg >= min && reg <= max) | |
7473 | { | |
7474 | specs[count++] = tmpl; | |
7475 | } | |
7476 | } | |
7477 | } | |
7478 | } | |
800eeca4 | 7479 | else if (note == 9) |
542d6675 KH |
7480 | { |
7481 | int min = dep->regindex == PSR_MFL ? 2 : 32; | |
7482 | int max = dep->regindex == PSR_MFL ? 31 : 127; | |
7483 | /* mfh is read on writes to FR32-127; mfl is read on writes to | |
7484 | FR2-31 */ | |
7485 | for (i = 0; i < idesc->num_outputs; i++) | |
7486 | { | |
7487 | if (idesc->operands[i] == IA64_OPND_F1) | |
7488 | { | |
7489 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7490 | if (reg >= min && reg <= max) | |
7491 | { | |
7492 | specs[count++] = tmpl; | |
7493 | } | |
7494 | } | |
7495 | } | |
7496 | } | |
800eeca4 | 7497 | else if (note == 10) |
542d6675 KH |
7498 | { |
7499 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7500 | { | |
7501 | if (idesc->operands[i] == IA64_OPND_R1 | |
7502 | || idesc->operands[i] == IA64_OPND_R2 | |
7503 | || idesc->operands[i] == IA64_OPND_R3) | |
7504 | { | |
7505 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7506 | if (regno >= 16 && regno <= 31) | |
7507 | { | |
7508 | specs[count++] = tmpl; | |
7509 | } | |
7510 | } | |
7511 | } | |
7512 | } | |
800eeca4 | 7513 | else |
542d6675 KH |
7514 | { |
7515 | UNHANDLED; | |
7516 | } | |
800eeca4 JW |
7517 | break; |
7518 | ||
7519 | case IA64_RS_AR_FPSR: | |
7520 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
542d6675 KH |
7521 | { |
7522 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7523 | if (regno == AR_FPSR) | |
7524 | { | |
7525 | specs[count++] = tmpl; | |
7526 | } | |
7527 | } | |
800eeca4 | 7528 | else |
542d6675 KH |
7529 | { |
7530 | specs[count++] = tmpl; | |
7531 | } | |
800eeca4 JW |
7532 | break; |
7533 | ||
197865e8 | 7534 | case IA64_RS_ARX: |
800eeca4 JW |
7535 | /* Handle all AR[REG] resources */ |
7536 | if (note == 0 || note == 1) | |
542d6675 KH |
7537 | { |
7538 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7539 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 | |
7540 | && regno == dep->regindex) | |
7541 | { | |
7542 | specs[count++] = tmpl; | |
7543 | } | |
7544 | /* other AR[REG] resources may be affected by AR accesses */ | |
7545 | else if (idesc->operands[0] == IA64_OPND_AR3) | |
7546 | { | |
7547 | /* AR[] writes */ | |
7548 | regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; | |
7549 | switch (dep->regindex) | |
7550 | { | |
7551 | default: | |
7552 | break; | |
7553 | case AR_BSP: | |
7554 | case AR_RNAT: | |
7555 | if (regno == AR_BSPSTORE) | |
7556 | { | |
7557 | specs[count++] = tmpl; | |
7558 | } | |
7559 | case AR_RSC: | |
7560 | if (!rsrc_write && | |
7561 | (regno == AR_BSPSTORE | |
7562 | || regno == AR_RNAT)) | |
7563 | { | |
7564 | specs[count++] = tmpl; | |
7565 | } | |
7566 | break; | |
7567 | } | |
7568 | } | |
7569 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
7570 | { | |
7571 | /* AR[] reads */ | |
7572 | regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; | |
7573 | switch (dep->regindex) | |
7574 | { | |
7575 | default: | |
7576 | break; | |
7577 | case AR_RSC: | |
7578 | if (regno == AR_BSPSTORE || regno == AR_RNAT) | |
7579 | { | |
7580 | specs[count++] = tmpl; | |
7581 | } | |
7582 | break; | |
7583 | } | |
7584 | } | |
7585 | else | |
7586 | { | |
7587 | specs[count++] = tmpl; | |
7588 | } | |
7589 | } | |
800eeca4 | 7590 | else |
542d6675 KH |
7591 | { |
7592 | UNHANDLED; | |
7593 | } | |
800eeca4 JW |
7594 | break; |
7595 | ||
7596 | case IA64_RS_CRX: | |
7597 | /* Handle all CR[REG] resources */ | |
7598 | if (note == 0 || note == 1) | |
542d6675 KH |
7599 | { |
7600 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
7601 | { | |
7602 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7603 | if (regno == dep->regindex) | |
7604 | { | |
7605 | specs[count++] = tmpl; | |
7606 | } | |
7607 | else if (!rsrc_write) | |
7608 | { | |
7609 | /* Reads from CR[IVR] affect other resources. */ | |
7610 | if (regno == CR_IVR) | |
7611 | { | |
7612 | if ((dep->regindex >= CR_IRR0 | |
7613 | && dep->regindex <= CR_IRR3) | |
7614 | || dep->regindex == CR_TPR) | |
7615 | { | |
7616 | specs[count++] = tmpl; | |
7617 | } | |
7618 | } | |
7619 | } | |
7620 | } | |
7621 | else | |
7622 | { | |
7623 | specs[count++] = tmpl; | |
7624 | } | |
7625 | } | |
800eeca4 | 7626 | else |
542d6675 KH |
7627 | { |
7628 | UNHANDLED; | |
7629 | } | |
800eeca4 JW |
7630 | break; |
7631 | ||
7632 | case IA64_RS_INSERVICE: | |
7633 | /* look for write of EOI (67) or read of IVR (65) */ | |
7634 | if ((idesc->operands[0] == IA64_OPND_CR3 | |
542d6675 KH |
7635 | && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) |
7636 | || (idesc->operands[1] == IA64_OPND_CR3 | |
7637 | && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) | |
7638 | { | |
7639 | specs[count++] = tmpl; | |
7640 | } | |
800eeca4 JW |
7641 | break; |
7642 | ||
7643 | case IA64_RS_GR0: | |
7644 | if (note == 1) | |
542d6675 KH |
7645 | { |
7646 | specs[count++] = tmpl; | |
7647 | } | |
800eeca4 | 7648 | else |
542d6675 KH |
7649 | { |
7650 | UNHANDLED; | |
7651 | } | |
800eeca4 JW |
7652 | break; |
7653 | ||
7654 | case IA64_RS_CFM: | |
7655 | if (note != 2) | |
542d6675 KH |
7656 | { |
7657 | specs[count++] = tmpl; | |
7658 | } | |
800eeca4 | 7659 | else |
542d6675 KH |
7660 | { |
7661 | /* Check if any of the registers accessed are in the rotating region. | |
7662 | mov to/from pr accesses CFM only when qp_regno is in the rotating | |
7663 | region */ | |
7664 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7665 | { | |
7666 | if (idesc->operands[i] == IA64_OPND_R1 | |
7667 | || idesc->operands[i] == IA64_OPND_R2 | |
7668 | || idesc->operands[i] == IA64_OPND_R3) | |
7669 | { | |
7670 | int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7671 | /* Assumes that md.rot.num_regs is always valid */ | |
7672 | if (md.rot.num_regs > 0 | |
7673 | && num > 31 | |
7674 | && num < 31 + md.rot.num_regs) | |
7675 | { | |
7676 | specs[count] = tmpl; | |
7677 | specs[count++].specific = 0; | |
7678 | } | |
7679 | } | |
7680 | else if (idesc->operands[i] == IA64_OPND_F1 | |
7681 | || idesc->operands[i] == IA64_OPND_F2 | |
7682 | || idesc->operands[i] == IA64_OPND_F3 | |
7683 | || idesc->operands[i] == IA64_OPND_F4) | |
7684 | { | |
7685 | int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7686 | if (num > 31) | |
7687 | { | |
7688 | specs[count] = tmpl; | |
7689 | specs[count++].specific = 0; | |
7690 | } | |
7691 | } | |
7692 | else if (idesc->operands[i] == IA64_OPND_P1 | |
7693 | || idesc->operands[i] == IA64_OPND_P2) | |
7694 | { | |
7695 | int num = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
7696 | if (num > 15) | |
7697 | { | |
7698 | specs[count] = tmpl; | |
7699 | specs[count++].specific = 0; | |
7700 | } | |
7701 | } | |
7702 | } | |
7703 | if (CURR_SLOT.qp_regno > 15) | |
7704 | { | |
7705 | specs[count] = tmpl; | |
7706 | specs[count++].specific = 0; | |
7707 | } | |
7708 | } | |
800eeca4 JW |
7709 | break; |
7710 | ||
139368c9 JW |
7711 | /* This is the same as IA64_RS_PRr, except simplified to account for |
7712 | the fact that there is only one register. */ | |
800eeca4 JW |
7713 | case IA64_RS_PR63: |
7714 | if (note == 0) | |
542d6675 KH |
7715 | { |
7716 | specs[count++] = tmpl; | |
7717 | } | |
139368c9 JW |
7718 | else if (note == 7) |
7719 | { | |
7720 | valueT mask = 0; | |
7721 | if (idesc->operands[2] == IA64_OPND_IMM17) | |
7722 | mask = CURR_SLOT.opnd[2].X_add_number; | |
7723 | if (mask & ((valueT) 1 << 63)) | |
7724 | specs[count++] = tmpl; | |
7725 | } | |
800eeca4 | 7726 | else if (note == 11) |
542d6675 KH |
7727 | { |
7728 | if ((idesc->operands[0] == IA64_OPND_P1 | |
7729 | && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) | |
7730 | || (idesc->operands[1] == IA64_OPND_P2 | |
7731 | && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) | |
7732 | { | |
7733 | specs[count++] = tmpl; | |
7734 | } | |
7735 | } | |
800eeca4 | 7736 | else if (note == 12) |
542d6675 KH |
7737 | { |
7738 | if (CURR_SLOT.qp_regno == 63) | |
7739 | { | |
7740 | specs[count++] = tmpl; | |
7741 | } | |
7742 | } | |
800eeca4 | 7743 | else if (note == 1) |
542d6675 KH |
7744 | { |
7745 | if (rsrc_write) | |
7746 | { | |
7484b8e6 TW |
7747 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
7748 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
7749 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; | |
7750 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; | |
7751 | ||
4a4f25cf | 7752 | if (p1 == 63 |
7484b8e6 TW |
7753 | && (idesc->operands[0] == IA64_OPND_P1 |
7754 | || idesc->operands[0] == IA64_OPND_P2)) | |
7755 | { | |
7756 | specs[count] = tmpl; | |
4a4f25cf | 7757 | specs[count++].cmp_type = |
7484b8e6 TW |
7758 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
7759 | } | |
7760 | if (p2 == 63 | |
7761 | && (idesc->operands[1] == IA64_OPND_P1 | |
7762 | || idesc->operands[1] == IA64_OPND_P2)) | |
7763 | { | |
7764 | specs[count] = tmpl; | |
4a4f25cf | 7765 | specs[count++].cmp_type = |
7484b8e6 TW |
7766 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
7767 | } | |
542d6675 KH |
7768 | } |
7769 | else | |
7770 | { | |
7771 | if (CURR_SLOT.qp_regno == 63) | |
7772 | { | |
7773 | specs[count++] = tmpl; | |
7774 | } | |
7775 | } | |
7776 | } | |
800eeca4 | 7777 | else |
542d6675 KH |
7778 | { |
7779 | UNHANDLED; | |
7780 | } | |
800eeca4 JW |
7781 | break; |
7782 | ||
7783 | case IA64_RS_RSE: | |
7784 | /* FIXME we can identify some individual RSE written resources, but RSE | |
542d6675 KH |
7785 | read resources have not yet been completely identified, so for now |
7786 | treat RSE as a single resource */ | |
800eeca4 | 7787 | if (strncmp (idesc->name, "mov", 3) == 0) |
542d6675 KH |
7788 | { |
7789 | if (rsrc_write) | |
7790 | { | |
7791 | if (idesc->operands[0] == IA64_OPND_AR3 | |
7792 | && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) | |
7793 | { | |
7794 | specs[count] = tmpl; | |
7795 | specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ | |
7796 | } | |
7797 | } | |
7798 | else | |
7799 | { | |
7800 | if (idesc->operands[0] == IA64_OPND_AR3) | |
7801 | { | |
7802 | if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE | |
7803 | || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) | |
7804 | { | |
7805 | specs[count++] = tmpl; | |
7806 | } | |
7807 | } | |
7808 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
7809 | { | |
7810 | if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP | |
7811 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE | |
7812 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) | |
7813 | { | |
7814 | specs[count++] = tmpl; | |
7815 | } | |
7816 | } | |
7817 | } | |
7818 | } | |
197865e8 | 7819 | else |
542d6675 KH |
7820 | { |
7821 | specs[count++] = tmpl; | |
7822 | } | |
800eeca4 JW |
7823 | break; |
7824 | ||
7825 | case IA64_RS_ANY: | |
7826 | /* FIXME -- do any of these need to be non-specific? */ | |
7827 | specs[count++] = tmpl; | |
7828 | break; | |
7829 | ||
7830 | default: | |
7831 | as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); | |
7832 | break; | |
7833 | } | |
7834 | ||
7835 | return count; | |
7836 | } | |
7837 | ||
7838 | /* Clear branch flags on marked resources. This breaks the link between the | |
542d6675 KH |
7839 | QP of the marking instruction and a subsequent branch on the same QP. */ |
7840 | ||
800eeca4 JW |
7841 | static void |
7842 | clear_qp_branch_flag (mask) | |
542d6675 | 7843 | valueT mask; |
800eeca4 JW |
7844 | { |
7845 | int i; | |
542d6675 | 7846 | for (i = 0; i < regdepslen; i++) |
800eeca4 | 7847 | { |
197865e8 | 7848 | valueT bit = ((valueT) 1 << regdeps[i].qp_regno); |
800eeca4 | 7849 | if ((bit & mask) != 0) |
542d6675 KH |
7850 | { |
7851 | regdeps[i].link_to_qp_branch = 0; | |
7852 | } | |
800eeca4 JW |
7853 | } |
7854 | } | |
7855 | ||
197865e8 | 7856 | /* Remove any mutexes which contain any of the PRs indicated in the mask. |
800eeca4 | 7857 | |
542d6675 KH |
7858 | Any changes to a PR clears the mutex relations which include that PR. */ |
7859 | ||
800eeca4 JW |
7860 | static void |
7861 | clear_qp_mutex (mask) | |
542d6675 | 7862 | valueT mask; |
800eeca4 JW |
7863 | { |
7864 | int i; | |
7865 | ||
7866 | i = 0; | |
7867 | while (i < qp_mutexeslen) | |
7868 | { | |
7869 | if ((qp_mutexes[i].prmask & mask) != 0) | |
542d6675 KH |
7870 | { |
7871 | if (md.debug_dv) | |
7872 | { | |
7873 | fprintf (stderr, " Clearing mutex relation"); | |
7874 | print_prmask (qp_mutexes[i].prmask); | |
7875 | fprintf (stderr, "\n"); | |
7876 | } | |
7877 | qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; | |
7878 | } | |
800eeca4 | 7879 | else |
542d6675 | 7880 | ++i; |
800eeca4 JW |
7881 | } |
7882 | } | |
7883 | ||
7884 | /* Clear implies relations which contain PRs in the given masks. | |
7885 | P1_MASK indicates the source of the implies relation, while P2_MASK | |
542d6675 KH |
7886 | indicates the implied PR. */ |
7887 | ||
800eeca4 JW |
7888 | static void |
7889 | clear_qp_implies (p1_mask, p2_mask) | |
542d6675 KH |
7890 | valueT p1_mask; |
7891 | valueT p2_mask; | |
800eeca4 JW |
7892 | { |
7893 | int i; | |
7894 | ||
7895 | i = 0; | |
7896 | while (i < qp_implieslen) | |
7897 | { | |
197865e8 | 7898 | if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 |
542d6675 KH |
7899 | || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) |
7900 | { | |
7901 | if (md.debug_dv) | |
7902 | fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", | |
7903 | qp_implies[i].p1, qp_implies[i].p2); | |
7904 | qp_implies[i] = qp_implies[--qp_implieslen]; | |
7905 | } | |
197865e8 | 7906 | else |
542d6675 | 7907 | ++i; |
800eeca4 JW |
7908 | } |
7909 | } | |
7910 | ||
542d6675 KH |
7911 | /* Add the PRs specified to the list of implied relations. */ |
7912 | ||
800eeca4 JW |
7913 | static void |
7914 | add_qp_imply (p1, p2) | |
542d6675 | 7915 | int p1, p2; |
800eeca4 JW |
7916 | { |
7917 | valueT mask; | |
7918 | valueT bit; | |
7919 | int i; | |
7920 | ||
542d6675 | 7921 | /* p0 is not meaningful here. */ |
800eeca4 JW |
7922 | if (p1 == 0 || p2 == 0) |
7923 | abort (); | |
7924 | ||
7925 | if (p1 == p2) | |
7926 | return; | |
7927 | ||
542d6675 KH |
7928 | /* If it exists already, ignore it. */ |
7929 | for (i = 0; i < qp_implieslen; i++) | |
800eeca4 | 7930 | { |
197865e8 | 7931 | if (qp_implies[i].p1 == p1 |
542d6675 KH |
7932 | && qp_implies[i].p2 == p2 |
7933 | && qp_implies[i].path == md.path | |
7934 | && !qp_implies[i].p2_branched) | |
7935 | return; | |
800eeca4 JW |
7936 | } |
7937 | ||
7938 | if (qp_implieslen == qp_impliestotlen) | |
7939 | { | |
7940 | qp_impliestotlen += 20; | |
7941 | qp_implies = (struct qp_imply *) | |
542d6675 KH |
7942 | xrealloc ((void *) qp_implies, |
7943 | qp_impliestotlen * sizeof (struct qp_imply)); | |
800eeca4 JW |
7944 | } |
7945 | if (md.debug_dv) | |
7946 | fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); | |
7947 | qp_implies[qp_implieslen].p1 = p1; | |
7948 | qp_implies[qp_implieslen].p2 = p2; | |
7949 | qp_implies[qp_implieslen].path = md.path; | |
7950 | qp_implies[qp_implieslen++].p2_branched = 0; | |
7951 | ||
7952 | /* Add in the implied transitive relations; for everything that p2 implies, | |
7953 | make p1 imply that, too; for everything that implies p1, make it imply p2 | |
197865e8 | 7954 | as well. */ |
542d6675 | 7955 | for (i = 0; i < qp_implieslen; i++) |
800eeca4 JW |
7956 | { |
7957 | if (qp_implies[i].p1 == p2) | |
542d6675 | 7958 | add_qp_imply (p1, qp_implies[i].p2); |
800eeca4 | 7959 | if (qp_implies[i].p2 == p1) |
542d6675 | 7960 | add_qp_imply (qp_implies[i].p1, p2); |
800eeca4 JW |
7961 | } |
7962 | /* Add in mutex relations implied by this implies relation; for each mutex | |
197865e8 KH |
7963 | relation containing p2, duplicate it and replace p2 with p1. */ |
7964 | bit = (valueT) 1 << p1; | |
7965 | mask = (valueT) 1 << p2; | |
542d6675 | 7966 | for (i = 0; i < qp_mutexeslen; i++) |
800eeca4 JW |
7967 | { |
7968 | if (qp_mutexes[i].prmask & mask) | |
542d6675 | 7969 | add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); |
800eeca4 JW |
7970 | } |
7971 | } | |
7972 | ||
800eeca4 JW |
7973 | /* Add the PRs specified in the mask to the mutex list; this means that only |
7974 | one of the PRs can be true at any time. PR0 should never be included in | |
7975 | the mask. */ | |
542d6675 | 7976 | |
800eeca4 JW |
7977 | static void |
7978 | add_qp_mutex (mask) | |
542d6675 | 7979 | valueT mask; |
800eeca4 JW |
7980 | { |
7981 | if (mask & 0x1) | |
7982 | abort (); | |
7983 | ||
7984 | if (qp_mutexeslen == qp_mutexestotlen) | |
7985 | { | |
7986 | qp_mutexestotlen += 20; | |
7987 | qp_mutexes = (struct qpmutex *) | |
542d6675 KH |
7988 | xrealloc ((void *) qp_mutexes, |
7989 | qp_mutexestotlen * sizeof (struct qpmutex)); | |
800eeca4 JW |
7990 | } |
7991 | if (md.debug_dv) | |
7992 | { | |
7993 | fprintf (stderr, " Registering mutex on"); | |
7994 | print_prmask (mask); | |
7995 | fprintf (stderr, "\n"); | |
7996 | } | |
7997 | qp_mutexes[qp_mutexeslen].path = md.path; | |
7998 | qp_mutexes[qp_mutexeslen++].prmask = mask; | |
7999 | } | |
8000 | ||
8001 | static void | |
8002 | clear_register_values () | |
8003 | { | |
8004 | int i; | |
8005 | if (md.debug_dv) | |
8006 | fprintf (stderr, " Clearing register values\n"); | |
542d6675 | 8007 | for (i = 1; i < NELEMS (gr_values); i++) |
800eeca4 JW |
8008 | gr_values[i].known = 0; |
8009 | } | |
8010 | ||
8011 | /* Keep track of register values/changes which affect DV tracking. | |
8012 | ||
8013 | optimization note: should add a flag to classes of insns where otherwise we | |
542d6675 | 8014 | have to examine a group of strings to identify them. */ |
800eeca4 | 8015 | |
800eeca4 JW |
8016 | static void |
8017 | note_register_values (idesc) | |
542d6675 | 8018 | struct ia64_opcode *idesc; |
800eeca4 JW |
8019 | { |
8020 | valueT qp_changemask = 0; | |
8021 | int i; | |
8022 | ||
542d6675 KH |
8023 | /* Invalidate values for registers being written to. */ |
8024 | for (i = 0; i < idesc->num_outputs; i++) | |
800eeca4 | 8025 | { |
197865e8 | 8026 | if (idesc->operands[i] == IA64_OPND_R1 |
542d6675 KH |
8027 | || idesc->operands[i] == IA64_OPND_R2 |
8028 | || idesc->operands[i] == IA64_OPND_R3) | |
8029 | { | |
8030 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8031 | if (regno > 0 && regno < NELEMS (gr_values)) | |
8032 | gr_values[regno].known = 0; | |
8033 | } | |
50b81f19 JW |
8034 | else if (idesc->operands[i] == IA64_OPND_R3_2) |
8035 | { | |
8036 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8037 | if (regno > 0 && regno < 4) | |
8038 | gr_values[regno].known = 0; | |
8039 | } | |
197865e8 | 8040 | else if (idesc->operands[i] == IA64_OPND_P1 |
542d6675 KH |
8041 | || idesc->operands[i] == IA64_OPND_P2) |
8042 | { | |
8043 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8044 | qp_changemask |= (valueT) 1 << regno; | |
8045 | } | |
800eeca4 | 8046 | else if (idesc->operands[i] == IA64_OPND_PR) |
542d6675 KH |
8047 | { |
8048 | if (idesc->operands[2] & (valueT) 0x10000) | |
8049 | qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; | |
8050 | else | |
8051 | qp_changemask = idesc->operands[2]; | |
8052 | break; | |
8053 | } | |
800eeca4 | 8054 | else if (idesc->operands[i] == IA64_OPND_PR_ROT) |
542d6675 KH |
8055 | { |
8056 | if (idesc->operands[1] & ((valueT) 1 << 43)) | |
8057 | qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; | |
8058 | else | |
8059 | qp_changemask = idesc->operands[1]; | |
8060 | qp_changemask &= ~(valueT) 0xFFFF; | |
8061 | break; | |
8062 | } | |
8063 | } | |
8064 | ||
8065 | /* Always clear qp branch flags on any PR change. */ | |
8066 | /* FIXME there may be exceptions for certain compares. */ | |
800eeca4 JW |
8067 | clear_qp_branch_flag (qp_changemask); |
8068 | ||
542d6675 | 8069 | /* Invalidate rotating registers on insns which affect RRBs in CFM. */ |
800eeca4 JW |
8070 | if (idesc->flags & IA64_OPCODE_MOD_RRBS) |
8071 | { | |
197865e8 | 8072 | qp_changemask |= ~(valueT) 0xFFFF; |
800eeca4 | 8073 | if (strcmp (idesc->name, "clrrrb.pr") != 0) |
542d6675 KH |
8074 | { |
8075 | for (i = 32; i < 32 + md.rot.num_regs; i++) | |
8076 | gr_values[i].known = 0; | |
8077 | } | |
800eeca4 JW |
8078 | clear_qp_mutex (qp_changemask); |
8079 | clear_qp_implies (qp_changemask, qp_changemask); | |
8080 | } | |
542d6675 KH |
8081 | /* After a call, all register values are undefined, except those marked |
8082 | as "safe". */ | |
800eeca4 | 8083 | else if (strncmp (idesc->name, "br.call", 6) == 0 |
542d6675 | 8084 | || strncmp (idesc->name, "brl.call", 7) == 0) |
800eeca4 | 8085 | { |
56d27c17 | 8086 | /* FIXME keep GR values which are marked as "safe_across_calls" */ |
800eeca4 JW |
8087 | clear_register_values (); |
8088 | clear_qp_mutex (~qp_safe_across_calls); | |
8089 | clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); | |
8090 | clear_qp_branch_flag (~qp_safe_across_calls); | |
8091 | } | |
e9718fe1 | 8092 | else if (is_interruption_or_rfi (idesc) |
542d6675 | 8093 | || is_taken_branch (idesc)) |
e9718fe1 TW |
8094 | { |
8095 | clear_register_values (); | |
197865e8 KH |
8096 | clear_qp_mutex (~(valueT) 0); |
8097 | clear_qp_implies (~(valueT) 0, ~(valueT) 0); | |
e9718fe1 | 8098 | } |
542d6675 | 8099 | /* Look for mutex and implies relations. */ |
197865e8 | 8100 | else if ((idesc->operands[0] == IA64_OPND_P1 |
542d6675 KH |
8101 | || idesc->operands[0] == IA64_OPND_P2) |
8102 | && (idesc->operands[1] == IA64_OPND_P1 | |
8103 | || idesc->operands[1] == IA64_OPND_P2)) | |
800eeca4 JW |
8104 | { |
8105 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
197865e8 KH |
8106 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
8107 | valueT p1mask = (valueT) 1 << p1; | |
8108 | valueT p2mask = (valueT) 1 << p2; | |
800eeca4 | 8109 | |
542d6675 | 8110 | /* If one of the PRs is PR0, we can't really do anything. */ |
800eeca4 | 8111 | if (p1 == 0 || p2 == 0) |
542d6675 KH |
8112 | { |
8113 | if (md.debug_dv) | |
8114 | fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); | |
8115 | } | |
800eeca4 | 8116 | /* In general, clear mutexes and implies which include P1 or P2, |
542d6675 | 8117 | with the following exceptions. */ |
800eeca4 | 8118 | else if (strstr (idesc->name, ".or.andcm") != NULL) |
542d6675 KH |
8119 | { |
8120 | add_qp_mutex (p1mask | p2mask); | |
8121 | clear_qp_implies (p2mask, p1mask); | |
8122 | } | |
800eeca4 | 8123 | else if (strstr (idesc->name, ".and.orcm") != NULL) |
542d6675 KH |
8124 | { |
8125 | add_qp_mutex (p1mask | p2mask); | |
8126 | clear_qp_implies (p1mask, p2mask); | |
8127 | } | |
800eeca4 | 8128 | else if (strstr (idesc->name, ".and") != NULL) |
542d6675 KH |
8129 | { |
8130 | clear_qp_implies (0, p1mask | p2mask); | |
8131 | } | |
800eeca4 | 8132 | else if (strstr (idesc->name, ".or") != NULL) |
542d6675 KH |
8133 | { |
8134 | clear_qp_mutex (p1mask | p2mask); | |
8135 | clear_qp_implies (p1mask | p2mask, 0); | |
8136 | } | |
800eeca4 | 8137 | else |
542d6675 KH |
8138 | { |
8139 | clear_qp_implies (p1mask | p2mask, p1mask | p2mask); | |
8140 | if (strstr (idesc->name, ".unc") != NULL) | |
8141 | { | |
8142 | add_qp_mutex (p1mask | p2mask); | |
8143 | if (CURR_SLOT.qp_regno != 0) | |
8144 | { | |
8145 | add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, | |
8146 | CURR_SLOT.qp_regno); | |
8147 | add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, | |
8148 | CURR_SLOT.qp_regno); | |
8149 | } | |
8150 | } | |
8151 | else if (CURR_SLOT.qp_regno == 0) | |
8152 | { | |
8153 | add_qp_mutex (p1mask | p2mask); | |
8154 | } | |
8155 | else | |
8156 | { | |
8157 | clear_qp_mutex (p1mask | p2mask); | |
8158 | } | |
8159 | } | |
8160 | } | |
8161 | /* Look for mov imm insns into GRs. */ | |
800eeca4 | 8162 | else if (idesc->operands[0] == IA64_OPND_R1 |
542d6675 KH |
8163 | && (idesc->operands[1] == IA64_OPND_IMM22 |
8164 | || idesc->operands[1] == IA64_OPND_IMMU64) | |
8165 | && (strcmp (idesc->name, "mov") == 0 | |
8166 | || strcmp (idesc->name, "movl") == 0)) | |
800eeca4 JW |
8167 | { |
8168 | int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
542d6675 KH |
8169 | if (regno > 0 && regno < NELEMS (gr_values)) |
8170 | { | |
8171 | gr_values[regno].known = 1; | |
8172 | gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; | |
8173 | gr_values[regno].path = md.path; | |
8174 | if (md.debug_dv) | |
8175 | fprintf (stderr, " Know gr%d = 0x%llx\n", | |
8176 | regno, gr_values[regno].value); | |
8177 | } | |
800eeca4 | 8178 | } |
197865e8 | 8179 | else |
800eeca4 JW |
8180 | { |
8181 | clear_qp_mutex (qp_changemask); | |
8182 | clear_qp_implies (qp_changemask, qp_changemask); | |
8183 | } | |
8184 | } | |
8185 | ||
542d6675 KH |
8186 | /* Return whether the given predicate registers are currently mutex. */ |
8187 | ||
800eeca4 JW |
8188 | static int |
8189 | qp_mutex (p1, p2, path) | |
542d6675 KH |
8190 | int p1; |
8191 | int p2; | |
8192 | int path; | |
800eeca4 JW |
8193 | { |
8194 | int i; | |
8195 | valueT mask; | |
8196 | ||
8197 | if (p1 != p2) | |
8198 | { | |
542d6675 KH |
8199 | mask = ((valueT) 1 << p1) | (valueT) 1 << p2; |
8200 | for (i = 0; i < qp_mutexeslen; i++) | |
8201 | { | |
8202 | if (qp_mutexes[i].path >= path | |
8203 | && (qp_mutexes[i].prmask & mask) == mask) | |
8204 | return 1; | |
8205 | } | |
800eeca4 JW |
8206 | } |
8207 | return 0; | |
8208 | } | |
8209 | ||
8210 | /* Return whether the given resource is in the given insn's list of chks | |
8211 | Return 1 if the conflict is absolutely determined, 2 if it's a potential | |
542d6675 KH |
8212 | conflict. */ |
8213 | ||
800eeca4 JW |
8214 | static int |
8215 | resources_match (rs, idesc, note, qp_regno, path) | |
542d6675 KH |
8216 | struct rsrc *rs; |
8217 | struct ia64_opcode *idesc; | |
8218 | int note; | |
8219 | int qp_regno; | |
8220 | int path; | |
800eeca4 JW |
8221 | { |
8222 | struct rsrc specs[MAX_SPECS]; | |
8223 | int count; | |
8224 | ||
8225 | /* If the marked resource's qp_regno and the given qp_regno are mutex, | |
8226 | we don't need to check. One exception is note 11, which indicates that | |
8227 | target predicates are written regardless of PR[qp]. */ | |
197865e8 | 8228 | if (qp_mutex (rs->qp_regno, qp_regno, path) |
800eeca4 JW |
8229 | && note != 11) |
8230 | return 0; | |
8231 | ||
8232 | count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); | |
8233 | while (count-- > 0) | |
8234 | { | |
8235 | /* UNAT checking is a bit more specific than other resources */ | |
8236 | if (rs->dependency->specifier == IA64_RS_AR_UNAT | |
542d6675 KH |
8237 | && specs[count].mem_offset.hint |
8238 | && rs->mem_offset.hint) | |
8239 | { | |
8240 | if (rs->mem_offset.base == specs[count].mem_offset.base) | |
8241 | { | |
8242 | if (((rs->mem_offset.offset >> 3) & 0x3F) == | |
8243 | ((specs[count].mem_offset.offset >> 3) & 0x3F)) | |
8244 | return 1; | |
8245 | else | |
8246 | continue; | |
8247 | } | |
8248 | } | |
800eeca4 | 8249 | |
7484b8e6 | 8250 | /* Skip apparent PR write conflicts where both writes are an AND or both |
4a4f25cf | 8251 | writes are an OR. */ |
7484b8e6 | 8252 | if (rs->dependency->specifier == IA64_RS_PR |
afa680f8 | 8253 | || rs->dependency->specifier == IA64_RS_PRr |
7484b8e6 TW |
8254 | || rs->dependency->specifier == IA64_RS_PR63) |
8255 | { | |
8256 | if (specs[count].cmp_type != CMP_NONE | |
8257 | && specs[count].cmp_type == rs->cmp_type) | |
8258 | { | |
8259 | if (md.debug_dv) | |
8260 | fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", | |
8261 | dv_mode[rs->dependency->mode], | |
afa680f8 | 8262 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 TW |
8263 | specs[count].index : 63); |
8264 | continue; | |
8265 | } | |
8266 | if (md.debug_dv) | |
4a4f25cf | 8267 | fprintf (stderr, |
7484b8e6 TW |
8268 | " %s on parallel compare conflict %s vs %s on PR%d\n", |
8269 | dv_mode[rs->dependency->mode], | |
4a4f25cf | 8270 | dv_cmp_type[rs->cmp_type], |
7484b8e6 | 8271 | dv_cmp_type[specs[count].cmp_type], |
afa680f8 | 8272 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 | 8273 | specs[count].index : 63); |
4a4f25cf | 8274 | |
7484b8e6 TW |
8275 | } |
8276 | ||
800eeca4 | 8277 | /* If either resource is not specific, conservatively assume a conflict |
197865e8 | 8278 | */ |
800eeca4 | 8279 | if (!specs[count].specific || !rs->specific) |
542d6675 | 8280 | return 2; |
800eeca4 | 8281 | else if (specs[count].index == rs->index) |
542d6675 | 8282 | return 1; |
800eeca4 JW |
8283 | } |
8284 | #if 0 | |
8285 | if (md.debug_dv) | |
8286 | fprintf (stderr, " No %s conflicts\n", rs->dependency->name); | |
8287 | #endif | |
8288 | ||
8289 | return 0; | |
8290 | } | |
8291 | ||
8292 | /* Indicate an instruction group break; if INSERT_STOP is non-zero, then | |
8293 | insert a stop to create the break. Update all resource dependencies | |
8294 | appropriately. If QP_REGNO is non-zero, only apply the break to resources | |
8295 | which use the same QP_REGNO and have the link_to_qp_branch flag set. | |
8296 | If SAVE_CURRENT is non-zero, don't affect resources marked by the current | |
542d6675 | 8297 | instruction. */ |
800eeca4 JW |
8298 | |
8299 | static void | |
8300 | insn_group_break (insert_stop, qp_regno, save_current) | |
542d6675 KH |
8301 | int insert_stop; |
8302 | int qp_regno; | |
8303 | int save_current; | |
800eeca4 JW |
8304 | { |
8305 | int i; | |
8306 | ||
8307 | if (insert_stop && md.num_slots_in_use > 0) | |
8308 | PREV_SLOT.end_of_insn_group = 1; | |
8309 | ||
8310 | if (md.debug_dv) | |
8311 | { | |
197865e8 | 8312 | fprintf (stderr, " Insn group break%s", |
542d6675 | 8313 | (insert_stop ? " (w/stop)" : "")); |
800eeca4 | 8314 | if (qp_regno != 0) |
542d6675 | 8315 | fprintf (stderr, " effective for QP=%d", qp_regno); |
800eeca4 JW |
8316 | fprintf (stderr, "\n"); |
8317 | } | |
8318 | ||
8319 | i = 0; | |
8320 | while (i < regdepslen) | |
8321 | { | |
8322 | const struct ia64_dependency *dep = regdeps[i].dependency; | |
8323 | ||
8324 | if (qp_regno != 0 | |
542d6675 KH |
8325 | && regdeps[i].qp_regno != qp_regno) |
8326 | { | |
8327 | ++i; | |
8328 | continue; | |
8329 | } | |
800eeca4 JW |
8330 | |
8331 | if (save_current | |
542d6675 KH |
8332 | && CURR_SLOT.src_file == regdeps[i].file |
8333 | && CURR_SLOT.src_line == regdeps[i].line) | |
8334 | { | |
8335 | ++i; | |
8336 | continue; | |
8337 | } | |
800eeca4 JW |
8338 | |
8339 | /* clear dependencies which are automatically cleared by a stop, or | |
542d6675 | 8340 | those that have reached the appropriate state of insn serialization */ |
800eeca4 | 8341 | if (dep->semantics == IA64_DVS_IMPLIED |
542d6675 KH |
8342 | || dep->semantics == IA64_DVS_IMPLIEDF |
8343 | || regdeps[i].insn_srlz == STATE_SRLZ) | |
8344 | { | |
8345 | print_dependency ("Removing", i); | |
8346 | regdeps[i] = regdeps[--regdepslen]; | |
8347 | } | |
800eeca4 | 8348 | else |
542d6675 KH |
8349 | { |
8350 | if (dep->semantics == IA64_DVS_DATA | |
8351 | || dep->semantics == IA64_DVS_INSTR | |
800eeca4 | 8352 | || dep->semantics == IA64_DVS_SPECIFIC) |
542d6675 KH |
8353 | { |
8354 | if (regdeps[i].insn_srlz == STATE_NONE) | |
8355 | regdeps[i].insn_srlz = STATE_STOP; | |
8356 | if (regdeps[i].data_srlz == STATE_NONE) | |
8357 | regdeps[i].data_srlz = STATE_STOP; | |
8358 | } | |
8359 | ++i; | |
8360 | } | |
800eeca4 JW |
8361 | } |
8362 | } | |
8363 | ||
542d6675 KH |
8364 | /* Add the given resource usage spec to the list of active dependencies. */ |
8365 | ||
197865e8 | 8366 | static void |
800eeca4 | 8367 | mark_resource (idesc, dep, spec, depind, path) |
542d6675 KH |
8368 | struct ia64_opcode *idesc; |
8369 | const struct ia64_dependency *dep; | |
8370 | struct rsrc *spec; | |
8371 | int depind; | |
8372 | int path; | |
800eeca4 JW |
8373 | { |
8374 | if (regdepslen == regdepstotlen) | |
8375 | { | |
8376 | regdepstotlen += 20; | |
8377 | regdeps = (struct rsrc *) | |
542d6675 KH |
8378 | xrealloc ((void *) regdeps, |
8379 | regdepstotlen * sizeof(struct rsrc)); | |
800eeca4 JW |
8380 | } |
8381 | ||
8382 | regdeps[regdepslen] = *spec; | |
8383 | regdeps[regdepslen].depind = depind; | |
8384 | regdeps[regdepslen].path = path; | |
8385 | regdeps[regdepslen].file = CURR_SLOT.src_file; | |
8386 | regdeps[regdepslen].line = CURR_SLOT.src_line; | |
8387 | ||
8388 | print_dependency ("Adding", regdepslen); | |
8389 | ||
8390 | ++regdepslen; | |
8391 | } | |
8392 | ||
8393 | static void | |
8394 | print_dependency (action, depind) | |
542d6675 KH |
8395 | const char *action; |
8396 | int depind; | |
800eeca4 JW |
8397 | { |
8398 | if (md.debug_dv) | |
8399 | { | |
197865e8 | 8400 | fprintf (stderr, " %s %s '%s'", |
542d6675 KH |
8401 | action, dv_mode[(regdeps[depind].dependency)->mode], |
8402 | (regdeps[depind].dependency)->name); | |
800eeca4 | 8403 | if (regdeps[depind].specific && regdeps[depind].index != 0) |
542d6675 | 8404 | fprintf (stderr, " (%d)", regdeps[depind].index); |
800eeca4 | 8405 | if (regdeps[depind].mem_offset.hint) |
542d6675 KH |
8406 | fprintf (stderr, " 0x%llx+0x%llx", |
8407 | regdeps[depind].mem_offset.base, | |
8408 | regdeps[depind].mem_offset.offset); | |
800eeca4 JW |
8409 | fprintf (stderr, "\n"); |
8410 | } | |
8411 | } | |
8412 | ||
8413 | static void | |
8414 | instruction_serialization () | |
8415 | { | |
8416 | int i; | |
8417 | if (md.debug_dv) | |
8418 | fprintf (stderr, " Instruction serialization\n"); | |
542d6675 | 8419 | for (i = 0; i < regdepslen; i++) |
800eeca4 JW |
8420 | if (regdeps[i].insn_srlz == STATE_STOP) |
8421 | regdeps[i].insn_srlz = STATE_SRLZ; | |
8422 | } | |
8423 | ||
8424 | static void | |
8425 | data_serialization () | |
8426 | { | |
8427 | int i = 0; | |
8428 | if (md.debug_dv) | |
8429 | fprintf (stderr, " Data serialization\n"); | |
8430 | while (i < regdepslen) | |
8431 | { | |
8432 | if (regdeps[i].data_srlz == STATE_STOP | |
542d6675 KH |
8433 | /* Note: as of 991210, all "other" dependencies are cleared by a |
8434 | data serialization. This might change with new tables */ | |
8435 | || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) | |
8436 | { | |
8437 | print_dependency ("Removing", i); | |
8438 | regdeps[i] = regdeps[--regdepslen]; | |
8439 | } | |
800eeca4 | 8440 | else |
542d6675 | 8441 | ++i; |
800eeca4 JW |
8442 | } |
8443 | } | |
8444 | ||
542d6675 KH |
8445 | /* Insert stops and serializations as needed to avoid DVs. */ |
8446 | ||
800eeca4 JW |
8447 | static void |
8448 | remove_marked_resource (rs) | |
542d6675 | 8449 | struct rsrc *rs; |
800eeca4 JW |
8450 | { |
8451 | switch (rs->dependency->semantics) | |
8452 | { | |
8453 | case IA64_DVS_SPECIFIC: | |
8454 | if (md.debug_dv) | |
8455 | fprintf (stderr, "Implementation-specific, assume worst case...\n"); | |
197865e8 | 8456 | /* ...fall through... */ |
800eeca4 JW |
8457 | case IA64_DVS_INSTR: |
8458 | if (md.debug_dv) | |
542d6675 | 8459 | fprintf (stderr, "Inserting instr serialization\n"); |
800eeca4 | 8460 | if (rs->insn_srlz < STATE_STOP) |
542d6675 | 8461 | insn_group_break (1, 0, 0); |
800eeca4 | 8462 | if (rs->insn_srlz < STATE_SRLZ) |
542d6675 KH |
8463 | { |
8464 | int oldqp = CURR_SLOT.qp_regno; | |
8465 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
8466 | /* Manually jam a srlz.i insn into the stream */ | |
8467 | CURR_SLOT.qp_regno = 0; | |
8468 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); | |
8469 | instruction_serialization (); | |
8470 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
8471 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
8472 | emit_one_bundle (); | |
8473 | CURR_SLOT.qp_regno = oldqp; | |
8474 | CURR_SLOT.idesc = oldidesc; | |
8475 | } | |
800eeca4 JW |
8476 | insn_group_break (1, 0, 0); |
8477 | break; | |
8478 | case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all | |
542d6675 KH |
8479 | "other" types of DV are eliminated |
8480 | by a data serialization */ | |
800eeca4 JW |
8481 | case IA64_DVS_DATA: |
8482 | if (md.debug_dv) | |
542d6675 | 8483 | fprintf (stderr, "Inserting data serialization\n"); |
800eeca4 | 8484 | if (rs->data_srlz < STATE_STOP) |
542d6675 | 8485 | insn_group_break (1, 0, 0); |
800eeca4 | 8486 | { |
542d6675 KH |
8487 | int oldqp = CURR_SLOT.qp_regno; |
8488 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
8489 | /* Manually jam a srlz.d insn into the stream */ | |
8490 | CURR_SLOT.qp_regno = 0; | |
8491 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); | |
8492 | data_serialization (); | |
8493 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
8494 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
8495 | emit_one_bundle (); | |
8496 | CURR_SLOT.qp_regno = oldqp; | |
8497 | CURR_SLOT.idesc = oldidesc; | |
800eeca4 JW |
8498 | } |
8499 | break; | |
8500 | case IA64_DVS_IMPLIED: | |
8501 | case IA64_DVS_IMPLIEDF: | |
8502 | if (md.debug_dv) | |
542d6675 | 8503 | fprintf (stderr, "Inserting stop\n"); |
800eeca4 JW |
8504 | insn_group_break (1, 0, 0); |
8505 | break; | |
8506 | default: | |
8507 | break; | |
8508 | } | |
8509 | } | |
8510 | ||
8511 | /* Check the resources used by the given opcode against the current dependency | |
197865e8 | 8512 | list. |
800eeca4 JW |
8513 | |
8514 | The check is run once for each execution path encountered. In this case, | |
8515 | a unique execution path is the sequence of instructions following a code | |
8516 | entry point, e.g. the following has three execution paths, one starting | |
8517 | at L0, one at L1, and one at L2. | |
197865e8 | 8518 | |
800eeca4 JW |
8519 | L0: nop |
8520 | L1: add | |
8521 | L2: add | |
197865e8 | 8522 | br.ret |
800eeca4 | 8523 | */ |
542d6675 | 8524 | |
800eeca4 JW |
8525 | static void |
8526 | check_dependencies (idesc) | |
542d6675 | 8527 | struct ia64_opcode *idesc; |
800eeca4 JW |
8528 | { |
8529 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
8530 | int path; | |
8531 | int i; | |
8532 | ||
8533 | /* Note that the number of marked resources may change within the | |
197865e8 | 8534 | loop if in auto mode. */ |
800eeca4 JW |
8535 | i = 0; |
8536 | while (i < regdepslen) | |
8537 | { | |
8538 | struct rsrc *rs = ®deps[i]; | |
8539 | const struct ia64_dependency *dep = rs->dependency; | |
8540 | int chkind; | |
8541 | int note; | |
8542 | int start_over = 0; | |
8543 | ||
8544 | if (dep->semantics == IA64_DVS_NONE | |
542d6675 KH |
8545 | || (chkind = depends_on (rs->depind, idesc)) == -1) |
8546 | { | |
8547 | ++i; | |
8548 | continue; | |
8549 | } | |
8550 | ||
8551 | note = NOTE (opdeps->chks[chkind]); | |
8552 | ||
8553 | /* Check this resource against each execution path seen thus far. */ | |
8554 | for (path = 0; path <= md.path; path++) | |
8555 | { | |
8556 | int matchtype; | |
8557 | ||
8558 | /* If the dependency wasn't on the path being checked, ignore it. */ | |
8559 | if (rs->path < path) | |
8560 | continue; | |
8561 | ||
8562 | /* If the QP for this insn implies a QP which has branched, don't | |
8563 | bother checking. Ed. NOTE: I don't think this check is terribly | |
8564 | useful; what's the point of generating code which will only be | |
8565 | reached if its QP is zero? | |
8566 | This code was specifically inserted to handle the following code, | |
8567 | based on notes from Intel's DV checking code, where p1 implies p2. | |
8568 | ||
8569 | mov r4 = 2 | |
8570 | (p2) br.cond L | |
8571 | (p1) mov r4 = 7 | |
8572 | */ | |
8573 | if (CURR_SLOT.qp_regno != 0) | |
8574 | { | |
8575 | int skip = 0; | |
8576 | int implies; | |
8577 | for (implies = 0; implies < qp_implieslen; implies++) | |
8578 | { | |
8579 | if (qp_implies[implies].path >= path | |
8580 | && qp_implies[implies].p1 == CURR_SLOT.qp_regno | |
8581 | && qp_implies[implies].p2_branched) | |
8582 | { | |
8583 | skip = 1; | |
8584 | break; | |
8585 | } | |
8586 | } | |
8587 | if (skip) | |
8588 | continue; | |
8589 | } | |
8590 | ||
8591 | if ((matchtype = resources_match (rs, idesc, note, | |
8592 | CURR_SLOT.qp_regno, path)) != 0) | |
8593 | { | |
8594 | char msg[1024]; | |
8595 | char pathmsg[256] = ""; | |
8596 | char indexmsg[256] = ""; | |
8597 | int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); | |
8598 | ||
8599 | if (path != 0) | |
8600 | sprintf (pathmsg, " when entry is at label '%s'", | |
8601 | md.entry_labels[path - 1]); | |
8602 | if (rs->specific && rs->index != 0) | |
8603 | sprintf (indexmsg, ", specific resource number is %d", | |
8604 | rs->index); | |
8605 | sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", | |
8606 | idesc->name, | |
8607 | (certain ? "violates" : "may violate"), | |
8608 | dv_mode[dep->mode], dep->name, | |
8609 | dv_sem[dep->semantics], | |
8610 | pathmsg, indexmsg); | |
8611 | ||
8612 | if (md.explicit_mode) | |
8613 | { | |
8614 | as_warn ("%s", msg); | |
8615 | if (path < md.path) | |
8616 | as_warn (_("Only the first path encountering the conflict " | |
8617 | "is reported")); | |
8618 | as_warn_where (rs->file, rs->line, | |
8619 | _("This is the location of the " | |
8620 | "conflicting usage")); | |
8621 | /* Don't bother checking other paths, to avoid duplicating | |
8622 | the same warning */ | |
8623 | break; | |
8624 | } | |
8625 | else | |
8626 | { | |
8627 | if (md.debug_dv) | |
8628 | fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); | |
8629 | ||
8630 | remove_marked_resource (rs); | |
8631 | ||
8632 | /* since the set of dependencies has changed, start over */ | |
8633 | /* FIXME -- since we're removing dvs as we go, we | |
8634 | probably don't really need to start over... */ | |
8635 | start_over = 1; | |
8636 | break; | |
8637 | } | |
8638 | } | |
8639 | } | |
800eeca4 | 8640 | if (start_over) |
542d6675 | 8641 | i = 0; |
800eeca4 | 8642 | else |
542d6675 | 8643 | ++i; |
800eeca4 JW |
8644 | } |
8645 | } | |
8646 | ||
542d6675 KH |
8647 | /* Register new dependencies based on the given opcode. */ |
8648 | ||
800eeca4 JW |
8649 | static void |
8650 | mark_resources (idesc) | |
542d6675 | 8651 | struct ia64_opcode *idesc; |
800eeca4 JW |
8652 | { |
8653 | int i; | |
8654 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
8655 | int add_only_qp_reads = 0; | |
8656 | ||
8657 | /* A conditional branch only uses its resources if it is taken; if it is | |
8658 | taken, we stop following that path. The other branch types effectively | |
8659 | *always* write their resources. If it's not taken, register only QP | |
197865e8 | 8660 | reads. */ |
800eeca4 JW |
8661 | if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) |
8662 | { | |
8663 | add_only_qp_reads = 1; | |
8664 | } | |
8665 | ||
8666 | if (md.debug_dv) | |
8667 | fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); | |
8668 | ||
542d6675 | 8669 | for (i = 0; i < opdeps->nregs; i++) |
800eeca4 JW |
8670 | { |
8671 | const struct ia64_dependency *dep; | |
8672 | struct rsrc specs[MAX_SPECS]; | |
8673 | int note; | |
8674 | int path; | |
8675 | int count; | |
197865e8 | 8676 | |
800eeca4 | 8677 | dep = ia64_find_dependency (opdeps->regs[i]); |
542d6675 | 8678 | note = NOTE (opdeps->regs[i]); |
800eeca4 JW |
8679 | |
8680 | if (add_only_qp_reads | |
542d6675 KH |
8681 | && !(dep->mode == IA64_DV_WAR |
8682 | && (dep->specifier == IA64_RS_PR | |
139368c9 | 8683 | || dep->specifier == IA64_RS_PRr |
542d6675 KH |
8684 | || dep->specifier == IA64_RS_PR63))) |
8685 | continue; | |
800eeca4 JW |
8686 | |
8687 | count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); | |
8688 | ||
8689 | #if 0 | |
8690 | if (md.debug_dv && !count) | |
542d6675 KH |
8691 | fprintf (stderr, " No %s %s usage found (path %d)\n", |
8692 | dv_mode[dep->mode], dep->name, md.path); | |
800eeca4 | 8693 | #endif |
197865e8 | 8694 | |
800eeca4 | 8695 | while (count-- > 0) |
542d6675 KH |
8696 | { |
8697 | mark_resource (idesc, dep, &specs[count], | |
8698 | DEP (opdeps->regs[i]), md.path); | |
8699 | } | |
800eeca4 JW |
8700 | |
8701 | /* The execution path may affect register values, which may in turn | |
542d6675 | 8702 | affect which indirect-access resources are accessed. */ |
800eeca4 | 8703 | switch (dep->specifier) |
542d6675 KH |
8704 | { |
8705 | default: | |
8706 | break; | |
8707 | case IA64_RS_CPUID: | |
8708 | case IA64_RS_DBR: | |
8709 | case IA64_RS_IBR: | |
800eeca4 | 8710 | case IA64_RS_MSR: |
542d6675 KH |
8711 | case IA64_RS_PKR: |
8712 | case IA64_RS_PMC: | |
8713 | case IA64_RS_PMD: | |
8714 | case IA64_RS_RR: | |
8715 | for (path = 0; path < md.path; path++) | |
8716 | { | |
8717 | count = specify_resource (dep, idesc, DV_REG, specs, note, path); | |
8718 | while (count-- > 0) | |
8719 | mark_resource (idesc, dep, &specs[count], | |
8720 | DEP (opdeps->regs[i]), path); | |
8721 | } | |
8722 | break; | |
8723 | } | |
8724 | } | |
8725 | } | |
8726 | ||
8727 | /* Remove dependencies when they no longer apply. */ | |
8728 | ||
800eeca4 JW |
8729 | static void |
8730 | update_dependencies (idesc) | |
542d6675 | 8731 | struct ia64_opcode *idesc; |
800eeca4 JW |
8732 | { |
8733 | int i; | |
8734 | ||
8735 | if (strcmp (idesc->name, "srlz.i") == 0) | |
8736 | { | |
8737 | instruction_serialization (); | |
8738 | } | |
8739 | else if (strcmp (idesc->name, "srlz.d") == 0) | |
8740 | { | |
8741 | data_serialization (); | |
8742 | } | |
8743 | else if (is_interruption_or_rfi (idesc) | |
542d6675 | 8744 | || is_taken_branch (idesc)) |
800eeca4 | 8745 | { |
542d6675 KH |
8746 | /* Although technically the taken branch doesn't clear dependencies |
8747 | which require a srlz.[id], we don't follow the branch; the next | |
8748 | instruction is assumed to start with a clean slate. */ | |
800eeca4 | 8749 | regdepslen = 0; |
800eeca4 JW |
8750 | md.path = 0; |
8751 | } | |
8752 | else if (is_conditional_branch (idesc) | |
542d6675 | 8753 | && CURR_SLOT.qp_regno != 0) |
800eeca4 JW |
8754 | { |
8755 | int is_call = strstr (idesc->name, ".call") != NULL; | |
8756 | ||
542d6675 KH |
8757 | for (i = 0; i < qp_implieslen; i++) |
8758 | { | |
8759 | /* If the conditional branch's predicate is implied by the predicate | |
8760 | in an existing dependency, remove that dependency. */ | |
8761 | if (qp_implies[i].p2 == CURR_SLOT.qp_regno) | |
8762 | { | |
8763 | int depind = 0; | |
8764 | /* Note that this implied predicate takes a branch so that if | |
8765 | a later insn generates a DV but its predicate implies this | |
8766 | one, we can avoid the false DV warning. */ | |
8767 | qp_implies[i].p2_branched = 1; | |
8768 | while (depind < regdepslen) | |
8769 | { | |
8770 | if (regdeps[depind].qp_regno == qp_implies[i].p1) | |
8771 | { | |
8772 | print_dependency ("Removing", depind); | |
8773 | regdeps[depind] = regdeps[--regdepslen]; | |
8774 | } | |
8775 | else | |
8776 | ++depind; | |
8777 | } | |
8778 | } | |
8779 | } | |
800eeca4 | 8780 | /* Any marked resources which have this same predicate should be |
542d6675 KH |
8781 | cleared, provided that the QP hasn't been modified between the |
8782 | marking instruction and the branch. */ | |
800eeca4 | 8783 | if (is_call) |
542d6675 KH |
8784 | { |
8785 | insn_group_break (0, CURR_SLOT.qp_regno, 1); | |
8786 | } | |
800eeca4 | 8787 | else |
542d6675 KH |
8788 | { |
8789 | i = 0; | |
8790 | while (i < regdepslen) | |
8791 | { | |
8792 | if (regdeps[i].qp_regno == CURR_SLOT.qp_regno | |
8793 | && regdeps[i].link_to_qp_branch | |
8794 | && (regdeps[i].file != CURR_SLOT.src_file | |
8795 | || regdeps[i].line != CURR_SLOT.src_line)) | |
8796 | { | |
8797 | /* Treat like a taken branch */ | |
8798 | print_dependency ("Removing", i); | |
8799 | regdeps[i] = regdeps[--regdepslen]; | |
8800 | } | |
8801 | else | |
8802 | ++i; | |
8803 | } | |
8804 | } | |
800eeca4 JW |
8805 | } |
8806 | } | |
8807 | ||
8808 | /* Examine the current instruction for dependency violations. */ | |
542d6675 | 8809 | |
800eeca4 JW |
8810 | static int |
8811 | check_dv (idesc) | |
542d6675 | 8812 | struct ia64_opcode *idesc; |
800eeca4 JW |
8813 | { |
8814 | if (md.debug_dv) | |
8815 | { | |
197865e8 | 8816 | fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", |
542d6675 KH |
8817 | idesc->name, CURR_SLOT.src_line, |
8818 | idesc->dependencies->nchks, | |
8819 | idesc->dependencies->nregs); | |
800eeca4 JW |
8820 | } |
8821 | ||
197865e8 | 8822 | /* Look through the list of currently marked resources; if the current |
800eeca4 | 8823 | instruction has the dependency in its chks list which uses that resource, |
542d6675 | 8824 | check against the specific resources used. */ |
800eeca4 JW |
8825 | check_dependencies (idesc); |
8826 | ||
542d6675 KH |
8827 | /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), |
8828 | then add them to the list of marked resources. */ | |
800eeca4 JW |
8829 | mark_resources (idesc); |
8830 | ||
8831 | /* There are several types of dependency semantics, and each has its own | |
197865e8 KH |
8832 | requirements for being cleared |
8833 | ||
800eeca4 JW |
8834 | Instruction serialization (insns separated by interruption, rfi, or |
8835 | writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. | |
8836 | ||
8837 | Data serialization (instruction serialization, or writer + srlz.d + | |
8838 | reader, where writer and srlz.d are in separate groups) clears | |
8839 | DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to | |
8840 | always be the case). | |
8841 | ||
8842 | Instruction group break (groups separated by stop, taken branch, | |
8843 | interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. | |
8844 | */ | |
8845 | update_dependencies (idesc); | |
8846 | ||
8847 | /* Sometimes, knowing a register value allows us to avoid giving a false DV | |
197865e8 | 8848 | warning. Keep track of as many as possible that are useful. */ |
800eeca4 JW |
8849 | note_register_values (idesc); |
8850 | ||
197865e8 | 8851 | /* We don't need or want this anymore. */ |
800eeca4 JW |
8852 | md.mem_offset.hint = 0; |
8853 | ||
8854 | return 0; | |
8855 | } | |
8856 | ||
8857 | /* Translate one line of assembly. Pseudo ops and labels do not show | |
8858 | here. */ | |
8859 | void | |
8860 | md_assemble (str) | |
8861 | char *str; | |
8862 | { | |
8863 | char *saved_input_line_pointer, *mnemonic; | |
8864 | const struct pseudo_opcode *pdesc; | |
8865 | struct ia64_opcode *idesc; | |
8866 | unsigned char qp_regno; | |
8867 | unsigned int flags; | |
8868 | int ch; | |
8869 | ||
8870 | saved_input_line_pointer = input_line_pointer; | |
8871 | input_line_pointer = str; | |
8872 | ||
542d6675 | 8873 | /* extract the opcode (mnemonic): */ |
800eeca4 JW |
8874 | |
8875 | mnemonic = input_line_pointer; | |
8876 | ch = get_symbol_end (); | |
8877 | pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); | |
8878 | if (pdesc) | |
8879 | { | |
8880 | *input_line_pointer = ch; | |
8881 | (*pdesc->handler) (pdesc->arg); | |
8882 | goto done; | |
8883 | } | |
8884 | ||
542d6675 | 8885 | /* Find the instruction descriptor matching the arguments. */ |
800eeca4 JW |
8886 | |
8887 | idesc = ia64_find_opcode (mnemonic); | |
8888 | *input_line_pointer = ch; | |
8889 | if (!idesc) | |
8890 | { | |
8891 | as_bad ("Unknown opcode `%s'", mnemonic); | |
8892 | goto done; | |
8893 | } | |
8894 | ||
8895 | idesc = parse_operands (idesc); | |
8896 | if (!idesc) | |
8897 | goto done; | |
8898 | ||
542d6675 | 8899 | /* Handle the dynamic ops we can handle now: */ |
800eeca4 JW |
8900 | if (idesc->type == IA64_TYPE_DYN) |
8901 | { | |
8902 | if (strcmp (idesc->name, "add") == 0) | |
8903 | { | |
8904 | if (CURR_SLOT.opnd[2].X_op == O_register | |
8905 | && CURR_SLOT.opnd[2].X_add_number < 4) | |
8906 | mnemonic = "addl"; | |
8907 | else | |
8908 | mnemonic = "adds"; | |
3d56ab85 | 8909 | ia64_free_opcode (idesc); |
800eeca4 JW |
8910 | idesc = ia64_find_opcode (mnemonic); |
8911 | #if 0 | |
8912 | know (!idesc->next); | |
8913 | #endif | |
8914 | } | |
8915 | else if (strcmp (idesc->name, "mov") == 0) | |
8916 | { | |
8917 | enum ia64_opnd opnd1, opnd2; | |
8918 | int rop; | |
8919 | ||
8920 | opnd1 = idesc->operands[0]; | |
8921 | opnd2 = idesc->operands[1]; | |
8922 | if (opnd1 == IA64_OPND_AR3) | |
8923 | rop = 0; | |
8924 | else if (opnd2 == IA64_OPND_AR3) | |
8925 | rop = 1; | |
8926 | else | |
8927 | abort (); | |
8928 | if (CURR_SLOT.opnd[rop].X_op == O_register | |
8929 | && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) | |
8930 | mnemonic = "mov.i"; | |
8931 | else | |
8932 | mnemonic = "mov.m"; | |
3d56ab85 | 8933 | ia64_free_opcode (idesc); |
800eeca4 JW |
8934 | idesc = ia64_find_opcode (mnemonic); |
8935 | while (idesc != NULL | |
8936 | && (idesc->operands[0] != opnd1 | |
8937 | || idesc->operands[1] != opnd2)) | |
8938 | idesc = get_next_opcode (idesc); | |
8939 | } | |
8940 | } | |
8941 | ||
8942 | qp_regno = 0; | |
8943 | if (md.qp.X_op == O_register) | |
f1bcba5b JW |
8944 | { |
8945 | qp_regno = md.qp.X_add_number - REG_P; | |
8946 | md.qp.X_op = O_absent; | |
8947 | } | |
800eeca4 JW |
8948 | |
8949 | flags = idesc->flags; | |
8950 | ||
8951 | if ((flags & IA64_OPCODE_FIRST) != 0) | |
8952 | insn_group_break (1, 0, 0); | |
8953 | ||
8954 | if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) | |
8955 | { | |
8956 | as_bad ("`%s' cannot be predicated", idesc->name); | |
8957 | goto done; | |
8958 | } | |
8959 | ||
542d6675 | 8960 | /* Build the instruction. */ |
800eeca4 JW |
8961 | CURR_SLOT.qp_regno = qp_regno; |
8962 | CURR_SLOT.idesc = idesc; | |
8963 | as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); | |
8964 | if (debug_type == DEBUG_DWARF2) | |
8965 | dwarf2_where (&CURR_SLOT.debug_line); | |
8966 | ||
8967 | /* Add unwind entry, if there is one. */ | |
e0c9811a | 8968 | if (unwind.current_entry) |
800eeca4 | 8969 | { |
e0c9811a JW |
8970 | CURR_SLOT.unwind_record = unwind.current_entry; |
8971 | unwind.current_entry = NULL; | |
800eeca4 JW |
8972 | } |
8973 | ||
542d6675 | 8974 | /* Check for dependency violations. */ |
800eeca4 | 8975 | if (md.detect_dv) |
542d6675 | 8976 | check_dv (idesc); |
800eeca4 JW |
8977 | |
8978 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
8979 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
8980 | emit_one_bundle (); | |
8981 | ||
8982 | if ((flags & IA64_OPCODE_LAST) != 0) | |
8983 | insn_group_break (1, 0, 0); | |
8984 | ||
8985 | md.last_text_seg = now_seg; | |
8986 | ||
8987 | done: | |
8988 | input_line_pointer = saved_input_line_pointer; | |
8989 | } | |
8990 | ||
8991 | /* Called when symbol NAME cannot be found in the symbol table. | |
8992 | Should be used for dynamic valued symbols only. */ | |
542d6675 KH |
8993 | |
8994 | symbolS * | |
800eeca4 JW |
8995 | md_undefined_symbol (name) |
8996 | char *name; | |
8997 | { | |
8998 | return 0; | |
8999 | } | |
9000 | ||
9001 | /* Called for any expression that can not be recognized. When the | |
9002 | function is called, `input_line_pointer' will point to the start of | |
9003 | the expression. */ | |
542d6675 | 9004 | |
800eeca4 JW |
9005 | void |
9006 | md_operand (e) | |
9007 | expressionS *e; | |
9008 | { | |
9009 | enum pseudo_type pseudo_type; | |
e0c9811a | 9010 | const char *name; |
800eeca4 JW |
9011 | size_t len; |
9012 | int ch, i; | |
9013 | ||
9014 | switch (*input_line_pointer) | |
9015 | { | |
9016 | case '@': | |
542d6675 | 9017 | /* Find what relocation pseudo-function we're dealing with. */ |
800eeca4 JW |
9018 | pseudo_type = 0; |
9019 | ch = *++input_line_pointer; | |
9020 | for (i = 0; i < NELEMS (pseudo_func); ++i) | |
9021 | if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) | |
9022 | { | |
9023 | len = strlen (pseudo_func[i].name); | |
9024 | if (strncmp (pseudo_func[i].name + 1, | |
9025 | input_line_pointer + 1, len - 1) == 0 | |
9026 | && !is_part_of_name (input_line_pointer[len])) | |
9027 | { | |
9028 | input_line_pointer += len; | |
9029 | pseudo_type = pseudo_func[i].type; | |
9030 | break; | |
9031 | } | |
9032 | } | |
9033 | switch (pseudo_type) | |
9034 | { | |
9035 | case PSEUDO_FUNC_RELOC: | |
9036 | SKIP_WHITESPACE (); | |
9037 | if (*input_line_pointer != '(') | |
9038 | { | |
9039 | as_bad ("Expected '('"); | |
9040 | goto err; | |
9041 | } | |
542d6675 KH |
9042 | /* Skip '('. */ |
9043 | ++input_line_pointer; | |
800eeca4 JW |
9044 | expression (e); |
9045 | if (*input_line_pointer++ != ')') | |
9046 | { | |
9047 | as_bad ("Missing ')'"); | |
9048 | goto err; | |
9049 | } | |
9050 | if (e->X_op != O_symbol) | |
9051 | { | |
9052 | if (e->X_op != O_pseudo_fixup) | |
9053 | { | |
9054 | as_bad ("Not a symbolic expression"); | |
9055 | goto err; | |
9056 | } | |
9057 | if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE | |
9058 | && i == FUNC_LT_RELATIVE) | |
9059 | i = FUNC_LT_FPTR_RELATIVE; | |
9060 | else | |
9061 | { | |
9062 | as_bad ("Illegal combination of relocation functions"); | |
9063 | goto err; | |
9064 | } | |
9065 | } | |
542d6675 KH |
9066 | /* Make sure gas doesn't get rid of local symbols that are used |
9067 | in relocs. */ | |
800eeca4 JW |
9068 | e->X_op = O_pseudo_fixup; |
9069 | e->X_op_symbol = pseudo_func[i].u.sym; | |
9070 | break; | |
9071 | ||
9072 | case PSEUDO_FUNC_CONST: | |
9073 | e->X_op = O_constant; | |
9074 | e->X_add_number = pseudo_func[i].u.ival; | |
9075 | break; | |
9076 | ||
e0c9811a JW |
9077 | case PSEUDO_FUNC_REG: |
9078 | e->X_op = O_register; | |
9079 | e->X_add_number = pseudo_func[i].u.ival; | |
9080 | break; | |
9081 | ||
800eeca4 | 9082 | default: |
e0c9811a JW |
9083 | name = input_line_pointer - 1; |
9084 | get_symbol_end (); | |
9085 | as_bad ("Unknown pseudo function `%s'", name); | |
800eeca4 JW |
9086 | goto err; |
9087 | } | |
9088 | break; | |
9089 | ||
9090 | case '[': | |
9091 | ++input_line_pointer; | |
9092 | expression (e); | |
9093 | if (*input_line_pointer != ']') | |
9094 | { | |
9095 | as_bad ("Closing bracket misssing"); | |
9096 | goto err; | |
9097 | } | |
9098 | else | |
9099 | { | |
9100 | if (e->X_op != O_register) | |
9101 | as_bad ("Register expected as index"); | |
9102 | ||
9103 | ++input_line_pointer; | |
9104 | e->X_op = O_index; | |
9105 | } | |
9106 | break; | |
9107 | ||
9108 | default: | |
9109 | break; | |
9110 | } | |
9111 | return; | |
9112 | ||
9113 | err: | |
9114 | ignore_rest_of_line (); | |
9115 | } | |
9116 | ||
9117 | /* Return 1 if it's OK to adjust a reloc by replacing the symbol with | |
9118 | a section symbol plus some offset. For relocs involving @fptr(), | |
9119 | directives we don't want such adjustments since we need to have the | |
9120 | original symbol's name in the reloc. */ | |
9121 | int | |
9122 | ia64_fix_adjustable (fix) | |
9123 | fixS *fix; | |
9124 | { | |
9125 | /* Prevent all adjustments to global symbols */ | |
9126 | if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) | |
9127 | return 0; | |
9128 | ||
9129 | switch (fix->fx_r_type) | |
9130 | { | |
9131 | case BFD_RELOC_IA64_FPTR64I: | |
9132 | case BFD_RELOC_IA64_FPTR32MSB: | |
9133 | case BFD_RELOC_IA64_FPTR32LSB: | |
9134 | case BFD_RELOC_IA64_FPTR64MSB: | |
9135 | case BFD_RELOC_IA64_FPTR64LSB: | |
9136 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9137 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9138 | return 0; | |
9139 | default: | |
9140 | break; | |
9141 | } | |
9142 | ||
9143 | return 1; | |
9144 | } | |
9145 | ||
9146 | int | |
9147 | ia64_force_relocation (fix) | |
9148 | fixS *fix; | |
9149 | { | |
9150 | switch (fix->fx_r_type) | |
9151 | { | |
9152 | case BFD_RELOC_IA64_FPTR64I: | |
9153 | case BFD_RELOC_IA64_FPTR32MSB: | |
9154 | case BFD_RELOC_IA64_FPTR32LSB: | |
9155 | case BFD_RELOC_IA64_FPTR64MSB: | |
9156 | case BFD_RELOC_IA64_FPTR64LSB: | |
9157 | ||
9158 | case BFD_RELOC_IA64_LTOFF22: | |
9159 | case BFD_RELOC_IA64_LTOFF64I: | |
9160 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9161 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9162 | case BFD_RELOC_IA64_PLTOFF22: | |
9163 | case BFD_RELOC_IA64_PLTOFF64I: | |
9164 | case BFD_RELOC_IA64_PLTOFF64MSB: | |
9165 | case BFD_RELOC_IA64_PLTOFF64LSB: | |
9166 | return 1; | |
9167 | ||
9168 | default: | |
9169 | return 0; | |
9170 | } | |
9171 | return 0; | |
9172 | } | |
9173 | ||
9174 | /* Decide from what point a pc-relative relocation is relative to, | |
9175 | relative to the pc-relative fixup. Er, relatively speaking. */ | |
9176 | long | |
9177 | ia64_pcrel_from_section (fix, sec) | |
9178 | fixS *fix; | |
9179 | segT sec; | |
9180 | { | |
9181 | unsigned long off = fix->fx_frag->fr_address + fix->fx_where; | |
197865e8 | 9182 | |
800eeca4 JW |
9183 | if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) |
9184 | off &= ~0xfUL; | |
9185 | ||
9186 | return off; | |
9187 | } | |
9188 | ||
9189 | /* This is called whenever some data item (not an instruction) needs a | |
9190 | fixup. We pick the right reloc code depending on the byteorder | |
9191 | currently in effect. */ | |
9192 | void | |
9193 | ia64_cons_fix_new (f, where, nbytes, exp) | |
9194 | fragS *f; | |
9195 | int where; | |
9196 | int nbytes; | |
9197 | expressionS *exp; | |
9198 | { | |
9199 | bfd_reloc_code_real_type code; | |
9200 | fixS *fix; | |
9201 | ||
9202 | switch (nbytes) | |
9203 | { | |
9204 | /* There are no reloc for 8 and 16 bit quantities, but we allow | |
9205 | them here since they will work fine as long as the expression | |
9206 | is fully defined at the end of the pass over the source file. */ | |
9207 | case 1: code = BFD_RELOC_8; break; | |
9208 | case 2: code = BFD_RELOC_16; break; | |
9209 | case 4: | |
9210 | if (target_big_endian) | |
9211 | code = BFD_RELOC_IA64_DIR32MSB; | |
9212 | else | |
9213 | code = BFD_RELOC_IA64_DIR32LSB; | |
9214 | break; | |
9215 | ||
9216 | case 8: | |
9217 | if (target_big_endian) | |
9218 | code = BFD_RELOC_IA64_DIR64MSB; | |
9219 | else | |
9220 | code = BFD_RELOC_IA64_DIR64LSB; | |
9221 | break; | |
9222 | ||
9223 | default: | |
9224 | as_bad ("Unsupported fixup size %d", nbytes); | |
9225 | ignore_rest_of_line (); | |
9226 | return; | |
9227 | } | |
9228 | if (exp->X_op == O_pseudo_fixup) | |
9229 | { | |
9230 | /* ??? */ | |
9231 | exp->X_op = O_symbol; | |
9232 | code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); | |
9233 | } | |
9234 | fix = fix_new_exp (f, where, nbytes, exp, 0, code); | |
9235 | /* We need to store the byte order in effect in case we're going | |
9236 | to fix an 8 or 16 bit relocation (for which there no real | |
9237 | relocs available). See md_apply_fix(). */ | |
9238 | fix->tc_fix_data.bigendian = target_big_endian; | |
9239 | } | |
9240 | ||
9241 | /* Return the actual relocation we wish to associate with the pseudo | |
9242 | reloc described by SYM and R_TYPE. SYM should be one of the | |
197865e8 | 9243 | symbols in the pseudo_func array, or NULL. */ |
800eeca4 JW |
9244 | |
9245 | static bfd_reloc_code_real_type | |
9246 | ia64_gen_real_reloc_type (sym, r_type) | |
9247 | struct symbol *sym; | |
9248 | bfd_reloc_code_real_type r_type; | |
9249 | { | |
9250 | bfd_reloc_code_real_type new = 0; | |
9251 | ||
9252 | if (sym == NULL) | |
9253 | { | |
9254 | return r_type; | |
9255 | } | |
9256 | ||
9257 | switch (S_GET_VALUE (sym)) | |
9258 | { | |
9259 | case FUNC_FPTR_RELATIVE: | |
9260 | switch (r_type) | |
9261 | { | |
9262 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; | |
9263 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; | |
9264 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; | |
9265 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; | |
9266 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; | |
9267 | default: break; | |
9268 | } | |
9269 | break; | |
9270 | ||
9271 | case FUNC_GP_RELATIVE: | |
9272 | switch (r_type) | |
9273 | { | |
9274 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; | |
9275 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; | |
9276 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; | |
9277 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; | |
9278 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; | |
9279 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; | |
9280 | default: break; | |
9281 | } | |
9282 | break; | |
9283 | ||
9284 | case FUNC_LT_RELATIVE: | |
9285 | switch (r_type) | |
9286 | { | |
9287 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; | |
9288 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; | |
9289 | default: break; | |
9290 | } | |
9291 | break; | |
9292 | ||
c67e42c9 RH |
9293 | case FUNC_PC_RELATIVE: |
9294 | switch (r_type) | |
9295 | { | |
9296 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; | |
9297 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; | |
9298 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; | |
9299 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; | |
9300 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; | |
9301 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; | |
9302 | default: break; | |
9303 | } | |
9304 | break; | |
9305 | ||
800eeca4 JW |
9306 | case FUNC_PLT_RELATIVE: |
9307 | switch (r_type) | |
9308 | { | |
9309 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; | |
9310 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; | |
9311 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; | |
9312 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; | |
9313 | default: break; | |
9314 | } | |
9315 | break; | |
9316 | ||
9317 | case FUNC_SEC_RELATIVE: | |
9318 | switch (r_type) | |
9319 | { | |
9320 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; | |
9321 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; | |
9322 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; | |
9323 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; | |
9324 | default: break; | |
9325 | } | |
9326 | break; | |
9327 | ||
9328 | case FUNC_SEG_RELATIVE: | |
9329 | switch (r_type) | |
9330 | { | |
9331 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; | |
9332 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; | |
9333 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; | |
9334 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; | |
9335 | default: break; | |
9336 | } | |
9337 | break; | |
9338 | ||
9339 | case FUNC_LTV_RELATIVE: | |
9340 | switch (r_type) | |
9341 | { | |
9342 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; | |
9343 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; | |
9344 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; | |
9345 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; | |
9346 | default: break; | |
9347 | } | |
9348 | break; | |
9349 | ||
9350 | case FUNC_LT_FPTR_RELATIVE: | |
9351 | switch (r_type) | |
9352 | { | |
9353 | case BFD_RELOC_IA64_IMM22: | |
9354 | new = BFD_RELOC_IA64_LTOFF_FPTR22; break; | |
9355 | case BFD_RELOC_IA64_IMM64: | |
9356 | new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; | |
9357 | default: | |
9358 | break; | |
9359 | } | |
9360 | break; | |
9361 | default: | |
9362 | abort (); | |
9363 | } | |
9364 | /* Hmmmm. Should this ever occur? */ | |
9365 | if (new) | |
9366 | return new; | |
9367 | else | |
9368 | return r_type; | |
9369 | } | |
9370 | ||
9371 | /* Here is where generate the appropriate reloc for pseudo relocation | |
9372 | functions. */ | |
9373 | void | |
9374 | ia64_validate_fix (fix) | |
9375 | fixS *fix; | |
9376 | { | |
9377 | switch (fix->fx_r_type) | |
9378 | { | |
9379 | case BFD_RELOC_IA64_FPTR64I: | |
9380 | case BFD_RELOC_IA64_FPTR32MSB: | |
9381 | case BFD_RELOC_IA64_FPTR64LSB: | |
9382 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
9383 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
9384 | if (fix->fx_offset != 0) | |
9385 | as_bad_where (fix->fx_file, fix->fx_line, | |
9386 | "No addend allowed in @fptr() relocation"); | |
9387 | break; | |
9388 | default: | |
9389 | break; | |
9390 | } | |
9391 | ||
9392 | return; | |
9393 | } | |
9394 | ||
9395 | static void | |
9396 | fix_insn (fix, odesc, value) | |
9397 | fixS *fix; | |
9398 | const struct ia64_operand *odesc; | |
9399 | valueT value; | |
9400 | { | |
9401 | bfd_vma insn[3], t0, t1, control_bits; | |
9402 | const char *err; | |
9403 | char *fixpos; | |
9404 | long slot; | |
9405 | ||
9406 | slot = fix->fx_where & 0x3; | |
9407 | fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); | |
9408 | ||
c67e42c9 | 9409 | /* Bundles are always in little-endian byte order */ |
800eeca4 JW |
9410 | t0 = bfd_getl64 (fixpos); |
9411 | t1 = bfd_getl64 (fixpos + 8); | |
9412 | control_bits = t0 & 0x1f; | |
9413 | insn[0] = (t0 >> 5) & 0x1ffffffffffLL; | |
9414 | insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); | |
9415 | insn[2] = (t1 >> 23) & 0x1ffffffffffLL; | |
9416 | ||
c67e42c9 RH |
9417 | err = NULL; |
9418 | if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) | |
800eeca4 | 9419 | { |
c67e42c9 RH |
9420 | insn[1] = (value >> 22) & 0x1ffffffffffLL; |
9421 | insn[2] |= (((value & 0x7f) << 13) | |
9422 | | (((value >> 7) & 0x1ff) << 27) | |
9423 | | (((value >> 16) & 0x1f) << 22) | |
9424 | | (((value >> 21) & 0x1) << 21) | |
9425 | | (((value >> 63) & 0x1) << 36)); | |
800eeca4 | 9426 | } |
c67e42c9 RH |
9427 | else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) |
9428 | { | |
9429 | if (value & ~0x3fffffffffffffffULL) | |
9430 | err = "integer operand out of range"; | |
9431 | insn[1] = (value >> 21) & 0x1ffffffffffLL; | |
9432 | insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); | |
9433 | } | |
9434 | else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) | |
9435 | { | |
9436 | value >>= 4; | |
9437 | insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; | |
9438 | insn[2] |= ((((value >> 59) & 0x1) << 36) | |
9439 | | (((value >> 0) & 0xfffff) << 13)); | |
9440 | } | |
9441 | else | |
9442 | err = (*odesc->insert) (odesc, value, insn + slot); | |
9443 | ||
9444 | if (err) | |
9445 | as_bad_where (fix->fx_file, fix->fx_line, err); | |
800eeca4 JW |
9446 | |
9447 | t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); | |
9448 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
44f5c83a JW |
9449 | number_to_chars_littleendian (fixpos + 0, t0, 8); |
9450 | number_to_chars_littleendian (fixpos + 8, t1, 8); | |
800eeca4 JW |
9451 | } |
9452 | ||
9453 | /* Attempt to simplify or even eliminate a fixup. The return value is | |
9454 | ignored; perhaps it was once meaningful, but now it is historical. | |
9455 | To indicate that a fixup has been eliminated, set FIXP->FX_DONE. | |
9456 | ||
9457 | If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry | |
197865e8 | 9458 | (if possible). */ |
800eeca4 JW |
9459 | int |
9460 | md_apply_fix3 (fix, valuep, seg) | |
9461 | fixS *fix; | |
9462 | valueT *valuep; | |
9463 | segT seg; | |
9464 | { | |
9465 | char *fixpos; | |
9466 | valueT value = *valuep; | |
9467 | int adjust = 0; | |
9468 | ||
9469 | fixpos = fix->fx_frag->fr_literal + fix->fx_where; | |
9470 | ||
9471 | if (fix->fx_pcrel) | |
9472 | { | |
9473 | switch (fix->fx_r_type) | |
9474 | { | |
9475 | case BFD_RELOC_IA64_DIR32MSB: | |
9476 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; | |
9477 | adjust = 1; | |
9478 | break; | |
9479 | ||
9480 | case BFD_RELOC_IA64_DIR32LSB: | |
9481 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; | |
9482 | adjust = 1; | |
9483 | break; | |
9484 | ||
9485 | case BFD_RELOC_IA64_DIR64MSB: | |
9486 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; | |
9487 | adjust = 1; | |
9488 | break; | |
9489 | ||
9490 | case BFD_RELOC_IA64_DIR64LSB: | |
9491 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; | |
9492 | adjust = 1; | |
9493 | break; | |
9494 | ||
9495 | default: | |
9496 | break; | |
9497 | } | |
9498 | } | |
9499 | if (fix->fx_addsy) | |
9500 | { | |
9501 | switch (fix->fx_r_type) | |
9502 | { | |
9503 | case 0: | |
9504 | as_bad_where (fix->fx_file, fix->fx_line, | |
9505 | "%s must have a constant value", | |
9506 | elf64_ia64_operands[fix->tc_fix_data.opnd].desc); | |
9507 | break; | |
9508 | ||
9509 | default: | |
9510 | break; | |
9511 | } | |
9512 | ||
9513 | /* ??? This is a hack copied from tc-i386.c to make PCREL relocs | |
542d6675 | 9514 | work. There should be a better way to handle this. */ |
800eeca4 JW |
9515 | if (adjust) |
9516 | fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; | |
9517 | } | |
9518 | else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) | |
9519 | { | |
9520 | if (fix->tc_fix_data.bigendian) | |
9521 | number_to_chars_bigendian (fixpos, value, fix->fx_size); | |
9522 | else | |
9523 | number_to_chars_littleendian (fixpos, value, fix->fx_size); | |
9524 | fix->fx_done = 1; | |
9525 | return 1; | |
9526 | } | |
9527 | else | |
9528 | { | |
9529 | fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); | |
9530 | fix->fx_done = 1; | |
9531 | return 1; | |
9532 | } | |
9533 | return 1; | |
9534 | } | |
9535 | ||
9536 | /* Generate the BFD reloc to be stuck in the object file from the | |
9537 | fixup used internally in the assembler. */ | |
542d6675 KH |
9538 | |
9539 | arelent * | |
800eeca4 JW |
9540 | tc_gen_reloc (sec, fixp) |
9541 | asection *sec; | |
9542 | fixS *fixp; | |
9543 | { | |
9544 | arelent *reloc; | |
9545 | ||
9546 | reloc = xmalloc (sizeof (*reloc)); | |
9547 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
9548 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
9549 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9550 | reloc->addend = fixp->fx_offset; | |
9551 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
9552 | ||
9553 | if (!reloc->howto) | |
9554 | { | |
9555 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9556 | "Cannot represent %s relocation in object file", | |
9557 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
9558 | } | |
9559 | return reloc; | |
9560 | } | |
9561 | ||
9562 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9563 | of type TYPE, and store the appropriate bytes in *LIT. The number |
9564 | of LITTLENUMS emitted is stored in *SIZE. An error message is | |
800eeca4 JW |
9565 | returned, or NULL on OK. */ |
9566 | ||
9567 | #define MAX_LITTLENUMS 5 | |
9568 | ||
542d6675 | 9569 | char * |
800eeca4 JW |
9570 | md_atof (type, lit, size) |
9571 | int type; | |
9572 | char *lit; | |
9573 | int *size; | |
9574 | { | |
9575 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
9576 | LITTLENUM_TYPE *word; | |
9577 | char *t; | |
9578 | int prec; | |
9579 | ||
9580 | switch (type) | |
9581 | { | |
9582 | /* IEEE floats */ | |
9583 | case 'f': | |
9584 | case 'F': | |
9585 | case 's': | |
9586 | case 'S': | |
9587 | prec = 2; | |
9588 | break; | |
9589 | ||
9590 | case 'd': | |
9591 | case 'D': | |
9592 | case 'r': | |
9593 | case 'R': | |
9594 | prec = 4; | |
9595 | break; | |
9596 | ||
9597 | case 'x': | |
9598 | case 'X': | |
9599 | case 'p': | |
9600 | case 'P': | |
9601 | prec = 5; | |
9602 | break; | |
9603 | ||
9604 | default: | |
9605 | *size = 0; | |
9606 | return "Bad call to MD_ATOF()"; | |
9607 | } | |
9608 | t = atof_ieee (input_line_pointer, type, words); | |
9609 | if (t) | |
9610 | input_line_pointer = t; | |
9611 | *size = prec * sizeof (LITTLENUM_TYPE); | |
9612 | ||
9613 | for (word = words + prec - 1; prec--;) | |
9614 | { | |
9615 | md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); | |
9616 | lit += sizeof (LITTLENUM_TYPE); | |
9617 | } | |
9618 | return 0; | |
9619 | } | |
9620 | ||
9621 | /* Round up a section's size to the appropriate boundary. */ | |
9622 | valueT | |
9623 | md_section_align (seg, size) | |
9624 | segT seg; | |
9625 | valueT size; | |
9626 | { | |
9627 | int align = bfd_get_section_alignment (stdoutput, seg); | |
197865e8 | 9628 | valueT mask = ((valueT) 1 << align) - 1; |
800eeca4 JW |
9629 | |
9630 | return (size + mask) & ~mask; | |
9631 | } | |
9632 | ||
9633 | /* Handle ia64 specific semantics of the align directive. */ | |
9634 | ||
9635 | int | |
9636 | ia64_md_do_align (n, fill, len, max) | |
9637 | int n; | |
9638 | const char *fill; | |
9639 | int len; | |
9640 | int max; | |
9641 | { | |
9642 | /* Fill any pending bundle with nops. */ | |
9643 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) | |
9644 | ia64_flush_insns (); | |
9645 | ||
9646 | /* When we align code in a text section, emit a bundle of 3 nops instead of | |
9647 | zero bytes. We can only do this if a multiple of 16 bytes was requested. | |
9648 | N is log base 2 of the requested alignment. */ | |
9649 | if (fill == NULL | |
9650 | && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE | |
9651 | && n > 4) | |
9652 | { | |
9653 | /* Use mfi bundle of nops with no stop bits. */ | |
9654 | static const unsigned char be_nop[] | |
9655 | = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, | |
9656 | 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; | |
9657 | static const unsigned char le_nop[] | |
9658 | = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, | |
9659 | 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; | |
197865e8 | 9660 | |
800eeca4 JW |
9661 | /* Make sure we are on a 16-byte boundary, in case someone has been |
9662 | putting data into a text section. */ | |
9663 | frag_align (4, 0, 0); | |
9664 | ||
9665 | if (target_big_endian) | |
9666 | frag_align_pattern (n, be_nop, 16, max); | |
9667 | else | |
9668 | frag_align_pattern (n, le_nop, 16, max); | |
9669 | return 1; | |
9670 | } | |
9671 | ||
9672 | return 0; | |
9673 | } |