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1 | /* tc-m32c.c -- Assembler for the Renesas M32C. |
2 | Copyright (C) 2005 Free Software Foundation. | |
3 | Contributed by RedHat. | |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "symcat.h" | |
26 | #include "opcodes/m32c-desc.h" | |
27 | #include "opcodes/m32c-opc.h" | |
28 | #include "cgen.h" | |
29 | #include "elf/common.h" | |
30 | #include "elf/m32c.h" | |
31 | #include "libbfd.h" | |
32 | #include "libiberty.h" | |
33 | #include "safe-ctype.h" | |
34 | ||
35 | /* Structure to hold all of the different components | |
36 | describing an individual instruction. */ | |
37 | typedef struct | |
38 | { | |
39 | const CGEN_INSN * insn; | |
40 | const CGEN_INSN * orig_insn; | |
41 | CGEN_FIELDS fields; | |
42 | #if CGEN_INT_INSN_P | |
43 | CGEN_INSN_INT buffer [1]; | |
44 | #define INSN_VALUE(buf) (*(buf)) | |
45 | #else | |
46 | unsigned char buffer [CGEN_MAX_INSN_SIZE]; | |
47 | #define INSN_VALUE(buf) (buf) | |
48 | #endif | |
49 | char * addr; | |
50 | fragS * frag; | |
51 | int num_fixups; | |
52 | fixS * fixups [GAS_CGEN_MAX_FIXUPS]; | |
53 | int indices [MAX_OPERAND_INSTANCES]; | |
54 | } | |
55 | m32c_insn; | |
56 | ||
57 | const char comment_chars[] = ";"; | |
58 | const char line_comment_chars[] = "#"; | |
59 | const char line_separator_chars[] = "|"; | |
60 | const char EXP_CHARS[] = "eE"; | |
61 | const char FLT_CHARS[] = "dD"; | |
62 | \f | |
63 | #define M32C_SHORTOPTS "" | |
64 | const char * md_shortopts = M32C_SHORTOPTS; | |
65 | ||
66 | /* assembler options */ | |
67 | #define OPTION_CPU_M16C (OPTION_MD_BASE) | |
68 | #define OPTION_CPU_M32C (OPTION_MD_BASE + 1) | |
69 | ||
70 | struct option md_longopts[] = | |
71 | { | |
72 | { "m16c", no_argument, NULL, OPTION_CPU_M16C }, | |
73 | { "m32c", no_argument, NULL, OPTION_CPU_M32C }, | |
74 | {NULL, no_argument, NULL, 0} | |
75 | }; | |
76 | size_t md_longopts_size = sizeof (md_longopts); | |
77 | ||
78 | /* Default machine */ | |
79 | ||
80 | #define DEFAULT_MACHINE bfd_mach_m16c | |
81 | #define DEFAULT_FLAGS EF_M32C_CPU_M16C | |
82 | ||
83 | static unsigned long m32c_mach = bfd_mach_m16c; | |
84 | static int cpu_mach = (1 << MACH_M16C); | |
85 | static int insn_size; | |
86 | ||
87 | /* Flags to set in the elf header */ | |
88 | static flagword m32c_flags = DEFAULT_FLAGS; | |
89 | ||
90 | static unsigned int m32c_isa = (1 << ISA_M16C); | |
91 | ||
92 | static void | |
93 | set_isa (enum isa_attr isa_num) | |
94 | { | |
95 | m32c_isa = (1 << isa_num); | |
96 | } | |
97 | ||
98 | static void s_bss (int); | |
99 | ||
100 | int | |
101 | md_parse_option (int c, char * arg ATTRIBUTE_UNUSED) | |
102 | { | |
103 | switch (c) | |
104 | { | |
105 | case OPTION_CPU_M16C: | |
106 | m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C; | |
107 | m32c_mach = bfd_mach_m16c; | |
108 | cpu_mach = (1 << MACH_M16C); | |
109 | set_isa (ISA_M16C); | |
110 | break; | |
111 | ||
112 | case OPTION_CPU_M32C: | |
113 | m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C; | |
114 | m32c_mach = bfd_mach_m32c; | |
115 | cpu_mach = (1 << MACH_M32C); | |
116 | set_isa (ISA_M32C); | |
117 | break; | |
118 | ||
119 | default: | |
120 | return 0; | |
121 | } | |
122 | return 1; | |
123 | } | |
124 | ||
125 | void | |
126 | md_show_usage (FILE * stream) | |
127 | { | |
128 | fprintf (stream, _(" M32C specific command line options:\n")); | |
129 | } | |
130 | ||
131 | static void | |
132 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
133 | { | |
134 | int temp; | |
135 | ||
136 | temp = get_absolute_expression (); | |
137 | subseg_set (bss_section, (subsegT) temp); | |
138 | demand_empty_rest_of_line (); | |
139 | } | |
140 | ||
141 | /* The target specific pseudo-ops which we support. */ | |
142 | const pseudo_typeS md_pseudo_table[] = | |
143 | { | |
144 | { "bss", s_bss, 0}, | |
145 | { "word", cons, 4 }, | |
146 | { NULL, NULL, 0 } | |
147 | }; | |
148 | ||
149 | \f | |
150 | void | |
151 | md_begin (void) | |
152 | { | |
153 | /* Initialize the `cgen' interface. */ | |
154 | ||
155 | /* Set the machine number and endian. */ | |
156 | gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach, | |
157 | CGEN_CPU_OPEN_ENDIAN, | |
158 | CGEN_ENDIAN_BIG, | |
e729279b | 159 | CGEN_CPU_OPEN_ISAS, m32c_isa, |
49f58d10 JB |
160 | CGEN_CPU_OPEN_END); |
161 | ||
162 | m32c_cgen_init_asm (gas_cgen_cpu_desc); | |
163 | ||
164 | /* This is a callback from cgen to gas to parse operands. */ | |
165 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); | |
166 | ||
167 | /* Set the ELF flags if desired. */ | |
168 | if (m32c_flags) | |
169 | bfd_set_private_flags (stdoutput, m32c_flags); | |
170 | ||
171 | /* Set the machine type */ | |
172 | bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach); | |
173 | ||
174 | insn_size = 0; | |
175 | } | |
176 | ||
177 | void | |
178 | m32c_md_end (void) | |
179 | { | |
180 | int i, n_nops; | |
181 | ||
182 | /* Pad with nops for objdump. */ | |
183 | n_nops = (32 - ((insn_size) % 32)) / 8; | |
184 | for (i = 1; i <= n_nops; i++) | |
185 | md_assemble ("nop"); | |
186 | } | |
187 | ||
188 | void | |
189 | m32c_start_line_hook (void) | |
190 | { | |
191 | #if 0 /* not necessary....handled in the .cpu file */ | |
192 | char *s = input_line_pointer; | |
193 | char *sg; | |
194 | ||
195 | for (s = input_line_pointer ; s && s[0] != '\n'; s++) | |
196 | { | |
197 | if (s[0] == ':') | |
198 | { | |
199 | /* Remove :g suffix. Squeeze out blanks. */ | |
200 | if (s[1] == 'g') | |
201 | { | |
202 | for (sg = s - 1; sg && sg >= input_line_pointer; sg--) | |
203 | { | |
204 | sg[2] = sg[0]; | |
205 | } | |
206 | sg[1] = ' '; | |
207 | sg[2] = ' '; | |
208 | input_line_pointer += 2; | |
209 | } | |
210 | } | |
211 | } | |
212 | #endif | |
213 | } | |
214 | ||
215 | /* Process [[indirect-operands]] in instruction str. */ | |
216 | ||
217 | static bfd_boolean | |
218 | m32c_indirect_operand (char *str) | |
219 | { | |
220 | char *new_str; | |
221 | char *s; | |
222 | char *ns; | |
223 | int ns_len; | |
224 | char *ns_end; | |
225 | enum indirect_type {none, relative, absolute} ; | |
226 | enum indirect_type indirection [3] = { none, none, none }; | |
227 | int brace_n [3] = { 0, 0, 0 }; | |
228 | int operand; | |
229 | ||
230 | s = str; | |
231 | operand = 1; | |
232 | for (s = str; *s; s++) | |
233 | { | |
234 | if (s[0] == ',') | |
235 | operand = 2; | |
236 | /* [abs] where abs is not a0 or a1 */ | |
237 | if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1')) | |
238 | && (ISBLANK (s[0]) || s[0] == ',')) | |
239 | indirection[operand] = absolute; | |
240 | if (s[0] == ']' && s[1] == ']') | |
241 | indirection[operand] = relative; | |
242 | if (s[0] == '[' && s[1] == '[') | |
243 | indirection[operand] = relative; | |
244 | } | |
245 | ||
246 | if (indirection[1] == none && indirection[2] == none) | |
247 | return FALSE; | |
248 | ||
249 | operand = 1; | |
250 | ns_len = strlen (str); | |
251 | new_str = (char*) xmalloc (ns_len); | |
252 | ns = new_str; | |
253 | ns_end = ns + ns_len; | |
254 | ||
255 | for (s = str; *s; s++) | |
256 | { | |
257 | if (s[0] == ',') | |
258 | operand = 2; | |
259 | ||
260 | if (s[0] == '[' && ! brace_n[operand]) | |
261 | { | |
262 | brace_n[operand] += 1; | |
263 | /* Squeeze [[ to [ if this is an indirect operand. */ | |
264 | if (indirection[operand] != none) | |
265 | continue; | |
266 | } | |
267 | ||
268 | else if (s[0] == '[' && brace_n[operand]) | |
269 | { | |
270 | brace_n[operand] += 1; | |
271 | } | |
272 | else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative) | |
273 | { | |
274 | s += 1; /* skip one ]. */ | |
275 | brace_n[operand] -= 2; /* allow for 2 [. */ | |
276 | } | |
277 | else if (s[0] == ']' && indirection[operand] == absolute) | |
278 | { | |
279 | brace_n[operand] -= 1; | |
280 | continue; /* skip closing ]. */ | |
281 | } | |
282 | else if (s[0] == ']') | |
283 | { | |
284 | brace_n[operand] -= 1; | |
285 | } | |
286 | *ns = s[0]; | |
287 | ns += 1; | |
288 | if (ns >= ns_end) | |
289 | return FALSE; | |
290 | if (s[0] == 0) | |
291 | break; | |
292 | } | |
293 | *ns = '\0'; | |
294 | for (operand = 1; operand <= 2; operand++) | |
295 | if (brace_n[operand]) | |
296 | { | |
297 | fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]); | |
298 | } | |
299 | ||
300 | if (indirection[1] != none && indirection[2] != none) | |
301 | md_assemble ("src-dest-indirect"); | |
302 | else if (indirection[1] != none) | |
303 | md_assemble ("src-indirect"); | |
304 | else if (indirection[2] != none) | |
305 | md_assemble ("dest-indirect"); | |
306 | ||
307 | md_assemble (new_str); | |
308 | free (new_str); | |
309 | return TRUE; | |
310 | } | |
311 | ||
312 | void | |
313 | md_assemble (char * str) | |
314 | { | |
315 | static int last_insn_had_delay_slot = 0; | |
316 | m32c_insn insn; | |
317 | char * errmsg; | |
318 | ||
319 | if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str)) | |
320 | return; | |
321 | ||
322 | /* Initialize GAS's cgen interface for a new instruction. */ | |
323 | gas_cgen_init_parse (); | |
324 | ||
325 | insn.insn = m32c_cgen_assemble_insn | |
326 | (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); | |
327 | ||
328 | if (!insn.insn) | |
329 | { | |
6b73c529 | 330 | as_bad ("%s", errmsg); |
49f58d10 JB |
331 | return; |
332 | } | |
333 | ||
334 | /* Doesn't really matter what we pass for RELAX_P here. */ | |
335 | gas_cgen_finish_insn (insn.insn, insn.buffer, | |
336 | CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); | |
337 | ||
338 | last_insn_had_delay_slot | |
339 | = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); | |
340 | insn_size = CGEN_INSN_BITSIZE(insn.insn); | |
341 | } | |
342 | ||
343 | /* The syntax in the manual says constants begin with '#'. | |
344 | We just ignore it. */ | |
345 | ||
346 | void | |
347 | md_operand (expressionS * exp) | |
348 | { | |
349 | /* In case of a syntax error, escape back to try next syntax combo. */ | |
350 | if (exp->X_op == O_absent) | |
351 | gas_cgen_md_operand (exp); | |
352 | } | |
353 | ||
354 | valueT | |
355 | md_section_align (segT segment, valueT size) | |
356 | { | |
357 | int align = bfd_get_section_alignment (stdoutput, segment); | |
358 | return ((size + (1 << align) - 1) & (-1 << align)); | |
359 | } | |
360 | ||
361 | symbolS * | |
362 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
363 | { | |
364 | return 0; | |
365 | } | |
366 | \f | |
367 | const relax_typeS md_relax_table[] = | |
368 | { | |
369 | /* The fields are: | |
370 | 1) most positive reach of this state, | |
371 | 2) most negative reach of this state, | |
372 | 3) how many bytes this mode will have in the variable part of the frag | |
373 | 4) which index into the table to try if we can't fit into this one. */ | |
374 | ||
375 | /* 0 */ { 0, 0, 0, 0 }, /* unused */ | |
376 | /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */ | |
377 | ||
378 | /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */ | |
379 | /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */ | |
380 | /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */ | |
381 | ||
382 | /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */ | |
383 | /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */ | |
384 | /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */ | |
385 | ||
386 | /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */ | |
387 | /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */ | |
388 | /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */ | |
389 | /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */ | |
390 | ||
391 | /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */ | |
392 | /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */ | |
393 | /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */ | |
394 | ||
395 | /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */ | |
396 | /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */ | |
397 | /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */ | |
d14c4fad DD |
398 | /* 18 */ { 0, 0, 4, 0 }, /* jmp32.a */ |
399 | ||
400 | /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */ | |
401 | /* 20 */ { 0, 0, 4, 0 }, /* jsr16.a */ | |
402 | /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */ | |
403 | /* 22 */ { 0, 0, 4, 0 } /* jsr32.a */ | |
49f58d10 JB |
404 | }; |
405 | ||
406 | enum { | |
407 | M32C_MACRO_JCND16_5_W, | |
408 | M32C_MACRO_JCND16_5_A, | |
409 | M32C_MACRO_JCND16_W, | |
410 | M32C_MACRO_JCND16_A, | |
411 | M32C_MACRO_JCND32_W, | |
412 | M32C_MACRO_JCND32_A, | |
413 | } M32C_Macros; | |
414 | ||
415 | static struct { | |
416 | int insn; | |
417 | int bytes; | |
418 | int insn_for_extern; | |
419 | int pcrel_aim_offset; | |
420 | } subtype_mappings[] = { | |
421 | /* 0 */ { 0, 0, 0, 0 }, | |
422 | /* 1 */ { 0, 0, 0, 0 }, | |
423 | ||
424 | /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 }, | |
425 | /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 }, | |
426 | /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 }, | |
427 | ||
428 | /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 }, | |
429 | /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 }, | |
430 | /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 }, | |
431 | ||
432 | /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 }, | |
433 | /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 }, | |
434 | /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 }, | |
435 | /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 }, | |
436 | ||
437 | /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 }, | |
438 | /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 }, | |
439 | /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 }, | |
440 | ||
441 | /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 }, | |
442 | /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 }, | |
443 | /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 }, | |
d14c4fad DD |
444 | /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 }, |
445 | ||
446 | /* 19 */ { M32C_INSN_JSR16_W, 3, M32C_INSN_JSR16_A, 2 }, | |
447 | /* 20 */ { M32C_INSN_JSR16_A, 4, M32C_INSN_JSR16_A, 0 }, | |
448 | /* 21 */ { M32C_INSN_JSR32_W, 3, M32C_INSN_JSR32_A, 2 }, | |
449 | /* 22 */ { M32C_INSN_JSR32_A, 4, M32C_INSN_JSR32_A, 0 } | |
49f58d10 JB |
450 | }; |
451 | #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0])) | |
452 | ||
453 | void | |
454 | m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state) | |
455 | { | |
456 | symbolS *symbolP = fragP->fr_symbol; | |
457 | if (symbolP && !S_IS_DEFINED (symbolP)) | |
458 | *aim = 0; | |
459 | /* Adjust for m32c pcrel not being relative to the next opcode. */ | |
460 | *aim += subtype_mappings[this_state].pcrel_aim_offset; | |
461 | } | |
462 | ||
463 | static int | |
464 | insn_to_subtype (int insn) | |
465 | { | |
466 | unsigned int i; | |
467 | for (i=0; i<NUM_MAPPINGS; i++) | |
468 | if (insn == subtype_mappings[i].insn) | |
469 | { | |
470 | /*printf("mapping %d used\n", i);*/ | |
471 | return i; | |
472 | } | |
473 | abort (); | |
474 | } | |
475 | ||
476 | /* Return an initial guess of the length by which a fragment must grow to | |
477 | hold a branch to reach its destination. | |
478 | Also updates fr_type/fr_subtype as necessary. | |
479 | ||
480 | Called just before doing relaxation. | |
481 | Any symbol that is now undefined will not become defined. | |
482 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
483 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
484 | Although it may not be explicit in the frag, pretend fr_var starts with a | |
485 | 0 value. */ | |
486 | ||
487 | int | |
488 | md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED) | |
489 | { | |
490 | int where = fragP->fr_opcode - fragP->fr_literal; | |
491 | ||
492 | if (fragP->fr_subtype == 1) | |
493 | fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num); | |
494 | ||
495 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) | |
496 | { | |
497 | int new_insn; | |
498 | ||
499 | new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern; | |
500 | fragP->fr_subtype = insn_to_subtype (new_insn); | |
501 | } | |
502 | ||
503 | if (fragP->fr_cgen.insn->base | |
504 | && fragP->fr_cgen.insn->base->num | |
505 | != subtype_mappings[fragP->fr_subtype].insn | |
506 | && subtype_mappings[fragP->fr_subtype].insn > 0) | |
507 | { | |
508 | int new_insn= subtype_mappings[fragP->fr_subtype].insn; | |
509 | if (new_insn >= 0) | |
510 | { | |
511 | fragP->fr_cgen.insn = (fragP->fr_cgen.insn | |
512 | - fragP->fr_cgen.insn->base->num | |
513 | + new_insn); | |
514 | } | |
515 | } | |
516 | ||
517 | return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where); | |
518 | } | |
519 | ||
520 | /* *fragP has been relaxed to its final size, and now needs to have | |
521 | the bytes inside it modified to conform to the new size. | |
522 | ||
523 | Called after relaxation is finished. | |
524 | fragP->fr_type == rs_machine_dependent. | |
525 | fragP->fr_subtype is the subtype of what the address relaxed to. */ | |
526 | ||
527 | static int | |
528 | target_address_for (fragS *frag) | |
529 | { | |
530 | int rv = frag->fr_offset; | |
531 | symbolS *sym = frag->fr_symbol; | |
532 | ||
533 | if (sym) | |
534 | rv += S_GET_VALUE (sym); | |
535 | ||
536 | /*printf("target_address_for returns %d\n", rv);*/ | |
537 | return rv; | |
538 | } | |
539 | ||
540 | void | |
541 | md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, | |
542 | segT sec ATTRIBUTE_UNUSED, | |
543 | fragS * fragP ATTRIBUTE_UNUSED) | |
544 | { | |
545 | int addend; | |
546 | int operand; | |
547 | int new_insn; | |
548 | int where = fragP->fr_opcode - fragP->fr_literal; | |
549 | unsigned char *op = (unsigned char *)fragP->fr_opcode; | |
550 | ||
551 | addend = target_address_for (fragP) - (fragP->fr_address + where); | |
552 | new_insn = subtype_mappings[fragP->fr_subtype].insn; | |
553 | ||
554 | fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes; | |
555 | ||
556 | switch (subtype_mappings[fragP->fr_subtype].insn) | |
557 | { | |
558 | case M32C_INSN_JCND16_5: | |
559 | op[1] = addend - 1; | |
560 | operand = M32C_OPERAND_LAB_8_8; | |
561 | break; | |
562 | ||
563 | case -M32C_MACRO_JCND16_5_W: | |
564 | op[0] ^= 0x04; | |
565 | op[1] = 4; | |
566 | op[2] = 0xf4; | |
567 | op[3] = addend - 3; | |
568 | op[4] = (addend - 3) >> 8; | |
569 | operand = M32C_OPERAND_LAB_8_16; | |
570 | where += 2; | |
571 | new_insn = M32C_INSN_JMP16_W; | |
572 | break; | |
573 | ||
574 | case -M32C_MACRO_JCND16_5_A: | |
575 | op[0] ^= 0x04; | |
576 | op[1] = 5; | |
577 | op[2] = 0xfc; | |
578 | operand = M32C_OPERAND_LAB_8_24; | |
579 | where += 2; | |
580 | new_insn = M32C_INSN_JMP16_A; | |
581 | break; | |
582 | ||
583 | ||
584 | case M32C_INSN_JCND16: | |
585 | op[2] = addend - 2; | |
586 | operand = M32C_OPERAND_LAB_16_8; | |
587 | break; | |
588 | ||
589 | case -M32C_MACRO_JCND16_W: | |
590 | op[1] ^= 0x04; | |
591 | op[2] = 4; | |
592 | op[3] = 0xf4; | |
593 | op[4] = addend - 4; | |
594 | op[5] = (addend - 4) >> 8; | |
595 | operand = M32C_OPERAND_LAB_8_16; | |
596 | where += 3; | |
597 | new_insn = M32C_INSN_JMP16_W; | |
598 | break; | |
599 | ||
600 | case -M32C_MACRO_JCND16_A: | |
601 | op[1] ^= 0x04; | |
602 | op[2] = 5; | |
603 | op[3] = 0xfc; | |
604 | operand = M32C_OPERAND_LAB_8_24; | |
605 | where += 3; | |
606 | new_insn = M32C_INSN_JMP16_A; | |
607 | break; | |
608 | ||
609 | case M32C_INSN_JMP16_S: | |
610 | op[0] = 0x60 | ((addend-2) & 0x07); | |
611 | operand = M32C_OPERAND_LAB_5_3; | |
612 | break; | |
613 | ||
614 | case M32C_INSN_JMP16_B: | |
615 | op[0] = 0xfe; | |
616 | op[1] = addend - 1; | |
617 | operand = M32C_OPERAND_LAB_8_8; | |
618 | break; | |
619 | ||
620 | case M32C_INSN_JMP16_W: | |
621 | op[0] = 0xf4; | |
622 | op[1] = addend - 1; | |
623 | op[2] = (addend - 1) >> 8; | |
624 | operand = M32C_OPERAND_LAB_8_16; | |
625 | break; | |
626 | ||
627 | case M32C_INSN_JMP16_A: | |
628 | op[0] = 0xfc; | |
629 | op[1] = 0; | |
630 | op[2] = 0; | |
631 | op[3] = 0; | |
632 | operand = M32C_OPERAND_LAB_8_24; | |
633 | break; | |
634 | ||
635 | case M32C_INSN_JCND32: | |
636 | op[1] = addend - 1; | |
637 | operand = M32C_OPERAND_LAB_8_8; | |
638 | break; | |
639 | ||
640 | case -M32C_MACRO_JCND32_W: | |
641 | op[0] ^= 0x40; | |
642 | op[1] = 4; | |
643 | op[2] = 0xce; | |
644 | op[3] = addend - 3; | |
645 | op[4] = (addend - 3) >> 8; | |
646 | operand = M32C_OPERAND_LAB_8_16; | |
647 | where += 2; | |
648 | new_insn = M32C_INSN_JMP32_W; | |
649 | break; | |
650 | ||
651 | case -M32C_MACRO_JCND32_A: | |
652 | op[0] ^= 0x40; | |
653 | op[1] = 5; | |
654 | op[2] = 0xcc; | |
655 | operand = M32C_OPERAND_LAB_8_24; | |
656 | where += 2; | |
657 | new_insn = M32C_INSN_JMP32_A; | |
658 | break; | |
659 | ||
660 | ||
661 | ||
662 | case M32C_INSN_JMP32_S: | |
663 | addend = ((addend-2) & 0x07); | |
664 | op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30); | |
665 | operand = M32C_OPERAND_LAB32_JMP_S; | |
666 | break; | |
667 | ||
668 | case M32C_INSN_JMP32_B: | |
669 | op[0] = 0xbb; | |
670 | op[1] = addend - 1; | |
671 | operand = M32C_OPERAND_LAB_8_8; | |
672 | break; | |
673 | ||
674 | case M32C_INSN_JMP32_W: | |
675 | op[0] = 0xce; | |
676 | op[1] = addend - 1; | |
677 | op[2] = (addend - 1) >> 8; | |
678 | operand = M32C_OPERAND_LAB_8_16; | |
679 | break; | |
680 | ||
681 | case M32C_INSN_JMP32_A: | |
682 | op[0] = 0xcc; | |
683 | op[1] = 0; | |
684 | op[2] = 0; | |
685 | op[3] = 0; | |
686 | operand = M32C_OPERAND_LAB_8_24; | |
687 | break; | |
688 | ||
689 | ||
d14c4fad DD |
690 | case M32C_INSN_JSR16_W: |
691 | op[0] = 0xf5; | |
692 | op[1] = addend - 1; | |
693 | op[2] = (addend - 1) >> 8; | |
694 | operand = M32C_OPERAND_LAB_8_16; | |
695 | break; | |
696 | ||
697 | case M32C_INSN_JSR16_A: | |
698 | op[0] = 0xfd; | |
699 | op[1] = 0; | |
700 | op[2] = 0; | |
701 | op[3] = 0; | |
702 | operand = M32C_OPERAND_LAB_8_24; | |
703 | break; | |
704 | ||
705 | case M32C_INSN_JSR32_W: | |
706 | op[0] = 0xcf; | |
707 | op[1] = addend - 1; | |
708 | op[2] = (addend - 1) >> 8; | |
709 | operand = M32C_OPERAND_LAB_8_16; | |
710 | break; | |
711 | ||
712 | case M32C_INSN_JSR32_A: | |
713 | op[0] = 0xcd; | |
714 | op[1] = 0; | |
715 | op[2] = 0; | |
716 | op[3] = 0; | |
717 | operand = M32C_OPERAND_LAB_8_24; | |
718 | break; | |
719 | ||
720 | ||
721 | ||
49f58d10 JB |
722 | default: |
723 | printf("\nHey! Need more opcode converters! missing: %d %s\n\n", | |
724 | fragP->fr_subtype, | |
725 | fragP->fr_cgen.insn->base->name); | |
726 | abort(); | |
727 | } | |
728 | ||
729 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec | |
730 | || operand == M32C_OPERAND_LAB_8_24) | |
731 | { | |
732 | assert (fragP->fr_cgen.insn != 0); | |
733 | gas_cgen_record_fixup (fragP, | |
734 | where, | |
735 | fragP->fr_cgen.insn, | |
736 | (fragP->fr_fix - where) * 8, | |
737 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, | |
738 | operand), | |
739 | fragP->fr_cgen.opinfo, | |
740 | fragP->fr_symbol, fragP->fr_offset); | |
741 | } | |
742 | } | |
743 | \f | |
744 | /* Functions concerning relocs. */ | |
745 | ||
746 | /* The location from which a PC relative jump should be calculated, | |
747 | given a PC relative reloc. */ | |
748 | ||
749 | long | |
750 | md_pcrel_from_section (fixS * fixP, segT sec) | |
751 | { | |
752 | if (fixP->fx_addsy != (symbolS *) NULL | |
753 | && (! S_IS_DEFINED (fixP->fx_addsy) | |
754 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) | |
755 | /* The symbol is undefined (or is defined but not in this section). | |
756 | Let the linker figure it out. */ | |
757 | return 0; | |
758 | ||
759 | return (fixP->fx_frag->fr_address + fixP->fx_where); | |
760 | } | |
761 | ||
762 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. | |
763 | Returns BFD_RELOC_NONE if no reloc type can be found. | |
764 | *FIXP may be modified if desired. */ | |
765 | ||
766 | bfd_reloc_code_real_type | |
767 | md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, | |
768 | const CGEN_OPERAND * operand, | |
769 | fixS * fixP ATTRIBUTE_UNUSED) | |
770 | { | |
771 | static const struct op_reloc { | |
772 | /* A CGEN operand type that can be a relocatable expression. */ | |
773 | CGEN_OPERAND_TYPE operand; | |
774 | ||
775 | /* The appropriate BFD reloc type to use for that. */ | |
776 | bfd_reloc_code_real_type reloc; | |
777 | ||
778 | /* The offset from the start of the instruction to the field to be | |
779 | relocated, in bytes. */ | |
780 | int offset; | |
781 | } op_reloc_table[] = { | |
782 | ||
cab0a0db DD |
783 | /* PC-REL relocs for 8-bit fields. */ |
784 | { M32C_OPERAND_LAB_16_8, BFD_RELOC_8_PCREL, 2 }, | |
785 | { M32C_OPERAND_LAB_24_8, BFD_RELOC_8_PCREL, 3 }, | |
786 | { M32C_OPERAND_LAB_32_8, BFD_RELOC_8_PCREL, 4 }, | |
787 | { M32C_OPERAND_LAB_40_8, BFD_RELOC_8_PCREL, 5 }, | |
788 | ||
fd54057a DD |
789 | /* Absolute relocs for 8-bit fields. */ |
790 | { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 }, | |
791 | { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 }, | |
792 | { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 }, | |
793 | { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 }, | |
794 | { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 }, | |
795 | { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 }, | |
796 | { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 }, | |
797 | { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 }, | |
798 | { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 }, | |
799 | { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 }, | |
800 | { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 }, | |
801 | { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 }, | |
802 | { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 }, | |
803 | { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 }, | |
804 | { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 }, | |
805 | { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 }, | |
806 | { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 }, | |
807 | { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 }, | |
808 | { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 }, | |
6b73c529 DD |
809 | { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, BFD_RELOC_8, 2 }, |
810 | { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, BFD_RELOC_8, 2 }, | |
811 | { M32C_OPERAND_BITBASE32_24_S11_PREFIXED, BFD_RELOC_8, 3 }, | |
812 | { M32C_OPERAND_BITBASE32_24_U11_PREFIXED, BFD_RELOC_8, 3 }, | |
fd54057a | 813 | |
49f58d10 | 814 | /* Absolute relocs for 16-bit fields. */ |
6b73c529 | 815 | { M32C_OPERAND_IMM_8_HI, BFD_RELOC_16, 1 }, |
49f58d10 JB |
816 | { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 }, |
817 | { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 }, | |
818 | { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 }, | |
cab0a0db DD |
819 | { M32C_OPERAND_IMM_40_HI, BFD_RELOC_16, 5 }, |
820 | { M32C_OPERAND_IMM_48_HI, BFD_RELOC_16, 6 }, | |
821 | { M32C_OPERAND_IMM_56_HI, BFD_RELOC_16, 7 }, | |
822 | { M32C_OPERAND_IMM_64_HI, BFD_RELOC_16, 8 }, | |
49f58d10 JB |
823 | { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 }, |
824 | { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 }, | |
825 | { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 }, | |
826 | { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 }, | |
827 | { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 }, | |
828 | { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 }, | |
829 | { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 }, | |
830 | { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 }, | |
cab0a0db DD |
831 | { M32C_OPERAND_DSP_40_U16, BFD_RELOC_16, 5 }, |
832 | { M32C_OPERAND_DSP_48_U16, BFD_RELOC_16, 6 }, | |
6b73c529 DD |
833 | { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, BFD_RELOC_16, 2 }, |
834 | { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, BFD_RELOC_16, 2 }, | |
835 | { M32C_OPERAND_BITBASE32_24_S19_PREFIXED, BFD_RELOC_16, 3 }, | |
836 | { M32C_OPERAND_BITBASE32_24_U19_PREFIXED, BFD_RELOC_16, 3 }, | |
49f58d10 JB |
837 | |
838 | /* Absolute relocs for 24-bit fields. */ | |
839 | { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 }, | |
6b73c529 | 840 | { M32C_OPERAND_DSP_8_S24, BFD_RELOC_24, 1 }, |
cab0a0db | 841 | { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 }, |
49f58d10 JB |
842 | { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 }, |
843 | { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 }, | |
844 | { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 }, | |
845 | { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 }, | |
cab0a0db DD |
846 | { M32C_OPERAND_DSP_48_U24, BFD_RELOC_24, 6 }, |
847 | { M32C_OPERAND_DSP_16_U20, BFD_RELOC_24, 2 }, | |
848 | { M32C_OPERAND_DSP_24_U20, BFD_RELOC_24, 3 }, | |
849 | { M32C_OPERAND_DSP_32_U20, BFD_RELOC_24, 4 }, | |
6b73c529 DD |
850 | { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, BFD_RELOC_24, 2 }, |
851 | { M32C_OPERAND_BITBASE32_24_U27_PREFIXED, BFD_RELOC_24, 3 }, | |
49f58d10 JB |
852 | |
853 | /* Absolute relocs for 32-bit fields. */ | |
854 | { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 }, | |
855 | { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 }, | |
856 | { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 }, | |
857 | { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 }, | |
858 | ||
859 | }; | |
860 | ||
861 | int i; | |
862 | ||
863 | for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; ) | |
864 | { | |
865 | const struct op_reloc *or = &op_reloc_table[i]; | |
866 | ||
867 | if (or->operand == operand->type) | |
868 | { | |
869 | fixP->fx_where += or->offset; | |
870 | fixP->fx_size -= or->offset; | |
fd54057a DD |
871 | |
872 | if (fixP->fx_cgen.opinfo | |
873 | && fixP->fx_cgen.opinfo != BFD_RELOC_NONE) | |
874 | return fixP->fx_cgen.opinfo; | |
875 | ||
49f58d10 JB |
876 | return or->reloc; |
877 | } | |
878 | } | |
879 | ||
880 | fprintf | |
881 | (stderr, | |
cab0a0db DD |
882 | "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n", |
883 | operand->name); | |
49f58d10 JB |
884 | |
885 | return BFD_RELOC_NONE; | |
886 | } | |
887 | ||
888 | /* See whether we need to force a relocation into the output file. | |
889 | This is used to force out switch and PC relative relocations when | |
890 | relaxing. */ | |
891 | ||
892 | int | |
893 | m32c_force_relocation (fixS * fixp) | |
894 | { | |
895 | int reloc = fixp->fx_r_type; | |
896 | ||
897 | if (reloc > (int)BFD_RELOC_UNUSED) | |
898 | { | |
899 | reloc -= (int)BFD_RELOC_UNUSED; | |
900 | switch (reloc) | |
901 | { | |
902 | case M32C_OPERAND_DSP_32_S16: | |
903 | case M32C_OPERAND_DSP_32_U16: | |
904 | case M32C_OPERAND_IMM_32_HI: | |
905 | case M32C_OPERAND_DSP_16_S16: | |
906 | case M32C_OPERAND_DSP_16_U16: | |
907 | case M32C_OPERAND_IMM_16_HI: | |
908 | case M32C_OPERAND_DSP_24_S16: | |
909 | case M32C_OPERAND_DSP_24_U16: | |
910 | case M32C_OPERAND_IMM_24_HI: | |
911 | return 1; | |
912 | } | |
913 | } | |
914 | else | |
915 | { | |
916 | if (fixp->fx_r_type == BFD_RELOC_16) | |
917 | return 1; | |
918 | } | |
919 | ||
920 | return generic_force_reloc (fixp); | |
921 | } | |
922 | \f | |
923 | /* Write a value out to the object file, using the appropriate endianness. */ | |
924 | ||
925 | void | |
926 | md_number_to_chars (char * buf, valueT val, int n) | |
927 | { | |
928 | number_to_chars_littleendian (buf, val, n); | |
929 | } | |
930 | ||
931 | /* Turn a string in input_line_pointer into a floating point constant of type | |
932 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
933 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. */ | |
934 | ||
935 | /* Equal to MAX_PRECISION in atof-ieee.c. */ | |
936 | #define MAX_LITTLENUMS 6 | |
937 | ||
938 | char * | |
939 | md_atof (int type, char * litP, int * sizeP) | |
940 | { | |
941 | int i; | |
942 | int prec; | |
943 | LITTLENUM_TYPE words [MAX_LITTLENUMS]; | |
944 | char * t; | |
945 | ||
946 | switch (type) | |
947 | { | |
948 | case 'f': | |
949 | case 'F': | |
950 | case 's': | |
951 | case 'S': | |
952 | prec = 2; | |
953 | break; | |
954 | ||
955 | case 'd': | |
956 | case 'D': | |
957 | case 'r': | |
958 | case 'R': | |
959 | prec = 4; | |
960 | break; | |
961 | ||
962 | /* FIXME: Some targets allow other format chars for bigger sizes here. */ | |
963 | ||
964 | default: | |
965 | * sizeP = 0; | |
966 | return _("Bad call to md_atof()"); | |
967 | } | |
968 | ||
969 | t = atof_ieee (input_line_pointer, type, words); | |
970 | if (t) | |
971 | input_line_pointer = t; | |
972 | * sizeP = prec * sizeof (LITTLENUM_TYPE); | |
973 | ||
974 | for (i = 0; i < prec; i++) | |
975 | { | |
976 | md_number_to_chars (litP, (valueT) words[i], | |
977 | sizeof (LITTLENUM_TYPE)); | |
978 | litP += sizeof (LITTLENUM_TYPE); | |
979 | } | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
984 | bfd_boolean | |
985 | m32c_fix_adjustable (fixS * fixP) | |
986 | { | |
987 | int reloc; | |
988 | if (fixP->fx_addsy == NULL) | |
989 | return 1; | |
990 | ||
991 | /* We need the symbol name for the VTABLE entries. */ | |
992 | reloc = fixP->fx_r_type; | |
993 | if (reloc > (int)BFD_RELOC_UNUSED) | |
994 | { | |
995 | reloc -= (int)BFD_RELOC_UNUSED; | |
996 | switch (reloc) | |
997 | { | |
998 | case M32C_OPERAND_DSP_32_S16: | |
999 | case M32C_OPERAND_DSP_32_U16: | |
1000 | case M32C_OPERAND_IMM_32_HI: | |
1001 | case M32C_OPERAND_DSP_16_S16: | |
1002 | case M32C_OPERAND_DSP_16_U16: | |
1003 | case M32C_OPERAND_IMM_16_HI: | |
1004 | case M32C_OPERAND_DSP_24_S16: | |
1005 | case M32C_OPERAND_DSP_24_U16: | |
1006 | case M32C_OPERAND_IMM_24_HI: | |
1007 | return 0; | |
1008 | } | |
1009 | } | |
1010 | else | |
1011 | { | |
1012 | if (fixP->fx_r_type == BFD_RELOC_16) | |
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | /* Do not adjust relocations involving symbols in merged sections. | |
1017 | ||
1018 | A reloc patching in the value of some symbol S plus some addend A | |
1019 | can be produced in different ways: | |
1020 | ||
1021 | 1) It might simply be a reference to the data at S + A. Clearly, | |
1022 | if linker merging shift that data around, the value patched in | |
1023 | by the reloc needs to be adjusted accordingly. | |
1024 | ||
1025 | 2) Or, it might be a reference to S, with A added in as a constant | |
1026 | bias. For example, given code like this: | |
1027 | ||
1028 | static int S[100]; | |
1029 | ||
1030 | ... S[i - 8] ... | |
1031 | ||
1032 | it would be reasonable for the compiler to rearrange the array | |
1033 | reference to something like: | |
1034 | ||
1035 | ... (S-8)[i] ... | |
1036 | ||
1037 | and emit assembly code that refers to S - (8 * sizeof (int)), | |
1038 | so the subtraction is done entirely at compile-time. In this | |
1039 | case, the reloc's addend A would be -(8 * sizeof (int)), and | |
1040 | shifting around code or data at S + A should not affect the | |
1041 | reloc: the reloc isn't referring to that code or data at all. | |
1042 | ||
1043 | The linker has no way of knowing which case it has in hand. So, | |
1044 | to disambiguate, we have the linker always treat reloc addends as | |
1045 | in case 2): they're constants that should be simply added to the | |
1046 | symbol value, just like the reloc says. And we express case 1) | |
1047 | in different way: we have the compiler place a label at the real | |
1048 | target, and reference that label with an addend of zero. (The | |
1049 | compiler is unlikely to reference code using a label plus an | |
1050 | offset anyway, since it doesn't know the sizes of the | |
1051 | instructions.) | |
1052 | ||
1053 | The simplification being done by gas/write.c:adjust_reloc_syms, | |
1054 | however, turns the explicit-label usage into the label-plus- | |
1055 | offset usage, re-introducing the ambiguity the compiler avoided. | |
1056 | So we need to disable that simplification for symbols referring | |
1057 | to merged data. | |
1058 | ||
1059 | This only affects object size a little bit. */ | |
1060 | if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) | |
1061 | return 0; | |
1062 | ||
1063 | return 1; | |
1064 | } | |
1065 | ||
1066 | /* Worker function for m32c_is_colon_insn(). */ | |
1067 | static char restore_colon PARAMS ((int)); | |
1068 | ||
1069 | static char | |
1070 | restore_colon (int advance_i_l_p_by) | |
1071 | { | |
1072 | char c; | |
1073 | ||
1074 | /* Restore the colon, and advance input_line_pointer to | |
1075 | the end of the new symbol. */ | |
1076 | * input_line_pointer = ':'; | |
1077 | input_line_pointer += advance_i_l_p_by; | |
1078 | c = * input_line_pointer; | |
1079 | * input_line_pointer = 0; | |
1080 | ||
1081 | return c; | |
1082 | } | |
1083 | ||
1084 | /* Determines if the symbol starting at START and ending in | |
1085 | a colon that was at the location pointed to by INPUT_LINE_POINTER | |
1086 | (but which has now been replaced bu a NUL) is in fact an | |
1087 | :Z, :S, :Q, or :G suffix. | |
1088 | If it is, then it restores the colon, advances INPUT_LINE_POINTER | |
1089 | to the real end of the instruction/symbol, and returns the character | |
1090 | that really terminated the symbol. Otherwise it returns 0. */ | |
1091 | char | |
1092 | m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED) | |
1093 | { | |
1094 | char * i_l_p = input_line_pointer; | |
1095 | ||
1096 | /* Check to see if the text following the colon is 'G' */ | |
1097 | if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) | |
1098 | return restore_colon (2); | |
1099 | ||
1100 | /* Check to see if the text following the colon is 'Q' */ | |
1101 | if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) | |
1102 | return restore_colon (2); | |
1103 | ||
1104 | /* Check to see if the text following the colon is 'S' */ | |
1105 | if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) | |
1106 | return restore_colon (2); | |
1107 | ||
1108 | /* Check to see if the text following the colon is 'Z' */ | |
1109 | if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) | |
1110 | return restore_colon (2); | |
1111 | ||
1112 | return 0; | |
1113 | } |