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* armemu.c (handle_v6_insn): Fix typo in sign extension test of the sext and sxtah...
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
266abb8f 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
2da12c60
NS		 155static const enum m68k_register m68000_ctrl[] = { 0 };
156static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 157 SFC, DFC, USP, VBR,
158 0
159};
2da12c60 160static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
2da12c60 164static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
2da12c60 169static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
2da12c60 174static const enum m68k_register mcf_ctrl[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 176 RAMBAR0, RAMBAR1, MBAR,
177 0
178};
2da12c60 179static const enum m68k_register mcf5208_ctrl[] = {
266abb8f
NS		 180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182};
2da12c60 183static const enum m68k_register mcf5213_ctrl[] = {
266abb8f
NS		 184 VBR, RAMBAR, FLASHBAR,
185 0
186};
2da12c60
NS		 187static const enum m68k_register mcf5216_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
266abb8f
NS		 189 0
190};
2da12c60
NS		 191static const enum m68k_register mcf5235_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, RAMBAR,
e80e0390
NC		 193 0
194};
2da12c60
NS		 195static const enum m68k_register mcf5249_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
3e602632
NC		 197 0
198};
2da12c60
NS		 199static const enum m68k_register mcf5250_ctrl[] = {
200 VBR,
201 0
202};
203static const enum m68k_register mcf5271_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
205 0
206};
207static const enum m68k_register mcf5272_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
209 0
210};
211static const enum m68k_register mcf5275_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR,
213 0
214};
215static const enum m68k_register mcf5282_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
217 0
218};
219static const enum m68k_register mcf5329_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR,
221 0
222};
223static const enum m68k_register mcf5373_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226};
227static const enum m68k_register mcfv4e_ctrl[] = {
3e602632
NC		 228 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
229 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
230 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
231 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
232 0
233};
f7ec513b
KH		 234static const enum m68k_register fido_ctrl[] = {
235 SFC, DFC, USP, VBR, CAC, MBB,
236 0
237};
2da12c60 238#define cpu32_ctrl m68010_ctrl
252b5132
RH		 239
240static const enum m68k_register *control_regs;
241
36759679 242/* Internal form of a 68020 instruction. */
252b5132
RH		 243struct m68k_it
244{
245 const char *error;
36759679 246 const char *args; /* List of opcode info. */
252b5132
RH		 247 int numargs;
248
36759679 249 int numo; /* Number of shorts in opcode. */
252b5132
RH		 250 short opcode[11];
251
252 struct m68k_op operands[6];
253
36759679 254 int nexp; /* Number of exprs in use. */
252b5132
RH		 255 struct m68k_exp exprs[4];
256
36759679 257 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 258 struct
259 {
36759679 260 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 261 symbolS *fadd;
262 offsetT foff;
263 int fragty;
264 }
265 fragb[4];
266
36759679 267 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 268 struct
269 {
270 int n;
271 expressionS exp;
272 char wid;
273 char pcrel;
274 /* In a pc relative address the difference between the address
275 of the offset and the address that the offset is relative
276 to. This depends on the addressing mode. Basically this
277 is the value to put in the offset field to address the
278 first byte of the offset, without regarding the special
279 significance of some values (in the branch instruction, for
280 example). */
281 int pcrel_fix;
282#ifdef OBJ_ELF
283 /* Whether this expression needs special pic relocation, and if
284 so, which. */
285 enum pic_relocation pic_reloc;
286#endif
287 }
36759679 288 reloc[5]; /* Five is enough??? */
252b5132
RH		 289};
290
9840d27e 291#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 292#define float_of_arch(x) ((x) & mfloat)
293#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 294#define arch_coldfire_p(x) ((x) & mcfisa_a)
295#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 296
36759679 297/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 298#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 299
36759679 300static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 301
302#define op(ex) ((ex)->exp.X_op)
303#define adds(ex) ((ex)->exp.X_add_symbol)
304#define subs(ex) ((ex)->exp.X_op_symbol)
305#define offs(ex) ((ex)->exp.X_add_number)
306
36759679 307/* Macros for adding things to the m68k_it struct. */
31302357 308#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 309
36759679
NC		 310/* Like addword, but goes BEFORE general operands. */
311
252b5132 312static void
31302357 313insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 314{
315 int z;
07726851 316 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 317 the_ins.opcode[z] = the_ins.opcode[z - 1];
318 for (z = 0; z < the_ins.nrel; z++)
319 the_ins.reloc[z].n += 2;
252b5132
RH		 320 for (z = 0; z < the_ins.nfrag; z++)
321 the_ins.fragb[z].fragoff++;
8a104df9 322 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 323 the_ins.numo++;
324}
325
326/* The numo+1 kludge is so we can hit the low order byte of the prev word.
327 Blecch. */
328static void
31302357 329add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 330{
31302357
AS		 331 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
332 ? the_ins.numo * 2 - 1
333 : (width == 'b'
334 ? the_ins.numo * 2 + 1
335 : the_ins.numo * 2));
252b5132
RH		 336 the_ins.reloc[the_ins.nrel].exp = exp->exp;
337 the_ins.reloc[the_ins.nrel].wid = width;
338 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
339#ifdef OBJ_ELF
340 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
341#endif
342 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
343}
344
345/* Cause an extra frag to be generated here, inserting up to 10 bytes
346 (that value is chosen in the frag_var call in md_assemble). TYPE
347 is the subtype of the frag to be generated; its primary type is
348 rs_machine_dependent.
349
350 The TYPE parameter is also used by md_convert_frag_1 and
351 md_estimate_size_before_relax. The appropriate type of fixup will
352 be emitted by md_convert_frag_1.
353
354 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
355static void
31302357 356add_frag (symbolS *add, offsetT off, int type)
252b5132 357{
8a104df9
KH		 358 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
359 the_ins.fragb[the_ins.nfrag].fadd = add;
360 the_ins.fragb[the_ins.nfrag].foff = off;
361 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 362}
363
364#define isvar(ex) \
365 (op (ex) != O_constant && op (ex) != O_big)
366
31302357
AS		 367static char *crack_operand (char *str, struct m68k_op *opP);
368static int get_num (struct m68k_exp *exp, int ok);
369static int reverse_16_bits (int in);
370static int reverse_8_bits (int in);
371static void install_gen_operand (int mode, int val);
372static void install_operand (int mode, int val);
373static void s_bss (int);
374static void s_data1 (int);
375static void s_data2 (int);
376static void s_even (int);
377static void s_proc (int);
378static void s_chip (int);
379static void s_fopt (int);
380static void s_opt (int);
381static void s_reg (int);
382static void s_restore (int);
383static void s_save (int);
384static void s_mri_if (int);
385static void s_mri_else (int);
386static void s_mri_endi (int);
387static void s_mri_break (int);
388static void s_mri_next (int);
389static void s_mri_for (int);
390static void s_mri_endf (int);
391static void s_mri_repeat (int);
392static void s_mri_until (int);
393static void s_mri_while (int);
394static void s_mri_endw (int);
266abb8f
NS		 395static void s_m68k_cpu (int);
396static void s_m68k_arch (int);
397
398struct m68k_cpu
399{
400 unsigned long arch; /* Architecture features. */
2da12c60 401 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 402 const char *name; /* Name */
0b2e31dc
NS		 403 int alias; /* Alias for a cannonical name. If 1, then
404 succeeds canonical name, if -1 then
405 succeeds canonical name, if <-1 ||>1 this is a
406 deprecated name, and the next/previous name
407 should be used. */
266abb8f 408};
252b5132 409
266abb8f
NS		 410/* We hold flags for features explicitly enabled and explicitly
411 disabled. */
252b5132 412static int current_architecture;
266abb8f 413static int not_current_architecture;
266abb8f
NS		 414static const struct m68k_cpu *selected_arch;
415static const struct m68k_cpu *selected_cpu;
416static int initialized;
252b5132 417
266abb8f
NS		 418/* Architecture models. */
419static const struct m68k_cpu m68k_archs[] =
420{
2da12c60
NS		 421 {m68000, m68000_ctrl, "68000", 0},
422 {m68010, m68010_ctrl, "68010", 0},
423 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
424 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
425 {m68040, m68040_ctrl, "68040", 0},
426 {m68060, m68060_ctrl, "68060", 0},
427 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 428 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 429 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
430 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
431 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
432 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
433 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 434 {0,0,NULL, 0}
435};
252b5132 436
0b2e31dc
NS		 437/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
438 for either. */
266abb8f
NS		 439static const struct m68k_cpu m68k_extensions[] =
440{
2da12c60
NS		 441 {m68851, NULL, "68851", -1},
442 {m68881, NULL, "68881", -1},
443 {m68881, NULL, "68882", -1},
0b2e31dc 444
2da12c60 445 {cfloat|m68881, NULL, "float", 0},
266abb8f 446
2da12c60
NS		 447 {mcfhwdiv, NULL, "div", 1},
448 {mcfusp, NULL, "usp", 1},
449 {mcfmac, NULL, "mac", 1},
450 {mcfemac, NULL, "emac", 1},
266abb8f 451
2da12c60 452 {0,NULL,NULL, 0}
266abb8f
NS		 453};
454
455/* Processor list */
456static const struct m68k_cpu m68k_cpus[] =
457{
2da12c60
NS		 458 {m68000, m68000_ctrl, "68000", 0},
459 {m68000, m68000_ctrl, "68ec000", 1},
460 {m68000, m68000_ctrl, "68hc000", 1},
461 {m68000, m68000_ctrl, "68hc001", 1},
462 {m68000, m68000_ctrl, "68008", 1},
463 {m68000, m68000_ctrl, "68302", 1},
464 {m68000, m68000_ctrl, "68306", 1},
465 {m68000, m68000_ctrl, "68307", 1},
466 {m68000, m68000_ctrl, "68322", 1},
467 {m68000, m68000_ctrl, "68356", 1},
468 {m68010, m68010_ctrl, "68010", 0},
469 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
470 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
471 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
472 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
473 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
474 {m68040, m68040_ctrl, "68040", 0},
475 {m68040, m68040_ctrl, "68ec040", 1},
476 {m68060, m68060_ctrl, "68060", 0},
477 {m68060, m68060_ctrl, "68ec060", 1},
478
479 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
480 {cpu32|m68881, cpu32_ctrl, "68330", 1},
481 {cpu32|m68881, cpu32_ctrl, "68331", 1},
482 {cpu32|m68881, cpu32_ctrl, "68332", 1},
483 {cpu32|m68881, cpu32_ctrl, "68333", 1},
484 {cpu32|m68881, cpu32_ctrl, "68334", 1},
485 {cpu32|m68881, cpu32_ctrl, "68336", 1},
486 {cpu32|m68881, cpu32_ctrl, "68340", 1},
487 {cpu32|m68881, cpu32_ctrl, "68341", 1},
488 {cpu32|m68881, cpu32_ctrl, "68349", 1},
489 {cpu32|m68881, cpu32_ctrl, "68360", 1},
490
491 {mcfisa_a, mcf_ctrl, "5200", 0},
492 {mcfisa_a, mcf_ctrl, "5202", 1},
493 {mcfisa_a, mcf_ctrl, "5204", 1},
494 {mcfisa_a, mcf_ctrl, "5206", 1},
495
496 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
497
498 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
499 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
500
501 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
502 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
503 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
504
505 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
506 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
507 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
508
509 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
510 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
511 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
512 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
513 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
514
515 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
516 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
517
518 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
519 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
520
521 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
522
523 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
524 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
525
526 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
527 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
528 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
529 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
530
531 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
532
533 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
534 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
535 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
536 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
537
538 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
539 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
540 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
541
542 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
543
544 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
545 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
546 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
547 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
548 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
549 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
550 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
551
552 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
553 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
554 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
555 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
556 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
557 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
558 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
559
3bdcfdf4 560 {fido_a, fido_ctrl, "fido", 1},
9840d27e 561
2da12c60 562 {0,NULL,NULL, 0}
dc84e067 563 };
252b5132 564
266abb8f
NS		 565static const struct m68k_cpu *m68k_lookup_cpu
566(const char *, const struct m68k_cpu *, int, int *);
567static int m68k_set_arch (const char *, int, int);
568static int m68k_set_cpu (const char *, int, int);
569static int m68k_set_extension (const char *, int, int);
570static void m68k_init_arch (void);
252b5132 571
151337e8
NC		 572/* This is the assembler relaxation table for m68k. m68k is a rich CISC
573 architecture and we have a lot of relaxation modes. */
252b5132 574
151337e8
NC		 575/* Macros used in the relaxation code. */
576#define TAB(x,y) (((x) << 2) + (y))
577#define TABTYPE(x) ((x) >> 2)
578
579/* Relaxation states. */
580#define BYTE 0
581#define SHORT 1
582#define LONG 2
583#define SZ_UNDEF 3
584
585/* Here are all the relaxation modes we support. First we can relax ordinary
586 branches. On 68020 and higher and on CPU32 all branch instructions take
587 three forms, so on these CPUs all branches always remain as such. When we
588 have to expand to the LONG form on a 68000, though, we substitute an
589 absolute jump instead. This is a direct replacement for unconditional
590 branches and a branch over a jump for conditional branches. However, if the
591 user requires PIC and disables this with --pcrel, we can only relax between
592 BYTE and SHORT forms, punting if that isn't enough. This gives us four
593 different relaxation modes for branches: */
594
36759679
NC		 595#define BRANCHBWL 0 /* Branch byte, word, or long. */
596#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
597#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
598#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 599
600/* We also relax coprocessor branches and DBcc's. All CPUs that support
601 coprocessor branches support them in word and long forms, so we have only
602 one relaxation mode for them. DBcc's are word only on all CPUs. We can
603 relax them to the LONG form with a branch-around sequence. This sequence
604 can use a long branch (if available) or an absolute jump (if acceptable).
605 This gives us two relaxation modes. If long branches are not available and
606 absolute jumps are not acceptable, we don't relax DBcc's. */
607
36759679
NC		 608#define FBRANCH 4 /* Coprocessor branch. */
609#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
610#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 611
612/* That's all for instruction relaxation. However, we also relax PC-relative
613 operands. Specifically, we have three operand relaxation modes. On the
614 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
615 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
616 two. Also PC+displacement+index operands in their simple form (with a non-
617 suppressed index without memory indirection) are supported on all CPUs, but
618 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
619 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
620 form of the PC+displacement+index operand. Finally, some absolute operands
621 can be relaxed down to 16-bit PC-relative. */
622
36759679
NC		 623#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
624#define PCINDEX 8 /* PC + displacement + index. */
625#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 626
627/* Note that calls to frag_var need to specify the maximum expansion
628 needed; this is currently 10 bytes for DBCC. */
629
630/* The fields are:
631 How far Forward this mode will reach:
632 How far Backward this mode will reach:
633 How many bytes this mode will add to the size of the frag
634 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 635
636 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 637relax_typeS md_relax_table[] =
638{
ac62c346
AM		 639 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
640 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
641 { 0, 0, 4, 0 },
642 { 1, 1, 0, 0 },
643
644 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
645 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
646 { 0, 0, 4, 0 },
647 { 1, 1, 0, 0 },
648
649 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
650 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
651 { 0, 0, 6, 0 },
652 { 1, 1, 0, 0 },
653
654 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
655 { 0, 0, 2, 0 },
656 { 1, 1, 0, 0 },
657 { 1, 1, 0, 0 },
658
36759679 659 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 660 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
661 { 0, 0, 4, 0 },
662 { 1, 1, 0, 0 },
663
36759679 664 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 665 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
666 { 0, 0, 10, 0 },
667 { 1, 1, 0, 0 },
668
36759679 669 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 670 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
671 { 0, 0, 10, 0 },
672 { 1, 1, 0, 0 },
673
36759679 674 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 675 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
676 { 0, 0, 6, 0 },
677 { 1, 1, 0, 0 },
678
679 { 125, -130, 0, TAB (PCINDEX, SHORT) },
680 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
681 { 0, 0, 4, 0 },
682 { 1, 1, 0, 0 },
683
36759679 684 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 685 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
686 { 0, 0, 4, 0 },
687 { 1, 1, 0, 0 },
252b5132
RH		 688};
689
690/* These are the machine dependent pseudo-ops. These are included so
691 the assembler can work on the output from the SUN C compiler, which
36759679 692 generates these. */
252b5132
RH		 693
694/* This table describes all the machine specific pseudo-ops the assembler
695 has to support. The fields are:
696 pseudo-op name without dot
697 function to call to execute this pseudo-op
36759679 698 Integer arg to pass to the function. */
252b5132
RH		 699const pseudo_typeS md_pseudo_table[] =
700{
701 {"data1", s_data1, 0},
702 {"data2", s_data2, 0},
703 {"bss", s_bss, 0},
704 {"even", s_even, 0},
705 {"skip", s_space, 0},
706 {"proc", s_proc, 0},
707#if defined (TE_SUN3) || defined (OBJ_ELF)
708 {"align", s_align_bytes, 0},
709#endif
710#ifdef OBJ_ELF
711 {"swbeg", s_ignore, 0},
712#endif
713 {"extend", float_cons, 'x'},
714 {"ldouble", float_cons, 'x'},
715
266abb8f
NS		 716 {"arch", s_m68k_arch, 0},
717 {"cpu", s_m68k_cpu, 0},
718
252b5132
RH		 719 /* The following pseudo-ops are supported for MRI compatibility. */
720 {"chip", s_chip, 0},
721 {"comline", s_space, 1},
722 {"fopt", s_fopt, 0},
723 {"mask2", s_ignore, 0},
724 {"opt", s_opt, 0},
725 {"reg", s_reg, 0},
726 {"restore", s_restore, 0},
727 {"save", s_save, 0},
728
729 {"if", s_mri_if, 0},
730 {"if.b", s_mri_if, 'b'},
731 {"if.w", s_mri_if, 'w'},
732 {"if.l", s_mri_if, 'l'},
733 {"else", s_mri_else, 0},
734 {"else.s", s_mri_else, 's'},
735 {"else.l", s_mri_else, 'l'},
736 {"endi", s_mri_endi, 0},
737 {"break", s_mri_break, 0},
738 {"break.s", s_mri_break, 's'},
739 {"break.l", s_mri_break, 'l'},
740 {"next", s_mri_next, 0},
741 {"next.s", s_mri_next, 's'},
742 {"next.l", s_mri_next, 'l'},
743 {"for", s_mri_for, 0},
744 {"for.b", s_mri_for, 'b'},
745 {"for.w", s_mri_for, 'w'},
746 {"for.l", s_mri_for, 'l'},
747 {"endf", s_mri_endf, 0},
748 {"repeat", s_mri_repeat, 0},
749 {"until", s_mri_until, 0},
750 {"until.b", s_mri_until, 'b'},
751 {"until.w", s_mri_until, 'w'},
752 {"until.l", s_mri_until, 'l'},
753 {"while", s_mri_while, 0},
754 {"while.b", s_mri_while, 'b'},
755 {"while.w", s_mri_while, 'w'},
756 {"while.l", s_mri_while, 'l'},
757 {"endw", s_mri_endw, 0},
758
759 {0, 0, 0}
760};
761
252b5132 762/* The mote pseudo ops are put into the opcode table, since they
31302357 763 don't start with a . they look like opcodes to gas. */
252b5132 764
5a38dc70 765const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 766{
767
768 {"dcl", cons, 4},
769 {"dc", cons, 2},
770 {"dcw", cons, 2},
771 {"dcb", cons, 1},
772
773 {"dsl", s_space, 4},
774 {"ds", s_space, 2},
775 {"dsw", s_space, 2},
776 {"dsb", s_space, 1},
777
778 {"xdef", s_globl, 0},
779#ifdef OBJ_ELF
780 {"align", s_align_bytes, 0},
781#else
782 {"align", s_align_ptwo, 0},
783#endif
784#ifdef M68KCOFF
785 {"sect", obj_coff_section, 0},
786 {"section", obj_coff_section, 0},
787#endif
788 {0, 0, 0}
789};
790
bd17c2c3
AM		 791/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
792 gives identical results to a 32-bit host. */
793#define TRUNC(X) ((valueT) (X) & 0xffffffff)
794#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
795
796#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
797#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
798#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
799#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
800
801#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
802#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 803#define islong(x) (1)
804
252b5132
RH		 805static char notend_table[256];
806static char alt_notend_table[256];
807#define notend(s) \
808 (! (notend_table[(unsigned char) *s] \
809 || (*s == ':' \
810 && alt_notend_table[(unsigned char) s[1]])))
811
252b5132
RH		 812#ifdef OBJ_ELF
813
c801568a
AM		 814/* Return zero if the reference to SYMBOL from within the same segment may
815 be relaxed. */
816
817/* On an ELF system, we can't relax an externally visible symbol,
818 because it may be overridden by a shared library. However, if
819 TARGET_OS is "elf", then we presume that we are assembling for an
820 embedded system, in which case we don't have to worry about shared
821 libraries, and we can relax any external sym. */
822
823#define relaxable_symbol(symbol) \
6358301e 824 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 825 || S_IS_WEAK (symbol)))
826
252b5132
RH		 827/* Compute the relocation code for a fixup of SIZE bytes, using pc
828 relative relocation if PCREL is non-zero. PIC says whether a special
829 pic relocation was requested. */
830
252b5132 831static bfd_reloc_code_real_type
31302357 832get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 833{
834 switch (pic)
835 {
836 case pic_got_pcrel:
837 switch (size)
838 {
839 case 1:
840 return BFD_RELOC_8_GOT_PCREL;
841 case 2:
842 return BFD_RELOC_16_GOT_PCREL;
843 case 4:
844 return BFD_RELOC_32_GOT_PCREL;
845 }
846 break;
847
848 case pic_got_off:
849 switch (size)
850 {
851 case 1:
852 return BFD_RELOC_8_GOTOFF;
853 case 2:
854 return BFD_RELOC_16_GOTOFF;
855 case 4:
856 return BFD_RELOC_32_GOTOFF;
857 }
858 break;
859
860 case pic_plt_pcrel:
861 switch (size)
862 {
863 case 1:
864 return BFD_RELOC_8_PLT_PCREL;
865 case 2:
866 return BFD_RELOC_16_PLT_PCREL;
867 case 4:
868 return BFD_RELOC_32_PLT_PCREL;
869 }
870 break;
871
872 case pic_plt_off:
873 switch (size)
874 {
875 case 1:
876 return BFD_RELOC_8_PLTOFF;
877 case 2:
878 return BFD_RELOC_16_PLTOFF;
879 case 4:
880 return BFD_RELOC_32_PLTOFF;
881 }
882 break;
883
884 case pic_none:
885 if (pcrel)
886 {
887 switch (size)
888 {
889 case 1:
890 return BFD_RELOC_8_PCREL;
891 case 2:
892 return BFD_RELOC_16_PCREL;
893 case 4:
894 return BFD_RELOC_32_PCREL;
895 }
896 }
897 else
898 {
899 switch (size)
900 {
901 case 1:
902 return BFD_RELOC_8;
903 case 2:
904 return BFD_RELOC_16;
905 case 4:
906 return BFD_RELOC_32;
907 }
908 }
909 }
910
911 if (pcrel)
912 {
913 if (pic == pic_none)
914 as_bad (_("Can not do %d byte pc-relative relocation"), size);
915 else
916 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
917 }
918 else
919 {
920 if (pic == pic_none)
921 as_bad (_("Can not do %d byte relocation"), size);
922 else
923 as_bad (_("Can not do %d byte pic relocation"), size);
924 }
925
926 return BFD_RELOC_NONE;
927}
928
929/* Here we decide which fixups can be adjusted to make them relative
930 to the beginning of the section instead of the symbol. Basically
931 we need to make sure that the dynamic relocations are done
932 correctly, so in some cases we force the original symbol to be
933 used. */
934int
31302357 935tc_m68k_fix_adjustable (fixS *fixP)
252b5132 936{
36759679 937 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 938 switch (fixP->fx_r_type)
939 {
940 case BFD_RELOC_8_GOT_PCREL:
941 case BFD_RELOC_16_GOT_PCREL:
942 case BFD_RELOC_32_GOT_PCREL:
943 case BFD_RELOC_8_GOTOFF:
944 case BFD_RELOC_16_GOTOFF:
945 case BFD_RELOC_32_GOTOFF:
946 case BFD_RELOC_8_PLT_PCREL:
947 case BFD_RELOC_16_PLT_PCREL:
948 case BFD_RELOC_32_PLT_PCREL:
949 case BFD_RELOC_8_PLTOFF:
950 case BFD_RELOC_16_PLTOFF:
951 case BFD_RELOC_32_PLTOFF:
952 return 0;
953
954 case BFD_RELOC_VTABLE_INHERIT:
955 case BFD_RELOC_VTABLE_ENTRY:
956 return 0;
957
958 default:
959 return 1;
960 }
961}
962
963#else /* !OBJ_ELF */
964
965#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
966
c801568a
AM		 967#define relaxable_symbol(symbol) 1
968
252b5132
RH		 969#endif /* OBJ_ELF */
970
252b5132 971arelent *
31302357 972tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 973{
974 arelent *reloc;
975 bfd_reloc_code_real_type code;
976
8ec6253e
NC		 977 /* If the tcbit is set, then this was a fixup of a negative value
978 that was never resolved. We do not have a reloc to handle this,
979 so just return. We assume that other code will have detected this
980 situation and produced a helpful error message, so we just tell the
981 user that the reloc cannot be produced. */
252b5132 982 if (fixp->fx_tcbit)
8ec6253e
NC		 983 {
984 if (fixp->fx_addsy)
b091f402
AM		 985 as_bad_where (fixp->fx_file, fixp->fx_line,
986 _("Unable to produce reloc against symbol '%s'"),
987 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 988 return NULL;
989 }
252b5132
RH		 990
991 if (fixp->fx_r_type != BFD_RELOC_NONE)
992 {
993 code = fixp->fx_r_type;
994
995 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
996 that fixup_segment converted a non-PC relative reloc into a
997 PC relative reloc. In such a case, we need to convert the
998 reloc code. */
999 if (fixp->fx_pcrel)
1000 {
1001 switch (code)
1002 {
1003 case BFD_RELOC_8:
1004 code = BFD_RELOC_8_PCREL;
1005 break;
1006 case BFD_RELOC_16:
1007 code = BFD_RELOC_16_PCREL;
1008 break;
1009 case BFD_RELOC_32:
1010 code = BFD_RELOC_32_PCREL;
1011 break;
1012 case BFD_RELOC_8_PCREL:
1013 case BFD_RELOC_16_PCREL:
1014 case BFD_RELOC_32_PCREL:
1015 case BFD_RELOC_8_GOT_PCREL:
1016 case BFD_RELOC_16_GOT_PCREL:
1017 case BFD_RELOC_32_GOT_PCREL:
1018 case BFD_RELOC_8_GOTOFF:
1019 case BFD_RELOC_16_GOTOFF:
1020 case BFD_RELOC_32_GOTOFF:
1021 case BFD_RELOC_8_PLT_PCREL:
1022 case BFD_RELOC_16_PLT_PCREL:
1023 case BFD_RELOC_32_PLT_PCREL:
1024 case BFD_RELOC_8_PLTOFF:
1025 case BFD_RELOC_16_PLTOFF:
1026 case BFD_RELOC_32_PLTOFF:
1027 break;
1028 default:
1029 as_bad_where (fixp->fx_file, fixp->fx_line,
1030 _("Cannot make %s relocation PC relative"),
1031 bfd_get_reloc_code_name (code));
1032 }
1033 }
1034 }
1035 else
1036 {
1037#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1038 switch (F (fixp->fx_size, fixp->fx_pcrel))
1039 {
1040#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1041 MAP (1, 0, BFD_RELOC_8);
1042 MAP (2, 0, BFD_RELOC_16);
1043 MAP (4, 0, BFD_RELOC_32);
1044 MAP (1, 1, BFD_RELOC_8_PCREL);
1045 MAP (2, 1, BFD_RELOC_16_PCREL);
1046 MAP (4, 1, BFD_RELOC_32_PCREL);
1047 default:
1048 abort ();
1049 }
1050 }
1051#undef F
1052#undef MAP
1053
1054 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1055 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1056 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1057 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1058#ifndef OBJ_ELF
1059 if (fixp->fx_pcrel)
1060 reloc->addend = fixp->fx_addnumber;
1061 else
1062 reloc->addend = 0;
1063#else
1064 if (!fixp->fx_pcrel)
1065 reloc->addend = fixp->fx_addnumber;
1066 else
1067 reloc->addend = (section->vma
8390138c
AS		 1068 /* Explicit sign extension in case char is
1069 unsigned. */
1070 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1071 + fixp->fx_addnumber
1072 + md_pcrel_from (fixp));
1073#endif
1074
1075 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1076 assert (reloc->howto != 0);
1077
1078 return reloc;
1079}
1080
252b5132
RH		 1081/* Handle of the OPCODE hash table. NULL means any use before
1082 m68k_ip_begin() will crash. */
1083static struct hash_control *op_hash;
1084\f
1085/* Assemble an m68k instruction. */
1086
1087static void
31302357 1088m68k_ip (char *instring)
252b5132
RH		 1089{
1090 register char *p;
1091 register struct m68k_op *opP;
1092 register const struct m68k_incant *opcode;
1093 register const char *s;
1094 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1095 char *pdot, *pdotmove;
1096 enum m68k_size siz1, siz2;
1097 char c;
1098 int losing;
1099 int opsfound;
03b13e59 1100 struct m68k_op operands_backup[6];
252b5132
RH		 1101 LITTLENUM_TYPE words[6];
1102 LITTLENUM_TYPE *wordp;
1103 unsigned long ok_arch = 0;
1104
1105 if (*instring == ' ')
36759679 1106 instring++; /* Skip leading whitespace. */
252b5132
RH		 1107
1108 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1109 or exactly 1 space. */
252b5132
RH		 1110 pdot = 0;
1111 for (p = instring; *p != '\0'; p++)
1112 {
1113 if (*p == ' ')
1114 break;
1115 if (*p == '.')
1116 pdot = p;
1117 }
1118
1119 if (p == instring)
1120 {
1121 the_ins.error = _("No operator");
1122 return;
1123 }
1124
1125 /* p now points to the end of the opcode name, probably whitespace.
1126 Make sure the name is null terminated by clobbering the
1127 whitespace, look it up in the hash table, then fix it back.
1128 Remove a dot, first, since the opcode tables have none. */
1129 if (pdot != NULL)
1130 {
1131 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1132 *pdotmove = pdotmove[1];
1133 p--;
1134 }
1135
1136 c = *p;
1137 *p = '\0';
1138 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1139 *p = c;
1140
1141 if (pdot != NULL)
1142 {
1143 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1144 *pdotmove = pdotmove[-1];
1145 *pdot = '.';
1146 ++p;
1147 }
1148
1149 if (opcode == NULL)
1150 {
1151 the_ins.error = _("Unknown operator");
1152 return;
1153 }
1154
36759679 1155 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1156 while (*p == ' ')
1157 ++p;
1158
1159 if (opcode->m_operands == 0)
1160 {
1161 char *old = input_line_pointer;
1162 *old = '\n';
1163 input_line_pointer = p;
36759679 1164 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1165 mote_pseudo_table[opcode->m_opnum].poc_handler
1166 (mote_pseudo_table[opcode->m_opnum].poc_val);
1167 input_line_pointer = old;
1168 *old = 0;
1169
1170 return;
1171 }
1172
1173 if (flag_mri && opcode->m_opnum == 0)
1174 {
1175 /* In MRI mode, random garbage is allowed after an instruction
1176 which accepts no operands. */
1177 the_ins.args = opcode->m_operands;
1178 the_ins.numargs = opcode->m_opnum;
1179 the_ins.numo = opcode->m_codenum;
1180 the_ins.opcode[0] = getone (opcode);
1181 the_ins.opcode[1] = gettwo (opcode);
1182 return;
1183 }
1184
1185 for (opP = &the_ins.operands[0]; *p; opP++)
1186 {
1187 p = crack_operand (p, opP);
1188
1189 if (opP->error)
1190 {
1191 the_ins.error = opP->error;
1192 return;
1193 }
1194 }
1195
1196 opsfound = opP - &the_ins.operands[0];
1197
1198 /* This ugly hack is to support the floating pt opcodes in their
1199 standard form. Essentially, we fake a first enty of type COP#1 */
1200 if (opcode->m_operands[0] == 'I')
1201 {
1202 int n;
1203
1204 for (n = opsfound; n > 0; --n)
1205 the_ins.operands[n] = the_ins.operands[n - 1];
1206
31302357 1207 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1208 the_ins.operands[0].mode = CONTROL;
1209 the_ins.operands[0].reg = m68k_float_copnum;
1210 opsfound++;
1211 }
1212
36759679 1213 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1214 for (losing = 0;;)
1215 {
1216 /* If we didn't get the right number of ops, or we have no
92774660 1217 common model with this pattern then reject this pattern. */
252b5132
RH		 1218
1219 ok_arch |= opcode->m_arch;
1220 if (opsfound != opcode->m_opnum
1221 || ((opcode->m_arch & current_architecture) == 0))
1222 ++losing;
1223 else
1224 {
03b13e59
NC		 1225 int i;
1226
1227 /* Make a copy of the operands of this insn so that
1228 we can modify them safely, should we want to. */
1229 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1230 for (i = 0; i < opsfound; i++)
1231 operands_backup[i] = the_ins.operands[i];
1232
1233 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1234 *s && !losing;
1235 s += 2, opP++)
1236 {
1237 /* Warning: this switch is huge! */
1238 /* I've tried to organize the cases into this order:
1239 non-alpha first, then alpha by letter. Lower-case
1240 goes directly before uppercase counterpart. */
1241 /* Code with multiple case ...: gets sorted by the lowest
1242 case ... it belongs to. I hope this makes sense. */
1243 switch (*s)
1244 {
1245 case '!':
1246 switch (opP->mode)
1247 {
1248 case IMMED:
1249 case DREG:
1250 case AREG:
1251 case FPREG:
1252 case CONTROL:
1253 case AINC:
1254 case ADEC:
1255 case REGLST:
1256 losing++;
1257 break;
1258 default:
1259 break;
1260 }
1261 break;
1262
1263 case '<':
1264 switch (opP->mode)
1265 {
1266 case DREG:
1267 case AREG:
1268 case FPREG:
1269 case CONTROL:
1270 case IMMED:
1271 case ADEC:
1272 case REGLST:
1273 losing++;
1274 break;
1275 default:
1276 break;
1277 }
1278 break;
1279
1280 case '>':
1281 switch (opP->mode)
1282 {
1283 case DREG:
1284 case AREG:
1285 case FPREG:
1286 case CONTROL:
1287 case IMMED:
1288 case AINC:
1289 case REGLST:
1290 losing++;
1291 break;
1292 case ABSL:
1293 break;
1294 default:
1295 if (opP->reg == PC
1296 || opP->reg == ZPC)
1297 losing++;
1298 break;
1299 }
1300 break;
1301
1302 case 'm':
1303 switch (opP->mode)
1304 {
1305 case DREG:
1306 case AREG:
1307 case AINDR:
1308 case AINC:
1309 case ADEC:
1310 break;
1311 default:
1312 losing++;
1313 }
8a104df9 1314 break;
252b5132
RH		 1315
1316 case 'n':
1317 switch (opP->mode)
1318 {
1319 case DISP:
1320 break;
1321 default:
1322 losing++;
1323 }
8a104df9 1324 break;
252b5132
RH		 1325
1326 case 'o':
1327 switch (opP->mode)
1328 {
1329 case BASE:
1330 case ABSL:
1331 case IMMED:
1332 break;
1333 default:
1334 losing++;
1335 }
8a104df9 1336 break;
252b5132
RH		 1337
1338 case 'p':
1339 switch (opP->mode)
1340 {
1341 case DREG:
1342 case AREG:
1343 case AINDR:
1344 case AINC:
1345 case ADEC:
1346 break;
1347 case DISP:
1348 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1349 losing++;
252b5132
RH		 1350 break;
1351 default:
1352 losing++;
1353 }
8a104df9 1354 break;
252b5132
RH		 1355
1356 case 'q':
1357 switch (opP->mode)
1358 {
1359 case DREG:
1360 case AINDR:
1361 case AINC:
1362 case ADEC:
1363 break;
1364 case DISP:
1365 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1366 losing++;
252b5132
RH		 1367 break;
1368 default:
1369 losing++;
1370 break;
1371 }
8a104df9 1372 break;
252b5132
RH		 1373
1374 case 'v':
1375 switch (opP->mode)
1376 {
1377 case DREG:
1378 case AINDR:
1379 case AINC:
1380 case ADEC:
1381 case ABSL:
1382 break;
1383 case DISP:
1384 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1385 losing++;
252b5132
RH		 1386 break;
1387 default:
1388 losing++;
1389 break;
1390 }
1391 break;
1392
1393 case '#':
1394 if (opP->mode != IMMED)
1395 losing++;
1396 else if (s[1] == 'b'
1397 && ! isvar (&opP->disp)
1398 && (opP->disp.exp.X_op != O_constant
1399 || ! isbyte (opP->disp.exp.X_add_number)))
1400 losing++;
1401 else if (s[1] == 'B'
1402 && ! isvar (&opP->disp)
1403 && (opP->disp.exp.X_op != O_constant
1404 || ! issbyte (opP->disp.exp.X_add_number)))
1405 losing++;
1406 else if (s[1] == 'w'
1407 && ! isvar (&opP->disp)
1408 && (opP->disp.exp.X_op != O_constant
1409 || ! isword (opP->disp.exp.X_add_number)))
1410 losing++;
1411 else if (s[1] == 'W'
1412 && ! isvar (&opP->disp)
1413 && (opP->disp.exp.X_op != O_constant
1414 || ! issword (opP->disp.exp.X_add_number)))
1415 losing++;
1416 break;
1417
1418 case '^':
1419 case 'T':
1420 if (opP->mode != IMMED)
1421 losing++;
1422 break;
1423
1424 case '$':
1425 if (opP->mode == AREG
1426 || opP->mode == CONTROL
1427 || opP->mode == FPREG
1428 || opP->mode == IMMED
1429 || opP->mode == REGLST
1430 || (opP->mode != ABSL
1431 && (opP->reg == PC
1432 || opP->reg == ZPC)))
1433 losing++;
1434 break;
1435
1436 case '%':
1437 if (opP->mode == CONTROL
1438 || opP->mode == FPREG
1439 || opP->mode == REGLST
1440 || opP->mode == IMMED
1441 || (opP->mode != ABSL
1442 && (opP->reg == PC
1443 || opP->reg == ZPC)))
1444 losing++;
1445 break;
1446
1447 case '&':
1448 switch (opP->mode)
1449 {
1450 case DREG:
1451 case AREG:
1452 case FPREG:
1453 case CONTROL:
1454 case IMMED:
1455 case AINC:
1456 case ADEC:
1457 case REGLST:
1458 losing++;
1459 break;
1460 case ABSL:
1461 break;
1462 default:
1463 if (opP->reg == PC
1464 || opP->reg == ZPC)
1465 losing++;
1466 break;
1467 }
1468 break;
1469
1470 case '*':
1471 if (opP->mode == CONTROL
1472 || opP->mode == FPREG
1473 || opP->mode == REGLST)
1474 losing++;
1475 break;
1476
1477 case '+':
1478 if (opP->mode != AINC)
1479 losing++;
1480 break;
1481
1482 case '-':
1483 if (opP->mode != ADEC)
1484 losing++;
1485 break;
1486
1487 case '/':
1488 switch (opP->mode)
1489 {
1490 case AREG:
1491 case CONTROL:
1492 case FPREG:
1493 case AINC:
1494 case ADEC:
1495 case IMMED:
1496 case REGLST:
1497 losing++;
1498 break;
1499 default:
1500 break;
1501 }
1502 break;
1503
1504 case ';':
1505 switch (opP->mode)
1506 {
1507 case AREG:
1508 case CONTROL:
1509 case FPREG:
1510 case REGLST:
1511 losing++;
1512 break;
1513 default:
1514 break;
1515 }
1516 break;
1517
1518 case '?':
1519 switch (opP->mode)
1520 {
1521 case AREG:
1522 case CONTROL:
1523 case FPREG:
1524 case AINC:
1525 case ADEC:
1526 case IMMED:
1527 case REGLST:
1528 losing++;
1529 break;
1530 case ABSL:
1531 break;
1532 default:
1533 if (opP->reg == PC || opP->reg == ZPC)
1534 losing++;
1535 break;
1536 }
1537 break;
1538
1539 case '@':
1540 switch (opP->mode)
1541 {
1542 case AREG:
1543 case CONTROL:
1544 case FPREG:
1545 case IMMED:
1546 case REGLST:
1547 losing++;
1548 break;
1549 default:
1550 break;
1551 }
1552 break;
1553
1554 case '~': /* For now! (JF FOO is this right?) */
1555 switch (opP->mode)
1556 {
1557 case DREG:
1558 case AREG:
1559 case CONTROL:
1560 case FPREG:
1561 case IMMED:
1562 case REGLST:
1563 losing++;
1564 break;
1565 case ABSL:
1566 break;
1567 default:
1568 if (opP->reg == PC
1569 || opP->reg == ZPC)
1570 losing++;
1571 break;
1572 }
1573 break;
1574
1575 case '3':
1576 if (opP->mode != CONTROL
1577 || (opP->reg != TT0 && opP->reg != TT1))
1578 losing++;
1579 break;
1580
1581 case 'A':
1582 if (opP->mode != AREG)
1583 losing++;
1584 break;
1585
1586 case 'a':
1587 if (opP->mode != AINDR)
1588 ++losing;
1589 break;
1590
fd99574b
NC		 1591 case '4':
1592 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1593 && (opP->mode != DISP
1594 || opP->reg < ADDR0
1595 || opP->reg > ADDR7))
1596 ++losing;
1597 break;
1598
252b5132
RH		 1599 case 'B': /* FOO */
1600 if (opP->mode != ABSL
1601 || (flag_long_jumps
1602 && strncmp (instring, "jbsr", 4) == 0))
1603 losing++;
1604 break;
1605
3e602632
NC		 1606 case 'b':
1607 switch (opP->mode)
1608 {
1609 case IMMED:
1610 case ABSL:
1611 case AREG:
1612 case FPREG:
1613 case CONTROL:
1614 case POST:
1615 case PRE:
1616 case REGLST:
1617 losing++;
1618 break;
1619 default:
1620 break;
1621 }
1622 break;
1623
252b5132
RH		 1624 case 'C':
1625 if (opP->mode != CONTROL || opP->reg != CCR)
1626 losing++;
1627 break;
1628
1629 case 'd':
1630 if (opP->mode != DISP
1631 || opP->reg < ADDR0
1632 || opP->reg > ADDR7)
1633 losing++;
1634 break;
1635
1636 case 'D':
1637 if (opP->mode != DREG)
1638 losing++;
1639 break;
1640
6da466c7
ILT		 1641 case 'E':
1642 if (opP->reg != ACC)
1643 losing++;
1644 break;
1645
fd99574b
NC		 1646 case 'e':
1647 if (opP->reg != ACC && opP->reg != ACC1
1648 && opP->reg != ACC2 && opP->reg != ACC3)
1649 losing++;
1650 break;
1651
252b5132
RH		 1652 case 'F':
1653 if (opP->mode != FPREG)
1654 losing++;
1655 break;
1656
6da466c7
ILT		 1657 case 'G':
1658 if (opP->reg != MACSR)
1659 losing++;
1660 break;
1661
fd99574b
NC		 1662 case 'g':
1663 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1664 losing++;
1665 break;
1666
6da466c7
ILT		 1667 case 'H':
1668 if (opP->reg != MASK)
1669 losing++;
1670 break;
1671
252b5132
RH		 1672 case 'I':
1673 if (opP->mode != CONTROL
1674 || opP->reg < COP0
1675 || opP->reg > COP7)
1676 losing++;
1677 break;
1678
fd99574b
NC		 1679 case 'i':
1680 if (opP->mode != LSH && opP->mode != RSH)
1681 losing++;
1682 break;
1683
252b5132
RH		 1684 case 'J':
1685 if (opP->mode != CONTROL
1686 || opP->reg < USP
0b2e31dc
NS		 1687 || opP->reg > last_movec_reg
1688 || !control_regs)
252b5132
RH		 1689 losing++;
1690 else
1691 {
1692 const enum m68k_register *rp;
0b2e31dc 1693
252b5132
RH		 1694 for (rp = control_regs; *rp; rp++)
1695 if (*rp == opP->reg)
1696 break;
1697 if (*rp == 0)
1698 losing++;
1699 }
1700 break;
1701
1702 case 'k':
1703 if (opP->mode != IMMED)
1704 losing++;
1705 break;
1706
1707 case 'l':
1708 case 'L':
1709 if (opP->mode == DREG
1710 || opP->mode == AREG
1711 || opP->mode == FPREG)
1712 {
1713 if (s[1] == '8')
1714 losing++;
1715 else
1716 {
1717 switch (opP->mode)
1718 {
1719 case DREG:
1720 opP->mask = 1 << (opP->reg - DATA0);
1721 break;
1722 case AREG:
1723 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1724 break;
1725 case FPREG:
1726 opP->mask = 1 << (opP->reg - FP0 + 16);
1727 break;
1728 default:
1729 abort ();
1730 }
1731 opP->mode = REGLST;
1732 }
1733 }
1734 else if (opP->mode == CONTROL)
1735 {
1736 if (s[1] != '8')
1737 losing++;
1738 else
1739 {
1740 switch (opP->reg)
1741 {
1742 case FPI:
1743 opP->mask = 1 << 24;
1744 break;
1745 case FPS:
1746 opP->mask = 1 << 25;
1747 break;
1748 case FPC:
1749 opP->mask = 1 << 26;
1750 break;
1751 default:
1752 losing++;
1753 break;
1754 }
1755 opP->mode = REGLST;
1756 }
1757 }
1758 else if (opP->mode != REGLST)
1759 losing++;
1760 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1761 losing++;
1762 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1763 losing++;
1764 break;
1765
1766 case 'M':
1767 if (opP->mode != IMMED)
1768 losing++;
1769 else if (opP->disp.exp.X_op != O_constant
1770 || ! issbyte (opP->disp.exp.X_add_number))
1771 losing++;
1772 else if (! m68k_quick
1773 && instring[3] != 'q'
1774 && instring[4] != 'q')
1775 losing++;
1776 break;
1777
1778 case 'O':
1779 if (opP->mode != DREG
1780 && opP->mode != IMMED
1781 && opP->mode != ABSL)
1782 losing++;
1783 break;
1784
1785 case 'Q':
1786 if (opP->mode != IMMED)
1787 losing++;
1788 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1789 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1790 losing++;
1791 else if (! m68k_quick
1792 && (strncmp (instring, "add", 3) == 0
1793 || strncmp (instring, "sub", 3) == 0)
1794 && instring[3] != 'q')
1795 losing++;
1796 break;
1797
1798 case 'R':
1799 if (opP->mode != DREG && opP->mode != AREG)
1800 losing++;
1801 break;
1802
1803 case 'r':
1804 if (opP->mode != AINDR
1805 && (opP->mode != BASE
1806 || (opP->reg != 0
1807 && opP->reg != ZADDR0)
1808 || opP->disp.exp.X_op != O_absent
1809 || ((opP->index.reg < DATA0
1810 || opP->index.reg > DATA7)
1811 && (opP->index.reg < ADDR0
1812 || opP->index.reg > ADDR7))
1813 || opP->index.size != SIZE_UNSPEC
1814 || opP->index.scale != 1))
1815 losing++;
1816 break;
1817
1818 case 's':
1819 if (opP->mode != CONTROL
1820 || ! (opP->reg == FPI
1821 || opP->reg == FPS
1822 || opP->reg == FPC))
1823 losing++;
1824 break;
1825
1826 case 'S':
1827 if (opP->mode != CONTROL || opP->reg != SR)
1828 losing++;
1829 break;
1830
1831 case 't':
1832 if (opP->mode != IMMED)
1833 losing++;
1834 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1835 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1836 losing++;
1837 break;
1838
1839 case 'U':
1840 if (opP->mode != CONTROL || opP->reg != USP)
1841 losing++;
1842 break;
1843
3e602632
NC		 1844 case 'x':
1845 if (opP->mode != IMMED)
1846 losing++;
1847 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1848 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1849 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1850 losing++;
1851 break;
1852
252b5132
RH		 1853 /* JF these are out of order. We could put them
1854 in order if we were willing to put up with
1855 bunches of #ifdef m68851s in the code.
1856
1857 Don't forget that you need these operands
1858 to use 68030 MMU instructions. */
1859#ifndef NO_68851
36759679 1860 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1861 case '|':
1862 if (opP->mode == CONTROL
1863 || opP->mode == FPREG
1864 || opP->mode == DREG
1865 || opP->mode == AREG
1866 || opP->mode == REGLST)
1867 losing++;
1868 /* We should accept immediate operands, but they
1869 supposedly have to be quad word, and we don't
1870 handle that. I would like to see what a Motorola
1871 assembler does before doing something here. */
1872 if (opP->mode == IMMED)
1873 losing++;
1874 break;
1875
1876 case 'f':
1877 if (opP->mode != CONTROL
1878 || (opP->reg != SFC && opP->reg != DFC))
1879 losing++;
1880 break;
1881
1882 case '0':
1883 if (opP->mode != CONTROL || opP->reg != TC)
1884 losing++;
1885 break;
1886
1887 case '1':
1888 if (opP->mode != CONTROL || opP->reg != AC)
1889 losing++;
1890 break;
1891
1892 case '2':
1893 if (opP->mode != CONTROL
1894 || (opP->reg != CAL
1895 && opP->reg != VAL
1896 && opP->reg != SCC))
1897 losing++;
1898 break;
1899
1900 case 'V':
1901 if (opP->mode != CONTROL
1902 || opP->reg != VAL)
1903 losing++;
1904 break;
1905
1906 case 'W':
1907 if (opP->mode != CONTROL
1908 || (opP->reg != DRP
1909 && opP->reg != SRP
1910 && opP->reg != CRP))
1911 losing++;
1912 break;
1913
3e602632
NC		 1914 case 'w':
1915 switch (opP->mode)
1916 {
1917 case IMMED:
1918 case ABSL:
1919 case AREG:
1920 case DREG:
1921 case FPREG:
1922 case CONTROL:
1923 case POST:
1924 case PRE:
1925 case REGLST:
1926 losing++;
1927 break;
1928 default:
1929 break;
1930 }
1931 break;
1932
252b5132
RH		 1933 case 'X':
1934 if (opP->mode != CONTROL
1935 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1936 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1937 losing++;
1938 break;
1939
1940 case 'Y':
1941 if (opP->mode != CONTROL || opP->reg != PSR)
1942 losing++;
1943 break;
1944
1945 case 'Z':
1946 if (opP->mode != CONTROL || opP->reg != PCSR)
1947 losing++;
1948 break;
1949#endif
1950 case 'c':
1951 if (opP->mode != CONTROL
1952 || (opP->reg != NC
1953 && opP->reg != IC
1954 && opP->reg != DC
1955 && opP->reg != BC))
36759679 1956 losing++;
252b5132
RH		 1957 break;
1958
1959 case '_':
1960 if (opP->mode != ABSL)
1961 ++losing;
1962 break;
1963
6da466c7
ILT		 1964 case 'u':
1965 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1966 losing++;
1967 /* FIXME: kludge instead of fixing parser:
1968 upper/lower registers are *not* CONTROL
92774660 1969 registers, but ordinary ones. */
6da466c7
ILT		 1970 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1971 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1972 opP->mode = DREG;
1973 else
1974 opP->mode = AREG;
1975 break;
1976
3e602632
NC		 1977 case 'y':
1978 if (!(opP->mode == AINDR
31302357
AS		 1979 || (opP->mode == DISP
1980 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 1981 losing++;
1982 break;
1983
1984 case 'z':
1985 if (!(opP->mode == AINDR || opP->mode == DISP))
1986 losing++;
1987 break;
1988
252b5132
RH		 1989 default:
1990 abort ();
36759679 1991 }
252b5132
RH		 1992
1993 if (losing)
1994 break;
36759679 1995 }
03b13e59
NC		 1996
1997 /* Since we have found the correct instruction, copy
1998 in the modifications that we may have made. */
1999 if (!losing)
2000 for (i = 0; i < opsfound; i++)
2001 the_ins.operands[i] = operands_backup[i];
36759679 2002 }
252b5132
RH		 2003
2004 if (!losing)
36759679 2005 break;
252b5132
RH		 2006
2007 opcode = opcode->m_next;
2008
2009 if (!opcode)
2010 {
2011 if (ok_arch
2012 && !(ok_arch & current_architecture))
2013 {
6d89cc8f
NS		 2014 const struct m68k_cpu *cpu;
2015 int any = 0;
2016 size_t space = 400;
2017 char *buf = xmalloc (space + 1);
2018 size_t len;
2019 int paren = 1;
2020
2021 the_ins.error = buf;
2022 /* Make sure there's a NUL at the end of the buffer -- strncpy
2023 won't write one when it runs out of buffer */
2024 buf[space] = 0;
2025#define APPEND(STRING) \
2026 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2027
2028 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2029 switch (ok_arch)
2030 {
6b6e92f4 2031 case mcfisa_a:
6d89cc8f 2032 APPEND (_("ColdFire ISA_A"));
6b6e92f4
NC		 2033 break;
2034 case mcfhwdiv:
6d89cc8f 2035 APPEND (_("ColdFire hardware divide"));
6b6e92f4
NC		 2036 break;
2037 case mcfisa_aa:
6d89cc8f 2038 APPEND (_("ColdFire ISA_A+"));
6b6e92f4
NC		 2039 break;
2040 case mcfisa_b:
6d89cc8f 2041 APPEND (_("ColdFire ISA_B"));
6b6e92f4 2042 break;
3e602632 2043 case cfloat:
6d89cc8f 2044 APPEND (_("ColdFire fpu"));
3e602632 2045 break;
252b5132 2046 case mfloat:
6d89cc8f 2047 APPEND (_("M68K fpu"));
252b5132
RH		 2048 break;
2049 case mmmu:
6d89cc8f 2050 APPEND (_("M68K mmu"));
252b5132
RH		 2051 break;
2052 case m68020up:
6d89cc8f 2053 APPEND (_("68020 or higher"));
252b5132
RH		 2054 break;
2055 case m68000up:
6d89cc8f 2056 APPEND (_("68000 or higher"));
252b5132
RH		 2057 break;
2058 case m68010up:
6d89cc8f 2059 APPEND (_("68010 or higher"));
252b5132
RH		 2060 break;
2061 default:
6d89cc8f
NS		 2062 paren = 0;
2063 }
2064 if (paren)
2065 APPEND (" (");
6b6e92f4 2066
6d89cc8f
NS		 2067 for (cpu = m68k_cpus; cpu->name; cpu++)
2068 if (!cpu->alias && (cpu->arch & ok_arch))
2069 {
2070 const struct m68k_cpu *alias;
869ddf2a
NS		 2071 int seen_master = 0;
2072
6d89cc8f
NS		 2073 if (any)
2074 APPEND (", ");
2075 any = 0;
2076 APPEND (cpu->name);
869ddf2a
NS		 2077 for (alias = cpu; alias != m68k_cpus; alias--)
2078 if (alias[-1].alias >= 0)
2079 break;
2080 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2081 {
869ddf2a
NS		 2082 if (!alias->alias)
2083 seen_master = 1;
2084 else
2085 {
2086 if (any)
2087 APPEND (", ");
2088 else
2089 APPEND (" [");
2090 APPEND (alias->name);
2091 any = 1;
2092 }
6d89cc8f 2093 }
869ddf2a
NS		 2094 if (any)
2095 APPEND ("]");
6d89cc8f 2096 any = 1;
252b5132 2097 }
6d89cc8f
NS		 2098 if (paren)
2099 APPEND (")");
2100#undef APPEND
2101 if (!space)
2102 {
2103 /* we ran out of space, so replace the end of the list
2104 with ellipsis. */
2105 buf -= 4;
2106 while (*buf != ' ')
2107 buf--;
2108 strcpy (buf, " ...");
252b5132 2109 }
252b5132
RH		 2110 }
2111 else
2112 the_ins.error = _("operands mismatch");
2113 return;
36759679 2114 }
252b5132
RH		 2115
2116 losing = 0;
2117 }
2118
36759679 2119 /* Now assemble it. */
252b5132
RH		 2120 the_ins.args = opcode->m_operands;
2121 the_ins.numargs = opcode->m_opnum;
2122 the_ins.numo = opcode->m_codenum;
2123 the_ins.opcode[0] = getone (opcode);
2124 the_ins.opcode[1] = gettwo (opcode);
2125
2126 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2127 {
2128 /* This switch is a doozy.
31302357 2129 Watch the first step; its a big one! */
252b5132
RH		 2130 switch (s[0])
2131 {
2132
2133 case '*':
2134 case '~':
2135 case '%':
2136 case ';':
2137 case '@':
2138 case '!':
2139 case '&':
2140 case '$':
2141 case '?':
2142 case '/':
2143 case '<':
2144 case '>':
3e602632 2145 case 'b':
252b5132
RH		 2146 case 'm':
2147 case 'n':
2148 case 'o':
2149 case 'p':
2150 case 'q':
2151 case 'v':
3e602632
NC		 2152 case 'w':
2153 case 'y':
2154 case 'z':
fd99574b 2155 case '4':
252b5132
RH		 2156#ifndef NO_68851
2157 case '|':
2158#endif
2159 switch (opP->mode)
2160 {
2161 case IMMED:
2162 tmpreg = 0x3c; /* 7.4 */
2163 if (strchr ("bwl", s[1]))
3e602632 2164 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2165 else
2166 nextword = get_num (&opP->disp, 0);
2167 if (isvar (&opP->disp))
2168 add_fix (s[1], &opP->disp, 0, 0);
2169 switch (s[1])
2170 {
2171 case 'b':
2172 if (!isbyte (nextword))
2173 opP->error = _("operand out of range");
2174 addword (nextword);
2175 baseo = 0;
2176 break;
2177 case 'w':
2178 if (!isword (nextword))
2179 opP->error = _("operand out of range");
2180 addword (nextword);
2181 baseo = 0;
2182 break;
2183 case 'W':
2184 if (!issword (nextword))
2185 opP->error = _("operand out of range");
2186 addword (nextword);
2187 baseo = 0;
2188 break;
2189 case 'l':
2190 addword (nextword >> 16);
2191 addword (nextword);
2192 baseo = 0;
2193 break;
2194
2195 case 'f':
2196 baseo = 2;
2197 outro = 8;
2198 break;
2199 case 'F':
2200 baseo = 4;
2201 outro = 11;
2202 break;
2203 case 'x':
2204 baseo = 6;
2205 outro = 15;
2206 break;
2207 case 'p':
2208 baseo = 6;
2209 outro = -1;
2210 break;
2211 default:
2212 abort ();
2213 }
2214 if (!baseo)
2215 break;
2216
36759679 2217 /* We gotta put out some float. */
252b5132
RH		 2218 if (op (&opP->disp) != O_big)
2219 {
2220 valueT val;
2221 int gencnt;
2222
2223 /* Can other cases happen here? */
2224 if (op (&opP->disp) != O_constant)
2225 abort ();
2226
2227 val = (valueT) offs (&opP->disp);
2228 gencnt = 0;
2229 do
2230 {
2231 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2232 val >>= LITTLENUM_NUMBER_OF_BITS;
2233 ++gencnt;
2234 }
2235 while (val != 0);
2236 offs (&opP->disp) = gencnt;
2237 }
2238 if (offs (&opP->disp) > 0)
2239 {
2240 if (offs (&opP->disp) > baseo)
2241 {
2242 as_warn (_("Bignum too big for %c format; truncated"),
2243 s[1]);
2244 offs (&opP->disp) = baseo;
2245 }
2246 baseo -= offs (&opP->disp);
2247 while (baseo--)
2248 addword (0);
2249 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2250 offs (&opP->disp)--;
2251 --wordp)
2252 addword (*wordp);
2253 break;
2254 }
2255 gen_to_words (words, baseo, (long) outro);
2256 for (wordp = words; baseo--; wordp++)
2257 addword (*wordp);
2258 break;
2259 case DREG:
2260 tmpreg = opP->reg - DATA; /* 0.dreg */
2261 break;
2262 case AREG:
2263 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2264 break;
2265 case AINDR:
2266 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2267 break;
2268 case ADEC:
2269 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2270 break;
2271 case AINC:
2272 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2273 break;
2274 case DISP:
2275
3e602632 2276 nextword = get_num (&opP->disp, 90);
252b5132 2277
580b9172
NC		 2278 /* Convert mode 5 addressing with a zero offset into
2279 mode 2 addressing to reduce the instruction size by a
2280 word. */
2281 if (! isvar (&opP->disp)
2282 && (nextword == 0)
2283 && (opP->disp.size == SIZE_UNSPEC)
2284 && (opP->reg >= ADDR0)
2285 && (opP->reg <= ADDR7))
2286 {
2287 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2288 break;
2289 }
2290
252b5132
RH		 2291 if (opP->reg == PC
2292 && ! isvar (&opP->disp)
2293 && m68k_abspcadd)
2294 {
2295 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2296 opP->disp.exp.X_add_symbol =
2297 section_symbol (absolute_section);
252b5132
RH		 2298 }
2299
36759679 2300 /* Force into index mode. Hope this works. */
252b5132
RH		 2301
2302 /* We do the first bit for 32-bit displacements, and the
2303 second bit for 16 bit ones. It is possible that we
2304 should make the default be WORD instead of LONG, but
2305 I think that'd break GCC, so we put up with a little
2306 inefficiency for the sake of working output. */
2307
2308 if (!issword (nextword)
2309 || (isvar (&opP->disp)
2310 && ((opP->disp.size == SIZE_UNSPEC
2311 && flag_short_refs == 0
2312 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2313 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2314 || opP->disp.size == SIZE_LONG)))
2315 {
2316 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2317 || arch_coldfire_p (current_architecture))
252b5132
RH		 2318 opP->error =
2319 _("displacement too large for this architecture; needs 68020 or higher");
2320 if (opP->reg == PC)
2321 tmpreg = 0x3B; /* 7.3 */
2322 else
2323 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2324 if (isvar (&opP->disp))
2325 {
2326 if (opP->reg == PC)
2327 {
2328 if (opP->disp.size == SIZE_LONG
2329#ifdef OBJ_ELF
2330 /* If the displacement needs pic
2331 relocation it cannot be relaxed. */
2332 || opP->disp.pic_reloc != pic_none
2333#endif
2334 )
2335 {
2336 addword (0x0170);
2337 add_fix ('l', &opP->disp, 1, 2);
2338 }
2339 else
2340 {
2341 add_frag (adds (&opP->disp),
bd17c2c3 2342 SEXT (offs (&opP->disp)),
151337e8 2343 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2344 break;
2345 }
2346 }
2347 else
2348 {
2349 addword (0x0170);
2350 add_fix ('l', &opP->disp, 0, 0);
2351 }
2352 }
2353 else
2354 addword (0x0170);
2355 addword (nextword >> 16);
2356 }
2357 else
2358 {
2359 if (opP->reg == PC)
2360 tmpreg = 0x3A; /* 7.2 */
2361 else
2362 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2363
2364 if (isvar (&opP->disp))
2365 {
2366 if (opP->reg == PC)
2367 {
2368 add_fix ('w', &opP->disp, 1, 0);
2369 }
2370 else
2371 add_fix ('w', &opP->disp, 0, 0);
2372 }
2373 }
2374 addword (nextword);
2375 break;
2376
2377 case POST:
2378 case PRE:
2379 case BASE:
2380 nextword = 0;
3e602632 2381 baseo = get_num (&opP->disp, 90);
252b5132 2382 if (opP->mode == POST || opP->mode == PRE)
3e602632 2383 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2384 /* Figure out the `addressing mode'.
2385 Also turn on the BASE_DISABLE bit, if needed. */
2386 if (opP->reg == PC || opP->reg == ZPC)
2387 {
2388 tmpreg = 0x3b; /* 7.3 */
2389 if (opP->reg == ZPC)
2390 nextword |= 0x80;
2391 }
2392 else if (opP->reg == 0)
2393 {
2394 nextword |= 0x80;
2395 tmpreg = 0x30; /* 6.garbage */
2396 }
2397 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2398 {
2399 nextword |= 0x80;
2400 tmpreg = 0x30 + opP->reg - ZADDR0;
2401 }
2402 else
2403 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2404
2405 siz1 = opP->disp.size;
2406 if (opP->mode == POST || opP->mode == PRE)
2407 siz2 = opP->odisp.size;
2408 else
2409 siz2 = SIZE_UNSPEC;
2410
36759679 2411 /* Index register stuff. */
252b5132
RH		 2412 if (opP->index.reg != 0
2413 && opP->index.reg >= DATA
2414 && opP->index.reg <= ADDR7)
2415 {
2416 nextword |= (opP->index.reg - DATA) << 12;
2417
2418 if (opP->index.size == SIZE_LONG
2419 || (opP->index.size == SIZE_UNSPEC
2420 && m68k_index_width_default == SIZE_LONG))
2421 nextword |= 0x800;
2422
92774660 2423 if ((opP->index.scale != 1
252b5132 2424 && cpu_of_arch (current_architecture) < m68020)
92774660 2425 || (opP->index.scale == 8
3e602632 2426 && (arch_coldfire_p (current_architecture)
6b6e92f4 2427 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2428 {
2429 opP->error =
2430 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2431 }
2432
6da466c7
ILT		 2433 if (arch_coldfire_p (current_architecture)
2434 && opP->index.size == SIZE_WORD)
2435 opP->error = _("invalid index size for coldfire");
2436
252b5132
RH		 2437 switch (opP->index.scale)
2438 {
2439 case 1:
2440 break;
2441 case 2:
2442 nextword |= 0x200;
2443 break;
2444 case 4:
2445 nextword |= 0x400;
2446 break;
2447 case 8:
2448 nextword |= 0x600;
2449 break;
2450 default:
2451 abort ();
2452 }
2453 /* IF its simple,
2454 GET US OUT OF HERE! */
2455
2456 /* Must be INDEX, with an index register. Address
2457 register cannot be ZERO-PC, and either :b was
2458 forced, or we know it will fit. For a 68000 or
2459 68010, force this mode anyways, because the
2460 larger modes aren't supported. */
2461 if (opP->mode == BASE
2462 && ((opP->reg >= ADDR0
2463 && opP->reg <= ADDR7)
2464 || opP->reg == PC))
2465 {
2466 if (siz1 == SIZE_BYTE
2467 || cpu_of_arch (current_architecture) < m68020
6da466c7 2468 || arch_coldfire_p (current_architecture)
252b5132
RH		 2469 || (siz1 == SIZE_UNSPEC
2470 && ! isvar (&opP->disp)
2471 && issbyte (baseo)))
2472 {
2473 nextword += baseo & 0xff;
2474 addword (nextword);
2475 if (isvar (&opP->disp))
2476 {
2477 /* Do a byte relocation. If it doesn't
2478 fit (possible on m68000) let the
2479 fixup processing complain later. */
2480 if (opP->reg == PC)
2481 add_fix ('B', &opP->disp, 1, 1);
2482 else
2483 add_fix ('B', &opP->disp, 0, 0);
2484 }
2485 else if (siz1 != SIZE_BYTE)
2486 {
2487 if (siz1 != SIZE_UNSPEC)
2488 as_warn (_("Forcing byte displacement"));
2489 if (! issbyte (baseo))
2490 opP->error = _("byte displacement out of range");
2491 }
2492
2493 break;
2494 }
2495 else if (siz1 == SIZE_UNSPEC
2496 && opP->reg == PC
2497 && isvar (&opP->disp)
2498 && subs (&opP->disp) == NULL
2499#ifdef OBJ_ELF
2500 /* If the displacement needs pic
2501 relocation it cannot be relaxed. */
2502 && opP->disp.pic_reloc == pic_none
2503#endif
2504 )
2505 {
2506 /* The code in md_convert_frag_1 needs to be
2507 able to adjust nextword. Call frag_grow
2508 to ensure that we have enough space in
2509 the frag obstack to make all the bytes
2510 contiguous. */
2511 frag_grow (14);
8a104df9
KH		 2512 nextword += baseo & 0xff;
2513 addword (nextword);
bd17c2c3
AM		 2514 add_frag (adds (&opP->disp),
2515 SEXT (offs (&opP->disp)),
8a104df9 2516 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2517
2518 break;
8a104df9 2519 }
252b5132
RH		 2520 }
2521 }
2522 else
2523 {
36759679 2524 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2525 if (opP->index.reg >= ZDATA0
2526 && opP->index.reg <= ZDATA7)
2527 nextword |= (opP->index.reg - ZDATA0) << 12;
2528 else if (opP->index.reg >= ZADDR0
2529 || opP->index.reg <= ZADDR7)
2530 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2531 }
2532
2533 /* It isn't simple. */
2534
2535 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2536 || arch_coldfire_p (current_architecture))
252b5132
RH		 2537 opP->error =
2538 _("invalid operand mode for this architecture; needs 68020 or higher");
2539
2540 nextword |= 0x100;
2541 /* If the guy specified a width, we assume that it is
2542 wide enough. Maybe it isn't. If so, we lose. */
2543 switch (siz1)
2544 {
2545 case SIZE_UNSPEC:
2546 if (isvar (&opP->disp)
2547 ? m68k_rel32
2548 : ! issword (baseo))
2549 {
2550 siz1 = SIZE_LONG;
2551 nextword |= 0x30;
2552 }
2553 else if (! isvar (&opP->disp) && baseo == 0)
2554 nextword |= 0x10;
2555 else
2556 {
2557 nextword |= 0x20;
2558 siz1 = SIZE_WORD;
2559 }
2560 break;
2561 case SIZE_BYTE:
2562 as_warn (_(":b not permitted; defaulting to :w"));
2563 /* Fall through. */
2564 case SIZE_WORD:
2565 nextword |= 0x20;
2566 break;
2567 case SIZE_LONG:
2568 nextword |= 0x30;
2569 break;
2570 }
2571
67c1ffbe 2572 /* Figure out inner displacement stuff. */
252b5132
RH		 2573 if (opP->mode == POST || opP->mode == PRE)
2574 {
2575 if (cpu_of_arch (current_architecture) & cpu32)
2576 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2577 switch (siz2)
2578 {
2579 case SIZE_UNSPEC:
2580 if (isvar (&opP->odisp)
2581 ? m68k_rel32
2582 : ! issword (outro))
2583 {
2584 siz2 = SIZE_LONG;
2585 nextword |= 0x3;
2586 }
2587 else if (! isvar (&opP->odisp) && outro == 0)
2588 nextword |= 0x1;
2589 else
2590 {
2591 nextword |= 0x2;
2592 siz2 = SIZE_WORD;
2593 }
2594 break;
2595 case 1:
2596 as_warn (_(":b not permitted; defaulting to :w"));
2597 /* Fall through. */
2598 case 2:
2599 nextword |= 0x2;
2600 break;
2601 case 3:
2602 nextword |= 0x3;
2603 break;
2604 }
2605 if (opP->mode == POST
2606 && (nextword & 0x40) == 0)
2607 nextword |= 0x04;
2608 }
2609 addword (nextword);
2610
2611 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2612 {
2613 if (opP->reg == PC || opP->reg == ZPC)
2614 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2615 else
2616 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2617 }
2618 if (siz1 == SIZE_LONG)
2619 addword (baseo >> 16);
2620 if (siz1 != SIZE_UNSPEC)
2621 addword (baseo);
2622
2623 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2624 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2625 if (siz2 == SIZE_LONG)
2626 addword (outro >> 16);
2627 if (siz2 != SIZE_UNSPEC)
2628 addword (outro);
2629
2630 break;
2631
2632 case ABSL:
3e602632 2633 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2634 switch (opP->disp.size)
2635 {
2636 default:
2637 abort ();
2638 case SIZE_UNSPEC:
2639 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2640 {
2641 tmpreg = 0x38; /* 7.0 */
2642 addword (nextword);
2643 break;
2644 }
252b5132
RH		 2645 if (isvar (&opP->disp)
2646 && !subs (&opP->disp)
2647 && adds (&opP->disp)
2648#ifdef OBJ_ELF
2649 /* If the displacement needs pic relocation it
2650 cannot be relaxed. */
2651 && opP->disp.pic_reloc == pic_none
2652#endif
252b5132
RH		 2653 && !flag_long_jumps
2654 && !strchr ("~%&$?", s[0]))
2655 {
2656 tmpreg = 0x3A; /* 7.2 */
2657 add_frag (adds (&opP->disp),
bd17c2c3 2658 SEXT (offs (&opP->disp)),
151337e8 2659 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2660 break;
2661 }
36759679 2662 /* Fall through into long. */
252b5132
RH		 2663 case SIZE_LONG:
2664 if (isvar (&opP->disp))
2665 add_fix ('l', &opP->disp, 0, 0);
2666
2667 tmpreg = 0x39;/* 7.1 mode */
2668 addword (nextword >> 16);
2669 addword (nextword);
2670 break;
2671
2672 case SIZE_BYTE:
2673 as_bad (_("unsupported byte value; use a different suffix"));
2674 /* Fall through. */
36759679
NC		 2675
2676 case SIZE_WORD:
252b5132
RH		 2677 if (isvar (&opP->disp))
2678 add_fix ('w', &opP->disp, 0, 0);
2679
2680 tmpreg = 0x38;/* 7.0 mode */
2681 addword (nextword);
2682 break;
2683 }
2684 break;
2685 case CONTROL:
2686 case FPREG:
2687 default:
2688 as_bad (_("unknown/incorrect operand"));
bc805888 2689 /* abort (); */
252b5132 2690 }
fd99574b
NC		 2691
2692 /* If s[0] is '4', then this is for the mac instructions
2693 that can have a trailing_ampersand set. If so, set 0x100
2694 bit on tmpreg so install_gen_operand can check for it and
2695 set the appropriate bit (word2, bit 5). */
2696 if (s[0] == '4')
2697 {
2698 if (opP->trailing_ampersand)
2699 tmpreg |= 0x100;
2700 }
252b5132
RH		 2701 install_gen_operand (s[1], tmpreg);
2702 break;
2703
2704 case '#':
2705 case '^':
2706 switch (s[1])
2707 { /* JF: I hate floating point! */
2708 case 'j':
2709 tmpreg = 70;
2710 break;
2711 case '8':
2712 tmpreg = 20;
2713 break;
2714 case 'C':
2715 tmpreg = 50;
2716 break;
2717 case '3':
2718 default:
3e602632 2719 tmpreg = 90;
252b5132
RH		 2720 break;
2721 }
2722 tmpreg = get_num (&opP->disp, tmpreg);
2723 if (isvar (&opP->disp))
2724 add_fix (s[1], &opP->disp, 0, 0);
2725 switch (s[1])
2726 {
2727 case 'b': /* Danger: These do no check for
2728 certain types of overflow.
2729 user beware! */
2730 if (!isbyte (tmpreg))
2731 opP->error = _("out of range");
2732 insop (tmpreg, opcode);
2733 if (isvar (&opP->disp))
2734 the_ins.reloc[the_ins.nrel - 1].n =
2735 (opcode->m_codenum) * 2 + 1;
2736 break;
2737 case 'B':
2738 if (!issbyte (tmpreg))
2739 opP->error = _("out of range");
2740 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2741 if (isvar (&opP->disp))
2742 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2743 break;
2744 case 'w':
2745 if (!isword (tmpreg))
2746 opP->error = _("out of range");
2747 insop (tmpreg, opcode);
2748 if (isvar (&opP->disp))
2749 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2750 break;
2751 case 'W':
2752 if (!issword (tmpreg))
2753 opP->error = _("out of range");
2754 insop (tmpreg, opcode);
2755 if (isvar (&opP->disp))
2756 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2757 break;
2758 case 'l':
2759 /* Because of the way insop works, we put these two out
2760 backwards. */
2761 insop (tmpreg, opcode);
2762 insop (tmpreg >> 16, opcode);
2763 if (isvar (&opP->disp))
2764 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2765 break;
2766 case '3':
2767 tmpreg &= 0xFF;
2768 case '8':
2769 case 'C':
2770 case 'j':
2771 install_operand (s[1], tmpreg);
2772 break;
2773 default:
2774 abort ();
2775 }
2776 break;
2777
2778 case '+':
2779 case '-':
2780 case 'A':
2781 case 'a':
2782 install_operand (s[1], opP->reg - ADDR);
2783 break;
2784
2785 case 'B':
3e602632 2786 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2787 switch (s[1])
2788 {
2789 case 'B':
8390138c 2790 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2791 break;
2792 case 'W':
2793 add_fix ('w', &opP->disp, 1, 0);
2794 addword (0);
2795 break;
2796 case 'L':
2797 long_branch:
151337e8 2798 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2799 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2800 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2801 add_fix ('l', &opP->disp, 1, 0);
2802 addword (0);
2803 addword (0);
2804 break;
2805 case 'g':
36759679 2806 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2807 goto long_branch;
2808
2809#ifdef OBJ_ELF
2810 /* If the displacement needs pic relocation it cannot be
2811 relaxed. */
2812 if (opP->disp.pic_reloc != pic_none)
2813 goto long_branch;
2814#endif
252b5132 2815 /* This could either be a symbol, or an absolute
151337e8
NC		 2816 address. If it's an absolute address, turn it into
2817 an absolute jump right here and keep it out of the
2818 relaxer. */
2819 if (adds (&opP->disp) == 0)
2820 {
2821 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2822 the_ins.opcode[0] = 0x4EF9;
151337e8 2823 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2824 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2825 else /* jCC */
2826 {
2827 the_ins.opcode[0] ^= 0x0100;
2828 the_ins.opcode[0] |= 0x0006;
18566f55 2829 addword (0x4EF9);
151337e8
NC		 2830 }
2831 add_fix ('l', &opP->disp, 0, 0);
2832 addword (0);
2833 addword (0);
2834 break;
2835 }
2836
2837 /* Now we know it's going into the relaxer. Now figure
2838 out which mode. We try in this order of preference:
2839 long branch, absolute jump, byte/word branches only. */
2840 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2841 add_frag (adds (&opP->disp),
2842 SEXT (offs (&opP->disp)),
151337e8
NC		 2843 TAB (BRANCHBWL, SZ_UNDEF));
2844 else if (! flag_keep_pcrel)
2845 {
2846 if ((the_ins.opcode[0] == 0x6000)
2847 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2848 add_frag (adds (&opP->disp),
2849 SEXT (offs (&opP->disp)),
151337e8
NC		 2850 TAB (BRABSJUNC, SZ_UNDEF));
2851 else
bd17c2c3
AM		 2852 add_frag (adds (&opP->disp),
2853 SEXT (offs (&opP->disp)),
151337e8
NC		 2854 TAB (BRABSJCOND, SZ_UNDEF));
2855 }
252b5132 2856 else
bd17c2c3
AM		 2857 add_frag (adds (&opP->disp),
2858 SEXT (offs (&opP->disp)),
151337e8 2859 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2860 break;
2861 case 'w':
2862 if (isvar (&opP->disp))
2863 {
151337e8
NC		 2864 /* Check for DBcc instructions. We can relax them,
2865 but only if we have long branches and/or absolute
2866 jumps. */
2867 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2868 && (HAVE_LONG_BRANCH (current_architecture)
2869 || (! flag_keep_pcrel)))
252b5132 2870 {
151337e8 2871 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2872 add_frag (adds (&opP->disp),
2873 SEXT (offs (&opP->disp)),
151337e8
NC		 2874 TAB (DBCCLBR, SZ_UNDEF));
2875 else
bd17c2c3
AM		 2876 add_frag (adds (&opP->disp),
2877 SEXT (offs (&opP->disp)),
151337e8 2878 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2879 break;
2880 }
252b5132
RH		 2881 add_fix ('w', &opP->disp, 1, 0);
2882 }
2883 addword (0);
2884 break;
36759679 2885 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2886 add_fix ('l', &opP->disp, 1, 0);
2887 addword (0);
2888 addword (0);
2889 break;
36759679 2890 case 'c': /* Var size Coprocesssor branches. */
151337e8 2891 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2892 {
252b5132
RH		 2893 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2894 add_fix ('l', &opP->disp, 1, 0);
2895 addword (0);
2896 addword (0);
2897 }
151337e8 2898 else
bd17c2c3
AM		 2899 add_frag (adds (&opP->disp),
2900 SEXT (offs (&opP->disp)),
151337e8 2901 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2902 break;
2903 default:
2904 abort ();
2905 }
2906 break;
2907
36759679 2908 case 'C': /* Ignore it. */
252b5132
RH		 2909 break;
2910
36759679 2911 case 'd': /* JF this is a kludge. */
252b5132 2912 install_operand ('s', opP->reg - ADDR);
3e602632 2913 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2914 if (!issword (tmpreg))
2915 {
2916 as_warn (_("Expression out of range, using 0"));
2917 tmpreg = 0;
2918 }
2919 addword (tmpreg);
2920 break;
2921
2922 case 'D':
2923 install_operand (s[1], opP->reg - DATA);
2924 break;
2925
fd99574b
NC		 2926 case 'e': /* EMAC ACCx, reg/reg. */
2927 install_operand (s[1], opP->reg - ACC);
2928 break;
2929
36759679 2930 case 'E': /* Ignore it. */
6da466c7
ILT		 2931 break;
2932
252b5132
RH		 2933 case 'F':
2934 install_operand (s[1], opP->reg - FP0);
2935 break;
2936
fd99574b
NC		 2937 case 'g': /* EMAC ACCEXTx. */
2938 install_operand (s[1], opP->reg - ACCEXT01);
2939 break;
2940
36759679 2941 case 'G': /* Ignore it. */
6da466c7
ILT		 2942 case 'H':
2943 break;
2944
252b5132
RH		 2945 case 'I':
2946 tmpreg = opP->reg - COP0;
2947 install_operand (s[1], tmpreg);
2948 break;
2949
fd99574b
NC		 2950 case 'i': /* MAC/EMAC scale factor. */
2951 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2952 break;
2953
36759679 2954 case 'J': /* JF foo. */
252b5132
RH		 2955 switch (opP->reg)
2956 {
2957 case SFC:
2958 tmpreg = 0x000;
2959 break;
2960 case DFC:
2961 tmpreg = 0x001;
2962 break;
2963 case CACR:
2964 tmpreg = 0x002;
2965 break;
2966 case TC:
2967 tmpreg = 0x003;
2968 break;
3e602632 2969 case ACR0:
252b5132
RH		 2970 case ITT0:
2971 tmpreg = 0x004;
2972 break;
3e602632 2973 case ACR1:
252b5132
RH		 2974 case ITT1:
2975 tmpreg = 0x005;
2976 break;
3e602632 2977 case ACR2:
252b5132
RH		 2978 case DTT0:
2979 tmpreg = 0x006;
2980 break;
3e602632 2981 case ACR3:
252b5132
RH		 2982 case DTT1:
2983 tmpreg = 0x007;
2984 break;
2985 case BUSCR:
2986 tmpreg = 0x008;
2987 break;
2988
2989 case USP:
2990 tmpreg = 0x800;
2991 break;
2992 case VBR:
2993 tmpreg = 0x801;
2994 break;
2995 case CAAR:
2996 tmpreg = 0x802;
2997 break;
2998 case MSP:
2999 tmpreg = 0x803;
3000 break;
3001 case ISP:
3002 tmpreg = 0x804;
3003 break;
3004 case MMUSR:
3005 tmpreg = 0x805;
3006 break;
3007 case URP:
3008 tmpreg = 0x806;
3009 break;
3010 case SRP:
3011 tmpreg = 0x807;
3012 break;
3013 case PCR:
3014 tmpreg = 0x808;
3015 break;
3016 case ROMBAR:
3017 tmpreg = 0xC00;
3018 break;
3e602632
NC		 3019 case ROMBAR1:
3020 tmpreg = 0xC01;
3021 break;
3022 case FLASHBAR:
252b5132
RH		 3023 case RAMBAR0:
3024 tmpreg = 0xC04;
3025 break;
3e602632 3026 case RAMBAR:
252b5132
RH		 3027 case RAMBAR1:
3028 tmpreg = 0xC05;
3029 break;
3e602632
NC		 3030 case MPCR:
3031 tmpreg = 0xC0C;
3032 break;
3033 case EDRAMBAR:
3034 tmpreg = 0xC0D;
3035 break;
3036 case MBAR0:
e80e0390 3037 case MBAR2:
3e602632
NC		 3038 case SECMBAR:
3039 tmpreg = 0xC0E;
3040 break;
3041 case MBAR1:
252b5132
RH		 3042 case MBAR:
3043 tmpreg = 0xC0F;
3044 break;
3e602632
NC		 3045 case PCR1U0:
3046 tmpreg = 0xD02;
3047 break;
3048 case PCR1L0:
3049 tmpreg = 0xD03;
3050 break;
3051 case PCR2U0:
3052 tmpreg = 0xD04;
3053 break;
3054 case PCR2L0:
3055 tmpreg = 0xD05;
3056 break;
3057 case PCR3U0:
3058 tmpreg = 0xD06;
3059 break;
3060 case PCR3L0:
3061 tmpreg = 0xD07;
3062 break;
3063 case PCR1L1:
3064 tmpreg = 0xD0A;
3065 break;
3066 case PCR1U1:
3067 tmpreg = 0xD0B;
3068 break;
3069 case PCR2L1:
3070 tmpreg = 0xD0C;
3071 break;
3072 case PCR2U1:
3073 tmpreg = 0xD0D;
3074 break;
3075 case PCR3L1:
3076 tmpreg = 0xD0E;
3077 break;
3078 case PCR3U1:
3079 tmpreg = 0xD0F;
3080 break;
f7ec513b
KH		 3081 case CAC:
3082 tmpreg = 0xFFE;
3083 break;
3084 case MBB:
3085 tmpreg = 0xFFF;
3086 break;
252b5132
RH		 3087 default:
3088 abort ();
3089 }
3090 install_operand (s[1], tmpreg);
3091 break;
3092
3093 case 'k':
3094 tmpreg = get_num (&opP->disp, 55);
3095 install_operand (s[1], tmpreg & 0x7f);
3096 break;
3097
3098 case 'l':
3099 tmpreg = opP->mask;
3100 if (s[1] == 'w')
3101 {
3102 if (tmpreg & 0x7FF0000)
3103 as_bad (_("Floating point register in register list"));
3104 insop (reverse_16_bits (tmpreg), opcode);
3105 }
3106 else
3107 {
3108 if (tmpreg & 0x700FFFF)
3109 as_bad (_("Wrong register in floating-point reglist"));
3110 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3111 }
3112 break;
3113
3114 case 'L':
3115 tmpreg = opP->mask;
3116 if (s[1] == 'w')
3117 {
3118 if (tmpreg & 0x7FF0000)
3119 as_bad (_("Floating point register in register list"));
3120 insop (tmpreg, opcode);
3121 }
3122 else if (s[1] == '8')
3123 {
3124 if (tmpreg & 0x0FFFFFF)
3125 as_bad (_("incorrect register in reglist"));
3126 install_operand (s[1], tmpreg >> 24);
3127 }
3128 else
3129 {
3130 if (tmpreg & 0x700FFFF)
3131 as_bad (_("wrong register in floating-point reglist"));
3132 else
3133 install_operand (s[1], tmpreg >> 16);
3134 }
3135 break;
3136
3137 case 'M':
3138 install_operand (s[1], get_num (&opP->disp, 60));
3139 break;
3140
3141 case 'O':
3142 tmpreg = ((opP->mode == DREG)
8fce3f5e 3143 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3144 : (get_num (&opP->disp, 40) & 0x1F));
3145 install_operand (s[1], tmpreg);
3146 break;
3147
3148 case 'Q':
3149 tmpreg = get_num (&opP->disp, 10);
3150 if (tmpreg == 8)
3151 tmpreg = 0;
3152 install_operand (s[1], tmpreg);
3153 break;
3154
3155 case 'R':
3156 /* This depends on the fact that ADDR registers are eight
3157 more than their corresponding DATA regs, so the result
36759679 3158 will have the ADDR_REG bit set. */
252b5132
RH		 3159 install_operand (s[1], opP->reg - DATA);
3160 break;
3161
3162 case 'r':
3163 if (opP->mode == AINDR)
3164 install_operand (s[1], opP->reg - DATA);
3165 else
3166 install_operand (s[1], opP->index.reg - DATA);
3167 break;
3168
3169 case 's':
3170 if (opP->reg == FPI)
3171 tmpreg = 0x1;
3172 else if (opP->reg == FPS)
3173 tmpreg = 0x2;
3174 else if (opP->reg == FPC)
3175 tmpreg = 0x4;
3176 else
3177 abort ();
3178 install_operand (s[1], tmpreg);
3179 break;
3180
36759679 3181 case 'S': /* Ignore it. */
252b5132
RH		 3182 break;
3183
3184 case 'T':
3185 install_operand (s[1], get_num (&opP->disp, 30));
3186 break;
3187
36759679 3188 case 'U': /* Ignore it. */
252b5132
RH		 3189 break;
3190
3191 case 'c':
3192 switch (opP->reg)
3193 {
3194 case NC:
3195 tmpreg = 0;
3196 break;
3197 case DC:
3198 tmpreg = 1;
3199 break;
3200 case IC:
3201 tmpreg = 2;
3202 break;
3203 case BC:
3204 tmpreg = 3;
3205 break;
3206 default:
3207 as_fatal (_("failed sanity check"));
36759679 3208 } /* switch on cache token. */
252b5132
RH		 3209 install_operand (s[1], tmpreg);
3210 break;
3211#ifndef NO_68851
92774660 3212 /* JF: These are out of order, I fear. */
252b5132
RH		 3213 case 'f':
3214 switch (opP->reg)
3215 {
3216 case SFC:
3217 tmpreg = 0;
3218 break;
3219 case DFC:
3220 tmpreg = 1;
3221 break;
3222 default:
3223 abort ();
3224 }
3225 install_operand (s[1], tmpreg);
3226 break;
3227
3228 case '0':
3229 case '1':
3230 case '2':
3231 switch (opP->reg)
3232 {
3233 case TC:
3234 tmpreg = 0;
3235 break;
3236 case CAL:
3237 tmpreg = 4;
3238 break;
3239 case VAL:
3240 tmpreg = 5;
3241 break;
3242 case SCC:
3243 tmpreg = 6;
3244 break;
3245 case AC:
3246 tmpreg = 7;
3247 break;
3248 default:
3249 abort ();
3250 }
3251 install_operand (s[1], tmpreg);
3252 break;
3253
3254 case 'V':
3255 if (opP->reg == VAL)
3256 break;
3257 abort ();
3258
3259 case 'W':
3260 switch (opP->reg)
3261 {
3262 case DRP:
3263 tmpreg = 1;
3264 break;
3265 case SRP:
3266 tmpreg = 2;
3267 break;
3268 case CRP:
3269 tmpreg = 3;
3270 break;
3271 default:
3272 abort ();
3273 }
3274 install_operand (s[1], tmpreg);
3275 break;
3276
3277 case 'X':
3278 switch (opP->reg)
3279 {
3280 case BAD:
3281 case BAD + 1:
3282 case BAD + 2:
3283 case BAD + 3:
3284 case BAD + 4:
3285 case BAD + 5:
3286 case BAD + 6:
3287 case BAD + 7:
3288 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3289 break;
3290
3291 case BAC:
3292 case BAC + 1:
3293 case BAC + 2:
3294 case BAC + 3:
3295 case BAC + 4:
3296 case BAC + 5:
3297 case BAC + 6:
3298 case BAC + 7:
3299 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3300 break;
3301
3302 default:
3303 abort ();
3304 }
3305 install_operand (s[1], tmpreg);
3306 break;
3307 case 'Y':
3308 know (opP->reg == PSR);
3309 break;
3310 case 'Z':
3311 know (opP->reg == PCSR);
3312 break;
3313#endif /* m68851 */
3314 case '3':
3315 switch (opP->reg)
3316 {
3317 case TT0:
3318 tmpreg = 2;
3319 break;
3320 case TT1:
3321 tmpreg = 3;
3322 break;
3323 default:
3324 abort ();
3325 }
3326 install_operand (s[1], tmpreg);
3327 break;
3328 case 't':
3329 tmpreg = get_num (&opP->disp, 20);
3330 install_operand (s[1], tmpreg);
3331 break;
36759679 3332 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3333 if (isvar (&opP->disp))
3334 add_fix ('l', &opP->disp, 0, 0);
3e602632 3335 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3336 addword (tmpreg >> 16);
3337 addword (tmpreg & 0xFFFF);
3338 break;
6da466c7
ILT		 3339 case 'u':
3340 install_operand (s[1], opP->reg - DATA0L);
3341 opP->reg -= (DATA0L);
36759679 3342 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3343 break;
3e602632
NC		 3344 case 'x':
3345 tmpreg = get_num (&opP->disp, 80);
3346 if (tmpreg == -1)
3347 tmpreg = 0;
3348 install_operand (s[1], tmpreg);
3349 break;
252b5132
RH		 3350 default:
3351 abort ();
3352 }
3353 }
3354
3355 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3356 instruction, ready to be emitted. . . */
252b5132
RH		 3357}
3358
3359static int
31302357 3360reverse_16_bits (int in)
252b5132
RH		 3361{
3362 int out = 0;
3363 int n;
3364
3365 static int mask[16] =
3366 {
3367 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3368 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3369 };
3370 for (n = 0; n < 16; n++)
3371 {
3372 if (in & mask[n])
3373 out |= mask[15 - n];
3374 }
3375 return out;
3376} /* reverse_16_bits() */
3377
3378static int
31302357 3379reverse_8_bits (int in)
252b5132
RH		 3380{
3381 int out = 0;
3382 int n;
3383
3384 static int mask[8] =
3385 {
3386 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3387 };
3388
3389 for (n = 0; n < 8; n++)
3390 {
3391 if (in & mask[n])
3392 out |= mask[7 - n];
3393 }
3394 return out;
3395} /* reverse_8_bits() */
3396
3397/* Cause an extra frag to be generated here, inserting up to 10 bytes
3398 (that value is chosen in the frag_var call in md_assemble). TYPE
3399 is the subtype of the frag to be generated; its primary type is
3400 rs_machine_dependent.
3401
3402 The TYPE parameter is also used by md_convert_frag_1 and
3403 md_estimate_size_before_relax. The appropriate type of fixup will
3404 be emitted by md_convert_frag_1.
3405
3406 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3407static void
31302357 3408install_operand (int mode, int val)
252b5132
RH		 3409{
3410 switch (mode)
3411 {
3412 case 's':
36759679 3413 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3414 break;
3415 case 'd':
3416 the_ins.opcode[0] |= val << 9;
3417 break;
3418 case '1':
3419 the_ins.opcode[1] |= val << 12;
3420 break;
3421 case '2':
3422 the_ins.opcode[1] |= val << 6;
3423 break;
3424 case '3':
3425 the_ins.opcode[1] |= val;
3426 break;
3427 case '4':
3428 the_ins.opcode[2] |= val << 12;
3429 break;
3430 case '5':
3431 the_ins.opcode[2] |= val << 6;
3432 break;
3433 case '6':
3434 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3435 three words long! */
3436 the_ins.numo++;
3437 the_ins.opcode[2] |= val;
3438 break;
3439 case '7':
3440 the_ins.opcode[1] |= val << 7;
3441 break;
3442 case '8':
3443 the_ins.opcode[1] |= val << 10;
3444 break;
3445#ifndef NO_68851
3446 case '9':
3447 the_ins.opcode[1] |= val << 5;
3448 break;
3449#endif
3450
3451 case 't':
3452 the_ins.opcode[1] |= (val << 10) | (val << 7);
3453 break;
3454 case 'D':
3455 the_ins.opcode[1] |= (val << 12) | val;
3456 break;
3457 case 'g':
3458 the_ins.opcode[0] |= val = 0xff;
3459 break;
3460 case 'i':
3461 the_ins.opcode[0] |= val << 9;
3462 break;
3463 case 'C':
3464 the_ins.opcode[1] |= val;
3465 break;
3466 case 'j':
3467 the_ins.opcode[1] |= val;
36759679 3468 the_ins.numo++; /* What a hack. */
252b5132
RH		 3469 break;
3470 case 'k':
3471 the_ins.opcode[1] |= val << 4;
3472 break;
3473 case 'b':
3474 case 'w':
3475 case 'W':
3476 case 'l':
3477 break;
3478 case 'e':
3479 the_ins.opcode[0] |= (val << 6);
3480 break;
3481 case 'L':
3482 the_ins.opcode[1] = (val >> 16);
3483 the_ins.opcode[2] = val & 0xffff;
3484 break;
6da466c7
ILT		 3485 case 'm':
3486 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3487 the_ins.opcode[0] |= ((val & 0x7) << 9);
3488 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3489 break;
fd99574b 3490 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3491 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3492 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3493 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3494 break;
fd99574b 3495 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3496 the_ins.opcode[1] |= val << 12;
3497 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3498 break;
fd99574b 3499 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3500 the_ins.opcode[0] |= (val & 0xF);
3501 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3502 break;
fd99574b 3503 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3504 the_ins.opcode[1] |= (val & 0xF);
3505 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3506 break;
3507 case 'h':
3508 the_ins.opcode[1] |= ((val != 1) << 10);
3509 break;
fd99574b
NC		 3510 case 'F':
3511 the_ins.opcode[0] |= ((val & 0x3) << 9);
3512 break;
3513 case 'f':
3514 the_ins.opcode[0] |= ((val & 0x3) << 0);
3515 break;
be8c092b 3516 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3517 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3518 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3519 break;
be8c092b 3520 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3521 the_ins.opcode[0] |= ((val & 0x1) << 7);
3522 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3523 break;
3524 case 'I':
3525 the_ins.opcode[1] |= ((val & 0x3) << 9);
3526 break;
3527 case ']':
3528 the_ins.opcode[0] |= (val & 0x1) <<10;
3529 break;
252b5132
RH		 3530 case 'c':
3531 default:
3532 as_fatal (_("failed sanity check."));
3533 }
6b6e92f4 3534}
252b5132
RH		 3535
3536static void
31302357 3537install_gen_operand (int mode, int val)
252b5132
RH		 3538{
3539 switch (mode)
3540 {
fd99574b
NC		 3541 case '/': /* Special for mask loads for mac/msac insns with
3542 possible mask; trailing_ampersend set in bit 8. */
3543 the_ins.opcode[0] |= (val & 0x3f);
3544 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3545 break;
252b5132
RH		 3546 case 's':
3547 the_ins.opcode[0] |= val;
3548 break;
3549 case 'd':
3550 /* This is a kludge!!! */
3551 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3552 break;
3553 case 'b':
3554 case 'w':
3555 case 'l':
3556 case 'f':
3557 case 'F':
3558 case 'x':
3559 case 'p':
3560 the_ins.opcode[0] |= val;
3561 break;
36759679 3562 /* more stuff goes here. */
252b5132
RH		 3563 default:
3564 as_fatal (_("failed sanity check."));
3565 }
6b6e92f4 3566}
252b5132 3567
6b6e92f4
NC		 3568/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3569 then deal with the bitfield hack. */
252b5132
RH		 3570
3571static char *
31302357 3572crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3573{
3574 register int parens;
3575 register int c;
3576 register char *beg_str;
3577 int inquote = 0;
3578
3579 if (!str)
3580 {
3581 return str;
3582 }
3583 beg_str = str;
3584 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3585 {
3586 if (! inquote)
3587 {
3588 if (*str == '(')
3589 parens++;
3590 else if (*str == ')')
3591 {
3592 if (!parens)
36759679 3593 { /* ERROR. */
252b5132
RH		 3594 opP->error = _("Extra )");
3595 return str;
3596 }
3597 --parens;
3598 }
3599 }
3600 if (flag_mri && *str == '\'')
3601 inquote = ! inquote;
3602 }
3603 if (!*str && parens)
36759679 3604 { /* ERROR. */
252b5132
RH		 3605 opP->error = _("Missing )");
3606 return str;
3607 }
3608 c = *str;
3609 *str = '\0';
3610 if (m68k_ip_op (beg_str, opP) != 0)
3611 {
3612 *str = c;
3613 return str;
3614 }
3615 *str = c;
3616 if (c == '}')
36759679 3617 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3618 if (c)
3619 {
3620 c = *++str;
3621 if (!c)
3622 as_bad (_("Missing operand"));
3623 }
3624
3625 /* Detect MRI REG symbols and convert them to REGLSTs. */
3626 if (opP->mode == CONTROL && (int)opP->reg < 0)
3627 {
3628 opP->mode = REGLST;
3629 opP->mask = ~(int)opP->reg;
3630 opP->reg = 0;
3631 }
3632
3633 return str;
3634}
3635
3636/* This is the guts of the machine-dependent assembler. STR points to a
3637 machine dependent instruction. This function is supposed to emit
3638 the frags/bytes it assembles to.
3639 */
3640
3641static void
31302357 3642insert_reg (const char *regname, int regnum)
252b5132
RH		 3643{
3644 char buf[100];
3645 int i;
3646
3647#ifdef REGISTER_PREFIX
3648 if (!flag_reg_prefix_optional)
3649 {
3650 buf[0] = REGISTER_PREFIX;
3651 strcpy (buf + 1, regname);
3652 regname = buf;
3653 }
3654#endif
3655
3656 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3657 &zero_address_frag));
3658
3659 for (i = 0; regname[i]; i++)
3882b010 3660 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3661 buf[i] = '\0';
3662
3663 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3664 &zero_address_frag));
3665}
3666
3667struct init_entry
3668 {
3669 const char *name;
3670 int number;
3671 };
3672
3673static const struct init_entry init_table[] =
3674{
3675 { "d0", DATA0 },
3676 { "d1", DATA1 },
3677 { "d2", DATA2 },
3678 { "d3", DATA3 },
3679 { "d4", DATA4 },
3680 { "d5", DATA5 },
3681 { "d6", DATA6 },
3682 { "d7", DATA7 },
3683 { "a0", ADDR0 },
3684 { "a1", ADDR1 },
3685 { "a2", ADDR2 },
3686 { "a3", ADDR3 },
3687 { "a4", ADDR4 },
3688 { "a5", ADDR5 },
3689 { "a6", ADDR6 },
3690 { "fp", ADDR6 },
3691 { "a7", ADDR7 },
3692 { "sp", ADDR7 },
3693 { "ssp", ADDR7 },
3694 { "fp0", FP0 },
3695 { "fp1", FP1 },
3696 { "fp2", FP2 },
3697 { "fp3", FP3 },
3698 { "fp4", FP4 },
3699 { "fp5", FP5 },
3700 { "fp6", FP6 },
3701 { "fp7", FP7 },
3702 { "fpi", FPI },
3703 { "fpiar", FPI },
3704 { "fpc", FPI },
3705 { "fps", FPS },
3706 { "fpsr", FPS },
3707 { "fpc", FPC },
3708 { "fpcr", FPC },
3709 { "control", FPC },
3710 { "status", FPS },
3711 { "iaddr", FPI },
3712
3713 { "cop0", COP0 },
3714 { "cop1", COP1 },
3715 { "cop2", COP2 },
3716 { "cop3", COP3 },
3717 { "cop4", COP4 },
3718 { "cop5", COP5 },
3719 { "cop6", COP6 },
3720 { "cop7", COP7 },
3721 { "pc", PC },
3722 { "zpc", ZPC },
3723 { "sr", SR },
3724
3725 { "ccr", CCR },
3726 { "cc", CCR },
3727
6da466c7 3728 { "acc", ACC },
fd99574b
NC		 3729 { "acc0", ACC },
3730 { "acc1", ACC1 },
3731 { "acc2", ACC2 },
3732 { "acc3", ACC3 },
3733 { "accext01", ACCEXT01 },
3734 { "accext23", ACCEXT23 },
6da466c7
ILT		 3735 { "macsr", MACSR },
3736 { "mask", MASK },
3737
36759679
NC		 3738 /* Control registers. */
3739 { "sfc", SFC }, /* Source Function Code. */
252b5132 3740 { "sfcr", SFC },
36759679 3741 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3742 { "dfcr", DFC },
36759679
NC		 3743 { "cacr", CACR }, /* Cache Control Register. */
3744 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3745
36759679
NC		 3746 { "usp", USP }, /* User Stack Pointer. */
3747 { "vbr", VBR }, /* Vector Base Register. */
3748 { "msp", MSP }, /* Master Stack Pointer. */
3749 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3750
36759679
NC		 3751 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3752 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3753 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3754 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3755
3756 /* 68ec040 versions of same */
36759679
NC		 3757 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3758 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3759 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3760 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3761
3762 /* mcf5200 versions of same. The ColdFire programmer's reference
3763 manual indicated that the order is 2,3,0,1, but Ken Rose
3764 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3765 { "acr0", ACR0 }, /* Access Control Unit 0. */
3766 { "acr1", ACR1 }, /* Access Control Unit 1. */
3767 { "acr2", ACR2 }, /* Access Control Unit 2. */
3768 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3769
36759679 3770 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3771 { "tcr", TC },
3772
36759679
NC		 3773 { "mmusr", MMUSR }, /* MMU Status Register. */
3774 { "srp", SRP }, /* User Root Pointer. */
3775 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3776
3777 { "buscr", BUSCR },
3778 { "pcr", PCR },
3779
36759679
NC		 3780 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3781 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3782 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3783 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3784
3785 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3786 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3787 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3788 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3789 { "mpcr", MPCR }, /* mcfv4e registers. */
3790 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3791 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3792 { "asid", TC }, /* mcfv4e registers. */
3793 { "mmubar", BUSCR }, /* mcfv4e registers. */
3794 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3795 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3796 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3797 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3798 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3799 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3800 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3801 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3802 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3803 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3804 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3805 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3806
3807 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3808 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3809
3810 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b
KH		 3811
3812 { "cac", CAC }, /* fido registers. */
3813 { "mbb", MBB }, /* fido registers. */
36759679 3814 /* End of control registers. */
252b5132
RH		 3815
3816 { "ac", AC },
3817 { "bc", BC },
3818 { "cal", CAL },
3819 { "crp", CRP },
3820 { "drp", DRP },
3821 { "pcsr", PCSR },
3822 { "psr", PSR },
3823 { "scc", SCC },
3824 { "val", VAL },
3825 { "bad0", BAD0 },
3826 { "bad1", BAD1 },
3827 { "bad2", BAD2 },
3828 { "bad3", BAD3 },
3829 { "bad4", BAD4 },
3830 { "bad5", BAD5 },
3831 { "bad6", BAD6 },
3832 { "bad7", BAD7 },
3833 { "bac0", BAC0 },
3834 { "bac1", BAC1 },
3835 { "bac2", BAC2 },
3836 { "bac3", BAC3 },
3837 { "bac4", BAC4 },
3838 { "bac5", BAC5 },
3839 { "bac6", BAC6 },
3840 { "bac7", BAC7 },
3841
3842 { "ic", IC },
3843 { "dc", DC },
3844 { "nc", NC },
3845
3846 { "tt0", TT0 },
3847 { "tt1", TT1 },
36759679 3848 /* 68ec030 versions of same. */
252b5132
RH		 3849 { "ac0", TT0 },
3850 { "ac1", TT1 },
36759679 3851 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3852 { "acusr", PSR },
3853
3854 /* Suppressed data and address registers. */
3855 { "zd0", ZDATA0 },
3856 { "zd1", ZDATA1 },
3857 { "zd2", ZDATA2 },
3858 { "zd3", ZDATA3 },
3859 { "zd4", ZDATA4 },
3860 { "zd5", ZDATA5 },
3861 { "zd6", ZDATA6 },
3862 { "zd7", ZDATA7 },
3863 { "za0", ZADDR0 },
3864 { "za1", ZADDR1 },
3865 { "za2", ZADDR2 },
3866 { "za3", ZADDR3 },
3867 { "za4", ZADDR4 },
3868 { "za5", ZADDR5 },
3869 { "za6", ZADDR6 },
3870 { "za7", ZADDR7 },
3871
92774660 3872 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3873 { "d0l", DATA0L },
3874 { "d1l", DATA1L },
3875 { "d2l", DATA2L },
3876 { "d3l", DATA3L },
3877 { "d4l", DATA4L },
3878 { "d5l", DATA5L },
3879 { "d6l", DATA6L },
3880 { "d7l", DATA7L },
3881
3882 { "a0l", ADDR0L },
3883 { "a1l", ADDR1L },
3884 { "a2l", ADDR2L },
3885 { "a3l", ADDR3L },
3886 { "a4l", ADDR4L },
3887 { "a5l", ADDR5L },
3888 { "a6l", ADDR6L },
3889 { "a7l", ADDR7L },
3890
3891 { "d0u", DATA0U },
3892 { "d1u", DATA1U },
3893 { "d2u", DATA2U },
3894 { "d3u", DATA3U },
3895 { "d4u", DATA4U },
3896 { "d5u", DATA5U },
3897 { "d6u", DATA6U },
3898 { "d7u", DATA7U },
3899
3900 { "a0u", ADDR0U },
3901 { "a1u", ADDR1U },
3902 { "a2u", ADDR2U },
3903 { "a3u", ADDR3U },
3904 { "a4u", ADDR4U },
3905 { "a5u", ADDR5U },
3906 { "a6u", ADDR6U },
3907 { "a7u", ADDR7U },
3908
252b5132
RH		 3909 { 0, 0 }
3910};
3911
3912static void
31302357 3913init_regtable (void)
252b5132
RH		 3914{
3915 int i;
3916 for (i = 0; init_table[i].name; i++)
3917 insert_reg (init_table[i].name, init_table[i].number);
3918}
3919
252b5132 3920void
31302357 3921md_assemble (char *str)
252b5132
RH		 3922{
3923 const char *er;
3924 short *fromP;
3925 char *toP = NULL;
3926 int m, n = 0;
3927 char *to_beg_P;
3928 int shorts_this_frag;
3929 fixS *fixP;
3930
266abb8f
NS		 3931 if (!selected_cpu && !selected_arch)
3932 {
3933 /* We've not selected an architecture yet. Set the default
3934 now. We do this lazily so that an initial .cpu or .arch directive
3935 can specify. */
3936 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3937 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3938 }
3939 if (!initialized)
3940 m68k_init_arch ();
3941
252b5132
RH		 3942 /* In MRI mode, the instruction and operands are separated by a
3943 space. Anything following the operands is a comment. The label
3944 has already been removed. */
3945 if (flag_mri)
3946 {
3947 char *s;
3948 int fields = 0;
3949 int infield = 0;
3950 int inquote = 0;
3951
3952 for (s = str; *s != '\0'; s++)
3953 {
3954 if ((*s == ' ' || *s == '\t') && ! inquote)
3955 {
3956 if (infield)
3957 {
3958 ++fields;
3959 if (fields >= 2)
3960 {
3961 *s = '\0';
3962 break;
3963 }
3964 infield = 0;
3965 }
3966 }
3967 else
3968 {
3969 if (! infield)
3970 infield = 1;
3971 if (*s == '\'')
3972 inquote = ! inquote;
3973 }
3974 }
3975 }
3976
31302357 3977 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 3978 m68k_ip (str);
3979 er = the_ins.error;
3980 if (!er)
3981 {
3982 for (n = 0; n < the_ins.numargs; n++)
3983 if (the_ins.operands[n].error)
3984 {
3985 er = the_ins.operands[n].error;
3986 break;
3987 }
3988 }
3989 if (er)
3990 {
3991 as_bad (_("%s -- statement `%s' ignored"), er, str);
3992 return;
3993 }
3994
3995 /* If there is a current label, record that it marks an instruction. */
3996 if (current_label != NULL)
3997 {
3998 current_label->text = 1;
3999 current_label = NULL;
4000 }
4001
f27a3839
AS		 4002#ifdef OBJ_ELF
4003 /* Tie dwarf2 debug info to the address at the start of the insn. */
4004 dwarf2_emit_insn (0);
4005#endif
4006
252b5132
RH		 4007 if (the_ins.nfrag == 0)
4008 {
36759679 4009 /* No frag hacking involved; just put it out. */
252b5132
RH		 4010 toP = frag_more (2 * the_ins.numo);
4011 fromP = &the_ins.opcode[0];
4012 for (m = the_ins.numo; m; --m)
4013 {
4014 md_number_to_chars (toP, (long) (*fromP), 2);
4015 toP += 2;
4016 fromP++;
4017 }
36759679 4018 /* Put out symbol-dependent info. */
252b5132
RH		 4019 for (m = 0; m < the_ins.nrel; m++)
4020 {
4021 switch (the_ins.reloc[m].wid)
4022 {
4023 case 'B':
4024 n = 1;
4025 break;
4026 case 'b':
4027 n = 1;
4028 break;
4029 case '3':
4030 n = 1;
4031 break;
4032 case 'w':
4033 case 'W':
4034 n = 2;
4035 break;
4036 case 'l':
4037 n = 4;
4038 break;
4039 default:
4040 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4041 the_ins.reloc[m].wid);
4042 }
4043
4044 fixP = fix_new_exp (frag_now,
4045 ((toP - frag_now->fr_literal)
4046 - the_ins.numo * 2 + the_ins.reloc[m].n),
4047 n,
4048 &the_ins.reloc[m].exp,
4049 the_ins.reloc[m].pcrel,
4050 get_reloc_code (n, the_ins.reloc[m].pcrel,
4051 the_ins.reloc[m].pic_reloc));
4052 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4053 if (the_ins.reloc[m].wid == 'B')
4054 fixP->fx_signed = 1;
4055 }
4056 return;
4057 }
4058
36759679 4059 /* There's some frag hacking. */
fbe572f9
AM		 4060 {
4061 /* Calculate the max frag size. */
4062 int wid;
4063
4064 wid = 2 * the_ins.fragb[0].fragoff;
4065 for (n = 1; n < the_ins.nfrag; n++)
4066 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4067 /* frag_var part. */
4068 wid += 10;
4069 /* Make sure the whole insn fits in one chunk, in particular that
4070 the var part is attached, as we access one byte before the
4071 variable frag for byte branches. */
4072 frag_grow (wid);
4073 }
4074
252b5132
RH		 4075 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4076 {
4077 int wid;
4078
4079 if (n == 0)
4080 wid = 2 * the_ins.fragb[n].fragoff;
4081 else
4082 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4083 toP = frag_more (wid);
4084 to_beg_P = toP;
4085 shorts_this_frag = 0;
4086 for (m = wid / 2; m; --m)
4087 {
4088 md_number_to_chars (toP, (long) (*fromP), 2);
4089 toP += 2;
4090 fromP++;
4091 shorts_this_frag++;
4092 }
4093 for (m = 0; m < the_ins.nrel; m++)
4094 {
4095 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4096 {
4097 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4098 break;
4099 }
4100 wid = the_ins.reloc[m].wid;
4101 if (wid == 0)
4102 continue;
4103 the_ins.reloc[m].wid = 0;
4104 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4105
4106 fixP = fix_new_exp (frag_now,
4107 ((toP - frag_now->fr_literal)
4108 - the_ins.numo * 2 + the_ins.reloc[m].n),
4109 wid,
4110 &the_ins.reloc[m].exp,
4111 the_ins.reloc[m].pcrel,
4112 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4113 the_ins.reloc[m].pic_reloc));
4114 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4115 }
4116 (void) frag_var (rs_machine_dependent, 10, 0,
4117 (relax_substateT) (the_ins.fragb[n].fragty),
4118 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4119 }
4120 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4121 shorts_this_frag = 0;
4122 if (n)
4123 {
055d1eb0 4124 toP = frag_more (n * 2);
252b5132
RH		 4125 while (n--)
4126 {
4127 md_number_to_chars (toP, (long) (*fromP), 2);
4128 toP += 2;
4129 fromP++;
4130 shorts_this_frag++;
4131 }
4132 }
4133 for (m = 0; m < the_ins.nrel; m++)
4134 {
4135 int wid;
4136
4137 wid = the_ins.reloc[m].wid;
4138 if (wid == 0)
4139 continue;
4140 the_ins.reloc[m].wid = 0;
4141 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4142
4143 fixP = fix_new_exp (frag_now,
4144 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4145 - shorts_this_frag * 2),
4146 wid,
4147 &the_ins.reloc[m].exp,
4148 the_ins.reloc[m].pcrel,
4149 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4150 the_ins.reloc[m].pic_reloc));
4151 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4152 }
4153}
4154
60fed2d3
NC		 4155/* Comparison function used by qsort to rank the opcode entries by name. */
4156
4157static int
4158m68k_compare_opcode (const void * v1, const void * v2)
4159{
4160 struct m68k_opcode * op1, * op2;
4161 int ret;
4162
03b13e59
NC		 4163 if (v1 == v2)
4164 return 0;
4165
60fed2d3
NC		 4166 op1 = *(struct m68k_opcode **) v1;
4167 op2 = *(struct m68k_opcode **) v2;
4168
4169 /* Compare the two names. If different, return the comparison.
4170 If the same, return the order they are in the opcode table. */
4171 ret = strcmp (op1->name, op2->name);
4172 if (ret)
4173 return ret;
4174 if (op1 < op2)
4175 return -1;
03b13e59 4176 return 1;
60fed2d3
NC		 4177}
4178
252b5132 4179void
60fed2d3 4180md_begin (void)
252b5132 4181{
60fed2d3
NC		 4182 const struct m68k_opcode *ins;
4183 struct m68k_incant *hack, *slak;
4184 const char *retval = 0; /* Empty string, or error msg text. */
4185 int i;
4186
4187 /* Set up hash tables with 68000 instructions.
4188 similar to what the vax assembler does. */
252b5132
RH		 4189 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4190 a copy of it at runtime, adding in the information we want but isn't
4191 there. I think it'd be better to have an awk script hack the table
4192 at compile time. Or even just xstr the table and use it as-is. But
4193 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4194 names. */
4195
252b5132
RH		 4196 if (flag_mri)
4197 {
4198 flag_reg_prefix_optional = 1;
4199 m68k_abspcadd = 1;
4200 if (! m68k_rel32_from_cmdline)
4201 m68k_rel32 = 0;
4202 }
4203
60fed2d3
NC		 4204 /* First sort the opcode table into alphabetical order to seperate
4205 the order that the assembler wants to see the opcodes from the
4206 order that the disassembler wants to see them. */
4207 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4208 if (!m68k_sorted_opcodes)
4209 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4210 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4211
4212 for (i = m68k_numopcodes; i--;)
4213 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4214
4215 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4216 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4217
252b5132
RH		 4218 op_hash = hash_new ();
4219
4220 obstack_begin (&robyn, 4000);
4221 for (i = 0; i < m68k_numopcodes; i++)
4222 {
4223 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4224 do
4225 {
60fed2d3
NC		 4226 ins = m68k_sorted_opcodes[i];
4227
4228 /* We *could* ignore insns that don't match our
4229 arch here by just leaving them out of the hash. */
252b5132
RH		 4230 slak->m_operands = ins->args;
4231 slak->m_opnum = strlen (slak->m_operands) / 2;
4232 slak->m_arch = ins->arch;
4233 slak->m_opcode = ins->opcode;
36759679 4234 /* This is kludgey. */
252b5132
RH		 4235 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4236 if (i + 1 != m68k_numopcodes
60fed2d3 4237 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4238 {
60fed2d3 4239 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4240 i++;
4241 }
4242 else
4243 slak->m_next = 0;
4244 slak = slak->m_next;
4245 }
4246 while (slak);
4247
4248 retval = hash_insert (op_hash, ins->name, (char *) hack);
4249 if (retval)
4250 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4251 }
4252
4253 for (i = 0; i < m68k_numaliases; i++)
4254 {
4255 const char *name = m68k_opcode_aliases[i].primary;
4256 const char *alias = m68k_opcode_aliases[i].alias;
4257 PTR val = hash_find (op_hash, name);
60fed2d3 4258
252b5132
RH		 4259 if (!val)
4260 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4261 retval = hash_insert (op_hash, alias, val);
4262 if (retval)
4263 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4264 }
4265
4266 /* In MRI mode, all unsized branches are variable sized. Normally,
4267 they are word sized. */
4268 if (flag_mri)
4269 {
4270 static struct m68k_opcode_alias mri_aliases[] =
4271 {
4272 { "bhi", "jhi", },
4273 { "bls", "jls", },
4274 { "bcc", "jcc", },
4275 { "bcs", "jcs", },
4276 { "bne", "jne", },
4277 { "beq", "jeq", },
4278 { "bvc", "jvc", },
4279 { "bvs", "jvs", },
4280 { "bpl", "jpl", },
4281 { "bmi", "jmi", },
4282 { "bge", "jge", },
4283 { "blt", "jlt", },
4284 { "bgt", "jgt", },
4285 { "ble", "jle", },
4286 { "bra", "jra", },
4287 { "bsr", "jbsr", },
4288 };
4289
8fce3f5e
AM		 4290 for (i = 0;
4291 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4292 i++)
252b5132
RH		 4293 {
4294 const char *name = mri_aliases[i].primary;
4295 const char *alias = mri_aliases[i].alias;
4296 PTR val = hash_find (op_hash, name);
60fed2d3 4297
252b5132
RH		 4298 if (!val)
4299 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4300 retval = hash_jam (op_hash, alias, val);
4301 if (retval)
4302 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4303 }
4304 }
4305
8fce3f5e 4306 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4307 {
4308 notend_table[i] = 0;
4309 alt_notend_table[i] = 0;
4310 }
60fed2d3 4311
252b5132
RH		 4312 notend_table[','] = 1;
4313 notend_table['{'] = 1;
4314 notend_table['}'] = 1;
4315 alt_notend_table['a'] = 1;
4316 alt_notend_table['A'] = 1;
4317 alt_notend_table['d'] = 1;
4318 alt_notend_table['D'] = 1;
4319 alt_notend_table['#'] = 1;
4320 alt_notend_table['&'] = 1;
4321 alt_notend_table['f'] = 1;
4322 alt_notend_table['F'] = 1;
4323#ifdef REGISTER_PREFIX
4324 alt_notend_table[REGISTER_PREFIX] = 1;
4325#endif
4326
4327 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4328 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4329 alt_notend_table['('] = 1;
4330
4331 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4332 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4333 alt_notend_table['@'] = 1;
4334
4335 /* We need to put digits in alt_notend_table to handle
60fed2d3 4336 bfextu %d0{24:1},%d0 */
252b5132
RH		 4337 alt_notend_table['0'] = 1;
4338 alt_notend_table['1'] = 1;
4339 alt_notend_table['2'] = 1;
4340 alt_notend_table['3'] = 1;
4341 alt_notend_table['4'] = 1;
4342 alt_notend_table['5'] = 1;
4343 alt_notend_table['6'] = 1;
4344 alt_notend_table['7'] = 1;
4345 alt_notend_table['8'] = 1;
4346 alt_notend_table['9'] = 1;
4347
4348#ifndef MIT_SYNTAX_ONLY
4349 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4350 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4351 {
4352 int n = 0;
60fed2d3 4353
252b5132
RH		 4354 while (mote_pseudo_table[n].poc_name)
4355 {
60fed2d3 4356 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4357 hash_insert (op_hash,
4358 mote_pseudo_table[n].poc_name, (char *) hack);
4359 hack->m_operands = 0;
4360 hack->m_opnum = n;
4361 n++;
4362 }
4363 }
4364#endif
4365
4366 init_regtable ();
4367
4368#ifdef OBJ_ELF
4369 record_alignment (text_section, 2);
4370 record_alignment (data_section, 2);
4371 record_alignment (bss_section, 2);
4372#endif
4373}
4374
252b5132
RH		 4375\f
4376/* This is called when a label is defined. */
4377
4378void
31302357 4379m68k_frob_label (symbolS *sym)
252b5132
RH		 4380{
4381 struct label_line *n;
4382
4383 n = (struct label_line *) xmalloc (sizeof *n);
4384 n->next = labels;
4385 n->label = sym;
4386 as_where (&n->file, &n->line);
4387 n->text = 0;
4388 labels = n;
4389 current_label = n;
07a53e5c
RH		 4390
4391#ifdef OBJ_ELF
4392 dwarf2_emit_label (sym);
4393#endif
252b5132
RH		 4394}
4395
4396/* This is called when a value that is not an instruction is emitted. */
4397
4398void
31302357 4399m68k_flush_pending_output (void)
252b5132
RH		 4400{
4401 current_label = NULL;
4402}
4403
4404/* This is called at the end of the assembly, when the final value of
4405 the label is known. We warn if this is a text symbol aligned at an
4406 odd location. */
4407
4408void
31302357 4409m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4410{
4411 if (S_GET_SEGMENT (sym) == reg_section
4412 && (int) S_GET_VALUE (sym) < 0)
4413 {
4414 S_SET_SEGMENT (sym, absolute_section);
4415 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4416 }
4417 else if ((S_GET_VALUE (sym) & 1) != 0)
4418 {
4419 struct label_line *l;
4420
4421 for (l = labels; l != NULL; l = l->next)
4422 {
4423 if (l->label == sym)
4424 {
4425 if (l->text)
4426 as_warn_where (l->file, l->line,
4427 _("text label `%s' aligned to odd boundary"),
4428 S_GET_NAME (sym));
4429 break;
4430 }
4431 }
4432 }
4433}
4434\f
4435/* This is called if we go in or out of MRI mode because of the .mri
4436 pseudo-op. */
4437
4438void
31302357 4439m68k_mri_mode_change (int on)
252b5132
RH		 4440{
4441 if (on)
4442 {
4443 if (! flag_reg_prefix_optional)
4444 {
4445 flag_reg_prefix_optional = 1;
4446#ifdef REGISTER_PREFIX
4447 init_regtable ();
4448#endif
4449 }
4450 m68k_abspcadd = 1;
4451 if (! m68k_rel32_from_cmdline)
4452 m68k_rel32 = 0;
4453 }
4454 else
4455 {
4456 if (! reg_prefix_optional_seen)
4457 {
4458#ifdef REGISTER_PREFIX_OPTIONAL
4459 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4460#else
4461 flag_reg_prefix_optional = 0;
4462#endif
4463#ifdef REGISTER_PREFIX
4464 init_regtable ();
4465#endif
4466 }
4467 m68k_abspcadd = 0;
4468 if (! m68k_rel32_from_cmdline)
4469 m68k_rel32 = 1;
4470 }
4471}
4472
36759679 4473/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4474#define MAX_LITTLENUMS 6
4475
4476/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4477 of type TYPE, and store the appropriate bytes in *LITP. The number
4478 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4479 returned, or NULL on OK. */
4480
4481char *
31302357 4482md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4483{
4484 int prec;
4485 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4486 LITTLENUM_TYPE *wordP;
4487 char *t;
4488
4489 switch (type)
4490 {
4491 case 'f':
4492 case 'F':
4493 case 's':
4494 case 'S':
4495 prec = 2;
4496 break;
4497
4498 case 'd':
4499 case 'D':
4500 case 'r':
4501 case 'R':
4502 prec = 4;
4503 break;
4504
4505 case 'x':
4506 case 'X':
4507 prec = 6;
4508 break;
4509
4510 case 'p':
4511 case 'P':
4512 prec = 6;
4513 break;
4514
4515 default:
4516 *sizeP = 0;
4517 return _("Bad call to MD_ATOF()");
4518 }
4519 t = atof_ieee (input_line_pointer, type, words);
4520 if (t)
4521 input_line_pointer = t;
4522
4523 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4524 for (wordP = words; prec--;)
4525 {
4526 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4527 litP += sizeof (LITTLENUM_TYPE);
4528 }
4529 return 0;
4530}
4531
4532void
31302357 4533md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4534{
4535 number_to_chars_bigendian (buf, val, n);
4536}
4537
94f592af 4538void
55cf6793 4539md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4540{
bbe8ef22 4541 offsetT val = *valP;
252b5132
RH		 4542 addressT upper_limit;
4543 offsetT lower_limit;
4544
4545 /* This is unnecessary but it convinces the native rs6000 compiler
4546 to generate the code we want. */
4547 char *buf = fixP->fx_frag->fr_literal;
4548 buf += fixP->fx_where;
36759679 4549 /* End ibm compiler workaround. */
252b5132 4550
bd17c2c3 4551 val = SEXT (val);
252b5132 4552
94f592af
NC		 4553 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4554 fixP->fx_done = 1;
4555
252b5132
RH		 4556#ifdef OBJ_ELF
4557 if (fixP->fx_addsy)
4558 {
4559 memset (buf, 0, fixP->fx_size);
36759679 4560 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4561
4562 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4563 && !S_IS_DEFINED (fixP->fx_addsy)
4564 && !S_IS_WEAK (fixP->fx_addsy))
4565 S_SET_WEAK (fixP->fx_addsy);
4566 return;
4567 }
4568#endif
4569
252b5132
RH		 4570 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4571 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4572 return;
252b5132
RH		 4573
4574 switch (fixP->fx_size)
4575 {
94f592af
NC		 4576 /* The cast to offsetT below are necessary to make code
4577 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4578 case 1:
4579 *buf++ = val;
4580 upper_limit = 0x7f;
4581 lower_limit = - (offsetT) 0x80;
4582 break;
4583 case 2:
4584 *buf++ = (val >> 8);
4585 *buf++ = val;
4586 upper_limit = 0x7fff;
4587 lower_limit = - (offsetT) 0x8000;
4588 break;
4589 case 4:
4590 *buf++ = (val >> 24);
4591 *buf++ = (val >> 16);
4592 *buf++ = (val >> 8);
4593 *buf++ = val;
4594 upper_limit = 0x7fffffff;
36759679 4595 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4596 break;
4597 default:
4598 BAD_CASE (fixP->fx_size);
4599 }
4600
4601 /* Fix up a negative reloc. */
4602 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4603 {
4604 fixP->fx_addsy = fixP->fx_subsy;
4605 fixP->fx_subsy = NULL;
4606 fixP->fx_tcbit = 1;
4607 }
4608
4609 /* For non-pc-relative values, it's conceivable we might get something
4610 like "0xff" for a byte field. So extend the upper part of the range
4611 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4612 so that we can do any range checking at all. */
4613 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4614 upper_limit = upper_limit * 2 + 1;
4615
4616 if ((addressT) val > upper_limit
4617 && (val > 0 || val < lower_limit))
4618 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4619
4620 /* A one byte PC-relative reloc means a short branch. We can't use
4621 a short branch with a value of 0 or -1, because those indicate
4622 different opcodes (branches with longer offsets). fixup_segment
4623 in write.c may have clobbered fx_pcrel, so we need to examine the
4624 reloc type. */
4625 if ((fixP->fx_pcrel
7be1c489 4626 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4627 && fixP->fx_size == 1
4628 && (fixP->fx_addsy == NULL
4629 || S_IS_DEFINED (fixP->fx_addsy))
4630 && (val == 0 || val == -1))
4631 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4632}
4633
252b5132
RH		 4634/* *fragP has been relaxed to its final size, and now needs to have
4635 the bytes inside it modified to conform to the new size There is UGLY
4636 MAGIC here. ..
4637 */
4638static void
31302357 4639md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4640{
4641 long disp;
252b5132
RH		 4642 fixS *fixP;
4643
4644 /* Address in object code of the displacement. */
4645 register int object_address = fragP->fr_fix + fragP->fr_address;
4646
4647 /* Address in gas core of the place to store the displacement. */
4648 /* This convinces the native rs6000 compiler to generate the code we
92774660 4649 want. */
252b5132
RH		 4650 register char *buffer_address = fragP->fr_literal;
4651 buffer_address += fragP->fr_fix;
36759679 4652 /* End ibm compiler workaround. */
252b5132
RH		 4653
4654 /* The displacement of the address, from current location. */
4655 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4656 disp = (disp + fragP->fr_offset) - object_address;
4657
252b5132
RH		 4658 switch (fragP->fr_subtype)
4659 {
151337e8
NC		 4660 case TAB (BRANCHBWL, BYTE):
4661 case TAB (BRABSJUNC, BYTE):
4662 case TAB (BRABSJCOND, BYTE):
4663 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4664 know (issbyte (disp));
4665 if (disp == 0)
b091f402
AM		 4666 as_bad_where (fragP->fr_file, fragP->fr_line,
4667 _("short branch with zero offset: use :w"));
151337e8 4668 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4669 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4670 fixP->fx_pcrel_adjust = -1;
252b5132 4671 break;
151337e8
NC		 4672 case TAB (BRANCHBWL, SHORT):
4673 case TAB (BRABSJUNC, SHORT):
4674 case TAB (BRABSJCOND, SHORT):
4675 case TAB (BRANCHBW, SHORT):
252b5132 4676 fragP->fr_opcode[1] = 0x00;
151337e8 4677 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4678 1, RELAX_RELOC_PC16);
151337e8
NC		 4679 fragP->fr_fix += 2;
4680 break;
4681 case TAB (BRANCHBWL, LONG):
4682 fragP->fr_opcode[1] = (char) 0xFF;
4683 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4684 1, RELAX_RELOC_PC32);
151337e8 4685 fragP->fr_fix += 4;
252b5132 4686 break;
151337e8
NC		 4687 case TAB (BRABSJUNC, LONG):
4688 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4689 {
36759679 4690 if (flag_keep_pcrel)
6b6e92f4 4691 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4692 fragP->fr_opcode[0] = 0x4E;
36759679 4693 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4694 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4695 0, RELAX_RELOC_ABS32);
151337e8
NC		 4696 fragP->fr_fix += 4;
4697 }
4698 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4699 {
36759679 4700 if (flag_keep_pcrel)
6b6e92f4 4701 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4702 fragP->fr_opcode[0] = 0x4E;
36759679 4703 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4704 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4705 0, RELAX_RELOC_ABS32);
151337e8 4706 fragP->fr_fix += 4;
252b5132
RH		 4707 }
4708 else
4709 {
151337e8
NC		 4710 /* This cannot happen, because jbsr and jbra are the only two
4711 unconditional branches. */
4712 abort ();
252b5132
RH		 4713 }
4714 break;
151337e8 4715 case TAB (BRABSJCOND, LONG):
36759679 4716 if (flag_keep_pcrel)
6b6e92f4 4717 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4718
36759679
NC		 4719 /* Only Bcc 68000 instructions can come here
4720 Change bcc into b!cc/jmp absl long. */
4721 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4722 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4723
4724 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4725 different frag, in which case referring to them is a no-no.
92774660 4726 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4727 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4728 *buffer_address++ = (char) 0xf9;
36759679 4729 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4730 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4731 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4732 fragP->fr_fix += 4;
4733 break;
4734 case TAB (FBRANCH, SHORT):
4735 know ((fragP->fr_opcode[1] & 0x40) == 0);
4736 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4737 1, RELAX_RELOC_PC16);
151337e8
NC		 4738 fragP->fr_fix += 2;
4739 break;
4740 case TAB (FBRANCH, LONG):
36759679 4741 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4742 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4743 1, RELAX_RELOC_PC32);
252b5132 4744 fragP->fr_fix += 4;
252b5132 4745 break;
151337e8
NC		 4746 case TAB (DBCCLBR, SHORT):
4747 case TAB (DBCCABSJ, SHORT):
4748 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4749 1, RELAX_RELOC_PC16);
151337e8
NC		 4750 fragP->fr_fix += 2;
4751 break;
4752 case TAB (DBCCLBR, LONG):
36759679
NC		 4753 /* Only DBcc instructions can come here.
4754 Change dbcc into dbcc/bral.
4755 JF: these used to be fr_opcode[2-7], but that's wrong. */
4756 if (flag_keep_pcrel)
6b6e92f4 4757 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4758
36759679 4759 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4760 *buffer_address++ = 0x04;
36759679 4761 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4762 *buffer_address++ = 0x06;
151337e8
NC		 4763 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4764 *buffer_address++ = (char) 0xff;
252b5132 4765
36759679 4766 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4767 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4768 RELAX_RELOC_PC32);
252b5132 4769 fragP->fr_fix += 4;
252b5132 4770 break;
151337e8 4771 case TAB (DBCCABSJ, LONG):
36759679
NC		 4772 /* Only DBcc instructions can come here.
4773 Change dbcc into dbcc/jmp.
4774 JF: these used to be fr_opcode[2-7], but that's wrong. */
4775 if (flag_keep_pcrel)
6b6e92f4 4776 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4777
36759679 4778 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4779 *buffer_address++ = 0x04;
36759679 4780 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4781 *buffer_address++ = 0x06;
36759679 4782 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4783 *buffer_address++ = (char) 0xf9;
4784
36759679 4785 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4786 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4787 RELAX_RELOC_ABS32);
252b5132 4788 fragP->fr_fix += 4;
252b5132 4789 break;
151337e8 4790 case TAB (PCREL1632, SHORT):
252b5132
RH		 4791 fragP->fr_opcode[1] &= ~0x3F;
4792 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4793 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4794 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4795 fragP->fr_fix += 2;
252b5132 4796 break;
151337e8 4797 case TAB (PCREL1632, LONG):
252b5132
RH		 4798 /* Already set to mode 7.3; this indicates: PC indirect with
4799 suppressed index, 32-bit displacement. */
4800 *buffer_address++ = 0x01;
4801 *buffer_address++ = 0x70;
4802 fragP->fr_fix += 2;
151337e8 4803 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4804 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4805 fixP->fx_pcrel_adjust = 2;
4806 fragP->fr_fix += 4;
252b5132 4807 break;
252b5132 4808 case TAB (PCINDEX, BYTE):
252b5132
RH		 4809 assert (fragP->fr_fix >= 2);
4810 buffer_address[-2] &= ~1;
151337e8 4811 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4812 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4813 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4814 break;
4815 case TAB (PCINDEX, SHORT):
252b5132
RH		 4816 assert (fragP->fr_fix >= 2);
4817 buffer_address[-2] |= 0x1;
4818 buffer_address[-1] = 0x20;
4819 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4820 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4821 fixP->fx_pcrel_adjust = 2;
151337e8 4822 fragP->fr_fix += 2;
252b5132
RH		 4823 break;
4824 case TAB (PCINDEX, LONG):
252b5132
RH		 4825 assert (fragP->fr_fix >= 2);
4826 buffer_address[-2] |= 0x1;
4827 buffer_address[-1] = 0x30;
151337e8 4828 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4829 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4830 fixP->fx_pcrel_adjust = 2;
4831 fragP->fr_fix += 4;
4832 break;
4833 case TAB (ABSTOPCREL, SHORT):
4834 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4835 1, RELAX_RELOC_PC16);
151337e8
NC		 4836 fragP->fr_fix += 2;
4837 break;
4838 case TAB (ABSTOPCREL, LONG):
36759679 4839 if (flag_keep_pcrel)
6b6e92f4 4840 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4841 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4842 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4843 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4844 abort ();
4845 fragP->fr_opcode[1] &= ~0x3F;
4846 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4847 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4848 0, RELAX_RELOC_ABS32);
151337e8 4849 fragP->fr_fix += 4;
252b5132 4850 break;
252b5132
RH		 4851 }
4852}
4853
252b5132 4854void
31302357
AS		 4855md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4856 segT sec ATTRIBUTE_UNUSED,
4857 fragS *fragP)
252b5132
RH		 4858{
4859 md_convert_frag_1 (fragP);
4860}
252b5132
RH		 4861
4862/* Force truly undefined symbols to their maximum size, and generally set up
4863 the frag list to be relaxed
4864 */
4865int
31302357 4866md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4867{
151337e8 4868 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4869 switch (fragP->fr_subtype)
4870 {
151337e8
NC		 4871 case TAB (BRANCHBWL, SZ_UNDEF):
4872 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4873 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4874 {
151337e8
NC		 4875 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4876 && relaxable_symbol (fragP->fr_symbol))
252b5132 4877 {
151337e8
NC		 4878 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4879 }
4880 else if (flag_short_refs)
4881 {
4882 /* Symbol is undefined and we want short ref. */
4883 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4884 }
4885 else
4886 {
151337e8
NC		 4887 /* Symbol is still undefined. Make it LONG. */
4888 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4889 }
4890 break;
151337e8 4891 }
252b5132 4892
151337e8 4893 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4894 {
151337e8
NC		 4895 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4896 && relaxable_symbol (fragP->fr_symbol))
252b5132 4897 {
151337e8 4898 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4899 }
4900 else
4901 {
151337e8
NC		 4902 /* Symbol is undefined and we don't have long branches. */
4903 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4904 }
4905 break;
151337e8 4906 }
252b5132 4907
151337e8 4908 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4909 case TAB (DBCCLBR, SZ_UNDEF):
4910 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4911 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4912 {
8ec6253e
NC		 4913 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4914 && relaxable_symbol (fragP->fr_symbol))
151337e8 4915 || flag_short_refs)
252b5132 4916 {
151337e8 4917 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4918 }
4919 else
4920 {
151337e8 4921 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4922 }
4923 break;
151337e8 4924 }
81d4177b 4925
252b5132
RH		 4926 case TAB (PCINDEX, SZ_UNDEF):
4927 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4928 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4929 {
4930 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4931 }
4932 else
4933 {
4934 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4935 }
4936 break;
4937
151337e8
NC		 4938 case TAB (ABSTOPCREL, SZ_UNDEF):
4939 {
4940 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4941 && relaxable_symbol (fragP->fr_symbol)))
4942 {
4943 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4944 }
4945 else
4946 {
4947 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4948 }
4949 break;
4950 }
4951
252b5132
RH		 4952 default:
4953 break;
4954 }
4955
151337e8 4956 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4957 switch (fragP->fr_subtype)
4958 {
151337e8
NC		 4959 case TAB (BRANCHBWL, BYTE):
4960 case TAB (BRABSJUNC, BYTE):
4961 case TAB (BRABSJCOND, BYTE):
4962 case TAB (BRANCHBW, BYTE):
252b5132 4963 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4964 case we force word mode. If the symbol is at the start of a
4965 frag, and it is the next frag with any data in it (usually
4966 this is just the next frag, but assembler listings may
4967 introduce empty frags), we must use word mode. */
4968 if (fragP->fr_symbol)
252b5132 4969 {
ac62c346 4970 fragS *sym_frag;
252b5132 4971
ac62c346
AM		 4972 sym_frag = symbol_get_frag (fragP->fr_symbol);
4973 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4974 {
ac62c346
AM		 4975 fragS *l;
4976
23b7f870 4977 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4978 if (l->fr_fix != 0)
4979 break;
4980 if (l == sym_frag)
4981 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4982 }
4983 }
4984 break;
4985 default:
4986 break;
4987 }
ac62c346 4988 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4989}
4990
4991#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4992/* the bit-field entries in the relocation_info struct plays hell
4993 with the byte-order problems of cross-assembly. So as a hack,
4994 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 4995 you there. -KWK */
252b5132
RH		 4996/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4997 are symbolnum, most sig. byte first. Last byte is broken up with
4998 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4999 nibble as nuthin. (on Sun 3 at least) */
5000/* Translate the internal relocation information into target-specific
92774660 5001 format. */
252b5132
RH		 5002#ifdef comment
5003void
31302357 5004md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5005{
36759679 5006 /* This is easy. */
252b5132 5007 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5008 /* Now the fun stuff. */
252b5132 5009 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5010 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5011 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5012 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5013 | ((ri->r_length << 5) & 0x60)
5014 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5015}
5016
36759679 5017#endif
252b5132 5018
252b5132
RH		 5019#endif /* OBJ_AOUT or OBJ_BOUT */
5020
5021#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5022int md_short_jump_size = 4;
5023int md_long_jump_size = 6;
252b5132
RH		 5024
5025void
31302357
AS		 5026md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5027 fragS *frag ATTRIBUTE_UNUSED,
5028 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5029{
5030 valueT offset;
5031
5032 offset = to_addr - (from_addr + 2);
5033
5034 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5035 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5036}
5037
5038void
31302357
AS		 5039md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5040 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5041{
5042 valueT offset;
5043
6b6e92f4 5044 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5045 {
36759679 5046 if (flag_keep_pcrel)
6b6e92f4 5047 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5048 offset = to_addr - S_GET_VALUE (to_symbol);
5049 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5050 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5051 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5052 0, NO_RELOC);
5053 }
5054 else
5055 {
5056 offset = to_addr - (from_addr + 2);
5057 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5058 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5059 }
5060}
5061
5062#endif
5063
5064/* Different values of OK tell what its OK to return. Things that
5065 aren't OK are an error (what a shock, no?)
5066
5067 0: Everything is OK
3e602632
NC		 5068 10: Absolute 1:8 only
5069 20: Absolute 0:7 only
5070 30: absolute 0:15 only
5071 40: Absolute 0:31 only
5072 50: absolute 0:127 only
252b5132 5073 55: absolute -64:63 only
3e602632
NC		 5074 60: absolute -128:127 only
5075 70: absolute 0:4095 only
5076 80: absolute -1, 1:7 only
5077 90: No bignums. */
252b5132
RH		 5078
5079static int
31302357 5080get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5081{
5082 if (exp->exp.X_op == O_absent)
5083 {
36759679 5084 /* Do the same thing the VAX asm does. */
252b5132
RH		 5085 op (exp) = O_constant;
5086 adds (exp) = 0;
5087 subs (exp) = 0;
5088 offs (exp) = 0;
5089 if (ok == 10)
5090 {
5091 as_warn (_("expression out of range: defaulting to 1"));
5092 offs (exp) = 1;
5093 }
5094 }
5095 else if (exp->exp.X_op == O_constant)
5096 {
5097 switch (ok)
5098 {
5099 case 10:
bd17c2c3 5100 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5101 {
5102 as_warn (_("expression out of range: defaulting to 1"));
5103 offs (exp) = 1;
5104 }
5105 break;
5106 case 20:
bd17c2c3 5107 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5108 goto outrange;
5109 break;
5110 case 30:
bd17c2c3 5111 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5112 goto outrange;
5113 break;
5114 case 40:
bd17c2c3 5115 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5116 goto outrange;
5117 break;
5118 case 50:
bd17c2c3 5119 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5120 goto outrange;
5121 break;
5122 case 55:
bd17c2c3 5123 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5124 goto outrange;
5125 break;
5126 case 60:
bd17c2c3 5127 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5128 goto outrange;
5129 break;
5130 case 70:
bd17c2c3 5131 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5132 {
5133 outrange:
5134 as_warn (_("expression out of range: defaulting to 0"));
5135 offs (exp) = 0;
5136 }
5137 break;
3e602632 5138 case 80:
bd17c2c3
AM		 5139 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5140 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5141 {
5142 as_warn (_("expression out of range: defaulting to 1"));
5143 offs (exp) = 1;
5144 }
5145 break;
252b5132
RH		 5146 default:
5147 break;
5148 }
5149 }
5150 else if (exp->exp.X_op == O_big)
5151 {
36759679 5152 if (offs (exp) <= 0 /* flonum. */
3e602632 5153 && (ok == 90 /* no bignums */
36759679 5154 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5155 /* If we have a flonum zero, a zero integer should
5156 do as well (e.g., in moveq). */
5157 && generic_floating_point_number.exponent == 0
5158 && generic_floating_point_number.low[0] == 0)))
5159 {
36759679 5160 /* HACK! Turn it into a long. */
252b5132
RH		 5161 LITTLENUM_TYPE words[6];
5162
36759679 5163 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5164 op (exp) = O_constant;
5165 adds (exp) = 0;
5166 subs (exp) = 0;
5167 offs (exp) = words[1] | (words[0] << 16);
5168 }
5169 else if (ok != 0)
5170 {
5171 op (exp) = O_constant;
5172 adds (exp) = 0;
5173 subs (exp) = 0;
5174 offs (exp) = (ok == 10) ? 1 : 0;
5175 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5176 (long) offs (exp));
252b5132
RH		 5177 }
5178 }
5179 else
5180 {
3e602632 5181 if (ok >= 10 && ok <= 80)
252b5132
RH		 5182 {
5183 op (exp) = O_constant;
5184 adds (exp) = 0;
5185 subs (exp) = 0;
5186 offs (exp) = (ok == 10) ? 1 : 0;
5187 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5188 (long) offs (exp));
252b5132
RH		 5189 }
5190 }
5191
5192 if (exp->size != SIZE_UNSPEC)
5193 {
5194 switch (exp->size)
5195 {
5196 case SIZE_UNSPEC:
5197 case SIZE_LONG:
5198 break;
5199 case SIZE_BYTE:
5200 if (!isbyte (offs (exp)))
5201 as_warn (_("expression doesn't fit in BYTE"));
5202 break;
5203 case SIZE_WORD:
5204 if (!isword (offs (exp)))
5205 as_warn (_("expression doesn't fit in WORD"));
5206 break;
5207 }
5208 }
5209
5210 return offs (exp);
5211}
5212
5213/* These are the back-ends for the various machine dependent pseudo-ops. */
5214
5215static void
31302357 5216s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5217{
5218 subseg_set (data_section, 1);
5219 demand_empty_rest_of_line ();
5220}
5221
5222static void
31302357 5223s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5224{
5225 subseg_set (data_section, 2);
5226 demand_empty_rest_of_line ();
5227}
5228
5229static void
31302357 5230s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5231{
5232 /* We don't support putting frags in the BSS segment, we fake it
5233 by marking in_bss, then looking at s_skip for clues. */
5234
5235 subseg_set (bss_section, 0);
5236 demand_empty_rest_of_line ();
5237}
5238
5239static void
31302357 5240s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5241{
5242 register int temp;
5243 register long temp_fill;
5244
5245 temp = 1; /* JF should be 2? */
5246 temp_fill = get_absolute_expression ();
92774660 5247 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5248 frag_align (temp, (int) temp_fill, 0);
5249 demand_empty_rest_of_line ();
5250 record_alignment (now_seg, temp);
5251}
5252
5253static void
31302357 5254s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5255{
5256 demand_empty_rest_of_line ();
5257}
5258\f
5259/* Pseudo-ops handled for MRI compatibility. */
5260
5261/* This function returns non-zero if the argument is a conditional
5262 pseudo-op. This is called when checking whether a pending
5263 alignment is needed. */
5264
5265int
31302357 5266m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5267{
5268 return (pop->poc_handler == s_mri_if
5269 || pop->poc_handler == s_mri_else);
5270}
5271
5272/* Handle an MRI style chip specification. */
5273
5274static void
31302357 5275mri_chip (void)
252b5132
RH		 5276{
5277 char *s;
5278 char c;
5279 int i;
5280
5281 s = input_line_pointer;
5282 /* We can't use get_symbol_end since the processor names are not proper
5283 symbols. */
5284 while (is_part_of_name (c = *input_line_pointer++))
5285 ;
5286 *--input_line_pointer = 0;
266abb8f
NS		 5287 for (i = 0; m68k_cpus[i].name; i++)
5288 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5289 break;
266abb8f 5290 if (!m68k_cpus[i].name)
252b5132
RH		 5291 {
5292 as_bad (_("%s: unrecognized processor name"), s);
5293 *input_line_pointer = c;
5294 ignore_rest_of_line ();
5295 return;
5296 }
5297 *input_line_pointer = c;
5298
5299 if (*input_line_pointer == '/')
5300 current_architecture = 0;
5301 else
5302 current_architecture &= m68881 | m68851;
266abb8f 5303 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5304 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5305
5306 while (*input_line_pointer == '/')
5307 {
5308 ++input_line_pointer;
5309 s = input_line_pointer;
5310 /* We can't use get_symbol_end since the processor names are not
5311 proper symbols. */
5312 while (is_part_of_name (c = *input_line_pointer++))
5313 ;
5314 *--input_line_pointer = 0;
5315 if (strcmp (s, "68881") == 0)
5316 current_architecture |= m68881;
5317 else if (strcmp (s, "68851") == 0)
5318 current_architecture |= m68851;
5319 *input_line_pointer = c;
5320 }
252b5132
RH		 5321}
5322
5323/* The MRI CHIP pseudo-op. */
5324
5325static void
31302357 5326s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5327{
5328 char *stop = NULL;
5329 char stopc;
5330
5331 if (flag_mri)
5332 stop = mri_comment_field (&stopc);
5333 mri_chip ();
5334 if (flag_mri)
5335 mri_comment_end (stop, stopc);
5336 demand_empty_rest_of_line ();
5337}
5338
5339/* The MRI FOPT pseudo-op. */
5340
5341static void
31302357 5342s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5343{
5344 SKIP_WHITESPACE ();
5345
5346 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5347 {
5348 int temp;
5349
5350 input_line_pointer += 3;
5351 temp = get_absolute_expression ();
5352 if (temp < 0 || temp > 7)
5353 as_bad (_("bad coprocessor id"));
5354 else
5355 m68k_float_copnum = COP0 + temp;
5356 }
5357 else
5358 {
5359 as_bad (_("unrecognized fopt option"));
5360 ignore_rest_of_line ();
5361 return;
5362 }
5363
5364 demand_empty_rest_of_line ();
5365}
5366
5367/* The structure used to handle the MRI OPT pseudo-op. */
5368
5369struct opt_action
5370{
5371 /* The name of the option. */
5372 const char *name;
5373
5374 /* If this is not NULL, just call this function. The first argument
5375 is the ARG field of this structure, the second argument is
5376 whether the option was negated. */
31302357 5377 void (*pfn) (int arg, int on);
252b5132
RH		 5378
5379 /* If this is not NULL, and the PFN field is NULL, set the variable
5380 this points to. Set it to the ARG field if the option was not
5381 negated, and the NOTARG field otherwise. */
5382 int *pvar;
5383
5384 /* The value to pass to PFN or to assign to *PVAR. */
5385 int arg;
5386
5387 /* The value to assign to *PVAR if the option is negated. If PFN is
5388 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5389 the option may not be negated. */
5390 int notarg;
5391};
5392
5393/* The table used to handle the MRI OPT pseudo-op. */
5394
31302357
AS		 5395static void skip_to_comma (int, int);
5396static void opt_nest (int, int);
5397static void opt_chip (int, int);
5398static void opt_list (int, int);
5399static void opt_list_symbols (int, int);
252b5132
RH		 5400
5401static const struct opt_action opt_table[] =
5402{
5403 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5404
5405 /* We do relaxing, so there is little use for these options. */
5406 { "b", 0, 0, 0, 0 },
5407 { "brs", 0, 0, 0, 0 },
5408 { "brb", 0, 0, 0, 0 },
5409 { "brl", 0, 0, 0, 0 },
5410 { "brw", 0, 0, 0, 0 },
5411
5412 { "c", 0, 0, 0, 0 },
5413 { "cex", 0, 0, 0, 0 },
5414 { "case", 0, &symbols_case_sensitive, 1, 0 },
5415 { "cl", 0, 0, 0, 0 },
5416 { "cre", 0, 0, 0, 0 },
5417 { "d", 0, &flag_keep_locals, 1, 0 },
5418 { "e", 0, 0, 0, 0 },
5419 { "f", 0, &flag_short_refs, 1, 0 },
5420 { "frs", 0, &flag_short_refs, 1, 0 },
5421 { "frl", 0, &flag_short_refs, 0, 1 },
5422 { "g", 0, 0, 0, 0 },
5423 { "i", 0, 0, 0, 0 },
5424 { "m", 0, 0, 0, 0 },
5425 { "mex", 0, 0, 0, 0 },
5426 { "mc", 0, 0, 0, 0 },
5427 { "md", 0, 0, 0, 0 },
5428 { "nest", opt_nest, 0, 0, 0 },
5429 { "next", skip_to_comma, 0, 0, 0 },
5430 { "o", 0, 0, 0, 0 },
5431 { "old", 0, 0, 0, 0 },
5432 { "op", skip_to_comma, 0, 0, 0 },
5433 { "pco", 0, 0, 0, 0 },
5434 { "p", opt_chip, 0, 0, 0 },
5435 { "pcr", 0, 0, 0, 0 },
5436 { "pcs", 0, 0, 0, 0 },
5437 { "r", 0, 0, 0, 0 },
5438 { "quick", 0, &m68k_quick, 1, 0 },
5439 { "rel32", 0, &m68k_rel32, 1, 0 },
5440 { "s", opt_list, 0, 0, 0 },
5441 { "t", opt_list_symbols, 0, 0, 0 },
5442 { "w", 0, &flag_no_warnings, 0, 1 },
5443 { "x", 0, 0, 0, 0 }
5444};
5445
8fce3f5e 5446#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5447
5448/* The MRI OPT pseudo-op. */
5449
5450static void
31302357 5451s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5452{
5453 do
5454 {
5455 int t;
5456 char *s;
5457 char c;
5458 int i;
5459 const struct opt_action *o;
5460
5461 SKIP_WHITESPACE ();
5462
5463 t = 1;
5464 if (*input_line_pointer == '-')
5465 {
5466 ++input_line_pointer;
5467 t = 0;
5468 }
5469 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5470 {
5471 input_line_pointer += 2;
5472 t = 0;
5473 }
5474
5475 s = input_line_pointer;
5476 c = get_symbol_end ();
5477
5478 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5479 {
5480 if (strcasecmp (s, o->name) == 0)
5481 {
5482 if (o->pfn)
5483 {
5484 /* Restore input_line_pointer now in case the option
5485 takes arguments. */
5486 *input_line_pointer = c;
5487 (*o->pfn) (o->arg, t);
5488 }
5489 else if (o->pvar != NULL)
5490 {
5491 if (! t && o->arg == o->notarg)
5492 as_bad (_("option `%s' may not be negated"), s);
5493 *input_line_pointer = c;
5494 *o->pvar = t ? o->arg : o->notarg;
5495 }
5496 else
5497 *input_line_pointer = c;
5498 break;
5499 }
5500 }
5501 if (i >= OPTCOUNT)
5502 {
5503 as_bad (_("option `%s' not recognized"), s);
5504 *input_line_pointer = c;
5505 }
5506 }
5507 while (*input_line_pointer++ == ',');
5508
5509 /* Move back to terminating character. */
5510 --input_line_pointer;
5511 demand_empty_rest_of_line ();
5512}
5513
5514/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5515 not support and which take arguments. */
252b5132
RH		 5516
5517static void
31302357 5518skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5519{
5520 while (*input_line_pointer != ','
5521 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5522 ++input_line_pointer;
5523}
5524
5525/* Handle the OPT NEST=depth option. */
5526
5527static void
31302357 5528opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5529{
5530 if (*input_line_pointer != '=')
5531 {
5532 as_bad (_("bad format of OPT NEST=depth"));
5533 return;
5534 }
5535
5536 ++input_line_pointer;
5537 max_macro_nest = get_absolute_expression ();
5538}
5539
5540/* Handle the OPT P=chip option. */
5541
5542static void
31302357 5543opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5544{
5545 if (*input_line_pointer != '=')
5546 {
5547 /* This is just OPT P, which we do not support. */
5548 return;
5549 }
5550
5551 ++input_line_pointer;
5552 mri_chip ();
5553}
5554
5555/* Handle the OPT S option. */
5556
5557static void
31302357 5558opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5559{
5560 listing_list (on);
5561}
5562
5563/* Handle the OPT T option. */
5564
5565static void
31302357 5566opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5567{
5568 if (on)
5569 listing |= LISTING_SYMBOLS;
5570 else
8a104df9 5571 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5572}
5573
5574/* Handle the MRI REG pseudo-op. */
5575
5576static void
31302357 5577s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5578{
5579 char *s;
5580 int c;
5581 struct m68k_op rop;
5582 int mask;
5583 char *stop = NULL;
5584 char stopc;
5585
5586 if (line_label == NULL)
5587 {
5588 as_bad (_("missing label"));
5589 ignore_rest_of_line ();
5590 return;
5591 }
5592
5593 if (flag_mri)
5594 stop = mri_comment_field (&stopc);
5595
5596 SKIP_WHITESPACE ();
5597
5598 s = input_line_pointer;
3882b010 5599 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5600#ifdef REGISTER_PREFIX
5601 || *input_line_pointer == REGISTER_PREFIX
5602#endif
5603 || *input_line_pointer == '/'
5604 || *input_line_pointer == '-')
5605 ++input_line_pointer;
5606 c = *input_line_pointer;
5607 *input_line_pointer = '\0';
5608
5609 if (m68k_ip_op (s, &rop) != 0)
5610 {
5611 if (rop.error == NULL)
5612 as_bad (_("bad register list"));
5613 else
5614 as_bad (_("bad register list: %s"), rop.error);
5615 *input_line_pointer = c;
5616 ignore_rest_of_line ();
5617 return;
5618 }
5619
5620 *input_line_pointer = c;
5621
5622 if (rop.mode == REGLST)
5623 mask = rop.mask;
5624 else if (rop.mode == DREG)
5625 mask = 1 << (rop.reg - DATA0);
5626 else if (rop.mode == AREG)
5627 mask = 1 << (rop.reg - ADDR0 + 8);
5628 else if (rop.mode == FPREG)
5629 mask = 1 << (rop.reg - FP0 + 16);
5630 else if (rop.mode == CONTROL
5631 && rop.reg == FPI)
5632 mask = 1 << 24;
5633 else if (rop.mode == CONTROL
5634 && rop.reg == FPS)
5635 mask = 1 << 25;
5636 else if (rop.mode == CONTROL
5637 && rop.reg == FPC)
5638 mask = 1 << 26;
5639 else
5640 {
5641 as_bad (_("bad register list"));
5642 ignore_rest_of_line ();
5643 return;
5644 }
5645
5646 S_SET_SEGMENT (line_label, reg_section);
5647 S_SET_VALUE (line_label, ~mask);
49309057 5648 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5649
5650 if (flag_mri)
5651 mri_comment_end (stop, stopc);
5652
5653 demand_empty_rest_of_line ();
5654}
5655
5656/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5657
5658struct save_opts
5659{
5660 struct save_opts *next;
5661 int abspcadd;
5662 int symbols_case_sensitive;
5663 int keep_locals;
5664 int short_refs;
5665 int architecture;
2da12c60 5666 const enum m68k_register *control_regs;
252b5132
RH		 5667 int quick;
5668 int rel32;
5669 int listing;
5670 int no_warnings;
5671 /* FIXME: We don't save OPT S. */
5672};
5673
5674/* This variable holds the stack of saved options. */
5675
5676static struct save_opts *save_stack;
5677
5678/* The MRI SAVE pseudo-op. */
5679
5680static void
31302357 5681s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5682{
5683 struct save_opts *s;
5684
5685 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5686 s->abspcadd = m68k_abspcadd;
5687 s->symbols_case_sensitive = symbols_case_sensitive;
5688 s->keep_locals = flag_keep_locals;
5689 s->short_refs = flag_short_refs;
5690 s->architecture = current_architecture;
2da12c60 5691 s->control_regs = control_regs;
252b5132
RH		 5692 s->quick = m68k_quick;
5693 s->rel32 = m68k_rel32;
5694 s->listing = listing;
5695 s->no_warnings = flag_no_warnings;
5696
5697 s->next = save_stack;
5698 save_stack = s;
5699
5700 demand_empty_rest_of_line ();
5701}
5702
5703/* The MRI RESTORE pseudo-op. */
5704
5705static void
31302357 5706s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5707{
5708 struct save_opts *s;
5709
5710 if (save_stack == NULL)
5711 {
5712 as_bad (_("restore without save"));
5713 ignore_rest_of_line ();
5714 return;
5715 }
5716
5717 s = save_stack;
5718 save_stack = s->next;
5719
5720 m68k_abspcadd = s->abspcadd;
5721 symbols_case_sensitive = s->symbols_case_sensitive;
5722 flag_keep_locals = s->keep_locals;
5723 flag_short_refs = s->short_refs;
5724 current_architecture = s->architecture;
2da12c60 5725 control_regs = s->control_regs;
252b5132
RH		 5726 m68k_quick = s->quick;
5727 m68k_rel32 = s->rel32;
5728 listing = s->listing;
5729 flag_no_warnings = s->no_warnings;
5730
5731 free (s);
5732
5733 demand_empty_rest_of_line ();
5734}
5735
5736/* Types of MRI structured control directives. */
5737
5738enum mri_control_type
5739{
5740 mri_for,
5741 mri_if,
5742 mri_repeat,
5743 mri_while
5744};
5745
5746/* This structure is used to stack the MRI structured control
5747 directives. */
5748
5749struct mri_control_info
5750{
5751 /* The directive within which this one is enclosed. */
5752 struct mri_control_info *outer;
5753
5754 /* The type of directive. */
5755 enum mri_control_type type;
5756
5757 /* Whether an ELSE has been in an IF. */
5758 int else_seen;
5759
5760 /* The add or sub statement at the end of a FOR. */
5761 char *incr;
5762
5763 /* The label of the top of a FOR or REPEAT loop. */
5764 char *top;
5765
5766 /* The label to jump to for the next iteration, or the else
5767 expression of a conditional. */
5768 char *next;
5769
5770 /* The label to jump to to break out of the loop, or the label past
5771 the end of a conditional. */
5772 char *bottom;
5773};
5774
5775/* The stack of MRI structured control directives. */
5776
5777static struct mri_control_info *mri_control_stack;
5778
5779/* The current MRI structured control directive index number, used to
5780 generate label names. */
5781
5782static int mri_control_index;
5783
252b5132
RH		 5784/* Assemble an instruction for an MRI structured control directive. */
5785
5786static void
31302357 5787mri_assemble (char *str)
252b5132
RH		 5788{
5789 char *s;
5790
5791 /* md_assemble expects the opcode to be in lower case. */
5792 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5793 *s = TOLOWER (*s);
252b5132
RH		 5794
5795 md_assemble (str);
5796}
5797
5798/* Generate a new MRI label structured control directive label name. */
5799
5800static char *
31302357 5801mri_control_label (void)
252b5132
RH		 5802{
5803 char *n;
5804
5805 n = (char *) xmalloc (20);
5806 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5807 ++mri_control_index;
5808 return n;
5809}
5810
5811/* Create a new MRI structured control directive. */
5812
5813static struct mri_control_info *
31302357 5814push_mri_control (enum mri_control_type type)
252b5132
RH		 5815{
5816 struct mri_control_info *n;
5817
5818 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5819
5820 n->type = type;
5821 n->else_seen = 0;
5822 if (type == mri_if || type == mri_while)
5823 n->top = NULL;
5824 else
5825 n->top = mri_control_label ();
5826 n->next = mri_control_label ();
5827 n->bottom = mri_control_label ();
5828
5829 n->outer = mri_control_stack;
5830 mri_control_stack = n;
5831
5832 return n;
5833}
5834
5835/* Pop off the stack of MRI structured control directives. */
5836
5837static void
31302357 5838pop_mri_control (void)
252b5132
RH		 5839{
5840 struct mri_control_info *n;
5841
5842 n = mri_control_stack;
5843 mri_control_stack = n->outer;
5844 if (n->top != NULL)
5845 free (n->top);
5846 free (n->next);
5847 free (n->bottom);
5848 free (n);
5849}
5850
5851/* Recognize a condition code in an MRI structured control expression. */
5852
5853static int
31302357 5854parse_mri_condition (int *pcc)
252b5132
RH		 5855{
5856 char c1, c2;
5857
5858 know (*input_line_pointer == '<');
5859
5860 ++input_line_pointer;
5861 c1 = *input_line_pointer++;
5862 c2 = *input_line_pointer++;
5863
5864 if (*input_line_pointer != '>')
5865 {
5866 as_bad (_("syntax error in structured control directive"));
5867 return 0;
5868 }
5869
5870 ++input_line_pointer;
5871 SKIP_WHITESPACE ();
5872
3882b010
L		 5873 c1 = TOLOWER (c1);
5874 c2 = TOLOWER (c2);
252b5132
RH		 5875
5876 *pcc = (c1 << 8) | c2;
5877
5878 return 1;
5879}
5880
5881/* Parse a single operand in an MRI structured control expression. */
5882
5883static int
31302357
AS		 5884parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5885 char **rightstart, char **rightstop)
252b5132
RH		 5886{
5887 char *s;
5888
5889 SKIP_WHITESPACE ();
5890
5891 *pcc = -1;
5892 *leftstart = NULL;
5893 *leftstop = NULL;
5894 *rightstart = NULL;
5895 *rightstop = NULL;
5896
5897 if (*input_line_pointer == '<')
5898 {
5899 /* It's just a condition code. */
5900 return parse_mri_condition (pcc);
5901 }
5902
5903 /* Look ahead for the condition code. */
5904 for (s = input_line_pointer; *s != '\0'; ++s)
5905 {
5906 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5907 break;
5908 }
5909 if (*s == '\0')
5910 {
5911 as_bad (_("missing condition code in structured control directive"));
5912 return 0;
5913 }
5914
5915 *leftstart = input_line_pointer;
5916 *leftstop = s;
5917 if (*leftstop > *leftstart
5918 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5919 --*leftstop;
5920
5921 input_line_pointer = s;
5922 if (! parse_mri_condition (pcc))
5923 return 0;
5924
5925 /* Look ahead for AND or OR or end of line. */
5926 for (s = input_line_pointer; *s != '\0'; ++s)
5927 {
e1f44d10
NC		 5928 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5929 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5930 ^^^ ^^ */
8a104df9
KH		 5931 if ((s == input_line_pointer
5932 || *(s-1) == ' '
5933 || *(s-1) == '\t')
5934 && ((strncasecmp (s, "AND", 3) == 0
5935 && (s[3] == '.' || ! is_part_of_name (s[3])))
5936 || (strncasecmp (s, "OR", 2) == 0
5937 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5938 break;
252b5132
RH		 5939 }
5940
5941 *rightstart = input_line_pointer;
5942 *rightstop = s;
5943 if (*rightstop > *rightstart
5944 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5945 --*rightstop;
5946
5947 input_line_pointer = s;
5948
5949 return 1;
5950}
5951
5952#define MCC(b1, b2) (((b1) << 8) | (b2))
5953
5954/* Swap the sense of a condition. This changes the condition so that
5955 it generates the same result when the operands are swapped. */
5956
5957static int
31302357 5958swap_mri_condition (int cc)
252b5132
RH		 5959{
5960 switch (cc)
5961 {
5962 case MCC ('h', 'i'): return MCC ('c', 's');
5963 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 5964 /* <HS> is an alias for <CC>. */
e1f44d10 5965 case MCC ('h', 's'):
252b5132 5966 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 5967 /* <LO> is an alias for <CS>. */
e1f44d10 5968 case MCC ('l', 'o'):
252b5132
RH		 5969 case MCC ('c', 's'): return MCC ('h', 'i');
5970 case MCC ('p', 'l'): return MCC ('m', 'i');
5971 case MCC ('m', 'i'): return MCC ('p', 'l');
5972 case MCC ('g', 'e'): return MCC ('l', 'e');
5973 case MCC ('l', 't'): return MCC ('g', 't');
5974 case MCC ('g', 't'): return MCC ('l', 't');
5975 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 5976 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 5977 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5978 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5979 case MCC ('v', 'c'):
5980 case MCC ('v', 's'):
5981 default :
5982 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5983 (char) (cc >> 8), (char) (cc));
5984 break;
252b5132
RH		 5985 }
5986 return cc;
5987}
5988
5989/* Reverse the sense of a condition. */
5990
5991static int
31302357 5992reverse_mri_condition (int cc)
252b5132
RH		 5993{
5994 switch (cc)
5995 {
5996 case MCC ('h', 'i'): return MCC ('l', 's');
5997 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5998 /* <HS> is an alias for <CC> */
5999 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6000 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6001 /* <LO> is an alias for <CS> */
6002 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6003 case MCC ('c', 's'): return MCC ('c', 'c');
6004 case MCC ('n', 'e'): return MCC ('e', 'q');
6005 case MCC ('e', 'q'): return MCC ('n', 'e');
6006 case MCC ('v', 'c'): return MCC ('v', 's');
6007 case MCC ('v', 's'): return MCC ('v', 'c');
6008 case MCC ('p', 'l'): return MCC ('m', 'i');
6009 case MCC ('m', 'i'): return MCC ('p', 'l');
6010 case MCC ('g', 'e'): return MCC ('l', 't');
6011 case MCC ('l', 't'): return MCC ('g', 'e');
6012 case MCC ('g', 't'): return MCC ('l', 'e');
6013 case MCC ('l', 'e'): return MCC ('g', 't');
6014 }
6015 return cc;
6016}
6017
6018/* Build an MRI structured control expression. This generates test
6019 and branch instructions. It goes to TRUELAB if the condition is
6020 true, and to FALSELAB if the condition is false. Exactly one of
6021 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6022 is the size qualifier for the expression. EXTENT is the size to
6023 use for the branch. */
6024
6025static void
31302357
AS		 6026build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6027 char *rightstart, char *rightstop,
6028 const char *truelab, const char *falselab,
6029 int extent)
252b5132
RH		 6030{
6031 char *buf;
6032 char *s;
6033
6034 if (leftstart != NULL)
6035 {
6036 struct m68k_op leftop, rightop;
6037 char c;
6038
6039 /* Swap the compare operands, if necessary, to produce a legal
6040 m68k compare instruction. Comparing a register operand with
6041 a non-register operand requires the register to be on the
6042 right (cmp, cmpa). Comparing an immediate value with
6043 anything requires the immediate value to be on the left
6044 (cmpi). */
6045
6046 c = *leftstop;
6047 *leftstop = '\0';
6048 (void) m68k_ip_op (leftstart, &leftop);
6049 *leftstop = c;
6050
6051 c = *rightstop;
6052 *rightstop = '\0';
6053 (void) m68k_ip_op (rightstart, &rightop);
6054 *rightstop = c;
6055
6056 if (rightop.mode == IMMED
6057 || ((leftop.mode == DREG || leftop.mode == AREG)
6058 && (rightop.mode != DREG && rightop.mode != AREG)))
6059 {
6060 char *temp;
6061
31302357
AS		 6062 /* Correct conditional handling:
6063 if #1 <lt> d0 then ;means if (1 < d0)
6064 ...
6065 endi
e1f44d10 6066
31302357 6067 should assemble to:
e1f44d10 6068
31302357
AS		 6069 cmp #1,d0 if we do *not* swap the operands
6070 bgt true we need the swapped condition!
6071 ble false
6072 true:
6073 ...
6074 false:
6075 */
252b5132
RH		 6076 temp = leftstart;
6077 leftstart = rightstart;
6078 rightstart = temp;
6079 temp = leftstop;
6080 leftstop = rightstop;
6081 rightstop = temp;
8a104df9
KH		 6082 }
6083 else
6084 {
e1f44d10 6085 cc = swap_mri_condition (cc);
252b5132
RH		 6086 }
6087 }
6088
6089 if (truelab == NULL)
6090 {
6091 cc = reverse_mri_condition (cc);
6092 truelab = falselab;
6093 }
92774660 6094
252b5132
RH		 6095 if (leftstart != NULL)
6096 {
6097 buf = (char *) xmalloc (20
6098 + (leftstop - leftstart)
6099 + (rightstop - rightstart));
6100 s = buf;
6101 *s++ = 'c';
6102 *s++ = 'm';
6103 *s++ = 'p';
6104 if (qual != '\0')
3882b010 6105 *s++ = TOLOWER (qual);
252b5132
RH		 6106 *s++ = ' ';
6107 memcpy (s, leftstart, leftstop - leftstart);
6108 s += leftstop - leftstart;
6109 *s++ = ',';
6110 memcpy (s, rightstart, rightstop - rightstart);
6111 s += rightstop - rightstart;
6112 *s = '\0';
6113 mri_assemble (buf);
6114 free (buf);
6115 }
92774660 6116
252b5132
RH		 6117 buf = (char *) xmalloc (20 + strlen (truelab));
6118 s = buf;
6119 *s++ = 'b';
6120 *s++ = cc >> 8;
6121 *s++ = cc & 0xff;
6122 if (extent != '\0')
3882b010 6123 *s++ = TOLOWER (extent);
252b5132
RH		 6124 *s++ = ' ';
6125 strcpy (s, truelab);
6126 mri_assemble (buf);
6127 free (buf);
6128}
6129
6130/* Parse an MRI structured control expression. This generates test
6131 and branch instructions. STOP is where the expression ends. It
6132 goes to TRUELAB if the condition is true, and to FALSELAB if the
6133 condition is false. Exactly one of TRUELAB and FALSELAB will be
6134 NULL, meaning to fall through. QUAL is the size qualifier for the
6135 expression. EXTENT is the size to use for the branch. */
6136
6137static void
31302357
AS		 6138parse_mri_control_expression (char *stop, int qual, const char *truelab,
6139 const char *falselab, int extent)
252b5132
RH		 6140{
6141 int c;
6142 int cc;
6143 char *leftstart;
6144 char *leftstop;
6145 char *rightstart;
6146 char *rightstop;
6147
6148 c = *stop;
6149 *stop = '\0';
6150
6151 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6152 &rightstart, &rightstop))
6153 {
6154 *stop = c;
6155 return;
6156 }
6157
6158 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6159 {
6160 const char *flab;
6161
6162 if (falselab != NULL)
6163 flab = falselab;
6164 else
6165 flab = mri_control_label ();
6166
6167 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6168 rightstop, (const char *) NULL, flab, extent);
6169
6170 input_line_pointer += 3;
6171 if (*input_line_pointer != '.'
6172 || input_line_pointer[1] == '\0')
6173 qual = '\0';
6174 else
6175 {
6176 qual = input_line_pointer[1];
6177 input_line_pointer += 2;
6178 }
6179
6180 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6181 &rightstart, &rightstop))
6182 {
6183 *stop = c;
6184 return;
6185 }
6186
6187 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6188 rightstop, truelab, falselab, extent);
6189
6190 if (falselab == NULL)
6191 colon (flab);
6192 }
6193 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6194 {
6195 const char *tlab;
6196
6197 if (truelab != NULL)
6198 tlab = truelab;
6199 else
6200 tlab = mri_control_label ();
6201
6202 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6203 rightstop, tlab, (const char *) NULL, extent);
6204
6205 input_line_pointer += 2;
6206 if (*input_line_pointer != '.'
6207 || input_line_pointer[1] == '\0')
6208 qual = '\0';
6209 else
6210 {
6211 qual = input_line_pointer[1];
6212 input_line_pointer += 2;
6213 }
6214
6215 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6216 &rightstart, &rightstop))
6217 {
6218 *stop = c;
6219 return;
6220 }
6221
6222 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6223 rightstop, truelab, falselab, extent);
6224
6225 if (truelab == NULL)
6226 colon (tlab);
6227 }
6228 else
6229 {
6230 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6231 rightstop, truelab, falselab, extent);
6232 }
6233
6234 *stop = c;
6235 if (input_line_pointer != stop)
6236 as_bad (_("syntax error in structured control directive"));
6237}
6238
6239/* Handle the MRI IF pseudo-op. This may be a structured control
6240 directive, or it may be a regular assembler conditional, depending
6241 on its operands. */
6242
6243static void
31302357 6244s_mri_if (int qual)
252b5132
RH		 6245{
6246 char *s;
6247 int c;
6248 struct mri_control_info *n;
6249
6250 /* A structured control directive must end with THEN with an
6251 optional qualifier. */
6252 s = input_line_pointer;
e1f44d10
NC		 6253 /* We only accept '*' as introduction of comments if preceded by white space
6254 or at first column of a line (I think this can't actually happen here?)
6255 This is important when assembling:
6256 if d0 <ne> 12(a0,d0*2) then
36759679 6257 if d0 <ne> #CONST*20 then. */
31302357
AS		 6258 while (! (is_end_of_line[(unsigned char) *s]
6259 || (flag_mri
6260 && *s == '*'
6261 && (s == input_line_pointer
6262 || *(s-1) == ' '
6263 || *(s-1) == '\t'))))
252b5132
RH		 6264 ++s;
6265 --s;
6266 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6267 --s;
6268
6269 if (s - input_line_pointer > 1
6270 && s[-1] == '.')
6271 s -= 2;
6272
6273 if (s - input_line_pointer < 3
6274 || strncasecmp (s - 3, "THEN", 4) != 0)
6275 {
6276 if (qual != '\0')
6277 {
6278 as_bad (_("missing then"));
6279 ignore_rest_of_line ();
6280 return;
6281 }
6282
6283 /* It's a conditional. */
6284 s_if (O_ne);
6285 return;
6286 }
6287
6288 /* Since this might be a conditional if, this pseudo-op will be
6289 called even if we are supported to be ignoring input. Double
6290 check now. Clobber *input_line_pointer so that ignore_input
6291 thinks that this is not a special pseudo-op. */
6292 c = *input_line_pointer;
6293 *input_line_pointer = 0;
6294 if (ignore_input ())
6295 {
6296 *input_line_pointer = c;
6297 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6298 ++input_line_pointer;
6299 demand_empty_rest_of_line ();
6300 return;
6301 }
6302 *input_line_pointer = c;
6303
6304 n = push_mri_control (mri_if);
6305
6306 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6307 n->next, s[1] == '.' ? s[2] : '\0');
6308
6309 if (s[1] == '.')
6310 input_line_pointer = s + 3;
6311 else
6312 input_line_pointer = s + 1;
6313
6314 if (flag_mri)
6315 {
6316 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6317 ++input_line_pointer;
6318 }
6319
6320 demand_empty_rest_of_line ();
6321}
6322
6323/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6324 structured IF, associate the ELSE with the IF. Otherwise, assume
6325 it is a conditional else. */
6326
6327static void
31302357 6328s_mri_else (int qual)
252b5132
RH		 6329{
6330 int c;
6331 char *buf;
6332 char q[2];
6333
6334 if (qual == '\0'
6335 && (mri_control_stack == NULL
6336 || mri_control_stack->type != mri_if
6337 || mri_control_stack->else_seen))
6338 {
6339 s_else (0);
6340 return;
6341 }
6342
6343 c = *input_line_pointer;
6344 *input_line_pointer = 0;
6345 if (ignore_input ())
6346 {
6347 *input_line_pointer = c;
6348 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6349 ++input_line_pointer;
6350 demand_empty_rest_of_line ();
6351 return;
6352 }
6353 *input_line_pointer = c;
6354
6355 if (mri_control_stack == NULL
6356 || mri_control_stack->type != mri_if
6357 || mri_control_stack->else_seen)
6358 {
6359 as_bad (_("else without matching if"));
6360 ignore_rest_of_line ();
6361 return;
6362 }
6363
6364 mri_control_stack->else_seen = 1;
6365
6366 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6367 q[0] = TOLOWER (qual);
252b5132
RH		 6368 q[1] = '\0';
6369 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6370 mri_assemble (buf);
6371 free (buf);
6372
6373 colon (mri_control_stack->next);
6374
6375 if (flag_mri)
6376 {
6377 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6378 ++input_line_pointer;
6379 }
6380
6381 demand_empty_rest_of_line ();
6382}
6383
6384/* Handle the MRI ENDI pseudo-op. */
6385
6386static void
31302357 6387s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6388{
6389 if (mri_control_stack == NULL
6390 || mri_control_stack->type != mri_if)
6391 {
6392 as_bad (_("endi without matching if"));
6393 ignore_rest_of_line ();
6394 return;
6395 }
6396
6397 /* ignore_input will not return true for ENDI, so we don't need to
6398 worry about checking it again here. */
6399
6400 if (! mri_control_stack->else_seen)
6401 colon (mri_control_stack->next);
6402 colon (mri_control_stack->bottom);
6403
6404 pop_mri_control ();
6405
6406 if (flag_mri)
6407 {
6408 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6409 ++input_line_pointer;
6410 }
6411
6412 demand_empty_rest_of_line ();
6413}
6414
6415/* Handle the MRI BREAK pseudo-op. */
6416
6417static void
31302357 6418s_mri_break (int extent)
252b5132
RH		 6419{
6420 struct mri_control_info *n;
6421 char *buf;
6422 char ex[2];
6423
6424 n = mri_control_stack;
6425 while (n != NULL
6426 && n->type != mri_for
6427 && n->type != mri_repeat
6428 && n->type != mri_while)
6429 n = n->outer;
6430 if (n == NULL)
6431 {
6432 as_bad (_("break outside of structured loop"));
6433 ignore_rest_of_line ();
6434 return;
6435 }
6436
6437 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6438 ex[0] = TOLOWER (extent);
252b5132
RH		 6439 ex[1] = '\0';
6440 sprintf (buf, "bra%s %s", ex, n->bottom);
6441 mri_assemble (buf);
6442 free (buf);
6443
6444 if (flag_mri)
6445 {
6446 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6447 ++input_line_pointer;
6448 }
6449
6450 demand_empty_rest_of_line ();
6451}
6452
6453/* Handle the MRI NEXT pseudo-op. */
6454
6455static void
31302357 6456s_mri_next (int extent)
252b5132
RH		 6457{
6458 struct mri_control_info *n;
6459 char *buf;
6460 char ex[2];
6461
6462 n = mri_control_stack;
6463 while (n != NULL
6464 && n->type != mri_for
6465 && n->type != mri_repeat
6466 && n->type != mri_while)
6467 n = n->outer;
6468 if (n == NULL)
6469 {
6470 as_bad (_("next outside of structured loop"));
6471 ignore_rest_of_line ();
6472 return;
6473 }
6474
6475 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6476 ex[0] = TOLOWER (extent);
252b5132
RH		 6477 ex[1] = '\0';
6478 sprintf (buf, "bra%s %s", ex, n->next);
6479 mri_assemble (buf);
6480 free (buf);
6481
6482 if (flag_mri)
6483 {
6484 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6485 ++input_line_pointer;
6486 }
6487
6488 demand_empty_rest_of_line ();
6489}
6490
6491/* Handle the MRI FOR pseudo-op. */
6492
6493static void
31302357 6494s_mri_for (int qual)
252b5132
RH		 6495{
6496 const char *varstart, *varstop;
6497 const char *initstart, *initstop;
6498 const char *endstart, *endstop;
6499 const char *bystart, *bystop;
6500 int up;
6501 int by;
6502 int extent;
6503 struct mri_control_info *n;
6504 char *buf;
6505 char *s;
6506 char ex[2];
6507
6508 /* The syntax is
6509 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6510 */
6511
6512 SKIP_WHITESPACE ();
6513 varstart = input_line_pointer;
6514
6515 /* Look for the '='. */
6516 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6517 && *input_line_pointer != '=')
6518 ++input_line_pointer;
6519 if (*input_line_pointer != '=')
6520 {
6521 as_bad (_("missing ="));
6522 ignore_rest_of_line ();
6523 return;
6524 }
6525
6526 varstop = input_line_pointer;
6527 if (varstop > varstart
6528 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6529 --varstop;
6530
6531 ++input_line_pointer;
6532
6533 initstart = input_line_pointer;
6534
6535 /* Look for TO or DOWNTO. */
6536 up = 1;
6537 initstop = NULL;
6538 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6539 {
6540 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6541 && ! is_part_of_name (input_line_pointer[2]))
6542 {
6543 initstop = input_line_pointer;
6544 input_line_pointer += 2;
6545 break;
6546 }
6547 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6548 && ! is_part_of_name (input_line_pointer[6]))
6549 {
6550 initstop = input_line_pointer;
6551 up = 0;
6552 input_line_pointer += 6;
6553 break;
6554 }
6555 ++input_line_pointer;
6556 }
6557 if (initstop == NULL)
6558 {
6559 as_bad (_("missing to or downto"));
6560 ignore_rest_of_line ();
6561 return;
6562 }
6563 if (initstop > initstart
6564 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6565 --initstop;
6566
6567 SKIP_WHITESPACE ();
6568 endstart = input_line_pointer;
6569
6570 /* Look for BY or DO. */
6571 by = 0;
6572 endstop = NULL;
6573 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6574 {
6575 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6576 && ! is_part_of_name (input_line_pointer[2]))
6577 {
6578 endstop = input_line_pointer;
6579 by = 1;
6580 input_line_pointer += 2;
6581 break;
6582 }
6583 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6584 && (input_line_pointer[2] == '.'
6585 || ! is_part_of_name (input_line_pointer[2])))
6586 {
6587 endstop = input_line_pointer;
6588 input_line_pointer += 2;
6589 break;
6590 }
6591 ++input_line_pointer;
6592 }
6593 if (endstop == NULL)
6594 {
6595 as_bad (_("missing do"));
6596 ignore_rest_of_line ();
6597 return;
6598 }
6599 if (endstop > endstart
6600 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6601 --endstop;
6602
6603 if (! by)
6604 {
6605 bystart = "#1";
6606 bystop = bystart + 2;
6607 }
6608 else
6609 {
6610 SKIP_WHITESPACE ();
6611 bystart = input_line_pointer;
6612
6613 /* Look for DO. */
6614 bystop = NULL;
6615 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6616 {
6617 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6618 && (input_line_pointer[2] == '.'
6619 || ! is_part_of_name (input_line_pointer[2])))
6620 {
6621 bystop = input_line_pointer;
6622 input_line_pointer += 2;
6623 break;
6624 }
6625 ++input_line_pointer;
6626 }
6627 if (bystop == NULL)
6628 {
6629 as_bad (_("missing do"));
6630 ignore_rest_of_line ();
6631 return;
6632 }
6633 if (bystop > bystart
6634 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6635 --bystop;
6636 }
6637
6638 if (*input_line_pointer != '.')
6639 extent = '\0';
6640 else
6641 {
6642 extent = input_line_pointer[1];
6643 input_line_pointer += 2;
6644 }
6645
6646 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6647 n = push_mri_control (mri_for);
6648
6649 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6650
36759679 6651 /* Move init,var. */
252b5132
RH		 6652 s = buf;
6653 *s++ = 'm';
6654 *s++ = 'o';
6655 *s++ = 'v';
6656 *s++ = 'e';
6657 if (qual != '\0')
3882b010 6658 *s++ = TOLOWER (qual);
252b5132
RH		 6659 *s++ = ' ';
6660 memcpy (s, initstart, initstop - initstart);
6661 s += initstop - initstart;
6662 *s++ = ',';
6663 memcpy (s, varstart, varstop - varstart);
6664 s += varstop - varstart;
6665 *s = '\0';
6666 mri_assemble (buf);
6667
6668 colon (n->top);
6669
36759679 6670 /* cmp end,var. */
252b5132
RH		 6671 s = buf;
6672 *s++ = 'c';
6673 *s++ = 'm';
6674 *s++ = 'p';
6675 if (qual != '\0')
3882b010 6676 *s++ = TOLOWER (qual);
252b5132
RH		 6677 *s++ = ' ';
6678 memcpy (s, endstart, endstop - endstart);
6679 s += endstop - endstart;
6680 *s++ = ',';
6681 memcpy (s, varstart, varstop - varstart);
6682 s += varstop - varstart;
6683 *s = '\0';
6684 mri_assemble (buf);
6685
36759679 6686 /* bcc bottom. */
3882b010 6687 ex[0] = TOLOWER (extent);
252b5132
RH		 6688 ex[1] = '\0';
6689 if (up)
6690 sprintf (buf, "blt%s %s", ex, n->bottom);
6691 else
6692 sprintf (buf, "bgt%s %s", ex, n->bottom);
6693 mri_assemble (buf);
6694
6695 /* Put together the add or sub instruction used by ENDF. */
6696 s = buf;
6697 if (up)
6698 strcpy (s, "add");
6699 else
6700 strcpy (s, "sub");
6701 s += 3;
6702 if (qual != '\0')
3882b010 6703 *s++ = TOLOWER (qual);
252b5132
RH		 6704 *s++ = ' ';
6705 memcpy (s, bystart, bystop - bystart);
6706 s += bystop - bystart;
6707 *s++ = ',';
6708 memcpy (s, varstart, varstop - varstart);
6709 s += varstop - varstart;
6710 *s = '\0';
6711 n->incr = buf;
6712
6713 if (flag_mri)
6714 {
6715 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6716 ++input_line_pointer;
6717 }
6718
6719 demand_empty_rest_of_line ();
6720}
6721
6722/* Handle the MRI ENDF pseudo-op. */
6723
6724static void
31302357 6725s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6726{
6727 if (mri_control_stack == NULL
6728 || mri_control_stack->type != mri_for)
6729 {
6730 as_bad (_("endf without for"));
6731 ignore_rest_of_line ();
6732 return;
6733 }
6734
6735 colon (mri_control_stack->next);
6736
6737 mri_assemble (mri_control_stack->incr);
6738
6739 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6740 mri_assemble (mri_control_stack->incr);
6741
6742 free (mri_control_stack->incr);
6743
6744 colon (mri_control_stack->bottom);
6745
6746 pop_mri_control ();
6747
6748 if (flag_mri)
6749 {
6750 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6751 ++input_line_pointer;
6752 }
6753
6754 demand_empty_rest_of_line ();
6755}
6756
6757/* Handle the MRI REPEAT pseudo-op. */
6758
6759static void
31302357 6760s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6761{
6762 struct mri_control_info *n;
6763
6764 n = push_mri_control (mri_repeat);
6765 colon (n->top);
6766 if (flag_mri)
6767 {
6768 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6769 ++input_line_pointer;
6770 }
6771 demand_empty_rest_of_line ();
6772}
6773
6774/* Handle the MRI UNTIL pseudo-op. */
6775
6776static void
31302357 6777s_mri_until (int qual)
252b5132
RH		 6778{
6779 char *s;
6780
6781 if (mri_control_stack == NULL
6782 || mri_control_stack->type != mri_repeat)
6783 {
6784 as_bad (_("until without repeat"));
6785 ignore_rest_of_line ();
6786 return;
6787 }
6788
6789 colon (mri_control_stack->next);
6790
6791 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6792 ;
6793
6794 parse_mri_control_expression (s, qual, (const char *) NULL,
6795 mri_control_stack->top, '\0');
6796
6797 colon (mri_control_stack->bottom);
6798
6799 input_line_pointer = s;
6800
6801 pop_mri_control ();
6802
6803 if (flag_mri)
6804 {
6805 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6806 ++input_line_pointer;
6807 }
6808
6809 demand_empty_rest_of_line ();
6810}
6811
6812/* Handle the MRI WHILE pseudo-op. */
6813
6814static void
31302357 6815s_mri_while (int qual)
252b5132
RH		 6816{
6817 char *s;
6818
6819 struct mri_control_info *n;
6820
6821 s = input_line_pointer;
e1f44d10
NC		 6822 /* We only accept '*' as introduction of comments if preceded by white space
6823 or at first column of a line (I think this can't actually happen here?)
6824 This is important when assembling:
6825 while d0 <ne> 12(a0,d0*2) do
36759679 6826 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6827 while (! (is_end_of_line[(unsigned char) *s]
6828 || (flag_mri
6829 && *s == '*'
6830 && (s == input_line_pointer
6831 || *(s-1) == ' '
6832 || *(s-1) == '\t'))))
252b5132
RH		 6833 s++;
6834 --s;
6835 while (*s == ' ' || *s == '\t')
6836 --s;
6837 if (s - input_line_pointer > 1
6838 && s[-1] == '.')
6839 s -= 2;
6840 if (s - input_line_pointer < 2
6841 || strncasecmp (s - 1, "DO", 2) != 0)
6842 {
6843 as_bad (_("missing do"));
6844 ignore_rest_of_line ();
6845 return;
6846 }
6847
6848 n = push_mri_control (mri_while);
6849
6850 colon (n->next);
6851
6852 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6853 s[1] == '.' ? s[2] : '\0');
6854
6855 input_line_pointer = s + 1;
6856 if (*input_line_pointer == '.')
6857 input_line_pointer += 2;
6858
6859 if (flag_mri)
6860 {
6861 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6862 ++input_line_pointer;
6863 }
6864
6865 demand_empty_rest_of_line ();
6866}
6867
6868/* Handle the MRI ENDW pseudo-op. */
6869
6870static void
31302357 6871s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6872{
6873 char *buf;
6874
6875 if (mri_control_stack == NULL
6876 || mri_control_stack->type != mri_while)
6877 {
6878 as_bad (_("endw without while"));
6879 ignore_rest_of_line ();
6880 return;
6881 }
6882
6883 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6884 sprintf (buf, "bra %s", mri_control_stack->next);
6885 mri_assemble (buf);
6886 free (buf);
6887
6888 colon (mri_control_stack->bottom);
6889
6890 pop_mri_control ();
6891
6892 if (flag_mri)
6893 {
6894 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6895 ++input_line_pointer;
6896 }
6897
6898 demand_empty_rest_of_line ();
6899}
6900\f
266abb8f
NS		 6901/* Parse a .cpu directive. */
6902
6903static void
6904s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6905{
6906 char saved_char;
6907 char *name;
6908
6909 if (initialized)
6910 {
6911 as_bad (_("already assembled instructions"));
6912 ignore_rest_of_line ();
6913 return;
6914 }
6915
6916 name = input_line_pointer;
6917 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6918 input_line_pointer++;
6919 saved_char = *input_line_pointer;
6920 *input_line_pointer = 0;
6921
6922 m68k_set_cpu (name, 1, 0);
6923
6924 *input_line_pointer = saved_char;
6925 demand_empty_rest_of_line ();
6926 return;
6927}
6928
6929/* Parse a .arch directive. */
6930
6931static void
6932s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6933{
6934 char saved_char;
6935 char *name;
6936
6937 if (initialized)
6938 {
6939 as_bad (_("already assembled instructions"));
6940 ignore_rest_of_line ();
6941 return;
6942 }
6943
6944 name = input_line_pointer;
6945 while (*input_line_pointer && *input_line_pointer != ','
6946 && !ISSPACE (*input_line_pointer))
6947 input_line_pointer++;
6948 saved_char = *input_line_pointer;
6949 *input_line_pointer = 0;
6950
6951 if (m68k_set_arch (name, 1, 0))
6952 {
6953 /* Scan extensions. */
6954 do
6955 {
6956 *input_line_pointer++ = saved_char;
6957 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
6958 break;
6959 name = input_line_pointer;
6960 while (*input_line_pointer && *input_line_pointer != ','
6961 && !ISSPACE (*input_line_pointer))
6962 input_line_pointer++;
6963 saved_char = *input_line_pointer;
6964 *input_line_pointer = 0;
6965 }
6966 while (m68k_set_extension (name, 1, 0));
6967 }
6968
6969 *input_line_pointer = saved_char;
6970 demand_empty_rest_of_line ();
6971 return;
6972}
6973\f
6974/* Lookup a cpu name in TABLE and return the slot found. Return NULL
6975 if none is found, the caller is responsible for emitting an error
6976 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
6977 cpu name, if it begins with a '6' (possibly skipping an intervening
6978 'c'. We also allow a 'c' in the same place. if NEGATED is
6979 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
6980 the option is indeed negated. */
6981
6982static const struct m68k_cpu *
6983m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
6984 int allow_m, int *negated)
6985{
6986 /* allow negated value? */
6987 if (negated)
6988 {
6989 *negated = 0;
6990
6991 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6992 {
6993 arg += 3;
6994 *negated = 1;
6995 }
6996 }
6997
6998 /* Remove 'm' or 'mc' prefix from 68k variants. */
6999 if (allow_m)
7000 {
7001 if (arg[0] == 'm')
7002 {
7003 if (arg[1] == '6')
7004 arg += 1;
7005 else if (arg[1] == 'c' && arg[2] == '6')
7006 arg += 2;
7007 }
7008 }
7009 else if (arg[0] == 'c' && arg[1] == '6')
7010 arg += 1;
7011
7012 for (; table->name; table++)
7013 if (!strcmp (arg, table->name))
2da12c60
NS		 7014 {
7015 if (table->alias < -1 || table->alias > 1)
7016 as_bad (_("`%s' is deprecated, use `%s'"),
7017 table->name, table[table->alias < 0 ? 1 : -1].name);
7018 return table;
7019 }
266abb8f
NS		 7020 return 0;
7021}
7022
7023/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7024
7025static int
7026m68k_set_cpu (char const *name, int allow_m, int silent)
7027{
7028 const struct m68k_cpu *cpu;
7029
7030 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7031
7032 if (!cpu)
7033 {
7034 if (!silent)
7035 as_bad (_("cpu `%s' unrecognized"), name);
7036 return 0;
7037 }
7038
7039 if (selected_cpu && selected_cpu != cpu)
7040 {
7041 as_bad (_("already selected `%s' processor"),
7042 selected_cpu->name);
7043 return 0;
7044 }
7045 selected_cpu = cpu;
7046 return 1;
7047}
7048
7049/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7050
7051static int
7052m68k_set_arch (char const *name, int allow_m, int silent)
7053{
7054 const struct m68k_cpu *arch;
7055
7056 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7057
7058 if (!arch)
7059 {
7060 if (!silent)
7061 as_bad (_("architecture `%s' unrecognized"), name);
7062 return 0;
7063 }
7064
7065 if (selected_arch && selected_arch != arch)
7066 {
7067 as_bad (_("already selected `%s' architecture"),
7068 selected_arch->name);
7069 return 0;
7070 }
7071
7072 selected_arch = arch;
7073 return 1;
7074}
7075
7076/* Set the architecture extension, issuing errors if it is
7077 unrecognized, or invalid */
7078
7079static int
7080m68k_set_extension (char const *name, int allow_m, int silent)
7081{
7082 int negated;
7083 const struct m68k_cpu *ext;
7084
7085 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7086
7087 if (!ext)
7088 {
7089 if (!silent)
7090 as_bad (_("extension `%s' unrecognized"), name);
7091 return 0;
7092 }
7093
7094 if (negated)
7095 not_current_architecture |= ext->arch;
7096 else
7097 current_architecture |= ext->arch;
7098 return 1;
7099}
7100
31302357
AS		 7101/* md_parse_option
7102 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7103 */
252b5132
RH		 7104
7105#ifdef OBJ_ELF
5a38dc70 7106const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7107#else
5a38dc70 7108const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7109#endif
7110
7111struct option md_longopts[] = {
7112#define OPTION_PIC (OPTION_MD_BASE)
7113 {"pic", no_argument, NULL, OPTION_PIC},
7114#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7115 {"register-prefix-optional", no_argument, NULL,
7116 OPTION_REGISTER_PREFIX_OPTIONAL},
7117#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7118 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7119#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7120 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7121#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7122 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7123#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7124 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7125#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7126 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7127#define OPTION_PCREL (OPTION_MD_BASE + 7)
7128 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7129 {NULL, no_argument, NULL, 0}
7130};
bc805888 7131size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7132
7133int
31302357 7134md_parse_option (int c, char *arg)
252b5132
RH		 7135{
7136 switch (c)
7137 {
7138 case 'l': /* -l means keep external to 2 bit offset
36759679 7139 rather than 16 bit one. */
252b5132
RH		 7140 flag_short_refs = 1;
7141 break;
7142
7143 case 'S': /* -S means that jbsr's always turn into
7144 jsr's. */
7145 flag_long_jumps = 1;
7146 break;
7147
28e7409f
NC		 7148 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7149 branches into absolute jumps. */
7150 flag_keep_pcrel = 1;
7151 break;
7152
252b5132
RH		 7153 case OPTION_PIC:
7154 case 'k':
7155 flag_want_pic = 1;
36759679 7156 break; /* -pic, Position Independent Code. */
252b5132
RH		 7157
7158 case OPTION_REGISTER_PREFIX_OPTIONAL:
7159 flag_reg_prefix_optional = 1;
7160 reg_prefix_optional_seen = 1;
7161 break;
7162
7163 /* -V: SVR4 argument to print version ID. */
7164 case 'V':
7165 print_version_id ();
7166 break;
7167
7168 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7169 should be emitted or not. FIXME: Not implemented. */
7170 case 'Q':
7171 break;
7172
7173 case OPTION_BITWISE_OR:
7174 {
7175 char *n, *t;
7176 const char *s;
7177
7178 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7179 t = n;
7180 for (s = m68k_comment_chars; *s != '\0'; s++)
7181 if (*s != '|')
7182 *t++ = *s;
7183 *t = '\0';
7184 m68k_comment_chars = n;
7185 }
7186 break;
7187
7188 case OPTION_BASE_SIZE_DEFAULT_16:
7189 m68k_index_width_default = SIZE_WORD;
7190 break;
7191
7192 case OPTION_BASE_SIZE_DEFAULT_32:
7193 m68k_index_width_default = SIZE_LONG;
7194 break;
7195
7196 case OPTION_DISP_SIZE_DEFAULT_16:
7197 m68k_rel32 = 0;
7198 m68k_rel32_from_cmdline = 1;
7199 break;
7200
7201 case OPTION_DISP_SIZE_DEFAULT_32:
7202 m68k_rel32 = 1;
7203 m68k_rel32_from_cmdline = 1;
7204 break;
7205
266abb8f
NS		 7206 case 'A':
7207#if WARN_DEPRECATED
7208 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7209 arg, arg));
7210#endif
7211 /* Intentional fall-through. */
7212 case 'm':
7213 if (!strncmp (arg, "arch=", 5))
7214 m68k_set_arch (arg + 5, 1, 0);
7215 else if (!strncmp (arg, "cpu=", 4))
7216 m68k_set_cpu (arg + 4, 1, 0);
7217 else if (m68k_set_extension (arg, 0, 1))
7218 ;
0b2e31dc
NS		 7219 else if (m68k_set_arch (arg, 0, 1))
7220 ;
266abb8f
NS		 7221 else if (m68k_set_cpu (arg, 0, 1))
7222 ;
7223 else
7224 return 0;
7225 break;
7226
252b5132
RH		 7227 default:
7228 return 0;
7229 }
7230
7231 return 1;
7232}
7233
266abb8f
NS		 7234/* Setup tables from the selected arch and/or cpu */
7235
7236static void
7237m68k_init_arch (void)
7238{
266abb8f
NS		 7239 if (not_current_architecture & current_architecture)
7240 {
7241 as_bad (_("architecture features both enabled and disabled"));
7242 not_current_architecture &= ~current_architecture;
7243 }
7244 if (selected_arch)
2da12c60
NS		 7245 {
7246 current_architecture |= selected_arch->arch;
7247 control_regs = selected_arch->control_regs;
7248 }
0b2e31dc
NS		 7249 else
7250 current_architecture |= selected_cpu->arch;
0b2e31dc 7251
2da12c60
NS		 7252 current_architecture &= ~not_current_architecture;
7253
377260ba
NS		 7254 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7255 {
7256 /* Determine which float is really meant. */
7257 if (current_architecture & (m68k_mask & ~m68881))
7258 current_architecture ^= cfloat;
7259 else
7260 current_architecture ^= m68881;
7261 }
7262
0b2e31dc 7263 if (selected_cpu)
266abb8f 7264 {
2da12c60 7265 control_regs = selected_cpu->control_regs;
0b2e31dc 7266 if (current_architecture & ~selected_cpu->arch)
266abb8f 7267 {
0b2e31dc
NS		 7268 as_bad (_("selected processor does not have all features of selected architecture"));
7269 current_architecture
7270 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7271 }
7272 }
266abb8f 7273
266abb8f
NS		 7274 if ((current_architecture & m68k_mask)
7275 && (current_architecture & ~m68k_mask))
7276 {
7277 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7278 if (current_architecture & m68k_mask)
266abb8f
NS		 7279 current_architecture &= m68k_mask;
7280 else
7281 current_architecture &= ~m68k_mask;
7282 }
7283
7284 /* Permit m68881 specification with all cpus; those that can't work
7285 with a coprocessor could be doing emulation. */
7286 if (current_architecture & m68851)
7287 {
7288 if (current_architecture & m68040)
7289 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7290 }
7291 /* What other incompatibilities could we check for? */
7292
266abb8f
NS		 7293 if (cpu_of_arch (current_architecture) < m68020
7294 || arch_coldfire_p (current_architecture))
7295 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7296
7297 initialized = 1;
7298}
7299
252b5132 7300void
31302357 7301md_show_usage (FILE *stream)
252b5132 7302{
76f57f3a 7303 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7304 int i;
7305 unsigned int default_arch;
76f57f3a 7306
8a104df9 7307 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7308 if (*default_cpu == 'm')
7309 default_cpu++;
266abb8f 7310 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7311 {
266abb8f 7312 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7313 {
266abb8f 7314 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7315 while (m68k_cpus[i].alias > 0)
7316 i--;
7317 while (m68k_cpus[i].alias < 0)
7318 i++;
7319 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7320 }
7321 }
7322
bc805888 7323 fprintf (stream, _("\
266abb8f
NS		 7324-march=<arch> set architecture\n\
7325-mcpu=<cpu> set cpu [default %s]\n\
7326"), default_cpu);
7327 for (i = 0; m68k_extensions[i].name; i++)
7328 fprintf (stream, _("\
0b2e31dc
NS		 7329-m[no-]%-16s enable/disable%s architecture extension\n\
7330"), m68k_extensions[i].name,
7331 m68k_extensions[i].alias > 0 ? " ColdFire"
7332 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7333
bc805888 7334 fprintf (stream, _("\
266abb8f 7335-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7336-pic, -k generate position independent code\n\
7337-S turn jbsr into jsr\n\
28e7409f 7338--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7339--register-prefix-optional\n\
7340 recognize register names without prefix character\n\
266abb8f 7341--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7342--base-size-default-16 base reg without size is 16 bits\n\
7343--base-size-default-32 base reg without size is 32 bits (default)\n\
7344--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7345--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7346"));
7347
7348 fprintf (stream, _("Architecture variants are: "));
7349 for (i = 0; m68k_archs[i].name; i++)
7350 {
7351 if (i)
7352 fprintf (stream, " | ");
7353 fprintf (stream, m68k_archs[i].name);
7354 }
7355 fprintf (stream, "\n");
7356
7357 fprintf (stream, _("Processor variants are: "));
7358 for (i = 0; m68k_cpus[i].name; i++)
7359 {
7360 if (i)
7361 fprintf (stream, " | ");
7362 fprintf (stream, m68k_cpus[i].name);
7363 }
7364 fprintf (stream, _("\n"));
252b5132
RH		 7365}
7366\f
7367#ifdef TEST2
7368
7369/* TEST2: Test md_assemble() */
36759679
NC		 7370/* Warning, this routine probably doesn't work anymore. */
7371int
31302357 7372main (void)
252b5132
RH		 7373{
7374 struct m68k_it the_ins;
7375 char buf[120];
7376 char *cp;
7377 int n;
7378
7379 m68k_ip_begin ();
7380 for (;;)
7381 {
7382 if (!gets (buf) || !*buf)
7383 break;
7384 if (buf[0] == '|' || buf[1] == '.')
7385 continue;
7386 for (cp = buf; *cp; cp++)
7387 if (*cp == '\t')
7388 *cp = ' ';
7389 if (is_label (buf))
7390 continue;
7391 memset (&the_ins, '\0', sizeof (the_ins));
7392 m68k_ip (&the_ins, buf);
7393 if (the_ins.error)
7394 {
7395 printf (_("Error %s in %s\n"), the_ins.error, buf);
7396 }
7397 else
7398 {
7399 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7400 for (n = 0; n < the_ins.numo; n++)
7401 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7402 printf (" ");
7403 print_the_insn (&the_ins.opcode[0], stdout);
7404 (void) putchar ('\n');
7405 }
7406 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7407 {
7408 if (the_ins.operands[n].error)
7409 {
7410 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7411 continue;
7412 }
31302357
AS		 7413 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7414 the_ins.operands[n].reg);
252b5132 7415 if (the_ins.operands[n].b_const)
31302357
AS		 7416 printf ("Constant: '%.*s', ",
7417 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7418 the_ins.operands[n].b_const);
7419 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7420 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7421 if (the_ins.operands[n].b_iadd)
31302357
AS		 7422 printf ("Iadd: '%.*s',",
7423 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7424 the_ins.operands[n].b_iadd);
7425 putchar ('\n');
252b5132
RH		 7426 }
7427 }
7428 m68k_ip_end ();
7429 return 0;
7430}
7431
31302357
AS		 7432int
7433is_label (char *str)
252b5132
RH		 7434{
7435 while (*str == ' ')
7436 str++;
7437 while (*str && *str != ' ')
7438 str++;
7439 if (str[-1] == ':' || str[1] == '=')
7440 return 1;
7441 return 0;
7442}
7443
7444#endif
7445
7446/* Possible states for relaxation:
7447
7448 0 0 branch offset byte (bra, etc)
7449 0 1 word
7450 0 2 long
7451
7452 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7453 1 1 word
7454 1 2 long
7455
7456 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7457 2 1 word-long
7458 2 2 long-word
7459 2 3 long-long
7460
7461 */
7462
7463/* We have no need to default values of symbols. */
7464
252b5132 7465symbolS *
31302357 7466md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7467{
7468 return 0;
7469}
7470
7471/* Round up a section size to the appropriate boundary. */
7472valueT
31302357 7473md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7474{
7475#ifdef OBJ_AOUT
252b5132
RH		 7476 /* For a.out, force the section size to be aligned. If we don't do
7477 this, BFD will align it for us, but it will not write out the
7478 final bytes of the section. This may be a bug in BFD, but it is
7479 easier to fix it here since that is how the other a.out targets
7480 work. */
7481 int align;
7482
7483 align = bfd_get_section_alignment (stdoutput, segment);
7484 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7485#endif
7486
7487 return size;
7488}
7489
7490/* Exactly what point is a PC-relative offset relative TO?
7491 On the 68k, it is relative to the address of the first extension
7492 word. The difference between the addresses of the offset and the
92774660 7493 first extension word is stored in fx_pcrel_adjust. */
252b5132 7494long
31302357 7495md_pcrel_from (fixS *fixP)
252b5132
RH		 7496{
7497 int adjust;
7498
8390138c
AS		 7499 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7500 sign extend the value here. */
7501 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7502 if (adjust == 64)
7503 adjust = -1;
7504 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7505}
7506
0d96863f 7507#ifdef OBJ_ELF
8a104df9 7508void
31302357 7509m68k_elf_final_processing (void)
0d96863f 7510{
266abb8f
NS		 7511 unsigned flags = 0;
7512
238d258f 7513 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7514 flags |= EF_M68K_CFV4E;
7515 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7516 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7517 flags |= EF_M68K_CPU32;
7518 else if (cpu_of_arch (current_architecture) & fido_a)
7519 flags |= EF_M68K_FIDO;
8a104df9
KH		 7520 else if ((cpu_of_arch (current_architecture) & m68000up)
7521 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7522 flags |= EF_M68K_M68000;
7523
7524 if (current_architecture & mcfisa_a)
7525 {
0b2e31dc
NS		 7526 static const unsigned isa_features[][2] =
7527 {
c694fd50
KH		 7528 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7529 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7530 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7531 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7532 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
0b2e31dc
NS		 7533 {0,0},
7534 };
7535 static const unsigned mac_features[][2] =
7536 {
c694fd50
KH		 7537 {EF_M68K_CF_MAC, mcfmac},
7538 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7539 {0,0},
7540 };
7541 unsigned ix;
7542 unsigned pattern;
266abb8f 7543
0b2e31dc
NS		 7544 pattern = (current_architecture
7545 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7546 for (ix = 0; isa_features[ix][1]; ix++)
7547 {
7548 if (pattern == isa_features[ix][1])
7549 {
7550 flags |= isa_features[ix][0];
7551 break;
7552 }
7553 }
7554 if (!isa_features[ix][1])
7555 {
7556 cf_bad:
7557 as_warn (_("Not a defined coldfire architecture"));
7558 }
7559 else
7560 {
7561 if (current_architecture & cfloat)
c694fd50 7562 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7563
0b2e31dc
NS		 7564 pattern = current_architecture & (mcfmac|mcfemac);
7565 if (pattern)
7566 {
7567 for (ix = 0; mac_features[ix][1]; ix++)
7568 {
7569 if (pattern == mac_features[ix][1])
7570 {
7571 flags |= mac_features[ix][0];
7572 break;
7573 }
7574 }
7575 if (!mac_features[ix][1])
7576 goto cf_bad;
7577 }
7578 }
266abb8f
NS		 7579 }
7580 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f
CM		 7581}
7582#endif
c04898f8
AS		 7583
7584int
1df69f4f 7585tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 7586{
7587 unsigned int regnum;
7588 static const char *const regnames[] =
7589 {
7590 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7591 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7592 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7593 "pc"
7594 };
7595
7596 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7597 if (strcmp (regname, regnames[regnum]) == 0)
7598 return regnum;
7599
7600 return -1;
7601}
7602
7603void
7604tc_m68k_frame_initial_instructions (void)
7605{
7606 static int sp_regno = -1;
7607
7608 if (sp_regno < 0)
7609 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7610
7611 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7612 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7613}
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