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Port dw2gencfi.c to str_htab.
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
b3adc24a 2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
252b5132 21#include "as.h"
3882b010 22#include "safe-ctype.h"
252b5132
RH		 23#include "obstack.h"
24#include "subsegs.h"
f27a3839 25#include "dwarf2dbg.h"
c04898f8 26#include "dw2gencfi.h"
252b5132
RH		 27
28#include "opcode/m68k.h"
29#include "m68k-parse.h"
0d96863f 30#include "elf/m68k.h"
31302357 31
cf869cce 32static void m68k_elf_cons (int);
85f7484a 33static void m68k_elf_gnu_attribute (int);
cf869cce 34
252b5132
RH		 35/* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39#if defined (TE_SVR4) || defined (TE_DELTA)
40const char *m68k_comment_chars = "|#";
41#else
42const char *m68k_comment_chars = "|";
43#endif
44
45/* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48/* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
92774660
KH		 50 #NO_APP at the beginning of its output. */
51/* Also note that comments like this one will always work. */
252b5132
RH		 52const char line_comment_chars[] = "#*";
53
63a0b638 54const char line_separator_chars[] = ";";
252b5132 55
36759679 56/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 57const char EXP_CHARS[] = "eE";
252b5132
RH		 58
59/* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
61
5a38dc70 62const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 63
64/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
67
252b5132
RH		 68/* Are we trying to generate PIC code? If so, absolute references
69 ought to be made into linkage table references or pc-relative
92774660 70 references. Not implemented. For ELF there are other means
252b5132
RH		 71 to denote pic relocations. */
72int flag_want_pic;
73
36759679
NC		 74static int flag_short_refs; /* -l option. */
75static int flag_long_jumps; /* -S option. */
28e7409f 76static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 77
78#ifdef REGISTER_PREFIX_OPTIONAL
79int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
80#else
81int flag_reg_prefix_optional;
82#endif
83
84/* Whether --register-prefix-optional was used on the command line. */
85static int reg_prefix_optional_seen;
86
87/* The floating point coprocessor to use by default. */
88static enum m68k_register m68k_float_copnum = COP1;
89
90/* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92static int m68k_abspcadd;
93
94/* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96static int m68k_quick = 1;
97
98/* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
100 be 32 bits. */
101static int m68k_rel32 = 1;
102
103/* This is non-zero if m68k_rel32 was set from the command line. */
104static int m68k_rel32_from_cmdline;
105
106/* The default width to use for an index register when using a base
107 displacement. */
108static enum m68k_size m68k_index_width_default = SIZE_LONG;
109
110/* We want to warn if any text labels are misaligned. In order to get
111 the right line number, we need to record the line number for each
112 label. */
252b5132
RH		 113struct label_line
114{
115 struct label_line *next;
116 symbolS *label;
3b4dbbbf 117 const char *file;
252b5132
RH		 118 unsigned int line;
119 int text;
120};
121
122/* The list of labels. */
123
124static struct label_line *labels;
125
126/* The current label. */
127
128static struct label_line *current_label;
129
60fed2d3
NC		 130/* Pointer to list holding the opcodes sorted by name. */
131static struct m68k_opcode const ** m68k_sorted_opcodes;
132
33eaf5de 133/* It's an arbitrary name: This means I don't approve of it.
36759679 134 See flames below. */
252b5132
RH		 135static struct obstack robyn;
136
252b5132
RH		 137struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148#define gettwo(x) (((x)->m_opcode)&0xffff)
149
2da12c60
NS		 150static const enum m68k_register m68000_ctrl[] = { 0 };
151static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 152 SFC, DFC, USP, VBR,
153 0
154};
2da12c60 155static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158};
2da12c60 159static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163};
2da12c60 164static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168};
2da12c60 169static const enum m68k_register mcf_ctrl[] = {
3e602632 170 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 171 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
172 0
173};
87298967
NS		 174static const enum m68k_register mcf51_ctrl[] = {
175 VBR, CPUCR,
f75192f2
KH		 176 0
177};
78336706 178static const enum m68k_register mcf5206_ctrl[] = {
0d999f33 179 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 180 0
181};
2da12c60 182static const enum m68k_register mcf5208_ctrl[] = {
78336706 183 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 184 0
185};
96e0bbcc 186static const enum m68k_register mcf5210a_ctrl[] = {
78336706 187 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 188 0
189};
2da12c60 190static const enum m68k_register mcf5213_ctrl[] = {
78336706 191 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 192 0
193};
2da12c60 194static const enum m68k_register mcf5216_ctrl[] = {
78336706 195 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 196 0
197};
46203761
MK		 198static const enum m68k_register mcf5221x_ctrl[] = {
199 VBR, FLASHBAR, RAMBAR, RAMBAR1,
200 0
201};
d5be9593 202static const enum m68k_register mcf52223_ctrl[] = {
0d999f33 203 VBR, FLASHBAR, RAMBAR, RAMBAR1,
d5be9593
NS		 204 0
205};
96e0bbcc 206static const enum m68k_register mcf52235_ctrl[] = {
b345c8c2 207 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 208 0
209};
210static const enum m68k_register mcf5225_ctrl[] = {
78336706 211 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 212 0
213};
87298967
NS		 214static const enum m68k_register mcf52259_ctrl[] = {
215 VBR, FLASHBAR, RAMBAR, RAMBAR1,
216 0
217};
218static const enum m68k_register mcf52277_ctrl[] = {
219 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
220 0
221};
2da12c60 222static const enum m68k_register mcf5235_ctrl[] = {
78336706 223 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 224 0
225};
2da12c60 226static const enum m68k_register mcf5249_ctrl[] = {
78336706 227 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 228 0
229};
2da12c60
NS		 230static const enum m68k_register mcf5250_ctrl[] = {
231 VBR,
232 0
233};
d5be9593 234static const enum m68k_register mcf5253_ctrl[] = {
def8fc92 235 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
d5be9593
NS		 236 0
237};
2da12c60 238static const enum m68k_register mcf5271_ctrl[] = {
78336706 239 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 240 0
241};
242static const enum m68k_register mcf5272_ctrl[] = {
78336706 243 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 244 0
245};
246static const enum m68k_register mcf5275_ctrl[] = {
78336706 247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 248 0
249};
250static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 251 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
252 0
253};
87298967 254static const enum m68k_register mcf53017_ctrl[] = {
b345c8c2 255 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
87298967
NS		 256 0
257};
78336706 258static const enum m68k_register mcf5307_ctrl[] = {
87298967 259 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 260 0
261};
262static const enum m68k_register mcf5329_ctrl[] = {
78336706 263 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 264 0
265};
266static const enum m68k_register mcf5373_ctrl[] = {
78336706 267 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 268 0
269};
270static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 271 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
272 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
273 MBAR, SECMBAR,
274 MPCR /* Multiprocessor Control register */,
275 EDRAMBAR /* Embedded DRAM Base Address Register */,
276 /* Permutation control registers. */
3e602632
NC		 277 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
278 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 279 /* Legacy names */
280 TC /* ASID */, BUSCR /* MMUBAR */,
281 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
282 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 283 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 284 0
285};
def8fc92
KH		 286static const enum m68k_register mcf5407_ctrl[] = {
287 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
288 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
289 /* Legacy names */
290 TC /* ASID */,
291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
292 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
293 0
294};
0d999f33
MK		 295static const enum m68k_register mcf54418_ctrl[] = {
296 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
297 VBR, PC, RAMBAR1,
298 /* Legacy names */
299 TC /* ASID */, BUSCR /* MMUBAR */,
300 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
301 RAMBAR /* RAMBAR1 */,
302 0
303};
9a2e615a
NS		 304static const enum m68k_register mcf54455_ctrl[] = {
305 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
0d999f33 306 VBR, PC, RAMBAR1,
9a2e615a
NS		 307 /* Legacy names */
308 TC /* ASID */, BUSCR /* MMUBAR */,
309 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
0d999f33 310 RAMBAR /* RAMBAR1 */,
9a2e615a
NS		 311 0
312};
a8e24a56
NS		 313static const enum m68k_register mcf5475_ctrl[] = {
314 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
315 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
316 /* Legacy names */
317 TC /* ASID */, BUSCR /* MMUBAR */,
318 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 319 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 320 0
321};
322static const enum m68k_register mcf5485_ctrl[] = {
323 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
324 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
325 /* Legacy names */
326 TC /* ASID */, BUSCR /* MMUBAR */,
327 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 328 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 329 0
330};
f7ec513b 331static const enum m68k_register fido_ctrl[] = {
d0fa1372 332 SFC, DFC, USP, VBR, CAC, MBO,
f7ec513b
KH		 333 0
334};
2da12c60 335#define cpu32_ctrl m68010_ctrl
252b5132
RH		 336
337static const enum m68k_register *control_regs;
338
36759679 339/* Internal form of a 68020 instruction. */
252b5132
RH		 340struct m68k_it
341{
342 const char *error;
36759679 343 const char *args; /* List of opcode info. */
252b5132
RH		 344 int numargs;
345
36759679 346 int numo; /* Number of shorts in opcode. */
252b5132
RH		 347 short opcode[11];
348
349 struct m68k_op operands[6];
350
36759679 351 int nexp; /* Number of exprs in use. */
252b5132
RH		 352 struct m68k_exp exprs[4];
353
36759679 354 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 355 struct
356 {
36759679 357 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 358 symbolS *fadd;
359 offsetT foff;
360 int fragty;
361 }
362 fragb[4];
363
33eaf5de 364 int nrel; /* Num of reloc structs in use. */
252b5132
RH		 365 struct
366 {
367 int n;
368 expressionS exp;
369 char wid;
370 char pcrel;
371 /* In a pc relative address the difference between the address
372 of the offset and the address that the offset is relative
373 to. This depends on the addressing mode. Basically this
374 is the value to put in the offset field to address the
375 first byte of the offset, without regarding the special
376 significance of some values (in the branch instruction, for
377 example). */
378 int pcrel_fix;
252b5132
RH		 379 /* Whether this expression needs special pic relocation, and if
380 so, which. */
381 enum pic_relocation pic_reloc;
252b5132 382 }
36759679 383 reloc[5]; /* Five is enough??? */
252b5132
RH		 384};
385
9840d27e 386#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 387#define float_of_arch(x) ((x) & mfloat)
388#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 389#define arch_coldfire_p(x) ((x) & mcfisa_a)
390#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 391
36759679 392/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 393#define HAVE_LONG_DISP(x) \
394 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
395#define HAVE_LONG_CALL(x) \
396 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
397#define HAVE_LONG_COND(x) \
398 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
399#define HAVE_LONG_BRANCH(x) \
400 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
cac27205 401#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
252b5132 402
36759679 403static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 404
405#define op(ex) ((ex)->exp.X_op)
406#define adds(ex) ((ex)->exp.X_add_symbol)
407#define subs(ex) ((ex)->exp.X_op_symbol)
408#define offs(ex) ((ex)->exp.X_add_number)
409
36759679 410/* Macros for adding things to the m68k_it struct. */
31302357 411#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 412
36759679
NC		 413/* Like addword, but goes BEFORE general operands. */
414
252b5132 415static void
31302357 416insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 417{
418 int z;
07726851 419 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 420 the_ins.opcode[z] = the_ins.opcode[z - 1];
421 for (z = 0; z < the_ins.nrel; z++)
422 the_ins.reloc[z].n += 2;
252b5132
RH		 423 for (z = 0; z < the_ins.nfrag; z++)
424 the_ins.fragb[z].fragoff++;
8a104df9 425 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 426 the_ins.numo++;
427}
428
429/* The numo+1 kludge is so we can hit the low order byte of the prev word.
430 Blecch. */
431static void
31302357 432add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 433{
31302357
AS		 434 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
435 ? the_ins.numo * 2 - 1
436 : (width == 'b'
437 ? the_ins.numo * 2 + 1
438 : the_ins.numo * 2));
252b5132
RH		 439 the_ins.reloc[the_ins.nrel].exp = exp->exp;
440 the_ins.reloc[the_ins.nrel].wid = width;
441 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
252b5132 442 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
252b5132
RH		 443 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
444}
445
446/* Cause an extra frag to be generated here, inserting up to 10 bytes
447 (that value is chosen in the frag_var call in md_assemble). TYPE
448 is the subtype of the frag to be generated; its primary type is
449 rs_machine_dependent.
450
451 The TYPE parameter is also used by md_convert_frag_1 and
452 md_estimate_size_before_relax. The appropriate type of fixup will
453 be emitted by md_convert_frag_1.
454
455 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
456static void
31302357 457add_frag (symbolS *add, offsetT off, int type)
252b5132 458{
8a104df9
KH		 459 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
460 the_ins.fragb[the_ins.nfrag].fadd = add;
461 the_ins.fragb[the_ins.nfrag].foff = off;
462 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 463}
464
465#define isvar(ex) \
466 (op (ex) != O_constant && op (ex) != O_big)
467
31302357
AS		 468static char *crack_operand (char *str, struct m68k_op *opP);
469static int get_num (struct m68k_exp *exp, int ok);
470static int reverse_16_bits (int in);
471static int reverse_8_bits (int in);
472static void install_gen_operand (int mode, int val);
473static void install_operand (int mode, int val);
474static void s_bss (int);
475static void s_data1 (int);
476static void s_data2 (int);
477static void s_even (int);
478static void s_proc (int);
479static void s_chip (int);
480static void s_fopt (int);
481static void s_opt (int);
482static void s_reg (int);
483static void s_restore (int);
484static void s_save (int);
485static void s_mri_if (int);
486static void s_mri_else (int);
487static void s_mri_endi (int);
488static void s_mri_break (int);
489static void s_mri_next (int);
490static void s_mri_for (int);
491static void s_mri_endf (int);
492static void s_mri_repeat (int);
493static void s_mri_until (int);
494static void s_mri_while (int);
495static void s_mri_endw (int);
266abb8f
NS		 496static void s_m68k_cpu (int);
497static void s_m68k_arch (int);
498
499struct m68k_cpu
500{
501 unsigned long arch; /* Architecture features. */
2da12c60 502 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 503 const char *name; /* Name */
2b0f3761 504 int alias; /* Alias for a canonical name. If 1, then
0b2e31dc
NS		 505 succeeds canonical name, if -1 then
506 succeeds canonical name, if <-1 ||>1 this is a
507 deprecated name, and the next/previous name
508 should be used. */
266abb8f 509};
252b5132 510
266abb8f
NS		 511/* We hold flags for features explicitly enabled and explicitly
512 disabled. */
252b5132 513static int current_architecture;
266abb8f 514static int not_current_architecture;
266abb8f
NS		 515static const struct m68k_cpu *selected_arch;
516static const struct m68k_cpu *selected_cpu;
517static int initialized;
252b5132 518
266abb8f
NS		 519/* Architecture models. */
520static const struct m68k_cpu m68k_archs[] =
521{
2da12c60
NS		 522 {m68000, m68000_ctrl, "68000", 0},
523 {m68010, m68010_ctrl, "68010", 0},
524 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
525 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
526 {m68040, m68040_ctrl, "68040", 0},
527 {m68060, m68060_ctrl, "68060", 0},
528 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 529 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 530 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
531 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
532 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 533 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 534 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
535 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 536 {0,0,NULL, 0}
537};
252b5132 538
87298967
NS		 539/* For -mno-mac we want to turn off all types of mac. */
540static const unsigned no_mac = mcfmac | mcfemac;
541
0b2e31dc
NS		 542/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
543 for either. */
266abb8f
NS		 544static const struct m68k_cpu m68k_extensions[] =
545{
2da12c60
NS		 546 {m68851, NULL, "68851", -1},
547 {m68881, NULL, "68881", -1},
548 {m68881, NULL, "68882", -1},
cf869cce 549
2da12c60 550 {cfloat|m68881, NULL, "float", 0},
cf869cce 551
2da12c60
NS		 552 {mcfhwdiv, NULL, "div", 1},
553 {mcfusp, NULL, "usp", 1},
87298967 554 {mcfmac, (void *)&no_mac, "mac", 1},
2da12c60 555 {mcfemac, NULL, "emac", 1},
cf869cce 556
2da12c60 557 {0,NULL,NULL, 0}
266abb8f
NS		 558};
559
560/* Processor list */
561static const struct m68k_cpu m68k_cpus[] =
562{
2da12c60
NS		 563 {m68000, m68000_ctrl, "68000", 0},
564 {m68000, m68000_ctrl, "68ec000", 1},
565 {m68000, m68000_ctrl, "68hc000", 1},
566 {m68000, m68000_ctrl, "68hc001", 1},
567 {m68000, m68000_ctrl, "68008", 1},
568 {m68000, m68000_ctrl, "68302", 1},
569 {m68000, m68000_ctrl, "68306", 1},
570 {m68000, m68000_ctrl, "68307", 1},
571 {m68000, m68000_ctrl, "68322", 1},
572 {m68000, m68000_ctrl, "68356", 1},
573 {m68010, m68010_ctrl, "68010", 0},
574 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
575 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
576 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
577 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
578 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
579 {m68040, m68040_ctrl, "68040", 0},
580 {m68040, m68040_ctrl, "68ec040", 1},
581 {m68060, m68060_ctrl, "68060", 0},
582 {m68060, m68060_ctrl, "68ec060", 1},
cf869cce 583
2da12c60
NS		 584 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
585 {cpu32|m68881, cpu32_ctrl, "68330", 1},
586 {cpu32|m68881, cpu32_ctrl, "68331", 1},
587 {cpu32|m68881, cpu32_ctrl, "68332", 1},
588 {cpu32|m68881, cpu32_ctrl, "68333", 1},
589 {cpu32|m68881, cpu32_ctrl, "68334", 1},
590 {cpu32|m68881, cpu32_ctrl, "68336", 1},
591 {cpu32|m68881, cpu32_ctrl, "68340", 1},
592 {cpu32|m68881, cpu32_ctrl, "68341", 1},
593 {cpu32|m68881, cpu32_ctrl, "68349", 1},
594 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2 595
87298967
NS		 596 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
597 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
c1c30076 598 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1},
87298967
NS		 599 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
600 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
c1c30076
NS		 601 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1},
602 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1},
603 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1},
87298967 604 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
c1c30076 605 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1},
87298967 606 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
c1c30076 607 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1},
cf869cce 608
2da12c60
NS		 609 {mcfisa_a, mcf_ctrl, "5200", 0},
610 {mcfisa_a, mcf_ctrl, "5202", 1},
611 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 612 {mcfisa_a, mcf5206_ctrl, "5206", 1},
cf869cce 613
78336706 614 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
cf869cce 615
2da12c60
NS		 616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
617 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
cf869cce 618
96e0bbcc
NS		 619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
cf869cce 621
2da12c60
NS		 622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
624 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
cf869cce 625
2da12c60
NS		 626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
629
46203761
MK		 630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
631
d5be9593
NS		 632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
634
96e0bbcc
NS		 635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
cf869cce 639
96e0bbcc
NS		 640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
cf869cce 642
87298967
NS		 643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
3739860c 645
2da12c60
NS		 646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
3739860c 651
2da12c60
NS		 652 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
653 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 654 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
87298967
NS		 655
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
3739860c 662
2da12c60
NS		 663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
3739860c 665
2da12c60 666 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
3739860c 667
2da12c60
NS		 668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
3739860c 670
2da12c60
NS		 671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
674 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
3739860c 675
87298967
NS		 676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
678 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
679 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
682 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
3739860c 683
78336706 684 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
3739860c 685
2da12c60
NS		 686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
3739860c 690
2da12c60
NS		 691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
3739860c 694
def8fc92 695 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
9a2e615a 696
0d999f33
MK		 697 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
698 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
699 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
700 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
701 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
702
9a2e615a
NS		 703 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
704 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
705 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
706 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
707 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
708 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
3739860c 709
a8e24a56
NS		 710 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
711 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
712 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
713 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
714 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
715 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
716 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
3739860c 717
a8e24a56
NS		 718 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
719 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
720 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
721 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
3739860c 725
b3768379 726 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 727 {fido_a, fido_ctrl, "fido", 1},
9840d27e 728
2da12c60 729 {0,NULL,NULL, 0}
dc84e067 730 };
252b5132 731
266abb8f
NS		 732static const struct m68k_cpu *m68k_lookup_cpu
733(const char *, const struct m68k_cpu *, int, int *);
734static int m68k_set_arch (const char *, int, int);
735static int m68k_set_cpu (const char *, int, int);
736static int m68k_set_extension (const char *, int, int);
737static void m68k_init_arch (void);
252b5132 738
151337e8
NC		 739/* This is the assembler relaxation table for m68k. m68k is a rich CISC
740 architecture and we have a lot of relaxation modes. */
252b5132 741
151337e8
NC		 742/* Macros used in the relaxation code. */
743#define TAB(x,y) (((x) << 2) + (y))
744#define TABTYPE(x) ((x) >> 2)
745
746/* Relaxation states. */
747#define BYTE 0
748#define SHORT 1
749#define LONG 2
750#define SZ_UNDEF 3
751
752/* Here are all the relaxation modes we support. First we can relax ordinary
753 branches. On 68020 and higher and on CPU32 all branch instructions take
754 three forms, so on these CPUs all branches always remain as such. When we
755 have to expand to the LONG form on a 68000, though, we substitute an
756 absolute jump instead. This is a direct replacement for unconditional
757 branches and a branch over a jump for conditional branches. However, if the
758 user requires PIC and disables this with --pcrel, we can only relax between
759 BYTE and SHORT forms, punting if that isn't enough. This gives us four
760 different relaxation modes for branches: */
761
36759679
NC		 762#define BRANCHBWL 0 /* Branch byte, word, or long. */
763#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
764#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
765#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 766
767/* We also relax coprocessor branches and DBcc's. All CPUs that support
768 coprocessor branches support them in word and long forms, so we have only
769 one relaxation mode for them. DBcc's are word only on all CPUs. We can
770 relax them to the LONG form with a branch-around sequence. This sequence
771 can use a long branch (if available) or an absolute jump (if acceptable).
772 This gives us two relaxation modes. If long branches are not available and
773 absolute jumps are not acceptable, we don't relax DBcc's. */
774
36759679
NC		 775#define FBRANCH 4 /* Coprocessor branch. */
776#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
777#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 778
779/* That's all for instruction relaxation. However, we also relax PC-relative
780 operands. Specifically, we have three operand relaxation modes. On the
781 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
782 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
783 two. Also PC+displacement+index operands in their simple form (with a non-
784 suppressed index without memory indirection) are supported on all CPUs, but
785 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
786 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
787 form of the PC+displacement+index operand. Finally, some absolute operands
788 can be relaxed down to 16-bit PC-relative. */
789
36759679
NC		 790#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
791#define PCINDEX 8 /* PC + displacement + index. */
792#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132 793
cac27205
NC		 794/* This relaxation is required for branches where there is no long
795 branch and we are in pcrel mode. We generate a bne/beq pair. */
796#define BRANCHBWPL 10 /* Branch byte, word or pair of longs
797 */
798
252b5132 799/* Note that calls to frag_var need to specify the maximum expansion
cac27205
NC		 800 needed; this is currently 12 bytes for bne/beq pair. */
801#define FRAG_VAR_SIZE 12
252b5132
RH		 802
803/* The fields are:
804 How far Forward this mode will reach:
805 How far Backward this mode will reach:
806 How many bytes this mode will add to the size of the frag
807 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 808
809 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 810relax_typeS md_relax_table[] =
811{
ac62c346
AM		 812 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
813 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
814 { 0, 0, 4, 0 },
815 { 1, 1, 0, 0 },
816
817 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
818 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
819 { 0, 0, 4, 0 },
820 { 1, 1, 0, 0 },
821
822 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
823 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
824 { 0, 0, 6, 0 },
825 { 1, 1, 0, 0 },
826
827 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
828 { 0, 0, 2, 0 },
829 { 1, 1, 0, 0 },
830 { 1, 1, 0, 0 },
831
36759679 832 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 833 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
834 { 0, 0, 4, 0 },
835 { 1, 1, 0, 0 },
836
36759679 837 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 838 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
839 { 0, 0, 10, 0 },
840 { 1, 1, 0, 0 },
841
36759679 842 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 843 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
844 { 0, 0, 10, 0 },
845 { 1, 1, 0, 0 },
846
36759679 847 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 848 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
849 { 0, 0, 6, 0 },
850 { 1, 1, 0, 0 },
851
852 { 125, -130, 0, TAB (PCINDEX, SHORT) },
853 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
854 { 0, 0, 4, 0 },
855 { 1, 1, 0, 0 },
856
36759679 857 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 858 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
859 { 0, 0, 4, 0 },
860 { 1, 1, 0, 0 },
3739860c 861
cac27205
NC		 862 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
863 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
864 { 0, 0, 10, 0 },
865 { 1, 1, 0, 0 },
252b5132
RH		 866};
867
868/* These are the machine dependent pseudo-ops. These are included so
869 the assembler can work on the output from the SUN C compiler, which
36759679 870 generates these. */
252b5132
RH		 871
872/* This table describes all the machine specific pseudo-ops the assembler
873 has to support. The fields are:
874 pseudo-op name without dot
875 function to call to execute this pseudo-op
36759679 876 Integer arg to pass to the function. */
252b5132
RH		 877const pseudo_typeS md_pseudo_table[] =
878{
879 {"data1", s_data1, 0},
880 {"data2", s_data2, 0},
881 {"bss", s_bss, 0},
882 {"even", s_even, 0},
883 {"skip", s_space, 0},
884 {"proc", s_proc, 0},
252b5132 885 {"align", s_align_bytes, 0},
252b5132 886 {"swbeg", s_ignore, 0},
cf869cce 887 {"long", m68k_elf_cons, 4},
252b5132
RH		 888 {"extend", float_cons, 'x'},
889 {"ldouble", float_cons, 'x'},
890
266abb8f
NS		 891 {"arch", s_m68k_arch, 0},
892 {"cpu", s_m68k_cpu, 0},
85f7484a 893 {"gnu_attribute", m68k_elf_gnu_attribute, 0},
266abb8f 894
252b5132
RH		 895 /* The following pseudo-ops are supported for MRI compatibility. */
896 {"chip", s_chip, 0},
897 {"comline", s_space, 1},
898 {"fopt", s_fopt, 0},
899 {"mask2", s_ignore, 0},
900 {"opt", s_opt, 0},
901 {"reg", s_reg, 0},
902 {"restore", s_restore, 0},
903 {"save", s_save, 0},
904
905 {"if", s_mri_if, 0},
906 {"if.b", s_mri_if, 'b'},
907 {"if.w", s_mri_if, 'w'},
908 {"if.l", s_mri_if, 'l'},
909 {"else", s_mri_else, 0},
910 {"else.s", s_mri_else, 's'},
911 {"else.l", s_mri_else, 'l'},
912 {"endi", s_mri_endi, 0},
913 {"break", s_mri_break, 0},
914 {"break.s", s_mri_break, 's'},
915 {"break.l", s_mri_break, 'l'},
916 {"next", s_mri_next, 0},
917 {"next.s", s_mri_next, 's'},
918 {"next.l", s_mri_next, 'l'},
919 {"for", s_mri_for, 0},
920 {"for.b", s_mri_for, 'b'},
921 {"for.w", s_mri_for, 'w'},
922 {"for.l", s_mri_for, 'l'},
923 {"endf", s_mri_endf, 0},
924 {"repeat", s_mri_repeat, 0},
925 {"until", s_mri_until, 0},
926 {"until.b", s_mri_until, 'b'},
927 {"until.w", s_mri_until, 'w'},
928 {"until.l", s_mri_until, 'l'},
929 {"while", s_mri_while, 0},
930 {"while.b", s_mri_while, 'b'},
931 {"while.w", s_mri_while, 'w'},
932 {"while.l", s_mri_while, 'l'},
933 {"endw", s_mri_endw, 0},
934
935 {0, 0, 0}
936};
937
252b5132 938/* The mote pseudo ops are put into the opcode table, since they
31302357 939 don't start with a . they look like opcodes to gas. */
252b5132 940
5a38dc70 941const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 942{
943
944 {"dcl", cons, 4},
945 {"dc", cons, 2},
946 {"dcw", cons, 2},
947 {"dcb", cons, 1},
948
949 {"dsl", s_space, 4},
950 {"ds", s_space, 2},
951 {"dsw", s_space, 2},
952 {"dsb", s_space, 1},
953
954 {"xdef", s_globl, 0},
252b5132 955 {"align", s_align_bytes, 0},
252b5132
RH		 956 {0, 0, 0}
957};
958
bd17c2c3
AM		 959/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
960 gives identical results to a 32-bit host. */
961#define TRUNC(X) ((valueT) (X) & 0xffffffff)
962#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
963
964#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
965#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
966#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
967#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
968
969#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
970#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 971#define islong(x) (1)
972
252b5132
RH		 973static char notend_table[256];
974static char alt_notend_table[256];
975#define notend(s) \
976 (! (notend_table[(unsigned char) *s] \
977 || (*s == ':' \
978 && alt_notend_table[(unsigned char) s[1]])))
979
252b5132 980
c801568a
AM		 981/* Return zero if the reference to SYMBOL from within the same segment may
982 be relaxed. */
983
984/* On an ELF system, we can't relax an externally visible symbol,
985 because it may be overridden by a shared library. However, if
986 TARGET_OS is "elf", then we presume that we are assembling for an
987 embedded system, in which case we don't have to worry about shared
988 libraries, and we can relax any external sym. */
989
990#define relaxable_symbol(symbol) \
6358301e 991 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 992 || S_IS_WEAK (symbol)))
993
252b5132
RH		 994/* Compute the relocation code for a fixup of SIZE bytes, using pc
995 relative relocation if PCREL is non-zero. PIC says whether a special
996 pic relocation was requested. */
997
252b5132 998static bfd_reloc_code_real_type
31302357 999get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 1000{
1001 switch (pic)
1002 {
1003 case pic_got_pcrel:
1004 switch (size)
1005 {
1006 case 1:
1007 return BFD_RELOC_8_GOT_PCREL;
1008 case 2:
1009 return BFD_RELOC_16_GOT_PCREL;
1010 case 4:
1011 return BFD_RELOC_32_GOT_PCREL;
1012 }
1013 break;
1014
1015 case pic_got_off:
1016 switch (size)
1017 {
1018 case 1:
1019 return BFD_RELOC_8_GOTOFF;
1020 case 2:
1021 return BFD_RELOC_16_GOTOFF;
1022 case 4:
1023 return BFD_RELOC_32_GOTOFF;
1024 }
1025 break;
1026
1027 case pic_plt_pcrel:
1028 switch (size)
1029 {
1030 case 1:
1031 return BFD_RELOC_8_PLT_PCREL;
1032 case 2:
1033 return BFD_RELOC_16_PLT_PCREL;
1034 case 4:
1035 return BFD_RELOC_32_PLT_PCREL;
1036 }
1037 break;
1038
1039 case pic_plt_off:
1040 switch (size)
1041 {
1042 case 1:
1043 return BFD_RELOC_8_PLTOFF;
1044 case 2:
1045 return BFD_RELOC_16_PLTOFF;
1046 case 4:
1047 return BFD_RELOC_32_PLTOFF;
1048 }
1049 break;
1050
cf869cce
NC		 1051 case pic_tls_gd:
1052 switch (size)
1053 {
1054 case 1:
1055 return BFD_RELOC_68K_TLS_GD8;
1056 case 2:
1057 return BFD_RELOC_68K_TLS_GD16;
1058 case 4:
1059 return BFD_RELOC_68K_TLS_GD32;
1060 }
1061 break;
1062
1063 case pic_tls_ldm:
1064 switch (size)
1065 {
1066 case 1:
1067 return BFD_RELOC_68K_TLS_LDM8;
1068 case 2:
1069 return BFD_RELOC_68K_TLS_LDM16;
1070 case 4:
1071 return BFD_RELOC_68K_TLS_LDM32;
1072 }
1073 break;
1074
1075 case pic_tls_ldo:
1076 switch (size)
1077 {
1078 case 1:
1079 return BFD_RELOC_68K_TLS_LDO8;
1080 case 2:
1081 return BFD_RELOC_68K_TLS_LDO16;
1082 case 4:
1083 return BFD_RELOC_68K_TLS_LDO32;
1084 }
1085 break;
1086
1087 case pic_tls_ie:
1088 switch (size)
1089 {
1090 case 1:
1091 return BFD_RELOC_68K_TLS_IE8;
1092 case 2:
1093 return BFD_RELOC_68K_TLS_IE16;
1094 case 4:
1095 return BFD_RELOC_68K_TLS_IE32;
1096 }
1097 break;
1098
1099 case pic_tls_le:
1100 switch (size)
1101 {
1102 case 1:
1103 return BFD_RELOC_68K_TLS_LE8;
1104 case 2:
1105 return BFD_RELOC_68K_TLS_LE16;
1106 case 4:
1107 return BFD_RELOC_68K_TLS_LE32;
1108 }
1109 break;
1110
252b5132
RH		 1111 case pic_none:
1112 if (pcrel)
1113 {
1114 switch (size)
1115 {
1116 case 1:
1117 return BFD_RELOC_8_PCREL;
1118 case 2:
1119 return BFD_RELOC_16_PCREL;
1120 case 4:
1121 return BFD_RELOC_32_PCREL;
1122 }
1123 }
1124 else
1125 {
1126 switch (size)
1127 {
1128 case 1:
1129 return BFD_RELOC_8;
1130 case 2:
1131 return BFD_RELOC_16;
1132 case 4:
1133 return BFD_RELOC_32;
1134 }
1135 }
1136 }
1137
1138 if (pcrel)
1139 {
1140 if (pic == pic_none)
1141 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1142 else
1143 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1144 }
1145 else
1146 {
1147 if (pic == pic_none)
1148 as_bad (_("Can not do %d byte relocation"), size);
1149 else
1150 as_bad (_("Can not do %d byte pic relocation"), size);
1151 }
1152
1153 return BFD_RELOC_NONE;
1154}
1155
1156/* Here we decide which fixups can be adjusted to make them relative
1157 to the beginning of the section instead of the symbol. Basically
1158 we need to make sure that the dynamic relocations are done
1159 correctly, so in some cases we force the original symbol to be
1160 used. */
1161int
31302357 1162tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1163{
36759679 1164 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1165 switch (fixP->fx_r_type)
1166 {
1167 case BFD_RELOC_8_GOT_PCREL:
1168 case BFD_RELOC_16_GOT_PCREL:
1169 case BFD_RELOC_32_GOT_PCREL:
1170 case BFD_RELOC_8_GOTOFF:
1171 case BFD_RELOC_16_GOTOFF:
1172 case BFD_RELOC_32_GOTOFF:
1173 case BFD_RELOC_8_PLT_PCREL:
1174 case BFD_RELOC_16_PLT_PCREL:
1175 case BFD_RELOC_32_PLT_PCREL:
1176 case BFD_RELOC_8_PLTOFF:
1177 case BFD_RELOC_16_PLTOFF:
1178 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1179 case BFD_RELOC_68K_TLS_GD32:
1180 case BFD_RELOC_68K_TLS_GD16:
1181 case BFD_RELOC_68K_TLS_GD8:
1182 case BFD_RELOC_68K_TLS_LDM32:
1183 case BFD_RELOC_68K_TLS_LDM16:
1184 case BFD_RELOC_68K_TLS_LDM8:
1185 case BFD_RELOC_68K_TLS_LDO32:
1186 case BFD_RELOC_68K_TLS_LDO16:
1187 case BFD_RELOC_68K_TLS_LDO8:
1188 case BFD_RELOC_68K_TLS_IE32:
1189 case BFD_RELOC_68K_TLS_IE16:
1190 case BFD_RELOC_68K_TLS_IE8:
1191 case BFD_RELOC_68K_TLS_LE32:
1192 case BFD_RELOC_68K_TLS_LE16:
1193 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1194 return 0;
1195
1196 case BFD_RELOC_VTABLE_INHERIT:
1197 case BFD_RELOC_VTABLE_ENTRY:
1198 return 0;
1199
1200 default:
1201 return 1;
1202 }
1203}
1204
252b5132 1205arelent *
31302357 1206tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1207{
1208 arelent *reloc;
1209 bfd_reloc_code_real_type code;
1210
8ec6253e
NC		 1211 /* If the tcbit is set, then this was a fixup of a negative value
1212 that was never resolved. We do not have a reloc to handle this,
1213 so just return. We assume that other code will have detected this
1214 situation and produced a helpful error message, so we just tell the
1215 user that the reloc cannot be produced. */
252b5132 1216 if (fixp->fx_tcbit)
8ec6253e
NC		 1217 {
1218 if (fixp->fx_addsy)
b091f402
AM		 1219 as_bad_where (fixp->fx_file, fixp->fx_line,
1220 _("Unable to produce reloc against symbol '%s'"),
1221 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1222 return NULL;
1223 }
252b5132
RH		 1224
1225 if (fixp->fx_r_type != BFD_RELOC_NONE)
1226 {
1227 code = fixp->fx_r_type;
1228
1229 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1230 that fixup_segment converted a non-PC relative reloc into a
1231 PC relative reloc. In such a case, we need to convert the
1232 reloc code. */
1233 if (fixp->fx_pcrel)
1234 {
1235 switch (code)
1236 {
1237 case BFD_RELOC_8:
1238 code = BFD_RELOC_8_PCREL;
1239 break;
1240 case BFD_RELOC_16:
1241 code = BFD_RELOC_16_PCREL;
1242 break;
1243 case BFD_RELOC_32:
1244 code = BFD_RELOC_32_PCREL;
1245 break;
1246 case BFD_RELOC_8_PCREL:
1247 case BFD_RELOC_16_PCREL:
1248 case BFD_RELOC_32_PCREL:
1249 case BFD_RELOC_8_GOT_PCREL:
1250 case BFD_RELOC_16_GOT_PCREL:
1251 case BFD_RELOC_32_GOT_PCREL:
1252 case BFD_RELOC_8_GOTOFF:
1253 case BFD_RELOC_16_GOTOFF:
1254 case BFD_RELOC_32_GOTOFF:
1255 case BFD_RELOC_8_PLT_PCREL:
1256 case BFD_RELOC_16_PLT_PCREL:
1257 case BFD_RELOC_32_PLT_PCREL:
1258 case BFD_RELOC_8_PLTOFF:
1259 case BFD_RELOC_16_PLTOFF:
1260 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1261 case BFD_RELOC_68K_TLS_GD32:
1262 case BFD_RELOC_68K_TLS_GD16:
1263 case BFD_RELOC_68K_TLS_GD8:
1264 case BFD_RELOC_68K_TLS_LDM32:
1265 case BFD_RELOC_68K_TLS_LDM16:
1266 case BFD_RELOC_68K_TLS_LDM8:
1267 case BFD_RELOC_68K_TLS_LDO32:
1268 case BFD_RELOC_68K_TLS_LDO16:
1269 case BFD_RELOC_68K_TLS_LDO8:
1270 case BFD_RELOC_68K_TLS_IE32:
1271 case BFD_RELOC_68K_TLS_IE16:
1272 case BFD_RELOC_68K_TLS_IE8:
1273 case BFD_RELOC_68K_TLS_LE32:
1274 case BFD_RELOC_68K_TLS_LE16:
1275 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1276 break;
1277 default:
1278 as_bad_where (fixp->fx_file, fixp->fx_line,
1279 _("Cannot make %s relocation PC relative"),
1280 bfd_get_reloc_code_name (code));
1281 }
1282 }
1283 }
1284 else
1285 {
1286#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1287 switch (F (fixp->fx_size, fixp->fx_pcrel))
1288 {
1289#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1290 MAP (1, 0, BFD_RELOC_8);
1291 MAP (2, 0, BFD_RELOC_16);
1292 MAP (4, 0, BFD_RELOC_32);
1293 MAP (1, 1, BFD_RELOC_8_PCREL);
1294 MAP (2, 1, BFD_RELOC_16_PCREL);
1295 MAP (4, 1, BFD_RELOC_32_PCREL);
1296 default:
1297 abort ();
1298 }
1299 }
1300#undef F
1301#undef MAP
1302
add39d23
TS		 1303 reloc = XNEW (arelent);
1304 reloc->sym_ptr_ptr = XNEW (asymbol *);
49309057 1305 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132 1306 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
252b5132
RH		 1307 if (!fixp->fx_pcrel)
1308 reloc->addend = fixp->fx_addnumber;
1309 else
1310 reloc->addend = (section->vma
552c607f 1311 + fixp->fx_pcrel_adjust
252b5132
RH		 1312 + fixp->fx_addnumber
1313 + md_pcrel_from (fixp));
252b5132
RH		 1314
1315 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
9c2799c2 1316 gas_assert (reloc->howto != 0);
252b5132
RH		 1317
1318 return reloc;
1319}
1320
252b5132
RH		 1321/* Handle of the OPCODE hash table. NULL means any use before
1322 m68k_ip_begin() will crash. */
1323static struct hash_control *op_hash;
1324\f
1325/* Assemble an m68k instruction. */
1326
1327static void
31302357 1328m68k_ip (char *instring)
252b5132 1329{
ed9e98c2
AM		 1330 char *p;
1331 struct m68k_op *opP;
1332 const struct m68k_incant *opcode;
1333 const char *s;
1334 int tmpreg = 0, baseo = 0, outro = 0, nextword;
252b5132
RH		 1335 char *pdot, *pdotmove;
1336 enum m68k_size siz1, siz2;
1337 char c;
1338 int losing;
1339 int opsfound;
03b13e59 1340 struct m68k_op operands_backup[6];
252b5132
RH		 1341 LITTLENUM_TYPE words[6];
1342 LITTLENUM_TYPE *wordp;
1343 unsigned long ok_arch = 0;
1344
1345 if (*instring == ' ')
36759679 1346 instring++; /* Skip leading whitespace. */
252b5132
RH		 1347
1348 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1349 or exactly 1 space. */
252b5132
RH		 1350 pdot = 0;
1351 for (p = instring; *p != '\0'; p++)
1352 {
1353 if (*p == ' ')
1354 break;
1355 if (*p == '.')
1356 pdot = p;
1357 }
1358
1359 if (p == instring)
1360 {
1361 the_ins.error = _("No operator");
1362 return;
1363 }
1364
1365 /* p now points to the end of the opcode name, probably whitespace.
1366 Make sure the name is null terminated by clobbering the
1367 whitespace, look it up in the hash table, then fix it back.
1368 Remove a dot, first, since the opcode tables have none. */
1369 if (pdot != NULL)
1370 {
1371 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1372 *pdotmove = pdotmove[1];
1373 p--;
1374 }
1375
1376 c = *p;
1377 *p = '\0';
1378 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1379 *p = c;
1380
1381 if (pdot != NULL)
1382 {
1383 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1384 *pdotmove = pdotmove[-1];
1385 *pdot = '.';
1386 ++p;
1387 }
1388
1389 if (opcode == NULL)
1390 {
1391 the_ins.error = _("Unknown operator");
1392 return;
1393 }
1394
36759679 1395 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1396 while (*p == ' ')
1397 ++p;
1398
1399 if (opcode->m_operands == 0)
1400 {
1401 char *old = input_line_pointer;
1402 *old = '\n';
1403 input_line_pointer = p;
2b0f3761 1404 /* Ahh - it's a motorola style pseudo op. */
252b5132
RH		 1405 mote_pseudo_table[opcode->m_opnum].poc_handler
1406 (mote_pseudo_table[opcode->m_opnum].poc_val);
1407 input_line_pointer = old;
1408 *old = 0;
1409
1410 return;
1411 }
1412
1413 if (flag_mri && opcode->m_opnum == 0)
1414 {
1415 /* In MRI mode, random garbage is allowed after an instruction
1416 which accepts no operands. */
1417 the_ins.args = opcode->m_operands;
1418 the_ins.numargs = opcode->m_opnum;
1419 the_ins.numo = opcode->m_codenum;
1420 the_ins.opcode[0] = getone (opcode);
1421 the_ins.opcode[1] = gettwo (opcode);
1422 return;
1423 }
1424
1425 for (opP = &the_ins.operands[0]; *p; opP++)
1426 {
1427 p = crack_operand (p, opP);
1428
1429 if (opP->error)
1430 {
1431 the_ins.error = opP->error;
1432 return;
1433 }
1434 }
1435
1436 opsfound = opP - &the_ins.operands[0];
1437
1438 /* This ugly hack is to support the floating pt opcodes in their
33eaf5de 1439 standard form. Essentially, we fake a first entry of type COP#1 */
252b5132
RH		 1440 if (opcode->m_operands[0] == 'I')
1441 {
1442 int n;
1443
1444 for (n = opsfound; n > 0; --n)
1445 the_ins.operands[n] = the_ins.operands[n - 1];
1446
31302357 1447 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1448 the_ins.operands[0].mode = CONTROL;
1449 the_ins.operands[0].reg = m68k_float_copnum;
1450 opsfound++;
1451 }
1452
36759679 1453 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1454 for (losing = 0;;)
1455 {
1456 /* If we didn't get the right number of ops, or we have no
92774660 1457 common model with this pattern then reject this pattern. */
252b5132
RH		 1458
1459 ok_arch |= opcode->m_arch;
1460 if (opsfound != opcode->m_opnum
1461 || ((opcode->m_arch & current_architecture) == 0))
1462 ++losing;
1463 else
1464 {
03b13e59
NC		 1465 int i;
1466
1467 /* Make a copy of the operands of this insn so that
1468 we can modify them safely, should we want to. */
9c2799c2 1469 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
03b13e59
NC		 1470 for (i = 0; i < opsfound; i++)
1471 operands_backup[i] = the_ins.operands[i];
1472
1473 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1474 *s && !losing;
1475 s += 2, opP++)
1476 {
1477 /* Warning: this switch is huge! */
1478 /* I've tried to organize the cases into this order:
1479 non-alpha first, then alpha by letter. Lower-case
1480 goes directly before uppercase counterpart. */
1481 /* Code with multiple case ...: gets sorted by the lowest
1482 case ... it belongs to. I hope this makes sense. */
1483 switch (*s)
1484 {
1485 case '!':
1486 switch (opP->mode)
1487 {
1488 case IMMED:
1489 case DREG:
1490 case AREG:
1491 case FPREG:
1492 case CONTROL:
1493 case AINC:
1494 case ADEC:
1495 case REGLST:
1496 losing++;
1497 break;
1498 default:
1499 break;
1500 }
1501 break;
1502
1503 case '<':
1504 switch (opP->mode)
1505 {
1506 case DREG:
1507 case AREG:
1508 case FPREG:
1509 case CONTROL:
1510 case IMMED:
1511 case ADEC:
1512 case REGLST:
1513 losing++;
1514 break;
1515 default:
1516 break;
1517 }
1518 break;
1519
1520 case '>':
1521 switch (opP->mode)
1522 {
1523 case DREG:
1524 case AREG:
1525 case FPREG:
1526 case CONTROL:
1527 case IMMED:
1528 case AINC:
1529 case REGLST:
1530 losing++;
1531 break;
1532 case ABSL:
1533 break;
1534 default:
1535 if (opP->reg == PC
1536 || opP->reg == ZPC)
1537 losing++;
1538 break;
1539 }
1540 break;
1541
1542 case 'm':
1543 switch (opP->mode)
1544 {
1545 case DREG:
1546 case AREG:
1547 case AINDR:
1548 case AINC:
1549 case ADEC:
1550 break;
1551 default:
1552 losing++;
1553 }
8a104df9 1554 break;
252b5132
RH		 1555
1556 case 'n':
1557 switch (opP->mode)
1558 {
1559 case DISP:
1560 break;
1561 default:
1562 losing++;
1563 }
8a104df9 1564 break;
252b5132
RH		 1565
1566 case 'o':
1567 switch (opP->mode)
1568 {
1569 case BASE:
1570 case ABSL:
1571 case IMMED:
1572 break;
1573 default:
1574 losing++;
1575 }
8a104df9 1576 break;
252b5132
RH		 1577
1578 case 'p':
1579 switch (opP->mode)
1580 {
1581 case DREG:
1582 case AREG:
1583 case AINDR:
1584 case AINC:
1585 case ADEC:
1586 break;
1587 case DISP:
1588 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1589 losing++;
252b5132
RH		 1590 break;
1591 default:
1592 losing++;
1593 }
8a104df9 1594 break;
252b5132
RH		 1595
1596 case 'q':
1597 switch (opP->mode)
1598 {
1599 case DREG:
1600 case AINDR:
1601 case AINC:
1602 case ADEC:
1603 break;
1604 case DISP:
1605 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1606 losing++;
252b5132
RH		 1607 break;
1608 default:
1609 losing++;
1610 break;
1611 }
8a104df9 1612 break;
252b5132
RH		 1613
1614 case 'v':
1615 switch (opP->mode)
1616 {
1617 case DREG:
1618 case AINDR:
1619 case AINC:
1620 case ADEC:
1621 case ABSL:
1622 break;
1623 case DISP:
1624 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1625 losing++;
252b5132
RH		 1626 break;
1627 default:
1628 losing++;
1629 break;
1630 }
1631 break;
1632
1633 case '#':
1634 if (opP->mode != IMMED)
1635 losing++;
1636 else if (s[1] == 'b'
1637 && ! isvar (&opP->disp)
1638 && (opP->disp.exp.X_op != O_constant
1639 || ! isbyte (opP->disp.exp.X_add_number)))
1640 losing++;
1641 else if (s[1] == 'B'
1642 && ! isvar (&opP->disp)
1643 && (opP->disp.exp.X_op != O_constant
1644 || ! issbyte (opP->disp.exp.X_add_number)))
1645 losing++;
1646 else if (s[1] == 'w'
1647 && ! isvar (&opP->disp)
1648 && (opP->disp.exp.X_op != O_constant
1649 || ! isword (opP->disp.exp.X_add_number)))
1650 losing++;
1651 else if (s[1] == 'W'
1652 && ! isvar (&opP->disp)
1653 && (opP->disp.exp.X_op != O_constant
1654 || ! issword (opP->disp.exp.X_add_number)))
1655 losing++;
1656 break;
1657
1658 case '^':
1659 case 'T':
1660 if (opP->mode != IMMED)
1661 losing++;
1662 break;
1663
1664 case '$':
1665 if (opP->mode == AREG
1666 || opP->mode == CONTROL
1667 || opP->mode == FPREG
1668 || opP->mode == IMMED
1669 || opP->mode == REGLST
1670 || (opP->mode != ABSL
1671 && (opP->reg == PC
1672 || opP->reg == ZPC)))
1673 losing++;
1674 break;
1675
1676 case '%':
1677 if (opP->mode == CONTROL
1678 || opP->mode == FPREG
1679 || opP->mode == REGLST
1680 || opP->mode == IMMED
1681 || (opP->mode != ABSL
1682 && (opP->reg == PC
1683 || opP->reg == ZPC)))
1684 losing++;
1685 break;
1686
1687 case '&':
1688 switch (opP->mode)
1689 {
1690 case DREG:
1691 case AREG:
1692 case FPREG:
1693 case CONTROL:
1694 case IMMED:
1695 case AINC:
1696 case ADEC:
1697 case REGLST:
1698 losing++;
1699 break;
1700 case ABSL:
1701 break;
1702 default:
1703 if (opP->reg == PC
1704 || opP->reg == ZPC)
1705 losing++;
1706 break;
1707 }
1708 break;
1709
1710 case '*':
1711 if (opP->mode == CONTROL
1712 || opP->mode == FPREG
1713 || opP->mode == REGLST)
1714 losing++;
1715 break;
1716
1717 case '+':
1718 if (opP->mode != AINC)
1719 losing++;
1720 break;
1721
1722 case '-':
1723 if (opP->mode != ADEC)
1724 losing++;
1725 break;
1726
1727 case '/':
1728 switch (opP->mode)
1729 {
1730 case AREG:
1731 case CONTROL:
1732 case FPREG:
1733 case AINC:
1734 case ADEC:
1735 case IMMED:
1736 case REGLST:
1737 losing++;
1738 break;
1739 default:
1740 break;
1741 }
1742 break;
1743
1744 case ';':
1745 switch (opP->mode)
1746 {
1747 case AREG:
1748 case CONTROL:
1749 case FPREG:
1750 case REGLST:
1751 losing++;
1752 break;
1753 default:
1754 break;
1755 }
1756 break;
1757
1758 case '?':
1759 switch (opP->mode)
1760 {
1761 case AREG:
1762 case CONTROL:
1763 case FPREG:
1764 case AINC:
1765 case ADEC:
1766 case IMMED:
1767 case REGLST:
1768 losing++;
1769 break;
1770 case ABSL:
1771 break;
1772 default:
1773 if (opP->reg == PC || opP->reg == ZPC)
1774 losing++;
1775 break;
1776 }
1777 break;
1778
1779 case '@':
1780 switch (opP->mode)
1781 {
1782 case AREG:
1783 case CONTROL:
1784 case FPREG:
1785 case IMMED:
1786 case REGLST:
1787 losing++;
1788 break;
1789 default:
1790 break;
1791 }
1792 break;
1793
1794 case '~': /* For now! (JF FOO is this right?) */
1795 switch (opP->mode)
1796 {
1797 case DREG:
1798 case AREG:
1799 case CONTROL:
1800 case FPREG:
1801 case IMMED:
1802 case REGLST:
1803 losing++;
1804 break;
1805 case ABSL:
1806 break;
1807 default:
1808 if (opP->reg == PC
1809 || opP->reg == ZPC)
1810 losing++;
1811 break;
1812 }
1813 break;
1814
1815 case '3':
1816 if (opP->mode != CONTROL
1817 || (opP->reg != TT0 && opP->reg != TT1))
1818 losing++;
1819 break;
1820
1821 case 'A':
1822 if (opP->mode != AREG)
1823 losing++;
1824 break;
1825
1826 case 'a':
1827 if (opP->mode != AINDR)
1828 ++losing;
1829 break;
1830
fd99574b
NC		 1831 case '4':
1832 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1833 && (opP->mode != DISP
1834 || opP->reg < ADDR0
1835 || opP->reg > ADDR7))
1836 ++losing;
1837 break;
1838
252b5132
RH		 1839 case 'B': /* FOO */
1840 if (opP->mode != ABSL
1841 || (flag_long_jumps
1842 && strncmp (instring, "jbsr", 4) == 0))
1843 losing++;
1844 break;
1845
3e602632
NC		 1846 case 'b':
1847 switch (opP->mode)
1848 {
1849 case IMMED:
1850 case ABSL:
1851 case AREG:
1852 case FPREG:
1853 case CONTROL:
1854 case POST:
1855 case PRE:
1856 case REGLST:
1857 losing++;
1858 break;
1859 default:
1860 break;
1861 }
1862 break;
1863
252b5132
RH		 1864 case 'C':
1865 if (opP->mode != CONTROL || opP->reg != CCR)
1866 losing++;
1867 break;
1868
1869 case 'd':
1870 if (opP->mode != DISP
1871 || opP->reg < ADDR0
1872 || opP->reg > ADDR7)
1873 losing++;
1874 break;
1875
1876 case 'D':
1877 if (opP->mode != DREG)
1878 losing++;
1879 break;
1880
6da466c7
ILT		 1881 case 'E':
1882 if (opP->reg != ACC)
1883 losing++;
1884 break;
1885
fd99574b
NC		 1886 case 'e':
1887 if (opP->reg != ACC && opP->reg != ACC1
1888 && opP->reg != ACC2 && opP->reg != ACC3)
1889 losing++;
1890 break;
1891
252b5132
RH		 1892 case 'F':
1893 if (opP->mode != FPREG)
1894 losing++;
1895 break;
1896
6da466c7
ILT		 1897 case 'G':
1898 if (opP->reg != MACSR)
1899 losing++;
1900 break;
1901
fd99574b
NC		 1902 case 'g':
1903 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1904 losing++;
1905 break;
1906
6da466c7
ILT		 1907 case 'H':
1908 if (opP->reg != MASK)
1909 losing++;
1910 break;
1911
252b5132
RH		 1912 case 'I':
1913 if (opP->mode != CONTROL
1914 || opP->reg < COP0
1915 || opP->reg > COP7)
1916 losing++;
1917 break;
1918
fd99574b
NC		 1919 case 'i':
1920 if (opP->mode != LSH && opP->mode != RSH)
1921 losing++;
1922 break;
1923
252b5132
RH		 1924 case 'J':
1925 if (opP->mode != CONTROL
1926 || opP->reg < USP
0b2e31dc
NS		 1927 || opP->reg > last_movec_reg
1928 || !control_regs)
252b5132
RH		 1929 losing++;
1930 else
1931 {
1932 const enum m68k_register *rp;
3739860c 1933
252b5132 1934 for (rp = control_regs; *rp; rp++)
78336706
NS		 1935 {
1936 if (*rp == opP->reg)
1937 break;
1938 /* In most CPUs RAMBAR refers to control reg
1939 c05 (RAMBAR1), but a few CPUs have it
1940 refer to c04 (RAMBAR0). */
1941 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1942 {
1943 opP->reg = RAMBAR_ALT;
1944 break;
1945 }
1946 }
252b5132
RH		 1947 if (*rp == 0)
1948 losing++;
1949 }
1950 break;
1951
1952 case 'k':
1953 if (opP->mode != IMMED)
1954 losing++;
1955 break;
1956
1957 case 'l':
1958 case 'L':
1959 if (opP->mode == DREG
1960 || opP->mode == AREG
1961 || opP->mode == FPREG)
1962 {
1963 if (s[1] == '8')
1964 losing++;
1965 else
1966 {
1967 switch (opP->mode)
1968 {
1969 case DREG:
1970 opP->mask = 1 << (opP->reg - DATA0);
1971 break;
1972 case AREG:
1973 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1974 break;
1975 case FPREG:
1976 opP->mask = 1 << (opP->reg - FP0 + 16);
1977 break;
1978 default:
1979 abort ();
1980 }
1981 opP->mode = REGLST;
1982 }
1983 }
1984 else if (opP->mode == CONTROL)
1985 {
1986 if (s[1] != '8')
1987 losing++;
1988 else
1989 {
1990 switch (opP->reg)
1991 {
1992 case FPI:
1993 opP->mask = 1 << 24;
1994 break;
1995 case FPS:
1996 opP->mask = 1 << 25;
1997 break;
1998 case FPC:
1999 opP->mask = 1 << 26;
2000 break;
2001 default:
2002 losing++;
2003 break;
2004 }
2005 opP->mode = REGLST;
2006 }
2007 }
2008 else if (opP->mode != REGLST)
2009 losing++;
2010 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2011 losing++;
2012 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2013 losing++;
2014 break;
2015
2016 case 'M':
2017 if (opP->mode != IMMED)
2018 losing++;
2019 else if (opP->disp.exp.X_op != O_constant
2020 || ! issbyte (opP->disp.exp.X_add_number))
2021 losing++;
2022 else if (! m68k_quick
2023 && instring[3] != 'q'
2024 && instring[4] != 'q')
2025 losing++;
2026 break;
2027
2028 case 'O':
2029 if (opP->mode != DREG
2030 && opP->mode != IMMED
2031 && opP->mode != ABSL)
2032 losing++;
2033 break;
2034
2035 case 'Q':
2036 if (opP->mode != IMMED)
2037 losing++;
2038 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2039 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 2040 losing++;
2041 else if (! m68k_quick
2042 && (strncmp (instring, "add", 3) == 0
2043 || strncmp (instring, "sub", 3) == 0)
2044 && instring[3] != 'q')
2045 losing++;
2046 break;
2047
2048 case 'R':
2049 if (opP->mode != DREG && opP->mode != AREG)
2050 losing++;
2051 break;
2052
2053 case 'r':
2054 if (opP->mode != AINDR
2055 && (opP->mode != BASE
2056 || (opP->reg != 0
2057 && opP->reg != ZADDR0)
2058 || opP->disp.exp.X_op != O_absent
2059 || ((opP->index.reg < DATA0
2060 || opP->index.reg > DATA7)
2061 && (opP->index.reg < ADDR0
2062 || opP->index.reg > ADDR7))
2063 || opP->index.size != SIZE_UNSPEC
2064 || opP->index.scale != 1))
2065 losing++;
2066 break;
2067
2068 case 's':
2069 if (opP->mode != CONTROL
2070 || ! (opP->reg == FPI
2071 || opP->reg == FPS
2072 || opP->reg == FPC))
2073 losing++;
2074 break;
2075
2076 case 'S':
2077 if (opP->mode != CONTROL || opP->reg != SR)
2078 losing++;
2079 break;
2080
2081 case 't':
2082 if (opP->mode != IMMED)
2083 losing++;
2084 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2085 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 2086 losing++;
2087 break;
2088
2089 case 'U':
2090 if (opP->mode != CONTROL || opP->reg != USP)
2091 losing++;
2092 break;
2093
3e602632
NC		 2094 case 'x':
2095 if (opP->mode != IMMED)
2096 losing++;
2097 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 2098 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2099 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 2100 losing++;
2101 break;
2102
afa2158f
NS		 2103 case 'j':
2104 if (opP->mode != IMMED)
2105 losing++;
2106 else if (opP->disp.exp.X_op != O_constant
2107 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2108 losing++;
2109 break;
2110
2111 case 'K':
2112 if (opP->mode != IMMED)
2113 losing++;
2114 else if (opP->disp.exp.X_op != O_constant
2115 || TRUNC (opP->disp.exp.X_add_number) > 511)
2116 losing++;
2117 break;
2118
252b5132
RH		 2119 /* JF these are out of order. We could put them
2120 in order if we were willing to put up with
2121 bunches of #ifdef m68851s in the code.
2122
2123 Don't forget that you need these operands
2124 to use 68030 MMU instructions. */
2125#ifndef NO_68851
36759679 2126 /* Memory addressing mode used by pflushr. */
252b5132
RH		 2127 case '|':
2128 if (opP->mode == CONTROL
2129 || opP->mode == FPREG
2130 || opP->mode == DREG
2131 || opP->mode == AREG
2132 || opP->mode == REGLST)
2133 losing++;
2134 /* We should accept immediate operands, but they
2135 supposedly have to be quad word, and we don't
2136 handle that. I would like to see what a Motorola
2137 assembler does before doing something here. */
2138 if (opP->mode == IMMED)
2139 losing++;
2140 break;
2141
2142 case 'f':
2143 if (opP->mode != CONTROL
2144 || (opP->reg != SFC && opP->reg != DFC))
2145 losing++;
2146 break;
2147
2148 case '0':
2149 if (opP->mode != CONTROL || opP->reg != TC)
2150 losing++;
2151 break;
2152
2153 case '1':
2154 if (opP->mode != CONTROL || opP->reg != AC)
2155 losing++;
2156 break;
2157
2158 case '2':
2159 if (opP->mode != CONTROL
2160 || (opP->reg != CAL
2161 && opP->reg != VAL
2162 && opP->reg != SCC))
2163 losing++;
2164 break;
2165
2166 case 'V':
2167 if (opP->mode != CONTROL
2168 || opP->reg != VAL)
2169 losing++;
2170 break;
2171
2172 case 'W':
2173 if (opP->mode != CONTROL
2174 || (opP->reg != DRP
2175 && opP->reg != SRP
2176 && opP->reg != CRP))
2177 losing++;
2178 break;
2179
3e602632
NC		 2180 case 'w':
2181 switch (opP->mode)
2182 {
2183 case IMMED:
2184 case ABSL:
2185 case AREG:
2186 case DREG:
2187 case FPREG:
2188 case CONTROL:
2189 case POST:
2190 case PRE:
2191 case REGLST:
2192 losing++;
2193 break;
2194 default:
2195 break;
2196 }
2197 break;
2198
252b5132
RH		 2199 case 'X':
2200 if (opP->mode != CONTROL
2201 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2202 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2203 losing++;
2204 break;
2205
2206 case 'Y':
2207 if (opP->mode != CONTROL || opP->reg != PSR)
2208 losing++;
2209 break;
2210
2211 case 'Z':
2212 if (opP->mode != CONTROL || opP->reg != PCSR)
2213 losing++;
2214 break;
2215#endif
2216 case 'c':
2217 if (opP->mode != CONTROL
2218 || (opP->reg != NC
2219 && opP->reg != IC
2220 && opP->reg != DC
2221 && opP->reg != BC))
36759679 2222 losing++;
252b5132
RH		 2223 break;
2224
2225 case '_':
2226 if (opP->mode != ABSL)
2227 ++losing;
2228 break;
2229
6da466c7
ILT		 2230 case 'u':
2231 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2232 losing++;
2233 /* FIXME: kludge instead of fixing parser:
2234 upper/lower registers are *not* CONTROL
92774660 2235 registers, but ordinary ones. */
6da466c7
ILT		 2236 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2237 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2238 opP->mode = DREG;
2239 else
2240 opP->mode = AREG;
2241 break;
2242
3e602632
NC		 2243 case 'y':
2244 if (!(opP->mode == AINDR
31302357
AS		 2245 || (opP->mode == DISP
2246 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2247 losing++;
2248 break;
2249
2250 case 'z':
2251 if (!(opP->mode == AINDR || opP->mode == DISP))
2252 losing++;
2253 break;
2254
252b5132
RH		 2255 default:
2256 abort ();
36759679 2257 }
252b5132
RH		 2258
2259 if (losing)
2260 break;
36759679 2261 }
03b13e59
NC		 2262
2263 /* Since we have found the correct instruction, copy
2264 in the modifications that we may have made. */
2265 if (!losing)
2266 for (i = 0; i < opsfound; i++)
2267 the_ins.operands[i] = operands_backup[i];
36759679 2268 }
252b5132
RH		 2269
2270 if (!losing)
36759679 2271 break;
252b5132
RH		 2272
2273 opcode = opcode->m_next;
2274
2275 if (!opcode)
2276 {
2277 if (ok_arch
2278 && !(ok_arch & current_architecture))
2279 {
6d89cc8f
NS		 2280 const struct m68k_cpu *cpu;
2281 int any = 0;
2282 size_t space = 400;
325801bd 2283 char *buf = XNEWVEC (char, space + 1);
6d89cc8f
NS		 2284 size_t len;
2285 int paren = 1;
2286
2287 the_ins.error = buf;
2288 /* Make sure there's a NUL at the end of the buffer -- strncpy
b2f58c0c 2289 won't write one when it runs out of buffer. */
6d89cc8f
NS		 2290 buf[space] = 0;
2291#define APPEND(STRING) \
2292 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2293
2294 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2295 switch (ok_arch)
2296 {
6b6e92f4 2297 case mcfisa_a:
b2f58c0c 2298 APPEND ("ColdFire ISA_A");
6b6e92f4
NC		 2299 break;
2300 case mcfhwdiv:
b2f58c0c
NC		 2301 APPEND ("ColdFire ");
2302 APPEND (_("hardware divide"));
6b6e92f4
NC		 2303 break;
2304 case mcfisa_aa:
b2f58c0c 2305 APPEND ("ColdFire ISA_A+");
6b6e92f4
NC		 2306 break;
2307 case mcfisa_b:
b2f58c0c 2308 APPEND ("ColdFire ISA_B");
6b6e92f4 2309 break;
8d100c32 2310 case mcfisa_c:
b2f58c0c 2311 APPEND ("ColdFire ISA_C");
8d100c32 2312 break;
3e602632 2313 case cfloat:
b2f58c0c 2314 APPEND ("ColdFire fpu");
3e602632 2315 break;
252b5132 2316 case mfloat:
b2f58c0c 2317 APPEND ("M68K fpu");
252b5132
RH		 2318 break;
2319 case mmmu:
b2f58c0c 2320 APPEND ("M68K mmu");
252b5132
RH		 2321 break;
2322 case m68020up:
b2f58c0c
NC		 2323 APPEND ("68020 ");
2324 APPEND (_("or higher"));
252b5132
RH		 2325 break;
2326 case m68000up:
b2f58c0c
NC		 2327 APPEND ("68000 ");
2328 APPEND (_("or higher"));
252b5132
RH		 2329 break;
2330 case m68010up:
b2f58c0c
NC		 2331 APPEND ("68010 ");
2332 APPEND (_("or higher"));
252b5132
RH		 2333 break;
2334 default:
6d89cc8f
NS		 2335 paren = 0;
2336 }
2337 if (paren)
2338 APPEND (" (");
6b6e92f4 2339
6d89cc8f
NS		 2340 for (cpu = m68k_cpus; cpu->name; cpu++)
2341 if (!cpu->alias && (cpu->arch & ok_arch))
2342 {
2343 const struct m68k_cpu *alias;
869ddf2a 2344 int seen_master = 0;
3739860c 2345
6d89cc8f
NS		 2346 if (any)
2347 APPEND (", ");
2348 any = 0;
2349 APPEND (cpu->name);
869ddf2a
NS		 2350 for (alias = cpu; alias != m68k_cpus; alias--)
2351 if (alias[-1].alias >= 0)
2352 break;
2353 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2354 {
869ddf2a
NS		 2355 if (!alias->alias)
2356 seen_master = 1;
2357 else
2358 {
2359 if (any)
2360 APPEND (", ");
2361 else
2362 APPEND (" [");
2363 APPEND (alias->name);
2364 any = 1;
2365 }
6d89cc8f 2366 }
869ddf2a
NS		 2367 if (any)
2368 APPEND ("]");
6d89cc8f 2369 any = 1;
252b5132 2370 }
6d89cc8f
NS		 2371 if (paren)
2372 APPEND (")");
2373#undef APPEND
2374 if (!space)
2375 {
b2f58c0c 2376 /* We ran out of space, so replace the end of the list
6d89cc8f
NS		 2377 with ellipsis. */
2378 buf -= 4;
2379 while (*buf != ' ')
2380 buf--;
2381 strcpy (buf, " ...");
252b5132 2382 }
252b5132
RH		 2383 }
2384 else
2385 the_ins.error = _("operands mismatch");
2386 return;
36759679 2387 }
252b5132
RH		 2388
2389 losing = 0;
2390 }
2391
36759679 2392 /* Now assemble it. */
252b5132
RH		 2393 the_ins.args = opcode->m_operands;
2394 the_ins.numargs = opcode->m_opnum;
2395 the_ins.numo = opcode->m_codenum;
2396 the_ins.opcode[0] = getone (opcode);
2397 the_ins.opcode[1] = gettwo (opcode);
2398
2399 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2400 {
9a2e615a 2401 int have_disp = 0;
cac27205 2402 int use_pl = 0;
3739860c 2403
252b5132 2404 /* This switch is a doozy.
33eaf5de 2405 Watch the first step; it's a big one! */
252b5132
RH		 2406 switch (s[0])
2407 {
2408
2409 case '*':
2410 case '~':
2411 case '%':
2412 case ';':
2413 case '@':
2414 case '!':
2415 case '&':
2416 case '$':
2417 case '?':
2418 case '/':
2419 case '<':
2420 case '>':
3e602632 2421 case 'b':
252b5132
RH		 2422 case 'm':
2423 case 'n':
2424 case 'o':
2425 case 'p':
2426 case 'q':
2427 case 'v':
3e602632
NC		 2428 case 'w':
2429 case 'y':
2430 case 'z':
fd99574b 2431 case '4':
252b5132
RH		 2432#ifndef NO_68851
2433 case '|':
2434#endif
2435 switch (opP->mode)
2436 {
2437 case IMMED:
2438 tmpreg = 0x3c; /* 7.4 */
2439 if (strchr ("bwl", s[1]))
3e602632 2440 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2441 else
2442 nextword = get_num (&opP->disp, 0);
2443 if (isvar (&opP->disp))
2444 add_fix (s[1], &opP->disp, 0, 0);
2445 switch (s[1])
2446 {
2447 case 'b':
2448 if (!isbyte (nextword))
2449 opP->error = _("operand out of range");
2450 addword (nextword);
2451 baseo = 0;
2452 break;
2453 case 'w':
2454 if (!isword (nextword))
2455 opP->error = _("operand out of range");
2456 addword (nextword);
2457 baseo = 0;
2458 break;
2459 case 'W':
2460 if (!issword (nextword))
2461 opP->error = _("operand out of range");
2462 addword (nextword);
2463 baseo = 0;
2464 break;
2465 case 'l':
2466 addword (nextword >> 16);
2467 addword (nextword);
2468 baseo = 0;
2469 break;
2470
2471 case 'f':
2472 baseo = 2;
2473 outro = 8;
2474 break;
2475 case 'F':
2476 baseo = 4;
2477 outro = 11;
2478 break;
2479 case 'x':
2480 baseo = 6;
2481 outro = 15;
2482 break;
2483 case 'p':
2484 baseo = 6;
2485 outro = -1;
2486 break;
2487 default:
2488 abort ();
2489 }
2490 if (!baseo)
2491 break;
2492
36759679 2493 /* We gotta put out some float. */
252b5132
RH		 2494 if (op (&opP->disp) != O_big)
2495 {
2496 valueT val;
2497 int gencnt;
2498
2499 /* Can other cases happen here? */
2500 if (op (&opP->disp) != O_constant)
2501 abort ();
2502
2503 val = (valueT) offs (&opP->disp);
2504 gencnt = 0;
2505 do
2506 {
2507 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2508 val >>= LITTLENUM_NUMBER_OF_BITS;
2509 ++gencnt;
2510 }
2511 while (val != 0);
2512 offs (&opP->disp) = gencnt;
2513 }
2514 if (offs (&opP->disp) > 0)
2515 {
2516 if (offs (&opP->disp) > baseo)
2517 {
2518 as_warn (_("Bignum too big for %c format; truncated"),
2519 s[1]);
2520 offs (&opP->disp) = baseo;
2521 }
2522 baseo -= offs (&opP->disp);
2523 while (baseo--)
2524 addword (0);
2525 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2526 offs (&opP->disp)--;
2527 --wordp)
2528 addword (*wordp);
2529 break;
2530 }
2531 gen_to_words (words, baseo, (long) outro);
2532 for (wordp = words; baseo--; wordp++)
2533 addword (*wordp);
2534 break;
2535 case DREG:
2536 tmpreg = opP->reg - DATA; /* 0.dreg */
2537 break;
2538 case AREG:
2539 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2540 break;
2541 case AINDR:
2542 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2543 break;
2544 case ADEC:
2545 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2546 break;
2547 case AINC:
2548 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2549 break;
2550 case DISP:
2551
3e602632 2552 nextword = get_num (&opP->disp, 90);
252b5132 2553
580b9172
NC		 2554 /* Convert mode 5 addressing with a zero offset into
2555 mode 2 addressing to reduce the instruction size by a
2556 word. */
2557 if (! isvar (&opP->disp)
2558 && (nextword == 0)
2559 && (opP->disp.size == SIZE_UNSPEC)
2560 && (opP->reg >= ADDR0)
2561 && (opP->reg <= ADDR7))
2562 {
2563 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2564 break;
2565 }
2566
252b5132
RH		 2567 if (opP->reg == PC
2568 && ! isvar (&opP->disp)
2569 && m68k_abspcadd)
2570 {
2571 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2572 opP->disp.exp.X_add_symbol =
2573 section_symbol (absolute_section);
252b5132
RH		 2574 }
2575
36759679 2576 /* Force into index mode. Hope this works. */
252b5132
RH		 2577
2578 /* We do the first bit for 32-bit displacements, and the
2579 second bit for 16 bit ones. It is possible that we
2580 should make the default be WORD instead of LONG, but
2581 I think that'd break GCC, so we put up with a little
2582 inefficiency for the sake of working output. */
2583
2584 if (!issword (nextword)
2585 || (isvar (&opP->disp)
2586 && ((opP->disp.size == SIZE_UNSPEC
2587 && flag_short_refs == 0
2588 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2589 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2590 || opP->disp.size == SIZE_LONG)))
2591 {
2592 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2593 || arch_coldfire_p (current_architecture))
252b5132
RH		 2594 opP->error =
2595 _("displacement too large for this architecture; needs 68020 or higher");
2596 if (opP->reg == PC)
2597 tmpreg = 0x3B; /* 7.3 */
2598 else
2599 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2600 if (isvar (&opP->disp))
2601 {
2602 if (opP->reg == PC)
2603 {
2604 if (opP->disp.size == SIZE_LONG
252b5132
RH		 2605 /* If the displacement needs pic
2606 relocation it cannot be relaxed. */
dc12032b 2607 || opP->disp.pic_reloc != pic_none)
252b5132
RH		 2608 {
2609 addword (0x0170);
2610 add_fix ('l', &opP->disp, 1, 2);
2611 }
2612 else
2613 {
2614 add_frag (adds (&opP->disp),
bd17c2c3 2615 SEXT (offs (&opP->disp)),
151337e8 2616 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2617 break;
2618 }
2619 }
2620 else
2621 {
2622 addword (0x0170);
2623 add_fix ('l', &opP->disp, 0, 0);
2624 }
2625 }
2626 else
2627 addword (0x0170);
2628 addword (nextword >> 16);
2629 }
2630 else
2631 {
2632 if (opP->reg == PC)
2633 tmpreg = 0x3A; /* 7.2 */
2634 else
2635 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2636
2637 if (isvar (&opP->disp))
2638 {
2639 if (opP->reg == PC)
2640 {
2641 add_fix ('w', &opP->disp, 1, 0);
2642 }
2643 else
2644 add_fix ('w', &opP->disp, 0, 0);
2645 }
2646 }
2647 addword (nextword);
2648 break;
2649
2650 case POST:
2651 case PRE:
2652 case BASE:
2653 nextword = 0;
3e602632 2654 baseo = get_num (&opP->disp, 90);
252b5132 2655 if (opP->mode == POST || opP->mode == PRE)
3e602632 2656 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2657 /* Figure out the `addressing mode'.
2658 Also turn on the BASE_DISABLE bit, if needed. */
2659 if (opP->reg == PC || opP->reg == ZPC)
2660 {
2661 tmpreg = 0x3b; /* 7.3 */
2662 if (opP->reg == ZPC)
2663 nextword |= 0x80;
2664 }
2665 else if (opP->reg == 0)
2666 {
2667 nextword |= 0x80;
2668 tmpreg = 0x30; /* 6.garbage */
2669 }
2670 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2671 {
2672 nextword |= 0x80;
2673 tmpreg = 0x30 + opP->reg - ZADDR0;
2674 }
2675 else
2676 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2677
2678 siz1 = opP->disp.size;
2679 if (opP->mode == POST || opP->mode == PRE)
2680 siz2 = opP->odisp.size;
2681 else
2682 siz2 = SIZE_UNSPEC;
2683
36759679 2684 /* Index register stuff. */
252b5132
RH		 2685 if (opP->index.reg != 0
2686 && opP->index.reg >= DATA
2687 && opP->index.reg <= ADDR7)
2688 {
2689 nextword |= (opP->index.reg - DATA) << 12;
2690
2691 if (opP->index.size == SIZE_LONG
2692 || (opP->index.size == SIZE_UNSPEC
2693 && m68k_index_width_default == SIZE_LONG))
2694 nextword |= 0x800;
2695
92774660 2696 if ((opP->index.scale != 1
252b5132 2697 && cpu_of_arch (current_architecture) < m68020)
92774660 2698 || (opP->index.scale == 8
3e602632 2699 && (arch_coldfire_p (current_architecture)
6b6e92f4 2700 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2701 {
2702 opP->error =
2703 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2704 }
2705
6da466c7
ILT		 2706 if (arch_coldfire_p (current_architecture)
2707 && opP->index.size == SIZE_WORD)
2708 opP->error = _("invalid index size for coldfire");
2709
252b5132
RH		 2710 switch (opP->index.scale)
2711 {
2712 case 1:
2713 break;
2714 case 2:
2715 nextword |= 0x200;
2716 break;
2717 case 4:
2718 nextword |= 0x400;
2719 break;
2720 case 8:
2721 nextword |= 0x600;
2722 break;
2723 default:
2724 abort ();
2725 }
33eaf5de 2726 /* IF it's simple,
252b5132
RH		 2727 GET US OUT OF HERE! */
2728
2729 /* Must be INDEX, with an index register. Address
2730 register cannot be ZERO-PC, and either :b was
2731 forced, or we know it will fit. For a 68000 or
2732 68010, force this mode anyways, because the
2733 larger modes aren't supported. */
2734 if (opP->mode == BASE
2735 && ((opP->reg >= ADDR0
2736 && opP->reg <= ADDR7)
2737 || opP->reg == PC))
2738 {
2739 if (siz1 == SIZE_BYTE
2740 || cpu_of_arch (current_architecture) < m68020
6da466c7 2741 || arch_coldfire_p (current_architecture)
252b5132
RH		 2742 || (siz1 == SIZE_UNSPEC
2743 && ! isvar (&opP->disp)
2744 && issbyte (baseo)))
2745 {
2746 nextword += baseo & 0xff;
2747 addword (nextword);
2748 if (isvar (&opP->disp))
2749 {
2750 /* Do a byte relocation. If it doesn't
2751 fit (possible on m68000) let the
2752 fixup processing complain later. */
2753 if (opP->reg == PC)
2754 add_fix ('B', &opP->disp, 1, 1);
2755 else
2756 add_fix ('B', &opP->disp, 0, 0);
2757 }
2758 else if (siz1 != SIZE_BYTE)
2759 {
2760 if (siz1 != SIZE_UNSPEC)
2761 as_warn (_("Forcing byte displacement"));
2762 if (! issbyte (baseo))
2763 opP->error = _("byte displacement out of range");
2764 }
2765
2766 break;
2767 }
2768 else if (siz1 == SIZE_UNSPEC
2769 && opP->reg == PC
2770 && isvar (&opP->disp)
2771 && subs (&opP->disp) == NULL
252b5132
RH		 2772 /* If the displacement needs pic
2773 relocation it cannot be relaxed. */
dc12032b 2774 && opP->disp.pic_reloc == pic_none)
252b5132
RH		 2775 {
2776 /* The code in md_convert_frag_1 needs to be
2777 able to adjust nextword. Call frag_grow
2778 to ensure that we have enough space in
2779 the frag obstack to make all the bytes
2780 contiguous. */
2781 frag_grow (14);
8a104df9
KH		 2782 nextword += baseo & 0xff;
2783 addword (nextword);
bd17c2c3
AM		 2784 add_frag (adds (&opP->disp),
2785 SEXT (offs (&opP->disp)),
8a104df9 2786 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2787
2788 break;
8a104df9 2789 }
252b5132
RH		 2790 }
2791 }
2792 else
2793 {
36759679 2794 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2795 if (opP->index.reg >= ZDATA0
2796 && opP->index.reg <= ZDATA7)
2797 nextword |= (opP->index.reg - ZDATA0) << 12;
2798 else if (opP->index.reg >= ZADDR0
59e28a97 2799 && opP->index.reg <= ZADDR7)
252b5132
RH		 2800 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2801 }
2802
2803 /* It isn't simple. */
2804
2805 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2806 || arch_coldfire_p (current_architecture))
252b5132
RH		 2807 opP->error =
2808 _("invalid operand mode for this architecture; needs 68020 or higher");
2809
2810 nextword |= 0x100;
2811 /* If the guy specified a width, we assume that it is
2812 wide enough. Maybe it isn't. If so, we lose. */
2813 switch (siz1)
2814 {
2815 case SIZE_UNSPEC:
2816 if (isvar (&opP->disp)
2817 ? m68k_rel32
2818 : ! issword (baseo))
2819 {
2820 siz1 = SIZE_LONG;
2821 nextword |= 0x30;
2822 }
2823 else if (! isvar (&opP->disp) && baseo == 0)
2824 nextword |= 0x10;
2825 else
2826 {
2827 nextword |= 0x20;
2828 siz1 = SIZE_WORD;
2829 }
2830 break;
2831 case SIZE_BYTE:
2832 as_warn (_(":b not permitted; defaulting to :w"));
2833 /* Fall through. */
2834 case SIZE_WORD:
2835 nextword |= 0x20;
2836 break;
2837 case SIZE_LONG:
2838 nextword |= 0x30;
2839 break;
2840 }
2841
67c1ffbe 2842 /* Figure out inner displacement stuff. */
252b5132
RH		 2843 if (opP->mode == POST || opP->mode == PRE)
2844 {
2845 if (cpu_of_arch (current_architecture) & cpu32)
2846 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2847 switch (siz2)
2848 {
2849 case SIZE_UNSPEC:
2850 if (isvar (&opP->odisp)
2851 ? m68k_rel32
2852 : ! issword (outro))
2853 {
2854 siz2 = SIZE_LONG;
2855 nextword |= 0x3;
2856 }
2857 else if (! isvar (&opP->odisp) && outro == 0)
2858 nextword |= 0x1;
2859 else
2860 {
2861 nextword |= 0x2;
2862 siz2 = SIZE_WORD;
2863 }
2864 break;
2865 case 1:
2866 as_warn (_(":b not permitted; defaulting to :w"));
2867 /* Fall through. */
2868 case 2:
2869 nextword |= 0x2;
2870 break;
2871 case 3:
2872 nextword |= 0x3;
2873 break;
2874 }
2875 if (opP->mode == POST
2876 && (nextword & 0x40) == 0)
2877 nextword |= 0x04;
2878 }
2879 addword (nextword);
2880
2881 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2882 {
2883 if (opP->reg == PC || opP->reg == ZPC)
2884 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2885 else
2886 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2887 }
2888 if (siz1 == SIZE_LONG)
2889 addword (baseo >> 16);
2890 if (siz1 != SIZE_UNSPEC)
2891 addword (baseo);
2892
2893 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2894 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2895 if (siz2 == SIZE_LONG)
2896 addword (outro >> 16);
2897 if (siz2 != SIZE_UNSPEC)
2898 addword (outro);
2899
2900 break;
2901
2902 case ABSL:
3e602632 2903 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2904 switch (opP->disp.size)
2905 {
2906 default:
2907 abort ();
2908 case SIZE_UNSPEC:
2909 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2910 {
2911 tmpreg = 0x38; /* 7.0 */
2912 addword (nextword);
2913 break;
2914 }
252b5132
RH		 2915 if (isvar (&opP->disp)
2916 && !subs (&opP->disp)
2917 && adds (&opP->disp)
252b5132
RH		 2918 /* If the displacement needs pic relocation it
2919 cannot be relaxed. */
2920 && opP->disp.pic_reloc == pic_none
252b5132
RH		 2921 && !flag_long_jumps
2922 && !strchr ("~%&$?", s[0]))
2923 {
2924 tmpreg = 0x3A; /* 7.2 */
2925 add_frag (adds (&opP->disp),
bd17c2c3 2926 SEXT (offs (&opP->disp)),
151337e8 2927 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2928 break;
2929 }
1a0670f3 2930 /* Fall through. */
252b5132
RH		 2931 case SIZE_LONG:
2932 if (isvar (&opP->disp))
2933 add_fix ('l', &opP->disp, 0, 0);
2934
2935 tmpreg = 0x39;/* 7.1 mode */
2936 addword (nextword >> 16);
2937 addword (nextword);
2938 break;
2939
2940 case SIZE_BYTE:
2941 as_bad (_("unsupported byte value; use a different suffix"));
2942 /* Fall through. */
36759679
NC		 2943
2944 case SIZE_WORD:
252b5132
RH		 2945 if (isvar (&opP->disp))
2946 add_fix ('w', &opP->disp, 0, 0);
2947
2948 tmpreg = 0x38;/* 7.0 mode */
2949 addword (nextword);
2950 break;
2951 }
2952 break;
2953 case CONTROL:
2954 case FPREG:
2955 default:
2956 as_bad (_("unknown/incorrect operand"));
bc805888 2957 /* abort (); */
252b5132 2958 }
fd99574b
NC		 2959
2960 /* If s[0] is '4', then this is for the mac instructions
2961 that can have a trailing_ampersand set. If so, set 0x100
2962 bit on tmpreg so install_gen_operand can check for it and
2963 set the appropriate bit (word2, bit 5). */
2964 if (s[0] == '4')
2965 {
2966 if (opP->trailing_ampersand)
2967 tmpreg |= 0x100;
2968 }
252b5132
RH		 2969 install_gen_operand (s[1], tmpreg);
2970 break;
2971
2972 case '#':
2973 case '^':
2974 switch (s[1])
2975 { /* JF: I hate floating point! */
2976 case 'j':
2977 tmpreg = 70;
2978 break;
2979 case '8':
2980 tmpreg = 20;
2981 break;
2982 case 'C':
2983 tmpreg = 50;
2984 break;
2985 case '3':
2986 default:
3e602632 2987 tmpreg = 90;
252b5132
RH		 2988 break;
2989 }
2990 tmpreg = get_num (&opP->disp, tmpreg);
2991 if (isvar (&opP->disp))
2992 add_fix (s[1], &opP->disp, 0, 0);
2993 switch (s[1])
2994 {
2995 case 'b': /* Danger: These do no check for
2996 certain types of overflow.
2997 user beware! */
2998 if (!isbyte (tmpreg))
2999 opP->error = _("out of range");
3000 insop (tmpreg, opcode);
3001 if (isvar (&opP->disp))
3002 the_ins.reloc[the_ins.nrel - 1].n =
3003 (opcode->m_codenum) * 2 + 1;
3004 break;
3005 case 'B':
3006 if (!issbyte (tmpreg))
3007 opP->error = _("out of range");
3008 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3009 if (isvar (&opP->disp))
3010 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3011 break;
3012 case 'w':
3013 if (!isword (tmpreg))
3014 opP->error = _("out of range");
3015 insop (tmpreg, opcode);
3016 if (isvar (&opP->disp))
3017 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3018 break;
3019 case 'W':
3020 if (!issword (tmpreg))
3021 opP->error = _("out of range");
3022 insop (tmpreg, opcode);
3023 if (isvar (&opP->disp))
3024 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3025 break;
3026 case 'l':
3027 /* Because of the way insop works, we put these two out
3028 backwards. */
3029 insop (tmpreg, opcode);
3030 insop (tmpreg >> 16, opcode);
3031 if (isvar (&opP->disp))
3032 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3033 break;
3034 case '3':
3035 tmpreg &= 0xFF;
1a0670f3 3036 /* Fall through. */
252b5132
RH		 3037 case '8':
3038 case 'C':
3039 case 'j':
3040 install_operand (s[1], tmpreg);
3041 break;
3042 default:
3043 abort ();
3044 }
3045 break;
3046
3047 case '+':
3048 case '-':
3049 case 'A':
3050 case 'a':
3051 install_operand (s[1], opP->reg - ADDR);
3052 break;
3053
3054 case 'B':
3e602632 3055 tmpreg = get_num (&opP->disp, 90);
3739860c 3056
252b5132
RH		 3057 switch (s[1])
3058 {
3059 case 'B':
8390138c 3060 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 3061 break;
3062 case 'W':
3063 add_fix ('w', &opP->disp, 1, 0);
3064 addword (0);
3065 break;
3066 case 'L':
3067 long_branch:
151337e8 3068 the_ins.opcode[0] |= 0xff;
252b5132
RH		 3069 add_fix ('l', &opP->disp, 1, 0);
3070 addword (0);
3071 addword (0);
3072 break;
9a2e615a
NS		 3073 case 'g': /* Conditional branch */
3074 have_disp = HAVE_LONG_CALL (current_architecture);
3075 goto var_branch;
3739860c 3076
9a2e615a
NS		 3077 case 'b': /* Unconditional branch */
3078 have_disp = HAVE_LONG_BRANCH (current_architecture);
cac27205 3079 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
9a2e615a 3080 goto var_branch;
3739860c 3081
9a2e615a
NS		 3082 case 's': /* Unconditional subroutine */
3083 have_disp = HAVE_LONG_CALL (current_architecture);
3739860c 3084
9a2e615a
NS		 3085 var_branch:
3086 if (subs (&opP->disp) /* We can't relax it. */
9a2e615a
NS		 3087 /* If the displacement needs pic relocation it cannot be
3088 relaxed. */
dc12032b 3089 || opP->disp.pic_reloc != pic_none)
9a2e615a
NS		 3090 {
3091 if (!have_disp)
3092 as_warn (_("Can't use long branches on this architecture"));
3093 goto long_branch;
3094 }
3739860c 3095
252b5132 3096 /* This could either be a symbol, or an absolute
151337e8
NC		 3097 address. If it's an absolute address, turn it into
3098 an absolute jump right here and keep it out of the
3099 relaxer. */
3100 if (adds (&opP->disp) == 0)
3101 {
3102 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 3103 the_ins.opcode[0] = 0x4EF9;
151337e8 3104 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 3105 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 3106 else /* jCC */
3107 {
3108 the_ins.opcode[0] ^= 0x0100;
3109 the_ins.opcode[0] |= 0x0006;
18566f55 3110 addword (0x4EF9);
151337e8
NC		 3111 }
3112 add_fix ('l', &opP->disp, 0, 0);
3113 addword (0);
3114 addword (0);
3115 break;
3116 }
3117
3118 /* Now we know it's going into the relaxer. Now figure
3119 out which mode. We try in this order of preference:
3120 long branch, absolute jump, byte/word branches only. */
9a2e615a 3121 if (have_disp)
bd17c2c3
AM		 3122 add_frag (adds (&opP->disp),
3123 SEXT (offs (&opP->disp)),
151337e8
NC		 3124 TAB (BRANCHBWL, SZ_UNDEF));
3125 else if (! flag_keep_pcrel)
3126 {
3127 if ((the_ins.opcode[0] == 0x6000)
3128 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3129 add_frag (adds (&opP->disp),
3130 SEXT (offs (&opP->disp)),
151337e8
NC		 3131 TAB (BRABSJUNC, SZ_UNDEF));
3132 else
bd17c2c3
AM		 3133 add_frag (adds (&opP->disp),
3134 SEXT (offs (&opP->disp)),
151337e8
NC		 3135 TAB (BRABSJCOND, SZ_UNDEF));
3136 }
252b5132 3137 else
bd17c2c3
AM		 3138 add_frag (adds (&opP->disp),
3139 SEXT (offs (&opP->disp)),
cac27205
NC		 3140 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3141 : TAB (BRANCHBW, SZ_UNDEF)));
252b5132
RH		 3142 break;
3143 case 'w':
3144 if (isvar (&opP->disp))
3145 {
151337e8
NC		 3146 /* Check for DBcc instructions. We can relax them,
3147 but only if we have long branches and/or absolute
3148 jumps. */
3149 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3150 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3151 || ! flag_keep_pcrel))
252b5132 3152 {
151337e8 3153 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3154 add_frag (adds (&opP->disp),
3155 SEXT (offs (&opP->disp)),
151337e8
NC		 3156 TAB (DBCCLBR, SZ_UNDEF));
3157 else
bd17c2c3
AM		 3158 add_frag (adds (&opP->disp),
3159 SEXT (offs (&opP->disp)),
151337e8 3160 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3161 break;
3162 }
252b5132
RH		 3163 add_fix ('w', &opP->disp, 1, 0);
3164 }
3165 addword (0);
3166 break;
36759679 3167 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3168 add_fix ('l', &opP->disp, 1, 0);
3169 addword (0);
3170 addword (0);
3171 break;
36759679 3172 case 'c': /* Var size Coprocesssor branches. */
151337e8 3173 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3174 {
252b5132
RH		 3175 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3176 add_fix ('l', &opP->disp, 1, 0);
3177 addword (0);
3178 addword (0);
3179 }
151337e8 3180 else
bd17c2c3
AM		 3181 add_frag (adds (&opP->disp),
3182 SEXT (offs (&opP->disp)),
151337e8 3183 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3184 break;
3185 default:
3186 abort ();
3187 }
3188 break;
3189
36759679 3190 case 'C': /* Ignore it. */
252b5132
RH		 3191 break;
3192
36759679 3193 case 'd': /* JF this is a kludge. */
252b5132 3194 install_operand ('s', opP->reg - ADDR);
3e602632 3195 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3196 if (!issword (tmpreg))
3197 {
3198 as_warn (_("Expression out of range, using 0"));
3199 tmpreg = 0;
3200 }
3201 addword (tmpreg);
3202 break;
3203
3204 case 'D':
3205 install_operand (s[1], opP->reg - DATA);
3206 break;
3207
fd99574b
NC		 3208 case 'e': /* EMAC ACCx, reg/reg. */
3209 install_operand (s[1], opP->reg - ACC);
3210 break;
3739860c 3211
36759679 3212 case 'E': /* Ignore it. */
6da466c7
ILT		 3213 break;
3214
252b5132
RH		 3215 case 'F':
3216 install_operand (s[1], opP->reg - FP0);
3217 break;
3218
fd99574b
NC		 3219 case 'g': /* EMAC ACCEXTx. */
3220 install_operand (s[1], opP->reg - ACCEXT01);
3221 break;
3222
36759679 3223 case 'G': /* Ignore it. */
6da466c7
ILT		 3224 case 'H':
3225 break;
3226
252b5132
RH		 3227 case 'I':
3228 tmpreg = opP->reg - COP0;
3229 install_operand (s[1], tmpreg);
3230 break;
3231
fd99574b
NC		 3232 case 'i': /* MAC/EMAC scale factor. */
3233 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3234 break;
3235
36759679 3236 case 'J': /* JF foo. */
252b5132
RH		 3237 switch (opP->reg)
3238 {
3239 case SFC:
3240 tmpreg = 0x000;
3241 break;
3242 case DFC:
3243 tmpreg = 0x001;
3244 break;
3245 case CACR:
3246 tmpreg = 0x002;
3247 break;
3248 case TC:
a8e24a56 3249 case ASID:
252b5132
RH		 3250 tmpreg = 0x003;
3251 break;
3e602632 3252 case ACR0:
252b5132
RH		 3253 case ITT0:
3254 tmpreg = 0x004;
3255 break;
3e602632 3256 case ACR1:
252b5132
RH		 3257 case ITT1:
3258 tmpreg = 0x005;
3259 break;
3e602632 3260 case ACR2:
252b5132
RH		 3261 case DTT0:
3262 tmpreg = 0x006;
3263 break;
3e602632 3264 case ACR3:
252b5132
RH		 3265 case DTT1:
3266 tmpreg = 0x007;
3267 break;
3268 case BUSCR:
a8e24a56 3269 case MMUBAR:
252b5132
RH		 3270 tmpreg = 0x008;
3271 break;
0d999f33
MK		 3272 case RGPIOBAR:
3273 tmpreg = 0x009;
3274 break;
3275 case ACR4:
3276 case ACR5:
3277 case ACR6:
3278 case ACR7:
3279 tmpreg = 0x00c + (opP->reg - ACR4);
3280 break;
252b5132
RH		 3281
3282 case USP:
3283 tmpreg = 0x800;
3284 break;
3285 case VBR:
3286 tmpreg = 0x801;
3287 break;
3288 case CAAR:
87298967 3289 case CPUCR:
252b5132
RH		 3290 tmpreg = 0x802;
3291 break;
3292 case MSP:
3293 tmpreg = 0x803;
3294 break;
3295 case ISP:
3296 tmpreg = 0x804;
3297 break;
3298 case MMUSR:
3299 tmpreg = 0x805;
3300 break;
3301 case URP:
3302 tmpreg = 0x806;
3303 break;
3304 case SRP:
3305 tmpreg = 0x807;
3306 break;
3307 case PCR:
3308 tmpreg = 0x808;
3309 break;
3310 case ROMBAR:
a8e24a56 3311 case ROMBAR0:
252b5132
RH		 3312 tmpreg = 0xC00;
3313 break;
3e602632
NC		 3314 case ROMBAR1:
3315 tmpreg = 0xC01;
3316 break;
3317 case FLASHBAR:
252b5132 3318 case RAMBAR0:
78336706 3319 case RAMBAR_ALT:
252b5132
RH		 3320 tmpreg = 0xC04;
3321 break;
3e602632 3322 case RAMBAR:
252b5132
RH		 3323 case RAMBAR1:
3324 tmpreg = 0xC05;
3325 break;
3e602632
NC		 3326 case MPCR:
3327 tmpreg = 0xC0C;
3328 break;
3329 case EDRAMBAR:
3330 tmpreg = 0xC0D;
3331 break;
3332 case MBAR0:
e80e0390 3333 case MBAR2:
3e602632
NC		 3334 case SECMBAR:
3335 tmpreg = 0xC0E;
3336 break;
3337 case MBAR1:
252b5132
RH		 3338 case MBAR:
3339 tmpreg = 0xC0F;
3340 break;
3e602632
NC		 3341 case PCR1U0:
3342 tmpreg = 0xD02;
3343 break;
3344 case PCR1L0:
3345 tmpreg = 0xD03;
3346 break;
3347 case PCR2U0:
3348 tmpreg = 0xD04;
3349 break;
3350 case PCR2L0:
3351 tmpreg = 0xD05;
3352 break;
3353 case PCR3U0:
3354 tmpreg = 0xD06;
3355 break;
3356 case PCR3L0:
3357 tmpreg = 0xD07;
3358 break;
3359 case PCR1L1:
3360 tmpreg = 0xD0A;
3361 break;
3362 case PCR1U1:
3363 tmpreg = 0xD0B;
3364 break;
3365 case PCR2L1:
3366 tmpreg = 0xD0C;
3367 break;
3368 case PCR2U1:
3369 tmpreg = 0xD0D;
3370 break;
3371 case PCR3L1:
3372 tmpreg = 0xD0E;
3373 break;
3374 case PCR3U1:
3375 tmpreg = 0xD0F;
3376 break;
f7ec513b
KH		 3377 case CAC:
3378 tmpreg = 0xFFE;
3379 break;
d0fa1372 3380 case MBO:
f7ec513b
KH		 3381 tmpreg = 0xFFF;
3382 break;
252b5132
RH		 3383 default:
3384 abort ();
3385 }
3386 install_operand (s[1], tmpreg);
3387 break;
3388
3389 case 'k':
3390 tmpreg = get_num (&opP->disp, 55);
3391 install_operand (s[1], tmpreg & 0x7f);
3392 break;
3393
3394 case 'l':
3395 tmpreg = opP->mask;
3396 if (s[1] == 'w')
3397 {
3398 if (tmpreg & 0x7FF0000)
3399 as_bad (_("Floating point register in register list"));
3400 insop (reverse_16_bits (tmpreg), opcode);
3401 }
3402 else
3403 {
3404 if (tmpreg & 0x700FFFF)
3405 as_bad (_("Wrong register in floating-point reglist"));
3406 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3407 }
3408 break;
3409
3410 case 'L':
3411 tmpreg = opP->mask;
3412 if (s[1] == 'w')
3413 {
3414 if (tmpreg & 0x7FF0000)
3415 as_bad (_("Floating point register in register list"));
3416 insop (tmpreg, opcode);
3417 }
3418 else if (s[1] == '8')
3419 {
3420 if (tmpreg & 0x0FFFFFF)
3421 as_bad (_("incorrect register in reglist"));
3422 install_operand (s[1], tmpreg >> 24);
3423 }
3424 else
3425 {
3426 if (tmpreg & 0x700FFFF)
3427 as_bad (_("wrong register in floating-point reglist"));
3428 else
3429 install_operand (s[1], tmpreg >> 16);
3430 }
3431 break;
3432
3433 case 'M':
3434 install_operand (s[1], get_num (&opP->disp, 60));
3435 break;
3436
3437 case 'O':
3438 tmpreg = ((opP->mode == DREG)
8fce3f5e 3439 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3440 : (get_num (&opP->disp, 40) & 0x1F));
3441 install_operand (s[1], tmpreg);
3442 break;
3443
3444 case 'Q':
3445 tmpreg = get_num (&opP->disp, 10);
3446 if (tmpreg == 8)
3447 tmpreg = 0;
3448 install_operand (s[1], tmpreg);
3449 break;
3450
3451 case 'R':
3452 /* This depends on the fact that ADDR registers are eight
3453 more than their corresponding DATA regs, so the result
36759679 3454 will have the ADDR_REG bit set. */
252b5132
RH		 3455 install_operand (s[1], opP->reg - DATA);
3456 break;
3457
3458 case 'r':
3459 if (opP->mode == AINDR)
3460 install_operand (s[1], opP->reg - DATA);
3461 else
3462 install_operand (s[1], opP->index.reg - DATA);
3463 break;
3464
3465 case 's':
3466 if (opP->reg == FPI)
3467 tmpreg = 0x1;
3468 else if (opP->reg == FPS)
3469 tmpreg = 0x2;
3470 else if (opP->reg == FPC)
3471 tmpreg = 0x4;
3472 else
3473 abort ();
3474 install_operand (s[1], tmpreg);
3475 break;
3476
36759679 3477 case 'S': /* Ignore it. */
252b5132
RH		 3478 break;
3479
3480 case 'T':
3481 install_operand (s[1], get_num (&opP->disp, 30));
3482 break;
3483
36759679 3484 case 'U': /* Ignore it. */
252b5132
RH		 3485 break;
3486
3487 case 'c':
3488 switch (opP->reg)
3489 {
3490 case NC:
3491 tmpreg = 0;
3492 break;
3493 case DC:
3494 tmpreg = 1;
3495 break;
3496 case IC:
3497 tmpreg = 2;
3498 break;
3499 case BC:
3500 tmpreg = 3;
3501 break;
3502 default:
3503 as_fatal (_("failed sanity check"));
36759679 3504 } /* switch on cache token. */
252b5132
RH		 3505 install_operand (s[1], tmpreg);
3506 break;
3507#ifndef NO_68851
92774660 3508 /* JF: These are out of order, I fear. */
252b5132
RH		 3509 case 'f':
3510 switch (opP->reg)
3511 {
3512 case SFC:
3513 tmpreg = 0;
3514 break;
3515 case DFC:
3516 tmpreg = 1;
3517 break;
3518 default:
3519 abort ();
3520 }
3521 install_operand (s[1], tmpreg);
3522 break;
3523
3524 case '0':
3525 case '1':
3526 case '2':
3527 switch (opP->reg)
3528 {
3529 case TC:
3530 tmpreg = 0;
3531 break;
3532 case CAL:
3533 tmpreg = 4;
3534 break;
3535 case VAL:
3536 tmpreg = 5;
3537 break;
3538 case SCC:
3539 tmpreg = 6;
3540 break;
3541 case AC:
3542 tmpreg = 7;
3543 break;
3544 default:
3545 abort ();
3546 }
3547 install_operand (s[1], tmpreg);
3548 break;
3549
3550 case 'V':
3551 if (opP->reg == VAL)
3552 break;
3553 abort ();
3554
3555 case 'W':
3556 switch (opP->reg)
3557 {
3558 case DRP:
3559 tmpreg = 1;
3560 break;
3561 case SRP:
3562 tmpreg = 2;
3563 break;
3564 case CRP:
3565 tmpreg = 3;
3566 break;
3567 default:
3568 abort ();
3569 }
3570 install_operand (s[1], tmpreg);
3571 break;
3572
3573 case 'X':
3574 switch (opP->reg)
3575 {
3576 case BAD:
3577 case BAD + 1:
3578 case BAD + 2:
3579 case BAD + 3:
3580 case BAD + 4:
3581 case BAD + 5:
3582 case BAD + 6:
3583 case BAD + 7:
3584 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3585 break;
3586
3587 case BAC:
3588 case BAC + 1:
3589 case BAC + 2:
3590 case BAC + 3:
3591 case BAC + 4:
3592 case BAC + 5:
3593 case BAC + 6:
3594 case BAC + 7:
3595 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3596 break;
3597
3598 default:
3599 abort ();
3600 }
3601 install_operand (s[1], tmpreg);
3602 break;
3603 case 'Y':
3604 know (opP->reg == PSR);
3605 break;
3606 case 'Z':
3607 know (opP->reg == PCSR);
3608 break;
3609#endif /* m68851 */
3610 case '3':
3611 switch (opP->reg)
3612 {
3613 case TT0:
3614 tmpreg = 2;
3615 break;
3616 case TT1:
3617 tmpreg = 3;
3618 break;
3619 default:
3620 abort ();
3621 }
3622 install_operand (s[1], tmpreg);
3623 break;
3624 case 't':
3625 tmpreg = get_num (&opP->disp, 20);
3626 install_operand (s[1], tmpreg);
3627 break;
36759679 3628 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3629 if (isvar (&opP->disp))
3630 add_fix ('l', &opP->disp, 0, 0);
3e602632 3631 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3632 addword (tmpreg >> 16);
3633 addword (tmpreg & 0xFFFF);
3634 break;
6da466c7
ILT		 3635 case 'u':
3636 install_operand (s[1], opP->reg - DATA0L);
3637 opP->reg -= (DATA0L);
36759679 3638 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3639 break;
3e602632
NC		 3640 case 'x':
3641 tmpreg = get_num (&opP->disp, 80);
3642 if (tmpreg == -1)
3643 tmpreg = 0;
3644 install_operand (s[1], tmpreg);
3645 break;
afa2158f
NS		 3646 case 'j':
3647 tmpreg = get_num (&opP->disp, 10);
3648 install_operand (s[1], tmpreg - 1);
3649 break;
3650 case 'K':
3651 tmpreg = get_num (&opP->disp, 65);
3652 install_operand (s[1], tmpreg);
3653 break;
252b5132
RH		 3654 default:
3655 abort ();
3656 }
3657 }
3658
33eaf5de 3659 /* By the time when get here (FINALLY) the_ins contains the complete
92774660 3660 instruction, ready to be emitted. . . */
252b5132
RH		 3661}
3662
3663static int
31302357 3664reverse_16_bits (int in)
252b5132
RH		 3665{
3666 int out = 0;
3667 int n;
3668
3669 static int mask[16] =
3670 {
3671 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3672 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3673 };
3674 for (n = 0; n < 16; n++)
3675 {
3676 if (in & mask[n])
3677 out |= mask[15 - n];
3678 }
3679 return out;
3680} /* reverse_16_bits() */
3681
3682static int
31302357 3683reverse_8_bits (int in)
252b5132
RH		 3684{
3685 int out = 0;
3686 int n;
3687
3688 static int mask[8] =
3689 {
3690 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3691 };
3692
3693 for (n = 0; n < 8; n++)
3694 {
3695 if (in & mask[n])
3696 out |= mask[7 - n];
3697 }
3698 return out;
3699} /* reverse_8_bits() */
3700
cac27205
NC		 3701/* Cause an extra frag to be generated here, inserting up to
3702 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3703 generated; its primary type is rs_machine_dependent.
252b5132
RH		 3704
3705 The TYPE parameter is also used by md_convert_frag_1 and
3706 md_estimate_size_before_relax. The appropriate type of fixup will
3707 be emitted by md_convert_frag_1.
3708
3709 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3710static void
31302357 3711install_operand (int mode, int val)
252b5132
RH		 3712{
3713 switch (mode)
3714 {
3715 case 's':
36759679 3716 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3717 break;
3718 case 'd':
3719 the_ins.opcode[0] |= val << 9;
3720 break;
afa2158f
NS		 3721 case 'E':
3722 the_ins.opcode[1] |= val << 9;
3723 break;
252b5132
RH		 3724 case '1':
3725 the_ins.opcode[1] |= val << 12;
3726 break;
3727 case '2':
3728 the_ins.opcode[1] |= val << 6;
3729 break;
3730 case '3':
3731 the_ins.opcode[1] |= val;
3732 break;
3733 case '4':
3734 the_ins.opcode[2] |= val << 12;
3735 break;
3736 case '5':
3737 the_ins.opcode[2] |= val << 6;
3738 break;
3739 case '6':
3740 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3741 three words long! */
3742 the_ins.numo++;
3743 the_ins.opcode[2] |= val;
3744 break;
3745 case '7':
3746 the_ins.opcode[1] |= val << 7;
3747 break;
3748 case '8':
3749 the_ins.opcode[1] |= val << 10;
3750 break;
3751#ifndef NO_68851
3752 case '9':
3753 the_ins.opcode[1] |= val << 5;
3754 break;
3755#endif
3756
3757 case 't':
3758 the_ins.opcode[1] |= (val << 10) | (val << 7);
3759 break;
3760 case 'D':
3761 the_ins.opcode[1] |= (val << 12) | val;
3762 break;
3763 case 'g':
3764 the_ins.opcode[0] |= val = 0xff;
3765 break;
3766 case 'i':
3767 the_ins.opcode[0] |= val << 9;
3768 break;
3769 case 'C':
3770 the_ins.opcode[1] |= val;
3771 break;
3772 case 'j':
3773 the_ins.opcode[1] |= val;
36759679 3774 the_ins.numo++; /* What a hack. */
252b5132
RH		 3775 break;
3776 case 'k':
3777 the_ins.opcode[1] |= val << 4;
3778 break;
3779 case 'b':
3780 case 'w':
3781 case 'W':
3782 case 'l':
3783 break;
3784 case 'e':
3785 the_ins.opcode[0] |= (val << 6);
3786 break;
3787 case 'L':
3788 the_ins.opcode[1] = (val >> 16);
3789 the_ins.opcode[2] = val & 0xffff;
3790 break;
6da466c7
ILT		 3791 case 'm':
3792 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3793 the_ins.opcode[0] |= ((val & 0x7) << 9);
3794 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3795 break;
fd99574b 3796 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3797 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3798 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3799 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3800 break;
fd99574b 3801 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3802 the_ins.opcode[1] |= val << 12;
3803 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3804 break;
fd99574b 3805 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3806 the_ins.opcode[0] |= (val & 0xF);
3807 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3808 break;
fd99574b 3809 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3810 the_ins.opcode[1] |= (val & 0xF);
3811 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3812 break;
3813 case 'h':
3814 the_ins.opcode[1] |= ((val != 1) << 10);
3815 break;
fd99574b
NC		 3816 case 'F':
3817 the_ins.opcode[0] |= ((val & 0x3) << 9);
3818 break;
3819 case 'f':
3820 the_ins.opcode[0] |= ((val & 0x3) << 0);
3821 break;
be8c092b 3822 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3823 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3824 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3825 break;
be8c092b 3826 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3827 the_ins.opcode[0] |= ((val & 0x1) << 7);
3828 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3829 break;
3830 case 'I':
3831 the_ins.opcode[1] |= ((val & 0x3) << 9);
3832 break;
3833 case ']':
3834 the_ins.opcode[0] |= (val & 0x1) <<10;
3835 break;
252b5132
RH		 3836 case 'c':
3837 default:
3838 as_fatal (_("failed sanity check."));
3839 }
6b6e92f4 3840}
252b5132
RH		 3841
3842static void
31302357 3843install_gen_operand (int mode, int val)
252b5132
RH		 3844{
3845 switch (mode)
3846 {
fd99574b 3847 case '/': /* Special for mask loads for mac/msac insns with
33eaf5de 3848 possible mask; trailing_ampersand set in bit 8. */
fd99574b
NC		 3849 the_ins.opcode[0] |= (val & 0x3f);
3850 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3851 break;
252b5132
RH		 3852 case 's':
3853 the_ins.opcode[0] |= val;
3854 break;
3855 case 'd':
3856 /* This is a kludge!!! */
3857 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3858 break;
3859 case 'b':
3860 case 'w':
3861 case 'l':
3862 case 'f':
3863 case 'F':
3864 case 'x':
3865 case 'p':
3866 the_ins.opcode[0] |= val;
3867 break;
36759679 3868 /* more stuff goes here. */
252b5132
RH		 3869 default:
3870 as_fatal (_("failed sanity check."));
3871 }
6b6e92f4 3872}
252b5132 3873
6b6e92f4
NC		 3874/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3875 then deal with the bitfield hack. */
252b5132
RH		 3876
3877static char *
31302357 3878crack_operand (char *str, struct m68k_op *opP)
252b5132 3879{
ed9e98c2
AM		 3880 int parens;
3881 int c;
3882 char *beg_str;
252b5132
RH		 3883 int inquote = 0;
3884
3885 if (!str)
3886 {
3887 return str;
3888 }
3889 beg_str = str;
3890 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3891 {
3892 if (! inquote)
3893 {
3894 if (*str == '(')
3895 parens++;
3896 else if (*str == ')')
3897 {
3898 if (!parens)
36759679 3899 { /* ERROR. */
252b5132
RH		 3900 opP->error = _("Extra )");
3901 return str;
3902 }
3903 --parens;
3904 }
3905 }
3906 if (flag_mri && *str == '\'')
3907 inquote = ! inquote;
3908 }
3909 if (!*str && parens)
36759679 3910 { /* ERROR. */
252b5132
RH		 3911 opP->error = _("Missing )");
3912 return str;
3913 }
3914 c = *str;
3915 *str = '\0';
3916 if (m68k_ip_op (beg_str, opP) != 0)
3917 {
3918 *str = c;
3919 return str;
3920 }
3921 *str = c;
3922 if (c == '}')
36759679 3923 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3924 if (c)
3925 {
3926 c = *++str;
3927 if (!c)
3928 as_bad (_("Missing operand"));
3929 }
3930
3931 /* Detect MRI REG symbols and convert them to REGLSTs. */
3932 if (opP->mode == CONTROL && (int)opP->reg < 0)
3933 {
3934 opP->mode = REGLST;
3935 opP->mask = ~(int)opP->reg;
3936 opP->reg = 0;
3937 }
3938
3939 return str;
3940}
3941
3942/* This is the guts of the machine-dependent assembler. STR points to a
3943 machine dependent instruction. This function is supposed to emit
3944 the frags/bytes it assembles to.
3945 */
3946
3947static void
31302357 3948insert_reg (const char *regname, int regnum)
252b5132
RH		 3949{
3950 char buf[100];
3951 int i;
3952
3953#ifdef REGISTER_PREFIX
3954 if (!flag_reg_prefix_optional)
3955 {
3956 buf[0] = REGISTER_PREFIX;
3957 strcpy (buf + 1, regname);
3958 regname = buf;
3959 }
3960#endif
3961
3962 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3963 &zero_address_frag));
3964
3965 for (i = 0; regname[i]; i++)
3882b010 3966 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3967 buf[i] = '\0';
3968
3969 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3970 &zero_address_frag));
3971}
3972
3973struct init_entry
3974 {
3975 const char *name;
3976 int number;
3977 };
3978
3979static const struct init_entry init_table[] =
3980{
3981 { "d0", DATA0 },
3982 { "d1", DATA1 },
3983 { "d2", DATA2 },
3984 { "d3", DATA3 },
3985 { "d4", DATA4 },
3986 { "d5", DATA5 },
3987 { "d6", DATA6 },
3988 { "d7", DATA7 },
3989 { "a0", ADDR0 },
3990 { "a1", ADDR1 },
3991 { "a2", ADDR2 },
3992 { "a3", ADDR3 },
3993 { "a4", ADDR4 },
3994 { "a5", ADDR5 },
3995 { "a6", ADDR6 },
3996 { "fp", ADDR6 },
3997 { "a7", ADDR7 },
3998 { "sp", ADDR7 },
3999 { "ssp", ADDR7 },
4000 { "fp0", FP0 },
4001 { "fp1", FP1 },
4002 { "fp2", FP2 },
4003 { "fp3", FP3 },
4004 { "fp4", FP4 },
4005 { "fp5", FP5 },
4006 { "fp6", FP6 },
4007 { "fp7", FP7 },
4008 { "fpi", FPI },
4009 { "fpiar", FPI },
4010 { "fpc", FPI },
4011 { "fps", FPS },
4012 { "fpsr", FPS },
4013 { "fpc", FPC },
4014 { "fpcr", FPC },
4015 { "control", FPC },
4016 { "status", FPS },
4017 { "iaddr", FPI },
4018
4019 { "cop0", COP0 },
4020 { "cop1", COP1 },
4021 { "cop2", COP2 },
4022 { "cop3", COP3 },
4023 { "cop4", COP4 },
4024 { "cop5", COP5 },
4025 { "cop6", COP6 },
4026 { "cop7", COP7 },
4027 { "pc", PC },
4028 { "zpc", ZPC },
4029 { "sr", SR },
4030
4031 { "ccr", CCR },
4032 { "cc", CCR },
4033
6da466c7 4034 { "acc", ACC },
fd99574b
NC		 4035 { "acc0", ACC },
4036 { "acc1", ACC1 },
4037 { "acc2", ACC2 },
4038 { "acc3", ACC3 },
4039 { "accext01", ACCEXT01 },
4040 { "accext23", ACCEXT23 },
6da466c7
ILT		 4041 { "macsr", MACSR },
4042 { "mask", MASK },
4043
36759679
NC		 4044 /* Control registers. */
4045 { "sfc", SFC }, /* Source Function Code. */
252b5132 4046 { "sfcr", SFC },
36759679 4047 { "dfc", DFC }, /* Destination Function Code. */
252b5132 4048 { "dfcr", DFC },
36759679
NC		 4049 { "cacr", CACR }, /* Cache Control Register. */
4050 { "caar", CAAR }, /* Cache Address Register. */
87298967 4051 { "cpucr", CPUCR }, /* CPU Control Register. */
252b5132 4052
36759679
NC		 4053 { "usp", USP }, /* User Stack Pointer. */
4054 { "vbr", VBR }, /* Vector Base Register. */
4055 { "msp", MSP }, /* Master Stack Pointer. */
4056 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 4057
36759679
NC		 4058 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4059 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4060 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4061 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 4062
4063 /* 68ec040 versions of same */
36759679
NC		 4064 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4065 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4066 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4067 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 4068
a8e24a56 4069 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 4070 manual indicated that the order is 2,3,0,1, but Ken Rose
4071 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 4072 { "acr0", ACR0 }, /* Access Control Unit 0. */
4073 { "acr1", ACR1 }, /* Access Control Unit 1. */
4074 { "acr2", ACR2 }, /* Access Control Unit 2. */
4075 { "acr3", ACR3 }, /* Access Control Unit 3. */
0d999f33
MK		 4076 { "acr4", ACR4 }, /* Access Control Unit 4. */
4077 { "acr5", ACR5 }, /* Access Control Unit 5. */
4078 { "acr6", ACR6 }, /* Access Control Unit 6. */
4079 { "acr7", ACR7 }, /* Access Control Unit 7. */
252b5132 4080
36759679 4081 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 4082 { "tcr", TC },
a8e24a56 4083 { "asid", ASID },
252b5132 4084
36759679
NC		 4085 { "mmusr", MMUSR }, /* MMU Status Register. */
4086 { "srp", SRP }, /* User Root Pointer. */
4087 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 4088
4089 { "buscr", BUSCR },
a8e24a56 4090 { "mmubar", MMUBAR },
252b5132
RH		 4091 { "pcr", PCR },
4092
36759679
NC		 4093 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4094 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4095 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4096 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 4097
4098 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4099 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 4100 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 4101 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4102 { "mpcr", MPCR }, /* mcfv4e registers. */
4103 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4104 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4105 { "asid", TC }, /* mcfv4e registers. */
4106 { "mmubar", BUSCR }, /* mcfv4e registers. */
4107 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4108 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4109 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4110 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4111 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4112 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4113 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4114 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4115 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4116 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4117 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4118 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4119
4120 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4121 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 4122
4123 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b 4124
0d999f33
MK		 4125 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4126
f7ec513b 4127 { "cac", CAC }, /* fido registers. */
d0fa1372
KH		 4128 { "mbb", MBO }, /* fido registers (obsolete). */
4129 { "mbo", MBO }, /* fido registers. */
36759679 4130 /* End of control registers. */
252b5132
RH		 4131
4132 { "ac", AC },
4133 { "bc", BC },
4134 { "cal", CAL },
4135 { "crp", CRP },
4136 { "drp", DRP },
4137 { "pcsr", PCSR },
4138 { "psr", PSR },
4139 { "scc", SCC },
4140 { "val", VAL },
4141 { "bad0", BAD0 },
4142 { "bad1", BAD1 },
4143 { "bad2", BAD2 },
4144 { "bad3", BAD3 },
4145 { "bad4", BAD4 },
4146 { "bad5", BAD5 },
4147 { "bad6", BAD6 },
4148 { "bad7", BAD7 },
4149 { "bac0", BAC0 },
4150 { "bac1", BAC1 },
4151 { "bac2", BAC2 },
4152 { "bac3", BAC3 },
4153 { "bac4", BAC4 },
4154 { "bac5", BAC5 },
4155 { "bac6", BAC6 },
4156 { "bac7", BAC7 },
4157
4158 { "ic", IC },
4159 { "dc", DC },
4160 { "nc", NC },
4161
4162 { "tt0", TT0 },
4163 { "tt1", TT1 },
36759679 4164 /* 68ec030 versions of same. */
252b5132
RH		 4165 { "ac0", TT0 },
4166 { "ac1", TT1 },
36759679 4167 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4168 { "acusr", PSR },
4169
4170 /* Suppressed data and address registers. */
4171 { "zd0", ZDATA0 },
4172 { "zd1", ZDATA1 },
4173 { "zd2", ZDATA2 },
4174 { "zd3", ZDATA3 },
4175 { "zd4", ZDATA4 },
4176 { "zd5", ZDATA5 },
4177 { "zd6", ZDATA6 },
4178 { "zd7", ZDATA7 },
4179 { "za0", ZADDR0 },
4180 { "za1", ZADDR1 },
4181 { "za2", ZADDR2 },
4182 { "za3", ZADDR3 },
4183 { "za4", ZADDR4 },
4184 { "za5", ZADDR5 },
4185 { "za6", ZADDR6 },
4186 { "za7", ZADDR7 },
4187
92774660 4188 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4189 { "d0l", DATA0L },
4190 { "d1l", DATA1L },
4191 { "d2l", DATA2L },
4192 { "d3l", DATA3L },
4193 { "d4l", DATA4L },
4194 { "d5l", DATA5L },
4195 { "d6l", DATA6L },
4196 { "d7l", DATA7L },
4197
4198 { "a0l", ADDR0L },
4199 { "a1l", ADDR1L },
4200 { "a2l", ADDR2L },
4201 { "a3l", ADDR3L },
4202 { "a4l", ADDR4L },
4203 { "a5l", ADDR5L },
4204 { "a6l", ADDR6L },
4205 { "a7l", ADDR7L },
4206
4207 { "d0u", DATA0U },
4208 { "d1u", DATA1U },
4209 { "d2u", DATA2U },
4210 { "d3u", DATA3U },
4211 { "d4u", DATA4U },
4212 { "d5u", DATA5U },
4213 { "d6u", DATA6U },
4214 { "d7u", DATA7U },
4215
4216 { "a0u", ADDR0U },
4217 { "a1u", ADDR1U },
4218 { "a2u", ADDR2U },
4219 { "a3u", ADDR3U },
4220 { "a4u", ADDR4U },
4221 { "a5u", ADDR5U },
4222 { "a6u", ADDR6U },
4223 { "a7u", ADDR7U },
4224
252b5132
RH		 4225 { 0, 0 }
4226};
4227
4228static void
31302357 4229init_regtable (void)
252b5132
RH		 4230{
4231 int i;
4232 for (i = 0; init_table[i].name; i++)
4233 insert_reg (init_table[i].name, init_table[i].number);
4234}
4235
252b5132 4236void
31302357 4237md_assemble (char *str)
252b5132
RH		 4238{
4239 const char *er;
4240 short *fromP;
4241 char *toP = NULL;
4242 int m, n = 0;
4243 char *to_beg_P;
4244 int shorts_this_frag;
4245 fixS *fixP;
4246
266abb8f
NS		 4247 if (!selected_cpu && !selected_arch)
4248 {
4249 /* We've not selected an architecture yet. Set the default
4250 now. We do this lazily so that an initial .cpu or .arch directive
4251 can specify. */
4252 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4253 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4254 }
4255 if (!initialized)
4256 m68k_init_arch ();
3739860c 4257
252b5132
RH		 4258 /* In MRI mode, the instruction and operands are separated by a
4259 space. Anything following the operands is a comment. The label
4260 has already been removed. */
4261 if (flag_mri)
4262 {
4263 char *s;
4264 int fields = 0;
4265 int infield = 0;
4266 int inquote = 0;
4267
4268 for (s = str; *s != '\0'; s++)
4269 {
4270 if ((*s == ' ' || *s == '\t') && ! inquote)
4271 {
4272 if (infield)
4273 {
4274 ++fields;
4275 if (fields >= 2)
4276 {
4277 *s = '\0';
4278 break;
4279 }
4280 infield = 0;
4281 }
4282 }
4283 else
4284 {
4285 if (! infield)
4286 infield = 1;
4287 if (*s == '\'')
4288 inquote = ! inquote;
4289 }
4290 }
4291 }
4292
31302357 4293 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4294 m68k_ip (str);
4295 er = the_ins.error;
4296 if (!er)
4297 {
4298 for (n = 0; n < the_ins.numargs; n++)
4299 if (the_ins.operands[n].error)
4300 {
4301 er = the_ins.operands[n].error;
4302 break;
4303 }
4304 }
4305 if (er)
4306 {
4307 as_bad (_("%s -- statement `%s' ignored"), er, str);
4308 return;
4309 }
4310
4311 /* If there is a current label, record that it marks an instruction. */
4312 if (current_label != NULL)
4313 {
4314 current_label->text = 1;
4315 current_label = NULL;
4316 }
4317
f27a3839
AS		 4318 /* Tie dwarf2 debug info to the address at the start of the insn. */
4319 dwarf2_emit_insn (0);
f27a3839 4320
252b5132
RH		 4321 if (the_ins.nfrag == 0)
4322 {
36759679 4323 /* No frag hacking involved; just put it out. */
252b5132
RH		 4324 toP = frag_more (2 * the_ins.numo);
4325 fromP = &the_ins.opcode[0];
4326 for (m = the_ins.numo; m; --m)
4327 {
4328 md_number_to_chars (toP, (long) (*fromP), 2);
4329 toP += 2;
4330 fromP++;
4331 }
36759679 4332 /* Put out symbol-dependent info. */
252b5132
RH		 4333 for (m = 0; m < the_ins.nrel; m++)
4334 {
4335 switch (the_ins.reloc[m].wid)
4336 {
4337 case 'B':
4338 n = 1;
4339 break;
4340 case 'b':
4341 n = 1;
4342 break;
4343 case '3':
4344 n = 1;
4345 break;
4346 case 'w':
4347 case 'W':
4348 n = 2;
4349 break;
4350 case 'l':
4351 n = 4;
4352 break;
4353 default:
33eaf5de 4354 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
252b5132
RH		 4355 the_ins.reloc[m].wid);
4356 }
4357
4358 fixP = fix_new_exp (frag_now,
4359 ((toP - frag_now->fr_literal)
4360 - the_ins.numo * 2 + the_ins.reloc[m].n),
4361 n,
4362 &the_ins.reloc[m].exp,
4363 the_ins.reloc[m].pcrel,
4364 get_reloc_code (n, the_ins.reloc[m].pcrel,
4365 the_ins.reloc[m].pic_reloc));
4366 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4367 if (the_ins.reloc[m].wid == 'B')
4368 fixP->fx_signed = 1;
4369 }
4370 return;
4371 }
4372
36759679 4373 /* There's some frag hacking. */
fbe572f9
AM		 4374 {
4375 /* Calculate the max frag size. */
4376 int wid;
4377
4378 wid = 2 * the_ins.fragb[0].fragoff;
4379 for (n = 1; n < the_ins.nfrag; n++)
4380 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4381 /* frag_var part. */
cac27205 4382 wid += FRAG_VAR_SIZE;
fbe572f9
AM		 4383 /* Make sure the whole insn fits in one chunk, in particular that
4384 the var part is attached, as we access one byte before the
4385 variable frag for byte branches. */
4386 frag_grow (wid);
4387 }
4388
252b5132
RH		 4389 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4390 {
4391 int wid;
4392
4393 if (n == 0)
4394 wid = 2 * the_ins.fragb[n].fragoff;
4395 else
4396 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4397 toP = frag_more (wid);
4398 to_beg_P = toP;
4399 shorts_this_frag = 0;
4400 for (m = wid / 2; m; --m)
4401 {
4402 md_number_to_chars (toP, (long) (*fromP), 2);
4403 toP += 2;
4404 fromP++;
4405 shorts_this_frag++;
4406 }
4407 for (m = 0; m < the_ins.nrel; m++)
4408 {
4409 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4410 {
4411 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4412 break;
4413 }
4414 wid = the_ins.reloc[m].wid;
4415 if (wid == 0)
4416 continue;
4417 the_ins.reloc[m].wid = 0;
4418 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4419
4420 fixP = fix_new_exp (frag_now,
4421 ((toP - frag_now->fr_literal)
4422 - the_ins.numo * 2 + the_ins.reloc[m].n),
4423 wid,
4424 &the_ins.reloc[m].exp,
4425 the_ins.reloc[m].pcrel,
4426 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4427 the_ins.reloc[m].pic_reloc));
4428 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4429 }
cac27205 4430 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
252b5132
RH		 4431 (relax_substateT) (the_ins.fragb[n].fragty),
4432 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4433 }
28a0da39
AM		 4434 gas_assert (the_ins.nfrag >= 1);
4435 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff;
252b5132
RH		 4436 shorts_this_frag = 0;
4437 if (n)
4438 {
055d1eb0 4439 toP = frag_more (n * 2);
252b5132
RH		 4440 while (n--)
4441 {
4442 md_number_to_chars (toP, (long) (*fromP), 2);
4443 toP += 2;
4444 fromP++;
4445 shorts_this_frag++;
4446 }
4447 }
4448 for (m = 0; m < the_ins.nrel; m++)
4449 {
4450 int wid;
4451
4452 wid = the_ins.reloc[m].wid;
4453 if (wid == 0)
4454 continue;
4455 the_ins.reloc[m].wid = 0;
4456 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4457
4458 fixP = fix_new_exp (frag_now,
4459 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4460 - shorts_this_frag * 2),
4461 wid,
4462 &the_ins.reloc[m].exp,
4463 the_ins.reloc[m].pcrel,
4464 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4465 the_ins.reloc[m].pic_reloc));
4466 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4467 }
4468}
4469
60fed2d3
NC		 4470/* Comparison function used by qsort to rank the opcode entries by name. */
4471
4472static int
4473m68k_compare_opcode (const void * v1, const void * v2)
4474{
4475 struct m68k_opcode * op1, * op2;
4476 int ret;
4477
03b13e59
NC		 4478 if (v1 == v2)
4479 return 0;
4480
60fed2d3
NC		 4481 op1 = *(struct m68k_opcode **) v1;
4482 op2 = *(struct m68k_opcode **) v2;
4483
4484 /* Compare the two names. If different, return the comparison.
4485 If the same, return the order they are in the opcode table. */
4486 ret = strcmp (op1->name, op2->name);
4487 if (ret)
4488 return ret;
4489 if (op1 < op2)
4490 return -1;
03b13e59 4491 return 1;
60fed2d3
NC		 4492}
4493
252b5132 4494void
60fed2d3 4495md_begin (void)
252b5132 4496{
60fed2d3
NC		 4497 const struct m68k_opcode *ins;
4498 struct m68k_incant *hack, *slak;
4499 const char *retval = 0; /* Empty string, or error msg text. */
4500 int i;
4501
4502 /* Set up hash tables with 68000 instructions.
4503 similar to what the vax assembler does. */
252b5132
RH		 4504 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4505 a copy of it at runtime, adding in the information we want but isn't
4506 there. I think it'd be better to have an awk script hack the table
4507 at compile time. Or even just xstr the table and use it as-is. But
4508 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4509 names. */
4510
252b5132
RH		 4511 if (flag_mri)
4512 {
4513 flag_reg_prefix_optional = 1;
4514 m68k_abspcadd = 1;
4515 if (! m68k_rel32_from_cmdline)
4516 m68k_rel32 = 0;
4517 }
4518
2b0f3761 4519 /* First sort the opcode table into alphabetical order to separate
60fed2d3
NC		 4520 the order that the assembler wants to see the opcodes from the
4521 order that the disassembler wants to see them. */
325801bd 4522 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes);
60fed2d3
NC		 4523
4524 for (i = m68k_numopcodes; i--;)
4525 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4526
4527 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4528 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4529
252b5132
RH		 4530 op_hash = hash_new ();
4531
4532 obstack_begin (&robyn, 4000);
4533 for (i = 0; i < m68k_numopcodes; i++)
4534 {
aff7ae12 4535 hack = slak = XOBNEW (&robyn, struct m68k_incant);
252b5132
RH		 4536 do
4537 {
60fed2d3
NC		 4538 ins = m68k_sorted_opcodes[i];
4539
afa2158f
NS		 4540 /* We must enter all insns into the table, because .arch and
4541 .cpu directives can change things. */
252b5132 4542 slak->m_operands = ins->args;
252b5132
RH		 4543 slak->m_arch = ins->arch;
4544 slak->m_opcode = ins->opcode;
3739860c 4545
afa2158f
NS		 4546 /* In most cases we can determine the number of opcode words
4547 by checking the second word of the mask. Unfortunately
4548 some instructions have 2 opcode words, but no fixed bits
4549 in the second word. A leading dot in the operands
4550 string also indicates 2 opcodes. */
4551 if (*slak->m_operands == '.')
4552 {
4553 slak->m_operands++;
4554 slak->m_codenum = 2;
4555 }
4556 else if (ins->match & 0xffffL)
4557 slak->m_codenum = 2;
4558 else
4559 slak->m_codenum = 1;
4560 slak->m_opnum = strlen (slak->m_operands) / 2;
3739860c 4561
252b5132 4562 if (i + 1 != m68k_numopcodes
60fed2d3 4563 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4564 {
aff7ae12 4565 slak->m_next = XOBNEW (&robyn, struct m68k_incant);
252b5132
RH		 4566 i++;
4567 }
4568 else
4569 slak->m_next = 0;
4570 slak = slak->m_next;
4571 }
4572 while (slak);
4573
4574 retval = hash_insert (op_hash, ins->name, (char *) hack);
4575 if (retval)
4576 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4577 }
4578
4579 for (i = 0; i < m68k_numaliases; i++)
4580 {
4581 const char *name = m68k_opcode_aliases[i].primary;
4582 const char *alias = m68k_opcode_aliases[i].alias;
5a49b8ac 4583 void *val = hash_find (op_hash, name);
60fed2d3 4584
252b5132
RH		 4585 if (!val)
4586 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4587 retval = hash_insert (op_hash, alias, val);
4588 if (retval)
4589 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4590 }
4591
4592 /* In MRI mode, all unsized branches are variable sized. Normally,
4593 they are word sized. */
4594 if (flag_mri)
4595 {
4596 static struct m68k_opcode_alias mri_aliases[] =
4597 {
4598 { "bhi", "jhi", },
4599 { "bls", "jls", },
4600 { "bcc", "jcc", },
4601 { "bcs", "jcs", },
4602 { "bne", "jne", },
4603 { "beq", "jeq", },
4604 { "bvc", "jvc", },
4605 { "bvs", "jvs", },
4606 { "bpl", "jpl", },
4607 { "bmi", "jmi", },
4608 { "bge", "jge", },
4609 { "blt", "jlt", },
4610 { "bgt", "jgt", },
4611 { "ble", "jle", },
4612 { "bra", "jra", },
4613 { "bsr", "jbsr", },
4614 };
4615
8fce3f5e
AM		 4616 for (i = 0;
4617 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4618 i++)
252b5132
RH		 4619 {
4620 const char *name = mri_aliases[i].primary;
4621 const char *alias = mri_aliases[i].alias;
5a49b8ac 4622 void *val = hash_find (op_hash, name);
60fed2d3 4623
252b5132
RH		 4624 if (!val)
4625 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4626 retval = hash_jam (op_hash, alias, val);
4627 if (retval)
4628 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4629 }
4630 }
4631
8fce3f5e 4632 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4633 {
4634 notend_table[i] = 0;
4635 alt_notend_table[i] = 0;
4636 }
60fed2d3 4637
252b5132
RH		 4638 notend_table[','] = 1;
4639 notend_table['{'] = 1;
4640 notend_table['}'] = 1;
4641 alt_notend_table['a'] = 1;
4642 alt_notend_table['A'] = 1;
4643 alt_notend_table['d'] = 1;
4644 alt_notend_table['D'] = 1;
4645 alt_notend_table['#'] = 1;
4646 alt_notend_table['&'] = 1;
4647 alt_notend_table['f'] = 1;
4648 alt_notend_table['F'] = 1;
4649#ifdef REGISTER_PREFIX
4650 alt_notend_table[REGISTER_PREFIX] = 1;
4651#endif
4652
4653 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4654 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4655 alt_notend_table['('] = 1;
4656
4657 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4658 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4659 alt_notend_table['@'] = 1;
4660
4661 /* We need to put digits in alt_notend_table to handle
60fed2d3 4662 bfextu %d0{24:1},%d0 */
252b5132
RH		 4663 alt_notend_table['0'] = 1;
4664 alt_notend_table['1'] = 1;
4665 alt_notend_table['2'] = 1;
4666 alt_notend_table['3'] = 1;
4667 alt_notend_table['4'] = 1;
4668 alt_notend_table['5'] = 1;
4669 alt_notend_table['6'] = 1;
4670 alt_notend_table['7'] = 1;
4671 alt_notend_table['8'] = 1;
4672 alt_notend_table['9'] = 1;
4673
4674#ifndef MIT_SYNTAX_ONLY
4675 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4676 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4677 {
4678 int n = 0;
60fed2d3 4679
252b5132
RH		 4680 while (mote_pseudo_table[n].poc_name)
4681 {
aff7ae12 4682 hack = XOBNEW (&robyn, struct m68k_incant);
252b5132
RH		 4683 hash_insert (op_hash,
4684 mote_pseudo_table[n].poc_name, (char *) hack);
4685 hack->m_operands = 0;
4686 hack->m_opnum = n;
4687 n++;
4688 }
4689 }
4690#endif
4691
4692 init_regtable ();
4693
252b5132
RH		 4694 record_alignment (text_section, 2);
4695 record_alignment (data_section, 2);
4696 record_alignment (bss_section, 2);
252b5132
RH		 4697}
4698
252b5132
RH		 4699\f
4700/* This is called when a label is defined. */
4701
4702void
31302357 4703m68k_frob_label (symbolS *sym)
252b5132
RH		 4704{
4705 struct label_line *n;
4706
add39d23 4707 n = XNEW (struct label_line);
252b5132
RH		 4708 n->next = labels;
4709 n->label = sym;
3b4dbbbf 4710 n->file = as_where (&n->line);
252b5132
RH		 4711 n->text = 0;
4712 labels = n;
4713 current_label = n;
07a53e5c 4714
07a53e5c 4715 dwarf2_emit_label (sym);
252b5132
RH		 4716}
4717
4718/* This is called when a value that is not an instruction is emitted. */
4719
4720void
31302357 4721m68k_flush_pending_output (void)
252b5132
RH		 4722{
4723 current_label = NULL;
4724}
4725
4726/* This is called at the end of the assembly, when the final value of
4727 the label is known. We warn if this is a text symbol aligned at an
4728 odd location. */
4729
4730void
31302357 4731m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4732{
4733 if (S_GET_SEGMENT (sym) == reg_section
4734 && (int) S_GET_VALUE (sym) < 0)
4735 {
4736 S_SET_SEGMENT (sym, absolute_section);
4737 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4738 }
4739 else if ((S_GET_VALUE (sym) & 1) != 0)
4740 {
4741 struct label_line *l;
4742
4743 for (l = labels; l != NULL; l = l->next)
4744 {
4745 if (l->label == sym)
4746 {
4747 if (l->text)
4748 as_warn_where (l->file, l->line,
4749 _("text label `%s' aligned to odd boundary"),
4750 S_GET_NAME (sym));
4751 break;
4752 }
4753 }
4754 }
4755}
4756\f
4757/* This is called if we go in or out of MRI mode because of the .mri
4758 pseudo-op. */
4759
4760void
31302357 4761m68k_mri_mode_change (int on)
252b5132
RH		 4762{
4763 if (on)
4764 {
4765 if (! flag_reg_prefix_optional)
4766 {
4767 flag_reg_prefix_optional = 1;
4768#ifdef REGISTER_PREFIX
4769 init_regtable ();
4770#endif
4771 }
4772 m68k_abspcadd = 1;
4773 if (! m68k_rel32_from_cmdline)
4774 m68k_rel32 = 0;
4775 }
4776 else
4777 {
4778 if (! reg_prefix_optional_seen)
4779 {
4780#ifdef REGISTER_PREFIX_OPTIONAL
4781 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4782#else
4783 flag_reg_prefix_optional = 0;
4784#endif
4785#ifdef REGISTER_PREFIX
4786 init_regtable ();
4787#endif
4788 }
4789 m68k_abspcadd = 0;
4790 if (! m68k_rel32_from_cmdline)
4791 m68k_rel32 = 1;
4792 }
4793}
4794
6d4af3c2 4795const char *
31302357 4796md_atof (int type, char *litP, int *sizeP)
252b5132 4797{
499ac353 4798 return ieee_md_atof (type, litP, sizeP, TRUE);
252b5132
RH		 4799}
4800
4801void
31302357 4802md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4803{
4804 number_to_chars_bigendian (buf, val, n);
4805}
4806
94f592af 4807void
55cf6793 4808md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4809{
bbe8ef22 4810 offsetT val = *valP;
252b5132
RH		 4811 addressT upper_limit;
4812 offsetT lower_limit;
4813
4814 /* This is unnecessary but it convinces the native rs6000 compiler
4815 to generate the code we want. */
4816 char *buf = fixP->fx_frag->fr_literal;
4817 buf += fixP->fx_where;
36759679 4818 /* End ibm compiler workaround. */
252b5132 4819
bd17c2c3 4820 val = SEXT (val);
252b5132 4821
94f592af
NC		 4822 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4823 fixP->fx_done = 1;
4824
252b5132
RH		 4825 if (fixP->fx_addsy)
4826 {
4827 memset (buf, 0, fixP->fx_size);
36759679 4828 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4829
4830 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4831 && !S_IS_DEFINED (fixP->fx_addsy)
4832 && !S_IS_WEAK (fixP->fx_addsy))
4833 S_SET_WEAK (fixP->fx_addsy);
cf869cce
NC		 4834
4835 switch (fixP->fx_r_type)
4836 {
4837 case BFD_RELOC_68K_TLS_GD32:
4838 case BFD_RELOC_68K_TLS_GD16:
4839 case BFD_RELOC_68K_TLS_GD8:
4840 case BFD_RELOC_68K_TLS_LDM32:
4841 case BFD_RELOC_68K_TLS_LDM16:
4842 case BFD_RELOC_68K_TLS_LDM8:
4843 case BFD_RELOC_68K_TLS_LDO32:
4844 case BFD_RELOC_68K_TLS_LDO16:
4845 case BFD_RELOC_68K_TLS_LDO8:
4846 case BFD_RELOC_68K_TLS_IE32:
4847 case BFD_RELOC_68K_TLS_IE16:
4848 case BFD_RELOC_68K_TLS_IE8:
4849 case BFD_RELOC_68K_TLS_LE32:
4850 case BFD_RELOC_68K_TLS_LE16:
4851 case BFD_RELOC_68K_TLS_LE8:
4852 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4853 break;
4854
4855 default:
4856 break;
4857 }
4858
252b5132
RH		 4859 return;
4860 }
252b5132 4861
252b5132
RH		 4862 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4863 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4864 return;
252b5132
RH		 4865
4866 switch (fixP->fx_size)
4867 {
94f592af
NC		 4868 /* The cast to offsetT below are necessary to make code
4869 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4870 case 1:
4871 *buf++ = val;
4872 upper_limit = 0x7f;
4873 lower_limit = - (offsetT) 0x80;
4874 break;
4875 case 2:
4876 *buf++ = (val >> 8);
4877 *buf++ = val;
4878 upper_limit = 0x7fff;
4879 lower_limit = - (offsetT) 0x8000;
4880 break;
4881 case 4:
4882 *buf++ = (val >> 24);
4883 *buf++ = (val >> 16);
4884 *buf++ = (val >> 8);
4885 *buf++ = val;
4886 upper_limit = 0x7fffffff;
36759679 4887 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4888 break;
4889 default:
4890 BAD_CASE (fixP->fx_size);
4891 }
4892
4893 /* Fix up a negative reloc. */
4894 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4895 {
4896 fixP->fx_addsy = fixP->fx_subsy;
4897 fixP->fx_subsy = NULL;
4898 fixP->fx_tcbit = 1;
4899 }
4900
4901 /* For non-pc-relative values, it's conceivable we might get something
4902 like "0xff" for a byte field. So extend the upper part of the range
4903 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4904 so that we can do any range checking at all. */
4905 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4906 upper_limit = upper_limit * 2 + 1;
4907
4908 if ((addressT) val > upper_limit
4909 && (val > 0 || val < lower_limit))
2b878742
NS		 4910 as_bad_where (fixP->fx_file, fixP->fx_line,
4911 _("value %ld out of range"), (long)val);
252b5132
RH		 4912
4913 /* A one byte PC-relative reloc means a short branch. We can't use
4914 a short branch with a value of 0 or -1, because those indicate
4915 different opcodes (branches with longer offsets). fixup_segment
4916 in write.c may have clobbered fx_pcrel, so we need to examine the
4917 reloc type. */
4918 if ((fixP->fx_pcrel
7be1c489 4919 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4920 && fixP->fx_size == 1
4921 && (fixP->fx_addsy == NULL
4922 || S_IS_DEFINED (fixP->fx_addsy))
4923 && (val == 0 || val == -1))
2b878742
NS		 4924 as_bad_where (fixP->fx_file, fixP->fx_line,
4925 _("invalid byte branch offset"));
252b5132
RH		 4926}
4927
252b5132
RH		 4928/* *fragP has been relaxed to its final size, and now needs to have
4929 the bytes inside it modified to conform to the new size There is UGLY
4930 MAGIC here. ..
4931 */
4932static void
31302357 4933md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4934{
4935 long disp;
2b878742 4936 fixS *fixP = NULL;
252b5132
RH		 4937
4938 /* Address in object code of the displacement. */
ed9e98c2 4939 int object_address = fragP->fr_fix + fragP->fr_address;
252b5132
RH		 4940
4941 /* Address in gas core of the place to store the displacement. */
4942 /* This convinces the native rs6000 compiler to generate the code we
92774660 4943 want. */
ed9e98c2 4944 char *buffer_address = fragP->fr_literal;
252b5132 4945 buffer_address += fragP->fr_fix;
36759679 4946 /* End ibm compiler workaround. */
252b5132
RH		 4947
4948 /* The displacement of the address, from current location. */
4949 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4950 disp = (disp + fragP->fr_offset) - object_address;
4951
252b5132
RH		 4952 switch (fragP->fr_subtype)
4953 {
151337e8
NC		 4954 case TAB (BRANCHBWL, BYTE):
4955 case TAB (BRABSJUNC, BYTE):
4956 case TAB (BRABSJCOND, BYTE):
4957 case TAB (BRANCHBW, BYTE):
cac27205 4958 case TAB (BRANCHBWPL, BYTE):
252b5132
RH		 4959 know (issbyte (disp));
4960 if (disp == 0)
b091f402
AM		 4961 as_bad_where (fragP->fr_file, fragP->fr_line,
4962 _("short branch with zero offset: use :w"));
151337e8 4963 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4964 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4965 fixP->fx_pcrel_adjust = -1;
252b5132 4966 break;
151337e8
NC		 4967 case TAB (BRANCHBWL, SHORT):
4968 case TAB (BRABSJUNC, SHORT):
4969 case TAB (BRABSJCOND, SHORT):
4970 case TAB (BRANCHBW, SHORT):
cac27205 4971 case TAB (BRANCHBWPL, SHORT):
252b5132 4972 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 4973 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4974 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4975 fragP->fr_fix += 2;
4976 break;
4977 case TAB (BRANCHBWL, LONG):
4978 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 4979 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4980 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 4981 fragP->fr_fix += 4;
252b5132 4982 break;
cac27205
NC		 4983 case TAB (BRANCHBWPL, LONG):
4984 /* Here we are converting an unconditional branch into a pair of
4985 conditional branches, in order to get the range. */
4986 fragP->fr_opcode[0] = 0x66; /* bne */
4987 fragP->fr_opcode[1] = 0xFF;
4988 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4989 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4990 fixP->fx_file = fragP->fr_file;
4991 fixP->fx_line = fragP->fr_line;
4992 fragP->fr_fix += 4; /* Skip first offset */
4993 buffer_address += 4;
4994 *buffer_address++ = 0x67; /* beq */
4995 *buffer_address++ = 0xff;
4996 fragP->fr_fix += 2; /* Skip second branch opcode */
4997 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4998 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4999 fragP->fr_fix += 4;
5000 break;
151337e8
NC		 5001 case TAB (BRABSJUNC, LONG):
5002 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 5003 {
36759679 5004 if (flag_keep_pcrel)
2b878742
NS		 5005 as_bad_where (fragP->fr_file, fragP->fr_line,
5006 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 5007 fragP->fr_opcode[0] = 0x4E;
36759679 5008 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 5009 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5010 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5011 fragP->fr_fix += 4;
5012 }
5013 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5014 {
36759679 5015 if (flag_keep_pcrel)
2b878742
NS		 5016 as_bad_where (fragP->fr_file, fragP->fr_line,
5017 _("Conversion of PC relative branch to absolute jump"));
151337e8 5018 fragP->fr_opcode[0] = 0x4E;
36759679 5019 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 5020 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5021 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5022 fragP->fr_fix += 4;
252b5132
RH		 5023 }
5024 else
5025 {
151337e8
NC		 5026 /* This cannot happen, because jbsr and jbra are the only two
5027 unconditional branches. */
5028 abort ();
252b5132
RH		 5029 }
5030 break;
151337e8 5031 case TAB (BRABSJCOND, LONG):
36759679 5032 if (flag_keep_pcrel)
2b878742
NS		 5033 as_bad_where (fragP->fr_file, fragP->fr_line,
5034 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 5035
36759679
NC		 5036 /* Only Bcc 68000 instructions can come here
5037 Change bcc into b!cc/jmp absl long. */
5038 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5039 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 5040
5041 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 5042 different frag, in which case referring to them is a no-no.
92774660 5043 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 5044 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5045 *buffer_address++ = (char) 0xf9;
36759679 5046 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 5047 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5048 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5049 fragP->fr_fix += 4;
5050 break;
5051 case TAB (FBRANCH, SHORT):
5052 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 5053 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5054 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5055 fragP->fr_fix += 2;
5056 break;
5057 case TAB (FBRANCH, LONG):
36759679 5058 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 5059 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5060 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5061 fragP->fr_fix += 4;
252b5132 5062 break;
151337e8
NC		 5063 case TAB (DBCCLBR, SHORT):
5064 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 5065 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5066 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5067 fragP->fr_fix += 2;
5068 break;
5069 case TAB (DBCCLBR, LONG):
36759679
NC		 5070 /* Only DBcc instructions can come here.
5071 Change dbcc into dbcc/bral.
5072 JF: these used to be fr_opcode[2-7], but that's wrong. */
36759679 5073 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 5074 *buffer_address++ = 0x04;
36759679 5075 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 5076 *buffer_address++ = 0x06;
151337e8
NC		 5077 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5078 *buffer_address++ = (char) 0xff;
252b5132 5079
36759679 5080 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5081 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5082 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5083 fragP->fr_fix += 4;
252b5132 5084 break;
151337e8 5085 case TAB (DBCCABSJ, LONG):
36759679
NC		 5086 /* Only DBcc instructions can come here.
5087 Change dbcc into dbcc/jmp.
5088 JF: these used to be fr_opcode[2-7], but that's wrong. */
5089 if (flag_keep_pcrel)
2b878742
NS		 5090 as_bad_where (fragP->fr_file, fragP->fr_line,
5091 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 5092
36759679 5093 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 5094 *buffer_address++ = 0x04;
36759679 5095 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 5096 *buffer_address++ = 0x06;
36759679 5097 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 5098 *buffer_address++ = (char) 0xf9;
5099
36759679 5100 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5101 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5102 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 5103 fragP->fr_fix += 4;
252b5132 5104 break;
151337e8 5105 case TAB (PCREL1632, SHORT):
252b5132
RH		 5106 fragP->fr_opcode[1] &= ~0x3F;
5107 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 5108 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5109 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 5110 fragP->fr_fix += 2;
252b5132 5111 break;
151337e8 5112 case TAB (PCREL1632, LONG):
252b5132
RH		 5113 /* Already set to mode 7.3; this indicates: PC indirect with
5114 suppressed index, 32-bit displacement. */
5115 *buffer_address++ = 0x01;
5116 *buffer_address++ = 0x70;
5117 fragP->fr_fix += 2;
151337e8 5118 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5119 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5120 fixP->fx_pcrel_adjust = 2;
5121 fragP->fr_fix += 4;
252b5132 5122 break;
252b5132 5123 case TAB (PCINDEX, BYTE):
9c2799c2 5124 gas_assert (fragP->fr_fix >= 2);
252b5132 5125 buffer_address[-2] &= ~1;
151337e8 5126 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5127 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5128 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5129 break;
5130 case TAB (PCINDEX, SHORT):
9c2799c2 5131 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5132 buffer_address[-2] |= 0x1;
5133 buffer_address[-1] = 0x20;
5134 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5135 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5136 fixP->fx_pcrel_adjust = 2;
151337e8 5137 fragP->fr_fix += 2;
252b5132
RH		 5138 break;
5139 case TAB (PCINDEX, LONG):
9c2799c2 5140 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5141 buffer_address[-2] |= 0x1;
5142 buffer_address[-1] = 0x30;
151337e8 5143 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5144 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5145 fixP->fx_pcrel_adjust = 2;
5146 fragP->fr_fix += 4;
5147 break;
5148 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5149 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5150 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5151 fragP->fr_fix += 2;
5152 break;
5153 case TAB (ABSTOPCREL, LONG):
36759679 5154 if (flag_keep_pcrel)
025987ea
NS		 5155 as_bad_where (fragP->fr_file, fragP->fr_line,
5156 _("Conversion of PC relative displacement to absolute"));
151337e8 5157 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5158 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5159 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5160 abort ();
5161 fragP->fr_opcode[1] &= ~0x3F;
5162 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5163 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5164 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5165 fragP->fr_fix += 4;
252b5132 5166 break;
252b5132 5167 }
2b878742
NS		 5168 if (fixP)
5169 {
5170 fixP->fx_file = fragP->fr_file;
5171 fixP->fx_line = fragP->fr_line;
5172 }
252b5132
RH		 5173}
5174
252b5132 5175void
31302357
AS		 5176md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5177 segT sec ATTRIBUTE_UNUSED,
5178 fragS *fragP)
252b5132
RH		 5179{
5180 md_convert_frag_1 (fragP);
5181}
252b5132
RH		 5182
5183/* Force truly undefined symbols to their maximum size, and generally set up
5184 the frag list to be relaxed
5185 */
5186int
31302357 5187md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5188{
151337e8 5189 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5190 switch (fragP->fr_subtype)
5191 {
151337e8 5192 case TAB (BRANCHBWL, SZ_UNDEF):
cac27205 5193 case TAB (BRANCHBWPL, SZ_UNDEF):
151337e8 5194 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5195 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5196 {
151337e8
NC		 5197 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5198 && relaxable_symbol (fragP->fr_symbol))
252b5132 5199 {
151337e8
NC		 5200 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5201 }
5202 else if (flag_short_refs)
5203 {
5204 /* Symbol is undefined and we want short ref. */
5205 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5206 }
5207 else
5208 {
151337e8
NC		 5209 /* Symbol is still undefined. Make it LONG. */
5210 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5211 }
5212 break;
151337e8 5213 }
252b5132 5214
151337e8 5215 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5216 {
151337e8
NC		 5217 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5218 && relaxable_symbol (fragP->fr_symbol))
252b5132 5219 {
151337e8 5220 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5221 }
5222 else
5223 {
151337e8
NC		 5224 /* Symbol is undefined and we don't have long branches. */
5225 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5226 }
5227 break;
151337e8 5228 }
252b5132 5229
151337e8 5230 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5231 case TAB (DBCCLBR, SZ_UNDEF):
5232 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5233 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5234 {
8ec6253e
NC		 5235 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5236 && relaxable_symbol (fragP->fr_symbol))
151337e8 5237 || flag_short_refs)
252b5132 5238 {
151337e8 5239 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5240 }
5241 else
5242 {
151337e8 5243 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5244 }
5245 break;
151337e8 5246 }
81d4177b 5247
252b5132
RH		 5248 case TAB (PCINDEX, SZ_UNDEF):
5249 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5250 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5251 {
5252 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5253 }
5254 else
5255 {
5256 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5257 }
5258 break;
5259
151337e8
NC		 5260 case TAB (ABSTOPCREL, SZ_UNDEF):
5261 {
5262 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5263 && relaxable_symbol (fragP->fr_symbol)))
5264 {
5265 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5266 }
5267 else
5268 {
5269 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5270 }
5271 break;
5272 }
5273
252b5132
RH		 5274 default:
5275 break;
5276 }
5277
151337e8 5278 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5279 switch (fragP->fr_subtype)
5280 {
151337e8
NC		 5281 case TAB (BRANCHBWL, BYTE):
5282 case TAB (BRABSJUNC, BYTE):
5283 case TAB (BRABSJCOND, BYTE):
5284 case TAB (BRANCHBW, BYTE):
252b5132 5285 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5286 case we force word mode. If the symbol is at the start of a
5287 frag, and it is the next frag with any data in it (usually
5288 this is just the next frag, but assembler listings may
5289 introduce empty frags), we must use word mode. */
5290 if (fragP->fr_symbol)
252b5132 5291 {
ac62c346 5292 fragS *sym_frag;
252b5132 5293
ac62c346
AM		 5294 sym_frag = symbol_get_frag (fragP->fr_symbol);
5295 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5296 {
ac62c346
AM		 5297 fragS *l;
5298
23b7f870 5299 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5300 if (l->fr_fix != 0)
5301 break;
5302 if (l == sym_frag)
5303 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5304 }
5305 }
5306 break;
5307 default:
5308 break;
5309 }
ac62c346 5310 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5311}
5312
252b5132 5313#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5314int md_short_jump_size = 4;
5315int md_long_jump_size = 6;
252b5132
RH		 5316
5317void
31302357
AS		 5318md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5319 fragS *frag ATTRIBUTE_UNUSED,
5320 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5321{
5322 valueT offset;
5323
5324 offset = to_addr - (from_addr + 2);
5325
5326 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5327 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5328}
5329
5330void
31302357
AS		 5331md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5332 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5333{
5334 valueT offset;
5335
6b6e92f4 5336 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5337 {
36759679 5338 if (flag_keep_pcrel)
6b6e92f4 5339 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5340 offset = to_addr - S_GET_VALUE (to_symbol);
5341 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5342 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5343 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5344 0, NO_RELOC);
5345 }
5346 else
5347 {
5348 offset = to_addr - (from_addr + 2);
5349 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5350 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5351 }
5352}
5353
5354#endif
5355
33eaf5de 5356/* Different values of OK tell what it's OK to return. Things that
252b5132
RH		 5357 aren't OK are an error (what a shock, no?)
5358
5359 0: Everything is OK
3e602632
NC		 5360 10: Absolute 1:8 only
5361 20: Absolute 0:7 only
5362 30: absolute 0:15 only
5363 40: Absolute 0:31 only
5364 50: absolute 0:127 only
252b5132 5365 55: absolute -64:63 only
3e602632 5366 60: absolute -128:127 only
afa2158f 5367 65: absolute 0:511 only
3e602632
NC		 5368 70: absolute 0:4095 only
5369 80: absolute -1, 1:7 only
5370 90: No bignums. */
252b5132
RH		 5371
5372static int
31302357 5373get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5374{
5375 if (exp->exp.X_op == O_absent)
5376 {
36759679 5377 /* Do the same thing the VAX asm does. */
252b5132
RH		 5378 op (exp) = O_constant;
5379 adds (exp) = 0;
5380 subs (exp) = 0;
5381 offs (exp) = 0;
5382 if (ok == 10)
5383 {
5384 as_warn (_("expression out of range: defaulting to 1"));
5385 offs (exp) = 1;
5386 }
5387 }
5388 else if (exp->exp.X_op == O_constant)
5389 {
5390 switch (ok)
5391 {
5392 case 10:
bd17c2c3 5393 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5394 {
5395 as_warn (_("expression out of range: defaulting to 1"));
5396 offs (exp) = 1;
5397 }
5398 break;
5399 case 20:
bd17c2c3 5400 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5401 goto outrange;
5402 break;
5403 case 30:
bd17c2c3 5404 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5405 goto outrange;
5406 break;
5407 case 40:
bd17c2c3 5408 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5409 goto outrange;
5410 break;
5411 case 50:
bd17c2c3 5412 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5413 goto outrange;
5414 break;
5415 case 55:
bd17c2c3 5416 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5417 goto outrange;
5418 break;
5419 case 60:
bd17c2c3 5420 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5421 goto outrange;
afa2158f
NS		 5422 break;
5423 case 65:
5424 if ((valueT) TRUNC (offs (exp)) > 511)
5425 goto outrange;
252b5132
RH		 5426 break;
5427 case 70:
bd17c2c3 5428 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5429 {
5430 outrange:
5431 as_warn (_("expression out of range: defaulting to 0"));
5432 offs (exp) = 0;
5433 }
5434 break;
3e602632 5435 case 80:
bd17c2c3
AM		 5436 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5437 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5438 {
5439 as_warn (_("expression out of range: defaulting to 1"));
5440 offs (exp) = 1;
5441 }
5442 break;
252b5132
RH		 5443 default:
5444 break;
5445 }
5446 }
5447 else if (exp->exp.X_op == O_big)
5448 {
36759679 5449 if (offs (exp) <= 0 /* flonum. */
3e602632 5450 && (ok == 90 /* no bignums */
36759679 5451 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5452 /* If we have a flonum zero, a zero integer should
5453 do as well (e.g., in moveq). */
5454 && generic_floating_point_number.exponent == 0
5455 && generic_floating_point_number.low[0] == 0)))
5456 {
36759679 5457 /* HACK! Turn it into a long. */
252b5132
RH		 5458 LITTLENUM_TYPE words[6];
5459
36759679 5460 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5461 op (exp) = O_constant;
5462 adds (exp) = 0;
5463 subs (exp) = 0;
5464 offs (exp) = words[1] | (words[0] << 16);
5465 }
5466 else if (ok != 0)
5467 {
5468 op (exp) = O_constant;
5469 adds (exp) = 0;
5470 subs (exp) = 0;
5471 offs (exp) = (ok == 10) ? 1 : 0;
5472 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5473 (long) offs (exp));
252b5132
RH		 5474 }
5475 }
5476 else
5477 {
3e602632 5478 if (ok >= 10 && ok <= 80)
252b5132
RH		 5479 {
5480 op (exp) = O_constant;
5481 adds (exp) = 0;
5482 subs (exp) = 0;
5483 offs (exp) = (ok == 10) ? 1 : 0;
5484 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5485 (long) offs (exp));
252b5132
RH		 5486 }
5487 }
5488
5489 if (exp->size != SIZE_UNSPEC)
5490 {
5491 switch (exp->size)
5492 {
5493 case SIZE_UNSPEC:
5494 case SIZE_LONG:
5495 break;
5496 case SIZE_BYTE:
5497 if (!isbyte (offs (exp)))
5498 as_warn (_("expression doesn't fit in BYTE"));
5499 break;
5500 case SIZE_WORD:
5501 if (!isword (offs (exp)))
5502 as_warn (_("expression doesn't fit in WORD"));
5503 break;
5504 }
5505 }
5506
5507 return offs (exp);
5508}
5509
5510/* These are the back-ends for the various machine dependent pseudo-ops. */
5511
5512static void
31302357 5513s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5514{
5515 subseg_set (data_section, 1);
5516 demand_empty_rest_of_line ();
5517}
5518
5519static void
31302357 5520s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5521{
5522 subseg_set (data_section, 2);
5523 demand_empty_rest_of_line ();
5524}
5525
5526static void
31302357 5527s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5528{
5529 /* We don't support putting frags in the BSS segment, we fake it
5530 by marking in_bss, then looking at s_skip for clues. */
5531
5532 subseg_set (bss_section, 0);
5533 demand_empty_rest_of_line ();
5534}
5535
5536static void
31302357 5537s_even (int ignore ATTRIBUTE_UNUSED)
252b5132 5538{
ed9e98c2
AM		 5539 int temp;
5540 long temp_fill;
252b5132
RH		 5541
5542 temp = 1; /* JF should be 2? */
5543 temp_fill = get_absolute_expression ();
92774660 5544 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5545 frag_align (temp, (int) temp_fill, 0);
5546 demand_empty_rest_of_line ();
5547 record_alignment (now_seg, temp);
5548}
5549
5550static void
31302357 5551s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5552{
5553 demand_empty_rest_of_line ();
5554}
5555\f
5556/* Pseudo-ops handled for MRI compatibility. */
5557
5558/* This function returns non-zero if the argument is a conditional
5559 pseudo-op. This is called when checking whether a pending
5560 alignment is needed. */
5561
5562int
32e4c1c2 5563m68k_conditional_pseudoop (const pseudo_typeS *pop)
252b5132
RH		 5564{
5565 return (pop->poc_handler == s_mri_if
5566 || pop->poc_handler == s_mri_else);
5567}
5568
5569/* Handle an MRI style chip specification. */
5570
5571static void
31302357 5572mri_chip (void)
252b5132
RH		 5573{
5574 char *s;
5575 char c;
5576 int i;
5577
5578 s = input_line_pointer;
d02603dc 5579 /* We can't use get_symbol_name since the processor names are not proper
252b5132
RH		 5580 symbols. */
5581 while (is_part_of_name (c = *input_line_pointer++))
5582 ;
5583 *--input_line_pointer = 0;
266abb8f
NS		 5584 for (i = 0; m68k_cpus[i].name; i++)
5585 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5586 break;
266abb8f 5587 if (!m68k_cpus[i].name)
252b5132
RH		 5588 {
5589 as_bad (_("%s: unrecognized processor name"), s);
5590 *input_line_pointer = c;
5591 ignore_rest_of_line ();
5592 return;
5593 }
5594 *input_line_pointer = c;
5595
5596 if (*input_line_pointer == '/')
5597 current_architecture = 0;
5598 else
5599 current_architecture &= m68881 | m68851;
266abb8f 5600 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5601 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5602
5603 while (*input_line_pointer == '/')
5604 {
5605 ++input_line_pointer;
5606 s = input_line_pointer;
d02603dc 5607 /* We can't use get_symbol_name since the processor names are not
252b5132
RH		 5608 proper symbols. */
5609 while (is_part_of_name (c = *input_line_pointer++))
5610 ;
5611 *--input_line_pointer = 0;
5612 if (strcmp (s, "68881") == 0)
5613 current_architecture |= m68881;
5614 else if (strcmp (s, "68851") == 0)
5615 current_architecture |= m68851;
5616 *input_line_pointer = c;
5617 }
252b5132
RH		 5618}
5619
5620/* The MRI CHIP pseudo-op. */
5621
5622static void
31302357 5623s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5624{
5625 char *stop = NULL;
5626 char stopc;
5627
5628 if (flag_mri)
5629 stop = mri_comment_field (&stopc);
5630 mri_chip ();
5631 if (flag_mri)
5632 mri_comment_end (stop, stopc);
5633 demand_empty_rest_of_line ();
5634}
5635
5636/* The MRI FOPT pseudo-op. */
5637
5638static void
31302357 5639s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5640{
5641 SKIP_WHITESPACE ();
5642
5643 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5644 {
5645 int temp;
5646
5647 input_line_pointer += 3;
5648 temp = get_absolute_expression ();
5649 if (temp < 0 || temp > 7)
5650 as_bad (_("bad coprocessor id"));
5651 else
5652 m68k_float_copnum = COP0 + temp;
5653 }
5654 else
5655 {
5656 as_bad (_("unrecognized fopt option"));
5657 ignore_rest_of_line ();
5658 return;
5659 }
5660
5661 demand_empty_rest_of_line ();
5662}
5663
5664/* The structure used to handle the MRI OPT pseudo-op. */
5665
5666struct opt_action
5667{
5668 /* The name of the option. */
5669 const char *name;
5670
5671 /* If this is not NULL, just call this function. The first argument
5672 is the ARG field of this structure, the second argument is
5673 whether the option was negated. */
31302357 5674 void (*pfn) (int arg, int on);
252b5132
RH		 5675
5676 /* If this is not NULL, and the PFN field is NULL, set the variable
5677 this points to. Set it to the ARG field if the option was not
5678 negated, and the NOTARG field otherwise. */
5679 int *pvar;
5680
5681 /* The value to pass to PFN or to assign to *PVAR. */
5682 int arg;
5683
5684 /* The value to assign to *PVAR if the option is negated. If PFN is
5685 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5686 the option may not be negated. */
5687 int notarg;
5688};
5689
5690/* The table used to handle the MRI OPT pseudo-op. */
5691
31302357
AS		 5692static void skip_to_comma (int, int);
5693static void opt_nest (int, int);
5694static void opt_chip (int, int);
5695static void opt_list (int, int);
5696static void opt_list_symbols (int, int);
252b5132
RH		 5697
5698static const struct opt_action opt_table[] =
5699{
5700 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5701
5702 /* We do relaxing, so there is little use for these options. */
5703 { "b", 0, 0, 0, 0 },
5704 { "brs", 0, 0, 0, 0 },
5705 { "brb", 0, 0, 0, 0 },
5706 { "brl", 0, 0, 0, 0 },
5707 { "brw", 0, 0, 0, 0 },
5708
5709 { "c", 0, 0, 0, 0 },
5710 { "cex", 0, 0, 0, 0 },
5711 { "case", 0, &symbols_case_sensitive, 1, 0 },
5712 { "cl", 0, 0, 0, 0 },
5713 { "cre", 0, 0, 0, 0 },
5714 { "d", 0, &flag_keep_locals, 1, 0 },
5715 { "e", 0, 0, 0, 0 },
5716 { "f", 0, &flag_short_refs, 1, 0 },
5717 { "frs", 0, &flag_short_refs, 1, 0 },
5718 { "frl", 0, &flag_short_refs, 0, 1 },
5719 { "g", 0, 0, 0, 0 },
5720 { "i", 0, 0, 0, 0 },
5721 { "m", 0, 0, 0, 0 },
5722 { "mex", 0, 0, 0, 0 },
5723 { "mc", 0, 0, 0, 0 },
5724 { "md", 0, 0, 0, 0 },
5725 { "nest", opt_nest, 0, 0, 0 },
5726 { "next", skip_to_comma, 0, 0, 0 },
5727 { "o", 0, 0, 0, 0 },
5728 { "old", 0, 0, 0, 0 },
5729 { "op", skip_to_comma, 0, 0, 0 },
5730 { "pco", 0, 0, 0, 0 },
5731 { "p", opt_chip, 0, 0, 0 },
5732 { "pcr", 0, 0, 0, 0 },
5733 { "pcs", 0, 0, 0, 0 },
5734 { "r", 0, 0, 0, 0 },
5735 { "quick", 0, &m68k_quick, 1, 0 },
5736 { "rel32", 0, &m68k_rel32, 1, 0 },
5737 { "s", opt_list, 0, 0, 0 },
5738 { "t", opt_list_symbols, 0, 0, 0 },
5739 { "w", 0, &flag_no_warnings, 0, 1 },
5740 { "x", 0, 0, 0, 0 }
5741};
5742
8fce3f5e 5743#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5744
5745/* The MRI OPT pseudo-op. */
5746
5747static void
31302357 5748s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5749{
5750 do
5751 {
5752 int t;
5753 char *s;
5754 char c;
5755 int i;
5756 const struct opt_action *o;
5757
5758 SKIP_WHITESPACE ();
5759
5760 t = 1;
5761 if (*input_line_pointer == '-')
5762 {
5763 ++input_line_pointer;
5764 t = 0;
5765 }
5766 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5767 {
5768 input_line_pointer += 2;
5769 t = 0;
5770 }
5771
d02603dc 5772 c = get_symbol_name (&s);
252b5132
RH		 5773
5774 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5775 {
5776 if (strcasecmp (s, o->name) == 0)
5777 {
5778 if (o->pfn)
5779 {
5780 /* Restore input_line_pointer now in case the option
5781 takes arguments. */
d02603dc 5782 (void) restore_line_pointer (c);
252b5132
RH		 5783 (*o->pfn) (o->arg, t);
5784 }
5785 else if (o->pvar != NULL)
5786 {
5787 if (! t && o->arg == o->notarg)
5788 as_bad (_("option `%s' may not be negated"), s);
d02603dc 5789 restore_line_pointer (c);
252b5132
RH		 5790 *o->pvar = t ? o->arg : o->notarg;
5791 }
5792 else
5793 *input_line_pointer = c;
5794 break;
5795 }
5796 }
5797 if (i >= OPTCOUNT)
5798 {
5799 as_bad (_("option `%s' not recognized"), s);
d02603dc 5800 restore_line_pointer (c);
252b5132
RH		 5801 }
5802 }
5803 while (*input_line_pointer++ == ',');
5804
5805 /* Move back to terminating character. */
5806 --input_line_pointer;
5807 demand_empty_rest_of_line ();
5808}
5809
5810/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5811 not support and which take arguments. */
252b5132
RH		 5812
5813static void
31302357 5814skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5815{
5816 while (*input_line_pointer != ','
5817 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5818 ++input_line_pointer;
5819}
5820
5821/* Handle the OPT NEST=depth option. */
5822
5823static void
31302357 5824opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5825{
5826 if (*input_line_pointer != '=')
5827 {
5828 as_bad (_("bad format of OPT NEST=depth"));
5829 return;
5830 }
5831
5832 ++input_line_pointer;
5833 max_macro_nest = get_absolute_expression ();
5834}
5835
5836/* Handle the OPT P=chip option. */
5837
5838static void
31302357 5839opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5840{
5841 if (*input_line_pointer != '=')
5842 {
5843 /* This is just OPT P, which we do not support. */
5844 return;
5845 }
5846
5847 ++input_line_pointer;
5848 mri_chip ();
5849}
5850
5851/* Handle the OPT S option. */
5852
5853static void
31302357 5854opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5855{
5856 listing_list (on);
5857}
5858
5859/* Handle the OPT T option. */
5860
5861static void
31302357 5862opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5863{
5864 if (on)
5865 listing |= LISTING_SYMBOLS;
5866 else
8a104df9 5867 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5868}
5869
5870/* Handle the MRI REG pseudo-op. */
5871
5872static void
31302357 5873s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5874{
5875 char *s;
5876 int c;
5877 struct m68k_op rop;
5878 int mask;
5879 char *stop = NULL;
5880 char stopc;
5881
5882 if (line_label == NULL)
5883 {
5884 as_bad (_("missing label"));
5885 ignore_rest_of_line ();
5886 return;
5887 }
5888
5889 if (flag_mri)
5890 stop = mri_comment_field (&stopc);
5891
5892 SKIP_WHITESPACE ();
5893
5894 s = input_line_pointer;
3882b010 5895 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5896#ifdef REGISTER_PREFIX
5897 || *input_line_pointer == REGISTER_PREFIX
5898#endif
5899 || *input_line_pointer == '/'
5900 || *input_line_pointer == '-')
5901 ++input_line_pointer;
5902 c = *input_line_pointer;
5903 *input_line_pointer = '\0';
5904
5905 if (m68k_ip_op (s, &rop) != 0)
5906 {
5907 if (rop.error == NULL)
5908 as_bad (_("bad register list"));
5909 else
5910 as_bad (_("bad register list: %s"), rop.error);
5911 *input_line_pointer = c;
5912 ignore_rest_of_line ();
5913 return;
5914 }
5915
5916 *input_line_pointer = c;
5917
5918 if (rop.mode == REGLST)
5919 mask = rop.mask;
5920 else if (rop.mode == DREG)
5921 mask = 1 << (rop.reg - DATA0);
5922 else if (rop.mode == AREG)
5923 mask = 1 << (rop.reg - ADDR0 + 8);
5924 else if (rop.mode == FPREG)
5925 mask = 1 << (rop.reg - FP0 + 16);
5926 else if (rop.mode == CONTROL
5927 && rop.reg == FPI)
5928 mask = 1 << 24;
5929 else if (rop.mode == CONTROL
5930 && rop.reg == FPS)
5931 mask = 1 << 25;
5932 else if (rop.mode == CONTROL
5933 && rop.reg == FPC)
5934 mask = 1 << 26;
5935 else
5936 {
5937 as_bad (_("bad register list"));
5938 ignore_rest_of_line ();
5939 return;
5940 }
5941
5942 S_SET_SEGMENT (line_label, reg_section);
5943 S_SET_VALUE (line_label, ~mask);
49309057 5944 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5945
5946 if (flag_mri)
5947 mri_comment_end (stop, stopc);
5948
5949 demand_empty_rest_of_line ();
5950}
5951
5952/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5953
5954struct save_opts
5955{
5956 struct save_opts *next;
5957 int abspcadd;
5958 int symbols_case_sensitive;
5959 int keep_locals;
5960 int short_refs;
5961 int architecture;
2da12c60 5962 const enum m68k_register *control_regs;
252b5132
RH		 5963 int quick;
5964 int rel32;
5965 int listing;
5966 int no_warnings;
5967 /* FIXME: We don't save OPT S. */
5968};
5969
5970/* This variable holds the stack of saved options. */
5971
5972static struct save_opts *save_stack;
5973
5974/* The MRI SAVE pseudo-op. */
5975
5976static void
31302357 5977s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5978{
5979 struct save_opts *s;
5980
add39d23 5981 s = XNEW (struct save_opts);
252b5132
RH		 5982 s->abspcadd = m68k_abspcadd;
5983 s->symbols_case_sensitive = symbols_case_sensitive;
5984 s->keep_locals = flag_keep_locals;
5985 s->short_refs = flag_short_refs;
5986 s->architecture = current_architecture;
2da12c60 5987 s->control_regs = control_regs;
252b5132
RH		 5988 s->quick = m68k_quick;
5989 s->rel32 = m68k_rel32;
5990 s->listing = listing;
5991 s->no_warnings = flag_no_warnings;
5992
5993 s->next = save_stack;
5994 save_stack = s;
5995
5996 demand_empty_rest_of_line ();
5997}
5998
5999/* The MRI RESTORE pseudo-op. */
6000
6001static void
31302357 6002s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6003{
6004 struct save_opts *s;
6005
6006 if (save_stack == NULL)
6007 {
6008 as_bad (_("restore without save"));
6009 ignore_rest_of_line ();
6010 return;
6011 }
6012
6013 s = save_stack;
6014 save_stack = s->next;
6015
6016 m68k_abspcadd = s->abspcadd;
6017 symbols_case_sensitive = s->symbols_case_sensitive;
6018 flag_keep_locals = s->keep_locals;
6019 flag_short_refs = s->short_refs;
6020 current_architecture = s->architecture;
2da12c60 6021 control_regs = s->control_regs;
252b5132
RH		 6022 m68k_quick = s->quick;
6023 m68k_rel32 = s->rel32;
6024 listing = s->listing;
6025 flag_no_warnings = s->no_warnings;
6026
6027 free (s);
6028
6029 demand_empty_rest_of_line ();
6030}
6031
6032/* Types of MRI structured control directives. */
6033
6034enum mri_control_type
6035{
6036 mri_for,
6037 mri_if,
6038 mri_repeat,
6039 mri_while
6040};
6041
6042/* This structure is used to stack the MRI structured control
6043 directives. */
6044
6045struct mri_control_info
6046{
6047 /* The directive within which this one is enclosed. */
6048 struct mri_control_info *outer;
6049
6050 /* The type of directive. */
6051 enum mri_control_type type;
6052
6053 /* Whether an ELSE has been in an IF. */
6054 int else_seen;
6055
6056 /* The add or sub statement at the end of a FOR. */
6057 char *incr;
6058
6059 /* The label of the top of a FOR or REPEAT loop. */
6060 char *top;
6061
6062 /* The label to jump to for the next iteration, or the else
6063 expression of a conditional. */
6064 char *next;
6065
6066 /* The label to jump to to break out of the loop, or the label past
6067 the end of a conditional. */
6068 char *bottom;
6069};
6070
6071/* The stack of MRI structured control directives. */
6072
6073static struct mri_control_info *mri_control_stack;
6074
6075/* The current MRI structured control directive index number, used to
6076 generate label names. */
6077
6078static int mri_control_index;
6079
252b5132
RH		 6080/* Assemble an instruction for an MRI structured control directive. */
6081
6082static void
31302357 6083mri_assemble (char *str)
252b5132
RH		 6084{
6085 char *s;
6086
6087 /* md_assemble expects the opcode to be in lower case. */
6088 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6089 *s = TOLOWER (*s);
252b5132
RH		 6090
6091 md_assemble (str);
6092}
6093
6094/* Generate a new MRI label structured control directive label name. */
6095
6096static char *
31302357 6097mri_control_label (void)
252b5132
RH		 6098{
6099 char *n;
6100
add39d23 6101 n = XNEWVEC (char, 20);
252b5132
RH		 6102 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6103 ++mri_control_index;
6104 return n;
6105}
6106
6107/* Create a new MRI structured control directive. */
6108
6109static struct mri_control_info *
31302357 6110push_mri_control (enum mri_control_type type)
252b5132
RH		 6111{
6112 struct mri_control_info *n;
6113
add39d23 6114 n = XNEW (struct mri_control_info);
252b5132
RH		 6115
6116 n->type = type;
6117 n->else_seen = 0;
6118 if (type == mri_if || type == mri_while)
6119 n->top = NULL;
6120 else
6121 n->top = mri_control_label ();
6122 n->next = mri_control_label ();
6123 n->bottom = mri_control_label ();
6124
6125 n->outer = mri_control_stack;
6126 mri_control_stack = n;
6127
6128 return n;
6129}
6130
6131/* Pop off the stack of MRI structured control directives. */
6132
6133static void
31302357 6134pop_mri_control (void)
252b5132
RH		 6135{
6136 struct mri_control_info *n;
6137
6138 n = mri_control_stack;
6139 mri_control_stack = n->outer;
9fbb53c7 6140 free (n->top);
252b5132
RH		 6141 free (n->next);
6142 free (n->bottom);
6143 free (n);
6144}
6145
6146/* Recognize a condition code in an MRI structured control expression. */
6147
6148static int
31302357 6149parse_mri_condition (int *pcc)
252b5132
RH		 6150{
6151 char c1, c2;
6152
6153 know (*input_line_pointer == '<');
6154
6155 ++input_line_pointer;
6156 c1 = *input_line_pointer++;
6157 c2 = *input_line_pointer++;
6158
6159 if (*input_line_pointer != '>')
6160 {
6161 as_bad (_("syntax error in structured control directive"));
6162 return 0;
6163 }
6164
6165 ++input_line_pointer;
6166 SKIP_WHITESPACE ();
6167
3882b010
L		 6168 c1 = TOLOWER (c1);
6169 c2 = TOLOWER (c2);
252b5132
RH		 6170
6171 *pcc = (c1 << 8) | c2;
6172
6173 return 1;
6174}
6175
6176/* Parse a single operand in an MRI structured control expression. */
6177
6178static int
31302357
AS		 6179parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6180 char **rightstart, char **rightstop)
252b5132
RH		 6181{
6182 char *s;
6183
6184 SKIP_WHITESPACE ();
6185
6186 *pcc = -1;
6187 *leftstart = NULL;
6188 *leftstop = NULL;
6189 *rightstart = NULL;
6190 *rightstop = NULL;
6191
6192 if (*input_line_pointer == '<')
6193 {
6194 /* It's just a condition code. */
6195 return parse_mri_condition (pcc);
6196 }
6197
6198 /* Look ahead for the condition code. */
6199 for (s = input_line_pointer; *s != '\0'; ++s)
6200 {
6201 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6202 break;
6203 }
6204 if (*s == '\0')
6205 {
6206 as_bad (_("missing condition code in structured control directive"));
6207 return 0;
6208 }
6209
6210 *leftstart = input_line_pointer;
6211 *leftstop = s;
6212 if (*leftstop > *leftstart
6213 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6214 --*leftstop;
6215
6216 input_line_pointer = s;
6217 if (! parse_mri_condition (pcc))
6218 return 0;
6219
6220 /* Look ahead for AND or OR or end of line. */
6221 for (s = input_line_pointer; *s != '\0'; ++s)
6222 {
e1f44d10
NC		 6223 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6224 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6225 ^^^ ^^ */
8a104df9
KH		 6226 if ((s == input_line_pointer
6227 || *(s-1) == ' '
6228 || *(s-1) == '\t')
6229 && ((strncasecmp (s, "AND", 3) == 0
6230 && (s[3] == '.' || ! is_part_of_name (s[3])))
6231 || (strncasecmp (s, "OR", 2) == 0
6232 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6233 break;
252b5132
RH		 6234 }
6235
6236 *rightstart = input_line_pointer;
6237 *rightstop = s;
6238 if (*rightstop > *rightstart
6239 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6240 --*rightstop;
6241
6242 input_line_pointer = s;
6243
6244 return 1;
6245}
6246
6247#define MCC(b1, b2) (((b1) << 8) | (b2))
6248
6249/* Swap the sense of a condition. This changes the condition so that
6250 it generates the same result when the operands are swapped. */
6251
6252static int
31302357 6253swap_mri_condition (int cc)
252b5132
RH		 6254{
6255 switch (cc)
6256 {
6257 case MCC ('h', 'i'): return MCC ('c', 's');
6258 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6259 /* <HS> is an alias for <CC>. */
e1f44d10 6260 case MCC ('h', 's'):
252b5132 6261 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6262 /* <LO> is an alias for <CS>. */
e1f44d10 6263 case MCC ('l', 'o'):
252b5132
RH		 6264 case MCC ('c', 's'): return MCC ('h', 'i');
6265 case MCC ('p', 'l'): return MCC ('m', 'i');
6266 case MCC ('m', 'i'): return MCC ('p', 'l');
6267 case MCC ('g', 'e'): return MCC ('l', 'e');
6268 case MCC ('l', 't'): return MCC ('g', 't');
6269 case MCC ('g', 't'): return MCC ('l', 't');
6270 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6271 /* Issue a warning for conditions we can not swap. */
8fc4ee9b
AM		 6272 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6273 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
e1f44d10
NC		 6274 case MCC ('v', 'c'):
6275 case MCC ('v', 's'):
6276 default :
6277 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6278 (char) (cc >> 8), (char) (cc));
6279 break;
252b5132
RH		 6280 }
6281 return cc;
6282}
6283
6284/* Reverse the sense of a condition. */
6285
6286static int
31302357 6287reverse_mri_condition (int cc)
252b5132
RH		 6288{
6289 switch (cc)
6290 {
6291 case MCC ('h', 'i'): return MCC ('l', 's');
6292 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6293 /* <HS> is an alias for <CC> */
6294 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6295 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6296 /* <LO> is an alias for <CS> */
6297 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6298 case MCC ('c', 's'): return MCC ('c', 'c');
6299 case MCC ('n', 'e'): return MCC ('e', 'q');
6300 case MCC ('e', 'q'): return MCC ('n', 'e');
6301 case MCC ('v', 'c'): return MCC ('v', 's');
6302 case MCC ('v', 's'): return MCC ('v', 'c');
6303 case MCC ('p', 'l'): return MCC ('m', 'i');
6304 case MCC ('m', 'i'): return MCC ('p', 'l');
6305 case MCC ('g', 'e'): return MCC ('l', 't');
6306 case MCC ('l', 't'): return MCC ('g', 'e');
6307 case MCC ('g', 't'): return MCC ('l', 'e');
6308 case MCC ('l', 'e'): return MCC ('g', 't');
6309 }
6310 return cc;
6311}
6312
6313/* Build an MRI structured control expression. This generates test
6314 and branch instructions. It goes to TRUELAB if the condition is
6315 true, and to FALSELAB if the condition is false. Exactly one of
6316 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6317 is the size qualifier for the expression. EXTENT is the size to
6318 use for the branch. */
6319
6320static void
31302357
AS		 6321build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6322 char *rightstart, char *rightstop,
6323 const char *truelab, const char *falselab,
6324 int extent)
252b5132
RH		 6325{
6326 char *buf;
6327 char *s;
6328
6329 if (leftstart != NULL)
6330 {
6331 struct m68k_op leftop, rightop;
6332 char c;
6333
6334 /* Swap the compare operands, if necessary, to produce a legal
6335 m68k compare instruction. Comparing a register operand with
6336 a non-register operand requires the register to be on the
6337 right (cmp, cmpa). Comparing an immediate value with
6338 anything requires the immediate value to be on the left
6339 (cmpi). */
6340
6341 c = *leftstop;
6342 *leftstop = '\0';
6343 (void) m68k_ip_op (leftstart, &leftop);
6344 *leftstop = c;
6345
6346 c = *rightstop;
6347 *rightstop = '\0';
6348 (void) m68k_ip_op (rightstart, &rightop);
6349 *rightstop = c;
6350
6351 if (rightop.mode == IMMED
6352 || ((leftop.mode == DREG || leftop.mode == AREG)
6353 && (rightop.mode != DREG && rightop.mode != AREG)))
6354 {
6355 char *temp;
6356
31302357
AS		 6357 /* Correct conditional handling:
6358 if #1 <lt> d0 then ;means if (1 < d0)
6359 ...
6360 endi
e1f44d10 6361
31302357 6362 should assemble to:
e1f44d10 6363
31302357
AS		 6364 cmp #1,d0 if we do *not* swap the operands
6365 bgt true we need the swapped condition!
6366 ble false
6367 true:
6368 ...
6369 false:
6370 */
252b5132
RH		 6371 temp = leftstart;
6372 leftstart = rightstart;
6373 rightstart = temp;
6374 temp = leftstop;
6375 leftstop = rightstop;
6376 rightstop = temp;
8a104df9
KH		 6377 }
6378 else
6379 {
e1f44d10 6380 cc = swap_mri_condition (cc);
252b5132
RH		 6381 }
6382 }
6383
6384 if (truelab == NULL)
6385 {
6386 cc = reverse_mri_condition (cc);
6387 truelab = falselab;
6388 }
92774660 6389
252b5132
RH		 6390 if (leftstart != NULL)
6391 {
add39d23
TS		 6392 buf = XNEWVEC (char, (20
6393 + (leftstop - leftstart)
6394 + (rightstop - rightstart)));
252b5132
RH		 6395 s = buf;
6396 *s++ = 'c';
6397 *s++ = 'm';
6398 *s++ = 'p';
6399 if (qual != '\0')
3882b010 6400 *s++ = TOLOWER (qual);
252b5132
RH		 6401 *s++ = ' ';
6402 memcpy (s, leftstart, leftstop - leftstart);
6403 s += leftstop - leftstart;
6404 *s++ = ',';
6405 memcpy (s, rightstart, rightstop - rightstart);
6406 s += rightstop - rightstart;
6407 *s = '\0';
6408 mri_assemble (buf);
6409 free (buf);
6410 }
92774660 6411
add39d23 6412 buf = XNEWVEC (char, 20 + strlen (truelab));
252b5132
RH		 6413 s = buf;
6414 *s++ = 'b';
6415 *s++ = cc >> 8;
6416 *s++ = cc & 0xff;
6417 if (extent != '\0')
3882b010 6418 *s++ = TOLOWER (extent);
252b5132
RH		 6419 *s++ = ' ';
6420 strcpy (s, truelab);
6421 mri_assemble (buf);
6422 free (buf);
6423}
6424
6425/* Parse an MRI structured control expression. This generates test
6426 and branch instructions. STOP is where the expression ends. It
6427 goes to TRUELAB if the condition is true, and to FALSELAB if the
6428 condition is false. Exactly one of TRUELAB and FALSELAB will be
6429 NULL, meaning to fall through. QUAL is the size qualifier for the
6430 expression. EXTENT is the size to use for the branch. */
6431
6432static void
31302357
AS		 6433parse_mri_control_expression (char *stop, int qual, const char *truelab,
6434 const char *falselab, int extent)
252b5132
RH		 6435{
6436 int c;
6437 int cc;
6438 char *leftstart;
6439 char *leftstop;
6440 char *rightstart;
6441 char *rightstop;
6442
6443 c = *stop;
6444 *stop = '\0';
6445
6446 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6447 &rightstart, &rightstop))
6448 {
6449 *stop = c;
6450 return;
6451 }
6452
6453 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6454 {
6455 const char *flab;
6456
6457 if (falselab != NULL)
6458 flab = falselab;
6459 else
6460 flab = mri_control_label ();
6461
6462 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6463 rightstop, (const char *) NULL, flab, extent);
6464
6465 input_line_pointer += 3;
6466 if (*input_line_pointer != '.'
6467 || input_line_pointer[1] == '\0')
6468 qual = '\0';
6469 else
6470 {
6471 qual = input_line_pointer[1];
6472 input_line_pointer += 2;
6473 }
6474
6475 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6476 &rightstart, &rightstop))
6477 {
6478 *stop = c;
6479 return;
6480 }
6481
6482 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6483 rightstop, truelab, falselab, extent);
6484
6485 if (falselab == NULL)
6486 colon (flab);
6487 }
6488 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6489 {
6490 const char *tlab;
6491
6492 if (truelab != NULL)
6493 tlab = truelab;
6494 else
6495 tlab = mri_control_label ();
6496
6497 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6498 rightstop, tlab, (const char *) NULL, extent);
6499
6500 input_line_pointer += 2;
6501 if (*input_line_pointer != '.'
6502 || input_line_pointer[1] == '\0')
6503 qual = '\0';
6504 else
6505 {
6506 qual = input_line_pointer[1];
6507 input_line_pointer += 2;
6508 }
6509
6510 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6511 &rightstart, &rightstop))
6512 {
6513 *stop = c;
6514 return;
6515 }
6516
6517 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6518 rightstop, truelab, falselab, extent);
6519
6520 if (truelab == NULL)
6521 colon (tlab);
6522 }
6523 else
6524 {
6525 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6526 rightstop, truelab, falselab, extent);
6527 }
6528
6529 *stop = c;
6530 if (input_line_pointer != stop)
6531 as_bad (_("syntax error in structured control directive"));
6532}
6533
6534/* Handle the MRI IF pseudo-op. This may be a structured control
6535 directive, or it may be a regular assembler conditional, depending
6536 on its operands. */
6537
6538static void
31302357 6539s_mri_if (int qual)
252b5132
RH		 6540{
6541 char *s;
6542 int c;
6543 struct mri_control_info *n;
6544
6545 /* A structured control directive must end with THEN with an
6546 optional qualifier. */
6547 s = input_line_pointer;
e1f44d10
NC		 6548 /* We only accept '*' as introduction of comments if preceded by white space
6549 or at first column of a line (I think this can't actually happen here?)
6550 This is important when assembling:
6551 if d0 <ne> 12(a0,d0*2) then
36759679 6552 if d0 <ne> #CONST*20 then. */
31302357
AS		 6553 while (! (is_end_of_line[(unsigned char) *s]
6554 || (flag_mri
6555 && *s == '*'
6556 && (s == input_line_pointer
6557 || *(s-1) == ' '
6558 || *(s-1) == '\t'))))
252b5132
RH		 6559 ++s;
6560 --s;
6561 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6562 --s;
6563
6564 if (s - input_line_pointer > 1
6565 && s[-1] == '.')
6566 s -= 2;
6567
6568 if (s - input_line_pointer < 3
6569 || strncasecmp (s - 3, "THEN", 4) != 0)
6570 {
6571 if (qual != '\0')
6572 {
6573 as_bad (_("missing then"));
6574 ignore_rest_of_line ();
6575 return;
6576 }
6577
6578 /* It's a conditional. */
6579 s_if (O_ne);
6580 return;
6581 }
6582
6583 /* Since this might be a conditional if, this pseudo-op will be
6584 called even if we are supported to be ignoring input. Double
6585 check now. Clobber *input_line_pointer so that ignore_input
6586 thinks that this is not a special pseudo-op. */
6587 c = *input_line_pointer;
6588 *input_line_pointer = 0;
6589 if (ignore_input ())
6590 {
6591 *input_line_pointer = c;
6592 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6593 ++input_line_pointer;
6594 demand_empty_rest_of_line ();
6595 return;
6596 }
6597 *input_line_pointer = c;
6598
6599 n = push_mri_control (mri_if);
6600
6601 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6602 n->next, s[1] == '.' ? s[2] : '\0');
6603
6604 if (s[1] == '.')
6605 input_line_pointer = s + 3;
6606 else
6607 input_line_pointer = s + 1;
6608
6609 if (flag_mri)
6610 {
6611 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6612 ++input_line_pointer;
6613 }
6614
6615 demand_empty_rest_of_line ();
6616}
6617
6618/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6619 structured IF, associate the ELSE with the IF. Otherwise, assume
6620 it is a conditional else. */
6621
6622static void
31302357 6623s_mri_else (int qual)
252b5132
RH		 6624{
6625 int c;
6626 char *buf;
6627 char q[2];
6628
6629 if (qual == '\0'
6630 && (mri_control_stack == NULL
6631 || mri_control_stack->type != mri_if
6632 || mri_control_stack->else_seen))
6633 {
6634 s_else (0);
6635 return;
6636 }
6637
6638 c = *input_line_pointer;
6639 *input_line_pointer = 0;
6640 if (ignore_input ())
6641 {
6642 *input_line_pointer = c;
6643 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6644 ++input_line_pointer;
6645 demand_empty_rest_of_line ();
6646 return;
6647 }
6648 *input_line_pointer = c;
6649
6650 if (mri_control_stack == NULL
6651 || mri_control_stack->type != mri_if
6652 || mri_control_stack->else_seen)
6653 {
6654 as_bad (_("else without matching if"));
6655 ignore_rest_of_line ();
6656 return;
6657 }
6658
6659 mri_control_stack->else_seen = 1;
6660
add39d23 6661 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom));
3882b010 6662 q[0] = TOLOWER (qual);
252b5132
RH		 6663 q[1] = '\0';
6664 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6665 mri_assemble (buf);
6666 free (buf);
6667
6668 colon (mri_control_stack->next);
6669
6670 if (flag_mri)
6671 {
6672 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6673 ++input_line_pointer;
6674 }
6675
6676 demand_empty_rest_of_line ();
6677}
6678
6679/* Handle the MRI ENDI pseudo-op. */
6680
6681static void
31302357 6682s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6683{
6684 if (mri_control_stack == NULL
6685 || mri_control_stack->type != mri_if)
6686 {
6687 as_bad (_("endi without matching if"));
6688 ignore_rest_of_line ();
6689 return;
6690 }
6691
6692 /* ignore_input will not return true for ENDI, so we don't need to
6693 worry about checking it again here. */
6694
6695 if (! mri_control_stack->else_seen)
6696 colon (mri_control_stack->next);
6697 colon (mri_control_stack->bottom);
6698
6699 pop_mri_control ();
6700
6701 if (flag_mri)
6702 {
6703 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6704 ++input_line_pointer;
6705 }
6706
6707 demand_empty_rest_of_line ();
6708}
6709
6710/* Handle the MRI BREAK pseudo-op. */
6711
6712static void
31302357 6713s_mri_break (int extent)
252b5132
RH		 6714{
6715 struct mri_control_info *n;
6716 char *buf;
6717 char ex[2];
6718
6719 n = mri_control_stack;
6720 while (n != NULL
6721 && n->type != mri_for
6722 && n->type != mri_repeat
6723 && n->type != mri_while)
6724 n = n->outer;
6725 if (n == NULL)
6726 {
6727 as_bad (_("break outside of structured loop"));
6728 ignore_rest_of_line ();
6729 return;
6730 }
6731
add39d23 6732 buf = XNEWVEC (char, 20 + strlen (n->bottom));
3882b010 6733 ex[0] = TOLOWER (extent);
252b5132
RH		 6734 ex[1] = '\0';
6735 sprintf (buf, "bra%s %s", ex, n->bottom);
6736 mri_assemble (buf);
6737 free (buf);
6738
6739 if (flag_mri)
6740 {
6741 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6742 ++input_line_pointer;
6743 }
6744
6745 demand_empty_rest_of_line ();
6746}
6747
6748/* Handle the MRI NEXT pseudo-op. */
6749
6750static void
31302357 6751s_mri_next (int extent)
252b5132
RH		 6752{
6753 struct mri_control_info *n;
6754 char *buf;
6755 char ex[2];
6756
6757 n = mri_control_stack;
6758 while (n != NULL
6759 && n->type != mri_for
6760 && n->type != mri_repeat
6761 && n->type != mri_while)
6762 n = n->outer;
6763 if (n == NULL)
6764 {
6765 as_bad (_("next outside of structured loop"));
6766 ignore_rest_of_line ();
6767 return;
6768 }
6769
add39d23 6770 buf = XNEWVEC (char, 20 + strlen (n->next));
3882b010 6771 ex[0] = TOLOWER (extent);
252b5132
RH		 6772 ex[1] = '\0';
6773 sprintf (buf, "bra%s %s", ex, n->next);
6774 mri_assemble (buf);
6775 free (buf);
6776
6777 if (flag_mri)
6778 {
6779 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6780 ++input_line_pointer;
6781 }
6782
6783 demand_empty_rest_of_line ();
6784}
6785
6786/* Handle the MRI FOR pseudo-op. */
6787
6788static void
31302357 6789s_mri_for (int qual)
252b5132
RH		 6790{
6791 const char *varstart, *varstop;
6792 const char *initstart, *initstop;
6793 const char *endstart, *endstop;
6794 const char *bystart, *bystop;
6795 int up;
6796 int by;
6797 int extent;
6798 struct mri_control_info *n;
6799 char *buf;
6800 char *s;
6801 char ex[2];
6802
6803 /* The syntax is
6804 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6805 */
6806
6807 SKIP_WHITESPACE ();
6808 varstart = input_line_pointer;
6809
6810 /* Look for the '='. */
6811 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6812 && *input_line_pointer != '=')
6813 ++input_line_pointer;
6814 if (*input_line_pointer != '=')
6815 {
6816 as_bad (_("missing ="));
6817 ignore_rest_of_line ();
6818 return;
6819 }
6820
6821 varstop = input_line_pointer;
6822 if (varstop > varstart
6823 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6824 --varstop;
6825
6826 ++input_line_pointer;
6827
6828 initstart = input_line_pointer;
6829
6830 /* Look for TO or DOWNTO. */
6831 up = 1;
6832 initstop = NULL;
6833 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6834 {
6835 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6836 && ! is_part_of_name (input_line_pointer[2]))
6837 {
6838 initstop = input_line_pointer;
6839 input_line_pointer += 2;
6840 break;
6841 }
6842 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6843 && ! is_part_of_name (input_line_pointer[6]))
6844 {
6845 initstop = input_line_pointer;
6846 up = 0;
6847 input_line_pointer += 6;
6848 break;
6849 }
6850 ++input_line_pointer;
6851 }
6852 if (initstop == NULL)
6853 {
6854 as_bad (_("missing to or downto"));
6855 ignore_rest_of_line ();
6856 return;
6857 }
6858 if (initstop > initstart
6859 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6860 --initstop;
6861
6862 SKIP_WHITESPACE ();
6863 endstart = input_line_pointer;
6864
6865 /* Look for BY or DO. */
6866 by = 0;
6867 endstop = NULL;
6868 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6869 {
6870 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6871 && ! is_part_of_name (input_line_pointer[2]))
6872 {
6873 endstop = input_line_pointer;
6874 by = 1;
6875 input_line_pointer += 2;
6876 break;
6877 }
6878 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6879 && (input_line_pointer[2] == '.'
6880 || ! is_part_of_name (input_line_pointer[2])))
6881 {
6882 endstop = input_line_pointer;
6883 input_line_pointer += 2;
6884 break;
6885 }
6886 ++input_line_pointer;
6887 }
6888 if (endstop == NULL)
6889 {
6890 as_bad (_("missing do"));
6891 ignore_rest_of_line ();
6892 return;
6893 }
6894 if (endstop > endstart
6895 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6896 --endstop;
6897
6898 if (! by)
6899 {
6900 bystart = "#1";
6901 bystop = bystart + 2;
6902 }
6903 else
6904 {
6905 SKIP_WHITESPACE ();
6906 bystart = input_line_pointer;
6907
6908 /* Look for DO. */
6909 bystop = NULL;
6910 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6911 {
6912 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6913 && (input_line_pointer[2] == '.'
6914 || ! is_part_of_name (input_line_pointer[2])))
6915 {
6916 bystop = input_line_pointer;
6917 input_line_pointer += 2;
6918 break;
6919 }
6920 ++input_line_pointer;
6921 }
6922 if (bystop == NULL)
6923 {
6924 as_bad (_("missing do"));
6925 ignore_rest_of_line ();
6926 return;
6927 }
6928 if (bystop > bystart
6929 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6930 --bystop;
6931 }
6932
6933 if (*input_line_pointer != '.')
6934 extent = '\0';
6935 else
6936 {
6937 extent = input_line_pointer[1];
6938 input_line_pointer += 2;
6939 }
6940
6941 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6942 n = push_mri_control (mri_for);
6943
add39d23 6944 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart));
252b5132 6945
36759679 6946 /* Move init,var. */
252b5132
RH		 6947 s = buf;
6948 *s++ = 'm';
6949 *s++ = 'o';
6950 *s++ = 'v';
6951 *s++ = 'e';
6952 if (qual != '\0')
3882b010 6953 *s++ = TOLOWER (qual);
252b5132
RH		 6954 *s++ = ' ';
6955 memcpy (s, initstart, initstop - initstart);
6956 s += initstop - initstart;
6957 *s++ = ',';
6958 memcpy (s, varstart, varstop - varstart);
6959 s += varstop - varstart;
6960 *s = '\0';
6961 mri_assemble (buf);
6962
6963 colon (n->top);
6964
36759679 6965 /* cmp end,var. */
252b5132
RH		 6966 s = buf;
6967 *s++ = 'c';
6968 *s++ = 'm';
6969 *s++ = 'p';
6970 if (qual != '\0')
3882b010 6971 *s++ = TOLOWER (qual);
252b5132
RH		 6972 *s++ = ' ';
6973 memcpy (s, endstart, endstop - endstart);
6974 s += endstop - endstart;
6975 *s++ = ',';
6976 memcpy (s, varstart, varstop - varstart);
6977 s += varstop - varstart;
6978 *s = '\0';
6979 mri_assemble (buf);
6980
36759679 6981 /* bcc bottom. */
3882b010 6982 ex[0] = TOLOWER (extent);
252b5132
RH		 6983 ex[1] = '\0';
6984 if (up)
6985 sprintf (buf, "blt%s %s", ex, n->bottom);
6986 else
6987 sprintf (buf, "bgt%s %s", ex, n->bottom);
6988 mri_assemble (buf);
6989
6990 /* Put together the add or sub instruction used by ENDF. */
6991 s = buf;
6992 if (up)
6993 strcpy (s, "add");
6994 else
6995 strcpy (s, "sub");
6996 s += 3;
6997 if (qual != '\0')
3882b010 6998 *s++ = TOLOWER (qual);
252b5132
RH		 6999 *s++ = ' ';
7000 memcpy (s, bystart, bystop - bystart);
7001 s += bystop - bystart;
7002 *s++ = ',';
7003 memcpy (s, varstart, varstop - varstart);
7004 s += varstop - varstart;
7005 *s = '\0';
7006 n->incr = buf;
7007
7008 if (flag_mri)
7009 {
7010 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7011 ++input_line_pointer;
7012 }
7013
7014 demand_empty_rest_of_line ();
7015}
7016
7017/* Handle the MRI ENDF pseudo-op. */
7018
7019static void
31302357 7020s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7021{
7022 if (mri_control_stack == NULL
7023 || mri_control_stack->type != mri_for)
7024 {
7025 as_bad (_("endf without for"));
7026 ignore_rest_of_line ();
7027 return;
7028 }
7029
7030 colon (mri_control_stack->next);
7031
7032 mri_assemble (mri_control_stack->incr);
7033
7034 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7035 mri_assemble (mri_control_stack->incr);
7036
7037 free (mri_control_stack->incr);
7038
7039 colon (mri_control_stack->bottom);
7040
7041 pop_mri_control ();
7042
7043 if (flag_mri)
7044 {
7045 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7046 ++input_line_pointer;
7047 }
7048
7049 demand_empty_rest_of_line ();
7050}
7051
7052/* Handle the MRI REPEAT pseudo-op. */
7053
7054static void
31302357 7055s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7056{
7057 struct mri_control_info *n;
7058
7059 n = push_mri_control (mri_repeat);
7060 colon (n->top);
7061 if (flag_mri)
7062 {
7063 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7064 ++input_line_pointer;
7065 }
7066 demand_empty_rest_of_line ();
7067}
7068
7069/* Handle the MRI UNTIL pseudo-op. */
7070
7071static void
31302357 7072s_mri_until (int qual)
252b5132
RH		 7073{
7074 char *s;
7075
7076 if (mri_control_stack == NULL
7077 || mri_control_stack->type != mri_repeat)
7078 {
7079 as_bad (_("until without repeat"));
7080 ignore_rest_of_line ();
7081 return;
7082 }
7083
7084 colon (mri_control_stack->next);
7085
7086 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7087 ;
7088
7089 parse_mri_control_expression (s, qual, (const char *) NULL,
7090 mri_control_stack->top, '\0');
7091
7092 colon (mri_control_stack->bottom);
7093
7094 input_line_pointer = s;
7095
7096 pop_mri_control ();
7097
7098 if (flag_mri)
7099 {
7100 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7101 ++input_line_pointer;
7102 }
7103
7104 demand_empty_rest_of_line ();
7105}
7106
7107/* Handle the MRI WHILE pseudo-op. */
7108
7109static void
31302357 7110s_mri_while (int qual)
252b5132
RH		 7111{
7112 char *s;
7113
7114 struct mri_control_info *n;
7115
7116 s = input_line_pointer;
e1f44d10
NC		 7117 /* We only accept '*' as introduction of comments if preceded by white space
7118 or at first column of a line (I think this can't actually happen here?)
7119 This is important when assembling:
7120 while d0 <ne> 12(a0,d0*2) do
36759679 7121 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7122 while (! (is_end_of_line[(unsigned char) *s]
7123 || (flag_mri
7124 && *s == '*'
7125 && (s == input_line_pointer
7126 || *(s-1) == ' '
7127 || *(s-1) == '\t'))))
252b5132
RH		 7128 s++;
7129 --s;
7130 while (*s == ' ' || *s == '\t')
7131 --s;
7132 if (s - input_line_pointer > 1
7133 && s[-1] == '.')
7134 s -= 2;
7135 if (s - input_line_pointer < 2
7136 || strncasecmp (s - 1, "DO", 2) != 0)
7137 {
7138 as_bad (_("missing do"));
7139 ignore_rest_of_line ();
7140 return;
7141 }
7142
7143 n = push_mri_control (mri_while);
7144
7145 colon (n->next);
7146
7147 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7148 s[1] == '.' ? s[2] : '\0');
7149
7150 input_line_pointer = s + 1;
7151 if (*input_line_pointer == '.')
7152 input_line_pointer += 2;
7153
7154 if (flag_mri)
7155 {
7156 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7157 ++input_line_pointer;
7158 }
7159
7160 demand_empty_rest_of_line ();
7161}
7162
7163/* Handle the MRI ENDW pseudo-op. */
7164
7165static void
31302357 7166s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7167{
7168 char *buf;
7169
7170 if (mri_control_stack == NULL
7171 || mri_control_stack->type != mri_while)
7172 {
7173 as_bad (_("endw without while"));
7174 ignore_rest_of_line ();
7175 return;
7176 }
7177
add39d23 7178 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next));
252b5132
RH		 7179 sprintf (buf, "bra %s", mri_control_stack->next);
7180 mri_assemble (buf);
7181 free (buf);
7182
7183 colon (mri_control_stack->bottom);
7184
7185 pop_mri_control ();
7186
7187 if (flag_mri)
7188 {
7189 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7190 ++input_line_pointer;
7191 }
7192
7193 demand_empty_rest_of_line ();
7194}
7195\f
266abb8f
NS		 7196/* Parse a .cpu directive. */
7197
7198static void
7199s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7200{
7201 char saved_char;
7202 char *name;
7203
7204 if (initialized)
7205 {
7206 as_bad (_("already assembled instructions"));
7207 ignore_rest_of_line ();
7208 return;
7209 }
3739860c 7210
266abb8f
NS		 7211 name = input_line_pointer;
7212 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7213 input_line_pointer++;
7214 saved_char = *input_line_pointer;
7215 *input_line_pointer = 0;
7216
7217 m68k_set_cpu (name, 1, 0);
3739860c 7218
266abb8f
NS		 7219 *input_line_pointer = saved_char;
7220 demand_empty_rest_of_line ();
7221 return;
7222}
7223
7224/* Parse a .arch directive. */
7225
7226static void
7227s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7228{
7229 char saved_char;
7230 char *name;
7231
7232 if (initialized)
7233 {
7234 as_bad (_("already assembled instructions"));
7235 ignore_rest_of_line ();
7236 return;
7237 }
3739860c 7238
266abb8f
NS		 7239 name = input_line_pointer;
7240 while (*input_line_pointer && *input_line_pointer != ','
7241 && !ISSPACE (*input_line_pointer))
7242 input_line_pointer++;
7243 saved_char = *input_line_pointer;
7244 *input_line_pointer = 0;
7245
7246 if (m68k_set_arch (name, 1, 0))
7247 {
7248 /* Scan extensions. */
7249 do
7250 {
7251 *input_line_pointer++ = saved_char;
7252 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7253 break;
7254 name = input_line_pointer;
7255 while (*input_line_pointer && *input_line_pointer != ','
7256 && !ISSPACE (*input_line_pointer))
7257 input_line_pointer++;
7258 saved_char = *input_line_pointer;
7259 *input_line_pointer = 0;
7260 }
7261 while (m68k_set_extension (name, 1, 0));
7262 }
3739860c 7263
266abb8f
NS		 7264 *input_line_pointer = saved_char;
7265 demand_empty_rest_of_line ();
7266 return;
7267}
7268\f
7269/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7270 if none is found, the caller is responsible for emitting an error
7271 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7272 cpu name, if it begins with a '6' (possibly skipping an intervening
7273 'c'. We also allow a 'c' in the same place. if NEGATED is
7274 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7275 the option is indeed negated. */
7276
7277static const struct m68k_cpu *
7278m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7279 int allow_m, int *negated)
7280{
7281 /* allow negated value? */
7282 if (negated)
7283 {
7284 *negated = 0;
7285
7286 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7287 {
7288 arg += 3;
7289 *negated = 1;
7290 }
7291 }
3739860c 7292
266abb8f
NS		 7293 /* Remove 'm' or 'mc' prefix from 68k variants. */
7294 if (allow_m)
7295 {
7296 if (arg[0] == 'm')
7297 {
7298 if (arg[1] == '6')
7299 arg += 1;
7300 else if (arg[1] == 'c' && arg[2] == '6')
7301 arg += 2;
7302 }
7303 }
7304 else if (arg[0] == 'c' && arg[1] == '6')
7305 arg += 1;
7306
7307 for (; table->name; table++)
7308 if (!strcmp (arg, table->name))
2da12c60
NS		 7309 {
7310 if (table->alias < -1 || table->alias > 1)
7311 as_bad (_("`%s' is deprecated, use `%s'"),
7312 table->name, table[table->alias < 0 ? 1 : -1].name);
7313 return table;
7314 }
266abb8f
NS		 7315 return 0;
7316}
7317
bfbba8e4 7318/* Set the cpu, issuing errors if it is unrecognized. */
266abb8f
NS		 7319
7320static int
7321m68k_set_cpu (char const *name, int allow_m, int silent)
7322{
7323 const struct m68k_cpu *cpu;
7324
7325 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7326
7327 if (!cpu)
7328 {
7329 if (!silent)
7330 as_bad (_("cpu `%s' unrecognized"), name);
7331 return 0;
7332 }
266abb8f
NS		 7333 selected_cpu = cpu;
7334 return 1;
7335}
7336
bfbba8e4 7337/* Set the architecture, issuing errors if it is unrecognized. */
266abb8f
NS		 7338
7339static int
7340m68k_set_arch (char const *name, int allow_m, int silent)
7341{
7342 const struct m68k_cpu *arch;
7343
7344 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7345
7346 if (!arch)
7347 {
7348 if (!silent)
7349 as_bad (_("architecture `%s' unrecognized"), name);
7350 return 0;
7351 }
266abb8f
NS		 7352 selected_arch = arch;
7353 return 1;
7354}
7355
7356/* Set the architecture extension, issuing errors if it is
7357 unrecognized, or invalid */
7358
7359static int
7360m68k_set_extension (char const *name, int allow_m, int silent)
7361{
7362 int negated;
7363 const struct m68k_cpu *ext;
7364
7365 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7366
7367 if (!ext)
7368 {
7369 if (!silent)
7370 as_bad (_("extension `%s' unrecognized"), name);
7371 return 0;
7372 }
7373
7374 if (negated)
87298967
NS		 7375 not_current_architecture |= (ext->control_regs
7376 ? *(unsigned *)ext->control_regs: ext->arch);
266abb8f
NS		 7377 else
7378 current_architecture |= ext->arch;
7379 return 1;
7380}
7381
31302357
AS		 7382/* md_parse_option
7383 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7384 */
252b5132 7385
5a38dc70 7386const char *md_shortopts = "lSA:m:kQ:V";
252b5132
RH		 7387
7388struct option md_longopts[] = {
7389#define OPTION_PIC (OPTION_MD_BASE)
7390 {"pic", no_argument, NULL, OPTION_PIC},
7391#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7392 {"register-prefix-optional", no_argument, NULL,
7393 OPTION_REGISTER_PREFIX_OPTIONAL},
7394#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7395 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7396#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7397 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7398#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7399 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7400#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7401 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7402#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7403 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7404#define OPTION_PCREL (OPTION_MD_BASE + 7)
7405 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7406 {NULL, no_argument, NULL, 0}
7407};
bc805888 7408size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7409
7410int
17b9d67d 7411md_parse_option (int c, const char *arg)
252b5132
RH		 7412{
7413 switch (c)
7414 {
7415 case 'l': /* -l means keep external to 2 bit offset
36759679 7416 rather than 16 bit one. */
252b5132
RH		 7417 flag_short_refs = 1;
7418 break;
7419
7420 case 'S': /* -S means that jbsr's always turn into
7421 jsr's. */
7422 flag_long_jumps = 1;
7423 break;
7424
28e7409f
NC		 7425 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7426 branches into absolute jumps. */
7427 flag_keep_pcrel = 1;
7428 break;
7429
252b5132
RH		 7430 case OPTION_PIC:
7431 case 'k':
7432 flag_want_pic = 1;
36759679 7433 break; /* -pic, Position Independent Code. */
252b5132
RH		 7434
7435 case OPTION_REGISTER_PREFIX_OPTIONAL:
7436 flag_reg_prefix_optional = 1;
7437 reg_prefix_optional_seen = 1;
7438 break;
7439
7440 /* -V: SVR4 argument to print version ID. */
7441 case 'V':
7442 print_version_id ();
7443 break;
7444
7445 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7446 should be emitted or not. FIXME: Not implemented. */
7447 case 'Q':
7448 break;
7449
7450 case OPTION_BITWISE_OR:
7451 {
7452 char *n, *t;
7453 const char *s;
7454
add39d23 7455 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1);
252b5132
RH		 7456 t = n;
7457 for (s = m68k_comment_chars; *s != '\0'; s++)
7458 if (*s != '|')
7459 *t++ = *s;
7460 *t = '\0';
7461 m68k_comment_chars = n;
7462 }
7463 break;
7464
7465 case OPTION_BASE_SIZE_DEFAULT_16:
7466 m68k_index_width_default = SIZE_WORD;
7467 break;
7468
7469 case OPTION_BASE_SIZE_DEFAULT_32:
7470 m68k_index_width_default = SIZE_LONG;
7471 break;
7472
7473 case OPTION_DISP_SIZE_DEFAULT_16:
7474 m68k_rel32 = 0;
7475 m68k_rel32_from_cmdline = 1;
7476 break;
7477
7478 case OPTION_DISP_SIZE_DEFAULT_32:
7479 m68k_rel32 = 1;
7480 m68k_rel32_from_cmdline = 1;
7481 break;
7482
266abb8f
NS		 7483 case 'A':
7484#if WARN_DEPRECATED
7485 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7486 arg, arg));
7487#endif
7488 /* Intentional fall-through. */
7489 case 'm':
7490 if (!strncmp (arg, "arch=", 5))
7491 m68k_set_arch (arg + 5, 1, 0);
7492 else if (!strncmp (arg, "cpu=", 4))
7493 m68k_set_cpu (arg + 4, 1, 0);
7494 else if (m68k_set_extension (arg, 0, 1))
7495 ;
0b2e31dc
NS		 7496 else if (m68k_set_arch (arg, 0, 1))
7497 ;
266abb8f
NS		 7498 else if (m68k_set_cpu (arg, 0, 1))
7499 ;
7500 else
7501 return 0;
7502 break;
7503
252b5132
RH		 7504 default:
7505 return 0;
7506 }
7507
7508 return 1;
7509}
7510
266abb8f
NS		 7511/* Setup tables from the selected arch and/or cpu */
7512
7513static void
7514m68k_init_arch (void)
7515{
266abb8f
NS		 7516 if (not_current_architecture & current_architecture)
7517 {
7518 as_bad (_("architecture features both enabled and disabled"));
7519 not_current_architecture &= ~current_architecture;
7520 }
7521 if (selected_arch)
2da12c60
NS		 7522 {
7523 current_architecture |= selected_arch->arch;
7524 control_regs = selected_arch->control_regs;
7525 }
0b2e31dc
NS		 7526 else
7527 current_architecture |= selected_cpu->arch;
3739860c 7528
2da12c60
NS		 7529 current_architecture &= ~not_current_architecture;
7530
377260ba
NS		 7531 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7532 {
7533 /* Determine which float is really meant. */
7534 if (current_architecture & (m68k_mask & ~m68881))
7535 current_architecture ^= cfloat;
7536 else
7537 current_architecture ^= m68881;
7538 }
7539
0b2e31dc 7540 if (selected_cpu)
266abb8f 7541 {
2da12c60 7542 control_regs = selected_cpu->control_regs;
0b2e31dc 7543 if (current_architecture & ~selected_cpu->arch)
266abb8f 7544 {
0b2e31dc
NS		 7545 as_bad (_("selected processor does not have all features of selected architecture"));
7546 current_architecture
7547 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7548 }
7549 }
266abb8f 7550
266abb8f
NS		 7551 if ((current_architecture & m68k_mask)
7552 && (current_architecture & ~m68k_mask))
7553 {
7554 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7555 if (current_architecture & m68k_mask)
266abb8f
NS		 7556 current_architecture &= m68k_mask;
7557 else
7558 current_architecture &= ~m68k_mask;
7559 }
3739860c 7560
266abb8f
NS		 7561 /* Permit m68881 specification with all cpus; those that can't work
7562 with a coprocessor could be doing emulation. */
7563 if (current_architecture & m68851)
7564 {
7565 if (current_architecture & m68040)
7566 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7567 }
7568 /* What other incompatibilities could we check for? */
7569
266abb8f
NS		 7570 if (cpu_of_arch (current_architecture) < m68020
7571 || arch_coldfire_p (current_architecture))
7572 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3739860c 7573
266abb8f
NS		 7574 initialized = 1;
7575}
7576
252b5132 7577void
31302357 7578md_show_usage (FILE *stream)
252b5132 7579{
76f57f3a 7580 const char *default_cpu = TARGET_CPU;
f1f5ef86 7581 int i;
76f57f3a 7582
8a104df9 7583 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7584 if (*default_cpu == 'm')
7585 default_cpu++;
266abb8f 7586 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7587 {
266abb8f 7588 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7589 {
2da12c60
NS		 7590 while (m68k_cpus[i].alias > 0)
7591 i--;
7592 while (m68k_cpus[i].alias < 0)
7593 i++;
7594 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7595 }
7596 }
7597
bc805888 7598 fprintf (stream, _("\
266abb8f
NS		 7599-march=<arch> set architecture\n\
7600-mcpu=<cpu> set cpu [default %s]\n\
7601"), default_cpu);
7602 for (i = 0; m68k_extensions[i].name; i++)
7603 fprintf (stream, _("\
33eaf5de 7604-m[no-]%-16s enable/disable %s architecture extension\n\
0b2e31dc
NS		 7605"), m68k_extensions[i].name,
7606 m68k_extensions[i].alias > 0 ? " ColdFire"
7607 : m68k_extensions[i].alias < 0 ? " m68k" : "");
3739860c 7608
bc805888 7609 fprintf (stream, _("\
266abb8f 7610-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7611-pic, -k generate position independent code\n\
7612-S turn jbsr into jsr\n\
28e7409f 7613--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7614--register-prefix-optional\n\
7615 recognize register names without prefix character\n\
266abb8f 7616--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7617--base-size-default-16 base reg without size is 16 bits\n\
7618--base-size-default-32 base reg without size is 32 bits (default)\n\
7619--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7620--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7621"));
3739860c 7622
266abb8f
NS		 7623 fprintf (stream, _("Architecture variants are: "));
7624 for (i = 0; m68k_archs[i].name; i++)
7625 {
7626 if (i)
7627 fprintf (stream, " | ");
87298967 7628 fprintf (stream, "%s", m68k_archs[i].name);
266abb8f
NS		 7629 }
7630 fprintf (stream, "\n");
7631
7632 fprintf (stream, _("Processor variants are: "));
7633 for (i = 0; m68k_cpus[i].name; i++)
7634 {
7635 if (i)
7636 fprintf (stream, " | ");
87298967 7637 fprintf (stream, "%s", m68k_cpus[i].name);
266abb8f
NS		 7638 }
7639 fprintf (stream, _("\n"));
252b5132
RH		 7640}
7641\f
7642#ifdef TEST2
7643
7644/* TEST2: Test md_assemble() */
36759679
NC		 7645/* Warning, this routine probably doesn't work anymore. */
7646int
31302357 7647main (void)
252b5132
RH		 7648{
7649 struct m68k_it the_ins;
7650 char buf[120];
7651 char *cp;
7652 int n;
7653
7654 m68k_ip_begin ();
7655 for (;;)
7656 {
7657 if (!gets (buf) || !*buf)
7658 break;
7659 if (buf[0] == '|' || buf[1] == '.')
7660 continue;
7661 for (cp = buf; *cp; cp++)
7662 if (*cp == '\t')
7663 *cp = ' ';
7664 if (is_label (buf))
7665 continue;
7666 memset (&the_ins, '\0', sizeof (the_ins));
7667 m68k_ip (&the_ins, buf);
7668 if (the_ins.error)
7669 {
7670 printf (_("Error %s in %s\n"), the_ins.error, buf);
7671 }
7672 else
7673 {
7674 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7675 for (n = 0; n < the_ins.numo; n++)
7676 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7677 printf (" ");
7678 print_the_insn (&the_ins.opcode[0], stdout);
7679 (void) putchar ('\n');
7680 }
7681 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7682 {
7683 if (the_ins.operands[n].error)
7684 {
7685 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7686 continue;
7687 }
31302357
AS		 7688 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7689 the_ins.operands[n].reg);
252b5132 7690 if (the_ins.operands[n].b_const)
31302357
AS		 7691 printf ("Constant: '%.*s', ",
7692 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7693 the_ins.operands[n].b_const);
7694 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7695 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7696 if (the_ins.operands[n].b_iadd)
31302357
AS		 7697 printf ("Iadd: '%.*s',",
7698 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7699 the_ins.operands[n].b_iadd);
7700 putchar ('\n');
252b5132
RH		 7701 }
7702 }
7703 m68k_ip_end ();
7704 return 0;
7705}
7706
31302357
AS		 7707int
7708is_label (char *str)
252b5132
RH		 7709{
7710 while (*str == ' ')
7711 str++;
7712 while (*str && *str != ' ')
7713 str++;
7714 if (str[-1] == ':' || str[1] == '=')
7715 return 1;
7716 return 0;
7717}
7718
7719#endif
7720
7721/* Possible states for relaxation:
7722
7723 0 0 branch offset byte (bra, etc)
7724 0 1 word
7725 0 2 long
7726
7727 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7728 1 1 word
7729 1 2 long
7730
7731 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7732 2 1 word-long
7733 2 2 long-word
7734 2 3 long-long
7735
7736 */
7737
7738/* We have no need to default values of symbols. */
7739
252b5132 7740symbolS *
31302357 7741md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7742{
7743 return 0;
7744}
7745
7746/* Round up a section size to the appropriate boundary. */
7747valueT
31302357 7748md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 7749{
252b5132
RH		 7750 return size;
7751}
7752
7753/* Exactly what point is a PC-relative offset relative TO?
7754 On the 68k, it is relative to the address of the first extension
7755 word. The difference between the addresses of the offset and the
92774660 7756 first extension word is stored in fx_pcrel_adjust. */
252b5132 7757long
31302357 7758md_pcrel_from (fixS *fixP)
252b5132
RH		 7759{
7760 int adjust;
7761
552c607f 7762 adjust = fixP->fx_pcrel_adjust;
252b5132
RH		 7763 if (adjust == 64)
7764 adjust = -1;
7765 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7766}
7767
8a104df9 7768void
31302357 7769m68k_elf_final_processing (void)
0d96863f 7770{
266abb8f 7771 unsigned flags = 0;
3739860c 7772
238d258f 7773 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7774 flags |= EF_M68K_CFV4E;
7775 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7776 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7777 flags |= EF_M68K_CPU32;
7778 else if (cpu_of_arch (current_architecture) & fido_a)
7779 flags |= EF_M68K_FIDO;
8a104df9
KH		 7780 else if ((cpu_of_arch (current_architecture) & m68000up)
7781 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f 7782 flags |= EF_M68K_M68000;
3739860c 7783
266abb8f
NS		 7784 if (current_architecture & mcfisa_a)
7785 {
0b2e31dc
NS		 7786 static const unsigned isa_features[][2] =
7787 {
9a2e615a 7788 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7789 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7790 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7791 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7792 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7793 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
8d100c32 7794 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
0b2e31dc
NS		 7795 {0,0},
7796 };
7797 static const unsigned mac_features[][2] =
7798 {
c694fd50
KH		 7799 {EF_M68K_CF_MAC, mcfmac},
7800 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7801 {0,0},
7802 };
7803 unsigned ix;
7804 unsigned pattern;
3739860c 7805
0b2e31dc 7806 pattern = (current_architecture
9a2e615a 7807 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7808 for (ix = 0; isa_features[ix][1]; ix++)
7809 {
7810 if (pattern == isa_features[ix][1])
7811 {
7812 flags |= isa_features[ix][0];
7813 break;
7814 }
7815 }
7816 if (!isa_features[ix][1])
7817 {
7818 cf_bad:
7819 as_warn (_("Not a defined coldfire architecture"));
7820 }
7821 else
7822 {
7823 if (current_architecture & cfloat)
c694fd50 7824 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7825
0b2e31dc
NS		 7826 pattern = current_architecture & (mcfmac|mcfemac);
7827 if (pattern)
7828 {
7829 for (ix = 0; mac_features[ix][1]; ix++)
7830 {
7831 if (pattern == mac_features[ix][1])
7832 {
7833 flags |= mac_features[ix][0];
7834 break;
7835 }
7836 }
7837 if (!mac_features[ix][1])
7838 goto cf_bad;
7839 }
7840 }
266abb8f
NS		 7841 }
7842 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f 7843}
cf869cce
NC		 7844
7845/* Parse @TLSLDO and return the desired relocation. */
7846static bfd_reloc_code_real_type
7847m68k_elf_suffix (char **str_p, expressionS *exp_p)
7848{
7849 char ident[20];
7850 char *str = *str_p;
7851 char *str2;
7852 int ch;
7853 int len;
7854
7855 if (*str++ != '@')
7856 return BFD_RELOC_UNUSED;
7857
7858 for (ch = *str, str2 = ident;
7859 (str2 < ident + sizeof (ident) - 1
7860 && (ISALNUM (ch) || ch == '@'));
7861 ch = *++str)
7862 {
7863 *str2++ = ch;
7864 }
7865
7866 *str2 = '\0';
7867 len = str2 - ident;
7868
7869 if (strncmp (ident, "TLSLDO", 6) == 0
7870 && len == 6)
7871 {
7872 /* Now check for identifier@suffix+constant. */
7873 if (*str == '-' || *str == '+')
7874 {
7875 char *orig_line = input_line_pointer;
7876 expressionS new_exp;
7877
7878 input_line_pointer = str;
7879 expression (&new_exp);
7880 if (new_exp.X_op == O_constant)
7881 {
7882 exp_p->X_add_number += new_exp.X_add_number;
7883 str = input_line_pointer;
7884 }
7885
7886 if (&input_line_pointer != str_p)
7887 input_line_pointer = orig_line;
7888 }
7889 *str_p = str;
7890
7891 return BFD_RELOC_68K_TLS_LDO32;
7892 }
7893
7894 return BFD_RELOC_UNUSED;
7895}
7896
7897/* Handles .long <tls_symbol>+0x8000 debug info.
7898 Clobbers input_line_pointer, checks end-of-line.
7899 Adapted from tc-ppc.c:ppc_elf_cons. */
7900static void
7901m68k_elf_cons (int nbytes /* 4=.long */)
7902{
7903 if (is_it_end_of_statement ())
7904 {
7905 demand_empty_rest_of_line ();
7906 return;
7907 }
7908
7909 do
7910 {
7911 expressionS exp;
7912 bfd_reloc_code_real_type reloc;
7913
7914 expression (&exp);
7915 if (exp.X_op == O_symbol
7916 && *input_line_pointer == '@'
7917 && (reloc = m68k_elf_suffix (&input_line_pointer,
7918 &exp)) != BFD_RELOC_UNUSED)
7919 {
7920 reloc_howto_type *reloc_howto;
7921 int size;
7922
7923 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
7924 size = bfd_get_reloc_size (reloc_howto);
7925
7926 if (size > nbytes)
7927 {
992a06ee
AM		 7928 as_bad (ngettext ("%s relocations do not fit in %u byte",
7929 "%s relocations do not fit in %u bytes",
7930 nbytes),
cf869cce
NC		 7931 reloc_howto->name, nbytes);
7932 }
7933 else
7934 {
7935 char *p;
7936 int offset;
7937
7938 p = frag_more (nbytes);
7939 offset = 0;
7940 if (target_big_endian)
7941 offset = nbytes - size;
7942 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7943 &exp, 0, reloc);
7944 }
7945 }
7946 else
7947 emit_expr (&exp, (unsigned int) nbytes);
7948 }
7949 while (*input_line_pointer++ == ',');
7950
7951 /* Put terminator back into stream. */
7952 input_line_pointer--;
7953 demand_empty_rest_of_line ();
7954}
c04898f8 7955
85f7484a
PB		 7956/* Parse a .gnu_attribute directive. */
7957static void
7958m68k_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED)
7959{
7960 int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU);
7961
7962 /* Check validity of defined m68k tags. */
7963 if (tag == Tag_GNU_M68K_ABI_FP)
7964 {
7965 unsigned int val;
7966
7967 val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag);
7968
7969 if (tag == Tag_GNU_M68K_ABI_FP && val > 2)
7970 as_warn (_("unknown .gnu_attribute value"));
7971 }
7972}
7973
c04898f8 7974int
e0471c16 7975tc_m68k_regname_to_dw2regnum (const char *regname)
c04898f8
AS		 7976{
7977 unsigned int regnum;
7978 static const char *const regnames[] =
7979 {
7980 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7981 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7982 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7983 "pc"
7984 };
7985
7986 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7987 if (strcmp (regname, regnames[regnum]) == 0)
7988 return regnum;
7989
7990 return -1;
7991}
7992
7993void
7994tc_m68k_frame_initial_instructions (void)
7995{
7996 static int sp_regno = -1;
7997
7998 if (sp_regno < 0)
7999 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8000
8001 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8002 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8003}
909c7f9c
NC		 8004
8005/* Check and emit error if broken-word handling has failed to fix up a
8006 case-table. This is called from write.c, after doing everything it
8007 knows about how to handle broken words. */
8008
8009void
8010tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
8011{
8012 if (new_offset > 32767 || new_offset < -32768)
8013 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
8014 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),
8015 (long) new_offset);
8016}
8017
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