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[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3e602632 3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
252b5132
RH		 36/* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40#if defined (TE_SVR4) || defined (TE_DELTA)
41const char *m68k_comment_chars = "|#";
42#else
43const char *m68k_comment_chars = "|";
44#endif
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
92774660
KH		 51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
252b5132
RH		 53const char line_comment_chars[] = "#*";
54
63a0b638 55const char line_separator_chars[] = ";";
252b5132 56
36759679 57/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 58const char EXP_CHARS[] = "eE";
252b5132
RH		 59
60/* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
5a38dc70 63const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 64
65/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
36759679 69const int md_reloc_size = 8; /* Size of relocation record. */
252b5132
RH		 70
71/* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
92774660 73 references. Not implemented. For ELF there are other means
252b5132
RH		 74 to denote pic relocations. */
75int flag_want_pic;
76
36759679
NC		 77static int flag_short_refs; /* -l option. */
78static int flag_long_jumps; /* -S option. */
28e7409f 79static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 80
81#ifdef REGISTER_PREFIX_OPTIONAL
82int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83#else
84int flag_reg_prefix_optional;
85#endif
86
87/* Whether --register-prefix-optional was used on the command line. */
88static int reg_prefix_optional_seen;
89
90/* The floating point coprocessor to use by default. */
91static enum m68k_register m68k_float_copnum = COP1;
92
93/* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95static int m68k_abspcadd;
96
97/* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99static int m68k_quick = 1;
100
101/* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104static int m68k_rel32 = 1;
105
106/* This is non-zero if m68k_rel32 was set from the command line. */
107static int m68k_rel32_from_cmdline;
108
109/* The default width to use for an index register when using a base
110 displacement. */
111static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113/* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
252b5132
RH		 116struct label_line
117{
118 struct label_line *next;
119 symbolS *label;
120 char *file;
121 unsigned int line;
122 int text;
123};
124
125/* The list of labels. */
126
127static struct label_line *labels;
128
129/* The current label. */
130
131static struct label_line *current_label;
132
36759679
NC		 133/* Its an arbitrary name: This means I don't approve of it.
134 See flames below. */
252b5132
RH		 135static struct obstack robyn;
136
252b5132
RH		 137struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148#define gettwo(x) (((x)->m_opcode)&0xffff)
149
150static const enum m68k_register m68000_control_regs[] = { 0 };
151static const enum m68k_register m68010_control_regs[] = {
152 SFC, DFC, USP, VBR,
153 0
154};
155static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158};
159static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163};
164static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168};
6da466c7 169static const enum m68k_register mcf_control_regs[] = {
3e602632 170 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 171 RAMBAR0, RAMBAR1, MBAR,
172 0
173};
3e602632
NC		 174static const enum m68k_register mcf528x_control_regs[] = {
175 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
176 0
177};
178static const enum m68k_register mcfv4e_control_regs[] = {
179 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
180 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
181 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
182 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
183 0
184};
252b5132
RH		 185#define cpu32_control_regs m68010_control_regs
186
187static const enum m68k_register *control_regs;
188
36759679 189/* Internal form of a 68020 instruction. */
252b5132
RH		 190struct m68k_it
191{
192 const char *error;
36759679 193 const char *args; /* List of opcode info. */
252b5132
RH		 194 int numargs;
195
36759679 196 int numo; /* Number of shorts in opcode. */
252b5132
RH		 197 short opcode[11];
198
199 struct m68k_op operands[6];
200
36759679 201 int nexp; /* Number of exprs in use. */
252b5132
RH		 202 struct m68k_exp exprs[4];
203
36759679 204 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 205 struct
206 {
36759679 207 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 208 symbolS *fadd;
209 offsetT foff;
210 int fragty;
211 }
212 fragb[4];
213
36759679 214 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 215 struct
216 {
217 int n;
218 expressionS exp;
219 char wid;
220 char pcrel;
221 /* In a pc relative address the difference between the address
222 of the offset and the address that the offset is relative
223 to. This depends on the addressing mode. Basically this
224 is the value to put in the offset field to address the
225 first byte of the offset, without regarding the special
226 significance of some values (in the branch instruction, for
227 example). */
228 int pcrel_fix;
229#ifdef OBJ_ELF
230 /* Whether this expression needs special pic relocation, and if
231 so, which. */
232 enum pic_relocation pic_reloc;
233#endif
234 }
36759679 235 reloc[5]; /* Five is enough??? */
252b5132
RH		 236};
237
3e602632 238#define cpu_of_arch(x) ((x) & (m68000up | mcf))
252b5132
RH		 239#define float_of_arch(x) ((x) & mfloat)
240#define mmu_of_arch(x) ((x) & mmmu)
3e602632
NC		 241#define arch_coldfire_p(x) ((x) & mcf)
242#define arch_coldfire_v4e_p(x) ((x) & mcfv4e)
252b5132 243
36759679 244/* Macros for determining if cpu supports a specific addressing mode. */
3e602632 245#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407|mcfv4e))
252b5132 246
36759679 247static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 248
249#define op(ex) ((ex)->exp.X_op)
250#define adds(ex) ((ex)->exp.X_add_symbol)
251#define subs(ex) ((ex)->exp.X_op_symbol)
252#define offs(ex) ((ex)->exp.X_add_number)
253
36759679 254/* Macros for adding things to the m68k_it struct. */
252b5132
RH		 255#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
256
257/* Static functions. */
252b5132
RH		 258static void insop PARAMS ((int, const struct m68k_incant *));
259static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
260static void add_frag PARAMS ((symbolS *, offsetT, int));
261
36759679
NC		 262/* Like addword, but goes BEFORE general operands. */
263
252b5132
RH		 264static void
265insop (w, opcode)
266 int w;
267 const struct m68k_incant *opcode;
268{
269 int z;
07726851 270 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 271 the_ins.opcode[z] = the_ins.opcode[z - 1];
272 for (z = 0; z < the_ins.nrel; z++)
273 the_ins.reloc[z].n += 2;
252b5132
RH		 274 for (z = 0; z < the_ins.nfrag; z++)
275 the_ins.fragb[z].fragoff++;
8a104df9 276 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 277 the_ins.numo++;
278}
279
280/* The numo+1 kludge is so we can hit the low order byte of the prev word.
281 Blecch. */
282static void
283add_fix (width, exp, pc_rel, pc_fix)
284 int width;
285 struct m68k_exp *exp;
286 int pc_rel;
287 int pc_fix;
288{
289 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
290 ? (the_ins.numo*2-1)
291 : (((width)=='b')
292 ? (the_ins.numo*2+1)
293 : (the_ins.numo*2)));
294 the_ins.reloc[the_ins.nrel].exp = exp->exp;
295 the_ins.reloc[the_ins.nrel].wid = width;
296 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
297#ifdef OBJ_ELF
298 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
299#endif
300 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
301}
302
303/* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
307
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
311
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
313static void
314add_frag (add, off, type)
315 symbolS *add;
316 offsetT off;
317 int type;
318{
8a104df9
KH		 319 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
320 the_ins.fragb[the_ins.nfrag].fadd = add;
321 the_ins.fragb[the_ins.nfrag].foff = off;
322 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 323}
324
325#define isvar(ex) \
326 (op (ex) != O_constant && op (ex) != O_big)
327
328static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
329static int get_num PARAMS ((struct m68k_exp *exp, int ok));
330static void m68k_ip PARAMS ((char *));
331static void insert_reg PARAMS ((const char *, int));
332static void select_control_regs PARAMS ((void));
333static void init_regtable PARAMS ((void));
334static int reverse_16_bits PARAMS ((int in));
335static int reverse_8_bits PARAMS ((int in));
336static void install_gen_operand PARAMS ((int mode, int val));
337static void install_operand PARAMS ((int mode, int val));
338static void s_bss PARAMS ((int));
339static void s_data1 PARAMS ((int));
340static void s_data2 PARAMS ((int));
341static void s_even PARAMS ((int));
342static void s_proc PARAMS ((int));
343static void mri_chip PARAMS ((void));
344static void s_chip PARAMS ((int));
345static void s_fopt PARAMS ((int));
346static void s_opt PARAMS ((int));
347static void s_reg PARAMS ((int));
348static void s_restore PARAMS ((int));
349static void s_save PARAMS ((int));
350static void s_mri_if PARAMS ((int));
351static void s_mri_else PARAMS ((int));
352static void s_mri_endi PARAMS ((int));
353static void s_mri_break PARAMS ((int));
354static void s_mri_next PARAMS ((int));
355static void s_mri_for PARAMS ((int));
356static void s_mri_endf PARAMS ((int));
357static void s_mri_repeat PARAMS ((int));
358static void s_mri_until PARAMS ((int));
359static void s_mri_while PARAMS ((int));
360static void s_mri_endw PARAMS ((int));
252b5132
RH		 361static void md_convert_frag_1 PARAMS ((fragS *));
362
363static int current_architecture;
364
dc84e067
NC		 365struct m68k_cpu
366 {
367 unsigned long arch;
368 const char *name;
369 int alias;
370 };
252b5132 371
dc84e067
NC		 372static const struct m68k_cpu archs[] =
373 {
3e602632
NC		 374 { m68000, "68000", 0 },
375 { m68010, "68010", 0 },
376 { m68020, "68020", 0 },
377 { m68030, "68030", 0 },
378 { m68040, "68040", 0 },
379 { m68060, "68060", 0 },
380 { cpu32, "cpu32", 0 },
381 { m68881, "68881", 0 },
382 { m68851, "68851", 0 },
383 { mcf5200, "5200", 0 },
384 { mcf5206e,"5206e", 0 },
385 { mcf528x, "528x", 0 },
386 { mcf5307, "5307", 0 },
387 { mcf5407, "5407", 0 },
388 { mcfv4e, "cfv4e", 0 },
dc84e067
NC		 389 /* Aliases (effectively, so far as gas is concerned) for the above
390 cpus. */
391 { m68020, "68k", 1 },
392 { m68000, "68008", 1 },
393 { m68000, "68302", 1 },
394 { m68000, "68306", 1 },
395 { m68000, "68307", 1 },
396 { m68000, "68322", 1 },
397 { m68000, "68356", 1 },
398 { m68000, "68ec000", 1 },
399 { m68000, "68hc000", 1 },
400 { m68000, "68hc001", 1 },
401 { m68020, "68ec020", 1 },
402 { m68030, "68ec030", 1 },
403 { m68040, "68ec040", 1 },
404 { m68060, "68ec060", 1 },
405 { cpu32, "68330", 1 },
406 { cpu32, "68331", 1 },
407 { cpu32, "68332", 1 },
408 { cpu32, "68333", 1 },
409 { cpu32, "68334", 1 },
410 { cpu32, "68336", 1 },
411 { cpu32, "68340", 1 },
412 { cpu32, "68341", 1 },
413 { cpu32, "68349", 1 },
414 { cpu32, "68360", 1 },
415 { m68881, "68882", 1 },
416 { mcf5200, "5202", 1 },
417 { mcf5200, "5204", 1 },
418 { mcf5200, "5206", 1 },
3e602632 419 { mcf5407, "cfv4", 1 },
dc84e067 420 };
252b5132
RH		 421
422static const int n_archs = sizeof (archs) / sizeof (archs[0]);
423
151337e8
NC		 424/* This is the assembler relaxation table for m68k. m68k is a rich CISC
425 architecture and we have a lot of relaxation modes. */
252b5132 426
151337e8
NC		 427/* Macros used in the relaxation code. */
428#define TAB(x,y) (((x) << 2) + (y))
429#define TABTYPE(x) ((x) >> 2)
430
431/* Relaxation states. */
432#define BYTE 0
433#define SHORT 1
434#define LONG 2
435#define SZ_UNDEF 3
436
437/* Here are all the relaxation modes we support. First we can relax ordinary
438 branches. On 68020 and higher and on CPU32 all branch instructions take
439 three forms, so on these CPUs all branches always remain as such. When we
440 have to expand to the LONG form on a 68000, though, we substitute an
441 absolute jump instead. This is a direct replacement for unconditional
442 branches and a branch over a jump for conditional branches. However, if the
443 user requires PIC and disables this with --pcrel, we can only relax between
444 BYTE and SHORT forms, punting if that isn't enough. This gives us four
445 different relaxation modes for branches: */
446
36759679
NC		 447#define BRANCHBWL 0 /* Branch byte, word, or long. */
448#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
449#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
450#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 451
452/* We also relax coprocessor branches and DBcc's. All CPUs that support
453 coprocessor branches support them in word and long forms, so we have only
454 one relaxation mode for them. DBcc's are word only on all CPUs. We can
455 relax them to the LONG form with a branch-around sequence. This sequence
456 can use a long branch (if available) or an absolute jump (if acceptable).
457 This gives us two relaxation modes. If long branches are not available and
458 absolute jumps are not acceptable, we don't relax DBcc's. */
459
36759679
NC		 460#define FBRANCH 4 /* Coprocessor branch. */
461#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
462#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 463
464/* That's all for instruction relaxation. However, we also relax PC-relative
465 operands. Specifically, we have three operand relaxation modes. On the
466 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
467 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
468 two. Also PC+displacement+index operands in their simple form (with a non-
469 suppressed index without memory indirection) are supported on all CPUs, but
470 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
471 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
472 form of the PC+displacement+index operand. Finally, some absolute operands
473 can be relaxed down to 16-bit PC-relative. */
474
36759679
NC		 475#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
476#define PCINDEX 8 /* PC + displacement + index. */
477#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 478
479/* Note that calls to frag_var need to specify the maximum expansion
480 needed; this is currently 10 bytes for DBCC. */
481
482/* The fields are:
483 How far Forward this mode will reach:
484 How far Backward this mode will reach:
485 How many bytes this mode will add to the size of the frag
486 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 487
488 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 489relax_typeS md_relax_table[] =
490{
ac62c346
AM		 491 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
492 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
493 { 0, 0, 4, 0 },
494 { 1, 1, 0, 0 },
495
496 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
497 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
498 { 0, 0, 4, 0 },
499 { 1, 1, 0, 0 },
500
501 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
502 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
503 { 0, 0, 6, 0 },
504 { 1, 1, 0, 0 },
505
506 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
507 { 0, 0, 2, 0 },
508 { 1, 1, 0, 0 },
509 { 1, 1, 0, 0 },
510
36759679 511 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 512 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
513 { 0, 0, 4, 0 },
514 { 1, 1, 0, 0 },
515
36759679 516 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 517 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
518 { 0, 0, 10, 0 },
519 { 1, 1, 0, 0 },
520
36759679 521 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 522 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
523 { 0, 0, 10, 0 },
524 { 1, 1, 0, 0 },
525
36759679 526 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 527 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
528 { 0, 0, 6, 0 },
529 { 1, 1, 0, 0 },
530
531 { 125, -130, 0, TAB (PCINDEX, SHORT) },
532 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
533 { 0, 0, 4, 0 },
534 { 1, 1, 0, 0 },
535
36759679 536 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 537 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
538 { 0, 0, 4, 0 },
539 { 1, 1, 0, 0 },
252b5132
RH		 540};
541
542/* These are the machine dependent pseudo-ops. These are included so
543 the assembler can work on the output from the SUN C compiler, which
36759679 544 generates these. */
252b5132
RH		 545
546/* This table describes all the machine specific pseudo-ops the assembler
547 has to support. The fields are:
548 pseudo-op name without dot
549 function to call to execute this pseudo-op
36759679 550 Integer arg to pass to the function. */
252b5132
RH		 551const pseudo_typeS md_pseudo_table[] =
552{
553 {"data1", s_data1, 0},
554 {"data2", s_data2, 0},
555 {"bss", s_bss, 0},
556 {"even", s_even, 0},
557 {"skip", s_space, 0},
558 {"proc", s_proc, 0},
559#if defined (TE_SUN3) || defined (OBJ_ELF)
560 {"align", s_align_bytes, 0},
561#endif
562#ifdef OBJ_ELF
563 {"swbeg", s_ignore, 0},
564#endif
565 {"extend", float_cons, 'x'},
566 {"ldouble", float_cons, 'x'},
567
568 /* The following pseudo-ops are supported for MRI compatibility. */
569 {"chip", s_chip, 0},
570 {"comline", s_space, 1},
571 {"fopt", s_fopt, 0},
572 {"mask2", s_ignore, 0},
573 {"opt", s_opt, 0},
574 {"reg", s_reg, 0},
575 {"restore", s_restore, 0},
576 {"save", s_save, 0},
577
578 {"if", s_mri_if, 0},
579 {"if.b", s_mri_if, 'b'},
580 {"if.w", s_mri_if, 'w'},
581 {"if.l", s_mri_if, 'l'},
582 {"else", s_mri_else, 0},
583 {"else.s", s_mri_else, 's'},
584 {"else.l", s_mri_else, 'l'},
585 {"endi", s_mri_endi, 0},
586 {"break", s_mri_break, 0},
587 {"break.s", s_mri_break, 's'},
588 {"break.l", s_mri_break, 'l'},
589 {"next", s_mri_next, 0},
590 {"next.s", s_mri_next, 's'},
591 {"next.l", s_mri_next, 'l'},
592 {"for", s_mri_for, 0},
593 {"for.b", s_mri_for, 'b'},
594 {"for.w", s_mri_for, 'w'},
595 {"for.l", s_mri_for, 'l'},
596 {"endf", s_mri_endf, 0},
597 {"repeat", s_mri_repeat, 0},
598 {"until", s_mri_until, 0},
599 {"until.b", s_mri_until, 'b'},
600 {"until.w", s_mri_until, 'w'},
601 {"until.l", s_mri_until, 'l'},
602 {"while", s_mri_while, 0},
603 {"while.b", s_mri_while, 'b'},
604 {"while.w", s_mri_while, 'w'},
605 {"while.l", s_mri_while, 'l'},
606 {"endw", s_mri_endw, 0},
607
608 {0, 0, 0}
609};
610
252b5132
RH		 611/* The mote pseudo ops are put into the opcode table, since they
612 don't start with a . they look like opcodes to gas.
613 */
614
615#ifdef M68KCOFF
616extern void obj_coff_section PARAMS ((int));
617#endif
618
5a38dc70 619const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 620{
621
622 {"dcl", cons, 4},
623 {"dc", cons, 2},
624 {"dcw", cons, 2},
625 {"dcb", cons, 1},
626
627 {"dsl", s_space, 4},
628 {"ds", s_space, 2},
629 {"dsw", s_space, 2},
630 {"dsb", s_space, 1},
631
632 {"xdef", s_globl, 0},
633#ifdef OBJ_ELF
634 {"align", s_align_bytes, 0},
635#else
636 {"align", s_align_ptwo, 0},
637#endif
638#ifdef M68KCOFF
639 {"sect", obj_coff_section, 0},
640 {"section", obj_coff_section, 0},
641#endif
642 {0, 0, 0}
643};
644
645#define issbyte(x) ((x)>=-128 && (x)<=127)
646#define isubyte(x) ((x)>=0 && (x)<=255)
647#define issword(x) ((x)>=-32768 && (x)<=32767)
648#define isuword(x) ((x)>=0 && (x)<=65535)
649
650#define isbyte(x) ((x)>= -255 && (x)<=255)
651#define isword(x) ((x)>=-65536 && (x)<=65535)
652#define islong(x) (1)
653
654extern char *input_line_pointer;
655
252b5132
RH		 656static char notend_table[256];
657static char alt_notend_table[256];
658#define notend(s) \
659 (! (notend_table[(unsigned char) *s] \
660 || (*s == ':' \
661 && alt_notend_table[(unsigned char) s[1]])))
662
663#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
664
665#ifdef NO_PCREL_RELOCS
666
667int
668make_pcrel_absolute(fixP, add_number)
669 fixS *fixP;
670 long *add_number;
671{
672 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
673
36759679
NC		 674 /* Rewrite the PC relative instructions to absolute address ones.
675 these are rumoured to be faster, and the apollo linker refuses
676 to deal with the PC relative relocations. */
677 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
252b5132 678 {
36759679
NC		 679 if (flag_keep_pcrel)
680 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 681 opcode[0] = 0x4e;
682 opcode[1] = 0xf9;
683 }
36759679 684 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
252b5132 685 {
36759679
NC		 686 if (flag_keep_pcrel)
687 as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
252b5132
RH		 688 opcode[0] = 0x4e;
689 opcode[1] = 0xb9;
690 }
691 else
692 as_fatal (_("Unknown PC relative instruction"));
693 *add_number -= 4;
694 return 0;
695}
696
697#endif /* NO_PCREL_RELOCS */
698
699short
700tc_coff_fix2rtype (fixP)
701 fixS *fixP;
702{
703 if (fixP->fx_tcbit && fixP->fx_size == 4)
704 return R_RELLONG_NEG;
705#ifdef NO_PCREL_RELOCS
706 know (fixP->fx_pcrel == 0);
707 return (fixP->fx_size == 1 ? R_RELBYTE
708 : fixP->fx_size == 2 ? R_DIR16
709 : R_DIR32);
710#else
711 return (fixP->fx_pcrel ?
712 (fixP->fx_size == 1 ? R_PCRBYTE :
713 fixP->fx_size == 2 ? R_PCRWORD :
714 R_PCRLONG) :
715 (fixP->fx_size == 1 ? R_RELBYTE :
716 fixP->fx_size == 2 ? R_RELWORD :
717 R_RELLONG));
718#endif
719}
720
721#endif
722
723#ifdef OBJ_ELF
724
c801568a
AM		 725/* Return zero if the reference to SYMBOL from within the same segment may
726 be relaxed. */
727
728/* On an ELF system, we can't relax an externally visible symbol,
729 because it may be overridden by a shared library. However, if
730 TARGET_OS is "elf", then we presume that we are assembling for an
731 embedded system, in which case we don't have to worry about shared
732 libraries, and we can relax any external sym. */
733
734#define relaxable_symbol(symbol) \
735 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
736 || S_IS_WEAK (symbol)))
737
252b5132
RH		 738/* Compute the relocation code for a fixup of SIZE bytes, using pc
739 relative relocation if PCREL is non-zero. PIC says whether a special
740 pic relocation was requested. */
741
742static bfd_reloc_code_real_type get_reloc_code
743 PARAMS ((int, int, enum pic_relocation));
744
745static bfd_reloc_code_real_type
746get_reloc_code (size, pcrel, pic)
747 int size;
748 int pcrel;
749 enum pic_relocation pic;
750{
751 switch (pic)
752 {
753 case pic_got_pcrel:
754 switch (size)
755 {
756 case 1:
757 return BFD_RELOC_8_GOT_PCREL;
758 case 2:
759 return BFD_RELOC_16_GOT_PCREL;
760 case 4:
761 return BFD_RELOC_32_GOT_PCREL;
762 }
763 break;
764
765 case pic_got_off:
766 switch (size)
767 {
768 case 1:
769 return BFD_RELOC_8_GOTOFF;
770 case 2:
771 return BFD_RELOC_16_GOTOFF;
772 case 4:
773 return BFD_RELOC_32_GOTOFF;
774 }
775 break;
776
777 case pic_plt_pcrel:
778 switch (size)
779 {
780 case 1:
781 return BFD_RELOC_8_PLT_PCREL;
782 case 2:
783 return BFD_RELOC_16_PLT_PCREL;
784 case 4:
785 return BFD_RELOC_32_PLT_PCREL;
786 }
787 break;
788
789 case pic_plt_off:
790 switch (size)
791 {
792 case 1:
793 return BFD_RELOC_8_PLTOFF;
794 case 2:
795 return BFD_RELOC_16_PLTOFF;
796 case 4:
797 return BFD_RELOC_32_PLTOFF;
798 }
799 break;
800
801 case pic_none:
802 if (pcrel)
803 {
804 switch (size)
805 {
806 case 1:
807 return BFD_RELOC_8_PCREL;
808 case 2:
809 return BFD_RELOC_16_PCREL;
810 case 4:
811 return BFD_RELOC_32_PCREL;
812 }
813 }
814 else
815 {
816 switch (size)
817 {
818 case 1:
819 return BFD_RELOC_8;
820 case 2:
821 return BFD_RELOC_16;
822 case 4:
823 return BFD_RELOC_32;
824 }
825 }
826 }
827
828 if (pcrel)
829 {
830 if (pic == pic_none)
831 as_bad (_("Can not do %d byte pc-relative relocation"), size);
832 else
833 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
834 }
835 else
836 {
837 if (pic == pic_none)
838 as_bad (_("Can not do %d byte relocation"), size);
839 else
840 as_bad (_("Can not do %d byte pic relocation"), size);
841 }
842
843 return BFD_RELOC_NONE;
844}
845
846/* Here we decide which fixups can be adjusted to make them relative
847 to the beginning of the section instead of the symbol. Basically
848 we need to make sure that the dynamic relocations are done
849 correctly, so in some cases we force the original symbol to be
850 used. */
851int
852tc_m68k_fix_adjustable (fixP)
853 fixS *fixP;
854{
36759679 855 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 856 switch (fixP->fx_r_type)
857 {
858 case BFD_RELOC_8_GOT_PCREL:
859 case BFD_RELOC_16_GOT_PCREL:
860 case BFD_RELOC_32_GOT_PCREL:
861 case BFD_RELOC_8_GOTOFF:
862 case BFD_RELOC_16_GOTOFF:
863 case BFD_RELOC_32_GOTOFF:
864 case BFD_RELOC_8_PLT_PCREL:
865 case BFD_RELOC_16_PLT_PCREL:
866 case BFD_RELOC_32_PLT_PCREL:
867 case BFD_RELOC_8_PLTOFF:
868 case BFD_RELOC_16_PLTOFF:
869 case BFD_RELOC_32_PLTOFF:
870 return 0;
871
872 case BFD_RELOC_VTABLE_INHERIT:
873 case BFD_RELOC_VTABLE_ENTRY:
874 return 0;
875
876 default:
877 return 1;
878 }
879}
880
881#else /* !OBJ_ELF */
882
883#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
884
c801568a
AM		 885#define relaxable_symbol(symbol) 1
886
252b5132
RH		 887#endif /* OBJ_ELF */
888
889#ifdef BFD_ASSEMBLER
890
891arelent *
892tc_gen_reloc (section, fixp)
f1f5ef86 893 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 894 fixS *fixp;
895{
896 arelent *reloc;
897 bfd_reloc_code_real_type code;
898
8ec6253e
NC		 899 /* If the tcbit is set, then this was a fixup of a negative value
900 that was never resolved. We do not have a reloc to handle this,
901 so just return. We assume that other code will have detected this
902 situation and produced a helpful error message, so we just tell the
903 user that the reloc cannot be produced. */
252b5132 904 if (fixp->fx_tcbit)
8ec6253e
NC		 905 {
906 if (fixp->fx_addsy)
b091f402
AM		 907 as_bad_where (fixp->fx_file, fixp->fx_line,
908 _("Unable to produce reloc against symbol '%s'"),
909 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 910 return NULL;
911 }
252b5132
RH		 912
913 if (fixp->fx_r_type != BFD_RELOC_NONE)
914 {
915 code = fixp->fx_r_type;
916
917 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
918 that fixup_segment converted a non-PC relative reloc into a
919 PC relative reloc. In such a case, we need to convert the
920 reloc code. */
921 if (fixp->fx_pcrel)
922 {
923 switch (code)
924 {
925 case BFD_RELOC_8:
926 code = BFD_RELOC_8_PCREL;
927 break;
928 case BFD_RELOC_16:
929 code = BFD_RELOC_16_PCREL;
930 break;
931 case BFD_RELOC_32:
932 code = BFD_RELOC_32_PCREL;
933 break;
934 case BFD_RELOC_8_PCREL:
935 case BFD_RELOC_16_PCREL:
936 case BFD_RELOC_32_PCREL:
937 case BFD_RELOC_8_GOT_PCREL:
938 case BFD_RELOC_16_GOT_PCREL:
939 case BFD_RELOC_32_GOT_PCREL:
940 case BFD_RELOC_8_GOTOFF:
941 case BFD_RELOC_16_GOTOFF:
942 case BFD_RELOC_32_GOTOFF:
943 case BFD_RELOC_8_PLT_PCREL:
944 case BFD_RELOC_16_PLT_PCREL:
945 case BFD_RELOC_32_PLT_PCREL:
946 case BFD_RELOC_8_PLTOFF:
947 case BFD_RELOC_16_PLTOFF:
948 case BFD_RELOC_32_PLTOFF:
949 break;
950 default:
951 as_bad_where (fixp->fx_file, fixp->fx_line,
952 _("Cannot make %s relocation PC relative"),
953 bfd_get_reloc_code_name (code));
954 }
955 }
956 }
957 else
958 {
959#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
960 switch (F (fixp->fx_size, fixp->fx_pcrel))
961 {
962#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
963 MAP (1, 0, BFD_RELOC_8);
964 MAP (2, 0, BFD_RELOC_16);
965 MAP (4, 0, BFD_RELOC_32);
966 MAP (1, 1, BFD_RELOC_8_PCREL);
967 MAP (2, 1, BFD_RELOC_16_PCREL);
968 MAP (4, 1, BFD_RELOC_32_PCREL);
969 default:
970 abort ();
971 }
972 }
973#undef F
974#undef MAP
975
976 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 977 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
978 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 979 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
980#ifndef OBJ_ELF
981 if (fixp->fx_pcrel)
982 reloc->addend = fixp->fx_addnumber;
983 else
984 reloc->addend = 0;
985#else
986 if (!fixp->fx_pcrel)
987 reloc->addend = fixp->fx_addnumber;
988 else
989 reloc->addend = (section->vma
8390138c
AS		 990 /* Explicit sign extension in case char is
991 unsigned. */
992 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 993 + fixp->fx_addnumber
994 + md_pcrel_from (fixp));
995#endif
996
997 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
998 assert (reloc->howto != 0);
999
1000 return reloc;
1001}
1002
1003#endif /* BFD_ASSEMBLER */
1004
252b5132
RH		 1005/* Handle of the OPCODE hash table. NULL means any use before
1006 m68k_ip_begin() will crash. */
1007static struct hash_control *op_hash;
1008\f
1009/* Assemble an m68k instruction. */
1010
1011static void
1012m68k_ip (instring)
1013 char *instring;
1014{
1015 register char *p;
1016 register struct m68k_op *opP;
1017 register const struct m68k_incant *opcode;
1018 register const char *s;
1019 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1020 char *pdot, *pdotmove;
1021 enum m68k_size siz1, siz2;
1022 char c;
1023 int losing;
1024 int opsfound;
1025 LITTLENUM_TYPE words[6];
1026 LITTLENUM_TYPE *wordp;
1027 unsigned long ok_arch = 0;
1028
1029 if (*instring == ' ')
36759679 1030 instring++; /* Skip leading whitespace. */
252b5132
RH		 1031
1032 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1033 or exactly 1 space. */
252b5132
RH		 1034 pdot = 0;
1035 for (p = instring; *p != '\0'; p++)
1036 {
1037 if (*p == ' ')
1038 break;
1039 if (*p == '.')
1040 pdot = p;
1041 }
1042
1043 if (p == instring)
1044 {
1045 the_ins.error = _("No operator");
1046 return;
1047 }
1048
1049 /* p now points to the end of the opcode name, probably whitespace.
1050 Make sure the name is null terminated by clobbering the
1051 whitespace, look it up in the hash table, then fix it back.
1052 Remove a dot, first, since the opcode tables have none. */
1053 if (pdot != NULL)
1054 {
1055 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1056 *pdotmove = pdotmove[1];
1057 p--;
1058 }
1059
1060 c = *p;
1061 *p = '\0';
1062 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1063 *p = c;
1064
1065 if (pdot != NULL)
1066 {
1067 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1068 *pdotmove = pdotmove[-1];
1069 *pdot = '.';
1070 ++p;
1071 }
1072
1073 if (opcode == NULL)
1074 {
1075 the_ins.error = _("Unknown operator");
1076 return;
1077 }
1078
36759679 1079 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1080 while (*p == ' ')
1081 ++p;
1082
1083 if (opcode->m_operands == 0)
1084 {
1085 char *old = input_line_pointer;
1086 *old = '\n';
1087 input_line_pointer = p;
36759679 1088 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1089 mote_pseudo_table[opcode->m_opnum].poc_handler
1090 (mote_pseudo_table[opcode->m_opnum].poc_val);
1091 input_line_pointer = old;
1092 *old = 0;
1093
1094 return;
1095 }
1096
1097 if (flag_mri && opcode->m_opnum == 0)
1098 {
1099 /* In MRI mode, random garbage is allowed after an instruction
1100 which accepts no operands. */
1101 the_ins.args = opcode->m_operands;
1102 the_ins.numargs = opcode->m_opnum;
1103 the_ins.numo = opcode->m_codenum;
1104 the_ins.opcode[0] = getone (opcode);
1105 the_ins.opcode[1] = gettwo (opcode);
1106 return;
1107 }
1108
1109 for (opP = &the_ins.operands[0]; *p; opP++)
1110 {
1111 p = crack_operand (p, opP);
1112
1113 if (opP->error)
1114 {
1115 the_ins.error = opP->error;
1116 return;
1117 }
1118 }
1119
1120 opsfound = opP - &the_ins.operands[0];
1121
1122 /* This ugly hack is to support the floating pt opcodes in their
1123 standard form. Essentially, we fake a first enty of type COP#1 */
1124 if (opcode->m_operands[0] == 'I')
1125 {
1126 int n;
1127
1128 for (n = opsfound; n > 0; --n)
1129 the_ins.operands[n] = the_ins.operands[n - 1];
1130
1131 memset ((char *) (&the_ins.operands[0]), '\0',
1132 sizeof (the_ins.operands[0]));
1133 the_ins.operands[0].mode = CONTROL;
1134 the_ins.operands[0].reg = m68k_float_copnum;
1135 opsfound++;
1136 }
1137
36759679 1138 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1139 for (losing = 0;;)
1140 {
1141 /* If we didn't get the right number of ops, or we have no
92774660 1142 common model with this pattern then reject this pattern. */
252b5132
RH		 1143
1144 ok_arch |= opcode->m_arch;
1145 if (opsfound != opcode->m_opnum
1146 || ((opcode->m_arch & current_architecture) == 0))
1147 ++losing;
1148 else
1149 {
1150 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1151 *s && !losing;
1152 s += 2, opP++)
1153 {
1154 /* Warning: this switch is huge! */
1155 /* I've tried to organize the cases into this order:
1156 non-alpha first, then alpha by letter. Lower-case
1157 goes directly before uppercase counterpart. */
1158 /* Code with multiple case ...: gets sorted by the lowest
1159 case ... it belongs to. I hope this makes sense. */
1160 switch (*s)
1161 {
1162 case '!':
1163 switch (opP->mode)
1164 {
1165 case IMMED:
1166 case DREG:
1167 case AREG:
1168 case FPREG:
1169 case CONTROL:
1170 case AINC:
1171 case ADEC:
1172 case REGLST:
1173 losing++;
1174 break;
1175 default:
1176 break;
1177 }
1178 break;
1179
1180 case '<':
1181 switch (opP->mode)
1182 {
1183 case DREG:
1184 case AREG:
1185 case FPREG:
1186 case CONTROL:
1187 case IMMED:
1188 case ADEC:
1189 case REGLST:
1190 losing++;
1191 break;
1192 default:
1193 break;
1194 }
1195 break;
1196
1197 case '>':
1198 switch (opP->mode)
1199 {
1200 case DREG:
1201 case AREG:
1202 case FPREG:
1203 case CONTROL:
1204 case IMMED:
1205 case AINC:
1206 case REGLST:
1207 losing++;
1208 break;
1209 case ABSL:
1210 break;
1211 default:
1212 if (opP->reg == PC
1213 || opP->reg == ZPC)
1214 losing++;
1215 break;
1216 }
1217 break;
1218
1219 case 'm':
1220 switch (opP->mode)
1221 {
1222 case DREG:
1223 case AREG:
1224 case AINDR:
1225 case AINC:
1226 case ADEC:
1227 break;
1228 default:
1229 losing++;
1230 }
8a104df9 1231 break;
252b5132
RH		 1232
1233 case 'n':
1234 switch (opP->mode)
1235 {
1236 case DISP:
1237 break;
1238 default:
1239 losing++;
1240 }
8a104df9 1241 break;
252b5132
RH		 1242
1243 case 'o':
1244 switch (opP->mode)
1245 {
1246 case BASE:
1247 case ABSL:
1248 case IMMED:
1249 break;
1250 default:
1251 losing++;
1252 }
8a104df9 1253 break;
252b5132
RH		 1254
1255 case 'p':
1256 switch (opP->mode)
1257 {
1258 case DREG:
1259 case AREG:
1260 case AINDR:
1261 case AINC:
1262 case ADEC:
1263 break;
1264 case DISP:
1265 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1266 losing++;
252b5132
RH		 1267 break;
1268 default:
1269 losing++;
1270 }
8a104df9 1271 break;
252b5132
RH		 1272
1273 case 'q':
1274 switch (opP->mode)
1275 {
1276 case DREG:
1277 case AINDR:
1278 case AINC:
1279 case ADEC:
1280 break;
1281 case DISP:
1282 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1283 losing++;
252b5132
RH		 1284 break;
1285 default:
1286 losing++;
1287 break;
1288 }
8a104df9 1289 break;
252b5132
RH		 1290
1291 case 'v':
1292 switch (opP->mode)
1293 {
1294 case DREG:
1295 case AINDR:
1296 case AINC:
1297 case ADEC:
1298 case ABSL:
1299 break;
1300 case DISP:
1301 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1302 losing++;
252b5132
RH		 1303 break;
1304 default:
1305 losing++;
1306 break;
1307 }
1308 break;
1309
1310 case '#':
1311 if (opP->mode != IMMED)
1312 losing++;
1313 else if (s[1] == 'b'
1314 && ! isvar (&opP->disp)
1315 && (opP->disp.exp.X_op != O_constant
1316 || ! isbyte (opP->disp.exp.X_add_number)))
1317 losing++;
1318 else if (s[1] == 'B'
1319 && ! isvar (&opP->disp)
1320 && (opP->disp.exp.X_op != O_constant
1321 || ! issbyte (opP->disp.exp.X_add_number)))
1322 losing++;
1323 else if (s[1] == 'w'
1324 && ! isvar (&opP->disp)
1325 && (opP->disp.exp.X_op != O_constant
1326 || ! isword (opP->disp.exp.X_add_number)))
1327 losing++;
1328 else if (s[1] == 'W'
1329 && ! isvar (&opP->disp)
1330 && (opP->disp.exp.X_op != O_constant
1331 || ! issword (opP->disp.exp.X_add_number)))
1332 losing++;
1333 break;
1334
1335 case '^':
1336 case 'T':
1337 if (opP->mode != IMMED)
1338 losing++;
1339 break;
1340
1341 case '$':
1342 if (opP->mode == AREG
1343 || opP->mode == CONTROL
1344 || opP->mode == FPREG
1345 || opP->mode == IMMED
1346 || opP->mode == REGLST
1347 || (opP->mode != ABSL
1348 && (opP->reg == PC
1349 || opP->reg == ZPC)))
1350 losing++;
1351 break;
1352
1353 case '%':
1354 if (opP->mode == CONTROL
1355 || opP->mode == FPREG
1356 || opP->mode == REGLST
1357 || opP->mode == IMMED
1358 || (opP->mode != ABSL
1359 && (opP->reg == PC
1360 || opP->reg == ZPC)))
1361 losing++;
1362 break;
1363
1364 case '&':
1365 switch (opP->mode)
1366 {
1367 case DREG:
1368 case AREG:
1369 case FPREG:
1370 case CONTROL:
1371 case IMMED:
1372 case AINC:
1373 case ADEC:
1374 case REGLST:
1375 losing++;
1376 break;
1377 case ABSL:
1378 break;
1379 default:
1380 if (opP->reg == PC
1381 || opP->reg == ZPC)
1382 losing++;
1383 break;
1384 }
1385 break;
1386
1387 case '*':
1388 if (opP->mode == CONTROL
1389 || opP->mode == FPREG
1390 || opP->mode == REGLST)
1391 losing++;
1392 break;
1393
1394 case '+':
1395 if (opP->mode != AINC)
1396 losing++;
1397 break;
1398
1399 case '-':
1400 if (opP->mode != ADEC)
1401 losing++;
1402 break;
1403
1404 case '/':
1405 switch (opP->mode)
1406 {
1407 case AREG:
1408 case CONTROL:
1409 case FPREG:
1410 case AINC:
1411 case ADEC:
1412 case IMMED:
1413 case REGLST:
1414 losing++;
1415 break;
1416 default:
1417 break;
1418 }
1419 break;
1420
1421 case ';':
1422 switch (opP->mode)
1423 {
1424 case AREG:
1425 case CONTROL:
1426 case FPREG:
1427 case REGLST:
1428 losing++;
1429 break;
1430 default:
1431 break;
1432 }
1433 break;
1434
1435 case '?':
1436 switch (opP->mode)
1437 {
1438 case AREG:
1439 case CONTROL:
1440 case FPREG:
1441 case AINC:
1442 case ADEC:
1443 case IMMED:
1444 case REGLST:
1445 losing++;
1446 break;
1447 case ABSL:
1448 break;
1449 default:
1450 if (opP->reg == PC || opP->reg == ZPC)
1451 losing++;
1452 break;
1453 }
1454 break;
1455
1456 case '@':
1457 switch (opP->mode)
1458 {
1459 case AREG:
1460 case CONTROL:
1461 case FPREG:
1462 case IMMED:
1463 case REGLST:
1464 losing++;
1465 break;
1466 default:
1467 break;
1468 }
1469 break;
1470
1471 case '~': /* For now! (JF FOO is this right?) */
1472 switch (opP->mode)
1473 {
1474 case DREG:
1475 case AREG:
1476 case CONTROL:
1477 case FPREG:
1478 case IMMED:
1479 case REGLST:
1480 losing++;
1481 break;
1482 case ABSL:
1483 break;
1484 default:
1485 if (opP->reg == PC
1486 || opP->reg == ZPC)
1487 losing++;
1488 break;
1489 }
1490 break;
1491
1492 case '3':
1493 if (opP->mode != CONTROL
1494 || (opP->reg != TT0 && opP->reg != TT1))
1495 losing++;
1496 break;
1497
1498 case 'A':
1499 if (opP->mode != AREG)
1500 losing++;
1501 break;
1502
1503 case 'a':
1504 if (opP->mode != AINDR)
1505 ++losing;
1506 break;
1507
1508 case 'B': /* FOO */
1509 if (opP->mode != ABSL
1510 || (flag_long_jumps
1511 && strncmp (instring, "jbsr", 4) == 0))
1512 losing++;
1513 break;
1514
3e602632
NC		 1515 case 'b':
1516 switch (opP->mode)
1517 {
1518 case IMMED:
1519 case ABSL:
1520 case AREG:
1521 case FPREG:
1522 case CONTROL:
1523 case POST:
1524 case PRE:
1525 case REGLST:
1526 losing++;
1527 break;
1528 default:
1529 break;
1530 }
1531 break;
1532
252b5132
RH		 1533 case 'C':
1534 if (opP->mode != CONTROL || opP->reg != CCR)
1535 losing++;
1536 break;
1537
1538 case 'd':
1539 if (opP->mode != DISP
1540 || opP->reg < ADDR0
1541 || opP->reg > ADDR7)
1542 losing++;
1543 break;
1544
1545 case 'D':
1546 if (opP->mode != DREG)
1547 losing++;
1548 break;
1549
6da466c7
ILT		 1550 case 'E':
1551 if (opP->reg != ACC)
1552 losing++;
1553 break;
1554
252b5132
RH		 1555 case 'F':
1556 if (opP->mode != FPREG)
1557 losing++;
1558 break;
1559
6da466c7
ILT		 1560 case 'G':
1561 if (opP->reg != MACSR)
1562 losing++;
1563 break;
1564
1565 case 'H':
1566 if (opP->reg != MASK)
1567 losing++;
1568 break;
1569
252b5132
RH		 1570 case 'I':
1571 if (opP->mode != CONTROL
1572 || opP->reg < COP0
1573 || opP->reg > COP7)
1574 losing++;
1575 break;
1576
1577 case 'J':
1578 if (opP->mode != CONTROL
1579 || opP->reg < USP
1580 || opP->reg > last_movec_reg)
1581 losing++;
1582 else
1583 {
1584 const enum m68k_register *rp;
1585 for (rp = control_regs; *rp; rp++)
1586 if (*rp == opP->reg)
1587 break;
1588 if (*rp == 0)
1589 losing++;
1590 }
1591 break;
1592
1593 case 'k':
1594 if (opP->mode != IMMED)
1595 losing++;
1596 break;
1597
1598 case 'l':
1599 case 'L':
1600 if (opP->mode == DREG
1601 || opP->mode == AREG
1602 || opP->mode == FPREG)
1603 {
1604 if (s[1] == '8')
1605 losing++;
1606 else
1607 {
1608 switch (opP->mode)
1609 {
1610 case DREG:
1611 opP->mask = 1 << (opP->reg - DATA0);
1612 break;
1613 case AREG:
1614 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1615 break;
1616 case FPREG:
1617 opP->mask = 1 << (opP->reg - FP0 + 16);
1618 break;
1619 default:
1620 abort ();
1621 }
1622 opP->mode = REGLST;
1623 }
1624 }
1625 else if (opP->mode == CONTROL)
1626 {
1627 if (s[1] != '8')
1628 losing++;
1629 else
1630 {
1631 switch (opP->reg)
1632 {
1633 case FPI:
1634 opP->mask = 1 << 24;
1635 break;
1636 case FPS:
1637 opP->mask = 1 << 25;
1638 break;
1639 case FPC:
1640 opP->mask = 1 << 26;
1641 break;
1642 default:
1643 losing++;
1644 break;
1645 }
1646 opP->mode = REGLST;
1647 }
1648 }
1649 else if (opP->mode != REGLST)
1650 losing++;
1651 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1652 losing++;
1653 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1654 losing++;
1655 break;
1656
1657 case 'M':
1658 if (opP->mode != IMMED)
1659 losing++;
1660 else if (opP->disp.exp.X_op != O_constant
1661 || ! issbyte (opP->disp.exp.X_add_number))
1662 losing++;
1663 else if (! m68k_quick
1664 && instring[3] != 'q'
1665 && instring[4] != 'q')
1666 losing++;
1667 break;
1668
1669 case 'O':
1670 if (opP->mode != DREG
1671 && opP->mode != IMMED
1672 && opP->mode != ABSL)
1673 losing++;
1674 break;
1675
1676 case 'Q':
1677 if (opP->mode != IMMED)
1678 losing++;
1679 else if (opP->disp.exp.X_op != O_constant
1680 || opP->disp.exp.X_add_number < 1
1681 || opP->disp.exp.X_add_number > 8)
1682 losing++;
1683 else if (! m68k_quick
1684 && (strncmp (instring, "add", 3) == 0
1685 || strncmp (instring, "sub", 3) == 0)
1686 && instring[3] != 'q')
1687 losing++;
1688 break;
1689
1690 case 'R':
1691 if (opP->mode != DREG && opP->mode != AREG)
1692 losing++;
1693 break;
1694
1695 case 'r':
1696 if (opP->mode != AINDR
1697 && (opP->mode != BASE
1698 || (opP->reg != 0
1699 && opP->reg != ZADDR0)
1700 || opP->disp.exp.X_op != O_absent
1701 || ((opP->index.reg < DATA0
1702 || opP->index.reg > DATA7)
1703 && (opP->index.reg < ADDR0
1704 || opP->index.reg > ADDR7))
1705 || opP->index.size != SIZE_UNSPEC
1706 || opP->index.scale != 1))
1707 losing++;
1708 break;
1709
1710 case 's':
1711 if (opP->mode != CONTROL
1712 || ! (opP->reg == FPI
1713 || opP->reg == FPS
1714 || opP->reg == FPC))
1715 losing++;
1716 break;
1717
1718 case 'S':
1719 if (opP->mode != CONTROL || opP->reg != SR)
1720 losing++;
1721 break;
1722
1723 case 't':
1724 if (opP->mode != IMMED)
1725 losing++;
1726 else if (opP->disp.exp.X_op != O_constant
1727 || opP->disp.exp.X_add_number < 0
1728 || opP->disp.exp.X_add_number > 7)
1729 losing++;
1730 break;
1731
1732 case 'U':
1733 if (opP->mode != CONTROL || opP->reg != USP)
1734 losing++;
1735 break;
1736
3e602632
NC		 1737 case 'x':
1738 if (opP->mode != IMMED)
1739 losing++;
1740 else if (opP->disp.exp.X_op != O_constant
1741 || opP->disp.exp.X_add_number < -1
1742 || opP->disp.exp.X_add_number > 7
1743 || opP->disp.exp.X_add_number == 0)
1744 losing++;
1745 break;
1746
252b5132
RH		 1747 /* JF these are out of order. We could put them
1748 in order if we were willing to put up with
1749 bunches of #ifdef m68851s in the code.
1750
1751 Don't forget that you need these operands
1752 to use 68030 MMU instructions. */
1753#ifndef NO_68851
36759679 1754 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1755 case '|':
1756 if (opP->mode == CONTROL
1757 || opP->mode == FPREG
1758 || opP->mode == DREG
1759 || opP->mode == AREG
1760 || opP->mode == REGLST)
1761 losing++;
1762 /* We should accept immediate operands, but they
1763 supposedly have to be quad word, and we don't
1764 handle that. I would like to see what a Motorola
1765 assembler does before doing something here. */
1766 if (opP->mode == IMMED)
1767 losing++;
1768 break;
1769
1770 case 'f':
1771 if (opP->mode != CONTROL
1772 || (opP->reg != SFC && opP->reg != DFC))
1773 losing++;
1774 break;
1775
1776 case '0':
1777 if (opP->mode != CONTROL || opP->reg != TC)
1778 losing++;
1779 break;
1780
1781 case '1':
1782 if (opP->mode != CONTROL || opP->reg != AC)
1783 losing++;
1784 break;
1785
1786 case '2':
1787 if (opP->mode != CONTROL
1788 || (opP->reg != CAL
1789 && opP->reg != VAL
1790 && opP->reg != SCC))
1791 losing++;
1792 break;
1793
1794 case 'V':
1795 if (opP->mode != CONTROL
1796 || opP->reg != VAL)
1797 losing++;
1798 break;
1799
1800 case 'W':
1801 if (opP->mode != CONTROL
1802 || (opP->reg != DRP
1803 && opP->reg != SRP
1804 && opP->reg != CRP))
1805 losing++;
1806 break;
1807
3e602632
NC		 1808 case 'w':
1809 switch (opP->mode)
1810 {
1811 case IMMED:
1812 case ABSL:
1813 case AREG:
1814 case DREG:
1815 case FPREG:
1816 case CONTROL:
1817 case POST:
1818 case PRE:
1819 case REGLST:
1820 losing++;
1821 break;
1822 default:
1823 break;
1824 }
1825 break;
1826
252b5132
RH		 1827 case 'X':
1828 if (opP->mode != CONTROL
1829 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1830 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1831 losing++;
1832 break;
1833
1834 case 'Y':
1835 if (opP->mode != CONTROL || opP->reg != PSR)
1836 losing++;
1837 break;
1838
1839 case 'Z':
1840 if (opP->mode != CONTROL || opP->reg != PCSR)
1841 losing++;
1842 break;
1843#endif
1844 case 'c':
1845 if (opP->mode != CONTROL
1846 || (opP->reg != NC
1847 && opP->reg != IC
1848 && opP->reg != DC
1849 && opP->reg != BC))
36759679 1850 losing++;
252b5132
RH		 1851 break;
1852
1853 case '_':
1854 if (opP->mode != ABSL)
1855 ++losing;
1856 break;
1857
6da466c7
ILT		 1858 case 'u':
1859 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1860 losing++;
1861 /* FIXME: kludge instead of fixing parser:
1862 upper/lower registers are *not* CONTROL
92774660 1863 registers, but ordinary ones. */
6da466c7
ILT		 1864 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1865 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1866 opP->mode = DREG;
1867 else
1868 opP->mode = AREG;
1869 break;
1870
3e602632
NC		 1871 case 'y':
1872 if (!(opP->mode == AINDR
1873 || (opP->mode == DISP && !(opP->reg == PC ||
1874 opP->reg == ZPC))))
1875 losing++;
1876 break;
1877
1878 case 'z':
1879 if (!(opP->mode == AINDR || opP->mode == DISP))
1880 losing++;
1881 break;
1882
252b5132
RH		 1883 default:
1884 abort ();
36759679 1885 }
252b5132
RH		 1886
1887 if (losing)
1888 break;
36759679
NC		 1889 }
1890 }
252b5132
RH		 1891
1892 if (!losing)
36759679 1893 break;
252b5132
RH		 1894
1895 opcode = opcode->m_next;
1896
1897 if (!opcode)
1898 {
1899 if (ok_arch
1900 && !(ok_arch & current_architecture))
1901 {
1902 char buf[200], *cp;
1903
1904 strcpy (buf,
1905 _("invalid instruction for this architecture; needs "));
1906 cp = buf + strlen (buf);
1907 switch (ok_arch)
1908 {
3e602632
NC		 1909 case cfloat:
1910 strcpy (cp, _("ColdFire fpu (cfv4e)"));
1911 break;
252b5132
RH		 1912 case mfloat:
1913 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1914 break;
1915 case mmmu:
1916 strcpy (cp, _("mmu (68030 or 68851)"));
1917 break;
1918 case m68020up:
1919 strcpy (cp, _("68020 or higher"));
1920 break;
1921 case m68000up:
1922 strcpy (cp, _("68000 or higher"));
1923 break;
1924 case m68010up:
1925 strcpy (cp, _("68010 or higher"));
1926 break;
1927 default:
1928 {
1929 int got_one = 0, idx;
8fce3f5e
AM		 1930 for (idx = 0;
1931 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1932 idx++)
1933 {
1934 if ((archs[idx].arch & ok_arch)
1935 && ! archs[idx].alias)
1936 {
1937 if (got_one)
1938 {
1939 strcpy (cp, " or ");
1940 cp += strlen (cp);
1941 }
1942 got_one = 1;
1943 strcpy (cp, archs[idx].name);
1944 cp += strlen (cp);
1945 }
1946 }
1947 }
1948 }
1949 cp = xmalloc (strlen (buf) + 1);
1950 strcpy (cp, buf);
1951 the_ins.error = cp;
1952 }
1953 else
1954 the_ins.error = _("operands mismatch");
1955 return;
36759679 1956 }
252b5132
RH		 1957
1958 losing = 0;
1959 }
1960
36759679 1961 /* Now assemble it. */
252b5132
RH		 1962 the_ins.args = opcode->m_operands;
1963 the_ins.numargs = opcode->m_opnum;
1964 the_ins.numo = opcode->m_codenum;
1965 the_ins.opcode[0] = getone (opcode);
1966 the_ins.opcode[1] = gettwo (opcode);
1967
1968 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1969 {
1970 /* This switch is a doozy.
1971 Watch the first step; its a big one! */
1972 switch (s[0])
1973 {
1974
1975 case '*':
1976 case '~':
1977 case '%':
1978 case ';':
1979 case '@':
1980 case '!':
1981 case '&':
1982 case '$':
1983 case '?':
1984 case '/':
1985 case '<':
1986 case '>':
3e602632 1987 case 'b':
252b5132
RH		 1988 case 'm':
1989 case 'n':
1990 case 'o':
1991 case 'p':
1992 case 'q':
1993 case 'v':
3e602632
NC		 1994 case 'w':
1995 case 'y':
1996 case 'z':
252b5132
RH		 1997#ifndef NO_68851
1998 case '|':
1999#endif
2000 switch (opP->mode)
2001 {
2002 case IMMED:
2003 tmpreg = 0x3c; /* 7.4 */
2004 if (strchr ("bwl", s[1]))
3e602632 2005 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2006 else
2007 nextword = get_num (&opP->disp, 0);
2008 if (isvar (&opP->disp))
2009 add_fix (s[1], &opP->disp, 0, 0);
2010 switch (s[1])
2011 {
2012 case 'b':
2013 if (!isbyte (nextword))
2014 opP->error = _("operand out of range");
2015 addword (nextword);
2016 baseo = 0;
2017 break;
2018 case 'w':
2019 if (!isword (nextword))
2020 opP->error = _("operand out of range");
2021 addword (nextword);
2022 baseo = 0;
2023 break;
2024 case 'W':
2025 if (!issword (nextword))
2026 opP->error = _("operand out of range");
2027 addword (nextword);
2028 baseo = 0;
2029 break;
2030 case 'l':
2031 addword (nextword >> 16);
2032 addword (nextword);
2033 baseo = 0;
2034 break;
2035
2036 case 'f':
2037 baseo = 2;
2038 outro = 8;
2039 break;
2040 case 'F':
2041 baseo = 4;
2042 outro = 11;
2043 break;
2044 case 'x':
2045 baseo = 6;
2046 outro = 15;
2047 break;
2048 case 'p':
2049 baseo = 6;
2050 outro = -1;
2051 break;
2052 default:
2053 abort ();
2054 }
2055 if (!baseo)
2056 break;
2057
36759679 2058 /* We gotta put out some float. */
252b5132
RH		 2059 if (op (&opP->disp) != O_big)
2060 {
2061 valueT val;
2062 int gencnt;
2063
2064 /* Can other cases happen here? */
2065 if (op (&opP->disp) != O_constant)
2066 abort ();
2067
2068 val = (valueT) offs (&opP->disp);
2069 gencnt = 0;
2070 do
2071 {
2072 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2073 val >>= LITTLENUM_NUMBER_OF_BITS;
2074 ++gencnt;
2075 }
2076 while (val != 0);
2077 offs (&opP->disp) = gencnt;
2078 }
2079 if (offs (&opP->disp) > 0)
2080 {
2081 if (offs (&opP->disp) > baseo)
2082 {
2083 as_warn (_("Bignum too big for %c format; truncated"),
2084 s[1]);
2085 offs (&opP->disp) = baseo;
2086 }
2087 baseo -= offs (&opP->disp);
2088 while (baseo--)
2089 addword (0);
2090 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2091 offs (&opP->disp)--;
2092 --wordp)
2093 addword (*wordp);
2094 break;
2095 }
2096 gen_to_words (words, baseo, (long) outro);
2097 for (wordp = words; baseo--; wordp++)
2098 addword (*wordp);
2099 break;
2100 case DREG:
2101 tmpreg = opP->reg - DATA; /* 0.dreg */
2102 break;
2103 case AREG:
2104 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2105 break;
2106 case AINDR:
2107 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2108 break;
2109 case ADEC:
2110 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2111 break;
2112 case AINC:
2113 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2114 break;
2115 case DISP:
2116
3e602632 2117 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2118
2119 if (opP->reg == PC
2120 && ! isvar (&opP->disp)
2121 && m68k_abspcadd)
2122 {
2123 opP->disp.exp.X_op = O_symbol;
2124#ifndef BFD_ASSEMBLER
2125 opP->disp.exp.X_add_symbol = &abs_symbol;
2126#else
2127 opP->disp.exp.X_add_symbol =
2128 section_symbol (absolute_section);
2129#endif
2130 }
2131
36759679 2132 /* Force into index mode. Hope this works. */
252b5132
RH		 2133
2134 /* We do the first bit for 32-bit displacements, and the
2135 second bit for 16 bit ones. It is possible that we
2136 should make the default be WORD instead of LONG, but
2137 I think that'd break GCC, so we put up with a little
2138 inefficiency for the sake of working output. */
2139
2140 if (!issword (nextword)
2141 || (isvar (&opP->disp)
2142 && ((opP->disp.size == SIZE_UNSPEC
2143 && flag_short_refs == 0
2144 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2145 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2146 || opP->disp.size == SIZE_LONG)))
2147 {
2148 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2149 || arch_coldfire_p (current_architecture))
252b5132
RH		 2150 opP->error =
2151 _("displacement too large for this architecture; needs 68020 or higher");
2152 if (opP->reg == PC)
2153 tmpreg = 0x3B; /* 7.3 */
2154 else
2155 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2156 if (isvar (&opP->disp))
2157 {
2158 if (opP->reg == PC)
2159 {
2160 if (opP->disp.size == SIZE_LONG
2161#ifdef OBJ_ELF
2162 /* If the displacement needs pic
2163 relocation it cannot be relaxed. */
2164 || opP->disp.pic_reloc != pic_none
2165#endif
2166 )
2167 {
2168 addword (0x0170);
2169 add_fix ('l', &opP->disp, 1, 2);
2170 }
2171 else
2172 {
2173 add_frag (adds (&opP->disp),
2174 offs (&opP->disp),
151337e8 2175 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2176 break;
2177 }
2178 }
2179 else
2180 {
2181 addword (0x0170);
2182 add_fix ('l', &opP->disp, 0, 0);
2183 }
2184 }
2185 else
2186 addword (0x0170);
2187 addword (nextword >> 16);
2188 }
2189 else
2190 {
2191 if (opP->reg == PC)
2192 tmpreg = 0x3A; /* 7.2 */
2193 else
2194 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2195
2196 if (isvar (&opP->disp))
2197 {
2198 if (opP->reg == PC)
2199 {
2200 add_fix ('w', &opP->disp, 1, 0);
2201 }
2202 else
2203 add_fix ('w', &opP->disp, 0, 0);
2204 }
2205 }
2206 addword (nextword);
2207 break;
2208
2209 case POST:
2210 case PRE:
2211 case BASE:
2212 nextword = 0;
3e602632 2213 baseo = get_num (&opP->disp, 90);
252b5132 2214 if (opP->mode == POST || opP->mode == PRE)
3e602632 2215 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2216 /* Figure out the `addressing mode'.
2217 Also turn on the BASE_DISABLE bit, if needed. */
2218 if (opP->reg == PC || opP->reg == ZPC)
2219 {
2220 tmpreg = 0x3b; /* 7.3 */
2221 if (opP->reg == ZPC)
2222 nextword |= 0x80;
2223 }
2224 else if (opP->reg == 0)
2225 {
2226 nextword |= 0x80;
2227 tmpreg = 0x30; /* 6.garbage */
2228 }
2229 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2230 {
2231 nextword |= 0x80;
2232 tmpreg = 0x30 + opP->reg - ZADDR0;
2233 }
2234 else
2235 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2236
2237 siz1 = opP->disp.size;
2238 if (opP->mode == POST || opP->mode == PRE)
2239 siz2 = opP->odisp.size;
2240 else
2241 siz2 = SIZE_UNSPEC;
2242
36759679 2243 /* Index register stuff. */
252b5132
RH		 2244 if (opP->index.reg != 0
2245 && opP->index.reg >= DATA
2246 && opP->index.reg <= ADDR7)
2247 {
2248 nextword |= (opP->index.reg - DATA) << 12;
2249
2250 if (opP->index.size == SIZE_LONG
2251 || (opP->index.size == SIZE_UNSPEC
2252 && m68k_index_width_default == SIZE_LONG))
2253 nextword |= 0x800;
2254
92774660 2255 if ((opP->index.scale != 1
252b5132 2256 && cpu_of_arch (current_architecture) < m68020)
92774660 2257 || (opP->index.scale == 8
3e602632
NC		 2258 && (arch_coldfire_p (current_architecture)
2259 && !arch_coldfire_v4e_p(current_architecture))))
252b5132
RH		 2260 {
2261 opP->error =
2262 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2263 }
2264
6da466c7
ILT		 2265 if (arch_coldfire_p (current_architecture)
2266 && opP->index.size == SIZE_WORD)
2267 opP->error = _("invalid index size for coldfire");
2268
252b5132
RH		 2269 switch (opP->index.scale)
2270 {
2271 case 1:
2272 break;
2273 case 2:
2274 nextword |= 0x200;
2275 break;
2276 case 4:
2277 nextword |= 0x400;
2278 break;
2279 case 8:
2280 nextword |= 0x600;
2281 break;
2282 default:
2283 abort ();
2284 }
2285 /* IF its simple,
2286 GET US OUT OF HERE! */
2287
2288 /* Must be INDEX, with an index register. Address
2289 register cannot be ZERO-PC, and either :b was
2290 forced, or we know it will fit. For a 68000 or
2291 68010, force this mode anyways, because the
2292 larger modes aren't supported. */
2293 if (opP->mode == BASE
2294 && ((opP->reg >= ADDR0
2295 && opP->reg <= ADDR7)
2296 || opP->reg == PC))
2297 {
2298 if (siz1 == SIZE_BYTE
2299 || cpu_of_arch (current_architecture) < m68020
6da466c7 2300 || arch_coldfire_p (current_architecture)
252b5132
RH		 2301 || (siz1 == SIZE_UNSPEC
2302 && ! isvar (&opP->disp)
2303 && issbyte (baseo)))
2304 {
2305 nextword += baseo & 0xff;
2306 addword (nextword);
2307 if (isvar (&opP->disp))
2308 {
2309 /* Do a byte relocation. If it doesn't
2310 fit (possible on m68000) let the
2311 fixup processing complain later. */
2312 if (opP->reg == PC)
2313 add_fix ('B', &opP->disp, 1, 1);
2314 else
2315 add_fix ('B', &opP->disp, 0, 0);
2316 }
2317 else if (siz1 != SIZE_BYTE)
2318 {
2319 if (siz1 != SIZE_UNSPEC)
2320 as_warn (_("Forcing byte displacement"));
2321 if (! issbyte (baseo))
2322 opP->error = _("byte displacement out of range");
2323 }
2324
2325 break;
2326 }
2327 else if (siz1 == SIZE_UNSPEC
2328 && opP->reg == PC
2329 && isvar (&opP->disp)
2330 && subs (&opP->disp) == NULL
2331#ifdef OBJ_ELF
2332 /* If the displacement needs pic
2333 relocation it cannot be relaxed. */
2334 && opP->disp.pic_reloc == pic_none
2335#endif
2336 )
2337 {
2338 /* The code in md_convert_frag_1 needs to be
2339 able to adjust nextword. Call frag_grow
2340 to ensure that we have enough space in
2341 the frag obstack to make all the bytes
2342 contiguous. */
2343 frag_grow (14);
8a104df9
KH		 2344 nextword += baseo & 0xff;
2345 addword (nextword);
2346 add_frag (adds (&opP->disp), offs (&opP->disp),
2347 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2348
2349 break;
8a104df9 2350 }
252b5132
RH		 2351 }
2352 }
2353 else
2354 {
36759679 2355 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2356 if (opP->index.reg >= ZDATA0
2357 && opP->index.reg <= ZDATA7)
2358 nextword |= (opP->index.reg - ZDATA0) << 12;
2359 else if (opP->index.reg >= ZADDR0
2360 || opP->index.reg <= ZADDR7)
2361 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2362 }
2363
2364 /* It isn't simple. */
2365
2366 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2367 || arch_coldfire_p (current_architecture))
252b5132
RH		 2368 opP->error =
2369 _("invalid operand mode for this architecture; needs 68020 or higher");
2370
2371 nextword |= 0x100;
2372 /* If the guy specified a width, we assume that it is
2373 wide enough. Maybe it isn't. If so, we lose. */
2374 switch (siz1)
2375 {
2376 case SIZE_UNSPEC:
2377 if (isvar (&opP->disp)
2378 ? m68k_rel32
2379 : ! issword (baseo))
2380 {
2381 siz1 = SIZE_LONG;
2382 nextword |= 0x30;
2383 }
2384 else if (! isvar (&opP->disp) && baseo == 0)
2385 nextword |= 0x10;
2386 else
2387 {
2388 nextword |= 0x20;
2389 siz1 = SIZE_WORD;
2390 }
2391 break;
2392 case SIZE_BYTE:
2393 as_warn (_(":b not permitted; defaulting to :w"));
2394 /* Fall through. */
2395 case SIZE_WORD:
2396 nextword |= 0x20;
2397 break;
2398 case SIZE_LONG:
2399 nextword |= 0x30;
2400 break;
2401 }
2402
36759679 2403 /* Figure out innner displacement stuff. */
252b5132
RH		 2404 if (opP->mode == POST || opP->mode == PRE)
2405 {
2406 if (cpu_of_arch (current_architecture) & cpu32)
2407 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2408 switch (siz2)
2409 {
2410 case SIZE_UNSPEC:
2411 if (isvar (&opP->odisp)
2412 ? m68k_rel32
2413 : ! issword (outro))
2414 {
2415 siz2 = SIZE_LONG;
2416 nextword |= 0x3;
2417 }
2418 else if (! isvar (&opP->odisp) && outro == 0)
2419 nextword |= 0x1;
2420 else
2421 {
2422 nextword |= 0x2;
2423 siz2 = SIZE_WORD;
2424 }
2425 break;
2426 case 1:
2427 as_warn (_(":b not permitted; defaulting to :w"));
2428 /* Fall through. */
2429 case 2:
2430 nextword |= 0x2;
2431 break;
2432 case 3:
2433 nextword |= 0x3;
2434 break;
2435 }
2436 if (opP->mode == POST
2437 && (nextword & 0x40) == 0)
2438 nextword |= 0x04;
2439 }
2440 addword (nextword);
2441
2442 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2443 {
2444 if (opP->reg == PC || opP->reg == ZPC)
2445 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2446 else
2447 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2448 }
2449 if (siz1 == SIZE_LONG)
2450 addword (baseo >> 16);
2451 if (siz1 != SIZE_UNSPEC)
2452 addword (baseo);
2453
2454 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2455 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2456 if (siz2 == SIZE_LONG)
2457 addword (outro >> 16);
2458 if (siz2 != SIZE_UNSPEC)
2459 addword (outro);
2460
2461 break;
2462
2463 case ABSL:
3e602632 2464 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2465 switch (opP->disp.size)
2466 {
2467 default:
2468 abort ();
2469 case SIZE_UNSPEC:
2470 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2471 {
2472 tmpreg = 0x38; /* 7.0 */
2473 addword (nextword);
2474 break;
2475 }
252b5132
RH		 2476 if (isvar (&opP->disp)
2477 && !subs (&opP->disp)
2478 && adds (&opP->disp)
2479#ifdef OBJ_ELF
2480 /* If the displacement needs pic relocation it
2481 cannot be relaxed. */
2482 && opP->disp.pic_reloc == pic_none
2483#endif
252b5132
RH		 2484 && !flag_long_jumps
2485 && !strchr ("~%&$?", s[0]))
2486 {
2487 tmpreg = 0x3A; /* 7.2 */
2488 add_frag (adds (&opP->disp),
2489 offs (&opP->disp),
151337e8 2490 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2491 break;
2492 }
36759679 2493 /* Fall through into long. */
252b5132
RH		 2494 case SIZE_LONG:
2495 if (isvar (&opP->disp))
2496 add_fix ('l', &opP->disp, 0, 0);
2497
2498 tmpreg = 0x39;/* 7.1 mode */
2499 addword (nextword >> 16);
2500 addword (nextword);
2501 break;
2502
2503 case SIZE_BYTE:
2504 as_bad (_("unsupported byte value; use a different suffix"));
2505 /* Fall through. */
36759679
NC		 2506
2507 case SIZE_WORD:
252b5132
RH		 2508 if (isvar (&opP->disp))
2509 add_fix ('w', &opP->disp, 0, 0);
2510
2511 tmpreg = 0x38;/* 7.0 mode */
2512 addword (nextword);
2513 break;
2514 }
2515 break;
2516 case CONTROL:
2517 case FPREG:
2518 default:
2519 as_bad (_("unknown/incorrect operand"));
bc805888 2520 /* abort (); */
252b5132
RH		 2521 }
2522 install_gen_operand (s[1], tmpreg);
2523 break;
2524
2525 case '#':
2526 case '^':
2527 switch (s[1])
2528 { /* JF: I hate floating point! */
2529 case 'j':
2530 tmpreg = 70;
2531 break;
2532 case '8':
2533 tmpreg = 20;
2534 break;
2535 case 'C':
2536 tmpreg = 50;
2537 break;
2538 case '3':
2539 default:
3e602632 2540 tmpreg = 90;
252b5132
RH		 2541 break;
2542 }
2543 tmpreg = get_num (&opP->disp, tmpreg);
2544 if (isvar (&opP->disp))
2545 add_fix (s[1], &opP->disp, 0, 0);
2546 switch (s[1])
2547 {
2548 case 'b': /* Danger: These do no check for
2549 certain types of overflow.
2550 user beware! */
2551 if (!isbyte (tmpreg))
2552 opP->error = _("out of range");
2553 insop (tmpreg, opcode);
2554 if (isvar (&opP->disp))
2555 the_ins.reloc[the_ins.nrel - 1].n =
2556 (opcode->m_codenum) * 2 + 1;
2557 break;
2558 case 'B':
2559 if (!issbyte (tmpreg))
2560 opP->error = _("out of range");
2561 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2562 if (isvar (&opP->disp))
2563 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2564 break;
2565 case 'w':
2566 if (!isword (tmpreg))
2567 opP->error = _("out of range");
2568 insop (tmpreg, opcode);
2569 if (isvar (&opP->disp))
2570 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2571 break;
2572 case 'W':
2573 if (!issword (tmpreg))
2574 opP->error = _("out of range");
2575 insop (tmpreg, opcode);
2576 if (isvar (&opP->disp))
2577 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2578 break;
2579 case 'l':
2580 /* Because of the way insop works, we put these two out
2581 backwards. */
2582 insop (tmpreg, opcode);
2583 insop (tmpreg >> 16, opcode);
2584 if (isvar (&opP->disp))
2585 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2586 break;
2587 case '3':
2588 tmpreg &= 0xFF;
2589 case '8':
2590 case 'C':
2591 case 'j':
2592 install_operand (s[1], tmpreg);
2593 break;
2594 default:
2595 abort ();
2596 }
2597 break;
2598
2599 case '+':
2600 case '-':
2601 case 'A':
2602 case 'a':
2603 install_operand (s[1], opP->reg - ADDR);
2604 break;
2605
2606 case 'B':
3e602632 2607 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2608 switch (s[1])
2609 {
2610 case 'B':
8390138c 2611 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2612 break;
2613 case 'W':
2614 add_fix ('w', &opP->disp, 1, 0);
2615 addword (0);
2616 break;
2617 case 'L':
2618 long_branch:
151337e8 2619 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2620 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2621 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2622 add_fix ('l', &opP->disp, 1, 0);
2623 addword (0);
2624 addword (0);
2625 break;
2626 case 'g':
36759679 2627 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2628 goto long_branch;
2629
2630#ifdef OBJ_ELF
2631 /* If the displacement needs pic relocation it cannot be
2632 relaxed. */
2633 if (opP->disp.pic_reloc != pic_none)
2634 goto long_branch;
2635#endif
252b5132 2636 /* This could either be a symbol, or an absolute
151337e8
NC		 2637 address. If it's an absolute address, turn it into
2638 an absolute jump right here and keep it out of the
2639 relaxer. */
2640 if (adds (&opP->disp) == 0)
2641 {
2642 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2643 the_ins.opcode[0] = 0x4EF9;
151337e8 2644 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2645 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2646 else /* jCC */
2647 {
2648 the_ins.opcode[0] ^= 0x0100;
2649 the_ins.opcode[0] |= 0x0006;
18566f55 2650 addword (0x4EF9);
151337e8
NC		 2651 }
2652 add_fix ('l', &opP->disp, 0, 0);
2653 addword (0);
2654 addword (0);
2655 break;
2656 }
2657
2658 /* Now we know it's going into the relaxer. Now figure
2659 out which mode. We try in this order of preference:
2660 long branch, absolute jump, byte/word branches only. */
2661 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2662 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2663 TAB (BRANCHBWL, SZ_UNDEF));
2664 else if (! flag_keep_pcrel)
2665 {
2666 if ((the_ins.opcode[0] == 0x6000)
2667 || (the_ins.opcode[0] == 0x6100))
2668 add_frag (adds (&opP->disp), offs (&opP->disp),
2669 TAB (BRABSJUNC, SZ_UNDEF));
2670 else
2671 add_frag (adds (&opP->disp), offs (&opP->disp),
2672 TAB (BRABSJCOND, SZ_UNDEF));
2673 }
252b5132
RH		 2674 else
2675 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2676 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2677 break;
2678 case 'w':
2679 if (isvar (&opP->disp))
2680 {
151337e8
NC		 2681 /* Check for DBcc instructions. We can relax them,
2682 but only if we have long branches and/or absolute
2683 jumps. */
2684 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2685 && (HAVE_LONG_BRANCH (current_architecture)
2686 || (! flag_keep_pcrel)))
252b5132 2687 {
151337e8
NC		 2688 if (HAVE_LONG_BRANCH (current_architecture))
2689 add_frag (adds (&opP->disp), offs (&opP->disp),
2690 TAB (DBCCLBR, SZ_UNDEF));
2691 else
2692 add_frag (adds (&opP->disp), offs (&opP->disp),
2693 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2694 break;
2695 }
252b5132
RH		 2696 add_fix ('w', &opP->disp, 1, 0);
2697 }
2698 addword (0);
2699 break;
36759679 2700 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2701 add_fix ('l', &opP->disp, 1, 0);
2702 addword (0);
2703 addword (0);
2704 break;
36759679 2705 case 'c': /* Var size Coprocesssor branches. */
151337e8 2706 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2707 {
252b5132
RH		 2708 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2709 add_fix ('l', &opP->disp, 1, 0);
2710 addword (0);
2711 addword (0);
2712 }
151337e8
NC		 2713 else
2714 add_frag (adds (&opP->disp), offs (&opP->disp),
2715 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2716 break;
2717 default:
2718 abort ();
2719 }
2720 break;
2721
36759679 2722 case 'C': /* Ignore it. */
252b5132
RH		 2723 break;
2724
36759679 2725 case 'd': /* JF this is a kludge. */
252b5132 2726 install_operand ('s', opP->reg - ADDR);
3e602632 2727 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2728 if (!issword (tmpreg))
2729 {
2730 as_warn (_("Expression out of range, using 0"));
2731 tmpreg = 0;
2732 }
2733 addword (tmpreg);
2734 break;
2735
2736 case 'D':
2737 install_operand (s[1], opP->reg - DATA);
2738 break;
2739
36759679 2740 case 'E': /* Ignore it. */
6da466c7
ILT		 2741 break;
2742
252b5132
RH		 2743 case 'F':
2744 install_operand (s[1], opP->reg - FP0);
2745 break;
2746
36759679 2747 case 'G': /* Ignore it. */
6da466c7
ILT		 2748 case 'H':
2749 break;
2750
252b5132
RH		 2751 case 'I':
2752 tmpreg = opP->reg - COP0;
2753 install_operand (s[1], tmpreg);
2754 break;
2755
36759679 2756 case 'J': /* JF foo. */
252b5132
RH		 2757 switch (opP->reg)
2758 {
2759 case SFC:
2760 tmpreg = 0x000;
2761 break;
2762 case DFC:
2763 tmpreg = 0x001;
2764 break;
2765 case CACR:
2766 tmpreg = 0x002;
2767 break;
2768 case TC:
2769 tmpreg = 0x003;
2770 break;
3e602632 2771 case ACR0:
252b5132
RH		 2772 case ITT0:
2773 tmpreg = 0x004;
2774 break;
3e602632 2775 case ACR1:
252b5132
RH		 2776 case ITT1:
2777 tmpreg = 0x005;
2778 break;
3e602632 2779 case ACR2:
252b5132
RH		 2780 case DTT0:
2781 tmpreg = 0x006;
2782 break;
3e602632 2783 case ACR3:
252b5132
RH		 2784 case DTT1:
2785 tmpreg = 0x007;
2786 break;
2787 case BUSCR:
2788 tmpreg = 0x008;
2789 break;
2790
2791 case USP:
2792 tmpreg = 0x800;
2793 break;
2794 case VBR:
2795 tmpreg = 0x801;
2796 break;
2797 case CAAR:
2798 tmpreg = 0x802;
2799 break;
2800 case MSP:
2801 tmpreg = 0x803;
2802 break;
2803 case ISP:
2804 tmpreg = 0x804;
2805 break;
2806 case MMUSR:
2807 tmpreg = 0x805;
2808 break;
2809 case URP:
2810 tmpreg = 0x806;
2811 break;
2812 case SRP:
2813 tmpreg = 0x807;
2814 break;
2815 case PCR:
2816 tmpreg = 0x808;
2817 break;
2818 case ROMBAR:
2819 tmpreg = 0xC00;
2820 break;
3e602632
NC		 2821 case ROMBAR1:
2822 tmpreg = 0xC01;
2823 break;
2824 case FLASHBAR:
252b5132
RH		 2825 case RAMBAR0:
2826 tmpreg = 0xC04;
2827 break;
3e602632 2828 case RAMBAR:
252b5132
RH		 2829 case RAMBAR1:
2830 tmpreg = 0xC05;
2831 break;
3e602632
NC		 2832 case MPCR:
2833 tmpreg = 0xC0C;
2834 break;
2835 case EDRAMBAR:
2836 tmpreg = 0xC0D;
2837 break;
2838 case MBAR0:
2839 case SECMBAR:
2840 tmpreg = 0xC0E;
2841 break;
2842 case MBAR1:
252b5132
RH		 2843 case MBAR:
2844 tmpreg = 0xC0F;
2845 break;
3e602632
NC		 2846 case PCR1U0:
2847 tmpreg = 0xD02;
2848 break;
2849 case PCR1L0:
2850 tmpreg = 0xD03;
2851 break;
2852 case PCR2U0:
2853 tmpreg = 0xD04;
2854 break;
2855 case PCR2L0:
2856 tmpreg = 0xD05;
2857 break;
2858 case PCR3U0:
2859 tmpreg = 0xD06;
2860 break;
2861 case PCR3L0:
2862 tmpreg = 0xD07;
2863 break;
2864 case PCR1L1:
2865 tmpreg = 0xD0A;
2866 break;
2867 case PCR1U1:
2868 tmpreg = 0xD0B;
2869 break;
2870 case PCR2L1:
2871 tmpreg = 0xD0C;
2872 break;
2873 case PCR2U1:
2874 tmpreg = 0xD0D;
2875 break;
2876 case PCR3L1:
2877 tmpreg = 0xD0E;
2878 break;
2879 case PCR3U1:
2880 tmpreg = 0xD0F;
2881 break;
252b5132
RH		 2882 default:
2883 abort ();
2884 }
2885 install_operand (s[1], tmpreg);
2886 break;
2887
2888 case 'k':
2889 tmpreg = get_num (&opP->disp, 55);
2890 install_operand (s[1], tmpreg & 0x7f);
2891 break;
2892
2893 case 'l':
2894 tmpreg = opP->mask;
2895 if (s[1] == 'w')
2896 {
2897 if (tmpreg & 0x7FF0000)
2898 as_bad (_("Floating point register in register list"));
2899 insop (reverse_16_bits (tmpreg), opcode);
2900 }
2901 else
2902 {
2903 if (tmpreg & 0x700FFFF)
2904 as_bad (_("Wrong register in floating-point reglist"));
2905 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2906 }
2907 break;
2908
2909 case 'L':
2910 tmpreg = opP->mask;
2911 if (s[1] == 'w')
2912 {
2913 if (tmpreg & 0x7FF0000)
2914 as_bad (_("Floating point register in register list"));
2915 insop (tmpreg, opcode);
2916 }
2917 else if (s[1] == '8')
2918 {
2919 if (tmpreg & 0x0FFFFFF)
2920 as_bad (_("incorrect register in reglist"));
2921 install_operand (s[1], tmpreg >> 24);
2922 }
2923 else
2924 {
2925 if (tmpreg & 0x700FFFF)
2926 as_bad (_("wrong register in floating-point reglist"));
2927 else
2928 install_operand (s[1], tmpreg >> 16);
2929 }
2930 break;
2931
2932 case 'M':
2933 install_operand (s[1], get_num (&opP->disp, 60));
2934 break;
2935
2936 case 'O':
2937 tmpreg = ((opP->mode == DREG)
8fce3f5e 2938 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2939 : (get_num (&opP->disp, 40) & 0x1F));
2940 install_operand (s[1], tmpreg);
2941 break;
2942
2943 case 'Q':
2944 tmpreg = get_num (&opP->disp, 10);
2945 if (tmpreg == 8)
2946 tmpreg = 0;
2947 install_operand (s[1], tmpreg);
2948 break;
2949
2950 case 'R':
2951 /* This depends on the fact that ADDR registers are eight
2952 more than their corresponding DATA regs, so the result
36759679 2953 will have the ADDR_REG bit set. */
252b5132
RH		 2954 install_operand (s[1], opP->reg - DATA);
2955 break;
2956
2957 case 'r':
2958 if (opP->mode == AINDR)
2959 install_operand (s[1], opP->reg - DATA);
2960 else
2961 install_operand (s[1], opP->index.reg - DATA);
2962 break;
2963
2964 case 's':
2965 if (opP->reg == FPI)
2966 tmpreg = 0x1;
2967 else if (opP->reg == FPS)
2968 tmpreg = 0x2;
2969 else if (opP->reg == FPC)
2970 tmpreg = 0x4;
2971 else
2972 abort ();
2973 install_operand (s[1], tmpreg);
2974 break;
2975
36759679 2976 case 'S': /* Ignore it. */
252b5132
RH		 2977 break;
2978
2979 case 'T':
2980 install_operand (s[1], get_num (&opP->disp, 30));
2981 break;
2982
36759679 2983 case 'U': /* Ignore it. */
252b5132
RH		 2984 break;
2985
2986 case 'c':
2987 switch (opP->reg)
2988 {
2989 case NC:
2990 tmpreg = 0;
2991 break;
2992 case DC:
2993 tmpreg = 1;
2994 break;
2995 case IC:
2996 tmpreg = 2;
2997 break;
2998 case BC:
2999 tmpreg = 3;
3000 break;
3001 default:
3002 as_fatal (_("failed sanity check"));
36759679 3003 } /* switch on cache token. */
252b5132
RH		 3004 install_operand (s[1], tmpreg);
3005 break;
3006#ifndef NO_68851
92774660 3007 /* JF: These are out of order, I fear. */
252b5132
RH		 3008 case 'f':
3009 switch (opP->reg)
3010 {
3011 case SFC:
3012 tmpreg = 0;
3013 break;
3014 case DFC:
3015 tmpreg = 1;
3016 break;
3017 default:
3018 abort ();
3019 }
3020 install_operand (s[1], tmpreg);
3021 break;
3022
3023 case '0':
3024 case '1':
3025 case '2':
3026 switch (opP->reg)
3027 {
3028 case TC:
3029 tmpreg = 0;
3030 break;
3031 case CAL:
3032 tmpreg = 4;
3033 break;
3034 case VAL:
3035 tmpreg = 5;
3036 break;
3037 case SCC:
3038 tmpreg = 6;
3039 break;
3040 case AC:
3041 tmpreg = 7;
3042 break;
3043 default:
3044 abort ();
3045 }
3046 install_operand (s[1], tmpreg);
3047 break;
3048
3049 case 'V':
3050 if (opP->reg == VAL)
3051 break;
3052 abort ();
3053
3054 case 'W':
3055 switch (opP->reg)
3056 {
3057 case DRP:
3058 tmpreg = 1;
3059 break;
3060 case SRP:
3061 tmpreg = 2;
3062 break;
3063 case CRP:
3064 tmpreg = 3;
3065 break;
3066 default:
3067 abort ();
3068 }
3069 install_operand (s[1], tmpreg);
3070 break;
3071
3072 case 'X':
3073 switch (opP->reg)
3074 {
3075 case BAD:
3076 case BAD + 1:
3077 case BAD + 2:
3078 case BAD + 3:
3079 case BAD + 4:
3080 case BAD + 5:
3081 case BAD + 6:
3082 case BAD + 7:
3083 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3084 break;
3085
3086 case BAC:
3087 case BAC + 1:
3088 case BAC + 2:
3089 case BAC + 3:
3090 case BAC + 4:
3091 case BAC + 5:
3092 case BAC + 6:
3093 case BAC + 7:
3094 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3095 break;
3096
3097 default:
3098 abort ();
3099 }
3100 install_operand (s[1], tmpreg);
3101 break;
3102 case 'Y':
3103 know (opP->reg == PSR);
3104 break;
3105 case 'Z':
3106 know (opP->reg == PCSR);
3107 break;
3108#endif /* m68851 */
3109 case '3':
3110 switch (opP->reg)
3111 {
3112 case TT0:
3113 tmpreg = 2;
3114 break;
3115 case TT1:
3116 tmpreg = 3;
3117 break;
3118 default:
3119 abort ();
3120 }
3121 install_operand (s[1], tmpreg);
3122 break;
3123 case 't':
3124 tmpreg = get_num (&opP->disp, 20);
3125 install_operand (s[1], tmpreg);
3126 break;
36759679 3127 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3128 if (isvar (&opP->disp))
3129 add_fix ('l', &opP->disp, 0, 0);
3e602632 3130 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3131 addword (tmpreg >> 16);
3132 addword (tmpreg & 0xFFFF);
3133 break;
6da466c7
ILT		 3134 case 'u':
3135 install_operand (s[1], opP->reg - DATA0L);
3136 opP->reg -= (DATA0L);
36759679 3137 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3138 break;
3e602632
NC		 3139 case 'x':
3140 tmpreg = get_num (&opP->disp, 80);
3141 if (tmpreg == -1)
3142 tmpreg = 0;
3143 install_operand (s[1], tmpreg);
3144 break;
252b5132
RH		 3145 default:
3146 abort ();
3147 }
3148 }
3149
3150 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3151 instruction, ready to be emitted. . . */
252b5132
RH		 3152}
3153
3154static int
3155reverse_16_bits (in)
3156 int in;
3157{
3158 int out = 0;
3159 int n;
3160
3161 static int mask[16] =
3162 {
3163 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3164 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3165 };
3166 for (n = 0; n < 16; n++)
3167 {
3168 if (in & mask[n])
3169 out |= mask[15 - n];
3170 }
3171 return out;
3172} /* reverse_16_bits() */
3173
3174static int
3175reverse_8_bits (in)
3176 int in;
3177{
3178 int out = 0;
3179 int n;
3180
3181 static int mask[8] =
3182 {
3183 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3184 };
3185
3186 for (n = 0; n < 8; n++)
3187 {
3188 if (in & mask[n])
3189 out |= mask[7 - n];
3190 }
3191 return out;
3192} /* reverse_8_bits() */
3193
3194/* Cause an extra frag to be generated here, inserting up to 10 bytes
3195 (that value is chosen in the frag_var call in md_assemble). TYPE
3196 is the subtype of the frag to be generated; its primary type is
3197 rs_machine_dependent.
3198
3199 The TYPE parameter is also used by md_convert_frag_1 and
3200 md_estimate_size_before_relax. The appropriate type of fixup will
3201 be emitted by md_convert_frag_1.
3202
3203 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3204static void
3205install_operand (mode, val)
3206 int mode;
3207 int val;
3208{
3209 switch (mode)
3210 {
3211 case 's':
36759679 3212 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3213 break;
3214 case 'd':
3215 the_ins.opcode[0] |= val << 9;
3216 break;
3217 case '1':
3218 the_ins.opcode[1] |= val << 12;
3219 break;
3220 case '2':
3221 the_ins.opcode[1] |= val << 6;
3222 break;
3223 case '3':
3224 the_ins.opcode[1] |= val;
3225 break;
3226 case '4':
3227 the_ins.opcode[2] |= val << 12;
3228 break;
3229 case '5':
3230 the_ins.opcode[2] |= val << 6;
3231 break;
3232 case '6':
3233 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3234 three words long! */
3235 the_ins.numo++;
3236 the_ins.opcode[2] |= val;
3237 break;
3238 case '7':
3239 the_ins.opcode[1] |= val << 7;
3240 break;
3241 case '8':
3242 the_ins.opcode[1] |= val << 10;
3243 break;
3244#ifndef NO_68851
3245 case '9':
3246 the_ins.opcode[1] |= val << 5;
3247 break;
3248#endif
3249
3250 case 't':
3251 the_ins.opcode[1] |= (val << 10) | (val << 7);
3252 break;
3253 case 'D':
3254 the_ins.opcode[1] |= (val << 12) | val;
3255 break;
3256 case 'g':
3257 the_ins.opcode[0] |= val = 0xff;
3258 break;
3259 case 'i':
3260 the_ins.opcode[0] |= val << 9;
3261 break;
3262 case 'C':
3263 the_ins.opcode[1] |= val;
3264 break;
3265 case 'j':
3266 the_ins.opcode[1] |= val;
36759679 3267 the_ins.numo++; /* What a hack. */
252b5132
RH		 3268 break;
3269 case 'k':
3270 the_ins.opcode[1] |= val << 4;
3271 break;
3272 case 'b':
3273 case 'w':
3274 case 'W':
3275 case 'l':
3276 break;
3277 case 'e':
3278 the_ins.opcode[0] |= (val << 6);
3279 break;
3280 case 'L':
3281 the_ins.opcode[1] = (val >> 16);
3282 the_ins.opcode[2] = val & 0xffff;
3283 break;
6da466c7
ILT		 3284 case 'm':
3285 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3286 the_ins.opcode[0] |= ((val & 0x7) << 9);
3287 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3288 break;
3289 case 'n':
3290 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3291 the_ins.opcode[0] |= ((val & 0x7) << 9);
3292 break;
3293 case 'o':
3294 the_ins.opcode[1] |= val << 12;
3295 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3296 break;
3297 case 'M':
3298 the_ins.opcode[0] |= (val & 0xF);
3299 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3300 break;
3301 case 'N':
3302 the_ins.opcode[1] |= (val & 0xF);
3303 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3304 break;
3305 case 'h':
3306 the_ins.opcode[1] |= ((val != 1) << 10);
3307 break;
252b5132
RH		 3308 case 'c':
3309 default:
3310 as_fatal (_("failed sanity check."));
3311 }
3312} /* install_operand() */
3313
3314static void
3315install_gen_operand (mode, val)
3316 int mode;
3317 int val;
3318{
3319 switch (mode)
3320 {
3321 case 's':
3322 the_ins.opcode[0] |= val;
3323 break;
3324 case 'd':
3325 /* This is a kludge!!! */
3326 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3327 break;
3328 case 'b':
3329 case 'w':
3330 case 'l':
3331 case 'f':
3332 case 'F':
3333 case 'x':
3334 case 'p':
3335 the_ins.opcode[0] |= val;
3336 break;
36759679 3337 /* more stuff goes here. */
252b5132
RH		 3338 default:
3339 as_fatal (_("failed sanity check."));
3340 }
3341} /* install_gen_operand() */
3342
3343/*
3344 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3345 * then deal with the bitfield hack.
3346 */
3347
3348static char *
3349crack_operand (str, opP)
3350 register char *str;
3351 register struct m68k_op *opP;
3352{
3353 register int parens;
3354 register int c;
3355 register char *beg_str;
3356 int inquote = 0;
3357
3358 if (!str)
3359 {
3360 return str;
3361 }
3362 beg_str = str;
3363 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3364 {
3365 if (! inquote)
3366 {
3367 if (*str == '(')
3368 parens++;
3369 else if (*str == ')')
3370 {
3371 if (!parens)
36759679 3372 { /* ERROR. */
252b5132
RH		 3373 opP->error = _("Extra )");
3374 return str;
3375 }
3376 --parens;
3377 }
3378 }
3379 if (flag_mri && *str == '\'')
3380 inquote = ! inquote;
3381 }
3382 if (!*str && parens)
36759679 3383 { /* ERROR. */
252b5132
RH		 3384 opP->error = _("Missing )");
3385 return str;
3386 }
3387 c = *str;
3388 *str = '\0';
3389 if (m68k_ip_op (beg_str, opP) != 0)
3390 {
3391 *str = c;
3392 return str;
3393 }
3394 *str = c;
3395 if (c == '}')
36759679 3396 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3397 if (c)
3398 {
3399 c = *++str;
3400 if (!c)
3401 as_bad (_("Missing operand"));
3402 }
3403
3404 /* Detect MRI REG symbols and convert them to REGLSTs. */
3405 if (opP->mode == CONTROL && (int)opP->reg < 0)
3406 {
3407 opP->mode = REGLST;
3408 opP->mask = ~(int)opP->reg;
3409 opP->reg = 0;
3410 }
3411
3412 return str;
3413}
3414
3415/* This is the guts of the machine-dependent assembler. STR points to a
3416 machine dependent instruction. This function is supposed to emit
3417 the frags/bytes it assembles to.
3418 */
3419
3420static void
3421insert_reg (regname, regnum)
3422 const char *regname;
3423 int regnum;
3424{
3425 char buf[100];
3426 int i;
3427
3428#ifdef REGISTER_PREFIX
3429 if (!flag_reg_prefix_optional)
3430 {
3431 buf[0] = REGISTER_PREFIX;
3432 strcpy (buf + 1, regname);
3433 regname = buf;
3434 }
3435#endif
3436
3437 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3438 &zero_address_frag));
3439
3440 for (i = 0; regname[i]; i++)
3882b010 3441 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3442 buf[i] = '\0';
3443
3444 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3445 &zero_address_frag));
3446}
3447
3448struct init_entry
3449 {
3450 const char *name;
3451 int number;
3452 };
3453
3454static const struct init_entry init_table[] =
3455{
3456 { "d0", DATA0 },
3457 { "d1", DATA1 },
3458 { "d2", DATA2 },
3459 { "d3", DATA3 },
3460 { "d4", DATA4 },
3461 { "d5", DATA5 },
3462 { "d6", DATA6 },
3463 { "d7", DATA7 },
3464 { "a0", ADDR0 },
3465 { "a1", ADDR1 },
3466 { "a2", ADDR2 },
3467 { "a3", ADDR3 },
3468 { "a4", ADDR4 },
3469 { "a5", ADDR5 },
3470 { "a6", ADDR6 },
3471 { "fp", ADDR6 },
3472 { "a7", ADDR7 },
3473 { "sp", ADDR7 },
3474 { "ssp", ADDR7 },
3475 { "fp0", FP0 },
3476 { "fp1", FP1 },
3477 { "fp2", FP2 },
3478 { "fp3", FP3 },
3479 { "fp4", FP4 },
3480 { "fp5", FP5 },
3481 { "fp6", FP6 },
3482 { "fp7", FP7 },
3483 { "fpi", FPI },
3484 { "fpiar", FPI },
3485 { "fpc", FPI },
3486 { "fps", FPS },
3487 { "fpsr", FPS },
3488 { "fpc", FPC },
3489 { "fpcr", FPC },
3490 { "control", FPC },
3491 { "status", FPS },
3492 { "iaddr", FPI },
3493
3494 { "cop0", COP0 },
3495 { "cop1", COP1 },
3496 { "cop2", COP2 },
3497 { "cop3", COP3 },
3498 { "cop4", COP4 },
3499 { "cop5", COP5 },
3500 { "cop6", COP6 },
3501 { "cop7", COP7 },
3502 { "pc", PC },
3503 { "zpc", ZPC },
3504 { "sr", SR },
3505
3506 { "ccr", CCR },
3507 { "cc", CCR },
3508
6da466c7
ILT		 3509 { "acc", ACC },
3510 { "macsr", MACSR },
3511 { "mask", MASK },
3512
36759679
NC		 3513 /* Control registers. */
3514 { "sfc", SFC }, /* Source Function Code. */
252b5132 3515 { "sfcr", SFC },
36759679 3516 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3517 { "dfcr", DFC },
36759679
NC		 3518 { "cacr", CACR }, /* Cache Control Register. */
3519 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3520
36759679
NC		 3521 { "usp", USP }, /* User Stack Pointer. */
3522 { "vbr", VBR }, /* Vector Base Register. */
3523 { "msp", MSP }, /* Master Stack Pointer. */
3524 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3525
36759679
NC		 3526 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3527 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3528 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3529 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3530
3531 /* 68ec040 versions of same */
36759679
NC		 3532 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3533 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3534 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3535 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3536
3537 /* mcf5200 versions of same. The ColdFire programmer's reference
3538 manual indicated that the order is 2,3,0,1, but Ken Rose
3539 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3540 { "acr0", ACR0 }, /* Access Control Unit 0. */
3541 { "acr1", ACR1 }, /* Access Control Unit 1. */
3542 { "acr2", ACR2 }, /* Access Control Unit 2. */
3543 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3544
36759679 3545 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3546 { "tcr", TC },
3547
36759679
NC		 3548 { "mmusr", MMUSR }, /* MMU Status Register. */
3549 { "srp", SRP }, /* User Root Pointer. */
3550 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3551
3552 { "buscr", BUSCR },
3553 { "pcr", PCR },
3554
36759679
NC		 3555 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3556 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3557 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3558 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3559
3560 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3561 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3562 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3563 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3564 { "mpcr", MPCR }, /* mcfv4e registers. */
3565 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3566 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3567 { "asid", TC }, /* mcfv4e registers. */
3568 { "mmubar", BUSCR }, /* mcfv4e registers. */
3569 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3570 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3571 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3572 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3573 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3574 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3575 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3576 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3577 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3578 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3579 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3580 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3581
3582 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3583 { "rambar", RAMBAR }, /* mcf528x registers. */
36759679 3584 /* End of control registers. */
252b5132
RH		 3585
3586 { "ac", AC },
3587 { "bc", BC },
3588 { "cal", CAL },
3589 { "crp", CRP },
3590 { "drp", DRP },
3591 { "pcsr", PCSR },
3592 { "psr", PSR },
3593 { "scc", SCC },
3594 { "val", VAL },
3595 { "bad0", BAD0 },
3596 { "bad1", BAD1 },
3597 { "bad2", BAD2 },
3598 { "bad3", BAD3 },
3599 { "bad4", BAD4 },
3600 { "bad5", BAD5 },
3601 { "bad6", BAD6 },
3602 { "bad7", BAD7 },
3603 { "bac0", BAC0 },
3604 { "bac1", BAC1 },
3605 { "bac2", BAC2 },
3606 { "bac3", BAC3 },
3607 { "bac4", BAC4 },
3608 { "bac5", BAC5 },
3609 { "bac6", BAC6 },
3610 { "bac7", BAC7 },
3611
3612 { "ic", IC },
3613 { "dc", DC },
3614 { "nc", NC },
3615
3616 { "tt0", TT0 },
3617 { "tt1", TT1 },
36759679 3618 /* 68ec030 versions of same. */
252b5132
RH		 3619 { "ac0", TT0 },
3620 { "ac1", TT1 },
36759679 3621 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3622 { "acusr", PSR },
3623
3624 /* Suppressed data and address registers. */
3625 { "zd0", ZDATA0 },
3626 { "zd1", ZDATA1 },
3627 { "zd2", ZDATA2 },
3628 { "zd3", ZDATA3 },
3629 { "zd4", ZDATA4 },
3630 { "zd5", ZDATA5 },
3631 { "zd6", ZDATA6 },
3632 { "zd7", ZDATA7 },
3633 { "za0", ZADDR0 },
3634 { "za1", ZADDR1 },
3635 { "za2", ZADDR2 },
3636 { "za3", ZADDR3 },
3637 { "za4", ZADDR4 },
3638 { "za5", ZADDR5 },
3639 { "za6", ZADDR6 },
3640 { "za7", ZADDR7 },
3641
92774660 3642 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3643 { "d0l", DATA0L },
3644 { "d1l", DATA1L },
3645 { "d2l", DATA2L },
3646 { "d3l", DATA3L },
3647 { "d4l", DATA4L },
3648 { "d5l", DATA5L },
3649 { "d6l", DATA6L },
3650 { "d7l", DATA7L },
3651
3652 { "a0l", ADDR0L },
3653 { "a1l", ADDR1L },
3654 { "a2l", ADDR2L },
3655 { "a3l", ADDR3L },
3656 { "a4l", ADDR4L },
3657 { "a5l", ADDR5L },
3658 { "a6l", ADDR6L },
3659 { "a7l", ADDR7L },
3660
3661 { "d0u", DATA0U },
3662 { "d1u", DATA1U },
3663 { "d2u", DATA2U },
3664 { "d3u", DATA3U },
3665 { "d4u", DATA4U },
3666 { "d5u", DATA5U },
3667 { "d6u", DATA6U },
3668 { "d7u", DATA7U },
3669
3670 { "a0u", ADDR0U },
3671 { "a1u", ADDR1U },
3672 { "a2u", ADDR2U },
3673 { "a3u", ADDR3U },
3674 { "a4u", ADDR4U },
3675 { "a5u", ADDR5U },
3676 { "a6u", ADDR6U },
3677 { "a7u", ADDR7U },
3678
252b5132
RH		 3679 { 0, 0 }
3680};
3681
3682static void
3683init_regtable ()
3684{
3685 int i;
3686 for (i = 0; init_table[i].name; i++)
3687 insert_reg (init_table[i].name, init_table[i].number);
3688}
3689
3690static int no_68851, no_68881;
3691
3692#ifdef OBJ_AOUT
3693/* a.out machine type. Default to 68020. */
3694int m68k_aout_machtype = 2;
3695#endif
3696
3697void
3698md_assemble (str)
3699 char *str;
3700{
3701 const char *er;
3702 short *fromP;
3703 char *toP = NULL;
3704 int m, n = 0;
3705 char *to_beg_P;
3706 int shorts_this_frag;
3707 fixS *fixP;
3708
3709 /* In MRI mode, the instruction and operands are separated by a
3710 space. Anything following the operands is a comment. The label
3711 has already been removed. */
3712 if (flag_mri)
3713 {
3714 char *s;
3715 int fields = 0;
3716 int infield = 0;
3717 int inquote = 0;
3718
3719 for (s = str; *s != '\0'; s++)
3720 {
3721 if ((*s == ' ' || *s == '\t') && ! inquote)
3722 {
3723 if (infield)
3724 {
3725 ++fields;
3726 if (fields >= 2)
3727 {
3728 *s = '\0';
3729 break;
3730 }
3731 infield = 0;
3732 }
3733 }
3734 else
3735 {
3736 if (! infield)
3737 infield = 1;
3738 if (*s == '\'')
3739 inquote = ! inquote;
3740 }
3741 }
3742 }
3743
3744 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3745 m68k_ip (str);
3746 er = the_ins.error;
3747 if (!er)
3748 {
3749 for (n = 0; n < the_ins.numargs; n++)
3750 if (the_ins.operands[n].error)
3751 {
3752 er = the_ins.operands[n].error;
3753 break;
3754 }
3755 }
3756 if (er)
3757 {
3758 as_bad (_("%s -- statement `%s' ignored"), er, str);
3759 return;
3760 }
3761
3762 /* If there is a current label, record that it marks an instruction. */
3763 if (current_label != NULL)
3764 {
3765 current_label->text = 1;
3766 current_label = NULL;
3767 }
3768
f27a3839
AS		 3769#ifdef OBJ_ELF
3770 /* Tie dwarf2 debug info to the address at the start of the insn. */
3771 dwarf2_emit_insn (0);
3772#endif
3773
252b5132
RH		 3774 if (the_ins.nfrag == 0)
3775 {
36759679 3776 /* No frag hacking involved; just put it out. */
252b5132
RH		 3777 toP = frag_more (2 * the_ins.numo);
3778 fromP = &the_ins.opcode[0];
3779 for (m = the_ins.numo; m; --m)
3780 {
3781 md_number_to_chars (toP, (long) (*fromP), 2);
3782 toP += 2;
3783 fromP++;
3784 }
36759679 3785 /* Put out symbol-dependent info. */
252b5132
RH		 3786 for (m = 0; m < the_ins.nrel; m++)
3787 {
3788 switch (the_ins.reloc[m].wid)
3789 {
3790 case 'B':
3791 n = 1;
3792 break;
3793 case 'b':
3794 n = 1;
3795 break;
3796 case '3':
3797 n = 1;
3798 break;
3799 case 'w':
3800 case 'W':
3801 n = 2;
3802 break;
3803 case 'l':
3804 n = 4;
3805 break;
3806 default:
3807 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3808 the_ins.reloc[m].wid);
3809 }
3810
3811 fixP = fix_new_exp (frag_now,
3812 ((toP - frag_now->fr_literal)
3813 - the_ins.numo * 2 + the_ins.reloc[m].n),
3814 n,
3815 &the_ins.reloc[m].exp,
3816 the_ins.reloc[m].pcrel,
3817 get_reloc_code (n, the_ins.reloc[m].pcrel,
3818 the_ins.reloc[m].pic_reloc));
3819 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3820 if (the_ins.reloc[m].wid == 'B')
3821 fixP->fx_signed = 1;
3822 }
3823 return;
3824 }
3825
36759679 3826 /* There's some frag hacking. */
fbe572f9
AM		 3827 {
3828 /* Calculate the max frag size. */
3829 int wid;
3830
3831 wid = 2 * the_ins.fragb[0].fragoff;
3832 for (n = 1; n < the_ins.nfrag; n++)
3833 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3834 /* frag_var part. */
3835 wid += 10;
3836 /* Make sure the whole insn fits in one chunk, in particular that
3837 the var part is attached, as we access one byte before the
3838 variable frag for byte branches. */
3839 frag_grow (wid);
3840 }
3841
252b5132
RH		 3842 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3843 {
3844 int wid;
3845
3846 if (n == 0)
3847 wid = 2 * the_ins.fragb[n].fragoff;
3848 else
3849 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3850 toP = frag_more (wid);
3851 to_beg_P = toP;
3852 shorts_this_frag = 0;
3853 for (m = wid / 2; m; --m)
3854 {
3855 md_number_to_chars (toP, (long) (*fromP), 2);
3856 toP += 2;
3857 fromP++;
3858 shorts_this_frag++;
3859 }
3860 for (m = 0; m < the_ins.nrel; m++)
3861 {
3862 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3863 {
3864 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3865 break;
3866 }
3867 wid = the_ins.reloc[m].wid;
3868 if (wid == 0)
3869 continue;
3870 the_ins.reloc[m].wid = 0;
3871 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3872
3873 fixP = fix_new_exp (frag_now,
3874 ((toP - frag_now->fr_literal)
3875 - the_ins.numo * 2 + the_ins.reloc[m].n),
3876 wid,
3877 &the_ins.reloc[m].exp,
3878 the_ins.reloc[m].pcrel,
3879 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3880 the_ins.reloc[m].pic_reloc));
3881 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3882 }
3883 (void) frag_var (rs_machine_dependent, 10, 0,
3884 (relax_substateT) (the_ins.fragb[n].fragty),
3885 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3886 }
3887 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3888 shorts_this_frag = 0;
3889 if (n)
3890 {
3891 toP = frag_more (n * sizeof (short));
3892 while (n--)
3893 {
3894 md_number_to_chars (toP, (long) (*fromP), 2);
3895 toP += 2;
3896 fromP++;
3897 shorts_this_frag++;
3898 }
3899 }
3900 for (m = 0; m < the_ins.nrel; m++)
3901 {
3902 int wid;
3903
3904 wid = the_ins.reloc[m].wid;
3905 if (wid == 0)
3906 continue;
3907 the_ins.reloc[m].wid = 0;
3908 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3909
3910 fixP = fix_new_exp (frag_now,
3911 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3912 - shorts_this_frag * 2),
3913 wid,
3914 &the_ins.reloc[m].exp,
3915 the_ins.reloc[m].pcrel,
3916 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3917 the_ins.reloc[m].pic_reloc));
3918 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3919 }
3920}
3921
3922void
3923md_begin ()
3924{
3925 /*
3926 * md_begin -- set up hash tables with 68000 instructions.
3927 * similar to what the vax assembler does. ---phr
3928 */
3929 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3930 a copy of it at runtime, adding in the information we want but isn't
3931 there. I think it'd be better to have an awk script hack the table
3932 at compile time. Or even just xstr the table and use it as-is. But
3933 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3934 names. */
3935
94f592af
NC		 3936 const struct m68k_opcode *ins;
3937 struct m68k_incant *hack, *slak;
36759679 3938 const char *retval = 0; /* Empty string, or error msg text. */
94f592af 3939 int i;
252b5132
RH		 3940
3941 if (flag_mri)
3942 {
3943 flag_reg_prefix_optional = 1;
3944 m68k_abspcadd = 1;
3945 if (! m68k_rel32_from_cmdline)
3946 m68k_rel32 = 0;
3947 }
3948
3949 op_hash = hash_new ();
3950
3951 obstack_begin (&robyn, 4000);
3952 for (i = 0; i < m68k_numopcodes; i++)
3953 {
3954 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3955 do
3956 {
3957 ins = &m68k_opcodes[i];
3958 /* We *could* ignore insns that don't match our arch here
92774660 3959 but just leaving them out of the hash. */
252b5132
RH		 3960 slak->m_operands = ins->args;
3961 slak->m_opnum = strlen (slak->m_operands) / 2;
3962 slak->m_arch = ins->arch;
3963 slak->m_opcode = ins->opcode;
36759679 3964 /* This is kludgey. */
252b5132
RH		 3965 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3966 if (i + 1 != m68k_numopcodes
3967 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3968 {
3969 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3970 i++;
3971 }
3972 else
3973 slak->m_next = 0;
3974 slak = slak->m_next;
3975 }
3976 while (slak);
3977
3978 retval = hash_insert (op_hash, ins->name, (char *) hack);
3979 if (retval)
3980 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3981 }
3982
3983 for (i = 0; i < m68k_numaliases; i++)
3984 {
3985 const char *name = m68k_opcode_aliases[i].primary;
3986 const char *alias = m68k_opcode_aliases[i].alias;
3987 PTR val = hash_find (op_hash, name);
3988 if (!val)
3989 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3990 retval = hash_insert (op_hash, alias, val);
3991 if (retval)
3992 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3993 }
3994
3995 /* In MRI mode, all unsized branches are variable sized. Normally,
3996 they are word sized. */
3997 if (flag_mri)
3998 {
3999 static struct m68k_opcode_alias mri_aliases[] =
4000 {
4001 { "bhi", "jhi", },
4002 { "bls", "jls", },
4003 { "bcc", "jcc", },
4004 { "bcs", "jcs", },
4005 { "bne", "jne", },
4006 { "beq", "jeq", },
4007 { "bvc", "jvc", },
4008 { "bvs", "jvs", },
4009 { "bpl", "jpl", },
4010 { "bmi", "jmi", },
4011 { "bge", "jge", },
4012 { "blt", "jlt", },
4013 { "bgt", "jgt", },
4014 { "ble", "jle", },
4015 { "bra", "jra", },
4016 { "bsr", "jbsr", },
4017 };
4018
8fce3f5e
AM		 4019 for (i = 0;
4020 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4021 i++)
252b5132
RH		 4022 {
4023 const char *name = mri_aliases[i].primary;
4024 const char *alias = mri_aliases[i].alias;
4025 PTR val = hash_find (op_hash, name);
4026 if (!val)
4027 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4028 retval = hash_jam (op_hash, alias, val);
4029 if (retval)
4030 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4031 }
4032 }
4033
8fce3f5e 4034 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4035 {
4036 notend_table[i] = 0;
4037 alt_notend_table[i] = 0;
4038 }
4039 notend_table[','] = 1;
4040 notend_table['{'] = 1;
4041 notend_table['}'] = 1;
4042 alt_notend_table['a'] = 1;
4043 alt_notend_table['A'] = 1;
4044 alt_notend_table['d'] = 1;
4045 alt_notend_table['D'] = 1;
4046 alt_notend_table['#'] = 1;
4047 alt_notend_table['&'] = 1;
4048 alt_notend_table['f'] = 1;
4049 alt_notend_table['F'] = 1;
4050#ifdef REGISTER_PREFIX
4051 alt_notend_table[REGISTER_PREFIX] = 1;
4052#endif
4053
4054 /* We need to put '(' in alt_notend_table to handle
4055 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
4056 */
4057 alt_notend_table['('] = 1;
4058
4059 /* We need to put '@' in alt_notend_table to handle
4060 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
4061 */
4062 alt_notend_table['@'] = 1;
4063
4064 /* We need to put digits in alt_notend_table to handle
4065 bfextu %d0{24:1},%d0
4066 */
4067 alt_notend_table['0'] = 1;
4068 alt_notend_table['1'] = 1;
4069 alt_notend_table['2'] = 1;
4070 alt_notend_table['3'] = 1;
4071 alt_notend_table['4'] = 1;
4072 alt_notend_table['5'] = 1;
4073 alt_notend_table['6'] = 1;
4074 alt_notend_table['7'] = 1;
4075 alt_notend_table['8'] = 1;
4076 alt_notend_table['9'] = 1;
4077
4078#ifndef MIT_SYNTAX_ONLY
4079 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4080 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4081 {
4082 int n = 0;
4083 while (mote_pseudo_table[n].poc_name)
4084 {
4085 hack = (struct m68k_incant *)
4086 obstack_alloc (&robyn, sizeof (struct m68k_incant));
4087 hash_insert (op_hash,
4088 mote_pseudo_table[n].poc_name, (char *) hack);
4089 hack->m_operands = 0;
4090 hack->m_opnum = n;
4091 n++;
4092 }
4093 }
4094#endif
4095
4096 init_regtable ();
4097
4098#ifdef OBJ_ELF
4099 record_alignment (text_section, 2);
4100 record_alignment (data_section, 2);
4101 record_alignment (bss_section, 2);
4102#endif
4103}
4104
4105static void
4106select_control_regs ()
4107{
4108 /* Note which set of "movec" control registers is available. */
4109 switch (cpu_of_arch (current_architecture))
4110 {
4f2a7c9e
NC		 4111 case 0:
4112 as_warn (_("architecture not yet selected: defaulting to 68020"));
4113 control_regs = m68020_control_regs;
4114 break;
4115
252b5132
RH		 4116 case m68000:
4117 control_regs = m68000_control_regs;
4118 break;
4119 case m68010:
4120 control_regs = m68010_control_regs;
4121 break;
4122 case m68020:
4123 case m68030:
4124 control_regs = m68020_control_regs;
4125 break;
4126 case m68040:
4127 control_regs = m68040_control_regs;
4128 break;
4129 case m68060:
4130 control_regs = m68060_control_regs;
4131 break;
4132 case cpu32:
4133 control_regs = cpu32_control_regs;
4134 break;
4135 case mcf5200:
6da466c7
ILT		 4136 case mcf5206e:
4137 case mcf5307:
dc84e067 4138 case mcf5407:
6da466c7 4139 control_regs = mcf_control_regs;
252b5132 4140 break;
3e602632
NC		 4141 case mcf528x:
4142 control_regs = mcf528x_control_regs;
4143 break;
4144 case mcfv4e:
4145 control_regs = mcfv4e_control_regs;
4146 break;
252b5132
RH		 4147 default:
4148 abort ();
4149 }
4150}
4151
4152void
4153m68k_init_after_args ()
4154{
4155 if (cpu_of_arch (current_architecture) == 0)
4156 {
4157 int i;
4158 const char *default_cpu = TARGET_CPU;
4159
4160 if (*default_cpu == 'm')
4161 default_cpu++;
4162 for (i = 0; i < n_archs; i++)
4163 if (strcasecmp (default_cpu, archs[i].name) == 0)
4164 break;
4165 if (i == n_archs)
4166 {
4167 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4168 current_architecture |= m68020;
4169 }
4170 else
4171 current_architecture |= archs[i].arch;
4172 }
4173 /* Permit m68881 specification with all cpus; those that can't work
4174 with a coprocessor could be doing emulation. */
4175 if (current_architecture & m68851)
4176 {
4177 if (current_architecture & m68040)
4178 {
4179 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4180 }
4181 }
4182 /* What other incompatibilities could we check for? */
4183
4184 /* Toss in some default assumptions about coprocessors. */
4185 if (!no_68881
4186 && (cpu_of_arch (current_architecture)
4187 /* Can CPU32 have a 68881 coprocessor?? */
4188 & (m68020 | m68030 | cpu32)))
4189 {
4190 current_architecture |= m68881;
4191 }
4192 if (!no_68851
4193 && (cpu_of_arch (current_architecture) & m68020up) != 0
4194 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4195 {
4196 current_architecture |= m68851;
4197 }
4198 if (no_68881 && (current_architecture & m68881))
4199 as_bad (_("options for 68881 and no-68881 both given"));
4200 if (no_68851 && (current_architecture & m68851))
4201 as_bad (_("options for 68851 and no-68851 both given"));
4202
4203#ifdef OBJ_AOUT
4204 /* Work out the magic number. This isn't very general. */
4205 if (current_architecture & m68000)
4206 m68k_aout_machtype = 0;
4207 else if (current_architecture & m68010)
4208 m68k_aout_machtype = 1;
4209 else if (current_architecture & m68020)
4210 m68k_aout_machtype = 2;
4211 else
4212 m68k_aout_machtype = 2;
4213#endif
4214
4215 /* Note which set of "movec" control registers is available. */
4216 select_control_regs ();
4217
4218 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4219 || arch_coldfire_p (current_architecture))
252b5132
RH		 4220 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4221}
4222\f
4223/* This is called when a label is defined. */
4224
4225void
4226m68k_frob_label (sym)
4227 symbolS *sym;
4228{
4229 struct label_line *n;
4230
4231 n = (struct label_line *) xmalloc (sizeof *n);
4232 n->next = labels;
4233 n->label = sym;
4234 as_where (&n->file, &n->line);
4235 n->text = 0;
4236 labels = n;
4237 current_label = n;
4238}
4239
4240/* This is called when a value that is not an instruction is emitted. */
4241
4242void
4243m68k_flush_pending_output ()
4244{
4245 current_label = NULL;
4246}
4247
4248/* This is called at the end of the assembly, when the final value of
4249 the label is known. We warn if this is a text symbol aligned at an
4250 odd location. */
4251
4252void
4253m68k_frob_symbol (sym)
4254 symbolS *sym;
4255{
4256 if (S_GET_SEGMENT (sym) == reg_section
4257 && (int) S_GET_VALUE (sym) < 0)
4258 {
4259 S_SET_SEGMENT (sym, absolute_section);
4260 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4261 }
4262 else if ((S_GET_VALUE (sym) & 1) != 0)
4263 {
4264 struct label_line *l;
4265
4266 for (l = labels; l != NULL; l = l->next)
4267 {
4268 if (l->label == sym)
4269 {
4270 if (l->text)
4271 as_warn_where (l->file, l->line,
4272 _("text label `%s' aligned to odd boundary"),
4273 S_GET_NAME (sym));
4274 break;
4275 }
4276 }
4277 }
4278}
4279\f
4280/* This is called if we go in or out of MRI mode because of the .mri
4281 pseudo-op. */
4282
4283void
4284m68k_mri_mode_change (on)
4285 int on;
4286{
4287 if (on)
4288 {
4289 if (! flag_reg_prefix_optional)
4290 {
4291 flag_reg_prefix_optional = 1;
4292#ifdef REGISTER_PREFIX
4293 init_regtable ();
4294#endif
4295 }
4296 m68k_abspcadd = 1;
4297 if (! m68k_rel32_from_cmdline)
4298 m68k_rel32 = 0;
4299 }
4300 else
4301 {
4302 if (! reg_prefix_optional_seen)
4303 {
4304#ifdef REGISTER_PREFIX_OPTIONAL
4305 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4306#else
4307 flag_reg_prefix_optional = 0;
4308#endif
4309#ifdef REGISTER_PREFIX
4310 init_regtable ();
4311#endif
4312 }
4313 m68k_abspcadd = 0;
4314 if (! m68k_rel32_from_cmdline)
4315 m68k_rel32 = 1;
4316 }
4317}
4318
36759679 4319/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4320#define MAX_LITTLENUMS 6
4321
4322/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4323 of type TYPE, and store the appropriate bytes in *LITP. The number
4324 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4325 returned, or NULL on OK. */
4326
4327char *
4328md_atof (type, litP, sizeP)
4329 char type;
4330 char *litP;
4331 int *sizeP;
4332{
4333 int prec;
4334 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4335 LITTLENUM_TYPE *wordP;
4336 char *t;
4337
4338 switch (type)
4339 {
4340 case 'f':
4341 case 'F':
4342 case 's':
4343 case 'S':
4344 prec = 2;
4345 break;
4346
4347 case 'd':
4348 case 'D':
4349 case 'r':
4350 case 'R':
4351 prec = 4;
4352 break;
4353
4354 case 'x':
4355 case 'X':
4356 prec = 6;
4357 break;
4358
4359 case 'p':
4360 case 'P':
4361 prec = 6;
4362 break;
4363
4364 default:
4365 *sizeP = 0;
4366 return _("Bad call to MD_ATOF()");
4367 }
4368 t = atof_ieee (input_line_pointer, type, words);
4369 if (t)
4370 input_line_pointer = t;
4371
4372 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4373 for (wordP = words; prec--;)
4374 {
4375 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4376 litP += sizeof (LITTLENUM_TYPE);
4377 }
4378 return 0;
4379}
4380
4381void
4382md_number_to_chars (buf, val, n)
4383 char *buf;
4384 valueT val;
4385 int n;
4386{
4387 number_to_chars_bigendian (buf, val, n);
4388}
4389
94f592af
NC		 4390void
4391md_apply_fix3 (fixP, valP, seg)
252b5132 4392 fixS *fixP;
bbe8ef22 4393 valueT *valP;
94f592af 4394 segT seg ATTRIBUTE_UNUSED;
252b5132 4395{
bbe8ef22 4396 offsetT val = *valP;
252b5132
RH		 4397 addressT upper_limit;
4398 offsetT lower_limit;
4399
4400 /* This is unnecessary but it convinces the native rs6000 compiler
4401 to generate the code we want. */
4402 char *buf = fixP->fx_frag->fr_literal;
4403 buf += fixP->fx_where;
36759679 4404 /* End ibm compiler workaround. */
252b5132 4405
c801568a 4406 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132 4407
94f592af
NC		 4408 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4409 fixP->fx_done = 1;
4410
252b5132
RH		 4411#ifdef OBJ_ELF
4412 if (fixP->fx_addsy)
4413 {
4414 memset (buf, 0, fixP->fx_size);
36759679 4415 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4416
4417 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4418 && !S_IS_DEFINED (fixP->fx_addsy)
4419 && !S_IS_WEAK (fixP->fx_addsy))
4420 S_SET_WEAK (fixP->fx_addsy);
4421 return;
4422 }
4423#endif
4424
4425#ifdef BFD_ASSEMBLER
4426 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4427 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4428 return;
4429#endif
4430
4431 switch (fixP->fx_size)
4432 {
94f592af
NC		 4433 /* The cast to offsetT below are necessary to make code
4434 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4435 case 1:
4436 *buf++ = val;
4437 upper_limit = 0x7f;
4438 lower_limit = - (offsetT) 0x80;
4439 break;
4440 case 2:
4441 *buf++ = (val >> 8);
4442 *buf++ = val;
4443 upper_limit = 0x7fff;
4444 lower_limit = - (offsetT) 0x8000;
4445 break;
4446 case 4:
4447 *buf++ = (val >> 24);
4448 *buf++ = (val >> 16);
4449 *buf++ = (val >> 8);
4450 *buf++ = val;
4451 upper_limit = 0x7fffffff;
36759679 4452 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4453 break;
4454 default:
4455 BAD_CASE (fixP->fx_size);
4456 }
4457
4458 /* Fix up a negative reloc. */
4459 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4460 {
4461 fixP->fx_addsy = fixP->fx_subsy;
4462 fixP->fx_subsy = NULL;
4463 fixP->fx_tcbit = 1;
4464 }
4465
4466 /* For non-pc-relative values, it's conceivable we might get something
4467 like "0xff" for a byte field. So extend the upper part of the range
4468 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4469 so that we can do any range checking at all. */
4470 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4471 upper_limit = upper_limit * 2 + 1;
4472
4473 if ((addressT) val > upper_limit
4474 && (val > 0 || val < lower_limit))
4475 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4476
4477 /* A one byte PC-relative reloc means a short branch. We can't use
4478 a short branch with a value of 0 or -1, because those indicate
4479 different opcodes (branches with longer offsets). fixup_segment
4480 in write.c may have clobbered fx_pcrel, so we need to examine the
4481 reloc type. */
4482 if ((fixP->fx_pcrel
4483#ifdef BFD_ASSEMBLER
4484 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4485#endif
4486 )
4487 && fixP->fx_size == 1
4488 && (fixP->fx_addsy == NULL
4489 || S_IS_DEFINED (fixP->fx_addsy))
4490 && (val == 0 || val == -1))
4491 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4492}
4493
252b5132
RH		 4494/* *fragP has been relaxed to its final size, and now needs to have
4495 the bytes inside it modified to conform to the new size There is UGLY
4496 MAGIC here. ..
4497 */
4498static void
4499md_convert_frag_1 (fragP)
4500 register fragS *fragP;
4501{
4502 long disp;
252b5132
RH		 4503 fixS *fixP;
4504
4505 /* Address in object code of the displacement. */
4506 register int object_address = fragP->fr_fix + fragP->fr_address;
4507
4508 /* Address in gas core of the place to store the displacement. */
4509 /* This convinces the native rs6000 compiler to generate the code we
92774660 4510 want. */
252b5132
RH		 4511 register char *buffer_address = fragP->fr_literal;
4512 buffer_address += fragP->fr_fix;
36759679 4513 /* End ibm compiler workaround. */
252b5132
RH		 4514
4515 /* The displacement of the address, from current location. */
4516 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4517 disp = (disp + fragP->fr_offset) - object_address;
4518
252b5132
RH		 4519 switch (fragP->fr_subtype)
4520 {
151337e8
NC		 4521 case TAB (BRANCHBWL, BYTE):
4522 case TAB (BRABSJUNC, BYTE):
4523 case TAB (BRABSJCOND, BYTE):
4524 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4525 know (issbyte (disp));
4526 if (disp == 0)
b091f402
AM		 4527 as_bad_where (fragP->fr_file, fragP->fr_line,
4528 _("short branch with zero offset: use :w"));
151337e8 4529 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4530 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4531 fixP->fx_pcrel_adjust = -1;
252b5132 4532 break;
151337e8
NC		 4533 case TAB (BRANCHBWL, SHORT):
4534 case TAB (BRABSJUNC, SHORT):
4535 case TAB (BRABSJCOND, SHORT):
4536 case TAB (BRANCHBW, SHORT):
252b5132 4537 fragP->fr_opcode[1] = 0x00;
151337e8 4538 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4539 1, RELAX_RELOC_PC16);
151337e8
NC		 4540 fragP->fr_fix += 2;
4541 break;
4542 case TAB (BRANCHBWL, LONG):
4543 fragP->fr_opcode[1] = (char) 0xFF;
4544 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4545 1, RELAX_RELOC_PC32);
151337e8 4546 fragP->fr_fix += 4;
252b5132 4547 break;
151337e8
NC		 4548 case TAB (BRABSJUNC, LONG):
4549 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4550 {
36759679
NC		 4551 if (flag_keep_pcrel)
4552 as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4553 fragP->fr_opcode[0] = 0x4E;
36759679 4554 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4555 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4556 0, RELAX_RELOC_ABS32);
151337e8
NC		 4557 fragP->fr_fix += 4;
4558 }
4559 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4560 {
36759679
NC		 4561 if (flag_keep_pcrel)
4562 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
151337e8 4563 fragP->fr_opcode[0] = 0x4E;
36759679 4564 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4565 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4566 0, RELAX_RELOC_ABS32);
151337e8 4567 fragP->fr_fix += 4;
252b5132
RH		 4568 }
4569 else
4570 {
151337e8
NC		 4571 /* This cannot happen, because jbsr and jbra are the only two
4572 unconditional branches. */
4573 abort ();
252b5132
RH		 4574 }
4575 break;
151337e8 4576 case TAB (BRABSJCOND, LONG):
36759679
NC		 4577 if (flag_keep_pcrel)
4578 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4579
36759679
NC		 4580 /* Only Bcc 68000 instructions can come here
4581 Change bcc into b!cc/jmp absl long. */
4582 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4583 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4584
4585 /* JF: these used to be fr_opcode[2,3], but they may be in a
4586 different frag, in which case refering to them is a no-no.
92774660 4587 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4588 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4589 *buffer_address++ = (char) 0xf9;
36759679 4590 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4591 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4592 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4593 fragP->fr_fix += 4;
4594 break;
4595 case TAB (FBRANCH, SHORT):
4596 know ((fragP->fr_opcode[1] & 0x40) == 0);
4597 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4598 1, RELAX_RELOC_PC16);
151337e8
NC		 4599 fragP->fr_fix += 2;
4600 break;
4601 case TAB (FBRANCH, LONG):
36759679 4602 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4603 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4604 1, RELAX_RELOC_PC32);
252b5132 4605 fragP->fr_fix += 4;
252b5132 4606 break;
151337e8
NC		 4607 case TAB (DBCCLBR, SHORT):
4608 case TAB (DBCCABSJ, SHORT):
4609 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4610 1, RELAX_RELOC_PC16);
151337e8
NC		 4611 fragP->fr_fix += 2;
4612 break;
4613 case TAB (DBCCLBR, LONG):
36759679
NC		 4614 /* Only DBcc instructions can come here.
4615 Change dbcc into dbcc/bral.
4616 JF: these used to be fr_opcode[2-7], but that's wrong. */
4617 if (flag_keep_pcrel)
4618 as_fatal(_("Tried to convert DBcc to absolute jump"));
28e7409f 4619
36759679 4620 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4621 *buffer_address++ = 0x04;
36759679 4622 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4623 *buffer_address++ = 0x06;
151337e8
NC		 4624 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4625 *buffer_address++ = (char) 0xff;
252b5132 4626
36759679 4627 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4628 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4629 RELAX_RELOC_PC32);
252b5132 4630 fragP->fr_fix += 4;
252b5132 4631 break;
151337e8 4632 case TAB (DBCCABSJ, LONG):
36759679
NC		 4633 /* Only DBcc instructions can come here.
4634 Change dbcc into dbcc/jmp.
4635 JF: these used to be fr_opcode[2-7], but that's wrong. */
4636 if (flag_keep_pcrel)
4637 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4638
36759679 4639 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4640 *buffer_address++ = 0x04;
36759679 4641 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4642 *buffer_address++ = 0x06;
36759679 4643 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4644 *buffer_address++ = (char) 0xf9;
4645
36759679 4646 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4647 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4648 RELAX_RELOC_ABS32);
252b5132 4649 fragP->fr_fix += 4;
252b5132 4650 break;
151337e8 4651 case TAB (PCREL1632, SHORT):
252b5132
RH		 4652 fragP->fr_opcode[1] &= ~0x3F;
4653 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4654 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4655 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4656 fragP->fr_fix += 2;
252b5132 4657 break;
151337e8 4658 case TAB (PCREL1632, LONG):
252b5132
RH		 4659 /* Already set to mode 7.3; this indicates: PC indirect with
4660 suppressed index, 32-bit displacement. */
4661 *buffer_address++ = 0x01;
4662 *buffer_address++ = 0x70;
4663 fragP->fr_fix += 2;
151337e8 4664 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4665 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4666 fixP->fx_pcrel_adjust = 2;
4667 fragP->fr_fix += 4;
252b5132 4668 break;
252b5132 4669 case TAB (PCINDEX, BYTE):
252b5132
RH		 4670 assert (fragP->fr_fix >= 2);
4671 buffer_address[-2] &= ~1;
151337e8 4672 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4673 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4674 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4675 break;
4676 case TAB (PCINDEX, SHORT):
252b5132
RH		 4677 assert (fragP->fr_fix >= 2);
4678 buffer_address[-2] |= 0x1;
4679 buffer_address[-1] = 0x20;
4680 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4681 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4682 fixP->fx_pcrel_adjust = 2;
151337e8 4683 fragP->fr_fix += 2;
252b5132
RH		 4684 break;
4685 case TAB (PCINDEX, LONG):
252b5132
RH		 4686 assert (fragP->fr_fix >= 2);
4687 buffer_address[-2] |= 0x1;
4688 buffer_address[-1] = 0x30;
151337e8 4689 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4690 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4691 fixP->fx_pcrel_adjust = 2;
4692 fragP->fr_fix += 4;
4693 break;
4694 case TAB (ABSTOPCREL, SHORT):
4695 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4696 1, RELAX_RELOC_PC16);
151337e8
NC		 4697 fragP->fr_fix += 2;
4698 break;
4699 case TAB (ABSTOPCREL, LONG):
36759679
NC		 4700 if (flag_keep_pcrel)
4701 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4702 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4703 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4704 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4705 abort ();
4706 fragP->fr_opcode[1] &= ~0x3F;
4707 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4708 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4709 0, RELAX_RELOC_ABS32);
151337e8 4710 fragP->fr_fix += 4;
252b5132 4711 break;
252b5132
RH		 4712 }
4713}
4714
4715#ifndef BFD_ASSEMBLER
4716
4717void
4718md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4719 object_headers *headers ATTRIBUTE_UNUSED;
4720 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4721 fragS *fragP;
4722{
4723 md_convert_frag_1 (fragP);
4724}
4725
4726#else
4727
4728void
4729md_convert_frag (abfd, sec, fragP)
36823076
AS		 4730 bfd *abfd ATTRIBUTE_UNUSED;
4731 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4732 fragS *fragP;
4733{
4734 md_convert_frag_1 (fragP);
4735}
4736#endif
4737
4738/* Force truly undefined symbols to their maximum size, and generally set up
4739 the frag list to be relaxed
4740 */
4741int
4742md_estimate_size_before_relax (fragP, segment)
4743 register fragS *fragP;
4744 segT segment;
4745{
151337e8 4746 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4747 switch (fragP->fr_subtype)
4748 {
151337e8
NC		 4749 case TAB (BRANCHBWL, SZ_UNDEF):
4750 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4751 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4752 {
151337e8
NC		 4753 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4754 && relaxable_symbol (fragP->fr_symbol))
252b5132 4755 {
151337e8
NC		 4756 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4757 }
4758 else if (flag_short_refs)
4759 {
4760 /* Symbol is undefined and we want short ref. */
4761 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4762 }
4763 else
4764 {
151337e8
NC		 4765 /* Symbol is still undefined. Make it LONG. */
4766 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4767 }
4768 break;
151337e8 4769 }
252b5132 4770
151337e8 4771 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4772 {
151337e8
NC		 4773 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4774 && relaxable_symbol (fragP->fr_symbol))
252b5132 4775 {
151337e8 4776 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4777 }
4778 else
4779 {
151337e8
NC		 4780 /* Symbol is undefined and we don't have long branches. */
4781 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4782 }
4783 break;
151337e8 4784 }
252b5132 4785
151337e8 4786 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4787 case TAB (DBCCLBR, SZ_UNDEF):
4788 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4789 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4790 {
8ec6253e
NC		 4791 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4792 && relaxable_symbol (fragP->fr_symbol))
151337e8 4793 || flag_short_refs)
252b5132 4794 {
151337e8 4795 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4796 }
4797 else
4798 {
151337e8 4799 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4800 }
4801 break;
151337e8 4802 }
81d4177b 4803
252b5132
RH		 4804 case TAB (PCINDEX, SZ_UNDEF):
4805 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4806 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4807 {
4808 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4809 }
4810 else
4811 {
4812 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4813 }
4814 break;
4815
151337e8
NC		 4816 case TAB (ABSTOPCREL, SZ_UNDEF):
4817 {
4818 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4819 && relaxable_symbol (fragP->fr_symbol)))
4820 {
4821 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4822 }
4823 else
4824 {
4825 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4826 }
4827 break;
4828 }
4829
252b5132
RH		 4830 default:
4831 break;
4832 }
4833
151337e8 4834 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4835 switch (fragP->fr_subtype)
4836 {
151337e8
NC		 4837 case TAB (BRANCHBWL, BYTE):
4838 case TAB (BRABSJUNC, BYTE):
4839 case TAB (BRABSJCOND, BYTE):
4840 case TAB (BRANCHBW, BYTE):
252b5132 4841 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4842 case we force word mode. If the symbol is at the start of a
4843 frag, and it is the next frag with any data in it (usually
4844 this is just the next frag, but assembler listings may
4845 introduce empty frags), we must use word mode. */
4846 if (fragP->fr_symbol)
252b5132 4847 {
ac62c346 4848 fragS *sym_frag;
252b5132 4849
ac62c346
AM		 4850 sym_frag = symbol_get_frag (fragP->fr_symbol);
4851 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4852 {
ac62c346
AM		 4853 fragS *l;
4854
23b7f870 4855 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4856 if (l->fr_fix != 0)
4857 break;
4858 if (l == sym_frag)
4859 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4860 }
4861 }
4862 break;
4863 default:
4864 break;
4865 }
ac62c346 4866 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4867}
4868
4869#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4870/* the bit-field entries in the relocation_info struct plays hell
4871 with the byte-order problems of cross-assembly. So as a hack,
4872 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 4873 you there. -KWK */
252b5132
RH		 4874/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4875 are symbolnum, most sig. byte first. Last byte is broken up with
4876 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4877 nibble as nuthin. (on Sun 3 at least) */
4878/* Translate the internal relocation information into target-specific
92774660 4879 format. */
252b5132
RH		 4880#ifdef comment
4881void
4882md_ri_to_chars (the_bytes, ri)
4883 char *the_bytes;
4884 struct reloc_info_generic *ri;
4885{
36759679 4886 /* This is easy. */
252b5132 4887 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 4888 /* Now the fun stuff. */
252b5132 4889 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 4890 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4891 the_bytes[6] = ri->r_symbolnum & 0x0ff;
252b5132
RH		 4892 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4893 ((ri->r_extern << 4) & 0x10));
4894}
4895
36759679 4896#endif
252b5132
RH		 4897
4898#ifndef BFD_ASSEMBLER
4899void
4900tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4901 char *where;
4902 fixS *fixP;
4903 relax_addressT segment_address_in_file;
4904{
4905 /*
4906 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4907 * Out: GNU LD relocation length code: 0, 1, or 2.
4908 */
4909
5a38dc70 4910 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
252b5132
RH		 4911 long r_symbolnum;
4912
4913 know (fixP->fx_addsy != NULL);
4914
4915 md_number_to_chars (where,
4916 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4917 4);
4918
4919 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4920 ? S_GET_TYPE (fixP->fx_addsy)
4921 : fixP->fx_addsy->sy_number);
4922
4923 where[4] = (r_symbolnum >> 16) & 0x0ff;
4924 where[5] = (r_symbolnum >> 8) & 0x0ff;
4925 where[6] = r_symbolnum & 0x0ff;
4926 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4927 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4928}
4929#endif
4930
4931#endif /* OBJ_AOUT or OBJ_BOUT */
4932
4933#ifndef WORKING_DOT_WORD
5a38dc70
AM		 4934const int md_short_jump_size = 4;
4935const int md_long_jump_size = 6;
252b5132
RH		 4936
4937void
4938md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4939 char *ptr;
4940 addressT from_addr, to_addr;
36823076
AS		 4941 fragS *frag ATTRIBUTE_UNUSED;
4942 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4943{
4944 valueT offset;
4945
4946 offset = to_addr - (from_addr + 2);
4947
4948 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4949 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4950}
4951
4952void
4953md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4954 char *ptr;
4955 addressT from_addr, to_addr;
4956 fragS *frag;
4957 symbolS *to_symbol;
4958{
4959 valueT offset;
4960
4961 if (!HAVE_LONG_BRANCH(current_architecture))
4962 {
36759679
NC		 4963 if (flag_keep_pcrel)
4964 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 4965 offset = to_addr - S_GET_VALUE (to_symbol);
4966 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4967 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4968 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4969 0, NO_RELOC);
4970 }
4971 else
4972 {
4973 offset = to_addr - (from_addr + 2);
4974 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4975 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4976 }
4977}
4978
4979#endif
4980
4981/* Different values of OK tell what its OK to return. Things that
4982 aren't OK are an error (what a shock, no?)
4983
4984 0: Everything is OK
3e602632
NC		 4985 10: Absolute 1:8 only
4986 20: Absolute 0:7 only
4987 30: absolute 0:15 only
4988 40: Absolute 0:31 only
4989 50: absolute 0:127 only
252b5132 4990 55: absolute -64:63 only
3e602632
NC		 4991 60: absolute -128:127 only
4992 70: absolute 0:4095 only
4993 80: absolute -1, 1:7 only
4994 90: No bignums. */
252b5132
RH		 4995
4996static int
4997get_num (exp, ok)
4998 struct m68k_exp *exp;
4999 int ok;
5000{
5001 if (exp->exp.X_op == O_absent)
5002 {
36759679 5003 /* Do the same thing the VAX asm does. */
252b5132
RH		 5004 op (exp) = O_constant;
5005 adds (exp) = 0;
5006 subs (exp) = 0;
5007 offs (exp) = 0;
5008 if (ok == 10)
5009 {
5010 as_warn (_("expression out of range: defaulting to 1"));
5011 offs (exp) = 1;
5012 }
5013 }
5014 else if (exp->exp.X_op == O_constant)
5015 {
5016 switch (ok)
5017 {
5018 case 10:
5019 if (offs (exp) < 1 || offs (exp) > 8)
5020 {
5021 as_warn (_("expression out of range: defaulting to 1"));
5022 offs (exp) = 1;
5023 }
5024 break;
5025 case 20:
5026 if (offs (exp) < 0 || offs (exp) > 7)
5027 goto outrange;
5028 break;
5029 case 30:
5030 if (offs (exp) < 0 || offs (exp) > 15)
5031 goto outrange;
5032 break;
5033 case 40:
5034 if (offs (exp) < 0 || offs (exp) > 32)
5035 goto outrange;
5036 break;
5037 case 50:
5038 if (offs (exp) < 0 || offs (exp) > 127)
5039 goto outrange;
5040 break;
5041 case 55:
5042 if (offs (exp) < -64 || offs (exp) > 63)
5043 goto outrange;
5044 break;
5045 case 60:
5046 if (offs (exp) < -128 || offs (exp) > 127)
5047 goto outrange;
5048 break;
5049 case 70:
5050 if (offs (exp) < 0 || offs (exp) > 4095)
5051 {
5052 outrange:
5053 as_warn (_("expression out of range: defaulting to 0"));
5054 offs (exp) = 0;
5055 }
5056 break;
3e602632
NC		 5057 case 80:
5058 if (offs (exp) < -1
5059 || offs (exp) > 7
5060 || offs (exp) == 0)
5061 {
5062 as_warn (_("expression out of range: defaulting to 1"));
5063 offs (exp) = 1;
5064 }
5065 break;
252b5132
RH		 5066 default:
5067 break;
5068 }
5069 }
5070 else if (exp->exp.X_op == O_big)
5071 {
36759679 5072 if (offs (exp) <= 0 /* flonum. */
3e602632 5073 && (ok == 90 /* no bignums */
36759679 5074 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5075 /* If we have a flonum zero, a zero integer should
5076 do as well (e.g., in moveq). */
5077 && generic_floating_point_number.exponent == 0
5078 && generic_floating_point_number.low[0] == 0)))
5079 {
36759679 5080 /* HACK! Turn it into a long. */
252b5132
RH		 5081 LITTLENUM_TYPE words[6];
5082
36759679 5083 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5084 op (exp) = O_constant;
5085 adds (exp) = 0;
5086 subs (exp) = 0;
5087 offs (exp) = words[1] | (words[0] << 16);
5088 }
5089 else if (ok != 0)
5090 {
5091 op (exp) = O_constant;
5092 adds (exp) = 0;
5093 subs (exp) = 0;
5094 offs (exp) = (ok == 10) ? 1 : 0;
5095 as_warn (_("Can't deal with expression; defaulting to %ld"),
5096 offs (exp));
5097 }
5098 }
5099 else
5100 {
3e602632 5101 if (ok >= 10 && ok <= 80)
252b5132
RH		 5102 {
5103 op (exp) = O_constant;
5104 adds (exp) = 0;
5105 subs (exp) = 0;
5106 offs (exp) = (ok == 10) ? 1 : 0;
5107 as_warn (_("Can't deal with expression; defaulting to %ld"),
5108 offs (exp));
5109 }
5110 }
5111
5112 if (exp->size != SIZE_UNSPEC)
5113 {
5114 switch (exp->size)
5115 {
5116 case SIZE_UNSPEC:
5117 case SIZE_LONG:
5118 break;
5119 case SIZE_BYTE:
5120 if (!isbyte (offs (exp)))
5121 as_warn (_("expression doesn't fit in BYTE"));
5122 break;
5123 case SIZE_WORD:
5124 if (!isword (offs (exp)))
5125 as_warn (_("expression doesn't fit in WORD"));
5126 break;
5127 }
5128 }
5129
5130 return offs (exp);
5131}
5132
5133/* These are the back-ends for the various machine dependent pseudo-ops. */
5134
5135static void
5136s_data1 (ignore)
36823076 5137 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5138{
5139 subseg_set (data_section, 1);
5140 demand_empty_rest_of_line ();
5141}
5142
5143static void
5144s_data2 (ignore)
36823076 5145 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5146{
5147 subseg_set (data_section, 2);
5148 demand_empty_rest_of_line ();
5149}
5150
5151static void
5152s_bss (ignore)
36823076 5153 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5154{
5155 /* We don't support putting frags in the BSS segment, we fake it
5156 by marking in_bss, then looking at s_skip for clues. */
5157
5158 subseg_set (bss_section, 0);
5159 demand_empty_rest_of_line ();
5160}
5161
5162static void
5163s_even (ignore)
36823076 5164 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5165{
5166 register int temp;
5167 register long temp_fill;
5168
5169 temp = 1; /* JF should be 2? */
5170 temp_fill = get_absolute_expression ();
92774660 5171 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5172 frag_align (temp, (int) temp_fill, 0);
5173 demand_empty_rest_of_line ();
5174 record_alignment (now_seg, temp);
5175}
5176
5177static void
5178s_proc (ignore)
36823076 5179 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5180{
5181 demand_empty_rest_of_line ();
5182}
5183\f
5184/* Pseudo-ops handled for MRI compatibility. */
5185
5186/* This function returns non-zero if the argument is a conditional
5187 pseudo-op. This is called when checking whether a pending
5188 alignment is needed. */
5189
5190int
5191m68k_conditional_pseudoop (pop)
5192 pseudo_typeS *pop;
5193{
5194 return (pop->poc_handler == s_mri_if
5195 || pop->poc_handler == s_mri_else);
5196}
5197
5198/* Handle an MRI style chip specification. */
5199
5200static void
5201mri_chip ()
5202{
5203 char *s;
5204 char c;
5205 int i;
5206
5207 s = input_line_pointer;
5208 /* We can't use get_symbol_end since the processor names are not proper
5209 symbols. */
5210 while (is_part_of_name (c = *input_line_pointer++))
5211 ;
5212 *--input_line_pointer = 0;
5213 for (i = 0; i < n_archs; i++)
5214 if (strcasecmp (s, archs[i].name) == 0)
5215 break;
5216 if (i >= n_archs)
5217 {
5218 as_bad (_("%s: unrecognized processor name"), s);
5219 *input_line_pointer = c;
5220 ignore_rest_of_line ();
5221 return;
5222 }
5223 *input_line_pointer = c;
5224
5225 if (*input_line_pointer == '/')
5226 current_architecture = 0;
5227 else
5228 current_architecture &= m68881 | m68851;
5229 current_architecture |= archs[i].arch;
5230
5231 while (*input_line_pointer == '/')
5232 {
5233 ++input_line_pointer;
5234 s = input_line_pointer;
5235 /* We can't use get_symbol_end since the processor names are not
5236 proper symbols. */
5237 while (is_part_of_name (c = *input_line_pointer++))
5238 ;
5239 *--input_line_pointer = 0;
5240 if (strcmp (s, "68881") == 0)
5241 current_architecture |= m68881;
5242 else if (strcmp (s, "68851") == 0)
5243 current_architecture |= m68851;
5244 *input_line_pointer = c;
5245 }
5246
5247 /* Update info about available control registers. */
5248 select_control_regs ();
5249}
5250
5251/* The MRI CHIP pseudo-op. */
5252
5253static void
5254s_chip (ignore)
36823076 5255 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5256{
5257 char *stop = NULL;
5258 char stopc;
5259
5260 if (flag_mri)
5261 stop = mri_comment_field (&stopc);
5262 mri_chip ();
5263 if (flag_mri)
5264 mri_comment_end (stop, stopc);
5265 demand_empty_rest_of_line ();
5266}
5267
5268/* The MRI FOPT pseudo-op. */
5269
5270static void
5271s_fopt (ignore)
36823076 5272 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5273{
5274 SKIP_WHITESPACE ();
5275
5276 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5277 {
5278 int temp;
5279
5280 input_line_pointer += 3;
5281 temp = get_absolute_expression ();
5282 if (temp < 0 || temp > 7)
5283 as_bad (_("bad coprocessor id"));
5284 else
5285 m68k_float_copnum = COP0 + temp;
5286 }
5287 else
5288 {
5289 as_bad (_("unrecognized fopt option"));
5290 ignore_rest_of_line ();
5291 return;
5292 }
5293
5294 demand_empty_rest_of_line ();
5295}
5296
5297/* The structure used to handle the MRI OPT pseudo-op. */
5298
5299struct opt_action
5300{
5301 /* The name of the option. */
5302 const char *name;
5303
5304 /* If this is not NULL, just call this function. The first argument
5305 is the ARG field of this structure, the second argument is
5306 whether the option was negated. */
5307 void (*pfn) PARAMS ((int arg, int on));
5308
5309 /* If this is not NULL, and the PFN field is NULL, set the variable
5310 this points to. Set it to the ARG field if the option was not
5311 negated, and the NOTARG field otherwise. */
5312 int *pvar;
5313
5314 /* The value to pass to PFN or to assign to *PVAR. */
5315 int arg;
5316
5317 /* The value to assign to *PVAR if the option is negated. If PFN is
5318 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5319 the option may not be negated. */
5320 int notarg;
5321};
5322
5323/* The table used to handle the MRI OPT pseudo-op. */
5324
5325static void skip_to_comma PARAMS ((int, int));
5326static void opt_nest PARAMS ((int, int));
5327static void opt_chip PARAMS ((int, int));
5328static void opt_list PARAMS ((int, int));
5329static void opt_list_symbols PARAMS ((int, int));
5330
5331static const struct opt_action opt_table[] =
5332{
5333 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5334
5335 /* We do relaxing, so there is little use for these options. */
5336 { "b", 0, 0, 0, 0 },
5337 { "brs", 0, 0, 0, 0 },
5338 { "brb", 0, 0, 0, 0 },
5339 { "brl", 0, 0, 0, 0 },
5340 { "brw", 0, 0, 0, 0 },
5341
5342 { "c", 0, 0, 0, 0 },
5343 { "cex", 0, 0, 0, 0 },
5344 { "case", 0, &symbols_case_sensitive, 1, 0 },
5345 { "cl", 0, 0, 0, 0 },
5346 { "cre", 0, 0, 0, 0 },
5347 { "d", 0, &flag_keep_locals, 1, 0 },
5348 { "e", 0, 0, 0, 0 },
5349 { "f", 0, &flag_short_refs, 1, 0 },
5350 { "frs", 0, &flag_short_refs, 1, 0 },
5351 { "frl", 0, &flag_short_refs, 0, 1 },
5352 { "g", 0, 0, 0, 0 },
5353 { "i", 0, 0, 0, 0 },
5354 { "m", 0, 0, 0, 0 },
5355 { "mex", 0, 0, 0, 0 },
5356 { "mc", 0, 0, 0, 0 },
5357 { "md", 0, 0, 0, 0 },
5358 { "nest", opt_nest, 0, 0, 0 },
5359 { "next", skip_to_comma, 0, 0, 0 },
5360 { "o", 0, 0, 0, 0 },
5361 { "old", 0, 0, 0, 0 },
5362 { "op", skip_to_comma, 0, 0, 0 },
5363 { "pco", 0, 0, 0, 0 },
5364 { "p", opt_chip, 0, 0, 0 },
5365 { "pcr", 0, 0, 0, 0 },
5366 { "pcs", 0, 0, 0, 0 },
5367 { "r", 0, 0, 0, 0 },
5368 { "quick", 0, &m68k_quick, 1, 0 },
5369 { "rel32", 0, &m68k_rel32, 1, 0 },
5370 { "s", opt_list, 0, 0, 0 },
5371 { "t", opt_list_symbols, 0, 0, 0 },
5372 { "w", 0, &flag_no_warnings, 0, 1 },
5373 { "x", 0, 0, 0, 0 }
5374};
5375
8fce3f5e 5376#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5377
5378/* The MRI OPT pseudo-op. */
5379
5380static void
5381s_opt (ignore)
36823076 5382 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5383{
5384 do
5385 {
5386 int t;
5387 char *s;
5388 char c;
5389 int i;
5390 const struct opt_action *o;
5391
5392 SKIP_WHITESPACE ();
5393
5394 t = 1;
5395 if (*input_line_pointer == '-')
5396 {
5397 ++input_line_pointer;
5398 t = 0;
5399 }
5400 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5401 {
5402 input_line_pointer += 2;
5403 t = 0;
5404 }
5405
5406 s = input_line_pointer;
5407 c = get_symbol_end ();
5408
5409 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5410 {
5411 if (strcasecmp (s, o->name) == 0)
5412 {
5413 if (o->pfn)
5414 {
5415 /* Restore input_line_pointer now in case the option
5416 takes arguments. */
5417 *input_line_pointer = c;
5418 (*o->pfn) (o->arg, t);
5419 }
5420 else if (o->pvar != NULL)
5421 {
5422 if (! t && o->arg == o->notarg)
5423 as_bad (_("option `%s' may not be negated"), s);
5424 *input_line_pointer = c;
5425 *o->pvar = t ? o->arg : o->notarg;
5426 }
5427 else
5428 *input_line_pointer = c;
5429 break;
5430 }
5431 }
5432 if (i >= OPTCOUNT)
5433 {
5434 as_bad (_("option `%s' not recognized"), s);
5435 *input_line_pointer = c;
5436 }
5437 }
5438 while (*input_line_pointer++ == ',');
5439
5440 /* Move back to terminating character. */
5441 --input_line_pointer;
5442 demand_empty_rest_of_line ();
5443}
5444
5445/* Skip ahead to a comma. This is used for OPT options which we do
5446 not suppor tand which take arguments. */
5447
5448static void
5449skip_to_comma (arg, on)
36823076
AS		 5450 int arg ATTRIBUTE_UNUSED;
5451 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5452{
5453 while (*input_line_pointer != ','
5454 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5455 ++input_line_pointer;
5456}
5457
5458/* Handle the OPT NEST=depth option. */
5459
5460static void
5461opt_nest (arg, on)
36823076
AS		 5462 int arg ATTRIBUTE_UNUSED;
5463 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5464{
5465 if (*input_line_pointer != '=')
5466 {
5467 as_bad (_("bad format of OPT NEST=depth"));
5468 return;
5469 }
5470
5471 ++input_line_pointer;
5472 max_macro_nest = get_absolute_expression ();
5473}
5474
5475/* Handle the OPT P=chip option. */
5476
5477static void
5478opt_chip (arg, on)
36823076
AS		 5479 int arg ATTRIBUTE_UNUSED;
5480 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5481{
5482 if (*input_line_pointer != '=')
5483 {
5484 /* This is just OPT P, which we do not support. */
5485 return;
5486 }
5487
5488 ++input_line_pointer;
5489 mri_chip ();
5490}
5491
5492/* Handle the OPT S option. */
5493
5494static void
5495opt_list (arg, on)
36823076 5496 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5497 int on;
5498{
5499 listing_list (on);
5500}
5501
5502/* Handle the OPT T option. */
5503
5504static void
5505opt_list_symbols (arg, on)
36823076 5506 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5507 int on;
5508{
5509 if (on)
5510 listing |= LISTING_SYMBOLS;
5511 else
8a104df9 5512 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5513}
5514
5515/* Handle the MRI REG pseudo-op. */
5516
5517static void
5518s_reg (ignore)
36823076 5519 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5520{
5521 char *s;
5522 int c;
5523 struct m68k_op rop;
5524 int mask;
5525 char *stop = NULL;
5526 char stopc;
5527
5528 if (line_label == NULL)
5529 {
5530 as_bad (_("missing label"));
5531 ignore_rest_of_line ();
5532 return;
5533 }
5534
5535 if (flag_mri)
5536 stop = mri_comment_field (&stopc);
5537
5538 SKIP_WHITESPACE ();
5539
5540 s = input_line_pointer;
3882b010 5541 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5542#ifdef REGISTER_PREFIX
5543 || *input_line_pointer == REGISTER_PREFIX
5544#endif
5545 || *input_line_pointer == '/'
5546 || *input_line_pointer == '-')
5547 ++input_line_pointer;
5548 c = *input_line_pointer;
5549 *input_line_pointer = '\0';
5550
5551 if (m68k_ip_op (s, &rop) != 0)
5552 {
5553 if (rop.error == NULL)
5554 as_bad (_("bad register list"));
5555 else
5556 as_bad (_("bad register list: %s"), rop.error);
5557 *input_line_pointer = c;
5558 ignore_rest_of_line ();
5559 return;
5560 }
5561
5562 *input_line_pointer = c;
5563
5564 if (rop.mode == REGLST)
5565 mask = rop.mask;
5566 else if (rop.mode == DREG)
5567 mask = 1 << (rop.reg - DATA0);
5568 else if (rop.mode == AREG)
5569 mask = 1 << (rop.reg - ADDR0 + 8);
5570 else if (rop.mode == FPREG)
5571 mask = 1 << (rop.reg - FP0 + 16);
5572 else if (rop.mode == CONTROL
5573 && rop.reg == FPI)
5574 mask = 1 << 24;
5575 else if (rop.mode == CONTROL
5576 && rop.reg == FPS)
5577 mask = 1 << 25;
5578 else if (rop.mode == CONTROL
5579 && rop.reg == FPC)
5580 mask = 1 << 26;
5581 else
5582 {
5583 as_bad (_("bad register list"));
5584 ignore_rest_of_line ();
5585 return;
5586 }
5587
5588 S_SET_SEGMENT (line_label, reg_section);
5589 S_SET_VALUE (line_label, ~mask);
49309057 5590 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5591
5592 if (flag_mri)
5593 mri_comment_end (stop, stopc);
5594
5595 demand_empty_rest_of_line ();
5596}
5597
5598/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5599
5600struct save_opts
5601{
5602 struct save_opts *next;
5603 int abspcadd;
5604 int symbols_case_sensitive;
5605 int keep_locals;
5606 int short_refs;
5607 int architecture;
5608 int quick;
5609 int rel32;
5610 int listing;
5611 int no_warnings;
5612 /* FIXME: We don't save OPT S. */
5613};
5614
5615/* This variable holds the stack of saved options. */
5616
5617static struct save_opts *save_stack;
5618
5619/* The MRI SAVE pseudo-op. */
5620
5621static void
5622s_save (ignore)
36823076 5623 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5624{
5625 struct save_opts *s;
5626
5627 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5628 s->abspcadd = m68k_abspcadd;
5629 s->symbols_case_sensitive = symbols_case_sensitive;
5630 s->keep_locals = flag_keep_locals;
5631 s->short_refs = flag_short_refs;
5632 s->architecture = current_architecture;
5633 s->quick = m68k_quick;
5634 s->rel32 = m68k_rel32;
5635 s->listing = listing;
5636 s->no_warnings = flag_no_warnings;
5637
5638 s->next = save_stack;
5639 save_stack = s;
5640
5641 demand_empty_rest_of_line ();
5642}
5643
5644/* The MRI RESTORE pseudo-op. */
5645
5646static void
5647s_restore (ignore)
36823076 5648 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5649{
5650 struct save_opts *s;
5651
5652 if (save_stack == NULL)
5653 {
5654 as_bad (_("restore without save"));
5655 ignore_rest_of_line ();
5656 return;
5657 }
5658
5659 s = save_stack;
5660 save_stack = s->next;
5661
5662 m68k_abspcadd = s->abspcadd;
5663 symbols_case_sensitive = s->symbols_case_sensitive;
5664 flag_keep_locals = s->keep_locals;
5665 flag_short_refs = s->short_refs;
5666 current_architecture = s->architecture;
5667 m68k_quick = s->quick;
5668 m68k_rel32 = s->rel32;
5669 listing = s->listing;
5670 flag_no_warnings = s->no_warnings;
5671
5672 free (s);
5673
5674 demand_empty_rest_of_line ();
5675}
5676
5677/* Types of MRI structured control directives. */
5678
5679enum mri_control_type
5680{
5681 mri_for,
5682 mri_if,
5683 mri_repeat,
5684 mri_while
5685};
5686
5687/* This structure is used to stack the MRI structured control
5688 directives. */
5689
5690struct mri_control_info
5691{
5692 /* The directive within which this one is enclosed. */
5693 struct mri_control_info *outer;
5694
5695 /* The type of directive. */
5696 enum mri_control_type type;
5697
5698 /* Whether an ELSE has been in an IF. */
5699 int else_seen;
5700
5701 /* The add or sub statement at the end of a FOR. */
5702 char *incr;
5703
5704 /* The label of the top of a FOR or REPEAT loop. */
5705 char *top;
5706
5707 /* The label to jump to for the next iteration, or the else
5708 expression of a conditional. */
5709 char *next;
5710
5711 /* The label to jump to to break out of the loop, or the label past
5712 the end of a conditional. */
5713 char *bottom;
5714};
5715
5716/* The stack of MRI structured control directives. */
5717
5718static struct mri_control_info *mri_control_stack;
5719
5720/* The current MRI structured control directive index number, used to
5721 generate label names. */
5722
5723static int mri_control_index;
5724
5725/* Some function prototypes. */
5726
5727static void mri_assemble PARAMS ((char *));
5728static char *mri_control_label PARAMS ((void));
5729static struct mri_control_info *push_mri_control
5730 PARAMS ((enum mri_control_type));
5731static void pop_mri_control PARAMS ((void));
5732static int parse_mri_condition PARAMS ((int *));
5733static int parse_mri_control_operand
5734 PARAMS ((int *, char **, char **, char **, char **));
5735static int swap_mri_condition PARAMS ((int));
5736static int reverse_mri_condition PARAMS ((int));
5737static void build_mri_control_operand
5738 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5739 const char *, int));
5740static void parse_mri_control_expression
5741 PARAMS ((char *, int, const char *, const char *, int));
5742
5743/* Assemble an instruction for an MRI structured control directive. */
5744
5745static void
5746mri_assemble (str)
5747 char *str;
5748{
5749 char *s;
5750
5751 /* md_assemble expects the opcode to be in lower case. */
5752 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5753 *s = TOLOWER (*s);
252b5132
RH		 5754
5755 md_assemble (str);
5756}
5757
5758/* Generate a new MRI label structured control directive label name. */
5759
5760static char *
5761mri_control_label ()
5762{
5763 char *n;
5764
5765 n = (char *) xmalloc (20);
5766 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5767 ++mri_control_index;
5768 return n;
5769}
5770
5771/* Create a new MRI structured control directive. */
5772
5773static struct mri_control_info *
5774push_mri_control (type)
5775 enum mri_control_type type;
5776{
5777 struct mri_control_info *n;
5778
5779 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5780
5781 n->type = type;
5782 n->else_seen = 0;
5783 if (type == mri_if || type == mri_while)
5784 n->top = NULL;
5785 else
5786 n->top = mri_control_label ();
5787 n->next = mri_control_label ();
5788 n->bottom = mri_control_label ();
5789
5790 n->outer = mri_control_stack;
5791 mri_control_stack = n;
5792
5793 return n;
5794}
5795
5796/* Pop off the stack of MRI structured control directives. */
5797
5798static void
5799pop_mri_control ()
5800{
5801 struct mri_control_info *n;
5802
5803 n = mri_control_stack;
5804 mri_control_stack = n->outer;
5805 if (n->top != NULL)
5806 free (n->top);
5807 free (n->next);
5808 free (n->bottom);
5809 free (n);
5810}
5811
5812/* Recognize a condition code in an MRI structured control expression. */
5813
5814static int
5815parse_mri_condition (pcc)
5816 int *pcc;
5817{
5818 char c1, c2;
5819
5820 know (*input_line_pointer == '<');
5821
5822 ++input_line_pointer;
5823 c1 = *input_line_pointer++;
5824 c2 = *input_line_pointer++;
5825
5826 if (*input_line_pointer != '>')
5827 {
5828 as_bad (_("syntax error in structured control directive"));
5829 return 0;
5830 }
5831
5832 ++input_line_pointer;
5833 SKIP_WHITESPACE ();
5834
3882b010
L		 5835 c1 = TOLOWER (c1);
5836 c2 = TOLOWER (c2);
252b5132
RH		 5837
5838 *pcc = (c1 << 8) | c2;
5839
5840 return 1;
5841}
5842
5843/* Parse a single operand in an MRI structured control expression. */
5844
5845static int
5846parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5847 int *pcc;
5848 char **leftstart;
5849 char **leftstop;
5850 char **rightstart;
5851 char **rightstop;
5852{
5853 char *s;
5854
5855 SKIP_WHITESPACE ();
5856
5857 *pcc = -1;
5858 *leftstart = NULL;
5859 *leftstop = NULL;
5860 *rightstart = NULL;
5861 *rightstop = NULL;
5862
5863 if (*input_line_pointer == '<')
5864 {
5865 /* It's just a condition code. */
5866 return parse_mri_condition (pcc);
5867 }
5868
5869 /* Look ahead for the condition code. */
5870 for (s = input_line_pointer; *s != '\0'; ++s)
5871 {
5872 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5873 break;
5874 }
5875 if (*s == '\0')
5876 {
5877 as_bad (_("missing condition code in structured control directive"));
5878 return 0;
5879 }
5880
5881 *leftstart = input_line_pointer;
5882 *leftstop = s;
5883 if (*leftstop > *leftstart
5884 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5885 --*leftstop;
5886
5887 input_line_pointer = s;
5888 if (! parse_mri_condition (pcc))
5889 return 0;
5890
5891 /* Look ahead for AND or OR or end of line. */
5892 for (s = input_line_pointer; *s != '\0'; ++s)
5893 {
e1f44d10
NC		 5894 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5895 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5896 ^^^ ^^ */
8a104df9
KH		 5897 if ((s == input_line_pointer
5898 || *(s-1) == ' '
5899 || *(s-1) == '\t')
5900 && ((strncasecmp (s, "AND", 3) == 0
5901 && (s[3] == '.' || ! is_part_of_name (s[3])))
5902 || (strncasecmp (s, "OR", 2) == 0
5903 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5904 break;
252b5132
RH		 5905 }
5906
5907 *rightstart = input_line_pointer;
5908 *rightstop = s;
5909 if (*rightstop > *rightstart
5910 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5911 --*rightstop;
5912
5913 input_line_pointer = s;
5914
5915 return 1;
5916}
5917
5918#define MCC(b1, b2) (((b1) << 8) | (b2))
5919
5920/* Swap the sense of a condition. This changes the condition so that
5921 it generates the same result when the operands are swapped. */
5922
5923static int
5924swap_mri_condition (cc)
5925 int cc;
5926{
5927 switch (cc)
5928 {
5929 case MCC ('h', 'i'): return MCC ('c', 's');
5930 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 5931 /* <HS> is an alias for <CC>. */
e1f44d10 5932 case MCC ('h', 's'):
252b5132 5933 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 5934 /* <LO> is an alias for <CS>. */
e1f44d10 5935 case MCC ('l', 'o'):
252b5132
RH		 5936 case MCC ('c', 's'): return MCC ('h', 'i');
5937 case MCC ('p', 'l'): return MCC ('m', 'i');
5938 case MCC ('m', 'i'): return MCC ('p', 'l');
5939 case MCC ('g', 'e'): return MCC ('l', 'e');
5940 case MCC ('l', 't'): return MCC ('g', 't');
5941 case MCC ('g', 't'): return MCC ('l', 't');
5942 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 5943 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 5944 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5945 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5946 case MCC ('v', 'c'):
5947 case MCC ('v', 's'):
5948 default :
5949 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5950 (char) (cc >> 8), (char) (cc));
5951 break;
252b5132
RH		 5952 }
5953 return cc;
5954}
5955
5956/* Reverse the sense of a condition. */
5957
5958static int
5959reverse_mri_condition (cc)
5960 int cc;
5961{
5962 switch (cc)
5963 {
5964 case MCC ('h', 'i'): return MCC ('l', 's');
5965 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5966 /* <HS> is an alias for <CC> */
5967 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5968 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5969 /* <LO> is an alias for <CS> */
5970 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5971 case MCC ('c', 's'): return MCC ('c', 'c');
5972 case MCC ('n', 'e'): return MCC ('e', 'q');
5973 case MCC ('e', 'q'): return MCC ('n', 'e');
5974 case MCC ('v', 'c'): return MCC ('v', 's');
5975 case MCC ('v', 's'): return MCC ('v', 'c');
5976 case MCC ('p', 'l'): return MCC ('m', 'i');
5977 case MCC ('m', 'i'): return MCC ('p', 'l');
5978 case MCC ('g', 'e'): return MCC ('l', 't');
5979 case MCC ('l', 't'): return MCC ('g', 'e');
5980 case MCC ('g', 't'): return MCC ('l', 'e');
5981 case MCC ('l', 'e'): return MCC ('g', 't');
5982 }
5983 return cc;
5984}
5985
5986/* Build an MRI structured control expression. This generates test
5987 and branch instructions. It goes to TRUELAB if the condition is
5988 true, and to FALSELAB if the condition is false. Exactly one of
5989 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5990 is the size qualifier for the expression. EXTENT is the size to
5991 use for the branch. */
5992
5993static void
5994build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5995 rightstop, truelab, falselab, extent)
5996 int qual;
5997 int cc;
5998 char *leftstart;
5999 char *leftstop;
6000 char *rightstart;
6001 char *rightstop;
6002 const char *truelab;
6003 const char *falselab;
6004 int extent;
6005{
6006 char *buf;
6007 char *s;
6008
6009 if (leftstart != NULL)
6010 {
6011 struct m68k_op leftop, rightop;
6012 char c;
6013
6014 /* Swap the compare operands, if necessary, to produce a legal
6015 m68k compare instruction. Comparing a register operand with
6016 a non-register operand requires the register to be on the
6017 right (cmp, cmpa). Comparing an immediate value with
6018 anything requires the immediate value to be on the left
6019 (cmpi). */
6020
6021 c = *leftstop;
6022 *leftstop = '\0';
6023 (void) m68k_ip_op (leftstart, &leftop);
6024 *leftstop = c;
6025
6026 c = *rightstop;
6027 *rightstop = '\0';
6028 (void) m68k_ip_op (rightstart, &rightop);
6029 *rightstop = c;
6030
6031 if (rightop.mode == IMMED
6032 || ((leftop.mode == DREG || leftop.mode == AREG)
6033 && (rightop.mode != DREG && rightop.mode != AREG)))
6034 {
6035 char *temp;
6036
e1f44d10
NC		 6037 /* Correct conditional handling:
6038 if #1 <lt> d0 then ;means if (1 < d0)
6039 ...
6040 endi
6041
6042 should assemble to:
6043
6044 cmp #1,d0 if we do *not* swap the operands
6045 bgt true we need the swapped condition!
6046 ble false
6047 true:
6048 ...
6049 false:
6050 */
252b5132
RH		 6051 temp = leftstart;
6052 leftstart = rightstart;
6053 rightstart = temp;
6054 temp = leftstop;
6055 leftstop = rightstop;
6056 rightstop = temp;
8a104df9
KH		 6057 }
6058 else
6059 {
e1f44d10 6060 cc = swap_mri_condition (cc);
252b5132
RH		 6061 }
6062 }
6063
6064 if (truelab == NULL)
6065 {
6066 cc = reverse_mri_condition (cc);
6067 truelab = falselab;
6068 }
92774660 6069
252b5132
RH		 6070 if (leftstart != NULL)
6071 {
6072 buf = (char *) xmalloc (20
6073 + (leftstop - leftstart)
6074 + (rightstop - rightstart));
6075 s = buf;
6076 *s++ = 'c';
6077 *s++ = 'm';
6078 *s++ = 'p';
6079 if (qual != '\0')
3882b010 6080 *s++ = TOLOWER (qual);
252b5132
RH		 6081 *s++ = ' ';
6082 memcpy (s, leftstart, leftstop - leftstart);
6083 s += leftstop - leftstart;
6084 *s++ = ',';
6085 memcpy (s, rightstart, rightstop - rightstart);
6086 s += rightstop - rightstart;
6087 *s = '\0';
6088 mri_assemble (buf);
6089 free (buf);
6090 }
92774660 6091
252b5132
RH		 6092 buf = (char *) xmalloc (20 + strlen (truelab));
6093 s = buf;
6094 *s++ = 'b';
6095 *s++ = cc >> 8;
6096 *s++ = cc & 0xff;
6097 if (extent != '\0')
3882b010 6098 *s++ = TOLOWER (extent);
252b5132
RH		 6099 *s++ = ' ';
6100 strcpy (s, truelab);
6101 mri_assemble (buf);
6102 free (buf);
6103}
6104
6105/* Parse an MRI structured control expression. This generates test
6106 and branch instructions. STOP is where the expression ends. It
6107 goes to TRUELAB if the condition is true, and to FALSELAB if the
6108 condition is false. Exactly one of TRUELAB and FALSELAB will be
6109 NULL, meaning to fall through. QUAL is the size qualifier for the
6110 expression. EXTENT is the size to use for the branch. */
6111
6112static void
6113parse_mri_control_expression (stop, qual, truelab, falselab, extent)
6114 char *stop;
6115 int qual;
6116 const char *truelab;
6117 const char *falselab;
6118 int extent;
6119{
6120 int c;
6121 int cc;
6122 char *leftstart;
6123 char *leftstop;
6124 char *rightstart;
6125 char *rightstop;
6126
6127 c = *stop;
6128 *stop = '\0';
6129
6130 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6131 &rightstart, &rightstop))
6132 {
6133 *stop = c;
6134 return;
6135 }
6136
6137 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6138 {
6139 const char *flab;
6140
6141 if (falselab != NULL)
6142 flab = falselab;
6143 else
6144 flab = mri_control_label ();
6145
6146 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6147 rightstop, (const char *) NULL, flab, extent);
6148
6149 input_line_pointer += 3;
6150 if (*input_line_pointer != '.'
6151 || input_line_pointer[1] == '\0')
6152 qual = '\0';
6153 else
6154 {
6155 qual = input_line_pointer[1];
6156 input_line_pointer += 2;
6157 }
6158
6159 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6160 &rightstart, &rightstop))
6161 {
6162 *stop = c;
6163 return;
6164 }
6165
6166 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6167 rightstop, truelab, falselab, extent);
6168
6169 if (falselab == NULL)
6170 colon (flab);
6171 }
6172 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6173 {
6174 const char *tlab;
6175
6176 if (truelab != NULL)
6177 tlab = truelab;
6178 else
6179 tlab = mri_control_label ();
6180
6181 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6182 rightstop, tlab, (const char *) NULL, extent);
6183
6184 input_line_pointer += 2;
6185 if (*input_line_pointer != '.'
6186 || input_line_pointer[1] == '\0')
6187 qual = '\0';
6188 else
6189 {
6190 qual = input_line_pointer[1];
6191 input_line_pointer += 2;
6192 }
6193
6194 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6195 &rightstart, &rightstop))
6196 {
6197 *stop = c;
6198 return;
6199 }
6200
6201 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6202 rightstop, truelab, falselab, extent);
6203
6204 if (truelab == NULL)
6205 colon (tlab);
6206 }
6207 else
6208 {
6209 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6210 rightstop, truelab, falselab, extent);
6211 }
6212
6213 *stop = c;
6214 if (input_line_pointer != stop)
6215 as_bad (_("syntax error in structured control directive"));
6216}
6217
6218/* Handle the MRI IF pseudo-op. This may be a structured control
6219 directive, or it may be a regular assembler conditional, depending
6220 on its operands. */
6221
6222static void
6223s_mri_if (qual)
6224 int qual;
6225{
6226 char *s;
6227 int c;
6228 struct mri_control_info *n;
6229
6230 /* A structured control directive must end with THEN with an
6231 optional qualifier. */
6232 s = input_line_pointer;
e1f44d10
NC		 6233 /* We only accept '*' as introduction of comments if preceded by white space
6234 or at first column of a line (I think this can't actually happen here?)
6235 This is important when assembling:
6236 if d0 <ne> 12(a0,d0*2) then
36759679 6237 if d0 <ne> #CONST*20 then. */
e1f44d10
NC		 6238 while ( ! ( is_end_of_line[(unsigned char) *s]
6239 || ( flag_mri
6240 && *s == '*'
6241 && ( s == input_line_pointer
6242 || *(s-1) == ' '
6243 || *(s-1) == '\t'))))
252b5132
RH		 6244 ++s;
6245 --s;
6246 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6247 --s;
6248
6249 if (s - input_line_pointer > 1
6250 && s[-1] == '.')
6251 s -= 2;
6252
6253 if (s - input_line_pointer < 3
6254 || strncasecmp (s - 3, "THEN", 4) != 0)
6255 {
6256 if (qual != '\0')
6257 {
6258 as_bad (_("missing then"));
6259 ignore_rest_of_line ();
6260 return;
6261 }
6262
6263 /* It's a conditional. */
6264 s_if (O_ne);
6265 return;
6266 }
6267
6268 /* Since this might be a conditional if, this pseudo-op will be
6269 called even if we are supported to be ignoring input. Double
6270 check now. Clobber *input_line_pointer so that ignore_input
6271 thinks that this is not a special pseudo-op. */
6272 c = *input_line_pointer;
6273 *input_line_pointer = 0;
6274 if (ignore_input ())
6275 {
6276 *input_line_pointer = c;
6277 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6278 ++input_line_pointer;
6279 demand_empty_rest_of_line ();
6280 return;
6281 }
6282 *input_line_pointer = c;
6283
6284 n = push_mri_control (mri_if);
6285
6286 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6287 n->next, s[1] == '.' ? s[2] : '\0');
6288
6289 if (s[1] == '.')
6290 input_line_pointer = s + 3;
6291 else
6292 input_line_pointer = s + 1;
6293
6294 if (flag_mri)
6295 {
6296 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6297 ++input_line_pointer;
6298 }
6299
6300 demand_empty_rest_of_line ();
6301}
6302
6303/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6304 structured IF, associate the ELSE with the IF. Otherwise, assume
6305 it is a conditional else. */
6306
6307static void
6308s_mri_else (qual)
6309 int qual;
6310{
6311 int c;
6312 char *buf;
6313 char q[2];
6314
6315 if (qual == '\0'
6316 && (mri_control_stack == NULL
6317 || mri_control_stack->type != mri_if
6318 || mri_control_stack->else_seen))
6319 {
6320 s_else (0);
6321 return;
6322 }
6323
6324 c = *input_line_pointer;
6325 *input_line_pointer = 0;
6326 if (ignore_input ())
6327 {
6328 *input_line_pointer = c;
6329 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6330 ++input_line_pointer;
6331 demand_empty_rest_of_line ();
6332 return;
6333 }
6334 *input_line_pointer = c;
6335
6336 if (mri_control_stack == NULL
6337 || mri_control_stack->type != mri_if
6338 || mri_control_stack->else_seen)
6339 {
6340 as_bad (_("else without matching if"));
6341 ignore_rest_of_line ();
6342 return;
6343 }
6344
6345 mri_control_stack->else_seen = 1;
6346
6347 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6348 q[0] = TOLOWER (qual);
252b5132
RH		 6349 q[1] = '\0';
6350 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6351 mri_assemble (buf);
6352 free (buf);
6353
6354 colon (mri_control_stack->next);
6355
6356 if (flag_mri)
6357 {
6358 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6359 ++input_line_pointer;
6360 }
6361
6362 demand_empty_rest_of_line ();
6363}
6364
6365/* Handle the MRI ENDI pseudo-op. */
6366
6367static void
6368s_mri_endi (ignore)
36823076 6369 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6370{
6371 if (mri_control_stack == NULL
6372 || mri_control_stack->type != mri_if)
6373 {
6374 as_bad (_("endi without matching if"));
6375 ignore_rest_of_line ();
6376 return;
6377 }
6378
6379 /* ignore_input will not return true for ENDI, so we don't need to
6380 worry about checking it again here. */
6381
6382 if (! mri_control_stack->else_seen)
6383 colon (mri_control_stack->next);
6384 colon (mri_control_stack->bottom);
6385
6386 pop_mri_control ();
6387
6388 if (flag_mri)
6389 {
6390 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6391 ++input_line_pointer;
6392 }
6393
6394 demand_empty_rest_of_line ();
6395}
6396
6397/* Handle the MRI BREAK pseudo-op. */
6398
6399static void
6400s_mri_break (extent)
6401 int extent;
6402{
6403 struct mri_control_info *n;
6404 char *buf;
6405 char ex[2];
6406
6407 n = mri_control_stack;
6408 while (n != NULL
6409 && n->type != mri_for
6410 && n->type != mri_repeat
6411 && n->type != mri_while)
6412 n = n->outer;
6413 if (n == NULL)
6414 {
6415 as_bad (_("break outside of structured loop"));
6416 ignore_rest_of_line ();
6417 return;
6418 }
6419
6420 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6421 ex[0] = TOLOWER (extent);
252b5132
RH		 6422 ex[1] = '\0';
6423 sprintf (buf, "bra%s %s", ex, n->bottom);
6424 mri_assemble (buf);
6425 free (buf);
6426
6427 if (flag_mri)
6428 {
6429 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6430 ++input_line_pointer;
6431 }
6432
6433 demand_empty_rest_of_line ();
6434}
6435
6436/* Handle the MRI NEXT pseudo-op. */
6437
6438static void
6439s_mri_next (extent)
6440 int extent;
6441{
6442 struct mri_control_info *n;
6443 char *buf;
6444 char ex[2];
6445
6446 n = mri_control_stack;
6447 while (n != NULL
6448 && n->type != mri_for
6449 && n->type != mri_repeat
6450 && n->type != mri_while)
6451 n = n->outer;
6452 if (n == NULL)
6453 {
6454 as_bad (_("next outside of structured loop"));
6455 ignore_rest_of_line ();
6456 return;
6457 }
6458
6459 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6460 ex[0] = TOLOWER (extent);
252b5132
RH		 6461 ex[1] = '\0';
6462 sprintf (buf, "bra%s %s", ex, n->next);
6463 mri_assemble (buf);
6464 free (buf);
6465
6466 if (flag_mri)
6467 {
6468 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6469 ++input_line_pointer;
6470 }
6471
6472 demand_empty_rest_of_line ();
6473}
6474
6475/* Handle the MRI FOR pseudo-op. */
6476
6477static void
6478s_mri_for (qual)
6479 int qual;
6480{
6481 const char *varstart, *varstop;
6482 const char *initstart, *initstop;
6483 const char *endstart, *endstop;
6484 const char *bystart, *bystop;
6485 int up;
6486 int by;
6487 int extent;
6488 struct mri_control_info *n;
6489 char *buf;
6490 char *s;
6491 char ex[2];
6492
6493 /* The syntax is
6494 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6495 */
6496
6497 SKIP_WHITESPACE ();
6498 varstart = input_line_pointer;
6499
6500 /* Look for the '='. */
6501 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6502 && *input_line_pointer != '=')
6503 ++input_line_pointer;
6504 if (*input_line_pointer != '=')
6505 {
6506 as_bad (_("missing ="));
6507 ignore_rest_of_line ();
6508 return;
6509 }
6510
6511 varstop = input_line_pointer;
6512 if (varstop > varstart
6513 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6514 --varstop;
6515
6516 ++input_line_pointer;
6517
6518 initstart = input_line_pointer;
6519
6520 /* Look for TO or DOWNTO. */
6521 up = 1;
6522 initstop = NULL;
6523 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6524 {
6525 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6526 && ! is_part_of_name (input_line_pointer[2]))
6527 {
6528 initstop = input_line_pointer;
6529 input_line_pointer += 2;
6530 break;
6531 }
6532 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6533 && ! is_part_of_name (input_line_pointer[6]))
6534 {
6535 initstop = input_line_pointer;
6536 up = 0;
6537 input_line_pointer += 6;
6538 break;
6539 }
6540 ++input_line_pointer;
6541 }
6542 if (initstop == NULL)
6543 {
6544 as_bad (_("missing to or downto"));
6545 ignore_rest_of_line ();
6546 return;
6547 }
6548 if (initstop > initstart
6549 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6550 --initstop;
6551
6552 SKIP_WHITESPACE ();
6553 endstart = input_line_pointer;
6554
6555 /* Look for BY or DO. */
6556 by = 0;
6557 endstop = NULL;
6558 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6559 {
6560 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6561 && ! is_part_of_name (input_line_pointer[2]))
6562 {
6563 endstop = input_line_pointer;
6564 by = 1;
6565 input_line_pointer += 2;
6566 break;
6567 }
6568 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6569 && (input_line_pointer[2] == '.'
6570 || ! is_part_of_name (input_line_pointer[2])))
6571 {
6572 endstop = input_line_pointer;
6573 input_line_pointer += 2;
6574 break;
6575 }
6576 ++input_line_pointer;
6577 }
6578 if (endstop == NULL)
6579 {
6580 as_bad (_("missing do"));
6581 ignore_rest_of_line ();
6582 return;
6583 }
6584 if (endstop > endstart
6585 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6586 --endstop;
6587
6588 if (! by)
6589 {
6590 bystart = "#1";
6591 bystop = bystart + 2;
6592 }
6593 else
6594 {
6595 SKIP_WHITESPACE ();
6596 bystart = input_line_pointer;
6597
6598 /* Look for DO. */
6599 bystop = NULL;
6600 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6601 {
6602 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6603 && (input_line_pointer[2] == '.'
6604 || ! is_part_of_name (input_line_pointer[2])))
6605 {
6606 bystop = input_line_pointer;
6607 input_line_pointer += 2;
6608 break;
6609 }
6610 ++input_line_pointer;
6611 }
6612 if (bystop == NULL)
6613 {
6614 as_bad (_("missing do"));
6615 ignore_rest_of_line ();
6616 return;
6617 }
6618 if (bystop > bystart
6619 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6620 --bystop;
6621 }
6622
6623 if (*input_line_pointer != '.')
6624 extent = '\0';
6625 else
6626 {
6627 extent = input_line_pointer[1];
6628 input_line_pointer += 2;
6629 }
6630
6631 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6632 n = push_mri_control (mri_for);
6633
6634 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6635
36759679 6636 /* Move init,var. */
252b5132
RH		 6637 s = buf;
6638 *s++ = 'm';
6639 *s++ = 'o';
6640 *s++ = 'v';
6641 *s++ = 'e';
6642 if (qual != '\0')
3882b010 6643 *s++ = TOLOWER (qual);
252b5132
RH		 6644 *s++ = ' ';
6645 memcpy (s, initstart, initstop - initstart);
6646 s += initstop - initstart;
6647 *s++ = ',';
6648 memcpy (s, varstart, varstop - varstart);
6649 s += varstop - varstart;
6650 *s = '\0';
6651 mri_assemble (buf);
6652
6653 colon (n->top);
6654
36759679 6655 /* cmp end,var. */
252b5132
RH		 6656 s = buf;
6657 *s++ = 'c';
6658 *s++ = 'm';
6659 *s++ = 'p';
6660 if (qual != '\0')
3882b010 6661 *s++ = TOLOWER (qual);
252b5132
RH		 6662 *s++ = ' ';
6663 memcpy (s, endstart, endstop - endstart);
6664 s += endstop - endstart;
6665 *s++ = ',';
6666 memcpy (s, varstart, varstop - varstart);
6667 s += varstop - varstart;
6668 *s = '\0';
6669 mri_assemble (buf);
6670
36759679 6671 /* bcc bottom. */
3882b010 6672 ex[0] = TOLOWER (extent);
252b5132
RH		 6673 ex[1] = '\0';
6674 if (up)
6675 sprintf (buf, "blt%s %s", ex, n->bottom);
6676 else
6677 sprintf (buf, "bgt%s %s", ex, n->bottom);
6678 mri_assemble (buf);
6679
6680 /* Put together the add or sub instruction used by ENDF. */
6681 s = buf;
6682 if (up)
6683 strcpy (s, "add");
6684 else
6685 strcpy (s, "sub");
6686 s += 3;
6687 if (qual != '\0')
3882b010 6688 *s++ = TOLOWER (qual);
252b5132
RH		 6689 *s++ = ' ';
6690 memcpy (s, bystart, bystop - bystart);
6691 s += bystop - bystart;
6692 *s++ = ',';
6693 memcpy (s, varstart, varstop - varstart);
6694 s += varstop - varstart;
6695 *s = '\0';
6696 n->incr = buf;
6697
6698 if (flag_mri)
6699 {
6700 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6701 ++input_line_pointer;
6702 }
6703
6704 demand_empty_rest_of_line ();
6705}
6706
6707/* Handle the MRI ENDF pseudo-op. */
6708
6709static void
6710s_mri_endf (ignore)
36823076 6711 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6712{
6713 if (mri_control_stack == NULL
6714 || mri_control_stack->type != mri_for)
6715 {
6716 as_bad (_("endf without for"));
6717 ignore_rest_of_line ();
6718 return;
6719 }
6720
6721 colon (mri_control_stack->next);
6722
6723 mri_assemble (mri_control_stack->incr);
6724
6725 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6726 mri_assemble (mri_control_stack->incr);
6727
6728 free (mri_control_stack->incr);
6729
6730 colon (mri_control_stack->bottom);
6731
6732 pop_mri_control ();
6733
6734 if (flag_mri)
6735 {
6736 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6737 ++input_line_pointer;
6738 }
6739
6740 demand_empty_rest_of_line ();
6741}
6742
6743/* Handle the MRI REPEAT pseudo-op. */
6744
6745static void
6746s_mri_repeat (ignore)
36823076 6747 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6748{
6749 struct mri_control_info *n;
6750
6751 n = push_mri_control (mri_repeat);
6752 colon (n->top);
6753 if (flag_mri)
6754 {
6755 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6756 ++input_line_pointer;
6757 }
6758 demand_empty_rest_of_line ();
6759}
6760
6761/* Handle the MRI UNTIL pseudo-op. */
6762
6763static void
6764s_mri_until (qual)
6765 int qual;
6766{
6767 char *s;
6768
6769 if (mri_control_stack == NULL
6770 || mri_control_stack->type != mri_repeat)
6771 {
6772 as_bad (_("until without repeat"));
6773 ignore_rest_of_line ();
6774 return;
6775 }
6776
6777 colon (mri_control_stack->next);
6778
6779 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6780 ;
6781
6782 parse_mri_control_expression (s, qual, (const char *) NULL,
6783 mri_control_stack->top, '\0');
6784
6785 colon (mri_control_stack->bottom);
6786
6787 input_line_pointer = s;
6788
6789 pop_mri_control ();
6790
6791 if (flag_mri)
6792 {
6793 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6794 ++input_line_pointer;
6795 }
6796
6797 demand_empty_rest_of_line ();
6798}
6799
6800/* Handle the MRI WHILE pseudo-op. */
6801
6802static void
6803s_mri_while (qual)
6804 int qual;
6805{
6806 char *s;
6807
6808 struct mri_control_info *n;
6809
6810 s = input_line_pointer;
e1f44d10
NC		 6811 /* We only accept '*' as introduction of comments if preceded by white space
6812 or at first column of a line (I think this can't actually happen here?)
6813 This is important when assembling:
6814 while d0 <ne> 12(a0,d0*2) do
36759679 6815 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6816 while (! (is_end_of_line[(unsigned char) *s]
6817 || (flag_mri
6818 && *s == '*'
6819 && (s == input_line_pointer
6820 || *(s-1) == ' '
6821 || *(s-1) == '\t'))))
252b5132
RH		 6822 s++;
6823 --s;
6824 while (*s == ' ' || *s == '\t')
6825 --s;
6826 if (s - input_line_pointer > 1
6827 && s[-1] == '.')
6828 s -= 2;
6829 if (s - input_line_pointer < 2
6830 || strncasecmp (s - 1, "DO", 2) != 0)
6831 {
6832 as_bad (_("missing do"));
6833 ignore_rest_of_line ();
6834 return;
6835 }
6836
6837 n = push_mri_control (mri_while);
6838
6839 colon (n->next);
6840
6841 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6842 s[1] == '.' ? s[2] : '\0');
6843
6844 input_line_pointer = s + 1;
6845 if (*input_line_pointer == '.')
6846 input_line_pointer += 2;
6847
6848 if (flag_mri)
6849 {
6850 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6851 ++input_line_pointer;
6852 }
6853
6854 demand_empty_rest_of_line ();
6855}
6856
6857/* Handle the MRI ENDW pseudo-op. */
6858
6859static void
6860s_mri_endw (ignore)
36823076 6861 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6862{
6863 char *buf;
6864
6865 if (mri_control_stack == NULL
6866 || mri_control_stack->type != mri_while)
6867 {
6868 as_bad (_("endw without while"));
6869 ignore_rest_of_line ();
6870 return;
6871 }
6872
6873 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6874 sprintf (buf, "bra %s", mri_control_stack->next);
6875 mri_assemble (buf);
6876 free (buf);
6877
6878 colon (mri_control_stack->bottom);
6879
6880 pop_mri_control ();
6881
6882 if (flag_mri)
6883 {
6884 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6885 ++input_line_pointer;
6886 }
6887
6888 demand_empty_rest_of_line ();
6889}
6890\f
6891/*
6892 * md_parse_option
6893 * Invocation line includes a switch not recognized by the base assembler.
6894 * See if it's a processor-specific option. These are:
6895 *
6896 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6897 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6898 * Select the architecture. Instructions or features not
6899 * supported by the selected architecture cause fatal
6900 * errors. More than one may be specified. The default is
6901 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6902 * for -m68000, and -m68882 is a synonym for -m68881.
6903 * -[A]m[c]no-68851, -[A]m[c]no-68881
6904 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6905 * so don't use or document it, but that's the way the parsing
6906 * works).
6907 *
6908 * -pic Indicates PIC.
6909 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6910 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6911 *
6912 * --bitwise-or
6913 * Permit `|' to be used in expressions.
6914 *
6915 */
6916
6917#ifdef OBJ_ELF
5a38dc70 6918const char *md_shortopts = "lSA:m:kQ:V";
252b5132 6919#else
5a38dc70 6920const char *md_shortopts = "lSA:m:k";
252b5132
RH		 6921#endif
6922
6923struct option md_longopts[] = {
6924#define OPTION_PIC (OPTION_MD_BASE)
6925 {"pic", no_argument, NULL, OPTION_PIC},
6926#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6927 {"register-prefix-optional", no_argument, NULL,
6928 OPTION_REGISTER_PREFIX_OPTIONAL},
6929#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6930 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6931#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6932 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6933#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6934 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6935#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6936 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6937#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6938 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6939#define OPTION_PCREL (OPTION_MD_BASE + 7)
6940 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6941 {NULL, no_argument, NULL, 0}
6942};
bc805888 6943size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6944
6945int
6946md_parse_option (c, arg)
6947 int c;
6948 char *arg;
6949{
6950 switch (c)
6951 {
6952 case 'l': /* -l means keep external to 2 bit offset
36759679 6953 rather than 16 bit one. */
252b5132
RH		 6954 flag_short_refs = 1;
6955 break;
6956
6957 case 'S': /* -S means that jbsr's always turn into
6958 jsr's. */
6959 flag_long_jumps = 1;
6960 break;
6961
28e7409f
NC		 6962 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6963 branches into absolute jumps. */
6964 flag_keep_pcrel = 1;
6965 break;
6966
252b5132
RH		 6967 case 'A':
6968 if (*arg == 'm')
8a104df9 6969 arg++;
36759679 6970 /* Intentional fall-through. */
252b5132
RH		 6971 case 'm':
6972
6973 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6974 {
6975 int i;
6976 unsigned long arch;
6977 const char *oarg = arg;
6978
6979 arg += 3;
6980 if (*arg == 'm')
6981 {
6982 arg++;
6983 if (arg[0] == 'c' && arg[1] == '6')
6984 arg++;
6985 }
6986 for (i = 0; i < n_archs; i++)
6987 if (!strcmp (arg, archs[i].name))
6988 break;
6989 if (i == n_archs)
6990 {
6991 unknown:
6992 as_bad (_("unrecognized option `%s'"), oarg);
6993 return 0;
6994 }
6995 arch = archs[i].arch;
6996 if (arch == m68881)
6997 no_68881 = 1;
6998 else if (arch == m68851)
6999 no_68851 = 1;
7000 else
7001 goto unknown;
7002 }
7003 else
7004 {
7005 int i;
7006
7007 if (arg[0] == 'c' && arg[1] == '6')
7008 arg++;
7009
7010 for (i = 0; i < n_archs; i++)
7011 if (!strcmp (arg, archs[i].name))
7012 {
7013 unsigned long arch = archs[i].arch;
7014 if (cpu_of_arch (arch))
7015 /* It's a cpu spec. */
7016 {
7017 current_architecture &= ~m68000up;
7018 current_architecture |= arch;
7019 }
7020 else if (arch == m68881)
7021 {
7022 current_architecture |= m68881;
7023 no_68881 = 0;
7024 }
7025 else if (arch == m68851)
7026 {
7027 current_architecture |= m68851;
7028 no_68851 = 0;
7029 }
7030 else
7031 /* ??? */
7032 abort ();
7033 break;
7034 }
7035 if (i == n_archs)
7036 {
7037 as_bad (_("unrecognized architecture specification `%s'"), arg);
7038 return 0;
7039 }
7040 }
7041 break;
7042
7043 case OPTION_PIC:
7044 case 'k':
7045 flag_want_pic = 1;
36759679 7046 break; /* -pic, Position Independent Code. */
252b5132
RH		 7047
7048 case OPTION_REGISTER_PREFIX_OPTIONAL:
7049 flag_reg_prefix_optional = 1;
7050 reg_prefix_optional_seen = 1;
7051 break;
7052
7053 /* -V: SVR4 argument to print version ID. */
7054 case 'V':
7055 print_version_id ();
7056 break;
7057
7058 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7059 should be emitted or not. FIXME: Not implemented. */
7060 case 'Q':
7061 break;
7062
7063 case OPTION_BITWISE_OR:
7064 {
7065 char *n, *t;
7066 const char *s;
7067
7068 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7069 t = n;
7070 for (s = m68k_comment_chars; *s != '\0'; s++)
7071 if (*s != '|')
7072 *t++ = *s;
7073 *t = '\0';
7074 m68k_comment_chars = n;
7075 }
7076 break;
7077
7078 case OPTION_BASE_SIZE_DEFAULT_16:
7079 m68k_index_width_default = SIZE_WORD;
7080 break;
7081
7082 case OPTION_BASE_SIZE_DEFAULT_32:
7083 m68k_index_width_default = SIZE_LONG;
7084 break;
7085
7086 case OPTION_DISP_SIZE_DEFAULT_16:
7087 m68k_rel32 = 0;
7088 m68k_rel32_from_cmdline = 1;
7089 break;
7090
7091 case OPTION_DISP_SIZE_DEFAULT_32:
7092 m68k_rel32 = 1;
7093 m68k_rel32_from_cmdline = 1;
7094 break;
7095
7096 default:
7097 return 0;
7098 }
7099
7100 return 1;
7101}
7102
7103void
7104md_show_usage (stream)
7105 FILE *stream;
7106{
76f57f3a 7107 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7108 int i;
7109 unsigned int default_arch;
76f57f3a 7110
8a104df9 7111 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7112 if (*default_cpu == 'm')
7113 default_cpu++;
7114 for (i = 0; i < n_archs; i++)
7115 {
7116 if (strcasecmp (default_cpu, archs[i].name) == 0)
7117 {
7118 default_arch = archs[i].arch;
7119 for (i = 0; i < n_archs; i++)
7120 {
7121 if (archs[i].arch == default_arch
7122 && !archs[i].alias)
7123 {
7124 default_cpu = archs[i].name;
7125 break;
7126 }
7127 }
7128 }
7129 }
7130
bc805888 7131 fprintf (stream, _("\
252b5132
RH		 7132680X0 options:\n\
7133-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 7134-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7135-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
3e602632
NC		 7136-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m528x | -m5307 |\n\
7137-m5407 | -mcfv4 | -mcfv4e\n\
76f57f3a 7138 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 7139-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7140 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 7141 [default yes for 68020, 68030, and cpu32]\n"),
7142 default_cpu);
bc805888 7143 fprintf (stream, _("\
252b5132
RH		 7144-m68851 | -mno-68851\n\
7145 target has/lacks memory-management unit coprocessor\n\
7146 [default yes for 68020 and up]\n\
7147-pic, -k generate position independent code\n\
7148-S turn jbsr into jsr\n\
28e7409f 7149--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7150--register-prefix-optional\n\
7151 recognize register names without prefix character\n\
7152--bitwise-or do not treat `|' as a comment character\n"));
7153 fprintf (stream, _("\
7154--base-size-default-16 base reg without size is 16 bits\n\
7155--base-size-default-32 base reg without size is 32 bits (default)\n\
7156--disp-size-default-16 displacement with unknown size is 16 bits\n\
7157--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7158}
7159\f
7160#ifdef TEST2
7161
7162/* TEST2: Test md_assemble() */
36759679
NC		 7163/* Warning, this routine probably doesn't work anymore. */
7164int
252b5132
RH		 7165main ()
7166{
7167 struct m68k_it the_ins;
7168 char buf[120];
7169 char *cp;
7170 int n;
7171
7172 m68k_ip_begin ();
7173 for (;;)
7174 {
7175 if (!gets (buf) || !*buf)
7176 break;
7177 if (buf[0] == '|' || buf[1] == '.')
7178 continue;
7179 for (cp = buf; *cp; cp++)
7180 if (*cp == '\t')
7181 *cp = ' ';
7182 if (is_label (buf))
7183 continue;
7184 memset (&the_ins, '\0', sizeof (the_ins));
7185 m68k_ip (&the_ins, buf);
7186 if (the_ins.error)
7187 {
7188 printf (_("Error %s in %s\n"), the_ins.error, buf);
7189 }
7190 else
7191 {
7192 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7193 for (n = 0; n < the_ins.numo; n++)
7194 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7195 printf (" ");
7196 print_the_insn (&the_ins.opcode[0], stdout);
7197 (void) putchar ('\n');
7198 }
7199 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7200 {
7201 if (the_ins.operands[n].error)
7202 {
7203 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7204 continue;
7205 }
7206 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7207 if (the_ins.operands[n].b_const)
7208 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7209 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7210 if (the_ins.operands[n].b_iadd)
7211 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7212 (void) putchar ('\n');
7213 }
7214 }
7215 m68k_ip_end ();
7216 return 0;
7217}
7218
7219is_label (str)
7220 char *str;
7221{
7222 while (*str == ' ')
7223 str++;
7224 while (*str && *str != ' ')
7225 str++;
7226 if (str[-1] == ':' || str[1] == '=')
7227 return 1;
7228 return 0;
7229}
7230
7231#endif
7232
7233/* Possible states for relaxation:
7234
7235 0 0 branch offset byte (bra, etc)
7236 0 1 word
7237 0 2 long
7238
7239 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7240 1 1 word
7241 1 2 long
7242
7243 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7244 2 1 word-long
7245 2 2 long-word
7246 2 3 long-long
7247
7248 */
7249
7250/* We have no need to default values of symbols. */
7251
252b5132
RH		 7252symbolS *
7253md_undefined_symbol (name)
36823076 7254 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7255{
7256 return 0;
7257}
7258
7259/* Round up a section size to the appropriate boundary. */
7260valueT
7261md_section_align (segment, size)
36823076 7262 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7263 valueT size;
7264{
7265#ifdef OBJ_AOUT
7266#ifdef BFD_ASSEMBLER
7267 /* For a.out, force the section size to be aligned. If we don't do
7268 this, BFD will align it for us, but it will not write out the
7269 final bytes of the section. This may be a bug in BFD, but it is
7270 easier to fix it here since that is how the other a.out targets
7271 work. */
7272 int align;
7273
7274 align = bfd_get_section_alignment (stdoutput, segment);
7275 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7276#endif
7277#endif
7278
7279 return size;
7280}
7281
7282/* Exactly what point is a PC-relative offset relative TO?
7283 On the 68k, it is relative to the address of the first extension
7284 word. The difference between the addresses of the offset and the
92774660 7285 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7286long
7287md_pcrel_from (fixP)
7288 fixS *fixP;
7289{
7290 int adjust;
7291
8390138c
AS		 7292 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7293 sign extend the value here. */
7294 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7295 if (adjust == 64)
7296 adjust = -1;
7297 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7298}
7299
7300#ifndef BFD_ASSEMBLER
7301#ifdef OBJ_COFF
7302
252b5132
RH		 7303void
7304tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7305 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7306{
7307}
7308
7309int
7310tc_coff_sizemachdep (frag)
7311 fragS *frag;
7312{
7313 switch (frag->fr_subtype & 0x3)
7314 {
7315 case BYTE:
7316 return 1;
7317 case SHORT:
7318 return 2;
7319 case LONG:
7320 return 4;
7321 default:
7322 abort ();
7323 return 0;
7324 }
7325}
7326
7327#endif
7328#endif
0d96863f 7329#ifdef OBJ_ELF
8a104df9
KH		 7330void
7331m68k_elf_final_processing ()
0d96863f 7332{
36759679 7333 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9
KH		 7334 if (cpu_of_arch (current_architecture) & cpu32)
7335 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7336 else if ((cpu_of_arch (current_architecture) & m68000up)
7337 && !(cpu_of_arch (current_architecture) & m68020up))
7338 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7339}
7340#endif
c04898f8
AS		 7341
7342int
7343tc_m68k_regname_to_dw2regnum (const char *regname)
7344{
7345 unsigned int regnum;
7346 static const char *const regnames[] =
7347 {
7348 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7349 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7350 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7351 "pc"
7352 };
7353
7354 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7355 if (strcmp (regname, regnames[regnum]) == 0)
7356 return regnum;
7357
7358 return -1;
7359}
7360
7361void
7362tc_m68k_frame_initial_instructions (void)
7363{
7364 static int sp_regno = -1;
7365
7366 if (sp_regno < 0)
7367 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7368
7369 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7370 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7371}
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