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Fix normal operation for h8300-coff target
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c04898f8 3 2000, 2001, 2002, 2003
252b5132
RH		 4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
c04898f8 28#include "dw2gencfi.h"
252b5132
RH		 29
30#include "opcode/m68k.h"
31#include "m68k-parse.h"
32
0d96863f
CM		 33#if defined (OBJ_ELF)
34#include "elf/m68k.h"
35#endif
36
252b5132
RH		 37/* This string holds the chars that always start a comment. If the
38 pre-processor is disabled, these aren't very useful. The macro
39 tc_comment_chars points to this. We use this, rather than the
40 usual comment_chars, so that the --bitwise-or option will work. */
41#if defined (TE_SVR4) || defined (TE_DELTA)
42const char *m68k_comment_chars = "|#";
43#else
44const char *m68k_comment_chars = "|";
45#endif
46
47/* This array holds the chars that only start a comment at the beginning of
48 a line. If the line seems to have the form '# 123 filename'
49 .line and .file directives will appear in the pre-processed output */
50/* Note that input_file.c hand checks for '#' at the beginning of the
51 first line of the input file. This is because the compiler outputs
92774660
KH		 52 #NO_APP at the beginning of its output. */
53/* Also note that comments like this one will always work. */
252b5132
RH		 54const char line_comment_chars[] = "#*";
55
63a0b638 56const char line_separator_chars[] = ";";
252b5132
RH		 57
58/* Chars that can be used to separate mant from exp in floating point nums */
5a38dc70 59const char EXP_CHARS[] = "eE";
252b5132
RH		 60
61/* Chars that mean this number is a floating point constant, as
62 in "0f12.456" or "0d1.2345e12". */
63
5a38dc70 64const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 65
66/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here. */
69
70const int md_reloc_size = 8; /* Size of relocation record */
71
72/* Are we trying to generate PIC code? If so, absolute references
73 ought to be made into linkage table references or pc-relative
92774660 74 references. Not implemented. For ELF there are other means
252b5132
RH		 75 to denote pic relocations. */
76int flag_want_pic;
77
78static int flag_short_refs; /* -l option */
79static int flag_long_jumps; /* -S option */
28e7409f 80static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 81
82#ifdef REGISTER_PREFIX_OPTIONAL
83int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
84#else
85int flag_reg_prefix_optional;
86#endif
87
88/* Whether --register-prefix-optional was used on the command line. */
89static int reg_prefix_optional_seen;
90
91/* The floating point coprocessor to use by default. */
92static enum m68k_register m68k_float_copnum = COP1;
93
94/* If this is non-zero, then references to number(%pc) will be taken
95 to refer to number, rather than to %pc + number. */
96static int m68k_abspcadd;
97
98/* If this is non-zero, then the quick forms of the move, add, and sub
99 instructions are used when possible. */
100static int m68k_quick = 1;
101
102/* If this is non-zero, then if the size is not specified for a base
103 or outer displacement, the assembler assumes that the size should
104 be 32 bits. */
105static int m68k_rel32 = 1;
106
107/* This is non-zero if m68k_rel32 was set from the command line. */
108static int m68k_rel32_from_cmdline;
109
110/* The default width to use for an index register when using a base
111 displacement. */
112static enum m68k_size m68k_index_width_default = SIZE_LONG;
113
114/* We want to warn if any text labels are misaligned. In order to get
115 the right line number, we need to record the line number for each
116 label. */
117
118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
135/* Its an arbitrary name: This means I don't approve of it */
136/* See flames below */
137static struct obstack robyn;
138
252b5132
RH		 139struct m68k_incant
140 {
141 const char *m_operands;
142 unsigned long m_opcode;
143 short m_opnum;
144 short m_codenum;
145 int m_arch;
146 struct m68k_incant *m_next;
147 };
148
149#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
150#define gettwo(x) (((x)->m_opcode)&0xffff)
151
152static const enum m68k_register m68000_control_regs[] = { 0 };
153static const enum m68k_register m68010_control_regs[] = {
154 SFC, DFC, USP, VBR,
155 0
156};
157static const enum m68k_register m68020_control_regs[] = {
158 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
159 0
160};
161static const enum m68k_register m68040_control_regs[] = {
162 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
163 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
164 0
165};
166static const enum m68k_register m68060_control_regs[] = {
167 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
168 USP, VBR, URP, SRP, PCR,
169 0
170};
6da466c7 171static const enum m68k_register mcf_control_regs[] = {
92774660 172 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 173 RAMBAR0, RAMBAR1, MBAR,
174 0
175};
176#define cpu32_control_regs m68010_control_regs
177
178static const enum m68k_register *control_regs;
179
180/* internal form of a 68020 instruction */
181struct m68k_it
182{
183 const char *error;
184 const char *args; /* list of opcode info */
185 int numargs;
186
187 int numo; /* Number of shorts in opcode */
188 short opcode[11];
189
190 struct m68k_op operands[6];
191
192 int nexp; /* number of exprs in use */
193 struct m68k_exp exprs[4];
194
195 int nfrag; /* Number of frags we have to produce */
196 struct
197 {
198 int fragoff; /* Where in the current opcode the frag ends */
199 symbolS *fadd;
200 offsetT foff;
201 int fragty;
202 }
203 fragb[4];
204
205 int nrel; /* Num of reloc strucs in use */
206 struct
207 {
208 int n;
209 expressionS exp;
210 char wid;
211 char pcrel;
212 /* In a pc relative address the difference between the address
213 of the offset and the address that the offset is relative
214 to. This depends on the addressing mode. Basically this
215 is the value to put in the offset field to address the
216 first byte of the offset, without regarding the special
217 significance of some values (in the branch instruction, for
218 example). */
219 int pcrel_fix;
220#ifdef OBJ_ELF
221 /* Whether this expression needs special pic relocation, and if
222 so, which. */
223 enum pic_relocation pic_reloc;
224#endif
225 }
226 reloc[5]; /* Five is enough??? */
227};
228
6da466c7 229#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 230#define float_of_arch(x) ((x) & mfloat)
231#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 232#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 233
234/* Macros for determining if cpu supports a specific addressing mode */
dc84e067 235#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
252b5132
RH		 236
237static struct m68k_it the_ins; /* the instruction being assembled */
238
239#define op(ex) ((ex)->exp.X_op)
240#define adds(ex) ((ex)->exp.X_add_symbol)
241#define subs(ex) ((ex)->exp.X_op_symbol)
242#define offs(ex) ((ex)->exp.X_add_number)
243
244/* Macros for adding things to the m68k_it struct */
245
246#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
247
248/* Static functions. */
249
250static void insop PARAMS ((int, const struct m68k_incant *));
251static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
252static void add_frag PARAMS ((symbolS *, offsetT, int));
253
254/* Like addword, but goes BEFORE general operands */
255static void
256insop (w, opcode)
257 int w;
258 const struct m68k_incant *opcode;
259{
260 int z;
07726851 261 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 262 the_ins.opcode[z] = the_ins.opcode[z - 1];
263 for (z = 0; z < the_ins.nrel; z++)
264 the_ins.reloc[z].n += 2;
252b5132
RH		 265 for (z = 0; z < the_ins.nfrag; z++)
266 the_ins.fragb[z].fragoff++;
8a104df9 267 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 268 the_ins.numo++;
269}
270
271/* The numo+1 kludge is so we can hit the low order byte of the prev word.
272 Blecch. */
273static void
274add_fix (width, exp, pc_rel, pc_fix)
275 int width;
276 struct m68k_exp *exp;
277 int pc_rel;
278 int pc_fix;
279{
280 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
281 ? (the_ins.numo*2-1)
282 : (((width)=='b')
283 ? (the_ins.numo*2+1)
284 : (the_ins.numo*2)));
285 the_ins.reloc[the_ins.nrel].exp = exp->exp;
286 the_ins.reloc[the_ins.nrel].wid = width;
287 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
288#ifdef OBJ_ELF
289 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
290#endif
291 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
292}
293
294/* Cause an extra frag to be generated here, inserting up to 10 bytes
295 (that value is chosen in the frag_var call in md_assemble). TYPE
296 is the subtype of the frag to be generated; its primary type is
297 rs_machine_dependent.
298
299 The TYPE parameter is also used by md_convert_frag_1 and
300 md_estimate_size_before_relax. The appropriate type of fixup will
301 be emitted by md_convert_frag_1.
302
303 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
304static void
305add_frag (add, off, type)
306 symbolS *add;
307 offsetT off;
308 int type;
309{
8a104df9
KH		 310 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
311 the_ins.fragb[the_ins.nfrag].fadd = add;
312 the_ins.fragb[the_ins.nfrag].foff = off;
313 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 314}
315
316#define isvar(ex) \
317 (op (ex) != O_constant && op (ex) != O_big)
318
319static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
320static int get_num PARAMS ((struct m68k_exp *exp, int ok));
321static void m68k_ip PARAMS ((char *));
322static void insert_reg PARAMS ((const char *, int));
323static void select_control_regs PARAMS ((void));
324static void init_regtable PARAMS ((void));
325static int reverse_16_bits PARAMS ((int in));
326static int reverse_8_bits PARAMS ((int in));
327static void install_gen_operand PARAMS ((int mode, int val));
328static void install_operand PARAMS ((int mode, int val));
329static void s_bss PARAMS ((int));
330static void s_data1 PARAMS ((int));
331static void s_data2 PARAMS ((int));
332static void s_even PARAMS ((int));
333static void s_proc PARAMS ((int));
334static void mri_chip PARAMS ((void));
335static void s_chip PARAMS ((int));
336static void s_fopt PARAMS ((int));
337static void s_opt PARAMS ((int));
338static void s_reg PARAMS ((int));
339static void s_restore PARAMS ((int));
340static void s_save PARAMS ((int));
341static void s_mri_if PARAMS ((int));
342static void s_mri_else PARAMS ((int));
343static void s_mri_endi PARAMS ((int));
344static void s_mri_break PARAMS ((int));
345static void s_mri_next PARAMS ((int));
346static void s_mri_for PARAMS ((int));
347static void s_mri_endf PARAMS ((int));
348static void s_mri_repeat PARAMS ((int));
349static void s_mri_until PARAMS ((int));
350static void s_mri_while PARAMS ((int));
351static void s_mri_endw PARAMS ((int));
252b5132
RH		 352static void md_convert_frag_1 PARAMS ((fragS *));
353
354static int current_architecture;
355
dc84e067
NC		 356struct m68k_cpu
357 {
358 unsigned long arch;
359 const char *name;
360 int alias;
361 };
252b5132 362
dc84e067
NC		 363static const struct m68k_cpu archs[] =
364 {
365 { m68000, "68000", 0 },
366 { m68010, "68010", 0 },
367 { m68020, "68020", 0 },
368 { m68030, "68030", 0 },
369 { m68040, "68040", 0 },
370 { m68060, "68060", 0 },
371 { cpu32, "cpu32", 0 },
372 { m68881, "68881", 0 },
373 { m68851, "68851", 0 },
374 { mcf5200, "5200", 0 },
375 { mcf5206e, "5206e", 0 },
376 { mcf5307, "5307", 0},
377 { mcf5407, "5407", 0},
378 /* Aliases (effectively, so far as gas is concerned) for the above
379 cpus. */
380 { m68020, "68k", 1 },
381 { m68000, "68008", 1 },
382 { m68000, "68302", 1 },
383 { m68000, "68306", 1 },
384 { m68000, "68307", 1 },
385 { m68000, "68322", 1 },
386 { m68000, "68356", 1 },
387 { m68000, "68ec000", 1 },
388 { m68000, "68hc000", 1 },
389 { m68000, "68hc001", 1 },
390 { m68020, "68ec020", 1 },
391 { m68030, "68ec030", 1 },
392 { m68040, "68ec040", 1 },
393 { m68060, "68ec060", 1 },
394 { cpu32, "68330", 1 },
395 { cpu32, "68331", 1 },
396 { cpu32, "68332", 1 },
397 { cpu32, "68333", 1 },
398 { cpu32, "68334", 1 },
399 { cpu32, "68336", 1 },
400 { cpu32, "68340", 1 },
401 { cpu32, "68341", 1 },
402 { cpu32, "68349", 1 },
403 { cpu32, "68360", 1 },
404 { m68881, "68882", 1 },
405 { mcf5200, "5202", 1 },
406 { mcf5200, "5204", 1 },
407 { mcf5200, "5206", 1 },
408 };
252b5132
RH		 409
410static const int n_archs = sizeof (archs) / sizeof (archs[0]);
411
151337e8
NC		 412/* This is the assembler relaxation table for m68k. m68k is a rich CISC
413 architecture and we have a lot of relaxation modes. */
252b5132 414
151337e8
NC		 415/* Macros used in the relaxation code. */
416#define TAB(x,y) (((x) << 2) + (y))
417#define TABTYPE(x) ((x) >> 2)
418
419/* Relaxation states. */
420#define BYTE 0
421#define SHORT 1
422#define LONG 2
423#define SZ_UNDEF 3
424
425/* Here are all the relaxation modes we support. First we can relax ordinary
426 branches. On 68020 and higher and on CPU32 all branch instructions take
427 three forms, so on these CPUs all branches always remain as such. When we
428 have to expand to the LONG form on a 68000, though, we substitute an
429 absolute jump instead. This is a direct replacement for unconditional
430 branches and a branch over a jump for conditional branches. However, if the
431 user requires PIC and disables this with --pcrel, we can only relax between
432 BYTE and SHORT forms, punting if that isn't enough. This gives us four
433 different relaxation modes for branches: */
434
ac62c346
AM		 435#define BRANCHBWL 0 /* branch byte, word, or long */
436#define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
437#define BRABSJCOND 2 /* absolute jump for LONG, conditional */
438#define BRANCHBW 3 /* branch byte or word */
151337e8
NC		 439
440/* We also relax coprocessor branches and DBcc's. All CPUs that support
441 coprocessor branches support them in word and long forms, so we have only
442 one relaxation mode for them. DBcc's are word only on all CPUs. We can
443 relax them to the LONG form with a branch-around sequence. This sequence
444 can use a long branch (if available) or an absolute jump (if acceptable).
445 This gives us two relaxation modes. If long branches are not available and
446 absolute jumps are not acceptable, we don't relax DBcc's. */
447
ac62c346
AM		 448#define FBRANCH 4 /* coprocessor branch */
449#define DBCCLBR 5 /* DBcc relaxable with a long branch */
450#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
151337e8
NC		 451
452/* That's all for instruction relaxation. However, we also relax PC-relative
453 operands. Specifically, we have three operand relaxation modes. On the
454 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
455 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
456 two. Also PC+displacement+index operands in their simple form (with a non-
457 suppressed index without memory indirection) are supported on all CPUs, but
458 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
459 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
460 form of the PC+displacement+index operand. Finally, some absolute operands
461 can be relaxed down to 16-bit PC-relative. */
462
ac62c346
AM		 463#define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
464#define PCINDEX 8 /* PC+displacement+index */
465#define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 466
467/* Note that calls to frag_var need to specify the maximum expansion
468 needed; this is currently 10 bytes for DBCC. */
469
470/* The fields are:
471 How far Forward this mode will reach:
472 How far Backward this mode will reach:
473 How many bytes this mode will add to the size of the frag
474 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 475
476 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 477relax_typeS md_relax_table[] =
478{
ac62c346
AM		 479 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
480 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
481 { 0, 0, 4, 0 },
482 { 1, 1, 0, 0 },
483
484 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
485 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
486 { 0, 0, 4, 0 },
487 { 1, 1, 0, 0 },
488
489 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
490 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
491 { 0, 0, 6, 0 },
492 { 1, 1, 0, 0 },
493
494 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
495 { 0, 0, 2, 0 },
496 { 1, 1, 0, 0 },
497 { 1, 1, 0, 0 },
498
499 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
500 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
501 { 0, 0, 4, 0 },
502 { 1, 1, 0, 0 },
503
504 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
505 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
506 { 0, 0, 10, 0 },
507 { 1, 1, 0, 0 },
508
509 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
510 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
511 { 0, 0, 10, 0 },
512 { 1, 1, 0, 0 },
513
514 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
515 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
516 { 0, 0, 6, 0 },
517 { 1, 1, 0, 0 },
518
519 { 125, -130, 0, TAB (PCINDEX, SHORT) },
520 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
521 { 0, 0, 4, 0 },
522 { 1, 1, 0, 0 },
523
524 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
525 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
526 { 0, 0, 4, 0 },
527 { 1, 1, 0, 0 },
252b5132
RH		 528};
529
530/* These are the machine dependent pseudo-ops. These are included so
531 the assembler can work on the output from the SUN C compiler, which
532 generates these.
533 */
534
535/* This table describes all the machine specific pseudo-ops the assembler
536 has to support. The fields are:
537 pseudo-op name without dot
538 function to call to execute this pseudo-op
539 Integer arg to pass to the function
540 */
541const pseudo_typeS md_pseudo_table[] =
542{
543 {"data1", s_data1, 0},
544 {"data2", s_data2, 0},
545 {"bss", s_bss, 0},
546 {"even", s_even, 0},
547 {"skip", s_space, 0},
548 {"proc", s_proc, 0},
549#if defined (TE_SUN3) || defined (OBJ_ELF)
550 {"align", s_align_bytes, 0},
551#endif
552#ifdef OBJ_ELF
553 {"swbeg", s_ignore, 0},
554#endif
555 {"extend", float_cons, 'x'},
556 {"ldouble", float_cons, 'x'},
557
558 /* The following pseudo-ops are supported for MRI compatibility. */
559 {"chip", s_chip, 0},
560 {"comline", s_space, 1},
561 {"fopt", s_fopt, 0},
562 {"mask2", s_ignore, 0},
563 {"opt", s_opt, 0},
564 {"reg", s_reg, 0},
565 {"restore", s_restore, 0},
566 {"save", s_save, 0},
567
568 {"if", s_mri_if, 0},
569 {"if.b", s_mri_if, 'b'},
570 {"if.w", s_mri_if, 'w'},
571 {"if.l", s_mri_if, 'l'},
572 {"else", s_mri_else, 0},
573 {"else.s", s_mri_else, 's'},
574 {"else.l", s_mri_else, 'l'},
575 {"endi", s_mri_endi, 0},
576 {"break", s_mri_break, 0},
577 {"break.s", s_mri_break, 's'},
578 {"break.l", s_mri_break, 'l'},
579 {"next", s_mri_next, 0},
580 {"next.s", s_mri_next, 's'},
581 {"next.l", s_mri_next, 'l'},
582 {"for", s_mri_for, 0},
583 {"for.b", s_mri_for, 'b'},
584 {"for.w", s_mri_for, 'w'},
585 {"for.l", s_mri_for, 'l'},
586 {"endf", s_mri_endf, 0},
587 {"repeat", s_mri_repeat, 0},
588 {"until", s_mri_until, 0},
589 {"until.b", s_mri_until, 'b'},
590 {"until.w", s_mri_until, 'w'},
591 {"until.l", s_mri_until, 'l'},
592 {"while", s_mri_while, 0},
593 {"while.b", s_mri_while, 'b'},
594 {"while.w", s_mri_while, 'w'},
595 {"while.l", s_mri_while, 'l'},
596 {"endw", s_mri_endw, 0},
597
598 {0, 0, 0}
599};
600
252b5132
RH		 601/* The mote pseudo ops are put into the opcode table, since they
602 don't start with a . they look like opcodes to gas.
603 */
604
605#ifdef M68KCOFF
606extern void obj_coff_section PARAMS ((int));
607#endif
608
5a38dc70 609const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 610{
611
612 {"dcl", cons, 4},
613 {"dc", cons, 2},
614 {"dcw", cons, 2},
615 {"dcb", cons, 1},
616
617 {"dsl", s_space, 4},
618 {"ds", s_space, 2},
619 {"dsw", s_space, 2},
620 {"dsb", s_space, 1},
621
622 {"xdef", s_globl, 0},
623#ifdef OBJ_ELF
624 {"align", s_align_bytes, 0},
625#else
626 {"align", s_align_ptwo, 0},
627#endif
628#ifdef M68KCOFF
629 {"sect", obj_coff_section, 0},
630 {"section", obj_coff_section, 0},
631#endif
632 {0, 0, 0}
633};
634
635#define issbyte(x) ((x)>=-128 && (x)<=127)
636#define isubyte(x) ((x)>=0 && (x)<=255)
637#define issword(x) ((x)>=-32768 && (x)<=32767)
638#define isuword(x) ((x)>=0 && (x)<=65535)
639
640#define isbyte(x) ((x)>= -255 && (x)<=255)
641#define isword(x) ((x)>=-65536 && (x)<=65535)
642#define islong(x) (1)
643
644extern char *input_line_pointer;
645
252b5132
RH		 646static char notend_table[256];
647static char alt_notend_table[256];
648#define notend(s) \
649 (! (notend_table[(unsigned char) *s] \
650 || (*s == ':' \
651 && alt_notend_table[(unsigned char) s[1]])))
652
653#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
654
655#ifdef NO_PCREL_RELOCS
656
657int
658make_pcrel_absolute(fixP, add_number)
659 fixS *fixP;
660 long *add_number;
661{
662 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
663
664 /* rewrite the PC relative instructions to absolute address ones.
665 * these are rumoured to be faster, and the apollo linker refuses
666 * to deal with the PC relative relocations.
667 */
668 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
669 {
670 opcode[0] = 0x4e;
671 opcode[1] = 0xf9;
672 }
673 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
674 {
675 opcode[0] = 0x4e;
676 opcode[1] = 0xb9;
677 }
678 else
679 as_fatal (_("Unknown PC relative instruction"));
680 *add_number -= 4;
681 return 0;
682}
683
684#endif /* NO_PCREL_RELOCS */
685
686short
687tc_coff_fix2rtype (fixP)
688 fixS *fixP;
689{
690 if (fixP->fx_tcbit && fixP->fx_size == 4)
691 return R_RELLONG_NEG;
692#ifdef NO_PCREL_RELOCS
693 know (fixP->fx_pcrel == 0);
694 return (fixP->fx_size == 1 ? R_RELBYTE
695 : fixP->fx_size == 2 ? R_DIR16
696 : R_DIR32);
697#else
698 return (fixP->fx_pcrel ?
699 (fixP->fx_size == 1 ? R_PCRBYTE :
700 fixP->fx_size == 2 ? R_PCRWORD :
701 R_PCRLONG) :
702 (fixP->fx_size == 1 ? R_RELBYTE :
703 fixP->fx_size == 2 ? R_RELWORD :
704 R_RELLONG));
705#endif
706}
707
708#endif
709
710#ifdef OBJ_ELF
711
c801568a
AM		 712/* Return zero if the reference to SYMBOL from within the same segment may
713 be relaxed. */
714
715/* On an ELF system, we can't relax an externally visible symbol,
716 because it may be overridden by a shared library. However, if
717 TARGET_OS is "elf", then we presume that we are assembling for an
718 embedded system, in which case we don't have to worry about shared
719 libraries, and we can relax any external sym. */
720
721#define relaxable_symbol(symbol) \
722 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
723 || S_IS_WEAK (symbol)))
724
252b5132
RH		 725/* Compute the relocation code for a fixup of SIZE bytes, using pc
726 relative relocation if PCREL is non-zero. PIC says whether a special
727 pic relocation was requested. */
728
729static bfd_reloc_code_real_type get_reloc_code
730 PARAMS ((int, int, enum pic_relocation));
731
732static bfd_reloc_code_real_type
733get_reloc_code (size, pcrel, pic)
734 int size;
735 int pcrel;
736 enum pic_relocation pic;
737{
738 switch (pic)
739 {
740 case pic_got_pcrel:
741 switch (size)
742 {
743 case 1:
744 return BFD_RELOC_8_GOT_PCREL;
745 case 2:
746 return BFD_RELOC_16_GOT_PCREL;
747 case 4:
748 return BFD_RELOC_32_GOT_PCREL;
749 }
750 break;
751
752 case pic_got_off:
753 switch (size)
754 {
755 case 1:
756 return BFD_RELOC_8_GOTOFF;
757 case 2:
758 return BFD_RELOC_16_GOTOFF;
759 case 4:
760 return BFD_RELOC_32_GOTOFF;
761 }
762 break;
763
764 case pic_plt_pcrel:
765 switch (size)
766 {
767 case 1:
768 return BFD_RELOC_8_PLT_PCREL;
769 case 2:
770 return BFD_RELOC_16_PLT_PCREL;
771 case 4:
772 return BFD_RELOC_32_PLT_PCREL;
773 }
774 break;
775
776 case pic_plt_off:
777 switch (size)
778 {
779 case 1:
780 return BFD_RELOC_8_PLTOFF;
781 case 2:
782 return BFD_RELOC_16_PLTOFF;
783 case 4:
784 return BFD_RELOC_32_PLTOFF;
785 }
786 break;
787
788 case pic_none:
789 if (pcrel)
790 {
791 switch (size)
792 {
793 case 1:
794 return BFD_RELOC_8_PCREL;
795 case 2:
796 return BFD_RELOC_16_PCREL;
797 case 4:
798 return BFD_RELOC_32_PCREL;
799 }
800 }
801 else
802 {
803 switch (size)
804 {
805 case 1:
806 return BFD_RELOC_8;
807 case 2:
808 return BFD_RELOC_16;
809 case 4:
810 return BFD_RELOC_32;
811 }
812 }
813 }
814
815 if (pcrel)
816 {
817 if (pic == pic_none)
818 as_bad (_("Can not do %d byte pc-relative relocation"), size);
819 else
820 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
821 }
822 else
823 {
824 if (pic == pic_none)
825 as_bad (_("Can not do %d byte relocation"), size);
826 else
827 as_bad (_("Can not do %d byte pic relocation"), size);
828 }
829
830 return BFD_RELOC_NONE;
831}
832
833/* Here we decide which fixups can be adjusted to make them relative
834 to the beginning of the section instead of the symbol. Basically
835 we need to make sure that the dynamic relocations are done
836 correctly, so in some cases we force the original symbol to be
837 used. */
838int
839tc_m68k_fix_adjustable (fixP)
840 fixS *fixP;
841{
252b5132
RH		 842 /* adjust_reloc_syms doesn't know about the GOT */
843 switch (fixP->fx_r_type)
844 {
845 case BFD_RELOC_8_GOT_PCREL:
846 case BFD_RELOC_16_GOT_PCREL:
847 case BFD_RELOC_32_GOT_PCREL:
848 case BFD_RELOC_8_GOTOFF:
849 case BFD_RELOC_16_GOTOFF:
850 case BFD_RELOC_32_GOTOFF:
851 case BFD_RELOC_8_PLT_PCREL:
852 case BFD_RELOC_16_PLT_PCREL:
853 case BFD_RELOC_32_PLT_PCREL:
854 case BFD_RELOC_8_PLTOFF:
855 case BFD_RELOC_16_PLTOFF:
856 case BFD_RELOC_32_PLTOFF:
857 return 0;
858
859 case BFD_RELOC_VTABLE_INHERIT:
860 case BFD_RELOC_VTABLE_ENTRY:
861 return 0;
862
863 default:
864 return 1;
865 }
866}
867
868#else /* !OBJ_ELF */
869
870#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
871
c801568a
AM		 872#define relaxable_symbol(symbol) 1
873
252b5132
RH		 874#endif /* OBJ_ELF */
875
876#ifdef BFD_ASSEMBLER
877
878arelent *
879tc_gen_reloc (section, fixp)
f1f5ef86 880 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 881 fixS *fixp;
882{
883 arelent *reloc;
884 bfd_reloc_code_real_type code;
885
8ec6253e
NC		 886 /* If the tcbit is set, then this was a fixup of a negative value
887 that was never resolved. We do not have a reloc to handle this,
888 so just return. We assume that other code will have detected this
889 situation and produced a helpful error message, so we just tell the
890 user that the reloc cannot be produced. */
252b5132 891 if (fixp->fx_tcbit)
8ec6253e
NC		 892 {
893 if (fixp->fx_addsy)
b091f402
AM		 894 as_bad_where (fixp->fx_file, fixp->fx_line,
895 _("Unable to produce reloc against symbol '%s'"),
896 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 897 return NULL;
898 }
252b5132
RH		 899
900 if (fixp->fx_r_type != BFD_RELOC_NONE)
901 {
902 code = fixp->fx_r_type;
903
904 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
905 that fixup_segment converted a non-PC relative reloc into a
906 PC relative reloc. In such a case, we need to convert the
907 reloc code. */
908 if (fixp->fx_pcrel)
909 {
910 switch (code)
911 {
912 case BFD_RELOC_8:
913 code = BFD_RELOC_8_PCREL;
914 break;
915 case BFD_RELOC_16:
916 code = BFD_RELOC_16_PCREL;
917 break;
918 case BFD_RELOC_32:
919 code = BFD_RELOC_32_PCREL;
920 break;
921 case BFD_RELOC_8_PCREL:
922 case BFD_RELOC_16_PCREL:
923 case BFD_RELOC_32_PCREL:
924 case BFD_RELOC_8_GOT_PCREL:
925 case BFD_RELOC_16_GOT_PCREL:
926 case BFD_RELOC_32_GOT_PCREL:
927 case BFD_RELOC_8_GOTOFF:
928 case BFD_RELOC_16_GOTOFF:
929 case BFD_RELOC_32_GOTOFF:
930 case BFD_RELOC_8_PLT_PCREL:
931 case BFD_RELOC_16_PLT_PCREL:
932 case BFD_RELOC_32_PLT_PCREL:
933 case BFD_RELOC_8_PLTOFF:
934 case BFD_RELOC_16_PLTOFF:
935 case BFD_RELOC_32_PLTOFF:
936 break;
937 default:
938 as_bad_where (fixp->fx_file, fixp->fx_line,
939 _("Cannot make %s relocation PC relative"),
940 bfd_get_reloc_code_name (code));
941 }
942 }
943 }
944 else
945 {
946#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
947 switch (F (fixp->fx_size, fixp->fx_pcrel))
948 {
949#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
950 MAP (1, 0, BFD_RELOC_8);
951 MAP (2, 0, BFD_RELOC_16);
952 MAP (4, 0, BFD_RELOC_32);
953 MAP (1, 1, BFD_RELOC_8_PCREL);
954 MAP (2, 1, BFD_RELOC_16_PCREL);
955 MAP (4, 1, BFD_RELOC_32_PCREL);
956 default:
957 abort ();
958 }
959 }
960#undef F
961#undef MAP
962
963 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 964 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
965 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 966 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
967#ifndef OBJ_ELF
968 if (fixp->fx_pcrel)
969 reloc->addend = fixp->fx_addnumber;
970 else
971 reloc->addend = 0;
972#else
973 if (!fixp->fx_pcrel)
974 reloc->addend = fixp->fx_addnumber;
975 else
976 reloc->addend = (section->vma
8390138c
AS		 977 /* Explicit sign extension in case char is
978 unsigned. */
979 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 980 + fixp->fx_addnumber
981 + md_pcrel_from (fixp));
982#endif
983
984 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
985 assert (reloc->howto != 0);
986
987 return reloc;
988}
989
990#endif /* BFD_ASSEMBLER */
991
252b5132
RH		 992/* Handle of the OPCODE hash table. NULL means any use before
993 m68k_ip_begin() will crash. */
994static struct hash_control *op_hash;
995\f
996/* Assemble an m68k instruction. */
997
998static void
999m68k_ip (instring)
1000 char *instring;
1001{
1002 register char *p;
1003 register struct m68k_op *opP;
1004 register const struct m68k_incant *opcode;
1005 register const char *s;
1006 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1007 char *pdot, *pdotmove;
1008 enum m68k_size siz1, siz2;
1009 char c;
1010 int losing;
1011 int opsfound;
1012 LITTLENUM_TYPE words[6];
1013 LITTLENUM_TYPE *wordp;
1014 unsigned long ok_arch = 0;
1015
1016 if (*instring == ' ')
1017 instring++; /* skip leading whitespace */
1018
1019 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1020 or exactly 1 space. */
252b5132
RH		 1021 pdot = 0;
1022 for (p = instring; *p != '\0'; p++)
1023 {
1024 if (*p == ' ')
1025 break;
1026 if (*p == '.')
1027 pdot = p;
1028 }
1029
1030 if (p == instring)
1031 {
1032 the_ins.error = _("No operator");
1033 return;
1034 }
1035
1036 /* p now points to the end of the opcode name, probably whitespace.
1037 Make sure the name is null terminated by clobbering the
1038 whitespace, look it up in the hash table, then fix it back.
1039 Remove a dot, first, since the opcode tables have none. */
1040 if (pdot != NULL)
1041 {
1042 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1043 *pdotmove = pdotmove[1];
1044 p--;
1045 }
1046
1047 c = *p;
1048 *p = '\0';
1049 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1050 *p = c;
1051
1052 if (pdot != NULL)
1053 {
1054 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1055 *pdotmove = pdotmove[-1];
1056 *pdot = '.';
1057 ++p;
1058 }
1059
1060 if (opcode == NULL)
1061 {
1062 the_ins.error = _("Unknown operator");
1063 return;
1064 }
1065
1066 /* found a legitimate opcode, start matching operands */
1067 while (*p == ' ')
1068 ++p;
1069
1070 if (opcode->m_operands == 0)
1071 {
1072 char *old = input_line_pointer;
1073 *old = '\n';
1074 input_line_pointer = p;
1075 /* Ahh - it's a motorola style psuedo op */
1076 mote_pseudo_table[opcode->m_opnum].poc_handler
1077 (mote_pseudo_table[opcode->m_opnum].poc_val);
1078 input_line_pointer = old;
1079 *old = 0;
1080
1081 return;
1082 }
1083
1084 if (flag_mri && opcode->m_opnum == 0)
1085 {
1086 /* In MRI mode, random garbage is allowed after an instruction
1087 which accepts no operands. */
1088 the_ins.args = opcode->m_operands;
1089 the_ins.numargs = opcode->m_opnum;
1090 the_ins.numo = opcode->m_codenum;
1091 the_ins.opcode[0] = getone (opcode);
1092 the_ins.opcode[1] = gettwo (opcode);
1093 return;
1094 }
1095
1096 for (opP = &the_ins.operands[0]; *p; opP++)
1097 {
1098 p = crack_operand (p, opP);
1099
1100 if (opP->error)
1101 {
1102 the_ins.error = opP->error;
1103 return;
1104 }
1105 }
1106
1107 opsfound = opP - &the_ins.operands[0];
1108
1109 /* This ugly hack is to support the floating pt opcodes in their
1110 standard form. Essentially, we fake a first enty of type COP#1 */
1111 if (opcode->m_operands[0] == 'I')
1112 {
1113 int n;
1114
1115 for (n = opsfound; n > 0; --n)
1116 the_ins.operands[n] = the_ins.operands[n - 1];
1117
1118 memset ((char *) (&the_ins.operands[0]), '\0',
1119 sizeof (the_ins.operands[0]));
1120 the_ins.operands[0].mode = CONTROL;
1121 the_ins.operands[0].reg = m68k_float_copnum;
1122 opsfound++;
1123 }
1124
1125 /* We've got the operands. Find an opcode that'll accept them */
1126 for (losing = 0;;)
1127 {
1128 /* If we didn't get the right number of ops, or we have no
92774660 1129 common model with this pattern then reject this pattern. */
252b5132
RH		 1130
1131 ok_arch |= opcode->m_arch;
1132 if (opsfound != opcode->m_opnum
1133 || ((opcode->m_arch & current_architecture) == 0))
1134 ++losing;
1135 else
1136 {
1137 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1138 *s && !losing;
1139 s += 2, opP++)
1140 {
1141 /* Warning: this switch is huge! */
1142 /* I've tried to organize the cases into this order:
1143 non-alpha first, then alpha by letter. Lower-case
1144 goes directly before uppercase counterpart. */
1145 /* Code with multiple case ...: gets sorted by the lowest
1146 case ... it belongs to. I hope this makes sense. */
1147 switch (*s)
1148 {
1149 case '!':
1150 switch (opP->mode)
1151 {
1152 case IMMED:
1153 case DREG:
1154 case AREG:
1155 case FPREG:
1156 case CONTROL:
1157 case AINC:
1158 case ADEC:
1159 case REGLST:
1160 losing++;
1161 break;
1162 default:
1163 break;
1164 }
1165 break;
1166
1167 case '<':
1168 switch (opP->mode)
1169 {
1170 case DREG:
1171 case AREG:
1172 case FPREG:
1173 case CONTROL:
1174 case IMMED:
1175 case ADEC:
1176 case REGLST:
1177 losing++;
1178 break;
1179 default:
1180 break;
1181 }
1182 break;
1183
1184 case '>':
1185 switch (opP->mode)
1186 {
1187 case DREG:
1188 case AREG:
1189 case FPREG:
1190 case CONTROL:
1191 case IMMED:
1192 case AINC:
1193 case REGLST:
1194 losing++;
1195 break;
1196 case ABSL:
1197 break;
1198 default:
1199 if (opP->reg == PC
1200 || opP->reg == ZPC)
1201 losing++;
1202 break;
1203 }
1204 break;
1205
1206 case 'm':
1207 switch (opP->mode)
1208 {
1209 case DREG:
1210 case AREG:
1211 case AINDR:
1212 case AINC:
1213 case ADEC:
1214 break;
1215 default:
1216 losing++;
1217 }
8a104df9 1218 break;
252b5132
RH		 1219
1220 case 'n':
1221 switch (opP->mode)
1222 {
1223 case DISP:
1224 break;
1225 default:
1226 losing++;
1227 }
8a104df9 1228 break;
252b5132
RH		 1229
1230 case 'o':
1231 switch (opP->mode)
1232 {
1233 case BASE:
1234 case ABSL:
1235 case IMMED:
1236 break;
1237 default:
1238 losing++;
1239 }
8a104df9 1240 break;
252b5132
RH		 1241
1242 case 'p':
1243 switch (opP->mode)
1244 {
1245 case DREG:
1246 case AREG:
1247 case AINDR:
1248 case AINC:
1249 case ADEC:
1250 break;
1251 case DISP:
1252 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1253 losing++;
252b5132
RH		 1254 break;
1255 default:
1256 losing++;
1257 }
8a104df9 1258 break;
252b5132
RH		 1259
1260 case 'q':
1261 switch (opP->mode)
1262 {
1263 case DREG:
1264 case AINDR:
1265 case AINC:
1266 case ADEC:
1267 break;
1268 case DISP:
1269 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1270 losing++;
252b5132
RH		 1271 break;
1272 default:
1273 losing++;
1274 break;
1275 }
8a104df9 1276 break;
252b5132
RH		 1277
1278 case 'v':
1279 switch (opP->mode)
1280 {
1281 case DREG:
1282 case AINDR:
1283 case AINC:
1284 case ADEC:
1285 case ABSL:
1286 break;
1287 case DISP:
1288 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1289 losing++;
252b5132
RH		 1290 break;
1291 default:
1292 losing++;
1293 break;
1294 }
1295 break;
1296
1297 case '#':
1298 if (opP->mode != IMMED)
1299 losing++;
1300 else if (s[1] == 'b'
1301 && ! isvar (&opP->disp)
1302 && (opP->disp.exp.X_op != O_constant
1303 || ! isbyte (opP->disp.exp.X_add_number)))
1304 losing++;
1305 else if (s[1] == 'B'
1306 && ! isvar (&opP->disp)
1307 && (opP->disp.exp.X_op != O_constant
1308 || ! issbyte (opP->disp.exp.X_add_number)))
1309 losing++;
1310 else if (s[1] == 'w'
1311 && ! isvar (&opP->disp)
1312 && (opP->disp.exp.X_op != O_constant
1313 || ! isword (opP->disp.exp.X_add_number)))
1314 losing++;
1315 else if (s[1] == 'W'
1316 && ! isvar (&opP->disp)
1317 && (opP->disp.exp.X_op != O_constant
1318 || ! issword (opP->disp.exp.X_add_number)))
1319 losing++;
1320 break;
1321
1322 case '^':
1323 case 'T':
1324 if (opP->mode != IMMED)
1325 losing++;
1326 break;
1327
1328 case '$':
1329 if (opP->mode == AREG
1330 || opP->mode == CONTROL
1331 || opP->mode == FPREG
1332 || opP->mode == IMMED
1333 || opP->mode == REGLST
1334 || (opP->mode != ABSL
1335 && (opP->reg == PC
1336 || opP->reg == ZPC)))
1337 losing++;
1338 break;
1339
1340 case '%':
1341 if (opP->mode == CONTROL
1342 || opP->mode == FPREG
1343 || opP->mode == REGLST
1344 || opP->mode == IMMED
1345 || (opP->mode != ABSL
1346 && (opP->reg == PC
1347 || opP->reg == ZPC)))
1348 losing++;
1349 break;
1350
1351 case '&':
1352 switch (opP->mode)
1353 {
1354 case DREG:
1355 case AREG:
1356 case FPREG:
1357 case CONTROL:
1358 case IMMED:
1359 case AINC:
1360 case ADEC:
1361 case REGLST:
1362 losing++;
1363 break;
1364 case ABSL:
1365 break;
1366 default:
1367 if (opP->reg == PC
1368 || opP->reg == ZPC)
1369 losing++;
1370 break;
1371 }
1372 break;
1373
1374 case '*':
1375 if (opP->mode == CONTROL
1376 || opP->mode == FPREG
1377 || opP->mode == REGLST)
1378 losing++;
1379 break;
1380
1381 case '+':
1382 if (opP->mode != AINC)
1383 losing++;
1384 break;
1385
1386 case '-':
1387 if (opP->mode != ADEC)
1388 losing++;
1389 break;
1390
1391 case '/':
1392 switch (opP->mode)
1393 {
1394 case AREG:
1395 case CONTROL:
1396 case FPREG:
1397 case AINC:
1398 case ADEC:
1399 case IMMED:
1400 case REGLST:
1401 losing++;
1402 break;
1403 default:
1404 break;
1405 }
1406 break;
1407
1408 case ';':
1409 switch (opP->mode)
1410 {
1411 case AREG:
1412 case CONTROL:
1413 case FPREG:
1414 case REGLST:
1415 losing++;
1416 break;
1417 default:
1418 break;
1419 }
1420 break;
1421
1422 case '?':
1423 switch (opP->mode)
1424 {
1425 case AREG:
1426 case CONTROL:
1427 case FPREG:
1428 case AINC:
1429 case ADEC:
1430 case IMMED:
1431 case REGLST:
1432 losing++;
1433 break;
1434 case ABSL:
1435 break;
1436 default:
1437 if (opP->reg == PC || opP->reg == ZPC)
1438 losing++;
1439 break;
1440 }
1441 break;
1442
1443 case '@':
1444 switch (opP->mode)
1445 {
1446 case AREG:
1447 case CONTROL:
1448 case FPREG:
1449 case IMMED:
1450 case REGLST:
1451 losing++;
1452 break;
1453 default:
1454 break;
1455 }
1456 break;
1457
1458 case '~': /* For now! (JF FOO is this right?) */
1459 switch (opP->mode)
1460 {
1461 case DREG:
1462 case AREG:
1463 case CONTROL:
1464 case FPREG:
1465 case IMMED:
1466 case REGLST:
1467 losing++;
1468 break;
1469 case ABSL:
1470 break;
1471 default:
1472 if (opP->reg == PC
1473 || opP->reg == ZPC)
1474 losing++;
1475 break;
1476 }
1477 break;
1478
1479 case '3':
1480 if (opP->mode != CONTROL
1481 || (opP->reg != TT0 && opP->reg != TT1))
1482 losing++;
1483 break;
1484
1485 case 'A':
1486 if (opP->mode != AREG)
1487 losing++;
1488 break;
1489
1490 case 'a':
1491 if (opP->mode != AINDR)
1492 ++losing;
1493 break;
1494
1495 case 'B': /* FOO */
1496 if (opP->mode != ABSL
1497 || (flag_long_jumps
1498 && strncmp (instring, "jbsr", 4) == 0))
1499 losing++;
1500 break;
1501
1502 case 'C':
1503 if (opP->mode != CONTROL || opP->reg != CCR)
1504 losing++;
1505 break;
1506
1507 case 'd':
1508 if (opP->mode != DISP
1509 || opP->reg < ADDR0
1510 || opP->reg > ADDR7)
1511 losing++;
1512 break;
1513
1514 case 'D':
1515 if (opP->mode != DREG)
1516 losing++;
1517 break;
1518
6da466c7
ILT		 1519 case 'E':
1520 if (opP->reg != ACC)
1521 losing++;
1522 break;
1523
252b5132
RH		 1524 case 'F':
1525 if (opP->mode != FPREG)
1526 losing++;
1527 break;
1528
6da466c7
ILT		 1529 case 'G':
1530 if (opP->reg != MACSR)
1531 losing++;
1532 break;
1533
1534 case 'H':
1535 if (opP->reg != MASK)
1536 losing++;
1537 break;
1538
252b5132
RH		 1539 case 'I':
1540 if (opP->mode != CONTROL
1541 || opP->reg < COP0
1542 || opP->reg > COP7)
1543 losing++;
1544 break;
1545
1546 case 'J':
1547 if (opP->mode != CONTROL
1548 || opP->reg < USP
1549 || opP->reg > last_movec_reg)
1550 losing++;
1551 else
1552 {
1553 const enum m68k_register *rp;
1554 for (rp = control_regs; *rp; rp++)
1555 if (*rp == opP->reg)
1556 break;
1557 if (*rp == 0)
1558 losing++;
1559 }
1560 break;
1561
1562 case 'k':
1563 if (opP->mode != IMMED)
1564 losing++;
1565 break;
1566
1567 case 'l':
1568 case 'L':
1569 if (opP->mode == DREG
1570 || opP->mode == AREG
1571 || opP->mode == FPREG)
1572 {
1573 if (s[1] == '8')
1574 losing++;
1575 else
1576 {
1577 switch (opP->mode)
1578 {
1579 case DREG:
1580 opP->mask = 1 << (opP->reg - DATA0);
1581 break;
1582 case AREG:
1583 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1584 break;
1585 case FPREG:
1586 opP->mask = 1 << (opP->reg - FP0 + 16);
1587 break;
1588 default:
1589 abort ();
1590 }
1591 opP->mode = REGLST;
1592 }
1593 }
1594 else if (opP->mode == CONTROL)
1595 {
1596 if (s[1] != '8')
1597 losing++;
1598 else
1599 {
1600 switch (opP->reg)
1601 {
1602 case FPI:
1603 opP->mask = 1 << 24;
1604 break;
1605 case FPS:
1606 opP->mask = 1 << 25;
1607 break;
1608 case FPC:
1609 opP->mask = 1 << 26;
1610 break;
1611 default:
1612 losing++;
1613 break;
1614 }
1615 opP->mode = REGLST;
1616 }
1617 }
1618 else if (opP->mode != REGLST)
1619 losing++;
1620 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1621 losing++;
1622 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1623 losing++;
1624 break;
1625
1626 case 'M':
1627 if (opP->mode != IMMED)
1628 losing++;
1629 else if (opP->disp.exp.X_op != O_constant
1630 || ! issbyte (opP->disp.exp.X_add_number))
1631 losing++;
1632 else if (! m68k_quick
1633 && instring[3] != 'q'
1634 && instring[4] != 'q')
1635 losing++;
1636 break;
1637
1638 case 'O':
1639 if (opP->mode != DREG
1640 && opP->mode != IMMED
1641 && opP->mode != ABSL)
1642 losing++;
1643 break;
1644
1645 case 'Q':
1646 if (opP->mode != IMMED)
1647 losing++;
1648 else if (opP->disp.exp.X_op != O_constant
1649 || opP->disp.exp.X_add_number < 1
1650 || opP->disp.exp.X_add_number > 8)
1651 losing++;
1652 else if (! m68k_quick
1653 && (strncmp (instring, "add", 3) == 0
1654 || strncmp (instring, "sub", 3) == 0)
1655 && instring[3] != 'q')
1656 losing++;
1657 break;
1658
1659 case 'R':
1660 if (opP->mode != DREG && opP->mode != AREG)
1661 losing++;
1662 break;
1663
1664 case 'r':
1665 if (opP->mode != AINDR
1666 && (opP->mode != BASE
1667 || (opP->reg != 0
1668 && opP->reg != ZADDR0)
1669 || opP->disp.exp.X_op != O_absent
1670 || ((opP->index.reg < DATA0
1671 || opP->index.reg > DATA7)
1672 && (opP->index.reg < ADDR0
1673 || opP->index.reg > ADDR7))
1674 || opP->index.size != SIZE_UNSPEC
1675 || opP->index.scale != 1))
1676 losing++;
1677 break;
1678
1679 case 's':
1680 if (opP->mode != CONTROL
1681 || ! (opP->reg == FPI
1682 || opP->reg == FPS
1683 || opP->reg == FPC))
1684 losing++;
1685 break;
1686
1687 case 'S':
1688 if (opP->mode != CONTROL || opP->reg != SR)
1689 losing++;
1690 break;
1691
1692 case 't':
1693 if (opP->mode != IMMED)
1694 losing++;
1695 else if (opP->disp.exp.X_op != O_constant
1696 || opP->disp.exp.X_add_number < 0
1697 || opP->disp.exp.X_add_number > 7)
1698 losing++;
1699 break;
1700
1701 case 'U':
1702 if (opP->mode != CONTROL || opP->reg != USP)
1703 losing++;
1704 break;
1705
1706 /* JF these are out of order. We could put them
1707 in order if we were willing to put up with
1708 bunches of #ifdef m68851s in the code.
1709
1710 Don't forget that you need these operands
1711 to use 68030 MMU instructions. */
1712#ifndef NO_68851
1713 /* Memory addressing mode used by pflushr */
1714 case '|':
1715 if (opP->mode == CONTROL
1716 || opP->mode == FPREG
1717 || opP->mode == DREG
1718 || opP->mode == AREG
1719 || opP->mode == REGLST)
1720 losing++;
1721 /* We should accept immediate operands, but they
1722 supposedly have to be quad word, and we don't
1723 handle that. I would like to see what a Motorola
1724 assembler does before doing something here. */
1725 if (opP->mode == IMMED)
1726 losing++;
1727 break;
1728
1729 case 'f':
1730 if (opP->mode != CONTROL
1731 || (opP->reg != SFC && opP->reg != DFC))
1732 losing++;
1733 break;
1734
1735 case '0':
1736 if (opP->mode != CONTROL || opP->reg != TC)
1737 losing++;
1738 break;
1739
1740 case '1':
1741 if (opP->mode != CONTROL || opP->reg != AC)
1742 losing++;
1743 break;
1744
1745 case '2':
1746 if (opP->mode != CONTROL
1747 || (opP->reg != CAL
1748 && opP->reg != VAL
1749 && opP->reg != SCC))
1750 losing++;
1751 break;
1752
1753 case 'V':
1754 if (opP->mode != CONTROL
1755 || opP->reg != VAL)
1756 losing++;
1757 break;
1758
1759 case 'W':
1760 if (opP->mode != CONTROL
1761 || (opP->reg != DRP
1762 && opP->reg != SRP
1763 && opP->reg != CRP))
1764 losing++;
1765 break;
1766
1767 case 'X':
1768 if (opP->mode != CONTROL
1769 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1770 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1771 losing++;
1772 break;
1773
1774 case 'Y':
1775 if (opP->mode != CONTROL || opP->reg != PSR)
1776 losing++;
1777 break;
1778
1779 case 'Z':
1780 if (opP->mode != CONTROL || opP->reg != PCSR)
1781 losing++;
1782 break;
1783#endif
1784 case 'c':
1785 if (opP->mode != CONTROL
1786 || (opP->reg != NC
1787 && opP->reg != IC
1788 && opP->reg != DC
1789 && opP->reg != BC))
1790 {
1791 losing++;
92774660 1792 } /* not a cache specifier. */
252b5132
RH		 1793 break;
1794
1795 case '_':
1796 if (opP->mode != ABSL)
1797 ++losing;
1798 break;
1799
6da466c7
ILT		 1800 case 'u':
1801 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1802 losing++;
1803 /* FIXME: kludge instead of fixing parser:
1804 upper/lower registers are *not* CONTROL
92774660 1805 registers, but ordinary ones. */
6da466c7
ILT		 1806 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1807 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1808 opP->mode = DREG;
1809 else
1810 opP->mode = AREG;
1811 break;
1812
252b5132
RH		 1813 default:
1814 abort ();
1815 } /* switch on type of operand */
1816
1817 if (losing)
1818 break;
1819 } /* for each operand */
1820 } /* if immediately wrong */
1821
1822 if (!losing)
1823 {
1824 break;
92774660 1825 } /* got it. */
252b5132
RH		 1826
1827 opcode = opcode->m_next;
1828
1829 if (!opcode)
1830 {
1831 if (ok_arch
1832 && !(ok_arch & current_architecture))
1833 {
1834 char buf[200], *cp;
1835
1836 strcpy (buf,
1837 _("invalid instruction for this architecture; needs "));
1838 cp = buf + strlen (buf);
1839 switch (ok_arch)
1840 {
1841 case mfloat:
1842 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1843 break;
1844 case mmmu:
1845 strcpy (cp, _("mmu (68030 or 68851)"));
1846 break;
1847 case m68020up:
1848 strcpy (cp, _("68020 or higher"));
1849 break;
1850 case m68000up:
1851 strcpy (cp, _("68000 or higher"));
1852 break;
1853 case m68010up:
1854 strcpy (cp, _("68010 or higher"));
1855 break;
1856 default:
1857 {
1858 int got_one = 0, idx;
8fce3f5e
AM		 1859 for (idx = 0;
1860 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1861 idx++)
1862 {
1863 if ((archs[idx].arch & ok_arch)
1864 && ! archs[idx].alias)
1865 {
1866 if (got_one)
1867 {
1868 strcpy (cp, " or ");
1869 cp += strlen (cp);
1870 }
1871 got_one = 1;
1872 strcpy (cp, archs[idx].name);
1873 cp += strlen (cp);
1874 }
1875 }
1876 }
1877 }
1878 cp = xmalloc (strlen (buf) + 1);
1879 strcpy (cp, buf);
1880 the_ins.error = cp;
1881 }
1882 else
1883 the_ins.error = _("operands mismatch");
1884 return;
1885 } /* Fell off the end */
1886
1887 losing = 0;
1888 }
1889
1890 /* now assemble it */
1891
1892 the_ins.args = opcode->m_operands;
1893 the_ins.numargs = opcode->m_opnum;
1894 the_ins.numo = opcode->m_codenum;
1895 the_ins.opcode[0] = getone (opcode);
1896 the_ins.opcode[1] = gettwo (opcode);
1897
1898 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1899 {
1900 /* This switch is a doozy.
1901 Watch the first step; its a big one! */
1902 switch (s[0])
1903 {
1904
1905 case '*':
1906 case '~':
1907 case '%':
1908 case ';':
1909 case '@':
1910 case '!':
1911 case '&':
1912 case '$':
1913 case '?':
1914 case '/':
1915 case '<':
1916 case '>':
1917 case 'm':
1918 case 'n':
1919 case 'o':
1920 case 'p':
1921 case 'q':
1922 case 'v':
1923#ifndef NO_68851
1924 case '|':
1925#endif
1926 switch (opP->mode)
1927 {
1928 case IMMED:
1929 tmpreg = 0x3c; /* 7.4 */
1930 if (strchr ("bwl", s[1]))
1931 nextword = get_num (&opP->disp, 80);
1932 else
1933 nextword = get_num (&opP->disp, 0);
1934 if (isvar (&opP->disp))
1935 add_fix (s[1], &opP->disp, 0, 0);
1936 switch (s[1])
1937 {
1938 case 'b':
1939 if (!isbyte (nextword))
1940 opP->error = _("operand out of range");
1941 addword (nextword);
1942 baseo = 0;
1943 break;
1944 case 'w':
1945 if (!isword (nextword))
1946 opP->error = _("operand out of range");
1947 addword (nextword);
1948 baseo = 0;
1949 break;
1950 case 'W':
1951 if (!issword (nextword))
1952 opP->error = _("operand out of range");
1953 addword (nextword);
1954 baseo = 0;
1955 break;
1956 case 'l':
1957 addword (nextword >> 16);
1958 addword (nextword);
1959 baseo = 0;
1960 break;
1961
1962 case 'f':
1963 baseo = 2;
1964 outro = 8;
1965 break;
1966 case 'F':
1967 baseo = 4;
1968 outro = 11;
1969 break;
1970 case 'x':
1971 baseo = 6;
1972 outro = 15;
1973 break;
1974 case 'p':
1975 baseo = 6;
1976 outro = -1;
1977 break;
1978 default:
1979 abort ();
1980 }
1981 if (!baseo)
1982 break;
1983
1984 /* We gotta put out some float */
1985 if (op (&opP->disp) != O_big)
1986 {
1987 valueT val;
1988 int gencnt;
1989
1990 /* Can other cases happen here? */
1991 if (op (&opP->disp) != O_constant)
1992 abort ();
1993
1994 val = (valueT) offs (&opP->disp);
1995 gencnt = 0;
1996 do
1997 {
1998 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1999 val >>= LITTLENUM_NUMBER_OF_BITS;
2000 ++gencnt;
2001 }
2002 while (val != 0);
2003 offs (&opP->disp) = gencnt;
2004 }
2005 if (offs (&opP->disp) > 0)
2006 {
2007 if (offs (&opP->disp) > baseo)
2008 {
2009 as_warn (_("Bignum too big for %c format; truncated"),
2010 s[1]);
2011 offs (&opP->disp) = baseo;
2012 }
2013 baseo -= offs (&opP->disp);
2014 while (baseo--)
2015 addword (0);
2016 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2017 offs (&opP->disp)--;
2018 --wordp)
2019 addword (*wordp);
2020 break;
2021 }
2022 gen_to_words (words, baseo, (long) outro);
2023 for (wordp = words; baseo--; wordp++)
2024 addword (*wordp);
2025 break;
2026 case DREG:
2027 tmpreg = opP->reg - DATA; /* 0.dreg */
2028 break;
2029 case AREG:
2030 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2031 break;
2032 case AINDR:
2033 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2034 break;
2035 case ADEC:
2036 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2037 break;
2038 case AINC:
2039 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2040 break;
2041 case DISP:
2042
2043 nextword = get_num (&opP->disp, 80);
2044
2045 if (opP->reg == PC
2046 && ! isvar (&opP->disp)
2047 && m68k_abspcadd)
2048 {
2049 opP->disp.exp.X_op = O_symbol;
2050#ifndef BFD_ASSEMBLER
2051 opP->disp.exp.X_add_symbol = &abs_symbol;
2052#else
2053 opP->disp.exp.X_add_symbol =
2054 section_symbol (absolute_section);
2055#endif
2056 }
2057
2058 /* Force into index mode. Hope this works */
2059
2060 /* We do the first bit for 32-bit displacements, and the
2061 second bit for 16 bit ones. It is possible that we
2062 should make the default be WORD instead of LONG, but
2063 I think that'd break GCC, so we put up with a little
2064 inefficiency for the sake of working output. */
2065
2066 if (!issword (nextword)
2067 || (isvar (&opP->disp)
2068 && ((opP->disp.size == SIZE_UNSPEC
2069 && flag_short_refs == 0
2070 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2071 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2072 || opP->disp.size == SIZE_LONG)))
2073 {
2074 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2075 || arch_coldfire_p (current_architecture))
252b5132
RH		 2076 opP->error =
2077 _("displacement too large for this architecture; needs 68020 or higher");
2078 if (opP->reg == PC)
2079 tmpreg = 0x3B; /* 7.3 */
2080 else
2081 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2082 if (isvar (&opP->disp))
2083 {
2084 if (opP->reg == PC)
2085 {
2086 if (opP->disp.size == SIZE_LONG
2087#ifdef OBJ_ELF
2088 /* If the displacement needs pic
2089 relocation it cannot be relaxed. */
2090 || opP->disp.pic_reloc != pic_none
2091#endif
2092 )
2093 {
2094 addword (0x0170);
2095 add_fix ('l', &opP->disp, 1, 2);
2096 }
2097 else
2098 {
2099 add_frag (adds (&opP->disp),
2100 offs (&opP->disp),
151337e8 2101 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2102 break;
2103 }
2104 }
2105 else
2106 {
2107 addword (0x0170);
2108 add_fix ('l', &opP->disp, 0, 0);
2109 }
2110 }
2111 else
2112 addword (0x0170);
2113 addword (nextword >> 16);
2114 }
2115 else
2116 {
2117 if (opP->reg == PC)
2118 tmpreg = 0x3A; /* 7.2 */
2119 else
2120 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2121
2122 if (isvar (&opP->disp))
2123 {
2124 if (opP->reg == PC)
2125 {
2126 add_fix ('w', &opP->disp, 1, 0);
2127 }
2128 else
2129 add_fix ('w', &opP->disp, 0, 0);
2130 }
2131 }
2132 addword (nextword);
2133 break;
2134
2135 case POST:
2136 case PRE:
2137 case BASE:
2138 nextword = 0;
2139 baseo = get_num (&opP->disp, 80);
2140 if (opP->mode == POST || opP->mode == PRE)
2141 outro = get_num (&opP->odisp, 80);
2142 /* Figure out the `addressing mode'.
2143 Also turn on the BASE_DISABLE bit, if needed. */
2144 if (opP->reg == PC || opP->reg == ZPC)
2145 {
2146 tmpreg = 0x3b; /* 7.3 */
2147 if (opP->reg == ZPC)
2148 nextword |= 0x80;
2149 }
2150 else if (opP->reg == 0)
2151 {
2152 nextword |= 0x80;
2153 tmpreg = 0x30; /* 6.garbage */
2154 }
2155 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2156 {
2157 nextword |= 0x80;
2158 tmpreg = 0x30 + opP->reg - ZADDR0;
2159 }
2160 else
2161 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2162
2163 siz1 = opP->disp.size;
2164 if (opP->mode == POST || opP->mode == PRE)
2165 siz2 = opP->odisp.size;
2166 else
2167 siz2 = SIZE_UNSPEC;
2168
2169 /* Index register stuff */
2170 if (opP->index.reg != 0
2171 && opP->index.reg >= DATA
2172 && opP->index.reg <= ADDR7)
2173 {
2174 nextword |= (opP->index.reg - DATA) << 12;
2175
2176 if (opP->index.size == SIZE_LONG
2177 || (opP->index.size == SIZE_UNSPEC
2178 && m68k_index_width_default == SIZE_LONG))
2179 nextword |= 0x800;
2180
92774660 2181 if ((opP->index.scale != 1
252b5132 2182 && cpu_of_arch (current_architecture) < m68020)
92774660 2183 || (opP->index.scale == 8
6da466c7 2184 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2185 {
2186 opP->error =
2187 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2188 }
2189
6da466c7
ILT		 2190 if (arch_coldfire_p (current_architecture)
2191 && opP->index.size == SIZE_WORD)
2192 opP->error = _("invalid index size for coldfire");
2193
252b5132
RH		 2194 switch (opP->index.scale)
2195 {
2196 case 1:
2197 break;
2198 case 2:
2199 nextword |= 0x200;
2200 break;
2201 case 4:
2202 nextword |= 0x400;
2203 break;
2204 case 8:
2205 nextword |= 0x600;
2206 break;
2207 default:
2208 abort ();
2209 }
2210 /* IF its simple,
2211 GET US OUT OF HERE! */
2212
2213 /* Must be INDEX, with an index register. Address
2214 register cannot be ZERO-PC, and either :b was
2215 forced, or we know it will fit. For a 68000 or
2216 68010, force this mode anyways, because the
2217 larger modes aren't supported. */
2218 if (opP->mode == BASE
2219 && ((opP->reg >= ADDR0
2220 && opP->reg <= ADDR7)
2221 || opP->reg == PC))
2222 {
2223 if (siz1 == SIZE_BYTE
2224 || cpu_of_arch (current_architecture) < m68020
6da466c7 2225 || arch_coldfire_p (current_architecture)
252b5132
RH		 2226 || (siz1 == SIZE_UNSPEC
2227 && ! isvar (&opP->disp)
2228 && issbyte (baseo)))
2229 {
2230 nextword += baseo & 0xff;
2231 addword (nextword);
2232 if (isvar (&opP->disp))
2233 {
2234 /* Do a byte relocation. If it doesn't
2235 fit (possible on m68000) let the
2236 fixup processing complain later. */
2237 if (opP->reg == PC)
2238 add_fix ('B', &opP->disp, 1, 1);
2239 else
2240 add_fix ('B', &opP->disp, 0, 0);
2241 }
2242 else if (siz1 != SIZE_BYTE)
2243 {
2244 if (siz1 != SIZE_UNSPEC)
2245 as_warn (_("Forcing byte displacement"));
2246 if (! issbyte (baseo))
2247 opP->error = _("byte displacement out of range");
2248 }
2249
2250 break;
2251 }
2252 else if (siz1 == SIZE_UNSPEC
2253 && opP->reg == PC
2254 && isvar (&opP->disp)
2255 && subs (&opP->disp) == NULL
2256#ifdef OBJ_ELF
2257 /* If the displacement needs pic
2258 relocation it cannot be relaxed. */
2259 && opP->disp.pic_reloc == pic_none
2260#endif
2261 )
2262 {
2263 /* The code in md_convert_frag_1 needs to be
2264 able to adjust nextword. Call frag_grow
2265 to ensure that we have enough space in
2266 the frag obstack to make all the bytes
2267 contiguous. */
2268 frag_grow (14);
8a104df9
KH		 2269 nextword += baseo & 0xff;
2270 addword (nextword);
2271 add_frag (adds (&opP->disp), offs (&opP->disp),
2272 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2273
2274 break;
8a104df9 2275 }
252b5132
RH		 2276 }
2277 }
2278 else
2279 {
2280 nextword |= 0x40; /* No index reg */
2281 if (opP->index.reg >= ZDATA0
2282 && opP->index.reg <= ZDATA7)
2283 nextword |= (opP->index.reg - ZDATA0) << 12;
2284 else if (opP->index.reg >= ZADDR0
2285 || opP->index.reg <= ZADDR7)
2286 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2287 }
2288
2289 /* It isn't simple. */
2290
2291 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2292 || arch_coldfire_p (current_architecture))
252b5132
RH		 2293 opP->error =
2294 _("invalid operand mode for this architecture; needs 68020 or higher");
2295
2296 nextword |= 0x100;
2297 /* If the guy specified a width, we assume that it is
2298 wide enough. Maybe it isn't. If so, we lose. */
2299 switch (siz1)
2300 {
2301 case SIZE_UNSPEC:
2302 if (isvar (&opP->disp)
2303 ? m68k_rel32
2304 : ! issword (baseo))
2305 {
2306 siz1 = SIZE_LONG;
2307 nextword |= 0x30;
2308 }
2309 else if (! isvar (&opP->disp) && baseo == 0)
2310 nextword |= 0x10;
2311 else
2312 {
2313 nextword |= 0x20;
2314 siz1 = SIZE_WORD;
2315 }
2316 break;
2317 case SIZE_BYTE:
2318 as_warn (_(":b not permitted; defaulting to :w"));
2319 /* Fall through. */
2320 case SIZE_WORD:
2321 nextword |= 0x20;
2322 break;
2323 case SIZE_LONG:
2324 nextword |= 0x30;
2325 break;
2326 }
2327
2328 /* Figure out innner displacement stuff */
2329 if (opP->mode == POST || opP->mode == PRE)
2330 {
2331 if (cpu_of_arch (current_architecture) & cpu32)
2332 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2333 switch (siz2)
2334 {
2335 case SIZE_UNSPEC:
2336 if (isvar (&opP->odisp)
2337 ? m68k_rel32
2338 : ! issword (outro))
2339 {
2340 siz2 = SIZE_LONG;
2341 nextword |= 0x3;
2342 }
2343 else if (! isvar (&opP->odisp) && outro == 0)
2344 nextword |= 0x1;
2345 else
2346 {
2347 nextword |= 0x2;
2348 siz2 = SIZE_WORD;
2349 }
2350 break;
2351 case 1:
2352 as_warn (_(":b not permitted; defaulting to :w"));
2353 /* Fall through. */
2354 case 2:
2355 nextword |= 0x2;
2356 break;
2357 case 3:
2358 nextword |= 0x3;
2359 break;
2360 }
2361 if (opP->mode == POST
2362 && (nextword & 0x40) == 0)
2363 nextword |= 0x04;
2364 }
2365 addword (nextword);
2366
2367 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2368 {
2369 if (opP->reg == PC || opP->reg == ZPC)
2370 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2371 else
2372 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2373 }
2374 if (siz1 == SIZE_LONG)
2375 addword (baseo >> 16);
2376 if (siz1 != SIZE_UNSPEC)
2377 addword (baseo);
2378
2379 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2380 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2381 if (siz2 == SIZE_LONG)
2382 addword (outro >> 16);
2383 if (siz2 != SIZE_UNSPEC)
2384 addword (outro);
2385
2386 break;
2387
2388 case ABSL:
2389 nextword = get_num (&opP->disp, 80);
2390 switch (opP->disp.size)
2391 {
2392 default:
2393 abort ();
2394 case SIZE_UNSPEC:
2395 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2396 {
2397 tmpreg = 0x38; /* 7.0 */
2398 addword (nextword);
2399 break;
2400 }
252b5132
RH		 2401 if (isvar (&opP->disp)
2402 && !subs (&opP->disp)
2403 && adds (&opP->disp)
2404#ifdef OBJ_ELF
2405 /* If the displacement needs pic relocation it
2406 cannot be relaxed. */
2407 && opP->disp.pic_reloc == pic_none
2408#endif
252b5132
RH		 2409 && !flag_long_jumps
2410 && !strchr ("~%&$?", s[0]))
2411 {
2412 tmpreg = 0x3A; /* 7.2 */
2413 add_frag (adds (&opP->disp),
2414 offs (&opP->disp),
151337e8 2415 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2416 break;
2417 }
2418 /* Fall through into long */
2419 case SIZE_LONG:
2420 if (isvar (&opP->disp))
2421 add_fix ('l', &opP->disp, 0, 0);
2422
2423 tmpreg = 0x39;/* 7.1 mode */
2424 addword (nextword >> 16);
2425 addword (nextword);
2426 break;
2427
2428 case SIZE_BYTE:
2429 as_bad (_("unsupported byte value; use a different suffix"));
2430 /* Fall through. */
2431 case SIZE_WORD: /* Word */
2432 if (isvar (&opP->disp))
2433 add_fix ('w', &opP->disp, 0, 0);
2434
2435 tmpreg = 0x38;/* 7.0 mode */
2436 addword (nextword);
2437 break;
2438 }
2439 break;
2440 case CONTROL:
2441 case FPREG:
2442 default:
2443 as_bad (_("unknown/incorrect operand"));
bc805888 2444 /* abort (); */
252b5132
RH		 2445 }
2446 install_gen_operand (s[1], tmpreg);
2447 break;
2448
2449 case '#':
2450 case '^':
2451 switch (s[1])
2452 { /* JF: I hate floating point! */
2453 case 'j':
2454 tmpreg = 70;
2455 break;
2456 case '8':
2457 tmpreg = 20;
2458 break;
2459 case 'C':
2460 tmpreg = 50;
2461 break;
2462 case '3':
2463 default:
2464 tmpreg = 80;
2465 break;
2466 }
2467 tmpreg = get_num (&opP->disp, tmpreg);
2468 if (isvar (&opP->disp))
2469 add_fix (s[1], &opP->disp, 0, 0);
2470 switch (s[1])
2471 {
2472 case 'b': /* Danger: These do no check for
2473 certain types of overflow.
2474 user beware! */
2475 if (!isbyte (tmpreg))
2476 opP->error = _("out of range");
2477 insop (tmpreg, opcode);
2478 if (isvar (&opP->disp))
2479 the_ins.reloc[the_ins.nrel - 1].n =
2480 (opcode->m_codenum) * 2 + 1;
2481 break;
2482 case 'B':
2483 if (!issbyte (tmpreg))
2484 opP->error = _("out of range");
2485 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2486 if (isvar (&opP->disp))
2487 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2488 break;
2489 case 'w':
2490 if (!isword (tmpreg))
2491 opP->error = _("out of range");
2492 insop (tmpreg, opcode);
2493 if (isvar (&opP->disp))
2494 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2495 break;
2496 case 'W':
2497 if (!issword (tmpreg))
2498 opP->error = _("out of range");
2499 insop (tmpreg, opcode);
2500 if (isvar (&opP->disp))
2501 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2502 break;
2503 case 'l':
2504 /* Because of the way insop works, we put these two out
2505 backwards. */
2506 insop (tmpreg, opcode);
2507 insop (tmpreg >> 16, opcode);
2508 if (isvar (&opP->disp))
2509 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2510 break;
2511 case '3':
2512 tmpreg &= 0xFF;
2513 case '8':
2514 case 'C':
2515 case 'j':
2516 install_operand (s[1], tmpreg);
2517 break;
2518 default:
2519 abort ();
2520 }
2521 break;
2522
2523 case '+':
2524 case '-':
2525 case 'A':
2526 case 'a':
2527 install_operand (s[1], opP->reg - ADDR);
2528 break;
2529
2530 case 'B':
2531 tmpreg = get_num (&opP->disp, 80);
2532 switch (s[1])
2533 {
2534 case 'B':
8390138c 2535 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2536 break;
2537 case 'W':
2538 add_fix ('w', &opP->disp, 1, 0);
2539 addword (0);
2540 break;
2541 case 'L':
2542 long_branch:
151337e8 2543 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2544 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2545 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2546 add_fix ('l', &opP->disp, 1, 0);
2547 addword (0);
2548 addword (0);
2549 break;
2550 case 'g':
2551 if (subs (&opP->disp)) /* We can't relax it */
2552 goto long_branch;
2553
2554#ifdef OBJ_ELF
2555 /* If the displacement needs pic relocation it cannot be
2556 relaxed. */
2557 if (opP->disp.pic_reloc != pic_none)
2558 goto long_branch;
2559#endif
252b5132 2560 /* This could either be a symbol, or an absolute
151337e8
NC		 2561 address. If it's an absolute address, turn it into
2562 an absolute jump right here and keep it out of the
2563 relaxer. */
2564 if (adds (&opP->disp) == 0)
2565 {
2566 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2567 the_ins.opcode[0] = 0x4EF9;
151337e8 2568 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2569 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2570 else /* jCC */
2571 {
2572 the_ins.opcode[0] ^= 0x0100;
2573 the_ins.opcode[0] |= 0x0006;
18566f55 2574 addword (0x4EF9);
151337e8
NC		 2575 }
2576 add_fix ('l', &opP->disp, 0, 0);
2577 addword (0);
2578 addword (0);
2579 break;
2580 }
2581
2582 /* Now we know it's going into the relaxer. Now figure
2583 out which mode. We try in this order of preference:
2584 long branch, absolute jump, byte/word branches only. */
2585 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2586 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2587 TAB (BRANCHBWL, SZ_UNDEF));
2588 else if (! flag_keep_pcrel)
2589 {
2590 if ((the_ins.opcode[0] == 0x6000)
2591 || (the_ins.opcode[0] == 0x6100))
2592 add_frag (adds (&opP->disp), offs (&opP->disp),
2593 TAB (BRABSJUNC, SZ_UNDEF));
2594 else
2595 add_frag (adds (&opP->disp), offs (&opP->disp),
2596 TAB (BRABSJCOND, SZ_UNDEF));
2597 }
252b5132
RH		 2598 else
2599 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2600 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2601 break;
2602 case 'w':
2603 if (isvar (&opP->disp))
2604 {
151337e8
NC		 2605 /* Check for DBcc instructions. We can relax them,
2606 but only if we have long branches and/or absolute
2607 jumps. */
2608 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2609 && (HAVE_LONG_BRANCH (current_architecture)
2610 || (! flag_keep_pcrel)))
252b5132 2611 {
151337e8
NC		 2612 if (HAVE_LONG_BRANCH (current_architecture))
2613 add_frag (adds (&opP->disp), offs (&opP->disp),
2614 TAB (DBCCLBR, SZ_UNDEF));
2615 else
2616 add_frag (adds (&opP->disp), offs (&opP->disp),
2617 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2618 break;
2619 }
252b5132
RH		 2620 add_fix ('w', &opP->disp, 1, 0);
2621 }
2622 addword (0);
2623 break;
2624 case 'C': /* Fixed size LONG coproc branches */
2625 add_fix ('l', &opP->disp, 1, 0);
2626 addword (0);
2627 addword (0);
2628 break;
2629 case 'c': /* Var size Coprocesssor branches */
151337e8 2630 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2631 {
252b5132
RH		 2632 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2633 add_fix ('l', &opP->disp, 1, 0);
2634 addword (0);
2635 addword (0);
2636 }
151337e8
NC		 2637 else
2638 add_frag (adds (&opP->disp), offs (&opP->disp),
2639 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2640 break;
2641 default:
2642 abort ();
2643 }
2644 break;
2645
2646 case 'C': /* Ignore it */
2647 break;
2648
2649 case 'd': /* JF this is a kludge */
2650 install_operand ('s', opP->reg - ADDR);
2651 tmpreg = get_num (&opP->disp, 80);
2652 if (!issword (tmpreg))
2653 {
2654 as_warn (_("Expression out of range, using 0"));
2655 tmpreg = 0;
2656 }
2657 addword (tmpreg);
2658 break;
2659
2660 case 'D':
2661 install_operand (s[1], opP->reg - DATA);
2662 break;
2663
6da466c7
ILT		 2664 case 'E': /* Ignore it */
2665 break;
2666
252b5132
RH		 2667 case 'F':
2668 install_operand (s[1], opP->reg - FP0);
2669 break;
2670
6da466c7
ILT		 2671 case 'G': /* Ignore it */
2672 case 'H':
2673 break;
2674
252b5132
RH		 2675 case 'I':
2676 tmpreg = opP->reg - COP0;
2677 install_operand (s[1], tmpreg);
2678 break;
2679
2680 case 'J': /* JF foo */
2681 switch (opP->reg)
2682 {
2683 case SFC:
2684 tmpreg = 0x000;
2685 break;
2686 case DFC:
2687 tmpreg = 0x001;
2688 break;
2689 case CACR:
2690 tmpreg = 0x002;
2691 break;
2692 case TC:
2693 tmpreg = 0x003;
2694 break;
2695 case ITT0:
2696 tmpreg = 0x004;
2697 break;
2698 case ITT1:
2699 tmpreg = 0x005;
2700 break;
2701 case DTT0:
2702 tmpreg = 0x006;
2703 break;
2704 case DTT1:
2705 tmpreg = 0x007;
2706 break;
2707 case BUSCR:
2708 tmpreg = 0x008;
2709 break;
2710
2711 case USP:
2712 tmpreg = 0x800;
2713 break;
2714 case VBR:
2715 tmpreg = 0x801;
2716 break;
2717 case CAAR:
2718 tmpreg = 0x802;
2719 break;
2720 case MSP:
2721 tmpreg = 0x803;
2722 break;
2723 case ISP:
2724 tmpreg = 0x804;
2725 break;
2726 case MMUSR:
2727 tmpreg = 0x805;
2728 break;
2729 case URP:
2730 tmpreg = 0x806;
2731 break;
2732 case SRP:
2733 tmpreg = 0x807;
2734 break;
2735 case PCR:
2736 tmpreg = 0x808;
2737 break;
2738 case ROMBAR:
2739 tmpreg = 0xC00;
2740 break;
2741 case RAMBAR0:
2742 tmpreg = 0xC04;
2743 break;
2744 case RAMBAR1:
2745 tmpreg = 0xC05;
2746 break;
2747 case MBAR:
2748 tmpreg = 0xC0F;
2749 break;
2750 default:
2751 abort ();
2752 }
2753 install_operand (s[1], tmpreg);
2754 break;
2755
2756 case 'k':
2757 tmpreg = get_num (&opP->disp, 55);
2758 install_operand (s[1], tmpreg & 0x7f);
2759 break;
2760
2761 case 'l':
2762 tmpreg = opP->mask;
2763 if (s[1] == 'w')
2764 {
2765 if (tmpreg & 0x7FF0000)
2766 as_bad (_("Floating point register in register list"));
2767 insop (reverse_16_bits (tmpreg), opcode);
2768 }
2769 else
2770 {
2771 if (tmpreg & 0x700FFFF)
2772 as_bad (_("Wrong register in floating-point reglist"));
2773 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2774 }
2775 break;
2776
2777 case 'L':
2778 tmpreg = opP->mask;
2779 if (s[1] == 'w')
2780 {
2781 if (tmpreg & 0x7FF0000)
2782 as_bad (_("Floating point register in register list"));
2783 insop (tmpreg, opcode);
2784 }
2785 else if (s[1] == '8')
2786 {
2787 if (tmpreg & 0x0FFFFFF)
2788 as_bad (_("incorrect register in reglist"));
2789 install_operand (s[1], tmpreg >> 24);
2790 }
2791 else
2792 {
2793 if (tmpreg & 0x700FFFF)
2794 as_bad (_("wrong register in floating-point reglist"));
2795 else
2796 install_operand (s[1], tmpreg >> 16);
2797 }
2798 break;
2799
2800 case 'M':
2801 install_operand (s[1], get_num (&opP->disp, 60));
2802 break;
2803
2804 case 'O':
2805 tmpreg = ((opP->mode == DREG)
8fce3f5e 2806 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2807 : (get_num (&opP->disp, 40) & 0x1F));
2808 install_operand (s[1], tmpreg);
2809 break;
2810
2811 case 'Q':
2812 tmpreg = get_num (&opP->disp, 10);
2813 if (tmpreg == 8)
2814 tmpreg = 0;
2815 install_operand (s[1], tmpreg);
2816 break;
2817
2818 case 'R':
2819 /* This depends on the fact that ADDR registers are eight
2820 more than their corresponding DATA regs, so the result
2821 will have the ADDR_REG bit set */
2822 install_operand (s[1], opP->reg - DATA);
2823 break;
2824
2825 case 'r':
2826 if (opP->mode == AINDR)
2827 install_operand (s[1], opP->reg - DATA);
2828 else
2829 install_operand (s[1], opP->index.reg - DATA);
2830 break;
2831
2832 case 's':
2833 if (opP->reg == FPI)
2834 tmpreg = 0x1;
2835 else if (opP->reg == FPS)
2836 tmpreg = 0x2;
2837 else if (opP->reg == FPC)
2838 tmpreg = 0x4;
2839 else
2840 abort ();
2841 install_operand (s[1], tmpreg);
2842 break;
2843
2844 case 'S': /* Ignore it */
2845 break;
2846
2847 case 'T':
2848 install_operand (s[1], get_num (&opP->disp, 30));
2849 break;
2850
2851 case 'U': /* Ignore it */
2852 break;
2853
2854 case 'c':
2855 switch (opP->reg)
2856 {
2857 case NC:
2858 tmpreg = 0;
2859 break;
2860 case DC:
2861 tmpreg = 1;
2862 break;
2863 case IC:
2864 tmpreg = 2;
2865 break;
2866 case BC:
2867 tmpreg = 3;
2868 break;
2869 default:
2870 as_fatal (_("failed sanity check"));
2871 } /* switch on cache token */
2872 install_operand (s[1], tmpreg);
2873 break;
2874#ifndef NO_68851
92774660 2875 /* JF: These are out of order, I fear. */
252b5132
RH		 2876 case 'f':
2877 switch (opP->reg)
2878 {
2879 case SFC:
2880 tmpreg = 0;
2881 break;
2882 case DFC:
2883 tmpreg = 1;
2884 break;
2885 default:
2886 abort ();
2887 }
2888 install_operand (s[1], tmpreg);
2889 break;
2890
2891 case '0':
2892 case '1':
2893 case '2':
2894 switch (opP->reg)
2895 {
2896 case TC:
2897 tmpreg = 0;
2898 break;
2899 case CAL:
2900 tmpreg = 4;
2901 break;
2902 case VAL:
2903 tmpreg = 5;
2904 break;
2905 case SCC:
2906 tmpreg = 6;
2907 break;
2908 case AC:
2909 tmpreg = 7;
2910 break;
2911 default:
2912 abort ();
2913 }
2914 install_operand (s[1], tmpreg);
2915 break;
2916
2917 case 'V':
2918 if (opP->reg == VAL)
2919 break;
2920 abort ();
2921
2922 case 'W':
2923 switch (opP->reg)
2924 {
2925 case DRP:
2926 tmpreg = 1;
2927 break;
2928 case SRP:
2929 tmpreg = 2;
2930 break;
2931 case CRP:
2932 tmpreg = 3;
2933 break;
2934 default:
2935 abort ();
2936 }
2937 install_operand (s[1], tmpreg);
2938 break;
2939
2940 case 'X':
2941 switch (opP->reg)
2942 {
2943 case BAD:
2944 case BAD + 1:
2945 case BAD + 2:
2946 case BAD + 3:
2947 case BAD + 4:
2948 case BAD + 5:
2949 case BAD + 6:
2950 case BAD + 7:
2951 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2952 break;
2953
2954 case BAC:
2955 case BAC + 1:
2956 case BAC + 2:
2957 case BAC + 3:
2958 case BAC + 4:
2959 case BAC + 5:
2960 case BAC + 6:
2961 case BAC + 7:
2962 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2963 break;
2964
2965 default:
2966 abort ();
2967 }
2968 install_operand (s[1], tmpreg);
2969 break;
2970 case 'Y':
2971 know (opP->reg == PSR);
2972 break;
2973 case 'Z':
2974 know (opP->reg == PCSR);
2975 break;
2976#endif /* m68851 */
2977 case '3':
2978 switch (opP->reg)
2979 {
2980 case TT0:
2981 tmpreg = 2;
2982 break;
2983 case TT1:
2984 tmpreg = 3;
2985 break;
2986 default:
2987 abort ();
2988 }
2989 install_operand (s[1], tmpreg);
2990 break;
2991 case 't':
2992 tmpreg = get_num (&opP->disp, 20);
2993 install_operand (s[1], tmpreg);
2994 break;
2995 case '_': /* used only for move16 absolute 32-bit address */
2996 if (isvar (&opP->disp))
2997 add_fix ('l', &opP->disp, 0, 0);
2998 tmpreg = get_num (&opP->disp, 80);
2999 addword (tmpreg >> 16);
3000 addword (tmpreg & 0xFFFF);
3001 break;
6da466c7
ILT		 3002 case 'u':
3003 install_operand (s[1], opP->reg - DATA0L);
3004 opP->reg -= (DATA0L);
3005 opP->reg &= 0x0F; /* remove upper/lower bit */
3006 break;
252b5132
RH		 3007 default:
3008 abort ();
3009 }
3010 }
3011
3012 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3013 instruction, ready to be emitted. . . */
252b5132
RH		 3014}
3015
3016static int
3017reverse_16_bits (in)
3018 int in;
3019{
3020 int out = 0;
3021 int n;
3022
3023 static int mask[16] =
3024 {
3025 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3026 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3027 };
3028 for (n = 0; n < 16; n++)
3029 {
3030 if (in & mask[n])
3031 out |= mask[15 - n];
3032 }
3033 return out;
3034} /* reverse_16_bits() */
3035
3036static int
3037reverse_8_bits (in)
3038 int in;
3039{
3040 int out = 0;
3041 int n;
3042
3043 static int mask[8] =
3044 {
3045 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3046 };
3047
3048 for (n = 0; n < 8; n++)
3049 {
3050 if (in & mask[n])
3051 out |= mask[7 - n];
3052 }
3053 return out;
3054} /* reverse_8_bits() */
3055
3056/* Cause an extra frag to be generated here, inserting up to 10 bytes
3057 (that value is chosen in the frag_var call in md_assemble). TYPE
3058 is the subtype of the frag to be generated; its primary type is
3059 rs_machine_dependent.
3060
3061 The TYPE parameter is also used by md_convert_frag_1 and
3062 md_estimate_size_before_relax. The appropriate type of fixup will
3063 be emitted by md_convert_frag_1.
3064
3065 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3066static void
3067install_operand (mode, val)
3068 int mode;
3069 int val;
3070{
3071 switch (mode)
3072 {
3073 case 's':
3074 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3075 break;
3076 case 'd':
3077 the_ins.opcode[0] |= val << 9;
3078 break;
3079 case '1':
3080 the_ins.opcode[1] |= val << 12;
3081 break;
3082 case '2':
3083 the_ins.opcode[1] |= val << 6;
3084 break;
3085 case '3':
3086 the_ins.opcode[1] |= val;
3087 break;
3088 case '4':
3089 the_ins.opcode[2] |= val << 12;
3090 break;
3091 case '5':
3092 the_ins.opcode[2] |= val << 6;
3093 break;
3094 case '6':
3095 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3096 three words long! */
3097 the_ins.numo++;
3098 the_ins.opcode[2] |= val;
3099 break;
3100 case '7':
3101 the_ins.opcode[1] |= val << 7;
3102 break;
3103 case '8':
3104 the_ins.opcode[1] |= val << 10;
3105 break;
3106#ifndef NO_68851
3107 case '9':
3108 the_ins.opcode[1] |= val << 5;
3109 break;
3110#endif
3111
3112 case 't':
3113 the_ins.opcode[1] |= (val << 10) | (val << 7);
3114 break;
3115 case 'D':
3116 the_ins.opcode[1] |= (val << 12) | val;
3117 break;
3118 case 'g':
3119 the_ins.opcode[0] |= val = 0xff;
3120 break;
3121 case 'i':
3122 the_ins.opcode[0] |= val << 9;
3123 break;
3124 case 'C':
3125 the_ins.opcode[1] |= val;
3126 break;
3127 case 'j':
3128 the_ins.opcode[1] |= val;
3129 the_ins.numo++; /* What a hack */
3130 break;
3131 case 'k':
3132 the_ins.opcode[1] |= val << 4;
3133 break;
3134 case 'b':
3135 case 'w':
3136 case 'W':
3137 case 'l':
3138 break;
3139 case 'e':
3140 the_ins.opcode[0] |= (val << 6);
3141 break;
3142 case 'L':
3143 the_ins.opcode[1] = (val >> 16);
3144 the_ins.opcode[2] = val & 0xffff;
3145 break;
6da466c7
ILT		 3146 case 'm':
3147 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3148 the_ins.opcode[0] |= ((val & 0x7) << 9);
3149 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3150 break;
3151 case 'n':
3152 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3153 the_ins.opcode[0] |= ((val & 0x7) << 9);
3154 break;
3155 case 'o':
3156 the_ins.opcode[1] |= val << 12;
3157 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3158 break;
3159 case 'M':
3160 the_ins.opcode[0] |= (val & 0xF);
3161 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3162 break;
3163 case 'N':
3164 the_ins.opcode[1] |= (val & 0xF);
3165 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3166 break;
3167 case 'h':
3168 the_ins.opcode[1] |= ((val != 1) << 10);
3169 break;
252b5132
RH		 3170 case 'c':
3171 default:
3172 as_fatal (_("failed sanity check."));
3173 }
3174} /* install_operand() */
3175
3176static void
3177install_gen_operand (mode, val)
3178 int mode;
3179 int val;
3180{
3181 switch (mode)
3182 {
3183 case 's':
3184 the_ins.opcode[0] |= val;
3185 break;
3186 case 'd':
3187 /* This is a kludge!!! */
3188 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3189 break;
3190 case 'b':
3191 case 'w':
3192 case 'l':
3193 case 'f':
3194 case 'F':
3195 case 'x':
3196 case 'p':
3197 the_ins.opcode[0] |= val;
3198 break;
3199 /* more stuff goes here */
3200 default:
3201 as_fatal (_("failed sanity check."));
3202 }
3203} /* install_gen_operand() */
3204
3205/*
3206 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3207 * then deal with the bitfield hack.
3208 */
3209
3210static char *
3211crack_operand (str, opP)
3212 register char *str;
3213 register struct m68k_op *opP;
3214{
3215 register int parens;
3216 register int c;
3217 register char *beg_str;
3218 int inquote = 0;
3219
3220 if (!str)
3221 {
3222 return str;
3223 }
3224 beg_str = str;
3225 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3226 {
3227 if (! inquote)
3228 {
3229 if (*str == '(')
3230 parens++;
3231 else if (*str == ')')
3232 {
3233 if (!parens)
3234 { /* ERROR */
3235 opP->error = _("Extra )");
3236 return str;
3237 }
3238 --parens;
3239 }
3240 }
3241 if (flag_mri && *str == '\'')
3242 inquote = ! inquote;
3243 }
3244 if (!*str && parens)
3245 { /* ERROR */
3246 opP->error = _("Missing )");
3247 return str;
3248 }
3249 c = *str;
3250 *str = '\0';
3251 if (m68k_ip_op (beg_str, opP) != 0)
3252 {
3253 *str = c;
3254 return str;
3255 }
3256 *str = c;
3257 if (c == '}')
3258 c = *++str; /* JF bitfield hack */
3259 if (c)
3260 {
3261 c = *++str;
3262 if (!c)
3263 as_bad (_("Missing operand"));
3264 }
3265
3266 /* Detect MRI REG symbols and convert them to REGLSTs. */
3267 if (opP->mode == CONTROL && (int)opP->reg < 0)
3268 {
3269 opP->mode = REGLST;
3270 opP->mask = ~(int)opP->reg;
3271 opP->reg = 0;
3272 }
3273
3274 return str;
3275}
3276
3277/* This is the guts of the machine-dependent assembler. STR points to a
3278 machine dependent instruction. This function is supposed to emit
3279 the frags/bytes it assembles to.
3280 */
3281
3282static void
3283insert_reg (regname, regnum)
3284 const char *regname;
3285 int regnum;
3286{
3287 char buf[100];
3288 int i;
3289
3290#ifdef REGISTER_PREFIX
3291 if (!flag_reg_prefix_optional)
3292 {
3293 buf[0] = REGISTER_PREFIX;
3294 strcpy (buf + 1, regname);
3295 regname = buf;
3296 }
3297#endif
3298
3299 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3300 &zero_address_frag));
3301
3302 for (i = 0; regname[i]; i++)
3882b010 3303 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3304 buf[i] = '\0';
3305
3306 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3307 &zero_address_frag));
3308}
3309
3310struct init_entry
3311 {
3312 const char *name;
3313 int number;
3314 };
3315
3316static const struct init_entry init_table[] =
3317{
3318 { "d0", DATA0 },
3319 { "d1", DATA1 },
3320 { "d2", DATA2 },
3321 { "d3", DATA3 },
3322 { "d4", DATA4 },
3323 { "d5", DATA5 },
3324 { "d6", DATA6 },
3325 { "d7", DATA7 },
3326 { "a0", ADDR0 },
3327 { "a1", ADDR1 },
3328 { "a2", ADDR2 },
3329 { "a3", ADDR3 },
3330 { "a4", ADDR4 },
3331 { "a5", ADDR5 },
3332 { "a6", ADDR6 },
3333 { "fp", ADDR6 },
3334 { "a7", ADDR7 },
3335 { "sp", ADDR7 },
3336 { "ssp", ADDR7 },
3337 { "fp0", FP0 },
3338 { "fp1", FP1 },
3339 { "fp2", FP2 },
3340 { "fp3", FP3 },
3341 { "fp4", FP4 },
3342 { "fp5", FP5 },
3343 { "fp6", FP6 },
3344 { "fp7", FP7 },
3345 { "fpi", FPI },
3346 { "fpiar", FPI },
3347 { "fpc", FPI },
3348 { "fps", FPS },
3349 { "fpsr", FPS },
3350 { "fpc", FPC },
3351 { "fpcr", FPC },
3352 { "control", FPC },
3353 { "status", FPS },
3354 { "iaddr", FPI },
3355
3356 { "cop0", COP0 },
3357 { "cop1", COP1 },
3358 { "cop2", COP2 },
3359 { "cop3", COP3 },
3360 { "cop4", COP4 },
3361 { "cop5", COP5 },
3362 { "cop6", COP6 },
3363 { "cop7", COP7 },
3364 { "pc", PC },
3365 { "zpc", ZPC },
3366 { "sr", SR },
3367
3368 { "ccr", CCR },
3369 { "cc", CCR },
3370
6da466c7
ILT		 3371 { "acc", ACC },
3372 { "macsr", MACSR },
3373 { "mask", MASK },
3374
252b5132
RH		 3375 /* control registers */
3376 { "sfc", SFC }, /* Source Function Code */
3377 { "sfcr", SFC },
3378 { "dfc", DFC }, /* Destination Function Code */
3379 { "dfcr", DFC },
3380 { "cacr", CACR }, /* Cache Control Register */
3381 { "caar", CAAR }, /* Cache Address Register */
3382
3383 { "usp", USP }, /* User Stack Pointer */
3384 { "vbr", VBR }, /* Vector Base Register */
3385 { "msp", MSP }, /* Master Stack Pointer */
3386 { "isp", ISP }, /* Interrupt Stack Pointer */
3387
3388 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3389 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3390 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3391 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3392
3393 /* 68ec040 versions of same */
3394 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3395 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3396 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3397 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3398
3399 /* mcf5200 versions of same. The ColdFire programmer's reference
3400 manual indicated that the order is 2,3,0,1, but Ken Rose
3401 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3402 { "acr0", ITT0 }, /* Access Control Unit 0 */
3403 { "acr1", ITT1 }, /* Access Control Unit 1 */
3404 { "acr2", DTT0 }, /* Access Control Unit 2 */
3405 { "acr3", DTT1 }, /* Access Control Unit 3 */
3406
3407 { "tc", TC }, /* MMU Translation Control Register */
3408 { "tcr", TC },
3409
3410 { "mmusr", MMUSR }, /* MMU Status Register */
3411 { "srp", SRP }, /* User Root Pointer */
3412 { "urp", URP }, /* Supervisor Root Pointer */
3413
3414 { "buscr", BUSCR },
3415 { "pcr", PCR },
3416
3417 { "rombar", ROMBAR }, /* ROM Base Address Register */
3418 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3419 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3420 { "mbar", MBAR }, /* Module Base Address Register */
3421 /* end of control registers */
3422
3423 { "ac", AC },
3424 { "bc", BC },
3425 { "cal", CAL },
3426 { "crp", CRP },
3427 { "drp", DRP },
3428 { "pcsr", PCSR },
3429 { "psr", PSR },
3430 { "scc", SCC },
3431 { "val", VAL },
3432 { "bad0", BAD0 },
3433 { "bad1", BAD1 },
3434 { "bad2", BAD2 },
3435 { "bad3", BAD3 },
3436 { "bad4", BAD4 },
3437 { "bad5", BAD5 },
3438 { "bad6", BAD6 },
3439 { "bad7", BAD7 },
3440 { "bac0", BAC0 },
3441 { "bac1", BAC1 },
3442 { "bac2", BAC2 },
3443 { "bac3", BAC3 },
3444 { "bac4", BAC4 },
3445 { "bac5", BAC5 },
3446 { "bac6", BAC6 },
3447 { "bac7", BAC7 },
3448
3449 { "ic", IC },
3450 { "dc", DC },
3451 { "nc", NC },
3452
3453 { "tt0", TT0 },
3454 { "tt1", TT1 },
3455 /* 68ec030 versions of same */
3456 { "ac0", TT0 },
3457 { "ac1", TT1 },
3458 /* 68ec030 access control unit, identical to 030 MMU status reg */
3459 { "acusr", PSR },
3460
3461 /* Suppressed data and address registers. */
3462 { "zd0", ZDATA0 },
3463 { "zd1", ZDATA1 },
3464 { "zd2", ZDATA2 },
3465 { "zd3", ZDATA3 },
3466 { "zd4", ZDATA4 },
3467 { "zd5", ZDATA5 },
3468 { "zd6", ZDATA6 },
3469 { "zd7", ZDATA7 },
3470 { "za0", ZADDR0 },
3471 { "za1", ZADDR1 },
3472 { "za2", ZADDR2 },
3473 { "za3", ZADDR3 },
3474 { "za4", ZADDR4 },
3475 { "za5", ZADDR5 },
3476 { "za6", ZADDR6 },
3477 { "za7", ZADDR7 },
3478
92774660 3479 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3480 { "d0l", DATA0L },
3481 { "d1l", DATA1L },
3482 { "d2l", DATA2L },
3483 { "d3l", DATA3L },
3484 { "d4l", DATA4L },
3485 { "d5l", DATA5L },
3486 { "d6l", DATA6L },
3487 { "d7l", DATA7L },
3488
3489 { "a0l", ADDR0L },
3490 { "a1l", ADDR1L },
3491 { "a2l", ADDR2L },
3492 { "a3l", ADDR3L },
3493 { "a4l", ADDR4L },
3494 { "a5l", ADDR5L },
3495 { "a6l", ADDR6L },
3496 { "a7l", ADDR7L },
3497
3498 { "d0u", DATA0U },
3499 { "d1u", DATA1U },
3500 { "d2u", DATA2U },
3501 { "d3u", DATA3U },
3502 { "d4u", DATA4U },
3503 { "d5u", DATA5U },
3504 { "d6u", DATA6U },
3505 { "d7u", DATA7U },
3506
3507 { "a0u", ADDR0U },
3508 { "a1u", ADDR1U },
3509 { "a2u", ADDR2U },
3510 { "a3u", ADDR3U },
3511 { "a4u", ADDR4U },
3512 { "a5u", ADDR5U },
3513 { "a6u", ADDR6U },
3514 { "a7u", ADDR7U },
3515
252b5132
RH		 3516 { 0, 0 }
3517};
3518
3519static void
3520init_regtable ()
3521{
3522 int i;
3523 for (i = 0; init_table[i].name; i++)
3524 insert_reg (init_table[i].name, init_table[i].number);
3525}
3526
3527static int no_68851, no_68881;
3528
3529#ifdef OBJ_AOUT
3530/* a.out machine type. Default to 68020. */
3531int m68k_aout_machtype = 2;
3532#endif
3533
3534void
3535md_assemble (str)
3536 char *str;
3537{
3538 const char *er;
3539 short *fromP;
3540 char *toP = NULL;
3541 int m, n = 0;
3542 char *to_beg_P;
3543 int shorts_this_frag;
3544 fixS *fixP;
3545
3546 /* In MRI mode, the instruction and operands are separated by a
3547 space. Anything following the operands is a comment. The label
3548 has already been removed. */
3549 if (flag_mri)
3550 {
3551 char *s;
3552 int fields = 0;
3553 int infield = 0;
3554 int inquote = 0;
3555
3556 for (s = str; *s != '\0'; s++)
3557 {
3558 if ((*s == ' ' || *s == '\t') && ! inquote)
3559 {
3560 if (infield)
3561 {
3562 ++fields;
3563 if (fields >= 2)
3564 {
3565 *s = '\0';
3566 break;
3567 }
3568 infield = 0;
3569 }
3570 }
3571 else
3572 {
3573 if (! infield)
3574 infield = 1;
3575 if (*s == '\'')
3576 inquote = ! inquote;
3577 }
3578 }
3579 }
3580
3581 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3582 m68k_ip (str);
3583 er = the_ins.error;
3584 if (!er)
3585 {
3586 for (n = 0; n < the_ins.numargs; n++)
3587 if (the_ins.operands[n].error)
3588 {
3589 er = the_ins.operands[n].error;
3590 break;
3591 }
3592 }
3593 if (er)
3594 {
3595 as_bad (_("%s -- statement `%s' ignored"), er, str);
3596 return;
3597 }
3598
3599 /* If there is a current label, record that it marks an instruction. */
3600 if (current_label != NULL)
3601 {
3602 current_label->text = 1;
3603 current_label = NULL;
3604 }
3605
f27a3839
AS		 3606#ifdef OBJ_ELF
3607 /* Tie dwarf2 debug info to the address at the start of the insn. */
3608 dwarf2_emit_insn (0);
3609#endif
3610
252b5132
RH		 3611 if (the_ins.nfrag == 0)
3612 {
3613 /* No frag hacking involved; just put it out */
3614 toP = frag_more (2 * the_ins.numo);
3615 fromP = &the_ins.opcode[0];
3616 for (m = the_ins.numo; m; --m)
3617 {
3618 md_number_to_chars (toP, (long) (*fromP), 2);
3619 toP += 2;
3620 fromP++;
3621 }
3622 /* put out symbol-dependent info */
3623 for (m = 0; m < the_ins.nrel; m++)
3624 {
3625 switch (the_ins.reloc[m].wid)
3626 {
3627 case 'B':
3628 n = 1;
3629 break;
3630 case 'b':
3631 n = 1;
3632 break;
3633 case '3':
3634 n = 1;
3635 break;
3636 case 'w':
3637 case 'W':
3638 n = 2;
3639 break;
3640 case 'l':
3641 n = 4;
3642 break;
3643 default:
3644 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3645 the_ins.reloc[m].wid);
3646 }
3647
3648 fixP = fix_new_exp (frag_now,
3649 ((toP - frag_now->fr_literal)
3650 - the_ins.numo * 2 + the_ins.reloc[m].n),
3651 n,
3652 &the_ins.reloc[m].exp,
3653 the_ins.reloc[m].pcrel,
3654 get_reloc_code (n, the_ins.reloc[m].pcrel,
3655 the_ins.reloc[m].pic_reloc));
3656 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3657 if (the_ins.reloc[m].wid == 'B')
3658 fixP->fx_signed = 1;
3659 }
3660 return;
3661 }
3662
3663 /* There's some frag hacking */
fbe572f9
AM		 3664 {
3665 /* Calculate the max frag size. */
3666 int wid;
3667
3668 wid = 2 * the_ins.fragb[0].fragoff;
3669 for (n = 1; n < the_ins.nfrag; n++)
3670 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3671 /* frag_var part. */
3672 wid += 10;
3673 /* Make sure the whole insn fits in one chunk, in particular that
3674 the var part is attached, as we access one byte before the
3675 variable frag for byte branches. */
3676 frag_grow (wid);
3677 }
3678
252b5132
RH		 3679 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3680 {
3681 int wid;
3682
3683 if (n == 0)
3684 wid = 2 * the_ins.fragb[n].fragoff;
3685 else
3686 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3687 toP = frag_more (wid);
3688 to_beg_P = toP;
3689 shorts_this_frag = 0;
3690 for (m = wid / 2; m; --m)
3691 {
3692 md_number_to_chars (toP, (long) (*fromP), 2);
3693 toP += 2;
3694 fromP++;
3695 shorts_this_frag++;
3696 }
3697 for (m = 0; m < the_ins.nrel; m++)
3698 {
3699 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3700 {
3701 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3702 break;
3703 }
3704 wid = the_ins.reloc[m].wid;
3705 if (wid == 0)
3706 continue;
3707 the_ins.reloc[m].wid = 0;
3708 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3709
3710 fixP = fix_new_exp (frag_now,
3711 ((toP - frag_now->fr_literal)
3712 - the_ins.numo * 2 + the_ins.reloc[m].n),
3713 wid,
3714 &the_ins.reloc[m].exp,
3715 the_ins.reloc[m].pcrel,
3716 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3717 the_ins.reloc[m].pic_reloc));
3718 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3719 }
3720 (void) frag_var (rs_machine_dependent, 10, 0,
3721 (relax_substateT) (the_ins.fragb[n].fragty),
3722 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3723 }
3724 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3725 shorts_this_frag = 0;
3726 if (n)
3727 {
3728 toP = frag_more (n * sizeof (short));
3729 while (n--)
3730 {
3731 md_number_to_chars (toP, (long) (*fromP), 2);
3732 toP += 2;
3733 fromP++;
3734 shorts_this_frag++;
3735 }
3736 }
3737 for (m = 0; m < the_ins.nrel; m++)
3738 {
3739 int wid;
3740
3741 wid = the_ins.reloc[m].wid;
3742 if (wid == 0)
3743 continue;
3744 the_ins.reloc[m].wid = 0;
3745 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3746
3747 fixP = fix_new_exp (frag_now,
3748 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3749 - shorts_this_frag * 2),
3750 wid,
3751 &the_ins.reloc[m].exp,
3752 the_ins.reloc[m].pcrel,
3753 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3754 the_ins.reloc[m].pic_reloc));
3755 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3756 }
3757}
3758
3759void
3760md_begin ()
3761{
3762 /*
3763 * md_begin -- set up hash tables with 68000 instructions.
3764 * similar to what the vax assembler does. ---phr
3765 */
3766 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3767 a copy of it at runtime, adding in the information we want but isn't
3768 there. I think it'd be better to have an awk script hack the table
3769 at compile time. Or even just xstr the table and use it as-is. But
3770 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3771 names. */
3772
94f592af
NC		 3773 const struct m68k_opcode *ins;
3774 struct m68k_incant *hack, *slak;
3775 const char *retval = 0; /* empty string, or error msg text */
3776 int i;
252b5132
RH		 3777
3778 if (flag_mri)
3779 {
3780 flag_reg_prefix_optional = 1;
3781 m68k_abspcadd = 1;
3782 if (! m68k_rel32_from_cmdline)
3783 m68k_rel32 = 0;
3784 }
3785
3786 op_hash = hash_new ();
3787
3788 obstack_begin (&robyn, 4000);
3789 for (i = 0; i < m68k_numopcodes; i++)
3790 {
3791 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3792 do
3793 {
3794 ins = &m68k_opcodes[i];
3795 /* We *could* ignore insns that don't match our arch here
92774660 3796 but just leaving them out of the hash. */
252b5132
RH		 3797 slak->m_operands = ins->args;
3798 slak->m_opnum = strlen (slak->m_operands) / 2;
3799 slak->m_arch = ins->arch;
3800 slak->m_opcode = ins->opcode;
3801 /* This is kludgey */
3802 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3803 if (i + 1 != m68k_numopcodes
3804 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3805 {
3806 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3807 i++;
3808 }
3809 else
3810 slak->m_next = 0;
3811 slak = slak->m_next;
3812 }
3813 while (slak);
3814
3815 retval = hash_insert (op_hash, ins->name, (char *) hack);
3816 if (retval)
3817 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3818 }
3819
3820 for (i = 0; i < m68k_numaliases; i++)
3821 {
3822 const char *name = m68k_opcode_aliases[i].primary;
3823 const char *alias = m68k_opcode_aliases[i].alias;
3824 PTR val = hash_find (op_hash, name);
3825 if (!val)
3826 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3827 retval = hash_insert (op_hash, alias, val);
3828 if (retval)
3829 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3830 }
3831
3832 /* In MRI mode, all unsized branches are variable sized. Normally,
3833 they are word sized. */
3834 if (flag_mri)
3835 {
3836 static struct m68k_opcode_alias mri_aliases[] =
3837 {
3838 { "bhi", "jhi", },
3839 { "bls", "jls", },
3840 { "bcc", "jcc", },
3841 { "bcs", "jcs", },
3842 { "bne", "jne", },
3843 { "beq", "jeq", },
3844 { "bvc", "jvc", },
3845 { "bvs", "jvs", },
3846 { "bpl", "jpl", },
3847 { "bmi", "jmi", },
3848 { "bge", "jge", },
3849 { "blt", "jlt", },
3850 { "bgt", "jgt", },
3851 { "ble", "jle", },
3852 { "bra", "jra", },
3853 { "bsr", "jbsr", },
3854 };
3855
8fce3f5e
AM		 3856 for (i = 0;
3857 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3858 i++)
252b5132
RH		 3859 {
3860 const char *name = mri_aliases[i].primary;
3861 const char *alias = mri_aliases[i].alias;
3862 PTR val = hash_find (op_hash, name);
3863 if (!val)
3864 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3865 retval = hash_jam (op_hash, alias, val);
3866 if (retval)
3867 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3868 }
3869 }
3870
8fce3f5e 3871 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3872 {
3873 notend_table[i] = 0;
3874 alt_notend_table[i] = 0;
3875 }
3876 notend_table[','] = 1;
3877 notend_table['{'] = 1;
3878 notend_table['}'] = 1;
3879 alt_notend_table['a'] = 1;
3880 alt_notend_table['A'] = 1;
3881 alt_notend_table['d'] = 1;
3882 alt_notend_table['D'] = 1;
3883 alt_notend_table['#'] = 1;
3884 alt_notend_table['&'] = 1;
3885 alt_notend_table['f'] = 1;
3886 alt_notend_table['F'] = 1;
3887#ifdef REGISTER_PREFIX
3888 alt_notend_table[REGISTER_PREFIX] = 1;
3889#endif
3890
3891 /* We need to put '(' in alt_notend_table to handle
3892 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3893 */
3894 alt_notend_table['('] = 1;
3895
3896 /* We need to put '@' in alt_notend_table to handle
3897 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3898 */
3899 alt_notend_table['@'] = 1;
3900
3901 /* We need to put digits in alt_notend_table to handle
3902 bfextu %d0{24:1},%d0
3903 */
3904 alt_notend_table['0'] = 1;
3905 alt_notend_table['1'] = 1;
3906 alt_notend_table['2'] = 1;
3907 alt_notend_table['3'] = 1;
3908 alt_notend_table['4'] = 1;
3909 alt_notend_table['5'] = 1;
3910 alt_notend_table['6'] = 1;
3911 alt_notend_table['7'] = 1;
3912 alt_notend_table['8'] = 1;
3913 alt_notend_table['9'] = 1;
3914
3915#ifndef MIT_SYNTAX_ONLY
3916 /* Insert pseudo ops, these have to go into the opcode table since
3917 gas expects pseudo ops to start with a dot */
3918 {
3919 int n = 0;
3920 while (mote_pseudo_table[n].poc_name)
3921 {
3922 hack = (struct m68k_incant *)
3923 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3924 hash_insert (op_hash,
3925 mote_pseudo_table[n].poc_name, (char *) hack);
3926 hack->m_operands = 0;
3927 hack->m_opnum = n;
3928 n++;
3929 }
3930 }
3931#endif
3932
3933 init_regtable ();
3934
3935#ifdef OBJ_ELF
3936 record_alignment (text_section, 2);
3937 record_alignment (data_section, 2);
3938 record_alignment (bss_section, 2);
3939#endif
3940}
3941
3942static void
3943select_control_regs ()
3944{
3945 /* Note which set of "movec" control registers is available. */
3946 switch (cpu_of_arch (current_architecture))
3947 {
4f2a7c9e
NC		 3948 case 0:
3949 as_warn (_("architecture not yet selected: defaulting to 68020"));
3950 control_regs = m68020_control_regs;
3951 break;
3952
252b5132
RH		 3953 case m68000:
3954 control_regs = m68000_control_regs;
3955 break;
3956 case m68010:
3957 control_regs = m68010_control_regs;
3958 break;
3959 case m68020:
3960 case m68030:
3961 control_regs = m68020_control_regs;
3962 break;
3963 case m68040:
3964 control_regs = m68040_control_regs;
3965 break;
3966 case m68060:
3967 control_regs = m68060_control_regs;
3968 break;
3969 case cpu32:
3970 control_regs = cpu32_control_regs;
3971 break;
3972 case mcf5200:
6da466c7
ILT		 3973 case mcf5206e:
3974 case mcf5307:
dc84e067 3975 case mcf5407:
6da466c7 3976 control_regs = mcf_control_regs;
252b5132
RH		 3977 break;
3978 default:
3979 abort ();
3980 }
3981}
3982
3983void
3984m68k_init_after_args ()
3985{
3986 if (cpu_of_arch (current_architecture) == 0)
3987 {
3988 int i;
3989 const char *default_cpu = TARGET_CPU;
3990
3991 if (*default_cpu == 'm')
3992 default_cpu++;
3993 for (i = 0; i < n_archs; i++)
3994 if (strcasecmp (default_cpu, archs[i].name) == 0)
3995 break;
3996 if (i == n_archs)
3997 {
3998 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3999 current_architecture |= m68020;
4000 }
4001 else
4002 current_architecture |= archs[i].arch;
4003 }
4004 /* Permit m68881 specification with all cpus; those that can't work
4005 with a coprocessor could be doing emulation. */
4006 if (current_architecture & m68851)
4007 {
4008 if (current_architecture & m68040)
4009 {
4010 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4011 }
4012 }
4013 /* What other incompatibilities could we check for? */
4014
4015 /* Toss in some default assumptions about coprocessors. */
4016 if (!no_68881
4017 && (cpu_of_arch (current_architecture)
4018 /* Can CPU32 have a 68881 coprocessor?? */
4019 & (m68020 | m68030 | cpu32)))
4020 {
4021 current_architecture |= m68881;
4022 }
4023 if (!no_68851
4024 && (cpu_of_arch (current_architecture) & m68020up) != 0
4025 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4026 {
4027 current_architecture |= m68851;
4028 }
4029 if (no_68881 && (current_architecture & m68881))
4030 as_bad (_("options for 68881 and no-68881 both given"));
4031 if (no_68851 && (current_architecture & m68851))
4032 as_bad (_("options for 68851 and no-68851 both given"));
4033
4034#ifdef OBJ_AOUT
4035 /* Work out the magic number. This isn't very general. */
4036 if (current_architecture & m68000)
4037 m68k_aout_machtype = 0;
4038 else if (current_architecture & m68010)
4039 m68k_aout_machtype = 1;
4040 else if (current_architecture & m68020)
4041 m68k_aout_machtype = 2;
4042 else
4043 m68k_aout_machtype = 2;
4044#endif
4045
4046 /* Note which set of "movec" control registers is available. */
4047 select_control_regs ();
4048
4049 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4050 || arch_coldfire_p (current_architecture))
252b5132
RH		 4051 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4052}
4053\f
4054/* This is called when a label is defined. */
4055
4056void
4057m68k_frob_label (sym)
4058 symbolS *sym;
4059{
4060 struct label_line *n;
4061
4062 n = (struct label_line *) xmalloc (sizeof *n);
4063 n->next = labels;
4064 n->label = sym;
4065 as_where (&n->file, &n->line);
4066 n->text = 0;
4067 labels = n;
4068 current_label = n;
4069}
4070
4071/* This is called when a value that is not an instruction is emitted. */
4072
4073void
4074m68k_flush_pending_output ()
4075{
4076 current_label = NULL;
4077}
4078
4079/* This is called at the end of the assembly, when the final value of
4080 the label is known. We warn if this is a text symbol aligned at an
4081 odd location. */
4082
4083void
4084m68k_frob_symbol (sym)
4085 symbolS *sym;
4086{
4087 if (S_GET_SEGMENT (sym) == reg_section
4088 && (int) S_GET_VALUE (sym) < 0)
4089 {
4090 S_SET_SEGMENT (sym, absolute_section);
4091 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4092 }
4093 else if ((S_GET_VALUE (sym) & 1) != 0)
4094 {
4095 struct label_line *l;
4096
4097 for (l = labels; l != NULL; l = l->next)
4098 {
4099 if (l->label == sym)
4100 {
4101 if (l->text)
4102 as_warn_where (l->file, l->line,
4103 _("text label `%s' aligned to odd boundary"),
4104 S_GET_NAME (sym));
4105 break;
4106 }
4107 }
4108 }
4109}
4110\f
4111/* This is called if we go in or out of MRI mode because of the .mri
4112 pseudo-op. */
4113
4114void
4115m68k_mri_mode_change (on)
4116 int on;
4117{
4118 if (on)
4119 {
4120 if (! flag_reg_prefix_optional)
4121 {
4122 flag_reg_prefix_optional = 1;
4123#ifdef REGISTER_PREFIX
4124 init_regtable ();
4125#endif
4126 }
4127 m68k_abspcadd = 1;
4128 if (! m68k_rel32_from_cmdline)
4129 m68k_rel32 = 0;
4130 }
4131 else
4132 {
4133 if (! reg_prefix_optional_seen)
4134 {
4135#ifdef REGISTER_PREFIX_OPTIONAL
4136 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4137#else
4138 flag_reg_prefix_optional = 0;
4139#endif
4140#ifdef REGISTER_PREFIX
4141 init_regtable ();
4142#endif
4143 }
4144 m68k_abspcadd = 0;
4145 if (! m68k_rel32_from_cmdline)
4146 m68k_rel32 = 1;
4147 }
4148}
4149
4150/* Equal to MAX_PRECISION in atof-ieee.c */
4151#define MAX_LITTLENUMS 6
4152
4153/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4154 of type TYPE, and store the appropriate bytes in *LITP. The number
4155 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4156 returned, or NULL on OK. */
4157
4158char *
4159md_atof (type, litP, sizeP)
4160 char type;
4161 char *litP;
4162 int *sizeP;
4163{
4164 int prec;
4165 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4166 LITTLENUM_TYPE *wordP;
4167 char *t;
4168
4169 switch (type)
4170 {
4171 case 'f':
4172 case 'F':
4173 case 's':
4174 case 'S':
4175 prec = 2;
4176 break;
4177
4178 case 'd':
4179 case 'D':
4180 case 'r':
4181 case 'R':
4182 prec = 4;
4183 break;
4184
4185 case 'x':
4186 case 'X':
4187 prec = 6;
4188 break;
4189
4190 case 'p':
4191 case 'P':
4192 prec = 6;
4193 break;
4194
4195 default:
4196 *sizeP = 0;
4197 return _("Bad call to MD_ATOF()");
4198 }
4199 t = atof_ieee (input_line_pointer, type, words);
4200 if (t)
4201 input_line_pointer = t;
4202
4203 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4204 for (wordP = words; prec--;)
4205 {
4206 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4207 litP += sizeof (LITTLENUM_TYPE);
4208 }
4209 return 0;
4210}
4211
4212void
4213md_number_to_chars (buf, val, n)
4214 char *buf;
4215 valueT val;
4216 int n;
4217{
4218 number_to_chars_bigendian (buf, val, n);
4219}
4220
94f592af
NC		 4221void
4222md_apply_fix3 (fixP, valP, seg)
252b5132 4223 fixS *fixP;
bbe8ef22 4224 valueT *valP;
94f592af 4225 segT seg ATTRIBUTE_UNUSED;
252b5132 4226{
bbe8ef22 4227 offsetT val = *valP;
252b5132
RH		 4228 addressT upper_limit;
4229 offsetT lower_limit;
4230
4231 /* This is unnecessary but it convinces the native rs6000 compiler
4232 to generate the code we want. */
4233 char *buf = fixP->fx_frag->fr_literal;
4234 buf += fixP->fx_where;
4235 /* end ibm compiler workaround */
4236
c801568a 4237 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132 4238
94f592af
NC		 4239 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4240 fixP->fx_done = 1;
4241
252b5132
RH		 4242#ifdef OBJ_ELF
4243 if (fixP->fx_addsy)
4244 {
4245 memset (buf, 0, fixP->fx_size);
4246 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4247
4248 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4249 && !S_IS_DEFINED (fixP->fx_addsy)
4250 && !S_IS_WEAK (fixP->fx_addsy))
4251 S_SET_WEAK (fixP->fx_addsy);
4252 return;
4253 }
4254#endif
4255
4256#ifdef BFD_ASSEMBLER
4257 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4258 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4259 return;
4260#endif
4261
4262 switch (fixP->fx_size)
4263 {
94f592af
NC		 4264 /* The cast to offsetT below are necessary to make code
4265 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4266 case 1:
4267 *buf++ = val;
4268 upper_limit = 0x7f;
4269 lower_limit = - (offsetT) 0x80;
4270 break;
4271 case 2:
4272 *buf++ = (val >> 8);
4273 *buf++ = val;
4274 upper_limit = 0x7fff;
4275 lower_limit = - (offsetT) 0x8000;
4276 break;
4277 case 4:
4278 *buf++ = (val >> 24);
4279 *buf++ = (val >> 16);
4280 *buf++ = (val >> 8);
4281 *buf++ = val;
4282 upper_limit = 0x7fffffff;
4283 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4284 break;
4285 default:
4286 BAD_CASE (fixP->fx_size);
4287 }
4288
4289 /* Fix up a negative reloc. */
4290 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4291 {
4292 fixP->fx_addsy = fixP->fx_subsy;
4293 fixP->fx_subsy = NULL;
4294 fixP->fx_tcbit = 1;
4295 }
4296
4297 /* For non-pc-relative values, it's conceivable we might get something
4298 like "0xff" for a byte field. So extend the upper part of the range
4299 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4300 so that we can do any range checking at all. */
4301 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4302 upper_limit = upper_limit * 2 + 1;
4303
4304 if ((addressT) val > upper_limit
4305 && (val > 0 || val < lower_limit))
4306 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4307
4308 /* A one byte PC-relative reloc means a short branch. We can't use
4309 a short branch with a value of 0 or -1, because those indicate
4310 different opcodes (branches with longer offsets). fixup_segment
4311 in write.c may have clobbered fx_pcrel, so we need to examine the
4312 reloc type. */
4313 if ((fixP->fx_pcrel
4314#ifdef BFD_ASSEMBLER
4315 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4316#endif
4317 )
4318 && fixP->fx_size == 1
4319 && (fixP->fx_addsy == NULL
4320 || S_IS_DEFINED (fixP->fx_addsy))
4321 && (val == 0 || val == -1))
4322 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4323}
4324
252b5132
RH		 4325/* *fragP has been relaxed to its final size, and now needs to have
4326 the bytes inside it modified to conform to the new size There is UGLY
4327 MAGIC here. ..
4328 */
4329static void
4330md_convert_frag_1 (fragP)
4331 register fragS *fragP;
4332{
4333 long disp;
252b5132
RH		 4334 fixS *fixP;
4335
4336 /* Address in object code of the displacement. */
4337 register int object_address = fragP->fr_fix + fragP->fr_address;
4338
4339 /* Address in gas core of the place to store the displacement. */
4340 /* This convinces the native rs6000 compiler to generate the code we
92774660 4341 want. */
252b5132
RH		 4342 register char *buffer_address = fragP->fr_literal;
4343 buffer_address += fragP->fr_fix;
4344 /* end ibm compiler workaround */
4345
4346 /* The displacement of the address, from current location. */
4347 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4348 disp = (disp + fragP->fr_offset) - object_address;
4349
252b5132
RH		 4350 switch (fragP->fr_subtype)
4351 {
151337e8
NC		 4352 case TAB (BRANCHBWL, BYTE):
4353 case TAB (BRABSJUNC, BYTE):
4354 case TAB (BRABSJCOND, BYTE):
4355 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4356 know (issbyte (disp));
4357 if (disp == 0)
b091f402
AM		 4358 as_bad_where (fragP->fr_file, fragP->fr_line,
4359 _("short branch with zero offset: use :w"));
151337e8 4360 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4361 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4362 fixP->fx_pcrel_adjust = -1;
252b5132 4363 break;
151337e8
NC		 4364 case TAB (BRANCHBWL, SHORT):
4365 case TAB (BRABSJUNC, SHORT):
4366 case TAB (BRABSJCOND, SHORT):
4367 case TAB (BRANCHBW, SHORT):
252b5132 4368 fragP->fr_opcode[1] = 0x00;
151337e8 4369 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4370 1, RELAX_RELOC_PC16);
151337e8
NC		 4371 fragP->fr_fix += 2;
4372 break;
4373 case TAB (BRANCHBWL, LONG):
4374 fragP->fr_opcode[1] = (char) 0xFF;
4375 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4376 1, RELAX_RELOC_PC32);
151337e8 4377 fragP->fr_fix += 4;
252b5132 4378 break;
151337e8
NC		 4379 case TAB (BRABSJUNC, LONG):
4380 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4381 {
151337e8
NC		 4382 fragP->fr_opcode[0] = 0x4E;
4383 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4384 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4385 0, RELAX_RELOC_ABS32);
151337e8
NC		 4386 fragP->fr_fix += 4;
4387 }
4388 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4389 {
4390 fragP->fr_opcode[0] = 0x4E;
4391 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4392 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4393 0, RELAX_RELOC_ABS32);
151337e8 4394 fragP->fr_fix += 4;
252b5132
RH		 4395 }
4396 else
4397 {
151337e8
NC		 4398 /* This cannot happen, because jbsr and jbra are the only two
4399 unconditional branches. */
4400 abort ();
252b5132
RH		 4401 }
4402 break;
151337e8
NC		 4403 case TAB (BRABSJCOND, LONG):
4404 /* Only Bcc 68000 instructions can come here. */
4405 /* Change bcc into b!cc/jmp absl long. */
92774660 4406
252b5132
RH		 4407 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4408 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4409
4410 /* JF: these used to be fr_opcode[2,3], but they may be in a
4411 different frag, in which case refering to them is a no-no.
92774660 4412 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4413 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4414 *buffer_address++ = (char) 0xf9;
4415 fragP->fr_fix += 2; /* account for jmp instruction */
4416 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4417 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4418 fragP->fr_fix += 4;
4419 break;
4420 case TAB (FBRANCH, SHORT):
4421 know ((fragP->fr_opcode[1] & 0x40) == 0);
4422 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4423 1, RELAX_RELOC_PC16);
151337e8
NC		 4424 fragP->fr_fix += 2;
4425 break;
4426 case TAB (FBRANCH, LONG):
4427 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4428 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4429 1, RELAX_RELOC_PC32);
252b5132 4430 fragP->fr_fix += 4;
252b5132 4431 break;
151337e8
NC		 4432 case TAB (DBCCLBR, SHORT):
4433 case TAB (DBCCABSJ, SHORT):
4434 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4435 1, RELAX_RELOC_PC16);
151337e8
NC		 4436 fragP->fr_fix += 2;
4437 break;
4438 case TAB (DBCCLBR, LONG):
4439 /* only DBcc instructions can come here */
28e7409f 4440 /* Change dbcc into dbcc/bral. */
28e7409f 4441
252b5132
RH		 4442 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4443 *buffer_address++ = 0x00; /* branch offset = 4 */
4444 *buffer_address++ = 0x04;
4445 *buffer_address++ = 0x60; /* put in bra pc+6 */
4446 *buffer_address++ = 0x06;
151337e8
NC		 4447 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4448 *buffer_address++ = (char) 0xff;
252b5132
RH		 4449
4450 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8 4451 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4452 RELAX_RELOC_PC32);
252b5132 4453 fragP->fr_fix += 4;
252b5132 4454 break;
151337e8
NC		 4455 case TAB (DBCCABSJ, LONG):
4456 /* only DBcc instructions can come here */
4457 /* Change dbcc into dbcc/jmp. */
4458
4459 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4460 *buffer_address++ = 0x00; /* branch offset = 4 */
4461 *buffer_address++ = 0x04;
4462 *buffer_address++ = 0x60; /* put in bra pc+6 */
4463 *buffer_address++ = 0x06;
4464 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4465 *buffer_address++ = (char) 0xf9;
4466
4467 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4468 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4469 RELAX_RELOC_ABS32);
252b5132 4470 fragP->fr_fix += 4;
252b5132 4471 break;
151337e8 4472 case TAB (PCREL1632, SHORT):
252b5132
RH		 4473 fragP->fr_opcode[1] &= ~0x3F;
4474 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4475 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4476 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4477 fragP->fr_fix += 2;
252b5132 4478 break;
151337e8 4479 case TAB (PCREL1632, LONG):
252b5132
RH		 4480 /* Already set to mode 7.3; this indicates: PC indirect with
4481 suppressed index, 32-bit displacement. */
4482 *buffer_address++ = 0x01;
4483 *buffer_address++ = 0x70;
4484 fragP->fr_fix += 2;
151337e8 4485 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4486 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4487 fixP->fx_pcrel_adjust = 2;
4488 fragP->fr_fix += 4;
252b5132 4489 break;
252b5132 4490 case TAB (PCINDEX, BYTE):
252b5132
RH		 4491 assert (fragP->fr_fix >= 2);
4492 buffer_address[-2] &= ~1;
151337e8 4493 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4494 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4495 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4496 break;
4497 case TAB (PCINDEX, SHORT):
252b5132
RH		 4498 assert (fragP->fr_fix >= 2);
4499 buffer_address[-2] |= 0x1;
4500 buffer_address[-1] = 0x20;
4501 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4502 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4503 fixP->fx_pcrel_adjust = 2;
151337e8 4504 fragP->fr_fix += 2;
252b5132
RH		 4505 break;
4506 case TAB (PCINDEX, LONG):
252b5132
RH		 4507 assert (fragP->fr_fix >= 2);
4508 buffer_address[-2] |= 0x1;
4509 buffer_address[-1] = 0x30;
151337e8 4510 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4511 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4512 fixP->fx_pcrel_adjust = 2;
4513 fragP->fr_fix += 4;
4514 break;
4515 case TAB (ABSTOPCREL, SHORT):
4516 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4517 1, RELAX_RELOC_PC16);
151337e8
NC		 4518 fragP->fr_fix += 2;
4519 break;
4520 case TAB (ABSTOPCREL, LONG):
4521 /* The thing to do here is force it to ABSOLUTE LONG, since
4522 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4523 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4524 abort ();
4525 fragP->fr_opcode[1] &= ~0x3F;
4526 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4527 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4528 0, RELAX_RELOC_ABS32);
151337e8 4529 fragP->fr_fix += 4;
252b5132 4530 break;
252b5132
RH		 4531 }
4532}
4533
4534#ifndef BFD_ASSEMBLER
4535
4536void
4537md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4538 object_headers *headers ATTRIBUTE_UNUSED;
4539 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4540 fragS *fragP;
4541{
4542 md_convert_frag_1 (fragP);
4543}
4544
4545#else
4546
4547void
4548md_convert_frag (abfd, sec, fragP)
36823076
AS		 4549 bfd *abfd ATTRIBUTE_UNUSED;
4550 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4551 fragS *fragP;
4552{
4553 md_convert_frag_1 (fragP);
4554}
4555#endif
4556
4557/* Force truly undefined symbols to their maximum size, and generally set up
4558 the frag list to be relaxed
4559 */
4560int
4561md_estimate_size_before_relax (fragP, segment)
4562 register fragS *fragP;
4563 segT segment;
4564{
151337e8 4565 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4566 switch (fragP->fr_subtype)
4567 {
151337e8
NC		 4568 case TAB (BRANCHBWL, SZ_UNDEF):
4569 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4570 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4571 {
151337e8
NC		 4572 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4573 && relaxable_symbol (fragP->fr_symbol))
252b5132 4574 {
151337e8
NC		 4575 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4576 }
4577 else if (flag_short_refs)
4578 {
4579 /* Symbol is undefined and we want short ref. */
4580 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4581 }
4582 else
4583 {
151337e8
NC		 4584 /* Symbol is still undefined. Make it LONG. */
4585 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4586 }
4587 break;
151337e8 4588 }
252b5132 4589
151337e8 4590 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4591 {
151337e8
NC		 4592 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4593 && relaxable_symbol (fragP->fr_symbol))
252b5132 4594 {
151337e8 4595 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4596 }
4597 else
4598 {
151337e8
NC		 4599 /* Symbol is undefined and we don't have long branches. */
4600 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4601 }
4602 break;
151337e8 4603 }
252b5132 4604
151337e8 4605 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4606 case TAB (DBCCLBR, SZ_UNDEF):
4607 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4608 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4609 {
8ec6253e
NC		 4610 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4611 && relaxable_symbol (fragP->fr_symbol))
151337e8 4612 || flag_short_refs)
252b5132 4613 {
151337e8 4614 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4615 }
4616 else
4617 {
151337e8 4618 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4619 }
4620 break;
151337e8 4621 }
81d4177b 4622
252b5132
RH		 4623 case TAB (PCINDEX, SZ_UNDEF):
4624 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4625 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4626 {
4627 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4628 }
4629 else
4630 {
4631 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4632 }
4633 break;
4634
151337e8
NC		 4635 case TAB (ABSTOPCREL, SZ_UNDEF):
4636 {
4637 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4638 && relaxable_symbol (fragP->fr_symbol)))
4639 {
4640 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4641 }
4642 else
4643 {
4644 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4645 }
4646 break;
4647 }
4648
252b5132
RH		 4649 default:
4650 break;
4651 }
4652
151337e8 4653 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4654 switch (fragP->fr_subtype)
4655 {
151337e8
NC		 4656 case TAB (BRANCHBWL, BYTE):
4657 case TAB (BRABSJUNC, BYTE):
4658 case TAB (BRABSJCOND, BYTE):
4659 case TAB (BRANCHBW, BYTE):
252b5132 4660 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4661 case we force word mode. If the symbol is at the start of a
4662 frag, and it is the next frag with any data in it (usually
4663 this is just the next frag, but assembler listings may
4664 introduce empty frags), we must use word mode. */
4665 if (fragP->fr_symbol)
252b5132 4666 {
ac62c346 4667 fragS *sym_frag;
252b5132 4668
ac62c346
AM		 4669 sym_frag = symbol_get_frag (fragP->fr_symbol);
4670 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4671 {
ac62c346
AM		 4672 fragS *l;
4673
23b7f870 4674 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4675 if (l->fr_fix != 0)
4676 break;
4677 if (l == sym_frag)
4678 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4679 }
4680 }
4681 break;
4682 default:
4683 break;
4684 }
ac62c346 4685 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4686}
4687
4688#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4689/* the bit-field entries in the relocation_info struct plays hell
4690 with the byte-order problems of cross-assembly. So as a hack,
4691 I added this mach. dependent ri twiddler. Ugly, but it gets
4692 you there. -KWK */
4693/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4694 are symbolnum, most sig. byte first. Last byte is broken up with
4695 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4696 nibble as nuthin. (on Sun 3 at least) */
4697/* Translate the internal relocation information into target-specific
92774660 4698 format. */
252b5132
RH		 4699#ifdef comment
4700void
4701md_ri_to_chars (the_bytes, ri)
4702 char *the_bytes;
4703 struct reloc_info_generic *ri;
4704{
4705 /* this is easy */
4706 md_number_to_chars (the_bytes, ri->r_address, 4);
4707 /* now the fun stuff */
4708 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4709 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4710 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4711 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4712 ((ri->r_extern << 4) & 0x10));
4713}
4714
4715#endif /* comment */
4716
4717#ifndef BFD_ASSEMBLER
4718void
4719tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4720 char *where;
4721 fixS *fixP;
4722 relax_addressT segment_address_in_file;
4723{
4724 /*
4725 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4726 * Out: GNU LD relocation length code: 0, 1, or 2.
4727 */
4728
5a38dc70 4729 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
252b5132
RH		 4730 long r_symbolnum;
4731
4732 know (fixP->fx_addsy != NULL);
4733
4734 md_number_to_chars (where,
4735 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4736 4);
4737
4738 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4739 ? S_GET_TYPE (fixP->fx_addsy)
4740 : fixP->fx_addsy->sy_number);
4741
4742 where[4] = (r_symbolnum >> 16) & 0x0ff;
4743 where[5] = (r_symbolnum >> 8) & 0x0ff;
4744 where[6] = r_symbolnum & 0x0ff;
4745 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4746 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4747}
4748#endif
4749
4750#endif /* OBJ_AOUT or OBJ_BOUT */
4751
4752#ifndef WORKING_DOT_WORD
5a38dc70
AM		 4753const int md_short_jump_size = 4;
4754const int md_long_jump_size = 6;
252b5132
RH		 4755
4756void
4757md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4758 char *ptr;
4759 addressT from_addr, to_addr;
36823076
AS		 4760 fragS *frag ATTRIBUTE_UNUSED;
4761 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4762{
4763 valueT offset;
4764
4765 offset = to_addr - (from_addr + 2);
4766
4767 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4768 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4769}
4770
4771void
4772md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4773 char *ptr;
4774 addressT from_addr, to_addr;
4775 fragS *frag;
4776 symbolS *to_symbol;
4777{
4778 valueT offset;
4779
4780 if (!HAVE_LONG_BRANCH(current_architecture))
4781 {
4782 offset = to_addr - S_GET_VALUE (to_symbol);
4783 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4784 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4785 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4786 0, NO_RELOC);
4787 }
4788 else
4789 {
4790 offset = to_addr - (from_addr + 2);
4791 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4792 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4793 }
4794}
4795
4796#endif
4797
4798/* Different values of OK tell what its OK to return. Things that
4799 aren't OK are an error (what a shock, no?)
4800
4801 0: Everything is OK
4802 10: Absolute 1:8 only
4803 20: Absolute 0:7 only
4804 30: absolute 0:15 only
4805 40: Absolute 0:31 only
4806 50: absolute 0:127 only
4807 55: absolute -64:63 only
4808 60: absolute -128:127 only
4809 70: absolute 0:4095 only
4810 80: No bignums
4811
4812 */
4813
4814static int
4815get_num (exp, ok)
4816 struct m68k_exp *exp;
4817 int ok;
4818{
4819 if (exp->exp.X_op == O_absent)
4820 {
4821 /* Do the same thing the VAX asm does */
4822 op (exp) = O_constant;
4823 adds (exp) = 0;
4824 subs (exp) = 0;
4825 offs (exp) = 0;
4826 if (ok == 10)
4827 {
4828 as_warn (_("expression out of range: defaulting to 1"));
4829 offs (exp) = 1;
4830 }
4831 }
4832 else if (exp->exp.X_op == O_constant)
4833 {
4834 switch (ok)
4835 {
4836 case 10:
4837 if (offs (exp) < 1 || offs (exp) > 8)
4838 {
4839 as_warn (_("expression out of range: defaulting to 1"));
4840 offs (exp) = 1;
4841 }
4842 break;
4843 case 20:
4844 if (offs (exp) < 0 || offs (exp) > 7)
4845 goto outrange;
4846 break;
4847 case 30:
4848 if (offs (exp) < 0 || offs (exp) > 15)
4849 goto outrange;
4850 break;
4851 case 40:
4852 if (offs (exp) < 0 || offs (exp) > 32)
4853 goto outrange;
4854 break;
4855 case 50:
4856 if (offs (exp) < 0 || offs (exp) > 127)
4857 goto outrange;
4858 break;
4859 case 55:
4860 if (offs (exp) < -64 || offs (exp) > 63)
4861 goto outrange;
4862 break;
4863 case 60:
4864 if (offs (exp) < -128 || offs (exp) > 127)
4865 goto outrange;
4866 break;
4867 case 70:
4868 if (offs (exp) < 0 || offs (exp) > 4095)
4869 {
4870 outrange:
4871 as_warn (_("expression out of range: defaulting to 0"));
4872 offs (exp) = 0;
4873 }
4874 break;
4875 default:
4876 break;
4877 }
4878 }
4879 else if (exp->exp.X_op == O_big)
4880 {
4881 if (offs (exp) <= 0 /* flonum */
4882 && (ok == 80 /* no bignums */
4883 || (ok > 10 /* small-int ranges including 0 ok */
4884 /* If we have a flonum zero, a zero integer should
4885 do as well (e.g., in moveq). */
4886 && generic_floating_point_number.exponent == 0
4887 && generic_floating_point_number.low[0] == 0)))
4888 {
4889 /* HACK! Turn it into a long */
4890 LITTLENUM_TYPE words[6];
4891
4892 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4893 op (exp) = O_constant;
4894 adds (exp) = 0;
4895 subs (exp) = 0;
4896 offs (exp) = words[1] | (words[0] << 16);
4897 }
4898 else if (ok != 0)
4899 {
4900 op (exp) = O_constant;
4901 adds (exp) = 0;
4902 subs (exp) = 0;
4903 offs (exp) = (ok == 10) ? 1 : 0;
4904 as_warn (_("Can't deal with expression; defaulting to %ld"),
4905 offs (exp));
4906 }
4907 }
4908 else
4909 {
4910 if (ok >= 10 && ok <= 70)
4911 {
4912 op (exp) = O_constant;
4913 adds (exp) = 0;
4914 subs (exp) = 0;
4915 offs (exp) = (ok == 10) ? 1 : 0;
4916 as_warn (_("Can't deal with expression; defaulting to %ld"),
4917 offs (exp));
4918 }
4919 }
4920
4921 if (exp->size != SIZE_UNSPEC)
4922 {
4923 switch (exp->size)
4924 {
4925 case SIZE_UNSPEC:
4926 case SIZE_LONG:
4927 break;
4928 case SIZE_BYTE:
4929 if (!isbyte (offs (exp)))
4930 as_warn (_("expression doesn't fit in BYTE"));
4931 break;
4932 case SIZE_WORD:
4933 if (!isword (offs (exp)))
4934 as_warn (_("expression doesn't fit in WORD"));
4935 break;
4936 }
4937 }
4938
4939 return offs (exp);
4940}
4941
4942/* These are the back-ends for the various machine dependent pseudo-ops. */
4943
4944static void
4945s_data1 (ignore)
36823076 4946 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4947{
4948 subseg_set (data_section, 1);
4949 demand_empty_rest_of_line ();
4950}
4951
4952static void
4953s_data2 (ignore)
36823076 4954 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4955{
4956 subseg_set (data_section, 2);
4957 demand_empty_rest_of_line ();
4958}
4959
4960static void
4961s_bss (ignore)
36823076 4962 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4963{
4964 /* We don't support putting frags in the BSS segment, we fake it
4965 by marking in_bss, then looking at s_skip for clues. */
4966
4967 subseg_set (bss_section, 0);
4968 demand_empty_rest_of_line ();
4969}
4970
4971static void
4972s_even (ignore)
36823076 4973 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4974{
4975 register int temp;
4976 register long temp_fill;
4977
4978 temp = 1; /* JF should be 2? */
4979 temp_fill = get_absolute_expression ();
92774660 4980 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 4981 frag_align (temp, (int) temp_fill, 0);
4982 demand_empty_rest_of_line ();
4983 record_alignment (now_seg, temp);
4984}
4985
4986static void
4987s_proc (ignore)
36823076 4988 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4989{
4990 demand_empty_rest_of_line ();
4991}
4992\f
4993/* Pseudo-ops handled for MRI compatibility. */
4994
4995/* This function returns non-zero if the argument is a conditional
4996 pseudo-op. This is called when checking whether a pending
4997 alignment is needed. */
4998
4999int
5000m68k_conditional_pseudoop (pop)
5001 pseudo_typeS *pop;
5002{
5003 return (pop->poc_handler == s_mri_if
5004 || pop->poc_handler == s_mri_else);
5005}
5006
5007/* Handle an MRI style chip specification. */
5008
5009static void
5010mri_chip ()
5011{
5012 char *s;
5013 char c;
5014 int i;
5015
5016 s = input_line_pointer;
5017 /* We can't use get_symbol_end since the processor names are not proper
5018 symbols. */
5019 while (is_part_of_name (c = *input_line_pointer++))
5020 ;
5021 *--input_line_pointer = 0;
5022 for (i = 0; i < n_archs; i++)
5023 if (strcasecmp (s, archs[i].name) == 0)
5024 break;
5025 if (i >= n_archs)
5026 {
5027 as_bad (_("%s: unrecognized processor name"), s);
5028 *input_line_pointer = c;
5029 ignore_rest_of_line ();
5030 return;
5031 }
5032 *input_line_pointer = c;
5033
5034 if (*input_line_pointer == '/')
5035 current_architecture = 0;
5036 else
5037 current_architecture &= m68881 | m68851;
5038 current_architecture |= archs[i].arch;
5039
5040 while (*input_line_pointer == '/')
5041 {
5042 ++input_line_pointer;
5043 s = input_line_pointer;
5044 /* We can't use get_symbol_end since the processor names are not
5045 proper symbols. */
5046 while (is_part_of_name (c = *input_line_pointer++))
5047 ;
5048 *--input_line_pointer = 0;
5049 if (strcmp (s, "68881") == 0)
5050 current_architecture |= m68881;
5051 else if (strcmp (s, "68851") == 0)
5052 current_architecture |= m68851;
5053 *input_line_pointer = c;
5054 }
5055
5056 /* Update info about available control registers. */
5057 select_control_regs ();
5058}
5059
5060/* The MRI CHIP pseudo-op. */
5061
5062static void
5063s_chip (ignore)
36823076 5064 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5065{
5066 char *stop = NULL;
5067 char stopc;
5068
5069 if (flag_mri)
5070 stop = mri_comment_field (&stopc);
5071 mri_chip ();
5072 if (flag_mri)
5073 mri_comment_end (stop, stopc);
5074 demand_empty_rest_of_line ();
5075}
5076
5077/* The MRI FOPT pseudo-op. */
5078
5079static void
5080s_fopt (ignore)
36823076 5081 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5082{
5083 SKIP_WHITESPACE ();
5084
5085 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5086 {
5087 int temp;
5088
5089 input_line_pointer += 3;
5090 temp = get_absolute_expression ();
5091 if (temp < 0 || temp > 7)
5092 as_bad (_("bad coprocessor id"));
5093 else
5094 m68k_float_copnum = COP0 + temp;
5095 }
5096 else
5097 {
5098 as_bad (_("unrecognized fopt option"));
5099 ignore_rest_of_line ();
5100 return;
5101 }
5102
5103 demand_empty_rest_of_line ();
5104}
5105
5106/* The structure used to handle the MRI OPT pseudo-op. */
5107
5108struct opt_action
5109{
5110 /* The name of the option. */
5111 const char *name;
5112
5113 /* If this is not NULL, just call this function. The first argument
5114 is the ARG field of this structure, the second argument is
5115 whether the option was negated. */
5116 void (*pfn) PARAMS ((int arg, int on));
5117
5118 /* If this is not NULL, and the PFN field is NULL, set the variable
5119 this points to. Set it to the ARG field if the option was not
5120 negated, and the NOTARG field otherwise. */
5121 int *pvar;
5122
5123 /* The value to pass to PFN or to assign to *PVAR. */
5124 int arg;
5125
5126 /* The value to assign to *PVAR if the option is negated. If PFN is
5127 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5128 the option may not be negated. */
5129 int notarg;
5130};
5131
5132/* The table used to handle the MRI OPT pseudo-op. */
5133
5134static void skip_to_comma PARAMS ((int, int));
5135static void opt_nest PARAMS ((int, int));
5136static void opt_chip PARAMS ((int, int));
5137static void opt_list PARAMS ((int, int));
5138static void opt_list_symbols PARAMS ((int, int));
5139
5140static const struct opt_action opt_table[] =
5141{
5142 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5143
5144 /* We do relaxing, so there is little use for these options. */
5145 { "b", 0, 0, 0, 0 },
5146 { "brs", 0, 0, 0, 0 },
5147 { "brb", 0, 0, 0, 0 },
5148 { "brl", 0, 0, 0, 0 },
5149 { "brw", 0, 0, 0, 0 },
5150
5151 { "c", 0, 0, 0, 0 },
5152 { "cex", 0, 0, 0, 0 },
5153 { "case", 0, &symbols_case_sensitive, 1, 0 },
5154 { "cl", 0, 0, 0, 0 },
5155 { "cre", 0, 0, 0, 0 },
5156 { "d", 0, &flag_keep_locals, 1, 0 },
5157 { "e", 0, 0, 0, 0 },
5158 { "f", 0, &flag_short_refs, 1, 0 },
5159 { "frs", 0, &flag_short_refs, 1, 0 },
5160 { "frl", 0, &flag_short_refs, 0, 1 },
5161 { "g", 0, 0, 0, 0 },
5162 { "i", 0, 0, 0, 0 },
5163 { "m", 0, 0, 0, 0 },
5164 { "mex", 0, 0, 0, 0 },
5165 { "mc", 0, 0, 0, 0 },
5166 { "md", 0, 0, 0, 0 },
5167 { "nest", opt_nest, 0, 0, 0 },
5168 { "next", skip_to_comma, 0, 0, 0 },
5169 { "o", 0, 0, 0, 0 },
5170 { "old", 0, 0, 0, 0 },
5171 { "op", skip_to_comma, 0, 0, 0 },
5172 { "pco", 0, 0, 0, 0 },
5173 { "p", opt_chip, 0, 0, 0 },
5174 { "pcr", 0, 0, 0, 0 },
5175 { "pcs", 0, 0, 0, 0 },
5176 { "r", 0, 0, 0, 0 },
5177 { "quick", 0, &m68k_quick, 1, 0 },
5178 { "rel32", 0, &m68k_rel32, 1, 0 },
5179 { "s", opt_list, 0, 0, 0 },
5180 { "t", opt_list_symbols, 0, 0, 0 },
5181 { "w", 0, &flag_no_warnings, 0, 1 },
5182 { "x", 0, 0, 0, 0 }
5183};
5184
8fce3f5e 5185#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5186
5187/* The MRI OPT pseudo-op. */
5188
5189static void
5190s_opt (ignore)
36823076 5191 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5192{
5193 do
5194 {
5195 int t;
5196 char *s;
5197 char c;
5198 int i;
5199 const struct opt_action *o;
5200
5201 SKIP_WHITESPACE ();
5202
5203 t = 1;
5204 if (*input_line_pointer == '-')
5205 {
5206 ++input_line_pointer;
5207 t = 0;
5208 }
5209 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5210 {
5211 input_line_pointer += 2;
5212 t = 0;
5213 }
5214
5215 s = input_line_pointer;
5216 c = get_symbol_end ();
5217
5218 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5219 {
5220 if (strcasecmp (s, o->name) == 0)
5221 {
5222 if (o->pfn)
5223 {
5224 /* Restore input_line_pointer now in case the option
5225 takes arguments. */
5226 *input_line_pointer = c;
5227 (*o->pfn) (o->arg, t);
5228 }
5229 else if (o->pvar != NULL)
5230 {
5231 if (! t && o->arg == o->notarg)
5232 as_bad (_("option `%s' may not be negated"), s);
5233 *input_line_pointer = c;
5234 *o->pvar = t ? o->arg : o->notarg;
5235 }
5236 else
5237 *input_line_pointer = c;
5238 break;
5239 }
5240 }
5241 if (i >= OPTCOUNT)
5242 {
5243 as_bad (_("option `%s' not recognized"), s);
5244 *input_line_pointer = c;
5245 }
5246 }
5247 while (*input_line_pointer++ == ',');
5248
5249 /* Move back to terminating character. */
5250 --input_line_pointer;
5251 demand_empty_rest_of_line ();
5252}
5253
5254/* Skip ahead to a comma. This is used for OPT options which we do
5255 not suppor tand which take arguments. */
5256
5257static void
5258skip_to_comma (arg, on)
36823076
AS		 5259 int arg ATTRIBUTE_UNUSED;
5260 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5261{
5262 while (*input_line_pointer != ','
5263 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5264 ++input_line_pointer;
5265}
5266
5267/* Handle the OPT NEST=depth option. */
5268
5269static void
5270opt_nest (arg, on)
36823076
AS		 5271 int arg ATTRIBUTE_UNUSED;
5272 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5273{
5274 if (*input_line_pointer != '=')
5275 {
5276 as_bad (_("bad format of OPT NEST=depth"));
5277 return;
5278 }
5279
5280 ++input_line_pointer;
5281 max_macro_nest = get_absolute_expression ();
5282}
5283
5284/* Handle the OPT P=chip option. */
5285
5286static void
5287opt_chip (arg, on)
36823076
AS		 5288 int arg ATTRIBUTE_UNUSED;
5289 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5290{
5291 if (*input_line_pointer != '=')
5292 {
5293 /* This is just OPT P, which we do not support. */
5294 return;
5295 }
5296
5297 ++input_line_pointer;
5298 mri_chip ();
5299}
5300
5301/* Handle the OPT S option. */
5302
5303static void
5304opt_list (arg, on)
36823076 5305 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5306 int on;
5307{
5308 listing_list (on);
5309}
5310
5311/* Handle the OPT T option. */
5312
5313static void
5314opt_list_symbols (arg, on)
36823076 5315 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5316 int on;
5317{
5318 if (on)
5319 listing |= LISTING_SYMBOLS;
5320 else
8a104df9 5321 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5322}
5323
5324/* Handle the MRI REG pseudo-op. */
5325
5326static void
5327s_reg (ignore)
36823076 5328 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5329{
5330 char *s;
5331 int c;
5332 struct m68k_op rop;
5333 int mask;
5334 char *stop = NULL;
5335 char stopc;
5336
5337 if (line_label == NULL)
5338 {
5339 as_bad (_("missing label"));
5340 ignore_rest_of_line ();
5341 return;
5342 }
5343
5344 if (flag_mri)
5345 stop = mri_comment_field (&stopc);
5346
5347 SKIP_WHITESPACE ();
5348
5349 s = input_line_pointer;
3882b010 5350 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5351#ifdef REGISTER_PREFIX
5352 || *input_line_pointer == REGISTER_PREFIX
5353#endif
5354 || *input_line_pointer == '/'
5355 || *input_line_pointer == '-')
5356 ++input_line_pointer;
5357 c = *input_line_pointer;
5358 *input_line_pointer = '\0';
5359
5360 if (m68k_ip_op (s, &rop) != 0)
5361 {
5362 if (rop.error == NULL)
5363 as_bad (_("bad register list"));
5364 else
5365 as_bad (_("bad register list: %s"), rop.error);
5366 *input_line_pointer = c;
5367 ignore_rest_of_line ();
5368 return;
5369 }
5370
5371 *input_line_pointer = c;
5372
5373 if (rop.mode == REGLST)
5374 mask = rop.mask;
5375 else if (rop.mode == DREG)
5376 mask = 1 << (rop.reg - DATA0);
5377 else if (rop.mode == AREG)
5378 mask = 1 << (rop.reg - ADDR0 + 8);
5379 else if (rop.mode == FPREG)
5380 mask = 1 << (rop.reg - FP0 + 16);
5381 else if (rop.mode == CONTROL
5382 && rop.reg == FPI)
5383 mask = 1 << 24;
5384 else if (rop.mode == CONTROL
5385 && rop.reg == FPS)
5386 mask = 1 << 25;
5387 else if (rop.mode == CONTROL
5388 && rop.reg == FPC)
5389 mask = 1 << 26;
5390 else
5391 {
5392 as_bad (_("bad register list"));
5393 ignore_rest_of_line ();
5394 return;
5395 }
5396
5397 S_SET_SEGMENT (line_label, reg_section);
5398 S_SET_VALUE (line_label, ~mask);
49309057 5399 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5400
5401 if (flag_mri)
5402 mri_comment_end (stop, stopc);
5403
5404 demand_empty_rest_of_line ();
5405}
5406
5407/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5408
5409struct save_opts
5410{
5411 struct save_opts *next;
5412 int abspcadd;
5413 int symbols_case_sensitive;
5414 int keep_locals;
5415 int short_refs;
5416 int architecture;
5417 int quick;
5418 int rel32;
5419 int listing;
5420 int no_warnings;
5421 /* FIXME: We don't save OPT S. */
5422};
5423
5424/* This variable holds the stack of saved options. */
5425
5426static struct save_opts *save_stack;
5427
5428/* The MRI SAVE pseudo-op. */
5429
5430static void
5431s_save (ignore)
36823076 5432 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5433{
5434 struct save_opts *s;
5435
5436 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5437 s->abspcadd = m68k_abspcadd;
5438 s->symbols_case_sensitive = symbols_case_sensitive;
5439 s->keep_locals = flag_keep_locals;
5440 s->short_refs = flag_short_refs;
5441 s->architecture = current_architecture;
5442 s->quick = m68k_quick;
5443 s->rel32 = m68k_rel32;
5444 s->listing = listing;
5445 s->no_warnings = flag_no_warnings;
5446
5447 s->next = save_stack;
5448 save_stack = s;
5449
5450 demand_empty_rest_of_line ();
5451}
5452
5453/* The MRI RESTORE pseudo-op. */
5454
5455static void
5456s_restore (ignore)
36823076 5457 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5458{
5459 struct save_opts *s;
5460
5461 if (save_stack == NULL)
5462 {
5463 as_bad (_("restore without save"));
5464 ignore_rest_of_line ();
5465 return;
5466 }
5467
5468 s = save_stack;
5469 save_stack = s->next;
5470
5471 m68k_abspcadd = s->abspcadd;
5472 symbols_case_sensitive = s->symbols_case_sensitive;
5473 flag_keep_locals = s->keep_locals;
5474 flag_short_refs = s->short_refs;
5475 current_architecture = s->architecture;
5476 m68k_quick = s->quick;
5477 m68k_rel32 = s->rel32;
5478 listing = s->listing;
5479 flag_no_warnings = s->no_warnings;
5480
5481 free (s);
5482
5483 demand_empty_rest_of_line ();
5484}
5485
5486/* Types of MRI structured control directives. */
5487
5488enum mri_control_type
5489{
5490 mri_for,
5491 mri_if,
5492 mri_repeat,
5493 mri_while
5494};
5495
5496/* This structure is used to stack the MRI structured control
5497 directives. */
5498
5499struct mri_control_info
5500{
5501 /* The directive within which this one is enclosed. */
5502 struct mri_control_info *outer;
5503
5504 /* The type of directive. */
5505 enum mri_control_type type;
5506
5507 /* Whether an ELSE has been in an IF. */
5508 int else_seen;
5509
5510 /* The add or sub statement at the end of a FOR. */
5511 char *incr;
5512
5513 /* The label of the top of a FOR or REPEAT loop. */
5514 char *top;
5515
5516 /* The label to jump to for the next iteration, or the else
5517 expression of a conditional. */
5518 char *next;
5519
5520 /* The label to jump to to break out of the loop, or the label past
5521 the end of a conditional. */
5522 char *bottom;
5523};
5524
5525/* The stack of MRI structured control directives. */
5526
5527static struct mri_control_info *mri_control_stack;
5528
5529/* The current MRI structured control directive index number, used to
5530 generate label names. */
5531
5532static int mri_control_index;
5533
5534/* Some function prototypes. */
5535
5536static void mri_assemble PARAMS ((char *));
5537static char *mri_control_label PARAMS ((void));
5538static struct mri_control_info *push_mri_control
5539 PARAMS ((enum mri_control_type));
5540static void pop_mri_control PARAMS ((void));
5541static int parse_mri_condition PARAMS ((int *));
5542static int parse_mri_control_operand
5543 PARAMS ((int *, char **, char **, char **, char **));
5544static int swap_mri_condition PARAMS ((int));
5545static int reverse_mri_condition PARAMS ((int));
5546static void build_mri_control_operand
5547 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5548 const char *, int));
5549static void parse_mri_control_expression
5550 PARAMS ((char *, int, const char *, const char *, int));
5551
5552/* Assemble an instruction for an MRI structured control directive. */
5553
5554static void
5555mri_assemble (str)
5556 char *str;
5557{
5558 char *s;
5559
5560 /* md_assemble expects the opcode to be in lower case. */
5561 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5562 *s = TOLOWER (*s);
252b5132
RH		 5563
5564 md_assemble (str);
5565}
5566
5567/* Generate a new MRI label structured control directive label name. */
5568
5569static char *
5570mri_control_label ()
5571{
5572 char *n;
5573
5574 n = (char *) xmalloc (20);
5575 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5576 ++mri_control_index;
5577 return n;
5578}
5579
5580/* Create a new MRI structured control directive. */
5581
5582static struct mri_control_info *
5583push_mri_control (type)
5584 enum mri_control_type type;
5585{
5586 struct mri_control_info *n;
5587
5588 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5589
5590 n->type = type;
5591 n->else_seen = 0;
5592 if (type == mri_if || type == mri_while)
5593 n->top = NULL;
5594 else
5595 n->top = mri_control_label ();
5596 n->next = mri_control_label ();
5597 n->bottom = mri_control_label ();
5598
5599 n->outer = mri_control_stack;
5600 mri_control_stack = n;
5601
5602 return n;
5603}
5604
5605/* Pop off the stack of MRI structured control directives. */
5606
5607static void
5608pop_mri_control ()
5609{
5610 struct mri_control_info *n;
5611
5612 n = mri_control_stack;
5613 mri_control_stack = n->outer;
5614 if (n->top != NULL)
5615 free (n->top);
5616 free (n->next);
5617 free (n->bottom);
5618 free (n);
5619}
5620
5621/* Recognize a condition code in an MRI structured control expression. */
5622
5623static int
5624parse_mri_condition (pcc)
5625 int *pcc;
5626{
5627 char c1, c2;
5628
5629 know (*input_line_pointer == '<');
5630
5631 ++input_line_pointer;
5632 c1 = *input_line_pointer++;
5633 c2 = *input_line_pointer++;
5634
5635 if (*input_line_pointer != '>')
5636 {
5637 as_bad (_("syntax error in structured control directive"));
5638 return 0;
5639 }
5640
5641 ++input_line_pointer;
5642 SKIP_WHITESPACE ();
5643
3882b010
L		 5644 c1 = TOLOWER (c1);
5645 c2 = TOLOWER (c2);
252b5132
RH		 5646
5647 *pcc = (c1 << 8) | c2;
5648
5649 return 1;
5650}
5651
5652/* Parse a single operand in an MRI structured control expression. */
5653
5654static int
5655parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5656 int *pcc;
5657 char **leftstart;
5658 char **leftstop;
5659 char **rightstart;
5660 char **rightstop;
5661{
5662 char *s;
5663
5664 SKIP_WHITESPACE ();
5665
5666 *pcc = -1;
5667 *leftstart = NULL;
5668 *leftstop = NULL;
5669 *rightstart = NULL;
5670 *rightstop = NULL;
5671
5672 if (*input_line_pointer == '<')
5673 {
5674 /* It's just a condition code. */
5675 return parse_mri_condition (pcc);
5676 }
5677
5678 /* Look ahead for the condition code. */
5679 for (s = input_line_pointer; *s != '\0'; ++s)
5680 {
5681 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5682 break;
5683 }
5684 if (*s == '\0')
5685 {
5686 as_bad (_("missing condition code in structured control directive"));
5687 return 0;
5688 }
5689
5690 *leftstart = input_line_pointer;
5691 *leftstop = s;
5692 if (*leftstop > *leftstart
5693 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5694 --*leftstop;
5695
5696 input_line_pointer = s;
5697 if (! parse_mri_condition (pcc))
5698 return 0;
5699
5700 /* Look ahead for AND or OR or end of line. */
5701 for (s = input_line_pointer; *s != '\0'; ++s)
5702 {
e1f44d10
NC		 5703 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5704 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5705 ^^^ ^^ */
8a104df9
KH		 5706 if ((s == input_line_pointer
5707 || *(s-1) == ' '
5708 || *(s-1) == '\t')
5709 && ((strncasecmp (s, "AND", 3) == 0
5710 && (s[3] == '.' || ! is_part_of_name (s[3])))
5711 || (strncasecmp (s, "OR", 2) == 0
5712 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5713 break;
252b5132
RH		 5714 }
5715
5716 *rightstart = input_line_pointer;
5717 *rightstop = s;
5718 if (*rightstop > *rightstart
5719 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5720 --*rightstop;
5721
5722 input_line_pointer = s;
5723
5724 return 1;
5725}
5726
5727#define MCC(b1, b2) (((b1) << 8) | (b2))
5728
5729/* Swap the sense of a condition. This changes the condition so that
5730 it generates the same result when the operands are swapped. */
5731
5732static int
5733swap_mri_condition (cc)
5734 int cc;
5735{
5736 switch (cc)
5737 {
5738 case MCC ('h', 'i'): return MCC ('c', 's');
5739 case MCC ('l', 's'): return MCC ('c', 'c');
e1f44d10
NC		 5740 /* <HS> is an alias for <CC> */
5741 case MCC ('h', 's'):
252b5132 5742 case MCC ('c', 'c'): return MCC ('l', 's');
e1f44d10
NC		 5743 /* <LO> is an alias for <CS> */
5744 case MCC ('l', 'o'):
252b5132
RH		 5745 case MCC ('c', 's'): return MCC ('h', 'i');
5746 case MCC ('p', 'l'): return MCC ('m', 'i');
5747 case MCC ('m', 'i'): return MCC ('p', 'l');
5748 case MCC ('g', 'e'): return MCC ('l', 'e');
5749 case MCC ('l', 't'): return MCC ('g', 't');
5750 case MCC ('g', 't'): return MCC ('l', 't');
5751 case MCC ('l', 'e'): return MCC ('g', 'e');
e1f44d10
NC		 5752 /* issue a warning for conditions we can not swap */
5753 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5754 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5755 case MCC ('v', 'c'):
5756 case MCC ('v', 's'):
5757 default :
5758 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5759 (char) (cc >> 8), (char) (cc));
5760 break;
252b5132
RH		 5761 }
5762 return cc;
5763}
5764
5765/* Reverse the sense of a condition. */
5766
5767static int
5768reverse_mri_condition (cc)
5769 int cc;
5770{
5771 switch (cc)
5772 {
5773 case MCC ('h', 'i'): return MCC ('l', 's');
5774 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5775 /* <HS> is an alias for <CC> */
5776 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5777 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5778 /* <LO> is an alias for <CS> */
5779 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5780 case MCC ('c', 's'): return MCC ('c', 'c');
5781 case MCC ('n', 'e'): return MCC ('e', 'q');
5782 case MCC ('e', 'q'): return MCC ('n', 'e');
5783 case MCC ('v', 'c'): return MCC ('v', 's');
5784 case MCC ('v', 's'): return MCC ('v', 'c');
5785 case MCC ('p', 'l'): return MCC ('m', 'i');
5786 case MCC ('m', 'i'): return MCC ('p', 'l');
5787 case MCC ('g', 'e'): return MCC ('l', 't');
5788 case MCC ('l', 't'): return MCC ('g', 'e');
5789 case MCC ('g', 't'): return MCC ('l', 'e');
5790 case MCC ('l', 'e'): return MCC ('g', 't');
5791 }
5792 return cc;
5793}
5794
5795/* Build an MRI structured control expression. This generates test
5796 and branch instructions. It goes to TRUELAB if the condition is
5797 true, and to FALSELAB if the condition is false. Exactly one of
5798 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5799 is the size qualifier for the expression. EXTENT is the size to
5800 use for the branch. */
5801
5802static void
5803build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5804 rightstop, truelab, falselab, extent)
5805 int qual;
5806 int cc;
5807 char *leftstart;
5808 char *leftstop;
5809 char *rightstart;
5810 char *rightstop;
5811 const char *truelab;
5812 const char *falselab;
5813 int extent;
5814{
5815 char *buf;
5816 char *s;
5817
5818 if (leftstart != NULL)
5819 {
5820 struct m68k_op leftop, rightop;
5821 char c;
5822
5823 /* Swap the compare operands, if necessary, to produce a legal
5824 m68k compare instruction. Comparing a register operand with
5825 a non-register operand requires the register to be on the
5826 right (cmp, cmpa). Comparing an immediate value with
5827 anything requires the immediate value to be on the left
5828 (cmpi). */
5829
5830 c = *leftstop;
5831 *leftstop = '\0';
5832 (void) m68k_ip_op (leftstart, &leftop);
5833 *leftstop = c;
5834
5835 c = *rightstop;
5836 *rightstop = '\0';
5837 (void) m68k_ip_op (rightstart, &rightop);
5838 *rightstop = c;
5839
5840 if (rightop.mode == IMMED
5841 || ((leftop.mode == DREG || leftop.mode == AREG)
5842 && (rightop.mode != DREG && rightop.mode != AREG)))
5843 {
5844 char *temp;
5845
e1f44d10
NC		 5846 /* Correct conditional handling:
5847 if #1 <lt> d0 then ;means if (1 < d0)
5848 ...
5849 endi
5850
5851 should assemble to:
5852
5853 cmp #1,d0 if we do *not* swap the operands
5854 bgt true we need the swapped condition!
5855 ble false
5856 true:
5857 ...
5858 false:
5859 */
252b5132
RH		 5860 temp = leftstart;
5861 leftstart = rightstart;
5862 rightstart = temp;
5863 temp = leftstop;
5864 leftstop = rightstop;
5865 rightstop = temp;
8a104df9
KH		 5866 }
5867 else
5868 {
e1f44d10 5869 cc = swap_mri_condition (cc);
252b5132
RH		 5870 }
5871 }
5872
5873 if (truelab == NULL)
5874 {
5875 cc = reverse_mri_condition (cc);
5876 truelab = falselab;
5877 }
92774660 5878
252b5132
RH		 5879 if (leftstart != NULL)
5880 {
5881 buf = (char *) xmalloc (20
5882 + (leftstop - leftstart)
5883 + (rightstop - rightstart));
5884 s = buf;
5885 *s++ = 'c';
5886 *s++ = 'm';
5887 *s++ = 'p';
5888 if (qual != '\0')
3882b010 5889 *s++ = TOLOWER (qual);
252b5132
RH		 5890 *s++ = ' ';
5891 memcpy (s, leftstart, leftstop - leftstart);
5892 s += leftstop - leftstart;
5893 *s++ = ',';
5894 memcpy (s, rightstart, rightstop - rightstart);
5895 s += rightstop - rightstart;
5896 *s = '\0';
5897 mri_assemble (buf);
5898 free (buf);
5899 }
92774660 5900
252b5132
RH		 5901 buf = (char *) xmalloc (20 + strlen (truelab));
5902 s = buf;
5903 *s++ = 'b';
5904 *s++ = cc >> 8;
5905 *s++ = cc & 0xff;
5906 if (extent != '\0')
3882b010 5907 *s++ = TOLOWER (extent);
252b5132
RH		 5908 *s++ = ' ';
5909 strcpy (s, truelab);
5910 mri_assemble (buf);
5911 free (buf);
5912}
5913
5914/* Parse an MRI structured control expression. This generates test
5915 and branch instructions. STOP is where the expression ends. It
5916 goes to TRUELAB if the condition is true, and to FALSELAB if the
5917 condition is false. Exactly one of TRUELAB and FALSELAB will be
5918 NULL, meaning to fall through. QUAL is the size qualifier for the
5919 expression. EXTENT is the size to use for the branch. */
5920
5921static void
5922parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5923 char *stop;
5924 int qual;
5925 const char *truelab;
5926 const char *falselab;
5927 int extent;
5928{
5929 int c;
5930 int cc;
5931 char *leftstart;
5932 char *leftstop;
5933 char *rightstart;
5934 char *rightstop;
5935
5936 c = *stop;
5937 *stop = '\0';
5938
5939 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5940 &rightstart, &rightstop))
5941 {
5942 *stop = c;
5943 return;
5944 }
5945
5946 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5947 {
5948 const char *flab;
5949
5950 if (falselab != NULL)
5951 flab = falselab;
5952 else
5953 flab = mri_control_label ();
5954
5955 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5956 rightstop, (const char *) NULL, flab, extent);
5957
5958 input_line_pointer += 3;
5959 if (*input_line_pointer != '.'
5960 || input_line_pointer[1] == '\0')
5961 qual = '\0';
5962 else
5963 {
5964 qual = input_line_pointer[1];
5965 input_line_pointer += 2;
5966 }
5967
5968 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5969 &rightstart, &rightstop))
5970 {
5971 *stop = c;
5972 return;
5973 }
5974
5975 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5976 rightstop, truelab, falselab, extent);
5977
5978 if (falselab == NULL)
5979 colon (flab);
5980 }
5981 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5982 {
5983 const char *tlab;
5984
5985 if (truelab != NULL)
5986 tlab = truelab;
5987 else
5988 tlab = mri_control_label ();
5989
5990 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5991 rightstop, tlab, (const char *) NULL, extent);
5992
5993 input_line_pointer += 2;
5994 if (*input_line_pointer != '.'
5995 || input_line_pointer[1] == '\0')
5996 qual = '\0';
5997 else
5998 {
5999 qual = input_line_pointer[1];
6000 input_line_pointer += 2;
6001 }
6002
6003 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6004 &rightstart, &rightstop))
6005 {
6006 *stop = c;
6007 return;
6008 }
6009
6010 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6011 rightstop, truelab, falselab, extent);
6012
6013 if (truelab == NULL)
6014 colon (tlab);
6015 }
6016 else
6017 {
6018 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6019 rightstop, truelab, falselab, extent);
6020 }
6021
6022 *stop = c;
6023 if (input_line_pointer != stop)
6024 as_bad (_("syntax error in structured control directive"));
6025}
6026
6027/* Handle the MRI IF pseudo-op. This may be a structured control
6028 directive, or it may be a regular assembler conditional, depending
6029 on its operands. */
6030
6031static void
6032s_mri_if (qual)
6033 int qual;
6034{
6035 char *s;
6036 int c;
6037 struct mri_control_info *n;
6038
6039 /* A structured control directive must end with THEN with an
6040 optional qualifier. */
6041 s = input_line_pointer;
e1f44d10
NC		 6042 /* We only accept '*' as introduction of comments if preceded by white space
6043 or at first column of a line (I think this can't actually happen here?)
6044 This is important when assembling:
6045 if d0 <ne> 12(a0,d0*2) then
6046 if d0 <ne> #CONST*20 then */
6047 while ( ! ( is_end_of_line[(unsigned char) *s]
6048 || ( flag_mri
6049 && *s == '*'
6050 && ( s == input_line_pointer
6051 || *(s-1) == ' '
6052 || *(s-1) == '\t'))))
252b5132
RH		 6053 ++s;
6054 --s;
6055 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6056 --s;
6057
6058 if (s - input_line_pointer > 1
6059 && s[-1] == '.')
6060 s -= 2;
6061
6062 if (s - input_line_pointer < 3
6063 || strncasecmp (s - 3, "THEN", 4) != 0)
6064 {
6065 if (qual != '\0')
6066 {
6067 as_bad (_("missing then"));
6068 ignore_rest_of_line ();
6069 return;
6070 }
6071
6072 /* It's a conditional. */
6073 s_if (O_ne);
6074 return;
6075 }
6076
6077 /* Since this might be a conditional if, this pseudo-op will be
6078 called even if we are supported to be ignoring input. Double
6079 check now. Clobber *input_line_pointer so that ignore_input
6080 thinks that this is not a special pseudo-op. */
6081 c = *input_line_pointer;
6082 *input_line_pointer = 0;
6083 if (ignore_input ())
6084 {
6085 *input_line_pointer = c;
6086 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6087 ++input_line_pointer;
6088 demand_empty_rest_of_line ();
6089 return;
6090 }
6091 *input_line_pointer = c;
6092
6093 n = push_mri_control (mri_if);
6094
6095 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6096 n->next, s[1] == '.' ? s[2] : '\0');
6097
6098 if (s[1] == '.')
6099 input_line_pointer = s + 3;
6100 else
6101 input_line_pointer = s + 1;
6102
6103 if (flag_mri)
6104 {
6105 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6106 ++input_line_pointer;
6107 }
6108
6109 demand_empty_rest_of_line ();
6110}
6111
6112/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6113 structured IF, associate the ELSE with the IF. Otherwise, assume
6114 it is a conditional else. */
6115
6116static void
6117s_mri_else (qual)
6118 int qual;
6119{
6120 int c;
6121 char *buf;
6122 char q[2];
6123
6124 if (qual == '\0'
6125 && (mri_control_stack == NULL
6126 || mri_control_stack->type != mri_if
6127 || mri_control_stack->else_seen))
6128 {
6129 s_else (0);
6130 return;
6131 }
6132
6133 c = *input_line_pointer;
6134 *input_line_pointer = 0;
6135 if (ignore_input ())
6136 {
6137 *input_line_pointer = c;
6138 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6139 ++input_line_pointer;
6140 demand_empty_rest_of_line ();
6141 return;
6142 }
6143 *input_line_pointer = c;
6144
6145 if (mri_control_stack == NULL
6146 || mri_control_stack->type != mri_if
6147 || mri_control_stack->else_seen)
6148 {
6149 as_bad (_("else without matching if"));
6150 ignore_rest_of_line ();
6151 return;
6152 }
6153
6154 mri_control_stack->else_seen = 1;
6155
6156 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6157 q[0] = TOLOWER (qual);
252b5132
RH		 6158 q[1] = '\0';
6159 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6160 mri_assemble (buf);
6161 free (buf);
6162
6163 colon (mri_control_stack->next);
6164
6165 if (flag_mri)
6166 {
6167 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6168 ++input_line_pointer;
6169 }
6170
6171 demand_empty_rest_of_line ();
6172}
6173
6174/* Handle the MRI ENDI pseudo-op. */
6175
6176static void
6177s_mri_endi (ignore)
36823076 6178 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6179{
6180 if (mri_control_stack == NULL
6181 || mri_control_stack->type != mri_if)
6182 {
6183 as_bad (_("endi without matching if"));
6184 ignore_rest_of_line ();
6185 return;
6186 }
6187
6188 /* ignore_input will not return true for ENDI, so we don't need to
6189 worry about checking it again here. */
6190
6191 if (! mri_control_stack->else_seen)
6192 colon (mri_control_stack->next);
6193 colon (mri_control_stack->bottom);
6194
6195 pop_mri_control ();
6196
6197 if (flag_mri)
6198 {
6199 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6200 ++input_line_pointer;
6201 }
6202
6203 demand_empty_rest_of_line ();
6204}
6205
6206/* Handle the MRI BREAK pseudo-op. */
6207
6208static void
6209s_mri_break (extent)
6210 int extent;
6211{
6212 struct mri_control_info *n;
6213 char *buf;
6214 char ex[2];
6215
6216 n = mri_control_stack;
6217 while (n != NULL
6218 && n->type != mri_for
6219 && n->type != mri_repeat
6220 && n->type != mri_while)
6221 n = n->outer;
6222 if (n == NULL)
6223 {
6224 as_bad (_("break outside of structured loop"));
6225 ignore_rest_of_line ();
6226 return;
6227 }
6228
6229 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6230 ex[0] = TOLOWER (extent);
252b5132
RH		 6231 ex[1] = '\0';
6232 sprintf (buf, "bra%s %s", ex, n->bottom);
6233 mri_assemble (buf);
6234 free (buf);
6235
6236 if (flag_mri)
6237 {
6238 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6239 ++input_line_pointer;
6240 }
6241
6242 demand_empty_rest_of_line ();
6243}
6244
6245/* Handle the MRI NEXT pseudo-op. */
6246
6247static void
6248s_mri_next (extent)
6249 int extent;
6250{
6251 struct mri_control_info *n;
6252 char *buf;
6253 char ex[2];
6254
6255 n = mri_control_stack;
6256 while (n != NULL
6257 && n->type != mri_for
6258 && n->type != mri_repeat
6259 && n->type != mri_while)
6260 n = n->outer;
6261 if (n == NULL)
6262 {
6263 as_bad (_("next outside of structured loop"));
6264 ignore_rest_of_line ();
6265 return;
6266 }
6267
6268 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6269 ex[0] = TOLOWER (extent);
252b5132
RH		 6270 ex[1] = '\0';
6271 sprintf (buf, "bra%s %s", ex, n->next);
6272 mri_assemble (buf);
6273 free (buf);
6274
6275 if (flag_mri)
6276 {
6277 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6278 ++input_line_pointer;
6279 }
6280
6281 demand_empty_rest_of_line ();
6282}
6283
6284/* Handle the MRI FOR pseudo-op. */
6285
6286static void
6287s_mri_for (qual)
6288 int qual;
6289{
6290 const char *varstart, *varstop;
6291 const char *initstart, *initstop;
6292 const char *endstart, *endstop;
6293 const char *bystart, *bystop;
6294 int up;
6295 int by;
6296 int extent;
6297 struct mri_control_info *n;
6298 char *buf;
6299 char *s;
6300 char ex[2];
6301
6302 /* The syntax is
6303 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6304 */
6305
6306 SKIP_WHITESPACE ();
6307 varstart = input_line_pointer;
6308
6309 /* Look for the '='. */
6310 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6311 && *input_line_pointer != '=')
6312 ++input_line_pointer;
6313 if (*input_line_pointer != '=')
6314 {
6315 as_bad (_("missing ="));
6316 ignore_rest_of_line ();
6317 return;
6318 }
6319
6320 varstop = input_line_pointer;
6321 if (varstop > varstart
6322 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6323 --varstop;
6324
6325 ++input_line_pointer;
6326
6327 initstart = input_line_pointer;
6328
6329 /* Look for TO or DOWNTO. */
6330 up = 1;
6331 initstop = NULL;
6332 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6333 {
6334 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6335 && ! is_part_of_name (input_line_pointer[2]))
6336 {
6337 initstop = input_line_pointer;
6338 input_line_pointer += 2;
6339 break;
6340 }
6341 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6342 && ! is_part_of_name (input_line_pointer[6]))
6343 {
6344 initstop = input_line_pointer;
6345 up = 0;
6346 input_line_pointer += 6;
6347 break;
6348 }
6349 ++input_line_pointer;
6350 }
6351 if (initstop == NULL)
6352 {
6353 as_bad (_("missing to or downto"));
6354 ignore_rest_of_line ();
6355 return;
6356 }
6357 if (initstop > initstart
6358 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6359 --initstop;
6360
6361 SKIP_WHITESPACE ();
6362 endstart = input_line_pointer;
6363
6364 /* Look for BY or DO. */
6365 by = 0;
6366 endstop = NULL;
6367 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6368 {
6369 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6370 && ! is_part_of_name (input_line_pointer[2]))
6371 {
6372 endstop = input_line_pointer;
6373 by = 1;
6374 input_line_pointer += 2;
6375 break;
6376 }
6377 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6378 && (input_line_pointer[2] == '.'
6379 || ! is_part_of_name (input_line_pointer[2])))
6380 {
6381 endstop = input_line_pointer;
6382 input_line_pointer += 2;
6383 break;
6384 }
6385 ++input_line_pointer;
6386 }
6387 if (endstop == NULL)
6388 {
6389 as_bad (_("missing do"));
6390 ignore_rest_of_line ();
6391 return;
6392 }
6393 if (endstop > endstart
6394 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6395 --endstop;
6396
6397 if (! by)
6398 {
6399 bystart = "#1";
6400 bystop = bystart + 2;
6401 }
6402 else
6403 {
6404 SKIP_WHITESPACE ();
6405 bystart = input_line_pointer;
6406
6407 /* Look for DO. */
6408 bystop = NULL;
6409 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6410 {
6411 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6412 && (input_line_pointer[2] == '.'
6413 || ! is_part_of_name (input_line_pointer[2])))
6414 {
6415 bystop = input_line_pointer;
6416 input_line_pointer += 2;
6417 break;
6418 }
6419 ++input_line_pointer;
6420 }
6421 if (bystop == NULL)
6422 {
6423 as_bad (_("missing do"));
6424 ignore_rest_of_line ();
6425 return;
6426 }
6427 if (bystop > bystart
6428 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6429 --bystop;
6430 }
6431
6432 if (*input_line_pointer != '.')
6433 extent = '\0';
6434 else
6435 {
6436 extent = input_line_pointer[1];
6437 input_line_pointer += 2;
6438 }
6439
6440 /* We have fully parsed the FOR operands. Now build the loop. */
6441
6442 n = push_mri_control (mri_for);
6443
6444 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6445
6446 /* move init,var */
6447 s = buf;
6448 *s++ = 'm';
6449 *s++ = 'o';
6450 *s++ = 'v';
6451 *s++ = 'e';
6452 if (qual != '\0')
3882b010 6453 *s++ = TOLOWER (qual);
252b5132
RH		 6454 *s++ = ' ';
6455 memcpy (s, initstart, initstop - initstart);
6456 s += initstop - initstart;
6457 *s++ = ',';
6458 memcpy (s, varstart, varstop - varstart);
6459 s += varstop - varstart;
6460 *s = '\0';
6461 mri_assemble (buf);
6462
6463 colon (n->top);
6464
6465 /* cmp end,var */
6466 s = buf;
6467 *s++ = 'c';
6468 *s++ = 'm';
6469 *s++ = 'p';
6470 if (qual != '\0')
3882b010 6471 *s++ = TOLOWER (qual);
252b5132
RH		 6472 *s++ = ' ';
6473 memcpy (s, endstart, endstop - endstart);
6474 s += endstop - endstart;
6475 *s++ = ',';
6476 memcpy (s, varstart, varstop - varstart);
6477 s += varstop - varstart;
6478 *s = '\0';
6479 mri_assemble (buf);
6480
6481 /* bcc bottom */
3882b010 6482 ex[0] = TOLOWER (extent);
252b5132
RH		 6483 ex[1] = '\0';
6484 if (up)
6485 sprintf (buf, "blt%s %s", ex, n->bottom);
6486 else
6487 sprintf (buf, "bgt%s %s", ex, n->bottom);
6488 mri_assemble (buf);
6489
6490 /* Put together the add or sub instruction used by ENDF. */
6491 s = buf;
6492 if (up)
6493 strcpy (s, "add");
6494 else
6495 strcpy (s, "sub");
6496 s += 3;
6497 if (qual != '\0')
3882b010 6498 *s++ = TOLOWER (qual);
252b5132
RH		 6499 *s++ = ' ';
6500 memcpy (s, bystart, bystop - bystart);
6501 s += bystop - bystart;
6502 *s++ = ',';
6503 memcpy (s, varstart, varstop - varstart);
6504 s += varstop - varstart;
6505 *s = '\0';
6506 n->incr = buf;
6507
6508 if (flag_mri)
6509 {
6510 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6511 ++input_line_pointer;
6512 }
6513
6514 demand_empty_rest_of_line ();
6515}
6516
6517/* Handle the MRI ENDF pseudo-op. */
6518
6519static void
6520s_mri_endf (ignore)
36823076 6521 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6522{
6523 if (mri_control_stack == NULL
6524 || mri_control_stack->type != mri_for)
6525 {
6526 as_bad (_("endf without for"));
6527 ignore_rest_of_line ();
6528 return;
6529 }
6530
6531 colon (mri_control_stack->next);
6532
6533 mri_assemble (mri_control_stack->incr);
6534
6535 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6536 mri_assemble (mri_control_stack->incr);
6537
6538 free (mri_control_stack->incr);
6539
6540 colon (mri_control_stack->bottom);
6541
6542 pop_mri_control ();
6543
6544 if (flag_mri)
6545 {
6546 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6547 ++input_line_pointer;
6548 }
6549
6550 demand_empty_rest_of_line ();
6551}
6552
6553/* Handle the MRI REPEAT pseudo-op. */
6554
6555static void
6556s_mri_repeat (ignore)
36823076 6557 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6558{
6559 struct mri_control_info *n;
6560
6561 n = push_mri_control (mri_repeat);
6562 colon (n->top);
6563 if (flag_mri)
6564 {
6565 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6566 ++input_line_pointer;
6567 }
6568 demand_empty_rest_of_line ();
6569}
6570
6571/* Handle the MRI UNTIL pseudo-op. */
6572
6573static void
6574s_mri_until (qual)
6575 int qual;
6576{
6577 char *s;
6578
6579 if (mri_control_stack == NULL
6580 || mri_control_stack->type != mri_repeat)
6581 {
6582 as_bad (_("until without repeat"));
6583 ignore_rest_of_line ();
6584 return;
6585 }
6586
6587 colon (mri_control_stack->next);
6588
6589 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6590 ;
6591
6592 parse_mri_control_expression (s, qual, (const char *) NULL,
6593 mri_control_stack->top, '\0');
6594
6595 colon (mri_control_stack->bottom);
6596
6597 input_line_pointer = s;
6598
6599 pop_mri_control ();
6600
6601 if (flag_mri)
6602 {
6603 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6604 ++input_line_pointer;
6605 }
6606
6607 demand_empty_rest_of_line ();
6608}
6609
6610/* Handle the MRI WHILE pseudo-op. */
6611
6612static void
6613s_mri_while (qual)
6614 int qual;
6615{
6616 char *s;
6617
6618 struct mri_control_info *n;
6619
6620 s = input_line_pointer;
e1f44d10
NC		 6621 /* We only accept '*' as introduction of comments if preceded by white space
6622 or at first column of a line (I think this can't actually happen here?)
6623 This is important when assembling:
6624 while d0 <ne> 12(a0,d0*2) do
6625 while d0 <ne> #CONST*20 do */
8a104df9
KH		 6626 while (! (is_end_of_line[(unsigned char) *s]
6627 || (flag_mri
6628 && *s == '*'
6629 && (s == input_line_pointer
6630 || *(s-1) == ' '
6631 || *(s-1) == '\t'))))
252b5132
RH		 6632 s++;
6633 --s;
6634 while (*s == ' ' || *s == '\t')
6635 --s;
6636 if (s - input_line_pointer > 1
6637 && s[-1] == '.')
6638 s -= 2;
6639 if (s - input_line_pointer < 2
6640 || strncasecmp (s - 1, "DO", 2) != 0)
6641 {
6642 as_bad (_("missing do"));
6643 ignore_rest_of_line ();
6644 return;
6645 }
6646
6647 n = push_mri_control (mri_while);
6648
6649 colon (n->next);
6650
6651 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6652 s[1] == '.' ? s[2] : '\0');
6653
6654 input_line_pointer = s + 1;
6655 if (*input_line_pointer == '.')
6656 input_line_pointer += 2;
6657
6658 if (flag_mri)
6659 {
6660 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6661 ++input_line_pointer;
6662 }
6663
6664 demand_empty_rest_of_line ();
6665}
6666
6667/* Handle the MRI ENDW pseudo-op. */
6668
6669static void
6670s_mri_endw (ignore)
36823076 6671 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6672{
6673 char *buf;
6674
6675 if (mri_control_stack == NULL
6676 || mri_control_stack->type != mri_while)
6677 {
6678 as_bad (_("endw without while"));
6679 ignore_rest_of_line ();
6680 return;
6681 }
6682
6683 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6684 sprintf (buf, "bra %s", mri_control_stack->next);
6685 mri_assemble (buf);
6686 free (buf);
6687
6688 colon (mri_control_stack->bottom);
6689
6690 pop_mri_control ();
6691
6692 if (flag_mri)
6693 {
6694 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6695 ++input_line_pointer;
6696 }
6697
6698 demand_empty_rest_of_line ();
6699}
6700\f
6701/*
6702 * md_parse_option
6703 * Invocation line includes a switch not recognized by the base assembler.
6704 * See if it's a processor-specific option. These are:
6705 *
6706 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6707 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6708 * Select the architecture. Instructions or features not
6709 * supported by the selected architecture cause fatal
6710 * errors. More than one may be specified. The default is
6711 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6712 * for -m68000, and -m68882 is a synonym for -m68881.
6713 * -[A]m[c]no-68851, -[A]m[c]no-68881
6714 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6715 * so don't use or document it, but that's the way the parsing
6716 * works).
6717 *
6718 * -pic Indicates PIC.
6719 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6720 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6721 *
6722 * --bitwise-or
6723 * Permit `|' to be used in expressions.
6724 *
6725 */
6726
6727#ifdef OBJ_ELF
5a38dc70 6728const char *md_shortopts = "lSA:m:kQ:V";
252b5132 6729#else
5a38dc70 6730const char *md_shortopts = "lSA:m:k";
252b5132
RH		 6731#endif
6732
6733struct option md_longopts[] = {
6734#define OPTION_PIC (OPTION_MD_BASE)
6735 {"pic", no_argument, NULL, OPTION_PIC},
6736#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6737 {"register-prefix-optional", no_argument, NULL,
6738 OPTION_REGISTER_PREFIX_OPTIONAL},
6739#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6740 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6741#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6742 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6743#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6744 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6745#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6746 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6747#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6748 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6749#define OPTION_PCREL (OPTION_MD_BASE + 7)
6750 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6751 {NULL, no_argument, NULL, 0}
6752};
bc805888 6753size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6754
6755int
6756md_parse_option (c, arg)
6757 int c;
6758 char *arg;
6759{
6760 switch (c)
6761 {
6762 case 'l': /* -l means keep external to 2 bit offset
6763 rather than 16 bit one */
6764 flag_short_refs = 1;
6765 break;
6766
6767 case 'S': /* -S means that jbsr's always turn into
6768 jsr's. */
6769 flag_long_jumps = 1;
6770 break;
6771
28e7409f
NC		 6772 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6773 branches into absolute jumps. */
6774 flag_keep_pcrel = 1;
6775 break;
6776
252b5132
RH		 6777 case 'A':
6778 if (*arg == 'm')
8a104df9 6779 arg++;
252b5132
RH		 6780 /* intentional fall-through */
6781 case 'm':
6782
6783 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6784 {
6785 int i;
6786 unsigned long arch;
6787 const char *oarg = arg;
6788
6789 arg += 3;
6790 if (*arg == 'm')
6791 {
6792 arg++;
6793 if (arg[0] == 'c' && arg[1] == '6')
6794 arg++;
6795 }
6796 for (i = 0; i < n_archs; i++)
6797 if (!strcmp (arg, archs[i].name))
6798 break;
6799 if (i == n_archs)
6800 {
6801 unknown:
6802 as_bad (_("unrecognized option `%s'"), oarg);
6803 return 0;
6804 }
6805 arch = archs[i].arch;
6806 if (arch == m68881)
6807 no_68881 = 1;
6808 else if (arch == m68851)
6809 no_68851 = 1;
6810 else
6811 goto unknown;
6812 }
6813 else
6814 {
6815 int i;
6816
6817 if (arg[0] == 'c' && arg[1] == '6')
6818 arg++;
6819
6820 for (i = 0; i < n_archs; i++)
6821 if (!strcmp (arg, archs[i].name))
6822 {
6823 unsigned long arch = archs[i].arch;
6824 if (cpu_of_arch (arch))
6825 /* It's a cpu spec. */
6826 {
6827 current_architecture &= ~m68000up;
6828 current_architecture |= arch;
6829 }
6830 else if (arch == m68881)
6831 {
6832 current_architecture |= m68881;
6833 no_68881 = 0;
6834 }
6835 else if (arch == m68851)
6836 {
6837 current_architecture |= m68851;
6838 no_68851 = 0;
6839 }
6840 else
6841 /* ??? */
6842 abort ();
6843 break;
6844 }
6845 if (i == n_archs)
6846 {
6847 as_bad (_("unrecognized architecture specification `%s'"), arg);
6848 return 0;
6849 }
6850 }
6851 break;
6852
6853 case OPTION_PIC:
6854 case 'k':
6855 flag_want_pic = 1;
6856 break; /* -pic, Position Independent Code */
6857
6858 case OPTION_REGISTER_PREFIX_OPTIONAL:
6859 flag_reg_prefix_optional = 1;
6860 reg_prefix_optional_seen = 1;
6861 break;
6862
6863 /* -V: SVR4 argument to print version ID. */
6864 case 'V':
6865 print_version_id ();
6866 break;
6867
6868 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6869 should be emitted or not. FIXME: Not implemented. */
6870 case 'Q':
6871 break;
6872
6873 case OPTION_BITWISE_OR:
6874 {
6875 char *n, *t;
6876 const char *s;
6877
6878 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6879 t = n;
6880 for (s = m68k_comment_chars; *s != '\0'; s++)
6881 if (*s != '|')
6882 *t++ = *s;
6883 *t = '\0';
6884 m68k_comment_chars = n;
6885 }
6886 break;
6887
6888 case OPTION_BASE_SIZE_DEFAULT_16:
6889 m68k_index_width_default = SIZE_WORD;
6890 break;
6891
6892 case OPTION_BASE_SIZE_DEFAULT_32:
6893 m68k_index_width_default = SIZE_LONG;
6894 break;
6895
6896 case OPTION_DISP_SIZE_DEFAULT_16:
6897 m68k_rel32 = 0;
6898 m68k_rel32_from_cmdline = 1;
6899 break;
6900
6901 case OPTION_DISP_SIZE_DEFAULT_32:
6902 m68k_rel32 = 1;
6903 m68k_rel32_from_cmdline = 1;
6904 break;
6905
6906 default:
6907 return 0;
6908 }
6909
6910 return 1;
6911}
6912
6913void
6914md_show_usage (stream)
6915 FILE *stream;
6916{
76f57f3a 6917 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 6918 int i;
6919 unsigned int default_arch;
76f57f3a 6920
8a104df9 6921 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 6922 if (*default_cpu == 'm')
6923 default_cpu++;
6924 for (i = 0; i < n_archs; i++)
6925 {
6926 if (strcasecmp (default_cpu, archs[i].name) == 0)
6927 {
6928 default_arch = archs[i].arch;
6929 for (i = 0; i < n_archs; i++)
6930 {
6931 if (archs[i].arch == default_arch
6932 && !archs[i].alias)
6933 {
6934 default_cpu = archs[i].name;
6935 break;
6936 }
6937 }
6938 }
6939 }
6940
bc805888 6941 fprintf (stream, _("\
252b5132
RH		 6942680X0 options:\n\
6943-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 6944-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6945-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6946-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
76f57f3a 6947 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 6948-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6949 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 6950 [default yes for 68020, 68030, and cpu32]\n"),
6951 default_cpu);
bc805888 6952 fprintf (stream, _("\
252b5132
RH		 6953-m68851 | -mno-68851\n\
6954 target has/lacks memory-management unit coprocessor\n\
6955 [default yes for 68020 and up]\n\
6956-pic, -k generate position independent code\n\
6957-S turn jbsr into jsr\n\
28e7409f 6958--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6959--register-prefix-optional\n\
6960 recognize register names without prefix character\n\
6961--bitwise-or do not treat `|' as a comment character\n"));
6962 fprintf (stream, _("\
6963--base-size-default-16 base reg without size is 16 bits\n\
6964--base-size-default-32 base reg without size is 32 bits (default)\n\
6965--disp-size-default-16 displacement with unknown size is 16 bits\n\
6966--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6967}
6968\f
6969#ifdef TEST2
6970
6971/* TEST2: Test md_assemble() */
6972/* Warning, this routine probably doesn't work anymore */
6973
6974main ()
6975{
6976 struct m68k_it the_ins;
6977 char buf[120];
6978 char *cp;
6979 int n;
6980
6981 m68k_ip_begin ();
6982 for (;;)
6983 {
6984 if (!gets (buf) || !*buf)
6985 break;
6986 if (buf[0] == '|' || buf[1] == '.')
6987 continue;
6988 for (cp = buf; *cp; cp++)
6989 if (*cp == '\t')
6990 *cp = ' ';
6991 if (is_label (buf))
6992 continue;
6993 memset (&the_ins, '\0', sizeof (the_ins));
6994 m68k_ip (&the_ins, buf);
6995 if (the_ins.error)
6996 {
6997 printf (_("Error %s in %s\n"), the_ins.error, buf);
6998 }
6999 else
7000 {
7001 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7002 for (n = 0; n < the_ins.numo; n++)
7003 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7004 printf (" ");
7005 print_the_insn (&the_ins.opcode[0], stdout);
7006 (void) putchar ('\n');
7007 }
7008 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7009 {
7010 if (the_ins.operands[n].error)
7011 {
7012 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7013 continue;
7014 }
7015 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7016 if (the_ins.operands[n].b_const)
7017 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7018 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7019 if (the_ins.operands[n].b_iadd)
7020 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7021 (void) putchar ('\n');
7022 }
7023 }
7024 m68k_ip_end ();
7025 return 0;
7026}
7027
7028is_label (str)
7029 char *str;
7030{
7031 while (*str == ' ')
7032 str++;
7033 while (*str && *str != ' ')
7034 str++;
7035 if (str[-1] == ':' || str[1] == '=')
7036 return 1;
7037 return 0;
7038}
7039
7040#endif
7041
7042/* Possible states for relaxation:
7043
7044 0 0 branch offset byte (bra, etc)
7045 0 1 word
7046 0 2 long
7047
7048 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7049 1 1 word
7050 1 2 long
7051
7052 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7053 2 1 word-long
7054 2 2 long-word
7055 2 3 long-long
7056
7057 */
7058
7059/* We have no need to default values of symbols. */
7060
252b5132
RH		 7061symbolS *
7062md_undefined_symbol (name)
36823076 7063 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7064{
7065 return 0;
7066}
7067
7068/* Round up a section size to the appropriate boundary. */
7069valueT
7070md_section_align (segment, size)
36823076 7071 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7072 valueT size;
7073{
7074#ifdef OBJ_AOUT
7075#ifdef BFD_ASSEMBLER
7076 /* For a.out, force the section size to be aligned. If we don't do
7077 this, BFD will align it for us, but it will not write out the
7078 final bytes of the section. This may be a bug in BFD, but it is
7079 easier to fix it here since that is how the other a.out targets
7080 work. */
7081 int align;
7082
7083 align = bfd_get_section_alignment (stdoutput, segment);
7084 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7085#endif
7086#endif
7087
7088 return size;
7089}
7090
7091/* Exactly what point is a PC-relative offset relative TO?
7092 On the 68k, it is relative to the address of the first extension
7093 word. The difference between the addresses of the offset and the
92774660 7094 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7095long
7096md_pcrel_from (fixP)
7097 fixS *fixP;
7098{
7099 int adjust;
7100
8390138c
AS		 7101 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7102 sign extend the value here. */
7103 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7104 if (adjust == 64)
7105 adjust = -1;
7106 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7107}
7108
7109#ifndef BFD_ASSEMBLER
7110#ifdef OBJ_COFF
7111
252b5132
RH		 7112void
7113tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7114 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7115{
7116}
7117
7118int
7119tc_coff_sizemachdep (frag)
7120 fragS *frag;
7121{
7122 switch (frag->fr_subtype & 0x3)
7123 {
7124 case BYTE:
7125 return 1;
7126 case SHORT:
7127 return 2;
7128 case LONG:
7129 return 4;
7130 default:
7131 abort ();
7132 return 0;
7133 }
7134}
7135
7136#endif
7137#endif
0d96863f 7138#ifdef OBJ_ELF
8a104df9
KH		 7139void
7140m68k_elf_final_processing ()
0d96863f 7141{
8a104df9
KH		 7142 /* Set file-specific flags if this is a cpu32 processor */
7143 if (cpu_of_arch (current_architecture) & cpu32)
7144 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7145 else if ((cpu_of_arch (current_architecture) & m68000up)
7146 && !(cpu_of_arch (current_architecture) & m68020up))
7147 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7148}
7149#endif
c04898f8
AS		 7150
7151int
7152tc_m68k_regname_to_dw2regnum (const char *regname)
7153{
7154 unsigned int regnum;
7155 static const char *const regnames[] =
7156 {
7157 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7158 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7159 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7160 "pc"
7161 };
7162
7163 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7164 if (strcmp (regname, regnames[regnum]) == 0)
7165 return regnum;
7166
7167 return -1;
7168}
7169
7170void
7171tc_m68k_frame_initial_instructions (void)
7172{
7173 static int sp_regno = -1;
7174
7175 if (sp_regno < 0)
7176 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7177
7178 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7179 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7180}
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