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2005-05-24 Paolo Bonzini <bonzini@gnu.org>
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
6358301e 3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
252b5132
RH		 36/* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40#if defined (TE_SVR4) || defined (TE_DELTA)
41const char *m68k_comment_chars = "|#";
42#else
43const char *m68k_comment_chars = "|";
44#endif
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
92774660
KH		 51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
252b5132
RH		 53const char line_comment_chars[] = "#*";
54
63a0b638 55const char line_separator_chars[] = ";";
252b5132 56
36759679 57/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 58const char EXP_CHARS[] = "eE";
252b5132
RH		 59
60/* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
5a38dc70 63const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 64
65/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
36759679 69const int md_reloc_size = 8; /* Size of relocation record. */
252b5132
RH		 70
71/* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
92774660 73 references. Not implemented. For ELF there are other means
252b5132
RH		 74 to denote pic relocations. */
75int flag_want_pic;
76
36759679
NC		 77static int flag_short_refs; /* -l option. */
78static int flag_long_jumps; /* -S option. */
28e7409f 79static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 80
81#ifdef REGISTER_PREFIX_OPTIONAL
82int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83#else
84int flag_reg_prefix_optional;
85#endif
86
87/* Whether --register-prefix-optional was used on the command line. */
88static int reg_prefix_optional_seen;
89
90/* The floating point coprocessor to use by default. */
91static enum m68k_register m68k_float_copnum = COP1;
92
93/* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95static int m68k_abspcadd;
96
97/* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99static int m68k_quick = 1;
100
101/* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104static int m68k_rel32 = 1;
105
106/* This is non-zero if m68k_rel32 was set from the command line. */
107static int m68k_rel32_from_cmdline;
108
109/* The default width to use for an index register when using a base
110 displacement. */
111static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113/* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
252b5132
RH		 116struct label_line
117{
118 struct label_line *next;
119 symbolS *label;
120 char *file;
121 unsigned int line;
122 int text;
123};
124
125/* The list of labels. */
126
127static struct label_line *labels;
128
129/* The current label. */
130
131static struct label_line *current_label;
132
36759679
NC		 133/* Its an arbitrary name: This means I don't approve of it.
134 See flames below. */
252b5132
RH		 135static struct obstack robyn;
136
252b5132
RH		 137struct m68k_incant
138 {
139 const char *m_operands;
140 unsigned long m_opcode;
141 short m_opnum;
142 short m_codenum;
143 int m_arch;
144 struct m68k_incant *m_next;
145 };
146
147#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148#define gettwo(x) (((x)->m_opcode)&0xffff)
149
150static const enum m68k_register m68000_control_regs[] = { 0 };
151static const enum m68k_register m68010_control_regs[] = {
152 SFC, DFC, USP, VBR,
153 0
154};
155static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
157 0
158};
159static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
162 0
163};
164static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
167 0
168};
6da466c7 169static const enum m68k_register mcf_control_regs[] = {
3e602632 170 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 171 RAMBAR0, RAMBAR1, MBAR,
172 0
173};
3e602632
NC		 174static const enum m68k_register mcf528x_control_regs[] = {
175 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
176 0
177};
178static const enum m68k_register mcfv4e_control_regs[] = {
179 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
180 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
181 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
182 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
183 0
184};
252b5132
RH		 185#define cpu32_control_regs m68010_control_regs
186
187static const enum m68k_register *control_regs;
188
36759679 189/* Internal form of a 68020 instruction. */
252b5132
RH		 190struct m68k_it
191{
192 const char *error;
36759679 193 const char *args; /* List of opcode info. */
252b5132
RH		 194 int numargs;
195
36759679 196 int numo; /* Number of shorts in opcode. */
252b5132
RH		 197 short opcode[11];
198
199 struct m68k_op operands[6];
200
36759679 201 int nexp; /* Number of exprs in use. */
252b5132
RH		 202 struct m68k_exp exprs[4];
203
36759679 204 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 205 struct
206 {
36759679 207 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 208 symbolS *fadd;
209 offsetT foff;
210 int fragty;
211 }
212 fragb[4];
213
36759679 214 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 215 struct
216 {
217 int n;
218 expressionS exp;
219 char wid;
220 char pcrel;
221 /* In a pc relative address the difference between the address
222 of the offset and the address that the offset is relative
223 to. This depends on the addressing mode. Basically this
224 is the value to put in the offset field to address the
225 first byte of the offset, without regarding the special
226 significance of some values (in the branch instruction, for
227 example). */
228 int pcrel_fix;
229#ifdef OBJ_ELF
230 /* Whether this expression needs special pic relocation, and if
231 so, which. */
232 enum pic_relocation pic_reloc;
233#endif
234 }
36759679 235 reloc[5]; /* Five is enough??? */
252b5132
RH		 236};
237
6b6e92f4 238#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
252b5132
RH		 239#define float_of_arch(x) ((x) & mfloat)
240#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 241#define arch_coldfire_p(x) ((x) & mcfisa_a)
242#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 243
36759679 244/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 245#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 246
36759679 247static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 248
249#define op(ex) ((ex)->exp.X_op)
250#define adds(ex) ((ex)->exp.X_add_symbol)
251#define subs(ex) ((ex)->exp.X_op_symbol)
252#define offs(ex) ((ex)->exp.X_add_number)
253
36759679 254/* Macros for adding things to the m68k_it struct. */
252b5132
RH		 255#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
256
257/* Static functions. */
252b5132
RH		 258static void insop PARAMS ((int, const struct m68k_incant *));
259static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
260static void add_frag PARAMS ((symbolS *, offsetT, int));
261
36759679
NC		 262/* Like addword, but goes BEFORE general operands. */
263
252b5132
RH		 264static void
265insop (w, opcode)
266 int w;
267 const struct m68k_incant *opcode;
268{
269 int z;
07726851 270 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 271 the_ins.opcode[z] = the_ins.opcode[z - 1];
272 for (z = 0; z < the_ins.nrel; z++)
273 the_ins.reloc[z].n += 2;
252b5132
RH		 274 for (z = 0; z < the_ins.nfrag; z++)
275 the_ins.fragb[z].fragoff++;
8a104df9 276 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 277 the_ins.numo++;
278}
279
280/* The numo+1 kludge is so we can hit the low order byte of the prev word.
281 Blecch. */
282static void
283add_fix (width, exp, pc_rel, pc_fix)
284 int width;
285 struct m68k_exp *exp;
286 int pc_rel;
287 int pc_fix;
288{
289 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
290 ? (the_ins.numo*2-1)
291 : (((width)=='b')
292 ? (the_ins.numo*2+1)
293 : (the_ins.numo*2)));
294 the_ins.reloc[the_ins.nrel].exp = exp->exp;
295 the_ins.reloc[the_ins.nrel].wid = width;
296 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
297#ifdef OBJ_ELF
298 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
299#endif
300 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
301}
302
303/* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
307
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
311
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
313static void
314add_frag (add, off, type)
315 symbolS *add;
316 offsetT off;
317 int type;
318{
8a104df9
KH		 319 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
320 the_ins.fragb[the_ins.nfrag].fadd = add;
321 the_ins.fragb[the_ins.nfrag].foff = off;
322 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 323}
324
325#define isvar(ex) \
326 (op (ex) != O_constant && op (ex) != O_big)
327
328static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
329static int get_num PARAMS ((struct m68k_exp *exp, int ok));
330static void m68k_ip PARAMS ((char *));
331static void insert_reg PARAMS ((const char *, int));
332static void select_control_regs PARAMS ((void));
333static void init_regtable PARAMS ((void));
334static int reverse_16_bits PARAMS ((int in));
335static int reverse_8_bits PARAMS ((int in));
336static void install_gen_operand PARAMS ((int mode, int val));
337static void install_operand PARAMS ((int mode, int val));
338static void s_bss PARAMS ((int));
339static void s_data1 PARAMS ((int));
340static void s_data2 PARAMS ((int));
341static void s_even PARAMS ((int));
342static void s_proc PARAMS ((int));
343static void mri_chip PARAMS ((void));
344static void s_chip PARAMS ((int));
345static void s_fopt PARAMS ((int));
346static void s_opt PARAMS ((int));
347static void s_reg PARAMS ((int));
348static void s_restore PARAMS ((int));
349static void s_save PARAMS ((int));
350static void s_mri_if PARAMS ((int));
351static void s_mri_else PARAMS ((int));
352static void s_mri_endi PARAMS ((int));
353static void s_mri_break PARAMS ((int));
354static void s_mri_next PARAMS ((int));
355static void s_mri_for PARAMS ((int));
356static void s_mri_endf PARAMS ((int));
357static void s_mri_repeat PARAMS ((int));
358static void s_mri_until PARAMS ((int));
359static void s_mri_while PARAMS ((int));
360static void s_mri_endw PARAMS ((int));
252b5132
RH		 361static void md_convert_frag_1 PARAMS ((fragS *));
362
363static int current_architecture;
6b6e92f4 364static int current_chip;
252b5132 365
dc84e067
NC		 366struct m68k_cpu
367 {
368 unsigned long arch;
6b6e92f4 369 unsigned long chip;
dc84e067
NC		 370 const char *name;
371 int alias;
372 };
252b5132 373
dc84e067
NC		 374static const struct m68k_cpu archs[] =
375 {
6b6e92f4
NC		 376 { m68000, m68000, "68000", 0 },
377 { m68010, m68010, "68010", 0 },
378 { m68020, m68020, "68020", 0 },
379 { m68030, m68030, "68030", 0 },
380 { m68040, m68040, "68040", 0 },
381 { m68060, m68060, "68060", 0 },
382 { cpu32, cpu32, "cpu32", 0 },
383 { m68881, m68881, "68881", 0 },
384 { m68851, m68851, "68851", 0 },
385 { mcfisa_a, mcf5200, "5200", 0 },
386 { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
387 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
388 { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
389 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
390 { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
391 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
392 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
393 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
dc84e067
NC		 394 /* Aliases (effectively, so far as gas is concerned) for the above
395 cpus. */
6b6e92f4
NC		 396 { m68020, m68020, "68k", 1 },
397 { m68000, m68000, "68008", 1 },
398 { m68000, m68000, "68302", 1 },
399 { m68000, m68000, "68306", 1 },
400 { m68000, m68000, "68307", 1 },
401 { m68000, m68000, "68322", 1 },
402 { m68000, m68000, "68356", 1 },
403 { m68000, m68000, "68ec000", 1 },
404 { m68000, m68000, "68hc000", 1 },
405 { m68000, m68000, "68hc001", 1 },
406 { m68020, m68020, "68ec020", 1 },
407 { m68030, m68030, "68ec030", 1 },
408 { m68040, m68040, "68ec040", 1 },
409 { m68060, m68060, "68ec060", 1 },
410 { cpu32, cpu32, "68330", 1 },
411 { cpu32, cpu32, "68331", 1 },
412 { cpu32, cpu32, "68332", 1 },
413 { cpu32, cpu32, "68333", 1 },
414 { cpu32, cpu32, "68334", 1 },
415 { cpu32, cpu32, "68336", 1 },
416 { cpu32, cpu32, "68340", 1 },
417 { cpu32, cpu32, "68341", 1 },
418 { cpu32, cpu32, "68349", 1 },
419 { cpu32, cpu32, "68360", 1 },
420 { m68881, m68881, "68882", 1 },
421 { mcfisa_a, mcf5200, "5202", 1 },
422 { mcfisa_a, mcf5200, "5204", 1 },
423 { mcfisa_a, mcf5200, "5206", 1 },
424 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
425 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
426 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
427 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
428 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
429 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
430 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
431 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
432 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
433 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
434 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
435 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
436 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
437 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
438 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
439 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
440 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
441 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
442 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
dc84e067 443 };
252b5132
RH		 444
445static const int n_archs = sizeof (archs) / sizeof (archs[0]);
446
151337e8
NC		 447/* This is the assembler relaxation table for m68k. m68k is a rich CISC
448 architecture and we have a lot of relaxation modes. */
252b5132 449
151337e8
NC		 450/* Macros used in the relaxation code. */
451#define TAB(x,y) (((x) << 2) + (y))
452#define TABTYPE(x) ((x) >> 2)
453
454/* Relaxation states. */
455#define BYTE 0
456#define SHORT 1
457#define LONG 2
458#define SZ_UNDEF 3
459
460/* Here are all the relaxation modes we support. First we can relax ordinary
461 branches. On 68020 and higher and on CPU32 all branch instructions take
462 three forms, so on these CPUs all branches always remain as such. When we
463 have to expand to the LONG form on a 68000, though, we substitute an
464 absolute jump instead. This is a direct replacement for unconditional
465 branches and a branch over a jump for conditional branches. However, if the
466 user requires PIC and disables this with --pcrel, we can only relax between
467 BYTE and SHORT forms, punting if that isn't enough. This gives us four
468 different relaxation modes for branches: */
469
36759679
NC		 470#define BRANCHBWL 0 /* Branch byte, word, or long. */
471#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
472#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
473#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 474
475/* We also relax coprocessor branches and DBcc's. All CPUs that support
476 coprocessor branches support them in word and long forms, so we have only
477 one relaxation mode for them. DBcc's are word only on all CPUs. We can
478 relax them to the LONG form with a branch-around sequence. This sequence
479 can use a long branch (if available) or an absolute jump (if acceptable).
480 This gives us two relaxation modes. If long branches are not available and
481 absolute jumps are not acceptable, we don't relax DBcc's. */
482
36759679
NC		 483#define FBRANCH 4 /* Coprocessor branch. */
484#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
485#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 486
487/* That's all for instruction relaxation. However, we also relax PC-relative
488 operands. Specifically, we have three operand relaxation modes. On the
489 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
490 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
491 two. Also PC+displacement+index operands in their simple form (with a non-
492 suppressed index without memory indirection) are supported on all CPUs, but
493 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
494 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
495 form of the PC+displacement+index operand. Finally, some absolute operands
496 can be relaxed down to 16-bit PC-relative. */
497
36759679
NC		 498#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
499#define PCINDEX 8 /* PC + displacement + index. */
500#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 501
502/* Note that calls to frag_var need to specify the maximum expansion
503 needed; this is currently 10 bytes for DBCC. */
504
505/* The fields are:
506 How far Forward this mode will reach:
507 How far Backward this mode will reach:
508 How many bytes this mode will add to the size of the frag
509 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 510
511 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 512relax_typeS md_relax_table[] =
513{
ac62c346
AM		 514 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
515 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
516 { 0, 0, 4, 0 },
517 { 1, 1, 0, 0 },
518
519 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
520 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
521 { 0, 0, 4, 0 },
522 { 1, 1, 0, 0 },
523
524 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
525 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
526 { 0, 0, 6, 0 },
527 { 1, 1, 0, 0 },
528
529 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
530 { 0, 0, 2, 0 },
531 { 1, 1, 0, 0 },
532 { 1, 1, 0, 0 },
533
36759679 534 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 535 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
536 { 0, 0, 4, 0 },
537 { 1, 1, 0, 0 },
538
36759679 539 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 540 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
541 { 0, 0, 10, 0 },
542 { 1, 1, 0, 0 },
543
36759679 544 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 545 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
546 { 0, 0, 10, 0 },
547 { 1, 1, 0, 0 },
548
36759679 549 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 550 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
551 { 0, 0, 6, 0 },
552 { 1, 1, 0, 0 },
553
554 { 125, -130, 0, TAB (PCINDEX, SHORT) },
555 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
556 { 0, 0, 4, 0 },
557 { 1, 1, 0, 0 },
558
36759679 559 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 560 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
561 { 0, 0, 4, 0 },
562 { 1, 1, 0, 0 },
252b5132
RH		 563};
564
565/* These are the machine dependent pseudo-ops. These are included so
566 the assembler can work on the output from the SUN C compiler, which
36759679 567 generates these. */
252b5132
RH		 568
569/* This table describes all the machine specific pseudo-ops the assembler
570 has to support. The fields are:
571 pseudo-op name without dot
572 function to call to execute this pseudo-op
36759679 573 Integer arg to pass to the function. */
252b5132
RH		 574const pseudo_typeS md_pseudo_table[] =
575{
576 {"data1", s_data1, 0},
577 {"data2", s_data2, 0},
578 {"bss", s_bss, 0},
579 {"even", s_even, 0},
580 {"skip", s_space, 0},
581 {"proc", s_proc, 0},
582#if defined (TE_SUN3) || defined (OBJ_ELF)
583 {"align", s_align_bytes, 0},
584#endif
585#ifdef OBJ_ELF
586 {"swbeg", s_ignore, 0},
587#endif
588 {"extend", float_cons, 'x'},
589 {"ldouble", float_cons, 'x'},
590
591 /* The following pseudo-ops are supported for MRI compatibility. */
592 {"chip", s_chip, 0},
593 {"comline", s_space, 1},
594 {"fopt", s_fopt, 0},
595 {"mask2", s_ignore, 0},
596 {"opt", s_opt, 0},
597 {"reg", s_reg, 0},
598 {"restore", s_restore, 0},
599 {"save", s_save, 0},
600
601 {"if", s_mri_if, 0},
602 {"if.b", s_mri_if, 'b'},
603 {"if.w", s_mri_if, 'w'},
604 {"if.l", s_mri_if, 'l'},
605 {"else", s_mri_else, 0},
606 {"else.s", s_mri_else, 's'},
607 {"else.l", s_mri_else, 'l'},
608 {"endi", s_mri_endi, 0},
609 {"break", s_mri_break, 0},
610 {"break.s", s_mri_break, 's'},
611 {"break.l", s_mri_break, 'l'},
612 {"next", s_mri_next, 0},
613 {"next.s", s_mri_next, 's'},
614 {"next.l", s_mri_next, 'l'},
615 {"for", s_mri_for, 0},
616 {"for.b", s_mri_for, 'b'},
617 {"for.w", s_mri_for, 'w'},
618 {"for.l", s_mri_for, 'l'},
619 {"endf", s_mri_endf, 0},
620 {"repeat", s_mri_repeat, 0},
621 {"until", s_mri_until, 0},
622 {"until.b", s_mri_until, 'b'},
623 {"until.w", s_mri_until, 'w'},
624 {"until.l", s_mri_until, 'l'},
625 {"while", s_mri_while, 0},
626 {"while.b", s_mri_while, 'b'},
627 {"while.w", s_mri_while, 'w'},
628 {"while.l", s_mri_while, 'l'},
629 {"endw", s_mri_endw, 0},
630
631 {0, 0, 0}
632};
633
252b5132
RH		 634/* The mote pseudo ops are put into the opcode table, since they
635 don't start with a . they look like opcodes to gas.
636 */
637
638#ifdef M68KCOFF
639extern void obj_coff_section PARAMS ((int));
640#endif
641
5a38dc70 642const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 643{
644
645 {"dcl", cons, 4},
646 {"dc", cons, 2},
647 {"dcw", cons, 2},
648 {"dcb", cons, 1},
649
650 {"dsl", s_space, 4},
651 {"ds", s_space, 2},
652 {"dsw", s_space, 2},
653 {"dsb", s_space, 1},
654
655 {"xdef", s_globl, 0},
656#ifdef OBJ_ELF
657 {"align", s_align_bytes, 0},
658#else
659 {"align", s_align_ptwo, 0},
660#endif
661#ifdef M68KCOFF
662 {"sect", obj_coff_section, 0},
663 {"section", obj_coff_section, 0},
664#endif
665 {0, 0, 0}
666};
667
668#define issbyte(x) ((x)>=-128 && (x)<=127)
669#define isubyte(x) ((x)>=0 && (x)<=255)
670#define issword(x) ((x)>=-32768 && (x)<=32767)
671#define isuword(x) ((x)>=0 && (x)<=65535)
672
673#define isbyte(x) ((x)>= -255 && (x)<=255)
674#define isword(x) ((x)>=-65536 && (x)<=65535)
675#define islong(x) (1)
676
677extern char *input_line_pointer;
678
252b5132
RH		 679static char notend_table[256];
680static char alt_notend_table[256];
681#define notend(s) \
682 (! (notend_table[(unsigned char) *s] \
683 || (*s == ':' \
684 && alt_notend_table[(unsigned char) s[1]])))
685
6b6e92f4
NC		 686/* Return a human readable string holding the list of chips that are
687 valid for a particular architecture, suppressing aliases (unless
688 there is only one of them). */
689
690static char *
691find_cf_chip (int architecture)
692{
693 static char buf[1024];
694 int i, j, n_chips, n_alias;
695 char *cp;
696
697 strcpy (buf, " (");
698 cp = buf + strlen (buf);
699
700 for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
701 if (archs[i].arch & architecture)
702 {
703 n_chips++;
704 if (archs[i].alias)
705 n_alias++;
706 }
707
708 if (n_chips == 0)
709 as_fatal (_("no matching ColdFire architectures found"));
710
711 if (n_alias > 1)
712 n_chips -= n_alias;
713
714 for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
715 if (archs[i].arch & architecture)
716 {
717 if (j)
718 {
719 if (((j == n_chips - 1) && !(n_alias > 1))|| ! n_alias)
720 {
721 if (n_chips == 2)
722 {
723 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
724 cp += strlen (cp);
725 }
726 else
727 {
728 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
729 cp += strlen (cp);
730 }
731 }
732 else
733 {
734 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
735 cp += strlen (cp);
736 }
737 }
738 strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
739 cp += strlen (cp);
740 j++;
741 }
742
743 if (n_alias > 1)
744 {
745 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
746 cp += strlen (cp);
747 }
748
749 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
750
751 return buf;
752}
753
252b5132
RH		 754#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
755
756#ifdef NO_PCREL_RELOCS
757
758int
6b6e92f4 759make_pcrel_absolute (fixP, add_number)
252b5132
RH		 760 fixS *fixP;
761 long *add_number;
762{
763 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
764
36759679 765 /* Rewrite the PC relative instructions to absolute address ones.
67c1ffbe 766 these are rumored to be faster, and the apollo linker refuses
36759679
NC		 767 to deal with the PC relative relocations. */
768 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
252b5132 769 {
36759679 770 if (flag_keep_pcrel)
6b6e92f4 771 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 772 opcode[0] = 0x4e;
773 opcode[1] = 0xf9;
774 }
36759679 775 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
252b5132 776 {
36759679 777 if (flag_keep_pcrel)
6b6e92f4 778 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
252b5132
RH		 779 opcode[0] = 0x4e;
780 opcode[1] = 0xb9;
781 }
782 else
783 as_fatal (_("Unknown PC relative instruction"));
784 *add_number -= 4;
785 return 0;
786}
787
788#endif /* NO_PCREL_RELOCS */
789
790short
791tc_coff_fix2rtype (fixP)
792 fixS *fixP;
793{
794 if (fixP->fx_tcbit && fixP->fx_size == 4)
795 return R_RELLONG_NEG;
796#ifdef NO_PCREL_RELOCS
797 know (fixP->fx_pcrel == 0);
798 return (fixP->fx_size == 1 ? R_RELBYTE
799 : fixP->fx_size == 2 ? R_DIR16
800 : R_DIR32);
801#else
802 return (fixP->fx_pcrel ?
803 (fixP->fx_size == 1 ? R_PCRBYTE :
804 fixP->fx_size == 2 ? R_PCRWORD :
805 R_PCRLONG) :
806 (fixP->fx_size == 1 ? R_RELBYTE :
807 fixP->fx_size == 2 ? R_RELWORD :
808 R_RELLONG));
809#endif
810}
811
812#endif
813
814#ifdef OBJ_ELF
815
c801568a
AM		 816/* Return zero if the reference to SYMBOL from within the same segment may
817 be relaxed. */
818
819/* On an ELF system, we can't relax an externally visible symbol,
820 because it may be overridden by a shared library. However, if
821 TARGET_OS is "elf", then we presume that we are assembling for an
822 embedded system, in which case we don't have to worry about shared
823 libraries, and we can relax any external sym. */
824
825#define relaxable_symbol(symbol) \
6358301e 826 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 827 || S_IS_WEAK (symbol)))
828
252b5132
RH		 829/* Compute the relocation code for a fixup of SIZE bytes, using pc
830 relative relocation if PCREL is non-zero. PIC says whether a special
831 pic relocation was requested. */
832
833static bfd_reloc_code_real_type get_reloc_code
834 PARAMS ((int, int, enum pic_relocation));
835
836static bfd_reloc_code_real_type
837get_reloc_code (size, pcrel, pic)
838 int size;
839 int pcrel;
840 enum pic_relocation pic;
841{
842 switch (pic)
843 {
844 case pic_got_pcrel:
845 switch (size)
846 {
847 case 1:
848 return BFD_RELOC_8_GOT_PCREL;
849 case 2:
850 return BFD_RELOC_16_GOT_PCREL;
851 case 4:
852 return BFD_RELOC_32_GOT_PCREL;
853 }
854 break;
855
856 case pic_got_off:
857 switch (size)
858 {
859 case 1:
860 return BFD_RELOC_8_GOTOFF;
861 case 2:
862 return BFD_RELOC_16_GOTOFF;
863 case 4:
864 return BFD_RELOC_32_GOTOFF;
865 }
866 break;
867
868 case pic_plt_pcrel:
869 switch (size)
870 {
871 case 1:
872 return BFD_RELOC_8_PLT_PCREL;
873 case 2:
874 return BFD_RELOC_16_PLT_PCREL;
875 case 4:
876 return BFD_RELOC_32_PLT_PCREL;
877 }
878 break;
879
880 case pic_plt_off:
881 switch (size)
882 {
883 case 1:
884 return BFD_RELOC_8_PLTOFF;
885 case 2:
886 return BFD_RELOC_16_PLTOFF;
887 case 4:
888 return BFD_RELOC_32_PLTOFF;
889 }
890 break;
891
892 case pic_none:
893 if (pcrel)
894 {
895 switch (size)
896 {
897 case 1:
898 return BFD_RELOC_8_PCREL;
899 case 2:
900 return BFD_RELOC_16_PCREL;
901 case 4:
902 return BFD_RELOC_32_PCREL;
903 }
904 }
905 else
906 {
907 switch (size)
908 {
909 case 1:
910 return BFD_RELOC_8;
911 case 2:
912 return BFD_RELOC_16;
913 case 4:
914 return BFD_RELOC_32;
915 }
916 }
917 }
918
919 if (pcrel)
920 {
921 if (pic == pic_none)
922 as_bad (_("Can not do %d byte pc-relative relocation"), size);
923 else
924 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
925 }
926 else
927 {
928 if (pic == pic_none)
929 as_bad (_("Can not do %d byte relocation"), size);
930 else
931 as_bad (_("Can not do %d byte pic relocation"), size);
932 }
933
934 return BFD_RELOC_NONE;
935}
936
937/* Here we decide which fixups can be adjusted to make them relative
938 to the beginning of the section instead of the symbol. Basically
939 we need to make sure that the dynamic relocations are done
940 correctly, so in some cases we force the original symbol to be
941 used. */
942int
943tc_m68k_fix_adjustable (fixP)
944 fixS *fixP;
945{
36759679 946 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 947 switch (fixP->fx_r_type)
948 {
949 case BFD_RELOC_8_GOT_PCREL:
950 case BFD_RELOC_16_GOT_PCREL:
951 case BFD_RELOC_32_GOT_PCREL:
952 case BFD_RELOC_8_GOTOFF:
953 case BFD_RELOC_16_GOTOFF:
954 case BFD_RELOC_32_GOTOFF:
955 case BFD_RELOC_8_PLT_PCREL:
956 case BFD_RELOC_16_PLT_PCREL:
957 case BFD_RELOC_32_PLT_PCREL:
958 case BFD_RELOC_8_PLTOFF:
959 case BFD_RELOC_16_PLTOFF:
960 case BFD_RELOC_32_PLTOFF:
961 return 0;
962
963 case BFD_RELOC_VTABLE_INHERIT:
964 case BFD_RELOC_VTABLE_ENTRY:
965 return 0;
966
967 default:
968 return 1;
969 }
970}
971
972#else /* !OBJ_ELF */
973
974#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
975
c801568a
AM		 976#define relaxable_symbol(symbol) 1
977
252b5132
RH		 978#endif /* OBJ_ELF */
979
980#ifdef BFD_ASSEMBLER
981
982arelent *
983tc_gen_reloc (section, fixp)
f1f5ef86 984 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 985 fixS *fixp;
986{
987 arelent *reloc;
988 bfd_reloc_code_real_type code;
989
8ec6253e
NC		 990 /* If the tcbit is set, then this was a fixup of a negative value
991 that was never resolved. We do not have a reloc to handle this,
992 so just return. We assume that other code will have detected this
993 situation and produced a helpful error message, so we just tell the
994 user that the reloc cannot be produced. */
252b5132 995 if (fixp->fx_tcbit)
8ec6253e
NC		 996 {
997 if (fixp->fx_addsy)
b091f402
AM		 998 as_bad_where (fixp->fx_file, fixp->fx_line,
999 _("Unable to produce reloc against symbol '%s'"),
1000 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1001 return NULL;
1002 }
252b5132
RH		 1003
1004 if (fixp->fx_r_type != BFD_RELOC_NONE)
1005 {
1006 code = fixp->fx_r_type;
1007
1008 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1009 that fixup_segment converted a non-PC relative reloc into a
1010 PC relative reloc. In such a case, we need to convert the
1011 reloc code. */
1012 if (fixp->fx_pcrel)
1013 {
1014 switch (code)
1015 {
1016 case BFD_RELOC_8:
1017 code = BFD_RELOC_8_PCREL;
1018 break;
1019 case BFD_RELOC_16:
1020 code = BFD_RELOC_16_PCREL;
1021 break;
1022 case BFD_RELOC_32:
1023 code = BFD_RELOC_32_PCREL;
1024 break;
1025 case BFD_RELOC_8_PCREL:
1026 case BFD_RELOC_16_PCREL:
1027 case BFD_RELOC_32_PCREL:
1028 case BFD_RELOC_8_GOT_PCREL:
1029 case BFD_RELOC_16_GOT_PCREL:
1030 case BFD_RELOC_32_GOT_PCREL:
1031 case BFD_RELOC_8_GOTOFF:
1032 case BFD_RELOC_16_GOTOFF:
1033 case BFD_RELOC_32_GOTOFF:
1034 case BFD_RELOC_8_PLT_PCREL:
1035 case BFD_RELOC_16_PLT_PCREL:
1036 case BFD_RELOC_32_PLT_PCREL:
1037 case BFD_RELOC_8_PLTOFF:
1038 case BFD_RELOC_16_PLTOFF:
1039 case BFD_RELOC_32_PLTOFF:
1040 break;
1041 default:
1042 as_bad_where (fixp->fx_file, fixp->fx_line,
1043 _("Cannot make %s relocation PC relative"),
1044 bfd_get_reloc_code_name (code));
1045 }
1046 }
1047 }
1048 else
1049 {
1050#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1051 switch (F (fixp->fx_size, fixp->fx_pcrel))
1052 {
1053#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1054 MAP (1, 0, BFD_RELOC_8);
1055 MAP (2, 0, BFD_RELOC_16);
1056 MAP (4, 0, BFD_RELOC_32);
1057 MAP (1, 1, BFD_RELOC_8_PCREL);
1058 MAP (2, 1, BFD_RELOC_16_PCREL);
1059 MAP (4, 1, BFD_RELOC_32_PCREL);
1060 default:
1061 abort ();
1062 }
1063 }
1064#undef F
1065#undef MAP
1066
1067 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1068 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1069 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1070 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1071#ifndef OBJ_ELF
1072 if (fixp->fx_pcrel)
1073 reloc->addend = fixp->fx_addnumber;
1074 else
1075 reloc->addend = 0;
1076#else
1077 if (!fixp->fx_pcrel)
1078 reloc->addend = fixp->fx_addnumber;
1079 else
1080 reloc->addend = (section->vma
8390138c
AS		 1081 /* Explicit sign extension in case char is
1082 unsigned. */
1083 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1084 + fixp->fx_addnumber
1085 + md_pcrel_from (fixp));
1086#endif
1087
1088 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1089 assert (reloc->howto != 0);
1090
1091 return reloc;
1092}
1093
1094#endif /* BFD_ASSEMBLER */
1095
252b5132
RH		 1096/* Handle of the OPCODE hash table. NULL means any use before
1097 m68k_ip_begin() will crash. */
1098static struct hash_control *op_hash;
1099\f
1100/* Assemble an m68k instruction. */
1101
1102static void
1103m68k_ip (instring)
1104 char *instring;
1105{
1106 register char *p;
1107 register struct m68k_op *opP;
1108 register const struct m68k_incant *opcode;
1109 register const char *s;
1110 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1111 char *pdot, *pdotmove;
1112 enum m68k_size siz1, siz2;
1113 char c;
1114 int losing;
1115 int opsfound;
1116 LITTLENUM_TYPE words[6];
1117 LITTLENUM_TYPE *wordp;
1118 unsigned long ok_arch = 0;
1119
1120 if (*instring == ' ')
36759679 1121 instring++; /* Skip leading whitespace. */
252b5132
RH		 1122
1123 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1124 or exactly 1 space. */
252b5132
RH		 1125 pdot = 0;
1126 for (p = instring; *p != '\0'; p++)
1127 {
1128 if (*p == ' ')
1129 break;
1130 if (*p == '.')
1131 pdot = p;
1132 }
1133
1134 if (p == instring)
1135 {
1136 the_ins.error = _("No operator");
1137 return;
1138 }
1139
1140 /* p now points to the end of the opcode name, probably whitespace.
1141 Make sure the name is null terminated by clobbering the
1142 whitespace, look it up in the hash table, then fix it back.
1143 Remove a dot, first, since the opcode tables have none. */
1144 if (pdot != NULL)
1145 {
1146 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1147 *pdotmove = pdotmove[1];
1148 p--;
1149 }
1150
1151 c = *p;
1152 *p = '\0';
1153 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1154 *p = c;
1155
1156 if (pdot != NULL)
1157 {
1158 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1159 *pdotmove = pdotmove[-1];
1160 *pdot = '.';
1161 ++p;
1162 }
1163
1164 if (opcode == NULL)
1165 {
1166 the_ins.error = _("Unknown operator");
1167 return;
1168 }
1169
36759679 1170 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1171 while (*p == ' ')
1172 ++p;
1173
1174 if (opcode->m_operands == 0)
1175 {
1176 char *old = input_line_pointer;
1177 *old = '\n';
1178 input_line_pointer = p;
36759679 1179 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1180 mote_pseudo_table[opcode->m_opnum].poc_handler
1181 (mote_pseudo_table[opcode->m_opnum].poc_val);
1182 input_line_pointer = old;
1183 *old = 0;
1184
1185 return;
1186 }
1187
1188 if (flag_mri && opcode->m_opnum == 0)
1189 {
1190 /* In MRI mode, random garbage is allowed after an instruction
1191 which accepts no operands. */
1192 the_ins.args = opcode->m_operands;
1193 the_ins.numargs = opcode->m_opnum;
1194 the_ins.numo = opcode->m_codenum;
1195 the_ins.opcode[0] = getone (opcode);
1196 the_ins.opcode[1] = gettwo (opcode);
1197 return;
1198 }
1199
1200 for (opP = &the_ins.operands[0]; *p; opP++)
1201 {
1202 p = crack_operand (p, opP);
1203
1204 if (opP->error)
1205 {
1206 the_ins.error = opP->error;
1207 return;
1208 }
1209 }
1210
1211 opsfound = opP - &the_ins.operands[0];
1212
1213 /* This ugly hack is to support the floating pt opcodes in their
1214 standard form. Essentially, we fake a first enty of type COP#1 */
1215 if (opcode->m_operands[0] == 'I')
1216 {
1217 int n;
1218
1219 for (n = opsfound; n > 0; --n)
1220 the_ins.operands[n] = the_ins.operands[n - 1];
1221
1222 memset ((char *) (&the_ins.operands[0]), '\0',
1223 sizeof (the_ins.operands[0]));
1224 the_ins.operands[0].mode = CONTROL;
1225 the_ins.operands[0].reg = m68k_float_copnum;
1226 opsfound++;
1227 }
1228
36759679 1229 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1230 for (losing = 0;;)
1231 {
1232 /* If we didn't get the right number of ops, or we have no
92774660 1233 common model with this pattern then reject this pattern. */
252b5132
RH		 1234
1235 ok_arch |= opcode->m_arch;
1236 if (opsfound != opcode->m_opnum
1237 || ((opcode->m_arch & current_architecture) == 0))
1238 ++losing;
1239 else
1240 {
1241 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1242 *s && !losing;
1243 s += 2, opP++)
1244 {
1245 /* Warning: this switch is huge! */
1246 /* I've tried to organize the cases into this order:
1247 non-alpha first, then alpha by letter. Lower-case
1248 goes directly before uppercase counterpart. */
1249 /* Code with multiple case ...: gets sorted by the lowest
1250 case ... it belongs to. I hope this makes sense. */
1251 switch (*s)
1252 {
1253 case '!':
1254 switch (opP->mode)
1255 {
1256 case IMMED:
1257 case DREG:
1258 case AREG:
1259 case FPREG:
1260 case CONTROL:
1261 case AINC:
1262 case ADEC:
1263 case REGLST:
1264 losing++;
1265 break;
1266 default:
1267 break;
1268 }
1269 break;
1270
1271 case '<':
1272 switch (opP->mode)
1273 {
1274 case DREG:
1275 case AREG:
1276 case FPREG:
1277 case CONTROL:
1278 case IMMED:
1279 case ADEC:
1280 case REGLST:
1281 losing++;
1282 break;
1283 default:
1284 break;
1285 }
1286 break;
1287
1288 case '>':
1289 switch (opP->mode)
1290 {
1291 case DREG:
1292 case AREG:
1293 case FPREG:
1294 case CONTROL:
1295 case IMMED:
1296 case AINC:
1297 case REGLST:
1298 losing++;
1299 break;
1300 case ABSL:
1301 break;
1302 default:
1303 if (opP->reg == PC
1304 || opP->reg == ZPC)
1305 losing++;
1306 break;
1307 }
1308 break;
1309
1310 case 'm':
1311 switch (opP->mode)
1312 {
1313 case DREG:
1314 case AREG:
1315 case AINDR:
1316 case AINC:
1317 case ADEC:
1318 break;
1319 default:
1320 losing++;
1321 }
8a104df9 1322 break;
252b5132
RH		 1323
1324 case 'n':
1325 switch (opP->mode)
1326 {
1327 case DISP:
1328 break;
1329 default:
1330 losing++;
1331 }
8a104df9 1332 break;
252b5132
RH		 1333
1334 case 'o':
1335 switch (opP->mode)
1336 {
1337 case BASE:
1338 case ABSL:
1339 case IMMED:
1340 break;
1341 default:
1342 losing++;
1343 }
8a104df9 1344 break;
252b5132
RH		 1345
1346 case 'p':
1347 switch (opP->mode)
1348 {
1349 case DREG:
1350 case AREG:
1351 case AINDR:
1352 case AINC:
1353 case ADEC:
1354 break;
1355 case DISP:
1356 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1357 losing++;
252b5132
RH		 1358 break;
1359 default:
1360 losing++;
1361 }
8a104df9 1362 break;
252b5132
RH		 1363
1364 case 'q':
1365 switch (opP->mode)
1366 {
1367 case DREG:
1368 case AINDR:
1369 case AINC:
1370 case ADEC:
1371 break;
1372 case DISP:
1373 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1374 losing++;
252b5132
RH		 1375 break;
1376 default:
1377 losing++;
1378 break;
1379 }
8a104df9 1380 break;
252b5132
RH		 1381
1382 case 'v':
1383 switch (opP->mode)
1384 {
1385 case DREG:
1386 case AINDR:
1387 case AINC:
1388 case ADEC:
1389 case ABSL:
1390 break;
1391 case DISP:
1392 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1393 losing++;
252b5132
RH		 1394 break;
1395 default:
1396 losing++;
1397 break;
1398 }
1399 break;
1400
1401 case '#':
1402 if (opP->mode != IMMED)
1403 losing++;
1404 else if (s[1] == 'b'
1405 && ! isvar (&opP->disp)
1406 && (opP->disp.exp.X_op != O_constant
1407 || ! isbyte (opP->disp.exp.X_add_number)))
1408 losing++;
1409 else if (s[1] == 'B'
1410 && ! isvar (&opP->disp)
1411 && (opP->disp.exp.X_op != O_constant
1412 || ! issbyte (opP->disp.exp.X_add_number)))
1413 losing++;
1414 else if (s[1] == 'w'
1415 && ! isvar (&opP->disp)
1416 && (opP->disp.exp.X_op != O_constant
1417 || ! isword (opP->disp.exp.X_add_number)))
1418 losing++;
1419 else if (s[1] == 'W'
1420 && ! isvar (&opP->disp)
1421 && (opP->disp.exp.X_op != O_constant
1422 || ! issword (opP->disp.exp.X_add_number)))
1423 losing++;
1424 break;
1425
1426 case '^':
1427 case 'T':
1428 if (opP->mode != IMMED)
1429 losing++;
1430 break;
1431
1432 case '$':
1433 if (opP->mode == AREG
1434 || opP->mode == CONTROL
1435 || opP->mode == FPREG
1436 || opP->mode == IMMED
1437 || opP->mode == REGLST
1438 || (opP->mode != ABSL
1439 && (opP->reg == PC
1440 || opP->reg == ZPC)))
1441 losing++;
1442 break;
1443
1444 case '%':
1445 if (opP->mode == CONTROL
1446 || opP->mode == FPREG
1447 || opP->mode == REGLST
1448 || opP->mode == IMMED
1449 || (opP->mode != ABSL
1450 && (opP->reg == PC
1451 || opP->reg == ZPC)))
1452 losing++;
1453 break;
1454
1455 case '&':
1456 switch (opP->mode)
1457 {
1458 case DREG:
1459 case AREG:
1460 case FPREG:
1461 case CONTROL:
1462 case IMMED:
1463 case AINC:
1464 case ADEC:
1465 case REGLST:
1466 losing++;
1467 break;
1468 case ABSL:
1469 break;
1470 default:
1471 if (opP->reg == PC
1472 || opP->reg == ZPC)
1473 losing++;
1474 break;
1475 }
1476 break;
1477
1478 case '*':
1479 if (opP->mode == CONTROL
1480 || opP->mode == FPREG
1481 || opP->mode == REGLST)
1482 losing++;
1483 break;
1484
1485 case '+':
1486 if (opP->mode != AINC)
1487 losing++;
1488 break;
1489
1490 case '-':
1491 if (opP->mode != ADEC)
1492 losing++;
1493 break;
1494
1495 case '/':
1496 switch (opP->mode)
1497 {
1498 case AREG:
1499 case CONTROL:
1500 case FPREG:
1501 case AINC:
1502 case ADEC:
1503 case IMMED:
1504 case REGLST:
1505 losing++;
1506 break;
1507 default:
1508 break;
1509 }
1510 break;
1511
1512 case ';':
1513 switch (opP->mode)
1514 {
1515 case AREG:
1516 case CONTROL:
1517 case FPREG:
1518 case REGLST:
1519 losing++;
1520 break;
1521 default:
1522 break;
1523 }
1524 break;
1525
1526 case '?':
1527 switch (opP->mode)
1528 {
1529 case AREG:
1530 case CONTROL:
1531 case FPREG:
1532 case AINC:
1533 case ADEC:
1534 case IMMED:
1535 case REGLST:
1536 losing++;
1537 break;
1538 case ABSL:
1539 break;
1540 default:
1541 if (opP->reg == PC || opP->reg == ZPC)
1542 losing++;
1543 break;
1544 }
1545 break;
1546
1547 case '@':
1548 switch (opP->mode)
1549 {
1550 case AREG:
1551 case CONTROL:
1552 case FPREG:
1553 case IMMED:
1554 case REGLST:
1555 losing++;
1556 break;
1557 default:
1558 break;
1559 }
1560 break;
1561
1562 case '~': /* For now! (JF FOO is this right?) */
1563 switch (opP->mode)
1564 {
1565 case DREG:
1566 case AREG:
1567 case CONTROL:
1568 case FPREG:
1569 case IMMED:
1570 case REGLST:
1571 losing++;
1572 break;
1573 case ABSL:
1574 break;
1575 default:
1576 if (opP->reg == PC
1577 || opP->reg == ZPC)
1578 losing++;
1579 break;
1580 }
1581 break;
1582
1583 case '3':
1584 if (opP->mode != CONTROL
1585 || (opP->reg != TT0 && opP->reg != TT1))
1586 losing++;
1587 break;
1588
1589 case 'A':
1590 if (opP->mode != AREG)
1591 losing++;
1592 break;
1593
1594 case 'a':
1595 if (opP->mode != AINDR)
1596 ++losing;
1597 break;
1598
fd99574b
NC		 1599 case '4':
1600 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1601 && (opP->mode != DISP
1602 || opP->reg < ADDR0
1603 || opP->reg > ADDR7))
1604 ++losing;
1605 break;
1606
252b5132
RH		 1607 case 'B': /* FOO */
1608 if (opP->mode != ABSL
1609 || (flag_long_jumps
1610 && strncmp (instring, "jbsr", 4) == 0))
1611 losing++;
1612 break;
1613
3e602632
NC		 1614 case 'b':
1615 switch (opP->mode)
1616 {
1617 case IMMED:
1618 case ABSL:
1619 case AREG:
1620 case FPREG:
1621 case CONTROL:
1622 case POST:
1623 case PRE:
1624 case REGLST:
1625 losing++;
1626 break;
1627 default:
1628 break;
1629 }
1630 break;
1631
252b5132
RH		 1632 case 'C':
1633 if (opP->mode != CONTROL || opP->reg != CCR)
1634 losing++;
1635 break;
1636
1637 case 'd':
1638 if (opP->mode != DISP
1639 || opP->reg < ADDR0
1640 || opP->reg > ADDR7)
1641 losing++;
1642 break;
1643
1644 case 'D':
1645 if (opP->mode != DREG)
1646 losing++;
1647 break;
1648
6da466c7
ILT		 1649 case 'E':
1650 if (opP->reg != ACC)
1651 losing++;
1652 break;
1653
fd99574b
NC		 1654 case 'e':
1655 if (opP->reg != ACC && opP->reg != ACC1
1656 && opP->reg != ACC2 && opP->reg != ACC3)
1657 losing++;
1658 break;
1659
252b5132
RH		 1660 case 'F':
1661 if (opP->mode != FPREG)
1662 losing++;
1663 break;
1664
6da466c7
ILT		 1665 case 'G':
1666 if (opP->reg != MACSR)
1667 losing++;
1668 break;
1669
fd99574b
NC		 1670 case 'g':
1671 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1672 losing++;
1673 break;
1674
6da466c7
ILT		 1675 case 'H':
1676 if (opP->reg != MASK)
1677 losing++;
1678 break;
1679
252b5132
RH		 1680 case 'I':
1681 if (opP->mode != CONTROL
1682 || opP->reg < COP0
1683 || opP->reg > COP7)
1684 losing++;
1685 break;
1686
fd99574b
NC		 1687 case 'i':
1688 if (opP->mode != LSH && opP->mode != RSH)
1689 losing++;
1690 break;
1691
252b5132
RH		 1692 case 'J':
1693 if (opP->mode != CONTROL
1694 || opP->reg < USP
1695 || opP->reg > last_movec_reg)
1696 losing++;
1697 else
1698 {
1699 const enum m68k_register *rp;
1700 for (rp = control_regs; *rp; rp++)
1701 if (*rp == opP->reg)
1702 break;
1703 if (*rp == 0)
1704 losing++;
1705 }
1706 break;
1707
1708 case 'k':
1709 if (opP->mode != IMMED)
1710 losing++;
1711 break;
1712
1713 case 'l':
1714 case 'L':
1715 if (opP->mode == DREG
1716 || opP->mode == AREG
1717 || opP->mode == FPREG)
1718 {
1719 if (s[1] == '8')
1720 losing++;
1721 else
1722 {
1723 switch (opP->mode)
1724 {
1725 case DREG:
1726 opP->mask = 1 << (opP->reg - DATA0);
1727 break;
1728 case AREG:
1729 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1730 break;
1731 case FPREG:
1732 opP->mask = 1 << (opP->reg - FP0 + 16);
1733 break;
1734 default:
1735 abort ();
1736 }
1737 opP->mode = REGLST;
1738 }
1739 }
1740 else if (opP->mode == CONTROL)
1741 {
1742 if (s[1] != '8')
1743 losing++;
1744 else
1745 {
1746 switch (opP->reg)
1747 {
1748 case FPI:
1749 opP->mask = 1 << 24;
1750 break;
1751 case FPS:
1752 opP->mask = 1 << 25;
1753 break;
1754 case FPC:
1755 opP->mask = 1 << 26;
1756 break;
1757 default:
1758 losing++;
1759 break;
1760 }
1761 opP->mode = REGLST;
1762 }
1763 }
1764 else if (opP->mode != REGLST)
1765 losing++;
1766 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1767 losing++;
1768 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1769 losing++;
1770 break;
1771
1772 case 'M':
1773 if (opP->mode != IMMED)
1774 losing++;
1775 else if (opP->disp.exp.X_op != O_constant
1776 || ! issbyte (opP->disp.exp.X_add_number))
1777 losing++;
1778 else if (! m68k_quick
1779 && instring[3] != 'q'
1780 && instring[4] != 'q')
1781 losing++;
1782 break;
1783
1784 case 'O':
1785 if (opP->mode != DREG
1786 && opP->mode != IMMED
1787 && opP->mode != ABSL)
1788 losing++;
1789 break;
1790
1791 case 'Q':
1792 if (opP->mode != IMMED)
1793 losing++;
1794 else if (opP->disp.exp.X_op != O_constant
1795 || opP->disp.exp.X_add_number < 1
1796 || opP->disp.exp.X_add_number > 8)
1797 losing++;
1798 else if (! m68k_quick
1799 && (strncmp (instring, "add", 3) == 0
1800 || strncmp (instring, "sub", 3) == 0)
1801 && instring[3] != 'q')
1802 losing++;
1803 break;
1804
1805 case 'R':
1806 if (opP->mode != DREG && opP->mode != AREG)
1807 losing++;
1808 break;
1809
1810 case 'r':
1811 if (opP->mode != AINDR
1812 && (opP->mode != BASE
1813 || (opP->reg != 0
1814 && opP->reg != ZADDR0)
1815 || opP->disp.exp.X_op != O_absent
1816 || ((opP->index.reg < DATA0
1817 || opP->index.reg > DATA7)
1818 && (opP->index.reg < ADDR0
1819 || opP->index.reg > ADDR7))
1820 || opP->index.size != SIZE_UNSPEC
1821 || opP->index.scale != 1))
1822 losing++;
1823 break;
1824
1825 case 's':
1826 if (opP->mode != CONTROL
1827 || ! (opP->reg == FPI
1828 || opP->reg == FPS
1829 || opP->reg == FPC))
1830 losing++;
1831 break;
1832
1833 case 'S':
1834 if (opP->mode != CONTROL || opP->reg != SR)
1835 losing++;
1836 break;
1837
1838 case 't':
1839 if (opP->mode != IMMED)
1840 losing++;
1841 else if (opP->disp.exp.X_op != O_constant
1842 || opP->disp.exp.X_add_number < 0
1843 || opP->disp.exp.X_add_number > 7)
1844 losing++;
1845 break;
1846
1847 case 'U':
1848 if (opP->mode != CONTROL || opP->reg != USP)
1849 losing++;
1850 break;
1851
3e602632
NC		 1852 case 'x':
1853 if (opP->mode != IMMED)
1854 losing++;
1855 else if (opP->disp.exp.X_op != O_constant
1856 || opP->disp.exp.X_add_number < -1
1857 || opP->disp.exp.X_add_number > 7
1858 || opP->disp.exp.X_add_number == 0)
1859 losing++;
1860 break;
1861
252b5132
RH		 1862 /* JF these are out of order. We could put them
1863 in order if we were willing to put up with
1864 bunches of #ifdef m68851s in the code.
1865
1866 Don't forget that you need these operands
1867 to use 68030 MMU instructions. */
1868#ifndef NO_68851
36759679 1869 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1870 case '|':
1871 if (opP->mode == CONTROL
1872 || opP->mode == FPREG
1873 || opP->mode == DREG
1874 || opP->mode == AREG
1875 || opP->mode == REGLST)
1876 losing++;
1877 /* We should accept immediate operands, but they
1878 supposedly have to be quad word, and we don't
1879 handle that. I would like to see what a Motorola
1880 assembler does before doing something here. */
1881 if (opP->mode == IMMED)
1882 losing++;
1883 break;
1884
1885 case 'f':
1886 if (opP->mode != CONTROL
1887 || (opP->reg != SFC && opP->reg != DFC))
1888 losing++;
1889 break;
1890
1891 case '0':
1892 if (opP->mode != CONTROL || opP->reg != TC)
1893 losing++;
1894 break;
1895
1896 case '1':
1897 if (opP->mode != CONTROL || opP->reg != AC)
1898 losing++;
1899 break;
1900
1901 case '2':
1902 if (opP->mode != CONTROL
1903 || (opP->reg != CAL
1904 && opP->reg != VAL
1905 && opP->reg != SCC))
1906 losing++;
1907 break;
1908
1909 case 'V':
1910 if (opP->mode != CONTROL
1911 || opP->reg != VAL)
1912 losing++;
1913 break;
1914
1915 case 'W':
1916 if (opP->mode != CONTROL
1917 || (opP->reg != DRP
1918 && opP->reg != SRP
1919 && opP->reg != CRP))
1920 losing++;
1921 break;
1922
3e602632
NC		 1923 case 'w':
1924 switch (opP->mode)
1925 {
1926 case IMMED:
1927 case ABSL:
1928 case AREG:
1929 case DREG:
1930 case FPREG:
1931 case CONTROL:
1932 case POST:
1933 case PRE:
1934 case REGLST:
1935 losing++;
1936 break;
1937 default:
1938 break;
1939 }
1940 break;
1941
252b5132
RH		 1942 case 'X':
1943 if (opP->mode != CONTROL
1944 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1945 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1946 losing++;
1947 break;
1948
1949 case 'Y':
1950 if (opP->mode != CONTROL || opP->reg != PSR)
1951 losing++;
1952 break;
1953
1954 case 'Z':
1955 if (opP->mode != CONTROL || opP->reg != PCSR)
1956 losing++;
1957 break;
1958#endif
1959 case 'c':
1960 if (opP->mode != CONTROL
1961 || (opP->reg != NC
1962 && opP->reg != IC
1963 && opP->reg != DC
1964 && opP->reg != BC))
36759679 1965 losing++;
252b5132
RH		 1966 break;
1967
1968 case '_':
1969 if (opP->mode != ABSL)
1970 ++losing;
1971 break;
1972
6da466c7
ILT		 1973 case 'u':
1974 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1975 losing++;
1976 /* FIXME: kludge instead of fixing parser:
1977 upper/lower registers are *not* CONTROL
92774660 1978 registers, but ordinary ones. */
6da466c7
ILT		 1979 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1980 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1981 opP->mode = DREG;
1982 else
1983 opP->mode = AREG;
1984 break;
1985
3e602632
NC		 1986 case 'y':
1987 if (!(opP->mode == AINDR
1988 || (opP->mode == DISP && !(opP->reg == PC ||
1989 opP->reg == ZPC))))
1990 losing++;
1991 break;
1992
1993 case 'z':
1994 if (!(opP->mode == AINDR || opP->mode == DISP))
1995 losing++;
1996 break;
1997
252b5132
RH		 1998 default:
1999 abort ();
36759679 2000 }
252b5132
RH		 2001
2002 if (losing)
2003 break;
36759679
NC		 2004 }
2005 }
252b5132
RH		 2006
2007 if (!losing)
36759679 2008 break;
252b5132
RH		 2009
2010 opcode = opcode->m_next;
2011
2012 if (!opcode)
2013 {
2014 if (ok_arch
2015 && !(ok_arch & current_architecture))
2016 {
2017 char buf[200], *cp;
2018
6b6e92f4
NC		 2019 strncpy (buf,
2020 _("invalid instruction for this architecture; needs "), sizeof (buf));
252b5132
RH		 2021 cp = buf + strlen (buf);
2022 switch (ok_arch)
2023 {
6b6e92f4
NC		 2024 case mcfisa_a:
2025 strncpy (cp, _("ColdFire ISA_A"), (sizeof (buf) - (cp - buf)));
2026 cp += strlen (cp);
2027 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2028 cp += strlen (cp);
2029 break;
2030 case mcfhwdiv:
2031 strncpy (cp, _("ColdFire hardware divide"), (sizeof (buf) - (cp - buf)));
2032 cp += strlen (cp);
2033 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2034 cp += strlen (cp);
2035 break;
2036 case mcfisa_aa:
2037 strncpy (cp, _("ColdFire ISA_A+"), (sizeof (buf) - (cp - buf)));
2038 cp += strlen (cp);
2039 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2040 cp += strlen (cp);
2041 break;
2042 case mcfisa_b:
2043 strncpy (cp, _("ColdFire ISA_B"), (sizeof (buf) - (cp - buf)));
2044 cp += strlen (cp);
2045 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2046 cp += strlen (cp);
2047 break;
3e602632 2048 case cfloat:
6b6e92f4
NC		 2049 strncpy (cp, _("ColdFire fpu"), (sizeof (buf) - (cp - buf)));
2050 cp += strlen (cp);
2051 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2052 cp += strlen (cp);
3e602632 2053 break;
252b5132
RH		 2054 case mfloat:
2055 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2056 break;
2057 case mmmu:
2058 strcpy (cp, _("mmu (68030 or 68851)"));
2059 break;
2060 case m68020up:
2061 strcpy (cp, _("68020 or higher"));
2062 break;
2063 case m68000up:
2064 strcpy (cp, _("68000 or higher"));
2065 break;
2066 case m68010up:
2067 strcpy (cp, _("68010 or higher"));
2068 break;
2069 default:
2070 {
2071 int got_one = 0, idx;
6b6e92f4
NC		 2072
2073 for (idx = 0; idx < n_archs; idx++)
252b5132
RH		 2074 {
2075 if ((archs[idx].arch & ok_arch)
2076 && ! archs[idx].alias)
2077 {
2078 if (got_one)
2079 {
2080 strcpy (cp, " or ");
2081 cp += strlen (cp);
2082 }
2083 got_one = 1;
2084 strcpy (cp, archs[idx].name);
2085 cp += strlen (cp);
2086 }
2087 }
2088 }
2089 }
2090 cp = xmalloc (strlen (buf) + 1);
2091 strcpy (cp, buf);
2092 the_ins.error = cp;
2093 }
2094 else
2095 the_ins.error = _("operands mismatch");
2096 return;
36759679 2097 }
252b5132
RH		 2098
2099 losing = 0;
2100 }
2101
36759679 2102 /* Now assemble it. */
252b5132
RH		 2103 the_ins.args = opcode->m_operands;
2104 the_ins.numargs = opcode->m_opnum;
2105 the_ins.numo = opcode->m_codenum;
2106 the_ins.opcode[0] = getone (opcode);
2107 the_ins.opcode[1] = gettwo (opcode);
2108
2109 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2110 {
2111 /* This switch is a doozy.
2112 Watch the first step; its a big one! */
2113 switch (s[0])
2114 {
2115
2116 case '*':
2117 case '~':
2118 case '%':
2119 case ';':
2120 case '@':
2121 case '!':
2122 case '&':
2123 case '$':
2124 case '?':
2125 case '/':
2126 case '<':
2127 case '>':
3e602632 2128 case 'b':
252b5132
RH		 2129 case 'm':
2130 case 'n':
2131 case 'o':
2132 case 'p':
2133 case 'q':
2134 case 'v':
3e602632
NC		 2135 case 'w':
2136 case 'y':
2137 case 'z':
fd99574b 2138 case '4':
252b5132
RH		 2139#ifndef NO_68851
2140 case '|':
2141#endif
2142 switch (opP->mode)
2143 {
2144 case IMMED:
2145 tmpreg = 0x3c; /* 7.4 */
2146 if (strchr ("bwl", s[1]))
3e602632 2147 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2148 else
2149 nextword = get_num (&opP->disp, 0);
2150 if (isvar (&opP->disp))
2151 add_fix (s[1], &opP->disp, 0, 0);
2152 switch (s[1])
2153 {
2154 case 'b':
2155 if (!isbyte (nextword))
2156 opP->error = _("operand out of range");
2157 addword (nextword);
2158 baseo = 0;
2159 break;
2160 case 'w':
2161 if (!isword (nextword))
2162 opP->error = _("operand out of range");
2163 addword (nextword);
2164 baseo = 0;
2165 break;
2166 case 'W':
2167 if (!issword (nextword))
2168 opP->error = _("operand out of range");
2169 addword (nextword);
2170 baseo = 0;
2171 break;
2172 case 'l':
2173 addword (nextword >> 16);
2174 addword (nextword);
2175 baseo = 0;
2176 break;
2177
2178 case 'f':
2179 baseo = 2;
2180 outro = 8;
2181 break;
2182 case 'F':
2183 baseo = 4;
2184 outro = 11;
2185 break;
2186 case 'x':
2187 baseo = 6;
2188 outro = 15;
2189 break;
2190 case 'p':
2191 baseo = 6;
2192 outro = -1;
2193 break;
2194 default:
2195 abort ();
2196 }
2197 if (!baseo)
2198 break;
2199
36759679 2200 /* We gotta put out some float. */
252b5132
RH		 2201 if (op (&opP->disp) != O_big)
2202 {
2203 valueT val;
2204 int gencnt;
2205
2206 /* Can other cases happen here? */
2207 if (op (&opP->disp) != O_constant)
2208 abort ();
2209
2210 val = (valueT) offs (&opP->disp);
2211 gencnt = 0;
2212 do
2213 {
2214 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2215 val >>= LITTLENUM_NUMBER_OF_BITS;
2216 ++gencnt;
2217 }
2218 while (val != 0);
2219 offs (&opP->disp) = gencnt;
2220 }
2221 if (offs (&opP->disp) > 0)
2222 {
2223 if (offs (&opP->disp) > baseo)
2224 {
2225 as_warn (_("Bignum too big for %c format; truncated"),
2226 s[1]);
2227 offs (&opP->disp) = baseo;
2228 }
2229 baseo -= offs (&opP->disp);
2230 while (baseo--)
2231 addword (0);
2232 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2233 offs (&opP->disp)--;
2234 --wordp)
2235 addword (*wordp);
2236 break;
2237 }
2238 gen_to_words (words, baseo, (long) outro);
2239 for (wordp = words; baseo--; wordp++)
2240 addword (*wordp);
2241 break;
2242 case DREG:
2243 tmpreg = opP->reg - DATA; /* 0.dreg */
2244 break;
2245 case AREG:
2246 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2247 break;
2248 case AINDR:
2249 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2250 break;
2251 case ADEC:
2252 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2253 break;
2254 case AINC:
2255 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2256 break;
2257 case DISP:
2258
3e602632 2259 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2260
2261 if (opP->reg == PC
2262 && ! isvar (&opP->disp)
2263 && m68k_abspcadd)
2264 {
2265 opP->disp.exp.X_op = O_symbol;
2266#ifndef BFD_ASSEMBLER
2267 opP->disp.exp.X_add_symbol = &abs_symbol;
2268#else
2269 opP->disp.exp.X_add_symbol =
2270 section_symbol (absolute_section);
2271#endif
2272 }
2273
36759679 2274 /* Force into index mode. Hope this works. */
252b5132
RH		 2275
2276 /* We do the first bit for 32-bit displacements, and the
2277 second bit for 16 bit ones. It is possible that we
2278 should make the default be WORD instead of LONG, but
2279 I think that'd break GCC, so we put up with a little
2280 inefficiency for the sake of working output. */
2281
2282 if (!issword (nextword)
2283 || (isvar (&opP->disp)
2284 && ((opP->disp.size == SIZE_UNSPEC
2285 && flag_short_refs == 0
2286 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2287 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2288 || opP->disp.size == SIZE_LONG)))
2289 {
2290 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2291 || arch_coldfire_p (current_architecture))
252b5132
RH		 2292 opP->error =
2293 _("displacement too large for this architecture; needs 68020 or higher");
2294 if (opP->reg == PC)
2295 tmpreg = 0x3B; /* 7.3 */
2296 else
2297 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2298 if (isvar (&opP->disp))
2299 {
2300 if (opP->reg == PC)
2301 {
2302 if (opP->disp.size == SIZE_LONG
2303#ifdef OBJ_ELF
2304 /* If the displacement needs pic
2305 relocation it cannot be relaxed. */
2306 || opP->disp.pic_reloc != pic_none
2307#endif
2308 )
2309 {
2310 addword (0x0170);
2311 add_fix ('l', &opP->disp, 1, 2);
2312 }
2313 else
2314 {
2315 add_frag (adds (&opP->disp),
2316 offs (&opP->disp),
151337e8 2317 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2318 break;
2319 }
2320 }
2321 else
2322 {
2323 addword (0x0170);
2324 add_fix ('l', &opP->disp, 0, 0);
2325 }
2326 }
2327 else
2328 addword (0x0170);
2329 addword (nextword >> 16);
2330 }
2331 else
2332 {
2333 if (opP->reg == PC)
2334 tmpreg = 0x3A; /* 7.2 */
2335 else
2336 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2337
2338 if (isvar (&opP->disp))
2339 {
2340 if (opP->reg == PC)
2341 {
2342 add_fix ('w', &opP->disp, 1, 0);
2343 }
2344 else
2345 add_fix ('w', &opP->disp, 0, 0);
2346 }
2347 }
2348 addword (nextword);
2349 break;
2350
2351 case POST:
2352 case PRE:
2353 case BASE:
2354 nextword = 0;
3e602632 2355 baseo = get_num (&opP->disp, 90);
252b5132 2356 if (opP->mode == POST || opP->mode == PRE)
3e602632 2357 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2358 /* Figure out the `addressing mode'.
2359 Also turn on the BASE_DISABLE bit, if needed. */
2360 if (opP->reg == PC || opP->reg == ZPC)
2361 {
2362 tmpreg = 0x3b; /* 7.3 */
2363 if (opP->reg == ZPC)
2364 nextword |= 0x80;
2365 }
2366 else if (opP->reg == 0)
2367 {
2368 nextword |= 0x80;
2369 tmpreg = 0x30; /* 6.garbage */
2370 }
2371 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2372 {
2373 nextword |= 0x80;
2374 tmpreg = 0x30 + opP->reg - ZADDR0;
2375 }
2376 else
2377 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2378
2379 siz1 = opP->disp.size;
2380 if (opP->mode == POST || opP->mode == PRE)
2381 siz2 = opP->odisp.size;
2382 else
2383 siz2 = SIZE_UNSPEC;
2384
36759679 2385 /* Index register stuff. */
252b5132
RH		 2386 if (opP->index.reg != 0
2387 && opP->index.reg >= DATA
2388 && opP->index.reg <= ADDR7)
2389 {
2390 nextword |= (opP->index.reg - DATA) << 12;
2391
2392 if (opP->index.size == SIZE_LONG
2393 || (opP->index.size == SIZE_UNSPEC
2394 && m68k_index_width_default == SIZE_LONG))
2395 nextword |= 0x800;
2396
92774660 2397 if ((opP->index.scale != 1
252b5132 2398 && cpu_of_arch (current_architecture) < m68020)
92774660 2399 || (opP->index.scale == 8
3e602632 2400 && (arch_coldfire_p (current_architecture)
6b6e92f4 2401 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2402 {
2403 opP->error =
2404 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2405 }
2406
6da466c7
ILT		 2407 if (arch_coldfire_p (current_architecture)
2408 && opP->index.size == SIZE_WORD)
2409 opP->error = _("invalid index size for coldfire");
2410
252b5132
RH		 2411 switch (opP->index.scale)
2412 {
2413 case 1:
2414 break;
2415 case 2:
2416 nextword |= 0x200;
2417 break;
2418 case 4:
2419 nextword |= 0x400;
2420 break;
2421 case 8:
2422 nextword |= 0x600;
2423 break;
2424 default:
2425 abort ();
2426 }
2427 /* IF its simple,
2428 GET US OUT OF HERE! */
2429
2430 /* Must be INDEX, with an index register. Address
2431 register cannot be ZERO-PC, and either :b was
2432 forced, or we know it will fit. For a 68000 or
2433 68010, force this mode anyways, because the
2434 larger modes aren't supported. */
2435 if (opP->mode == BASE
2436 && ((opP->reg >= ADDR0
2437 && opP->reg <= ADDR7)
2438 || opP->reg == PC))
2439 {
2440 if (siz1 == SIZE_BYTE
2441 || cpu_of_arch (current_architecture) < m68020
6da466c7 2442 || arch_coldfire_p (current_architecture)
252b5132
RH		 2443 || (siz1 == SIZE_UNSPEC
2444 && ! isvar (&opP->disp)
2445 && issbyte (baseo)))
2446 {
2447 nextword += baseo & 0xff;
2448 addword (nextword);
2449 if (isvar (&opP->disp))
2450 {
2451 /* Do a byte relocation. If it doesn't
2452 fit (possible on m68000) let the
2453 fixup processing complain later. */
2454 if (opP->reg == PC)
2455 add_fix ('B', &opP->disp, 1, 1);
2456 else
2457 add_fix ('B', &opP->disp, 0, 0);
2458 }
2459 else if (siz1 != SIZE_BYTE)
2460 {
2461 if (siz1 != SIZE_UNSPEC)
2462 as_warn (_("Forcing byte displacement"));
2463 if (! issbyte (baseo))
2464 opP->error = _("byte displacement out of range");
2465 }
2466
2467 break;
2468 }
2469 else if (siz1 == SIZE_UNSPEC
2470 && opP->reg == PC
2471 && isvar (&opP->disp)
2472 && subs (&opP->disp) == NULL
2473#ifdef OBJ_ELF
2474 /* If the displacement needs pic
2475 relocation it cannot be relaxed. */
2476 && opP->disp.pic_reloc == pic_none
2477#endif
2478 )
2479 {
2480 /* The code in md_convert_frag_1 needs to be
2481 able to adjust nextword. Call frag_grow
2482 to ensure that we have enough space in
2483 the frag obstack to make all the bytes
2484 contiguous. */
2485 frag_grow (14);
8a104df9
KH		 2486 nextword += baseo & 0xff;
2487 addword (nextword);
2488 add_frag (adds (&opP->disp), offs (&opP->disp),
2489 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2490
2491 break;
8a104df9 2492 }
252b5132
RH		 2493 }
2494 }
2495 else
2496 {
36759679 2497 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2498 if (opP->index.reg >= ZDATA0
2499 && opP->index.reg <= ZDATA7)
2500 nextword |= (opP->index.reg - ZDATA0) << 12;
2501 else if (opP->index.reg >= ZADDR0
2502 || opP->index.reg <= ZADDR7)
2503 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2504 }
2505
2506 /* It isn't simple. */
2507
2508 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2509 || arch_coldfire_p (current_architecture))
252b5132
RH		 2510 opP->error =
2511 _("invalid operand mode for this architecture; needs 68020 or higher");
2512
2513 nextword |= 0x100;
2514 /* If the guy specified a width, we assume that it is
2515 wide enough. Maybe it isn't. If so, we lose. */
2516 switch (siz1)
2517 {
2518 case SIZE_UNSPEC:
2519 if (isvar (&opP->disp)
2520 ? m68k_rel32
2521 : ! issword (baseo))
2522 {
2523 siz1 = SIZE_LONG;
2524 nextword |= 0x30;
2525 }
2526 else if (! isvar (&opP->disp) && baseo == 0)
2527 nextword |= 0x10;
2528 else
2529 {
2530 nextword |= 0x20;
2531 siz1 = SIZE_WORD;
2532 }
2533 break;
2534 case SIZE_BYTE:
2535 as_warn (_(":b not permitted; defaulting to :w"));
2536 /* Fall through. */
2537 case SIZE_WORD:
2538 nextword |= 0x20;
2539 break;
2540 case SIZE_LONG:
2541 nextword |= 0x30;
2542 break;
2543 }
2544
67c1ffbe 2545 /* Figure out inner displacement stuff. */
252b5132
RH		 2546 if (opP->mode == POST || opP->mode == PRE)
2547 {
2548 if (cpu_of_arch (current_architecture) & cpu32)
2549 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2550 switch (siz2)
2551 {
2552 case SIZE_UNSPEC:
2553 if (isvar (&opP->odisp)
2554 ? m68k_rel32
2555 : ! issword (outro))
2556 {
2557 siz2 = SIZE_LONG;
2558 nextword |= 0x3;
2559 }
2560 else if (! isvar (&opP->odisp) && outro == 0)
2561 nextword |= 0x1;
2562 else
2563 {
2564 nextword |= 0x2;
2565 siz2 = SIZE_WORD;
2566 }
2567 break;
2568 case 1:
2569 as_warn (_(":b not permitted; defaulting to :w"));
2570 /* Fall through. */
2571 case 2:
2572 nextword |= 0x2;
2573 break;
2574 case 3:
2575 nextword |= 0x3;
2576 break;
2577 }
2578 if (opP->mode == POST
2579 && (nextword & 0x40) == 0)
2580 nextword |= 0x04;
2581 }
2582 addword (nextword);
2583
2584 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2585 {
2586 if (opP->reg == PC || opP->reg == ZPC)
2587 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2588 else
2589 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2590 }
2591 if (siz1 == SIZE_LONG)
2592 addword (baseo >> 16);
2593 if (siz1 != SIZE_UNSPEC)
2594 addword (baseo);
2595
2596 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2597 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2598 if (siz2 == SIZE_LONG)
2599 addword (outro >> 16);
2600 if (siz2 != SIZE_UNSPEC)
2601 addword (outro);
2602
2603 break;
2604
2605 case ABSL:
3e602632 2606 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2607 switch (opP->disp.size)
2608 {
2609 default:
2610 abort ();
2611 case SIZE_UNSPEC:
2612 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2613 {
2614 tmpreg = 0x38; /* 7.0 */
2615 addword (nextword);
2616 break;
2617 }
252b5132
RH		 2618 if (isvar (&opP->disp)
2619 && !subs (&opP->disp)
2620 && adds (&opP->disp)
2621#ifdef OBJ_ELF
2622 /* If the displacement needs pic relocation it
2623 cannot be relaxed. */
2624 && opP->disp.pic_reloc == pic_none
2625#endif
252b5132
RH		 2626 && !flag_long_jumps
2627 && !strchr ("~%&$?", s[0]))
2628 {
2629 tmpreg = 0x3A; /* 7.2 */
2630 add_frag (adds (&opP->disp),
2631 offs (&opP->disp),
151337e8 2632 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2633 break;
2634 }
36759679 2635 /* Fall through into long. */
252b5132
RH		 2636 case SIZE_LONG:
2637 if (isvar (&opP->disp))
2638 add_fix ('l', &opP->disp, 0, 0);
2639
2640 tmpreg = 0x39;/* 7.1 mode */
2641 addword (nextword >> 16);
2642 addword (nextword);
2643 break;
2644
2645 case SIZE_BYTE:
2646 as_bad (_("unsupported byte value; use a different suffix"));
2647 /* Fall through. */
36759679
NC		 2648
2649 case SIZE_WORD:
252b5132
RH		 2650 if (isvar (&opP->disp))
2651 add_fix ('w', &opP->disp, 0, 0);
2652
2653 tmpreg = 0x38;/* 7.0 mode */
2654 addword (nextword);
2655 break;
2656 }
2657 break;
2658 case CONTROL:
2659 case FPREG:
2660 default:
2661 as_bad (_("unknown/incorrect operand"));
bc805888 2662 /* abort (); */
252b5132 2663 }
fd99574b
NC		 2664
2665 /* If s[0] is '4', then this is for the mac instructions
2666 that can have a trailing_ampersand set. If so, set 0x100
2667 bit on tmpreg so install_gen_operand can check for it and
2668 set the appropriate bit (word2, bit 5). */
2669 if (s[0] == '4')
2670 {
2671 if (opP->trailing_ampersand)
2672 tmpreg |= 0x100;
2673 }
252b5132
RH		 2674 install_gen_operand (s[1], tmpreg);
2675 break;
2676
2677 case '#':
2678 case '^':
2679 switch (s[1])
2680 { /* JF: I hate floating point! */
2681 case 'j':
2682 tmpreg = 70;
2683 break;
2684 case '8':
2685 tmpreg = 20;
2686 break;
2687 case 'C':
2688 tmpreg = 50;
2689 break;
2690 case '3':
2691 default:
3e602632 2692 tmpreg = 90;
252b5132
RH		 2693 break;
2694 }
2695 tmpreg = get_num (&opP->disp, tmpreg);
2696 if (isvar (&opP->disp))
2697 add_fix (s[1], &opP->disp, 0, 0);
2698 switch (s[1])
2699 {
2700 case 'b': /* Danger: These do no check for
2701 certain types of overflow.
2702 user beware! */
2703 if (!isbyte (tmpreg))
2704 opP->error = _("out of range");
2705 insop (tmpreg, opcode);
2706 if (isvar (&opP->disp))
2707 the_ins.reloc[the_ins.nrel - 1].n =
2708 (opcode->m_codenum) * 2 + 1;
2709 break;
2710 case 'B':
2711 if (!issbyte (tmpreg))
2712 opP->error = _("out of range");
2713 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2714 if (isvar (&opP->disp))
2715 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2716 break;
2717 case 'w':
2718 if (!isword (tmpreg))
2719 opP->error = _("out of range");
2720 insop (tmpreg, opcode);
2721 if (isvar (&opP->disp))
2722 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2723 break;
2724 case 'W':
2725 if (!issword (tmpreg))
2726 opP->error = _("out of range");
2727 insop (tmpreg, opcode);
2728 if (isvar (&opP->disp))
2729 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2730 break;
2731 case 'l':
2732 /* Because of the way insop works, we put these two out
2733 backwards. */
2734 insop (tmpreg, opcode);
2735 insop (tmpreg >> 16, opcode);
2736 if (isvar (&opP->disp))
2737 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2738 break;
2739 case '3':
2740 tmpreg &= 0xFF;
2741 case '8':
2742 case 'C':
2743 case 'j':
2744 install_operand (s[1], tmpreg);
2745 break;
2746 default:
2747 abort ();
2748 }
2749 break;
2750
2751 case '+':
2752 case '-':
2753 case 'A':
2754 case 'a':
2755 install_operand (s[1], opP->reg - ADDR);
2756 break;
2757
2758 case 'B':
3e602632 2759 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2760 switch (s[1])
2761 {
2762 case 'B':
8390138c 2763 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2764 break;
2765 case 'W':
2766 add_fix ('w', &opP->disp, 1, 0);
2767 addword (0);
2768 break;
2769 case 'L':
2770 long_branch:
151337e8 2771 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2772 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2773 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2774 add_fix ('l', &opP->disp, 1, 0);
2775 addword (0);
2776 addword (0);
2777 break;
2778 case 'g':
36759679 2779 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2780 goto long_branch;
2781
2782#ifdef OBJ_ELF
2783 /* If the displacement needs pic relocation it cannot be
2784 relaxed. */
2785 if (opP->disp.pic_reloc != pic_none)
2786 goto long_branch;
2787#endif
252b5132 2788 /* This could either be a symbol, or an absolute
151337e8
NC		 2789 address. If it's an absolute address, turn it into
2790 an absolute jump right here and keep it out of the
2791 relaxer. */
2792 if (adds (&opP->disp) == 0)
2793 {
2794 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2795 the_ins.opcode[0] = 0x4EF9;
151337e8 2796 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2797 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2798 else /* jCC */
2799 {
2800 the_ins.opcode[0] ^= 0x0100;
2801 the_ins.opcode[0] |= 0x0006;
18566f55 2802 addword (0x4EF9);
151337e8
NC		 2803 }
2804 add_fix ('l', &opP->disp, 0, 0);
2805 addword (0);
2806 addword (0);
2807 break;
2808 }
2809
2810 /* Now we know it's going into the relaxer. Now figure
2811 out which mode. We try in this order of preference:
2812 long branch, absolute jump, byte/word branches only. */
2813 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2814 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2815 TAB (BRANCHBWL, SZ_UNDEF));
2816 else if (! flag_keep_pcrel)
2817 {
2818 if ((the_ins.opcode[0] == 0x6000)
2819 || (the_ins.opcode[0] == 0x6100))
2820 add_frag (adds (&opP->disp), offs (&opP->disp),
2821 TAB (BRABSJUNC, SZ_UNDEF));
2822 else
2823 add_frag (adds (&opP->disp), offs (&opP->disp),
2824 TAB (BRABSJCOND, SZ_UNDEF));
2825 }
252b5132
RH		 2826 else
2827 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2828 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2829 break;
2830 case 'w':
2831 if (isvar (&opP->disp))
2832 {
151337e8
NC		 2833 /* Check for DBcc instructions. We can relax them,
2834 but only if we have long branches and/or absolute
2835 jumps. */
2836 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2837 && (HAVE_LONG_BRANCH (current_architecture)
2838 || (! flag_keep_pcrel)))
252b5132 2839 {
151337e8
NC		 2840 if (HAVE_LONG_BRANCH (current_architecture))
2841 add_frag (adds (&opP->disp), offs (&opP->disp),
2842 TAB (DBCCLBR, SZ_UNDEF));
2843 else
2844 add_frag (adds (&opP->disp), offs (&opP->disp),
2845 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2846 break;
2847 }
252b5132
RH		 2848 add_fix ('w', &opP->disp, 1, 0);
2849 }
2850 addword (0);
2851 break;
36759679 2852 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2853 add_fix ('l', &opP->disp, 1, 0);
2854 addword (0);
2855 addword (0);
2856 break;
36759679 2857 case 'c': /* Var size Coprocesssor branches. */
151337e8 2858 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2859 {
252b5132
RH		 2860 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2861 add_fix ('l', &opP->disp, 1, 0);
2862 addword (0);
2863 addword (0);
2864 }
151337e8
NC		 2865 else
2866 add_frag (adds (&opP->disp), offs (&opP->disp),
2867 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2868 break;
2869 default:
2870 abort ();
2871 }
2872 break;
2873
36759679 2874 case 'C': /* Ignore it. */
252b5132
RH		 2875 break;
2876
36759679 2877 case 'd': /* JF this is a kludge. */
252b5132 2878 install_operand ('s', opP->reg - ADDR);
3e602632 2879 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2880 if (!issword (tmpreg))
2881 {
2882 as_warn (_("Expression out of range, using 0"));
2883 tmpreg = 0;
2884 }
2885 addword (tmpreg);
2886 break;
2887
2888 case 'D':
2889 install_operand (s[1], opP->reg - DATA);
2890 break;
2891
fd99574b
NC		 2892 case 'e': /* EMAC ACCx, reg/reg. */
2893 install_operand (s[1], opP->reg - ACC);
2894 break;
2895
36759679 2896 case 'E': /* Ignore it. */
6da466c7
ILT		 2897 break;
2898
252b5132
RH		 2899 case 'F':
2900 install_operand (s[1], opP->reg - FP0);
2901 break;
2902
fd99574b
NC		 2903 case 'g': /* EMAC ACCEXTx. */
2904 install_operand (s[1], opP->reg - ACCEXT01);
2905 break;
2906
36759679 2907 case 'G': /* Ignore it. */
6da466c7
ILT		 2908 case 'H':
2909 break;
2910
252b5132
RH		 2911 case 'I':
2912 tmpreg = opP->reg - COP0;
2913 install_operand (s[1], tmpreg);
2914 break;
2915
fd99574b
NC		 2916 case 'i': /* MAC/EMAC scale factor. */
2917 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2918 break;
2919
36759679 2920 case 'J': /* JF foo. */
252b5132
RH		 2921 switch (opP->reg)
2922 {
2923 case SFC:
2924 tmpreg = 0x000;
2925 break;
2926 case DFC:
2927 tmpreg = 0x001;
2928 break;
2929 case CACR:
2930 tmpreg = 0x002;
2931 break;
2932 case TC:
2933 tmpreg = 0x003;
2934 break;
3e602632 2935 case ACR0:
252b5132
RH		 2936 case ITT0:
2937 tmpreg = 0x004;
2938 break;
3e602632 2939 case ACR1:
252b5132
RH		 2940 case ITT1:
2941 tmpreg = 0x005;
2942 break;
3e602632 2943 case ACR2:
252b5132
RH		 2944 case DTT0:
2945 tmpreg = 0x006;
2946 break;
3e602632 2947 case ACR3:
252b5132
RH		 2948 case DTT1:
2949 tmpreg = 0x007;
2950 break;
2951 case BUSCR:
2952 tmpreg = 0x008;
2953 break;
2954
2955 case USP:
2956 tmpreg = 0x800;
2957 break;
2958 case VBR:
2959 tmpreg = 0x801;
2960 break;
2961 case CAAR:
2962 tmpreg = 0x802;
2963 break;
2964 case MSP:
2965 tmpreg = 0x803;
2966 break;
2967 case ISP:
2968 tmpreg = 0x804;
2969 break;
2970 case MMUSR:
2971 tmpreg = 0x805;
2972 break;
2973 case URP:
2974 tmpreg = 0x806;
2975 break;
2976 case SRP:
2977 tmpreg = 0x807;
2978 break;
2979 case PCR:
2980 tmpreg = 0x808;
2981 break;
2982 case ROMBAR:
2983 tmpreg = 0xC00;
2984 break;
3e602632
NC		 2985 case ROMBAR1:
2986 tmpreg = 0xC01;
2987 break;
2988 case FLASHBAR:
252b5132
RH		 2989 case RAMBAR0:
2990 tmpreg = 0xC04;
2991 break;
3e602632 2992 case RAMBAR:
252b5132
RH		 2993 case RAMBAR1:
2994 tmpreg = 0xC05;
2995 break;
3e602632
NC		 2996 case MPCR:
2997 tmpreg = 0xC0C;
2998 break;
2999 case EDRAMBAR:
3000 tmpreg = 0xC0D;
3001 break;
3002 case MBAR0:
3003 case SECMBAR:
3004 tmpreg = 0xC0E;
3005 break;
3006 case MBAR1:
252b5132
RH		 3007 case MBAR:
3008 tmpreg = 0xC0F;
3009 break;
3e602632
NC		 3010 case PCR1U0:
3011 tmpreg = 0xD02;
3012 break;
3013 case PCR1L0:
3014 tmpreg = 0xD03;
3015 break;
3016 case PCR2U0:
3017 tmpreg = 0xD04;
3018 break;
3019 case PCR2L0:
3020 tmpreg = 0xD05;
3021 break;
3022 case PCR3U0:
3023 tmpreg = 0xD06;
3024 break;
3025 case PCR3L0:
3026 tmpreg = 0xD07;
3027 break;
3028 case PCR1L1:
3029 tmpreg = 0xD0A;
3030 break;
3031 case PCR1U1:
3032 tmpreg = 0xD0B;
3033 break;
3034 case PCR2L1:
3035 tmpreg = 0xD0C;
3036 break;
3037 case PCR2U1:
3038 tmpreg = 0xD0D;
3039 break;
3040 case PCR3L1:
3041 tmpreg = 0xD0E;
3042 break;
3043 case PCR3U1:
3044 tmpreg = 0xD0F;
3045 break;
252b5132
RH		 3046 default:
3047 abort ();
3048 }
3049 install_operand (s[1], tmpreg);
3050 break;
3051
3052 case 'k':
3053 tmpreg = get_num (&opP->disp, 55);
3054 install_operand (s[1], tmpreg & 0x7f);
3055 break;
3056
3057 case 'l':
3058 tmpreg = opP->mask;
3059 if (s[1] == 'w')
3060 {
3061 if (tmpreg & 0x7FF0000)
3062 as_bad (_("Floating point register in register list"));
3063 insop (reverse_16_bits (tmpreg), opcode);
3064 }
3065 else
3066 {
3067 if (tmpreg & 0x700FFFF)
3068 as_bad (_("Wrong register in floating-point reglist"));
3069 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3070 }
3071 break;
3072
3073 case 'L':
3074 tmpreg = opP->mask;
3075 if (s[1] == 'w')
3076 {
3077 if (tmpreg & 0x7FF0000)
3078 as_bad (_("Floating point register in register list"));
3079 insop (tmpreg, opcode);
3080 }
3081 else if (s[1] == '8')
3082 {
3083 if (tmpreg & 0x0FFFFFF)
3084 as_bad (_("incorrect register in reglist"));
3085 install_operand (s[1], tmpreg >> 24);
3086 }
3087 else
3088 {
3089 if (tmpreg & 0x700FFFF)
3090 as_bad (_("wrong register in floating-point reglist"));
3091 else
3092 install_operand (s[1], tmpreg >> 16);
3093 }
3094 break;
3095
3096 case 'M':
3097 install_operand (s[1], get_num (&opP->disp, 60));
3098 break;
3099
3100 case 'O':
3101 tmpreg = ((opP->mode == DREG)
8fce3f5e 3102 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3103 : (get_num (&opP->disp, 40) & 0x1F));
3104 install_operand (s[1], tmpreg);
3105 break;
3106
3107 case 'Q':
3108 tmpreg = get_num (&opP->disp, 10);
3109 if (tmpreg == 8)
3110 tmpreg = 0;
3111 install_operand (s[1], tmpreg);
3112 break;
3113
3114 case 'R':
3115 /* This depends on the fact that ADDR registers are eight
3116 more than their corresponding DATA regs, so the result
36759679 3117 will have the ADDR_REG bit set. */
252b5132
RH		 3118 install_operand (s[1], opP->reg - DATA);
3119 break;
3120
3121 case 'r':
3122 if (opP->mode == AINDR)
3123 install_operand (s[1], opP->reg - DATA);
3124 else
3125 install_operand (s[1], opP->index.reg - DATA);
3126 break;
3127
3128 case 's':
3129 if (opP->reg == FPI)
3130 tmpreg = 0x1;
3131 else if (opP->reg == FPS)
3132 tmpreg = 0x2;
3133 else if (opP->reg == FPC)
3134 tmpreg = 0x4;
3135 else
3136 abort ();
3137 install_operand (s[1], tmpreg);
3138 break;
3139
36759679 3140 case 'S': /* Ignore it. */
252b5132
RH		 3141 break;
3142
3143 case 'T':
3144 install_operand (s[1], get_num (&opP->disp, 30));
3145 break;
3146
36759679 3147 case 'U': /* Ignore it. */
252b5132
RH		 3148 break;
3149
3150 case 'c':
3151 switch (opP->reg)
3152 {
3153 case NC:
3154 tmpreg = 0;
3155 break;
3156 case DC:
3157 tmpreg = 1;
3158 break;
3159 case IC:
3160 tmpreg = 2;
3161 break;
3162 case BC:
3163 tmpreg = 3;
3164 break;
3165 default:
3166 as_fatal (_("failed sanity check"));
36759679 3167 } /* switch on cache token. */
252b5132
RH		 3168 install_operand (s[1], tmpreg);
3169 break;
3170#ifndef NO_68851
92774660 3171 /* JF: These are out of order, I fear. */
252b5132
RH		 3172 case 'f':
3173 switch (opP->reg)
3174 {
3175 case SFC:
3176 tmpreg = 0;
3177 break;
3178 case DFC:
3179 tmpreg = 1;
3180 break;
3181 default:
3182 abort ();
3183 }
3184 install_operand (s[1], tmpreg);
3185 break;
3186
3187 case '0':
3188 case '1':
3189 case '2':
3190 switch (opP->reg)
3191 {
3192 case TC:
3193 tmpreg = 0;
3194 break;
3195 case CAL:
3196 tmpreg = 4;
3197 break;
3198 case VAL:
3199 tmpreg = 5;
3200 break;
3201 case SCC:
3202 tmpreg = 6;
3203 break;
3204 case AC:
3205 tmpreg = 7;
3206 break;
3207 default:
3208 abort ();
3209 }
3210 install_operand (s[1], tmpreg);
3211 break;
3212
3213 case 'V':
3214 if (opP->reg == VAL)
3215 break;
3216 abort ();
3217
3218 case 'W':
3219 switch (opP->reg)
3220 {
3221 case DRP:
3222 tmpreg = 1;
3223 break;
3224 case SRP:
3225 tmpreg = 2;
3226 break;
3227 case CRP:
3228 tmpreg = 3;
3229 break;
3230 default:
3231 abort ();
3232 }
3233 install_operand (s[1], tmpreg);
3234 break;
3235
3236 case 'X':
3237 switch (opP->reg)
3238 {
3239 case BAD:
3240 case BAD + 1:
3241 case BAD + 2:
3242 case BAD + 3:
3243 case BAD + 4:
3244 case BAD + 5:
3245 case BAD + 6:
3246 case BAD + 7:
3247 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3248 break;
3249
3250 case BAC:
3251 case BAC + 1:
3252 case BAC + 2:
3253 case BAC + 3:
3254 case BAC + 4:
3255 case BAC + 5:
3256 case BAC + 6:
3257 case BAC + 7:
3258 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3259 break;
3260
3261 default:
3262 abort ();
3263 }
3264 install_operand (s[1], tmpreg);
3265 break;
3266 case 'Y':
3267 know (opP->reg == PSR);
3268 break;
3269 case 'Z':
3270 know (opP->reg == PCSR);
3271 break;
3272#endif /* m68851 */
3273 case '3':
3274 switch (opP->reg)
3275 {
3276 case TT0:
3277 tmpreg = 2;
3278 break;
3279 case TT1:
3280 tmpreg = 3;
3281 break;
3282 default:
3283 abort ();
3284 }
3285 install_operand (s[1], tmpreg);
3286 break;
3287 case 't':
3288 tmpreg = get_num (&opP->disp, 20);
3289 install_operand (s[1], tmpreg);
3290 break;
36759679 3291 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3292 if (isvar (&opP->disp))
3293 add_fix ('l', &opP->disp, 0, 0);
3e602632 3294 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3295 addword (tmpreg >> 16);
3296 addword (tmpreg & 0xFFFF);
3297 break;
6da466c7
ILT		 3298 case 'u':
3299 install_operand (s[1], opP->reg - DATA0L);
3300 opP->reg -= (DATA0L);
36759679 3301 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3302 break;
3e602632
NC		 3303 case 'x':
3304 tmpreg = get_num (&opP->disp, 80);
3305 if (tmpreg == -1)
3306 tmpreg = 0;
3307 install_operand (s[1], tmpreg);
3308 break;
252b5132
RH		 3309 default:
3310 abort ();
3311 }
3312 }
3313
3314 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3315 instruction, ready to be emitted. . . */
252b5132
RH		 3316}
3317
3318static int
3319reverse_16_bits (in)
3320 int in;
3321{
3322 int out = 0;
3323 int n;
3324
3325 static int mask[16] =
3326 {
3327 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3328 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3329 };
3330 for (n = 0; n < 16; n++)
3331 {
3332 if (in & mask[n])
3333 out |= mask[15 - n];
3334 }
3335 return out;
3336} /* reverse_16_bits() */
3337
3338static int
3339reverse_8_bits (in)
3340 int in;
3341{
3342 int out = 0;
3343 int n;
3344
3345 static int mask[8] =
3346 {
3347 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3348 };
3349
3350 for (n = 0; n < 8; n++)
3351 {
3352 if (in & mask[n])
3353 out |= mask[7 - n];
3354 }
3355 return out;
3356} /* reverse_8_bits() */
3357
3358/* Cause an extra frag to be generated here, inserting up to 10 bytes
3359 (that value is chosen in the frag_var call in md_assemble). TYPE
3360 is the subtype of the frag to be generated; its primary type is
3361 rs_machine_dependent.
3362
3363 The TYPE parameter is also used by md_convert_frag_1 and
3364 md_estimate_size_before_relax. The appropriate type of fixup will
3365 be emitted by md_convert_frag_1.
3366
3367 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3368static void
3369install_operand (mode, val)
3370 int mode;
3371 int val;
3372{
3373 switch (mode)
3374 {
3375 case 's':
36759679 3376 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3377 break;
3378 case 'd':
3379 the_ins.opcode[0] |= val << 9;
3380 break;
3381 case '1':
3382 the_ins.opcode[1] |= val << 12;
3383 break;
3384 case '2':
3385 the_ins.opcode[1] |= val << 6;
3386 break;
3387 case '3':
3388 the_ins.opcode[1] |= val;
3389 break;
3390 case '4':
3391 the_ins.opcode[2] |= val << 12;
3392 break;
3393 case '5':
3394 the_ins.opcode[2] |= val << 6;
3395 break;
3396 case '6':
3397 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3398 three words long! */
3399 the_ins.numo++;
3400 the_ins.opcode[2] |= val;
3401 break;
3402 case '7':
3403 the_ins.opcode[1] |= val << 7;
3404 break;
3405 case '8':
3406 the_ins.opcode[1] |= val << 10;
3407 break;
3408#ifndef NO_68851
3409 case '9':
3410 the_ins.opcode[1] |= val << 5;
3411 break;
3412#endif
3413
3414 case 't':
3415 the_ins.opcode[1] |= (val << 10) | (val << 7);
3416 break;
3417 case 'D':
3418 the_ins.opcode[1] |= (val << 12) | val;
3419 break;
3420 case 'g':
3421 the_ins.opcode[0] |= val = 0xff;
3422 break;
3423 case 'i':
3424 the_ins.opcode[0] |= val << 9;
3425 break;
3426 case 'C':
3427 the_ins.opcode[1] |= val;
3428 break;
3429 case 'j':
3430 the_ins.opcode[1] |= val;
36759679 3431 the_ins.numo++; /* What a hack. */
252b5132
RH		 3432 break;
3433 case 'k':
3434 the_ins.opcode[1] |= val << 4;
3435 break;
3436 case 'b':
3437 case 'w':
3438 case 'W':
3439 case 'l':
3440 break;
3441 case 'e':
3442 the_ins.opcode[0] |= (val << 6);
3443 break;
3444 case 'L':
3445 the_ins.opcode[1] = (val >> 16);
3446 the_ins.opcode[2] = val & 0xffff;
3447 break;
6da466c7
ILT		 3448 case 'm':
3449 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3450 the_ins.opcode[0] |= ((val & 0x7) << 9);
3451 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3452 break;
fd99574b 3453 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3454 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3455 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3456 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3457 break;
fd99574b 3458 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3459 the_ins.opcode[1] |= val << 12;
3460 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3461 break;
fd99574b 3462 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3463 the_ins.opcode[0] |= (val & 0xF);
3464 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3465 break;
fd99574b 3466 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3467 the_ins.opcode[1] |= (val & 0xF);
3468 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3469 break;
3470 case 'h':
3471 the_ins.opcode[1] |= ((val != 1) << 10);
3472 break;
fd99574b
NC		 3473 case 'F':
3474 the_ins.opcode[0] |= ((val & 0x3) << 9);
3475 break;
3476 case 'f':
3477 the_ins.opcode[0] |= ((val & 0x3) << 0);
3478 break;
3479 case 'G':
3480 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3481 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3482 break;
3483 case 'H':
3484 the_ins.opcode[0] |= ((val & 0x1) << 7);
3485 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3486 break;
3487 case 'I':
3488 the_ins.opcode[1] |= ((val & 0x3) << 9);
3489 break;
3490 case ']':
3491 the_ins.opcode[0] |= (val & 0x1) <<10;
3492 break;
252b5132
RH		 3493 case 'c':
3494 default:
3495 as_fatal (_("failed sanity check."));
3496 }
6b6e92f4 3497}
252b5132
RH		 3498
3499static void
3500install_gen_operand (mode, val)
3501 int mode;
3502 int val;
3503{
3504 switch (mode)
3505 {
fd99574b
NC		 3506 case '/': /* Special for mask loads for mac/msac insns with
3507 possible mask; trailing_ampersend set in bit 8. */
3508 the_ins.opcode[0] |= (val & 0x3f);
3509 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3510 break;
252b5132
RH		 3511 case 's':
3512 the_ins.opcode[0] |= val;
3513 break;
3514 case 'd':
3515 /* This is a kludge!!! */
3516 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3517 break;
3518 case 'b':
3519 case 'w':
3520 case 'l':
3521 case 'f':
3522 case 'F':
3523 case 'x':
3524 case 'p':
3525 the_ins.opcode[0] |= val;
3526 break;
36759679 3527 /* more stuff goes here. */
252b5132
RH		 3528 default:
3529 as_fatal (_("failed sanity check."));
3530 }
6b6e92f4 3531}
252b5132 3532
6b6e92f4
NC		 3533/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3534 then deal with the bitfield hack. */
252b5132
RH		 3535
3536static char *
3537crack_operand (str, opP)
3538 register char *str;
3539 register struct m68k_op *opP;
3540{
3541 register int parens;
3542 register int c;
3543 register char *beg_str;
3544 int inquote = 0;
3545
3546 if (!str)
3547 {
3548 return str;
3549 }
3550 beg_str = str;
3551 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3552 {
3553 if (! inquote)
3554 {
3555 if (*str == '(')
3556 parens++;
3557 else if (*str == ')')
3558 {
3559 if (!parens)
36759679 3560 { /* ERROR. */
252b5132
RH		 3561 opP->error = _("Extra )");
3562 return str;
3563 }
3564 --parens;
3565 }
3566 }
3567 if (flag_mri && *str == '\'')
3568 inquote = ! inquote;
3569 }
3570 if (!*str && parens)
36759679 3571 { /* ERROR. */
252b5132
RH		 3572 opP->error = _("Missing )");
3573 return str;
3574 }
3575 c = *str;
3576 *str = '\0';
3577 if (m68k_ip_op (beg_str, opP) != 0)
3578 {
3579 *str = c;
3580 return str;
3581 }
3582 *str = c;
3583 if (c == '}')
36759679 3584 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3585 if (c)
3586 {
3587 c = *++str;
3588 if (!c)
3589 as_bad (_("Missing operand"));
3590 }
3591
3592 /* Detect MRI REG symbols and convert them to REGLSTs. */
3593 if (opP->mode == CONTROL && (int)opP->reg < 0)
3594 {
3595 opP->mode = REGLST;
3596 opP->mask = ~(int)opP->reg;
3597 opP->reg = 0;
3598 }
3599
3600 return str;
3601}
3602
3603/* This is the guts of the machine-dependent assembler. STR points to a
3604 machine dependent instruction. This function is supposed to emit
3605 the frags/bytes it assembles to.
3606 */
3607
3608static void
3609insert_reg (regname, regnum)
3610 const char *regname;
3611 int regnum;
3612{
3613 char buf[100];
3614 int i;
3615
3616#ifdef REGISTER_PREFIX
3617 if (!flag_reg_prefix_optional)
3618 {
3619 buf[0] = REGISTER_PREFIX;
3620 strcpy (buf + 1, regname);
3621 regname = buf;
3622 }
3623#endif
3624
3625 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3626 &zero_address_frag));
3627
3628 for (i = 0; regname[i]; i++)
3882b010 3629 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3630 buf[i] = '\0';
3631
3632 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3633 &zero_address_frag));
3634}
3635
3636struct init_entry
3637 {
3638 const char *name;
3639 int number;
3640 };
3641
3642static const struct init_entry init_table[] =
3643{
3644 { "d0", DATA0 },
3645 { "d1", DATA1 },
3646 { "d2", DATA2 },
3647 { "d3", DATA3 },
3648 { "d4", DATA4 },
3649 { "d5", DATA5 },
3650 { "d6", DATA6 },
3651 { "d7", DATA7 },
3652 { "a0", ADDR0 },
3653 { "a1", ADDR1 },
3654 { "a2", ADDR2 },
3655 { "a3", ADDR3 },
3656 { "a4", ADDR4 },
3657 { "a5", ADDR5 },
3658 { "a6", ADDR6 },
3659 { "fp", ADDR6 },
3660 { "a7", ADDR7 },
3661 { "sp", ADDR7 },
3662 { "ssp", ADDR7 },
3663 { "fp0", FP0 },
3664 { "fp1", FP1 },
3665 { "fp2", FP2 },
3666 { "fp3", FP3 },
3667 { "fp4", FP4 },
3668 { "fp5", FP5 },
3669 { "fp6", FP6 },
3670 { "fp7", FP7 },
3671 { "fpi", FPI },
3672 { "fpiar", FPI },
3673 { "fpc", FPI },
3674 { "fps", FPS },
3675 { "fpsr", FPS },
3676 { "fpc", FPC },
3677 { "fpcr", FPC },
3678 { "control", FPC },
3679 { "status", FPS },
3680 { "iaddr", FPI },
3681
3682 { "cop0", COP0 },
3683 { "cop1", COP1 },
3684 { "cop2", COP2 },
3685 { "cop3", COP3 },
3686 { "cop4", COP4 },
3687 { "cop5", COP5 },
3688 { "cop6", COP6 },
3689 { "cop7", COP7 },
3690 { "pc", PC },
3691 { "zpc", ZPC },
3692 { "sr", SR },
3693
3694 { "ccr", CCR },
3695 { "cc", CCR },
3696
6da466c7 3697 { "acc", ACC },
fd99574b
NC		 3698 { "acc0", ACC },
3699 { "acc1", ACC1 },
3700 { "acc2", ACC2 },
3701 { "acc3", ACC3 },
3702 { "accext01", ACCEXT01 },
3703 { "accext23", ACCEXT23 },
6da466c7
ILT		 3704 { "macsr", MACSR },
3705 { "mask", MASK },
3706
36759679
NC		 3707 /* Control registers. */
3708 { "sfc", SFC }, /* Source Function Code. */
252b5132 3709 { "sfcr", SFC },
36759679 3710 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3711 { "dfcr", DFC },
36759679
NC		 3712 { "cacr", CACR }, /* Cache Control Register. */
3713 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3714
36759679
NC		 3715 { "usp", USP }, /* User Stack Pointer. */
3716 { "vbr", VBR }, /* Vector Base Register. */
3717 { "msp", MSP }, /* Master Stack Pointer. */
3718 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3719
36759679
NC		 3720 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3721 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3722 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3723 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3724
3725 /* 68ec040 versions of same */
36759679
NC		 3726 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3727 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3728 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3729 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3730
3731 /* mcf5200 versions of same. The ColdFire programmer's reference
3732 manual indicated that the order is 2,3,0,1, but Ken Rose
3733 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3734 { "acr0", ACR0 }, /* Access Control Unit 0. */
3735 { "acr1", ACR1 }, /* Access Control Unit 1. */
3736 { "acr2", ACR2 }, /* Access Control Unit 2. */
3737 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3738
36759679 3739 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3740 { "tcr", TC },
3741
36759679
NC		 3742 { "mmusr", MMUSR }, /* MMU Status Register. */
3743 { "srp", SRP }, /* User Root Pointer. */
3744 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3745
3746 { "buscr", BUSCR },
3747 { "pcr", PCR },
3748
36759679
NC		 3749 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3750 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3751 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3752 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3753
3754 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3755 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3756 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3757 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3758 { "mpcr", MPCR }, /* mcfv4e registers. */
3759 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3760 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3761 { "asid", TC }, /* mcfv4e registers. */
3762 { "mmubar", BUSCR }, /* mcfv4e registers. */
3763 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3764 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3765 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3766 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3767 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3768 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3769 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3770 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3771 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3772 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3773 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3774 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3775
3776 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3777 { "rambar", RAMBAR }, /* mcf528x registers. */
36759679 3778 /* End of control registers. */
252b5132
RH		 3779
3780 { "ac", AC },
3781 { "bc", BC },
3782 { "cal", CAL },
3783 { "crp", CRP },
3784 { "drp", DRP },
3785 { "pcsr", PCSR },
3786 { "psr", PSR },
3787 { "scc", SCC },
3788 { "val", VAL },
3789 { "bad0", BAD0 },
3790 { "bad1", BAD1 },
3791 { "bad2", BAD2 },
3792 { "bad3", BAD3 },
3793 { "bad4", BAD4 },
3794 { "bad5", BAD5 },
3795 { "bad6", BAD6 },
3796 { "bad7", BAD7 },
3797 { "bac0", BAC0 },
3798 { "bac1", BAC1 },
3799 { "bac2", BAC2 },
3800 { "bac3", BAC3 },
3801 { "bac4", BAC4 },
3802 { "bac5", BAC5 },
3803 { "bac6", BAC6 },
3804 { "bac7", BAC7 },
3805
3806 { "ic", IC },
3807 { "dc", DC },
3808 { "nc", NC },
3809
3810 { "tt0", TT0 },
3811 { "tt1", TT1 },
36759679 3812 /* 68ec030 versions of same. */
252b5132
RH		 3813 { "ac0", TT0 },
3814 { "ac1", TT1 },
36759679 3815 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3816 { "acusr", PSR },
3817
3818 /* Suppressed data and address registers. */
3819 { "zd0", ZDATA0 },
3820 { "zd1", ZDATA1 },
3821 { "zd2", ZDATA2 },
3822 { "zd3", ZDATA3 },
3823 { "zd4", ZDATA4 },
3824 { "zd5", ZDATA5 },
3825 { "zd6", ZDATA6 },
3826 { "zd7", ZDATA7 },
3827 { "za0", ZADDR0 },
3828 { "za1", ZADDR1 },
3829 { "za2", ZADDR2 },
3830 { "za3", ZADDR3 },
3831 { "za4", ZADDR4 },
3832 { "za5", ZADDR5 },
3833 { "za6", ZADDR6 },
3834 { "za7", ZADDR7 },
3835
92774660 3836 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3837 { "d0l", DATA0L },
3838 { "d1l", DATA1L },
3839 { "d2l", DATA2L },
3840 { "d3l", DATA3L },
3841 { "d4l", DATA4L },
3842 { "d5l", DATA5L },
3843 { "d6l", DATA6L },
3844 { "d7l", DATA7L },
3845
3846 { "a0l", ADDR0L },
3847 { "a1l", ADDR1L },
3848 { "a2l", ADDR2L },
3849 { "a3l", ADDR3L },
3850 { "a4l", ADDR4L },
3851 { "a5l", ADDR5L },
3852 { "a6l", ADDR6L },
3853 { "a7l", ADDR7L },
3854
3855 { "d0u", DATA0U },
3856 { "d1u", DATA1U },
3857 { "d2u", DATA2U },
3858 { "d3u", DATA3U },
3859 { "d4u", DATA4U },
3860 { "d5u", DATA5U },
3861 { "d6u", DATA6U },
3862 { "d7u", DATA7U },
3863
3864 { "a0u", ADDR0U },
3865 { "a1u", ADDR1U },
3866 { "a2u", ADDR2U },
3867 { "a3u", ADDR3U },
3868 { "a4u", ADDR4U },
3869 { "a5u", ADDR5U },
3870 { "a6u", ADDR6U },
3871 { "a7u", ADDR7U },
3872
252b5132
RH		 3873 { 0, 0 }
3874};
3875
3876static void
3877init_regtable ()
3878{
3879 int i;
3880 for (i = 0; init_table[i].name; i++)
3881 insert_reg (init_table[i].name, init_table[i].number);
3882}
3883
3884static int no_68851, no_68881;
3885
3886#ifdef OBJ_AOUT
3887/* a.out machine type. Default to 68020. */
3888int m68k_aout_machtype = 2;
3889#endif
3890
3891void
3892md_assemble (str)
3893 char *str;
3894{
3895 const char *er;
3896 short *fromP;
3897 char *toP = NULL;
3898 int m, n = 0;
3899 char *to_beg_P;
3900 int shorts_this_frag;
3901 fixS *fixP;
3902
3903 /* In MRI mode, the instruction and operands are separated by a
3904 space. Anything following the operands is a comment. The label
3905 has already been removed. */
3906 if (flag_mri)
3907 {
3908 char *s;
3909 int fields = 0;
3910 int infield = 0;
3911 int inquote = 0;
3912
3913 for (s = str; *s != '\0'; s++)
3914 {
3915 if ((*s == ' ' || *s == '\t') && ! inquote)
3916 {
3917 if (infield)
3918 {
3919 ++fields;
3920 if (fields >= 2)
3921 {
3922 *s = '\0';
3923 break;
3924 }
3925 infield = 0;
3926 }
3927 }
3928 else
3929 {
3930 if (! infield)
3931 infield = 1;
3932 if (*s == '\'')
3933 inquote = ! inquote;
3934 }
3935 }
3936 }
3937
3938 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3939 m68k_ip (str);
3940 er = the_ins.error;
3941 if (!er)
3942 {
3943 for (n = 0; n < the_ins.numargs; n++)
3944 if (the_ins.operands[n].error)
3945 {
3946 er = the_ins.operands[n].error;
3947 break;
3948 }
3949 }
3950 if (er)
3951 {
3952 as_bad (_("%s -- statement `%s' ignored"), er, str);
3953 return;
3954 }
3955
3956 /* If there is a current label, record that it marks an instruction. */
3957 if (current_label != NULL)
3958 {
3959 current_label->text = 1;
3960 current_label = NULL;
3961 }
3962
f27a3839
AS		 3963#ifdef OBJ_ELF
3964 /* Tie dwarf2 debug info to the address at the start of the insn. */
3965 dwarf2_emit_insn (0);
3966#endif
3967
252b5132
RH		 3968 if (the_ins.nfrag == 0)
3969 {
36759679 3970 /* No frag hacking involved; just put it out. */
252b5132
RH		 3971 toP = frag_more (2 * the_ins.numo);
3972 fromP = &the_ins.opcode[0];
3973 for (m = the_ins.numo; m; --m)
3974 {
3975 md_number_to_chars (toP, (long) (*fromP), 2);
3976 toP += 2;
3977 fromP++;
3978 }
36759679 3979 /* Put out symbol-dependent info. */
252b5132
RH		 3980 for (m = 0; m < the_ins.nrel; m++)
3981 {
3982 switch (the_ins.reloc[m].wid)
3983 {
3984 case 'B':
3985 n = 1;
3986 break;
3987 case 'b':
3988 n = 1;
3989 break;
3990 case '3':
3991 n = 1;
3992 break;
3993 case 'w':
3994 case 'W':
3995 n = 2;
3996 break;
3997 case 'l':
3998 n = 4;
3999 break;
4000 default:
4001 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4002 the_ins.reloc[m].wid);
4003 }
4004
4005 fixP = fix_new_exp (frag_now,
4006 ((toP - frag_now->fr_literal)
4007 - the_ins.numo * 2 + the_ins.reloc[m].n),
4008 n,
4009 &the_ins.reloc[m].exp,
4010 the_ins.reloc[m].pcrel,
4011 get_reloc_code (n, the_ins.reloc[m].pcrel,
4012 the_ins.reloc[m].pic_reloc));
4013 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4014 if (the_ins.reloc[m].wid == 'B')
4015 fixP->fx_signed = 1;
4016 }
4017 return;
4018 }
4019
36759679 4020 /* There's some frag hacking. */
fbe572f9
AM		 4021 {
4022 /* Calculate the max frag size. */
4023 int wid;
4024
4025 wid = 2 * the_ins.fragb[0].fragoff;
4026 for (n = 1; n < the_ins.nfrag; n++)
4027 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4028 /* frag_var part. */
4029 wid += 10;
4030 /* Make sure the whole insn fits in one chunk, in particular that
4031 the var part is attached, as we access one byte before the
4032 variable frag for byte branches. */
4033 frag_grow (wid);
4034 }
4035
252b5132
RH		 4036 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4037 {
4038 int wid;
4039
4040 if (n == 0)
4041 wid = 2 * the_ins.fragb[n].fragoff;
4042 else
4043 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4044 toP = frag_more (wid);
4045 to_beg_P = toP;
4046 shorts_this_frag = 0;
4047 for (m = wid / 2; m; --m)
4048 {
4049 md_number_to_chars (toP, (long) (*fromP), 2);
4050 toP += 2;
4051 fromP++;
4052 shorts_this_frag++;
4053 }
4054 for (m = 0; m < the_ins.nrel; m++)
4055 {
4056 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4057 {
4058 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4059 break;
4060 }
4061 wid = the_ins.reloc[m].wid;
4062 if (wid == 0)
4063 continue;
4064 the_ins.reloc[m].wid = 0;
4065 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4066
4067 fixP = fix_new_exp (frag_now,
4068 ((toP - frag_now->fr_literal)
4069 - the_ins.numo * 2 + the_ins.reloc[m].n),
4070 wid,
4071 &the_ins.reloc[m].exp,
4072 the_ins.reloc[m].pcrel,
4073 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4074 the_ins.reloc[m].pic_reloc));
4075 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4076 }
4077 (void) frag_var (rs_machine_dependent, 10, 0,
4078 (relax_substateT) (the_ins.fragb[n].fragty),
4079 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4080 }
4081 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4082 shorts_this_frag = 0;
4083 if (n)
4084 {
4085 toP = frag_more (n * sizeof (short));
4086 while (n--)
4087 {
4088 md_number_to_chars (toP, (long) (*fromP), 2);
4089 toP += 2;
4090 fromP++;
4091 shorts_this_frag++;
4092 }
4093 }
4094 for (m = 0; m < the_ins.nrel; m++)
4095 {
4096 int wid;
4097
4098 wid = the_ins.reloc[m].wid;
4099 if (wid == 0)
4100 continue;
4101 the_ins.reloc[m].wid = 0;
4102 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4103
4104 fixP = fix_new_exp (frag_now,
4105 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4106 - shorts_this_frag * 2),
4107 wid,
4108 &the_ins.reloc[m].exp,
4109 the_ins.reloc[m].pcrel,
4110 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4111 the_ins.reloc[m].pic_reloc));
4112 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4113 }
4114}
4115
4116void
4117md_begin ()
4118{
4119 /*
4120 * md_begin -- set up hash tables with 68000 instructions.
4121 * similar to what the vax assembler does. ---phr
4122 */
4123 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4124 a copy of it at runtime, adding in the information we want but isn't
4125 there. I think it'd be better to have an awk script hack the table
4126 at compile time. Or even just xstr the table and use it as-is. But
4127 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4128 names. */
4129
94f592af
NC		 4130 const struct m68k_opcode *ins;
4131 struct m68k_incant *hack, *slak;
36759679 4132 const char *retval = 0; /* Empty string, or error msg text. */
94f592af 4133 int i;
252b5132
RH		 4134
4135 if (flag_mri)
4136 {
4137 flag_reg_prefix_optional = 1;
4138 m68k_abspcadd = 1;
4139 if (! m68k_rel32_from_cmdline)
4140 m68k_rel32 = 0;
4141 }
4142
4143 op_hash = hash_new ();
4144
4145 obstack_begin (&robyn, 4000);
4146 for (i = 0; i < m68k_numopcodes; i++)
4147 {
4148 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4149 do
4150 {
4151 ins = &m68k_opcodes[i];
4152 /* We *could* ignore insns that don't match our arch here
92774660 4153 but just leaving them out of the hash. */
252b5132
RH		 4154 slak->m_operands = ins->args;
4155 slak->m_opnum = strlen (slak->m_operands) / 2;
4156 slak->m_arch = ins->arch;
4157 slak->m_opcode = ins->opcode;
36759679 4158 /* This is kludgey. */
252b5132
RH		 4159 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4160 if (i + 1 != m68k_numopcodes
4161 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
4162 {
4163 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4164 i++;
4165 }
4166 else
4167 slak->m_next = 0;
4168 slak = slak->m_next;
4169 }
4170 while (slak);
4171
4172 retval = hash_insert (op_hash, ins->name, (char *) hack);
4173 if (retval)
4174 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4175 }
4176
4177 for (i = 0; i < m68k_numaliases; i++)
4178 {
4179 const char *name = m68k_opcode_aliases[i].primary;
4180 const char *alias = m68k_opcode_aliases[i].alias;
4181 PTR val = hash_find (op_hash, name);
4182 if (!val)
4183 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4184 retval = hash_insert (op_hash, alias, val);
4185 if (retval)
4186 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4187 }
4188
4189 /* In MRI mode, all unsized branches are variable sized. Normally,
4190 they are word sized. */
4191 if (flag_mri)
4192 {
4193 static struct m68k_opcode_alias mri_aliases[] =
4194 {
4195 { "bhi", "jhi", },
4196 { "bls", "jls", },
4197 { "bcc", "jcc", },
4198 { "bcs", "jcs", },
4199 { "bne", "jne", },
4200 { "beq", "jeq", },
4201 { "bvc", "jvc", },
4202 { "bvs", "jvs", },
4203 { "bpl", "jpl", },
4204 { "bmi", "jmi", },
4205 { "bge", "jge", },
4206 { "blt", "jlt", },
4207 { "bgt", "jgt", },
4208 { "ble", "jle", },
4209 { "bra", "jra", },
4210 { "bsr", "jbsr", },
4211 };
4212
8fce3f5e
AM		 4213 for (i = 0;
4214 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4215 i++)
252b5132
RH		 4216 {
4217 const char *name = mri_aliases[i].primary;
4218 const char *alias = mri_aliases[i].alias;
4219 PTR val = hash_find (op_hash, name);
4220 if (!val)
4221 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4222 retval = hash_jam (op_hash, alias, val);
4223 if (retval)
4224 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4225 }
4226 }
4227
8fce3f5e 4228 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4229 {
4230 notend_table[i] = 0;
4231 alt_notend_table[i] = 0;
4232 }
4233 notend_table[','] = 1;
4234 notend_table['{'] = 1;
4235 notend_table['}'] = 1;
4236 alt_notend_table['a'] = 1;
4237 alt_notend_table['A'] = 1;
4238 alt_notend_table['d'] = 1;
4239 alt_notend_table['D'] = 1;
4240 alt_notend_table['#'] = 1;
4241 alt_notend_table['&'] = 1;
4242 alt_notend_table['f'] = 1;
4243 alt_notend_table['F'] = 1;
4244#ifdef REGISTER_PREFIX
4245 alt_notend_table[REGISTER_PREFIX] = 1;
4246#endif
4247
4248 /* We need to put '(' in alt_notend_table to handle
4249 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
4250 */
4251 alt_notend_table['('] = 1;
4252
4253 /* We need to put '@' in alt_notend_table to handle
4254 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
4255 */
4256 alt_notend_table['@'] = 1;
4257
4258 /* We need to put digits in alt_notend_table to handle
4259 bfextu %d0{24:1},%d0
4260 */
4261 alt_notend_table['0'] = 1;
4262 alt_notend_table['1'] = 1;
4263 alt_notend_table['2'] = 1;
4264 alt_notend_table['3'] = 1;
4265 alt_notend_table['4'] = 1;
4266 alt_notend_table['5'] = 1;
4267 alt_notend_table['6'] = 1;
4268 alt_notend_table['7'] = 1;
4269 alt_notend_table['8'] = 1;
4270 alt_notend_table['9'] = 1;
4271
4272#ifndef MIT_SYNTAX_ONLY
4273 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4274 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4275 {
4276 int n = 0;
4277 while (mote_pseudo_table[n].poc_name)
4278 {
4279 hack = (struct m68k_incant *)
4280 obstack_alloc (&robyn, sizeof (struct m68k_incant));
4281 hash_insert (op_hash,
4282 mote_pseudo_table[n].poc_name, (char *) hack);
4283 hack->m_operands = 0;
4284 hack->m_opnum = n;
4285 n++;
4286 }
4287 }
4288#endif
4289
4290 init_regtable ();
4291
4292#ifdef OBJ_ELF
4293 record_alignment (text_section, 2);
4294 record_alignment (data_section, 2);
4295 record_alignment (bss_section, 2);
4296#endif
4297}
4298
4299static void
4300select_control_regs ()
4301{
4302 /* Note which set of "movec" control registers is available. */
6b6e92f4 4303 switch (current_chip)
252b5132 4304 {
4f2a7c9e 4305 case 0:
6b6e92f4
NC		 4306 if (verbose)
4307 as_warn (_("architecture not yet selected: defaulting to 68020"));
4f2a7c9e
NC		 4308 control_regs = m68020_control_regs;
4309 break;
4310
252b5132
RH		 4311 case m68000:
4312 control_regs = m68000_control_regs;
4313 break;
4314 case m68010:
4315 control_regs = m68010_control_regs;
4316 break;
4317 case m68020:
4318 case m68030:
4319 control_regs = m68020_control_regs;
4320 break;
4321 case m68040:
4322 control_regs = m68040_control_regs;
4323 break;
4324 case m68060:
4325 control_regs = m68060_control_regs;
4326 break;
4327 case cpu32:
4328 control_regs = cpu32_control_regs;
4329 break;
4330 case mcf5200:
6da466c7
ILT		 4331 case mcf5206e:
4332 case mcf5307:
dc84e067 4333 case mcf5407:
6da466c7 4334 control_regs = mcf_control_regs;
252b5132 4335 break;
3e602632 4336 case mcf528x:
6b6e92f4 4337 case mcf521x:
3e602632
NC		 4338 control_regs = mcf528x_control_regs;
4339 break;
6b6e92f4
NC		 4340 case mcf5470:
4341 case mcf5480:
3e602632
NC		 4342 control_regs = mcfv4e_control_regs;
4343 break;
252b5132
RH		 4344 default:
4345 abort ();
4346 }
4347}
4348
4349void
4350m68k_init_after_args ()
4351{
4352 if (cpu_of_arch (current_architecture) == 0)
4353 {
4354 int i;
4355 const char *default_cpu = TARGET_CPU;
4356
4357 if (*default_cpu == 'm')
4358 default_cpu++;
4359 for (i = 0; i < n_archs; i++)
4360 if (strcasecmp (default_cpu, archs[i].name) == 0)
4361 break;
4362 if (i == n_archs)
4363 {
4364 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4365 current_architecture |= m68020;
4366 }
4367 else
4368 current_architecture |= archs[i].arch;
4369 }
4370 /* Permit m68881 specification with all cpus; those that can't work
4371 with a coprocessor could be doing emulation. */
4372 if (current_architecture & m68851)
4373 {
4374 if (current_architecture & m68040)
4375 {
4376 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4377 }
4378 }
4379 /* What other incompatibilities could we check for? */
4380
4381 /* Toss in some default assumptions about coprocessors. */
4382 if (!no_68881
4383 && (cpu_of_arch (current_architecture)
4384 /* Can CPU32 have a 68881 coprocessor?? */
4385 & (m68020 | m68030 | cpu32)))
4386 {
4387 current_architecture |= m68881;
4388 }
4389 if (!no_68851
4390 && (cpu_of_arch (current_architecture) & m68020up) != 0
4391 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4392 {
4393 current_architecture |= m68851;
4394 }
4395 if (no_68881 && (current_architecture & m68881))
4396 as_bad (_("options for 68881 and no-68881 both given"));
4397 if (no_68851 && (current_architecture & m68851))
4398 as_bad (_("options for 68851 and no-68851 both given"));
4399
4400#ifdef OBJ_AOUT
4401 /* Work out the magic number. This isn't very general. */
4402 if (current_architecture & m68000)
4403 m68k_aout_machtype = 0;
4404 else if (current_architecture & m68010)
4405 m68k_aout_machtype = 1;
4406 else if (current_architecture & m68020)
4407 m68k_aout_machtype = 2;
4408 else
4409 m68k_aout_machtype = 2;
4410#endif
4411
4412 /* Note which set of "movec" control registers is available. */
4413 select_control_regs ();
4414
4415 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4416 || arch_coldfire_p (current_architecture))
252b5132
RH		 4417 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4418}
4419\f
4420/* This is called when a label is defined. */
4421
4422void
4423m68k_frob_label (sym)
4424 symbolS *sym;
4425{
4426 struct label_line *n;
4427
4428 n = (struct label_line *) xmalloc (sizeof *n);
4429 n->next = labels;
4430 n->label = sym;
4431 as_where (&n->file, &n->line);
4432 n->text = 0;
4433 labels = n;
4434 current_label = n;
4435}
4436
4437/* This is called when a value that is not an instruction is emitted. */
4438
4439void
4440m68k_flush_pending_output ()
4441{
4442 current_label = NULL;
4443}
4444
4445/* This is called at the end of the assembly, when the final value of
4446 the label is known. We warn if this is a text symbol aligned at an
4447 odd location. */
4448
4449void
4450m68k_frob_symbol (sym)
4451 symbolS *sym;
4452{
4453 if (S_GET_SEGMENT (sym) == reg_section
4454 && (int) S_GET_VALUE (sym) < 0)
4455 {
4456 S_SET_SEGMENT (sym, absolute_section);
4457 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4458 }
4459 else if ((S_GET_VALUE (sym) & 1) != 0)
4460 {
4461 struct label_line *l;
4462
4463 for (l = labels; l != NULL; l = l->next)
4464 {
4465 if (l->label == sym)
4466 {
4467 if (l->text)
4468 as_warn_where (l->file, l->line,
4469 _("text label `%s' aligned to odd boundary"),
4470 S_GET_NAME (sym));
4471 break;
4472 }
4473 }
4474 }
4475}
4476\f
4477/* This is called if we go in or out of MRI mode because of the .mri
4478 pseudo-op. */
4479
4480void
4481m68k_mri_mode_change (on)
4482 int on;
4483{
4484 if (on)
4485 {
4486 if (! flag_reg_prefix_optional)
4487 {
4488 flag_reg_prefix_optional = 1;
4489#ifdef REGISTER_PREFIX
4490 init_regtable ();
4491#endif
4492 }
4493 m68k_abspcadd = 1;
4494 if (! m68k_rel32_from_cmdline)
4495 m68k_rel32 = 0;
4496 }
4497 else
4498 {
4499 if (! reg_prefix_optional_seen)
4500 {
4501#ifdef REGISTER_PREFIX_OPTIONAL
4502 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4503#else
4504 flag_reg_prefix_optional = 0;
4505#endif
4506#ifdef REGISTER_PREFIX
4507 init_regtable ();
4508#endif
4509 }
4510 m68k_abspcadd = 0;
4511 if (! m68k_rel32_from_cmdline)
4512 m68k_rel32 = 1;
4513 }
4514}
4515
36759679 4516/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4517#define MAX_LITTLENUMS 6
4518
4519/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4520 of type TYPE, and store the appropriate bytes in *LITP. The number
4521 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4522 returned, or NULL on OK. */
4523
4524char *
4525md_atof (type, litP, sizeP)
4526 char type;
4527 char *litP;
4528 int *sizeP;
4529{
4530 int prec;
4531 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4532 LITTLENUM_TYPE *wordP;
4533 char *t;
4534
4535 switch (type)
4536 {
4537 case 'f':
4538 case 'F':
4539 case 's':
4540 case 'S':
4541 prec = 2;
4542 break;
4543
4544 case 'd':
4545 case 'D':
4546 case 'r':
4547 case 'R':
4548 prec = 4;
4549 break;
4550
4551 case 'x':
4552 case 'X':
4553 prec = 6;
4554 break;
4555
4556 case 'p':
4557 case 'P':
4558 prec = 6;
4559 break;
4560
4561 default:
4562 *sizeP = 0;
4563 return _("Bad call to MD_ATOF()");
4564 }
4565 t = atof_ieee (input_line_pointer, type, words);
4566 if (t)
4567 input_line_pointer = t;
4568
4569 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4570 for (wordP = words; prec--;)
4571 {
4572 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4573 litP += sizeof (LITTLENUM_TYPE);
4574 }
4575 return 0;
4576}
4577
4578void
4579md_number_to_chars (buf, val, n)
4580 char *buf;
4581 valueT val;
4582 int n;
4583{
4584 number_to_chars_bigendian (buf, val, n);
4585}
4586
94f592af
NC		 4587void
4588md_apply_fix3 (fixP, valP, seg)
252b5132 4589 fixS *fixP;
bbe8ef22 4590 valueT *valP;
94f592af 4591 segT seg ATTRIBUTE_UNUSED;
252b5132 4592{
bbe8ef22 4593 offsetT val = *valP;
252b5132
RH		 4594 addressT upper_limit;
4595 offsetT lower_limit;
4596
4597 /* This is unnecessary but it convinces the native rs6000 compiler
4598 to generate the code we want. */
4599 char *buf = fixP->fx_frag->fr_literal;
4600 buf += fixP->fx_where;
36759679 4601 /* End ibm compiler workaround. */
252b5132 4602
c801568a 4603 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132 4604
94f592af
NC		 4605 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4606 fixP->fx_done = 1;
4607
252b5132
RH		 4608#ifdef OBJ_ELF
4609 if (fixP->fx_addsy)
4610 {
4611 memset (buf, 0, fixP->fx_size);
36759679 4612 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4613
4614 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4615 && !S_IS_DEFINED (fixP->fx_addsy)
4616 && !S_IS_WEAK (fixP->fx_addsy))
4617 S_SET_WEAK (fixP->fx_addsy);
4618 return;
4619 }
4620#endif
4621
4622#ifdef BFD_ASSEMBLER
4623 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4624 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4625 return;
4626#endif
4627
4628 switch (fixP->fx_size)
4629 {
94f592af
NC		 4630 /* The cast to offsetT below are necessary to make code
4631 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4632 case 1:
4633 *buf++ = val;
4634 upper_limit = 0x7f;
4635 lower_limit = - (offsetT) 0x80;
4636 break;
4637 case 2:
4638 *buf++ = (val >> 8);
4639 *buf++ = val;
4640 upper_limit = 0x7fff;
4641 lower_limit = - (offsetT) 0x8000;
4642 break;
4643 case 4:
4644 *buf++ = (val >> 24);
4645 *buf++ = (val >> 16);
4646 *buf++ = (val >> 8);
4647 *buf++ = val;
4648 upper_limit = 0x7fffffff;
36759679 4649 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4650 break;
4651 default:
4652 BAD_CASE (fixP->fx_size);
4653 }
4654
4655 /* Fix up a negative reloc. */
4656 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4657 {
4658 fixP->fx_addsy = fixP->fx_subsy;
4659 fixP->fx_subsy = NULL;
4660 fixP->fx_tcbit = 1;
4661 }
4662
4663 /* For non-pc-relative values, it's conceivable we might get something
4664 like "0xff" for a byte field. So extend the upper part of the range
4665 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4666 so that we can do any range checking at all. */
4667 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4668 upper_limit = upper_limit * 2 + 1;
4669
4670 if ((addressT) val > upper_limit
4671 && (val > 0 || val < lower_limit))
4672 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4673
4674 /* A one byte PC-relative reloc means a short branch. We can't use
4675 a short branch with a value of 0 or -1, because those indicate
4676 different opcodes (branches with longer offsets). fixup_segment
4677 in write.c may have clobbered fx_pcrel, so we need to examine the
4678 reloc type. */
4679 if ((fixP->fx_pcrel
4680#ifdef BFD_ASSEMBLER
4681 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4682#endif
4683 )
4684 && fixP->fx_size == 1
4685 && (fixP->fx_addsy == NULL
4686 || S_IS_DEFINED (fixP->fx_addsy))
4687 && (val == 0 || val == -1))
4688 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4689}
4690
252b5132
RH		 4691/* *fragP has been relaxed to its final size, and now needs to have
4692 the bytes inside it modified to conform to the new size There is UGLY
4693 MAGIC here. ..
4694 */
4695static void
4696md_convert_frag_1 (fragP)
4697 register fragS *fragP;
4698{
4699 long disp;
252b5132
RH		 4700 fixS *fixP;
4701
4702 /* Address in object code of the displacement. */
4703 register int object_address = fragP->fr_fix + fragP->fr_address;
4704
4705 /* Address in gas core of the place to store the displacement. */
4706 /* This convinces the native rs6000 compiler to generate the code we
92774660 4707 want. */
252b5132
RH		 4708 register char *buffer_address = fragP->fr_literal;
4709 buffer_address += fragP->fr_fix;
36759679 4710 /* End ibm compiler workaround. */
252b5132
RH		 4711
4712 /* The displacement of the address, from current location. */
4713 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4714 disp = (disp + fragP->fr_offset) - object_address;
4715
252b5132
RH		 4716 switch (fragP->fr_subtype)
4717 {
151337e8
NC		 4718 case TAB (BRANCHBWL, BYTE):
4719 case TAB (BRABSJUNC, BYTE):
4720 case TAB (BRABSJCOND, BYTE):
4721 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4722 know (issbyte (disp));
4723 if (disp == 0)
b091f402
AM		 4724 as_bad_where (fragP->fr_file, fragP->fr_line,
4725 _("short branch with zero offset: use :w"));
151337e8 4726 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4727 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4728 fixP->fx_pcrel_adjust = -1;
252b5132 4729 break;
151337e8
NC		 4730 case TAB (BRANCHBWL, SHORT):
4731 case TAB (BRABSJUNC, SHORT):
4732 case TAB (BRABSJCOND, SHORT):
4733 case TAB (BRANCHBW, SHORT):
252b5132 4734 fragP->fr_opcode[1] = 0x00;
151337e8 4735 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4736 1, RELAX_RELOC_PC16);
151337e8
NC		 4737 fragP->fr_fix += 2;
4738 break;
4739 case TAB (BRANCHBWL, LONG):
4740 fragP->fr_opcode[1] = (char) 0xFF;
4741 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4742 1, RELAX_RELOC_PC32);
151337e8 4743 fragP->fr_fix += 4;
252b5132 4744 break;
151337e8
NC		 4745 case TAB (BRABSJUNC, LONG):
4746 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4747 {
36759679 4748 if (flag_keep_pcrel)
6b6e92f4 4749 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4750 fragP->fr_opcode[0] = 0x4E;
36759679 4751 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4752 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4753 0, RELAX_RELOC_ABS32);
151337e8
NC		 4754 fragP->fr_fix += 4;
4755 }
4756 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4757 {
36759679 4758 if (flag_keep_pcrel)
6b6e92f4 4759 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4760 fragP->fr_opcode[0] = 0x4E;
36759679 4761 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4762 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4763 0, RELAX_RELOC_ABS32);
151337e8 4764 fragP->fr_fix += 4;
252b5132
RH		 4765 }
4766 else
4767 {
151337e8
NC		 4768 /* This cannot happen, because jbsr and jbra are the only two
4769 unconditional branches. */
4770 abort ();
252b5132
RH		 4771 }
4772 break;
151337e8 4773 case TAB (BRABSJCOND, LONG):
36759679 4774 if (flag_keep_pcrel)
6b6e92f4 4775 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4776
36759679
NC		 4777 /* Only Bcc 68000 instructions can come here
4778 Change bcc into b!cc/jmp absl long. */
4779 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4780 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4781
4782 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4783 different frag, in which case referring to them is a no-no.
92774660 4784 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4785 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4786 *buffer_address++ = (char) 0xf9;
36759679 4787 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4788 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4789 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4790 fragP->fr_fix += 4;
4791 break;
4792 case TAB (FBRANCH, SHORT):
4793 know ((fragP->fr_opcode[1] & 0x40) == 0);
4794 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4795 1, RELAX_RELOC_PC16);
151337e8
NC		 4796 fragP->fr_fix += 2;
4797 break;
4798 case TAB (FBRANCH, LONG):
36759679 4799 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4800 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4801 1, RELAX_RELOC_PC32);
252b5132 4802 fragP->fr_fix += 4;
252b5132 4803 break;
151337e8
NC		 4804 case TAB (DBCCLBR, SHORT):
4805 case TAB (DBCCABSJ, SHORT):
4806 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4807 1, RELAX_RELOC_PC16);
151337e8
NC		 4808 fragP->fr_fix += 2;
4809 break;
4810 case TAB (DBCCLBR, LONG):
36759679
NC		 4811 /* Only DBcc instructions can come here.
4812 Change dbcc into dbcc/bral.
4813 JF: these used to be fr_opcode[2-7], but that's wrong. */
4814 if (flag_keep_pcrel)
6b6e92f4 4815 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4816
36759679 4817 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4818 *buffer_address++ = 0x04;
36759679 4819 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4820 *buffer_address++ = 0x06;
151337e8
NC		 4821 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4822 *buffer_address++ = (char) 0xff;
252b5132 4823
36759679 4824 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4825 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4826 RELAX_RELOC_PC32);
252b5132 4827 fragP->fr_fix += 4;
252b5132 4828 break;
151337e8 4829 case TAB (DBCCABSJ, LONG):
36759679
NC		 4830 /* Only DBcc instructions can come here.
4831 Change dbcc into dbcc/jmp.
4832 JF: these used to be fr_opcode[2-7], but that's wrong. */
4833 if (flag_keep_pcrel)
6b6e92f4 4834 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4835
36759679 4836 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4837 *buffer_address++ = 0x04;
36759679 4838 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4839 *buffer_address++ = 0x06;
36759679 4840 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4841 *buffer_address++ = (char) 0xf9;
4842
36759679 4843 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4844 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4845 RELAX_RELOC_ABS32);
252b5132 4846 fragP->fr_fix += 4;
252b5132 4847 break;
151337e8 4848 case TAB (PCREL1632, SHORT):
252b5132
RH		 4849 fragP->fr_opcode[1] &= ~0x3F;
4850 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4851 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4852 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4853 fragP->fr_fix += 2;
252b5132 4854 break;
151337e8 4855 case TAB (PCREL1632, LONG):
252b5132
RH		 4856 /* Already set to mode 7.3; this indicates: PC indirect with
4857 suppressed index, 32-bit displacement. */
4858 *buffer_address++ = 0x01;
4859 *buffer_address++ = 0x70;
4860 fragP->fr_fix += 2;
151337e8 4861 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4862 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4863 fixP->fx_pcrel_adjust = 2;
4864 fragP->fr_fix += 4;
252b5132 4865 break;
252b5132 4866 case TAB (PCINDEX, BYTE):
252b5132
RH		 4867 assert (fragP->fr_fix >= 2);
4868 buffer_address[-2] &= ~1;
151337e8 4869 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4870 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4871 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4872 break;
4873 case TAB (PCINDEX, SHORT):
252b5132
RH		 4874 assert (fragP->fr_fix >= 2);
4875 buffer_address[-2] |= 0x1;
4876 buffer_address[-1] = 0x20;
4877 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4878 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4879 fixP->fx_pcrel_adjust = 2;
151337e8 4880 fragP->fr_fix += 2;
252b5132
RH		 4881 break;
4882 case TAB (PCINDEX, LONG):
252b5132
RH		 4883 assert (fragP->fr_fix >= 2);
4884 buffer_address[-2] |= 0x1;
4885 buffer_address[-1] = 0x30;
151337e8 4886 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4887 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4888 fixP->fx_pcrel_adjust = 2;
4889 fragP->fr_fix += 4;
4890 break;
4891 case TAB (ABSTOPCREL, SHORT):
4892 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4893 1, RELAX_RELOC_PC16);
151337e8
NC		 4894 fragP->fr_fix += 2;
4895 break;
4896 case TAB (ABSTOPCREL, LONG):
36759679 4897 if (flag_keep_pcrel)
6b6e92f4 4898 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4899 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4900 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4901 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4902 abort ();
4903 fragP->fr_opcode[1] &= ~0x3F;
4904 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4905 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4906 0, RELAX_RELOC_ABS32);
151337e8 4907 fragP->fr_fix += 4;
252b5132 4908 break;
252b5132
RH		 4909 }
4910}
4911
4912#ifndef BFD_ASSEMBLER
4913
4914void
4915md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4916 object_headers *headers ATTRIBUTE_UNUSED;
4917 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4918 fragS *fragP;
4919{
4920 md_convert_frag_1 (fragP);
4921}
4922
4923#else
4924
4925void
4926md_convert_frag (abfd, sec, fragP)
36823076
AS		 4927 bfd *abfd ATTRIBUTE_UNUSED;
4928 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4929 fragS *fragP;
4930{
4931 md_convert_frag_1 (fragP);
4932}
4933#endif
4934
4935/* Force truly undefined symbols to their maximum size, and generally set up
4936 the frag list to be relaxed
4937 */
4938int
4939md_estimate_size_before_relax (fragP, segment)
4940 register fragS *fragP;
4941 segT segment;
4942{
151337e8 4943 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4944 switch (fragP->fr_subtype)
4945 {
151337e8
NC		 4946 case TAB (BRANCHBWL, SZ_UNDEF):
4947 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4948 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4949 {
151337e8
NC		 4950 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4951 && relaxable_symbol (fragP->fr_symbol))
252b5132 4952 {
151337e8
NC		 4953 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4954 }
4955 else if (flag_short_refs)
4956 {
4957 /* Symbol is undefined and we want short ref. */
4958 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4959 }
4960 else
4961 {
151337e8
NC		 4962 /* Symbol is still undefined. Make it LONG. */
4963 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4964 }
4965 break;
151337e8 4966 }
252b5132 4967
151337e8 4968 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4969 {
151337e8
NC		 4970 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4971 && relaxable_symbol (fragP->fr_symbol))
252b5132 4972 {
151337e8 4973 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4974 }
4975 else
4976 {
151337e8
NC		 4977 /* Symbol is undefined and we don't have long branches. */
4978 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4979 }
4980 break;
151337e8 4981 }
252b5132 4982
151337e8 4983 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4984 case TAB (DBCCLBR, SZ_UNDEF):
4985 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4986 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4987 {
8ec6253e
NC		 4988 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4989 && relaxable_symbol (fragP->fr_symbol))
151337e8 4990 || flag_short_refs)
252b5132 4991 {
151337e8 4992 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4993 }
4994 else
4995 {
151337e8 4996 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4997 }
4998 break;
151337e8 4999 }
81d4177b 5000
252b5132
RH		 5001 case TAB (PCINDEX, SZ_UNDEF):
5002 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5003 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5004 {
5005 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5006 }
5007 else
5008 {
5009 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5010 }
5011 break;
5012
151337e8
NC		 5013 case TAB (ABSTOPCREL, SZ_UNDEF):
5014 {
5015 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5016 && relaxable_symbol (fragP->fr_symbol)))
5017 {
5018 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5019 }
5020 else
5021 {
5022 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5023 }
5024 break;
5025 }
5026
252b5132
RH		 5027 default:
5028 break;
5029 }
5030
151337e8 5031 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5032 switch (fragP->fr_subtype)
5033 {
151337e8
NC		 5034 case TAB (BRANCHBWL, BYTE):
5035 case TAB (BRABSJUNC, BYTE):
5036 case TAB (BRABSJCOND, BYTE):
5037 case TAB (BRANCHBW, BYTE):
252b5132 5038 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5039 case we force word mode. If the symbol is at the start of a
5040 frag, and it is the next frag with any data in it (usually
5041 this is just the next frag, but assembler listings may
5042 introduce empty frags), we must use word mode. */
5043 if (fragP->fr_symbol)
252b5132 5044 {
ac62c346 5045 fragS *sym_frag;
252b5132 5046
ac62c346
AM		 5047 sym_frag = symbol_get_frag (fragP->fr_symbol);
5048 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5049 {
ac62c346
AM		 5050 fragS *l;
5051
23b7f870 5052 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5053 if (l->fr_fix != 0)
5054 break;
5055 if (l == sym_frag)
5056 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5057 }
5058 }
5059 break;
5060 default:
5061 break;
5062 }
ac62c346 5063 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5064}
5065
5066#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5067/* the bit-field entries in the relocation_info struct plays hell
5068 with the byte-order problems of cross-assembly. So as a hack,
5069 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5070 you there. -KWK */
252b5132
RH		 5071/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5072 are symbolnum, most sig. byte first. Last byte is broken up with
5073 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5074 nibble as nuthin. (on Sun 3 at least) */
5075/* Translate the internal relocation information into target-specific
92774660 5076 format. */
252b5132
RH		 5077#ifdef comment
5078void
5079md_ri_to_chars (the_bytes, ri)
5080 char *the_bytes;
5081 struct reloc_info_generic *ri;
5082{
36759679 5083 /* This is easy. */
252b5132 5084 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5085 /* Now the fun stuff. */
252b5132 5086 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5087 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5088 the_bytes[6] = ri->r_symbolnum & 0x0ff;
252b5132
RH		 5089 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
5090 ((ri->r_extern << 4) & 0x10));
5091}
5092
36759679 5093#endif
252b5132
RH		 5094
5095#ifndef BFD_ASSEMBLER
5096void
5097tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5098 char *where;
5099 fixS *fixP;
5100 relax_addressT segment_address_in_file;
5101{
5102 /*
5103 * In: length of relocation (or of address) in chars: 1, 2 or 4.
5104 * Out: GNU LD relocation length code: 0, 1, or 2.
5105 */
5106
5a38dc70 5107 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
252b5132
RH		 5108 long r_symbolnum;
5109
5110 know (fixP->fx_addsy != NULL);
5111
5112 md_number_to_chars (where,
5113 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
5114 4);
5115
5116 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5117 ? S_GET_TYPE (fixP->fx_addsy)
5118 : fixP->fx_addsy->sy_number);
5119
5120 where[4] = (r_symbolnum >> 16) & 0x0ff;
5121 where[5] = (r_symbolnum >> 8) & 0x0ff;
5122 where[6] = r_symbolnum & 0x0ff;
5123 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
5124 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
5125}
5126#endif
5127
5128#endif /* OBJ_AOUT or OBJ_BOUT */
5129
5130#ifndef WORKING_DOT_WORD
5a38dc70
AM		 5131const int md_short_jump_size = 4;
5132const int md_long_jump_size = 6;
252b5132
RH		 5133
5134void
5135md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5136 char *ptr;
5137 addressT from_addr, to_addr;
36823076
AS		 5138 fragS *frag ATTRIBUTE_UNUSED;
5139 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 5140{
5141 valueT offset;
5142
5143 offset = to_addr - (from_addr + 2);
5144
5145 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5146 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5147}
5148
5149void
5150md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5151 char *ptr;
5152 addressT from_addr, to_addr;
5153 fragS *frag;
5154 symbolS *to_symbol;
5155{
5156 valueT offset;
5157
6b6e92f4 5158 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5159 {
36759679 5160 if (flag_keep_pcrel)
6b6e92f4 5161 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5162 offset = to_addr - S_GET_VALUE (to_symbol);
5163 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5164 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5165 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5166 0, NO_RELOC);
5167 }
5168 else
5169 {
5170 offset = to_addr - (from_addr + 2);
5171 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5172 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5173 }
5174}
5175
5176#endif
5177
5178/* Different values of OK tell what its OK to return. Things that
5179 aren't OK are an error (what a shock, no?)
5180
5181 0: Everything is OK
3e602632
NC		 5182 10: Absolute 1:8 only
5183 20: Absolute 0:7 only
5184 30: absolute 0:15 only
5185 40: Absolute 0:31 only
5186 50: absolute 0:127 only
252b5132 5187 55: absolute -64:63 only
3e602632
NC		 5188 60: absolute -128:127 only
5189 70: absolute 0:4095 only
5190 80: absolute -1, 1:7 only
5191 90: No bignums. */
252b5132
RH		 5192
5193static int
5194get_num (exp, ok)
5195 struct m68k_exp *exp;
5196 int ok;
5197{
5198 if (exp->exp.X_op == O_absent)
5199 {
36759679 5200 /* Do the same thing the VAX asm does. */
252b5132
RH		 5201 op (exp) = O_constant;
5202 adds (exp) = 0;
5203 subs (exp) = 0;
5204 offs (exp) = 0;
5205 if (ok == 10)
5206 {
5207 as_warn (_("expression out of range: defaulting to 1"));
5208 offs (exp) = 1;
5209 }
5210 }
5211 else if (exp->exp.X_op == O_constant)
5212 {
5213 switch (ok)
5214 {
5215 case 10:
5216 if (offs (exp) < 1 || offs (exp) > 8)
5217 {
5218 as_warn (_("expression out of range: defaulting to 1"));
5219 offs (exp) = 1;
5220 }
5221 break;
5222 case 20:
5223 if (offs (exp) < 0 || offs (exp) > 7)
5224 goto outrange;
5225 break;
5226 case 30:
5227 if (offs (exp) < 0 || offs (exp) > 15)
5228 goto outrange;
5229 break;
5230 case 40:
5231 if (offs (exp) < 0 || offs (exp) > 32)
5232 goto outrange;
5233 break;
5234 case 50:
5235 if (offs (exp) < 0 || offs (exp) > 127)
5236 goto outrange;
5237 break;
5238 case 55:
5239 if (offs (exp) < -64 || offs (exp) > 63)
5240 goto outrange;
5241 break;
5242 case 60:
5243 if (offs (exp) < -128 || offs (exp) > 127)
5244 goto outrange;
5245 break;
5246 case 70:
5247 if (offs (exp) < 0 || offs (exp) > 4095)
5248 {
5249 outrange:
5250 as_warn (_("expression out of range: defaulting to 0"));
5251 offs (exp) = 0;
5252 }
5253 break;
3e602632
NC		 5254 case 80:
5255 if (offs (exp) < -1
5256 || offs (exp) > 7
5257 || offs (exp) == 0)
5258 {
5259 as_warn (_("expression out of range: defaulting to 1"));
5260 offs (exp) = 1;
5261 }
5262 break;
252b5132
RH		 5263 default:
5264 break;
5265 }
5266 }
5267 else if (exp->exp.X_op == O_big)
5268 {
36759679 5269 if (offs (exp) <= 0 /* flonum. */
3e602632 5270 && (ok == 90 /* no bignums */
36759679 5271 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5272 /* If we have a flonum zero, a zero integer should
5273 do as well (e.g., in moveq). */
5274 && generic_floating_point_number.exponent == 0
5275 && generic_floating_point_number.low[0] == 0)))
5276 {
36759679 5277 /* HACK! Turn it into a long. */
252b5132
RH		 5278 LITTLENUM_TYPE words[6];
5279
36759679 5280 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5281 op (exp) = O_constant;
5282 adds (exp) = 0;
5283 subs (exp) = 0;
5284 offs (exp) = words[1] | (words[0] << 16);
5285 }
5286 else if (ok != 0)
5287 {
5288 op (exp) = O_constant;
5289 adds (exp) = 0;
5290 subs (exp) = 0;
5291 offs (exp) = (ok == 10) ? 1 : 0;
5292 as_warn (_("Can't deal with expression; defaulting to %ld"),
5293 offs (exp));
5294 }
5295 }
5296 else
5297 {
3e602632 5298 if (ok >= 10 && ok <= 80)
252b5132
RH		 5299 {
5300 op (exp) = O_constant;
5301 adds (exp) = 0;
5302 subs (exp) = 0;
5303 offs (exp) = (ok == 10) ? 1 : 0;
5304 as_warn (_("Can't deal with expression; defaulting to %ld"),
5305 offs (exp));
5306 }
5307 }
5308
5309 if (exp->size != SIZE_UNSPEC)
5310 {
5311 switch (exp->size)
5312 {
5313 case SIZE_UNSPEC:
5314 case SIZE_LONG:
5315 break;
5316 case SIZE_BYTE:
5317 if (!isbyte (offs (exp)))
5318 as_warn (_("expression doesn't fit in BYTE"));
5319 break;
5320 case SIZE_WORD:
5321 if (!isword (offs (exp)))
5322 as_warn (_("expression doesn't fit in WORD"));
5323 break;
5324 }
5325 }
5326
5327 return offs (exp);
5328}
5329
5330/* These are the back-ends for the various machine dependent pseudo-ops. */
5331
5332static void
5333s_data1 (ignore)
36823076 5334 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5335{
5336 subseg_set (data_section, 1);
5337 demand_empty_rest_of_line ();
5338}
5339
5340static void
5341s_data2 (ignore)
36823076 5342 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5343{
5344 subseg_set (data_section, 2);
5345 demand_empty_rest_of_line ();
5346}
5347
5348static void
5349s_bss (ignore)
36823076 5350 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5351{
5352 /* We don't support putting frags in the BSS segment, we fake it
5353 by marking in_bss, then looking at s_skip for clues. */
5354
5355 subseg_set (bss_section, 0);
5356 demand_empty_rest_of_line ();
5357}
5358
5359static void
5360s_even (ignore)
36823076 5361 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5362{
5363 register int temp;
5364 register long temp_fill;
5365
5366 temp = 1; /* JF should be 2? */
5367 temp_fill = get_absolute_expression ();
92774660 5368 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5369 frag_align (temp, (int) temp_fill, 0);
5370 demand_empty_rest_of_line ();
5371 record_alignment (now_seg, temp);
5372}
5373
5374static void
5375s_proc (ignore)
36823076 5376 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5377{
5378 demand_empty_rest_of_line ();
5379}
5380\f
5381/* Pseudo-ops handled for MRI compatibility. */
5382
5383/* This function returns non-zero if the argument is a conditional
5384 pseudo-op. This is called when checking whether a pending
5385 alignment is needed. */
5386
5387int
5388m68k_conditional_pseudoop (pop)
5389 pseudo_typeS *pop;
5390{
5391 return (pop->poc_handler == s_mri_if
5392 || pop->poc_handler == s_mri_else);
5393}
5394
5395/* Handle an MRI style chip specification. */
5396
5397static void
5398mri_chip ()
5399{
5400 char *s;
5401 char c;
5402 int i;
5403
5404 s = input_line_pointer;
5405 /* We can't use get_symbol_end since the processor names are not proper
5406 symbols. */
5407 while (is_part_of_name (c = *input_line_pointer++))
5408 ;
5409 *--input_line_pointer = 0;
5410 for (i = 0; i < n_archs; i++)
5411 if (strcasecmp (s, archs[i].name) == 0)
5412 break;
5413 if (i >= n_archs)
5414 {
5415 as_bad (_("%s: unrecognized processor name"), s);
5416 *input_line_pointer = c;
5417 ignore_rest_of_line ();
5418 return;
5419 }
5420 *input_line_pointer = c;
5421
5422 if (*input_line_pointer == '/')
5423 current_architecture = 0;
5424 else
5425 current_architecture &= m68881 | m68851;
5426 current_architecture |= archs[i].arch;
6b6e92f4 5427 current_chip |= archs[i].chip;
252b5132
RH		 5428
5429 while (*input_line_pointer == '/')
5430 {
5431 ++input_line_pointer;
5432 s = input_line_pointer;
5433 /* We can't use get_symbol_end since the processor names are not
5434 proper symbols. */
5435 while (is_part_of_name (c = *input_line_pointer++))
5436 ;
5437 *--input_line_pointer = 0;
5438 if (strcmp (s, "68881") == 0)
5439 current_architecture |= m68881;
5440 else if (strcmp (s, "68851") == 0)
5441 current_architecture |= m68851;
5442 *input_line_pointer = c;
5443 }
5444
5445 /* Update info about available control registers. */
5446 select_control_regs ();
5447}
5448
5449/* The MRI CHIP pseudo-op. */
5450
5451static void
5452s_chip (ignore)
36823076 5453 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5454{
5455 char *stop = NULL;
5456 char stopc;
5457
5458 if (flag_mri)
5459 stop = mri_comment_field (&stopc);
5460 mri_chip ();
5461 if (flag_mri)
5462 mri_comment_end (stop, stopc);
5463 demand_empty_rest_of_line ();
5464}
5465
5466/* The MRI FOPT pseudo-op. */
5467
5468static void
5469s_fopt (ignore)
36823076 5470 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5471{
5472 SKIP_WHITESPACE ();
5473
5474 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5475 {
5476 int temp;
5477
5478 input_line_pointer += 3;
5479 temp = get_absolute_expression ();
5480 if (temp < 0 || temp > 7)
5481 as_bad (_("bad coprocessor id"));
5482 else
5483 m68k_float_copnum = COP0 + temp;
5484 }
5485 else
5486 {
5487 as_bad (_("unrecognized fopt option"));
5488 ignore_rest_of_line ();
5489 return;
5490 }
5491
5492 demand_empty_rest_of_line ();
5493}
5494
5495/* The structure used to handle the MRI OPT pseudo-op. */
5496
5497struct opt_action
5498{
5499 /* The name of the option. */
5500 const char *name;
5501
5502 /* If this is not NULL, just call this function. The first argument
5503 is the ARG field of this structure, the second argument is
5504 whether the option was negated. */
5505 void (*pfn) PARAMS ((int arg, int on));
5506
5507 /* If this is not NULL, and the PFN field is NULL, set the variable
5508 this points to. Set it to the ARG field if the option was not
5509 negated, and the NOTARG field otherwise. */
5510 int *pvar;
5511
5512 /* The value to pass to PFN or to assign to *PVAR. */
5513 int arg;
5514
5515 /* The value to assign to *PVAR if the option is negated. If PFN is
5516 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5517 the option may not be negated. */
5518 int notarg;
5519};
5520
5521/* The table used to handle the MRI OPT pseudo-op. */
5522
5523static void skip_to_comma PARAMS ((int, int));
5524static void opt_nest PARAMS ((int, int));
5525static void opt_chip PARAMS ((int, int));
5526static void opt_list PARAMS ((int, int));
5527static void opt_list_symbols PARAMS ((int, int));
5528
5529static const struct opt_action opt_table[] =
5530{
5531 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5532
5533 /* We do relaxing, so there is little use for these options. */
5534 { "b", 0, 0, 0, 0 },
5535 { "brs", 0, 0, 0, 0 },
5536 { "brb", 0, 0, 0, 0 },
5537 { "brl", 0, 0, 0, 0 },
5538 { "brw", 0, 0, 0, 0 },
5539
5540 { "c", 0, 0, 0, 0 },
5541 { "cex", 0, 0, 0, 0 },
5542 { "case", 0, &symbols_case_sensitive, 1, 0 },
5543 { "cl", 0, 0, 0, 0 },
5544 { "cre", 0, 0, 0, 0 },
5545 { "d", 0, &flag_keep_locals, 1, 0 },
5546 { "e", 0, 0, 0, 0 },
5547 { "f", 0, &flag_short_refs, 1, 0 },
5548 { "frs", 0, &flag_short_refs, 1, 0 },
5549 { "frl", 0, &flag_short_refs, 0, 1 },
5550 { "g", 0, 0, 0, 0 },
5551 { "i", 0, 0, 0, 0 },
5552 { "m", 0, 0, 0, 0 },
5553 { "mex", 0, 0, 0, 0 },
5554 { "mc", 0, 0, 0, 0 },
5555 { "md", 0, 0, 0, 0 },
5556 { "nest", opt_nest, 0, 0, 0 },
5557 { "next", skip_to_comma, 0, 0, 0 },
5558 { "o", 0, 0, 0, 0 },
5559 { "old", 0, 0, 0, 0 },
5560 { "op", skip_to_comma, 0, 0, 0 },
5561 { "pco", 0, 0, 0, 0 },
5562 { "p", opt_chip, 0, 0, 0 },
5563 { "pcr", 0, 0, 0, 0 },
5564 { "pcs", 0, 0, 0, 0 },
5565 { "r", 0, 0, 0, 0 },
5566 { "quick", 0, &m68k_quick, 1, 0 },
5567 { "rel32", 0, &m68k_rel32, 1, 0 },
5568 { "s", opt_list, 0, 0, 0 },
5569 { "t", opt_list_symbols, 0, 0, 0 },
5570 { "w", 0, &flag_no_warnings, 0, 1 },
5571 { "x", 0, 0, 0, 0 }
5572};
5573
8fce3f5e 5574#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5575
5576/* The MRI OPT pseudo-op. */
5577
5578static void
5579s_opt (ignore)
36823076 5580 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5581{
5582 do
5583 {
5584 int t;
5585 char *s;
5586 char c;
5587 int i;
5588 const struct opt_action *o;
5589
5590 SKIP_WHITESPACE ();
5591
5592 t = 1;
5593 if (*input_line_pointer == '-')
5594 {
5595 ++input_line_pointer;
5596 t = 0;
5597 }
5598 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5599 {
5600 input_line_pointer += 2;
5601 t = 0;
5602 }
5603
5604 s = input_line_pointer;
5605 c = get_symbol_end ();
5606
5607 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5608 {
5609 if (strcasecmp (s, o->name) == 0)
5610 {
5611 if (o->pfn)
5612 {
5613 /* Restore input_line_pointer now in case the option
5614 takes arguments. */
5615 *input_line_pointer = c;
5616 (*o->pfn) (o->arg, t);
5617 }
5618 else if (o->pvar != NULL)
5619 {
5620 if (! t && o->arg == o->notarg)
5621 as_bad (_("option `%s' may not be negated"), s);
5622 *input_line_pointer = c;
5623 *o->pvar = t ? o->arg : o->notarg;
5624 }
5625 else
5626 *input_line_pointer = c;
5627 break;
5628 }
5629 }
5630 if (i >= OPTCOUNT)
5631 {
5632 as_bad (_("option `%s' not recognized"), s);
5633 *input_line_pointer = c;
5634 }
5635 }
5636 while (*input_line_pointer++ == ',');
5637
5638 /* Move back to terminating character. */
5639 --input_line_pointer;
5640 demand_empty_rest_of_line ();
5641}
5642
5643/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5644 not support and which take arguments. */
252b5132
RH		 5645
5646static void
5647skip_to_comma (arg, on)
36823076
AS		 5648 int arg ATTRIBUTE_UNUSED;
5649 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5650{
5651 while (*input_line_pointer != ','
5652 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5653 ++input_line_pointer;
5654}
5655
5656/* Handle the OPT NEST=depth option. */
5657
5658static void
5659opt_nest (arg, on)
36823076
AS		 5660 int arg ATTRIBUTE_UNUSED;
5661 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5662{
5663 if (*input_line_pointer != '=')
5664 {
5665 as_bad (_("bad format of OPT NEST=depth"));
5666 return;
5667 }
5668
5669 ++input_line_pointer;
5670 max_macro_nest = get_absolute_expression ();
5671}
5672
5673/* Handle the OPT P=chip option. */
5674
5675static void
5676opt_chip (arg, on)
36823076
AS		 5677 int arg ATTRIBUTE_UNUSED;
5678 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5679{
5680 if (*input_line_pointer != '=')
5681 {
5682 /* This is just OPT P, which we do not support. */
5683 return;
5684 }
5685
5686 ++input_line_pointer;
5687 mri_chip ();
5688}
5689
5690/* Handle the OPT S option. */
5691
5692static void
5693opt_list (arg, on)
36823076 5694 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5695 int on;
5696{
5697 listing_list (on);
5698}
5699
5700/* Handle the OPT T option. */
5701
5702static void
5703opt_list_symbols (arg, on)
36823076 5704 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5705 int on;
5706{
5707 if (on)
5708 listing |= LISTING_SYMBOLS;
5709 else
8a104df9 5710 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5711}
5712
5713/* Handle the MRI REG pseudo-op. */
5714
5715static void
5716s_reg (ignore)
36823076 5717 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5718{
5719 char *s;
5720 int c;
5721 struct m68k_op rop;
5722 int mask;
5723 char *stop = NULL;
5724 char stopc;
5725
5726 if (line_label == NULL)
5727 {
5728 as_bad (_("missing label"));
5729 ignore_rest_of_line ();
5730 return;
5731 }
5732
5733 if (flag_mri)
5734 stop = mri_comment_field (&stopc);
5735
5736 SKIP_WHITESPACE ();
5737
5738 s = input_line_pointer;
3882b010 5739 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5740#ifdef REGISTER_PREFIX
5741 || *input_line_pointer == REGISTER_PREFIX
5742#endif
5743 || *input_line_pointer == '/'
5744 || *input_line_pointer == '-')
5745 ++input_line_pointer;
5746 c = *input_line_pointer;
5747 *input_line_pointer = '\0';
5748
5749 if (m68k_ip_op (s, &rop) != 0)
5750 {
5751 if (rop.error == NULL)
5752 as_bad (_("bad register list"));
5753 else
5754 as_bad (_("bad register list: %s"), rop.error);
5755 *input_line_pointer = c;
5756 ignore_rest_of_line ();
5757 return;
5758 }
5759
5760 *input_line_pointer = c;
5761
5762 if (rop.mode == REGLST)
5763 mask = rop.mask;
5764 else if (rop.mode == DREG)
5765 mask = 1 << (rop.reg - DATA0);
5766 else if (rop.mode == AREG)
5767 mask = 1 << (rop.reg - ADDR0 + 8);
5768 else if (rop.mode == FPREG)
5769 mask = 1 << (rop.reg - FP0 + 16);
5770 else if (rop.mode == CONTROL
5771 && rop.reg == FPI)
5772 mask = 1 << 24;
5773 else if (rop.mode == CONTROL
5774 && rop.reg == FPS)
5775 mask = 1 << 25;
5776 else if (rop.mode == CONTROL
5777 && rop.reg == FPC)
5778 mask = 1 << 26;
5779 else
5780 {
5781 as_bad (_("bad register list"));
5782 ignore_rest_of_line ();
5783 return;
5784 }
5785
5786 S_SET_SEGMENT (line_label, reg_section);
5787 S_SET_VALUE (line_label, ~mask);
49309057 5788 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5789
5790 if (flag_mri)
5791 mri_comment_end (stop, stopc);
5792
5793 demand_empty_rest_of_line ();
5794}
5795
5796/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5797
5798struct save_opts
5799{
5800 struct save_opts *next;
5801 int abspcadd;
5802 int symbols_case_sensitive;
5803 int keep_locals;
5804 int short_refs;
5805 int architecture;
6b6e92f4 5806 int chip;
252b5132
RH		 5807 int quick;
5808 int rel32;
5809 int listing;
5810 int no_warnings;
5811 /* FIXME: We don't save OPT S. */
5812};
5813
5814/* This variable holds the stack of saved options. */
5815
5816static struct save_opts *save_stack;
5817
5818/* The MRI SAVE pseudo-op. */
5819
5820static void
5821s_save (ignore)
36823076 5822 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5823{
5824 struct save_opts *s;
5825
5826 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5827 s->abspcadd = m68k_abspcadd;
5828 s->symbols_case_sensitive = symbols_case_sensitive;
5829 s->keep_locals = flag_keep_locals;
5830 s->short_refs = flag_short_refs;
5831 s->architecture = current_architecture;
6b6e92f4 5832 s->chip = current_chip;
252b5132
RH		 5833 s->quick = m68k_quick;
5834 s->rel32 = m68k_rel32;
5835 s->listing = listing;
5836 s->no_warnings = flag_no_warnings;
5837
5838 s->next = save_stack;
5839 save_stack = s;
5840
5841 demand_empty_rest_of_line ();
5842}
5843
5844/* The MRI RESTORE pseudo-op. */
5845
5846static void
5847s_restore (ignore)
36823076 5848 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5849{
5850 struct save_opts *s;
5851
5852 if (save_stack == NULL)
5853 {
5854 as_bad (_("restore without save"));
5855 ignore_rest_of_line ();
5856 return;
5857 }
5858
5859 s = save_stack;
5860 save_stack = s->next;
5861
5862 m68k_abspcadd = s->abspcadd;
5863 symbols_case_sensitive = s->symbols_case_sensitive;
5864 flag_keep_locals = s->keep_locals;
5865 flag_short_refs = s->short_refs;
5866 current_architecture = s->architecture;
6b6e92f4 5867 current_chip = s->chip;
252b5132
RH		 5868 m68k_quick = s->quick;
5869 m68k_rel32 = s->rel32;
5870 listing = s->listing;
5871 flag_no_warnings = s->no_warnings;
5872
5873 free (s);
5874
5875 demand_empty_rest_of_line ();
5876}
5877
5878/* Types of MRI structured control directives. */
5879
5880enum mri_control_type
5881{
5882 mri_for,
5883 mri_if,
5884 mri_repeat,
5885 mri_while
5886};
5887
5888/* This structure is used to stack the MRI structured control
5889 directives. */
5890
5891struct mri_control_info
5892{
5893 /* The directive within which this one is enclosed. */
5894 struct mri_control_info *outer;
5895
5896 /* The type of directive. */
5897 enum mri_control_type type;
5898
5899 /* Whether an ELSE has been in an IF. */
5900 int else_seen;
5901
5902 /* The add or sub statement at the end of a FOR. */
5903 char *incr;
5904
5905 /* The label of the top of a FOR or REPEAT loop. */
5906 char *top;
5907
5908 /* The label to jump to for the next iteration, or the else
5909 expression of a conditional. */
5910 char *next;
5911
5912 /* The label to jump to to break out of the loop, or the label past
5913 the end of a conditional. */
5914 char *bottom;
5915};
5916
5917/* The stack of MRI structured control directives. */
5918
5919static struct mri_control_info *mri_control_stack;
5920
5921/* The current MRI structured control directive index number, used to
5922 generate label names. */
5923
5924static int mri_control_index;
5925
5926/* Some function prototypes. */
5927
5928static void mri_assemble PARAMS ((char *));
5929static char *mri_control_label PARAMS ((void));
5930static struct mri_control_info *push_mri_control
5931 PARAMS ((enum mri_control_type));
5932static void pop_mri_control PARAMS ((void));
5933static int parse_mri_condition PARAMS ((int *));
5934static int parse_mri_control_operand
5935 PARAMS ((int *, char **, char **, char **, char **));
5936static int swap_mri_condition PARAMS ((int));
5937static int reverse_mri_condition PARAMS ((int));
5938static void build_mri_control_operand
5939 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5940 const char *, int));
5941static void parse_mri_control_expression
5942 PARAMS ((char *, int, const char *, const char *, int));
5943
5944/* Assemble an instruction for an MRI structured control directive. */
5945
5946static void
5947mri_assemble (str)
5948 char *str;
5949{
5950 char *s;
5951
5952 /* md_assemble expects the opcode to be in lower case. */
5953 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5954 *s = TOLOWER (*s);
252b5132
RH		 5955
5956 md_assemble (str);
5957}
5958
5959/* Generate a new MRI label structured control directive label name. */
5960
5961static char *
5962mri_control_label ()
5963{
5964 char *n;
5965
5966 n = (char *) xmalloc (20);
5967 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5968 ++mri_control_index;
5969 return n;
5970}
5971
5972/* Create a new MRI structured control directive. */
5973
5974static struct mri_control_info *
5975push_mri_control (type)
5976 enum mri_control_type type;
5977{
5978 struct mri_control_info *n;
5979
5980 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5981
5982 n->type = type;
5983 n->else_seen = 0;
5984 if (type == mri_if || type == mri_while)
5985 n->top = NULL;
5986 else
5987 n->top = mri_control_label ();
5988 n->next = mri_control_label ();
5989 n->bottom = mri_control_label ();
5990
5991 n->outer = mri_control_stack;
5992 mri_control_stack = n;
5993
5994 return n;
5995}
5996
5997/* Pop off the stack of MRI structured control directives. */
5998
5999static void
6000pop_mri_control ()
6001{
6002 struct mri_control_info *n;
6003
6004 n = mri_control_stack;
6005 mri_control_stack = n->outer;
6006 if (n->top != NULL)
6007 free (n->top);
6008 free (n->next);
6009 free (n->bottom);
6010 free (n);
6011}
6012
6013/* Recognize a condition code in an MRI structured control expression. */
6014
6015static int
6016parse_mri_condition (pcc)
6017 int *pcc;
6018{
6019 char c1, c2;
6020
6021 know (*input_line_pointer == '<');
6022
6023 ++input_line_pointer;
6024 c1 = *input_line_pointer++;
6025 c2 = *input_line_pointer++;
6026
6027 if (*input_line_pointer != '>')
6028 {
6029 as_bad (_("syntax error in structured control directive"));
6030 return 0;
6031 }
6032
6033 ++input_line_pointer;
6034 SKIP_WHITESPACE ();
6035
3882b010
L		 6036 c1 = TOLOWER (c1);
6037 c2 = TOLOWER (c2);
252b5132
RH		 6038
6039 *pcc = (c1 << 8) | c2;
6040
6041 return 1;
6042}
6043
6044/* Parse a single operand in an MRI structured control expression. */
6045
6046static int
6047parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
6048 int *pcc;
6049 char **leftstart;
6050 char **leftstop;
6051 char **rightstart;
6052 char **rightstop;
6053{
6054 char *s;
6055
6056 SKIP_WHITESPACE ();
6057
6058 *pcc = -1;
6059 *leftstart = NULL;
6060 *leftstop = NULL;
6061 *rightstart = NULL;
6062 *rightstop = NULL;
6063
6064 if (*input_line_pointer == '<')
6065 {
6066 /* It's just a condition code. */
6067 return parse_mri_condition (pcc);
6068 }
6069
6070 /* Look ahead for the condition code. */
6071 for (s = input_line_pointer; *s != '\0'; ++s)
6072 {
6073 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6074 break;
6075 }
6076 if (*s == '\0')
6077 {
6078 as_bad (_("missing condition code in structured control directive"));
6079 return 0;
6080 }
6081
6082 *leftstart = input_line_pointer;
6083 *leftstop = s;
6084 if (*leftstop > *leftstart
6085 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6086 --*leftstop;
6087
6088 input_line_pointer = s;
6089 if (! parse_mri_condition (pcc))
6090 return 0;
6091
6092 /* Look ahead for AND or OR or end of line. */
6093 for (s = input_line_pointer; *s != '\0'; ++s)
6094 {
e1f44d10
NC		 6095 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6096 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6097 ^^^ ^^ */
8a104df9
KH		 6098 if ((s == input_line_pointer
6099 || *(s-1) == ' '
6100 || *(s-1) == '\t')
6101 && ((strncasecmp (s, "AND", 3) == 0
6102 && (s[3] == '.' || ! is_part_of_name (s[3])))
6103 || (strncasecmp (s, "OR", 2) == 0
6104 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6105 break;
252b5132
RH		 6106 }
6107
6108 *rightstart = input_line_pointer;
6109 *rightstop = s;
6110 if (*rightstop > *rightstart
6111 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6112 --*rightstop;
6113
6114 input_line_pointer = s;
6115
6116 return 1;
6117}
6118
6119#define MCC(b1, b2) (((b1) << 8) | (b2))
6120
6121/* Swap the sense of a condition. This changes the condition so that
6122 it generates the same result when the operands are swapped. */
6123
6124static int
6125swap_mri_condition (cc)
6126 int cc;
6127{
6128 switch (cc)
6129 {
6130 case MCC ('h', 'i'): return MCC ('c', 's');
6131 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6132 /* <HS> is an alias for <CC>. */
e1f44d10 6133 case MCC ('h', 's'):
252b5132 6134 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6135 /* <LO> is an alias for <CS>. */
e1f44d10 6136 case MCC ('l', 'o'):
252b5132
RH		 6137 case MCC ('c', 's'): return MCC ('h', 'i');
6138 case MCC ('p', 'l'): return MCC ('m', 'i');
6139 case MCC ('m', 'i'): return MCC ('p', 'l');
6140 case MCC ('g', 'e'): return MCC ('l', 'e');
6141 case MCC ('l', 't'): return MCC ('g', 't');
6142 case MCC ('g', 't'): return MCC ('l', 't');
6143 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6144 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6145 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6146 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6147 case MCC ('v', 'c'):
6148 case MCC ('v', 's'):
6149 default :
6150 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6151 (char) (cc >> 8), (char) (cc));
6152 break;
252b5132
RH		 6153 }
6154 return cc;
6155}
6156
6157/* Reverse the sense of a condition. */
6158
6159static int
6160reverse_mri_condition (cc)
6161 int cc;
6162{
6163 switch (cc)
6164 {
6165 case MCC ('h', 'i'): return MCC ('l', 's');
6166 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6167 /* <HS> is an alias for <CC> */
6168 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6169 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6170 /* <LO> is an alias for <CS> */
6171 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6172 case MCC ('c', 's'): return MCC ('c', 'c');
6173 case MCC ('n', 'e'): return MCC ('e', 'q');
6174 case MCC ('e', 'q'): return MCC ('n', 'e');
6175 case MCC ('v', 'c'): return MCC ('v', 's');
6176 case MCC ('v', 's'): return MCC ('v', 'c');
6177 case MCC ('p', 'l'): return MCC ('m', 'i');
6178 case MCC ('m', 'i'): return MCC ('p', 'l');
6179 case MCC ('g', 'e'): return MCC ('l', 't');
6180 case MCC ('l', 't'): return MCC ('g', 'e');
6181 case MCC ('g', 't'): return MCC ('l', 'e');
6182 case MCC ('l', 'e'): return MCC ('g', 't');
6183 }
6184 return cc;
6185}
6186
6187/* Build an MRI structured control expression. This generates test
6188 and branch instructions. It goes to TRUELAB if the condition is
6189 true, and to FALSELAB if the condition is false. Exactly one of
6190 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6191 is the size qualifier for the expression. EXTENT is the size to
6192 use for the branch. */
6193
6194static void
6195build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6196 rightstop, truelab, falselab, extent)
6197 int qual;
6198 int cc;
6199 char *leftstart;
6200 char *leftstop;
6201 char *rightstart;
6202 char *rightstop;
6203 const char *truelab;
6204 const char *falselab;
6205 int extent;
6206{
6207 char *buf;
6208 char *s;
6209
6210 if (leftstart != NULL)
6211 {
6212 struct m68k_op leftop, rightop;
6213 char c;
6214
6215 /* Swap the compare operands, if necessary, to produce a legal
6216 m68k compare instruction. Comparing a register operand with
6217 a non-register operand requires the register to be on the
6218 right (cmp, cmpa). Comparing an immediate value with
6219 anything requires the immediate value to be on the left
6220 (cmpi). */
6221
6222 c = *leftstop;
6223 *leftstop = '\0';
6224 (void) m68k_ip_op (leftstart, &leftop);
6225 *leftstop = c;
6226
6227 c = *rightstop;
6228 *rightstop = '\0';
6229 (void) m68k_ip_op (rightstart, &rightop);
6230 *rightstop = c;
6231
6232 if (rightop.mode == IMMED
6233 || ((leftop.mode == DREG || leftop.mode == AREG)
6234 && (rightop.mode != DREG && rightop.mode != AREG)))
6235 {
6236 char *temp;
6237
e1f44d10
NC		 6238 /* Correct conditional handling:
6239 if #1 <lt> d0 then ;means if (1 < d0)
6240 ...
6241 endi
6242
6243 should assemble to:
6244
6245 cmp #1,d0 if we do *not* swap the operands
6246 bgt true we need the swapped condition!
6247 ble false
6248 true:
6249 ...
6250 false:
6251 */
252b5132
RH		 6252 temp = leftstart;
6253 leftstart = rightstart;
6254 rightstart = temp;
6255 temp = leftstop;
6256 leftstop = rightstop;
6257 rightstop = temp;
8a104df9
KH		 6258 }
6259 else
6260 {
e1f44d10 6261 cc = swap_mri_condition (cc);
252b5132
RH		 6262 }
6263 }
6264
6265 if (truelab == NULL)
6266 {
6267 cc = reverse_mri_condition (cc);
6268 truelab = falselab;
6269 }
92774660 6270
252b5132
RH		 6271 if (leftstart != NULL)
6272 {
6273 buf = (char *) xmalloc (20
6274 + (leftstop - leftstart)
6275 + (rightstop - rightstart));
6276 s = buf;
6277 *s++ = 'c';
6278 *s++ = 'm';
6279 *s++ = 'p';
6280 if (qual != '\0')
3882b010 6281 *s++ = TOLOWER (qual);
252b5132
RH		 6282 *s++ = ' ';
6283 memcpy (s, leftstart, leftstop - leftstart);
6284 s += leftstop - leftstart;
6285 *s++ = ',';
6286 memcpy (s, rightstart, rightstop - rightstart);
6287 s += rightstop - rightstart;
6288 *s = '\0';
6289 mri_assemble (buf);
6290 free (buf);
6291 }
92774660 6292
252b5132
RH		 6293 buf = (char *) xmalloc (20 + strlen (truelab));
6294 s = buf;
6295 *s++ = 'b';
6296 *s++ = cc >> 8;
6297 *s++ = cc & 0xff;
6298 if (extent != '\0')
3882b010 6299 *s++ = TOLOWER (extent);
252b5132
RH		 6300 *s++ = ' ';
6301 strcpy (s, truelab);
6302 mri_assemble (buf);
6303 free (buf);
6304}
6305
6306/* Parse an MRI structured control expression. This generates test
6307 and branch instructions. STOP is where the expression ends. It
6308 goes to TRUELAB if the condition is true, and to FALSELAB if the
6309 condition is false. Exactly one of TRUELAB and FALSELAB will be
6310 NULL, meaning to fall through. QUAL is the size qualifier for the
6311 expression. EXTENT is the size to use for the branch. */
6312
6313static void
6314parse_mri_control_expression (stop, qual, truelab, falselab, extent)
6315 char *stop;
6316 int qual;
6317 const char *truelab;
6318 const char *falselab;
6319 int extent;
6320{
6321 int c;
6322 int cc;
6323 char *leftstart;
6324 char *leftstop;
6325 char *rightstart;
6326 char *rightstop;
6327
6328 c = *stop;
6329 *stop = '\0';
6330
6331 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6332 &rightstart, &rightstop))
6333 {
6334 *stop = c;
6335 return;
6336 }
6337
6338 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6339 {
6340 const char *flab;
6341
6342 if (falselab != NULL)
6343 flab = falselab;
6344 else
6345 flab = mri_control_label ();
6346
6347 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6348 rightstop, (const char *) NULL, flab, extent);
6349
6350 input_line_pointer += 3;
6351 if (*input_line_pointer != '.'
6352 || input_line_pointer[1] == '\0')
6353 qual = '\0';
6354 else
6355 {
6356 qual = input_line_pointer[1];
6357 input_line_pointer += 2;
6358 }
6359
6360 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6361 &rightstart, &rightstop))
6362 {
6363 *stop = c;
6364 return;
6365 }
6366
6367 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6368 rightstop, truelab, falselab, extent);
6369
6370 if (falselab == NULL)
6371 colon (flab);
6372 }
6373 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6374 {
6375 const char *tlab;
6376
6377 if (truelab != NULL)
6378 tlab = truelab;
6379 else
6380 tlab = mri_control_label ();
6381
6382 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6383 rightstop, tlab, (const char *) NULL, extent);
6384
6385 input_line_pointer += 2;
6386 if (*input_line_pointer != '.'
6387 || input_line_pointer[1] == '\0')
6388 qual = '\0';
6389 else
6390 {
6391 qual = input_line_pointer[1];
6392 input_line_pointer += 2;
6393 }
6394
6395 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6396 &rightstart, &rightstop))
6397 {
6398 *stop = c;
6399 return;
6400 }
6401
6402 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6403 rightstop, truelab, falselab, extent);
6404
6405 if (truelab == NULL)
6406 colon (tlab);
6407 }
6408 else
6409 {
6410 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6411 rightstop, truelab, falselab, extent);
6412 }
6413
6414 *stop = c;
6415 if (input_line_pointer != stop)
6416 as_bad (_("syntax error in structured control directive"));
6417}
6418
6419/* Handle the MRI IF pseudo-op. This may be a structured control
6420 directive, or it may be a regular assembler conditional, depending
6421 on its operands. */
6422
6423static void
6424s_mri_if (qual)
6425 int qual;
6426{
6427 char *s;
6428 int c;
6429 struct mri_control_info *n;
6430
6431 /* A structured control directive must end with THEN with an
6432 optional qualifier. */
6433 s = input_line_pointer;
e1f44d10
NC		 6434 /* We only accept '*' as introduction of comments if preceded by white space
6435 or at first column of a line (I think this can't actually happen here?)
6436 This is important when assembling:
6437 if d0 <ne> 12(a0,d0*2) then
36759679 6438 if d0 <ne> #CONST*20 then. */
e1f44d10
NC		 6439 while ( ! ( is_end_of_line[(unsigned char) *s]
6440 || ( flag_mri
6441 && *s == '*'
6442 && ( s == input_line_pointer
6443 || *(s-1) == ' '
6444 || *(s-1) == '\t'))))
252b5132
RH		 6445 ++s;
6446 --s;
6447 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6448 --s;
6449
6450 if (s - input_line_pointer > 1
6451 && s[-1] == '.')
6452 s -= 2;
6453
6454 if (s - input_line_pointer < 3
6455 || strncasecmp (s - 3, "THEN", 4) != 0)
6456 {
6457 if (qual != '\0')
6458 {
6459 as_bad (_("missing then"));
6460 ignore_rest_of_line ();
6461 return;
6462 }
6463
6464 /* It's a conditional. */
6465 s_if (O_ne);
6466 return;
6467 }
6468
6469 /* Since this might be a conditional if, this pseudo-op will be
6470 called even if we are supported to be ignoring input. Double
6471 check now. Clobber *input_line_pointer so that ignore_input
6472 thinks that this is not a special pseudo-op. */
6473 c = *input_line_pointer;
6474 *input_line_pointer = 0;
6475 if (ignore_input ())
6476 {
6477 *input_line_pointer = c;
6478 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6479 ++input_line_pointer;
6480 demand_empty_rest_of_line ();
6481 return;
6482 }
6483 *input_line_pointer = c;
6484
6485 n = push_mri_control (mri_if);
6486
6487 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6488 n->next, s[1] == '.' ? s[2] : '\0');
6489
6490 if (s[1] == '.')
6491 input_line_pointer = s + 3;
6492 else
6493 input_line_pointer = s + 1;
6494
6495 if (flag_mri)
6496 {
6497 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6498 ++input_line_pointer;
6499 }
6500
6501 demand_empty_rest_of_line ();
6502}
6503
6504/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6505 structured IF, associate the ELSE with the IF. Otherwise, assume
6506 it is a conditional else. */
6507
6508static void
6509s_mri_else (qual)
6510 int qual;
6511{
6512 int c;
6513 char *buf;
6514 char q[2];
6515
6516 if (qual == '\0'
6517 && (mri_control_stack == NULL
6518 || mri_control_stack->type != mri_if
6519 || mri_control_stack->else_seen))
6520 {
6521 s_else (0);
6522 return;
6523 }
6524
6525 c = *input_line_pointer;
6526 *input_line_pointer = 0;
6527 if (ignore_input ())
6528 {
6529 *input_line_pointer = c;
6530 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6531 ++input_line_pointer;
6532 demand_empty_rest_of_line ();
6533 return;
6534 }
6535 *input_line_pointer = c;
6536
6537 if (mri_control_stack == NULL
6538 || mri_control_stack->type != mri_if
6539 || mri_control_stack->else_seen)
6540 {
6541 as_bad (_("else without matching if"));
6542 ignore_rest_of_line ();
6543 return;
6544 }
6545
6546 mri_control_stack->else_seen = 1;
6547
6548 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6549 q[0] = TOLOWER (qual);
252b5132
RH		 6550 q[1] = '\0';
6551 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6552 mri_assemble (buf);
6553 free (buf);
6554
6555 colon (mri_control_stack->next);
6556
6557 if (flag_mri)
6558 {
6559 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6560 ++input_line_pointer;
6561 }
6562
6563 demand_empty_rest_of_line ();
6564}
6565
6566/* Handle the MRI ENDI pseudo-op. */
6567
6568static void
6569s_mri_endi (ignore)
36823076 6570 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6571{
6572 if (mri_control_stack == NULL
6573 || mri_control_stack->type != mri_if)
6574 {
6575 as_bad (_("endi without matching if"));
6576 ignore_rest_of_line ();
6577 return;
6578 }
6579
6580 /* ignore_input will not return true for ENDI, so we don't need to
6581 worry about checking it again here. */
6582
6583 if (! mri_control_stack->else_seen)
6584 colon (mri_control_stack->next);
6585 colon (mri_control_stack->bottom);
6586
6587 pop_mri_control ();
6588
6589 if (flag_mri)
6590 {
6591 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6592 ++input_line_pointer;
6593 }
6594
6595 demand_empty_rest_of_line ();
6596}
6597
6598/* Handle the MRI BREAK pseudo-op. */
6599
6600static void
6601s_mri_break (extent)
6602 int extent;
6603{
6604 struct mri_control_info *n;
6605 char *buf;
6606 char ex[2];
6607
6608 n = mri_control_stack;
6609 while (n != NULL
6610 && n->type != mri_for
6611 && n->type != mri_repeat
6612 && n->type != mri_while)
6613 n = n->outer;
6614 if (n == NULL)
6615 {
6616 as_bad (_("break outside of structured loop"));
6617 ignore_rest_of_line ();
6618 return;
6619 }
6620
6621 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6622 ex[0] = TOLOWER (extent);
252b5132
RH		 6623 ex[1] = '\0';
6624 sprintf (buf, "bra%s %s", ex, n->bottom);
6625 mri_assemble (buf);
6626 free (buf);
6627
6628 if (flag_mri)
6629 {
6630 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6631 ++input_line_pointer;
6632 }
6633
6634 demand_empty_rest_of_line ();
6635}
6636
6637/* Handle the MRI NEXT pseudo-op. */
6638
6639static void
6640s_mri_next (extent)
6641 int extent;
6642{
6643 struct mri_control_info *n;
6644 char *buf;
6645 char ex[2];
6646
6647 n = mri_control_stack;
6648 while (n != NULL
6649 && n->type != mri_for
6650 && n->type != mri_repeat
6651 && n->type != mri_while)
6652 n = n->outer;
6653 if (n == NULL)
6654 {
6655 as_bad (_("next outside of structured loop"));
6656 ignore_rest_of_line ();
6657 return;
6658 }
6659
6660 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6661 ex[0] = TOLOWER (extent);
252b5132
RH		 6662 ex[1] = '\0';
6663 sprintf (buf, "bra%s %s", ex, n->next);
6664 mri_assemble (buf);
6665 free (buf);
6666
6667 if (flag_mri)
6668 {
6669 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6670 ++input_line_pointer;
6671 }
6672
6673 demand_empty_rest_of_line ();
6674}
6675
6676/* Handle the MRI FOR pseudo-op. */
6677
6678static void
6679s_mri_for (qual)
6680 int qual;
6681{
6682 const char *varstart, *varstop;
6683 const char *initstart, *initstop;
6684 const char *endstart, *endstop;
6685 const char *bystart, *bystop;
6686 int up;
6687 int by;
6688 int extent;
6689 struct mri_control_info *n;
6690 char *buf;
6691 char *s;
6692 char ex[2];
6693
6694 /* The syntax is
6695 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6696 */
6697
6698 SKIP_WHITESPACE ();
6699 varstart = input_line_pointer;
6700
6701 /* Look for the '='. */
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6703 && *input_line_pointer != '=')
6704 ++input_line_pointer;
6705 if (*input_line_pointer != '=')
6706 {
6707 as_bad (_("missing ="));
6708 ignore_rest_of_line ();
6709 return;
6710 }
6711
6712 varstop = input_line_pointer;
6713 if (varstop > varstart
6714 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6715 --varstop;
6716
6717 ++input_line_pointer;
6718
6719 initstart = input_line_pointer;
6720
6721 /* Look for TO or DOWNTO. */
6722 up = 1;
6723 initstop = NULL;
6724 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6725 {
6726 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6727 && ! is_part_of_name (input_line_pointer[2]))
6728 {
6729 initstop = input_line_pointer;
6730 input_line_pointer += 2;
6731 break;
6732 }
6733 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6734 && ! is_part_of_name (input_line_pointer[6]))
6735 {
6736 initstop = input_line_pointer;
6737 up = 0;
6738 input_line_pointer += 6;
6739 break;
6740 }
6741 ++input_line_pointer;
6742 }
6743 if (initstop == NULL)
6744 {
6745 as_bad (_("missing to or downto"));
6746 ignore_rest_of_line ();
6747 return;
6748 }
6749 if (initstop > initstart
6750 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6751 --initstop;
6752
6753 SKIP_WHITESPACE ();
6754 endstart = input_line_pointer;
6755
6756 /* Look for BY or DO. */
6757 by = 0;
6758 endstop = NULL;
6759 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6760 {
6761 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6762 && ! is_part_of_name (input_line_pointer[2]))
6763 {
6764 endstop = input_line_pointer;
6765 by = 1;
6766 input_line_pointer += 2;
6767 break;
6768 }
6769 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6770 && (input_line_pointer[2] == '.'
6771 || ! is_part_of_name (input_line_pointer[2])))
6772 {
6773 endstop = input_line_pointer;
6774 input_line_pointer += 2;
6775 break;
6776 }
6777 ++input_line_pointer;
6778 }
6779 if (endstop == NULL)
6780 {
6781 as_bad (_("missing do"));
6782 ignore_rest_of_line ();
6783 return;
6784 }
6785 if (endstop > endstart
6786 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6787 --endstop;
6788
6789 if (! by)
6790 {
6791 bystart = "#1";
6792 bystop = bystart + 2;
6793 }
6794 else
6795 {
6796 SKIP_WHITESPACE ();
6797 bystart = input_line_pointer;
6798
6799 /* Look for DO. */
6800 bystop = NULL;
6801 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6802 {
6803 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6804 && (input_line_pointer[2] == '.'
6805 || ! is_part_of_name (input_line_pointer[2])))
6806 {
6807 bystop = input_line_pointer;
6808 input_line_pointer += 2;
6809 break;
6810 }
6811 ++input_line_pointer;
6812 }
6813 if (bystop == NULL)
6814 {
6815 as_bad (_("missing do"));
6816 ignore_rest_of_line ();
6817 return;
6818 }
6819 if (bystop > bystart
6820 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6821 --bystop;
6822 }
6823
6824 if (*input_line_pointer != '.')
6825 extent = '\0';
6826 else
6827 {
6828 extent = input_line_pointer[1];
6829 input_line_pointer += 2;
6830 }
6831
6832 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6833 n = push_mri_control (mri_for);
6834
6835 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6836
36759679 6837 /* Move init,var. */
252b5132
RH		 6838 s = buf;
6839 *s++ = 'm';
6840 *s++ = 'o';
6841 *s++ = 'v';
6842 *s++ = 'e';
6843 if (qual != '\0')
3882b010 6844 *s++ = TOLOWER (qual);
252b5132
RH		 6845 *s++ = ' ';
6846 memcpy (s, initstart, initstop - initstart);
6847 s += initstop - initstart;
6848 *s++ = ',';
6849 memcpy (s, varstart, varstop - varstart);
6850 s += varstop - varstart;
6851 *s = '\0';
6852 mri_assemble (buf);
6853
6854 colon (n->top);
6855
36759679 6856 /* cmp end,var. */
252b5132
RH		 6857 s = buf;
6858 *s++ = 'c';
6859 *s++ = 'm';
6860 *s++ = 'p';
6861 if (qual != '\0')
3882b010 6862 *s++ = TOLOWER (qual);
252b5132
RH		 6863 *s++ = ' ';
6864 memcpy (s, endstart, endstop - endstart);
6865 s += endstop - endstart;
6866 *s++ = ',';
6867 memcpy (s, varstart, varstop - varstart);
6868 s += varstop - varstart;
6869 *s = '\0';
6870 mri_assemble (buf);
6871
36759679 6872 /* bcc bottom. */
3882b010 6873 ex[0] = TOLOWER (extent);
252b5132
RH		 6874 ex[1] = '\0';
6875 if (up)
6876 sprintf (buf, "blt%s %s", ex, n->bottom);
6877 else
6878 sprintf (buf, "bgt%s %s", ex, n->bottom);
6879 mri_assemble (buf);
6880
6881 /* Put together the add or sub instruction used by ENDF. */
6882 s = buf;
6883 if (up)
6884 strcpy (s, "add");
6885 else
6886 strcpy (s, "sub");
6887 s += 3;
6888 if (qual != '\0')
3882b010 6889 *s++ = TOLOWER (qual);
252b5132
RH		 6890 *s++ = ' ';
6891 memcpy (s, bystart, bystop - bystart);
6892 s += bystop - bystart;
6893 *s++ = ',';
6894 memcpy (s, varstart, varstop - varstart);
6895 s += varstop - varstart;
6896 *s = '\0';
6897 n->incr = buf;
6898
6899 if (flag_mri)
6900 {
6901 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6902 ++input_line_pointer;
6903 }
6904
6905 demand_empty_rest_of_line ();
6906}
6907
6908/* Handle the MRI ENDF pseudo-op. */
6909
6910static void
6911s_mri_endf (ignore)
36823076 6912 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6913{
6914 if (mri_control_stack == NULL
6915 || mri_control_stack->type != mri_for)
6916 {
6917 as_bad (_("endf without for"));
6918 ignore_rest_of_line ();
6919 return;
6920 }
6921
6922 colon (mri_control_stack->next);
6923
6924 mri_assemble (mri_control_stack->incr);
6925
6926 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6927 mri_assemble (mri_control_stack->incr);
6928
6929 free (mri_control_stack->incr);
6930
6931 colon (mri_control_stack->bottom);
6932
6933 pop_mri_control ();
6934
6935 if (flag_mri)
6936 {
6937 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6938 ++input_line_pointer;
6939 }
6940
6941 demand_empty_rest_of_line ();
6942}
6943
6944/* Handle the MRI REPEAT pseudo-op. */
6945
6946static void
6947s_mri_repeat (ignore)
36823076 6948 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6949{
6950 struct mri_control_info *n;
6951
6952 n = push_mri_control (mri_repeat);
6953 colon (n->top);
6954 if (flag_mri)
6955 {
6956 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6957 ++input_line_pointer;
6958 }
6959 demand_empty_rest_of_line ();
6960}
6961
6962/* Handle the MRI UNTIL pseudo-op. */
6963
6964static void
6965s_mri_until (qual)
6966 int qual;
6967{
6968 char *s;
6969
6970 if (mri_control_stack == NULL
6971 || mri_control_stack->type != mri_repeat)
6972 {
6973 as_bad (_("until without repeat"));
6974 ignore_rest_of_line ();
6975 return;
6976 }
6977
6978 colon (mri_control_stack->next);
6979
6980 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6981 ;
6982
6983 parse_mri_control_expression (s, qual, (const char *) NULL,
6984 mri_control_stack->top, '\0');
6985
6986 colon (mri_control_stack->bottom);
6987
6988 input_line_pointer = s;
6989
6990 pop_mri_control ();
6991
6992 if (flag_mri)
6993 {
6994 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6995 ++input_line_pointer;
6996 }
6997
6998 demand_empty_rest_of_line ();
6999}
7000
7001/* Handle the MRI WHILE pseudo-op. */
7002
7003static void
7004s_mri_while (qual)
7005 int qual;
7006{
7007 char *s;
7008
7009 struct mri_control_info *n;
7010
7011 s = input_line_pointer;
e1f44d10
NC		 7012 /* We only accept '*' as introduction of comments if preceded by white space
7013 or at first column of a line (I think this can't actually happen here?)
7014 This is important when assembling:
7015 while d0 <ne> 12(a0,d0*2) do
36759679 7016 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7017 while (! (is_end_of_line[(unsigned char) *s]
7018 || (flag_mri
7019 && *s == '*'
7020 && (s == input_line_pointer
7021 || *(s-1) == ' '
7022 || *(s-1) == '\t'))))
252b5132
RH		 7023 s++;
7024 --s;
7025 while (*s == ' ' || *s == '\t')
7026 --s;
7027 if (s - input_line_pointer > 1
7028 && s[-1] == '.')
7029 s -= 2;
7030 if (s - input_line_pointer < 2
7031 || strncasecmp (s - 1, "DO", 2) != 0)
7032 {
7033 as_bad (_("missing do"));
7034 ignore_rest_of_line ();
7035 return;
7036 }
7037
7038 n = push_mri_control (mri_while);
7039
7040 colon (n->next);
7041
7042 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7043 s[1] == '.' ? s[2] : '\0');
7044
7045 input_line_pointer = s + 1;
7046 if (*input_line_pointer == '.')
7047 input_line_pointer += 2;
7048
7049 if (flag_mri)
7050 {
7051 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7052 ++input_line_pointer;
7053 }
7054
7055 demand_empty_rest_of_line ();
7056}
7057
7058/* Handle the MRI ENDW pseudo-op. */
7059
7060static void
7061s_mri_endw (ignore)
36823076 7062 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7063{
7064 char *buf;
7065
7066 if (mri_control_stack == NULL
7067 || mri_control_stack->type != mri_while)
7068 {
7069 as_bad (_("endw without while"));
7070 ignore_rest_of_line ();
7071 return;
7072 }
7073
7074 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7075 sprintf (buf, "bra %s", mri_control_stack->next);
7076 mri_assemble (buf);
7077 free (buf);
7078
7079 colon (mri_control_stack->bottom);
7080
7081 pop_mri_control ();
7082
7083 if (flag_mri)
7084 {
7085 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7086 ++input_line_pointer;
7087 }
7088
7089 demand_empty_rest_of_line ();
7090}
7091\f
7092/*
7093 * md_parse_option
7094 * Invocation line includes a switch not recognized by the base assembler.
7095 * See if it's a processor-specific option. These are:
7096 *
7097 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
7098 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
7099 * Select the architecture. Instructions or features not
7100 * supported by the selected architecture cause fatal
7101 * errors. More than one may be specified. The default is
7102 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
7103 * for -m68000, and -m68882 is a synonym for -m68881.
7104 * -[A]m[c]no-68851, -[A]m[c]no-68881
7105 * Don't accept 688?1 instructions. (The "c" is kind of silly,
7106 * so don't use or document it, but that's the way the parsing
7107 * works).
7108 *
7109 * -pic Indicates PIC.
7110 * -k Indicates PIC. (Sun 3 only.)
28e7409f 7111 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 7112 *
7113 * --bitwise-or
7114 * Permit `|' to be used in expressions.
7115 *
7116 */
7117
7118#ifdef OBJ_ELF
5a38dc70 7119const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7120#else
5a38dc70 7121const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7122#endif
7123
7124struct option md_longopts[] = {
7125#define OPTION_PIC (OPTION_MD_BASE)
7126 {"pic", no_argument, NULL, OPTION_PIC},
7127#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7128 {"register-prefix-optional", no_argument, NULL,
7129 OPTION_REGISTER_PREFIX_OPTIONAL},
7130#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7131 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7132#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7133 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7134#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7135 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7136#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7137 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7138#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7139 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7140#define OPTION_PCREL (OPTION_MD_BASE + 7)
7141 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7142 {NULL, no_argument, NULL, 0}
7143};
bc805888 7144size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7145
7146int
7147md_parse_option (c, arg)
7148 int c;
7149 char *arg;
7150{
7151 switch (c)
7152 {
7153 case 'l': /* -l means keep external to 2 bit offset
36759679 7154 rather than 16 bit one. */
252b5132
RH		 7155 flag_short_refs = 1;
7156 break;
7157
7158 case 'S': /* -S means that jbsr's always turn into
7159 jsr's. */
7160 flag_long_jumps = 1;
7161 break;
7162
28e7409f
NC		 7163 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7164 branches into absolute jumps. */
7165 flag_keep_pcrel = 1;
7166 break;
7167
252b5132
RH		 7168 case 'A':
7169 if (*arg == 'm')
8a104df9 7170 arg++;
36759679 7171 /* Intentional fall-through. */
252b5132
RH		 7172 case 'm':
7173
7174 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7175 {
7176 int i;
7177 unsigned long arch;
7178 const char *oarg = arg;
7179
7180 arg += 3;
7181 if (*arg == 'm')
7182 {
7183 arg++;
7184 if (arg[0] == 'c' && arg[1] == '6')
7185 arg++;
7186 }
7187 for (i = 0; i < n_archs; i++)
7188 if (!strcmp (arg, archs[i].name))
7189 break;
7190 if (i == n_archs)
7191 {
7192 unknown:
7193 as_bad (_("unrecognized option `%s'"), oarg);
7194 return 0;
7195 }
7196 arch = archs[i].arch;
7197 if (arch == m68881)
7198 no_68881 = 1;
7199 else if (arch == m68851)
7200 no_68851 = 1;
7201 else
7202 goto unknown;
7203 }
7204 else
7205 {
7206 int i;
7207
7208 if (arg[0] == 'c' && arg[1] == '6')
7209 arg++;
7210
7211 for (i = 0; i < n_archs; i++)
7212 if (!strcmp (arg, archs[i].name))
7213 {
7214 unsigned long arch = archs[i].arch;
7215 if (cpu_of_arch (arch))
7216 /* It's a cpu spec. */
7217 {
7218 current_architecture &= ~m68000up;
7219 current_architecture |= arch;
6b6e92f4 7220 current_chip |= archs[i].chip;
252b5132
RH		 7221 }
7222 else if (arch == m68881)
7223 {
7224 current_architecture |= m68881;
7225 no_68881 = 0;
7226 }
7227 else if (arch == m68851)
7228 {
7229 current_architecture |= m68851;
7230 no_68851 = 0;
7231 }
7232 else
7233 /* ??? */
7234 abort ();
7235 break;
7236 }
7237 if (i == n_archs)
7238 {
7239 as_bad (_("unrecognized architecture specification `%s'"), arg);
7240 return 0;
7241 }
7242 }
7243 break;
7244
7245 case OPTION_PIC:
7246 case 'k':
7247 flag_want_pic = 1;
36759679 7248 break; /* -pic, Position Independent Code. */
252b5132
RH		 7249
7250 case OPTION_REGISTER_PREFIX_OPTIONAL:
7251 flag_reg_prefix_optional = 1;
7252 reg_prefix_optional_seen = 1;
7253 break;
7254
7255 /* -V: SVR4 argument to print version ID. */
7256 case 'V':
7257 print_version_id ();
7258 break;
7259
7260 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7261 should be emitted or not. FIXME: Not implemented. */
7262 case 'Q':
7263 break;
7264
7265 case OPTION_BITWISE_OR:
7266 {
7267 char *n, *t;
7268 const char *s;
7269
7270 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7271 t = n;
7272 for (s = m68k_comment_chars; *s != '\0'; s++)
7273 if (*s != '|')
7274 *t++ = *s;
7275 *t = '\0';
7276 m68k_comment_chars = n;
7277 }
7278 break;
7279
7280 case OPTION_BASE_SIZE_DEFAULT_16:
7281 m68k_index_width_default = SIZE_WORD;
7282 break;
7283
7284 case OPTION_BASE_SIZE_DEFAULT_32:
7285 m68k_index_width_default = SIZE_LONG;
7286 break;
7287
7288 case OPTION_DISP_SIZE_DEFAULT_16:
7289 m68k_rel32 = 0;
7290 m68k_rel32_from_cmdline = 1;
7291 break;
7292
7293 case OPTION_DISP_SIZE_DEFAULT_32:
7294 m68k_rel32 = 1;
7295 m68k_rel32_from_cmdline = 1;
7296 break;
7297
7298 default:
7299 return 0;
7300 }
7301
7302 return 1;
7303}
7304
7305void
7306md_show_usage (stream)
7307 FILE *stream;
7308{
76f57f3a 7309 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7310 int i;
7311 unsigned int default_arch;
76f57f3a 7312
8a104df9 7313 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7314 if (*default_cpu == 'm')
7315 default_cpu++;
7316 for (i = 0; i < n_archs; i++)
7317 {
7318 if (strcasecmp (default_cpu, archs[i].name) == 0)
7319 {
7320 default_arch = archs[i].arch;
7321 for (i = 0; i < n_archs; i++)
7322 {
7323 if (archs[i].arch == default_arch
7324 && !archs[i].alias)
7325 {
7326 default_cpu = archs[i].name;
7327 break;
7328 }
7329 }
7330 }
7331 }
7332
bc805888 7333 fprintf (stream, _("\
252b5132
RH		 7334680X0 options:\n\
7335-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 7336-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7337-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6b6e92f4
NC		 7338-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7339-m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
76f57f3a 7340 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 7341-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7342 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 7343 [default yes for 68020, 68030, and cpu32]\n"),
7344 default_cpu);
bc805888 7345 fprintf (stream, _("\
252b5132
RH		 7346-m68851 | -mno-68851\n\
7347 target has/lacks memory-management unit coprocessor\n\
7348 [default yes for 68020 and up]\n\
7349-pic, -k generate position independent code\n\
7350-S turn jbsr into jsr\n\
28e7409f 7351--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7352--register-prefix-optional\n\
7353 recognize register names without prefix character\n\
7354--bitwise-or do not treat `|' as a comment character\n"));
7355 fprintf (stream, _("\
7356--base-size-default-16 base reg without size is 16 bits\n\
7357--base-size-default-32 base reg without size is 32 bits (default)\n\
7358--disp-size-default-16 displacement with unknown size is 16 bits\n\
7359--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7360}
7361\f
7362#ifdef TEST2
7363
7364/* TEST2: Test md_assemble() */
36759679
NC		 7365/* Warning, this routine probably doesn't work anymore. */
7366int
252b5132
RH		 7367main ()
7368{
7369 struct m68k_it the_ins;
7370 char buf[120];
7371 char *cp;
7372 int n;
7373
7374 m68k_ip_begin ();
7375 for (;;)
7376 {
7377 if (!gets (buf) || !*buf)
7378 break;
7379 if (buf[0] == '|' || buf[1] == '.')
7380 continue;
7381 for (cp = buf; *cp; cp++)
7382 if (*cp == '\t')
7383 *cp = ' ';
7384 if (is_label (buf))
7385 continue;
7386 memset (&the_ins, '\0', sizeof (the_ins));
7387 m68k_ip (&the_ins, buf);
7388 if (the_ins.error)
7389 {
7390 printf (_("Error %s in %s\n"), the_ins.error, buf);
7391 }
7392 else
7393 {
7394 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7395 for (n = 0; n < the_ins.numo; n++)
7396 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7397 printf (" ");
7398 print_the_insn (&the_ins.opcode[0], stdout);
7399 (void) putchar ('\n');
7400 }
7401 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7402 {
7403 if (the_ins.operands[n].error)
7404 {
7405 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7406 continue;
7407 }
7408 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7409 if (the_ins.operands[n].b_const)
7410 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7411 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7412 if (the_ins.operands[n].b_iadd)
7413 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7414 (void) putchar ('\n');
7415 }
7416 }
7417 m68k_ip_end ();
7418 return 0;
7419}
7420
7421is_label (str)
7422 char *str;
7423{
7424 while (*str == ' ')
7425 str++;
7426 while (*str && *str != ' ')
7427 str++;
7428 if (str[-1] == ':' || str[1] == '=')
7429 return 1;
7430 return 0;
7431}
7432
7433#endif
7434
7435/* Possible states for relaxation:
7436
7437 0 0 branch offset byte (bra, etc)
7438 0 1 word
7439 0 2 long
7440
7441 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7442 1 1 word
7443 1 2 long
7444
7445 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7446 2 1 word-long
7447 2 2 long-word
7448 2 3 long-long
7449
7450 */
7451
7452/* We have no need to default values of symbols. */
7453
252b5132
RH		 7454symbolS *
7455md_undefined_symbol (name)
36823076 7456 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7457{
7458 return 0;
7459}
7460
7461/* Round up a section size to the appropriate boundary. */
7462valueT
7463md_section_align (segment, size)
36823076 7464 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7465 valueT size;
7466{
7467#ifdef OBJ_AOUT
7468#ifdef BFD_ASSEMBLER
7469 /* For a.out, force the section size to be aligned. If we don't do
7470 this, BFD will align it for us, but it will not write out the
7471 final bytes of the section. This may be a bug in BFD, but it is
7472 easier to fix it here since that is how the other a.out targets
7473 work. */
7474 int align;
7475
7476 align = bfd_get_section_alignment (stdoutput, segment);
7477 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7478#endif
7479#endif
7480
7481 return size;
7482}
7483
7484/* Exactly what point is a PC-relative offset relative TO?
7485 On the 68k, it is relative to the address of the first extension
7486 word. The difference between the addresses of the offset and the
92774660 7487 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7488long
7489md_pcrel_from (fixP)
7490 fixS *fixP;
7491{
7492 int adjust;
7493
8390138c
AS		 7494 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7495 sign extend the value here. */
7496 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7497 if (adjust == 64)
7498 adjust = -1;
7499 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7500}
7501
7502#ifndef BFD_ASSEMBLER
7503#ifdef OBJ_COFF
7504
252b5132
RH		 7505void
7506tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7507 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7508{
7509}
7510
7511int
7512tc_coff_sizemachdep (frag)
7513 fragS *frag;
7514{
7515 switch (frag->fr_subtype & 0x3)
7516 {
7517 case BYTE:
7518 return 1;
7519 case SHORT:
7520 return 2;
7521 case LONG:
7522 return 4;
7523 default:
7524 abort ();
7525 return 0;
7526 }
7527}
7528
7529#endif
7530#endif
0d96863f 7531#ifdef OBJ_ELF
8a104df9
KH		 7532void
7533m68k_elf_final_processing ()
0d96863f 7534{
36759679 7535 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9
KH		 7536 if (cpu_of_arch (current_architecture) & cpu32)
7537 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7538 else if ((cpu_of_arch (current_architecture) & m68000up)
7539 && !(cpu_of_arch (current_architecture) & m68020up))
7540 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7541}
7542#endif
c04898f8
AS		 7543
7544int
7545tc_m68k_regname_to_dw2regnum (const char *regname)
7546{
7547 unsigned int regnum;
7548 static const char *const regnames[] =
7549 {
7550 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7551 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7552 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7553 "pc"
7554 };
7555
7556 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7557 if (strcmp (regname, regnames[regnum]) == 0)
7558 return regnum;
7559
7560 return -1;
7561}
7562
7563void
7564tc_m68k_frame_initial_instructions (void)
7565{
7566 static int sp_regno = -1;
7567
7568 if (sp_regno < 0)
7569 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7570
7571 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7572 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7573}
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