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* gas/all/gas.exp: Remove a29k and m88k support.
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
f17c130b 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
36759679 73const int md_reloc_size = 8; /* Size of relocation record. */
252b5132
RH		 74
75/* Are we trying to generate PIC code? If so, absolute references
76 ought to be made into linkage table references or pc-relative
92774660 77 references. Not implemented. For ELF there are other means
252b5132
RH		 78 to denote pic relocations. */
79int flag_want_pic;
80
36759679
NC		 81static int flag_short_refs; /* -l option. */
82static int flag_long_jumps; /* -S option. */
28e7409f 83static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 84
85#ifdef REGISTER_PREFIX_OPTIONAL
86int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
87#else
88int flag_reg_prefix_optional;
89#endif
90
91/* Whether --register-prefix-optional was used on the command line. */
92static int reg_prefix_optional_seen;
93
94/* The floating point coprocessor to use by default. */
95static enum m68k_register m68k_float_copnum = COP1;
96
97/* If this is non-zero, then references to number(%pc) will be taken
98 to refer to number, rather than to %pc + number. */
99static int m68k_abspcadd;
100
101/* If this is non-zero, then the quick forms of the move, add, and sub
102 instructions are used when possible. */
103static int m68k_quick = 1;
104
105/* If this is non-zero, then if the size is not specified for a base
106 or outer displacement, the assembler assumes that the size should
107 be 32 bits. */
108static int m68k_rel32 = 1;
109
110/* This is non-zero if m68k_rel32 was set from the command line. */
111static int m68k_rel32_from_cmdline;
112
113/* The default width to use for an index register when using a base
114 displacement. */
115static enum m68k_size m68k_index_width_default = SIZE_LONG;
116
117/* We want to warn if any text labels are misaligned. In order to get
118 the right line number, we need to record the line number for each
119 label. */
252b5132
RH		 120struct label_line
121{
122 struct label_line *next;
123 symbolS *label;
124 char *file;
125 unsigned int line;
126 int text;
127};
128
129/* The list of labels. */
130
131static struct label_line *labels;
132
133/* The current label. */
134
135static struct label_line *current_label;
136
60fed2d3
NC		 137/* Pointer to list holding the opcodes sorted by name. */
138static struct m68k_opcode const ** m68k_sorted_opcodes;
139
36759679
NC		 140/* Its an arbitrary name: This means I don't approve of it.
141 See flames below. */
252b5132
RH		 142static struct obstack robyn;
143
252b5132
RH		 144struct m68k_incant
145 {
146 const char *m_operands;
147 unsigned long m_opcode;
148 short m_opnum;
149 short m_codenum;
150 int m_arch;
151 struct m68k_incant *m_next;
152 };
153
154#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
155#define gettwo(x) (((x)->m_opcode)&0xffff)
156
157static const enum m68k_register m68000_control_regs[] = { 0 };
158static const enum m68k_register m68010_control_regs[] = {
159 SFC, DFC, USP, VBR,
160 0
161};
162static const enum m68k_register m68020_control_regs[] = {
163 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
164 0
165};
166static const enum m68k_register m68040_control_regs[] = {
167 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
168 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
169 0
170};
171static const enum m68k_register m68060_control_regs[] = {
172 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
173 USP, VBR, URP, SRP, PCR,
174 0
175};
6da466c7 176static const enum m68k_register mcf_control_regs[] = {
3e602632 177 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 178 RAMBAR0, RAMBAR1, MBAR,
179 0
180};
e80e0390
NC		 181static const enum m68k_register mcf5249_control_regs[] = {
182 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR1, MBAR, MBAR2,
183 0
184};
3e602632
NC		 185static const enum m68k_register mcf528x_control_regs[] = {
186 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
187 0
188};
189static const enum m68k_register mcfv4e_control_regs[] = {
190 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
191 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
192 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
193 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
194 0
195};
252b5132
RH		 196#define cpu32_control_regs m68010_control_regs
197
198static const enum m68k_register *control_regs;
199
36759679 200/* Internal form of a 68020 instruction. */
252b5132
RH		 201struct m68k_it
202{
203 const char *error;
36759679 204 const char *args; /* List of opcode info. */
252b5132
RH		 205 int numargs;
206
36759679 207 int numo; /* Number of shorts in opcode. */
252b5132
RH		 208 short opcode[11];
209
210 struct m68k_op operands[6];
211
36759679 212 int nexp; /* Number of exprs in use. */
252b5132
RH		 213 struct m68k_exp exprs[4];
214
36759679 215 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 216 struct
217 {
36759679 218 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 219 symbolS *fadd;
220 offsetT foff;
221 int fragty;
222 }
223 fragb[4];
224
36759679 225 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 226 struct
227 {
228 int n;
229 expressionS exp;
230 char wid;
231 char pcrel;
232 /* In a pc relative address the difference between the address
233 of the offset and the address that the offset is relative
234 to. This depends on the addressing mode. Basically this
235 is the value to put in the offset field to address the
236 first byte of the offset, without regarding the special
237 significance of some values (in the branch instruction, for
238 example). */
239 int pcrel_fix;
240#ifdef OBJ_ELF
241 /* Whether this expression needs special pic relocation, and if
242 so, which. */
243 enum pic_relocation pic_reloc;
244#endif
245 }
36759679 246 reloc[5]; /* Five is enough??? */
252b5132
RH		 247};
248
6b6e92f4 249#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
252b5132
RH		 250#define float_of_arch(x) ((x) & mfloat)
251#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 252#define arch_coldfire_p(x) ((x) & mcfisa_a)
253#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 254
36759679 255/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 256#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 257
36759679 258static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 259
260#define op(ex) ((ex)->exp.X_op)
261#define adds(ex) ((ex)->exp.X_add_symbol)
262#define subs(ex) ((ex)->exp.X_op_symbol)
263#define offs(ex) ((ex)->exp.X_add_number)
264
36759679 265/* Macros for adding things to the m68k_it struct. */
31302357 266#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 267
36759679
NC		 268/* Like addword, but goes BEFORE general operands. */
269
252b5132 270static void
31302357 271insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 272{
273 int z;
07726851 274 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 275 the_ins.opcode[z] = the_ins.opcode[z - 1];
276 for (z = 0; z < the_ins.nrel; z++)
277 the_ins.reloc[z].n += 2;
252b5132
RH		 278 for (z = 0; z < the_ins.nfrag; z++)
279 the_ins.fragb[z].fragoff++;
8a104df9 280 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 281 the_ins.numo++;
282}
283
284/* The numo+1 kludge is so we can hit the low order byte of the prev word.
285 Blecch. */
286static void
31302357 287add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 288{
31302357
AS		 289 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
290 ? the_ins.numo * 2 - 1
291 : (width == 'b'
292 ? the_ins.numo * 2 + 1
293 : the_ins.numo * 2));
252b5132
RH		 294 the_ins.reloc[the_ins.nrel].exp = exp->exp;
295 the_ins.reloc[the_ins.nrel].wid = width;
296 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
297#ifdef OBJ_ELF
298 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
299#endif
300 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
301}
302
303/* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
307
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
311
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
313static void
31302357 314add_frag (symbolS *add, offsetT off, int type)
252b5132 315{
8a104df9
KH		 316 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
317 the_ins.fragb[the_ins.nfrag].fadd = add;
318 the_ins.fragb[the_ins.nfrag].foff = off;
319 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 320}
321
322#define isvar(ex) \
323 (op (ex) != O_constant && op (ex) != O_big)
324
31302357
AS		 325static char *crack_operand (char *str, struct m68k_op *opP);
326static int get_num (struct m68k_exp *exp, int ok);
327static int reverse_16_bits (int in);
328static int reverse_8_bits (int in);
329static void install_gen_operand (int mode, int val);
330static void install_operand (int mode, int val);
331static void s_bss (int);
332static void s_data1 (int);
333static void s_data2 (int);
334static void s_even (int);
335static void s_proc (int);
336static void s_chip (int);
337static void s_fopt (int);
338static void s_opt (int);
339static void s_reg (int);
340static void s_restore (int);
341static void s_save (int);
342static void s_mri_if (int);
343static void s_mri_else (int);
344static void s_mri_endi (int);
345static void s_mri_break (int);
346static void s_mri_next (int);
347static void s_mri_for (int);
348static void s_mri_endf (int);
349static void s_mri_repeat (int);
350static void s_mri_until (int);
351static void s_mri_while (int);
352static void s_mri_endw (int);
252b5132
RH		 353
354static int current_architecture;
6b6e92f4 355static int current_chip;
252b5132 356
dc84e067
NC		 357struct m68k_cpu
358 {
359 unsigned long arch;
6b6e92f4 360 unsigned long chip;
dc84e067
NC		 361 const char *name;
362 int alias;
363 };
252b5132 364
dc84e067
NC		 365static const struct m68k_cpu archs[] =
366 {
6b6e92f4
NC		 367 { m68000, m68000, "68000", 0 },
368 { m68010, m68010, "68010", 0 },
369 { m68020, m68020, "68020", 0 },
370 { m68030, m68030, "68030", 0 },
371 { m68040, m68040, "68040", 0 },
372 { m68060, m68060, "68060", 0 },
373 { cpu32, cpu32, "cpu32", 0 },
374 { m68881, m68881, "68881", 0 },
375 { m68851, m68851, "68851", 0 },
376 { mcfisa_a, mcf5200, "5200", 0 },
377 { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
378 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
379 { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
380 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
381 { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
382 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
383 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
384 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
dc84e067
NC		 385 /* Aliases (effectively, so far as gas is concerned) for the above
386 cpus. */
6b6e92f4
NC		 387 { m68020, m68020, "68k", 1 },
388 { m68000, m68000, "68008", 1 },
389 { m68000, m68000, "68302", 1 },
390 { m68000, m68000, "68306", 1 },
391 { m68000, m68000, "68307", 1 },
392 { m68000, m68000, "68322", 1 },
393 { m68000, m68000, "68356", 1 },
394 { m68000, m68000, "68ec000", 1 },
395 { m68000, m68000, "68hc000", 1 },
396 { m68000, m68000, "68hc001", 1 },
397 { m68020, m68020, "68ec020", 1 },
398 { m68030, m68030, "68ec030", 1 },
399 { m68040, m68040, "68ec040", 1 },
400 { m68060, m68060, "68ec060", 1 },
401 { cpu32, cpu32, "68330", 1 },
402 { cpu32, cpu32, "68331", 1 },
403 { cpu32, cpu32, "68332", 1 },
404 { cpu32, cpu32, "68333", 1 },
405 { cpu32, cpu32, "68334", 1 },
406 { cpu32, cpu32, "68336", 1 },
407 { cpu32, cpu32, "68340", 1 },
408 { cpu32, cpu32, "68341", 1 },
409 { cpu32, cpu32, "68349", 1 },
410 { cpu32, cpu32, "68360", 1 },
411 { m68881, m68881, "68882", 1 },
412 { mcfisa_a, mcf5200, "5202", 1 },
413 { mcfisa_a, mcf5200, "5204", 1 },
414 { mcfisa_a, mcf5200, "5206", 1 },
415 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
416 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
417 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
418 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
419 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
420 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
421 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
422 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
423 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
424 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
425 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
426 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
427 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
428 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
429 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
430 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
431 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
432 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
433 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
dc84e067 434 };
252b5132
RH		 435
436static const int n_archs = sizeof (archs) / sizeof (archs[0]);
437
151337e8
NC		 438/* This is the assembler relaxation table for m68k. m68k is a rich CISC
439 architecture and we have a lot of relaxation modes. */
252b5132 440
151337e8
NC		 441/* Macros used in the relaxation code. */
442#define TAB(x,y) (((x) << 2) + (y))
443#define TABTYPE(x) ((x) >> 2)
444
445/* Relaxation states. */
446#define BYTE 0
447#define SHORT 1
448#define LONG 2
449#define SZ_UNDEF 3
450
451/* Here are all the relaxation modes we support. First we can relax ordinary
452 branches. On 68020 and higher and on CPU32 all branch instructions take
453 three forms, so on these CPUs all branches always remain as such. When we
454 have to expand to the LONG form on a 68000, though, we substitute an
455 absolute jump instead. This is a direct replacement for unconditional
456 branches and a branch over a jump for conditional branches. However, if the
457 user requires PIC and disables this with --pcrel, we can only relax between
458 BYTE and SHORT forms, punting if that isn't enough. This gives us four
459 different relaxation modes for branches: */
460
36759679
NC		 461#define BRANCHBWL 0 /* Branch byte, word, or long. */
462#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
463#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
464#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 465
466/* We also relax coprocessor branches and DBcc's. All CPUs that support
467 coprocessor branches support them in word and long forms, so we have only
468 one relaxation mode for them. DBcc's are word only on all CPUs. We can
469 relax them to the LONG form with a branch-around sequence. This sequence
470 can use a long branch (if available) or an absolute jump (if acceptable).
471 This gives us two relaxation modes. If long branches are not available and
472 absolute jumps are not acceptable, we don't relax DBcc's. */
473
36759679
NC		 474#define FBRANCH 4 /* Coprocessor branch. */
475#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
476#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 477
478/* That's all for instruction relaxation. However, we also relax PC-relative
479 operands. Specifically, we have three operand relaxation modes. On the
480 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
481 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
482 two. Also PC+displacement+index operands in their simple form (with a non-
483 suppressed index without memory indirection) are supported on all CPUs, but
484 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
485 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
486 form of the PC+displacement+index operand. Finally, some absolute operands
487 can be relaxed down to 16-bit PC-relative. */
488
36759679
NC		 489#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
490#define PCINDEX 8 /* PC + displacement + index. */
491#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 492
493/* Note that calls to frag_var need to specify the maximum expansion
494 needed; this is currently 10 bytes for DBCC. */
495
496/* The fields are:
497 How far Forward this mode will reach:
498 How far Backward this mode will reach:
499 How many bytes this mode will add to the size of the frag
500 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 501
502 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 503relax_typeS md_relax_table[] =
504{
ac62c346
AM		 505 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
506 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
507 { 0, 0, 4, 0 },
508 { 1, 1, 0, 0 },
509
510 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
511 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
512 { 0, 0, 4, 0 },
513 { 1, 1, 0, 0 },
514
515 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
516 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
517 { 0, 0, 6, 0 },
518 { 1, 1, 0, 0 },
519
520 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
521 { 0, 0, 2, 0 },
522 { 1, 1, 0, 0 },
523 { 1, 1, 0, 0 },
524
36759679 525 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 526 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
527 { 0, 0, 4, 0 },
528 { 1, 1, 0, 0 },
529
36759679 530 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 531 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
532 { 0, 0, 10, 0 },
533 { 1, 1, 0, 0 },
534
36759679 535 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 536 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
537 { 0, 0, 10, 0 },
538 { 1, 1, 0, 0 },
539
36759679 540 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 541 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
542 { 0, 0, 6, 0 },
543 { 1, 1, 0, 0 },
544
545 { 125, -130, 0, TAB (PCINDEX, SHORT) },
546 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
547 { 0, 0, 4, 0 },
548 { 1, 1, 0, 0 },
549
36759679 550 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 551 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
552 { 0, 0, 4, 0 },
553 { 1, 1, 0, 0 },
252b5132
RH		 554};
555
556/* These are the machine dependent pseudo-ops. These are included so
557 the assembler can work on the output from the SUN C compiler, which
36759679 558 generates these. */
252b5132
RH		 559
560/* This table describes all the machine specific pseudo-ops the assembler
561 has to support. The fields are:
562 pseudo-op name without dot
563 function to call to execute this pseudo-op
36759679 564 Integer arg to pass to the function. */
252b5132
RH		 565const pseudo_typeS md_pseudo_table[] =
566{
567 {"data1", s_data1, 0},
568 {"data2", s_data2, 0},
569 {"bss", s_bss, 0},
570 {"even", s_even, 0},
571 {"skip", s_space, 0},
572 {"proc", s_proc, 0},
573#if defined (TE_SUN3) || defined (OBJ_ELF)
574 {"align", s_align_bytes, 0},
575#endif
576#ifdef OBJ_ELF
577 {"swbeg", s_ignore, 0},
578#endif
579 {"extend", float_cons, 'x'},
580 {"ldouble", float_cons, 'x'},
581
582 /* The following pseudo-ops are supported for MRI compatibility. */
583 {"chip", s_chip, 0},
584 {"comline", s_space, 1},
585 {"fopt", s_fopt, 0},
586 {"mask2", s_ignore, 0},
587 {"opt", s_opt, 0},
588 {"reg", s_reg, 0},
589 {"restore", s_restore, 0},
590 {"save", s_save, 0},
591
592 {"if", s_mri_if, 0},
593 {"if.b", s_mri_if, 'b'},
594 {"if.w", s_mri_if, 'w'},
595 {"if.l", s_mri_if, 'l'},
596 {"else", s_mri_else, 0},
597 {"else.s", s_mri_else, 's'},
598 {"else.l", s_mri_else, 'l'},
599 {"endi", s_mri_endi, 0},
600 {"break", s_mri_break, 0},
601 {"break.s", s_mri_break, 's'},
602 {"break.l", s_mri_break, 'l'},
603 {"next", s_mri_next, 0},
604 {"next.s", s_mri_next, 's'},
605 {"next.l", s_mri_next, 'l'},
606 {"for", s_mri_for, 0},
607 {"for.b", s_mri_for, 'b'},
608 {"for.w", s_mri_for, 'w'},
609 {"for.l", s_mri_for, 'l'},
610 {"endf", s_mri_endf, 0},
611 {"repeat", s_mri_repeat, 0},
612 {"until", s_mri_until, 0},
613 {"until.b", s_mri_until, 'b'},
614 {"until.w", s_mri_until, 'w'},
615 {"until.l", s_mri_until, 'l'},
616 {"while", s_mri_while, 0},
617 {"while.b", s_mri_while, 'b'},
618 {"while.w", s_mri_while, 'w'},
619 {"while.l", s_mri_while, 'l'},
620 {"endw", s_mri_endw, 0},
621
622 {0, 0, 0}
623};
624
252b5132 625/* The mote pseudo ops are put into the opcode table, since they
31302357 626 don't start with a . they look like opcodes to gas. */
252b5132 627
5a38dc70 628const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 629{
630
631 {"dcl", cons, 4},
632 {"dc", cons, 2},
633 {"dcw", cons, 2},
634 {"dcb", cons, 1},
635
636 {"dsl", s_space, 4},
637 {"ds", s_space, 2},
638 {"dsw", s_space, 2},
639 {"dsb", s_space, 1},
640
641 {"xdef", s_globl, 0},
642#ifdef OBJ_ELF
643 {"align", s_align_bytes, 0},
644#else
645 {"align", s_align_ptwo, 0},
646#endif
647#ifdef M68KCOFF
648 {"sect", obj_coff_section, 0},
649 {"section", obj_coff_section, 0},
650#endif
651 {0, 0, 0}
652};
653
bd17c2c3
AM		 654/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
655 gives identical results to a 32-bit host. */
656#define TRUNC(X) ((valueT) (X) & 0xffffffff)
657#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
658
659#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
660#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
661#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
662#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
663
664#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
665#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 666#define islong(x) (1)
667
252b5132
RH		 668static char notend_table[256];
669static char alt_notend_table[256];
670#define notend(s) \
671 (! (notend_table[(unsigned char) *s] \
672 || (*s == ':' \
673 && alt_notend_table[(unsigned char) s[1]])))
674
6b6e92f4
NC		 675/* Return a human readable string holding the list of chips that are
676 valid for a particular architecture, suppressing aliases (unless
677 there is only one of them). */
678
679static char *
680find_cf_chip (int architecture)
681{
682 static char buf[1024];
683 int i, j, n_chips, n_alias;
684 char *cp;
685
686 strcpy (buf, " (");
687 cp = buf + strlen (buf);
688
689 for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
690 if (archs[i].arch & architecture)
691 {
692 n_chips++;
693 if (archs[i].alias)
694 n_alias++;
695 }
696
697 if (n_chips == 0)
698 as_fatal (_("no matching ColdFire architectures found"));
699
700 if (n_alias > 1)
701 n_chips -= n_alias;
702
703 for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
704 if (archs[i].arch & architecture)
705 {
706 if (j)
707 {
31302357 708 if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias)
6b6e92f4
NC		 709 {
710 if (n_chips == 2)
711 {
712 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
713 cp += strlen (cp);
714 }
715 else
716 {
717 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
718 cp += strlen (cp);
719 }
720 }
721 else
722 {
723 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
724 cp += strlen (cp);
725 }
726 }
727 strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
728 cp += strlen (cp);
729 j++;
730 }
731
732 if (n_alias > 1)
733 {
734 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
735 cp += strlen (cp);
736 }
737
738 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
739
740 return buf;
741}
742
252b5132
RH		 743#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
744
745#ifdef NO_PCREL_RELOCS
746
747int
31302357 748make_pcrel_absolute (fixS *fixP, long *add_number)
252b5132
RH		 749{
750 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
751
36759679 752 /* Rewrite the PC relative instructions to absolute address ones.
67c1ffbe 753 these are rumored to be faster, and the apollo linker refuses
36759679
NC		 754 to deal with the PC relative relocations. */
755 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
252b5132 756 {
36759679 757 if (flag_keep_pcrel)
6b6e92f4 758 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 759 opcode[0] = 0x4e;
760 opcode[1] = 0xf9;
761 }
36759679 762 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
252b5132 763 {
36759679 764 if (flag_keep_pcrel)
6b6e92f4 765 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
252b5132
RH		 766 opcode[0] = 0x4e;
767 opcode[1] = 0xb9;
768 }
769 else
770 as_fatal (_("Unknown PC relative instruction"));
771 *add_number -= 4;
772 return 0;
773}
774
775#endif /* NO_PCREL_RELOCS */
776
777short
31302357 778tc_coff_fix2rtype (fixS *fixP)
252b5132
RH		 779{
780 if (fixP->fx_tcbit && fixP->fx_size == 4)
781 return R_RELLONG_NEG;
782#ifdef NO_PCREL_RELOCS
783 know (fixP->fx_pcrel == 0);
784 return (fixP->fx_size == 1 ? R_RELBYTE
785 : fixP->fx_size == 2 ? R_DIR16
786 : R_DIR32);
787#else
31302357
AS		 788 return (fixP->fx_pcrel
789 ? (fixP->fx_size == 1 ? R_PCRBYTE
790 : fixP->fx_size == 2 ? R_PCRWORD
791 : R_PCRLONG)
792 : (fixP->fx_size == 1 ? R_RELBYTE
793 : fixP->fx_size == 2 ? R_RELWORD
794 : R_RELLONG));
252b5132
RH		 795#endif
796}
797
798#endif
799
800#ifdef OBJ_ELF
801
c801568a
AM		 802/* Return zero if the reference to SYMBOL from within the same segment may
803 be relaxed. */
804
805/* On an ELF system, we can't relax an externally visible symbol,
806 because it may be overridden by a shared library. However, if
807 TARGET_OS is "elf", then we presume that we are assembling for an
808 embedded system, in which case we don't have to worry about shared
809 libraries, and we can relax any external sym. */
810
811#define relaxable_symbol(symbol) \
6358301e 812 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 813 || S_IS_WEAK (symbol)))
814
252b5132
RH		 815/* Compute the relocation code for a fixup of SIZE bytes, using pc
816 relative relocation if PCREL is non-zero. PIC says whether a special
817 pic relocation was requested. */
818
252b5132 819static bfd_reloc_code_real_type
31302357 820get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 821{
822 switch (pic)
823 {
824 case pic_got_pcrel:
825 switch (size)
826 {
827 case 1:
828 return BFD_RELOC_8_GOT_PCREL;
829 case 2:
830 return BFD_RELOC_16_GOT_PCREL;
831 case 4:
832 return BFD_RELOC_32_GOT_PCREL;
833 }
834 break;
835
836 case pic_got_off:
837 switch (size)
838 {
839 case 1:
840 return BFD_RELOC_8_GOTOFF;
841 case 2:
842 return BFD_RELOC_16_GOTOFF;
843 case 4:
844 return BFD_RELOC_32_GOTOFF;
845 }
846 break;
847
848 case pic_plt_pcrel:
849 switch (size)
850 {
851 case 1:
852 return BFD_RELOC_8_PLT_PCREL;
853 case 2:
854 return BFD_RELOC_16_PLT_PCREL;
855 case 4:
856 return BFD_RELOC_32_PLT_PCREL;
857 }
858 break;
859
860 case pic_plt_off:
861 switch (size)
862 {
863 case 1:
864 return BFD_RELOC_8_PLTOFF;
865 case 2:
866 return BFD_RELOC_16_PLTOFF;
867 case 4:
868 return BFD_RELOC_32_PLTOFF;
869 }
870 break;
871
872 case pic_none:
873 if (pcrel)
874 {
875 switch (size)
876 {
877 case 1:
878 return BFD_RELOC_8_PCREL;
879 case 2:
880 return BFD_RELOC_16_PCREL;
881 case 4:
882 return BFD_RELOC_32_PCREL;
883 }
884 }
885 else
886 {
887 switch (size)
888 {
889 case 1:
890 return BFD_RELOC_8;
891 case 2:
892 return BFD_RELOC_16;
893 case 4:
894 return BFD_RELOC_32;
895 }
896 }
897 }
898
899 if (pcrel)
900 {
901 if (pic == pic_none)
902 as_bad (_("Can not do %d byte pc-relative relocation"), size);
903 else
904 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
905 }
906 else
907 {
908 if (pic == pic_none)
909 as_bad (_("Can not do %d byte relocation"), size);
910 else
911 as_bad (_("Can not do %d byte pic relocation"), size);
912 }
913
914 return BFD_RELOC_NONE;
915}
916
917/* Here we decide which fixups can be adjusted to make them relative
918 to the beginning of the section instead of the symbol. Basically
919 we need to make sure that the dynamic relocations are done
920 correctly, so in some cases we force the original symbol to be
921 used. */
922int
31302357 923tc_m68k_fix_adjustable (fixS *fixP)
252b5132 924{
36759679 925 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 926 switch (fixP->fx_r_type)
927 {
928 case BFD_RELOC_8_GOT_PCREL:
929 case BFD_RELOC_16_GOT_PCREL:
930 case BFD_RELOC_32_GOT_PCREL:
931 case BFD_RELOC_8_GOTOFF:
932 case BFD_RELOC_16_GOTOFF:
933 case BFD_RELOC_32_GOTOFF:
934 case BFD_RELOC_8_PLT_PCREL:
935 case BFD_RELOC_16_PLT_PCREL:
936 case BFD_RELOC_32_PLT_PCREL:
937 case BFD_RELOC_8_PLTOFF:
938 case BFD_RELOC_16_PLTOFF:
939 case BFD_RELOC_32_PLTOFF:
940 return 0;
941
942 case BFD_RELOC_VTABLE_INHERIT:
943 case BFD_RELOC_VTABLE_ENTRY:
944 return 0;
945
946 default:
947 return 1;
948 }
949}
950
951#else /* !OBJ_ELF */
952
953#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
954
c801568a
AM		 955#define relaxable_symbol(symbol) 1
956
252b5132
RH		 957#endif /* OBJ_ELF */
958
959#ifdef BFD_ASSEMBLER
960
961arelent *
31302357 962tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 963{
964 arelent *reloc;
965 bfd_reloc_code_real_type code;
966
8ec6253e
NC		 967 /* If the tcbit is set, then this was a fixup of a negative value
968 that was never resolved. We do not have a reloc to handle this,
969 so just return. We assume that other code will have detected this
970 situation and produced a helpful error message, so we just tell the
971 user that the reloc cannot be produced. */
252b5132 972 if (fixp->fx_tcbit)
8ec6253e
NC		 973 {
974 if (fixp->fx_addsy)
b091f402
AM		 975 as_bad_where (fixp->fx_file, fixp->fx_line,
976 _("Unable to produce reloc against symbol '%s'"),
977 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 978 return NULL;
979 }
252b5132
RH		 980
981 if (fixp->fx_r_type != BFD_RELOC_NONE)
982 {
983 code = fixp->fx_r_type;
984
985 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
986 that fixup_segment converted a non-PC relative reloc into a
987 PC relative reloc. In such a case, we need to convert the
988 reloc code. */
989 if (fixp->fx_pcrel)
990 {
991 switch (code)
992 {
993 case BFD_RELOC_8:
994 code = BFD_RELOC_8_PCREL;
995 break;
996 case BFD_RELOC_16:
997 code = BFD_RELOC_16_PCREL;
998 break;
999 case BFD_RELOC_32:
1000 code = BFD_RELOC_32_PCREL;
1001 break;
1002 case BFD_RELOC_8_PCREL:
1003 case BFD_RELOC_16_PCREL:
1004 case BFD_RELOC_32_PCREL:
1005 case BFD_RELOC_8_GOT_PCREL:
1006 case BFD_RELOC_16_GOT_PCREL:
1007 case BFD_RELOC_32_GOT_PCREL:
1008 case BFD_RELOC_8_GOTOFF:
1009 case BFD_RELOC_16_GOTOFF:
1010 case BFD_RELOC_32_GOTOFF:
1011 case BFD_RELOC_8_PLT_PCREL:
1012 case BFD_RELOC_16_PLT_PCREL:
1013 case BFD_RELOC_32_PLT_PCREL:
1014 case BFD_RELOC_8_PLTOFF:
1015 case BFD_RELOC_16_PLTOFF:
1016 case BFD_RELOC_32_PLTOFF:
1017 break;
1018 default:
1019 as_bad_where (fixp->fx_file, fixp->fx_line,
1020 _("Cannot make %s relocation PC relative"),
1021 bfd_get_reloc_code_name (code));
1022 }
1023 }
1024 }
1025 else
1026 {
1027#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1028 switch (F (fixp->fx_size, fixp->fx_pcrel))
1029 {
1030#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1031 MAP (1, 0, BFD_RELOC_8);
1032 MAP (2, 0, BFD_RELOC_16);
1033 MAP (4, 0, BFD_RELOC_32);
1034 MAP (1, 1, BFD_RELOC_8_PCREL);
1035 MAP (2, 1, BFD_RELOC_16_PCREL);
1036 MAP (4, 1, BFD_RELOC_32_PCREL);
1037 default:
1038 abort ();
1039 }
1040 }
1041#undef F
1042#undef MAP
1043
1044 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1045 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1046 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1047 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1048#ifndef OBJ_ELF
1049 if (fixp->fx_pcrel)
1050 reloc->addend = fixp->fx_addnumber;
1051 else
1052 reloc->addend = 0;
1053#else
1054 if (!fixp->fx_pcrel)
1055 reloc->addend = fixp->fx_addnumber;
1056 else
1057 reloc->addend = (section->vma
8390138c
AS		 1058 /* Explicit sign extension in case char is
1059 unsigned. */
1060 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1061 + fixp->fx_addnumber
1062 + md_pcrel_from (fixp));
1063#endif
1064
1065 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1066 assert (reloc->howto != 0);
1067
1068 return reloc;
1069}
1070
1071#endif /* BFD_ASSEMBLER */
1072
252b5132
RH		 1073/* Handle of the OPCODE hash table. NULL means any use before
1074 m68k_ip_begin() will crash. */
1075static struct hash_control *op_hash;
1076\f
1077/* Assemble an m68k instruction. */
1078
1079static void
31302357 1080m68k_ip (char *instring)
252b5132
RH		 1081{
1082 register char *p;
1083 register struct m68k_op *opP;
1084 register const struct m68k_incant *opcode;
1085 register const char *s;
1086 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1087 char *pdot, *pdotmove;
1088 enum m68k_size siz1, siz2;
1089 char c;
1090 int losing;
1091 int opsfound;
03b13e59 1092 struct m68k_op operands_backup[6];
252b5132
RH		 1093 LITTLENUM_TYPE words[6];
1094 LITTLENUM_TYPE *wordp;
1095 unsigned long ok_arch = 0;
1096
1097 if (*instring == ' ')
36759679 1098 instring++; /* Skip leading whitespace. */
252b5132
RH		 1099
1100 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1101 or exactly 1 space. */
252b5132
RH		 1102 pdot = 0;
1103 for (p = instring; *p != '\0'; p++)
1104 {
1105 if (*p == ' ')
1106 break;
1107 if (*p == '.')
1108 pdot = p;
1109 }
1110
1111 if (p == instring)
1112 {
1113 the_ins.error = _("No operator");
1114 return;
1115 }
1116
1117 /* p now points to the end of the opcode name, probably whitespace.
1118 Make sure the name is null terminated by clobbering the
1119 whitespace, look it up in the hash table, then fix it back.
1120 Remove a dot, first, since the opcode tables have none. */
1121 if (pdot != NULL)
1122 {
1123 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1124 *pdotmove = pdotmove[1];
1125 p--;
1126 }
1127
1128 c = *p;
1129 *p = '\0';
1130 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1131 *p = c;
1132
1133 if (pdot != NULL)
1134 {
1135 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1136 *pdotmove = pdotmove[-1];
1137 *pdot = '.';
1138 ++p;
1139 }
1140
1141 if (opcode == NULL)
1142 {
1143 the_ins.error = _("Unknown operator");
1144 return;
1145 }
1146
36759679 1147 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1148 while (*p == ' ')
1149 ++p;
1150
1151 if (opcode->m_operands == 0)
1152 {
1153 char *old = input_line_pointer;
1154 *old = '\n';
1155 input_line_pointer = p;
36759679 1156 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1157 mote_pseudo_table[opcode->m_opnum].poc_handler
1158 (mote_pseudo_table[opcode->m_opnum].poc_val);
1159 input_line_pointer = old;
1160 *old = 0;
1161
1162 return;
1163 }
1164
1165 if (flag_mri && opcode->m_opnum == 0)
1166 {
1167 /* In MRI mode, random garbage is allowed after an instruction
1168 which accepts no operands. */
1169 the_ins.args = opcode->m_operands;
1170 the_ins.numargs = opcode->m_opnum;
1171 the_ins.numo = opcode->m_codenum;
1172 the_ins.opcode[0] = getone (opcode);
1173 the_ins.opcode[1] = gettwo (opcode);
1174 return;
1175 }
1176
1177 for (opP = &the_ins.operands[0]; *p; opP++)
1178 {
1179 p = crack_operand (p, opP);
1180
1181 if (opP->error)
1182 {
1183 the_ins.error = opP->error;
1184 return;
1185 }
1186 }
1187
1188 opsfound = opP - &the_ins.operands[0];
1189
1190 /* This ugly hack is to support the floating pt opcodes in their
1191 standard form. Essentially, we fake a first enty of type COP#1 */
1192 if (opcode->m_operands[0] == 'I')
1193 {
1194 int n;
1195
1196 for (n = opsfound; n > 0; --n)
1197 the_ins.operands[n] = the_ins.operands[n - 1];
1198
31302357 1199 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1200 the_ins.operands[0].mode = CONTROL;
1201 the_ins.operands[0].reg = m68k_float_copnum;
1202 opsfound++;
1203 }
1204
36759679 1205 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1206 for (losing = 0;;)
1207 {
1208 /* If we didn't get the right number of ops, or we have no
92774660 1209 common model with this pattern then reject this pattern. */
252b5132
RH		 1210
1211 ok_arch |= opcode->m_arch;
1212 if (opsfound != opcode->m_opnum
1213 || ((opcode->m_arch & current_architecture) == 0))
1214 ++losing;
1215 else
1216 {
03b13e59
NC		 1217 int i;
1218
1219 /* Make a copy of the operands of this insn so that
1220 we can modify them safely, should we want to. */
1221 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1222 for (i = 0; i < opsfound; i++)
1223 operands_backup[i] = the_ins.operands[i];
1224
1225 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1226 *s && !losing;
1227 s += 2, opP++)
1228 {
1229 /* Warning: this switch is huge! */
1230 /* I've tried to organize the cases into this order:
1231 non-alpha first, then alpha by letter. Lower-case
1232 goes directly before uppercase counterpart. */
1233 /* Code with multiple case ...: gets sorted by the lowest
1234 case ... it belongs to. I hope this makes sense. */
1235 switch (*s)
1236 {
1237 case '!':
1238 switch (opP->mode)
1239 {
1240 case IMMED:
1241 case DREG:
1242 case AREG:
1243 case FPREG:
1244 case CONTROL:
1245 case AINC:
1246 case ADEC:
1247 case REGLST:
1248 losing++;
1249 break;
1250 default:
1251 break;
1252 }
1253 break;
1254
1255 case '<':
1256 switch (opP->mode)
1257 {
1258 case DREG:
1259 case AREG:
1260 case FPREG:
1261 case CONTROL:
1262 case IMMED:
1263 case ADEC:
1264 case REGLST:
1265 losing++;
1266 break;
1267 default:
1268 break;
1269 }
1270 break;
1271
1272 case '>':
1273 switch (opP->mode)
1274 {
1275 case DREG:
1276 case AREG:
1277 case FPREG:
1278 case CONTROL:
1279 case IMMED:
1280 case AINC:
1281 case REGLST:
1282 losing++;
1283 break;
1284 case ABSL:
1285 break;
1286 default:
1287 if (opP->reg == PC
1288 || opP->reg == ZPC)
1289 losing++;
1290 break;
1291 }
1292 break;
1293
1294 case 'm':
1295 switch (opP->mode)
1296 {
1297 case DREG:
1298 case AREG:
1299 case AINDR:
1300 case AINC:
1301 case ADEC:
1302 break;
1303 default:
1304 losing++;
1305 }
8a104df9 1306 break;
252b5132
RH		 1307
1308 case 'n':
1309 switch (opP->mode)
1310 {
1311 case DISP:
1312 break;
1313 default:
1314 losing++;
1315 }
8a104df9 1316 break;
252b5132
RH		 1317
1318 case 'o':
1319 switch (opP->mode)
1320 {
1321 case BASE:
1322 case ABSL:
1323 case IMMED:
1324 break;
1325 default:
1326 losing++;
1327 }
8a104df9 1328 break;
252b5132
RH		 1329
1330 case 'p':
1331 switch (opP->mode)
1332 {
1333 case DREG:
1334 case AREG:
1335 case AINDR:
1336 case AINC:
1337 case ADEC:
1338 break;
1339 case DISP:
1340 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1341 losing++;
252b5132
RH		 1342 break;
1343 default:
1344 losing++;
1345 }
8a104df9 1346 break;
252b5132
RH		 1347
1348 case 'q':
1349 switch (opP->mode)
1350 {
1351 case DREG:
1352 case AINDR:
1353 case AINC:
1354 case ADEC:
1355 break;
1356 case DISP:
1357 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1358 losing++;
252b5132
RH		 1359 break;
1360 default:
1361 losing++;
1362 break;
1363 }
8a104df9 1364 break;
252b5132
RH		 1365
1366 case 'v':
1367 switch (opP->mode)
1368 {
1369 case DREG:
1370 case AINDR:
1371 case AINC:
1372 case ADEC:
1373 case ABSL:
1374 break;
1375 case DISP:
1376 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1377 losing++;
252b5132
RH		 1378 break;
1379 default:
1380 losing++;
1381 break;
1382 }
1383 break;
1384
1385 case '#':
1386 if (opP->mode != IMMED)
1387 losing++;
1388 else if (s[1] == 'b'
1389 && ! isvar (&opP->disp)
1390 && (opP->disp.exp.X_op != O_constant
1391 || ! isbyte (opP->disp.exp.X_add_number)))
1392 losing++;
1393 else if (s[1] == 'B'
1394 && ! isvar (&opP->disp)
1395 && (opP->disp.exp.X_op != O_constant
1396 || ! issbyte (opP->disp.exp.X_add_number)))
1397 losing++;
1398 else if (s[1] == 'w'
1399 && ! isvar (&opP->disp)
1400 && (opP->disp.exp.X_op != O_constant
1401 || ! isword (opP->disp.exp.X_add_number)))
1402 losing++;
1403 else if (s[1] == 'W'
1404 && ! isvar (&opP->disp)
1405 && (opP->disp.exp.X_op != O_constant
1406 || ! issword (opP->disp.exp.X_add_number)))
1407 losing++;
1408 break;
1409
1410 case '^':
1411 case 'T':
1412 if (opP->mode != IMMED)
1413 losing++;
1414 break;
1415
1416 case '$':
1417 if (opP->mode == AREG
1418 || opP->mode == CONTROL
1419 || opP->mode == FPREG
1420 || opP->mode == IMMED
1421 || opP->mode == REGLST
1422 || (opP->mode != ABSL
1423 && (opP->reg == PC
1424 || opP->reg == ZPC)))
1425 losing++;
1426 break;
1427
1428 case '%':
1429 if (opP->mode == CONTROL
1430 || opP->mode == FPREG
1431 || opP->mode == REGLST
1432 || opP->mode == IMMED
1433 || (opP->mode != ABSL
1434 && (opP->reg == PC
1435 || opP->reg == ZPC)))
1436 losing++;
1437 break;
1438
1439 case '&':
1440 switch (opP->mode)
1441 {
1442 case DREG:
1443 case AREG:
1444 case FPREG:
1445 case CONTROL:
1446 case IMMED:
1447 case AINC:
1448 case ADEC:
1449 case REGLST:
1450 losing++;
1451 break;
1452 case ABSL:
1453 break;
1454 default:
1455 if (opP->reg == PC
1456 || opP->reg == ZPC)
1457 losing++;
1458 break;
1459 }
1460 break;
1461
1462 case '*':
1463 if (opP->mode == CONTROL
1464 || opP->mode == FPREG
1465 || opP->mode == REGLST)
1466 losing++;
1467 break;
1468
1469 case '+':
1470 if (opP->mode != AINC)
1471 losing++;
1472 break;
1473
1474 case '-':
1475 if (opP->mode != ADEC)
1476 losing++;
1477 break;
1478
1479 case '/':
1480 switch (opP->mode)
1481 {
1482 case AREG:
1483 case CONTROL:
1484 case FPREG:
1485 case AINC:
1486 case ADEC:
1487 case IMMED:
1488 case REGLST:
1489 losing++;
1490 break;
1491 default:
1492 break;
1493 }
1494 break;
1495
1496 case ';':
1497 switch (opP->mode)
1498 {
1499 case AREG:
1500 case CONTROL:
1501 case FPREG:
1502 case REGLST:
1503 losing++;
1504 break;
1505 default:
1506 break;
1507 }
1508 break;
1509
1510 case '?':
1511 switch (opP->mode)
1512 {
1513 case AREG:
1514 case CONTROL:
1515 case FPREG:
1516 case AINC:
1517 case ADEC:
1518 case IMMED:
1519 case REGLST:
1520 losing++;
1521 break;
1522 case ABSL:
1523 break;
1524 default:
1525 if (opP->reg == PC || opP->reg == ZPC)
1526 losing++;
1527 break;
1528 }
1529 break;
1530
1531 case '@':
1532 switch (opP->mode)
1533 {
1534 case AREG:
1535 case CONTROL:
1536 case FPREG:
1537 case IMMED:
1538 case REGLST:
1539 losing++;
1540 break;
1541 default:
1542 break;
1543 }
1544 break;
1545
1546 case '~': /* For now! (JF FOO is this right?) */
1547 switch (opP->mode)
1548 {
1549 case DREG:
1550 case AREG:
1551 case CONTROL:
1552 case FPREG:
1553 case IMMED:
1554 case REGLST:
1555 losing++;
1556 break;
1557 case ABSL:
1558 break;
1559 default:
1560 if (opP->reg == PC
1561 || opP->reg == ZPC)
1562 losing++;
1563 break;
1564 }
1565 break;
1566
1567 case '3':
1568 if (opP->mode != CONTROL
1569 || (opP->reg != TT0 && opP->reg != TT1))
1570 losing++;
1571 break;
1572
1573 case 'A':
1574 if (opP->mode != AREG)
1575 losing++;
1576 break;
1577
1578 case 'a':
1579 if (opP->mode != AINDR)
1580 ++losing;
1581 break;
1582
fd99574b
NC		 1583 case '4':
1584 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1585 && (opP->mode != DISP
1586 || opP->reg < ADDR0
1587 || opP->reg > ADDR7))
1588 ++losing;
1589 break;
1590
252b5132
RH		 1591 case 'B': /* FOO */
1592 if (opP->mode != ABSL
1593 || (flag_long_jumps
1594 && strncmp (instring, "jbsr", 4) == 0))
1595 losing++;
1596 break;
1597
3e602632
NC		 1598 case 'b':
1599 switch (opP->mode)
1600 {
1601 case IMMED:
1602 case ABSL:
1603 case AREG:
1604 case FPREG:
1605 case CONTROL:
1606 case POST:
1607 case PRE:
1608 case REGLST:
1609 losing++;
1610 break;
1611 default:
1612 break;
1613 }
1614 break;
1615
252b5132
RH		 1616 case 'C':
1617 if (opP->mode != CONTROL || opP->reg != CCR)
1618 losing++;
1619 break;
1620
1621 case 'd':
1622 if (opP->mode != DISP
1623 || opP->reg < ADDR0
1624 || opP->reg > ADDR7)
1625 losing++;
1626 break;
1627
1628 case 'D':
1629 if (opP->mode != DREG)
1630 losing++;
1631 break;
1632
6da466c7
ILT		 1633 case 'E':
1634 if (opP->reg != ACC)
1635 losing++;
1636 break;
1637
fd99574b
NC		 1638 case 'e':
1639 if (opP->reg != ACC && opP->reg != ACC1
1640 && opP->reg != ACC2 && opP->reg != ACC3)
1641 losing++;
1642 break;
1643
252b5132
RH		 1644 case 'F':
1645 if (opP->mode != FPREG)
1646 losing++;
1647 break;
1648
6da466c7
ILT		 1649 case 'G':
1650 if (opP->reg != MACSR)
1651 losing++;
1652 break;
1653
fd99574b
NC		 1654 case 'g':
1655 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1656 losing++;
1657 break;
1658
6da466c7
ILT		 1659 case 'H':
1660 if (opP->reg != MASK)
1661 losing++;
1662 break;
1663
252b5132
RH		 1664 case 'I':
1665 if (opP->mode != CONTROL
1666 || opP->reg < COP0
1667 || opP->reg > COP7)
1668 losing++;
1669 break;
1670
fd99574b
NC		 1671 case 'i':
1672 if (opP->mode != LSH && opP->mode != RSH)
1673 losing++;
1674 break;
1675
252b5132
RH		 1676 case 'J':
1677 if (opP->mode != CONTROL
1678 || opP->reg < USP
1679 || opP->reg > last_movec_reg)
1680 losing++;
1681 else
1682 {
1683 const enum m68k_register *rp;
1684 for (rp = control_regs; *rp; rp++)
1685 if (*rp == opP->reg)
1686 break;
1687 if (*rp == 0)
1688 losing++;
1689 }
1690 break;
1691
1692 case 'k':
1693 if (opP->mode != IMMED)
1694 losing++;
1695 break;
1696
1697 case 'l':
1698 case 'L':
1699 if (opP->mode == DREG
1700 || opP->mode == AREG
1701 || opP->mode == FPREG)
1702 {
1703 if (s[1] == '8')
1704 losing++;
1705 else
1706 {
1707 switch (opP->mode)
1708 {
1709 case DREG:
1710 opP->mask = 1 << (opP->reg - DATA0);
1711 break;
1712 case AREG:
1713 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1714 break;
1715 case FPREG:
1716 opP->mask = 1 << (opP->reg - FP0 + 16);
1717 break;
1718 default:
1719 abort ();
1720 }
1721 opP->mode = REGLST;
1722 }
1723 }
1724 else if (opP->mode == CONTROL)
1725 {
1726 if (s[1] != '8')
1727 losing++;
1728 else
1729 {
1730 switch (opP->reg)
1731 {
1732 case FPI:
1733 opP->mask = 1 << 24;
1734 break;
1735 case FPS:
1736 opP->mask = 1 << 25;
1737 break;
1738 case FPC:
1739 opP->mask = 1 << 26;
1740 break;
1741 default:
1742 losing++;
1743 break;
1744 }
1745 opP->mode = REGLST;
1746 }
1747 }
1748 else if (opP->mode != REGLST)
1749 losing++;
1750 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1751 losing++;
1752 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1753 losing++;
1754 break;
1755
1756 case 'M':
1757 if (opP->mode != IMMED)
1758 losing++;
1759 else if (opP->disp.exp.X_op != O_constant
1760 || ! issbyte (opP->disp.exp.X_add_number))
1761 losing++;
1762 else if (! m68k_quick
1763 && instring[3] != 'q'
1764 && instring[4] != 'q')
1765 losing++;
1766 break;
1767
1768 case 'O':
1769 if (opP->mode != DREG
1770 && opP->mode != IMMED
1771 && opP->mode != ABSL)
1772 losing++;
1773 break;
1774
1775 case 'Q':
1776 if (opP->mode != IMMED)
1777 losing++;
1778 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1779 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1780 losing++;
1781 else if (! m68k_quick
1782 && (strncmp (instring, "add", 3) == 0
1783 || strncmp (instring, "sub", 3) == 0)
1784 && instring[3] != 'q')
1785 losing++;
1786 break;
1787
1788 case 'R':
1789 if (opP->mode != DREG && opP->mode != AREG)
1790 losing++;
1791 break;
1792
1793 case 'r':
1794 if (opP->mode != AINDR
1795 && (opP->mode != BASE
1796 || (opP->reg != 0
1797 && opP->reg != ZADDR0)
1798 || opP->disp.exp.X_op != O_absent
1799 || ((opP->index.reg < DATA0
1800 || opP->index.reg > DATA7)
1801 && (opP->index.reg < ADDR0
1802 || opP->index.reg > ADDR7))
1803 || opP->index.size != SIZE_UNSPEC
1804 || opP->index.scale != 1))
1805 losing++;
1806 break;
1807
1808 case 's':
1809 if (opP->mode != CONTROL
1810 || ! (opP->reg == FPI
1811 || opP->reg == FPS
1812 || opP->reg == FPC))
1813 losing++;
1814 break;
1815
1816 case 'S':
1817 if (opP->mode != CONTROL || opP->reg != SR)
1818 losing++;
1819 break;
1820
1821 case 't':
1822 if (opP->mode != IMMED)
1823 losing++;
1824 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1825 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1826 losing++;
1827 break;
1828
1829 case 'U':
1830 if (opP->mode != CONTROL || opP->reg != USP)
1831 losing++;
1832 break;
1833
3e602632
NC		 1834 case 'x':
1835 if (opP->mode != IMMED)
1836 losing++;
1837 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1838 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1839 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1840 losing++;
1841 break;
1842
252b5132
RH		 1843 /* JF these are out of order. We could put them
1844 in order if we were willing to put up with
1845 bunches of #ifdef m68851s in the code.
1846
1847 Don't forget that you need these operands
1848 to use 68030 MMU instructions. */
1849#ifndef NO_68851
36759679 1850 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1851 case '|':
1852 if (opP->mode == CONTROL
1853 || opP->mode == FPREG
1854 || opP->mode == DREG
1855 || opP->mode == AREG
1856 || opP->mode == REGLST)
1857 losing++;
1858 /* We should accept immediate operands, but they
1859 supposedly have to be quad word, and we don't
1860 handle that. I would like to see what a Motorola
1861 assembler does before doing something here. */
1862 if (opP->mode == IMMED)
1863 losing++;
1864 break;
1865
1866 case 'f':
1867 if (opP->mode != CONTROL
1868 || (opP->reg != SFC && opP->reg != DFC))
1869 losing++;
1870 break;
1871
1872 case '0':
1873 if (opP->mode != CONTROL || opP->reg != TC)
1874 losing++;
1875 break;
1876
1877 case '1':
1878 if (opP->mode != CONTROL || opP->reg != AC)
1879 losing++;
1880 break;
1881
1882 case '2':
1883 if (opP->mode != CONTROL
1884 || (opP->reg != CAL
1885 && opP->reg != VAL
1886 && opP->reg != SCC))
1887 losing++;
1888 break;
1889
1890 case 'V':
1891 if (opP->mode != CONTROL
1892 || opP->reg != VAL)
1893 losing++;
1894 break;
1895
1896 case 'W':
1897 if (opP->mode != CONTROL
1898 || (opP->reg != DRP
1899 && opP->reg != SRP
1900 && opP->reg != CRP))
1901 losing++;
1902 break;
1903
3e602632
NC		 1904 case 'w':
1905 switch (opP->mode)
1906 {
1907 case IMMED:
1908 case ABSL:
1909 case AREG:
1910 case DREG:
1911 case FPREG:
1912 case CONTROL:
1913 case POST:
1914 case PRE:
1915 case REGLST:
1916 losing++;
1917 break;
1918 default:
1919 break;
1920 }
1921 break;
1922
252b5132
RH		 1923 case 'X':
1924 if (opP->mode != CONTROL
1925 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1926 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1927 losing++;
1928 break;
1929
1930 case 'Y':
1931 if (opP->mode != CONTROL || opP->reg != PSR)
1932 losing++;
1933 break;
1934
1935 case 'Z':
1936 if (opP->mode != CONTROL || opP->reg != PCSR)
1937 losing++;
1938 break;
1939#endif
1940 case 'c':
1941 if (opP->mode != CONTROL
1942 || (opP->reg != NC
1943 && opP->reg != IC
1944 && opP->reg != DC
1945 && opP->reg != BC))
36759679 1946 losing++;
252b5132
RH		 1947 break;
1948
1949 case '_':
1950 if (opP->mode != ABSL)
1951 ++losing;
1952 break;
1953
6da466c7
ILT		 1954 case 'u':
1955 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1956 losing++;
1957 /* FIXME: kludge instead of fixing parser:
1958 upper/lower registers are *not* CONTROL
92774660 1959 registers, but ordinary ones. */
6da466c7
ILT		 1960 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1961 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1962 opP->mode = DREG;
1963 else
1964 opP->mode = AREG;
1965 break;
1966
3e602632
NC		 1967 case 'y':
1968 if (!(opP->mode == AINDR
31302357
AS		 1969 || (opP->mode == DISP
1970 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 1971 losing++;
1972 break;
1973
1974 case 'z':
1975 if (!(opP->mode == AINDR || opP->mode == DISP))
1976 losing++;
1977 break;
1978
252b5132
RH		 1979 default:
1980 abort ();
36759679 1981 }
252b5132
RH		 1982
1983 if (losing)
1984 break;
36759679 1985 }
03b13e59
NC		 1986
1987 /* Since we have found the correct instruction, copy
1988 in the modifications that we may have made. */
1989 if (!losing)
1990 for (i = 0; i < opsfound; i++)
1991 the_ins.operands[i] = operands_backup[i];
36759679 1992 }
252b5132
RH		 1993
1994 if (!losing)
36759679 1995 break;
252b5132
RH		 1996
1997 opcode = opcode->m_next;
1998
1999 if (!opcode)
2000 {
2001 if (ok_arch
2002 && !(ok_arch & current_architecture))
2003 {
2004 char buf[200], *cp;
2005
6b6e92f4 2006 strncpy (buf,
31302357
AS		 2007 _("invalid instruction for this architecture; needs "),
2008 sizeof (buf));
252b5132
RH		 2009 cp = buf + strlen (buf);
2010 switch (ok_arch)
2011 {
6b6e92f4 2012 case mcfisa_a:
31302357
AS		 2013 strncpy (cp, _("ColdFire ISA_A"),
2014 sizeof (buf) - (cp - buf));
6b6e92f4 2015 cp += strlen (cp);
31302357
AS		 2016 strncpy (cp, find_cf_chip (ok_arch),
2017 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2018 cp += strlen (cp);
2019 break;
2020 case mcfhwdiv:
31302357
AS		 2021 strncpy (cp, _("ColdFire hardware divide"),
2022 sizeof (buf) - (cp - buf));
6b6e92f4 2023 cp += strlen (cp);
31302357
AS		 2024 strncpy (cp, find_cf_chip (ok_arch),
2025 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2026 cp += strlen (cp);
2027 break;
2028 case mcfisa_aa:
31302357
AS		 2029 strncpy (cp, _("ColdFire ISA_A+"),
2030 sizeof (buf) - (cp - buf));
6b6e92f4 2031 cp += strlen (cp);
31302357
AS		 2032 strncpy (cp, find_cf_chip (ok_arch),
2033 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2034 cp += strlen (cp);
2035 break;
2036 case mcfisa_b:
31302357
AS		 2037 strncpy (cp, _("ColdFire ISA_B"),
2038 sizeof (buf) - (cp - buf));
6b6e92f4 2039 cp += strlen (cp);
31302357
AS		 2040 strncpy (cp, find_cf_chip (ok_arch),
2041 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 2042 cp += strlen (cp);
2043 break;
3e602632 2044 case cfloat:
31302357 2045 strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
6b6e92f4 2046 cp += strlen (cp);
31302357
AS		 2047 strncpy (cp, find_cf_chip (ok_arch),
2048 sizeof (buf) - (cp - buf));
6b6e92f4 2049 cp += strlen (cp);
3e602632 2050 break;
252b5132
RH		 2051 case mfloat:
2052 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2053 break;
2054 case mmmu:
2055 strcpy (cp, _("mmu (68030 or 68851)"));
2056 break;
2057 case m68020up:
2058 strcpy (cp, _("68020 or higher"));
2059 break;
2060 case m68000up:
2061 strcpy (cp, _("68000 or higher"));
2062 break;
2063 case m68010up:
2064 strcpy (cp, _("68010 or higher"));
2065 break;
2066 default:
2067 {
2068 int got_one = 0, idx;
6b6e92f4
NC		 2069
2070 for (idx = 0; idx < n_archs; idx++)
252b5132
RH		 2071 {
2072 if ((archs[idx].arch & ok_arch)
2073 && ! archs[idx].alias)
2074 {
2075 if (got_one)
2076 {
2077 strcpy (cp, " or ");
2078 cp += strlen (cp);
2079 }
2080 got_one = 1;
2081 strcpy (cp, archs[idx].name);
2082 cp += strlen (cp);
2083 }
2084 }
2085 }
2086 }
2087 cp = xmalloc (strlen (buf) + 1);
2088 strcpy (cp, buf);
2089 the_ins.error = cp;
2090 }
2091 else
2092 the_ins.error = _("operands mismatch");
2093 return;
36759679 2094 }
252b5132
RH		 2095
2096 losing = 0;
2097 }
2098
36759679 2099 /* Now assemble it. */
252b5132
RH		 2100 the_ins.args = opcode->m_operands;
2101 the_ins.numargs = opcode->m_opnum;
2102 the_ins.numo = opcode->m_codenum;
2103 the_ins.opcode[0] = getone (opcode);
2104 the_ins.opcode[1] = gettwo (opcode);
2105
2106 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2107 {
2108 /* This switch is a doozy.
31302357 2109 Watch the first step; its a big one! */
252b5132
RH		 2110 switch (s[0])
2111 {
2112
2113 case '*':
2114 case '~':
2115 case '%':
2116 case ';':
2117 case '@':
2118 case '!':
2119 case '&':
2120 case '$':
2121 case '?':
2122 case '/':
2123 case '<':
2124 case '>':
3e602632 2125 case 'b':
252b5132
RH		 2126 case 'm':
2127 case 'n':
2128 case 'o':
2129 case 'p':
2130 case 'q':
2131 case 'v':
3e602632
NC		 2132 case 'w':
2133 case 'y':
2134 case 'z':
fd99574b 2135 case '4':
252b5132
RH		 2136#ifndef NO_68851
2137 case '|':
2138#endif
2139 switch (opP->mode)
2140 {
2141 case IMMED:
2142 tmpreg = 0x3c; /* 7.4 */
2143 if (strchr ("bwl", s[1]))
3e602632 2144 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2145 else
2146 nextword = get_num (&opP->disp, 0);
2147 if (isvar (&opP->disp))
2148 add_fix (s[1], &opP->disp, 0, 0);
2149 switch (s[1])
2150 {
2151 case 'b':
2152 if (!isbyte (nextword))
2153 opP->error = _("operand out of range");
2154 addword (nextword);
2155 baseo = 0;
2156 break;
2157 case 'w':
2158 if (!isword (nextword))
2159 opP->error = _("operand out of range");
2160 addword (nextword);
2161 baseo = 0;
2162 break;
2163 case 'W':
2164 if (!issword (nextword))
2165 opP->error = _("operand out of range");
2166 addword (nextword);
2167 baseo = 0;
2168 break;
2169 case 'l':
2170 addword (nextword >> 16);
2171 addword (nextword);
2172 baseo = 0;
2173 break;
2174
2175 case 'f':
2176 baseo = 2;
2177 outro = 8;
2178 break;
2179 case 'F':
2180 baseo = 4;
2181 outro = 11;
2182 break;
2183 case 'x':
2184 baseo = 6;
2185 outro = 15;
2186 break;
2187 case 'p':
2188 baseo = 6;
2189 outro = -1;
2190 break;
2191 default:
2192 abort ();
2193 }
2194 if (!baseo)
2195 break;
2196
36759679 2197 /* We gotta put out some float. */
252b5132
RH		 2198 if (op (&opP->disp) != O_big)
2199 {
2200 valueT val;
2201 int gencnt;
2202
2203 /* Can other cases happen here? */
2204 if (op (&opP->disp) != O_constant)
2205 abort ();
2206
2207 val = (valueT) offs (&opP->disp);
2208 gencnt = 0;
2209 do
2210 {
2211 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2212 val >>= LITTLENUM_NUMBER_OF_BITS;
2213 ++gencnt;
2214 }
2215 while (val != 0);
2216 offs (&opP->disp) = gencnt;
2217 }
2218 if (offs (&opP->disp) > 0)
2219 {
2220 if (offs (&opP->disp) > baseo)
2221 {
2222 as_warn (_("Bignum too big for %c format; truncated"),
2223 s[1]);
2224 offs (&opP->disp) = baseo;
2225 }
2226 baseo -= offs (&opP->disp);
2227 while (baseo--)
2228 addword (0);
2229 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2230 offs (&opP->disp)--;
2231 --wordp)
2232 addword (*wordp);
2233 break;
2234 }
2235 gen_to_words (words, baseo, (long) outro);
2236 for (wordp = words; baseo--; wordp++)
2237 addword (*wordp);
2238 break;
2239 case DREG:
2240 tmpreg = opP->reg - DATA; /* 0.dreg */
2241 break;
2242 case AREG:
2243 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2244 break;
2245 case AINDR:
2246 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2247 break;
2248 case ADEC:
2249 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2250 break;
2251 case AINC:
2252 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2253 break;
2254 case DISP:
2255
3e602632 2256 nextword = get_num (&opP->disp, 90);
252b5132 2257
580b9172
NC		 2258 /* Convert mode 5 addressing with a zero offset into
2259 mode 2 addressing to reduce the instruction size by a
2260 word. */
2261 if (! isvar (&opP->disp)
2262 && (nextword == 0)
2263 && (opP->disp.size == SIZE_UNSPEC)
2264 && (opP->reg >= ADDR0)
2265 && (opP->reg <= ADDR7))
2266 {
2267 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2268 break;
2269 }
2270
252b5132
RH		 2271 if (opP->reg == PC
2272 && ! isvar (&opP->disp)
2273 && m68k_abspcadd)
2274 {
2275 opP->disp.exp.X_op = O_symbol;
2276#ifndef BFD_ASSEMBLER
2277 opP->disp.exp.X_add_symbol = &abs_symbol;
2278#else
2279 opP->disp.exp.X_add_symbol =
2280 section_symbol (absolute_section);
2281#endif
2282 }
2283
36759679 2284 /* Force into index mode. Hope this works. */
252b5132
RH		 2285
2286 /* We do the first bit for 32-bit displacements, and the
2287 second bit for 16 bit ones. It is possible that we
2288 should make the default be WORD instead of LONG, but
2289 I think that'd break GCC, so we put up with a little
2290 inefficiency for the sake of working output. */
2291
2292 if (!issword (nextword)
2293 || (isvar (&opP->disp)
2294 && ((opP->disp.size == SIZE_UNSPEC
2295 && flag_short_refs == 0
2296 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2297 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2298 || opP->disp.size == SIZE_LONG)))
2299 {
2300 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2301 || arch_coldfire_p (current_architecture))
252b5132
RH		 2302 opP->error =
2303 _("displacement too large for this architecture; needs 68020 or higher");
2304 if (opP->reg == PC)
2305 tmpreg = 0x3B; /* 7.3 */
2306 else
2307 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2308 if (isvar (&opP->disp))
2309 {
2310 if (opP->reg == PC)
2311 {
2312 if (opP->disp.size == SIZE_LONG
2313#ifdef OBJ_ELF
2314 /* If the displacement needs pic
2315 relocation it cannot be relaxed. */
2316 || opP->disp.pic_reloc != pic_none
2317#endif
2318 )
2319 {
2320 addword (0x0170);
2321 add_fix ('l', &opP->disp, 1, 2);
2322 }
2323 else
2324 {
2325 add_frag (adds (&opP->disp),
bd17c2c3 2326 SEXT (offs (&opP->disp)),
151337e8 2327 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2328 break;
2329 }
2330 }
2331 else
2332 {
2333 addword (0x0170);
2334 add_fix ('l', &opP->disp, 0, 0);
2335 }
2336 }
2337 else
2338 addword (0x0170);
2339 addword (nextword >> 16);
2340 }
2341 else
2342 {
2343 if (opP->reg == PC)
2344 tmpreg = 0x3A; /* 7.2 */
2345 else
2346 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2347
2348 if (isvar (&opP->disp))
2349 {
2350 if (opP->reg == PC)
2351 {
2352 add_fix ('w', &opP->disp, 1, 0);
2353 }
2354 else
2355 add_fix ('w', &opP->disp, 0, 0);
2356 }
2357 }
2358 addword (nextword);
2359 break;
2360
2361 case POST:
2362 case PRE:
2363 case BASE:
2364 nextword = 0;
3e602632 2365 baseo = get_num (&opP->disp, 90);
252b5132 2366 if (opP->mode == POST || opP->mode == PRE)
3e602632 2367 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2368 /* Figure out the `addressing mode'.
2369 Also turn on the BASE_DISABLE bit, if needed. */
2370 if (opP->reg == PC || opP->reg == ZPC)
2371 {
2372 tmpreg = 0x3b; /* 7.3 */
2373 if (opP->reg == ZPC)
2374 nextword |= 0x80;
2375 }
2376 else if (opP->reg == 0)
2377 {
2378 nextword |= 0x80;
2379 tmpreg = 0x30; /* 6.garbage */
2380 }
2381 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2382 {
2383 nextword |= 0x80;
2384 tmpreg = 0x30 + opP->reg - ZADDR0;
2385 }
2386 else
2387 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2388
2389 siz1 = opP->disp.size;
2390 if (opP->mode == POST || opP->mode == PRE)
2391 siz2 = opP->odisp.size;
2392 else
2393 siz2 = SIZE_UNSPEC;
2394
36759679 2395 /* Index register stuff. */
252b5132
RH		 2396 if (opP->index.reg != 0
2397 && opP->index.reg >= DATA
2398 && opP->index.reg <= ADDR7)
2399 {
2400 nextword |= (opP->index.reg - DATA) << 12;
2401
2402 if (opP->index.size == SIZE_LONG
2403 || (opP->index.size == SIZE_UNSPEC
2404 && m68k_index_width_default == SIZE_LONG))
2405 nextword |= 0x800;
2406
92774660 2407 if ((opP->index.scale != 1
252b5132 2408 && cpu_of_arch (current_architecture) < m68020)
92774660 2409 || (opP->index.scale == 8
3e602632 2410 && (arch_coldfire_p (current_architecture)
6b6e92f4 2411 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2412 {
2413 opP->error =
2414 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2415 }
2416
6da466c7
ILT		 2417 if (arch_coldfire_p (current_architecture)
2418 && opP->index.size == SIZE_WORD)
2419 opP->error = _("invalid index size for coldfire");
2420
252b5132
RH		 2421 switch (opP->index.scale)
2422 {
2423 case 1:
2424 break;
2425 case 2:
2426 nextword |= 0x200;
2427 break;
2428 case 4:
2429 nextword |= 0x400;
2430 break;
2431 case 8:
2432 nextword |= 0x600;
2433 break;
2434 default:
2435 abort ();
2436 }
2437 /* IF its simple,
2438 GET US OUT OF HERE! */
2439
2440 /* Must be INDEX, with an index register. Address
2441 register cannot be ZERO-PC, and either :b was
2442 forced, or we know it will fit. For a 68000 or
2443 68010, force this mode anyways, because the
2444 larger modes aren't supported. */
2445 if (opP->mode == BASE
2446 && ((opP->reg >= ADDR0
2447 && opP->reg <= ADDR7)
2448 || opP->reg == PC))
2449 {
2450 if (siz1 == SIZE_BYTE
2451 || cpu_of_arch (current_architecture) < m68020
6da466c7 2452 || arch_coldfire_p (current_architecture)
252b5132
RH		 2453 || (siz1 == SIZE_UNSPEC
2454 && ! isvar (&opP->disp)
2455 && issbyte (baseo)))
2456 {
2457 nextword += baseo & 0xff;
2458 addword (nextword);
2459 if (isvar (&opP->disp))
2460 {
2461 /* Do a byte relocation. If it doesn't
2462 fit (possible on m68000) let the
2463 fixup processing complain later. */
2464 if (opP->reg == PC)
2465 add_fix ('B', &opP->disp, 1, 1);
2466 else
2467 add_fix ('B', &opP->disp, 0, 0);
2468 }
2469 else if (siz1 != SIZE_BYTE)
2470 {
2471 if (siz1 != SIZE_UNSPEC)
2472 as_warn (_("Forcing byte displacement"));
2473 if (! issbyte (baseo))
2474 opP->error = _("byte displacement out of range");
2475 }
2476
2477 break;
2478 }
2479 else if (siz1 == SIZE_UNSPEC
2480 && opP->reg == PC
2481 && isvar (&opP->disp)
2482 && subs (&opP->disp) == NULL
2483#ifdef OBJ_ELF
2484 /* If the displacement needs pic
2485 relocation it cannot be relaxed. */
2486 && opP->disp.pic_reloc == pic_none
2487#endif
2488 )
2489 {
2490 /* The code in md_convert_frag_1 needs to be
2491 able to adjust nextword. Call frag_grow
2492 to ensure that we have enough space in
2493 the frag obstack to make all the bytes
2494 contiguous. */
2495 frag_grow (14);
8a104df9
KH		 2496 nextword += baseo & 0xff;
2497 addword (nextword);
bd17c2c3
AM		 2498 add_frag (adds (&opP->disp),
2499 SEXT (offs (&opP->disp)),
8a104df9 2500 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2501
2502 break;
8a104df9 2503 }
252b5132
RH		 2504 }
2505 }
2506 else
2507 {
36759679 2508 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2509 if (opP->index.reg >= ZDATA0
2510 && opP->index.reg <= ZDATA7)
2511 nextword |= (opP->index.reg - ZDATA0) << 12;
2512 else if (opP->index.reg >= ZADDR0
2513 || opP->index.reg <= ZADDR7)
2514 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2515 }
2516
2517 /* It isn't simple. */
2518
2519 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2520 || arch_coldfire_p (current_architecture))
252b5132
RH		 2521 opP->error =
2522 _("invalid operand mode for this architecture; needs 68020 or higher");
2523
2524 nextword |= 0x100;
2525 /* If the guy specified a width, we assume that it is
2526 wide enough. Maybe it isn't. If so, we lose. */
2527 switch (siz1)
2528 {
2529 case SIZE_UNSPEC:
2530 if (isvar (&opP->disp)
2531 ? m68k_rel32
2532 : ! issword (baseo))
2533 {
2534 siz1 = SIZE_LONG;
2535 nextword |= 0x30;
2536 }
2537 else if (! isvar (&opP->disp) && baseo == 0)
2538 nextword |= 0x10;
2539 else
2540 {
2541 nextword |= 0x20;
2542 siz1 = SIZE_WORD;
2543 }
2544 break;
2545 case SIZE_BYTE:
2546 as_warn (_(":b not permitted; defaulting to :w"));
2547 /* Fall through. */
2548 case SIZE_WORD:
2549 nextword |= 0x20;
2550 break;
2551 case SIZE_LONG:
2552 nextword |= 0x30;
2553 break;
2554 }
2555
67c1ffbe 2556 /* Figure out inner displacement stuff. */
252b5132
RH		 2557 if (opP->mode == POST || opP->mode == PRE)
2558 {
2559 if (cpu_of_arch (current_architecture) & cpu32)
2560 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2561 switch (siz2)
2562 {
2563 case SIZE_UNSPEC:
2564 if (isvar (&opP->odisp)
2565 ? m68k_rel32
2566 : ! issword (outro))
2567 {
2568 siz2 = SIZE_LONG;
2569 nextword |= 0x3;
2570 }
2571 else if (! isvar (&opP->odisp) && outro == 0)
2572 nextword |= 0x1;
2573 else
2574 {
2575 nextword |= 0x2;
2576 siz2 = SIZE_WORD;
2577 }
2578 break;
2579 case 1:
2580 as_warn (_(":b not permitted; defaulting to :w"));
2581 /* Fall through. */
2582 case 2:
2583 nextword |= 0x2;
2584 break;
2585 case 3:
2586 nextword |= 0x3;
2587 break;
2588 }
2589 if (opP->mode == POST
2590 && (nextword & 0x40) == 0)
2591 nextword |= 0x04;
2592 }
2593 addword (nextword);
2594
2595 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2596 {
2597 if (opP->reg == PC || opP->reg == ZPC)
2598 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2599 else
2600 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2601 }
2602 if (siz1 == SIZE_LONG)
2603 addword (baseo >> 16);
2604 if (siz1 != SIZE_UNSPEC)
2605 addword (baseo);
2606
2607 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2608 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2609 if (siz2 == SIZE_LONG)
2610 addword (outro >> 16);
2611 if (siz2 != SIZE_UNSPEC)
2612 addword (outro);
2613
2614 break;
2615
2616 case ABSL:
3e602632 2617 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2618 switch (opP->disp.size)
2619 {
2620 default:
2621 abort ();
2622 case SIZE_UNSPEC:
2623 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2624 {
2625 tmpreg = 0x38; /* 7.0 */
2626 addword (nextword);
2627 break;
2628 }
252b5132
RH		 2629 if (isvar (&opP->disp)
2630 && !subs (&opP->disp)
2631 && adds (&opP->disp)
2632#ifdef OBJ_ELF
2633 /* If the displacement needs pic relocation it
2634 cannot be relaxed. */
2635 && opP->disp.pic_reloc == pic_none
2636#endif
252b5132
RH		 2637 && !flag_long_jumps
2638 && !strchr ("~%&$?", s[0]))
2639 {
2640 tmpreg = 0x3A; /* 7.2 */
2641 add_frag (adds (&opP->disp),
bd17c2c3 2642 SEXT (offs (&opP->disp)),
151337e8 2643 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2644 break;
2645 }
36759679 2646 /* Fall through into long. */
252b5132
RH		 2647 case SIZE_LONG:
2648 if (isvar (&opP->disp))
2649 add_fix ('l', &opP->disp, 0, 0);
2650
2651 tmpreg = 0x39;/* 7.1 mode */
2652 addword (nextword >> 16);
2653 addword (nextword);
2654 break;
2655
2656 case SIZE_BYTE:
2657 as_bad (_("unsupported byte value; use a different suffix"));
2658 /* Fall through. */
36759679
NC		 2659
2660 case SIZE_WORD:
252b5132
RH		 2661 if (isvar (&opP->disp))
2662 add_fix ('w', &opP->disp, 0, 0);
2663
2664 tmpreg = 0x38;/* 7.0 mode */
2665 addword (nextword);
2666 break;
2667 }
2668 break;
2669 case CONTROL:
2670 case FPREG:
2671 default:
2672 as_bad (_("unknown/incorrect operand"));
bc805888 2673 /* abort (); */
252b5132 2674 }
fd99574b
NC		 2675
2676 /* If s[0] is '4', then this is for the mac instructions
2677 that can have a trailing_ampersand set. If so, set 0x100
2678 bit on tmpreg so install_gen_operand can check for it and
2679 set the appropriate bit (word2, bit 5). */
2680 if (s[0] == '4')
2681 {
2682 if (opP->trailing_ampersand)
2683 tmpreg |= 0x100;
2684 }
252b5132
RH		 2685 install_gen_operand (s[1], tmpreg);
2686 break;
2687
2688 case '#':
2689 case '^':
2690 switch (s[1])
2691 { /* JF: I hate floating point! */
2692 case 'j':
2693 tmpreg = 70;
2694 break;
2695 case '8':
2696 tmpreg = 20;
2697 break;
2698 case 'C':
2699 tmpreg = 50;
2700 break;
2701 case '3':
2702 default:
3e602632 2703 tmpreg = 90;
252b5132
RH		 2704 break;
2705 }
2706 tmpreg = get_num (&opP->disp, tmpreg);
2707 if (isvar (&opP->disp))
2708 add_fix (s[1], &opP->disp, 0, 0);
2709 switch (s[1])
2710 {
2711 case 'b': /* Danger: These do no check for
2712 certain types of overflow.
2713 user beware! */
2714 if (!isbyte (tmpreg))
2715 opP->error = _("out of range");
2716 insop (tmpreg, opcode);
2717 if (isvar (&opP->disp))
2718 the_ins.reloc[the_ins.nrel - 1].n =
2719 (opcode->m_codenum) * 2 + 1;
2720 break;
2721 case 'B':
2722 if (!issbyte (tmpreg))
2723 opP->error = _("out of range");
2724 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2725 if (isvar (&opP->disp))
2726 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2727 break;
2728 case 'w':
2729 if (!isword (tmpreg))
2730 opP->error = _("out of range");
2731 insop (tmpreg, opcode);
2732 if (isvar (&opP->disp))
2733 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2734 break;
2735 case 'W':
2736 if (!issword (tmpreg))
2737 opP->error = _("out of range");
2738 insop (tmpreg, opcode);
2739 if (isvar (&opP->disp))
2740 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2741 break;
2742 case 'l':
2743 /* Because of the way insop works, we put these two out
2744 backwards. */
2745 insop (tmpreg, opcode);
2746 insop (tmpreg >> 16, opcode);
2747 if (isvar (&opP->disp))
2748 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2749 break;
2750 case '3':
2751 tmpreg &= 0xFF;
2752 case '8':
2753 case 'C':
2754 case 'j':
2755 install_operand (s[1], tmpreg);
2756 break;
2757 default:
2758 abort ();
2759 }
2760 break;
2761
2762 case '+':
2763 case '-':
2764 case 'A':
2765 case 'a':
2766 install_operand (s[1], opP->reg - ADDR);
2767 break;
2768
2769 case 'B':
3e602632 2770 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2771 switch (s[1])
2772 {
2773 case 'B':
8390138c 2774 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2775 break;
2776 case 'W':
2777 add_fix ('w', &opP->disp, 1, 0);
2778 addword (0);
2779 break;
2780 case 'L':
2781 long_branch:
151337e8 2782 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2783 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2784 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2785 add_fix ('l', &opP->disp, 1, 0);
2786 addword (0);
2787 addword (0);
2788 break;
2789 case 'g':
36759679 2790 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2791 goto long_branch;
2792
2793#ifdef OBJ_ELF
2794 /* If the displacement needs pic relocation it cannot be
2795 relaxed. */
2796 if (opP->disp.pic_reloc != pic_none)
2797 goto long_branch;
2798#endif
252b5132 2799 /* This could either be a symbol, or an absolute
151337e8
NC		 2800 address. If it's an absolute address, turn it into
2801 an absolute jump right here and keep it out of the
2802 relaxer. */
2803 if (adds (&opP->disp) == 0)
2804 {
2805 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2806 the_ins.opcode[0] = 0x4EF9;
151337e8 2807 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2808 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2809 else /* jCC */
2810 {
2811 the_ins.opcode[0] ^= 0x0100;
2812 the_ins.opcode[0] |= 0x0006;
18566f55 2813 addword (0x4EF9);
151337e8
NC		 2814 }
2815 add_fix ('l', &opP->disp, 0, 0);
2816 addword (0);
2817 addword (0);
2818 break;
2819 }
2820
2821 /* Now we know it's going into the relaxer. Now figure
2822 out which mode. We try in this order of preference:
2823 long branch, absolute jump, byte/word branches only. */
2824 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2825 add_frag (adds (&opP->disp),
2826 SEXT (offs (&opP->disp)),
151337e8
NC		 2827 TAB (BRANCHBWL, SZ_UNDEF));
2828 else if (! flag_keep_pcrel)
2829 {
2830 if ((the_ins.opcode[0] == 0x6000)
2831 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2832 add_frag (adds (&opP->disp),
2833 SEXT (offs (&opP->disp)),
151337e8
NC		 2834 TAB (BRABSJUNC, SZ_UNDEF));
2835 else
bd17c2c3
AM		 2836 add_frag (adds (&opP->disp),
2837 SEXT (offs (&opP->disp)),
151337e8
NC		 2838 TAB (BRABSJCOND, SZ_UNDEF));
2839 }
252b5132 2840 else
bd17c2c3
AM		 2841 add_frag (adds (&opP->disp),
2842 SEXT (offs (&opP->disp)),
151337e8 2843 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2844 break;
2845 case 'w':
2846 if (isvar (&opP->disp))
2847 {
151337e8
NC		 2848 /* Check for DBcc instructions. We can relax them,
2849 but only if we have long branches and/or absolute
2850 jumps. */
2851 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2852 && (HAVE_LONG_BRANCH (current_architecture)
2853 || (! flag_keep_pcrel)))
252b5132 2854 {
151337e8 2855 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2856 add_frag (adds (&opP->disp),
2857 SEXT (offs (&opP->disp)),
151337e8
NC		 2858 TAB (DBCCLBR, SZ_UNDEF));
2859 else
bd17c2c3
AM		 2860 add_frag (adds (&opP->disp),
2861 SEXT (offs (&opP->disp)),
151337e8 2862 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2863 break;
2864 }
252b5132
RH		 2865 add_fix ('w', &opP->disp, 1, 0);
2866 }
2867 addword (0);
2868 break;
36759679 2869 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2870 add_fix ('l', &opP->disp, 1, 0);
2871 addword (0);
2872 addword (0);
2873 break;
36759679 2874 case 'c': /* Var size Coprocesssor branches. */
151337e8 2875 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2876 {
252b5132
RH		 2877 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2878 add_fix ('l', &opP->disp, 1, 0);
2879 addword (0);
2880 addword (0);
2881 }
151337e8 2882 else
bd17c2c3
AM		 2883 add_frag (adds (&opP->disp),
2884 SEXT (offs (&opP->disp)),
151337e8 2885 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2886 break;
2887 default:
2888 abort ();
2889 }
2890 break;
2891
36759679 2892 case 'C': /* Ignore it. */
252b5132
RH		 2893 break;
2894
36759679 2895 case 'd': /* JF this is a kludge. */
252b5132 2896 install_operand ('s', opP->reg - ADDR);
3e602632 2897 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2898 if (!issword (tmpreg))
2899 {
2900 as_warn (_("Expression out of range, using 0"));
2901 tmpreg = 0;
2902 }
2903 addword (tmpreg);
2904 break;
2905
2906 case 'D':
2907 install_operand (s[1], opP->reg - DATA);
2908 break;
2909
fd99574b
NC		 2910 case 'e': /* EMAC ACCx, reg/reg. */
2911 install_operand (s[1], opP->reg - ACC);
2912 break;
2913
36759679 2914 case 'E': /* Ignore it. */
6da466c7
ILT		 2915 break;
2916
252b5132
RH		 2917 case 'F':
2918 install_operand (s[1], opP->reg - FP0);
2919 break;
2920
fd99574b
NC		 2921 case 'g': /* EMAC ACCEXTx. */
2922 install_operand (s[1], opP->reg - ACCEXT01);
2923 break;
2924
36759679 2925 case 'G': /* Ignore it. */
6da466c7
ILT		 2926 case 'H':
2927 break;
2928
252b5132
RH		 2929 case 'I':
2930 tmpreg = opP->reg - COP0;
2931 install_operand (s[1], tmpreg);
2932 break;
2933
fd99574b
NC		 2934 case 'i': /* MAC/EMAC scale factor. */
2935 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2936 break;
2937
36759679 2938 case 'J': /* JF foo. */
252b5132
RH		 2939 switch (opP->reg)
2940 {
2941 case SFC:
2942 tmpreg = 0x000;
2943 break;
2944 case DFC:
2945 tmpreg = 0x001;
2946 break;
2947 case CACR:
2948 tmpreg = 0x002;
2949 break;
2950 case TC:
2951 tmpreg = 0x003;
2952 break;
3e602632 2953 case ACR0:
252b5132
RH		 2954 case ITT0:
2955 tmpreg = 0x004;
2956 break;
3e602632 2957 case ACR1:
252b5132
RH		 2958 case ITT1:
2959 tmpreg = 0x005;
2960 break;
3e602632 2961 case ACR2:
252b5132
RH		 2962 case DTT0:
2963 tmpreg = 0x006;
2964 break;
3e602632 2965 case ACR3:
252b5132
RH		 2966 case DTT1:
2967 tmpreg = 0x007;
2968 break;
2969 case BUSCR:
2970 tmpreg = 0x008;
2971 break;
2972
2973 case USP:
2974 tmpreg = 0x800;
2975 break;
2976 case VBR:
2977 tmpreg = 0x801;
2978 break;
2979 case CAAR:
2980 tmpreg = 0x802;
2981 break;
2982 case MSP:
2983 tmpreg = 0x803;
2984 break;
2985 case ISP:
2986 tmpreg = 0x804;
2987 break;
2988 case MMUSR:
2989 tmpreg = 0x805;
2990 break;
2991 case URP:
2992 tmpreg = 0x806;
2993 break;
2994 case SRP:
2995 tmpreg = 0x807;
2996 break;
2997 case PCR:
2998 tmpreg = 0x808;
2999 break;
3000 case ROMBAR:
3001 tmpreg = 0xC00;
3002 break;
3e602632
NC		 3003 case ROMBAR1:
3004 tmpreg = 0xC01;
3005 break;
3006 case FLASHBAR:
252b5132
RH		 3007 case RAMBAR0:
3008 tmpreg = 0xC04;
3009 break;
3e602632 3010 case RAMBAR:
252b5132
RH		 3011 case RAMBAR1:
3012 tmpreg = 0xC05;
3013 break;
3e602632
NC		 3014 case MPCR:
3015 tmpreg = 0xC0C;
3016 break;
3017 case EDRAMBAR:
3018 tmpreg = 0xC0D;
3019 break;
3020 case MBAR0:
e80e0390 3021 case MBAR2:
3e602632
NC		 3022 case SECMBAR:
3023 tmpreg = 0xC0E;
3024 break;
3025 case MBAR1:
252b5132
RH		 3026 case MBAR:
3027 tmpreg = 0xC0F;
3028 break;
3e602632
NC		 3029 case PCR1U0:
3030 tmpreg = 0xD02;
3031 break;
3032 case PCR1L0:
3033 tmpreg = 0xD03;
3034 break;
3035 case PCR2U0:
3036 tmpreg = 0xD04;
3037 break;
3038 case PCR2L0:
3039 tmpreg = 0xD05;
3040 break;
3041 case PCR3U0:
3042 tmpreg = 0xD06;
3043 break;
3044 case PCR3L0:
3045 tmpreg = 0xD07;
3046 break;
3047 case PCR1L1:
3048 tmpreg = 0xD0A;
3049 break;
3050 case PCR1U1:
3051 tmpreg = 0xD0B;
3052 break;
3053 case PCR2L1:
3054 tmpreg = 0xD0C;
3055 break;
3056 case PCR2U1:
3057 tmpreg = 0xD0D;
3058 break;
3059 case PCR3L1:
3060 tmpreg = 0xD0E;
3061 break;
3062 case PCR3U1:
3063 tmpreg = 0xD0F;
3064 break;
252b5132
RH		 3065 default:
3066 abort ();
3067 }
3068 install_operand (s[1], tmpreg);
3069 break;
3070
3071 case 'k':
3072 tmpreg = get_num (&opP->disp, 55);
3073 install_operand (s[1], tmpreg & 0x7f);
3074 break;
3075
3076 case 'l':
3077 tmpreg = opP->mask;
3078 if (s[1] == 'w')
3079 {
3080 if (tmpreg & 0x7FF0000)
3081 as_bad (_("Floating point register in register list"));
3082 insop (reverse_16_bits (tmpreg), opcode);
3083 }
3084 else
3085 {
3086 if (tmpreg & 0x700FFFF)
3087 as_bad (_("Wrong register in floating-point reglist"));
3088 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3089 }
3090 break;
3091
3092 case 'L':
3093 tmpreg = opP->mask;
3094 if (s[1] == 'w')
3095 {
3096 if (tmpreg & 0x7FF0000)
3097 as_bad (_("Floating point register in register list"));
3098 insop (tmpreg, opcode);
3099 }
3100 else if (s[1] == '8')
3101 {
3102 if (tmpreg & 0x0FFFFFF)
3103 as_bad (_("incorrect register in reglist"));
3104 install_operand (s[1], tmpreg >> 24);
3105 }
3106 else
3107 {
3108 if (tmpreg & 0x700FFFF)
3109 as_bad (_("wrong register in floating-point reglist"));
3110 else
3111 install_operand (s[1], tmpreg >> 16);
3112 }
3113 break;
3114
3115 case 'M':
3116 install_operand (s[1], get_num (&opP->disp, 60));
3117 break;
3118
3119 case 'O':
3120 tmpreg = ((opP->mode == DREG)
8fce3f5e 3121 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3122 : (get_num (&opP->disp, 40) & 0x1F));
3123 install_operand (s[1], tmpreg);
3124 break;
3125
3126 case 'Q':
3127 tmpreg = get_num (&opP->disp, 10);
3128 if (tmpreg == 8)
3129 tmpreg = 0;
3130 install_operand (s[1], tmpreg);
3131 break;
3132
3133 case 'R':
3134 /* This depends on the fact that ADDR registers are eight
3135 more than their corresponding DATA regs, so the result
36759679 3136 will have the ADDR_REG bit set. */
252b5132
RH		 3137 install_operand (s[1], opP->reg - DATA);
3138 break;
3139
3140 case 'r':
3141 if (opP->mode == AINDR)
3142 install_operand (s[1], opP->reg - DATA);
3143 else
3144 install_operand (s[1], opP->index.reg - DATA);
3145 break;
3146
3147 case 's':
3148 if (opP->reg == FPI)
3149 tmpreg = 0x1;
3150 else if (opP->reg == FPS)
3151 tmpreg = 0x2;
3152 else if (opP->reg == FPC)
3153 tmpreg = 0x4;
3154 else
3155 abort ();
3156 install_operand (s[1], tmpreg);
3157 break;
3158
36759679 3159 case 'S': /* Ignore it. */
252b5132
RH		 3160 break;
3161
3162 case 'T':
3163 install_operand (s[1], get_num (&opP->disp, 30));
3164 break;
3165
36759679 3166 case 'U': /* Ignore it. */
252b5132
RH		 3167 break;
3168
3169 case 'c':
3170 switch (opP->reg)
3171 {
3172 case NC:
3173 tmpreg = 0;
3174 break;
3175 case DC:
3176 tmpreg = 1;
3177 break;
3178 case IC:
3179 tmpreg = 2;
3180 break;
3181 case BC:
3182 tmpreg = 3;
3183 break;
3184 default:
3185 as_fatal (_("failed sanity check"));
36759679 3186 } /* switch on cache token. */
252b5132
RH		 3187 install_operand (s[1], tmpreg);
3188 break;
3189#ifndef NO_68851
92774660 3190 /* JF: These are out of order, I fear. */
252b5132
RH		 3191 case 'f':
3192 switch (opP->reg)
3193 {
3194 case SFC:
3195 tmpreg = 0;
3196 break;
3197 case DFC:
3198 tmpreg = 1;
3199 break;
3200 default:
3201 abort ();
3202 }
3203 install_operand (s[1], tmpreg);
3204 break;
3205
3206 case '0':
3207 case '1':
3208 case '2':
3209 switch (opP->reg)
3210 {
3211 case TC:
3212 tmpreg = 0;
3213 break;
3214 case CAL:
3215 tmpreg = 4;
3216 break;
3217 case VAL:
3218 tmpreg = 5;
3219 break;
3220 case SCC:
3221 tmpreg = 6;
3222 break;
3223 case AC:
3224 tmpreg = 7;
3225 break;
3226 default:
3227 abort ();
3228 }
3229 install_operand (s[1], tmpreg);
3230 break;
3231
3232 case 'V':
3233 if (opP->reg == VAL)
3234 break;
3235 abort ();
3236
3237 case 'W':
3238 switch (opP->reg)
3239 {
3240 case DRP:
3241 tmpreg = 1;
3242 break;
3243 case SRP:
3244 tmpreg = 2;
3245 break;
3246 case CRP:
3247 tmpreg = 3;
3248 break;
3249 default:
3250 abort ();
3251 }
3252 install_operand (s[1], tmpreg);
3253 break;
3254
3255 case 'X':
3256 switch (opP->reg)
3257 {
3258 case BAD:
3259 case BAD + 1:
3260 case BAD + 2:
3261 case BAD + 3:
3262 case BAD + 4:
3263 case BAD + 5:
3264 case BAD + 6:
3265 case BAD + 7:
3266 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3267 break;
3268
3269 case BAC:
3270 case BAC + 1:
3271 case BAC + 2:
3272 case BAC + 3:
3273 case BAC + 4:
3274 case BAC + 5:
3275 case BAC + 6:
3276 case BAC + 7:
3277 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3278 break;
3279
3280 default:
3281 abort ();
3282 }
3283 install_operand (s[1], tmpreg);
3284 break;
3285 case 'Y':
3286 know (opP->reg == PSR);
3287 break;
3288 case 'Z':
3289 know (opP->reg == PCSR);
3290 break;
3291#endif /* m68851 */
3292 case '3':
3293 switch (opP->reg)
3294 {
3295 case TT0:
3296 tmpreg = 2;
3297 break;
3298 case TT1:
3299 tmpreg = 3;
3300 break;
3301 default:
3302 abort ();
3303 }
3304 install_operand (s[1], tmpreg);
3305 break;
3306 case 't':
3307 tmpreg = get_num (&opP->disp, 20);
3308 install_operand (s[1], tmpreg);
3309 break;
36759679 3310 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3311 if (isvar (&opP->disp))
3312 add_fix ('l', &opP->disp, 0, 0);
3e602632 3313 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3314 addword (tmpreg >> 16);
3315 addword (tmpreg & 0xFFFF);
3316 break;
6da466c7
ILT		 3317 case 'u':
3318 install_operand (s[1], opP->reg - DATA0L);
3319 opP->reg -= (DATA0L);
36759679 3320 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3321 break;
3e602632
NC		 3322 case 'x':
3323 tmpreg = get_num (&opP->disp, 80);
3324 if (tmpreg == -1)
3325 tmpreg = 0;
3326 install_operand (s[1], tmpreg);
3327 break;
252b5132
RH		 3328 default:
3329 abort ();
3330 }
3331 }
3332
3333 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3334 instruction, ready to be emitted. . . */
252b5132
RH		 3335}
3336
3337static int
31302357 3338reverse_16_bits (int in)
252b5132
RH		 3339{
3340 int out = 0;
3341 int n;
3342
3343 static int mask[16] =
3344 {
3345 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3346 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3347 };
3348 for (n = 0; n < 16; n++)
3349 {
3350 if (in & mask[n])
3351 out |= mask[15 - n];
3352 }
3353 return out;
3354} /* reverse_16_bits() */
3355
3356static int
31302357 3357reverse_8_bits (int in)
252b5132
RH		 3358{
3359 int out = 0;
3360 int n;
3361
3362 static int mask[8] =
3363 {
3364 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3365 };
3366
3367 for (n = 0; n < 8; n++)
3368 {
3369 if (in & mask[n])
3370 out |= mask[7 - n];
3371 }
3372 return out;
3373} /* reverse_8_bits() */
3374
3375/* Cause an extra frag to be generated here, inserting up to 10 bytes
3376 (that value is chosen in the frag_var call in md_assemble). TYPE
3377 is the subtype of the frag to be generated; its primary type is
3378 rs_machine_dependent.
3379
3380 The TYPE parameter is also used by md_convert_frag_1 and
3381 md_estimate_size_before_relax. The appropriate type of fixup will
3382 be emitted by md_convert_frag_1.
3383
3384 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3385static void
31302357 3386install_operand (int mode, int val)
252b5132
RH		 3387{
3388 switch (mode)
3389 {
3390 case 's':
36759679 3391 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3392 break;
3393 case 'd':
3394 the_ins.opcode[0] |= val << 9;
3395 break;
3396 case '1':
3397 the_ins.opcode[1] |= val << 12;
3398 break;
3399 case '2':
3400 the_ins.opcode[1] |= val << 6;
3401 break;
3402 case '3':
3403 the_ins.opcode[1] |= val;
3404 break;
3405 case '4':
3406 the_ins.opcode[2] |= val << 12;
3407 break;
3408 case '5':
3409 the_ins.opcode[2] |= val << 6;
3410 break;
3411 case '6':
3412 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3413 three words long! */
3414 the_ins.numo++;
3415 the_ins.opcode[2] |= val;
3416 break;
3417 case '7':
3418 the_ins.opcode[1] |= val << 7;
3419 break;
3420 case '8':
3421 the_ins.opcode[1] |= val << 10;
3422 break;
3423#ifndef NO_68851
3424 case '9':
3425 the_ins.opcode[1] |= val << 5;
3426 break;
3427#endif
3428
3429 case 't':
3430 the_ins.opcode[1] |= (val << 10) | (val << 7);
3431 break;
3432 case 'D':
3433 the_ins.opcode[1] |= (val << 12) | val;
3434 break;
3435 case 'g':
3436 the_ins.opcode[0] |= val = 0xff;
3437 break;
3438 case 'i':
3439 the_ins.opcode[0] |= val << 9;
3440 break;
3441 case 'C':
3442 the_ins.opcode[1] |= val;
3443 break;
3444 case 'j':
3445 the_ins.opcode[1] |= val;
36759679 3446 the_ins.numo++; /* What a hack. */
252b5132
RH		 3447 break;
3448 case 'k':
3449 the_ins.opcode[1] |= val << 4;
3450 break;
3451 case 'b':
3452 case 'w':
3453 case 'W':
3454 case 'l':
3455 break;
3456 case 'e':
3457 the_ins.opcode[0] |= (val << 6);
3458 break;
3459 case 'L':
3460 the_ins.opcode[1] = (val >> 16);
3461 the_ins.opcode[2] = val & 0xffff;
3462 break;
6da466c7
ILT		 3463 case 'm':
3464 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3465 the_ins.opcode[0] |= ((val & 0x7) << 9);
3466 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3467 break;
fd99574b 3468 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3469 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3470 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3471 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3472 break;
fd99574b 3473 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3474 the_ins.opcode[1] |= val << 12;
3475 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3476 break;
fd99574b 3477 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3478 the_ins.opcode[0] |= (val & 0xF);
3479 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3480 break;
fd99574b 3481 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3482 the_ins.opcode[1] |= (val & 0xF);
3483 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3484 break;
3485 case 'h':
3486 the_ins.opcode[1] |= ((val != 1) << 10);
3487 break;
fd99574b
NC		 3488 case 'F':
3489 the_ins.opcode[0] |= ((val & 0x3) << 9);
3490 break;
3491 case 'f':
3492 the_ins.opcode[0] |= ((val & 0x3) << 0);
3493 break;
be8c092b 3494 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3495 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3496 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3497 break;
be8c092b 3498 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3499 the_ins.opcode[0] |= ((val & 0x1) << 7);
3500 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3501 break;
3502 case 'I':
3503 the_ins.opcode[1] |= ((val & 0x3) << 9);
3504 break;
3505 case ']':
3506 the_ins.opcode[0] |= (val & 0x1) <<10;
3507 break;
252b5132
RH		 3508 case 'c':
3509 default:
3510 as_fatal (_("failed sanity check."));
3511 }
6b6e92f4 3512}
252b5132
RH		 3513
3514static void
31302357 3515install_gen_operand (int mode, int val)
252b5132
RH		 3516{
3517 switch (mode)
3518 {
fd99574b
NC		 3519 case '/': /* Special for mask loads for mac/msac insns with
3520 possible mask; trailing_ampersend set in bit 8. */
3521 the_ins.opcode[0] |= (val & 0x3f);
3522 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3523 break;
252b5132
RH		 3524 case 's':
3525 the_ins.opcode[0] |= val;
3526 break;
3527 case 'd':
3528 /* This is a kludge!!! */
3529 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3530 break;
3531 case 'b':
3532 case 'w':
3533 case 'l':
3534 case 'f':
3535 case 'F':
3536 case 'x':
3537 case 'p':
3538 the_ins.opcode[0] |= val;
3539 break;
36759679 3540 /* more stuff goes here. */
252b5132
RH		 3541 default:
3542 as_fatal (_("failed sanity check."));
3543 }
6b6e92f4 3544}
252b5132 3545
6b6e92f4
NC		 3546/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3547 then deal with the bitfield hack. */
252b5132
RH		 3548
3549static char *
31302357 3550crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3551{
3552 register int parens;
3553 register int c;
3554 register char *beg_str;
3555 int inquote = 0;
3556
3557 if (!str)
3558 {
3559 return str;
3560 }
3561 beg_str = str;
3562 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3563 {
3564 if (! inquote)
3565 {
3566 if (*str == '(')
3567 parens++;
3568 else if (*str == ')')
3569 {
3570 if (!parens)
36759679 3571 { /* ERROR. */
252b5132
RH		 3572 opP->error = _("Extra )");
3573 return str;
3574 }
3575 --parens;
3576 }
3577 }
3578 if (flag_mri && *str == '\'')
3579 inquote = ! inquote;
3580 }
3581 if (!*str && parens)
36759679 3582 { /* ERROR. */
252b5132
RH		 3583 opP->error = _("Missing )");
3584 return str;
3585 }
3586 c = *str;
3587 *str = '\0';
3588 if (m68k_ip_op (beg_str, opP) != 0)
3589 {
3590 *str = c;
3591 return str;
3592 }
3593 *str = c;
3594 if (c == '}')
36759679 3595 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3596 if (c)
3597 {
3598 c = *++str;
3599 if (!c)
3600 as_bad (_("Missing operand"));
3601 }
3602
3603 /* Detect MRI REG symbols and convert them to REGLSTs. */
3604 if (opP->mode == CONTROL && (int)opP->reg < 0)
3605 {
3606 opP->mode = REGLST;
3607 opP->mask = ~(int)opP->reg;
3608 opP->reg = 0;
3609 }
3610
3611 return str;
3612}
3613
3614/* This is the guts of the machine-dependent assembler. STR points to a
3615 machine dependent instruction. This function is supposed to emit
3616 the frags/bytes it assembles to.
3617 */
3618
3619static void
31302357 3620insert_reg (const char *regname, int regnum)
252b5132
RH		 3621{
3622 char buf[100];
3623 int i;
3624
3625#ifdef REGISTER_PREFIX
3626 if (!flag_reg_prefix_optional)
3627 {
3628 buf[0] = REGISTER_PREFIX;
3629 strcpy (buf + 1, regname);
3630 regname = buf;
3631 }
3632#endif
3633
3634 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3635 &zero_address_frag));
3636
3637 for (i = 0; regname[i]; i++)
3882b010 3638 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3639 buf[i] = '\0';
3640
3641 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3642 &zero_address_frag));
3643}
3644
3645struct init_entry
3646 {
3647 const char *name;
3648 int number;
3649 };
3650
3651static const struct init_entry init_table[] =
3652{
3653 { "d0", DATA0 },
3654 { "d1", DATA1 },
3655 { "d2", DATA2 },
3656 { "d3", DATA3 },
3657 { "d4", DATA4 },
3658 { "d5", DATA5 },
3659 { "d6", DATA6 },
3660 { "d7", DATA7 },
3661 { "a0", ADDR0 },
3662 { "a1", ADDR1 },
3663 { "a2", ADDR2 },
3664 { "a3", ADDR3 },
3665 { "a4", ADDR4 },
3666 { "a5", ADDR5 },
3667 { "a6", ADDR6 },
3668 { "fp", ADDR6 },
3669 { "a7", ADDR7 },
3670 { "sp", ADDR7 },
3671 { "ssp", ADDR7 },
3672 { "fp0", FP0 },
3673 { "fp1", FP1 },
3674 { "fp2", FP2 },
3675 { "fp3", FP3 },
3676 { "fp4", FP4 },
3677 { "fp5", FP5 },
3678 { "fp6", FP6 },
3679 { "fp7", FP7 },
3680 { "fpi", FPI },
3681 { "fpiar", FPI },
3682 { "fpc", FPI },
3683 { "fps", FPS },
3684 { "fpsr", FPS },
3685 { "fpc", FPC },
3686 { "fpcr", FPC },
3687 { "control", FPC },
3688 { "status", FPS },
3689 { "iaddr", FPI },
3690
3691 { "cop0", COP0 },
3692 { "cop1", COP1 },
3693 { "cop2", COP2 },
3694 { "cop3", COP3 },
3695 { "cop4", COP4 },
3696 { "cop5", COP5 },
3697 { "cop6", COP6 },
3698 { "cop7", COP7 },
3699 { "pc", PC },
3700 { "zpc", ZPC },
3701 { "sr", SR },
3702
3703 { "ccr", CCR },
3704 { "cc", CCR },
3705
6da466c7 3706 { "acc", ACC },
fd99574b
NC		 3707 { "acc0", ACC },
3708 { "acc1", ACC1 },
3709 { "acc2", ACC2 },
3710 { "acc3", ACC3 },
3711 { "accext01", ACCEXT01 },
3712 { "accext23", ACCEXT23 },
6da466c7
ILT		 3713 { "macsr", MACSR },
3714 { "mask", MASK },
3715
36759679
NC		 3716 /* Control registers. */
3717 { "sfc", SFC }, /* Source Function Code. */
252b5132 3718 { "sfcr", SFC },
36759679 3719 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3720 { "dfcr", DFC },
36759679
NC		 3721 { "cacr", CACR }, /* Cache Control Register. */
3722 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3723
36759679
NC		 3724 { "usp", USP }, /* User Stack Pointer. */
3725 { "vbr", VBR }, /* Vector Base Register. */
3726 { "msp", MSP }, /* Master Stack Pointer. */
3727 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3728
36759679
NC		 3729 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3730 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3731 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3732 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3733
3734 /* 68ec040 versions of same */
36759679
NC		 3735 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3736 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3737 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3738 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3739
3740 /* mcf5200 versions of same. The ColdFire programmer's reference
3741 manual indicated that the order is 2,3,0,1, but Ken Rose
3742 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3743 { "acr0", ACR0 }, /* Access Control Unit 0. */
3744 { "acr1", ACR1 }, /* Access Control Unit 1. */
3745 { "acr2", ACR2 }, /* Access Control Unit 2. */
3746 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3747
36759679 3748 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3749 { "tcr", TC },
3750
36759679
NC		 3751 { "mmusr", MMUSR }, /* MMU Status Register. */
3752 { "srp", SRP }, /* User Root Pointer. */
3753 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3754
3755 { "buscr", BUSCR },
3756 { "pcr", PCR },
3757
36759679
NC		 3758 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3759 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3760 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3761 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3762
3763 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3764 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3765 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3766 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3767 { "mpcr", MPCR }, /* mcfv4e registers. */
3768 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3769 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3770 { "asid", TC }, /* mcfv4e registers. */
3771 { "mmubar", BUSCR }, /* mcfv4e registers. */
3772 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3773 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3774 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3775 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3776 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3777 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3778 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3779 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3780 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3781 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3782 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3783 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3784
3785 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3786 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3787
3788 { "mbar2", MBAR2 }, /* mcf5249 registers. */
36759679 3789 /* End of control registers. */
252b5132
RH		 3790
3791 { "ac", AC },
3792 { "bc", BC },
3793 { "cal", CAL },
3794 { "crp", CRP },
3795 { "drp", DRP },
3796 { "pcsr", PCSR },
3797 { "psr", PSR },
3798 { "scc", SCC },
3799 { "val", VAL },
3800 { "bad0", BAD0 },
3801 { "bad1", BAD1 },
3802 { "bad2", BAD2 },
3803 { "bad3", BAD3 },
3804 { "bad4", BAD4 },
3805 { "bad5", BAD5 },
3806 { "bad6", BAD6 },
3807 { "bad7", BAD7 },
3808 { "bac0", BAC0 },
3809 { "bac1", BAC1 },
3810 { "bac2", BAC2 },
3811 { "bac3", BAC3 },
3812 { "bac4", BAC4 },
3813 { "bac5", BAC5 },
3814 { "bac6", BAC6 },
3815 { "bac7", BAC7 },
3816
3817 { "ic", IC },
3818 { "dc", DC },
3819 { "nc", NC },
3820
3821 { "tt0", TT0 },
3822 { "tt1", TT1 },
36759679 3823 /* 68ec030 versions of same. */
252b5132
RH		 3824 { "ac0", TT0 },
3825 { "ac1", TT1 },
36759679 3826 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3827 { "acusr", PSR },
3828
3829 /* Suppressed data and address registers. */
3830 { "zd0", ZDATA0 },
3831 { "zd1", ZDATA1 },
3832 { "zd2", ZDATA2 },
3833 { "zd3", ZDATA3 },
3834 { "zd4", ZDATA4 },
3835 { "zd5", ZDATA5 },
3836 { "zd6", ZDATA6 },
3837 { "zd7", ZDATA7 },
3838 { "za0", ZADDR0 },
3839 { "za1", ZADDR1 },
3840 { "za2", ZADDR2 },
3841 { "za3", ZADDR3 },
3842 { "za4", ZADDR4 },
3843 { "za5", ZADDR5 },
3844 { "za6", ZADDR6 },
3845 { "za7", ZADDR7 },
3846
92774660 3847 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3848 { "d0l", DATA0L },
3849 { "d1l", DATA1L },
3850 { "d2l", DATA2L },
3851 { "d3l", DATA3L },
3852 { "d4l", DATA4L },
3853 { "d5l", DATA5L },
3854 { "d6l", DATA6L },
3855 { "d7l", DATA7L },
3856
3857 { "a0l", ADDR0L },
3858 { "a1l", ADDR1L },
3859 { "a2l", ADDR2L },
3860 { "a3l", ADDR3L },
3861 { "a4l", ADDR4L },
3862 { "a5l", ADDR5L },
3863 { "a6l", ADDR6L },
3864 { "a7l", ADDR7L },
3865
3866 { "d0u", DATA0U },
3867 { "d1u", DATA1U },
3868 { "d2u", DATA2U },
3869 { "d3u", DATA3U },
3870 { "d4u", DATA4U },
3871 { "d5u", DATA5U },
3872 { "d6u", DATA6U },
3873 { "d7u", DATA7U },
3874
3875 { "a0u", ADDR0U },
3876 { "a1u", ADDR1U },
3877 { "a2u", ADDR2U },
3878 { "a3u", ADDR3U },
3879 { "a4u", ADDR4U },
3880 { "a5u", ADDR5U },
3881 { "a6u", ADDR6U },
3882 { "a7u", ADDR7U },
3883
252b5132
RH		 3884 { 0, 0 }
3885};
3886
3887static void
31302357 3888init_regtable (void)
252b5132
RH		 3889{
3890 int i;
3891 for (i = 0; init_table[i].name; i++)
3892 insert_reg (init_table[i].name, init_table[i].number);
3893}
3894
3895static int no_68851, no_68881;
3896
3897#ifdef OBJ_AOUT
3898/* a.out machine type. Default to 68020. */
3899int m68k_aout_machtype = 2;
3900#endif
3901
3902void
31302357 3903md_assemble (char *str)
252b5132
RH		 3904{
3905 const char *er;
3906 short *fromP;
3907 char *toP = NULL;
3908 int m, n = 0;
3909 char *to_beg_P;
3910 int shorts_this_frag;
3911 fixS *fixP;
3912
3913 /* In MRI mode, the instruction and operands are separated by a
3914 space. Anything following the operands is a comment. The label
3915 has already been removed. */
3916 if (flag_mri)
3917 {
3918 char *s;
3919 int fields = 0;
3920 int infield = 0;
3921 int inquote = 0;
3922
3923 for (s = str; *s != '\0'; s++)
3924 {
3925 if ((*s == ' ' || *s == '\t') && ! inquote)
3926 {
3927 if (infield)
3928 {
3929 ++fields;
3930 if (fields >= 2)
3931 {
3932 *s = '\0';
3933 break;
3934 }
3935 infield = 0;
3936 }
3937 }
3938 else
3939 {
3940 if (! infield)
3941 infield = 1;
3942 if (*s == '\'')
3943 inquote = ! inquote;
3944 }
3945 }
3946 }
3947
31302357 3948 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 3949 m68k_ip (str);
3950 er = the_ins.error;
3951 if (!er)
3952 {
3953 for (n = 0; n < the_ins.numargs; n++)
3954 if (the_ins.operands[n].error)
3955 {
3956 er = the_ins.operands[n].error;
3957 break;
3958 }
3959 }
3960 if (er)
3961 {
3962 as_bad (_("%s -- statement `%s' ignored"), er, str);
3963 return;
3964 }
3965
3966 /* If there is a current label, record that it marks an instruction. */
3967 if (current_label != NULL)
3968 {
3969 current_label->text = 1;
3970 current_label = NULL;
3971 }
3972
f27a3839
AS		 3973#ifdef OBJ_ELF
3974 /* Tie dwarf2 debug info to the address at the start of the insn. */
3975 dwarf2_emit_insn (0);
3976#endif
3977
252b5132
RH		 3978 if (the_ins.nfrag == 0)
3979 {
36759679 3980 /* No frag hacking involved; just put it out. */
252b5132
RH		 3981 toP = frag_more (2 * the_ins.numo);
3982 fromP = &the_ins.opcode[0];
3983 for (m = the_ins.numo; m; --m)
3984 {
3985 md_number_to_chars (toP, (long) (*fromP), 2);
3986 toP += 2;
3987 fromP++;
3988 }
36759679 3989 /* Put out symbol-dependent info. */
252b5132
RH		 3990 for (m = 0; m < the_ins.nrel; m++)
3991 {
3992 switch (the_ins.reloc[m].wid)
3993 {
3994 case 'B':
3995 n = 1;
3996 break;
3997 case 'b':
3998 n = 1;
3999 break;
4000 case '3':
4001 n = 1;
4002 break;
4003 case 'w':
4004 case 'W':
4005 n = 2;
4006 break;
4007 case 'l':
4008 n = 4;
4009 break;
4010 default:
4011 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4012 the_ins.reloc[m].wid);
4013 }
4014
4015 fixP = fix_new_exp (frag_now,
4016 ((toP - frag_now->fr_literal)
4017 - the_ins.numo * 2 + the_ins.reloc[m].n),
4018 n,
4019 &the_ins.reloc[m].exp,
4020 the_ins.reloc[m].pcrel,
4021 get_reloc_code (n, the_ins.reloc[m].pcrel,
4022 the_ins.reloc[m].pic_reloc));
4023 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4024 if (the_ins.reloc[m].wid == 'B')
4025 fixP->fx_signed = 1;
4026 }
4027 return;
4028 }
4029
36759679 4030 /* There's some frag hacking. */
fbe572f9
AM		 4031 {
4032 /* Calculate the max frag size. */
4033 int wid;
4034
4035 wid = 2 * the_ins.fragb[0].fragoff;
4036 for (n = 1; n < the_ins.nfrag; n++)
4037 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4038 /* frag_var part. */
4039 wid += 10;
4040 /* Make sure the whole insn fits in one chunk, in particular that
4041 the var part is attached, as we access one byte before the
4042 variable frag for byte branches. */
4043 frag_grow (wid);
4044 }
4045
252b5132
RH		 4046 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4047 {
4048 int wid;
4049
4050 if (n == 0)
4051 wid = 2 * the_ins.fragb[n].fragoff;
4052 else
4053 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4054 toP = frag_more (wid);
4055 to_beg_P = toP;
4056 shorts_this_frag = 0;
4057 for (m = wid / 2; m; --m)
4058 {
4059 md_number_to_chars (toP, (long) (*fromP), 2);
4060 toP += 2;
4061 fromP++;
4062 shorts_this_frag++;
4063 }
4064 for (m = 0; m < the_ins.nrel; m++)
4065 {
4066 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4067 {
4068 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4069 break;
4070 }
4071 wid = the_ins.reloc[m].wid;
4072 if (wid == 0)
4073 continue;
4074 the_ins.reloc[m].wid = 0;
4075 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4076
4077 fixP = fix_new_exp (frag_now,
4078 ((toP - frag_now->fr_literal)
4079 - the_ins.numo * 2 + the_ins.reloc[m].n),
4080 wid,
4081 &the_ins.reloc[m].exp,
4082 the_ins.reloc[m].pcrel,
4083 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4084 the_ins.reloc[m].pic_reloc));
4085 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4086 }
4087 (void) frag_var (rs_machine_dependent, 10, 0,
4088 (relax_substateT) (the_ins.fragb[n].fragty),
4089 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4090 }
4091 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4092 shorts_this_frag = 0;
4093 if (n)
4094 {
055d1eb0 4095 toP = frag_more (n * 2);
252b5132
RH		 4096 while (n--)
4097 {
4098 md_number_to_chars (toP, (long) (*fromP), 2);
4099 toP += 2;
4100 fromP++;
4101 shorts_this_frag++;
4102 }
4103 }
4104 for (m = 0; m < the_ins.nrel; m++)
4105 {
4106 int wid;
4107
4108 wid = the_ins.reloc[m].wid;
4109 if (wid == 0)
4110 continue;
4111 the_ins.reloc[m].wid = 0;
4112 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4113
4114 fixP = fix_new_exp (frag_now,
4115 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4116 - shorts_this_frag * 2),
4117 wid,
4118 &the_ins.reloc[m].exp,
4119 the_ins.reloc[m].pcrel,
4120 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4121 the_ins.reloc[m].pic_reloc));
4122 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4123 }
4124}
4125
60fed2d3
NC		 4126/* Comparison function used by qsort to rank the opcode entries by name. */
4127
4128static int
4129m68k_compare_opcode (const void * v1, const void * v2)
4130{
4131 struct m68k_opcode * op1, * op2;
4132 int ret;
4133
03b13e59
NC		 4134 if (v1 == v2)
4135 return 0;
4136
60fed2d3
NC		 4137 op1 = *(struct m68k_opcode **) v1;
4138 op2 = *(struct m68k_opcode **) v2;
4139
4140 /* Compare the two names. If different, return the comparison.
4141 If the same, return the order they are in the opcode table. */
4142 ret = strcmp (op1->name, op2->name);
4143 if (ret)
4144 return ret;
4145 if (op1 < op2)
4146 return -1;
03b13e59 4147 return 1;
60fed2d3
NC		 4148}
4149
252b5132 4150void
60fed2d3 4151md_begin (void)
252b5132 4152{
60fed2d3
NC		 4153 const struct m68k_opcode *ins;
4154 struct m68k_incant *hack, *slak;
4155 const char *retval = 0; /* Empty string, or error msg text. */
4156 int i;
4157
4158 /* Set up hash tables with 68000 instructions.
4159 similar to what the vax assembler does. */
252b5132
RH		 4160 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4161 a copy of it at runtime, adding in the information we want but isn't
4162 there. I think it'd be better to have an awk script hack the table
4163 at compile time. Or even just xstr the table and use it as-is. But
4164 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4165 names. */
4166
252b5132
RH		 4167 if (flag_mri)
4168 {
4169 flag_reg_prefix_optional = 1;
4170 m68k_abspcadd = 1;
4171 if (! m68k_rel32_from_cmdline)
4172 m68k_rel32 = 0;
4173 }
4174
60fed2d3
NC		 4175 /* First sort the opcode table into alphabetical order to seperate
4176 the order that the assembler wants to see the opcodes from the
4177 order that the disassembler wants to see them. */
4178 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4179 if (!m68k_sorted_opcodes)
4180 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4181 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4182
4183 for (i = m68k_numopcodes; i--;)
4184 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4185
4186 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4187 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4188
252b5132
RH		 4189 op_hash = hash_new ();
4190
4191 obstack_begin (&robyn, 4000);
4192 for (i = 0; i < m68k_numopcodes; i++)
4193 {
4194 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4195 do
4196 {
60fed2d3
NC		 4197 ins = m68k_sorted_opcodes[i];
4198
4199 /* We *could* ignore insns that don't match our
4200 arch here by just leaving them out of the hash. */
252b5132
RH		 4201 slak->m_operands = ins->args;
4202 slak->m_opnum = strlen (slak->m_operands) / 2;
4203 slak->m_arch = ins->arch;
4204 slak->m_opcode = ins->opcode;
36759679 4205 /* This is kludgey. */
252b5132
RH		 4206 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4207 if (i + 1 != m68k_numopcodes
60fed2d3 4208 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4209 {
60fed2d3 4210 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4211 i++;
4212 }
4213 else
4214 slak->m_next = 0;
4215 slak = slak->m_next;
4216 }
4217 while (slak);
4218
4219 retval = hash_insert (op_hash, ins->name, (char *) hack);
4220 if (retval)
4221 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4222 }
4223
4224 for (i = 0; i < m68k_numaliases; i++)
4225 {
4226 const char *name = m68k_opcode_aliases[i].primary;
4227 const char *alias = m68k_opcode_aliases[i].alias;
4228 PTR val = hash_find (op_hash, name);
60fed2d3 4229
252b5132
RH		 4230 if (!val)
4231 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4232 retval = hash_insert (op_hash, alias, val);
4233 if (retval)
4234 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4235 }
4236
4237 /* In MRI mode, all unsized branches are variable sized. Normally,
4238 they are word sized. */
4239 if (flag_mri)
4240 {
4241 static struct m68k_opcode_alias mri_aliases[] =
4242 {
4243 { "bhi", "jhi", },
4244 { "bls", "jls", },
4245 { "bcc", "jcc", },
4246 { "bcs", "jcs", },
4247 { "bne", "jne", },
4248 { "beq", "jeq", },
4249 { "bvc", "jvc", },
4250 { "bvs", "jvs", },
4251 { "bpl", "jpl", },
4252 { "bmi", "jmi", },
4253 { "bge", "jge", },
4254 { "blt", "jlt", },
4255 { "bgt", "jgt", },
4256 { "ble", "jle", },
4257 { "bra", "jra", },
4258 { "bsr", "jbsr", },
4259 };
4260
8fce3f5e
AM		 4261 for (i = 0;
4262 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4263 i++)
252b5132
RH		 4264 {
4265 const char *name = mri_aliases[i].primary;
4266 const char *alias = mri_aliases[i].alias;
4267 PTR val = hash_find (op_hash, name);
60fed2d3 4268
252b5132
RH		 4269 if (!val)
4270 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4271 retval = hash_jam (op_hash, alias, val);
4272 if (retval)
4273 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4274 }
4275 }
4276
8fce3f5e 4277 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4278 {
4279 notend_table[i] = 0;
4280 alt_notend_table[i] = 0;
4281 }
60fed2d3 4282
252b5132
RH		 4283 notend_table[','] = 1;
4284 notend_table['{'] = 1;
4285 notend_table['}'] = 1;
4286 alt_notend_table['a'] = 1;
4287 alt_notend_table['A'] = 1;
4288 alt_notend_table['d'] = 1;
4289 alt_notend_table['D'] = 1;
4290 alt_notend_table['#'] = 1;
4291 alt_notend_table['&'] = 1;
4292 alt_notend_table['f'] = 1;
4293 alt_notend_table['F'] = 1;
4294#ifdef REGISTER_PREFIX
4295 alt_notend_table[REGISTER_PREFIX] = 1;
4296#endif
4297
4298 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4299 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4300 alt_notend_table['('] = 1;
4301
4302 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4303 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4304 alt_notend_table['@'] = 1;
4305
4306 /* We need to put digits in alt_notend_table to handle
60fed2d3 4307 bfextu %d0{24:1},%d0 */
252b5132
RH		 4308 alt_notend_table['0'] = 1;
4309 alt_notend_table['1'] = 1;
4310 alt_notend_table['2'] = 1;
4311 alt_notend_table['3'] = 1;
4312 alt_notend_table['4'] = 1;
4313 alt_notend_table['5'] = 1;
4314 alt_notend_table['6'] = 1;
4315 alt_notend_table['7'] = 1;
4316 alt_notend_table['8'] = 1;
4317 alt_notend_table['9'] = 1;
4318
4319#ifndef MIT_SYNTAX_ONLY
4320 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4321 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4322 {
4323 int n = 0;
60fed2d3 4324
252b5132
RH		 4325 while (mote_pseudo_table[n].poc_name)
4326 {
60fed2d3 4327 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4328 hash_insert (op_hash,
4329 mote_pseudo_table[n].poc_name, (char *) hack);
4330 hack->m_operands = 0;
4331 hack->m_opnum = n;
4332 n++;
4333 }
4334 }
4335#endif
4336
4337 init_regtable ();
4338
4339#ifdef OBJ_ELF
4340 record_alignment (text_section, 2);
4341 record_alignment (data_section, 2);
4342 record_alignment (bss_section, 2);
4343#endif
4344}
4345
4346static void
31302357 4347select_control_regs (void)
252b5132
RH		 4348{
4349 /* Note which set of "movec" control registers is available. */
6b6e92f4 4350 switch (current_chip)
252b5132 4351 {
4f2a7c9e 4352 case 0:
6b6e92f4
NC		 4353 if (verbose)
4354 as_warn (_("architecture not yet selected: defaulting to 68020"));
4f2a7c9e
NC		 4355 control_regs = m68020_control_regs;
4356 break;
4357
252b5132
RH		 4358 case m68000:
4359 control_regs = m68000_control_regs;
4360 break;
4361 case m68010:
4362 control_regs = m68010_control_regs;
4363 break;
4364 case m68020:
4365 case m68030:
4366 control_regs = m68020_control_regs;
4367 break;
4368 case m68040:
4369 control_regs = m68040_control_regs;
4370 break;
4371 case m68060:
4372 control_regs = m68060_control_regs;
4373 break;
4374 case cpu32:
4375 control_regs = cpu32_control_regs;
4376 break;
4377 case mcf5200:
6da466c7
ILT		 4378 case mcf5206e:
4379 case mcf5307:
dc84e067 4380 case mcf5407:
6da466c7 4381 control_regs = mcf_control_regs;
252b5132 4382 break;
e80e0390
NC		 4383 case mcf5249:
4384 control_regs = mcf5249_control_regs;
4385 break;
3e602632 4386 case mcf528x:
6b6e92f4 4387 case mcf521x:
3e602632
NC		 4388 control_regs = mcf528x_control_regs;
4389 break;
6b6e92f4
NC		 4390 case mcf5470:
4391 case mcf5480:
3e602632
NC		 4392 control_regs = mcfv4e_control_regs;
4393 break;
252b5132
RH		 4394 default:
4395 abort ();
4396 }
4397}
4398
4399void
31302357 4400m68k_init_after_args (void)
252b5132
RH		 4401{
4402 if (cpu_of_arch (current_architecture) == 0)
4403 {
4404 int i;
4405 const char *default_cpu = TARGET_CPU;
4406
4407 if (*default_cpu == 'm')
4408 default_cpu++;
4409 for (i = 0; i < n_archs; i++)
4410 if (strcasecmp (default_cpu, archs[i].name) == 0)
4411 break;
4412 if (i == n_archs)
4413 {
4414 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4415 current_architecture |= m68020;
4416 }
4417 else
4418 current_architecture |= archs[i].arch;
4419 }
4420 /* Permit m68881 specification with all cpus; those that can't work
4421 with a coprocessor could be doing emulation. */
4422 if (current_architecture & m68851)
4423 {
4424 if (current_architecture & m68040)
60fed2d3 4425 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
252b5132
RH		 4426 }
4427 /* What other incompatibilities could we check for? */
4428
4429 /* Toss in some default assumptions about coprocessors. */
4430 if (!no_68881
4431 && (cpu_of_arch (current_architecture)
4432 /* Can CPU32 have a 68881 coprocessor?? */
4433 & (m68020 | m68030 | cpu32)))
60fed2d3
NC		 4434 current_architecture |= m68881;
4435
252b5132
RH		 4436 if (!no_68851
4437 && (cpu_of_arch (current_architecture) & m68020up) != 0
4438 && (cpu_of_arch (current_architecture) & m68040up) == 0)
60fed2d3
NC		 4439 current_architecture |= m68851;
4440
252b5132
RH		 4441 if (no_68881 && (current_architecture & m68881))
4442 as_bad (_("options for 68881 and no-68881 both given"));
60fed2d3 4443
252b5132
RH		 4444 if (no_68851 && (current_architecture & m68851))
4445 as_bad (_("options for 68851 and no-68851 both given"));
4446
4447#ifdef OBJ_AOUT
4448 /* Work out the magic number. This isn't very general. */
4449 if (current_architecture & m68000)
4450 m68k_aout_machtype = 0;
4451 else if (current_architecture & m68010)
4452 m68k_aout_machtype = 1;
4453 else if (current_architecture & m68020)
4454 m68k_aout_machtype = 2;
4455 else
4456 m68k_aout_machtype = 2;
4457#endif
4458
4459 /* Note which set of "movec" control registers is available. */
4460 select_control_regs ();
4461
4462 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4463 || arch_coldfire_p (current_architecture))
252b5132
RH		 4464 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4465}
4466\f
4467/* This is called when a label is defined. */
4468
4469void
31302357 4470m68k_frob_label (symbolS *sym)
252b5132
RH		 4471{
4472 struct label_line *n;
4473
4474 n = (struct label_line *) xmalloc (sizeof *n);
4475 n->next = labels;
4476 n->label = sym;
4477 as_where (&n->file, &n->line);
4478 n->text = 0;
4479 labels = n;
4480 current_label = n;
4481}
4482
4483/* This is called when a value that is not an instruction is emitted. */
4484
4485void
31302357 4486m68k_flush_pending_output (void)
252b5132
RH		 4487{
4488 current_label = NULL;
4489}
4490
4491/* This is called at the end of the assembly, when the final value of
4492 the label is known. We warn if this is a text symbol aligned at an
4493 odd location. */
4494
4495void
31302357 4496m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4497{
4498 if (S_GET_SEGMENT (sym) == reg_section
4499 && (int) S_GET_VALUE (sym) < 0)
4500 {
4501 S_SET_SEGMENT (sym, absolute_section);
4502 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4503 }
4504 else if ((S_GET_VALUE (sym) & 1) != 0)
4505 {
4506 struct label_line *l;
4507
4508 for (l = labels; l != NULL; l = l->next)
4509 {
4510 if (l->label == sym)
4511 {
4512 if (l->text)
4513 as_warn_where (l->file, l->line,
4514 _("text label `%s' aligned to odd boundary"),
4515 S_GET_NAME (sym));
4516 break;
4517 }
4518 }
4519 }
4520}
4521\f
4522/* This is called if we go in or out of MRI mode because of the .mri
4523 pseudo-op. */
4524
4525void
31302357 4526m68k_mri_mode_change (int on)
252b5132
RH		 4527{
4528 if (on)
4529 {
4530 if (! flag_reg_prefix_optional)
4531 {
4532 flag_reg_prefix_optional = 1;
4533#ifdef REGISTER_PREFIX
4534 init_regtable ();
4535#endif
4536 }
4537 m68k_abspcadd = 1;
4538 if (! m68k_rel32_from_cmdline)
4539 m68k_rel32 = 0;
4540 }
4541 else
4542 {
4543 if (! reg_prefix_optional_seen)
4544 {
4545#ifdef REGISTER_PREFIX_OPTIONAL
4546 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4547#else
4548 flag_reg_prefix_optional = 0;
4549#endif
4550#ifdef REGISTER_PREFIX
4551 init_regtable ();
4552#endif
4553 }
4554 m68k_abspcadd = 0;
4555 if (! m68k_rel32_from_cmdline)
4556 m68k_rel32 = 1;
4557 }
4558}
4559
36759679 4560/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4561#define MAX_LITTLENUMS 6
4562
4563/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4564 of type TYPE, and store the appropriate bytes in *LITP. The number
4565 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4566 returned, or NULL on OK. */
4567
4568char *
31302357 4569md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4570{
4571 int prec;
4572 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4573 LITTLENUM_TYPE *wordP;
4574 char *t;
4575
4576 switch (type)
4577 {
4578 case 'f':
4579 case 'F':
4580 case 's':
4581 case 'S':
4582 prec = 2;
4583 break;
4584
4585 case 'd':
4586 case 'D':
4587 case 'r':
4588 case 'R':
4589 prec = 4;
4590 break;
4591
4592 case 'x':
4593 case 'X':
4594 prec = 6;
4595 break;
4596
4597 case 'p':
4598 case 'P':
4599 prec = 6;
4600 break;
4601
4602 default:
4603 *sizeP = 0;
4604 return _("Bad call to MD_ATOF()");
4605 }
4606 t = atof_ieee (input_line_pointer, type, words);
4607 if (t)
4608 input_line_pointer = t;
4609
4610 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4611 for (wordP = words; prec--;)
4612 {
4613 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4614 litP += sizeof (LITTLENUM_TYPE);
4615 }
4616 return 0;
4617}
4618
4619void
31302357 4620md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4621{
4622 number_to_chars_bigendian (buf, val, n);
4623}
4624
94f592af 4625void
55cf6793 4626md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4627{
bbe8ef22 4628 offsetT val = *valP;
252b5132
RH		 4629 addressT upper_limit;
4630 offsetT lower_limit;
4631
4632 /* This is unnecessary but it convinces the native rs6000 compiler
4633 to generate the code we want. */
4634 char *buf = fixP->fx_frag->fr_literal;
4635 buf += fixP->fx_where;
36759679 4636 /* End ibm compiler workaround. */
252b5132 4637
bd17c2c3 4638 val = SEXT (val);
252b5132 4639
94f592af
NC		 4640 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4641 fixP->fx_done = 1;
4642
252b5132
RH		 4643#ifdef OBJ_ELF
4644 if (fixP->fx_addsy)
4645 {
4646 memset (buf, 0, fixP->fx_size);
36759679 4647 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4648
4649 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4650 && !S_IS_DEFINED (fixP->fx_addsy)
4651 && !S_IS_WEAK (fixP->fx_addsy))
4652 S_SET_WEAK (fixP->fx_addsy);
4653 return;
4654 }
4655#endif
4656
4657#ifdef BFD_ASSEMBLER
4658 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4659 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4660 return;
4661#endif
4662
4663 switch (fixP->fx_size)
4664 {
94f592af
NC		 4665 /* The cast to offsetT below are necessary to make code
4666 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4667 case 1:
4668 *buf++ = val;
4669 upper_limit = 0x7f;
4670 lower_limit = - (offsetT) 0x80;
4671 break;
4672 case 2:
4673 *buf++ = (val >> 8);
4674 *buf++ = val;
4675 upper_limit = 0x7fff;
4676 lower_limit = - (offsetT) 0x8000;
4677 break;
4678 case 4:
4679 *buf++ = (val >> 24);
4680 *buf++ = (val >> 16);
4681 *buf++ = (val >> 8);
4682 *buf++ = val;
4683 upper_limit = 0x7fffffff;
36759679 4684 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4685 break;
4686 default:
4687 BAD_CASE (fixP->fx_size);
4688 }
4689
4690 /* Fix up a negative reloc. */
4691 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4692 {
4693 fixP->fx_addsy = fixP->fx_subsy;
4694 fixP->fx_subsy = NULL;
4695 fixP->fx_tcbit = 1;
4696 }
4697
4698 /* For non-pc-relative values, it's conceivable we might get something
4699 like "0xff" for a byte field. So extend the upper part of the range
4700 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4701 so that we can do any range checking at all. */
4702 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4703 upper_limit = upper_limit * 2 + 1;
4704
4705 if ((addressT) val > upper_limit
4706 && (val > 0 || val < lower_limit))
4707 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4708
4709 /* A one byte PC-relative reloc means a short branch. We can't use
4710 a short branch with a value of 0 or -1, because those indicate
4711 different opcodes (branches with longer offsets). fixup_segment
4712 in write.c may have clobbered fx_pcrel, so we need to examine the
4713 reloc type. */
4714 if ((fixP->fx_pcrel
4715#ifdef BFD_ASSEMBLER
4716 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4717#endif
4718 )
4719 && fixP->fx_size == 1
4720 && (fixP->fx_addsy == NULL
4721 || S_IS_DEFINED (fixP->fx_addsy))
4722 && (val == 0 || val == -1))
4723 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4724}
4725
252b5132
RH		 4726/* *fragP has been relaxed to its final size, and now needs to have
4727 the bytes inside it modified to conform to the new size There is UGLY
4728 MAGIC here. ..
4729 */
4730static void
31302357 4731md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4732{
4733 long disp;
252b5132
RH		 4734 fixS *fixP;
4735
4736 /* Address in object code of the displacement. */
4737 register int object_address = fragP->fr_fix + fragP->fr_address;
4738
4739 /* Address in gas core of the place to store the displacement. */
4740 /* This convinces the native rs6000 compiler to generate the code we
92774660 4741 want. */
252b5132
RH		 4742 register char *buffer_address = fragP->fr_literal;
4743 buffer_address += fragP->fr_fix;
36759679 4744 /* End ibm compiler workaround. */
252b5132
RH		 4745
4746 /* The displacement of the address, from current location. */
4747 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4748 disp = (disp + fragP->fr_offset) - object_address;
4749
252b5132
RH		 4750 switch (fragP->fr_subtype)
4751 {
151337e8
NC		 4752 case TAB (BRANCHBWL, BYTE):
4753 case TAB (BRABSJUNC, BYTE):
4754 case TAB (BRABSJCOND, BYTE):
4755 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4756 know (issbyte (disp));
4757 if (disp == 0)
b091f402
AM		 4758 as_bad_where (fragP->fr_file, fragP->fr_line,
4759 _("short branch with zero offset: use :w"));
151337e8 4760 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4761 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4762 fixP->fx_pcrel_adjust = -1;
252b5132 4763 break;
151337e8
NC		 4764 case TAB (BRANCHBWL, SHORT):
4765 case TAB (BRABSJUNC, SHORT):
4766 case TAB (BRABSJCOND, SHORT):
4767 case TAB (BRANCHBW, SHORT):
252b5132 4768 fragP->fr_opcode[1] = 0x00;
151337e8 4769 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4770 1, RELAX_RELOC_PC16);
151337e8
NC		 4771 fragP->fr_fix += 2;
4772 break;
4773 case TAB (BRANCHBWL, LONG):
4774 fragP->fr_opcode[1] = (char) 0xFF;
4775 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4776 1, RELAX_RELOC_PC32);
151337e8 4777 fragP->fr_fix += 4;
252b5132 4778 break;
151337e8
NC		 4779 case TAB (BRABSJUNC, LONG):
4780 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4781 {
36759679 4782 if (flag_keep_pcrel)
6b6e92f4 4783 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4784 fragP->fr_opcode[0] = 0x4E;
36759679 4785 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4786 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4787 0, RELAX_RELOC_ABS32);
151337e8
NC		 4788 fragP->fr_fix += 4;
4789 }
4790 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4791 {
36759679 4792 if (flag_keep_pcrel)
6b6e92f4 4793 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4794 fragP->fr_opcode[0] = 0x4E;
36759679 4795 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4796 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4797 0, RELAX_RELOC_ABS32);
151337e8 4798 fragP->fr_fix += 4;
252b5132
RH		 4799 }
4800 else
4801 {
151337e8
NC		 4802 /* This cannot happen, because jbsr and jbra are the only two
4803 unconditional branches. */
4804 abort ();
252b5132
RH		 4805 }
4806 break;
151337e8 4807 case TAB (BRABSJCOND, LONG):
36759679 4808 if (flag_keep_pcrel)
6b6e92f4 4809 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4810
36759679
NC		 4811 /* Only Bcc 68000 instructions can come here
4812 Change bcc into b!cc/jmp absl long. */
4813 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4814 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4815
4816 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4817 different frag, in which case referring to them is a no-no.
92774660 4818 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4819 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4820 *buffer_address++ = (char) 0xf9;
36759679 4821 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4822 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4823 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4824 fragP->fr_fix += 4;
4825 break;
4826 case TAB (FBRANCH, SHORT):
4827 know ((fragP->fr_opcode[1] & 0x40) == 0);
4828 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4829 1, RELAX_RELOC_PC16);
151337e8
NC		 4830 fragP->fr_fix += 2;
4831 break;
4832 case TAB (FBRANCH, LONG):
36759679 4833 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4834 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4835 1, RELAX_RELOC_PC32);
252b5132 4836 fragP->fr_fix += 4;
252b5132 4837 break;
151337e8
NC		 4838 case TAB (DBCCLBR, SHORT):
4839 case TAB (DBCCABSJ, SHORT):
4840 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4841 1, RELAX_RELOC_PC16);
151337e8
NC		 4842 fragP->fr_fix += 2;
4843 break;
4844 case TAB (DBCCLBR, LONG):
36759679
NC		 4845 /* Only DBcc instructions can come here.
4846 Change dbcc into dbcc/bral.
4847 JF: these used to be fr_opcode[2-7], but that's wrong. */
4848 if (flag_keep_pcrel)
6b6e92f4 4849 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4850
36759679 4851 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4852 *buffer_address++ = 0x04;
36759679 4853 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4854 *buffer_address++ = 0x06;
151337e8
NC		 4855 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4856 *buffer_address++ = (char) 0xff;
252b5132 4857
36759679 4858 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4859 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4860 RELAX_RELOC_PC32);
252b5132 4861 fragP->fr_fix += 4;
252b5132 4862 break;
151337e8 4863 case TAB (DBCCABSJ, LONG):
36759679
NC		 4864 /* Only DBcc instructions can come here.
4865 Change dbcc into dbcc/jmp.
4866 JF: these used to be fr_opcode[2-7], but that's wrong. */
4867 if (flag_keep_pcrel)
6b6e92f4 4868 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4869
36759679 4870 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4871 *buffer_address++ = 0x04;
36759679 4872 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4873 *buffer_address++ = 0x06;
36759679 4874 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4875 *buffer_address++ = (char) 0xf9;
4876
36759679 4877 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4878 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4879 RELAX_RELOC_ABS32);
252b5132 4880 fragP->fr_fix += 4;
252b5132 4881 break;
151337e8 4882 case TAB (PCREL1632, SHORT):
252b5132
RH		 4883 fragP->fr_opcode[1] &= ~0x3F;
4884 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4885 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4886 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4887 fragP->fr_fix += 2;
252b5132 4888 break;
151337e8 4889 case TAB (PCREL1632, LONG):
252b5132
RH		 4890 /* Already set to mode 7.3; this indicates: PC indirect with
4891 suppressed index, 32-bit displacement. */
4892 *buffer_address++ = 0x01;
4893 *buffer_address++ = 0x70;
4894 fragP->fr_fix += 2;
151337e8 4895 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4896 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4897 fixP->fx_pcrel_adjust = 2;
4898 fragP->fr_fix += 4;
252b5132 4899 break;
252b5132 4900 case TAB (PCINDEX, BYTE):
252b5132
RH		 4901 assert (fragP->fr_fix >= 2);
4902 buffer_address[-2] &= ~1;
151337e8 4903 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4904 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4905 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4906 break;
4907 case TAB (PCINDEX, SHORT):
252b5132
RH		 4908 assert (fragP->fr_fix >= 2);
4909 buffer_address[-2] |= 0x1;
4910 buffer_address[-1] = 0x20;
4911 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4912 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4913 fixP->fx_pcrel_adjust = 2;
151337e8 4914 fragP->fr_fix += 2;
252b5132
RH		 4915 break;
4916 case TAB (PCINDEX, LONG):
252b5132
RH		 4917 assert (fragP->fr_fix >= 2);
4918 buffer_address[-2] |= 0x1;
4919 buffer_address[-1] = 0x30;
151337e8 4920 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4921 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4922 fixP->fx_pcrel_adjust = 2;
4923 fragP->fr_fix += 4;
4924 break;
4925 case TAB (ABSTOPCREL, SHORT):
4926 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4927 1, RELAX_RELOC_PC16);
151337e8
NC		 4928 fragP->fr_fix += 2;
4929 break;
4930 case TAB (ABSTOPCREL, LONG):
36759679 4931 if (flag_keep_pcrel)
6b6e92f4 4932 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4933 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4934 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4935 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4936 abort ();
4937 fragP->fr_opcode[1] &= ~0x3F;
4938 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4939 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4940 0, RELAX_RELOC_ABS32);
151337e8 4941 fragP->fr_fix += 4;
252b5132 4942 break;
252b5132
RH		 4943 }
4944}
4945
4946#ifndef BFD_ASSEMBLER
4947
4948void
31302357
AS		 4949md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED,
4950 segT sec ATTRIBUTE_UNUSED,
4951 fragS *fragP)
252b5132
RH		 4952{
4953 md_convert_frag_1 (fragP);
4954}
4955
4956#else
4957
4958void
31302357
AS		 4959md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4960 segT sec ATTRIBUTE_UNUSED,
4961 fragS *fragP)
252b5132
RH		 4962{
4963 md_convert_frag_1 (fragP);
4964}
4965#endif
4966
4967/* Force truly undefined symbols to their maximum size, and generally set up
4968 the frag list to be relaxed
4969 */
4970int
31302357 4971md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4972{
151337e8 4973 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4974 switch (fragP->fr_subtype)
4975 {
151337e8
NC		 4976 case TAB (BRANCHBWL, SZ_UNDEF):
4977 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4978 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4979 {
151337e8
NC		 4980 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4981 && relaxable_symbol (fragP->fr_symbol))
252b5132 4982 {
151337e8
NC		 4983 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4984 }
4985 else if (flag_short_refs)
4986 {
4987 /* Symbol is undefined and we want short ref. */
4988 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4989 }
4990 else
4991 {
151337e8
NC		 4992 /* Symbol is still undefined. Make it LONG. */
4993 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4994 }
4995 break;
151337e8 4996 }
252b5132 4997
151337e8 4998 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4999 {
151337e8
NC		 5000 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5001 && relaxable_symbol (fragP->fr_symbol))
252b5132 5002 {
151337e8 5003 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5004 }
5005 else
5006 {
151337e8
NC		 5007 /* Symbol is undefined and we don't have long branches. */
5008 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5009 }
5010 break;
151337e8 5011 }
252b5132 5012
151337e8 5013 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5014 case TAB (DBCCLBR, SZ_UNDEF):
5015 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5016 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5017 {
8ec6253e
NC		 5018 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5019 && relaxable_symbol (fragP->fr_symbol))
151337e8 5020 || flag_short_refs)
252b5132 5021 {
151337e8 5022 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5023 }
5024 else
5025 {
151337e8 5026 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5027 }
5028 break;
151337e8 5029 }
81d4177b 5030
252b5132
RH		 5031 case TAB (PCINDEX, SZ_UNDEF):
5032 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5033 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5034 {
5035 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5036 }
5037 else
5038 {
5039 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5040 }
5041 break;
5042
151337e8
NC		 5043 case TAB (ABSTOPCREL, SZ_UNDEF):
5044 {
5045 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5046 && relaxable_symbol (fragP->fr_symbol)))
5047 {
5048 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5049 }
5050 else
5051 {
5052 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5053 }
5054 break;
5055 }
5056
252b5132
RH		 5057 default:
5058 break;
5059 }
5060
151337e8 5061 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5062 switch (fragP->fr_subtype)
5063 {
151337e8
NC		 5064 case TAB (BRANCHBWL, BYTE):
5065 case TAB (BRABSJUNC, BYTE):
5066 case TAB (BRABSJCOND, BYTE):
5067 case TAB (BRANCHBW, BYTE):
252b5132 5068 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5069 case we force word mode. If the symbol is at the start of a
5070 frag, and it is the next frag with any data in it (usually
5071 this is just the next frag, but assembler listings may
5072 introduce empty frags), we must use word mode. */
5073 if (fragP->fr_symbol)
252b5132 5074 {
ac62c346 5075 fragS *sym_frag;
252b5132 5076
ac62c346
AM		 5077 sym_frag = symbol_get_frag (fragP->fr_symbol);
5078 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5079 {
ac62c346
AM		 5080 fragS *l;
5081
23b7f870 5082 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5083 if (l->fr_fix != 0)
5084 break;
5085 if (l == sym_frag)
5086 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5087 }
5088 }
5089 break;
5090 default:
5091 break;
5092 }
ac62c346 5093 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5094}
5095
5096#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5097/* the bit-field entries in the relocation_info struct plays hell
5098 with the byte-order problems of cross-assembly. So as a hack,
5099 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5100 you there. -KWK */
252b5132
RH		 5101/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5102 are symbolnum, most sig. byte first. Last byte is broken up with
5103 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5104 nibble as nuthin. (on Sun 3 at least) */
5105/* Translate the internal relocation information into target-specific
92774660 5106 format. */
252b5132
RH		 5107#ifdef comment
5108void
31302357 5109md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5110{
36759679 5111 /* This is easy. */
252b5132 5112 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5113 /* Now the fun stuff. */
252b5132 5114 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5115 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5116 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5117 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5118 | ((ri->r_length << 5) & 0x60)
5119 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5120}
5121
36759679 5122#endif
252b5132
RH		 5123
5124#ifndef BFD_ASSEMBLER
5125void
31302357
AS		 5126tc_aout_fix_to_chars (char *where, fixS *fixP,
5127 relax_addressT segment_address_in_file)
252b5132
RH		 5128{
5129 /*
5130 * In: length of relocation (or of address) in chars: 1, 2 or 4.
5131 * Out: GNU LD relocation length code: 0, 1, or 2.
5132 */
5133
5a38dc70 5134 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
252b5132
RH		 5135 long r_symbolnum;
5136
5137 know (fixP->fx_addsy != NULL);
5138
5139 md_number_to_chars (where,
31302357
AS		 5140 (fixP->fx_frag->fr_address
5141 + fixP->fx_where - segment_address_in_file), 4);
252b5132
RH		 5142
5143 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5144 ? S_GET_TYPE (fixP->fx_addsy)
5145 : fixP->fx_addsy->sy_number);
5146
5147 where[4] = (r_symbolnum >> 16) & 0x0ff;
5148 where[5] = (r_symbolnum >> 8) & 0x0ff;
5149 where[6] = r_symbolnum & 0x0ff;
31302357
AS		 5150 where[7] = (((fixP->fx_pcrel << 7) & 0x80)
5151 | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60)
5152 | ((!S_IS_DEFINED (fixP->fx_addsy) << 4) & 0x10));
252b5132
RH		 5153}
5154#endif
5155
5156#endif /* OBJ_AOUT or OBJ_BOUT */
5157
5158#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5159int md_short_jump_size = 4;
5160int md_long_jump_size = 6;
252b5132
RH		 5161
5162void
31302357
AS		 5163md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5164 fragS *frag ATTRIBUTE_UNUSED,
5165 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5166{
5167 valueT offset;
5168
5169 offset = to_addr - (from_addr + 2);
5170
5171 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5172 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5173}
5174
5175void
31302357
AS		 5176md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5177 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5178{
5179 valueT offset;
5180
6b6e92f4 5181 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5182 {
36759679 5183 if (flag_keep_pcrel)
6b6e92f4 5184 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5185 offset = to_addr - S_GET_VALUE (to_symbol);
5186 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5187 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5188 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5189 0, NO_RELOC);
5190 }
5191 else
5192 {
5193 offset = to_addr - (from_addr + 2);
5194 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5195 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5196 }
5197}
5198
5199#endif
5200
5201/* Different values of OK tell what its OK to return. Things that
5202 aren't OK are an error (what a shock, no?)
5203
5204 0: Everything is OK
3e602632
NC		 5205 10: Absolute 1:8 only
5206 20: Absolute 0:7 only
5207 30: absolute 0:15 only
5208 40: Absolute 0:31 only
5209 50: absolute 0:127 only
252b5132 5210 55: absolute -64:63 only
3e602632
NC		 5211 60: absolute -128:127 only
5212 70: absolute 0:4095 only
5213 80: absolute -1, 1:7 only
5214 90: No bignums. */
252b5132
RH		 5215
5216static int
31302357 5217get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5218{
5219 if (exp->exp.X_op == O_absent)
5220 {
36759679 5221 /* Do the same thing the VAX asm does. */
252b5132
RH		 5222 op (exp) = O_constant;
5223 adds (exp) = 0;
5224 subs (exp) = 0;
5225 offs (exp) = 0;
5226 if (ok == 10)
5227 {
5228 as_warn (_("expression out of range: defaulting to 1"));
5229 offs (exp) = 1;
5230 }
5231 }
5232 else if (exp->exp.X_op == O_constant)
5233 {
5234 switch (ok)
5235 {
5236 case 10:
bd17c2c3 5237 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5238 {
5239 as_warn (_("expression out of range: defaulting to 1"));
5240 offs (exp) = 1;
5241 }
5242 break;
5243 case 20:
bd17c2c3 5244 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5245 goto outrange;
5246 break;
5247 case 30:
bd17c2c3 5248 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5249 goto outrange;
5250 break;
5251 case 40:
bd17c2c3 5252 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5253 goto outrange;
5254 break;
5255 case 50:
bd17c2c3 5256 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5257 goto outrange;
5258 break;
5259 case 55:
bd17c2c3 5260 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5261 goto outrange;
5262 break;
5263 case 60:
bd17c2c3 5264 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5265 goto outrange;
5266 break;
5267 case 70:
bd17c2c3 5268 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5269 {
5270 outrange:
5271 as_warn (_("expression out of range: defaulting to 0"));
5272 offs (exp) = 0;
5273 }
5274 break;
3e602632 5275 case 80:
bd17c2c3
AM		 5276 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5277 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5278 {
5279 as_warn (_("expression out of range: defaulting to 1"));
5280 offs (exp) = 1;
5281 }
5282 break;
252b5132
RH		 5283 default:
5284 break;
5285 }
5286 }
5287 else if (exp->exp.X_op == O_big)
5288 {
36759679 5289 if (offs (exp) <= 0 /* flonum. */
3e602632 5290 && (ok == 90 /* no bignums */
36759679 5291 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5292 /* If we have a flonum zero, a zero integer should
5293 do as well (e.g., in moveq). */
5294 && generic_floating_point_number.exponent == 0
5295 && generic_floating_point_number.low[0] == 0)))
5296 {
36759679 5297 /* HACK! Turn it into a long. */
252b5132
RH		 5298 LITTLENUM_TYPE words[6];
5299
36759679 5300 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5301 op (exp) = O_constant;
5302 adds (exp) = 0;
5303 subs (exp) = 0;
5304 offs (exp) = words[1] | (words[0] << 16);
5305 }
5306 else if (ok != 0)
5307 {
5308 op (exp) = O_constant;
5309 adds (exp) = 0;
5310 subs (exp) = 0;
5311 offs (exp) = (ok == 10) ? 1 : 0;
5312 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5313 (long) offs (exp));
252b5132
RH		 5314 }
5315 }
5316 else
5317 {
3e602632 5318 if (ok >= 10 && ok <= 80)
252b5132
RH		 5319 {
5320 op (exp) = O_constant;
5321 adds (exp) = 0;
5322 subs (exp) = 0;
5323 offs (exp) = (ok == 10) ? 1 : 0;
5324 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5325 (long) offs (exp));
252b5132
RH		 5326 }
5327 }
5328
5329 if (exp->size != SIZE_UNSPEC)
5330 {
5331 switch (exp->size)
5332 {
5333 case SIZE_UNSPEC:
5334 case SIZE_LONG:
5335 break;
5336 case SIZE_BYTE:
5337 if (!isbyte (offs (exp)))
5338 as_warn (_("expression doesn't fit in BYTE"));
5339 break;
5340 case SIZE_WORD:
5341 if (!isword (offs (exp)))
5342 as_warn (_("expression doesn't fit in WORD"));
5343 break;
5344 }
5345 }
5346
5347 return offs (exp);
5348}
5349
5350/* These are the back-ends for the various machine dependent pseudo-ops. */
5351
5352static void
31302357 5353s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5354{
5355 subseg_set (data_section, 1);
5356 demand_empty_rest_of_line ();
5357}
5358
5359static void
31302357 5360s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5361{
5362 subseg_set (data_section, 2);
5363 demand_empty_rest_of_line ();
5364}
5365
5366static void
31302357 5367s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5368{
5369 /* We don't support putting frags in the BSS segment, we fake it
5370 by marking in_bss, then looking at s_skip for clues. */
5371
5372 subseg_set (bss_section, 0);
5373 demand_empty_rest_of_line ();
5374}
5375
5376static void
31302357 5377s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5378{
5379 register int temp;
5380 register long temp_fill;
5381
5382 temp = 1; /* JF should be 2? */
5383 temp_fill = get_absolute_expression ();
92774660 5384 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5385 frag_align (temp, (int) temp_fill, 0);
5386 demand_empty_rest_of_line ();
5387 record_alignment (now_seg, temp);
5388}
5389
5390static void
31302357 5391s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5392{
5393 demand_empty_rest_of_line ();
5394}
5395\f
5396/* Pseudo-ops handled for MRI compatibility. */
5397
5398/* This function returns non-zero if the argument is a conditional
5399 pseudo-op. This is called when checking whether a pending
5400 alignment is needed. */
5401
5402int
31302357 5403m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5404{
5405 return (pop->poc_handler == s_mri_if
5406 || pop->poc_handler == s_mri_else);
5407}
5408
5409/* Handle an MRI style chip specification. */
5410
5411static void
31302357 5412mri_chip (void)
252b5132
RH		 5413{
5414 char *s;
5415 char c;
5416 int i;
5417
5418 s = input_line_pointer;
5419 /* We can't use get_symbol_end since the processor names are not proper
5420 symbols. */
5421 while (is_part_of_name (c = *input_line_pointer++))
5422 ;
5423 *--input_line_pointer = 0;
5424 for (i = 0; i < n_archs; i++)
5425 if (strcasecmp (s, archs[i].name) == 0)
5426 break;
5427 if (i >= n_archs)
5428 {
5429 as_bad (_("%s: unrecognized processor name"), s);
5430 *input_line_pointer = c;
5431 ignore_rest_of_line ();
5432 return;
5433 }
5434 *input_line_pointer = c;
5435
5436 if (*input_line_pointer == '/')
5437 current_architecture = 0;
5438 else
5439 current_architecture &= m68881 | m68851;
5440 current_architecture |= archs[i].arch;
990ae22a 5441 current_chip = archs[i].chip;
252b5132
RH		 5442
5443 while (*input_line_pointer == '/')
5444 {
5445 ++input_line_pointer;
5446 s = input_line_pointer;
5447 /* We can't use get_symbol_end since the processor names are not
5448 proper symbols. */
5449 while (is_part_of_name (c = *input_line_pointer++))
5450 ;
5451 *--input_line_pointer = 0;
5452 if (strcmp (s, "68881") == 0)
5453 current_architecture |= m68881;
5454 else if (strcmp (s, "68851") == 0)
5455 current_architecture |= m68851;
5456 *input_line_pointer = c;
5457 }
5458
5459 /* Update info about available control registers. */
5460 select_control_regs ();
5461}
5462
5463/* The MRI CHIP pseudo-op. */
5464
5465static void
31302357 5466s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5467{
5468 char *stop = NULL;
5469 char stopc;
5470
5471 if (flag_mri)
5472 stop = mri_comment_field (&stopc);
5473 mri_chip ();
5474 if (flag_mri)
5475 mri_comment_end (stop, stopc);
5476 demand_empty_rest_of_line ();
5477}
5478
5479/* The MRI FOPT pseudo-op. */
5480
5481static void
31302357 5482s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5483{
5484 SKIP_WHITESPACE ();
5485
5486 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5487 {
5488 int temp;
5489
5490 input_line_pointer += 3;
5491 temp = get_absolute_expression ();
5492 if (temp < 0 || temp > 7)
5493 as_bad (_("bad coprocessor id"));
5494 else
5495 m68k_float_copnum = COP0 + temp;
5496 }
5497 else
5498 {
5499 as_bad (_("unrecognized fopt option"));
5500 ignore_rest_of_line ();
5501 return;
5502 }
5503
5504 demand_empty_rest_of_line ();
5505}
5506
5507/* The structure used to handle the MRI OPT pseudo-op. */
5508
5509struct opt_action
5510{
5511 /* The name of the option. */
5512 const char *name;
5513
5514 /* If this is not NULL, just call this function. The first argument
5515 is the ARG field of this structure, the second argument is
5516 whether the option was negated. */
31302357 5517 void (*pfn) (int arg, int on);
252b5132
RH		 5518
5519 /* If this is not NULL, and the PFN field is NULL, set the variable
5520 this points to. Set it to the ARG field if the option was not
5521 negated, and the NOTARG field otherwise. */
5522 int *pvar;
5523
5524 /* The value to pass to PFN or to assign to *PVAR. */
5525 int arg;
5526
5527 /* The value to assign to *PVAR if the option is negated. If PFN is
5528 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5529 the option may not be negated. */
5530 int notarg;
5531};
5532
5533/* The table used to handle the MRI OPT pseudo-op. */
5534
31302357
AS		 5535static void skip_to_comma (int, int);
5536static void opt_nest (int, int);
5537static void opt_chip (int, int);
5538static void opt_list (int, int);
5539static void opt_list_symbols (int, int);
252b5132
RH		 5540
5541static const struct opt_action opt_table[] =
5542{
5543 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5544
5545 /* We do relaxing, so there is little use for these options. */
5546 { "b", 0, 0, 0, 0 },
5547 { "brs", 0, 0, 0, 0 },
5548 { "brb", 0, 0, 0, 0 },
5549 { "brl", 0, 0, 0, 0 },
5550 { "brw", 0, 0, 0, 0 },
5551
5552 { "c", 0, 0, 0, 0 },
5553 { "cex", 0, 0, 0, 0 },
5554 { "case", 0, &symbols_case_sensitive, 1, 0 },
5555 { "cl", 0, 0, 0, 0 },
5556 { "cre", 0, 0, 0, 0 },
5557 { "d", 0, &flag_keep_locals, 1, 0 },
5558 { "e", 0, 0, 0, 0 },
5559 { "f", 0, &flag_short_refs, 1, 0 },
5560 { "frs", 0, &flag_short_refs, 1, 0 },
5561 { "frl", 0, &flag_short_refs, 0, 1 },
5562 { "g", 0, 0, 0, 0 },
5563 { "i", 0, 0, 0, 0 },
5564 { "m", 0, 0, 0, 0 },
5565 { "mex", 0, 0, 0, 0 },
5566 { "mc", 0, 0, 0, 0 },
5567 { "md", 0, 0, 0, 0 },
5568 { "nest", opt_nest, 0, 0, 0 },
5569 { "next", skip_to_comma, 0, 0, 0 },
5570 { "o", 0, 0, 0, 0 },
5571 { "old", 0, 0, 0, 0 },
5572 { "op", skip_to_comma, 0, 0, 0 },
5573 { "pco", 0, 0, 0, 0 },
5574 { "p", opt_chip, 0, 0, 0 },
5575 { "pcr", 0, 0, 0, 0 },
5576 { "pcs", 0, 0, 0, 0 },
5577 { "r", 0, 0, 0, 0 },
5578 { "quick", 0, &m68k_quick, 1, 0 },
5579 { "rel32", 0, &m68k_rel32, 1, 0 },
5580 { "s", opt_list, 0, 0, 0 },
5581 { "t", opt_list_symbols, 0, 0, 0 },
5582 { "w", 0, &flag_no_warnings, 0, 1 },
5583 { "x", 0, 0, 0, 0 }
5584};
5585
8fce3f5e 5586#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5587
5588/* The MRI OPT pseudo-op. */
5589
5590static void
31302357 5591s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5592{
5593 do
5594 {
5595 int t;
5596 char *s;
5597 char c;
5598 int i;
5599 const struct opt_action *o;
5600
5601 SKIP_WHITESPACE ();
5602
5603 t = 1;
5604 if (*input_line_pointer == '-')
5605 {
5606 ++input_line_pointer;
5607 t = 0;
5608 }
5609 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5610 {
5611 input_line_pointer += 2;
5612 t = 0;
5613 }
5614
5615 s = input_line_pointer;
5616 c = get_symbol_end ();
5617
5618 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5619 {
5620 if (strcasecmp (s, o->name) == 0)
5621 {
5622 if (o->pfn)
5623 {
5624 /* Restore input_line_pointer now in case the option
5625 takes arguments. */
5626 *input_line_pointer = c;
5627 (*o->pfn) (o->arg, t);
5628 }
5629 else if (o->pvar != NULL)
5630 {
5631 if (! t && o->arg == o->notarg)
5632 as_bad (_("option `%s' may not be negated"), s);
5633 *input_line_pointer = c;
5634 *o->pvar = t ? o->arg : o->notarg;
5635 }
5636 else
5637 *input_line_pointer = c;
5638 break;
5639 }
5640 }
5641 if (i >= OPTCOUNT)
5642 {
5643 as_bad (_("option `%s' not recognized"), s);
5644 *input_line_pointer = c;
5645 }
5646 }
5647 while (*input_line_pointer++ == ',');
5648
5649 /* Move back to terminating character. */
5650 --input_line_pointer;
5651 demand_empty_rest_of_line ();
5652}
5653
5654/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5655 not support and which take arguments. */
252b5132
RH		 5656
5657static void
31302357 5658skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5659{
5660 while (*input_line_pointer != ','
5661 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5662 ++input_line_pointer;
5663}
5664
5665/* Handle the OPT NEST=depth option. */
5666
5667static void
31302357 5668opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5669{
5670 if (*input_line_pointer != '=')
5671 {
5672 as_bad (_("bad format of OPT NEST=depth"));
5673 return;
5674 }
5675
5676 ++input_line_pointer;
5677 max_macro_nest = get_absolute_expression ();
5678}
5679
5680/* Handle the OPT P=chip option. */
5681
5682static void
31302357 5683opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5684{
5685 if (*input_line_pointer != '=')
5686 {
5687 /* This is just OPT P, which we do not support. */
5688 return;
5689 }
5690
5691 ++input_line_pointer;
5692 mri_chip ();
5693}
5694
5695/* Handle the OPT S option. */
5696
5697static void
31302357 5698opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5699{
5700 listing_list (on);
5701}
5702
5703/* Handle the OPT T option. */
5704
5705static void
31302357 5706opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5707{
5708 if (on)
5709 listing |= LISTING_SYMBOLS;
5710 else
8a104df9 5711 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5712}
5713
5714/* Handle the MRI REG pseudo-op. */
5715
5716static void
31302357 5717s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5718{
5719 char *s;
5720 int c;
5721 struct m68k_op rop;
5722 int mask;
5723 char *stop = NULL;
5724 char stopc;
5725
5726 if (line_label == NULL)
5727 {
5728 as_bad (_("missing label"));
5729 ignore_rest_of_line ();
5730 return;
5731 }
5732
5733 if (flag_mri)
5734 stop = mri_comment_field (&stopc);
5735
5736 SKIP_WHITESPACE ();
5737
5738 s = input_line_pointer;
3882b010 5739 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5740#ifdef REGISTER_PREFIX
5741 || *input_line_pointer == REGISTER_PREFIX
5742#endif
5743 || *input_line_pointer == '/'
5744 || *input_line_pointer == '-')
5745 ++input_line_pointer;
5746 c = *input_line_pointer;
5747 *input_line_pointer = '\0';
5748
5749 if (m68k_ip_op (s, &rop) != 0)
5750 {
5751 if (rop.error == NULL)
5752 as_bad (_("bad register list"));
5753 else
5754 as_bad (_("bad register list: %s"), rop.error);
5755 *input_line_pointer = c;
5756 ignore_rest_of_line ();
5757 return;
5758 }
5759
5760 *input_line_pointer = c;
5761
5762 if (rop.mode == REGLST)
5763 mask = rop.mask;
5764 else if (rop.mode == DREG)
5765 mask = 1 << (rop.reg - DATA0);
5766 else if (rop.mode == AREG)
5767 mask = 1 << (rop.reg - ADDR0 + 8);
5768 else if (rop.mode == FPREG)
5769 mask = 1 << (rop.reg - FP0 + 16);
5770 else if (rop.mode == CONTROL
5771 && rop.reg == FPI)
5772 mask = 1 << 24;
5773 else if (rop.mode == CONTROL
5774 && rop.reg == FPS)
5775 mask = 1 << 25;
5776 else if (rop.mode == CONTROL
5777 && rop.reg == FPC)
5778 mask = 1 << 26;
5779 else
5780 {
5781 as_bad (_("bad register list"));
5782 ignore_rest_of_line ();
5783 return;
5784 }
5785
5786 S_SET_SEGMENT (line_label, reg_section);
5787 S_SET_VALUE (line_label, ~mask);
49309057 5788 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5789
5790 if (flag_mri)
5791 mri_comment_end (stop, stopc);
5792
5793 demand_empty_rest_of_line ();
5794}
5795
5796/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5797
5798struct save_opts
5799{
5800 struct save_opts *next;
5801 int abspcadd;
5802 int symbols_case_sensitive;
5803 int keep_locals;
5804 int short_refs;
5805 int architecture;
6b6e92f4 5806 int chip;
252b5132
RH		 5807 int quick;
5808 int rel32;
5809 int listing;
5810 int no_warnings;
5811 /* FIXME: We don't save OPT S. */
5812};
5813
5814/* This variable holds the stack of saved options. */
5815
5816static struct save_opts *save_stack;
5817
5818/* The MRI SAVE pseudo-op. */
5819
5820static void
31302357 5821s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5822{
5823 struct save_opts *s;
5824
5825 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5826 s->abspcadd = m68k_abspcadd;
5827 s->symbols_case_sensitive = symbols_case_sensitive;
5828 s->keep_locals = flag_keep_locals;
5829 s->short_refs = flag_short_refs;
5830 s->architecture = current_architecture;
6b6e92f4 5831 s->chip = current_chip;
252b5132
RH		 5832 s->quick = m68k_quick;
5833 s->rel32 = m68k_rel32;
5834 s->listing = listing;
5835 s->no_warnings = flag_no_warnings;
5836
5837 s->next = save_stack;
5838 save_stack = s;
5839
5840 demand_empty_rest_of_line ();
5841}
5842
5843/* The MRI RESTORE pseudo-op. */
5844
5845static void
31302357 5846s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5847{
5848 struct save_opts *s;
5849
5850 if (save_stack == NULL)
5851 {
5852 as_bad (_("restore without save"));
5853 ignore_rest_of_line ();
5854 return;
5855 }
5856
5857 s = save_stack;
5858 save_stack = s->next;
5859
5860 m68k_abspcadd = s->abspcadd;
5861 symbols_case_sensitive = s->symbols_case_sensitive;
5862 flag_keep_locals = s->keep_locals;
5863 flag_short_refs = s->short_refs;
5864 current_architecture = s->architecture;
6b6e92f4 5865 current_chip = s->chip;
252b5132
RH		 5866 m68k_quick = s->quick;
5867 m68k_rel32 = s->rel32;
5868 listing = s->listing;
5869 flag_no_warnings = s->no_warnings;
5870
5871 free (s);
5872
5873 demand_empty_rest_of_line ();
5874}
5875
5876/* Types of MRI structured control directives. */
5877
5878enum mri_control_type
5879{
5880 mri_for,
5881 mri_if,
5882 mri_repeat,
5883 mri_while
5884};
5885
5886/* This structure is used to stack the MRI structured control
5887 directives. */
5888
5889struct mri_control_info
5890{
5891 /* The directive within which this one is enclosed. */
5892 struct mri_control_info *outer;
5893
5894 /* The type of directive. */
5895 enum mri_control_type type;
5896
5897 /* Whether an ELSE has been in an IF. */
5898 int else_seen;
5899
5900 /* The add or sub statement at the end of a FOR. */
5901 char *incr;
5902
5903 /* The label of the top of a FOR or REPEAT loop. */
5904 char *top;
5905
5906 /* The label to jump to for the next iteration, or the else
5907 expression of a conditional. */
5908 char *next;
5909
5910 /* The label to jump to to break out of the loop, or the label past
5911 the end of a conditional. */
5912 char *bottom;
5913};
5914
5915/* The stack of MRI structured control directives. */
5916
5917static struct mri_control_info *mri_control_stack;
5918
5919/* The current MRI structured control directive index number, used to
5920 generate label names. */
5921
5922static int mri_control_index;
5923
252b5132
RH		 5924/* Assemble an instruction for an MRI structured control directive. */
5925
5926static void
31302357 5927mri_assemble (char *str)
252b5132
RH		 5928{
5929 char *s;
5930
5931 /* md_assemble expects the opcode to be in lower case. */
5932 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5933 *s = TOLOWER (*s);
252b5132
RH		 5934
5935 md_assemble (str);
5936}
5937
5938/* Generate a new MRI label structured control directive label name. */
5939
5940static char *
31302357 5941mri_control_label (void)
252b5132
RH		 5942{
5943 char *n;
5944
5945 n = (char *) xmalloc (20);
5946 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5947 ++mri_control_index;
5948 return n;
5949}
5950
5951/* Create a new MRI structured control directive. */
5952
5953static struct mri_control_info *
31302357 5954push_mri_control (enum mri_control_type type)
252b5132
RH		 5955{
5956 struct mri_control_info *n;
5957
5958 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5959
5960 n->type = type;
5961 n->else_seen = 0;
5962 if (type == mri_if || type == mri_while)
5963 n->top = NULL;
5964 else
5965 n->top = mri_control_label ();
5966 n->next = mri_control_label ();
5967 n->bottom = mri_control_label ();
5968
5969 n->outer = mri_control_stack;
5970 mri_control_stack = n;
5971
5972 return n;
5973}
5974
5975/* Pop off the stack of MRI structured control directives. */
5976
5977static void
31302357 5978pop_mri_control (void)
252b5132
RH		 5979{
5980 struct mri_control_info *n;
5981
5982 n = mri_control_stack;
5983 mri_control_stack = n->outer;
5984 if (n->top != NULL)
5985 free (n->top);
5986 free (n->next);
5987 free (n->bottom);
5988 free (n);
5989}
5990
5991/* Recognize a condition code in an MRI structured control expression. */
5992
5993static int
31302357 5994parse_mri_condition (int *pcc)
252b5132
RH		 5995{
5996 char c1, c2;
5997
5998 know (*input_line_pointer == '<');
5999
6000 ++input_line_pointer;
6001 c1 = *input_line_pointer++;
6002 c2 = *input_line_pointer++;
6003
6004 if (*input_line_pointer != '>')
6005 {
6006 as_bad (_("syntax error in structured control directive"));
6007 return 0;
6008 }
6009
6010 ++input_line_pointer;
6011 SKIP_WHITESPACE ();
6012
3882b010
L		 6013 c1 = TOLOWER (c1);
6014 c2 = TOLOWER (c2);
252b5132
RH		 6015
6016 *pcc = (c1 << 8) | c2;
6017
6018 return 1;
6019}
6020
6021/* Parse a single operand in an MRI structured control expression. */
6022
6023static int
31302357
AS		 6024parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6025 char **rightstart, char **rightstop)
252b5132
RH		 6026{
6027 char *s;
6028
6029 SKIP_WHITESPACE ();
6030
6031 *pcc = -1;
6032 *leftstart = NULL;
6033 *leftstop = NULL;
6034 *rightstart = NULL;
6035 *rightstop = NULL;
6036
6037 if (*input_line_pointer == '<')
6038 {
6039 /* It's just a condition code. */
6040 return parse_mri_condition (pcc);
6041 }
6042
6043 /* Look ahead for the condition code. */
6044 for (s = input_line_pointer; *s != '\0'; ++s)
6045 {
6046 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6047 break;
6048 }
6049 if (*s == '\0')
6050 {
6051 as_bad (_("missing condition code in structured control directive"));
6052 return 0;
6053 }
6054
6055 *leftstart = input_line_pointer;
6056 *leftstop = s;
6057 if (*leftstop > *leftstart
6058 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6059 --*leftstop;
6060
6061 input_line_pointer = s;
6062 if (! parse_mri_condition (pcc))
6063 return 0;
6064
6065 /* Look ahead for AND or OR or end of line. */
6066 for (s = input_line_pointer; *s != '\0'; ++s)
6067 {
e1f44d10
NC		 6068 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6069 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6070 ^^^ ^^ */
8a104df9
KH		 6071 if ((s == input_line_pointer
6072 || *(s-1) == ' '
6073 || *(s-1) == '\t')
6074 && ((strncasecmp (s, "AND", 3) == 0
6075 && (s[3] == '.' || ! is_part_of_name (s[3])))
6076 || (strncasecmp (s, "OR", 2) == 0
6077 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6078 break;
252b5132
RH		 6079 }
6080
6081 *rightstart = input_line_pointer;
6082 *rightstop = s;
6083 if (*rightstop > *rightstart
6084 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6085 --*rightstop;
6086
6087 input_line_pointer = s;
6088
6089 return 1;
6090}
6091
6092#define MCC(b1, b2) (((b1) << 8) | (b2))
6093
6094/* Swap the sense of a condition. This changes the condition so that
6095 it generates the same result when the operands are swapped. */
6096
6097static int
31302357 6098swap_mri_condition (int cc)
252b5132
RH		 6099{
6100 switch (cc)
6101 {
6102 case MCC ('h', 'i'): return MCC ('c', 's');
6103 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6104 /* <HS> is an alias for <CC>. */
e1f44d10 6105 case MCC ('h', 's'):
252b5132 6106 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6107 /* <LO> is an alias for <CS>. */
e1f44d10 6108 case MCC ('l', 'o'):
252b5132
RH		 6109 case MCC ('c', 's'): return MCC ('h', 'i');
6110 case MCC ('p', 'l'): return MCC ('m', 'i');
6111 case MCC ('m', 'i'): return MCC ('p', 'l');
6112 case MCC ('g', 'e'): return MCC ('l', 'e');
6113 case MCC ('l', 't'): return MCC ('g', 't');
6114 case MCC ('g', 't'): return MCC ('l', 't');
6115 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6116 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6117 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6118 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6119 case MCC ('v', 'c'):
6120 case MCC ('v', 's'):
6121 default :
6122 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6123 (char) (cc >> 8), (char) (cc));
6124 break;
252b5132
RH		 6125 }
6126 return cc;
6127}
6128
6129/* Reverse the sense of a condition. */
6130
6131static int
31302357 6132reverse_mri_condition (int cc)
252b5132
RH		 6133{
6134 switch (cc)
6135 {
6136 case MCC ('h', 'i'): return MCC ('l', 's');
6137 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6138 /* <HS> is an alias for <CC> */
6139 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6140 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6141 /* <LO> is an alias for <CS> */
6142 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6143 case MCC ('c', 's'): return MCC ('c', 'c');
6144 case MCC ('n', 'e'): return MCC ('e', 'q');
6145 case MCC ('e', 'q'): return MCC ('n', 'e');
6146 case MCC ('v', 'c'): return MCC ('v', 's');
6147 case MCC ('v', 's'): return MCC ('v', 'c');
6148 case MCC ('p', 'l'): return MCC ('m', 'i');
6149 case MCC ('m', 'i'): return MCC ('p', 'l');
6150 case MCC ('g', 'e'): return MCC ('l', 't');
6151 case MCC ('l', 't'): return MCC ('g', 'e');
6152 case MCC ('g', 't'): return MCC ('l', 'e');
6153 case MCC ('l', 'e'): return MCC ('g', 't');
6154 }
6155 return cc;
6156}
6157
6158/* Build an MRI structured control expression. This generates test
6159 and branch instructions. It goes to TRUELAB if the condition is
6160 true, and to FALSELAB if the condition is false. Exactly one of
6161 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6162 is the size qualifier for the expression. EXTENT is the size to
6163 use for the branch. */
6164
6165static void
31302357
AS		 6166build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6167 char *rightstart, char *rightstop,
6168 const char *truelab, const char *falselab,
6169 int extent)
252b5132
RH		 6170{
6171 char *buf;
6172 char *s;
6173
6174 if (leftstart != NULL)
6175 {
6176 struct m68k_op leftop, rightop;
6177 char c;
6178
6179 /* Swap the compare operands, if necessary, to produce a legal
6180 m68k compare instruction. Comparing a register operand with
6181 a non-register operand requires the register to be on the
6182 right (cmp, cmpa). Comparing an immediate value with
6183 anything requires the immediate value to be on the left
6184 (cmpi). */
6185
6186 c = *leftstop;
6187 *leftstop = '\0';
6188 (void) m68k_ip_op (leftstart, &leftop);
6189 *leftstop = c;
6190
6191 c = *rightstop;
6192 *rightstop = '\0';
6193 (void) m68k_ip_op (rightstart, &rightop);
6194 *rightstop = c;
6195
6196 if (rightop.mode == IMMED
6197 || ((leftop.mode == DREG || leftop.mode == AREG)
6198 && (rightop.mode != DREG && rightop.mode != AREG)))
6199 {
6200 char *temp;
6201
31302357
AS		 6202 /* Correct conditional handling:
6203 if #1 <lt> d0 then ;means if (1 < d0)
6204 ...
6205 endi
e1f44d10 6206
31302357 6207 should assemble to:
e1f44d10 6208
31302357
AS		 6209 cmp #1,d0 if we do *not* swap the operands
6210 bgt true we need the swapped condition!
6211 ble false
6212 true:
6213 ...
6214 false:
6215 */
252b5132
RH		 6216 temp = leftstart;
6217 leftstart = rightstart;
6218 rightstart = temp;
6219 temp = leftstop;
6220 leftstop = rightstop;
6221 rightstop = temp;
8a104df9
KH		 6222 }
6223 else
6224 {
e1f44d10 6225 cc = swap_mri_condition (cc);
252b5132
RH		 6226 }
6227 }
6228
6229 if (truelab == NULL)
6230 {
6231 cc = reverse_mri_condition (cc);
6232 truelab = falselab;
6233 }
92774660 6234
252b5132
RH		 6235 if (leftstart != NULL)
6236 {
6237 buf = (char *) xmalloc (20
6238 + (leftstop - leftstart)
6239 + (rightstop - rightstart));
6240 s = buf;
6241 *s++ = 'c';
6242 *s++ = 'm';
6243 *s++ = 'p';
6244 if (qual != '\0')
3882b010 6245 *s++ = TOLOWER (qual);
252b5132
RH		 6246 *s++ = ' ';
6247 memcpy (s, leftstart, leftstop - leftstart);
6248 s += leftstop - leftstart;
6249 *s++ = ',';
6250 memcpy (s, rightstart, rightstop - rightstart);
6251 s += rightstop - rightstart;
6252 *s = '\0';
6253 mri_assemble (buf);
6254 free (buf);
6255 }
92774660 6256
252b5132
RH		 6257 buf = (char *) xmalloc (20 + strlen (truelab));
6258 s = buf;
6259 *s++ = 'b';
6260 *s++ = cc >> 8;
6261 *s++ = cc & 0xff;
6262 if (extent != '\0')
3882b010 6263 *s++ = TOLOWER (extent);
252b5132
RH		 6264 *s++ = ' ';
6265 strcpy (s, truelab);
6266 mri_assemble (buf);
6267 free (buf);
6268}
6269
6270/* Parse an MRI structured control expression. This generates test
6271 and branch instructions. STOP is where the expression ends. It
6272 goes to TRUELAB if the condition is true, and to FALSELAB if the
6273 condition is false. Exactly one of TRUELAB and FALSELAB will be
6274 NULL, meaning to fall through. QUAL is the size qualifier for the
6275 expression. EXTENT is the size to use for the branch. */
6276
6277static void
31302357
AS		 6278parse_mri_control_expression (char *stop, int qual, const char *truelab,
6279 const char *falselab, int extent)
252b5132
RH		 6280{
6281 int c;
6282 int cc;
6283 char *leftstart;
6284 char *leftstop;
6285 char *rightstart;
6286 char *rightstop;
6287
6288 c = *stop;
6289 *stop = '\0';
6290
6291 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6292 &rightstart, &rightstop))
6293 {
6294 *stop = c;
6295 return;
6296 }
6297
6298 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6299 {
6300 const char *flab;
6301
6302 if (falselab != NULL)
6303 flab = falselab;
6304 else
6305 flab = mri_control_label ();
6306
6307 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6308 rightstop, (const char *) NULL, flab, extent);
6309
6310 input_line_pointer += 3;
6311 if (*input_line_pointer != '.'
6312 || input_line_pointer[1] == '\0')
6313 qual = '\0';
6314 else
6315 {
6316 qual = input_line_pointer[1];
6317 input_line_pointer += 2;
6318 }
6319
6320 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6321 &rightstart, &rightstop))
6322 {
6323 *stop = c;
6324 return;
6325 }
6326
6327 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6328 rightstop, truelab, falselab, extent);
6329
6330 if (falselab == NULL)
6331 colon (flab);
6332 }
6333 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6334 {
6335 const char *tlab;
6336
6337 if (truelab != NULL)
6338 tlab = truelab;
6339 else
6340 tlab = mri_control_label ();
6341
6342 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6343 rightstop, tlab, (const char *) NULL, extent);
6344
6345 input_line_pointer += 2;
6346 if (*input_line_pointer != '.'
6347 || input_line_pointer[1] == '\0')
6348 qual = '\0';
6349 else
6350 {
6351 qual = input_line_pointer[1];
6352 input_line_pointer += 2;
6353 }
6354
6355 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6356 &rightstart, &rightstop))
6357 {
6358 *stop = c;
6359 return;
6360 }
6361
6362 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6363 rightstop, truelab, falselab, extent);
6364
6365 if (truelab == NULL)
6366 colon (tlab);
6367 }
6368 else
6369 {
6370 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6371 rightstop, truelab, falselab, extent);
6372 }
6373
6374 *stop = c;
6375 if (input_line_pointer != stop)
6376 as_bad (_("syntax error in structured control directive"));
6377}
6378
6379/* Handle the MRI IF pseudo-op. This may be a structured control
6380 directive, or it may be a regular assembler conditional, depending
6381 on its operands. */
6382
6383static void
31302357 6384s_mri_if (int qual)
252b5132
RH		 6385{
6386 char *s;
6387 int c;
6388 struct mri_control_info *n;
6389
6390 /* A structured control directive must end with THEN with an
6391 optional qualifier. */
6392 s = input_line_pointer;
e1f44d10
NC		 6393 /* We only accept '*' as introduction of comments if preceded by white space
6394 or at first column of a line (I think this can't actually happen here?)
6395 This is important when assembling:
6396 if d0 <ne> 12(a0,d0*2) then
36759679 6397 if d0 <ne> #CONST*20 then. */
31302357
AS		 6398 while (! (is_end_of_line[(unsigned char) *s]
6399 || (flag_mri
6400 && *s == '*'
6401 && (s == input_line_pointer
6402 || *(s-1) == ' '
6403 || *(s-1) == '\t'))))
252b5132
RH		 6404 ++s;
6405 --s;
6406 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6407 --s;
6408
6409 if (s - input_line_pointer > 1
6410 && s[-1] == '.')
6411 s -= 2;
6412
6413 if (s - input_line_pointer < 3
6414 || strncasecmp (s - 3, "THEN", 4) != 0)
6415 {
6416 if (qual != '\0')
6417 {
6418 as_bad (_("missing then"));
6419 ignore_rest_of_line ();
6420 return;
6421 }
6422
6423 /* It's a conditional. */
6424 s_if (O_ne);
6425 return;
6426 }
6427
6428 /* Since this might be a conditional if, this pseudo-op will be
6429 called even if we are supported to be ignoring input. Double
6430 check now. Clobber *input_line_pointer so that ignore_input
6431 thinks that this is not a special pseudo-op. */
6432 c = *input_line_pointer;
6433 *input_line_pointer = 0;
6434 if (ignore_input ())
6435 {
6436 *input_line_pointer = c;
6437 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6438 ++input_line_pointer;
6439 demand_empty_rest_of_line ();
6440 return;
6441 }
6442 *input_line_pointer = c;
6443
6444 n = push_mri_control (mri_if);
6445
6446 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6447 n->next, s[1] == '.' ? s[2] : '\0');
6448
6449 if (s[1] == '.')
6450 input_line_pointer = s + 3;
6451 else
6452 input_line_pointer = s + 1;
6453
6454 if (flag_mri)
6455 {
6456 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6457 ++input_line_pointer;
6458 }
6459
6460 demand_empty_rest_of_line ();
6461}
6462
6463/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6464 structured IF, associate the ELSE with the IF. Otherwise, assume
6465 it is a conditional else. */
6466
6467static void
31302357 6468s_mri_else (int qual)
252b5132
RH		 6469{
6470 int c;
6471 char *buf;
6472 char q[2];
6473
6474 if (qual == '\0'
6475 && (mri_control_stack == NULL
6476 || mri_control_stack->type != mri_if
6477 || mri_control_stack->else_seen))
6478 {
6479 s_else (0);
6480 return;
6481 }
6482
6483 c = *input_line_pointer;
6484 *input_line_pointer = 0;
6485 if (ignore_input ())
6486 {
6487 *input_line_pointer = c;
6488 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6489 ++input_line_pointer;
6490 demand_empty_rest_of_line ();
6491 return;
6492 }
6493 *input_line_pointer = c;
6494
6495 if (mri_control_stack == NULL
6496 || mri_control_stack->type != mri_if
6497 || mri_control_stack->else_seen)
6498 {
6499 as_bad (_("else without matching if"));
6500 ignore_rest_of_line ();
6501 return;
6502 }
6503
6504 mri_control_stack->else_seen = 1;
6505
6506 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6507 q[0] = TOLOWER (qual);
252b5132
RH		 6508 q[1] = '\0';
6509 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6510 mri_assemble (buf);
6511 free (buf);
6512
6513 colon (mri_control_stack->next);
6514
6515 if (flag_mri)
6516 {
6517 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6518 ++input_line_pointer;
6519 }
6520
6521 demand_empty_rest_of_line ();
6522}
6523
6524/* Handle the MRI ENDI pseudo-op. */
6525
6526static void
31302357 6527s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6528{
6529 if (mri_control_stack == NULL
6530 || mri_control_stack->type != mri_if)
6531 {
6532 as_bad (_("endi without matching if"));
6533 ignore_rest_of_line ();
6534 return;
6535 }
6536
6537 /* ignore_input will not return true for ENDI, so we don't need to
6538 worry about checking it again here. */
6539
6540 if (! mri_control_stack->else_seen)
6541 colon (mri_control_stack->next);
6542 colon (mri_control_stack->bottom);
6543
6544 pop_mri_control ();
6545
6546 if (flag_mri)
6547 {
6548 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6549 ++input_line_pointer;
6550 }
6551
6552 demand_empty_rest_of_line ();
6553}
6554
6555/* Handle the MRI BREAK pseudo-op. */
6556
6557static void
31302357 6558s_mri_break (int extent)
252b5132
RH		 6559{
6560 struct mri_control_info *n;
6561 char *buf;
6562 char ex[2];
6563
6564 n = mri_control_stack;
6565 while (n != NULL
6566 && n->type != mri_for
6567 && n->type != mri_repeat
6568 && n->type != mri_while)
6569 n = n->outer;
6570 if (n == NULL)
6571 {
6572 as_bad (_("break outside of structured loop"));
6573 ignore_rest_of_line ();
6574 return;
6575 }
6576
6577 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6578 ex[0] = TOLOWER (extent);
252b5132
RH		 6579 ex[1] = '\0';
6580 sprintf (buf, "bra%s %s", ex, n->bottom);
6581 mri_assemble (buf);
6582 free (buf);
6583
6584 if (flag_mri)
6585 {
6586 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6587 ++input_line_pointer;
6588 }
6589
6590 demand_empty_rest_of_line ();
6591}
6592
6593/* Handle the MRI NEXT pseudo-op. */
6594
6595static void
31302357 6596s_mri_next (int extent)
252b5132
RH		 6597{
6598 struct mri_control_info *n;
6599 char *buf;
6600 char ex[2];
6601
6602 n = mri_control_stack;
6603 while (n != NULL
6604 && n->type != mri_for
6605 && n->type != mri_repeat
6606 && n->type != mri_while)
6607 n = n->outer;
6608 if (n == NULL)
6609 {
6610 as_bad (_("next outside of structured loop"));
6611 ignore_rest_of_line ();
6612 return;
6613 }
6614
6615 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6616 ex[0] = TOLOWER (extent);
252b5132
RH		 6617 ex[1] = '\0';
6618 sprintf (buf, "bra%s %s", ex, n->next);
6619 mri_assemble (buf);
6620 free (buf);
6621
6622 if (flag_mri)
6623 {
6624 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6625 ++input_line_pointer;
6626 }
6627
6628 demand_empty_rest_of_line ();
6629}
6630
6631/* Handle the MRI FOR pseudo-op. */
6632
6633static void
31302357 6634s_mri_for (int qual)
252b5132
RH		 6635{
6636 const char *varstart, *varstop;
6637 const char *initstart, *initstop;
6638 const char *endstart, *endstop;
6639 const char *bystart, *bystop;
6640 int up;
6641 int by;
6642 int extent;
6643 struct mri_control_info *n;
6644 char *buf;
6645 char *s;
6646 char ex[2];
6647
6648 /* The syntax is
6649 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6650 */
6651
6652 SKIP_WHITESPACE ();
6653 varstart = input_line_pointer;
6654
6655 /* Look for the '='. */
6656 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6657 && *input_line_pointer != '=')
6658 ++input_line_pointer;
6659 if (*input_line_pointer != '=')
6660 {
6661 as_bad (_("missing ="));
6662 ignore_rest_of_line ();
6663 return;
6664 }
6665
6666 varstop = input_line_pointer;
6667 if (varstop > varstart
6668 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6669 --varstop;
6670
6671 ++input_line_pointer;
6672
6673 initstart = input_line_pointer;
6674
6675 /* Look for TO or DOWNTO. */
6676 up = 1;
6677 initstop = NULL;
6678 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6679 {
6680 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6681 && ! is_part_of_name (input_line_pointer[2]))
6682 {
6683 initstop = input_line_pointer;
6684 input_line_pointer += 2;
6685 break;
6686 }
6687 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6688 && ! is_part_of_name (input_line_pointer[6]))
6689 {
6690 initstop = input_line_pointer;
6691 up = 0;
6692 input_line_pointer += 6;
6693 break;
6694 }
6695 ++input_line_pointer;
6696 }
6697 if (initstop == NULL)
6698 {
6699 as_bad (_("missing to or downto"));
6700 ignore_rest_of_line ();
6701 return;
6702 }
6703 if (initstop > initstart
6704 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6705 --initstop;
6706
6707 SKIP_WHITESPACE ();
6708 endstart = input_line_pointer;
6709
6710 /* Look for BY or DO. */
6711 by = 0;
6712 endstop = NULL;
6713 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6714 {
6715 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6716 && ! is_part_of_name (input_line_pointer[2]))
6717 {
6718 endstop = input_line_pointer;
6719 by = 1;
6720 input_line_pointer += 2;
6721 break;
6722 }
6723 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6724 && (input_line_pointer[2] == '.'
6725 || ! is_part_of_name (input_line_pointer[2])))
6726 {
6727 endstop = input_line_pointer;
6728 input_line_pointer += 2;
6729 break;
6730 }
6731 ++input_line_pointer;
6732 }
6733 if (endstop == NULL)
6734 {
6735 as_bad (_("missing do"));
6736 ignore_rest_of_line ();
6737 return;
6738 }
6739 if (endstop > endstart
6740 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6741 --endstop;
6742
6743 if (! by)
6744 {
6745 bystart = "#1";
6746 bystop = bystart + 2;
6747 }
6748 else
6749 {
6750 SKIP_WHITESPACE ();
6751 bystart = input_line_pointer;
6752
6753 /* Look for DO. */
6754 bystop = NULL;
6755 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6756 {
6757 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6758 && (input_line_pointer[2] == '.'
6759 || ! is_part_of_name (input_line_pointer[2])))
6760 {
6761 bystop = input_line_pointer;
6762 input_line_pointer += 2;
6763 break;
6764 }
6765 ++input_line_pointer;
6766 }
6767 if (bystop == NULL)
6768 {
6769 as_bad (_("missing do"));
6770 ignore_rest_of_line ();
6771 return;
6772 }
6773 if (bystop > bystart
6774 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6775 --bystop;
6776 }
6777
6778 if (*input_line_pointer != '.')
6779 extent = '\0';
6780 else
6781 {
6782 extent = input_line_pointer[1];
6783 input_line_pointer += 2;
6784 }
6785
6786 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6787 n = push_mri_control (mri_for);
6788
6789 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6790
36759679 6791 /* Move init,var. */
252b5132
RH		 6792 s = buf;
6793 *s++ = 'm';
6794 *s++ = 'o';
6795 *s++ = 'v';
6796 *s++ = 'e';
6797 if (qual != '\0')
3882b010 6798 *s++ = TOLOWER (qual);
252b5132
RH		 6799 *s++ = ' ';
6800 memcpy (s, initstart, initstop - initstart);
6801 s += initstop - initstart;
6802 *s++ = ',';
6803 memcpy (s, varstart, varstop - varstart);
6804 s += varstop - varstart;
6805 *s = '\0';
6806 mri_assemble (buf);
6807
6808 colon (n->top);
6809
36759679 6810 /* cmp end,var. */
252b5132
RH		 6811 s = buf;
6812 *s++ = 'c';
6813 *s++ = 'm';
6814 *s++ = 'p';
6815 if (qual != '\0')
3882b010 6816 *s++ = TOLOWER (qual);
252b5132
RH		 6817 *s++ = ' ';
6818 memcpy (s, endstart, endstop - endstart);
6819 s += endstop - endstart;
6820 *s++ = ',';
6821 memcpy (s, varstart, varstop - varstart);
6822 s += varstop - varstart;
6823 *s = '\0';
6824 mri_assemble (buf);
6825
36759679 6826 /* bcc bottom. */
3882b010 6827 ex[0] = TOLOWER (extent);
252b5132
RH		 6828 ex[1] = '\0';
6829 if (up)
6830 sprintf (buf, "blt%s %s", ex, n->bottom);
6831 else
6832 sprintf (buf, "bgt%s %s", ex, n->bottom);
6833 mri_assemble (buf);
6834
6835 /* Put together the add or sub instruction used by ENDF. */
6836 s = buf;
6837 if (up)
6838 strcpy (s, "add");
6839 else
6840 strcpy (s, "sub");
6841 s += 3;
6842 if (qual != '\0')
3882b010 6843 *s++ = TOLOWER (qual);
252b5132
RH		 6844 *s++ = ' ';
6845 memcpy (s, bystart, bystop - bystart);
6846 s += bystop - bystart;
6847 *s++ = ',';
6848 memcpy (s, varstart, varstop - varstart);
6849 s += varstop - varstart;
6850 *s = '\0';
6851 n->incr = buf;
6852
6853 if (flag_mri)
6854 {
6855 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6856 ++input_line_pointer;
6857 }
6858
6859 demand_empty_rest_of_line ();
6860}
6861
6862/* Handle the MRI ENDF pseudo-op. */
6863
6864static void
31302357 6865s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6866{
6867 if (mri_control_stack == NULL
6868 || mri_control_stack->type != mri_for)
6869 {
6870 as_bad (_("endf without for"));
6871 ignore_rest_of_line ();
6872 return;
6873 }
6874
6875 colon (mri_control_stack->next);
6876
6877 mri_assemble (mri_control_stack->incr);
6878
6879 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6880 mri_assemble (mri_control_stack->incr);
6881
6882 free (mri_control_stack->incr);
6883
6884 colon (mri_control_stack->bottom);
6885
6886 pop_mri_control ();
6887
6888 if (flag_mri)
6889 {
6890 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6891 ++input_line_pointer;
6892 }
6893
6894 demand_empty_rest_of_line ();
6895}
6896
6897/* Handle the MRI REPEAT pseudo-op. */
6898
6899static void
31302357 6900s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6901{
6902 struct mri_control_info *n;
6903
6904 n = push_mri_control (mri_repeat);
6905 colon (n->top);
6906 if (flag_mri)
6907 {
6908 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6909 ++input_line_pointer;
6910 }
6911 demand_empty_rest_of_line ();
6912}
6913
6914/* Handle the MRI UNTIL pseudo-op. */
6915
6916static void
31302357 6917s_mri_until (int qual)
252b5132
RH		 6918{
6919 char *s;
6920
6921 if (mri_control_stack == NULL
6922 || mri_control_stack->type != mri_repeat)
6923 {
6924 as_bad (_("until without repeat"));
6925 ignore_rest_of_line ();
6926 return;
6927 }
6928
6929 colon (mri_control_stack->next);
6930
6931 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6932 ;
6933
6934 parse_mri_control_expression (s, qual, (const char *) NULL,
6935 mri_control_stack->top, '\0');
6936
6937 colon (mri_control_stack->bottom);
6938
6939 input_line_pointer = s;
6940
6941 pop_mri_control ();
6942
6943 if (flag_mri)
6944 {
6945 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6946 ++input_line_pointer;
6947 }
6948
6949 demand_empty_rest_of_line ();
6950}
6951
6952/* Handle the MRI WHILE pseudo-op. */
6953
6954static void
31302357 6955s_mri_while (int qual)
252b5132
RH		 6956{
6957 char *s;
6958
6959 struct mri_control_info *n;
6960
6961 s = input_line_pointer;
e1f44d10
NC		 6962 /* We only accept '*' as introduction of comments if preceded by white space
6963 or at first column of a line (I think this can't actually happen here?)
6964 This is important when assembling:
6965 while d0 <ne> 12(a0,d0*2) do
36759679 6966 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6967 while (! (is_end_of_line[(unsigned char) *s]
6968 || (flag_mri
6969 && *s == '*'
6970 && (s == input_line_pointer
6971 || *(s-1) == ' '
6972 || *(s-1) == '\t'))))
252b5132
RH		 6973 s++;
6974 --s;
6975 while (*s == ' ' || *s == '\t')
6976 --s;
6977 if (s - input_line_pointer > 1
6978 && s[-1] == '.')
6979 s -= 2;
6980 if (s - input_line_pointer < 2
6981 || strncasecmp (s - 1, "DO", 2) != 0)
6982 {
6983 as_bad (_("missing do"));
6984 ignore_rest_of_line ();
6985 return;
6986 }
6987
6988 n = push_mri_control (mri_while);
6989
6990 colon (n->next);
6991
6992 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6993 s[1] == '.' ? s[2] : '\0');
6994
6995 input_line_pointer = s + 1;
6996 if (*input_line_pointer == '.')
6997 input_line_pointer += 2;
6998
6999 if (flag_mri)
7000 {
7001 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7002 ++input_line_pointer;
7003 }
7004
7005 demand_empty_rest_of_line ();
7006}
7007
7008/* Handle the MRI ENDW pseudo-op. */
7009
7010static void
31302357 7011s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7012{
7013 char *buf;
7014
7015 if (mri_control_stack == NULL
7016 || mri_control_stack->type != mri_while)
7017 {
7018 as_bad (_("endw without while"));
7019 ignore_rest_of_line ();
7020 return;
7021 }
7022
7023 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7024 sprintf (buf, "bra %s", mri_control_stack->next);
7025 mri_assemble (buf);
7026 free (buf);
7027
7028 colon (mri_control_stack->bottom);
7029
7030 pop_mri_control ();
7031
7032 if (flag_mri)
7033 {
7034 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7035 ++input_line_pointer;
7036 }
7037
7038 demand_empty_rest_of_line ();
7039}
7040\f
31302357
AS		 7041/* md_parse_option
7042 Invocation line includes a switch not recognized by the base assembler.
7043 See if it's a processor-specific option. These are:
7044
7045 -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
7046 -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
7047 Select the architecture. Instructions or features not
7048 supported by the selected architecture cause fatal
7049 errors. More than one may be specified. The default is
7050 -m68020 -m68851 -m68881. Note that -m68008 is a synonym
7051 for -m68000, and -m68882 is a synonym for -m68881.
7052 -[A]m[c]no-68851, -[A]m[c]no-68881
7053 Don't accept 688?1 instructions. (The "c" is kind of silly,
7054 so don't use or document it, but that's the way the parsing
7055 works).
7056
7057 -pic Indicates PIC.
7058 -k Indicates PIC. (Sun 3 only.)
7059 --pcrel
7060 Never turn PC-relative branches into absolute jumps.
7061 --bitwise-or
7062 Permit `|' to be used in expressions. */
252b5132
RH		 7063
7064#ifdef OBJ_ELF
5a38dc70 7065const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7066#else
5a38dc70 7067const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7068#endif
7069
7070struct option md_longopts[] = {
7071#define OPTION_PIC (OPTION_MD_BASE)
7072 {"pic", no_argument, NULL, OPTION_PIC},
7073#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7074 {"register-prefix-optional", no_argument, NULL,
7075 OPTION_REGISTER_PREFIX_OPTIONAL},
7076#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7077 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7078#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7079 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7080#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7081 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7082#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7083 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7084#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7085 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7086#define OPTION_PCREL (OPTION_MD_BASE + 7)
7087 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7088 {NULL, no_argument, NULL, 0}
7089};
bc805888 7090size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7091
7092int
31302357 7093md_parse_option (int c, char *arg)
252b5132
RH		 7094{
7095 switch (c)
7096 {
7097 case 'l': /* -l means keep external to 2 bit offset
36759679 7098 rather than 16 bit one. */
252b5132
RH		 7099 flag_short_refs = 1;
7100 break;
7101
7102 case 'S': /* -S means that jbsr's always turn into
7103 jsr's. */
7104 flag_long_jumps = 1;
7105 break;
7106
28e7409f
NC		 7107 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7108 branches into absolute jumps. */
7109 flag_keep_pcrel = 1;
7110 break;
7111
252b5132
RH		 7112 case 'A':
7113 if (*arg == 'm')
8a104df9 7114 arg++;
36759679 7115 /* Intentional fall-through. */
252b5132
RH		 7116 case 'm':
7117
7118 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7119 {
7120 int i;
7121 unsigned long arch;
252b5132
RH		 7122
7123 arg += 3;
7124 if (*arg == 'm')
7125 {
7126 arg++;
7127 if (arg[0] == 'c' && arg[1] == '6')
7128 arg++;
7129 }
7130 for (i = 0; i < n_archs; i++)
7131 if (!strcmp (arg, archs[i].name))
7132 break;
7133 if (i == n_archs)
329e276d
NC		 7134 return 0;
7135
252b5132
RH		 7136 arch = archs[i].arch;
7137 if (arch == m68881)
7138 no_68881 = 1;
7139 else if (arch == m68851)
7140 no_68851 = 1;
7141 else
329e276d 7142 return 0;
252b5132
RH		 7143 }
7144 else
7145 {
7146 int i;
7147
7148 if (arg[0] == 'c' && arg[1] == '6')
7149 arg++;
7150
7151 for (i = 0; i < n_archs; i++)
7152 if (!strcmp (arg, archs[i].name))
7153 {
7154 unsigned long arch = archs[i].arch;
329e276d 7155
252b5132
RH		 7156 if (cpu_of_arch (arch))
7157 /* It's a cpu spec. */
7158 {
7159 current_architecture &= ~m68000up;
7160 current_architecture |= arch;
990ae22a 7161 current_chip = archs[i].chip;
252b5132
RH		 7162 }
7163 else if (arch == m68881)
7164 {
7165 current_architecture |= m68881;
7166 no_68881 = 0;
7167 }
7168 else if (arch == m68851)
7169 {
7170 current_architecture |= m68851;
7171 no_68851 = 0;
7172 }
7173 else
7174 /* ??? */
7175 abort ();
7176 break;
7177 }
7178 if (i == n_archs)
7179 {
7180 as_bad (_("unrecognized architecture specification `%s'"), arg);
7181 return 0;
7182 }
7183 }
7184 break;
7185
7186 case OPTION_PIC:
7187 case 'k':
7188 flag_want_pic = 1;
36759679 7189 break; /* -pic, Position Independent Code. */
252b5132
RH		 7190
7191 case OPTION_REGISTER_PREFIX_OPTIONAL:
7192 flag_reg_prefix_optional = 1;
7193 reg_prefix_optional_seen = 1;
7194 break;
7195
7196 /* -V: SVR4 argument to print version ID. */
7197 case 'V':
7198 print_version_id ();
7199 break;
7200
7201 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7202 should be emitted or not. FIXME: Not implemented. */
7203 case 'Q':
7204 break;
7205
7206 case OPTION_BITWISE_OR:
7207 {
7208 char *n, *t;
7209 const char *s;
7210
7211 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7212 t = n;
7213 for (s = m68k_comment_chars; *s != '\0'; s++)
7214 if (*s != '|')
7215 *t++ = *s;
7216 *t = '\0';
7217 m68k_comment_chars = n;
7218 }
7219 break;
7220
7221 case OPTION_BASE_SIZE_DEFAULT_16:
7222 m68k_index_width_default = SIZE_WORD;
7223 break;
7224
7225 case OPTION_BASE_SIZE_DEFAULT_32:
7226 m68k_index_width_default = SIZE_LONG;
7227 break;
7228
7229 case OPTION_DISP_SIZE_DEFAULT_16:
7230 m68k_rel32 = 0;
7231 m68k_rel32_from_cmdline = 1;
7232 break;
7233
7234 case OPTION_DISP_SIZE_DEFAULT_32:
7235 m68k_rel32 = 1;
7236 m68k_rel32_from_cmdline = 1;
7237 break;
7238
7239 default:
7240 return 0;
7241 }
7242
7243 return 1;
7244}
7245
7246void
31302357 7247md_show_usage (FILE *stream)
252b5132 7248{
76f57f3a 7249 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7250 int i;
7251 unsigned int default_arch;
76f57f3a 7252
8a104df9 7253 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7254 if (*default_cpu == 'm')
7255 default_cpu++;
7256 for (i = 0; i < n_archs; i++)
7257 {
7258 if (strcasecmp (default_cpu, archs[i].name) == 0)
7259 {
7260 default_arch = archs[i].arch;
7261 for (i = 0; i < n_archs; i++)
7262 {
7263 if (archs[i].arch == default_arch
7264 && !archs[i].alias)
7265 {
7266 default_cpu = archs[i].name;
7267 break;
7268 }
7269 }
7270 }
7271 }
7272
bc805888 7273 fprintf (stream, _("\
252b5132
RH		 7274680X0 options:\n\
7275-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 7276-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7277-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6b6e92f4
NC		 7278-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7279-m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
76f57f3a 7280 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 7281-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7282 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 7283 [default yes for 68020, 68030, and cpu32]\n"),
7284 default_cpu);
bc805888 7285 fprintf (stream, _("\
252b5132
RH		 7286-m68851 | -mno-68851\n\
7287 target has/lacks memory-management unit coprocessor\n\
7288 [default yes for 68020 and up]\n\
7289-pic, -k generate position independent code\n\
7290-S turn jbsr into jsr\n\
28e7409f 7291--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7292--register-prefix-optional\n\
7293 recognize register names without prefix character\n\
7294--bitwise-or do not treat `|' as a comment character\n"));
7295 fprintf (stream, _("\
7296--base-size-default-16 base reg without size is 16 bits\n\
7297--base-size-default-32 base reg without size is 32 bits (default)\n\
7298--disp-size-default-16 displacement with unknown size is 16 bits\n\
7299--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7300}
7301\f
7302#ifdef TEST2
7303
7304/* TEST2: Test md_assemble() */
36759679
NC		 7305/* Warning, this routine probably doesn't work anymore. */
7306int
31302357 7307main (void)
252b5132
RH		 7308{
7309 struct m68k_it the_ins;
7310 char buf[120];
7311 char *cp;
7312 int n;
7313
7314 m68k_ip_begin ();
7315 for (;;)
7316 {
7317 if (!gets (buf) || !*buf)
7318 break;
7319 if (buf[0] == '|' || buf[1] == '.')
7320 continue;
7321 for (cp = buf; *cp; cp++)
7322 if (*cp == '\t')
7323 *cp = ' ';
7324 if (is_label (buf))
7325 continue;
7326 memset (&the_ins, '\0', sizeof (the_ins));
7327 m68k_ip (&the_ins, buf);
7328 if (the_ins.error)
7329 {
7330 printf (_("Error %s in %s\n"), the_ins.error, buf);
7331 }
7332 else
7333 {
7334 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7335 for (n = 0; n < the_ins.numo; n++)
7336 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7337 printf (" ");
7338 print_the_insn (&the_ins.opcode[0], stdout);
7339 (void) putchar ('\n');
7340 }
7341 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7342 {
7343 if (the_ins.operands[n].error)
7344 {
7345 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7346 continue;
7347 }
31302357
AS		 7348 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7349 the_ins.operands[n].reg);
252b5132 7350 if (the_ins.operands[n].b_const)
31302357
AS		 7351 printf ("Constant: '%.*s', ",
7352 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7353 the_ins.operands[n].b_const);
7354 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7355 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7356 if (the_ins.operands[n].b_iadd)
31302357
AS		 7357 printf ("Iadd: '%.*s',",
7358 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7359 the_ins.operands[n].b_iadd);
7360 putchar ('\n');
252b5132
RH		 7361 }
7362 }
7363 m68k_ip_end ();
7364 return 0;
7365}
7366
31302357
AS		 7367int
7368is_label (char *str)
252b5132
RH		 7369{
7370 while (*str == ' ')
7371 str++;
7372 while (*str && *str != ' ')
7373 str++;
7374 if (str[-1] == ':' || str[1] == '=')
7375 return 1;
7376 return 0;
7377}
7378
7379#endif
7380
7381/* Possible states for relaxation:
7382
7383 0 0 branch offset byte (bra, etc)
7384 0 1 word
7385 0 2 long
7386
7387 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7388 1 1 word
7389 1 2 long
7390
7391 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7392 2 1 word-long
7393 2 2 long-word
7394 2 3 long-long
7395
7396 */
7397
7398/* We have no need to default values of symbols. */
7399
252b5132 7400symbolS *
31302357 7401md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7402{
7403 return 0;
7404}
7405
7406/* Round up a section size to the appropriate boundary. */
7407valueT
31302357 7408md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7409{
7410#ifdef OBJ_AOUT
7411#ifdef BFD_ASSEMBLER
7412 /* For a.out, force the section size to be aligned. If we don't do
7413 this, BFD will align it for us, but it will not write out the
7414 final bytes of the section. This may be a bug in BFD, but it is
7415 easier to fix it here since that is how the other a.out targets
7416 work. */
7417 int align;
7418
7419 align = bfd_get_section_alignment (stdoutput, segment);
7420 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7421#endif
7422#endif
7423
7424 return size;
7425}
7426
7427/* Exactly what point is a PC-relative offset relative TO?
7428 On the 68k, it is relative to the address of the first extension
7429 word. The difference between the addresses of the offset and the
92774660 7430 first extension word is stored in fx_pcrel_adjust. */
252b5132 7431long
31302357 7432md_pcrel_from (fixS *fixP)
252b5132
RH		 7433{
7434 int adjust;
7435
8390138c
AS		 7436 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7437 sign extend the value here. */
7438 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7439 if (adjust == 64)
7440 adjust = -1;
7441 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7442}
7443
7444#ifndef BFD_ASSEMBLER
7445#ifdef OBJ_COFF
7446
252b5132 7447void
31302357 7448tc_coff_symbol_emit_hook (symbolS *ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7449{
7450}
7451
7452int
31302357 7453tc_coff_sizemachdep (fragS *frag)
252b5132
RH		 7454{
7455 switch (frag->fr_subtype & 0x3)
7456 {
7457 case BYTE:
7458 return 1;
7459 case SHORT:
7460 return 2;
7461 case LONG:
7462 return 4;
7463 default:
7464 abort ();
7465 return 0;
7466 }
7467}
7468
7469#endif
7470#endif
31302357 7471
0d96863f 7472#ifdef OBJ_ELF
8a104df9 7473void
31302357 7474m68k_elf_final_processing (void)
0d96863f 7475{
36759679 7476 /* Set file-specific flags if this is a cpu32 processor. */
238d258f
NC		 7477 if (arch_coldfire_fpu (current_architecture))
7478 elf_elfheader (stdoutput)->e_flags |= EF_CFV4E;
8a104df9
KH		 7479 if (cpu_of_arch (current_architecture) & cpu32)
7480 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7481 else if ((cpu_of_arch (current_architecture) & m68000up)
7482 && !(cpu_of_arch (current_architecture) & m68020up))
7483 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7484}
7485#endif
c04898f8
AS		 7486
7487int
7488tc_m68k_regname_to_dw2regnum (const char *regname)
7489{
7490 unsigned int regnum;
7491 static const char *const regnames[] =
7492 {
7493 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7494 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7495 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7496 "pc"
7497 };
7498
7499 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7500 if (strcmp (regname, regnames[regnum]) == 0)
7501 return regnum;
7502
7503 return -1;
7504}
7505
7506void
7507tc_m68k_frame_initial_instructions (void)
7508{
7509 static int sp_regno = -1;
7510
7511 if (sp_regno < 0)
7512 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7513
7514 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7515 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7516}
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