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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | /* Allow override of standard little-endian ECOFF format. */ |
108 | ||
109 | #ifndef ECOFF_LITTLE_FORMAT | |
110 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
111 | #endif | |
112 | ||
113 | extern int target_big_endian; | |
114 | ||
252b5132 | 115 | /* The name of the readonly data section. */ |
4d0d148d | 116 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 117 | ? ".rdata" \ |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
47e39b9d RS |
124 | /* Information about an instruction, including its format, operands |
125 | and fixups. */ | |
126 | struct mips_cl_insn | |
127 | { | |
128 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
129 | const struct mips_opcode *insn_mo; | |
130 | ||
131 | /* True if this is a mips16 instruction and if we want the extended | |
132 | form of INSN_MO. */ | |
133 | bfd_boolean use_extend; | |
134 | ||
135 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
136 | unsigned short extend; | |
137 | ||
138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
139 | a copy of INSN_MO->match with the operands filled in. */ | |
140 | unsigned long insn_opcode; | |
141 | ||
142 | /* The frag that contains the instruction. */ | |
143 | struct frag *frag; | |
144 | ||
145 | /* The offset into FRAG of the first instruction byte. */ | |
146 | long where; | |
147 | ||
148 | /* The relocs associated with the instruction, if any. */ | |
149 | fixS *fixp[3]; | |
150 | ||
a38419a5 RS |
151 | /* True if this entry cannot be moved from its current position. */ |
152 | unsigned int fixed_p : 1; | |
47e39b9d | 153 | |
708587a4 | 154 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
155 | unsigned int noreorder_p : 1; |
156 | ||
2fa15973 RS |
157 | /* True for mips16 instructions that jump to an absolute address. */ |
158 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
159 | }; |
160 | ||
a325df1d TS |
161 | /* The ABI to use. */ |
162 | enum mips_abi_level | |
163 | { | |
164 | NO_ABI = 0, | |
165 | O32_ABI, | |
166 | O64_ABI, | |
167 | N32_ABI, | |
168 | N64_ABI, | |
169 | EABI_ABI | |
170 | }; | |
171 | ||
172 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 173 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 174 | |
143d77c5 EC |
175 | /* Whether or not we have code that can call pic code. */ |
176 | int mips_abicalls = FALSE; | |
177 | ||
aa6975fb ILT |
178 | /* Whether or not we have code which can be put into a shared |
179 | library. */ | |
180 | static bfd_boolean mips_in_shared = TRUE; | |
181 | ||
252b5132 RH |
182 | /* This is the set of options which may be modified by the .set |
183 | pseudo-op. We use a struct so that .set push and .set pop are more | |
184 | reliable. */ | |
185 | ||
e972090a NC |
186 | struct mips_set_options |
187 | { | |
252b5132 RH |
188 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
189 | if it has not been initialized. Changed by `.set mipsN', and the | |
190 | -mipsN command line option, and the default CPU. */ | |
191 | int isa; | |
1f25f5d3 CD |
192 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
193 | if they have not been initialized. Changed by `.set <asename>', by | |
194 | command line options, and based on the default architecture. */ | |
195 | int ase_mips3d; | |
deec1734 | 196 | int ase_mdmx; |
e16bfa71 | 197 | int ase_smartmips; |
74cd071d | 198 | int ase_dsp; |
8b082fb1 | 199 | int ase_dspr2; |
ef2e4d86 | 200 | int ase_mt; |
252b5132 RH |
201 | /* Whether we are assembling for the mips16 processor. 0 if we are |
202 | not, 1 if we are, and -1 if the value has not been initialized. | |
203 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
204 | -nomips16 command line options, and the default CPU. */ | |
205 | int mips16; | |
206 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
207 | reorder' and `.set noreorder'. */ | |
208 | int noreorder; | |
741fe287 MR |
209 | /* Non-zero if we should not permit the register designated "assembler |
210 | temporary" to be used in instructions. The value is the register | |
211 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
212 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
213 | unsigned int at; | |
252b5132 RH |
214 | /* Non-zero if we should warn when a macro instruction expands into |
215 | more than one machine instruction. Changed by `.set nomacro' and | |
216 | `.set macro'. */ | |
217 | int warn_about_macros; | |
218 | /* Non-zero if we should not move instructions. Changed by `.set | |
219 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
220 | int nomove; | |
221 | /* Non-zero if we should not optimize branches by moving the target | |
222 | of the branch into the delay slot. Actually, we don't perform | |
223 | this optimization anyhow. Changed by `.set bopt' and `.set | |
224 | nobopt'. */ | |
225 | int nobopt; | |
226 | /* Non-zero if we should not autoextend mips16 instructions. | |
227 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
228 | int noautoextend; | |
a325df1d TS |
229 | /* Restrict general purpose registers and floating point registers |
230 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
231 | is passed but can changed if the assembler code uses .set mipsN. */ | |
232 | int gp32; | |
233 | int fp32; | |
fef14a42 TS |
234 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
235 | command line option, and the default CPU. */ | |
236 | int arch; | |
aed1a261 RS |
237 | /* True if ".set sym32" is in effect. */ |
238 | bfd_boolean sym32; | |
037b32b9 AN |
239 | /* True if floating-point operations are not allowed. Changed by .set |
240 | softfloat or .set hardfloat, by command line options -msoft-float or | |
241 | -mhard-float. The default is false. */ | |
242 | bfd_boolean soft_float; | |
243 | ||
244 | /* True if only single-precision floating-point operations are allowed. | |
245 | Changed by .set singlefloat or .set doublefloat, command-line options | |
246 | -msingle-float or -mdouble-float. The default is false. */ | |
247 | bfd_boolean single_float; | |
252b5132 RH |
248 | }; |
249 | ||
037b32b9 AN |
250 | /* This is the struct we use to hold the current set of options. Note |
251 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
252 | -1 to indicate that they have not been initialized. */ | |
253 | ||
a325df1d | 254 | /* True if -mgp32 was passed. */ |
a8e8e863 | 255 | static int file_mips_gp32 = -1; |
a325df1d TS |
256 | |
257 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 258 | static int file_mips_fp32 = -1; |
a325df1d | 259 | |
037b32b9 AN |
260 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
261 | static int file_mips_soft_float = 0; | |
262 | ||
263 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
264 | static int file_mips_single_float = 0; | |
252b5132 | 265 | |
e972090a NC |
266 | static struct mips_set_options mips_opts = |
267 | { | |
037b32b9 AN |
268 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
269 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
270 | /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG, | |
271 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
272 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
273 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 274 | }; |
252b5132 RH |
275 | |
276 | /* These variables are filled in with the masks of registers used. | |
277 | The object format code reads them and puts them in the appropriate | |
278 | place. */ | |
279 | unsigned long mips_gprmask; | |
280 | unsigned long mips_cprmask[4]; | |
281 | ||
282 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 283 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 284 | |
a4672219 TS |
285 | /* True if -mips16 was passed or implied by arguments passed on the |
286 | command line (e.g., by -march). */ | |
287 | static int file_ase_mips16; | |
288 | ||
3994f87e TS |
289 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
290 | || mips_opts.isa == ISA_MIPS32R2 \ | |
291 | || mips_opts.isa == ISA_MIPS64 \ | |
292 | || mips_opts.isa == ISA_MIPS64R2) | |
293 | ||
b12dd2e4 CF |
294 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
295 | #ifdef TE_IRIX | |
1180b5a4 | 296 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 297 | #else |
1180b5a4 RS |
298 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
299 | because there's no place for any addend, the only acceptable | |
300 | expression is a bare symbol. */ | |
301 | #define MIPS_JALR_HINT_P(EXPR) \ | |
302 | (!HAVE_IN_PLACE_ADDENDS \ | |
303 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
304 | #endif |
305 | ||
1f25f5d3 CD |
306 | /* True if -mips3d was passed or implied by arguments passed on the |
307 | command line (e.g., by -march). */ | |
308 | static int file_ase_mips3d; | |
309 | ||
deec1734 CD |
310 | /* True if -mdmx was passed or implied by arguments passed on the |
311 | command line (e.g., by -march). */ | |
312 | static int file_ase_mdmx; | |
313 | ||
e16bfa71 TS |
314 | /* True if -msmartmips was passed or implied by arguments passed on the |
315 | command line (e.g., by -march). */ | |
316 | static int file_ase_smartmips; | |
317 | ||
ad3fea08 TS |
318 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
319 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 320 | |
74cd071d CF |
321 | /* True if -mdsp was passed or implied by arguments passed on the |
322 | command line (e.g., by -march). */ | |
323 | static int file_ase_dsp; | |
324 | ||
ad3fea08 TS |
325 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
326 | || mips_opts.isa == ISA_MIPS64R2) | |
327 | ||
65263ce3 TS |
328 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
329 | ||
8b082fb1 TS |
330 | /* True if -mdspr2 was passed or implied by arguments passed on the |
331 | command line (e.g., by -march). */ | |
332 | static int file_ase_dspr2; | |
333 | ||
334 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
335 | || mips_opts.isa == ISA_MIPS64R2) | |
336 | ||
ef2e4d86 CF |
337 | /* True if -mmt was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_mt; | |
340 | ||
ad3fea08 TS |
341 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
342 | || mips_opts.isa == ISA_MIPS64R2) | |
343 | ||
ec68c924 | 344 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 345 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 346 | static const char *mips_arch_string; |
ec68c924 EC |
347 | |
348 | /* The argument of the -mtune= flag. The architecture for which we | |
349 | are optimizing. */ | |
350 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 351 | static const char *mips_tune_string; |
ec68c924 | 352 | |
316f5878 | 353 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
354 | static int mips_32bitmode = 0; |
355 | ||
316f5878 RS |
356 | /* True if the given ABI requires 32-bit registers. */ |
357 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
358 | ||
359 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
360 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
361 | ((ABI) == N32_ABI \ | |
362 | || (ABI) == N64_ABI \ | |
316f5878 RS |
363 | || (ABI) == O64_ABI) |
364 | ||
ad3fea08 | 365 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
366 | #define ISA_HAS_64BIT_REGS(ISA) \ |
367 | ((ISA) == ISA_MIPS3 \ | |
368 | || (ISA) == ISA_MIPS4 \ | |
369 | || (ISA) == ISA_MIPS5 \ | |
370 | || (ISA) == ISA_MIPS64 \ | |
371 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 372 | |
ad3fea08 TS |
373 | /* Return true if ISA supports 64 bit wide float registers. */ |
374 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
375 | ((ISA) == ISA_MIPS3 \ | |
376 | || (ISA) == ISA_MIPS4 \ | |
377 | || (ISA) == ISA_MIPS5 \ | |
378 | || (ISA) == ISA_MIPS32R2 \ | |
379 | || (ISA) == ISA_MIPS64 \ | |
380 | || (ISA) == ISA_MIPS64R2) | |
381 | ||
af7ee8bf CD |
382 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
383 | instructions. */ | |
707bfff6 TS |
384 | #define ISA_HAS_DROR(ISA) \ |
385 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
386 | |
387 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
388 | instructions. */ | |
707bfff6 TS |
389 | #define ISA_HAS_ROR(ISA) \ |
390 | ((ISA) == ISA_MIPS32R2 \ | |
391 | || (ISA) == ISA_MIPS64R2 \ | |
392 | || mips_opts.ase_smartmips) | |
393 | ||
7455baf8 TS |
394 | /* Return true if ISA supports single-precision floats in odd registers. */ |
395 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
396 | ((ISA) == ISA_MIPS32 \ | |
397 | || (ISA) == ISA_MIPS32R2 \ | |
398 | || (ISA) == ISA_MIPS64 \ | |
399 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 400 | |
ad3fea08 TS |
401 | /* Return true if ISA supports move to/from high part of a 64-bit |
402 | floating-point register. */ | |
403 | #define ISA_HAS_MXHC1(ISA) \ | |
404 | ((ISA) == ISA_MIPS32R2 \ | |
405 | || (ISA) == ISA_MIPS64R2) | |
406 | ||
e013f690 | 407 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 408 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 409 | |
e013f690 | 410 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 411 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 412 | |
ad3fea08 TS |
413 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
414 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 415 | |
316f5878 | 416 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 417 | |
316f5878 | 418 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 419 | |
3b91255e RS |
420 | /* True if relocations are stored in-place. */ |
421 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
422 | ||
aed1a261 RS |
423 | /* The ABI-derived address size. */ |
424 | #define HAVE_64BIT_ADDRESSES \ | |
425 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
426 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 427 | |
aed1a261 RS |
428 | /* The size of symbolic constants (i.e., expressions of the form |
429 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
430 | #define HAVE_32BIT_SYMBOLS \ | |
431 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
432 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 433 | |
b7c7d6c1 TS |
434 | /* Addresses are loaded in different ways, depending on the address size |
435 | in use. The n32 ABI Documentation also mandates the use of additions | |
436 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 437 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 438 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
439 | |
440 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 441 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
442 | |
443 | #define ADDRESS_LOAD_INSN \ | |
444 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
445 | ||
446 | #define ADDRESS_STORE_INSN \ | |
447 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
448 | ||
a4672219 | 449 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
450 | #define CPU_HAS_MIPS16(cpu) \ |
451 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
452 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 453 | |
60b63b72 RS |
454 | /* True if CPU has a dror instruction. */ |
455 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
456 | ||
457 | /* True if CPU has a ror instruction. */ | |
458 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
459 | ||
dd3cbb7e NC |
460 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
461 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
462 | ||
b19e8a9b AN |
463 | /* True if CPU does not implement the all the coprocessor insns. For these |
464 | CPUs only those COP insns are accepted that are explicitly marked to be | |
465 | available on the CPU. ISA membership for COP insns is ignored. */ | |
466 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
467 | ||
c8978940 CD |
468 | /* True if mflo and mfhi can be immediately followed by instructions |
469 | which write to the HI and LO registers. | |
470 | ||
471 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
472 | (at least) two instructions between the reads of HI/LO and | |
473 | instructions which write them, and later ISAs do not. Contradicting | |
474 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
475 | the UM for the NEC Vr5000) document needing the instructions between | |
476 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
477 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
478 | earlier-ISA CPUs for which CPU documentation declares that the | |
479 | instructions are really interlocked. */ | |
480 | #define hilo_interlocks \ | |
481 | (mips_opts.isa == ISA_MIPS32 \ | |
482 | || mips_opts.isa == ISA_MIPS32R2 \ | |
483 | || mips_opts.isa == ISA_MIPS64 \ | |
484 | || mips_opts.isa == ISA_MIPS64R2 \ | |
485 | || mips_opts.arch == CPU_R4010 \ | |
486 | || mips_opts.arch == CPU_R10000 \ | |
487 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
488 | || mips_opts.arch == CPU_R14000 \ |
489 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 490 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 CD |
491 | || mips_opts.arch == CPU_VR5500 \ |
492 | ) | |
252b5132 RH |
493 | |
494 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
495 | from the GPRs after they are loaded from memory, and thus does not |
496 | require nops to be inserted. This applies to instructions marked | |
497 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
498 | level I. */ | |
252b5132 | 499 | #define gpr_interlocks \ |
e7af610e | 500 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 501 | || mips_opts.arch == CPU_R3900) |
252b5132 | 502 | |
81912461 ILT |
503 | /* Whether the processor uses hardware interlocks to avoid delays |
504 | required by coprocessor instructions, and thus does not require | |
505 | nops to be inserted. This applies to instructions marked | |
506 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
507 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
508 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
509 | levels I, II, and III. */ | |
bdaaa2e1 | 510 | /* Itbl support may require additional care here. */ |
81912461 ILT |
511 | #define cop_interlocks \ |
512 | ((mips_opts.isa != ISA_MIPS1 \ | |
513 | && mips_opts.isa != ISA_MIPS2 \ | |
514 | && mips_opts.isa != ISA_MIPS3) \ | |
515 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
516 | ) |
517 | ||
518 | /* Whether the processor uses hardware interlocks to protect reads | |
519 | from coprocessor registers after they are loaded from memory, and | |
520 | thus does not require nops to be inserted. This applies to | |
521 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
522 | requires at MIPS ISA level I. */ | |
523 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 524 | |
6b76fefe CM |
525 | /* Is this a mfhi or mflo instruction? */ |
526 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
527 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
528 | ||
529 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
530 | or writing the condition code is only possible on the coprocessors and | |
531 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 532 | condition-code flags. */ |
b19e8a9b AN |
533 | #define COP_INSN(PINFO) \ |
534 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
535 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
536 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 537 | |
252b5132 RH |
538 | /* MIPS PIC level. */ |
539 | ||
a161fe53 | 540 | enum mips_pic_level mips_pic; |
252b5132 | 541 | |
c9914766 | 542 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 543 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 544 | static int mips_big_got = 0; |
252b5132 RH |
545 | |
546 | /* 1 if trap instructions should used for overflow rather than break | |
547 | instructions. */ | |
c9914766 | 548 | static int mips_trap = 0; |
252b5132 | 549 | |
119d663a | 550 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 551 | by assembling two single width halves into two single width floating |
119d663a NC |
552 | point registers which just happen to alias the double width destination |
553 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 554 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
555 | automatically at assemble time. */ |
556 | static int mips_disable_float_construction; | |
557 | ||
252b5132 RH |
558 | /* Non-zero if any .set noreorder directives were used. */ |
559 | ||
560 | static int mips_any_noreorder; | |
561 | ||
6b76fefe CM |
562 | /* Non-zero if nops should be inserted when the register referenced in |
563 | an mfhi/mflo instruction is read in the next two instructions. */ | |
564 | static int mips_7000_hilo_fix; | |
565 | ||
02ffd3e4 | 566 | /* The size of objects in the small data section. */ |
156c2f8b | 567 | static unsigned int g_switch_value = 8; |
252b5132 RH |
568 | /* Whether the -G option was used. */ |
569 | static int g_switch_seen = 0; | |
570 | ||
571 | #define N_RMASK 0xc4 | |
572 | #define N_VFP 0xd4 | |
573 | ||
574 | /* If we can determine in advance that GP optimization won't be | |
575 | possible, we can skip the relaxation stuff that tries to produce | |
576 | GP-relative references. This makes delay slot optimization work | |
577 | better. | |
578 | ||
579 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
580 | gcc output. It needs to guess right for gcc, otherwise gcc |
581 | will put what it thinks is a GP-relative instruction in a branch | |
582 | delay slot. | |
252b5132 RH |
583 | |
584 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
585 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 586 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
587 | |
588 | /* handle of the OPCODE hash table */ | |
589 | static struct hash_control *op_hash = NULL; | |
590 | ||
591 | /* The opcode hash table we use for the mips16. */ | |
592 | static struct hash_control *mips16_op_hash = NULL; | |
593 | ||
594 | /* This array holds the chars that always start a comment. If the | |
595 | pre-processor is disabled, these aren't very useful */ | |
596 | const char comment_chars[] = "#"; | |
597 | ||
598 | /* This array holds the chars that only start a comment at the beginning of | |
599 | a line. If the line seems to have the form '# 123 filename' | |
600 | .line and .file directives will appear in the pre-processed output */ | |
601 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
602 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 603 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
604 | /* Also note that C style comments are always supported. */ |
605 | const char line_comment_chars[] = "#"; | |
606 | ||
bdaaa2e1 | 607 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 608 | const char line_separator_chars[] = ";"; |
252b5132 RH |
609 | |
610 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
611 | const char EXP_CHARS[] = "eE"; | |
612 | ||
613 | /* Chars that mean this number is a floating point constant */ | |
614 | /* As in 0f12.456 */ | |
615 | /* or 0d1.2345e12 */ | |
616 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
617 | ||
618 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
619 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
620 | but nothing is ideal around here. | |
621 | */ | |
622 | ||
623 | static char *insn_error; | |
624 | ||
625 | static int auto_align = 1; | |
626 | ||
627 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
628 | offset in the stack frame from which to restore the $gp register. | |
629 | This is set by the .cprestore pseudo-op, and saved in this | |
630 | variable. */ | |
631 | static offsetT mips_cprestore_offset = -1; | |
632 | ||
67c1ffbe | 633 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 634 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 635 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
636 | static offsetT mips_cpreturn_offset = -1; |
637 | static int mips_cpreturn_register = -1; | |
638 | static int mips_gp_register = GP; | |
def2e0dd | 639 | static int mips_gprel_offset = 0; |
6478892d | 640 | |
7a621144 DJ |
641 | /* Whether mips_cprestore_offset has been set in the current function |
642 | (or whether it has already been warned about, if not). */ | |
643 | static int mips_cprestore_valid = 0; | |
644 | ||
252b5132 RH |
645 | /* This is the register which holds the stack frame, as set by the |
646 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
647 | static int mips_frame_reg = SP; | |
648 | ||
7a621144 DJ |
649 | /* Whether mips_frame_reg has been set in the current function |
650 | (or whether it has already been warned about, if not). */ | |
651 | static int mips_frame_reg_valid = 0; | |
652 | ||
252b5132 RH |
653 | /* To output NOP instructions correctly, we need to keep information |
654 | about the previous two instructions. */ | |
655 | ||
656 | /* Whether we are optimizing. The default value of 2 means to remove | |
657 | unneeded NOPs and swap branch instructions when possible. A value | |
658 | of 1 means to not swap branches. A value of 0 means to always | |
659 | insert NOPs. */ | |
660 | static int mips_optimize = 2; | |
661 | ||
662 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
663 | equivalent to seeing no -g option at all. */ | |
664 | static int mips_debug = 0; | |
665 | ||
7d8e00cf RS |
666 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
667 | #define MAX_VR4130_NOPS 4 | |
668 | ||
669 | /* The maximum number of NOPs needed to fill delay slots. */ | |
670 | #define MAX_DELAY_NOPS 2 | |
671 | ||
672 | /* The maximum number of NOPs needed for any purpose. */ | |
673 | #define MAX_NOPS 4 | |
71400594 RS |
674 | |
675 | /* A list of previous instructions, with index 0 being the most recent. | |
676 | We need to look back MAX_NOPS instructions when filling delay slots | |
677 | or working around processor errata. We need to look back one | |
678 | instruction further if we're thinking about using history[0] to | |
679 | fill a branch delay slot. */ | |
680 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 681 | |
1e915849 RS |
682 | /* Nop instructions used by emit_nop. */ |
683 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
684 | ||
685 | /* The appropriate nop for the current mode. */ | |
686 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 687 | |
252b5132 RH |
688 | /* If this is set, it points to a frag holding nop instructions which |
689 | were inserted before the start of a noreorder section. If those | |
690 | nops turn out to be unnecessary, the size of the frag can be | |
691 | decreased. */ | |
692 | static fragS *prev_nop_frag; | |
693 | ||
694 | /* The number of nop instructions we created in prev_nop_frag. */ | |
695 | static int prev_nop_frag_holds; | |
696 | ||
697 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 698 | prev_nop_frag. */ |
252b5132 RH |
699 | static int prev_nop_frag_required; |
700 | ||
701 | /* The number of instructions we've seen since prev_nop_frag. */ | |
702 | static int prev_nop_frag_since; | |
703 | ||
704 | /* For ECOFF and ELF, relocations against symbols are done in two | |
705 | parts, with a HI relocation and a LO relocation. Each relocation | |
706 | has only 16 bits of space to store an addend. This means that in | |
707 | order for the linker to handle carries correctly, it must be able | |
708 | to locate both the HI and the LO relocation. This means that the | |
709 | relocations must appear in order in the relocation table. | |
710 | ||
711 | In order to implement this, we keep track of each unmatched HI | |
712 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 713 | corresponding LO relocation. */ |
252b5132 | 714 | |
e972090a NC |
715 | struct mips_hi_fixup |
716 | { | |
252b5132 RH |
717 | /* Next HI fixup. */ |
718 | struct mips_hi_fixup *next; | |
719 | /* This fixup. */ | |
720 | fixS *fixp; | |
721 | /* The section this fixup is in. */ | |
722 | segT seg; | |
723 | }; | |
724 | ||
725 | /* The list of unmatched HI relocs. */ | |
726 | ||
727 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
728 | ||
64bdfcaf RS |
729 | /* The frag containing the last explicit relocation operator. |
730 | Null if explicit relocations have not been used. */ | |
731 | ||
732 | static fragS *prev_reloc_op_frag; | |
733 | ||
252b5132 RH |
734 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
735 | ||
736 | #define X ILLEGAL_REG | |
e972090a NC |
737 | static const int mips32_to_16_reg_map[] = |
738 | { | |
252b5132 RH |
739 | X, X, 2, 3, 4, 5, 6, 7, |
740 | X, X, X, X, X, X, X, X, | |
741 | 0, 1, X, X, X, X, X, X, | |
742 | X, X, X, X, X, X, X, X | |
743 | }; | |
744 | #undef X | |
745 | ||
746 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
747 | ||
e972090a NC |
748 | static const unsigned int mips16_to_32_reg_map[] = |
749 | { | |
252b5132 RH |
750 | 16, 17, 2, 3, 4, 5, 6, 7 |
751 | }; | |
60b63b72 | 752 | |
71400594 RS |
753 | /* Classifies the kind of instructions we're interested in when |
754 | implementing -mfix-vr4120. */ | |
c67a084a NC |
755 | enum fix_vr4120_class |
756 | { | |
71400594 RS |
757 | FIX_VR4120_MACC, |
758 | FIX_VR4120_DMACC, | |
759 | FIX_VR4120_MULT, | |
760 | FIX_VR4120_DMULT, | |
761 | FIX_VR4120_DIV, | |
762 | FIX_VR4120_MTHILO, | |
763 | NUM_FIX_VR4120_CLASSES | |
764 | }; | |
765 | ||
c67a084a NC |
766 | /* ...likewise -mfix-loongson2f-jump. */ |
767 | static bfd_boolean mips_fix_loongson2f_jump; | |
768 | ||
769 | /* ...likewise -mfix-loongson2f-nop. */ | |
770 | static bfd_boolean mips_fix_loongson2f_nop; | |
771 | ||
772 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
773 | static bfd_boolean mips_fix_loongson2f; | |
774 | ||
71400594 RS |
775 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
776 | there must be at least one other instruction between an instruction | |
777 | of type X and an instruction of type Y. */ | |
778 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
779 | ||
780 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 781 | static int mips_fix_vr4120; |
4a6a3df4 | 782 | |
7d8e00cf RS |
783 | /* ...likewise -mfix-vr4130. */ |
784 | static int mips_fix_vr4130; | |
785 | ||
6a32d874 CM |
786 | /* ...likewise -mfix-24k. */ |
787 | static int mips_fix_24k; | |
788 | ||
d954098f DD |
789 | /* ...likewise -mfix-cn63xxp1 */ |
790 | static bfd_boolean mips_fix_cn63xxp1; | |
791 | ||
4a6a3df4 AO |
792 | /* We don't relax branches by default, since this causes us to expand |
793 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
794 | fail to compute the offset before expanding the macro to the most | |
795 | efficient expansion. */ | |
796 | ||
797 | static int mips_relax_branch; | |
252b5132 | 798 | \f |
4d7206a2 RS |
799 | /* The expansion of many macros depends on the type of symbol that |
800 | they refer to. For example, when generating position-dependent code, | |
801 | a macro that refers to a symbol may have two different expansions, | |
802 | one which uses GP-relative addresses and one which uses absolute | |
803 | addresses. When generating SVR4-style PIC, a macro may have | |
804 | different expansions for local and global symbols. | |
805 | ||
806 | We handle these situations by generating both sequences and putting | |
807 | them in variant frags. In position-dependent code, the first sequence | |
808 | will be the GP-relative one and the second sequence will be the | |
809 | absolute one. In SVR4 PIC, the first sequence will be for global | |
810 | symbols and the second will be for local symbols. | |
811 | ||
584892a6 RS |
812 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
813 | SECOND are the lengths of the two sequences in bytes. These fields | |
814 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
815 | the subtype has the following flags: | |
4d7206a2 | 816 | |
584892a6 RS |
817 | RELAX_USE_SECOND |
818 | Set if it has been decided that we should use the second | |
819 | sequence instead of the first. | |
820 | ||
821 | RELAX_SECOND_LONGER | |
822 | Set in the first variant frag if the macro's second implementation | |
823 | is longer than its first. This refers to the macro as a whole, | |
824 | not an individual relaxation. | |
825 | ||
826 | RELAX_NOMACRO | |
827 | Set in the first variant frag if the macro appeared in a .set nomacro | |
828 | block and if one alternative requires a warning but the other does not. | |
829 | ||
830 | RELAX_DELAY_SLOT | |
831 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
832 | delay slot. | |
4d7206a2 RS |
833 | |
834 | The frag's "opcode" points to the first fixup for relaxable code. | |
835 | ||
836 | Relaxable macros are generated using a sequence such as: | |
837 | ||
838 | relax_start (SYMBOL); | |
839 | ... generate first expansion ... | |
840 | relax_switch (); | |
841 | ... generate second expansion ... | |
842 | relax_end (); | |
843 | ||
844 | The code and fixups for the unwanted alternative are discarded | |
845 | by md_convert_frag. */ | |
584892a6 | 846 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 847 | |
584892a6 RS |
848 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
849 | #define RELAX_SECOND(X) ((X) & 0xff) | |
850 | #define RELAX_USE_SECOND 0x10000 | |
851 | #define RELAX_SECOND_LONGER 0x20000 | |
852 | #define RELAX_NOMACRO 0x40000 | |
853 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 854 | |
4a6a3df4 AO |
855 | /* Branch without likely bit. If label is out of range, we turn: |
856 | ||
857 | beq reg1, reg2, label | |
858 | delay slot | |
859 | ||
860 | into | |
861 | ||
862 | bne reg1, reg2, 0f | |
863 | nop | |
864 | j label | |
865 | 0: delay slot | |
866 | ||
867 | with the following opcode replacements: | |
868 | ||
869 | beq <-> bne | |
870 | blez <-> bgtz | |
871 | bltz <-> bgez | |
872 | bc1f <-> bc1t | |
873 | ||
874 | bltzal <-> bgezal (with jal label instead of j label) | |
875 | ||
876 | Even though keeping the delay slot instruction in the delay slot of | |
877 | the branch would be more efficient, it would be very tricky to do | |
878 | correctly, because we'd have to introduce a variable frag *after* | |
879 | the delay slot instruction, and expand that instead. Let's do it | |
880 | the easy way for now, even if the branch-not-taken case now costs | |
881 | one additional instruction. Out-of-range branches are not supposed | |
882 | to be common, anyway. | |
883 | ||
884 | Branch likely. If label is out of range, we turn: | |
885 | ||
886 | beql reg1, reg2, label | |
887 | delay slot (annulled if branch not taken) | |
888 | ||
889 | into | |
890 | ||
891 | beql reg1, reg2, 1f | |
892 | nop | |
893 | beql $0, $0, 2f | |
894 | nop | |
895 | 1: j[al] label | |
896 | delay slot (executed only if branch taken) | |
897 | 2: | |
898 | ||
899 | It would be possible to generate a shorter sequence by losing the | |
900 | likely bit, generating something like: | |
b34976b6 | 901 | |
4a6a3df4 AO |
902 | bne reg1, reg2, 0f |
903 | nop | |
904 | j[al] label | |
905 | delay slot (executed only if branch taken) | |
906 | 0: | |
907 | ||
908 | beql -> bne | |
909 | bnel -> beq | |
910 | blezl -> bgtz | |
911 | bgtzl -> blez | |
912 | bltzl -> bgez | |
913 | bgezl -> bltz | |
914 | bc1fl -> bc1t | |
915 | bc1tl -> bc1f | |
916 | ||
917 | bltzall -> bgezal (with jal label instead of j label) | |
918 | bgezall -> bltzal (ditto) | |
919 | ||
920 | ||
921 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 922 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
923 | ((relax_substateT) \ |
924 | (0xc0000000 \ | |
925 | | ((toofar) ? 1 : 0) \ | |
926 | | ((link) ? 2 : 0) \ | |
927 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 928 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 929 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
930 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
931 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
932 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 933 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 934 | |
252b5132 RH |
935 | /* For mips16 code, we use an entirely different form of relaxation. |
936 | mips16 supports two versions of most instructions which take | |
937 | immediate values: a small one which takes some small value, and a | |
938 | larger one which takes a 16 bit value. Since branches also follow | |
939 | this pattern, relaxing these values is required. | |
940 | ||
941 | We can assemble both mips16 and normal MIPS code in a single | |
942 | object. Therefore, we need to support this type of relaxation at | |
943 | the same time that we support the relaxation described above. We | |
944 | use the high bit of the subtype field to distinguish these cases. | |
945 | ||
946 | The information we store for this type of relaxation is the | |
947 | argument code found in the opcode file for this relocation, whether | |
948 | the user explicitly requested a small or extended form, and whether | |
949 | the relocation is in a jump or jal delay slot. That tells us the | |
950 | size of the value, and how it should be stored. We also store | |
951 | whether the fragment is considered to be extended or not. We also | |
952 | store whether this is known to be a branch to a different section, | |
953 | whether we have tried to relax this frag yet, and whether we have | |
954 | ever extended a PC relative fragment because of a shift count. */ | |
955 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
956 | (0x80000000 \ | |
957 | | ((type) & 0xff) \ | |
958 | | ((small) ? 0x100 : 0) \ | |
959 | | ((ext) ? 0x200 : 0) \ | |
960 | | ((dslot) ? 0x400 : 0) \ | |
961 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 962 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
963 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
964 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
965 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
966 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
967 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
968 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
969 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
970 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
971 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
972 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
973 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
974 | |
975 | /* Is the given value a sign-extended 32-bit value? */ | |
976 | #define IS_SEXT_32BIT_NUM(x) \ | |
977 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
978 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
979 | ||
980 | /* Is the given value a sign-extended 16-bit value? */ | |
981 | #define IS_SEXT_16BIT_NUM(x) \ | |
982 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
983 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
984 | ||
2051e8c4 MR |
985 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
986 | #define IS_ZEXT_32BIT_NUM(x) \ | |
987 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
988 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
989 | ||
bf12938e RS |
990 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
991 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
992 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
993 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
994 | | (((VALUE) & (MASK)) << (SHIFT))) | |
995 | ||
996 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
997 | SHIFT places. */ | |
998 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
999 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1000 | ||
1001 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1002 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1003 | ||
1004 | include/opcode/mips.h specifies operand fields using the macros | |
1005 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1006 | with "MIPS16OP" instead of "OP". */ | |
1007 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1008 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1009 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
1010 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1011 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1012 | ||
1013 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
1014 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
1015 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
1016 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
1017 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1018 | MIPS16OP_MASK_##FIELD, \ | |
1019 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
1020 | \f |
1021 | /* Global variables used when generating relaxable macros. See the | |
1022 | comment above RELAX_ENCODE for more details about how relaxation | |
1023 | is used. */ | |
1024 | static struct { | |
1025 | /* 0 if we're not emitting a relaxable macro. | |
1026 | 1 if we're emitting the first of the two relaxation alternatives. | |
1027 | 2 if we're emitting the second alternative. */ | |
1028 | int sequence; | |
1029 | ||
1030 | /* The first relaxable fixup in the current frag. (In other words, | |
1031 | the first fixup that refers to relaxable code.) */ | |
1032 | fixS *first_fixup; | |
1033 | ||
1034 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1035 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1036 | unsigned int sizes[2]; | |
1037 | ||
1038 | /* The symbol on which the choice of sequence depends. */ | |
1039 | symbolS *symbol; | |
1040 | } mips_relax; | |
252b5132 | 1041 | \f |
584892a6 RS |
1042 | /* Global variables used to decide whether a macro needs a warning. */ |
1043 | static struct { | |
1044 | /* True if the macro is in a branch delay slot. */ | |
1045 | bfd_boolean delay_slot_p; | |
1046 | ||
1047 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
1048 | in bytes and sizes[1] is the length of the second alternative. | |
1049 | For non-relaxable macros, both elements give the length of the | |
1050 | macro in bytes. */ | |
1051 | unsigned int sizes[2]; | |
1052 | ||
1053 | /* The first variant frag for this macro. */ | |
1054 | fragS *first_frag; | |
1055 | } mips_macro_warning; | |
1056 | \f | |
252b5132 RH |
1057 | /* Prototypes for static functions. */ |
1058 | ||
17a2f251 | 1059 | #define internalError() \ |
252b5132 | 1060 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1061 | |
1062 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1063 | ||
b34976b6 | 1064 | static void append_insn |
c67a084a | 1065 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *); |
7d10b47d | 1066 | static void mips_no_prev_insn (void); |
c67a084a | 1067 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1068 | static void mips16_macro_build |
03ea81db | 1069 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1070 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1071 | static void macro_start (void); |
1072 | static void macro_end (void); | |
17a2f251 TS |
1073 | static void macro (struct mips_cl_insn * ip); |
1074 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 1075 | #ifdef LOSING_COMPILER |
17a2f251 | 1076 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 1077 | #endif |
17a2f251 TS |
1078 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1079 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1080 | static void mips16_immed |
17a2f251 TS |
1081 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1082 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1083 | static size_t my_getSmallExpression |
17a2f251 TS |
1084 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1085 | static void my_getExpression (expressionS *, char *); | |
1086 | static void s_align (int); | |
1087 | static void s_change_sec (int); | |
1088 | static void s_change_section (int); | |
1089 | static void s_cons (int); | |
1090 | static void s_float_cons (int); | |
1091 | static void s_mips_globl (int); | |
1092 | static void s_option (int); | |
1093 | static void s_mipsset (int); | |
1094 | static void s_abicalls (int); | |
1095 | static void s_cpload (int); | |
1096 | static void s_cpsetup (int); | |
1097 | static void s_cplocal (int); | |
1098 | static void s_cprestore (int); | |
1099 | static void s_cpreturn (int); | |
741d6ea8 JM |
1100 | static void s_dtprelword (int); |
1101 | static void s_dtpreldword (int); | |
17a2f251 TS |
1102 | static void s_gpvalue (int); |
1103 | static void s_gpword (int); | |
1104 | static void s_gpdword (int); | |
1105 | static void s_cpadd (int); | |
1106 | static void s_insn (int); | |
1107 | static void md_obj_begin (void); | |
1108 | static void md_obj_end (void); | |
1109 | static void s_mips_ent (int); | |
1110 | static void s_mips_end (int); | |
1111 | static void s_mips_frame (int); | |
1112 | static void s_mips_mask (int reg_type); | |
1113 | static void s_mips_stab (int); | |
1114 | static void s_mips_weakext (int); | |
1115 | static void s_mips_file (int); | |
1116 | static void s_mips_loc (int); | |
1117 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1118 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1119 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1120 | |
1121 | /* Table and functions used to map between CPU/ISA names, and | |
1122 | ISA levels, and CPU numbers. */ | |
1123 | ||
e972090a NC |
1124 | struct mips_cpu_info |
1125 | { | |
e7af610e | 1126 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1127 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1128 | int isa; /* ISA level. */ |
1129 | int cpu; /* CPU number (default CPU if ISA). */ | |
1130 | }; | |
1131 | ||
ad3fea08 TS |
1132 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1133 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1134 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1135 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1136 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1137 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1138 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1139 | |
17a2f251 TS |
1140 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1141 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1142 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1143 | \f |
1144 | /* Pseudo-op table. | |
1145 | ||
1146 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1147 | should be defined here, but are currently unsupported: .alias, | |
1148 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1149 | ||
1150 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1151 | specific to the type of debugging information being generated, and | |
1152 | should be defined by the object format: .aent, .begin, .bend, | |
1153 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1154 | .vreg. | |
1155 | ||
1156 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1157 | not MIPS CPU specific, but are also not specific to the object file | |
1158 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1159 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1160 | |
e972090a NC |
1161 | static const pseudo_typeS mips_pseudo_table[] = |
1162 | { | |
beae10d5 | 1163 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1164 | {"option", s_option, 0}, |
1165 | {"set", s_mipsset, 0}, | |
1166 | {"rdata", s_change_sec, 'r'}, | |
1167 | {"sdata", s_change_sec, 's'}, | |
1168 | {"livereg", s_ignore, 0}, | |
1169 | {"abicalls", s_abicalls, 0}, | |
1170 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1171 | {"cpsetup", s_cpsetup, 0}, |
1172 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1173 | {"cprestore", s_cprestore, 0}, |
6478892d | 1174 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1175 | {"dtprelword", s_dtprelword, 0}, |
1176 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1177 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1178 | {"gpword", s_gpword, 0}, |
10181a0d | 1179 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1180 | {"cpadd", s_cpadd, 0}, |
1181 | {"insn", s_insn, 0}, | |
1182 | ||
beae10d5 | 1183 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1184 | chips. */ |
38a57ae7 | 1185 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1186 | {"bss", s_change_sec, 'b'}, |
1187 | {"err", s_err, 0}, | |
1188 | {"half", s_cons, 1}, | |
1189 | {"dword", s_cons, 3}, | |
1190 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1191 | {"origin", s_org, 0}, |
1192 | {"repeat", s_rept, 0}, | |
252b5132 | 1193 | |
beae10d5 | 1194 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1195 | here for one reason or another. */ |
1196 | {"align", s_align, 0}, | |
1197 | {"byte", s_cons, 0}, | |
1198 | {"data", s_change_sec, 'd'}, | |
1199 | {"double", s_float_cons, 'd'}, | |
1200 | {"float", s_float_cons, 'f'}, | |
1201 | {"globl", s_mips_globl, 0}, | |
1202 | {"global", s_mips_globl, 0}, | |
1203 | {"hword", s_cons, 1}, | |
1204 | {"int", s_cons, 2}, | |
1205 | {"long", s_cons, 2}, | |
1206 | {"octa", s_cons, 4}, | |
1207 | {"quad", s_cons, 3}, | |
cca86cc8 | 1208 | {"section", s_change_section, 0}, |
252b5132 RH |
1209 | {"short", s_cons, 1}, |
1210 | {"single", s_float_cons, 'f'}, | |
1211 | {"stabn", s_mips_stab, 'n'}, | |
1212 | {"text", s_change_sec, 't'}, | |
1213 | {"word", s_cons, 2}, | |
add56521 | 1214 | |
add56521 | 1215 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1216 | |
43841e91 | 1217 | { NULL, NULL, 0 }, |
252b5132 RH |
1218 | }; |
1219 | ||
e972090a NC |
1220 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1221 | { | |
beae10d5 KH |
1222 | /* These pseudo-ops should be defined by the object file format. |
1223 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1224 | {"aent", s_mips_ent, 1}, |
1225 | {"bgnb", s_ignore, 0}, | |
1226 | {"end", s_mips_end, 0}, | |
1227 | {"endb", s_ignore, 0}, | |
1228 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1229 | {"file", s_mips_file, 0}, |
252b5132 RH |
1230 | {"fmask", s_mips_mask, 'F'}, |
1231 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1232 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1233 | {"mask", s_mips_mask, 'R'}, |
1234 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1235 | { NULL, NULL, 0 }, |
252b5132 RH |
1236 | }; |
1237 | ||
17a2f251 | 1238 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1239 | |
1240 | void | |
17a2f251 | 1241 | mips_pop_insert (void) |
252b5132 RH |
1242 | { |
1243 | pop_insert (mips_pseudo_table); | |
1244 | if (! ECOFF_DEBUGGING) | |
1245 | pop_insert (mips_nonecoff_pseudo_table); | |
1246 | } | |
1247 | \f | |
1248 | /* Symbols labelling the current insn. */ | |
1249 | ||
e972090a NC |
1250 | struct insn_label_list |
1251 | { | |
252b5132 RH |
1252 | struct insn_label_list *next; |
1253 | symbolS *label; | |
1254 | }; | |
1255 | ||
252b5132 | 1256 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1257 | #define label_list tc_segment_info_data.labels |
252b5132 | 1258 | |
17a2f251 | 1259 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1260 | |
1261 | static inline void | |
17a2f251 | 1262 | mips_clear_insn_labels (void) |
252b5132 RH |
1263 | { |
1264 | register struct insn_label_list **pl; | |
a8dbcb85 | 1265 | segment_info_type *si; |
252b5132 | 1266 | |
a8dbcb85 TS |
1267 | if (now_seg) |
1268 | { | |
1269 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1270 | ; | |
1271 | ||
1272 | si = seg_info (now_seg); | |
1273 | *pl = si->label_list; | |
1274 | si->label_list = NULL; | |
1275 | } | |
252b5132 | 1276 | } |
a8dbcb85 | 1277 | |
252b5132 RH |
1278 | \f |
1279 | static char *expr_end; | |
1280 | ||
1281 | /* Expressions which appear in instructions. These are set by | |
1282 | mips_ip. */ | |
1283 | ||
1284 | static expressionS imm_expr; | |
5f74bc13 | 1285 | static expressionS imm2_expr; |
252b5132 RH |
1286 | static expressionS offset_expr; |
1287 | ||
1288 | /* Relocs associated with imm_expr and offset_expr. */ | |
1289 | ||
f6688943 TS |
1290 | static bfd_reloc_code_real_type imm_reloc[3] |
1291 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1292 | static bfd_reloc_code_real_type offset_reloc[3] | |
1293 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1294 | |
252b5132 RH |
1295 | /* These are set by mips16_ip if an explicit extension is used. */ |
1296 | ||
b34976b6 | 1297 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1298 | |
7ed4a06a | 1299 | #ifdef OBJ_ELF |
ecb4347a DJ |
1300 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1301 | ECOFF debugging. */ | |
252b5132 RH |
1302 | |
1303 | static segT pdr_seg; | |
7ed4a06a | 1304 | #endif |
252b5132 | 1305 | |
e013f690 TS |
1306 | /* The default target format to use. */ |
1307 | ||
1308 | const char * | |
17a2f251 | 1309 | mips_target_format (void) |
e013f690 TS |
1310 | { |
1311 | switch (OUTPUT_FLAVOR) | |
1312 | { | |
e013f690 TS |
1313 | case bfd_target_ecoff_flavour: |
1314 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1315 | case bfd_target_coff_flavour: | |
1316 | return "pe-mips"; | |
1317 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1318 | #ifdef TE_VXWORKS |
1319 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1320 | return (target_big_endian | |
1321 | ? "elf32-bigmips-vxworks" | |
1322 | : "elf32-littlemips-vxworks"); | |
1323 | #endif | |
e013f690 | 1324 | #ifdef TE_TMIPS |
cfe86eaa | 1325 | /* This is traditional mips. */ |
e013f690 | 1326 | return (target_big_endian |
cfe86eaa TS |
1327 | ? (HAVE_64BIT_OBJECTS |
1328 | ? "elf64-tradbigmips" | |
1329 | : (HAVE_NEWABI | |
1330 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1331 | : (HAVE_64BIT_OBJECTS | |
1332 | ? "elf64-tradlittlemips" | |
1333 | : (HAVE_NEWABI | |
1334 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1335 | #else |
1336 | return (target_big_endian | |
cfe86eaa TS |
1337 | ? (HAVE_64BIT_OBJECTS |
1338 | ? "elf64-bigmips" | |
1339 | : (HAVE_NEWABI | |
1340 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1341 | : (HAVE_64BIT_OBJECTS | |
1342 | ? "elf64-littlemips" | |
1343 | : (HAVE_NEWABI | |
1344 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1345 | #endif |
1346 | default: | |
1347 | abort (); | |
1348 | return NULL; | |
1349 | } | |
1350 | } | |
1351 | ||
1e915849 RS |
1352 | /* Return the length of instruction INSN. */ |
1353 | ||
1354 | static inline unsigned int | |
1355 | insn_length (const struct mips_cl_insn *insn) | |
1356 | { | |
1357 | if (!mips_opts.mips16) | |
1358 | return 4; | |
1359 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1360 | } | |
1361 | ||
1362 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1363 | ||
1364 | static void | |
1365 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1366 | { | |
1367 | size_t i; | |
1368 | ||
1369 | insn->insn_mo = mo; | |
1370 | insn->use_extend = FALSE; | |
1371 | insn->extend = 0; | |
1372 | insn->insn_opcode = mo->match; | |
1373 | insn->frag = NULL; | |
1374 | insn->where = 0; | |
1375 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1376 | insn->fixp[i] = NULL; | |
1377 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1378 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1379 | insn->mips16_absolute_jump_p = 0; | |
1380 | } | |
1381 | ||
742a56fe RS |
1382 | /* Record the current MIPS16 mode in now_seg. */ |
1383 | ||
1384 | static void | |
1385 | mips_record_mips16_mode (void) | |
1386 | { | |
1387 | segment_info_type *si; | |
1388 | ||
1389 | si = seg_info (now_seg); | |
1390 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1391 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
1392 | } | |
1393 | ||
1e915849 RS |
1394 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1395 | ||
1396 | static void | |
1397 | install_insn (const struct mips_cl_insn *insn) | |
1398 | { | |
1399 | char *f = insn->frag->fr_literal + insn->where; | |
1400 | if (!mips_opts.mips16) | |
1401 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1402 | else if (insn->mips16_absolute_jump_p) | |
1403 | { | |
1404 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1405 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1406 | } | |
1407 | else | |
1408 | { | |
1409 | if (insn->use_extend) | |
1410 | { | |
1411 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1412 | f += 2; | |
1413 | } | |
1414 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1415 | } | |
742a56fe | 1416 | mips_record_mips16_mode (); |
1e915849 RS |
1417 | } |
1418 | ||
1419 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1420 | and install the opcode in the new location. */ | |
1421 | ||
1422 | static void | |
1423 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1424 | { | |
1425 | size_t i; | |
1426 | ||
1427 | insn->frag = frag; | |
1428 | insn->where = where; | |
1429 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1430 | if (insn->fixp[i] != NULL) | |
1431 | { | |
1432 | insn->fixp[i]->fx_frag = frag; | |
1433 | insn->fixp[i]->fx_where = where; | |
1434 | } | |
1435 | install_insn (insn); | |
1436 | } | |
1437 | ||
1438 | /* Add INSN to the end of the output. */ | |
1439 | ||
1440 | static void | |
1441 | add_fixed_insn (struct mips_cl_insn *insn) | |
1442 | { | |
1443 | char *f = frag_more (insn_length (insn)); | |
1444 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1445 | } | |
1446 | ||
1447 | /* Start a variant frag and move INSN to the start of the variant part, | |
1448 | marking it as fixed. The other arguments are as for frag_var. */ | |
1449 | ||
1450 | static void | |
1451 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1452 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1453 | { | |
1454 | frag_grow (max_chars); | |
1455 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1456 | insn->fixed_p = 1; | |
1457 | frag_var (rs_machine_dependent, max_chars, var, | |
1458 | subtype, symbol, offset, NULL); | |
1459 | } | |
1460 | ||
1461 | /* Insert N copies of INSN into the history buffer, starting at | |
1462 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1463 | ||
1464 | static void | |
1465 | insert_into_history (unsigned int first, unsigned int n, | |
1466 | const struct mips_cl_insn *insn) | |
1467 | { | |
1468 | if (mips_relax.sequence != 2) | |
1469 | { | |
1470 | unsigned int i; | |
1471 | ||
1472 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1473 | if (i >= first + n) | |
1474 | history[i] = history[i - n]; | |
1475 | else | |
1476 | history[i] = *insn; | |
1477 | } | |
1478 | } | |
1479 | ||
1480 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1481 | ||
1482 | static void | |
1483 | emit_nop (void) | |
1484 | { | |
1485 | add_fixed_insn (NOP_INSN); | |
1486 | insert_into_history (0, 1, NOP_INSN); | |
1487 | } | |
1488 | ||
71400594 RS |
1489 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1490 | the idea is to make it obvious at a glance that each errata is | |
1491 | included. */ | |
1492 | ||
1493 | static void | |
1494 | init_vr4120_conflicts (void) | |
1495 | { | |
1496 | #define CONFLICT(FIRST, SECOND) \ | |
1497 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1498 | ||
1499 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1500 | CONFLICT (MACC, DIV); | |
1501 | CONFLICT (DMACC, DIV); | |
1502 | ||
1503 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1504 | CONFLICT (DMULT, DMULT); | |
1505 | CONFLICT (DMULT, DMACC); | |
1506 | CONFLICT (DMACC, DMULT); | |
1507 | CONFLICT (DMACC, DMACC); | |
1508 | ||
1509 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1510 | CONFLICT (MACC, MTHILO); | |
1511 | CONFLICT (DMACC, MTHILO); | |
1512 | ||
1513 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1514 | instruction is executed immediately after a MACC or DMACC | |
1515 | instruction, the result of [either instruction] is incorrect." */ | |
1516 | CONFLICT (MACC, MULT); | |
1517 | CONFLICT (MACC, DMULT); | |
1518 | CONFLICT (DMACC, MULT); | |
1519 | CONFLICT (DMACC, DMULT); | |
1520 | ||
1521 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1522 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1523 | DDIV or DDIVU instruction, the result of the MACC or | |
1524 | DMACC instruction is incorrect.". */ | |
1525 | CONFLICT (DMULT, MACC); | |
1526 | CONFLICT (DMULT, DMACC); | |
1527 | CONFLICT (DIV, MACC); | |
1528 | CONFLICT (DIV, DMACC); | |
1529 | ||
1530 | #undef CONFLICT | |
1531 | } | |
1532 | ||
707bfff6 TS |
1533 | struct regname { |
1534 | const char *name; | |
1535 | unsigned int num; | |
1536 | }; | |
1537 | ||
1538 | #define RTYPE_MASK 0x1ff00 | |
1539 | #define RTYPE_NUM 0x00100 | |
1540 | #define RTYPE_FPU 0x00200 | |
1541 | #define RTYPE_FCC 0x00400 | |
1542 | #define RTYPE_VEC 0x00800 | |
1543 | #define RTYPE_GP 0x01000 | |
1544 | #define RTYPE_CP0 0x02000 | |
1545 | #define RTYPE_PC 0x04000 | |
1546 | #define RTYPE_ACC 0x08000 | |
1547 | #define RTYPE_CCC 0x10000 | |
1548 | #define RNUM_MASK 0x000ff | |
1549 | #define RWARN 0x80000 | |
1550 | ||
1551 | #define GENERIC_REGISTER_NUMBERS \ | |
1552 | {"$0", RTYPE_NUM | 0}, \ | |
1553 | {"$1", RTYPE_NUM | 1}, \ | |
1554 | {"$2", RTYPE_NUM | 2}, \ | |
1555 | {"$3", RTYPE_NUM | 3}, \ | |
1556 | {"$4", RTYPE_NUM | 4}, \ | |
1557 | {"$5", RTYPE_NUM | 5}, \ | |
1558 | {"$6", RTYPE_NUM | 6}, \ | |
1559 | {"$7", RTYPE_NUM | 7}, \ | |
1560 | {"$8", RTYPE_NUM | 8}, \ | |
1561 | {"$9", RTYPE_NUM | 9}, \ | |
1562 | {"$10", RTYPE_NUM | 10}, \ | |
1563 | {"$11", RTYPE_NUM | 11}, \ | |
1564 | {"$12", RTYPE_NUM | 12}, \ | |
1565 | {"$13", RTYPE_NUM | 13}, \ | |
1566 | {"$14", RTYPE_NUM | 14}, \ | |
1567 | {"$15", RTYPE_NUM | 15}, \ | |
1568 | {"$16", RTYPE_NUM | 16}, \ | |
1569 | {"$17", RTYPE_NUM | 17}, \ | |
1570 | {"$18", RTYPE_NUM | 18}, \ | |
1571 | {"$19", RTYPE_NUM | 19}, \ | |
1572 | {"$20", RTYPE_NUM | 20}, \ | |
1573 | {"$21", RTYPE_NUM | 21}, \ | |
1574 | {"$22", RTYPE_NUM | 22}, \ | |
1575 | {"$23", RTYPE_NUM | 23}, \ | |
1576 | {"$24", RTYPE_NUM | 24}, \ | |
1577 | {"$25", RTYPE_NUM | 25}, \ | |
1578 | {"$26", RTYPE_NUM | 26}, \ | |
1579 | {"$27", RTYPE_NUM | 27}, \ | |
1580 | {"$28", RTYPE_NUM | 28}, \ | |
1581 | {"$29", RTYPE_NUM | 29}, \ | |
1582 | {"$30", RTYPE_NUM | 30}, \ | |
1583 | {"$31", RTYPE_NUM | 31} | |
1584 | ||
1585 | #define FPU_REGISTER_NAMES \ | |
1586 | {"$f0", RTYPE_FPU | 0}, \ | |
1587 | {"$f1", RTYPE_FPU | 1}, \ | |
1588 | {"$f2", RTYPE_FPU | 2}, \ | |
1589 | {"$f3", RTYPE_FPU | 3}, \ | |
1590 | {"$f4", RTYPE_FPU | 4}, \ | |
1591 | {"$f5", RTYPE_FPU | 5}, \ | |
1592 | {"$f6", RTYPE_FPU | 6}, \ | |
1593 | {"$f7", RTYPE_FPU | 7}, \ | |
1594 | {"$f8", RTYPE_FPU | 8}, \ | |
1595 | {"$f9", RTYPE_FPU | 9}, \ | |
1596 | {"$f10", RTYPE_FPU | 10}, \ | |
1597 | {"$f11", RTYPE_FPU | 11}, \ | |
1598 | {"$f12", RTYPE_FPU | 12}, \ | |
1599 | {"$f13", RTYPE_FPU | 13}, \ | |
1600 | {"$f14", RTYPE_FPU | 14}, \ | |
1601 | {"$f15", RTYPE_FPU | 15}, \ | |
1602 | {"$f16", RTYPE_FPU | 16}, \ | |
1603 | {"$f17", RTYPE_FPU | 17}, \ | |
1604 | {"$f18", RTYPE_FPU | 18}, \ | |
1605 | {"$f19", RTYPE_FPU | 19}, \ | |
1606 | {"$f20", RTYPE_FPU | 20}, \ | |
1607 | {"$f21", RTYPE_FPU | 21}, \ | |
1608 | {"$f22", RTYPE_FPU | 22}, \ | |
1609 | {"$f23", RTYPE_FPU | 23}, \ | |
1610 | {"$f24", RTYPE_FPU | 24}, \ | |
1611 | {"$f25", RTYPE_FPU | 25}, \ | |
1612 | {"$f26", RTYPE_FPU | 26}, \ | |
1613 | {"$f27", RTYPE_FPU | 27}, \ | |
1614 | {"$f28", RTYPE_FPU | 28}, \ | |
1615 | {"$f29", RTYPE_FPU | 29}, \ | |
1616 | {"$f30", RTYPE_FPU | 30}, \ | |
1617 | {"$f31", RTYPE_FPU | 31} | |
1618 | ||
1619 | #define FPU_CONDITION_CODE_NAMES \ | |
1620 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1621 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1622 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1623 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1624 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1625 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1626 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1627 | {"$fcc7", RTYPE_FCC | 7} | |
1628 | ||
1629 | #define COPROC_CONDITION_CODE_NAMES \ | |
1630 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1631 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1632 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1633 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1634 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1635 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1636 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1637 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1638 | ||
1639 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1640 | {"$a4", RTYPE_GP | 8}, \ | |
1641 | {"$a5", RTYPE_GP | 9}, \ | |
1642 | {"$a6", RTYPE_GP | 10}, \ | |
1643 | {"$a7", RTYPE_GP | 11}, \ | |
1644 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1645 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1646 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1647 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1648 | {"$t0", RTYPE_GP | 12}, \ | |
1649 | {"$t1", RTYPE_GP | 13}, \ | |
1650 | {"$t2", RTYPE_GP | 14}, \ | |
1651 | {"$t3", RTYPE_GP | 15} | |
1652 | ||
1653 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1654 | {"$t0", RTYPE_GP | 8}, \ | |
1655 | {"$t1", RTYPE_GP | 9}, \ | |
1656 | {"$t2", RTYPE_GP | 10}, \ | |
1657 | {"$t3", RTYPE_GP | 11}, \ | |
1658 | {"$t4", RTYPE_GP | 12}, \ | |
1659 | {"$t5", RTYPE_GP | 13}, \ | |
1660 | {"$t6", RTYPE_GP | 14}, \ | |
1661 | {"$t7", RTYPE_GP | 15}, \ | |
1662 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1663 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1664 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1665 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1666 | ||
1667 | /* Remaining symbolic register names */ | |
1668 | #define SYMBOLIC_REGISTER_NAMES \ | |
1669 | {"$zero", RTYPE_GP | 0}, \ | |
1670 | {"$at", RTYPE_GP | 1}, \ | |
1671 | {"$AT", RTYPE_GP | 1}, \ | |
1672 | {"$v0", RTYPE_GP | 2}, \ | |
1673 | {"$v1", RTYPE_GP | 3}, \ | |
1674 | {"$a0", RTYPE_GP | 4}, \ | |
1675 | {"$a1", RTYPE_GP | 5}, \ | |
1676 | {"$a2", RTYPE_GP | 6}, \ | |
1677 | {"$a3", RTYPE_GP | 7}, \ | |
1678 | {"$s0", RTYPE_GP | 16}, \ | |
1679 | {"$s1", RTYPE_GP | 17}, \ | |
1680 | {"$s2", RTYPE_GP | 18}, \ | |
1681 | {"$s3", RTYPE_GP | 19}, \ | |
1682 | {"$s4", RTYPE_GP | 20}, \ | |
1683 | {"$s5", RTYPE_GP | 21}, \ | |
1684 | {"$s6", RTYPE_GP | 22}, \ | |
1685 | {"$s7", RTYPE_GP | 23}, \ | |
1686 | {"$t8", RTYPE_GP | 24}, \ | |
1687 | {"$t9", RTYPE_GP | 25}, \ | |
1688 | {"$k0", RTYPE_GP | 26}, \ | |
1689 | {"$kt0", RTYPE_GP | 26}, \ | |
1690 | {"$k1", RTYPE_GP | 27}, \ | |
1691 | {"$kt1", RTYPE_GP | 27}, \ | |
1692 | {"$gp", RTYPE_GP | 28}, \ | |
1693 | {"$sp", RTYPE_GP | 29}, \ | |
1694 | {"$s8", RTYPE_GP | 30}, \ | |
1695 | {"$fp", RTYPE_GP | 30}, \ | |
1696 | {"$ra", RTYPE_GP | 31} | |
1697 | ||
1698 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1699 | {"$pc", RTYPE_PC | 0} | |
1700 | ||
1701 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1702 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1703 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1704 | {"$v2", RTYPE_VEC | 2}, \ | |
1705 | {"$v3", RTYPE_VEC | 3}, \ | |
1706 | {"$v4", RTYPE_VEC | 4}, \ | |
1707 | {"$v5", RTYPE_VEC | 5}, \ | |
1708 | {"$v6", RTYPE_VEC | 6}, \ | |
1709 | {"$v7", RTYPE_VEC | 7}, \ | |
1710 | {"$v8", RTYPE_VEC | 8}, \ | |
1711 | {"$v9", RTYPE_VEC | 9}, \ | |
1712 | {"$v10", RTYPE_VEC | 10}, \ | |
1713 | {"$v11", RTYPE_VEC | 11}, \ | |
1714 | {"$v12", RTYPE_VEC | 12}, \ | |
1715 | {"$v13", RTYPE_VEC | 13}, \ | |
1716 | {"$v14", RTYPE_VEC | 14}, \ | |
1717 | {"$v15", RTYPE_VEC | 15}, \ | |
1718 | {"$v16", RTYPE_VEC | 16}, \ | |
1719 | {"$v17", RTYPE_VEC | 17}, \ | |
1720 | {"$v18", RTYPE_VEC | 18}, \ | |
1721 | {"$v19", RTYPE_VEC | 19}, \ | |
1722 | {"$v20", RTYPE_VEC | 20}, \ | |
1723 | {"$v21", RTYPE_VEC | 21}, \ | |
1724 | {"$v22", RTYPE_VEC | 22}, \ | |
1725 | {"$v23", RTYPE_VEC | 23}, \ | |
1726 | {"$v24", RTYPE_VEC | 24}, \ | |
1727 | {"$v25", RTYPE_VEC | 25}, \ | |
1728 | {"$v26", RTYPE_VEC | 26}, \ | |
1729 | {"$v27", RTYPE_VEC | 27}, \ | |
1730 | {"$v28", RTYPE_VEC | 28}, \ | |
1731 | {"$v29", RTYPE_VEC | 29}, \ | |
1732 | {"$v30", RTYPE_VEC | 30}, \ | |
1733 | {"$v31", RTYPE_VEC | 31} | |
1734 | ||
1735 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1736 | {"$ac0", RTYPE_ACC | 0}, \ | |
1737 | {"$ac1", RTYPE_ACC | 1}, \ | |
1738 | {"$ac2", RTYPE_ACC | 2}, \ | |
1739 | {"$ac3", RTYPE_ACC | 3} | |
1740 | ||
1741 | static const struct regname reg_names[] = { | |
1742 | GENERIC_REGISTER_NUMBERS, | |
1743 | FPU_REGISTER_NAMES, | |
1744 | FPU_CONDITION_CODE_NAMES, | |
1745 | COPROC_CONDITION_CODE_NAMES, | |
1746 | ||
1747 | /* The $txx registers depends on the abi, | |
1748 | these will be added later into the symbol table from | |
1749 | one of the tables below once mips_abi is set after | |
1750 | parsing of arguments from the command line. */ | |
1751 | SYMBOLIC_REGISTER_NAMES, | |
1752 | ||
1753 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1754 | MDMX_VECTOR_REGISTER_NAMES, | |
1755 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1756 | {0, 0} | |
1757 | }; | |
1758 | ||
1759 | static const struct regname reg_names_o32[] = { | |
1760 | O32_SYMBOLIC_REGISTER_NAMES, | |
1761 | {0, 0} | |
1762 | }; | |
1763 | ||
1764 | static const struct regname reg_names_n32n64[] = { | |
1765 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1766 | {0, 0} | |
1767 | }; | |
1768 | ||
1769 | static int | |
1770 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1771 | { | |
1772 | symbolS *symbolP; | |
1773 | char *e; | |
1774 | char save_c; | |
1775 | int reg = -1; | |
1776 | ||
1777 | /* Find end of name. */ | |
1778 | e = *s; | |
1779 | if (is_name_beginner (*e)) | |
1780 | ++e; | |
1781 | while (is_part_of_name (*e)) | |
1782 | ++e; | |
1783 | ||
1784 | /* Terminate name. */ | |
1785 | save_c = *e; | |
1786 | *e = '\0'; | |
1787 | ||
1788 | /* Look for a register symbol. */ | |
1789 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1790 | { | |
1791 | int r = S_GET_VALUE (symbolP); | |
1792 | if (r & types) | |
1793 | reg = r & RNUM_MASK; | |
1794 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1795 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1796 | reg = (r & RNUM_MASK) - 2; | |
1797 | } | |
1798 | /* Else see if this is a register defined in an itbl entry. */ | |
1799 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1800 | { | |
1801 | char *n = *s; | |
1802 | unsigned long r; | |
1803 | ||
1804 | if (*n == '$') | |
1805 | ++n; | |
1806 | if (itbl_get_reg_val (n, &r)) | |
1807 | reg = r & RNUM_MASK; | |
1808 | } | |
1809 | ||
1810 | /* Advance to next token if a register was recognised. */ | |
1811 | if (reg >= 0) | |
1812 | *s = e; | |
1813 | else if (types & RWARN) | |
20203fb9 | 1814 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
1815 | |
1816 | *e = save_c; | |
1817 | if (regnop) | |
1818 | *regnop = reg; | |
1819 | return reg >= 0; | |
1820 | } | |
1821 | ||
037b32b9 | 1822 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 1823 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
1824 | |
1825 | static bfd_boolean | |
f79e2745 | 1826 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
1827 | { |
1828 | int isa = mips_opts.isa; | |
1829 | int fp_s, fp_d; | |
1830 | ||
1831 | if (mips_opts.ase_mdmx) | |
1832 | isa |= INSN_MDMX; | |
1833 | if (mips_opts.ase_dsp) | |
1834 | isa |= INSN_DSP; | |
1835 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
1836 | isa |= INSN_DSP64; | |
1837 | if (mips_opts.ase_dspr2) | |
1838 | isa |= INSN_DSPR2; | |
1839 | if (mips_opts.ase_mt) | |
1840 | isa |= INSN_MT; | |
1841 | if (mips_opts.ase_mips3d) | |
1842 | isa |= INSN_MIPS3D; | |
1843 | if (mips_opts.ase_smartmips) | |
1844 | isa |= INSN_SMARTMIPS; | |
1845 | ||
b19e8a9b AN |
1846 | /* Don't accept instructions based on the ISA if the CPU does not implement |
1847 | all the coprocessor insns. */ | |
1848 | if (NO_ISA_COP (mips_opts.arch) | |
1849 | && COP_INSN (mo->pinfo)) | |
1850 | isa = 0; | |
1851 | ||
037b32b9 AN |
1852 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
1853 | return FALSE; | |
1854 | ||
1855 | /* Check whether the instruction or macro requires single-precision or | |
1856 | double-precision floating-point support. Note that this information is | |
1857 | stored differently in the opcode table for insns and macros. */ | |
1858 | if (mo->pinfo == INSN_MACRO) | |
1859 | { | |
1860 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
1861 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
1862 | } | |
1863 | else | |
1864 | { | |
1865 | fp_s = mo->pinfo & FP_S; | |
1866 | fp_d = mo->pinfo & FP_D; | |
1867 | } | |
1868 | ||
1869 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
1870 | return FALSE; | |
1871 | ||
1872 | if (fp_s && mips_opts.soft_float) | |
1873 | return FALSE; | |
1874 | ||
1875 | return TRUE; | |
1876 | } | |
1877 | ||
1878 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
1879 | selected ISA and architecture. */ | |
1880 | ||
1881 | static bfd_boolean | |
1882 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
1883 | { | |
1884 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
1885 | } | |
1886 | ||
707bfff6 TS |
1887 | /* This function is called once, at assembler startup time. It should set up |
1888 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1889 | |
252b5132 | 1890 | void |
17a2f251 | 1891 | md_begin (void) |
252b5132 | 1892 | { |
3994f87e | 1893 | const char *retval = NULL; |
156c2f8b | 1894 | int i = 0; |
252b5132 | 1895 | int broken = 0; |
1f25f5d3 | 1896 | |
0a44bf69 RS |
1897 | if (mips_pic != NO_PIC) |
1898 | { | |
1899 | if (g_switch_seen && g_switch_value != 0) | |
1900 | as_bad (_("-G may not be used in position-independent code")); | |
1901 | g_switch_value = 0; | |
1902 | } | |
1903 | ||
fef14a42 | 1904 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1905 | as_warn (_("Could not set architecture and machine")); |
1906 | ||
252b5132 RH |
1907 | op_hash = hash_new (); |
1908 | ||
1909 | for (i = 0; i < NUMOPCODES;) | |
1910 | { | |
1911 | const char *name = mips_opcodes[i].name; | |
1912 | ||
17a2f251 | 1913 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1914 | if (retval != NULL) |
1915 | { | |
1916 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1917 | mips_opcodes[i].name, retval); | |
1918 | /* Probably a memory allocation problem? Give up now. */ | |
1919 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1920 | } | |
1921 | do | |
1922 | { | |
1923 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1924 | { | |
1925 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1926 | broken = 1; | |
1e915849 RS |
1927 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1928 | { | |
1929 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
1930 | if (mips_fix_loongson2f_nop) |
1931 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
1932 | nop_insn.fixed_p = 1; |
1933 | } | |
252b5132 RH |
1934 | } |
1935 | ++i; | |
1936 | } | |
1937 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1938 | } | |
1939 | ||
1940 | mips16_op_hash = hash_new (); | |
1941 | ||
1942 | i = 0; | |
1943 | while (i < bfd_mips16_num_opcodes) | |
1944 | { | |
1945 | const char *name = mips16_opcodes[i].name; | |
1946 | ||
17a2f251 | 1947 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1948 | if (retval != NULL) |
1949 | as_fatal (_("internal: can't hash `%s': %s"), | |
1950 | mips16_opcodes[i].name, retval); | |
1951 | do | |
1952 | { | |
1953 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1954 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1955 | != mips16_opcodes[i].match)) | |
1956 | { | |
1957 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1958 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1959 | broken = 1; | |
1960 | } | |
1e915849 RS |
1961 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1962 | { | |
1963 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1964 | mips16_nop_insn.fixed_p = 1; | |
1965 | } | |
252b5132 RH |
1966 | ++i; |
1967 | } | |
1968 | while (i < bfd_mips16_num_opcodes | |
1969 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1970 | } | |
1971 | ||
1972 | if (broken) | |
1973 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1974 | ||
1975 | /* We add all the general register names to the symbol table. This | |
1976 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1977 | for (i = 0; reg_names[i].name; i++) |
1978 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 1979 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
1980 | &zero_address_frag)); |
1981 | if (HAVE_NEWABI) | |
1982 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1983 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 1984 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 1985 | &zero_address_frag)); |
707bfff6 TS |
1986 | else |
1987 | for (i = 0; reg_names_o32[i].name; i++) | |
1988 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 1989 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 1990 | &zero_address_frag)); |
6047c971 | 1991 | |
7d10b47d | 1992 | mips_no_prev_insn (); |
252b5132 RH |
1993 | |
1994 | mips_gprmask = 0; | |
1995 | mips_cprmask[0] = 0; | |
1996 | mips_cprmask[1] = 0; | |
1997 | mips_cprmask[2] = 0; | |
1998 | mips_cprmask[3] = 0; | |
1999 | ||
2000 | /* set the default alignment for the text section (2**2) */ | |
2001 | record_alignment (text_section, 2); | |
2002 | ||
4d0d148d | 2003 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2004 | |
707bfff6 | 2005 | #ifdef OBJ_ELF |
f43abd2b | 2006 | if (IS_ELF) |
252b5132 | 2007 | { |
0a44bf69 RS |
2008 | /* On a native system other than VxWorks, sections must be aligned |
2009 | to 16 byte boundaries. When configured for an embedded ELF | |
2010 | target, we don't bother. */ | |
c41e87e3 CF |
2011 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2012 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2013 | { |
2014 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2015 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2016 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2017 | } | |
2018 | ||
2019 | /* Create a .reginfo section for register masks and a .mdebug | |
2020 | section for debugging information. */ | |
2021 | { | |
2022 | segT seg; | |
2023 | subsegT subseg; | |
2024 | flagword flags; | |
2025 | segT sec; | |
2026 | ||
2027 | seg = now_seg; | |
2028 | subseg = now_subseg; | |
2029 | ||
2030 | /* The ABI says this section should be loaded so that the | |
2031 | running program can access it. However, we don't load it | |
2032 | if we are configured for an embedded target */ | |
2033 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2034 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2035 | flags |= SEC_ALLOC | SEC_LOAD; |
2036 | ||
316f5878 | 2037 | if (mips_abi != N64_ABI) |
252b5132 RH |
2038 | { |
2039 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2040 | ||
195325d2 TS |
2041 | bfd_set_section_flags (stdoutput, sec, flags); |
2042 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2043 | |
252b5132 | 2044 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2045 | } |
2046 | else | |
2047 | { | |
2048 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2049 | .reginfo section. */ | |
2050 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2051 | bfd_set_section_flags (stdoutput, sec, flags); |
2052 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2053 | |
252b5132 RH |
2054 | /* Set up the option header. */ |
2055 | { | |
2056 | Elf_Internal_Options opthdr; | |
2057 | char *f; | |
2058 | ||
2059 | opthdr.kind = ODK_REGINFO; | |
2060 | opthdr.size = (sizeof (Elf_External_Options) | |
2061 | + sizeof (Elf64_External_RegInfo)); | |
2062 | opthdr.section = 0; | |
2063 | opthdr.info = 0; | |
2064 | f = frag_more (sizeof (Elf_External_Options)); | |
2065 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2066 | (Elf_External_Options *) f); | |
2067 | ||
2068 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2069 | } | |
252b5132 RH |
2070 | } |
2071 | ||
2072 | if (ECOFF_DEBUGGING) | |
2073 | { | |
2074 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2075 | (void) bfd_set_section_flags (stdoutput, sec, | |
2076 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2077 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2078 | } | |
f43abd2b | 2079 | else if (mips_flag_pdr) |
ecb4347a DJ |
2080 | { |
2081 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2082 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2083 | SEC_READONLY | SEC_RELOC | |
2084 | | SEC_DEBUGGING); | |
2085 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2086 | } | |
252b5132 RH |
2087 | |
2088 | subseg_set (seg, subseg); | |
2089 | } | |
2090 | } | |
707bfff6 | 2091 | #endif /* OBJ_ELF */ |
252b5132 RH |
2092 | |
2093 | if (! ECOFF_DEBUGGING) | |
2094 | md_obj_begin (); | |
71400594 RS |
2095 | |
2096 | if (mips_fix_vr4120) | |
2097 | init_vr4120_conflicts (); | |
252b5132 RH |
2098 | } |
2099 | ||
2100 | void | |
17a2f251 | 2101 | md_mips_end (void) |
252b5132 RH |
2102 | { |
2103 | if (! ECOFF_DEBUGGING) | |
2104 | md_obj_end (); | |
2105 | } | |
2106 | ||
2107 | void | |
17a2f251 | 2108 | md_assemble (char *str) |
252b5132 RH |
2109 | { |
2110 | struct mips_cl_insn insn; | |
f6688943 TS |
2111 | bfd_reloc_code_real_type unused_reloc[3] |
2112 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2113 | |
2114 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2115 | imm2_expr.X_op = O_absent; |
252b5132 | 2116 | offset_expr.X_op = O_absent; |
f6688943 TS |
2117 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2118 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2119 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2120 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2121 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2122 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2123 | |
2124 | if (mips_opts.mips16) | |
2125 | mips16_ip (str, &insn); | |
2126 | else | |
2127 | { | |
2128 | mips_ip (str, &insn); | |
beae10d5 KH |
2129 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2130 | str, insn.insn_opcode)); | |
252b5132 RH |
2131 | } |
2132 | ||
2133 | if (insn_error) | |
2134 | { | |
2135 | as_bad ("%s `%s'", insn_error, str); | |
2136 | return; | |
2137 | } | |
2138 | ||
2139 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2140 | { | |
584892a6 | 2141 | macro_start (); |
252b5132 RH |
2142 | if (mips_opts.mips16) |
2143 | mips16_macro (&insn); | |
2144 | else | |
2145 | macro (&insn); | |
584892a6 | 2146 | macro_end (); |
252b5132 RH |
2147 | } |
2148 | else | |
2149 | { | |
2150 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 2151 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 2152 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2153 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2154 | else |
4d7206a2 | 2155 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2156 | } |
2157 | } | |
2158 | ||
738e5348 RS |
2159 | /* Convenience functions for abstracting away the differences between |
2160 | MIPS16 and non-MIPS16 relocations. */ | |
2161 | ||
2162 | static inline bfd_boolean | |
2163 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2164 | { | |
2165 | switch (reloc) | |
2166 | { | |
2167 | case BFD_RELOC_MIPS16_JMP: | |
2168 | case BFD_RELOC_MIPS16_GPREL: | |
2169 | case BFD_RELOC_MIPS16_GOT16: | |
2170 | case BFD_RELOC_MIPS16_CALL16: | |
2171 | case BFD_RELOC_MIPS16_HI16_S: | |
2172 | case BFD_RELOC_MIPS16_HI16: | |
2173 | case BFD_RELOC_MIPS16_LO16: | |
2174 | return TRUE; | |
2175 | ||
2176 | default: | |
2177 | return FALSE; | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | static inline bfd_boolean | |
2182 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2183 | { | |
2184 | return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16; | |
2185 | } | |
2186 | ||
2187 | static inline bfd_boolean | |
2188 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2189 | { | |
2190 | return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S; | |
2191 | } | |
2192 | ||
2193 | static inline bfd_boolean | |
2194 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2195 | { | |
2196 | return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16; | |
2197 | } | |
2198 | ||
5919d012 | 2199 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2200 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2201 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2202 | |
2203 | static inline bfd_boolean | |
17a2f251 | 2204 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2205 | { |
3b91255e | 2206 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2207 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2208 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2209 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2210 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2211 | } | |
2212 | ||
2213 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2214 | reloc_needs_lo_p. */ | |
2215 | ||
2216 | static inline bfd_reloc_code_real_type | |
2217 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2218 | { | |
2219 | return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16; | |
5919d012 RS |
2220 | } |
2221 | ||
2222 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2223 | relocation. */ | |
2224 | ||
2225 | static inline bfd_boolean | |
17a2f251 | 2226 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2227 | { |
2228 | return (fixp->fx_next != NULL | |
738e5348 | 2229 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2230 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2231 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2232 | } | |
2233 | ||
252b5132 RH |
2234 | /* See whether instruction IP reads register REG. CLASS is the type |
2235 | of register. */ | |
2236 | ||
2237 | static int | |
71400594 | 2238 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
96d56e9f | 2239 | enum mips_regclass regclass) |
252b5132 | 2240 | { |
96d56e9f | 2241 | if (regclass == MIPS16_REG) |
252b5132 | 2242 | { |
9c2799c2 | 2243 | gas_assert (mips_opts.mips16); |
252b5132 | 2244 | reg = mips16_to_32_reg_map[reg]; |
96d56e9f | 2245 | regclass = MIPS_GR_REG; |
252b5132 RH |
2246 | } |
2247 | ||
85b51719 | 2248 | /* Don't report on general register ZERO, since it never changes. */ |
96d56e9f | 2249 | if (regclass == MIPS_GR_REG && reg == ZERO) |
252b5132 RH |
2250 | return 0; |
2251 | ||
96d56e9f | 2252 | if (regclass == MIPS_FP_REG) |
252b5132 | 2253 | { |
9c2799c2 | 2254 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
2255 | /* If we are called with either $f0 or $f1, we must check $f0. |
2256 | This is not optimal, because it will introduce an unnecessary | |
2257 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2258 | need to distinguish reading both $f0 and $f1 or just one of | |
2259 | them. Note that we don't have to check the other way, | |
2260 | because there is no instruction that sets both $f0 and $f1 | |
2261 | and requires a delay. */ | |
2262 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2263 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2264 | == (reg &~ (unsigned) 1))) |
2265 | return 1; | |
2266 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2267 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2268 | == (reg &~ (unsigned) 1))) |
2269 | return 1; | |
2270 | } | |
2271 | else if (! mips_opts.mips16) | |
2272 | { | |
2273 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2274 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2275 | return 1; |
2276 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2277 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2278 | return 1; |
2279 | } | |
2280 | else | |
2281 | { | |
2282 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2283 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2284 | return 1; |
2285 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2286 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2287 | return 1; |
2288 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2289 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2290 | == reg)) |
2291 | return 1; | |
2292 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2293 | return 1; | |
2294 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2295 | return 1; | |
2296 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2297 | return 1; | |
2298 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2299 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2300 | return 1; |
2301 | } | |
2302 | ||
2303 | return 0; | |
2304 | } | |
2305 | ||
2306 | /* This function returns true if modifying a register requires a | |
2307 | delay. */ | |
2308 | ||
2309 | static int | |
17a2f251 | 2310 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2311 | { |
2312 | unsigned long prev_pinfo; | |
2313 | ||
47e39b9d | 2314 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2315 | if (! mips_opts.noreorder |
81912461 ILT |
2316 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2317 | && ! gpr_interlocks) | |
2318 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2319 | && ! cop_interlocks))) | |
252b5132 | 2320 | { |
81912461 ILT |
2321 | /* A load from a coprocessor or from memory. All load delays |
2322 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2323 | /* Itbl support may require additional care here. */ |
252b5132 | 2324 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2325 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2326 | return 1; |
2327 | } | |
2328 | ||
2329 | return 0; | |
2330 | } | |
2331 | ||
404a8071 RS |
2332 | /* Move all labels in insn_labels to the current insertion point. */ |
2333 | ||
2334 | static void | |
2335 | mips_move_labels (void) | |
2336 | { | |
a8dbcb85 | 2337 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2338 | struct insn_label_list *l; |
2339 | valueT val; | |
2340 | ||
a8dbcb85 | 2341 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2342 | { |
9c2799c2 | 2343 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2344 | symbol_set_frag (l->label, frag_now); |
2345 | val = (valueT) frag_now_fix (); | |
2346 | /* mips16 text labels are stored as odd. */ | |
2347 | if (mips_opts.mips16) | |
2348 | ++val; | |
2349 | S_SET_VALUE (l->label, val); | |
2350 | } | |
2351 | } | |
2352 | ||
5f0fe04b TS |
2353 | static bfd_boolean |
2354 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2355 | { | |
2356 | bfd_boolean linkonce = FALSE; | |
2357 | segT symseg = S_GET_SEGMENT (sym); | |
2358 | ||
2359 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2360 | { | |
2361 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2362 | linkonce = TRUE; | |
2363 | #ifdef OBJ_ELF | |
2364 | /* The GNU toolchain uses an extension for ELF: a section | |
2365 | beginning with the magic string .gnu.linkonce is a | |
2366 | linkonce section. */ | |
2367 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2368 | sizeof ".gnu.linkonce" - 1) == 0) | |
2369 | linkonce = TRUE; | |
2370 | #endif | |
2371 | } | |
2372 | return linkonce; | |
2373 | } | |
2374 | ||
252b5132 RH |
2375 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2376 | handle them specially, such as generating jalx instructions when | |
2377 | needed. We also make them odd for the duration of the assembly, in | |
2378 | order to generate the right sort of code. We will make them even | |
2379 | in the adjust_symtab routine, while leaving them marked. This is | |
2380 | convenient for the debugger and the disassembler. The linker knows | |
2381 | to make them odd again. */ | |
2382 | ||
2383 | static void | |
17a2f251 | 2384 | mips16_mark_labels (void) |
252b5132 | 2385 | { |
a8dbcb85 TS |
2386 | segment_info_type *si = seg_info (now_seg); |
2387 | struct insn_label_list *l; | |
252b5132 | 2388 | |
a8dbcb85 TS |
2389 | if (!mips_opts.mips16) |
2390 | return; | |
2391 | ||
2392 | for (l = si->label_list; l != NULL; l = l->next) | |
2393 | { | |
2394 | symbolS *label = l->label; | |
2395 | ||
2396 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2397 | if (IS_ELF) |
30c09090 | 2398 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
252b5132 | 2399 | #endif |
5f0fe04b TS |
2400 | if ((S_GET_VALUE (label) & 1) == 0 |
2401 | /* Don't adjust the address if the label is global or weak, or | |
2402 | in a link-once section, since we'll be emitting symbol reloc | |
2403 | references to it which will be patched up by the linker, and | |
2404 | the final value of the symbol may or may not be MIPS16. */ | |
2405 | && ! S_IS_WEAK (label) | |
2406 | && ! S_IS_EXTERNAL (label) | |
2407 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2408 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2409 | } |
2410 | } | |
2411 | ||
4d7206a2 RS |
2412 | /* End the current frag. Make it a variant frag and record the |
2413 | relaxation info. */ | |
2414 | ||
2415 | static void | |
2416 | relax_close_frag (void) | |
2417 | { | |
584892a6 | 2418 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2419 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2420 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2421 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2422 | ||
2423 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2424 | mips_relax.first_fixup = 0; | |
2425 | } | |
2426 | ||
2427 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2428 | See the comment above RELAX_ENCODE for more details. */ | |
2429 | ||
2430 | static void | |
2431 | relax_start (symbolS *symbol) | |
2432 | { | |
9c2799c2 | 2433 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2434 | mips_relax.sequence = 1; |
2435 | mips_relax.symbol = symbol; | |
2436 | } | |
2437 | ||
2438 | /* Start generating the second version of a relaxable sequence. | |
2439 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2440 | |
2441 | static void | |
4d7206a2 RS |
2442 | relax_switch (void) |
2443 | { | |
9c2799c2 | 2444 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2445 | mips_relax.sequence = 2; |
2446 | } | |
2447 | ||
2448 | /* End the current relaxable sequence. */ | |
2449 | ||
2450 | static void | |
2451 | relax_end (void) | |
2452 | { | |
9c2799c2 | 2453 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2454 | relax_close_frag (); |
2455 | mips_relax.sequence = 0; | |
2456 | } | |
2457 | ||
71400594 RS |
2458 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2459 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2460 | by VR4120 errata. */ | |
4d7206a2 | 2461 | |
71400594 RS |
2462 | static unsigned int |
2463 | classify_vr4120_insn (const char *name) | |
252b5132 | 2464 | { |
71400594 RS |
2465 | if (strncmp (name, "macc", 4) == 0) |
2466 | return FIX_VR4120_MACC; | |
2467 | if (strncmp (name, "dmacc", 5) == 0) | |
2468 | return FIX_VR4120_DMACC; | |
2469 | if (strncmp (name, "mult", 4) == 0) | |
2470 | return FIX_VR4120_MULT; | |
2471 | if (strncmp (name, "dmult", 5) == 0) | |
2472 | return FIX_VR4120_DMULT; | |
2473 | if (strstr (name, "div")) | |
2474 | return FIX_VR4120_DIV; | |
2475 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2476 | return FIX_VR4120_MTHILO; | |
2477 | return NUM_FIX_VR4120_CLASSES; | |
2478 | } | |
252b5132 | 2479 | |
ff239038 CM |
2480 | #define INSN_ERET 0x42000018 |
2481 | #define INSN_DERET 0x4200001f | |
2482 | ||
71400594 RS |
2483 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2484 | where INSN1 is the earlier instruction. Return the worst-case value | |
2485 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2486 | |
71400594 RS |
2487 | static unsigned int |
2488 | insns_between (const struct mips_cl_insn *insn1, | |
2489 | const struct mips_cl_insn *insn2) | |
2490 | { | |
2491 | unsigned long pinfo1, pinfo2; | |
2492 | ||
2493 | /* This function needs to know which pinfo flags are set for INSN2 | |
2494 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2495 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2496 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2497 | pinfo1 = insn1->insn_mo->pinfo; | |
2498 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2499 | |
71400594 RS |
2500 | #define INSN2_USES_REG(REG, CLASS) \ |
2501 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2502 | ||
2503 | /* For most targets, write-after-read dependencies on the HI and LO | |
2504 | registers must be separated by at least two instructions. */ | |
2505 | if (!hilo_interlocks) | |
252b5132 | 2506 | { |
71400594 RS |
2507 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2508 | return 2; | |
2509 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2510 | return 2; | |
2511 | } | |
2512 | ||
2513 | /* If we're working around r7000 errata, there must be two instructions | |
2514 | between an mfhi or mflo and any instruction that uses the result. */ | |
2515 | if (mips_7000_hilo_fix | |
2516 | && MF_HILO_INSN (pinfo1) | |
2517 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2518 | return 2; | |
2519 | ||
ff239038 CM |
2520 | /* If we're working around 24K errata, one instruction is required |
2521 | if an ERET or DERET is followed by a branch instruction. */ | |
2522 | if (mips_fix_24k) | |
2523 | { | |
2524 | if (insn1->insn_opcode == INSN_ERET | |
2525 | || insn1->insn_opcode == INSN_DERET) | |
2526 | { | |
2527 | if (insn2 == NULL | |
2528 | || insn2->insn_opcode == INSN_ERET | |
2529 | || insn2->insn_opcode == INSN_DERET | |
2530 | || (insn2->insn_mo->pinfo | |
2531 | & (INSN_UNCOND_BRANCH_DELAY | |
2532 | | INSN_COND_BRANCH_DELAY | |
2533 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
2534 | return 1; | |
2535 | } | |
2536 | } | |
2537 | ||
71400594 RS |
2538 | /* If working around VR4120 errata, check for combinations that need |
2539 | a single intervening instruction. */ | |
2540 | if (mips_fix_vr4120) | |
2541 | { | |
2542 | unsigned int class1, class2; | |
252b5132 | 2543 | |
71400594 RS |
2544 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2545 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2546 | { |
71400594 RS |
2547 | if (insn2 == NULL) |
2548 | return 1; | |
2549 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2550 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2551 | return 1; | |
252b5132 | 2552 | } |
71400594 RS |
2553 | } |
2554 | ||
2555 | if (!mips_opts.mips16) | |
2556 | { | |
2557 | /* Check for GPR or coprocessor load delays. All such delays | |
2558 | are on the RT register. */ | |
2559 | /* Itbl support may require additional care here. */ | |
2560 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2561 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2562 | { |
71400594 RS |
2563 | know (pinfo1 & INSN_WRITE_GPR_T); |
2564 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2565 | return 1; | |
2566 | } | |
2567 | ||
2568 | /* Check for generic coprocessor hazards. | |
2569 | ||
2570 | This case is not handled very well. There is no special | |
2571 | knowledge of CP0 handling, and the coprocessors other than | |
2572 | the floating point unit are not distinguished at all. */ | |
2573 | /* Itbl support may require additional care here. FIXME! | |
2574 | Need to modify this to include knowledge about | |
2575 | user specified delays! */ | |
2576 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2577 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2578 | { | |
2579 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2580 | register. There must be a one instruction delay before INSN2 | |
2581 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2582 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2583 | { |
71400594 RS |
2584 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2585 | return 1; | |
252b5132 | 2586 | } |
71400594 | 2587 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2588 | { |
71400594 RS |
2589 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2590 | return 1; | |
252b5132 RH |
2591 | } |
2592 | else | |
2593 | { | |
71400594 RS |
2594 | /* Read-after-write dependencies on the control registers |
2595 | require a two-instruction gap. */ | |
2596 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2597 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2598 | return 2; | |
2599 | ||
2600 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2601 | also a coprocessor instruction, assume there must be | |
2602 | a one instruction gap. */ | |
2603 | if (pinfo2 & INSN_COP) | |
2604 | return 1; | |
252b5132 RH |
2605 | } |
2606 | } | |
6b76fefe | 2607 | |
71400594 RS |
2608 | /* Check for read-after-write dependencies on the coprocessor |
2609 | control registers in cases where INSN1 does not need a general | |
2610 | coprocessor delay. This means that INSN1 is a floating point | |
2611 | comparison instruction. */ | |
2612 | /* Itbl support may require additional care here. */ | |
2613 | else if (!cop_interlocks | |
2614 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2615 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2616 | return 1; | |
2617 | } | |
6b76fefe | 2618 | |
71400594 | 2619 | #undef INSN2_USES_REG |
6b76fefe | 2620 | |
71400594 RS |
2621 | return 0; |
2622 | } | |
6b76fefe | 2623 | |
7d8e00cf RS |
2624 | /* Return the number of nops that would be needed to work around the |
2625 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
91d6fa6a | 2626 | the MAX_VR4130_NOPS instructions described by HIST. */ |
7d8e00cf RS |
2627 | |
2628 | static int | |
91d6fa6a | 2629 | nops_for_vr4130 (const struct mips_cl_insn *hist, |
7d8e00cf RS |
2630 | const struct mips_cl_insn *insn) |
2631 | { | |
2632 | int i, j, reg; | |
2633 | ||
2634 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2635 | are not affected by the errata. */ | |
2636 | if (insn != 0 | |
2637 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2638 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2639 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2640 | return 0; | |
2641 | ||
2642 | /* Search for the first MFLO or MFHI. */ | |
2643 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 2644 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
2645 | { |
2646 | /* Extract the destination register. */ | |
2647 | if (mips_opts.mips16) | |
91d6fa6a | 2648 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])]; |
7d8e00cf | 2649 | else |
91d6fa6a | 2650 | reg = EXTRACT_OPERAND (RD, hist[i]); |
7d8e00cf RS |
2651 | |
2652 | /* No nops are needed if INSN reads that register. */ | |
2653 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2654 | return 0; | |
2655 | ||
2656 | /* ...or if any of the intervening instructions do. */ | |
2657 | for (j = 0; j < i; j++) | |
91d6fa6a | 2658 | if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG)) |
7d8e00cf RS |
2659 | return 0; |
2660 | ||
2661 | return MAX_VR4130_NOPS - i; | |
2662 | } | |
2663 | return 0; | |
2664 | } | |
2665 | ||
71400594 | 2666 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a NC |
2667 | immediately followed the MAX_NOPS instructions given by HIST, |
2668 | where HIST[0] is the most recent instruction. If INSN is null, | |
71400594 | 2669 | return the worse-case number of nops for any instruction. */ |
bdaaa2e1 | 2670 | |
71400594 | 2671 | static int |
91d6fa6a | 2672 | nops_for_insn (const struct mips_cl_insn *hist, |
71400594 RS |
2673 | const struct mips_cl_insn *insn) |
2674 | { | |
2675 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2676 | |
71400594 | 2677 | nops = 0; |
7d8e00cf | 2678 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
65b02341 | 2679 | { |
91d6fa6a | 2680 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
2681 | if (tmp_nops > nops) |
2682 | nops = tmp_nops; | |
2683 | } | |
7d8e00cf RS |
2684 | |
2685 | if (mips_fix_vr4130) | |
2686 | { | |
91d6fa6a | 2687 | tmp_nops = nops_for_vr4130 (hist, insn); |
7d8e00cf RS |
2688 | if (tmp_nops > nops) |
2689 | nops = tmp_nops; | |
2690 | } | |
2691 | ||
71400594 RS |
2692 | return nops; |
2693 | } | |
252b5132 | 2694 | |
71400594 | 2695 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 2696 | might be added to HIST. Return the largest number of nops that |
71400594 | 2697 | would be needed after the extended sequence. */ |
252b5132 | 2698 | |
71400594 | 2699 | static int |
91d6fa6a | 2700 | nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...) |
71400594 RS |
2701 | { |
2702 | va_list args; | |
2703 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2704 | struct mips_cl_insn *cursor; | |
2705 | int nops; | |
2706 | ||
91d6fa6a | 2707 | va_start (args, hist); |
71400594 | 2708 | cursor = buffer + num_insns; |
91d6fa6a | 2709 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
2710 | while (cursor > buffer) |
2711 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2712 | ||
2713 | nops = nops_for_insn (buffer, NULL); | |
2714 | va_end (args); | |
2715 | return nops; | |
2716 | } | |
252b5132 | 2717 | |
71400594 RS |
2718 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2719 | worst-case delay for the branch target. */ | |
252b5132 | 2720 | |
71400594 | 2721 | static int |
91d6fa6a | 2722 | nops_for_insn_or_target (const struct mips_cl_insn *hist, |
71400594 RS |
2723 | const struct mips_cl_insn *insn) |
2724 | { | |
2725 | int nops, tmp_nops; | |
60b63b72 | 2726 | |
91d6fa6a | 2727 | nops = nops_for_insn (hist, insn); |
71400594 RS |
2728 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
2729 | | INSN_COND_BRANCH_DELAY | |
2730 | | INSN_COND_BRANCH_LIKELY)) | |
2731 | { | |
91d6fa6a | 2732 | tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN); |
71400594 RS |
2733 | if (tmp_nops > nops) |
2734 | nops = tmp_nops; | |
2735 | } | |
9a2c7088 MR |
2736 | else if (mips_opts.mips16 |
2737 | && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2738 | | MIPS16_INSN_COND_BRANCH))) | |
71400594 | 2739 | { |
91d6fa6a | 2740 | tmp_nops = nops_for_sequence (1, hist, insn); |
71400594 RS |
2741 | if (tmp_nops > nops) |
2742 | nops = tmp_nops; | |
2743 | } | |
2744 | return nops; | |
2745 | } | |
2746 | ||
c67a084a NC |
2747 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
2748 | ||
2749 | static void | |
2750 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
2751 | { | |
2752 | if (strcmp (ip->insn_mo->name, "nop") == 0) | |
2753 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
2754 | } | |
2755 | ||
2756 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
2757 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
2758 | ||
2759 | static void | |
2760 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
2761 | { | |
2762 | if (strcmp (ip->insn_mo->name, "j") == 0 | |
2763 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
2764 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
2765 | { | |
2766 | int sreg; | |
2767 | expressionS ep; | |
2768 | ||
2769 | if (! mips_opts.at) | |
2770 | return; | |
2771 | ||
2772 | sreg = EXTRACT_OPERAND (RS, *ip); | |
2773 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) | |
2774 | return; | |
2775 | ||
2776 | ep.X_op = O_constant; | |
2777 | ep.X_add_number = 0xcfff0000; | |
2778 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
2779 | ep.X_add_number = 0xffff; | |
2780 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
2781 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
2782 | } | |
2783 | } | |
2784 | ||
2785 | static void | |
2786 | fix_loongson2f (struct mips_cl_insn * ip) | |
2787 | { | |
2788 | if (mips_fix_loongson2f_nop) | |
2789 | fix_loongson2f_nop (ip); | |
2790 | ||
2791 | if (mips_fix_loongson2f_jump) | |
2792 | fix_loongson2f_jump (ip); | |
2793 | } | |
2794 | ||
71400594 RS |
2795 | /* Output an instruction. IP is the instruction information. |
2796 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2797 | RELOC_TYPE. */ | |
2798 | ||
2799 | static void | |
2800 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2801 | bfd_reloc_code_real_type *reloc_type) | |
2802 | { | |
3994f87e | 2803 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2804 | relax_stateT prev_insn_frag_type = 0; |
2805 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2806 | segment_info_type *si = seg_info (now_seg); |
71400594 | 2807 | |
c67a084a NC |
2808 | if (mips_fix_loongson2f) |
2809 | fix_loongson2f (ip); | |
2810 | ||
71400594 RS |
2811 | /* Mark instruction labels in mips16 mode. */ |
2812 | mips16_mark_labels (); | |
2813 | ||
2814 | prev_pinfo = history[0].insn_mo->pinfo; | |
2815 | pinfo = ip->insn_mo->pinfo; | |
2816 | ||
2817 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2818 | { | |
2819 | /* There are a lot of optimizations we could do that we don't. | |
2820 | In particular, we do not, in general, reorder instructions. | |
2821 | If you use gcc with optimization, it will reorder | |
2822 | instructions and generally do much more optimization then we | |
2823 | do here; repeating all that work in the assembler would only | |
2824 | benefit hand written assembly code, and does not seem worth | |
2825 | it. */ | |
2826 | int nops = (mips_optimize == 0 | |
2827 | ? nops_for_insn (history, NULL) | |
2828 | : nops_for_insn_or_target (history, ip)); | |
2829 | if (nops > 0) | |
252b5132 RH |
2830 | { |
2831 | fragS *old_frag; | |
2832 | unsigned long old_frag_offset; | |
2833 | int i; | |
252b5132 RH |
2834 | |
2835 | old_frag = frag_now; | |
2836 | old_frag_offset = frag_now_fix (); | |
2837 | ||
2838 | for (i = 0; i < nops; i++) | |
2839 | emit_nop (); | |
2840 | ||
2841 | if (listing) | |
2842 | { | |
2843 | listing_prev_line (); | |
2844 | /* We may be at the start of a variant frag. In case we | |
2845 | are, make sure there is enough space for the frag | |
2846 | after the frags created by listing_prev_line. The | |
2847 | argument to frag_grow here must be at least as large | |
2848 | as the argument to all other calls to frag_grow in | |
2849 | this file. We don't have to worry about being in the | |
2850 | middle of a variant frag, because the variants insert | |
2851 | all needed nop instructions themselves. */ | |
2852 | frag_grow (40); | |
2853 | } | |
2854 | ||
404a8071 | 2855 | mips_move_labels (); |
252b5132 RH |
2856 | |
2857 | #ifndef NO_ECOFF_DEBUGGING | |
2858 | if (ECOFF_DEBUGGING) | |
2859 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2860 | #endif | |
2861 | } | |
71400594 RS |
2862 | } |
2863 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2864 | { | |
2865 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2866 | int nops = nops_for_insn_or_target (history, ip); | |
9c2799c2 | 2867 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 2868 | |
71400594 RS |
2869 | /* Enforce NOPS as a minimum. */ |
2870 | if (nops > prev_nop_frag_required) | |
2871 | prev_nop_frag_required = nops; | |
252b5132 | 2872 | |
71400594 RS |
2873 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2874 | { | |
2875 | /* Settle for the current number of nops. Update the history | |
2876 | accordingly (for the benefit of any future .set reorder code). */ | |
2877 | prev_nop_frag = NULL; | |
2878 | insert_into_history (prev_nop_frag_since, | |
2879 | prev_nop_frag_holds, NOP_INSN); | |
2880 | } | |
2881 | else | |
2882 | { | |
2883 | /* Allow this instruction to replace one of the nops that was | |
2884 | tentatively added to prev_nop_frag. */ | |
2885 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2886 | prev_nop_frag_holds--; | |
2887 | prev_nop_frag_since++; | |
252b5132 RH |
2888 | } |
2889 | } | |
2890 | ||
58e2ea4d MR |
2891 | #ifdef OBJ_ELF |
2892 | /* The value passed to dwarf2_emit_insn is the distance between | |
2893 | the beginning of the current instruction and the address that | |
2894 | should be recorded in the debug tables. For MIPS16 debug info | |
2895 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2896 | address higher by one than the current. */ | |
2897 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2898 | #endif | |
2899 | ||
895921c9 | 2900 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2901 | if (history[0].frag) |
2902 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2903 | |
4d7206a2 | 2904 | if (address_expr |
0b25d3e6 | 2905 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2906 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2907 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2908 | && mips_relax_branch | |
2909 | /* Don't try branch relaxation within .set nomacro, or within | |
2910 | .set noat if we use $at for PIC computations. If it turns | |
2911 | out that the branch was out-of-range, we'll get an error. */ | |
2912 | && !mips_opts.warn_about_macros | |
741fe287 | 2913 | && (mips_opts.at || mips_pic == NO_PIC) |
4a6a3df4 AO |
2914 | && !mips_opts.mips16) |
2915 | { | |
895921c9 | 2916 | relaxed_branch = TRUE; |
1e915849 RS |
2917 | add_relaxed_insn (ip, (relaxed_branch_length |
2918 | (NULL, NULL, | |
2919 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2920 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2921 | : 0)), 4, | |
2922 | RELAX_BRANCH_ENCODE | |
2923 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2924 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2925 | pinfo & INSN_WRITE_GPR_31, | |
2926 | 0), | |
2927 | address_expr->X_add_symbol, | |
2928 | address_expr->X_add_number); | |
4a6a3df4 AO |
2929 | *reloc_type = BFD_RELOC_UNUSED; |
2930 | } | |
2931 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2932 | { |
2933 | /* We need to set up a variant frag. */ | |
9c2799c2 | 2934 | gas_assert (mips_opts.mips16 && address_expr != NULL); |
1e915849 RS |
2935 | add_relaxed_insn (ip, 4, 0, |
2936 | RELAX_MIPS16_ENCODE | |
2937 | (*reloc_type - BFD_RELOC_UNUSED, | |
2938 | mips16_small, mips16_ext, | |
2939 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2940 | history[0].mips16_absolute_jump_p), | |
2941 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2942 | } |
252b5132 RH |
2943 | else if (mips_opts.mips16 |
2944 | && ! ip->use_extend | |
f6688943 | 2945 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2946 | { |
b8ee1a6e DU |
2947 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2948 | /* Make sure there is enough room to swap this instruction with | |
2949 | a following jump instruction. */ | |
2950 | frag_grow (6); | |
1e915849 | 2951 | add_fixed_insn (ip); |
252b5132 RH |
2952 | } |
2953 | else | |
2954 | { | |
2955 | if (mips_opts.mips16 | |
2956 | && mips_opts.noreorder | |
2957 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2958 | as_warn (_("extended instruction in delay slot")); | |
2959 | ||
4d7206a2 RS |
2960 | if (mips_relax.sequence) |
2961 | { | |
2962 | /* If we've reached the end of this frag, turn it into a variant | |
2963 | frag and record the information for the instructions we've | |
2964 | written so far. */ | |
2965 | if (frag_room () < 4) | |
2966 | relax_close_frag (); | |
2967 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2968 | } | |
2969 | ||
584892a6 RS |
2970 | if (mips_relax.sequence != 2) |
2971 | mips_macro_warning.sizes[0] += 4; | |
2972 | if (mips_relax.sequence != 1) | |
2973 | mips_macro_warning.sizes[1] += 4; | |
2974 | ||
1e915849 RS |
2975 | if (mips_opts.mips16) |
2976 | { | |
2977 | ip->fixed_p = 1; | |
2978 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2979 | } | |
2980 | add_fixed_insn (ip); | |
252b5132 RH |
2981 | } |
2982 | ||
01a3f561 | 2983 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2984 | { |
2985 | if (address_expr->X_op == O_constant) | |
2986 | { | |
f17c130b | 2987 | unsigned int tmp; |
f6688943 TS |
2988 | |
2989 | switch (*reloc_type) | |
252b5132 RH |
2990 | { |
2991 | case BFD_RELOC_32: | |
2992 | ip->insn_opcode |= address_expr->X_add_number; | |
2993 | break; | |
2994 | ||
f6688943 | 2995 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2996 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2997 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2998 | break; |
2999 | ||
3000 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
3001 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
3002 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3003 | break; |
3004 | ||
3005 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
3006 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
3007 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
3008 | break; |
3009 | ||
3010 | case BFD_RELOC_HI16: | |
3011 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
3012 | break; | |
3013 | ||
01a3f561 | 3014 | case BFD_RELOC_UNUSED: |
252b5132 | 3015 | case BFD_RELOC_LO16: |
ed6fb7bd | 3016 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
3017 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
3018 | break; | |
3019 | ||
3020 | case BFD_RELOC_MIPS_JMP: | |
3021 | if ((address_expr->X_add_number & 3) != 0) | |
3022 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3023 | (unsigned long) address_expr->X_add_number); | |
3024 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
3025 | break; | |
3026 | ||
3027 | case BFD_RELOC_MIPS16_JMP: | |
3028 | if ((address_expr->X_add_number & 3) != 0) | |
3029 | as_bad (_("jump to misaligned address (0x%lx)"), | |
3030 | (unsigned long) address_expr->X_add_number); | |
3031 | ip->insn_opcode |= | |
3032 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
3033 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
3034 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
3035 | break; | |
3036 | ||
252b5132 | 3037 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
3038 | if ((address_expr->X_add_number & 3) != 0) |
3039 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3040 | (unsigned long) address_expr->X_add_number); | |
3041 | if (mips_relax_branch) | |
3042 | goto need_reloc; | |
3043 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
3044 | as_bad (_("branch address range overflow (0x%lx)"), | |
3045 | (unsigned long) address_expr->X_add_number); | |
3046 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
3047 | break; | |
252b5132 RH |
3048 | |
3049 | default: | |
3050 | internalError (); | |
3051 | } | |
3052 | } | |
01a3f561 | 3053 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 3054 | need_reloc: |
4d7206a2 RS |
3055 | { |
3056 | reloc_howto_type *howto; | |
3057 | int i; | |
34ce925e | 3058 | |
4d7206a2 RS |
3059 | /* In a compound relocation, it is the final (outermost) |
3060 | operator that determines the relocated field. */ | |
3061 | for (i = 1; i < 3; i++) | |
3062 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
3063 | break; | |
34ce925e | 3064 | |
4d7206a2 | 3065 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
23fce1e3 NC |
3066 | if (howto == NULL) |
3067 | { | |
3068 | /* To reproduce this failure try assembling gas/testsuites/ | |
3069 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
3070 | assembler. */ | |
3071 | as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]); | |
3072 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); | |
3073 | } | |
3074 | ||
1e915849 RS |
3075 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
3076 | bfd_get_reloc_size (howto), | |
3077 | address_expr, | |
3078 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
3079 | reloc_type[0]); | |
4d7206a2 | 3080 | |
b314ec0e RS |
3081 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
3082 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
3083 | && ip->fixp[0]->fx_addsy) | |
3084 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
3085 | ||
4d7206a2 RS |
3086 | /* These relocations can have an addend that won't fit in |
3087 | 4 octets for 64bit assembly. */ | |
3088 | if (HAVE_64BIT_GPRS | |
3089 | && ! howto->partial_inplace | |
3090 | && (reloc_type[0] == BFD_RELOC_16 | |
3091 | || reloc_type[0] == BFD_RELOC_32 | |
3092 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4d7206a2 RS |
3093 | || reloc_type[0] == BFD_RELOC_GPREL16 |
3094 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
3095 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
3096 | || reloc_type[0] == BFD_RELOC_64 | |
3097 | || reloc_type[0] == BFD_RELOC_CTOR | |
3098 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
3099 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
3100 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
3101 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
3102 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
3103 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
3104 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
738e5348 RS |
3105 | || hi16_reloc_p (reloc_type[0]) |
3106 | || lo16_reloc_p (reloc_type[0]))) | |
1e915849 | 3107 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
3108 | |
3109 | if (mips_relax.sequence) | |
3110 | { | |
3111 | if (mips_relax.first_fixup == 0) | |
1e915849 | 3112 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
3113 | } |
3114 | else if (reloc_needs_lo_p (*reloc_type)) | |
3115 | { | |
3116 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 3117 | |
4d7206a2 RS |
3118 | /* Reuse the last entry if it already has a matching %lo. */ |
3119 | hi_fixup = mips_hi_fixup_list; | |
3120 | if (hi_fixup == 0 | |
3121 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
3122 | { | |
3123 | hi_fixup = ((struct mips_hi_fixup *) | |
3124 | xmalloc (sizeof (struct mips_hi_fixup))); | |
3125 | hi_fixup->next = mips_hi_fixup_list; | |
3126 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 3127 | } |
1e915849 | 3128 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
3129 | hi_fixup->seg = now_seg; |
3130 | } | |
f6688943 | 3131 | |
4d7206a2 RS |
3132 | /* Add fixups for the second and third relocations, if given. |
3133 | Note that the ABI allows the second relocation to be | |
3134 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
3135 | moment we only use RSS_UNDEF, but we could add support | |
3136 | for the others if it ever becomes necessary. */ | |
3137 | for (i = 1; i < 3; i++) | |
3138 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
3139 | { | |
1e915849 RS |
3140 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
3141 | ip->fixp[0]->fx_size, NULL, 0, | |
3142 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
3143 | |
3144 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
3145 | ip->fixp[0]->fx_tcbit = 1; |
3146 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 3147 | } |
252b5132 RH |
3148 | } |
3149 | } | |
1e915849 | 3150 | install_insn (ip); |
252b5132 RH |
3151 | |
3152 | /* Update the register mask information. */ | |
3153 | if (! mips_opts.mips16) | |
3154 | { | |
3155 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3156 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 3157 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 3158 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 3159 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 3160 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 3161 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 3162 | mips_gprmask |= 1 << RA; |
252b5132 | 3163 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 3164 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 3165 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 3166 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 3167 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 3168 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 3169 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 3170 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
3171 | if (pinfo & INSN_COP) |
3172 | { | |
bdaaa2e1 KH |
3173 | /* We don't keep enough information to sort these cases out. |
3174 | The itbl support does keep this information however, although | |
3175 | we currently don't support itbl fprmats as part of the cop | |
3176 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
3177 | } |
3178 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 3179 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
3180 | } |
3181 | else | |
3182 | { | |
3183 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 3184 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 3185 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 3186 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 3187 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 3188 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
3189 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
3190 | mips_gprmask |= 1 << TREG; | |
3191 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
3192 | mips_gprmask |= 1 << SP; | |
3193 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
3194 | mips_gprmask |= 1 << RA; | |
3195 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3196 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3197 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 3198 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 3199 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 3200 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
3201 | } |
3202 | ||
4d7206a2 | 3203 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
3204 | { |
3205 | /* Filling the branch delay slot is more complex. We try to | |
3206 | switch the branch with the previous instruction, which we can | |
3207 | do if the previous instruction does not set up a condition | |
3208 | that the branch tests and if the branch is not itself the | |
3209 | target of any branch. */ | |
3210 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3211 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
3212 | { | |
3213 | if (mips_optimize < 2 | |
3214 | /* If we have seen .set volatile or .set nomove, don't | |
3215 | optimize. */ | |
3216 | || mips_opts.nomove != 0 | |
a38419a5 RS |
3217 | /* We can't swap if the previous instruction's position |
3218 | is fixed. */ | |
3219 | || history[0].fixed_p | |
252b5132 RH |
3220 | /* If the previous previous insn was in a .set |
3221 | noreorder, we can't swap. Actually, the MIPS | |
3222 | assembler will swap in this situation. However, gcc | |
3223 | configured -with-gnu-as will generate code like | |
3224 | .set noreorder | |
3225 | lw $4,XXX | |
3226 | .set reorder | |
3227 | INSN | |
3228 | bne $4,$0,foo | |
3229 | in which we can not swap the bne and INSN. If gcc is | |
3230 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 3231 | .set pseudo-ops. */ |
47e39b9d | 3232 | || history[1].noreorder_p |
252b5132 RH |
3233 | /* If the branch is itself the target of a branch, we |
3234 | can not swap. We cheat on this; all we check for is | |
3235 | whether there is a label on this instruction. If | |
3236 | there are any branches to anything other than a | |
3237 | label, users must use .set noreorder. */ | |
a8dbcb85 | 3238 | || si->label_list != NULL |
895921c9 MR |
3239 | /* If the previous instruction is in a variant frag |
3240 | other than this branch's one, we cannot do the swap. | |
3241 | This does not apply to the mips16, which uses variant | |
3242 | frags for different purposes. */ | |
252b5132 | 3243 | || (! mips_opts.mips16 |
895921c9 | 3244 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
3245 | /* Check for conflicts between the branch and the instructions |
3246 | before the candidate delay slot. */ | |
3247 | || nops_for_insn (history + 1, ip) > 0 | |
3248 | /* Check for conflicts between the swapped sequence and the | |
3249 | target of the branch. */ | |
3250 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
3251 | /* We do not swap with a trap instruction, since it |
3252 | complicates trap handlers to have the trap | |
3253 | instruction be in a delay slot. */ | |
3254 | || (prev_pinfo & INSN_TRAP) | |
3255 | /* If the branch reads a register that the previous | |
3256 | instruction sets, we can not swap. */ | |
3257 | || (! mips_opts.mips16 | |
3258 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 3259 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
3260 | MIPS_GR_REG)) |
3261 | || (! mips_opts.mips16 | |
3262 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 3263 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
3264 | MIPS_GR_REG)) |
3265 | || (mips_opts.mips16 | |
3266 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
3267 | && (insn_uses_reg |
3268 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
3269 | MIPS16_REG))) | |
252b5132 | 3270 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
3271 | && (insn_uses_reg |
3272 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
3273 | MIPS16_REG))) | |
252b5132 | 3274 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
3275 | && (insn_uses_reg |
3276 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
3277 | MIPS16_REG))) | |
252b5132 RH |
3278 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
3279 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3280 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3281 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3282 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3283 | && insn_uses_reg (ip, | |
47e39b9d RS |
3284 | MIPS16OP_EXTRACT_REG32R |
3285 | (history[0].insn_opcode), | |
252b5132 RH |
3286 | MIPS_GR_REG)))) |
3287 | /* If the branch writes a register that the previous | |
3288 | instruction sets, we can not swap (we know that | |
3289 | branches write only to RD or to $31). */ | |
3290 | || (! mips_opts.mips16 | |
3291 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3292 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3293 | && (EXTRACT_OPERAND (RT, history[0]) |
3294 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3295 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3296 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3297 | || (! mips_opts.mips16 |
3298 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3299 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3300 | && (EXTRACT_OPERAND (RD, history[0]) |
3301 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3302 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3303 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3304 | || (mips_opts.mips16 |
3305 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3306 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3307 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3308 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3309 | == RA)))) |
3310 | /* If the branch writes a register that the previous | |
3311 | instruction reads, we can not swap (we know that | |
3312 | branches only write to RD or to $31). */ | |
3313 | || (! mips_opts.mips16 | |
3314 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3315 | && insn_uses_reg (&history[0], |
bf12938e | 3316 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3317 | MIPS_GR_REG)) |
3318 | || (! mips_opts.mips16 | |
3319 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3320 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3321 | || (mips_opts.mips16 |
3322 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3323 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3324 | /* If one instruction sets a condition code and the |
3325 | other one uses a condition code, we can not swap. */ | |
3326 | || ((pinfo & INSN_READ_COND_CODE) | |
3327 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3328 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3329 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3330 | /* If the previous instruction uses the PC, we can not | |
3331 | swap. */ | |
3332 | || (mips_opts.mips16 | |
3333 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3334 | /* If the previous instruction had a fixup in mips16 |
3335 | mode, we can not swap. This normally means that the | |
3336 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3337 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3338 | /* If the previous instruction is a sync, sync.l, or |
3339 | sync.p, we can not swap. */ | |
6a32d874 CM |
3340 | || (prev_pinfo & INSN_SYNC) |
3341 | /* If the previous instruction is an ERET or | |
3342 | DERET, avoid the swap. */ | |
3343 | || (history[0].insn_opcode == INSN_ERET) | |
3344 | || (history[0].insn_opcode == INSN_DERET)) | |
252b5132 | 3345 | { |
29024861 DU |
3346 | if (mips_opts.mips16 |
3347 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3348 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3349 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3350 | { |
3351 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3352 | ip->insn_opcode |= 0x0080; | |
3353 | install_insn (ip); | |
3354 | insert_into_history (0, 1, ip); | |
3355 | } | |
3356 | else | |
3357 | { | |
3358 | /* We could do even better for unconditional branches to | |
3359 | portions of this object file; we could pick up the | |
3360 | instruction at the destination, put it in the delay | |
3361 | slot, and bump the destination address. */ | |
3362 | insert_into_history (0, 1, ip); | |
3363 | emit_nop (); | |
3364 | } | |
3365 | ||
dd22970f ILT |
3366 | if (mips_relax.sequence) |
3367 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3368 | } |
3369 | else | |
3370 | { | |
3371 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3372 | struct mips_cl_insn delay = history[0]; |
3373 | if (mips_opts.mips16) | |
252b5132 | 3374 | { |
b8ee1a6e DU |
3375 | know (delay.frag == ip->frag); |
3376 | move_insn (ip, delay.frag, delay.where); | |
3377 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3378 | } |
3379 | else if (relaxed_branch) | |
3380 | { | |
3381 | /* Add the delay slot instruction to the end of the | |
3382 | current frag and shrink the fixed part of the | |
3383 | original frag. If the branch occupies the tail of | |
3384 | the latter, move it backwards to cover the gap. */ | |
3385 | delay.frag->fr_fix -= 4; | |
3386 | if (delay.frag == ip->frag) | |
3387 | move_insn (ip, ip->frag, ip->where - 4); | |
3388 | add_fixed_insn (&delay); | |
252b5132 RH |
3389 | } |
3390 | else | |
3391 | { | |
1e915849 RS |
3392 | move_insn (&delay, ip->frag, ip->where); |
3393 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3394 | } |
1e915849 RS |
3395 | history[0] = *ip; |
3396 | delay.fixed_p = 1; | |
3397 | insert_into_history (0, 1, &delay); | |
252b5132 | 3398 | } |
252b5132 RH |
3399 | |
3400 | /* If that was an unconditional branch, forget the previous | |
3401 | insn information. */ | |
3402 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
6a32d874 | 3403 | { |
6a32d874 CM |
3404 | mips_no_prev_insn (); |
3405 | } | |
252b5132 RH |
3406 | } |
3407 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3408 | { | |
3409 | /* We don't yet optimize a branch likely. What we should do | |
3410 | is look at the target, copy the instruction found there | |
3411 | into the delay slot, and increment the branch to jump to | |
3412 | the next instruction. */ | |
1e915849 | 3413 | insert_into_history (0, 1, ip); |
252b5132 | 3414 | emit_nop (); |
252b5132 RH |
3415 | } |
3416 | else | |
1e915849 | 3417 | insert_into_history (0, 1, ip); |
252b5132 | 3418 | } |
1e915849 RS |
3419 | else |
3420 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3421 | |
3422 | /* We just output an insn, so the next one doesn't have a label. */ | |
3423 | mips_clear_insn_labels (); | |
252b5132 RH |
3424 | } |
3425 | ||
7d10b47d | 3426 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3427 | |
3428 | static void | |
7d10b47d | 3429 | mips_no_prev_insn (void) |
252b5132 | 3430 | { |
7d10b47d RS |
3431 | prev_nop_frag = NULL; |
3432 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3433 | mips_clear_insn_labels (); |
3434 | } | |
3435 | ||
7d10b47d RS |
3436 | /* This function must be called before we emit something other than |
3437 | instructions. It is like mips_no_prev_insn except that it inserts | |
3438 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3439 | |
7d10b47d RS |
3440 | void |
3441 | mips_emit_delays (void) | |
252b5132 RH |
3442 | { |
3443 | if (! mips_opts.noreorder) | |
3444 | { | |
71400594 | 3445 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3446 | if (nops > 0) |
3447 | { | |
7d10b47d RS |
3448 | while (nops-- > 0) |
3449 | add_fixed_insn (NOP_INSN); | |
3450 | mips_move_labels (); | |
3451 | } | |
3452 | } | |
3453 | mips_no_prev_insn (); | |
3454 | } | |
3455 | ||
3456 | /* Start a (possibly nested) noreorder block. */ | |
3457 | ||
3458 | static void | |
3459 | start_noreorder (void) | |
3460 | { | |
3461 | if (mips_opts.noreorder == 0) | |
3462 | { | |
3463 | unsigned int i; | |
3464 | int nops; | |
3465 | ||
3466 | /* None of the instructions before the .set noreorder can be moved. */ | |
3467 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3468 | history[i].fixed_p = 1; | |
3469 | ||
3470 | /* Insert any nops that might be needed between the .set noreorder | |
3471 | block and the previous instructions. We will later remove any | |
3472 | nops that turn out not to be needed. */ | |
3473 | nops = nops_for_insn (history, NULL); | |
3474 | if (nops > 0) | |
3475 | { | |
3476 | if (mips_optimize != 0) | |
252b5132 RH |
3477 | { |
3478 | /* Record the frag which holds the nop instructions, so | |
3479 | that we can remove them if we don't need them. */ | |
3480 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3481 | prev_nop_frag = frag_now; | |
3482 | prev_nop_frag_holds = nops; | |
3483 | prev_nop_frag_required = 0; | |
3484 | prev_nop_frag_since = 0; | |
3485 | } | |
3486 | ||
3487 | for (; nops > 0; --nops) | |
1e915849 | 3488 | add_fixed_insn (NOP_INSN); |
252b5132 | 3489 | |
7d10b47d RS |
3490 | /* Move on to a new frag, so that it is safe to simply |
3491 | decrease the size of prev_nop_frag. */ | |
3492 | frag_wane (frag_now); | |
3493 | frag_new (0); | |
404a8071 | 3494 | mips_move_labels (); |
252b5132 | 3495 | } |
7d10b47d RS |
3496 | mips16_mark_labels (); |
3497 | mips_clear_insn_labels (); | |
252b5132 | 3498 | } |
7d10b47d RS |
3499 | mips_opts.noreorder++; |
3500 | mips_any_noreorder = 1; | |
3501 | } | |
252b5132 | 3502 | |
7d10b47d | 3503 | /* End a nested noreorder block. */ |
252b5132 | 3504 | |
7d10b47d RS |
3505 | static void |
3506 | end_noreorder (void) | |
3507 | { | |
6a32d874 | 3508 | |
7d10b47d RS |
3509 | mips_opts.noreorder--; |
3510 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3511 | { | |
3512 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3513 | handling nop insertion the .set reorder way. */ | |
3514 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3515 | * (mips_opts.mips16 ? 2 : 4)); | |
3516 | insert_into_history (prev_nop_frag_since, | |
3517 | prev_nop_frag_required, NOP_INSN); | |
3518 | prev_nop_frag = NULL; | |
3519 | } | |
252b5132 RH |
3520 | } |
3521 | ||
584892a6 RS |
3522 | /* Set up global variables for the start of a new macro. */ |
3523 | ||
3524 | static void | |
3525 | macro_start (void) | |
3526 | { | |
3527 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3528 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3529 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3530 | & (INSN_UNCOND_BRANCH_DELAY |
3531 | | INSN_COND_BRANCH_DELAY | |
3532 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3533 | } | |
3534 | ||
3535 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3536 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3537 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3538 | ||
3539 | static const char * | |
3540 | macro_warning (relax_substateT subtype) | |
3541 | { | |
3542 | if (subtype & RELAX_DELAY_SLOT) | |
3543 | return _("Macro instruction expanded into multiple instructions" | |
3544 | " in a branch delay slot"); | |
3545 | else if (subtype & RELAX_NOMACRO) | |
3546 | return _("Macro instruction expanded into multiple instructions"); | |
3547 | else | |
3548 | return 0; | |
3549 | } | |
3550 | ||
3551 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3552 | ||
3553 | static void | |
3554 | macro_end (void) | |
3555 | { | |
3556 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3557 | { | |
3558 | relax_substateT subtype; | |
3559 | ||
3560 | /* Set up the relaxation warning flags. */ | |
3561 | subtype = 0; | |
3562 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3563 | subtype |= RELAX_SECOND_LONGER; | |
3564 | if (mips_opts.warn_about_macros) | |
3565 | subtype |= RELAX_NOMACRO; | |
3566 | if (mips_macro_warning.delay_slot_p) | |
3567 | subtype |= RELAX_DELAY_SLOT; | |
3568 | ||
3569 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3570 | { | |
3571 | /* Either the macro has a single implementation or both | |
3572 | implementations are longer than 4 bytes. Emit the | |
3573 | warning now. */ | |
3574 | const char *msg = macro_warning (subtype); | |
3575 | if (msg != 0) | |
520725ea | 3576 | as_warn ("%s", msg); |
584892a6 RS |
3577 | } |
3578 | else | |
3579 | { | |
3580 | /* One implementation might need a warning but the other | |
3581 | definitely doesn't. */ | |
3582 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3583 | } | |
3584 | } | |
3585 | } | |
3586 | ||
6e1304d8 RS |
3587 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3588 | The first argument in *ARGS will be either the code for a single | |
3589 | relocation or -1 followed by the three codes that make up a | |
3590 | composite relocation. */ | |
3591 | ||
3592 | static void | |
3593 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3594 | { | |
3595 | int i, next; | |
3596 | ||
3597 | next = va_arg (*args, int); | |
3598 | if (next >= 0) | |
3599 | r[0] = (bfd_reloc_code_real_type) next; | |
3600 | else | |
3601 | for (i = 0; i < 3; i++) | |
3602 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3603 | } | |
3604 | ||
252b5132 RH |
3605 | /* Build an instruction created by a macro expansion. This is passed |
3606 | a pointer to the count of instructions created so far, an | |
3607 | expression, the name of the instruction to build, an operand format | |
3608 | string, and corresponding arguments. */ | |
3609 | ||
252b5132 | 3610 | static void |
67c0d1eb | 3611 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3612 | { |
1e915849 | 3613 | const struct mips_opcode *mo; |
252b5132 | 3614 | struct mips_cl_insn insn; |
f6688943 | 3615 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3616 | va_list args; |
252b5132 | 3617 | |
252b5132 | 3618 | va_start (args, fmt); |
252b5132 | 3619 | |
252b5132 RH |
3620 | if (mips_opts.mips16) |
3621 | { | |
03ea81db | 3622 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
3623 | va_end (args); |
3624 | return; | |
3625 | } | |
3626 | ||
f6688943 TS |
3627 | r[0] = BFD_RELOC_UNUSED; |
3628 | r[1] = BFD_RELOC_UNUSED; | |
3629 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 | 3630 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
9c2799c2 NC |
3631 | gas_assert (mo); |
3632 | gas_assert (strcmp (name, mo->name) == 0); | |
1e915849 | 3633 | |
8b082fb1 TS |
3634 | while (1) |
3635 | { | |
3636 | /* Search until we get a match for NAME. It is assumed here that | |
3637 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3638 | if (strcmp (fmt, mo->args) == 0 | |
3639 | && mo->pinfo != INSN_MACRO | |
f79e2745 | 3640 | && is_opcode_valid (mo)) |
8b082fb1 TS |
3641 | break; |
3642 | ||
1e915849 | 3643 | ++mo; |
9c2799c2 NC |
3644 | gas_assert (mo->name); |
3645 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3646 | } |
3647 | ||
1e915849 | 3648 | create_insn (&insn, mo); |
252b5132 RH |
3649 | for (;;) |
3650 | { | |
3651 | switch (*fmt++) | |
3652 | { | |
3653 | case '\0': | |
3654 | break; | |
3655 | ||
3656 | case ',': | |
3657 | case '(': | |
3658 | case ')': | |
3659 | continue; | |
3660 | ||
5f74bc13 CD |
3661 | case '+': |
3662 | switch (*fmt++) | |
3663 | { | |
3664 | case 'A': | |
3665 | case 'E': | |
bf12938e | 3666 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3667 | continue; |
3668 | ||
3669 | case 'B': | |
3670 | case 'F': | |
3671 | /* Note that in the macro case, these arguments are already | |
3672 | in MSB form. (When handling the instruction in the | |
3673 | non-macro case, these arguments are sizes from which | |
3674 | MSB values must be calculated.) */ | |
bf12938e | 3675 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3676 | continue; |
3677 | ||
3678 | case 'C': | |
3679 | case 'G': | |
3680 | case 'H': | |
3681 | /* Note that in the macro case, these arguments are already | |
3682 | in MSBD form. (When handling the instruction in the | |
3683 | non-macro case, these arguments are sizes from which | |
3684 | MSBD values must be calculated.) */ | |
bf12938e | 3685 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3686 | continue; |
3687 | ||
dd3cbb7e NC |
3688 | case 'Q': |
3689 | INSERT_OPERAND (SEQI, insn, va_arg (args, int)); | |
3690 | continue; | |
3691 | ||
5f74bc13 CD |
3692 | default: |
3693 | internalError (); | |
3694 | } | |
3695 | continue; | |
3696 | ||
8b082fb1 TS |
3697 | case '2': |
3698 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3699 | continue; | |
3700 | ||
252b5132 RH |
3701 | case 't': |
3702 | case 'w': | |
3703 | case 'E': | |
bf12938e | 3704 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3705 | continue; |
3706 | ||
3707 | case 'c': | |
bf12938e | 3708 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3709 | continue; |
3710 | ||
252b5132 RH |
3711 | case 'T': |
3712 | case 'W': | |
bf12938e | 3713 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3714 | continue; |
3715 | ||
3716 | case 'd': | |
3717 | case 'G': | |
af7ee8bf | 3718 | case 'K': |
bf12938e | 3719 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3720 | continue; |
3721 | ||
4372b673 NC |
3722 | case 'U': |
3723 | { | |
3724 | int tmp = va_arg (args, int); | |
3725 | ||
bf12938e RS |
3726 | INSERT_OPERAND (RT, insn, tmp); |
3727 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3728 | continue; |
4372b673 NC |
3729 | } |
3730 | ||
252b5132 RH |
3731 | case 'V': |
3732 | case 'S': | |
bf12938e | 3733 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3734 | continue; |
3735 | ||
3736 | case 'z': | |
3737 | continue; | |
3738 | ||
3739 | case '<': | |
bf12938e | 3740 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3741 | continue; |
3742 | ||
3743 | case 'D': | |
bf12938e | 3744 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3745 | continue; |
3746 | ||
3747 | case 'B': | |
bf12938e | 3748 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3749 | continue; |
3750 | ||
4372b673 | 3751 | case 'J': |
bf12938e | 3752 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3753 | continue; |
3754 | ||
252b5132 | 3755 | case 'q': |
bf12938e | 3756 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3757 | continue; |
3758 | ||
3759 | case 'b': | |
3760 | case 's': | |
3761 | case 'r': | |
3762 | case 'v': | |
bf12938e | 3763 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3764 | continue; |
3765 | ||
3766 | case 'i': | |
3767 | case 'j': | |
3768 | case 'o': | |
6e1304d8 | 3769 | macro_read_relocs (&args, r); |
9c2799c2 | 3770 | gas_assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3771 | || *r == BFD_RELOC_MIPS_LITERAL |
3772 | || *r == BFD_RELOC_MIPS_HIGHER | |
3773 | || *r == BFD_RELOC_HI16_S | |
3774 | || *r == BFD_RELOC_LO16 | |
3775 | || *r == BFD_RELOC_MIPS_GOT16 | |
3776 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3777 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3778 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3779 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3780 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3781 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3782 | continue; |
3783 | ||
3784 | case 'u': | |
6e1304d8 | 3785 | macro_read_relocs (&args, r); |
9c2799c2 | 3786 | gas_assert (ep != NULL |
252b5132 RH |
3787 | && (ep->X_op == O_constant |
3788 | || (ep->X_op == O_symbol | |
f6688943 TS |
3789 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3790 | || *r == BFD_RELOC_HI16_S | |
3791 | || *r == BFD_RELOC_HI16 | |
3792 | || *r == BFD_RELOC_GPREL16 | |
3793 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3794 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3795 | continue; |
3796 | ||
3797 | case 'p': | |
9c2799c2 | 3798 | gas_assert (ep != NULL); |
bad36eac | 3799 | |
252b5132 RH |
3800 | /* |
3801 | * This allows macro() to pass an immediate expression for | |
3802 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3803 | * |
3804 | * We don't allow branch relaxation for these branches, as | |
3805 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3806 | */ |
3807 | if (ep->X_op == O_constant) | |
3808 | { | |
bad36eac DJ |
3809 | if ((ep->X_add_number & 3) != 0) |
3810 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3811 | (unsigned long) ep->X_add_number); | |
3812 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3813 | as_bad (_("branch address range overflow (0x%lx)"), | |
3814 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3815 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3816 | ep = NULL; | |
3817 | } | |
3818 | else | |
0b25d3e6 | 3819 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3820 | continue; |
3821 | ||
3822 | case 'a': | |
9c2799c2 | 3823 | gas_assert (ep != NULL); |
f6688943 | 3824 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3825 | continue; |
3826 | ||
3827 | case 'C': | |
a9e24354 | 3828 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3829 | continue; |
3830 | ||
d43b4baf | 3831 | case 'k': |
a9e24354 | 3832 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3833 | continue; |
3834 | ||
252b5132 RH |
3835 | default: |
3836 | internalError (); | |
3837 | } | |
3838 | break; | |
3839 | } | |
3840 | va_end (args); | |
9c2799c2 | 3841 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3842 | |
4d7206a2 | 3843 | append_insn (&insn, ep, r); |
252b5132 RH |
3844 | } |
3845 | ||
3846 | static void | |
67c0d1eb | 3847 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 3848 | va_list *args) |
252b5132 | 3849 | { |
1e915849 | 3850 | struct mips_opcode *mo; |
252b5132 | 3851 | struct mips_cl_insn insn; |
f6688943 TS |
3852 | bfd_reloc_code_real_type r[3] |
3853 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3854 | |
1e915849 | 3855 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
3856 | gas_assert (mo); |
3857 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3858 | |
1e915849 | 3859 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3860 | { |
1e915849 | 3861 | ++mo; |
9c2799c2 NC |
3862 | gas_assert (mo->name); |
3863 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3864 | } |
3865 | ||
1e915849 | 3866 | create_insn (&insn, mo); |
252b5132 RH |
3867 | for (;;) |
3868 | { | |
3869 | int c; | |
3870 | ||
3871 | c = *fmt++; | |
3872 | switch (c) | |
3873 | { | |
3874 | case '\0': | |
3875 | break; | |
3876 | ||
3877 | case ',': | |
3878 | case '(': | |
3879 | case ')': | |
3880 | continue; | |
3881 | ||
3882 | case 'y': | |
3883 | case 'w': | |
03ea81db | 3884 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
3885 | continue; |
3886 | ||
3887 | case 'x': | |
3888 | case 'v': | |
03ea81db | 3889 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
3890 | continue; |
3891 | ||
3892 | case 'z': | |
03ea81db | 3893 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
3894 | continue; |
3895 | ||
3896 | case 'Z': | |
03ea81db | 3897 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
3898 | continue; |
3899 | ||
3900 | case '0': | |
3901 | case 'S': | |
3902 | case 'P': | |
3903 | case 'R': | |
3904 | continue; | |
3905 | ||
3906 | case 'X': | |
03ea81db | 3907 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
3908 | continue; |
3909 | ||
3910 | case 'Y': | |
3911 | { | |
3912 | int regno; | |
3913 | ||
03ea81db | 3914 | regno = va_arg (*args, int); |
252b5132 | 3915 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 3916 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3917 | } |
3918 | continue; | |
3919 | ||
3920 | case '<': | |
3921 | case '>': | |
3922 | case '4': | |
3923 | case '5': | |
3924 | case 'H': | |
3925 | case 'W': | |
3926 | case 'D': | |
3927 | case 'j': | |
3928 | case '8': | |
3929 | case 'V': | |
3930 | case 'C': | |
3931 | case 'U': | |
3932 | case 'k': | |
3933 | case 'K': | |
3934 | case 'p': | |
3935 | case 'q': | |
3936 | { | |
9c2799c2 | 3937 | gas_assert (ep != NULL); |
252b5132 RH |
3938 | |
3939 | if (ep->X_op != O_constant) | |
874e8986 | 3940 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3941 | else |
3942 | { | |
b34976b6 AM |
3943 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3944 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3945 | &insn.extend); |
252b5132 | 3946 | ep = NULL; |
f6688943 | 3947 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3948 | } |
3949 | } | |
3950 | continue; | |
3951 | ||
3952 | case '6': | |
03ea81db | 3953 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
3954 | continue; |
3955 | } | |
3956 | ||
3957 | break; | |
3958 | } | |
3959 | ||
9c2799c2 | 3960 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3961 | |
4d7206a2 | 3962 | append_insn (&insn, ep, r); |
252b5132 RH |
3963 | } |
3964 | ||
2051e8c4 MR |
3965 | /* |
3966 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3967 | * higher bits unset. | |
3968 | */ | |
9f872bbe | 3969 | static void |
2051e8c4 MR |
3970 | normalize_constant_expr (expressionS *ex) |
3971 | { | |
9ee2a2d4 | 3972 | if (ex->X_op == O_constant |
2051e8c4 MR |
3973 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3974 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3975 | - 0x80000000); | |
3976 | } | |
3977 | ||
3978 | /* | |
3979 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3980 | * all higher bits unset. | |
3981 | */ | |
3982 | static void | |
3983 | normalize_address_expr (expressionS *ex) | |
3984 | { | |
3985 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3986 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3987 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3988 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3989 | - 0x80000000); | |
3990 | } | |
3991 | ||
438c16b8 TS |
3992 | /* |
3993 | * Generate a "jalr" instruction with a relocation hint to the called | |
3994 | * function. This occurs in NewABI PIC code. | |
3995 | */ | |
3996 | static void | |
67c0d1eb | 3997 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3998 | { |
685736be | 3999 | char *f = NULL; |
b34976b6 | 4000 | |
1180b5a4 | 4001 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4002 | { |
cc3d92a5 | 4003 | frag_grow (8); |
f21f8242 AO |
4004 | f = frag_more (0); |
4005 | } | |
67c0d1eb | 4006 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
1180b5a4 | 4007 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 4008 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 4009 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
4010 | } |
4011 | ||
252b5132 RH |
4012 | /* |
4013 | * Generate a "lui" instruction. | |
4014 | */ | |
4015 | static void | |
67c0d1eb | 4016 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
4017 | { |
4018 | expressionS high_expr; | |
1e915849 | 4019 | const struct mips_opcode *mo; |
252b5132 | 4020 | struct mips_cl_insn insn; |
f6688943 TS |
4021 | bfd_reloc_code_real_type r[3] |
4022 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
4023 | const char *name = "lui"; |
4024 | const char *fmt = "t,u"; | |
252b5132 | 4025 | |
9c2799c2 | 4026 | gas_assert (! mips_opts.mips16); |
252b5132 | 4027 | |
4d7206a2 | 4028 | high_expr = *ep; |
252b5132 RH |
4029 | |
4030 | if (high_expr.X_op == O_constant) | |
4031 | { | |
54f4ddb3 | 4032 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
4033 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
4034 | >> 16) & 0xffff; | |
f6688943 | 4035 | *r = BFD_RELOC_UNUSED; |
252b5132 | 4036 | } |
78e1bb40 | 4037 | else |
252b5132 | 4038 | { |
9c2799c2 | 4039 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
4040 | /* _gp_disp is a special case, used from s_cpload. |
4041 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 4042 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 4043 | || (! HAVE_NEWABI |
aa6975fb ILT |
4044 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
4045 | || (! mips_in_shared | |
bbe506e8 TS |
4046 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
4047 | "__gnu_local_gp") == 0)); | |
f6688943 | 4048 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
4049 | } |
4050 | ||
1e915849 | 4051 | mo = hash_find (op_hash, name); |
9c2799c2 NC |
4052 | gas_assert (strcmp (name, mo->name) == 0); |
4053 | gas_assert (strcmp (fmt, mo->args) == 0); | |
1e915849 | 4054 | create_insn (&insn, mo); |
252b5132 | 4055 | |
bf12938e RS |
4056 | insn.insn_opcode = insn.insn_mo->match; |
4057 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 4058 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
4059 | { |
4060 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 4061 | append_insn (&insn, NULL, r); |
252b5132 RH |
4062 | } |
4063 | else | |
4d7206a2 | 4064 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
4065 | } |
4066 | ||
885add95 CD |
4067 | /* Generate a sequence of instructions to do a load or store from a constant |
4068 | offset off of a base register (breg) into/from a target register (treg), | |
4069 | using AT if necessary. */ | |
4070 | static void | |
67c0d1eb RS |
4071 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
4072 | int treg, int breg, int dbl) | |
885add95 | 4073 | { |
9c2799c2 | 4074 | gas_assert (ep->X_op == O_constant); |
885add95 | 4075 | |
256ab948 | 4076 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
4077 | if (!dbl) |
4078 | normalize_constant_expr (ep); | |
256ab948 | 4079 | |
67c1ffbe | 4080 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 4081 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
4082 | as_warn (_("operand overflow")); |
4083 | ||
4084 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
4085 | { | |
4086 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 4087 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
4088 | } |
4089 | else | |
4090 | { | |
4091 | /* 32-bit offset, need multiple instructions and AT, like: | |
4092 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
4093 | addu $tempreg,$tempreg,$breg | |
4094 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
4095 | to handle the complete offset. */ | |
67c0d1eb RS |
4096 | macro_build_lui (ep, AT); |
4097 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
4098 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 4099 | |
741fe287 | 4100 | if (!mips_opts.at) |
8fc2e39e | 4101 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
4102 | } |
4103 | } | |
4104 | ||
252b5132 RH |
4105 | /* set_at() |
4106 | * Generates code to set the $at register to true (one) | |
4107 | * if reg is less than the immediate expression. | |
4108 | */ | |
4109 | static void | |
67c0d1eb | 4110 | set_at (int reg, int unsignedp) |
252b5132 RH |
4111 | { |
4112 | if (imm_expr.X_op == O_constant | |
4113 | && imm_expr.X_add_number >= -0x8000 | |
4114 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
4115 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
4116 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
4117 | else |
4118 | { | |
67c0d1eb RS |
4119 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4120 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
4121 | } |
4122 | } | |
4123 | ||
4124 | /* Warn if an expression is not a constant. */ | |
4125 | ||
4126 | static void | |
17a2f251 | 4127 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
4128 | { |
4129 | if (ex->X_op == O_big) | |
4130 | as_bad (_("unsupported large constant")); | |
4131 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
4132 | as_bad (_("Instruction %s requires absolute expression"), |
4133 | ip->insn_mo->name); | |
13757d0c | 4134 | |
9ee2a2d4 MR |
4135 | if (HAVE_32BIT_GPRS) |
4136 | normalize_constant_expr (ex); | |
252b5132 RH |
4137 | } |
4138 | ||
4139 | /* Count the leading zeroes by performing a binary chop. This is a | |
4140 | bulky bit of source, but performance is a LOT better for the | |
4141 | majority of values than a simple loop to count the bits: | |
4142 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
4143 | if ((v) & (1 << (31 - lcnt))) | |
4144 | break; | |
4145 | However it is not code size friendly, and the gain will drop a bit | |
4146 | on certain cached systems. | |
4147 | */ | |
4148 | #define COUNT_TOP_ZEROES(v) \ | |
4149 | (((v) & ~0xffff) == 0 \ | |
4150 | ? ((v) & ~0xff) == 0 \ | |
4151 | ? ((v) & ~0xf) == 0 \ | |
4152 | ? ((v) & ~0x3) == 0 \ | |
4153 | ? ((v) & ~0x1) == 0 \ | |
4154 | ? !(v) \ | |
4155 | ? 32 \ | |
4156 | : 31 \ | |
4157 | : 30 \ | |
4158 | : ((v) & ~0x7) == 0 \ | |
4159 | ? 29 \ | |
4160 | : 28 \ | |
4161 | : ((v) & ~0x3f) == 0 \ | |
4162 | ? ((v) & ~0x1f) == 0 \ | |
4163 | ? 27 \ | |
4164 | : 26 \ | |
4165 | : ((v) & ~0x7f) == 0 \ | |
4166 | ? 25 \ | |
4167 | : 24 \ | |
4168 | : ((v) & ~0xfff) == 0 \ | |
4169 | ? ((v) & ~0x3ff) == 0 \ | |
4170 | ? ((v) & ~0x1ff) == 0 \ | |
4171 | ? 23 \ | |
4172 | : 22 \ | |
4173 | : ((v) & ~0x7ff) == 0 \ | |
4174 | ? 21 \ | |
4175 | : 20 \ | |
4176 | : ((v) & ~0x3fff) == 0 \ | |
4177 | ? ((v) & ~0x1fff) == 0 \ | |
4178 | ? 19 \ | |
4179 | : 18 \ | |
4180 | : ((v) & ~0x7fff) == 0 \ | |
4181 | ? 17 \ | |
4182 | : 16 \ | |
4183 | : ((v) & ~0xffffff) == 0 \ | |
4184 | ? ((v) & ~0xfffff) == 0 \ | |
4185 | ? ((v) & ~0x3ffff) == 0 \ | |
4186 | ? ((v) & ~0x1ffff) == 0 \ | |
4187 | ? 15 \ | |
4188 | : 14 \ | |
4189 | : ((v) & ~0x7ffff) == 0 \ | |
4190 | ? 13 \ | |
4191 | : 12 \ | |
4192 | : ((v) & ~0x3fffff) == 0 \ | |
4193 | ? ((v) & ~0x1fffff) == 0 \ | |
4194 | ? 11 \ | |
4195 | : 10 \ | |
4196 | : ((v) & ~0x7fffff) == 0 \ | |
4197 | ? 9 \ | |
4198 | : 8 \ | |
4199 | : ((v) & ~0xfffffff) == 0 \ | |
4200 | ? ((v) & ~0x3ffffff) == 0 \ | |
4201 | ? ((v) & ~0x1ffffff) == 0 \ | |
4202 | ? 7 \ | |
4203 | : 6 \ | |
4204 | : ((v) & ~0x7ffffff) == 0 \ | |
4205 | ? 5 \ | |
4206 | : 4 \ | |
4207 | : ((v) & ~0x3fffffff) == 0 \ | |
4208 | ? ((v) & ~0x1fffffff) == 0 \ | |
4209 | ? 3 \ | |
4210 | : 2 \ | |
4211 | : ((v) & ~0x7fffffff) == 0 \ | |
4212 | ? 1 \ | |
4213 | : 0) | |
4214 | ||
4215 | /* load_register() | |
67c1ffbe | 4216 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
4217 | * an absolute expression value into a register. |
4218 | */ | |
4219 | static void | |
67c0d1eb | 4220 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
4221 | { |
4222 | int freg; | |
4223 | expressionS hi32, lo32; | |
4224 | ||
4225 | if (ep->X_op != O_big) | |
4226 | { | |
9c2799c2 | 4227 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
4228 | |
4229 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
4230 | if (!dbl) |
4231 | normalize_constant_expr (ep); | |
256ab948 TS |
4232 | |
4233 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
4234 | { |
4235 | /* We can handle 16 bit signed values with an addiu to | |
4236 | $zero. No need to ever use daddiu here, since $zero and | |
4237 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 4238 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4239 | return; |
4240 | } | |
4241 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
4242 | { | |
4243 | /* We can handle 16 bit unsigned values with an ori to | |
4244 | $zero. */ | |
67c0d1eb | 4245 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4246 | return; |
4247 | } | |
256ab948 | 4248 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
4249 | { |
4250 | /* 32 bit values require an lui. */ | |
67c0d1eb | 4251 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4252 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 4253 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
4254 | return; |
4255 | } | |
4256 | } | |
4257 | ||
4258 | /* The value is larger than 32 bits. */ | |
4259 | ||
2051e8c4 | 4260 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 4261 | { |
55e08f71 NC |
4262 | char value[32]; |
4263 | ||
4264 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 4265 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 4266 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
4267 | return; |
4268 | } | |
4269 | ||
4270 | if (ep->X_op != O_big) | |
4271 | { | |
4272 | hi32 = *ep; | |
4273 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4274 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
4275 | hi32.X_add_number &= 0xffffffff; | |
4276 | lo32 = *ep; | |
4277 | lo32.X_add_number &= 0xffffffff; | |
4278 | } | |
4279 | else | |
4280 | { | |
9c2799c2 | 4281 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
4282 | if (ep->X_add_number == 3) |
4283 | generic_bignum[3] = 0; | |
4284 | else if (ep->X_add_number > 4) | |
4285 | as_bad (_("Number larger than 64 bits")); | |
4286 | lo32.X_op = O_constant; | |
4287 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4288 | hi32.X_op = O_constant; | |
4289 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4290 | } | |
4291 | ||
4292 | if (hi32.X_add_number == 0) | |
4293 | freg = 0; | |
4294 | else | |
4295 | { | |
4296 | int shift, bit; | |
4297 | unsigned long hi, lo; | |
4298 | ||
956cd1d6 | 4299 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4300 | { |
4301 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4302 | { | |
67c0d1eb | 4303 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4304 | return; |
4305 | } | |
4306 | if (lo32.X_add_number & 0x80000000) | |
4307 | { | |
67c0d1eb | 4308 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4309 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4310 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4311 | return; |
4312 | } | |
4313 | } | |
252b5132 RH |
4314 | |
4315 | /* Check for 16bit shifted constant. We know that hi32 is | |
4316 | non-zero, so start the mask on the first bit of the hi32 | |
4317 | value. */ | |
4318 | shift = 17; | |
4319 | do | |
beae10d5 KH |
4320 | { |
4321 | unsigned long himask, lomask; | |
4322 | ||
4323 | if (shift < 32) | |
4324 | { | |
4325 | himask = 0xffff >> (32 - shift); | |
4326 | lomask = (0xffff << shift) & 0xffffffff; | |
4327 | } | |
4328 | else | |
4329 | { | |
4330 | himask = 0xffff << (shift - 32); | |
4331 | lomask = 0; | |
4332 | } | |
4333 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4334 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4335 | { | |
4336 | expressionS tmp; | |
4337 | ||
4338 | tmp.X_op = O_constant; | |
4339 | if (shift < 32) | |
4340 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4341 | | (lo32.X_add_number >> shift)); | |
4342 | else | |
4343 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4344 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4345 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4346 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4347 | return; |
4348 | } | |
f9419b05 | 4349 | ++shift; |
beae10d5 KH |
4350 | } |
4351 | while (shift <= (64 - 16)); | |
252b5132 RH |
4352 | |
4353 | /* Find the bit number of the lowest one bit, and store the | |
4354 | shifted value in hi/lo. */ | |
4355 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4356 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4357 | if (lo != 0) | |
4358 | { | |
4359 | bit = 0; | |
4360 | while ((lo & 1) == 0) | |
4361 | { | |
4362 | lo >>= 1; | |
4363 | ++bit; | |
4364 | } | |
4365 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4366 | hi >>= bit; | |
4367 | } | |
4368 | else | |
4369 | { | |
4370 | bit = 32; | |
4371 | while ((hi & 1) == 0) | |
4372 | { | |
4373 | hi >>= 1; | |
4374 | ++bit; | |
4375 | } | |
4376 | lo = hi; | |
4377 | hi = 0; | |
4378 | } | |
4379 | ||
4380 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4381 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4382 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4383 | { |
4384 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4385 | if (shift != 0) |
beae10d5 | 4386 | { |
252b5132 RH |
4387 | expressionS tmp; |
4388 | ||
4389 | /* This instruction will set the register to be all | |
4390 | ones. */ | |
beae10d5 KH |
4391 | tmp.X_op = O_constant; |
4392 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4393 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4394 | if (bit != 0) |
4395 | { | |
4396 | bit += shift; | |
67c0d1eb RS |
4397 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4398 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4399 | } |
67c0d1eb RS |
4400 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4401 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4402 | return; |
4403 | } | |
4404 | } | |
252b5132 RH |
4405 | |
4406 | /* Sign extend hi32 before calling load_register, because we can | |
4407 | generally get better code when we load a sign extended value. */ | |
4408 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4409 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4410 | load_register (reg, &hi32, 0); |
252b5132 RH |
4411 | freg = reg; |
4412 | } | |
4413 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4414 | { | |
4415 | if (freg != 0) | |
4416 | { | |
67c0d1eb | 4417 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4418 | freg = reg; |
4419 | } | |
4420 | } | |
4421 | else | |
4422 | { | |
4423 | expressionS mid16; | |
4424 | ||
956cd1d6 | 4425 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4426 | { |
67c0d1eb RS |
4427 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4428 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4429 | return; |
4430 | } | |
252b5132 RH |
4431 | |
4432 | if (freg != 0) | |
4433 | { | |
67c0d1eb | 4434 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4435 | freg = reg; |
4436 | } | |
4437 | mid16 = lo32; | |
4438 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4439 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4440 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4441 | freg = reg; |
4442 | } | |
4443 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4444 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4445 | } |
4446 | ||
269137b2 TS |
4447 | static inline void |
4448 | load_delay_nop (void) | |
4449 | { | |
4450 | if (!gpr_interlocks) | |
4451 | macro_build (NULL, "nop", ""); | |
4452 | } | |
4453 | ||
252b5132 RH |
4454 | /* Load an address into a register. */ |
4455 | ||
4456 | static void | |
67c0d1eb | 4457 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4458 | { |
252b5132 RH |
4459 | if (ep->X_op != O_constant |
4460 | && ep->X_op != O_symbol) | |
4461 | { | |
4462 | as_bad (_("expression too complex")); | |
4463 | ep->X_op = O_constant; | |
4464 | } | |
4465 | ||
4466 | if (ep->X_op == O_constant) | |
4467 | { | |
67c0d1eb | 4468 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4469 | return; |
4470 | } | |
4471 | ||
4472 | if (mips_pic == NO_PIC) | |
4473 | { | |
4474 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4475 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4476 | Otherwise we want |
4477 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4478 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4479 | If we have an addend, we always use the latter form. |
76b3015f | 4480 | |
d6bc6245 TS |
4481 | With 64bit address space and a usable $at we want |
4482 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4483 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4484 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4485 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4486 | dsll32 $reg,0 | |
3a482fd5 | 4487 | daddu $reg,$reg,$at |
76b3015f | 4488 | |
c03099e6 | 4489 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4490 | on superscalar processors. |
4491 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4492 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4493 | dsll $reg,16 | |
4494 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4495 | dsll $reg,16 | |
4496 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4497 | |
4498 | For GP relative symbols in 64bit address space we can use | |
4499 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4500 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4501 | { |
6caf9ef4 TS |
4502 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4503 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4504 | { | |
4505 | relax_start (ep->X_add_symbol); | |
4506 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4507 | mips_gp_register, BFD_RELOC_GPREL16); | |
4508 | relax_switch (); | |
4509 | } | |
d6bc6245 | 4510 | |
741fe287 | 4511 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 4512 | { |
67c0d1eb RS |
4513 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4514 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4515 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4516 | BFD_RELOC_MIPS_HIGHER); | |
4517 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4518 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4519 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4520 | *used_at = 1; |
4521 | } | |
4522 | else | |
4523 | { | |
67c0d1eb RS |
4524 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4525 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4526 | BFD_RELOC_MIPS_HIGHER); | |
4527 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4528 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4529 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4530 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4531 | } |
6caf9ef4 TS |
4532 | |
4533 | if (mips_relax.sequence) | |
4534 | relax_end (); | |
d6bc6245 | 4535 | } |
252b5132 RH |
4536 | else |
4537 | { | |
d6bc6245 | 4538 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4539 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4540 | { |
4d7206a2 | 4541 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4542 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4543 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4544 | relax_switch (); |
d6bc6245 | 4545 | } |
67c0d1eb RS |
4546 | macro_build_lui (ep, reg); |
4547 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4548 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4549 | if (mips_relax.sequence) |
4550 | relax_end (); | |
d6bc6245 | 4551 | } |
252b5132 | 4552 | } |
0a44bf69 | 4553 | else if (!mips_big_got) |
252b5132 RH |
4554 | { |
4555 | expressionS ex; | |
4556 | ||
4557 | /* If this is a reference to an external symbol, we want | |
4558 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4559 | Otherwise we want | |
4560 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4561 | nop | |
4562 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4563 | If there is a constant, it must be added in after. |
4564 | ||
ed6fb7bd | 4565 | If we have NewABI, we want |
f5040a92 AO |
4566 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4567 | unless we're referencing a global symbol with a non-zero | |
4568 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4569 | if (HAVE_NEWABI) |
4570 | { | |
f5040a92 AO |
4571 | if (ep->X_add_number) |
4572 | { | |
4d7206a2 | 4573 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4574 | ep->X_add_number = 0; |
4d7206a2 | 4575 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4576 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4577 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4578 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4579 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4580 | ex.X_op = O_constant; | |
67c0d1eb | 4581 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4582 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4583 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4584 | relax_switch (); |
f5040a92 | 4585 | } |
67c0d1eb | 4586 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4587 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4588 | if (mips_relax.sequence) |
4589 | relax_end (); | |
ed6fb7bd SC |
4590 | } |
4591 | else | |
4592 | { | |
f5040a92 AO |
4593 | ex.X_add_number = ep->X_add_number; |
4594 | ep->X_add_number = 0; | |
67c0d1eb RS |
4595 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4596 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4597 | load_delay_nop (); |
4d7206a2 RS |
4598 | relax_start (ep->X_add_symbol); |
4599 | relax_switch (); | |
67c0d1eb | 4600 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4601 | BFD_RELOC_LO16); |
4d7206a2 | 4602 | relax_end (); |
ed6fb7bd | 4603 | |
f5040a92 AO |
4604 | if (ex.X_add_number != 0) |
4605 | { | |
4606 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4607 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4608 | ex.X_op = O_constant; | |
67c0d1eb | 4609 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4610 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4611 | } |
252b5132 RH |
4612 | } |
4613 | } | |
0a44bf69 | 4614 | else if (mips_big_got) |
252b5132 RH |
4615 | { |
4616 | expressionS ex; | |
252b5132 RH |
4617 | |
4618 | /* This is the large GOT case. If this is a reference to an | |
4619 | external symbol, we want | |
4620 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4621 | addu $reg,$reg,$gp | |
4622 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4623 | |
4624 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4625 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4626 | nop | |
4627 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4628 | If there is a constant, it must be added in after. |
f5040a92 AO |
4629 | |
4630 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4631 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4632 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4633 | */ |
438c16b8 TS |
4634 | if (HAVE_NEWABI) |
4635 | { | |
4d7206a2 | 4636 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4637 | ep->X_add_number = 0; |
4d7206a2 | 4638 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4639 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4640 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4641 | reg, reg, mips_gp_register); | |
4642 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4643 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4644 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4645 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4646 | else if (ex.X_add_number) | |
4647 | { | |
4648 | ex.X_op = O_constant; | |
67c0d1eb RS |
4649 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4650 | BFD_RELOC_LO16); | |
f5040a92 AO |
4651 | } |
4652 | ||
4653 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4654 | relax_switch (); |
67c0d1eb | 4655 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4656 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4657 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4658 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4659 | relax_end (); |
438c16b8 | 4660 | } |
252b5132 | 4661 | else |
438c16b8 | 4662 | { |
f5040a92 AO |
4663 | ex.X_add_number = ep->X_add_number; |
4664 | ep->X_add_number = 0; | |
4d7206a2 | 4665 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4666 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4667 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4668 | reg, reg, mips_gp_register); | |
4669 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4670 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4671 | relax_switch (); |
4672 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4673 | { |
4674 | /* We need a nop before loading from $gp. This special | |
4675 | check is required because the lui which starts the main | |
4676 | instruction stream does not refer to $gp, and so will not | |
4677 | insert the nop which may be required. */ | |
67c0d1eb | 4678 | macro_build (NULL, "nop", ""); |
438c16b8 | 4679 | } |
67c0d1eb | 4680 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4681 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4682 | load_delay_nop (); |
67c0d1eb | 4683 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4684 | BFD_RELOC_LO16); |
4d7206a2 | 4685 | relax_end (); |
438c16b8 | 4686 | |
f5040a92 AO |
4687 | if (ex.X_add_number != 0) |
4688 | { | |
4689 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4690 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4691 | ex.X_op = O_constant; | |
67c0d1eb RS |
4692 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4693 | BFD_RELOC_LO16); | |
f5040a92 | 4694 | } |
252b5132 RH |
4695 | } |
4696 | } | |
252b5132 RH |
4697 | else |
4698 | abort (); | |
8fc2e39e | 4699 | |
741fe287 | 4700 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 4701 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
4702 | } |
4703 | ||
ea1fb5dc RS |
4704 | /* Move the contents of register SOURCE into register DEST. */ |
4705 | ||
4706 | static void | |
67c0d1eb | 4707 | move_register (int dest, int source) |
ea1fb5dc | 4708 | { |
67c0d1eb RS |
4709 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4710 | dest, source, 0); | |
ea1fb5dc RS |
4711 | } |
4712 | ||
4d7206a2 | 4713 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4714 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4715 | The two alternatives are: | |
4d7206a2 RS |
4716 | |
4717 | Global symbol Local sybmol | |
4718 | ------------- ------------ | |
4719 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4720 | ... ... | |
4721 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4722 | ||
4723 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4724 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4725 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4726 | |
4727 | static void | |
67c0d1eb | 4728 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4729 | { |
4730 | expressionS global; | |
4731 | ||
4732 | global = *local; | |
4733 | global.X_add_number = 0; | |
4734 | ||
4735 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4736 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4737 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4738 | relax_switch (); |
67c0d1eb RS |
4739 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4740 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4741 | relax_end (); |
4742 | } | |
4743 | ||
4744 | static void | |
67c0d1eb | 4745 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4746 | { |
4747 | expressionS global; | |
4748 | ||
4749 | global.X_op = O_constant; | |
4750 | global.X_op_symbol = NULL; | |
4751 | global.X_add_symbol = NULL; | |
4752 | global.X_add_number = local->X_add_number; | |
4753 | ||
4754 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4755 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4756 | dest, dest, BFD_RELOC_LO16); |
4757 | relax_switch (); | |
67c0d1eb | 4758 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4759 | relax_end (); |
4760 | } | |
4761 | ||
f6a22291 MR |
4762 | static void |
4763 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4764 | { | |
4765 | expressionS global; | |
4766 | int hold_mips_optimize; | |
4767 | ||
4768 | global.X_op = O_constant; | |
4769 | global.X_op_symbol = NULL; | |
4770 | global.X_add_symbol = NULL; | |
4771 | global.X_add_number = local->X_add_number; | |
4772 | ||
4773 | relax_start (local->X_add_symbol); | |
4774 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4775 | relax_switch (); | |
4776 | /* Set mips_optimize around the lui instruction to avoid | |
4777 | inserting an unnecessary nop after the lw. */ | |
4778 | hold_mips_optimize = mips_optimize; | |
4779 | mips_optimize = 2; | |
4780 | macro_build_lui (&global, tmp); | |
4781 | mips_optimize = hold_mips_optimize; | |
4782 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4783 | relax_end (); | |
4784 | ||
4785 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4786 | } | |
4787 | ||
252b5132 RH |
4788 | /* |
4789 | * Build macros | |
4790 | * This routine implements the seemingly endless macro or synthesized | |
4791 | * instructions and addressing modes in the mips assembly language. Many | |
4792 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4793 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4794 | * this verbose method. Others are not simple macros but are more like |
4795 | * optimizing code generation. | |
4796 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4797 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4798 | * The ensuing load upper instructions are ommited. This implies some kind |
4799 | * of global optimization. We currently only optimize within a single macro. | |
4800 | * For many of the load and store macros if the address is specified as a | |
4801 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4802 | * first load register 'at' with zero and use it as the base register. The | |
4803 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4804 | * we're missing. | |
4805 | */ | |
4806 | static void | |
17a2f251 | 4807 | macro (struct mips_cl_insn *ip) |
252b5132 | 4808 | { |
741fe287 MR |
4809 | unsigned int treg, sreg, dreg, breg; |
4810 | unsigned int tempreg; | |
252b5132 | 4811 | int mask; |
43841e91 | 4812 | int used_at = 0; |
252b5132 RH |
4813 | expressionS expr1; |
4814 | const char *s; | |
4815 | const char *s2; | |
4816 | const char *fmt; | |
4817 | int likely = 0; | |
4818 | int dbl = 0; | |
4819 | int coproc = 0; | |
4820 | int lr = 0; | |
4821 | int imm = 0; | |
1abe91b1 | 4822 | int call = 0; |
252b5132 | 4823 | int off; |
67c0d1eb | 4824 | offsetT maxnum; |
252b5132 | 4825 | bfd_reloc_code_real_type r; |
252b5132 RH |
4826 | int hold_mips_optimize; |
4827 | ||
9c2799c2 | 4828 | gas_assert (! mips_opts.mips16); |
252b5132 RH |
4829 | |
4830 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4831 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4832 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4833 | mask = ip->insn_mo->mask; | |
4834 | ||
4835 | expr1.X_op = O_constant; | |
4836 | expr1.X_op_symbol = NULL; | |
4837 | expr1.X_add_symbol = NULL; | |
4838 | expr1.X_add_number = 1; | |
4839 | ||
4840 | switch (mask) | |
4841 | { | |
4842 | case M_DABS: | |
4843 | dbl = 1; | |
4844 | case M_ABS: | |
4845 | /* bgez $a0,.+12 | |
4846 | move v0,$a0 | |
4847 | sub v0,$zero,$a0 | |
4848 | */ | |
4849 | ||
7d10b47d | 4850 | start_noreorder (); |
252b5132 RH |
4851 | |
4852 | expr1.X_add_number = 8; | |
67c0d1eb | 4853 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4854 | if (dreg == sreg) |
67c0d1eb | 4855 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4856 | else |
67c0d1eb RS |
4857 | move_register (dreg, sreg); |
4858 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4859 | |
7d10b47d | 4860 | end_noreorder (); |
8fc2e39e | 4861 | break; |
252b5132 RH |
4862 | |
4863 | case M_ADD_I: | |
4864 | s = "addi"; | |
4865 | s2 = "add"; | |
4866 | goto do_addi; | |
4867 | case M_ADDU_I: | |
4868 | s = "addiu"; | |
4869 | s2 = "addu"; | |
4870 | goto do_addi; | |
4871 | case M_DADD_I: | |
4872 | dbl = 1; | |
4873 | s = "daddi"; | |
4874 | s2 = "dadd"; | |
4875 | goto do_addi; | |
4876 | case M_DADDU_I: | |
4877 | dbl = 1; | |
4878 | s = "daddiu"; | |
4879 | s2 = "daddu"; | |
4880 | do_addi: | |
4881 | if (imm_expr.X_op == O_constant | |
4882 | && imm_expr.X_add_number >= -0x8000 | |
4883 | && imm_expr.X_add_number < 0x8000) | |
4884 | { | |
67c0d1eb | 4885 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4886 | break; |
252b5132 | 4887 | } |
8fc2e39e | 4888 | used_at = 1; |
67c0d1eb RS |
4889 | load_register (AT, &imm_expr, dbl); |
4890 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4891 | break; |
4892 | ||
4893 | case M_AND_I: | |
4894 | s = "andi"; | |
4895 | s2 = "and"; | |
4896 | goto do_bit; | |
4897 | case M_OR_I: | |
4898 | s = "ori"; | |
4899 | s2 = "or"; | |
4900 | goto do_bit; | |
4901 | case M_NOR_I: | |
4902 | s = ""; | |
4903 | s2 = "nor"; | |
4904 | goto do_bit; | |
4905 | case M_XOR_I: | |
4906 | s = "xori"; | |
4907 | s2 = "xor"; | |
4908 | do_bit: | |
4909 | if (imm_expr.X_op == O_constant | |
4910 | && imm_expr.X_add_number >= 0 | |
4911 | && imm_expr.X_add_number < 0x10000) | |
4912 | { | |
4913 | if (mask != M_NOR_I) | |
67c0d1eb | 4914 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4915 | else |
4916 | { | |
67c0d1eb RS |
4917 | macro_build (&imm_expr, "ori", "t,r,i", |
4918 | treg, sreg, BFD_RELOC_LO16); | |
4919 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4920 | } |
8fc2e39e | 4921 | break; |
252b5132 RH |
4922 | } |
4923 | ||
8fc2e39e | 4924 | used_at = 1; |
67c0d1eb RS |
4925 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4926 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4927 | break; |
4928 | ||
8b082fb1 TS |
4929 | case M_BALIGN: |
4930 | switch (imm_expr.X_add_number) | |
4931 | { | |
4932 | case 0: | |
4933 | macro_build (NULL, "nop", ""); | |
4934 | break; | |
4935 | case 2: | |
4936 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4937 | break; | |
4938 | default: | |
4939 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
4940 | (int)imm_expr.X_add_number); | |
4941 | break; | |
4942 | } | |
4943 | break; | |
4944 | ||
252b5132 RH |
4945 | case M_BEQ_I: |
4946 | s = "beq"; | |
4947 | goto beq_i; | |
4948 | case M_BEQL_I: | |
4949 | s = "beql"; | |
4950 | likely = 1; | |
4951 | goto beq_i; | |
4952 | case M_BNE_I: | |
4953 | s = "bne"; | |
4954 | goto beq_i; | |
4955 | case M_BNEL_I: | |
4956 | s = "bnel"; | |
4957 | likely = 1; | |
4958 | beq_i: | |
4959 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4960 | { | |
67c0d1eb | 4961 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4962 | break; |
252b5132 | 4963 | } |
8fc2e39e | 4964 | used_at = 1; |
67c0d1eb RS |
4965 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4966 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4967 | break; |
4968 | ||
4969 | case M_BGEL: | |
4970 | likely = 1; | |
4971 | case M_BGE: | |
4972 | if (treg == 0) | |
4973 | { | |
67c0d1eb | 4974 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4975 | break; |
252b5132 RH |
4976 | } |
4977 | if (sreg == 0) | |
4978 | { | |
67c0d1eb | 4979 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4980 | break; |
252b5132 | 4981 | } |
8fc2e39e | 4982 | used_at = 1; |
67c0d1eb RS |
4983 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4984 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4985 | break; |
4986 | ||
4987 | case M_BGTL_I: | |
4988 | likely = 1; | |
4989 | case M_BGT_I: | |
4990 | /* check for > max integer */ | |
4991 | maxnum = 0x7fffffff; | |
ca4e0257 | 4992 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4993 | { |
4994 | maxnum <<= 16; | |
4995 | maxnum |= 0xffff; | |
4996 | maxnum <<= 16; | |
4997 | maxnum |= 0xffff; | |
4998 | } | |
4999 | if (imm_expr.X_op == O_constant | |
5000 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5001 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5002 | { |
5003 | do_false: | |
5004 | /* result is always false */ | |
5005 | if (! likely) | |
67c0d1eb | 5006 | macro_build (NULL, "nop", "", 0); |
252b5132 | 5007 | else |
67c0d1eb | 5008 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 5009 | break; |
252b5132 RH |
5010 | } |
5011 | if (imm_expr.X_op != O_constant) | |
5012 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5013 | ++imm_expr.X_add_number; |
252b5132 RH |
5014 | /* FALLTHROUGH */ |
5015 | case M_BGE_I: | |
5016 | case M_BGEL_I: | |
5017 | if (mask == M_BGEL_I) | |
5018 | likely = 1; | |
5019 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5020 | { | |
67c0d1eb | 5021 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 5022 | break; |
252b5132 RH |
5023 | } |
5024 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5025 | { | |
67c0d1eb | 5026 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5027 | break; |
252b5132 RH |
5028 | } |
5029 | maxnum = 0x7fffffff; | |
ca4e0257 | 5030 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5031 | { |
5032 | maxnum <<= 16; | |
5033 | maxnum |= 0xffff; | |
5034 | maxnum <<= 16; | |
5035 | maxnum |= 0xffff; | |
5036 | } | |
5037 | maxnum = - maxnum - 1; | |
5038 | if (imm_expr.X_op == O_constant | |
5039 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 5040 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5041 | { |
5042 | do_true: | |
5043 | /* result is always true */ | |
5044 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 5045 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5046 | break; |
252b5132 | 5047 | } |
8fc2e39e | 5048 | used_at = 1; |
67c0d1eb RS |
5049 | set_at (sreg, 0); |
5050 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5051 | break; |
5052 | ||
5053 | case M_BGEUL: | |
5054 | likely = 1; | |
5055 | case M_BGEU: | |
5056 | if (treg == 0) | |
5057 | goto do_true; | |
5058 | if (sreg == 0) | |
5059 | { | |
67c0d1eb | 5060 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 5061 | "s,t,p", 0, treg); |
8fc2e39e | 5062 | break; |
252b5132 | 5063 | } |
8fc2e39e | 5064 | used_at = 1; |
67c0d1eb RS |
5065 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
5066 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5067 | break; |
5068 | ||
5069 | case M_BGTUL_I: | |
5070 | likely = 1; | |
5071 | case M_BGTU_I: | |
5072 | if (sreg == 0 | |
ca4e0257 | 5073 | || (HAVE_32BIT_GPRS |
252b5132 | 5074 | && imm_expr.X_op == O_constant |
956cd1d6 | 5075 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
5076 | goto do_false; |
5077 | if (imm_expr.X_op != O_constant) | |
5078 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5079 | ++imm_expr.X_add_number; |
252b5132 RH |
5080 | /* FALLTHROUGH */ |
5081 | case M_BGEU_I: | |
5082 | case M_BGEUL_I: | |
5083 | if (mask == M_BGEUL_I) | |
5084 | likely = 1; | |
5085 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5086 | goto do_true; | |
5087 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5088 | { | |
67c0d1eb | 5089 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5090 | "s,t,p", sreg, 0); |
8fc2e39e | 5091 | break; |
252b5132 | 5092 | } |
8fc2e39e | 5093 | used_at = 1; |
67c0d1eb RS |
5094 | set_at (sreg, 1); |
5095 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5096 | break; |
5097 | ||
5098 | case M_BGTL: | |
5099 | likely = 1; | |
5100 | case M_BGT: | |
5101 | if (treg == 0) | |
5102 | { | |
67c0d1eb | 5103 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 5104 | break; |
252b5132 RH |
5105 | } |
5106 | if (sreg == 0) | |
5107 | { | |
67c0d1eb | 5108 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 5109 | break; |
252b5132 | 5110 | } |
8fc2e39e | 5111 | used_at = 1; |
67c0d1eb RS |
5112 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
5113 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5114 | break; |
5115 | ||
5116 | case M_BGTUL: | |
5117 | likely = 1; | |
5118 | case M_BGTU: | |
5119 | if (treg == 0) | |
5120 | { | |
67c0d1eb | 5121 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5122 | "s,t,p", sreg, 0); |
8fc2e39e | 5123 | break; |
252b5132 RH |
5124 | } |
5125 | if (sreg == 0) | |
5126 | goto do_false; | |
8fc2e39e | 5127 | used_at = 1; |
67c0d1eb RS |
5128 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
5129 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5130 | break; |
5131 | ||
5132 | case M_BLEL: | |
5133 | likely = 1; | |
5134 | case M_BLE: | |
5135 | if (treg == 0) | |
5136 | { | |
67c0d1eb | 5137 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5138 | break; |
252b5132 RH |
5139 | } |
5140 | if (sreg == 0) | |
5141 | { | |
67c0d1eb | 5142 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 5143 | break; |
252b5132 | 5144 | } |
8fc2e39e | 5145 | used_at = 1; |
67c0d1eb RS |
5146 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
5147 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5148 | break; |
5149 | ||
5150 | case M_BLEL_I: | |
5151 | likely = 1; | |
5152 | case M_BLE_I: | |
5153 | maxnum = 0x7fffffff; | |
ca4e0257 | 5154 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
5155 | { |
5156 | maxnum <<= 16; | |
5157 | maxnum |= 0xffff; | |
5158 | maxnum <<= 16; | |
5159 | maxnum |= 0xffff; | |
5160 | } | |
5161 | if (imm_expr.X_op == O_constant | |
5162 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 5163 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
5164 | goto do_true; |
5165 | if (imm_expr.X_op != O_constant) | |
5166 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5167 | ++imm_expr.X_add_number; |
252b5132 RH |
5168 | /* FALLTHROUGH */ |
5169 | case M_BLT_I: | |
5170 | case M_BLTL_I: | |
5171 | if (mask == M_BLTL_I) | |
5172 | likely = 1; | |
5173 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5174 | { | |
67c0d1eb | 5175 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5176 | break; |
252b5132 RH |
5177 | } |
5178 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5179 | { | |
67c0d1eb | 5180 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 5181 | break; |
252b5132 | 5182 | } |
8fc2e39e | 5183 | used_at = 1; |
67c0d1eb RS |
5184 | set_at (sreg, 0); |
5185 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5186 | break; |
5187 | ||
5188 | case M_BLEUL: | |
5189 | likely = 1; | |
5190 | case M_BLEU: | |
5191 | if (treg == 0) | |
5192 | { | |
67c0d1eb | 5193 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 5194 | "s,t,p", sreg, 0); |
8fc2e39e | 5195 | break; |
252b5132 RH |
5196 | } |
5197 | if (sreg == 0) | |
5198 | goto do_true; | |
8fc2e39e | 5199 | used_at = 1; |
67c0d1eb RS |
5200 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
5201 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
5202 | break; |
5203 | ||
5204 | case M_BLEUL_I: | |
5205 | likely = 1; | |
5206 | case M_BLEU_I: | |
5207 | if (sreg == 0 | |
ca4e0257 | 5208 | || (HAVE_32BIT_GPRS |
252b5132 | 5209 | && imm_expr.X_op == O_constant |
956cd1d6 | 5210 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
5211 | goto do_true; |
5212 | if (imm_expr.X_op != O_constant) | |
5213 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 5214 | ++imm_expr.X_add_number; |
252b5132 RH |
5215 | /* FALLTHROUGH */ |
5216 | case M_BLTU_I: | |
5217 | case M_BLTUL_I: | |
5218 | if (mask == M_BLTUL_I) | |
5219 | likely = 1; | |
5220 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5221 | goto do_false; | |
5222 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5223 | { | |
67c0d1eb | 5224 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 5225 | "s,t,p", sreg, 0); |
8fc2e39e | 5226 | break; |
252b5132 | 5227 | } |
8fc2e39e | 5228 | used_at = 1; |
67c0d1eb RS |
5229 | set_at (sreg, 1); |
5230 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5231 | break; |
5232 | ||
5233 | case M_BLTL: | |
5234 | likely = 1; | |
5235 | case M_BLT: | |
5236 | if (treg == 0) | |
5237 | { | |
67c0d1eb | 5238 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 5239 | break; |
252b5132 RH |
5240 | } |
5241 | if (sreg == 0) | |
5242 | { | |
67c0d1eb | 5243 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 5244 | break; |
252b5132 | 5245 | } |
8fc2e39e | 5246 | used_at = 1; |
67c0d1eb RS |
5247 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
5248 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5249 | break; |
5250 | ||
5251 | case M_BLTUL: | |
5252 | likely = 1; | |
5253 | case M_BLTU: | |
5254 | if (treg == 0) | |
5255 | goto do_false; | |
5256 | if (sreg == 0) | |
5257 | { | |
67c0d1eb | 5258 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 5259 | "s,t,p", 0, treg); |
8fc2e39e | 5260 | break; |
252b5132 | 5261 | } |
8fc2e39e | 5262 | used_at = 1; |
67c0d1eb RS |
5263 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
5264 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
5265 | break; |
5266 | ||
5f74bc13 CD |
5267 | case M_DEXT: |
5268 | { | |
5269 | unsigned long pos; | |
5270 | unsigned long size; | |
5271 | ||
5272 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5273 | { | |
5274 | as_bad (_("Unsupported large constant")); | |
5275 | pos = size = 1; | |
5276 | } | |
5277 | else | |
5278 | { | |
5279 | pos = (unsigned long) imm_expr.X_add_number; | |
5280 | size = (unsigned long) imm2_expr.X_add_number; | |
5281 | } | |
5282 | ||
5283 | if (pos > 63) | |
5284 | { | |
5285 | as_bad (_("Improper position (%lu)"), pos); | |
5286 | pos = 1; | |
5287 | } | |
5288 | if (size == 0 || size > 64 | |
5289 | || (pos + size - 1) > 63) | |
5290 | { | |
5291 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
5292 | size, pos); | |
5293 | size = 1; | |
5294 | } | |
5295 | ||
5296 | if (size <= 32 && pos < 32) | |
5297 | { | |
5298 | s = "dext"; | |
5299 | fmt = "t,r,+A,+C"; | |
5300 | } | |
5301 | else if (size <= 32) | |
5302 | { | |
5303 | s = "dextu"; | |
5304 | fmt = "t,r,+E,+H"; | |
5305 | } | |
5306 | else | |
5307 | { | |
5308 | s = "dextm"; | |
5309 | fmt = "t,r,+A,+G"; | |
5310 | } | |
67c0d1eb | 5311 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 5312 | } |
8fc2e39e | 5313 | break; |
5f74bc13 CD |
5314 | |
5315 | case M_DINS: | |
5316 | { | |
5317 | unsigned long pos; | |
5318 | unsigned long size; | |
5319 | ||
5320 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5321 | { | |
5322 | as_bad (_("Unsupported large constant")); | |
5323 | pos = size = 1; | |
5324 | } | |
5325 | else | |
5326 | { | |
5327 | pos = (unsigned long) imm_expr.X_add_number; | |
5328 | size = (unsigned long) imm2_expr.X_add_number; | |
5329 | } | |
5330 | ||
5331 | if (pos > 63) | |
5332 | { | |
5333 | as_bad (_("Improper position (%lu)"), pos); | |
5334 | pos = 1; | |
5335 | } | |
5336 | if (size == 0 || size > 64 | |
5337 | || (pos + size - 1) > 63) | |
5338 | { | |
5339 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5340 | size, pos); | |
5341 | size = 1; | |
5342 | } | |
5343 | ||
5344 | if (pos < 32 && (pos + size - 1) < 32) | |
5345 | { | |
5346 | s = "dins"; | |
5347 | fmt = "t,r,+A,+B"; | |
5348 | } | |
5349 | else if (pos >= 32) | |
5350 | { | |
5351 | s = "dinsu"; | |
5352 | fmt = "t,r,+E,+F"; | |
5353 | } | |
5354 | else | |
5355 | { | |
5356 | s = "dinsm"; | |
5357 | fmt = "t,r,+A,+F"; | |
5358 | } | |
750bdd57 AS |
5359 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
5360 | (int) (pos + size - 1)); | |
5f74bc13 | 5361 | } |
8fc2e39e | 5362 | break; |
5f74bc13 | 5363 | |
252b5132 RH |
5364 | case M_DDIV_3: |
5365 | dbl = 1; | |
5366 | case M_DIV_3: | |
5367 | s = "mflo"; | |
5368 | goto do_div3; | |
5369 | case M_DREM_3: | |
5370 | dbl = 1; | |
5371 | case M_REM_3: | |
5372 | s = "mfhi"; | |
5373 | do_div3: | |
5374 | if (treg == 0) | |
5375 | { | |
5376 | as_warn (_("Divide by zero.")); | |
5377 | if (mips_trap) | |
67c0d1eb | 5378 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5379 | else |
67c0d1eb | 5380 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5381 | break; |
252b5132 RH |
5382 | } |
5383 | ||
7d10b47d | 5384 | start_noreorder (); |
252b5132 RH |
5385 | if (mips_trap) |
5386 | { | |
67c0d1eb RS |
5387 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5388 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5389 | } |
5390 | else | |
5391 | { | |
5392 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5393 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5394 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5395 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5396 | } |
5397 | expr1.X_add_number = -1; | |
8fc2e39e | 5398 | used_at = 1; |
f6a22291 | 5399 | load_register (AT, &expr1, dbl); |
252b5132 | 5400 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5401 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5402 | if (dbl) |
5403 | { | |
5404 | expr1.X_add_number = 1; | |
f6a22291 | 5405 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5406 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5407 | } |
5408 | else | |
5409 | { | |
5410 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5411 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5412 | } |
5413 | if (mips_trap) | |
5414 | { | |
67c0d1eb | 5415 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5416 | /* We want to close the noreorder block as soon as possible, so |
5417 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5418 | end_noreorder (); |
252b5132 RH |
5419 | } |
5420 | else | |
5421 | { | |
5422 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5423 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5424 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5425 | |
5426 | /* We want to close the noreorder block as soon as possible, so | |
5427 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5428 | end_noreorder (); |
252b5132 | 5429 | |
67c0d1eb | 5430 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5431 | } |
67c0d1eb | 5432 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5433 | break; |
5434 | ||
5435 | case M_DIV_3I: | |
5436 | s = "div"; | |
5437 | s2 = "mflo"; | |
5438 | goto do_divi; | |
5439 | case M_DIVU_3I: | |
5440 | s = "divu"; | |
5441 | s2 = "mflo"; | |
5442 | goto do_divi; | |
5443 | case M_REM_3I: | |
5444 | s = "div"; | |
5445 | s2 = "mfhi"; | |
5446 | goto do_divi; | |
5447 | case M_REMU_3I: | |
5448 | s = "divu"; | |
5449 | s2 = "mfhi"; | |
5450 | goto do_divi; | |
5451 | case M_DDIV_3I: | |
5452 | dbl = 1; | |
5453 | s = "ddiv"; | |
5454 | s2 = "mflo"; | |
5455 | goto do_divi; | |
5456 | case M_DDIVU_3I: | |
5457 | dbl = 1; | |
5458 | s = "ddivu"; | |
5459 | s2 = "mflo"; | |
5460 | goto do_divi; | |
5461 | case M_DREM_3I: | |
5462 | dbl = 1; | |
5463 | s = "ddiv"; | |
5464 | s2 = "mfhi"; | |
5465 | goto do_divi; | |
5466 | case M_DREMU_3I: | |
5467 | dbl = 1; | |
5468 | s = "ddivu"; | |
5469 | s2 = "mfhi"; | |
5470 | do_divi: | |
5471 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5472 | { | |
5473 | as_warn (_("Divide by zero.")); | |
5474 | if (mips_trap) | |
67c0d1eb | 5475 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5476 | else |
67c0d1eb | 5477 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5478 | break; |
252b5132 RH |
5479 | } |
5480 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5481 | { | |
5482 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5483 | move_register (dreg, sreg); |
252b5132 | 5484 | else |
67c0d1eb | 5485 | move_register (dreg, 0); |
8fc2e39e | 5486 | break; |
252b5132 RH |
5487 | } |
5488 | if (imm_expr.X_op == O_constant | |
5489 | && imm_expr.X_add_number == -1 | |
5490 | && s[strlen (s) - 1] != 'u') | |
5491 | { | |
5492 | if (strcmp (s2, "mflo") == 0) | |
5493 | { | |
67c0d1eb | 5494 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5495 | } |
5496 | else | |
67c0d1eb | 5497 | move_register (dreg, 0); |
8fc2e39e | 5498 | break; |
252b5132 RH |
5499 | } |
5500 | ||
8fc2e39e | 5501 | used_at = 1; |
67c0d1eb RS |
5502 | load_register (AT, &imm_expr, dbl); |
5503 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5504 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5505 | break; |
5506 | ||
5507 | case M_DIVU_3: | |
5508 | s = "divu"; | |
5509 | s2 = "mflo"; | |
5510 | goto do_divu3; | |
5511 | case M_REMU_3: | |
5512 | s = "divu"; | |
5513 | s2 = "mfhi"; | |
5514 | goto do_divu3; | |
5515 | case M_DDIVU_3: | |
5516 | s = "ddivu"; | |
5517 | s2 = "mflo"; | |
5518 | goto do_divu3; | |
5519 | case M_DREMU_3: | |
5520 | s = "ddivu"; | |
5521 | s2 = "mfhi"; | |
5522 | do_divu3: | |
7d10b47d | 5523 | start_noreorder (); |
252b5132 RH |
5524 | if (mips_trap) |
5525 | { | |
67c0d1eb RS |
5526 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5527 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5528 | /* We want to close the noreorder block as soon as possible, so |
5529 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5530 | end_noreorder (); |
252b5132 RH |
5531 | } |
5532 | else | |
5533 | { | |
5534 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5535 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5536 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5537 | |
5538 | /* We want to close the noreorder block as soon as possible, so | |
5539 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5540 | end_noreorder (); |
67c0d1eb | 5541 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5542 | } |
67c0d1eb | 5543 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5544 | break; |
252b5132 | 5545 | |
1abe91b1 MR |
5546 | case M_DLCA_AB: |
5547 | dbl = 1; | |
5548 | case M_LCA_AB: | |
5549 | call = 1; | |
5550 | goto do_la; | |
252b5132 RH |
5551 | case M_DLA_AB: |
5552 | dbl = 1; | |
5553 | case M_LA_AB: | |
1abe91b1 | 5554 | do_la: |
252b5132 RH |
5555 | /* Load the address of a symbol into a register. If breg is not |
5556 | zero, we then add a base register to it. */ | |
5557 | ||
3bec30a8 TS |
5558 | if (dbl && HAVE_32BIT_GPRS) |
5559 | as_warn (_("dla used to load 32-bit register")); | |
5560 | ||
c90bbe5b | 5561 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5562 | as_warn (_("la used to load 64-bit address")); |
5563 | ||
0c11417f MR |
5564 | if (offset_expr.X_op == O_constant |
5565 | && offset_expr.X_add_number >= -0x8000 | |
5566 | && offset_expr.X_add_number < 0x8000) | |
5567 | { | |
aed1a261 | 5568 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5569 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5570 | break; |
0c11417f MR |
5571 | } |
5572 | ||
741fe287 | 5573 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
5574 | { |
5575 | tempreg = AT; | |
5576 | used_at = 1; | |
5577 | } | |
5578 | else | |
5579 | { | |
5580 | tempreg = treg; | |
afdbd6d0 CD |
5581 | } |
5582 | ||
252b5132 RH |
5583 | if (offset_expr.X_op != O_symbol |
5584 | && offset_expr.X_op != O_constant) | |
5585 | { | |
5586 | as_bad (_("expression too complex")); | |
5587 | offset_expr.X_op = O_constant; | |
5588 | } | |
5589 | ||
252b5132 | 5590 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5591 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5592 | else if (mips_pic == NO_PIC) |
5593 | { | |
d6bc6245 | 5594 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5595 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5596 | Otherwise we want |
5597 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5598 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5599 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5600 | so we may as well always use the latter form. |
76b3015f | 5601 | |
6caf9ef4 TS |
5602 | With 64bit address space and a usable $at we want |
5603 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5604 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5605 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5606 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5607 | dsll32 $tempreg,0 | |
5608 | daddu $tempreg,$tempreg,$at | |
5609 | ||
5610 | If $at is already in use, we use a path which is suboptimal | |
5611 | on superscalar processors. | |
5612 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5613 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5614 | dsll $tempreg,16 | |
5615 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5616 | dsll $tempreg,16 | |
5617 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5618 | ||
5619 | For GP relative symbols in 64bit address space we can use | |
5620 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5621 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5622 | { |
6caf9ef4 TS |
5623 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5624 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5625 | { | |
5626 | relax_start (offset_expr.X_add_symbol); | |
5627 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5628 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5629 | relax_switch (); | |
5630 | } | |
d6bc6245 | 5631 | |
741fe287 | 5632 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 5633 | { |
67c0d1eb | 5634 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5635 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5636 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5637 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5638 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5639 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5640 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5641 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5642 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5643 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5644 | used_at = 1; |
5645 | } | |
5646 | else | |
5647 | { | |
67c0d1eb | 5648 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5649 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5650 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5651 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5652 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5653 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5654 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5655 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5656 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5657 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5658 | } |
6caf9ef4 TS |
5659 | |
5660 | if (mips_relax.sequence) | |
5661 | relax_end (); | |
98d3f06f KH |
5662 | } |
5663 | else | |
5664 | { | |
5665 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5666 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5667 | { |
4d7206a2 | 5668 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5669 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5670 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5671 | relax_switch (); |
98d3f06f | 5672 | } |
6943caf0 ILT |
5673 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5674 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5675 | macro_build_lui (&offset_expr, tempreg); |
5676 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5677 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5678 | if (mips_relax.sequence) |
5679 | relax_end (); | |
98d3f06f | 5680 | } |
252b5132 | 5681 | } |
0a44bf69 | 5682 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5683 | { |
9117d219 NC |
5684 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5685 | ||
252b5132 RH |
5686 | /* If this is a reference to an external symbol, and there |
5687 | is no constant, we want | |
5688 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5689 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5690 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5691 | For a local symbol, we want |
5692 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5693 | nop | |
5694 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5695 | ||
5696 | If we have a small constant, and this is a reference to | |
5697 | an external symbol, we want | |
5698 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5699 | nop | |
5700 | addiu $tempreg,$tempreg,<constant> | |
5701 | For a local symbol, we want the same instruction | |
5702 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5703 | addiu instruction. | |
5704 | ||
5705 | If we have a large constant, and this is a reference to | |
5706 | an external symbol, we want | |
5707 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5708 | lui $at,<hiconstant> | |
5709 | addiu $at,$at,<loconstant> | |
5710 | addu $tempreg,$tempreg,$at | |
5711 | For a local symbol, we want the same instruction | |
5712 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5713 | addiu instruction. |
ed6fb7bd SC |
5714 | */ |
5715 | ||
4d7206a2 | 5716 | if (offset_expr.X_add_number == 0) |
252b5132 | 5717 | { |
0a44bf69 RS |
5718 | if (mips_pic == SVR4_PIC |
5719 | && breg == 0 | |
5720 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5721 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5722 | ||
5723 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5724 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5725 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5726 | if (breg != 0) |
252b5132 RH |
5727 | { |
5728 | /* We're going to put in an addu instruction using | |
5729 | tempreg, so we may as well insert the nop right | |
5730 | now. */ | |
269137b2 | 5731 | load_delay_nop (); |
252b5132 | 5732 | } |
4d7206a2 | 5733 | relax_switch (); |
67c0d1eb RS |
5734 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5735 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5736 | load_delay_nop (); |
67c0d1eb RS |
5737 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5738 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5739 | relax_end (); |
252b5132 RH |
5740 | /* FIXME: If breg == 0, and the next instruction uses |
5741 | $tempreg, then if this variant case is used an extra | |
5742 | nop will be generated. */ | |
5743 | } | |
4d7206a2 RS |
5744 | else if (offset_expr.X_add_number >= -0x8000 |
5745 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5746 | { |
67c0d1eb | 5747 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5748 | load_delay_nop (); |
67c0d1eb | 5749 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5750 | } |
5751 | else | |
5752 | { | |
4d7206a2 RS |
5753 | expr1.X_add_number = offset_expr.X_add_number; |
5754 | offset_expr.X_add_number = | |
5755 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5756 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5757 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5758 | /* If we are going to add in a base register, and the |
5759 | target register and the base register are the same, | |
5760 | then we are using AT as a temporary register. Since | |
5761 | we want to load the constant into AT, we add our | |
5762 | current AT (from the global offset table) and the | |
5763 | register into the register now, and pretend we were | |
5764 | not using a base register. */ | |
67c0d1eb | 5765 | if (breg == treg) |
252b5132 | 5766 | { |
269137b2 | 5767 | load_delay_nop (); |
67c0d1eb | 5768 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5769 | treg, AT, breg); |
252b5132 RH |
5770 | breg = 0; |
5771 | tempreg = treg; | |
252b5132 | 5772 | } |
f6a22291 | 5773 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5774 | used_at = 1; |
5775 | } | |
5776 | } | |
0a44bf69 | 5777 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5778 | { |
67c0d1eb | 5779 | int add_breg_early = 0; |
f5040a92 AO |
5780 | |
5781 | /* If this is a reference to an external, and there is no | |
5782 | constant, or local symbol (*), with or without a | |
5783 | constant, we want | |
5784 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5785 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5786 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5787 | ||
5788 | If we have a small constant, and this is a reference to | |
5789 | an external symbol, we want | |
5790 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5791 | addiu $tempreg,$tempreg,<constant> | |
5792 | ||
5793 | If we have a large constant, and this is a reference to | |
5794 | an external symbol, we want | |
5795 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5796 | lui $at,<hiconstant> | |
5797 | addiu $at,$at,<loconstant> | |
5798 | addu $tempreg,$tempreg,$at | |
5799 | ||
5800 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5801 | local symbols, even though it introduces an additional | |
5802 | instruction. */ | |
5803 | ||
f5040a92 AO |
5804 | if (offset_expr.X_add_number) |
5805 | { | |
4d7206a2 | 5806 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5807 | offset_expr.X_add_number = 0; |
5808 | ||
4d7206a2 | 5809 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5810 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5811 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5812 | |
5813 | if (expr1.X_add_number >= -0x8000 | |
5814 | && expr1.X_add_number < 0x8000) | |
5815 | { | |
67c0d1eb RS |
5816 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5817 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5818 | } |
ecd13cd3 | 5819 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 5820 | { |
f5040a92 AO |
5821 | /* If we are going to add in a base register, and the |
5822 | target register and the base register are the same, | |
5823 | then we are using AT as a temporary register. Since | |
5824 | we want to load the constant into AT, we add our | |
5825 | current AT (from the global offset table) and the | |
5826 | register into the register now, and pretend we were | |
5827 | not using a base register. */ | |
5828 | if (breg != treg) | |
5829 | dreg = tempreg; | |
5830 | else | |
5831 | { | |
9c2799c2 | 5832 | gas_assert (tempreg == AT); |
67c0d1eb RS |
5833 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5834 | treg, AT, breg); | |
f5040a92 | 5835 | dreg = treg; |
67c0d1eb | 5836 | add_breg_early = 1; |
f5040a92 AO |
5837 | } |
5838 | ||
f6a22291 | 5839 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5840 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5841 | dreg, dreg, AT); |
f5040a92 | 5842 | |
f5040a92 AO |
5843 | used_at = 1; |
5844 | } | |
5845 | else | |
5846 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5847 | ||
4d7206a2 | 5848 | relax_switch (); |
f5040a92 AO |
5849 | offset_expr.X_add_number = expr1.X_add_number; |
5850 | ||
67c0d1eb RS |
5851 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5852 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5853 | if (add_breg_early) | |
f5040a92 | 5854 | { |
67c0d1eb | 5855 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5856 | treg, tempreg, breg); |
f5040a92 AO |
5857 | breg = 0; |
5858 | tempreg = treg; | |
5859 | } | |
4d7206a2 | 5860 | relax_end (); |
f5040a92 | 5861 | } |
4d7206a2 | 5862 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5863 | { |
4d7206a2 | 5864 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5865 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5866 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5867 | relax_switch (); |
67c0d1eb RS |
5868 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5869 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5870 | relax_end (); |
f5040a92 | 5871 | } |
4d7206a2 | 5872 | else |
f5040a92 | 5873 | { |
67c0d1eb RS |
5874 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5875 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5876 | } |
5877 | } | |
0a44bf69 | 5878 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5879 | { |
67c0d1eb | 5880 | int gpdelay; |
9117d219 NC |
5881 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5882 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5883 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5884 | |
5885 | /* This is the large GOT case. If this is a reference to an | |
5886 | external symbol, and there is no constant, we want | |
5887 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5888 | addu $tempreg,$tempreg,$gp | |
5889 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5890 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5891 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5892 | addu $tempreg,$tempreg,$gp | |
5893 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5894 | For a local symbol, we want |
5895 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5896 | nop | |
5897 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5898 | ||
5899 | If we have a small constant, and this is a reference to | |
5900 | an external symbol, we want | |
5901 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5902 | addu $tempreg,$tempreg,$gp | |
5903 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5904 | nop | |
5905 | addiu $tempreg,$tempreg,<constant> | |
5906 | For a local symbol, we want | |
5907 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5908 | nop | |
5909 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5910 | ||
5911 | If we have a large constant, and this is a reference to | |
5912 | an external symbol, we want | |
5913 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5914 | addu $tempreg,$tempreg,$gp | |
5915 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5916 | lui $at,<hiconstant> | |
5917 | addiu $at,$at,<loconstant> | |
5918 | addu $tempreg,$tempreg,$at | |
5919 | For a local symbol, we want | |
5920 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5921 | lui $at,<hiconstant> | |
5922 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5923 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5924 | */ |
438c16b8 | 5925 | |
252b5132 RH |
5926 | expr1.X_add_number = offset_expr.X_add_number; |
5927 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5928 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5929 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5930 | if (expr1.X_add_number == 0 && breg == 0 |
5931 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5932 | { |
5933 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5934 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5935 | } | |
67c0d1eb RS |
5936 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5937 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5938 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5939 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5940 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5941 | if (expr1.X_add_number == 0) |
5942 | { | |
67c0d1eb | 5943 | if (breg != 0) |
252b5132 RH |
5944 | { |
5945 | /* We're going to put in an addu instruction using | |
5946 | tempreg, so we may as well insert the nop right | |
5947 | now. */ | |
269137b2 | 5948 | load_delay_nop (); |
252b5132 | 5949 | } |
252b5132 RH |
5950 | } |
5951 | else if (expr1.X_add_number >= -0x8000 | |
5952 | && expr1.X_add_number < 0x8000) | |
5953 | { | |
269137b2 | 5954 | load_delay_nop (); |
67c0d1eb | 5955 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5956 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5957 | } |
5958 | else | |
5959 | { | |
252b5132 RH |
5960 | /* If we are going to add in a base register, and the |
5961 | target register and the base register are the same, | |
5962 | then we are using AT as a temporary register. Since | |
5963 | we want to load the constant into AT, we add our | |
5964 | current AT (from the global offset table) and the | |
5965 | register into the register now, and pretend we were | |
5966 | not using a base register. */ | |
5967 | if (breg != treg) | |
67c0d1eb | 5968 | dreg = tempreg; |
252b5132 RH |
5969 | else |
5970 | { | |
9c2799c2 | 5971 | gas_assert (tempreg == AT); |
269137b2 | 5972 | load_delay_nop (); |
67c0d1eb | 5973 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5974 | treg, AT, breg); |
252b5132 | 5975 | dreg = treg; |
252b5132 RH |
5976 | } |
5977 | ||
f6a22291 | 5978 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5979 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5980 | |
252b5132 RH |
5981 | used_at = 1; |
5982 | } | |
4d7206a2 RS |
5983 | offset_expr.X_add_number = |
5984 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5985 | relax_switch (); | |
252b5132 | 5986 | |
67c0d1eb | 5987 | if (gpdelay) |
252b5132 RH |
5988 | { |
5989 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5990 | the first instruction on the main stream does not. */ |
67c0d1eb | 5991 | macro_build (NULL, "nop", ""); |
252b5132 | 5992 | } |
ed6fb7bd | 5993 | |
67c0d1eb RS |
5994 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5995 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5996 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5997 | && expr1.X_add_number < 0x8000) |
5998 | { | |
269137b2 | 5999 | load_delay_nop (); |
67c0d1eb RS |
6000 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6001 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 6002 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
6003 | register, the external symbol case ended with a load, |
6004 | so if the symbol turns out to not be external, and | |
6005 | the next instruction uses tempreg, an unnecessary nop | |
6006 | will be inserted. */ | |
252b5132 RH |
6007 | } |
6008 | else | |
6009 | { | |
6010 | if (breg == treg) | |
6011 | { | |
6012 | /* We must add in the base register now, as in the | |
f5040a92 | 6013 | external symbol case. */ |
9c2799c2 | 6014 | gas_assert (tempreg == AT); |
269137b2 | 6015 | load_delay_nop (); |
67c0d1eb | 6016 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6017 | treg, AT, breg); |
252b5132 RH |
6018 | tempreg = treg; |
6019 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 6020 | it in in both cases. */ |
252b5132 RH |
6021 | breg = 0; |
6022 | } | |
6023 | ||
67c0d1eb RS |
6024 | macro_build_lui (&expr1, AT); |
6025 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 6026 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 6027 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6028 | tempreg, tempreg, AT); |
8fc2e39e | 6029 | used_at = 1; |
252b5132 | 6030 | } |
4d7206a2 | 6031 | relax_end (); |
252b5132 | 6032 | } |
0a44bf69 | 6033 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6034 | { |
f5040a92 AO |
6035 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
6036 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 6037 | int add_breg_early = 0; |
f5040a92 AO |
6038 | |
6039 | /* This is the large GOT case. If this is a reference to an | |
6040 | external symbol, and there is no constant, we want | |
6041 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6042 | add $tempreg,$tempreg,$gp | |
6043 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 6044 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
6045 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
6046 | add $tempreg,$tempreg,$gp | |
6047 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
6048 | ||
6049 | If we have a small constant, and this is a reference to | |
6050 | an external symbol, we want | |
6051 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6052 | add $tempreg,$tempreg,$gp | |
6053 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6054 | addi $tempreg,$tempreg,<constant> | |
6055 | ||
6056 | If we have a large constant, and this is a reference to | |
6057 | an external symbol, we want | |
6058 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6059 | addu $tempreg,$tempreg,$gp | |
6060 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6061 | lui $at,<hiconstant> | |
6062 | addi $at,$at,<loconstant> | |
6063 | add $tempreg,$tempreg,$at | |
6064 | ||
6065 | If we have NewABI, and we know it's a local symbol, we want | |
6066 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6067 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
6068 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
6069 | ||
4d7206a2 | 6070 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 6071 | |
4d7206a2 | 6072 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6073 | offset_expr.X_add_number = 0; |
6074 | ||
1abe91b1 MR |
6075 | if (expr1.X_add_number == 0 && breg == 0 |
6076 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
6077 | { |
6078 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
6079 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
6080 | } | |
67c0d1eb RS |
6081 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
6082 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6083 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
6084 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6085 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
6086 | |
6087 | if (expr1.X_add_number == 0) | |
4d7206a2 | 6088 | ; |
f5040a92 AO |
6089 | else if (expr1.X_add_number >= -0x8000 |
6090 | && expr1.X_add_number < 0x8000) | |
6091 | { | |
67c0d1eb | 6092 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6093 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 6094 | } |
ecd13cd3 | 6095 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 6096 | { |
f5040a92 AO |
6097 | /* If we are going to add in a base register, and the |
6098 | target register and the base register are the same, | |
6099 | then we are using AT as a temporary register. Since | |
6100 | we want to load the constant into AT, we add our | |
6101 | current AT (from the global offset table) and the | |
6102 | register into the register now, and pretend we were | |
6103 | not using a base register. */ | |
6104 | if (breg != treg) | |
6105 | dreg = tempreg; | |
6106 | else | |
6107 | { | |
9c2799c2 | 6108 | gas_assert (tempreg == AT); |
67c0d1eb | 6109 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6110 | treg, AT, breg); |
f5040a92 | 6111 | dreg = treg; |
67c0d1eb | 6112 | add_breg_early = 1; |
f5040a92 AO |
6113 | } |
6114 | ||
f6a22291 | 6115 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 6116 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 6117 | |
f5040a92 AO |
6118 | used_at = 1; |
6119 | } | |
6120 | else | |
6121 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
6122 | ||
4d7206a2 | 6123 | relax_switch (); |
f5040a92 | 6124 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6125 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6126 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
6127 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
6128 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
6129 | if (add_breg_early) | |
f5040a92 | 6130 | { |
67c0d1eb | 6131 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6132 | treg, tempreg, breg); |
f5040a92 AO |
6133 | breg = 0; |
6134 | tempreg = treg; | |
6135 | } | |
4d7206a2 | 6136 | relax_end (); |
f5040a92 | 6137 | } |
252b5132 RH |
6138 | else |
6139 | abort (); | |
6140 | ||
6141 | if (breg != 0) | |
aed1a261 | 6142 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
6143 | break; |
6144 | ||
52b6b6b9 JM |
6145 | case M_MSGSND: |
6146 | { | |
6147 | unsigned long temp = (treg << 16) | (0x01); | |
6148 | macro_build (NULL, "c2", "C", temp); | |
6149 | } | |
6150 | /* AT is not used, just return */ | |
6151 | return; | |
6152 | ||
6153 | case M_MSGLD: | |
6154 | { | |
6155 | unsigned long temp = (0x02); | |
6156 | macro_build (NULL, "c2", "C", temp); | |
6157 | } | |
6158 | /* AT is not used, just return */ | |
6159 | return; | |
6160 | ||
6161 | case M_MSGLD_T: | |
6162 | { | |
6163 | unsigned long temp = (treg << 16) | (0x02); | |
6164 | macro_build (NULL, "c2", "C", temp); | |
6165 | } | |
6166 | /* AT is not used, just return */ | |
6167 | return; | |
6168 | ||
6169 | case M_MSGWAIT: | |
6170 | macro_build (NULL, "c2", "C", 3); | |
6171 | /* AT is not used, just return */ | |
6172 | return; | |
6173 | ||
6174 | case M_MSGWAIT_T: | |
6175 | { | |
6176 | unsigned long temp = (treg << 16) | 0x03; | |
6177 | macro_build (NULL, "c2", "C", temp); | |
6178 | } | |
6179 | /* AT is not used, just return */ | |
6180 | return; | |
6181 | ||
252b5132 RH |
6182 | case M_J_A: |
6183 | /* The j instruction may not be used in PIC code, since it | |
6184 | requires an absolute address. We convert it to a b | |
6185 | instruction. */ | |
6186 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6187 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 6188 | else |
67c0d1eb | 6189 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6190 | break; |
252b5132 RH |
6191 | |
6192 | /* The jal instructions must be handled as macros because when | |
6193 | generating PIC code they expand to multi-instruction | |
6194 | sequences. Normally they are simple instructions. */ | |
6195 | case M_JAL_1: | |
6196 | dreg = RA; | |
6197 | /* Fall through. */ | |
6198 | case M_JAL_2: | |
3e722fb5 | 6199 | if (mips_pic == NO_PIC) |
67c0d1eb | 6200 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6201 | else |
252b5132 RH |
6202 | { |
6203 | if (sreg != PIC_CALL_REG) | |
6204 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 6205 | |
67c0d1eb | 6206 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 6207 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 6208 | { |
6478892d TS |
6209 | if (mips_cprestore_offset < 0) |
6210 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6211 | else | |
6212 | { | |
7a621144 DJ |
6213 | if (! mips_frame_reg_valid) |
6214 | { | |
6215 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6216 | /* Quiet this warning. */ | |
6217 | mips_frame_reg_valid = 1; | |
6218 | } | |
6219 | if (! mips_cprestore_valid) | |
6220 | { | |
6221 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6222 | /* Quiet this warning. */ | |
6223 | mips_cprestore_valid = 1; | |
6224 | } | |
d3fca0b5 MR |
6225 | if (mips_opts.noreorder) |
6226 | macro_build (NULL, "nop", ""); | |
6478892d | 6227 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6228 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6229 | mips_gp_register, |
256ab948 TS |
6230 | mips_frame_reg, |
6231 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6232 | } |
252b5132 RH |
6233 | } |
6234 | } | |
252b5132 | 6235 | |
8fc2e39e | 6236 | break; |
252b5132 RH |
6237 | |
6238 | case M_JAL_A: | |
6239 | if (mips_pic == NO_PIC) | |
67c0d1eb | 6240 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
6241 | else if (mips_pic == SVR4_PIC) |
6242 | { | |
6243 | /* If this is a reference to an external symbol, and we are | |
6244 | using a small GOT, we want | |
6245 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
6246 | nop | |
f9419b05 | 6247 | jalr $ra,$25 |
252b5132 RH |
6248 | nop |
6249 | lw $gp,cprestore($sp) | |
6250 | The cprestore value is set using the .cprestore | |
6251 | pseudo-op. If we are using a big GOT, we want | |
6252 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
6253 | addu $25,$25,$gp | |
6254 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
6255 | nop | |
f9419b05 | 6256 | jalr $ra,$25 |
252b5132 RH |
6257 | nop |
6258 | lw $gp,cprestore($sp) | |
6259 | If the symbol is not external, we want | |
6260 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6261 | nop | |
6262 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 6263 | jalr $ra,$25 |
252b5132 | 6264 | nop |
438c16b8 | 6265 | lw $gp,cprestore($sp) |
f5040a92 AO |
6266 | |
6267 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
6268 | sequences above, minus nops, unless the symbol is local, | |
6269 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
6270 | GOT_DISP. */ | |
438c16b8 | 6271 | if (HAVE_NEWABI) |
252b5132 | 6272 | { |
f5040a92 AO |
6273 | if (! mips_big_got) |
6274 | { | |
4d7206a2 | 6275 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6276 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6277 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 6278 | mips_gp_register); |
4d7206a2 | 6279 | relax_switch (); |
67c0d1eb RS |
6280 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6281 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
6282 | mips_gp_register); |
6283 | relax_end (); | |
f5040a92 AO |
6284 | } |
6285 | else | |
6286 | { | |
4d7206a2 | 6287 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6288 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
6289 | BFD_RELOC_MIPS_CALL_HI16); | |
6290 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6291 | PIC_CALL_REG, mips_gp_register); | |
6292 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6293 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6294 | PIC_CALL_REG); | |
4d7206a2 | 6295 | relax_switch (); |
67c0d1eb RS |
6296 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6297 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
6298 | mips_gp_register); | |
6299 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
6300 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 6301 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 6302 | relax_end (); |
f5040a92 | 6303 | } |
684022ea | 6304 | |
67c0d1eb | 6305 | macro_build_jalr (&offset_expr); |
252b5132 RH |
6306 | } |
6307 | else | |
6308 | { | |
4d7206a2 | 6309 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
6310 | if (! mips_big_got) |
6311 | { | |
67c0d1eb RS |
6312 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6313 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 6314 | mips_gp_register); |
269137b2 | 6315 | load_delay_nop (); |
4d7206a2 | 6316 | relax_switch (); |
438c16b8 | 6317 | } |
252b5132 | 6318 | else |
252b5132 | 6319 | { |
67c0d1eb RS |
6320 | int gpdelay; |
6321 | ||
6322 | gpdelay = reg_needs_delay (mips_gp_register); | |
6323 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6324 | BFD_RELOC_MIPS_CALL_HI16); | |
6325 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6326 | PIC_CALL_REG, mips_gp_register); | |
6327 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6328 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6329 | PIC_CALL_REG); | |
269137b2 | 6330 | load_delay_nop (); |
4d7206a2 | 6331 | relax_switch (); |
67c0d1eb RS |
6332 | if (gpdelay) |
6333 | macro_build (NULL, "nop", ""); | |
252b5132 | 6334 | } |
67c0d1eb RS |
6335 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6336 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6337 | mips_gp_register); |
269137b2 | 6338 | load_delay_nop (); |
67c0d1eb RS |
6339 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6340 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6341 | relax_end (); |
67c0d1eb | 6342 | macro_build_jalr (&offset_expr); |
438c16b8 | 6343 | |
6478892d TS |
6344 | if (mips_cprestore_offset < 0) |
6345 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6346 | else | |
6347 | { | |
7a621144 DJ |
6348 | if (! mips_frame_reg_valid) |
6349 | { | |
6350 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6351 | /* Quiet this warning. */ | |
6352 | mips_frame_reg_valid = 1; | |
6353 | } | |
6354 | if (! mips_cprestore_valid) | |
6355 | { | |
6356 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6357 | /* Quiet this warning. */ | |
6358 | mips_cprestore_valid = 1; | |
6359 | } | |
6478892d | 6360 | if (mips_opts.noreorder) |
67c0d1eb | 6361 | macro_build (NULL, "nop", ""); |
6478892d | 6362 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6363 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6364 | mips_gp_register, |
256ab948 TS |
6365 | mips_frame_reg, |
6366 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6367 | } |
252b5132 RH |
6368 | } |
6369 | } | |
0a44bf69 RS |
6370 | else if (mips_pic == VXWORKS_PIC) |
6371 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6372 | else |
6373 | abort (); | |
6374 | ||
8fc2e39e | 6375 | break; |
252b5132 RH |
6376 | |
6377 | case M_LB_AB: | |
6378 | s = "lb"; | |
6379 | goto ld; | |
6380 | case M_LBU_AB: | |
6381 | s = "lbu"; | |
6382 | goto ld; | |
6383 | case M_LH_AB: | |
6384 | s = "lh"; | |
6385 | goto ld; | |
6386 | case M_LHU_AB: | |
6387 | s = "lhu"; | |
6388 | goto ld; | |
6389 | case M_LW_AB: | |
6390 | s = "lw"; | |
6391 | goto ld; | |
6392 | case M_LWC0_AB: | |
6393 | s = "lwc0"; | |
bdaaa2e1 | 6394 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6395 | coproc = 1; |
6396 | goto ld; | |
6397 | case M_LWC1_AB: | |
6398 | s = "lwc1"; | |
bdaaa2e1 | 6399 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6400 | coproc = 1; |
6401 | goto ld; | |
6402 | case M_LWC2_AB: | |
6403 | s = "lwc2"; | |
bdaaa2e1 | 6404 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6405 | coproc = 1; |
6406 | goto ld; | |
6407 | case M_LWC3_AB: | |
6408 | s = "lwc3"; | |
bdaaa2e1 | 6409 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6410 | coproc = 1; |
6411 | goto ld; | |
6412 | case M_LWL_AB: | |
6413 | s = "lwl"; | |
6414 | lr = 1; | |
6415 | goto ld; | |
6416 | case M_LWR_AB: | |
6417 | s = "lwr"; | |
6418 | lr = 1; | |
6419 | goto ld; | |
6420 | case M_LDC1_AB: | |
252b5132 | 6421 | s = "ldc1"; |
bdaaa2e1 | 6422 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6423 | coproc = 1; |
6424 | goto ld; | |
6425 | case M_LDC2_AB: | |
6426 | s = "ldc2"; | |
bdaaa2e1 | 6427 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6428 | coproc = 1; |
6429 | goto ld; | |
6430 | case M_LDC3_AB: | |
6431 | s = "ldc3"; | |
bdaaa2e1 | 6432 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6433 | coproc = 1; |
6434 | goto ld; | |
6435 | case M_LDL_AB: | |
6436 | s = "ldl"; | |
6437 | lr = 1; | |
6438 | goto ld; | |
6439 | case M_LDR_AB: | |
6440 | s = "ldr"; | |
6441 | lr = 1; | |
6442 | goto ld; | |
6443 | case M_LL_AB: | |
6444 | s = "ll"; | |
6445 | goto ld; | |
6446 | case M_LLD_AB: | |
6447 | s = "lld"; | |
6448 | goto ld; | |
6449 | case M_LWU_AB: | |
6450 | s = "lwu"; | |
6451 | ld: | |
8fc2e39e | 6452 | if (breg == treg || coproc || lr) |
252b5132 RH |
6453 | { |
6454 | tempreg = AT; | |
6455 | used_at = 1; | |
6456 | } | |
6457 | else | |
6458 | { | |
6459 | tempreg = treg; | |
252b5132 RH |
6460 | } |
6461 | goto ld_st; | |
6462 | case M_SB_AB: | |
6463 | s = "sb"; | |
6464 | goto st; | |
6465 | case M_SH_AB: | |
6466 | s = "sh"; | |
6467 | goto st; | |
6468 | case M_SW_AB: | |
6469 | s = "sw"; | |
6470 | goto st; | |
6471 | case M_SWC0_AB: | |
6472 | s = "swc0"; | |
bdaaa2e1 | 6473 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6474 | coproc = 1; |
6475 | goto st; | |
6476 | case M_SWC1_AB: | |
6477 | s = "swc1"; | |
bdaaa2e1 | 6478 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6479 | coproc = 1; |
6480 | goto st; | |
6481 | case M_SWC2_AB: | |
6482 | s = "swc2"; | |
bdaaa2e1 | 6483 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6484 | coproc = 1; |
6485 | goto st; | |
6486 | case M_SWC3_AB: | |
6487 | s = "swc3"; | |
bdaaa2e1 | 6488 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6489 | coproc = 1; |
6490 | goto st; | |
6491 | case M_SWL_AB: | |
6492 | s = "swl"; | |
6493 | goto st; | |
6494 | case M_SWR_AB: | |
6495 | s = "swr"; | |
6496 | goto st; | |
6497 | case M_SC_AB: | |
6498 | s = "sc"; | |
6499 | goto st; | |
6500 | case M_SCD_AB: | |
6501 | s = "scd"; | |
6502 | goto st; | |
d43b4baf TS |
6503 | case M_CACHE_AB: |
6504 | s = "cache"; | |
6505 | goto st; | |
252b5132 | 6506 | case M_SDC1_AB: |
252b5132 RH |
6507 | s = "sdc1"; |
6508 | coproc = 1; | |
bdaaa2e1 | 6509 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6510 | goto st; |
6511 | case M_SDC2_AB: | |
6512 | s = "sdc2"; | |
bdaaa2e1 | 6513 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6514 | coproc = 1; |
6515 | goto st; | |
6516 | case M_SDC3_AB: | |
6517 | s = "sdc3"; | |
bdaaa2e1 | 6518 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6519 | coproc = 1; |
6520 | goto st; | |
6521 | case M_SDL_AB: | |
6522 | s = "sdl"; | |
6523 | goto st; | |
6524 | case M_SDR_AB: | |
6525 | s = "sdr"; | |
6526 | st: | |
8fc2e39e TS |
6527 | tempreg = AT; |
6528 | used_at = 1; | |
252b5132 | 6529 | ld_st: |
b19e8a9b AN |
6530 | if (coproc |
6531 | && NO_ISA_COP (mips_opts.arch) | |
6532 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
6533 | { | |
6534 | as_bad (_("opcode not supported on this processor: %s"), | |
6535 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
6536 | break; | |
6537 | } | |
6538 | ||
bdaaa2e1 | 6539 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6540 | if (mask == M_LWC1_AB |
6541 | || mask == M_SWC1_AB | |
6542 | || mask == M_LDC1_AB | |
6543 | || mask == M_SDC1_AB | |
6544 | || mask == M_L_DAB | |
6545 | || mask == M_S_DAB) | |
6546 | fmt = "T,o(b)"; | |
d43b4baf TS |
6547 | else if (mask == M_CACHE_AB) |
6548 | fmt = "k,o(b)"; | |
252b5132 RH |
6549 | else if (coproc) |
6550 | fmt = "E,o(b)"; | |
6551 | else | |
6552 | fmt = "t,o(b)"; | |
6553 | ||
6554 | if (offset_expr.X_op != O_constant | |
6555 | && offset_expr.X_op != O_symbol) | |
6556 | { | |
6557 | as_bad (_("expression too complex")); | |
6558 | offset_expr.X_op = O_constant; | |
6559 | } | |
6560 | ||
2051e8c4 MR |
6561 | if (HAVE_32BIT_ADDRESSES |
6562 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6563 | { |
6564 | char value [32]; | |
6565 | ||
6566 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6567 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6568 | } |
2051e8c4 | 6569 | |
252b5132 RH |
6570 | /* A constant expression in PIC code can be handled just as it |
6571 | is in non PIC code. */ | |
aed1a261 RS |
6572 | if (offset_expr.X_op == O_constant) |
6573 | { | |
aed1a261 RS |
6574 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6575 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6576 | normalize_address_expr (&expr1); |
aed1a261 RS |
6577 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6578 | if (breg != 0) | |
6579 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6580 | tempreg, tempreg, breg); | |
6581 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6582 | } | |
6583 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6584 | { |
6585 | /* If this is a reference to a GP relative symbol, and there | |
6586 | is no base register, we want | |
cdf6fd85 | 6587 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6588 | Otherwise, if there is no base register, we want |
6589 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6590 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6591 | If we have a constant, we need two instructions anyhow, | |
6592 | so we always use the latter form. | |
6593 | ||
6594 | If we have a base register, and this is a reference to a | |
6595 | GP relative symbol, we want | |
6596 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6597 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6598 | Otherwise we want |
6599 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6600 | addu $tempreg,$tempreg,$breg | |
6601 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6602 | With a constant we always use the latter case. |
76b3015f | 6603 | |
d6bc6245 TS |
6604 | With 64bit address space and no base register and $at usable, |
6605 | we want | |
6606 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6607 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6608 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6609 | dsll32 $tempreg,0 | |
6610 | daddu $tempreg,$at | |
6611 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6612 | If we have a base register, we want | |
6613 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6614 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6615 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6616 | daddu $at,$breg | |
6617 | dsll32 $tempreg,0 | |
6618 | daddu $tempreg,$at | |
6619 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6620 | ||
6621 | Without $at we can't generate the optimal path for superscalar | |
6622 | processors here since this would require two temporary registers. | |
6623 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6624 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6625 | dsll $tempreg,16 | |
6626 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6627 | dsll $tempreg,16 | |
6628 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6629 | If we have a base register, we want | |
6630 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6631 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6632 | dsll $tempreg,16 | |
6633 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6634 | dsll $tempreg,16 | |
6635 | daddu $tempreg,$tempreg,$breg | |
6636 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6637 | |
6caf9ef4 | 6638 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6639 | the same sequence as in 32bit address space. */ |
6640 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6641 | { |
aed1a261 | 6642 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6643 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6644 | { | |
6645 | relax_start (offset_expr.X_add_symbol); | |
6646 | if (breg == 0) | |
6647 | { | |
6648 | macro_build (&offset_expr, s, fmt, treg, | |
6649 | BFD_RELOC_GPREL16, mips_gp_register); | |
6650 | } | |
6651 | else | |
6652 | { | |
6653 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6654 | tempreg, breg, mips_gp_register); | |
6655 | macro_build (&offset_expr, s, fmt, treg, | |
6656 | BFD_RELOC_GPREL16, tempreg); | |
6657 | } | |
6658 | relax_switch (); | |
6659 | } | |
d6bc6245 | 6660 | |
741fe287 | 6661 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 6662 | { |
67c0d1eb RS |
6663 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6664 | BFD_RELOC_MIPS_HIGHEST); | |
6665 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6666 | BFD_RELOC_HI16_S); | |
6667 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6668 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6669 | if (breg != 0) |
67c0d1eb RS |
6670 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6671 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6672 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6673 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6674 | tempreg); | |
d6bc6245 TS |
6675 | used_at = 1; |
6676 | } | |
6677 | else | |
6678 | { | |
67c0d1eb RS |
6679 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6680 | BFD_RELOC_MIPS_HIGHEST); | |
6681 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6682 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6683 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6684 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6685 | tempreg, BFD_RELOC_HI16_S); | |
6686 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6687 | if (breg != 0) |
67c0d1eb | 6688 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6689 | tempreg, tempreg, breg); |
67c0d1eb | 6690 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6691 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6692 | } |
6caf9ef4 TS |
6693 | |
6694 | if (mips_relax.sequence) | |
6695 | relax_end (); | |
8fc2e39e | 6696 | break; |
d6bc6245 | 6697 | } |
256ab948 | 6698 | |
252b5132 RH |
6699 | if (breg == 0) |
6700 | { | |
67c0d1eb | 6701 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6702 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6703 | { |
4d7206a2 | 6704 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6705 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6706 | mips_gp_register); | |
4d7206a2 | 6707 | relax_switch (); |
252b5132 | 6708 | } |
67c0d1eb RS |
6709 | macro_build_lui (&offset_expr, tempreg); |
6710 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6711 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6712 | if (mips_relax.sequence) |
6713 | relax_end (); | |
252b5132 RH |
6714 | } |
6715 | else | |
6716 | { | |
67c0d1eb | 6717 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6718 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6719 | { |
4d7206a2 | 6720 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6721 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6722 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6723 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6724 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6725 | relax_switch (); |
252b5132 | 6726 | } |
67c0d1eb RS |
6727 | macro_build_lui (&offset_expr, tempreg); |
6728 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6729 | tempreg, tempreg, breg); |
67c0d1eb | 6730 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6731 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6732 | if (mips_relax.sequence) |
6733 | relax_end (); | |
252b5132 RH |
6734 | } |
6735 | } | |
0a44bf69 | 6736 | else if (!mips_big_got) |
252b5132 | 6737 | { |
ed6fb7bd | 6738 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6739 | |
252b5132 RH |
6740 | /* If this is a reference to an external symbol, we want |
6741 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6742 | nop | |
6743 | <op> $treg,0($tempreg) | |
6744 | Otherwise we want | |
6745 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6746 | nop | |
6747 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6748 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6749 | |
6750 | For NewABI, we want | |
6751 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6752 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6753 | ||
252b5132 RH |
6754 | If there is a base register, we add it to $tempreg before |
6755 | the <op>. If there is a constant, we stick it in the | |
6756 | <op> instruction. We don't handle constants larger than | |
6757 | 16 bits, because we have no way to load the upper 16 bits | |
6758 | (actually, we could handle them for the subset of cases | |
6759 | in which we are not using $at). */ | |
9c2799c2 | 6760 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
6761 | if (HAVE_NEWABI) |
6762 | { | |
67c0d1eb RS |
6763 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6764 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6765 | if (breg != 0) |
67c0d1eb | 6766 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6767 | tempreg, tempreg, breg); |
67c0d1eb | 6768 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6769 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6770 | break; |
6771 | } | |
252b5132 RH |
6772 | expr1.X_add_number = offset_expr.X_add_number; |
6773 | offset_expr.X_add_number = 0; | |
6774 | if (expr1.X_add_number < -0x8000 | |
6775 | || expr1.X_add_number >= 0x8000) | |
6776 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6777 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6778 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6779 | load_delay_nop (); |
4d7206a2 RS |
6780 | relax_start (offset_expr.X_add_symbol); |
6781 | relax_switch (); | |
67c0d1eb RS |
6782 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6783 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6784 | relax_end (); |
252b5132 | 6785 | if (breg != 0) |
67c0d1eb | 6786 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6787 | tempreg, tempreg, breg); |
67c0d1eb | 6788 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6789 | } |
0a44bf69 | 6790 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6791 | { |
67c0d1eb | 6792 | int gpdelay; |
252b5132 RH |
6793 | |
6794 | /* If this is a reference to an external symbol, we want | |
6795 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6796 | addu $tempreg,$tempreg,$gp | |
6797 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6798 | <op> $treg,0($tempreg) | |
6799 | Otherwise we want | |
6800 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6801 | nop | |
6802 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6803 | <op> $treg,0($tempreg) | |
6804 | If there is a base register, we add it to $tempreg before | |
6805 | the <op>. If there is a constant, we stick it in the | |
6806 | <op> instruction. We don't handle constants larger than | |
6807 | 16 bits, because we have no way to load the upper 16 bits | |
6808 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6809 | in which we are not using $at). */ |
9c2799c2 | 6810 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
6811 | expr1.X_add_number = offset_expr.X_add_number; |
6812 | offset_expr.X_add_number = 0; | |
6813 | if (expr1.X_add_number < -0x8000 | |
6814 | || expr1.X_add_number >= 0x8000) | |
6815 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6816 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6817 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6818 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6819 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6820 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6821 | mips_gp_register); | |
6822 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6823 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6824 | relax_switch (); |
67c0d1eb RS |
6825 | if (gpdelay) |
6826 | macro_build (NULL, "nop", ""); | |
6827 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6828 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6829 | load_delay_nop (); |
67c0d1eb RS |
6830 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6831 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6832 | relax_end (); |
6833 | ||
252b5132 | 6834 | if (breg != 0) |
67c0d1eb | 6835 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6836 | tempreg, tempreg, breg); |
67c0d1eb | 6837 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6838 | } |
0a44bf69 | 6839 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6840 | { |
f5040a92 AO |
6841 | /* If this is a reference to an external symbol, we want |
6842 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6843 | add $tempreg,$tempreg,$gp | |
6844 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6845 | <op> $treg,<ofst>($tempreg) | |
6846 | Otherwise, for local symbols, we want: | |
6847 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6848 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 6849 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 6850 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6851 | offset_expr.X_add_number = 0; |
6852 | if (expr1.X_add_number < -0x8000 | |
6853 | || expr1.X_add_number >= 0x8000) | |
6854 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6855 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6856 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6857 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6858 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6859 | mips_gp_register); | |
6860 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6861 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6862 | if (breg != 0) |
67c0d1eb | 6863 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6864 | tempreg, tempreg, breg); |
67c0d1eb | 6865 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6866 | |
4d7206a2 | 6867 | relax_switch (); |
f5040a92 | 6868 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6869 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6870 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6871 | if (breg != 0) |
67c0d1eb | 6872 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6873 | tempreg, tempreg, breg); |
67c0d1eb | 6874 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6875 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6876 | relax_end (); |
f5040a92 | 6877 | } |
252b5132 RH |
6878 | else |
6879 | abort (); | |
6880 | ||
252b5132 RH |
6881 | break; |
6882 | ||
6883 | case M_LI: | |
6884 | case M_LI_S: | |
67c0d1eb | 6885 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6886 | break; |
252b5132 RH |
6887 | |
6888 | case M_DLI: | |
67c0d1eb | 6889 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6890 | break; |
252b5132 RH |
6891 | |
6892 | case M_LI_SS: | |
6893 | if (imm_expr.X_op == O_constant) | |
6894 | { | |
8fc2e39e | 6895 | used_at = 1; |
67c0d1eb RS |
6896 | load_register (AT, &imm_expr, 0); |
6897 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6898 | break; |
6899 | } | |
6900 | else | |
6901 | { | |
9c2799c2 | 6902 | gas_assert (offset_expr.X_op == O_symbol |
252b5132 RH |
6903 | && strcmp (segment_name (S_GET_SEGMENT |
6904 | (offset_expr.X_add_symbol)), | |
6905 | ".lit4") == 0 | |
6906 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6907 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6908 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6909 | break; |
252b5132 RH |
6910 | } |
6911 | ||
6912 | case M_LI_D: | |
ca4e0257 RS |
6913 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6914 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6915 | order 32 bits of the value and the low order 32 bits are either | |
6916 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6917 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6918 | { | |
ca4e0257 | 6919 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6920 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6921 | else |
6922 | { | |
6923 | int hreg, lreg; | |
6924 | ||
6925 | if (target_big_endian) | |
6926 | { | |
6927 | hreg = treg; | |
6928 | lreg = treg + 1; | |
6929 | } | |
6930 | else | |
6931 | { | |
6932 | hreg = treg + 1; | |
6933 | lreg = treg; | |
6934 | } | |
6935 | ||
6936 | if (hreg <= 31) | |
67c0d1eb | 6937 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6938 | if (lreg <= 31) |
6939 | { | |
6940 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6941 | move_register (lreg, 0); |
252b5132 RH |
6942 | else |
6943 | { | |
9c2799c2 | 6944 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 6945 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6946 | } |
6947 | } | |
6948 | } | |
8fc2e39e | 6949 | break; |
252b5132 RH |
6950 | } |
6951 | ||
6952 | /* We know that sym is in the .rdata section. First we get the | |
6953 | upper 16 bits of the address. */ | |
6954 | if (mips_pic == NO_PIC) | |
6955 | { | |
67c0d1eb | 6956 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6957 | used_at = 1; |
252b5132 | 6958 | } |
0a44bf69 | 6959 | else |
252b5132 | 6960 | { |
67c0d1eb RS |
6961 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6962 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6963 | used_at = 1; |
252b5132 | 6964 | } |
bdaaa2e1 | 6965 | |
252b5132 | 6966 | /* Now we load the register(s). */ |
ca4e0257 | 6967 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6968 | { |
6969 | used_at = 1; | |
6970 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6971 | } | |
252b5132 RH |
6972 | else |
6973 | { | |
8fc2e39e | 6974 | used_at = 1; |
67c0d1eb | 6975 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6976 | if (treg != RA) |
252b5132 RH |
6977 | { |
6978 | /* FIXME: How in the world do we deal with the possible | |
6979 | overflow here? */ | |
6980 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6981 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6982 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6983 | } |
6984 | } | |
252b5132 RH |
6985 | break; |
6986 | ||
6987 | case M_LI_DD: | |
ca4e0257 RS |
6988 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6989 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6990 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6991 | the value and the low order 32 bits are either zero or in | |
6992 | OFFSET_EXPR. */ | |
252b5132 RH |
6993 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6994 | { | |
8fc2e39e | 6995 | used_at = 1; |
67c0d1eb | 6996 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6997 | if (HAVE_64BIT_FPRS) |
6998 | { | |
9c2799c2 | 6999 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 7000 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 7001 | } |
252b5132 RH |
7002 | else |
7003 | { | |
67c0d1eb | 7004 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 7005 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 7006 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
7007 | else |
7008 | { | |
9c2799c2 | 7009 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
7010 | load_register (AT, &offset_expr, 0); |
7011 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
7012 | } |
7013 | } | |
7014 | break; | |
7015 | } | |
7016 | ||
9c2799c2 | 7017 | gas_assert (offset_expr.X_op == O_symbol |
252b5132 RH |
7018 | && offset_expr.X_add_number == 0); |
7019 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
7020 | if (strcmp (s, ".lit8") == 0) | |
7021 | { | |
e7af610e | 7022 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7023 | { |
67c0d1eb | 7024 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 7025 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 7026 | break; |
252b5132 | 7027 | } |
c9914766 | 7028 | breg = mips_gp_register; |
252b5132 RH |
7029 | r = BFD_RELOC_MIPS_LITERAL; |
7030 | goto dob; | |
7031 | } | |
7032 | else | |
7033 | { | |
9c2799c2 | 7034 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 7035 | used_at = 1; |
0a44bf69 | 7036 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
7037 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
7038 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
7039 | else |
7040 | { | |
7041 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 7042 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7043 | } |
bdaaa2e1 | 7044 | |
e7af610e | 7045 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 7046 | { |
67c0d1eb RS |
7047 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
7048 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
7049 | break; |
7050 | } | |
7051 | breg = AT; | |
7052 | r = BFD_RELOC_LO16; | |
7053 | goto dob; | |
7054 | } | |
7055 | ||
7056 | case M_L_DOB: | |
252b5132 RH |
7057 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7058 | to adjust when loading from memory. */ | |
7059 | r = BFD_RELOC_LO16; | |
7060 | dob: | |
9c2799c2 | 7061 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 7062 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7063 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
7064 | /* FIXME: A possible overflow which I don't know how to deal |
7065 | with. */ | |
7066 | offset_expr.X_add_number += 4; | |
67c0d1eb | 7067 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 7068 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
7069 | break; |
7070 | ||
7071 | case M_L_DAB: | |
7072 | /* | |
7073 | * The MIPS assembler seems to check for X_add_number not | |
7074 | * being double aligned and generating: | |
7075 | * lui at,%hi(foo+1) | |
7076 | * addu at,at,v1 | |
7077 | * addiu at,at,%lo(foo+1) | |
7078 | * lwc1 f2,0(at) | |
7079 | * lwc1 f3,4(at) | |
7080 | * But, the resulting address is the same after relocation so why | |
7081 | * generate the extra instruction? | |
7082 | */ | |
bdaaa2e1 | 7083 | /* Itbl support may require additional care here. */ |
252b5132 | 7084 | coproc = 1; |
e7af610e | 7085 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7086 | { |
7087 | s = "ldc1"; | |
7088 | goto ld; | |
7089 | } | |
7090 | ||
7091 | s = "lwc1"; | |
7092 | fmt = "T,o(b)"; | |
7093 | goto ldd_std; | |
7094 | ||
7095 | case M_S_DAB: | |
e7af610e | 7096 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
7097 | { |
7098 | s = "sdc1"; | |
7099 | goto st; | |
7100 | } | |
7101 | ||
7102 | s = "swc1"; | |
7103 | fmt = "T,o(b)"; | |
bdaaa2e1 | 7104 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7105 | coproc = 1; |
7106 | goto ldd_std; | |
7107 | ||
7108 | case M_LD_AB: | |
ca4e0257 | 7109 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7110 | { |
7111 | s = "ld"; | |
7112 | goto ld; | |
7113 | } | |
7114 | ||
7115 | s = "lw"; | |
7116 | fmt = "t,o(b)"; | |
7117 | goto ldd_std; | |
7118 | ||
7119 | case M_SD_AB: | |
ca4e0257 | 7120 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
7121 | { |
7122 | s = "sd"; | |
7123 | goto st; | |
7124 | } | |
7125 | ||
7126 | s = "sw"; | |
7127 | fmt = "t,o(b)"; | |
7128 | ||
7129 | ldd_std: | |
7130 | if (offset_expr.X_op != O_symbol | |
7131 | && offset_expr.X_op != O_constant) | |
7132 | { | |
7133 | as_bad (_("expression too complex")); | |
7134 | offset_expr.X_op = O_constant; | |
7135 | } | |
7136 | ||
2051e8c4 MR |
7137 | if (HAVE_32BIT_ADDRESSES |
7138 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
7139 | { |
7140 | char value [32]; | |
7141 | ||
7142 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 7143 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 7144 | } |
2051e8c4 | 7145 | |
252b5132 RH |
7146 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7147 | to adjust when loading from memory. We set coproc if we must | |
7148 | load $fn+1 first. */ | |
bdaaa2e1 | 7149 | /* Itbl support may require additional care here. */ |
252b5132 RH |
7150 | if (! target_big_endian) |
7151 | coproc = 0; | |
7152 | ||
7153 | if (mips_pic == NO_PIC | |
7154 | || offset_expr.X_op == O_constant) | |
7155 | { | |
7156 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
7157 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
7158 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7159 | If we have a base register, we use this |
7160 | addu $at,$breg,$gp | |
cdf6fd85 TS |
7161 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
7162 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
7163 | If this is not a GP relative symbol, we want |
7164 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7165 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7166 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7167 | If there is a base register, we add it to $at after the | |
7168 | lui instruction. If there is a constant, we always use | |
7169 | the last case. */ | |
39a59cf8 MR |
7170 | if (offset_expr.X_op == O_symbol |
7171 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7172 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 7173 | { |
4d7206a2 | 7174 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
7175 | if (breg == 0) |
7176 | { | |
c9914766 | 7177 | tempreg = mips_gp_register; |
252b5132 RH |
7178 | } |
7179 | else | |
7180 | { | |
67c0d1eb | 7181 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7182 | AT, breg, mips_gp_register); |
252b5132 | 7183 | tempreg = AT; |
252b5132 RH |
7184 | used_at = 1; |
7185 | } | |
7186 | ||
beae10d5 | 7187 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7188 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7189 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7190 | offset_expr.X_add_number += 4; |
7191 | ||
7192 | /* Set mips_optimize to 2 to avoid inserting an | |
7193 | undesired nop. */ | |
7194 | hold_mips_optimize = mips_optimize; | |
7195 | mips_optimize = 2; | |
beae10d5 | 7196 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7197 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7198 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
7199 | mips_optimize = hold_mips_optimize; |
7200 | ||
4d7206a2 | 7201 | relax_switch (); |
252b5132 RH |
7202 | |
7203 | /* We just generated two relocs. When tc_gen_reloc | |
7204 | handles this case, it will skip the first reloc and | |
7205 | handle the second. The second reloc already has an | |
7206 | extra addend of 4, which we added above. We must | |
7207 | subtract it out, and then subtract another 4 to make | |
7208 | the first reloc come out right. The second reloc | |
7209 | will come out right because we are going to add 4 to | |
7210 | offset_expr when we build its instruction below. | |
7211 | ||
7212 | If we have a symbol, then we don't want to include | |
7213 | the offset, because it will wind up being included | |
7214 | when we generate the reloc. */ | |
7215 | ||
7216 | if (offset_expr.X_op == O_constant) | |
7217 | offset_expr.X_add_number -= 8; | |
7218 | else | |
7219 | { | |
7220 | offset_expr.X_add_number = -4; | |
7221 | offset_expr.X_op = O_constant; | |
7222 | } | |
7223 | } | |
8fc2e39e | 7224 | used_at = 1; |
67c0d1eb | 7225 | macro_build_lui (&offset_expr, AT); |
252b5132 | 7226 | if (breg != 0) |
67c0d1eb | 7227 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7228 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7229 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7230 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7231 | /* FIXME: How do we handle overflow here? */ |
7232 | offset_expr.X_add_number += 4; | |
beae10d5 | 7233 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7234 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7235 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
7236 | if (mips_relax.sequence) |
7237 | relax_end (); | |
bdaaa2e1 | 7238 | } |
0a44bf69 | 7239 | else if (!mips_big_got) |
252b5132 | 7240 | { |
252b5132 RH |
7241 | /* If this is a reference to an external symbol, we want |
7242 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7243 | nop | |
7244 | <op> $treg,0($at) | |
7245 | <op> $treg+1,4($at) | |
7246 | Otherwise we want | |
7247 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7248 | nop | |
7249 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7250 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7251 | If there is a base register we add it to $at before the | |
7252 | lwc1 instructions. If there is a constant we include it | |
7253 | in the lwc1 instructions. */ | |
7254 | used_at = 1; | |
7255 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
7256 | if (expr1.X_add_number < -0x8000 |
7257 | || expr1.X_add_number >= 0x8000 - 4) | |
7258 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7259 | load_got_offset (AT, &offset_expr); |
269137b2 | 7260 | load_delay_nop (); |
252b5132 | 7261 | if (breg != 0) |
67c0d1eb | 7262 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
7263 | |
7264 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7265 | nop. */ | |
7266 | hold_mips_optimize = mips_optimize; | |
7267 | mips_optimize = 2; | |
4d7206a2 | 7268 | |
beae10d5 | 7269 | /* Itbl support may require additional care here. */ |
4d7206a2 | 7270 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7271 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
7272 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7273 | expr1.X_add_number += 4; |
67c0d1eb RS |
7274 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
7275 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7276 | relax_switch (); |
67c0d1eb RS |
7277 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7278 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7279 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7280 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7281 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7282 | relax_end (); |
252b5132 | 7283 | |
4d7206a2 | 7284 | mips_optimize = hold_mips_optimize; |
252b5132 | 7285 | } |
0a44bf69 | 7286 | else if (mips_big_got) |
252b5132 | 7287 | { |
67c0d1eb | 7288 | int gpdelay; |
252b5132 RH |
7289 | |
7290 | /* If this is a reference to an external symbol, we want | |
7291 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7292 | addu $at,$at,$gp | |
7293 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
7294 | nop | |
7295 | <op> $treg,0($at) | |
7296 | <op> $treg+1,4($at) | |
7297 | Otherwise we want | |
7298 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7299 | nop | |
7300 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7301 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7302 | If there is a base register we add it to $at before the | |
7303 | lwc1 instructions. If there is a constant we include it | |
7304 | in the lwc1 instructions. */ | |
7305 | used_at = 1; | |
7306 | expr1.X_add_number = offset_expr.X_add_number; | |
7307 | offset_expr.X_add_number = 0; | |
7308 | if (expr1.X_add_number < -0x8000 | |
7309 | || expr1.X_add_number >= 0x8000 - 4) | |
7310 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7311 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7312 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7313 | macro_build (&offset_expr, "lui", "t,u", |
7314 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7315 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7316 | AT, AT, mips_gp_register); |
67c0d1eb | 7317 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7318 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7319 | load_delay_nop (); |
252b5132 | 7320 | if (breg != 0) |
67c0d1eb | 7321 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7322 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7323 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7324 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7325 | expr1.X_add_number += 4; |
7326 | ||
7327 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7328 | nop. */ | |
7329 | hold_mips_optimize = mips_optimize; | |
7330 | mips_optimize = 2; | |
beae10d5 | 7331 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7332 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7333 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7334 | mips_optimize = hold_mips_optimize; |
7335 | expr1.X_add_number -= 4; | |
7336 | ||
4d7206a2 RS |
7337 | relax_switch (); |
7338 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7339 | if (gpdelay) |
7340 | macro_build (NULL, "nop", ""); | |
7341 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7342 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7343 | load_delay_nop (); |
252b5132 | 7344 | if (breg != 0) |
67c0d1eb | 7345 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7346 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7347 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7348 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7349 | offset_expr.X_add_number += 4; |
252b5132 RH |
7350 | |
7351 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7352 | nop. */ | |
7353 | hold_mips_optimize = mips_optimize; | |
7354 | mips_optimize = 2; | |
beae10d5 | 7355 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7356 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7357 | BFD_RELOC_LO16, AT); | |
252b5132 | 7358 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7359 | relax_end (); |
252b5132 | 7360 | } |
252b5132 RH |
7361 | else |
7362 | abort (); | |
7363 | ||
252b5132 RH |
7364 | break; |
7365 | ||
7366 | case M_LD_OB: | |
7367 | s = "lw"; | |
7368 | goto sd_ob; | |
7369 | case M_SD_OB: | |
7370 | s = "sw"; | |
7371 | sd_ob: | |
9c2799c2 | 7372 | gas_assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7373 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7374 | offset_expr.X_add_number += 4; |
67c0d1eb | 7375 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7376 | break; |
252b5132 RH |
7377 | |
7378 | /* New code added to support COPZ instructions. | |
7379 | This code builds table entries out of the macros in mip_opcodes. | |
7380 | R4000 uses interlocks to handle coproc delays. | |
7381 | Other chips (like the R3000) require nops to be inserted for delays. | |
7382 | ||
f72c8c98 | 7383 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7384 | In order to fill delay slots for non-interlocked chips, |
7385 | we must have a way to specify delays based on the coprocessor. | |
7386 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7387 | What are the side-effects of the cop instruction? | |
7388 | What cache support might we have and what are its effects? | |
7389 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7390 | What registers are read/set/modified? |
252b5132 RH |
7391 | |
7392 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7393 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7394 | |
7395 | case M_COP0: | |
7396 | s = "c0"; | |
7397 | goto copz; | |
7398 | case M_COP1: | |
7399 | s = "c1"; | |
7400 | goto copz; | |
7401 | case M_COP2: | |
7402 | s = "c2"; | |
7403 | goto copz; | |
7404 | case M_COP3: | |
7405 | s = "c3"; | |
7406 | copz: | |
b19e8a9b AN |
7407 | if (NO_ISA_COP (mips_opts.arch) |
7408 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
7409 | { | |
7410 | as_bad (_("opcode not supported on this processor: %s"), | |
7411 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
7412 | break; | |
7413 | } | |
7414 | ||
252b5132 RH |
7415 | /* For now we just do C (same as Cz). The parameter will be |
7416 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7417 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7418 | break; |
252b5132 | 7419 | |
ea1fb5dc | 7420 | case M_MOVE: |
67c0d1eb | 7421 | move_register (dreg, sreg); |
8fc2e39e | 7422 | break; |
ea1fb5dc | 7423 | |
252b5132 RH |
7424 | #ifdef LOSING_COMPILER |
7425 | default: | |
7426 | /* Try and see if this is a new itbl instruction. | |
7427 | This code builds table entries out of the macros in mip_opcodes. | |
7428 | FIXME: For now we just assemble the expression and pass it's | |
7429 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7430 | We may want to have the assembler assemble this value, |
252b5132 RH |
7431 | so that we gain the assembler's knowledge of delay slots, |
7432 | symbols, etc. | |
7433 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7434 | if (itbl_have_entries |
252b5132 | 7435 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7436 | { |
252b5132 RH |
7437 | s = ip->insn_mo->name; |
7438 | s2 = "cop3"; | |
7439 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7440 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7441 | break; |
beae10d5 | 7442 | } |
252b5132 | 7443 | macro2 (ip); |
8fc2e39e | 7444 | break; |
252b5132 | 7445 | } |
741fe287 | 7446 | if (!mips_opts.at && used_at) |
8fc2e39e | 7447 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 | 7448 | } |
bdaaa2e1 | 7449 | |
252b5132 | 7450 | static void |
17a2f251 | 7451 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7452 | { |
741fe287 MR |
7453 | unsigned int treg, sreg, dreg, breg; |
7454 | unsigned int tempreg; | |
252b5132 | 7455 | int mask; |
252b5132 RH |
7456 | int used_at; |
7457 | expressionS expr1; | |
7458 | const char *s; | |
7459 | const char *s2; | |
7460 | const char *fmt; | |
7461 | int likely = 0; | |
7462 | int dbl = 0; | |
7463 | int coproc = 0; | |
7464 | int lr = 0; | |
7465 | int imm = 0; | |
7466 | int off; | |
7467 | offsetT maxnum; | |
7468 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7469 | |
252b5132 RH |
7470 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7471 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7472 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7473 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7474 | |
252b5132 RH |
7475 | expr1.X_op = O_constant; |
7476 | expr1.X_op_symbol = NULL; | |
7477 | expr1.X_add_symbol = NULL; | |
7478 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7479 | |
252b5132 RH |
7480 | switch (mask) |
7481 | { | |
7482 | #endif /* LOSING_COMPILER */ | |
7483 | ||
7484 | case M_DMUL: | |
7485 | dbl = 1; | |
7486 | case M_MUL: | |
67c0d1eb RS |
7487 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7488 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7489 | break; |
252b5132 RH |
7490 | |
7491 | case M_DMUL_I: | |
7492 | dbl = 1; | |
7493 | case M_MUL_I: | |
7494 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7495 | not trying to be that fancy. GCC should do this for us | |
7496 | anyway. */ | |
8fc2e39e | 7497 | used_at = 1; |
67c0d1eb RS |
7498 | load_register (AT, &imm_expr, dbl); |
7499 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7500 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7501 | break; |
7502 | ||
7503 | case M_DMULO_I: | |
7504 | dbl = 1; | |
7505 | case M_MULO_I: | |
7506 | imm = 1; | |
7507 | goto do_mulo; | |
7508 | ||
7509 | case M_DMULO: | |
7510 | dbl = 1; | |
7511 | case M_MULO: | |
7512 | do_mulo: | |
7d10b47d | 7513 | start_noreorder (); |
8fc2e39e | 7514 | used_at = 1; |
252b5132 | 7515 | if (imm) |
67c0d1eb RS |
7516 | load_register (AT, &imm_expr, dbl); |
7517 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7518 | macro_build (NULL, "mflo", "d", dreg); | |
7519 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7520 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7521 | if (mips_trap) |
67c0d1eb | 7522 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7523 | else |
7524 | { | |
7525 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7526 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7527 | macro_build (NULL, "nop", "", 0); | |
7528 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7529 | } |
7d10b47d | 7530 | end_noreorder (); |
67c0d1eb | 7531 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7532 | break; |
7533 | ||
7534 | case M_DMULOU_I: | |
7535 | dbl = 1; | |
7536 | case M_MULOU_I: | |
7537 | imm = 1; | |
7538 | goto do_mulou; | |
7539 | ||
7540 | case M_DMULOU: | |
7541 | dbl = 1; | |
7542 | case M_MULOU: | |
7543 | do_mulou: | |
7d10b47d | 7544 | start_noreorder (); |
8fc2e39e | 7545 | used_at = 1; |
252b5132 | 7546 | if (imm) |
67c0d1eb RS |
7547 | load_register (AT, &imm_expr, dbl); |
7548 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7549 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7550 | macro_build (NULL, "mfhi", "d", AT); |
7551 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7552 | if (mips_trap) |
67c0d1eb | 7553 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7554 | else |
7555 | { | |
7556 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7557 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7558 | macro_build (NULL, "nop", "", 0); | |
7559 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7560 | } |
7d10b47d | 7561 | end_noreorder (); |
252b5132 RH |
7562 | break; |
7563 | ||
771c7ce4 | 7564 | case M_DROL: |
fef14a42 | 7565 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7566 | { |
7567 | if (dreg == sreg) | |
7568 | { | |
7569 | tempreg = AT; | |
7570 | used_at = 1; | |
7571 | } | |
7572 | else | |
7573 | { | |
7574 | tempreg = dreg; | |
82dd0097 | 7575 | } |
67c0d1eb RS |
7576 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7577 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7578 | break; |
82dd0097 | 7579 | } |
8fc2e39e | 7580 | used_at = 1; |
67c0d1eb RS |
7581 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7582 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7583 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7584 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7585 | break; |
7586 | ||
252b5132 | 7587 | case M_ROL: |
fef14a42 | 7588 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7589 | { |
7590 | if (dreg == sreg) | |
7591 | { | |
7592 | tempreg = AT; | |
7593 | used_at = 1; | |
7594 | } | |
7595 | else | |
7596 | { | |
7597 | tempreg = dreg; | |
82dd0097 | 7598 | } |
67c0d1eb RS |
7599 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7600 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7601 | break; |
82dd0097 | 7602 | } |
8fc2e39e | 7603 | used_at = 1; |
67c0d1eb RS |
7604 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7605 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7606 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7607 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7608 | break; |
7609 | ||
771c7ce4 TS |
7610 | case M_DROL_I: |
7611 | { | |
7612 | unsigned int rot; | |
91d6fa6a NC |
7613 | char *l; |
7614 | char *rr; | |
771c7ce4 TS |
7615 | |
7616 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7617 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7618 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7619 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7620 | { |
7621 | rot = (64 - rot) & 0x3f; | |
7622 | if (rot >= 32) | |
67c0d1eb | 7623 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7624 | else |
67c0d1eb | 7625 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7626 | break; |
60b63b72 | 7627 | } |
483fc7cd | 7628 | if (rot == 0) |
483fc7cd | 7629 | { |
67c0d1eb | 7630 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7631 | break; |
483fc7cd | 7632 | } |
82dd0097 | 7633 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 7634 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 7635 | rot &= 0x1f; |
8fc2e39e | 7636 | used_at = 1; |
67c0d1eb | 7637 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
91d6fa6a | 7638 | macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
67c0d1eb | 7639 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
7640 | } |
7641 | break; | |
7642 | ||
252b5132 | 7643 | case M_ROL_I: |
771c7ce4 TS |
7644 | { |
7645 | unsigned int rot; | |
7646 | ||
7647 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7648 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7649 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7650 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7651 | { |
67c0d1eb | 7652 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7653 | break; |
60b63b72 | 7654 | } |
483fc7cd | 7655 | if (rot == 0) |
483fc7cd | 7656 | { |
67c0d1eb | 7657 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7658 | break; |
483fc7cd | 7659 | } |
8fc2e39e | 7660 | used_at = 1; |
67c0d1eb RS |
7661 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7662 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7663 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7664 | } |
7665 | break; | |
7666 | ||
7667 | case M_DROR: | |
fef14a42 | 7668 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7669 | { |
67c0d1eb | 7670 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7671 | break; |
82dd0097 | 7672 | } |
8fc2e39e | 7673 | used_at = 1; |
67c0d1eb RS |
7674 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7675 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7676 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7677 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7678 | break; |
7679 | ||
7680 | case M_ROR: | |
fef14a42 | 7681 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7682 | { |
67c0d1eb | 7683 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7684 | break; |
82dd0097 | 7685 | } |
8fc2e39e | 7686 | used_at = 1; |
67c0d1eb RS |
7687 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7688 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7689 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7690 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7691 | break; |
7692 | ||
771c7ce4 TS |
7693 | case M_DROR_I: |
7694 | { | |
7695 | unsigned int rot; | |
91d6fa6a NC |
7696 | char *l; |
7697 | char *rr; | |
771c7ce4 TS |
7698 | |
7699 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7700 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7701 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7702 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7703 | { |
7704 | if (rot >= 32) | |
67c0d1eb | 7705 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7706 | else |
67c0d1eb | 7707 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7708 | break; |
82dd0097 | 7709 | } |
483fc7cd | 7710 | if (rot == 0) |
483fc7cd | 7711 | { |
67c0d1eb | 7712 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7713 | break; |
483fc7cd | 7714 | } |
91d6fa6a | 7715 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
7716 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
7717 | rot &= 0x1f; | |
8fc2e39e | 7718 | used_at = 1; |
91d6fa6a | 7719 | macro_build (NULL, rr, "d,w,<", AT, sreg, rot); |
67c0d1eb RS |
7720 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); |
7721 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7722 | } |
7723 | break; | |
7724 | ||
252b5132 | 7725 | case M_ROR_I: |
771c7ce4 TS |
7726 | { |
7727 | unsigned int rot; | |
7728 | ||
7729 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7730 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7731 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7732 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7733 | { |
67c0d1eb | 7734 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7735 | break; |
82dd0097 | 7736 | } |
483fc7cd | 7737 | if (rot == 0) |
483fc7cd | 7738 | { |
67c0d1eb | 7739 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7740 | break; |
483fc7cd | 7741 | } |
8fc2e39e | 7742 | used_at = 1; |
67c0d1eb RS |
7743 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7744 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7745 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7746 | } |
252b5132 RH |
7747 | break; |
7748 | ||
7749 | case M_S_DOB: | |
9c2799c2 | 7750 | gas_assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7751 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7752 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7753 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7754 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7755 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7756 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7757 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7758 | break; |
252b5132 RH |
7759 | |
7760 | case M_SEQ: | |
7761 | if (sreg == 0) | |
67c0d1eb | 7762 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7763 | else if (treg == 0) |
67c0d1eb | 7764 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7765 | else |
7766 | { | |
67c0d1eb RS |
7767 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7768 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7769 | } |
8fc2e39e | 7770 | break; |
252b5132 RH |
7771 | |
7772 | case M_SEQ_I: | |
7773 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7774 | { | |
67c0d1eb | 7775 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7776 | break; |
252b5132 RH |
7777 | } |
7778 | if (sreg == 0) | |
7779 | { | |
7780 | as_warn (_("Instruction %s: result is always false"), | |
7781 | ip->insn_mo->name); | |
67c0d1eb | 7782 | move_register (dreg, 0); |
8fc2e39e | 7783 | break; |
252b5132 | 7784 | } |
dd3cbb7e NC |
7785 | if (CPU_HAS_SEQ (mips_opts.arch) |
7786 | && -512 <= imm_expr.X_add_number | |
7787 | && imm_expr.X_add_number < 512) | |
7788 | { | |
7789 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7790 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7791 | break; |
7792 | } | |
252b5132 RH |
7793 | if (imm_expr.X_op == O_constant |
7794 | && imm_expr.X_add_number >= 0 | |
7795 | && imm_expr.X_add_number < 0x10000) | |
7796 | { | |
67c0d1eb | 7797 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7798 | } |
7799 | else if (imm_expr.X_op == O_constant | |
7800 | && imm_expr.X_add_number > -0x8000 | |
7801 | && imm_expr.X_add_number < 0) | |
7802 | { | |
7803 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7804 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7805 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7806 | } |
dd3cbb7e NC |
7807 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7808 | { | |
7809 | used_at = 1; | |
7810 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7811 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
7812 | break; | |
7813 | } | |
252b5132 RH |
7814 | else |
7815 | { | |
67c0d1eb RS |
7816 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7817 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7818 | used_at = 1; |
7819 | } | |
67c0d1eb | 7820 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7821 | break; |
252b5132 RH |
7822 | |
7823 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7824 | s = "slt"; | |
7825 | goto sge; | |
7826 | case M_SGEU: | |
7827 | s = "sltu"; | |
7828 | sge: | |
67c0d1eb RS |
7829 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7830 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7831 | break; |
252b5132 RH |
7832 | |
7833 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7834 | case M_SGEU_I: | |
7835 | if (imm_expr.X_op == O_constant | |
7836 | && imm_expr.X_add_number >= -0x8000 | |
7837 | && imm_expr.X_add_number < 0x8000) | |
7838 | { | |
67c0d1eb RS |
7839 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7840 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7841 | } |
7842 | else | |
7843 | { | |
67c0d1eb RS |
7844 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7845 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7846 | dreg, sreg, AT); | |
252b5132 RH |
7847 | used_at = 1; |
7848 | } | |
67c0d1eb | 7849 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7850 | break; |
252b5132 RH |
7851 | |
7852 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7853 | s = "slt"; | |
7854 | goto sgt; | |
7855 | case M_SGTU: | |
7856 | s = "sltu"; | |
7857 | sgt: | |
67c0d1eb | 7858 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7859 | break; |
252b5132 RH |
7860 | |
7861 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7862 | s = "slt"; | |
7863 | goto sgti; | |
7864 | case M_SGTU_I: | |
7865 | s = "sltu"; | |
7866 | sgti: | |
8fc2e39e | 7867 | used_at = 1; |
67c0d1eb RS |
7868 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7869 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7870 | break; |
7871 | ||
2396cfb9 | 7872 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7873 | s = "slt"; |
7874 | goto sle; | |
7875 | case M_SLEU: | |
7876 | s = "sltu"; | |
7877 | sle: | |
67c0d1eb RS |
7878 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7879 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7880 | break; |
252b5132 | 7881 | |
2396cfb9 | 7882 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7883 | s = "slt"; |
7884 | goto slei; | |
7885 | case M_SLEU_I: | |
7886 | s = "sltu"; | |
7887 | slei: | |
8fc2e39e | 7888 | used_at = 1; |
67c0d1eb RS |
7889 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7890 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7891 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7892 | break; |
7893 | ||
7894 | case M_SLT_I: | |
7895 | if (imm_expr.X_op == O_constant | |
7896 | && imm_expr.X_add_number >= -0x8000 | |
7897 | && imm_expr.X_add_number < 0x8000) | |
7898 | { | |
67c0d1eb | 7899 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7900 | break; |
252b5132 | 7901 | } |
8fc2e39e | 7902 | used_at = 1; |
67c0d1eb RS |
7903 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7904 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7905 | break; |
7906 | ||
7907 | case M_SLTU_I: | |
7908 | if (imm_expr.X_op == O_constant | |
7909 | && imm_expr.X_add_number >= -0x8000 | |
7910 | && imm_expr.X_add_number < 0x8000) | |
7911 | { | |
67c0d1eb | 7912 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7913 | BFD_RELOC_LO16); |
8fc2e39e | 7914 | break; |
252b5132 | 7915 | } |
8fc2e39e | 7916 | used_at = 1; |
67c0d1eb RS |
7917 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7918 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7919 | break; |
7920 | ||
7921 | case M_SNE: | |
7922 | if (sreg == 0) | |
67c0d1eb | 7923 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7924 | else if (treg == 0) |
67c0d1eb | 7925 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7926 | else |
7927 | { | |
67c0d1eb RS |
7928 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7929 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7930 | } |
8fc2e39e | 7931 | break; |
252b5132 RH |
7932 | |
7933 | case M_SNE_I: | |
7934 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7935 | { | |
67c0d1eb | 7936 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7937 | break; |
252b5132 RH |
7938 | } |
7939 | if (sreg == 0) | |
7940 | { | |
7941 | as_warn (_("Instruction %s: result is always true"), | |
7942 | ip->insn_mo->name); | |
67c0d1eb RS |
7943 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7944 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7945 | break; |
252b5132 | 7946 | } |
dd3cbb7e NC |
7947 | if (CPU_HAS_SEQ (mips_opts.arch) |
7948 | && -512 <= imm_expr.X_add_number | |
7949 | && imm_expr.X_add_number < 512) | |
7950 | { | |
7951 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 7952 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
7953 | break; |
7954 | } | |
252b5132 RH |
7955 | if (imm_expr.X_op == O_constant |
7956 | && imm_expr.X_add_number >= 0 | |
7957 | && imm_expr.X_add_number < 0x10000) | |
7958 | { | |
67c0d1eb | 7959 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7960 | } |
7961 | else if (imm_expr.X_op == O_constant | |
7962 | && imm_expr.X_add_number > -0x8000 | |
7963 | && imm_expr.X_add_number < 0) | |
7964 | { | |
7965 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7966 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7967 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 7968 | } |
dd3cbb7e NC |
7969 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
7970 | { | |
7971 | used_at = 1; | |
7972 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
7973 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
7974 | break; | |
7975 | } | |
252b5132 RH |
7976 | else |
7977 | { | |
67c0d1eb RS |
7978 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7979 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7980 | used_at = 1; |
7981 | } | |
67c0d1eb | 7982 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7983 | break; |
252b5132 RH |
7984 | |
7985 | case M_DSUB_I: | |
7986 | dbl = 1; | |
7987 | case M_SUB_I: | |
7988 | if (imm_expr.X_op == O_constant | |
7989 | && imm_expr.X_add_number > -0x8000 | |
7990 | && imm_expr.X_add_number <= 0x8000) | |
7991 | { | |
7992 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7993 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7994 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7995 | break; |
252b5132 | 7996 | } |
8fc2e39e | 7997 | used_at = 1; |
67c0d1eb RS |
7998 | load_register (AT, &imm_expr, dbl); |
7999 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8000 | break; |
8001 | ||
8002 | case M_DSUBU_I: | |
8003 | dbl = 1; | |
8004 | case M_SUBU_I: | |
8005 | if (imm_expr.X_op == O_constant | |
8006 | && imm_expr.X_add_number > -0x8000 | |
8007 | && imm_expr.X_add_number <= 0x8000) | |
8008 | { | |
8009 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
8010 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
8011 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 8012 | break; |
252b5132 | 8013 | } |
8fc2e39e | 8014 | used_at = 1; |
67c0d1eb RS |
8015 | load_register (AT, &imm_expr, dbl); |
8016 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
8017 | break; |
8018 | ||
8019 | case M_TEQ_I: | |
8020 | s = "teq"; | |
8021 | goto trap; | |
8022 | case M_TGE_I: | |
8023 | s = "tge"; | |
8024 | goto trap; | |
8025 | case M_TGEU_I: | |
8026 | s = "tgeu"; | |
8027 | goto trap; | |
8028 | case M_TLT_I: | |
8029 | s = "tlt"; | |
8030 | goto trap; | |
8031 | case M_TLTU_I: | |
8032 | s = "tltu"; | |
8033 | goto trap; | |
8034 | case M_TNE_I: | |
8035 | s = "tne"; | |
8036 | trap: | |
8fc2e39e | 8037 | used_at = 1; |
67c0d1eb RS |
8038 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
8039 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
8040 | break; |
8041 | ||
252b5132 | 8042 | case M_TRUNCWS: |
43841e91 | 8043 | case M_TRUNCWD: |
9c2799c2 | 8044 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 8045 | used_at = 1; |
252b5132 RH |
8046 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
8047 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
8048 | ||
8049 | /* | |
8050 | * Is the double cfc1 instruction a bug in the mips assembler; | |
8051 | * or is there a reason for it? | |
8052 | */ | |
7d10b47d | 8053 | start_noreorder (); |
67c0d1eb RS |
8054 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
8055 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
8056 | macro_build (NULL, "nop", ""); | |
252b5132 | 8057 | expr1.X_add_number = 3; |
67c0d1eb | 8058 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 8059 | expr1.X_add_number = 2; |
67c0d1eb RS |
8060 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
8061 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
8062 | macro_build (NULL, "nop", ""); | |
8063 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
8064 | dreg, sreg); | |
8065 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
8066 | macro_build (NULL, "nop", ""); | |
7d10b47d | 8067 | end_noreorder (); |
252b5132 RH |
8068 | break; |
8069 | ||
8070 | case M_ULH: | |
8071 | s = "lb"; | |
8072 | goto ulh; | |
8073 | case M_ULHU: | |
8074 | s = "lbu"; | |
8075 | ulh: | |
8fc2e39e | 8076 | used_at = 1; |
252b5132 RH |
8077 | if (offset_expr.X_add_number >= 0x7fff) |
8078 | as_bad (_("operand overflow")); | |
252b5132 | 8079 | if (! target_big_endian) |
f9419b05 | 8080 | ++offset_expr.X_add_number; |
67c0d1eb | 8081 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 8082 | if (! target_big_endian) |
f9419b05 | 8083 | --offset_expr.X_add_number; |
252b5132 | 8084 | else |
f9419b05 | 8085 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8086 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8087 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
8088 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8089 | break; |
8090 | ||
8091 | case M_ULD: | |
8092 | s = "ldl"; | |
8093 | s2 = "ldr"; | |
8094 | off = 7; | |
8095 | goto ulw; | |
8096 | case M_ULW: | |
8097 | s = "lwl"; | |
8098 | s2 = "lwr"; | |
8099 | off = 3; | |
8100 | ulw: | |
8101 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8102 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
8103 | if (treg != breg) |
8104 | tempreg = treg; | |
8105 | else | |
8fc2e39e TS |
8106 | { |
8107 | used_at = 1; | |
8108 | tempreg = AT; | |
8109 | } | |
252b5132 RH |
8110 | if (! target_big_endian) |
8111 | offset_expr.X_add_number += off; | |
67c0d1eb | 8112 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
8113 | if (! target_big_endian) |
8114 | offset_expr.X_add_number -= off; | |
8115 | else | |
8116 | offset_expr.X_add_number += off; | |
67c0d1eb | 8117 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
8118 | |
8119 | /* If necessary, move the result in tempreg the final destination. */ | |
8120 | if (treg == tempreg) | |
8fc2e39e | 8121 | break; |
af22f5b2 | 8122 | /* Protect second load's delay slot. */ |
017315e4 | 8123 | load_delay_nop (); |
67c0d1eb | 8124 | move_register (treg, tempreg); |
af22f5b2 | 8125 | break; |
252b5132 RH |
8126 | |
8127 | case M_ULD_A: | |
8128 | s = "ldl"; | |
8129 | s2 = "ldr"; | |
8130 | off = 7; | |
8131 | goto ulwa; | |
8132 | case M_ULW_A: | |
8133 | s = "lwl"; | |
8134 | s2 = "lwr"; | |
8135 | off = 3; | |
8136 | ulwa: | |
d6bc6245 | 8137 | used_at = 1; |
67c0d1eb | 8138 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8139 | if (breg != 0) |
67c0d1eb | 8140 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8141 | if (! target_big_endian) |
8142 | expr1.X_add_number = off; | |
8143 | else | |
8144 | expr1.X_add_number = 0; | |
67c0d1eb | 8145 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8146 | if (! target_big_endian) |
8147 | expr1.X_add_number = 0; | |
8148 | else | |
8149 | expr1.X_add_number = off; | |
67c0d1eb | 8150 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8151 | break; |
8152 | ||
8153 | case M_ULH_A: | |
8154 | case M_ULHU_A: | |
d6bc6245 | 8155 | used_at = 1; |
67c0d1eb | 8156 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8157 | if (breg != 0) |
67c0d1eb | 8158 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8159 | if (target_big_endian) |
8160 | expr1.X_add_number = 0; | |
67c0d1eb | 8161 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 8162 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8163 | if (target_big_endian) |
8164 | expr1.X_add_number = 1; | |
8165 | else | |
8166 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8167 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8168 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8169 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8170 | break; |
8171 | ||
8172 | case M_USH: | |
8fc2e39e | 8173 | used_at = 1; |
252b5132 RH |
8174 | if (offset_expr.X_add_number >= 0x7fff) |
8175 | as_bad (_("operand overflow")); | |
8176 | if (target_big_endian) | |
f9419b05 | 8177 | ++offset_expr.X_add_number; |
67c0d1eb RS |
8178 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8179 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 8180 | if (target_big_endian) |
f9419b05 | 8181 | --offset_expr.X_add_number; |
252b5132 | 8182 | else |
f9419b05 | 8183 | ++offset_expr.X_add_number; |
67c0d1eb | 8184 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
8185 | break; |
8186 | ||
8187 | case M_USD: | |
8188 | s = "sdl"; | |
8189 | s2 = "sdr"; | |
8190 | off = 7; | |
8191 | goto usw; | |
8192 | case M_USW: | |
8193 | s = "swl"; | |
8194 | s2 = "swr"; | |
8195 | off = 3; | |
8196 | usw: | |
8197 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8198 | as_bad (_("operand overflow")); | |
8199 | if (! target_big_endian) | |
8200 | offset_expr.X_add_number += off; | |
67c0d1eb | 8201 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
8202 | if (! target_big_endian) |
8203 | offset_expr.X_add_number -= off; | |
8204 | else | |
8205 | offset_expr.X_add_number += off; | |
67c0d1eb | 8206 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 8207 | break; |
252b5132 RH |
8208 | |
8209 | case M_USD_A: | |
8210 | s = "sdl"; | |
8211 | s2 = "sdr"; | |
8212 | off = 7; | |
8213 | goto uswa; | |
8214 | case M_USW_A: | |
8215 | s = "swl"; | |
8216 | s2 = "swr"; | |
8217 | off = 3; | |
8218 | uswa: | |
d6bc6245 | 8219 | used_at = 1; |
67c0d1eb | 8220 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8221 | if (breg != 0) |
67c0d1eb | 8222 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8223 | if (! target_big_endian) |
8224 | expr1.X_add_number = off; | |
8225 | else | |
8226 | expr1.X_add_number = 0; | |
67c0d1eb | 8227 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8228 | if (! target_big_endian) |
8229 | expr1.X_add_number = 0; | |
8230 | else | |
8231 | expr1.X_add_number = off; | |
67c0d1eb | 8232 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8233 | break; |
8234 | ||
8235 | case M_USH_A: | |
d6bc6245 | 8236 | used_at = 1; |
67c0d1eb | 8237 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 8238 | if (breg != 0) |
67c0d1eb | 8239 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
8240 | if (! target_big_endian) |
8241 | expr1.X_add_number = 0; | |
67c0d1eb RS |
8242 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
8243 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
8244 | if (! target_big_endian) |
8245 | expr1.X_add_number = 1; | |
8246 | else | |
8247 | expr1.X_add_number = 0; | |
67c0d1eb | 8248 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
8249 | if (! target_big_endian) |
8250 | expr1.X_add_number = 0; | |
8251 | else | |
8252 | expr1.X_add_number = 1; | |
67c0d1eb RS |
8253 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
8254 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
8255 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
8256 | break; |
8257 | ||
8258 | default: | |
8259 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 8260 | are added dynamically. */ |
252b5132 RH |
8261 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
8262 | break; | |
8263 | } | |
741fe287 | 8264 | if (!mips_opts.at && used_at) |
8fc2e39e | 8265 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
8266 | } |
8267 | ||
8268 | /* Implement macros in mips16 mode. */ | |
8269 | ||
8270 | static void | |
17a2f251 | 8271 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
8272 | { |
8273 | int mask; | |
8274 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
8275 | expressionS expr1; |
8276 | int dbl; | |
8277 | const char *s, *s2, *s3; | |
8278 | ||
8279 | mask = ip->insn_mo->mask; | |
8280 | ||
bf12938e RS |
8281 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
8282 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
8283 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 8284 | |
252b5132 RH |
8285 | expr1.X_op = O_constant; |
8286 | expr1.X_op_symbol = NULL; | |
8287 | expr1.X_add_symbol = NULL; | |
8288 | expr1.X_add_number = 1; | |
8289 | ||
8290 | dbl = 0; | |
8291 | ||
8292 | switch (mask) | |
8293 | { | |
8294 | default: | |
8295 | internalError (); | |
8296 | ||
8297 | case M_DDIV_3: | |
8298 | dbl = 1; | |
8299 | case M_DIV_3: | |
8300 | s = "mflo"; | |
8301 | goto do_div3; | |
8302 | case M_DREM_3: | |
8303 | dbl = 1; | |
8304 | case M_REM_3: | |
8305 | s = "mfhi"; | |
8306 | do_div3: | |
7d10b47d | 8307 | start_noreorder (); |
67c0d1eb | 8308 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 8309 | expr1.X_add_number = 2; |
67c0d1eb RS |
8310 | macro_build (&expr1, "bnez", "x,p", yreg); |
8311 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 8312 | |
252b5132 RH |
8313 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
8314 | since that causes an overflow. We should do that as well, | |
8315 | but I don't see how to do the comparisons without a temporary | |
8316 | register. */ | |
7d10b47d | 8317 | end_noreorder (); |
67c0d1eb | 8318 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
8319 | break; |
8320 | ||
8321 | case M_DIVU_3: | |
8322 | s = "divu"; | |
8323 | s2 = "mflo"; | |
8324 | goto do_divu3; | |
8325 | case M_REMU_3: | |
8326 | s = "divu"; | |
8327 | s2 = "mfhi"; | |
8328 | goto do_divu3; | |
8329 | case M_DDIVU_3: | |
8330 | s = "ddivu"; | |
8331 | s2 = "mflo"; | |
8332 | goto do_divu3; | |
8333 | case M_DREMU_3: | |
8334 | s = "ddivu"; | |
8335 | s2 = "mfhi"; | |
8336 | do_divu3: | |
7d10b47d | 8337 | start_noreorder (); |
67c0d1eb | 8338 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8339 | expr1.X_add_number = 2; |
67c0d1eb RS |
8340 | macro_build (&expr1, "bnez", "x,p", yreg); |
8341 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8342 | end_noreorder (); |
67c0d1eb | 8343 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8344 | break; |
8345 | ||
8346 | case M_DMUL: | |
8347 | dbl = 1; | |
8348 | case M_MUL: | |
67c0d1eb RS |
8349 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8350 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8351 | break; |
252b5132 RH |
8352 | |
8353 | case M_DSUBU_I: | |
8354 | dbl = 1; | |
8355 | goto do_subu; | |
8356 | case M_SUBU_I: | |
8357 | do_subu: | |
8358 | if (imm_expr.X_op != O_constant) | |
8359 | as_bad (_("Unsupported large constant")); | |
8360 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8361 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8362 | break; |
8363 | ||
8364 | case M_SUBU_I_2: | |
8365 | if (imm_expr.X_op != O_constant) | |
8366 | as_bad (_("Unsupported large constant")); | |
8367 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8368 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8369 | break; |
8370 | ||
8371 | case M_DSUBU_I_2: | |
8372 | if (imm_expr.X_op != O_constant) | |
8373 | as_bad (_("Unsupported large constant")); | |
8374 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8375 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8376 | break; |
8377 | ||
8378 | case M_BEQ: | |
8379 | s = "cmp"; | |
8380 | s2 = "bteqz"; | |
8381 | goto do_branch; | |
8382 | case M_BNE: | |
8383 | s = "cmp"; | |
8384 | s2 = "btnez"; | |
8385 | goto do_branch; | |
8386 | case M_BLT: | |
8387 | s = "slt"; | |
8388 | s2 = "btnez"; | |
8389 | goto do_branch; | |
8390 | case M_BLTU: | |
8391 | s = "sltu"; | |
8392 | s2 = "btnez"; | |
8393 | goto do_branch; | |
8394 | case M_BLE: | |
8395 | s = "slt"; | |
8396 | s2 = "bteqz"; | |
8397 | goto do_reverse_branch; | |
8398 | case M_BLEU: | |
8399 | s = "sltu"; | |
8400 | s2 = "bteqz"; | |
8401 | goto do_reverse_branch; | |
8402 | case M_BGE: | |
8403 | s = "slt"; | |
8404 | s2 = "bteqz"; | |
8405 | goto do_branch; | |
8406 | case M_BGEU: | |
8407 | s = "sltu"; | |
8408 | s2 = "bteqz"; | |
8409 | goto do_branch; | |
8410 | case M_BGT: | |
8411 | s = "slt"; | |
8412 | s2 = "btnez"; | |
8413 | goto do_reverse_branch; | |
8414 | case M_BGTU: | |
8415 | s = "sltu"; | |
8416 | s2 = "btnez"; | |
8417 | ||
8418 | do_reverse_branch: | |
8419 | tmp = xreg; | |
8420 | xreg = yreg; | |
8421 | yreg = tmp; | |
8422 | ||
8423 | do_branch: | |
67c0d1eb RS |
8424 | macro_build (NULL, s, "x,y", xreg, yreg); |
8425 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8426 | break; |
8427 | ||
8428 | case M_BEQ_I: | |
8429 | s = "cmpi"; | |
8430 | s2 = "bteqz"; | |
8431 | s3 = "x,U"; | |
8432 | goto do_branch_i; | |
8433 | case M_BNE_I: | |
8434 | s = "cmpi"; | |
8435 | s2 = "btnez"; | |
8436 | s3 = "x,U"; | |
8437 | goto do_branch_i; | |
8438 | case M_BLT_I: | |
8439 | s = "slti"; | |
8440 | s2 = "btnez"; | |
8441 | s3 = "x,8"; | |
8442 | goto do_branch_i; | |
8443 | case M_BLTU_I: | |
8444 | s = "sltiu"; | |
8445 | s2 = "btnez"; | |
8446 | s3 = "x,8"; | |
8447 | goto do_branch_i; | |
8448 | case M_BLE_I: | |
8449 | s = "slti"; | |
8450 | s2 = "btnez"; | |
8451 | s3 = "x,8"; | |
8452 | goto do_addone_branch_i; | |
8453 | case M_BLEU_I: | |
8454 | s = "sltiu"; | |
8455 | s2 = "btnez"; | |
8456 | s3 = "x,8"; | |
8457 | goto do_addone_branch_i; | |
8458 | case M_BGE_I: | |
8459 | s = "slti"; | |
8460 | s2 = "bteqz"; | |
8461 | s3 = "x,8"; | |
8462 | goto do_branch_i; | |
8463 | case M_BGEU_I: | |
8464 | s = "sltiu"; | |
8465 | s2 = "bteqz"; | |
8466 | s3 = "x,8"; | |
8467 | goto do_branch_i; | |
8468 | case M_BGT_I: | |
8469 | s = "slti"; | |
8470 | s2 = "bteqz"; | |
8471 | s3 = "x,8"; | |
8472 | goto do_addone_branch_i; | |
8473 | case M_BGTU_I: | |
8474 | s = "sltiu"; | |
8475 | s2 = "bteqz"; | |
8476 | s3 = "x,8"; | |
8477 | ||
8478 | do_addone_branch_i: | |
8479 | if (imm_expr.X_op != O_constant) | |
8480 | as_bad (_("Unsupported large constant")); | |
8481 | ++imm_expr.X_add_number; | |
8482 | ||
8483 | do_branch_i: | |
67c0d1eb RS |
8484 | macro_build (&imm_expr, s, s3, xreg); |
8485 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8486 | break; |
8487 | ||
8488 | case M_ABS: | |
8489 | expr1.X_add_number = 0; | |
67c0d1eb | 8490 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8491 | if (xreg != yreg) |
67c0d1eb | 8492 | move_register (xreg, yreg); |
252b5132 | 8493 | expr1.X_add_number = 2; |
67c0d1eb RS |
8494 | macro_build (&expr1, "bteqz", "p"); |
8495 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8496 | } |
8497 | } | |
8498 | ||
8499 | /* For consistency checking, verify that all bits are specified either | |
8500 | by the match/mask part of the instruction definition, or by the | |
8501 | operand list. */ | |
8502 | static int | |
17a2f251 | 8503 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8504 | { |
8505 | const char *p = opc->args; | |
8506 | char c; | |
8507 | unsigned long used_bits = opc->mask; | |
8508 | ||
8509 | if ((used_bits & opc->match) != opc->match) | |
8510 | { | |
8511 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8512 | opc->name, opc->args); | |
8513 | return 0; | |
8514 | } | |
8515 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8516 | while (*p) | |
8517 | switch (c = *p++) | |
8518 | { | |
8519 | case ',': break; | |
8520 | case '(': break; | |
8521 | case ')': break; | |
af7ee8bf CD |
8522 | case '+': |
8523 | switch (c = *p++) | |
8524 | { | |
9bcd4f99 TS |
8525 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8526 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8527 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8528 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8529 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8530 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8531 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8532 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8533 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8534 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8535 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8536 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8537 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8538 | case 'I': break; | |
ef2e4d86 CF |
8539 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8540 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8541 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
8542 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
8543 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
8544 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
8545 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 8546 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
8547 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
8548 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
8549 | ||
af7ee8bf CD |
8550 | default: |
8551 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8552 | c, opc->name, opc->args); | |
8553 | return 0; | |
8554 | } | |
8555 | break; | |
252b5132 RH |
8556 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8557 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8558 | case 'A': break; | |
4372b673 | 8559 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8560 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8561 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8562 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8563 | case 'F': break; | |
8564 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8565 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8566 | case 'I': break; |
e972090a | 8567 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8568 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8569 | case 'L': break; |
8570 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8571 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8572 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8573 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8574 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8575 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8576 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8577 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8578 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8579 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8580 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8581 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8582 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8583 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8584 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8585 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8586 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8587 | case 'f': break; | |
8588 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8589 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8590 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8591 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8592 | case 'l': break; | |
8593 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8594 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8595 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8596 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8597 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8598 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8599 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8600 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8601 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8602 | case 'x': break; | |
8603 | case 'z': break; | |
8604 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8605 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8606 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8607 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8608 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8609 | case '[': break; | |
8610 | case ']': break; | |
620edafd | 8611 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 8612 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8613 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8614 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8615 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8616 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8617 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8618 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8619 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8620 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8621 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8622 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8623 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8624 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8625 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8626 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8627 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8628 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8629 | default: |
8630 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8631 | c, opc->name, opc->args); | |
8632 | return 0; | |
8633 | } | |
8634 | #undef USE_BITS | |
8635 | if (used_bits != 0xffffffff) | |
8636 | { | |
8637 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8638 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8639 | return 0; | |
8640 | } | |
8641 | return 1; | |
8642 | } | |
8643 | ||
9bcd4f99 TS |
8644 | /* UDI immediates. */ |
8645 | struct mips_immed { | |
8646 | char type; | |
8647 | unsigned int shift; | |
8648 | unsigned long mask; | |
8649 | const char * desc; | |
8650 | }; | |
8651 | ||
8652 | static const struct mips_immed mips_immed[] = { | |
8653 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8654 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8655 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8656 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8657 | { 0,0,0,0 } | |
8658 | }; | |
8659 | ||
7455baf8 TS |
8660 | /* Check whether an odd floating-point register is allowed. */ |
8661 | static int | |
8662 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8663 | { | |
8664 | const char *s = insn->name; | |
8665 | ||
8666 | if (insn->pinfo == INSN_MACRO) | |
8667 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8668 | return 1; | |
8669 | ||
8670 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8671 | { | |
8672 | /* Allow odd registers for single-precision ops. */ | |
8673 | switch (insn->pinfo & (FP_S | FP_D)) | |
8674 | { | |
8675 | case FP_S: | |
8676 | case 0: | |
8677 | return 1; /* both single precision - ok */ | |
8678 | case FP_D: | |
8679 | return 0; /* both double precision - fail */ | |
8680 | default: | |
8681 | break; | |
8682 | } | |
8683 | ||
8684 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8685 | s = strchr (insn->name, '.'); | |
8686 | if (argnum == 2) | |
8687 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8688 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8689 | } | |
8690 | ||
8691 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8692 | if ((insn->pinfo & FP_S) | |
8693 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8694 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8695 | return 1; | |
8696 | ||
8697 | return 0; | |
8698 | } | |
8699 | ||
252b5132 RH |
8700 | /* This routine assembles an instruction into its binary format. As a |
8701 | side effect, it sets one of the global variables imm_reloc or | |
8702 | offset_reloc to the type of relocation to do if one of the operands | |
8703 | is an address expression. */ | |
8704 | ||
8705 | static void | |
17a2f251 | 8706 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8707 | { |
8708 | char *s; | |
8709 | const char *args; | |
43841e91 | 8710 | char c = 0; |
252b5132 RH |
8711 | struct mips_opcode *insn; |
8712 | char *argsStart; | |
8713 | unsigned int regno; | |
8714 | unsigned int lastregno = 0; | |
af7ee8bf | 8715 | unsigned int lastpos = 0; |
071742cf | 8716 | unsigned int limlo, limhi; |
252b5132 RH |
8717 | char *s_reset; |
8718 | char save_c = 0; | |
74cd071d | 8719 | offsetT min_range, max_range; |
707bfff6 TS |
8720 | int argnum; |
8721 | unsigned int rtype; | |
252b5132 RH |
8722 | |
8723 | insn_error = NULL; | |
8724 | ||
8725 | /* If the instruction contains a '.', we first try to match an instruction | |
8726 | including the '.'. Then we try again without the '.'. */ | |
8727 | insn = NULL; | |
3882b010 | 8728 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8729 | continue; |
8730 | ||
8731 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8732 | the call to hash_find. Save the character we replaced just in case we | |
8733 | have to re-parse the instruction. */ | |
3882b010 | 8734 | if (ISSPACE (*s)) |
252b5132 RH |
8735 | { |
8736 | save_c = *s; | |
8737 | *s++ = '\0'; | |
8738 | } | |
bdaaa2e1 | 8739 | |
252b5132 RH |
8740 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8741 | ||
8742 | /* If we didn't find the instruction in the opcode table, try again, but | |
8743 | this time with just the instruction up to, but not including the | |
8744 | first '.'. */ | |
8745 | if (insn == NULL) | |
8746 | { | |
bdaaa2e1 | 8747 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8748 | if (save_c) |
8749 | *(--s) = save_c; | |
8750 | ||
8751 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8752 | for (s = str; |
8753 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8754 | ++s) | |
252b5132 RH |
8755 | continue; |
8756 | ||
8757 | /* If we did not find a '.', then we can quit now. */ | |
8758 | if (*s != '.') | |
8759 | { | |
20203fb9 | 8760 | insn_error = _("unrecognized opcode"); |
252b5132 RH |
8761 | return; |
8762 | } | |
8763 | ||
8764 | /* Lookup the instruction in the hash table. */ | |
8765 | *s++ = '\0'; | |
8766 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8767 | { | |
20203fb9 | 8768 | insn_error = _("unrecognized opcode"); |
252b5132 RH |
8769 | return; |
8770 | } | |
252b5132 RH |
8771 | } |
8772 | ||
8773 | argsStart = s; | |
8774 | for (;;) | |
8775 | { | |
b34976b6 | 8776 | bfd_boolean ok; |
252b5132 | 8777 | |
9c2799c2 | 8778 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 8779 | |
f79e2745 | 8780 | ok = is_opcode_valid (insn); |
252b5132 RH |
8781 | if (! ok) |
8782 | { | |
8783 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8784 | && strcmp (insn->name, insn[1].name) == 0) | |
8785 | { | |
8786 | ++insn; | |
8787 | continue; | |
8788 | } | |
252b5132 | 8789 | else |
beae10d5 | 8790 | { |
268f6bed L |
8791 | if (!insn_error) |
8792 | { | |
8793 | static char buf[100]; | |
fef14a42 TS |
8794 | sprintf (buf, |
8795 | _("opcode not supported on this processor: %s (%s)"), | |
8796 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8797 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8798 | insn_error = buf; |
8799 | } | |
8800 | if (save_c) | |
8801 | *(--s) = save_c; | |
2bd7f1f3 | 8802 | return; |
252b5132 | 8803 | } |
252b5132 RH |
8804 | } |
8805 | ||
1e915849 | 8806 | create_insn (ip, insn); |
268f6bed | 8807 | insn_error = NULL; |
707bfff6 | 8808 | argnum = 1; |
24864476 | 8809 | lastregno = 0xffffffff; |
252b5132 RH |
8810 | for (args = insn->args;; ++args) |
8811 | { | |
deec1734 CD |
8812 | int is_mdmx; |
8813 | ||
ad8d3bb3 | 8814 | s += strspn (s, " \t"); |
deec1734 | 8815 | is_mdmx = 0; |
252b5132 RH |
8816 | switch (*args) |
8817 | { | |
8818 | case '\0': /* end of args */ | |
8819 | if (*s == '\0') | |
8820 | return; | |
8821 | break; | |
8822 | ||
8b082fb1 TS |
8823 | case '2': /* dsp 2-bit unsigned immediate in bit 11 */ |
8824 | my_getExpression (&imm_expr, s); | |
8825 | check_absolute_expr (ip, &imm_expr); | |
8826 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8827 | && (unsigned long) imm_expr.X_add_number != 3) | |
8828 | { | |
8829 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8830 | (unsigned long) imm_expr.X_add_number); | |
8831 | } | |
8832 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8833 | imm_expr.X_op = O_absent; | |
8834 | s = expr_end; | |
8835 | continue; | |
8836 | ||
74cd071d CF |
8837 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8838 | my_getExpression (&imm_expr, s); | |
8839 | check_absolute_expr (ip, &imm_expr); | |
8840 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8841 | { | |
a9e24354 TS |
8842 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8843 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8844 | } |
a9e24354 | 8845 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8846 | imm_expr.X_op = O_absent; |
8847 | s = expr_end; | |
8848 | continue; | |
8849 | ||
8850 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8851 | my_getExpression (&imm_expr, s); | |
8852 | check_absolute_expr (ip, &imm_expr); | |
8853 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8854 | { | |
a9e24354 TS |
8855 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8856 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8857 | } |
a9e24354 | 8858 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8859 | imm_expr.X_op = O_absent; |
8860 | s = expr_end; | |
8861 | continue; | |
8862 | ||
8863 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8864 | my_getExpression (&imm_expr, s); | |
8865 | check_absolute_expr (ip, &imm_expr); | |
8866 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8867 | { | |
a9e24354 TS |
8868 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8869 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8870 | } |
a9e24354 | 8871 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8872 | imm_expr.X_op = O_absent; |
8873 | s = expr_end; | |
8874 | continue; | |
8875 | ||
8876 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8877 | my_getExpression (&imm_expr, s); | |
8878 | check_absolute_expr (ip, &imm_expr); | |
8879 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8880 | { | |
a9e24354 TS |
8881 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8882 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8883 | } |
a9e24354 | 8884 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8885 | imm_expr.X_op = O_absent; |
8886 | s = expr_end; | |
8887 | continue; | |
8888 | ||
8889 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8890 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8891 | s[3] >= '0' && s[3] <= '3') | |
8892 | { | |
8893 | regno = s[3] - '0'; | |
8894 | s += 4; | |
a9e24354 | 8895 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8896 | continue; |
8897 | } | |
8898 | else | |
8899 | as_bad (_("Invalid dsp acc register")); | |
8900 | break; | |
8901 | ||
8902 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8903 | my_getExpression (&imm_expr, s); | |
8904 | check_absolute_expr (ip, &imm_expr); | |
8905 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8906 | { | |
a9e24354 TS |
8907 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8908 | OP_MASK_WRDSP, | |
8909 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8910 | } |
a9e24354 | 8911 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8912 | imm_expr.X_op = O_absent; |
8913 | s = expr_end; | |
8914 | continue; | |
8915 | ||
8916 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8917 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8918 | s[3] >= '0' && s[3] <= '3') | |
8919 | { | |
8920 | regno = s[3] - '0'; | |
8921 | s += 4; | |
a9e24354 | 8922 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8923 | continue; |
8924 | } | |
8925 | else | |
8926 | as_bad (_("Invalid dsp acc register")); | |
8927 | break; | |
8928 | ||
8929 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8930 | my_getExpression (&imm_expr, s); | |
8931 | check_absolute_expr (ip, &imm_expr); | |
8932 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8933 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8934 | if (imm_expr.X_add_number < min_range || | |
8935 | imm_expr.X_add_number > max_range) | |
8936 | { | |
a9e24354 TS |
8937 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8938 | (long) min_range, (long) max_range, | |
8939 | (long) imm_expr.X_add_number); | |
74cd071d | 8940 | } |
a9e24354 | 8941 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8942 | imm_expr.X_op = O_absent; |
8943 | s = expr_end; | |
8944 | continue; | |
8945 | ||
8946 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8947 | my_getExpression (&imm_expr, s); | |
8948 | check_absolute_expr (ip, &imm_expr); | |
8949 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8950 | { | |
a9e24354 TS |
8951 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8952 | OP_MASK_RDDSP, | |
8953 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8954 | } |
a9e24354 | 8955 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8956 | imm_expr.X_op = O_absent; |
8957 | s = expr_end; | |
8958 | continue; | |
8959 | ||
8960 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8961 | my_getExpression (&imm_expr, s); | |
8962 | check_absolute_expr (ip, &imm_expr); | |
8963 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8964 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8965 | if (imm_expr.X_add_number < min_range || | |
8966 | imm_expr.X_add_number > max_range) | |
8967 | { | |
a9e24354 TS |
8968 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8969 | (long) min_range, (long) max_range, | |
8970 | (long) imm_expr.X_add_number); | |
74cd071d | 8971 | } |
a9e24354 | 8972 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8973 | imm_expr.X_op = O_absent; |
8974 | s = expr_end; | |
8975 | continue; | |
8976 | ||
8977 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8978 | my_getExpression (&imm_expr, s); | |
8979 | check_absolute_expr (ip, &imm_expr); | |
8980 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8981 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8982 | if (imm_expr.X_add_number < min_range || | |
8983 | imm_expr.X_add_number > max_range) | |
8984 | { | |
a9e24354 TS |
8985 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8986 | (long) min_range, (long) max_range, | |
8987 | (long) imm_expr.X_add_number); | |
74cd071d | 8988 | } |
a9e24354 | 8989 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8990 | imm_expr.X_op = O_absent; |
8991 | s = expr_end; | |
8992 | continue; | |
8993 | ||
a9e24354 | 8994 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8995 | my_getExpression (&imm_expr, s); |
8996 | check_absolute_expr (ip, &imm_expr); | |
8997 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8998 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8999 | (unsigned long) imm_expr.X_add_number); | |
9000 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9001 | imm_expr.X_op = O_absent; |
9002 | s = expr_end; | |
9003 | continue; | |
9004 | ||
a9e24354 | 9005 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
9006 | my_getExpression (&imm_expr, s); |
9007 | check_absolute_expr (ip, &imm_expr); | |
9008 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
9009 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
9010 | (unsigned long) imm_expr.X_add_number); | |
9011 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
9012 | imm_expr.X_op = O_absent; |
9013 | s = expr_end; | |
9014 | continue; | |
9015 | ||
9016 | case '*': /* four dsp accumulators in bits 18,19 */ | |
9017 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
9018 | s[3] >= '0' && s[3] <= '3') | |
9019 | { | |
9020 | regno = s[3] - '0'; | |
9021 | s += 4; | |
a9e24354 | 9022 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
9023 | continue; |
9024 | } | |
9025 | else | |
9026 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9027 | break; | |
9028 | ||
9029 | case '&': /* four dsp accumulators in bits 13,14 */ | |
9030 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
9031 | s[3] >= '0' && s[3] <= '3') | |
9032 | { | |
9033 | regno = s[3] - '0'; | |
9034 | s += 4; | |
a9e24354 | 9035 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
9036 | continue; |
9037 | } | |
9038 | else | |
9039 | as_bad (_("Invalid dsp/smartmips acc register")); | |
9040 | break; | |
9041 | ||
252b5132 | 9042 | case ',': |
a339155f | 9043 | ++argnum; |
252b5132 RH |
9044 | if (*s++ == *args) |
9045 | continue; | |
9046 | s--; | |
9047 | switch (*++args) | |
9048 | { | |
9049 | case 'r': | |
9050 | case 'v': | |
bf12938e | 9051 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9052 | continue; |
9053 | ||
9054 | case 'w': | |
bf12938e | 9055 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
9056 | continue; |
9057 | ||
252b5132 | 9058 | case 'W': |
bf12938e | 9059 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9060 | continue; |
9061 | ||
9062 | case 'V': | |
bf12938e | 9063 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9064 | continue; |
9065 | } | |
9066 | break; | |
9067 | ||
9068 | case '(': | |
9069 | /* Handle optional base register. | |
9070 | Either the base register is omitted or | |
bdaaa2e1 | 9071 | we must have a left paren. */ |
252b5132 RH |
9072 | /* This is dependent on the next operand specifier |
9073 | is a base register specification. */ | |
9c2799c2 | 9074 | gas_assert (args[1] == 'b' || args[1] == '5' |
252b5132 RH |
9075 | || args[1] == '-' || args[1] == '4'); |
9076 | if (*s == '\0') | |
9077 | return; | |
9078 | ||
9079 | case ')': /* these must match exactly */ | |
60b63b72 RS |
9080 | case '[': |
9081 | case ']': | |
252b5132 RH |
9082 | if (*s++ == *args) |
9083 | continue; | |
9084 | break; | |
9085 | ||
af7ee8bf CD |
9086 | case '+': /* Opcode extension character. */ |
9087 | switch (*++args) | |
9088 | { | |
9bcd4f99 TS |
9089 | case '1': /* UDI immediates. */ |
9090 | case '2': | |
9091 | case '3': | |
9092 | case '4': | |
9093 | { | |
9094 | const struct mips_immed *imm = mips_immed; | |
9095 | ||
9096 | while (imm->type && imm->type != *args) | |
9097 | ++imm; | |
9098 | if (! imm->type) | |
9099 | internalError (); | |
9100 | my_getExpression (&imm_expr, s); | |
9101 | check_absolute_expr (ip, &imm_expr); | |
9102 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
9103 | { | |
9104 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
9105 | imm->desc ? imm->desc : ip->insn_mo->name, | |
9106 | (unsigned long) imm_expr.X_add_number, | |
9107 | (unsigned long) imm_expr.X_add_number); | |
9108 | imm_expr.X_add_number &= imm->mask; | |
9109 | } | |
9110 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
9111 | << imm->shift); | |
9112 | imm_expr.X_op = O_absent; | |
9113 | s = expr_end; | |
9114 | } | |
9115 | continue; | |
9116 | ||
071742cf CD |
9117 | case 'A': /* ins/ext position, becomes LSB. */ |
9118 | limlo = 0; | |
9119 | limhi = 31; | |
5f74bc13 CD |
9120 | goto do_lsb; |
9121 | case 'E': | |
9122 | limlo = 32; | |
9123 | limhi = 63; | |
9124 | goto do_lsb; | |
9125 | do_lsb: | |
071742cf CD |
9126 | my_getExpression (&imm_expr, s); |
9127 | check_absolute_expr (ip, &imm_expr); | |
9128 | if ((unsigned long) imm_expr.X_add_number < limlo | |
9129 | || (unsigned long) imm_expr.X_add_number > limhi) | |
9130 | { | |
9131 | as_bad (_("Improper position (%lu)"), | |
9132 | (unsigned long) imm_expr.X_add_number); | |
9133 | imm_expr.X_add_number = limlo; | |
9134 | } | |
9135 | lastpos = imm_expr.X_add_number; | |
bf12938e | 9136 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
9137 | imm_expr.X_op = O_absent; |
9138 | s = expr_end; | |
9139 | continue; | |
9140 | ||
9141 | case 'B': /* ins size, becomes MSB. */ | |
9142 | limlo = 1; | |
9143 | limhi = 32; | |
5f74bc13 CD |
9144 | goto do_msb; |
9145 | case 'F': | |
9146 | limlo = 33; | |
9147 | limhi = 64; | |
9148 | goto do_msb; | |
9149 | do_msb: | |
071742cf CD |
9150 | my_getExpression (&imm_expr, s); |
9151 | check_absolute_expr (ip, &imm_expr); | |
9152 | /* Check for negative input so that small negative numbers | |
9153 | will not succeed incorrectly. The checks against | |
9154 | (pos+size) transitively check "size" itself, | |
9155 | assuming that "pos" is reasonable. */ | |
9156 | if ((long) imm_expr.X_add_number < 0 | |
9157 | || ((unsigned long) imm_expr.X_add_number | |
9158 | + lastpos) < limlo | |
9159 | || ((unsigned long) imm_expr.X_add_number | |
9160 | + lastpos) > limhi) | |
9161 | { | |
9162 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
9163 | (unsigned long) imm_expr.X_add_number, | |
9164 | (unsigned long) lastpos); | |
9165 | imm_expr.X_add_number = limlo - lastpos; | |
9166 | } | |
bf12938e RS |
9167 | INSERT_OPERAND (INSMSB, *ip, |
9168 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
9169 | imm_expr.X_op = O_absent; |
9170 | s = expr_end; | |
9171 | continue; | |
9172 | ||
9173 | case 'C': /* ext size, becomes MSBD. */ | |
9174 | limlo = 1; | |
9175 | limhi = 32; | |
5f74bc13 CD |
9176 | goto do_msbd; |
9177 | case 'G': | |
9178 | limlo = 33; | |
9179 | limhi = 64; | |
9180 | goto do_msbd; | |
9181 | case 'H': | |
9182 | limlo = 33; | |
9183 | limhi = 64; | |
9184 | goto do_msbd; | |
9185 | do_msbd: | |
071742cf CD |
9186 | my_getExpression (&imm_expr, s); |
9187 | check_absolute_expr (ip, &imm_expr); | |
9188 | /* Check for negative input so that small negative numbers | |
9189 | will not succeed incorrectly. The checks against | |
9190 | (pos+size) transitively check "size" itself, | |
9191 | assuming that "pos" is reasonable. */ | |
9192 | if ((long) imm_expr.X_add_number < 0 | |
9193 | || ((unsigned long) imm_expr.X_add_number | |
9194 | + lastpos) < limlo | |
9195 | || ((unsigned long) imm_expr.X_add_number | |
9196 | + lastpos) > limhi) | |
9197 | { | |
9198 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
9199 | (unsigned long) imm_expr.X_add_number, | |
9200 | (unsigned long) lastpos); | |
9201 | imm_expr.X_add_number = limlo - lastpos; | |
9202 | } | |
bf12938e | 9203 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
9204 | imm_expr.X_op = O_absent; |
9205 | s = expr_end; | |
9206 | continue; | |
af7ee8bf | 9207 | |
bbcc0807 CD |
9208 | case 'D': |
9209 | /* +D is for disassembly only; never match. */ | |
9210 | break; | |
9211 | ||
5f74bc13 CD |
9212 | case 'I': |
9213 | /* "+I" is like "I", except that imm2_expr is used. */ | |
9214 | my_getExpression (&imm2_expr, s); | |
9215 | if (imm2_expr.X_op != O_big | |
9216 | && imm2_expr.X_op != O_constant) | |
9217 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9218 | if (HAVE_32BIT_GPRS) |
9219 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
9220 | s = expr_end; |
9221 | continue; | |
9222 | ||
707bfff6 | 9223 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
9224 | /* +T is for disassembly only; never match. */ |
9225 | break; | |
9226 | ||
707bfff6 | 9227 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
9228 | if (s[0] == '$' && ISDIGIT (s[1])) |
9229 | { | |
9230 | ++s; | |
9231 | regno = 0; | |
9232 | do | |
9233 | { | |
9234 | regno *= 10; | |
9235 | regno += *s - '0'; | |
9236 | ++s; | |
9237 | } | |
9238 | while (ISDIGIT (*s)); | |
9239 | if (regno > 31) | |
9240 | as_bad (_("Invalid register number (%d)"), regno); | |
9241 | else | |
9242 | { | |
a9e24354 | 9243 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
9244 | continue; |
9245 | } | |
9246 | } | |
9247 | else | |
9248 | as_bad (_("Invalid coprocessor 0 register number")); | |
9249 | break; | |
9250 | ||
bb35fb24 NC |
9251 | case 'x': |
9252 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
9253 | is not in the valid range. */ | |
9254 | my_getExpression (&imm_expr, s); | |
9255 | check_absolute_expr (ip, &imm_expr); | |
9256 | if ((unsigned) imm_expr.X_add_number > 31) | |
9257 | { | |
9258 | as_bad (_("Improper bit index (%lu)"), | |
9259 | (unsigned long) imm_expr.X_add_number); | |
9260 | imm_expr.X_add_number = 0; | |
9261 | } | |
9262 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number); | |
9263 | imm_expr.X_op = O_absent; | |
9264 | s = expr_end; | |
9265 | continue; | |
9266 | ||
9267 | case 'X': | |
9268 | /* bbit[01] bit index when bbit is used but we generate | |
9269 | bbit[01]32 because the index is over 32. Move to the | |
9270 | next candidate if index is not in the valid range. */ | |
9271 | my_getExpression (&imm_expr, s); | |
9272 | check_absolute_expr (ip, &imm_expr); | |
9273 | if ((unsigned) imm_expr.X_add_number < 32 | |
9274 | || (unsigned) imm_expr.X_add_number > 63) | |
9275 | break; | |
9276 | INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32); | |
9277 | imm_expr.X_op = O_absent; | |
9278 | s = expr_end; | |
9279 | continue; | |
9280 | ||
9281 | case 'p': | |
9282 | /* cins, cins32, exts and exts32 position field. Give error | |
9283 | if it's not in the valid range. */ | |
9284 | my_getExpression (&imm_expr, s); | |
9285 | check_absolute_expr (ip, &imm_expr); | |
9286 | if ((unsigned) imm_expr.X_add_number > 31) | |
9287 | { | |
9288 | as_bad (_("Improper position (%lu)"), | |
9289 | (unsigned long) imm_expr.X_add_number); | |
9290 | imm_expr.X_add_number = 0; | |
9291 | } | |
9292 | /* Make the pos explicit to simplify +S. */ | |
9293 | lastpos = imm_expr.X_add_number + 32; | |
9294 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number); | |
9295 | imm_expr.X_op = O_absent; | |
9296 | s = expr_end; | |
9297 | continue; | |
9298 | ||
9299 | case 'P': | |
9300 | /* cins, cins32, exts and exts32 position field. Move to | |
9301 | the next candidate if it's not in the valid range. */ | |
9302 | my_getExpression (&imm_expr, s); | |
9303 | check_absolute_expr (ip, &imm_expr); | |
9304 | if ((unsigned) imm_expr.X_add_number < 32 | |
9305 | || (unsigned) imm_expr.X_add_number > 63) | |
9306 | break; | |
9307 | lastpos = imm_expr.X_add_number; | |
9308 | INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32); | |
9309 | imm_expr.X_op = O_absent; | |
9310 | s = expr_end; | |
9311 | continue; | |
9312 | ||
9313 | case 's': | |
9314 | /* cins and exts length-minus-one field. */ | |
9315 | my_getExpression (&imm_expr, s); | |
9316 | check_absolute_expr (ip, &imm_expr); | |
9317 | if ((unsigned long) imm_expr.X_add_number > 31) | |
9318 | { | |
9319 | as_bad (_("Improper size (%lu)"), | |
9320 | (unsigned long) imm_expr.X_add_number); | |
9321 | imm_expr.X_add_number = 0; | |
9322 | } | |
9323 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9324 | imm_expr.X_op = O_absent; | |
9325 | s = expr_end; | |
9326 | continue; | |
9327 | ||
9328 | case 'S': | |
9329 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
9330 | length-minus-one field. */ | |
9331 | my_getExpression (&imm_expr, s); | |
9332 | check_absolute_expr (ip, &imm_expr); | |
9333 | if ((long) imm_expr.X_add_number < 0 | |
9334 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
9335 | { | |
9336 | as_bad (_("Improper size (%lu)"), | |
9337 | (unsigned long) imm_expr.X_add_number); | |
9338 | imm_expr.X_add_number = 0; | |
9339 | } | |
9340 | INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number); | |
9341 | imm_expr.X_op = O_absent; | |
9342 | s = expr_end; | |
9343 | continue; | |
9344 | ||
dd3cbb7e NC |
9345 | case 'Q': |
9346 | /* seqi/snei immediate field. */ | |
9347 | my_getExpression (&imm_expr, s); | |
9348 | check_absolute_expr (ip, &imm_expr); | |
9349 | if ((long) imm_expr.X_add_number < -512 | |
9350 | || (long) imm_expr.X_add_number >= 512) | |
9351 | { | |
9352 | as_bad (_("Improper immediate (%ld)"), | |
9353 | (long) imm_expr.X_add_number); | |
9354 | imm_expr.X_add_number = 0; | |
9355 | } | |
9356 | INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number); | |
9357 | imm_expr.X_op = O_absent; | |
9358 | s = expr_end; | |
9359 | continue; | |
9360 | ||
af7ee8bf CD |
9361 | default: |
9362 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
9363 | *args, insn->name, insn->args); | |
9364 | /* Further processing is fruitless. */ | |
9365 | return; | |
9366 | } | |
9367 | break; | |
9368 | ||
252b5132 RH |
9369 | case '<': /* must be at least one digit */ |
9370 | /* | |
9371 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
9372 | * than 31 or less than 0, then the shift amount should be |
9373 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
9374 | * We issue a warning and mask out all but the low 5 bits. |
9375 | */ | |
9376 | my_getExpression (&imm_expr, s); | |
9377 | check_absolute_expr (ip, &imm_expr); | |
9378 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9379 | as_warn (_("Improper shift amount (%lu)"), |
9380 | (unsigned long) imm_expr.X_add_number); | |
9381 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9382 | imm_expr.X_op = O_absent; |
9383 | s = expr_end; | |
9384 | continue; | |
9385 | ||
9386 | case '>': /* shift amount minus 32 */ | |
9387 | my_getExpression (&imm_expr, s); | |
9388 | check_absolute_expr (ip, &imm_expr); | |
9389 | if ((unsigned long) imm_expr.X_add_number < 32 | |
9390 | || (unsigned long) imm_expr.X_add_number > 63) | |
9391 | break; | |
bf12938e | 9392 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
9393 | imm_expr.X_op = O_absent; |
9394 | s = expr_end; | |
9395 | continue; | |
9396 | ||
252b5132 RH |
9397 | case 'k': /* cache code */ |
9398 | case 'h': /* prefx code */ | |
620edafd | 9399 | case '1': /* sync type */ |
252b5132 RH |
9400 | my_getExpression (&imm_expr, s); |
9401 | check_absolute_expr (ip, &imm_expr); | |
9402 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
9403 | as_warn (_("Invalid value for `%s' (%lu)"), |
9404 | ip->insn_mo->name, | |
9405 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 9406 | if (*args == 'k') |
d954098f DD |
9407 | { |
9408 | if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0) | |
9409 | switch (imm_expr.X_add_number) | |
9410 | { | |
9411 | case 5: | |
9412 | case 25: | |
9413 | case 26: | |
9414 | case 27: | |
9415 | case 28: | |
9416 | case 29: | |
9417 | case 30: | |
9418 | case 31: /* These are ok. */ | |
9419 | break; | |
9420 | ||
9421 | default: /* The rest must be changed to 28. */ | |
9422 | imm_expr.X_add_number = 28; | |
9423 | break; | |
9424 | } | |
9425 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); | |
9426 | } | |
620edafd | 9427 | else if (*args == 'h') |
bf12938e | 9428 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
620edafd CF |
9429 | else |
9430 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9431 | imm_expr.X_op = O_absent; |
9432 | s = expr_end; | |
9433 | continue; | |
9434 | ||
9435 | case 'c': /* break code */ | |
9436 | my_getExpression (&imm_expr, s); | |
9437 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9438 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
9439 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
9440 | ip->insn_mo->name, | |
bf12938e RS |
9441 | (unsigned long) imm_expr.X_add_number); |
9442 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9443 | imm_expr.X_op = O_absent; |
9444 | s = expr_end; | |
9445 | continue; | |
9446 | ||
9447 | case 'q': /* lower break code */ | |
9448 | my_getExpression (&imm_expr, s); | |
9449 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
9450 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9451 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9452 | ip->insn_mo->name, | |
bf12938e RS |
9453 | (unsigned long) imm_expr.X_add_number); |
9454 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9455 | imm_expr.X_op = O_absent; |
9456 | s = expr_end; | |
9457 | continue; | |
9458 | ||
4372b673 | 9459 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 9460 | my_getExpression (&imm_expr, s); |
156c2f8b | 9461 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9462 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9463 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9464 | ip->insn_mo->name, | |
793b27f4 | 9465 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9466 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9467 | imm_expr.X_op = O_absent; |
9468 | s = expr_end; | |
9469 | continue; | |
9470 | ||
98d3f06f | 9471 | case 'C': /* Coprocessor code */ |
beae10d5 | 9472 | my_getExpression (&imm_expr, s); |
252b5132 | 9473 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9474 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9475 | { |
793b27f4 TS |
9476 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9477 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9478 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9479 | } |
a9e24354 | 9480 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9481 | imm_expr.X_op = O_absent; |
9482 | s = expr_end; | |
9483 | continue; | |
252b5132 | 9484 | |
4372b673 NC |
9485 | case 'J': /* 19-bit wait code. */ |
9486 | my_getExpression (&imm_expr, s); | |
9487 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9488 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9489 | { |
9490 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9491 | (unsigned long) imm_expr.X_add_number); | |
9492 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9493 | } | |
bf12938e | 9494 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9495 | imm_expr.X_op = O_absent; |
9496 | s = expr_end; | |
9497 | continue; | |
9498 | ||
707bfff6 | 9499 | case 'P': /* Performance register. */ |
beae10d5 | 9500 | my_getExpression (&imm_expr, s); |
252b5132 | 9501 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9502 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9503 | as_warn (_("Invalid performance register (%lu)"), |
9504 | (unsigned long) imm_expr.X_add_number); | |
9505 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9506 | imm_expr.X_op = O_absent; |
9507 | s = expr_end; | |
9508 | continue; | |
252b5132 | 9509 | |
707bfff6 TS |
9510 | case 'G': /* Coprocessor destination register. */ |
9511 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9512 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9513 | else | |
9514 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9515 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9516 | if (ok) |
9517 | { | |
9518 | lastregno = regno; | |
9519 | continue; | |
9520 | } | |
9521 | else | |
9522 | break; | |
9523 | ||
252b5132 RH |
9524 | case 'b': /* base register */ |
9525 | case 'd': /* destination register */ | |
9526 | case 's': /* source register */ | |
9527 | case 't': /* target register */ | |
9528 | case 'r': /* both target and source */ | |
9529 | case 'v': /* both dest and source */ | |
9530 | case 'w': /* both dest and target */ | |
9531 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9532 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9533 | case 'x': /* ignore register name */ |
9534 | case 'z': /* must be zero register */ | |
4372b673 | 9535 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9536 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9537 | s_reset = s; |
9538 | if (*args == 'E' || *args == 'K') | |
9539 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9540 | else | |
9541 | { | |
9542 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
9543 | if (regno == AT && mips_opts.at) |
9544 | { | |
9545 | if (mips_opts.at == ATREG) | |
9546 | as_warn (_("used $at without \".set noat\"")); | |
9547 | else | |
9548 | as_warn (_("used $%u with \".set at=$%u\""), | |
9549 | regno, mips_opts.at); | |
9550 | } | |
707bfff6 TS |
9551 | } |
9552 | if (ok) | |
252b5132 | 9553 | { |
252b5132 RH |
9554 | c = *args; |
9555 | if (*s == ' ') | |
f9419b05 | 9556 | ++s; |
252b5132 RH |
9557 | if (args[1] != *s) |
9558 | { | |
9559 | if (c == 'r' || c == 'v' || c == 'w') | |
9560 | { | |
9561 | regno = lastregno; | |
9562 | s = s_reset; | |
f9419b05 | 9563 | ++args; |
252b5132 RH |
9564 | } |
9565 | } | |
9566 | /* 'z' only matches $0. */ | |
9567 | if (c == 'z' && regno != 0) | |
9568 | break; | |
9569 | ||
24864476 | 9570 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
9571 | { |
9572 | if (regno == lastregno) | |
9573 | { | |
24864476 | 9574 | insn_error = _("source and destination must be different"); |
e7c604dd CM |
9575 | continue; |
9576 | } | |
24864476 | 9577 | if (regno == 31 && lastregno == 0xffffffff) |
e7c604dd CM |
9578 | { |
9579 | insn_error = _("a destination register must be supplied"); | |
9580 | continue; | |
9581 | } | |
9582 | } | |
bdaaa2e1 KH |
9583 | /* Now that we have assembled one operand, we use the args string |
9584 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9585 | switch (c) |
9586 | { | |
9587 | case 'r': | |
9588 | case 's': | |
9589 | case 'v': | |
9590 | case 'b': | |
bf12938e | 9591 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9592 | break; |
9593 | case 'd': | |
9594 | case 'G': | |
af7ee8bf | 9595 | case 'K': |
ef2e4d86 | 9596 | case 'g': |
bf12938e | 9597 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9598 | break; |
4372b673 | 9599 | case 'U': |
bf12938e RS |
9600 | INSERT_OPERAND (RD, *ip, regno); |
9601 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9602 | break; |
252b5132 RH |
9603 | case 'w': |
9604 | case 't': | |
9605 | case 'E': | |
bf12938e | 9606 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9607 | break; |
9608 | case 'x': | |
9609 | /* This case exists because on the r3000 trunc | |
9610 | expands into a macro which requires a gp | |
9611 | register. On the r6000 or r4000 it is | |
9612 | assembled into a single instruction which | |
9613 | ignores the register. Thus the insn version | |
9614 | is MIPS_ISA2 and uses 'x', and the macro | |
9615 | version is MIPS_ISA1 and uses 't'. */ | |
9616 | break; | |
9617 | case 'z': | |
9618 | /* This case is for the div instruction, which | |
9619 | acts differently if the destination argument | |
9620 | is $0. This only matches $0, and is checked | |
9621 | outside the switch. */ | |
9622 | break; | |
9623 | case 'D': | |
9624 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9625 | break; | |
9626 | /* What about all other operands like 'i', which | |
9627 | can be specified in the opcode table? */ | |
9628 | } | |
9629 | lastregno = regno; | |
9630 | continue; | |
9631 | } | |
252b5132 RH |
9632 | switch (*args++) |
9633 | { | |
9634 | case 'r': | |
9635 | case 'v': | |
bf12938e | 9636 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9637 | continue; |
9638 | case 'w': | |
bf12938e | 9639 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9640 | continue; |
9641 | } | |
9642 | break; | |
9643 | ||
deec1734 CD |
9644 | case 'O': /* MDMX alignment immediate constant. */ |
9645 | my_getExpression (&imm_expr, s); | |
9646 | check_absolute_expr (ip, &imm_expr); | |
9647 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 9648 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e RS |
9649 | (long) imm_expr.X_add_number); |
9650 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9651 | imm_expr.X_op = O_absent; |
9652 | s = expr_end; | |
9653 | continue; | |
9654 | ||
9655 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9656 | if (s[0] != '$') | |
9657 | { | |
9658 | /* MDMX Immediate. */ | |
9659 | my_getExpression (&imm_expr, s); | |
9660 | check_absolute_expr (ip, &imm_expr); | |
9661 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9662 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9663 | (long) imm_expr.X_add_number); | |
9664 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9665 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9666 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9667 | else | |
9668 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9669 | imm_expr.X_op = O_absent; |
9670 | s = expr_end; | |
9671 | continue; | |
9672 | } | |
9673 | /* Not MDMX Immediate. Fall through. */ | |
9674 | case 'X': /* MDMX destination register. */ | |
9675 | case 'Y': /* MDMX source register. */ | |
9676 | case 'Z': /* MDMX target register. */ | |
9677 | is_mdmx = 1; | |
252b5132 RH |
9678 | case 'D': /* floating point destination register */ |
9679 | case 'S': /* floating point source register */ | |
9680 | case 'T': /* floating point target register */ | |
9681 | case 'R': /* floating point source register */ | |
9682 | case 'V': | |
9683 | case 'W': | |
707bfff6 TS |
9684 | rtype = RTYPE_FPU; |
9685 | if (is_mdmx | |
9686 | || (mips_opts.ase_mdmx | |
9687 | && (ip->insn_mo->pinfo & FP_D) | |
9688 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9689 | | INSN_COPROC_MEMORY_DELAY | |
9690 | | INSN_LOAD_COPROC_DELAY | |
9691 | | INSN_LOAD_MEMORY_DELAY | |
9692 | | INSN_STORE_MEMORY)))) | |
9693 | rtype |= RTYPE_VEC; | |
252b5132 | 9694 | s_reset = s; |
707bfff6 | 9695 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9696 | { |
252b5132 | 9697 | if ((regno & 1) != 0 |
ca4e0257 | 9698 | && HAVE_32BIT_FPRS |
7455baf8 | 9699 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9700 | as_warn (_("Float register should be even, was %d"), |
9701 | regno); | |
9702 | ||
9703 | c = *args; | |
9704 | if (*s == ' ') | |
f9419b05 | 9705 | ++s; |
252b5132 RH |
9706 | if (args[1] != *s) |
9707 | { | |
9708 | if (c == 'V' || c == 'W') | |
9709 | { | |
9710 | regno = lastregno; | |
9711 | s = s_reset; | |
f9419b05 | 9712 | ++args; |
252b5132 RH |
9713 | } |
9714 | } | |
9715 | switch (c) | |
9716 | { | |
9717 | case 'D': | |
deec1734 | 9718 | case 'X': |
bf12938e | 9719 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9720 | break; |
9721 | case 'V': | |
9722 | case 'S': | |
deec1734 | 9723 | case 'Y': |
bf12938e | 9724 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9725 | break; |
deec1734 CD |
9726 | case 'Q': |
9727 | /* This is like 'Z', but also needs to fix the MDMX | |
9728 | vector/scalar select bits. Note that the | |
9729 | scalar immediate case is handled above. */ | |
9730 | if (*s == '[') | |
9731 | { | |
9732 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9733 | int max_el = (is_qh ? 3 : 7); | |
9734 | s++; | |
9735 | my_getExpression(&imm_expr, s); | |
9736 | check_absolute_expr (ip, &imm_expr); | |
9737 | s = expr_end; | |
9738 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
9739 | as_bad (_("Bad element selector %ld"), |
9740 | (long) imm_expr.X_add_number); | |
deec1734 CD |
9741 | imm_expr.X_add_number &= max_el; |
9742 | ip->insn_opcode |= (imm_expr.X_add_number | |
9743 | << (OP_SH_VSEL + | |
9744 | (is_qh ? 2 : 1))); | |
01a3f561 | 9745 | imm_expr.X_op = O_absent; |
deec1734 | 9746 | if (*s != ']') |
20203fb9 | 9747 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
9748 | else |
9749 | s++; | |
9750 | } | |
9751 | else | |
9752 | { | |
9753 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9754 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9755 | << OP_SH_VSEL); | |
9756 | else | |
9757 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9758 | OP_SH_VSEL); | |
9759 | } | |
9760 | /* Fall through */ | |
252b5132 RH |
9761 | case 'W': |
9762 | case 'T': | |
deec1734 | 9763 | case 'Z': |
bf12938e | 9764 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9765 | break; |
9766 | case 'R': | |
bf12938e | 9767 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9768 | break; |
9769 | } | |
9770 | lastregno = regno; | |
9771 | continue; | |
9772 | } | |
9773 | ||
252b5132 RH |
9774 | switch (*args++) |
9775 | { | |
9776 | case 'V': | |
bf12938e | 9777 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9778 | continue; |
9779 | case 'W': | |
bf12938e | 9780 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9781 | continue; |
9782 | } | |
9783 | break; | |
9784 | ||
9785 | case 'I': | |
9786 | my_getExpression (&imm_expr, s); | |
9787 | if (imm_expr.X_op != O_big | |
9788 | && imm_expr.X_op != O_constant) | |
9789 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9790 | if (HAVE_32BIT_GPRS) |
9791 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9792 | s = expr_end; |
9793 | continue; | |
9794 | ||
9795 | case 'A': | |
9796 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9797 | normalize_address_expr (&offset_expr); |
f6688943 | 9798 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9799 | s = expr_end; |
9800 | continue; | |
9801 | ||
9802 | case 'F': | |
9803 | case 'L': | |
9804 | case 'f': | |
9805 | case 'l': | |
9806 | { | |
9807 | int f64; | |
ca4e0257 | 9808 | int using_gprs; |
252b5132 RH |
9809 | char *save_in; |
9810 | char *err; | |
9811 | unsigned char temp[8]; | |
9812 | int len; | |
9813 | unsigned int length; | |
9814 | segT seg; | |
9815 | subsegT subseg; | |
9816 | char *p; | |
9817 | ||
9818 | /* These only appear as the last operand in an | |
9819 | instruction, and every instruction that accepts | |
9820 | them in any variant accepts them in all variants. | |
9821 | This means we don't have to worry about backing out | |
9822 | any changes if the instruction does not match. | |
9823 | ||
9824 | The difference between them is the size of the | |
9825 | floating point constant and where it goes. For 'F' | |
9826 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9827 | is 32 bits. Where the constant is placed is based | |
9828 | on how the MIPS assembler does things: | |
9829 | F -- .rdata | |
9830 | L -- .lit8 | |
9831 | f -- immediate value | |
9832 | l -- .lit4 | |
9833 | ||
9834 | The .lit4 and .lit8 sections are only used if | |
9835 | permitted by the -G argument. | |
9836 | ||
ca4e0257 RS |
9837 | The code below needs to know whether the target register |
9838 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9839 | 'F' are used with GPR-based instructions and 'l' and | |
9840 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9841 | |
9842 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9843 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9844 | |
9845 | save_in = input_line_pointer; | |
9846 | input_line_pointer = s; | |
9847 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9848 | length = len; | |
9849 | s = input_line_pointer; | |
9850 | input_line_pointer = save_in; | |
9851 | if (err != NULL && *err != '\0') | |
9852 | { | |
9853 | as_bad (_("Bad floating point constant: %s"), err); | |
9854 | memset (temp, '\0', sizeof temp); | |
9855 | length = f64 ? 8 : 4; | |
9856 | } | |
9857 | ||
9c2799c2 | 9858 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9859 | |
9860 | if (*args == 'f' | |
9861 | || (*args == 'l' | |
3e722fb5 | 9862 | && (g_switch_value < 4 |
252b5132 RH |
9863 | || (temp[0] == 0 && temp[1] == 0) |
9864 | || (temp[2] == 0 && temp[3] == 0)))) | |
9865 | { | |
9866 | imm_expr.X_op = O_constant; | |
9867 | if (! target_big_endian) | |
9868 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9869 | else | |
9870 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9871 | } | |
9872 | else if (length > 4 | |
119d663a | 9873 | && ! mips_disable_float_construction |
ca4e0257 RS |
9874 | /* Constants can only be constructed in GPRs and |
9875 | copied to FPRs if the GPRs are at least as wide | |
9876 | as the FPRs. Force the constant into memory if | |
9877 | we are using 64-bit FPRs but the GPRs are only | |
9878 | 32 bits wide. */ | |
9879 | && (using_gprs | |
9880 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9881 | && ((temp[0] == 0 && temp[1] == 0) |
9882 | || (temp[2] == 0 && temp[3] == 0)) | |
9883 | && ((temp[4] == 0 && temp[5] == 0) | |
9884 | || (temp[6] == 0 && temp[7] == 0))) | |
9885 | { | |
ca4e0257 RS |
9886 | /* The value is simple enough to load with a couple of |
9887 | instructions. If using 32-bit registers, set | |
9888 | imm_expr to the high order 32 bits and offset_expr to | |
9889 | the low order 32 bits. Otherwise, set imm_expr to | |
9890 | the entire 64 bit constant. */ | |
9891 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9892 | { |
9893 | imm_expr.X_op = O_constant; | |
9894 | offset_expr.X_op = O_constant; | |
9895 | if (! target_big_endian) | |
9896 | { | |
9897 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9898 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9899 | } | |
9900 | else | |
9901 | { | |
9902 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9903 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9904 | } | |
9905 | if (offset_expr.X_add_number == 0) | |
9906 | offset_expr.X_op = O_absent; | |
9907 | } | |
9908 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9909 | { | |
9910 | imm_expr.X_op = O_constant; | |
9911 | if (! target_big_endian) | |
9912 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9913 | else | |
9914 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9915 | } | |
9916 | else | |
9917 | { | |
9918 | imm_expr.X_op = O_big; | |
9919 | imm_expr.X_add_number = 4; | |
9920 | if (! target_big_endian) | |
9921 | { | |
9922 | generic_bignum[0] = bfd_getl16 (temp); | |
9923 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9924 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9925 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9926 | } | |
9927 | else | |
9928 | { | |
9929 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9930 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9931 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9932 | generic_bignum[3] = bfd_getb16 (temp); | |
9933 | } | |
9934 | } | |
9935 | } | |
9936 | else | |
9937 | { | |
9938 | const char *newname; | |
9939 | segT new_seg; | |
9940 | ||
9941 | /* Switch to the right section. */ | |
9942 | seg = now_seg; | |
9943 | subseg = now_subseg; | |
9944 | switch (*args) | |
9945 | { | |
9946 | default: /* unused default case avoids warnings. */ | |
9947 | case 'L': | |
9948 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9949 | if (g_switch_value >= 8) |
252b5132 RH |
9950 | newname = ".lit8"; |
9951 | break; | |
9952 | case 'F': | |
3e722fb5 | 9953 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9954 | break; |
9955 | case 'l': | |
9c2799c2 | 9956 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
9957 | newname = ".lit4"; |
9958 | break; | |
9959 | } | |
9960 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9961 | if (IS_ELF) |
252b5132 RH |
9962 | bfd_set_section_flags (stdoutput, new_seg, |
9963 | (SEC_ALLOC | |
9964 | | SEC_LOAD | |
9965 | | SEC_READONLY | |
9966 | | SEC_DATA)); | |
9967 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 9968 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
9969 | record_alignment (new_seg, 4); |
9970 | else | |
9971 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9972 | if (seg == now_seg) | |
9973 | as_bad (_("Can't use floating point insn in this section")); | |
9974 | ||
9975 | /* Set the argument to the current address in the | |
9976 | section. */ | |
9977 | offset_expr.X_op = O_symbol; | |
8680f6e1 | 9978 | offset_expr.X_add_symbol = symbol_temp_new_now (); |
252b5132 RH |
9979 | offset_expr.X_add_number = 0; |
9980 | ||
9981 | /* Put the floating point number into the section. */ | |
9982 | p = frag_more ((int) length); | |
9983 | memcpy (p, temp, length); | |
9984 | ||
9985 | /* Switch back to the original section. */ | |
9986 | subseg_set (seg, subseg); | |
9987 | } | |
9988 | } | |
9989 | continue; | |
9990 | ||
9991 | case 'i': /* 16 bit unsigned immediate */ | |
9992 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9993 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9994 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9995 | { |
9996 | int more; | |
5e0116d5 RS |
9997 | offsetT minval, maxval; |
9998 | ||
9999 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
10000 | && strcmp (insn->name, insn[1].name) == 0); | |
10001 | ||
10002 | /* If the expression was written as an unsigned number, | |
10003 | only treat it as signed if there are no more | |
10004 | alternatives. */ | |
10005 | if (more | |
10006 | && *args == 'j' | |
10007 | && sizeof (imm_expr.X_add_number) <= 4 | |
10008 | && imm_expr.X_op == O_constant | |
10009 | && imm_expr.X_add_number < 0 | |
10010 | && imm_expr.X_unsigned | |
10011 | && HAVE_64BIT_GPRS) | |
10012 | break; | |
10013 | ||
10014 | /* For compatibility with older assemblers, we accept | |
10015 | 0x8000-0xffff as signed 16-bit numbers when only | |
10016 | signed numbers are allowed. */ | |
10017 | if (*args == 'i') | |
10018 | minval = 0, maxval = 0xffff; | |
10019 | else if (more) | |
10020 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 10021 | else |
5e0116d5 RS |
10022 | minval = -0x8000, maxval = 0xffff; |
10023 | ||
10024 | if (imm_expr.X_op != O_constant | |
10025 | || imm_expr.X_add_number < minval | |
10026 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
10027 | { |
10028 | if (more) | |
10029 | break; | |
2ae7e77b AH |
10030 | if (imm_expr.X_op == O_constant |
10031 | || imm_expr.X_op == O_big) | |
5e0116d5 | 10032 | as_bad (_("expression out of range")); |
252b5132 RH |
10033 | } |
10034 | } | |
10035 | s = expr_end; | |
10036 | continue; | |
10037 | ||
10038 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
10039 | /* Check whether there is only a single bracketed expression |
10040 | left. If so, it must be the base register and the | |
10041 | constant must be zero. */ | |
10042 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
10043 | { | |
10044 | offset_expr.X_op = O_constant; | |
10045 | offset_expr.X_add_number = 0; | |
10046 | continue; | |
10047 | } | |
252b5132 RH |
10048 | |
10049 | /* If this value won't fit into a 16 bit offset, then go | |
10050 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 10051 | code pattern. */ |
5e0116d5 | 10052 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
10053 | && (offset_expr.X_op != O_constant |
10054 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 10055 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
10056 | break; |
10057 | ||
252b5132 RH |
10058 | s = expr_end; |
10059 | continue; | |
10060 | ||
10061 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 10062 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
10063 | my_getExpression (&offset_expr, s); |
10064 | s = expr_end; | |
10065 | continue; | |
10066 | ||
10067 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
10068 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
10069 | && imm_expr.X_op == O_constant | |
10070 | && (imm_expr.X_add_number < 0 | |
10071 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
10072 | as_bad (_("lui expression not in range 0..65535")); |
10073 | s = expr_end; | |
10074 | continue; | |
10075 | ||
10076 | case 'a': /* 26 bit address */ | |
10077 | my_getExpression (&offset_expr, s); | |
10078 | s = expr_end; | |
f6688943 | 10079 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
10080 | continue; |
10081 | ||
10082 | case 'N': /* 3 bit branch condition code */ | |
10083 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
10084 | rtype = RTYPE_CCC; |
10085 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
10086 | rtype |= RTYPE_FCC; | |
10087 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 10088 | break; |
30c378fd CD |
10089 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
10090 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
10091 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
10092 | && (regno & 1) != 0) | |
20203fb9 NC |
10093 | as_warn (_("Condition code register should be even for %s, was %d"), |
10094 | str, regno); | |
30c378fd CD |
10095 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 |
10096 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
10097 | && (regno & 3) != 0) | |
20203fb9 NC |
10098 | as_warn (_("Condition code register should be 0 or 4 for %s, was %d"), |
10099 | str, regno); | |
252b5132 | 10100 | if (*args == 'N') |
bf12938e | 10101 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 10102 | else |
bf12938e | 10103 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 10104 | continue; |
252b5132 | 10105 | |
156c2f8b NC |
10106 | case 'H': |
10107 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
10108 | s += 2; | |
3882b010 | 10109 | if (ISDIGIT (*s)) |
156c2f8b NC |
10110 | { |
10111 | c = 0; | |
10112 | do | |
10113 | { | |
10114 | c *= 10; | |
10115 | c += *s - '0'; | |
10116 | ++s; | |
10117 | } | |
3882b010 | 10118 | while (ISDIGIT (*s)); |
156c2f8b NC |
10119 | } |
10120 | else | |
10121 | c = 8; /* Invalid sel value. */ | |
10122 | ||
10123 | if (c > 7) | |
10124 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
10125 | ip->insn_opcode |= c; | |
10126 | continue; | |
10127 | ||
60b63b72 RS |
10128 | case 'e': |
10129 | /* Must be at least one digit. */ | |
10130 | my_getExpression (&imm_expr, s); | |
10131 | check_absolute_expr (ip, &imm_expr); | |
10132 | ||
10133 | if ((unsigned long) imm_expr.X_add_number | |
10134 | > (unsigned long) OP_MASK_VECBYTE) | |
10135 | { | |
10136 | as_bad (_("bad byte vector index (%ld)"), | |
10137 | (long) imm_expr.X_add_number); | |
10138 | imm_expr.X_add_number = 0; | |
10139 | } | |
10140 | ||
bf12938e | 10141 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10142 | imm_expr.X_op = O_absent; |
10143 | s = expr_end; | |
10144 | continue; | |
10145 | ||
10146 | case '%': | |
10147 | my_getExpression (&imm_expr, s); | |
10148 | check_absolute_expr (ip, &imm_expr); | |
10149 | ||
10150 | if ((unsigned long) imm_expr.X_add_number | |
10151 | > (unsigned long) OP_MASK_VECALIGN) | |
10152 | { | |
10153 | as_bad (_("bad byte vector index (%ld)"), | |
10154 | (long) imm_expr.X_add_number); | |
10155 | imm_expr.X_add_number = 0; | |
10156 | } | |
10157 | ||
bf12938e | 10158 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
10159 | imm_expr.X_op = O_absent; |
10160 | s = expr_end; | |
10161 | continue; | |
10162 | ||
252b5132 RH |
10163 | default: |
10164 | as_bad (_("bad char = '%c'\n"), *args); | |
10165 | internalError (); | |
10166 | } | |
10167 | break; | |
10168 | } | |
10169 | /* Args don't match. */ | |
10170 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
10171 | !strcmp (insn->name, insn[1].name)) | |
10172 | { | |
10173 | ++insn; | |
10174 | s = argsStart; | |
268f6bed | 10175 | insn_error = _("illegal operands"); |
252b5132 RH |
10176 | continue; |
10177 | } | |
268f6bed | 10178 | if (save_c) |
570de991 | 10179 | *(--argsStart) = save_c; |
252b5132 RH |
10180 | insn_error = _("illegal operands"); |
10181 | return; | |
10182 | } | |
10183 | } | |
10184 | ||
0499d65b TS |
10185 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
10186 | ||
252b5132 RH |
10187 | /* This routine assembles an instruction into its binary format when |
10188 | assembling for the mips16. As a side effect, it sets one of the | |
10189 | global variables imm_reloc or offset_reloc to the type of | |
10190 | relocation to do if one of the operands is an address expression. | |
10191 | It also sets mips16_small and mips16_ext if the user explicitly | |
10192 | requested a small or extended instruction. */ | |
10193 | ||
10194 | static void | |
17a2f251 | 10195 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
10196 | { |
10197 | char *s; | |
10198 | const char *args; | |
10199 | struct mips_opcode *insn; | |
10200 | char *argsstart; | |
10201 | unsigned int regno; | |
10202 | unsigned int lastregno = 0; | |
10203 | char *s_reset; | |
d6f16593 | 10204 | size_t i; |
252b5132 RH |
10205 | |
10206 | insn_error = NULL; | |
10207 | ||
b34976b6 AM |
10208 | mips16_small = FALSE; |
10209 | mips16_ext = FALSE; | |
252b5132 | 10210 | |
3882b010 | 10211 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
10212 | ; |
10213 | switch (*s) | |
10214 | { | |
10215 | case '\0': | |
10216 | break; | |
10217 | ||
10218 | case ' ': | |
10219 | *s++ = '\0'; | |
10220 | break; | |
10221 | ||
10222 | case '.': | |
10223 | if (s[1] == 't' && s[2] == ' ') | |
10224 | { | |
10225 | *s = '\0'; | |
b34976b6 | 10226 | mips16_small = TRUE; |
252b5132 RH |
10227 | s += 3; |
10228 | break; | |
10229 | } | |
10230 | else if (s[1] == 'e' && s[2] == ' ') | |
10231 | { | |
10232 | *s = '\0'; | |
b34976b6 | 10233 | mips16_ext = TRUE; |
252b5132 RH |
10234 | s += 3; |
10235 | break; | |
10236 | } | |
10237 | /* Fall through. */ | |
10238 | default: | |
10239 | insn_error = _("unknown opcode"); | |
10240 | return; | |
10241 | } | |
10242 | ||
10243 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 10244 | mips16_small = TRUE; |
252b5132 RH |
10245 | |
10246 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
10247 | { | |
10248 | insn_error = _("unrecognized opcode"); | |
10249 | return; | |
10250 | } | |
10251 | ||
10252 | argsstart = s; | |
10253 | for (;;) | |
10254 | { | |
9b3f89ee TS |
10255 | bfd_boolean ok; |
10256 | ||
9c2799c2 | 10257 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 10258 | |
037b32b9 | 10259 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
10260 | if (! ok) |
10261 | { | |
10262 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
10263 | && strcmp (insn->name, insn[1].name) == 0) | |
10264 | { | |
10265 | ++insn; | |
10266 | continue; | |
10267 | } | |
10268 | else | |
10269 | { | |
10270 | if (!insn_error) | |
10271 | { | |
10272 | static char buf[100]; | |
10273 | sprintf (buf, | |
10274 | _("opcode not supported on this processor: %s (%s)"), | |
10275 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10276 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10277 | insn_error = buf; | |
10278 | } | |
10279 | return; | |
10280 | } | |
10281 | } | |
10282 | ||
1e915849 | 10283 | create_insn (ip, insn); |
252b5132 | 10284 | imm_expr.X_op = O_absent; |
f6688943 TS |
10285 | imm_reloc[0] = BFD_RELOC_UNUSED; |
10286 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
10287 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 10288 | imm2_expr.X_op = O_absent; |
252b5132 | 10289 | offset_expr.X_op = O_absent; |
f6688943 TS |
10290 | offset_reloc[0] = BFD_RELOC_UNUSED; |
10291 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10292 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
10293 | for (args = insn->args; 1; ++args) |
10294 | { | |
10295 | int c; | |
10296 | ||
10297 | if (*s == ' ') | |
10298 | ++s; | |
10299 | ||
10300 | /* In this switch statement we call break if we did not find | |
10301 | a match, continue if we did find a match, or return if we | |
10302 | are done. */ | |
10303 | ||
10304 | c = *args; | |
10305 | switch (c) | |
10306 | { | |
10307 | case '\0': | |
10308 | if (*s == '\0') | |
10309 | { | |
10310 | /* Stuff the immediate value in now, if we can. */ | |
10311 | if (imm_expr.X_op == O_constant | |
f6688943 | 10312 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
10313 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
10314 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
10315 | && insn->pinfo != INSN_MACRO) |
10316 | { | |
d6f16593 MR |
10317 | valueT tmp; |
10318 | ||
10319 | switch (*offset_reloc) | |
10320 | { | |
10321 | case BFD_RELOC_MIPS16_HI16_S: | |
10322 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
10323 | break; | |
10324 | ||
10325 | case BFD_RELOC_MIPS16_HI16: | |
10326 | tmp = imm_expr.X_add_number >> 16; | |
10327 | break; | |
10328 | ||
10329 | case BFD_RELOC_MIPS16_LO16: | |
10330 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
10331 | - 0x8000; | |
10332 | break; | |
10333 | ||
10334 | case BFD_RELOC_UNUSED: | |
10335 | tmp = imm_expr.X_add_number; | |
10336 | break; | |
10337 | ||
10338 | default: | |
10339 | internalError (); | |
10340 | } | |
10341 | *offset_reloc = BFD_RELOC_UNUSED; | |
10342 | ||
c4e7957c | 10343 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 10344 | tmp, TRUE, mips16_small, |
252b5132 RH |
10345 | mips16_ext, &ip->insn_opcode, |
10346 | &ip->use_extend, &ip->extend); | |
10347 | imm_expr.X_op = O_absent; | |
f6688943 | 10348 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
10349 | } |
10350 | ||
10351 | return; | |
10352 | } | |
10353 | break; | |
10354 | ||
10355 | case ',': | |
10356 | if (*s++ == c) | |
10357 | continue; | |
10358 | s--; | |
10359 | switch (*++args) | |
10360 | { | |
10361 | case 'v': | |
bf12938e | 10362 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
10363 | continue; |
10364 | case 'w': | |
bf12938e | 10365 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10366 | continue; |
10367 | } | |
10368 | break; | |
10369 | ||
10370 | case '(': | |
10371 | case ')': | |
10372 | if (*s++ == c) | |
10373 | continue; | |
10374 | break; | |
10375 | ||
10376 | case 'v': | |
10377 | case 'w': | |
10378 | if (s[0] != '$') | |
10379 | { | |
10380 | if (c == 'v') | |
bf12938e | 10381 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 10382 | else |
bf12938e | 10383 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
10384 | ++args; |
10385 | continue; | |
10386 | } | |
10387 | /* Fall through. */ | |
10388 | case 'x': | |
10389 | case 'y': | |
10390 | case 'z': | |
10391 | case 'Z': | |
10392 | case '0': | |
10393 | case 'S': | |
10394 | case 'R': | |
10395 | case 'X': | |
10396 | case 'Y': | |
707bfff6 TS |
10397 | s_reset = s; |
10398 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 10399 | { |
707bfff6 | 10400 | if (c == 'v' || c == 'w') |
85b51719 | 10401 | { |
707bfff6 | 10402 | if (c == 'v') |
a9e24354 | 10403 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 10404 | else |
a9e24354 | 10405 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
10406 | ++args; |
10407 | continue; | |
85b51719 | 10408 | } |
707bfff6 | 10409 | break; |
252b5132 RH |
10410 | } |
10411 | ||
10412 | if (*s == ' ') | |
10413 | ++s; | |
10414 | if (args[1] != *s) | |
10415 | { | |
10416 | if (c == 'v' || c == 'w') | |
10417 | { | |
10418 | regno = mips16_to_32_reg_map[lastregno]; | |
10419 | s = s_reset; | |
f9419b05 | 10420 | ++args; |
252b5132 RH |
10421 | } |
10422 | } | |
10423 | ||
10424 | switch (c) | |
10425 | { | |
10426 | case 'x': | |
10427 | case 'y': | |
10428 | case 'z': | |
10429 | case 'v': | |
10430 | case 'w': | |
10431 | case 'Z': | |
10432 | regno = mips32_to_16_reg_map[regno]; | |
10433 | break; | |
10434 | ||
10435 | case '0': | |
10436 | if (regno != 0) | |
10437 | regno = ILLEGAL_REG; | |
10438 | break; | |
10439 | ||
10440 | case 'S': | |
10441 | if (regno != SP) | |
10442 | regno = ILLEGAL_REG; | |
10443 | break; | |
10444 | ||
10445 | case 'R': | |
10446 | if (regno != RA) | |
10447 | regno = ILLEGAL_REG; | |
10448 | break; | |
10449 | ||
10450 | case 'X': | |
10451 | case 'Y': | |
741fe287 MR |
10452 | if (regno == AT && mips_opts.at) |
10453 | { | |
10454 | if (mips_opts.at == ATREG) | |
10455 | as_warn (_("used $at without \".set noat\"")); | |
10456 | else | |
10457 | as_warn (_("used $%u with \".set at=$%u\""), | |
10458 | regno, mips_opts.at); | |
10459 | } | |
252b5132 RH |
10460 | break; |
10461 | ||
10462 | default: | |
10463 | internalError (); | |
10464 | } | |
10465 | ||
10466 | if (regno == ILLEGAL_REG) | |
10467 | break; | |
10468 | ||
10469 | switch (c) | |
10470 | { | |
10471 | case 'x': | |
10472 | case 'v': | |
bf12938e | 10473 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10474 | break; |
10475 | case 'y': | |
10476 | case 'w': | |
bf12938e | 10477 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10478 | break; |
10479 | case 'z': | |
bf12938e | 10480 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10481 | break; |
10482 | case 'Z': | |
bf12938e | 10483 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10484 | case '0': |
10485 | case 'S': | |
10486 | case 'R': | |
10487 | break; | |
10488 | case 'X': | |
bf12938e | 10489 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10490 | break; |
10491 | case 'Y': | |
10492 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10493 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10494 | break; |
10495 | default: | |
10496 | internalError (); | |
10497 | } | |
10498 | ||
10499 | lastregno = regno; | |
10500 | continue; | |
10501 | ||
10502 | case 'P': | |
10503 | if (strncmp (s, "$pc", 3) == 0) | |
10504 | { | |
10505 | s += 3; | |
10506 | continue; | |
10507 | } | |
10508 | break; | |
10509 | ||
252b5132 RH |
10510 | case '5': |
10511 | case 'H': | |
10512 | case 'W': | |
10513 | case 'D': | |
10514 | case 'j': | |
252b5132 RH |
10515 | case 'V': |
10516 | case 'C': | |
10517 | case 'U': | |
10518 | case 'k': | |
10519 | case 'K': | |
d6f16593 MR |
10520 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10521 | if (i > 0) | |
252b5132 | 10522 | { |
d6f16593 | 10523 | if (imm_expr.X_op != O_constant) |
252b5132 | 10524 | { |
b34976b6 | 10525 | mips16_ext = TRUE; |
b34976b6 | 10526 | ip->use_extend = TRUE; |
252b5132 | 10527 | ip->extend = 0; |
252b5132 | 10528 | } |
d6f16593 MR |
10529 | else |
10530 | { | |
10531 | /* We need to relax this instruction. */ | |
10532 | *offset_reloc = *imm_reloc; | |
10533 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10534 | } | |
10535 | s = expr_end; | |
10536 | continue; | |
252b5132 | 10537 | } |
d6f16593 MR |
10538 | *imm_reloc = BFD_RELOC_UNUSED; |
10539 | /* Fall through. */ | |
10540 | case '<': | |
10541 | case '>': | |
10542 | case '[': | |
10543 | case ']': | |
10544 | case '4': | |
10545 | case '8': | |
10546 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10547 | if (imm_expr.X_op == O_register) |
10548 | { | |
10549 | /* What we thought was an expression turned out to | |
10550 | be a register. */ | |
10551 | ||
10552 | if (s[0] == '(' && args[1] == '(') | |
10553 | { | |
10554 | /* It looks like the expression was omitted | |
10555 | before a register indirection, which means | |
10556 | that the expression is implicitly zero. We | |
10557 | still set up imm_expr, so that we handle | |
10558 | explicit extensions correctly. */ | |
10559 | imm_expr.X_op = O_constant; | |
10560 | imm_expr.X_add_number = 0; | |
f6688943 | 10561 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10562 | continue; |
10563 | } | |
10564 | ||
10565 | break; | |
10566 | } | |
10567 | ||
10568 | /* We need to relax this instruction. */ | |
f6688943 | 10569 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10570 | s = expr_end; |
10571 | continue; | |
10572 | ||
10573 | case 'p': | |
10574 | case 'q': | |
10575 | case 'A': | |
10576 | case 'B': | |
10577 | case 'E': | |
10578 | /* We use offset_reloc rather than imm_reloc for the PC | |
10579 | relative operands. This lets macros with both | |
10580 | immediate and address operands work correctly. */ | |
10581 | my_getExpression (&offset_expr, s); | |
10582 | ||
10583 | if (offset_expr.X_op == O_register) | |
10584 | break; | |
10585 | ||
10586 | /* We need to relax this instruction. */ | |
f6688943 | 10587 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10588 | s = expr_end; |
10589 | continue; | |
10590 | ||
10591 | case '6': /* break code */ | |
10592 | my_getExpression (&imm_expr, s); | |
10593 | check_absolute_expr (ip, &imm_expr); | |
10594 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10595 | as_warn (_("Invalid value for `%s' (%lu)"), |
10596 | ip->insn_mo->name, | |
10597 | (unsigned long) imm_expr.X_add_number); | |
10598 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10599 | imm_expr.X_op = O_absent; |
10600 | s = expr_end; | |
10601 | continue; | |
10602 | ||
10603 | case 'a': /* 26 bit address */ | |
10604 | my_getExpression (&offset_expr, s); | |
10605 | s = expr_end; | |
f6688943 | 10606 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10607 | ip->insn_opcode <<= 16; |
10608 | continue; | |
10609 | ||
10610 | case 'l': /* register list for entry macro */ | |
10611 | case 'L': /* register list for exit macro */ | |
10612 | { | |
10613 | int mask; | |
10614 | ||
10615 | if (c == 'l') | |
10616 | mask = 0; | |
10617 | else | |
10618 | mask = 7 << 3; | |
10619 | while (*s != '\0') | |
10620 | { | |
707bfff6 | 10621 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10622 | |
10623 | while (*s == ' ' || *s == ',') | |
10624 | ++s; | |
707bfff6 | 10625 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10626 | freg = 0; |
707bfff6 TS |
10627 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10628 | freg = 1; | |
252b5132 RH |
10629 | else |
10630 | { | |
707bfff6 TS |
10631 | as_bad (_("can't parse register list")); |
10632 | break; | |
252b5132 RH |
10633 | } |
10634 | if (*s == ' ') | |
10635 | ++s; | |
10636 | if (*s != '-') | |
10637 | reg2 = reg1; | |
10638 | else | |
10639 | { | |
10640 | ++s; | |
707bfff6 TS |
10641 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10642 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10643 | { |
707bfff6 TS |
10644 | as_bad (_("invalid register list")); |
10645 | break; | |
252b5132 RH |
10646 | } |
10647 | } | |
10648 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10649 | { | |
10650 | mask &= ~ (7 << 3); | |
10651 | mask |= 5 << 3; | |
10652 | } | |
10653 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10654 | { | |
10655 | mask &= ~ (7 << 3); | |
10656 | mask |= 6 << 3; | |
10657 | } | |
10658 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10659 | mask |= (reg2 - 3) << 3; | |
10660 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10661 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10662 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10663 | mask |= 1; |
10664 | else | |
10665 | { | |
10666 | as_bad (_("invalid register list")); | |
10667 | break; | |
10668 | } | |
10669 | } | |
10670 | /* The mask is filled in in the opcode table for the | |
10671 | benefit of the disassembler. We remove it before | |
10672 | applying the actual mask. */ | |
10673 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10674 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10675 | } | |
10676 | continue; | |
10677 | ||
0499d65b TS |
10678 | case 'm': /* Register list for save insn. */ |
10679 | case 'M': /* Register list for restore insn. */ | |
10680 | { | |
10681 | int opcode = 0; | |
10682 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 10683 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
10684 | |
10685 | while (*s != '\0') | |
10686 | { | |
10687 | unsigned int reg1, reg2; | |
10688 | ||
10689 | SKIP_SPACE_TABS (s); | |
10690 | while (*s == ',') | |
10691 | ++s; | |
10692 | SKIP_SPACE_TABS (s); | |
10693 | ||
10694 | my_getExpression (&imm_expr, s); | |
10695 | if (imm_expr.X_op == O_constant) | |
10696 | { | |
10697 | /* Handle the frame size. */ | |
10698 | if (seen_framesz) | |
10699 | { | |
10700 | as_bad (_("more than one frame size in list")); | |
10701 | break; | |
10702 | } | |
10703 | seen_framesz = 1; | |
10704 | framesz = imm_expr.X_add_number; | |
10705 | imm_expr.X_op = O_absent; | |
10706 | s = expr_end; | |
10707 | continue; | |
10708 | } | |
10709 | ||
707bfff6 | 10710 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10711 | { |
10712 | as_bad (_("can't parse register list")); | |
10713 | break; | |
10714 | } | |
0499d65b | 10715 | |
707bfff6 TS |
10716 | while (*s == ' ') |
10717 | ++s; | |
10718 | ||
0499d65b TS |
10719 | if (*s != '-') |
10720 | reg2 = reg1; | |
10721 | else | |
10722 | { | |
10723 | ++s; | |
707bfff6 TS |
10724 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10725 | || reg2 < reg1) | |
0499d65b TS |
10726 | { |
10727 | as_bad (_("can't parse register list")); | |
10728 | break; | |
10729 | } | |
0499d65b TS |
10730 | } |
10731 | ||
10732 | while (reg1 <= reg2) | |
10733 | { | |
10734 | if (reg1 >= 4 && reg1 <= 7) | |
10735 | { | |
3a93f742 | 10736 | if (!seen_framesz) |
0499d65b | 10737 | /* args $a0-$a3 */ |
91d6fa6a | 10738 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
10739 | else |
10740 | /* statics $a0-$a3 */ | |
10741 | statics |= 1 << (reg1 - 4); | |
10742 | } | |
10743 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10744 | { | |
10745 | /* $s0-$s8 */ | |
10746 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10747 | } | |
10748 | else if (reg1 == 31) | |
10749 | { | |
10750 | /* Add $ra to insn. */ | |
10751 | opcode |= 0x40; | |
10752 | } | |
10753 | else | |
10754 | { | |
10755 | as_bad (_("unexpected register in list")); | |
10756 | break; | |
10757 | } | |
10758 | if (++reg1 == 24) | |
10759 | reg1 = 30; | |
10760 | } | |
10761 | } | |
10762 | ||
10763 | /* Encode args/statics combination. */ | |
91d6fa6a | 10764 | if (nargs & statics) |
0499d65b | 10765 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 10766 | else if (nargs == 0xf) |
0499d65b TS |
10767 | /* All $a0-$a3 are args. */ |
10768 | opcode |= MIPS16_ALL_ARGS << 16; | |
10769 | else if (statics == 0xf) | |
10770 | /* All $a0-$a3 are statics. */ | |
10771 | opcode |= MIPS16_ALL_STATICS << 16; | |
10772 | else | |
10773 | { | |
10774 | int narg = 0, nstat = 0; | |
10775 | ||
10776 | /* Count arg registers. */ | |
91d6fa6a | 10777 | while (nargs & 0x1) |
0499d65b | 10778 | { |
91d6fa6a | 10779 | nargs >>= 1; |
0499d65b TS |
10780 | narg++; |
10781 | } | |
91d6fa6a | 10782 | if (nargs != 0) |
0499d65b TS |
10783 | as_bad (_("invalid arg register list")); |
10784 | ||
10785 | /* Count static registers. */ | |
10786 | while (statics & 0x8) | |
10787 | { | |
10788 | statics = (statics << 1) & 0xf; | |
10789 | nstat++; | |
10790 | } | |
10791 | if (statics != 0) | |
10792 | as_bad (_("invalid static register list")); | |
10793 | ||
10794 | /* Encode args/statics. */ | |
10795 | opcode |= ((narg << 2) | nstat) << 16; | |
10796 | } | |
10797 | ||
10798 | /* Encode $s0/$s1. */ | |
10799 | if (sregs & (1 << 0)) /* $s0 */ | |
10800 | opcode |= 0x20; | |
10801 | if (sregs & (1 << 1)) /* $s1 */ | |
10802 | opcode |= 0x10; | |
10803 | sregs >>= 2; | |
10804 | ||
10805 | if (sregs != 0) | |
10806 | { | |
10807 | /* Count regs $s2-$s8. */ | |
10808 | int nsreg = 0; | |
10809 | while (sregs & 1) | |
10810 | { | |
10811 | sregs >>= 1; | |
10812 | nsreg++; | |
10813 | } | |
10814 | if (sregs != 0) | |
10815 | as_bad (_("invalid static register list")); | |
10816 | /* Encode $s2-$s8. */ | |
10817 | opcode |= nsreg << 24; | |
10818 | } | |
10819 | ||
10820 | /* Encode frame size. */ | |
10821 | if (!seen_framesz) | |
10822 | as_bad (_("missing frame size")); | |
10823 | else if ((framesz & 7) != 0 || framesz < 0 | |
10824 | || framesz > 0xff * 8) | |
10825 | as_bad (_("invalid frame size")); | |
10826 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10827 | { | |
10828 | framesz /= 8; | |
10829 | opcode |= (((framesz & 0xf0) << 16) | |
10830 | | (framesz & 0x0f)); | |
10831 | } | |
10832 | ||
10833 | /* Finally build the instruction. */ | |
10834 | if ((opcode >> 16) != 0 || framesz == 0) | |
10835 | { | |
10836 | ip->use_extend = TRUE; | |
10837 | ip->extend = opcode >> 16; | |
10838 | } | |
10839 | ip->insn_opcode |= opcode & 0x7f; | |
10840 | } | |
10841 | continue; | |
10842 | ||
252b5132 RH |
10843 | case 'e': /* extend code */ |
10844 | my_getExpression (&imm_expr, s); | |
10845 | check_absolute_expr (ip, &imm_expr); | |
10846 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10847 | { | |
10848 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10849 | ip->insn_mo->name, | |
10850 | (unsigned long) imm_expr.X_add_number); | |
10851 | imm_expr.X_add_number &= 0x7ff; | |
10852 | } | |
10853 | ip->insn_opcode |= imm_expr.X_add_number; | |
10854 | imm_expr.X_op = O_absent; | |
10855 | s = expr_end; | |
10856 | continue; | |
10857 | ||
10858 | default: | |
10859 | internalError (); | |
10860 | } | |
10861 | break; | |
10862 | } | |
10863 | ||
10864 | /* Args don't match. */ | |
10865 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10866 | strcmp (insn->name, insn[1].name) == 0) | |
10867 | { | |
10868 | ++insn; | |
10869 | s = argsstart; | |
10870 | continue; | |
10871 | } | |
10872 | ||
10873 | insn_error = _("illegal operands"); | |
10874 | ||
10875 | return; | |
10876 | } | |
10877 | } | |
10878 | ||
10879 | /* This structure holds information we know about a mips16 immediate | |
10880 | argument type. */ | |
10881 | ||
e972090a NC |
10882 | struct mips16_immed_operand |
10883 | { | |
252b5132 RH |
10884 | /* The type code used in the argument string in the opcode table. */ |
10885 | int type; | |
10886 | /* The number of bits in the short form of the opcode. */ | |
10887 | int nbits; | |
10888 | /* The number of bits in the extended form of the opcode. */ | |
10889 | int extbits; | |
10890 | /* The amount by which the short form is shifted when it is used; | |
10891 | for example, the sw instruction has a shift count of 2. */ | |
10892 | int shift; | |
10893 | /* The amount by which the short form is shifted when it is stored | |
10894 | into the instruction code. */ | |
10895 | int op_shift; | |
10896 | /* Non-zero if the short form is unsigned. */ | |
10897 | int unsp; | |
10898 | /* Non-zero if the extended form is unsigned. */ | |
10899 | int extu; | |
10900 | /* Non-zero if the value is PC relative. */ | |
10901 | int pcrel; | |
10902 | }; | |
10903 | ||
10904 | /* The mips16 immediate operand types. */ | |
10905 | ||
10906 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10907 | { | |
10908 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10909 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10910 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10911 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10912 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10913 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10914 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10915 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10916 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10917 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10918 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10919 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10920 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10921 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10922 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10923 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10924 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10925 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10926 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10927 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10928 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10929 | }; | |
10930 | ||
10931 | #define MIPS16_NUM_IMMED \ | |
10932 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10933 | ||
10934 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10935 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10936 | whether an extended value is needed; if one is needed, it sets | |
10937 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10938 | If SMALL is true, an unextended opcode was explicitly requested. | |
10939 | If EXT is true, an extended opcode was explicitly requested. If | |
10940 | WARN is true, warn if EXT does not match reality. */ | |
10941 | ||
10942 | static void | |
17a2f251 TS |
10943 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10944 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10945 | unsigned long *insn, bfd_boolean *use_extend, | |
10946 | unsigned short *extend) | |
252b5132 | 10947 | { |
3994f87e | 10948 | const struct mips16_immed_operand *op; |
252b5132 | 10949 | int mintiny, maxtiny; |
b34976b6 | 10950 | bfd_boolean needext; |
252b5132 RH |
10951 | |
10952 | op = mips16_immed_operands; | |
10953 | while (op->type != type) | |
10954 | { | |
10955 | ++op; | |
9c2799c2 | 10956 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
10957 | } |
10958 | ||
10959 | if (op->unsp) | |
10960 | { | |
10961 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10962 | { | |
10963 | mintiny = 1; | |
10964 | maxtiny = 1 << op->nbits; | |
10965 | } | |
10966 | else | |
10967 | { | |
10968 | mintiny = 0; | |
10969 | maxtiny = (1 << op->nbits) - 1; | |
10970 | } | |
10971 | } | |
10972 | else | |
10973 | { | |
10974 | mintiny = - (1 << (op->nbits - 1)); | |
10975 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10976 | } | |
10977 | ||
10978 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10979 | if (type == 'p' || type == 'q') | |
10980 | val /= 2; | |
10981 | ||
10982 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10983 | || val < (mintiny << op->shift) | |
10984 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10985 | needext = TRUE; |
252b5132 | 10986 | else |
b34976b6 | 10987 | needext = FALSE; |
252b5132 RH |
10988 | |
10989 | if (warn && ext && ! needext) | |
beae10d5 KH |
10990 | as_warn_where (file, line, |
10991 | _("extended operand requested but not required")); | |
252b5132 RH |
10992 | if (small && needext) |
10993 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10994 | ||
10995 | if (small || (! ext && ! needext)) | |
10996 | { | |
10997 | int insnval; | |
10998 | ||
b34976b6 | 10999 | *use_extend = FALSE; |
252b5132 RH |
11000 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
11001 | insnval <<= op->op_shift; | |
11002 | *insn |= insnval; | |
11003 | } | |
11004 | else | |
11005 | { | |
11006 | long minext, maxext; | |
11007 | int extval; | |
11008 | ||
11009 | if (op->extu) | |
11010 | { | |
11011 | minext = 0; | |
11012 | maxext = (1 << op->extbits) - 1; | |
11013 | } | |
11014 | else | |
11015 | { | |
11016 | minext = - (1 << (op->extbits - 1)); | |
11017 | maxext = (1 << (op->extbits - 1)) - 1; | |
11018 | } | |
11019 | if (val < minext || val > maxext) | |
11020 | as_bad_where (file, line, | |
11021 | _("operand value out of range for instruction")); | |
11022 | ||
b34976b6 | 11023 | *use_extend = TRUE; |
252b5132 RH |
11024 | if (op->extbits == 16) |
11025 | { | |
11026 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
11027 | val &= 0x1f; | |
11028 | } | |
11029 | else if (op->extbits == 15) | |
11030 | { | |
11031 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
11032 | val &= 0xf; | |
11033 | } | |
11034 | else | |
11035 | { | |
11036 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
11037 | val = 0; | |
11038 | } | |
11039 | ||
11040 | *extend = (unsigned short) extval; | |
11041 | *insn |= val; | |
11042 | } | |
11043 | } | |
11044 | \f | |
d6f16593 | 11045 | struct percent_op_match |
ad8d3bb3 | 11046 | { |
5e0116d5 RS |
11047 | const char *str; |
11048 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
11049 | }; |
11050 | ||
11051 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 11052 | { |
5e0116d5 | 11053 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 11054 | #ifdef OBJ_ELF |
5e0116d5 RS |
11055 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
11056 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
11057 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
11058 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
11059 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
11060 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
11061 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
11062 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
11063 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
11064 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
11065 | {"%half", BFD_RELOC_16}, | |
11066 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
11067 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
11068 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
11069 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
11070 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
11071 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
11072 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
11073 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
11074 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
11075 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 11076 | #endif |
5e0116d5 | 11077 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
11078 | }; |
11079 | ||
d6f16593 MR |
11080 | static const struct percent_op_match mips16_percent_op[] = |
11081 | { | |
11082 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
11083 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
11084 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
11085 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
11086 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
11087 | }; | |
11088 | ||
252b5132 | 11089 | |
5e0116d5 RS |
11090 | /* Return true if *STR points to a relocation operator. When returning true, |
11091 | move *STR over the operator and store its relocation code in *RELOC. | |
11092 | Leave both *STR and *RELOC alone when returning false. */ | |
11093 | ||
11094 | static bfd_boolean | |
17a2f251 | 11095 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 11096 | { |
d6f16593 MR |
11097 | const struct percent_op_match *percent_op; |
11098 | size_t limit, i; | |
11099 | ||
11100 | if (mips_opts.mips16) | |
11101 | { | |
11102 | percent_op = mips16_percent_op; | |
11103 | limit = ARRAY_SIZE (mips16_percent_op); | |
11104 | } | |
11105 | else | |
11106 | { | |
11107 | percent_op = mips_percent_op; | |
11108 | limit = ARRAY_SIZE (mips_percent_op); | |
11109 | } | |
76b3015f | 11110 | |
d6f16593 | 11111 | for (i = 0; i < limit; i++) |
5e0116d5 | 11112 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 11113 | { |
3f98094e DJ |
11114 | int len = strlen (percent_op[i].str); |
11115 | ||
11116 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
11117 | continue; | |
11118 | ||
5e0116d5 RS |
11119 | *str += strlen (percent_op[i].str); |
11120 | *reloc = percent_op[i].reloc; | |
394f9b3a | 11121 | |
5e0116d5 RS |
11122 | /* Check whether the output BFD supports this relocation. |
11123 | If not, issue an error and fall back on something safe. */ | |
11124 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 11125 | { |
20203fb9 | 11126 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 11127 | percent_op[i].str); |
01a3f561 | 11128 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 11129 | } |
5e0116d5 | 11130 | return TRUE; |
394f9b3a | 11131 | } |
5e0116d5 | 11132 | return FALSE; |
394f9b3a | 11133 | } |
ad8d3bb3 | 11134 | |
ad8d3bb3 | 11135 | |
5e0116d5 RS |
11136 | /* Parse string STR as a 16-bit relocatable operand. Store the |
11137 | expression in *EP and the relocations in the array starting | |
11138 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 11139 | |
01a3f561 | 11140 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 11141 | |
5e0116d5 | 11142 | static size_t |
17a2f251 TS |
11143 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
11144 | char *str) | |
ad8d3bb3 | 11145 | { |
5e0116d5 RS |
11146 | bfd_reloc_code_real_type reversed_reloc[3]; |
11147 | size_t reloc_index, i; | |
09b8f35a RS |
11148 | int crux_depth, str_depth; |
11149 | char *crux; | |
5e0116d5 RS |
11150 | |
11151 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
11152 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
11153 | of the main expression and with CRUX_DEPTH containing the number | |
11154 | of open brackets at that point. */ | |
11155 | reloc_index = -1; | |
11156 | str_depth = 0; | |
11157 | do | |
fb1b3232 | 11158 | { |
09b8f35a RS |
11159 | reloc_index++; |
11160 | crux = str; | |
11161 | crux_depth = str_depth; | |
11162 | ||
11163 | /* Skip over whitespace and brackets, keeping count of the number | |
11164 | of brackets. */ | |
11165 | while (*str == ' ' || *str == '\t' || *str == '(') | |
11166 | if (*str++ == '(') | |
11167 | str_depth++; | |
5e0116d5 | 11168 | } |
09b8f35a RS |
11169 | while (*str == '%' |
11170 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
11171 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 11172 | |
09b8f35a | 11173 | my_getExpression (ep, crux); |
5e0116d5 | 11174 | str = expr_end; |
394f9b3a | 11175 | |
5e0116d5 | 11176 | /* Match every open bracket. */ |
09b8f35a | 11177 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 11178 | if (*str++ == ')') |
09b8f35a | 11179 | crux_depth--; |
394f9b3a | 11180 | |
09b8f35a | 11181 | if (crux_depth > 0) |
20203fb9 | 11182 | as_bad (_("unclosed '('")); |
394f9b3a | 11183 | |
5e0116d5 | 11184 | expr_end = str; |
252b5132 | 11185 | |
01a3f561 | 11186 | if (reloc_index != 0) |
64bdfcaf RS |
11187 | { |
11188 | prev_reloc_op_frag = frag_now; | |
11189 | for (i = 0; i < reloc_index; i++) | |
11190 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
11191 | } | |
fb1b3232 | 11192 | |
5e0116d5 | 11193 | return reloc_index; |
252b5132 RH |
11194 | } |
11195 | ||
11196 | static void | |
17a2f251 | 11197 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
11198 | { |
11199 | char *save_in; | |
98aa84af | 11200 | valueT val; |
252b5132 RH |
11201 | |
11202 | save_in = input_line_pointer; | |
11203 | input_line_pointer = str; | |
11204 | expression (ep); | |
11205 | expr_end = input_line_pointer; | |
11206 | input_line_pointer = save_in; | |
11207 | ||
11208 | /* If we are in mips16 mode, and this is an expression based on `.', | |
11209 | then we bump the value of the symbol by 1 since that is how other | |
11210 | text symbols are handled. We don't bother to handle complex | |
11211 | expressions, just `.' plus or minus a constant. */ | |
11212 | if (mips_opts.mips16 | |
11213 | && ep->X_op == O_symbol | |
11214 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
11215 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
11216 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
11217 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
11218 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
11219 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
11220 | } |
11221 | ||
252b5132 | 11222 | char * |
17a2f251 | 11223 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11224 | { |
499ac353 | 11225 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
11226 | } |
11227 | ||
11228 | void | |
17a2f251 | 11229 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
11230 | { |
11231 | if (target_big_endian) | |
11232 | number_to_chars_bigendian (buf, val, n); | |
11233 | else | |
11234 | number_to_chars_littleendian (buf, val, n); | |
11235 | } | |
11236 | \f | |
ae948b86 | 11237 | #ifdef OBJ_ELF |
e013f690 TS |
11238 | static int support_64bit_objects(void) |
11239 | { | |
11240 | const char **list, **l; | |
aa3d8fdf | 11241 | int yes; |
e013f690 TS |
11242 | |
11243 | list = bfd_target_list (); | |
11244 | for (l = list; *l != NULL; l++) | |
11245 | #ifdef TE_TMIPS | |
11246 | /* This is traditional mips */ | |
11247 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
11248 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
11249 | #else | |
11250 | if (strcmp (*l, "elf64-bigmips") == 0 | |
11251 | || strcmp (*l, "elf64-littlemips") == 0) | |
11252 | #endif | |
11253 | break; | |
aa3d8fdf | 11254 | yes = (*l != NULL); |
e013f690 | 11255 | free (list); |
aa3d8fdf | 11256 | return yes; |
e013f690 | 11257 | } |
ae948b86 | 11258 | #endif /* OBJ_ELF */ |
e013f690 | 11259 | |
78849248 | 11260 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 11261 | |
23fce1e3 NC |
11262 | enum options |
11263 | { | |
11264 | OPTION_MARCH = OPTION_MD_BASE, | |
11265 | OPTION_MTUNE, | |
11266 | OPTION_MIPS1, | |
11267 | OPTION_MIPS2, | |
11268 | OPTION_MIPS3, | |
11269 | OPTION_MIPS4, | |
11270 | OPTION_MIPS5, | |
11271 | OPTION_MIPS32, | |
11272 | OPTION_MIPS64, | |
11273 | OPTION_MIPS32R2, | |
11274 | OPTION_MIPS64R2, | |
11275 | OPTION_MIPS16, | |
11276 | OPTION_NO_MIPS16, | |
11277 | OPTION_MIPS3D, | |
11278 | OPTION_NO_MIPS3D, | |
11279 | OPTION_MDMX, | |
11280 | OPTION_NO_MDMX, | |
11281 | OPTION_DSP, | |
11282 | OPTION_NO_DSP, | |
11283 | OPTION_MT, | |
11284 | OPTION_NO_MT, | |
11285 | OPTION_SMARTMIPS, | |
11286 | OPTION_NO_SMARTMIPS, | |
11287 | OPTION_DSPR2, | |
11288 | OPTION_NO_DSPR2, | |
11289 | OPTION_COMPAT_ARCH_BASE, | |
11290 | OPTION_M4650, | |
11291 | OPTION_NO_M4650, | |
11292 | OPTION_M4010, | |
11293 | OPTION_NO_M4010, | |
11294 | OPTION_M4100, | |
11295 | OPTION_NO_M4100, | |
11296 | OPTION_M3900, | |
11297 | OPTION_NO_M3900, | |
11298 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
11299 | OPTION_MNO_7000_HILO_FIX, |
11300 | OPTION_FIX_24K, | |
11301 | OPTION_NO_FIX_24K, | |
c67a084a NC |
11302 | OPTION_FIX_LOONGSON2F_JUMP, |
11303 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
11304 | OPTION_FIX_LOONGSON2F_NOP, | |
11305 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
11306 | OPTION_FIX_VR4120, |
11307 | OPTION_NO_FIX_VR4120, | |
11308 | OPTION_FIX_VR4130, | |
11309 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
11310 | OPTION_FIX_CN63XXP1, |
11311 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
11312 | OPTION_TRAP, |
11313 | OPTION_BREAK, | |
11314 | OPTION_EB, | |
11315 | OPTION_EL, | |
11316 | OPTION_FP32, | |
11317 | OPTION_GP32, | |
11318 | OPTION_CONSTRUCT_FLOATS, | |
11319 | OPTION_NO_CONSTRUCT_FLOATS, | |
11320 | OPTION_FP64, | |
11321 | OPTION_GP64, | |
11322 | OPTION_RELAX_BRANCH, | |
11323 | OPTION_NO_RELAX_BRANCH, | |
11324 | OPTION_MSHARED, | |
11325 | OPTION_MNO_SHARED, | |
11326 | OPTION_MSYM32, | |
11327 | OPTION_MNO_SYM32, | |
11328 | OPTION_SOFT_FLOAT, | |
11329 | OPTION_HARD_FLOAT, | |
11330 | OPTION_SINGLE_FLOAT, | |
11331 | OPTION_DOUBLE_FLOAT, | |
11332 | OPTION_32, | |
11333 | #ifdef OBJ_ELF | |
11334 | OPTION_CALL_SHARED, | |
11335 | OPTION_CALL_NONPIC, | |
11336 | OPTION_NON_SHARED, | |
11337 | OPTION_XGOT, | |
11338 | OPTION_MABI, | |
11339 | OPTION_N32, | |
11340 | OPTION_64, | |
11341 | OPTION_MDEBUG, | |
11342 | OPTION_NO_MDEBUG, | |
11343 | OPTION_PDR, | |
11344 | OPTION_NO_PDR, | |
11345 | OPTION_MVXWORKS_PIC, | |
11346 | #endif /* OBJ_ELF */ | |
11347 | OPTION_END_OF_ENUM | |
11348 | }; | |
11349 | ||
e972090a NC |
11350 | struct option md_longopts[] = |
11351 | { | |
f9b4148d | 11352 | /* Options which specify architecture. */ |
f9b4148d | 11353 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 11354 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
11355 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
11356 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 11357 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 11358 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 11359 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 11360 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 11361 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 11362 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 11363 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 11364 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
11365 | |
11366 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 11367 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 11368 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 11369 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 11370 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 11371 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 11372 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 11373 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 11374 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 11375 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 11376 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 11377 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 11378 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 11379 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 11380 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
f9b4148d CD |
11381 | |
11382 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 11383 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 11384 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 11385 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 11386 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 11387 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 11388 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 11389 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
11390 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
11391 | ||
11392 | /* Options which enable bug fixes. */ | |
f9b4148d | 11393 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
11394 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
11395 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
11396 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
11397 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
11398 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
11399 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
11400 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
11401 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
11402 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
11403 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
11404 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
11405 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
11406 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
11407 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
11408 | |
11409 | /* Miscellaneous options. */ | |
252b5132 RH |
11410 | {"trap", no_argument, NULL, OPTION_TRAP}, |
11411 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
11412 | {"break", no_argument, NULL, OPTION_BREAK}, |
11413 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 11414 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 11415 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 11416 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 11417 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 11418 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 11419 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 11420 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 11421 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
11422 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
11423 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
11424 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
11425 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
11426 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
11427 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
11428 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
11429 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
11430 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
11431 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
11432 | |
11433 | /* Strictly speaking this next option is ELF specific, | |
11434 | but we allow it for other ports as well in order to | |
11435 | make testing easier. */ | |
11436 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 11437 | |
f9b4148d | 11438 | /* ELF-specific options. */ |
156c2f8b | 11439 | #ifdef OBJ_ELF |
156c2f8b NC |
11440 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
11441 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 11442 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
11443 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
11444 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 11445 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 11446 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 11447 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 11448 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 11449 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 11450 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 11451 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 11452 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 11453 | #endif /* OBJ_ELF */ |
f9b4148d | 11454 | |
252b5132 RH |
11455 | {NULL, no_argument, NULL, 0} |
11456 | }; | |
156c2f8b | 11457 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11458 | |
316f5878 RS |
11459 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11460 | NEW_VALUE. Warn if another value was already specified. Note: | |
11461 | we have to defer parsing the -march and -mtune arguments in order | |
11462 | to handle 'from-abi' correctly, since the ABI might be specified | |
11463 | in a later argument. */ | |
11464 | ||
11465 | static void | |
17a2f251 | 11466 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11467 | { |
11468 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11469 | as_warn (_("A different %s was already specified, is now %s"), | |
11470 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11471 | new_value); | |
11472 | ||
11473 | *string_ptr = new_value; | |
11474 | } | |
11475 | ||
252b5132 | 11476 | int |
17a2f251 | 11477 | md_parse_option (int c, char *arg) |
252b5132 RH |
11478 | { |
11479 | switch (c) | |
11480 | { | |
119d663a NC |
11481 | case OPTION_CONSTRUCT_FLOATS: |
11482 | mips_disable_float_construction = 0; | |
11483 | break; | |
bdaaa2e1 | 11484 | |
119d663a NC |
11485 | case OPTION_NO_CONSTRUCT_FLOATS: |
11486 | mips_disable_float_construction = 1; | |
11487 | break; | |
bdaaa2e1 | 11488 | |
252b5132 RH |
11489 | case OPTION_TRAP: |
11490 | mips_trap = 1; | |
11491 | break; | |
11492 | ||
11493 | case OPTION_BREAK: | |
11494 | mips_trap = 0; | |
11495 | break; | |
11496 | ||
11497 | case OPTION_EB: | |
11498 | target_big_endian = 1; | |
11499 | break; | |
11500 | ||
11501 | case OPTION_EL: | |
11502 | target_big_endian = 0; | |
11503 | break; | |
11504 | ||
11505 | case 'O': | |
4ffff32f TS |
11506 | if (arg == NULL) |
11507 | mips_optimize = 1; | |
11508 | else if (arg[0] == '0') | |
11509 | mips_optimize = 0; | |
11510 | else if (arg[0] == '1') | |
252b5132 RH |
11511 | mips_optimize = 1; |
11512 | else | |
11513 | mips_optimize = 2; | |
11514 | break; | |
11515 | ||
11516 | case 'g': | |
11517 | if (arg == NULL) | |
11518 | mips_debug = 2; | |
11519 | else | |
11520 | mips_debug = atoi (arg); | |
252b5132 RH |
11521 | break; |
11522 | ||
11523 | case OPTION_MIPS1: | |
316f5878 | 11524 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11525 | break; |
11526 | ||
11527 | case OPTION_MIPS2: | |
316f5878 | 11528 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11529 | break; |
11530 | ||
11531 | case OPTION_MIPS3: | |
316f5878 | 11532 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11533 | break; |
11534 | ||
11535 | case OPTION_MIPS4: | |
316f5878 | 11536 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11537 | break; |
11538 | ||
84ea6cf2 | 11539 | case OPTION_MIPS5: |
316f5878 | 11540 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11541 | break; |
11542 | ||
e7af610e | 11543 | case OPTION_MIPS32: |
316f5878 | 11544 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11545 | break; |
11546 | ||
af7ee8bf CD |
11547 | case OPTION_MIPS32R2: |
11548 | file_mips_isa = ISA_MIPS32R2; | |
11549 | break; | |
11550 | ||
5f74bc13 CD |
11551 | case OPTION_MIPS64R2: |
11552 | file_mips_isa = ISA_MIPS64R2; | |
11553 | break; | |
11554 | ||
84ea6cf2 | 11555 | case OPTION_MIPS64: |
316f5878 | 11556 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11557 | break; |
11558 | ||
ec68c924 | 11559 | case OPTION_MTUNE: |
316f5878 RS |
11560 | mips_set_option_string (&mips_tune_string, arg); |
11561 | break; | |
ec68c924 | 11562 | |
316f5878 RS |
11563 | case OPTION_MARCH: |
11564 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11565 | break; |
11566 | ||
11567 | case OPTION_M4650: | |
316f5878 RS |
11568 | mips_set_option_string (&mips_arch_string, "4650"); |
11569 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11570 | break; |
11571 | ||
11572 | case OPTION_NO_M4650: | |
11573 | break; | |
11574 | ||
11575 | case OPTION_M4010: | |
316f5878 RS |
11576 | mips_set_option_string (&mips_arch_string, "4010"); |
11577 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11578 | break; |
11579 | ||
11580 | case OPTION_NO_M4010: | |
11581 | break; | |
11582 | ||
11583 | case OPTION_M4100: | |
316f5878 RS |
11584 | mips_set_option_string (&mips_arch_string, "4100"); |
11585 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11586 | break; |
11587 | ||
11588 | case OPTION_NO_M4100: | |
11589 | break; | |
11590 | ||
252b5132 | 11591 | case OPTION_M3900: |
316f5878 RS |
11592 | mips_set_option_string (&mips_arch_string, "3900"); |
11593 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11594 | break; |
bdaaa2e1 | 11595 | |
252b5132 RH |
11596 | case OPTION_NO_M3900: |
11597 | break; | |
11598 | ||
deec1734 CD |
11599 | case OPTION_MDMX: |
11600 | mips_opts.ase_mdmx = 1; | |
11601 | break; | |
11602 | ||
11603 | case OPTION_NO_MDMX: | |
11604 | mips_opts.ase_mdmx = 0; | |
11605 | break; | |
11606 | ||
74cd071d CF |
11607 | case OPTION_DSP: |
11608 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11609 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11610 | break; |
11611 | ||
11612 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11613 | mips_opts.ase_dsp = 0; |
11614 | mips_opts.ase_dspr2 = 0; | |
11615 | break; | |
11616 | ||
11617 | case OPTION_DSPR2: | |
11618 | mips_opts.ase_dspr2 = 1; | |
11619 | mips_opts.ase_dsp = 1; | |
11620 | break; | |
11621 | ||
11622 | case OPTION_NO_DSPR2: | |
11623 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11624 | mips_opts.ase_dsp = 0; |
11625 | break; | |
11626 | ||
ef2e4d86 CF |
11627 | case OPTION_MT: |
11628 | mips_opts.ase_mt = 1; | |
11629 | break; | |
11630 | ||
11631 | case OPTION_NO_MT: | |
11632 | mips_opts.ase_mt = 0; | |
11633 | break; | |
11634 | ||
252b5132 RH |
11635 | case OPTION_MIPS16: |
11636 | mips_opts.mips16 = 1; | |
7d10b47d | 11637 | mips_no_prev_insn (); |
252b5132 RH |
11638 | break; |
11639 | ||
11640 | case OPTION_NO_MIPS16: | |
11641 | mips_opts.mips16 = 0; | |
7d10b47d | 11642 | mips_no_prev_insn (); |
252b5132 RH |
11643 | break; |
11644 | ||
1f25f5d3 CD |
11645 | case OPTION_MIPS3D: |
11646 | mips_opts.ase_mips3d = 1; | |
11647 | break; | |
11648 | ||
11649 | case OPTION_NO_MIPS3D: | |
11650 | mips_opts.ase_mips3d = 0; | |
11651 | break; | |
11652 | ||
e16bfa71 TS |
11653 | case OPTION_SMARTMIPS: |
11654 | mips_opts.ase_smartmips = 1; | |
11655 | break; | |
11656 | ||
11657 | case OPTION_NO_SMARTMIPS: | |
11658 | mips_opts.ase_smartmips = 0; | |
11659 | break; | |
11660 | ||
6a32d874 CM |
11661 | case OPTION_FIX_24K: |
11662 | mips_fix_24k = 1; | |
11663 | break; | |
11664 | ||
11665 | case OPTION_NO_FIX_24K: | |
11666 | mips_fix_24k = 0; | |
11667 | break; | |
11668 | ||
c67a084a NC |
11669 | case OPTION_FIX_LOONGSON2F_JUMP: |
11670 | mips_fix_loongson2f_jump = TRUE; | |
11671 | break; | |
11672 | ||
11673 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
11674 | mips_fix_loongson2f_jump = FALSE; | |
11675 | break; | |
11676 | ||
11677 | case OPTION_FIX_LOONGSON2F_NOP: | |
11678 | mips_fix_loongson2f_nop = TRUE; | |
11679 | break; | |
11680 | ||
11681 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
11682 | mips_fix_loongson2f_nop = FALSE; | |
11683 | break; | |
11684 | ||
d766e8ec RS |
11685 | case OPTION_FIX_VR4120: |
11686 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11687 | break; |
11688 | ||
d766e8ec RS |
11689 | case OPTION_NO_FIX_VR4120: |
11690 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11691 | break; |
11692 | ||
7d8e00cf RS |
11693 | case OPTION_FIX_VR4130: |
11694 | mips_fix_vr4130 = 1; | |
11695 | break; | |
11696 | ||
11697 | case OPTION_NO_FIX_VR4130: | |
11698 | mips_fix_vr4130 = 0; | |
11699 | break; | |
11700 | ||
d954098f DD |
11701 | case OPTION_FIX_CN63XXP1: |
11702 | mips_fix_cn63xxp1 = TRUE; | |
11703 | break; | |
11704 | ||
11705 | case OPTION_NO_FIX_CN63XXP1: | |
11706 | mips_fix_cn63xxp1 = FALSE; | |
11707 | break; | |
11708 | ||
4a6a3df4 AO |
11709 | case OPTION_RELAX_BRANCH: |
11710 | mips_relax_branch = 1; | |
11711 | break; | |
11712 | ||
11713 | case OPTION_NO_RELAX_BRANCH: | |
11714 | mips_relax_branch = 0; | |
11715 | break; | |
11716 | ||
aa6975fb ILT |
11717 | case OPTION_MSHARED: |
11718 | mips_in_shared = TRUE; | |
11719 | break; | |
11720 | ||
11721 | case OPTION_MNO_SHARED: | |
11722 | mips_in_shared = FALSE; | |
11723 | break; | |
11724 | ||
aed1a261 RS |
11725 | case OPTION_MSYM32: |
11726 | mips_opts.sym32 = TRUE; | |
11727 | break; | |
11728 | ||
11729 | case OPTION_MNO_SYM32: | |
11730 | mips_opts.sym32 = FALSE; | |
11731 | break; | |
11732 | ||
0f074f60 | 11733 | #ifdef OBJ_ELF |
252b5132 RH |
11734 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11735 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11736 | intended to be compatible with Irix 5. */ | |
11737 | case OPTION_CALL_SHARED: | |
f43abd2b | 11738 | if (!IS_ELF) |
252b5132 RH |
11739 | { |
11740 | as_bad (_("-call_shared is supported only for ELF format")); | |
11741 | return 0; | |
11742 | } | |
11743 | mips_pic = SVR4_PIC; | |
143d77c5 | 11744 | mips_abicalls = TRUE; |
252b5132 RH |
11745 | break; |
11746 | ||
861fb55a DJ |
11747 | case OPTION_CALL_NONPIC: |
11748 | if (!IS_ELF) | |
11749 | { | |
11750 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
11751 | return 0; | |
11752 | } | |
11753 | mips_pic = NO_PIC; | |
11754 | mips_abicalls = TRUE; | |
11755 | break; | |
11756 | ||
252b5132 | 11757 | case OPTION_NON_SHARED: |
f43abd2b | 11758 | if (!IS_ELF) |
252b5132 RH |
11759 | { |
11760 | as_bad (_("-non_shared is supported only for ELF format")); | |
11761 | return 0; | |
11762 | } | |
11763 | mips_pic = NO_PIC; | |
143d77c5 | 11764 | mips_abicalls = FALSE; |
252b5132 RH |
11765 | break; |
11766 | ||
44075ae2 TS |
11767 | /* The -xgot option tells the assembler to use 32 bit offsets |
11768 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11769 | compatibility. */ |
11770 | case OPTION_XGOT: | |
11771 | mips_big_got = 1; | |
11772 | break; | |
0f074f60 | 11773 | #endif /* OBJ_ELF */ |
252b5132 RH |
11774 | |
11775 | case 'G': | |
6caf9ef4 TS |
11776 | g_switch_value = atoi (arg); |
11777 | g_switch_seen = 1; | |
252b5132 RH |
11778 | break; |
11779 | ||
34ba82a8 TS |
11780 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11781 | and -mabi=64. */ | |
252b5132 | 11782 | case OPTION_32: |
23fce1e3 NC |
11783 | if (IS_ELF) |
11784 | mips_abi = O32_ABI; | |
11785 | /* We silently ignore -32 for non-ELF targets. This greatly | |
11786 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
11787 | break; |
11788 | ||
23fce1e3 | 11789 | #ifdef OBJ_ELF |
e013f690 | 11790 | case OPTION_N32: |
f43abd2b | 11791 | if (!IS_ELF) |
34ba82a8 TS |
11792 | { |
11793 | as_bad (_("-n32 is supported for ELF format only")); | |
11794 | return 0; | |
11795 | } | |
316f5878 | 11796 | mips_abi = N32_ABI; |
e013f690 | 11797 | break; |
252b5132 | 11798 | |
e013f690 | 11799 | case OPTION_64: |
f43abd2b | 11800 | if (!IS_ELF) |
34ba82a8 TS |
11801 | { |
11802 | as_bad (_("-64 is supported for ELF format only")); | |
11803 | return 0; | |
11804 | } | |
316f5878 | 11805 | mips_abi = N64_ABI; |
f43abd2b | 11806 | if (!support_64bit_objects()) |
e013f690 | 11807 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11808 | break; |
ae948b86 | 11809 | #endif /* OBJ_ELF */ |
252b5132 | 11810 | |
c97ef257 | 11811 | case OPTION_GP32: |
a325df1d | 11812 | file_mips_gp32 = 1; |
c97ef257 AH |
11813 | break; |
11814 | ||
11815 | case OPTION_GP64: | |
a325df1d | 11816 | file_mips_gp32 = 0; |
c97ef257 | 11817 | break; |
252b5132 | 11818 | |
ca4e0257 | 11819 | case OPTION_FP32: |
a325df1d | 11820 | file_mips_fp32 = 1; |
316f5878 RS |
11821 | break; |
11822 | ||
11823 | case OPTION_FP64: | |
11824 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11825 | break; |
11826 | ||
037b32b9 AN |
11827 | case OPTION_SINGLE_FLOAT: |
11828 | file_mips_single_float = 1; | |
11829 | break; | |
11830 | ||
11831 | case OPTION_DOUBLE_FLOAT: | |
11832 | file_mips_single_float = 0; | |
11833 | break; | |
11834 | ||
11835 | case OPTION_SOFT_FLOAT: | |
11836 | file_mips_soft_float = 1; | |
11837 | break; | |
11838 | ||
11839 | case OPTION_HARD_FLOAT: | |
11840 | file_mips_soft_float = 0; | |
11841 | break; | |
11842 | ||
ae948b86 | 11843 | #ifdef OBJ_ELF |
252b5132 | 11844 | case OPTION_MABI: |
f43abd2b | 11845 | if (!IS_ELF) |
34ba82a8 TS |
11846 | { |
11847 | as_bad (_("-mabi is supported for ELF format only")); | |
11848 | return 0; | |
11849 | } | |
e013f690 | 11850 | if (strcmp (arg, "32") == 0) |
316f5878 | 11851 | mips_abi = O32_ABI; |
e013f690 | 11852 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11853 | mips_abi = O64_ABI; |
e013f690 | 11854 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11855 | mips_abi = N32_ABI; |
e013f690 TS |
11856 | else if (strcmp (arg, "64") == 0) |
11857 | { | |
316f5878 | 11858 | mips_abi = N64_ABI; |
e013f690 TS |
11859 | if (! support_64bit_objects()) |
11860 | as_fatal (_("No compiled in support for 64 bit object file " | |
11861 | "format")); | |
11862 | } | |
11863 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11864 | mips_abi = EABI_ABI; |
e013f690 | 11865 | else |
da0e507f TS |
11866 | { |
11867 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11868 | return 0; | |
11869 | } | |
252b5132 | 11870 | break; |
e013f690 | 11871 | #endif /* OBJ_ELF */ |
252b5132 | 11872 | |
6b76fefe | 11873 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11874 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11875 | break; |
11876 | ||
9ee72ff1 | 11877 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11878 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11879 | break; |
11880 | ||
ecb4347a DJ |
11881 | #ifdef OBJ_ELF |
11882 | case OPTION_MDEBUG: | |
b34976b6 | 11883 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11884 | break; |
11885 | ||
11886 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11887 | mips_flag_mdebug = FALSE; |
ecb4347a | 11888 | break; |
dcd410fe RO |
11889 | |
11890 | case OPTION_PDR: | |
11891 | mips_flag_pdr = TRUE; | |
11892 | break; | |
11893 | ||
11894 | case OPTION_NO_PDR: | |
11895 | mips_flag_pdr = FALSE; | |
11896 | break; | |
0a44bf69 RS |
11897 | |
11898 | case OPTION_MVXWORKS_PIC: | |
11899 | mips_pic = VXWORKS_PIC; | |
11900 | break; | |
ecb4347a DJ |
11901 | #endif /* OBJ_ELF */ |
11902 | ||
252b5132 RH |
11903 | default: |
11904 | return 0; | |
11905 | } | |
11906 | ||
c67a084a NC |
11907 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
11908 | ||
252b5132 RH |
11909 | return 1; |
11910 | } | |
316f5878 RS |
11911 | \f |
11912 | /* Set up globals to generate code for the ISA or processor | |
11913 | described by INFO. */ | |
252b5132 | 11914 | |
252b5132 | 11915 | static void |
17a2f251 | 11916 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11917 | { |
316f5878 | 11918 | if (info != 0) |
252b5132 | 11919 | { |
fef14a42 TS |
11920 | file_mips_arch = info->cpu; |
11921 | mips_opts.arch = info->cpu; | |
316f5878 | 11922 | mips_opts.isa = info->isa; |
252b5132 | 11923 | } |
252b5132 RH |
11924 | } |
11925 | ||
252b5132 | 11926 | |
316f5878 | 11927 | /* Likewise for tuning. */ |
252b5132 | 11928 | |
316f5878 | 11929 | static void |
17a2f251 | 11930 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11931 | { |
11932 | if (info != 0) | |
fef14a42 | 11933 | mips_tune = info->cpu; |
316f5878 | 11934 | } |
80cc45a5 | 11935 | |
34ba82a8 | 11936 | |
252b5132 | 11937 | void |
17a2f251 | 11938 | mips_after_parse_args (void) |
e9670677 | 11939 | { |
fef14a42 TS |
11940 | const struct mips_cpu_info *arch_info = 0; |
11941 | const struct mips_cpu_info *tune_info = 0; | |
11942 | ||
e9670677 | 11943 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11944 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11945 | { |
6caf9ef4 | 11946 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11947 | as_bad (_("-G not supported in this configuration.")); |
11948 | g_switch_value = 0; | |
11949 | } | |
11950 | ||
cac012d6 AO |
11951 | if (mips_abi == NO_ABI) |
11952 | mips_abi = MIPS_DEFAULT_ABI; | |
11953 | ||
22923709 RS |
11954 | /* The following code determines the architecture and register size. |
11955 | Similar code was added to GCC 3.3 (see override_options() in | |
11956 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11957 | as much as possible. */ | |
e9670677 | 11958 | |
316f5878 | 11959 | if (mips_arch_string != 0) |
fef14a42 | 11960 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11961 | |
316f5878 | 11962 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11963 | { |
316f5878 | 11964 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11965 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11966 | the -march selection (if any). */ |
fef14a42 | 11967 | if (arch_info != 0) |
e9670677 | 11968 | { |
316f5878 RS |
11969 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11970 | There's no harm in specifying both as long as the ISA levels | |
11971 | are the same. */ | |
fef14a42 | 11972 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11973 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11974 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11975 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11976 | } |
316f5878 | 11977 | else |
fef14a42 | 11978 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11979 | } |
11980 | ||
fef14a42 TS |
11981 | if (arch_info == 0) |
11982 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11983 | |
fef14a42 | 11984 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 11985 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
11986 | arch_info->name); |
11987 | ||
11988 | mips_set_architecture (arch_info); | |
11989 | ||
11990 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11991 | if (mips_tune_string != 0) | |
11992 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11993 | |
fef14a42 TS |
11994 | if (tune_info == 0) |
11995 | mips_set_tune (arch_info); | |
11996 | else | |
11997 | mips_set_tune (tune_info); | |
e9670677 | 11998 | |
316f5878 | 11999 | if (file_mips_gp32 >= 0) |
e9670677 | 12000 | { |
316f5878 RS |
12001 | /* The user specified the size of the integer registers. Make sure |
12002 | it agrees with the ABI and ISA. */ | |
12003 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12004 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
12005 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12006 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
12007 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
12008 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
12009 | } |
12010 | else | |
12011 | { | |
316f5878 RS |
12012 | /* Infer the integer register size from the ABI and processor. |
12013 | Restrict ourselves to 32-bit registers if that's all the | |
12014 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
12015 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12016 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
12017 | } |
12018 | ||
ad3fea08 TS |
12019 | switch (file_mips_fp32) |
12020 | { | |
12021 | default: | |
12022 | case -1: | |
12023 | /* No user specified float register size. | |
12024 | ??? GAS treats single-float processors as though they had 64-bit | |
12025 | float registers (although it complains when double-precision | |
12026 | instructions are used). As things stand, saying they have 32-bit | |
12027 | registers would lead to spurious "register must be even" messages. | |
12028 | So here we assume float registers are never smaller than the | |
12029 | integer ones. */ | |
12030 | if (file_mips_gp32 == 0) | |
12031 | /* 64-bit integer registers implies 64-bit float registers. */ | |
12032 | file_mips_fp32 = 0; | |
12033 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
12034 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12035 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
12036 | file_mips_fp32 = 0; | |
12037 | else | |
12038 | /* 32-bit float registers. */ | |
12039 | file_mips_fp32 = 1; | |
12040 | break; | |
12041 | ||
12042 | /* The user specified the size of the float registers. Check if it | |
12043 | agrees with the ABI and ISA. */ | |
12044 | case 0: | |
12045 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12046 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
12047 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
12048 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
12049 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
12050 | break; | |
12051 | case 1: | |
12052 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
12053 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
12054 | break; | |
12055 | } | |
e9670677 | 12056 | |
316f5878 | 12057 | /* End of GCC-shared inference code. */ |
e9670677 | 12058 | |
17a2f251 TS |
12059 | /* This flag is set when we have a 64-bit capable CPU but use only |
12060 | 32-bit wide registers. Note that EABI does not use it. */ | |
12061 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
12062 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
12063 | || mips_abi == O32_ABI)) | |
316f5878 | 12064 | mips_32bitmode = 1; |
e9670677 MR |
12065 | |
12066 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
12067 | as_bad (_("trap exception not supported at ISA 1")); | |
12068 | ||
e9670677 MR |
12069 | /* If the selected architecture includes support for ASEs, enable |
12070 | generation of code for them. */ | |
a4672219 | 12071 | if (mips_opts.mips16 == -1) |
fef14a42 | 12072 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 12073 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 12074 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
12075 | && file_mips_fp32 == 0) ? 1 : 0; |
12076 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
12077 | as_bad (_("-mfp32 used with -mips3d")); | |
12078 | ||
ffdefa66 | 12079 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 12080 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
12081 | && file_mips_fp32 == 0) ? 1 : 0; |
12082 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
12083 | as_bad (_("-mfp32 used with -mdmx")); | |
12084 | ||
12085 | if (mips_opts.ase_smartmips == -1) | |
12086 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
12087 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
12088 | as_warn (_("%s ISA does not support SmartMIPS"), |
12089 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12090 | |
74cd071d | 12091 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
12092 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
12093 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
12094 | as_warn (_("%s ISA does not support DSP ASE"), |
12095 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 12096 | |
8b082fb1 TS |
12097 | if (mips_opts.ase_dspr2 == -1) |
12098 | { | |
12099 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
12100 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
12101 | } | |
12102 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
12103 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
12104 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 12105 | |
ef2e4d86 | 12106 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
12107 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
12108 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
12109 | as_warn (_("%s ISA does not support MT ASE"), |
12110 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 12111 | |
e9670677 | 12112 | file_mips_isa = mips_opts.isa; |
a4672219 | 12113 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
12114 | file_ase_mips3d = mips_opts.ase_mips3d; |
12115 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 12116 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 12117 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 12118 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 12119 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
12120 | mips_opts.gp32 = file_mips_gp32; |
12121 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
12122 | mips_opts.soft_float = file_mips_soft_float; |
12123 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 12124 | |
ecb4347a DJ |
12125 | if (mips_flag_mdebug < 0) |
12126 | { | |
12127 | #ifdef OBJ_MAYBE_ECOFF | |
12128 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
12129 | mips_flag_mdebug = 1; | |
12130 | else | |
12131 | #endif /* OBJ_MAYBE_ECOFF */ | |
12132 | mips_flag_mdebug = 0; | |
12133 | } | |
e9670677 MR |
12134 | } |
12135 | \f | |
12136 | void | |
17a2f251 | 12137 | mips_init_after_args (void) |
252b5132 RH |
12138 | { |
12139 | /* initialize opcodes */ | |
12140 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 12141 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
12142 | } |
12143 | ||
12144 | long | |
17a2f251 | 12145 | md_pcrel_from (fixS *fixP) |
252b5132 | 12146 | { |
a7ebbfdf TS |
12147 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
12148 | switch (fixP->fx_r_type) | |
12149 | { | |
12150 | case BFD_RELOC_16_PCREL_S2: | |
12151 | case BFD_RELOC_MIPS_JMP: | |
12152 | /* Return the address of the delay slot. */ | |
12153 | return addr + 4; | |
12154 | default: | |
58ea3d6a | 12155 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
12156 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
12157 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12158 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
12159 | return addr; |
12160 | } | |
252b5132 RH |
12161 | } |
12162 | ||
252b5132 RH |
12163 | /* This is called before the symbol table is processed. In order to |
12164 | work with gcc when using mips-tfile, we must keep all local labels. | |
12165 | However, in other cases, we want to discard them. If we were | |
12166 | called with -g, but we didn't see any debugging information, it may | |
12167 | mean that gcc is smuggling debugging information through to | |
12168 | mips-tfile, in which case we must generate all local labels. */ | |
12169 | ||
12170 | void | |
17a2f251 | 12171 | mips_frob_file_before_adjust (void) |
252b5132 RH |
12172 | { |
12173 | #ifndef NO_ECOFF_DEBUGGING | |
12174 | if (ECOFF_DEBUGGING | |
12175 | && mips_debug != 0 | |
12176 | && ! ecoff_debugging_seen) | |
12177 | flag_keep_locals = 1; | |
12178 | #endif | |
12179 | } | |
12180 | ||
3b91255e | 12181 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 12182 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
12183 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
12184 | relocation operators. | |
12185 | ||
12186 | For our purposes, a %lo() expression matches a %got() or %hi() | |
12187 | expression if: | |
12188 | ||
12189 | (a) it refers to the same symbol; and | |
12190 | (b) the offset applied in the %lo() expression is no lower than | |
12191 | the offset applied in the %got() or %hi(). | |
12192 | ||
12193 | (b) allows us to cope with code like: | |
12194 | ||
12195 | lui $4,%hi(foo) | |
12196 | lh $4,%lo(foo+2)($4) | |
12197 | ||
12198 | ...which is legal on RELA targets, and has a well-defined behaviour | |
12199 | if the user knows that adding 2 to "foo" will not induce a carry to | |
12200 | the high 16 bits. | |
12201 | ||
12202 | When several %lo()s match a particular %got() or %hi(), we use the | |
12203 | following rules to distinguish them: | |
12204 | ||
12205 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
12206 | higher offsets. | |
12207 | ||
12208 | (2) %lo()s with no matching %got() or %hi() are better than those | |
12209 | that already have a matching %got() or %hi(). | |
12210 | ||
12211 | (3) later %lo()s are better than earlier %lo()s. | |
12212 | ||
12213 | These rules are applied in order. | |
12214 | ||
12215 | (1) means, among other things, that %lo()s with identical offsets are | |
12216 | chosen if they exist. | |
12217 | ||
12218 | (2) means that we won't associate several high-part relocations with | |
12219 | the same low-part relocation unless there's no alternative. Having | |
12220 | several high parts for the same low part is a GNU extension; this rule | |
12221 | allows careful users to avoid it. | |
12222 | ||
12223 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
12224 | with the last high-part relocation being at the front of the list. | |
12225 | It therefore makes sense to choose the last matching low-part | |
12226 | relocation, all other things being equal. It's also easier | |
12227 | to code that way. */ | |
252b5132 RH |
12228 | |
12229 | void | |
17a2f251 | 12230 | mips_frob_file (void) |
252b5132 RH |
12231 | { |
12232 | struct mips_hi_fixup *l; | |
35903be0 | 12233 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
12234 | |
12235 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
12236 | { | |
12237 | segment_info_type *seginfo; | |
3b91255e RS |
12238 | bfd_boolean matched_lo_p; |
12239 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 12240 | |
9c2799c2 | 12241 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 12242 | |
5919d012 RS |
12243 | /* If a GOT16 relocation turns out to be against a global symbol, |
12244 | there isn't supposed to be a matching LO. */ | |
738e5348 | 12245 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
12246 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
12247 | continue; | |
12248 | ||
12249 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
12250 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
12251 | continue; |
12252 | ||
252b5132 | 12253 | seginfo = seg_info (l->seg); |
252b5132 | 12254 | |
3b91255e RS |
12255 | /* Set HI_POS to the position of this relocation in the chain. |
12256 | Set LO_POS to the position of the chosen low-part relocation. | |
12257 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
12258 | relocation that matches an immediately-preceding high-part | |
12259 | relocation. */ | |
12260 | hi_pos = NULL; | |
12261 | lo_pos = NULL; | |
12262 | matched_lo_p = FALSE; | |
738e5348 | 12263 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 12264 | |
3b91255e RS |
12265 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
12266 | { | |
12267 | if (*pos == l->fixp) | |
12268 | hi_pos = pos; | |
12269 | ||
35903be0 | 12270 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 12271 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
12272 | && (*pos)->fx_offset >= l->fixp->fx_offset |
12273 | && (lo_pos == NULL | |
12274 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
12275 | || (!matched_lo_p | |
12276 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
12277 | lo_pos = pos; | |
12278 | ||
12279 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
12280 | && fixup_has_matching_lo_p (*pos)); | |
12281 | } | |
12282 | ||
12283 | /* If we found a match, remove the high-part relocation from its | |
12284 | current position and insert it before the low-part relocation. | |
12285 | Make the offsets match so that fixup_has_matching_lo_p() | |
12286 | will return true. | |
12287 | ||
12288 | We don't warn about unmatched high-part relocations since some | |
12289 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
12290 | instructions. */ | |
12291 | if (lo_pos != NULL) | |
12292 | { | |
12293 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
12294 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 12295 | { |
3b91255e RS |
12296 | *hi_pos = l->fixp->fx_next; |
12297 | l->fixp->fx_next = *lo_pos; | |
12298 | *lo_pos = l->fixp; | |
252b5132 | 12299 | } |
252b5132 RH |
12300 | } |
12301 | } | |
12302 | } | |
12303 | ||
3e722fb5 | 12304 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 12305 | We have to prevent gas from dropping them. */ |
252b5132 | 12306 | |
252b5132 | 12307 | int |
17a2f251 | 12308 | mips_force_relocation (fixS *fixp) |
252b5132 | 12309 | { |
ae6063d4 | 12310 | if (generic_force_reloc (fixp)) |
252b5132 RH |
12311 | return 1; |
12312 | ||
f6688943 TS |
12313 | if (HAVE_NEWABI |
12314 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
12315 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
12316 | || hi16_reloc_p (fixp->fx_r_type) |
12317 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
12318 | return 1; |
12319 | ||
3e722fb5 | 12320 | return 0; |
252b5132 RH |
12321 | } |
12322 | ||
12323 | /* Apply a fixup to the object file. */ | |
12324 | ||
94f592af | 12325 | void |
55cf6793 | 12326 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12327 | { |
874e8986 | 12328 | bfd_byte *buf; |
98aa84af | 12329 | long insn; |
a7ebbfdf | 12330 | reloc_howto_type *howto; |
252b5132 | 12331 | |
a7ebbfdf TS |
12332 | /* We ignore generic BFD relocations we don't know about. */ |
12333 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
12334 | if (! howto) | |
12335 | return; | |
65551fa4 | 12336 | |
9c2799c2 | 12337 | gas_assert (fixP->fx_size == 4 |
252b5132 RH |
12338 | || fixP->fx_r_type == BFD_RELOC_16 |
12339 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
12340 | || fixP->fx_r_type == BFD_RELOC_CTOR |
12341 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 12342 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
741d6ea8 JM |
12343 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
12344 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 12345 | |
a7ebbfdf | 12346 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 12347 | |
9c2799c2 | 12348 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
12349 | |
12350 | /* Don't treat parts of a composite relocation as done. There are two | |
12351 | reasons for this: | |
12352 | ||
12353 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
12354 | should nevertheless be emitted if the first part is. | |
12355 | ||
12356 | (2) In normal usage, composite relocations are never assembly-time | |
12357 | constants. The easiest way of dealing with the pathological | |
12358 | exceptions is to generate a relocation against STN_UNDEF and | |
12359 | leave everything up to the linker. */ | |
3994f87e | 12360 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
12361 | fixP->fx_done = 1; |
12362 | ||
12363 | switch (fixP->fx_r_type) | |
12364 | { | |
3f98094e DJ |
12365 | case BFD_RELOC_MIPS_TLS_GD: |
12366 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
12367 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
12368 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
12369 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
12370 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
12371 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
12372 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
12373 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
12374 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12375 | /* fall through */ | |
12376 | ||
252b5132 | 12377 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
12378 | case BFD_RELOC_MIPS_SHIFT5: |
12379 | case BFD_RELOC_MIPS_SHIFT6: | |
12380 | case BFD_RELOC_MIPS_GOT_DISP: | |
12381 | case BFD_RELOC_MIPS_GOT_PAGE: | |
12382 | case BFD_RELOC_MIPS_GOT_OFST: | |
12383 | case BFD_RELOC_MIPS_SUB: | |
12384 | case BFD_RELOC_MIPS_INSERT_A: | |
12385 | case BFD_RELOC_MIPS_INSERT_B: | |
12386 | case BFD_RELOC_MIPS_DELETE: | |
12387 | case BFD_RELOC_MIPS_HIGHEST: | |
12388 | case BFD_RELOC_MIPS_HIGHER: | |
12389 | case BFD_RELOC_MIPS_SCN_DISP: | |
12390 | case BFD_RELOC_MIPS_REL16: | |
12391 | case BFD_RELOC_MIPS_RELGOT: | |
12392 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
12393 | case BFD_RELOC_HI16: |
12394 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 12395 | case BFD_RELOC_GPREL16: |
252b5132 RH |
12396 | case BFD_RELOC_MIPS_LITERAL: |
12397 | case BFD_RELOC_MIPS_CALL16: | |
12398 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 12399 | case BFD_RELOC_GPREL32: |
252b5132 RH |
12400 | case BFD_RELOC_MIPS_GOT_HI16: |
12401 | case BFD_RELOC_MIPS_GOT_LO16: | |
12402 | case BFD_RELOC_MIPS_CALL_HI16: | |
12403 | case BFD_RELOC_MIPS_CALL_LO16: | |
12404 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
12405 | case BFD_RELOC_MIPS16_GOT16: |
12406 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
12407 | case BFD_RELOC_MIPS16_HI16: |
12408 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 12409 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 12410 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
12411 | break; |
12412 | ||
252b5132 RH |
12413 | case BFD_RELOC_64: |
12414 | /* This is handled like BFD_RELOC_32, but we output a sign | |
12415 | extended value if we are only 32 bits. */ | |
3e722fb5 | 12416 | if (fixP->fx_done) |
252b5132 RH |
12417 | { |
12418 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 12419 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
12420 | else |
12421 | { | |
a7ebbfdf | 12422 | valueT hiv; |
252b5132 | 12423 | |
a7ebbfdf | 12424 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
12425 | hiv = 0xffffffff; |
12426 | else | |
12427 | hiv = 0; | |
b215186b | 12428 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 12429 | *valP, 4); |
b215186b | 12430 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 12431 | hiv, 4); |
252b5132 RH |
12432 | } |
12433 | } | |
12434 | break; | |
12435 | ||
056350c6 | 12436 | case BFD_RELOC_RVA: |
252b5132 | 12437 | case BFD_RELOC_32: |
252b5132 RH |
12438 | case BFD_RELOC_16: |
12439 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
12440 | value now. This can happen if we have a .word which is not |
12441 | resolved when it appears but is later defined. */ | |
252b5132 | 12442 | if (fixP->fx_done) |
54f4ddb3 | 12443 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
12444 | break; |
12445 | ||
12446 | case BFD_RELOC_LO16: | |
d6f16593 | 12447 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
12448 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
12449 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
12450 | /* When handling an embedded PIC switch statement, we can wind |
12451 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
12452 | if (fixP->fx_done) | |
12453 | { | |
a7ebbfdf | 12454 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
12455 | as_bad_where (fixP->fx_file, fixP->fx_line, |
12456 | _("relocation overflow")); | |
252b5132 RH |
12457 | if (target_big_endian) |
12458 | buf += 2; | |
2132e3a3 | 12459 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
12460 | } |
12461 | break; | |
12462 | ||
12463 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 12464 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 12465 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 12466 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 12467 | |
54f4ddb3 TS |
12468 | /* We need to save the bits in the instruction since fixup_segment() |
12469 | might be deleting the relocation entry (i.e., a branch within | |
12470 | the current segment). */ | |
a7ebbfdf | 12471 | if (! fixP->fx_done) |
bb2d6cd7 | 12472 | break; |
252b5132 | 12473 | |
54f4ddb3 | 12474 | /* Update old instruction data. */ |
252b5132 RH |
12475 | if (target_big_endian) |
12476 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
12477 | else | |
12478 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
12479 | ||
a7ebbfdf TS |
12480 | if (*valP + 0x20000 <= 0x3ffff) |
12481 | { | |
12482 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 12483 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12484 | } |
12485 | else if (mips_pic == NO_PIC | |
12486 | && fixP->fx_done | |
12487 | && fixP->fx_frag->fr_address >= text_section->vma | |
12488 | && (fixP->fx_frag->fr_address | |
587aac4e | 12489 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
12490 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
12491 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
12492 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
12493 | { |
12494 | /* The branch offset is too large. If this is an | |
12495 | unconditional branch, and we are not generating PIC code, | |
12496 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
12497 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
12498 | insn = 0x0c000000; /* jal */ | |
252b5132 | 12499 | else |
a7ebbfdf TS |
12500 | insn = 0x08000000; /* j */ |
12501 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
12502 | fixP->fx_done = 0; | |
12503 | fixP->fx_addsy = section_symbol (text_section); | |
12504 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 12505 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
12506 | } |
12507 | else | |
12508 | { | |
12509 | /* If we got here, we have branch-relaxation disabled, | |
12510 | and there's nothing we can do to fix this instruction | |
12511 | without turning it into a longer sequence. */ | |
12512 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
12513 | _("Branch out of range")); | |
252b5132 | 12514 | } |
252b5132 RH |
12515 | break; |
12516 | ||
12517 | case BFD_RELOC_VTABLE_INHERIT: | |
12518 | fixP->fx_done = 0; | |
12519 | if (fixP->fx_addsy | |
12520 | && !S_IS_DEFINED (fixP->fx_addsy) | |
12521 | && !S_IS_WEAK (fixP->fx_addsy)) | |
12522 | S_SET_WEAK (fixP->fx_addsy); | |
12523 | break; | |
12524 | ||
12525 | case BFD_RELOC_VTABLE_ENTRY: | |
12526 | fixP->fx_done = 0; | |
12527 | break; | |
12528 | ||
12529 | default: | |
12530 | internalError (); | |
12531 | } | |
a7ebbfdf TS |
12532 | |
12533 | /* Remember value for tc_gen_reloc. */ | |
12534 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12535 | } |
12536 | ||
252b5132 | 12537 | static symbolS * |
17a2f251 | 12538 | get_symbol (void) |
252b5132 RH |
12539 | { |
12540 | int c; | |
12541 | char *name; | |
12542 | symbolS *p; | |
12543 | ||
12544 | name = input_line_pointer; | |
12545 | c = get_symbol_end (); | |
12546 | p = (symbolS *) symbol_find_or_make (name); | |
12547 | *input_line_pointer = c; | |
12548 | return p; | |
12549 | } | |
12550 | ||
742a56fe RS |
12551 | /* Align the current frag to a given power of two. If a particular |
12552 | fill byte should be used, FILL points to an integer that contains | |
12553 | that byte, otherwise FILL is null. | |
12554 | ||
12555 | The MIPS assembler also automatically adjusts any preceding | |
12556 | label. */ | |
252b5132 RH |
12557 | |
12558 | static void | |
742a56fe | 12559 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 12560 | { |
7d10b47d | 12561 | mips_emit_delays (); |
742a56fe RS |
12562 | mips_record_mips16_mode (); |
12563 | if (fill == NULL && subseg_text_p (now_seg)) | |
12564 | frag_align_code (to, 0); | |
12565 | else | |
12566 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
12567 | record_alignment (now_seg, to); |
12568 | if (label != NULL) | |
12569 | { | |
9c2799c2 | 12570 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 12571 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12572 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12573 | } | |
12574 | } | |
12575 | ||
12576 | /* Align to a given power of two. .align 0 turns off the automatic | |
12577 | alignment used by the data creating pseudo-ops. */ | |
12578 | ||
12579 | static void | |
17a2f251 | 12580 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12581 | { |
742a56fe | 12582 | int temp, fill_value, *fill_ptr; |
49954fb4 | 12583 | long max_alignment = 28; |
252b5132 | 12584 | |
54f4ddb3 | 12585 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12586 | to the aligned address. |
54f4ddb3 | 12587 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12588 | a .align pseudo instruction. |
54f4ddb3 | 12589 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12590 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12591 | We don't. */ |
252b5132 RH |
12592 | |
12593 | temp = get_absolute_expression (); | |
12594 | if (temp > max_alignment) | |
12595 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12596 | else if (temp < 0) | |
12597 | { | |
12598 | as_warn (_("Alignment negative: 0 assumed.")); | |
12599 | temp = 0; | |
12600 | } | |
12601 | if (*input_line_pointer == ',') | |
12602 | { | |
f9419b05 | 12603 | ++input_line_pointer; |
742a56fe RS |
12604 | fill_value = get_absolute_expression (); |
12605 | fill_ptr = &fill_value; | |
252b5132 RH |
12606 | } |
12607 | else | |
742a56fe | 12608 | fill_ptr = 0; |
252b5132 RH |
12609 | if (temp) |
12610 | { | |
a8dbcb85 TS |
12611 | segment_info_type *si = seg_info (now_seg); |
12612 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12613 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12614 | auto_align = 1; |
742a56fe | 12615 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
12616 | } |
12617 | else | |
12618 | { | |
12619 | auto_align = 0; | |
12620 | } | |
12621 | ||
12622 | demand_empty_rest_of_line (); | |
12623 | } | |
12624 | ||
252b5132 | 12625 | static void |
17a2f251 | 12626 | s_change_sec (int sec) |
252b5132 RH |
12627 | { |
12628 | segT seg; | |
12629 | ||
252b5132 RH |
12630 | #ifdef OBJ_ELF |
12631 | /* The ELF backend needs to know that we are changing sections, so | |
12632 | that .previous works correctly. We could do something like check | |
b6ff326e | 12633 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12634 | as it would not be appropriate to use it in the section changing |
12635 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12636 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12637 | if (IS_ELF) |
12638 | obj_elf_section_change_hook (); | |
252b5132 RH |
12639 | #endif |
12640 | ||
7d10b47d | 12641 | mips_emit_delays (); |
6a32d874 | 12642 | |
252b5132 RH |
12643 | switch (sec) |
12644 | { | |
12645 | case 't': | |
12646 | s_text (0); | |
12647 | break; | |
12648 | case 'd': | |
12649 | s_data (0); | |
12650 | break; | |
12651 | case 'b': | |
12652 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12653 | demand_empty_rest_of_line (); | |
12654 | break; | |
12655 | ||
12656 | case 'r': | |
4d0d148d TS |
12657 | seg = subseg_new (RDATA_SECTION_NAME, |
12658 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12659 | if (IS_ELF) |
252b5132 | 12660 | { |
4d0d148d TS |
12661 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12662 | | SEC_READONLY | SEC_RELOC | |
12663 | | SEC_DATA)); | |
c41e87e3 | 12664 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12665 | record_alignment (seg, 4); |
252b5132 | 12666 | } |
4d0d148d | 12667 | demand_empty_rest_of_line (); |
252b5132 RH |
12668 | break; |
12669 | ||
12670 | case 's': | |
4d0d148d | 12671 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12672 | if (IS_ELF) |
252b5132 | 12673 | { |
4d0d148d TS |
12674 | bfd_set_section_flags (stdoutput, seg, |
12675 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 12676 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 12677 | record_alignment (seg, 4); |
252b5132 | 12678 | } |
4d0d148d TS |
12679 | demand_empty_rest_of_line (); |
12680 | break; | |
252b5132 RH |
12681 | } |
12682 | ||
12683 | auto_align = 1; | |
12684 | } | |
b34976b6 | 12685 | |
cca86cc8 | 12686 | void |
17a2f251 | 12687 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12688 | { |
7ed4a06a | 12689 | #ifdef OBJ_ELF |
cca86cc8 SC |
12690 | char *section_name; |
12691 | char c; | |
684022ea | 12692 | char next_c = 0; |
cca86cc8 SC |
12693 | int section_type; |
12694 | int section_flag; | |
12695 | int section_entry_size; | |
12696 | int section_alignment; | |
b34976b6 | 12697 | |
f43abd2b | 12698 | if (!IS_ELF) |
7ed4a06a TS |
12699 | return; |
12700 | ||
cca86cc8 SC |
12701 | section_name = input_line_pointer; |
12702 | c = get_symbol_end (); | |
a816d1ed AO |
12703 | if (c) |
12704 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12705 | |
4cf0dd0d TS |
12706 | /* Do we have .section Name<,"flags">? */ |
12707 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12708 | { |
4cf0dd0d TS |
12709 | /* just after name is now '\0'. */ |
12710 | *input_line_pointer = c; | |
cca86cc8 SC |
12711 | input_line_pointer = section_name; |
12712 | obj_elf_section (ignore); | |
12713 | return; | |
12714 | } | |
12715 | input_line_pointer++; | |
12716 | ||
12717 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12718 | if (c == ',') | |
12719 | section_type = get_absolute_expression (); | |
12720 | else | |
12721 | section_type = 0; | |
12722 | if (*input_line_pointer++ == ',') | |
12723 | section_flag = get_absolute_expression (); | |
12724 | else | |
12725 | section_flag = 0; | |
12726 | if (*input_line_pointer++ == ',') | |
12727 | section_entry_size = get_absolute_expression (); | |
12728 | else | |
12729 | section_entry_size = 0; | |
12730 | if (*input_line_pointer++ == ',') | |
12731 | section_alignment = get_absolute_expression (); | |
12732 | else | |
12733 | section_alignment = 0; | |
87975d2a AM |
12734 | /* FIXME: really ignore? */ |
12735 | (void) section_alignment; | |
cca86cc8 | 12736 | |
a816d1ed AO |
12737 | section_name = xstrdup (section_name); |
12738 | ||
8ab8a5c8 RS |
12739 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12740 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12741 | traditionally had to fall back on the more common @progbits instead. | |
12742 | ||
12743 | There's nothing really harmful in this, since bfd will correct | |
12744 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12745 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12746 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12747 | ||
12748 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12749 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12750 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12751 | generic type-checking code. */ | |
12752 | if (section_type == SHT_MIPS_DWARF) | |
12753 | section_type = SHT_PROGBITS; | |
12754 | ||
cca86cc8 SC |
12755 | obj_elf_change_section (section_name, section_type, section_flag, |
12756 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12757 | |
12758 | if (now_seg->name != section_name) | |
12759 | free (section_name); | |
7ed4a06a | 12760 | #endif /* OBJ_ELF */ |
cca86cc8 | 12761 | } |
252b5132 RH |
12762 | |
12763 | void | |
17a2f251 | 12764 | mips_enable_auto_align (void) |
252b5132 RH |
12765 | { |
12766 | auto_align = 1; | |
12767 | } | |
12768 | ||
12769 | static void | |
17a2f251 | 12770 | s_cons (int log_size) |
252b5132 | 12771 | { |
a8dbcb85 TS |
12772 | segment_info_type *si = seg_info (now_seg); |
12773 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12774 | symbolS *label; |
12775 | ||
a8dbcb85 | 12776 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12777 | mips_emit_delays (); |
252b5132 RH |
12778 | if (log_size > 0 && auto_align) |
12779 | mips_align (log_size, 0, label); | |
12780 | mips_clear_insn_labels (); | |
12781 | cons (1 << log_size); | |
12782 | } | |
12783 | ||
12784 | static void | |
17a2f251 | 12785 | s_float_cons (int type) |
252b5132 | 12786 | { |
a8dbcb85 TS |
12787 | segment_info_type *si = seg_info (now_seg); |
12788 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12789 | symbolS *label; |
12790 | ||
a8dbcb85 | 12791 | label = l != NULL ? l->label : NULL; |
252b5132 | 12792 | |
7d10b47d | 12793 | mips_emit_delays (); |
252b5132 RH |
12794 | |
12795 | if (auto_align) | |
49309057 ILT |
12796 | { |
12797 | if (type == 'd') | |
12798 | mips_align (3, 0, label); | |
12799 | else | |
12800 | mips_align (2, 0, label); | |
12801 | } | |
252b5132 RH |
12802 | |
12803 | mips_clear_insn_labels (); | |
12804 | ||
12805 | float_cons (type); | |
12806 | } | |
12807 | ||
12808 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12809 | permitted to say | |
12810 | .globl foo .text | |
12811 | where foo is an undefined symbol, to mean that foo should be | |
12812 | considered to be the address of a function. */ | |
12813 | ||
12814 | static void | |
17a2f251 | 12815 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12816 | { |
12817 | char *name; | |
12818 | int c; | |
12819 | symbolS *symbolP; | |
12820 | flagword flag; | |
12821 | ||
8a06b769 | 12822 | do |
252b5132 | 12823 | { |
8a06b769 | 12824 | name = input_line_pointer; |
252b5132 | 12825 | c = get_symbol_end (); |
8a06b769 TS |
12826 | symbolP = symbol_find_or_make (name); |
12827 | S_SET_EXTERNAL (symbolP); | |
12828 | ||
252b5132 | 12829 | *input_line_pointer = c; |
8a06b769 | 12830 | SKIP_WHITESPACE (); |
252b5132 | 12831 | |
8a06b769 TS |
12832 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12833 | being a function is apparently labelled as being an object. */ | |
12834 | flag = BSF_OBJECT; | |
252b5132 | 12835 | |
8a06b769 TS |
12836 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12837 | && (*input_line_pointer != ',')) | |
12838 | { | |
12839 | char *secname; | |
12840 | asection *sec; | |
12841 | ||
12842 | secname = input_line_pointer; | |
12843 | c = get_symbol_end (); | |
12844 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12845 | if (sec == NULL) | |
12846 | as_bad (_("%s: no such section"), secname); | |
12847 | *input_line_pointer = c; | |
12848 | ||
12849 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12850 | flag = BSF_FUNCTION; | |
12851 | } | |
12852 | ||
12853 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12854 | ||
12855 | c = *input_line_pointer; | |
12856 | if (c == ',') | |
12857 | { | |
12858 | input_line_pointer++; | |
12859 | SKIP_WHITESPACE (); | |
12860 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12861 | c = '\n'; | |
12862 | } | |
12863 | } | |
12864 | while (c == ','); | |
252b5132 | 12865 | |
252b5132 RH |
12866 | demand_empty_rest_of_line (); |
12867 | } | |
12868 | ||
12869 | static void | |
17a2f251 | 12870 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12871 | { |
12872 | char *opt; | |
12873 | char c; | |
12874 | ||
12875 | opt = input_line_pointer; | |
12876 | c = get_symbol_end (); | |
12877 | ||
12878 | if (*opt == 'O') | |
12879 | { | |
12880 | /* FIXME: What does this mean? */ | |
12881 | } | |
12882 | else if (strncmp (opt, "pic", 3) == 0) | |
12883 | { | |
12884 | int i; | |
12885 | ||
12886 | i = atoi (opt + 3); | |
12887 | if (i == 0) | |
12888 | mips_pic = NO_PIC; | |
12889 | else if (i == 2) | |
143d77c5 | 12890 | { |
252b5132 | 12891 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12892 | mips_abicalls = TRUE; |
12893 | } | |
252b5132 RH |
12894 | else |
12895 | as_bad (_(".option pic%d not supported"), i); | |
12896 | ||
4d0d148d | 12897 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12898 | { |
12899 | if (g_switch_seen && g_switch_value != 0) | |
12900 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12901 | g_switch_value = 0; | |
12902 | bfd_set_gp_size (stdoutput, 0); | |
12903 | } | |
12904 | } | |
12905 | else | |
12906 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12907 | ||
12908 | *input_line_pointer = c; | |
12909 | demand_empty_rest_of_line (); | |
12910 | } | |
12911 | ||
12912 | /* This structure is used to hold a stack of .set values. */ | |
12913 | ||
e972090a NC |
12914 | struct mips_option_stack |
12915 | { | |
252b5132 RH |
12916 | struct mips_option_stack *next; |
12917 | struct mips_set_options options; | |
12918 | }; | |
12919 | ||
12920 | static struct mips_option_stack *mips_opts_stack; | |
12921 | ||
12922 | /* Handle the .set pseudo-op. */ | |
12923 | ||
12924 | static void | |
17a2f251 | 12925 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12926 | { |
12927 | char *name = input_line_pointer, ch; | |
12928 | ||
12929 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12930 | ++input_line_pointer; |
252b5132 RH |
12931 | ch = *input_line_pointer; |
12932 | *input_line_pointer = '\0'; | |
12933 | ||
12934 | if (strcmp (name, "reorder") == 0) | |
12935 | { | |
7d10b47d RS |
12936 | if (mips_opts.noreorder) |
12937 | end_noreorder (); | |
252b5132 RH |
12938 | } |
12939 | else if (strcmp (name, "noreorder") == 0) | |
12940 | { | |
7d10b47d RS |
12941 | if (!mips_opts.noreorder) |
12942 | start_noreorder (); | |
252b5132 | 12943 | } |
741fe287 MR |
12944 | else if (strncmp (name, "at=", 3) == 0) |
12945 | { | |
12946 | char *s = name + 3; | |
12947 | ||
12948 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
12949 | as_bad (_("Unrecognized register name `%s'"), s); | |
12950 | } | |
252b5132 RH |
12951 | else if (strcmp (name, "at") == 0) |
12952 | { | |
741fe287 | 12953 | mips_opts.at = ATREG; |
252b5132 RH |
12954 | } |
12955 | else if (strcmp (name, "noat") == 0) | |
12956 | { | |
741fe287 | 12957 | mips_opts.at = ZERO; |
252b5132 RH |
12958 | } |
12959 | else if (strcmp (name, "macro") == 0) | |
12960 | { | |
12961 | mips_opts.warn_about_macros = 0; | |
12962 | } | |
12963 | else if (strcmp (name, "nomacro") == 0) | |
12964 | { | |
12965 | if (mips_opts.noreorder == 0) | |
12966 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12967 | mips_opts.warn_about_macros = 1; | |
12968 | } | |
12969 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12970 | { | |
12971 | mips_opts.nomove = 0; | |
12972 | } | |
12973 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12974 | { | |
12975 | mips_opts.nomove = 1; | |
12976 | } | |
12977 | else if (strcmp (name, "bopt") == 0) | |
12978 | { | |
12979 | mips_opts.nobopt = 0; | |
12980 | } | |
12981 | else if (strcmp (name, "nobopt") == 0) | |
12982 | { | |
12983 | mips_opts.nobopt = 1; | |
12984 | } | |
ad3fea08 TS |
12985 | else if (strcmp (name, "gp=default") == 0) |
12986 | mips_opts.gp32 = file_mips_gp32; | |
12987 | else if (strcmp (name, "gp=32") == 0) | |
12988 | mips_opts.gp32 = 1; | |
12989 | else if (strcmp (name, "gp=64") == 0) | |
12990 | { | |
12991 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 12992 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
12993 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
12994 | mips_opts.gp32 = 0; | |
12995 | } | |
12996 | else if (strcmp (name, "fp=default") == 0) | |
12997 | mips_opts.fp32 = file_mips_fp32; | |
12998 | else if (strcmp (name, "fp=32") == 0) | |
12999 | mips_opts.fp32 = 1; | |
13000 | else if (strcmp (name, "fp=64") == 0) | |
13001 | { | |
13002 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 13003 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
13004 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13005 | mips_opts.fp32 = 0; | |
13006 | } | |
037b32b9 AN |
13007 | else if (strcmp (name, "softfloat") == 0) |
13008 | mips_opts.soft_float = 1; | |
13009 | else if (strcmp (name, "hardfloat") == 0) | |
13010 | mips_opts.soft_float = 0; | |
13011 | else if (strcmp (name, "singlefloat") == 0) | |
13012 | mips_opts.single_float = 1; | |
13013 | else if (strcmp (name, "doublefloat") == 0) | |
13014 | mips_opts.single_float = 0; | |
252b5132 RH |
13015 | else if (strcmp (name, "mips16") == 0 |
13016 | || strcmp (name, "MIPS-16") == 0) | |
13017 | mips_opts.mips16 = 1; | |
13018 | else if (strcmp (name, "nomips16") == 0 | |
13019 | || strcmp (name, "noMIPS-16") == 0) | |
13020 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
13021 | else if (strcmp (name, "smartmips") == 0) |
13022 | { | |
ad3fea08 | 13023 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 13024 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
13025 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13026 | mips_opts.ase_smartmips = 1; | |
13027 | } | |
13028 | else if (strcmp (name, "nosmartmips") == 0) | |
13029 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
13030 | else if (strcmp (name, "mips3d") == 0) |
13031 | mips_opts.ase_mips3d = 1; | |
13032 | else if (strcmp (name, "nomips3d") == 0) | |
13033 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
13034 | else if (strcmp (name, "mdmx") == 0) |
13035 | mips_opts.ase_mdmx = 1; | |
13036 | else if (strcmp (name, "nomdmx") == 0) | |
13037 | mips_opts.ase_mdmx = 0; | |
74cd071d | 13038 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
13039 | { |
13040 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 13041 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
13042 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13043 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 13044 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 13045 | } |
74cd071d | 13046 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
13047 | { |
13048 | mips_opts.ase_dsp = 0; | |
13049 | mips_opts.ase_dspr2 = 0; | |
13050 | } | |
13051 | else if (strcmp (name, "dspr2") == 0) | |
13052 | { | |
13053 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 13054 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
13055 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13056 | mips_opts.ase_dspr2 = 1; | |
13057 | mips_opts.ase_dsp = 1; | |
13058 | } | |
13059 | else if (strcmp (name, "nodspr2") == 0) | |
13060 | { | |
13061 | mips_opts.ase_dspr2 = 0; | |
13062 | mips_opts.ase_dsp = 0; | |
13063 | } | |
ef2e4d86 | 13064 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
13065 | { |
13066 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 13067 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
13068 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
13069 | mips_opts.ase_mt = 1; | |
13070 | } | |
ef2e4d86 CF |
13071 | else if (strcmp (name, "nomt") == 0) |
13072 | mips_opts.ase_mt = 0; | |
1a2c1fad | 13073 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 13074 | { |
af7ee8bf | 13075 | int reset = 0; |
252b5132 | 13076 | |
1a2c1fad CD |
13077 | /* Permit the user to change the ISA and architecture on the fly. |
13078 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 13079 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
13080 | { |
13081 | reset = 1; | |
13082 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 13083 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
13084 | } |
13085 | else if (strncmp (name, "arch=", 5) == 0) | |
13086 | { | |
13087 | const struct mips_cpu_info *p; | |
13088 | ||
13089 | p = mips_parse_cpu("internal use", name + 5); | |
13090 | if (!p) | |
13091 | as_bad (_("unknown architecture %s"), name + 5); | |
13092 | else | |
13093 | { | |
13094 | mips_opts.arch = p->cpu; | |
13095 | mips_opts.isa = p->isa; | |
13096 | } | |
13097 | } | |
81a21e38 TS |
13098 | else if (strncmp (name, "mips", 4) == 0) |
13099 | { | |
13100 | const struct mips_cpu_info *p; | |
13101 | ||
13102 | p = mips_parse_cpu("internal use", name); | |
13103 | if (!p) | |
13104 | as_bad (_("unknown ISA level %s"), name + 4); | |
13105 | else | |
13106 | { | |
13107 | mips_opts.arch = p->cpu; | |
13108 | mips_opts.isa = p->isa; | |
13109 | } | |
13110 | } | |
af7ee8bf | 13111 | else |
81a21e38 | 13112 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
13113 | |
13114 | switch (mips_opts.isa) | |
98d3f06f KH |
13115 | { |
13116 | case 0: | |
98d3f06f | 13117 | break; |
af7ee8bf CD |
13118 | case ISA_MIPS1: |
13119 | case ISA_MIPS2: | |
13120 | case ISA_MIPS32: | |
13121 | case ISA_MIPS32R2: | |
98d3f06f KH |
13122 | mips_opts.gp32 = 1; |
13123 | mips_opts.fp32 = 1; | |
13124 | break; | |
af7ee8bf CD |
13125 | case ISA_MIPS3: |
13126 | case ISA_MIPS4: | |
13127 | case ISA_MIPS5: | |
13128 | case ISA_MIPS64: | |
5f74bc13 | 13129 | case ISA_MIPS64R2: |
98d3f06f KH |
13130 | mips_opts.gp32 = 0; |
13131 | mips_opts.fp32 = 0; | |
13132 | break; | |
13133 | default: | |
13134 | as_bad (_("unknown ISA level %s"), name + 4); | |
13135 | break; | |
13136 | } | |
af7ee8bf | 13137 | if (reset) |
98d3f06f | 13138 | { |
af7ee8bf CD |
13139 | mips_opts.gp32 = file_mips_gp32; |
13140 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 13141 | } |
252b5132 RH |
13142 | } |
13143 | else if (strcmp (name, "autoextend") == 0) | |
13144 | mips_opts.noautoextend = 0; | |
13145 | else if (strcmp (name, "noautoextend") == 0) | |
13146 | mips_opts.noautoextend = 1; | |
13147 | else if (strcmp (name, "push") == 0) | |
13148 | { | |
13149 | struct mips_option_stack *s; | |
13150 | ||
13151 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
13152 | s->next = mips_opts_stack; | |
13153 | s->options = mips_opts; | |
13154 | mips_opts_stack = s; | |
13155 | } | |
13156 | else if (strcmp (name, "pop") == 0) | |
13157 | { | |
13158 | struct mips_option_stack *s; | |
13159 | ||
13160 | s = mips_opts_stack; | |
13161 | if (s == NULL) | |
13162 | as_bad (_(".set pop with no .set push")); | |
13163 | else | |
13164 | { | |
13165 | /* If we're changing the reorder mode we need to handle | |
13166 | delay slots correctly. */ | |
13167 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 13168 | start_noreorder (); |
252b5132 | 13169 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 13170 | end_noreorder (); |
252b5132 RH |
13171 | |
13172 | mips_opts = s->options; | |
13173 | mips_opts_stack = s->next; | |
13174 | free (s); | |
13175 | } | |
13176 | } | |
aed1a261 RS |
13177 | else if (strcmp (name, "sym32") == 0) |
13178 | mips_opts.sym32 = TRUE; | |
13179 | else if (strcmp (name, "nosym32") == 0) | |
13180 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
13181 | else if (strchr (name, ',')) |
13182 | { | |
13183 | /* Generic ".set" directive; use the generic handler. */ | |
13184 | *input_line_pointer = ch; | |
13185 | input_line_pointer = name; | |
13186 | s_set (0); | |
13187 | return; | |
13188 | } | |
252b5132 RH |
13189 | else |
13190 | { | |
13191 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
13192 | } | |
13193 | *input_line_pointer = ch; | |
13194 | demand_empty_rest_of_line (); | |
13195 | } | |
13196 | ||
13197 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
13198 | .option pic2. It means to generate SVR4 PIC calls. */ | |
13199 | ||
13200 | static void | |
17a2f251 | 13201 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13202 | { |
13203 | mips_pic = SVR4_PIC; | |
143d77c5 | 13204 | mips_abicalls = TRUE; |
4d0d148d TS |
13205 | |
13206 | if (g_switch_seen && g_switch_value != 0) | |
13207 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
13208 | g_switch_value = 0; | |
13209 | ||
252b5132 RH |
13210 | bfd_set_gp_size (stdoutput, 0); |
13211 | demand_empty_rest_of_line (); | |
13212 | } | |
13213 | ||
13214 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
13215 | PIC code. It sets the $gp register for the function based on the | |
13216 | function address, which is in the register named in the argument. | |
13217 | This uses a relocation against _gp_disp, which is handled specially | |
13218 | by the linker. The result is: | |
13219 | lui $gp,%hi(_gp_disp) | |
13220 | addiu $gp,$gp,%lo(_gp_disp) | |
13221 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
13222 | The .cpload argument is normally $25 == $t9. |
13223 | ||
13224 | The -mno-shared option changes this to: | |
bbe506e8 TS |
13225 | lui $gp,%hi(__gnu_local_gp) |
13226 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
13227 | and the argument is ignored. This saves an instruction, but the |
13228 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
13229 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
13230 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
13231 | |
13232 | static void | |
17a2f251 | 13233 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13234 | { |
13235 | expressionS ex; | |
aa6975fb ILT |
13236 | int reg; |
13237 | int in_shared; | |
252b5132 | 13238 | |
6478892d TS |
13239 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
13240 | .cpload is ignored. */ | |
13241 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
13242 | { |
13243 | s_ignore (0); | |
13244 | return; | |
13245 | } | |
13246 | ||
d3ecfc59 | 13247 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
13248 | if (mips_opts.noreorder == 0) |
13249 | as_warn (_(".cpload not in noreorder section")); | |
13250 | ||
aa6975fb ILT |
13251 | reg = tc_get_register (0); |
13252 | ||
13253 | /* If we need to produce a 64-bit address, we are better off using | |
13254 | the default instruction sequence. */ | |
aed1a261 | 13255 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 13256 | |
252b5132 | 13257 | ex.X_op = O_symbol; |
bbe506e8 TS |
13258 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
13259 | "__gnu_local_gp"); | |
252b5132 RH |
13260 | ex.X_op_symbol = NULL; |
13261 | ex.X_add_number = 0; | |
13262 | ||
13263 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 13264 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 13265 | |
584892a6 | 13266 | macro_start (); |
67c0d1eb RS |
13267 | macro_build_lui (&ex, mips_gp_register); |
13268 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 13269 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
13270 | if (in_shared) |
13271 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
13272 | mips_gp_register, reg); | |
584892a6 | 13273 | macro_end (); |
252b5132 RH |
13274 | |
13275 | demand_empty_rest_of_line (); | |
13276 | } | |
13277 | ||
6478892d TS |
13278 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
13279 | .cpsetup $reg1, offset|$reg2, label | |
13280 | ||
13281 | If offset is given, this results in: | |
13282 | sd $gp, offset($sp) | |
956cd1d6 | 13283 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13284 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13285 | daddu $gp, $gp, $reg1 | |
6478892d TS |
13286 | |
13287 | If $reg2 is given, this results in: | |
13288 | daddu $reg2, $gp, $0 | |
956cd1d6 | 13289 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
13290 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
13291 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
13292 | $reg1 is normally $25 == $t9. |
13293 | ||
13294 | The -mno-shared option replaces the last three instructions with | |
13295 | lui $gp,%hi(_gp) | |
54f4ddb3 | 13296 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 13297 | |
6478892d | 13298 | static void |
17a2f251 | 13299 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13300 | { |
13301 | expressionS ex_off; | |
13302 | expressionS ex_sym; | |
13303 | int reg1; | |
6478892d | 13304 | |
8586fc66 | 13305 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
13306 | We also need NewABI support. */ |
13307 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13308 | { | |
13309 | s_ignore (0); | |
13310 | return; | |
13311 | } | |
13312 | ||
13313 | reg1 = tc_get_register (0); | |
13314 | SKIP_WHITESPACE (); | |
13315 | if (*input_line_pointer != ',') | |
13316 | { | |
13317 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13318 | return; | |
13319 | } | |
13320 | else | |
80245285 | 13321 | ++input_line_pointer; |
6478892d TS |
13322 | SKIP_WHITESPACE (); |
13323 | if (*input_line_pointer == '$') | |
80245285 TS |
13324 | { |
13325 | mips_cpreturn_register = tc_get_register (0); | |
13326 | mips_cpreturn_offset = -1; | |
13327 | } | |
6478892d | 13328 | else |
80245285 TS |
13329 | { |
13330 | mips_cpreturn_offset = get_absolute_expression (); | |
13331 | mips_cpreturn_register = -1; | |
13332 | } | |
6478892d TS |
13333 | SKIP_WHITESPACE (); |
13334 | if (*input_line_pointer != ',') | |
13335 | { | |
13336 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
13337 | return; | |
13338 | } | |
13339 | else | |
f9419b05 | 13340 | ++input_line_pointer; |
6478892d | 13341 | SKIP_WHITESPACE (); |
f21f8242 | 13342 | expression (&ex_sym); |
6478892d | 13343 | |
584892a6 | 13344 | macro_start (); |
6478892d TS |
13345 | if (mips_cpreturn_register == -1) |
13346 | { | |
13347 | ex_off.X_op = O_constant; | |
13348 | ex_off.X_add_symbol = NULL; | |
13349 | ex_off.X_op_symbol = NULL; | |
13350 | ex_off.X_add_number = mips_cpreturn_offset; | |
13351 | ||
67c0d1eb | 13352 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 13353 | BFD_RELOC_LO16, SP); |
6478892d TS |
13354 | } |
13355 | else | |
67c0d1eb | 13356 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 13357 | mips_gp_register, 0); |
6478892d | 13358 | |
aed1a261 | 13359 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
13360 | { |
13361 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
13362 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
13363 | BFD_RELOC_HI16_S); | |
13364 | ||
13365 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
13366 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
13367 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
13368 | ||
13369 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
13370 | mips_gp_register, reg1); | |
13371 | } | |
13372 | else | |
13373 | { | |
13374 | expressionS ex; | |
13375 | ||
13376 | ex.X_op = O_symbol; | |
4184909a | 13377 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
13378 | ex.X_op_symbol = NULL; |
13379 | ex.X_add_number = 0; | |
6e1304d8 | 13380 | |
aa6975fb ILT |
13381 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
13382 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
13383 | ||
13384 | macro_build_lui (&ex, mips_gp_register); | |
13385 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
13386 | mips_gp_register, BFD_RELOC_LO16); | |
13387 | } | |
f21f8242 | 13388 | |
584892a6 | 13389 | macro_end (); |
6478892d TS |
13390 | |
13391 | demand_empty_rest_of_line (); | |
13392 | } | |
13393 | ||
13394 | static void | |
17a2f251 | 13395 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13396 | { |
13397 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 13398 | .cplocal is ignored. */ |
6478892d TS |
13399 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
13400 | { | |
13401 | s_ignore (0); | |
13402 | return; | |
13403 | } | |
13404 | ||
13405 | mips_gp_register = tc_get_register (0); | |
85b51719 | 13406 | demand_empty_rest_of_line (); |
6478892d TS |
13407 | } |
13408 | ||
252b5132 RH |
13409 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
13410 | offset from $sp. The offset is remembered, and after making a PIC | |
13411 | call $gp is restored from that location. */ | |
13412 | ||
13413 | static void | |
17a2f251 | 13414 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13415 | { |
13416 | expressionS ex; | |
252b5132 | 13417 | |
6478892d | 13418 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 13419 | .cprestore is ignored. */ |
6478892d | 13420 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
13421 | { |
13422 | s_ignore (0); | |
13423 | return; | |
13424 | } | |
13425 | ||
13426 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 13427 | mips_cprestore_valid = 1; |
252b5132 RH |
13428 | |
13429 | ex.X_op = O_constant; | |
13430 | ex.X_add_symbol = NULL; | |
13431 | ex.X_op_symbol = NULL; | |
13432 | ex.X_add_number = mips_cprestore_offset; | |
13433 | ||
584892a6 | 13434 | macro_start (); |
67c0d1eb RS |
13435 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
13436 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 13437 | macro_end (); |
252b5132 RH |
13438 | |
13439 | demand_empty_rest_of_line (); | |
13440 | } | |
13441 | ||
6478892d | 13442 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 13443 | was given in the preceding .cpsetup, it results in: |
6478892d | 13444 | ld $gp, offset($sp) |
76b3015f | 13445 | |
6478892d | 13446 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
13447 | daddu $gp, $reg2, $0 */ |
13448 | ||
6478892d | 13449 | static void |
17a2f251 | 13450 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13451 | { |
13452 | expressionS ex; | |
6478892d TS |
13453 | |
13454 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
13455 | We also need NewABI support. */ | |
13456 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13457 | { | |
13458 | s_ignore (0); | |
13459 | return; | |
13460 | } | |
13461 | ||
584892a6 | 13462 | macro_start (); |
6478892d TS |
13463 | if (mips_cpreturn_register == -1) |
13464 | { | |
13465 | ex.X_op = O_constant; | |
13466 | ex.X_add_symbol = NULL; | |
13467 | ex.X_op_symbol = NULL; | |
13468 | ex.X_add_number = mips_cpreturn_offset; | |
13469 | ||
67c0d1eb | 13470 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
13471 | } |
13472 | else | |
67c0d1eb | 13473 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 13474 | mips_cpreturn_register, 0); |
584892a6 | 13475 | macro_end (); |
6478892d TS |
13476 | |
13477 | demand_empty_rest_of_line (); | |
13478 | } | |
13479 | ||
741d6ea8 JM |
13480 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
13481 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
13482 | use in DWARF debug information. */ | |
13483 | ||
13484 | static void | |
13485 | s_dtprel_internal (size_t bytes) | |
13486 | { | |
13487 | expressionS ex; | |
13488 | char *p; | |
13489 | ||
13490 | expression (&ex); | |
13491 | ||
13492 | if (ex.X_op != O_symbol) | |
13493 | { | |
13494 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
13495 | ? ".dtpreldword" | |
13496 | : ".dtprelword")); | |
13497 | ignore_rest_of_line (); | |
13498 | } | |
13499 | ||
13500 | p = frag_more (bytes); | |
13501 | md_number_to_chars (p, 0, bytes); | |
13502 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
13503 | (bytes == 8 | |
13504 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
13505 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
13506 | ||
13507 | demand_empty_rest_of_line (); | |
13508 | } | |
13509 | ||
13510 | /* Handle .dtprelword. */ | |
13511 | ||
13512 | static void | |
13513 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
13514 | { | |
13515 | s_dtprel_internal (4); | |
13516 | } | |
13517 | ||
13518 | /* Handle .dtpreldword. */ | |
13519 | ||
13520 | static void | |
13521 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
13522 | { | |
13523 | s_dtprel_internal (8); | |
13524 | } | |
13525 | ||
6478892d TS |
13526 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
13527 | code. It sets the offset to use in gp_rel relocations. */ | |
13528 | ||
13529 | static void | |
17a2f251 | 13530 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
13531 | { |
13532 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
13533 | We also need NewABI support. */ | |
13534 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
13535 | { | |
13536 | s_ignore (0); | |
13537 | return; | |
13538 | } | |
13539 | ||
def2e0dd | 13540 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
13541 | |
13542 | demand_empty_rest_of_line (); | |
13543 | } | |
13544 | ||
252b5132 RH |
13545 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
13546 | code. It generates a 32 bit GP relative reloc. */ | |
13547 | ||
13548 | static void | |
17a2f251 | 13549 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13550 | { |
a8dbcb85 TS |
13551 | segment_info_type *si; |
13552 | struct insn_label_list *l; | |
252b5132 RH |
13553 | symbolS *label; |
13554 | expressionS ex; | |
13555 | char *p; | |
13556 | ||
13557 | /* When not generating PIC code, this is treated as .word. */ | |
13558 | if (mips_pic != SVR4_PIC) | |
13559 | { | |
13560 | s_cons (2); | |
13561 | return; | |
13562 | } | |
13563 | ||
a8dbcb85 TS |
13564 | si = seg_info (now_seg); |
13565 | l = si->label_list; | |
13566 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13567 | mips_emit_delays (); |
252b5132 RH |
13568 | if (auto_align) |
13569 | mips_align (2, 0, label); | |
13570 | mips_clear_insn_labels (); | |
13571 | ||
13572 | expression (&ex); | |
13573 | ||
13574 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13575 | { | |
13576 | as_bad (_("Unsupported use of .gpword")); | |
13577 | ignore_rest_of_line (); | |
13578 | } | |
13579 | ||
13580 | p = frag_more (4); | |
17a2f251 | 13581 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13582 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13583 | BFD_RELOC_GPREL32); |
252b5132 RH |
13584 | |
13585 | demand_empty_rest_of_line (); | |
13586 | } | |
13587 | ||
10181a0d | 13588 | static void |
17a2f251 | 13589 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13590 | { |
a8dbcb85 TS |
13591 | segment_info_type *si; |
13592 | struct insn_label_list *l; | |
10181a0d AO |
13593 | symbolS *label; |
13594 | expressionS ex; | |
13595 | char *p; | |
13596 | ||
13597 | /* When not generating PIC code, this is treated as .dword. */ | |
13598 | if (mips_pic != SVR4_PIC) | |
13599 | { | |
13600 | s_cons (3); | |
13601 | return; | |
13602 | } | |
13603 | ||
a8dbcb85 TS |
13604 | si = seg_info (now_seg); |
13605 | l = si->label_list; | |
13606 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13607 | mips_emit_delays (); |
10181a0d AO |
13608 | if (auto_align) |
13609 | mips_align (3, 0, label); | |
13610 | mips_clear_insn_labels (); | |
13611 | ||
13612 | expression (&ex); | |
13613 | ||
13614 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13615 | { | |
13616 | as_bad (_("Unsupported use of .gpdword")); | |
13617 | ignore_rest_of_line (); | |
13618 | } | |
13619 | ||
13620 | p = frag_more (8); | |
17a2f251 | 13621 | md_number_to_chars (p, 0, 8); |
a105a300 | 13622 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13623 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13624 | |
13625 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13626 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13627 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13628 | |
13629 | demand_empty_rest_of_line (); | |
13630 | } | |
13631 | ||
252b5132 RH |
13632 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13633 | tables in SVR4 PIC code. */ | |
13634 | ||
13635 | static void | |
17a2f251 | 13636 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13637 | { |
252b5132 RH |
13638 | int reg; |
13639 | ||
10181a0d AO |
13640 | /* This is ignored when not generating SVR4 PIC code. */ |
13641 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13642 | { |
13643 | s_ignore (0); | |
13644 | return; | |
13645 | } | |
13646 | ||
13647 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13648 | macro_start (); |
252b5132 | 13649 | reg = tc_get_register (0); |
67c0d1eb | 13650 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13651 | macro_end (); |
252b5132 | 13652 | |
bdaaa2e1 | 13653 | demand_empty_rest_of_line (); |
252b5132 RH |
13654 | } |
13655 | ||
13656 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13657 | mips16 mode. This permits the linker to handle them specially, | |
13658 | such as generating jalx instructions when needed. We also make | |
13659 | them odd for the duration of the assembly, in order to generate the | |
13660 | right sort of code. We will make them even in the adjust_symtab | |
13661 | routine, while leaving them marked. This is convenient for the | |
13662 | debugger and the disassembler. The linker knows to make them odd | |
13663 | again. */ | |
13664 | ||
13665 | static void | |
17a2f251 | 13666 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13667 | { |
f9419b05 | 13668 | mips16_mark_labels (); |
252b5132 RH |
13669 | |
13670 | demand_empty_rest_of_line (); | |
13671 | } | |
13672 | ||
13673 | /* Handle a .stabn directive. We need these in order to mark a label | |
13674 | as being a mips16 text label correctly. Sometimes the compiler | |
13675 | will emit a label, followed by a .stabn, and then switch sections. | |
13676 | If the label and .stabn are in mips16 mode, then the label is | |
13677 | really a mips16 text label. */ | |
13678 | ||
13679 | static void | |
17a2f251 | 13680 | s_mips_stab (int type) |
252b5132 | 13681 | { |
f9419b05 | 13682 | if (type == 'n') |
252b5132 RH |
13683 | mips16_mark_labels (); |
13684 | ||
13685 | s_stab (type); | |
13686 | } | |
13687 | ||
54f4ddb3 | 13688 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13689 | |
13690 | static void | |
17a2f251 | 13691 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13692 | { |
13693 | char *name; | |
13694 | int c; | |
13695 | symbolS *symbolP; | |
13696 | expressionS exp; | |
13697 | ||
13698 | name = input_line_pointer; | |
13699 | c = get_symbol_end (); | |
13700 | symbolP = symbol_find_or_make (name); | |
13701 | S_SET_WEAK (symbolP); | |
13702 | *input_line_pointer = c; | |
13703 | ||
13704 | SKIP_WHITESPACE (); | |
13705 | ||
13706 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13707 | { | |
13708 | if (S_IS_DEFINED (symbolP)) | |
13709 | { | |
20203fb9 | 13710 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
13711 | S_GET_NAME (symbolP)); |
13712 | ignore_rest_of_line (); | |
13713 | return; | |
13714 | } | |
bdaaa2e1 | 13715 | |
252b5132 RH |
13716 | if (*input_line_pointer == ',') |
13717 | { | |
13718 | ++input_line_pointer; | |
13719 | SKIP_WHITESPACE (); | |
13720 | } | |
bdaaa2e1 | 13721 | |
252b5132 RH |
13722 | expression (&exp); |
13723 | if (exp.X_op != O_symbol) | |
13724 | { | |
20203fb9 | 13725 | as_bad (_("bad .weakext directive")); |
98d3f06f | 13726 | ignore_rest_of_line (); |
252b5132 RH |
13727 | return; |
13728 | } | |
49309057 | 13729 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13730 | } |
13731 | ||
13732 | demand_empty_rest_of_line (); | |
13733 | } | |
13734 | ||
13735 | /* Parse a register string into a number. Called from the ECOFF code | |
13736 | to parse .frame. The argument is non-zero if this is the frame | |
13737 | register, so that we can record it in mips_frame_reg. */ | |
13738 | ||
13739 | int | |
17a2f251 | 13740 | tc_get_register (int frame) |
252b5132 | 13741 | { |
707bfff6 | 13742 | unsigned int reg; |
252b5132 RH |
13743 | |
13744 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13745 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13746 | reg = 0; | |
252b5132 | 13747 | if (frame) |
7a621144 DJ |
13748 | { |
13749 | mips_frame_reg = reg != 0 ? reg : SP; | |
13750 | mips_frame_reg_valid = 1; | |
13751 | mips_cprestore_valid = 0; | |
13752 | } | |
252b5132 RH |
13753 | return reg; |
13754 | } | |
13755 | ||
13756 | valueT | |
17a2f251 | 13757 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13758 | { |
13759 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13760 | ||
b4c71f56 TS |
13761 | if (IS_ELF) |
13762 | { | |
13763 | /* We don't need to align ELF sections to the full alignment. | |
13764 | However, Irix 5 may prefer that we align them at least to a 16 | |
13765 | byte boundary. We don't bother to align the sections if we | |
13766 | are targeted for an embedded system. */ | |
c41e87e3 | 13767 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
13768 | return addr; |
13769 | if (align > 4) | |
13770 | align = 4; | |
13771 | } | |
252b5132 RH |
13772 | |
13773 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13774 | } | |
13775 | ||
13776 | /* Utility routine, called from above as well. If called while the | |
13777 | input file is still being read, it's only an approximation. (For | |
13778 | example, a symbol may later become defined which appeared to be | |
13779 | undefined earlier.) */ | |
13780 | ||
13781 | static int | |
17a2f251 | 13782 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13783 | { |
13784 | if (sym == 0) | |
13785 | return 0; | |
13786 | ||
4d0d148d | 13787 | if (g_switch_value > 0) |
252b5132 RH |
13788 | { |
13789 | const char *symname; | |
13790 | int change; | |
13791 | ||
c9914766 | 13792 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13793 | register. It can be if it is smaller than the -G size or if |
13794 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13795 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13796 | they can. */ |
13797 | symname = S_GET_NAME (sym); | |
13798 | if (symname != (const char *) NULL | |
13799 | && (strcmp (symname, "eprol") == 0 | |
13800 | || strcmp (symname, "etext") == 0 | |
13801 | || strcmp (symname, "_gp") == 0 | |
13802 | || strcmp (symname, "edata") == 0 | |
13803 | || strcmp (symname, "_fbss") == 0 | |
13804 | || strcmp (symname, "_fdata") == 0 | |
13805 | || strcmp (symname, "_ftext") == 0 | |
13806 | || strcmp (symname, "end") == 0 | |
13807 | || strcmp (symname, "_gp_disp") == 0)) | |
13808 | change = 1; | |
13809 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13810 | && (0 | |
13811 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13812 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13813 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13814 | <= g_switch_value)) | |
252b5132 RH |
13815 | #endif |
13816 | /* We must defer this decision until after the whole | |
13817 | file has been read, since there might be a .extern | |
13818 | after the first use of this symbol. */ | |
13819 | || (before_relaxing | |
13820 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13821 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13822 | #endif |
13823 | && S_GET_VALUE (sym) == 0) | |
13824 | || (S_GET_VALUE (sym) != 0 | |
13825 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13826 | change = 0; | |
13827 | else | |
13828 | { | |
13829 | const char *segname; | |
13830 | ||
13831 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 13832 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
13833 | && strcmp (segname, ".lit4") != 0); |
13834 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13835 | && strcmp (segname, ".sbss") != 0 |
13836 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13837 | && strncmp (segname, ".sbss.", 6) != 0 |
13838 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13839 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13840 | } |
13841 | return change; | |
13842 | } | |
13843 | else | |
c9914766 | 13844 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13845 | return 1; |
13846 | } | |
13847 | ||
5919d012 RS |
13848 | |
13849 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13850 | ||
13851 | static bfd_boolean | |
17a2f251 | 13852 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13853 | { |
13854 | asection *symsec; | |
5919d012 RS |
13855 | |
13856 | /* Handle the case of a symbol equated to another symbol. */ | |
13857 | while (symbol_equated_reloc_p (sym)) | |
13858 | { | |
13859 | symbolS *n; | |
13860 | ||
5f0fe04b | 13861 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13862 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13863 | if (n == sym) | |
13864 | break; | |
13865 | sym = n; | |
13866 | } | |
13867 | ||
df1f3cda DD |
13868 | if (symbol_section_p (sym)) |
13869 | return TRUE; | |
13870 | ||
5919d012 RS |
13871 | symsec = S_GET_SEGMENT (sym); |
13872 | ||
5919d012 RS |
13873 | /* This must duplicate the test in adjust_reloc_syms. */ |
13874 | return (symsec != &bfd_und_section | |
13875 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13876 | && !bfd_is_com_section (symsec) |
13877 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13878 | #ifdef OBJ_ELF |
13879 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13880 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13881 | #endif |
13882 | ); | |
13883 | } | |
13884 | ||
13885 | ||
252b5132 RH |
13886 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13887 | extended opcode. SEC is the section the frag is in. */ | |
13888 | ||
13889 | static int | |
17a2f251 | 13890 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13891 | { |
13892 | int type; | |
3994f87e | 13893 | const struct mips16_immed_operand *op; |
252b5132 RH |
13894 | offsetT val; |
13895 | int mintiny, maxtiny; | |
13896 | segT symsec; | |
98aa84af | 13897 | fragS *sym_frag; |
252b5132 RH |
13898 | |
13899 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13900 | return 0; | |
13901 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13902 | return 1; | |
13903 | ||
13904 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13905 | op = mips16_immed_operands; | |
13906 | while (op->type != type) | |
13907 | { | |
13908 | ++op; | |
9c2799c2 | 13909 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13910 | } |
13911 | ||
13912 | if (op->unsp) | |
13913 | { | |
13914 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13915 | { | |
13916 | mintiny = 1; | |
13917 | maxtiny = 1 << op->nbits; | |
13918 | } | |
13919 | else | |
13920 | { | |
13921 | mintiny = 0; | |
13922 | maxtiny = (1 << op->nbits) - 1; | |
13923 | } | |
13924 | } | |
13925 | else | |
13926 | { | |
13927 | mintiny = - (1 << (op->nbits - 1)); | |
13928 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13929 | } | |
13930 | ||
98aa84af | 13931 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13932 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13933 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13934 | |
13935 | if (op->pcrel) | |
13936 | { | |
13937 | addressT addr; | |
13938 | ||
13939 | /* We won't have the section when we are called from | |
13940 | mips_relax_frag. However, we will always have been called | |
13941 | from md_estimate_size_before_relax first. If this is a | |
13942 | branch to a different section, we mark it as such. If SEC is | |
13943 | NULL, and the frag is not marked, then it must be a branch to | |
13944 | the same section. */ | |
13945 | if (sec == NULL) | |
13946 | { | |
13947 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13948 | return 1; | |
13949 | } | |
13950 | else | |
13951 | { | |
98aa84af | 13952 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13953 | if (symsec != sec) |
13954 | { | |
13955 | fragp->fr_subtype = | |
13956 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13957 | ||
13958 | /* FIXME: We should support this, and let the linker | |
13959 | catch branches and loads that are out of range. */ | |
13960 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13961 | _("unsupported PC relative reference to different section")); | |
13962 | ||
13963 | return 1; | |
13964 | } | |
98aa84af AM |
13965 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13966 | /* Assume non-extended on the first relaxation pass. | |
13967 | The address we have calculated will be bogus if this is | |
13968 | a forward branch to another frag, as the forward frag | |
13969 | will have fr_address == 0. */ | |
13970 | return 0; | |
252b5132 RH |
13971 | } |
13972 | ||
13973 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13974 | the same section. If the relax_marker of the symbol fragment |
13975 | differs from the relax_marker of this fragment, we have not | |
13976 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13977 | in STRETCH in order to get a better estimate of the address. |
13978 | This particularly matters because of the shift bits. */ | |
13979 | if (stretch != 0 | |
98aa84af | 13980 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13981 | { |
13982 | fragS *f; | |
13983 | ||
13984 | /* Adjust stretch for any alignment frag. Note that if have | |
13985 | been expanding the earlier code, the symbol may be | |
13986 | defined in what appears to be an earlier frag. FIXME: | |
13987 | This doesn't handle the fr_subtype field, which specifies | |
13988 | a maximum number of bytes to skip when doing an | |
13989 | alignment. */ | |
98aa84af | 13990 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13991 | { |
13992 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13993 | { | |
13994 | if (stretch < 0) | |
13995 | stretch = - ((- stretch) | |
13996 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13997 | else | |
13998 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13999 | if (stretch == 0) | |
14000 | break; | |
14001 | } | |
14002 | } | |
14003 | if (f != NULL) | |
14004 | val += stretch; | |
14005 | } | |
14006 | ||
14007 | addr = fragp->fr_address + fragp->fr_fix; | |
14008 | ||
14009 | /* The base address rules are complicated. The base address of | |
14010 | a branch is the following instruction. The base address of a | |
14011 | PC relative load or add is the instruction itself, but if it | |
14012 | is in a delay slot (in which case it can not be extended) use | |
14013 | the address of the instruction whose delay slot it is in. */ | |
14014 | if (type == 'p' || type == 'q') | |
14015 | { | |
14016 | addr += 2; | |
14017 | ||
14018 | /* If we are currently assuming that this frag should be | |
14019 | extended, then, the current address is two bytes | |
bdaaa2e1 | 14020 | higher. */ |
252b5132 RH |
14021 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
14022 | addr += 2; | |
14023 | ||
14024 | /* Ignore the low bit in the target, since it will be set | |
14025 | for a text label. */ | |
14026 | if ((val & 1) != 0) | |
14027 | --val; | |
14028 | } | |
14029 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14030 | addr -= 4; | |
14031 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14032 | addr -= 2; | |
14033 | ||
14034 | val -= addr & ~ ((1 << op->shift) - 1); | |
14035 | ||
14036 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14037 | if (type == 'p' || type == 'q') | |
14038 | val /= 2; | |
14039 | ||
14040 | /* If any of the shifted bits are set, we must use an extended | |
14041 | opcode. If the address depends on the size of this | |
14042 | instruction, this can lead to a loop, so we arrange to always | |
14043 | use an extended opcode. We only check this when we are in | |
14044 | the main relaxation loop, when SEC is NULL. */ | |
14045 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
14046 | { | |
14047 | fragp->fr_subtype = | |
14048 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14049 | return 1; | |
14050 | } | |
14051 | ||
14052 | /* If we are about to mark a frag as extended because the value | |
14053 | is precisely maxtiny + 1, then there is a chance of an | |
14054 | infinite loop as in the following code: | |
14055 | la $4,foo | |
14056 | .skip 1020 | |
14057 | .align 2 | |
14058 | foo: | |
14059 | In this case when the la is extended, foo is 0x3fc bytes | |
14060 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
14061 | the la must be extended. To avoid this loop, we mark the | |
14062 | frag as extended if it was small, and is about to become | |
14063 | extended with a value of maxtiny + 1. */ | |
14064 | if (val == ((maxtiny + 1) << op->shift) | |
14065 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
14066 | && sec == NULL) | |
14067 | { | |
14068 | fragp->fr_subtype = | |
14069 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
14070 | return 1; | |
14071 | } | |
14072 | } | |
14073 | else if (symsec != absolute_section && sec != NULL) | |
14074 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
14075 | ||
14076 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14077 | || val < (mintiny << op->shift) | |
14078 | || val > (maxtiny << op->shift)) | |
14079 | return 1; | |
14080 | else | |
14081 | return 0; | |
14082 | } | |
14083 | ||
4a6a3df4 AO |
14084 | /* Compute the length of a branch sequence, and adjust the |
14085 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
14086 | worst-case length is computed, with UPDATE being used to indicate | |
14087 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
14088 | branch is to be computed. */ | |
14089 | static int | |
17a2f251 | 14090 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 14091 | { |
b34976b6 | 14092 | bfd_boolean toofar; |
4a6a3df4 AO |
14093 | int length; |
14094 | ||
14095 | if (fragp | |
14096 | && S_IS_DEFINED (fragp->fr_symbol) | |
14097 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
14098 | { | |
14099 | addressT addr; | |
14100 | offsetT val; | |
14101 | ||
14102 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
14103 | ||
14104 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
14105 | ||
14106 | val -= addr; | |
14107 | ||
14108 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
14109 | } | |
14110 | else if (fragp) | |
14111 | /* If the symbol is not defined or it's in a different segment, | |
14112 | assume the user knows what's going on and emit a short | |
14113 | branch. */ | |
b34976b6 | 14114 | toofar = FALSE; |
4a6a3df4 | 14115 | else |
b34976b6 | 14116 | toofar = TRUE; |
4a6a3df4 AO |
14117 | |
14118 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
14119 | fragp->fr_subtype | |
af6ae2ad | 14120 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
14121 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
14122 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
14123 | toofar); | |
14124 | ||
14125 | length = 4; | |
14126 | if (toofar) | |
14127 | { | |
14128 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
14129 | length += 8; | |
14130 | ||
14131 | if (mips_pic != NO_PIC) | |
14132 | { | |
14133 | /* Additional space for PIC loading of target address. */ | |
14134 | length += 8; | |
14135 | if (mips_opts.isa == ISA_MIPS1) | |
14136 | /* Additional space for $at-stabilizing nop. */ | |
14137 | length += 4; | |
14138 | } | |
14139 | ||
14140 | /* If branch is conditional. */ | |
14141 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
14142 | length += 8; | |
14143 | } | |
b34976b6 | 14144 | |
4a6a3df4 AO |
14145 | return length; |
14146 | } | |
14147 | ||
252b5132 RH |
14148 | /* Estimate the size of a frag before relaxing. Unless this is the |
14149 | mips16, we are not really relaxing here, and the final size is | |
14150 | encoded in the subtype information. For the mips16, we have to | |
14151 | decide whether we are using an extended opcode or not. */ | |
14152 | ||
252b5132 | 14153 | int |
17a2f251 | 14154 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 14155 | { |
5919d012 | 14156 | int change; |
252b5132 | 14157 | |
4a6a3df4 AO |
14158 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14159 | { | |
14160 | ||
b34976b6 AM |
14161 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
14162 | ||
4a6a3df4 AO |
14163 | return fragp->fr_var; |
14164 | } | |
14165 | ||
252b5132 | 14166 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
14167 | /* We don't want to modify the EXTENDED bit here; it might get us |
14168 | into infinite loops. We change it only in mips_relax_frag(). */ | |
14169 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
14170 | |
14171 | if (mips_pic == NO_PIC) | |
5919d012 | 14172 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 14173 | else if (mips_pic == SVR4_PIC) |
5919d012 | 14174 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
14175 | else if (mips_pic == VXWORKS_PIC) |
14176 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
14177 | change = 0; | |
252b5132 RH |
14178 | else |
14179 | abort (); | |
14180 | ||
14181 | if (change) | |
14182 | { | |
4d7206a2 | 14183 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 14184 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 14185 | } |
4d7206a2 RS |
14186 | else |
14187 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
14188 | } |
14189 | ||
14190 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 14191 | should be converted into a reloc against a section. */ |
252b5132 RH |
14192 | |
14193 | int | |
17a2f251 | 14194 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 14195 | { |
252b5132 RH |
14196 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
14197 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14198 | return 0; | |
a161fe53 | 14199 | |
252b5132 RH |
14200 | if (fixp->fx_addsy == NULL) |
14201 | return 1; | |
a161fe53 | 14202 | |
de7e6852 RS |
14203 | /* If symbol SYM is in a mergeable section, relocations of the form |
14204 | SYM + 0 can usually be made section-relative. The mergeable data | |
14205 | is then identified by the section offset rather than by the symbol. | |
14206 | ||
14207 | However, if we're generating REL LO16 relocations, the offset is split | |
14208 | between the LO16 and parterning high part relocation. The linker will | |
14209 | need to recalculate the complete offset in order to correctly identify | |
14210 | the merge data. | |
14211 | ||
14212 | The linker has traditionally not looked for the parterning high part | |
14213 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
14214 | placed anywhere. Rather than break backwards compatibility by changing | |
14215 | this, it seems better not to force the issue, and instead keep the | |
14216 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 14217 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 14218 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
14219 | && HAVE_IN_PLACE_ADDENDS |
14220 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
14221 | return 0; | |
14222 | ||
1180b5a4 RS |
14223 | /* There is no place to store an in-place offset for JALR relocations. */ |
14224 | if (fixp->fx_r_type == BFD_RELOC_MIPS_JALR && HAVE_IN_PLACE_ADDENDS) | |
14225 | return 0; | |
14226 | ||
252b5132 | 14227 | #ifdef OBJ_ELF |
b314ec0e RS |
14228 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
14229 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
14230 | relocations against MIPS16 functions; in this case, the stub becomes | |
14231 | the function's canonical address. | |
14232 | ||
14233 | Floating-point stubs are stored in unique .mips16.call.* or | |
14234 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
14235 | the first relocation in section S must be against F; this is how the | |
14236 | linker determines the target function. All relocations that might | |
14237 | resolve to T must also be against F. We therefore have the following | |
14238 | restrictions, which are given in an intentionally-redundant way: | |
14239 | ||
14240 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
14241 | symbols. | |
14242 | ||
14243 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
14244 | if that stub might be used. | |
14245 | ||
14246 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
14247 | symbols. | |
14248 | ||
14249 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
14250 | that stub might be used. | |
14251 | ||
14252 | There is a further restriction: | |
14253 | ||
14254 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
14255 | on targets with in-place addends; the relocation field cannot | |
14256 | encode the low bit. | |
14257 | ||
14258 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
14259 | against a MIPS16 symbol. | |
14260 | ||
14261 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
14262 | relocation against some symbol R, no relocation against R may be | |
14263 | reduced. (Note that this deals with (2) as well as (1) because | |
14264 | relocations against global symbols will never be reduced on ELF | |
14265 | targets.) This approach is a little simpler than trying to detect | |
14266 | stub sections, and gives the "all or nothing" per-symbol consistency | |
14267 | that we have for MIPS16 symbols. */ | |
f43abd2b | 14268 | if (IS_ELF |
b314ec0e | 14269 | && fixp->fx_subsy == NULL |
30c09090 | 14270 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
b314ec0e | 14271 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 RH |
14272 | return 0; |
14273 | #endif | |
a161fe53 | 14274 | |
252b5132 RH |
14275 | return 1; |
14276 | } | |
14277 | ||
14278 | /* Translate internal representation of relocation info to BFD target | |
14279 | format. */ | |
14280 | ||
14281 | arelent ** | |
17a2f251 | 14282 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14283 | { |
14284 | static arelent *retval[4]; | |
14285 | arelent *reloc; | |
14286 | bfd_reloc_code_real_type code; | |
14287 | ||
4b0cff4e TS |
14288 | memset (retval, 0, sizeof(retval)); |
14289 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
14290 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
14291 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
14292 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
14293 | ||
bad36eac DJ |
14294 | if (fixp->fx_pcrel) |
14295 | { | |
9c2799c2 | 14296 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); |
bad36eac DJ |
14297 | |
14298 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
14299 | Relocations want only the symbol offset. */ | |
14300 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 14301 | if (!IS_ELF) |
bad36eac DJ |
14302 | { |
14303 | /* A gruesome hack which is a result of the gruesome gas | |
14304 | reloc handling. What's worse, for COFF (as opposed to | |
14305 | ECOFF), we might need yet another copy of reloc->address. | |
14306 | See bfd_install_relocation. */ | |
14307 | reloc->addend += reloc->address; | |
14308 | } | |
14309 | } | |
14310 | else | |
14311 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 14312 | |
438c16b8 TS |
14313 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
14314 | entry to be used in the relocation's section offset. */ | |
14315 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
14316 | { |
14317 | reloc->address = reloc->addend; | |
14318 | reloc->addend = 0; | |
14319 | } | |
14320 | ||
252b5132 | 14321 | code = fixp->fx_r_type; |
252b5132 | 14322 | |
bad36eac | 14323 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
14324 | if (reloc->howto == NULL) |
14325 | { | |
14326 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14327 | _("Can not represent %s relocation in this object file format"), | |
14328 | bfd_get_reloc_code_name (code)); | |
14329 | retval[0] = NULL; | |
14330 | } | |
14331 | ||
14332 | return retval; | |
14333 | } | |
14334 | ||
14335 | /* Relax a machine dependent frag. This returns the amount by which | |
14336 | the current size of the frag should change. */ | |
14337 | ||
14338 | int | |
17a2f251 | 14339 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 14340 | { |
4a6a3df4 AO |
14341 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14342 | { | |
14343 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
14344 | |
14345 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
14346 | |
14347 | return fragp->fr_var - old_var; | |
14348 | } | |
14349 | ||
252b5132 RH |
14350 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
14351 | return 0; | |
14352 | ||
c4e7957c | 14353 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
14354 | { |
14355 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14356 | return 0; | |
14357 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
14358 | return 2; | |
14359 | } | |
14360 | else | |
14361 | { | |
14362 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14363 | return 0; | |
14364 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
14365 | return -2; | |
14366 | } | |
14367 | ||
14368 | return 0; | |
14369 | } | |
14370 | ||
14371 | /* Convert a machine dependent frag. */ | |
14372 | ||
14373 | void | |
17a2f251 | 14374 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 14375 | { |
4a6a3df4 AO |
14376 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
14377 | { | |
14378 | bfd_byte *buf; | |
14379 | unsigned long insn; | |
14380 | expressionS exp; | |
14381 | fixS *fixp; | |
b34976b6 | 14382 | |
4a6a3df4 AO |
14383 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
14384 | ||
14385 | if (target_big_endian) | |
14386 | insn = bfd_getb32 (buf); | |
14387 | else | |
14388 | insn = bfd_getl32 (buf); | |
b34976b6 | 14389 | |
4a6a3df4 AO |
14390 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
14391 | { | |
14392 | /* We generate a fixup instead of applying it right now | |
14393 | because, if there are linker relaxations, we're going to | |
14394 | need the relocations. */ | |
14395 | exp.X_op = O_symbol; | |
14396 | exp.X_add_symbol = fragp->fr_symbol; | |
14397 | exp.X_add_number = fragp->fr_offset; | |
14398 | ||
14399 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14400 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
14401 | fixp->fx_file = fragp->fr_file; |
14402 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14403 | |
2132e3a3 | 14404 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14405 | buf += 4; |
14406 | } | |
14407 | else | |
14408 | { | |
14409 | int i; | |
14410 | ||
14411 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14412 | _("relaxed out-of-range branch into a jump")); | |
14413 | ||
14414 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
14415 | goto uncond; | |
14416 | ||
14417 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14418 | { | |
14419 | /* Reverse the branch. */ | |
14420 | switch ((insn >> 28) & 0xf) | |
14421 | { | |
14422 | case 4: | |
14423 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
14424 | have the condition reversed by tweaking a single | |
14425 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 14426 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
14427 | insn ^= 0x00010000; |
14428 | break; | |
14429 | ||
14430 | case 0: | |
14431 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 14432 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 14433 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
14434 | insn ^= 0x00010000; |
14435 | break; | |
b34976b6 | 14436 | |
4a6a3df4 AO |
14437 | case 1: |
14438 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 14439 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
14440 | insn ^= 0x04000000; |
14441 | break; | |
14442 | ||
14443 | default: | |
14444 | abort (); | |
14445 | } | |
14446 | } | |
14447 | ||
14448 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14449 | { | |
14450 | /* Clear the and-link bit. */ | |
9c2799c2 | 14451 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 14452 | |
54f4ddb3 TS |
14453 | /* bltzal 0x04100000 bgezal 0x04110000 |
14454 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
14455 | insn &= ~0x00100000; |
14456 | } | |
14457 | ||
14458 | /* Branch over the branch (if the branch was likely) or the | |
14459 | full jump (not likely case). Compute the offset from the | |
14460 | current instruction to branch to. */ | |
14461 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14462 | i = 16; | |
14463 | else | |
14464 | { | |
14465 | /* How many bytes in instructions we've already emitted? */ | |
14466 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14467 | /* How many bytes in instructions from here to the end? */ | |
14468 | i = fragp->fr_var - i; | |
14469 | } | |
14470 | /* Convert to instruction count. */ | |
14471 | i >>= 2; | |
14472 | /* Branch counts from the next instruction. */ | |
b34976b6 | 14473 | i--; |
4a6a3df4 AO |
14474 | insn |= i; |
14475 | /* Branch over the jump. */ | |
2132e3a3 | 14476 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14477 | buf += 4; |
14478 | ||
54f4ddb3 | 14479 | /* nop */ |
2132e3a3 | 14480 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14481 | buf += 4; |
14482 | ||
14483 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
14484 | { | |
14485 | /* beql $0, $0, 2f */ | |
14486 | insn = 0x50000000; | |
14487 | /* Compute the PC offset from the current instruction to | |
14488 | the end of the variable frag. */ | |
14489 | /* How many bytes in instructions we've already emitted? */ | |
14490 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
14491 | /* How many bytes in instructions from here to the end? */ | |
14492 | i = fragp->fr_var - i; | |
14493 | /* Convert to instruction count. */ | |
14494 | i >>= 2; | |
14495 | /* Don't decrement i, because we want to branch over the | |
14496 | delay slot. */ | |
14497 | ||
14498 | insn |= i; | |
2132e3a3 | 14499 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14500 | buf += 4; |
14501 | ||
2132e3a3 | 14502 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14503 | buf += 4; |
14504 | } | |
14505 | ||
14506 | uncond: | |
14507 | if (mips_pic == NO_PIC) | |
14508 | { | |
14509 | /* j or jal. */ | |
14510 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
14511 | ? 0x0c000000 : 0x08000000); | |
14512 | exp.X_op = O_symbol; | |
14513 | exp.X_add_symbol = fragp->fr_symbol; | |
14514 | exp.X_add_number = fragp->fr_offset; | |
14515 | ||
14516 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14517 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
14518 | fixp->fx_file = fragp->fr_file; |
14519 | fixp->fx_line = fragp->fr_line; | |
14520 | ||
2132e3a3 | 14521 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14522 | buf += 4; |
14523 | } | |
14524 | else | |
14525 | { | |
14526 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
14527 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
14528 | exp.X_op = O_symbol; | |
14529 | exp.X_add_symbol = fragp->fr_symbol; | |
14530 | exp.X_add_number = fragp->fr_offset; | |
14531 | ||
14532 | if (fragp->fr_offset) | |
14533 | { | |
14534 | exp.X_add_symbol = make_expr_symbol (&exp); | |
14535 | exp.X_add_number = 0; | |
14536 | } | |
14537 | ||
14538 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14539 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
14540 | fixp->fx_file = fragp->fr_file; |
14541 | fixp->fx_line = fragp->fr_line; | |
14542 | ||
2132e3a3 | 14543 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 14544 | buf += 4; |
b34976b6 | 14545 | |
4a6a3df4 AO |
14546 | if (mips_opts.isa == ISA_MIPS1) |
14547 | { | |
14548 | /* nop */ | |
2132e3a3 | 14549 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
14550 | buf += 4; |
14551 | } | |
14552 | ||
14553 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
14554 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14555 | ||
14556 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14557 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14558 | fixp->fx_file = fragp->fr_file; |
14559 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14560 | |
2132e3a3 | 14561 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14562 | buf += 4; |
14563 | ||
14564 | /* j(al)r $at. */ | |
14565 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14566 | insn = 0x0020f809; | |
14567 | else | |
14568 | insn = 0x00200008; | |
14569 | ||
2132e3a3 | 14570 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14571 | buf += 4; |
14572 | } | |
14573 | } | |
14574 | ||
9c2799c2 | 14575 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
14576 | + fragp->fr_fix + fragp->fr_var); |
14577 | ||
14578 | fragp->fr_fix += fragp->fr_var; | |
14579 | ||
14580 | return; | |
14581 | } | |
14582 | ||
252b5132 RH |
14583 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14584 | { | |
14585 | int type; | |
3994f87e | 14586 | const struct mips16_immed_operand *op; |
b34976b6 | 14587 | bfd_boolean small, ext; |
252b5132 RH |
14588 | offsetT val; |
14589 | bfd_byte *buf; | |
14590 | unsigned long insn; | |
b34976b6 | 14591 | bfd_boolean use_extend; |
252b5132 RH |
14592 | unsigned short extend; |
14593 | ||
14594 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14595 | op = mips16_immed_operands; | |
14596 | while (op->type != type) | |
14597 | ++op; | |
14598 | ||
14599 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14600 | { | |
b34976b6 AM |
14601 | small = FALSE; |
14602 | ext = TRUE; | |
252b5132 RH |
14603 | } |
14604 | else | |
14605 | { | |
b34976b6 AM |
14606 | small = TRUE; |
14607 | ext = FALSE; | |
252b5132 RH |
14608 | } |
14609 | ||
6386f3a7 | 14610 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14611 | val = S_GET_VALUE (fragp->fr_symbol); |
14612 | if (op->pcrel) | |
14613 | { | |
14614 | addressT addr; | |
14615 | ||
14616 | addr = fragp->fr_address + fragp->fr_fix; | |
14617 | ||
14618 | /* The rules for the base address of a PC relative reloc are | |
14619 | complicated; see mips16_extended_frag. */ | |
14620 | if (type == 'p' || type == 'q') | |
14621 | { | |
14622 | addr += 2; | |
14623 | if (ext) | |
14624 | addr += 2; | |
14625 | /* Ignore the low bit in the target, since it will be | |
14626 | set for a text label. */ | |
14627 | if ((val & 1) != 0) | |
14628 | --val; | |
14629 | } | |
14630 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14631 | addr -= 4; | |
14632 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14633 | addr -= 2; | |
14634 | ||
14635 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14636 | val -= addr; | |
14637 | ||
14638 | /* Make sure the section winds up with the alignment we have | |
14639 | assumed. */ | |
14640 | if (op->shift > 0) | |
14641 | record_alignment (asec, op->shift); | |
14642 | } | |
14643 | ||
14644 | if (ext | |
14645 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14646 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14647 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14648 | _("extended instruction in delay slot")); | |
14649 | ||
14650 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14651 | ||
14652 | if (target_big_endian) | |
14653 | insn = bfd_getb16 (buf); | |
14654 | else | |
14655 | insn = bfd_getl16 (buf); | |
14656 | ||
14657 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14658 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14659 | small, ext, &insn, &use_extend, &extend); | |
14660 | ||
14661 | if (use_extend) | |
14662 | { | |
2132e3a3 | 14663 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14664 | fragp->fr_fix += 2; |
14665 | buf += 2; | |
14666 | } | |
14667 | ||
2132e3a3 | 14668 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14669 | fragp->fr_fix += 2; |
14670 | buf += 2; | |
14671 | } | |
14672 | else | |
14673 | { | |
4d7206a2 RS |
14674 | int first, second; |
14675 | fixS *fixp; | |
252b5132 | 14676 | |
4d7206a2 RS |
14677 | first = RELAX_FIRST (fragp->fr_subtype); |
14678 | second = RELAX_SECOND (fragp->fr_subtype); | |
14679 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14680 | |
584892a6 RS |
14681 | /* Possibly emit a warning if we've chosen the longer option. */ |
14682 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14683 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14684 | { | |
14685 | const char *msg = macro_warning (fragp->fr_subtype); | |
14686 | if (msg != 0) | |
520725ea | 14687 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
584892a6 RS |
14688 | } |
14689 | ||
4d7206a2 RS |
14690 | /* Go through all the fixups for the first sequence. Disable them |
14691 | (by marking them as done) if we're going to use the second | |
14692 | sequence instead. */ | |
14693 | while (fixp | |
14694 | && fixp->fx_frag == fragp | |
14695 | && fixp->fx_where < fragp->fr_fix - second) | |
14696 | { | |
14697 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14698 | fixp->fx_done = 1; | |
14699 | fixp = fixp->fx_next; | |
14700 | } | |
252b5132 | 14701 | |
4d7206a2 RS |
14702 | /* Go through the fixups for the second sequence. Disable them if |
14703 | we're going to use the first sequence, otherwise adjust their | |
14704 | addresses to account for the relaxation. */ | |
14705 | while (fixp && fixp->fx_frag == fragp) | |
14706 | { | |
14707 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14708 | fixp->fx_where -= first; | |
14709 | else | |
14710 | fixp->fx_done = 1; | |
14711 | fixp = fixp->fx_next; | |
14712 | } | |
14713 | ||
14714 | /* Now modify the frag contents. */ | |
14715 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14716 | { | |
14717 | char *start; | |
14718 | ||
14719 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14720 | memmove (start, start + first, second); | |
14721 | fragp->fr_fix -= first; | |
14722 | } | |
14723 | else | |
14724 | fragp->fr_fix -= second; | |
252b5132 RH |
14725 | } |
14726 | } | |
14727 | ||
14728 | #ifdef OBJ_ELF | |
14729 | ||
14730 | /* This function is called after the relocs have been generated. | |
14731 | We've been storing mips16 text labels as odd. Here we convert them | |
14732 | back to even for the convenience of the debugger. */ | |
14733 | ||
14734 | void | |
17a2f251 | 14735 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14736 | { |
14737 | asymbol **syms; | |
14738 | unsigned int count, i; | |
14739 | ||
f43abd2b | 14740 | if (!IS_ELF) |
252b5132 RH |
14741 | return; |
14742 | ||
14743 | syms = bfd_get_outsymbols (stdoutput); | |
14744 | count = bfd_get_symcount (stdoutput); | |
14745 | for (i = 0; i < count; i++, syms++) | |
14746 | { | |
30c09090 | 14747 | if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other) |
252b5132 RH |
14748 | && ((*syms)->value & 1) != 0) |
14749 | { | |
14750 | (*syms)->value &= ~1; | |
14751 | /* If the symbol has an odd size, it was probably computed | |
14752 | incorrectly, so adjust that as well. */ | |
14753 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14754 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14755 | } | |
14756 | } | |
14757 | } | |
14758 | ||
14759 | #endif | |
14760 | ||
14761 | /* This function is called whenever a label is defined. It is used | |
14762 | when handling branch delays; if a branch has a label, we assume we | |
14763 | can not move it. */ | |
14764 | ||
14765 | void | |
17a2f251 | 14766 | mips_define_label (symbolS *sym) |
252b5132 | 14767 | { |
a8dbcb85 | 14768 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14769 | struct insn_label_list *l; |
14770 | ||
14771 | if (free_insn_labels == NULL) | |
14772 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14773 | else | |
14774 | { | |
14775 | l = free_insn_labels; | |
14776 | free_insn_labels = l->next; | |
14777 | } | |
14778 | ||
14779 | l->label = sym; | |
a8dbcb85 TS |
14780 | l->next = si->label_list; |
14781 | si->label_list = l; | |
07a53e5c RH |
14782 | |
14783 | #ifdef OBJ_ELF | |
14784 | dwarf2_emit_label (sym); | |
14785 | #endif | |
252b5132 RH |
14786 | } |
14787 | \f | |
14788 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14789 | ||
14790 | /* Some special processing for a MIPS ELF file. */ | |
14791 | ||
14792 | void | |
17a2f251 | 14793 | mips_elf_final_processing (void) |
252b5132 RH |
14794 | { |
14795 | /* Write out the register information. */ | |
316f5878 | 14796 | if (mips_abi != N64_ABI) |
252b5132 RH |
14797 | { |
14798 | Elf32_RegInfo s; | |
14799 | ||
14800 | s.ri_gprmask = mips_gprmask; | |
14801 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14802 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14803 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14804 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14805 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14806 | ||
14807 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14808 | ((Elf32_External_RegInfo *) | |
14809 | mips_regmask_frag)); | |
14810 | } | |
14811 | else | |
14812 | { | |
14813 | Elf64_Internal_RegInfo s; | |
14814 | ||
14815 | s.ri_gprmask = mips_gprmask; | |
14816 | s.ri_pad = 0; | |
14817 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14818 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14819 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14820 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14821 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14822 | ||
14823 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14824 | ((Elf64_External_RegInfo *) | |
14825 | mips_regmask_frag)); | |
14826 | } | |
14827 | ||
14828 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14829 | sort of BFD interface for this. */ | |
14830 | if (mips_any_noreorder) | |
14831 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14832 | if (mips_pic != NO_PIC) | |
143d77c5 | 14833 | { |
252b5132 | 14834 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14835 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14836 | } | |
14837 | if (mips_abicalls) | |
14838 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14839 | |
98d3f06f | 14840 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14841 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14842 | file_ase_dsp is true. */ | |
8b082fb1 | 14843 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14844 | /* We may need to define a new flag for MT ASE, and set this flag when |
14845 | file_ase_mt is true. */ | |
a4672219 TS |
14846 | if (file_ase_mips16) |
14847 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14848 | #if 0 /* XXX FIXME */ |
14849 | if (file_ase_mips3d) | |
14850 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14851 | #endif | |
deec1734 CD |
14852 | if (file_ase_mdmx) |
14853 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14854 | |
bdaaa2e1 | 14855 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14856 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14857 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14858 | else if (mips_abi == O64_ABI) |
252b5132 | 14859 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14860 | else if (mips_abi == EABI_ABI) |
252b5132 | 14861 | { |
316f5878 | 14862 | if (!file_mips_gp32) |
252b5132 RH |
14863 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14864 | else | |
14865 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14866 | } | |
316f5878 | 14867 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14868 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14869 | ||
c9914766 | 14870 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14871 | |
14872 | if (mips_32bitmode) | |
14873 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14874 | |
14875 | #if 0 /* XXX FIXME */ | |
14876 | /* 32 bit code with 64 bit FP registers. */ | |
14877 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14878 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14879 | #endif | |
252b5132 RH |
14880 | } |
14881 | ||
14882 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14883 | \f | |
beae10d5 | 14884 | typedef struct proc { |
9b2f1d35 EC |
14885 | symbolS *func_sym; |
14886 | symbolS *func_end_sym; | |
beae10d5 KH |
14887 | unsigned long reg_mask; |
14888 | unsigned long reg_offset; | |
14889 | unsigned long fpreg_mask; | |
14890 | unsigned long fpreg_offset; | |
14891 | unsigned long frame_offset; | |
14892 | unsigned long frame_reg; | |
14893 | unsigned long pc_reg; | |
14894 | } procS; | |
252b5132 RH |
14895 | |
14896 | static procS cur_proc; | |
14897 | static procS *cur_proc_ptr; | |
14898 | static int numprocs; | |
14899 | ||
742a56fe RS |
14900 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal |
14901 | nop as "0". */ | |
14902 | ||
14903 | char | |
14904 | mips_nop_opcode (void) | |
14905 | { | |
14906 | return seg_info (now_seg)->tc_segment_info_data.mips16; | |
14907 | } | |
14908 | ||
14909 | /* Fill in an rs_align_code fragment. This only needs to do something | |
14910 | for MIPS16 code, where 0 is not a nop. */ | |
a19d8eb0 | 14911 | |
0a9ef439 | 14912 | void |
17a2f251 | 14913 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14914 | { |
742a56fe | 14915 | char *p; |
c67a084a NC |
14916 | int bytes, size, excess; |
14917 | valueT opcode; | |
742a56fe | 14918 | |
0a9ef439 RH |
14919 | if (fragp->fr_type != rs_align_code) |
14920 | return; | |
14921 | ||
742a56fe RS |
14922 | p = fragp->fr_literal + fragp->fr_fix; |
14923 | if (*p) | |
a19d8eb0 | 14924 | { |
c67a084a NC |
14925 | opcode = mips16_nop_insn.insn_opcode; |
14926 | size = 2; | |
14927 | } | |
14928 | else | |
14929 | { | |
14930 | opcode = nop_insn.insn_opcode; | |
14931 | size = 4; | |
14932 | } | |
a19d8eb0 | 14933 | |
c67a084a NC |
14934 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14935 | excess = bytes % size; | |
14936 | if (excess != 0) | |
14937 | { | |
14938 | /* If we're not inserting a whole number of instructions, | |
14939 | pad the end of the fixed part of the frag with zeros. */ | |
14940 | memset (p, 0, excess); | |
14941 | p += excess; | |
14942 | fragp->fr_fix += excess; | |
a19d8eb0 | 14943 | } |
c67a084a NC |
14944 | |
14945 | md_number_to_chars (p, opcode, size); | |
14946 | fragp->fr_var = size; | |
a19d8eb0 CP |
14947 | } |
14948 | ||
252b5132 | 14949 | static void |
17a2f251 | 14950 | md_obj_begin (void) |
252b5132 RH |
14951 | { |
14952 | } | |
14953 | ||
14954 | static void | |
17a2f251 | 14955 | md_obj_end (void) |
252b5132 | 14956 | { |
54f4ddb3 | 14957 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14958 | if (cur_proc_ptr) |
9a41af64 | 14959 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14960 | } |
14961 | ||
14962 | static long | |
17a2f251 | 14963 | get_number (void) |
252b5132 RH |
14964 | { |
14965 | int negative = 0; | |
14966 | long val = 0; | |
14967 | ||
14968 | if (*input_line_pointer == '-') | |
14969 | { | |
14970 | ++input_line_pointer; | |
14971 | negative = 1; | |
14972 | } | |
3882b010 | 14973 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14974 | as_bad (_("expected simple number")); |
252b5132 RH |
14975 | if (input_line_pointer[0] == '0') |
14976 | { | |
14977 | if (input_line_pointer[1] == 'x') | |
14978 | { | |
14979 | input_line_pointer += 2; | |
3882b010 | 14980 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14981 | { |
14982 | val <<= 4; | |
14983 | val |= hex_value (*input_line_pointer++); | |
14984 | } | |
14985 | return negative ? -val : val; | |
14986 | } | |
14987 | else | |
14988 | { | |
14989 | ++input_line_pointer; | |
3882b010 | 14990 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14991 | { |
14992 | val <<= 3; | |
14993 | val |= *input_line_pointer++ - '0'; | |
14994 | } | |
14995 | return negative ? -val : val; | |
14996 | } | |
14997 | } | |
3882b010 | 14998 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14999 | { |
15000 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
15001 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 15002 | as_warn (_("invalid number")); |
252b5132 RH |
15003 | return -1; |
15004 | } | |
3882b010 | 15005 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
15006 | { |
15007 | val *= 10; | |
15008 | val += *input_line_pointer++ - '0'; | |
15009 | } | |
15010 | return negative ? -val : val; | |
15011 | } | |
15012 | ||
15013 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
15014 | is an initial number which is the ECOFF file index. In the non-ECOFF |
15015 | case .file implies DWARF-2. */ | |
15016 | ||
15017 | static void | |
17a2f251 | 15018 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 15019 | { |
ecb4347a DJ |
15020 | static int first_file_directive = 0; |
15021 | ||
c5dd6aab DJ |
15022 | if (ECOFF_DEBUGGING) |
15023 | { | |
15024 | get_number (); | |
15025 | s_app_file (0); | |
15026 | } | |
15027 | else | |
ecb4347a DJ |
15028 | { |
15029 | char *filename; | |
15030 | ||
15031 | filename = dwarf2_directive_file (0); | |
15032 | ||
15033 | /* Versions of GCC up to 3.1 start files with a ".file" | |
15034 | directive even for stabs output. Make sure that this | |
15035 | ".file" is handled. Note that you need a version of GCC | |
15036 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
15037 | if (filename != NULL && ! first_file_directive) | |
15038 | { | |
15039 | (void) new_logical_line (filename, -1); | |
c04f5787 | 15040 | s_app_file_string (filename, 0); |
ecb4347a DJ |
15041 | } |
15042 | first_file_directive = 1; | |
15043 | } | |
c5dd6aab DJ |
15044 | } |
15045 | ||
15046 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
15047 | |
15048 | static void | |
17a2f251 | 15049 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 15050 | { |
c5dd6aab DJ |
15051 | if (!ECOFF_DEBUGGING) |
15052 | dwarf2_directive_loc (0); | |
252b5132 RH |
15053 | } |
15054 | ||
252b5132 RH |
15055 | /* The .end directive. */ |
15056 | ||
15057 | static void | |
17a2f251 | 15058 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15059 | { |
15060 | symbolS *p; | |
252b5132 | 15061 | |
7a621144 DJ |
15062 | /* Following functions need their own .frame and .cprestore directives. */ |
15063 | mips_frame_reg_valid = 0; | |
15064 | mips_cprestore_valid = 0; | |
15065 | ||
252b5132 RH |
15066 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
15067 | { | |
15068 | p = get_symbol (); | |
15069 | demand_empty_rest_of_line (); | |
15070 | } | |
15071 | else | |
15072 | p = NULL; | |
15073 | ||
14949570 | 15074 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15075 | as_warn (_(".end not in text section")); |
15076 | ||
15077 | if (!cur_proc_ptr) | |
15078 | { | |
15079 | as_warn (_(".end directive without a preceding .ent directive.")); | |
15080 | demand_empty_rest_of_line (); | |
15081 | return; | |
15082 | } | |
15083 | ||
15084 | if (p != NULL) | |
15085 | { | |
9c2799c2 | 15086 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 15087 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 15088 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
15089 | |
15090 | if (debug_type == DEBUG_STABS) | |
15091 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
15092 | S_GET_NAME (p)); | |
252b5132 RH |
15093 | } |
15094 | else | |
15095 | as_warn (_(".end directive missing or unknown symbol")); | |
15096 | ||
2132e3a3 | 15097 | #ifdef OBJ_ELF |
9b2f1d35 EC |
15098 | /* Create an expression to calculate the size of the function. */ |
15099 | if (p && cur_proc_ptr) | |
15100 | { | |
15101 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
15102 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
15103 | ||
15104 | obj->size = exp; | |
15105 | exp->X_op = O_subtract; | |
15106 | exp->X_add_symbol = symbol_temp_new_now (); | |
15107 | exp->X_op_symbol = p; | |
15108 | exp->X_add_number = 0; | |
15109 | ||
15110 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
15111 | } | |
15112 | ||
ecb4347a | 15113 | /* Generate a .pdr section. */ |
f43abd2b | 15114 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
15115 | { |
15116 | segT saved_seg = now_seg; | |
15117 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
15118 | expressionS exp; |
15119 | char *fragp; | |
252b5132 | 15120 | |
252b5132 | 15121 | #ifdef md_flush_pending_output |
ecb4347a | 15122 | md_flush_pending_output (); |
252b5132 RH |
15123 | #endif |
15124 | ||
9c2799c2 | 15125 | gas_assert (pdr_seg); |
ecb4347a | 15126 | subseg_set (pdr_seg, 0); |
252b5132 | 15127 | |
ecb4347a DJ |
15128 | /* Write the symbol. */ |
15129 | exp.X_op = O_symbol; | |
15130 | exp.X_add_symbol = p; | |
15131 | exp.X_add_number = 0; | |
15132 | emit_expr (&exp, 4); | |
252b5132 | 15133 | |
ecb4347a | 15134 | fragp = frag_more (7 * 4); |
252b5132 | 15135 | |
17a2f251 TS |
15136 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
15137 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
15138 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
15139 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
15140 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
15141 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
15142 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 15143 | |
ecb4347a DJ |
15144 | subseg_set (saved_seg, saved_subseg); |
15145 | } | |
15146 | #endif /* OBJ_ELF */ | |
252b5132 RH |
15147 | |
15148 | cur_proc_ptr = NULL; | |
15149 | } | |
15150 | ||
15151 | /* The .aent and .ent directives. */ | |
15152 | ||
15153 | static void | |
17a2f251 | 15154 | s_mips_ent (int aent) |
252b5132 | 15155 | { |
252b5132 | 15156 | symbolS *symbolP; |
252b5132 RH |
15157 | |
15158 | symbolP = get_symbol (); | |
15159 | if (*input_line_pointer == ',') | |
f9419b05 | 15160 | ++input_line_pointer; |
252b5132 | 15161 | SKIP_WHITESPACE (); |
3882b010 | 15162 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 15163 | || *input_line_pointer == '-') |
874e8986 | 15164 | get_number (); |
252b5132 | 15165 | |
14949570 | 15166 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
15167 | as_warn (_(".ent or .aent not in text section.")); |
15168 | ||
15169 | if (!aent && cur_proc_ptr) | |
9a41af64 | 15170 | as_warn (_("missing .end")); |
252b5132 RH |
15171 | |
15172 | if (!aent) | |
15173 | { | |
7a621144 DJ |
15174 | /* This function needs its own .frame and .cprestore directives. */ |
15175 | mips_frame_reg_valid = 0; | |
15176 | mips_cprestore_valid = 0; | |
15177 | ||
252b5132 RH |
15178 | cur_proc_ptr = &cur_proc; |
15179 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
15180 | ||
9b2f1d35 | 15181 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 15182 | |
f9419b05 | 15183 | ++numprocs; |
ecb4347a DJ |
15184 | |
15185 | if (debug_type == DEBUG_STABS) | |
15186 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
15187 | S_GET_NAME (symbolP)); | |
252b5132 RH |
15188 | } |
15189 | ||
7c0fc524 MR |
15190 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
15191 | ||
252b5132 RH |
15192 | demand_empty_rest_of_line (); |
15193 | } | |
15194 | ||
15195 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 15196 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 15197 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 15198 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
15199 | symbol table (in the mdebug section). */ |
15200 | ||
15201 | static void | |
17a2f251 | 15202 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15203 | { |
ecb4347a | 15204 | #ifdef OBJ_ELF |
f43abd2b | 15205 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
15206 | { |
15207 | long val; | |
252b5132 | 15208 | |
ecb4347a DJ |
15209 | if (cur_proc_ptr == (procS *) NULL) |
15210 | { | |
15211 | as_warn (_(".frame outside of .ent")); | |
15212 | demand_empty_rest_of_line (); | |
15213 | return; | |
15214 | } | |
252b5132 | 15215 | |
ecb4347a DJ |
15216 | cur_proc_ptr->frame_reg = tc_get_register (1); |
15217 | ||
15218 | SKIP_WHITESPACE (); | |
15219 | if (*input_line_pointer++ != ',' | |
15220 | || get_absolute_expression_and_terminator (&val) != ',') | |
15221 | { | |
15222 | as_warn (_("Bad .frame directive")); | |
15223 | --input_line_pointer; | |
15224 | demand_empty_rest_of_line (); | |
15225 | return; | |
15226 | } | |
252b5132 | 15227 | |
ecb4347a DJ |
15228 | cur_proc_ptr->frame_offset = val; |
15229 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 15230 | |
252b5132 | 15231 | demand_empty_rest_of_line (); |
252b5132 | 15232 | } |
ecb4347a DJ |
15233 | else |
15234 | #endif /* OBJ_ELF */ | |
15235 | s_ignore (ignore); | |
252b5132 RH |
15236 | } |
15237 | ||
bdaaa2e1 KH |
15238 | /* The .fmask and .mask directives. If the mdebug section is present |
15239 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 15240 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 15241 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
15242 | make reference to the ecoff symbol table (in the mdebug section). */ |
15243 | ||
15244 | static void | |
17a2f251 | 15245 | s_mips_mask (int reg_type) |
252b5132 | 15246 | { |
ecb4347a | 15247 | #ifdef OBJ_ELF |
f43abd2b | 15248 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 15249 | { |
ecb4347a | 15250 | long mask, off; |
252b5132 | 15251 | |
ecb4347a DJ |
15252 | if (cur_proc_ptr == (procS *) NULL) |
15253 | { | |
15254 | as_warn (_(".mask/.fmask outside of .ent")); | |
15255 | demand_empty_rest_of_line (); | |
15256 | return; | |
15257 | } | |
252b5132 | 15258 | |
ecb4347a DJ |
15259 | if (get_absolute_expression_and_terminator (&mask) != ',') |
15260 | { | |
15261 | as_warn (_("Bad .mask/.fmask directive")); | |
15262 | --input_line_pointer; | |
15263 | demand_empty_rest_of_line (); | |
15264 | return; | |
15265 | } | |
252b5132 | 15266 | |
ecb4347a DJ |
15267 | off = get_absolute_expression (); |
15268 | ||
15269 | if (reg_type == 'F') | |
15270 | { | |
15271 | cur_proc_ptr->fpreg_mask = mask; | |
15272 | cur_proc_ptr->fpreg_offset = off; | |
15273 | } | |
15274 | else | |
15275 | { | |
15276 | cur_proc_ptr->reg_mask = mask; | |
15277 | cur_proc_ptr->reg_offset = off; | |
15278 | } | |
15279 | ||
15280 | demand_empty_rest_of_line (); | |
252b5132 RH |
15281 | } |
15282 | else | |
ecb4347a DJ |
15283 | #endif /* OBJ_ELF */ |
15284 | s_ignore (reg_type); | |
252b5132 RH |
15285 | } |
15286 | ||
316f5878 RS |
15287 | /* A table describing all the processors gas knows about. Names are |
15288 | matched in the order listed. | |
e7af610e | 15289 | |
316f5878 RS |
15290 | To ease comparison, please keep this table in the same order as |
15291 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
15292 | static const struct mips_cpu_info mips_cpu_info_table[] = |
15293 | { | |
316f5878 | 15294 | /* Entries for generic ISAs */ |
ad3fea08 TS |
15295 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
15296 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
15297 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
15298 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
15299 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
15300 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
15301 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15302 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
15303 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
15304 | |
15305 | /* MIPS I */ | |
ad3fea08 TS |
15306 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
15307 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
15308 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
15309 | |
15310 | /* MIPS II */ | |
ad3fea08 | 15311 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
15312 | |
15313 | /* MIPS III */ | |
ad3fea08 TS |
15314 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
15315 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
15316 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
15317 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
15318 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
15319 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
15320 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
15321 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
15322 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
15323 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
15324 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
15325 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
15326 | /* ST Microelectronics Loongson 2E and 2F cores */ |
15327 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
15328 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
15329 | |
15330 | /* MIPS IV */ | |
ad3fea08 TS |
15331 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
15332 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
15333 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
15334 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
15335 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
15336 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
15337 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
15338 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
15339 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
15340 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
15341 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
15342 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
15343 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
15344 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
15345 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
15346 | |
15347 | /* MIPS 32 */ | |
ad3fea08 TS |
15348 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
15349 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15350 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
15351 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
15352 | ||
15353 | /* MIPS 32 Release 2 */ | |
15354 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15355 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15356 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15357 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15358 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15359 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15360 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15361 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15362 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15363 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15364 | /* Deprecated forms of the above. */ | |
15365 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 15366 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15367 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 15368 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 15369 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 15370 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
15371 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
15372 | /* Deprecated forms of the above. */ | |
15373 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 15374 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 15375 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
15376 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15377 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15378 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15379 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15380 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15381 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15382 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15383 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15384 | /* Deprecated forms of the above. */ | |
15385 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15386 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
15387 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
15388 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15389 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
15390 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15391 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15392 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15393 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15394 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15395 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
15396 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15397 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15398 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15399 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15400 | /* Deprecated forms of the above. */ | |
15401 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
15402 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
15403 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
15404 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
15405 | /* 1004K cores are multiprocessor versions of the 34K. */ |
15406 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15407 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15408 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15409 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15410 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15411 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
15412 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
15413 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 15414 | |
316f5878 | 15415 | /* MIPS 64 */ |
ad3fea08 TS |
15416 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
15417 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
15418 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 15419 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 15420 | |
c7a23324 | 15421 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
15422 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
15423 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
15424 | /* Broadcom SB-1A CPU core */ |
15425 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
15426 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 15427 | |
ed163775 MR |
15428 | /* MIPS 64 Release 2 */ |
15429 | ||
967344c6 AN |
15430 | /* Cavium Networks Octeon CPU core */ |
15431 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
15432 | ||
52b6b6b9 JM |
15433 | /* RMI Xlr */ |
15434 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
15435 | ||
316f5878 RS |
15436 | /* End marker */ |
15437 | { NULL, 0, 0, 0 } | |
15438 | }; | |
e7af610e | 15439 | |
84ea6cf2 | 15440 | |
316f5878 RS |
15441 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15442 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 15443 | |
316f5878 | 15444 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 15445 | |
b34976b6 | 15446 | static bfd_boolean |
17a2f251 | 15447 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15448 | { |
15449 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
15450 | given++, canonical++; | |
15451 | ||
15452 | return ((*given == 0 && *canonical == 0) | |
15453 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15454 | } | |
15455 | ||
15456 | ||
15457 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
15458 | CPU name. We've traditionally allowed a lot of variation here. | |
15459 | ||
15460 | Note: this function is shared between GCC and GAS. */ | |
15461 | ||
b34976b6 | 15462 | static bfd_boolean |
17a2f251 | 15463 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
15464 | { |
15465 | /* First see if the name matches exactly, or with a final "000" | |
15466 | turned into "k". */ | |
15467 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 15468 | return TRUE; |
316f5878 RS |
15469 | |
15470 | /* If not, try comparing based on numerical designation alone. | |
15471 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15472 | if (TOLOWER (*given) == 'r') | |
15473 | given++; | |
15474 | if (!ISDIGIT (*given)) | |
b34976b6 | 15475 | return FALSE; |
316f5878 RS |
15476 | |
15477 | /* Skip over some well-known prefixes in the canonical name, | |
15478 | hoping to find a number there too. */ | |
15479 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15480 | canonical += 2; | |
15481 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15482 | canonical += 2; | |
15483 | else if (TOLOWER (canonical[0]) == 'r') | |
15484 | canonical += 1; | |
15485 | ||
15486 | return mips_strict_matching_cpu_name_p (canonical, given); | |
15487 | } | |
15488 | ||
15489 | ||
15490 | /* Parse an option that takes the name of a processor as its argument. | |
15491 | OPTION is the name of the option and CPU_STRING is the argument. | |
15492 | Return the corresponding processor enumeration if the CPU_STRING is | |
15493 | recognized, otherwise report an error and return null. | |
15494 | ||
15495 | A similar function exists in GCC. */ | |
e7af610e NC |
15496 | |
15497 | static const struct mips_cpu_info * | |
17a2f251 | 15498 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 15499 | { |
316f5878 | 15500 | const struct mips_cpu_info *p; |
e7af610e | 15501 | |
316f5878 RS |
15502 | /* 'from-abi' selects the most compatible architecture for the given |
15503 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15504 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
15505 | version. Look first at the -mgp options, if given, otherwise base | |
15506 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 15507 | |
316f5878 RS |
15508 | Treat NO_ABI like the EABIs. One reason to do this is that the |
15509 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
15510 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
15511 | 'mips64', just as we did in the days before 'from-abi'. */ | |
15512 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
15513 | { | |
15514 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15515 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
15516 | ||
15517 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15518 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
15519 | ||
15520 | if (file_mips_gp32 >= 0) | |
15521 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
15522 | ||
15523 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
15524 | ? ISA_MIPS3 | |
15525 | : ISA_MIPS1); | |
15526 | } | |
15527 | ||
15528 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15529 | if (strcasecmp (cpu_string, "default") == 0) | |
15530 | return 0; | |
15531 | ||
15532 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
15533 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
15534 | return p; | |
15535 | ||
20203fb9 | 15536 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 15537 | return 0; |
e7af610e NC |
15538 | } |
15539 | ||
316f5878 RS |
15540 | /* Return the canonical processor information for ISA (a member of the |
15541 | ISA_MIPS* enumeration). */ | |
15542 | ||
e7af610e | 15543 | static const struct mips_cpu_info * |
17a2f251 | 15544 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
15545 | { |
15546 | int i; | |
15547 | ||
15548 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 15549 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 15550 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
15551 | return (&mips_cpu_info_table[i]); |
15552 | ||
e972090a | 15553 | return NULL; |
e7af610e | 15554 | } |
fef14a42 TS |
15555 | |
15556 | static const struct mips_cpu_info * | |
17a2f251 | 15557 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
15558 | { |
15559 | int i; | |
15560 | ||
15561 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
15562 | if (arch == mips_cpu_info_table[i].cpu) | |
15563 | return (&mips_cpu_info_table[i]); | |
15564 | ||
15565 | return NULL; | |
15566 | } | |
316f5878 RS |
15567 | \f |
15568 | static void | |
17a2f251 | 15569 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
15570 | { |
15571 | if (*first_p) | |
15572 | { | |
15573 | fprintf (stream, "%24s", ""); | |
15574 | *col_p = 24; | |
15575 | } | |
15576 | else | |
15577 | { | |
15578 | fprintf (stream, ", "); | |
15579 | *col_p += 2; | |
15580 | } | |
e7af610e | 15581 | |
316f5878 RS |
15582 | if (*col_p + strlen (string) > 72) |
15583 | { | |
15584 | fprintf (stream, "\n%24s", ""); | |
15585 | *col_p = 24; | |
15586 | } | |
15587 | ||
15588 | fprintf (stream, "%s", string); | |
15589 | *col_p += strlen (string); | |
15590 | ||
15591 | *first_p = 0; | |
15592 | } | |
15593 | ||
15594 | void | |
17a2f251 | 15595 | md_show_usage (FILE *stream) |
e7af610e | 15596 | { |
316f5878 RS |
15597 | int column, first; |
15598 | size_t i; | |
15599 | ||
15600 | fprintf (stream, _("\ | |
15601 | MIPS options:\n\ | |
316f5878 RS |
15602 | -EB generate big endian output\n\ |
15603 | -EL generate little endian output\n\ | |
15604 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15605 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15606 | implicitly with the gp register [default 8]\n")); | |
15607 | fprintf (stream, _("\ | |
15608 | -mips1 generate MIPS ISA I instructions\n\ | |
15609 | -mips2 generate MIPS ISA II instructions\n\ | |
15610 | -mips3 generate MIPS ISA III instructions\n\ | |
15611 | -mips4 generate MIPS ISA IV instructions\n\ | |
15612 | -mips5 generate MIPS ISA V instructions\n\ | |
15613 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15614 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15615 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15616 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15617 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15618 | ||
15619 | first = 1; | |
e7af610e NC |
15620 | |
15621 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15622 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15623 | show (stream, "from-abi", &column, &first); | |
15624 | fputc ('\n', stream); | |
e7af610e | 15625 | |
316f5878 RS |
15626 | fprintf (stream, _("\ |
15627 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15628 | -no-mCPU don't generate code specific to CPU.\n\ | |
15629 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15630 | ||
15631 | first = 1; | |
15632 | ||
15633 | show (stream, "3900", &column, &first); | |
15634 | show (stream, "4010", &column, &first); | |
15635 | show (stream, "4100", &column, &first); | |
15636 | show (stream, "4650", &column, &first); | |
15637 | fputc ('\n', stream); | |
15638 | ||
15639 | fprintf (stream, _("\ | |
15640 | -mips16 generate mips16 instructions\n\ | |
15641 | -no-mips16 do not generate mips16 instructions\n")); | |
15642 | fprintf (stream, _("\ | |
e16bfa71 TS |
15643 | -msmartmips generate smartmips instructions\n\ |
15644 | -mno-smartmips do not generate smartmips instructions\n")); | |
15645 | fprintf (stream, _("\ | |
74cd071d CF |
15646 | -mdsp generate DSP instructions\n\ |
15647 | -mno-dsp do not generate DSP instructions\n")); | |
15648 | fprintf (stream, _("\ | |
8b082fb1 TS |
15649 | -mdspr2 generate DSP R2 instructions\n\ |
15650 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15651 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15652 | -mmt generate MT instructions\n\ |
15653 | -mno-mt do not generate MT instructions\n")); | |
15654 | fprintf (stream, _("\ | |
c67a084a NC |
15655 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
15656 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 15657 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15658 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 15659 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 15660 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
15661 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15662 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15663 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15664 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15665 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15666 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
15667 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
15668 | fprintf (stream, _("\ |
15669 | -mhard-float allow floating-point instructions\n\ | |
15670 | -msoft-float do not allow floating-point instructions\n\ | |
15671 | -msingle-float only allow 32-bit floating-point operations\n\ | |
15672 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
15673 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
15674 | )); | |
316f5878 RS |
15675 | #ifdef OBJ_ELF |
15676 | fprintf (stream, _("\ | |
15677 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 15678 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 15679 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 15680 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 15681 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 15682 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15683 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15684 | position dependent (non shared) code\n\ |
316f5878 RS |
15685 | -mabi=ABI create ABI conformant object file for:\n")); |
15686 | ||
15687 | first = 1; | |
15688 | ||
15689 | show (stream, "32", &column, &first); | |
15690 | show (stream, "o64", &column, &first); | |
15691 | show (stream, "n32", &column, &first); | |
15692 | show (stream, "64", &column, &first); | |
15693 | show (stream, "eabi", &column, &first); | |
15694 | ||
15695 | fputc ('\n', stream); | |
15696 | ||
15697 | fprintf (stream, _("\ | |
15698 | -32 create o32 ABI object file (default)\n\ | |
15699 | -n32 create n32 ABI object file\n\ | |
15700 | -64 create 64 ABI object file\n")); | |
15701 | #endif | |
e7af610e | 15702 | } |
14e777e0 | 15703 | |
1575952e | 15704 | #ifdef TE_IRIX |
14e777e0 | 15705 | enum dwarf2_format |
413a266c | 15706 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 15707 | { |
369943fe | 15708 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 15709 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
15710 | else |
15711 | return dwarf2_format_32bit; | |
15712 | } | |
1575952e | 15713 | #endif |
73369e65 EC |
15714 | |
15715 | int | |
15716 | mips_dwarf2_addr_size (void) | |
15717 | { | |
6b6b3450 | 15718 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 15719 | return 8; |
73369e65 EC |
15720 | else |
15721 | return 4; | |
15722 | } | |
5862107c EC |
15723 | |
15724 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15725 | void | |
15726 | mips_cfi_frame_initial_instructions (void) | |
15727 | { | |
15728 | cfi_add_CFA_def_cfa_register (SP); | |
15729 | } | |
15730 | ||
707bfff6 TS |
15731 | int |
15732 | tc_mips_regname_to_dw2regnum (char *regname) | |
15733 | { | |
15734 | unsigned int regnum = -1; | |
15735 | unsigned int reg; | |
15736 | ||
15737 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15738 | regnum = reg; | |
15739 | ||
15740 | return regnum; | |
15741 | } |