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3d3c5039 ILT |
1 | /* tc-mips.c -- assemble code for a MIPS chip. |
2 | Copyright (C) 1993 Free Software Foundation, Inc. | |
3 | Contributed by the OSF and Ralph Campbell. | |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to | |
22 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
23 | ||
24 | #include "as.h" | |
8358c818 | 25 | #include "config.h" |
3d3c5039 ILT |
26 | |
27 | #include <ctype.h> | |
28 | ||
29 | #ifndef __STDC__ | |
30 | #ifndef NO_STDARG | |
31 | #define NO_STDARG | |
32 | #endif | |
33 | #endif | |
34 | ||
35 | #ifndef NO_STDARG | |
36 | #include <stdarg.h> | |
37 | #else | |
38 | #ifndef NO_VARARGS | |
39 | #include <varargs.h> | |
40 | #endif /* NO_VARARGS */ | |
41 | #endif /* NO_STDARG */ | |
42 | ||
918692a5 | 43 | #include "opcode/mips.h" |
3d3c5039 | 44 | |
f2a663d3 ILT |
45 | #ifdef OBJ_ELF |
46 | #include "elf/mips.h" | |
47 | ||
48 | static char *mips_regmask_frag; | |
49 | #endif | |
50 | ||
3d3c5039 | 51 | #define AT 1 |
9226253a | 52 | #define PIC_CALL_REG 25 |
670a50eb | 53 | #define GP 28 |
9226253a ILT |
54 | #define SP 29 |
55 | #define FP 30 | |
3d3c5039 ILT |
56 | #define RA 31 |
57 | ||
88225433 ILT |
58 | /* Decide whether to do GP reference optimizations based on the object |
59 | file format. */ | |
60 | #undef GPOPT | |
61 | #ifdef OBJ_ECOFF | |
62 | #define GPOPT | |
63 | #endif | |
64 | #ifdef OBJ_ELF | |
65 | #define GPOPT | |
66 | #endif | |
67 | ||
04cb3372 ILT |
68 | /* The default target format to use. */ |
69 | #ifdef OBJ_AOUT | |
70 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
71 | #define DEFAULT_TARGET_FORMAT "a.out-mips-big" | |
72 | #else | |
73 | #define DEFAULT_TARGET_FORMAT "a.out-mips-little" | |
74 | #endif | |
75 | #endif /* OBJ_AOUT */ | |
76 | #ifdef OBJ_ECOFF | |
77 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
78 | #define DEFAULT_TARGET_FORMAT "ecoff-bigmips" | |
79 | #else | |
80 | #define DEFAULT_TARGET_FORMAT "ecoff-littlemips" | |
81 | #endif | |
82 | #endif /* OBJ_ECOFF */ | |
83 | #ifdef OBJ_ELF | |
84 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
85 | #define DEFAULT_TARGET_FORMAT "elf32-bigmips" | |
86 | #else | |
87 | #define DEFAULT_TARGET_FORMAT "elf32-littlemips" | |
88 | #endif | |
89 | #endif /* OBJ_ELF */ | |
90 | ||
91 | const char *mips_target_format = DEFAULT_TARGET_FORMAT; | |
92 | ||
d2c71068 ILT |
93 | /* The name of the readonly data section. */ |
94 | #ifdef OBJ_AOUT | |
95 | #define RDATA_SECTION_NAME ".data" | |
96 | #endif | |
97 | #ifdef OBJ_ECOFF | |
98 | #define RDATA_SECTION_NAME ".rdata" | |
99 | #endif | |
100 | #ifdef OBJ_ELF | |
101 | #define RDATA_SECTION_NAME ".rodata" | |
102 | #endif | |
103 | ||
1aa6938e ILT |
104 | /* These variables are filled in with the masks of registers used. |
105 | The object format code reads them and puts them in the appropriate | |
106 | place. */ | |
107 | unsigned long mips_gprmask; | |
108 | unsigned long mips_cprmask[4]; | |
109 | ||
1051c97f ILT |
110 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
111 | temporarily using .set mipsN). */ | |
8358c818 ILT |
112 | static int mips_isa = -1; |
113 | ||
1051c97f ILT |
114 | /* MIPS ISA we are using for this output file. */ |
115 | static int file_mips_isa; | |
116 | ||
8c63448a ILT |
117 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
118 | static int mips_cpu; | |
119 | ||
d9aba805 ILT |
120 | /* MIPS PIC level. */ |
121 | ||
122 | enum mips_pic_level | |
123 | { | |
124 | /* Do not generate PIC code. */ | |
125 | NO_PIC, | |
126 | ||
127 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
128 | not sure what it is supposed to do. */ | |
129 | IRIX4_PIC, | |
130 | ||
131 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
132 | SVR4_PIC, | |
133 | ||
134 | /* Generate PIC code without using a global offset table: the data | |
135 | segment has a maximum size of 64K, all data references are off | |
136 | the $gp register, and all text references are PC relative. This | |
137 | is used on some embedded systems. */ | |
138 | EMBEDDED_PIC | |
139 | }; | |
140 | ||
141 | static enum mips_pic_level mips_pic; | |
9226253a | 142 | |
8ea7f4e8 ILT |
143 | /* 1 if trap instructions should used for overflow rather than break |
144 | instructions. */ | |
145 | static int mips_trap; | |
146 | ||
3d3c5039 ILT |
147 | static int mips_warn_about_macros; |
148 | static int mips_noreorder; | |
0dd2d296 | 149 | static int mips_any_noreorder; |
3d3c5039 ILT |
150 | static int mips_nomove; |
151 | static int mips_noat; | |
152 | static int mips_nobopt; | |
153 | ||
88225433 | 154 | #ifdef GPOPT |
670a50eb ILT |
155 | /* The size of the small data section. */ |
156 | static int g_switch_value = 8; | |
42562568 ILT |
157 | /* Whether the -G option was used. */ |
158 | static int g_switch_seen = 0; | |
670a50eb ILT |
159 | #endif |
160 | ||
3d3c5039 ILT |
161 | #define N_RMASK 0xc4 |
162 | #define N_VFP 0xd4 | |
163 | ||
164 | /* handle of the OPCODE hash table */ | |
165 | static struct hash_control *op_hash = NULL; | |
166 | ||
167 | /* This array holds the chars that always start a comment. If the | |
168 | pre-processor is disabled, these aren't very useful */ | |
169 | const char comment_chars[] = "#"; | |
170 | ||
171 | /* This array holds the chars that only start a comment at the beginning of | |
172 | a line. If the line seems to have the form '# 123 filename' | |
173 | .line and .file directives will appear in the pre-processed output */ | |
174 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
175 | first line of the input file. This is because the compiler outputs | |
176 | #NO_APP at the beginning of its output. */ | |
177 | /* Also note that C style comments are always supported. */ | |
178 | const char line_comment_chars[] = "#"; | |
179 | ||
180 | /* This array holds machine specific line separator characters. */ | |
181 | const char line_separator_chars[] = ""; | |
182 | ||
183 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
184 | const char EXP_CHARS[] = "eE"; | |
185 | ||
186 | /* Chars that mean this number is a floating point constant */ | |
187 | /* As in 0f12.456 */ | |
188 | /* or 0d1.2345e12 */ | |
189 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
190 | ||
191 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
192 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
193 | but nothing is ideal around here. | |
194 | */ | |
195 | ||
670a50eb | 196 | static char *insn_error; |
3d3c5039 ILT |
197 | |
198 | static int byte_order = BYTE_ORDER; | |
199 | ||
200 | static int auto_align = 1; | |
becfe05e ILT |
201 | |
202 | /* Symbol labelling the current insn. */ | |
203 | static symbolS *insn_label; | |
204 | ||
9226253a ILT |
205 | /* When outputting SVR4 PIC code, the assembler needs to know the |
206 | offset in the stack frame from which to restore the $gp register. | |
207 | This is set by the .cprestore pseudo-op, and saved in this | |
208 | variable. */ | |
0dd2d296 ILT |
209 | static offsetT mips_cprestore_offset = -1; |
210 | ||
211 | /* This is the register which holds the stack frame, as set by the | |
212 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
213 | static int mips_frame_reg = SP; | |
9226253a | 214 | |
becfe05e ILT |
215 | /* To output NOP instructions correctly, we need to keep information |
216 | about the previous two instructions. */ | |
217 | ||
0aa07269 ILT |
218 | /* Whether we are optimizing. The default value of 2 means to remove |
219 | unneeded NOPs and swap branch instructions when possible. A value | |
220 | of 1 means to not swap branches. A value of 0 means to always | |
221 | insert NOPs. */ | |
222 | static int mips_optimize = 2; | |
4e95866e | 223 | |
becfe05e ILT |
224 | /* The previous instruction. */ |
225 | static struct mips_cl_insn prev_insn; | |
226 | ||
227 | /* The instruction before prev_insn. */ | |
228 | static struct mips_cl_insn prev_prev_insn; | |
229 | ||
230 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
231 | point the insn_mo field at this dummy integer. */ | |
232 | static const struct mips_opcode dummy_opcode = { 0 }; | |
233 | ||
234 | /* Non-zero if prev_insn is valid. */ | |
235 | static int prev_insn_valid; | |
236 | ||
237 | /* The frag for the previous instruction. */ | |
238 | static struct frag *prev_insn_frag; | |
239 | ||
240 | /* The offset into prev_insn_frag for the previous instruction. */ | |
241 | static long prev_insn_where; | |
242 | ||
243 | /* The reloc for the previous instruction, if any. */ | |
244 | static fixS *prev_insn_fixp; | |
245 | ||
246 | /* Non-zero if the previous instruction was in a delay slot. */ | |
247 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
248 | |
249 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
250 | static int prev_insn_unreordered; | |
251 | ||
252 | /* Non-zero if the previous previous instruction was in a .set | |
253 | noreorder. */ | |
254 | static int prev_prev_insn_unreordered; | |
8c63448a ILT |
255 | |
256 | /* The number of instructions since the last instruction which | |
257 | accesses the data cache. The instruction itself counts as 1, so 0 | |
258 | means no information. This is used to work around a bug on the | |
259 | r4600 (ORION) chip. */ | |
260 | static int insns_since_cache_access; | |
3d3c5039 | 261 | \f |
0dd2d296 ILT |
262 | /* Since the MIPS does not have multiple forms of PC relative |
263 | instructions, we do not have to do relaxing as is done on other | |
264 | platforms. However, we do have to handle GP relative addressing | |
265 | correctly, which turns out to be a similar problem. | |
266 | ||
267 | Every macro that refers to a symbol can occur in (at least) two | |
268 | forms, one with GP relative addressing and one without. For | |
269 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 270 | a macro instruction like this: |
0dd2d296 ILT |
271 | lw $4,i |
272 | If i can be addressed off the GP register (this is true if it is in | |
273 | the .sbss or .sdata section, or if it is known to be smaller than | |
274 | the -G argument) this will generate the following instruction: | |
275 | lw $4,i($gp) | |
276 | This instruction will use a GPREL reloc. If i can not be addressed | |
277 | off the GP register, the following instruction sequence will be used: | |
278 | lui $at,i | |
279 | lw $4,i($at) | |
280 | In this case the first instruction will have a HI16 reloc, and the | |
281 | second reloc will have a LO16 reloc. Both relocs will be against | |
282 | the symbol i. | |
283 | ||
284 | The issue here is that we may not know whether i is GP addressable | |
285 | until after we see the instruction that uses it. Therefore, we | |
286 | want to be able to choose the final instruction sequence only at | |
287 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 288 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
289 | end of assembly. |
290 | ||
291 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
292 | addressing in quite the same way, but the issue still arises as |
293 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
294 | |
295 | We handle these issues by actually generating both possible | |
296 | instruction sequences. The longer one is put in a frag_var with | |
297 | type rs_machine_dependent. We encode what to do with the frag in | |
298 | the subtype field. We encode (1) the number of existing bytes to | |
299 | replace, (2) the number of new bytes to use, (3) the offset from | |
300 | the start of the existing bytes to the first reloc we must generate | |
301 | (that is, the offset is applied from the start of the existing | |
302 | bytes after they are replaced by the new bytes, if any), (4) the | |
303 | offset from the start of the existing bytes to the second reloc, | |
304 | (5) whether a third reloc is needed (the third reloc is always four | |
305 | bytes after the second reloc), and (6) whether to warn if this | |
306 | variant is used (this is sometimes needed if .set nomacro or .set | |
307 | noat is in effect). All these numbers are reasonably small. | |
308 | ||
309 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
310 | ensure that delay slots are handled correctly. Fortunately, there |
311 | are a limited number of cases. When the second instruction | |
312 | sequence is generated, append_insn is directed to maintain the | |
313 | existing delay slot information, so it continues to apply to any | |
314 | code after the second instruction sequence. This means that the | |
315 | second instruction sequence must not impose any requirements not | |
316 | required by the first instruction sequence. | |
0dd2d296 ILT |
317 | |
318 | These variant frags are then handled in functions called by the | |
319 | machine independent code. md_estimate_size_before_relax returns | |
320 | the final size of the frag. md_convert_frag sets up the final form | |
321 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
322 | one if needed. */ | |
323 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
324 | ((relax_substateT) \ | |
325 | (((old) << 24) \ | |
326 | | ((new) << 16) \ | |
327 | | (((reloc1) + 64) << 9) \ | |
328 | | (((reloc2) + 64) << 2) \ | |
329 | | ((reloc3) ? (1 << 1) : 0) \ | |
330 | | ((warn) ? 1 : 0))) | |
331 | #define RELAX_OLD(i) (((i) >> 24) & 0xff) | |
332 | #define RELAX_NEW(i) (((i) >> 16) & 0xff) | |
333 | #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64) | |
334 | #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64) | |
335 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) | |
336 | #define RELAX_WARN(i) ((i) & 1) | |
337 | \f | |
3d3c5039 ILT |
338 | /* Prototypes for static functions. */ |
339 | ||
340 | #ifdef __STDC__ | |
341 | #define internalError() \ | |
342 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
343 | #else | |
344 | #define internalError() as_fatal ("MIPS internal Error"); | |
345 | #endif | |
346 | ||
becfe05e | 347 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
604633ae | 348 | unsigned int reg, int fpr)); |
0dd2d296 ILT |
349 | static void append_insn PARAMS ((char *place, |
350 | struct mips_cl_insn * ip, | |
670a50eb | 351 | expressionS * p, |
3d3c5039 | 352 | bfd_reloc_code_real_type r)); |
becfe05e ILT |
353 | static void mips_no_prev_insn PARAMS ((void)); |
354 | static void mips_emit_delays PARAMS ((void)); | |
0dd2d296 | 355 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
356 | const char *name, const char *fmt, |
357 | ...)); | |
0dd2d296 ILT |
358 | static void macro_build_lui PARAMS ((char *place, int *counter, |
359 | expressionS * ep, int regnum)); | |
6e8dda9c | 360 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 361 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 362 | expressionS *)); |
0dd2d296 ILT |
363 | static void load_register PARAMS ((int *counter, int reg, expressionS * ep)); |
364 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); | |
670a50eb | 365 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
366 | #ifdef LOSING_COMPILER |
367 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
368 | #endif | |
670a50eb ILT |
369 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
370 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
371 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 372 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 373 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 | 374 | static void s_align PARAMS ((int)); |
becfe05e | 375 | static void s_stringer PARAMS ((int)); |
3d3c5039 ILT |
376 | static void s_change_sec PARAMS ((int)); |
377 | static void s_cons PARAMS ((int)); | |
378 | static void s_err PARAMS ((int)); | |
379 | static void s_extern PARAMS ((int)); | |
380 | static void s_float_cons PARAMS ((int)); | |
c1444ec4 | 381 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
382 | static void s_option PARAMS ((int)); |
383 | static void s_mipsset PARAMS ((int)); | |
becfe05e | 384 | static void s_mips_space PARAMS ((int)); |
9226253a ILT |
385 | static void s_abicalls PARAMS ((int)); |
386 | static void s_cpload PARAMS ((int)); | |
387 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
388 | static void s_gpword PARAMS ((int)); |
389 | static void s_cpadd PARAMS ((int)); | |
390 | #ifndef ECOFF_DEBUGGING | |
3d3c5039 ILT |
391 | static void md_obj_begin PARAMS ((void)); |
392 | static void md_obj_end PARAMS ((void)); | |
393 | static long get_number PARAMS ((void)); | |
394 | static void s_ent PARAMS ((int)); | |
395 | static void s_mipsend PARAMS ((int)); | |
396 | static void s_file PARAMS ((int)); | |
88225433 | 397 | #if 0 |
3d3c5039 ILT |
398 | static void s_frame PARAMS ((int)); |
399 | static void s_loc PARAMS ((int)); | |
400 | static void s_mask PARAMS ((char)); | |
401 | #endif | |
88225433 | 402 | #endif |
3d3c5039 ILT |
403 | \f |
404 | /* Pseudo-op table. | |
405 | ||
406 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
407 | should be defined here, but are currently unsupported: .alias, | |
408 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
409 | ||
410 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
411 | specific to the type of debugging information being generated, and | |
412 | should be defined by the object format: .aent, .begin, .bend, | |
413 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
414 | .vreg. | |
415 | ||
416 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
417 | not MIPS CPU specific, but are also not specific to the object file | |
418 | format. This file is probably the best place to define them, but | |
419 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
420 | .struct, .weakext. */ | |
421 | ||
422 | const pseudo_typeS md_pseudo_table[] = | |
423 | { | |
670a50eb ILT |
424 | /* MIPS specific pseudo-ops. */ |
425 | {"option", s_option, 0}, | |
426 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
427 | {"rdata", s_change_sec, 'r'}, |
428 | {"sdata", s_change_sec, 's'}, | |
429 | {"livereg", s_ignore, 0}, | |
9226253a ILT |
430 | { "abicalls", s_abicalls, 0}, |
431 | { "cpload", s_cpload, 0}, | |
432 | { "cprestore", s_cprestore, 0}, | |
0dd2d296 ILT |
433 | { "gpword", s_gpword, 0}, |
434 | { "cpadd", s_cpadd, 0}, | |
3d3c5039 | 435 | |
670a50eb | 436 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 437 | chips. */ |
becfe05e | 438 | {"asciiz", s_stringer, 1}, |
670a50eb ILT |
439 | {"bss", s_change_sec, 'b'}, |
440 | {"err", s_err, 0}, | |
441 | {"half", s_cons, 1}, | |
52aa70b5 | 442 | {"dword", s_cons, 3}, |
3d3c5039 | 443 | |
670a50eb | 444 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 445 | here for one reason or another. */ |
670a50eb | 446 | {"align", s_align, 0}, |
becfe05e ILT |
447 | {"ascii", s_stringer, 0}, |
448 | {"asciz", s_stringer, 1}, | |
670a50eb ILT |
449 | {"byte", s_cons, 0}, |
450 | {"data", s_change_sec, 'd'}, | |
becfe05e | 451 | {"double", s_float_cons, 'd'}, |
670a50eb | 452 | {"extern", s_extern, 0}, |
becfe05e | 453 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
454 | {"globl", s_mips_globl, 0}, |
455 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
456 | {"hword", s_cons, 1}, |
457 | {"int", s_cons, 2}, | |
458 | {"long", s_cons, 2}, | |
459 | {"octa", s_cons, 4}, | |
460 | {"quad", s_cons, 3}, | |
461 | {"short", s_cons, 1}, | |
462 | {"single", s_float_cons, 'f'}, | |
becfe05e | 463 | {"space", s_mips_space, 0}, |
670a50eb ILT |
464 | {"text", s_change_sec, 't'}, |
465 | {"word", s_cons, 2}, | |
3d3c5039 | 466 | |
0dd2d296 | 467 | #ifndef ECOFF_DEBUGGING |
670a50eb | 468 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 469 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 470 | {"aent", s_ent, 1}, |
9226253a | 471 | {"bgnb", s_ignore, 0}, |
670a50eb | 472 | {"end", s_mipsend, 0}, |
9226253a | 473 | {"endb", s_ignore, 0}, |
670a50eb ILT |
474 | {"ent", s_ent, 0}, |
475 | {"file", s_file, 0}, | |
476 | {"fmask", s_ignore, 'F'}, | |
477 | {"frame", s_ignore, 0}, | |
478 | {"loc", s_ignore, 0}, | |
479 | {"mask", s_ignore, 'R'}, | |
480 | {"verstamp", s_ignore, 0}, | |
3d3c5039 ILT |
481 | #endif |
482 | ||
670a50eb ILT |
483 | /* Sentinel. */ |
484 | {NULL} | |
3d3c5039 ILT |
485 | }; |
486 | \f | |
670a50eb ILT |
487 | const relax_typeS md_relax_table[] = |
488 | { | |
918692a5 | 489 | { 0 } |
3d3c5039 ILT |
490 | }; |
491 | ||
3d3c5039 ILT |
492 | static char *expr_end; |
493 | ||
494 | static expressionS imm_expr; | |
495 | static expressionS offset_expr; | |
496 | static bfd_reloc_code_real_type imm_reloc; | |
497 | static bfd_reloc_code_real_type offset_reloc; | |
498 | ||
abdad6bc ILT |
499 | /* FIXME: This should be handled in a different way. */ |
500 | extern int target_big_endian; | |
501 | ||
3d3c5039 ILT |
502 | /* |
503 | * This function is called once, at assembler startup time. It should | |
504 | * set up all the tables, etc. that the MD part of the assembler will need. | |
505 | */ | |
506 | void | |
670a50eb | 507 | md_begin () |
3d3c5039 | 508 | { |
0dd2d296 | 509 | boolean ok = false; |
604633ae | 510 | register const char *retval = NULL; |
670a50eb | 511 | register unsigned int i = 0; |
3d3c5039 | 512 | |
8358c818 ILT |
513 | if (mips_isa == -1) |
514 | { | |
8c63448a ILT |
515 | const char *cpu; |
516 | char *a = NULL; | |
517 | ||
518 | cpu = TARGET_CPU; | |
519 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
520 | { | |
521 | a = xmalloc (sizeof TARGET_CPU); | |
522 | strcpy (a, TARGET_CPU); | |
523 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
524 | cpu = a; | |
525 | } | |
526 | ||
527 | if (strcmp (cpu, "mips") == 0) | |
528 | { | |
529 | mips_isa = 1; | |
530 | mips_cpu = 3000; | |
531 | } | |
532 | else if (strcmp (cpu, "r6000") == 0 | |
533 | || strcmp (cpu, "mips2") == 0) | |
534 | { | |
535 | mips_isa = 2; | |
536 | mips_cpu = 6000; | |
537 | } | |
538 | else if (strcmp (cpu, "mips64") == 0 | |
539 | || strcmp (cpu, "r4000") == 0 | |
540 | || strcmp (cpu, "mips3") == 0) | |
541 | { | |
542 | mips_isa = 3; | |
543 | mips_cpu = 4000; | |
544 | } | |
545 | else if (strcmp (cpu, "r4400") == 0) | |
546 | { | |
547 | mips_isa = 3; | |
548 | mips_cpu = 4400; | |
549 | } | |
550 | else if (strcmp (cpu, "mips64orion") == 0 | |
551 | || strcmp (cpu, "r4600") == 0) | |
552 | { | |
553 | mips_isa = 3; | |
554 | mips_cpu = 4600; | |
555 | } | |
8358c818 | 556 | else |
8c63448a ILT |
557 | { |
558 | mips_isa = 1; | |
559 | mips_cpu = 3000; | |
560 | } | |
561 | ||
562 | if (a != NULL) | |
563 | free (a); | |
8358c818 ILT |
564 | } |
565 | ||
8ea7f4e8 ILT |
566 | if (mips_isa < 2 && mips_trap) |
567 | as_bad ("trap exception not supported at ISA 1"); | |
568 | ||
97f99d11 ILT |
569 | switch (mips_isa) |
570 | { | |
571 | case 1: | |
572 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
573 | break; | |
574 | case 2: | |
575 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
576 | break; | |
577 | case 3: | |
578 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
579 | break; | |
580 | } | |
581 | if (! ok) | |
582 | as_warn ("Could not set architecture and machine"); | |
583 | ||
1051c97f ILT |
584 | file_mips_isa = mips_isa; |
585 | ||
13fe1379 ILT |
586 | op_hash = hash_new (); |
587 | ||
670a50eb ILT |
588 | for (i = 0; i < NUMOPCODES;) |
589 | { | |
590 | const char *name = mips_opcodes[i].name; | |
591 | ||
604633ae | 592 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 593 | if (retval != NULL) |
670a50eb ILT |
594 | { |
595 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
596 | mips_opcodes[i].name, retval); | |
597 | as_fatal ("Broken assembler. No assembly attempted."); | |
598 | } | |
599 | do | |
600 | { | |
8358c818 ILT |
601 | if (mips_opcodes[i].pinfo != INSN_MACRO |
602 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
603 | != mips_opcodes[i].match)) | |
670a50eb ILT |
604 | { |
605 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
606 | mips_opcodes[i].name, mips_opcodes[i].args); | |
607 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 608 | } |
670a50eb ILT |
609 | ++i; |
610 | } | |
611 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
612 | } |
613 | ||
becfe05e ILT |
614 | mips_no_prev_insn (); |
615 | ||
1aa6938e ILT |
616 | mips_gprmask = 0; |
617 | mips_cprmask[0] = 0; | |
618 | mips_cprmask[1] = 0; | |
619 | mips_cprmask[2] = 0; | |
620 | mips_cprmask[3] = 0; | |
621 | ||
8358c818 ILT |
622 | /* set the default alignment for the text section (2**2) */ |
623 | record_alignment (text_section, 2); | |
624 | ||
abdad6bc ILT |
625 | /* FIXME: This should be handled in a different way. */ |
626 | target_big_endian = byte_order == BIG_ENDIAN; | |
627 | ||
88225433 | 628 | #ifdef GPOPT |
8358c818 ILT |
629 | bfd_set_gp_size (stdoutput, g_switch_value); |
630 | #endif | |
631 | ||
f2a663d3 | 632 | #ifdef OBJ_ELF |
0dd2d296 ILT |
633 | /* Sections must be aligned to 16 byte boundaries. */ |
634 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
635 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
636 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
637 | ||
638 | /* Create a .reginfo section for register masks and a .mdebug | |
639 | section for debugging information. */ | |
f2a663d3 ILT |
640 | { |
641 | segT seg; | |
642 | subsegT subseg; | |
0dd2d296 | 643 | segT sec; |
f2a663d3 ILT |
644 | |
645 | seg = now_seg; | |
646 | subseg = now_subseg; | |
0dd2d296 | 647 | sec = subseg_new (".reginfo", (subsegT) 0); |
f2a663d3 | 648 | |
04cb3372 ILT |
649 | /* The ABI says this section should be loaded so that the running |
650 | program can access it. */ | |
0dd2d296 ILT |
651 | (void) bfd_set_section_flags (stdoutput, sec, |
652 | (SEC_ALLOC | SEC_LOAD | |
653 | | SEC_READONLY | SEC_DATA)); | |
654 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
f2a663d3 ILT |
655 | |
656 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
657 | ||
0dd2d296 ILT |
658 | #ifdef ECOFF_DEBUGGING |
659 | sec = subseg_new (".mdebug", (subsegT) 0); | |
660 | (void) bfd_set_section_flags (stdoutput, sec, | |
661 | SEC_HAS_CONTENTS | SEC_READONLY); | |
662 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
663 | #endif | |
664 | ||
f2a663d3 ILT |
665 | subseg_set (seg, subseg); |
666 | } | |
667 | #endif /* OBJ_ELF */ | |
668 | ||
0dd2d296 | 669 | #ifndef ECOFF_DEBUGGING |
670a50eb | 670 | md_obj_begin (); |
3d3c5039 ILT |
671 | #endif |
672 | } | |
673 | ||
674 | void | |
13fe1379 | 675 | md_mips_end () |
3d3c5039 | 676 | { |
0dd2d296 | 677 | #ifndef ECOFF_DEBUGGING |
3d3c5039 ILT |
678 | md_obj_end (); |
679 | #endif | |
680 | } | |
681 | ||
682 | void | |
670a50eb ILT |
683 | md_assemble (str) |
684 | char *str; | |
3d3c5039 | 685 | { |
670a50eb | 686 | struct mips_cl_insn insn; |
3d3c5039 | 687 | |
5ac34ac3 ILT |
688 | imm_expr.X_op = O_absent; |
689 | offset_expr.X_op = O_absent; | |
3d3c5039 | 690 | |
670a50eb ILT |
691 | mips_ip (str, &insn); |
692 | if (insn_error) | |
693 | { | |
694 | as_bad ("%s `%s'", insn_error, str); | |
695 | return; | |
696 | } | |
697 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
698 | { | |
699 | macro (&insn); | |
3d3c5039 | 700 | } |
670a50eb ILT |
701 | else |
702 | { | |
5ac34ac3 | 703 | if (imm_expr.X_op != O_absent) |
0dd2d296 | 704 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc); |
5ac34ac3 | 705 | else if (offset_expr.X_op != O_absent) |
0dd2d296 | 706 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc); |
670a50eb | 707 | else |
0dd2d296 | 708 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED); |
3d3c5039 ILT |
709 | } |
710 | } | |
711 | ||
becfe05e ILT |
712 | /* See whether instruction IP reads register REG. If FPR is non-zero, |
713 | REG is a floating point register. */ | |
714 | ||
715 | static int | |
716 | insn_uses_reg (ip, reg, fpr) | |
717 | struct mips_cl_insn *ip; | |
604633ae | 718 | unsigned int reg; |
becfe05e ILT |
719 | int fpr; |
720 | { | |
721 | /* Don't report on general register 0, since it never changes. */ | |
722 | if (! fpr && reg == 0) | |
723 | return 0; | |
724 | ||
725 | if (fpr) | |
726 | { | |
727 | /* If we are called with either $f0 or $f1, we must check $f0. | |
728 | This is not optimal, because it will introduce an unnecessary | |
729 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
730 | need to distinguish reading both $f0 and $f1 or just one of | |
731 | them. Note that we don't have to check the other way, | |
732 | because there is no instruction that sets both $f0 and $f1 | |
733 | and requires a delay. */ | |
734 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
735 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
736 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
737 | return 1; |
738 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
739 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
740 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
741 | return 1; |
742 | } | |
743 | else | |
744 | { | |
745 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
746 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
747 | return 1; | |
748 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
749 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
750 | return 1; | |
751 | } | |
752 | ||
753 | return 0; | |
754 | } | |
755 | ||
0dd2d296 ILT |
756 | /* Output an instruction. PLACE is where to put the instruction; if |
757 | it is NULL, this uses frag_more to get room. IP is the instruction | |
758 | information. ADDRESS_EXPR is an operand of the instruction to be | |
759 | used with RELOC_TYPE. */ | |
3d3c5039 | 760 | |
3d3c5039 | 761 | static void |
0dd2d296 ILT |
762 | append_insn (place, ip, address_expr, reloc_type) |
763 | char *place; | |
670a50eb ILT |
764 | struct mips_cl_insn *ip; |
765 | expressionS *address_expr; | |
766 | bfd_reloc_code_real_type reloc_type; | |
3d3c5039 | 767 | { |
1aa6938e | 768 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 769 | char *f; |
becfe05e ILT |
770 | fixS *fixp; |
771 | int nops = 0; | |
3d3c5039 | 772 | |
1aa6938e ILT |
773 | prev_pinfo = prev_insn.insn_mo->pinfo; |
774 | pinfo = ip->insn_mo->pinfo; | |
775 | ||
0dd2d296 | 776 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
777 | { |
778 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 779 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 780 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
781 | (1) a load from memory delay |
782 | (2) a load from a coprocessor delay | |
783 | (3) an unconditional branch delay | |
784 | (4) a conditional branch delay | |
785 | (5) a move to coprocessor register delay | |
786 | (6) a load coprocessor register from memory delay | |
787 | (7) a coprocessor condition code delay | |
788 | (8) a HI/LO special register delay | |
becfe05e ILT |
789 | |
790 | There are a lot of optimizations we could do that we don't. | |
791 | In particular, we do not, in general, reorder instructions. | |
792 | If you use gcc with optimization, it will reorder | |
793 | instructions and generally do much more optimization then we | |
794 | do here; repeating all that work in the assembler would only | |
795 | benefit hand written assembly code, and does not seem worth | |
796 | it. */ | |
797 | ||
798 | /* This is how a NOP is emitted. */ | |
799 | #define emit_nop() md_number_to_chars (frag_more (4), 0, 4) | |
800 | ||
801 | /* The previous insn might require a delay slot, depending upon | |
802 | the contents of the current insn. */ | |
1aa6938e | 803 | if ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
8358c818 | 804 | || (mips_isa < 2 |
1aa6938e | 805 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))) |
8358c818 ILT |
806 | { |
807 | /* A load from a coprocessor or from memory. All load | |
808 | delays delay the use of general register rt for one | |
809 | instruction on the r3000. The r6000 and r4000 use | |
810 | interlocks. */ | |
1aa6938e | 811 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
812 | if (mips_optimize == 0 |
813 | || insn_uses_reg (ip, | |
814 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
815 | & OP_MASK_RT), | |
816 | 0)) | |
becfe05e ILT |
817 | ++nops; |
818 | } | |
1aa6938e | 819 | else if ((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
8358c818 | 820 | || (mips_isa < 2 |
1aa6938e | 821 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))) |
becfe05e ILT |
822 | { |
823 | /* A generic coprocessor delay. The previous instruction | |
824 | modified a coprocessor general or control register. If | |
825 | it modified a control register, we need to avoid any | |
826 | coprocessor instruction (this is probably not always | |
827 | required, but it sometimes is). If it modified a general | |
828 | register, we avoid using that register. | |
829 | ||
8358c818 ILT |
830 | On the r6000 and r4000 loading a coprocessor register |
831 | from memory is interlocked, and does not require a delay. | |
832 | ||
becfe05e ILT |
833 | This case is not handled very well. There is no special |
834 | knowledge of CP0 handling, and the coprocessors other | |
835 | than the floating point unit are not distinguished at | |
836 | all. */ | |
1aa6938e | 837 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 838 | { |
0aa07269 ILT |
839 | if (mips_optimize == 0 |
840 | || insn_uses_reg (ip, | |
8358c818 ILT |
841 | ((prev_insn.insn_opcode >> OP_SH_FT) |
842 | & OP_MASK_FT), | |
0aa07269 | 843 | 1)) |
becfe05e ILT |
844 | ++nops; |
845 | } | |
1aa6938e | 846 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 847 | { |
0aa07269 ILT |
848 | if (mips_optimize == 0 |
849 | || insn_uses_reg (ip, | |
8358c818 ILT |
850 | ((prev_insn.insn_opcode >> OP_SH_FS) |
851 | & OP_MASK_FS), | |
0aa07269 | 852 | 1)) |
becfe05e ILT |
853 | ++nops; |
854 | } | |
855 | else | |
856 | { | |
857 | /* We don't know exactly what the previous instruction | |
858 | does. If the current instruction uses a coprocessor | |
859 | register, we must insert a NOP. If previous | |
860 | instruction may set the condition codes, and the | |
861 | current instruction uses them, we must insert two | |
862 | NOPS. */ | |
0aa07269 | 863 | if (mips_optimize == 0 |
1aa6938e ILT |
864 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
865 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 866 | nops += 2; |
1aa6938e | 867 | else if (pinfo & INSN_COP) |
becfe05e ILT |
868 | ++nops; |
869 | } | |
870 | } | |
1aa6938e | 871 | else if (prev_pinfo & INSN_WRITE_COND_CODE) |
becfe05e ILT |
872 | { |
873 | /* The previous instruction sets the coprocessor condition | |
874 | codes, but does not require a general coprocessor delay | |
875 | (this means it is a floating point comparison | |
876 | instruction). If this instruction uses the condition | |
877 | codes, we need to insert a single NOP. */ | |
0aa07269 | 878 | if (mips_optimize == 0 |
1aa6938e | 879 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
880 | ++nops; |
881 | } | |
1aa6938e | 882 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
883 | { |
884 | /* The previous instruction reads the LO register; if the | |
885 | current instruction writes to the LO register, we must | |
886 | insert two NOPS. */ | |
0aa07269 | 887 | if (mips_optimize == 0 |
1aa6938e | 888 | || (pinfo & INSN_WRITE_LO)) |
becfe05e ILT |
889 | nops += 2; |
890 | } | |
891 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
892 | { | |
893 | /* The previous instruction reads the HI register; if the | |
894 | current instruction writes to the HI register, we must | |
895 | insert a NOP. */ | |
0aa07269 | 896 | if (mips_optimize == 0 |
1aa6938e | 897 | || (pinfo & INSN_WRITE_HI)) |
becfe05e ILT |
898 | nops += 2; |
899 | } | |
900 | ||
901 | /* There are two cases which require two intervening | |
902 | instructions: 1) setting the condition codes using a move to | |
903 | coprocessor instruction which requires a general coprocessor | |
904 | delay and then reading the condition codes 2) reading the HI | |
905 | or LO register and then writing to it. If we are not already | |
906 | emitting a NOP instruction, we must check for these cases | |
907 | compared to the instruction previous to the previous | |
908 | instruction. */ | |
909 | if (nops == 0 | |
8358c818 | 910 | && (((prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 911 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
1aa6938e | 912 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e | 913 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
1aa6938e | 914 | && (pinfo & INSN_WRITE_LO)) |
becfe05e | 915 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1aa6938e | 916 | && (pinfo & INSN_WRITE_HI)))) |
becfe05e ILT |
917 | ++nops; |
918 | ||
8c63448a ILT |
919 | /* The r4600 (ORION) chip has a bug: at least four instructions |
920 | are required between an instruction which accesses memory and | |
921 | a certain set of CACHE instructions. Handle that now. */ | |
922 | if (mips_cpu == 4600 | |
923 | && insns_since_cache_access != 0 | |
924 | && 5 - insns_since_cache_access > nops | |
925 | && ((ip->insn_opcode & 0xffff0000) == 0xbc0d0000 | |
926 | || (ip->insn_opcode & 0xffff0000) == 0xbc110000 | |
927 | || (ip->insn_opcode & 0xfc1f0000) == 0xbc150000 | |
928 | || (ip->insn_opcode & 0xffff0000) == 0xbc190000)) | |
929 | nops = 5 - insns_since_cache_access; | |
930 | ||
0dd2d296 ILT |
931 | /* If we are being given a nop instruction, don't bother with |
932 | one of the nops we would otherwise output. This will only | |
933 | happen when a nop instruction is used with mips_optimize set | |
934 | to 0. */ | |
935 | if (nops > 0 && ip->insn_opcode == 0) | |
936 | --nops; | |
937 | ||
becfe05e ILT |
938 | /* Now emit the right number of NOP instructions. */ |
939 | if (nops > 0) | |
940 | { | |
8c63448a ILT |
941 | int i; |
942 | ||
943 | for (i = 0; i < nops; i++) | |
becfe05e | 944 | emit_nop (); |
af255ca0 ILT |
945 | if (listing) |
946 | listing_prev_line (); | |
becfe05e ILT |
947 | if (insn_label != NULL) |
948 | { | |
949 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
950 | insn_label->sy_frag = frag_now; | |
604633ae | 951 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e ILT |
952 | } |
953 | } | |
954 | } | |
955 | ||
0dd2d296 ILT |
956 | if (place == NULL) |
957 | f = frag_more (4); | |
958 | else | |
959 | f = place; | |
becfe05e | 960 | fixp = NULL; |
670a50eb ILT |
961 | if (address_expr != NULL) |
962 | { | |
5ac34ac3 | 963 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
964 | { |
965 | switch (reloc_type) | |
966 | { | |
3d3c5039 | 967 | case BFD_RELOC_32: |
670a50eb ILT |
968 | ip->insn_opcode |= address_expr->X_add_number; |
969 | break; | |
3d3c5039 ILT |
970 | |
971 | case BFD_RELOC_LO16: | |
670a50eb ILT |
972 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
973 | break; | |
3d3c5039 ILT |
974 | |
975 | case BFD_RELOC_MIPS_JMP: | |
976 | case BFD_RELOC_16_PCREL_S2: | |
670a50eb | 977 | goto need_reloc; |
3d3c5039 ILT |
978 | |
979 | default: | |
670a50eb | 980 | internalError (); |
3d3c5039 | 981 | } |
670a50eb ILT |
982 | } |
983 | else | |
984 | { | |
985 | assert (reloc_type != BFD_RELOC_UNUSED); | |
3d3c5039 | 986 | need_reloc: |
0dd2d296 ILT |
987 | /* Don't generate a reloc if we are writing into a variant |
988 | frag. */ | |
989 | if (place == NULL) | |
990 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
991 | address_expr, | |
992 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
993 | reloc_type); | |
3d3c5039 ILT |
994 | } |
995 | } | |
becfe05e | 996 | |
670a50eb ILT |
997 | md_number_to_chars (f, ip->insn_opcode, 4); |
998 | ||
1aa6938e ILT |
999 | /* Update the register mask information. */ |
1000 | if (pinfo & INSN_WRITE_GPR_D) | |
1001 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1002 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1003 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1004 | if (pinfo & INSN_READ_GPR_S) | |
1005 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1006 | if (pinfo & INSN_WRITE_GPR_31) | |
1007 | mips_gprmask |= 1 << 31; | |
1008 | if (pinfo & INSN_WRITE_FPR_D) | |
1009 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1010 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1011 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1012 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1013 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1014 | if (pinfo & INSN_COP) | |
1015 | { | |
1016 | /* We don't keep enough information to sort these cases out. */ | |
1017 | } | |
1018 | /* Never set the bit for $0, which is always zero. */ | |
1019 | mips_gprmask &=~ 1 << 0; | |
1020 | ||
0dd2d296 | 1021 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1022 | { |
becfe05e ILT |
1023 | /* Filling the branch delay slot is more complex. We try to |
1024 | switch the branch with the previous instruction, which we can | |
1025 | do if the previous instruction does not set up a condition | |
1026 | that the branch tests and if the branch is not itself the | |
1027 | target of any branch. */ | |
1aa6938e ILT |
1028 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1029 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1030 | { |
0aa07269 | 1031 | if (mips_optimize < 2 |
19ed8960 ILT |
1032 | /* If we have seen .set volatile or .set nomove, don't |
1033 | optimize. */ | |
1034 | || mips_nomove != 0 | |
4e95866e ILT |
1035 | /* If we had to emit any NOP instructions, then we |
1036 | already know we can not swap. */ | |
1037 | || nops != 0 | |
becfe05e ILT |
1038 | /* If we don't even know the previous insn, we can not |
1039 | swap. */ | |
1040 | || ! prev_insn_valid | |
1041 | /* If the previous insn is already in a branch delay | |
1042 | slot, then we can not swap. */ | |
1043 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1044 | /* If the previous previous insn was in a .set |
1045 | noreorder, we can't swap. Actually, the MIPS | |
1046 | assembler will swap in this situation. However, gcc | |
1047 | configured -with-gnu-as will generate code like | |
1048 | .set noreorder | |
1049 | lw $4,XXX | |
1050 | .set reorder | |
1051 | INSN | |
1052 | bne $4,$0,foo | |
1053 | in which we can not swap the bne and INSN. If gcc is | |
1054 | not configured -with-gnu-as, it does not output the | |
1055 | .set pseudo-ops. We don't have to check | |
1056 | prev_insn_unreordered, because prev_insn_valid will | |
1057 | be 0 in that case. We don't want to use | |
1058 | prev_prev_insn_valid, because we do want to be able | |
1059 | to swap at the start of a function. */ | |
1060 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1061 | /* If the branch is itself the target of a branch, we |
1062 | can not swap. We cheat on this; all we check for is | |
1063 | whether there is a label on this instruction. If | |
1064 | there are any branches to anything other than a | |
1065 | label, users must use .set noreorder. */ | |
1066 | || insn_label != NULL | |
777ad64d ILT |
1067 | /* If the previous instruction is in a variant frag, we |
1068 | can not do the swap. */ | |
1069 | || prev_insn_frag->fr_type == rs_machine_dependent | |
becfe05e ILT |
1070 | /* If the branch reads the condition codes, we don't |
1071 | even try to swap, because in the sequence | |
1072 | ctc1 $X,$31 | |
1073 | INSN | |
1074 | INSN | |
1075 | bc1t LABEL | |
1076 | we can not swap, and I don't feel like handling that | |
1077 | case. */ | |
1aa6938e | 1078 | || (pinfo & INSN_READ_COND_CODE) |
becfe05e ILT |
1079 | /* We can not swap with an instruction that requires a |
1080 | delay slot, becase the target of the branch might | |
1081 | interfere with that instruction. */ | |
1aa6938e | 1082 | || (prev_pinfo |
8358c818 ILT |
1083 | & (INSN_LOAD_COPROC_DELAY |
1084 | | INSN_COPROC_MOVE_DELAY | |
becfe05e ILT |
1085 | | INSN_WRITE_COND_CODE |
1086 | | INSN_READ_LO | |
1087 | | INSN_READ_HI)) | |
8358c818 | 1088 | || (mips_isa < 2 |
1aa6938e | 1089 | && (prev_pinfo |
8358c818 ILT |
1090 | & (INSN_LOAD_MEMORY_DELAY |
1091 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1092 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1093 | || (prev_pinfo |
6e8dda9c ILT |
1094 | & (INSN_UNCOND_BRANCH_DELAY |
1095 | | INSN_COND_BRANCH_DELAY | |
1096 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1097 | /* We do not swap with a trap instruction, since it |
1098 | complicates trap handlers to have the trap | |
1099 | instruction be in a delay slot. */ | |
1aa6938e | 1100 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1101 | /* If the branch reads a register that the previous |
1102 | instruction sets, we can not swap. */ | |
1aa6938e | 1103 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
1104 | && insn_uses_reg (ip, |
1105 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1106 | & OP_MASK_RT), | |
1107 | 0)) | |
1aa6938e | 1108 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1109 | && insn_uses_reg (ip, |
1110 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1111 | & OP_MASK_RD), | |
1112 | 0)) | |
1849d646 ILT |
1113 | /* If the branch writes a register that the previous |
1114 | instruction sets, we can not swap (we know that | |
1115 | branches write only to RD or to $31). */ | |
1aa6938e ILT |
1116 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
1117 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1118 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1119 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1120 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1121 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1122 | & OP_MASK_RT) | |
1123 | == 31)))) | |
1aa6938e ILT |
1124 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
1125 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1126 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1127 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1128 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1129 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1130 | & OP_MASK_RD) | |
1131 | == 31)))) | |
becfe05e ILT |
1132 | /* If the branch writes a register that the previous |
1133 | instruction reads, we can not swap (we know that | |
1134 | branches only write to RD or to $31). */ | |
1aa6938e | 1135 | || ((pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1136 | && insn_uses_reg (&prev_insn, |
1137 | ((ip->insn_opcode >> OP_SH_RD) | |
1138 | & OP_MASK_RD), | |
1139 | 0)) | |
1aa6938e | 1140 | || ((pinfo & INSN_WRITE_GPR_31) |
becfe05e | 1141 | && insn_uses_reg (&prev_insn, 31, 0)) |
5b63f465 ILT |
1142 | /* If we are generating embedded PIC code, the branch |
1143 | might be expanded into a sequence which uses $at, so | |
1144 | we can't swap with an instruction which reads it. */ | |
1145 | || (mips_pic == EMBEDDED_PIC | |
1146 | && insn_uses_reg (&prev_insn, AT, 0)) | |
becfe05e ILT |
1147 | /* If the previous previous instruction has a load |
1148 | delay, and sets a register that the branch reads, we | |
1149 | can not swap. */ | |
8358c818 ILT |
1150 | || (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1151 | || (mips_isa < 2 | |
1152 | && (prev_prev_insn.insn_mo->pinfo | |
1153 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1154 | && insn_uses_reg (ip, |
1155 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1156 | & OP_MASK_RT), | |
1157 | 0))) | |
1158 | { | |
1159 | /* We could do even better for unconditional branches to | |
1160 | portions of this object file; we could pick up the | |
1161 | instruction at the destination, put it in the delay | |
1162 | slot, and bump the destination address. */ | |
1163 | emit_nop (); | |
1164 | /* Update the previous insn information. */ | |
1165 | prev_prev_insn = *ip; | |
1166 | prev_insn.insn_mo = &dummy_opcode; | |
1167 | } | |
1168 | else | |
1169 | { | |
1170 | char *prev_f; | |
1171 | char temp[4]; | |
1172 | ||
1173 | /* It looks like we can actually do the swap. */ | |
1174 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1175 | memcpy (temp, prev_f, 4); | |
1176 | memcpy (prev_f, f, 4); | |
1177 | memcpy (f, temp, 4); | |
1178 | if (prev_insn_fixp) | |
1179 | { | |
1180 | prev_insn_fixp->fx_frag = frag_now; | |
1181 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1182 | } | |
1183 | if (fixp) | |
1184 | { | |
1185 | fixp->fx_frag = prev_insn_frag; | |
1186 | fixp->fx_where = prev_insn_where; | |
1187 | } | |
1188 | /* Update the previous insn information; leave prev_insn | |
1189 | unchanged. */ | |
1190 | prev_prev_insn = *ip; | |
1191 | } | |
1192 | prev_insn_is_delay_slot = 1; | |
1193 | ||
1194 | /* If that was an unconditional branch, forget the previous | |
1195 | insn information. */ | |
1aa6938e | 1196 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1197 | { |
1198 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1199 | prev_insn.insn_mo = &dummy_opcode; | |
1200 | } | |
1201 | } | |
1aa6938e | 1202 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1203 | { |
1204 | /* We don't yet optimize a branch likely. What we should do | |
1205 | is look at the target, copy the instruction found there | |
1206 | into the delay slot, and increment the branch to jump to | |
1207 | the next instruction. */ | |
1208 | emit_nop (); | |
1209 | /* Update the previous insn information. */ | |
1210 | prev_prev_insn = *ip; | |
1211 | prev_insn.insn_mo = &dummy_opcode; | |
1212 | } | |
becfe05e | 1213 | else |
670a50eb | 1214 | { |
becfe05e ILT |
1215 | /* Update the previous insn information. */ |
1216 | if (nops > 0) | |
1217 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1218 | else | |
1219 | prev_prev_insn = prev_insn; | |
1220 | prev_insn = *ip; | |
1221 | ||
1222 | /* Any time we see a branch, we always fill the delay slot | |
1223 | immediately; since this insn is not a branch, we know it | |
1224 | is not in a delay slot. */ | |
1225 | prev_insn_is_delay_slot = 0; | |
1226 | } | |
1227 | ||
4e95866e ILT |
1228 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1229 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1230 | prev_insn_frag = frag_now; |
1231 | prev_insn_where = f - frag_now->fr_literal; | |
1232 | prev_insn_fixp = fixp; | |
1233 | prev_insn_valid = 1; | |
8c63448a ILT |
1234 | if ((pinfo & INSN_LOAD_MEMORY_DELAY) != 0 |
1235 | || (pinfo & INSN_STORE_MEMORY) != 0) | |
1236 | insns_since_cache_access = 1; | |
1237 | else if (insns_since_cache_access != 0) | |
1238 | ++insns_since_cache_access; | |
becfe05e | 1239 | } |
3d3c5039 | 1240 | |
becfe05e ILT |
1241 | /* We just output an insn, so the next one doesn't have a label. */ |
1242 | insn_label = NULL; | |
1243 | } | |
1244 | ||
1245 | /* This function forgets that there was any previous instruction or | |
1246 | label. */ | |
1247 | ||
1248 | static void | |
1249 | mips_no_prev_insn () | |
1250 | { | |
1251 | prev_insn.insn_mo = &dummy_opcode; | |
1252 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1253 | prev_insn_valid = 0; | |
1254 | prev_insn_is_delay_slot = 0; | |
4e95866e ILT |
1255 | prev_insn_unreordered = 0; |
1256 | prev_prev_insn_unreordered = 0; | |
becfe05e ILT |
1257 | insn_label = NULL; |
1258 | } | |
1259 | ||
1260 | /* This function must be called whenever we turn on noreorder or emit | |
1261 | something other than instructions. It inserts any NOPS which might | |
1262 | be needed by the previous instruction, and clears the information | |
1263 | kept for the previous instructions. */ | |
1264 | ||
1265 | static void | |
1266 | mips_emit_delays () | |
1267 | { | |
1268 | if (! mips_noreorder) | |
1269 | { | |
1270 | int nop; | |
1271 | ||
1272 | nop = 0; | |
8358c818 ILT |
1273 | if ((prev_insn.insn_mo->pinfo |
1274 | & (INSN_LOAD_COPROC_DELAY | |
1275 | | INSN_COPROC_MOVE_DELAY | |
1276 | | INSN_WRITE_COND_CODE | |
1277 | | INSN_READ_LO | |
1278 | | INSN_READ_HI)) | |
1279 | || (mips_isa < 2 | |
1280 | && (prev_insn.insn_mo->pinfo | |
1281 | & (INSN_LOAD_MEMORY_DELAY | |
1282 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1283 | { |
1284 | nop = 1; | |
1285 | if ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1286 | || (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1287 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)) | |
1288 | emit_nop (); | |
1289 | } | |
1290 | else if ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1291 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1292 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)) | |
1293 | nop = 1; | |
1294 | if (nop) | |
670a50eb | 1295 | { |
becfe05e ILT |
1296 | emit_nop (); |
1297 | if (insn_label != NULL) | |
1298 | { | |
1299 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1300 | insn_label->sy_frag = frag_now; | |
604633ae | 1301 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e | 1302 | } |
3d3c5039 ILT |
1303 | } |
1304 | } | |
0221ddf7 ILT |
1305 | |
1306 | mips_no_prev_insn (); | |
3d3c5039 ILT |
1307 | } |
1308 | ||
670a50eb ILT |
1309 | /* Build an instruction created by a macro expansion. This is passed |
1310 | a pointer to the count of instructions created so far, an | |
1311 | expression, the name of the instruction to build, an operand format | |
1312 | string, and corresponding arguments. */ | |
1313 | ||
3d3c5039 ILT |
1314 | #ifndef NO_STDARG |
1315 | static void | |
0dd2d296 ILT |
1316 | macro_build (char *place, |
1317 | int *counter, | |
670a50eb | 1318 | expressionS * ep, |
3d3c5039 ILT |
1319 | const char *name, |
1320 | const char *fmt, | |
1321 | ...) | |
1322 | #else /* ! defined (NO_STDARG) */ | |
1323 | static void | |
0dd2d296 ILT |
1324 | macro_build (place, counter, ep, name, fmt, va_alist) |
1325 | char *place; | |
3d3c5039 ILT |
1326 | int *counter; |
1327 | expressionS *ep; | |
1328 | const char *name; | |
1329 | const char *fmt; | |
1330 | va_dcl | |
1331 | #endif /* ! defined (NO_STDARG) */ | |
1332 | { | |
670a50eb ILT |
1333 | struct mips_cl_insn insn; |
1334 | bfd_reloc_code_real_type r; | |
1335 | va_list args; | |
3d3c5039 ILT |
1336 | |
1337 | #ifndef NO_STDARG | |
670a50eb | 1338 | va_start (args, fmt); |
3d3c5039 | 1339 | #else |
670a50eb | 1340 | va_start (args); |
3d3c5039 ILT |
1341 | #endif |
1342 | ||
670a50eb ILT |
1343 | /* |
1344 | * If the macro is about to expand into a second instruction, | |
1345 | * print a warning if needed. We need to pass ip as a parameter | |
1346 | * to generate a better warning message here... | |
1347 | */ | |
0dd2d296 | 1348 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1349 | as_warn ("Macro instruction expanded into multiple instructions"); |
1350 | ||
0dd2d296 ILT |
1351 | if (place == NULL) |
1352 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1353 | |
1354 | r = BFD_RELOC_UNUSED; | |
1355 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1356 | assert (insn.insn_mo); | |
1357 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1358 | ||
9226253a ILT |
1359 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
1360 | || insn.insn_mo->pinfo == INSN_MACRO) | |
670a50eb ILT |
1361 | { |
1362 | ++insn.insn_mo; | |
1363 | assert (insn.insn_mo->name); | |
1364 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 1365 | } |
670a50eb ILT |
1366 | insn.insn_opcode = insn.insn_mo->match; |
1367 | for (;;) | |
1368 | { | |
1369 | switch (*fmt++) | |
1370 | { | |
3d3c5039 | 1371 | case '\0': |
670a50eb | 1372 | break; |
3d3c5039 ILT |
1373 | |
1374 | case ',': | |
1375 | case '(': | |
1376 | case ')': | |
670a50eb | 1377 | continue; |
3d3c5039 ILT |
1378 | |
1379 | case 't': | |
1380 | case 'w': | |
918692a5 | 1381 | case 'E': |
670a50eb ILT |
1382 | insn.insn_opcode |= va_arg (args, int) << 16; |
1383 | continue; | |
3d3c5039 ILT |
1384 | |
1385 | case 'c': | |
1386 | case 'T': | |
1387 | case 'W': | |
670a50eb ILT |
1388 | insn.insn_opcode |= va_arg (args, int) << 16; |
1389 | continue; | |
3d3c5039 ILT |
1390 | |
1391 | case 'd': | |
918692a5 | 1392 | case 'G': |
670a50eb ILT |
1393 | insn.insn_opcode |= va_arg (args, int) << 11; |
1394 | continue; | |
3d3c5039 ILT |
1395 | |
1396 | case 'V': | |
1397 | case 'S': | |
670a50eb ILT |
1398 | insn.insn_opcode |= va_arg (args, int) << 11; |
1399 | continue; | |
3d3c5039 | 1400 | |
ff3a5c18 ILT |
1401 | case 'z': |
1402 | continue; | |
1403 | ||
3d3c5039 | 1404 | case '<': |
670a50eb ILT |
1405 | insn.insn_opcode |= va_arg (args, int) << 6; |
1406 | continue; | |
3d3c5039 ILT |
1407 | |
1408 | case 'D': | |
670a50eb ILT |
1409 | insn.insn_opcode |= va_arg (args, int) << 6; |
1410 | continue; | |
3d3c5039 | 1411 | |
918692a5 ILT |
1412 | case 'B': |
1413 | insn.insn_opcode |= va_arg (args, int) << 6; | |
1414 | continue; | |
1415 | ||
3d3c5039 ILT |
1416 | case 'b': |
1417 | case 's': | |
1418 | case 'r': | |
1419 | case 'v': | |
670a50eb ILT |
1420 | insn.insn_opcode |= va_arg (args, int) << 21; |
1421 | continue; | |
3d3c5039 ILT |
1422 | |
1423 | case 'i': | |
1424 | case 'j': | |
1425 | case 'o': | |
9226253a | 1426 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
1427 | assert (r == BFD_RELOC_MIPS_GPREL |
1428 | || r == BFD_RELOC_MIPS_LITERAL | |
1429 | || r == BFD_RELOC_LO16 | |
1430 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c ILT |
1431 | || r == BFD_RELOC_MIPS_CALL16 |
1432 | || (ep->X_op == O_subtract | |
1433 | && now_seg == text_section | |
1434 | && S_GET_SEGMENT (ep->X_op_symbol) == text_section | |
1435 | && r == BFD_RELOC_PCREL_LO16)); | |
670a50eb | 1436 | continue; |
3d3c5039 | 1437 | |
6e8dda9c | 1438 | case 'u': |
ecd4ca1c ILT |
1439 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
1440 | assert (ep != NULL | |
1441 | && (ep->X_op == O_constant | |
1442 | || (ep->X_op == O_symbol | |
1443 | && (r == BFD_RELOC_HI16_S | |
1444 | || r == BFD_RELOC_HI16)) | |
1445 | || (ep->X_op == O_subtract | |
1446 | && now_seg == text_section | |
1447 | && S_GET_SEGMENT (ep->X_op_symbol) == text_section | |
1448 | && r == BFD_RELOC_PCREL_HI16_S))); | |
1449 | if (ep->X_op == O_constant) | |
1450 | { | |
1451 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
1452 | ep = NULL; | |
1453 | r = BFD_RELOC_UNUSED; | |
1454 | } | |
6e8dda9c ILT |
1455 | continue; |
1456 | ||
3d3c5039 | 1457 | case 'p': |
670a50eb ILT |
1458 | assert (ep != NULL); |
1459 | /* | |
1460 | * This allows macro() to pass an immediate expression for | |
1461 | * creating short branches without creating a symbol. | |
1462 | * Note that the expression still might come from the assembly | |
1463 | * input, in which case the value is not checked for range nor | |
1464 | * is a relocation entry generated (yuck). | |
1465 | */ | |
5ac34ac3 | 1466 | if (ep->X_op == O_constant) |
670a50eb ILT |
1467 | { |
1468 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
1469 | ep = NULL; | |
1470 | } | |
1471 | else | |
1472 | r = BFD_RELOC_16_PCREL_S2; | |
1473 | continue; | |
3d3c5039 | 1474 | |
9226253a ILT |
1475 | case 'a': |
1476 | assert (ep != NULL); | |
1477 | r = BFD_RELOC_MIPS_JMP; | |
1478 | continue; | |
1479 | ||
3d3c5039 | 1480 | default: |
670a50eb | 1481 | internalError (); |
3d3c5039 | 1482 | } |
670a50eb | 1483 | break; |
3d3c5039 | 1484 | } |
670a50eb ILT |
1485 | va_end (args); |
1486 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1487 | ||
0dd2d296 | 1488 | append_insn (place, &insn, ep, r); |
3d3c5039 ILT |
1489 | } |
1490 | ||
1491 | /* | |
1492 | * Generate a "lui" instruction. | |
1493 | */ | |
1494 | static void | |
0dd2d296 ILT |
1495 | macro_build_lui (place, counter, ep, regnum) |
1496 | char *place; | |
3d3c5039 ILT |
1497 | int *counter; |
1498 | expressionS *ep; | |
1499 | int regnum; | |
1500 | { | |
670a50eb ILT |
1501 | expressionS high_expr; |
1502 | struct mips_cl_insn insn; | |
1503 | bfd_reloc_code_real_type r; | |
1504 | CONST char *name = "lui"; | |
1505 | CONST char *fmt = "t,u"; | |
1506 | ||
0dd2d296 ILT |
1507 | if (place == NULL) |
1508 | high_expr = *ep; | |
1509 | else | |
1510 | { | |
1511 | high_expr.X_op = O_constant; | |
1512 | high_expr.X_add_number = 0; | |
1513 | } | |
670a50eb | 1514 | |
5ac34ac3 | 1515 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
1516 | { |
1517 | /* we can compute the instruction now without a relocation entry */ | |
1518 | if (high_expr.X_add_number & 0x8000) | |
1519 | high_expr.X_add_number += 0x10000; | |
1520 | high_expr.X_add_number = | |
1521 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
1522 | r = BFD_RELOC_UNUSED; | |
1523 | } | |
1524 | else | |
0dd2d296 ILT |
1525 | { |
1526 | assert (ep->X_op == O_symbol); | |
1527 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 1528 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
1529 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
1530 | r = BFD_RELOC_HI16_S; | |
1531 | } | |
670a50eb ILT |
1532 | |
1533 | /* | |
1534 | * If the macro is about to expand into a second instruction, | |
1535 | * print a warning if needed. We need to pass ip as a parameter | |
1536 | * to generate a better warning message here... | |
1537 | */ | |
0dd2d296 | 1538 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1539 | as_warn ("Macro instruction expanded into multiple instructions"); |
1540 | ||
0dd2d296 ILT |
1541 | if (place == NULL) |
1542 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1543 | |
1544 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1545 | assert (insn.insn_mo); | |
1546 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1547 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
1548 | ||
0dd2d296 | 1549 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
1550 | if (r == BFD_RELOC_UNUSED) |
1551 | { | |
1552 | insn.insn_opcode |= high_expr.X_add_number; | |
0dd2d296 | 1553 | append_insn (place, &insn, NULL, r); |
670a50eb ILT |
1554 | } |
1555 | else | |
0dd2d296 | 1556 | append_insn (place, &insn, &high_expr, r); |
3d3c5039 ILT |
1557 | } |
1558 | ||
1559 | /* set_at() | |
1560 | * Generates code to set the $at register to true (one) | |
1561 | * if reg is less than the immediate expression. | |
1562 | */ | |
1563 | static void | |
6e8dda9c | 1564 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
1565 | int *counter; |
1566 | int reg; | |
6e8dda9c | 1567 | int unsignedp; |
3d3c5039 | 1568 | { |
6e8dda9c | 1569 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 1570 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 1571 | unsignedp ? "sltiu" : "slti", |
9226253a | 1572 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 1573 | else |
670a50eb | 1574 | { |
6e8dda9c | 1575 | load_register (counter, AT, &imm_expr); |
0dd2d296 | 1576 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
1577 | unsignedp ? "sltu" : "slt", |
1578 | "d,v,t", AT, reg, AT); | |
670a50eb | 1579 | } |
3d3c5039 ILT |
1580 | } |
1581 | ||
6e8dda9c | 1582 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
1583 | |
1584 | static void | |
19ed8960 | 1585 | check_absolute_expr (ip, ex) |
3d3c5039 | 1586 | struct mips_cl_insn *ip; |
19ed8960 | 1587 | expressionS *ex; |
3d3c5039 | 1588 | { |
19ed8960 | 1589 | if (ex->X_op != O_constant) |
670a50eb | 1590 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
1591 | } |
1592 | ||
1593 | /* load_register() | |
1594 | * This routine generates the least number of instructions neccessary to load | |
1595 | * an absolute expression value into a register. | |
1596 | */ | |
1597 | static void | |
6e8dda9c | 1598 | load_register (counter, reg, ep) |
670a50eb | 1599 | int *counter; |
670a50eb ILT |
1600 | int reg; |
1601 | expressionS *ep; | |
3d3c5039 | 1602 | { |
6e8dda9c ILT |
1603 | assert (ep->X_op == O_constant); |
1604 | if (ep->X_add_number >= -0x8000 && ep->X_add_number < 0x8000) | |
0dd2d296 | 1605 | macro_build ((char *) NULL, counter, ep, |
6e8dda9c | 1606 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 1607 | "t,r,j", reg, 0, (int) BFD_RELOC_LO16); |
6e8dda9c | 1608 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) |
0dd2d296 ILT |
1609 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, |
1610 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
1611 | else if ((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
1612 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
1613 | == ~ (offsetT) 0x7fffffff)) | |
1614 | { | |
ecd4ca1c ILT |
1615 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, |
1616 | (int) BFD_RELOC_HI16); | |
6e8dda9c | 1617 | if ((ep->X_add_number & 0xffff) != 0) |
0dd2d296 | 1618 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, |
9226253a | 1619 | (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
1620 | } |
1621 | else if (mips_isa < 3) | |
670a50eb | 1622 | { |
6e8dda9c | 1623 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 1624 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 1625 | (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
1626 | } |
1627 | else | |
1628 | { | |
1629 | int shift; | |
1630 | expressionS hi32, lo32; | |
1631 | ||
1632 | hi32 = *ep; | |
1633 | shift = 32; | |
1634 | hi32.X_add_number >>= shift; | |
1635 | hi32.X_add_number &= 0xffffffff; | |
1636 | if ((hi32.X_add_number & 0x80000000) != 0) | |
1637 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
1638 | load_register (counter, reg, &hi32); | |
1639 | lo32 = *ep; | |
1640 | lo32.X_add_number &= 0xffffffff; | |
1641 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
0dd2d296 ILT |
1642 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, |
1643 | reg, 0); | |
6e8dda9c ILT |
1644 | else |
1645 | { | |
1646 | expressionS mid16; | |
670a50eb | 1647 | |
0dd2d296 ILT |
1648 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
1649 | reg, 16); | |
6e8dda9c ILT |
1650 | mid16 = lo32; |
1651 | mid16.X_add_number >>= 16; | |
0dd2d296 ILT |
1652 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, |
1653 | reg, (int) BFD_RELOC_LO16); | |
1654 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
1655 | reg, 16); | |
6e8dda9c ILT |
1656 | } |
1657 | if ((lo32.X_add_number & 0xffff) != 0) | |
0dd2d296 | 1658 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, reg, |
9226253a | 1659 | (int) BFD_RELOC_LO16); |
670a50eb | 1660 | } |
3d3c5039 ILT |
1661 | } |
1662 | ||
0dd2d296 ILT |
1663 | /* Load an address into a register. */ |
1664 | ||
1665 | static void | |
1666 | load_address (counter, reg, ep) | |
1667 | int *counter; | |
1668 | int reg; | |
1669 | expressionS *ep; | |
1670 | { | |
1671 | char *p; | |
1672 | ||
1673 | if (ep->X_op != O_constant | |
1674 | && ep->X_op != O_symbol) | |
1675 | { | |
1676 | as_bad ("expression too complex"); | |
1677 | ep->X_op = O_constant; | |
1678 | } | |
1679 | ||
1680 | if (ep->X_op == O_constant) | |
d9aba805 ILT |
1681 | { |
1682 | load_register (counter, reg, ep); | |
1683 | return; | |
1684 | } | |
1685 | ||
1686 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
1687 | { |
1688 | /* If this is a reference to a GP relative symbol, we want | |
1689 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
1690 | Otherwise we want | |
04cb3372 | 1691 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
1692 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
1693 | If we have an addend, we always use the latter form. */ | |
1694 | if (ep->X_add_number != 0) | |
1695 | p = NULL; | |
1696 | else | |
1697 | { | |
8ea7f4e8 | 1698 | frag_grow (20); |
0dd2d296 ILT |
1699 | macro_build ((char *) NULL, counter, ep, |
1700 | mips_isa < 3 ? "addiu" : "daddiu", | |
1701 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
1702 | p = frag_var (rs_machine_dependent, 8, 0, | |
1703 | RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros), | |
1704 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
1705 | } | |
1706 | macro_build_lui (p, counter, ep, reg); | |
1707 | if (p != NULL) | |
1708 | p += 4; | |
1709 | macro_build (p, counter, ep, | |
1710 | mips_isa < 3 ? "addiu" : "daddiu", | |
1711 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1712 | } | |
d9aba805 | 1713 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
1714 | { |
1715 | expressionS ex; | |
1716 | ||
1717 | /* If this is a reference to an external symbol, we want | |
1718 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1719 | Otherwise we want | |
1720 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1721 | nop | |
1722 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 1723 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
1724 | ex.X_add_number = ep->X_add_number; |
1725 | ep->X_add_number = 0; | |
8ea7f4e8 | 1726 | frag_grow (20); |
0dd2d296 ILT |
1727 | macro_build ((char *) NULL, counter, ep, |
1728 | mips_isa < 3 ? "lw" : "ld", | |
1729 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
1730 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
1731 | p = frag_var (rs_machine_dependent, 4, 0, | |
1732 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
1733 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
1734 | macro_build (p, counter, ep, | |
1735 | mips_isa < 3 ? "addiu" : "daddiu", | |
1736 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1737 | if (ex.X_add_number != 0) | |
1738 | { | |
1739 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
1740 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
1741 | ex.X_op = O_constant; | |
1742 | macro_build (p, counter, &ex, | |
1743 | mips_isa < 3 ? "addiu" : "daddiu", | |
1744 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1745 | } | |
d9aba805 ILT |
1746 | } |
1747 | else if (mips_pic == EMBEDDED_PIC) | |
1748 | { | |
1749 | /* We always do | |
1750 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
1751 | */ | |
1752 | macro_build ((char *) NULL, counter, ep, | |
1753 | mips_isa < 3 ? "addiu" : "daddiu", | |
1754 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
1755 | } | |
1756 | else | |
1757 | abort (); | |
0dd2d296 ILT |
1758 | } |
1759 | ||
3d3c5039 ILT |
1760 | /* |
1761 | * Build macros | |
1762 | * This routine implements the seemingly endless macro or synthesized | |
1763 | * instructions and addressing modes in the mips assembly language. Many | |
1764 | * of these macros are simple and are similar to each other. These could | |
1765 | * probably be handled by some kind of table or grammer aproach instead of | |
1766 | * this verbose method. Others are not simple macros but are more like | |
1767 | * optimizing code generation. | |
1768 | * One interesting optimization is when several store macros appear | |
1769 | * consecutivly that would load AT with the upper half of the same address. | |
1770 | * The ensuing load upper instructions are ommited. This implies some kind | |
1771 | * of global optimization. We currently only optimize within a single macro. | |
1772 | * For many of the load and store macros if the address is specified as a | |
1773 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
1774 | * first load register 'at' with zero and use it as the base register. The | |
1775 | * mips assembler simply uses register $zero. Just one tiny optimization | |
1776 | * we're missing. | |
1777 | */ | |
1778 | static void | |
1779 | macro (ip) | |
1780 | struct mips_cl_insn *ip; | |
1781 | { | |
670a50eb ILT |
1782 | register int treg, sreg, dreg, breg; |
1783 | int tempreg; | |
1784 | int mask; | |
1785 | int icnt = 0; | |
1786 | int used_at; | |
670a50eb ILT |
1787 | expressionS expr1; |
1788 | const char *s; | |
8358c818 | 1789 | const char *s2; |
670a50eb | 1790 | const char *fmt; |
8358c818 ILT |
1791 | int likely = 0; |
1792 | int dbl = 0; | |
1793 | int coproc = 0; | |
6e8dda9c | 1794 | offsetT maxnum; |
9226253a | 1795 | bfd_reloc_code_real_type r; |
0dd2d296 | 1796 | char *p; |
55933a58 | 1797 | int hold_mips_optimize; |
670a50eb ILT |
1798 | |
1799 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
1800 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
1801 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
1802 | mask = ip->insn_mo->mask; | |
1803 | ||
5ac34ac3 ILT |
1804 | expr1.X_op = O_constant; |
1805 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
1806 | expr1.X_add_symbol = NULL; |
1807 | expr1.X_add_number = 1; | |
1808 | ||
1809 | switch (mask) | |
1810 | { | |
6e8dda9c ILT |
1811 | case M_DABS: |
1812 | dbl = 1; | |
3d3c5039 | 1813 | case M_ABS: |
6e8dda9c ILT |
1814 | /* bgez $a0,.+12 |
1815 | move v0,$a0 | |
1816 | sub v0,$zero,$a0 | |
1817 | */ | |
3d3c5039 | 1818 | |
becfe05e ILT |
1819 | mips_emit_delays (); |
1820 | ++mips_noreorder; | |
0dd2d296 | 1821 | mips_any_noreorder = 1; |
3d3c5039 | 1822 | |
670a50eb | 1823 | expr1.X_add_number = 8; |
0dd2d296 | 1824 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 1825 | if (dreg == sreg) |
0dd2d296 | 1826 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 1827 | else |
0dd2d296 ILT |
1828 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
1829 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
1830 | dbl ? "dsub" : "sub", |
1831 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 1832 | |
becfe05e | 1833 | --mips_noreorder; |
670a50eb | 1834 | return; |
3d3c5039 ILT |
1835 | |
1836 | case M_ADD_I: | |
8358c818 ILT |
1837 | s = "addi"; |
1838 | s2 = "add"; | |
1839 | goto do_addi; | |
3d3c5039 | 1840 | case M_ADDU_I: |
8358c818 ILT |
1841 | s = "addiu"; |
1842 | s2 = "addu"; | |
1843 | goto do_addi; | |
1844 | case M_DADD_I: | |
6e8dda9c | 1845 | dbl = 1; |
8358c818 ILT |
1846 | s = "daddi"; |
1847 | s2 = "dadd"; | |
1848 | goto do_addi; | |
1849 | case M_DADDU_I: | |
6e8dda9c | 1850 | dbl = 1; |
8358c818 ILT |
1851 | s = "daddiu"; |
1852 | s2 = "daddu"; | |
1853 | do_addi: | |
6e8dda9c | 1854 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 1855 | { |
0dd2d296 | 1856 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 1857 | (int) BFD_RELOC_LO16); |
670a50eb | 1858 | return; |
3d3c5039 | 1859 | } |
6e8dda9c | 1860 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 1861 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 1862 | break; |
3d3c5039 ILT |
1863 | |
1864 | case M_AND_I: | |
6e8dda9c ILT |
1865 | s = "andi"; |
1866 | s2 = "and"; | |
1867 | goto do_bit; | |
3d3c5039 | 1868 | case M_OR_I: |
6e8dda9c ILT |
1869 | s = "ori"; |
1870 | s2 = "or"; | |
1871 | goto do_bit; | |
3d3c5039 | 1872 | case M_NOR_I: |
6e8dda9c ILT |
1873 | s = ""; |
1874 | s2 = "nor"; | |
1875 | goto do_bit; | |
3d3c5039 | 1876 | case M_XOR_I: |
6e8dda9c ILT |
1877 | s = "xori"; |
1878 | s2 = "xor"; | |
1879 | do_bit: | |
1880 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 1881 | { |
6e8dda9c | 1882 | if (mask != M_NOR_I) |
0dd2d296 ILT |
1883 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
1884 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 1885 | else |
670a50eb | 1886 | { |
0dd2d296 ILT |
1887 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
1888 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 1889 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 1890 | treg, treg, 0); |
3d3c5039 | 1891 | } |
6e8dda9c | 1892 | return; |
3d3c5039 | 1893 | } |
6e8dda9c ILT |
1894 | |
1895 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 | 1896 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 1897 | break; |
3d3c5039 ILT |
1898 | |
1899 | case M_BEQ_I: | |
8358c818 ILT |
1900 | s = "beq"; |
1901 | goto beq_i; | |
1902 | case M_BEQL_I: | |
1903 | s = "beql"; | |
1904 | likely = 1; | |
1905 | goto beq_i; | |
3d3c5039 | 1906 | case M_BNE_I: |
8358c818 ILT |
1907 | s = "bne"; |
1908 | goto beq_i; | |
1909 | case M_BNEL_I: | |
1910 | s = "bnel"; | |
1911 | likely = 1; | |
1912 | beq_i: | |
670a50eb ILT |
1913 | if (imm_expr.X_add_number == 0) |
1914 | { | |
0dd2d296 ILT |
1915 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
1916 | 0); | |
670a50eb ILT |
1917 | return; |
1918 | } | |
6e8dda9c | 1919 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 1920 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 1921 | break; |
3d3c5039 | 1922 | |
8358c818 ILT |
1923 | case M_BGEL: |
1924 | likely = 1; | |
3d3c5039 | 1925 | case M_BGE: |
670a50eb ILT |
1926 | if (treg == 0) |
1927 | { | |
0dd2d296 | 1928 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1929 | likely ? "bgezl" : "bgez", |
1930 | "s,p", sreg); | |
670a50eb | 1931 | return; |
3d3c5039 | 1932 | } |
9a7d824a ILT |
1933 | if (sreg == 0) |
1934 | { | |
0dd2d296 | 1935 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1936 | likely ? "blezl" : "blez", |
1937 | "s,p", treg); | |
9a7d824a ILT |
1938 | return; |
1939 | } | |
0dd2d296 ILT |
1940 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
1941 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
1942 | likely ? "beql" : "beq", |
1943 | "s,t,p", AT, 0); | |
670a50eb | 1944 | break; |
3d3c5039 | 1945 | |
8358c818 ILT |
1946 | case M_BGTL_I: |
1947 | likely = 1; | |
3d3c5039 | 1948 | case M_BGT_I: |
9a7d824a | 1949 | /* check for > max integer */ |
6e8dda9c ILT |
1950 | maxnum = 0x7fffffff; |
1951 | if (mips_isa >= 3) | |
1952 | { | |
1953 | maxnum <<= 16; | |
1954 | maxnum |= 0xffff; | |
1955 | maxnum <<= 16; | |
1956 | maxnum |= 0xffff; | |
1957 | } | |
1958 | if (imm_expr.X_add_number >= maxnum) | |
9a7d824a ILT |
1959 | { |
1960 | do_false: | |
1961 | /* result is always false */ | |
8358c818 ILT |
1962 | if (! likely) |
1963 | { | |
1964 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 1965 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
1966 | } |
1967 | else | |
1968 | { | |
1969 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
1970 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
1971 | "s,t,p", 0, 0); | |
8358c818 | 1972 | } |
9a7d824a ILT |
1973 | return; |
1974 | } | |
670a50eb ILT |
1975 | imm_expr.X_add_number++; |
1976 | /* FALLTHROUGH */ | |
3d3c5039 | 1977 | case M_BGE_I: |
8358c818 ILT |
1978 | case M_BGEL_I: |
1979 | if (mask == M_BGEL_I) | |
1980 | likely = 1; | |
670a50eb ILT |
1981 | if (imm_expr.X_add_number == 0) |
1982 | { | |
0dd2d296 | 1983 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1984 | likely ? "bgezl" : "bgez", |
1985 | "s,p", sreg); | |
670a50eb | 1986 | return; |
3d3c5039 | 1987 | } |
670a50eb ILT |
1988 | if (imm_expr.X_add_number == 1) |
1989 | { | |
0dd2d296 | 1990 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1991 | likely ? "bgtzl" : "bgtz", |
1992 | "s,p", sreg); | |
670a50eb | 1993 | return; |
3d3c5039 | 1994 | } |
6e8dda9c ILT |
1995 | maxnum = 0x7fffffff; |
1996 | if (mips_isa >= 3) | |
1997 | { | |
1998 | maxnum <<= 16; | |
1999 | maxnum |= 0xffff; | |
2000 | maxnum <<= 16; | |
2001 | maxnum |= 0xffff; | |
2002 | } | |
2003 | maxnum = - maxnum - 1; | |
2004 | if (imm_expr.X_add_number <= maxnum) | |
9a7d824a ILT |
2005 | { |
2006 | do_true: | |
2007 | /* result is always true */ | |
2008 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 2009 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
2010 | return; |
2011 | } | |
6e8dda9c | 2012 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2013 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2014 | likely ? "beql" : "beq", |
2015 | "s,t,p", AT, 0); | |
670a50eb | 2016 | break; |
3d3c5039 | 2017 | |
8358c818 ILT |
2018 | case M_BGEUL: |
2019 | likely = 1; | |
3d3c5039 | 2020 | case M_BGEU: |
670a50eb | 2021 | if (treg == 0) |
9a7d824a ILT |
2022 | goto do_true; |
2023 | if (sreg == 0) | |
670a50eb | 2024 | { |
0dd2d296 | 2025 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2026 | likely ? "beql" : "beq", |
2027 | "s,t,p", 0, treg); | |
670a50eb | 2028 | return; |
3d3c5039 | 2029 | } |
0dd2d296 ILT |
2030 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2031 | treg); | |
2032 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2033 | likely ? "beql" : "beq", |
2034 | "s,t,p", AT, 0); | |
670a50eb | 2035 | break; |
3d3c5039 | 2036 | |
8358c818 ILT |
2037 | case M_BGTUL_I: |
2038 | likely = 1; | |
9a7d824a | 2039 | case M_BGTU_I: |
6e8dda9c | 2040 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2041 | goto do_false; |
2042 | imm_expr.X_add_number++; | |
2043 | /* FALLTHROUGH */ | |
3d3c5039 | 2044 | case M_BGEU_I: |
8358c818 ILT |
2045 | case M_BGEUL_I: |
2046 | if (mask == M_BGEUL_I) | |
2047 | likely = 1; | |
670a50eb | 2048 | if (imm_expr.X_add_number == 0) |
9a7d824a | 2049 | goto do_true; |
670a50eb ILT |
2050 | if (imm_expr.X_add_number == 1) |
2051 | { | |
0dd2d296 | 2052 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2053 | likely ? "bnel" : "bne", |
2054 | "s,t,p", sreg, 0); | |
670a50eb | 2055 | return; |
3d3c5039 | 2056 | } |
6e8dda9c | 2057 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2058 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2059 | likely ? "beql" : "beq", |
2060 | "s,t,p", AT, 0); | |
670a50eb | 2061 | break; |
3d3c5039 | 2062 | |
8358c818 ILT |
2063 | case M_BGTL: |
2064 | likely = 1; | |
3d3c5039 | 2065 | case M_BGT: |
670a50eb ILT |
2066 | if (treg == 0) |
2067 | { | |
0dd2d296 | 2068 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2069 | likely ? "bgtzl" : "bgtz", |
2070 | "s,p", sreg); | |
670a50eb | 2071 | return; |
3d3c5039 | 2072 | } |
9a7d824a ILT |
2073 | if (sreg == 0) |
2074 | { | |
0dd2d296 | 2075 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2076 | likely ? "bltzl" : "bltz", |
2077 | "s,p", treg); | |
9a7d824a ILT |
2078 | return; |
2079 | } | |
0dd2d296 ILT |
2080 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2081 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2082 | likely ? "bnel" : "bne", |
2083 | "s,t,p", AT, 0); | |
670a50eb | 2084 | break; |
3d3c5039 | 2085 | |
8358c818 ILT |
2086 | case M_BGTUL: |
2087 | likely = 1; | |
3d3c5039 | 2088 | case M_BGTU: |
670a50eb ILT |
2089 | if (treg == 0) |
2090 | { | |
0dd2d296 | 2091 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2092 | likely ? "bnel" : "bne", |
2093 | "s,t,p", sreg, 0); | |
670a50eb | 2094 | return; |
3d3c5039 | 2095 | } |
9a7d824a ILT |
2096 | if (sreg == 0) |
2097 | goto do_false; | |
0dd2d296 ILT |
2098 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2099 | sreg); | |
2100 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2101 | likely ? "bnel" : "bne", |
2102 | "s,t,p", AT, 0); | |
670a50eb | 2103 | break; |
3d3c5039 | 2104 | |
8358c818 ILT |
2105 | case M_BLEL: |
2106 | likely = 1; | |
3d3c5039 | 2107 | case M_BLE: |
670a50eb ILT |
2108 | if (treg == 0) |
2109 | { | |
0dd2d296 | 2110 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2111 | likely ? "blezl" : "blez", |
2112 | "s,p", sreg); | |
670a50eb ILT |
2113 | return; |
2114 | } | |
9a7d824a ILT |
2115 | if (sreg == 0) |
2116 | { | |
0dd2d296 | 2117 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2118 | likely ? "bgezl" : "bgez", |
2119 | "s,p", treg); | |
9a7d824a ILT |
2120 | return; |
2121 | } | |
0dd2d296 ILT |
2122 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2123 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2124 | likely ? "beql" : "beq", |
2125 | "s,t,p", AT, 0); | |
670a50eb | 2126 | break; |
3d3c5039 | 2127 | |
8358c818 ILT |
2128 | case M_BLEL_I: |
2129 | likely = 1; | |
3d3c5039 | 2130 | case M_BLE_I: |
6e8dda9c ILT |
2131 | maxnum = 0x7fffffff; |
2132 | if (mips_isa >= 3) | |
2133 | { | |
2134 | maxnum <<= 16; | |
2135 | maxnum |= 0xffff; | |
2136 | maxnum <<= 16; | |
2137 | maxnum |= 0xffff; | |
2138 | } | |
2139 | if (imm_expr.X_add_number >= maxnum) | |
9a7d824a ILT |
2140 | goto do_true; |
2141 | imm_expr.X_add_number++; | |
2142 | /* FALLTHROUGH */ | |
9a7d824a | 2143 | case M_BLT_I: |
8358c818 ILT |
2144 | case M_BLTL_I: |
2145 | if (mask == M_BLTL_I) | |
2146 | likely = 1; | |
670a50eb ILT |
2147 | if (imm_expr.X_add_number == 0) |
2148 | { | |
0dd2d296 | 2149 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2150 | likely ? "bltzl" : "bltz", |
2151 | "s,p", sreg); | |
670a50eb ILT |
2152 | return; |
2153 | } | |
9a7d824a | 2154 | if (imm_expr.X_add_number == 1) |
670a50eb | 2155 | { |
0dd2d296 | 2156 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2157 | likely ? "blezl" : "blez", |
2158 | "s,p", sreg); | |
670a50eb ILT |
2159 | return; |
2160 | } | |
6e8dda9c | 2161 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2162 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2163 | likely ? "bnel" : "bne", |
2164 | "s,t,p", AT, 0); | |
670a50eb | 2165 | break; |
3d3c5039 | 2166 | |
8358c818 ILT |
2167 | case M_BLEUL: |
2168 | likely = 1; | |
3d3c5039 | 2169 | case M_BLEU: |
670a50eb ILT |
2170 | if (treg == 0) |
2171 | { | |
0dd2d296 | 2172 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2173 | likely ? "beql" : "beq", |
2174 | "s,t,p", sreg, 0); | |
670a50eb | 2175 | return; |
3d3c5039 | 2176 | } |
9a7d824a ILT |
2177 | if (sreg == 0) |
2178 | goto do_true; | |
0dd2d296 ILT |
2179 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2180 | sreg); | |
2181 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2182 | likely ? "beql" : "beq", |
2183 | "s,t,p", AT, 0); | |
670a50eb | 2184 | break; |
3d3c5039 | 2185 | |
8358c818 ILT |
2186 | case M_BLEUL_I: |
2187 | likely = 1; | |
3d3c5039 | 2188 | case M_BLEU_I: |
6e8dda9c | 2189 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2190 | goto do_true; |
2191 | imm_expr.X_add_number++; | |
2192 | /* FALLTHROUGH */ | |
9a7d824a | 2193 | case M_BLTU_I: |
8358c818 ILT |
2194 | case M_BLTUL_I: |
2195 | if (mask == M_BLTUL_I) | |
2196 | likely = 1; | |
670a50eb | 2197 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
2198 | goto do_false; |
2199 | if (imm_expr.X_add_number == 1) | |
670a50eb | 2200 | { |
0dd2d296 | 2201 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2202 | likely ? "beql" : "beq", |
2203 | "s,t,p", sreg, 0); | |
670a50eb | 2204 | return; |
3d3c5039 | 2205 | } |
6e8dda9c | 2206 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2207 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2208 | likely ? "bnel" : "bne", |
2209 | "s,t,p", AT, 0); | |
670a50eb | 2210 | break; |
3d3c5039 | 2211 | |
8358c818 ILT |
2212 | case M_BLTL: |
2213 | likely = 1; | |
3d3c5039 | 2214 | case M_BLT: |
670a50eb ILT |
2215 | if (treg == 0) |
2216 | { | |
0dd2d296 | 2217 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2218 | likely ? "bltzl" : "bltz", |
2219 | "s,p", sreg); | |
670a50eb | 2220 | return; |
3d3c5039 | 2221 | } |
9a7d824a | 2222 | if (sreg == 0) |
670a50eb | 2223 | { |
0dd2d296 | 2224 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2225 | likely ? "bgtzl" : "bgtz", |
2226 | "s,p", treg); | |
670a50eb | 2227 | return; |
3d3c5039 | 2228 | } |
0dd2d296 ILT |
2229 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
2230 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2231 | likely ? "bnel" : "bne", |
2232 | "s,t,p", AT, 0); | |
670a50eb | 2233 | break; |
3d3c5039 | 2234 | |
8358c818 ILT |
2235 | case M_BLTUL: |
2236 | likely = 1; | |
3d3c5039 | 2237 | case M_BLTU: |
670a50eb | 2238 | if (treg == 0) |
9a7d824a ILT |
2239 | goto do_false; |
2240 | if (sreg == 0) | |
670a50eb | 2241 | { |
0dd2d296 | 2242 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2243 | likely ? "bnel" : "bne", |
2244 | "s,t,p", 0, treg); | |
670a50eb ILT |
2245 | return; |
2246 | } | |
0dd2d296 ILT |
2247 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2248 | treg); | |
2249 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2250 | likely ? "bnel" : "bne", |
2251 | "s,t,p", AT, 0); | |
670a50eb | 2252 | break; |
3d3c5039 | 2253 | |
8358c818 ILT |
2254 | case M_DDIV_3: |
2255 | dbl = 1; | |
3d3c5039 | 2256 | case M_DIV_3: |
8358c818 ILT |
2257 | s = "mflo"; |
2258 | goto do_div3; | |
2259 | case M_DREM_3: | |
2260 | dbl = 1; | |
3d3c5039 | 2261 | case M_REM_3: |
8358c818 ILT |
2262 | s = "mfhi"; |
2263 | do_div3: | |
670a50eb ILT |
2264 | if (treg == 0) |
2265 | { | |
2266 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2267 | if (mips_trap) |
2268 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2269 | else | |
2270 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2271 | return; |
2272 | } | |
2273 | ||
becfe05e ILT |
2274 | mips_emit_delays (); |
2275 | ++mips_noreorder; | |
0dd2d296 ILT |
2276 | mips_any_noreorder = 1; |
2277 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 2278 | dbl ? "ddiv" : "div", |
ff3a5c18 | 2279 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
2280 | if (mips_trap) |
2281 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2282 | else | |
2283 | { | |
2284 | expr1.X_add_number = 8; | |
2285 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2286 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2287 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2288 | } | |
670a50eb | 2289 | expr1.X_add_number = -1; |
0dd2d296 | 2290 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 2291 | dbl ? "daddiu" : "addiu", |
9226253a | 2292 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 2293 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 2294 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
2295 | if (dbl) |
2296 | { | |
2297 | expr1.X_add_number = 1; | |
0dd2d296 | 2298 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 2299 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
2300 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
2301 | 31); | |
8358c818 ILT |
2302 | } |
2303 | else | |
2304 | { | |
2305 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
2306 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
2307 | (int) BFD_RELOC_HI16); | |
8358c818 | 2308 | } |
8ea7f4e8 ILT |
2309 | if (mips_trap) |
2310 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
2311 | else | |
2312 | { | |
2313 | expr1.X_add_number = 8; | |
2314 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2315 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2316 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
2317 | } | |
becfe05e | 2318 | --mips_noreorder; |
0dd2d296 | 2319 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 2320 | break; |
3d3c5039 ILT |
2321 | |
2322 | case M_DIV_3I: | |
8358c818 ILT |
2323 | s = "div"; |
2324 | s2 = "mflo"; | |
2325 | goto do_divi; | |
3d3c5039 | 2326 | case M_DIVU_3I: |
8358c818 ILT |
2327 | s = "divu"; |
2328 | s2 = "mflo"; | |
2329 | goto do_divi; | |
3d3c5039 | 2330 | case M_REM_3I: |
8358c818 ILT |
2331 | s = "div"; |
2332 | s2 = "mfhi"; | |
2333 | goto do_divi; | |
3d3c5039 | 2334 | case M_REMU_3I: |
8358c818 ILT |
2335 | s = "divu"; |
2336 | s2 = "mfhi"; | |
2337 | goto do_divi; | |
2338 | case M_DDIV_3I: | |
2339 | dbl = 1; | |
2340 | s = "ddiv"; | |
2341 | s2 = "mflo"; | |
2342 | goto do_divi; | |
2343 | case M_DDIVU_3I: | |
2344 | dbl = 1; | |
2345 | s = "ddivu"; | |
2346 | s2 = "mflo"; | |
2347 | goto do_divi; | |
2348 | case M_DREM_3I: | |
2349 | dbl = 1; | |
2350 | s = "ddiv"; | |
2351 | s2 = "mfhi"; | |
2352 | goto do_divi; | |
2353 | case M_DREMU_3I: | |
2354 | dbl = 1; | |
2355 | s = "ddivu"; | |
2356 | s2 = "mfhi"; | |
2357 | do_divi: | |
670a50eb ILT |
2358 | if (imm_expr.X_add_number == 0) |
2359 | { | |
2360 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2361 | if (mips_trap) |
2362 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2363 | else | |
2364 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2365 | return; |
2366 | } | |
2367 | if (imm_expr.X_add_number == 1) | |
2368 | { | |
8358c818 | 2369 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
2370 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
2371 | sreg); | |
3d3c5039 | 2372 | else |
0dd2d296 | 2373 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
2374 | return; |
2375 | } | |
8358c818 ILT |
2376 | if (imm_expr.X_add_number == -1 |
2377 | && s[strlen (s) - 1] != 'u') | |
2378 | { | |
2379 | if (strcmp (s2, "mflo") == 0) | |
2380 | { | |
2381 | if (dbl) | |
0dd2d296 ILT |
2382 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
2383 | sreg); | |
8358c818 | 2384 | else |
0dd2d296 ILT |
2385 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
2386 | sreg); | |
8358c818 ILT |
2387 | } |
2388 | else | |
0dd2d296 | 2389 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
2390 | return; |
2391 | } | |
3d3c5039 | 2392 | |
6e8dda9c | 2393 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
2394 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
2395 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
2396 | break; |
2397 | ||
2398 | case M_DIVU_3: | |
8358c818 ILT |
2399 | s = "divu"; |
2400 | s2 = "mflo"; | |
2401 | goto do_divu3; | |
670a50eb | 2402 | case M_REMU_3: |
8358c818 ILT |
2403 | s = "divu"; |
2404 | s2 = "mfhi"; | |
2405 | goto do_divu3; | |
2406 | case M_DDIVU_3: | |
2407 | s = "ddivu"; | |
2408 | s2 = "mflo"; | |
2409 | goto do_divu3; | |
2410 | case M_DREMU_3: | |
2411 | s = "ddivu"; | |
2412 | s2 = "mfhi"; | |
2413 | do_divu3: | |
becfe05e ILT |
2414 | mips_emit_delays (); |
2415 | ++mips_noreorder; | |
0dd2d296 ILT |
2416 | mips_any_noreorder = 1; |
2417 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
2418 | if (mips_trap) |
2419 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2420 | else | |
2421 | { | |
2422 | expr1.X_add_number = 8; | |
2423 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2424 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2425 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2426 | } | |
becfe05e | 2427 | --mips_noreorder; |
0dd2d296 | 2428 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 2429 | return; |
3d3c5039 | 2430 | |
0dd2d296 | 2431 | case M_LA_AB: |
d9aba805 ILT |
2432 | /* Load the address of a symbol into a register. If breg is not |
2433 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
2434 | |
2435 | /* When generating embedded PIC code, we permit expressions of | |
2436 | the form | |
2437 | la $4,foo-bar | |
2438 | where bar is an address in the .text section. These are used | |
2439 | when getting the addresses of functions. We don't permit | |
2440 | X_add_number to be non-zero, because if the symbol is | |
2441 | external the relaxing code needs to know that any addend is | |
2442 | purely the offset to X_op_symbol. */ | |
2443 | if (mips_pic == EMBEDDED_PIC | |
2444 | && offset_expr.X_op == O_subtract | |
2445 | && now_seg == text_section | |
2446 | && S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
2447 | && breg == 0 | |
2448 | && offset_expr.X_add_number == 0) | |
2449 | { | |
2450 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
2451 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
2452 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2453 | mips_isa < 3 ? "addiu" : "daddiu", | |
2454 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
2455 | return; | |
2456 | } | |
2457 | ||
0dd2d296 ILT |
2458 | if (offset_expr.X_op != O_symbol |
2459 | && offset_expr.X_op != O_constant) | |
670a50eb | 2460 | { |
0dd2d296 ILT |
2461 | as_bad ("expression too complex"); |
2462 | offset_expr.X_op = O_constant; | |
2463 | } | |
2464 | ||
2465 | if (treg == breg) | |
2466 | { | |
2467 | tempreg = AT; | |
2468 | used_at = 1; | |
3d3c5039 | 2469 | } |
670a50eb ILT |
2470 | else |
2471 | { | |
0dd2d296 ILT |
2472 | tempreg = treg; |
2473 | used_at = 0; | |
670a50eb | 2474 | } |
3d3c5039 | 2475 | |
5ac34ac3 | 2476 | if (offset_expr.X_op == O_constant) |
6e8dda9c | 2477 | load_register (&icnt, tempreg, &offset_expr); |
d9aba805 | 2478 | else if (mips_pic == NO_PIC) |
670a50eb | 2479 | { |
0dd2d296 ILT |
2480 | /* If this is a reference to an GP relative symbol, we want |
2481 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2482 | Otherwise we want | |
2483 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
2484 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2485 | If we have a constant, we need two instructions anyhow, | |
2486 | so we may as well always use the latter form. */ | |
2487 | if (offset_expr.X_add_number != 0) | |
2488 | p = NULL; | |
2489 | else | |
2490 | { | |
8ea7f4e8 | 2491 | frag_grow (20); |
0dd2d296 ILT |
2492 | macro_build ((char *) NULL, &icnt, &offset_expr, |
2493 | mips_isa < 3 ? "addiu" : "daddiu", | |
2494 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2495 | p = frag_var (rs_machine_dependent, 8, 0, | |
2496 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
2497 | mips_warn_about_macros), | |
2498 | offset_expr.X_add_symbol, (long) 0, | |
2499 | (char *) NULL); | |
2500 | } | |
2501 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2502 | if (p != NULL) | |
2503 | p += 4; | |
2504 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 2505 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
2506 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
2507 | } | |
d9aba805 | 2508 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
2509 | { |
2510 | /* If this is a reference to an external symbol, and there | |
2511 | is no constant, we want | |
2512 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2513 | For a local symbol, we want | |
2514 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2515 | nop | |
2516 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2517 | ||
2518 | If we have a small constant, and this is a reference to | |
2519 | an external symbol, we want | |
2520 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2521 | nop | |
2522 | addiu $tempreg,$tempreg,<constant> | |
2523 | For a local symbol, we want the same instruction | |
2524 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
2525 | addiu instruction. | |
2526 | ||
2527 | If we have a large constant, and this is a reference to | |
2528 | an external symbol, we want | |
2529 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2530 | lui $at,<hiconstant> | |
2531 | addiu $at,$at,<loconstant> | |
2532 | addu $tempreg,$tempreg,$at | |
2533 | For a local symbol, we want the same instruction | |
2534 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
2535 | addiu instruction. */ | |
2536 | expr1.X_add_number = offset_expr.X_add_number; | |
2537 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 2538 | frag_grow (32); |
0dd2d296 ILT |
2539 | macro_build ((char *) NULL, &icnt, &offset_expr, |
2540 | mips_isa < 3 ? "lw" : "ld", | |
2541 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2542 | if (expr1.X_add_number == 0) | |
2543 | { | |
2544 | int off; | |
2545 | ||
2546 | if (breg == 0) | |
2547 | off = 0; | |
2548 | else | |
2549 | { | |
2550 | /* We're going to put in an addu instruction using | |
2551 | tempreg, so we may as well insert the nop right | |
2552 | now. */ | |
2553 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2554 | "nop", ""); | |
2555 | off = 4; | |
2556 | } | |
2557 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
2558 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
2559 | (breg == 0 | |
2560 | ? mips_warn_about_macros | |
2561 | : 0)), | |
2562 | offset_expr.X_add_symbol, (long) 0, | |
2563 | (char *) NULL); | |
2564 | if (breg == 0) | |
2565 | { | |
2566 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
2567 | p += 4; | |
2568 | } | |
2569 | macro_build (p, &icnt, &expr1, | |
2570 | mips_isa < 3 ? "addiu" : "daddiu", | |
2571 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
2572 | /* FIXME: If breg == 0, and the next instruction uses | |
2573 | $tempreg, then if this variant case is used an extra | |
2574 | nop will be generated. */ | |
2575 | } | |
2576 | else if (expr1.X_add_number >= -0x8000 | |
2577 | && expr1.X_add_number < 0x8000) | |
2578 | { | |
2579 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2580 | "nop", ""); | |
2581 | macro_build ((char *) NULL, &icnt, &expr1, | |
2582 | mips_isa < 3 ? "addiu" : "daddiu", | |
2583 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
2584 | (void) frag_var (rs_machine_dependent, 0, 0, | |
2585 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
2586 | offset_expr.X_add_symbol, (long) 0, | |
2587 | (char *) NULL); | |
2588 | } | |
2589 | else | |
2590 | { | |
2591 | int off1; | |
2592 | ||
2593 | /* If we are going to add in a base register, and the | |
2594 | target register and the base register are the same, | |
2595 | then we are using AT as a temporary register. Since | |
2596 | we want to load the constant into AT, we add our | |
2597 | current AT (from the global offset table) and the | |
2598 | register into the register now, and pretend we were | |
2599 | not using a base register. */ | |
2600 | if (breg != treg) | |
2601 | off1 = 0; | |
2602 | else | |
2603 | { | |
2604 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2605 | "nop", ""); | |
2606 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2607 | mips_isa < 3 ? "addu" : "daddu", | |
2608 | "d,v,t", treg, AT, breg); | |
2609 | breg = 0; | |
2610 | tempreg = treg; | |
2611 | off1 = -8; | |
2612 | } | |
2613 | ||
55933a58 ILT |
2614 | /* Set mips_optimize around the lui instruction to avoid |
2615 | inserting an unnecessary nop after the lw. */ | |
2616 | hold_mips_optimize = mips_optimize; | |
2617 | mips_optimize = 2; | |
0dd2d296 | 2618 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
2619 | mips_optimize = hold_mips_optimize; |
2620 | ||
0dd2d296 ILT |
2621 | macro_build ((char *) NULL, &icnt, &expr1, |
2622 | mips_isa < 3 ? "addiu" : "daddiu", | |
2623 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
2624 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2625 | mips_isa < 3 ? "addu" : "daddu", | |
2626 | "d,v,t", tempreg, tempreg, AT); | |
2627 | (void) frag_var (rs_machine_dependent, 0, 0, | |
2628 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
2629 | offset_expr.X_add_symbol, (long) 0, | |
2630 | (char *) NULL); | |
2631 | used_at = 1; | |
2632 | } | |
670a50eb | 2633 | } |
d9aba805 ILT |
2634 | else if (mips_pic == EMBEDDED_PIC) |
2635 | { | |
2636 | /* We use | |
2637 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2638 | */ | |
2639 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2640 | mips_isa < 3 ? "addiu" : "daddiu", | |
2641 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2642 | } | |
2643 | else | |
2644 | abort (); | |
0dd2d296 | 2645 | |
670a50eb | 2646 | if (breg != 0) |
0dd2d296 ILT |
2647 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
2648 | mips_isa < 3 ? "addu" : "daddu", | |
2649 | "d,v,t", treg, tempreg, breg); | |
2650 | ||
2651 | if (! used_at) | |
2652 | return; | |
2653 | ||
2654 | break; | |
2655 | ||
2656 | case M_J_A: | |
2657 | /* The j instruction may not be used in PIC code, since it | |
2658 | requires an absolute address. We convert it to a b | |
2659 | instruction. */ | |
d9aba805 | 2660 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
2661 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
2662 | else | |
2663 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 2664 | return; |
3d3c5039 | 2665 | |
9226253a ILT |
2666 | /* The jal instructions must be handled as macros because when |
2667 | generating PIC code they expand to multi-instruction | |
2668 | sequences. Normally they are simple instructions. */ | |
2669 | case M_JAL_1: | |
2670 | dreg = RA; | |
2671 | /* Fall through. */ | |
2672 | case M_JAL_2: | |
d9aba805 ILT |
2673 | if (mips_pic == NO_PIC |
2674 | || mips_pic == EMBEDDED_PIC) | |
2675 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
2676 | "d,s", dreg, sreg); | |
2677 | else if (mips_pic == SVR4_PIC) | |
9226253a | 2678 | { |
d9aba805 ILT |
2679 | if (sreg != PIC_CALL_REG) |
2680 | as_warn ("MIPS PIC call to register other than $25"); | |
2681 | ||
0dd2d296 ILT |
2682 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
2683 | "d,s", dreg, sreg); | |
d9aba805 ILT |
2684 | if (mips_cprestore_offset < 0) |
2685 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
2686 | else | |
2687 | { | |
2688 | expr1.X_add_number = mips_cprestore_offset; | |
2689 | macro_build ((char *) NULL, &icnt, &expr1, | |
2690 | mips_isa < 3 ? "lw" : "ld", | |
2691 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
2692 | } | |
9226253a | 2693 | } |
0dd2d296 | 2694 | else |
d9aba805 ILT |
2695 | abort (); |
2696 | ||
9226253a ILT |
2697 | return; |
2698 | ||
2699 | case M_JAL_A: | |
d9aba805 ILT |
2700 | if (mips_pic == NO_PIC) |
2701 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
2702 | else if (mips_pic == SVR4_PIC) | |
9226253a | 2703 | { |
d9aba805 ILT |
2704 | /* If this is a reference to an external symbol, we want |
2705 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
2706 | nop | |
2707 | jalr $25 | |
2708 | nop | |
2709 | lw $gp,cprestore($sp) | |
2710 | The cprestore value is set using the .cprestore | |
2711 | pseudo-op. If the symbol is not external, we want | |
2712 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2713 | nop | |
2714 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
2715 | jalr $25 | |
2716 | nop | |
2717 | lw $gp,cprestore($sp) | |
2718 | */ | |
2719 | frag_grow (20); | |
2720 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
0dd2d296 | 2721 | mips_isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
2722 | "t,o(b)", PIC_CALL_REG, |
2723 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
2724 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
2725 | p = frag_var (rs_machine_dependent, 4, 0, | |
2726 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
2727 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
2728 | macro_build (p, &icnt, &offset_expr, | |
2729 | mips_isa < 3 ? "addiu" : "daddiu", | |
2730 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
2731 | (int) BFD_RELOC_LO16); | |
2732 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2733 | "jalr", "s", PIC_CALL_REG); | |
2734 | if (mips_cprestore_offset < 0) | |
2735 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
2736 | else | |
2737 | { | |
2738 | if (mips_noreorder) | |
2739 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2740 | "nop", ""); | |
2741 | expr1.X_add_number = mips_cprestore_offset; | |
2742 | macro_build ((char *) NULL, &icnt, &expr1, | |
2743 | mips_isa < 3 ? "lw" : "ld", | |
2744 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
2745 | mips_frame_reg); | |
2746 | } | |
0dd2d296 | 2747 | } |
d9aba805 | 2748 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
2749 | { |
2750 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
2751 | /* The linker may expand the call to a longer sequence which | |
2752 | uses $at, so we must break rather than return. */ | |
2753 | break; | |
2754 | } | |
d9aba805 ILT |
2755 | else |
2756 | abort (); | |
2757 | ||
9226253a ILT |
2758 | return; |
2759 | ||
3d3c5039 | 2760 | case M_LB_AB: |
670a50eb ILT |
2761 | s = "lb"; |
2762 | goto ld; | |
3d3c5039 | 2763 | case M_LBU_AB: |
670a50eb ILT |
2764 | s = "lbu"; |
2765 | goto ld; | |
3d3c5039 | 2766 | case M_LH_AB: |
670a50eb ILT |
2767 | s = "lh"; |
2768 | goto ld; | |
3d3c5039 | 2769 | case M_LHU_AB: |
670a50eb ILT |
2770 | s = "lhu"; |
2771 | goto ld; | |
3d3c5039 | 2772 | case M_LW_AB: |
670a50eb ILT |
2773 | s = "lw"; |
2774 | goto ld; | |
3d3c5039 | 2775 | case M_LWC0_AB: |
670a50eb | 2776 | s = "lwc0"; |
8358c818 | 2777 | coproc = 1; |
670a50eb | 2778 | goto ld; |
3d3c5039 | 2779 | case M_LWC1_AB: |
670a50eb | 2780 | s = "lwc1"; |
8358c818 | 2781 | coproc = 1; |
670a50eb | 2782 | goto ld; |
3d3c5039 | 2783 | case M_LWC2_AB: |
670a50eb | 2784 | s = "lwc2"; |
8358c818 | 2785 | coproc = 1; |
670a50eb | 2786 | goto ld; |
3d3c5039 | 2787 | case M_LWC3_AB: |
670a50eb | 2788 | s = "lwc3"; |
8358c818 | 2789 | coproc = 1; |
670a50eb | 2790 | goto ld; |
3d3c5039 | 2791 | case M_LWL_AB: |
670a50eb ILT |
2792 | s = "lwl"; |
2793 | goto ld; | |
3d3c5039 | 2794 | case M_LWR_AB: |
670a50eb | 2795 | s = "lwr"; |
8358c818 ILT |
2796 | goto ld; |
2797 | case M_LDC1_AB: | |
2798 | s = "ldc1"; | |
2799 | coproc = 1; | |
2800 | goto ld; | |
2801 | case M_LDC2_AB: | |
2802 | s = "ldc2"; | |
2803 | coproc = 1; | |
2804 | goto ld; | |
2805 | case M_LDC3_AB: | |
2806 | s = "ldc3"; | |
2807 | coproc = 1; | |
2808 | goto ld; | |
2809 | case M_LDL_AB: | |
2810 | s = "ldl"; | |
2811 | goto ld; | |
2812 | case M_LDR_AB: | |
2813 | s = "ldr"; | |
2814 | goto ld; | |
2815 | case M_LL_AB: | |
2816 | s = "ll"; | |
2817 | goto ld; | |
2818 | case M_LLD_AB: | |
2819 | s = "lld"; | |
2820 | goto ld; | |
2821 | case M_LWU_AB: | |
2822 | s = "lwu"; | |
3d3c5039 | 2823 | ld: |
8358c818 | 2824 | if (breg == treg || coproc) |
670a50eb ILT |
2825 | { |
2826 | tempreg = AT; | |
2827 | used_at = 1; | |
2828 | } | |
2829 | else | |
2830 | { | |
2831 | tempreg = treg; | |
2832 | used_at = 0; | |
2833 | } | |
2834 | goto ld_st; | |
3d3c5039 | 2835 | case M_SB_AB: |
670a50eb ILT |
2836 | s = "sb"; |
2837 | goto st; | |
3d3c5039 | 2838 | case M_SH_AB: |
670a50eb ILT |
2839 | s = "sh"; |
2840 | goto st; | |
3d3c5039 | 2841 | case M_SW_AB: |
670a50eb ILT |
2842 | s = "sw"; |
2843 | goto st; | |
3d3c5039 | 2844 | case M_SWC0_AB: |
670a50eb | 2845 | s = "swc0"; |
8358c818 | 2846 | coproc = 1; |
670a50eb | 2847 | goto st; |
3d3c5039 | 2848 | case M_SWC1_AB: |
670a50eb | 2849 | s = "swc1"; |
8358c818 | 2850 | coproc = 1; |
670a50eb | 2851 | goto st; |
3d3c5039 | 2852 | case M_SWC2_AB: |
670a50eb | 2853 | s = "swc2"; |
8358c818 | 2854 | coproc = 1; |
670a50eb | 2855 | goto st; |
3d3c5039 | 2856 | case M_SWC3_AB: |
670a50eb | 2857 | s = "swc3"; |
8358c818 | 2858 | coproc = 1; |
670a50eb | 2859 | goto st; |
3d3c5039 | 2860 | case M_SWL_AB: |
670a50eb ILT |
2861 | s = "swl"; |
2862 | goto st; | |
3d3c5039 | 2863 | case M_SWR_AB: |
670a50eb | 2864 | s = "swr"; |
8358c818 ILT |
2865 | goto st; |
2866 | case M_SC_AB: | |
2867 | s = "sc"; | |
2868 | goto st; | |
2869 | case M_SCD_AB: | |
2870 | s = "scd"; | |
2871 | goto st; | |
2872 | case M_SDC1_AB: | |
2873 | s = "sdc1"; | |
2874 | coproc = 1; | |
2875 | goto st; | |
2876 | case M_SDC2_AB: | |
2877 | s = "sdc2"; | |
2878 | coproc = 1; | |
2879 | goto st; | |
2880 | case M_SDC3_AB: | |
2881 | s = "sdc3"; | |
2882 | coproc = 1; | |
2883 | goto st; | |
2884 | case M_SDL_AB: | |
2885 | s = "sdl"; | |
2886 | goto st; | |
2887 | case M_SDR_AB: | |
2888 | s = "sdr"; | |
3d3c5039 | 2889 | st: |
670a50eb ILT |
2890 | tempreg = AT; |
2891 | used_at = 1; | |
3d3c5039 | 2892 | ld_st: |
8358c818 ILT |
2893 | if (mask == M_LWC1_AB |
2894 | || mask == M_SWC1_AB | |
8358c818 | 2895 | || mask == M_LDC1_AB |
0dd2d296 ILT |
2896 | || mask == M_SDC1_AB |
2897 | || mask == M_L_DAB | |
2898 | || mask == M_S_DAB) | |
670a50eb | 2899 | fmt = "T,o(b)"; |
8358c818 | 2900 | else if (coproc) |
19ed8960 | 2901 | fmt = "E,o(b)"; |
670a50eb ILT |
2902 | else |
2903 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
2904 | |
2905 | if (offset_expr.X_op != O_constant | |
2906 | && offset_expr.X_op != O_symbol) | |
2907 | { | |
2908 | as_bad ("expression too complex"); | |
2909 | offset_expr.X_op = O_constant; | |
2910 | } | |
2911 | ||
2912 | /* A constant expression in PIC code can be handled just as it | |
2913 | is in non PIC code. */ | |
d9aba805 | 2914 | if (mips_pic == NO_PIC |
0dd2d296 | 2915 | || offset_expr.X_op == O_constant) |
670a50eb | 2916 | { |
0dd2d296 ILT |
2917 | /* If this is a reference to a GP relative symbol, and there |
2918 | is no base register, we want | |
2919 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 2920 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
2921 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
2922 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
2923 | If we have a constant, we need two instructions anyhow, | |
2924 | so we always use the latter form. | |
2925 | ||
2926 | If we have a base register, and this is a reference to a | |
2927 | GP relative symbol, we want | |
2928 | addu $tempreg,$breg,$gp | |
2929 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
2930 | Otherwise we want | |
2931 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
2932 | addu $tempreg,$tempreg,$breg | |
2933 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
2934 | With a constant we always use the latter case. */ | |
670a50eb ILT |
2935 | if (breg == 0) |
2936 | { | |
0dd2d296 ILT |
2937 | if (offset_expr.X_add_number != 0) |
2938 | p = NULL; | |
2939 | else | |
2940 | { | |
8ea7f4e8 | 2941 | frag_grow (20); |
0dd2d296 ILT |
2942 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
2943 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
2944 | p = frag_var (rs_machine_dependent, 8, 0, | |
2945 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
2946 | (mips_warn_about_macros |
2947 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
2948 | offset_expr.X_add_symbol, (long) 0, |
2949 | (char *) NULL); | |
8197b589 | 2950 | used_at = 0; |
0dd2d296 ILT |
2951 | } |
2952 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2953 | if (p != NULL) | |
2954 | p += 4; | |
2955 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
2956 | (int) BFD_RELOC_LO16, tempreg); | |
2957 | } | |
2958 | else | |
2959 | { | |
2960 | if (offset_expr.X_add_number != 0) | |
2961 | p = NULL; | |
2962 | else | |
2963 | { | |
8ea7f4e8 | 2964 | frag_grow (28); |
0dd2d296 ILT |
2965 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
2966 | mips_isa < 3 ? "addu" : "daddu", | |
2967 | "d,v,t", tempreg, breg, GP); | |
2968 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
2969 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
2970 | p = frag_var (rs_machine_dependent, 12, 0, | |
2971 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
2972 | offset_expr.X_add_symbol, (long) 0, | |
2973 | (char *) NULL); | |
2974 | } | |
2975 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2976 | if (p != NULL) | |
2977 | p += 4; | |
2978 | macro_build (p, &icnt, (expressionS *) NULL, | |
2979 | mips_isa < 3 ? "addu" : "daddu", | |
2980 | "d,v,t", tempreg, tempreg, breg); | |
2981 | if (p != NULL) | |
2982 | p += 4; | |
2983 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
2984 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 2985 | } |
670a50eb | 2986 | } |
d9aba805 | 2987 | else if (mips_pic == SVR4_PIC) |
670a50eb | 2988 | { |
0dd2d296 ILT |
2989 | /* If this is a reference to an external symbol, we want |
2990 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2991 | nop | |
2992 | <op> $treg,0($tempreg) | |
2993 | Otherwise we want | |
2994 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2995 | nop | |
2996 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2997 | <op> $treg,0($tempreg) | |
2998 | If there is a base register, we add it to $tempreg before | |
2999 | the <op>. If there is a constant, we stick it in the | |
3000 | <op> instruction. We don't handle constants larger than | |
3001 | 16 bits, because we have no way to load the upper 16 bits | |
3002 | (actually, we could handle them for the subset of cases | |
3003 | in which we are not using $at). */ | |
3004 | assert (offset_expr.X_op == O_symbol); | |
3005 | expr1.X_add_number = offset_expr.X_add_number; | |
3006 | offset_expr.X_add_number = 0; | |
3007 | if (expr1.X_add_number < -0x8000 | |
3008 | || expr1.X_add_number >= 0x8000) | |
3009 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 3010 | frag_grow (20); |
0dd2d296 ILT |
3011 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3012 | mips_isa < 3 ? "lw" : "ld", | |
3013 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3014 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
3015 | p = frag_var (rs_machine_dependent, 4, 0, | |
3016 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
3017 | offset_expr.X_add_symbol, (long) 0, | |
3018 | (char *) NULL); | |
3019 | macro_build (p, &icnt, &offset_expr, | |
3020 | mips_isa < 3 ? "addiu" : "daddiu", | |
3021 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3022 | if (breg != 0) |
0dd2d296 | 3023 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
3024 | mips_isa < 3 ? "addu" : "daddu", |
3025 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
3026 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
3027 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 3028 | } |
d9aba805 ILT |
3029 | else if (mips_pic == EMBEDDED_PIC) |
3030 | { | |
3031 | /* If there is no base register, we want | |
3032 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3033 | If there is a base register, we want | |
3034 | addu $tempreg,$breg,$gp | |
3035 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
3036 | */ | |
3037 | assert (offset_expr.X_op == O_symbol); | |
3038 | if (breg == 0) | |
3039 | { | |
3040 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3041 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
3042 | used_at = 0; | |
3043 | } | |
3044 | else | |
3045 | { | |
3046 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3047 | mips_isa < 3 ? "addu" : "daddu", | |
3048 | "d,v,t", tempreg, breg, GP); | |
3049 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3050 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3051 | } | |
3052 | } | |
3053 | else | |
3054 | abort (); | |
0dd2d296 ILT |
3055 | |
3056 | if (! used_at) | |
3057 | return; | |
3058 | ||
3059 | break; | |
3d3c5039 ILT |
3060 | |
3061 | case M_LI: | |
19ed8960 | 3062 | case M_LI_S: |
6e8dda9c | 3063 | load_register (&icnt, treg, &imm_expr); |
670a50eb | 3064 | return; |
3d3c5039 | 3065 | |
0dd2d296 | 3066 | case M_LI_SS: |
55933a58 | 3067 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 3068 | { |
d2c71068 ILT |
3069 | load_register (&icnt, AT, &imm_expr); |
3070 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3071 | "mtc1", "t,G", AT, treg); | |
3072 | break; | |
0dd2d296 | 3073 | } |
d9aba805 | 3074 | else |
d2c71068 | 3075 | { |
55933a58 ILT |
3076 | assert (offset_expr.X_op == O_symbol |
3077 | && strcmp (segment_name (S_GET_SEGMENT | |
3078 | (offset_expr.X_add_symbol)), | |
3079 | ".lit4") == 0 | |
3080 | && offset_expr.X_add_number == 0); | |
3081 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
3082 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
3083 | return; |
3084 | } | |
0dd2d296 | 3085 | |
3d3c5039 | 3086 | case M_LI_D: |
d9aba805 ILT |
3087 | /* We know that sym is in the .rdata section. First we get the |
3088 | upper 16 bits of the address. */ | |
3089 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3090 | { |
3091 | /* FIXME: This won't work for a 64 bit address. */ | |
3092 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
3093 | } | |
d9aba805 | 3094 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
3095 | { |
3096 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3097 | mips_isa < 3 ? "lw" : "ld", | |
3098 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3099 | } | |
d9aba805 ILT |
3100 | else if (mips_pic == EMBEDDED_PIC) |
3101 | { | |
3102 | /* For embedded PIC we pick up the entire address off $gp in | |
3103 | a single instruction. */ | |
3104 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3105 | mips_isa < 3 ? "addiu" : "daddiu", | |
3106 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3107 | offset_expr.X_op = O_constant; | |
3108 | offset_expr.X_add_number = 0; | |
3109 | } | |
3110 | else | |
3111 | abort (); | |
3112 | ||
0dd2d296 | 3113 | /* Now we load the register(s). */ |
8358c818 | 3114 | if (mips_isa >= 3) |
0dd2d296 ILT |
3115 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
3116 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
3117 | else |
3118 | { | |
0dd2d296 ILT |
3119 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
3120 | treg, (int) BFD_RELOC_LO16, AT); | |
3121 | if (treg != 31) | |
3122 | { | |
3123 | /* FIXME: How in the world do we deal with the possible | |
3124 | overflow here? */ | |
3125 | offset_expr.X_add_number += 4; | |
3126 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
3127 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
3128 | } | |
8358c818 | 3129 | } |
d2c71068 ILT |
3130 | |
3131 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
3132 | does not become a variant frag. */ | |
3133 | frag_wane (frag_now); | |
3134 | frag_new (0); | |
3135 | ||
670a50eb | 3136 | break; |
3d3c5039 ILT |
3137 | |
3138 | case M_LI_DD: | |
55933a58 ILT |
3139 | assert (offset_expr.X_op == O_symbol |
3140 | && offset_expr.X_add_number == 0); | |
3141 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
3142 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 3143 | { |
0dd2d296 ILT |
3144 | if (mips_isa >= 2) |
3145 | { | |
3146 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
3147 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
3148 | return; | |
3149 | } | |
3150 | breg = GP; | |
3151 | r = BFD_RELOC_MIPS_LITERAL; | |
3152 | goto dob; | |
3153 | } | |
55933a58 | 3154 | else |
0dd2d296 | 3155 | { |
55933a58 ILT |
3156 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
3157 | if (mips_pic == SVR4_PIC) | |
3158 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3159 | mips_isa < 3 ? "lw" : "ld", | |
3160 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3161 | else | |
3162 | { | |
3163 | /* FIXME: This won't work for a 64 bit address. */ | |
3164 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
3165 | } | |
3166 | ||
0dd2d296 ILT |
3167 | if (mips_isa >= 2) |
3168 | { | |
3169 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 3170 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
3171 | break; |
3172 | } | |
3173 | breg = AT; | |
3174 | r = BFD_RELOC_LO16; | |
3175 | goto dob; | |
8358c818 | 3176 | } |
9226253a | 3177 | |
3d3c5039 | 3178 | case M_L_DOB: |
9a7d824a ILT |
3179 | /* Even on a big endian machine $fn comes before $fn+1. We have |
3180 | to adjust when loading from memory. */ | |
9226253a ILT |
3181 | r = BFD_RELOC_LO16; |
3182 | dob: | |
8358c818 | 3183 | assert (mips_isa < 2); |
0dd2d296 | 3184 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 3185 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 3186 | (int) r, breg); |
0dd2d296 ILT |
3187 | /* FIXME: A possible overflow which I don't know how to deal |
3188 | with. */ | |
670a50eb | 3189 | offset_expr.X_add_number += 4; |
0dd2d296 | 3190 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 3191 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 3192 | (int) r, breg); |
d2c71068 ILT |
3193 | |
3194 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
3195 | does not become a variant frag. */ | |
3196 | frag_wane (frag_now); | |
3197 | frag_new (0); | |
3198 | ||
0dd2d296 ILT |
3199 | if (breg != AT) |
3200 | return; | |
3201 | break; | |
3d3c5039 ILT |
3202 | |
3203 | case M_L_DAB: | |
670a50eb ILT |
3204 | /* |
3205 | * The MIPS assembler seems to check for X_add_number not | |
3206 | * being double aligned and generating: | |
3207 | * lui at,%hi(foo+1) | |
3208 | * addu at,at,v1 | |
3209 | * addiu at,at,%lo(foo+1) | |
3210 | * lwc1 f2,0(at) | |
3211 | * lwc1 f3,4(at) | |
3212 | * But, the resulting address is the same after relocation so why | |
3213 | * generate the extra instruction? | |
3214 | */ | |
4032d3f0 | 3215 | coproc = 1; |
0dd2d296 | 3216 | if (mips_isa >= 2) |
670a50eb | 3217 | { |
0dd2d296 ILT |
3218 | s = "ldc1"; |
3219 | goto ld; | |
670a50eb | 3220 | } |
0dd2d296 ILT |
3221 | |
3222 | s = "lwc1"; | |
3223 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
3224 | goto ldd_std; |
3225 | ||
3226 | case M_S_DAB: | |
8358c818 | 3227 | if (mips_isa >= 2) |
8358c818 | 3228 | { |
0dd2d296 ILT |
3229 | s = "sdc1"; |
3230 | goto st; | |
8358c818 | 3231 | } |
3d3c5039 | 3232 | |
0dd2d296 ILT |
3233 | s = "swc1"; |
3234 | fmt = "T,o(b)"; | |
3235 | coproc = 1; | |
3236 | goto ldd_std; | |
3d3c5039 ILT |
3237 | |
3238 | case M_LD_AB: | |
0dd2d296 | 3239 | if (mips_isa >= 3) |
670a50eb | 3240 | { |
0dd2d296 ILT |
3241 | s = "ld"; |
3242 | goto ld; | |
670a50eb | 3243 | } |
0dd2d296 ILT |
3244 | |
3245 | s = "lw"; | |
3246 | fmt = "t,o(b)"; | |
3247 | goto ldd_std; | |
3248 | ||
3249 | case M_SD_AB: | |
3250 | if (mips_isa >= 3) | |
670a50eb | 3251 | { |
0dd2d296 ILT |
3252 | s = "sd"; |
3253 | goto st; | |
670a50eb | 3254 | } |
0dd2d296 | 3255 | |
670a50eb | 3256 | s = "sw"; |
0dd2d296 ILT |
3257 | fmt = "t,o(b)"; |
3258 | ||
3259 | ldd_std: | |
3260 | if (offset_expr.X_op != O_symbol | |
3261 | && offset_expr.X_op != O_constant) | |
670a50eb | 3262 | { |
0dd2d296 ILT |
3263 | as_bad ("expression too complex"); |
3264 | offset_expr.X_op = O_constant; | |
3265 | } | |
3266 | ||
3267 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
3268 | to adjust when loading from memory. We set coproc if we must | |
3269 | load $fn+1 first. */ | |
3270 | if (byte_order == LITTLE_ENDIAN) | |
3271 | coproc = 0; | |
3272 | ||
d9aba805 | 3273 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
3274 | || offset_expr.X_op == O_constant) |
3275 | { | |
3276 | /* If this is a reference to a GP relative symbol, we want | |
3277 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3278 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
3279 | If we have a base register, we use this | |
3280 | addu $at,$breg,$gp | |
3281 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
3282 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
3283 | If this is not a GP relative symbol, we want | |
3284 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3285 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
3286 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
3287 | If there is a base register, we add it to $at after the | |
3288 | lui instruction. If there is a constant, we always use | |
3289 | the last case. */ | |
3290 | if (offset_expr.X_add_number != 0) | |
670a50eb | 3291 | { |
0dd2d296 ILT |
3292 | p = NULL; |
3293 | used_at = 1; | |
670a50eb ILT |
3294 | } |
3295 | else | |
0dd2d296 ILT |
3296 | { |
3297 | int off; | |
3298 | ||
3299 | if (breg == 0) | |
3300 | { | |
8ea7f4e8 | 3301 | frag_grow (28); |
0dd2d296 ILT |
3302 | tempreg = GP; |
3303 | off = 0; | |
3304 | used_at = 0; | |
3305 | } | |
3306 | else | |
3307 | { | |
8ea7f4e8 | 3308 | frag_grow (36); |
0dd2d296 ILT |
3309 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3310 | mips_isa < 3 ? "addu" : "daddu", | |
3311 | "d,v,t", AT, breg, GP); | |
3312 | tempreg = AT; | |
3313 | off = 4; | |
3314 | used_at = 1; | |
3315 | } | |
3316 | ||
3317 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3318 | coproc ? treg + 1 : treg, | |
3319 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3320 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
3321 | |
3322 | /* Set mips_optimize to 2 to avoid inserting an | |
3323 | undesired nop. */ | |
3324 | hold_mips_optimize = mips_optimize; | |
3325 | mips_optimize = 2; | |
0dd2d296 ILT |
3326 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
3327 | coproc ? treg : treg + 1, | |
3328 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
3329 | mips_optimize = hold_mips_optimize; |
3330 | ||
0dd2d296 ILT |
3331 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
3332 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 3333 | used_at && mips_noat), |
0dd2d296 ILT |
3334 | offset_expr.X_add_symbol, (long) 0, |
3335 | (char *) NULL); | |
777ad64d ILT |
3336 | |
3337 | /* We just generated two relocs. When tc_gen_reloc | |
3338 | handles this case, it will skip the first reloc and | |
3339 | handle the second. The second reloc already has an | |
3340 | extra addend of 4, which we added above. We must | |
3341 | subtract it out, and then subtract another 4 to make | |
3342 | the first reloc come out right. The second reloc | |
3343 | will come out right because we are going to add 4 to | |
3344 | offset_expr when we build its instruction below. */ | |
3345 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
3346 | offset_expr.X_op = O_constant; |
3347 | } | |
3348 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
3349 | if (p != NULL) | |
3350 | p += 4; | |
3351 | if (breg != 0) | |
3352 | { | |
3353 | macro_build (p, &icnt, (expressionS *) NULL, | |
3354 | mips_isa < 3 ? "addu" : "daddu", | |
3355 | "d,v,t", AT, breg, AT); | |
3356 | if (p != NULL) | |
3357 | p += 4; | |
3358 | } | |
3359 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
3360 | coproc ? treg + 1 : treg, | |
3361 | (int) BFD_RELOC_LO16, AT); | |
3362 | if (p != NULL) | |
3363 | p += 4; | |
3364 | /* FIXME: How do we handle overflow here? */ | |
3365 | offset_expr.X_add_number += 4; | |
3366 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
3367 | coproc ? treg : treg + 1, | |
3368 | (int) BFD_RELOC_LO16, AT); | |
3369 | } | |
d9aba805 | 3370 | else if (mips_pic == SVR4_PIC) |
670a50eb | 3371 | { |
0dd2d296 ILT |
3372 | int off; |
3373 | ||
3374 | /* If this is a reference to an external symbol, we want | |
3375 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3376 | nop | |
3377 | <op> $treg,0($at) | |
3378 | <op> $treg+1,4($at) | |
3379 | Otherwise we want | |
3380 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3381 | nop | |
3382 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
3383 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
3384 | If there is a base register we add it to $at before the | |
3385 | lwc1 instructions. If there is a constant we include it | |
3386 | in the lwc1 instructions. */ | |
3387 | used_at = 1; | |
3388 | expr1.X_add_number = offset_expr.X_add_number; | |
3389 | offset_expr.X_add_number = 0; | |
3390 | if (expr1.X_add_number < -0x8000 | |
3391 | || expr1.X_add_number >= 0x8000 - 4) | |
3392 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3393 | if (breg == 0) | |
3394 | off = 0; | |
3395 | else | |
3396 | off = 4; | |
8ea7f4e8 | 3397 | frag_grow (24 + off); |
0dd2d296 ILT |
3398 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3399 | mips_isa < 3 ? "lw" : "ld", | |
3400 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3401 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 3402 | if (breg != 0) |
0dd2d296 | 3403 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 3404 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
3405 | "d,v,t", AT, breg, AT); |
3406 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
3407 | coproc ? treg + 1 : treg, | |
3408 | (int) BFD_RELOC_LO16, AT); | |
3409 | expr1.X_add_number += 4; | |
55933a58 ILT |
3410 | |
3411 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
3412 | nop. */ | |
3413 | hold_mips_optimize = mips_optimize; | |
3414 | mips_optimize = 2; | |
0dd2d296 ILT |
3415 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
3416 | coproc ? treg : treg + 1, | |
3417 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
3418 | mips_optimize = hold_mips_optimize; |
3419 | ||
0dd2d296 ILT |
3420 | (void) frag_var (rs_machine_dependent, 0, 0, |
3421 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
3422 | offset_expr.X_add_symbol, (long) 0, | |
3423 | (char *) NULL); | |
8358c818 | 3424 | } |
d9aba805 ILT |
3425 | else if (mips_pic == EMBEDDED_PIC) |
3426 | { | |
3427 | /* If there is no base register, we use | |
3428 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3429 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
3430 | If we have a base register, we use | |
3431 | addu $at,$breg,$gp | |
3432 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
3433 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
3434 | */ | |
3435 | if (breg == 0) | |
3436 | { | |
3437 | tempreg = GP; | |
3438 | used_at = 0; | |
3439 | } | |
3440 | else | |
3441 | { | |
3442 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3443 | mips_isa < 3 ? "addu" : "daddu", | |
3444 | "d,v,t", AT, breg, GP); | |
3445 | tempreg = AT; | |
3446 | used_at = 1; | |
3447 | } | |
3448 | ||
3449 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3450 | coproc ? treg + 1 : treg, | |
3451 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3452 | offset_expr.X_add_number += 4; | |
3453 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3454 | coproc ? treg : treg + 1, | |
3455 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3456 | } | |
3457 | else | |
3458 | abort (); | |
0dd2d296 ILT |
3459 | |
3460 | if (! used_at) | |
3461 | return; | |
3462 | ||
3463 | break; | |
3464 | ||
3465 | case M_LD_OB: | |
3466 | s = "lw"; | |
3467 | goto sd_ob; | |
3468 | case M_SD_OB: | |
3469 | s = "sw"; | |
3470 | sd_ob: | |
3471 | assert (mips_isa < 3); | |
3472 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
3473 | (int) BFD_RELOC_LO16, breg); | |
3474 | offset_expr.X_add_number += 4; | |
3475 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
3476 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 3477 | return; |
917fae09 SS |
3478 | #ifdef LOSING_COMPILER |
3479 | default: | |
3480 | macro2 (ip); | |
3481 | return; | |
3482 | } | |
3483 | if (mips_noat) | |
3484 | as_warn ("Macro used $at after \".set noat\""); | |
3485 | } | |
3486 | ||
3487 | static void | |
3488 | macro2 (ip) | |
3489 | struct mips_cl_insn *ip; | |
3490 | { | |
3491 | register int treg, sreg, dreg, breg; | |
3492 | int tempreg; | |
3493 | int mask; | |
3494 | int icnt = 0; | |
3495 | int used_at; | |
3496 | expressionS expr1; | |
3497 | const char *s; | |
3498 | const char *s2; | |
3499 | const char *fmt; | |
3500 | int likely = 0; | |
3501 | int dbl = 0; | |
3502 | int coproc = 0; | |
3503 | offsetT maxnum; | |
3504 | bfd_reloc_code_real_type r; | |
3505 | char *p; | |
3506 | ||
3507 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3508 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3509 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3510 | mask = ip->insn_mo->mask; | |
3511 | ||
3512 | expr1.X_op = O_constant; | |
3513 | expr1.X_op_symbol = NULL; | |
3514 | expr1.X_add_symbol = NULL; | |
3515 | expr1.X_add_number = 1; | |
3516 | ||
3517 | switch (mask) | |
3518 | { | |
3519 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 3520 | |
8358c818 ILT |
3521 | case M_DMUL: |
3522 | dbl = 1; | |
3d3c5039 | 3523 | case M_MUL: |
0dd2d296 | 3524 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3525 | dbl ? "dmultu" : "multu", |
3526 | "s,t", sreg, treg); | |
0dd2d296 | 3527 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 3528 | return; |
3d3c5039 | 3529 | |
8358c818 ILT |
3530 | case M_DMUL_I: |
3531 | dbl = 1; | |
3d3c5039 | 3532 | case M_MUL_I: |
8358c818 ILT |
3533 | /* The MIPS assembler some times generates shifts and adds. I'm |
3534 | not trying to be that fancy. GCC should do this for us | |
3535 | anyway. */ | |
6e8dda9c | 3536 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3537 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3538 | dbl ? "dmult" : "mult", |
3539 | "s,t", sreg, AT); | |
0dd2d296 | 3540 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 3541 | break; |
3d3c5039 | 3542 | |
8358c818 ILT |
3543 | case M_DMULO: |
3544 | dbl = 1; | |
3545 | case M_MULO: | |
3546 | mips_emit_delays (); | |
3547 | ++mips_noreorder; | |
0dd2d296 ILT |
3548 | mips_any_noreorder = 1; |
3549 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3550 | dbl ? "dmult" : "mult", |
3551 | "s,t", sreg, treg); | |
0dd2d296 ILT |
3552 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
3553 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3554 | dbl ? "dsra32" : "sra", |
3555 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 3556 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
3557 | if (mips_trap) |
3558 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
3559 | else | |
3560 | { | |
3561 | expr1.X_add_number = 8; | |
3562 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
3563 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3564 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3565 | } | |
8358c818 | 3566 | --mips_noreorder; |
0dd2d296 | 3567 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
3568 | break; |
3569 | ||
3570 | case M_DMULOU: | |
3571 | dbl = 1; | |
3572 | case M_MULOU: | |
3573 | mips_emit_delays (); | |
3574 | ++mips_noreorder; | |
0dd2d296 ILT |
3575 | mips_any_noreorder = 1; |
3576 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3577 | dbl ? "dmultu" : "multu", |
3578 | "s,t", sreg, treg); | |
0dd2d296 ILT |
3579 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
3580 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
3581 | if (mips_trap) |
3582 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
3583 | else | |
3584 | { | |
3585 | expr1.X_add_number = 8; | |
3586 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
3587 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3588 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3589 | } | |
8358c818 ILT |
3590 | --mips_noreorder; |
3591 | break; | |
3592 | ||
3d3c5039 | 3593 | case M_ROL: |
0dd2d296 ILT |
3594 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
3595 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
3596 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
3597 | treg); | |
3598 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 3599 | break; |
3d3c5039 ILT |
3600 | |
3601 | case M_ROL_I: | |
0dd2d296 | 3602 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
670a50eb | 3603 | imm_expr.X_add_number & 0x1f); |
0dd2d296 | 3604 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
670a50eb | 3605 | (0 - imm_expr.X_add_number) & 0x1f); |
0dd2d296 | 3606 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 3607 | break; |
3d3c5039 ILT |
3608 | |
3609 | case M_ROR: | |
0dd2d296 ILT |
3610 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
3611 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
3612 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
3613 | treg); | |
3614 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 3615 | break; |
3d3c5039 ILT |
3616 | |
3617 | case M_ROR_I: | |
0dd2d296 | 3618 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
670a50eb | 3619 | imm_expr.X_add_number & 0x1f); |
0dd2d296 | 3620 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
670a50eb | 3621 | (0 - imm_expr.X_add_number) & 0x1f); |
0dd2d296 | 3622 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 3623 | break; |
3d3c5039 ILT |
3624 | |
3625 | case M_S_DOB: | |
8358c818 | 3626 | assert (mips_isa < 2); |
9a7d824a ILT |
3627 | /* Even on a big endian machine $fn comes before $fn+1. We have |
3628 | to adjust when storing to memory. */ | |
0dd2d296 | 3629 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 3630 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 3631 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3632 | offset_expr.X_add_number += 4; |
0dd2d296 | 3633 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 3634 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 3635 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3636 | return; |
3d3c5039 | 3637 | |
3d3c5039 | 3638 | case M_SEQ: |
670a50eb | 3639 | if (sreg == 0) |
0dd2d296 ILT |
3640 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3641 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 3642 | else if (treg == 0) |
0dd2d296 ILT |
3643 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3644 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
3645 | else |
3646 | { | |
0dd2d296 ILT |
3647 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3648 | sreg, treg); | |
3649 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
3650 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 3651 | } |
670a50eb | 3652 | return; |
3d3c5039 ILT |
3653 | |
3654 | case M_SEQ_I: | |
670a50eb ILT |
3655 | if (imm_expr.X_add_number == 0) |
3656 | { | |
0dd2d296 ILT |
3657 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3658 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3659 | return; |
3d3c5039 | 3660 | } |
670a50eb ILT |
3661 | if (sreg == 0) |
3662 | { | |
9a7d824a | 3663 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 3664 | ip->insn_mo->name); |
0dd2d296 | 3665 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 3666 | return; |
3d3c5039 | 3667 | } |
6e8dda9c | 3668 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 3669 | { |
0dd2d296 ILT |
3670 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
3671 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3672 | used_at = 0; |
6e8dda9c ILT |
3673 | } |
3674 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
3675 | { | |
3676 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3677 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 3678 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
3679 | "t,r,j", dreg, sreg, |
3680 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
3681 | used_at = 0; |
3682 | } | |
3683 | else | |
3684 | { | |
3685 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 ILT |
3686 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3687 | sreg, AT); | |
670a50eb ILT |
3688 | used_at = 1; |
3689 | } | |
0dd2d296 | 3690 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 3691 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
3692 | if (used_at) |
3693 | break; | |
3694 | return; | |
3d3c5039 ILT |
3695 | |
3696 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
3697 | s = "slt"; |
3698 | goto sge; | |
3d3c5039 | 3699 | case M_SGEU: |
670a50eb | 3700 | s = "sltu"; |
3d3c5039 | 3701 | sge: |
0dd2d296 ILT |
3702 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
3703 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3704 | (int) BFD_RELOC_LO16); |
670a50eb | 3705 | return; |
3d3c5039 | 3706 | |
670a50eb | 3707 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 3708 | case M_SGEU_I: |
6e8dda9c | 3709 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3710 | { |
0dd2d296 | 3711 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 3712 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 3713 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
3714 | used_at = 0; |
3715 | } | |
3716 | else | |
3717 | { | |
6e8dda9c | 3718 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3719 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
3720 | mask == M_SGE_I ? "slt" : "sltu", |
3721 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
3722 | used_at = 1; |
3723 | } | |
0dd2d296 | 3724 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 3725 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
3726 | if (used_at) |
3727 | break; | |
3728 | return; | |
3d3c5039 ILT |
3729 | |
3730 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
3731 | s = "slt"; |
3732 | goto sgt; | |
3d3c5039 | 3733 | case M_SGTU: |
670a50eb | 3734 | s = "sltu"; |
3d3c5039 | 3735 | sgt: |
0dd2d296 | 3736 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 3737 | return; |
3d3c5039 | 3738 | |
670a50eb ILT |
3739 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
3740 | s = "slt"; | |
3741 | goto sgti; | |
3d3c5039 | 3742 | case M_SGTU_I: |
670a50eb | 3743 | s = "sltu"; |
3d3c5039 | 3744 | sgti: |
6e8dda9c | 3745 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3746 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 3747 | break; |
3d3c5039 | 3748 | |
670a50eb ILT |
3749 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
3750 | s = "slt"; | |
3751 | goto sle; | |
3d3c5039 | 3752 | case M_SLEU: |
670a50eb | 3753 | s = "sltu"; |
3d3c5039 | 3754 | sle: |
0dd2d296 ILT |
3755 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
3756 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3757 | (int) BFD_RELOC_LO16); |
670a50eb | 3758 | return; |
3d3c5039 | 3759 | |
670a50eb ILT |
3760 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
3761 | s = "slt"; | |
3762 | goto slei; | |
3d3c5039 | 3763 | case M_SLEU_I: |
670a50eb | 3764 | s = "sltu"; |
3d3c5039 | 3765 | slei: |
6e8dda9c | 3766 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
3767 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
3768 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3769 | (int) BFD_RELOC_LO16); |
670a50eb | 3770 | break; |
3d3c5039 ILT |
3771 | |
3772 | case M_SLT_I: | |
6e8dda9c | 3773 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3774 | { |
0dd2d296 ILT |
3775 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
3776 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3777 | return; |
3d3c5039 | 3778 | } |
6e8dda9c | 3779 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3780 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 3781 | break; |
3d3c5039 ILT |
3782 | |
3783 | case M_SLTU_I: | |
6e8dda9c | 3784 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3785 | { |
0dd2d296 ILT |
3786 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
3787 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3788 | return; |
3d3c5039 | 3789 | } |
6e8dda9c | 3790 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
3791 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
3792 | AT); | |
670a50eb | 3793 | break; |
3d3c5039 ILT |
3794 | |
3795 | case M_SNE: | |
670a50eb | 3796 | if (sreg == 0) |
0dd2d296 ILT |
3797 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3798 | treg); | |
670a50eb | 3799 | else if (treg == 0) |
0dd2d296 ILT |
3800 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3801 | sreg); | |
670a50eb ILT |
3802 | else |
3803 | { | |
0dd2d296 ILT |
3804 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3805 | sreg, treg); | |
3806 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
3807 | dreg); | |
3d3c5039 | 3808 | } |
670a50eb | 3809 | return; |
3d3c5039 ILT |
3810 | |
3811 | case M_SNE_I: | |
670a50eb ILT |
3812 | if (imm_expr.X_add_number == 0) |
3813 | { | |
0dd2d296 ILT |
3814 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3815 | sreg); | |
670a50eb | 3816 | return; |
3d3c5039 | 3817 | } |
670a50eb ILT |
3818 | if (sreg == 0) |
3819 | { | |
9a7d824a | 3820 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 3821 | ip->insn_mo->name); |
0dd2d296 | 3822 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 3823 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 3824 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 3825 | return; |
3d3c5039 | 3826 | } |
6e8dda9c | 3827 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 3828 | { |
0dd2d296 ILT |
3829 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
3830 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3831 | used_at = 0; |
6e8dda9c ILT |
3832 | } |
3833 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
3834 | { | |
3835 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3836 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 3837 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 3838 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
3839 | used_at = 0; |
3840 | } | |
3841 | else | |
3842 | { | |
3843 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 ILT |
3844 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3845 | sreg, AT); | |
670a50eb ILT |
3846 | used_at = 1; |
3847 | } | |
0dd2d296 | 3848 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
3849 | if (used_at) |
3850 | break; | |
3851 | return; | |
3d3c5039 | 3852 | |
8358c818 ILT |
3853 | case M_DSUB_I: |
3854 | dbl = 1; | |
3d3c5039 | 3855 | case M_SUB_I: |
6e8dda9c | 3856 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
3857 | { |
3858 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3859 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 3860 | dbl ? "daddi" : "addi", |
9226253a | 3861 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 3862 | return; |
3d3c5039 | 3863 | } |
6e8dda9c | 3864 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3865 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3866 | dbl ? "dsub" : "sub", |
3867 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 3868 | break; |
3d3c5039 | 3869 | |
8358c818 ILT |
3870 | case M_DSUBU_I: |
3871 | dbl = 1; | |
3d3c5039 | 3872 | case M_SUBU_I: |
6e8dda9c | 3873 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
3874 | { |
3875 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3876 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 3877 | dbl ? "daddiu" : "addiu", |
9226253a | 3878 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 3879 | return; |
3d3c5039 | 3880 | } |
6e8dda9c | 3881 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3882 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3883 | dbl ? "dsubu" : "subu", |
3884 | "d,v,t", dreg, sreg, AT); | |
3885 | break; | |
3886 | ||
3887 | case M_TEQ_I: | |
3888 | s = "teq"; | |
3889 | goto trap; | |
3890 | case M_TGE_I: | |
3891 | s = "tge"; | |
3892 | goto trap; | |
3893 | case M_TGEU_I: | |
3894 | s = "tgeu"; | |
3895 | goto trap; | |
3896 | case M_TLT_I: | |
3897 | s = "tlt"; | |
3898 | goto trap; | |
3899 | case M_TLTU_I: | |
3900 | s = "tltu"; | |
3901 | goto trap; | |
3902 | case M_TNE_I: | |
3903 | s = "tne"; | |
3904 | trap: | |
6e8dda9c | 3905 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3906 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 3907 | break; |
3d3c5039 ILT |
3908 | |
3909 | case M_TRUNCWD: | |
3910 | case M_TRUNCWS: | |
8358c818 | 3911 | assert (mips_isa < 2); |
670a50eb ILT |
3912 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
3913 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
3914 | ||
3915 | /* | |
3916 | * Is the double cfc1 instruction a bug in the mips assembler; | |
3917 | * or is there a reason for it? | |
3918 | */ | |
becfe05e ILT |
3919 | mips_emit_delays (); |
3920 | ++mips_noreorder; | |
0dd2d296 ILT |
3921 | mips_any_noreorder = 1; |
3922 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
3923 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
3924 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 3925 | expr1.X_add_number = 3; |
0dd2d296 | 3926 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 3927 | (int) BFD_RELOC_LO16); |
670a50eb | 3928 | expr1.X_add_number = 2; |
0dd2d296 | 3929 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 3930 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3931 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
3932 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3933 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 3934 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
3935 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
3936 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 3937 | --mips_noreorder; |
670a50eb | 3938 | break; |
3d3c5039 ILT |
3939 | |
3940 | case M_ULH: | |
670a50eb ILT |
3941 | s = "lb"; |
3942 | goto ulh; | |
3d3c5039 | 3943 | case M_ULHU: |
670a50eb | 3944 | s = "lbu"; |
3d3c5039 | 3945 | ulh: |
8ea7f4e8 ILT |
3946 | if (offset_expr.X_add_number >= 0x7fff) |
3947 | as_bad ("operand overflow"); | |
670a50eb | 3948 | /* avoid load delay */ |
8ea7f4e8 ILT |
3949 | if (byte_order == LITTLE_ENDIAN) |
3950 | offset_expr.X_add_number += 1; | |
0dd2d296 | 3951 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 3952 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
3953 | if (byte_order == LITTLE_ENDIAN) |
3954 | offset_expr.X_add_number -= 1; | |
3955 | else | |
3956 | offset_expr.X_add_number += 1; | |
0dd2d296 | 3957 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 3958 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
3959 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
3960 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 3961 | break; |
3d3c5039 ILT |
3962 | |
3963 | case M_ULW: | |
8ea7f4e8 ILT |
3964 | if (offset_expr.X_add_number >= 0x7ffd) |
3965 | as_bad ("operand overflow"); | |
3966 | if (byte_order == LITTLE_ENDIAN) | |
3967 | offset_expr.X_add_number += 3; | |
0dd2d296 | 3968 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwl", "t,o(b)", treg, |
9226253a | 3969 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
3970 | if (byte_order == LITTLE_ENDIAN) |
3971 | offset_expr.X_add_number -= 3; | |
3972 | else | |
3973 | offset_expr.X_add_number += 3; | |
0dd2d296 | 3974 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwr", "t,o(b)", treg, |
9226253a | 3975 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3976 | return; |
3d3c5039 ILT |
3977 | |
3978 | case M_ULH_A: | |
3979 | case M_ULHU_A: | |
3980 | case M_ULW_A: | |
0dd2d296 | 3981 | load_address (&icnt, AT, &offset_expr); |
670a50eb ILT |
3982 | if (mask == M_ULW_A) |
3983 | { | |
8ea7f4e8 ILT |
3984 | if (byte_order == LITTLE_ENDIAN) |
3985 | expr1.X_add_number = 3; | |
3986 | else | |
3987 | expr1.X_add_number = 0; | |
0dd2d296 | 3988 | macro_build ((char *) NULL, &icnt, &expr1, "lwl", "t,o(b)", treg, |
9226253a | 3989 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
3990 | if (byte_order == LITTLE_ENDIAN) |
3991 | expr1.X_add_number = 0; | |
3992 | else | |
3993 | expr1.X_add_number = 3; | |
0dd2d296 | 3994 | macro_build ((char *) NULL, &icnt, &expr1, "lwr", "t,o(b)", treg, |
9226253a | 3995 | (int) BFD_RELOC_LO16, AT); |
670a50eb ILT |
3996 | } |
3997 | else | |
3998 | { | |
8ea7f4e8 ILT |
3999 | if (byte_order == BIG_ENDIAN) |
4000 | expr1.X_add_number = 0; | |
0dd2d296 | 4001 | macro_build ((char *) NULL, &icnt, &expr1, |
9226253a ILT |
4002 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, |
4003 | (int) BFD_RELOC_LO16, AT); | |
8ea7f4e8 ILT |
4004 | if (byte_order == BIG_ENDIAN) |
4005 | expr1.X_add_number = 1; | |
4006 | else | |
4007 | expr1.X_add_number = 0; | |
0dd2d296 | 4008 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
9226253a | 4009 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
4010 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, |
4011 | treg, 8); | |
4012 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
4013 | treg, AT); | |
670a50eb ILT |
4014 | } |
4015 | break; | |
3d3c5039 ILT |
4016 | |
4017 | case M_USH: | |
8ea7f4e8 ILT |
4018 | if (offset_expr.X_add_number >= 0x7fff) |
4019 | as_bad ("operand overflow"); | |
4020 | if (byte_order == BIG_ENDIAN) | |
4021 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4022 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 4023 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 4024 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
8ea7f4e8 ILT |
4025 | if (byte_order == BIG_ENDIAN) |
4026 | offset_expr.X_add_number -= 1; | |
4027 | else | |
4028 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4029 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 4030 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4031 | break; |
3d3c5039 ILT |
4032 | |
4033 | case M_USW: | |
8ea7f4e8 ILT |
4034 | if (offset_expr.X_add_number >= 0x7ffd) |
4035 | as_bad ("operand overflow"); | |
4036 | if (byte_order == LITTLE_ENDIAN) | |
4037 | offset_expr.X_add_number += 3; | |
0dd2d296 | 4038 | macro_build ((char *) NULL, &icnt, &offset_expr, "swl", "t,o(b)", treg, |
9226253a | 4039 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
4040 | if (byte_order == LITTLE_ENDIAN) |
4041 | offset_expr.X_add_number -= 3; | |
4042 | else | |
4043 | offset_expr.X_add_number += 3; | |
0dd2d296 | 4044 | macro_build ((char *) NULL, &icnt, &offset_expr, "swr", "t,o(b)", treg, |
9226253a | 4045 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4046 | return; |
3d3c5039 ILT |
4047 | |
4048 | case M_USH_A: | |
4049 | case M_USW_A: | |
0dd2d296 | 4050 | load_address (&icnt, AT, &offset_expr); |
670a50eb ILT |
4051 | if (mask == M_USW_A) |
4052 | { | |
8ea7f4e8 ILT |
4053 | if (byte_order == LITTLE_ENDIAN) |
4054 | expr1.X_add_number = 3; | |
4055 | else | |
4056 | expr1.X_add_number = 0; | |
0dd2d296 | 4057 | macro_build ((char *) NULL, &icnt, &expr1, "swl", "t,o(b)", treg, |
9226253a | 4058 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
4059 | if (byte_order == LITTLE_ENDIAN) |
4060 | expr1.X_add_number = 0; | |
4061 | else | |
4062 | expr1.X_add_number = 3; | |
0dd2d296 | 4063 | macro_build ((char *) NULL, &icnt, &expr1, "swr", "t,o(b)", treg, |
9226253a | 4064 | (int) BFD_RELOC_LO16, AT); |
670a50eb ILT |
4065 | } |
4066 | else | |
4067 | { | |
8ea7f4e8 ILT |
4068 | if (byte_order == LITTLE_ENDIAN) |
4069 | expr1.X_add_number = 0; | |
0dd2d296 | 4070 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
9226253a | 4071 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
4072 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, |
4073 | treg, 8); | |
8ea7f4e8 ILT |
4074 | if (byte_order == LITTLE_ENDIAN) |
4075 | expr1.X_add_number = 1; | |
4076 | else | |
4077 | expr1.X_add_number = 0; | |
0dd2d296 | 4078 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
9226253a | 4079 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
4080 | if (byte_order == LITTLE_ENDIAN) |
4081 | expr1.X_add_number = 0; | |
4082 | else | |
4083 | expr1.X_add_number = 1; | |
0dd2d296 | 4084 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
9226253a | 4085 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
4086 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, |
4087 | treg, 8); | |
4088 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
4089 | treg, AT); | |
670a50eb ILT |
4090 | } |
4091 | break; | |
3d3c5039 ILT |
4092 | |
4093 | default: | |
670a50eb | 4094 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 4095 | break; |
3d3c5039 | 4096 | } |
670a50eb ILT |
4097 | if (mips_noat) |
4098 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
4099 | } |
4100 | ||
4101 | ||
4102 | /* | |
4103 | This routine assembles an instruction into its binary format. As a side | |
4104 | effect it sets one of the global variables imm_reloc or offset_reloc to the | |
4105 | type of relocation to do if one of the operands is an address expression. | |
4106 | */ | |
4107 | static void | |
4108 | mips_ip (str, ip) | |
4109 | char *str; | |
4110 | struct mips_cl_insn *ip; | |
4111 | { | |
670a50eb ILT |
4112 | char *s; |
4113 | const char *args; | |
4114 | char c; | |
4115 | struct mips_opcode *insn; | |
4116 | char *argsStart; | |
4117 | unsigned int regno; | |
4118 | unsigned int lastregno = 0; | |
4119 | char *s_reset; | |
4120 | ||
4121 | insn_error = NULL; | |
4122 | ||
4123 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '.'; ++s) | |
4124 | continue; | |
4125 | switch (*s) | |
4126 | { | |
3d3c5039 | 4127 | case '\0': |
670a50eb | 4128 | break; |
3d3c5039 ILT |
4129 | |
4130 | case ' ': | |
670a50eb ILT |
4131 | *s++ = '\0'; |
4132 | break; | |
3d3c5039 ILT |
4133 | |
4134 | default: | |
460531da | 4135 | as_fatal ("Unknown opcode: `%s'", str); |
3d3c5039 | 4136 | } |
670a50eb ILT |
4137 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
4138 | { | |
4139 | as_warn ("`%s' not in hash table.", str); | |
4140 | insn_error = "ERROR: Unrecognized opcode"; | |
4141 | return; | |
3d3c5039 | 4142 | } |
670a50eb ILT |
4143 | argsStart = s; |
4144 | for (;;) | |
4145 | { | |
8358c818 ILT |
4146 | int insn_isa; |
4147 | ||
670a50eb | 4148 | assert (strcmp (insn->name, str) == 0); |
8358c818 ILT |
4149 | |
4150 | if (insn->pinfo == INSN_MACRO) | |
4151 | insn_isa = insn->match; | |
4152 | else if (insn->pinfo & INSN_ISA2) | |
4153 | insn_isa = 2; | |
4154 | else if (insn->pinfo & INSN_ISA3) | |
4155 | insn_isa = 3; | |
4156 | else | |
4157 | insn_isa = 1; | |
4158 | ||
4159 | if (insn_isa > mips_isa) | |
4160 | { | |
4161 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
4162 | && strcmp (insn->name, insn[1].name) == 0) | |
4163 | { | |
4164 | ++insn; | |
4165 | continue; | |
4166 | } | |
8bbad6fd | 4167 | as_warn ("Instruction not supported on this processor"); |
8358c818 ILT |
4168 | } |
4169 | ||
670a50eb ILT |
4170 | ip->insn_mo = insn; |
4171 | ip->insn_opcode = insn->match; | |
4172 | for (args = insn->args;; ++args) | |
4173 | { | |
4174 | if (*s == ' ') | |
4175 | ++s; | |
4176 | switch (*args) | |
4177 | { | |
4178 | case '\0': /* end of args */ | |
4179 | if (*s == '\0') | |
4180 | return; | |
4181 | break; | |
3d3c5039 ILT |
4182 | |
4183 | case ',': | |
670a50eb ILT |
4184 | if (*s++ == *args) |
4185 | continue; | |
4186 | s--; | |
4187 | switch (*++args) | |
4188 | { | |
3d3c5039 ILT |
4189 | case 'r': |
4190 | case 'v': | |
670a50eb ILT |
4191 | ip->insn_opcode |= lastregno << 21; |
4192 | continue; | |
3d3c5039 ILT |
4193 | |
4194 | case 'w': | |
4195 | case 'W': | |
670a50eb ILT |
4196 | ip->insn_opcode |= lastregno << 16; |
4197 | continue; | |
3d3c5039 ILT |
4198 | |
4199 | case 'V': | |
670a50eb ILT |
4200 | ip->insn_opcode |= lastregno << 11; |
4201 | continue; | |
3d3c5039 | 4202 | } |
670a50eb | 4203 | break; |
3d3c5039 ILT |
4204 | |
4205 | case '(': | |
670a50eb ILT |
4206 | /* handle optional base register. |
4207 | Either the base register is omitted or | |
4208 | we must have a left paren. */ | |
4209 | /* this is dependent on the next operand specifier | |
4210 | is a 'b' for base register */ | |
4211 | assert (args[1] == 'b'); | |
4212 | if (*s == '\0') | |
4213 | return; | |
3d3c5039 | 4214 | |
670a50eb ILT |
4215 | case ')': /* these must match exactly */ |
4216 | if (*s++ == *args) | |
3d3c5039 | 4217 | continue; |
670a50eb ILT |
4218 | break; |
4219 | ||
4220 | case '<': /* must be at least one digit */ | |
4221 | /* | |
4222 | * According to the manual, if the shift amount is greater | |
4223 | * than 31 or less than 0 the the shift amount should be | |
4224 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 4225 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
4226 | */ |
4227 | my_getExpression (&imm_expr, s); | |
4228 | check_absolute_expr (ip, &imm_expr); | |
4229 | if ((unsigned long) imm_expr.X_add_number > 31) | |
4230 | { | |
58d4951d ILT |
4231 | as_warn ("Improper shift amount (%ld)", |
4232 | (long) imm_expr.X_add_number); | |
9226253a | 4233 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
4234 | } |
4235 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 4236 | imm_expr.X_op = O_absent; |
670a50eb ILT |
4237 | s = expr_end; |
4238 | continue; | |
4239 | ||
56c96faa ILT |
4240 | case '>': /* shift amount minus 32 */ |
4241 | my_getExpression (&imm_expr, s); | |
4242 | check_absolute_expr (ip, &imm_expr); | |
4243 | if ((unsigned long) imm_expr.X_add_number < 32 | |
4244 | || (unsigned long) imm_expr.X_add_number > 63) | |
4245 | break; | |
4246 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
4247 | imm_expr.X_op = O_absent; | |
4248 | s = expr_end; | |
4249 | continue; | |
4250 | ||
9226253a ILT |
4251 | case 'k': /* cache code */ |
4252 | my_getExpression (&imm_expr, s); | |
4253 | check_absolute_expr (ip, &imm_expr); | |
4254 | if ((unsigned long) imm_expr.X_add_number > 31) | |
4255 | { | |
4256 | as_warn ("Invalid cahce opcode (%lu)", | |
4257 | (unsigned long) imm_expr.X_add_number); | |
4258 | imm_expr.X_add_number &= 0x1f; | |
4259 | } | |
4260 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
4261 | imm_expr.X_op = O_absent; | |
4262 | s = expr_end; | |
4263 | continue; | |
4264 | ||
670a50eb ILT |
4265 | case 'c': /* break code */ |
4266 | my_getExpression (&imm_expr, s); | |
4267 | check_absolute_expr (ip, &imm_expr); | |
4268 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
4269 | as_warn ("Illegal break code (%ld)", |
4270 | (long) imm_expr.X_add_number); | |
670a50eb | 4271 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 4272 | imm_expr.X_op = O_absent; |
670a50eb ILT |
4273 | s = expr_end; |
4274 | continue; | |
4275 | ||
918692a5 ILT |
4276 | case 'B': /* syscall code */ |
4277 | my_getExpression (&imm_expr, s); | |
4278 | check_absolute_expr (ip, &imm_expr); | |
4279 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
4280 | as_warn ("Illegal syscall code (%ld)", |
4281 | (long) imm_expr.X_add_number); | |
918692a5 | 4282 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 4283 | imm_expr.X_op = O_absent; |
918692a5 ILT |
4284 | s = expr_end; |
4285 | continue; | |
4286 | ||
0aa07269 ILT |
4287 | case 'C': /* Coprocessor code */ |
4288 | my_getExpression (&imm_expr, s); | |
4289 | check_absolute_expr (ip, &imm_expr); | |
4290 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
4291 | { | |
58d4951d ILT |
4292 | as_warn ("Coproccesor code > 25 bits (%ld)", |
4293 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
4294 | imm_expr.X_add_number &= ((1<<25) - 1); |
4295 | } | |
4296 | ip->insn_opcode |= imm_expr.X_add_number; | |
4297 | imm_expr.X_op = O_absent; | |
4298 | s = expr_end; | |
4299 | continue; | |
4300 | ||
670a50eb ILT |
4301 | case 'b': /* base register */ |
4302 | case 'd': /* destination register */ | |
4303 | case 's': /* source register */ | |
4304 | case 't': /* target register */ | |
4305 | case 'r': /* both target and source */ | |
4306 | case 'v': /* both dest and source */ | |
4307 | case 'w': /* both dest and target */ | |
918692a5 ILT |
4308 | case 'E': /* coprocessor target register */ |
4309 | case 'G': /* coprocessor destination register */ | |
8358c818 | 4310 | case 'x': /* ignore register name */ |
ff3a5c18 | 4311 | case 'z': /* must be zero register */ |
670a50eb ILT |
4312 | s_reset = s; |
4313 | if (s[0] == '$') | |
4314 | { | |
4315 | if (isdigit (s[1])) | |
4316 | { | |
4317 | ++s; | |
4318 | regno = 0; | |
4319 | do | |
4320 | { | |
4321 | regno *= 10; | |
4322 | regno += *s - '0'; | |
4323 | ++s; | |
4324 | } | |
4325 | while (isdigit (*s)); | |
0aa07269 ILT |
4326 | if (regno > 31) |
4327 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 4328 | } |
0dd2d296 ILT |
4329 | else if (*args == 'E' || *args == 'G') |
4330 | goto notreg; | |
4331 | else | |
670a50eb | 4332 | { |
0aa07269 ILT |
4333 | if (s[1] == 'f' && s[2] == 'p') |
4334 | { | |
4335 | s += 3; | |
9226253a | 4336 | regno = FP; |
0aa07269 ILT |
4337 | } |
4338 | else if (s[1] == 's' && s[2] == 'p') | |
4339 | { | |
4340 | s += 3; | |
9226253a | 4341 | regno = SP; |
0aa07269 ILT |
4342 | } |
4343 | else if (s[1] == 'g' && s[2] == 'p') | |
4344 | { | |
4345 | s += 3; | |
9226253a | 4346 | regno = GP; |
0aa07269 ILT |
4347 | } |
4348 | else if (s[1] == 'a' && s[2] == 't') | |
4349 | { | |
4350 | s += 3; | |
9226253a | 4351 | regno = AT; |
0aa07269 ILT |
4352 | } |
4353 | else | |
4354 | goto notreg; | |
670a50eb | 4355 | } |
13fe1379 ILT |
4356 | if (regno == AT && ! mips_noat) |
4357 | as_warn ("Used $at without \".set noat\""); | |
670a50eb ILT |
4358 | c = *args; |
4359 | if (*s == ' ') | |
4360 | s++; | |
4361 | if (args[1] != *s) | |
4362 | { | |
4363 | if (c == 'r' || c == 'v' || c == 'w') | |
4364 | { | |
4365 | regno = lastregno; | |
4366 | s = s_reset; | |
4367 | args++; | |
4368 | } | |
4369 | } | |
ff3a5c18 ILT |
4370 | /* 'z' only matches $0. */ |
4371 | if (c == 'z' && regno != 0) | |
4372 | break; | |
670a50eb ILT |
4373 | switch (c) |
4374 | { | |
3d3c5039 ILT |
4375 | case 'r': |
4376 | case 's': | |
4377 | case 'v': | |
4378 | case 'b': | |
670a50eb ILT |
4379 | ip->insn_opcode |= regno << 21; |
4380 | break; | |
3d3c5039 | 4381 | case 'd': |
918692a5 | 4382 | case 'G': |
670a50eb ILT |
4383 | ip->insn_opcode |= regno << 11; |
4384 | break; | |
3d3c5039 ILT |
4385 | case 'w': |
4386 | case 't': | |
918692a5 | 4387 | case 'E': |
670a50eb | 4388 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
4389 | break; |
4390 | case 'x': | |
4391 | /* This case exists because on the r3000 trunc | |
4392 | expands into a macro which requires a gp | |
4393 | register. On the r6000 or r4000 it is | |
4394 | assembled into a single instruction which | |
4395 | ignores the register. Thus the insn version | |
4396 | is MIPS_ISA2 and uses 'x', and the macro | |
4397 | version is MIPS_ISA1 and uses 't'. */ | |
4398 | break; | |
ff3a5c18 ILT |
4399 | case 'z': |
4400 | /* This case is for the div instruction, which | |
4401 | acts differently if the destination argument | |
4402 | is $0. This only matches $0, and is checked | |
4403 | outside the switch. */ | |
4404 | break; | |
3d3c5039 | 4405 | } |
670a50eb ILT |
4406 | lastregno = regno; |
4407 | continue; | |
3d3c5039 ILT |
4408 | } |
4409 | notreg: | |
670a50eb ILT |
4410 | switch (*args++) |
4411 | { | |
3d3c5039 ILT |
4412 | case 'r': |
4413 | case 'v': | |
670a50eb ILT |
4414 | ip->insn_opcode |= lastregno << 21; |
4415 | continue; | |
3d3c5039 | 4416 | case 'w': |
670a50eb ILT |
4417 | ip->insn_opcode |= lastregno << 16; |
4418 | continue; | |
3d3c5039 | 4419 | } |
670a50eb | 4420 | break; |
3d3c5039 | 4421 | |
670a50eb ILT |
4422 | case 'D': /* floating point destination register */ |
4423 | case 'S': /* floating point source register */ | |
4424 | case 'T': /* floating point target register */ | |
3d3c5039 ILT |
4425 | case 'V': |
4426 | case 'W': | |
670a50eb ILT |
4427 | s_reset = s; |
4428 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
4429 | { | |
4430 | s += 2; | |
4431 | regno = 0; | |
4432 | do | |
4433 | { | |
4434 | regno *= 10; | |
4435 | regno += *s - '0'; | |
4436 | ++s; | |
4437 | } | |
4438 | while (isdigit (*s)); | |
4439 | ||
4440 | if (regno > 31) | |
4441 | as_bad ("Invalid float register number (%d)", regno); | |
4442 | ||
9226253a ILT |
4443 | if ((regno & 1) != 0 |
4444 | && mips_isa < 3 | |
4445 | && ! (strcmp (str, "mtc1") == 0 || | |
4446 | strcmp (str, "mfc1") == 0 || | |
4447 | strcmp (str, "lwc1") == 0 || | |
4448 | strcmp (str, "swc1") == 0)) | |
670a50eb ILT |
4449 | as_warn ("Float register should be even, was %d", |
4450 | regno); | |
4451 | ||
4452 | c = *args; | |
4453 | if (*s == ' ') | |
4454 | s++; | |
4455 | if (args[1] != *s) | |
4456 | { | |
4457 | if (c == 'V' || c == 'W') | |
4458 | { | |
4459 | regno = lastregno; | |
4460 | s = s_reset; | |
4461 | args++; | |
3d3c5039 ILT |
4462 | } |
4463 | } | |
670a50eb ILT |
4464 | switch (c) |
4465 | { | |
3d3c5039 | 4466 | case 'D': |
670a50eb ILT |
4467 | ip->insn_opcode |= regno << 6; |
4468 | break; | |
3d3c5039 ILT |
4469 | case 'V': |
4470 | case 'S': | |
670a50eb ILT |
4471 | ip->insn_opcode |= regno << 11; |
4472 | break; | |
3d3c5039 ILT |
4473 | case 'W': |
4474 | case 'T': | |
670a50eb | 4475 | ip->insn_opcode |= regno << 16; |
3d3c5039 | 4476 | } |
670a50eb ILT |
4477 | lastregno = regno; |
4478 | continue; | |
3d3c5039 | 4479 | } |
670a50eb ILT |
4480 | switch (*args++) |
4481 | { | |
3d3c5039 | 4482 | case 'V': |
670a50eb ILT |
4483 | ip->insn_opcode |= lastregno << 11; |
4484 | continue; | |
3d3c5039 | 4485 | case 'W': |
670a50eb ILT |
4486 | ip->insn_opcode |= lastregno << 16; |
4487 | continue; | |
3d3c5039 | 4488 | } |
670a50eb | 4489 | break; |
3d3c5039 ILT |
4490 | |
4491 | case 'I': | |
670a50eb ILT |
4492 | my_getExpression (&imm_expr, s); |
4493 | check_absolute_expr (ip, &imm_expr); | |
4494 | s = expr_end; | |
4495 | continue; | |
3d3c5039 ILT |
4496 | |
4497 | case 'A': | |
670a50eb ILT |
4498 | my_getExpression (&offset_expr, s); |
4499 | imm_reloc = BFD_RELOC_32; | |
4500 | s = expr_end; | |
4501 | continue; | |
3d3c5039 ILT |
4502 | |
4503 | case 'F': | |
19ed8960 ILT |
4504 | case 'L': |
4505 | case 'f': | |
4506 | case 'l': | |
4507 | { | |
4508 | int f64; | |
4509 | char *save_in; | |
4510 | char *err; | |
4511 | unsigned char temp[8]; | |
604633ae ILT |
4512 | int len; |
4513 | unsigned int length; | |
19ed8960 ILT |
4514 | segT seg; |
4515 | subsegT subseg; | |
4516 | char *p; | |
4517 | ||
4518 | /* These only appear as the last operand in an | |
4519 | instruction, and every instruction that accepts | |
4520 | them in any variant accepts them in all variants. | |
4521 | This means we don't have to worry about backing out | |
4522 | any changes if the instruction does not match. | |
4523 | ||
4524 | The difference between them is the size of the | |
4525 | floating point constant and where it goes. For 'F' | |
4526 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
4527 | is 32 bits. Where the constant is placed is based | |
4528 | on how the MIPS assembler does things: | |
4529 | F -- .rdata | |
4530 | L -- .lit8 | |
4531 | f -- immediate value | |
4532 | l -- .lit4 | |
0dd2d296 | 4533 | |
55933a58 ILT |
4534 | The .lit4 and .lit8 sections are only used if |
4535 | permitted by the -G argument. | |
4536 | ||
4537 | When generating embedded PIC code, we use the | |
4538 | .lit8 section but not the .lit4 section (we can do | |
4539 | .lit4 inline easily; we need to put .lit8 | |
4540 | somewhere in the data segment, and using .lit8 | |
4541 | permits the linker to eventually combine identical | |
4542 | .lit8 entries). */ | |
19ed8960 ILT |
4543 | |
4544 | f64 = *args == 'F' || *args == 'L'; | |
4545 | ||
4546 | save_in = input_line_pointer; | |
4547 | input_line_pointer = s; | |
604633ae ILT |
4548 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
4549 | length = len; | |
19ed8960 ILT |
4550 | s = input_line_pointer; |
4551 | input_line_pointer = save_in; | |
4552 | if (err != NULL && *err != '\0') | |
4553 | { | |
4554 | as_bad ("Bad floating point constant: %s", err); | |
4555 | memset (temp, '\0', sizeof temp); | |
4556 | length = f64 ? 8 : 4; | |
4557 | } | |
4558 | ||
4559 | assert (length == (f64 ? 8 : 4)); | |
4560 | ||
0dd2d296 | 4561 | if (*args == 'f' |
55933a58 ILT |
4562 | || (*args == 'l' |
4563 | && (mips_pic == EMBEDDED_PIC | |
4564 | #ifdef GPOPT | |
4565 | || g_switch_value < 4 | |
4566 | #endif | |
4567 | ))) | |
19ed8960 ILT |
4568 | { |
4569 | imm_expr.X_op = O_constant; | |
4570 | if (byte_order == LITTLE_ENDIAN) | |
4571 | imm_expr.X_add_number = | |
4572 | (((((((int) temp[3] << 8) | |
4573 | | temp[2]) << 8) | |
4574 | | temp[1]) << 8) | |
4575 | | temp[0]); | |
4576 | else | |
4577 | imm_expr.X_add_number = | |
4578 | (((((((int) temp[0] << 8) | |
4579 | | temp[1]) << 8) | |
4580 | | temp[2]) << 8) | |
4581 | | temp[3]); | |
4582 | } | |
4583 | else | |
4584 | { | |
0dd2d296 ILT |
4585 | const char *newname; |
4586 | segT new_seg; | |
4587 | ||
19ed8960 ILT |
4588 | /* Switch to the right section. */ |
4589 | seg = now_seg; | |
4590 | subseg = now_subseg; | |
4591 | switch (*args) | |
4592 | { | |
0dd2d296 | 4593 | default: /* unused default case avoids warnings. */ |
19ed8960 | 4594 | case 'L': |
55933a58 ILT |
4595 | newname = ".lit8"; |
4596 | #ifdef GPOPT | |
4597 | if (g_switch_value < 8) | |
4598 | newname = RDATA_SECTION_NAME; | |
4599 | #endif | |
0dd2d296 ILT |
4600 | break; |
4601 | case 'F': | |
d2c71068 | 4602 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
4603 | break; |
4604 | case 'l': | |
55933a58 ILT |
4605 | #ifdef GPOPT |
4606 | assert (g_switch_value >= 4); | |
4607 | #endif | |
0dd2d296 | 4608 | newname = ".lit4"; |
19ed8960 ILT |
4609 | break; |
4610 | } | |
0dd2d296 | 4611 | new_seg = subseg_new (newname, (subsegT) 0); |
0221ddf7 | 4612 | frag_align (*args == 'l' ? 2 : 3, 0); |
0dd2d296 | 4613 | #ifdef OBJ_ELF |
0221ddf7 ILT |
4614 | record_alignment (new_seg, 4); |
4615 | #else | |
4616 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
0dd2d296 | 4617 | #endif |
19ed8960 ILT |
4618 | if (seg == now_seg) |
4619 | as_bad ("Can't use floating point insn in this section"); | |
4620 | ||
4621 | /* Set the argument to the current address in the | |
6e8dda9c | 4622 | section. */ |
19ed8960 ILT |
4623 | offset_expr.X_op = O_symbol; |
4624 | offset_expr.X_add_symbol = | |
4625 | symbol_new ("L0\001", now_seg, | |
4626 | (valueT) frag_now_fix (), frag_now); | |
4627 | offset_expr.X_add_number = 0; | |
4628 | ||
4629 | /* Put the floating point number into the section. */ | |
604633ae | 4630 | p = frag_more ((int) length); |
19ed8960 ILT |
4631 | memcpy (p, temp, length); |
4632 | ||
4633 | /* Switch back to the original section. */ | |
4634 | subseg_set (seg, subseg); | |
4635 | } | |
4636 | } | |
670a50eb ILT |
4637 | continue; |
4638 | ||
4639 | case 'i': /* 16 bit unsigned immediate */ | |
4640 | case 'j': /* 16 bit signed immediate */ | |
4641 | imm_reloc = BFD_RELOC_LO16; | |
4642 | c = my_getSmallExpression (&imm_expr, s); | |
4643 | if (c) | |
4644 | { | |
4645 | if (c != 'l') | |
4646 | { | |
5ac34ac3 | 4647 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
4648 | imm_expr.X_add_number = |
4649 | (imm_expr.X_add_number >> 16) & 0xffff; | |
4650 | else if (c == 'h') | |
4651 | imm_reloc = BFD_RELOC_HI16_S; | |
4652 | else | |
4653 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 4654 | } |
670a50eb ILT |
4655 | } |
4656 | else | |
4657 | check_absolute_expr (ip, &imm_expr); | |
4658 | if (*args == 'i') | |
4659 | { | |
6e8dda9c ILT |
4660 | if (imm_expr.X_add_number < 0 |
4661 | || imm_expr.X_add_number >= 0x10000) | |
99c24539 ILT |
4662 | { |
4663 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4664 | !strcmp (insn->name, insn[1].name)) | |
4665 | break; | |
4666 | as_bad ("16 bit expression not in range 0..65535"); | |
4667 | } | |
670a50eb ILT |
4668 | } |
4669 | else | |
4670 | { | |
d9aba805 ILT |
4671 | int more; |
4672 | offsetT max; | |
4673 | ||
be22008b ILT |
4674 | /* The upper bound should be 0x8000, but |
4675 | unfortunately the MIPS assembler accepts numbers | |
4676 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
4677 | we want to be compatible. We only permit this |
4678 | extended range for an instruction which does not | |
4679 | provide any further alternates, since those | |
4680 | alternates may handle other cases. People should | |
4681 | use the numbers they mean, rather than relying on | |
4682 | a mysterious sign extension. */ | |
4683 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4684 | strcmp (insn->name, insn[1].name) == 0); | |
4685 | if (more) | |
4686 | max = 0x8000; | |
4687 | else | |
4688 | max = 0x10000; | |
6e8dda9c | 4689 | if (imm_expr.X_add_number < -0x8000 || |
d9aba805 | 4690 | imm_expr.X_add_number >= max) |
99c24539 | 4691 | { |
d9aba805 | 4692 | if (more) |
99c24539 ILT |
4693 | break; |
4694 | as_bad ("16 bit expression not in range -32768..32767"); | |
4695 | } | |
3d3c5039 | 4696 | } |
670a50eb ILT |
4697 | s = expr_end; |
4698 | continue; | |
4699 | ||
4700 | case 'o': /* 16 bit offset */ | |
4701 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
4702 | |
4703 | /* If this value won't fit into a 16 bit offset, then go | |
4704 | find a macro that will generate the 32 bit offset | |
4705 | code pattern. As a special hack, we accept the | |
4706 | difference of two local symbols as a constant. This | |
4707 | is required to suppose embedded PIC switches, which | |
4708 | use an instruction which looks like | |
4709 | lw $4,$L12-$LS12($4) | |
4710 | The problem with handling this in a more general | |
4711 | fashion is that the macro function doesn't expect to | |
4712 | see anything which can be handled in a single | |
4713 | constant instruction. */ | |
6f0b87c3 SS |
4714 | if (c == 0 |
4715 | && (offset_expr.X_op != O_constant | |
4716 | || offset_expr.X_add_number >= 0x8000 | |
4717 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
4718 | && (mips_pic != EMBEDDED_PIC |
4719 | || offset_expr.X_op != O_subtract | |
4720 | || ! S_IS_LOCAL (offset_expr.X_add_symbol) | |
4721 | || ! S_IS_LOCAL (offset_expr.X_op_symbol))) | |
670a50eb | 4722 | break; |
3d3c5039 | 4723 | |
670a50eb ILT |
4724 | offset_reloc = BFD_RELOC_LO16; |
4725 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
4726 | { |
4727 | assert (offset_expr.X_op == O_constant); | |
4728 | offset_expr.X_add_number = | |
4729 | (offset_expr.X_add_number >> 16) & 0xffff; | |
4730 | } | |
670a50eb ILT |
4731 | s = expr_end; |
4732 | continue; | |
4733 | ||
4734 | case 'p': /* pc relative offset */ | |
4735 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
4736 | my_getExpression (&offset_expr, s); | |
4737 | s = expr_end; | |
4738 | continue; | |
4739 | ||
4740 | case 'u': /* upper 16 bits */ | |
4741 | c = my_getSmallExpression (&imm_expr, s); | |
36a87ad7 ILT |
4742 | if (imm_expr.X_op == O_constant |
4743 | && (imm_expr.X_add_number < 0 | |
4744 | || imm_expr.X_add_number >= 0x10000)) | |
670a50eb ILT |
4745 | as_bad ("lui expression not in range 0..65535"); |
4746 | imm_reloc = BFD_RELOC_LO16; | |
4747 | if (c) | |
4748 | { | |
4749 | if (c != 'l') | |
4750 | { | |
5ac34ac3 | 4751 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
4752 | imm_expr.X_add_number = |
4753 | (imm_expr.X_add_number >> 16) & 0xffff; | |
4754 | else if (c == 'h') | |
4755 | imm_reloc = BFD_RELOC_HI16_S; | |
4756 | else | |
4757 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 ILT |
4758 | } |
4759 | } | |
670a50eb ILT |
4760 | s = expr_end; |
4761 | continue; | |
3d3c5039 | 4762 | |
670a50eb ILT |
4763 | case 'a': /* 26 bit address */ |
4764 | my_getExpression (&offset_expr, s); | |
4765 | s = expr_end; | |
4766 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
4767 | continue; | |
3d3c5039 ILT |
4768 | |
4769 | default: | |
670a50eb ILT |
4770 | fprintf (stderr, "bad char = '%c'\n", *args); |
4771 | internalError (); | |
3d3c5039 | 4772 | } |
670a50eb | 4773 | break; |
3d3c5039 | 4774 | } |
670a50eb ILT |
4775 | /* Args don't match. */ |
4776 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4777 | !strcmp (insn->name, insn[1].name)) | |
4778 | { | |
4779 | ++insn; | |
4780 | s = argsStart; | |
4781 | continue; | |
3d3c5039 | 4782 | } |
670a50eb ILT |
4783 | insn_error = "ERROR: Illegal operands"; |
4784 | return; | |
3d3c5039 ILT |
4785 | } |
4786 | } | |
4787 | ||
4788 | #define LP '(' | |
4789 | #define RP ')' | |
4790 | ||
4791 | static int | |
4792 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
4793 | expressionS *ep; |
4794 | char *str; | |
3d3c5039 | 4795 | { |
670a50eb ILT |
4796 | char *sp; |
4797 | int c = 0; | |
4798 | ||
4799 | if (*str == ' ') | |
4800 | str++; | |
4801 | if (*str == LP | |
4802 | || (*str == '%' && | |
4803 | ((str[1] == 'h' && str[2] == 'i') | |
4804 | || (str[1] == 'H' && str[2] == 'I') | |
4805 | || (str[1] == 'l' && str[2] == 'o')) | |
4806 | && str[3] == LP)) | |
4807 | { | |
4808 | if (*str == LP) | |
4809 | c = 0; | |
4810 | else | |
4811 | { | |
4812 | c = str[1]; | |
4813 | str += 3; | |
4814 | } | |
4815 | ||
4816 | /* | |
4817 | * A small expression may be followed by a base register. | |
4818 | * Scan to the end of this operand, and then back over a possible | |
4819 | * base register. Then scan the small expression up to that | |
4820 | * point. (Based on code in sparc.c...) | |
4821 | */ | |
4822 | for (sp = str; *sp && *sp != ','; sp++) | |
4823 | ; | |
4824 | if (sp - 4 >= str && sp[-1] == RP) | |
4825 | { | |
4826 | if (isdigit (sp[-2])) | |
4827 | { | |
4828 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
4829 | ; | |
4830 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
4831 | { | |
4832 | sp--; | |
4833 | goto do_it; | |
3d3c5039 | 4834 | } |
670a50eb ILT |
4835 | } |
4836 | else if (sp - 5 >= str | |
4837 | && sp[-5] == LP | |
4838 | && sp[-4] == '$' | |
4839 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
4840 | || (sp[-3] == 's' && sp[-2] == 'p') | |
4841 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
4842 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
4843 | { | |
4844 | sp -= 5; | |
3d3c5039 | 4845 | do_it: |
670a50eb ILT |
4846 | if (sp == str) |
4847 | { | |
4848 | /* no expression means zero offset */ | |
4849 | if (c) | |
4850 | { | |
4851 | /* %xx(reg) is an error */ | |
5ac34ac3 | 4852 | ep->X_op = O_absent; |
670a50eb | 4853 | expr_end = str - 3; |
3d3c5039 | 4854 | } |
670a50eb ILT |
4855 | else |
4856 | { | |
52aa70b5 | 4857 | ep->X_op = O_constant; |
670a50eb ILT |
4858 | expr_end = sp; |
4859 | } | |
4860 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 4861 | ep->X_op_symbol = NULL; |
670a50eb ILT |
4862 | ep->X_add_number = 0; |
4863 | } | |
4864 | else | |
4865 | { | |
4866 | *sp = '\0'; | |
4867 | my_getExpression (ep, str); | |
4868 | *sp = LP; | |
3d3c5039 | 4869 | } |
670a50eb | 4870 | return c; |
3d3c5039 ILT |
4871 | } |
4872 | } | |
4873 | } | |
670a50eb ILT |
4874 | my_getExpression (ep, str); |
4875 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
4876 | } |
4877 | ||
4878 | static void | |
4879 | my_getExpression (ep, str) | |
670a50eb ILT |
4880 | expressionS *ep; |
4881 | char *str; | |
3d3c5039 | 4882 | { |
670a50eb | 4883 | char *save_in; |
670a50eb ILT |
4884 | |
4885 | save_in = input_line_pointer; | |
4886 | input_line_pointer = str; | |
5ac34ac3 | 4887 | expression (ep); |
670a50eb ILT |
4888 | expr_end = input_line_pointer; |
4889 | input_line_pointer = save_in; | |
3d3c5039 ILT |
4890 | } |
4891 | ||
becfe05e ILT |
4892 | /* Turn a string in input_line_pointer into a floating point constant |
4893 | of type type, and store the appropriate bytes in *litP. The number | |
4894 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
4895 | returned, or NULL on OK. */ | |
4896 | ||
3d3c5039 | 4897 | char * |
670a50eb | 4898 | md_atof (type, litP, sizeP) |
becfe05e | 4899 | int type; |
3d3c5039 ILT |
4900 | char *litP; |
4901 | int *sizeP; | |
4902 | { | |
becfe05e ILT |
4903 | int prec; |
4904 | LITTLENUM_TYPE words[4]; | |
4905 | char *t; | |
4906 | int i; | |
4907 | ||
4908 | switch (type) | |
4909 | { | |
4910 | case 'f': | |
4911 | prec = 2; | |
4912 | break; | |
4913 | ||
4914 | case 'd': | |
4915 | prec = 4; | |
4916 | break; | |
4917 | ||
4918 | default: | |
4919 | *sizeP = 0; | |
4920 | return "bad call to md_atof"; | |
4921 | } | |
4922 | ||
4923 | t = atof_ieee (input_line_pointer, type, words); | |
4924 | if (t) | |
4925 | input_line_pointer = t; | |
4926 | ||
4927 | *sizeP = prec * 2; | |
4928 | ||
4929 | if (byte_order == LITTLE_ENDIAN) | |
4930 | { | |
4931 | for (i = prec - 1; i >= 0; i--) | |
4932 | { | |
4933 | md_number_to_chars (litP, (valueT) words[i], 2); | |
4934 | litP += 2; | |
4935 | } | |
4936 | } | |
4937 | else | |
4938 | { | |
4939 | for (i = 0; i < prec; i++) | |
4940 | { | |
4941 | md_number_to_chars (litP, (valueT) words[i], 2); | |
4942 | litP += 2; | |
4943 | } | |
4944 | } | |
4945 | ||
670a50eb | 4946 | return NULL; |
3d3c5039 ILT |
4947 | } |
4948 | ||
4949 | void | |
4950 | md_number_to_chars (buf, val, n) | |
4951 | char *buf; | |
918692a5 | 4952 | valueT val; |
3d3c5039 ILT |
4953 | int n; |
4954 | { | |
670a50eb ILT |
4955 | switch (byte_order) |
4956 | { | |
3d3c5039 | 4957 | case LITTLE_ENDIAN: |
13fe1379 ILT |
4958 | number_to_chars_littleendian (buf, val, n); |
4959 | break; | |
3d3c5039 ILT |
4960 | |
4961 | case BIG_ENDIAN: | |
13fe1379 ILT |
4962 | number_to_chars_bigendian (buf, val, n); |
4963 | break; | |
3d3c5039 ILT |
4964 | |
4965 | default: | |
670a50eb | 4966 | internalError (); |
3d3c5039 ILT |
4967 | } |
4968 | } | |
f3d817d8 DM |
4969 | \f |
4970 | #ifdef GPOPT | |
e8d4d475 | 4971 | CONST char *md_shortopts = "O::g::G:"; |
f3d817d8 | 4972 | #else |
e8d4d475 | 4973 | CONST char *md_shortopts = "O::g::"; |
f3d817d8 DM |
4974 | #endif |
4975 | struct option md_longopts[] = { | |
4976 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
4977 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
4978 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
4979 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
4980 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
4981 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
4982 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
4983 | #define OPTION_MCPU (OPTION_MD_BASE + 4) | |
4984 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
4985 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5) | |
4986 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
4987 | #define OPTION_TRAP (OPTION_MD_BASE + 8) | |
4988 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
4989 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
4990 | #define OPTION_BREAK (OPTION_MD_BASE + 9) | |
4991 | {"break", no_argument, NULL, OPTION_BREAK}, | |
4992 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
e8d4d475 ILT |
4993 | #define OPTION_EB (OPTION_MD_BASE + 10) |
4994 | {"EB", no_argument, NULL, OPTION_EB}, | |
4995 | #define OPTION_EL (OPTION_MD_BASE + 11) | |
4996 | {"EL", no_argument, NULL, OPTION_EL}, | |
f3d817d8 DM |
4997 | |
4998 | #ifdef OBJ_ELF | |
4999 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6) | |
5000 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
5001 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
5002 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 7) | |
5003 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
5004 | #endif | |
5005 | ||
5006 | {NULL, no_argument, NULL, 0} | |
5007 | }; | |
5008 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
5009 | |
5010 | int | |
f3d817d8 DM |
5011 | md_parse_option (c, arg) |
5012 | int c; | |
5013 | char *arg; | |
3d3c5039 | 5014 | { |
f3d817d8 | 5015 | switch (c) |
670a50eb | 5016 | { |
f3d817d8 DM |
5017 | case OPTION_TRAP: |
5018 | mips_trap = 1; | |
5019 | break; | |
670a50eb | 5020 | |
f3d817d8 DM |
5021 | case OPTION_BREAK: |
5022 | mips_trap = 0; | |
5023 | break; | |
5024 | ||
e8d4d475 ILT |
5025 | case OPTION_EB: |
5026 | byte_order = BIG_ENDIAN; | |
04cb3372 | 5027 | #ifdef OBJ_AOUT |
e8d4d475 | 5028 | mips_target_format = "a.out-mips-big"; |
04cb3372 ILT |
5029 | #endif |
5030 | #ifdef OBJ_ECOFF | |
e8d4d475 | 5031 | mips_target_format = "ecoff-bigmips"; |
04cb3372 ILT |
5032 | #endif |
5033 | #ifdef OBJ_ELF | |
e8d4d475 | 5034 | mips_target_format = "elf32-bigmips"; |
04cb3372 | 5035 | #endif |
e8d4d475 | 5036 | break; |
04cb3372 | 5037 | |
e8d4d475 ILT |
5038 | case OPTION_EL: |
5039 | byte_order = LITTLE_ENDIAN; | |
5040 | #ifdef OBJ_AOUT | |
5041 | mips_target_format = "a.out-mips-little"; | |
5042 | #endif | |
5043 | #ifdef OBJ_ECOFF | |
5044 | mips_target_format = "ecoff-littlemips"; | |
5045 | #endif | |
5046 | #ifdef OBJ_ELF | |
5047 | mips_target_format = "elf32-littlemips"; | |
5048 | #endif | |
f3d817d8 | 5049 | break; |
670a50eb | 5050 | |
f3d817d8 DM |
5051 | case 'O': |
5052 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
5053 | mips_optimize = 1; |
5054 | else | |
5055 | mips_optimize = 2; | |
f3d817d8 | 5056 | break; |
0aa07269 | 5057 | |
f3d817d8 DM |
5058 | case 'g': |
5059 | if (arg == NULL || arg[1] == '2') | |
0aa07269 | 5060 | mips_optimize = 0; |
f3d817d8 | 5061 | break; |
4e95866e | 5062 | |
f3d817d8 DM |
5063 | case OPTION_MIPS1: |
5064 | mips_isa = 1; | |
8c63448a | 5065 | mips_cpu = 3000; |
f3d817d8 | 5066 | break; |
8358c818 | 5067 | |
f3d817d8 DM |
5068 | case OPTION_MIPS2: |
5069 | mips_isa = 2; | |
8c63448a | 5070 | mips_cpu = 6000; |
f3d817d8 | 5071 | break; |
8358c818 | 5072 | |
f3d817d8 DM |
5073 | case OPTION_MIPS3: |
5074 | mips_isa = 3; | |
8c63448a | 5075 | mips_cpu = 4000; |
f3d817d8 | 5076 | break; |
8358c818 | 5077 | |
f3d817d8 DM |
5078 | case OPTION_MCPU: |
5079 | { | |
5080 | char *p; | |
5081 | ||
5082 | /* Identify the processor type */ | |
5083 | p = arg; | |
5084 | if (strcmp (p, "default") == 0 | |
5085 | || strcmp (p, "DEFAULT") == 0) | |
8358c818 | 5086 | mips_isa = -1; |
f3d817d8 DM |
5087 | else |
5088 | { | |
5089 | if (*p == 'r' || *p == 'R') | |
5090 | p++; | |
8358c818 | 5091 | |
f3d817d8 DM |
5092 | mips_isa = -1; |
5093 | switch (*p) | |
5094 | { | |
5095 | case '2': | |
5096 | if (strcmp (p, "2000") == 0 | |
5097 | || strcmp (p, "2k") == 0 | |
5098 | || strcmp (p, "2K") == 0) | |
8c63448a ILT |
5099 | { |
5100 | mips_isa = 1; | |
5101 | mips_cpu = 2000; | |
5102 | } | |
f3d817d8 | 5103 | break; |
8358c818 | 5104 | |
f3d817d8 DM |
5105 | case '3': |
5106 | if (strcmp (p, "3000") == 0 | |
5107 | || strcmp (p, "3k") == 0 | |
5108 | || strcmp (p, "3K") == 0) | |
8c63448a ILT |
5109 | { |
5110 | mips_isa = 1; | |
5111 | mips_cpu = 3000; | |
5112 | } | |
f3d817d8 | 5113 | break; |
8358c818 | 5114 | |
f3d817d8 DM |
5115 | case '4': |
5116 | if (strcmp (p, "4000") == 0 | |
5117 | || strcmp (p, "4k") == 0 | |
8c63448a ILT |
5118 | || strcmp (p, "4K") == 0) |
5119 | { | |
5120 | mips_isa = 3; | |
5121 | mips_cpu = 4000; | |
5122 | } | |
5123 | else if (strcmp (p, "4400") == 0) | |
5124 | { | |
5125 | mips_isa = 3; | |
5126 | mips_cpu = 4400; | |
5127 | } | |
5128 | else if (strcmp (p, "4600") == 0) | |
5129 | { | |
5130 | mips_isa = 3; | |
5131 | mips_cpu = 4600; | |
5132 | } | |
f3d817d8 | 5133 | break; |
8358c818 | 5134 | |
f3d817d8 DM |
5135 | case '6': |
5136 | if (strcmp (p, "6000") == 0 | |
5137 | || strcmp (p, "6k") == 0 | |
5138 | || strcmp (p, "6K") == 0) | |
8c63448a ILT |
5139 | { |
5140 | mips_isa = 2; | |
5141 | mips_cpu = 6000; | |
5142 | } | |
f3d817d8 | 5143 | break; |
55933a58 ILT |
5144 | |
5145 | case 'o': | |
5146 | if (strcmp (p, "orion") == 0) | |
8c63448a ILT |
5147 | { |
5148 | mips_isa = 3; | |
5149 | mips_cpu = 4600; | |
5150 | } | |
55933a58 | 5151 | break; |
f3d817d8 | 5152 | } |
8358c818 | 5153 | |
f3d817d8 DM |
5154 | if (mips_isa == -1) |
5155 | { | |
5156 | as_bad ("invalid architecture -mcpu=%s", arg); | |
5157 | return 0; | |
5158 | } | |
5159 | } | |
5160 | } | |
5161 | break; | |
8358c818 | 5162 | |
f3d817d8 | 5163 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 5164 | mips_pic = EMBEDDED_PIC; |
5b63f465 ILT |
5165 | #ifdef GPOPT |
5166 | if (g_switch_seen) | |
f3d817d8 DM |
5167 | { |
5168 | as_bad ("-G may not be used with embedded PIC code"); | |
5169 | return 0; | |
5170 | } | |
5b63f465 ILT |
5171 | g_switch_value = 0x7fffffff; |
5172 | #endif | |
f3d817d8 | 5173 | break; |
d9aba805 ILT |
5174 | |
5175 | #ifdef OBJ_ELF | |
5176 | /* When generating ELF code, we permit -KPIC and -call_shared to | |
5177 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
5178 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 5179 | case OPTION_CALL_SHARED: |
d9aba805 ILT |
5180 | mips_pic = SVR4_PIC; |
5181 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
5182 | { |
5183 | as_bad ("-G may not be used with SVR4 PIC code"); | |
5184 | return 0; | |
5185 | } | |
d9aba805 | 5186 | g_switch_value = 0; |
f3d817d8 DM |
5187 | break; |
5188 | ||
5189 | case OPTION_NON_SHARED: | |
d9aba805 | 5190 | mips_pic = NO_PIC; |
f3d817d8 | 5191 | break; |
d9aba805 | 5192 | #endif /* OBJ_ELF */ |
8358c818 | 5193 | |
88225433 | 5194 | #ifdef GPOPT |
f3d817d8 | 5195 | case 'G': |
5b63f465 | 5196 | if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) |
670a50eb | 5197 | { |
f3d817d8 DM |
5198 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
5199 | return 0; | |
670a50eb ILT |
5200 | } |
5201 | else | |
f3d817d8 | 5202 | g_switch_value = atoi (arg); |
42562568 | 5203 | g_switch_seen = 1; |
f3d817d8 | 5204 | break; |
670a50eb | 5205 | #endif |
4e95866e | 5206 | |
f3d817d8 DM |
5207 | default: |
5208 | return 0; | |
8ea7f4e8 ILT |
5209 | } |
5210 | ||
f3d817d8 | 5211 | return 1; |
8ea7f4e8 ILT |
5212 | } |
5213 | ||
f3d817d8 DM |
5214 | void |
5215 | md_show_usage (stream) | |
5216 | FILE *stream; | |
5217 | { | |
5218 | fprintf(stream, "\ | |
5219 | MIPS options:\n\ | |
5220 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
5221 | -EB generate big endian output\n\ |
5222 | -EL generate little endian output\n\ | |
5223 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
5224 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
5225 | implicitly with the gp register [default 8]\n"); |
5226 | fprintf(stream, "\ | |
f3d817d8 DM |
5227 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
5228 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
5229 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
5230 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
5231 | -O remove unneeded NOPs and swap branches\n\ | |
5232 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
5233 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
5234 | #ifdef OBJ_ELF | |
5235 | fprintf(stream, "\ | |
5236 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
5237 | -non_shared do not generate position independent code\n"); | |
5238 | #endif | |
5239 | } | |
5240 | \f | |
3d3c5039 ILT |
5241 | long |
5242 | md_pcrel_from (fixP) | |
5243 | fixS *fixP; | |
5244 | { | |
5b63f465 ILT |
5245 | #ifndef OBJ_AOUT |
5246 | if (fixP->fx_addsy != (symbolS *) NULL | |
5247 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
5248 | { | |
5249 | /* This makes a branch to an undefined symbol be a branch to the | |
5250 | current location. */ | |
5251 | return 4; | |
5252 | } | |
5253 | #endif | |
5254 | ||
670a50eb ILT |
5255 | /* return the address of the delay slot */ |
5256 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
5257 | } |
5258 | ||
abdad6bc ILT |
5259 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
5260 | reloc for a cons. We could use the definition there, except that | |
5261 | we want to handle 64 bit relocs specially. */ | |
5262 | ||
5263 | void | |
5264 | cons_fix_new_mips (frag, where, nbytes, exp) | |
5265 | fragS *frag; | |
5266 | int where; | |
5267 | unsigned int nbytes; | |
5268 | expressionS *exp; | |
5269 | { | |
5270 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
5271 | 4 byte reloc. | |
5272 | FIXME: There is no way to select anything but 32 bit mode right | |
5273 | now. */ | |
5274 | if (nbytes == 8) | |
5275 | { | |
5276 | if (byte_order == BIG_ENDIAN) | |
5277 | where += 4; | |
5278 | nbytes = 4; | |
5279 | } | |
5280 | ||
5281 | if (nbytes != 2 && nbytes != 4) | |
5282 | as_bad ("Unsupported reloc size %d", nbytes); | |
5283 | ||
5284 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
5285 | nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32); | |
5286 | } | |
5287 | ||
1c803e52 ILT |
5288 | /* When generating embedded PIC code we need to use a special |
5289 | relocation to represent the difference of two symbols in the .text | |
5290 | section (switch tables use a difference of this sort). See | |
5291 | include/coff/mips.h for details. This macro checks whether this | |
5292 | fixup requires the special reloc. */ | |
5293 | #define SWITCH_TABLE(fixp) \ | |
5294 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
5295 | && (fixp)->fx_addsy != NULL \ | |
5296 | && (fixp)->fx_subsy != NULL \ | |
5297 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
5298 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
5299 | ||
5b63f465 | 5300 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
5301 | relocations, in case the linker has to relax a call. We also need |
5302 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
5303 | |
5304 | /*ARGSUSED*/ | |
5305 | int | |
5306 | mips_force_relocation (fixp) | |
5307 | fixS *fixp; | |
5308 | { | |
1c803e52 | 5309 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
5310 | && (fixp->fx_pcrel |
5311 | || SWITCH_TABLE (fixp) | |
5312 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
5313 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
5314 | } |
5315 | ||
5316 | /* Apply a fixup to the object file. */ | |
5317 | ||
3d3c5039 ILT |
5318 | int |
5319 | md_apply_fix (fixP, valueP) | |
5320 | fixS *fixP; | |
918692a5 | 5321 | valueT *valueP; |
3d3c5039 | 5322 | { |
670a50eb ILT |
5323 | unsigned char *buf; |
5324 | long insn, value; | |
3d3c5039 | 5325 | |
670a50eb | 5326 | assert (fixP->fx_size == 4); |
3d3c5039 | 5327 | |
670a50eb ILT |
5328 | value = *valueP; |
5329 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 5330 | |
5b63f465 ILT |
5331 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
5332 | fixP->fx_done = 1; | |
5333 | ||
670a50eb ILT |
5334 | switch (fixP->fx_r_type) |
5335 | { | |
3d3c5039 ILT |
5336 | case BFD_RELOC_MIPS_JMP: |
5337 | case BFD_RELOC_HI16: | |
5338 | case BFD_RELOC_HI16_S: | |
670a50eb | 5339 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
5340 | case BFD_RELOC_MIPS_LITERAL: |
5341 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
5342 | case BFD_RELOC_MIPS_GOT16: |
5343 | case BFD_RELOC_MIPS_GPREL32: | |
ecd4ca1c ILT |
5344 | if (fixP->fx_pcrel) |
5345 | as_bad ("Invalid PC relative reloc"); | |
670a50eb | 5346 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 5347 | break; |
3d3c5039 | 5348 | |
ecd4ca1c ILT |
5349 | case BFD_RELOC_PCREL_HI16_S: |
5350 | /* The addend for this is tricky if it is internal, so we just | |
5351 | do everything here rather than in bfd_perform_relocation. */ | |
5352 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
5353 | { | |
5354 | /* For an external symbol adjust by the address to make it | |
5355 | pcrel_offset. We use the address of the RELLO reloc | |
5356 | which follows this one. */ | |
5357 | value += (fixP->fx_next->fx_frag->fr_address | |
5358 | + fixP->fx_next->fx_where); | |
5359 | } | |
5360 | if (value & 0x8000) | |
5361 | value += 0x10000; | |
5362 | value >>= 16; | |
0221ddf7 | 5363 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
5364 | if (byte_order == BIG_ENDIAN) |
5365 | buf += 2; | |
5366 | md_number_to_chars (buf, value, 2); | |
5367 | break; | |
5368 | ||
5369 | case BFD_RELOC_PCREL_LO16: | |
5370 | /* The addend for this is tricky if it is internal, so we just | |
5371 | do everything here rather than in bfd_perform_relocation. */ | |
5372 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
5373 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 5374 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
5375 | if (byte_order == BIG_ENDIAN) |
5376 | buf += 2; | |
5377 | md_number_to_chars (buf, value, 2); | |
5378 | break; | |
5379 | ||
f3645945 ILT |
5380 | case BFD_RELOC_32: |
5381 | /* If we are deleting this reloc entry, we must fill in the | |
5382 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
5383 | resolved when it appears but is later defined. We also need |
5384 | to fill in the value if this is an embedded PIC switch table | |
5385 | entry. */ | |
5386 | if (fixP->fx_done | |
5387 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
5388 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5389 | value, 4); | |
5390 | break; | |
5391 | ||
5392 | case BFD_RELOC_LO16: | |
5393 | /* When handling an embedded PIC switch statement, we can wind | |
5394 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
5395 | if (fixP->fx_done) | |
5396 | { | |
5397 | if (value < -0x8000 || value > 0x7fff) | |
5398 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5399 | "relocation overflow"); | |
0221ddf7 | 5400 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
f3645945 ILT |
5401 | if (byte_order == BIG_ENDIAN) |
5402 | buf += 2; | |
5403 | md_number_to_chars (buf, value, 2); | |
5404 | } | |
5405 | break; | |
5406 | ||
3d3c5039 | 5407 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
5408 | /* |
5409 | * We need to save the bits in the instruction since fixup_segment() | |
5410 | * might be deleting the relocation entry (i.e., a branch within | |
5411 | * the current segment). | |
5412 | */ | |
5413 | if (value & 0x3) | |
58d4951d | 5414 | as_warn ("Branch to odd address (%lx)", value); |
670a50eb ILT |
5415 | value >>= 2; |
5416 | if ((value & ~0xFFFF) && (value & ~0xFFFF) != (-1 & ~0xFFFF)) | |
5417 | as_bad ("Relocation overflow"); | |
5418 | ||
5419 | /* update old instruction data */ | |
5420 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
5421 | switch (byte_order) | |
5422 | { | |
3d3c5039 | 5423 | case LITTLE_ENDIAN: |
670a50eb ILT |
5424 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
5425 | break; | |
3d3c5039 ILT |
5426 | |
5427 | case BIG_ENDIAN: | |
670a50eb ILT |
5428 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
5429 | break; | |
3d3c5039 ILT |
5430 | |
5431 | default: | |
670a50eb ILT |
5432 | internalError (); |
5433 | return 0; | |
3d3c5039 | 5434 | } |
670a50eb | 5435 | insn |= value & 0xFFFF; |
604633ae | 5436 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 5437 | break; |
3d3c5039 ILT |
5438 | |
5439 | default: | |
670a50eb | 5440 | internalError (); |
3d3c5039 | 5441 | } |
5b63f465 | 5442 | |
670a50eb | 5443 | return 1; |
3d3c5039 ILT |
5444 | } |
5445 | ||
5446 | #if 0 | |
5447 | void | |
670a50eb ILT |
5448 | printInsn (oc) |
5449 | unsigned long oc; | |
3d3c5039 | 5450 | { |
670a50eb ILT |
5451 | const struct mips_opcode *p; |
5452 | int treg, sreg, dreg, shamt; | |
5453 | short imm; | |
5454 | const char *args; | |
5455 | int i; | |
3d3c5039 | 5456 | |
670a50eb ILT |
5457 | for (i = 0; i < NUMOPCODES; ++i) |
5458 | { | |
5459 | p = &mips_opcodes[i]; | |
5460 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
5461 | { | |
5462 | printf ("%08lx %s\t", oc, p->name); | |
5463 | treg = (oc >> 16) & 0x1f; | |
5464 | sreg = (oc >> 21) & 0x1f; | |
5465 | dreg = (oc >> 11) & 0x1f; | |
5466 | shamt = (oc >> 6) & 0x1f; | |
5467 | imm = oc; | |
5468 | for (args = p->args;; ++args) | |
5469 | { | |
5470 | switch (*args) | |
5471 | { | |
3d3c5039 | 5472 | case '\0': |
670a50eb ILT |
5473 | printf ("\n"); |
5474 | break; | |
3d3c5039 ILT |
5475 | |
5476 | case ',': | |
5477 | case '(': | |
5478 | case ')': | |
670a50eb ILT |
5479 | printf ("%c", *args); |
5480 | continue; | |
3d3c5039 ILT |
5481 | |
5482 | case 'r': | |
670a50eb ILT |
5483 | assert (treg == sreg); |
5484 | printf ("$%d,$%d", treg, sreg); | |
5485 | continue; | |
3d3c5039 ILT |
5486 | |
5487 | case 'd': | |
918692a5 | 5488 | case 'G': |
670a50eb ILT |
5489 | printf ("$%d", dreg); |
5490 | continue; | |
3d3c5039 ILT |
5491 | |
5492 | case 't': | |
918692a5 | 5493 | case 'E': |
670a50eb ILT |
5494 | printf ("$%d", treg); |
5495 | continue; | |
3d3c5039 | 5496 | |
9226253a ILT |
5497 | case 'k': |
5498 | printf ("0x%x", treg); | |
5499 | continue; | |
5500 | ||
3d3c5039 ILT |
5501 | case 'b': |
5502 | case 's': | |
670a50eb ILT |
5503 | printf ("$%d", sreg); |
5504 | continue; | |
3d3c5039 ILT |
5505 | |
5506 | case 'a': | |
670a50eb ILT |
5507 | printf ("0x%08lx", oc & 0x1ffffff); |
5508 | continue; | |
3d3c5039 ILT |
5509 | |
5510 | case 'i': | |
5511 | case 'j': | |
5512 | case 'o': | |
5513 | case 'u': | |
670a50eb ILT |
5514 | printf ("%d", imm); |
5515 | continue; | |
3d3c5039 ILT |
5516 | |
5517 | case '<': | |
56c96faa | 5518 | case '>': |
670a50eb ILT |
5519 | printf ("$%d", shamt); |
5520 | continue; | |
3d3c5039 ILT |
5521 | |
5522 | default: | |
670a50eb | 5523 | internalError (); |
3d3c5039 | 5524 | } |
670a50eb | 5525 | break; |
3d3c5039 | 5526 | } |
670a50eb | 5527 | return; |
3d3c5039 ILT |
5528 | } |
5529 | } | |
670a50eb | 5530 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
5531 | } |
5532 | #endif | |
5533 | ||
5534 | static symbolS * | |
5535 | get_symbol () | |
5536 | { | |
670a50eb ILT |
5537 | int c; |
5538 | char *name; | |
5539 | symbolS *p; | |
5540 | ||
5541 | name = input_line_pointer; | |
5542 | c = get_symbol_end (); | |
5543 | p = (symbolS *) symbol_find_or_make (name); | |
5544 | *input_line_pointer = c; | |
5545 | return p; | |
3d3c5039 ILT |
5546 | } |
5547 | ||
becfe05e ILT |
5548 | /* Align the current frag to a given power of two. The MIPS assembler |
5549 | also automatically adjusts any preceding label. */ | |
5550 | ||
5551 | static void | |
23dc1ae3 | 5552 | mips_align (to, fill, label) |
becfe05e ILT |
5553 | int to; |
5554 | int fill; | |
23dc1ae3 | 5555 | symbolS *label; |
becfe05e ILT |
5556 | { |
5557 | mips_emit_delays (); | |
5558 | frag_align (to, fill); | |
5559 | record_alignment (now_seg, to); | |
23dc1ae3 | 5560 | if (label != NULL) |
becfe05e | 5561 | { |
23dc1ae3 ILT |
5562 | assert (S_GET_SEGMENT (label) == now_seg); |
5563 | label->sy_frag = frag_now; | |
5564 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
5565 | } |
5566 | } | |
5567 | ||
5568 | /* Align to a given power of two. .align 0 turns off the automatic | |
5569 | alignment used by the data creating pseudo-ops. */ | |
5570 | ||
3d3c5039 ILT |
5571 | static void |
5572 | s_align (x) | |
5573 | int x; | |
5574 | { | |
670a50eb ILT |
5575 | register int temp; |
5576 | register long temp_fill; | |
5577 | long max_alignment = 15; | |
3d3c5039 | 5578 | |
670a50eb | 5579 | /* |
3d3c5039 ILT |
5580 | |
5581 | o Note that the assembler pulls down any immediately preceeding label | |
5582 | to the aligned address. | |
5583 | o It's not documented but auto alignment is reinstated by | |
5584 | a .align pseudo instruction. | |
5585 | o Note also that after auto alignment is turned off the mips assembler | |
5586 | issues an error on attempt to assemble an improperly aligned data item. | |
5587 | We don't. | |
5588 | ||
5589 | */ | |
5590 | ||
670a50eb ILT |
5591 | temp = get_absolute_expression (); |
5592 | if (temp > max_alignment) | |
5593 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
5594 | else if (temp < 0) | |
5595 | { | |
5596 | as_warn ("Alignment negative: 0 assumed."); | |
5597 | temp = 0; | |
5598 | } | |
5599 | if (*input_line_pointer == ',') | |
5600 | { | |
5601 | input_line_pointer++; | |
5602 | temp_fill = get_absolute_expression (); | |
5603 | } | |
5604 | else | |
5605 | temp_fill = 0; | |
5606 | if (temp) | |
5607 | { | |
5608 | auto_align = 1; | |
23dc1ae3 | 5609 | mips_align (temp, (int) temp_fill, insn_label); |
3d3c5039 | 5610 | } |
670a50eb ILT |
5611 | else |
5612 | { | |
5613 | auto_align = 0; | |
3d3c5039 ILT |
5614 | } |
5615 | ||
670a50eb | 5616 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
5617 | } |
5618 | ||
becfe05e ILT |
5619 | /* Handle .ascii and .asciiz. This just calls stringer and forgets |
5620 | that there was a previous instruction. */ | |
5621 | ||
5622 | static void | |
5623 | s_stringer (append_zero) | |
5624 | int append_zero; | |
5625 | { | |
5626 | mips_emit_delays (); | |
1849d646 | 5627 | insn_label = NULL; |
becfe05e ILT |
5628 | stringer (append_zero); |
5629 | } | |
5630 | ||
3d3c5039 ILT |
5631 | static void |
5632 | s_change_sec (sec) | |
5633 | int sec; | |
5634 | { | |
88225433 ILT |
5635 | #ifdef GPOPT |
5636 | segT seg; | |
5637 | #endif | |
becfe05e | 5638 | |
5b63f465 ILT |
5639 | /* When generating embedded PIC code, we only use the .text, .lit8, |
5640 | .sdata and .sbss sections. We change the .data and .rdata | |
5641 | pseudo-ops to use .sdata. */ | |
5642 | if (mips_pic == EMBEDDED_PIC | |
5643 | && (sec == 'd' || sec == 'r')) | |
5644 | sec = 's'; | |
5645 | ||
becfe05e | 5646 | mips_emit_delays (); |
670a50eb ILT |
5647 | switch (sec) |
5648 | { | |
3d3c5039 | 5649 | case 't': |
604633ae | 5650 | s_text (0); |
670a50eb | 5651 | break; |
3d3c5039 | 5652 | case 'd': |
604633ae | 5653 | s_data (0); |
670a50eb | 5654 | break; |
3d3c5039 | 5655 | case 'b': |
670a50eb | 5656 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
5657 | demand_empty_rest_of_line (); |
5658 | break; | |
88225433 ILT |
5659 | |
5660 | case 'r': | |
d2c71068 ILT |
5661 | seg = subseg_new (RDATA_SECTION_NAME, |
5662 | (subsegT) get_absolute_expression ()); | |
88225433 | 5663 | #ifdef OBJ_ELF |
88225433 ILT |
5664 | bfd_set_section_flags (stdoutput, seg, |
5665 | (SEC_ALLOC | |
5666 | | SEC_LOAD | |
5667 | | SEC_READONLY | |
5668 | | SEC_RELOC | |
5669 | | SEC_DATA)); | |
0dd2d296 | 5670 | bfd_set_section_alignment (stdoutput, seg, 4); |
d2c71068 | 5671 | #endif |
88225433 ILT |
5672 | demand_empty_rest_of_line (); |
5673 | break; | |
88225433 ILT |
5674 | |
5675 | case 's': | |
5676 | #ifdef GPOPT | |
5677 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
5678 | #ifdef OBJ_ELF | |
5679 | bfd_set_section_flags (stdoutput, seg, | |
5680 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
0dd2d296 | 5681 | bfd_set_section_alignment (stdoutput, seg, 4); |
88225433 ILT |
5682 | #endif |
5683 | demand_empty_rest_of_line (); | |
5684 | break; | |
5685 | #else /* ! defined (GPOPT) */ | |
670a50eb | 5686 | as_bad ("Global pointers not supported; recompile -G 0"); |
becfe05e | 5687 | demand_empty_rest_of_line (); |
670a50eb | 5688 | return; |
88225433 | 5689 | #endif /* ! defined (GPOPT) */ |
3d3c5039 | 5690 | } |
88225433 | 5691 | |
670a50eb | 5692 | auto_align = 1; |
3d3c5039 ILT |
5693 | } |
5694 | ||
5695 | static void | |
5696 | s_cons (log_size) | |
5697 | int log_size; | |
5698 | { | |
23dc1ae3 ILT |
5699 | symbolS *label; |
5700 | ||
5701 | label = insn_label; | |
becfe05e | 5702 | mips_emit_delays (); |
670a50eb | 5703 | if (log_size > 0 && auto_align) |
23dc1ae3 | 5704 | mips_align (log_size, 0, label); |
1849d646 | 5705 | insn_label = NULL; |
670a50eb | 5706 | cons (1 << log_size); |
3d3c5039 ILT |
5707 | } |
5708 | ||
5709 | static void | |
5710 | s_err (x) | |
5711 | int x; | |
5712 | { | |
670a50eb | 5713 | as_fatal ("Encountered `.err', aborting assembly"); |
3d3c5039 ILT |
5714 | } |
5715 | ||
5716 | static void | |
5717 | s_extern (x) | |
5718 | int x; | |
5719 | { | |
604633ae | 5720 | valueT size; |
670a50eb ILT |
5721 | symbolS *symbolP; |
5722 | ||
5723 | symbolP = get_symbol (); | |
5724 | if (*input_line_pointer == ',') | |
5725 | input_line_pointer++; | |
5ac34ac3 | 5726 | size = get_absolute_expression (); |
670a50eb ILT |
5727 | S_SET_EXTERNAL (symbolP); |
5728 | ||
0dd2d296 | 5729 | #ifdef ECOFF_DEBUGGING |
8ea7f4e8 | 5730 | symbolP->ecoff_extern_size = size; |
670a50eb | 5731 | #endif |
3d3c5039 ILT |
5732 | } |
5733 | ||
5734 | static void | |
becfe05e ILT |
5735 | s_float_cons (type) |
5736 | int type; | |
3d3c5039 | 5737 | { |
23dc1ae3 ILT |
5738 | symbolS *label; |
5739 | ||
5740 | label = insn_label; | |
5741 | ||
becfe05e | 5742 | mips_emit_delays (); |
670a50eb ILT |
5743 | |
5744 | if (auto_align) | |
becfe05e | 5745 | if (type == 'd') |
23dc1ae3 | 5746 | mips_align (3, 0, label); |
670a50eb | 5747 | else |
23dc1ae3 | 5748 | mips_align (2, 0, label); |
670a50eb | 5749 | |
1849d646 ILT |
5750 | insn_label = NULL; |
5751 | ||
becfe05e | 5752 | float_cons (type); |
3d3c5039 ILT |
5753 | } |
5754 | ||
c1444ec4 ILT |
5755 | /* Handle .globl. We need to override it because on Irix 5 you are |
5756 | permitted to say | |
5757 | .globl foo .text | |
5758 | where foo is an undefined symbol, to mean that foo should be | |
5759 | considered to be the address of a function. */ | |
5760 | ||
5761 | static void | |
5762 | s_mips_globl (x) | |
5763 | int x; | |
5764 | { | |
5765 | char *name; | |
5766 | int c; | |
5767 | symbolS *symbolP; | |
5768 | ||
5769 | name = input_line_pointer; | |
5770 | c = get_symbol_end (); | |
5771 | symbolP = symbol_find_or_make (name); | |
5772 | *input_line_pointer = c; | |
5773 | SKIP_WHITESPACE (); | |
5774 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5775 | { | |
5776 | char *secname; | |
5777 | asection *sec; | |
5778 | ||
5779 | secname = input_line_pointer; | |
5780 | c = get_symbol_end (); | |
5781 | sec = bfd_get_section_by_name (stdoutput, secname); | |
5782 | if (sec == NULL) | |
5783 | as_bad ("%s: no such section", secname); | |
5784 | *input_line_pointer = c; | |
5785 | ||
5786 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
5787 | symbolP->bsym->flags |= BSF_FUNCTION; | |
5788 | } | |
5789 | ||
5790 | S_SET_EXTERNAL (symbolP); | |
5791 | demand_empty_rest_of_line (); | |
5792 | } | |
5793 | ||
3d3c5039 ILT |
5794 | static void |
5795 | s_option (x) | |
5796 | int x; | |
5797 | { | |
dd3f1f76 ILT |
5798 | char *opt; |
5799 | char c; | |
5800 | ||
5801 | opt = input_line_pointer; | |
5802 | c = get_symbol_end (); | |
5803 | ||
dd3f1f76 | 5804 | if (*opt == 'O') |
9226253a ILT |
5805 | { |
5806 | /* FIXME: What does this mean? */ | |
5807 | } | |
dd3f1f76 | 5808 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 5809 | { |
d9aba805 | 5810 | int i; |
42562568 | 5811 | |
d9aba805 ILT |
5812 | i = atoi (opt + 3); |
5813 | if (i == 0) | |
5814 | mips_pic = NO_PIC; | |
5815 | else if (i == 2) | |
5816 | mips_pic = SVR4_PIC; | |
5817 | else | |
5818 | as_bad (".option pic%d not supported", i); | |
5819 | ||
0221ddf7 | 5820 | #ifdef GPOPT |
d9aba805 | 5821 | if (mips_pic == SVR4_PIC) |
42562568 ILT |
5822 | { |
5823 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 5824 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
5825 | g_switch_value = 0; |
5826 | bfd_set_gp_size (stdoutput, 0); | |
5827 | } | |
0221ddf7 | 5828 | #endif |
9226253a | 5829 | } |
dd3f1f76 ILT |
5830 | else |
5831 | as_warn ("Unrecognized option \"%s\"", opt); | |
5832 | ||
5833 | *input_line_pointer = c; | |
670a50eb | 5834 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
5835 | } |
5836 | ||
5837 | static void | |
5838 | s_mipsset (x) | |
5839 | int x; | |
5840 | { | |
670a50eb ILT |
5841 | char *name = input_line_pointer, ch; |
5842 | ||
5843 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
5844 | input_line_pointer++; | |
5845 | ch = *input_line_pointer; | |
5846 | *input_line_pointer = '\0'; | |
5847 | ||
5848 | if (strcmp (name, "reorder") == 0) | |
5849 | { | |
4e95866e ILT |
5850 | if (mips_noreorder) |
5851 | { | |
5852 | prev_insn_unreordered = 1; | |
5853 | prev_prev_insn_unreordered = 1; | |
5854 | } | |
670a50eb ILT |
5855 | mips_noreorder = 0; |
5856 | } | |
5857 | else if (strcmp (name, "noreorder") == 0) | |
5858 | { | |
becfe05e | 5859 | mips_emit_delays (); |
670a50eb | 5860 | mips_noreorder = 1; |
0dd2d296 | 5861 | mips_any_noreorder = 1; |
670a50eb ILT |
5862 | } |
5863 | else if (strcmp (name, "at") == 0) | |
5864 | { | |
5865 | mips_noat = 0; | |
5866 | } | |
5867 | else if (strcmp (name, "noat") == 0) | |
5868 | { | |
5869 | mips_noat = 1; | |
3d3c5039 | 5870 | } |
670a50eb ILT |
5871 | else if (strcmp (name, "macro") == 0) |
5872 | { | |
5873 | mips_warn_about_macros = 0; | |
5874 | } | |
5875 | else if (strcmp (name, "nomacro") == 0) | |
5876 | { | |
5877 | if (mips_noreorder == 0) | |
5878 | as_bad ("`noreorder' must be set before `nomacro'"); | |
5879 | mips_warn_about_macros = 1; | |
5880 | } | |
5881 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
5882 | { | |
5883 | mips_nomove = 0; | |
5884 | } | |
5885 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
5886 | { | |
5887 | mips_nomove = 1; | |
5888 | } | |
5889 | else if (strcmp (name, "bopt") == 0) | |
5890 | { | |
5891 | mips_nobopt = 0; | |
5892 | } | |
5893 | else if (strcmp (name, "nobopt") == 0) | |
5894 | { | |
5895 | mips_nobopt = 1; | |
5896 | } | |
1051c97f ILT |
5897 | else if (strncmp (name, "mips", 4) == 0) |
5898 | { | |
5899 | int isa; | |
5900 | ||
5901 | /* Permit the user to change the ISA on the fly. Needless to | |
5902 | say, misuse can cause serious problems. */ | |
5903 | isa = atoi (name + 4); | |
5904 | if (isa == 0) | |
5905 | mips_isa = file_mips_isa; | |
5906 | else if (isa < 1 || isa > 3) | |
5907 | as_bad ("unknown ISA level"); | |
5908 | else | |
5909 | mips_isa = isa; | |
5910 | } | |
670a50eb ILT |
5911 | else |
5912 | { | |
5913 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
5914 | } | |
5915 | *input_line_pointer = ch; | |
5916 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
5917 | } |
5918 | ||
becfe05e ILT |
5919 | /* The same as the usual .space directive, except that we have to |
5920 | forget about any previous instruction. */ | |
5921 | ||
5922 | static void | |
5923 | s_mips_space (param) | |
5924 | int param; | |
5925 | { | |
5926 | mips_emit_delays (); | |
1849d646 | 5927 | insn_label = NULL; |
becfe05e ILT |
5928 | s_space (param); |
5929 | } | |
5930 | ||
9226253a ILT |
5931 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
5932 | .option pic2. It means to generate SVR4 PIC calls. */ | |
5933 | ||
5934 | static void | |
5935 | s_abicalls (ignore) | |
5936 | int ignore; | |
5937 | { | |
d9aba805 | 5938 | mips_pic = SVR4_PIC; |
0221ddf7 | 5939 | #ifdef GPOPT |
d9aba805 ILT |
5940 | if (g_switch_seen && g_switch_value != 0) |
5941 | as_warn ("-G may not be used with SVR4 PIC code"); | |
5942 | g_switch_value = 0; | |
0221ddf7 | 5943 | #endif |
d9aba805 | 5944 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
5945 | demand_empty_rest_of_line (); |
5946 | } | |
5947 | ||
5948 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
5949 | PIC code. It sets the $gp register for the function based on the | |
5950 | function address, which is in the register named in the argument. | |
5951 | This uses a relocation against _gp_disp, which is handled specially | |
5952 | by the linker. The result is: | |
5953 | lui $gp,%hi(_gp_disp) | |
5954 | addiu $gp,$gp,%lo(_gp_disp) | |
5955 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 5956 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
5957 | |
5958 | static void | |
5959 | s_cpload (ignore) | |
5960 | int ignore; | |
5961 | { | |
5962 | expressionS ex; | |
5963 | int icnt = 0; | |
5964 | ||
d9aba805 ILT |
5965 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
5966 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
5967 | { |
5968 | s_ignore (0); | |
5969 | return; | |
5970 | } | |
5971 | ||
5972 | /* .cpload should be a in .set noreorder section. */ | |
5973 | if (mips_noreorder == 0) | |
5974 | as_warn (".cpload not in noreorder section"); | |
5975 | ||
9226253a ILT |
5976 | ex.X_op = O_symbol; |
5977 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
5978 | ex.X_op_symbol = NULL; | |
5979 | ex.X_add_number = 0; | |
5980 | ||
0dd2d296 ILT |
5981 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
5982 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
5983 | (int) BFD_RELOC_LO16); |
5984 | ||
0dd2d296 ILT |
5985 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
5986 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
5987 | |
5988 | demand_empty_rest_of_line (); | |
5989 | } | |
5990 | ||
5991 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
5992 | offset from $sp. The offset is remembered, and after making a PIC | |
5993 | call $gp is restored from that location. */ | |
5994 | ||
5995 | static void | |
5996 | s_cprestore (ignore) | |
5997 | int ignore; | |
5998 | { | |
5999 | expressionS ex; | |
6000 | int icnt = 0; | |
6001 | ||
d9aba805 ILT |
6002 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
6003 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
6004 | { |
6005 | s_ignore (0); | |
6006 | return; | |
6007 | } | |
6008 | ||
9226253a ILT |
6009 | mips_cprestore_offset = get_absolute_expression (); |
6010 | ||
6011 | ex.X_op = O_constant; | |
6012 | ex.X_add_symbol = NULL; | |
6013 | ex.X_op_symbol = NULL; | |
6014 | ex.X_add_number = mips_cprestore_offset; | |
6015 | ||
0dd2d296 | 6016 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
6017 | mips_isa < 3 ? "sw" : "sd", |
6018 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
6019 | ||
6020 | demand_empty_rest_of_line (); | |
6021 | } | |
6022 | ||
0dd2d296 ILT |
6023 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
6024 | code. It generates a 32 bit GP relative reloc. */ | |
6025 | ||
6026 | static void | |
6027 | s_gpword (ignore) | |
6028 | int ignore; | |
6029 | { | |
23dc1ae3 | 6030 | symbolS *label; |
0dd2d296 ILT |
6031 | expressionS ex; |
6032 | char *p; | |
6033 | ||
6034 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 6035 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
6036 | { |
6037 | s_cons (2); | |
6038 | return; | |
6039 | } | |
6040 | ||
23dc1ae3 | 6041 | label = insn_label; |
0dd2d296 ILT |
6042 | mips_emit_delays (); |
6043 | if (auto_align) | |
23dc1ae3 | 6044 | mips_align (2, 0, label); |
0dd2d296 ILT |
6045 | insn_label = NULL; |
6046 | ||
6047 | expression (&ex); | |
6048 | ||
6049 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
6050 | { | |
6051 | as_bad ("Unsupported use of .gpword"); | |
6052 | ignore_rest_of_line (); | |
6053 | } | |
6054 | ||
6055 | p = frag_more (4); | |
6056 | md_number_to_chars (p, (valueT) 0, 4); | |
6057 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
6058 | BFD_RELOC_MIPS_GPREL32); | |
6059 | ||
6060 | demand_empty_rest_of_line (); | |
6061 | } | |
6062 | ||
6063 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
6064 | tables in SVR4 PIC code. */ | |
6065 | ||
6066 | static void | |
6067 | s_cpadd (ignore) | |
6068 | int ignore; | |
6069 | { | |
6070 | int icnt = 0; | |
6071 | int reg; | |
6072 | ||
6073 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 6074 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
6075 | { |
6076 | s_ignore (0); | |
6077 | return; | |
6078 | } | |
6079 | ||
6080 | /* Add $gp to the register named as an argument. */ | |
6081 | reg = tc_get_register (0); | |
6082 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6083 | mips_isa < 3 ? "addu" : "daddu", | |
6084 | "d,v,t", reg, reg, GP); | |
6085 | ||
6086 | demand_empty_rest_of_line (); | |
6087 | } | |
6088 | ||
9226253a | 6089 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
6090 | to parse .frame. The argument is non-zero if this is the frame |
6091 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 6092 | |
3d3c5039 | 6093 | int |
0dd2d296 ILT |
6094 | tc_get_register (frame) |
6095 | int frame; | |
3d3c5039 ILT |
6096 | { |
6097 | int reg; | |
6098 | ||
6099 | SKIP_WHITESPACE (); | |
6100 | if (*input_line_pointer++ != '$') | |
6101 | { | |
6102 | as_warn ("expected `$'"); | |
0dd2d296 | 6103 | reg = 0; |
3d3c5039 | 6104 | } |
0dd2d296 | 6105 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
6106 | { |
6107 | reg = get_absolute_expression (); | |
6108 | if (reg < 0 || reg >= 32) | |
6109 | { | |
6110 | as_warn ("Bad register number"); | |
6111 | reg = 0; | |
6112 | } | |
6113 | } | |
6114 | else | |
6115 | { | |
6116 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 6117 | reg = FP; |
3d3c5039 | 6118 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 6119 | reg = SP; |
3d3c5039 | 6120 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 6121 | reg = GP; |
3d3c5039 | 6122 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 6123 | reg = AT; |
3d3c5039 ILT |
6124 | else |
6125 | { | |
6126 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 6127 | reg = 0; |
3d3c5039 ILT |
6128 | } |
6129 | input_line_pointer += 2; | |
6130 | } | |
0dd2d296 ILT |
6131 | if (frame) |
6132 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
6133 | return reg; |
6134 | } | |
6135 | ||
0dd2d296 ILT |
6136 | valueT |
6137 | md_section_align (seg, addr) | |
6138 | asection *seg; | |
6139 | valueT addr; | |
6140 | { | |
6141 | int align = bfd_get_section_alignment (stdoutput, seg); | |
6142 | ||
6143 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
6144 | } | |
6145 | ||
6146 | /* Estimate the size of a frag before relaxing. We are not really | |
6147 | relaxing here, and the final size is encoded in the subtype | |
6148 | information. */ | |
6149 | ||
6150 | /*ARGSUSED*/ | |
6151 | int | |
6152 | md_estimate_size_before_relax (fragp, segtype) | |
6153 | fragS *fragp; | |
6154 | asection *segtype; | |
6155 | { | |
6156 | int change; | |
6157 | ||
d9aba805 | 6158 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
6159 | { |
6160 | #ifdef GPOPT | |
6161 | const char *symname; | |
6162 | ||
6163 | /* Find out whether this symbol can be referenced off the GP | |
6164 | register. It can be if it is smaller than the -G size or if | |
6165 | it is in the .sdata or .sbss section. Certain symbols can | |
6166 | not be referenced off the GP, although it appears as though | |
6167 | they can. */ | |
6168 | symname = S_GET_NAME (fragp->fr_symbol); | |
6169 | if (symname != (const char *) NULL | |
6170 | && (strcmp (symname, "eprol") == 0 | |
6171 | || strcmp (symname, "etext") == 0 | |
6172 | || strcmp (symname, "_gp") == 0 | |
6173 | || strcmp (symname, "edata") == 0 | |
6174 | || strcmp (symname, "_fbss") == 0 | |
6175 | || strcmp (symname, "_fdata") == 0 | |
6176 | || strcmp (symname, "_ftext") == 0 | |
6177 | || strcmp (symname, "end") == 0 | |
6178 | || strcmp (symname, "_gp_disp") == 0)) | |
6179 | change = 1; | |
6180 | else if (! S_IS_DEFINED (fragp->fr_symbol) | |
8ea7f4e8 ILT |
6181 | && ((fragp->fr_symbol->ecoff_extern_size != 0 |
6182 | && fragp->fr_symbol->ecoff_extern_size <= g_switch_value) | |
6183 | || (S_GET_VALUE (fragp->fr_symbol) != 0 | |
6184 | && S_GET_VALUE (fragp->fr_symbol) <= g_switch_value))) | |
0dd2d296 ILT |
6185 | change = 0; |
6186 | else | |
6187 | { | |
6188 | const char *segname; | |
6189 | ||
6190 | segname = segment_name (S_GET_SEGMENT (fragp->fr_symbol)); | |
6191 | assert (strcmp (segname, ".lit8") != 0 | |
6192 | && strcmp (segname, ".lit4") != 0); | |
6193 | change = (strcmp (segname, ".sdata") != 0 | |
6194 | && strcmp (segname, ".sbss") != 0); | |
6195 | } | |
6196 | #else /* ! defined (GPOPT) */ | |
6197 | /* We are not optimizing for the GP register. */ | |
6198 | change = 1; | |
6199 | #endif /* ! defined (GPOPT) */ | |
6200 | } | |
d9aba805 | 6201 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
6202 | { |
6203 | asection *symsec = fragp->fr_symbol->bsym->section; | |
6204 | ||
6205 | /* This must duplicate the test in adjust_reloc_syms. */ | |
6206 | change = (symsec != &bfd_und_section | |
6207 | && symsec != &bfd_abs_section | |
6208 | && ! bfd_is_com_section (symsec)); | |
6209 | } | |
d9aba805 ILT |
6210 | else |
6211 | abort (); | |
0dd2d296 ILT |
6212 | |
6213 | if (change) | |
6214 | { | |
6215 | /* Record the offset to the first reloc in the fr_opcode field. | |
6216 | This lets md_convert_frag and tc_gen_reloc know that the code | |
6217 | must be expanded. */ | |
6218 | fragp->fr_opcode = (fragp->fr_literal | |
6219 | + fragp->fr_fix | |
6220 | - RELAX_OLD (fragp->fr_subtype) | |
6221 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
6222 | /* FIXME: This really needs as_warn_where. */ | |
6223 | if (RELAX_WARN (fragp->fr_subtype)) | |
6224 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
6225 | } | |
6226 | ||
6227 | if (! change) | |
6228 | return 0; | |
6229 | else | |
6230 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
6231 | } | |
6232 | ||
6233 | /* Translate internal representation of relocation info to BFD target | |
6234 | format. */ | |
6235 | ||
6236 | arelent ** | |
3d3c5039 ILT |
6237 | tc_gen_reloc (section, fixp) |
6238 | asection *section; | |
6239 | fixS *fixp; | |
6240 | { | |
0dd2d296 | 6241 | static arelent *retval[4]; |
3d3c5039 ILT |
6242 | arelent *reloc; |
6243 | ||
0dd2d296 ILT |
6244 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
6245 | retval[1] = NULL; | |
3d3c5039 ILT |
6246 | |
6247 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
6248 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
6249 | |
6250 | if (mips_pic == EMBEDDED_PIC | |
6251 | && SWITCH_TABLE (fixp)) | |
6252 | { | |
6253 | /* For a switch table entry we use a special reloc. The addend | |
6254 | is actually the difference between the reloc address and the | |
6255 | subtrahend. */ | |
6256 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
6257 | #ifndef OBJ_ECOFF | |
ecd4ca1c | 6258 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); |
1c803e52 ILT |
6259 | #endif |
6260 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
6261 | } | |
ecd4ca1c ILT |
6262 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
6263 | { | |
6264 | /* We use a special addend for an internal RELLO reloc. */ | |
6265 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
6266 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
6267 | else | |
6268 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
6269 | } | |
6270 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
6271 | { | |
6272 | assert (fixp->fx_next != NULL | |
6273 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
6274 | /* We use a special addend for an internal RELHI reloc. The | |
6275 | reloc is relative to the RELLO; adjust the addend | |
6276 | accordingly. */ | |
6277 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
6278 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
6279 | + fixp->fx_next->fx_where | |
6280 | - S_GET_VALUE (fixp->fx_subsy)); | |
6281 | else | |
6282 | reloc->addend = (fixp->fx_addnumber | |
6283 | + fixp->fx_next->fx_frag->fr_address | |
6284 | + fixp->fx_next->fx_where); | |
6285 | } | |
1c803e52 | 6286 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
6287 | reloc->addend = fixp->fx_addnumber; |
6288 | else | |
5b63f465 | 6289 | { |
d9aba805 | 6290 | #ifndef OBJ_AOUT |
5b63f465 ILT |
6291 | /* A gruesome hack which is a result of the gruesome gas reloc |
6292 | handling. */ | |
6293 | reloc->addend = reloc->address; | |
3d3c5039 | 6294 | #else |
5b63f465 | 6295 | reloc->addend = -reloc->address; |
3d3c5039 | 6296 | #endif |
5b63f465 | 6297 | } |
0dd2d296 ILT |
6298 | |
6299 | /* If this is a variant frag, we may need to adjust the existing | |
6300 | reloc and generate a new one. */ | |
6301 | if (fixp->fx_frag->fr_opcode != NULL | |
6302 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
6303 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
6304 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16)) | |
6305 | { | |
6306 | arelent *reloc2; | |
6307 | ||
6308 | /* If this is not the last reloc in this frag, then we have two | |
6309 | GPREL relocs, both of which are being replaced. Let the | |
6310 | second one handle all of them. */ | |
6311 | if (fixp->fx_next != NULL | |
6312 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
6313 | { | |
6314 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
6315 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
6316 | retval[0] = NULL; | |
6317 | return retval; | |
6318 | } | |
6319 | ||
6320 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
6321 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
6322 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
6323 | retval[2] = NULL; | |
6324 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
6325 | reloc2->address = (reloc->address | |
6326 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
6327 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
6328 | reloc2->addend = fixp->fx_addnumber; | |
6329 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
6330 | assert (reloc2->howto != NULL); | |
6331 | ||
6332 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
6333 | { | |
6334 | arelent *reloc3; | |
6335 | ||
6336 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
6337 | retval[3] = NULL; | |
6338 | *reloc3 = *reloc2; | |
6339 | reloc3->address += 4; | |
6340 | } | |
6341 | ||
d9aba805 | 6342 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
6343 | { |
6344 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
6345 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
6346 | } | |
d9aba805 | 6347 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
6348 | { |
6349 | if (fixp->fx_r_type != BFD_RELOC_MIPS_GOT16) | |
6350 | { | |
6351 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_CALL16); | |
6352 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
6353 | } | |
6354 | } | |
d9aba805 ILT |
6355 | else |
6356 | abort (); | |
0dd2d296 ILT |
6357 | } |
6358 | ||
d9aba805 ILT |
6359 | /* To support a PC relative reloc when generating embedded PIC code |
6360 | for ECOFF, we use a Cygnus extension. We check for that here to | |
6361 | make sure that we don't let such a reloc escape normally. */ | |
6362 | #ifdef OBJ_ECOFF | |
6363 | if (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
6364 | && mips_pic != EMBEDDED_PIC) | |
6365 | reloc->howto = NULL; | |
6366 | else | |
6367 | #endif | |
6368 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
0dd2d296 | 6369 | |
52aa70b5 JW |
6370 | if (reloc->howto == NULL) |
6371 | { | |
6372 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
6373 | "Can not represent relocation in this object file format"); | |
0dd2d296 | 6374 | retval[0] = NULL; |
52aa70b5 | 6375 | } |
3d3c5039 | 6376 | |
0dd2d296 | 6377 | return retval; |
3d3c5039 ILT |
6378 | } |
6379 | ||
0dd2d296 ILT |
6380 | /* Convert a machine dependent frag. */ |
6381 | ||
6382 | void | |
6383 | md_convert_frag (abfd, asec, fragp) | |
6384 | bfd *abfd; | |
6385 | segT asec; | |
6386 | fragS *fragp; | |
3d3c5039 | 6387 | { |
0dd2d296 ILT |
6388 | int old, new; |
6389 | char *fixptr; | |
3d3c5039 | 6390 | |
0dd2d296 ILT |
6391 | if (fragp->fr_opcode == NULL) |
6392 | return; | |
3d3c5039 | 6393 | |
0dd2d296 ILT |
6394 | old = RELAX_OLD (fragp->fr_subtype); |
6395 | new = RELAX_NEW (fragp->fr_subtype); | |
6396 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
6397 | ||
6398 | if (new > 0) | |
6399 | memcpy (fixptr - old, fixptr, new); | |
6400 | ||
6401 | fragp->fr_fix += new - old; | |
6402 | } | |
becfe05e ILT |
6403 | |
6404 | /* This function is called whenever a label is defined. It is used | |
6405 | when handling branch delays; if a branch has a label, we assume we | |
6406 | can not move it. */ | |
6407 | ||
6408 | void | |
6409 | mips_define_label (sym) | |
6410 | symbolS *sym; | |
6411 | { | |
6412 | insn_label = sym; | |
6413 | } | |
3d3c5039 | 6414 | \f |
f2a663d3 ILT |
6415 | #ifdef OBJ_ELF |
6416 | ||
0dd2d296 | 6417 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
6418 | |
6419 | void | |
6420 | mips_elf_final_processing () | |
6421 | { | |
6422 | Elf32_RegInfo s; | |
6423 | ||
0dd2d296 | 6424 | /* Write out the .reginfo section. */ |
f2a663d3 ILT |
6425 | s.ri_gprmask = mips_gprmask; |
6426 | s.ri_cprmask[0] = mips_cprmask[0]; | |
6427 | s.ri_cprmask[1] = mips_cprmask[1]; | |
6428 | s.ri_cprmask[2] = mips_cprmask[2]; | |
6429 | s.ri_cprmask[3] = mips_cprmask[3]; | |
6430 | /* The gp_value field is set by the MIPS ELF backend. */ | |
6431 | ||
6432 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
6433 | ((Elf32_External_RegInfo *) | |
6434 | mips_regmask_frag)); | |
0dd2d296 ILT |
6435 | |
6436 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
6437 | sort of BFD interface for this. */ | |
6438 | if (mips_any_noreorder) | |
6439 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 6440 | if (mips_pic != NO_PIC) |
0dd2d296 | 6441 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
6442 | } |
6443 | ||
6444 | #endif /* OBJ_ELF */ | |
6445 | \f | |
0dd2d296 | 6446 | #ifndef ECOFF_DEBUGGING |
3d3c5039 ILT |
6447 | |
6448 | /* These functions should really be defined by the object file format, | |
6449 | since they are related to debugging information. However, this | |
6450 | code has to work for the a.out format, which does not define them, | |
6451 | so we provide simple versions here. These don't actually generate | |
6452 | any debugging information, but they do simple checking and someday | |
6453 | somebody may make them useful. */ | |
6454 | ||
670a50eb ILT |
6455 | typedef struct loc |
6456 | { | |
6457 | struct loc *loc_next; | |
6458 | unsigned long loc_fileno; | |
6459 | unsigned long loc_lineno; | |
6460 | unsigned long loc_offset; | |
6461 | unsigned short loc_delta; | |
6462 | unsigned short loc_count; | |
3d3c5039 | 6463 | #if 0 |
670a50eb | 6464 | fragS *loc_frag; |
3d3c5039 | 6465 | #endif |
670a50eb ILT |
6466 | } |
6467 | locS; | |
3d3c5039 | 6468 | |
670a50eb ILT |
6469 | typedef struct proc |
6470 | { | |
3d3c5039 ILT |
6471 | struct proc *proc_next; |
6472 | struct symbol *proc_isym; | |
6473 | struct symbol *proc_end; | |
6474 | unsigned long proc_reg_mask; | |
6475 | unsigned long proc_reg_offset; | |
6476 | unsigned long proc_fpreg_mask; | |
6477 | unsigned long proc_fpreg_offset; | |
6478 | unsigned long proc_frameoffset; | |
6479 | unsigned long proc_framereg; | |
6480 | unsigned long proc_pcreg; | |
6481 | locS *proc_iline; | |
6482 | struct file *proc_file; | |
6483 | int proc_index; | |
670a50eb ILT |
6484 | } |
6485 | procS; | |
3d3c5039 | 6486 | |
670a50eb ILT |
6487 | typedef struct file |
6488 | { | |
3d3c5039 ILT |
6489 | struct file *file_next; |
6490 | unsigned long file_fileno; | |
6491 | struct symbol *file_symbol; | |
6492 | struct symbol *file_end; | |
6493 | struct proc *file_proc; | |
6494 | int file_numprocs; | |
670a50eb ILT |
6495 | } |
6496 | fileS; | |
3d3c5039 ILT |
6497 | |
6498 | static struct obstack proc_frags; | |
6499 | static procS *proc_lastP; | |
6500 | static procS *proc_rootP; | |
6501 | static int numprocs; | |
6502 | ||
6503 | static void | |
6504 | md_obj_begin () | |
6505 | { | |
670a50eb | 6506 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
6507 | } |
6508 | ||
6509 | static void | |
6510 | md_obj_end () | |
6511 | { | |
6512 | /* check for premature end, nesting errors, etc */ | |
6513 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 6514 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
6515 | } |
6516 | ||
6517 | extern char hex_value[]; | |
6518 | ||
6519 | static long | |
6520 | get_number () | |
6521 | { | |
670a50eb ILT |
6522 | int negative = 0; |
6523 | long val = 0; | |
3d3c5039 | 6524 | |
670a50eb ILT |
6525 | if (*input_line_pointer == '-') |
6526 | { | |
6527 | ++input_line_pointer; | |
6528 | negative = 1; | |
3d3c5039 | 6529 | } |
670a50eb ILT |
6530 | if (!isdigit (*input_line_pointer)) |
6531 | as_bad ("Expected simple number."); | |
6532 | if (input_line_pointer[0] == '0') | |
6533 | { | |
6534 | if (input_line_pointer[1] == 'x') | |
6535 | { | |
6536 | input_line_pointer += 2; | |
6537 | while (isxdigit (*input_line_pointer)) | |
6538 | { | |
6539 | val <<= 4; | |
6540 | val |= hex_value[(int) *input_line_pointer++]; | |
3d3c5039 | 6541 | } |
670a50eb ILT |
6542 | return negative ? -val : val; |
6543 | } | |
6544 | else | |
6545 | { | |
6546 | ++input_line_pointer; | |
6547 | while (isdigit (*input_line_pointer)) | |
6548 | { | |
6549 | val <<= 3; | |
6550 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 6551 | } |
670a50eb | 6552 | return negative ? -val : val; |
3d3c5039 ILT |
6553 | } |
6554 | } | |
670a50eb ILT |
6555 | if (!isdigit (*input_line_pointer)) |
6556 | { | |
6557 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
6558 | *input_line_pointer, *input_line_pointer); | |
6559 | as_warn ("Invalid number"); | |
6560 | return -1; | |
3d3c5039 | 6561 | } |
670a50eb ILT |
6562 | while (isdigit (*input_line_pointer)) |
6563 | { | |
6564 | val *= 10; | |
6565 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 6566 | } |
670a50eb | 6567 | return negative ? -val : val; |
3d3c5039 ILT |
6568 | } |
6569 | ||
6570 | /* The .file directive; just like the usual .file directive, but there | |
6571 | is an initial number which is the ECOFF file index. */ | |
6572 | ||
6573 | static void | |
6574 | s_file (x) | |
6575 | int x; | |
6576 | { | |
670a50eb | 6577 | int line; |
3d3c5039 | 6578 | |
670a50eb | 6579 | line = get_number (); |
9a7d824a | 6580 | s_app_file (0); |
3d3c5039 ILT |
6581 | } |
6582 | ||
6583 | ||
6584 | /* The .end directive. */ | |
6585 | ||
6586 | static void | |
6587 | s_mipsend (x) | |
6588 | int x; | |
6589 | { | |
670a50eb ILT |
6590 | symbolS *p; |
6591 | ||
6592 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
6593 | { | |
6594 | p = get_symbol (); | |
6595 | demand_empty_rest_of_line (); | |
6596 | } | |
6597 | else | |
6598 | p = NULL; | |
6599 | if (now_seg != text_section) | |
6600 | as_warn (".end not in text section"); | |
6601 | if (!proc_lastP) | |
6602 | { | |
6603 | as_warn (".end and no .ent seen yet."); | |
6604 | return; | |
3d3c5039 ILT |
6605 | } |
6606 | ||
670a50eb ILT |
6607 | if (p != NULL) |
6608 | { | |
6609 | assert (S_GET_NAME (p)); | |
6610 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
6611 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
6612 | } |
6613 | ||
670a50eb | 6614 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
6615 | } |
6616 | ||
6617 | /* The .aent and .ent directives. */ | |
6618 | ||
6619 | static void | |
6620 | s_ent (aent) | |
6621 | int aent; | |
6622 | { | |
670a50eb ILT |
6623 | int number = 0; |
6624 | procS *procP; | |
6625 | symbolS *symbolP; | |
6626 | ||
6627 | symbolP = get_symbol (); | |
6628 | if (*input_line_pointer == ',') | |
6629 | input_line_pointer++; | |
dd3f1f76 | 6630 | SKIP_WHITESPACE (); |
670a50eb ILT |
6631 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
6632 | number = get_number (); | |
6633 | if (now_seg != text_section) | |
6634 | as_warn (".ent or .aent not in text section."); | |
6635 | ||
6636 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
6637 | as_warn ("missing `.end'"); | |
6638 | ||
6639 | if (!aent) | |
6640 | { | |
6641 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
6642 | procP->proc_isym = symbolP; | |
6643 | procP->proc_reg_mask = 0; | |
6644 | procP->proc_reg_offset = 0; | |
6645 | procP->proc_fpreg_mask = 0; | |
6646 | procP->proc_fpreg_offset = 0; | |
6647 | procP->proc_frameoffset = 0; | |
6648 | procP->proc_framereg = 0; | |
6649 | procP->proc_pcreg = 0; | |
6650 | procP->proc_end = NULL; | |
6651 | procP->proc_next = NULL; | |
6652 | if (proc_lastP) | |
6653 | proc_lastP->proc_next = procP; | |
6654 | else | |
6655 | proc_rootP = procP; | |
6656 | proc_lastP = procP; | |
6657 | numprocs++; | |
3d3c5039 | 6658 | } |
670a50eb | 6659 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
6660 | } |
6661 | ||
6662 | /* The .frame directive. */ | |
6663 | ||
88225433 | 6664 | #if 0 |
3d3c5039 ILT |
6665 | static void |
6666 | s_frame (x) | |
670a50eb | 6667 | int x; |
3d3c5039 | 6668 | { |
670a50eb ILT |
6669 | char str[100]; |
6670 | symbolS *symP; | |
6671 | int frame_reg; | |
6672 | int frame_off; | |
6673 | int pcreg; | |
6674 | ||
0dd2d296 | 6675 | frame_reg = tc_get_register (1); |
670a50eb ILT |
6676 | if (*input_line_pointer == ',') |
6677 | input_line_pointer++; | |
5ac34ac3 | 6678 | frame_off = get_absolute_expression (); |
670a50eb ILT |
6679 | if (*input_line_pointer == ',') |
6680 | input_line_pointer++; | |
0dd2d296 | 6681 | pcreg = tc_get_register (0); |
670a50eb ILT |
6682 | |
6683 | /* bob third eye */ | |
6684 | assert (proc_rootP); | |
6685 | proc_rootP->proc_framereg = frame_reg; | |
6686 | proc_rootP->proc_frameoffset = frame_off; | |
6687 | proc_rootP->proc_pcreg = pcreg; | |
6688 | /* bob macho .frame */ | |
6689 | ||
6690 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 6691 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
6692 | { |
6693 | if (!proc_lastP) | |
6694 | as_warn ("No .ent for .frame to use."); | |
6695 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
6696 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
6697 | S_SET_TYPE (symP, N_RMASK); | |
6698 | S_SET_OTHER (symP, 0); | |
6699 | S_SET_DESC (symP, 0); | |
6700 | symP->sy_forward = proc_lastP->proc_isym; | |
6701 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 6702 | } |
670a50eb | 6703 | demand_empty_rest_of_line (); |
3d3c5039 | 6704 | } |
88225433 | 6705 | #endif |
3d3c5039 ILT |
6706 | |
6707 | /* The .fmask and .mask directives. */ | |
6708 | ||
88225433 | 6709 | #if 0 |
3d3c5039 ILT |
6710 | static void |
6711 | s_mask (reg_type) | |
6712 | char reg_type; | |
6713 | { | |
670a50eb ILT |
6714 | char str[100], *strP; |
6715 | symbolS *symP; | |
6716 | int i; | |
6717 | unsigned int mask; | |
6718 | int off; | |
6719 | ||
6720 | mask = get_number (); | |
6721 | if (*input_line_pointer == ',') | |
6722 | input_line_pointer++; | |
6723 | off = get_absolute_expression (); | |
6724 | ||
6725 | /* bob only for coff */ | |
6726 | assert (proc_rootP); | |
6727 | if (reg_type == 'F') | |
6728 | { | |
6729 | proc_rootP->proc_fpreg_mask = mask; | |
6730 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 6731 | } |
670a50eb ILT |
6732 | else |
6733 | { | |
6734 | proc_rootP->proc_reg_mask = mask; | |
6735 | proc_rootP->proc_reg_offset = off; | |
6736 | } | |
6737 | ||
6738 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 6739 | |
670a50eb ILT |
6740 | /* We don't have to write out a mask stab if no saved regs. */ |
6741 | if (!(mask == 0)) | |
6742 | { | |
6743 | if (!proc_lastP) | |
6744 | as_warn ("No .ent for .mask to use."); | |
6745 | strP = str; | |
6746 | for (i = 0; i < 32; i++) | |
6747 | { | |
6748 | if (mask % 2) | |
6749 | { | |
6750 | sprintf (strP, "%c%d,", reg_type, i); | |
6751 | strP += strlen (strP); | |
6752 | } | |
3d3c5039 | 6753 | mask /= 2; |
670a50eb ILT |
6754 | } |
6755 | sprintf (strP, ";%d,", off); | |
6756 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
6757 | S_SET_TYPE (symP, N_RMASK); | |
6758 | S_SET_OTHER (symP, 0); | |
6759 | S_SET_DESC (symP, 0); | |
6760 | symP->sy_forward = proc_lastP->proc_isym; | |
6761 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 6762 | } |
3d3c5039 | 6763 | } |
88225433 | 6764 | #endif |
3d3c5039 ILT |
6765 | |
6766 | /* The .loc directive. */ | |
6767 | ||
88225433 | 6768 | #if 0 |
3d3c5039 ILT |
6769 | static void |
6770 | s_loc (x) | |
6771 | int x; | |
6772 | { | |
670a50eb ILT |
6773 | symbolS *symbolP; |
6774 | int lineno; | |
6775 | int addroff; | |
3d3c5039 | 6776 | |
670a50eb | 6777 | assert (now_seg == text_section); |
3d3c5039 | 6778 | |
670a50eb ILT |
6779 | lineno = get_number (); |
6780 | addroff = obstack_next_free (&frags) - frag_now->fr_literal; | |
3d3c5039 | 6781 | |
670a50eb ILT |
6782 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
6783 | S_SET_TYPE (symbolP, N_SLINE); | |
6784 | S_SET_OTHER (symbolP, 0); | |
6785 | S_SET_DESC (symbolP, lineno); | |
6786 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 6787 | } |
88225433 | 6788 | #endif |
3d3c5039 | 6789 | |
0dd2d296 | 6790 | #endif /* ! defined (ECOFF_DEBUGGING) */ |