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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
3d3c5039 | 39 | |
739708fa KR |
40 | #ifdef OBJ_MAYBE_ELF |
41 | /* Clean up namespace so we can include obj-elf.h too. */ | |
42 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
43 | #undef OBJ_PROCESS_STAB | |
44 | #undef OUTPUT_FLAVOR | |
45 | #undef S_GET_ALIGN | |
46 | #undef S_GET_SIZE | |
47 | #undef S_SET_ALIGN | |
48 | #undef S_SET_SIZE | |
49 | #undef TARGET_SYMBOL_FIELDS | |
50 | #undef obj_frob_file | |
cc5703cd | 51 | #undef obj_frob_file_after_relocs |
739708fa KR |
52 | #undef obj_frob_symbol |
53 | #undef obj_pop_insert | |
54 | #undef obj_sec_sym_ok_for_reloc | |
55 | ||
56 | #include "obj-elf.h" | |
57 | /* Fix any of them that we actually care about. */ | |
58 | #undef OUTPUT_FLAVOR | |
59 | #define OUTPUT_FLAVOR mips_output_flavor() | |
60 | #endif | |
61 | ||
62 | #if defined (OBJ_ELF) | |
f2a663d3 | 63 | #include "elf/mips.h" |
1dc1e798 | 64 | #endif |
f2a663d3 | 65 | |
739708fa | 66 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 67 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
68 | #define ECOFF_DEBUGGING 0 |
69 | #endif | |
70 | ||
22ba90ce ILT |
71 | #include "ecoff.h" |
72 | ||
a8aed9dd | 73 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 74 | static char *mips_regmask_frag; |
a8aed9dd | 75 | #endif |
f2a663d3 | 76 | |
3d3c5039 | 77 | #define AT 1 |
cc5703cd | 78 | #define TREG 24 |
9226253a | 79 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
80 | #define KT0 26 |
81 | #define KT1 27 | |
670a50eb | 82 | #define GP 28 |
9226253a ILT |
83 | #define SP 29 |
84 | #define FP 30 | |
3d3c5039 ILT |
85 | #define RA 31 |
86 | ||
cc5703cd ILT |
87 | #define ILLEGAL_REG (32) |
88 | ||
1dc1e798 | 89 | extern int target_big_endian; |
88225433 | 90 | |
7f9880e5 ILT |
91 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
92 | 32 bit ABI. This has no meaning for ECOFF. */ | |
93 | static int mips_64; | |
94 | ||
04cb3372 | 95 | /* The default target format to use. */ |
1dc1e798 KR |
96 | const char * |
97 | mips_target_format () | |
98 | { | |
99 | switch (OUTPUT_FLAVOR) | |
100 | { | |
101 | case bfd_target_aout_flavour: | |
102 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
103 | case bfd_target_ecoff_flavour: | |
104 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
105 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
106 | return (target_big_endian |
107 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
108 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
109 | default: |
110 | abort (); | |
111 | } | |
112 | } | |
04cb3372 | 113 | |
d2c71068 | 114 | /* The name of the readonly data section. */ |
1dc1e798 KR |
115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
116 | ? ".data" \ | |
117 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
118 | ? ".rdata" \ | |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
d2c71068 | 122 | |
1aa6938e ILT |
123 | /* These variables are filled in with the masks of registers used. |
124 | The object format code reads them and puts them in the appropriate | |
125 | place. */ | |
126 | unsigned long mips_gprmask; | |
127 | unsigned long mips_cprmask[4]; | |
128 | ||
1051c97f ILT |
129 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
130 | temporarily using .set mipsN). */ | |
8358c818 ILT |
131 | static int mips_isa = -1; |
132 | ||
1051c97f ILT |
133 | /* MIPS ISA we are using for this output file. */ |
134 | static int file_mips_isa; | |
135 | ||
cc5703cd ILT |
136 | /* Whether we are assembling for the mips16 processor. */ |
137 | static int mips16 = -1; | |
138 | ||
8c63448a | 139 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 140 | static int mips_cpu = -1; |
8c63448a | 141 | |
b2b8c24e ILT |
142 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
143 | static int mips_4650 = -1; | |
144 | ||
e532b44c ILT |
145 | /* Whether the 4010 instructions are permitted. */ |
146 | static int mips_4010 = -1; | |
147 | ||
c625fc23 JSC |
148 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
149 | static int mips_4100 = -1; | |
150 | ||
e532b44c ILT |
151 | /* Whether the processor uses hardware interlocks, and thus does not |
152 | require nops to be inserted. */ | |
153 | static int interlocks = -1; | |
154 | ||
344a8d61 JSC |
155 | /* As with "interlocks" this is used by hardware that has FP |
156 | (co-processor) interlocks. */ | |
157 | static int cop_interlocks = -1; | |
158 | ||
d9aba805 ILT |
159 | /* MIPS PIC level. */ |
160 | ||
161 | enum mips_pic_level | |
162 | { | |
163 | /* Do not generate PIC code. */ | |
164 | NO_PIC, | |
165 | ||
166 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
167 | not sure what it is supposed to do. */ | |
168 | IRIX4_PIC, | |
169 | ||
170 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
171 | SVR4_PIC, | |
172 | ||
173 | /* Generate PIC code without using a global offset table: the data | |
174 | segment has a maximum size of 64K, all data references are off | |
175 | the $gp register, and all text references are PC relative. This | |
176 | is used on some embedded systems. */ | |
177 | EMBEDDED_PIC | |
178 | }; | |
179 | ||
180 | static enum mips_pic_level mips_pic; | |
9226253a | 181 | |
fb251650 ILT |
182 | /* 1 if we should generate 32 bit offsets from the GP register in |
183 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
184 | static int mips_big_got; | |
185 | ||
8ea7f4e8 ILT |
186 | /* 1 if trap instructions should used for overflow rather than break |
187 | instructions. */ | |
188 | static int mips_trap; | |
189 | ||
cc5703cd ILT |
190 | /* 1 if we should autoextend mips16 instructions. */ |
191 | static int mips16_autoextend = 1; | |
192 | ||
3d3c5039 ILT |
193 | static int mips_warn_about_macros; |
194 | static int mips_noreorder; | |
0dd2d296 | 195 | static int mips_any_noreorder; |
3d3c5039 ILT |
196 | static int mips_nomove; |
197 | static int mips_noat; | |
198 | static int mips_nobopt; | |
199 | ||
670a50eb ILT |
200 | /* The size of the small data section. */ |
201 | static int g_switch_value = 8; | |
42562568 ILT |
202 | /* Whether the -G option was used. */ |
203 | static int g_switch_seen = 0; | |
670a50eb | 204 | |
3d3c5039 ILT |
205 | #define N_RMASK 0xc4 |
206 | #define N_VFP 0xd4 | |
207 | ||
d8a1c247 KR |
208 | /* If we can determine in advance that GP optimization won't be |
209 | possible, we can skip the relaxation stuff that tries to produce | |
210 | GP-relative references. This makes delay slot optimization work | |
211 | better. | |
212 | ||
213 | This function can only provide a guess, but it seems to work for | |
214 | gcc output. If it guesses wrong, the only loss should be in | |
215 | efficiency; it shouldn't introduce any bugs. | |
216 | ||
217 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
218 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
219 | static int nopic_need_relax PARAMS ((symbolS *)); | |
220 | ||
3d3c5039 ILT |
221 | /* handle of the OPCODE hash table */ |
222 | static struct hash_control *op_hash = NULL; | |
223 | ||
cc5703cd ILT |
224 | /* The opcode hash table we use for the mips16. */ |
225 | static struct hash_control *mips16_op_hash = NULL; | |
226 | ||
3d3c5039 ILT |
227 | /* This array holds the chars that always start a comment. If the |
228 | pre-processor is disabled, these aren't very useful */ | |
229 | const char comment_chars[] = "#"; | |
230 | ||
231 | /* This array holds the chars that only start a comment at the beginning of | |
232 | a line. If the line seems to have the form '# 123 filename' | |
233 | .line and .file directives will appear in the pre-processed output */ | |
234 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
235 | first line of the input file. This is because the compiler outputs | |
236 | #NO_APP at the beginning of its output. */ | |
237 | /* Also note that C style comments are always supported. */ | |
238 | const char line_comment_chars[] = "#"; | |
239 | ||
240 | /* This array holds machine specific line separator characters. */ | |
241 | const char line_separator_chars[] = ""; | |
242 | ||
243 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
244 | const char EXP_CHARS[] = "eE"; | |
245 | ||
246 | /* Chars that mean this number is a floating point constant */ | |
247 | /* As in 0f12.456 */ | |
248 | /* or 0d1.2345e12 */ | |
249 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
250 | ||
251 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
252 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
253 | but nothing is ideal around here. | |
254 | */ | |
255 | ||
670a50eb | 256 | static char *insn_error; |
3d3c5039 | 257 | |
3d3c5039 | 258 | static int auto_align = 1; |
becfe05e | 259 | |
9226253a ILT |
260 | /* When outputting SVR4 PIC code, the assembler needs to know the |
261 | offset in the stack frame from which to restore the $gp register. | |
262 | This is set by the .cprestore pseudo-op, and saved in this | |
263 | variable. */ | |
0dd2d296 ILT |
264 | static offsetT mips_cprestore_offset = -1; |
265 | ||
266 | /* This is the register which holds the stack frame, as set by the | |
267 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
268 | static int mips_frame_reg = SP; | |
9226253a | 269 | |
becfe05e ILT |
270 | /* To output NOP instructions correctly, we need to keep information |
271 | about the previous two instructions. */ | |
272 | ||
0aa07269 ILT |
273 | /* Whether we are optimizing. The default value of 2 means to remove |
274 | unneeded NOPs and swap branch instructions when possible. A value | |
275 | of 1 means to not swap branches. A value of 0 means to always | |
276 | insert NOPs. */ | |
277 | static int mips_optimize = 2; | |
4e95866e | 278 | |
22ba90ce ILT |
279 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
280 | equivalent to seeing no -g option at all. */ | |
281 | static int mips_debug = 0; | |
282 | ||
becfe05e ILT |
283 | /* The previous instruction. */ |
284 | static struct mips_cl_insn prev_insn; | |
285 | ||
286 | /* The instruction before prev_insn. */ | |
287 | static struct mips_cl_insn prev_prev_insn; | |
288 | ||
289 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
290 | point the insn_mo field at this dummy integer. */ | |
291 | static const struct mips_opcode dummy_opcode = { 0 }; | |
292 | ||
293 | /* Non-zero if prev_insn is valid. */ | |
294 | static int prev_insn_valid; | |
295 | ||
296 | /* The frag for the previous instruction. */ | |
297 | static struct frag *prev_insn_frag; | |
298 | ||
299 | /* The offset into prev_insn_frag for the previous instruction. */ | |
300 | static long prev_insn_where; | |
301 | ||
a677feeb ILT |
302 | /* The reloc type for the previous instruction, if any. */ |
303 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
304 | ||
becfe05e ILT |
305 | /* The reloc for the previous instruction, if any. */ |
306 | static fixS *prev_insn_fixp; | |
307 | ||
308 | /* Non-zero if the previous instruction was in a delay slot. */ | |
309 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
310 | |
311 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
312 | static int prev_insn_unreordered; | |
313 | ||
cc5703cd ILT |
314 | /* Non-zero if the previous instruction uses an extend opcode (if |
315 | mips16). */ | |
316 | static int prev_insn_extended; | |
317 | ||
4e95866e ILT |
318 | /* Non-zero if the previous previous instruction was in a .set |
319 | noreorder. */ | |
320 | static int prev_prev_insn_unreordered; | |
867a58b3 ILT |
321 | |
322 | /* For ECOFF and ELF, relocations against symbols are done in two | |
323 | parts, with a HI relocation and a LO relocation. Each relocation | |
324 | has only 16 bits of space to store an addend. This means that in | |
325 | order for the linker to handle carries correctly, it must be able | |
326 | to locate both the HI and the LO relocation. This means that the | |
327 | relocations must appear in order in the relocation table. | |
328 | ||
329 | In order to implement this, we keep track of each unmatched HI | |
330 | relocation. We then sort them so that they immediately precede the | |
331 | corresponding LO relocation. */ | |
332 | ||
333 | struct mips_hi_fixup | |
334 | { | |
335 | /* Next HI fixup. */ | |
336 | struct mips_hi_fixup *next; | |
337 | /* This fixup. */ | |
338 | fixS *fixp; | |
339 | /* The section this fixup is in. */ | |
340 | segT seg; | |
341 | }; | |
342 | ||
343 | /* The list of unmatched HI relocs. */ | |
344 | ||
345 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
346 | |
347 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
348 | ||
349 | #define X ILLEGAL_REG | |
350 | static const int mips32_to_16_reg_map[] = | |
351 | { | |
352 | X, X, 2, 3, 4, 5, 6, 7, | |
353 | X, X, X, X, X, X, X, X, | |
354 | 0, 1, X, X, X, X, X, X, | |
355 | X, X, X, X, X, X, X, X | |
356 | }; | |
357 | #undef X | |
358 | ||
359 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
360 | ||
361 | static const int mips16_to_32_reg_map[] = | |
362 | { | |
363 | 16, 17, 2, 3, 4, 5, 6, 7 | |
364 | }; | |
3d3c5039 | 365 | \f |
0dd2d296 ILT |
366 | /* Since the MIPS does not have multiple forms of PC relative |
367 | instructions, we do not have to do relaxing as is done on other | |
368 | platforms. However, we do have to handle GP relative addressing | |
369 | correctly, which turns out to be a similar problem. | |
370 | ||
371 | Every macro that refers to a symbol can occur in (at least) two | |
372 | forms, one with GP relative addressing and one without. For | |
373 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 374 | a macro instruction like this: |
0dd2d296 ILT |
375 | lw $4,i |
376 | If i can be addressed off the GP register (this is true if it is in | |
377 | the .sbss or .sdata section, or if it is known to be smaller than | |
378 | the -G argument) this will generate the following instruction: | |
379 | lw $4,i($gp) | |
380 | This instruction will use a GPREL reloc. If i can not be addressed | |
381 | off the GP register, the following instruction sequence will be used: | |
382 | lui $at,i | |
383 | lw $4,i($at) | |
384 | In this case the first instruction will have a HI16 reloc, and the | |
385 | second reloc will have a LO16 reloc. Both relocs will be against | |
386 | the symbol i. | |
387 | ||
388 | The issue here is that we may not know whether i is GP addressable | |
389 | until after we see the instruction that uses it. Therefore, we | |
390 | want to be able to choose the final instruction sequence only at | |
391 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 392 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
393 | end of assembly. |
394 | ||
395 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
396 | addressing in quite the same way, but the issue still arises as |
397 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
398 | |
399 | We handle these issues by actually generating both possible | |
400 | instruction sequences. The longer one is put in a frag_var with | |
401 | type rs_machine_dependent. We encode what to do with the frag in | |
402 | the subtype field. We encode (1) the number of existing bytes to | |
403 | replace, (2) the number of new bytes to use, (3) the offset from | |
404 | the start of the existing bytes to the first reloc we must generate | |
405 | (that is, the offset is applied from the start of the existing | |
406 | bytes after they are replaced by the new bytes, if any), (4) the | |
407 | offset from the start of the existing bytes to the second reloc, | |
408 | (5) whether a third reloc is needed (the third reloc is always four | |
409 | bytes after the second reloc), and (6) whether to warn if this | |
410 | variant is used (this is sometimes needed if .set nomacro or .set | |
411 | noat is in effect). All these numbers are reasonably small. | |
412 | ||
413 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
414 | ensure that delay slots are handled correctly. Fortunately, there |
415 | are a limited number of cases. When the second instruction | |
416 | sequence is generated, append_insn is directed to maintain the | |
417 | existing delay slot information, so it continues to apply to any | |
418 | code after the second instruction sequence. This means that the | |
419 | second instruction sequence must not impose any requirements not | |
420 | required by the first instruction sequence. | |
0dd2d296 ILT |
421 | |
422 | These variant frags are then handled in functions called by the | |
423 | machine independent code. md_estimate_size_before_relax returns | |
424 | the final size of the frag. md_convert_frag sets up the final form | |
425 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
426 | one if needed. */ | |
427 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
428 | ((relax_substateT) \ | |
cc5703cd | 429 | (((old) << 23) \ |
0dd2d296 ILT |
430 | | ((new) << 16) \ |
431 | | (((reloc1) + 64) << 9) \ | |
432 | | (((reloc2) + 64) << 2) \ | |
433 | | ((reloc3) ? (1 << 1) : 0) \ | |
434 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
435 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
436 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
437 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
438 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
439 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
440 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
441 | |
442 | /* For mips16 code, we use an entirely different form of relaxation. | |
443 | mips16 supports two versions of most instructions which take | |
444 | immediate values: a small one which takes some small value, and a | |
445 | larger one which takes a 16 bit value. Since branches also follow | |
446 | this pattern, relaxing these values is required. | |
447 | ||
448 | We can assemble both mips16 and normal MIPS code in a single | |
449 | object. Therefore, we need to support this type of relaxation at | |
450 | the same time that we support the relaxation described above. We | |
451 | use the high bit of the subtype field to distinguish these cases. | |
452 | ||
a677feeb ILT |
453 | The information we store for this type of relaxation is the |
454 | argument code found in the opcode file for this relocation, whether | |
455 | the user explicitly requested a small or extended form, and whether | |
456 | the relocation is in a jump or jal delay slot. That tells us the | |
457 | size of the value, and how it should be stored. We also store | |
458 | whether the fragment is considered to be extended or not. We also | |
459 | store whether this is known to be a branch to a different section, | |
460 | whether we have tried to relax this frag yet, and whether we have | |
461 | ever extended a PC relative fragment because of a shift count. */ | |
462 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
463 | (0x80000000 \ | |
464 | | ((type) & 0xff) \ | |
465 | | ((small) ? 0x100 : 0) \ | |
466 | | ((ext) ? 0x200 : 0) \ | |
467 | | ((dslot) ? 0x400 : 0) \ | |
468 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
469 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
470 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
471 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
472 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
473 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
474 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
475 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
476 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
477 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
478 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
479 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
480 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 481 | \f |
3d3c5039 ILT |
482 | /* Prototypes for static functions. */ |
483 | ||
484 | #ifdef __STDC__ | |
485 | #define internalError() \ | |
486 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
487 | #else | |
488 | #define internalError() as_fatal ("MIPS internal Error"); | |
489 | #endif | |
490 | ||
cc5703cd ILT |
491 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
492 | ||
becfe05e | 493 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 494 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 495 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
496 | static void append_insn PARAMS ((char *place, |
497 | struct mips_cl_insn * ip, | |
670a50eb | 498 | expressionS * p, |
867a58b3 ILT |
499 | bfd_reloc_code_real_type r, |
500 | boolean)); | |
becfe05e | 501 | static void mips_no_prev_insn PARAMS ((void)); |
fbcfacb7 | 502 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 503 | #ifdef USE_STDARG |
0dd2d296 | 504 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
505 | const char *name, const char *fmt, |
506 | ...)); | |
c625fc23 JSC |
507 | #else |
508 | static void macro_build (); | |
509 | #endif | |
cc5703cd ILT |
510 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
511 | const char *, const char *, | |
512 | va_list)); | |
0dd2d296 ILT |
513 | static void macro_build_lui PARAMS ((char *place, int *counter, |
514 | expressionS * ep, int regnum)); | |
6e8dda9c | 515 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 516 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 517 | expressionS *)); |
d8a1c247 | 518 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 519 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 520 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 521 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
522 | #ifdef LOSING_COMPILER |
523 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
524 | #endif | |
670a50eb | 525 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 526 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
527 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
528 | boolean, boolean, unsigned long *, | |
529 | boolean *, unsigned short *)); | |
670a50eb ILT |
530 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
531 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 532 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 533 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
534 | static void s_align PARAMS ((int)); |
535 | static void s_change_sec PARAMS ((int)); | |
536 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 537 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 538 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
539 | static void s_option PARAMS ((int)); |
540 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
541 | static void s_abicalls PARAMS ((int)); |
542 | static void s_cpload PARAMS ((int)); | |
543 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
544 | static void s_gpword PARAMS ((int)); |
545 | static void s_cpadd PARAMS ((int)); | |
3d3c5039 ILT |
546 | static void md_obj_begin PARAMS ((void)); |
547 | static void md_obj_end PARAMS ((void)); | |
548 | static long get_number PARAMS ((void)); | |
549 | static void s_ent PARAMS ((int)); | |
550 | static void s_mipsend PARAMS ((int)); | |
551 | static void s_file PARAMS ((int)); | |
cc5703cd | 552 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
553 | \f |
554 | /* Pseudo-op table. | |
555 | ||
556 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
557 | should be defined here, but are currently unsupported: .alias, | |
558 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
559 | ||
560 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
561 | specific to the type of debugging information being generated, and | |
562 | should be defined by the object format: .aent, .begin, .bend, | |
563 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
564 | .vreg. | |
565 | ||
566 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
567 | not MIPS CPU specific, but are also not specific to the object file | |
568 | format. This file is probably the best place to define them, but | |
569 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
570 | .struct, .weakext. */ | |
571 | ||
739708fa | 572 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 573 | { |
670a50eb ILT |
574 | /* MIPS specific pseudo-ops. */ |
575 | {"option", s_option, 0}, | |
576 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
577 | {"rdata", s_change_sec, 'r'}, |
578 | {"sdata", s_change_sec, 's'}, | |
579 | {"livereg", s_ignore, 0}, | |
739708fa KR |
580 | {"abicalls", s_abicalls, 0}, |
581 | {"cpload", s_cpload, 0}, | |
582 | {"cprestore", s_cprestore, 0}, | |
583 | {"gpword", s_gpword, 0}, | |
584 | {"cpadd", s_cpadd, 0}, | |
3d3c5039 | 585 | |
670a50eb | 586 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 587 | chips. */ |
739708fa | 588 | {"asciiz", stringer, 1}, |
670a50eb ILT |
589 | {"bss", s_change_sec, 'b'}, |
590 | {"err", s_err, 0}, | |
591 | {"half", s_cons, 1}, | |
52aa70b5 | 592 | {"dword", s_cons, 3}, |
3d3c5039 | 593 | |
670a50eb | 594 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 595 | here for one reason or another. */ |
670a50eb ILT |
596 | {"align", s_align, 0}, |
597 | {"byte", s_cons, 0}, | |
598 | {"data", s_change_sec, 'd'}, | |
becfe05e | 599 | {"double", s_float_cons, 'd'}, |
becfe05e | 600 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
601 | {"globl", s_mips_globl, 0}, |
602 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
603 | {"hword", s_cons, 1}, |
604 | {"int", s_cons, 2}, | |
605 | {"long", s_cons, 2}, | |
606 | {"octa", s_cons, 4}, | |
607 | {"quad", s_cons, 3}, | |
608 | {"short", s_cons, 1}, | |
609 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
610 | {"text", s_change_sec, 't'}, |
611 | {"word", s_cons, 2}, | |
739708fa KR |
612 | { 0 }, |
613 | }; | |
3d3c5039 | 614 | |
739708fa | 615 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 616 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 617 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 618 | {"aent", s_ent, 1}, |
9226253a | 619 | {"bgnb", s_ignore, 0}, |
670a50eb | 620 | {"end", s_mipsend, 0}, |
9226253a | 621 | {"endb", s_ignore, 0}, |
670a50eb ILT |
622 | {"ent", s_ent, 0}, |
623 | {"file", s_file, 0}, | |
624 | {"fmask", s_ignore, 'F'}, | |
625 | {"frame", s_ignore, 0}, | |
626 | {"loc", s_ignore, 0}, | |
627 | {"mask", s_ignore, 'R'}, | |
628 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
629 | { 0 }, |
630 | }; | |
61420a20 | 631 | |
739708fa KR |
632 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
633 | ||
634 | void | |
635 | mips_pop_insert () | |
636 | { | |
637 | pop_insert (mips_pseudo_table); | |
638 | if (! ECOFF_DEBUGGING) | |
639 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 640 | } |
3d3c5039 | 641 | \f |
fbcfacb7 ILT |
642 | /* Symbols labelling the current insn. */ |
643 | ||
644 | struct insn_label_list | |
645 | { | |
646 | struct insn_label_list *next; | |
647 | symbolS *label; | |
648 | }; | |
649 | ||
650 | static struct insn_label_list *insn_labels; | |
651 | static struct insn_label_list *free_insn_labels; | |
652 | ||
653 | static void mips_clear_insn_labels PARAMS ((void)); | |
654 | ||
655 | static inline void | |
656 | mips_clear_insn_labels () | |
657 | { | |
658 | register struct insn_label_list **pl; | |
659 | ||
660 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
661 | ; | |
662 | *pl = insn_labels; | |
663 | insn_labels = NULL; | |
664 | } | |
665 | \f | |
3d3c5039 ILT |
666 | static char *expr_end; |
667 | ||
867a58b3 ILT |
668 | /* Expressions which appear in instructions. These are set by |
669 | mips_ip. */ | |
670 | ||
3d3c5039 ILT |
671 | static expressionS imm_expr; |
672 | static expressionS offset_expr; | |
867a58b3 ILT |
673 | |
674 | /* Relocs associated with imm_expr and offset_expr. */ | |
675 | ||
3d3c5039 ILT |
676 | static bfd_reloc_code_real_type imm_reloc; |
677 | static bfd_reloc_code_real_type offset_reloc; | |
678 | ||
867a58b3 ILT |
679 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
680 | ||
681 | static boolean imm_unmatched_hi; | |
682 | ||
8728fa92 ILT |
683 | /* These are set by mips16_ip if an explicit extension is used. */ |
684 | ||
685 | static boolean mips16_small, mips16_ext; | |
686 | ||
3d3c5039 ILT |
687 | /* |
688 | * This function is called once, at assembler startup time. It should | |
689 | * set up all the tables, etc. that the MD part of the assembler will need. | |
690 | */ | |
691 | void | |
670a50eb | 692 | md_begin () |
3d3c5039 | 693 | { |
0dd2d296 | 694 | boolean ok = false; |
604633ae | 695 | register const char *retval = NULL; |
670a50eb | 696 | register unsigned int i = 0; |
3d3c5039 | 697 | |
8358c818 ILT |
698 | if (mips_isa == -1) |
699 | { | |
8c63448a ILT |
700 | const char *cpu; |
701 | char *a = NULL; | |
702 | ||
703 | cpu = TARGET_CPU; | |
704 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
705 | { | |
706 | a = xmalloc (sizeof TARGET_CPU); | |
707 | strcpy (a, TARGET_CPU); | |
708 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
709 | cpu = a; | |
710 | } | |
711 | ||
712 | if (strcmp (cpu, "mips") == 0) | |
713 | { | |
714 | mips_isa = 1; | |
4bb0cc41 ILT |
715 | if (mips_cpu == -1) |
716 | mips_cpu = 3000; | |
8c63448a ILT |
717 | } |
718 | else if (strcmp (cpu, "r6000") == 0 | |
719 | || strcmp (cpu, "mips2") == 0) | |
720 | { | |
721 | mips_isa = 2; | |
4bb0cc41 ILT |
722 | if (mips_cpu == -1) |
723 | mips_cpu = 6000; | |
8c63448a ILT |
724 | } |
725 | else if (strcmp (cpu, "mips64") == 0 | |
726 | || strcmp (cpu, "r4000") == 0 | |
727 | || strcmp (cpu, "mips3") == 0) | |
728 | { | |
729 | mips_isa = 3; | |
4bb0cc41 ILT |
730 | if (mips_cpu == -1) |
731 | mips_cpu = 4000; | |
8c63448a ILT |
732 | } |
733 | else if (strcmp (cpu, "r4400") == 0) | |
734 | { | |
735 | mips_isa = 3; | |
4bb0cc41 ILT |
736 | if (mips_cpu == -1) |
737 | mips_cpu = 4400; | |
8c63448a ILT |
738 | } |
739 | else if (strcmp (cpu, "mips64orion") == 0 | |
740 | || strcmp (cpu, "r4600") == 0) | |
741 | { | |
742 | mips_isa = 3; | |
4bb0cc41 ILT |
743 | if (mips_cpu == -1) |
744 | mips_cpu = 4600; | |
8c63448a | 745 | } |
b2b8c24e ILT |
746 | else if (strcmp (cpu, "r4650") == 0) |
747 | { | |
748 | mips_isa = 3; | |
749 | if (mips_cpu == -1) | |
750 | mips_cpu = 4650; | |
751 | if (mips_4650 == -1) | |
752 | mips_4650 = 1; | |
753 | } | |
c625fc23 JSC |
754 | else if (strcmp (cpu, "mips64vr4300") == 0) |
755 | { | |
756 | mips_isa = 3; | |
757 | if (mips_cpu == -1) | |
758 | mips_cpu = 4300; | |
759 | } | |
760 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
761 | { | |
762 | mips_isa = 3; | |
763 | if (mips_cpu == -1) | |
764 | mips_cpu = 4100; | |
765 | if (mips_4100 == -1) | |
766 | mips_4100 = 1; | |
767 | } | |
e532b44c ILT |
768 | else if (strcmp (cpu, "r4010") == 0) |
769 | { | |
770 | mips_isa = 2; | |
771 | if (mips_cpu == -1) | |
772 | mips_cpu = 4010; | |
773 | if (mips_4010 == -1) | |
774 | mips_4010 = 1; | |
775 | } | |
517078c1 ILT |
776 | else if (strcmp (cpu, "r5000") == 0 |
777 | || strcmp (cpu, "mips64vr5000") == 0) | |
778 | { | |
779 | mips_isa = 4; | |
780 | if (mips_cpu == -1) | |
781 | mips_cpu = 5000; | |
782 | } | |
d8a1c247 KR |
783 | else if (strcmp (cpu, "r8000") == 0 |
784 | || strcmp (cpu, "mips4") == 0) | |
785 | { | |
786 | mips_isa = 4; | |
787 | if (mips_cpu == -1) | |
788 | mips_cpu = 8000; | |
789 | } | |
790 | else if (strcmp (cpu, "r10000") == 0) | |
791 | { | |
792 | mips_isa = 4; | |
793 | if (mips_cpu == -1) | |
794 | mips_cpu = 10000; | |
795 | } | |
cc5703cd ILT |
796 | else if (strcmp (cpu, "mips16") == 0) |
797 | { | |
798 | mips_isa = 3; | |
799 | if (mips_cpu == -1) | |
800 | mips_cpu = 0; /* FIXME */ | |
801 | } | |
8358c818 | 802 | else |
8c63448a ILT |
803 | { |
804 | mips_isa = 1; | |
4bb0cc41 ILT |
805 | if (mips_cpu == -1) |
806 | mips_cpu = 3000; | |
8c63448a ILT |
807 | } |
808 | ||
809 | if (a != NULL) | |
810 | free (a); | |
8358c818 ILT |
811 | } |
812 | ||
cc5703cd ILT |
813 | if (mips16 < 0) |
814 | { | |
815 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
816 | mips16 = 1; | |
817 | else | |
818 | mips16 = 0; | |
819 | } | |
820 | ||
b2b8c24e ILT |
821 | if (mips_4650 < 0) |
822 | mips_4650 = 0; | |
823 | ||
e532b44c ILT |
824 | if (mips_4010 < 0) |
825 | mips_4010 = 0; | |
826 | ||
c625fc23 JSC |
827 | if (mips_4100 < 0) |
828 | mips_4100 = 0; | |
829 | ||
c36a90ef | 830 | if (mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
831 | interlocks = 1; |
832 | else | |
833 | interlocks = 0; | |
834 | ||
ca296aab | 835 | if (mips_cpu == 4300) |
344a8d61 JSC |
836 | cop_interlocks = 1; |
837 | else | |
838 | cop_interlocks = 0; | |
839 | ||
8ea7f4e8 ILT |
840 | if (mips_isa < 2 && mips_trap) |
841 | as_bad ("trap exception not supported at ISA 1"); | |
842 | ||
97f99d11 ILT |
843 | switch (mips_isa) |
844 | { | |
845 | case 1: | |
846 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
847 | break; | |
848 | case 2: | |
849 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
850 | break; | |
851 | case 3: | |
852 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
853 | break; | |
d8a1c247 KR |
854 | case 4: |
855 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
856 | break; | |
97f99d11 ILT |
857 | } |
858 | if (! ok) | |
859 | as_warn ("Could not set architecture and machine"); | |
860 | ||
1051c97f ILT |
861 | file_mips_isa = mips_isa; |
862 | ||
13fe1379 ILT |
863 | op_hash = hash_new (); |
864 | ||
670a50eb ILT |
865 | for (i = 0; i < NUMOPCODES;) |
866 | { | |
867 | const char *name = mips_opcodes[i].name; | |
868 | ||
604633ae | 869 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 870 | if (retval != NULL) |
670a50eb ILT |
871 | { |
872 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
873 | mips_opcodes[i].name, retval); | |
874 | as_fatal ("Broken assembler. No assembly attempted."); | |
875 | } | |
876 | do | |
877 | { | |
8358c818 ILT |
878 | if (mips_opcodes[i].pinfo != INSN_MACRO |
879 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
880 | != mips_opcodes[i].match)) | |
670a50eb ILT |
881 | { |
882 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
883 | mips_opcodes[i].name, mips_opcodes[i].args); | |
884 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 885 | } |
670a50eb ILT |
886 | ++i; |
887 | } | |
888 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
889 | } |
890 | ||
cc5703cd ILT |
891 | mips16_op_hash = hash_new (); |
892 | ||
893 | i = 0; | |
894 | while (i < bfd_mips16_num_opcodes) | |
895 | { | |
896 | const char *name = mips16_opcodes[i].name; | |
897 | ||
898 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
899 | if (retval != NULL) | |
900 | as_fatal ("internal error: can't hash `%s': %s\n", | |
901 | mips16_opcodes[i].name, retval); | |
902 | do | |
903 | { | |
904 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
905 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
906 | != mips16_opcodes[i].match)) | |
907 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
908 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
909 | ++i; | |
910 | } | |
911 | while (i < bfd_mips16_num_opcodes | |
912 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
913 | } | |
914 | ||
becfe05e ILT |
915 | mips_no_prev_insn (); |
916 | ||
1aa6938e ILT |
917 | mips_gprmask = 0; |
918 | mips_cprmask[0] = 0; | |
919 | mips_cprmask[1] = 0; | |
920 | mips_cprmask[2] = 0; | |
921 | mips_cprmask[3] = 0; | |
922 | ||
8358c818 | 923 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 924 | record_alignment (text_section, 2); |
8358c818 | 925 | |
1dc1e798 KR |
926 | if (USE_GLOBAL_POINTER_OPT) |
927 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 928 | |
1dc1e798 KR |
929 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
930 | { | |
08e17202 ILT |
931 | /* On a native system, sections must be aligned to 16 byte |
932 | boundaries. When configured for an embedded ELF target, we | |
933 | don't bother. */ | |
934 | if (strcmp (TARGET_OS, "elf") != 0) | |
935 | { | |
936 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
937 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
938 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
939 | } | |
1dc1e798 KR |
940 | |
941 | /* Create a .reginfo section for register masks and a .mdebug | |
942 | section for debugging information. */ | |
943 | { | |
944 | segT seg; | |
945 | subsegT subseg; | |
b3a64736 | 946 | flagword flags; |
1dc1e798 KR |
947 | segT sec; |
948 | ||
949 | seg = now_seg; | |
950 | subseg = now_subseg; | |
1dc1e798 | 951 | |
b3a64736 ILT |
952 | /* The ABI says this section should be loaded so that the |
953 | running program can access it. However, we don't load it | |
954 | if we are configured for an embedded target */ | |
955 | flags = SEC_READONLY | SEC_DATA; | |
956 | if (strcmp (TARGET_OS, "elf") != 0) | |
957 | flags |= SEC_ALLOC | SEC_LOAD; | |
958 | ||
87178180 ILT |
959 | if (! mips_64) |
960 | { | |
961 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 962 | |
b3a64736 ILT |
963 | |
964 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
965 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
966 | ||
f2a663d3 | 967 | #ifdef OBJ_ELF |
87178180 | 968 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 969 | #endif |
87178180 ILT |
970 | } |
971 | else | |
972 | { | |
973 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
974 | .reginfo section. */ | |
975 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 976 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
977 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
978 | ||
979 | #ifdef OBJ_ELF | |
980 | /* Set up the option header. */ | |
981 | { | |
982 | Elf_Internal_Options opthdr; | |
983 | char *f; | |
984 | ||
985 | opthdr.kind = ODK_REGINFO; | |
986 | opthdr.size = (sizeof (Elf_External_Options) | |
987 | + sizeof (Elf64_External_RegInfo)); | |
988 | opthdr.section = 0; | |
989 | opthdr.info = 0; | |
990 | f = frag_more (sizeof (Elf_External_Options)); | |
991 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
992 | (Elf_External_Options *) f); | |
993 | ||
994 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
995 | } | |
996 | #endif | |
997 | } | |
f2a663d3 | 998 | |
739708fa KR |
999 | if (ECOFF_DEBUGGING) |
1000 | { | |
1001 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1002 | (void) bfd_set_section_flags (stdoutput, sec, | |
1003 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1004 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1005 | } | |
0dd2d296 | 1006 | |
1dc1e798 KR |
1007 | subseg_set (seg, subseg); |
1008 | } | |
1009 | } | |
f2a663d3 | 1010 | |
739708fa KR |
1011 | if (! ECOFF_DEBUGGING) |
1012 | md_obj_begin (); | |
3d3c5039 ILT |
1013 | } |
1014 | ||
1015 | void | |
13fe1379 | 1016 | md_mips_end () |
3d3c5039 | 1017 | { |
739708fa KR |
1018 | if (! ECOFF_DEBUGGING) |
1019 | md_obj_end (); | |
3d3c5039 ILT |
1020 | } |
1021 | ||
1022 | void | |
670a50eb ILT |
1023 | md_assemble (str) |
1024 | char *str; | |
3d3c5039 | 1025 | { |
670a50eb | 1026 | struct mips_cl_insn insn; |
3d3c5039 | 1027 | |
5ac34ac3 | 1028 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1029 | imm_reloc = BFD_RELOC_UNUSED; |
1030 | imm_unmatched_hi = false; | |
5ac34ac3 | 1031 | offset_expr.X_op = O_absent; |
867a58b3 | 1032 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1033 | |
cc5703cd ILT |
1034 | if (mips16) |
1035 | mips16_ip (str, &insn); | |
1036 | else | |
1037 | mips_ip (str, &insn); | |
1038 | ||
670a50eb ILT |
1039 | if (insn_error) |
1040 | { | |
1041 | as_bad ("%s `%s'", insn_error, str); | |
1042 | return; | |
1043 | } | |
cc5703cd | 1044 | |
670a50eb ILT |
1045 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1046 | { | |
cc5703cd ILT |
1047 | if (mips16) |
1048 | mips16_macro (&insn); | |
1049 | else | |
1050 | macro (&insn); | |
3d3c5039 | 1051 | } |
670a50eb ILT |
1052 | else |
1053 | { | |
5ac34ac3 | 1054 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1055 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1056 | imm_unmatched_hi); | |
5ac34ac3 | 1057 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1058 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1059 | else |
867a58b3 | 1060 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1061 | } |
1062 | } | |
1063 | ||
cc5703cd ILT |
1064 | /* See whether instruction IP reads register REG. CLASS is the type |
1065 | of register. */ | |
becfe05e ILT |
1066 | |
1067 | static int | |
cc5703cd | 1068 | insn_uses_reg (ip, reg, class) |
becfe05e | 1069 | struct mips_cl_insn *ip; |
604633ae | 1070 | unsigned int reg; |
cc5703cd | 1071 | enum mips_regclass class; |
becfe05e | 1072 | { |
cc5703cd ILT |
1073 | if (class == MIPS16_REG) |
1074 | { | |
1075 | assert (mips16); | |
1076 | reg = mips16_to_32_reg_map[reg]; | |
1077 | class = MIPS_GR_REG; | |
1078 | } | |
1079 | ||
becfe05e | 1080 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1081 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1082 | return 0; |
1083 | ||
cc5703cd | 1084 | if (class == MIPS_FP_REG) |
becfe05e | 1085 | { |
cc5703cd | 1086 | assert (! mips16); |
becfe05e ILT |
1087 | /* If we are called with either $f0 or $f1, we must check $f0. |
1088 | This is not optimal, because it will introduce an unnecessary | |
1089 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1090 | need to distinguish reading both $f0 and $f1 or just one of | |
1091 | them. Note that we don't have to check the other way, | |
1092 | because there is no instruction that sets both $f0 and $f1 | |
1093 | and requires a delay. */ | |
1094 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1095 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1096 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1097 | return 1; |
1098 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1099 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1100 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1101 | return 1; |
1102 | } | |
cc5703cd | 1103 | else if (! mips16) |
becfe05e ILT |
1104 | { |
1105 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1106 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1107 | return 1; | |
1108 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1109 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1110 | return 1; | |
1111 | } | |
cc5703cd ILT |
1112 | else |
1113 | { | |
1114 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1115 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1116 | return 1; | |
1117 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1118 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1119 | return 1; | |
1120 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1121 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1122 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1123 | return 1; | |
1124 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1125 | return 1; | |
1126 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1127 | return 1; | |
1128 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1129 | return 1; | |
1130 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1131 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1132 | & MIPS16OP_MASK_REGR32) == reg) | |
1133 | return 1; | |
1134 | } | |
becfe05e ILT |
1135 | |
1136 | return 0; | |
1137 | } | |
1138 | ||
fb251650 ILT |
1139 | /* This function returns true if modifying a register requires a |
1140 | delay. */ | |
1141 | ||
1142 | static int | |
1143 | reg_needs_delay (reg) | |
1144 | int reg; | |
1145 | { | |
1146 | unsigned long prev_pinfo; | |
1147 | ||
1148 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1149 | if (! mips_noreorder | |
1150 | && mips_isa < 4 | |
1151 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1152 | || (mips_isa < 2 | |
1153 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1154 | { | |
1155 | /* A load from a coprocessor or from memory. All load | |
1156 | delays delay the use of general register rt for one | |
1157 | instruction on the r3000. The r6000 and r4000 use | |
1158 | interlocks. */ | |
1159 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1160 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1161 | return 1; | |
1162 | } | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
0dd2d296 ILT |
1167 | /* Output an instruction. PLACE is where to put the instruction; if |
1168 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1169 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1170 | used with RELOC_TYPE. */ | |
3d3c5039 | 1171 | |
3d3c5039 | 1172 | static void |
867a58b3 | 1173 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1174 | char *place; |
670a50eb ILT |
1175 | struct mips_cl_insn *ip; |
1176 | expressionS *address_expr; | |
1177 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1178 | boolean unmatched_hi; |
3d3c5039 | 1179 | { |
1aa6938e | 1180 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1181 | char *f; |
becfe05e ILT |
1182 | fixS *fixp; |
1183 | int nops = 0; | |
3d3c5039 | 1184 | |
fbcfacb7 ILT |
1185 | /* Mark instruction labels in mips16 mode. This permits the linker |
1186 | to handle them specially, such as generating jalx instructions | |
1187 | when needed. We also make them odd for the duration of the | |
1188 | assembly, in order to generate the right sort of code. We will | |
1189 | make them even in the adjust_symtab routine, while leaving them | |
1190 | marked. This is convenient for the debugger and the | |
1191 | disassembler. The linker knows to make them odd again. */ | |
1192 | if (mips16) | |
1193 | { | |
1194 | struct insn_label_list *l; | |
1195 | ||
1196 | for (l = insn_labels; l != NULL; l = l->next) | |
1197 | { | |
1198 | #ifdef S_SET_OTHER | |
1199 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1200 | S_SET_OTHER (l->label, STO_MIPS16); | |
1201 | #endif | |
1202 | ++l->label->sy_value.X_add_number; | |
1203 | } | |
1204 | } | |
1205 | ||
1aa6938e ILT |
1206 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1207 | pinfo = ip->insn_mo->pinfo; | |
1208 | ||
0dd2d296 | 1209 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
1210 | { |
1211 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 1212 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1213 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1214 | (1) a load from memory delay |
1215 | (2) a load from a coprocessor delay | |
1216 | (3) an unconditional branch delay | |
1217 | (4) a conditional branch delay | |
1218 | (5) a move to coprocessor register delay | |
1219 | (6) a load coprocessor register from memory delay | |
1220 | (7) a coprocessor condition code delay | |
1221 | (8) a HI/LO special register delay | |
becfe05e ILT |
1222 | |
1223 | There are a lot of optimizations we could do that we don't. | |
1224 | In particular, we do not, in general, reorder instructions. | |
1225 | If you use gcc with optimization, it will reorder | |
1226 | instructions and generally do much more optimization then we | |
1227 | do here; repeating all that work in the assembler would only | |
1228 | benefit hand written assembly code, and does not seem worth | |
1229 | it. */ | |
1230 | ||
1231 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1232 | #define emit_nop() \ |
1233 | (mips16 \ | |
1234 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1235 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1236 | |
1237 | /* The previous insn might require a delay slot, depending upon | |
1238 | the contents of the current insn. */ | |
cc5703cd ILT |
1239 | if (! mips16 |
1240 | && mips_isa < 4 | |
5af96dce ILT |
1241 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1242 | && ! cop_interlocks) | |
d8a1c247 KR |
1243 | || (mips_isa < 2 |
1244 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1245 | { |
1246 | /* A load from a coprocessor or from memory. All load | |
1247 | delays delay the use of general register rt for one | |
1248 | instruction on the r3000. The r6000 and r4000 use | |
1249 | interlocks. */ | |
1aa6938e | 1250 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1251 | if (mips_optimize == 0 |
1252 | || insn_uses_reg (ip, | |
1253 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1254 | & OP_MASK_RT), | |
cc5703cd | 1255 | MIPS_GR_REG)) |
becfe05e ILT |
1256 | ++nops; |
1257 | } | |
cc5703cd ILT |
1258 | else if (! mips16 |
1259 | && mips_isa < 4 | |
5af96dce ILT |
1260 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1261 | && ! cop_interlocks) | |
d8a1c247 KR |
1262 | || (mips_isa < 2 |
1263 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1264 | { |
1265 | /* A generic coprocessor delay. The previous instruction | |
1266 | modified a coprocessor general or control register. If | |
1267 | it modified a control register, we need to avoid any | |
1268 | coprocessor instruction (this is probably not always | |
1269 | required, but it sometimes is). If it modified a general | |
1270 | register, we avoid using that register. | |
1271 | ||
8358c818 ILT |
1272 | On the r6000 and r4000 loading a coprocessor register |
1273 | from memory is interlocked, and does not require a delay. | |
1274 | ||
becfe05e ILT |
1275 | This case is not handled very well. There is no special |
1276 | knowledge of CP0 handling, and the coprocessors other | |
1277 | than the floating point unit are not distinguished at | |
1278 | all. */ | |
1aa6938e | 1279 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1280 | { |
0aa07269 ILT |
1281 | if (mips_optimize == 0 |
1282 | || insn_uses_reg (ip, | |
8358c818 ILT |
1283 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1284 | & OP_MASK_FT), | |
cc5703cd | 1285 | MIPS_FP_REG)) |
becfe05e ILT |
1286 | ++nops; |
1287 | } | |
1aa6938e | 1288 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1289 | { |
0aa07269 ILT |
1290 | if (mips_optimize == 0 |
1291 | || insn_uses_reg (ip, | |
8358c818 ILT |
1292 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1293 | & OP_MASK_FS), | |
cc5703cd | 1294 | MIPS_FP_REG)) |
becfe05e ILT |
1295 | ++nops; |
1296 | } | |
1297 | else | |
1298 | { | |
1299 | /* We don't know exactly what the previous instruction | |
1300 | does. If the current instruction uses a coprocessor | |
1301 | register, we must insert a NOP. If previous | |
1302 | instruction may set the condition codes, and the | |
1303 | current instruction uses them, we must insert two | |
1304 | NOPS. */ | |
0aa07269 | 1305 | if (mips_optimize == 0 |
1aa6938e ILT |
1306 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1307 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1308 | nops += 2; |
1aa6938e | 1309 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1310 | ++nops; |
1311 | } | |
1312 | } | |
cc5703cd ILT |
1313 | else if (! mips16 |
1314 | && mips_isa < 4 | |
344a8d61 JSC |
1315 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1316 | && ! cop_interlocks) | |
becfe05e ILT |
1317 | { |
1318 | /* The previous instruction sets the coprocessor condition | |
1319 | codes, but does not require a general coprocessor delay | |
1320 | (this means it is a floating point comparison | |
1321 | instruction). If this instruction uses the condition | |
1322 | codes, we need to insert a single NOP. */ | |
0aa07269 | 1323 | if (mips_optimize == 0 |
1aa6938e | 1324 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1325 | ++nops; |
1326 | } | |
1aa6938e | 1327 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1328 | { |
1329 | /* The previous instruction reads the LO register; if the | |
1330 | current instruction writes to the LO register, we must | |
517078c1 | 1331 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1332 | if (! interlocks |
b2b8c24e ILT |
1333 | && (mips_optimize == 0 |
1334 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1335 | nops += 2; |
1336 | } | |
1337 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1338 | { | |
1339 | /* The previous instruction reads the HI register; if the | |
1340 | current instruction writes to the HI register, we must | |
517078c1 | 1341 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1342 | if (! interlocks |
b2b8c24e ILT |
1343 | && (mips_optimize == 0 |
1344 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1345 | nops += 2; |
1346 | } | |
1347 | ||
1348 | /* There are two cases which require two intervening | |
1349 | instructions: 1) setting the condition codes using a move to | |
1350 | coprocessor instruction which requires a general coprocessor | |
1351 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1352 | or LO register and then writing to it (except on processors |
1353 | which have interlocks). If we are not already emitting a NOP | |
1354 | instruction, we must check for these cases compared to the | |
1355 | instruction previous to the previous instruction. */ | |
becfe05e | 1356 | if (nops == 0 |
cc5703cd ILT |
1357 | && ((! mips16 |
1358 | && mips_isa < 4 | |
d8a1c247 | 1359 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 1360 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
344a8d61 JSC |
1361 | && (pinfo & INSN_READ_COND_CODE) |
1362 | && ! cop_interlocks) | |
becfe05e | 1363 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1364 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1365 | && ! interlocks) |
becfe05e | 1366 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1367 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1368 | && ! interlocks))) |
becfe05e ILT |
1369 | ++nops; |
1370 | ||
0dd2d296 ILT |
1371 | /* If we are being given a nop instruction, don't bother with |
1372 | one of the nops we would otherwise output. This will only | |
1373 | happen when a nop instruction is used with mips_optimize set | |
1374 | to 0. */ | |
cc5703cd | 1375 | if (nops > 0 && ip->insn_opcode == (mips16 ? 0x6500 : 0)) |
0dd2d296 ILT |
1376 | --nops; |
1377 | ||
becfe05e ILT |
1378 | /* Now emit the right number of NOP instructions. */ |
1379 | if (nops > 0) | |
1380 | { | |
5af96dce ILT |
1381 | fragS *old_frag; |
1382 | unsigned long old_frag_offset; | |
8c63448a | 1383 | int i; |
fbcfacb7 | 1384 | struct insn_label_list *l; |
8c63448a | 1385 | |
5af96dce ILT |
1386 | old_frag = frag_now; |
1387 | old_frag_offset = frag_now_fix (); | |
1388 | ||
8c63448a | 1389 | for (i = 0; i < nops; i++) |
becfe05e | 1390 | emit_nop (); |
5af96dce | 1391 | |
af255ca0 | 1392 | if (listing) |
546f5536 ILT |
1393 | { |
1394 | listing_prev_line (); | |
1395 | /* We may be at the start of a variant frag. In case we | |
1396 | are, make sure there is enough space for the frag | |
1397 | after the frags created by listing_prev_line. The | |
1398 | argument to frag_grow here must be at least as large | |
1399 | as the argument to all other calls to frag_grow in | |
1400 | this file. We don't have to worry about being in the | |
1401 | middle of a variant frag, because the variants insert | |
1402 | all needed nop instructions themselves. */ | |
1403 | frag_grow (40); | |
1404 | } | |
5af96dce | 1405 | |
fbcfacb7 | 1406 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1407 | { |
fbcfacb7 ILT |
1408 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1409 | l->label->sy_frag = frag_now; | |
1410 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1411 | /* mips16 text labels are stored as odd. */ | |
1412 | if (mips16) | |
1413 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1414 | } |
5af96dce ILT |
1415 | |
1416 | #ifndef NO_ECOFF_DEBUGGING | |
1417 | if (ECOFF_DEBUGGING) | |
1418 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1419 | #endif | |
becfe05e ILT |
1420 | } |
1421 | } | |
1422 | ||
cc5703cd ILT |
1423 | if (reloc_type > BFD_RELOC_UNUSED) |
1424 | { | |
1425 | /* We need to set up a variant frag. */ | |
1426 | assert (mips16 && address_expr != NULL); | |
1427 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1428 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1429 | mips16_small, mips16_ext, |
1430 | (prev_pinfo | |
1431 | & INSN_UNCOND_BRANCH_DELAY), | |
1432 | (prev_insn_reloc_type | |
1433 | == BFD_RELOC_MIPS16_JMP)), | |
cc5703cd ILT |
1434 | make_expr_symbol (address_expr), (long) 0, |
1435 | (char *) NULL); | |
1436 | } | |
1437 | else if (place != NULL) | |
0dd2d296 | 1438 | f = place; |
cc5703cd | 1439 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1440 | { |
1441 | /* Make sure there is enough room to swap this instruction with | |
1442 | a following jump instruction. */ | |
1443 | frag_grow (6); | |
1444 | f = frag_more (2); | |
1445 | } | |
cc5703cd ILT |
1446 | else |
1447 | f = frag_more (4); | |
becfe05e | 1448 | fixp = NULL; |
cc5703cd | 1449 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1450 | { |
5ac34ac3 | 1451 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1452 | { |
1453 | switch (reloc_type) | |
1454 | { | |
3d3c5039 | 1455 | case BFD_RELOC_32: |
670a50eb ILT |
1456 | ip->insn_opcode |= address_expr->X_add_number; |
1457 | break; | |
3d3c5039 ILT |
1458 | |
1459 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1460 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1461 | break; | |
3d3c5039 ILT |
1462 | |
1463 | case BFD_RELOC_MIPS_JMP: | |
5e1e8f23 ILT |
1464 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1465 | break; | |
1466 | ||
cc5703cd ILT |
1467 | case BFD_RELOC_MIPS16_JMP: |
1468 | ip->insn_opcode |= | |
1469 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1470 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1471 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1472 | break; | |
1473 | ||
3d3c5039 | 1474 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1475 | goto need_reloc; |
3d3c5039 ILT |
1476 | |
1477 | default: | |
670a50eb | 1478 | internalError (); |
3d3c5039 | 1479 | } |
670a50eb ILT |
1480 | } |
1481 | else | |
1482 | { | |
3d3c5039 | 1483 | need_reloc: |
0dd2d296 ILT |
1484 | /* Don't generate a reloc if we are writing into a variant |
1485 | frag. */ | |
1486 | if (place == NULL) | |
867a58b3 ILT |
1487 | { |
1488 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1489 | address_expr, | |
1490 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1491 | reloc_type); | |
1492 | if (unmatched_hi) | |
1493 | { | |
1494 | struct mips_hi_fixup *hi_fixup; | |
1495 | ||
1496 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1497 | hi_fixup = ((struct mips_hi_fixup *) | |
1498 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1499 | hi_fixup->fixp = fixp; | |
1500 | hi_fixup->seg = now_seg; | |
1501 | hi_fixup->next = mips_hi_fixup_list; | |
1502 | mips_hi_fixup_list = hi_fixup; | |
1503 | } | |
1504 | } | |
3d3c5039 ILT |
1505 | } |
1506 | } | |
becfe05e | 1507 | |
cc5703cd ILT |
1508 | if (! mips16 || reloc_type == BFD_RELOC_MIPS16_JMP) |
1509 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1510 | else | |
1511 | { | |
1512 | if (ip->use_extend) | |
1513 | { | |
1514 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1515 | f += 2; | |
1516 | } | |
1517 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1518 | } | |
670a50eb | 1519 | |
1aa6938e | 1520 | /* Update the register mask information. */ |
cc5703cd ILT |
1521 | if (! mips16) |
1522 | { | |
1523 | if (pinfo & INSN_WRITE_GPR_D) | |
1524 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1525 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1526 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1527 | if (pinfo & INSN_READ_GPR_S) | |
1528 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1529 | if (pinfo & INSN_WRITE_GPR_31) | |
1530 | mips_gprmask |= 1 << 31; | |
1531 | if (pinfo & INSN_WRITE_FPR_D) | |
1532 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1533 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1534 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1535 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1536 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1537 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1538 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1539 | if (pinfo & INSN_COP) | |
1540 | { | |
1541 | /* We don't keep enough information to sort these cases out. */ | |
1542 | } | |
1543 | /* Never set the bit for $0, which is always zero. */ | |
1544 | mips_gprmask &=~ 1 << 0; | |
1545 | } | |
1546 | else | |
1aa6938e | 1547 | { |
cc5703cd ILT |
1548 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1549 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1550 | & MIPS16OP_MASK_RX); | |
1551 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1552 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1553 | & MIPS16OP_MASK_RY); | |
1554 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1555 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1556 | & MIPS16OP_MASK_RZ); | |
1557 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1558 | mips_gprmask |= 1 << TREG; | |
1559 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1560 | mips_gprmask |= 1 << SP; | |
1561 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1562 | mips_gprmask |= 1 << RA; | |
1563 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1564 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1565 | if (pinfo & MIPS16_INSN_READ_Z) | |
1566 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1567 | & MIPS16OP_MASK_MOVE32Z); | |
1568 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1569 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1570 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1571 | } |
1aa6938e | 1572 | |
0dd2d296 | 1573 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1574 | { |
becfe05e ILT |
1575 | /* Filling the branch delay slot is more complex. We try to |
1576 | switch the branch with the previous instruction, which we can | |
1577 | do if the previous instruction does not set up a condition | |
1578 | that the branch tests and if the branch is not itself the | |
1579 | target of any branch. */ | |
1aa6938e ILT |
1580 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1581 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1582 | { |
0aa07269 | 1583 | if (mips_optimize < 2 |
19ed8960 ILT |
1584 | /* If we have seen .set volatile or .set nomove, don't |
1585 | optimize. */ | |
1586 | || mips_nomove != 0 | |
4e95866e ILT |
1587 | /* If we had to emit any NOP instructions, then we |
1588 | already know we can not swap. */ | |
1589 | || nops != 0 | |
becfe05e ILT |
1590 | /* If we don't even know the previous insn, we can not |
1591 | swap. */ | |
1592 | || ! prev_insn_valid | |
1593 | /* If the previous insn is already in a branch delay | |
1594 | slot, then we can not swap. */ | |
1595 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1596 | /* If the previous previous insn was in a .set |
1597 | noreorder, we can't swap. Actually, the MIPS | |
1598 | assembler will swap in this situation. However, gcc | |
1599 | configured -with-gnu-as will generate code like | |
1600 | .set noreorder | |
1601 | lw $4,XXX | |
1602 | .set reorder | |
1603 | INSN | |
1604 | bne $4,$0,foo | |
1605 | in which we can not swap the bne and INSN. If gcc is | |
1606 | not configured -with-gnu-as, it does not output the | |
1607 | .set pseudo-ops. We don't have to check | |
1608 | prev_insn_unreordered, because prev_insn_valid will | |
1609 | be 0 in that case. We don't want to use | |
1610 | prev_prev_insn_valid, because we do want to be able | |
1611 | to swap at the start of a function. */ | |
1612 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1613 | /* If the branch is itself the target of a branch, we |
1614 | can not swap. We cheat on this; all we check for is | |
1615 | whether there is a label on this instruction. If | |
1616 | there are any branches to anything other than a | |
1617 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1618 | || insn_labels != NULL |
777ad64d | 1619 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1620 | can not do the swap. This does not apply to the |
1621 | mips16, which uses variant frags for different | |
1622 | purposes. */ | |
1623 | || (! mips16 | |
1624 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1625 | /* If the branch reads the condition codes, we don't |
1626 | even try to swap, because in the sequence | |
1627 | ctc1 $X,$31 | |
1628 | INSN | |
1629 | INSN | |
1630 | bc1t LABEL | |
1631 | we can not swap, and I don't feel like handling that | |
1632 | case. */ | |
cc5703cd ILT |
1633 | || (! mips16 |
1634 | && mips_isa < 4 | |
d8a1c247 | 1635 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1636 | /* We can not swap with an instruction that requires a |
1637 | delay slot, becase the target of the branch might | |
1638 | interfere with that instruction. */ | |
cc5703cd ILT |
1639 | || (! mips16 |
1640 | && mips_isa < 4 | |
d8a1c247 KR |
1641 | && (prev_pinfo |
1642 | & (INSN_LOAD_COPROC_DELAY | |
1643 | | INSN_COPROC_MOVE_DELAY | |
1644 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1645 | || (! interlocks |
b2b8c24e ILT |
1646 | && (prev_pinfo |
1647 | & (INSN_READ_LO | |
1648 | | INSN_READ_HI))) | |
cc5703cd ILT |
1649 | || (! mips16 |
1650 | && mips_isa < 2 | |
1aa6938e | 1651 | && (prev_pinfo |
8358c818 ILT |
1652 | & (INSN_LOAD_MEMORY_DELAY |
1653 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1654 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1655 | || (prev_pinfo |
6e8dda9c ILT |
1656 | & (INSN_UNCOND_BRANCH_DELAY |
1657 | | INSN_COND_BRANCH_DELAY | |
1658 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1659 | /* We do not swap with a trap instruction, since it |
1660 | complicates trap handlers to have the trap | |
1661 | instruction be in a delay slot. */ | |
1aa6938e | 1662 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1663 | /* If the branch reads a register that the previous |
1664 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1665 | || (! mips16 |
1666 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1667 | && insn_uses_reg (ip, |
1668 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1669 | & OP_MASK_RT), | |
cc5703cd ILT |
1670 | MIPS_GR_REG)) |
1671 | || (! mips16 | |
1672 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1673 | && insn_uses_reg (ip, |
1674 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1675 | & OP_MASK_RD), | |
cc5703cd ILT |
1676 | MIPS_GR_REG)) |
1677 | || (mips16 | |
1678 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1679 | && insn_uses_reg (ip, | |
1680 | ((prev_insn.insn_opcode | |
1681 | >> MIPS16OP_SH_RX) | |
1682 | & MIPS16OP_MASK_RX), | |
1683 | MIPS16_REG)) | |
1684 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1685 | && insn_uses_reg (ip, | |
1686 | ((prev_insn.insn_opcode | |
1687 | >> MIPS16OP_SH_RY) | |
1688 | & MIPS16OP_MASK_RY), | |
1689 | MIPS16_REG)) | |
1690 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1691 | && insn_uses_reg (ip, | |
1692 | ((prev_insn.insn_opcode | |
1693 | >> MIPS16OP_SH_RZ) | |
1694 | & MIPS16OP_MASK_RZ), | |
1695 | MIPS16_REG)) | |
1696 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1697 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1698 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1699 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1700 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1701 | && insn_uses_reg (ip, | |
1702 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1703 | insn_opcode), | |
1704 | MIPS_GR_REG)))) | |
1849d646 ILT |
1705 | /* If the branch writes a register that the previous |
1706 | instruction sets, we can not swap (we know that | |
1707 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1708 | || (! mips16 |
1709 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1710 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1711 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1712 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1713 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1714 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1715 | & OP_MASK_RT) | |
1716 | == 31)))) | |
cc5703cd ILT |
1717 | || (! mips16 |
1718 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1719 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1720 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1721 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1722 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1723 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1724 | & OP_MASK_RD) | |
1725 | == 31)))) | |
cc5703cd ILT |
1726 | || (mips16 |
1727 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1728 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1729 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1730 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1731 | == RA)))) | |
becfe05e ILT |
1732 | /* If the branch writes a register that the previous |
1733 | instruction reads, we can not swap (we know that | |
1734 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1735 | || (! mips16 |
1736 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1737 | && insn_uses_reg (&prev_insn, |
1738 | ((ip->insn_opcode >> OP_SH_RD) | |
1739 | & OP_MASK_RD), | |
cc5703cd ILT |
1740 | MIPS_GR_REG)) |
1741 | || (! mips16 | |
1742 | && (pinfo & INSN_WRITE_GPR_31) | |
1743 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1744 | || (mips16 | |
1745 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1746 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1747 | /* If we are generating embedded PIC code, the branch |
1748 | might be expanded into a sequence which uses $at, so | |
1749 | we can't swap with an instruction which reads it. */ | |
1750 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1751 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1752 | /* If the previous previous instruction has a load |
1753 | delay, and sets a register that the branch reads, we | |
1754 | can not swap. */ | |
cc5703cd ILT |
1755 | || (! mips16 |
1756 | && mips_isa < 4 | |
d8a1c247 KR |
1757 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1758 | || (mips_isa < 2 | |
1759 | && (prev_prev_insn.insn_mo->pinfo | |
1760 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1761 | && insn_uses_reg (ip, |
1762 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1763 | & OP_MASK_RT), | |
cc5703cd | 1764 | MIPS_GR_REG)) |
d31a3f5e ILT |
1765 | /* If one instruction sets a condition code and the |
1766 | other one uses a condition code, we can not swap. */ | |
1767 | || ((pinfo & INSN_READ_COND_CODE) | |
1768 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1769 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1770 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1771 | /* If the previous instruction uses the PC, we can not | |
1772 | swap. */ | |
1773 | || (mips16 | |
1774 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1775 | /* If the previous instruction was extended, we can not | |
1776 | swap. */ | |
1777 | || (mips16 && prev_insn_extended) | |
1778 | /* If the previous instruction had a fixup in mips16 | |
1779 | mode, we can not swap. This normally means that the | |
1780 | previous instruction was a 4 byte branch anyhow. */ | |
1781 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1782 | { |
1783 | /* We could do even better for unconditional branches to | |
1784 | portions of this object file; we could pick up the | |
1785 | instruction at the destination, put it in the delay | |
1786 | slot, and bump the destination address. */ | |
1787 | emit_nop (); | |
1788 | /* Update the previous insn information. */ | |
1789 | prev_prev_insn = *ip; | |
1790 | prev_insn.insn_mo = &dummy_opcode; | |
1791 | } | |
1792 | else | |
1793 | { | |
becfe05e | 1794 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1795 | if (! mips16) |
1796 | { | |
1797 | char *prev_f; | |
1798 | char temp[4]; | |
1799 | ||
1800 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1801 | memcpy (temp, prev_f, 4); | |
1802 | memcpy (prev_f, f, 4); | |
1803 | memcpy (f, temp, 4); | |
1804 | if (prev_insn_fixp) | |
1805 | { | |
1806 | prev_insn_fixp->fx_frag = frag_now; | |
1807 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1808 | } | |
1809 | if (fixp) | |
1810 | { | |
1811 | fixp->fx_frag = prev_insn_frag; | |
1812 | fixp->fx_where = prev_insn_where; | |
1813 | } | |
1814 | } | |
1815 | else if (reloc_type > BFD_RELOC_UNUSED) | |
becfe05e | 1816 | { |
cc5703cd ILT |
1817 | char *prev_f; |
1818 | char temp[2]; | |
1819 | ||
1820 | /* We are in mips16 mode, and we have just created a | |
1821 | variant frag. We need to extract the old | |
1822 | instruction from the end of the previous frag, | |
1823 | and add it to a new frag. */ | |
1824 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1825 | memcpy (temp, prev_f, 2); | |
1826 | prev_insn_frag->fr_fix -= 2; | |
1827 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
1828 | { | |
1829 | assert (prev_insn_where == prev_insn_frag->fr_fix); | |
1830 | memcpy (prev_f, prev_f + 2, 2); | |
1831 | } | |
1832 | memcpy (frag_more (2), temp, 2); | |
becfe05e | 1833 | } |
cc5703cd | 1834 | else |
becfe05e | 1835 | { |
cc5703cd ILT |
1836 | char *prev_f; |
1837 | char temp[2]; | |
1838 | ||
1839 | assert (prev_insn_fixp == NULL); | |
1840 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1841 | memcpy (temp, prev_f, 2); | |
1842 | memcpy (prev_f, f, 2); | |
1843 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
1844 | memcpy (f, temp, 2); | |
1845 | else | |
1846 | { | |
1847 | memcpy (f, f + 2, 2); | |
1848 | memcpy (f + 2, temp, 2); | |
1849 | } | |
1850 | if (fixp) | |
1851 | { | |
1852 | fixp->fx_frag = prev_insn_frag; | |
1853 | fixp->fx_where = prev_insn_where; | |
1854 | } | |
becfe05e | 1855 | } |
cc5703cd | 1856 | |
becfe05e ILT |
1857 | /* Update the previous insn information; leave prev_insn |
1858 | unchanged. */ | |
1859 | prev_prev_insn = *ip; | |
1860 | } | |
1861 | prev_insn_is_delay_slot = 1; | |
1862 | ||
1863 | /* If that was an unconditional branch, forget the previous | |
1864 | insn information. */ | |
1aa6938e | 1865 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1866 | { |
1867 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1868 | prev_insn.insn_mo = &dummy_opcode; | |
1869 | } | |
a677feeb ILT |
1870 | |
1871 | prev_insn_fixp = NULL; | |
1872 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1873 | prev_insn_extended = 0; | |
becfe05e | 1874 | } |
1aa6938e | 1875 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1876 | { |
1877 | /* We don't yet optimize a branch likely. What we should do | |
1878 | is look at the target, copy the instruction found there | |
1879 | into the delay slot, and increment the branch to jump to | |
1880 | the next instruction. */ | |
1881 | emit_nop (); | |
1882 | /* Update the previous insn information. */ | |
1883 | prev_prev_insn = *ip; | |
1884 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
1885 | prev_insn_fixp = NULL; |
1886 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1887 | prev_insn_extended = 0; | |
8358c818 | 1888 | } |
becfe05e | 1889 | else |
670a50eb | 1890 | { |
becfe05e ILT |
1891 | /* Update the previous insn information. */ |
1892 | if (nops > 0) | |
1893 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1894 | else | |
1895 | prev_prev_insn = prev_insn; | |
1896 | prev_insn = *ip; | |
1897 | ||
1898 | /* Any time we see a branch, we always fill the delay slot | |
1899 | immediately; since this insn is not a branch, we know it | |
1900 | is not in a delay slot. */ | |
1901 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
1902 | |
1903 | prev_insn_fixp = fixp; | |
1904 | prev_insn_reloc_type = reloc_type; | |
1905 | if (mips16) | |
1906 | prev_insn_extended = (ip->use_extend | |
1907 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
1908 | } |
1909 | ||
4e95866e ILT |
1910 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1911 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1912 | prev_insn_frag = frag_now; |
1913 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
1914 | prev_insn_valid = 1; |
1915 | } | |
fbcfacb7 | 1916 | else if (place == NULL) |
a677feeb | 1917 | { |
fbcfacb7 | 1918 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
1919 | reordering, in order to determine the base address for mips16 |
1920 | PC relative relocs. */ | |
1921 | prev_insn = *ip; | |
1922 | prev_insn_reloc_type = reloc_type; | |
1923 | } | |
3d3c5039 | 1924 | |
becfe05e | 1925 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 1926 | mips_clear_insn_labels (); |
becfe05e ILT |
1927 | } |
1928 | ||
1929 | /* This function forgets that there was any previous instruction or | |
1930 | label. */ | |
1931 | ||
1932 | static void | |
1933 | mips_no_prev_insn () | |
1934 | { | |
1935 | prev_insn.insn_mo = &dummy_opcode; | |
1936 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1937 | prev_insn_valid = 0; | |
1938 | prev_insn_is_delay_slot = 0; | |
4e95866e | 1939 | prev_insn_unreordered = 0; |
cc5703cd | 1940 | prev_insn_extended = 0; |
a677feeb | 1941 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 1942 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 1943 | mips_clear_insn_labels (); |
becfe05e ILT |
1944 | } |
1945 | ||
1946 | /* This function must be called whenever we turn on noreorder or emit | |
1947 | something other than instructions. It inserts any NOPS which might | |
1948 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
1949 | kept for the previous instructions. The INSNS parameter is true if |
1950 | instructions are to follow. */ | |
becfe05e ILT |
1951 | |
1952 | static void | |
fbcfacb7 ILT |
1953 | mips_emit_delays (insns) |
1954 | boolean insns; | |
becfe05e ILT |
1955 | { |
1956 | if (! mips_noreorder) | |
1957 | { | |
1958 | int nop; | |
1959 | ||
1960 | nop = 0; | |
cc5703cd ILT |
1961 | if ((! mips16 |
1962 | && mips_isa < 4 | |
344a8d61 JSC |
1963 | && (! cop_interlocks |
1964 | && (prev_insn.insn_mo->pinfo | |
1965 | & (INSN_LOAD_COPROC_DELAY | |
1966 | | INSN_COPROC_MOVE_DELAY | |
1967 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 1968 | || (! interlocks |
b2b8c24e ILT |
1969 | && (prev_insn.insn_mo->pinfo |
1970 | & (INSN_READ_LO | |
1971 | | INSN_READ_HI))) | |
cc5703cd ILT |
1972 | || (! mips16 |
1973 | && mips_isa < 2 | |
8358c818 ILT |
1974 | && (prev_insn.insn_mo->pinfo |
1975 | & (INSN_LOAD_MEMORY_DELAY | |
1976 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1977 | { |
1978 | nop = 1; | |
cc5703cd ILT |
1979 | if ((! mips16 |
1980 | && mips_isa < 4 | |
344a8d61 JSC |
1981 | && (! cop_interlocks |
1982 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1983 | || (! interlocks |
b2b8c24e ILT |
1984 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1985 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1986 | emit_nop (); |
1987 | } | |
cc5703cd ILT |
1988 | else if ((! mips16 |
1989 | && mips_isa < 4 | |
344a8d61 JSC |
1990 | && (! cop_interlocks |
1991 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1992 | || (! interlocks |
b2b8c24e ILT |
1993 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1994 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1995 | nop = 1; |
1996 | if (nop) | |
670a50eb | 1997 | { |
fbcfacb7 ILT |
1998 | struct insn_label_list *l; |
1999 | ||
becfe05e | 2000 | emit_nop (); |
fbcfacb7 | 2001 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2002 | { |
fbcfacb7 ILT |
2003 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2004 | l->label->sy_frag = frag_now; | |
2005 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2006 | /* mips16 text labels are stored as odd. */ | |
2007 | if (mips16) | |
2008 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2009 | } |
3d3c5039 ILT |
2010 | } |
2011 | } | |
0221ddf7 | 2012 | |
fbcfacb7 ILT |
2013 | /* Mark instruction labels in mips16 mode. This permits the linker |
2014 | to handle them specially, such as generating jalx instructions | |
2015 | when needed. We also make them odd for the duration of the | |
2016 | assembly, in order to generate the right sort of code. We will | |
2017 | make them even in the adjust_symtab routine, while leaving them | |
2018 | marked. This is convenient for the debugger and the | |
2019 | disassembler. The linker knows to make them odd again. */ | |
2020 | if (mips16 && insns) | |
2021 | { | |
2022 | struct insn_label_list *l; | |
2023 | ||
2024 | for (l = insn_labels; l != NULL; l = l->next) | |
2025 | { | |
2026 | #ifdef S_SET_OTHER | |
2027 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2028 | S_SET_OTHER (l->label, STO_MIPS16); | |
2029 | #endif | |
2030 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2031 | ++l->label->sy_value.X_add_number; | |
2032 | } | |
2033 | } | |
2034 | ||
0221ddf7 | 2035 | mips_no_prev_insn (); |
3d3c5039 ILT |
2036 | } |
2037 | ||
670a50eb ILT |
2038 | /* Build an instruction created by a macro expansion. This is passed |
2039 | a pointer to the count of instructions created so far, an | |
2040 | expression, the name of the instruction to build, an operand format | |
2041 | string, and corresponding arguments. */ | |
2042 | ||
1dc1e798 | 2043 | #ifdef USE_STDARG |
3d3c5039 | 2044 | static void |
0dd2d296 ILT |
2045 | macro_build (char *place, |
2046 | int *counter, | |
670a50eb | 2047 | expressionS * ep, |
3d3c5039 ILT |
2048 | const char *name, |
2049 | const char *fmt, | |
2050 | ...) | |
1dc1e798 | 2051 | #else |
3d3c5039 | 2052 | static void |
0dd2d296 ILT |
2053 | macro_build (place, counter, ep, name, fmt, va_alist) |
2054 | char *place; | |
3d3c5039 ILT |
2055 | int *counter; |
2056 | expressionS *ep; | |
2057 | const char *name; | |
2058 | const char *fmt; | |
2059 | va_dcl | |
1dc1e798 | 2060 | #endif |
3d3c5039 | 2061 | { |
670a50eb ILT |
2062 | struct mips_cl_insn insn; |
2063 | bfd_reloc_code_real_type r; | |
2064 | va_list args; | |
3d3c5039 | 2065 | |
1dc1e798 | 2066 | #ifdef USE_STDARG |
670a50eb | 2067 | va_start (args, fmt); |
3d3c5039 | 2068 | #else |
670a50eb | 2069 | va_start (args); |
3d3c5039 ILT |
2070 | #endif |
2071 | ||
670a50eb ILT |
2072 | /* |
2073 | * If the macro is about to expand into a second instruction, | |
2074 | * print a warning if needed. We need to pass ip as a parameter | |
2075 | * to generate a better warning message here... | |
2076 | */ | |
0dd2d296 | 2077 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2078 | as_warn ("Macro instruction expanded into multiple instructions"); |
2079 | ||
0dd2d296 ILT |
2080 | if (place == NULL) |
2081 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2082 | |
cc5703cd ILT |
2083 | if (mips16) |
2084 | { | |
2085 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2086 | va_end (args); | |
2087 | return; | |
2088 | } | |
2089 | ||
670a50eb ILT |
2090 | r = BFD_RELOC_UNUSED; |
2091 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2092 | assert (insn.insn_mo); | |
2093 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2094 | ||
9226253a | 2095 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2096 | || insn.insn_mo->pinfo == INSN_MACRO |
2097 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2098 | && mips_isa < 2) | |
2099 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2100 | && mips_isa < 3) | |
2101 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2102 | && mips_isa < 4) | |
2103 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2104 | && ! mips_4650) | |
2105 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2106 | && ! mips_4010) | |
2107 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
2108 | && ! mips_4100)) | |
670a50eb ILT |
2109 | { |
2110 | ++insn.insn_mo; | |
2111 | assert (insn.insn_mo->name); | |
2112 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2113 | } |
670a50eb ILT |
2114 | insn.insn_opcode = insn.insn_mo->match; |
2115 | for (;;) | |
2116 | { | |
2117 | switch (*fmt++) | |
2118 | { | |
3d3c5039 | 2119 | case '\0': |
670a50eb | 2120 | break; |
3d3c5039 ILT |
2121 | |
2122 | case ',': | |
2123 | case '(': | |
2124 | case ')': | |
670a50eb | 2125 | continue; |
3d3c5039 ILT |
2126 | |
2127 | case 't': | |
2128 | case 'w': | |
918692a5 | 2129 | case 'E': |
670a50eb ILT |
2130 | insn.insn_opcode |= va_arg (args, int) << 16; |
2131 | continue; | |
3d3c5039 ILT |
2132 | |
2133 | case 'c': | |
2134 | case 'T': | |
2135 | case 'W': | |
670a50eb ILT |
2136 | insn.insn_opcode |= va_arg (args, int) << 16; |
2137 | continue; | |
3d3c5039 ILT |
2138 | |
2139 | case 'd': | |
918692a5 | 2140 | case 'G': |
670a50eb ILT |
2141 | insn.insn_opcode |= va_arg (args, int) << 11; |
2142 | continue; | |
3d3c5039 ILT |
2143 | |
2144 | case 'V': | |
2145 | case 'S': | |
670a50eb ILT |
2146 | insn.insn_opcode |= va_arg (args, int) << 11; |
2147 | continue; | |
3d3c5039 | 2148 | |
ff3a5c18 ILT |
2149 | case 'z': |
2150 | continue; | |
2151 | ||
3d3c5039 | 2152 | case '<': |
670a50eb ILT |
2153 | insn.insn_opcode |= va_arg (args, int) << 6; |
2154 | continue; | |
3d3c5039 ILT |
2155 | |
2156 | case 'D': | |
670a50eb ILT |
2157 | insn.insn_opcode |= va_arg (args, int) << 6; |
2158 | continue; | |
3d3c5039 | 2159 | |
918692a5 ILT |
2160 | case 'B': |
2161 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2162 | continue; | |
2163 | ||
3d3c5039 ILT |
2164 | case 'b': |
2165 | case 's': | |
2166 | case 'r': | |
2167 | case 'v': | |
670a50eb ILT |
2168 | insn.insn_opcode |= va_arg (args, int) << 21; |
2169 | continue; | |
3d3c5039 ILT |
2170 | |
2171 | case 'i': | |
2172 | case 'j': | |
2173 | case 'o': | |
9226253a | 2174 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2175 | assert (r == BFD_RELOC_MIPS_GPREL |
2176 | || r == BFD_RELOC_MIPS_LITERAL | |
2177 | || r == BFD_RELOC_LO16 | |
2178 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2179 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2180 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2181 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2182 | || (ep->X_op == O_subtract |
2183 | && now_seg == text_section | |
ecd4ca1c | 2184 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2185 | continue; |
3d3c5039 | 2186 | |
6e8dda9c | 2187 | case 'u': |
ecd4ca1c ILT |
2188 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2189 | assert (ep != NULL | |
2190 | && (ep->X_op == O_constant | |
2191 | || (ep->X_op == O_symbol | |
2192 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2193 | || r == BFD_RELOC_HI16 |
2194 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2195 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2196 | || (ep->X_op == O_subtract |
2197 | && now_seg == text_section | |
ecd4ca1c ILT |
2198 | && r == BFD_RELOC_PCREL_HI16_S))); |
2199 | if (ep->X_op == O_constant) | |
2200 | { | |
2201 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2202 | ep = NULL; | |
2203 | r = BFD_RELOC_UNUSED; | |
2204 | } | |
6e8dda9c ILT |
2205 | continue; |
2206 | ||
3d3c5039 | 2207 | case 'p': |
670a50eb ILT |
2208 | assert (ep != NULL); |
2209 | /* | |
2210 | * This allows macro() to pass an immediate expression for | |
2211 | * creating short branches without creating a symbol. | |
2212 | * Note that the expression still might come from the assembly | |
2213 | * input, in which case the value is not checked for range nor | |
2214 | * is a relocation entry generated (yuck). | |
2215 | */ | |
5ac34ac3 | 2216 | if (ep->X_op == O_constant) |
670a50eb ILT |
2217 | { |
2218 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2219 | ep = NULL; | |
2220 | } | |
2221 | else | |
2222 | r = BFD_RELOC_16_PCREL_S2; | |
2223 | continue; | |
3d3c5039 | 2224 | |
9226253a ILT |
2225 | case 'a': |
2226 | assert (ep != NULL); | |
2227 | r = BFD_RELOC_MIPS_JMP; | |
2228 | continue; | |
2229 | ||
3d3c5039 | 2230 | default: |
670a50eb | 2231 | internalError (); |
3d3c5039 | 2232 | } |
670a50eb | 2233 | break; |
3d3c5039 | 2234 | } |
670a50eb ILT |
2235 | va_end (args); |
2236 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2237 | ||
867a58b3 | 2238 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2239 | } |
2240 | ||
cc5703cd ILT |
2241 | static void |
2242 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2243 | char *place; | |
2244 | int *counter; | |
2245 | expressionS *ep; | |
2246 | const char *name; | |
2247 | const char *fmt; | |
2248 | va_list args; | |
2249 | { | |
2250 | struct mips_cl_insn insn; | |
2251 | bfd_reloc_code_real_type r; | |
2252 | ||
2253 | r = BFD_RELOC_UNUSED; | |
2254 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2255 | assert (insn.insn_mo); | |
2256 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2257 | ||
2258 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2259 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2260 | { | |
2261 | ++insn.insn_mo; | |
2262 | assert (insn.insn_mo->name); | |
2263 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2264 | } | |
2265 | ||
2266 | insn.insn_opcode = insn.insn_mo->match; | |
2267 | insn.use_extend = false; | |
2268 | ||
2269 | for (;;) | |
2270 | { | |
2271 | int c; | |
2272 | ||
2273 | c = *fmt++; | |
2274 | switch (c) | |
2275 | { | |
2276 | case '\0': | |
2277 | break; | |
2278 | ||
2279 | case ',': | |
2280 | case '(': | |
2281 | case ')': | |
2282 | continue; | |
2283 | ||
2284 | case 'y': | |
2285 | case 'w': | |
2286 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2287 | continue; | |
2288 | ||
2289 | case 'x': | |
2290 | case 'v': | |
2291 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2292 | continue; | |
2293 | ||
2294 | case 'z': | |
2295 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2296 | continue; | |
2297 | ||
2298 | case 'Z': | |
2299 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2300 | continue; | |
2301 | ||
2302 | case '0': | |
2303 | case 'S': | |
2304 | case 'P': | |
2305 | case 'R': | |
2306 | continue; | |
2307 | ||
2308 | case 'X': | |
2309 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2310 | continue; | |
2311 | ||
2312 | case 'Y': | |
2313 | { | |
2314 | int regno; | |
2315 | ||
2316 | regno = va_arg (args, int); | |
2317 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2318 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2319 | } | |
2320 | continue; | |
2321 | ||
2322 | case '<': | |
2323 | case '>': | |
2324 | case '4': | |
2325 | case '5': | |
2326 | case 'H': | |
2327 | case 'W': | |
2328 | case 'D': | |
2329 | case 'j': | |
2330 | case '8': | |
2331 | case 'V': | |
2332 | case 'C': | |
2333 | case 'U': | |
2334 | case 'k': | |
2335 | case 'K': | |
2336 | case 'p': | |
2337 | case 'q': | |
2338 | { | |
2339 | assert (ep != NULL); | |
2340 | ||
2341 | if (ep->X_op != O_constant) | |
2342 | r = BFD_RELOC_UNUSED + c; | |
2343 | else | |
2344 | { | |
15e69f98 ILT |
2345 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2346 | false, false, &insn.insn_opcode, | |
2347 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2348 | ep = NULL; |
2349 | r = BFD_RELOC_UNUSED; | |
2350 | } | |
2351 | } | |
2352 | continue; | |
2353 | ||
2354 | case '6': | |
2355 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2356 | continue; | |
2357 | } | |
2358 | ||
2359 | break; | |
2360 | } | |
2361 | ||
2362 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2363 | ||
2364 | append_insn (place, &insn, ep, r, false); | |
2365 | } | |
2366 | ||
3d3c5039 ILT |
2367 | /* |
2368 | * Generate a "lui" instruction. | |
2369 | */ | |
2370 | static void | |
0dd2d296 ILT |
2371 | macro_build_lui (place, counter, ep, regnum) |
2372 | char *place; | |
3d3c5039 ILT |
2373 | int *counter; |
2374 | expressionS *ep; | |
2375 | int regnum; | |
2376 | { | |
670a50eb ILT |
2377 | expressionS high_expr; |
2378 | struct mips_cl_insn insn; | |
2379 | bfd_reloc_code_real_type r; | |
2380 | CONST char *name = "lui"; | |
2381 | CONST char *fmt = "t,u"; | |
2382 | ||
cc5703cd ILT |
2383 | assert (! mips16); |
2384 | ||
0dd2d296 ILT |
2385 | if (place == NULL) |
2386 | high_expr = *ep; | |
2387 | else | |
2388 | { | |
2389 | high_expr.X_op = O_constant; | |
fb251650 | 2390 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2391 | } |
670a50eb | 2392 | |
5ac34ac3 | 2393 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2394 | { |
2395 | /* we can compute the instruction now without a relocation entry */ | |
2396 | if (high_expr.X_add_number & 0x8000) | |
2397 | high_expr.X_add_number += 0x10000; | |
2398 | high_expr.X_add_number = | |
2399 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2400 | r = BFD_RELOC_UNUSED; | |
2401 | } | |
2402 | else | |
0dd2d296 ILT |
2403 | { |
2404 | assert (ep->X_op == O_symbol); | |
2405 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2406 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2407 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2408 | r = BFD_RELOC_HI16_S; | |
2409 | } | |
670a50eb ILT |
2410 | |
2411 | /* | |
2412 | * If the macro is about to expand into a second instruction, | |
2413 | * print a warning if needed. We need to pass ip as a parameter | |
2414 | * to generate a better warning message here... | |
2415 | */ | |
0dd2d296 | 2416 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2417 | as_warn ("Macro instruction expanded into multiple instructions"); |
2418 | ||
0dd2d296 ILT |
2419 | if (place == NULL) |
2420 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2421 | |
2422 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2423 | assert (insn.insn_mo); | |
2424 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2425 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2426 | ||
0dd2d296 | 2427 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2428 | if (r == BFD_RELOC_UNUSED) |
2429 | { | |
2430 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2431 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2432 | } |
2433 | else | |
867a58b3 | 2434 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2435 | } |
2436 | ||
2437 | /* set_at() | |
2438 | * Generates code to set the $at register to true (one) | |
2439 | * if reg is less than the immediate expression. | |
2440 | */ | |
2441 | static void | |
6e8dda9c | 2442 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2443 | int *counter; |
2444 | int reg; | |
6e8dda9c | 2445 | int unsignedp; |
3d3c5039 | 2446 | { |
6e8dda9c | 2447 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2448 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2449 | unsignedp ? "sltiu" : "slti", |
9226253a | 2450 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2451 | else |
670a50eb | 2452 | { |
d8a1c247 | 2453 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2454 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2455 | unsignedp ? "sltu" : "slt", |
2456 | "d,v,t", AT, reg, AT); | |
670a50eb | 2457 | } |
3d3c5039 ILT |
2458 | } |
2459 | ||
6e8dda9c | 2460 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2461 | |
2462 | static void | |
19ed8960 | 2463 | check_absolute_expr (ip, ex) |
3d3c5039 | 2464 | struct mips_cl_insn *ip; |
19ed8960 | 2465 | expressionS *ex; |
3d3c5039 | 2466 | { |
19ed8960 | 2467 | if (ex->X_op != O_constant) |
670a50eb | 2468 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2469 | } |
2470 | ||
ff8716f5 JSC |
2471 | /* Count the leading zeroes by performing a binary chop. This is a |
2472 | bulky bit of source, but performance is a LOT better for the | |
2473 | majority of values than a simple loop to count the bits: | |
2474 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2475 | if ((v) & (1 << (31 - lcnt))) | |
2476 | break; | |
2477 | However it is not code size friendly, and the gain will drop a bit | |
2478 | on certain cached systems. | |
2479 | */ | |
2480 | #define COUNT_TOP_ZEROES(v) \ | |
2481 | (((v) & ~0xffff) == 0 \ | |
2482 | ? ((v) & ~0xff) == 0 \ | |
2483 | ? ((v) & ~0xf) == 0 \ | |
2484 | ? ((v) & ~0x3) == 0 \ | |
2485 | ? ((v) & ~0x1) == 0 \ | |
2486 | ? !(v) \ | |
2487 | ? 32 \ | |
2488 | : 31 \ | |
2489 | : 30 \ | |
2490 | : ((v) & ~0x7) == 0 \ | |
2491 | ? 29 \ | |
2492 | : 28 \ | |
2493 | : ((v) & ~0x3f) == 0 \ | |
2494 | ? ((v) & ~0x1f) == 0 \ | |
2495 | ? 27 \ | |
2496 | : 26 \ | |
2497 | : ((v) & ~0x7f) == 0 \ | |
2498 | ? 25 \ | |
2499 | : 24 \ | |
2500 | : ((v) & ~0xfff) == 0 \ | |
2501 | ? ((v) & ~0x3ff) == 0 \ | |
2502 | ? ((v) & ~0x1ff) == 0 \ | |
2503 | ? 23 \ | |
2504 | : 22 \ | |
2505 | : ((v) & ~0x7ff) == 0 \ | |
2506 | ? 21 \ | |
2507 | : 20 \ | |
2508 | : ((v) & ~0x3fff) == 0 \ | |
2509 | ? ((v) & ~0x1fff) == 0 \ | |
2510 | ? 19 \ | |
2511 | : 18 \ | |
2512 | : ((v) & ~0x7fff) == 0 \ | |
2513 | ? 17 \ | |
2514 | : 16 \ | |
2515 | : ((v) & ~0xffffff) == 0 \ | |
2516 | ? ((v) & ~0xfffff) == 0 \ | |
2517 | ? ((v) & ~0x3ffff) == 0 \ | |
2518 | ? ((v) & ~0x1ffff) == 0 \ | |
2519 | ? 15 \ | |
2520 | : 14 \ | |
2521 | : ((v) & ~0x7ffff) == 0 \ | |
2522 | ? 13 \ | |
2523 | : 12 \ | |
2524 | : ((v) & ~0x3fffff) == 0 \ | |
2525 | ? ((v) & ~0x1fffff) == 0 \ | |
2526 | ? 11 \ | |
2527 | : 10 \ | |
2528 | : ((v) & ~0x7fffff) == 0 \ | |
2529 | ? 9 \ | |
2530 | : 8 \ | |
2531 | : ((v) & ~0xfffffff) == 0 \ | |
2532 | ? ((v) & ~0x3ffffff) == 0 \ | |
2533 | ? ((v) & ~0x1ffffff) == 0 \ | |
2534 | ? 7 \ | |
2535 | : 6 \ | |
2536 | : ((v) & ~0x7ffffff) == 0 \ | |
2537 | ? 5 \ | |
2538 | : 4 \ | |
2539 | : ((v) & ~0x3fffffff) == 0 \ | |
2540 | ? ((v) & ~0x1fffffff) == 0 \ | |
2541 | ? 3 \ | |
2542 | : 2 \ | |
2543 | : ((v) & ~0x7fffffff) == 0 \ | |
2544 | ? 1 \ | |
2545 | : 0) | |
2546 | ||
3d3c5039 ILT |
2547 | /* load_register() |
2548 | * This routine generates the least number of instructions neccessary to load | |
2549 | * an absolute expression value into a register. | |
2550 | */ | |
2551 | static void | |
d8a1c247 | 2552 | load_register (counter, reg, ep, dbl) |
670a50eb | 2553 | int *counter; |
670a50eb ILT |
2554 | int reg; |
2555 | expressionS *ep; | |
d8a1c247 | 2556 | int dbl; |
3d3c5039 | 2557 | { |
c36a90ef ILT |
2558 | int freg; |
2559 | expressionS hi32, lo32; | |
847a01cd ILT |
2560 | |
2561 | if (ep->X_op != O_big) | |
6e8dda9c | 2562 | { |
847a01cd | 2563 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2564 | if (ep->X_add_number < 0x8000 |
2565 | && (ep->X_add_number >= 0 | |
2566 | || (ep->X_add_number >= -0x8000 | |
2567 | && (! dbl | |
2568 | || ! ep->X_unsigned | |
2569 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2570 | { |
2571 | /* We can handle 16 bit signed values with an addiu to | |
2572 | $zero. No need to ever use daddiu here, since $zero and | |
2573 | the result are always correct in 32 bit mode. */ | |
2574 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2575 | (int) BFD_RELOC_LO16); | |
2576 | return; | |
2577 | } | |
2578 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2579 | { | |
2580 | /* We can handle 16 bit unsigned values with an ori to | |
2581 | $zero. */ | |
2582 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2583 | (int) BFD_RELOC_LO16); | |
2584 | return; | |
2585 | } | |
98bfd087 ILT |
2586 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2587 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2588 | == ~ (offsetT) 0x7fffffff)) | |
2589 | && (! dbl | |
2590 | || ! ep->X_unsigned | |
2591 | || sizeof (ep->X_add_number) > 4 | |
2592 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2593 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2594 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2595 | { |
2596 | /* 32 bit values require an lui. */ | |
2597 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2598 | (int) BFD_RELOC_HI16); | |
2599 | if ((ep->X_add_number & 0xffff) != 0) | |
2600 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2601 | (int) BFD_RELOC_LO16); | |
2602 | return; | |
2603 | } | |
6e8dda9c | 2604 | } |
847a01cd ILT |
2605 | |
2606 | /* The value is larger than 32 bits. */ | |
2607 | ||
2608 | if (mips_isa < 3) | |
670a50eb | 2609 | { |
6e8dda9c | 2610 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2611 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2612 | (int) BFD_RELOC_LO16); |
847a01cd | 2613 | return; |
6e8dda9c | 2614 | } |
6e8dda9c | 2615 | |
847a01cd ILT |
2616 | if (ep->X_op != O_big) |
2617 | { | |
6e8dda9c | 2618 | hi32 = *ep; |
c36a90ef ILT |
2619 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2620 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2621 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2622 | lo32 = *ep; |
2623 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2624 | } |
847a01cd ILT |
2625 | else |
2626 | { | |
2627 | assert (ep->X_add_number > 2); | |
2628 | if (ep->X_add_number == 3) | |
2629 | generic_bignum[3] = 0; | |
2630 | else if (ep->X_add_number > 4) | |
2631 | as_bad ("Number larger than 64 bits"); | |
2632 | lo32.X_op = O_constant; | |
2633 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2634 | hi32.X_op = O_constant; | |
2635 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2636 | } | |
2637 | ||
d8a1c247 KR |
2638 | if (hi32.X_add_number == 0) |
2639 | freg = 0; | |
2640 | else | |
2641 | { | |
c36a90ef ILT |
2642 | int shift, bit; |
2643 | unsigned long hi, lo; | |
2644 | ||
fb251650 ILT |
2645 | if (hi32.X_add_number == 0xffffffff) |
2646 | { | |
2647 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2648 | { | |
c36a90ef ILT |
2649 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2650 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2651 | return; |
2652 | } | |
2653 | if (lo32.X_add_number & 0x80000000) | |
2654 | { | |
2655 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2656 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2657 | if (lo32.X_add_number & 0xffff) |
2658 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2659 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2660 | return; |
2661 | } | |
2662 | } | |
ff8716f5 | 2663 | |
c36a90ef ILT |
2664 | /* Check for 16bit shifted constant. We know that hi32 is |
2665 | non-zero, so start the mask on the first bit of the hi32 | |
2666 | value. */ | |
ff8716f5 JSC |
2667 | shift = 17; |
2668 | do | |
2669 | { | |
c36a90ef ILT |
2670 | unsigned long himask, lomask; |
2671 | ||
2672 | if (shift < 32) | |
2673 | { | |
2674 | himask = 0xffff >> (32 - shift); | |
2675 | lomask = (0xffff << shift) & 0xffffffff; | |
2676 | } | |
2677 | else | |
2678 | { | |
2679 | himask = 0xffff << (shift - 32); | |
2680 | lomask = 0; | |
2681 | } | |
2682 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2683 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2684 | { | |
2685 | expressionS tmp; | |
2686 | ||
2687 | tmp.X_op = O_constant; | |
2688 | if (shift < 32) | |
2689 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2690 | | (lo32.X_add_number >> shift)); | |
2691 | else | |
2692 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2693 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2694 | (int) BFD_RELOC_LO16); | |
2695 | macro_build ((char *) NULL, counter, NULL, | |
2696 | (shift >= 32) ? "dsll32" : "dsll", | |
2697 | "d,w,<", reg, reg, | |
2698 | (shift >= 32) ? shift - 32 : shift); | |
2699 | return; | |
2700 | } | |
ff8716f5 JSC |
2701 | shift++; |
2702 | } while (shift <= (64 - 16)); | |
2703 | ||
c36a90ef ILT |
2704 | /* Find the bit number of the lowest one bit, and store the |
2705 | shifted value in hi/lo. */ | |
2706 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2707 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2708 | if (lo != 0) | |
2709 | { | |
2710 | bit = 0; | |
2711 | while ((lo & 1) == 0) | |
2712 | { | |
2713 | lo >>= 1; | |
2714 | ++bit; | |
2715 | } | |
2716 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2717 | hi >>= bit; | |
2718 | } | |
2719 | else | |
2720 | { | |
2721 | bit = 32; | |
2722 | while ((hi & 1) == 0) | |
2723 | { | |
2724 | hi >>= 1; | |
2725 | ++bit; | |
2726 | } | |
2727 | lo = hi; | |
2728 | hi = 0; | |
2729 | } | |
2730 | ||
2731 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
2732 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
2733 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 2734 | { |
c36a90ef | 2735 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
2736 | if (shift != 0) |
2737 | { | |
c36a90ef ILT |
2738 | expressionS tmp; |
2739 | ||
2740 | /* This instruction will set the register to be all | |
2741 | ones. */ | |
ff8716f5 | 2742 | tmp.X_op = O_constant; |
c36a90ef ILT |
2743 | tmp.X_add_number = (offsetT) -1; |
2744 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
2745 | reg, 0, (int) BFD_RELOC_LO16); | |
2746 | if (bit != 0) | |
ff8716f5 | 2747 | { |
c36a90ef | 2748 | bit += shift; |
ff8716f5 | 2749 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 2750 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 2751 | "d,w,<", reg, reg, |
c36a90ef | 2752 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 2753 | } |
c36a90ef ILT |
2754 | macro_build ((char *) NULL, counter, NULL, |
2755 | (shift >= 32) ? "dsrl32" : "dsrl", | |
2756 | "d,w,<", reg, reg, | |
2757 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
2758 | return; |
2759 | } | |
2760 | } | |
c36a90ef ILT |
2761 | |
2762 | /* Sign extend hi32 before calling load_register, because we can | |
2763 | generally get better code when we load a sign extended value. */ | |
2764 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2765 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
2766 | load_register (counter, reg, &hi32, 0); |
2767 | freg = reg; | |
2768 | } | |
847a01cd | 2769 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2770 | { |
2771 | if (freg != 0) | |
2772 | { | |
2773 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2774 | freg, 0); | |
2775 | freg = reg; | |
2776 | } | |
2777 | } | |
847a01cd ILT |
2778 | else |
2779 | { | |
2780 | expressionS mid16; | |
2781 | ||
fb251650 ILT |
2782 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2783 | { | |
2784 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2785 | (int) BFD_RELOC_HI16); | |
2786 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2787 | reg, 0); |
fb251650 ILT |
2788 | return; |
2789 | } | |
2790 | ||
d8a1c247 KR |
2791 | if (freg != 0) |
2792 | { | |
2793 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2794 | freg, 16); | |
2795 | freg = reg; | |
2796 | } | |
847a01cd ILT |
2797 | mid16 = lo32; |
2798 | mid16.X_add_number >>= 16; | |
2799 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2800 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2801 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2802 | reg, 16); | |
d8a1c247 | 2803 | freg = reg; |
847a01cd ILT |
2804 | } |
2805 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 2806 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 2807 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
2808 | } |
2809 | ||
0dd2d296 ILT |
2810 | /* Load an address into a register. */ |
2811 | ||
2812 | static void | |
2813 | load_address (counter, reg, ep) | |
2814 | int *counter; | |
2815 | int reg; | |
2816 | expressionS *ep; | |
2817 | { | |
2818 | char *p; | |
2819 | ||
2820 | if (ep->X_op != O_constant | |
2821 | && ep->X_op != O_symbol) | |
2822 | { | |
2823 | as_bad ("expression too complex"); | |
2824 | ep->X_op = O_constant; | |
2825 | } | |
2826 | ||
2827 | if (ep->X_op == O_constant) | |
d9aba805 | 2828 | { |
d8a1c247 | 2829 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
2830 | return; |
2831 | } | |
2832 | ||
2833 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
2834 | { |
2835 | /* If this is a reference to a GP relative symbol, we want | |
2836 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2837 | Otherwise we want | |
04cb3372 | 2838 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
2839 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
2840 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
2841 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
2842 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
2843 | p = NULL; |
2844 | else | |
2845 | { | |
8ea7f4e8 | 2846 | frag_grow (20); |
0dd2d296 ILT |
2847 | macro_build ((char *) NULL, counter, ep, |
2848 | mips_isa < 3 ? "addiu" : "daddiu", | |
2849 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2850 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 2851 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
2852 | ep->X_add_symbol, (long) 0, (char *) NULL); |
2853 | } | |
2854 | macro_build_lui (p, counter, ep, reg); | |
2855 | if (p != NULL) | |
2856 | p += 4; | |
2857 | macro_build (p, counter, ep, | |
2858 | mips_isa < 3 ? "addiu" : "daddiu", | |
2859 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2860 | } | |
fb251650 | 2861 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2862 | { |
2863 | expressionS ex; | |
2864 | ||
2865 | /* If this is a reference to an external symbol, we want | |
2866 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2867 | Otherwise we want | |
2868 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2869 | nop | |
2870 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 2871 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
2872 | ex.X_add_number = ep->X_add_number; |
2873 | ep->X_add_number = 0; | |
8ea7f4e8 | 2874 | frag_grow (20); |
0dd2d296 ILT |
2875 | macro_build ((char *) NULL, counter, ep, |
2876 | mips_isa < 3 ? "lw" : "ld", | |
2877 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2878 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
2879 | p = frag_var (rs_machine_dependent, 4, 0, | |
2880 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
2881 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2882 | macro_build (p, counter, ep, | |
2883 | mips_isa < 3 ? "addiu" : "daddiu", | |
2884 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2885 | if (ex.X_add_number != 0) | |
2886 | { | |
2887 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2888 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2889 | ex.X_op = O_constant; | |
fb251650 ILT |
2890 | macro_build ((char *) NULL, counter, &ex, |
2891 | mips_isa < 3 ? "addiu" : "daddiu", | |
2892 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2893 | } | |
2894 | } | |
2895 | else if (mips_pic == SVR4_PIC) | |
2896 | { | |
2897 | expressionS ex; | |
2898 | int off; | |
2899 | ||
2900 | /* This is the large GOT case. If this is a reference to an | |
2901 | external symbol, we want | |
2902 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2903 | addu $reg,$reg,$gp | |
2904 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2905 | Otherwise, for a reference to a local symbol, we want | |
2906 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2907 | nop | |
2908 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2909 | If there is a constant, it must be added in after. */ | |
2910 | ex.X_add_number = ep->X_add_number; | |
2911 | ep->X_add_number = 0; | |
2912 | if (reg_needs_delay (GP)) | |
2913 | off = 4; | |
2914 | else | |
2915 | off = 0; | |
2916 | frag_grow (32); | |
2917 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2918 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2919 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2920 | mips_isa < 3 ? "addu" : "daddu", | |
2921 | "d,v,t", reg, reg, GP); | |
2922 | macro_build ((char *) NULL, counter, ep, | |
2923 | mips_isa < 3 ? "lw" : "ld", | |
2924 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2925 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
2926 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
2927 | mips_warn_about_macros), | |
2928 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2929 | if (off > 0) | |
2930 | { | |
2931 | /* We need a nop before loading from $gp. This special | |
2932 | check is required because the lui which starts the main | |
2933 | instruction stream does not refer to $gp, and so will not | |
2934 | insert the nop which may be required. */ | |
2935 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2936 | p += 4; | |
2937 | } | |
2938 | macro_build (p, counter, ep, | |
2939 | mips_isa < 3 ? "lw" : "ld", | |
2940 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2941 | p += 4; | |
2942 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2943 | p += 4; | |
2944 | macro_build (p, counter, ep, | |
2945 | mips_isa < 3 ? "addiu" : "daddiu", | |
2946 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2947 | if (ex.X_add_number != 0) | |
2948 | { | |
2949 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2950 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2951 | ex.X_op = O_constant; | |
2952 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
2953 | mips_isa < 3 ? "addiu" : "daddiu", |
2954 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2955 | } | |
d9aba805 ILT |
2956 | } |
2957 | else if (mips_pic == EMBEDDED_PIC) | |
2958 | { | |
2959 | /* We always do | |
2960 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2961 | */ | |
2962 | macro_build ((char *) NULL, counter, ep, | |
2963 | mips_isa < 3 ? "addiu" : "daddiu", | |
2964 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2965 | } | |
2966 | else | |
2967 | abort (); | |
0dd2d296 ILT |
2968 | } |
2969 | ||
3d3c5039 ILT |
2970 | /* |
2971 | * Build macros | |
2972 | * This routine implements the seemingly endless macro or synthesized | |
2973 | * instructions and addressing modes in the mips assembly language. Many | |
2974 | * of these macros are simple and are similar to each other. These could | |
2975 | * probably be handled by some kind of table or grammer aproach instead of | |
2976 | * this verbose method. Others are not simple macros but are more like | |
2977 | * optimizing code generation. | |
2978 | * One interesting optimization is when several store macros appear | |
2979 | * consecutivly that would load AT with the upper half of the same address. | |
2980 | * The ensuing load upper instructions are ommited. This implies some kind | |
2981 | * of global optimization. We currently only optimize within a single macro. | |
2982 | * For many of the load and store macros if the address is specified as a | |
2983 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
2984 | * first load register 'at' with zero and use it as the base register. The | |
2985 | * mips assembler simply uses register $zero. Just one tiny optimization | |
2986 | * we're missing. | |
2987 | */ | |
2988 | static void | |
2989 | macro (ip) | |
2990 | struct mips_cl_insn *ip; | |
2991 | { | |
670a50eb ILT |
2992 | register int treg, sreg, dreg, breg; |
2993 | int tempreg; | |
2994 | int mask; | |
2995 | int icnt = 0; | |
2996 | int used_at; | |
670a50eb ILT |
2997 | expressionS expr1; |
2998 | const char *s; | |
8358c818 | 2999 | const char *s2; |
670a50eb | 3000 | const char *fmt; |
8358c818 ILT |
3001 | int likely = 0; |
3002 | int dbl = 0; | |
3003 | int coproc = 0; | |
b2b8c24e | 3004 | int lr = 0; |
6e8dda9c | 3005 | offsetT maxnum; |
adcf2b9d | 3006 | int off; |
9226253a | 3007 | bfd_reloc_code_real_type r; |
0dd2d296 | 3008 | char *p; |
55933a58 | 3009 | int hold_mips_optimize; |
670a50eb | 3010 | |
cc5703cd ILT |
3011 | assert (! mips16); |
3012 | ||
670a50eb ILT |
3013 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3014 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3015 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3016 | mask = ip->insn_mo->mask; | |
3017 | ||
5ac34ac3 ILT |
3018 | expr1.X_op = O_constant; |
3019 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3020 | expr1.X_add_symbol = NULL; |
3021 | expr1.X_add_number = 1; | |
3022 | ||
3023 | switch (mask) | |
3024 | { | |
6e8dda9c ILT |
3025 | case M_DABS: |
3026 | dbl = 1; | |
3d3c5039 | 3027 | case M_ABS: |
6e8dda9c ILT |
3028 | /* bgez $a0,.+12 |
3029 | move v0,$a0 | |
3030 | sub v0,$zero,$a0 | |
3031 | */ | |
3d3c5039 | 3032 | |
fbcfacb7 | 3033 | mips_emit_delays (true); |
becfe05e | 3034 | ++mips_noreorder; |
0dd2d296 | 3035 | mips_any_noreorder = 1; |
3d3c5039 | 3036 | |
670a50eb | 3037 | expr1.X_add_number = 8; |
0dd2d296 | 3038 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3039 | if (dreg == sreg) |
0dd2d296 | 3040 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3041 | else |
0dd2d296 ILT |
3042 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3043 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3044 | dbl ? "dsub" : "sub", |
3045 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3046 | |
becfe05e | 3047 | --mips_noreorder; |
670a50eb | 3048 | return; |
3d3c5039 ILT |
3049 | |
3050 | case M_ADD_I: | |
8358c818 ILT |
3051 | s = "addi"; |
3052 | s2 = "add"; | |
3053 | goto do_addi; | |
3d3c5039 | 3054 | case M_ADDU_I: |
8358c818 ILT |
3055 | s = "addiu"; |
3056 | s2 = "addu"; | |
3057 | goto do_addi; | |
3058 | case M_DADD_I: | |
6e8dda9c | 3059 | dbl = 1; |
8358c818 ILT |
3060 | s = "daddi"; |
3061 | s2 = "dadd"; | |
3062 | goto do_addi; | |
3063 | case M_DADDU_I: | |
6e8dda9c | 3064 | dbl = 1; |
8358c818 ILT |
3065 | s = "daddiu"; |
3066 | s2 = "daddu"; | |
3067 | do_addi: | |
6e8dda9c | 3068 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3069 | { |
0dd2d296 | 3070 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3071 | (int) BFD_RELOC_LO16); |
670a50eb | 3072 | return; |
3d3c5039 | 3073 | } |
d8a1c247 | 3074 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3075 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3076 | break; |
3d3c5039 ILT |
3077 | |
3078 | case M_AND_I: | |
6e8dda9c ILT |
3079 | s = "andi"; |
3080 | s2 = "and"; | |
3081 | goto do_bit; | |
3d3c5039 | 3082 | case M_OR_I: |
6e8dda9c ILT |
3083 | s = "ori"; |
3084 | s2 = "or"; | |
3085 | goto do_bit; | |
3d3c5039 | 3086 | case M_NOR_I: |
6e8dda9c ILT |
3087 | s = ""; |
3088 | s2 = "nor"; | |
3089 | goto do_bit; | |
3d3c5039 | 3090 | case M_XOR_I: |
6e8dda9c ILT |
3091 | s = "xori"; |
3092 | s2 = "xor"; | |
3093 | do_bit: | |
3094 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3095 | { |
6e8dda9c | 3096 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3097 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3098 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3099 | else |
670a50eb | 3100 | { |
0dd2d296 ILT |
3101 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3102 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3103 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3104 | treg, treg, 0); |
3d3c5039 | 3105 | } |
6e8dda9c | 3106 | return; |
3d3c5039 | 3107 | } |
6e8dda9c | 3108 | |
d8a1c247 | 3109 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3110 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3111 | break; |
3d3c5039 ILT |
3112 | |
3113 | case M_BEQ_I: | |
8358c818 ILT |
3114 | s = "beq"; |
3115 | goto beq_i; | |
3116 | case M_BEQL_I: | |
3117 | s = "beql"; | |
3118 | likely = 1; | |
3119 | goto beq_i; | |
3d3c5039 | 3120 | case M_BNE_I: |
8358c818 ILT |
3121 | s = "bne"; |
3122 | goto beq_i; | |
3123 | case M_BNEL_I: | |
3124 | s = "bnel"; | |
3125 | likely = 1; | |
3126 | beq_i: | |
670a50eb ILT |
3127 | if (imm_expr.X_add_number == 0) |
3128 | { | |
0dd2d296 ILT |
3129 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3130 | 0); | |
670a50eb ILT |
3131 | return; |
3132 | } | |
d8a1c247 | 3133 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3134 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3135 | break; |
3d3c5039 | 3136 | |
8358c818 ILT |
3137 | case M_BGEL: |
3138 | likely = 1; | |
3d3c5039 | 3139 | case M_BGE: |
670a50eb ILT |
3140 | if (treg == 0) |
3141 | { | |
0dd2d296 | 3142 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3143 | likely ? "bgezl" : "bgez", |
3144 | "s,p", sreg); | |
670a50eb | 3145 | return; |
3d3c5039 | 3146 | } |
9a7d824a ILT |
3147 | if (sreg == 0) |
3148 | { | |
0dd2d296 | 3149 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3150 | likely ? "blezl" : "blez", |
3151 | "s,p", treg); | |
9a7d824a ILT |
3152 | return; |
3153 | } | |
0dd2d296 ILT |
3154 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3155 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3156 | likely ? "beql" : "beq", |
3157 | "s,t,p", AT, 0); | |
670a50eb | 3158 | break; |
3d3c5039 | 3159 | |
8358c818 ILT |
3160 | case M_BGTL_I: |
3161 | likely = 1; | |
3d3c5039 | 3162 | case M_BGT_I: |
9a7d824a | 3163 | /* check for > max integer */ |
6e8dda9c ILT |
3164 | maxnum = 0x7fffffff; |
3165 | if (mips_isa >= 3) | |
3166 | { | |
3167 | maxnum <<= 16; | |
3168 | maxnum |= 0xffff; | |
3169 | maxnum <<= 16; | |
3170 | maxnum |= 0xffff; | |
3171 | } | |
7b777690 ILT |
3172 | if (imm_expr.X_add_number >= maxnum |
3173 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3174 | { |
3175 | do_false: | |
3176 | /* result is always false */ | |
8358c818 ILT |
3177 | if (! likely) |
3178 | { | |
3179 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3180 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3181 | } |
3182 | else | |
3183 | { | |
3184 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3185 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3186 | "s,t,p", 0, 0); | |
8358c818 | 3187 | } |
9a7d824a ILT |
3188 | return; |
3189 | } | |
670a50eb ILT |
3190 | imm_expr.X_add_number++; |
3191 | /* FALLTHROUGH */ | |
3d3c5039 | 3192 | case M_BGE_I: |
8358c818 ILT |
3193 | case M_BGEL_I: |
3194 | if (mask == M_BGEL_I) | |
3195 | likely = 1; | |
670a50eb ILT |
3196 | if (imm_expr.X_add_number == 0) |
3197 | { | |
0dd2d296 | 3198 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3199 | likely ? "bgezl" : "bgez", |
3200 | "s,p", sreg); | |
670a50eb | 3201 | return; |
3d3c5039 | 3202 | } |
670a50eb ILT |
3203 | if (imm_expr.X_add_number == 1) |
3204 | { | |
0dd2d296 | 3205 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3206 | likely ? "bgtzl" : "bgtz", |
3207 | "s,p", sreg); | |
670a50eb | 3208 | return; |
3d3c5039 | 3209 | } |
6e8dda9c ILT |
3210 | maxnum = 0x7fffffff; |
3211 | if (mips_isa >= 3) | |
3212 | { | |
3213 | maxnum <<= 16; | |
3214 | maxnum |= 0xffff; | |
3215 | maxnum <<= 16; | |
3216 | maxnum |= 0xffff; | |
3217 | } | |
3218 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3219 | if (imm_expr.X_add_number <= maxnum |
3220 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3221 | { |
3222 | do_true: | |
3223 | /* result is always true */ | |
3224 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3225 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3226 | return; |
3227 | } | |
6e8dda9c | 3228 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3229 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3230 | likely ? "beql" : "beq", |
3231 | "s,t,p", AT, 0); | |
670a50eb | 3232 | break; |
3d3c5039 | 3233 | |
8358c818 ILT |
3234 | case M_BGEUL: |
3235 | likely = 1; | |
3d3c5039 | 3236 | case M_BGEU: |
670a50eb | 3237 | if (treg == 0) |
9a7d824a ILT |
3238 | goto do_true; |
3239 | if (sreg == 0) | |
670a50eb | 3240 | { |
0dd2d296 | 3241 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3242 | likely ? "beql" : "beq", |
3243 | "s,t,p", 0, treg); | |
670a50eb | 3244 | return; |
3d3c5039 | 3245 | } |
0dd2d296 ILT |
3246 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3247 | treg); | |
3248 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3249 | likely ? "beql" : "beq", |
3250 | "s,t,p", AT, 0); | |
670a50eb | 3251 | break; |
3d3c5039 | 3252 | |
8358c818 ILT |
3253 | case M_BGTUL_I: |
3254 | likely = 1; | |
9a7d824a | 3255 | case M_BGTU_I: |
6e8dda9c | 3256 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3257 | goto do_false; |
3258 | imm_expr.X_add_number++; | |
3259 | /* FALLTHROUGH */ | |
3d3c5039 | 3260 | case M_BGEU_I: |
8358c818 ILT |
3261 | case M_BGEUL_I: |
3262 | if (mask == M_BGEUL_I) | |
3263 | likely = 1; | |
670a50eb | 3264 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3265 | goto do_true; |
670a50eb ILT |
3266 | if (imm_expr.X_add_number == 1) |
3267 | { | |
0dd2d296 | 3268 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3269 | likely ? "bnel" : "bne", |
3270 | "s,t,p", sreg, 0); | |
670a50eb | 3271 | return; |
3d3c5039 | 3272 | } |
6e8dda9c | 3273 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3274 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3275 | likely ? "beql" : "beq", |
3276 | "s,t,p", AT, 0); | |
670a50eb | 3277 | break; |
3d3c5039 | 3278 | |
8358c818 ILT |
3279 | case M_BGTL: |
3280 | likely = 1; | |
3d3c5039 | 3281 | case M_BGT: |
670a50eb ILT |
3282 | if (treg == 0) |
3283 | { | |
0dd2d296 | 3284 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3285 | likely ? "bgtzl" : "bgtz", |
3286 | "s,p", sreg); | |
670a50eb | 3287 | return; |
3d3c5039 | 3288 | } |
9a7d824a ILT |
3289 | if (sreg == 0) |
3290 | { | |
0dd2d296 | 3291 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3292 | likely ? "bltzl" : "bltz", |
3293 | "s,p", treg); | |
9a7d824a ILT |
3294 | return; |
3295 | } | |
0dd2d296 ILT |
3296 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3297 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3298 | likely ? "bnel" : "bne", |
3299 | "s,t,p", AT, 0); | |
670a50eb | 3300 | break; |
3d3c5039 | 3301 | |
8358c818 ILT |
3302 | case M_BGTUL: |
3303 | likely = 1; | |
3d3c5039 | 3304 | case M_BGTU: |
670a50eb ILT |
3305 | if (treg == 0) |
3306 | { | |
0dd2d296 | 3307 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3308 | likely ? "bnel" : "bne", |
3309 | "s,t,p", sreg, 0); | |
670a50eb | 3310 | return; |
3d3c5039 | 3311 | } |
9a7d824a ILT |
3312 | if (sreg == 0) |
3313 | goto do_false; | |
0dd2d296 ILT |
3314 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3315 | sreg); | |
3316 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3317 | likely ? "bnel" : "bne", |
3318 | "s,t,p", AT, 0); | |
670a50eb | 3319 | break; |
3d3c5039 | 3320 | |
8358c818 ILT |
3321 | case M_BLEL: |
3322 | likely = 1; | |
3d3c5039 | 3323 | case M_BLE: |
670a50eb ILT |
3324 | if (treg == 0) |
3325 | { | |
0dd2d296 | 3326 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3327 | likely ? "blezl" : "blez", |
3328 | "s,p", sreg); | |
670a50eb ILT |
3329 | return; |
3330 | } | |
9a7d824a ILT |
3331 | if (sreg == 0) |
3332 | { | |
0dd2d296 | 3333 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3334 | likely ? "bgezl" : "bgez", |
3335 | "s,p", treg); | |
9a7d824a ILT |
3336 | return; |
3337 | } | |
0dd2d296 ILT |
3338 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3339 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3340 | likely ? "beql" : "beq", |
3341 | "s,t,p", AT, 0); | |
670a50eb | 3342 | break; |
3d3c5039 | 3343 | |
8358c818 ILT |
3344 | case M_BLEL_I: |
3345 | likely = 1; | |
3d3c5039 | 3346 | case M_BLE_I: |
6e8dda9c ILT |
3347 | maxnum = 0x7fffffff; |
3348 | if (mips_isa >= 3) | |
3349 | { | |
3350 | maxnum <<= 16; | |
3351 | maxnum |= 0xffff; | |
3352 | maxnum <<= 16; | |
3353 | maxnum |= 0xffff; | |
3354 | } | |
7b777690 ILT |
3355 | if (imm_expr.X_add_number >= maxnum |
3356 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3357 | goto do_true; |
3358 | imm_expr.X_add_number++; | |
3359 | /* FALLTHROUGH */ | |
9a7d824a | 3360 | case M_BLT_I: |
8358c818 ILT |
3361 | case M_BLTL_I: |
3362 | if (mask == M_BLTL_I) | |
3363 | likely = 1; | |
670a50eb ILT |
3364 | if (imm_expr.X_add_number == 0) |
3365 | { | |
0dd2d296 | 3366 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3367 | likely ? "bltzl" : "bltz", |
3368 | "s,p", sreg); | |
670a50eb ILT |
3369 | return; |
3370 | } | |
9a7d824a | 3371 | if (imm_expr.X_add_number == 1) |
670a50eb | 3372 | { |
0dd2d296 | 3373 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3374 | likely ? "blezl" : "blez", |
3375 | "s,p", sreg); | |
670a50eb ILT |
3376 | return; |
3377 | } | |
6e8dda9c | 3378 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3379 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3380 | likely ? "bnel" : "bne", |
3381 | "s,t,p", AT, 0); | |
670a50eb | 3382 | break; |
3d3c5039 | 3383 | |
8358c818 ILT |
3384 | case M_BLEUL: |
3385 | likely = 1; | |
3d3c5039 | 3386 | case M_BLEU: |
670a50eb ILT |
3387 | if (treg == 0) |
3388 | { | |
0dd2d296 | 3389 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3390 | likely ? "beql" : "beq", |
3391 | "s,t,p", sreg, 0); | |
670a50eb | 3392 | return; |
3d3c5039 | 3393 | } |
9a7d824a ILT |
3394 | if (sreg == 0) |
3395 | goto do_true; | |
0dd2d296 ILT |
3396 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3397 | sreg); | |
3398 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3399 | likely ? "beql" : "beq", |
3400 | "s,t,p", AT, 0); | |
670a50eb | 3401 | break; |
3d3c5039 | 3402 | |
8358c818 ILT |
3403 | case M_BLEUL_I: |
3404 | likely = 1; | |
3d3c5039 | 3405 | case M_BLEU_I: |
6e8dda9c | 3406 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3407 | goto do_true; |
3408 | imm_expr.X_add_number++; | |
3409 | /* FALLTHROUGH */ | |
9a7d824a | 3410 | case M_BLTU_I: |
8358c818 ILT |
3411 | case M_BLTUL_I: |
3412 | if (mask == M_BLTUL_I) | |
3413 | likely = 1; | |
670a50eb | 3414 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3415 | goto do_false; |
3416 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3417 | { |
0dd2d296 | 3418 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3419 | likely ? "beql" : "beq", |
3420 | "s,t,p", sreg, 0); | |
670a50eb | 3421 | return; |
3d3c5039 | 3422 | } |
6e8dda9c | 3423 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3424 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3425 | likely ? "bnel" : "bne", |
3426 | "s,t,p", AT, 0); | |
670a50eb | 3427 | break; |
3d3c5039 | 3428 | |
8358c818 ILT |
3429 | case M_BLTL: |
3430 | likely = 1; | |
3d3c5039 | 3431 | case M_BLT: |
670a50eb ILT |
3432 | if (treg == 0) |
3433 | { | |
0dd2d296 | 3434 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3435 | likely ? "bltzl" : "bltz", |
3436 | "s,p", sreg); | |
670a50eb | 3437 | return; |
3d3c5039 | 3438 | } |
9a7d824a | 3439 | if (sreg == 0) |
670a50eb | 3440 | { |
0dd2d296 | 3441 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3442 | likely ? "bgtzl" : "bgtz", |
3443 | "s,p", treg); | |
670a50eb | 3444 | return; |
3d3c5039 | 3445 | } |
0dd2d296 ILT |
3446 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3447 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3448 | likely ? "bnel" : "bne", |
3449 | "s,t,p", AT, 0); | |
670a50eb | 3450 | break; |
3d3c5039 | 3451 | |
8358c818 ILT |
3452 | case M_BLTUL: |
3453 | likely = 1; | |
3d3c5039 | 3454 | case M_BLTU: |
670a50eb | 3455 | if (treg == 0) |
9a7d824a ILT |
3456 | goto do_false; |
3457 | if (sreg == 0) | |
670a50eb | 3458 | { |
0dd2d296 | 3459 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3460 | likely ? "bnel" : "bne", |
3461 | "s,t,p", 0, treg); | |
670a50eb ILT |
3462 | return; |
3463 | } | |
0dd2d296 ILT |
3464 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3465 | treg); | |
3466 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3467 | likely ? "bnel" : "bne", |
3468 | "s,t,p", AT, 0); | |
670a50eb | 3469 | break; |
3d3c5039 | 3470 | |
8358c818 ILT |
3471 | case M_DDIV_3: |
3472 | dbl = 1; | |
3d3c5039 | 3473 | case M_DIV_3: |
8358c818 ILT |
3474 | s = "mflo"; |
3475 | goto do_div3; | |
3476 | case M_DREM_3: | |
3477 | dbl = 1; | |
3d3c5039 | 3478 | case M_REM_3: |
8358c818 ILT |
3479 | s = "mfhi"; |
3480 | do_div3: | |
670a50eb ILT |
3481 | if (treg == 0) |
3482 | { | |
3483 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3484 | if (mips_trap) |
3485 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3486 | else | |
3487 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3488 | return; |
3489 | } | |
3490 | ||
fbcfacb7 | 3491 | mips_emit_delays (true); |
becfe05e | 3492 | ++mips_noreorder; |
0dd2d296 ILT |
3493 | mips_any_noreorder = 1; |
3494 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3495 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3496 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3497 | if (mips_trap) |
3498 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3499 | else | |
3500 | { | |
3501 | expr1.X_add_number = 8; | |
3502 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3503 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3504 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3505 | } | |
670a50eb | 3506 | expr1.X_add_number = -1; |
0dd2d296 | 3507 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3508 | dbl ? "daddiu" : "addiu", |
9226253a | 3509 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3510 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3511 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3512 | if (dbl) |
3513 | { | |
3514 | expr1.X_add_number = 1; | |
0dd2d296 | 3515 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3516 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3517 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3518 | 31); | |
8358c818 ILT |
3519 | } |
3520 | else | |
3521 | { | |
3522 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3523 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3524 | (int) BFD_RELOC_HI16); | |
8358c818 | 3525 | } |
8ea7f4e8 ILT |
3526 | if (mips_trap) |
3527 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3528 | else | |
3529 | { | |
3530 | expr1.X_add_number = 8; | |
3531 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3532 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3533 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3534 | } | |
becfe05e | 3535 | --mips_noreorder; |
0dd2d296 | 3536 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3537 | break; |
3d3c5039 ILT |
3538 | |
3539 | case M_DIV_3I: | |
8358c818 ILT |
3540 | s = "div"; |
3541 | s2 = "mflo"; | |
3542 | goto do_divi; | |
3d3c5039 | 3543 | case M_DIVU_3I: |
8358c818 ILT |
3544 | s = "divu"; |
3545 | s2 = "mflo"; | |
3546 | goto do_divi; | |
3d3c5039 | 3547 | case M_REM_3I: |
8358c818 ILT |
3548 | s = "div"; |
3549 | s2 = "mfhi"; | |
3550 | goto do_divi; | |
3d3c5039 | 3551 | case M_REMU_3I: |
8358c818 ILT |
3552 | s = "divu"; |
3553 | s2 = "mfhi"; | |
3554 | goto do_divi; | |
3555 | case M_DDIV_3I: | |
3556 | dbl = 1; | |
3557 | s = "ddiv"; | |
3558 | s2 = "mflo"; | |
3559 | goto do_divi; | |
3560 | case M_DDIVU_3I: | |
3561 | dbl = 1; | |
3562 | s = "ddivu"; | |
3563 | s2 = "mflo"; | |
3564 | goto do_divi; | |
3565 | case M_DREM_3I: | |
3566 | dbl = 1; | |
3567 | s = "ddiv"; | |
3568 | s2 = "mfhi"; | |
3569 | goto do_divi; | |
3570 | case M_DREMU_3I: | |
3571 | dbl = 1; | |
3572 | s = "ddivu"; | |
3573 | s2 = "mfhi"; | |
3574 | do_divi: | |
670a50eb ILT |
3575 | if (imm_expr.X_add_number == 0) |
3576 | { | |
3577 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3578 | if (mips_trap) |
3579 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3580 | else | |
3581 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3582 | return; |
3583 | } | |
3584 | if (imm_expr.X_add_number == 1) | |
3585 | { | |
8358c818 | 3586 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3587 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3588 | sreg); | |
3d3c5039 | 3589 | else |
0dd2d296 | 3590 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3591 | return; |
3592 | } | |
8358c818 ILT |
3593 | if (imm_expr.X_add_number == -1 |
3594 | && s[strlen (s) - 1] != 'u') | |
3595 | { | |
3596 | if (strcmp (s2, "mflo") == 0) | |
3597 | { | |
3598 | if (dbl) | |
0dd2d296 ILT |
3599 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3600 | sreg); | |
8358c818 | 3601 | else |
0dd2d296 ILT |
3602 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3603 | sreg); | |
8358c818 ILT |
3604 | } |
3605 | else | |
0dd2d296 | 3606 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3607 | return; |
3608 | } | |
3d3c5039 | 3609 | |
d8a1c247 | 3610 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3611 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3612 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3613 | break; |
3614 | ||
3615 | case M_DIVU_3: | |
8358c818 ILT |
3616 | s = "divu"; |
3617 | s2 = "mflo"; | |
3618 | goto do_divu3; | |
670a50eb | 3619 | case M_REMU_3: |
8358c818 ILT |
3620 | s = "divu"; |
3621 | s2 = "mfhi"; | |
3622 | goto do_divu3; | |
3623 | case M_DDIVU_3: | |
3624 | s = "ddivu"; | |
3625 | s2 = "mflo"; | |
3626 | goto do_divu3; | |
3627 | case M_DREMU_3: | |
3628 | s = "ddivu"; | |
3629 | s2 = "mfhi"; | |
3630 | do_divu3: | |
fbcfacb7 | 3631 | mips_emit_delays (true); |
becfe05e | 3632 | ++mips_noreorder; |
0dd2d296 ILT |
3633 | mips_any_noreorder = 1; |
3634 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3635 | if (mips_trap) |
3636 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3637 | else | |
3638 | { | |
3639 | expr1.X_add_number = 8; | |
3640 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3641 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3642 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3643 | } | |
becfe05e | 3644 | --mips_noreorder; |
0dd2d296 | 3645 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3646 | return; |
3d3c5039 | 3647 | |
d8a1c247 KR |
3648 | case M_DLA_AB: |
3649 | dbl = 1; | |
0dd2d296 | 3650 | case M_LA_AB: |
d9aba805 ILT |
3651 | /* Load the address of a symbol into a register. If breg is not |
3652 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3653 | |
3654 | /* When generating embedded PIC code, we permit expressions of | |
3655 | the form | |
3656 | la $4,foo-bar | |
3657 | where bar is an address in the .text section. These are used | |
3658 | when getting the addresses of functions. We don't permit | |
3659 | X_add_number to be non-zero, because if the symbol is | |
3660 | external the relaxing code needs to know that any addend is | |
3661 | purely the offset to X_op_symbol. */ | |
3662 | if (mips_pic == EMBEDDED_PIC | |
3663 | && offset_expr.X_op == O_subtract | |
3664 | && now_seg == text_section | |
847a01cd ILT |
3665 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3666 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3667 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3668 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3669 | ->sy_value.X_add_symbol) | |
3670 | == text_section))) | |
ecd4ca1c ILT |
3671 | && breg == 0 |
3672 | && offset_expr.X_add_number == 0) | |
3673 | { | |
3674 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3675 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3676 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3677 | mips_isa < 3 ? "addiu" : "daddiu", | |
3678 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3679 | return; | |
3680 | } | |
3681 | ||
0dd2d296 ILT |
3682 | if (offset_expr.X_op != O_symbol |
3683 | && offset_expr.X_op != O_constant) | |
670a50eb | 3684 | { |
0dd2d296 ILT |
3685 | as_bad ("expression too complex"); |
3686 | offset_expr.X_op = O_constant; | |
3687 | } | |
3688 | ||
3689 | if (treg == breg) | |
3690 | { | |
3691 | tempreg = AT; | |
3692 | used_at = 1; | |
3d3c5039 | 3693 | } |
670a50eb ILT |
3694 | else |
3695 | { | |
0dd2d296 ILT |
3696 | tempreg = treg; |
3697 | used_at = 0; | |
670a50eb | 3698 | } |
3d3c5039 | 3699 | |
5ac34ac3 | 3700 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3701 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3702 | else if (mips_pic == NO_PIC) |
670a50eb | 3703 | { |
0dd2d296 ILT |
3704 | /* If this is a reference to an GP relative symbol, we want |
3705 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3706 | Otherwise we want | |
3707 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3708 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3709 | If we have a constant, we need two instructions anyhow, | |
3710 | so we may as well always use the latter form. */ | |
7a15a226 | 3711 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3712 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3713 | p = NULL; |
3714 | else | |
3715 | { | |
8ea7f4e8 | 3716 | frag_grow (20); |
0dd2d296 ILT |
3717 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3718 | mips_isa < 3 ? "addiu" : "daddiu", | |
3719 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3720 | p = frag_var (rs_machine_dependent, 8, 0, | |
3721 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3722 | mips_warn_about_macros), | |
3723 | offset_expr.X_add_symbol, (long) 0, | |
3724 | (char *) NULL); | |
3725 | } | |
3726 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3727 | if (p != NULL) | |
3728 | p += 4; | |
3729 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3730 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3731 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3732 | } | |
fb251650 | 3733 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3734 | { |
3735 | /* If this is a reference to an external symbol, and there | |
3736 | is no constant, we want | |
3737 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3738 | For a local symbol, we want | |
3739 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3740 | nop | |
3741 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3742 | ||
3743 | If we have a small constant, and this is a reference to | |
3744 | an external symbol, we want | |
3745 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3746 | nop | |
3747 | addiu $tempreg,$tempreg,<constant> | |
3748 | For a local symbol, we want the same instruction | |
3749 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3750 | addiu instruction. | |
3751 | ||
3752 | If we have a large constant, and this is a reference to | |
3753 | an external symbol, we want | |
3754 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3755 | lui $at,<hiconstant> | |
3756 | addiu $at,$at,<loconstant> | |
3757 | addu $tempreg,$tempreg,$at | |
3758 | For a local symbol, we want the same instruction | |
3759 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3760 | addiu instruction. */ | |
3761 | expr1.X_add_number = offset_expr.X_add_number; | |
3762 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3763 | frag_grow (32); |
0dd2d296 | 3764 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3765 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3766 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3767 | if (expr1.X_add_number == 0) | |
3768 | { | |
3769 | int off; | |
3770 | ||
3771 | if (breg == 0) | |
3772 | off = 0; | |
3773 | else | |
3774 | { | |
3775 | /* We're going to put in an addu instruction using | |
3776 | tempreg, so we may as well insert the nop right | |
3777 | now. */ | |
3778 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3779 | "nop", ""); | |
3780 | off = 4; | |
3781 | } | |
3782 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3783 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3784 | (breg == 0 | |
3785 | ? mips_warn_about_macros | |
3786 | : 0)), | |
3787 | offset_expr.X_add_symbol, (long) 0, | |
3788 | (char *) NULL); | |
3789 | if (breg == 0) | |
3790 | { | |
3791 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3792 | p += 4; | |
3793 | } | |
3794 | macro_build (p, &icnt, &expr1, | |
3795 | mips_isa < 3 ? "addiu" : "daddiu", | |
3796 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3797 | /* FIXME: If breg == 0, and the next instruction uses | |
3798 | $tempreg, then if this variant case is used an extra | |
3799 | nop will be generated. */ | |
3800 | } | |
3801 | else if (expr1.X_add_number >= -0x8000 | |
3802 | && expr1.X_add_number < 0x8000) | |
3803 | { | |
3804 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3805 | "nop", ""); | |
3806 | macro_build ((char *) NULL, &icnt, &expr1, | |
3807 | mips_isa < 3 ? "addiu" : "daddiu", | |
3808 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3809 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3810 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
3811 | offset_expr.X_add_symbol, (long) 0, | |
3812 | (char *) NULL); | |
3813 | } | |
3814 | else | |
3815 | { | |
3816 | int off1; | |
3817 | ||
3818 | /* If we are going to add in a base register, and the | |
3819 | target register and the base register are the same, | |
3820 | then we are using AT as a temporary register. Since | |
3821 | we want to load the constant into AT, we add our | |
3822 | current AT (from the global offset table) and the | |
3823 | register into the register now, and pretend we were | |
3824 | not using a base register. */ | |
3825 | if (breg != treg) | |
3826 | off1 = 0; | |
3827 | else | |
3828 | { | |
3829 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3830 | "nop", ""); | |
3831 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3832 | mips_isa < 3 ? "addu" : "daddu", | |
3833 | "d,v,t", treg, AT, breg); | |
3834 | breg = 0; | |
3835 | tempreg = treg; | |
3836 | off1 = -8; | |
3837 | } | |
3838 | ||
55933a58 ILT |
3839 | /* Set mips_optimize around the lui instruction to avoid |
3840 | inserting an unnecessary nop after the lw. */ | |
3841 | hold_mips_optimize = mips_optimize; | |
3842 | mips_optimize = 2; | |
0dd2d296 | 3843 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
3844 | mips_optimize = hold_mips_optimize; |
3845 | ||
0dd2d296 ILT |
3846 | macro_build ((char *) NULL, &icnt, &expr1, |
3847 | mips_isa < 3 ? "addiu" : "daddiu", | |
3848 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3849 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3850 | mips_isa < 3 ? "addu" : "daddu", | |
3851 | "d,v,t", tempreg, tempreg, AT); | |
3852 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3853 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
3854 | offset_expr.X_add_symbol, (long) 0, | |
3855 | (char *) NULL); | |
3856 | used_at = 1; | |
3857 | } | |
670a50eb | 3858 | } |
fb251650 ILT |
3859 | else if (mips_pic == SVR4_PIC) |
3860 | { | |
3861 | int gpdel; | |
3862 | ||
3863 | /* This is the large GOT case. If this is a reference to an | |
3864 | external symbol, and there is no constant, we want | |
3865 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3866 | addu $tempreg,$tempreg,$gp | |
3867 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3868 | For a local symbol, we want | |
3869 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3870 | nop | |
3871 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3872 | ||
3873 | If we have a small constant, and this is a reference to | |
3874 | an external symbol, we want | |
3875 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3876 | addu $tempreg,$tempreg,$gp | |
3877 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3878 | nop | |
3879 | addiu $tempreg,$tempreg,<constant> | |
3880 | For a local symbol, we want | |
3881 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3882 | nop | |
3883 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
3884 | ||
3885 | If we have a large constant, and this is a reference to | |
3886 | an external symbol, we want | |
3887 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3888 | addu $tempreg,$tempreg,$gp | |
3889 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3890 | lui $at,<hiconstant> | |
3891 | addiu $at,$at,<loconstant> | |
3892 | addu $tempreg,$tempreg,$at | |
3893 | For a local symbol, we want | |
3894 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3895 | lui $at,<hiconstant> | |
3896 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
3897 | addu $tempreg,$tempreg,$at | |
3898 | */ | |
3899 | expr1.X_add_number = offset_expr.X_add_number; | |
3900 | offset_expr.X_add_number = 0; | |
3901 | frag_grow (52); | |
3902 | if (reg_needs_delay (GP)) | |
3903 | gpdel = 4; | |
3904 | else | |
3905 | gpdel = 0; | |
3906 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3907 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3908 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3909 | mips_isa < 3 ? "addu" : "daddu", | |
3910 | "d,v,t", tempreg, tempreg, GP); | |
3911 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3912 | dbl ? "ld" : "lw", | |
3913 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3914 | tempreg); | |
3915 | if (expr1.X_add_number == 0) | |
3916 | { | |
3917 | int off; | |
3918 | ||
3919 | if (breg == 0) | |
3920 | off = 0; | |
3921 | else | |
3922 | { | |
3923 | /* We're going to put in an addu instruction using | |
3924 | tempreg, so we may as well insert the nop right | |
3925 | now. */ | |
3926 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3927 | "nop", ""); | |
3928 | off = 4; | |
3929 | } | |
3930 | ||
3931 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3932 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
3933 | 8 + gpdel, 0, | |
3934 | (breg == 0 | |
3935 | ? mips_warn_about_macros | |
3936 | : 0)), | |
3937 | offset_expr.X_add_symbol, (long) 0, | |
3938 | (char *) NULL); | |
3939 | } | |
3940 | else if (expr1.X_add_number >= -0x8000 | |
3941 | && expr1.X_add_number < 0x8000) | |
3942 | { | |
3943 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3944 | "nop", ""); | |
3945 | macro_build ((char *) NULL, &icnt, &expr1, | |
3946 | mips_isa < 3 ? "addiu" : "daddiu", | |
3947 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3948 | ||
3949 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3950 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
3951 | (breg == 0 | |
3952 | ? mips_warn_about_macros | |
3953 | : 0)), | |
3954 | offset_expr.X_add_symbol, (long) 0, | |
3955 | (char *) NULL); | |
3956 | } | |
3957 | else | |
3958 | { | |
3959 | int adj, dreg; | |
3960 | ||
3961 | /* If we are going to add in a base register, and the | |
3962 | target register and the base register are the same, | |
3963 | then we are using AT as a temporary register. Since | |
3964 | we want to load the constant into AT, we add our | |
3965 | current AT (from the global offset table) and the | |
3966 | register into the register now, and pretend we were | |
3967 | not using a base register. */ | |
3968 | if (breg != treg) | |
3969 | { | |
3970 | adj = 0; | |
3971 | dreg = tempreg; | |
3972 | } | |
3973 | else | |
3974 | { | |
3975 | assert (tempreg == AT); | |
3976 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3977 | "nop", ""); | |
3978 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3979 | mips_isa < 3 ? "addu" : "daddu", | |
3980 | "d,v,t", treg, AT, breg); | |
3981 | dreg = treg; | |
3982 | adj = 8; | |
3983 | } | |
3984 | ||
3985 | /* Set mips_optimize around the lui instruction to avoid | |
3986 | inserting an unnecessary nop after the lw. */ | |
3987 | hold_mips_optimize = mips_optimize; | |
3988 | mips_optimize = 2; | |
3989 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
3990 | mips_optimize = hold_mips_optimize; | |
3991 | ||
3992 | macro_build ((char *) NULL, &icnt, &expr1, | |
3993 | mips_isa < 3 ? "addiu" : "daddiu", | |
3994 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3995 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3996 | mips_isa < 3 ? "addu" : "daddu", | |
3997 | "d,v,t", dreg, dreg, AT); | |
3998 | ||
3999 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4000 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4001 | 8 + gpdel, 0, | |
4002 | (breg == 0 | |
4003 | ? mips_warn_about_macros | |
4004 | : 0)), | |
4005 | offset_expr.X_add_symbol, (long) 0, | |
4006 | (char *) NULL); | |
4007 | ||
4008 | used_at = 1; | |
4009 | } | |
4010 | ||
4011 | if (gpdel > 0) | |
4012 | { | |
4013 | /* This is needed because this instruction uses $gp, but | |
4014 | the first instruction on the main stream does not. */ | |
4015 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4016 | p += 4; | |
4017 | } | |
4018 | macro_build (p, &icnt, &offset_expr, | |
4019 | dbl ? "ld" : "lw", | |
4020 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4021 | p += 4; | |
4022 | if (expr1.X_add_number >= -0x8000 | |
4023 | && expr1.X_add_number < 0x8000) | |
4024 | { | |
4025 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4026 | p += 4; | |
4027 | macro_build (p, &icnt, &expr1, | |
4028 | mips_isa < 3 ? "addiu" : "daddiu", | |
4029 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4030 | /* FIXME: If add_number is 0, and there was no base | |
4031 | register, the external symbol case ended with a load, | |
4032 | so if the symbol turns out to not be external, and | |
4033 | the next instruction uses tempreg, an unnecessary nop | |
4034 | will be inserted. */ | |
4035 | } | |
4036 | else | |
4037 | { | |
4038 | if (breg == treg) | |
4039 | { | |
4040 | /* We must add in the base register now, as in the | |
4041 | external symbol case. */ | |
4042 | assert (tempreg == AT); | |
4043 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4044 | p += 4; | |
4045 | macro_build (p, &icnt, (expressionS *) NULL, | |
4046 | mips_isa < 3 ? "addu" : "daddu", | |
4047 | "d,v,t", treg, AT, breg); | |
4048 | p += 4; | |
4049 | tempreg = treg; | |
4050 | /* We set breg to 0 because we have arranged to add | |
4051 | it in in both cases. */ | |
4052 | breg = 0; | |
4053 | } | |
4054 | ||
4055 | macro_build_lui (p, &icnt, &expr1, AT); | |
4056 | p += 4; | |
4057 | macro_build (p, &icnt, &expr1, | |
4058 | mips_isa < 3 ? "addiu" : "daddiu", | |
4059 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4060 | p += 4; | |
4061 | macro_build (p, &icnt, (expressionS *) NULL, | |
4062 | mips_isa < 3 ? "addu" : "daddu", | |
4063 | "d,v,t", tempreg, tempreg, AT); | |
4064 | p += 4; | |
4065 | } | |
4066 | } | |
d9aba805 ILT |
4067 | else if (mips_pic == EMBEDDED_PIC) |
4068 | { | |
4069 | /* We use | |
4070 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4071 | */ | |
4072 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4073 | mips_isa < 3 ? "addiu" : "daddiu", | |
4074 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4075 | } | |
4076 | else | |
4077 | abort (); | |
0dd2d296 | 4078 | |
670a50eb | 4079 | if (breg != 0) |
0dd2d296 ILT |
4080 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4081 | mips_isa < 3 ? "addu" : "daddu", | |
4082 | "d,v,t", treg, tempreg, breg); | |
4083 | ||
4084 | if (! used_at) | |
4085 | return; | |
4086 | ||
4087 | break; | |
4088 | ||
4089 | case M_J_A: | |
4090 | /* The j instruction may not be used in PIC code, since it | |
4091 | requires an absolute address. We convert it to a b | |
4092 | instruction. */ | |
d9aba805 | 4093 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4094 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4095 | else | |
4096 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4097 | return; |
3d3c5039 | 4098 | |
9226253a ILT |
4099 | /* The jal instructions must be handled as macros because when |
4100 | generating PIC code they expand to multi-instruction | |
4101 | sequences. Normally they are simple instructions. */ | |
4102 | case M_JAL_1: | |
4103 | dreg = RA; | |
4104 | /* Fall through. */ | |
4105 | case M_JAL_2: | |
d9aba805 ILT |
4106 | if (mips_pic == NO_PIC |
4107 | || mips_pic == EMBEDDED_PIC) | |
4108 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4109 | "d,s", dreg, sreg); | |
4110 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4111 | { |
d9aba805 ILT |
4112 | if (sreg != PIC_CALL_REG) |
4113 | as_warn ("MIPS PIC call to register other than $25"); | |
4114 | ||
0dd2d296 ILT |
4115 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4116 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4117 | if (mips_cprestore_offset < 0) |
4118 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4119 | else | |
4120 | { | |
4121 | expr1.X_add_number = mips_cprestore_offset; | |
4122 | macro_build ((char *) NULL, &icnt, &expr1, | |
4123 | mips_isa < 3 ? "lw" : "ld", | |
4124 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4125 | } | |
9226253a | 4126 | } |
0dd2d296 | 4127 | else |
d9aba805 ILT |
4128 | abort (); |
4129 | ||
9226253a ILT |
4130 | return; |
4131 | ||
4132 | case M_JAL_A: | |
d9aba805 ILT |
4133 | if (mips_pic == NO_PIC) |
4134 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4135 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4136 | { |
fb251650 ILT |
4137 | /* If this is a reference to an external symbol, and we are |
4138 | using a small GOT, we want | |
d9aba805 ILT |
4139 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4140 | nop | |
4141 | jalr $25 | |
4142 | nop | |
4143 | lw $gp,cprestore($sp) | |
4144 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4145 | pseudo-op. If we are using a big GOT, we want |
4146 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4147 | addu $25,$25,$gp | |
4148 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4149 | nop | |
4150 | jalr $25 | |
4151 | nop | |
4152 | lw $gp,cprestore($sp) | |
4153 | If the symbol is not external, we want | |
d9aba805 ILT |
4154 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4155 | nop | |
4156 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4157 | jalr $25 | |
4158 | nop | |
fb251650 ILT |
4159 | lw $gp,cprestore($sp) */ |
4160 | frag_grow (40); | |
4161 | if (! mips_big_got) | |
4162 | { | |
4163 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4164 | mips_isa < 3 ? "lw" : "ld", | |
4165 | "t,o(b)", PIC_CALL_REG, | |
4166 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4167 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4168 | "nop", ""); | |
4169 | p = frag_var (rs_machine_dependent, 4, 0, | |
4170 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4171 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4172 | } | |
4173 | else | |
4174 | { | |
4175 | int gpdel; | |
4176 | ||
4177 | if (reg_needs_delay (GP)) | |
4178 | gpdel = 4; | |
4179 | else | |
4180 | gpdel = 0; | |
4181 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4182 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4183 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4184 | mips_isa < 3 ? "addu" : "daddu", | |
4185 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4186 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4187 | mips_isa < 3 ? "lw" : "ld", | |
4188 | "t,o(b)", PIC_CALL_REG, | |
4189 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4190 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4191 | "nop", ""); | |
4192 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4193 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4194 | 0, 0), | |
4195 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4196 | if (gpdel > 0) | |
4197 | { | |
4198 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4199 | p += 4; | |
4200 | } | |
4201 | macro_build (p, &icnt, &offset_expr, | |
4202 | mips_isa < 3 ? "lw" : "ld", | |
4203 | "t,o(b)", PIC_CALL_REG, | |
4204 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4205 | p += 4; | |
4206 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4207 | p += 4; | |
4208 | } | |
d9aba805 ILT |
4209 | macro_build (p, &icnt, &offset_expr, |
4210 | mips_isa < 3 ? "addiu" : "daddiu", | |
4211 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4212 | (int) BFD_RELOC_LO16); | |
4213 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4214 | "jalr", "s", PIC_CALL_REG); | |
4215 | if (mips_cprestore_offset < 0) | |
4216 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4217 | else | |
4218 | { | |
4219 | if (mips_noreorder) | |
4220 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4221 | "nop", ""); | |
4222 | expr1.X_add_number = mips_cprestore_offset; | |
4223 | macro_build ((char *) NULL, &icnt, &expr1, | |
4224 | mips_isa < 3 ? "lw" : "ld", | |
4225 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4226 | mips_frame_reg); | |
4227 | } | |
0dd2d296 | 4228 | } |
d9aba805 | 4229 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4230 | { |
4231 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4232 | /* The linker may expand the call to a longer sequence which | |
4233 | uses $at, so we must break rather than return. */ | |
4234 | break; | |
4235 | } | |
d9aba805 ILT |
4236 | else |
4237 | abort (); | |
4238 | ||
9226253a ILT |
4239 | return; |
4240 | ||
3d3c5039 | 4241 | case M_LB_AB: |
670a50eb ILT |
4242 | s = "lb"; |
4243 | goto ld; | |
3d3c5039 | 4244 | case M_LBU_AB: |
670a50eb ILT |
4245 | s = "lbu"; |
4246 | goto ld; | |
3d3c5039 | 4247 | case M_LH_AB: |
670a50eb ILT |
4248 | s = "lh"; |
4249 | goto ld; | |
3d3c5039 | 4250 | case M_LHU_AB: |
670a50eb ILT |
4251 | s = "lhu"; |
4252 | goto ld; | |
3d3c5039 | 4253 | case M_LW_AB: |
670a50eb ILT |
4254 | s = "lw"; |
4255 | goto ld; | |
3d3c5039 | 4256 | case M_LWC0_AB: |
670a50eb | 4257 | s = "lwc0"; |
8358c818 | 4258 | coproc = 1; |
670a50eb | 4259 | goto ld; |
3d3c5039 | 4260 | case M_LWC1_AB: |
670a50eb | 4261 | s = "lwc1"; |
8358c818 | 4262 | coproc = 1; |
670a50eb | 4263 | goto ld; |
3d3c5039 | 4264 | case M_LWC2_AB: |
670a50eb | 4265 | s = "lwc2"; |
8358c818 | 4266 | coproc = 1; |
670a50eb | 4267 | goto ld; |
3d3c5039 | 4268 | case M_LWC3_AB: |
670a50eb | 4269 | s = "lwc3"; |
8358c818 | 4270 | coproc = 1; |
670a50eb | 4271 | goto ld; |
3d3c5039 | 4272 | case M_LWL_AB: |
670a50eb | 4273 | s = "lwl"; |
b2b8c24e | 4274 | lr = 1; |
670a50eb | 4275 | goto ld; |
3d3c5039 | 4276 | case M_LWR_AB: |
670a50eb | 4277 | s = "lwr"; |
b2b8c24e | 4278 | lr = 1; |
8358c818 ILT |
4279 | goto ld; |
4280 | case M_LDC1_AB: | |
4281 | s = "ldc1"; | |
4282 | coproc = 1; | |
4283 | goto ld; | |
4284 | case M_LDC2_AB: | |
4285 | s = "ldc2"; | |
4286 | coproc = 1; | |
4287 | goto ld; | |
4288 | case M_LDC3_AB: | |
4289 | s = "ldc3"; | |
4290 | coproc = 1; | |
4291 | goto ld; | |
4292 | case M_LDL_AB: | |
4293 | s = "ldl"; | |
b2b8c24e | 4294 | lr = 1; |
8358c818 ILT |
4295 | goto ld; |
4296 | case M_LDR_AB: | |
4297 | s = "ldr"; | |
b2b8c24e | 4298 | lr = 1; |
8358c818 ILT |
4299 | goto ld; |
4300 | case M_LL_AB: | |
4301 | s = "ll"; | |
4302 | goto ld; | |
4303 | case M_LLD_AB: | |
4304 | s = "lld"; | |
4305 | goto ld; | |
4306 | case M_LWU_AB: | |
4307 | s = "lwu"; | |
3d3c5039 | 4308 | ld: |
b2b8c24e | 4309 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4310 | { |
4311 | tempreg = AT; | |
4312 | used_at = 1; | |
4313 | } | |
4314 | else | |
4315 | { | |
4316 | tempreg = treg; | |
4317 | used_at = 0; | |
4318 | } | |
4319 | goto ld_st; | |
3d3c5039 | 4320 | case M_SB_AB: |
670a50eb ILT |
4321 | s = "sb"; |
4322 | goto st; | |
3d3c5039 | 4323 | case M_SH_AB: |
670a50eb ILT |
4324 | s = "sh"; |
4325 | goto st; | |
3d3c5039 | 4326 | case M_SW_AB: |
670a50eb ILT |
4327 | s = "sw"; |
4328 | goto st; | |
3d3c5039 | 4329 | case M_SWC0_AB: |
670a50eb | 4330 | s = "swc0"; |
8358c818 | 4331 | coproc = 1; |
670a50eb | 4332 | goto st; |
3d3c5039 | 4333 | case M_SWC1_AB: |
670a50eb | 4334 | s = "swc1"; |
8358c818 | 4335 | coproc = 1; |
670a50eb | 4336 | goto st; |
3d3c5039 | 4337 | case M_SWC2_AB: |
670a50eb | 4338 | s = "swc2"; |
8358c818 | 4339 | coproc = 1; |
670a50eb | 4340 | goto st; |
3d3c5039 | 4341 | case M_SWC3_AB: |
670a50eb | 4342 | s = "swc3"; |
8358c818 | 4343 | coproc = 1; |
670a50eb | 4344 | goto st; |
3d3c5039 | 4345 | case M_SWL_AB: |
670a50eb ILT |
4346 | s = "swl"; |
4347 | goto st; | |
3d3c5039 | 4348 | case M_SWR_AB: |
670a50eb | 4349 | s = "swr"; |
8358c818 ILT |
4350 | goto st; |
4351 | case M_SC_AB: | |
4352 | s = "sc"; | |
4353 | goto st; | |
4354 | case M_SCD_AB: | |
4355 | s = "scd"; | |
4356 | goto st; | |
4357 | case M_SDC1_AB: | |
4358 | s = "sdc1"; | |
4359 | coproc = 1; | |
4360 | goto st; | |
4361 | case M_SDC2_AB: | |
4362 | s = "sdc2"; | |
4363 | coproc = 1; | |
4364 | goto st; | |
4365 | case M_SDC3_AB: | |
4366 | s = "sdc3"; | |
4367 | coproc = 1; | |
4368 | goto st; | |
4369 | case M_SDL_AB: | |
4370 | s = "sdl"; | |
4371 | goto st; | |
4372 | case M_SDR_AB: | |
4373 | s = "sdr"; | |
3d3c5039 | 4374 | st: |
670a50eb ILT |
4375 | tempreg = AT; |
4376 | used_at = 1; | |
3d3c5039 | 4377 | ld_st: |
8358c818 ILT |
4378 | if (mask == M_LWC1_AB |
4379 | || mask == M_SWC1_AB | |
8358c818 | 4380 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4381 | || mask == M_SDC1_AB |
4382 | || mask == M_L_DAB | |
4383 | || mask == M_S_DAB) | |
670a50eb | 4384 | fmt = "T,o(b)"; |
8358c818 | 4385 | else if (coproc) |
19ed8960 | 4386 | fmt = "E,o(b)"; |
670a50eb ILT |
4387 | else |
4388 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4389 | |
4390 | if (offset_expr.X_op != O_constant | |
4391 | && offset_expr.X_op != O_symbol) | |
4392 | { | |
4393 | as_bad ("expression too complex"); | |
4394 | offset_expr.X_op = O_constant; | |
4395 | } | |
4396 | ||
4397 | /* A constant expression in PIC code can be handled just as it | |
4398 | is in non PIC code. */ | |
d9aba805 | 4399 | if (mips_pic == NO_PIC |
0dd2d296 | 4400 | || offset_expr.X_op == O_constant) |
670a50eb | 4401 | { |
0dd2d296 ILT |
4402 | /* If this is a reference to a GP relative symbol, and there |
4403 | is no base register, we want | |
4404 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4405 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4406 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4407 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4408 | If we have a constant, we need two instructions anyhow, | |
4409 | so we always use the latter form. | |
4410 | ||
4411 | If we have a base register, and this is a reference to a | |
4412 | GP relative symbol, we want | |
4413 | addu $tempreg,$breg,$gp | |
4414 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4415 | Otherwise we want | |
4416 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4417 | addu $tempreg,$tempreg,$breg | |
4418 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4419 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4420 | if (breg == 0) |
4421 | { | |
7a15a226 | 4422 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4423 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4424 | p = NULL; |
4425 | else | |
4426 | { | |
8ea7f4e8 | 4427 | frag_grow (20); |
0dd2d296 ILT |
4428 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4429 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4430 | p = frag_var (rs_machine_dependent, 8, 0, | |
4431 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4432 | (mips_warn_about_macros |
4433 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4434 | offset_expr.X_add_symbol, (long) 0, |
4435 | (char *) NULL); | |
8197b589 | 4436 | used_at = 0; |
0dd2d296 ILT |
4437 | } |
4438 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4439 | if (p != NULL) | |
4440 | p += 4; | |
4441 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4442 | (int) BFD_RELOC_LO16, tempreg); | |
4443 | } | |
4444 | else | |
4445 | { | |
7a15a226 | 4446 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4447 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4448 | p = NULL; |
4449 | else | |
4450 | { | |
8ea7f4e8 | 4451 | frag_grow (28); |
0dd2d296 ILT |
4452 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4453 | mips_isa < 3 ? "addu" : "daddu", | |
4454 | "d,v,t", tempreg, breg, GP); | |
4455 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4456 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4457 | p = frag_var (rs_machine_dependent, 12, 0, | |
4458 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4459 | offset_expr.X_add_symbol, (long) 0, | |
4460 | (char *) NULL); | |
4461 | } | |
4462 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4463 | if (p != NULL) | |
4464 | p += 4; | |
4465 | macro_build (p, &icnt, (expressionS *) NULL, | |
4466 | mips_isa < 3 ? "addu" : "daddu", | |
4467 | "d,v,t", tempreg, tempreg, breg); | |
4468 | if (p != NULL) | |
4469 | p += 4; | |
4470 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4471 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4472 | } |
670a50eb | 4473 | } |
fb251650 | 4474 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4475 | { |
0dd2d296 ILT |
4476 | /* If this is a reference to an external symbol, we want |
4477 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4478 | nop | |
4479 | <op> $treg,0($tempreg) | |
4480 | Otherwise we want | |
4481 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4482 | nop | |
4483 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4484 | <op> $treg,0($tempreg) | |
4485 | If there is a base register, we add it to $tempreg before | |
4486 | the <op>. If there is a constant, we stick it in the | |
4487 | <op> instruction. We don't handle constants larger than | |
4488 | 16 bits, because we have no way to load the upper 16 bits | |
4489 | (actually, we could handle them for the subset of cases | |
4490 | in which we are not using $at). */ | |
4491 | assert (offset_expr.X_op == O_symbol); | |
4492 | expr1.X_add_number = offset_expr.X_add_number; | |
4493 | offset_expr.X_add_number = 0; | |
4494 | if (expr1.X_add_number < -0x8000 | |
4495 | || expr1.X_add_number >= 0x8000) | |
4496 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4497 | frag_grow (20); |
0dd2d296 ILT |
4498 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4499 | mips_isa < 3 ? "lw" : "ld", | |
4500 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4501 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4502 | p = frag_var (rs_machine_dependent, 4, 0, | |
4503 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4504 | offset_expr.X_add_symbol, (long) 0, | |
4505 | (char *) NULL); | |
4506 | macro_build (p, &icnt, &offset_expr, | |
4507 | mips_isa < 3 ? "addiu" : "daddiu", | |
4508 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4509 | if (breg != 0) |
0dd2d296 | 4510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4511 | mips_isa < 3 ? "addu" : "daddu", |
4512 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4513 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4514 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4515 | } |
fb251650 ILT |
4516 | else if (mips_pic == SVR4_PIC) |
4517 | { | |
4518 | int gpdel; | |
4519 | ||
4520 | /* If this is a reference to an external symbol, we want | |
4521 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4522 | addu $tempreg,$tempreg,$gp | |
4523 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4524 | <op> $treg,0($tempreg) | |
4525 | Otherwise we want | |
4526 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4527 | nop | |
4528 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4529 | <op> $treg,0($tempreg) | |
4530 | If there is a base register, we add it to $tempreg before | |
4531 | the <op>. If there is a constant, we stick it in the | |
4532 | <op> instruction. We don't handle constants larger than | |
4533 | 16 bits, because we have no way to load the upper 16 bits | |
4534 | (actually, we could handle them for the subset of cases | |
4535 | in which we are not using $at). */ | |
4536 | assert (offset_expr.X_op == O_symbol); | |
4537 | expr1.X_add_number = offset_expr.X_add_number; | |
4538 | offset_expr.X_add_number = 0; | |
4539 | if (expr1.X_add_number < -0x8000 | |
4540 | || expr1.X_add_number >= 0x8000) | |
4541 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4542 | if (reg_needs_delay (GP)) | |
4543 | gpdel = 4; | |
4544 | else | |
4545 | gpdel = 0; | |
4546 | frag_grow (36); | |
4547 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4548 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4549 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4550 | mips_isa < 3 ? "addu" : "daddu", | |
4551 | "d,v,t", tempreg, tempreg, GP); | |
4552 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4553 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4554 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4555 | tempreg); | |
fb251650 ILT |
4556 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4557 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4558 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4559 | if (gpdel > 0) | |
4560 | { | |
4561 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4562 | p += 4; | |
4563 | } | |
4564 | macro_build (p, &icnt, &offset_expr, | |
4565 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4566 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4567 | p += 4; |
4568 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4569 | p += 4; | |
4570 | macro_build (p, &icnt, &offset_expr, | |
4571 | mips_isa < 3 ? "addiu" : "daddiu", | |
4572 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4573 | if (breg != 0) | |
4574 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4575 | mips_isa < 3 ? "addu" : "daddu", | |
4576 | "d,v,t", tempreg, tempreg, breg); | |
4577 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4578 | (int) BFD_RELOC_LO16, tempreg); | |
4579 | } | |
d9aba805 ILT |
4580 | else if (mips_pic == EMBEDDED_PIC) |
4581 | { | |
4582 | /* If there is no base register, we want | |
4583 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4584 | If there is a base register, we want | |
4585 | addu $tempreg,$breg,$gp | |
4586 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4587 | */ | |
4588 | assert (offset_expr.X_op == O_symbol); | |
4589 | if (breg == 0) | |
4590 | { | |
4591 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4592 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4593 | used_at = 0; | |
4594 | } | |
4595 | else | |
4596 | { | |
4597 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4598 | mips_isa < 3 ? "addu" : "daddu", | |
4599 | "d,v,t", tempreg, breg, GP); | |
4600 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4601 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4602 | } | |
4603 | } | |
4604 | else | |
4605 | abort (); | |
0dd2d296 ILT |
4606 | |
4607 | if (! used_at) | |
4608 | return; | |
4609 | ||
4610 | break; | |
3d3c5039 ILT |
4611 | |
4612 | case M_LI: | |
19ed8960 | 4613 | case M_LI_S: |
d8a1c247 KR |
4614 | load_register (&icnt, treg, &imm_expr, 0); |
4615 | return; | |
4616 | ||
4617 | case M_DLI: | |
4618 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4619 | return; |
3d3c5039 | 4620 | |
0dd2d296 | 4621 | case M_LI_SS: |
55933a58 | 4622 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4623 | { |
d8a1c247 | 4624 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4625 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4626 | "mtc1", "t,G", AT, treg); | |
4627 | break; | |
0dd2d296 | 4628 | } |
d9aba805 | 4629 | else |
d2c71068 | 4630 | { |
55933a58 ILT |
4631 | assert (offset_expr.X_op == O_symbol |
4632 | && strcmp (segment_name (S_GET_SEGMENT | |
4633 | (offset_expr.X_add_symbol)), | |
4634 | ".lit4") == 0 | |
4635 | && offset_expr.X_add_number == 0); | |
4636 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4637 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4638 | return; |
4639 | } | |
0dd2d296 | 4640 | |
3d3c5039 | 4641 | case M_LI_D: |
d9aba805 ILT |
4642 | /* We know that sym is in the .rdata section. First we get the |
4643 | upper 16 bits of the address. */ | |
4644 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4645 | { |
4646 | /* FIXME: This won't work for a 64 bit address. */ | |
4647 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4648 | } | |
d9aba805 | 4649 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4650 | { |
4651 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4652 | mips_isa < 3 ? "lw" : "ld", | |
4653 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4654 | } | |
d9aba805 ILT |
4655 | else if (mips_pic == EMBEDDED_PIC) |
4656 | { | |
4657 | /* For embedded PIC we pick up the entire address off $gp in | |
4658 | a single instruction. */ | |
4659 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4660 | mips_isa < 3 ? "addiu" : "daddiu", | |
4661 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4662 | offset_expr.X_op = O_constant; | |
4663 | offset_expr.X_add_number = 0; | |
4664 | } | |
4665 | else | |
4666 | abort (); | |
4667 | ||
0dd2d296 | 4668 | /* Now we load the register(s). */ |
8358c818 | 4669 | if (mips_isa >= 3) |
0dd2d296 ILT |
4670 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4671 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4672 | else |
4673 | { | |
0dd2d296 ILT |
4674 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4675 | treg, (int) BFD_RELOC_LO16, AT); | |
4676 | if (treg != 31) | |
4677 | { | |
4678 | /* FIXME: How in the world do we deal with the possible | |
4679 | overflow here? */ | |
4680 | offset_expr.X_add_number += 4; | |
4681 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4682 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4683 | } | |
8358c818 | 4684 | } |
d2c71068 ILT |
4685 | |
4686 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4687 | does not become a variant frag. */ | |
4688 | frag_wane (frag_now); | |
4689 | frag_new (0); | |
4690 | ||
670a50eb | 4691 | break; |
3d3c5039 ILT |
4692 | |
4693 | case M_LI_DD: | |
55933a58 ILT |
4694 | assert (offset_expr.X_op == O_symbol |
4695 | && offset_expr.X_add_number == 0); | |
4696 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4697 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4698 | { |
0dd2d296 ILT |
4699 | if (mips_isa >= 2) |
4700 | { | |
4701 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4702 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4703 | return; | |
4704 | } | |
4705 | breg = GP; | |
4706 | r = BFD_RELOC_MIPS_LITERAL; | |
4707 | goto dob; | |
4708 | } | |
55933a58 | 4709 | else |
0dd2d296 | 4710 | { |
55933a58 ILT |
4711 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4712 | if (mips_pic == SVR4_PIC) | |
4713 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4714 | mips_isa < 3 ? "lw" : "ld", | |
4715 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4716 | else | |
4717 | { | |
4718 | /* FIXME: This won't work for a 64 bit address. */ | |
4719 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4720 | } | |
4721 | ||
0dd2d296 ILT |
4722 | if (mips_isa >= 2) |
4723 | { | |
4724 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4725 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4726 | |
4727 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4728 | that this does not become a variant frag. */ | |
4729 | frag_wane (frag_now); | |
4730 | frag_new (0); | |
4731 | ||
0dd2d296 ILT |
4732 | break; |
4733 | } | |
4734 | breg = AT; | |
4735 | r = BFD_RELOC_LO16; | |
4736 | goto dob; | |
8358c818 | 4737 | } |
9226253a | 4738 | |
3d3c5039 | 4739 | case M_L_DOB: |
9a7d824a ILT |
4740 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4741 | to adjust when loading from memory. */ | |
9226253a ILT |
4742 | r = BFD_RELOC_LO16; |
4743 | dob: | |
8358c818 | 4744 | assert (mips_isa < 2); |
0dd2d296 | 4745 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4746 | target_big_endian ? treg + 1 : treg, |
9226253a | 4747 | (int) r, breg); |
0dd2d296 ILT |
4748 | /* FIXME: A possible overflow which I don't know how to deal |
4749 | with. */ | |
670a50eb | 4750 | offset_expr.X_add_number += 4; |
0dd2d296 | 4751 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 4752 | target_big_endian ? treg : treg + 1, |
9226253a | 4753 | (int) r, breg); |
d2c71068 ILT |
4754 | |
4755 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4756 | does not become a variant frag. */ | |
4757 | frag_wane (frag_now); | |
4758 | frag_new (0); | |
4759 | ||
0dd2d296 ILT |
4760 | if (breg != AT) |
4761 | return; | |
4762 | break; | |
3d3c5039 ILT |
4763 | |
4764 | case M_L_DAB: | |
670a50eb ILT |
4765 | /* |
4766 | * The MIPS assembler seems to check for X_add_number not | |
4767 | * being double aligned and generating: | |
4768 | * lui at,%hi(foo+1) | |
4769 | * addu at,at,v1 | |
4770 | * addiu at,at,%lo(foo+1) | |
4771 | * lwc1 f2,0(at) | |
4772 | * lwc1 f3,4(at) | |
4773 | * But, the resulting address is the same after relocation so why | |
4774 | * generate the extra instruction? | |
4775 | */ | |
4032d3f0 | 4776 | coproc = 1; |
0dd2d296 | 4777 | if (mips_isa >= 2) |
670a50eb | 4778 | { |
0dd2d296 ILT |
4779 | s = "ldc1"; |
4780 | goto ld; | |
670a50eb | 4781 | } |
0dd2d296 ILT |
4782 | |
4783 | s = "lwc1"; | |
4784 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4785 | goto ldd_std; |
4786 | ||
4787 | case M_S_DAB: | |
8358c818 | 4788 | if (mips_isa >= 2) |
8358c818 | 4789 | { |
0dd2d296 ILT |
4790 | s = "sdc1"; |
4791 | goto st; | |
8358c818 | 4792 | } |
3d3c5039 | 4793 | |
0dd2d296 ILT |
4794 | s = "swc1"; |
4795 | fmt = "T,o(b)"; | |
4796 | coproc = 1; | |
4797 | goto ldd_std; | |
3d3c5039 ILT |
4798 | |
4799 | case M_LD_AB: | |
0dd2d296 | 4800 | if (mips_isa >= 3) |
670a50eb | 4801 | { |
0dd2d296 ILT |
4802 | s = "ld"; |
4803 | goto ld; | |
670a50eb | 4804 | } |
0dd2d296 ILT |
4805 | |
4806 | s = "lw"; | |
4807 | fmt = "t,o(b)"; | |
4808 | goto ldd_std; | |
4809 | ||
4810 | case M_SD_AB: | |
4811 | if (mips_isa >= 3) | |
670a50eb | 4812 | { |
0dd2d296 ILT |
4813 | s = "sd"; |
4814 | goto st; | |
670a50eb | 4815 | } |
0dd2d296 | 4816 | |
670a50eb | 4817 | s = "sw"; |
0dd2d296 ILT |
4818 | fmt = "t,o(b)"; |
4819 | ||
4820 | ldd_std: | |
4821 | if (offset_expr.X_op != O_symbol | |
4822 | && offset_expr.X_op != O_constant) | |
670a50eb | 4823 | { |
0dd2d296 ILT |
4824 | as_bad ("expression too complex"); |
4825 | offset_expr.X_op = O_constant; | |
4826 | } | |
4827 | ||
4828 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
4829 | to adjust when loading from memory. We set coproc if we must | |
4830 | load $fn+1 first. */ | |
b9129c6f | 4831 | if (! target_big_endian) |
0dd2d296 ILT |
4832 | coproc = 0; |
4833 | ||
d9aba805 | 4834 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
4835 | || offset_expr.X_op == O_constant) |
4836 | { | |
4837 | /* If this is a reference to a GP relative symbol, we want | |
4838 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4839 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4840 | If we have a base register, we use this | |
4841 | addu $at,$breg,$gp | |
4842 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4843 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4844 | If this is not a GP relative symbol, we want | |
4845 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4846 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4847 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4848 | If there is a base register, we add it to $at after the | |
4849 | lui instruction. If there is a constant, we always use | |
4850 | the last case. */ | |
7a15a226 | 4851 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4852 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 4853 | { |
0dd2d296 ILT |
4854 | p = NULL; |
4855 | used_at = 1; | |
670a50eb ILT |
4856 | } |
4857 | else | |
0dd2d296 ILT |
4858 | { |
4859 | int off; | |
4860 | ||
4861 | if (breg == 0) | |
4862 | { | |
8ea7f4e8 | 4863 | frag_grow (28); |
0dd2d296 ILT |
4864 | tempreg = GP; |
4865 | off = 0; | |
4866 | used_at = 0; | |
4867 | } | |
4868 | else | |
4869 | { | |
8ea7f4e8 | 4870 | frag_grow (36); |
0dd2d296 ILT |
4871 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4872 | mips_isa < 3 ? "addu" : "daddu", | |
4873 | "d,v,t", AT, breg, GP); | |
4874 | tempreg = AT; | |
4875 | off = 4; | |
4876 | used_at = 1; | |
4877 | } | |
4878 | ||
4879 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4880 | coproc ? treg + 1 : treg, | |
4881 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4882 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
4883 | |
4884 | /* Set mips_optimize to 2 to avoid inserting an | |
4885 | undesired nop. */ | |
4886 | hold_mips_optimize = mips_optimize; | |
4887 | mips_optimize = 2; | |
0dd2d296 ILT |
4888 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4889 | coproc ? treg : treg + 1, | |
4890 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
4891 | mips_optimize = hold_mips_optimize; |
4892 | ||
0dd2d296 ILT |
4893 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
4894 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 4895 | used_at && mips_noat), |
0dd2d296 ILT |
4896 | offset_expr.X_add_symbol, (long) 0, |
4897 | (char *) NULL); | |
777ad64d ILT |
4898 | |
4899 | /* We just generated two relocs. When tc_gen_reloc | |
4900 | handles this case, it will skip the first reloc and | |
4901 | handle the second. The second reloc already has an | |
4902 | extra addend of 4, which we added above. We must | |
4903 | subtract it out, and then subtract another 4 to make | |
4904 | the first reloc come out right. The second reloc | |
4905 | will come out right because we are going to add 4 to | |
4906 | offset_expr when we build its instruction below. */ | |
4907 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4908 | offset_expr.X_op = O_constant; |
4909 | } | |
4910 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4911 | if (p != NULL) | |
4912 | p += 4; | |
4913 | if (breg != 0) | |
4914 | { | |
4915 | macro_build (p, &icnt, (expressionS *) NULL, | |
4916 | mips_isa < 3 ? "addu" : "daddu", | |
4917 | "d,v,t", AT, breg, AT); | |
4918 | if (p != NULL) | |
4919 | p += 4; | |
4920 | } | |
4921 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4922 | coproc ? treg + 1 : treg, | |
4923 | (int) BFD_RELOC_LO16, AT); | |
4924 | if (p != NULL) | |
4925 | p += 4; | |
4926 | /* FIXME: How do we handle overflow here? */ | |
4927 | offset_expr.X_add_number += 4; | |
4928 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4929 | coproc ? treg : treg + 1, | |
4930 | (int) BFD_RELOC_LO16, AT); | |
4931 | } | |
fb251650 | 4932 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4933 | { |
0dd2d296 ILT |
4934 | int off; |
4935 | ||
4936 | /* If this is a reference to an external symbol, we want | |
4937 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4938 | nop | |
4939 | <op> $treg,0($at) | |
4940 | <op> $treg+1,4($at) | |
4941 | Otherwise we want | |
4942 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4943 | nop | |
4944 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4945 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4946 | If there is a base register we add it to $at before the | |
4947 | lwc1 instructions. If there is a constant we include it | |
4948 | in the lwc1 instructions. */ | |
4949 | used_at = 1; | |
4950 | expr1.X_add_number = offset_expr.X_add_number; | |
4951 | offset_expr.X_add_number = 0; | |
4952 | if (expr1.X_add_number < -0x8000 | |
4953 | || expr1.X_add_number >= 0x8000 - 4) | |
4954 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4955 | if (breg == 0) | |
4956 | off = 0; | |
4957 | else | |
4958 | off = 4; | |
8ea7f4e8 | 4959 | frag_grow (24 + off); |
0dd2d296 ILT |
4960 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4961 | mips_isa < 3 ? "lw" : "ld", | |
4962 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4963 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 4964 | if (breg != 0) |
0dd2d296 | 4965 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 4966 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4967 | "d,v,t", AT, breg, AT); |
4968 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4969 | coproc ? treg + 1 : treg, | |
4970 | (int) BFD_RELOC_LO16, AT); | |
4971 | expr1.X_add_number += 4; | |
55933a58 ILT |
4972 | |
4973 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4974 | nop. */ | |
4975 | hold_mips_optimize = mips_optimize; | |
4976 | mips_optimize = 2; | |
0dd2d296 ILT |
4977 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
4978 | coproc ? treg : treg + 1, | |
4979 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
4980 | mips_optimize = hold_mips_optimize; |
4981 | ||
0dd2d296 ILT |
4982 | (void) frag_var (rs_machine_dependent, 0, 0, |
4983 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
4984 | offset_expr.X_add_symbol, (long) 0, | |
4985 | (char *) NULL); | |
8358c818 | 4986 | } |
fb251650 ILT |
4987 | else if (mips_pic == SVR4_PIC) |
4988 | { | |
4989 | int gpdel, off; | |
4990 | ||
4991 | /* If this is a reference to an external symbol, we want | |
4992 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4993 | addu $at,$at,$gp | |
4994 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
4995 | nop | |
4996 | <op> $treg,0($at) | |
4997 | <op> $treg+1,4($at) | |
4998 | Otherwise we want | |
4999 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5000 | nop | |
5001 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5002 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5003 | If there is a base register we add it to $at before the | |
5004 | lwc1 instructions. If there is a constant we include it | |
5005 | in the lwc1 instructions. */ | |
5006 | used_at = 1; | |
5007 | expr1.X_add_number = offset_expr.X_add_number; | |
5008 | offset_expr.X_add_number = 0; | |
5009 | if (expr1.X_add_number < -0x8000 | |
5010 | || expr1.X_add_number >= 0x8000 - 4) | |
5011 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5012 | if (reg_needs_delay (GP)) | |
5013 | gpdel = 4; | |
5014 | else | |
5015 | gpdel = 0; | |
5016 | if (breg == 0) | |
5017 | off = 0; | |
5018 | else | |
5019 | off = 4; | |
5020 | frag_grow (56); | |
5021 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5022 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5023 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5024 | mips_isa < 3 ? "addu" : "daddu", | |
5025 | "d,v,t", AT, AT, GP); | |
5026 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5027 | mips_isa < 3 ? "lw" : "ld", | |
5028 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5029 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5030 | if (breg != 0) | |
5031 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5032 | mips_isa < 3 ? "addu" : "daddu", | |
5033 | "d,v,t", AT, breg, AT); | |
5034 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5035 | coproc ? treg + 1 : treg, | |
5036 | (int) BFD_RELOC_LO16, AT); | |
5037 | expr1.X_add_number += 4; | |
5038 | ||
5039 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5040 | nop. */ | |
5041 | hold_mips_optimize = mips_optimize; | |
5042 | mips_optimize = 2; | |
5043 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5044 | coproc ? treg : treg + 1, | |
5045 | (int) BFD_RELOC_LO16, AT); | |
5046 | mips_optimize = hold_mips_optimize; | |
5047 | expr1.X_add_number -= 4; | |
5048 | ||
5049 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5050 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5051 | 8 + gpdel + off, 1, 0), | |
5052 | offset_expr.X_add_symbol, (long) 0, | |
5053 | (char *) NULL); | |
5054 | if (gpdel > 0) | |
5055 | { | |
5056 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5057 | p += 4; | |
5058 | } | |
5059 | macro_build (p, &icnt, &offset_expr, | |
5060 | mips_isa < 3 ? "lw" : "ld", | |
5061 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5062 | p += 4; | |
5063 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5064 | p += 4; | |
5065 | if (breg != 0) | |
5066 | { | |
5067 | macro_build (p, &icnt, (expressionS *) NULL, | |
5068 | mips_isa < 3 ? "addu" : "daddu", | |
5069 | "d,v,t", AT, breg, AT); | |
5070 | p += 4; | |
5071 | } | |
5072 | macro_build (p, &icnt, &expr1, s, fmt, | |
5073 | coproc ? treg + 1 : treg, | |
5074 | (int) BFD_RELOC_LO16, AT); | |
5075 | p += 4; | |
5076 | expr1.X_add_number += 4; | |
5077 | ||
5078 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5079 | nop. */ | |
5080 | hold_mips_optimize = mips_optimize; | |
5081 | mips_optimize = 2; | |
5082 | macro_build (p, &icnt, &expr1, s, fmt, | |
5083 | coproc ? treg : treg + 1, | |
5084 | (int) BFD_RELOC_LO16, AT); | |
5085 | mips_optimize = hold_mips_optimize; | |
5086 | } | |
d9aba805 ILT |
5087 | else if (mips_pic == EMBEDDED_PIC) |
5088 | { | |
5089 | /* If there is no base register, we use | |
5090 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5091 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5092 | If we have a base register, we use | |
5093 | addu $at,$breg,$gp | |
5094 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5095 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5096 | */ | |
5097 | if (breg == 0) | |
5098 | { | |
5099 | tempreg = GP; | |
5100 | used_at = 0; | |
5101 | } | |
5102 | else | |
5103 | { | |
5104 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5105 | mips_isa < 3 ? "addu" : "daddu", | |
5106 | "d,v,t", AT, breg, GP); | |
5107 | tempreg = AT; | |
5108 | used_at = 1; | |
5109 | } | |
5110 | ||
5111 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5112 | coproc ? treg + 1 : treg, | |
5113 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5114 | offset_expr.X_add_number += 4; | |
5115 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5116 | coproc ? treg : treg + 1, | |
5117 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5118 | } | |
5119 | else | |
5120 | abort (); | |
0dd2d296 ILT |
5121 | |
5122 | if (! used_at) | |
5123 | return; | |
5124 | ||
5125 | break; | |
5126 | ||
5127 | case M_LD_OB: | |
5128 | s = "lw"; | |
5129 | goto sd_ob; | |
5130 | case M_SD_OB: | |
5131 | s = "sw"; | |
5132 | sd_ob: | |
5133 | assert (mips_isa < 3); | |
5134 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5135 | (int) BFD_RELOC_LO16, breg); | |
5136 | offset_expr.X_add_number += 4; | |
5137 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5138 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5139 | return; |
917fae09 SS |
5140 | #ifdef LOSING_COMPILER |
5141 | default: | |
5142 | macro2 (ip); | |
5143 | return; | |
5144 | } | |
5145 | if (mips_noat) | |
5146 | as_warn ("Macro used $at after \".set noat\""); | |
5147 | } | |
5148 | ||
5149 | static void | |
5150 | macro2 (ip) | |
5151 | struct mips_cl_insn *ip; | |
5152 | { | |
5153 | register int treg, sreg, dreg, breg; | |
5154 | int tempreg; | |
5155 | int mask; | |
5156 | int icnt = 0; | |
5157 | int used_at; | |
5158 | expressionS expr1; | |
5159 | const char *s; | |
5160 | const char *s2; | |
5161 | const char *fmt; | |
5162 | int likely = 0; | |
5163 | int dbl = 0; | |
5164 | int coproc = 0; | |
adcf2b9d ILT |
5165 | int lr = 0; |
5166 | int off; | |
917fae09 SS |
5167 | offsetT maxnum; |
5168 | bfd_reloc_code_real_type r; | |
5169 | char *p; | |
5170 | ||
5171 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5172 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5173 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5174 | mask = ip->insn_mo->mask; | |
5175 | ||
5176 | expr1.X_op = O_constant; | |
5177 | expr1.X_op_symbol = NULL; | |
5178 | expr1.X_add_symbol = NULL; | |
5179 | expr1.X_add_number = 1; | |
5180 | ||
5181 | switch (mask) | |
5182 | { | |
5183 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5184 | |
8358c818 ILT |
5185 | case M_DMUL: |
5186 | dbl = 1; | |
3d3c5039 | 5187 | case M_MUL: |
0dd2d296 | 5188 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5189 | dbl ? "dmultu" : "multu", |
5190 | "s,t", sreg, treg); | |
0dd2d296 | 5191 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5192 | return; |
3d3c5039 | 5193 | |
8358c818 ILT |
5194 | case M_DMUL_I: |
5195 | dbl = 1; | |
3d3c5039 | 5196 | case M_MUL_I: |
8358c818 ILT |
5197 | /* The MIPS assembler some times generates shifts and adds. I'm |
5198 | not trying to be that fancy. GCC should do this for us | |
5199 | anyway. */ | |
d8a1c247 | 5200 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5201 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5202 | dbl ? "dmult" : "mult", |
5203 | "s,t", sreg, AT); | |
0dd2d296 | 5204 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5205 | break; |
3d3c5039 | 5206 | |
8358c818 ILT |
5207 | case M_DMULO: |
5208 | dbl = 1; | |
5209 | case M_MULO: | |
fbcfacb7 | 5210 | mips_emit_delays (true); |
8358c818 | 5211 | ++mips_noreorder; |
0dd2d296 ILT |
5212 | mips_any_noreorder = 1; |
5213 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5214 | dbl ? "dmult" : "mult", |
5215 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5216 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5217 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5218 | dbl ? "dsra32" : "sra", |
5219 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5220 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5221 | if (mips_trap) |
5222 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5223 | else | |
5224 | { | |
5225 | expr1.X_add_number = 8; | |
5226 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5227 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5228 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5229 | } | |
8358c818 | 5230 | --mips_noreorder; |
0dd2d296 | 5231 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5232 | break; |
5233 | ||
5234 | case M_DMULOU: | |
5235 | dbl = 1; | |
5236 | case M_MULOU: | |
fbcfacb7 | 5237 | mips_emit_delays (true); |
8358c818 | 5238 | ++mips_noreorder; |
0dd2d296 ILT |
5239 | mips_any_noreorder = 1; |
5240 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5241 | dbl ? "dmultu" : "multu", |
5242 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5243 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5244 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5245 | if (mips_trap) |
5246 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5247 | else | |
5248 | { | |
5249 | expr1.X_add_number = 8; | |
5250 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5251 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5252 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5253 | } | |
8358c818 ILT |
5254 | --mips_noreorder; |
5255 | break; | |
5256 | ||
3d3c5039 | 5257 | case M_ROL: |
0dd2d296 ILT |
5258 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5259 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5260 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5261 | treg); | |
5262 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5263 | break; |
3d3c5039 ILT |
5264 | |
5265 | case M_ROL_I: | |
0dd2d296 | 5266 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5267 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5268 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5269 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5270 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5271 | break; |
3d3c5039 ILT |
5272 | |
5273 | case M_ROR: | |
0dd2d296 ILT |
5274 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5275 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5276 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5277 | treg); | |
5278 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5279 | break; |
3d3c5039 ILT |
5280 | |
5281 | case M_ROR_I: | |
0dd2d296 | 5282 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5283 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5284 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5285 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5286 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5287 | break; |
3d3c5039 ILT |
5288 | |
5289 | case M_S_DOB: | |
8358c818 | 5290 | assert (mips_isa < 2); |
9a7d824a ILT |
5291 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5292 | to adjust when storing to memory. */ | |
0dd2d296 | 5293 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5294 | target_big_endian ? treg + 1 : treg, |
9226253a | 5295 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5296 | offset_expr.X_add_number += 4; |
0dd2d296 | 5297 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5298 | target_big_endian ? treg : treg + 1, |
9226253a | 5299 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5300 | return; |
3d3c5039 | 5301 | |
3d3c5039 | 5302 | case M_SEQ: |
670a50eb | 5303 | if (sreg == 0) |
0dd2d296 ILT |
5304 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5305 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5306 | else if (treg == 0) |
0dd2d296 ILT |
5307 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5308 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5309 | else |
5310 | { | |
0dd2d296 ILT |
5311 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5312 | sreg, treg); | |
5313 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5314 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5315 | } |
670a50eb | 5316 | return; |
3d3c5039 ILT |
5317 | |
5318 | case M_SEQ_I: | |
670a50eb ILT |
5319 | if (imm_expr.X_add_number == 0) |
5320 | { | |
0dd2d296 ILT |
5321 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5322 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5323 | return; |
3d3c5039 | 5324 | } |
670a50eb ILT |
5325 | if (sreg == 0) |
5326 | { | |
9a7d824a | 5327 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5328 | ip->insn_mo->name); |
0dd2d296 | 5329 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5330 | return; |
3d3c5039 | 5331 | } |
6e8dda9c | 5332 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5333 | { |
0dd2d296 ILT |
5334 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5335 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5336 | used_at = 0; |
6e8dda9c ILT |
5337 | } |
5338 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5339 | { | |
5340 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5341 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5342 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5343 | "t,r,j", dreg, sreg, |
5344 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5345 | used_at = 0; |
5346 | } | |
5347 | else | |
5348 | { | |
d8a1c247 | 5349 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5350 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5351 | sreg, AT); | |
670a50eb ILT |
5352 | used_at = 1; |
5353 | } | |
0dd2d296 | 5354 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5355 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5356 | if (used_at) |
5357 | break; | |
5358 | return; | |
3d3c5039 ILT |
5359 | |
5360 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5361 | s = "slt"; |
5362 | goto sge; | |
3d3c5039 | 5363 | case M_SGEU: |
670a50eb | 5364 | s = "sltu"; |
3d3c5039 | 5365 | sge: |
0dd2d296 ILT |
5366 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5367 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5368 | (int) BFD_RELOC_LO16); |
670a50eb | 5369 | return; |
3d3c5039 | 5370 | |
670a50eb | 5371 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5372 | case M_SGEU_I: |
6e8dda9c | 5373 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5374 | { |
0dd2d296 | 5375 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5376 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5377 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5378 | used_at = 0; |
5379 | } | |
5380 | else | |
5381 | { | |
d8a1c247 | 5382 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5383 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5384 | mask == M_SGE_I ? "slt" : "sltu", |
5385 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5386 | used_at = 1; |
5387 | } | |
0dd2d296 | 5388 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5389 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5390 | if (used_at) |
5391 | break; | |
5392 | return; | |
3d3c5039 ILT |
5393 | |
5394 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5395 | s = "slt"; |
5396 | goto sgt; | |
3d3c5039 | 5397 | case M_SGTU: |
670a50eb | 5398 | s = "sltu"; |
3d3c5039 | 5399 | sgt: |
0dd2d296 | 5400 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5401 | return; |
3d3c5039 | 5402 | |
670a50eb ILT |
5403 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5404 | s = "slt"; | |
5405 | goto sgti; | |
3d3c5039 | 5406 | case M_SGTU_I: |
670a50eb | 5407 | s = "sltu"; |
3d3c5039 | 5408 | sgti: |
d8a1c247 | 5409 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5410 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5411 | break; |
3d3c5039 | 5412 | |
670a50eb ILT |
5413 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5414 | s = "slt"; | |
5415 | goto sle; | |
3d3c5039 | 5416 | case M_SLEU: |
670a50eb | 5417 | s = "sltu"; |
3d3c5039 | 5418 | sle: |
0dd2d296 ILT |
5419 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5420 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5421 | (int) BFD_RELOC_LO16); |
670a50eb | 5422 | return; |
3d3c5039 | 5423 | |
670a50eb ILT |
5424 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5425 | s = "slt"; | |
5426 | goto slei; | |
3d3c5039 | 5427 | case M_SLEU_I: |
670a50eb | 5428 | s = "sltu"; |
3d3c5039 | 5429 | slei: |
d8a1c247 | 5430 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5431 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5432 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5433 | (int) BFD_RELOC_LO16); |
670a50eb | 5434 | break; |
3d3c5039 ILT |
5435 | |
5436 | case M_SLT_I: | |
6e8dda9c | 5437 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5438 | { |
0dd2d296 ILT |
5439 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5440 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5441 | return; |
3d3c5039 | 5442 | } |
d8a1c247 | 5443 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5444 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5445 | break; |
3d3c5039 ILT |
5446 | |
5447 | case M_SLTU_I: | |
6e8dda9c | 5448 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5449 | { |
0dd2d296 ILT |
5450 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5451 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5452 | return; |
3d3c5039 | 5453 | } |
d8a1c247 | 5454 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5455 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5456 | AT); | |
670a50eb | 5457 | break; |
3d3c5039 ILT |
5458 | |
5459 | case M_SNE: | |
670a50eb | 5460 | if (sreg == 0) |
0dd2d296 ILT |
5461 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5462 | treg); | |
670a50eb | 5463 | else if (treg == 0) |
0dd2d296 ILT |
5464 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5465 | sreg); | |
670a50eb ILT |
5466 | else |
5467 | { | |
0dd2d296 ILT |
5468 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5469 | sreg, treg); | |
5470 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5471 | dreg); | |
3d3c5039 | 5472 | } |
670a50eb | 5473 | return; |
3d3c5039 ILT |
5474 | |
5475 | case M_SNE_I: | |
670a50eb ILT |
5476 | if (imm_expr.X_add_number == 0) |
5477 | { | |
0dd2d296 ILT |
5478 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5479 | sreg); | |
670a50eb | 5480 | return; |
3d3c5039 | 5481 | } |
670a50eb ILT |
5482 | if (sreg == 0) |
5483 | { | |
9a7d824a | 5484 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5485 | ip->insn_mo->name); |
0dd2d296 | 5486 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5487 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5488 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5489 | return; |
3d3c5039 | 5490 | } |
6e8dda9c | 5491 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5492 | { |
0dd2d296 ILT |
5493 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5494 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5495 | used_at = 0; |
6e8dda9c ILT |
5496 | } |
5497 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5498 | { | |
5499 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5500 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5501 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5502 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5503 | used_at = 0; |
5504 | } | |
5505 | else | |
5506 | { | |
d8a1c247 | 5507 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5508 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5509 | sreg, AT); | |
670a50eb ILT |
5510 | used_at = 1; |
5511 | } | |
0dd2d296 | 5512 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5513 | if (used_at) |
5514 | break; | |
5515 | return; | |
3d3c5039 | 5516 | |
8358c818 ILT |
5517 | case M_DSUB_I: |
5518 | dbl = 1; | |
3d3c5039 | 5519 | case M_SUB_I: |
6e8dda9c | 5520 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5521 | { |
5522 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5523 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5524 | dbl ? "daddi" : "addi", |
9226253a | 5525 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5526 | return; |
3d3c5039 | 5527 | } |
d8a1c247 | 5528 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5529 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5530 | dbl ? "dsub" : "sub", |
5531 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5532 | break; |
3d3c5039 | 5533 | |
8358c818 ILT |
5534 | case M_DSUBU_I: |
5535 | dbl = 1; | |
3d3c5039 | 5536 | case M_SUBU_I: |
6e8dda9c | 5537 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5538 | { |
5539 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5540 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5541 | dbl ? "daddiu" : "addiu", |
9226253a | 5542 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5543 | return; |
3d3c5039 | 5544 | } |
d8a1c247 | 5545 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5546 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5547 | dbl ? "dsubu" : "subu", |
5548 | "d,v,t", dreg, sreg, AT); | |
5549 | break; | |
5550 | ||
5551 | case M_TEQ_I: | |
5552 | s = "teq"; | |
5553 | goto trap; | |
5554 | case M_TGE_I: | |
5555 | s = "tge"; | |
5556 | goto trap; | |
5557 | case M_TGEU_I: | |
5558 | s = "tgeu"; | |
5559 | goto trap; | |
5560 | case M_TLT_I: | |
5561 | s = "tlt"; | |
5562 | goto trap; | |
5563 | case M_TLTU_I: | |
5564 | s = "tltu"; | |
5565 | goto trap; | |
5566 | case M_TNE_I: | |
5567 | s = "tne"; | |
5568 | trap: | |
d8a1c247 | 5569 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5570 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5571 | break; |
3d3c5039 ILT |
5572 | |
5573 | case M_TRUNCWD: | |
5574 | case M_TRUNCWS: | |
8358c818 | 5575 | assert (mips_isa < 2); |
670a50eb ILT |
5576 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5577 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5578 | ||
5579 | /* | |
5580 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5581 | * or is there a reason for it? | |
5582 | */ | |
fbcfacb7 | 5583 | mips_emit_delays (true); |
becfe05e | 5584 | ++mips_noreorder; |
0dd2d296 ILT |
5585 | mips_any_noreorder = 1; |
5586 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5587 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5588 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5589 | expr1.X_add_number = 3; |
0dd2d296 | 5590 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5591 | (int) BFD_RELOC_LO16); |
670a50eb | 5592 | expr1.X_add_number = 2; |
0dd2d296 | 5593 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5594 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5595 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5596 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5597 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5598 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5599 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5600 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5601 | --mips_noreorder; |
670a50eb | 5602 | break; |
3d3c5039 ILT |
5603 | |
5604 | case M_ULH: | |
670a50eb ILT |
5605 | s = "lb"; |
5606 | goto ulh; | |
3d3c5039 | 5607 | case M_ULHU: |
670a50eb | 5608 | s = "lbu"; |
3d3c5039 | 5609 | ulh: |
8ea7f4e8 ILT |
5610 | if (offset_expr.X_add_number >= 0x7fff) |
5611 | as_bad ("operand overflow"); | |
670a50eb | 5612 | /* avoid load delay */ |
b9129c6f | 5613 | if (! target_big_endian) |
8ea7f4e8 | 5614 | offset_expr.X_add_number += 1; |
0dd2d296 | 5615 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5616 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5617 | if (! target_big_endian) |
8ea7f4e8 ILT |
5618 | offset_expr.X_add_number -= 1; |
5619 | else | |
5620 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5621 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5622 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5623 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5624 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5625 | break; |
3d3c5039 | 5626 | |
adcf2b9d ILT |
5627 | case M_ULD: |
5628 | s = "ldl"; | |
5629 | s2 = "ldr"; | |
5630 | off = 7; | |
5631 | goto ulw; | |
3d3c5039 | 5632 | case M_ULW: |
adcf2b9d ILT |
5633 | s = "lwl"; |
5634 | s2 = "lwr"; | |
5635 | off = 3; | |
5636 | ulw: | |
5637 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5638 | as_bad ("operand overflow"); |
b9129c6f | 5639 | if (! target_big_endian) |
adcf2b9d ILT |
5640 | offset_expr.X_add_number += off; |
5641 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5642 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5643 | if (! target_big_endian) |
adcf2b9d | 5644 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5645 | else |
adcf2b9d ILT |
5646 | offset_expr.X_add_number += off; |
5647 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5648 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5649 | return; |
3d3c5039 | 5650 | |
adcf2b9d ILT |
5651 | case M_ULD_A: |
5652 | s = "ldl"; | |
5653 | s2 = "ldr"; | |
5654 | off = 7; | |
5655 | goto ulwa; | |
5656 | case M_ULW_A: | |
5657 | s = "lwl"; | |
5658 | s2 = "lwr"; | |
5659 | off = 3; | |
5660 | ulwa: | |
5661 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5662 | if (breg != 0) |
5663 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5664 | mips_isa < 3 ? "addu" : "daddu", | |
5665 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5666 | if (! target_big_endian) |
adcf2b9d ILT |
5667 | expr1.X_add_number = off; |
5668 | else | |
5669 | expr1.X_add_number = 0; | |
5670 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5671 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5672 | if (! target_big_endian) |
adcf2b9d ILT |
5673 | expr1.X_add_number = 0; |
5674 | else | |
5675 | expr1.X_add_number = off; | |
5676 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5677 | (int) BFD_RELOC_LO16, AT); | |
5678 | break; | |
5679 | ||
3d3c5039 ILT |
5680 | case M_ULH_A: |
5681 | case M_ULHU_A: | |
0dd2d296 | 5682 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5683 | if (breg != 0) |
5684 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5685 | mips_isa < 3 ? "addu" : "daddu", | |
5686 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5687 | if (target_big_endian) |
adcf2b9d ILT |
5688 | expr1.X_add_number = 0; |
5689 | macro_build ((char *) NULL, &icnt, &expr1, | |
5690 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5691 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5692 | if (target_big_endian) |
adcf2b9d | 5693 | expr1.X_add_number = 1; |
670a50eb | 5694 | else |
adcf2b9d ILT |
5695 | expr1.X_add_number = 0; |
5696 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5697 | (int) BFD_RELOC_LO16, AT); | |
5698 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5699 | treg, 8); | |
5700 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5701 | treg, AT); | |
670a50eb | 5702 | break; |
3d3c5039 ILT |
5703 | |
5704 | case M_USH: | |
8ea7f4e8 ILT |
5705 | if (offset_expr.X_add_number >= 0x7fff) |
5706 | as_bad ("operand overflow"); | |
b9129c6f | 5707 | if (target_big_endian) |
8ea7f4e8 | 5708 | offset_expr.X_add_number += 1; |
0dd2d296 | 5709 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5710 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5711 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 5712 | if (target_big_endian) |
8ea7f4e8 ILT |
5713 | offset_expr.X_add_number -= 1; |
5714 | else | |
5715 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5716 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5717 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5718 | break; |
3d3c5039 | 5719 | |
adcf2b9d ILT |
5720 | case M_USD: |
5721 | s = "sdl"; | |
5722 | s2 = "sdr"; | |
5723 | off = 7; | |
5724 | goto usw; | |
3d3c5039 | 5725 | case M_USW: |
adcf2b9d ILT |
5726 | s = "swl"; |
5727 | s2 = "swr"; | |
5728 | off = 3; | |
5729 | usw: | |
5730 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 5731 | as_bad ("operand overflow"); |
b9129c6f | 5732 | if (! target_big_endian) |
adcf2b9d ILT |
5733 | offset_expr.X_add_number += off; |
5734 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5735 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 5736 | if (! target_big_endian) |
adcf2b9d | 5737 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5738 | else |
adcf2b9d ILT |
5739 | offset_expr.X_add_number += off; |
5740 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5741 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5742 | return; |
3d3c5039 | 5743 | |
adcf2b9d ILT |
5744 | case M_USD_A: |
5745 | s = "sdl"; | |
5746 | s2 = "sdr"; | |
5747 | off = 7; | |
5748 | goto uswa; | |
3d3c5039 | 5749 | case M_USW_A: |
adcf2b9d ILT |
5750 | s = "swl"; |
5751 | s2 = "swr"; | |
5752 | off = 3; | |
5753 | uswa: | |
0dd2d296 | 5754 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5755 | if (breg != 0) |
5756 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5757 | mips_isa < 3 ? "addu" : "daddu", | |
5758 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5759 | if (! target_big_endian) |
adcf2b9d | 5760 | expr1.X_add_number = off; |
670a50eb | 5761 | else |
adcf2b9d ILT |
5762 | expr1.X_add_number = 0; |
5763 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5764 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5765 | if (! target_big_endian) |
adcf2b9d ILT |
5766 | expr1.X_add_number = 0; |
5767 | else | |
5768 | expr1.X_add_number = off; | |
5769 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5770 | (int) BFD_RELOC_LO16, AT); | |
5771 | break; | |
5772 | ||
5773 | case M_USH_A: | |
5774 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5775 | if (breg != 0) |
5776 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5777 | mips_isa < 3 ? "addu" : "daddu", | |
5778 | "d,v,t", AT, AT, breg); | |
b9129c6f | 5779 | if (! target_big_endian) |
adcf2b9d ILT |
5780 | expr1.X_add_number = 0; |
5781 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5782 | (int) BFD_RELOC_LO16, AT); | |
5783 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
5784 | treg, 8); | |
b9129c6f | 5785 | if (! target_big_endian) |
adcf2b9d ILT |
5786 | expr1.X_add_number = 1; |
5787 | else | |
5788 | expr1.X_add_number = 0; | |
5789 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5790 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 5791 | if (! target_big_endian) |
adcf2b9d ILT |
5792 | expr1.X_add_number = 0; |
5793 | else | |
5794 | expr1.X_add_number = 1; | |
5795 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5796 | (int) BFD_RELOC_LO16, AT); | |
5797 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5798 | treg, 8); | |
5799 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5800 | treg, AT); | |
670a50eb | 5801 | break; |
3d3c5039 ILT |
5802 | |
5803 | default: | |
670a50eb | 5804 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 5805 | break; |
3d3c5039 | 5806 | } |
670a50eb ILT |
5807 | if (mips_noat) |
5808 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
5809 | } |
5810 | ||
cc5703cd | 5811 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 5812 | |
3d3c5039 | 5813 | static void |
cc5703cd | 5814 | mips16_macro (ip) |
3d3c5039 ILT |
5815 | struct mips_cl_insn *ip; |
5816 | { | |
cc5703cd ILT |
5817 | int mask; |
5818 | int xreg, yreg, zreg, tmp; | |
5819 | int icnt; | |
5820 | expressionS expr1; | |
5821 | int dbl; | |
5822 | const char *s, *s2, *s3; | |
3d3c5039 | 5823 | |
cc5703cd | 5824 | mask = ip->insn_mo->mask; |
3d3c5039 | 5825 | |
cc5703cd ILT |
5826 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
5827 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
5828 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 5829 | |
cc5703cd | 5830 | icnt = 0; |
8358c818 | 5831 | |
cc5703cd ILT |
5832 | expr1.X_op = O_constant; |
5833 | expr1.X_op_symbol = NULL; | |
5834 | expr1.X_add_symbol = NULL; | |
5835 | expr1.X_add_number = 1; | |
8358c818 | 5836 | |
cc5703cd | 5837 | dbl = 0; |
517078c1 | 5838 | |
cc5703cd ILT |
5839 | switch (mask) |
5840 | { | |
5841 | default: | |
5842 | internalError (); | |
5843 | ||
5844 | case M_DDIV_3: | |
5845 | dbl = 1; | |
5846 | case M_DIV_3: | |
5847 | s = "mflo"; | |
5848 | goto do_div3; | |
5849 | case M_DREM_3: | |
5850 | dbl = 1; | |
5851 | case M_REM_3: | |
5852 | s = "mfhi"; | |
5853 | do_div3: | |
fbcfacb7 | 5854 | mips_emit_delays (true); |
cc5703cd ILT |
5855 | ++mips_noreorder; |
5856 | mips_any_noreorder = 1; | |
5857 | macro_build ((char *) NULL, &icnt, NULL, | |
5858 | dbl ? "ddiv" : "div", | |
5859 | "0,x,y", xreg, yreg); | |
8a8121d5 | 5860 | expr1.X_add_number = 2; |
cc5703cd | 5861 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5862 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5863 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
5864 | since that causes an overflow. We should do that as well, | |
5865 | but I don't see how to do the comparisons without a temporary | |
5866 | register. */ | |
5867 | --mips_noreorder; | |
5868 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
5869 | break; | |
5870 | ||
5871 | case M_DIVU_3: | |
5872 | s = "divu"; | |
5873 | s2 = "mflo"; | |
5874 | goto do_divu3; | |
5875 | case M_REMU_3: | |
5876 | s = "divu"; | |
5877 | s2 = "mfhi"; | |
5878 | goto do_divu3; | |
5879 | case M_DDIVU_3: | |
5880 | s = "ddivu"; | |
5881 | s2 = "mflo"; | |
5882 | goto do_divu3; | |
5883 | case M_DREMU_3: | |
5884 | s = "ddivu"; | |
5885 | s2 = "mfhi"; | |
5886 | do_divu3: | |
fbcfacb7 | 5887 | mips_emit_delays (true); |
cc5703cd ILT |
5888 | ++mips_noreorder; |
5889 | mips_any_noreorder = 1; | |
5890 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 5891 | expr1.X_add_number = 2; |
cc5703cd | 5892 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5893 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5894 | --mips_noreorder; | |
5895 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
5896 | break; | |
5897 | ||
5898 | case M_DSUBU_I: | |
5899 | dbl = 1; | |
5900 | goto do_subu; | |
5901 | case M_SUBU_I: | |
5902 | do_subu: | |
5903 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5904 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
5905 | dbl ? "daddiu" : "addiu", | |
5906 | "y,x,4", yreg, xreg); | |
5907 | break; | |
5908 | ||
5909 | case M_SUBU_I_2: | |
5910 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5911 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
5912 | "x,k", xreg); | |
5913 | break; | |
5914 | ||
5915 | case M_DSUBU_I_2: | |
5916 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5917 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
5918 | "y,j", yreg); | |
5919 | break; | |
5920 | ||
5921 | case M_BEQ: | |
5922 | s = "cmp"; | |
5923 | s2 = "bteqz"; | |
5924 | goto do_branch; | |
5925 | case M_BNE: | |
5926 | s = "cmp"; | |
5927 | s2 = "btnez"; | |
5928 | goto do_branch; | |
5929 | case M_BLT: | |
5930 | s = "slt"; | |
5931 | s2 = "btnez"; | |
5932 | goto do_branch; | |
5933 | case M_BLTU: | |
5934 | s = "sltu"; | |
5935 | s2 = "btnez"; | |
5936 | goto do_branch; | |
5937 | case M_BLE: | |
5938 | s = "slt"; | |
5939 | s2 = "bteqz"; | |
5940 | goto do_reverse_branch; | |
5941 | case M_BLEU: | |
5942 | s = "sltu"; | |
5943 | s2 = "bteqz"; | |
5944 | goto do_reverse_branch; | |
5945 | case M_BGE: | |
5946 | s = "slt"; | |
5947 | s2 = "bteqz"; | |
5948 | goto do_branch; | |
5949 | case M_BGEU: | |
5950 | s = "sltu"; | |
5951 | s2 = "bteqz"; | |
5952 | goto do_branch; | |
5953 | case M_BGT: | |
5954 | s = "slt"; | |
5955 | s2 = "btnez"; | |
5956 | goto do_reverse_branch; | |
5957 | case M_BGTU: | |
5958 | s = "sltu"; | |
5959 | s2 = "btnez"; | |
5960 | ||
5961 | do_reverse_branch: | |
5962 | tmp = xreg; | |
5963 | xreg = yreg; | |
5964 | yreg = tmp; | |
5965 | ||
5966 | do_branch: | |
5967 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
5968 | xreg, yreg); | |
5969 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
5970 | break; | |
5971 | ||
5972 | case M_BEQ_I: | |
5973 | s = "cmpi"; | |
5974 | s2 = "bteqz"; | |
5975 | s3 = "x,U"; | |
5976 | goto do_branch_i; | |
5977 | case M_BNE_I: | |
5978 | s = "cmpi"; | |
5979 | s2 = "btnez"; | |
5980 | s3 = "x,U"; | |
5981 | goto do_branch_i; | |
5982 | case M_BLT_I: | |
5983 | s = "slti"; | |
5984 | s2 = "btnez"; | |
5985 | s3 = "x,8"; | |
5986 | goto do_branch_i; | |
5987 | case M_BLTU_I: | |
5988 | s = "sltiu"; | |
5989 | s2 = "btnez"; | |
5990 | s3 = "x,8"; | |
5991 | goto do_branch_i; | |
5992 | case M_BLE_I: | |
5993 | s = "slti"; | |
5994 | s2 = "btnez"; | |
5995 | s3 = "x,8"; | |
5996 | goto do_addone_branch_i; | |
5997 | case M_BLEU_I: | |
5998 | s = "sltiu"; | |
5999 | s2 = "btnez"; | |
6000 | s3 = "x,8"; | |
6001 | goto do_addone_branch_i; | |
6002 | case M_BGE_I: | |
6003 | s = "slti"; | |
6004 | s2 = "bteqz"; | |
6005 | s3 = "x,8"; | |
6006 | goto do_branch_i; | |
6007 | case M_BGEU_I: | |
6008 | s = "sltiu"; | |
6009 | s2 = "bteqz"; | |
6010 | s3 = "x,8"; | |
6011 | goto do_branch_i; | |
6012 | case M_BGT_I: | |
6013 | s = "slti"; | |
6014 | s2 = "bteqz"; | |
6015 | s3 = "x,8"; | |
6016 | goto do_addone_branch_i; | |
6017 | case M_BGTU_I: | |
6018 | s = "sltiu"; | |
6019 | s2 = "bteqz"; | |
6020 | s3 = "x,8"; | |
6021 | ||
6022 | do_addone_branch_i: | |
6023 | ++imm_expr.X_add_number; | |
6024 | ||
6025 | do_branch_i: | |
6026 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6027 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6028 | break; | |
18e0764d ILT |
6029 | |
6030 | case M_ABS: | |
6031 | expr1.X_add_number = 0; | |
6032 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6033 | if (xreg != yreg) | |
6034 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6035 | "move", "y,X", xreg, yreg); | |
6036 | expr1.X_add_number = 2; | |
6037 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6038 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6039 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6040 | } |
6041 | } | |
6042 | ||
6043 | /* This routine assembles an instruction into its binary format. As a | |
6044 | side effect, it sets one of the global variables imm_reloc or | |
6045 | offset_reloc to the type of relocation to do if one of the operands | |
6046 | is an address expression. */ | |
6047 | ||
6048 | static void | |
6049 | mips_ip (str, ip) | |
6050 | char *str; | |
6051 | struct mips_cl_insn *ip; | |
6052 | { | |
6053 | char *s; | |
6054 | const char *args; | |
6055 | char c; | |
6056 | struct mips_opcode *insn; | |
6057 | char *argsStart; | |
6058 | unsigned int regno; | |
6059 | unsigned int lastregno = 0; | |
6060 | char *s_reset; | |
6061 | ||
6062 | insn_error = NULL; | |
6063 | ||
6064 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) | |
6065 | continue; | |
6066 | switch (*s) | |
6067 | { | |
6068 | case '\0': | |
6069 | break; | |
6070 | ||
6071 | case ' ': | |
6072 | *s++ = '\0'; | |
6073 | break; | |
6074 | ||
6075 | default: | |
6076 | as_fatal ("Unknown opcode: `%s'", str); | |
6077 | } | |
6078 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
6079 | { | |
6080 | insn_error = "unrecognized opcode"; | |
6081 | return; | |
6082 | } | |
6083 | argsStart = s; | |
6084 | for (;;) | |
6085 | { | |
6086 | int insn_isa; | |
6087 | ||
6088 | assert (strcmp (insn->name, str) == 0); | |
6089 | ||
6090 | if (insn->pinfo == INSN_MACRO) | |
6091 | insn_isa = insn->match; | |
6092 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6093 | insn_isa = 2; | |
6094 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6095 | insn_isa = 3; | |
6096 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6097 | insn_isa = 4; | |
6098 | else | |
6099 | insn_isa = 1; | |
6100 | ||
6101 | if (insn_isa > mips_isa | |
6102 | || ((insn->pinfo & INSN_ISA) == INSN_4650 | |
6103 | && ! mips_4650) | |
6104 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6105 | && ! mips_4010) | |
6106 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
6107 | && ! mips_4100)) | |
6108 | { | |
6109 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6110 | && strcmp (insn->name, insn[1].name) == 0) | |
6111 | { | |
6112 | ++insn; | |
6113 | continue; | |
6114 | } | |
6115 | if (insn_isa <= mips_isa) | |
6116 | insn_error = "opcode not supported on this processor"; | |
6117 | else | |
6118 | { | |
6119 | static char buf[100]; | |
6120 | ||
6121 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6122 | insn_error = buf; | |
6123 | } | |
6124 | return; | |
6125 | } | |
8358c818 | 6126 | |
670a50eb ILT |
6127 | ip->insn_mo = insn; |
6128 | ip->insn_opcode = insn->match; | |
6129 | for (args = insn->args;; ++args) | |
6130 | { | |
6131 | if (*s == ' ') | |
6132 | ++s; | |
6133 | switch (*args) | |
6134 | { | |
6135 | case '\0': /* end of args */ | |
6136 | if (*s == '\0') | |
6137 | return; | |
6138 | break; | |
3d3c5039 ILT |
6139 | |
6140 | case ',': | |
670a50eb ILT |
6141 | if (*s++ == *args) |
6142 | continue; | |
6143 | s--; | |
6144 | switch (*++args) | |
6145 | { | |
3d3c5039 ILT |
6146 | case 'r': |
6147 | case 'v': | |
670a50eb ILT |
6148 | ip->insn_opcode |= lastregno << 21; |
6149 | continue; | |
3d3c5039 ILT |
6150 | |
6151 | case 'w': | |
6152 | case 'W': | |
670a50eb ILT |
6153 | ip->insn_opcode |= lastregno << 16; |
6154 | continue; | |
3d3c5039 ILT |
6155 | |
6156 | case 'V': | |
670a50eb ILT |
6157 | ip->insn_opcode |= lastregno << 11; |
6158 | continue; | |
3d3c5039 | 6159 | } |
670a50eb | 6160 | break; |
3d3c5039 ILT |
6161 | |
6162 | case '(': | |
670a50eb ILT |
6163 | /* handle optional base register. |
6164 | Either the base register is omitted or | |
6165 | we must have a left paren. */ | |
6166 | /* this is dependent on the next operand specifier | |
6167 | is a 'b' for base register */ | |
6168 | assert (args[1] == 'b'); | |
6169 | if (*s == '\0') | |
6170 | return; | |
3d3c5039 | 6171 | |
670a50eb ILT |
6172 | case ')': /* these must match exactly */ |
6173 | if (*s++ == *args) | |
3d3c5039 | 6174 | continue; |
670a50eb ILT |
6175 | break; |
6176 | ||
6177 | case '<': /* must be at least one digit */ | |
6178 | /* | |
6179 | * According to the manual, if the shift amount is greater | |
6180 | * than 31 or less than 0 the the shift amount should be | |
6181 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6182 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6183 | */ |
6184 | my_getExpression (&imm_expr, s); | |
6185 | check_absolute_expr (ip, &imm_expr); | |
6186 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6187 | { | |
58d4951d ILT |
6188 | as_warn ("Improper shift amount (%ld)", |
6189 | (long) imm_expr.X_add_number); | |
9226253a | 6190 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6191 | } |
6192 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6193 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6194 | s = expr_end; |
6195 | continue; | |
6196 | ||
56c96faa ILT |
6197 | case '>': /* shift amount minus 32 */ |
6198 | my_getExpression (&imm_expr, s); | |
6199 | check_absolute_expr (ip, &imm_expr); | |
6200 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6201 | || (unsigned long) imm_expr.X_add_number > 63) | |
6202 | break; | |
6203 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6204 | imm_expr.X_op = O_absent; | |
6205 | s = expr_end; | |
6206 | continue; | |
6207 | ||
9226253a | 6208 | case 'k': /* cache code */ |
d8a1c247 | 6209 | case 'h': /* prefx code */ |
9226253a ILT |
6210 | my_getExpression (&imm_expr, s); |
6211 | check_absolute_expr (ip, &imm_expr); | |
6212 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6213 | { | |
d8a1c247 KR |
6214 | as_warn ("Invalid value for `%s' (%lu)", |
6215 | ip->insn_mo->name, | |
9226253a ILT |
6216 | (unsigned long) imm_expr.X_add_number); |
6217 | imm_expr.X_add_number &= 0x1f; | |
6218 | } | |
d8a1c247 KR |
6219 | if (*args == 'k') |
6220 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6221 | else | |
6222 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6223 | imm_expr.X_op = O_absent; |
6224 | s = expr_end; | |
6225 | continue; | |
6226 | ||
670a50eb ILT |
6227 | case 'c': /* break code */ |
6228 | my_getExpression (&imm_expr, s); | |
6229 | check_absolute_expr (ip, &imm_expr); | |
6230 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6231 | as_warn ("Illegal break code (%ld)", |
6232 | (long) imm_expr.X_add_number); | |
670a50eb | 6233 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6234 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6235 | s = expr_end; |
6236 | continue; | |
6237 | ||
918692a5 ILT |
6238 | case 'B': /* syscall code */ |
6239 | my_getExpression (&imm_expr, s); | |
6240 | check_absolute_expr (ip, &imm_expr); | |
6241 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6242 | as_warn ("Illegal syscall code (%ld)", |
6243 | (long) imm_expr.X_add_number); | |
918692a5 | 6244 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6245 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6246 | s = expr_end; |
6247 | continue; | |
6248 | ||
0aa07269 ILT |
6249 | case 'C': /* Coprocessor code */ |
6250 | my_getExpression (&imm_expr, s); | |
6251 | check_absolute_expr (ip, &imm_expr); | |
6252 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6253 | { | |
58d4951d ILT |
6254 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6255 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6256 | imm_expr.X_add_number &= ((1<<25) - 1); |
6257 | } | |
6258 | ip->insn_opcode |= imm_expr.X_add_number; | |
6259 | imm_expr.X_op = O_absent; | |
6260 | s = expr_end; | |
6261 | continue; | |
6262 | ||
670a50eb ILT |
6263 | case 'b': /* base register */ |
6264 | case 'd': /* destination register */ | |
6265 | case 's': /* source register */ | |
6266 | case 't': /* target register */ | |
6267 | case 'r': /* both target and source */ | |
6268 | case 'v': /* both dest and source */ | |
6269 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6270 | case 'E': /* coprocessor target register */ |
6271 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6272 | case 'x': /* ignore register name */ |
ff3a5c18 | 6273 | case 'z': /* must be zero register */ |
670a50eb ILT |
6274 | s_reset = s; |
6275 | if (s[0] == '$') | |
6276 | { | |
6277 | if (isdigit (s[1])) | |
6278 | { | |
6279 | ++s; | |
6280 | regno = 0; | |
6281 | do | |
6282 | { | |
6283 | regno *= 10; | |
6284 | regno += *s - '0'; | |
6285 | ++s; | |
6286 | } | |
6287 | while (isdigit (*s)); | |
0aa07269 ILT |
6288 | if (regno > 31) |
6289 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6290 | } |
0dd2d296 ILT |
6291 | else if (*args == 'E' || *args == 'G') |
6292 | goto notreg; | |
6293 | else | |
670a50eb | 6294 | { |
0aa07269 ILT |
6295 | if (s[1] == 'f' && s[2] == 'p') |
6296 | { | |
6297 | s += 3; | |
9226253a | 6298 | regno = FP; |
0aa07269 ILT |
6299 | } |
6300 | else if (s[1] == 's' && s[2] == 'p') | |
6301 | { | |
6302 | s += 3; | |
9226253a | 6303 | regno = SP; |
0aa07269 ILT |
6304 | } |
6305 | else if (s[1] == 'g' && s[2] == 'p') | |
6306 | { | |
6307 | s += 3; | |
9226253a | 6308 | regno = GP; |
0aa07269 ILT |
6309 | } |
6310 | else if (s[1] == 'a' && s[2] == 't') | |
6311 | { | |
6312 | s += 3; | |
9226253a | 6313 | regno = AT; |
0aa07269 | 6314 | } |
b2b8c24e ILT |
6315 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6316 | { | |
6317 | s += 4; | |
6318 | regno = KT0; | |
6319 | } | |
6320 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6321 | { | |
6322 | s += 4; | |
6323 | regno = KT1; | |
6324 | } | |
0aa07269 ILT |
6325 | else |
6326 | goto notreg; | |
670a50eb | 6327 | } |
9753202d ILT |
6328 | if (regno == AT |
6329 | && ! mips_noat | |
6330 | && *args != 'E' | |
6331 | && *args != 'G') | |
13fe1379 | 6332 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6333 | c = *args; |
6334 | if (*s == ' ') | |
6335 | s++; | |
6336 | if (args[1] != *s) | |
6337 | { | |
6338 | if (c == 'r' || c == 'v' || c == 'w') | |
6339 | { | |
6340 | regno = lastregno; | |
6341 | s = s_reset; | |
6342 | args++; | |
6343 | } | |
6344 | } | |
ff3a5c18 ILT |
6345 | /* 'z' only matches $0. */ |
6346 | if (c == 'z' && regno != 0) | |
6347 | break; | |
670a50eb ILT |
6348 | switch (c) |
6349 | { | |
3d3c5039 ILT |
6350 | case 'r': |
6351 | case 's': | |
6352 | case 'v': | |
6353 | case 'b': | |
670a50eb ILT |
6354 | ip->insn_opcode |= regno << 21; |
6355 | break; | |
3d3c5039 | 6356 | case 'd': |
918692a5 | 6357 | case 'G': |
670a50eb ILT |
6358 | ip->insn_opcode |= regno << 11; |
6359 | break; | |
3d3c5039 ILT |
6360 | case 'w': |
6361 | case 't': | |
918692a5 | 6362 | case 'E': |
670a50eb | 6363 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6364 | break; |
6365 | case 'x': | |
6366 | /* This case exists because on the r3000 trunc | |
6367 | expands into a macro which requires a gp | |
6368 | register. On the r6000 or r4000 it is | |
6369 | assembled into a single instruction which | |
6370 | ignores the register. Thus the insn version | |
6371 | is MIPS_ISA2 and uses 'x', and the macro | |
6372 | version is MIPS_ISA1 and uses 't'. */ | |
6373 | break; | |
ff3a5c18 ILT |
6374 | case 'z': |
6375 | /* This case is for the div instruction, which | |
6376 | acts differently if the destination argument | |
6377 | is $0. This only matches $0, and is checked | |
6378 | outside the switch. */ | |
6379 | break; | |
3d3c5039 | 6380 | } |
670a50eb ILT |
6381 | lastregno = regno; |
6382 | continue; | |
3d3c5039 ILT |
6383 | } |
6384 | notreg: | |
670a50eb ILT |
6385 | switch (*args++) |
6386 | { | |
3d3c5039 ILT |
6387 | case 'r': |
6388 | case 'v': | |
670a50eb ILT |
6389 | ip->insn_opcode |= lastregno << 21; |
6390 | continue; | |
3d3c5039 | 6391 | case 'w': |
670a50eb ILT |
6392 | ip->insn_opcode |= lastregno << 16; |
6393 | continue; | |
3d3c5039 | 6394 | } |
670a50eb | 6395 | break; |
3d3c5039 | 6396 | |
670a50eb ILT |
6397 | case 'D': /* floating point destination register */ |
6398 | case 'S': /* floating point source register */ | |
6399 | case 'T': /* floating point target register */ | |
d8a1c247 | 6400 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6401 | case 'V': |
6402 | case 'W': | |
670a50eb ILT |
6403 | s_reset = s; |
6404 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6405 | { | |
6406 | s += 2; | |
6407 | regno = 0; | |
6408 | do | |
6409 | { | |
6410 | regno *= 10; | |
6411 | regno += *s - '0'; | |
6412 | ++s; | |
6413 | } | |
6414 | while (isdigit (*s)); | |
6415 | ||
6416 | if (regno > 31) | |
6417 | as_bad ("Invalid float register number (%d)", regno); | |
6418 | ||
9226253a ILT |
6419 | if ((regno & 1) != 0 |
6420 | && mips_isa < 3 | |
538034cf ILT |
6421 | && ! (strcmp (str, "mtc1") == 0 |
6422 | || strcmp (str, "mfc1") == 0 | |
6423 | || strcmp (str, "lwc1") == 0 | |
6424 | || strcmp (str, "swc1") == 0 | |
6425 | || strcmp (str, "l.s") == 0 | |
6426 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6427 | as_warn ("Float register should be even, was %d", |
6428 | regno); | |
6429 | ||
6430 | c = *args; | |
6431 | if (*s == ' ') | |
6432 | s++; | |
6433 | if (args[1] != *s) | |
6434 | { | |
6435 | if (c == 'V' || c == 'W') | |
6436 | { | |
6437 | regno = lastregno; | |
6438 | s = s_reset; | |
6439 | args++; | |
3d3c5039 ILT |
6440 | } |
6441 | } | |
670a50eb ILT |
6442 | switch (c) |
6443 | { | |
3d3c5039 | 6444 | case 'D': |
670a50eb ILT |
6445 | ip->insn_opcode |= regno << 6; |
6446 | break; | |
3d3c5039 ILT |
6447 | case 'V': |
6448 | case 'S': | |
670a50eb ILT |
6449 | ip->insn_opcode |= regno << 11; |
6450 | break; | |
3d3c5039 ILT |
6451 | case 'W': |
6452 | case 'T': | |
670a50eb | 6453 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6454 | break; |
6455 | case 'R': | |
6456 | ip->insn_opcode |= regno << 21; | |
6457 | break; | |
3d3c5039 | 6458 | } |
670a50eb ILT |
6459 | lastregno = regno; |
6460 | continue; | |
3d3c5039 | 6461 | } |
670a50eb ILT |
6462 | switch (*args++) |
6463 | { | |
3d3c5039 | 6464 | case 'V': |
670a50eb ILT |
6465 | ip->insn_opcode |= lastregno << 11; |
6466 | continue; | |
3d3c5039 | 6467 | case 'W': |
670a50eb ILT |
6468 | ip->insn_opcode |= lastregno << 16; |
6469 | continue; | |
3d3c5039 | 6470 | } |
670a50eb | 6471 | break; |
3d3c5039 ILT |
6472 | |
6473 | case 'I': | |
670a50eb | 6474 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6475 | if (imm_expr.X_op != O_big |
6476 | && imm_expr.X_op != O_constant) | |
6477 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6478 | s = expr_end; |
6479 | continue; | |
3d3c5039 ILT |
6480 | |
6481 | case 'A': | |
670a50eb ILT |
6482 | my_getExpression (&offset_expr, s); |
6483 | imm_reloc = BFD_RELOC_32; | |
6484 | s = expr_end; | |
6485 | continue; | |
3d3c5039 ILT |
6486 | |
6487 | case 'F': | |
19ed8960 ILT |
6488 | case 'L': |
6489 | case 'f': | |
6490 | case 'l': | |
6491 | { | |
6492 | int f64; | |
6493 | char *save_in; | |
6494 | char *err; | |
6495 | unsigned char temp[8]; | |
604633ae ILT |
6496 | int len; |
6497 | unsigned int length; | |
19ed8960 ILT |
6498 | segT seg; |
6499 | subsegT subseg; | |
6500 | char *p; | |
6501 | ||
6502 | /* These only appear as the last operand in an | |
6503 | instruction, and every instruction that accepts | |
6504 | them in any variant accepts them in all variants. | |
6505 | This means we don't have to worry about backing out | |
6506 | any changes if the instruction does not match. | |
6507 | ||
6508 | The difference between them is the size of the | |
6509 | floating point constant and where it goes. For 'F' | |
6510 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6511 | is 32 bits. Where the constant is placed is based | |
6512 | on how the MIPS assembler does things: | |
6513 | F -- .rdata | |
6514 | L -- .lit8 | |
6515 | f -- immediate value | |
6516 | l -- .lit4 | |
0dd2d296 | 6517 | |
55933a58 ILT |
6518 | The .lit4 and .lit8 sections are only used if |
6519 | permitted by the -G argument. | |
6520 | ||
6521 | When generating embedded PIC code, we use the | |
6522 | .lit8 section but not the .lit4 section (we can do | |
6523 | .lit4 inline easily; we need to put .lit8 | |
6524 | somewhere in the data segment, and using .lit8 | |
6525 | permits the linker to eventually combine identical | |
6526 | .lit8 entries). */ | |
19ed8960 ILT |
6527 | |
6528 | f64 = *args == 'F' || *args == 'L'; | |
6529 | ||
6530 | save_in = input_line_pointer; | |
6531 | input_line_pointer = s; | |
604633ae ILT |
6532 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6533 | length = len; | |
19ed8960 ILT |
6534 | s = input_line_pointer; |
6535 | input_line_pointer = save_in; | |
6536 | if (err != NULL && *err != '\0') | |
6537 | { | |
6538 | as_bad ("Bad floating point constant: %s", err); | |
6539 | memset (temp, '\0', sizeof temp); | |
6540 | length = f64 ? 8 : 4; | |
6541 | } | |
6542 | ||
6543 | assert (length == (f64 ? 8 : 4)); | |
6544 | ||
0dd2d296 | 6545 | if (*args == 'f' |
55933a58 | 6546 | || (*args == 'l' |
1dc1e798 KR |
6547 | && (! USE_GLOBAL_POINTER_OPT |
6548 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6549 | || g_switch_value < 4) |
1113140a | 6550 | )) |
19ed8960 ILT |
6551 | { |
6552 | imm_expr.X_op = O_constant; | |
b9129c6f | 6553 | if (! target_big_endian) |
19ed8960 ILT |
6554 | imm_expr.X_add_number = |
6555 | (((((((int) temp[3] << 8) | |
6556 | | temp[2]) << 8) | |
6557 | | temp[1]) << 8) | |
6558 | | temp[0]); | |
6559 | else | |
6560 | imm_expr.X_add_number = | |
6561 | (((((((int) temp[0] << 8) | |
6562 | | temp[1]) << 8) | |
6563 | | temp[2]) << 8) | |
6564 | | temp[3]); | |
6565 | } | |
6566 | else | |
6567 | { | |
0dd2d296 ILT |
6568 | const char *newname; |
6569 | segT new_seg; | |
6570 | ||
19ed8960 ILT |
6571 | /* Switch to the right section. */ |
6572 | seg = now_seg; | |
6573 | subseg = now_subseg; | |
6574 | switch (*args) | |
6575 | { | |
0dd2d296 | 6576 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6577 | case 'L': |
1113140a | 6578 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6579 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6580 | newname = ".lit8"; |
0dd2d296 ILT |
6581 | break; |
6582 | case 'F': | |
d2c71068 | 6583 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6584 | break; |
6585 | case 'l': | |
1dc1e798 KR |
6586 | assert (!USE_GLOBAL_POINTER_OPT |
6587 | || g_switch_value >= 4); | |
0dd2d296 | 6588 | newname = ".lit4"; |
19ed8960 ILT |
6589 | break; |
6590 | } | |
0dd2d296 | 6591 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6592 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6593 | bfd_set_section_flags (stdoutput, new_seg, | |
6594 | (SEC_ALLOC | |
6595 | | SEC_LOAD | |
6596 | | SEC_READONLY | |
6597 | | SEC_DATA)); | |
0221ddf7 | 6598 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
6599 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6600 | record_alignment (new_seg, 4); | |
6601 | else | |
6602 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6603 | if (seg == now_seg) |
6604 | as_bad ("Can't use floating point insn in this section"); | |
6605 | ||
6606 | /* Set the argument to the current address in the | |
6e8dda9c | 6607 | section. */ |
19ed8960 ILT |
6608 | offset_expr.X_op = O_symbol; |
6609 | offset_expr.X_add_symbol = | |
6610 | symbol_new ("L0\001", now_seg, | |
6611 | (valueT) frag_now_fix (), frag_now); | |
6612 | offset_expr.X_add_number = 0; | |
6613 | ||
6614 | /* Put the floating point number into the section. */ | |
604633ae | 6615 | p = frag_more ((int) length); |
19ed8960 ILT |
6616 | memcpy (p, temp, length); |
6617 | ||
6618 | /* Switch back to the original section. */ | |
6619 | subseg_set (seg, subseg); | |
6620 | } | |
6621 | } | |
670a50eb ILT |
6622 | continue; |
6623 | ||
6624 | case 'i': /* 16 bit unsigned immediate */ | |
6625 | case 'j': /* 16 bit signed immediate */ | |
6626 | imm_reloc = BFD_RELOC_LO16; | |
6627 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6628 | if (c != '\0') |
670a50eb ILT |
6629 | { |
6630 | if (c != 'l') | |
6631 | { | |
5ac34ac3 | 6632 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6633 | imm_expr.X_add_number = |
6634 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6635 | else if (c == 'h') | |
867a58b3 ILT |
6636 | { |
6637 | imm_reloc = BFD_RELOC_HI16_S; | |
6638 | imm_unmatched_hi = true; | |
6639 | } | |
670a50eb ILT |
6640 | else |
6641 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6642 | } |
670a50eb | 6643 | } |
670a50eb ILT |
6644 | if (*args == 'i') |
6645 | { | |
344a8d61 | 6646 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6647 | || ((imm_expr.X_add_number < 0 |
6648 | || imm_expr.X_add_number >= 0x10000) | |
6649 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6650 | { |
6651 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6652 | !strcmp (insn->name, insn[1].name)) | |
6653 | break; | |
9753202d ILT |
6654 | if (imm_expr.X_op != O_constant |
6655 | && imm_expr.X_op != O_big) | |
6656 | insn_error = "absolute expression required"; | |
6657 | else | |
6658 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6659 | } |
670a50eb ILT |
6660 | } |
6661 | else | |
6662 | { | |
d9aba805 ILT |
6663 | int more; |
6664 | offsetT max; | |
6665 | ||
be22008b ILT |
6666 | /* The upper bound should be 0x8000, but |
6667 | unfortunately the MIPS assembler accepts numbers | |
6668 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6669 | we want to be compatible. We only permit this |
6670 | extended range for an instruction which does not | |
6671 | provide any further alternates, since those | |
6672 | alternates may handle other cases. People should | |
6673 | use the numbers they mean, rather than relying on | |
6674 | a mysterious sign extension. */ | |
6675 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6676 | strcmp (insn->name, insn[1].name) == 0); | |
6677 | if (more) | |
6678 | max = 0x8000; | |
6679 | else | |
6680 | max = 0x10000; | |
344a8d61 | 6681 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6682 | || ((imm_expr.X_add_number < -0x8000 |
6683 | || imm_expr.X_add_number >= max) | |
6684 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
6685 | || (more |
6686 | && imm_expr.X_add_number < 0 | |
6687 | && mips_isa >= 3 | |
6688 | && imm_expr.X_unsigned | |
6689 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 6690 | { |
d9aba805 | 6691 | if (more) |
99c24539 | 6692 | break; |
9753202d ILT |
6693 | if (imm_expr.X_op != O_constant |
6694 | && imm_expr.X_op != O_big) | |
6695 | insn_error = "absolute expression required"; | |
6696 | else | |
6697 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 6698 | } |
3d3c5039 | 6699 | } |
670a50eb ILT |
6700 | s = expr_end; |
6701 | continue; | |
6702 | ||
6703 | case 'o': /* 16 bit offset */ | |
6704 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
6705 | |
6706 | /* If this value won't fit into a 16 bit offset, then go | |
6707 | find a macro that will generate the 32 bit offset | |
6708 | code pattern. As a special hack, we accept the | |
6709 | difference of two local symbols as a constant. This | |
6710 | is required to suppose embedded PIC switches, which | |
6711 | use an instruction which looks like | |
6712 | lw $4,$L12-$LS12($4) | |
6713 | The problem with handling this in a more general | |
6714 | fashion is that the macro function doesn't expect to | |
6715 | see anything which can be handled in a single | |
6716 | constant instruction. */ | |
6f0b87c3 SS |
6717 | if (c == 0 |
6718 | && (offset_expr.X_op != O_constant | |
6719 | || offset_expr.X_add_number >= 0x8000 | |
6720 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
6721 | && (mips_pic != EMBEDDED_PIC |
6722 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
6723 | || now_seg != text_section |
6724 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
6725 | != text_section))) | |
670a50eb | 6726 | break; |
3d3c5039 | 6727 | |
670a50eb ILT |
6728 | offset_reloc = BFD_RELOC_LO16; |
6729 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
6730 | { |
6731 | assert (offset_expr.X_op == O_constant); | |
6732 | offset_expr.X_add_number = | |
6733 | (offset_expr.X_add_number >> 16) & 0xffff; | |
6734 | } | |
cc5703cd ILT |
6735 | s = expr_end; |
6736 | continue; | |
6737 | ||
6738 | case 'p': /* pc relative offset */ | |
6739 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
6740 | my_getExpression (&offset_expr, s); | |
6741 | s = expr_end; | |
6742 | continue; | |
6743 | ||
6744 | case 'u': /* upper 16 bits */ | |
6745 | c = my_getSmallExpression (&imm_expr, s); | |
6746 | if (imm_expr.X_op == O_constant | |
6747 | && (imm_expr.X_add_number < 0 | |
6748 | || imm_expr.X_add_number >= 0x10000)) | |
6749 | as_bad ("lui expression not in range 0..65535"); | |
6750 | imm_reloc = BFD_RELOC_LO16; | |
6751 | if (c) | |
6752 | { | |
6753 | if (c != 'l') | |
6754 | { | |
6755 | if (imm_expr.X_op == O_constant) | |
6756 | imm_expr.X_add_number = | |
6757 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6758 | else if (c == 'h') | |
6759 | { | |
6760 | imm_reloc = BFD_RELOC_HI16_S; | |
6761 | imm_unmatched_hi = true; | |
6762 | } | |
6763 | else | |
6764 | imm_reloc = BFD_RELOC_HI16; | |
6765 | } | |
6766 | } | |
6767 | s = expr_end; | |
6768 | continue; | |
6769 | ||
6770 | case 'a': /* 26 bit address */ | |
6771 | my_getExpression (&offset_expr, s); | |
6772 | s = expr_end; | |
6773 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
6774 | continue; | |
6775 | ||
6776 | case 'N': /* 3 bit branch condition code */ | |
6777 | case 'M': /* 3 bit compare condition code */ | |
6778 | if (strncmp (s, "$fcc", 4) != 0) | |
6779 | break; | |
6780 | s += 4; | |
6781 | regno = 0; | |
6782 | do | |
6783 | { | |
6784 | regno *= 10; | |
6785 | regno += *s - '0'; | |
6786 | ++s; | |
6787 | } | |
6788 | while (isdigit (*s)); | |
6789 | if (regno > 7) | |
6790 | as_bad ("invalid condition code register $fcc%d", regno); | |
6791 | if (*args == 'N') | |
6792 | ip->insn_opcode |= regno << OP_SH_BCC; | |
6793 | else | |
6794 | ip->insn_opcode |= regno << OP_SH_CCC; | |
6795 | continue; | |
6796 | ||
6797 | default: | |
6798 | fprintf (stderr, "bad char = '%c'\n", *args); | |
6799 | internalError (); | |
6800 | } | |
6801 | break; | |
6802 | } | |
6803 | /* Args don't match. */ | |
6804 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6805 | !strcmp (insn->name, insn[1].name)) | |
6806 | { | |
6807 | ++insn; | |
6808 | s = argsStart; | |
6809 | continue; | |
6810 | } | |
6811 | insn_error = "illegal operands"; | |
6812 | return; | |
6813 | } | |
6814 | } | |
6815 | ||
6816 | /* This routine assembles an instruction into its binary format when | |
6817 | assembling for the mips16. As a side effect, it sets one of the | |
6818 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
6819 | relocation to do if one of the operands is an address expression. |
6820 | It also sets mips16_small and mips16_ext if the user explicitly | |
6821 | requested a small or extended instruction. */ | |
cc5703cd ILT |
6822 | |
6823 | static void | |
6824 | mips16_ip (str, ip) | |
6825 | char *str; | |
6826 | struct mips_cl_insn *ip; | |
6827 | { | |
6828 | char *s; | |
cc5703cd ILT |
6829 | const char *args; |
6830 | struct mips_opcode *insn; | |
6831 | char *argsstart; | |
6832 | unsigned int regno; | |
6833 | unsigned int lastregno = 0; | |
6834 | char *s_reset; | |
6835 | ||
6836 | insn_error = NULL; | |
6837 | ||
8728fa92 ILT |
6838 | mips16_small = false; |
6839 | mips16_ext = false; | |
cc5703cd ILT |
6840 | |
6841 | for (s = str; islower (*s); ++s) | |
6842 | ; | |
6843 | switch (*s) | |
6844 | { | |
6845 | case '\0': | |
6846 | break; | |
6847 | ||
6848 | case ' ': | |
6849 | *s++ = '\0'; | |
6850 | break; | |
6851 | ||
6852 | case '.': | |
6853 | if (s[1] == 't' && s[2] == ' ') | |
6854 | { | |
6855 | *s = '\0'; | |
8728fa92 | 6856 | mips16_small = true; |
cc5703cd ILT |
6857 | s += 3; |
6858 | break; | |
6859 | } | |
6860 | else if (s[1] == 'e' && s[2] == ' ') | |
6861 | { | |
6862 | *s = '\0'; | |
8728fa92 | 6863 | mips16_ext = true; |
cc5703cd ILT |
6864 | s += 3; |
6865 | break; | |
6866 | } | |
6867 | /* Fall through. */ | |
6868 | default: | |
6869 | insn_error = "unknown opcode"; | |
6870 | return; | |
6871 | } | |
6872 | ||
8728fa92 ILT |
6873 | if (! mips16_autoextend && ! mips16_ext) |
6874 | mips16_small = true; | |
6875 | ||
cc5703cd ILT |
6876 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
6877 | { | |
6878 | insn_error = "unrecognized opcode"; | |
6879 | return; | |
6880 | } | |
6881 | ||
6882 | argsstart = s; | |
6883 | for (;;) | |
6884 | { | |
6885 | assert (strcmp (insn->name, str) == 0); | |
6886 | ||
6887 | ip->insn_mo = insn; | |
6888 | ip->insn_opcode = insn->match; | |
6889 | ip->use_extend = false; | |
6890 | imm_expr.X_op = O_absent; | |
6891 | imm_reloc = BFD_RELOC_UNUSED; | |
6892 | offset_expr.X_op = O_absent; | |
6893 | offset_reloc = BFD_RELOC_UNUSED; | |
6894 | for (args = insn->args; 1; ++args) | |
6895 | { | |
6896 | int c; | |
6897 | ||
6898 | if (*s == ' ') | |
6899 | ++s; | |
6900 | ||
6901 | /* In this switch statement we call break if we did not find | |
6902 | a match, continue if we did find a match, or return if we | |
6903 | are done. */ | |
6904 | ||
6905 | c = *args; | |
6906 | switch (c) | |
6907 | { | |
6908 | case '\0': | |
6909 | if (*s == '\0') | |
6910 | { | |
6911 | /* Stuff the immediate value in now, if we can. */ | |
6912 | if (imm_expr.X_op == O_constant | |
6913 | && imm_reloc > BFD_RELOC_UNUSED | |
6914 | && insn->pinfo != INSN_MACRO) | |
6915 | { | |
15e69f98 ILT |
6916 | mips16_immed ((char *) NULL, 0, |
6917 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
6918 | imm_expr.X_add_number, true, mips16_small, |
6919 | mips16_ext, &ip->insn_opcode, | |
6920 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
6921 | imm_expr.X_op = O_absent; |
6922 | imm_reloc = BFD_RELOC_UNUSED; | |
6923 | } | |
6924 | ||
6925 | return; | |
6926 | } | |
6927 | break; | |
6928 | ||
6929 | case ',': | |
6930 | if (*s++ == c) | |
6931 | continue; | |
6932 | s--; | |
6933 | switch (*++args) | |
6934 | { | |
6935 | case 'v': | |
6936 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6937 | continue; | |
6938 | case 'w': | |
6939 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6940 | continue; | |
6941 | } | |
6942 | break; | |
6943 | ||
6944 | case '(': | |
6945 | case ')': | |
6946 | if (*s++ == c) | |
6947 | continue; | |
6948 | break; | |
6949 | ||
6950 | case 'v': | |
6951 | case 'w': | |
6952 | if (s[0] != '$') | |
6953 | { | |
6954 | if (c == 'v') | |
6955 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6956 | else | |
6957 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6958 | ++args; | |
6959 | continue; | |
6960 | } | |
6961 | /* Fall through. */ | |
6962 | case 'x': | |
6963 | case 'y': | |
6964 | case 'z': | |
6965 | case 'Z': | |
6966 | case '0': | |
6967 | case 'S': | |
6968 | case 'R': | |
6969 | case 'X': | |
6970 | case 'Y': | |
6971 | if (s[0] != '$') | |
6972 | break; | |
6973 | s_reset = s; | |
6974 | if (isdigit (s[1])) | |
6975 | { | |
6976 | ++s; | |
6977 | regno = 0; | |
6978 | do | |
6979 | { | |
6980 | regno *= 10; | |
6981 | regno += *s - '0'; | |
6982 | ++s; | |
6983 | } | |
6984 | while (isdigit (*s)); | |
6985 | if (regno > 31) | |
6986 | { | |
6987 | as_bad ("invalid register number (%d)", regno); | |
6988 | regno = 2; | |
6989 | } | |
6990 | } | |
6991 | else | |
6992 | { | |
6993 | if (s[1] == 'f' && s[2] == 'p') | |
6994 | { | |
6995 | s += 3; | |
6996 | regno = FP; | |
6997 | } | |
6998 | else if (s[1] == 's' && s[2] == 'p') | |
6999 | { | |
7000 | s += 3; | |
7001 | regno = SP; | |
7002 | } | |
7003 | else if (s[1] == 'g' && s[2] == 'p') | |
7004 | { | |
7005 | s += 3; | |
7006 | regno = GP; | |
7007 | } | |
7008 | else if (s[1] == 'a' && s[2] == 't') | |
7009 | { | |
7010 | s += 3; | |
7011 | regno = AT; | |
7012 | } | |
7013 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7014 | { | |
7015 | s += 4; | |
7016 | regno = KT0; | |
7017 | } | |
7018 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7019 | { | |
7020 | s += 4; | |
7021 | regno = KT1; | |
7022 | } | |
7023 | else | |
7024 | break; | |
7025 | } | |
7026 | ||
7027 | if (*s == ' ') | |
7028 | ++s; | |
7029 | if (args[1] != *s) | |
7030 | { | |
7031 | if (c == 'v' || c == 'w') | |
7032 | { | |
7033 | regno = mips16_to_32_reg_map[lastregno]; | |
7034 | s = s_reset; | |
7035 | args++; | |
7036 | } | |
7037 | } | |
7038 | ||
7039 | switch (c) | |
7040 | { | |
7041 | case 'x': | |
7042 | case 'y': | |
7043 | case 'z': | |
7044 | case 'v': | |
7045 | case 'w': | |
7046 | case 'Z': | |
7047 | regno = mips32_to_16_reg_map[regno]; | |
7048 | break; | |
7049 | ||
7050 | case '0': | |
7051 | if (regno != 0) | |
7052 | regno = ILLEGAL_REG; | |
7053 | break; | |
7054 | ||
7055 | case 'S': | |
7056 | if (regno != SP) | |
7057 | regno = ILLEGAL_REG; | |
7058 | break; | |
7059 | ||
7060 | case 'R': | |
7061 | if (regno != RA) | |
7062 | regno = ILLEGAL_REG; | |
7063 | break; | |
7064 | ||
7065 | case 'X': | |
7066 | case 'Y': | |
7067 | if (regno == AT && ! mips_noat) | |
7068 | as_warn ("used $at without \".set noat\""); | |
7069 | break; | |
7070 | ||
7071 | default: | |
7072 | internalError (); | |
7073 | } | |
7074 | ||
7075 | if (regno == ILLEGAL_REG) | |
7076 | break; | |
7077 | ||
7078 | switch (c) | |
7079 | { | |
7080 | case 'x': | |
7081 | case 'v': | |
7082 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7083 | break; | |
7084 | case 'y': | |
7085 | case 'w': | |
7086 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7087 | break; | |
7088 | case 'z': | |
7089 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7090 | break; | |
7091 | case 'Z': | |
7092 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7093 | case '0': | |
7094 | case 'S': | |
7095 | case 'R': | |
7096 | break; | |
7097 | case 'X': | |
7098 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7099 | break; | |
7100 | case 'Y': | |
7101 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7102 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7103 | break; | |
7104 | default: | |
7105 | internalError (); | |
7106 | } | |
7107 | ||
7108 | lastregno = regno; | |
7109 | continue; | |
7110 | ||
7111 | case 'P': | |
7112 | if (strncmp (s, "$pc", 3) == 0) | |
7113 | { | |
7114 | s += 3; | |
7115 | continue; | |
7116 | } | |
7117 | break; | |
7118 | ||
7119 | case '<': | |
7120 | case '>': | |
7121 | case '[': | |
7122 | case ']': | |
7123 | case '4': | |
7124 | case '5': | |
7125 | case 'H': | |
7126 | case 'W': | |
7127 | case 'D': | |
7128 | case 'j': | |
7129 | case '8': | |
7130 | case 'V': | |
7131 | case 'C': | |
7132 | case 'U': | |
7133 | case 'k': | |
7134 | case 'K': | |
7135 | if (s[0] == '$' && isdigit (s[1])) | |
7136 | { | |
7137 | /* Looks like a register name. */ | |
7138 | break; | |
7139 | } | |
c0dea495 ILT |
7140 | |
7141 | if (s[0] == '(' | |
7142 | && args[1] == '(' | |
7143 | && s[1] == '$') | |
7144 | { | |
7145 | /* It looks like the expression was omitted before a | |
7146 | register indirection, which means that the | |
645cb4dc ILT |
7147 | expression is implicitly zero. We still set up |
7148 | imm_expr, so that we handle explicit extensions | |
7149 | correctly. */ | |
7150 | imm_expr.X_op = O_constant; | |
7151 | imm_expr.X_add_number = 0; | |
7152 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
c0dea495 ILT |
7153 | continue; |
7154 | } | |
7155 | ||
cc5703cd ILT |
7156 | my_getExpression (&imm_expr, s); |
7157 | /* We need to relax this instruction. */ | |
7158 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7159 | s = expr_end; | |
7160 | continue; | |
7161 | ||
7162 | case 'p': | |
7163 | case 'q': | |
7164 | case 'A': | |
7165 | case 'B': | |
7166 | case 'E': | |
7167 | /* We use offset_reloc rather than imm_reloc for the PC | |
7168 | relative operands. This lets macros with both | |
7169 | immediate and address operands work correctly. */ | |
7170 | if (s[0] == '$' && isdigit (s[1])) | |
7171 | { | |
7172 | /* Looks like a register name. */ | |
7173 | break; | |
7174 | } | |
670a50eb | 7175 | my_getExpression (&offset_expr, s); |
cc5703cd ILT |
7176 | /* We need to relax this instruction. */ |
7177 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7178 | s = expr_end; |
7179 | continue; | |
7180 | ||
cc5703cd ILT |
7181 | case '6': /* break code */ |
7182 | my_getExpression (&imm_expr, s); | |
7183 | check_absolute_expr (ip, &imm_expr); | |
7184 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7185 | { |
cc5703cd ILT |
7186 | as_warn ("Invalid value for `%s' (%lu)", |
7187 | ip->insn_mo->name, | |
7188 | (unsigned long) imm_expr.X_add_number); | |
7189 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7190 | } |
cc5703cd ILT |
7191 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7192 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7193 | s = expr_end; |
7194 | continue; | |
3d3c5039 | 7195 | |
670a50eb ILT |
7196 | case 'a': /* 26 bit address */ |
7197 | my_getExpression (&offset_expr, s); | |
7198 | s = expr_end; | |
cc5703cd ILT |
7199 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7200 | ip->insn_opcode <<= 16; | |
670a50eb | 7201 | continue; |
3d3c5039 | 7202 | |
cc5703cd ILT |
7203 | case 'l': /* register list for entry macro */ |
7204 | case 'L': /* register list for exit macro */ | |
7205 | { | |
7206 | int mask; | |
7207 | ||
7208 | if (c == 'l') | |
7209 | mask = 0; | |
7210 | else | |
7211 | mask = 7 << 3; | |
7212 | while (*s != '\0') | |
7213 | { | |
7214 | int reg1, reg2; | |
7215 | ||
7216 | while (*s == ' ' || *s == ',') | |
7217 | ++s; | |
7218 | if (*s != '$') | |
7219 | { | |
7220 | as_bad ("can't parse register list"); | |
7221 | break; | |
7222 | } | |
7223 | ++s; | |
7224 | reg1 = 0; | |
7225 | while (isdigit (*s)) | |
7226 | { | |
7227 | reg1 *= 10; | |
7228 | reg1 += *s - '0'; | |
7229 | ++s; | |
7230 | } | |
7231 | if (*s == ' ') | |
7232 | ++s; | |
7233 | if (*s != '-') | |
7234 | reg2 = reg1; | |
7235 | else | |
7236 | { | |
7237 | ++s; | |
7238 | if (*s != '$') | |
7239 | break; | |
7240 | ++s; | |
7241 | reg2 = 0; | |
7242 | while (isdigit (*s)) | |
7243 | { | |
7244 | reg2 *= 10; | |
7245 | reg2 += *s - '0'; | |
7246 | ++s; | |
7247 | } | |
7248 | } | |
7249 | if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
7250 | mask |= (reg2 - 3) << 3; | |
7251 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7252 | mask |= (reg2 - 15) << 1; | |
7253 | else if (reg1 == 31 && reg2 == 31) | |
7254 | mask |= 1; | |
7255 | else | |
7256 | as_bad ("invalid register list"); | |
7257 | } | |
7258 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
7259 | } | |
7260 | continue; | |
d8a1c247 | 7261 | |
3d3c5039 | 7262 | default: |
670a50eb | 7263 | internalError (); |
3d3c5039 | 7264 | } |
670a50eb | 7265 | break; |
3d3c5039 | 7266 | } |
cc5703cd | 7267 | |
670a50eb | 7268 | /* Args don't match. */ |
cc5703cd ILT |
7269 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7270 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7271 | { |
7272 | ++insn; | |
cc5703cd | 7273 | s = argsstart; |
670a50eb | 7274 | continue; |
3d3c5039 | 7275 | } |
cc5703cd | 7276 | |
9753202d | 7277 | insn_error = "illegal operands"; |
cc5703cd | 7278 | |
670a50eb | 7279 | return; |
3d3c5039 ILT |
7280 | } |
7281 | } | |
7282 | ||
cc5703cd ILT |
7283 | /* This structure holds information we know about a mips16 immediate |
7284 | argument type. */ | |
7285 | ||
7286 | struct mips16_immed_operand | |
7287 | { | |
7288 | /* The type code used in the argument string in the opcode table. */ | |
7289 | int type; | |
7290 | /* The number of bits in the short form of the opcode. */ | |
7291 | int nbits; | |
7292 | /* The number of bits in the extended form of the opcode. */ | |
7293 | int extbits; | |
7294 | /* The amount by which the short form is shifted when it is used; | |
7295 | for example, the sw instruction has a shift count of 2. */ | |
7296 | int shift; | |
7297 | /* The amount by which the short form is shifted when it is stored | |
7298 | into the instruction code. */ | |
7299 | int op_shift; | |
7300 | /* Non-zero if the short form is unsigned. */ | |
7301 | int unsp; | |
7302 | /* Non-zero if the extended form is unsigned. */ | |
7303 | int extu; | |
7304 | /* Non-zero if the value is PC relative. */ | |
7305 | int pcrel; | |
7306 | }; | |
7307 | ||
7308 | /* The mips16 immediate operand types. */ | |
7309 | ||
7310 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7311 | { | |
7312 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7313 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7314 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7315 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7316 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7317 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7318 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7319 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7320 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7321 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7322 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7323 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7324 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7325 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7326 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7327 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7328 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7329 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7330 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7331 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7332 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7333 | }; | |
7334 | ||
7335 | #define MIPS16_NUM_IMMED \ | |
7336 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7337 | ||
7338 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7339 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7340 | whether an extended value is needed; if one is needed, it sets | |
7341 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7342 | If SMALL is true, an unextended opcode was explicitly requested. | |
7343 | If EXT is true, an extended opcode was explicitly requested. If | |
7344 | WARN is true, warn if EXT does not match reality. */ | |
7345 | ||
7346 | static void | |
15e69f98 ILT |
7347 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7348 | extend) | |
7349 | char *file; | |
7350 | unsigned int line; | |
cc5703cd ILT |
7351 | int type; |
7352 | offsetT val; | |
7353 | boolean warn; | |
7354 | boolean small; | |
7355 | boolean ext; | |
7356 | unsigned long *insn; | |
7357 | boolean *use_extend; | |
7358 | unsigned short *extend; | |
7359 | { | |
7360 | register const struct mips16_immed_operand *op; | |
7361 | int mintiny, maxtiny; | |
7362 | boolean needext; | |
7363 | ||
7364 | op = mips16_immed_operands; | |
7365 | while (op->type != type) | |
7366 | { | |
7367 | ++op; | |
7368 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7369 | } | |
7370 | ||
7371 | if (op->unsp) | |
7372 | { | |
7373 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7374 | { | |
7375 | mintiny = 1; | |
7376 | maxtiny = 1 << op->nbits; | |
7377 | } | |
7378 | else | |
7379 | { | |
7380 | mintiny = 0; | |
7381 | maxtiny = (1 << op->nbits) - 1; | |
7382 | } | |
7383 | } | |
7384 | else | |
7385 | { | |
7386 | mintiny = - (1 << (op->nbits - 1)); | |
7387 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7388 | } | |
7389 | ||
7390 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7391 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7392 | val /= 2; |
cc5703cd ILT |
7393 | |
7394 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7395 | || val < (mintiny << op->shift) | |
7396 | || val > (maxtiny << op->shift)) | |
7397 | needext = true; | |
7398 | else | |
7399 | needext = false; | |
7400 | ||
7401 | if (warn && ext && ! needext) | |
15e69f98 | 7402 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7403 | if (small && needext) |
15e69f98 | 7404 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7405 | |
7406 | if (small || (! ext && ! needext)) | |
7407 | { | |
7408 | int insnval; | |
7409 | ||
7410 | *use_extend = false; | |
7411 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7412 | insnval <<= op->op_shift; | |
7413 | *insn |= insnval; | |
7414 | } | |
7415 | else | |
7416 | { | |
7417 | long minext, maxext; | |
7418 | int extval; | |
7419 | ||
7420 | if (op->extu) | |
7421 | { | |
7422 | minext = 0; | |
7423 | maxext = (1 << op->extbits) - 1; | |
7424 | } | |
7425 | else | |
7426 | { | |
7427 | minext = - (1 << (op->extbits - 1)); | |
7428 | maxext = (1 << (op->extbits - 1)) - 1; | |
7429 | } | |
7430 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7431 | as_bad_where (file, line, |
7432 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7433 | |
7434 | *use_extend = true; | |
7435 | if (op->extbits == 16) | |
7436 | { | |
7437 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7438 | val &= 0x1f; | |
7439 | } | |
7440 | else if (op->extbits == 15) | |
7441 | { | |
7442 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7443 | val &= 0xf; | |
7444 | } | |
7445 | else | |
7446 | { | |
7447 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7448 | val = 0; | |
7449 | } | |
7450 | ||
7451 | *extend = (unsigned short) extval; | |
7452 | *insn |= val; | |
7453 | } | |
7454 | } | |
7455 | \f | |
3d3c5039 ILT |
7456 | #define LP '(' |
7457 | #define RP ')' | |
7458 | ||
7459 | static int | |
7460 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7461 | expressionS *ep; |
7462 | char *str; | |
3d3c5039 | 7463 | { |
670a50eb ILT |
7464 | char *sp; |
7465 | int c = 0; | |
7466 | ||
7467 | if (*str == ' ') | |
7468 | str++; | |
7469 | if (*str == LP | |
7470 | || (*str == '%' && | |
7471 | ((str[1] == 'h' && str[2] == 'i') | |
7472 | || (str[1] == 'H' && str[2] == 'I') | |
7473 | || (str[1] == 'l' && str[2] == 'o')) | |
7474 | && str[3] == LP)) | |
7475 | { | |
7476 | if (*str == LP) | |
7477 | c = 0; | |
7478 | else | |
7479 | { | |
7480 | c = str[1]; | |
7481 | str += 3; | |
7482 | } | |
7483 | ||
7484 | /* | |
7485 | * A small expression may be followed by a base register. | |
7486 | * Scan to the end of this operand, and then back over a possible | |
7487 | * base register. Then scan the small expression up to that | |
7488 | * point. (Based on code in sparc.c...) | |
7489 | */ | |
7490 | for (sp = str; *sp && *sp != ','; sp++) | |
7491 | ; | |
7492 | if (sp - 4 >= str && sp[-1] == RP) | |
7493 | { | |
7494 | if (isdigit (sp[-2])) | |
7495 | { | |
7496 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7497 | ; | |
7498 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7499 | { | |
7500 | sp--; | |
7501 | goto do_it; | |
3d3c5039 | 7502 | } |
670a50eb ILT |
7503 | } |
7504 | else if (sp - 5 >= str | |
7505 | && sp[-5] == LP | |
7506 | && sp[-4] == '$' | |
7507 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7508 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7509 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7510 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7511 | { | |
7512 | sp -= 5; | |
3d3c5039 | 7513 | do_it: |
670a50eb ILT |
7514 | if (sp == str) |
7515 | { | |
7516 | /* no expression means zero offset */ | |
7517 | if (c) | |
7518 | { | |
7519 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7520 | ep->X_op = O_absent; |
670a50eb | 7521 | expr_end = str - 3; |
3d3c5039 | 7522 | } |
670a50eb ILT |
7523 | else |
7524 | { | |
52aa70b5 | 7525 | ep->X_op = O_constant; |
670a50eb ILT |
7526 | expr_end = sp; |
7527 | } | |
7528 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7529 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7530 | ep->X_add_number = 0; |
7531 | } | |
7532 | else | |
7533 | { | |
7534 | *sp = '\0'; | |
7535 | my_getExpression (ep, str); | |
7536 | *sp = LP; | |
3d3c5039 | 7537 | } |
670a50eb | 7538 | return c; |
3d3c5039 ILT |
7539 | } |
7540 | } | |
7541 | } | |
670a50eb ILT |
7542 | my_getExpression (ep, str); |
7543 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7544 | } |
7545 | ||
7546 | static void | |
7547 | my_getExpression (ep, str) | |
670a50eb ILT |
7548 | expressionS *ep; |
7549 | char *str; | |
3d3c5039 | 7550 | { |
670a50eb | 7551 | char *save_in; |
670a50eb ILT |
7552 | |
7553 | save_in = input_line_pointer; | |
7554 | input_line_pointer = str; | |
5ac34ac3 | 7555 | expression (ep); |
670a50eb ILT |
7556 | expr_end = input_line_pointer; |
7557 | input_line_pointer = save_in; | |
3d3c5039 ILT |
7558 | } |
7559 | ||
becfe05e ILT |
7560 | /* Turn a string in input_line_pointer into a floating point constant |
7561 | of type type, and store the appropriate bytes in *litP. The number | |
7562 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7563 | returned, or NULL on OK. */ | |
7564 | ||
3d3c5039 | 7565 | char * |
670a50eb | 7566 | md_atof (type, litP, sizeP) |
becfe05e | 7567 | int type; |
3d3c5039 ILT |
7568 | char *litP; |
7569 | int *sizeP; | |
7570 | { | |
becfe05e ILT |
7571 | int prec; |
7572 | LITTLENUM_TYPE words[4]; | |
7573 | char *t; | |
7574 | int i; | |
7575 | ||
7576 | switch (type) | |
7577 | { | |
7578 | case 'f': | |
7579 | prec = 2; | |
7580 | break; | |
7581 | ||
7582 | case 'd': | |
7583 | prec = 4; | |
7584 | break; | |
7585 | ||
7586 | default: | |
7587 | *sizeP = 0; | |
7588 | return "bad call to md_atof"; | |
7589 | } | |
7590 | ||
7591 | t = atof_ieee (input_line_pointer, type, words); | |
7592 | if (t) | |
7593 | input_line_pointer = t; | |
7594 | ||
7595 | *sizeP = prec * 2; | |
7596 | ||
b9129c6f | 7597 | if (! target_big_endian) |
becfe05e ILT |
7598 | { |
7599 | for (i = prec - 1; i >= 0; i--) | |
7600 | { | |
7601 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7602 | litP += 2; | |
7603 | } | |
7604 | } | |
7605 | else | |
7606 | { | |
7607 | for (i = 0; i < prec; i++) | |
7608 | { | |
7609 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7610 | litP += 2; | |
7611 | } | |
7612 | } | |
7613 | ||
670a50eb | 7614 | return NULL; |
3d3c5039 ILT |
7615 | } |
7616 | ||
7617 | void | |
7618 | md_number_to_chars (buf, val, n) | |
7619 | char *buf; | |
918692a5 | 7620 | valueT val; |
3d3c5039 ILT |
7621 | int n; |
7622 | { | |
b9129c6f ILT |
7623 | if (target_big_endian) |
7624 | number_to_chars_bigendian (buf, val, n); | |
7625 | else | |
7626 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 7627 | } |
f3d817d8 | 7628 | \f |
e8d4d475 | 7629 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 7630 | |
f3d817d8 DM |
7631 | struct option md_longopts[] = { |
7632 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
7633 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
7634 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
7635 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
7636 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
7637 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
7638 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
7639 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
7640 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
7641 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 7642 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 7643 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 7644 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 7645 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
7646 | {"trap", no_argument, NULL, OPTION_TRAP}, |
7647 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 7648 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
7649 | {"break", no_argument, NULL, OPTION_BREAK}, |
7650 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 7651 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 7652 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 7653 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 7654 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 7655 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 7656 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 7657 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 7658 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
7659 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
7660 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
7661 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
7662 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
7663 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
7664 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
7665 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
7666 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 7667 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 7668 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 7669 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 7670 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f3d817d8 | 7671 | |
d8a1c247 | 7672 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 7673 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 7674 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
7675 | #define OPTION_32 (OPTION_MD_BASE + 20) |
7676 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 7677 | #ifdef OBJ_ELF |
f3d817d8 | 7678 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 7679 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 7680 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 7681 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
7682 | {"32", no_argument, NULL, OPTION_32}, |
7683 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
7684 | #endif |
7685 | ||
7686 | {NULL, no_argument, NULL, 0} | |
7687 | }; | |
7688 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
7689 | |
7690 | int | |
f3d817d8 DM |
7691 | md_parse_option (c, arg) |
7692 | int c; | |
7693 | char *arg; | |
3d3c5039 | 7694 | { |
f3d817d8 | 7695 | switch (c) |
670a50eb | 7696 | { |
f3d817d8 DM |
7697 | case OPTION_TRAP: |
7698 | mips_trap = 1; | |
7699 | break; | |
670a50eb | 7700 | |
f3d817d8 DM |
7701 | case OPTION_BREAK: |
7702 | mips_trap = 0; | |
7703 | break; | |
7704 | ||
e8d4d475 | 7705 | case OPTION_EB: |
1dc1e798 | 7706 | target_big_endian = 1; |
e8d4d475 | 7707 | break; |
04cb3372 | 7708 | |
e8d4d475 | 7709 | case OPTION_EL: |
1dc1e798 | 7710 | target_big_endian = 0; |
f3d817d8 | 7711 | break; |
670a50eb | 7712 | |
f3d817d8 DM |
7713 | case 'O': |
7714 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
7715 | mips_optimize = 1; |
7716 | else | |
7717 | mips_optimize = 2; | |
f3d817d8 | 7718 | break; |
0aa07269 | 7719 | |
f3d817d8 | 7720 | case 'g': |
22ba90ce ILT |
7721 | if (arg == NULL) |
7722 | mips_debug = 2; | |
7723 | else | |
7724 | mips_debug = atoi (arg); | |
7725 | /* When the MIPS assembler sees -g or -g2, it does not do | |
7726 | optimizations which limit full symbolic debugging. We take | |
7727 | that to be equivalent to -O0. */ | |
7728 | if (mips_debug == 2) | |
0aa07269 | 7729 | mips_optimize = 0; |
f3d817d8 | 7730 | break; |
4e95866e | 7731 | |
f3d817d8 DM |
7732 | case OPTION_MIPS1: |
7733 | mips_isa = 1; | |
4bb0cc41 ILT |
7734 | if (mips_cpu == -1) |
7735 | mips_cpu = 3000; | |
f3d817d8 | 7736 | break; |
8358c818 | 7737 | |
f3d817d8 DM |
7738 | case OPTION_MIPS2: |
7739 | mips_isa = 2; | |
4bb0cc41 ILT |
7740 | if (mips_cpu == -1) |
7741 | mips_cpu = 6000; | |
f3d817d8 | 7742 | break; |
8358c818 | 7743 | |
f3d817d8 DM |
7744 | case OPTION_MIPS3: |
7745 | mips_isa = 3; | |
4bb0cc41 ILT |
7746 | if (mips_cpu == -1) |
7747 | mips_cpu = 4000; | |
f3d817d8 | 7748 | break; |
8358c818 | 7749 | |
d8a1c247 KR |
7750 | case OPTION_MIPS4: |
7751 | mips_isa = 4; | |
7752 | if (mips_cpu == -1) | |
7753 | mips_cpu = 8000; | |
7754 | break; | |
7755 | ||
f3d817d8 DM |
7756 | case OPTION_MCPU: |
7757 | { | |
7758 | char *p; | |
7759 | ||
7760 | /* Identify the processor type */ | |
7761 | p = arg; | |
7762 | if (strcmp (p, "default") == 0 | |
7763 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 7764 | mips_cpu = -1; |
f3d817d8 DM |
7765 | else |
7766 | { | |
c625fc23 JSC |
7767 | int sv = 0; |
7768 | ||
7769 | /* We need to cope with the various "vr" prefixes for the 4300 | |
7770 | processor. */ | |
7771 | if (*p == 'v' || *p == 'V') | |
7772 | { | |
7773 | sv = 1; | |
7774 | p++; | |
7775 | } | |
7776 | ||
f3d817d8 DM |
7777 | if (*p == 'r' || *p == 'R') |
7778 | p++; | |
8358c818 | 7779 | |
4bb0cc41 | 7780 | mips_cpu = -1; |
f3d817d8 DM |
7781 | switch (*p) |
7782 | { | |
d8a1c247 KR |
7783 | case '1': |
7784 | if (strcmp (p, "10000") == 0 | |
7785 | || strcmp (p, "10k") == 0 | |
7786 | || strcmp (p, "10K") == 0) | |
7787 | mips_cpu = 10000; | |
7788 | break; | |
7789 | ||
f3d817d8 DM |
7790 | case '2': |
7791 | if (strcmp (p, "2000") == 0 | |
7792 | || strcmp (p, "2k") == 0 | |
7793 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 7794 | mips_cpu = 2000; |
f3d817d8 | 7795 | break; |
8358c818 | 7796 | |
f3d817d8 DM |
7797 | case '3': |
7798 | if (strcmp (p, "3000") == 0 | |
7799 | || strcmp (p, "3k") == 0 | |
7800 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 7801 | mips_cpu = 3000; |
f3d817d8 | 7802 | break; |
8358c818 | 7803 | |
f3d817d8 DM |
7804 | case '4': |
7805 | if (strcmp (p, "4000") == 0 | |
7806 | || strcmp (p, "4k") == 0 | |
8c63448a | 7807 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 7808 | mips_cpu = 4000; |
c625fc23 JSC |
7809 | else if (strcmp (p, "4100") == 0) |
7810 | { | |
7811 | mips_cpu = 4100; | |
7812 | if (mips_4100 < 0) | |
7813 | mips_4100 = 1; | |
7814 | } | |
7815 | else if (strcmp (p, "4300") == 0) | |
7816 | mips_cpu = 4300; | |
8c63448a | 7817 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 7818 | mips_cpu = 4400; |
8c63448a | 7819 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 7820 | mips_cpu = 4600; |
b2b8c24e ILT |
7821 | else if (strcmp (p, "4650") == 0) |
7822 | { | |
7823 | mips_cpu = 4650; | |
7824 | if (mips_4650 < 0) | |
7825 | mips_4650 = 1; | |
7826 | } | |
e532b44c ILT |
7827 | else if (strcmp (p, "4010") == 0) |
7828 | { | |
7829 | mips_cpu = 4010; | |
7830 | if (mips_4010 < 0) | |
7831 | mips_4010 = 1; | |
7832 | } | |
f3d817d8 | 7833 | break; |
8358c818 | 7834 | |
517078c1 ILT |
7835 | case '5': |
7836 | if (strcmp (p, "5000") == 0 | |
7837 | || strcmp (p, "5k") == 0 | |
7838 | || strcmp (p, "5K") == 0) | |
7839 | mips_cpu = 5000; | |
7840 | break; | |
7841 | ||
f3d817d8 DM |
7842 | case '6': |
7843 | if (strcmp (p, "6000") == 0 | |
7844 | || strcmp (p, "6k") == 0 | |
7845 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 7846 | mips_cpu = 6000; |
f3d817d8 | 7847 | break; |
55933a58 | 7848 | |
d8a1c247 KR |
7849 | case '8': |
7850 | if (strcmp (p, "8000") == 0 | |
7851 | || strcmp (p, "8k") == 0 | |
7852 | || strcmp (p, "8K") == 0) | |
7853 | mips_cpu = 8000; | |
7854 | break; | |
7855 | ||
55933a58 ILT |
7856 | case 'o': |
7857 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 7858 | mips_cpu = 4600; |
55933a58 | 7859 | break; |
f3d817d8 | 7860 | } |
8358c818 | 7861 | |
517078c1 | 7862 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
7863 | { |
7864 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
7865 | return 0; | |
7866 | } | |
7867 | ||
4bb0cc41 | 7868 | if (mips_cpu == -1) |
f3d817d8 DM |
7869 | { |
7870 | as_bad ("invalid architecture -mcpu=%s", arg); | |
7871 | return 0; | |
7872 | } | |
7873 | } | |
7874 | } | |
7875 | break; | |
8358c818 | 7876 | |
b2b8c24e ILT |
7877 | case OPTION_M4650: |
7878 | mips_4650 = 1; | |
7879 | break; | |
7880 | ||
7881 | case OPTION_NO_M4650: | |
7882 | mips_4650 = 0; | |
7883 | break; | |
7884 | ||
e532b44c ILT |
7885 | case OPTION_M4010: |
7886 | mips_4010 = 1; | |
7887 | break; | |
7888 | ||
7889 | case OPTION_NO_M4010: | |
7890 | mips_4010 = 0; | |
7891 | break; | |
7892 | ||
c625fc23 JSC |
7893 | case OPTION_M4100: |
7894 | mips_4100 = 1; | |
7895 | break; | |
7896 | ||
7897 | case OPTION_NO_M4100: | |
7898 | mips_4100 = 0; | |
7899 | break; | |
7900 | ||
cc5703cd ILT |
7901 | case OPTION_MIPS16: |
7902 | mips16 = 1; | |
7903 | mips_no_prev_insn (); | |
7904 | break; | |
7905 | ||
7906 | case OPTION_NO_MIPS16: | |
7907 | mips16 = 0; | |
7908 | mips_no_prev_insn (); | |
7909 | break; | |
7910 | ||
f3d817d8 | 7911 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 7912 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 7913 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
7914 | { |
7915 | as_bad ("-G may not be used with embedded PIC code"); | |
7916 | return 0; | |
7917 | } | |
5b63f465 | 7918 | g_switch_value = 0x7fffffff; |
f3d817d8 | 7919 | break; |
d9aba805 | 7920 | |
fb251650 ILT |
7921 | /* When generating ELF code, we permit -KPIC and -call_shared to |
7922 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
7923 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 7924 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
7925 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
7926 | { | |
7927 | as_bad ("-call_shared is supported only for ELF format"); | |
7928 | return 0; | |
7929 | } | |
d9aba805 ILT |
7930 | mips_pic = SVR4_PIC; |
7931 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
7932 | { |
7933 | as_bad ("-G may not be used with SVR4 PIC code"); | |
7934 | return 0; | |
7935 | } | |
d9aba805 | 7936 | g_switch_value = 0; |
f3d817d8 DM |
7937 | break; |
7938 | ||
7939 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
7940 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
7941 | { | |
7942 | as_bad ("-non_shared is supported only for ELF format"); | |
7943 | return 0; | |
7944 | } | |
d9aba805 | 7945 | mips_pic = NO_PIC; |
f3d817d8 | 7946 | break; |
8358c818 | 7947 | |
fb251650 ILT |
7948 | /* The -xgot option tells the assembler to use 32 offsets when |
7949 | accessing the got in SVR4_PIC mode. It is for Irix | |
7950 | compatibility. */ | |
7951 | case OPTION_XGOT: | |
7952 | mips_big_got = 1; | |
7953 | break; | |
7954 | ||
f3d817d8 | 7955 | case 'G': |
1dc1e798 KR |
7956 | if (! USE_GLOBAL_POINTER_OPT) |
7957 | { | |
7958 | as_bad ("-G is not supported for this configuration"); | |
7959 | return 0; | |
7960 | } | |
7961 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 7962 | { |
f3d817d8 DM |
7963 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
7964 | return 0; | |
670a50eb ILT |
7965 | } |
7966 | else | |
f3d817d8 | 7967 | g_switch_value = atoi (arg); |
42562568 | 7968 | g_switch_seen = 1; |
f3d817d8 | 7969 | break; |
4e95866e | 7970 | |
7f9880e5 ILT |
7971 | /* The -32 and -64 options tell the assembler to output the 32 |
7972 | bit or the 64 bit MIPS ELF format. */ | |
7973 | case OPTION_32: | |
7974 | mips_64 = 0; | |
7975 | break; | |
7976 | ||
7977 | case OPTION_64: | |
9c44af60 ILT |
7978 | { |
7979 | const char **list, **l; | |
7980 | ||
7981 | list = bfd_target_list (); | |
7982 | for (l = list; *l != NULL; l++) | |
7983 | if (strcmp (*l, "elf64-bigmips") == 0 | |
7984 | || strcmp (*l, "elf64-littlemips") == 0) | |
7985 | break; | |
7986 | if (*l == NULL) | |
7987 | as_fatal ("No compiled in support for 64 bit object file format"); | |
7988 | free (list); | |
7989 | mips_64 = 1; | |
7990 | } | |
7f9880e5 ILT |
7991 | break; |
7992 | ||
f3d817d8 DM |
7993 | default: |
7994 | return 0; | |
8ea7f4e8 ILT |
7995 | } |
7996 | ||
f3d817d8 | 7997 | return 1; |
8ea7f4e8 ILT |
7998 | } |
7999 | ||
f3d817d8 DM |
8000 | void |
8001 | md_show_usage (stream) | |
8002 | FILE *stream; | |
8003 | { | |
8004 | fprintf(stream, "\ | |
8005 | MIPS options:\n\ | |
8006 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8007 | -EB generate big endian output\n\ |
8008 | -EL generate little endian output\n\ | |
8009 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8010 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8011 | implicitly with the gp register [default 8]\n"); |
8012 | fprintf(stream, "\ | |
f3d817d8 DM |
8013 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8014 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8015 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8016 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8017 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8018 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8019 | -m4650 permit R4650 instructions\n\ |
8020 | -no-m4650 do not permit R4650 instructions\n\ | |
8021 | -m4010 permit R4010 instructions\n\ | |
8022 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8023 | -m4100 permit VR4100 instructions\n\ |
8024 | -no-m4100 do not permit VR4100 instructions\n"); | |
8025 | fprintf(stream, "\ | |
cc5703cd ILT |
8026 | -mips16 generate mips16 instructions\n\ |
8027 | -no-mips16 do not generate mips16 instructions\n"); | |
8028 | fprintf(stream, "\ | |
f3d817d8 DM |
8029 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8030 | -O remove unneeded NOPs and swap branches\n\ | |
8031 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8032 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8033 | #ifdef OBJ_ELF | |
8034 | fprintf(stream, "\ | |
8035 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8036 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8037 | -xgot assume a 32 bit GOT\n\ |
8038 | -32 create 32 bit object file (default)\n\ | |
8039 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8040 | #endif |
8041 | } | |
8042 | \f | |
3d3c5039 ILT |
8043 | long |
8044 | md_pcrel_from (fixP) | |
8045 | fixS *fixP; | |
8046 | { | |
1dc1e798 KR |
8047 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8048 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8049 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8050 | { | |
8051 | /* This makes a branch to an undefined symbol be a branch to the | |
8052 | current location. */ | |
8053 | return 4; | |
8054 | } | |
5b63f465 | 8055 | |
670a50eb ILT |
8056 | /* return the address of the delay slot */ |
8057 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8058 | } |
8059 | ||
abdad6bc ILT |
8060 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8061 | reloc for a cons. We could use the definition there, except that | |
8062 | we want to handle 64 bit relocs specially. */ | |
8063 | ||
8064 | void | |
8065 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8066 | fragS *frag; | |
8067 | int where; | |
8068 | unsigned int nbytes; | |
8069 | expressionS *exp; | |
8070 | { | |
bf39474f | 8071 | #ifndef OBJ_ELF |
abdad6bc | 8072 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8073 | 4 byte reloc. */ |
8074 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8075 | { |
b9129c6f | 8076 | if (target_big_endian) |
abdad6bc ILT |
8077 | where += 4; |
8078 | nbytes = 4; | |
8079 | } | |
bf39474f | 8080 | #endif |
abdad6bc | 8081 | |
7f9880e5 | 8082 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8083 | as_bad ("Unsupported reloc size %d", nbytes); |
8084 | ||
8085 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8086 | (nbytes == 2 |
8087 | ? BFD_RELOC_16 | |
8088 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8089 | } |
8090 | ||
867a58b3 ILT |
8091 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8092 | the corresponding LO reloc. This is called before md_apply_fix and | |
8093 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8094 | explicit use of the %hi modifier. */ | |
8095 | ||
8096 | void | |
8097 | mips_frob_file () | |
8098 | { | |
8099 | struct mips_hi_fixup *l; | |
8100 | ||
8101 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8102 | { | |
8103 | segment_info_type *seginfo; | |
9b61d62b | 8104 | int pass; |
867a58b3 ILT |
8105 | |
8106 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8107 | ||
8108 | /* Check quickly whether the next fixup happens to be a matching | |
8109 | %lo. */ | |
8110 | if (l->fixp->fx_next != NULL | |
8111 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8112 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8113 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8114 | continue; | |
8115 | ||
8116 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8117 | When we find one, move the %hi just in front of it. We do |
8118 | this in two passes. In the first pass, we try to find a | |
8119 | unique %lo. In the second pass, we permit multiple %hi | |
8120 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8121 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8122 | for (pass = 0; pass < 2; pass++) |
8123 | { | |
8124 | fixS *f, *prev; | |
8125 | ||
8126 | prev = NULL; | |
8127 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8128 | { |
9b61d62b ILT |
8129 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8130 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8131 | && f->fx_addsy == l->fixp->fx_addsy | |
8132 | && f->fx_offset == l->fixp->fx_offset | |
8133 | && (pass == 1 | |
8134 | || prev == NULL | |
8135 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8136 | || prev->fx_addsy != f->fx_addsy | |
8137 | || prev->fx_offset != f->fx_offset)) | |
8138 | { | |
8139 | fixS **pf; | |
867a58b3 | 8140 | |
9b61d62b ILT |
8141 | /* Move l->fixp before f. */ |
8142 | for (pf = &seginfo->fix_root; | |
8143 | *pf != l->fixp; | |
8144 | pf = &(*pf)->fx_next) | |
8145 | assert (*pf != NULL); | |
867a58b3 | 8146 | |
9b61d62b | 8147 | *pf = l->fixp->fx_next; |
867a58b3 | 8148 | |
9b61d62b ILT |
8149 | l->fixp->fx_next = f; |
8150 | if (prev == NULL) | |
8151 | seginfo->fix_root = l->fixp; | |
8152 | else | |
8153 | prev->fx_next = l->fixp; | |
867a58b3 | 8154 | |
9b61d62b ILT |
8155 | break; |
8156 | } | |
8157 | ||
8158 | prev = f; | |
867a58b3 ILT |
8159 | } |
8160 | ||
9b61d62b ILT |
8161 | if (f != NULL) |
8162 | break; | |
867a58b3 | 8163 | |
9b61d62b ILT |
8164 | if (pass == 1) |
8165 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8166 | "Unmatched %%hi reloc"); | |
8167 | } | |
867a58b3 ILT |
8168 | } |
8169 | } | |
8170 | ||
1c803e52 ILT |
8171 | /* When generating embedded PIC code we need to use a special |
8172 | relocation to represent the difference of two symbols in the .text | |
8173 | section (switch tables use a difference of this sort). See | |
8174 | include/coff/mips.h for details. This macro checks whether this | |
8175 | fixup requires the special reloc. */ | |
8176 | #define SWITCH_TABLE(fixp) \ | |
8177 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8178 | && (fixp)->fx_addsy != NULL \ | |
8179 | && (fixp)->fx_subsy != NULL \ | |
8180 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8181 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8182 | ||
5b63f465 | 8183 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8184 | relocations, in case the linker has to relax a call. We also need |
8185 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8186 | |
8187 | /*ARGSUSED*/ | |
8188 | int | |
8189 | mips_force_relocation (fixp) | |
8190 | fixS *fixp; | |
8191 | { | |
1c803e52 | 8192 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8193 | && (fixp->fx_pcrel |
8194 | || SWITCH_TABLE (fixp) | |
8195 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8196 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8197 | } |
8198 | ||
8199 | /* Apply a fixup to the object file. */ | |
8200 | ||
3d3c5039 ILT |
8201 | int |
8202 | md_apply_fix (fixP, valueP) | |
8203 | fixS *fixP; | |
918692a5 | 8204 | valueT *valueP; |
3d3c5039 | 8205 | { |
670a50eb ILT |
8206 | unsigned char *buf; |
8207 | long insn, value; | |
3d3c5039 | 8208 | |
bf39474f ILT |
8209 | assert (fixP->fx_size == 4 |
8210 | || fixP->fx_r_type == BFD_RELOC_16 | |
8211 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8212 | |
670a50eb ILT |
8213 | value = *valueP; |
8214 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 8215 | |
5b63f465 ILT |
8216 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8217 | fixP->fx_done = 1; | |
8218 | ||
670a50eb ILT |
8219 | switch (fixP->fx_r_type) |
8220 | { | |
3d3c5039 ILT |
8221 | case BFD_RELOC_MIPS_JMP: |
8222 | case BFD_RELOC_HI16: | |
8223 | case BFD_RELOC_HI16_S: | |
670a50eb | 8224 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8225 | case BFD_RELOC_MIPS_LITERAL: |
8226 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8227 | case BFD_RELOC_MIPS_GOT16: |
8228 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8229 | case BFD_RELOC_MIPS_GOT_HI16: |
8230 | case BFD_RELOC_MIPS_GOT_LO16: | |
8231 | case BFD_RELOC_MIPS_CALL_HI16: | |
8232 | case BFD_RELOC_MIPS_CALL_LO16: | |
ecd4ca1c | 8233 | if (fixP->fx_pcrel) |
7b777690 ILT |
8234 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8235 | "Invalid PC relative reloc"); | |
670a50eb | 8236 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8237 | break; |
3d3c5039 | 8238 | |
cc5703cd ILT |
8239 | case BFD_RELOC_MIPS16_JMP: |
8240 | /* We currently always generate a reloc against a symbol, which | |
8241 | means that we don't want an addend even if the symbol is | |
8242 | defined. */ | |
8243 | fixP->fx_addnumber = 0; | |
8244 | break; | |
8245 | ||
ecd4ca1c ILT |
8246 | case BFD_RELOC_PCREL_HI16_S: |
8247 | /* The addend for this is tricky if it is internal, so we just | |
8248 | do everything here rather than in bfd_perform_relocation. */ | |
8249 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8250 | { | |
8251 | /* For an external symbol adjust by the address to make it | |
8252 | pcrel_offset. We use the address of the RELLO reloc | |
8253 | which follows this one. */ | |
8254 | value += (fixP->fx_next->fx_frag->fr_address | |
8255 | + fixP->fx_next->fx_where); | |
8256 | } | |
8257 | if (value & 0x8000) | |
8258 | value += 0x10000; | |
8259 | value >>= 16; | |
0221ddf7 | 8260 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8261 | if (target_big_endian) |
ecd4ca1c ILT |
8262 | buf += 2; |
8263 | md_number_to_chars (buf, value, 2); | |
8264 | break; | |
8265 | ||
8266 | case BFD_RELOC_PCREL_LO16: | |
8267 | /* The addend for this is tricky if it is internal, so we just | |
8268 | do everything here rather than in bfd_perform_relocation. */ | |
8269 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8270 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8271 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8272 | if (target_big_endian) |
ecd4ca1c ILT |
8273 | buf += 2; |
8274 | md_number_to_chars (buf, value, 2); | |
8275 | break; | |
8276 | ||
bf39474f ILT |
8277 | case BFD_RELOC_64: |
8278 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8279 | extended value if we are only 32 bits. */ | |
8280 | if (fixP->fx_done | |
8281 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8282 | { | |
8283 | if (8 <= sizeof (valueT)) | |
8284 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8285 | value, 8); | |
8286 | else | |
8287 | { | |
8288 | long w1, w2; | |
8289 | long hiv; | |
8290 | ||
8291 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 8292 | if (target_big_endian) |
bf39474f ILT |
8293 | w1 += 4; |
8294 | else | |
8295 | w2 += 4; | |
8296 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8297 | if ((value & 0x80000000) != 0) | |
8298 | hiv = 0xffffffff; | |
8299 | else | |
8300 | hiv = 0; | |
8301 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8302 | } | |
8303 | } | |
8304 | break; | |
8305 | ||
f3645945 ILT |
8306 | case BFD_RELOC_32: |
8307 | /* If we are deleting this reloc entry, we must fill in the | |
8308 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8309 | resolved when it appears but is later defined. We also need |
8310 | to fill in the value if this is an embedded PIC switch table | |
8311 | entry. */ | |
8312 | if (fixP->fx_done | |
8313 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8314 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8315 | value, 4); | |
8316 | break; | |
8317 | ||
49ad0c4c ILT |
8318 | case BFD_RELOC_16: |
8319 | /* If we are deleting this reloc entry, we must fill in the | |
8320 | value now. */ | |
8321 | assert (fixP->fx_size == 2); | |
8322 | if (fixP->fx_done) | |
8323 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8324 | value, 2); | |
8325 | break; | |
8326 | ||
f3645945 ILT |
8327 | case BFD_RELOC_LO16: |
8328 | /* When handling an embedded PIC switch statement, we can wind | |
8329 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8330 | if (fixP->fx_done) | |
8331 | { | |
8332 | if (value < -0x8000 || value > 0x7fff) | |
8333 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8334 | "relocation overflow"); | |
0221ddf7 | 8335 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8336 | if (target_big_endian) |
f3645945 ILT |
8337 | buf += 2; |
8338 | md_number_to_chars (buf, value, 2); | |
8339 | } | |
8340 | break; | |
8341 | ||
3d3c5039 | 8342 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8343 | /* |
8344 | * We need to save the bits in the instruction since fixup_segment() | |
8345 | * might be deleting the relocation entry (i.e., a branch within | |
8346 | * the current segment). | |
8347 | */ | |
fbcfacb7 | 8348 | if ((value & 0x3) != 0) |
3b320c48 ILT |
8349 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8350 | "Branch to odd address (%lx)", value); | |
670a50eb | 8351 | value >>= 2; |
670a50eb ILT |
8352 | |
8353 | /* update old instruction data */ | |
8354 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
8355 | if (target_big_endian) |
8356 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
8357 | else | |
8358 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
8359 | |
8360 | if (value >= -0x8000 && value < 0x8000) | |
8361 | insn |= value & 0xffff; | |
8362 | else | |
8363 | { | |
8364 | /* The branch offset is too large. If this is an | |
8365 | unconditional branch, and we are not generating PIC code, | |
8366 | we can convert it to an absolute jump instruction. */ | |
8367 | if (mips_pic == NO_PIC | |
8368 | && fixP->fx_done | |
8369 | && fixP->fx_frag->fr_address >= text_section->vma | |
8370 | && (fixP->fx_frag->fr_address | |
8371 | < text_section->vma + text_section->_raw_size) | |
8372 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8373 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8374 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8375 | { | |
8376 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8377 | insn = 0x0c000000; /* jal */ | |
8378 | else | |
8379 | insn = 0x08000000; /* j */ | |
8380 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8381 | fixP->fx_done = 0; | |
8382 | fixP->fx_addsy = section_symbol (text_section); | |
8383 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8384 | } | |
8385 | else | |
8386 | { | |
8387 | /* FIXME. It would be possible in principle to handle | |
8388 | conditional branches which overflow. They could be | |
8389 | transformed into a branch around a jump. This would | |
8390 | require setting up variant frags for each different | |
8391 | branch type. The native MIPS assembler attempts to | |
8392 | handle these cases, but it appears to do it | |
8393 | incorrectly. */ | |
8394 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8395 | "Relocation overflow"); | |
8396 | } | |
8397 | } | |
8398 | ||
604633ae | 8399 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8400 | break; |
3d3c5039 ILT |
8401 | |
8402 | default: | |
670a50eb | 8403 | internalError (); |
3d3c5039 | 8404 | } |
5b63f465 | 8405 | |
670a50eb | 8406 | return 1; |
3d3c5039 ILT |
8407 | } |
8408 | ||
8409 | #if 0 | |
8410 | void | |
670a50eb ILT |
8411 | printInsn (oc) |
8412 | unsigned long oc; | |
3d3c5039 | 8413 | { |
670a50eb ILT |
8414 | const struct mips_opcode *p; |
8415 | int treg, sreg, dreg, shamt; | |
8416 | short imm; | |
8417 | const char *args; | |
8418 | int i; | |
3d3c5039 | 8419 | |
670a50eb ILT |
8420 | for (i = 0; i < NUMOPCODES; ++i) |
8421 | { | |
8422 | p = &mips_opcodes[i]; | |
8423 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8424 | { | |
8425 | printf ("%08lx %s\t", oc, p->name); | |
8426 | treg = (oc >> 16) & 0x1f; | |
8427 | sreg = (oc >> 21) & 0x1f; | |
8428 | dreg = (oc >> 11) & 0x1f; | |
8429 | shamt = (oc >> 6) & 0x1f; | |
8430 | imm = oc; | |
8431 | for (args = p->args;; ++args) | |
8432 | { | |
8433 | switch (*args) | |
8434 | { | |
3d3c5039 | 8435 | case '\0': |
670a50eb ILT |
8436 | printf ("\n"); |
8437 | break; | |
3d3c5039 ILT |
8438 | |
8439 | case ',': | |
8440 | case '(': | |
8441 | case ')': | |
670a50eb ILT |
8442 | printf ("%c", *args); |
8443 | continue; | |
3d3c5039 ILT |
8444 | |
8445 | case 'r': | |
670a50eb ILT |
8446 | assert (treg == sreg); |
8447 | printf ("$%d,$%d", treg, sreg); | |
8448 | continue; | |
3d3c5039 ILT |
8449 | |
8450 | case 'd': | |
918692a5 | 8451 | case 'G': |
670a50eb ILT |
8452 | printf ("$%d", dreg); |
8453 | continue; | |
3d3c5039 ILT |
8454 | |
8455 | case 't': | |
918692a5 | 8456 | case 'E': |
670a50eb ILT |
8457 | printf ("$%d", treg); |
8458 | continue; | |
3d3c5039 | 8459 | |
9226253a ILT |
8460 | case 'k': |
8461 | printf ("0x%x", treg); | |
8462 | continue; | |
8463 | ||
3d3c5039 ILT |
8464 | case 'b': |
8465 | case 's': | |
670a50eb ILT |
8466 | printf ("$%d", sreg); |
8467 | continue; | |
3d3c5039 ILT |
8468 | |
8469 | case 'a': | |
670a50eb ILT |
8470 | printf ("0x%08lx", oc & 0x1ffffff); |
8471 | continue; | |
3d3c5039 ILT |
8472 | |
8473 | case 'i': | |
8474 | case 'j': | |
8475 | case 'o': | |
8476 | case 'u': | |
670a50eb ILT |
8477 | printf ("%d", imm); |
8478 | continue; | |
3d3c5039 ILT |
8479 | |
8480 | case '<': | |
56c96faa | 8481 | case '>': |
670a50eb ILT |
8482 | printf ("$%d", shamt); |
8483 | continue; | |
3d3c5039 ILT |
8484 | |
8485 | default: | |
670a50eb | 8486 | internalError (); |
3d3c5039 | 8487 | } |
670a50eb | 8488 | break; |
3d3c5039 | 8489 | } |
670a50eb | 8490 | return; |
3d3c5039 ILT |
8491 | } |
8492 | } | |
670a50eb | 8493 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8494 | } |
8495 | #endif | |
8496 | ||
8497 | static symbolS * | |
8498 | get_symbol () | |
8499 | { | |
670a50eb ILT |
8500 | int c; |
8501 | char *name; | |
8502 | symbolS *p; | |
8503 | ||
8504 | name = input_line_pointer; | |
8505 | c = get_symbol_end (); | |
8506 | p = (symbolS *) symbol_find_or_make (name); | |
8507 | *input_line_pointer = c; | |
8508 | return p; | |
3d3c5039 ILT |
8509 | } |
8510 | ||
becfe05e ILT |
8511 | /* Align the current frag to a given power of two. The MIPS assembler |
8512 | also automatically adjusts any preceding label. */ | |
8513 | ||
8514 | static void | |
23dc1ae3 | 8515 | mips_align (to, fill, label) |
becfe05e ILT |
8516 | int to; |
8517 | int fill; | |
23dc1ae3 | 8518 | symbolS *label; |
becfe05e | 8519 | { |
fbcfacb7 | 8520 | mips_emit_delays (false); |
becfe05e ILT |
8521 | frag_align (to, fill); |
8522 | record_alignment (now_seg, to); | |
23dc1ae3 | 8523 | if (label != NULL) |
becfe05e | 8524 | { |
23dc1ae3 ILT |
8525 | assert (S_GET_SEGMENT (label) == now_seg); |
8526 | label->sy_frag = frag_now; | |
8527 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8528 | } |
8529 | } | |
8530 | ||
8531 | /* Align to a given power of two. .align 0 turns off the automatic | |
8532 | alignment used by the data creating pseudo-ops. */ | |
8533 | ||
3d3c5039 ILT |
8534 | static void |
8535 | s_align (x) | |
8536 | int x; | |
8537 | { | |
670a50eb ILT |
8538 | register int temp; |
8539 | register long temp_fill; | |
8540 | long max_alignment = 15; | |
3d3c5039 | 8541 | |
670a50eb | 8542 | /* |
3d3c5039 ILT |
8543 | |
8544 | o Note that the assembler pulls down any immediately preceeding label | |
8545 | to the aligned address. | |
8546 | o It's not documented but auto alignment is reinstated by | |
8547 | a .align pseudo instruction. | |
8548 | o Note also that after auto alignment is turned off the mips assembler | |
8549 | issues an error on attempt to assemble an improperly aligned data item. | |
8550 | We don't. | |
8551 | ||
8552 | */ | |
8553 | ||
670a50eb ILT |
8554 | temp = get_absolute_expression (); |
8555 | if (temp > max_alignment) | |
8556 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
8557 | else if (temp < 0) | |
8558 | { | |
8559 | as_warn ("Alignment negative: 0 assumed."); | |
8560 | temp = 0; | |
8561 | } | |
8562 | if (*input_line_pointer == ',') | |
8563 | { | |
8564 | input_line_pointer++; | |
8565 | temp_fill = get_absolute_expression (); | |
8566 | } | |
8567 | else | |
8568 | temp_fill = 0; | |
8569 | if (temp) | |
8570 | { | |
8571 | auto_align = 1; | |
fbcfacb7 ILT |
8572 | mips_align (temp, (int) temp_fill, |
8573 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 8574 | } |
670a50eb ILT |
8575 | else |
8576 | { | |
8577 | auto_align = 0; | |
3d3c5039 ILT |
8578 | } |
8579 | ||
670a50eb | 8580 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8581 | } |
8582 | ||
739708fa KR |
8583 | void |
8584 | mips_flush_pending_output () | |
becfe05e | 8585 | { |
fbcfacb7 ILT |
8586 | mips_emit_delays (false); |
8587 | mips_clear_insn_labels (); | |
becfe05e ILT |
8588 | } |
8589 | ||
3d3c5039 ILT |
8590 | static void |
8591 | s_change_sec (sec) | |
8592 | int sec; | |
8593 | { | |
88225433 | 8594 | segT seg; |
becfe05e | 8595 | |
5b63f465 ILT |
8596 | /* When generating embedded PIC code, we only use the .text, .lit8, |
8597 | .sdata and .sbss sections. We change the .data and .rdata | |
8598 | pseudo-ops to use .sdata. */ | |
8599 | if (mips_pic == EMBEDDED_PIC | |
8600 | && (sec == 'd' || sec == 'r')) | |
8601 | sec = 's'; | |
8602 | ||
fbcfacb7 | 8603 | mips_emit_delays (false); |
670a50eb ILT |
8604 | switch (sec) |
8605 | { | |
3d3c5039 | 8606 | case 't': |
604633ae | 8607 | s_text (0); |
670a50eb | 8608 | break; |
3d3c5039 | 8609 | case 'd': |
604633ae | 8610 | s_data (0); |
670a50eb | 8611 | break; |
3d3c5039 | 8612 | case 'b': |
670a50eb | 8613 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
8614 | demand_empty_rest_of_line (); |
8615 | break; | |
88225433 ILT |
8616 | |
8617 | case 'r': | |
1dc1e798 KR |
8618 | if (USE_GLOBAL_POINTER_OPT) |
8619 | { | |
8620 | seg = subseg_new (RDATA_SECTION_NAME, | |
8621 | (subsegT) get_absolute_expression ()); | |
8622 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8623 | { | |
8624 | bfd_set_section_flags (stdoutput, seg, | |
8625 | (SEC_ALLOC | |
8626 | | SEC_LOAD | |
8627 | | SEC_READONLY | |
8628 | | SEC_RELOC | |
8629 | | SEC_DATA)); | |
08e17202 ILT |
8630 | if (strcmp (TARGET_OS, "elf") != 0) |
8631 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8632 | } |
8633 | demand_empty_rest_of_line (); | |
8634 | } | |
8635 | else | |
8636 | { | |
8637 | as_bad ("No read only data section in this object file format"); | |
8638 | demand_empty_rest_of_line (); | |
8639 | return; | |
8640 | } | |
88225433 | 8641 | break; |
88225433 ILT |
8642 | |
8643 | case 's': | |
1dc1e798 KR |
8644 | if (USE_GLOBAL_POINTER_OPT) |
8645 | { | |
8646 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
8647 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8648 | { | |
8649 | bfd_set_section_flags (stdoutput, seg, | |
8650 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
8651 | | SEC_DATA); | |
08e17202 ILT |
8652 | if (strcmp (TARGET_OS, "elf") != 0) |
8653 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8654 | } |
8655 | demand_empty_rest_of_line (); | |
8656 | break; | |
8657 | } | |
8658 | else | |
8659 | { | |
8660 | as_bad ("Global pointers not supported; recompile -G 0"); | |
8661 | demand_empty_rest_of_line (); | |
8662 | return; | |
8663 | } | |
3d3c5039 | 8664 | } |
88225433 | 8665 | |
670a50eb | 8666 | auto_align = 1; |
3d3c5039 ILT |
8667 | } |
8668 | ||
739708fa KR |
8669 | void |
8670 | mips_enable_auto_align () | |
9da4c5d1 | 8671 | { |
9da4c5d1 ILT |
8672 | auto_align = 1; |
8673 | } | |
8674 | ||
3d3c5039 ILT |
8675 | static void |
8676 | s_cons (log_size) | |
8677 | int log_size; | |
8678 | { | |
23dc1ae3 ILT |
8679 | symbolS *label; |
8680 | ||
fbcfacb7 ILT |
8681 | label = insn_labels != NULL ? insn_labels->label : NULL; |
8682 | mips_emit_delays (false); | |
670a50eb | 8683 | if (log_size > 0 && auto_align) |
23dc1ae3 | 8684 | mips_align (log_size, 0, label); |
fbcfacb7 | 8685 | mips_clear_insn_labels (); |
670a50eb | 8686 | cons (1 << log_size); |
3d3c5039 ILT |
8687 | } |
8688 | ||
3d3c5039 | 8689 | static void |
becfe05e ILT |
8690 | s_float_cons (type) |
8691 | int type; | |
3d3c5039 | 8692 | { |
23dc1ae3 ILT |
8693 | symbolS *label; |
8694 | ||
fbcfacb7 | 8695 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 8696 | |
fbcfacb7 | 8697 | mips_emit_delays (false); |
670a50eb ILT |
8698 | |
8699 | if (auto_align) | |
becfe05e | 8700 | if (type == 'd') |
23dc1ae3 | 8701 | mips_align (3, 0, label); |
670a50eb | 8702 | else |
23dc1ae3 | 8703 | mips_align (2, 0, label); |
670a50eb | 8704 | |
fbcfacb7 | 8705 | mips_clear_insn_labels (); |
1849d646 | 8706 | |
becfe05e | 8707 | float_cons (type); |
3d3c5039 ILT |
8708 | } |
8709 | ||
c1444ec4 ILT |
8710 | /* Handle .globl. We need to override it because on Irix 5 you are |
8711 | permitted to say | |
8712 | .globl foo .text | |
8713 | where foo is an undefined symbol, to mean that foo should be | |
8714 | considered to be the address of a function. */ | |
8715 | ||
8716 | static void | |
8717 | s_mips_globl (x) | |
8718 | int x; | |
8719 | { | |
8720 | char *name; | |
8721 | int c; | |
8722 | symbolS *symbolP; | |
fb251650 | 8723 | flagword flag; |
c1444ec4 ILT |
8724 | |
8725 | name = input_line_pointer; | |
8726 | c = get_symbol_end (); | |
8727 | symbolP = symbol_find_or_make (name); | |
8728 | *input_line_pointer = c; | |
8729 | SKIP_WHITESPACE (); | |
fb251650 ILT |
8730 | |
8731 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
8732 | being a function is apparently labelled as being an object. */ | |
8733 | flag = BSF_OBJECT; | |
8734 | ||
c1444ec4 ILT |
8735 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
8736 | { | |
8737 | char *secname; | |
8738 | asection *sec; | |
8739 | ||
8740 | secname = input_line_pointer; | |
8741 | c = get_symbol_end (); | |
8742 | sec = bfd_get_section_by_name (stdoutput, secname); | |
8743 | if (sec == NULL) | |
8744 | as_bad ("%s: no such section", secname); | |
8745 | *input_line_pointer = c; | |
8746 | ||
8747 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 8748 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
8749 | } |
8750 | ||
fb251650 ILT |
8751 | symbolP->bsym->flags |= flag; |
8752 | ||
c1444ec4 ILT |
8753 | S_SET_EXTERNAL (symbolP); |
8754 | demand_empty_rest_of_line (); | |
8755 | } | |
8756 | ||
3d3c5039 ILT |
8757 | static void |
8758 | s_option (x) | |
8759 | int x; | |
8760 | { | |
dd3f1f76 ILT |
8761 | char *opt; |
8762 | char c; | |
8763 | ||
8764 | opt = input_line_pointer; | |
8765 | c = get_symbol_end (); | |
8766 | ||
dd3f1f76 | 8767 | if (*opt == 'O') |
9226253a ILT |
8768 | { |
8769 | /* FIXME: What does this mean? */ | |
8770 | } | |
dd3f1f76 | 8771 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 8772 | { |
d9aba805 | 8773 | int i; |
42562568 | 8774 | |
d9aba805 ILT |
8775 | i = atoi (opt + 3); |
8776 | if (i == 0) | |
8777 | mips_pic = NO_PIC; | |
8778 | else if (i == 2) | |
8779 | mips_pic = SVR4_PIC; | |
8780 | else | |
8781 | as_bad (".option pic%d not supported", i); | |
8782 | ||
1dc1e798 | 8783 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
8784 | { |
8785 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 8786 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
8787 | g_switch_value = 0; |
8788 | bfd_set_gp_size (stdoutput, 0); | |
8789 | } | |
9226253a | 8790 | } |
dd3f1f76 ILT |
8791 | else |
8792 | as_warn ("Unrecognized option \"%s\"", opt); | |
8793 | ||
8794 | *input_line_pointer = c; | |
670a50eb | 8795 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8796 | } |
8797 | ||
8798 | static void | |
8799 | s_mipsset (x) | |
8800 | int x; | |
8801 | { | |
670a50eb ILT |
8802 | char *name = input_line_pointer, ch; |
8803 | ||
8804 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
8805 | input_line_pointer++; | |
8806 | ch = *input_line_pointer; | |
8807 | *input_line_pointer = '\0'; | |
8808 | ||
8809 | if (strcmp (name, "reorder") == 0) | |
8810 | { | |
4e95866e ILT |
8811 | if (mips_noreorder) |
8812 | { | |
8813 | prev_insn_unreordered = 1; | |
8814 | prev_prev_insn_unreordered = 1; | |
8815 | } | |
670a50eb ILT |
8816 | mips_noreorder = 0; |
8817 | } | |
8818 | else if (strcmp (name, "noreorder") == 0) | |
8819 | { | |
fbcfacb7 | 8820 | mips_emit_delays (true); |
670a50eb | 8821 | mips_noreorder = 1; |
0dd2d296 | 8822 | mips_any_noreorder = 1; |
670a50eb ILT |
8823 | } |
8824 | else if (strcmp (name, "at") == 0) | |
8825 | { | |
8826 | mips_noat = 0; | |
8827 | } | |
8828 | else if (strcmp (name, "noat") == 0) | |
8829 | { | |
8830 | mips_noat = 1; | |
3d3c5039 | 8831 | } |
670a50eb ILT |
8832 | else if (strcmp (name, "macro") == 0) |
8833 | { | |
8834 | mips_warn_about_macros = 0; | |
8835 | } | |
8836 | else if (strcmp (name, "nomacro") == 0) | |
8837 | { | |
8838 | if (mips_noreorder == 0) | |
8839 | as_bad ("`noreorder' must be set before `nomacro'"); | |
8840 | mips_warn_about_macros = 1; | |
8841 | } | |
8842 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
8843 | { | |
8844 | mips_nomove = 0; | |
8845 | } | |
8846 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
8847 | { | |
8848 | mips_nomove = 1; | |
8849 | } | |
8850 | else if (strcmp (name, "bopt") == 0) | |
8851 | { | |
8852 | mips_nobopt = 0; | |
8853 | } | |
8854 | else if (strcmp (name, "nobopt") == 0) | |
8855 | { | |
8856 | mips_nobopt = 1; | |
8857 | } | |
943321c0 ILT |
8858 | else if (strcmp (name, "mips16") == 0 |
8859 | || strcmp (name, "MIPS-16") == 0) | |
8860 | mips16 = 1; | |
8861 | else if (strcmp (name, "nomips16") == 0 | |
8862 | || strcmp (name, "noMIPS-16") == 0) | |
8863 | mips16 = 0; | |
1051c97f ILT |
8864 | else if (strncmp (name, "mips", 4) == 0) |
8865 | { | |
8866 | int isa; | |
8867 | ||
8868 | /* Permit the user to change the ISA on the fly. Needless to | |
8869 | say, misuse can cause serious problems. */ | |
8870 | isa = atoi (name + 4); | |
8871 | if (isa == 0) | |
8872 | mips_isa = file_mips_isa; | |
d8a1c247 | 8873 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
8874 | as_bad ("unknown ISA level"); |
8875 | else | |
8876 | mips_isa = isa; | |
8877 | } | |
cc5703cd ILT |
8878 | else if (strcmp (name, "autoextend") == 0) |
8879 | mips16_autoextend = 1; | |
8880 | else if (strcmp (name, "noautoextend") == 0) | |
8881 | mips16_autoextend = 0; | |
670a50eb ILT |
8882 | else |
8883 | { | |
8884 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
8885 | } | |
8886 | *input_line_pointer = ch; | |
8887 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
8888 | } |
8889 | ||
9226253a ILT |
8890 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
8891 | .option pic2. It means to generate SVR4 PIC calls. */ | |
8892 | ||
8893 | static void | |
8894 | s_abicalls (ignore) | |
8895 | int ignore; | |
8896 | { | |
d9aba805 | 8897 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
8898 | if (USE_GLOBAL_POINTER_OPT) |
8899 | { | |
8900 | if (g_switch_seen && g_switch_value != 0) | |
8901 | as_warn ("-G may not be used with SVR4 PIC code"); | |
8902 | g_switch_value = 0; | |
8903 | } | |
d9aba805 | 8904 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
8905 | demand_empty_rest_of_line (); |
8906 | } | |
8907 | ||
8908 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
8909 | PIC code. It sets the $gp register for the function based on the | |
8910 | function address, which is in the register named in the argument. | |
8911 | This uses a relocation against _gp_disp, which is handled specially | |
8912 | by the linker. The result is: | |
8913 | lui $gp,%hi(_gp_disp) | |
8914 | addiu $gp,$gp,%lo(_gp_disp) | |
8915 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 8916 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
8917 | |
8918 | static void | |
8919 | s_cpload (ignore) | |
8920 | int ignore; | |
8921 | { | |
8922 | expressionS ex; | |
8923 | int icnt = 0; | |
8924 | ||
d9aba805 ILT |
8925 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
8926 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
8927 | { |
8928 | s_ignore (0); | |
8929 | return; | |
8930 | } | |
8931 | ||
8932 | /* .cpload should be a in .set noreorder section. */ | |
8933 | if (mips_noreorder == 0) | |
8934 | as_warn (".cpload not in noreorder section"); | |
8935 | ||
9226253a ILT |
8936 | ex.X_op = O_symbol; |
8937 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
8938 | ex.X_op_symbol = NULL; | |
8939 | ex.X_add_number = 0; | |
8940 | ||
fb251650 ILT |
8941 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
8942 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
8943 | ||
0dd2d296 ILT |
8944 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
8945 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
8946 | (int) BFD_RELOC_LO16); |
8947 | ||
0dd2d296 ILT |
8948 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
8949 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
8950 | |
8951 | demand_empty_rest_of_line (); | |
8952 | } | |
8953 | ||
8954 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
8955 | offset from $sp. The offset is remembered, and after making a PIC | |
8956 | call $gp is restored from that location. */ | |
8957 | ||
8958 | static void | |
8959 | s_cprestore (ignore) | |
8960 | int ignore; | |
8961 | { | |
8962 | expressionS ex; | |
8963 | int icnt = 0; | |
8964 | ||
d9aba805 ILT |
8965 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
8966 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
8967 | { |
8968 | s_ignore (0); | |
8969 | return; | |
8970 | } | |
8971 | ||
9226253a ILT |
8972 | mips_cprestore_offset = get_absolute_expression (); |
8973 | ||
8974 | ex.X_op = O_constant; | |
8975 | ex.X_add_symbol = NULL; | |
8976 | ex.X_op_symbol = NULL; | |
8977 | ex.X_add_number = mips_cprestore_offset; | |
8978 | ||
0dd2d296 | 8979 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
8980 | mips_isa < 3 ? "sw" : "sd", |
8981 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
8982 | ||
8983 | demand_empty_rest_of_line (); | |
8984 | } | |
8985 | ||
0dd2d296 ILT |
8986 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
8987 | code. It generates a 32 bit GP relative reloc. */ | |
8988 | ||
8989 | static void | |
8990 | s_gpword (ignore) | |
8991 | int ignore; | |
8992 | { | |
23dc1ae3 | 8993 | symbolS *label; |
0dd2d296 ILT |
8994 | expressionS ex; |
8995 | char *p; | |
8996 | ||
8997 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 8998 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
8999 | { |
9000 | s_cons (2); | |
9001 | return; | |
9002 | } | |
9003 | ||
fbcfacb7 ILT |
9004 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9005 | mips_emit_delays (true); | |
0dd2d296 | 9006 | if (auto_align) |
23dc1ae3 | 9007 | mips_align (2, 0, label); |
fbcfacb7 | 9008 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9009 | |
9010 | expression (&ex); | |
9011 | ||
9012 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9013 | { | |
9014 | as_bad ("Unsupported use of .gpword"); | |
9015 | ignore_rest_of_line (); | |
9016 | } | |
9017 | ||
9018 | p = frag_more (4); | |
9019 | md_number_to_chars (p, (valueT) 0, 4); | |
9020 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9021 | BFD_RELOC_MIPS_GPREL32); | |
9022 | ||
9023 | demand_empty_rest_of_line (); | |
9024 | } | |
9025 | ||
9026 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9027 | tables in SVR4 PIC code. */ | |
9028 | ||
9029 | static void | |
9030 | s_cpadd (ignore) | |
9031 | int ignore; | |
9032 | { | |
9033 | int icnt = 0; | |
9034 | int reg; | |
9035 | ||
9036 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9037 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9038 | { |
9039 | s_ignore (0); | |
9040 | return; | |
9041 | } | |
9042 | ||
9043 | /* Add $gp to the register named as an argument. */ | |
9044 | reg = tc_get_register (0); | |
9045 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9046 | mips_isa < 3 ? "addu" : "daddu", | |
9047 | "d,v,t", reg, reg, GP); | |
9048 | ||
9049 | demand_empty_rest_of_line (); | |
9050 | } | |
9051 | ||
9226253a | 9052 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9053 | to parse .frame. The argument is non-zero if this is the frame |
9054 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9055 | |
3d3c5039 | 9056 | int |
0dd2d296 ILT |
9057 | tc_get_register (frame) |
9058 | int frame; | |
3d3c5039 ILT |
9059 | { |
9060 | int reg; | |
9061 | ||
9062 | SKIP_WHITESPACE (); | |
9063 | if (*input_line_pointer++ != '$') | |
9064 | { | |
9065 | as_warn ("expected `$'"); | |
0dd2d296 | 9066 | reg = 0; |
3d3c5039 | 9067 | } |
0dd2d296 | 9068 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9069 | { |
9070 | reg = get_absolute_expression (); | |
9071 | if (reg < 0 || reg >= 32) | |
9072 | { | |
9073 | as_warn ("Bad register number"); | |
9074 | reg = 0; | |
9075 | } | |
9076 | } | |
9077 | else | |
9078 | { | |
9079 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9080 | reg = FP; |
3d3c5039 | 9081 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9082 | reg = SP; |
3d3c5039 | 9083 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9084 | reg = GP; |
3d3c5039 | 9085 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9086 | reg = AT; |
3d3c5039 ILT |
9087 | else |
9088 | { | |
9089 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9090 | reg = 0; |
3d3c5039 ILT |
9091 | } |
9092 | input_line_pointer += 2; | |
9093 | } | |
0dd2d296 ILT |
9094 | if (frame) |
9095 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9096 | return reg; |
9097 | } | |
9098 | ||
0dd2d296 ILT |
9099 | valueT |
9100 | md_section_align (seg, addr) | |
9101 | asection *seg; | |
9102 | valueT addr; | |
9103 | { | |
9104 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9105 | ||
cf32394d ILT |
9106 | #ifdef OBJ_ELF |
9107 | /* We don't need to align ELF sections to the full alignment. | |
9108 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9109 | byte boundary. We don't bother to align the sections if we are |
9110 | targeted for an embedded system. */ | |
9111 | if (strcmp (TARGET_OS, "elf") == 0) | |
9112 | return addr; | |
943321c0 ILT |
9113 | if (align > 4) |
9114 | align = 4; | |
10a14e36 | 9115 | #endif |
cf32394d ILT |
9116 | |
9117 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9118 | } |
9119 | ||
d8a1c247 KR |
9120 | /* Utility routine, called from above as well. If called while the |
9121 | input file is still being read, it's only an approximation. (For | |
9122 | example, a symbol may later become defined which appeared to be | |
9123 | undefined earlier.) */ | |
22ba90ce ILT |
9124 | |
9125 | static int | |
9126 | nopic_need_relax (sym) | |
d8a1c247 KR |
9127 | symbolS *sym; |
9128 | { | |
9129 | if (sym == 0) | |
9130 | return 0; | |
9131 | ||
1dc1e798 KR |
9132 | if (USE_GLOBAL_POINTER_OPT) |
9133 | { | |
9134 | const char *symname; | |
9135 | int change; | |
9136 | ||
9137 | /* Find out whether this symbol can be referenced off the GP | |
9138 | register. It can be if it is smaller than the -G size or if | |
9139 | it is in the .sdata or .sbss section. Certain symbols can | |
9140 | not be referenced off the GP, although it appears as though | |
9141 | they can. */ | |
9142 | symname = S_GET_NAME (sym); | |
9143 | if (symname != (const char *) NULL | |
9144 | && (strcmp (symname, "eprol") == 0 | |
9145 | || strcmp (symname, "etext") == 0 | |
9146 | || strcmp (symname, "_gp") == 0 | |
9147 | || strcmp (symname, "edata") == 0 | |
9148 | || strcmp (symname, "_fbss") == 0 | |
9149 | || strcmp (symname, "_fdata") == 0 | |
9150 | || strcmp (symname, "_ftext") == 0 | |
9151 | || strcmp (symname, "end") == 0 | |
9152 | || strcmp (symname, "_gp_disp") == 0)) | |
9153 | change = 1; | |
9154 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
9155 | && (0 |
9156 | #ifndef NO_ECOFF_DEBUGGING | |
9157 | || (sym->ecoff_extern_size != 0 | |
9158 | && sym->ecoff_extern_size <= g_switch_value) | |
9159 | #endif | |
1dc1e798 KR |
9160 | || (S_GET_VALUE (sym) != 0 |
9161 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9162 | change = 0; | |
9163 | else | |
9164 | { | |
9165 | const char *segname; | |
d8a1c247 | 9166 | |
1dc1e798 KR |
9167 | segname = segment_name (S_GET_SEGMENT (sym)); |
9168 | assert (strcmp (segname, ".lit8") != 0 | |
9169 | && strcmp (segname, ".lit4") != 0); | |
9170 | change = (strcmp (segname, ".sdata") != 0 | |
9171 | && strcmp (segname, ".sbss") != 0); | |
9172 | } | |
9173 | return change; | |
9174 | } | |
9175 | else | |
9176 | /* We are not optimizing for the GP register. */ | |
9177 | return 1; | |
d8a1c247 KR |
9178 | } |
9179 | ||
cc5703cd ILT |
9180 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9181 | extended opcode. SEC is the section the frag is in. */ | |
9182 | ||
9183 | static int | |
9184 | mips16_extended_frag (fragp, sec, stretch) | |
9185 | fragS *fragp; | |
9186 | asection *sec; | |
9187 | long stretch; | |
9188 | { | |
9189 | int type; | |
9190 | register const struct mips16_immed_operand *op; | |
9191 | offsetT val; | |
9192 | int mintiny, maxtiny; | |
f74ba7a3 | 9193 | segT symsec; |
cc5703cd | 9194 | |
8728fa92 ILT |
9195 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9196 | return 0; | |
9197 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9198 | return 1; | |
9199 | ||
cc5703cd ILT |
9200 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9201 | op = mips16_immed_operands; | |
9202 | while (op->type != type) | |
9203 | { | |
9204 | ++op; | |
9205 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9206 | } | |
9207 | ||
9208 | if (op->unsp) | |
9209 | { | |
9210 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9211 | { | |
9212 | mintiny = 1; | |
9213 | maxtiny = 1 << op->nbits; | |
9214 | } | |
9215 | else | |
9216 | { | |
9217 | mintiny = 0; | |
9218 | maxtiny = (1 << op->nbits) - 1; | |
9219 | } | |
9220 | } | |
9221 | else | |
9222 | { | |
9223 | mintiny = - (1 << (op->nbits - 1)); | |
9224 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9225 | } | |
9226 | ||
f74ba7a3 ILT |
9227 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9228 | a particular frag address. */ | |
9229 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9230 | { | |
9231 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9232 | + fragp->fr_symbol->sy_frag->fr_address); | |
9233 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9234 | } | |
9235 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9236 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9237 | == O_constant)) | |
9238 | { | |
9239 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9240 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9241 | + fragp->fr_symbol->sy_value.X_add_number | |
9242 | + fragp->fr_symbol->sy_frag->fr_address); | |
9243 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9244 | } | |
9245 | else | |
9246 | return 1; | |
cc5703cd ILT |
9247 | |
9248 | if (op->pcrel) | |
9249 | { | |
9250 | addressT addr; | |
9251 | ||
9252 | /* We won't have the section when we are called from | |
9253 | mips_relax_frag. However, we will always have been called | |
9254 | from md_estimate_size_before_relax first. If this is a | |
9255 | branch to a different section, we mark it as such. If SEC is | |
9256 | NULL, and the frag is not marked, then it must be a branch to | |
9257 | the same section. */ | |
9258 | if (sec == NULL) | |
9259 | { | |
9260 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9261 | return 1; | |
9262 | } | |
9263 | else | |
9264 | { | |
f74ba7a3 | 9265 | if (symsec != sec) |
cc5703cd ILT |
9266 | { |
9267 | fragp->fr_subtype = | |
9268 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9269 | ||
9270 | /* FIXME: We should support this, and let the linker | |
9271 | catch branches and loads that are out of range. */ | |
9272 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9273 | "unsupported PC relative reference to different section"); | |
9274 | ||
9275 | return 1; | |
9276 | } | |
9277 | } | |
9278 | ||
9279 | /* In this case, we know for sure that the symbol fragment is in | |
9280 | the same section. If the fr_address of the symbol fragment | |
9281 | is greater then the address of this fragment we want to add | |
9282 | in STRETCH in order to get a better estimate of the address. | |
9283 | This particularly matters because of the shift bits. */ | |
9284 | if (stretch != 0 | |
9285 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9286 | { | |
9287 | fragS *f; | |
9288 | ||
9289 | /* Adjust stretch for any alignment frag. */ | |
9290 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) | |
9291 | { | |
9292 | assert (f != NULL); | |
9293 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9294 | { | |
9295 | if (stretch < 0) | |
9296 | stretch = - ((- stretch) | |
9297 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9298 | else | |
9299 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9300 | if (stretch == 0) | |
9301 | break; | |
9302 | } | |
9303 | } | |
9304 | val += stretch; | |
9305 | } | |
9306 | ||
a677feeb ILT |
9307 | addr = fragp->fr_address + fragp->fr_fix; |
9308 | ||
9309 | /* The base address rules are complicated. The base address of | |
9310 | a branch is the following instruction. The base address of a | |
9311 | PC relative load or add is the instruction itself, but if it | |
9312 | is extended add 2, and if it is in a delay slot (in which | |
9313 | case it can not be extended) use the address of the | |
9314 | instruction whose delay slot it is in. */ | |
9315 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9316 | { |
9317 | addr += 2; | |
9318 | /* Ignore the low bit in the target, since it will be set | |
9319 | for a text label. */ | |
9320 | if ((val & 1) != 0) | |
9321 | --val; | |
9322 | } | |
a677feeb ILT |
9323 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9324 | addr -= 4; | |
9325 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9326 | addr -= 2; | |
cc5703cd ILT |
9327 | |
9328 | /* If we are currently assuming that this frag should be | |
9329 | extended, then the current address is two bytes higher. */ | |
9330 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9331 | addr += 2; | |
9332 | ||
9333 | val -= addr & ~ ((1 << op->shift) - 1); | |
9334 | ||
9335 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9336 | if (type == 'p' || type == 'q') | |
9337 | val /= 2; | |
9338 | ||
9339 | /* If any of the shifted bits are set, we must use an extended | |
9340 | opcode. If the address depends on the size of this | |
9341 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9342 | use an extended opcode. We only check this when we are in |
9343 | the main relaxation loop, when SEC is NULL. */ | |
9344 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9345 | { | |
9346 | fragp->fr_subtype = | |
9347 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9348 | return 1; | |
9349 | } | |
9350 | ||
9351 | /* If we are about to mark a frag as extended because the value | |
9352 | is precisely maxtiny + 1, then there is a chance of an | |
9353 | infinite loop as in the following code: | |
9354 | la $4,foo | |
9355 | .skip 1020 | |
9356 | .align 2 | |
9357 | foo: | |
9358 | In this case when the la is extended, foo is 0x3fc bytes | |
9359 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9360 | the la must be extended. To avoid this loop, we mark the | |
9361 | frag as extended if it was small, and is about to become | |
9362 | extended with a value of maxtiny + 1. */ | |
9363 | if (val == ((maxtiny + 1) << op->shift) | |
9364 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9365 | && sec == NULL) | |
cc5703cd ILT |
9366 | { |
9367 | fragp->fr_subtype = | |
9368 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9369 | return 1; | |
9370 | } | |
9371 | } | |
41a0ed22 ILT |
9372 | else if (symsec != absolute_section && sec != NULL) |
9373 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9374 | |
9375 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9376 | || val < (mintiny << op->shift) | |
9377 | || val > (maxtiny << op->shift)) | |
9378 | return 1; | |
9379 | else | |
9380 | return 0; | |
9381 | } | |
9382 | ||
9383 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9384 | mips16, we are not really relaxing here, and the final size is | |
9385 | encoded in the subtype information. For the mips16, we have to | |
9386 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9387 | |
0dd2d296 ILT |
9388 | /*ARGSUSED*/ |
9389 | int | |
9390 | md_estimate_size_before_relax (fragp, segtype) | |
9391 | fragS *fragp; | |
9392 | asection *segtype; | |
9393 | { | |
9394 | int change; | |
9395 | ||
cc5703cd ILT |
9396 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9397 | { | |
9398 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9399 | { | |
9400 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9401 | return 4; | |
9402 | } | |
9403 | else | |
9404 | { | |
9405 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9406 | return 2; | |
9407 | } | |
9408 | } | |
9409 | ||
d9aba805 | 9410 | if (mips_pic == NO_PIC) |
0dd2d296 | 9411 | { |
d8a1c247 | 9412 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9413 | } |
d9aba805 | 9414 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9415 | { |
9416 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9417 | ||
9418 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9419 | change = (symsec != &bfd_und_section | |
9420 | && symsec != &bfd_abs_section | |
9421 | && ! bfd_is_com_section (symsec)); | |
9422 | } | |
d9aba805 ILT |
9423 | else |
9424 | abort (); | |
0dd2d296 ILT |
9425 | |
9426 | if (change) | |
9427 | { | |
9428 | /* Record the offset to the first reloc in the fr_opcode field. | |
9429 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9430 | must be expanded. */ | |
9431 | fragp->fr_opcode = (fragp->fr_literal | |
9432 | + fragp->fr_fix | |
9433 | - RELAX_OLD (fragp->fr_subtype) | |
9434 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9435 | /* FIXME: This really needs as_warn_where. */ | |
9436 | if (RELAX_WARN (fragp->fr_subtype)) | |
9437 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9438 | } | |
9439 | ||
9440 | if (! change) | |
9441 | return 0; | |
9442 | else | |
9443 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9444 | } | |
9445 | ||
9446 | /* Translate internal representation of relocation info to BFD target | |
9447 | format. */ | |
9448 | ||
9449 | arelent ** | |
3d3c5039 ILT |
9450 | tc_gen_reloc (section, fixp) |
9451 | asection *section; | |
9452 | fixS *fixp; | |
9453 | { | |
0dd2d296 | 9454 | static arelent *retval[4]; |
3d3c5039 | 9455 | arelent *reloc; |
a8aed9dd | 9456 | bfd_reloc_code_real_type code; |
3d3c5039 | 9457 | |
0dd2d296 ILT |
9458 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9459 | retval[1] = NULL; | |
3d3c5039 ILT |
9460 | |
9461 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9462 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9463 | |
9464 | if (mips_pic == EMBEDDED_PIC | |
9465 | && SWITCH_TABLE (fixp)) | |
9466 | { | |
9467 | /* For a switch table entry we use a special reloc. The addend | |
9468 | is actually the difference between the reloc address and the | |
9469 | subtrahend. */ | |
9470 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9471 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9472 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
9473 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
9474 | } | |
ecd4ca1c ILT |
9475 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
9476 | { | |
9477 | /* We use a special addend for an internal RELLO reloc. */ | |
9478 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9479 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
9480 | else | |
9481 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
9482 | } | |
9483 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
9484 | { | |
9485 | assert (fixp->fx_next != NULL | |
9486 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
9487 | /* We use a special addend for an internal RELHI reloc. The | |
9488 | reloc is relative to the RELLO; adjust the addend | |
9489 | accordingly. */ | |
9490 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9491 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
9492 | + fixp->fx_next->fx_where | |
9493 | - S_GET_VALUE (fixp->fx_subsy)); | |
9494 | else | |
9495 | reloc->addend = (fixp->fx_addnumber | |
9496 | + fixp->fx_next->fx_frag->fr_address | |
9497 | + fixp->fx_next->fx_where); | |
9498 | } | |
1c803e52 | 9499 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
9500 | reloc->addend = fixp->fx_addnumber; |
9501 | else | |
5b63f465 | 9502 | { |
1dc1e798 KR |
9503 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
9504 | /* A gruesome hack which is a result of the gruesome gas reloc | |
9505 | handling. */ | |
9506 | reloc->addend = reloc->address; | |
9507 | else | |
9508 | reloc->addend = -reloc->address; | |
5b63f465 | 9509 | } |
0dd2d296 ILT |
9510 | |
9511 | /* If this is a variant frag, we may need to adjust the existing | |
9512 | reloc and generate a new one. */ | |
9513 | if (fixp->fx_frag->fr_opcode != NULL | |
9514 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
9515 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
9516 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
9517 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9518 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
9519 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9520 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
9521 | { |
9522 | arelent *reloc2; | |
9523 | ||
cc5703cd ILT |
9524 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
9525 | ||
0dd2d296 | 9526 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
9527 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
9528 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
9529 | the second one handle all of them. */ | |
0dd2d296 ILT |
9530 | if (fixp->fx_next != NULL |
9531 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
9532 | { | |
fb251650 ILT |
9533 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
9534 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
9535 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9536 | && (fixp->fx_next->fx_r_type | |
9537 | == BFD_RELOC_MIPS_GOT_LO16)) | |
9538 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9539 | && (fixp->fx_next->fx_r_type | |
9540 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
9541 | retval[0] = NULL; |
9542 | return retval; | |
9543 | } | |
9544 | ||
9545 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
9546 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9547 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
9548 | retval[2] = NULL; | |
9549 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9550 | reloc2->address = (reloc->address | |
9551 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
9552 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
9553 | reloc2->addend = fixp->fx_addnumber; | |
9554 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
9555 | assert (reloc2->howto != NULL); | |
9556 | ||
9557 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
9558 | { | |
9559 | arelent *reloc3; | |
9560 | ||
9561 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
9562 | retval[3] = NULL; | |
9563 | *reloc3 = *reloc2; | |
9564 | reloc3->address += 4; | |
9565 | } | |
9566 | ||
d9aba805 | 9567 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
9568 | { |
9569 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
9570 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
9571 | } | |
d9aba805 | 9572 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 9573 | { |
fb251650 | 9574 | switch (fixp->fx_r_type) |
0dd2d296 | 9575 | { |
fb251650 ILT |
9576 | default: |
9577 | abort (); | |
9578 | case BFD_RELOC_MIPS_GOT16: | |
9579 | break; | |
9580 | case BFD_RELOC_MIPS_CALL16: | |
9581 | case BFD_RELOC_MIPS_GOT_LO16: | |
9582 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 9583 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 9584 | break; |
0dd2d296 ILT |
9585 | } |
9586 | } | |
d9aba805 ILT |
9587 | else |
9588 | abort (); | |
0dd2d296 ILT |
9589 | } |
9590 | ||
a8aed9dd ILT |
9591 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
9592 | fixup_segment converted a non-PC relative reloc into a PC | |
9593 | relative reloc. In such a case, we need to convert the reloc | |
9594 | code. */ | |
9595 | code = fixp->fx_r_type; | |
9596 | if (fixp->fx_pcrel) | |
9597 | { | |
9598 | switch (code) | |
9599 | { | |
9600 | case BFD_RELOC_8: | |
9601 | code = BFD_RELOC_8_PCREL; | |
9602 | break; | |
9603 | case BFD_RELOC_16: | |
9604 | code = BFD_RELOC_16_PCREL; | |
9605 | break; | |
9606 | case BFD_RELOC_32: | |
9607 | code = BFD_RELOC_32_PCREL; | |
9608 | break; | |
bf39474f ILT |
9609 | case BFD_RELOC_64: |
9610 | code = BFD_RELOC_64_PCREL; | |
9611 | break; | |
a8aed9dd ILT |
9612 | case BFD_RELOC_8_PCREL: |
9613 | case BFD_RELOC_16_PCREL: | |
9614 | case BFD_RELOC_32_PCREL: | |
bf39474f | 9615 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 9616 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
9617 | case BFD_RELOC_PCREL_HI16_S: |
9618 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
9619 | break; |
9620 | default: | |
9621 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9622 | "Cannot make %s relocation PC relative", | |
9623 | bfd_get_reloc_code_name (code)); | |
9624 | } | |
9625 | } | |
9626 | ||
d9aba805 ILT |
9627 | /* To support a PC relative reloc when generating embedded PIC code |
9628 | for ECOFF, we use a Cygnus extension. We check for that here to | |
9629 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 9630 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 9631 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
9632 | && mips_pic != EMBEDDED_PIC) |
9633 | reloc->howto = NULL; | |
9634 | else | |
a8aed9dd | 9635 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 9636 | |
52aa70b5 JW |
9637 | if (reloc->howto == NULL) |
9638 | { | |
9639 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
9640 | "Can not represent %s relocation in this object file format", |
9641 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 9642 | retval[0] = NULL; |
52aa70b5 | 9643 | } |
3d3c5039 | 9644 | |
0dd2d296 | 9645 | return retval; |
3d3c5039 ILT |
9646 | } |
9647 | ||
cc5703cd ILT |
9648 | /* Relax a machine dependent frag. This returns the amount by which |
9649 | the current size of the frag should change. */ | |
9650 | ||
9651 | int | |
9652 | mips_relax_frag (fragp, stretch) | |
9653 | fragS *fragp; | |
9654 | long stretch; | |
9655 | { | |
9656 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
9657 | return 0; | |
9658 | ||
9659 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
9660 | { | |
9661 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9662 | return 0; | |
9663 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9664 | return 2; | |
9665 | } | |
9666 | else | |
9667 | { | |
9668 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9669 | return 0; | |
9670 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9671 | return -2; | |
9672 | } | |
9673 | ||
9674 | return 0; | |
9675 | } | |
9676 | ||
0dd2d296 ILT |
9677 | /* Convert a machine dependent frag. */ |
9678 | ||
9679 | void | |
9680 | md_convert_frag (abfd, asec, fragp) | |
9681 | bfd *abfd; | |
9682 | segT asec; | |
9683 | fragS *fragp; | |
3d3c5039 | 9684 | { |
0dd2d296 ILT |
9685 | int old, new; |
9686 | char *fixptr; | |
3d3c5039 | 9687 | |
cc5703cd ILT |
9688 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9689 | { | |
9690 | int type; | |
9691 | register const struct mips16_immed_operand *op; | |
9692 | boolean small, ext; | |
9693 | offsetT val; | |
9694 | bfd_byte *buf; | |
9695 | unsigned long insn; | |
9696 | boolean use_extend; | |
9697 | unsigned short extend; | |
9698 | ||
9699 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
9700 | op = mips16_immed_operands; | |
9701 | while (op->type != type) | |
9702 | ++op; | |
9703 | ||
9704 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9705 | { | |
9706 | small = false; | |
9707 | ext = true; | |
9708 | } | |
9709 | else | |
9710 | { | |
9711 | small = true; | |
9712 | ext = false; | |
9713 | } | |
9714 | ||
f74ba7a3 | 9715 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 9716 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
9717 | if (op->pcrel) |
9718 | { | |
9719 | addressT addr; | |
9720 | ||
a677feeb ILT |
9721 | addr = fragp->fr_address + fragp->fr_fix; |
9722 | ||
9723 | /* The rules for the base address of a PC relative reloc are | |
9724 | complicated; see mips16_extended_frag. */ | |
9725 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9726 | { |
9727 | addr += 2; | |
9728 | /* Ignore the low bit in the target, since it will be | |
9729 | set for a text label. */ | |
9730 | if ((val & 1) != 0) | |
9731 | --val; | |
9732 | } | |
a677feeb ILT |
9733 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9734 | addr -= 4; | |
9735 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9736 | addr -= 2; | |
9737 | ||
cc5703cd ILT |
9738 | if (ext) |
9739 | addr += 2; | |
9740 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
9741 | val -= addr; | |
a677feeb ILT |
9742 | |
9743 | /* Make sure the section winds up with the alignment we have | |
9744 | assumed. */ | |
9745 | if (op->shift > 0) | |
9746 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
9747 | } |
9748 | ||
9749 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
9750 | ||
b9129c6f ILT |
9751 | if (target_big_endian) |
9752 | insn = bfd_getb16 (buf); | |
9753 | else | |
9754 | insn = bfd_getl16 (buf); | |
cc5703cd | 9755 | |
31a2c6ff ILT |
9756 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
9757 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
9758 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
9759 | |
9760 | if (use_extend) | |
9761 | { | |
9762 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
9763 | fragp->fr_fix += 2; | |
9764 | buf += 2; | |
9765 | } | |
3d3c5039 | 9766 | |
cc5703cd ILT |
9767 | md_number_to_chars (buf, insn, 2); |
9768 | fragp->fr_fix += 2; | |
9769 | buf += 2; | |
9770 | } | |
9771 | else | |
9772 | { | |
9773 | if (fragp->fr_opcode == NULL) | |
9774 | return; | |
0dd2d296 | 9775 | |
cc5703cd ILT |
9776 | old = RELAX_OLD (fragp->fr_subtype); |
9777 | new = RELAX_NEW (fragp->fr_subtype); | |
9778 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 9779 | |
cc5703cd ILT |
9780 | if (new > 0) |
9781 | memcpy (fixptr - old, fixptr, new); | |
9782 | ||
9783 | fragp->fr_fix += new - old; | |
9784 | } | |
0dd2d296 | 9785 | } |
becfe05e | 9786 | |
fbcfacb7 ILT |
9787 | #ifdef OBJ_ELF |
9788 | ||
9789 | /* This function is called after the relocs have been generated. | |
9790 | We've been storing mips16 text labels as odd. Here we convert them | |
9791 | back to even for the convenience of the debugger. */ | |
9792 | ||
9793 | void | |
9794 | mips_frob_file_after_relocs () | |
9795 | { | |
9796 | asymbol **syms; | |
9797 | unsigned int count, i; | |
9798 | ||
9799 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9800 | return; | |
9801 | ||
9802 | syms = bfd_get_outsymbols (stdoutput); | |
9803 | count = bfd_get_symcount (stdoutput); | |
9804 | for (i = 0; i < count; i++, syms++) | |
9805 | { | |
9806 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
9807 | && ((*syms)->value & 1) != 0) | |
9808 | { | |
9809 | (*syms)->value &= ~1; | |
9810 | /* If the symbol has an odd size, it was probably computed | |
9811 | incorrectly, so adjust that as well. */ | |
9812 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
9813 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
9814 | } | |
9815 | } | |
9816 | } | |
9817 | ||
9818 | #endif | |
9819 | ||
becfe05e ILT |
9820 | /* This function is called whenever a label is defined. It is used |
9821 | when handling branch delays; if a branch has a label, we assume we | |
9822 | can not move it. */ | |
9823 | ||
9824 | void | |
9825 | mips_define_label (sym) | |
9826 | symbolS *sym; | |
9827 | { | |
fbcfacb7 ILT |
9828 | struct insn_label_list *l; |
9829 | ||
9830 | if (free_insn_labels == NULL) | |
9831 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
9832 | else | |
9833 | { | |
9834 | l = free_insn_labels; | |
9835 | free_insn_labels = l->next; | |
9836 | } | |
9837 | ||
9838 | l->label = sym; | |
9839 | l->next = insn_labels; | |
9840 | insn_labels = l; | |
becfe05e | 9841 | } |
22ba90ce ILT |
9842 | |
9843 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
9844 | In order to work with gcc when using mips-tfile, we must keep all | |
9845 | local labels. However, in other cases, we want to discard them, | |
9846 | since they are useless. */ | |
9847 | ||
9848 | int | |
9849 | mips_local_label (name) | |
9850 | const char *name; | |
9851 | { | |
c625fc23 | 9852 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
9853 | if (ECOFF_DEBUGGING |
9854 | && mips_debug != 0 | |
9855 | && ! ecoff_debugging_seen) | |
9856 | { | |
9857 | /* We were called with -g, but we didn't see any debugging | |
9858 | information. That may mean that gcc is smuggling debugging | |
9859 | information through to mips-tfile, in which case we must | |
9860 | generate all local labels. */ | |
9861 | return 0; | |
9862 | } | |
c625fc23 | 9863 | #endif |
22ba90ce ILT |
9864 | |
9865 | /* Here it's OK to discard local labels. */ | |
9866 | ||
3af584b4 | 9867 | return name[0] == '$'; |
22ba90ce | 9868 | } |
3d3c5039 | 9869 | \f |
739708fa | 9870 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 9871 | |
0dd2d296 | 9872 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
9873 | |
9874 | void | |
9875 | mips_elf_final_processing () | |
9876 | { | |
87178180 ILT |
9877 | /* Write out the register information. */ |
9878 | if (! mips_64) | |
9879 | { | |
9880 | Elf32_RegInfo s; | |
9881 | ||
9882 | s.ri_gprmask = mips_gprmask; | |
9883 | s.ri_cprmask[0] = mips_cprmask[0]; | |
9884 | s.ri_cprmask[1] = mips_cprmask[1]; | |
9885 | s.ri_cprmask[2] = mips_cprmask[2]; | |
9886 | s.ri_cprmask[3] = mips_cprmask[3]; | |
9887 | /* The gp_value field is set by the MIPS ELF backend. */ | |
9888 | ||
9889 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
9890 | ((Elf32_External_RegInfo *) | |
9891 | mips_regmask_frag)); | |
9892 | } | |
9893 | else | |
9894 | { | |
9895 | Elf64_Internal_RegInfo s; | |
9896 | ||
9897 | s.ri_gprmask = mips_gprmask; | |
9898 | s.ri_pad = 0; | |
9899 | s.ri_cprmask[0] = mips_cprmask[0]; | |
9900 | s.ri_cprmask[1] = mips_cprmask[1]; | |
9901 | s.ri_cprmask[2] = mips_cprmask[2]; | |
9902 | s.ri_cprmask[3] = mips_cprmask[3]; | |
9903 | /* The gp_value field is set by the MIPS ELF backend. */ | |
9904 | ||
9905 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
9906 | ((Elf64_External_RegInfo *) | |
9907 | mips_regmask_frag)); | |
9908 | } | |
0dd2d296 ILT |
9909 | |
9910 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
9911 | sort of BFD interface for this. */ | |
9912 | if (mips_any_noreorder) | |
9913 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 9914 | if (mips_pic != NO_PIC) |
0dd2d296 | 9915 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
9916 | } |
9917 | ||
739708fa | 9918 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 9919 | \f |
3d3c5039 ILT |
9920 | /* These functions should really be defined by the object file format, |
9921 | since they are related to debugging information. However, this | |
9922 | code has to work for the a.out format, which does not define them, | |
9923 | so we provide simple versions here. These don't actually generate | |
9924 | any debugging information, but they do simple checking and someday | |
9925 | somebody may make them useful. */ | |
9926 | ||
670a50eb ILT |
9927 | typedef struct loc |
9928 | { | |
9929 | struct loc *loc_next; | |
9930 | unsigned long loc_fileno; | |
9931 | unsigned long loc_lineno; | |
9932 | unsigned long loc_offset; | |
9933 | unsigned short loc_delta; | |
9934 | unsigned short loc_count; | |
3d3c5039 | 9935 | #if 0 |
670a50eb | 9936 | fragS *loc_frag; |
3d3c5039 | 9937 | #endif |
670a50eb ILT |
9938 | } |
9939 | locS; | |
3d3c5039 | 9940 | |
670a50eb ILT |
9941 | typedef struct proc |
9942 | { | |
3d3c5039 ILT |
9943 | struct proc *proc_next; |
9944 | struct symbol *proc_isym; | |
9945 | struct symbol *proc_end; | |
9946 | unsigned long proc_reg_mask; | |
9947 | unsigned long proc_reg_offset; | |
9948 | unsigned long proc_fpreg_mask; | |
9949 | unsigned long proc_fpreg_offset; | |
9950 | unsigned long proc_frameoffset; | |
9951 | unsigned long proc_framereg; | |
9952 | unsigned long proc_pcreg; | |
9953 | locS *proc_iline; | |
9954 | struct file *proc_file; | |
9955 | int proc_index; | |
670a50eb ILT |
9956 | } |
9957 | procS; | |
3d3c5039 | 9958 | |
670a50eb ILT |
9959 | typedef struct file |
9960 | { | |
3d3c5039 ILT |
9961 | struct file *file_next; |
9962 | unsigned long file_fileno; | |
9963 | struct symbol *file_symbol; | |
9964 | struct symbol *file_end; | |
9965 | struct proc *file_proc; | |
9966 | int file_numprocs; | |
670a50eb ILT |
9967 | } |
9968 | fileS; | |
3d3c5039 ILT |
9969 | |
9970 | static struct obstack proc_frags; | |
9971 | static procS *proc_lastP; | |
9972 | static procS *proc_rootP; | |
9973 | static int numprocs; | |
9974 | ||
9975 | static void | |
9976 | md_obj_begin () | |
9977 | { | |
670a50eb | 9978 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
9979 | } |
9980 | ||
9981 | static void | |
9982 | md_obj_end () | |
9983 | { | |
9984 | /* check for premature end, nesting errors, etc */ | |
9985 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 9986 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
9987 | } |
9988 | ||
3d3c5039 ILT |
9989 | static long |
9990 | get_number () | |
9991 | { | |
670a50eb ILT |
9992 | int negative = 0; |
9993 | long val = 0; | |
3d3c5039 | 9994 | |
670a50eb ILT |
9995 | if (*input_line_pointer == '-') |
9996 | { | |
9997 | ++input_line_pointer; | |
9998 | negative = 1; | |
3d3c5039 | 9999 | } |
670a50eb ILT |
10000 | if (!isdigit (*input_line_pointer)) |
10001 | as_bad ("Expected simple number."); | |
10002 | if (input_line_pointer[0] == '0') | |
10003 | { | |
10004 | if (input_line_pointer[1] == 'x') | |
10005 | { | |
10006 | input_line_pointer += 2; | |
10007 | while (isxdigit (*input_line_pointer)) | |
10008 | { | |
10009 | val <<= 4; | |
3a762a0b | 10010 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10011 | } |
670a50eb ILT |
10012 | return negative ? -val : val; |
10013 | } | |
10014 | else | |
10015 | { | |
10016 | ++input_line_pointer; | |
10017 | while (isdigit (*input_line_pointer)) | |
10018 | { | |
10019 | val <<= 3; | |
10020 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10021 | } |
670a50eb | 10022 | return negative ? -val : val; |
3d3c5039 ILT |
10023 | } |
10024 | } | |
670a50eb ILT |
10025 | if (!isdigit (*input_line_pointer)) |
10026 | { | |
10027 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10028 | *input_line_pointer, *input_line_pointer); | |
10029 | as_warn ("Invalid number"); | |
10030 | return -1; | |
3d3c5039 | 10031 | } |
670a50eb ILT |
10032 | while (isdigit (*input_line_pointer)) |
10033 | { | |
10034 | val *= 10; | |
10035 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10036 | } |
670a50eb | 10037 | return negative ? -val : val; |
3d3c5039 ILT |
10038 | } |
10039 | ||
10040 | /* The .file directive; just like the usual .file directive, but there | |
10041 | is an initial number which is the ECOFF file index. */ | |
10042 | ||
10043 | static void | |
10044 | s_file (x) | |
10045 | int x; | |
10046 | { | |
670a50eb | 10047 | int line; |
3d3c5039 | 10048 | |
670a50eb | 10049 | line = get_number (); |
9a7d824a | 10050 | s_app_file (0); |
3d3c5039 ILT |
10051 | } |
10052 | ||
10053 | ||
10054 | /* The .end directive. */ | |
10055 | ||
10056 | static void | |
10057 | s_mipsend (x) | |
10058 | int x; | |
10059 | { | |
670a50eb ILT |
10060 | symbolS *p; |
10061 | ||
10062 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10063 | { | |
10064 | p = get_symbol (); | |
10065 | demand_empty_rest_of_line (); | |
10066 | } | |
10067 | else | |
10068 | p = NULL; | |
10069 | if (now_seg != text_section) | |
10070 | as_warn (".end not in text section"); | |
10071 | if (!proc_lastP) | |
10072 | { | |
10073 | as_warn (".end and no .ent seen yet."); | |
10074 | return; | |
3d3c5039 ILT |
10075 | } |
10076 | ||
670a50eb ILT |
10077 | if (p != NULL) |
10078 | { | |
10079 | assert (S_GET_NAME (p)); | |
10080 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10081 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10082 | } |
10083 | ||
670a50eb | 10084 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10085 | } |
10086 | ||
10087 | /* The .aent and .ent directives. */ | |
10088 | ||
10089 | static void | |
10090 | s_ent (aent) | |
10091 | int aent; | |
10092 | { | |
670a50eb ILT |
10093 | int number = 0; |
10094 | procS *procP; | |
10095 | symbolS *symbolP; | |
10096 | ||
10097 | symbolP = get_symbol (); | |
10098 | if (*input_line_pointer == ',') | |
10099 | input_line_pointer++; | |
dd3f1f76 | 10100 | SKIP_WHITESPACE (); |
670a50eb ILT |
10101 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10102 | number = get_number (); | |
10103 | if (now_seg != text_section) | |
10104 | as_warn (".ent or .aent not in text section."); | |
10105 | ||
10106 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10107 | as_warn ("missing `.end'"); | |
10108 | ||
10109 | if (!aent) | |
10110 | { | |
10111 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10112 | procP->proc_isym = symbolP; | |
10113 | procP->proc_reg_mask = 0; | |
10114 | procP->proc_reg_offset = 0; | |
10115 | procP->proc_fpreg_mask = 0; | |
10116 | procP->proc_fpreg_offset = 0; | |
10117 | procP->proc_frameoffset = 0; | |
10118 | procP->proc_framereg = 0; | |
10119 | procP->proc_pcreg = 0; | |
10120 | procP->proc_end = NULL; | |
10121 | procP->proc_next = NULL; | |
10122 | if (proc_lastP) | |
10123 | proc_lastP->proc_next = procP; | |
10124 | else | |
10125 | proc_rootP = procP; | |
10126 | proc_lastP = procP; | |
10127 | numprocs++; | |
3d3c5039 | 10128 | } |
670a50eb | 10129 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10130 | } |
10131 | ||
10132 | /* The .frame directive. */ | |
10133 | ||
88225433 | 10134 | #if 0 |
3d3c5039 ILT |
10135 | static void |
10136 | s_frame (x) | |
670a50eb | 10137 | int x; |
3d3c5039 | 10138 | { |
670a50eb ILT |
10139 | char str[100]; |
10140 | symbolS *symP; | |
10141 | int frame_reg; | |
10142 | int frame_off; | |
10143 | int pcreg; | |
10144 | ||
0dd2d296 | 10145 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10146 | if (*input_line_pointer == ',') |
10147 | input_line_pointer++; | |
5ac34ac3 | 10148 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10149 | if (*input_line_pointer == ',') |
10150 | input_line_pointer++; | |
0dd2d296 | 10151 | pcreg = tc_get_register (0); |
670a50eb ILT |
10152 | |
10153 | /* bob third eye */ | |
10154 | assert (proc_rootP); | |
10155 | proc_rootP->proc_framereg = frame_reg; | |
10156 | proc_rootP->proc_frameoffset = frame_off; | |
10157 | proc_rootP->proc_pcreg = pcreg; | |
10158 | /* bob macho .frame */ | |
10159 | ||
10160 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10161 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10162 | { |
10163 | if (!proc_lastP) | |
10164 | as_warn ("No .ent for .frame to use."); | |
10165 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10166 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10167 | S_SET_TYPE (symP, N_RMASK); | |
10168 | S_SET_OTHER (symP, 0); | |
10169 | S_SET_DESC (symP, 0); | |
10170 | symP->sy_forward = proc_lastP->proc_isym; | |
10171 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10172 | } |
670a50eb | 10173 | demand_empty_rest_of_line (); |
3d3c5039 | 10174 | } |
88225433 | 10175 | #endif |
3d3c5039 ILT |
10176 | |
10177 | /* The .fmask and .mask directives. */ | |
10178 | ||
88225433 | 10179 | #if 0 |
3d3c5039 ILT |
10180 | static void |
10181 | s_mask (reg_type) | |
10182 | char reg_type; | |
10183 | { | |
670a50eb ILT |
10184 | char str[100], *strP; |
10185 | symbolS *symP; | |
10186 | int i; | |
10187 | unsigned int mask; | |
10188 | int off; | |
10189 | ||
10190 | mask = get_number (); | |
10191 | if (*input_line_pointer == ',') | |
10192 | input_line_pointer++; | |
10193 | off = get_absolute_expression (); | |
10194 | ||
10195 | /* bob only for coff */ | |
10196 | assert (proc_rootP); | |
10197 | if (reg_type == 'F') | |
10198 | { | |
10199 | proc_rootP->proc_fpreg_mask = mask; | |
10200 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10201 | } |
670a50eb ILT |
10202 | else |
10203 | { | |
10204 | proc_rootP->proc_reg_mask = mask; | |
10205 | proc_rootP->proc_reg_offset = off; | |
10206 | } | |
10207 | ||
10208 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10209 | |
670a50eb ILT |
10210 | /* We don't have to write out a mask stab if no saved regs. */ |
10211 | if (!(mask == 0)) | |
10212 | { | |
10213 | if (!proc_lastP) | |
10214 | as_warn ("No .ent for .mask to use."); | |
10215 | strP = str; | |
10216 | for (i = 0; i < 32; i++) | |
10217 | { | |
10218 | if (mask % 2) | |
10219 | { | |
10220 | sprintf (strP, "%c%d,", reg_type, i); | |
10221 | strP += strlen (strP); | |
10222 | } | |
3d3c5039 | 10223 | mask /= 2; |
670a50eb ILT |
10224 | } |
10225 | sprintf (strP, ";%d,", off); | |
10226 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10227 | S_SET_TYPE (symP, N_RMASK); | |
10228 | S_SET_OTHER (symP, 0); | |
10229 | S_SET_DESC (symP, 0); | |
10230 | symP->sy_forward = proc_lastP->proc_isym; | |
10231 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10232 | } |
3d3c5039 | 10233 | } |
88225433 | 10234 | #endif |
3d3c5039 ILT |
10235 | |
10236 | /* The .loc directive. */ | |
10237 | ||
88225433 | 10238 | #if 0 |
3d3c5039 ILT |
10239 | static void |
10240 | s_loc (x) | |
10241 | int x; | |
10242 | { | |
670a50eb ILT |
10243 | symbolS *symbolP; |
10244 | int lineno; | |
10245 | int addroff; | |
3d3c5039 | 10246 | |
670a50eb | 10247 | assert (now_seg == text_section); |
3d3c5039 | 10248 | |
670a50eb | 10249 | lineno = get_number (); |
87e48495 | 10250 | addroff = frag_now_fix (); |
3d3c5039 | 10251 | |
670a50eb ILT |
10252 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10253 | S_SET_TYPE (symbolP, N_SLINE); | |
10254 | S_SET_OTHER (symbolP, 0); | |
10255 | S_SET_DESC (symbolP, lineno); | |
10256 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10257 | } |
88225433 | 10258 | #endif |