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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
db9b2be4 | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
148 | /* True if this is a mips16 instruction and if we want the extended | |
149 | form of INSN_MO. */ | |
150 | bfd_boolean use_extend; | |
151 | ||
152 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
153 | unsigned short extend; | |
154 | ||
155 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
156 | a copy of INSN_MO->match with the operands filled in. */ | |
157 | unsigned long insn_opcode; | |
158 | ||
159 | /* The frag that contains the instruction. */ | |
160 | struct frag *frag; | |
161 | ||
162 | /* The offset into FRAG of the first instruction byte. */ | |
163 | long where; | |
164 | ||
165 | /* The relocs associated with the instruction, if any. */ | |
166 | fixS *fixp[3]; | |
167 | ||
a38419a5 RS |
168 | /* True if this entry cannot be moved from its current position. */ |
169 | unsigned int fixed_p : 1; | |
47e39b9d | 170 | |
708587a4 | 171 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
172 | unsigned int noreorder_p : 1; |
173 | ||
2fa15973 RS |
174 | /* True for mips16 instructions that jump to an absolute address. */ |
175 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
176 | |
177 | /* True if this instruction is complete. */ | |
178 | unsigned int complete_p : 1; | |
47e39b9d RS |
179 | }; |
180 | ||
a325df1d TS |
181 | /* The ABI to use. */ |
182 | enum mips_abi_level | |
183 | { | |
184 | NO_ABI = 0, | |
185 | O32_ABI, | |
186 | O64_ABI, | |
187 | N32_ABI, | |
188 | N64_ABI, | |
189 | EABI_ABI | |
190 | }; | |
191 | ||
192 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 193 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 194 | |
143d77c5 EC |
195 | /* Whether or not we have code that can call pic code. */ |
196 | int mips_abicalls = FALSE; | |
197 | ||
aa6975fb ILT |
198 | /* Whether or not we have code which can be put into a shared |
199 | library. */ | |
200 | static bfd_boolean mips_in_shared = TRUE; | |
201 | ||
252b5132 RH |
202 | /* This is the set of options which may be modified by the .set |
203 | pseudo-op. We use a struct so that .set push and .set pop are more | |
204 | reliable. */ | |
205 | ||
e972090a NC |
206 | struct mips_set_options |
207 | { | |
252b5132 RH |
208 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
209 | if it has not been initialized. Changed by `.set mipsN', and the | |
210 | -mipsN command line option, and the default CPU. */ | |
211 | int isa; | |
1f25f5d3 CD |
212 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
213 | if they have not been initialized. Changed by `.set <asename>', by | |
214 | command line options, and based on the default architecture. */ | |
215 | int ase_mips3d; | |
deec1734 | 216 | int ase_mdmx; |
e16bfa71 | 217 | int ase_smartmips; |
74cd071d | 218 | int ase_dsp; |
8b082fb1 | 219 | int ase_dspr2; |
ef2e4d86 | 220 | int ase_mt; |
dec0624d | 221 | int ase_mcu; |
252b5132 RH |
222 | /* Whether we are assembling for the mips16 processor. 0 if we are |
223 | not, 1 if we are, and -1 if the value has not been initialized. | |
224 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
225 | -nomips16 command line options, and the default CPU. */ | |
226 | int mips16; | |
df58fc94 RS |
227 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
228 | 1 if we are, and -1 if the value has not been initialized. Changed | |
229 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
230 | and -mno-micromips command line options, and the default CPU. */ | |
231 | int micromips; | |
252b5132 RH |
232 | /* Non-zero if we should not reorder instructions. Changed by `.set |
233 | reorder' and `.set noreorder'. */ | |
234 | int noreorder; | |
741fe287 MR |
235 | /* Non-zero if we should not permit the register designated "assembler |
236 | temporary" to be used in instructions. The value is the register | |
237 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
238 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
239 | unsigned int at; | |
252b5132 RH |
240 | /* Non-zero if we should warn when a macro instruction expands into |
241 | more than one machine instruction. Changed by `.set nomacro' and | |
242 | `.set macro'. */ | |
243 | int warn_about_macros; | |
244 | /* Non-zero if we should not move instructions. Changed by `.set | |
245 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
246 | int nomove; | |
247 | /* Non-zero if we should not optimize branches by moving the target | |
248 | of the branch into the delay slot. Actually, we don't perform | |
249 | this optimization anyhow. Changed by `.set bopt' and `.set | |
250 | nobopt'. */ | |
251 | int nobopt; | |
252 | /* Non-zero if we should not autoextend mips16 instructions. | |
253 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
254 | int noautoextend; | |
a325df1d TS |
255 | /* Restrict general purpose registers and floating point registers |
256 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
257 | is passed but can changed if the assembler code uses .set mipsN. */ | |
258 | int gp32; | |
259 | int fp32; | |
fef14a42 TS |
260 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
261 | command line option, and the default CPU. */ | |
262 | int arch; | |
aed1a261 RS |
263 | /* True if ".set sym32" is in effect. */ |
264 | bfd_boolean sym32; | |
037b32b9 AN |
265 | /* True if floating-point operations are not allowed. Changed by .set |
266 | softfloat or .set hardfloat, by command line options -msoft-float or | |
267 | -mhard-float. The default is false. */ | |
268 | bfd_boolean soft_float; | |
269 | ||
270 | /* True if only single-precision floating-point operations are allowed. | |
271 | Changed by .set singlefloat or .set doublefloat, command-line options | |
272 | -msingle-float or -mdouble-float. The default is false. */ | |
273 | bfd_boolean single_float; | |
252b5132 RH |
274 | }; |
275 | ||
037b32b9 AN |
276 | /* This is the struct we use to hold the current set of options. Note |
277 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
278 | -1 to indicate that they have not been initialized. */ | |
279 | ||
a325df1d | 280 | /* True if -mgp32 was passed. */ |
a8e8e863 | 281 | static int file_mips_gp32 = -1; |
a325df1d TS |
282 | |
283 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 284 | static int file_mips_fp32 = -1; |
a325df1d | 285 | |
037b32b9 AN |
286 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
287 | static int file_mips_soft_float = 0; | |
288 | ||
289 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
290 | static int file_mips_single_float = 0; | |
252b5132 | 291 | |
e972090a NC |
292 | static struct mips_set_options mips_opts = |
293 | { | |
037b32b9 AN |
294 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
295 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
dec0624d MR |
296 | /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, |
297 | /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
037b32b9 AN |
298 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, |
299 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 300 | }; |
252b5132 RH |
301 | |
302 | /* These variables are filled in with the masks of registers used. | |
303 | The object format code reads them and puts them in the appropriate | |
304 | place. */ | |
305 | unsigned long mips_gprmask; | |
306 | unsigned long mips_cprmask[4]; | |
307 | ||
308 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 309 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 310 | |
738f4d98 | 311 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
312 | static int file_ase_mips16; |
313 | ||
3994f87e TS |
314 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
315 | || mips_opts.isa == ISA_MIPS32R2 \ | |
316 | || mips_opts.isa == ISA_MIPS64 \ | |
317 | || mips_opts.isa == ISA_MIPS64R2) | |
318 | ||
df58fc94 RS |
319 | /* True if any microMIPS code was produced. */ |
320 | static int file_ase_micromips; | |
321 | ||
b12dd2e4 CF |
322 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
323 | #ifdef TE_IRIX | |
1180b5a4 | 324 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 325 | #else |
1180b5a4 RS |
326 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
327 | because there's no place for any addend, the only acceptable | |
328 | expression is a bare symbol. */ | |
329 | #define MIPS_JALR_HINT_P(EXPR) \ | |
330 | (!HAVE_IN_PLACE_ADDENDS \ | |
331 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
332 | #endif |
333 | ||
1f25f5d3 CD |
334 | /* True if -mips3d was passed or implied by arguments passed on the |
335 | command line (e.g., by -march). */ | |
336 | static int file_ase_mips3d; | |
337 | ||
deec1734 CD |
338 | /* True if -mdmx was passed or implied by arguments passed on the |
339 | command line (e.g., by -march). */ | |
340 | static int file_ase_mdmx; | |
341 | ||
e16bfa71 TS |
342 | /* True if -msmartmips was passed or implied by arguments passed on the |
343 | command line (e.g., by -march). */ | |
344 | static int file_ase_smartmips; | |
345 | ||
ad3fea08 TS |
346 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
347 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 348 | |
74cd071d CF |
349 | /* True if -mdsp was passed or implied by arguments passed on the |
350 | command line (e.g., by -march). */ | |
351 | static int file_ase_dsp; | |
352 | ||
ad3fea08 TS |
353 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
354 | || mips_opts.isa == ISA_MIPS64R2) | |
355 | ||
65263ce3 TS |
356 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
357 | ||
8b082fb1 TS |
358 | /* True if -mdspr2 was passed or implied by arguments passed on the |
359 | command line (e.g., by -march). */ | |
360 | static int file_ase_dspr2; | |
361 | ||
362 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
363 | || mips_opts.isa == ISA_MIPS64R2) | |
364 | ||
ef2e4d86 CF |
365 | /* True if -mmt was passed or implied by arguments passed on the |
366 | command line (e.g., by -march). */ | |
367 | static int file_ase_mt; | |
368 | ||
ad3fea08 TS |
369 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
370 | || mips_opts.isa == ISA_MIPS64R2) | |
371 | ||
dec0624d | 372 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
9ddc84cc MR |
373 | || mips_opts.isa == ISA_MIPS64R2 \ |
374 | || mips_opts.micromips) | |
dec0624d | 375 | |
ec68c924 | 376 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 377 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 378 | static const char *mips_arch_string; |
ec68c924 EC |
379 | |
380 | /* The argument of the -mtune= flag. The architecture for which we | |
381 | are optimizing. */ | |
382 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 383 | static const char *mips_tune_string; |
ec68c924 | 384 | |
316f5878 | 385 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
386 | static int mips_32bitmode = 0; |
387 | ||
316f5878 RS |
388 | /* True if the given ABI requires 32-bit registers. */ |
389 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
390 | ||
391 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
392 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
393 | ((ABI) == N32_ABI \ | |
394 | || (ABI) == N64_ABI \ | |
316f5878 RS |
395 | || (ABI) == O64_ABI) |
396 | ||
ad3fea08 | 397 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
398 | #define ISA_HAS_64BIT_REGS(ISA) \ |
399 | ((ISA) == ISA_MIPS3 \ | |
400 | || (ISA) == ISA_MIPS4 \ | |
401 | || (ISA) == ISA_MIPS5 \ | |
402 | || (ISA) == ISA_MIPS64 \ | |
403 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 404 | |
ad3fea08 TS |
405 | /* Return true if ISA supports 64 bit wide float registers. */ |
406 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
407 | ((ISA) == ISA_MIPS3 \ | |
408 | || (ISA) == ISA_MIPS4 \ | |
409 | || (ISA) == ISA_MIPS5 \ | |
410 | || (ISA) == ISA_MIPS32R2 \ | |
411 | || (ISA) == ISA_MIPS64 \ | |
412 | || (ISA) == ISA_MIPS64R2) | |
413 | ||
af7ee8bf CD |
414 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
415 | instructions. */ | |
707bfff6 | 416 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
417 | ((ISA) == ISA_MIPS64R2 \ |
418 | || (mips_opts.micromips \ | |
419 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
420 | ) | |
af7ee8bf CD |
421 | |
422 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
423 | instructions. */ | |
707bfff6 TS |
424 | #define ISA_HAS_ROR(ISA) \ |
425 | ((ISA) == ISA_MIPS32R2 \ | |
426 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
427 | || mips_opts.ase_smartmips \ |
428 | || mips_opts.micromips \ | |
429 | ) | |
707bfff6 | 430 | |
7455baf8 TS |
431 | /* Return true if ISA supports single-precision floats in odd registers. */ |
432 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
433 | ((ISA) == ISA_MIPS32 \ | |
434 | || (ISA) == ISA_MIPS32R2 \ | |
435 | || (ISA) == ISA_MIPS64 \ | |
436 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 437 | |
ad3fea08 TS |
438 | /* Return true if ISA supports move to/from high part of a 64-bit |
439 | floating-point register. */ | |
440 | #define ISA_HAS_MXHC1(ISA) \ | |
441 | ((ISA) == ISA_MIPS32R2 \ | |
442 | || (ISA) == ISA_MIPS64R2) | |
443 | ||
e013f690 | 444 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 445 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 446 | |
e013f690 | 447 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 448 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 449 | |
ad3fea08 TS |
450 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
451 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 452 | |
316f5878 | 453 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 454 | |
316f5878 | 455 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 456 | |
3b91255e RS |
457 | /* True if relocations are stored in-place. */ |
458 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
459 | ||
aed1a261 RS |
460 | /* The ABI-derived address size. */ |
461 | #define HAVE_64BIT_ADDRESSES \ | |
462 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
463 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 464 | |
aed1a261 RS |
465 | /* The size of symbolic constants (i.e., expressions of the form |
466 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
467 | #define HAVE_32BIT_SYMBOLS \ | |
468 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
469 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 470 | |
b7c7d6c1 TS |
471 | /* Addresses are loaded in different ways, depending on the address size |
472 | in use. The n32 ABI Documentation also mandates the use of additions | |
473 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 474 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 475 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
476 | |
477 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 478 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
479 | |
480 | #define ADDRESS_LOAD_INSN \ | |
481 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
482 | ||
483 | #define ADDRESS_STORE_INSN \ | |
484 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
485 | ||
a4672219 | 486 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
487 | #define CPU_HAS_MIPS16(cpu) \ |
488 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
489 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 490 | |
2309ddf2 | 491 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
492 | #define CPU_HAS_MICROMIPS(cpu) 0 |
493 | ||
60b63b72 RS |
494 | /* True if CPU has a dror instruction. */ |
495 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
496 | ||
497 | /* True if CPU has a ror instruction. */ | |
498 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
499 | ||
dd6a37e7 | 500 | /* True if CPU is in the Octeon family */ |
432233b3 | 501 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 502 | |
dd3cbb7e | 503 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 504 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 505 | |
b19e8a9b AN |
506 | /* True if CPU does not implement the all the coprocessor insns. For these |
507 | CPUs only those COP insns are accepted that are explicitly marked to be | |
508 | available on the CPU. ISA membership for COP insns is ignored. */ | |
dd6a37e7 | 509 | #define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU)) |
b19e8a9b | 510 | |
c8978940 CD |
511 | /* True if mflo and mfhi can be immediately followed by instructions |
512 | which write to the HI and LO registers. | |
513 | ||
514 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
515 | (at least) two instructions between the reads of HI/LO and | |
516 | instructions which write them, and later ISAs do not. Contradicting | |
517 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
518 | the UM for the NEC Vr5000) document needing the instructions between | |
519 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
520 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
521 | earlier-ISA CPUs for which CPU documentation declares that the | |
522 | instructions are really interlocked. */ | |
523 | #define hilo_interlocks \ | |
524 | (mips_opts.isa == ISA_MIPS32 \ | |
525 | || mips_opts.isa == ISA_MIPS32R2 \ | |
526 | || mips_opts.isa == ISA_MIPS64 \ | |
527 | || mips_opts.isa == ISA_MIPS64R2 \ | |
528 | || mips_opts.arch == CPU_R4010 \ | |
529 | || mips_opts.arch == CPU_R10000 \ | |
530 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
531 | || mips_opts.arch == CPU_R14000 \ |
532 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 533 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 534 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 535 | || mips_opts.micromips \ |
c8978940 | 536 | ) |
252b5132 RH |
537 | |
538 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
539 | from the GPRs after they are loaded from memory, and thus does not |
540 | require nops to be inserted. This applies to instructions marked | |
541 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
542 | level I and microMIPS mode instructions are always interlocked. */ |
543 | #define gpr_interlocks \ | |
544 | (mips_opts.isa != ISA_MIPS1 \ | |
545 | || mips_opts.arch == CPU_R3900 \ | |
546 | || mips_opts.micromips \ | |
547 | ) | |
252b5132 | 548 | |
81912461 ILT |
549 | /* Whether the processor uses hardware interlocks to avoid delays |
550 | required by coprocessor instructions, and thus does not require | |
551 | nops to be inserted. This applies to instructions marked | |
552 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
553 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
554 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
555 | levels I, II, and III and microMIPS mode instructions are always |
556 | interlocked. */ | |
bdaaa2e1 | 557 | /* Itbl support may require additional care here. */ |
81912461 ILT |
558 | #define cop_interlocks \ |
559 | ((mips_opts.isa != ISA_MIPS1 \ | |
560 | && mips_opts.isa != ISA_MIPS2 \ | |
561 | && mips_opts.isa != ISA_MIPS3) \ | |
562 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 563 | || mips_opts.micromips \ |
81912461 ILT |
564 | ) |
565 | ||
566 | /* Whether the processor uses hardware interlocks to protect reads | |
567 | from coprocessor registers after they are loaded from memory, and | |
568 | thus does not require nops to be inserted. This applies to | |
569 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
570 | requires at MIPS ISA level I and microMIPS mode instructions are |
571 | always interlocked. */ | |
572 | #define cop_mem_interlocks \ | |
573 | (mips_opts.isa != ISA_MIPS1 \ | |
574 | || mips_opts.micromips \ | |
575 | ) | |
252b5132 | 576 | |
6b76fefe CM |
577 | /* Is this a mfhi or mflo instruction? */ |
578 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
579 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
580 | ||
581 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
582 | or writing the condition code is only possible on the coprocessors and | |
583 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 584 | condition-code flags. */ |
b19e8a9b AN |
585 | #define COP_INSN(PINFO) \ |
586 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
587 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
588 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 589 | |
df58fc94 RS |
590 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
591 | has been selected. This implies, in particular, that addresses of text | |
592 | labels have their LSB set. */ | |
593 | #define HAVE_CODE_COMPRESSION \ | |
594 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
595 | ||
252b5132 RH |
596 | /* MIPS PIC level. */ |
597 | ||
a161fe53 | 598 | enum mips_pic_level mips_pic; |
252b5132 | 599 | |
c9914766 | 600 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 601 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 602 | static int mips_big_got = 0; |
252b5132 RH |
603 | |
604 | /* 1 if trap instructions should used for overflow rather than break | |
605 | instructions. */ | |
c9914766 | 606 | static int mips_trap = 0; |
252b5132 | 607 | |
119d663a | 608 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 609 | by assembling two single width halves into two single width floating |
119d663a NC |
610 | point registers which just happen to alias the double width destination |
611 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 612 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
613 | automatically at assemble time. */ |
614 | static int mips_disable_float_construction; | |
615 | ||
252b5132 RH |
616 | /* Non-zero if any .set noreorder directives were used. */ |
617 | ||
618 | static int mips_any_noreorder; | |
619 | ||
6b76fefe CM |
620 | /* Non-zero if nops should be inserted when the register referenced in |
621 | an mfhi/mflo instruction is read in the next two instructions. */ | |
622 | static int mips_7000_hilo_fix; | |
623 | ||
02ffd3e4 | 624 | /* The size of objects in the small data section. */ |
156c2f8b | 625 | static unsigned int g_switch_value = 8; |
252b5132 RH |
626 | /* Whether the -G option was used. */ |
627 | static int g_switch_seen = 0; | |
628 | ||
629 | #define N_RMASK 0xc4 | |
630 | #define N_VFP 0xd4 | |
631 | ||
632 | /* If we can determine in advance that GP optimization won't be | |
633 | possible, we can skip the relaxation stuff that tries to produce | |
634 | GP-relative references. This makes delay slot optimization work | |
635 | better. | |
636 | ||
637 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
638 | gcc output. It needs to guess right for gcc, otherwise gcc |
639 | will put what it thinks is a GP-relative instruction in a branch | |
640 | delay slot. | |
252b5132 RH |
641 | |
642 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
643 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 644 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
645 | |
646 | /* handle of the OPCODE hash table */ | |
647 | static struct hash_control *op_hash = NULL; | |
648 | ||
649 | /* The opcode hash table we use for the mips16. */ | |
650 | static struct hash_control *mips16_op_hash = NULL; | |
651 | ||
df58fc94 RS |
652 | /* The opcode hash table we use for the microMIPS ASE. */ |
653 | static struct hash_control *micromips_op_hash = NULL; | |
654 | ||
252b5132 RH |
655 | /* This array holds the chars that always start a comment. If the |
656 | pre-processor is disabled, these aren't very useful */ | |
657 | const char comment_chars[] = "#"; | |
658 | ||
659 | /* This array holds the chars that only start a comment at the beginning of | |
660 | a line. If the line seems to have the form '# 123 filename' | |
661 | .line and .file directives will appear in the pre-processed output */ | |
662 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
663 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 664 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
665 | /* Also note that C style comments are always supported. */ |
666 | const char line_comment_chars[] = "#"; | |
667 | ||
bdaaa2e1 | 668 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 669 | const char line_separator_chars[] = ";"; |
252b5132 RH |
670 | |
671 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
672 | const char EXP_CHARS[] = "eE"; | |
673 | ||
674 | /* Chars that mean this number is a floating point constant */ | |
675 | /* As in 0f12.456 */ | |
676 | /* or 0d1.2345e12 */ | |
677 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
678 | ||
679 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
680 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
681 | but nothing is ideal around here. | |
682 | */ | |
683 | ||
684 | static char *insn_error; | |
685 | ||
686 | static int auto_align = 1; | |
687 | ||
688 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
689 | offset in the stack frame from which to restore the $gp register. | |
690 | This is set by the .cprestore pseudo-op, and saved in this | |
691 | variable. */ | |
692 | static offsetT mips_cprestore_offset = -1; | |
693 | ||
67c1ffbe | 694 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 695 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 696 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
697 | static offsetT mips_cpreturn_offset = -1; |
698 | static int mips_cpreturn_register = -1; | |
699 | static int mips_gp_register = GP; | |
def2e0dd | 700 | static int mips_gprel_offset = 0; |
6478892d | 701 | |
7a621144 DJ |
702 | /* Whether mips_cprestore_offset has been set in the current function |
703 | (or whether it has already been warned about, if not). */ | |
704 | static int mips_cprestore_valid = 0; | |
705 | ||
252b5132 RH |
706 | /* This is the register which holds the stack frame, as set by the |
707 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
708 | static int mips_frame_reg = SP; | |
709 | ||
7a621144 DJ |
710 | /* Whether mips_frame_reg has been set in the current function |
711 | (or whether it has already been warned about, if not). */ | |
712 | static int mips_frame_reg_valid = 0; | |
713 | ||
252b5132 RH |
714 | /* To output NOP instructions correctly, we need to keep information |
715 | about the previous two instructions. */ | |
716 | ||
717 | /* Whether we are optimizing. The default value of 2 means to remove | |
718 | unneeded NOPs and swap branch instructions when possible. A value | |
719 | of 1 means to not swap branches. A value of 0 means to always | |
720 | insert NOPs. */ | |
721 | static int mips_optimize = 2; | |
722 | ||
723 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
724 | equivalent to seeing no -g option at all. */ | |
725 | static int mips_debug = 0; | |
726 | ||
7d8e00cf RS |
727 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
728 | #define MAX_VR4130_NOPS 4 | |
729 | ||
730 | /* The maximum number of NOPs needed to fill delay slots. */ | |
731 | #define MAX_DELAY_NOPS 2 | |
732 | ||
733 | /* The maximum number of NOPs needed for any purpose. */ | |
734 | #define MAX_NOPS 4 | |
71400594 RS |
735 | |
736 | /* A list of previous instructions, with index 0 being the most recent. | |
737 | We need to look back MAX_NOPS instructions when filling delay slots | |
738 | or working around processor errata. We need to look back one | |
739 | instruction further if we're thinking about using history[0] to | |
740 | fill a branch delay slot. */ | |
741 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 742 | |
1e915849 | 743 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
744 | static struct mips_cl_insn nop_insn; |
745 | static struct mips_cl_insn mips16_nop_insn; | |
746 | static struct mips_cl_insn micromips_nop16_insn; | |
747 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
748 | |
749 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
750 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
751 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
752 | ||
753 | /* The size of NOP_INSN in bytes. */ | |
754 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 755 | |
252b5132 RH |
756 | /* If this is set, it points to a frag holding nop instructions which |
757 | were inserted before the start of a noreorder section. If those | |
758 | nops turn out to be unnecessary, the size of the frag can be | |
759 | decreased. */ | |
760 | static fragS *prev_nop_frag; | |
761 | ||
762 | /* The number of nop instructions we created in prev_nop_frag. */ | |
763 | static int prev_nop_frag_holds; | |
764 | ||
765 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 766 | prev_nop_frag. */ |
252b5132 RH |
767 | static int prev_nop_frag_required; |
768 | ||
769 | /* The number of instructions we've seen since prev_nop_frag. */ | |
770 | static int prev_nop_frag_since; | |
771 | ||
772 | /* For ECOFF and ELF, relocations against symbols are done in two | |
773 | parts, with a HI relocation and a LO relocation. Each relocation | |
774 | has only 16 bits of space to store an addend. This means that in | |
775 | order for the linker to handle carries correctly, it must be able | |
776 | to locate both the HI and the LO relocation. This means that the | |
777 | relocations must appear in order in the relocation table. | |
778 | ||
779 | In order to implement this, we keep track of each unmatched HI | |
780 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 781 | corresponding LO relocation. */ |
252b5132 | 782 | |
e972090a NC |
783 | struct mips_hi_fixup |
784 | { | |
252b5132 RH |
785 | /* Next HI fixup. */ |
786 | struct mips_hi_fixup *next; | |
787 | /* This fixup. */ | |
788 | fixS *fixp; | |
789 | /* The section this fixup is in. */ | |
790 | segT seg; | |
791 | }; | |
792 | ||
793 | /* The list of unmatched HI relocs. */ | |
794 | ||
795 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
796 | ||
64bdfcaf RS |
797 | /* The frag containing the last explicit relocation operator. |
798 | Null if explicit relocations have not been used. */ | |
799 | ||
800 | static fragS *prev_reloc_op_frag; | |
801 | ||
252b5132 RH |
802 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
803 | ||
804 | #define X ILLEGAL_REG | |
e972090a NC |
805 | static const int mips32_to_16_reg_map[] = |
806 | { | |
252b5132 RH |
807 | X, X, 2, 3, 4, 5, 6, 7, |
808 | X, X, X, X, X, X, X, X, | |
809 | 0, 1, X, X, X, X, X, X, | |
810 | X, X, X, X, X, X, X, X | |
811 | }; | |
812 | #undef X | |
813 | ||
814 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
815 | ||
e972090a NC |
816 | static const unsigned int mips16_to_32_reg_map[] = |
817 | { | |
252b5132 RH |
818 | 16, 17, 2, 3, 4, 5, 6, 7 |
819 | }; | |
60b63b72 | 820 | |
df58fc94 RS |
821 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
822 | ||
823 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
824 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
825 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
826 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
827 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
828 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
829 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
830 | ||
831 | #define X ILLEGAL_REG | |
832 | /* reg type h: 4, 5, 6. */ | |
833 | static const int mips32_to_micromips_reg_h_map[] = | |
834 | { | |
835 | X, X, X, X, 4, 5, 6, X, | |
836 | X, X, X, X, X, X, X, X, | |
837 | X, X, X, X, X, X, X, X, | |
838 | X, X, X, X, X, X, X, X | |
839 | }; | |
840 | ||
841 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
842 | static const int mips32_to_micromips_reg_m_map[] = | |
843 | { | |
844 | 0, X, 2, 3, X, X, X, X, | |
845 | X, X, X, X, X, X, X, X, | |
846 | 4, 1, 5, 6, 7, X, X, X, | |
847 | X, X, X, X, X, X, X, X | |
848 | }; | |
849 | ||
850 | /* reg type q: 0, 2-7. 17. */ | |
851 | static const int mips32_to_micromips_reg_q_map[] = | |
852 | { | |
853 | 0, X, 2, 3, 4, 5, 6, 7, | |
854 | X, X, X, X, X, X, X, X, | |
855 | X, 1, X, X, X, X, X, X, | |
856 | X, X, X, X, X, X, X, X | |
857 | }; | |
858 | ||
859 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
860 | #undef X | |
861 | ||
862 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
863 | ||
864 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
865 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
866 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
867 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
868 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
869 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
870 | ||
871 | /* The microMIPS registers with type h. */ | |
872 | static const unsigned int micromips_to_32_reg_h_map[] = | |
873 | { | |
874 | 5, 5, 6, 4, 4, 4, 4, 4 | |
875 | }; | |
876 | ||
877 | /* The microMIPS registers with type i. */ | |
878 | static const unsigned int micromips_to_32_reg_i_map[] = | |
879 | { | |
880 | 6, 7, 7, 21, 22, 5, 6, 7 | |
881 | }; | |
882 | ||
883 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
884 | ||
885 | /* The microMIPS registers with type m. */ | |
886 | static const unsigned int micromips_to_32_reg_m_map[] = | |
887 | { | |
888 | 0, 17, 2, 3, 16, 18, 19, 20 | |
889 | }; | |
890 | ||
891 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
892 | ||
893 | /* The microMIPS registers with type q. */ | |
894 | static const unsigned int micromips_to_32_reg_q_map[] = | |
895 | { | |
896 | 0, 17, 2, 3, 4, 5, 6, 7 | |
897 | }; | |
898 | ||
899 | /* microMIPS imm type B. */ | |
900 | static const int micromips_imm_b_map[] = | |
901 | { | |
902 | 1, 4, 8, 12, 16, 20, 24, -1 | |
903 | }; | |
904 | ||
905 | /* microMIPS imm type C. */ | |
906 | static const int micromips_imm_c_map[] = | |
907 | { | |
908 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
909 | }; | |
910 | ||
71400594 RS |
911 | /* Classifies the kind of instructions we're interested in when |
912 | implementing -mfix-vr4120. */ | |
c67a084a NC |
913 | enum fix_vr4120_class |
914 | { | |
71400594 RS |
915 | FIX_VR4120_MACC, |
916 | FIX_VR4120_DMACC, | |
917 | FIX_VR4120_MULT, | |
918 | FIX_VR4120_DMULT, | |
919 | FIX_VR4120_DIV, | |
920 | FIX_VR4120_MTHILO, | |
921 | NUM_FIX_VR4120_CLASSES | |
922 | }; | |
923 | ||
c67a084a NC |
924 | /* ...likewise -mfix-loongson2f-jump. */ |
925 | static bfd_boolean mips_fix_loongson2f_jump; | |
926 | ||
927 | /* ...likewise -mfix-loongson2f-nop. */ | |
928 | static bfd_boolean mips_fix_loongson2f_nop; | |
929 | ||
930 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
931 | static bfd_boolean mips_fix_loongson2f; | |
932 | ||
71400594 RS |
933 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
934 | there must be at least one other instruction between an instruction | |
935 | of type X and an instruction of type Y. */ | |
936 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
937 | ||
938 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 939 | static int mips_fix_vr4120; |
4a6a3df4 | 940 | |
7d8e00cf RS |
941 | /* ...likewise -mfix-vr4130. */ |
942 | static int mips_fix_vr4130; | |
943 | ||
6a32d874 CM |
944 | /* ...likewise -mfix-24k. */ |
945 | static int mips_fix_24k; | |
946 | ||
d954098f DD |
947 | /* ...likewise -mfix-cn63xxp1 */ |
948 | static bfd_boolean mips_fix_cn63xxp1; | |
949 | ||
4a6a3df4 AO |
950 | /* We don't relax branches by default, since this causes us to expand |
951 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
952 | fail to compute the offset before expanding the macro to the most | |
953 | efficient expansion. */ | |
954 | ||
955 | static int mips_relax_branch; | |
252b5132 | 956 | \f |
4d7206a2 RS |
957 | /* The expansion of many macros depends on the type of symbol that |
958 | they refer to. For example, when generating position-dependent code, | |
959 | a macro that refers to a symbol may have two different expansions, | |
960 | one which uses GP-relative addresses and one which uses absolute | |
961 | addresses. When generating SVR4-style PIC, a macro may have | |
962 | different expansions for local and global symbols. | |
963 | ||
964 | We handle these situations by generating both sequences and putting | |
965 | them in variant frags. In position-dependent code, the first sequence | |
966 | will be the GP-relative one and the second sequence will be the | |
967 | absolute one. In SVR4 PIC, the first sequence will be for global | |
968 | symbols and the second will be for local symbols. | |
969 | ||
584892a6 RS |
970 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
971 | SECOND are the lengths of the two sequences in bytes. These fields | |
972 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
973 | the subtype has the following flags: | |
4d7206a2 | 974 | |
584892a6 RS |
975 | RELAX_USE_SECOND |
976 | Set if it has been decided that we should use the second | |
977 | sequence instead of the first. | |
978 | ||
979 | RELAX_SECOND_LONGER | |
980 | Set in the first variant frag if the macro's second implementation | |
981 | is longer than its first. This refers to the macro as a whole, | |
982 | not an individual relaxation. | |
983 | ||
984 | RELAX_NOMACRO | |
985 | Set in the first variant frag if the macro appeared in a .set nomacro | |
986 | block and if one alternative requires a warning but the other does not. | |
987 | ||
988 | RELAX_DELAY_SLOT | |
989 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
990 | delay slot. | |
4d7206a2 | 991 | |
df58fc94 RS |
992 | RELAX_DELAY_SLOT_16BIT |
993 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
994 | 16-bit instruction. | |
995 | ||
996 | RELAX_DELAY_SLOT_SIZE_FIRST | |
997 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
998 | the macro is of the wrong size for the branch delay slot. | |
999 | ||
1000 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1001 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1002 | the macro is of the wrong size for the branch delay slot. | |
1003 | ||
4d7206a2 RS |
1004 | The frag's "opcode" points to the first fixup for relaxable code. |
1005 | ||
1006 | Relaxable macros are generated using a sequence such as: | |
1007 | ||
1008 | relax_start (SYMBOL); | |
1009 | ... generate first expansion ... | |
1010 | relax_switch (); | |
1011 | ... generate second expansion ... | |
1012 | relax_end (); | |
1013 | ||
1014 | The code and fixups for the unwanted alternative are discarded | |
1015 | by md_convert_frag. */ | |
584892a6 | 1016 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1017 | |
584892a6 RS |
1018 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1019 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1020 | #define RELAX_USE_SECOND 0x10000 | |
1021 | #define RELAX_SECOND_LONGER 0x20000 | |
1022 | #define RELAX_NOMACRO 0x40000 | |
1023 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1024 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1025 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1026 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1027 | |
4a6a3df4 AO |
1028 | /* Branch without likely bit. If label is out of range, we turn: |
1029 | ||
1030 | beq reg1, reg2, label | |
1031 | delay slot | |
1032 | ||
1033 | into | |
1034 | ||
1035 | bne reg1, reg2, 0f | |
1036 | nop | |
1037 | j label | |
1038 | 0: delay slot | |
1039 | ||
1040 | with the following opcode replacements: | |
1041 | ||
1042 | beq <-> bne | |
1043 | blez <-> bgtz | |
1044 | bltz <-> bgez | |
1045 | bc1f <-> bc1t | |
1046 | ||
1047 | bltzal <-> bgezal (with jal label instead of j label) | |
1048 | ||
1049 | Even though keeping the delay slot instruction in the delay slot of | |
1050 | the branch would be more efficient, it would be very tricky to do | |
1051 | correctly, because we'd have to introduce a variable frag *after* | |
1052 | the delay slot instruction, and expand that instead. Let's do it | |
1053 | the easy way for now, even if the branch-not-taken case now costs | |
1054 | one additional instruction. Out-of-range branches are not supposed | |
1055 | to be common, anyway. | |
1056 | ||
1057 | Branch likely. If label is out of range, we turn: | |
1058 | ||
1059 | beql reg1, reg2, label | |
1060 | delay slot (annulled if branch not taken) | |
1061 | ||
1062 | into | |
1063 | ||
1064 | beql reg1, reg2, 1f | |
1065 | nop | |
1066 | beql $0, $0, 2f | |
1067 | nop | |
1068 | 1: j[al] label | |
1069 | delay slot (executed only if branch taken) | |
1070 | 2: | |
1071 | ||
1072 | It would be possible to generate a shorter sequence by losing the | |
1073 | likely bit, generating something like: | |
b34976b6 | 1074 | |
4a6a3df4 AO |
1075 | bne reg1, reg2, 0f |
1076 | nop | |
1077 | j[al] label | |
1078 | delay slot (executed only if branch taken) | |
1079 | 0: | |
1080 | ||
1081 | beql -> bne | |
1082 | bnel -> beq | |
1083 | blezl -> bgtz | |
1084 | bgtzl -> blez | |
1085 | bltzl -> bgez | |
1086 | bgezl -> bltz | |
1087 | bc1fl -> bc1t | |
1088 | bc1tl -> bc1f | |
1089 | ||
1090 | bltzall -> bgezal (with jal label instead of j label) | |
1091 | bgezall -> bltzal (ditto) | |
1092 | ||
1093 | ||
1094 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1095 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1096 | ((relax_substateT) \ | |
1097 | (0xc0000000 \ | |
1098 | | ((at) & 0x1f) \ | |
1099 | | ((toofar) ? 0x20 : 0) \ | |
1100 | | ((link) ? 0x40 : 0) \ | |
1101 | | ((likely) ? 0x80 : 0) \ | |
1102 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1103 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1104 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1105 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1106 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1107 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1108 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1109 | |
252b5132 RH |
1110 | /* For mips16 code, we use an entirely different form of relaxation. |
1111 | mips16 supports two versions of most instructions which take | |
1112 | immediate values: a small one which takes some small value, and a | |
1113 | larger one which takes a 16 bit value. Since branches also follow | |
1114 | this pattern, relaxing these values is required. | |
1115 | ||
1116 | We can assemble both mips16 and normal MIPS code in a single | |
1117 | object. Therefore, we need to support this type of relaxation at | |
1118 | the same time that we support the relaxation described above. We | |
1119 | use the high bit of the subtype field to distinguish these cases. | |
1120 | ||
1121 | The information we store for this type of relaxation is the | |
1122 | argument code found in the opcode file for this relocation, whether | |
1123 | the user explicitly requested a small or extended form, and whether | |
1124 | the relocation is in a jump or jal delay slot. That tells us the | |
1125 | size of the value, and how it should be stored. We also store | |
1126 | whether the fragment is considered to be extended or not. We also | |
1127 | store whether this is known to be a branch to a different section, | |
1128 | whether we have tried to relax this frag yet, and whether we have | |
1129 | ever extended a PC relative fragment because of a shift count. */ | |
1130 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1131 | (0x80000000 \ | |
1132 | | ((type) & 0xff) \ | |
1133 | | ((small) ? 0x100 : 0) \ | |
1134 | | ((ext) ? 0x200 : 0) \ | |
1135 | | ((dslot) ? 0x400 : 0) \ | |
1136 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1137 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1138 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1139 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1140 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1141 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1142 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1143 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1144 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1145 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1146 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1147 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1148 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1149 | |
df58fc94 RS |
1150 | /* For microMIPS code, we use relaxation similar to one we use for |
1151 | MIPS16 code. Some instructions that take immediate values support | |
1152 | two encodings: a small one which takes some small value, and a | |
1153 | larger one which takes a 16 bit value. As some branches also follow | |
1154 | this pattern, relaxing these values is required. | |
1155 | ||
1156 | We can assemble both microMIPS and normal MIPS code in a single | |
1157 | object. Therefore, we need to support this type of relaxation at | |
1158 | the same time that we support the relaxation described above. We | |
1159 | use one of the high bits of the subtype field to distinguish these | |
1160 | cases. | |
1161 | ||
1162 | The information we store for this type of relaxation is the argument | |
1163 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1164 | selected as the assembler temporary, whether the branch is |
1165 | unconditional, whether it is compact, whether it stores the link | |
1166 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1167 | branches to a sequence of instructions is enabled, and whether the | |
1168 | displacement of a branch is too large to fit as an immediate argument | |
1169 | of a 16-bit and a 32-bit branch, respectively. */ | |
1170 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1171 | relax32, toofar16, toofar32) \ | |
1172 | (0x40000000 \ | |
1173 | | ((type) & 0xff) \ | |
1174 | | (((at) & 0x1f) << 8) \ | |
1175 | | ((uncond) ? 0x2000 : 0) \ | |
1176 | | ((compact) ? 0x4000 : 0) \ | |
1177 | | ((link) ? 0x8000 : 0) \ | |
1178 | | ((relax32) ? 0x10000 : 0) \ | |
1179 | | ((toofar16) ? 0x20000 : 0) \ | |
1180 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1181 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1182 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1183 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1184 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1185 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1186 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1187 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1188 | ||
1189 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1190 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1191 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1192 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1193 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1194 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1195 | |
885add95 CD |
1196 | /* Is the given value a sign-extended 32-bit value? */ |
1197 | #define IS_SEXT_32BIT_NUM(x) \ | |
1198 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1199 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1200 | ||
1201 | /* Is the given value a sign-extended 16-bit value? */ | |
1202 | #define IS_SEXT_16BIT_NUM(x) \ | |
1203 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1204 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1205 | ||
df58fc94 RS |
1206 | /* Is the given value a sign-extended 12-bit value? */ |
1207 | #define IS_SEXT_12BIT_NUM(x) \ | |
1208 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1209 | ||
2051e8c4 MR |
1210 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1211 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1212 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1213 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1214 | ||
bf12938e RS |
1215 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1216 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1217 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1218 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1219 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1220 | ||
1221 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1222 | SHIFT places. */ | |
1223 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1224 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1225 | ||
1226 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1227 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1228 | ||
1229 | include/opcode/mips.h specifies operand fields using the macros | |
1230 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1231 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1232 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1233 | do \ | |
1234 | if (!(MICROMIPS)) \ | |
1235 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1236 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1237 | else \ | |
1238 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1239 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1240 | while (0) | |
bf12938e RS |
1241 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1242 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1243 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1244 | ||
1245 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1246 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1247 | (!(MICROMIPS) \ | |
1248 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1249 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1250 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1251 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1252 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1253 | MIPS16OP_MASK_##FIELD, \ | |
1254 | MIPS16OP_SH_##FIELD) | |
4d7206a2 | 1255 | \f |
df58fc94 RS |
1256 | /* Whether or not we are emitting a branch-likely macro. */ |
1257 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1258 | ||
4d7206a2 RS |
1259 | /* Global variables used when generating relaxable macros. See the |
1260 | comment above RELAX_ENCODE for more details about how relaxation | |
1261 | is used. */ | |
1262 | static struct { | |
1263 | /* 0 if we're not emitting a relaxable macro. | |
1264 | 1 if we're emitting the first of the two relaxation alternatives. | |
1265 | 2 if we're emitting the second alternative. */ | |
1266 | int sequence; | |
1267 | ||
1268 | /* The first relaxable fixup in the current frag. (In other words, | |
1269 | the first fixup that refers to relaxable code.) */ | |
1270 | fixS *first_fixup; | |
1271 | ||
1272 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1273 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1274 | unsigned int sizes[2]; | |
1275 | ||
1276 | /* The symbol on which the choice of sequence depends. */ | |
1277 | symbolS *symbol; | |
1278 | } mips_relax; | |
252b5132 | 1279 | \f |
584892a6 RS |
1280 | /* Global variables used to decide whether a macro needs a warning. */ |
1281 | static struct { | |
1282 | /* True if the macro is in a branch delay slot. */ | |
1283 | bfd_boolean delay_slot_p; | |
1284 | ||
df58fc94 RS |
1285 | /* Set to the length in bytes required if the macro is in a delay slot |
1286 | that requires a specific length of instruction, otherwise zero. */ | |
1287 | unsigned int delay_slot_length; | |
1288 | ||
584892a6 RS |
1289 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1290 | in bytes and sizes[1] is the length of the second alternative. | |
1291 | For non-relaxable macros, both elements give the length of the | |
1292 | macro in bytes. */ | |
1293 | unsigned int sizes[2]; | |
1294 | ||
df58fc94 RS |
1295 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1296 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1297 | is the length of the first instruction of the second alternative. | |
1298 | For non-relaxable macros, both elements give the length of the first | |
1299 | instruction in bytes. | |
1300 | ||
1301 | Set to zero if we haven't yet seen the first instruction. */ | |
1302 | unsigned int first_insn_sizes[2]; | |
1303 | ||
1304 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1305 | first alternative and insns[1] is the number of instructions for the | |
1306 | second alternative. | |
1307 | ||
1308 | For non-relaxable macros, both elements give the number of | |
1309 | instructions for the macro. */ | |
1310 | unsigned int insns[2]; | |
1311 | ||
584892a6 RS |
1312 | /* The first variant frag for this macro. */ |
1313 | fragS *first_frag; | |
1314 | } mips_macro_warning; | |
1315 | \f | |
252b5132 RH |
1316 | /* Prototypes for static functions. */ |
1317 | ||
17a2f251 | 1318 | #define internalError() \ |
252b5132 | 1319 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1320 | |
1321 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1322 | ||
b34976b6 | 1323 | static void append_insn |
df58fc94 RS |
1324 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1325 | bfd_boolean expansionp); | |
7d10b47d | 1326 | static void mips_no_prev_insn (void); |
c67a084a | 1327 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1328 | static void mips16_macro_build |
03ea81db | 1329 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1330 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1331 | static void macro_start (void); |
1332 | static void macro_end (void); | |
17a2f251 TS |
1333 | static void macro (struct mips_cl_insn * ip); |
1334 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1335 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1336 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1337 | static void mips16_immed |
17a2f251 TS |
1338 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1339 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1340 | static size_t my_getSmallExpression |
17a2f251 TS |
1341 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1342 | static void my_getExpression (expressionS *, char *); | |
1343 | static void s_align (int); | |
1344 | static void s_change_sec (int); | |
1345 | static void s_change_section (int); | |
1346 | static void s_cons (int); | |
1347 | static void s_float_cons (int); | |
1348 | static void s_mips_globl (int); | |
1349 | static void s_option (int); | |
1350 | static void s_mipsset (int); | |
1351 | static void s_abicalls (int); | |
1352 | static void s_cpload (int); | |
1353 | static void s_cpsetup (int); | |
1354 | static void s_cplocal (int); | |
1355 | static void s_cprestore (int); | |
1356 | static void s_cpreturn (int); | |
741d6ea8 JM |
1357 | static void s_dtprelword (int); |
1358 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1359 | static void s_tprelword (int); |
1360 | static void s_tpreldword (int); | |
17a2f251 TS |
1361 | static void s_gpvalue (int); |
1362 | static void s_gpword (int); | |
1363 | static void s_gpdword (int); | |
1364 | static void s_cpadd (int); | |
1365 | static void s_insn (int); | |
1366 | static void md_obj_begin (void); | |
1367 | static void md_obj_end (void); | |
1368 | static void s_mips_ent (int); | |
1369 | static void s_mips_end (int); | |
1370 | static void s_mips_frame (int); | |
1371 | static void s_mips_mask (int reg_type); | |
1372 | static void s_mips_stab (int); | |
1373 | static void s_mips_weakext (int); | |
1374 | static void s_mips_file (int); | |
1375 | static void s_mips_loc (int); | |
1376 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1377 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1378 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1379 | static int validate_micromips_insn (const struct mips_opcode *); |
1380 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1381 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1382 | |
1383 | /* Table and functions used to map between CPU/ISA names, and | |
1384 | ISA levels, and CPU numbers. */ | |
1385 | ||
e972090a NC |
1386 | struct mips_cpu_info |
1387 | { | |
e7af610e | 1388 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1389 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1390 | int isa; /* ISA level. */ |
1391 | int cpu; /* CPU number (default CPU if ISA). */ | |
1392 | }; | |
1393 | ||
ad3fea08 TS |
1394 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1395 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1396 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1397 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1398 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1399 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1400 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1401 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
ad3fea08 | 1402 | |
17a2f251 TS |
1403 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1404 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1405 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1406 | \f |
1407 | /* Pseudo-op table. | |
1408 | ||
1409 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1410 | should be defined here, but are currently unsupported: .alias, | |
1411 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1412 | ||
1413 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1414 | specific to the type of debugging information being generated, and | |
1415 | should be defined by the object format: .aent, .begin, .bend, | |
1416 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1417 | .vreg. | |
1418 | ||
1419 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1420 | not MIPS CPU specific, but are also not specific to the object file | |
1421 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1422 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1423 | |
e972090a NC |
1424 | static const pseudo_typeS mips_pseudo_table[] = |
1425 | { | |
beae10d5 | 1426 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1427 | {"option", s_option, 0}, |
1428 | {"set", s_mipsset, 0}, | |
1429 | {"rdata", s_change_sec, 'r'}, | |
1430 | {"sdata", s_change_sec, 's'}, | |
1431 | {"livereg", s_ignore, 0}, | |
1432 | {"abicalls", s_abicalls, 0}, | |
1433 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1434 | {"cpsetup", s_cpsetup, 0}, |
1435 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1436 | {"cprestore", s_cprestore, 0}, |
6478892d | 1437 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1438 | {"dtprelword", s_dtprelword, 0}, |
1439 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1440 | {"tprelword", s_tprelword, 0}, |
1441 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1442 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1443 | {"gpword", s_gpword, 0}, |
10181a0d | 1444 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1445 | {"cpadd", s_cpadd, 0}, |
1446 | {"insn", s_insn, 0}, | |
1447 | ||
beae10d5 | 1448 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1449 | chips. */ |
38a57ae7 | 1450 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1451 | {"bss", s_change_sec, 'b'}, |
1452 | {"err", s_err, 0}, | |
1453 | {"half", s_cons, 1}, | |
1454 | {"dword", s_cons, 3}, | |
1455 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1456 | {"origin", s_org, 0}, |
1457 | {"repeat", s_rept, 0}, | |
252b5132 | 1458 | |
998b3c36 MR |
1459 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1460 | {"sbss", s_change_sec, 'B'}, | |
1461 | ||
beae10d5 | 1462 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1463 | here for one reason or another. */ |
1464 | {"align", s_align, 0}, | |
1465 | {"byte", s_cons, 0}, | |
1466 | {"data", s_change_sec, 'd'}, | |
1467 | {"double", s_float_cons, 'd'}, | |
1468 | {"float", s_float_cons, 'f'}, | |
1469 | {"globl", s_mips_globl, 0}, | |
1470 | {"global", s_mips_globl, 0}, | |
1471 | {"hword", s_cons, 1}, | |
1472 | {"int", s_cons, 2}, | |
1473 | {"long", s_cons, 2}, | |
1474 | {"octa", s_cons, 4}, | |
1475 | {"quad", s_cons, 3}, | |
cca86cc8 | 1476 | {"section", s_change_section, 0}, |
252b5132 RH |
1477 | {"short", s_cons, 1}, |
1478 | {"single", s_float_cons, 'f'}, | |
1479 | {"stabn", s_mips_stab, 'n'}, | |
1480 | {"text", s_change_sec, 't'}, | |
1481 | {"word", s_cons, 2}, | |
add56521 | 1482 | |
add56521 | 1483 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1484 | |
43841e91 | 1485 | { NULL, NULL, 0 }, |
252b5132 RH |
1486 | }; |
1487 | ||
e972090a NC |
1488 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1489 | { | |
beae10d5 KH |
1490 | /* These pseudo-ops should be defined by the object file format. |
1491 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1492 | {"aent", s_mips_ent, 1}, |
1493 | {"bgnb", s_ignore, 0}, | |
1494 | {"end", s_mips_end, 0}, | |
1495 | {"endb", s_ignore, 0}, | |
1496 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1497 | {"file", s_mips_file, 0}, |
252b5132 RH |
1498 | {"fmask", s_mips_mask, 'F'}, |
1499 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1500 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1501 | {"mask", s_mips_mask, 'R'}, |
1502 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1503 | { NULL, NULL, 0 }, |
252b5132 RH |
1504 | }; |
1505 | ||
3ae8dd8d MR |
1506 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1507 | purpose of the `.dc.a' internal pseudo-op. */ | |
1508 | ||
1509 | int | |
1510 | mips_address_bytes (void) | |
1511 | { | |
1512 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1513 | } | |
1514 | ||
17a2f251 | 1515 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1516 | |
1517 | void | |
17a2f251 | 1518 | mips_pop_insert (void) |
252b5132 RH |
1519 | { |
1520 | pop_insert (mips_pseudo_table); | |
1521 | if (! ECOFF_DEBUGGING) | |
1522 | pop_insert (mips_nonecoff_pseudo_table); | |
1523 | } | |
1524 | \f | |
1525 | /* Symbols labelling the current insn. */ | |
1526 | ||
e972090a NC |
1527 | struct insn_label_list |
1528 | { | |
252b5132 RH |
1529 | struct insn_label_list *next; |
1530 | symbolS *label; | |
1531 | }; | |
1532 | ||
252b5132 | 1533 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1534 | #define label_list tc_segment_info_data.labels |
252b5132 | 1535 | |
17a2f251 | 1536 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1537 | static void mips_mark_labels (void); |
1538 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1539 | |
1540 | static inline void | |
17a2f251 | 1541 | mips_clear_insn_labels (void) |
252b5132 RH |
1542 | { |
1543 | register struct insn_label_list **pl; | |
a8dbcb85 | 1544 | segment_info_type *si; |
252b5132 | 1545 | |
a8dbcb85 TS |
1546 | if (now_seg) |
1547 | { | |
1548 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1549 | ; | |
1550 | ||
1551 | si = seg_info (now_seg); | |
1552 | *pl = si->label_list; | |
1553 | si->label_list = NULL; | |
1554 | } | |
252b5132 | 1555 | } |
a8dbcb85 | 1556 | |
df58fc94 RS |
1557 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1558 | ||
1559 | static inline void | |
1560 | mips_mark_labels (void) | |
1561 | { | |
1562 | if (HAVE_CODE_COMPRESSION) | |
1563 | mips_compressed_mark_labels (); | |
1564 | } | |
252b5132 RH |
1565 | \f |
1566 | static char *expr_end; | |
1567 | ||
1568 | /* Expressions which appear in instructions. These are set by | |
1569 | mips_ip. */ | |
1570 | ||
1571 | static expressionS imm_expr; | |
5f74bc13 | 1572 | static expressionS imm2_expr; |
252b5132 RH |
1573 | static expressionS offset_expr; |
1574 | ||
1575 | /* Relocs associated with imm_expr and offset_expr. */ | |
1576 | ||
f6688943 TS |
1577 | static bfd_reloc_code_real_type imm_reloc[3] |
1578 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1579 | static bfd_reloc_code_real_type offset_reloc[3] | |
1580 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1581 | |
df58fc94 RS |
1582 | /* This is set to the resulting size of the instruction to be produced |
1583 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1584 | explicit size is supplied. */ | |
252b5132 | 1585 | |
df58fc94 | 1586 | static unsigned int forced_insn_length; |
252b5132 | 1587 | |
7ed4a06a | 1588 | #ifdef OBJ_ELF |
ecb4347a DJ |
1589 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1590 | ECOFF debugging. */ | |
252b5132 RH |
1591 | |
1592 | static segT pdr_seg; | |
7ed4a06a | 1593 | #endif |
252b5132 | 1594 | |
e013f690 TS |
1595 | /* The default target format to use. */ |
1596 | ||
aeffff67 RS |
1597 | #if defined (TE_FreeBSD) |
1598 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1599 | #elif defined (TE_TMIPS) | |
1600 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1601 | #else | |
1602 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1603 | #endif | |
1604 | ||
e013f690 | 1605 | const char * |
17a2f251 | 1606 | mips_target_format (void) |
e013f690 TS |
1607 | { |
1608 | switch (OUTPUT_FLAVOR) | |
1609 | { | |
e013f690 TS |
1610 | case bfd_target_ecoff_flavour: |
1611 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1612 | case bfd_target_coff_flavour: | |
1613 | return "pe-mips"; | |
1614 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1615 | #ifdef TE_VXWORKS |
1616 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1617 | return (target_big_endian | |
1618 | ? "elf32-bigmips-vxworks" | |
1619 | : "elf32-littlemips-vxworks"); | |
1620 | #endif | |
e013f690 | 1621 | return (target_big_endian |
cfe86eaa | 1622 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1623 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1624 | : (HAVE_NEWABI |
aeffff67 RS |
1625 | ? ELF_TARGET ("elf32-n", "big") |
1626 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1627 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1628 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1629 | : (HAVE_NEWABI |
aeffff67 RS |
1630 | ? ELF_TARGET ("elf32-n", "little") |
1631 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1632 | default: |
1633 | abort (); | |
1634 | return NULL; | |
1635 | } | |
1636 | } | |
1637 | ||
df58fc94 RS |
1638 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1639 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1640 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1641 | major opcode) will require further modifications to the opcode | |
1642 | table. */ | |
1643 | ||
1644 | static inline unsigned int | |
1645 | micromips_insn_length (const struct mips_opcode *mo) | |
1646 | { | |
1647 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1648 | } | |
1649 | ||
1e915849 RS |
1650 | /* Return the length of instruction INSN. */ |
1651 | ||
1652 | static inline unsigned int | |
1653 | insn_length (const struct mips_cl_insn *insn) | |
1654 | { | |
df58fc94 RS |
1655 | if (mips_opts.micromips) |
1656 | return micromips_insn_length (insn->insn_mo); | |
1657 | else if (mips_opts.mips16) | |
1658 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1659 | else | |
1e915849 | 1660 | return 4; |
1e915849 RS |
1661 | } |
1662 | ||
1663 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1664 | ||
1665 | static void | |
1666 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1667 | { | |
1668 | size_t i; | |
1669 | ||
1670 | insn->insn_mo = mo; | |
1671 | insn->use_extend = FALSE; | |
1672 | insn->extend = 0; | |
1673 | insn->insn_opcode = mo->match; | |
1674 | insn->frag = NULL; | |
1675 | insn->where = 0; | |
1676 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1677 | insn->fixp[i] = NULL; | |
1678 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1679 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1680 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1681 | insn->complete_p = 0; |
1e915849 RS |
1682 | } |
1683 | ||
df58fc94 | 1684 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1685 | |
1686 | static void | |
df58fc94 | 1687 | mips_record_compressed_mode (void) |
742a56fe RS |
1688 | { |
1689 | segment_info_type *si; | |
1690 | ||
1691 | si = seg_info (now_seg); | |
1692 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1693 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1694 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1695 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1696 | } |
1697 | ||
1e915849 RS |
1698 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1699 | ||
1700 | static void | |
1701 | install_insn (const struct mips_cl_insn *insn) | |
1702 | { | |
1703 | char *f = insn->frag->fr_literal + insn->where; | |
df58fc94 | 1704 | if (!HAVE_CODE_COMPRESSION) |
1e915849 | 1705 | md_number_to_chars (f, insn->insn_opcode, 4); |
df58fc94 RS |
1706 | else if (mips_opts.micromips) |
1707 | { | |
1708 | unsigned int length = insn_length (insn); | |
1709 | if (length == 2) | |
1710 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1711 | else if (length == 4) | |
1712 | { | |
1713 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1714 | f += 2; | |
1715 | md_number_to_chars (f, insn->insn_opcode & 0xffff, 2); | |
1716 | } | |
1717 | else | |
1718 | as_bad (_("48-bit microMIPS instructions are not supported")); | |
1719 | } | |
1e915849 RS |
1720 | else if (insn->mips16_absolute_jump_p) |
1721 | { | |
1722 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1723 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1724 | } | |
1725 | else | |
1726 | { | |
1727 | if (insn->use_extend) | |
1728 | { | |
1729 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1730 | f += 2; | |
1731 | } | |
1732 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1733 | } | |
df58fc94 | 1734 | mips_record_compressed_mode (); |
1e915849 RS |
1735 | } |
1736 | ||
1737 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1738 | and install the opcode in the new location. */ | |
1739 | ||
1740 | static void | |
1741 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1742 | { | |
1743 | size_t i; | |
1744 | ||
1745 | insn->frag = frag; | |
1746 | insn->where = where; | |
1747 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1748 | if (insn->fixp[i] != NULL) | |
1749 | { | |
1750 | insn->fixp[i]->fx_frag = frag; | |
1751 | insn->fixp[i]->fx_where = where; | |
1752 | } | |
1753 | install_insn (insn); | |
1754 | } | |
1755 | ||
1756 | /* Add INSN to the end of the output. */ | |
1757 | ||
1758 | static void | |
1759 | add_fixed_insn (struct mips_cl_insn *insn) | |
1760 | { | |
1761 | char *f = frag_more (insn_length (insn)); | |
1762 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1763 | } | |
1764 | ||
1765 | /* Start a variant frag and move INSN to the start of the variant part, | |
1766 | marking it as fixed. The other arguments are as for frag_var. */ | |
1767 | ||
1768 | static void | |
1769 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1770 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1771 | { | |
1772 | frag_grow (max_chars); | |
1773 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1774 | insn->fixed_p = 1; | |
1775 | frag_var (rs_machine_dependent, max_chars, var, | |
1776 | subtype, symbol, offset, NULL); | |
1777 | } | |
1778 | ||
1779 | /* Insert N copies of INSN into the history buffer, starting at | |
1780 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1781 | ||
1782 | static void | |
1783 | insert_into_history (unsigned int first, unsigned int n, | |
1784 | const struct mips_cl_insn *insn) | |
1785 | { | |
1786 | if (mips_relax.sequence != 2) | |
1787 | { | |
1788 | unsigned int i; | |
1789 | ||
1790 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1791 | if (i >= first + n) | |
1792 | history[i] = history[i - n]; | |
1793 | else | |
1794 | history[i] = *insn; | |
1795 | } | |
1796 | } | |
1797 | ||
71400594 RS |
1798 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1799 | the idea is to make it obvious at a glance that each errata is | |
1800 | included. */ | |
1801 | ||
1802 | static void | |
1803 | init_vr4120_conflicts (void) | |
1804 | { | |
1805 | #define CONFLICT(FIRST, SECOND) \ | |
1806 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1807 | ||
1808 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1809 | CONFLICT (MACC, DIV); | |
1810 | CONFLICT (DMACC, DIV); | |
1811 | ||
1812 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1813 | CONFLICT (DMULT, DMULT); | |
1814 | CONFLICT (DMULT, DMACC); | |
1815 | CONFLICT (DMACC, DMULT); | |
1816 | CONFLICT (DMACC, DMACC); | |
1817 | ||
1818 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1819 | CONFLICT (MACC, MTHILO); | |
1820 | CONFLICT (DMACC, MTHILO); | |
1821 | ||
1822 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1823 | instruction is executed immediately after a MACC or DMACC | |
1824 | instruction, the result of [either instruction] is incorrect." */ | |
1825 | CONFLICT (MACC, MULT); | |
1826 | CONFLICT (MACC, DMULT); | |
1827 | CONFLICT (DMACC, MULT); | |
1828 | CONFLICT (DMACC, DMULT); | |
1829 | ||
1830 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1831 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1832 | DDIV or DDIVU instruction, the result of the MACC or | |
1833 | DMACC instruction is incorrect.". */ | |
1834 | CONFLICT (DMULT, MACC); | |
1835 | CONFLICT (DMULT, DMACC); | |
1836 | CONFLICT (DIV, MACC); | |
1837 | CONFLICT (DIV, DMACC); | |
1838 | ||
1839 | #undef CONFLICT | |
1840 | } | |
1841 | ||
707bfff6 TS |
1842 | struct regname { |
1843 | const char *name; | |
1844 | unsigned int num; | |
1845 | }; | |
1846 | ||
1847 | #define RTYPE_MASK 0x1ff00 | |
1848 | #define RTYPE_NUM 0x00100 | |
1849 | #define RTYPE_FPU 0x00200 | |
1850 | #define RTYPE_FCC 0x00400 | |
1851 | #define RTYPE_VEC 0x00800 | |
1852 | #define RTYPE_GP 0x01000 | |
1853 | #define RTYPE_CP0 0x02000 | |
1854 | #define RTYPE_PC 0x04000 | |
1855 | #define RTYPE_ACC 0x08000 | |
1856 | #define RTYPE_CCC 0x10000 | |
1857 | #define RNUM_MASK 0x000ff | |
1858 | #define RWARN 0x80000 | |
1859 | ||
1860 | #define GENERIC_REGISTER_NUMBERS \ | |
1861 | {"$0", RTYPE_NUM | 0}, \ | |
1862 | {"$1", RTYPE_NUM | 1}, \ | |
1863 | {"$2", RTYPE_NUM | 2}, \ | |
1864 | {"$3", RTYPE_NUM | 3}, \ | |
1865 | {"$4", RTYPE_NUM | 4}, \ | |
1866 | {"$5", RTYPE_NUM | 5}, \ | |
1867 | {"$6", RTYPE_NUM | 6}, \ | |
1868 | {"$7", RTYPE_NUM | 7}, \ | |
1869 | {"$8", RTYPE_NUM | 8}, \ | |
1870 | {"$9", RTYPE_NUM | 9}, \ | |
1871 | {"$10", RTYPE_NUM | 10}, \ | |
1872 | {"$11", RTYPE_NUM | 11}, \ | |
1873 | {"$12", RTYPE_NUM | 12}, \ | |
1874 | {"$13", RTYPE_NUM | 13}, \ | |
1875 | {"$14", RTYPE_NUM | 14}, \ | |
1876 | {"$15", RTYPE_NUM | 15}, \ | |
1877 | {"$16", RTYPE_NUM | 16}, \ | |
1878 | {"$17", RTYPE_NUM | 17}, \ | |
1879 | {"$18", RTYPE_NUM | 18}, \ | |
1880 | {"$19", RTYPE_NUM | 19}, \ | |
1881 | {"$20", RTYPE_NUM | 20}, \ | |
1882 | {"$21", RTYPE_NUM | 21}, \ | |
1883 | {"$22", RTYPE_NUM | 22}, \ | |
1884 | {"$23", RTYPE_NUM | 23}, \ | |
1885 | {"$24", RTYPE_NUM | 24}, \ | |
1886 | {"$25", RTYPE_NUM | 25}, \ | |
1887 | {"$26", RTYPE_NUM | 26}, \ | |
1888 | {"$27", RTYPE_NUM | 27}, \ | |
1889 | {"$28", RTYPE_NUM | 28}, \ | |
1890 | {"$29", RTYPE_NUM | 29}, \ | |
1891 | {"$30", RTYPE_NUM | 30}, \ | |
1892 | {"$31", RTYPE_NUM | 31} | |
1893 | ||
1894 | #define FPU_REGISTER_NAMES \ | |
1895 | {"$f0", RTYPE_FPU | 0}, \ | |
1896 | {"$f1", RTYPE_FPU | 1}, \ | |
1897 | {"$f2", RTYPE_FPU | 2}, \ | |
1898 | {"$f3", RTYPE_FPU | 3}, \ | |
1899 | {"$f4", RTYPE_FPU | 4}, \ | |
1900 | {"$f5", RTYPE_FPU | 5}, \ | |
1901 | {"$f6", RTYPE_FPU | 6}, \ | |
1902 | {"$f7", RTYPE_FPU | 7}, \ | |
1903 | {"$f8", RTYPE_FPU | 8}, \ | |
1904 | {"$f9", RTYPE_FPU | 9}, \ | |
1905 | {"$f10", RTYPE_FPU | 10}, \ | |
1906 | {"$f11", RTYPE_FPU | 11}, \ | |
1907 | {"$f12", RTYPE_FPU | 12}, \ | |
1908 | {"$f13", RTYPE_FPU | 13}, \ | |
1909 | {"$f14", RTYPE_FPU | 14}, \ | |
1910 | {"$f15", RTYPE_FPU | 15}, \ | |
1911 | {"$f16", RTYPE_FPU | 16}, \ | |
1912 | {"$f17", RTYPE_FPU | 17}, \ | |
1913 | {"$f18", RTYPE_FPU | 18}, \ | |
1914 | {"$f19", RTYPE_FPU | 19}, \ | |
1915 | {"$f20", RTYPE_FPU | 20}, \ | |
1916 | {"$f21", RTYPE_FPU | 21}, \ | |
1917 | {"$f22", RTYPE_FPU | 22}, \ | |
1918 | {"$f23", RTYPE_FPU | 23}, \ | |
1919 | {"$f24", RTYPE_FPU | 24}, \ | |
1920 | {"$f25", RTYPE_FPU | 25}, \ | |
1921 | {"$f26", RTYPE_FPU | 26}, \ | |
1922 | {"$f27", RTYPE_FPU | 27}, \ | |
1923 | {"$f28", RTYPE_FPU | 28}, \ | |
1924 | {"$f29", RTYPE_FPU | 29}, \ | |
1925 | {"$f30", RTYPE_FPU | 30}, \ | |
1926 | {"$f31", RTYPE_FPU | 31} | |
1927 | ||
1928 | #define FPU_CONDITION_CODE_NAMES \ | |
1929 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1930 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1931 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1932 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1933 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1934 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1935 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1936 | {"$fcc7", RTYPE_FCC | 7} | |
1937 | ||
1938 | #define COPROC_CONDITION_CODE_NAMES \ | |
1939 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1940 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1941 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1942 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1943 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1944 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1945 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1946 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1947 | ||
1948 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1949 | {"$a4", RTYPE_GP | 8}, \ | |
1950 | {"$a5", RTYPE_GP | 9}, \ | |
1951 | {"$a6", RTYPE_GP | 10}, \ | |
1952 | {"$a7", RTYPE_GP | 11}, \ | |
1953 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1954 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1955 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1956 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1957 | {"$t0", RTYPE_GP | 12}, \ | |
1958 | {"$t1", RTYPE_GP | 13}, \ | |
1959 | {"$t2", RTYPE_GP | 14}, \ | |
1960 | {"$t3", RTYPE_GP | 15} | |
1961 | ||
1962 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1963 | {"$t0", RTYPE_GP | 8}, \ | |
1964 | {"$t1", RTYPE_GP | 9}, \ | |
1965 | {"$t2", RTYPE_GP | 10}, \ | |
1966 | {"$t3", RTYPE_GP | 11}, \ | |
1967 | {"$t4", RTYPE_GP | 12}, \ | |
1968 | {"$t5", RTYPE_GP | 13}, \ | |
1969 | {"$t6", RTYPE_GP | 14}, \ | |
1970 | {"$t7", RTYPE_GP | 15}, \ | |
1971 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1972 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1973 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1974 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1975 | ||
1976 | /* Remaining symbolic register names */ | |
1977 | #define SYMBOLIC_REGISTER_NAMES \ | |
1978 | {"$zero", RTYPE_GP | 0}, \ | |
1979 | {"$at", RTYPE_GP | 1}, \ | |
1980 | {"$AT", RTYPE_GP | 1}, \ | |
1981 | {"$v0", RTYPE_GP | 2}, \ | |
1982 | {"$v1", RTYPE_GP | 3}, \ | |
1983 | {"$a0", RTYPE_GP | 4}, \ | |
1984 | {"$a1", RTYPE_GP | 5}, \ | |
1985 | {"$a2", RTYPE_GP | 6}, \ | |
1986 | {"$a3", RTYPE_GP | 7}, \ | |
1987 | {"$s0", RTYPE_GP | 16}, \ | |
1988 | {"$s1", RTYPE_GP | 17}, \ | |
1989 | {"$s2", RTYPE_GP | 18}, \ | |
1990 | {"$s3", RTYPE_GP | 19}, \ | |
1991 | {"$s4", RTYPE_GP | 20}, \ | |
1992 | {"$s5", RTYPE_GP | 21}, \ | |
1993 | {"$s6", RTYPE_GP | 22}, \ | |
1994 | {"$s7", RTYPE_GP | 23}, \ | |
1995 | {"$t8", RTYPE_GP | 24}, \ | |
1996 | {"$t9", RTYPE_GP | 25}, \ | |
1997 | {"$k0", RTYPE_GP | 26}, \ | |
1998 | {"$kt0", RTYPE_GP | 26}, \ | |
1999 | {"$k1", RTYPE_GP | 27}, \ | |
2000 | {"$kt1", RTYPE_GP | 27}, \ | |
2001 | {"$gp", RTYPE_GP | 28}, \ | |
2002 | {"$sp", RTYPE_GP | 29}, \ | |
2003 | {"$s8", RTYPE_GP | 30}, \ | |
2004 | {"$fp", RTYPE_GP | 30}, \ | |
2005 | {"$ra", RTYPE_GP | 31} | |
2006 | ||
2007 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2008 | {"$pc", RTYPE_PC | 0} | |
2009 | ||
2010 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2011 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2012 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2013 | {"$v2", RTYPE_VEC | 2}, \ | |
2014 | {"$v3", RTYPE_VEC | 3}, \ | |
2015 | {"$v4", RTYPE_VEC | 4}, \ | |
2016 | {"$v5", RTYPE_VEC | 5}, \ | |
2017 | {"$v6", RTYPE_VEC | 6}, \ | |
2018 | {"$v7", RTYPE_VEC | 7}, \ | |
2019 | {"$v8", RTYPE_VEC | 8}, \ | |
2020 | {"$v9", RTYPE_VEC | 9}, \ | |
2021 | {"$v10", RTYPE_VEC | 10}, \ | |
2022 | {"$v11", RTYPE_VEC | 11}, \ | |
2023 | {"$v12", RTYPE_VEC | 12}, \ | |
2024 | {"$v13", RTYPE_VEC | 13}, \ | |
2025 | {"$v14", RTYPE_VEC | 14}, \ | |
2026 | {"$v15", RTYPE_VEC | 15}, \ | |
2027 | {"$v16", RTYPE_VEC | 16}, \ | |
2028 | {"$v17", RTYPE_VEC | 17}, \ | |
2029 | {"$v18", RTYPE_VEC | 18}, \ | |
2030 | {"$v19", RTYPE_VEC | 19}, \ | |
2031 | {"$v20", RTYPE_VEC | 20}, \ | |
2032 | {"$v21", RTYPE_VEC | 21}, \ | |
2033 | {"$v22", RTYPE_VEC | 22}, \ | |
2034 | {"$v23", RTYPE_VEC | 23}, \ | |
2035 | {"$v24", RTYPE_VEC | 24}, \ | |
2036 | {"$v25", RTYPE_VEC | 25}, \ | |
2037 | {"$v26", RTYPE_VEC | 26}, \ | |
2038 | {"$v27", RTYPE_VEC | 27}, \ | |
2039 | {"$v28", RTYPE_VEC | 28}, \ | |
2040 | {"$v29", RTYPE_VEC | 29}, \ | |
2041 | {"$v30", RTYPE_VEC | 30}, \ | |
2042 | {"$v31", RTYPE_VEC | 31} | |
2043 | ||
2044 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2045 | {"$ac0", RTYPE_ACC | 0}, \ | |
2046 | {"$ac1", RTYPE_ACC | 1}, \ | |
2047 | {"$ac2", RTYPE_ACC | 2}, \ | |
2048 | {"$ac3", RTYPE_ACC | 3} | |
2049 | ||
2050 | static const struct regname reg_names[] = { | |
2051 | GENERIC_REGISTER_NUMBERS, | |
2052 | FPU_REGISTER_NAMES, | |
2053 | FPU_CONDITION_CODE_NAMES, | |
2054 | COPROC_CONDITION_CODE_NAMES, | |
2055 | ||
2056 | /* The $txx registers depends on the abi, | |
2057 | these will be added later into the symbol table from | |
2058 | one of the tables below once mips_abi is set after | |
2059 | parsing of arguments from the command line. */ | |
2060 | SYMBOLIC_REGISTER_NAMES, | |
2061 | ||
2062 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2063 | MDMX_VECTOR_REGISTER_NAMES, | |
2064 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2065 | {0, 0} | |
2066 | }; | |
2067 | ||
2068 | static const struct regname reg_names_o32[] = { | |
2069 | O32_SYMBOLIC_REGISTER_NAMES, | |
2070 | {0, 0} | |
2071 | }; | |
2072 | ||
2073 | static const struct regname reg_names_n32n64[] = { | |
2074 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2075 | {0, 0} | |
2076 | }; | |
2077 | ||
df58fc94 RS |
2078 | /* Check if S points at a valid register specifier according to TYPES. |
2079 | If so, then return 1, advance S to consume the specifier and store | |
2080 | the register's number in REGNOP, otherwise return 0. */ | |
2081 | ||
707bfff6 TS |
2082 | static int |
2083 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2084 | { | |
2085 | symbolS *symbolP; | |
2086 | char *e; | |
2087 | char save_c; | |
2088 | int reg = -1; | |
2089 | ||
2090 | /* Find end of name. */ | |
2091 | e = *s; | |
2092 | if (is_name_beginner (*e)) | |
2093 | ++e; | |
2094 | while (is_part_of_name (*e)) | |
2095 | ++e; | |
2096 | ||
2097 | /* Terminate name. */ | |
2098 | save_c = *e; | |
2099 | *e = '\0'; | |
2100 | ||
2101 | /* Look for a register symbol. */ | |
2102 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2103 | { | |
2104 | int r = S_GET_VALUE (symbolP); | |
2105 | if (r & types) | |
2106 | reg = r & RNUM_MASK; | |
2107 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2108 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2109 | reg = (r & RNUM_MASK) - 2; | |
2110 | } | |
2111 | /* Else see if this is a register defined in an itbl entry. */ | |
2112 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2113 | { | |
2114 | char *n = *s; | |
2115 | unsigned long r; | |
2116 | ||
2117 | if (*n == '$') | |
2118 | ++n; | |
2119 | if (itbl_get_reg_val (n, &r)) | |
2120 | reg = r & RNUM_MASK; | |
2121 | } | |
2122 | ||
2123 | /* Advance to next token if a register was recognised. */ | |
2124 | if (reg >= 0) | |
2125 | *s = e; | |
2126 | else if (types & RWARN) | |
20203fb9 | 2127 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2128 | |
2129 | *e = save_c; | |
2130 | if (regnop) | |
2131 | *regnop = reg; | |
2132 | return reg >= 0; | |
2133 | } | |
2134 | ||
df58fc94 RS |
2135 | /* Check if S points at a valid register list according to TYPES. |
2136 | If so, then return 1, advance S to consume the list and store | |
2137 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2138 | otherwise return 0. A valid list comprises a comma-separated | |
2139 | enumeration of valid single registers and/or dash-separated | |
2140 | contiguous register ranges as determined by their numbers. | |
2141 | ||
2142 | As a special exception if one of s0-s7 registers is specified as | |
2143 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2144 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2145 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2146 | |
2147 | static int | |
2148 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2149 | { | |
2150 | unsigned int reglist = 0; | |
2151 | unsigned int lastregno; | |
2152 | bfd_boolean ok = TRUE; | |
2153 | unsigned int regmask; | |
2309ddf2 | 2154 | char *s_endlist = *s; |
df58fc94 | 2155 | char *s_reset = *s; |
2309ddf2 | 2156 | unsigned int regno; |
df58fc94 RS |
2157 | |
2158 | while (reg_lookup (s, types, ®no)) | |
2159 | { | |
2160 | lastregno = regno; | |
2161 | if (**s == '-') | |
2162 | { | |
2163 | (*s)++; | |
2164 | ok = reg_lookup (s, types, &lastregno); | |
2165 | if (ok && lastregno < regno) | |
2166 | ok = FALSE; | |
2167 | if (!ok) | |
2168 | break; | |
2169 | } | |
2170 | ||
2171 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2172 | { | |
2173 | lastregno = S7; | |
2174 | reglist |= 1 << FP; | |
2175 | } | |
2176 | regmask = 1 << lastregno; | |
2177 | regmask = (regmask << 1) - 1; | |
2178 | regmask ^= (1 << regno) - 1; | |
2179 | reglist |= regmask; | |
2180 | ||
2309ddf2 | 2181 | s_endlist = *s; |
df58fc94 RS |
2182 | if (**s != ',') |
2183 | break; | |
2184 | (*s)++; | |
2185 | } | |
2186 | ||
2187 | if (ok) | |
2309ddf2 | 2188 | *s = s_endlist; |
df58fc94 RS |
2189 | else |
2190 | *s = s_reset; | |
2191 | if (reglistp) | |
2192 | *reglistp = reglist; | |
2193 | return ok && reglist != 0; | |
2194 | } | |
2195 | ||
037b32b9 | 2196 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2197 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2198 | |
2199 | static bfd_boolean | |
f79e2745 | 2200 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2201 | { |
2202 | int isa = mips_opts.isa; | |
2203 | int fp_s, fp_d; | |
2204 | ||
2205 | if (mips_opts.ase_mdmx) | |
2206 | isa |= INSN_MDMX; | |
2207 | if (mips_opts.ase_dsp) | |
2208 | isa |= INSN_DSP; | |
2209 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2210 | isa |= INSN_DSP64; | |
2211 | if (mips_opts.ase_dspr2) | |
2212 | isa |= INSN_DSPR2; | |
2213 | if (mips_opts.ase_mt) | |
2214 | isa |= INSN_MT; | |
2215 | if (mips_opts.ase_mips3d) | |
2216 | isa |= INSN_MIPS3D; | |
2217 | if (mips_opts.ase_smartmips) | |
2218 | isa |= INSN_SMARTMIPS; | |
dec0624d MR |
2219 | if (mips_opts.ase_mcu) |
2220 | isa |= INSN_MCU; | |
037b32b9 | 2221 | |
b19e8a9b AN |
2222 | /* Don't accept instructions based on the ISA if the CPU does not implement |
2223 | all the coprocessor insns. */ | |
2224 | if (NO_ISA_COP (mips_opts.arch) | |
2225 | && COP_INSN (mo->pinfo)) | |
2226 | isa = 0; | |
2227 | ||
037b32b9 AN |
2228 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
2229 | return FALSE; | |
2230 | ||
2231 | /* Check whether the instruction or macro requires single-precision or | |
2232 | double-precision floating-point support. Note that this information is | |
2233 | stored differently in the opcode table for insns and macros. */ | |
2234 | if (mo->pinfo == INSN_MACRO) | |
2235 | { | |
2236 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2237 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2238 | } | |
2239 | else | |
2240 | { | |
2241 | fp_s = mo->pinfo & FP_S; | |
2242 | fp_d = mo->pinfo & FP_D; | |
2243 | } | |
2244 | ||
2245 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2246 | return FALSE; | |
2247 | ||
2248 | if (fp_s && mips_opts.soft_float) | |
2249 | return FALSE; | |
2250 | ||
2251 | return TRUE; | |
2252 | } | |
2253 | ||
2254 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2255 | selected ISA and architecture. */ | |
2256 | ||
2257 | static bfd_boolean | |
2258 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2259 | { | |
2260 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
2261 | } | |
2262 | ||
df58fc94 RS |
2263 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2264 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2265 | ||
2266 | static bfd_boolean | |
2267 | is_size_valid (const struct mips_opcode *mo) | |
2268 | { | |
2269 | if (!mips_opts.micromips) | |
2270 | return TRUE; | |
2271 | ||
2272 | if (!forced_insn_length) | |
2273 | return TRUE; | |
2274 | if (mo->pinfo == INSN_MACRO) | |
2275 | return FALSE; | |
2276 | return forced_insn_length == micromips_insn_length (mo); | |
2277 | } | |
2278 | ||
2279 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
2280 | of the preceding instruction. Always TRUE in the standard MIPS mode. */ | |
2281 | ||
2282 | static bfd_boolean | |
2283 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2284 | { | |
2285 | if (!mips_opts.micromips) | |
2286 | return TRUE; | |
2287 | ||
2288 | if (mo->pinfo == INSN_MACRO) | |
2289 | return TRUE; | |
2290 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
2291 | && micromips_insn_length (mo) != 4) | |
2292 | return FALSE; | |
2293 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2294 | && micromips_insn_length (mo) != 2) | |
2295 | return FALSE; | |
2296 | ||
2297 | return TRUE; | |
2298 | } | |
2299 | ||
707bfff6 TS |
2300 | /* This function is called once, at assembler startup time. It should set up |
2301 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2302 | |
252b5132 | 2303 | void |
17a2f251 | 2304 | md_begin (void) |
252b5132 | 2305 | { |
3994f87e | 2306 | const char *retval = NULL; |
156c2f8b | 2307 | int i = 0; |
252b5132 | 2308 | int broken = 0; |
1f25f5d3 | 2309 | |
0a44bf69 RS |
2310 | if (mips_pic != NO_PIC) |
2311 | { | |
2312 | if (g_switch_seen && g_switch_value != 0) | |
2313 | as_bad (_("-G may not be used in position-independent code")); | |
2314 | g_switch_value = 0; | |
2315 | } | |
2316 | ||
fef14a42 | 2317 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2318 | as_warn (_("Could not set architecture and machine")); |
2319 | ||
252b5132 RH |
2320 | op_hash = hash_new (); |
2321 | ||
2322 | for (i = 0; i < NUMOPCODES;) | |
2323 | { | |
2324 | const char *name = mips_opcodes[i].name; | |
2325 | ||
17a2f251 | 2326 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2327 | if (retval != NULL) |
2328 | { | |
2329 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2330 | mips_opcodes[i].name, retval); | |
2331 | /* Probably a memory allocation problem? Give up now. */ | |
2332 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2333 | } | |
2334 | do | |
2335 | { | |
2336 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2337 | { | |
2338 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2339 | broken = 1; | |
1e915849 RS |
2340 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2341 | { | |
2342 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2343 | if (mips_fix_loongson2f_nop) |
2344 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2345 | nop_insn.fixed_p = 1; |
2346 | } | |
252b5132 RH |
2347 | } |
2348 | ++i; | |
2349 | } | |
2350 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2351 | } | |
2352 | ||
2353 | mips16_op_hash = hash_new (); | |
2354 | ||
2355 | i = 0; | |
2356 | while (i < bfd_mips16_num_opcodes) | |
2357 | { | |
2358 | const char *name = mips16_opcodes[i].name; | |
2359 | ||
17a2f251 | 2360 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2361 | if (retval != NULL) |
2362 | as_fatal (_("internal: can't hash `%s': %s"), | |
2363 | mips16_opcodes[i].name, retval); | |
2364 | do | |
2365 | { | |
2366 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2367 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2368 | != mips16_opcodes[i].match)) | |
2369 | { | |
2370 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2371 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2372 | broken = 1; | |
2373 | } | |
1e915849 RS |
2374 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2375 | { | |
2376 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2377 | mips16_nop_insn.fixed_p = 1; | |
2378 | } | |
252b5132 RH |
2379 | ++i; |
2380 | } | |
2381 | while (i < bfd_mips16_num_opcodes | |
2382 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2383 | } | |
2384 | ||
df58fc94 RS |
2385 | micromips_op_hash = hash_new (); |
2386 | ||
2387 | i = 0; | |
2388 | while (i < bfd_micromips_num_opcodes) | |
2389 | { | |
2390 | const char *name = micromips_opcodes[i].name; | |
2391 | ||
2392 | retval = hash_insert (micromips_op_hash, name, | |
2393 | (void *) µmips_opcodes[i]); | |
2394 | if (retval != NULL) | |
2395 | as_fatal (_("internal: can't hash `%s': %s"), | |
2396 | micromips_opcodes[i].name, retval); | |
2397 | do | |
2398 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2399 | { | |
2400 | struct mips_cl_insn *micromips_nop_insn; | |
2401 | ||
2402 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2403 | broken = 1; | |
2404 | ||
2405 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2406 | micromips_nop_insn = µmips_nop16_insn; | |
2407 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2408 | micromips_nop_insn = µmips_nop32_insn; | |
2409 | else | |
2410 | continue; | |
2411 | ||
2412 | if (micromips_nop_insn->insn_mo == NULL | |
2413 | && strcmp (name, "nop") == 0) | |
2414 | { | |
2415 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2416 | micromips_nop_insn->fixed_p = 1; | |
2417 | } | |
2418 | } | |
2419 | while (++i < bfd_micromips_num_opcodes | |
2420 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2421 | } | |
2422 | ||
252b5132 RH |
2423 | if (broken) |
2424 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2425 | ||
2426 | /* We add all the general register names to the symbol table. This | |
2427 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2428 | for (i = 0; reg_names[i].name; i++) |
2429 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2430 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2431 | &zero_address_frag)); |
2432 | if (HAVE_NEWABI) | |
2433 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2434 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2435 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2436 | &zero_address_frag)); |
707bfff6 TS |
2437 | else |
2438 | for (i = 0; reg_names_o32[i].name; i++) | |
2439 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2440 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2441 | &zero_address_frag)); |
6047c971 | 2442 | |
7d10b47d | 2443 | mips_no_prev_insn (); |
252b5132 RH |
2444 | |
2445 | mips_gprmask = 0; | |
2446 | mips_cprmask[0] = 0; | |
2447 | mips_cprmask[1] = 0; | |
2448 | mips_cprmask[2] = 0; | |
2449 | mips_cprmask[3] = 0; | |
2450 | ||
2451 | /* set the default alignment for the text section (2**2) */ | |
2452 | record_alignment (text_section, 2); | |
2453 | ||
4d0d148d | 2454 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2455 | |
707bfff6 | 2456 | #ifdef OBJ_ELF |
f43abd2b | 2457 | if (IS_ELF) |
252b5132 | 2458 | { |
0a44bf69 RS |
2459 | /* On a native system other than VxWorks, sections must be aligned |
2460 | to 16 byte boundaries. When configured for an embedded ELF | |
2461 | target, we don't bother. */ | |
c41e87e3 CF |
2462 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2463 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2464 | { |
2465 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2466 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2467 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2468 | } | |
2469 | ||
2470 | /* Create a .reginfo section for register masks and a .mdebug | |
2471 | section for debugging information. */ | |
2472 | { | |
2473 | segT seg; | |
2474 | subsegT subseg; | |
2475 | flagword flags; | |
2476 | segT sec; | |
2477 | ||
2478 | seg = now_seg; | |
2479 | subseg = now_subseg; | |
2480 | ||
2481 | /* The ABI says this section should be loaded so that the | |
2482 | running program can access it. However, we don't load it | |
2483 | if we are configured for an embedded target */ | |
2484 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2485 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2486 | flags |= SEC_ALLOC | SEC_LOAD; |
2487 | ||
316f5878 | 2488 | if (mips_abi != N64_ABI) |
252b5132 RH |
2489 | { |
2490 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2491 | ||
195325d2 TS |
2492 | bfd_set_section_flags (stdoutput, sec, flags); |
2493 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2494 | |
252b5132 | 2495 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2496 | } |
2497 | else | |
2498 | { | |
2499 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2500 | .reginfo section. */ | |
2501 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2502 | bfd_set_section_flags (stdoutput, sec, flags); |
2503 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2504 | |
252b5132 RH |
2505 | /* Set up the option header. */ |
2506 | { | |
2507 | Elf_Internal_Options opthdr; | |
2508 | char *f; | |
2509 | ||
2510 | opthdr.kind = ODK_REGINFO; | |
2511 | opthdr.size = (sizeof (Elf_External_Options) | |
2512 | + sizeof (Elf64_External_RegInfo)); | |
2513 | opthdr.section = 0; | |
2514 | opthdr.info = 0; | |
2515 | f = frag_more (sizeof (Elf_External_Options)); | |
2516 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2517 | (Elf_External_Options *) f); | |
2518 | ||
2519 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2520 | } | |
252b5132 RH |
2521 | } |
2522 | ||
2523 | if (ECOFF_DEBUGGING) | |
2524 | { | |
2525 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2526 | (void) bfd_set_section_flags (stdoutput, sec, | |
2527 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2528 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2529 | } | |
f43abd2b | 2530 | else if (mips_flag_pdr) |
ecb4347a DJ |
2531 | { |
2532 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2533 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2534 | SEC_READONLY | SEC_RELOC | |
2535 | | SEC_DEBUGGING); | |
2536 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2537 | } | |
252b5132 RH |
2538 | |
2539 | subseg_set (seg, subseg); | |
2540 | } | |
2541 | } | |
707bfff6 | 2542 | #endif /* OBJ_ELF */ |
252b5132 RH |
2543 | |
2544 | if (! ECOFF_DEBUGGING) | |
2545 | md_obj_begin (); | |
71400594 RS |
2546 | |
2547 | if (mips_fix_vr4120) | |
2548 | init_vr4120_conflicts (); | |
252b5132 RH |
2549 | } |
2550 | ||
2551 | void | |
17a2f251 | 2552 | md_mips_end (void) |
252b5132 | 2553 | { |
02b1ab82 | 2554 | mips_emit_delays (); |
252b5132 RH |
2555 | if (! ECOFF_DEBUGGING) |
2556 | md_obj_end (); | |
2557 | } | |
2558 | ||
2559 | void | |
17a2f251 | 2560 | md_assemble (char *str) |
252b5132 RH |
2561 | { |
2562 | struct mips_cl_insn insn; | |
f6688943 TS |
2563 | bfd_reloc_code_real_type unused_reloc[3] |
2564 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2565 | |
2566 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2567 | imm2_expr.X_op = O_absent; |
252b5132 | 2568 | offset_expr.X_op = O_absent; |
f6688943 TS |
2569 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2570 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2571 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2572 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2573 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2574 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2575 | |
2576 | if (mips_opts.mips16) | |
2577 | mips16_ip (str, &insn); | |
2578 | else | |
2579 | { | |
2580 | mips_ip (str, &insn); | |
beae10d5 KH |
2581 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2582 | str, insn.insn_opcode)); | |
252b5132 RH |
2583 | } |
2584 | ||
2585 | if (insn_error) | |
2586 | { | |
2587 | as_bad ("%s `%s'", insn_error, str); | |
2588 | return; | |
2589 | } | |
2590 | ||
2591 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2592 | { | |
584892a6 | 2593 | macro_start (); |
252b5132 RH |
2594 | if (mips_opts.mips16) |
2595 | mips16_macro (&insn); | |
2596 | else | |
2597 | macro (&insn); | |
584892a6 | 2598 | macro_end (); |
252b5132 RH |
2599 | } |
2600 | else | |
2601 | { | |
2602 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2603 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2604 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2605 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2606 | else |
df58fc94 | 2607 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 RH |
2608 | } |
2609 | } | |
2610 | ||
738e5348 RS |
2611 | /* Convenience functions for abstracting away the differences between |
2612 | MIPS16 and non-MIPS16 relocations. */ | |
2613 | ||
2614 | static inline bfd_boolean | |
2615 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2616 | { | |
2617 | switch (reloc) | |
2618 | { | |
2619 | case BFD_RELOC_MIPS16_JMP: | |
2620 | case BFD_RELOC_MIPS16_GPREL: | |
2621 | case BFD_RELOC_MIPS16_GOT16: | |
2622 | case BFD_RELOC_MIPS16_CALL16: | |
2623 | case BFD_RELOC_MIPS16_HI16_S: | |
2624 | case BFD_RELOC_MIPS16_HI16: | |
2625 | case BFD_RELOC_MIPS16_LO16: | |
2626 | return TRUE; | |
2627 | ||
2628 | default: | |
2629 | return FALSE; | |
2630 | } | |
2631 | } | |
2632 | ||
df58fc94 RS |
2633 | static inline bfd_boolean |
2634 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2635 | { | |
2636 | switch (reloc) | |
2637 | { | |
2638 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2639 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2640 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2641 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2642 | case BFD_RELOC_MICROMIPS_JMP: | |
2643 | case BFD_RELOC_MICROMIPS_HI16: | |
2644 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2645 | case BFD_RELOC_MICROMIPS_LO16: | |
2646 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2647 | case BFD_RELOC_MICROMIPS_GOT16: | |
2648 | case BFD_RELOC_MICROMIPS_CALL16: | |
2649 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2650 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2651 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2652 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2653 | case BFD_RELOC_MICROMIPS_SUB: | |
2654 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2655 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2656 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2657 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2658 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2659 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2660 | case BFD_RELOC_MICROMIPS_JALR: | |
2661 | return TRUE; | |
2662 | ||
2663 | default: | |
2664 | return FALSE; | |
2665 | } | |
2666 | } | |
2667 | ||
2309ddf2 MR |
2668 | static inline bfd_boolean |
2669 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2670 | { | |
2671 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2672 | } | |
2673 | ||
738e5348 RS |
2674 | static inline bfd_boolean |
2675 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2676 | { | |
2309ddf2 | 2677 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2678 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2679 | } |
2680 | ||
2681 | static inline bfd_boolean | |
2682 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2683 | { | |
2309ddf2 | 2684 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2685 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2686 | } |
2687 | ||
2688 | static inline bfd_boolean | |
2689 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2690 | { | |
2309ddf2 | 2691 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2692 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2693 | } | |
2694 | ||
df58fc94 RS |
2695 | static inline bfd_boolean |
2696 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2697 | { | |
2309ddf2 | 2698 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2699 | } |
2700 | ||
5919d012 | 2701 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2702 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2703 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2704 | |
2705 | static inline bfd_boolean | |
17a2f251 | 2706 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2707 | { |
3b91255e | 2708 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2709 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2710 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2711 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2712 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2713 | } | |
2714 | ||
2715 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2716 | reloc_needs_lo_p. */ | |
2717 | ||
2718 | static inline bfd_reloc_code_real_type | |
2719 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2720 | { | |
df58fc94 RS |
2721 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2722 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2723 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2724 | } |
2725 | ||
2726 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2727 | relocation. */ | |
2728 | ||
2729 | static inline bfd_boolean | |
17a2f251 | 2730 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2731 | { |
2732 | return (fixp->fx_next != NULL | |
738e5348 | 2733 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2734 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2735 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2736 | } | |
2737 | ||
252b5132 RH |
2738 | /* This function returns true if modifying a register requires a |
2739 | delay. */ | |
2740 | ||
2741 | static int | |
17a2f251 | 2742 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2743 | { |
2744 | unsigned long prev_pinfo; | |
2745 | ||
47e39b9d | 2746 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2747 | if (! mips_opts.noreorder |
81912461 ILT |
2748 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2749 | && ! gpr_interlocks) | |
2750 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2751 | && ! cop_interlocks))) | |
252b5132 | 2752 | { |
81912461 ILT |
2753 | /* A load from a coprocessor or from memory. All load delays |
2754 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2755 | /* Itbl support may require additional care here. */ |
252b5132 | 2756 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2757 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2758 | return 1; |
2759 | } | |
2760 | ||
2761 | return 0; | |
2762 | } | |
2763 | ||
404a8071 RS |
2764 | /* Move all labels in insn_labels to the current insertion point. */ |
2765 | ||
2766 | static void | |
2767 | mips_move_labels (void) | |
2768 | { | |
a8dbcb85 | 2769 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2770 | struct insn_label_list *l; |
2771 | valueT val; | |
2772 | ||
a8dbcb85 | 2773 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2774 | { |
9c2799c2 | 2775 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2776 | symbol_set_frag (l->label, frag_now); |
2777 | val = (valueT) frag_now_fix (); | |
df58fc94 RS |
2778 | /* MIPS16/microMIPS text labels are stored as odd. */ |
2779 | if (HAVE_CODE_COMPRESSION) | |
404a8071 RS |
2780 | ++val; |
2781 | S_SET_VALUE (l->label, val); | |
2782 | } | |
2783 | } | |
2784 | ||
5f0fe04b TS |
2785 | static bfd_boolean |
2786 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2787 | { | |
2788 | bfd_boolean linkonce = FALSE; | |
2789 | segT symseg = S_GET_SEGMENT (sym); | |
2790 | ||
2791 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2792 | { | |
2793 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2794 | linkonce = TRUE; | |
2795 | #ifdef OBJ_ELF | |
2796 | /* The GNU toolchain uses an extension for ELF: a section | |
2797 | beginning with the magic string .gnu.linkonce is a | |
2798 | linkonce section. */ | |
2799 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2800 | sizeof ".gnu.linkonce" - 1) == 0) | |
2801 | linkonce = TRUE; | |
2802 | #endif | |
2803 | } | |
2804 | return linkonce; | |
2805 | } | |
2806 | ||
df58fc94 RS |
2807 | /* Mark instruction labels in MIPS16/microMIPS mode. This permits the |
2808 | linker to handle them specially, such as generating jalx instructions | |
2809 | when needed. We also make them odd for the duration of the assembly, | |
2810 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2811 | in the adjust_symtab routine, while leaving them marked. This is |
2812 | convenient for the debugger and the disassembler. The linker knows | |
2813 | to make them odd again. */ | |
2814 | ||
2815 | static void | |
df58fc94 | 2816 | mips_compressed_mark_labels (void) |
252b5132 | 2817 | { |
a8dbcb85 TS |
2818 | segment_info_type *si = seg_info (now_seg); |
2819 | struct insn_label_list *l; | |
252b5132 | 2820 | |
df58fc94 | 2821 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 TS |
2822 | |
2823 | for (l = si->label_list; l != NULL; l = l->next) | |
2824 | { | |
2825 | symbolS *label = l->label; | |
2826 | ||
2827 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2828 | if (IS_ELF) |
df58fc94 RS |
2829 | { |
2830 | if (mips_opts.mips16) | |
2831 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2832 | else | |
2833 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
2834 | } | |
252b5132 | 2835 | #endif |
5f0fe04b TS |
2836 | if ((S_GET_VALUE (label) & 1) == 0 |
2837 | /* Don't adjust the address if the label is global or weak, or | |
2838 | in a link-once section, since we'll be emitting symbol reloc | |
2839 | references to it which will be patched up by the linker, and | |
df58fc94 | 2840 | the final value of the symbol may or may not be MIPS16/microMIPS. */ |
5f0fe04b TS |
2841 | && ! S_IS_WEAK (label) |
2842 | && ! S_IS_EXTERNAL (label) | |
2843 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2844 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2845 | } |
2846 | } | |
2847 | ||
4d7206a2 RS |
2848 | /* End the current frag. Make it a variant frag and record the |
2849 | relaxation info. */ | |
2850 | ||
2851 | static void | |
2852 | relax_close_frag (void) | |
2853 | { | |
584892a6 | 2854 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2855 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2856 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2857 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2858 | ||
2859 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2860 | mips_relax.first_fixup = 0; | |
2861 | } | |
2862 | ||
2863 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2864 | See the comment above RELAX_ENCODE for more details. */ | |
2865 | ||
2866 | static void | |
2867 | relax_start (symbolS *symbol) | |
2868 | { | |
9c2799c2 | 2869 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2870 | mips_relax.sequence = 1; |
2871 | mips_relax.symbol = symbol; | |
2872 | } | |
2873 | ||
2874 | /* Start generating the second version of a relaxable sequence. | |
2875 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2876 | |
2877 | static void | |
4d7206a2 RS |
2878 | relax_switch (void) |
2879 | { | |
9c2799c2 | 2880 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2881 | mips_relax.sequence = 2; |
2882 | } | |
2883 | ||
2884 | /* End the current relaxable sequence. */ | |
2885 | ||
2886 | static void | |
2887 | relax_end (void) | |
2888 | { | |
9c2799c2 | 2889 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2890 | relax_close_frag (); |
2891 | mips_relax.sequence = 0; | |
2892 | } | |
2893 | ||
11625dd8 RS |
2894 | /* Return true if IP is a delayed branch or jump. */ |
2895 | ||
2896 | static inline bfd_boolean | |
2897 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2898 | { | |
2899 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2900 | | INSN_COND_BRANCH_DELAY | |
2901 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2902 | } | |
2903 | ||
2904 | /* Return true if IP is a compact branch or jump. */ | |
2905 | ||
2906 | static inline bfd_boolean | |
2907 | compact_branch_p (const struct mips_cl_insn *ip) | |
2908 | { | |
2909 | if (mips_opts.mips16) | |
2910 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2911 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
2912 | else | |
2913 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
2914 | | INSN2_COND_BRANCH)) != 0; | |
2915 | } | |
2916 | ||
2917 | /* Return true if IP is an unconditional branch or jump. */ | |
2918 | ||
2919 | static inline bfd_boolean | |
2920 | uncond_branch_p (const struct mips_cl_insn *ip) | |
2921 | { | |
2922 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
2923 | || (mips_opts.mips16 | |
2924 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
2925 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
2926 | } | |
2927 | ||
2928 | /* Return true if IP is a branch-likely instruction. */ | |
2929 | ||
2930 | static inline bfd_boolean | |
2931 | branch_likely_p (const struct mips_cl_insn *ip) | |
2932 | { | |
2933 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
2934 | } | |
2935 | ||
14fe068b RS |
2936 | /* Return the type of nop that should be used to fill the delay slot |
2937 | of delayed branch IP. */ | |
2938 | ||
2939 | static struct mips_cl_insn * | |
2940 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
2941 | { | |
2942 | if (mips_opts.micromips | |
2943 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
2944 | return µmips_nop32_insn; | |
2945 | return NOP_INSN; | |
2946 | } | |
2947 | ||
2309ddf2 | 2948 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
2949 | |
2950 | static unsigned int | |
2951 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
2952 | { | |
2309ddf2 | 2953 | unsigned long pinfo2; |
df58fc94 RS |
2954 | unsigned int mask; |
2955 | ||
2956 | mask = 0; | |
df58fc94 RS |
2957 | pinfo2 = ip->insn_mo->pinfo2; |
2958 | if (mips_opts.micromips) | |
2959 | { | |
df58fc94 RS |
2960 | if (pinfo2 & INSN2_MOD_GPR_MD) |
2961 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
2962 | if (pinfo2 & INSN2_MOD_GPR_MF) |
2963 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
2964 | if (pinfo2 & INSN2_MOD_SP) |
2965 | mask |= 1 << SP; | |
2966 | } | |
2967 | return mask; | |
2968 | } | |
2969 | ||
4c260379 RS |
2970 | /* Return the mask of core registers that IP reads. */ |
2971 | ||
2972 | static unsigned int | |
2973 | gpr_read_mask (const struct mips_cl_insn *ip) | |
2974 | { | |
2975 | unsigned long pinfo, pinfo2; | |
2976 | unsigned int mask; | |
2977 | ||
df58fc94 | 2978 | mask = gpr_mod_mask (ip); |
4c260379 RS |
2979 | pinfo = ip->insn_mo->pinfo; |
2980 | pinfo2 = ip->insn_mo->pinfo2; | |
2981 | if (mips_opts.mips16) | |
2982 | { | |
2983 | if (pinfo & MIPS16_INSN_READ_X) | |
2984 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2985 | if (pinfo & MIPS16_INSN_READ_Y) | |
2986 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2987 | if (pinfo & MIPS16_INSN_READ_T) | |
2988 | mask |= 1 << TREG; | |
2989 | if (pinfo & MIPS16_INSN_READ_SP) | |
2990 | mask |= 1 << SP; | |
2991 | if (pinfo & MIPS16_INSN_READ_31) | |
2992 | mask |= 1 << RA; | |
2993 | if (pinfo & MIPS16_INSN_READ_Z) | |
2994 | mask |= 1 << (mips16_to_32_reg_map | |
2995 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
2996 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2997 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
2998 | } | |
2999 | else | |
3000 | { | |
3001 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3002 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3003 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3004 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3005 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3006 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3007 | if (pinfo2 & INSN2_READ_GP) | |
3008 | mask |= 1 << GP; | |
3009 | if (pinfo2 & INSN2_READ_GPR_31) | |
3010 | mask |= 1 << RA; | |
4c260379 | 3011 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3012 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3013 | } |
2b0c8b40 MR |
3014 | if (mips_opts.micromips) |
3015 | { | |
3016 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3017 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3018 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3019 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3020 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3021 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3022 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3023 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3024 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3025 | { | |
3026 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3027 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3028 | } | |
3029 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3030 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3031 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3032 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3033 | } | |
fe35f09f RS |
3034 | /* Don't include register 0. */ |
3035 | return mask & ~1; | |
4c260379 RS |
3036 | } |
3037 | ||
3038 | /* Return the mask of core registers that IP writes. */ | |
3039 | ||
3040 | static unsigned int | |
3041 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3042 | { | |
3043 | unsigned long pinfo, pinfo2; | |
3044 | unsigned int mask; | |
3045 | ||
df58fc94 | 3046 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3047 | pinfo = ip->insn_mo->pinfo; |
3048 | pinfo2 = ip->insn_mo->pinfo2; | |
3049 | if (mips_opts.mips16) | |
3050 | { | |
3051 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3052 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3053 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3054 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3055 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3056 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3057 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3058 | mask |= 1 << TREG; | |
3059 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3060 | mask |= 1 << SP; | |
3061 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3062 | mask |= 1 << RA; | |
3063 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3064 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3065 | } | |
3066 | else | |
3067 | { | |
3068 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3069 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3070 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3071 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3072 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3073 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3074 | if (pinfo & INSN_WRITE_GPR_31) |
3075 | mask |= 1 << RA; | |
3076 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3077 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3078 | } |
2b0c8b40 MR |
3079 | if (mips_opts.micromips) |
3080 | { | |
3081 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3082 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3083 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3084 | { | |
3085 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3086 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3087 | } | |
3088 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3089 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3090 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3091 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3092 | } | |
fe35f09f RS |
3093 | /* Don't include register 0. */ |
3094 | return mask & ~1; | |
4c260379 RS |
3095 | } |
3096 | ||
3097 | /* Return the mask of floating-point registers that IP reads. */ | |
3098 | ||
3099 | static unsigned int | |
3100 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3101 | { | |
3102 | unsigned long pinfo, pinfo2; | |
3103 | unsigned int mask; | |
3104 | ||
3105 | mask = 0; | |
3106 | pinfo = ip->insn_mo->pinfo; | |
3107 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3108 | if (!mips_opts.mips16) |
df58fc94 RS |
3109 | { |
3110 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3111 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3112 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3113 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3114 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3115 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3116 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3117 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3118 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3119 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3120 | } |
3121 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3122 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3123 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3124 | mask |= mask << 1; | |
3125 | return mask; | |
3126 | } | |
3127 | ||
3128 | /* Return the mask of floating-point registers that IP writes. */ | |
3129 | ||
3130 | static unsigned int | |
3131 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3132 | { | |
3133 | unsigned long pinfo, pinfo2; | |
3134 | unsigned int mask; | |
3135 | ||
3136 | mask = 0; | |
3137 | pinfo = ip->insn_mo->pinfo; | |
3138 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3139 | if (!mips_opts.mips16) |
4c260379 RS |
3140 | { |
3141 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3142 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3143 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3144 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3145 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3146 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3147 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3148 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3149 | } |
3150 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3151 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3152 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3153 | mask |= mask << 1; | |
3154 | return mask; | |
3155 | } | |
3156 | ||
71400594 RS |
3157 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3158 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3159 | by VR4120 errata. */ | |
4d7206a2 | 3160 | |
71400594 RS |
3161 | static unsigned int |
3162 | classify_vr4120_insn (const char *name) | |
252b5132 | 3163 | { |
71400594 RS |
3164 | if (strncmp (name, "macc", 4) == 0) |
3165 | return FIX_VR4120_MACC; | |
3166 | if (strncmp (name, "dmacc", 5) == 0) | |
3167 | return FIX_VR4120_DMACC; | |
3168 | if (strncmp (name, "mult", 4) == 0) | |
3169 | return FIX_VR4120_MULT; | |
3170 | if (strncmp (name, "dmult", 5) == 0) | |
3171 | return FIX_VR4120_DMULT; | |
3172 | if (strstr (name, "div")) | |
3173 | return FIX_VR4120_DIV; | |
3174 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3175 | return FIX_VR4120_MTHILO; | |
3176 | return NUM_FIX_VR4120_CLASSES; | |
3177 | } | |
252b5132 | 3178 | |
ff239038 CM |
3179 | #define INSN_ERET 0x42000018 |
3180 | #define INSN_DERET 0x4200001f | |
3181 | ||
71400594 RS |
3182 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3183 | where INSN1 is the earlier instruction. Return the worst-case value | |
3184 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3185 | |
71400594 RS |
3186 | static unsigned int |
3187 | insns_between (const struct mips_cl_insn *insn1, | |
3188 | const struct mips_cl_insn *insn2) | |
3189 | { | |
3190 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3191 | unsigned int mask; |
71400594 RS |
3192 | |
3193 | /* This function needs to know which pinfo flags are set for INSN2 | |
3194 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3195 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3196 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3197 | pinfo1 = insn1->insn_mo->pinfo; |
3198 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3199 | |
4c260379 RS |
3200 | #define INSN2_USES_GPR(REG) \ |
3201 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3202 | |
3203 | /* For most targets, write-after-read dependencies on the HI and LO | |
3204 | registers must be separated by at least two instructions. */ | |
3205 | if (!hilo_interlocks) | |
252b5132 | 3206 | { |
71400594 RS |
3207 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3208 | return 2; | |
3209 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3210 | return 2; | |
3211 | } | |
3212 | ||
3213 | /* If we're working around r7000 errata, there must be two instructions | |
3214 | between an mfhi or mflo and any instruction that uses the result. */ | |
3215 | if (mips_7000_hilo_fix | |
df58fc94 | 3216 | && !mips_opts.micromips |
71400594 | 3217 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3218 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3219 | return 2; |
3220 | ||
ff239038 CM |
3221 | /* If we're working around 24K errata, one instruction is required |
3222 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3223 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3224 | { |
3225 | if (insn1->insn_opcode == INSN_ERET | |
3226 | || insn1->insn_opcode == INSN_DERET) | |
3227 | { | |
3228 | if (insn2 == NULL | |
3229 | || insn2->insn_opcode == INSN_ERET | |
3230 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3231 | || delayed_branch_p (insn2)) |
ff239038 CM |
3232 | return 1; |
3233 | } | |
3234 | } | |
3235 | ||
71400594 RS |
3236 | /* If working around VR4120 errata, check for combinations that need |
3237 | a single intervening instruction. */ | |
df58fc94 | 3238 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3239 | { |
3240 | unsigned int class1, class2; | |
252b5132 | 3241 | |
71400594 RS |
3242 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3243 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3244 | { |
71400594 RS |
3245 | if (insn2 == NULL) |
3246 | return 1; | |
3247 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3248 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3249 | return 1; | |
252b5132 | 3250 | } |
71400594 RS |
3251 | } |
3252 | ||
df58fc94 | 3253 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3254 | { |
3255 | /* Check for GPR or coprocessor load delays. All such delays | |
3256 | are on the RT register. */ | |
3257 | /* Itbl support may require additional care here. */ | |
3258 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3259 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3260 | { |
71400594 | 3261 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3262 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3263 | return 1; |
3264 | } | |
3265 | ||
3266 | /* Check for generic coprocessor hazards. | |
3267 | ||
3268 | This case is not handled very well. There is no special | |
3269 | knowledge of CP0 handling, and the coprocessors other than | |
3270 | the floating point unit are not distinguished at all. */ | |
3271 | /* Itbl support may require additional care here. FIXME! | |
3272 | Need to modify this to include knowledge about | |
3273 | user specified delays! */ | |
3274 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3275 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3276 | { | |
3277 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3278 | register. There must be a one instruction delay before INSN2 | |
3279 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3280 | mask = fpr_write_mask (insn1); |
3281 | if (mask != 0) | |
252b5132 | 3282 | { |
4c260379 | 3283 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3284 | return 1; |
252b5132 RH |
3285 | } |
3286 | else | |
3287 | { | |
71400594 RS |
3288 | /* Read-after-write dependencies on the control registers |
3289 | require a two-instruction gap. */ | |
3290 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3291 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3292 | return 2; | |
3293 | ||
3294 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3295 | also a coprocessor instruction, assume there must be | |
3296 | a one instruction gap. */ | |
3297 | if (pinfo2 & INSN_COP) | |
3298 | return 1; | |
252b5132 RH |
3299 | } |
3300 | } | |
6b76fefe | 3301 | |
71400594 RS |
3302 | /* Check for read-after-write dependencies on the coprocessor |
3303 | control registers in cases where INSN1 does not need a general | |
3304 | coprocessor delay. This means that INSN1 is a floating point | |
3305 | comparison instruction. */ | |
3306 | /* Itbl support may require additional care here. */ | |
3307 | else if (!cop_interlocks | |
3308 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3309 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3310 | return 1; | |
3311 | } | |
6b76fefe | 3312 | |
4c260379 | 3313 | #undef INSN2_USES_GPR |
6b76fefe | 3314 | |
71400594 RS |
3315 | return 0; |
3316 | } | |
6b76fefe | 3317 | |
7d8e00cf RS |
3318 | /* Return the number of nops that would be needed to work around the |
3319 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3320 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3321 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3322 | |
3323 | static int | |
932d1a1b | 3324 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3325 | const struct mips_cl_insn *insn) |
3326 | { | |
4c260379 RS |
3327 | int i, j; |
3328 | unsigned int mask; | |
7d8e00cf RS |
3329 | |
3330 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3331 | are not affected by the errata. */ | |
3332 | if (insn != 0 | |
3333 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3334 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3335 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3336 | return 0; | |
3337 | ||
3338 | /* Search for the first MFLO or MFHI. */ | |
3339 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3340 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3341 | { |
3342 | /* Extract the destination register. */ | |
4c260379 | 3343 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3344 | |
3345 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3346 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3347 | return 0; |
3348 | ||
3349 | /* ...or if any of the intervening instructions do. */ | |
3350 | for (j = 0; j < i; j++) | |
4c260379 | 3351 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3352 | return 0; |
3353 | ||
932d1a1b RS |
3354 | if (i >= ignore) |
3355 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3356 | } |
3357 | return 0; | |
3358 | } | |
3359 | ||
15be625d CM |
3360 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3361 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3362 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3363 | ||
3364 | /* Return the minimum alignment for this store instruction. */ | |
3365 | ||
3366 | static int | |
3367 | fix_24k_align_to (const struct mips_opcode *mo) | |
3368 | { | |
3369 | if (strcmp (mo->name, "sh") == 0) | |
3370 | return 2; | |
3371 | ||
3372 | if (strcmp (mo->name, "swc1") == 0 | |
3373 | || strcmp (mo->name, "swc2") == 0 | |
3374 | || strcmp (mo->name, "sw") == 0 | |
3375 | || strcmp (mo->name, "sc") == 0 | |
3376 | || strcmp (mo->name, "s.s") == 0) | |
3377 | return 4; | |
3378 | ||
3379 | if (strcmp (mo->name, "sdc1") == 0 | |
3380 | || strcmp (mo->name, "sdc2") == 0 | |
3381 | || strcmp (mo->name, "s.d") == 0) | |
3382 | return 8; | |
3383 | ||
3384 | /* sb, swl, swr */ | |
3385 | return 1; | |
3386 | } | |
3387 | ||
3388 | struct fix_24k_store_info | |
3389 | { | |
3390 | /* Immediate offset, if any, for this store instruction. */ | |
3391 | short off; | |
3392 | /* Alignment required by this store instruction. */ | |
3393 | int align_to; | |
3394 | /* True for register offsets. */ | |
3395 | int register_offset; | |
3396 | }; | |
3397 | ||
3398 | /* Comparison function used by qsort. */ | |
3399 | ||
3400 | static int | |
3401 | fix_24k_sort (const void *a, const void *b) | |
3402 | { | |
3403 | const struct fix_24k_store_info *pos1 = a; | |
3404 | const struct fix_24k_store_info *pos2 = b; | |
3405 | ||
3406 | return (pos1->off - pos2->off); | |
3407 | } | |
3408 | ||
3409 | /* INSN is a store instruction. Try to record the store information | |
3410 | in STINFO. Return false if the information isn't known. */ | |
3411 | ||
3412 | static bfd_boolean | |
3413 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3414 | const struct mips_cl_insn *insn) |
15be625d CM |
3415 | { |
3416 | /* The instruction must have a known offset. */ | |
3417 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3418 | return FALSE; | |
3419 | ||
3420 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3421 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3422 | return TRUE; | |
3423 | } | |
3424 | ||
932d1a1b RS |
3425 | /* Return the number of nops that would be needed to work around the 24k |
3426 | "lost data on stores during refill" errata if instruction INSN | |
3427 | immediately followed the 2 instructions described by HIST. | |
3428 | Ignore hazards that are contained within the first IGNORE | |
3429 | instructions of HIST. | |
3430 | ||
3431 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3432 | for the data cache refills and store data. The following describes | |
3433 | the scenario where the store data could be lost. | |
3434 | ||
3435 | * A data cache miss, due to either a load or a store, causing fill | |
3436 | data to be supplied by the memory subsystem | |
3437 | * The first three doublewords of fill data are returned and written | |
3438 | into the cache | |
3439 | * A sequence of four stores occurs in consecutive cycles around the | |
3440 | final doubleword of the fill: | |
3441 | * Store A | |
3442 | * Store B | |
3443 | * Store C | |
3444 | * Zero, One or more instructions | |
3445 | * Store D | |
3446 | ||
3447 | The four stores A-D must be to different doublewords of the line that | |
3448 | is being filled. The fourth instruction in the sequence above permits | |
3449 | the fill of the final doubleword to be transferred from the FSB into | |
3450 | the cache. In the sequence above, the stores may be either integer | |
3451 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3452 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3453 | different doublewords on the line. If the floating point unit is | |
3454 | running in 1:2 mode, it is not possible to create the sequence above | |
3455 | using only floating point store instructions. | |
15be625d CM |
3456 | |
3457 | In this case, the cache line being filled is incorrectly marked | |
3458 | invalid, thereby losing the data from any store to the line that | |
3459 | occurs between the original miss and the completion of the five | |
3460 | cycle sequence shown above. | |
3461 | ||
932d1a1b | 3462 | The workarounds are: |
15be625d | 3463 | |
932d1a1b RS |
3464 | * Run the data cache in write-through mode. |
3465 | * Insert a non-store instruction between | |
3466 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3467 | |
3468 | static int | |
932d1a1b | 3469 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3470 | const struct mips_cl_insn *insn) |
3471 | { | |
3472 | struct fix_24k_store_info pos[3]; | |
3473 | int align, i, base_offset; | |
3474 | ||
932d1a1b RS |
3475 | if (ignore >= 2) |
3476 | return 0; | |
3477 | ||
ab9794cf RS |
3478 | /* If the previous instruction wasn't a store, there's nothing to |
3479 | worry about. */ | |
15be625d CM |
3480 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3481 | return 0; | |
3482 | ||
ab9794cf RS |
3483 | /* If the instructions after the previous one are unknown, we have |
3484 | to assume the worst. */ | |
3485 | if (!insn) | |
15be625d CM |
3486 | return 1; |
3487 | ||
ab9794cf RS |
3488 | /* Check whether we are dealing with three consecutive stores. */ |
3489 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3490 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3491 | return 0; |
3492 | ||
3493 | /* If we don't know the relationship between the store addresses, | |
3494 | assume the worst. */ | |
ab9794cf | 3495 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3496 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3497 | return 1; | |
3498 | ||
3499 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3500 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3501 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3502 | return 1; | |
3503 | ||
3504 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3505 | ||
3506 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3507 | X bytes and such that the base register + X is known to be aligned | |
3508 | to align bytes. */ | |
3509 | ||
3510 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3511 | align = 8; | |
3512 | else | |
3513 | { | |
3514 | align = pos[0].align_to; | |
3515 | base_offset = pos[0].off; | |
3516 | for (i = 1; i < 3; i++) | |
3517 | if (align < pos[i].align_to) | |
3518 | { | |
3519 | align = pos[i].align_to; | |
3520 | base_offset = pos[i].off; | |
3521 | } | |
3522 | for (i = 0; i < 3; i++) | |
3523 | pos[i].off -= base_offset; | |
3524 | } | |
3525 | ||
3526 | pos[0].off &= ~align + 1; | |
3527 | pos[1].off &= ~align + 1; | |
3528 | pos[2].off &= ~align + 1; | |
3529 | ||
3530 | /* If any two stores write to the same chunk, they also write to the | |
3531 | same doubleword. The offsets are still sorted at this point. */ | |
3532 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3533 | return 0; | |
3534 | ||
3535 | /* A range of at least 9 bytes is needed for the stores to be in | |
3536 | non-overlapping doublewords. */ | |
3537 | if (pos[2].off - pos[0].off <= 8) | |
3538 | return 0; | |
3539 | ||
3540 | if (pos[2].off - pos[1].off >= 24 | |
3541 | || pos[1].off - pos[0].off >= 24 | |
3542 | || pos[2].off - pos[0].off >= 32) | |
3543 | return 0; | |
3544 | ||
3545 | return 1; | |
3546 | } | |
3547 | ||
71400594 | 3548 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3549 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3550 | where HIST[0] is the most recent instruction. Ignore hazards |
3551 | between INSN and the first IGNORE instructions in HIST. | |
3552 | ||
3553 | If INSN is null, return the worse-case number of nops for any | |
3554 | instruction. */ | |
bdaaa2e1 | 3555 | |
71400594 | 3556 | static int |
932d1a1b | 3557 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3558 | const struct mips_cl_insn *insn) |
3559 | { | |
3560 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3561 | |
71400594 | 3562 | nops = 0; |
932d1a1b | 3563 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3564 | { |
91d6fa6a | 3565 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3566 | if (tmp_nops > nops) |
3567 | nops = tmp_nops; | |
3568 | } | |
7d8e00cf | 3569 | |
df58fc94 | 3570 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3571 | { |
932d1a1b | 3572 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3573 | if (tmp_nops > nops) |
3574 | nops = tmp_nops; | |
3575 | } | |
3576 | ||
df58fc94 | 3577 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3578 | { |
932d1a1b | 3579 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3580 | if (tmp_nops > nops) |
3581 | nops = tmp_nops; | |
3582 | } | |
3583 | ||
71400594 RS |
3584 | return nops; |
3585 | } | |
252b5132 | 3586 | |
71400594 | 3587 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3588 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3589 | would be needed after the extended sequence, ignoring hazards |
3590 | in the first IGNORE instructions. */ | |
252b5132 | 3591 | |
71400594 | 3592 | static int |
932d1a1b RS |
3593 | nops_for_sequence (int num_insns, int ignore, |
3594 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3595 | { |
3596 | va_list args; | |
3597 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3598 | struct mips_cl_insn *cursor; | |
3599 | int nops; | |
3600 | ||
91d6fa6a | 3601 | va_start (args, hist); |
71400594 | 3602 | cursor = buffer + num_insns; |
91d6fa6a | 3603 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3604 | while (cursor > buffer) |
3605 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3606 | ||
932d1a1b | 3607 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3608 | va_end (args); |
3609 | return nops; | |
3610 | } | |
252b5132 | 3611 | |
71400594 RS |
3612 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3613 | worst-case delay for the branch target. */ | |
252b5132 | 3614 | |
71400594 | 3615 | static int |
932d1a1b | 3616 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3617 | const struct mips_cl_insn *insn) |
3618 | { | |
3619 | int nops, tmp_nops; | |
60b63b72 | 3620 | |
932d1a1b | 3621 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3622 | if (delayed_branch_p (insn)) |
71400594 | 3623 | { |
932d1a1b | 3624 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3625 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3626 | if (tmp_nops > nops) |
3627 | nops = tmp_nops; | |
3628 | } | |
11625dd8 | 3629 | else if (compact_branch_p (insn)) |
71400594 | 3630 | { |
932d1a1b | 3631 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3632 | if (tmp_nops > nops) |
3633 | nops = tmp_nops; | |
3634 | } | |
3635 | return nops; | |
3636 | } | |
3637 | ||
c67a084a NC |
3638 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3639 | ||
3640 | static void | |
3641 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3642 | { | |
df58fc94 | 3643 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3644 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3645 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3646 | } | |
3647 | ||
3648 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3649 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3650 | ||
3651 | static void | |
3652 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3653 | { | |
df58fc94 | 3654 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3655 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3656 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3657 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3658 | { | |
3659 | int sreg; | |
3660 | expressionS ep; | |
3661 | ||
3662 | if (! mips_opts.at) | |
3663 | return; | |
3664 | ||
df58fc94 | 3665 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3666 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3667 | return; | |
3668 | ||
3669 | ep.X_op = O_constant; | |
3670 | ep.X_add_number = 0xcfff0000; | |
3671 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3672 | ep.X_add_number = 0xffff; | |
3673 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3674 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3675 | } | |
3676 | } | |
3677 | ||
3678 | static void | |
3679 | fix_loongson2f (struct mips_cl_insn * ip) | |
3680 | { | |
3681 | if (mips_fix_loongson2f_nop) | |
3682 | fix_loongson2f_nop (ip); | |
3683 | ||
3684 | if (mips_fix_loongson2f_jump) | |
3685 | fix_loongson2f_jump (ip); | |
3686 | } | |
3687 | ||
a4e06468 RS |
3688 | /* IP is a branch that has a delay slot, and we need to fill it |
3689 | automatically. Return true if we can do that by swapping IP | |
3690 | with the previous instruction. */ | |
3691 | ||
3692 | static bfd_boolean | |
3693 | can_swap_branch_p (struct mips_cl_insn *ip) | |
3694 | { | |
2b0c8b40 | 3695 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3696 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3697 | ||
3698 | /* -O2 and above is required for this optimization. */ | |
3699 | if (mips_optimize < 2) | |
3700 | return FALSE; | |
3701 | ||
3702 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3703 | if (mips_opts.nomove) | |
3704 | return FALSE; | |
3705 | ||
3706 | /* We can't swap if the previous instruction's position is fixed. */ | |
3707 | if (history[0].fixed_p) | |
3708 | return FALSE; | |
3709 | ||
3710 | /* If the previous previous insn was in a .set noreorder, we can't | |
3711 | swap. Actually, the MIPS assembler will swap in this situation. | |
3712 | However, gcc configured -with-gnu-as will generate code like | |
3713 | ||
3714 | .set noreorder | |
3715 | lw $4,XXX | |
3716 | .set reorder | |
3717 | INSN | |
3718 | bne $4,$0,foo | |
3719 | ||
3720 | in which we can not swap the bne and INSN. If gcc is not configured | |
3721 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3722 | if (history[1].noreorder_p) | |
3723 | return FALSE; | |
3724 | ||
87333bb7 MR |
3725 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3726 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3727 | if (mips_opts.mips16 && history[0].fixp[0]) |
3728 | return FALSE; | |
3729 | ||
3730 | /* If the branch is itself the target of a branch, we can not swap. | |
3731 | We cheat on this; all we check for is whether there is a label on | |
3732 | this instruction. If there are any branches to anything other than | |
3733 | a label, users must use .set noreorder. */ | |
3734 | if (seg_info (now_seg)->label_list) | |
3735 | return FALSE; | |
3736 | ||
3737 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 3738 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
3739 | MIPS16 code, which uses variant frags for different purposes. */ |
3740 | if (!mips_opts.mips16 | |
a4e06468 RS |
3741 | && history[0].frag |
3742 | && history[0].frag->fr_type == rs_machine_dependent) | |
3743 | return FALSE; | |
3744 | ||
bcd530a7 RS |
3745 | /* We do not swap with instructions that cannot architecturally |
3746 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3747 | also refrain from swapping with a trap instruction, since it | |
3748 | complicates trap handlers to have the trap instruction be in | |
3749 | a delay slot. */ | |
a4e06468 | 3750 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3751 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3752 | return FALSE; |
3753 | ||
3754 | /* Check for conflicts between the branch and the instructions | |
3755 | before the candidate delay slot. */ | |
3756 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3757 | return FALSE; | |
3758 | ||
3759 | /* Check for conflicts between the swapped sequence and the | |
3760 | target of the branch. */ | |
3761 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3762 | return FALSE; | |
3763 | ||
3764 | /* If the branch reads a register that the previous | |
3765 | instruction sets, we can not swap. */ | |
3766 | gpr_read = gpr_read_mask (ip); | |
3767 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3768 | if (gpr_read & prev_gpr_write) | |
3769 | return FALSE; | |
3770 | ||
3771 | /* If the branch writes a register that the previous | |
3772 | instruction sets, we can not swap. */ | |
3773 | gpr_write = gpr_write_mask (ip); | |
3774 | if (gpr_write & prev_gpr_write) | |
3775 | return FALSE; | |
3776 | ||
3777 | /* If the branch writes a register that the previous | |
3778 | instruction reads, we can not swap. */ | |
3779 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3780 | if (gpr_write & prev_gpr_read) | |
3781 | return FALSE; | |
3782 | ||
3783 | /* If one instruction sets a condition code and the | |
3784 | other one uses a condition code, we can not swap. */ | |
3785 | pinfo = ip->insn_mo->pinfo; | |
3786 | if ((pinfo & INSN_READ_COND_CODE) | |
3787 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3788 | return FALSE; | |
3789 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3790 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3791 | return FALSE; | |
3792 | ||
3793 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3794 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3795 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3796 | return FALSE; | |
2b0c8b40 MR |
3797 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3798 | return FALSE; | |
a4e06468 | 3799 | |
df58fc94 RS |
3800 | /* If the previous instruction has an incorrect size for a fixed |
3801 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3802 | pinfo2 = ip->insn_mo->pinfo2; |
3803 | if (mips_opts.micromips | |
3804 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3805 | && insn_length (history) != 2) | |
3806 | return FALSE; | |
3807 | if (mips_opts.micromips | |
3808 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3809 | && insn_length (history) != 4) | |
3810 | return FALSE; | |
3811 | ||
a4e06468 RS |
3812 | return TRUE; |
3813 | } | |
3814 | ||
3815 | /* Decide how we should add IP to the instruction stream. */ | |
3816 | ||
3817 | static enum append_method | |
3818 | get_append_method (struct mips_cl_insn *ip) | |
3819 | { | |
3820 | unsigned long pinfo; | |
3821 | ||
3822 | /* The relaxed version of a macro sequence must be inherently | |
3823 | hazard-free. */ | |
3824 | if (mips_relax.sequence == 2) | |
3825 | return APPEND_ADD; | |
3826 | ||
3827 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3828 | if (mips_opts.noreorder) | |
3829 | return APPEND_ADD; | |
3830 | ||
3831 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3832 | if (delayed_branch_p (ip)) |
a4e06468 | 3833 | { |
11625dd8 | 3834 | if (!branch_likely_p (ip) && can_swap_branch_p (ip)) |
a4e06468 RS |
3835 | return APPEND_SWAP; |
3836 | ||
11625dd8 | 3837 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3838 | if (mips_opts.mips16 |
3839 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3840 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3841 | return APPEND_ADD_COMPACT; | |
3842 | ||
3843 | return APPEND_ADD_WITH_NOP; | |
3844 | } | |
3845 | ||
a4e06468 RS |
3846 | return APPEND_ADD; |
3847 | } | |
3848 | ||
ceb94aa5 RS |
3849 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3850 | Point IP->insn_mo to the new opcode's definition. */ | |
3851 | ||
3852 | static void | |
3853 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3854 | { | |
3855 | const struct mips_opcode *mo, *end; | |
3856 | ||
3857 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3858 | for (mo = ip->insn_mo; mo < end; mo++) | |
3859 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3860 | { | |
3861 | ip->insn_mo = mo; | |
3862 | return; | |
3863 | } | |
3864 | abort (); | |
3865 | } | |
3866 | ||
df58fc94 RS |
3867 | /* For microMIPS macros, we need to generate a local number label |
3868 | as the target of branches. */ | |
3869 | #define MICROMIPS_LABEL_CHAR '\037' | |
3870 | static unsigned long micromips_target_label; | |
3871 | static char micromips_target_name[32]; | |
3872 | ||
3873 | static char * | |
3874 | micromips_label_name (void) | |
3875 | { | |
3876 | char *p = micromips_target_name; | |
3877 | char symbol_name_temporary[24]; | |
3878 | unsigned long l; | |
3879 | int i; | |
3880 | ||
3881 | if (*p) | |
3882 | return p; | |
3883 | ||
3884 | i = 0; | |
3885 | l = micromips_target_label; | |
3886 | #ifdef LOCAL_LABEL_PREFIX | |
3887 | *p++ = LOCAL_LABEL_PREFIX; | |
3888 | #endif | |
3889 | *p++ = 'L'; | |
3890 | *p++ = MICROMIPS_LABEL_CHAR; | |
3891 | do | |
3892 | { | |
3893 | symbol_name_temporary[i++] = l % 10 + '0'; | |
3894 | l /= 10; | |
3895 | } | |
3896 | while (l != 0); | |
3897 | while (i > 0) | |
3898 | *p++ = symbol_name_temporary[--i]; | |
3899 | *p = '\0'; | |
3900 | ||
3901 | return micromips_target_name; | |
3902 | } | |
3903 | ||
3904 | static void | |
3905 | micromips_label_expr (expressionS *label_expr) | |
3906 | { | |
3907 | label_expr->X_op = O_symbol; | |
3908 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
3909 | label_expr->X_add_number = 0; | |
3910 | } | |
3911 | ||
3912 | static void | |
3913 | micromips_label_inc (void) | |
3914 | { | |
3915 | micromips_target_label++; | |
3916 | *micromips_target_name = '\0'; | |
3917 | } | |
3918 | ||
3919 | static void | |
3920 | micromips_add_label (void) | |
3921 | { | |
3922 | symbolS *s; | |
3923 | ||
3924 | s = colon (micromips_label_name ()); | |
3925 | micromips_label_inc (); | |
3926 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
3927 | if (IS_ELF) | |
3928 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
3929 | #else |
3930 | (void) s; | |
df58fc94 RS |
3931 | #endif |
3932 | } | |
3933 | ||
3934 | /* If assembling microMIPS code, then return the microMIPS reloc | |
3935 | corresponding to the requested one if any. Otherwise return | |
3936 | the reloc unchanged. */ | |
3937 | ||
3938 | static bfd_reloc_code_real_type | |
3939 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
3940 | { | |
3941 | static const bfd_reloc_code_real_type relocs[][2] = | |
3942 | { | |
3943 | /* Keep sorted incrementally by the left-hand key. */ | |
3944 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
3945 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
3946 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
3947 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
3948 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
3949 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
3950 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
3951 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
3952 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
3953 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
3954 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
3955 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
3956 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
3957 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
3958 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
3959 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
3960 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
3961 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
3962 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
3963 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
3964 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
3965 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
3966 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
3967 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
3968 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
3969 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
3970 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
3971 | }; | |
3972 | bfd_reloc_code_real_type r; | |
3973 | size_t i; | |
3974 | ||
3975 | if (!mips_opts.micromips) | |
3976 | return reloc; | |
3977 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
3978 | { | |
3979 | r = relocs[i][0]; | |
3980 | if (r > reloc) | |
3981 | return reloc; | |
3982 | if (r == reloc) | |
3983 | return relocs[i][1]; | |
3984 | } | |
3985 | return reloc; | |
3986 | } | |
3987 | ||
71400594 RS |
3988 | /* Output an instruction. IP is the instruction information. |
3989 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
3990 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
3991 | a macro expansion. */ | |
71400594 RS |
3992 | |
3993 | static void | |
3994 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 3995 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 3996 | { |
14fe068b | 3997 | unsigned long prev_pinfo2, pinfo; |
71400594 | 3998 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 3999 | enum append_method method; |
2309ddf2 | 4000 | bfd_boolean relax32; |
2b0c8b40 | 4001 | int branch_disp; |
71400594 | 4002 | |
2309ddf2 | 4003 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4004 | fix_loongson2f (ip); |
4005 | ||
df58fc94 | 4006 | mips_mark_labels (); |
71400594 | 4007 | |
738f4d98 | 4008 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4009 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4010 | |
df58fc94 | 4011 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4012 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4013 | |
4014 | if (mips_opts.micromips | |
4015 | && !expansionp | |
4016 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4017 | && micromips_insn_length (ip->insn_mo) != 2) | |
4018 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4019 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4020 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4021 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4022 | |
15be625d CM |
4023 | if (address_expr == NULL) |
4024 | ip->complete_p = 1; | |
4025 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
4026 | && address_expr->X_op == O_constant) | |
4027 | { | |
4028 | unsigned int tmp; | |
4029 | ||
4030 | ip->complete_p = 1; | |
4031 | switch (*reloc_type) | |
4032 | { | |
4033 | case BFD_RELOC_32: | |
4034 | ip->insn_opcode |= address_expr->X_add_number; | |
4035 | break; | |
4036 | ||
4037 | case BFD_RELOC_MIPS_HIGHEST: | |
4038 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
4039 | ip->insn_opcode |= tmp & 0xffff; | |
4040 | break; | |
4041 | ||
4042 | case BFD_RELOC_MIPS_HIGHER: | |
4043 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
4044 | ip->insn_opcode |= tmp & 0xffff; | |
4045 | break; | |
4046 | ||
4047 | case BFD_RELOC_HI16_S: | |
4048 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
4049 | ip->insn_opcode |= tmp & 0xffff; | |
4050 | break; | |
4051 | ||
4052 | case BFD_RELOC_HI16: | |
4053 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
4054 | break; | |
4055 | ||
4056 | case BFD_RELOC_UNUSED: | |
4057 | case BFD_RELOC_LO16: | |
4058 | case BFD_RELOC_MIPS_GOT_DISP: | |
4059 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
4060 | break; | |
4061 | ||
4062 | case BFD_RELOC_MIPS_JMP: | |
df58fc94 RS |
4063 | { |
4064 | int shift; | |
4065 | ||
4066 | shift = mips_opts.micromips ? 1 : 2; | |
4067 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4068 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4069 | (unsigned long) address_expr->X_add_number); | |
4070 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4071 | & 0x3ffffff); | |
4072 | ip->complete_p = 0; | |
4073 | } | |
15be625d CM |
4074 | break; |
4075 | ||
4076 | case BFD_RELOC_MIPS16_JMP: | |
4077 | if ((address_expr->X_add_number & 3) != 0) | |
4078 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4079 | (unsigned long) address_expr->X_add_number); | |
4080 | ip->insn_opcode |= | |
4081 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4082 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4083 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
4084 | ip->complete_p = 0; | |
4085 | break; | |
4086 | ||
4087 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4088 | { |
4089 | int shift; | |
4090 | ||
4091 | shift = mips_opts.micromips ? 1 : 2; | |
4092 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4093 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4094 | (unsigned long) address_expr->X_add_number); | |
4095 | if (!mips_relax_branch) | |
4096 | { | |
4097 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4098 | & ~((1 << (shift + 16)) - 1)) | |
4099 | as_bad (_("branch address range overflow (0x%lx)"), | |
4100 | (unsigned long) address_expr->X_add_number); | |
4101 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4102 | & 0xffff); | |
4103 | } | |
4104 | ip->complete_p = 0; | |
4105 | } | |
15be625d CM |
4106 | break; |
4107 | ||
4108 | default: | |
4109 | internalError (); | |
4110 | } | |
4111 | } | |
4112 | ||
71400594 RS |
4113 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4114 | { | |
4115 | /* There are a lot of optimizations we could do that we don't. | |
4116 | In particular, we do not, in general, reorder instructions. | |
4117 | If you use gcc with optimization, it will reorder | |
4118 | instructions and generally do much more optimization then we | |
4119 | do here; repeating all that work in the assembler would only | |
4120 | benefit hand written assembly code, and does not seem worth | |
4121 | it. */ | |
4122 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4123 | ? nops_for_insn (0, history, NULL) |
4124 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4125 | if (nops > 0) |
252b5132 RH |
4126 | { |
4127 | fragS *old_frag; | |
4128 | unsigned long old_frag_offset; | |
4129 | int i; | |
252b5132 RH |
4130 | |
4131 | old_frag = frag_now; | |
4132 | old_frag_offset = frag_now_fix (); | |
4133 | ||
4134 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4135 | add_fixed_insn (NOP_INSN); |
4136 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4137 | |
4138 | if (listing) | |
4139 | { | |
4140 | listing_prev_line (); | |
4141 | /* We may be at the start of a variant frag. In case we | |
4142 | are, make sure there is enough space for the frag | |
4143 | after the frags created by listing_prev_line. The | |
4144 | argument to frag_grow here must be at least as large | |
4145 | as the argument to all other calls to frag_grow in | |
4146 | this file. We don't have to worry about being in the | |
4147 | middle of a variant frag, because the variants insert | |
4148 | all needed nop instructions themselves. */ | |
4149 | frag_grow (40); | |
4150 | } | |
4151 | ||
404a8071 | 4152 | mips_move_labels (); |
252b5132 RH |
4153 | |
4154 | #ifndef NO_ECOFF_DEBUGGING | |
4155 | if (ECOFF_DEBUGGING) | |
4156 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4157 | #endif | |
4158 | } | |
71400594 RS |
4159 | } |
4160 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4161 | { | |
932d1a1b RS |
4162 | int nops; |
4163 | ||
4164 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4165 | ignoring hazards generated by the first prev_nop_frag_since | |
4166 | instructions. */ | |
4167 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4168 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4169 | |
71400594 RS |
4170 | /* Enforce NOPS as a minimum. */ |
4171 | if (nops > prev_nop_frag_required) | |
4172 | prev_nop_frag_required = nops; | |
252b5132 | 4173 | |
71400594 RS |
4174 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4175 | { | |
4176 | /* Settle for the current number of nops. Update the history | |
4177 | accordingly (for the benefit of any future .set reorder code). */ | |
4178 | prev_nop_frag = NULL; | |
4179 | insert_into_history (prev_nop_frag_since, | |
4180 | prev_nop_frag_holds, NOP_INSN); | |
4181 | } | |
4182 | else | |
4183 | { | |
4184 | /* Allow this instruction to replace one of the nops that was | |
4185 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4186 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4187 | prev_nop_frag_holds--; |
4188 | prev_nop_frag_since++; | |
252b5132 RH |
4189 | } |
4190 | } | |
4191 | ||
a4e06468 | 4192 | method = get_append_method (ip); |
2b0c8b40 | 4193 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4194 | |
58e2ea4d MR |
4195 | #ifdef OBJ_ELF |
4196 | /* The value passed to dwarf2_emit_insn is the distance between | |
4197 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4198 | should be recorded in the debug tables. This is normally the |
4199 | current address. | |
4200 | ||
df58fc94 RS |
4201 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4202 | addresses, so we use -1 for an address higher by one than the | |
4203 | current one. | |
e3a82c8e MR |
4204 | |
4205 | If the instruction produced is a branch that we will swap with | |
4206 | the preceding instruction, then we add the displacement by which | |
4207 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4208 | and for MIPS16/microMIPS code also prevents a debugger from |
4209 | placing a breakpoint in the middle of the branch (and corrupting | |
4210 | code if software breakpoints are used). */ | |
2b0c8b40 | 4211 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4212 | #endif |
4213 | ||
df58fc94 RS |
4214 | relax32 = (mips_relax_branch |
4215 | /* Don't try branch relaxation within .set nomacro, or within | |
4216 | .set noat if we use $at for PIC computations. If it turns | |
4217 | out that the branch was out-of-range, we'll get an error. */ | |
4218 | && !mips_opts.warn_about_macros | |
4219 | && (mips_opts.at || mips_pic == NO_PIC) | |
4220 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4221 | branches. */ | |
40209cad | 4222 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4223 | |
4224 | if (!HAVE_CODE_COMPRESSION | |
4225 | && address_expr | |
4226 | && relax32 | |
0b25d3e6 | 4227 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4228 | && delayed_branch_p (ip)) |
4a6a3df4 | 4229 | { |
895921c9 | 4230 | relaxed_branch = TRUE; |
1e915849 RS |
4231 | add_relaxed_insn (ip, (relaxed_branch_length |
4232 | (NULL, NULL, | |
11625dd8 RS |
4233 | uncond_branch_p (ip) ? -1 |
4234 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4235 | : 0)), 4, |
4236 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4237 | (AT, |
11625dd8 RS |
4238 | uncond_branch_p (ip), |
4239 | branch_likely_p (ip), | |
1e915849 RS |
4240 | pinfo & INSN_WRITE_GPR_31, |
4241 | 0), | |
4242 | address_expr->X_add_symbol, | |
4243 | address_expr->X_add_number); | |
4a6a3df4 AO |
4244 | *reloc_type = BFD_RELOC_UNUSED; |
4245 | } | |
df58fc94 RS |
4246 | else if (mips_opts.micromips |
4247 | && address_expr | |
4248 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4249 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4250 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4251 | /* Don't try branch relaxation when users specify | |
4252 | 16-bit/32-bit instructions. */ | |
4253 | && !forced_insn_length) | |
df58fc94 RS |
4254 | { |
4255 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4256 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4257 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4258 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4259 | int al = pinfo & INSN_WRITE_GPR_31; |
4260 | int length32; | |
4261 | ||
4262 | gas_assert (address_expr != NULL); | |
4263 | gas_assert (!mips_relax.sequence); | |
4264 | ||
2b0c8b40 | 4265 | relaxed_branch = TRUE; |
df58fc94 RS |
4266 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4267 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4268 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4269 | relax32, 0, 0), | |
df58fc94 RS |
4270 | address_expr->X_add_symbol, |
4271 | address_expr->X_add_number); | |
4272 | *reloc_type = BFD_RELOC_UNUSED; | |
4273 | } | |
4274 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4275 | { |
4276 | /* We need to set up a variant frag. */ | |
df58fc94 | 4277 | gas_assert (address_expr != NULL); |
1e915849 RS |
4278 | add_relaxed_insn (ip, 4, 0, |
4279 | RELAX_MIPS16_ENCODE | |
4280 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4281 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4282 | delayed_branch_p (&history[0]), |
1e915849 RS |
4283 | history[0].mips16_absolute_jump_p), |
4284 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4285 | } |
252b5132 RH |
4286 | else if (mips_opts.mips16 |
4287 | && ! ip->use_extend | |
f6688943 | 4288 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 4289 | { |
11625dd8 | 4290 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4291 | /* Make sure there is enough room to swap this instruction with |
4292 | a following jump instruction. */ | |
4293 | frag_grow (6); | |
1e915849 | 4294 | add_fixed_insn (ip); |
252b5132 RH |
4295 | } |
4296 | else | |
4297 | { | |
4298 | if (mips_opts.mips16 | |
4299 | && mips_opts.noreorder | |
11625dd8 | 4300 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4301 | as_warn (_("extended instruction in delay slot")); |
4302 | ||
4d7206a2 RS |
4303 | if (mips_relax.sequence) |
4304 | { | |
4305 | /* If we've reached the end of this frag, turn it into a variant | |
4306 | frag and record the information for the instructions we've | |
4307 | written so far. */ | |
4308 | if (frag_room () < 4) | |
4309 | relax_close_frag (); | |
df58fc94 | 4310 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4311 | } |
4312 | ||
584892a6 | 4313 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4314 | { |
4315 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4316 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4317 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4318 | mips_macro_warning.insns[0]++; | |
4319 | } | |
584892a6 | 4320 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4321 | { |
4322 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4323 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4324 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4325 | mips_macro_warning.insns[1]++; | |
4326 | } | |
584892a6 | 4327 | |
1e915849 RS |
4328 | if (mips_opts.mips16) |
4329 | { | |
4330 | ip->fixed_p = 1; | |
4331 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4332 | } | |
4333 | add_fixed_insn (ip); | |
252b5132 RH |
4334 | } |
4335 | ||
9fe77896 | 4336 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4337 | { |
df58fc94 | 4338 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4339 | reloc_howto_type *howto0; |
9fe77896 RS |
4340 | reloc_howto_type *howto; |
4341 | int i; | |
34ce925e | 4342 | |
df58fc94 RS |
4343 | /* Perform any necessary conversion to microMIPS relocations |
4344 | and find out how many relocations there actually are. */ | |
4345 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4346 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4347 | ||
9fe77896 RS |
4348 | /* In a compound relocation, it is the final (outermost) |
4349 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4350 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4351 | ||
9fe77896 RS |
4352 | if (howto == NULL) |
4353 | { | |
4354 | /* To reproduce this failure try assembling gas/testsuites/ | |
4355 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4356 | assembler. */ | |
df58fc94 RS |
4357 | as_bad (_("Unsupported MIPS relocation number %d"), |
4358 | final_type[i - 1]); | |
9fe77896 RS |
4359 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4360 | } | |
2309ddf2 MR |
4361 | |
4362 | if (i > 1) | |
4363 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4364 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4365 | bfd_get_reloc_size (howto), | |
4366 | address_expr, | |
2309ddf2 MR |
4367 | howto0 && howto0->pc_relative, |
4368 | final_type[0]); | |
9fe77896 RS |
4369 | |
4370 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4371 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4372 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4373 | ||
4374 | /* These relocations can have an addend that won't fit in | |
4375 | 4 octets for 64bit assembly. */ | |
4376 | if (HAVE_64BIT_GPRS | |
4377 | && ! howto->partial_inplace | |
4378 | && (reloc_type[0] == BFD_RELOC_16 | |
4379 | || reloc_type[0] == BFD_RELOC_32 | |
4380 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4381 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4382 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4383 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4384 | || reloc_type[0] == BFD_RELOC_64 | |
4385 | || reloc_type[0] == BFD_RELOC_CTOR | |
4386 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4387 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4388 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4389 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4390 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4391 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4392 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4393 | || hi16_reloc_p (reloc_type[0]) | |
4394 | || lo16_reloc_p (reloc_type[0]))) | |
4395 | ip->fixp[0]->fx_no_overflow = 1; | |
4396 | ||
4397 | if (mips_relax.sequence) | |
4398 | { | |
4399 | if (mips_relax.first_fixup == 0) | |
4400 | mips_relax.first_fixup = ip->fixp[0]; | |
4401 | } | |
4402 | else if (reloc_needs_lo_p (*reloc_type)) | |
4403 | { | |
4404 | struct mips_hi_fixup *hi_fixup; | |
4405 | ||
4406 | /* Reuse the last entry if it already has a matching %lo. */ | |
4407 | hi_fixup = mips_hi_fixup_list; | |
4408 | if (hi_fixup == 0 | |
4409 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4410 | { |
9fe77896 RS |
4411 | hi_fixup = ((struct mips_hi_fixup *) |
4412 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4413 | hi_fixup->next = mips_hi_fixup_list; | |
4414 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4415 | } |
9fe77896 RS |
4416 | hi_fixup->fixp = ip->fixp[0]; |
4417 | hi_fixup->seg = now_seg; | |
4418 | } | |
252b5132 | 4419 | |
9fe77896 RS |
4420 | /* Add fixups for the second and third relocations, if given. |
4421 | Note that the ABI allows the second relocation to be | |
4422 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4423 | moment we only use RSS_UNDEF, but we could add support | |
4424 | for the others if it ever becomes necessary. */ | |
4425 | for (i = 1; i < 3; i++) | |
4426 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4427 | { | |
4428 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4429 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4430 | FALSE, final_type[i]); |
f6688943 | 4431 | |
9fe77896 RS |
4432 | /* Use fx_tcbit to mark compound relocs. */ |
4433 | ip->fixp[0]->fx_tcbit = 1; | |
4434 | ip->fixp[i]->fx_tcbit = 1; | |
4435 | } | |
252b5132 | 4436 | } |
1e915849 | 4437 | install_insn (ip); |
252b5132 RH |
4438 | |
4439 | /* Update the register mask information. */ | |
4c260379 RS |
4440 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4441 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4442 | |
a4e06468 | 4443 | switch (method) |
252b5132 | 4444 | { |
a4e06468 RS |
4445 | case APPEND_ADD: |
4446 | insert_into_history (0, 1, ip); | |
4447 | break; | |
4448 | ||
4449 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4450 | { |
4451 | struct mips_cl_insn *nop; | |
4452 | ||
4453 | insert_into_history (0, 1, ip); | |
4454 | nop = get_delay_slot_nop (ip); | |
4455 | add_fixed_insn (nop); | |
4456 | insert_into_history (0, 1, nop); | |
4457 | if (mips_relax.sequence) | |
4458 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4459 | } | |
a4e06468 RS |
4460 | break; |
4461 | ||
4462 | case APPEND_ADD_COMPACT: | |
4463 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4464 | gas_assert (mips_opts.mips16); | |
4465 | ip->insn_opcode |= 0x0080; | |
4466 | find_altered_mips16_opcode (ip); | |
4467 | install_insn (ip); | |
4468 | insert_into_history (0, 1, ip); | |
4469 | break; | |
4470 | ||
4471 | case APPEND_SWAP: | |
4472 | { | |
4473 | struct mips_cl_insn delay = history[0]; | |
4474 | if (mips_opts.mips16) | |
4475 | { | |
4476 | know (delay.frag == ip->frag); | |
4477 | move_insn (ip, delay.frag, delay.where); | |
4478 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4479 | } | |
4480 | else if (relaxed_branch) | |
4481 | { | |
4482 | /* Add the delay slot instruction to the end of the | |
4483 | current frag and shrink the fixed part of the | |
4484 | original frag. If the branch occupies the tail of | |
4485 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4486 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4487 | if (delay.frag == ip->frag) |
2b0c8b40 | 4488 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4489 | add_fixed_insn (&delay); |
4490 | } | |
4491 | else | |
4492 | { | |
2b0c8b40 MR |
4493 | move_insn (&delay, ip->frag, |
4494 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4495 | move_insn (ip, history[0].frag, history[0].where); |
4496 | } | |
4497 | history[0] = *ip; | |
4498 | delay.fixed_p = 1; | |
4499 | insert_into_history (0, 1, &delay); | |
4500 | } | |
4501 | break; | |
252b5132 RH |
4502 | } |
4503 | ||
13408f1e | 4504 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4505 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4506 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
13408f1e RS |
4507 | mips_no_prev_insn (); |
4508 | ||
df58fc94 RS |
4509 | /* We need to emit a label at the end of branch-likely macros. */ |
4510 | if (emit_branch_likely_macro) | |
4511 | { | |
4512 | emit_branch_likely_macro = FALSE; | |
4513 | micromips_add_label (); | |
4514 | } | |
4515 | ||
252b5132 RH |
4516 | /* We just output an insn, so the next one doesn't have a label. */ |
4517 | mips_clear_insn_labels (); | |
252b5132 RH |
4518 | } |
4519 | ||
7d10b47d | 4520 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
4521 | |
4522 | static void | |
7d10b47d | 4523 | mips_no_prev_insn (void) |
252b5132 | 4524 | { |
7d10b47d RS |
4525 | prev_nop_frag = NULL; |
4526 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4527 | mips_clear_insn_labels (); |
4528 | } | |
4529 | ||
7d10b47d RS |
4530 | /* This function must be called before we emit something other than |
4531 | instructions. It is like mips_no_prev_insn except that it inserts | |
4532 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4533 | |
7d10b47d RS |
4534 | void |
4535 | mips_emit_delays (void) | |
252b5132 RH |
4536 | { |
4537 | if (! mips_opts.noreorder) | |
4538 | { | |
932d1a1b | 4539 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4540 | if (nops > 0) |
4541 | { | |
7d10b47d RS |
4542 | while (nops-- > 0) |
4543 | add_fixed_insn (NOP_INSN); | |
4544 | mips_move_labels (); | |
4545 | } | |
4546 | } | |
4547 | mips_no_prev_insn (); | |
4548 | } | |
4549 | ||
4550 | /* Start a (possibly nested) noreorder block. */ | |
4551 | ||
4552 | static void | |
4553 | start_noreorder (void) | |
4554 | { | |
4555 | if (mips_opts.noreorder == 0) | |
4556 | { | |
4557 | unsigned int i; | |
4558 | int nops; | |
4559 | ||
4560 | /* None of the instructions before the .set noreorder can be moved. */ | |
4561 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4562 | history[i].fixed_p = 1; | |
4563 | ||
4564 | /* Insert any nops that might be needed between the .set noreorder | |
4565 | block and the previous instructions. We will later remove any | |
4566 | nops that turn out not to be needed. */ | |
932d1a1b | 4567 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4568 | if (nops > 0) |
4569 | { | |
4570 | if (mips_optimize != 0) | |
252b5132 RH |
4571 | { |
4572 | /* Record the frag which holds the nop instructions, so | |
4573 | that we can remove them if we don't need them. */ | |
df58fc94 | 4574 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4575 | prev_nop_frag = frag_now; |
4576 | prev_nop_frag_holds = nops; | |
4577 | prev_nop_frag_required = 0; | |
4578 | prev_nop_frag_since = 0; | |
4579 | } | |
4580 | ||
4581 | for (; nops > 0; --nops) | |
1e915849 | 4582 | add_fixed_insn (NOP_INSN); |
252b5132 | 4583 | |
7d10b47d RS |
4584 | /* Move on to a new frag, so that it is safe to simply |
4585 | decrease the size of prev_nop_frag. */ | |
4586 | frag_wane (frag_now); | |
4587 | frag_new (0); | |
404a8071 | 4588 | mips_move_labels (); |
252b5132 | 4589 | } |
df58fc94 | 4590 | mips_mark_labels (); |
7d10b47d | 4591 | mips_clear_insn_labels (); |
252b5132 | 4592 | } |
7d10b47d RS |
4593 | mips_opts.noreorder++; |
4594 | mips_any_noreorder = 1; | |
4595 | } | |
252b5132 | 4596 | |
7d10b47d | 4597 | /* End a nested noreorder block. */ |
252b5132 | 4598 | |
7d10b47d RS |
4599 | static void |
4600 | end_noreorder (void) | |
4601 | { | |
4602 | mips_opts.noreorder--; | |
4603 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4604 | { | |
4605 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4606 | handling nop insertion the .set reorder way. */ | |
4607 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4608 | * NOP_INSN_SIZE); |
7d10b47d RS |
4609 | insert_into_history (prev_nop_frag_since, |
4610 | prev_nop_frag_required, NOP_INSN); | |
4611 | prev_nop_frag = NULL; | |
4612 | } | |
252b5132 RH |
4613 | } |
4614 | ||
584892a6 RS |
4615 | /* Set up global variables for the start of a new macro. */ |
4616 | ||
4617 | static void | |
4618 | macro_start (void) | |
4619 | { | |
4620 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4621 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4622 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4623 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4624 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4625 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4626 | switch (history[0].insn_mo->pinfo2 |
4627 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4628 | { | |
4629 | case INSN2_BRANCH_DELAY_32BIT: | |
4630 | mips_macro_warning.delay_slot_length = 4; | |
4631 | break; | |
4632 | case INSN2_BRANCH_DELAY_16BIT: | |
4633 | mips_macro_warning.delay_slot_length = 2; | |
4634 | break; | |
4635 | default: | |
4636 | mips_macro_warning.delay_slot_length = 0; | |
4637 | break; | |
4638 | } | |
4639 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4640 | } |
4641 | ||
df58fc94 RS |
4642 | /* Given that a macro is longer than one instruction or of the wrong size, |
4643 | return the appropriate warning for it. Return null if no warning is | |
4644 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4645 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4646 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4647 | |
4648 | static const char * | |
4649 | macro_warning (relax_substateT subtype) | |
4650 | { | |
4651 | if (subtype & RELAX_DELAY_SLOT) | |
4652 | return _("Macro instruction expanded into multiple instructions" | |
4653 | " in a branch delay slot"); | |
4654 | else if (subtype & RELAX_NOMACRO) | |
4655 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4656 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4657 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4658 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4659 | ? _("Macro instruction expanded into a wrong size instruction" | |
4660 | " in a 16-bit branch delay slot") | |
4661 | : _("Macro instruction expanded into a wrong size instruction" | |
4662 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4663 | else |
4664 | return 0; | |
4665 | } | |
4666 | ||
4667 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4668 | ||
4669 | static void | |
4670 | macro_end (void) | |
4671 | { | |
df58fc94 RS |
4672 | /* Relaxation warning flags. */ |
4673 | relax_substateT subtype = 0; | |
4674 | ||
4675 | /* Check delay slot size requirements. */ | |
4676 | if (mips_macro_warning.delay_slot_length == 2) | |
4677 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4678 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4679 | { |
df58fc94 RS |
4680 | if (mips_macro_warning.delay_slot_length |
4681 | != mips_macro_warning.first_insn_sizes[0]) | |
4682 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4683 | if (mips_macro_warning.delay_slot_length | |
4684 | != mips_macro_warning.first_insn_sizes[1]) | |
4685 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4686 | } | |
584892a6 | 4687 | |
df58fc94 RS |
4688 | /* Check instruction count requirements. */ |
4689 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4690 | { | |
4691 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4692 | subtype |= RELAX_SECOND_LONGER; |
4693 | if (mips_opts.warn_about_macros) | |
4694 | subtype |= RELAX_NOMACRO; | |
4695 | if (mips_macro_warning.delay_slot_p) | |
4696 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4697 | } |
584892a6 | 4698 | |
df58fc94 RS |
4699 | /* If both alternatives fail to fill a delay slot correctly, |
4700 | emit the warning now. */ | |
4701 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4702 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4703 | { | |
4704 | relax_substateT s; | |
4705 | const char *msg; | |
4706 | ||
4707 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4708 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4709 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4710 | msg = macro_warning (s); | |
4711 | if (msg != NULL) | |
4712 | as_warn ("%s", msg); | |
4713 | subtype &= ~s; | |
4714 | } | |
4715 | ||
4716 | /* If both implementations are longer than 1 instruction, then emit the | |
4717 | warning now. */ | |
4718 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4719 | { | |
4720 | relax_substateT s; | |
4721 | const char *msg; | |
4722 | ||
4723 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4724 | msg = macro_warning (s); | |
4725 | if (msg != NULL) | |
4726 | as_warn ("%s", msg); | |
4727 | subtype &= ~s; | |
584892a6 | 4728 | } |
df58fc94 RS |
4729 | |
4730 | /* If any flags still set, then one implementation might need a warning | |
4731 | and the other either will need one of a different kind or none at all. | |
4732 | Pass any remaining flags over to relaxation. */ | |
4733 | if (mips_macro_warning.first_frag != NULL) | |
4734 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4735 | } |
4736 | ||
df58fc94 RS |
4737 | /* Instruction operand formats used in macros that vary between |
4738 | standard MIPS and microMIPS code. */ | |
4739 | ||
4740 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4741 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4742 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4743 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4744 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4745 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4746 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4747 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4748 | ||
4749 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4750 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4751 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4752 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4753 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4754 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4755 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4756 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4757 | ||
6e1304d8 RS |
4758 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4759 | The first argument in *ARGS will be either the code for a single | |
4760 | relocation or -1 followed by the three codes that make up a | |
4761 | composite relocation. */ | |
4762 | ||
4763 | static void | |
4764 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4765 | { | |
4766 | int i, next; | |
4767 | ||
4768 | next = va_arg (*args, int); | |
4769 | if (next >= 0) | |
4770 | r[0] = (bfd_reloc_code_real_type) next; | |
4771 | else | |
4772 | for (i = 0; i < 3; i++) | |
4773 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4774 | } | |
4775 | ||
252b5132 RH |
4776 | /* Build an instruction created by a macro expansion. This is passed |
4777 | a pointer to the count of instructions created so far, an | |
4778 | expression, the name of the instruction to build, an operand format | |
4779 | string, and corresponding arguments. */ | |
4780 | ||
252b5132 | 4781 | static void |
67c0d1eb | 4782 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4783 | { |
df58fc94 | 4784 | const struct mips_opcode *mo = NULL; |
f6688943 | 4785 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4786 | const struct mips_opcode *amo; |
4787 | struct hash_control *hash; | |
4788 | struct mips_cl_insn insn; | |
252b5132 | 4789 | va_list args; |
252b5132 | 4790 | |
252b5132 | 4791 | va_start (args, fmt); |
252b5132 | 4792 | |
252b5132 RH |
4793 | if (mips_opts.mips16) |
4794 | { | |
03ea81db | 4795 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4796 | va_end (args); |
4797 | return; | |
4798 | } | |
4799 | ||
f6688943 TS |
4800 | r[0] = BFD_RELOC_UNUSED; |
4801 | r[1] = BFD_RELOC_UNUSED; | |
4802 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4803 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4804 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4805 | gas_assert (amo); | |
4806 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4807 | |
df58fc94 | 4808 | do |
8b082fb1 TS |
4809 | { |
4810 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4811 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4812 | We try to match an instruction that fulfils the branch delay | |
4813 | slot instruction length requirement (if any) of the previous | |
4814 | instruction. While doing this we record the first instruction | |
4815 | seen that matches all the other conditions and use it anyway | |
4816 | if the requirement cannot be met; we will issue an appropriate | |
4817 | warning later on. */ | |
4818 | if (strcmp (fmt, amo->args) == 0 | |
4819 | && amo->pinfo != INSN_MACRO | |
4820 | && is_opcode_valid (amo) | |
4821 | && is_size_valid (amo)) | |
4822 | { | |
4823 | if (is_delay_slot_valid (amo)) | |
4824 | { | |
4825 | mo = amo; | |
4826 | break; | |
4827 | } | |
4828 | else if (!mo) | |
4829 | mo = amo; | |
4830 | } | |
8b082fb1 | 4831 | |
df58fc94 RS |
4832 | ++amo; |
4833 | gas_assert (amo->name); | |
252b5132 | 4834 | } |
df58fc94 | 4835 | while (strcmp (name, amo->name) == 0); |
252b5132 | 4836 | |
df58fc94 | 4837 | gas_assert (mo); |
1e915849 | 4838 | create_insn (&insn, mo); |
252b5132 RH |
4839 | for (;;) |
4840 | { | |
4841 | switch (*fmt++) | |
4842 | { | |
4843 | case '\0': | |
4844 | break; | |
4845 | ||
4846 | case ',': | |
4847 | case '(': | |
4848 | case ')': | |
4849 | continue; | |
4850 | ||
5f74bc13 CD |
4851 | case '+': |
4852 | switch (*fmt++) | |
4853 | { | |
4854 | case 'A': | |
4855 | case 'E': | |
df58fc94 RS |
4856 | INSERT_OPERAND (mips_opts.micromips, |
4857 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4858 | continue; |
4859 | ||
4860 | case 'B': | |
4861 | case 'F': | |
4862 | /* Note that in the macro case, these arguments are already | |
4863 | in MSB form. (When handling the instruction in the | |
4864 | non-macro case, these arguments are sizes from which | |
4865 | MSB values must be calculated.) */ | |
df58fc94 RS |
4866 | INSERT_OPERAND (mips_opts.micromips, |
4867 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4868 | continue; |
4869 | ||
4870 | case 'C': | |
4871 | case 'G': | |
4872 | case 'H': | |
4873 | /* Note that in the macro case, these arguments are already | |
4874 | in MSBD form. (When handling the instruction in the | |
4875 | non-macro case, these arguments are sizes from which | |
4876 | MSBD values must be calculated.) */ | |
df58fc94 RS |
4877 | INSERT_OPERAND (mips_opts.micromips, |
4878 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
4879 | continue; |
4880 | ||
dd3cbb7e | 4881 | case 'Q': |
df58fc94 RS |
4882 | gas_assert (!mips_opts.micromips); |
4883 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
4884 | continue; |
4885 | ||
5f74bc13 CD |
4886 | default: |
4887 | internalError (); | |
4888 | } | |
4889 | continue; | |
4890 | ||
8b082fb1 | 4891 | case '2': |
df58fc94 RS |
4892 | gas_assert (!mips_opts.micromips); |
4893 | INSERT_OPERAND (0, BP, insn, va_arg (args, int)); | |
8b082fb1 TS |
4894 | continue; |
4895 | ||
df58fc94 RS |
4896 | case 'n': |
4897 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
4898 | case 't': |
4899 | case 'w': | |
4900 | case 'E': | |
df58fc94 | 4901 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
4902 | continue; |
4903 | ||
4904 | case 'c': | |
df58fc94 RS |
4905 | gas_assert (!mips_opts.micromips); |
4906 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
4907 | continue; |
4908 | ||
252b5132 | 4909 | case 'W': |
df58fc94 RS |
4910 | gas_assert (!mips_opts.micromips); |
4911 | case 'T': | |
4912 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
4913 | continue; |
4914 | ||
252b5132 | 4915 | case 'G': |
df58fc94 RS |
4916 | if (mips_opts.micromips) |
4917 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
4918 | else | |
4919 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
4920 | continue; | |
4921 | ||
af7ee8bf | 4922 | case 'K': |
df58fc94 RS |
4923 | gas_assert (!mips_opts.micromips); |
4924 | case 'd': | |
4925 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
4926 | continue; |
4927 | ||
4372b673 | 4928 | case 'U': |
df58fc94 | 4929 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
4930 | { |
4931 | int tmp = va_arg (args, int); | |
4932 | ||
df58fc94 RS |
4933 | INSERT_OPERAND (0, RT, insn, tmp); |
4934 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 4935 | } |
df58fc94 | 4936 | continue; |
4372b673 | 4937 | |
252b5132 RH |
4938 | case 'V': |
4939 | case 'S': | |
df58fc94 RS |
4940 | gas_assert (!mips_opts.micromips); |
4941 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
4942 | continue; |
4943 | ||
4944 | case 'z': | |
4945 | continue; | |
4946 | ||
4947 | case '<': | |
df58fc94 RS |
4948 | INSERT_OPERAND (mips_opts.micromips, |
4949 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
4950 | continue; |
4951 | ||
4952 | case 'D': | |
df58fc94 RS |
4953 | gas_assert (!mips_opts.micromips); |
4954 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
4955 | continue; |
4956 | ||
4957 | case 'B': | |
df58fc94 RS |
4958 | gas_assert (!mips_opts.micromips); |
4959 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
4960 | continue; |
4961 | ||
4372b673 | 4962 | case 'J': |
df58fc94 RS |
4963 | gas_assert (!mips_opts.micromips); |
4964 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
4965 | continue; |
4966 | ||
252b5132 | 4967 | case 'q': |
df58fc94 RS |
4968 | gas_assert (!mips_opts.micromips); |
4969 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
4970 | continue; |
4971 | ||
4972 | case 'b': | |
4973 | case 's': | |
4974 | case 'r': | |
4975 | case 'v': | |
df58fc94 | 4976 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
4977 | continue; |
4978 | ||
4979 | case 'i': | |
4980 | case 'j': | |
6e1304d8 | 4981 | macro_read_relocs (&args, r); |
9c2799c2 | 4982 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
4983 | || *r == BFD_RELOC_MIPS_HIGHER |
4984 | || *r == BFD_RELOC_HI16_S | |
4985 | || *r == BFD_RELOC_LO16 | |
4986 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
4987 | continue; | |
4988 | ||
4989 | case 'o': | |
4990 | macro_read_relocs (&args, r); | |
252b5132 RH |
4991 | continue; |
4992 | ||
4993 | case 'u': | |
6e1304d8 | 4994 | macro_read_relocs (&args, r); |
9c2799c2 | 4995 | gas_assert (ep != NULL |
90ecf173 MR |
4996 | && (ep->X_op == O_constant |
4997 | || (ep->X_op == O_symbol | |
4998 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
4999 | || *r == BFD_RELOC_HI16_S | |
5000 | || *r == BFD_RELOC_HI16 | |
5001 | || *r == BFD_RELOC_GPREL16 | |
5002 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5003 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5004 | continue; |
5005 | ||
5006 | case 'p': | |
9c2799c2 | 5007 | gas_assert (ep != NULL); |
bad36eac | 5008 | |
252b5132 RH |
5009 | /* |
5010 | * This allows macro() to pass an immediate expression for | |
5011 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5012 | * |
5013 | * We don't allow branch relaxation for these branches, as | |
5014 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5015 | */ |
5016 | if (ep->X_op == O_constant) | |
5017 | { | |
df58fc94 RS |
5018 | /* For microMIPS we always use relocations for branches. |
5019 | So we should not resolve immediate values. */ | |
5020 | gas_assert (!mips_opts.micromips); | |
5021 | ||
bad36eac DJ |
5022 | if ((ep->X_add_number & 3) != 0) |
5023 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5024 | (unsigned long) ep->X_add_number); | |
5025 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5026 | as_bad (_("branch address range overflow (0x%lx)"), | |
5027 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5028 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5029 | ep = NULL; | |
5030 | } | |
5031 | else | |
0b25d3e6 | 5032 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5033 | continue; |
5034 | ||
5035 | case 'a': | |
9c2799c2 | 5036 | gas_assert (ep != NULL); |
f6688943 | 5037 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5038 | continue; |
5039 | ||
5040 | case 'C': | |
df58fc94 RS |
5041 | gas_assert (!mips_opts.micromips); |
5042 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5043 | continue; |
5044 | ||
d43b4baf | 5045 | case 'k': |
df58fc94 RS |
5046 | INSERT_OPERAND (mips_opts.micromips, |
5047 | CACHE, insn, va_arg (args, unsigned long)); | |
5048 | continue; | |
5049 | ||
5050 | case '|': | |
5051 | gas_assert (mips_opts.micromips); | |
5052 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5053 | continue; | |
5054 | ||
5055 | case '.': | |
5056 | gas_assert (mips_opts.micromips); | |
5057 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5058 | continue; | |
5059 | ||
dec0624d MR |
5060 | case '\\': |
5061 | INSERT_OPERAND (mips_opts.micromips, | |
5062 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5063 | continue; | |
5064 | ||
df58fc94 | 5065 | case '~': |
dec0624d MR |
5066 | INSERT_OPERAND (mips_opts.micromips, |
5067 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5068 | continue; |
5069 | ||
5070 | case 'N': | |
5071 | gas_assert (mips_opts.micromips); | |
5072 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5073 | continue; | |
5074 | ||
5075 | case 'm': /* Opcode extension character. */ | |
5076 | gas_assert (mips_opts.micromips); | |
5077 | switch (*fmt++) | |
5078 | { | |
5079 | case 'j': | |
5080 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5081 | break; | |
5082 | ||
5083 | case 'p': | |
5084 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5085 | break; | |
5086 | ||
5087 | case 'F': | |
5088 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5089 | break; | |
5090 | ||
5091 | default: | |
5092 | internalError (); | |
5093 | } | |
d43b4baf TS |
5094 | continue; |
5095 | ||
252b5132 RH |
5096 | default: |
5097 | internalError (); | |
5098 | } | |
5099 | break; | |
5100 | } | |
5101 | va_end (args); | |
9c2799c2 | 5102 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5103 | |
df58fc94 | 5104 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5105 | } |
5106 | ||
5107 | static void | |
67c0d1eb | 5108 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5109 | va_list *args) |
252b5132 | 5110 | { |
1e915849 | 5111 | struct mips_opcode *mo; |
252b5132 | 5112 | struct mips_cl_insn insn; |
f6688943 TS |
5113 | bfd_reloc_code_real_type r[3] |
5114 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5115 | |
1e915849 | 5116 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5117 | gas_assert (mo); |
5118 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5119 | |
1e915849 | 5120 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5121 | { |
1e915849 | 5122 | ++mo; |
9c2799c2 NC |
5123 | gas_assert (mo->name); |
5124 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5125 | } |
5126 | ||
1e915849 | 5127 | create_insn (&insn, mo); |
252b5132 RH |
5128 | for (;;) |
5129 | { | |
5130 | int c; | |
5131 | ||
5132 | c = *fmt++; | |
5133 | switch (c) | |
5134 | { | |
5135 | case '\0': | |
5136 | break; | |
5137 | ||
5138 | case ',': | |
5139 | case '(': | |
5140 | case ')': | |
5141 | continue; | |
5142 | ||
5143 | case 'y': | |
5144 | case 'w': | |
03ea81db | 5145 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5146 | continue; |
5147 | ||
5148 | case 'x': | |
5149 | case 'v': | |
03ea81db | 5150 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5151 | continue; |
5152 | ||
5153 | case 'z': | |
03ea81db | 5154 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5155 | continue; |
5156 | ||
5157 | case 'Z': | |
03ea81db | 5158 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5159 | continue; |
5160 | ||
5161 | case '0': | |
5162 | case 'S': | |
5163 | case 'P': | |
5164 | case 'R': | |
5165 | continue; | |
5166 | ||
5167 | case 'X': | |
03ea81db | 5168 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5169 | continue; |
5170 | ||
5171 | case 'Y': | |
5172 | { | |
5173 | int regno; | |
5174 | ||
03ea81db | 5175 | regno = va_arg (*args, int); |
252b5132 | 5176 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5177 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5178 | } |
5179 | continue; | |
5180 | ||
5181 | case '<': | |
5182 | case '>': | |
5183 | case '4': | |
5184 | case '5': | |
5185 | case 'H': | |
5186 | case 'W': | |
5187 | case 'D': | |
5188 | case 'j': | |
5189 | case '8': | |
5190 | case 'V': | |
5191 | case 'C': | |
5192 | case 'U': | |
5193 | case 'k': | |
5194 | case 'K': | |
5195 | case 'p': | |
5196 | case 'q': | |
5197 | { | |
9c2799c2 | 5198 | gas_assert (ep != NULL); |
252b5132 RH |
5199 | |
5200 | if (ep->X_op != O_constant) | |
874e8986 | 5201 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
5202 | else |
5203 | { | |
b34976b6 AM |
5204 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
5205 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 5206 | &insn.extend); |
252b5132 | 5207 | ep = NULL; |
f6688943 | 5208 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5209 | } |
5210 | } | |
5211 | continue; | |
5212 | ||
5213 | case '6': | |
03ea81db | 5214 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5215 | continue; |
5216 | } | |
5217 | ||
5218 | break; | |
5219 | } | |
5220 | ||
9c2799c2 | 5221 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5222 | |
df58fc94 | 5223 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5224 | } |
5225 | ||
2051e8c4 MR |
5226 | /* |
5227 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5228 | * higher bits unset. | |
5229 | */ | |
9f872bbe | 5230 | static void |
2051e8c4 MR |
5231 | normalize_constant_expr (expressionS *ex) |
5232 | { | |
9ee2a2d4 | 5233 | if (ex->X_op == O_constant |
2051e8c4 MR |
5234 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5235 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5236 | - 0x80000000); | |
5237 | } | |
5238 | ||
5239 | /* | |
5240 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5241 | * all higher bits unset. | |
5242 | */ | |
5243 | static void | |
5244 | normalize_address_expr (expressionS *ex) | |
5245 | { | |
5246 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5247 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5248 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5249 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5250 | - 0x80000000); | |
5251 | } | |
5252 | ||
438c16b8 TS |
5253 | /* |
5254 | * Generate a "jalr" instruction with a relocation hint to the called | |
5255 | * function. This occurs in NewABI PIC code. | |
5256 | */ | |
5257 | static void | |
df58fc94 | 5258 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5259 | { |
df58fc94 RS |
5260 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5261 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5262 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5263 | const char *jalr; | |
685736be | 5264 | char *f = NULL; |
b34976b6 | 5265 | |
1180b5a4 | 5266 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5267 | { |
cc3d92a5 | 5268 | frag_grow (8); |
f21f8242 AO |
5269 | f = frag_more (0); |
5270 | } | |
2906b037 | 5271 | if (mips_opts.micromips) |
df58fc94 RS |
5272 | { |
5273 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
5274 | if (MIPS_JALR_HINT_P (ep)) | |
5275 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); | |
5276 | else | |
5277 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5278 | } | |
2906b037 MR |
5279 | else |
5280 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5281 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5282 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5283 | } |
5284 | ||
252b5132 RH |
5285 | /* |
5286 | * Generate a "lui" instruction. | |
5287 | */ | |
5288 | static void | |
67c0d1eb | 5289 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5290 | { |
9c2799c2 | 5291 | gas_assert (! mips_opts.mips16); |
252b5132 | 5292 | |
df58fc94 | 5293 | if (ep->X_op != O_constant) |
252b5132 | 5294 | { |
9c2799c2 | 5295 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5296 | /* _gp_disp is a special case, used from s_cpload. |
5297 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5298 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5299 | || (! HAVE_NEWABI |
aa6975fb ILT |
5300 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5301 | || (! mips_in_shared | |
bbe506e8 TS |
5302 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5303 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5304 | } |
5305 | ||
df58fc94 | 5306 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5307 | } |
5308 | ||
885add95 CD |
5309 | /* Generate a sequence of instructions to do a load or store from a constant |
5310 | offset off of a base register (breg) into/from a target register (treg), | |
5311 | using AT if necessary. */ | |
5312 | static void | |
67c0d1eb RS |
5313 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5314 | int treg, int breg, int dbl) | |
885add95 | 5315 | { |
9c2799c2 | 5316 | gas_assert (ep->X_op == O_constant); |
885add95 | 5317 | |
256ab948 | 5318 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5319 | if (!dbl) |
5320 | normalize_constant_expr (ep); | |
256ab948 | 5321 | |
67c1ffbe | 5322 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5323 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5324 | as_warn (_("operand overflow")); |
5325 | ||
5326 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5327 | { | |
5328 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5329 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5330 | } |
5331 | else | |
5332 | { | |
5333 | /* 32-bit offset, need multiple instructions and AT, like: | |
5334 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5335 | addu $tempreg,$tempreg,$breg | |
5336 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5337 | to handle the complete offset. */ | |
67c0d1eb RS |
5338 | macro_build_lui (ep, AT); |
5339 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5340 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5341 | |
741fe287 | 5342 | if (!mips_opts.at) |
8fc2e39e | 5343 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5344 | } |
5345 | } | |
5346 | ||
252b5132 RH |
5347 | /* set_at() |
5348 | * Generates code to set the $at register to true (one) | |
5349 | * if reg is less than the immediate expression. | |
5350 | */ | |
5351 | static void | |
67c0d1eb | 5352 | set_at (int reg, int unsignedp) |
252b5132 RH |
5353 | { |
5354 | if (imm_expr.X_op == O_constant | |
5355 | && imm_expr.X_add_number >= -0x8000 | |
5356 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5357 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5358 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5359 | else |
5360 | { | |
67c0d1eb RS |
5361 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5362 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5363 | } |
5364 | } | |
5365 | ||
5366 | /* Warn if an expression is not a constant. */ | |
5367 | ||
5368 | static void | |
17a2f251 | 5369 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5370 | { |
5371 | if (ex->X_op == O_big) | |
5372 | as_bad (_("unsupported large constant")); | |
5373 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5374 | as_bad (_("Instruction %s requires absolute expression"), |
5375 | ip->insn_mo->name); | |
13757d0c | 5376 | |
9ee2a2d4 MR |
5377 | if (HAVE_32BIT_GPRS) |
5378 | normalize_constant_expr (ex); | |
252b5132 RH |
5379 | } |
5380 | ||
5381 | /* Count the leading zeroes by performing a binary chop. This is a | |
5382 | bulky bit of source, but performance is a LOT better for the | |
5383 | majority of values than a simple loop to count the bits: | |
5384 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5385 | if ((v) & (1 << (31 - lcnt))) | |
5386 | break; | |
5387 | However it is not code size friendly, and the gain will drop a bit | |
5388 | on certain cached systems. | |
5389 | */ | |
5390 | #define COUNT_TOP_ZEROES(v) \ | |
5391 | (((v) & ~0xffff) == 0 \ | |
5392 | ? ((v) & ~0xff) == 0 \ | |
5393 | ? ((v) & ~0xf) == 0 \ | |
5394 | ? ((v) & ~0x3) == 0 \ | |
5395 | ? ((v) & ~0x1) == 0 \ | |
5396 | ? !(v) \ | |
5397 | ? 32 \ | |
5398 | : 31 \ | |
5399 | : 30 \ | |
5400 | : ((v) & ~0x7) == 0 \ | |
5401 | ? 29 \ | |
5402 | : 28 \ | |
5403 | : ((v) & ~0x3f) == 0 \ | |
5404 | ? ((v) & ~0x1f) == 0 \ | |
5405 | ? 27 \ | |
5406 | : 26 \ | |
5407 | : ((v) & ~0x7f) == 0 \ | |
5408 | ? 25 \ | |
5409 | : 24 \ | |
5410 | : ((v) & ~0xfff) == 0 \ | |
5411 | ? ((v) & ~0x3ff) == 0 \ | |
5412 | ? ((v) & ~0x1ff) == 0 \ | |
5413 | ? 23 \ | |
5414 | : 22 \ | |
5415 | : ((v) & ~0x7ff) == 0 \ | |
5416 | ? 21 \ | |
5417 | : 20 \ | |
5418 | : ((v) & ~0x3fff) == 0 \ | |
5419 | ? ((v) & ~0x1fff) == 0 \ | |
5420 | ? 19 \ | |
5421 | : 18 \ | |
5422 | : ((v) & ~0x7fff) == 0 \ | |
5423 | ? 17 \ | |
5424 | : 16 \ | |
5425 | : ((v) & ~0xffffff) == 0 \ | |
5426 | ? ((v) & ~0xfffff) == 0 \ | |
5427 | ? ((v) & ~0x3ffff) == 0 \ | |
5428 | ? ((v) & ~0x1ffff) == 0 \ | |
5429 | ? 15 \ | |
5430 | : 14 \ | |
5431 | : ((v) & ~0x7ffff) == 0 \ | |
5432 | ? 13 \ | |
5433 | : 12 \ | |
5434 | : ((v) & ~0x3fffff) == 0 \ | |
5435 | ? ((v) & ~0x1fffff) == 0 \ | |
5436 | ? 11 \ | |
5437 | : 10 \ | |
5438 | : ((v) & ~0x7fffff) == 0 \ | |
5439 | ? 9 \ | |
5440 | : 8 \ | |
5441 | : ((v) & ~0xfffffff) == 0 \ | |
5442 | ? ((v) & ~0x3ffffff) == 0 \ | |
5443 | ? ((v) & ~0x1ffffff) == 0 \ | |
5444 | ? 7 \ | |
5445 | : 6 \ | |
5446 | : ((v) & ~0x7ffffff) == 0 \ | |
5447 | ? 5 \ | |
5448 | : 4 \ | |
5449 | : ((v) & ~0x3fffffff) == 0 \ | |
5450 | ? ((v) & ~0x1fffffff) == 0 \ | |
5451 | ? 3 \ | |
5452 | : 2 \ | |
5453 | : ((v) & ~0x7fffffff) == 0 \ | |
5454 | ? 1 \ | |
5455 | : 0) | |
5456 | ||
5457 | /* load_register() | |
67c1ffbe | 5458 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5459 | * an absolute expression value into a register. |
5460 | */ | |
5461 | static void | |
67c0d1eb | 5462 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5463 | { |
5464 | int freg; | |
5465 | expressionS hi32, lo32; | |
5466 | ||
5467 | if (ep->X_op != O_big) | |
5468 | { | |
9c2799c2 | 5469 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5470 | |
5471 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5472 | if (!dbl) |
5473 | normalize_constant_expr (ep); | |
256ab948 TS |
5474 | |
5475 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5476 | { |
5477 | /* We can handle 16 bit signed values with an addiu to | |
5478 | $zero. No need to ever use daddiu here, since $zero and | |
5479 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5480 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5481 | return; |
5482 | } | |
5483 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5484 | { | |
5485 | /* We can handle 16 bit unsigned values with an ori to | |
5486 | $zero. */ | |
67c0d1eb | 5487 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5488 | return; |
5489 | } | |
256ab948 | 5490 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5491 | { |
5492 | /* 32 bit values require an lui. */ | |
df58fc94 | 5493 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5494 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5495 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5496 | return; |
5497 | } | |
5498 | } | |
5499 | ||
5500 | /* The value is larger than 32 bits. */ | |
5501 | ||
2051e8c4 | 5502 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5503 | { |
55e08f71 NC |
5504 | char value[32]; |
5505 | ||
5506 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5507 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5508 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5509 | return; |
5510 | } | |
5511 | ||
5512 | if (ep->X_op != O_big) | |
5513 | { | |
5514 | hi32 = *ep; | |
5515 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5516 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5517 | hi32.X_add_number &= 0xffffffff; | |
5518 | lo32 = *ep; | |
5519 | lo32.X_add_number &= 0xffffffff; | |
5520 | } | |
5521 | else | |
5522 | { | |
9c2799c2 | 5523 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5524 | if (ep->X_add_number == 3) |
5525 | generic_bignum[3] = 0; | |
5526 | else if (ep->X_add_number > 4) | |
5527 | as_bad (_("Number larger than 64 bits")); | |
5528 | lo32.X_op = O_constant; | |
5529 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5530 | hi32.X_op = O_constant; | |
5531 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5532 | } | |
5533 | ||
5534 | if (hi32.X_add_number == 0) | |
5535 | freg = 0; | |
5536 | else | |
5537 | { | |
5538 | int shift, bit; | |
5539 | unsigned long hi, lo; | |
5540 | ||
956cd1d6 | 5541 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5542 | { |
5543 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5544 | { | |
67c0d1eb | 5545 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5546 | return; |
5547 | } | |
5548 | if (lo32.X_add_number & 0x80000000) | |
5549 | { | |
df58fc94 | 5550 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5551 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5552 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5553 | return; |
5554 | } | |
5555 | } | |
252b5132 RH |
5556 | |
5557 | /* Check for 16bit shifted constant. We know that hi32 is | |
5558 | non-zero, so start the mask on the first bit of the hi32 | |
5559 | value. */ | |
5560 | shift = 17; | |
5561 | do | |
beae10d5 KH |
5562 | { |
5563 | unsigned long himask, lomask; | |
5564 | ||
5565 | if (shift < 32) | |
5566 | { | |
5567 | himask = 0xffff >> (32 - shift); | |
5568 | lomask = (0xffff << shift) & 0xffffffff; | |
5569 | } | |
5570 | else | |
5571 | { | |
5572 | himask = 0xffff << (shift - 32); | |
5573 | lomask = 0; | |
5574 | } | |
5575 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5576 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5577 | { | |
5578 | expressionS tmp; | |
5579 | ||
5580 | tmp.X_op = O_constant; | |
5581 | if (shift < 32) | |
5582 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5583 | | (lo32.X_add_number >> shift)); | |
5584 | else | |
5585 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5586 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5587 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5588 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5589 | return; |
5590 | } | |
f9419b05 | 5591 | ++shift; |
beae10d5 KH |
5592 | } |
5593 | while (shift <= (64 - 16)); | |
252b5132 RH |
5594 | |
5595 | /* Find the bit number of the lowest one bit, and store the | |
5596 | shifted value in hi/lo. */ | |
5597 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5598 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5599 | if (lo != 0) | |
5600 | { | |
5601 | bit = 0; | |
5602 | while ((lo & 1) == 0) | |
5603 | { | |
5604 | lo >>= 1; | |
5605 | ++bit; | |
5606 | } | |
5607 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5608 | hi >>= bit; | |
5609 | } | |
5610 | else | |
5611 | { | |
5612 | bit = 32; | |
5613 | while ((hi & 1) == 0) | |
5614 | { | |
5615 | hi >>= 1; | |
5616 | ++bit; | |
5617 | } | |
5618 | lo = hi; | |
5619 | hi = 0; | |
5620 | } | |
5621 | ||
5622 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5623 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5624 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5625 | { |
5626 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5627 | if (shift != 0) |
beae10d5 | 5628 | { |
252b5132 RH |
5629 | expressionS tmp; |
5630 | ||
5631 | /* This instruction will set the register to be all | |
5632 | ones. */ | |
beae10d5 KH |
5633 | tmp.X_op = O_constant; |
5634 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5635 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5636 | if (bit != 0) |
5637 | { | |
5638 | bit += shift; | |
df58fc94 | 5639 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5640 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5641 | } |
df58fc94 | 5642 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5643 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5644 | return; |
5645 | } | |
5646 | } | |
252b5132 RH |
5647 | |
5648 | /* Sign extend hi32 before calling load_register, because we can | |
5649 | generally get better code when we load a sign extended value. */ | |
5650 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5651 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5652 | load_register (reg, &hi32, 0); |
252b5132 RH |
5653 | freg = reg; |
5654 | } | |
5655 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5656 | { | |
5657 | if (freg != 0) | |
5658 | { | |
df58fc94 | 5659 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5660 | freg = reg; |
5661 | } | |
5662 | } | |
5663 | else | |
5664 | { | |
5665 | expressionS mid16; | |
5666 | ||
956cd1d6 | 5667 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5668 | { |
df58fc94 RS |
5669 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5670 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5671 | return; |
5672 | } | |
252b5132 RH |
5673 | |
5674 | if (freg != 0) | |
5675 | { | |
df58fc94 | 5676 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5677 | freg = reg; |
5678 | } | |
5679 | mid16 = lo32; | |
5680 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5681 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5682 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5683 | freg = reg; |
5684 | } | |
5685 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5686 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5687 | } |
5688 | ||
269137b2 TS |
5689 | static inline void |
5690 | load_delay_nop (void) | |
5691 | { | |
5692 | if (!gpr_interlocks) | |
5693 | macro_build (NULL, "nop", ""); | |
5694 | } | |
5695 | ||
252b5132 RH |
5696 | /* Load an address into a register. */ |
5697 | ||
5698 | static void | |
67c0d1eb | 5699 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5700 | { |
252b5132 RH |
5701 | if (ep->X_op != O_constant |
5702 | && ep->X_op != O_symbol) | |
5703 | { | |
5704 | as_bad (_("expression too complex")); | |
5705 | ep->X_op = O_constant; | |
5706 | } | |
5707 | ||
5708 | if (ep->X_op == O_constant) | |
5709 | { | |
67c0d1eb | 5710 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5711 | return; |
5712 | } | |
5713 | ||
5714 | if (mips_pic == NO_PIC) | |
5715 | { | |
5716 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5717 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5718 | Otherwise we want |
5719 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5720 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5721 | If we have an addend, we always use the latter form. |
76b3015f | 5722 | |
d6bc6245 TS |
5723 | With 64bit address space and a usable $at we want |
5724 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5725 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5726 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5727 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5728 | dsll32 $reg,0 | |
3a482fd5 | 5729 | daddu $reg,$reg,$at |
76b3015f | 5730 | |
c03099e6 | 5731 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5732 | on superscalar processors. |
5733 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5734 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5735 | dsll $reg,16 | |
5736 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5737 | dsll $reg,16 | |
5738 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5739 | |
5740 | For GP relative symbols in 64bit address space we can use | |
5741 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5742 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5743 | { |
6caf9ef4 TS |
5744 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5745 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5746 | { | |
5747 | relax_start (ep->X_add_symbol); | |
5748 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5749 | mips_gp_register, BFD_RELOC_GPREL16); | |
5750 | relax_switch (); | |
5751 | } | |
d6bc6245 | 5752 | |
741fe287 | 5753 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5754 | { |
df58fc94 RS |
5755 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5756 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5757 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5758 | BFD_RELOC_MIPS_HIGHER); | |
5759 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5760 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5761 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5762 | *used_at = 1; |
5763 | } | |
5764 | else | |
5765 | { | |
df58fc94 | 5766 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5767 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5768 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5769 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5770 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5771 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5772 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5773 | } |
6caf9ef4 TS |
5774 | |
5775 | if (mips_relax.sequence) | |
5776 | relax_end (); | |
d6bc6245 | 5777 | } |
252b5132 RH |
5778 | else |
5779 | { | |
d6bc6245 | 5780 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5781 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5782 | { |
4d7206a2 | 5783 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5784 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5785 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5786 | relax_switch (); |
d6bc6245 | 5787 | } |
67c0d1eb RS |
5788 | macro_build_lui (ep, reg); |
5789 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5790 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5791 | if (mips_relax.sequence) |
5792 | relax_end (); | |
d6bc6245 | 5793 | } |
252b5132 | 5794 | } |
0a44bf69 | 5795 | else if (!mips_big_got) |
252b5132 RH |
5796 | { |
5797 | expressionS ex; | |
5798 | ||
5799 | /* If this is a reference to an external symbol, we want | |
5800 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5801 | Otherwise we want | |
5802 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5803 | nop | |
5804 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5805 | If there is a constant, it must be added in after. |
5806 | ||
ed6fb7bd | 5807 | If we have NewABI, we want |
f5040a92 AO |
5808 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5809 | unless we're referencing a global symbol with a non-zero | |
5810 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5811 | if (HAVE_NEWABI) |
5812 | { | |
f5040a92 AO |
5813 | if (ep->X_add_number) |
5814 | { | |
4d7206a2 | 5815 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5816 | ep->X_add_number = 0; |
4d7206a2 | 5817 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5818 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5819 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5820 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5821 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5822 | ex.X_op = O_constant; | |
67c0d1eb | 5823 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5824 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5825 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5826 | relax_switch (); |
f5040a92 | 5827 | } |
67c0d1eb | 5828 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5829 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5830 | if (mips_relax.sequence) |
5831 | relax_end (); | |
ed6fb7bd SC |
5832 | } |
5833 | else | |
5834 | { | |
f5040a92 AO |
5835 | ex.X_add_number = ep->X_add_number; |
5836 | ep->X_add_number = 0; | |
67c0d1eb RS |
5837 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5838 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5839 | load_delay_nop (); |
4d7206a2 RS |
5840 | relax_start (ep->X_add_symbol); |
5841 | relax_switch (); | |
67c0d1eb | 5842 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5843 | BFD_RELOC_LO16); |
4d7206a2 | 5844 | relax_end (); |
ed6fb7bd | 5845 | |
f5040a92 AO |
5846 | if (ex.X_add_number != 0) |
5847 | { | |
5848 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5849 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5850 | ex.X_op = O_constant; | |
67c0d1eb | 5851 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5852 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5853 | } |
252b5132 RH |
5854 | } |
5855 | } | |
0a44bf69 | 5856 | else if (mips_big_got) |
252b5132 RH |
5857 | { |
5858 | expressionS ex; | |
252b5132 RH |
5859 | |
5860 | /* This is the large GOT case. If this is a reference to an | |
5861 | external symbol, we want | |
5862 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5863 | addu $reg,$reg,$gp | |
5864 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
5865 | |
5866 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
5867 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
5868 | nop | |
5869 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 5870 | If there is a constant, it must be added in after. |
f5040a92 AO |
5871 | |
5872 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
5873 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
5874 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 5875 | */ |
438c16b8 TS |
5876 | if (HAVE_NEWABI) |
5877 | { | |
4d7206a2 | 5878 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5879 | ep->X_add_number = 0; |
4d7206a2 | 5880 | relax_start (ep->X_add_symbol); |
df58fc94 | 5881 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5882 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5883 | reg, reg, mips_gp_register); | |
5884 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5885 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
5886 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5887 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5888 | else if (ex.X_add_number) | |
5889 | { | |
5890 | ex.X_op = O_constant; | |
67c0d1eb RS |
5891 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5892 | BFD_RELOC_LO16); | |
f5040a92 AO |
5893 | } |
5894 | ||
5895 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 5896 | relax_switch (); |
67c0d1eb | 5897 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5898 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
5899 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5900 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 5901 | relax_end (); |
438c16b8 | 5902 | } |
252b5132 | 5903 | else |
438c16b8 | 5904 | { |
f5040a92 AO |
5905 | ex.X_add_number = ep->X_add_number; |
5906 | ep->X_add_number = 0; | |
4d7206a2 | 5907 | relax_start (ep->X_add_symbol); |
df58fc94 | 5908 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5909 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5910 | reg, reg, mips_gp_register); | |
5911 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5912 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
5913 | relax_switch (); |
5914 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
5915 | { |
5916 | /* We need a nop before loading from $gp. This special | |
5917 | check is required because the lui which starts the main | |
5918 | instruction stream does not refer to $gp, and so will not | |
5919 | insert the nop which may be required. */ | |
67c0d1eb | 5920 | macro_build (NULL, "nop", ""); |
438c16b8 | 5921 | } |
67c0d1eb | 5922 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5923 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 5924 | load_delay_nop (); |
67c0d1eb | 5925 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5926 | BFD_RELOC_LO16); |
4d7206a2 | 5927 | relax_end (); |
438c16b8 | 5928 | |
f5040a92 AO |
5929 | if (ex.X_add_number != 0) |
5930 | { | |
5931 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5932 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5933 | ex.X_op = O_constant; | |
67c0d1eb RS |
5934 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5935 | BFD_RELOC_LO16); | |
f5040a92 | 5936 | } |
252b5132 RH |
5937 | } |
5938 | } | |
252b5132 RH |
5939 | else |
5940 | abort (); | |
8fc2e39e | 5941 | |
741fe287 | 5942 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 5943 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
5944 | } |
5945 | ||
ea1fb5dc RS |
5946 | /* Move the contents of register SOURCE into register DEST. */ |
5947 | ||
5948 | static void | |
67c0d1eb | 5949 | move_register (int dest, int source) |
ea1fb5dc | 5950 | { |
df58fc94 RS |
5951 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
5952 | instruction specifically requires a 32-bit one. */ | |
5953 | if (mips_opts.micromips | |
5954 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
7951ca42 | 5955 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
5956 | else |
5957 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
5958 | dest, source, 0); | |
ea1fb5dc RS |
5959 | } |
5960 | ||
4d7206a2 | 5961 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
5962 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
5963 | The two alternatives are: | |
4d7206a2 RS |
5964 | |
5965 | Global symbol Local sybmol | |
5966 | ------------- ------------ | |
5967 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
5968 | ... ... | |
5969 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
5970 | ||
5971 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
5972 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
5973 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
5974 | |
5975 | static void | |
67c0d1eb | 5976 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5977 | { |
5978 | expressionS global; | |
5979 | ||
5980 | global = *local; | |
5981 | global.X_add_number = 0; | |
5982 | ||
5983 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
5984 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5985 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 5986 | relax_switch (); |
67c0d1eb RS |
5987 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5988 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
5989 | relax_end (); |
5990 | } | |
5991 | ||
5992 | static void | |
67c0d1eb | 5993 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5994 | { |
5995 | expressionS global; | |
5996 | ||
5997 | global.X_op = O_constant; | |
5998 | global.X_op_symbol = NULL; | |
5999 | global.X_add_symbol = NULL; | |
6000 | global.X_add_number = local->X_add_number; | |
6001 | ||
6002 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6003 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6004 | dest, dest, BFD_RELOC_LO16); |
6005 | relax_switch (); | |
67c0d1eb | 6006 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6007 | relax_end (); |
6008 | } | |
6009 | ||
f6a22291 MR |
6010 | static void |
6011 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6012 | { | |
6013 | expressionS global; | |
6014 | int hold_mips_optimize; | |
6015 | ||
6016 | global.X_op = O_constant; | |
6017 | global.X_op_symbol = NULL; | |
6018 | global.X_add_symbol = NULL; | |
6019 | global.X_add_number = local->X_add_number; | |
6020 | ||
6021 | relax_start (local->X_add_symbol); | |
6022 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6023 | relax_switch (); | |
6024 | /* Set mips_optimize around the lui instruction to avoid | |
6025 | inserting an unnecessary nop after the lw. */ | |
6026 | hold_mips_optimize = mips_optimize; | |
6027 | mips_optimize = 2; | |
6028 | macro_build_lui (&global, tmp); | |
6029 | mips_optimize = hold_mips_optimize; | |
6030 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6031 | relax_end (); | |
6032 | ||
6033 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6034 | } | |
6035 | ||
df58fc94 RS |
6036 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6037 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6038 | is its complementing branch with the original condition negated. | |
6039 | CALL is set if the original branch specified the link operation. | |
6040 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6041 | ||
6042 | Code like this is produced in the noreorder mode: | |
6043 | ||
6044 | BRNEG <args>, 1f | |
6045 | nop | |
6046 | b <sym> | |
6047 | delay slot (executed only if branch taken) | |
6048 | 1: | |
6049 | ||
6050 | or, if CALL is set: | |
6051 | ||
6052 | BRNEG <args>, 1f | |
6053 | nop | |
6054 | bal <sym> | |
6055 | delay slot (executed only if branch taken) | |
6056 | 1: | |
6057 | ||
6058 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6059 | so code produced is simply: | |
6060 | ||
6061 | BR <args>, <sym> | |
6062 | nop | |
6063 | ||
6064 | This function is used when producing code for the microMIPS ASE that | |
6065 | does not implement branch likely instructions in hardware. */ | |
6066 | ||
6067 | static void | |
6068 | macro_build_branch_likely (const char *br, const char *brneg, | |
6069 | int call, expressionS *ep, const char *fmt, | |
6070 | unsigned int sreg, unsigned int treg) | |
6071 | { | |
6072 | int noreorder = mips_opts.noreorder; | |
6073 | expressionS expr1; | |
6074 | ||
6075 | gas_assert (mips_opts.micromips); | |
6076 | start_noreorder (); | |
6077 | if (noreorder) | |
6078 | { | |
6079 | micromips_label_expr (&expr1); | |
6080 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6081 | macro_build (NULL, "nop", ""); | |
6082 | macro_build (ep, call ? "bal" : "b", "p"); | |
6083 | ||
6084 | /* Set to true so that append_insn adds a label. */ | |
6085 | emit_branch_likely_macro = TRUE; | |
6086 | } | |
6087 | else | |
6088 | { | |
6089 | macro_build (ep, br, fmt, sreg, treg); | |
6090 | macro_build (NULL, "nop", ""); | |
6091 | } | |
6092 | end_noreorder (); | |
6093 | } | |
6094 | ||
6095 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6096 | the condition code tested. EP specifies the branch target. */ | |
6097 | ||
6098 | static void | |
6099 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6100 | { | |
6101 | const int call = 0; | |
6102 | const char *brneg; | |
6103 | const char *br; | |
6104 | ||
6105 | switch (type) | |
6106 | { | |
6107 | case M_BC1FL: | |
6108 | br = "bc1f"; | |
6109 | brneg = "bc1t"; | |
6110 | break; | |
6111 | case M_BC1TL: | |
6112 | br = "bc1t"; | |
6113 | brneg = "bc1f"; | |
6114 | break; | |
6115 | case M_BC2FL: | |
6116 | br = "bc2f"; | |
6117 | brneg = "bc2t"; | |
6118 | break; | |
6119 | case M_BC2TL: | |
6120 | br = "bc2t"; | |
6121 | brneg = "bc2f"; | |
6122 | break; | |
6123 | default: | |
6124 | abort (); | |
6125 | } | |
6126 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6127 | } | |
6128 | ||
6129 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6130 | the register tested. EP specifies the branch target. */ | |
6131 | ||
6132 | static void | |
6133 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6134 | { | |
6135 | const char *brneg = NULL; | |
6136 | const char *br; | |
6137 | int call = 0; | |
6138 | ||
6139 | switch (type) | |
6140 | { | |
6141 | case M_BGEZ: | |
6142 | br = "bgez"; | |
6143 | break; | |
6144 | case M_BGEZL: | |
6145 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6146 | brneg = "bltz"; | |
6147 | break; | |
6148 | case M_BGEZALL: | |
6149 | gas_assert (mips_opts.micromips); | |
6150 | br = "bgezals"; | |
6151 | brneg = "bltz"; | |
6152 | call = 1; | |
6153 | break; | |
6154 | case M_BGTZ: | |
6155 | br = "bgtz"; | |
6156 | break; | |
6157 | case M_BGTZL: | |
6158 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6159 | brneg = "blez"; | |
6160 | break; | |
6161 | case M_BLEZ: | |
6162 | br = "blez"; | |
6163 | break; | |
6164 | case M_BLEZL: | |
6165 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6166 | brneg = "bgtz"; | |
6167 | break; | |
6168 | case M_BLTZ: | |
6169 | br = "bltz"; | |
6170 | break; | |
6171 | case M_BLTZL: | |
6172 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6173 | brneg = "bgez"; | |
6174 | break; | |
6175 | case M_BLTZALL: | |
6176 | gas_assert (mips_opts.micromips); | |
6177 | br = "bltzals"; | |
6178 | brneg = "bgez"; | |
6179 | call = 1; | |
6180 | break; | |
6181 | default: | |
6182 | abort (); | |
6183 | } | |
6184 | if (mips_opts.micromips && brneg) | |
6185 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6186 | else | |
6187 | macro_build (ep, br, "s,p", sreg); | |
6188 | } | |
6189 | ||
6190 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6191 | TREG as the registers tested. EP specifies the branch target. */ | |
6192 | ||
6193 | static void | |
6194 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6195 | unsigned int sreg, unsigned int treg) | |
6196 | { | |
6197 | const char *brneg = NULL; | |
6198 | const int call = 0; | |
6199 | const char *br; | |
6200 | ||
6201 | switch (type) | |
6202 | { | |
6203 | case M_BEQ: | |
6204 | case M_BEQ_I: | |
6205 | br = "beq"; | |
6206 | break; | |
6207 | case M_BEQL: | |
6208 | case M_BEQL_I: | |
6209 | br = mips_opts.micromips ? "beq" : "beql"; | |
6210 | brneg = "bne"; | |
6211 | break; | |
6212 | case M_BNE: | |
6213 | case M_BNE_I: | |
6214 | br = "bne"; | |
6215 | break; | |
6216 | case M_BNEL: | |
6217 | case M_BNEL_I: | |
6218 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6219 | brneg = "beq"; | |
6220 | break; | |
6221 | default: | |
6222 | abort (); | |
6223 | } | |
6224 | if (mips_opts.micromips && brneg) | |
6225 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6226 | else | |
6227 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6228 | } | |
6229 | ||
252b5132 RH |
6230 | /* |
6231 | * Build macros | |
6232 | * This routine implements the seemingly endless macro or synthesized | |
6233 | * instructions and addressing modes in the mips assembly language. Many | |
6234 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6235 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6236 | * this verbose method. Others are not simple macros but are more like |
6237 | * optimizing code generation. | |
6238 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6239 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6240 | * The ensuing load upper instructions are ommited. This implies some kind |
6241 | * of global optimization. We currently only optimize within a single macro. | |
6242 | * For many of the load and store macros if the address is specified as a | |
6243 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6244 | * first load register 'at' with zero and use it as the base register. The | |
6245 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6246 | * we're missing. | |
6247 | */ | |
6248 | static void | |
17a2f251 | 6249 | macro (struct mips_cl_insn *ip) |
252b5132 | 6250 | { |
741fe287 MR |
6251 | unsigned int treg, sreg, dreg, breg; |
6252 | unsigned int tempreg; | |
252b5132 | 6253 | int mask; |
43841e91 | 6254 | int used_at = 0; |
df58fc94 | 6255 | expressionS label_expr; |
252b5132 | 6256 | expressionS expr1; |
df58fc94 | 6257 | expressionS *ep; |
252b5132 RH |
6258 | const char *s; |
6259 | const char *s2; | |
6260 | const char *fmt; | |
6261 | int likely = 0; | |
252b5132 | 6262 | int coproc = 0; |
df58fc94 | 6263 | int off12 = 0; |
1abe91b1 | 6264 | int call = 0; |
df58fc94 RS |
6265 | int jals = 0; |
6266 | int dbl = 0; | |
6267 | int imm = 0; | |
6268 | int ust = 0; | |
6269 | int lp = 0; | |
6270 | int ab = 0; | |
dd6a37e7 | 6271 | int off0 = 0; |
252b5132 | 6272 | int off; |
67c0d1eb | 6273 | offsetT maxnum; |
252b5132 | 6274 | bfd_reloc_code_real_type r; |
252b5132 RH |
6275 | int hold_mips_optimize; |
6276 | ||
9c2799c2 | 6277 | gas_assert (! mips_opts.mips16); |
252b5132 | 6278 | |
df58fc94 RS |
6279 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6280 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6281 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6282 | mask = ip->insn_mo->mask; |
6283 | ||
df58fc94 RS |
6284 | label_expr.X_op = O_constant; |
6285 | label_expr.X_op_symbol = NULL; | |
6286 | label_expr.X_add_symbol = NULL; | |
6287 | label_expr.X_add_number = 0; | |
6288 | ||
252b5132 RH |
6289 | expr1.X_op = O_constant; |
6290 | expr1.X_op_symbol = NULL; | |
6291 | expr1.X_add_symbol = NULL; | |
6292 | expr1.X_add_number = 1; | |
6293 | ||
6294 | switch (mask) | |
6295 | { | |
6296 | case M_DABS: | |
6297 | dbl = 1; | |
6298 | case M_ABS: | |
df58fc94 RS |
6299 | /* bgez $a0,1f |
6300 | move v0,$a0 | |
6301 | sub v0,$zero,$a0 | |
6302 | 1: | |
6303 | */ | |
252b5132 | 6304 | |
7d10b47d | 6305 | start_noreorder (); |
252b5132 | 6306 | |
df58fc94 RS |
6307 | if (mips_opts.micromips) |
6308 | micromips_label_expr (&label_expr); | |
6309 | else | |
6310 | label_expr.X_add_number = 8; | |
6311 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6312 | if (dreg == sreg) |
a605d2b3 | 6313 | macro_build (NULL, "nop", ""); |
252b5132 | 6314 | else |
67c0d1eb RS |
6315 | move_register (dreg, sreg); |
6316 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6317 | if (mips_opts.micromips) |
6318 | micromips_add_label (); | |
252b5132 | 6319 | |
7d10b47d | 6320 | end_noreorder (); |
8fc2e39e | 6321 | break; |
252b5132 RH |
6322 | |
6323 | case M_ADD_I: | |
6324 | s = "addi"; | |
6325 | s2 = "add"; | |
6326 | goto do_addi; | |
6327 | case M_ADDU_I: | |
6328 | s = "addiu"; | |
6329 | s2 = "addu"; | |
6330 | goto do_addi; | |
6331 | case M_DADD_I: | |
6332 | dbl = 1; | |
6333 | s = "daddi"; | |
6334 | s2 = "dadd"; | |
df58fc94 RS |
6335 | if (!mips_opts.micromips) |
6336 | goto do_addi; | |
6337 | if (imm_expr.X_op == O_constant | |
6338 | && imm_expr.X_add_number >= -0x200 | |
6339 | && imm_expr.X_add_number < 0x200) | |
6340 | { | |
6341 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6342 | break; | |
6343 | } | |
6344 | goto do_addi_i; | |
252b5132 RH |
6345 | case M_DADDU_I: |
6346 | dbl = 1; | |
6347 | s = "daddiu"; | |
6348 | s2 = "daddu"; | |
6349 | do_addi: | |
6350 | if (imm_expr.X_op == O_constant | |
6351 | && imm_expr.X_add_number >= -0x8000 | |
6352 | && imm_expr.X_add_number < 0x8000) | |
6353 | { | |
67c0d1eb | 6354 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6355 | break; |
252b5132 | 6356 | } |
df58fc94 | 6357 | do_addi_i: |
8fc2e39e | 6358 | used_at = 1; |
67c0d1eb RS |
6359 | load_register (AT, &imm_expr, dbl); |
6360 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6361 | break; |
6362 | ||
6363 | case M_AND_I: | |
6364 | s = "andi"; | |
6365 | s2 = "and"; | |
6366 | goto do_bit; | |
6367 | case M_OR_I: | |
6368 | s = "ori"; | |
6369 | s2 = "or"; | |
6370 | goto do_bit; | |
6371 | case M_NOR_I: | |
6372 | s = ""; | |
6373 | s2 = "nor"; | |
6374 | goto do_bit; | |
6375 | case M_XOR_I: | |
6376 | s = "xori"; | |
6377 | s2 = "xor"; | |
6378 | do_bit: | |
6379 | if (imm_expr.X_op == O_constant | |
6380 | && imm_expr.X_add_number >= 0 | |
6381 | && imm_expr.X_add_number < 0x10000) | |
6382 | { | |
6383 | if (mask != M_NOR_I) | |
67c0d1eb | 6384 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6385 | else |
6386 | { | |
67c0d1eb RS |
6387 | macro_build (&imm_expr, "ori", "t,r,i", |
6388 | treg, sreg, BFD_RELOC_LO16); | |
6389 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6390 | } |
8fc2e39e | 6391 | break; |
252b5132 RH |
6392 | } |
6393 | ||
8fc2e39e | 6394 | used_at = 1; |
67c0d1eb RS |
6395 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6396 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6397 | break; |
6398 | ||
8b082fb1 TS |
6399 | case M_BALIGN: |
6400 | switch (imm_expr.X_add_number) | |
6401 | { | |
6402 | case 0: | |
6403 | macro_build (NULL, "nop", ""); | |
6404 | break; | |
6405 | case 2: | |
6406 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6407 | break; | |
6408 | default: | |
6409 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 6410 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
6411 | break; |
6412 | } | |
6413 | break; | |
6414 | ||
df58fc94 RS |
6415 | case M_BC1FL: |
6416 | case M_BC1TL: | |
6417 | case M_BC2FL: | |
6418 | case M_BC2TL: | |
6419 | gas_assert (mips_opts.micromips); | |
6420 | macro_build_branch_ccl (mask, &offset_expr, | |
6421 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6422 | break; | |
6423 | ||
252b5132 | 6424 | case M_BEQ_I: |
252b5132 | 6425 | case M_BEQL_I: |
252b5132 | 6426 | case M_BNE_I: |
252b5132 | 6427 | case M_BNEL_I: |
252b5132 | 6428 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6429 | treg = 0; |
6430 | else | |
252b5132 | 6431 | { |
df58fc94 RS |
6432 | treg = AT; |
6433 | used_at = 1; | |
6434 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6435 | } |
df58fc94 RS |
6436 | /* Fall through. */ |
6437 | case M_BEQL: | |
6438 | case M_BNEL: | |
6439 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6440 | break; |
6441 | ||
6442 | case M_BGEL: | |
6443 | likely = 1; | |
6444 | case M_BGE: | |
6445 | if (treg == 0) | |
df58fc94 RS |
6446 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6447 | else if (sreg == 0) | |
6448 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6449 | else | |
252b5132 | 6450 | { |
df58fc94 RS |
6451 | used_at = 1; |
6452 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6453 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6454 | &offset_expr, AT, ZERO); | |
252b5132 | 6455 | } |
df58fc94 RS |
6456 | break; |
6457 | ||
6458 | case M_BGEZL: | |
6459 | case M_BGEZALL: | |
6460 | case M_BGTZL: | |
6461 | case M_BLEZL: | |
6462 | case M_BLTZL: | |
6463 | case M_BLTZALL: | |
6464 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6465 | break; |
6466 | ||
6467 | case M_BGTL_I: | |
6468 | likely = 1; | |
6469 | case M_BGT_I: | |
90ecf173 | 6470 | /* Check for > max integer. */ |
252b5132 | 6471 | maxnum = 0x7fffffff; |
ca4e0257 | 6472 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6473 | { |
6474 | maxnum <<= 16; | |
6475 | maxnum |= 0xffff; | |
6476 | maxnum <<= 16; | |
6477 | maxnum |= 0xffff; | |
6478 | } | |
6479 | if (imm_expr.X_op == O_constant | |
6480 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6481 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6482 | { |
6483 | do_false: | |
90ecf173 | 6484 | /* Result is always false. */ |
252b5132 | 6485 | if (! likely) |
a605d2b3 | 6486 | macro_build (NULL, "nop", ""); |
252b5132 | 6487 | else |
df58fc94 | 6488 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6489 | break; |
252b5132 RH |
6490 | } |
6491 | if (imm_expr.X_op != O_constant) | |
6492 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6493 | ++imm_expr.X_add_number; |
252b5132 RH |
6494 | /* FALLTHROUGH */ |
6495 | case M_BGE_I: | |
6496 | case M_BGEL_I: | |
6497 | if (mask == M_BGEL_I) | |
6498 | likely = 1; | |
6499 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6500 | { | |
df58fc94 RS |
6501 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6502 | &offset_expr, sreg); | |
8fc2e39e | 6503 | break; |
252b5132 RH |
6504 | } |
6505 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6506 | { | |
df58fc94 RS |
6507 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6508 | &offset_expr, sreg); | |
8fc2e39e | 6509 | break; |
252b5132 RH |
6510 | } |
6511 | maxnum = 0x7fffffff; | |
ca4e0257 | 6512 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6513 | { |
6514 | maxnum <<= 16; | |
6515 | maxnum |= 0xffff; | |
6516 | maxnum <<= 16; | |
6517 | maxnum |= 0xffff; | |
6518 | } | |
6519 | maxnum = - maxnum - 1; | |
6520 | if (imm_expr.X_op == O_constant | |
6521 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6522 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6523 | { |
6524 | do_true: | |
6525 | /* result is always true */ | |
6526 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6527 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6528 | break; |
252b5132 | 6529 | } |
8fc2e39e | 6530 | used_at = 1; |
67c0d1eb | 6531 | set_at (sreg, 0); |
df58fc94 RS |
6532 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6533 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6534 | break; |
6535 | ||
6536 | case M_BGEUL: | |
6537 | likely = 1; | |
6538 | case M_BGEU: | |
6539 | if (treg == 0) | |
6540 | goto do_true; | |
df58fc94 RS |
6541 | else if (sreg == 0) |
6542 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6543 | &offset_expr, ZERO, treg); | |
6544 | else | |
252b5132 | 6545 | { |
df58fc94 RS |
6546 | used_at = 1; |
6547 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6548 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6549 | &offset_expr, AT, ZERO); | |
252b5132 | 6550 | } |
252b5132 RH |
6551 | break; |
6552 | ||
6553 | case M_BGTUL_I: | |
6554 | likely = 1; | |
6555 | case M_BGTU_I: | |
6556 | if (sreg == 0 | |
ca4e0257 | 6557 | || (HAVE_32BIT_GPRS |
252b5132 | 6558 | && imm_expr.X_op == O_constant |
f01dc953 | 6559 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6560 | goto do_false; |
6561 | if (imm_expr.X_op != O_constant) | |
6562 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6563 | ++imm_expr.X_add_number; |
252b5132 RH |
6564 | /* FALLTHROUGH */ |
6565 | case M_BGEU_I: | |
6566 | case M_BGEUL_I: | |
6567 | if (mask == M_BGEUL_I) | |
6568 | likely = 1; | |
6569 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6570 | goto do_true; | |
df58fc94 RS |
6571 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6572 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6573 | &offset_expr, sreg, ZERO); | |
6574 | else | |
252b5132 | 6575 | { |
df58fc94 RS |
6576 | used_at = 1; |
6577 | set_at (sreg, 1); | |
6578 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6579 | &offset_expr, AT, ZERO); | |
252b5132 | 6580 | } |
252b5132 RH |
6581 | break; |
6582 | ||
6583 | case M_BGTL: | |
6584 | likely = 1; | |
6585 | case M_BGT: | |
6586 | if (treg == 0) | |
df58fc94 RS |
6587 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6588 | else if (sreg == 0) | |
6589 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6590 | else | |
252b5132 | 6591 | { |
df58fc94 RS |
6592 | used_at = 1; |
6593 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6594 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6595 | &offset_expr, AT, ZERO); | |
252b5132 | 6596 | } |
252b5132 RH |
6597 | break; |
6598 | ||
6599 | case M_BGTUL: | |
6600 | likely = 1; | |
6601 | case M_BGTU: | |
6602 | if (treg == 0) | |
df58fc94 RS |
6603 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6604 | &offset_expr, sreg, ZERO); | |
6605 | else if (sreg == 0) | |
6606 | goto do_false; | |
6607 | else | |
252b5132 | 6608 | { |
df58fc94 RS |
6609 | used_at = 1; |
6610 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6611 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6612 | &offset_expr, AT, ZERO); | |
252b5132 | 6613 | } |
252b5132 RH |
6614 | break; |
6615 | ||
6616 | case M_BLEL: | |
6617 | likely = 1; | |
6618 | case M_BLE: | |
6619 | if (treg == 0) | |
df58fc94 RS |
6620 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6621 | else if (sreg == 0) | |
6622 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6623 | else | |
252b5132 | 6624 | { |
df58fc94 RS |
6625 | used_at = 1; |
6626 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6627 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6628 | &offset_expr, AT, ZERO); | |
252b5132 | 6629 | } |
252b5132 RH |
6630 | break; |
6631 | ||
6632 | case M_BLEL_I: | |
6633 | likely = 1; | |
6634 | case M_BLE_I: | |
6635 | maxnum = 0x7fffffff; | |
ca4e0257 | 6636 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6637 | { |
6638 | maxnum <<= 16; | |
6639 | maxnum |= 0xffff; | |
6640 | maxnum <<= 16; | |
6641 | maxnum |= 0xffff; | |
6642 | } | |
6643 | if (imm_expr.X_op == O_constant | |
6644 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6645 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6646 | goto do_true; |
6647 | if (imm_expr.X_op != O_constant) | |
6648 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6649 | ++imm_expr.X_add_number; |
252b5132 RH |
6650 | /* FALLTHROUGH */ |
6651 | case M_BLT_I: | |
6652 | case M_BLTL_I: | |
6653 | if (mask == M_BLTL_I) | |
6654 | likely = 1; | |
6655 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6656 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6657 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6658 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6659 | else | |
252b5132 | 6660 | { |
df58fc94 RS |
6661 | used_at = 1; |
6662 | set_at (sreg, 0); | |
6663 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6664 | &offset_expr, AT, ZERO); | |
252b5132 | 6665 | } |
252b5132 RH |
6666 | break; |
6667 | ||
6668 | case M_BLEUL: | |
6669 | likely = 1; | |
6670 | case M_BLEU: | |
6671 | if (treg == 0) | |
df58fc94 RS |
6672 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6673 | &offset_expr, sreg, ZERO); | |
6674 | else if (sreg == 0) | |
6675 | goto do_true; | |
6676 | else | |
252b5132 | 6677 | { |
df58fc94 RS |
6678 | used_at = 1; |
6679 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6680 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6681 | &offset_expr, AT, ZERO); | |
252b5132 | 6682 | } |
252b5132 RH |
6683 | break; |
6684 | ||
6685 | case M_BLEUL_I: | |
6686 | likely = 1; | |
6687 | case M_BLEU_I: | |
6688 | if (sreg == 0 | |
ca4e0257 | 6689 | || (HAVE_32BIT_GPRS |
252b5132 | 6690 | && imm_expr.X_op == O_constant |
f01dc953 | 6691 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6692 | goto do_true; |
6693 | if (imm_expr.X_op != O_constant) | |
6694 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6695 | ++imm_expr.X_add_number; |
252b5132 RH |
6696 | /* FALLTHROUGH */ |
6697 | case M_BLTU_I: | |
6698 | case M_BLTUL_I: | |
6699 | if (mask == M_BLTUL_I) | |
6700 | likely = 1; | |
6701 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6702 | goto do_false; | |
df58fc94 RS |
6703 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6704 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6705 | &offset_expr, sreg, ZERO); | |
6706 | else | |
252b5132 | 6707 | { |
df58fc94 RS |
6708 | used_at = 1; |
6709 | set_at (sreg, 1); | |
6710 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6711 | &offset_expr, AT, ZERO); | |
252b5132 | 6712 | } |
252b5132 RH |
6713 | break; |
6714 | ||
6715 | case M_BLTL: | |
6716 | likely = 1; | |
6717 | case M_BLT: | |
6718 | if (treg == 0) | |
df58fc94 RS |
6719 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6720 | else if (sreg == 0) | |
6721 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6722 | else | |
252b5132 | 6723 | { |
df58fc94 RS |
6724 | used_at = 1; |
6725 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6726 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6727 | &offset_expr, AT, ZERO); | |
252b5132 | 6728 | } |
252b5132 RH |
6729 | break; |
6730 | ||
6731 | case M_BLTUL: | |
6732 | likely = 1; | |
6733 | case M_BLTU: | |
6734 | if (treg == 0) | |
6735 | goto do_false; | |
df58fc94 RS |
6736 | else if (sreg == 0) |
6737 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6738 | &offset_expr, ZERO, treg); | |
6739 | else | |
252b5132 | 6740 | { |
df58fc94 RS |
6741 | used_at = 1; |
6742 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6743 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6744 | &offset_expr, AT, ZERO); | |
252b5132 | 6745 | } |
252b5132 RH |
6746 | break; |
6747 | ||
5f74bc13 CD |
6748 | case M_DEXT: |
6749 | { | |
d5818fca MR |
6750 | /* Use unsigned arithmetic. */ |
6751 | addressT pos; | |
6752 | addressT size; | |
5f74bc13 | 6753 | |
90ecf173 | 6754 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6755 | { |
6756 | as_bad (_("Unsupported large constant")); | |
6757 | pos = size = 1; | |
6758 | } | |
6759 | else | |
6760 | { | |
d5818fca MR |
6761 | pos = imm_expr.X_add_number; |
6762 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6763 | } |
6764 | ||
6765 | if (pos > 63) | |
6766 | { | |
d5818fca | 6767 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6768 | pos = 1; |
6769 | } | |
90ecf173 | 6770 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6771 | { |
6772 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6773 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6774 | size = 1; |
6775 | } | |
6776 | ||
6777 | if (size <= 32 && pos < 32) | |
6778 | { | |
6779 | s = "dext"; | |
6780 | fmt = "t,r,+A,+C"; | |
6781 | } | |
6782 | else if (size <= 32) | |
6783 | { | |
6784 | s = "dextu"; | |
6785 | fmt = "t,r,+E,+H"; | |
6786 | } | |
6787 | else | |
6788 | { | |
6789 | s = "dextm"; | |
6790 | fmt = "t,r,+A,+G"; | |
6791 | } | |
d5818fca MR |
6792 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6793 | (int) (size - 1)); | |
5f74bc13 | 6794 | } |
8fc2e39e | 6795 | break; |
5f74bc13 CD |
6796 | |
6797 | case M_DINS: | |
6798 | { | |
d5818fca MR |
6799 | /* Use unsigned arithmetic. */ |
6800 | addressT pos; | |
6801 | addressT size; | |
5f74bc13 | 6802 | |
90ecf173 | 6803 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6804 | { |
6805 | as_bad (_("Unsupported large constant")); | |
6806 | pos = size = 1; | |
6807 | } | |
6808 | else | |
6809 | { | |
d5818fca MR |
6810 | pos = imm_expr.X_add_number; |
6811 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6812 | } |
6813 | ||
6814 | if (pos > 63) | |
6815 | { | |
d5818fca | 6816 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6817 | pos = 1; |
6818 | } | |
90ecf173 | 6819 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6820 | { |
6821 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6822 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6823 | size = 1; |
6824 | } | |
6825 | ||
6826 | if (pos < 32 && (pos + size - 1) < 32) | |
6827 | { | |
6828 | s = "dins"; | |
6829 | fmt = "t,r,+A,+B"; | |
6830 | } | |
6831 | else if (pos >= 32) | |
6832 | { | |
6833 | s = "dinsu"; | |
6834 | fmt = "t,r,+E,+F"; | |
6835 | } | |
6836 | else | |
6837 | { | |
6838 | s = "dinsm"; | |
6839 | fmt = "t,r,+A,+F"; | |
6840 | } | |
750bdd57 AS |
6841 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6842 | (int) (pos + size - 1)); | |
5f74bc13 | 6843 | } |
8fc2e39e | 6844 | break; |
5f74bc13 | 6845 | |
252b5132 RH |
6846 | case M_DDIV_3: |
6847 | dbl = 1; | |
6848 | case M_DIV_3: | |
6849 | s = "mflo"; | |
6850 | goto do_div3; | |
6851 | case M_DREM_3: | |
6852 | dbl = 1; | |
6853 | case M_REM_3: | |
6854 | s = "mfhi"; | |
6855 | do_div3: | |
6856 | if (treg == 0) | |
6857 | { | |
6858 | as_warn (_("Divide by zero.")); | |
6859 | if (mips_trap) | |
df58fc94 | 6860 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6861 | else |
df58fc94 | 6862 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6863 | break; |
252b5132 RH |
6864 | } |
6865 | ||
7d10b47d | 6866 | start_noreorder (); |
252b5132 RH |
6867 | if (mips_trap) |
6868 | { | |
df58fc94 | 6869 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6870 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
6871 | } |
6872 | else | |
6873 | { | |
df58fc94 RS |
6874 | if (mips_opts.micromips) |
6875 | micromips_label_expr (&label_expr); | |
6876 | else | |
6877 | label_expr.X_add_number = 8; | |
6878 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 6879 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
6880 | macro_build (NULL, "break", BRK_FMT, 7); |
6881 | if (mips_opts.micromips) | |
6882 | micromips_add_label (); | |
252b5132 RH |
6883 | } |
6884 | expr1.X_add_number = -1; | |
8fc2e39e | 6885 | used_at = 1; |
f6a22291 | 6886 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
6887 | if (mips_opts.micromips) |
6888 | micromips_label_expr (&label_expr); | |
6889 | else | |
6890 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
6891 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
6892 | if (dbl) |
6893 | { | |
6894 | expr1.X_add_number = 1; | |
f6a22291 | 6895 | load_register (AT, &expr1, dbl); |
df58fc94 | 6896 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
6897 | } |
6898 | else | |
6899 | { | |
6900 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 6901 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
6902 | } |
6903 | if (mips_trap) | |
6904 | { | |
df58fc94 | 6905 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
6906 | /* We want to close the noreorder block as soon as possible, so |
6907 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6908 | end_noreorder (); |
252b5132 RH |
6909 | } |
6910 | else | |
6911 | { | |
df58fc94 RS |
6912 | if (mips_opts.micromips) |
6913 | micromips_label_expr (&label_expr); | |
6914 | else | |
6915 | label_expr.X_add_number = 8; | |
6916 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 6917 | macro_build (NULL, "nop", ""); |
252b5132 RH |
6918 | |
6919 | /* We want to close the noreorder block as soon as possible, so | |
6920 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6921 | end_noreorder (); |
252b5132 | 6922 | |
df58fc94 | 6923 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 6924 | } |
df58fc94 RS |
6925 | if (mips_opts.micromips) |
6926 | micromips_add_label (); | |
6927 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
6928 | break; |
6929 | ||
6930 | case M_DIV_3I: | |
6931 | s = "div"; | |
6932 | s2 = "mflo"; | |
6933 | goto do_divi; | |
6934 | case M_DIVU_3I: | |
6935 | s = "divu"; | |
6936 | s2 = "mflo"; | |
6937 | goto do_divi; | |
6938 | case M_REM_3I: | |
6939 | s = "div"; | |
6940 | s2 = "mfhi"; | |
6941 | goto do_divi; | |
6942 | case M_REMU_3I: | |
6943 | s = "divu"; | |
6944 | s2 = "mfhi"; | |
6945 | goto do_divi; | |
6946 | case M_DDIV_3I: | |
6947 | dbl = 1; | |
6948 | s = "ddiv"; | |
6949 | s2 = "mflo"; | |
6950 | goto do_divi; | |
6951 | case M_DDIVU_3I: | |
6952 | dbl = 1; | |
6953 | s = "ddivu"; | |
6954 | s2 = "mflo"; | |
6955 | goto do_divi; | |
6956 | case M_DREM_3I: | |
6957 | dbl = 1; | |
6958 | s = "ddiv"; | |
6959 | s2 = "mfhi"; | |
6960 | goto do_divi; | |
6961 | case M_DREMU_3I: | |
6962 | dbl = 1; | |
6963 | s = "ddivu"; | |
6964 | s2 = "mfhi"; | |
6965 | do_divi: | |
6966 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6967 | { | |
6968 | as_warn (_("Divide by zero.")); | |
6969 | if (mips_trap) | |
df58fc94 | 6970 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6971 | else |
df58fc94 | 6972 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6973 | break; |
252b5132 RH |
6974 | } |
6975 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6976 | { | |
6977 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 6978 | move_register (dreg, sreg); |
252b5132 | 6979 | else |
c80c840e | 6980 | move_register (dreg, ZERO); |
8fc2e39e | 6981 | break; |
252b5132 RH |
6982 | } |
6983 | if (imm_expr.X_op == O_constant | |
6984 | && imm_expr.X_add_number == -1 | |
6985 | && s[strlen (s) - 1] != 'u') | |
6986 | { | |
6987 | if (strcmp (s2, "mflo") == 0) | |
6988 | { | |
67c0d1eb | 6989 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
6990 | } |
6991 | else | |
c80c840e | 6992 | move_register (dreg, ZERO); |
8fc2e39e | 6993 | break; |
252b5132 RH |
6994 | } |
6995 | ||
8fc2e39e | 6996 | used_at = 1; |
67c0d1eb RS |
6997 | load_register (AT, &imm_expr, dbl); |
6998 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 6999 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7000 | break; |
7001 | ||
7002 | case M_DIVU_3: | |
7003 | s = "divu"; | |
7004 | s2 = "mflo"; | |
7005 | goto do_divu3; | |
7006 | case M_REMU_3: | |
7007 | s = "divu"; | |
7008 | s2 = "mfhi"; | |
7009 | goto do_divu3; | |
7010 | case M_DDIVU_3: | |
7011 | s = "ddivu"; | |
7012 | s2 = "mflo"; | |
7013 | goto do_divu3; | |
7014 | case M_DREMU_3: | |
7015 | s = "ddivu"; | |
7016 | s2 = "mfhi"; | |
7017 | do_divu3: | |
7d10b47d | 7018 | start_noreorder (); |
252b5132 RH |
7019 | if (mips_trap) |
7020 | { | |
df58fc94 | 7021 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7022 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7023 | /* We want to close the noreorder block as soon as possible, so |
7024 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7025 | end_noreorder (); |
252b5132 RH |
7026 | } |
7027 | else | |
7028 | { | |
df58fc94 RS |
7029 | if (mips_opts.micromips) |
7030 | micromips_label_expr (&label_expr); | |
7031 | else | |
7032 | label_expr.X_add_number = 8; | |
7033 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7034 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7035 | |
7036 | /* We want to close the noreorder block as soon as possible, so | |
7037 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7038 | end_noreorder (); |
df58fc94 RS |
7039 | macro_build (NULL, "break", BRK_FMT, 7); |
7040 | if (mips_opts.micromips) | |
7041 | micromips_add_label (); | |
252b5132 | 7042 | } |
df58fc94 | 7043 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7044 | break; |
252b5132 | 7045 | |
1abe91b1 MR |
7046 | case M_DLCA_AB: |
7047 | dbl = 1; | |
7048 | case M_LCA_AB: | |
7049 | call = 1; | |
7050 | goto do_la; | |
252b5132 RH |
7051 | case M_DLA_AB: |
7052 | dbl = 1; | |
7053 | case M_LA_AB: | |
1abe91b1 | 7054 | do_la: |
252b5132 RH |
7055 | /* Load the address of a symbol into a register. If breg is not |
7056 | zero, we then add a base register to it. */ | |
7057 | ||
3bec30a8 TS |
7058 | if (dbl && HAVE_32BIT_GPRS) |
7059 | as_warn (_("dla used to load 32-bit register")); | |
7060 | ||
90ecf173 | 7061 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7062 | as_warn (_("la used to load 64-bit address")); |
7063 | ||
0c11417f MR |
7064 | if (offset_expr.X_op == O_constant |
7065 | && offset_expr.X_add_number >= -0x8000 | |
7066 | && offset_expr.X_add_number < 0x8000) | |
7067 | { | |
aed1a261 | 7068 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7069 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7070 | break; |
0c11417f MR |
7071 | } |
7072 | ||
741fe287 | 7073 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7074 | { |
7075 | tempreg = AT; | |
7076 | used_at = 1; | |
7077 | } | |
7078 | else | |
7079 | { | |
7080 | tempreg = treg; | |
afdbd6d0 CD |
7081 | } |
7082 | ||
252b5132 RH |
7083 | if (offset_expr.X_op != O_symbol |
7084 | && offset_expr.X_op != O_constant) | |
7085 | { | |
f71d0d44 | 7086 | as_bad (_("Expression too complex")); |
252b5132 RH |
7087 | offset_expr.X_op = O_constant; |
7088 | } | |
7089 | ||
252b5132 | 7090 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7091 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7092 | else if (mips_pic == NO_PIC) |
7093 | { | |
d6bc6245 | 7094 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7095 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7096 | Otherwise we want |
7097 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7098 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7099 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7100 | so we may as well always use the latter form. |
76b3015f | 7101 | |
6caf9ef4 TS |
7102 | With 64bit address space and a usable $at we want |
7103 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7104 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7105 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7106 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7107 | dsll32 $tempreg,0 | |
7108 | daddu $tempreg,$tempreg,$at | |
7109 | ||
7110 | If $at is already in use, we use a path which is suboptimal | |
7111 | on superscalar processors. | |
7112 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7113 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7114 | dsll $tempreg,16 | |
7115 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7116 | dsll $tempreg,16 | |
7117 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7118 | ||
7119 | For GP relative symbols in 64bit address space we can use | |
7120 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7121 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7122 | { |
6caf9ef4 TS |
7123 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7124 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7125 | { | |
7126 | relax_start (offset_expr.X_add_symbol); | |
7127 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7128 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7129 | relax_switch (); | |
7130 | } | |
d6bc6245 | 7131 | |
741fe287 | 7132 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7133 | { |
df58fc94 | 7134 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7135 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7136 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7137 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7138 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7139 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7140 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7141 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7142 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7143 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7144 | used_at = 1; |
7145 | } | |
7146 | else | |
7147 | { | |
df58fc94 | 7148 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7149 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7150 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7151 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7152 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7153 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7154 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7155 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7156 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7157 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7158 | } |
6caf9ef4 TS |
7159 | |
7160 | if (mips_relax.sequence) | |
7161 | relax_end (); | |
98d3f06f KH |
7162 | } |
7163 | else | |
7164 | { | |
7165 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7166 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7167 | { |
4d7206a2 | 7168 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7169 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7170 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7171 | relax_switch (); |
98d3f06f | 7172 | } |
6943caf0 | 7173 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7174 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7175 | macro_build_lui (&offset_expr, tempreg); |
7176 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7177 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7178 | if (mips_relax.sequence) |
7179 | relax_end (); | |
98d3f06f | 7180 | } |
252b5132 | 7181 | } |
0a44bf69 | 7182 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7183 | { |
9117d219 NC |
7184 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7185 | ||
252b5132 RH |
7186 | /* If this is a reference to an external symbol, and there |
7187 | is no constant, we want | |
7188 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7189 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7190 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7191 | For a local symbol, we want |
7192 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7193 | nop | |
7194 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7195 | ||
7196 | If we have a small constant, and this is a reference to | |
7197 | an external symbol, we want | |
7198 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7199 | nop | |
7200 | addiu $tempreg,$tempreg,<constant> | |
7201 | For a local symbol, we want the same instruction | |
7202 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7203 | addiu instruction. | |
7204 | ||
7205 | If we have a large constant, and this is a reference to | |
7206 | an external symbol, we want | |
7207 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7208 | lui $at,<hiconstant> | |
7209 | addiu $at,$at,<loconstant> | |
7210 | addu $tempreg,$tempreg,$at | |
7211 | For a local symbol, we want the same instruction | |
7212 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7213 | addiu instruction. |
ed6fb7bd SC |
7214 | */ |
7215 | ||
4d7206a2 | 7216 | if (offset_expr.X_add_number == 0) |
252b5132 | 7217 | { |
0a44bf69 RS |
7218 | if (mips_pic == SVR4_PIC |
7219 | && breg == 0 | |
7220 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7221 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7222 | ||
7223 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7224 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7225 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7226 | if (breg != 0) |
252b5132 RH |
7227 | { |
7228 | /* We're going to put in an addu instruction using | |
7229 | tempreg, so we may as well insert the nop right | |
7230 | now. */ | |
269137b2 | 7231 | load_delay_nop (); |
252b5132 | 7232 | } |
4d7206a2 | 7233 | relax_switch (); |
67c0d1eb RS |
7234 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7235 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7236 | load_delay_nop (); |
67c0d1eb RS |
7237 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7238 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7239 | relax_end (); |
252b5132 RH |
7240 | /* FIXME: If breg == 0, and the next instruction uses |
7241 | $tempreg, then if this variant case is used an extra | |
7242 | nop will be generated. */ | |
7243 | } | |
4d7206a2 RS |
7244 | else if (offset_expr.X_add_number >= -0x8000 |
7245 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7246 | { |
67c0d1eb | 7247 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7248 | load_delay_nop (); |
67c0d1eb | 7249 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7250 | } |
7251 | else | |
7252 | { | |
4d7206a2 RS |
7253 | expr1.X_add_number = offset_expr.X_add_number; |
7254 | offset_expr.X_add_number = | |
7255 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 7256 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7257 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7258 | /* If we are going to add in a base register, and the |
7259 | target register and the base register are the same, | |
7260 | then we are using AT as a temporary register. Since | |
7261 | we want to load the constant into AT, we add our | |
7262 | current AT (from the global offset table) and the | |
7263 | register into the register now, and pretend we were | |
7264 | not using a base register. */ | |
67c0d1eb | 7265 | if (breg == treg) |
252b5132 | 7266 | { |
269137b2 | 7267 | load_delay_nop (); |
67c0d1eb | 7268 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7269 | treg, AT, breg); |
252b5132 RH |
7270 | breg = 0; |
7271 | tempreg = treg; | |
252b5132 | 7272 | } |
f6a22291 | 7273 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7274 | used_at = 1; |
7275 | } | |
7276 | } | |
0a44bf69 | 7277 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7278 | { |
67c0d1eb | 7279 | int add_breg_early = 0; |
f5040a92 AO |
7280 | |
7281 | /* If this is a reference to an external, and there is no | |
7282 | constant, or local symbol (*), with or without a | |
7283 | constant, we want | |
7284 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7285 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7286 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7287 | ||
7288 | If we have a small constant, and this is a reference to | |
7289 | an external symbol, we want | |
7290 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7291 | addiu $tempreg,$tempreg,<constant> | |
7292 | ||
7293 | If we have a large constant, and this is a reference to | |
7294 | an external symbol, we want | |
7295 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7296 | lui $at,<hiconstant> | |
7297 | addiu $at,$at,<loconstant> | |
7298 | addu $tempreg,$tempreg,$at | |
7299 | ||
7300 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7301 | local symbols, even though it introduces an additional | |
7302 | instruction. */ | |
7303 | ||
f5040a92 AO |
7304 | if (offset_expr.X_add_number) |
7305 | { | |
4d7206a2 | 7306 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7307 | offset_expr.X_add_number = 0; |
7308 | ||
4d7206a2 | 7309 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7310 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7311 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7312 | |
7313 | if (expr1.X_add_number >= -0x8000 | |
7314 | && expr1.X_add_number < 0x8000) | |
7315 | { | |
67c0d1eb RS |
7316 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7317 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7318 | } |
ecd13cd3 | 7319 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7320 | { |
f5040a92 AO |
7321 | /* If we are going to add in a base register, and the |
7322 | target register and the base register are the same, | |
7323 | then we are using AT as a temporary register. Since | |
7324 | we want to load the constant into AT, we add our | |
7325 | current AT (from the global offset table) and the | |
7326 | register into the register now, and pretend we were | |
7327 | not using a base register. */ | |
7328 | if (breg != treg) | |
7329 | dreg = tempreg; | |
7330 | else | |
7331 | { | |
9c2799c2 | 7332 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7333 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7334 | treg, AT, breg); | |
f5040a92 | 7335 | dreg = treg; |
67c0d1eb | 7336 | add_breg_early = 1; |
f5040a92 AO |
7337 | } |
7338 | ||
f6a22291 | 7339 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7340 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7341 | dreg, dreg, AT); |
f5040a92 | 7342 | |
f5040a92 AO |
7343 | used_at = 1; |
7344 | } | |
7345 | else | |
7346 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7347 | ||
4d7206a2 | 7348 | relax_switch (); |
f5040a92 AO |
7349 | offset_expr.X_add_number = expr1.X_add_number; |
7350 | ||
67c0d1eb RS |
7351 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7352 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7353 | if (add_breg_early) | |
f5040a92 | 7354 | { |
67c0d1eb | 7355 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7356 | treg, tempreg, breg); |
f5040a92 AO |
7357 | breg = 0; |
7358 | tempreg = treg; | |
7359 | } | |
4d7206a2 | 7360 | relax_end (); |
f5040a92 | 7361 | } |
4d7206a2 | 7362 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7363 | { |
4d7206a2 | 7364 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7365 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7366 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7367 | relax_switch (); |
67c0d1eb RS |
7368 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7369 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7370 | relax_end (); |
f5040a92 | 7371 | } |
4d7206a2 | 7372 | else |
f5040a92 | 7373 | { |
67c0d1eb RS |
7374 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7375 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7376 | } |
7377 | } | |
0a44bf69 | 7378 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7379 | { |
67c0d1eb | 7380 | int gpdelay; |
9117d219 NC |
7381 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7382 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7383 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7384 | |
7385 | /* This is the large GOT case. If this is a reference to an | |
7386 | external symbol, and there is no constant, we want | |
7387 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7388 | addu $tempreg,$tempreg,$gp | |
7389 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7390 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7391 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7392 | addu $tempreg,$tempreg,$gp | |
7393 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7394 | For a local symbol, we want |
7395 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7396 | nop | |
7397 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7398 | ||
7399 | If we have a small constant, and this is a reference to | |
7400 | an external symbol, we want | |
7401 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7402 | addu $tempreg,$tempreg,$gp | |
7403 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7404 | nop | |
7405 | addiu $tempreg,$tempreg,<constant> | |
7406 | For a local symbol, we want | |
7407 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7408 | nop | |
7409 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7410 | ||
7411 | If we have a large constant, and this is a reference to | |
7412 | an external symbol, we want | |
7413 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7414 | addu $tempreg,$tempreg,$gp | |
7415 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7416 | lui $at,<hiconstant> | |
7417 | addiu $at,$at,<loconstant> | |
7418 | addu $tempreg,$tempreg,$at | |
7419 | For a local symbol, we want | |
7420 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7421 | lui $at,<hiconstant> | |
7422 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7423 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7424 | */ |
438c16b8 | 7425 | |
252b5132 RH |
7426 | expr1.X_add_number = offset_expr.X_add_number; |
7427 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7428 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7429 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7430 | if (expr1.X_add_number == 0 && breg == 0 |
7431 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7432 | { |
7433 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7434 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7435 | } | |
df58fc94 | 7436 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7437 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7438 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7439 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7440 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7441 | if (expr1.X_add_number == 0) |
7442 | { | |
67c0d1eb | 7443 | if (breg != 0) |
252b5132 RH |
7444 | { |
7445 | /* We're going to put in an addu instruction using | |
7446 | tempreg, so we may as well insert the nop right | |
7447 | now. */ | |
269137b2 | 7448 | load_delay_nop (); |
252b5132 | 7449 | } |
252b5132 RH |
7450 | } |
7451 | else if (expr1.X_add_number >= -0x8000 | |
7452 | && expr1.X_add_number < 0x8000) | |
7453 | { | |
269137b2 | 7454 | load_delay_nop (); |
67c0d1eb | 7455 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7456 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7457 | } |
7458 | else | |
7459 | { | |
252b5132 RH |
7460 | /* If we are going to add in a base register, and the |
7461 | target register and the base register are the same, | |
7462 | then we are using AT as a temporary register. Since | |
7463 | we want to load the constant into AT, we add our | |
7464 | current AT (from the global offset table) and the | |
7465 | register into the register now, and pretend we were | |
7466 | not using a base register. */ | |
7467 | if (breg != treg) | |
67c0d1eb | 7468 | dreg = tempreg; |
252b5132 RH |
7469 | else |
7470 | { | |
9c2799c2 | 7471 | gas_assert (tempreg == AT); |
269137b2 | 7472 | load_delay_nop (); |
67c0d1eb | 7473 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7474 | treg, AT, breg); |
252b5132 | 7475 | dreg = treg; |
252b5132 RH |
7476 | } |
7477 | ||
f6a22291 | 7478 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7479 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7480 | |
252b5132 RH |
7481 | used_at = 1; |
7482 | } | |
4d7206a2 RS |
7483 | offset_expr.X_add_number = |
7484 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
7485 | relax_switch (); | |
252b5132 | 7486 | |
67c0d1eb | 7487 | if (gpdelay) |
252b5132 RH |
7488 | { |
7489 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7490 | the first instruction on the main stream does not. */ |
67c0d1eb | 7491 | macro_build (NULL, "nop", ""); |
252b5132 | 7492 | } |
ed6fb7bd | 7493 | |
67c0d1eb RS |
7494 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7495 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7496 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7497 | && expr1.X_add_number < 0x8000) |
7498 | { | |
269137b2 | 7499 | load_delay_nop (); |
67c0d1eb RS |
7500 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7501 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7502 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7503 | register, the external symbol case ended with a load, |
7504 | so if the symbol turns out to not be external, and | |
7505 | the next instruction uses tempreg, an unnecessary nop | |
7506 | will be inserted. */ | |
252b5132 RH |
7507 | } |
7508 | else | |
7509 | { | |
7510 | if (breg == treg) | |
7511 | { | |
7512 | /* We must add in the base register now, as in the | |
f5040a92 | 7513 | external symbol case. */ |
9c2799c2 | 7514 | gas_assert (tempreg == AT); |
269137b2 | 7515 | load_delay_nop (); |
67c0d1eb | 7516 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7517 | treg, AT, breg); |
252b5132 RH |
7518 | tempreg = treg; |
7519 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7520 | it in in both cases. */ |
252b5132 RH |
7521 | breg = 0; |
7522 | } | |
7523 | ||
67c0d1eb RS |
7524 | macro_build_lui (&expr1, AT); |
7525 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7526 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7527 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7528 | tempreg, tempreg, AT); |
8fc2e39e | 7529 | used_at = 1; |
252b5132 | 7530 | } |
4d7206a2 | 7531 | relax_end (); |
252b5132 | 7532 | } |
0a44bf69 | 7533 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7534 | { |
f5040a92 AO |
7535 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7536 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7537 | int add_breg_early = 0; |
f5040a92 AO |
7538 | |
7539 | /* This is the large GOT case. If this is a reference to an | |
7540 | external symbol, and there is no constant, we want | |
7541 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7542 | add $tempreg,$tempreg,$gp | |
7543 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7544 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7545 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7546 | add $tempreg,$tempreg,$gp | |
7547 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7548 | ||
7549 | If we have a small constant, and this is a reference to | |
7550 | an external symbol, we want | |
7551 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7552 | add $tempreg,$tempreg,$gp | |
7553 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7554 | addi $tempreg,$tempreg,<constant> | |
7555 | ||
7556 | If we have a large constant, and this is a reference to | |
7557 | an external symbol, we want | |
7558 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7559 | addu $tempreg,$tempreg,$gp | |
7560 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7561 | lui $at,<hiconstant> | |
7562 | addi $at,$at,<loconstant> | |
7563 | add $tempreg,$tempreg,$at | |
7564 | ||
7565 | If we have NewABI, and we know it's a local symbol, we want | |
7566 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7567 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7568 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7569 | ||
4d7206a2 | 7570 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7571 | |
4d7206a2 | 7572 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7573 | offset_expr.X_add_number = 0; |
7574 | ||
1abe91b1 MR |
7575 | if (expr1.X_add_number == 0 && breg == 0 |
7576 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7577 | { |
7578 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7579 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7580 | } | |
df58fc94 | 7581 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7582 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7583 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7584 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7585 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7586 | |
7587 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7588 | ; |
f5040a92 AO |
7589 | else if (expr1.X_add_number >= -0x8000 |
7590 | && expr1.X_add_number < 0x8000) | |
7591 | { | |
67c0d1eb | 7592 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7593 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7594 | } |
ecd13cd3 | 7595 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7596 | { |
f5040a92 AO |
7597 | /* If we are going to add in a base register, and the |
7598 | target register and the base register are the same, | |
7599 | then we are using AT as a temporary register. Since | |
7600 | we want to load the constant into AT, we add our | |
7601 | current AT (from the global offset table) and the | |
7602 | register into the register now, and pretend we were | |
7603 | not using a base register. */ | |
7604 | if (breg != treg) | |
7605 | dreg = tempreg; | |
7606 | else | |
7607 | { | |
9c2799c2 | 7608 | gas_assert (tempreg == AT); |
67c0d1eb | 7609 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7610 | treg, AT, breg); |
f5040a92 | 7611 | dreg = treg; |
67c0d1eb | 7612 | add_breg_early = 1; |
f5040a92 AO |
7613 | } |
7614 | ||
f6a22291 | 7615 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7616 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7617 | |
f5040a92 AO |
7618 | used_at = 1; |
7619 | } | |
7620 | else | |
7621 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7622 | ||
4d7206a2 | 7623 | relax_switch (); |
f5040a92 | 7624 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7625 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7626 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7627 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7628 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7629 | if (add_breg_early) | |
f5040a92 | 7630 | { |
67c0d1eb | 7631 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7632 | treg, tempreg, breg); |
f5040a92 AO |
7633 | breg = 0; |
7634 | tempreg = treg; | |
7635 | } | |
4d7206a2 | 7636 | relax_end (); |
f5040a92 | 7637 | } |
252b5132 RH |
7638 | else |
7639 | abort (); | |
7640 | ||
7641 | if (breg != 0) | |
aed1a261 | 7642 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7643 | break; |
7644 | ||
52b6b6b9 | 7645 | case M_MSGSND: |
df58fc94 | 7646 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7647 | { |
7648 | unsigned long temp = (treg << 16) | (0x01); | |
7649 | macro_build (NULL, "c2", "C", temp); | |
7650 | } | |
c7af4273 | 7651 | break; |
52b6b6b9 JM |
7652 | |
7653 | case M_MSGLD: | |
df58fc94 | 7654 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7655 | { |
7656 | unsigned long temp = (0x02); | |
7657 | macro_build (NULL, "c2", "C", temp); | |
7658 | } | |
c7af4273 | 7659 | break; |
52b6b6b9 JM |
7660 | |
7661 | case M_MSGLD_T: | |
df58fc94 | 7662 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7663 | { |
7664 | unsigned long temp = (treg << 16) | (0x02); | |
7665 | macro_build (NULL, "c2", "C", temp); | |
7666 | } | |
c7af4273 | 7667 | break; |
52b6b6b9 JM |
7668 | |
7669 | case M_MSGWAIT: | |
df58fc94 | 7670 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7671 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7672 | break; |
52b6b6b9 JM |
7673 | |
7674 | case M_MSGWAIT_T: | |
df58fc94 | 7675 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7676 | { |
7677 | unsigned long temp = (treg << 16) | 0x03; | |
7678 | macro_build (NULL, "c2", "C", temp); | |
7679 | } | |
c7af4273 | 7680 | break; |
52b6b6b9 | 7681 | |
252b5132 RH |
7682 | case M_J_A: |
7683 | /* The j instruction may not be used in PIC code, since it | |
7684 | requires an absolute address. We convert it to a b | |
7685 | instruction. */ | |
7686 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7687 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7688 | else |
67c0d1eb | 7689 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7690 | break; |
252b5132 RH |
7691 | |
7692 | /* The jal instructions must be handled as macros because when | |
7693 | generating PIC code they expand to multi-instruction | |
7694 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7695 | case M_JALS_1: |
7696 | dreg = RA; | |
7697 | /* Fall through. */ | |
7698 | case M_JALS_2: | |
7699 | gas_assert (mips_opts.micromips); | |
7700 | jals = 1; | |
7701 | goto jal; | |
252b5132 RH |
7702 | case M_JAL_1: |
7703 | dreg = RA; | |
7704 | /* Fall through. */ | |
7705 | case M_JAL_2: | |
df58fc94 | 7706 | jal: |
3e722fb5 | 7707 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7708 | { |
7709 | s = jals ? "jalrs" : "jalr"; | |
7710 | if (mips_opts.micromips && dreg == RA) | |
7711 | macro_build (NULL, s, "mj", sreg); | |
7712 | else | |
7713 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7714 | } | |
0a44bf69 | 7715 | else |
252b5132 | 7716 | { |
df58fc94 RS |
7717 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7718 | && mips_cprestore_offset >= 0); | |
7719 | ||
252b5132 RH |
7720 | if (sreg != PIC_CALL_REG) |
7721 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7722 | |
df58fc94 RS |
7723 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7724 | ? "jalrs" : "jalr"); | |
7725 | if (mips_opts.micromips && dreg == RA) | |
7726 | macro_build (NULL, s, "mj", sreg); | |
7727 | else | |
7728 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7729 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7730 | { |
6478892d TS |
7731 | if (mips_cprestore_offset < 0) |
7732 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7733 | else | |
7734 | { | |
90ecf173 | 7735 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7736 | { |
7737 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7738 | /* Quiet this warning. */ | |
7739 | mips_frame_reg_valid = 1; | |
7740 | } | |
90ecf173 | 7741 | if (!mips_cprestore_valid) |
7a621144 DJ |
7742 | { |
7743 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7744 | /* Quiet this warning. */ | |
7745 | mips_cprestore_valid = 1; | |
7746 | } | |
d3fca0b5 MR |
7747 | if (mips_opts.noreorder) |
7748 | macro_build (NULL, "nop", ""); | |
6478892d | 7749 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7750 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7751 | mips_gp_register, |
256ab948 TS |
7752 | mips_frame_reg, |
7753 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7754 | } |
252b5132 RH |
7755 | } |
7756 | } | |
252b5132 | 7757 | |
8fc2e39e | 7758 | break; |
252b5132 | 7759 | |
df58fc94 RS |
7760 | case M_JALS_A: |
7761 | gas_assert (mips_opts.micromips); | |
7762 | jals = 1; | |
7763 | /* Fall through. */ | |
252b5132 RH |
7764 | case M_JAL_A: |
7765 | if (mips_pic == NO_PIC) | |
df58fc94 | 7766 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7767 | else if (mips_pic == SVR4_PIC) |
7768 | { | |
7769 | /* If this is a reference to an external symbol, and we are | |
7770 | using a small GOT, we want | |
7771 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7772 | nop | |
f9419b05 | 7773 | jalr $ra,$25 |
252b5132 RH |
7774 | nop |
7775 | lw $gp,cprestore($sp) | |
7776 | The cprestore value is set using the .cprestore | |
7777 | pseudo-op. If we are using a big GOT, we want | |
7778 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7779 | addu $25,$25,$gp | |
7780 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7781 | nop | |
f9419b05 | 7782 | jalr $ra,$25 |
252b5132 RH |
7783 | nop |
7784 | lw $gp,cprestore($sp) | |
7785 | If the symbol is not external, we want | |
7786 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7787 | nop | |
7788 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7789 | jalr $ra,$25 |
252b5132 | 7790 | nop |
438c16b8 | 7791 | lw $gp,cprestore($sp) |
f5040a92 AO |
7792 | |
7793 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7794 | sequences above, minus nops, unless the symbol is local, | |
7795 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7796 | GOT_DISP. */ | |
438c16b8 | 7797 | if (HAVE_NEWABI) |
252b5132 | 7798 | { |
90ecf173 | 7799 | if (!mips_big_got) |
f5040a92 | 7800 | { |
4d7206a2 | 7801 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7802 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7803 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7804 | mips_gp_register); |
4d7206a2 | 7805 | relax_switch (); |
67c0d1eb RS |
7806 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7807 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7808 | mips_gp_register); |
7809 | relax_end (); | |
f5040a92 AO |
7810 | } |
7811 | else | |
7812 | { | |
4d7206a2 | 7813 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7814 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7815 | BFD_RELOC_MIPS_CALL_HI16); |
7816 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7817 | PIC_CALL_REG, mips_gp_register); | |
7818 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7819 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7820 | PIC_CALL_REG); | |
4d7206a2 | 7821 | relax_switch (); |
67c0d1eb RS |
7822 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7823 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7824 | mips_gp_register); | |
7825 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7826 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 7827 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 7828 | relax_end (); |
f5040a92 | 7829 | } |
684022ea | 7830 | |
df58fc94 | 7831 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
7832 | } |
7833 | else | |
7834 | { | |
4d7206a2 | 7835 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 7836 | if (!mips_big_got) |
438c16b8 | 7837 | { |
67c0d1eb RS |
7838 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7839 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 7840 | mips_gp_register); |
269137b2 | 7841 | load_delay_nop (); |
4d7206a2 | 7842 | relax_switch (); |
438c16b8 | 7843 | } |
252b5132 | 7844 | else |
252b5132 | 7845 | { |
67c0d1eb RS |
7846 | int gpdelay; |
7847 | ||
7848 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 7849 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7850 | BFD_RELOC_MIPS_CALL_HI16); |
7851 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7852 | PIC_CALL_REG, mips_gp_register); | |
7853 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7854 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7855 | PIC_CALL_REG); | |
269137b2 | 7856 | load_delay_nop (); |
4d7206a2 | 7857 | relax_switch (); |
67c0d1eb RS |
7858 | if (gpdelay) |
7859 | macro_build (NULL, "nop", ""); | |
252b5132 | 7860 | } |
67c0d1eb RS |
7861 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7862 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 7863 | mips_gp_register); |
269137b2 | 7864 | load_delay_nop (); |
67c0d1eb RS |
7865 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7866 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 7867 | relax_end (); |
df58fc94 | 7868 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 7869 | |
6478892d TS |
7870 | if (mips_cprestore_offset < 0) |
7871 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7872 | else | |
7873 | { | |
90ecf173 | 7874 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7875 | { |
7876 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7877 | /* Quiet this warning. */ | |
7878 | mips_frame_reg_valid = 1; | |
7879 | } | |
90ecf173 | 7880 | if (!mips_cprestore_valid) |
7a621144 DJ |
7881 | { |
7882 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7883 | /* Quiet this warning. */ | |
7884 | mips_cprestore_valid = 1; | |
7885 | } | |
6478892d | 7886 | if (mips_opts.noreorder) |
67c0d1eb | 7887 | macro_build (NULL, "nop", ""); |
6478892d | 7888 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7889 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7890 | mips_gp_register, |
256ab948 TS |
7891 | mips_frame_reg, |
7892 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7893 | } |
252b5132 RH |
7894 | } |
7895 | } | |
0a44bf69 RS |
7896 | else if (mips_pic == VXWORKS_PIC) |
7897 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
7898 | else |
7899 | abort (); | |
7900 | ||
8fc2e39e | 7901 | break; |
252b5132 | 7902 | |
dec0624d MR |
7903 | case M_ACLR_AB: |
7904 | ab = 1; | |
7905 | case M_ACLR_OB: | |
7906 | s = "aclr"; | |
7907 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7908 | fmt = "\\,~(b)"; | |
7909 | off12 = 1; | |
7910 | goto ld_st; | |
7911 | case M_ASET_AB: | |
7912 | ab = 1; | |
7913 | case M_ASET_OB: | |
7914 | s = "aset"; | |
7915 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7916 | fmt = "\\,~(b)"; | |
7917 | off12 = 1; | |
7918 | goto ld_st; | |
252b5132 | 7919 | case M_LB_AB: |
df58fc94 | 7920 | ab = 1; |
252b5132 | 7921 | s = "lb"; |
df58fc94 | 7922 | fmt = "t,o(b)"; |
252b5132 RH |
7923 | goto ld; |
7924 | case M_LBU_AB: | |
df58fc94 | 7925 | ab = 1; |
252b5132 | 7926 | s = "lbu"; |
df58fc94 | 7927 | fmt = "t,o(b)"; |
252b5132 RH |
7928 | goto ld; |
7929 | case M_LH_AB: | |
df58fc94 | 7930 | ab = 1; |
252b5132 | 7931 | s = "lh"; |
df58fc94 | 7932 | fmt = "t,o(b)"; |
252b5132 RH |
7933 | goto ld; |
7934 | case M_LHU_AB: | |
df58fc94 | 7935 | ab = 1; |
252b5132 | 7936 | s = "lhu"; |
df58fc94 | 7937 | fmt = "t,o(b)"; |
252b5132 RH |
7938 | goto ld; |
7939 | case M_LW_AB: | |
df58fc94 | 7940 | ab = 1; |
252b5132 | 7941 | s = "lw"; |
df58fc94 | 7942 | fmt = "t,o(b)"; |
252b5132 RH |
7943 | goto ld; |
7944 | case M_LWC0_AB: | |
df58fc94 RS |
7945 | ab = 1; |
7946 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7947 | s = "lwc0"; |
df58fc94 | 7948 | fmt = "E,o(b)"; |
bdaaa2e1 | 7949 | /* Itbl support may require additional care here. */ |
252b5132 | 7950 | coproc = 1; |
df58fc94 | 7951 | goto ld_st; |
252b5132 | 7952 | case M_LWC1_AB: |
df58fc94 | 7953 | ab = 1; |
252b5132 | 7954 | s = "lwc1"; |
df58fc94 | 7955 | fmt = "T,o(b)"; |
bdaaa2e1 | 7956 | /* Itbl support may require additional care here. */ |
252b5132 | 7957 | coproc = 1; |
df58fc94 | 7958 | goto ld_st; |
252b5132 | 7959 | case M_LWC2_AB: |
df58fc94 RS |
7960 | ab = 1; |
7961 | case M_LWC2_OB: | |
252b5132 | 7962 | s = "lwc2"; |
df58fc94 RS |
7963 | fmt = COP12_FMT; |
7964 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7965 | /* Itbl support may require additional care here. */ |
252b5132 | 7966 | coproc = 1; |
df58fc94 | 7967 | goto ld_st; |
252b5132 | 7968 | case M_LWC3_AB: |
df58fc94 RS |
7969 | ab = 1; |
7970 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7971 | s = "lwc3"; |
df58fc94 | 7972 | fmt = "E,o(b)"; |
bdaaa2e1 | 7973 | /* Itbl support may require additional care here. */ |
252b5132 | 7974 | coproc = 1; |
df58fc94 | 7975 | goto ld_st; |
252b5132 | 7976 | case M_LWL_AB: |
df58fc94 RS |
7977 | ab = 1; |
7978 | case M_LWL_OB: | |
252b5132 | 7979 | s = "lwl"; |
df58fc94 RS |
7980 | fmt = MEM12_FMT; |
7981 | off12 = mips_opts.micromips; | |
7982 | goto ld_st; | |
252b5132 | 7983 | case M_LWR_AB: |
df58fc94 RS |
7984 | ab = 1; |
7985 | case M_LWR_OB: | |
252b5132 | 7986 | s = "lwr"; |
df58fc94 RS |
7987 | fmt = MEM12_FMT; |
7988 | off12 = mips_opts.micromips; | |
7989 | goto ld_st; | |
252b5132 | 7990 | case M_LDC1_AB: |
df58fc94 | 7991 | ab = 1; |
252b5132 | 7992 | s = "ldc1"; |
df58fc94 | 7993 | fmt = "T,o(b)"; |
bdaaa2e1 | 7994 | /* Itbl support may require additional care here. */ |
252b5132 | 7995 | coproc = 1; |
df58fc94 | 7996 | goto ld_st; |
252b5132 | 7997 | case M_LDC2_AB: |
df58fc94 RS |
7998 | ab = 1; |
7999 | case M_LDC2_OB: | |
252b5132 | 8000 | s = "ldc2"; |
df58fc94 RS |
8001 | fmt = COP12_FMT; |
8002 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8003 | /* Itbl support may require additional care here. */ |
252b5132 | 8004 | coproc = 1; |
df58fc94 | 8005 | goto ld_st; |
252b5132 | 8006 | case M_LDC3_AB: |
df58fc94 | 8007 | ab = 1; |
252b5132 | 8008 | s = "ldc3"; |
df58fc94 | 8009 | fmt = "E,o(b)"; |
bdaaa2e1 | 8010 | /* Itbl support may require additional care here. */ |
252b5132 | 8011 | coproc = 1; |
df58fc94 | 8012 | goto ld_st; |
252b5132 | 8013 | case M_LDL_AB: |
df58fc94 RS |
8014 | ab = 1; |
8015 | case M_LDL_OB: | |
252b5132 | 8016 | s = "ldl"; |
df58fc94 RS |
8017 | fmt = MEM12_FMT; |
8018 | off12 = mips_opts.micromips; | |
8019 | goto ld_st; | |
252b5132 | 8020 | case M_LDR_AB: |
df58fc94 RS |
8021 | ab = 1; |
8022 | case M_LDR_OB: | |
252b5132 | 8023 | s = "ldr"; |
df58fc94 RS |
8024 | fmt = MEM12_FMT; |
8025 | off12 = mips_opts.micromips; | |
8026 | goto ld_st; | |
252b5132 | 8027 | case M_LL_AB: |
df58fc94 RS |
8028 | ab = 1; |
8029 | case M_LL_OB: | |
252b5132 | 8030 | s = "ll"; |
df58fc94 RS |
8031 | fmt = MEM12_FMT; |
8032 | off12 = mips_opts.micromips; | |
252b5132 RH |
8033 | goto ld; |
8034 | case M_LLD_AB: | |
df58fc94 RS |
8035 | ab = 1; |
8036 | case M_LLD_OB: | |
252b5132 | 8037 | s = "lld"; |
df58fc94 RS |
8038 | fmt = MEM12_FMT; |
8039 | off12 = mips_opts.micromips; | |
252b5132 RH |
8040 | goto ld; |
8041 | case M_LWU_AB: | |
df58fc94 RS |
8042 | ab = 1; |
8043 | case M_LWU_OB: | |
252b5132 | 8044 | s = "lwu"; |
df58fc94 RS |
8045 | fmt = MEM12_FMT; |
8046 | off12 = mips_opts.micromips; | |
8047 | goto ld; | |
8048 | case M_LWP_AB: | |
8049 | ab = 1; | |
8050 | case M_LWP_OB: | |
8051 | gas_assert (mips_opts.micromips); | |
8052 | s = "lwp"; | |
8053 | fmt = "t,~(b)"; | |
8054 | off12 = 1; | |
8055 | lp = 1; | |
8056 | goto ld; | |
8057 | case M_LDP_AB: | |
8058 | ab = 1; | |
8059 | case M_LDP_OB: | |
8060 | gas_assert (mips_opts.micromips); | |
8061 | s = "ldp"; | |
8062 | fmt = "t,~(b)"; | |
8063 | off12 = 1; | |
8064 | lp = 1; | |
8065 | goto ld; | |
8066 | case M_LWM_AB: | |
8067 | ab = 1; | |
8068 | case M_LWM_OB: | |
8069 | gas_assert (mips_opts.micromips); | |
8070 | s = "lwm"; | |
8071 | fmt = "n,~(b)"; | |
8072 | off12 = 1; | |
8073 | goto ld_st; | |
8074 | case M_LDM_AB: | |
8075 | ab = 1; | |
8076 | case M_LDM_OB: | |
8077 | gas_assert (mips_opts.micromips); | |
8078 | s = "ldm"; | |
8079 | fmt = "n,~(b)"; | |
8080 | off12 = 1; | |
8081 | goto ld_st; | |
8082 | ||
252b5132 | 8083 | ld: |
df58fc94 RS |
8084 | if (breg == treg + lp) |
8085 | goto ld_st; | |
252b5132 | 8086 | else |
df58fc94 RS |
8087 | tempreg = treg + lp; |
8088 | goto ld_noat; | |
8089 | ||
252b5132 | 8090 | case M_SB_AB: |
df58fc94 | 8091 | ab = 1; |
252b5132 | 8092 | s = "sb"; |
df58fc94 RS |
8093 | fmt = "t,o(b)"; |
8094 | goto ld_st; | |
252b5132 | 8095 | case M_SH_AB: |
df58fc94 | 8096 | ab = 1; |
252b5132 | 8097 | s = "sh"; |
df58fc94 RS |
8098 | fmt = "t,o(b)"; |
8099 | goto ld_st; | |
252b5132 | 8100 | case M_SW_AB: |
df58fc94 | 8101 | ab = 1; |
252b5132 | 8102 | s = "sw"; |
df58fc94 RS |
8103 | fmt = "t,o(b)"; |
8104 | goto ld_st; | |
252b5132 | 8105 | case M_SWC0_AB: |
df58fc94 RS |
8106 | ab = 1; |
8107 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8108 | s = "swc0"; |
df58fc94 | 8109 | fmt = "E,o(b)"; |
bdaaa2e1 | 8110 | /* Itbl support may require additional care here. */ |
252b5132 | 8111 | coproc = 1; |
df58fc94 | 8112 | goto ld_st; |
252b5132 | 8113 | case M_SWC1_AB: |
df58fc94 | 8114 | ab = 1; |
252b5132 | 8115 | s = "swc1"; |
df58fc94 | 8116 | fmt = "T,o(b)"; |
bdaaa2e1 | 8117 | /* Itbl support may require additional care here. */ |
252b5132 | 8118 | coproc = 1; |
df58fc94 | 8119 | goto ld_st; |
252b5132 | 8120 | case M_SWC2_AB: |
df58fc94 RS |
8121 | ab = 1; |
8122 | case M_SWC2_OB: | |
252b5132 | 8123 | s = "swc2"; |
df58fc94 RS |
8124 | fmt = COP12_FMT; |
8125 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8126 | /* Itbl support may require additional care here. */ |
252b5132 | 8127 | coproc = 1; |
df58fc94 | 8128 | goto ld_st; |
252b5132 | 8129 | case M_SWC3_AB: |
df58fc94 RS |
8130 | ab = 1; |
8131 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8132 | s = "swc3"; |
df58fc94 | 8133 | fmt = "E,o(b)"; |
bdaaa2e1 | 8134 | /* Itbl support may require additional care here. */ |
252b5132 | 8135 | coproc = 1; |
df58fc94 | 8136 | goto ld_st; |
252b5132 | 8137 | case M_SWL_AB: |
df58fc94 RS |
8138 | ab = 1; |
8139 | case M_SWL_OB: | |
252b5132 | 8140 | s = "swl"; |
df58fc94 RS |
8141 | fmt = MEM12_FMT; |
8142 | off12 = mips_opts.micromips; | |
8143 | goto ld_st; | |
252b5132 | 8144 | case M_SWR_AB: |
df58fc94 RS |
8145 | ab = 1; |
8146 | case M_SWR_OB: | |
252b5132 | 8147 | s = "swr"; |
df58fc94 RS |
8148 | fmt = MEM12_FMT; |
8149 | off12 = mips_opts.micromips; | |
8150 | goto ld_st; | |
252b5132 | 8151 | case M_SC_AB: |
df58fc94 RS |
8152 | ab = 1; |
8153 | case M_SC_OB: | |
252b5132 | 8154 | s = "sc"; |
df58fc94 RS |
8155 | fmt = MEM12_FMT; |
8156 | off12 = mips_opts.micromips; | |
8157 | goto ld_st; | |
252b5132 | 8158 | case M_SCD_AB: |
df58fc94 RS |
8159 | ab = 1; |
8160 | case M_SCD_OB: | |
252b5132 | 8161 | s = "scd"; |
df58fc94 RS |
8162 | fmt = MEM12_FMT; |
8163 | off12 = mips_opts.micromips; | |
8164 | goto ld_st; | |
d43b4baf | 8165 | case M_CACHE_AB: |
df58fc94 RS |
8166 | ab = 1; |
8167 | case M_CACHE_OB: | |
d43b4baf | 8168 | s = "cache"; |
df58fc94 RS |
8169 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8170 | off12 = mips_opts.micromips; | |
8171 | goto ld_st; | |
3eebd5eb | 8172 | case M_PREF_AB: |
df58fc94 RS |
8173 | ab = 1; |
8174 | case M_PREF_OB: | |
3eebd5eb | 8175 | s = "pref"; |
df58fc94 RS |
8176 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8177 | off12 = mips_opts.micromips; | |
8178 | goto ld_st; | |
252b5132 | 8179 | case M_SDC1_AB: |
df58fc94 | 8180 | ab = 1; |
252b5132 | 8181 | s = "sdc1"; |
df58fc94 | 8182 | fmt = "T,o(b)"; |
252b5132 | 8183 | coproc = 1; |
bdaaa2e1 | 8184 | /* Itbl support may require additional care here. */ |
df58fc94 | 8185 | goto ld_st; |
252b5132 | 8186 | case M_SDC2_AB: |
df58fc94 RS |
8187 | ab = 1; |
8188 | case M_SDC2_OB: | |
252b5132 | 8189 | s = "sdc2"; |
df58fc94 RS |
8190 | fmt = COP12_FMT; |
8191 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8192 | /* Itbl support may require additional care here. */ |
252b5132 | 8193 | coproc = 1; |
df58fc94 | 8194 | goto ld_st; |
252b5132 | 8195 | case M_SDC3_AB: |
df58fc94 RS |
8196 | ab = 1; |
8197 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8198 | s = "sdc3"; |
df58fc94 | 8199 | fmt = "E,o(b)"; |
bdaaa2e1 | 8200 | /* Itbl support may require additional care here. */ |
252b5132 | 8201 | coproc = 1; |
df58fc94 | 8202 | goto ld_st; |
252b5132 | 8203 | case M_SDL_AB: |
df58fc94 RS |
8204 | ab = 1; |
8205 | case M_SDL_OB: | |
252b5132 | 8206 | s = "sdl"; |
df58fc94 RS |
8207 | fmt = MEM12_FMT; |
8208 | off12 = mips_opts.micromips; | |
8209 | goto ld_st; | |
252b5132 | 8210 | case M_SDR_AB: |
df58fc94 RS |
8211 | ab = 1; |
8212 | case M_SDR_OB: | |
252b5132 | 8213 | s = "sdr"; |
df58fc94 RS |
8214 | fmt = MEM12_FMT; |
8215 | off12 = mips_opts.micromips; | |
8216 | goto ld_st; | |
8217 | case M_SWP_AB: | |
8218 | ab = 1; | |
8219 | case M_SWP_OB: | |
8220 | gas_assert (mips_opts.micromips); | |
8221 | s = "swp"; | |
8222 | fmt = "t,~(b)"; | |
8223 | off12 = 1; | |
8224 | goto ld_st; | |
8225 | case M_SDP_AB: | |
8226 | ab = 1; | |
8227 | case M_SDP_OB: | |
8228 | gas_assert (mips_opts.micromips); | |
8229 | s = "sdp"; | |
8230 | fmt = "t,~(b)"; | |
8231 | off12 = 1; | |
8232 | goto ld_st; | |
8233 | case M_SWM_AB: | |
8234 | ab = 1; | |
8235 | case M_SWM_OB: | |
8236 | gas_assert (mips_opts.micromips); | |
8237 | s = "swm"; | |
8238 | fmt = "n,~(b)"; | |
8239 | off12 = 1; | |
8240 | goto ld_st; | |
8241 | case M_SDM_AB: | |
8242 | ab = 1; | |
8243 | case M_SDM_OB: | |
8244 | gas_assert (mips_opts.micromips); | |
8245 | s = "sdm"; | |
8246 | fmt = "n,~(b)"; | |
8247 | off12 = 1; | |
8248 | ||
8249 | ld_st: | |
8fc2e39e TS |
8250 | tempreg = AT; |
8251 | used_at = 1; | |
df58fc94 | 8252 | ld_noat: |
b19e8a9b AN |
8253 | if (coproc |
8254 | && NO_ISA_COP (mips_opts.arch) | |
8255 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
8256 | { | |
f71d0d44 | 8257 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
8258 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
8259 | break; | |
8260 | } | |
8261 | ||
252b5132 RH |
8262 | if (offset_expr.X_op != O_constant |
8263 | && offset_expr.X_op != O_symbol) | |
8264 | { | |
f71d0d44 | 8265 | as_bad (_("Expression too complex")); |
252b5132 RH |
8266 | offset_expr.X_op = O_constant; |
8267 | } | |
8268 | ||
2051e8c4 MR |
8269 | if (HAVE_32BIT_ADDRESSES |
8270 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8271 | { |
8272 | char value [32]; | |
8273 | ||
8274 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8275 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8276 | } |
2051e8c4 | 8277 | |
252b5132 RH |
8278 | /* A constant expression in PIC code can be handled just as it |
8279 | is in non PIC code. */ | |
aed1a261 RS |
8280 | if (offset_expr.X_op == O_constant) |
8281 | { | |
df58fc94 RS |
8282 | int hipart = 0; |
8283 | ||
842f8b2a | 8284 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8285 | normalize_address_expr (&expr1); |
df58fc94 | 8286 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8287 | { |
8288 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8289 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8290 | hipart = 1; |
8291 | } | |
8292 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8293 | { | |
8294 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8295 | & ~(bfd_vma) 0xfff); | |
8296 | hipart = 1; | |
8297 | } | |
8298 | if (hipart) | |
8299 | { | |
842f8b2a MR |
8300 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8301 | if (breg != 0) | |
8302 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8303 | tempreg, tempreg, breg); | |
8304 | breg = tempreg; | |
8305 | } | |
dd6a37e7 AP |
8306 | if (off0) |
8307 | { | |
8308 | if (offset_expr.X_add_number == 0) | |
8309 | tempreg = breg; | |
8310 | else | |
8311 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, | |
8312 | "t,r,j", tempreg, breg, BFD_RELOC_LO16); | |
8313 | macro_build (NULL, s, fmt, treg, tempreg); | |
8314 | } | |
8315 | else if (!off12) | |
df58fc94 RS |
8316 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); |
8317 | else | |
8318 | macro_build (NULL, s, fmt, | |
8319 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8320 | } | |
dd6a37e7 | 8321 | else if (off12 || off0) |
df58fc94 | 8322 | { |
dd6a37e7 AP |
8323 | /* A 12-bit or 0-bit offset field is too narrow to be used |
8324 | for a low-part relocation, so load the whole address into | |
8325 | the auxillary register. In the case of "A(b)" addresses, | |
8326 | we first load absolute address "A" into the register and | |
8327 | then add base register "b". In the case of "o(b)" addresses, | |
8328 | we simply need to add 16-bit offset "o" to base register "b", and | |
df58fc94 RS |
8329 | offset_reloc already contains the relocations associated |
8330 | with "o". */ | |
8331 | if (ab) | |
8332 | { | |
8333 | load_address (tempreg, &offset_expr, &used_at); | |
8334 | if (breg != 0) | |
8335 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8336 | tempreg, tempreg, breg); | |
8337 | } | |
8338 | else | |
8339 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8340 | tempreg, breg, -1, | |
8341 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8342 | expr1.X_add_number = 0; | |
dd6a37e7 AP |
8343 | if (off0) |
8344 | macro_build (NULL, s, fmt, treg, tempreg); | |
8345 | else | |
8346 | macro_build (NULL, s, fmt, | |
8347 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8348 | } |
8349 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8350 | { |
8351 | /* If this is a reference to a GP relative symbol, and there | |
8352 | is no base register, we want | |
cdf6fd85 | 8353 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8354 | Otherwise, if there is no base register, we want |
8355 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8356 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8357 | If we have a constant, we need two instructions anyhow, | |
8358 | so we always use the latter form. | |
8359 | ||
8360 | If we have a base register, and this is a reference to a | |
8361 | GP relative symbol, we want | |
8362 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8363 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8364 | Otherwise we want |
8365 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8366 | addu $tempreg,$tempreg,$breg | |
8367 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8368 | With a constant we always use the latter case. |
76b3015f | 8369 | |
d6bc6245 TS |
8370 | With 64bit address space and no base register and $at usable, |
8371 | we want | |
8372 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8373 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8374 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8375 | dsll32 $tempreg,0 | |
8376 | daddu $tempreg,$at | |
8377 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8378 | If we have a base register, we want | |
8379 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8380 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8381 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8382 | daddu $at,$breg | |
8383 | dsll32 $tempreg,0 | |
8384 | daddu $tempreg,$at | |
8385 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8386 | ||
8387 | Without $at we can't generate the optimal path for superscalar | |
8388 | processors here since this would require two temporary registers. | |
8389 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8390 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8391 | dsll $tempreg,16 | |
8392 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8393 | dsll $tempreg,16 | |
8394 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8395 | If we have a base register, we want | |
8396 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8397 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8398 | dsll $tempreg,16 | |
8399 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8400 | dsll $tempreg,16 | |
8401 | daddu $tempreg,$tempreg,$breg | |
8402 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8403 | |
6caf9ef4 | 8404 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8405 | the same sequence as in 32bit address space. */ |
8406 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8407 | { |
aed1a261 | 8408 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8409 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8410 | { | |
8411 | relax_start (offset_expr.X_add_symbol); | |
8412 | if (breg == 0) | |
8413 | { | |
8414 | macro_build (&offset_expr, s, fmt, treg, | |
8415 | BFD_RELOC_GPREL16, mips_gp_register); | |
8416 | } | |
8417 | else | |
8418 | { | |
8419 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8420 | tempreg, breg, mips_gp_register); | |
8421 | macro_build (&offset_expr, s, fmt, treg, | |
8422 | BFD_RELOC_GPREL16, tempreg); | |
8423 | } | |
8424 | relax_switch (); | |
8425 | } | |
d6bc6245 | 8426 | |
741fe287 | 8427 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8428 | { |
df58fc94 | 8429 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8430 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8431 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8432 | BFD_RELOC_HI16_S); |
8433 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8434 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8435 | if (breg != 0) |
67c0d1eb | 8436 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8437 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8438 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8439 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8440 | tempreg); | |
d6bc6245 TS |
8441 | used_at = 1; |
8442 | } | |
8443 | else | |
8444 | { | |
df58fc94 | 8445 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8446 | BFD_RELOC_MIPS_HIGHEST); |
8447 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8448 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8449 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8450 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8451 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8452 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8453 | if (breg != 0) |
67c0d1eb | 8454 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8455 | tempreg, tempreg, breg); |
67c0d1eb | 8456 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8457 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8458 | } |
6caf9ef4 TS |
8459 | |
8460 | if (mips_relax.sequence) | |
8461 | relax_end (); | |
8fc2e39e | 8462 | break; |
d6bc6245 | 8463 | } |
256ab948 | 8464 | |
252b5132 RH |
8465 | if (breg == 0) |
8466 | { | |
67c0d1eb | 8467 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8468 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8469 | { |
4d7206a2 | 8470 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8471 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8472 | mips_gp_register); | |
4d7206a2 | 8473 | relax_switch (); |
252b5132 | 8474 | } |
67c0d1eb RS |
8475 | macro_build_lui (&offset_expr, tempreg); |
8476 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8477 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8478 | if (mips_relax.sequence) |
8479 | relax_end (); | |
252b5132 RH |
8480 | } |
8481 | else | |
8482 | { | |
67c0d1eb | 8483 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8484 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8485 | { |
4d7206a2 | 8486 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8487 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8488 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8489 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8490 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8491 | relax_switch (); |
252b5132 | 8492 | } |
67c0d1eb RS |
8493 | macro_build_lui (&offset_expr, tempreg); |
8494 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8495 | tempreg, tempreg, breg); |
67c0d1eb | 8496 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8497 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8498 | if (mips_relax.sequence) |
8499 | relax_end (); | |
252b5132 RH |
8500 | } |
8501 | } | |
0a44bf69 | 8502 | else if (!mips_big_got) |
252b5132 | 8503 | { |
ed6fb7bd | 8504 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8505 | |
252b5132 RH |
8506 | /* If this is a reference to an external symbol, we want |
8507 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8508 | nop | |
8509 | <op> $treg,0($tempreg) | |
8510 | Otherwise we want | |
8511 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8512 | nop | |
8513 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8514 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8515 | |
8516 | For NewABI, we want | |
8517 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8518 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8519 | ||
252b5132 RH |
8520 | If there is a base register, we add it to $tempreg before |
8521 | the <op>. If there is a constant, we stick it in the | |
8522 | <op> instruction. We don't handle constants larger than | |
8523 | 16 bits, because we have no way to load the upper 16 bits | |
8524 | (actually, we could handle them for the subset of cases | |
8525 | in which we are not using $at). */ | |
9c2799c2 | 8526 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8527 | if (HAVE_NEWABI) |
8528 | { | |
67c0d1eb RS |
8529 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8530 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8531 | if (breg != 0) |
67c0d1eb | 8532 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8533 | tempreg, tempreg, breg); |
67c0d1eb | 8534 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8535 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8536 | break; |
8537 | } | |
252b5132 RH |
8538 | expr1.X_add_number = offset_expr.X_add_number; |
8539 | offset_expr.X_add_number = 0; | |
8540 | if (expr1.X_add_number < -0x8000 | |
8541 | || expr1.X_add_number >= 0x8000) | |
8542 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8543 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8544 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8545 | load_delay_nop (); |
4d7206a2 RS |
8546 | relax_start (offset_expr.X_add_symbol); |
8547 | relax_switch (); | |
67c0d1eb RS |
8548 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8549 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8550 | relax_end (); |
252b5132 | 8551 | if (breg != 0) |
67c0d1eb | 8552 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8553 | tempreg, tempreg, breg); |
67c0d1eb | 8554 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8555 | } |
0a44bf69 | 8556 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8557 | { |
67c0d1eb | 8558 | int gpdelay; |
252b5132 RH |
8559 | |
8560 | /* If this is a reference to an external symbol, we want | |
8561 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8562 | addu $tempreg,$tempreg,$gp | |
8563 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8564 | <op> $treg,0($tempreg) | |
8565 | Otherwise we want | |
8566 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8567 | nop | |
8568 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8569 | <op> $treg,0($tempreg) | |
8570 | If there is a base register, we add it to $tempreg before | |
8571 | the <op>. If there is a constant, we stick it in the | |
8572 | <op> instruction. We don't handle constants larger than | |
8573 | 16 bits, because we have no way to load the upper 16 bits | |
8574 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8575 | in which we are not using $at). */ |
9c2799c2 | 8576 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8577 | expr1.X_add_number = offset_expr.X_add_number; |
8578 | offset_expr.X_add_number = 0; | |
8579 | if (expr1.X_add_number < -0x8000 | |
8580 | || expr1.X_add_number >= 0x8000) | |
8581 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8582 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8583 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8584 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8585 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8586 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8587 | mips_gp_register); | |
8588 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8589 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8590 | relax_switch (); |
67c0d1eb RS |
8591 | if (gpdelay) |
8592 | macro_build (NULL, "nop", ""); | |
8593 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8594 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8595 | load_delay_nop (); |
67c0d1eb RS |
8596 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8597 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8598 | relax_end (); |
8599 | ||
252b5132 | 8600 | if (breg != 0) |
67c0d1eb | 8601 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8602 | tempreg, tempreg, breg); |
67c0d1eb | 8603 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8604 | } |
0a44bf69 | 8605 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8606 | { |
f5040a92 AO |
8607 | /* If this is a reference to an external symbol, we want |
8608 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8609 | add $tempreg,$tempreg,$gp | |
8610 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8611 | <op> $treg,<ofst>($tempreg) | |
8612 | Otherwise, for local symbols, we want: | |
8613 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8614 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8615 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8616 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8617 | offset_expr.X_add_number = 0; |
8618 | if (expr1.X_add_number < -0x8000 | |
8619 | || expr1.X_add_number >= 0x8000) | |
8620 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8621 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8622 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8623 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8624 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8625 | mips_gp_register); | |
8626 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8627 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8628 | if (breg != 0) |
67c0d1eb | 8629 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8630 | tempreg, tempreg, breg); |
67c0d1eb | 8631 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8632 | |
4d7206a2 | 8633 | relax_switch (); |
f5040a92 | 8634 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8635 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8636 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8637 | if (breg != 0) |
67c0d1eb | 8638 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8639 | tempreg, tempreg, breg); |
67c0d1eb | 8640 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8641 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8642 | relax_end (); |
f5040a92 | 8643 | } |
252b5132 RH |
8644 | else |
8645 | abort (); | |
8646 | ||
252b5132 RH |
8647 | break; |
8648 | ||
8649 | case M_LI: | |
8650 | case M_LI_S: | |
67c0d1eb | 8651 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8652 | break; |
252b5132 RH |
8653 | |
8654 | case M_DLI: | |
67c0d1eb | 8655 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8656 | break; |
252b5132 RH |
8657 | |
8658 | case M_LI_SS: | |
8659 | if (imm_expr.X_op == O_constant) | |
8660 | { | |
8fc2e39e | 8661 | used_at = 1; |
67c0d1eb RS |
8662 | load_register (AT, &imm_expr, 0); |
8663 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8664 | break; |
8665 | } | |
8666 | else | |
8667 | { | |
9c2799c2 | 8668 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8669 | && strcmp (segment_name (S_GET_SEGMENT |
8670 | (offset_expr.X_add_symbol)), | |
8671 | ".lit4") == 0 | |
8672 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8673 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8674 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8675 | break; |
252b5132 RH |
8676 | } |
8677 | ||
8678 | case M_LI_D: | |
ca4e0257 RS |
8679 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8680 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8681 | order 32 bits of the value and the low order 32 bits are either | |
8682 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8683 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8684 | { | |
ca4e0257 | 8685 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8686 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8687 | else |
8688 | { | |
8689 | int hreg, lreg; | |
8690 | ||
8691 | if (target_big_endian) | |
8692 | { | |
8693 | hreg = treg; | |
8694 | lreg = treg + 1; | |
8695 | } | |
8696 | else | |
8697 | { | |
8698 | hreg = treg + 1; | |
8699 | lreg = treg; | |
8700 | } | |
8701 | ||
8702 | if (hreg <= 31) | |
67c0d1eb | 8703 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8704 | if (lreg <= 31) |
8705 | { | |
8706 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8707 | move_register (lreg, 0); |
252b5132 RH |
8708 | else |
8709 | { | |
9c2799c2 | 8710 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8711 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8712 | } |
8713 | } | |
8714 | } | |
8fc2e39e | 8715 | break; |
252b5132 RH |
8716 | } |
8717 | ||
8718 | /* We know that sym is in the .rdata section. First we get the | |
8719 | upper 16 bits of the address. */ | |
8720 | if (mips_pic == NO_PIC) | |
8721 | { | |
67c0d1eb | 8722 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8723 | used_at = 1; |
252b5132 | 8724 | } |
0a44bf69 | 8725 | else |
252b5132 | 8726 | { |
67c0d1eb RS |
8727 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8728 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8729 | used_at = 1; |
252b5132 | 8730 | } |
bdaaa2e1 | 8731 | |
252b5132 | 8732 | /* Now we load the register(s). */ |
ca4e0257 | 8733 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8734 | { |
8735 | used_at = 1; | |
8736 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8737 | } | |
252b5132 RH |
8738 | else |
8739 | { | |
8fc2e39e | 8740 | used_at = 1; |
67c0d1eb | 8741 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8742 | if (treg != RA) |
252b5132 RH |
8743 | { |
8744 | /* FIXME: How in the world do we deal with the possible | |
8745 | overflow here? */ | |
8746 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8747 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8748 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8749 | } |
8750 | } | |
252b5132 RH |
8751 | break; |
8752 | ||
8753 | case M_LI_DD: | |
ca4e0257 RS |
8754 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8755 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8756 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8757 | the value and the low order 32 bits are either zero or in | |
8758 | OFFSET_EXPR. */ | |
252b5132 RH |
8759 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8760 | { | |
8fc2e39e | 8761 | used_at = 1; |
67c0d1eb | 8762 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8763 | if (HAVE_64BIT_FPRS) |
8764 | { | |
9c2799c2 | 8765 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8766 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8767 | } |
252b5132 RH |
8768 | else |
8769 | { | |
67c0d1eb | 8770 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8771 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8772 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8773 | else |
8774 | { | |
9c2799c2 | 8775 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8776 | load_register (AT, &offset_expr, 0); |
8777 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8778 | } |
8779 | } | |
8780 | break; | |
8781 | } | |
8782 | ||
9c2799c2 | 8783 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8784 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8785 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8786 | if (strcmp (s, ".lit8") == 0) | |
8787 | { | |
df58fc94 | 8788 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8789 | { |
67c0d1eb | 8790 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8791 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8792 | break; |
252b5132 | 8793 | } |
c9914766 | 8794 | breg = mips_gp_register; |
252b5132 RH |
8795 | r = BFD_RELOC_MIPS_LITERAL; |
8796 | goto dob; | |
8797 | } | |
8798 | else | |
8799 | { | |
9c2799c2 | 8800 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8801 | used_at = 1; |
0a44bf69 | 8802 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8803 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8804 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8805 | else |
8806 | { | |
8807 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8808 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8809 | } |
bdaaa2e1 | 8810 | |
df58fc94 | 8811 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8812 | { |
67c0d1eb RS |
8813 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8814 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8815 | break; |
8816 | } | |
8817 | breg = AT; | |
8818 | r = BFD_RELOC_LO16; | |
8819 | goto dob; | |
8820 | } | |
8821 | ||
8822 | case M_L_DOB: | |
252b5132 RH |
8823 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8824 | to adjust when loading from memory. */ | |
8825 | r = BFD_RELOC_LO16; | |
8826 | dob: | |
df58fc94 | 8827 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 8828 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 8829 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8830 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8831 | /* FIXME: A possible overflow which I don't know how to deal |
8832 | with. */ | |
8833 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8834 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8835 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
8836 | break; |
8837 | ||
c4a68bea | 8838 | case M_S_DOB: |
df58fc94 | 8839 | gas_assert (!mips_opts.micromips); |
c4a68bea MR |
8840 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8841 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
8842 | to adjust when storing to memory. */ | |
8843 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8844 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
8845 | offset_expr.X_add_number += 4; | |
8846 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8847 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8848 | break; | |
8849 | ||
252b5132 | 8850 | case M_L_DAB: |
df58fc94 | 8851 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
8852 | /* |
8853 | * The MIPS assembler seems to check for X_add_number not | |
8854 | * being double aligned and generating: | |
8855 | * lui at,%hi(foo+1) | |
8856 | * addu at,at,v1 | |
8857 | * addiu at,at,%lo(foo+1) | |
8858 | * lwc1 f2,0(at) | |
8859 | * lwc1 f3,4(at) | |
8860 | * But, the resulting address is the same after relocation so why | |
8861 | * generate the extra instruction? | |
8862 | */ | |
bdaaa2e1 | 8863 | /* Itbl support may require additional care here. */ |
252b5132 | 8864 | coproc = 1; |
df58fc94 | 8865 | fmt = "T,o(b)"; |
e7af610e | 8866 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8867 | { |
8868 | s = "ldc1"; | |
df58fc94 | 8869 | goto ld_st; |
252b5132 | 8870 | } |
252b5132 | 8871 | s = "lwc1"; |
252b5132 RH |
8872 | goto ldd_std; |
8873 | ||
8874 | case M_S_DAB: | |
df58fc94 RS |
8875 | gas_assert (!mips_opts.micromips); |
8876 | /* Itbl support may require additional care here. */ | |
8877 | coproc = 1; | |
8878 | fmt = "T,o(b)"; | |
e7af610e | 8879 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8880 | { |
8881 | s = "sdc1"; | |
df58fc94 | 8882 | goto ld_st; |
252b5132 | 8883 | } |
252b5132 | 8884 | s = "swc1"; |
252b5132 RH |
8885 | goto ldd_std; |
8886 | ||
8887 | case M_LD_AB: | |
df58fc94 | 8888 | fmt = "t,o(b)"; |
ca4e0257 | 8889 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8890 | { |
8891 | s = "ld"; | |
8892 | goto ld; | |
8893 | } | |
252b5132 | 8894 | s = "lw"; |
252b5132 RH |
8895 | goto ldd_std; |
8896 | ||
8897 | case M_SD_AB: | |
df58fc94 | 8898 | fmt = "t,o(b)"; |
ca4e0257 | 8899 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8900 | { |
8901 | s = "sd"; | |
df58fc94 | 8902 | goto ld_st; |
252b5132 | 8903 | } |
252b5132 | 8904 | s = "sw"; |
252b5132 RH |
8905 | |
8906 | ldd_std: | |
8907 | if (offset_expr.X_op != O_symbol | |
8908 | && offset_expr.X_op != O_constant) | |
8909 | { | |
f71d0d44 | 8910 | as_bad (_("Expression too complex")); |
252b5132 RH |
8911 | offset_expr.X_op = O_constant; |
8912 | } | |
8913 | ||
2051e8c4 MR |
8914 | if (HAVE_32BIT_ADDRESSES |
8915 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8916 | { |
8917 | char value [32]; | |
8918 | ||
8919 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8920 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8921 | } |
2051e8c4 | 8922 | |
252b5132 RH |
8923 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8924 | to adjust when loading from memory. We set coproc if we must | |
8925 | load $fn+1 first. */ | |
bdaaa2e1 | 8926 | /* Itbl support may require additional care here. */ |
90ecf173 | 8927 | if (!target_big_endian) |
252b5132 RH |
8928 | coproc = 0; |
8929 | ||
90ecf173 | 8930 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
8931 | { |
8932 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
8933 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
8934 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8935 | If we have a base register, we use this |
8936 | addu $at,$breg,$gp | |
cdf6fd85 TS |
8937 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
8938 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8939 | If this is not a GP relative symbol, we want |
8940 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8941 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8942 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8943 | If there is a base register, we add it to $at after the | |
8944 | lui instruction. If there is a constant, we always use | |
8945 | the last case. */ | |
39a59cf8 MR |
8946 | if (offset_expr.X_op == O_symbol |
8947 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 8948 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8949 | { |
4d7206a2 | 8950 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
8951 | if (breg == 0) |
8952 | { | |
c9914766 | 8953 | tempreg = mips_gp_register; |
252b5132 RH |
8954 | } |
8955 | else | |
8956 | { | |
67c0d1eb | 8957 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8958 | AT, breg, mips_gp_register); |
252b5132 | 8959 | tempreg = AT; |
252b5132 RH |
8960 | used_at = 1; |
8961 | } | |
8962 | ||
beae10d5 | 8963 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8964 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8965 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8966 | offset_expr.X_add_number += 4; |
8967 | ||
8968 | /* Set mips_optimize to 2 to avoid inserting an | |
8969 | undesired nop. */ | |
8970 | hold_mips_optimize = mips_optimize; | |
8971 | mips_optimize = 2; | |
beae10d5 | 8972 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8973 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8974 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8975 | mips_optimize = hold_mips_optimize; |
8976 | ||
4d7206a2 | 8977 | relax_switch (); |
252b5132 | 8978 | |
0970e49e | 8979 | offset_expr.X_add_number -= 4; |
252b5132 | 8980 | } |
8fc2e39e | 8981 | used_at = 1; |
67c0d1eb | 8982 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8983 | if (breg != 0) |
67c0d1eb | 8984 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 8985 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8986 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8987 | BFD_RELOC_LO16, AT); |
252b5132 RH |
8988 | /* FIXME: How do we handle overflow here? */ |
8989 | offset_expr.X_add_number += 4; | |
beae10d5 | 8990 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8991 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8992 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
8993 | if (mips_relax.sequence) |
8994 | relax_end (); | |
bdaaa2e1 | 8995 | } |
0a44bf69 | 8996 | else if (!mips_big_got) |
252b5132 | 8997 | { |
252b5132 RH |
8998 | /* If this is a reference to an external symbol, we want |
8999 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9000 | nop | |
9001 | <op> $treg,0($at) | |
9002 | <op> $treg+1,4($at) | |
9003 | Otherwise we want | |
9004 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9005 | nop | |
9006 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9007 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9008 | If there is a base register we add it to $at before the | |
9009 | lwc1 instructions. If there is a constant we include it | |
9010 | in the lwc1 instructions. */ | |
9011 | used_at = 1; | |
9012 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9013 | if (expr1.X_add_number < -0x8000 |
9014 | || expr1.X_add_number >= 0x8000 - 4) | |
9015 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9016 | load_got_offset (AT, &offset_expr); |
269137b2 | 9017 | load_delay_nop (); |
252b5132 | 9018 | if (breg != 0) |
67c0d1eb | 9019 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9020 | |
9021 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9022 | nop. */ | |
9023 | hold_mips_optimize = mips_optimize; | |
9024 | mips_optimize = 2; | |
4d7206a2 | 9025 | |
beae10d5 | 9026 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9027 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9028 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9029 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9030 | expr1.X_add_number += 4; |
67c0d1eb RS |
9031 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9032 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9033 | relax_switch (); |
67c0d1eb RS |
9034 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9035 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9036 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9037 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9038 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9039 | relax_end (); |
252b5132 | 9040 | |
4d7206a2 | 9041 | mips_optimize = hold_mips_optimize; |
252b5132 | 9042 | } |
0a44bf69 | 9043 | else if (mips_big_got) |
252b5132 | 9044 | { |
67c0d1eb | 9045 | int gpdelay; |
252b5132 RH |
9046 | |
9047 | /* If this is a reference to an external symbol, we want | |
9048 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9049 | addu $at,$at,$gp | |
9050 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9051 | nop | |
9052 | <op> $treg,0($at) | |
9053 | <op> $treg+1,4($at) | |
9054 | Otherwise we want | |
9055 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9056 | nop | |
9057 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9058 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9059 | If there is a base register we add it to $at before the | |
9060 | lwc1 instructions. If there is a constant we include it | |
9061 | in the lwc1 instructions. */ | |
9062 | used_at = 1; | |
9063 | expr1.X_add_number = offset_expr.X_add_number; | |
9064 | offset_expr.X_add_number = 0; | |
9065 | if (expr1.X_add_number < -0x8000 | |
9066 | || expr1.X_add_number >= 0x8000 - 4) | |
9067 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9068 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9069 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9070 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9071 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9072 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9073 | AT, AT, mips_gp_register); |
67c0d1eb | 9074 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9075 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9076 | load_delay_nop (); |
252b5132 | 9077 | if (breg != 0) |
67c0d1eb | 9078 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9079 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9080 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9081 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9082 | expr1.X_add_number += 4; |
9083 | ||
9084 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9085 | nop. */ | |
9086 | hold_mips_optimize = mips_optimize; | |
9087 | mips_optimize = 2; | |
beae10d5 | 9088 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9089 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9090 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9091 | mips_optimize = hold_mips_optimize; |
9092 | expr1.X_add_number -= 4; | |
9093 | ||
4d7206a2 RS |
9094 | relax_switch (); |
9095 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9096 | if (gpdelay) |
9097 | macro_build (NULL, "nop", ""); | |
9098 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9099 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9100 | load_delay_nop (); |
252b5132 | 9101 | if (breg != 0) |
67c0d1eb | 9102 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9103 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9104 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9105 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9106 | offset_expr.X_add_number += 4; |
252b5132 RH |
9107 | |
9108 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9109 | nop. */ | |
9110 | hold_mips_optimize = mips_optimize; | |
9111 | mips_optimize = 2; | |
beae10d5 | 9112 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9113 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9114 | BFD_RELOC_LO16, AT); | |
252b5132 | 9115 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9116 | relax_end (); |
252b5132 | 9117 | } |
252b5132 RH |
9118 | else |
9119 | abort (); | |
9120 | ||
252b5132 RH |
9121 | break; |
9122 | ||
9123 | case M_LD_OB: | |
704897fb | 9124 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9125 | goto sd_ob; |
9126 | case M_SD_OB: | |
704897fb | 9127 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9128 | sd_ob: |
4614d845 MR |
9129 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9130 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9131 | breg); | |
704897fb MR |
9132 | if (!HAVE_64BIT_GPRS) |
9133 | { | |
9134 | offset_expr.X_add_number += 4; | |
9135 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9136 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9137 | breg); | |
704897fb | 9138 | } |
8fc2e39e | 9139 | break; |
252b5132 | 9140 | |
dd6a37e7 AP |
9141 | |
9142 | case M_SAA_AB: | |
9143 | ab = 1; | |
9144 | case M_SAA_OB: | |
9145 | s = "saa"; | |
9146 | off0 = 1; | |
9147 | fmt = "t,(b)"; | |
9148 | goto ld_st; | |
9149 | case M_SAAD_AB: | |
9150 | ab = 1; | |
9151 | case M_SAAD_OB: | |
9152 | s = "saad"; | |
9153 | off0 = 1; | |
9154 | fmt = "t,(b)"; | |
9155 | goto ld_st; | |
9156 | ||
252b5132 RH |
9157 | /* New code added to support COPZ instructions. |
9158 | This code builds table entries out of the macros in mip_opcodes. | |
9159 | R4000 uses interlocks to handle coproc delays. | |
9160 | Other chips (like the R3000) require nops to be inserted for delays. | |
9161 | ||
f72c8c98 | 9162 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9163 | In order to fill delay slots for non-interlocked chips, |
9164 | we must have a way to specify delays based on the coprocessor. | |
9165 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9166 | What are the side-effects of the cop instruction? | |
9167 | What cache support might we have and what are its effects? | |
9168 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9169 | What registers are read/set/modified? |
252b5132 RH |
9170 | |
9171 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9172 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9173 | |
9174 | case M_COP0: | |
9175 | s = "c0"; | |
9176 | goto copz; | |
9177 | case M_COP1: | |
9178 | s = "c1"; | |
9179 | goto copz; | |
9180 | case M_COP2: | |
9181 | s = "c2"; | |
9182 | goto copz; | |
9183 | case M_COP3: | |
9184 | s = "c3"; | |
9185 | copz: | |
df58fc94 | 9186 | gas_assert (!mips_opts.micromips); |
b19e8a9b AN |
9187 | if (NO_ISA_COP (mips_opts.arch) |
9188 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
9189 | { | |
7bd942df | 9190 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
9191 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
9192 | break; | |
9193 | } | |
9194 | ||
252b5132 RH |
9195 | /* For now we just do C (same as Cz). The parameter will be |
9196 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9197 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9198 | break; |
252b5132 | 9199 | |
ea1fb5dc | 9200 | case M_MOVE: |
67c0d1eb | 9201 | move_register (dreg, sreg); |
8fc2e39e | 9202 | break; |
ea1fb5dc | 9203 | |
252b5132 RH |
9204 | case M_DMUL: |
9205 | dbl = 1; | |
9206 | case M_MUL: | |
67c0d1eb | 9207 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9208 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
8fc2e39e | 9209 | break; |
252b5132 RH |
9210 | |
9211 | case M_DMUL_I: | |
9212 | dbl = 1; | |
9213 | case M_MUL_I: | |
9214 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9215 | not trying to be that fancy. GCC should do this for us | |
9216 | anyway. */ | |
8fc2e39e | 9217 | used_at = 1; |
67c0d1eb RS |
9218 | load_register (AT, &imm_expr, dbl); |
9219 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9220 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9221 | break; |
9222 | ||
9223 | case M_DMULO_I: | |
9224 | dbl = 1; | |
9225 | case M_MULO_I: | |
9226 | imm = 1; | |
9227 | goto do_mulo; | |
9228 | ||
9229 | case M_DMULO: | |
9230 | dbl = 1; | |
9231 | case M_MULO: | |
9232 | do_mulo: | |
7d10b47d | 9233 | start_noreorder (); |
8fc2e39e | 9234 | used_at = 1; |
252b5132 | 9235 | if (imm) |
67c0d1eb RS |
9236 | load_register (AT, &imm_expr, dbl); |
9237 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9238 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9239 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9240 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9241 | if (mips_trap) |
df58fc94 | 9242 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9243 | else |
9244 | { | |
df58fc94 RS |
9245 | if (mips_opts.micromips) |
9246 | micromips_label_expr (&label_expr); | |
9247 | else | |
9248 | label_expr.X_add_number = 8; | |
9249 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9250 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9251 | macro_build (NULL, "break", BRK_FMT, 6); |
9252 | if (mips_opts.micromips) | |
9253 | micromips_add_label (); | |
252b5132 | 9254 | } |
7d10b47d | 9255 | end_noreorder (); |
df58fc94 | 9256 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9257 | break; |
9258 | ||
9259 | case M_DMULOU_I: | |
9260 | dbl = 1; | |
9261 | case M_MULOU_I: | |
9262 | imm = 1; | |
9263 | goto do_mulou; | |
9264 | ||
9265 | case M_DMULOU: | |
9266 | dbl = 1; | |
9267 | case M_MULOU: | |
9268 | do_mulou: | |
7d10b47d | 9269 | start_noreorder (); |
8fc2e39e | 9270 | used_at = 1; |
252b5132 | 9271 | if (imm) |
67c0d1eb RS |
9272 | load_register (AT, &imm_expr, dbl); |
9273 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9274 | sreg, imm ? AT : treg); |
df58fc94 RS |
9275 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9276 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9277 | if (mips_trap) |
df58fc94 | 9278 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9279 | else |
9280 | { | |
df58fc94 RS |
9281 | if (mips_opts.micromips) |
9282 | micromips_label_expr (&label_expr); | |
9283 | else | |
9284 | label_expr.X_add_number = 8; | |
9285 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9286 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9287 | macro_build (NULL, "break", BRK_FMT, 6); |
9288 | if (mips_opts.micromips) | |
9289 | micromips_add_label (); | |
252b5132 | 9290 | } |
7d10b47d | 9291 | end_noreorder (); |
252b5132 RH |
9292 | break; |
9293 | ||
771c7ce4 | 9294 | case M_DROL: |
fef14a42 | 9295 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9296 | { |
9297 | if (dreg == sreg) | |
9298 | { | |
9299 | tempreg = AT; | |
9300 | used_at = 1; | |
9301 | } | |
9302 | else | |
9303 | { | |
9304 | tempreg = dreg; | |
82dd0097 | 9305 | } |
67c0d1eb RS |
9306 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9307 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9308 | break; |
82dd0097 | 9309 | } |
8fc2e39e | 9310 | used_at = 1; |
c80c840e | 9311 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9312 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9313 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9314 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9315 | break; |
9316 | ||
252b5132 | 9317 | case M_ROL: |
fef14a42 | 9318 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9319 | { |
9320 | if (dreg == sreg) | |
9321 | { | |
9322 | tempreg = AT; | |
9323 | used_at = 1; | |
9324 | } | |
9325 | else | |
9326 | { | |
9327 | tempreg = dreg; | |
82dd0097 | 9328 | } |
67c0d1eb RS |
9329 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9330 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9331 | break; |
82dd0097 | 9332 | } |
8fc2e39e | 9333 | used_at = 1; |
c80c840e | 9334 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9335 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9336 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9337 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9338 | break; |
9339 | ||
771c7ce4 TS |
9340 | case M_DROL_I: |
9341 | { | |
9342 | unsigned int rot; | |
91d6fa6a NC |
9343 | char *l; |
9344 | char *rr; | |
771c7ce4 TS |
9345 | |
9346 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9347 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9348 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9349 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9350 | { |
9351 | rot = (64 - rot) & 0x3f; | |
9352 | if (rot >= 32) | |
df58fc94 | 9353 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9354 | else |
df58fc94 | 9355 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9356 | break; |
60b63b72 | 9357 | } |
483fc7cd | 9358 | if (rot == 0) |
483fc7cd | 9359 | { |
df58fc94 | 9360 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9361 | break; |
483fc7cd | 9362 | } |
82dd0097 | 9363 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9364 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9365 | rot &= 0x1f; |
8fc2e39e | 9366 | used_at = 1; |
df58fc94 RS |
9367 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9368 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9369 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9370 | } |
9371 | break; | |
9372 | ||
252b5132 | 9373 | case M_ROL_I: |
771c7ce4 TS |
9374 | { |
9375 | unsigned int rot; | |
9376 | ||
9377 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9378 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9379 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9380 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9381 | { |
df58fc94 | 9382 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9383 | break; |
60b63b72 | 9384 | } |
483fc7cd | 9385 | if (rot == 0) |
483fc7cd | 9386 | { |
df58fc94 | 9387 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9388 | break; |
483fc7cd | 9389 | } |
8fc2e39e | 9390 | used_at = 1; |
df58fc94 RS |
9391 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9392 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9393 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9394 | } |
9395 | break; | |
9396 | ||
9397 | case M_DROR: | |
fef14a42 | 9398 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9399 | { |
67c0d1eb | 9400 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9401 | break; |
82dd0097 | 9402 | } |
8fc2e39e | 9403 | used_at = 1; |
c80c840e | 9404 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9405 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9406 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9407 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9408 | break; |
9409 | ||
9410 | case M_ROR: | |
fef14a42 | 9411 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9412 | { |
67c0d1eb | 9413 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9414 | break; |
82dd0097 | 9415 | } |
8fc2e39e | 9416 | used_at = 1; |
c80c840e | 9417 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9418 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9419 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9420 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9421 | break; |
9422 | ||
771c7ce4 TS |
9423 | case M_DROR_I: |
9424 | { | |
9425 | unsigned int rot; | |
91d6fa6a NC |
9426 | char *l; |
9427 | char *rr; | |
771c7ce4 TS |
9428 | |
9429 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9430 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9431 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9432 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9433 | { |
9434 | if (rot >= 32) | |
df58fc94 | 9435 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9436 | else |
df58fc94 | 9437 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9438 | break; |
82dd0097 | 9439 | } |
483fc7cd | 9440 | if (rot == 0) |
483fc7cd | 9441 | { |
df58fc94 | 9442 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9443 | break; |
483fc7cd | 9444 | } |
91d6fa6a | 9445 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9446 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9447 | rot &= 0x1f; | |
8fc2e39e | 9448 | used_at = 1; |
df58fc94 RS |
9449 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9450 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9451 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9452 | } |
9453 | break; | |
9454 | ||
252b5132 | 9455 | case M_ROR_I: |
771c7ce4 TS |
9456 | { |
9457 | unsigned int rot; | |
9458 | ||
9459 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9460 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9461 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9462 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9463 | { |
df58fc94 | 9464 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9465 | break; |
82dd0097 | 9466 | } |
483fc7cd | 9467 | if (rot == 0) |
483fc7cd | 9468 | { |
df58fc94 | 9469 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9470 | break; |
483fc7cd | 9471 | } |
8fc2e39e | 9472 | used_at = 1; |
df58fc94 RS |
9473 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9474 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9475 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9476 | } |
252b5132 RH |
9477 | break; |
9478 | ||
252b5132 RH |
9479 | case M_SEQ: |
9480 | if (sreg == 0) | |
67c0d1eb | 9481 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9482 | else if (treg == 0) |
67c0d1eb | 9483 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9484 | else |
9485 | { | |
67c0d1eb RS |
9486 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9487 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9488 | } |
8fc2e39e | 9489 | break; |
252b5132 RH |
9490 | |
9491 | case M_SEQ_I: | |
9492 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9493 | { | |
67c0d1eb | 9494 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9495 | break; |
252b5132 RH |
9496 | } |
9497 | if (sreg == 0) | |
9498 | { | |
9499 | as_warn (_("Instruction %s: result is always false"), | |
9500 | ip->insn_mo->name); | |
67c0d1eb | 9501 | move_register (dreg, 0); |
8fc2e39e | 9502 | break; |
252b5132 | 9503 | } |
dd3cbb7e NC |
9504 | if (CPU_HAS_SEQ (mips_opts.arch) |
9505 | && -512 <= imm_expr.X_add_number | |
9506 | && imm_expr.X_add_number < 512) | |
9507 | { | |
9508 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9509 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9510 | break; |
9511 | } | |
252b5132 RH |
9512 | if (imm_expr.X_op == O_constant |
9513 | && imm_expr.X_add_number >= 0 | |
9514 | && imm_expr.X_add_number < 0x10000) | |
9515 | { | |
67c0d1eb | 9516 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9517 | } |
9518 | else if (imm_expr.X_op == O_constant | |
9519 | && imm_expr.X_add_number > -0x8000 | |
9520 | && imm_expr.X_add_number < 0) | |
9521 | { | |
9522 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9523 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9524 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9525 | } |
dd3cbb7e NC |
9526 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9527 | { | |
9528 | used_at = 1; | |
9529 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9530 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9531 | break; | |
9532 | } | |
252b5132 RH |
9533 | else |
9534 | { | |
67c0d1eb RS |
9535 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9536 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9537 | used_at = 1; |
9538 | } | |
67c0d1eb | 9539 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9540 | break; |
252b5132 RH |
9541 | |
9542 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9543 | s = "slt"; | |
9544 | goto sge; | |
9545 | case M_SGEU: | |
9546 | s = "sltu"; | |
9547 | sge: | |
67c0d1eb RS |
9548 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9549 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9550 | break; |
252b5132 RH |
9551 | |
9552 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9553 | case M_SGEU_I: | |
9554 | if (imm_expr.X_op == O_constant | |
9555 | && imm_expr.X_add_number >= -0x8000 | |
9556 | && imm_expr.X_add_number < 0x8000) | |
9557 | { | |
67c0d1eb RS |
9558 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9559 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9560 | } |
9561 | else | |
9562 | { | |
67c0d1eb RS |
9563 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9564 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9565 | dreg, sreg, AT); | |
252b5132 RH |
9566 | used_at = 1; |
9567 | } | |
67c0d1eb | 9568 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9569 | break; |
252b5132 RH |
9570 | |
9571 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9572 | s = "slt"; | |
9573 | goto sgt; | |
9574 | case M_SGTU: | |
9575 | s = "sltu"; | |
9576 | sgt: | |
67c0d1eb | 9577 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9578 | break; |
252b5132 RH |
9579 | |
9580 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9581 | s = "slt"; | |
9582 | goto sgti; | |
9583 | case M_SGTU_I: | |
9584 | s = "sltu"; | |
9585 | sgti: | |
8fc2e39e | 9586 | used_at = 1; |
67c0d1eb RS |
9587 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9588 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9589 | break; |
9590 | ||
2396cfb9 | 9591 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9592 | s = "slt"; |
9593 | goto sle; | |
9594 | case M_SLEU: | |
9595 | s = "sltu"; | |
9596 | sle: | |
67c0d1eb RS |
9597 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9598 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9599 | break; |
252b5132 | 9600 | |
2396cfb9 | 9601 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9602 | s = "slt"; |
9603 | goto slei; | |
9604 | case M_SLEU_I: | |
9605 | s = "sltu"; | |
9606 | slei: | |
8fc2e39e | 9607 | used_at = 1; |
67c0d1eb RS |
9608 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9609 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9610 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9611 | break; |
9612 | ||
9613 | case M_SLT_I: | |
9614 | if (imm_expr.X_op == O_constant | |
9615 | && imm_expr.X_add_number >= -0x8000 | |
9616 | && imm_expr.X_add_number < 0x8000) | |
9617 | { | |
67c0d1eb | 9618 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9619 | break; |
252b5132 | 9620 | } |
8fc2e39e | 9621 | used_at = 1; |
67c0d1eb RS |
9622 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9623 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9624 | break; |
9625 | ||
9626 | case M_SLTU_I: | |
9627 | if (imm_expr.X_op == O_constant | |
9628 | && imm_expr.X_add_number >= -0x8000 | |
9629 | && imm_expr.X_add_number < 0x8000) | |
9630 | { | |
67c0d1eb | 9631 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9632 | BFD_RELOC_LO16); |
8fc2e39e | 9633 | break; |
252b5132 | 9634 | } |
8fc2e39e | 9635 | used_at = 1; |
67c0d1eb RS |
9636 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9637 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9638 | break; |
9639 | ||
9640 | case M_SNE: | |
9641 | if (sreg == 0) | |
67c0d1eb | 9642 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9643 | else if (treg == 0) |
67c0d1eb | 9644 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9645 | else |
9646 | { | |
67c0d1eb RS |
9647 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9648 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9649 | } |
8fc2e39e | 9650 | break; |
252b5132 RH |
9651 | |
9652 | case M_SNE_I: | |
9653 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9654 | { | |
67c0d1eb | 9655 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9656 | break; |
252b5132 RH |
9657 | } |
9658 | if (sreg == 0) | |
9659 | { | |
9660 | as_warn (_("Instruction %s: result is always true"), | |
9661 | ip->insn_mo->name); | |
67c0d1eb RS |
9662 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9663 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9664 | break; |
252b5132 | 9665 | } |
dd3cbb7e NC |
9666 | if (CPU_HAS_SEQ (mips_opts.arch) |
9667 | && -512 <= imm_expr.X_add_number | |
9668 | && imm_expr.X_add_number < 512) | |
9669 | { | |
9670 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9671 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9672 | break; |
9673 | } | |
252b5132 RH |
9674 | if (imm_expr.X_op == O_constant |
9675 | && imm_expr.X_add_number >= 0 | |
9676 | && imm_expr.X_add_number < 0x10000) | |
9677 | { | |
67c0d1eb | 9678 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9679 | } |
9680 | else if (imm_expr.X_op == O_constant | |
9681 | && imm_expr.X_add_number > -0x8000 | |
9682 | && imm_expr.X_add_number < 0) | |
9683 | { | |
9684 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9685 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9686 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9687 | } |
dd3cbb7e NC |
9688 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9689 | { | |
9690 | used_at = 1; | |
9691 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9692 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9693 | break; | |
9694 | } | |
252b5132 RH |
9695 | else |
9696 | { | |
67c0d1eb RS |
9697 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9698 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9699 | used_at = 1; |
9700 | } | |
67c0d1eb | 9701 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9702 | break; |
252b5132 | 9703 | |
df58fc94 RS |
9704 | case M_SUB_I: |
9705 | s = "addi"; | |
9706 | s2 = "sub"; | |
9707 | goto do_subi; | |
9708 | case M_SUBU_I: | |
9709 | s = "addiu"; | |
9710 | s2 = "subu"; | |
9711 | goto do_subi; | |
252b5132 RH |
9712 | case M_DSUB_I: |
9713 | dbl = 1; | |
df58fc94 RS |
9714 | s = "daddi"; |
9715 | s2 = "dsub"; | |
9716 | if (!mips_opts.micromips) | |
9717 | goto do_subi; | |
252b5132 | 9718 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9719 | && imm_expr.X_add_number > -0x200 |
9720 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9721 | { |
df58fc94 | 9722 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9723 | break; |
252b5132 | 9724 | } |
df58fc94 | 9725 | goto do_subi_i; |
252b5132 RH |
9726 | case M_DSUBU_I: |
9727 | dbl = 1; | |
df58fc94 RS |
9728 | s = "daddiu"; |
9729 | s2 = "dsubu"; | |
9730 | do_subi: | |
252b5132 RH |
9731 | if (imm_expr.X_op == O_constant |
9732 | && imm_expr.X_add_number > -0x8000 | |
9733 | && imm_expr.X_add_number <= 0x8000) | |
9734 | { | |
9735 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9736 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9737 | break; |
252b5132 | 9738 | } |
df58fc94 | 9739 | do_subi_i: |
8fc2e39e | 9740 | used_at = 1; |
67c0d1eb | 9741 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9742 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9743 | break; |
9744 | ||
9745 | case M_TEQ_I: | |
9746 | s = "teq"; | |
9747 | goto trap; | |
9748 | case M_TGE_I: | |
9749 | s = "tge"; | |
9750 | goto trap; | |
9751 | case M_TGEU_I: | |
9752 | s = "tgeu"; | |
9753 | goto trap; | |
9754 | case M_TLT_I: | |
9755 | s = "tlt"; | |
9756 | goto trap; | |
9757 | case M_TLTU_I: | |
9758 | s = "tltu"; | |
9759 | goto trap; | |
9760 | case M_TNE_I: | |
9761 | s = "tne"; | |
9762 | trap: | |
8fc2e39e | 9763 | used_at = 1; |
67c0d1eb RS |
9764 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9765 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9766 | break; |
9767 | ||
252b5132 | 9768 | case M_TRUNCWS: |
43841e91 | 9769 | case M_TRUNCWD: |
df58fc94 | 9770 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 9771 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9772 | used_at = 1; |
252b5132 RH |
9773 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9774 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9775 | ||
9776 | /* | |
9777 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9778 | * or is there a reason for it? | |
9779 | */ | |
7d10b47d | 9780 | start_noreorder (); |
67c0d1eb RS |
9781 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9782 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9783 | macro_build (NULL, "nop", ""); | |
252b5132 | 9784 | expr1.X_add_number = 3; |
67c0d1eb | 9785 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9786 | expr1.X_add_number = 2; |
67c0d1eb RS |
9787 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9788 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9789 | macro_build (NULL, "nop", ""); | |
9790 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9791 | dreg, sreg); | |
9792 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9793 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9794 | end_noreorder (); |
252b5132 RH |
9795 | break; |
9796 | ||
df58fc94 RS |
9797 | case M_ULH_A: |
9798 | ab = 1; | |
252b5132 RH |
9799 | case M_ULH: |
9800 | s = "lb"; | |
df58fc94 RS |
9801 | s2 = "lbu"; |
9802 | off = 1; | |
9803 | goto uld_st; | |
9804 | case M_ULHU_A: | |
9805 | ab = 1; | |
252b5132 RH |
9806 | case M_ULHU: |
9807 | s = "lbu"; | |
df58fc94 RS |
9808 | s2 = "lbu"; |
9809 | off = 1; | |
9810 | goto uld_st; | |
9811 | case M_ULW_A: | |
9812 | ab = 1; | |
9813 | case M_ULW: | |
9814 | s = "lwl"; | |
9815 | s2 = "lwr"; | |
9816 | off12 = mips_opts.micromips; | |
9817 | off = 3; | |
9818 | goto uld_st; | |
9819 | case M_ULD_A: | |
9820 | ab = 1; | |
252b5132 RH |
9821 | case M_ULD: |
9822 | s = "ldl"; | |
9823 | s2 = "ldr"; | |
df58fc94 | 9824 | off12 = mips_opts.micromips; |
252b5132 | 9825 | off = 7; |
df58fc94 RS |
9826 | goto uld_st; |
9827 | case M_USH_A: | |
9828 | ab = 1; | |
9829 | case M_USH: | |
9830 | s = "sb"; | |
9831 | s2 = "sb"; | |
9832 | off = 1; | |
9833 | ust = 1; | |
9834 | goto uld_st; | |
9835 | case M_USW_A: | |
9836 | ab = 1; | |
9837 | case M_USW: | |
9838 | s = "swl"; | |
9839 | s2 = "swr"; | |
9840 | off12 = mips_opts.micromips; | |
252b5132 | 9841 | off = 3; |
df58fc94 RS |
9842 | ust = 1; |
9843 | goto uld_st; | |
9844 | case M_USD_A: | |
9845 | ab = 1; | |
9846 | case M_USD: | |
9847 | s = "sdl"; | |
9848 | s2 = "sdr"; | |
9849 | off12 = mips_opts.micromips; | |
9850 | off = 7; | |
9851 | ust = 1; | |
9852 | ||
9853 | uld_st: | |
9854 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 9855 | as_bad (_("Operand overflow")); |
df58fc94 RS |
9856 | |
9857 | ep = &offset_expr; | |
9858 | expr1.X_add_number = 0; | |
9859 | if (ab) | |
9860 | { | |
9861 | used_at = 1; | |
9862 | tempreg = AT; | |
9863 | load_address (tempreg, ep, &used_at); | |
9864 | if (breg != 0) | |
9865 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9866 | tempreg, tempreg, breg); | |
9867 | breg = tempreg; | |
9868 | tempreg = treg; | |
9869 | ep = &expr1; | |
9870 | } | |
9871 | else if (off12 | |
9872 | && (offset_expr.X_op != O_constant | |
9873 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
9874 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
9875 | { | |
9876 | used_at = 1; | |
9877 | tempreg = AT; | |
9878 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
9879 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
9880 | breg = tempreg; | |
9881 | tempreg = treg; | |
9882 | ep = &expr1; | |
9883 | } | |
9884 | else if (!ust && treg == breg) | |
8fc2e39e TS |
9885 | { |
9886 | used_at = 1; | |
9887 | tempreg = AT; | |
9888 | } | |
252b5132 | 9889 | else |
df58fc94 | 9890 | tempreg = treg; |
af22f5b2 | 9891 | |
df58fc94 RS |
9892 | if (off == 1) |
9893 | goto ulh_sh; | |
252b5132 | 9894 | |
90ecf173 | 9895 | if (!target_big_endian) |
df58fc94 RS |
9896 | ep->X_add_number += off; |
9897 | if (!off12) | |
9898 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9899 | else |
df58fc94 RS |
9900 | macro_build (NULL, s, "t,~(b)", |
9901 | tempreg, (unsigned long) ep->X_add_number, breg); | |
9902 | ||
90ecf173 | 9903 | if (!target_big_endian) |
df58fc94 | 9904 | ep->X_add_number -= off; |
252b5132 | 9905 | else |
df58fc94 RS |
9906 | ep->X_add_number += off; |
9907 | if (!off12) | |
9908 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9909 | else | |
9910 | macro_build (NULL, s2, "t,~(b)", | |
9911 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 9912 | |
df58fc94 RS |
9913 | /* If necessary, move the result in tempreg to the final destination. */ |
9914 | if (!ust && treg != tempreg) | |
9915 | { | |
9916 | /* Protect second load's delay slot. */ | |
9917 | load_delay_nop (); | |
9918 | move_register (treg, tempreg); | |
9919 | } | |
8fc2e39e | 9920 | break; |
252b5132 | 9921 | |
df58fc94 | 9922 | ulh_sh: |
d6bc6245 | 9923 | used_at = 1; |
df58fc94 RS |
9924 | if (target_big_endian == ust) |
9925 | ep->X_add_number += off; | |
9926 | tempreg = ust || ab ? treg : AT; | |
9927 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9928 | ||
9929 | /* For halfword transfers we need a temporary register to shuffle | |
9930 | bytes. Unfortunately for M_USH_A we have none available before | |
9931 | the next store as AT holds the base address. We deal with this | |
9932 | case by clobbering TREG and then restoring it as with ULH. */ | |
9933 | tempreg = ust == ab ? treg : AT; | |
9934 | if (ust) | |
9935 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
9936 | ||
9937 | if (target_big_endian == ust) | |
9938 | ep->X_add_number -= off; | |
252b5132 | 9939 | else |
df58fc94 RS |
9940 | ep->X_add_number += off; |
9941 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9942 | |
df58fc94 RS |
9943 | /* For M_USH_A re-retrieve the LSB. */ |
9944 | if (ust && ab) | |
9945 | { | |
9946 | if (target_big_endian) | |
9947 | ep->X_add_number += off; | |
9948 | else | |
9949 | ep->X_add_number -= off; | |
9950 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
9951 | } | |
9952 | /* For ULH and M_USH_A OR the LSB in. */ | |
9953 | if (!ust || ab) | |
9954 | { | |
9955 | tempreg = !ab ? AT : treg; | |
9956 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
9957 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
9958 | } | |
252b5132 RH |
9959 | break; |
9960 | ||
9961 | default: | |
9962 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 9963 | are added dynamically. */ |
252b5132 RH |
9964 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
9965 | break; | |
9966 | } | |
741fe287 | 9967 | if (!mips_opts.at && used_at) |
8fc2e39e | 9968 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
9969 | } |
9970 | ||
9971 | /* Implement macros in mips16 mode. */ | |
9972 | ||
9973 | static void | |
17a2f251 | 9974 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
9975 | { |
9976 | int mask; | |
9977 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
9978 | expressionS expr1; |
9979 | int dbl; | |
9980 | const char *s, *s2, *s3; | |
9981 | ||
9982 | mask = ip->insn_mo->mask; | |
9983 | ||
bf12938e RS |
9984 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
9985 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
9986 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 9987 | |
252b5132 RH |
9988 | expr1.X_op = O_constant; |
9989 | expr1.X_op_symbol = NULL; | |
9990 | expr1.X_add_symbol = NULL; | |
9991 | expr1.X_add_number = 1; | |
9992 | ||
9993 | dbl = 0; | |
9994 | ||
9995 | switch (mask) | |
9996 | { | |
9997 | default: | |
9998 | internalError (); | |
9999 | ||
10000 | case M_DDIV_3: | |
10001 | dbl = 1; | |
10002 | case M_DIV_3: | |
10003 | s = "mflo"; | |
10004 | goto do_div3; | |
10005 | case M_DREM_3: | |
10006 | dbl = 1; | |
10007 | case M_REM_3: | |
10008 | s = "mfhi"; | |
10009 | do_div3: | |
7d10b47d | 10010 | start_noreorder (); |
67c0d1eb | 10011 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10012 | expr1.X_add_number = 2; |
67c0d1eb RS |
10013 | macro_build (&expr1, "bnez", "x,p", yreg); |
10014 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10015 | |
252b5132 RH |
10016 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10017 | since that causes an overflow. We should do that as well, | |
10018 | but I don't see how to do the comparisons without a temporary | |
10019 | register. */ | |
7d10b47d | 10020 | end_noreorder (); |
67c0d1eb | 10021 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10022 | break; |
10023 | ||
10024 | case M_DIVU_3: | |
10025 | s = "divu"; | |
10026 | s2 = "mflo"; | |
10027 | goto do_divu3; | |
10028 | case M_REMU_3: | |
10029 | s = "divu"; | |
10030 | s2 = "mfhi"; | |
10031 | goto do_divu3; | |
10032 | case M_DDIVU_3: | |
10033 | s = "ddivu"; | |
10034 | s2 = "mflo"; | |
10035 | goto do_divu3; | |
10036 | case M_DREMU_3: | |
10037 | s = "ddivu"; | |
10038 | s2 = "mfhi"; | |
10039 | do_divu3: | |
7d10b47d | 10040 | start_noreorder (); |
67c0d1eb | 10041 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10042 | expr1.X_add_number = 2; |
67c0d1eb RS |
10043 | macro_build (&expr1, "bnez", "x,p", yreg); |
10044 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10045 | end_noreorder (); |
67c0d1eb | 10046 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10047 | break; |
10048 | ||
10049 | case M_DMUL: | |
10050 | dbl = 1; | |
10051 | case M_MUL: | |
67c0d1eb RS |
10052 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10053 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10054 | break; |
252b5132 RH |
10055 | |
10056 | case M_DSUBU_I: | |
10057 | dbl = 1; | |
10058 | goto do_subu; | |
10059 | case M_SUBU_I: | |
10060 | do_subu: | |
10061 | if (imm_expr.X_op != O_constant) | |
10062 | as_bad (_("Unsupported large constant")); | |
10063 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10064 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10065 | break; |
10066 | ||
10067 | case M_SUBU_I_2: | |
10068 | if (imm_expr.X_op != O_constant) | |
10069 | as_bad (_("Unsupported large constant")); | |
10070 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10071 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10072 | break; |
10073 | ||
10074 | case M_DSUBU_I_2: | |
10075 | if (imm_expr.X_op != O_constant) | |
10076 | as_bad (_("Unsupported large constant")); | |
10077 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10078 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10079 | break; |
10080 | ||
10081 | case M_BEQ: | |
10082 | s = "cmp"; | |
10083 | s2 = "bteqz"; | |
10084 | goto do_branch; | |
10085 | case M_BNE: | |
10086 | s = "cmp"; | |
10087 | s2 = "btnez"; | |
10088 | goto do_branch; | |
10089 | case M_BLT: | |
10090 | s = "slt"; | |
10091 | s2 = "btnez"; | |
10092 | goto do_branch; | |
10093 | case M_BLTU: | |
10094 | s = "sltu"; | |
10095 | s2 = "btnez"; | |
10096 | goto do_branch; | |
10097 | case M_BLE: | |
10098 | s = "slt"; | |
10099 | s2 = "bteqz"; | |
10100 | goto do_reverse_branch; | |
10101 | case M_BLEU: | |
10102 | s = "sltu"; | |
10103 | s2 = "bteqz"; | |
10104 | goto do_reverse_branch; | |
10105 | case M_BGE: | |
10106 | s = "slt"; | |
10107 | s2 = "bteqz"; | |
10108 | goto do_branch; | |
10109 | case M_BGEU: | |
10110 | s = "sltu"; | |
10111 | s2 = "bteqz"; | |
10112 | goto do_branch; | |
10113 | case M_BGT: | |
10114 | s = "slt"; | |
10115 | s2 = "btnez"; | |
10116 | goto do_reverse_branch; | |
10117 | case M_BGTU: | |
10118 | s = "sltu"; | |
10119 | s2 = "btnez"; | |
10120 | ||
10121 | do_reverse_branch: | |
10122 | tmp = xreg; | |
10123 | xreg = yreg; | |
10124 | yreg = tmp; | |
10125 | ||
10126 | do_branch: | |
67c0d1eb RS |
10127 | macro_build (NULL, s, "x,y", xreg, yreg); |
10128 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10129 | break; |
10130 | ||
10131 | case M_BEQ_I: | |
10132 | s = "cmpi"; | |
10133 | s2 = "bteqz"; | |
10134 | s3 = "x,U"; | |
10135 | goto do_branch_i; | |
10136 | case M_BNE_I: | |
10137 | s = "cmpi"; | |
10138 | s2 = "btnez"; | |
10139 | s3 = "x,U"; | |
10140 | goto do_branch_i; | |
10141 | case M_BLT_I: | |
10142 | s = "slti"; | |
10143 | s2 = "btnez"; | |
10144 | s3 = "x,8"; | |
10145 | goto do_branch_i; | |
10146 | case M_BLTU_I: | |
10147 | s = "sltiu"; | |
10148 | s2 = "btnez"; | |
10149 | s3 = "x,8"; | |
10150 | goto do_branch_i; | |
10151 | case M_BLE_I: | |
10152 | s = "slti"; | |
10153 | s2 = "btnez"; | |
10154 | s3 = "x,8"; | |
10155 | goto do_addone_branch_i; | |
10156 | case M_BLEU_I: | |
10157 | s = "sltiu"; | |
10158 | s2 = "btnez"; | |
10159 | s3 = "x,8"; | |
10160 | goto do_addone_branch_i; | |
10161 | case M_BGE_I: | |
10162 | s = "slti"; | |
10163 | s2 = "bteqz"; | |
10164 | s3 = "x,8"; | |
10165 | goto do_branch_i; | |
10166 | case M_BGEU_I: | |
10167 | s = "sltiu"; | |
10168 | s2 = "bteqz"; | |
10169 | s3 = "x,8"; | |
10170 | goto do_branch_i; | |
10171 | case M_BGT_I: | |
10172 | s = "slti"; | |
10173 | s2 = "bteqz"; | |
10174 | s3 = "x,8"; | |
10175 | goto do_addone_branch_i; | |
10176 | case M_BGTU_I: | |
10177 | s = "sltiu"; | |
10178 | s2 = "bteqz"; | |
10179 | s3 = "x,8"; | |
10180 | ||
10181 | do_addone_branch_i: | |
10182 | if (imm_expr.X_op != O_constant) | |
10183 | as_bad (_("Unsupported large constant")); | |
10184 | ++imm_expr.X_add_number; | |
10185 | ||
10186 | do_branch_i: | |
67c0d1eb RS |
10187 | macro_build (&imm_expr, s, s3, xreg); |
10188 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10189 | break; |
10190 | ||
10191 | case M_ABS: | |
10192 | expr1.X_add_number = 0; | |
67c0d1eb | 10193 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10194 | if (xreg != yreg) |
67c0d1eb | 10195 | move_register (xreg, yreg); |
252b5132 | 10196 | expr1.X_add_number = 2; |
67c0d1eb RS |
10197 | macro_build (&expr1, "bteqz", "p"); |
10198 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10199 | } |
10200 | } | |
10201 | ||
10202 | /* For consistency checking, verify that all bits are specified either | |
10203 | by the match/mask part of the instruction definition, or by the | |
10204 | operand list. */ | |
10205 | static int | |
17a2f251 | 10206 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10207 | { |
10208 | const char *p = opc->args; | |
10209 | char c; | |
10210 | unsigned long used_bits = opc->mask; | |
10211 | ||
10212 | if ((used_bits & opc->match) != opc->match) | |
10213 | { | |
10214 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10215 | opc->name, opc->args); | |
10216 | return 0; | |
10217 | } | |
10218 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10219 | while (*p) | |
10220 | switch (c = *p++) | |
10221 | { | |
10222 | case ',': break; | |
10223 | case '(': break; | |
10224 | case ')': break; | |
af7ee8bf CD |
10225 | case '+': |
10226 | switch (c = *p++) | |
10227 | { | |
9bcd4f99 TS |
10228 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10229 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10230 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10231 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10232 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10233 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10234 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10235 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10236 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10237 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10238 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10239 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10240 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10241 | case 'I': break; | |
ef2e4d86 CF |
10242 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10243 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10244 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10245 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10246 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10247 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10248 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10249 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10250 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10251 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10252 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10253 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10254 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10255 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10256 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10257 | |
af7ee8bf CD |
10258 | default: |
10259 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10260 | c, opc->name, opc->args); | |
10261 | return 0; | |
10262 | } | |
10263 | break; | |
252b5132 RH |
10264 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10265 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10266 | case 'A': break; | |
4372b673 | 10267 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10268 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10269 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10270 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10271 | case 'F': break; | |
10272 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10273 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10274 | case 'I': break; |
e972090a | 10275 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10276 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10277 | case 'L': break; |
10278 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10279 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10280 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10281 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10282 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10283 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10284 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10285 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10286 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10287 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10288 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10289 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10290 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10291 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10292 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10293 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10294 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10295 | case 'f': break; | |
10296 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10297 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10298 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10299 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10300 | case 'l': break; | |
10301 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10302 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10303 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10304 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10305 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10306 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10307 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10308 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10309 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10310 | case 'x': break; | |
10311 | case 'z': break; | |
10312 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10313 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10314 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10315 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10316 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10317 | case '[': break; | |
10318 | case ']': break; | |
620edafd | 10319 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10320 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10321 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10322 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10323 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10324 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10325 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10326 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10327 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10328 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10329 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10330 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10331 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10332 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10333 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10334 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10335 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10336 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10337 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10338 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10339 | default: |
10340 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10341 | c, opc->name, opc->args); | |
10342 | return 0; | |
10343 | } | |
10344 | #undef USE_BITS | |
10345 | if (used_bits != 0xffffffff) | |
10346 | { | |
10347 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10348 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10349 | return 0; | |
10350 | } | |
10351 | return 1; | |
10352 | } | |
10353 | ||
df58fc94 RS |
10354 | /* For consistency checking, verify that the length implied matches the |
10355 | major opcode and that all bits are specified either by the match/mask | |
10356 | part of the instruction definition, or by the operand list. */ | |
10357 | ||
10358 | static int | |
10359 | validate_micromips_insn (const struct mips_opcode *opc) | |
10360 | { | |
10361 | unsigned long match = opc->match; | |
10362 | unsigned long mask = opc->mask; | |
10363 | const char *p = opc->args; | |
10364 | unsigned long insn_bits; | |
10365 | unsigned long used_bits; | |
10366 | unsigned long major; | |
10367 | unsigned int length; | |
10368 | char e; | |
10369 | char c; | |
10370 | ||
10371 | if ((mask & match) != match) | |
10372 | { | |
10373 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10374 | opc->name, opc->args); | |
10375 | return 0; | |
10376 | } | |
10377 | length = micromips_insn_length (opc); | |
10378 | if (length != 2 && length != 4) | |
10379 | { | |
10380 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10381 | "%s %s"), length, opc->name, opc->args); | |
10382 | return 0; | |
10383 | } | |
10384 | major = match >> (10 + 8 * (length - 2)); | |
10385 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10386 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10387 | { | |
10388 | as_bad (_("Internal error: bad microMIPS opcode " | |
10389 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10390 | return 0; | |
10391 | } | |
10392 | ||
10393 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10394 | insn_bits = 1 << 4 * length; | |
10395 | insn_bits <<= 4 * length; | |
10396 | insn_bits -= 1; | |
10397 | used_bits = mask; | |
10398 | #define USE_BITS(field) \ | |
10399 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10400 | while (*p) | |
10401 | switch (c = *p++) | |
10402 | { | |
10403 | case ',': break; | |
10404 | case '(': break; | |
10405 | case ')': break; | |
10406 | case '+': | |
10407 | e = c; | |
10408 | switch (c = *p++) | |
10409 | { | |
10410 | case 'A': USE_BITS (EXTLSB); break; | |
10411 | case 'B': USE_BITS (INSMSB); break; | |
10412 | case 'C': USE_BITS (EXTMSBD); break; | |
10413 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10414 | case 'E': USE_BITS (EXTLSB); break; | |
10415 | case 'F': USE_BITS (INSMSB); break; | |
10416 | case 'G': USE_BITS (EXTMSBD); break; | |
10417 | case 'H': USE_BITS (EXTMSBD); break; | |
10418 | default: | |
10419 | as_bad (_("Internal error: bad mips opcode " | |
10420 | "(unknown extension operand type `%c%c'): %s %s"), | |
10421 | e, c, opc->name, opc->args); | |
10422 | return 0; | |
10423 | } | |
10424 | break; | |
10425 | case 'm': | |
10426 | e = c; | |
10427 | switch (c = *p++) | |
10428 | { | |
10429 | case 'A': USE_BITS (IMMA); break; | |
10430 | case 'B': USE_BITS (IMMB); break; | |
10431 | case 'C': USE_BITS (IMMC); break; | |
10432 | case 'D': USE_BITS (IMMD); break; | |
10433 | case 'E': USE_BITS (IMME); break; | |
10434 | case 'F': USE_BITS (IMMF); break; | |
10435 | case 'G': USE_BITS (IMMG); break; | |
10436 | case 'H': USE_BITS (IMMH); break; | |
10437 | case 'I': USE_BITS (IMMI); break; | |
10438 | case 'J': USE_BITS (IMMJ); break; | |
10439 | case 'L': USE_BITS (IMML); break; | |
10440 | case 'M': USE_BITS (IMMM); break; | |
10441 | case 'N': USE_BITS (IMMN); break; | |
10442 | case 'O': USE_BITS (IMMO); break; | |
10443 | case 'P': USE_BITS (IMMP); break; | |
10444 | case 'Q': USE_BITS (IMMQ); break; | |
10445 | case 'U': USE_BITS (IMMU); break; | |
10446 | case 'W': USE_BITS (IMMW); break; | |
10447 | case 'X': USE_BITS (IMMX); break; | |
10448 | case 'Y': USE_BITS (IMMY); break; | |
10449 | case 'Z': break; | |
10450 | case 'a': break; | |
10451 | case 'b': USE_BITS (MB); break; | |
10452 | case 'c': USE_BITS (MC); break; | |
10453 | case 'd': USE_BITS (MD); break; | |
10454 | case 'e': USE_BITS (ME); break; | |
10455 | case 'f': USE_BITS (MF); break; | |
10456 | case 'g': USE_BITS (MG); break; | |
10457 | case 'h': USE_BITS (MH); break; | |
10458 | case 'i': USE_BITS (MI); break; | |
10459 | case 'j': USE_BITS (MJ); break; | |
10460 | case 'l': USE_BITS (ML); break; | |
10461 | case 'm': USE_BITS (MM); break; | |
10462 | case 'n': USE_BITS (MN); break; | |
10463 | case 'p': USE_BITS (MP); break; | |
10464 | case 'q': USE_BITS (MQ); break; | |
10465 | case 'r': break; | |
10466 | case 's': break; | |
10467 | case 't': break; | |
10468 | case 'x': break; | |
10469 | case 'y': break; | |
10470 | case 'z': break; | |
10471 | default: | |
10472 | as_bad (_("Internal error: bad mips opcode " | |
10473 | "(unknown extension operand type `%c%c'): %s %s"), | |
10474 | e, c, opc->name, opc->args); | |
10475 | return 0; | |
10476 | } | |
10477 | break; | |
10478 | case '.': USE_BITS (OFFSET10); break; | |
10479 | case '1': USE_BITS (STYPE); break; | |
10480 | case '<': USE_BITS (SHAMT); break; | |
10481 | case '>': USE_BITS (SHAMT); break; | |
10482 | case 'B': USE_BITS (CODE10); break; | |
10483 | case 'C': USE_BITS (COPZ); break; | |
10484 | case 'D': USE_BITS (FD); break; | |
10485 | case 'E': USE_BITS (RT); break; | |
10486 | case 'G': USE_BITS (RS); break; | |
444d75be | 10487 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10488 | case 'K': USE_BITS (RS); break; |
10489 | case 'M': USE_BITS (CCC); break; | |
10490 | case 'N': USE_BITS (BCC); break; | |
10491 | case 'R': USE_BITS (FR); break; | |
10492 | case 'S': USE_BITS (FS); break; | |
10493 | case 'T': USE_BITS (FT); break; | |
10494 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10495 | case '\\': USE_BITS (3BITPOS); break; |
df58fc94 RS |
10496 | case 'a': USE_BITS (TARGET); break; |
10497 | case 'b': USE_BITS (RS); break; | |
10498 | case 'c': USE_BITS (CODE); break; | |
10499 | case 'd': USE_BITS (RD); break; | |
10500 | case 'h': USE_BITS (PREFX); break; | |
10501 | case 'i': USE_BITS (IMMEDIATE); break; | |
10502 | case 'j': USE_BITS (DELTA); break; | |
10503 | case 'k': USE_BITS (CACHE); break; | |
10504 | case 'n': USE_BITS (RT); break; | |
10505 | case 'o': USE_BITS (DELTA); break; | |
10506 | case 'p': USE_BITS (DELTA); break; | |
10507 | case 'q': USE_BITS (CODE2); break; | |
10508 | case 'r': USE_BITS (RS); break; | |
10509 | case 's': USE_BITS (RS); break; | |
10510 | case 't': USE_BITS (RT); break; | |
10511 | case 'u': USE_BITS (IMMEDIATE); break; | |
10512 | case 'v': USE_BITS (RS); break; | |
10513 | case 'w': USE_BITS (RT); break; | |
10514 | case 'y': USE_BITS (RS3); break; | |
10515 | case 'z': break; | |
10516 | case '|': USE_BITS (TRAP); break; | |
10517 | case '~': USE_BITS (OFFSET12); break; | |
10518 | default: | |
10519 | as_bad (_("Internal error: bad microMIPS opcode " | |
10520 | "(unknown operand type `%c'): %s %s"), | |
10521 | c, opc->name, opc->args); | |
10522 | return 0; | |
10523 | } | |
10524 | #undef USE_BITS | |
10525 | if (used_bits != insn_bits) | |
10526 | { | |
10527 | if (~used_bits & insn_bits) | |
10528 | as_bad (_("Internal error: bad microMIPS opcode " | |
10529 | "(bits 0x%lx undefined): %s %s"), | |
10530 | ~used_bits & insn_bits, opc->name, opc->args); | |
10531 | if (used_bits & ~insn_bits) | |
10532 | as_bad (_("Internal error: bad microMIPS opcode " | |
10533 | "(bits 0x%lx defined): %s %s"), | |
10534 | used_bits & ~insn_bits, opc->name, opc->args); | |
10535 | return 0; | |
10536 | } | |
10537 | return 1; | |
10538 | } | |
10539 | ||
9bcd4f99 TS |
10540 | /* UDI immediates. */ |
10541 | struct mips_immed { | |
10542 | char type; | |
10543 | unsigned int shift; | |
10544 | unsigned long mask; | |
10545 | const char * desc; | |
10546 | }; | |
10547 | ||
10548 | static const struct mips_immed mips_immed[] = { | |
10549 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10550 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10551 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10552 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10553 | { 0,0,0,0 } | |
10554 | }; | |
10555 | ||
7455baf8 TS |
10556 | /* Check whether an odd floating-point register is allowed. */ |
10557 | static int | |
10558 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10559 | { | |
10560 | const char *s = insn->name; | |
10561 | ||
10562 | if (insn->pinfo == INSN_MACRO) | |
10563 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10564 | return 1; | |
10565 | ||
10566 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
10567 | { | |
10568 | /* Allow odd registers for single-precision ops. */ | |
10569 | switch (insn->pinfo & (FP_S | FP_D)) | |
10570 | { | |
10571 | case FP_S: | |
10572 | case 0: | |
10573 | return 1; /* both single precision - ok */ | |
10574 | case FP_D: | |
10575 | return 0; /* both double precision - fail */ | |
10576 | default: | |
10577 | break; | |
10578 | } | |
10579 | ||
10580 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10581 | s = strchr (insn->name, '.'); | |
10582 | if (argnum == 2) | |
10583 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10584 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10585 | } | |
10586 | ||
10587 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10588 | if ((insn->pinfo & FP_S) | |
10589 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10590 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10591 | return 1; | |
10592 | ||
10593 | return 0; | |
10594 | } | |
10595 | ||
df58fc94 RS |
10596 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10597 | taking bits from BIT up. */ | |
10598 | static int | |
10599 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10600 | { | |
10601 | return (ep->X_op == O_constant | |
10602 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10603 | && ep->X_add_number >= min << bit | |
10604 | && ep->X_add_number < max << bit); | |
10605 | } | |
10606 | ||
252b5132 RH |
10607 | /* This routine assembles an instruction into its binary format. As a |
10608 | side effect, it sets one of the global variables imm_reloc or | |
10609 | offset_reloc to the type of relocation to do if one of the operands | |
10610 | is an address expression. */ | |
10611 | ||
10612 | static void | |
17a2f251 | 10613 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10614 | { |
df58fc94 RS |
10615 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10616 | bfd_boolean need_delay_slot_ok = TRUE; | |
10617 | struct mips_opcode *firstinsn = NULL; | |
10618 | const struct mips_opcode *past; | |
10619 | struct hash_control *hash; | |
252b5132 RH |
10620 | char *s; |
10621 | const char *args; | |
43841e91 | 10622 | char c = 0; |
252b5132 RH |
10623 | struct mips_opcode *insn; |
10624 | char *argsStart; | |
10625 | unsigned int regno; | |
34224acf | 10626 | unsigned int lastregno; |
df58fc94 | 10627 | unsigned int destregno = 0; |
af7ee8bf | 10628 | unsigned int lastpos = 0; |
071742cf | 10629 | unsigned int limlo, limhi; |
252b5132 | 10630 | char *s_reset; |
74cd071d | 10631 | offsetT min_range, max_range; |
df58fc94 | 10632 | long opend; |
a40bc9dd | 10633 | char *name; |
707bfff6 TS |
10634 | int argnum; |
10635 | unsigned int rtype; | |
df58fc94 | 10636 | char *dot; |
a40bc9dd | 10637 | long end; |
252b5132 RH |
10638 | |
10639 | insn_error = NULL; | |
10640 | ||
df58fc94 RS |
10641 | if (mips_opts.micromips) |
10642 | { | |
10643 | hash = micromips_op_hash; | |
10644 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10645 | } | |
10646 | else | |
10647 | { | |
10648 | hash = op_hash; | |
10649 | past = &mips_opcodes[NUMOPCODES]; | |
10650 | } | |
10651 | forced_insn_length = 0; | |
252b5132 | 10652 | insn = NULL; |
252b5132 | 10653 | |
df58fc94 | 10654 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10655 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10656 | continue; | |
bdaaa2e1 | 10657 | |
a40bc9dd RS |
10658 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10659 | name = alloca (end + 1); | |
10660 | memcpy (name, str, end); | |
10661 | name[end] = '\0'; | |
252b5132 | 10662 | |
df58fc94 RS |
10663 | for (;;) |
10664 | { | |
10665 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10666 | ||
10667 | if (insn != NULL || !mips_opts.micromips) | |
10668 | break; | |
10669 | if (forced_insn_length) | |
10670 | break; | |
10671 | ||
10672 | /* See if there's an instruction size override suffix, | |
10673 | either `16' or `32', at the end of the mnemonic proper, | |
10674 | that defines the operation, i.e. before the first `.' | |
10675 | character if any. Strip it and retry. */ | |
10676 | dot = strchr (name, '.'); | |
10677 | opend = dot != NULL ? dot - name : end; | |
10678 | if (opend < 3) | |
10679 | break; | |
10680 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10681 | forced_insn_length = 2; | |
10682 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10683 | forced_insn_length = 4; | |
10684 | else | |
10685 | break; | |
10686 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10687 | } | |
252b5132 RH |
10688 | if (insn == NULL) |
10689 | { | |
a40bc9dd RS |
10690 | insn_error = _("Unrecognized opcode"); |
10691 | return; | |
252b5132 RH |
10692 | } |
10693 | ||
df58fc94 RS |
10694 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10695 | we make up to two passes over the relevant fragment of the opcode | |
10696 | table. First we try instructions that meet the delay slot's length | |
10697 | requirement. If none matched, then we retry with the remaining ones | |
10698 | and if one matches, then we use it and then issue an appropriate | |
10699 | warning later on. */ | |
a40bc9dd | 10700 | argsStart = s = str + end; |
252b5132 RH |
10701 | for (;;) |
10702 | { | |
df58fc94 RS |
10703 | bfd_boolean delay_slot_ok; |
10704 | bfd_boolean size_ok; | |
b34976b6 | 10705 | bfd_boolean ok; |
252b5132 | 10706 | |
a40bc9dd | 10707 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10708 | |
f79e2745 | 10709 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10710 | size_ok = is_size_valid (insn); |
10711 | delay_slot_ok = is_delay_slot_valid (insn); | |
10712 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10713 | { |
df58fc94 RS |
10714 | firstinsn = insn; |
10715 | wrong_delay_slot_insns = TRUE; | |
10716 | } | |
10717 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10718 | { | |
10719 | static char buf[256]; | |
10720 | ||
10721 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10722 | { |
10723 | ++insn; | |
10724 | continue; | |
10725 | } | |
df58fc94 | 10726 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10727 | { |
df58fc94 RS |
10728 | gas_assert (firstinsn); |
10729 | need_delay_slot_ok = FALSE; | |
10730 | past = insn + 1; | |
10731 | insn = firstinsn; | |
10732 | continue; | |
252b5132 | 10733 | } |
df58fc94 RS |
10734 | |
10735 | if (insn_error) | |
10736 | return; | |
10737 | ||
10738 | if (!ok) | |
7bd942df | 10739 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
10740 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
10741 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10742 | else | |
10743 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10744 | 8 * forced_insn_length); | |
10745 | insn_error = buf; | |
10746 | ||
10747 | return; | |
252b5132 RH |
10748 | } |
10749 | ||
1e915849 | 10750 | create_insn (ip, insn); |
268f6bed | 10751 | insn_error = NULL; |
707bfff6 | 10752 | argnum = 1; |
24864476 | 10753 | lastregno = 0xffffffff; |
252b5132 RH |
10754 | for (args = insn->args;; ++args) |
10755 | { | |
deec1734 CD |
10756 | int is_mdmx; |
10757 | ||
ad8d3bb3 | 10758 | s += strspn (s, " \t"); |
deec1734 | 10759 | is_mdmx = 0; |
252b5132 RH |
10760 | switch (*args) |
10761 | { | |
10762 | case '\0': /* end of args */ | |
10763 | if (*s == '\0') | |
10764 | return; | |
10765 | break; | |
10766 | ||
90ecf173 | 10767 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
df58fc94 | 10768 | gas_assert (!mips_opts.micromips); |
8b082fb1 TS |
10769 | my_getExpression (&imm_expr, s); |
10770 | check_absolute_expr (ip, &imm_expr); | |
10771 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10772 | && (unsigned long) imm_expr.X_add_number != 3) | |
10773 | { | |
10774 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10775 | (unsigned long) imm_expr.X_add_number); | |
10776 | } | |
df58fc94 | 10777 | INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number); |
8b082fb1 TS |
10778 | imm_expr.X_op = O_absent; |
10779 | s = expr_end; | |
10780 | continue; | |
10781 | ||
90ecf173 | 10782 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
df58fc94 | 10783 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10784 | my_getExpression (&imm_expr, s); |
10785 | check_absolute_expr (ip, &imm_expr); | |
10786 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
10787 | { | |
a9e24354 TS |
10788 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10789 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10790 | } |
df58fc94 | 10791 | INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
10792 | imm_expr.X_op = O_absent; |
10793 | s = expr_end; | |
10794 | continue; | |
10795 | ||
90ecf173 | 10796 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
df58fc94 | 10797 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10798 | my_getExpression (&imm_expr, s); |
10799 | check_absolute_expr (ip, &imm_expr); | |
10800 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
10801 | { | |
a9e24354 TS |
10802 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10803 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10804 | } |
df58fc94 | 10805 | INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
10806 | imm_expr.X_op = O_absent; |
10807 | s = expr_end; | |
10808 | continue; | |
10809 | ||
90ecf173 | 10810 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
df58fc94 | 10811 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10812 | my_getExpression (&imm_expr, s); |
10813 | check_absolute_expr (ip, &imm_expr); | |
10814 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
10815 | { | |
a9e24354 TS |
10816 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10817 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10818 | } |
df58fc94 | 10819 | INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
10820 | imm_expr.X_op = O_absent; |
10821 | s = expr_end; | |
10822 | continue; | |
10823 | ||
90ecf173 | 10824 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
df58fc94 | 10825 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10826 | my_getExpression (&imm_expr, s); |
10827 | check_absolute_expr (ip, &imm_expr); | |
10828 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
10829 | { | |
a9e24354 TS |
10830 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10831 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10832 | } |
df58fc94 | 10833 | INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
10834 | imm_expr.X_op = O_absent; |
10835 | s = expr_end; | |
10836 | continue; | |
10837 | ||
90ecf173 | 10838 | case '7': /* Four DSP accumulators in bits 11,12. */ |
df58fc94 | 10839 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10840 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10841 | s[3] >= '0' && s[3] <= '3') | |
10842 | { | |
10843 | regno = s[3] - '0'; | |
10844 | s += 4; | |
df58fc94 | 10845 | INSERT_OPERAND (0, DSPACC, *ip, regno); |
74cd071d CF |
10846 | continue; |
10847 | } | |
10848 | else | |
10849 | as_bad (_("Invalid dsp acc register")); | |
10850 | break; | |
10851 | ||
90ecf173 | 10852 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
df58fc94 | 10853 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10854 | my_getExpression (&imm_expr, s); |
10855 | check_absolute_expr (ip, &imm_expr); | |
10856 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
10857 | { | |
a9e24354 TS |
10858 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10859 | OP_MASK_WRDSP, | |
10860 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10861 | } |
df58fc94 | 10862 | INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10863 | imm_expr.X_op = O_absent; |
10864 | s = expr_end; | |
10865 | continue; | |
10866 | ||
90ecf173 | 10867 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 10868 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10869 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10870 | s[3] >= '0' && s[3] <= '3') | |
10871 | { | |
10872 | regno = s[3] - '0'; | |
10873 | s += 4; | |
df58fc94 | 10874 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
10875 | continue; |
10876 | } | |
10877 | else | |
10878 | as_bad (_("Invalid dsp acc register")); | |
10879 | break; | |
10880 | ||
90ecf173 | 10881 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
df58fc94 | 10882 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10883 | my_getExpression (&imm_expr, s); |
10884 | check_absolute_expr (ip, &imm_expr); | |
10885 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
10886 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
10887 | if (imm_expr.X_add_number < min_range || | |
10888 | imm_expr.X_add_number > max_range) | |
10889 | { | |
a9e24354 TS |
10890 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10891 | (long) min_range, (long) max_range, | |
10892 | (long) imm_expr.X_add_number); | |
74cd071d | 10893 | } |
df58fc94 | 10894 | INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
10895 | imm_expr.X_op = O_absent; |
10896 | s = expr_end; | |
10897 | continue; | |
10898 | ||
90ecf173 | 10899 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 10900 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10901 | my_getExpression (&imm_expr, s); |
10902 | check_absolute_expr (ip, &imm_expr); | |
10903 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
10904 | { | |
a9e24354 TS |
10905 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10906 | OP_MASK_RDDSP, | |
10907 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10908 | } |
df58fc94 | 10909 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10910 | imm_expr.X_op = O_absent; |
10911 | s = expr_end; | |
10912 | continue; | |
10913 | ||
90ecf173 | 10914 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 10915 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10916 | my_getExpression (&imm_expr, s); |
10917 | check_absolute_expr (ip, &imm_expr); | |
10918 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
10919 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
10920 | if (imm_expr.X_add_number < min_range || | |
10921 | imm_expr.X_add_number > max_range) | |
10922 | { | |
a9e24354 TS |
10923 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10924 | (long) min_range, (long) max_range, | |
10925 | (long) imm_expr.X_add_number); | |
74cd071d | 10926 | } |
df58fc94 | 10927 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
10928 | imm_expr.X_op = O_absent; |
10929 | s = expr_end; | |
10930 | continue; | |
10931 | ||
90ecf173 | 10932 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
df58fc94 | 10933 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10934 | my_getExpression (&imm_expr, s); |
10935 | check_absolute_expr (ip, &imm_expr); | |
10936 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
10937 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
10938 | if (imm_expr.X_add_number < min_range || | |
10939 | imm_expr.X_add_number > max_range) | |
10940 | { | |
a9e24354 TS |
10941 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10942 | (long) min_range, (long) max_range, | |
10943 | (long) imm_expr.X_add_number); | |
74cd071d | 10944 | } |
df58fc94 | 10945 | INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
10946 | imm_expr.X_op = O_absent; |
10947 | s = expr_end; | |
10948 | continue; | |
10949 | ||
a9e24354 | 10950 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 10951 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10952 | my_getExpression (&imm_expr, s); |
10953 | check_absolute_expr (ip, &imm_expr); | |
10954 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
10955 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
10956 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10957 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10958 | imm_expr.X_op = O_absent; |
10959 | s = expr_end; | |
10960 | continue; | |
10961 | ||
a9e24354 | 10962 | case '$': /* MT load high flag bit. */ |
df58fc94 | 10963 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10964 | my_getExpression (&imm_expr, s); |
10965 | check_absolute_expr (ip, &imm_expr); | |
10966 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
10967 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
10968 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10969 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10970 | imm_expr.X_op = O_absent; |
10971 | s = expr_end; | |
10972 | continue; | |
10973 | ||
90ecf173 | 10974 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 10975 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10976 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10977 | s[3] >= '0' && s[3] <= '3') | |
10978 | { | |
10979 | regno = s[3] - '0'; | |
10980 | s += 4; | |
df58fc94 | 10981 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
10982 | continue; |
10983 | } | |
10984 | else | |
10985 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10986 | break; | |
10987 | ||
90ecf173 | 10988 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 10989 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10990 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10991 | s[3] >= '0' && s[3] <= '3') | |
10992 | { | |
10993 | regno = s[3] - '0'; | |
10994 | s += 4; | |
df58fc94 | 10995 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
10996 | continue; |
10997 | } | |
10998 | else | |
10999 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11000 | break; | |
11001 | ||
dec0624d MR |
11002 | case '\\': /* 3-bit bit position. */ |
11003 | { | |
2906b037 MR |
11004 | unsigned long mask = (mips_opts.micromips |
11005 | ? MICROMIPSOP_MASK_3BITPOS | |
11006 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11007 | |
11008 | my_getExpression (&imm_expr, s); | |
11009 | check_absolute_expr (ip, &imm_expr); | |
11010 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11011 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11012 | ip->insn_mo->name, | |
11013 | mask, (unsigned long) imm_expr.X_add_number); | |
11014 | INSERT_OPERAND (mips_opts.micromips, | |
11015 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11016 | imm_expr.X_op = O_absent; | |
11017 | s = expr_end; | |
11018 | } | |
11019 | continue; | |
11020 | ||
252b5132 | 11021 | case ',': |
a339155f | 11022 | ++argnum; |
252b5132 RH |
11023 | if (*s++ == *args) |
11024 | continue; | |
11025 | s--; | |
11026 | switch (*++args) | |
11027 | { | |
11028 | case 'r': | |
11029 | case 'v': | |
df58fc94 | 11030 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11031 | continue; |
11032 | ||
11033 | case 'w': | |
df58fc94 | 11034 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11035 | continue; |
11036 | ||
252b5132 | 11037 | case 'W': |
df58fc94 RS |
11038 | gas_assert (!mips_opts.micromips); |
11039 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11040 | continue; |
11041 | ||
11042 | case 'V': | |
df58fc94 | 11043 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11044 | continue; |
11045 | } | |
11046 | break; | |
11047 | ||
11048 | case '(': | |
11049 | /* Handle optional base register. | |
11050 | Either the base register is omitted or | |
bdaaa2e1 | 11051 | we must have a left paren. */ |
252b5132 RH |
11052 | /* This is dependent on the next operand specifier |
11053 | is a base register specification. */ | |
df58fc94 RS |
11054 | gas_assert (args[1] == 'b' |
11055 | || (mips_opts.micromips | |
11056 | && args[1] == 'm' | |
11057 | && (args[2] == 'l' || args[2] == 'n' | |
11058 | || args[2] == 's' || args[2] == 'a'))); | |
11059 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11060 | return; |
df58fc94 | 11061 | /* Fall through. */ |
252b5132 | 11062 | |
90ecf173 | 11063 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11064 | if (*s++ == *args) |
11065 | continue; | |
11066 | break; | |
11067 | ||
11068 | case '[': /* These must match exactly. */ | |
60b63b72 | 11069 | case ']': |
df58fc94 | 11070 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11071 | if (*s++ == *args) |
11072 | continue; | |
11073 | break; | |
11074 | ||
af7ee8bf CD |
11075 | case '+': /* Opcode extension character. */ |
11076 | switch (*++args) | |
11077 | { | |
9bcd4f99 TS |
11078 | case '1': /* UDI immediates. */ |
11079 | case '2': | |
11080 | case '3': | |
11081 | case '4': | |
df58fc94 | 11082 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11083 | { |
11084 | const struct mips_immed *imm = mips_immed; | |
11085 | ||
11086 | while (imm->type && imm->type != *args) | |
11087 | ++imm; | |
11088 | if (! imm->type) | |
11089 | internalError (); | |
11090 | my_getExpression (&imm_expr, s); | |
11091 | check_absolute_expr (ip, &imm_expr); | |
11092 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11093 | { | |
11094 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11095 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11096 | (unsigned long) imm_expr.X_add_number, | |
11097 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11098 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11099 | } |
11100 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11101 | << imm->shift); | |
11102 | imm_expr.X_op = O_absent; | |
11103 | s = expr_end; | |
11104 | } | |
11105 | continue; | |
90ecf173 | 11106 | |
071742cf CD |
11107 | case 'A': /* ins/ext position, becomes LSB. */ |
11108 | limlo = 0; | |
11109 | limhi = 31; | |
5f74bc13 CD |
11110 | goto do_lsb; |
11111 | case 'E': | |
11112 | limlo = 32; | |
11113 | limhi = 63; | |
11114 | goto do_lsb; | |
90ecf173 | 11115 | do_lsb: |
071742cf CD |
11116 | my_getExpression (&imm_expr, s); |
11117 | check_absolute_expr (ip, &imm_expr); | |
11118 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11119 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11120 | { | |
11121 | as_bad (_("Improper position (%lu)"), | |
11122 | (unsigned long) imm_expr.X_add_number); | |
11123 | imm_expr.X_add_number = limlo; | |
11124 | } | |
11125 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11126 | INSERT_OPERAND (mips_opts.micromips, |
11127 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11128 | imm_expr.X_op = O_absent; |
11129 | s = expr_end; | |
11130 | continue; | |
11131 | ||
11132 | case 'B': /* ins size, becomes MSB. */ | |
11133 | limlo = 1; | |
11134 | limhi = 32; | |
5f74bc13 CD |
11135 | goto do_msb; |
11136 | case 'F': | |
11137 | limlo = 33; | |
11138 | limhi = 64; | |
11139 | goto do_msb; | |
90ecf173 | 11140 | do_msb: |
071742cf CD |
11141 | my_getExpression (&imm_expr, s); |
11142 | check_absolute_expr (ip, &imm_expr); | |
11143 | /* Check for negative input so that small negative numbers | |
11144 | will not succeed incorrectly. The checks against | |
11145 | (pos+size) transitively check "size" itself, | |
11146 | assuming that "pos" is reasonable. */ | |
11147 | if ((long) imm_expr.X_add_number < 0 | |
11148 | || ((unsigned long) imm_expr.X_add_number | |
11149 | + lastpos) < limlo | |
11150 | || ((unsigned long) imm_expr.X_add_number | |
11151 | + lastpos) > limhi) | |
11152 | { | |
11153 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11154 | (unsigned long) imm_expr.X_add_number, | |
11155 | (unsigned long) lastpos); | |
11156 | imm_expr.X_add_number = limlo - lastpos; | |
11157 | } | |
df58fc94 RS |
11158 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11159 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11160 | imm_expr.X_op = O_absent; |
11161 | s = expr_end; | |
11162 | continue; | |
11163 | ||
11164 | case 'C': /* ext size, becomes MSBD. */ | |
11165 | limlo = 1; | |
11166 | limhi = 32; | |
5f74bc13 CD |
11167 | goto do_msbd; |
11168 | case 'G': | |
11169 | limlo = 33; | |
11170 | limhi = 64; | |
11171 | goto do_msbd; | |
11172 | case 'H': | |
11173 | limlo = 33; | |
11174 | limhi = 64; | |
11175 | goto do_msbd; | |
90ecf173 | 11176 | do_msbd: |
071742cf CD |
11177 | my_getExpression (&imm_expr, s); |
11178 | check_absolute_expr (ip, &imm_expr); | |
11179 | /* Check for negative input so that small negative numbers | |
11180 | will not succeed incorrectly. The checks against | |
11181 | (pos+size) transitively check "size" itself, | |
11182 | assuming that "pos" is reasonable. */ | |
11183 | if ((long) imm_expr.X_add_number < 0 | |
11184 | || ((unsigned long) imm_expr.X_add_number | |
11185 | + lastpos) < limlo | |
11186 | || ((unsigned long) imm_expr.X_add_number | |
11187 | + lastpos) > limhi) | |
11188 | { | |
11189 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11190 | (unsigned long) imm_expr.X_add_number, | |
11191 | (unsigned long) lastpos); | |
11192 | imm_expr.X_add_number = limlo - lastpos; | |
11193 | } | |
df58fc94 RS |
11194 | INSERT_OPERAND (mips_opts.micromips, |
11195 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11196 | imm_expr.X_op = O_absent; |
11197 | s = expr_end; | |
11198 | continue; | |
af7ee8bf | 11199 | |
bbcc0807 CD |
11200 | case 'D': |
11201 | /* +D is for disassembly only; never match. */ | |
11202 | break; | |
11203 | ||
5f74bc13 CD |
11204 | case 'I': |
11205 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11206 | my_getExpression (&imm2_expr, s); | |
11207 | if (imm2_expr.X_op != O_big | |
11208 | && imm2_expr.X_op != O_constant) | |
11209 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11210 | if (HAVE_32BIT_GPRS) |
11211 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11212 | s = expr_end; |
11213 | continue; | |
11214 | ||
707bfff6 | 11215 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11216 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11217 | /* +T is for disassembly only; never match. */ |
11218 | break; | |
11219 | ||
707bfff6 | 11220 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11221 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11222 | if (s[0] == '$' && ISDIGIT (s[1])) |
11223 | { | |
11224 | ++s; | |
11225 | regno = 0; | |
11226 | do | |
11227 | { | |
11228 | regno *= 10; | |
11229 | regno += *s - '0'; | |
11230 | ++s; | |
11231 | } | |
11232 | while (ISDIGIT (*s)); | |
11233 | if (regno > 31) | |
11234 | as_bad (_("Invalid register number (%d)"), regno); | |
11235 | else | |
11236 | { | |
df58fc94 | 11237 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11238 | continue; |
11239 | } | |
11240 | } | |
11241 | else | |
11242 | as_bad (_("Invalid coprocessor 0 register number")); | |
11243 | break; | |
11244 | ||
bb35fb24 NC |
11245 | case 'x': |
11246 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11247 | is not in the valid range. */ | |
df58fc94 | 11248 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11249 | my_getExpression (&imm_expr, s); |
11250 | check_absolute_expr (ip, &imm_expr); | |
11251 | if ((unsigned) imm_expr.X_add_number > 31) | |
11252 | { | |
11253 | as_bad (_("Improper bit index (%lu)"), | |
11254 | (unsigned long) imm_expr.X_add_number); | |
11255 | imm_expr.X_add_number = 0; | |
11256 | } | |
df58fc94 | 11257 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11258 | imm_expr.X_op = O_absent; |
11259 | s = expr_end; | |
11260 | continue; | |
11261 | ||
11262 | case 'X': | |
11263 | /* bbit[01] bit index when bbit is used but we generate | |
11264 | bbit[01]32 because the index is over 32. Move to the | |
11265 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11266 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11267 | my_getExpression (&imm_expr, s); |
11268 | check_absolute_expr (ip, &imm_expr); | |
11269 | if ((unsigned) imm_expr.X_add_number < 32 | |
11270 | || (unsigned) imm_expr.X_add_number > 63) | |
11271 | break; | |
df58fc94 | 11272 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11273 | imm_expr.X_op = O_absent; |
11274 | s = expr_end; | |
11275 | continue; | |
11276 | ||
11277 | case 'p': | |
11278 | /* cins, cins32, exts and exts32 position field. Give error | |
11279 | if it's not in the valid range. */ | |
df58fc94 | 11280 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11281 | my_getExpression (&imm_expr, s); |
11282 | check_absolute_expr (ip, &imm_expr); | |
11283 | if ((unsigned) imm_expr.X_add_number > 31) | |
11284 | { | |
11285 | as_bad (_("Improper position (%lu)"), | |
11286 | (unsigned long) imm_expr.X_add_number); | |
11287 | imm_expr.X_add_number = 0; | |
11288 | } | |
11289 | /* Make the pos explicit to simplify +S. */ | |
11290 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11291 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11292 | imm_expr.X_op = O_absent; |
11293 | s = expr_end; | |
11294 | continue; | |
11295 | ||
11296 | case 'P': | |
11297 | /* cins, cins32, exts and exts32 position field. Move to | |
11298 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11299 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11300 | my_getExpression (&imm_expr, s); |
11301 | check_absolute_expr (ip, &imm_expr); | |
11302 | if ((unsigned) imm_expr.X_add_number < 32 | |
11303 | || (unsigned) imm_expr.X_add_number > 63) | |
11304 | break; | |
11305 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11306 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11307 | imm_expr.X_op = O_absent; |
11308 | s = expr_end; | |
11309 | continue; | |
11310 | ||
11311 | case 's': | |
11312 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11313 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11314 | my_getExpression (&imm_expr, s); |
11315 | check_absolute_expr (ip, &imm_expr); | |
11316 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11317 | { | |
11318 | as_bad (_("Improper size (%lu)"), | |
11319 | (unsigned long) imm_expr.X_add_number); | |
11320 | imm_expr.X_add_number = 0; | |
11321 | } | |
df58fc94 | 11322 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11323 | imm_expr.X_op = O_absent; |
11324 | s = expr_end; | |
11325 | continue; | |
11326 | ||
11327 | case 'S': | |
11328 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11329 | length-minus-one field. */ | |
df58fc94 | 11330 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11331 | my_getExpression (&imm_expr, s); |
11332 | check_absolute_expr (ip, &imm_expr); | |
11333 | if ((long) imm_expr.X_add_number < 0 | |
11334 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11335 | { | |
11336 | as_bad (_("Improper size (%lu)"), | |
11337 | (unsigned long) imm_expr.X_add_number); | |
11338 | imm_expr.X_add_number = 0; | |
11339 | } | |
df58fc94 | 11340 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11341 | imm_expr.X_op = O_absent; |
11342 | s = expr_end; | |
11343 | continue; | |
11344 | ||
dd3cbb7e NC |
11345 | case 'Q': |
11346 | /* seqi/snei immediate field. */ | |
df58fc94 | 11347 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11348 | my_getExpression (&imm_expr, s); |
11349 | check_absolute_expr (ip, &imm_expr); | |
11350 | if ((long) imm_expr.X_add_number < -512 | |
11351 | || (long) imm_expr.X_add_number >= 512) | |
11352 | { | |
11353 | as_bad (_("Improper immediate (%ld)"), | |
11354 | (long) imm_expr.X_add_number); | |
11355 | imm_expr.X_add_number = 0; | |
11356 | } | |
df58fc94 | 11357 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11358 | imm_expr.X_op = O_absent; |
11359 | s = expr_end; | |
11360 | continue; | |
11361 | ||
98675402 | 11362 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11363 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11364 | my_getExpression (&imm_expr, s); |
11365 | check_absolute_expr (ip, &imm_expr); | |
11366 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11367 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11368 | if (imm_expr.X_add_number < min_range | |
11369 | || imm_expr.X_add_number > max_range) | |
11370 | { | |
c95354ed | 11371 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11372 | (long) min_range, (long) max_range, |
11373 | (long) imm_expr.X_add_number); | |
11374 | } | |
df58fc94 | 11375 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11376 | imm_expr.X_op = O_absent; |
11377 | s = expr_end; | |
11378 | continue; | |
11379 | ||
11380 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11381 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11382 | my_getExpression (&imm_expr, s); |
11383 | check_absolute_expr (ip, &imm_expr); | |
11384 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11385 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11386 | if (imm_expr.X_add_number < min_range | |
11387 | || imm_expr.X_add_number > max_range) | |
11388 | { | |
c95354ed | 11389 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11390 | (long) min_range, (long) max_range, |
11391 | (long) imm_expr.X_add_number); | |
11392 | } | |
df58fc94 | 11393 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11394 | imm_expr.X_op = O_absent; |
11395 | s = expr_end; | |
11396 | continue; | |
11397 | ||
11398 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11399 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11400 | my_getExpression (&imm_expr, s); |
11401 | check_absolute_expr (ip, &imm_expr); | |
11402 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11403 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11404 | /* We check the offset range before adjusted. */ |
11405 | min_range <<= 4; | |
11406 | max_range <<= 4; | |
98675402 RS |
11407 | if (imm_expr.X_add_number < min_range |
11408 | || imm_expr.X_add_number > max_range) | |
11409 | { | |
c95354ed | 11410 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11411 | (long) min_range, (long) max_range, |
11412 | (long) imm_expr.X_add_number); | |
11413 | } | |
c95354ed MX |
11414 | if (imm_expr.X_add_number & 0xf) |
11415 | { | |
11416 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11417 | (long) imm_expr.X_add_number); | |
11418 | } | |
11419 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11420 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11421 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11422 | imm_expr.X_op = O_absent; |
11423 | s = expr_end; | |
11424 | continue; | |
11425 | ||
11426 | case 'z': | |
df58fc94 | 11427 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11428 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11429 | break; | |
11430 | if (regno == AT && mips_opts.at) | |
11431 | { | |
11432 | if (mips_opts.at == ATREG) | |
11433 | as_warn (_("used $at without \".set noat\"")); | |
11434 | else | |
11435 | as_warn (_("used $%u with \".set at=$%u\""), | |
11436 | regno, mips_opts.at); | |
11437 | } | |
df58fc94 | 11438 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11439 | continue; |
11440 | ||
11441 | case 'Z': | |
df58fc94 | 11442 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11443 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11444 | break; | |
df58fc94 | 11445 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11446 | continue; |
11447 | ||
af7ee8bf | 11448 | default: |
df58fc94 | 11449 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11450 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11451 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11452 | *args, insn->name, insn->args); |
af7ee8bf CD |
11453 | /* Further processing is fruitless. */ |
11454 | return; | |
11455 | } | |
11456 | break; | |
11457 | ||
df58fc94 | 11458 | case '.': /* 10-bit offset. */ |
df58fc94 | 11459 | gas_assert (mips_opts.micromips); |
dec0624d | 11460 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11461 | { |
11462 | int shift = *args == '.' ? 9 : 11; | |
11463 | size_t i; | |
11464 | ||
11465 | /* Check whether there is only a single bracketed expression | |
11466 | left. If so, it must be the base register and the | |
11467 | constant must be zero. */ | |
11468 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11469 | continue; | |
11470 | ||
11471 | /* If this value won't fit into the offset, then go find | |
11472 | a macro that will generate a 16- or 32-bit offset code | |
11473 | pattern. */ | |
11474 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11475 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11476 | || imm_expr.X_add_number >= 1 << shift | |
11477 | || imm_expr.X_add_number < -1 << shift)) | |
11478 | || i > 0) | |
11479 | { | |
11480 | imm_expr.X_op = O_absent; | |
11481 | break; | |
11482 | } | |
11483 | if (shift == 9) | |
11484 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11485 | else | |
dec0624d MR |
11486 | INSERT_OPERAND (mips_opts.micromips, |
11487 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11488 | imm_expr.X_op = O_absent; |
11489 | s = expr_end; | |
11490 | } | |
11491 | continue; | |
11492 | ||
252b5132 RH |
11493 | case '<': /* must be at least one digit */ |
11494 | /* | |
11495 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11496 | * than 31 or less than 0, then the shift amount should be |
11497 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11498 | * We issue a warning and mask out all but the low 5 bits. |
11499 | */ | |
11500 | my_getExpression (&imm_expr, s); | |
11501 | check_absolute_expr (ip, &imm_expr); | |
11502 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11503 | as_warn (_("Improper shift amount (%lu)"), |
11504 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11505 | INSERT_OPERAND (mips_opts.micromips, |
11506 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11507 | imm_expr.X_op = O_absent; |
11508 | s = expr_end; | |
11509 | continue; | |
11510 | ||
11511 | case '>': /* shift amount minus 32 */ | |
11512 | my_getExpression (&imm_expr, s); | |
11513 | check_absolute_expr (ip, &imm_expr); | |
11514 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11515 | || (unsigned long) imm_expr.X_add_number > 63) | |
11516 | break; | |
df58fc94 RS |
11517 | INSERT_OPERAND (mips_opts.micromips, |
11518 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11519 | imm_expr.X_op = O_absent; |
11520 | s = expr_end; | |
11521 | continue; | |
11522 | ||
90ecf173 MR |
11523 | case 'k': /* CACHE code. */ |
11524 | case 'h': /* PREFX code. */ | |
11525 | case '1': /* SYNC type. */ | |
252b5132 RH |
11526 | my_getExpression (&imm_expr, s); |
11527 | check_absolute_expr (ip, &imm_expr); | |
11528 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11529 | as_warn (_("Invalid value for `%s' (%lu)"), |
11530 | ip->insn_mo->name, | |
11531 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11532 | switch (*args) |
d954098f | 11533 | { |
df58fc94 RS |
11534 | case 'k': |
11535 | if (mips_fix_cn63xxp1 | |
11536 | && !mips_opts.micromips | |
11537 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11538 | switch (imm_expr.X_add_number) |
11539 | { | |
11540 | case 5: | |
11541 | case 25: | |
11542 | case 26: | |
11543 | case 27: | |
11544 | case 28: | |
11545 | case 29: | |
11546 | case 30: | |
11547 | case 31: /* These are ok. */ | |
11548 | break; | |
11549 | ||
11550 | default: /* The rest must be changed to 28. */ | |
11551 | imm_expr.X_add_number = 28; | |
11552 | break; | |
11553 | } | |
df58fc94 RS |
11554 | INSERT_OPERAND (mips_opts.micromips, |
11555 | CACHE, *ip, imm_expr.X_add_number); | |
11556 | break; | |
11557 | case 'h': | |
11558 | INSERT_OPERAND (mips_opts.micromips, | |
11559 | PREFX, *ip, imm_expr.X_add_number); | |
11560 | break; | |
11561 | case '1': | |
11562 | INSERT_OPERAND (mips_opts.micromips, | |
11563 | STYPE, *ip, imm_expr.X_add_number); | |
11564 | break; | |
d954098f | 11565 | } |
252b5132 RH |
11566 | imm_expr.X_op = O_absent; |
11567 | s = expr_end; | |
11568 | continue; | |
11569 | ||
90ecf173 | 11570 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11571 | { |
11572 | unsigned long mask = (mips_opts.micromips | |
11573 | ? MICROMIPSOP_MASK_CODE | |
11574 | : OP_MASK_CODE); | |
11575 | ||
11576 | my_getExpression (&imm_expr, s); | |
11577 | check_absolute_expr (ip, &imm_expr); | |
11578 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11579 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11580 | ip->insn_mo->name, | |
11581 | mask, (unsigned long) imm_expr.X_add_number); | |
11582 | INSERT_OPERAND (mips_opts.micromips, | |
11583 | CODE, *ip, imm_expr.X_add_number); | |
11584 | imm_expr.X_op = O_absent; | |
11585 | s = expr_end; | |
11586 | } | |
252b5132 RH |
11587 | continue; |
11588 | ||
90ecf173 | 11589 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11590 | { |
11591 | unsigned long mask = (mips_opts.micromips | |
11592 | ? MICROMIPSOP_MASK_CODE2 | |
11593 | : OP_MASK_CODE2); | |
11594 | ||
11595 | my_getExpression (&imm_expr, s); | |
11596 | check_absolute_expr (ip, &imm_expr); | |
11597 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11598 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11599 | ip->insn_mo->name, | |
11600 | mask, (unsigned long) imm_expr.X_add_number); | |
11601 | INSERT_OPERAND (mips_opts.micromips, | |
11602 | CODE2, *ip, imm_expr.X_add_number); | |
11603 | imm_expr.X_op = O_absent; | |
11604 | s = expr_end; | |
11605 | } | |
252b5132 RH |
11606 | continue; |
11607 | ||
df58fc94 RS |
11608 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11609 | { | |
11610 | unsigned long mask = (mips_opts.micromips | |
11611 | ? MICROMIPSOP_MASK_CODE10 | |
11612 | : OP_MASK_CODE20); | |
11613 | ||
11614 | my_getExpression (&imm_expr, s); | |
11615 | check_absolute_expr (ip, &imm_expr); | |
11616 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11617 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11618 | ip->insn_mo->name, | |
11619 | mask, (unsigned long) imm_expr.X_add_number); | |
11620 | if (mips_opts.micromips) | |
11621 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11622 | else | |
11623 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11624 | imm_expr.X_op = O_absent; | |
11625 | s = expr_end; | |
11626 | } | |
252b5132 RH |
11627 | continue; |
11628 | ||
df58fc94 RS |
11629 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11630 | { | |
11631 | unsigned long mask = (mips_opts.micromips | |
11632 | ? MICROMIPSOP_MASK_COPZ | |
11633 | : OP_MASK_COPZ); | |
11634 | ||
11635 | my_getExpression (&imm_expr, s); | |
11636 | check_absolute_expr (ip, &imm_expr); | |
11637 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11638 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11639 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11640 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11641 | INSERT_OPERAND (mips_opts.micromips, |
11642 | COPZ, *ip, imm_expr.X_add_number); | |
11643 | imm_expr.X_op = O_absent; | |
11644 | s = expr_end; | |
11645 | } | |
beae10d5 | 11646 | continue; |
252b5132 | 11647 | |
df58fc94 RS |
11648 | case 'J': /* 19-bit WAIT code. */ |
11649 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11650 | my_getExpression (&imm_expr, s); |
11651 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11652 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11653 | { |
11654 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11655 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11656 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11657 | } | |
11658 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11659 | imm_expr.X_op = O_absent; |
11660 | s = expr_end; | |
11661 | continue; | |
11662 | ||
707bfff6 | 11663 | case 'P': /* Performance register. */ |
df58fc94 | 11664 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11665 | my_getExpression (&imm_expr, s); |
252b5132 | 11666 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11667 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11668 | as_warn (_("Invalid performance register (%lu)"), |
11669 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11670 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11671 | imm_expr.X_op = O_absent; |
11672 | s = expr_end; | |
11673 | continue; | |
252b5132 | 11674 | |
707bfff6 | 11675 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11676 | { |
11677 | unsigned long opcode = ip->insn_opcode; | |
11678 | unsigned long mask; | |
11679 | unsigned int types; | |
11680 | int cop0; | |
11681 | ||
11682 | if (mips_opts.micromips) | |
11683 | { | |
11684 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11685 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11686 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11687 | opcode &= mask; | |
11688 | switch (opcode) | |
11689 | { | |
11690 | case 0x000000fc: /* mfc0 */ | |
11691 | case 0x000002fc: /* mtc0 */ | |
11692 | case 0x580000fc: /* dmfc0 */ | |
11693 | case 0x580002fc: /* dmtc0 */ | |
11694 | cop0 = 1; | |
11695 | break; | |
11696 | default: | |
11697 | cop0 = 0; | |
11698 | break; | |
11699 | } | |
11700 | } | |
11701 | else | |
11702 | { | |
11703 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11704 | cop0 = opcode == OP_OP_COP0; | |
11705 | } | |
11706 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11707 | ok = reg_lookup (&s, types, ®no); | |
11708 | if (mips_opts.micromips) | |
11709 | INSERT_OPERAND (1, RS, *ip, regno); | |
11710 | else | |
11711 | INSERT_OPERAND (0, RD, *ip, regno); | |
11712 | if (ok) | |
11713 | { | |
11714 | lastregno = regno; | |
11715 | continue; | |
11716 | } | |
11717 | } | |
11718 | break; | |
707bfff6 | 11719 | |
df58fc94 RS |
11720 | case 'y': /* ALNV.PS source register. */ |
11721 | gas_assert (mips_opts.micromips); | |
11722 | goto do_reg; | |
11723 | case 'x': /* Ignore register name. */ | |
11724 | case 'U': /* Destination register (CLO/CLZ). */ | |
11725 | case 'g': /* Coprocessor destination register. */ | |
11726 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11727 | case 'b': /* Base register. */ |
11728 | case 'd': /* Destination register. */ | |
11729 | case 's': /* Source register. */ | |
11730 | case 't': /* Target register. */ | |
11731 | case 'r': /* Both target and source. */ | |
11732 | case 'v': /* Both dest and source. */ | |
11733 | case 'w': /* Both dest and target. */ | |
11734 | case 'E': /* Coprocessor target register. */ | |
11735 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11736 | case 'z': /* Must be zero register. */ |
df58fc94 | 11737 | do_reg: |
90ecf173 | 11738 | s_reset = s; |
707bfff6 TS |
11739 | if (*args == 'E' || *args == 'K') |
11740 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11741 | else | |
11742 | { | |
11743 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11744 | if (regno == AT && mips_opts.at) |
11745 | { | |
11746 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11747 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11748 | else |
f71d0d44 | 11749 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11750 | regno, mips_opts.at); |
11751 | } | |
707bfff6 TS |
11752 | } |
11753 | if (ok) | |
252b5132 | 11754 | { |
252b5132 RH |
11755 | c = *args; |
11756 | if (*s == ' ') | |
f9419b05 | 11757 | ++s; |
252b5132 RH |
11758 | if (args[1] != *s) |
11759 | { | |
11760 | if (c == 'r' || c == 'v' || c == 'w') | |
11761 | { | |
11762 | regno = lastregno; | |
11763 | s = s_reset; | |
f9419b05 | 11764 | ++args; |
252b5132 RH |
11765 | } |
11766 | } | |
11767 | /* 'z' only matches $0. */ | |
11768 | if (c == 'z' && regno != 0) | |
11769 | break; | |
11770 | ||
24864476 | 11771 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
11772 | { |
11773 | if (regno == lastregno) | |
90ecf173 MR |
11774 | { |
11775 | insn_error | |
f71d0d44 | 11776 | = _("Source and destination must be different"); |
e7c604dd | 11777 | continue; |
90ecf173 | 11778 | } |
24864476 | 11779 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
11780 | { |
11781 | insn_error | |
f71d0d44 | 11782 | = _("A destination register must be supplied"); |
e7c604dd | 11783 | continue; |
90ecf173 | 11784 | } |
e7c604dd | 11785 | } |
90ecf173 MR |
11786 | /* Now that we have assembled one operand, we use the args |
11787 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
11788 | switch (c) |
11789 | { | |
11790 | case 'r': | |
11791 | case 's': | |
11792 | case 'v': | |
11793 | case 'b': | |
df58fc94 | 11794 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 11795 | break; |
df58fc94 | 11796 | |
af7ee8bf | 11797 | case 'K': |
df58fc94 RS |
11798 | if (mips_opts.micromips) |
11799 | INSERT_OPERAND (1, RS, *ip, regno); | |
11800 | else | |
11801 | INSERT_OPERAND (0, RD, *ip, regno); | |
11802 | break; | |
11803 | ||
11804 | case 'd': | |
ef2e4d86 | 11805 | case 'g': |
df58fc94 | 11806 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 11807 | break; |
df58fc94 | 11808 | |
4372b673 | 11809 | case 'U': |
df58fc94 RS |
11810 | gas_assert (!mips_opts.micromips); |
11811 | INSERT_OPERAND (0, RD, *ip, regno); | |
11812 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 11813 | break; |
df58fc94 | 11814 | |
252b5132 RH |
11815 | case 'w': |
11816 | case 't': | |
11817 | case 'E': | |
df58fc94 RS |
11818 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
11819 | break; | |
11820 | ||
11821 | case 'y': | |
11822 | gas_assert (mips_opts.micromips); | |
11823 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 11824 | break; |
df58fc94 | 11825 | |
252b5132 RH |
11826 | case 'x': |
11827 | /* This case exists because on the r3000 trunc | |
11828 | expands into a macro which requires a gp | |
11829 | register. On the r6000 or r4000 it is | |
11830 | assembled into a single instruction which | |
11831 | ignores the register. Thus the insn version | |
11832 | is MIPS_ISA2 and uses 'x', and the macro | |
11833 | version is MIPS_ISA1 and uses 't'. */ | |
11834 | break; | |
df58fc94 | 11835 | |
252b5132 RH |
11836 | case 'z': |
11837 | /* This case is for the div instruction, which | |
11838 | acts differently if the destination argument | |
11839 | is $0. This only matches $0, and is checked | |
11840 | outside the switch. */ | |
11841 | break; | |
252b5132 RH |
11842 | } |
11843 | lastregno = regno; | |
11844 | continue; | |
11845 | } | |
252b5132 RH |
11846 | switch (*args++) |
11847 | { | |
11848 | case 'r': | |
11849 | case 'v': | |
df58fc94 | 11850 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 11851 | continue; |
df58fc94 | 11852 | |
252b5132 | 11853 | case 'w': |
df58fc94 | 11854 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
11855 | continue; |
11856 | } | |
11857 | break; | |
11858 | ||
deec1734 | 11859 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 11860 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11861 | my_getExpression (&imm_expr, s); |
11862 | check_absolute_expr (ip, &imm_expr); | |
11863 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 11864 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 11865 | (long) imm_expr.X_add_number); |
df58fc94 | 11866 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
11867 | imm_expr.X_op = O_absent; |
11868 | s = expr_end; | |
11869 | continue; | |
11870 | ||
11871 | case 'Q': /* MDMX vector, element sel, or const. */ | |
11872 | if (s[0] != '$') | |
11873 | { | |
11874 | /* MDMX Immediate. */ | |
df58fc94 | 11875 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11876 | my_getExpression (&imm_expr, s); |
11877 | check_absolute_expr (ip, &imm_expr); | |
11878 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
11879 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
11880 | (long) imm_expr.X_add_number); | |
df58fc94 | 11881 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
11882 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
11883 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
11884 | else | |
11885 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
11886 | imm_expr.X_op = O_absent; |
11887 | s = expr_end; | |
11888 | continue; | |
11889 | } | |
11890 | /* Not MDMX Immediate. Fall through. */ | |
11891 | case 'X': /* MDMX destination register. */ | |
11892 | case 'Y': /* MDMX source register. */ | |
11893 | case 'Z': /* MDMX target register. */ | |
11894 | is_mdmx = 1; | |
df58fc94 RS |
11895 | case 'W': |
11896 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11897 | case 'D': /* Floating point destination register. */ |
11898 | case 'S': /* Floating point source register. */ | |
11899 | case 'T': /* Floating point target register. */ | |
11900 | case 'R': /* Floating point source register. */ | |
252b5132 | 11901 | case 'V': |
707bfff6 TS |
11902 | rtype = RTYPE_FPU; |
11903 | if (is_mdmx | |
11904 | || (mips_opts.ase_mdmx | |
11905 | && (ip->insn_mo->pinfo & FP_D) | |
11906 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
11907 | | INSN_COPROC_MEMORY_DELAY | |
11908 | | INSN_LOAD_COPROC_DELAY | |
11909 | | INSN_LOAD_MEMORY_DELAY | |
11910 | | INSN_STORE_MEMORY)))) | |
11911 | rtype |= RTYPE_VEC; | |
252b5132 | 11912 | s_reset = s; |
707bfff6 | 11913 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 11914 | { |
252b5132 | 11915 | if ((regno & 1) != 0 |
ca4e0257 | 11916 | && HAVE_32BIT_FPRS |
90ecf173 | 11917 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
11918 | as_warn (_("Float register should be even, was %d"), |
11919 | regno); | |
11920 | ||
11921 | c = *args; | |
11922 | if (*s == ' ') | |
f9419b05 | 11923 | ++s; |
252b5132 RH |
11924 | if (args[1] != *s) |
11925 | { | |
11926 | if (c == 'V' || c == 'W') | |
11927 | { | |
11928 | regno = lastregno; | |
11929 | s = s_reset; | |
f9419b05 | 11930 | ++args; |
252b5132 RH |
11931 | } |
11932 | } | |
11933 | switch (c) | |
11934 | { | |
11935 | case 'D': | |
deec1734 | 11936 | case 'X': |
df58fc94 | 11937 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 11938 | break; |
df58fc94 | 11939 | |
252b5132 RH |
11940 | case 'V': |
11941 | case 'S': | |
deec1734 | 11942 | case 'Y': |
df58fc94 | 11943 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 11944 | break; |
df58fc94 | 11945 | |
deec1734 CD |
11946 | case 'Q': |
11947 | /* This is like 'Z', but also needs to fix the MDMX | |
11948 | vector/scalar select bits. Note that the | |
11949 | scalar immediate case is handled above. */ | |
11950 | if (*s == '[') | |
11951 | { | |
11952 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
11953 | int max_el = (is_qh ? 3 : 7); | |
11954 | s++; | |
11955 | my_getExpression(&imm_expr, s); | |
11956 | check_absolute_expr (ip, &imm_expr); | |
11957 | s = expr_end; | |
11958 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
11959 | as_bad (_("Bad element selector %ld"), |
11960 | (long) imm_expr.X_add_number); | |
deec1734 CD |
11961 | imm_expr.X_add_number &= max_el; |
11962 | ip->insn_opcode |= (imm_expr.X_add_number | |
11963 | << (OP_SH_VSEL + | |
11964 | (is_qh ? 2 : 1))); | |
01a3f561 | 11965 | imm_expr.X_op = O_absent; |
deec1734 | 11966 | if (*s != ']') |
20203fb9 | 11967 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
11968 | else |
11969 | s++; | |
11970 | } | |
11971 | else | |
11972 | { | |
11973 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
11974 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
11975 | << OP_SH_VSEL); | |
11976 | else | |
11977 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
11978 | OP_SH_VSEL); | |
11979 | } | |
90ecf173 | 11980 | /* Fall through. */ |
252b5132 RH |
11981 | case 'W': |
11982 | case 'T': | |
deec1734 | 11983 | case 'Z': |
df58fc94 | 11984 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 11985 | break; |
df58fc94 | 11986 | |
252b5132 | 11987 | case 'R': |
df58fc94 | 11988 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
11989 | break; |
11990 | } | |
11991 | lastregno = regno; | |
11992 | continue; | |
11993 | } | |
11994 | ||
252b5132 RH |
11995 | switch (*args++) |
11996 | { | |
11997 | case 'V': | |
df58fc94 | 11998 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 11999 | continue; |
df58fc94 | 12000 | |
252b5132 | 12001 | case 'W': |
df58fc94 | 12002 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12003 | continue; |
12004 | } | |
12005 | break; | |
12006 | ||
12007 | case 'I': | |
12008 | my_getExpression (&imm_expr, s); | |
12009 | if (imm_expr.X_op != O_big | |
12010 | && imm_expr.X_op != O_constant) | |
12011 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12012 | if (HAVE_32BIT_GPRS) |
12013 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12014 | s = expr_end; |
12015 | continue; | |
12016 | ||
12017 | case 'A': | |
12018 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 12019 | normalize_address_expr (&offset_expr); |
f6688943 | 12020 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
12021 | s = expr_end; |
12022 | continue; | |
12023 | ||
12024 | case 'F': | |
12025 | case 'L': | |
12026 | case 'f': | |
12027 | case 'l': | |
12028 | { | |
12029 | int f64; | |
ca4e0257 | 12030 | int using_gprs; |
252b5132 RH |
12031 | char *save_in; |
12032 | char *err; | |
12033 | unsigned char temp[8]; | |
12034 | int len; | |
12035 | unsigned int length; | |
12036 | segT seg; | |
12037 | subsegT subseg; | |
12038 | char *p; | |
12039 | ||
12040 | /* These only appear as the last operand in an | |
12041 | instruction, and every instruction that accepts | |
12042 | them in any variant accepts them in all variants. | |
12043 | This means we don't have to worry about backing out | |
12044 | any changes if the instruction does not match. | |
12045 | ||
12046 | The difference between them is the size of the | |
12047 | floating point constant and where it goes. For 'F' | |
12048 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12049 | is 32 bits. Where the constant is placed is based | |
12050 | on how the MIPS assembler does things: | |
12051 | F -- .rdata | |
12052 | L -- .lit8 | |
12053 | f -- immediate value | |
12054 | l -- .lit4 | |
12055 | ||
12056 | The .lit4 and .lit8 sections are only used if | |
12057 | permitted by the -G argument. | |
12058 | ||
ca4e0257 RS |
12059 | The code below needs to know whether the target register |
12060 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12061 | 'F' are used with GPR-based instructions and 'l' and | |
12062 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12063 | |
12064 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12065 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12066 | |
12067 | save_in = input_line_pointer; | |
12068 | input_line_pointer = s; | |
12069 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12070 | length = len; | |
12071 | s = input_line_pointer; | |
12072 | input_line_pointer = save_in; | |
12073 | if (err != NULL && *err != '\0') | |
12074 | { | |
12075 | as_bad (_("Bad floating point constant: %s"), err); | |
12076 | memset (temp, '\0', sizeof temp); | |
12077 | length = f64 ? 8 : 4; | |
12078 | } | |
12079 | ||
9c2799c2 | 12080 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12081 | |
12082 | if (*args == 'f' | |
12083 | || (*args == 'l' | |
3e722fb5 | 12084 | && (g_switch_value < 4 |
252b5132 RH |
12085 | || (temp[0] == 0 && temp[1] == 0) |
12086 | || (temp[2] == 0 && temp[3] == 0)))) | |
12087 | { | |
12088 | imm_expr.X_op = O_constant; | |
90ecf173 | 12089 | if (!target_big_endian) |
252b5132 RH |
12090 | imm_expr.X_add_number = bfd_getl32 (temp); |
12091 | else | |
12092 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12093 | } | |
12094 | else if (length > 4 | |
90ecf173 | 12095 | && !mips_disable_float_construction |
ca4e0257 RS |
12096 | /* Constants can only be constructed in GPRs and |
12097 | copied to FPRs if the GPRs are at least as wide | |
12098 | as the FPRs. Force the constant into memory if | |
12099 | we are using 64-bit FPRs but the GPRs are only | |
12100 | 32 bits wide. */ | |
12101 | && (using_gprs | |
90ecf173 | 12102 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12103 | && ((temp[0] == 0 && temp[1] == 0) |
12104 | || (temp[2] == 0 && temp[3] == 0)) | |
12105 | && ((temp[4] == 0 && temp[5] == 0) | |
12106 | || (temp[6] == 0 && temp[7] == 0))) | |
12107 | { | |
ca4e0257 | 12108 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12109 | instructions. If using 32-bit registers, set |
12110 | imm_expr to the high order 32 bits and offset_expr to | |
12111 | the low order 32 bits. Otherwise, set imm_expr to | |
12112 | the entire 64 bit constant. */ | |
ca4e0257 | 12113 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12114 | { |
12115 | imm_expr.X_op = O_constant; | |
12116 | offset_expr.X_op = O_constant; | |
90ecf173 | 12117 | if (!target_big_endian) |
252b5132 RH |
12118 | { |
12119 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12120 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12121 | } | |
12122 | else | |
12123 | { | |
12124 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12125 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12126 | } | |
12127 | if (offset_expr.X_add_number == 0) | |
12128 | offset_expr.X_op = O_absent; | |
12129 | } | |
12130 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12131 | { | |
12132 | imm_expr.X_op = O_constant; | |
90ecf173 | 12133 | if (!target_big_endian) |
252b5132 RH |
12134 | imm_expr.X_add_number = bfd_getl64 (temp); |
12135 | else | |
12136 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12137 | } | |
12138 | else | |
12139 | { | |
12140 | imm_expr.X_op = O_big; | |
12141 | imm_expr.X_add_number = 4; | |
90ecf173 | 12142 | if (!target_big_endian) |
252b5132 RH |
12143 | { |
12144 | generic_bignum[0] = bfd_getl16 (temp); | |
12145 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12146 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12147 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12148 | } | |
12149 | else | |
12150 | { | |
12151 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12152 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12153 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12154 | generic_bignum[3] = bfd_getb16 (temp); | |
12155 | } | |
12156 | } | |
12157 | } | |
12158 | else | |
12159 | { | |
12160 | const char *newname; | |
12161 | segT new_seg; | |
12162 | ||
12163 | /* Switch to the right section. */ | |
12164 | seg = now_seg; | |
12165 | subseg = now_subseg; | |
12166 | switch (*args) | |
12167 | { | |
12168 | default: /* unused default case avoids warnings. */ | |
12169 | case 'L': | |
12170 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12171 | if (g_switch_value >= 8) |
252b5132 RH |
12172 | newname = ".lit8"; |
12173 | break; | |
12174 | case 'F': | |
3e722fb5 | 12175 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12176 | break; |
12177 | case 'l': | |
9c2799c2 | 12178 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12179 | newname = ".lit4"; |
12180 | break; | |
12181 | } | |
12182 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12183 | if (IS_ELF) |
252b5132 RH |
12184 | bfd_set_section_flags (stdoutput, new_seg, |
12185 | (SEC_ALLOC | |
12186 | | SEC_LOAD | |
12187 | | SEC_READONLY | |
12188 | | SEC_DATA)); | |
12189 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12190 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12191 | record_alignment (new_seg, 4); |
12192 | else | |
12193 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12194 | if (seg == now_seg) | |
12195 | as_bad (_("Can't use floating point insn in this section")); | |
12196 | ||
df58fc94 RS |
12197 | /* Set the argument to the current address in the |
12198 | section. */ | |
12199 | offset_expr.X_op = O_symbol; | |
12200 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12201 | offset_expr.X_add_number = 0; | |
12202 | ||
12203 | /* Put the floating point number into the section. */ | |
12204 | p = frag_more ((int) length); | |
12205 | memcpy (p, temp, length); | |
12206 | ||
12207 | /* Switch back to the original section. */ | |
12208 | subseg_set (seg, subseg); | |
12209 | } | |
12210 | } | |
12211 | continue; | |
12212 | ||
12213 | case 'i': /* 16-bit unsigned immediate. */ | |
12214 | case 'j': /* 16-bit signed immediate. */ | |
12215 | *imm_reloc = BFD_RELOC_LO16; | |
12216 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12217 | { | |
12218 | int more; | |
12219 | offsetT minval, maxval; | |
12220 | ||
12221 | more = (insn + 1 < past | |
12222 | && strcmp (insn->name, insn[1].name) == 0); | |
12223 | ||
12224 | /* If the expression was written as an unsigned number, | |
12225 | only treat it as signed if there are no more | |
12226 | alternatives. */ | |
12227 | if (more | |
12228 | && *args == 'j' | |
12229 | && sizeof (imm_expr.X_add_number) <= 4 | |
12230 | && imm_expr.X_op == O_constant | |
12231 | && imm_expr.X_add_number < 0 | |
12232 | && imm_expr.X_unsigned | |
12233 | && HAVE_64BIT_GPRS) | |
12234 | break; | |
12235 | ||
12236 | /* For compatibility with older assemblers, we accept | |
12237 | 0x8000-0xffff as signed 16-bit numbers when only | |
12238 | signed numbers are allowed. */ | |
12239 | if (*args == 'i') | |
12240 | minval = 0, maxval = 0xffff; | |
12241 | else if (more) | |
12242 | minval = -0x8000, maxval = 0x7fff; | |
12243 | else | |
12244 | minval = -0x8000, maxval = 0xffff; | |
12245 | ||
12246 | if (imm_expr.X_op != O_constant | |
12247 | || imm_expr.X_add_number < minval | |
12248 | || imm_expr.X_add_number > maxval) | |
12249 | { | |
12250 | if (more) | |
12251 | break; | |
12252 | if (imm_expr.X_op == O_constant | |
12253 | || imm_expr.X_op == O_big) | |
12254 | as_bad (_("Expression out of range")); | |
12255 | } | |
12256 | } | |
12257 | s = expr_end; | |
12258 | continue; | |
12259 | ||
12260 | case 'o': /* 16-bit offset. */ | |
12261 | offset_reloc[0] = BFD_RELOC_LO16; | |
12262 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12263 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12264 | ||
12265 | /* Check whether there is only a single bracketed expression | |
12266 | left. If so, it must be the base register and the | |
12267 | constant must be zero. */ | |
12268 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12269 | { | |
12270 | offset_expr.X_op = O_constant; | |
12271 | offset_expr.X_add_number = 0; | |
12272 | continue; | |
12273 | } | |
12274 | ||
12275 | /* If this value won't fit into a 16 bit offset, then go | |
12276 | find a macro that will generate the 32 bit offset | |
12277 | code pattern. */ | |
12278 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12279 | && (offset_expr.X_op != O_constant | |
12280 | || offset_expr.X_add_number >= 0x8000 | |
12281 | || offset_expr.X_add_number < -0x8000)) | |
12282 | break; | |
12283 | ||
12284 | s = expr_end; | |
12285 | continue; | |
12286 | ||
12287 | case 'p': /* PC-relative offset. */ | |
12288 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12289 | my_getExpression (&offset_expr, s); | |
12290 | s = expr_end; | |
12291 | continue; | |
12292 | ||
12293 | case 'u': /* Upper 16 bits. */ | |
12294 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 | |
12295 | && imm_expr.X_op == O_constant | |
12296 | && (imm_expr.X_add_number < 0 | |
12297 | || imm_expr.X_add_number >= 0x10000)) | |
12298 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12299 | (unsigned long) imm_expr.X_add_number); | |
12300 | s = expr_end; | |
12301 | continue; | |
12302 | ||
12303 | case 'a': /* 26-bit address. */ | |
12304 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12305 | my_getExpression (&offset_expr, s); | |
12306 | s = expr_end; | |
12307 | continue; | |
12308 | ||
12309 | case 'N': /* 3-bit branch condition code. */ | |
12310 | case 'M': /* 3-bit compare condition code. */ | |
12311 | rtype = RTYPE_CCC; | |
12312 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12313 | rtype |= RTYPE_FCC; | |
12314 | if (!reg_lookup (&s, rtype, ®no)) | |
12315 | break; | |
12316 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12317 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12318 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12319 | && (regno & 1) != 0) | |
12320 | as_warn (_("Condition code register should be even for %s, " | |
12321 | "was %d"), | |
12322 | str, regno); | |
12323 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12324 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12325 | && (regno & 3) != 0) | |
12326 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12327 | "was %d"), | |
12328 | str, regno); | |
12329 | if (*args == 'N') | |
12330 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12331 | else | |
12332 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12333 | continue; | |
12334 | ||
12335 | case 'H': | |
12336 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12337 | s += 2; | |
12338 | if (ISDIGIT (*s)) | |
12339 | { | |
12340 | c = 0; | |
12341 | do | |
12342 | { | |
12343 | c *= 10; | |
12344 | c += *s - '0'; | |
12345 | ++s; | |
12346 | } | |
12347 | while (ISDIGIT (*s)); | |
12348 | } | |
12349 | else | |
12350 | c = 8; /* Invalid sel value. */ | |
12351 | ||
12352 | if (c > 7) | |
12353 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12354 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12355 | continue; | |
12356 | ||
12357 | case 'e': | |
12358 | gas_assert (!mips_opts.micromips); | |
12359 | /* Must be at least one digit. */ | |
12360 | my_getExpression (&imm_expr, s); | |
12361 | check_absolute_expr (ip, &imm_expr); | |
12362 | ||
12363 | if ((unsigned long) imm_expr.X_add_number | |
12364 | > (unsigned long) OP_MASK_VECBYTE) | |
12365 | { | |
12366 | as_bad (_("bad byte vector index (%ld)"), | |
12367 | (long) imm_expr.X_add_number); | |
12368 | imm_expr.X_add_number = 0; | |
12369 | } | |
12370 | ||
12371 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12372 | imm_expr.X_op = O_absent; | |
12373 | s = expr_end; | |
12374 | continue; | |
12375 | ||
12376 | case '%': | |
12377 | gas_assert (!mips_opts.micromips); | |
12378 | my_getExpression (&imm_expr, s); | |
12379 | check_absolute_expr (ip, &imm_expr); | |
12380 | ||
12381 | if ((unsigned long) imm_expr.X_add_number | |
12382 | > (unsigned long) OP_MASK_VECALIGN) | |
12383 | { | |
12384 | as_bad (_("bad byte vector index (%ld)"), | |
12385 | (long) imm_expr.X_add_number); | |
12386 | imm_expr.X_add_number = 0; | |
12387 | } | |
12388 | ||
12389 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12390 | imm_expr.X_op = O_absent; | |
12391 | s = expr_end; | |
12392 | continue; | |
12393 | ||
12394 | case 'm': /* Opcode extension character. */ | |
12395 | gas_assert (mips_opts.micromips); | |
12396 | c = *++args; | |
12397 | switch (c) | |
12398 | { | |
12399 | case 'r': | |
12400 | if (strncmp (s, "$pc", 3) == 0) | |
12401 | { | |
12402 | s += 3; | |
12403 | continue; | |
12404 | } | |
12405 | break; | |
12406 | ||
12407 | case 'a': | |
12408 | case 'b': | |
12409 | case 'c': | |
12410 | case 'd': | |
12411 | case 'e': | |
12412 | case 'f': | |
12413 | case 'g': | |
12414 | case 'h': | |
12415 | case 'i': | |
12416 | case 'j': | |
12417 | case 'l': | |
12418 | case 'm': | |
12419 | case 'n': | |
12420 | case 'p': | |
12421 | case 'q': | |
12422 | case 's': | |
12423 | case 't': | |
12424 | case 'x': | |
12425 | case 'y': | |
12426 | case 'z': | |
12427 | s_reset = s; | |
12428 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12429 | if (regno == AT && mips_opts.at) | |
12430 | { | |
12431 | if (mips_opts.at == ATREG) | |
12432 | as_warn (_("Used $at without \".set noat\"")); | |
12433 | else | |
12434 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12435 | regno, mips_opts.at); | |
12436 | } | |
12437 | if (!ok) | |
12438 | { | |
12439 | if (c == 'c') | |
12440 | { | |
12441 | gas_assert (args[1] == ','); | |
12442 | regno = lastregno; | |
12443 | ++args; | |
12444 | } | |
12445 | else if (c == 't') | |
12446 | { | |
12447 | gas_assert (args[1] == ','); | |
12448 | ++args; | |
12449 | continue; /* Nothing to do. */ | |
12450 | } | |
12451 | else | |
12452 | break; | |
12453 | } | |
12454 | ||
12455 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12456 | { | |
12457 | if (regno == lastregno) | |
12458 | { | |
12459 | insn_error | |
12460 | = _("Source and destination must be different"); | |
12461 | continue; | |
12462 | } | |
12463 | if (regno == 31 && lastregno == 0xffffffff) | |
12464 | { | |
12465 | insn_error | |
12466 | = _("A destination register must be supplied"); | |
12467 | continue; | |
12468 | } | |
12469 | } | |
12470 | ||
12471 | if (*s == ' ') | |
12472 | ++s; | |
12473 | if (args[1] != *s) | |
12474 | { | |
12475 | if (c == 'e') | |
12476 | { | |
12477 | gas_assert (args[1] == ','); | |
12478 | regno = lastregno; | |
12479 | s = s_reset; | |
12480 | ++args; | |
12481 | } | |
12482 | else if (c == 't') | |
12483 | { | |
12484 | gas_assert (args[1] == ','); | |
12485 | s = s_reset; | |
12486 | ++args; | |
12487 | continue; /* Nothing to do. */ | |
12488 | } | |
12489 | } | |
12490 | ||
12491 | /* Make sure regno is the same as lastregno. */ | |
12492 | if (c == 't' && regno != lastregno) | |
12493 | break; | |
12494 | ||
12495 | /* Make sure regno is the same as destregno. */ | |
12496 | if (c == 'x' && regno != destregno) | |
12497 | break; | |
12498 | ||
12499 | /* We need to save regno, before regno maps to the | |
12500 | microMIPS register encoding. */ | |
12501 | lastregno = regno; | |
12502 | ||
12503 | if (c == 'f') | |
12504 | destregno = regno; | |
12505 | ||
12506 | switch (c) | |
12507 | { | |
12508 | case 'a': | |
12509 | if (regno != GP) | |
12510 | regno = ILLEGAL_REG; | |
12511 | break; | |
12512 | ||
12513 | case 'b': | |
12514 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12515 | break; | |
12516 | ||
12517 | case 'c': | |
12518 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12519 | break; | |
12520 | ||
12521 | case 'd': | |
12522 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12523 | break; | |
12524 | ||
12525 | case 'e': | |
12526 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12527 | break; | |
12528 | ||
12529 | case 'f': | |
12530 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12531 | break; | |
12532 | ||
12533 | case 'g': | |
12534 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12535 | break; | |
12536 | ||
12537 | case 'h': | |
12538 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12539 | break; | |
12540 | ||
12541 | case 'i': | |
12542 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12543 | { | |
12544 | case 4: | |
12545 | if (regno == 21) | |
12546 | regno = 3; | |
12547 | else if (regno == 22) | |
12548 | regno = 4; | |
12549 | else if (regno == 5) | |
12550 | regno = 5; | |
12551 | else if (regno == 6) | |
12552 | regno = 6; | |
12553 | else if (regno == 7) | |
12554 | regno = 7; | |
12555 | else | |
12556 | regno = ILLEGAL_REG; | |
12557 | break; | |
12558 | ||
12559 | case 5: | |
12560 | if (regno == 6) | |
12561 | regno = 0; | |
12562 | else if (regno == 7) | |
12563 | regno = 1; | |
12564 | else | |
12565 | regno = ILLEGAL_REG; | |
12566 | break; | |
12567 | ||
12568 | case 6: | |
12569 | if (regno == 7) | |
12570 | regno = 2; | |
12571 | else | |
12572 | regno = ILLEGAL_REG; | |
12573 | break; | |
12574 | ||
12575 | default: | |
12576 | regno = ILLEGAL_REG; | |
12577 | break; | |
12578 | } | |
12579 | break; | |
12580 | ||
12581 | case 'l': | |
12582 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12583 | break; | |
12584 | ||
12585 | case 'm': | |
12586 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12587 | break; | |
12588 | ||
12589 | case 'n': | |
12590 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12591 | break; | |
12592 | ||
12593 | case 'q': | |
12594 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12595 | break; | |
12596 | ||
12597 | case 's': | |
12598 | if (regno != SP) | |
12599 | regno = ILLEGAL_REG; | |
12600 | break; | |
12601 | ||
12602 | case 'y': | |
12603 | if (regno != 31) | |
12604 | regno = ILLEGAL_REG; | |
12605 | break; | |
12606 | ||
12607 | case 'z': | |
12608 | if (regno != ZERO) | |
12609 | regno = ILLEGAL_REG; | |
12610 | break; | |
12611 | ||
12612 | case 'j': /* Do nothing. */ | |
12613 | case 'p': | |
12614 | case 't': | |
12615 | case 'x': | |
12616 | break; | |
12617 | ||
12618 | default: | |
12619 | internalError (); | |
12620 | } | |
12621 | ||
12622 | if (regno == ILLEGAL_REG) | |
12623 | break; | |
12624 | ||
12625 | switch (c) | |
12626 | { | |
12627 | case 'b': | |
12628 | INSERT_OPERAND (1, MB, *ip, regno); | |
12629 | break; | |
12630 | ||
12631 | case 'c': | |
12632 | INSERT_OPERAND (1, MC, *ip, regno); | |
12633 | break; | |
12634 | ||
12635 | case 'd': | |
12636 | INSERT_OPERAND (1, MD, *ip, regno); | |
12637 | break; | |
12638 | ||
12639 | case 'e': | |
12640 | INSERT_OPERAND (1, ME, *ip, regno); | |
12641 | break; | |
12642 | ||
12643 | case 'f': | |
12644 | INSERT_OPERAND (1, MF, *ip, regno); | |
12645 | break; | |
12646 | ||
12647 | case 'g': | |
12648 | INSERT_OPERAND (1, MG, *ip, regno); | |
12649 | break; | |
12650 | ||
12651 | case 'h': | |
12652 | INSERT_OPERAND (1, MH, *ip, regno); | |
12653 | break; | |
12654 | ||
12655 | case 'i': | |
12656 | INSERT_OPERAND (1, MI, *ip, regno); | |
12657 | break; | |
12658 | ||
12659 | case 'j': | |
12660 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12661 | break; | |
12662 | ||
12663 | case 'l': | |
12664 | INSERT_OPERAND (1, ML, *ip, regno); | |
12665 | break; | |
12666 | ||
12667 | case 'm': | |
12668 | INSERT_OPERAND (1, MM, *ip, regno); | |
12669 | break; | |
12670 | ||
12671 | case 'n': | |
12672 | INSERT_OPERAND (1, MN, *ip, regno); | |
12673 | break; | |
12674 | ||
12675 | case 'p': | |
12676 | INSERT_OPERAND (1, MP, *ip, regno); | |
12677 | break; | |
12678 | ||
12679 | case 'q': | |
12680 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12681 | break; | |
12682 | ||
12683 | case 'a': /* Do nothing. */ | |
12684 | case 's': /* Do nothing. */ | |
12685 | case 't': /* Do nothing. */ | |
12686 | case 'x': /* Do nothing. */ | |
12687 | case 'y': /* Do nothing. */ | |
12688 | case 'z': /* Do nothing. */ | |
12689 | break; | |
12690 | ||
12691 | default: | |
12692 | internalError (); | |
12693 | } | |
12694 | continue; | |
12695 | ||
12696 | case 'A': | |
12697 | { | |
12698 | bfd_reloc_code_real_type r[3]; | |
12699 | expressionS ep; | |
12700 | int imm; | |
12701 | ||
12702 | /* Check whether there is only a single bracketed | |
12703 | expression left. If so, it must be the base register | |
12704 | and the constant must be zero. */ | |
12705 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12706 | { | |
12707 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12708 | continue; | |
12709 | } | |
12710 | ||
12711 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12712 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12713 | break; | |
12714 | ||
12715 | imm = ep.X_add_number >> 2; | |
12716 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12717 | } | |
12718 | s = expr_end; | |
12719 | continue; | |
12720 | ||
12721 | case 'B': | |
12722 | { | |
12723 | bfd_reloc_code_real_type r[3]; | |
12724 | expressionS ep; | |
12725 | int imm; | |
12726 | ||
12727 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12728 | || ep.X_op != O_constant) | |
12729 | break; | |
12730 | ||
12731 | for (imm = 0; imm < 8; imm++) | |
12732 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12733 | break; | |
12734 | if (imm >= 8) | |
12735 | break; | |
12736 | ||
12737 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12738 | } | |
12739 | s = expr_end; | |
12740 | continue; | |
12741 | ||
12742 | case 'C': | |
12743 | { | |
12744 | bfd_reloc_code_real_type r[3]; | |
12745 | expressionS ep; | |
12746 | int imm; | |
12747 | ||
12748 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12749 | || ep.X_op != O_constant) | |
12750 | break; | |
12751 | ||
12752 | for (imm = 0; imm < 16; imm++) | |
12753 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12754 | break; | |
12755 | if (imm >= 16) | |
12756 | break; | |
12757 | ||
12758 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12759 | } | |
12760 | s = expr_end; | |
12761 | continue; | |
12762 | ||
12763 | case 'D': /* pc relative offset */ | |
12764 | case 'E': /* pc relative offset */ | |
12765 | my_getExpression (&offset_expr, s); | |
12766 | if (offset_expr.X_op == O_register) | |
12767 | break; | |
12768 | ||
40209cad MR |
12769 | if (!forced_insn_length) |
12770 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
12771 | else if (c == 'D') | |
12772 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
12773 | else | |
12774 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
12775 | s = expr_end; |
12776 | continue; | |
12777 | ||
12778 | case 'F': | |
12779 | { | |
12780 | bfd_reloc_code_real_type r[3]; | |
12781 | expressionS ep; | |
12782 | int imm; | |
12783 | ||
12784 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12785 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12786 | break; | |
12787 | ||
12788 | imm = ep.X_add_number; | |
12789 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
12790 | } | |
12791 | s = expr_end; | |
12792 | continue; | |
12793 | ||
12794 | case 'G': | |
12795 | { | |
12796 | bfd_reloc_code_real_type r[3]; | |
12797 | expressionS ep; | |
12798 | int imm; | |
12799 | ||
12800 | /* Check whether there is only a single bracketed | |
12801 | expression left. If so, it must be the base register | |
12802 | and the constant must be zero. */ | |
12803 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12804 | { | |
12805 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
12806 | continue; | |
12807 | } | |
12808 | ||
12809 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12810 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
12811 | break; | |
12812 | ||
12813 | imm = ep.X_add_number & 15; | |
12814 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
12815 | } | |
12816 | s = expr_end; | |
12817 | continue; | |
12818 | ||
12819 | case 'H': | |
12820 | { | |
12821 | bfd_reloc_code_real_type r[3]; | |
12822 | expressionS ep; | |
12823 | int imm; | |
12824 | ||
12825 | /* Check whether there is only a single bracketed | |
12826 | expression left. If so, it must be the base register | |
12827 | and the constant must be zero. */ | |
12828 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12829 | { | |
12830 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
12831 | continue; | |
12832 | } | |
12833 | ||
12834 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12835 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
12836 | break; | |
12837 | ||
12838 | imm = ep.X_add_number >> 1; | |
12839 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
12840 | } | |
12841 | s = expr_end; | |
12842 | continue; | |
12843 | ||
12844 | case 'I': | |
12845 | { | |
12846 | bfd_reloc_code_real_type r[3]; | |
12847 | expressionS ep; | |
12848 | int imm; | |
12849 | ||
12850 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12851 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
12852 | break; | |
12853 | ||
12854 | imm = ep.X_add_number & 127; | |
12855 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
12856 | } | |
12857 | s = expr_end; | |
12858 | continue; | |
12859 | ||
12860 | case 'J': | |
12861 | { | |
12862 | bfd_reloc_code_real_type r[3]; | |
12863 | expressionS ep; | |
12864 | int imm; | |
12865 | ||
12866 | /* Check whether there is only a single bracketed | |
12867 | expression left. If so, it must be the base register | |
12868 | and the constant must be zero. */ | |
12869 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12870 | { | |
12871 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
12872 | continue; | |
12873 | } | |
12874 | ||
12875 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12876 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
12877 | break; | |
12878 | ||
12879 | imm = ep.X_add_number >> 2; | |
12880 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
12881 | } | |
12882 | s = expr_end; | |
12883 | continue; | |
12884 | ||
12885 | case 'L': | |
12886 | { | |
12887 | bfd_reloc_code_real_type r[3]; | |
12888 | expressionS ep; | |
12889 | int imm; | |
12890 | ||
12891 | /* Check whether there is only a single bracketed | |
12892 | expression left. If so, it must be the base register | |
12893 | and the constant must be zero. */ | |
12894 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12895 | { | |
12896 | INSERT_OPERAND (1, IMML, *ip, 0); | |
12897 | continue; | |
12898 | } | |
12899 | ||
12900 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12901 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12902 | break; | |
12903 | ||
12904 | imm = ep.X_add_number; | |
12905 | INSERT_OPERAND (1, IMML, *ip, imm); | |
12906 | } | |
12907 | s = expr_end; | |
12908 | continue; | |
12909 | ||
12910 | case 'M': | |
12911 | { | |
12912 | bfd_reloc_code_real_type r[3]; | |
12913 | expressionS ep; | |
12914 | int imm; | |
12915 | ||
12916 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12917 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
12918 | break; | |
12919 | ||
12920 | imm = ep.X_add_number & 7; | |
12921 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
12922 | } | |
12923 | s = expr_end; | |
12924 | continue; | |
12925 | ||
12926 | case 'N': /* Register list for lwm and swm. */ | |
12927 | { | |
12928 | /* A comma-separated list of registers and/or | |
12929 | dash-separated contiguous ranges including | |
12930 | both ra and a set of one or more registers | |
12931 | starting at s0 up to s3 which have to be | |
12932 | consecutive, e.g.: | |
12933 | ||
12934 | s0, ra | |
12935 | s0, s1, ra, s2, s3 | |
12936 | s0-s2, ra | |
12937 | ||
12938 | and any permutations of these. */ | |
12939 | unsigned int reglist; | |
12940 | int imm; | |
12941 | ||
12942 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
12943 | break; | |
12944 | ||
12945 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
12946 | break; | |
12947 | ||
12948 | reglist = (reglist >> 17) & 7; | |
12949 | reglist += 1; | |
12950 | if ((reglist & -reglist) != reglist) | |
12951 | break; | |
252b5132 | 12952 | |
df58fc94 RS |
12953 | imm = ffs (reglist) - 1; |
12954 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
12955 | } | |
12956 | continue; | |
252b5132 | 12957 | |
df58fc94 RS |
12958 | case 'O': /* sdbbp 4-bit code. */ |
12959 | { | |
12960 | bfd_reloc_code_real_type r[3]; | |
12961 | expressionS ep; | |
12962 | int imm; | |
12963 | ||
12964 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12965 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12966 | break; | |
12967 | ||
12968 | imm = ep.X_add_number; | |
12969 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 12970 | } |
df58fc94 RS |
12971 | s = expr_end; |
12972 | continue; | |
252b5132 | 12973 | |
df58fc94 RS |
12974 | case 'P': |
12975 | { | |
12976 | bfd_reloc_code_real_type r[3]; | |
12977 | expressionS ep; | |
12978 | int imm; | |
5e0116d5 | 12979 | |
df58fc94 RS |
12980 | if (my_getSmallExpression (&ep, r, s) > 0 |
12981 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12982 | break; | |
5e0116d5 | 12983 | |
df58fc94 RS |
12984 | imm = ep.X_add_number >> 2; |
12985 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
12986 | } | |
12987 | s = expr_end; | |
12988 | continue; | |
5e0116d5 | 12989 | |
df58fc94 RS |
12990 | case 'Q': |
12991 | { | |
12992 | bfd_reloc_code_real_type r[3]; | |
12993 | expressionS ep; | |
12994 | int imm; | |
5e0116d5 | 12995 | |
df58fc94 RS |
12996 | if (my_getSmallExpression (&ep, r, s) > 0 |
12997 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
12998 | break; | |
252b5132 | 12999 | |
df58fc94 RS |
13000 | imm = ep.X_add_number >> 2; |
13001 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13002 | } | |
13003 | s = expr_end; | |
13004 | continue; | |
4614d845 | 13005 | |
df58fc94 RS |
13006 | case 'U': |
13007 | { | |
13008 | bfd_reloc_code_real_type r[3]; | |
13009 | expressionS ep; | |
13010 | int imm; | |
13011 | ||
13012 | /* Check whether there is only a single bracketed | |
13013 | expression left. If so, it must be the base register | |
13014 | and the constant must be zero. */ | |
13015 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13016 | { | |
13017 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13018 | continue; | |
13019 | } | |
13020 | ||
13021 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13022 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13023 | break; | |
13024 | ||
13025 | imm = ep.X_add_number >> 2; | |
13026 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13027 | } | |
13028 | s = expr_end; | |
5e0116d5 | 13029 | continue; |
252b5132 | 13030 | |
df58fc94 RS |
13031 | case 'W': |
13032 | { | |
13033 | bfd_reloc_code_real_type r[3]; | |
13034 | expressionS ep; | |
13035 | int imm; | |
252b5132 | 13036 | |
df58fc94 RS |
13037 | if (my_getSmallExpression (&ep, r, s) > 0 |
13038 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13039 | break; | |
252b5132 | 13040 | |
df58fc94 RS |
13041 | imm = ep.X_add_number >> 2; |
13042 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13043 | } | |
13044 | s = expr_end; | |
13045 | continue; | |
252b5132 | 13046 | |
df58fc94 RS |
13047 | case 'X': |
13048 | { | |
13049 | bfd_reloc_code_real_type r[3]; | |
13050 | expressionS ep; | |
13051 | int imm; | |
252b5132 | 13052 | |
df58fc94 RS |
13053 | if (my_getSmallExpression (&ep, r, s) > 0 |
13054 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13055 | break; | |
252b5132 | 13056 | |
df58fc94 RS |
13057 | imm = ep.X_add_number; |
13058 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13059 | } | |
13060 | s = expr_end; | |
13061 | continue; | |
252b5132 | 13062 | |
df58fc94 RS |
13063 | case 'Y': |
13064 | { | |
13065 | bfd_reloc_code_real_type r[3]; | |
13066 | expressionS ep; | |
13067 | int imm; | |
156c2f8b | 13068 | |
df58fc94 RS |
13069 | if (my_getSmallExpression (&ep, r, s) > 0 |
13070 | || expr_const_in_range (&ep, -2, 2, 2) | |
13071 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13072 | break; | |
156c2f8b | 13073 | |
df58fc94 RS |
13074 | imm = ep.X_add_number >> 2; |
13075 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13076 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13077 | } | |
13078 | s = expr_end; | |
13079 | continue; | |
60b63b72 | 13080 | |
df58fc94 RS |
13081 | case 'Z': |
13082 | { | |
13083 | bfd_reloc_code_real_type r[3]; | |
13084 | expressionS ep; | |
13085 | ||
13086 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13087 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13088 | break; | |
13089 | } | |
13090 | s = expr_end; | |
13091 | continue; | |
13092 | ||
13093 | default: | |
13094 | as_bad (_("Internal error: bad microMIPS opcode " | |
13095 | "(unknown extension operand type `m%c'): %s %s"), | |
13096 | *args, insn->name, insn->args); | |
13097 | /* Further processing is fruitless. */ | |
13098 | return; | |
60b63b72 | 13099 | } |
df58fc94 | 13100 | break; |
60b63b72 | 13101 | |
df58fc94 RS |
13102 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13103 | gas_assert (mips_opts.micromips); | |
13104 | { | |
13105 | /* A comma-separated list of registers and/or | |
13106 | dash-separated contiguous ranges including | |
13107 | at least one of ra and a set of one or more | |
13108 | registers starting at s0 up to s7 and then | |
13109 | s8 which have to be consecutive, e.g.: | |
13110 | ||
13111 | ra | |
13112 | s0 | |
13113 | ra, s0, s1, s2 | |
13114 | s0-s8 | |
13115 | s0-s5, ra | |
13116 | ||
13117 | and any permutations of these. */ | |
13118 | unsigned int reglist; | |
13119 | int imm; | |
13120 | int ra; | |
13121 | ||
13122 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13123 | break; | |
13124 | ||
13125 | if ((reglist & 0x3f00ffff) != 0) | |
13126 | break; | |
13127 | ||
13128 | ra = (reglist >> 27) & 0x10; | |
13129 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13130 | reglist += 1; | |
13131 | if ((reglist & -reglist) != reglist) | |
13132 | break; | |
13133 | ||
13134 | imm = (ffs (reglist) - 1) | ra; | |
13135 | INSERT_OPERAND (1, RT, *ip, imm); | |
13136 | imm_expr.X_op = O_absent; | |
13137 | } | |
60b63b72 RS |
13138 | continue; |
13139 | ||
df58fc94 RS |
13140 | case '|': /* 4-bit trap code. */ |
13141 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13142 | my_getExpression (&imm_expr, s); |
13143 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13144 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13145 | > MICROMIPSOP_MASK_TRAP) |
13146 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13147 | (unsigned long) imm_expr.X_add_number, | |
13148 | ip->insn_mo->name); | |
13149 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13150 | imm_expr.X_op = O_absent; |
13151 | s = expr_end; | |
13152 | continue; | |
13153 | ||
252b5132 | 13154 | default: |
f71d0d44 | 13155 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
13156 | internalError (); |
13157 | } | |
13158 | break; | |
13159 | } | |
13160 | /* Args don't match. */ | |
df58fc94 RS |
13161 | s = argsStart; |
13162 | insn_error = _("Illegal operands"); | |
13163 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13164 | { |
13165 | ++insn; | |
252b5132 RH |
13166 | continue; |
13167 | } | |
df58fc94 RS |
13168 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13169 | { | |
13170 | gas_assert (firstinsn); | |
13171 | need_delay_slot_ok = FALSE; | |
13172 | past = insn + 1; | |
13173 | insn = firstinsn; | |
13174 | continue; | |
13175 | } | |
252b5132 RH |
13176 | return; |
13177 | } | |
13178 | } | |
13179 | ||
0499d65b TS |
13180 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13181 | ||
252b5132 RH |
13182 | /* This routine assembles an instruction into its binary format when |
13183 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13184 | global variables imm_reloc or offset_reloc to the type of relocation |
13185 | to do if one of the operands is an address expression. It also sets | |
13186 | forced_insn_length to the resulting instruction size in bytes if the | |
13187 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13188 | |
13189 | static void | |
17a2f251 | 13190 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13191 | { |
13192 | char *s; | |
13193 | const char *args; | |
13194 | struct mips_opcode *insn; | |
13195 | char *argsstart; | |
13196 | unsigned int regno; | |
13197 | unsigned int lastregno = 0; | |
13198 | char *s_reset; | |
d6f16593 | 13199 | size_t i; |
252b5132 RH |
13200 | |
13201 | insn_error = NULL; | |
13202 | ||
df58fc94 | 13203 | forced_insn_length = 0; |
252b5132 | 13204 | |
3882b010 | 13205 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13206 | ; |
13207 | switch (*s) | |
13208 | { | |
13209 | case '\0': | |
13210 | break; | |
13211 | ||
13212 | case ' ': | |
13213 | *s++ = '\0'; | |
13214 | break; | |
13215 | ||
13216 | case '.': | |
13217 | if (s[1] == 't' && s[2] == ' ') | |
13218 | { | |
13219 | *s = '\0'; | |
df58fc94 | 13220 | forced_insn_length = 2; |
252b5132 RH |
13221 | s += 3; |
13222 | break; | |
13223 | } | |
13224 | else if (s[1] == 'e' && s[2] == ' ') | |
13225 | { | |
13226 | *s = '\0'; | |
df58fc94 | 13227 | forced_insn_length = 4; |
252b5132 RH |
13228 | s += 3; |
13229 | break; | |
13230 | } | |
13231 | /* Fall through. */ | |
13232 | default: | |
13233 | insn_error = _("unknown opcode"); | |
13234 | return; | |
13235 | } | |
13236 | ||
df58fc94 RS |
13237 | if (mips_opts.noautoextend && !forced_insn_length) |
13238 | forced_insn_length = 2; | |
252b5132 RH |
13239 | |
13240 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13241 | { | |
13242 | insn_error = _("unrecognized opcode"); | |
13243 | return; | |
13244 | } | |
13245 | ||
13246 | argsstart = s; | |
13247 | for (;;) | |
13248 | { | |
9b3f89ee TS |
13249 | bfd_boolean ok; |
13250 | ||
9c2799c2 | 13251 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13252 | |
037b32b9 | 13253 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13254 | if (! ok) |
13255 | { | |
13256 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13257 | && strcmp (insn->name, insn[1].name) == 0) | |
13258 | { | |
13259 | ++insn; | |
13260 | continue; | |
13261 | } | |
13262 | else | |
13263 | { | |
13264 | if (!insn_error) | |
13265 | { | |
13266 | static char buf[100]; | |
13267 | sprintf (buf, | |
7bd942df | 13268 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13269 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13270 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13271 | insn_error = buf; | |
13272 | } | |
13273 | return; | |
13274 | } | |
13275 | } | |
13276 | ||
1e915849 | 13277 | create_insn (ip, insn); |
252b5132 | 13278 | imm_expr.X_op = O_absent; |
f6688943 TS |
13279 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13280 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13281 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13282 | imm2_expr.X_op = O_absent; |
252b5132 | 13283 | offset_expr.X_op = O_absent; |
f6688943 TS |
13284 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13285 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13286 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13287 | for (args = insn->args; 1; ++args) |
13288 | { | |
13289 | int c; | |
13290 | ||
13291 | if (*s == ' ') | |
13292 | ++s; | |
13293 | ||
13294 | /* In this switch statement we call break if we did not find | |
13295 | a match, continue if we did find a match, or return if we | |
13296 | are done. */ | |
13297 | ||
13298 | c = *args; | |
13299 | switch (c) | |
13300 | { | |
13301 | case '\0': | |
13302 | if (*s == '\0') | |
13303 | { | |
13304 | /* Stuff the immediate value in now, if we can. */ | |
13305 | if (imm_expr.X_op == O_constant | |
f6688943 | 13306 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
13307 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
13308 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
13309 | && insn->pinfo != INSN_MACRO) |
13310 | { | |
d6f16593 MR |
13311 | valueT tmp; |
13312 | ||
13313 | switch (*offset_reloc) | |
13314 | { | |
13315 | case BFD_RELOC_MIPS16_HI16_S: | |
13316 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
13317 | break; | |
13318 | ||
13319 | case BFD_RELOC_MIPS16_HI16: | |
13320 | tmp = imm_expr.X_add_number >> 16; | |
13321 | break; | |
13322 | ||
13323 | case BFD_RELOC_MIPS16_LO16: | |
13324 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
13325 | - 0x8000; | |
13326 | break; | |
13327 | ||
13328 | case BFD_RELOC_UNUSED: | |
13329 | tmp = imm_expr.X_add_number; | |
13330 | break; | |
13331 | ||
13332 | default: | |
13333 | internalError (); | |
13334 | } | |
13335 | *offset_reloc = BFD_RELOC_UNUSED; | |
13336 | ||
c4e7957c | 13337 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
df58fc94 RS |
13338 | tmp, TRUE, forced_insn_length == 2, |
13339 | forced_insn_length == 4, &ip->insn_opcode, | |
252b5132 RH |
13340 | &ip->use_extend, &ip->extend); |
13341 | imm_expr.X_op = O_absent; | |
f6688943 | 13342 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13343 | } |
13344 | ||
13345 | return; | |
13346 | } | |
13347 | break; | |
13348 | ||
13349 | case ',': | |
13350 | if (*s++ == c) | |
13351 | continue; | |
13352 | s--; | |
13353 | switch (*++args) | |
13354 | { | |
13355 | case 'v': | |
bf12938e | 13356 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13357 | continue; |
13358 | case 'w': | |
bf12938e | 13359 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13360 | continue; |
13361 | } | |
13362 | break; | |
13363 | ||
13364 | case '(': | |
13365 | case ')': | |
13366 | if (*s++ == c) | |
13367 | continue; | |
13368 | break; | |
13369 | ||
13370 | case 'v': | |
13371 | case 'w': | |
13372 | if (s[0] != '$') | |
13373 | { | |
13374 | if (c == 'v') | |
bf12938e | 13375 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13376 | else |
bf12938e | 13377 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13378 | ++args; |
13379 | continue; | |
13380 | } | |
13381 | /* Fall through. */ | |
13382 | case 'x': | |
13383 | case 'y': | |
13384 | case 'z': | |
13385 | case 'Z': | |
13386 | case '0': | |
13387 | case 'S': | |
13388 | case 'R': | |
13389 | case 'X': | |
13390 | case 'Y': | |
707bfff6 TS |
13391 | s_reset = s; |
13392 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13393 | { |
707bfff6 | 13394 | if (c == 'v' || c == 'w') |
85b51719 | 13395 | { |
707bfff6 | 13396 | if (c == 'v') |
a9e24354 | 13397 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13398 | else |
a9e24354 | 13399 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13400 | ++args; |
13401 | continue; | |
85b51719 | 13402 | } |
707bfff6 | 13403 | break; |
252b5132 RH |
13404 | } |
13405 | ||
13406 | if (*s == ' ') | |
13407 | ++s; | |
13408 | if (args[1] != *s) | |
13409 | { | |
13410 | if (c == 'v' || c == 'w') | |
13411 | { | |
13412 | regno = mips16_to_32_reg_map[lastregno]; | |
13413 | s = s_reset; | |
f9419b05 | 13414 | ++args; |
252b5132 RH |
13415 | } |
13416 | } | |
13417 | ||
13418 | switch (c) | |
13419 | { | |
13420 | case 'x': | |
13421 | case 'y': | |
13422 | case 'z': | |
13423 | case 'v': | |
13424 | case 'w': | |
13425 | case 'Z': | |
13426 | regno = mips32_to_16_reg_map[regno]; | |
13427 | break; | |
13428 | ||
13429 | case '0': | |
13430 | if (regno != 0) | |
13431 | regno = ILLEGAL_REG; | |
13432 | break; | |
13433 | ||
13434 | case 'S': | |
13435 | if (regno != SP) | |
13436 | regno = ILLEGAL_REG; | |
13437 | break; | |
13438 | ||
13439 | case 'R': | |
13440 | if (regno != RA) | |
13441 | regno = ILLEGAL_REG; | |
13442 | break; | |
13443 | ||
13444 | case 'X': | |
13445 | case 'Y': | |
741fe287 MR |
13446 | if (regno == AT && mips_opts.at) |
13447 | { | |
13448 | if (mips_opts.at == ATREG) | |
13449 | as_warn (_("used $at without \".set noat\"")); | |
13450 | else | |
13451 | as_warn (_("used $%u with \".set at=$%u\""), | |
13452 | regno, mips_opts.at); | |
13453 | } | |
252b5132 RH |
13454 | break; |
13455 | ||
13456 | default: | |
13457 | internalError (); | |
13458 | } | |
13459 | ||
13460 | if (regno == ILLEGAL_REG) | |
13461 | break; | |
13462 | ||
13463 | switch (c) | |
13464 | { | |
13465 | case 'x': | |
13466 | case 'v': | |
bf12938e | 13467 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13468 | break; |
13469 | case 'y': | |
13470 | case 'w': | |
bf12938e | 13471 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13472 | break; |
13473 | case 'z': | |
bf12938e | 13474 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13475 | break; |
13476 | case 'Z': | |
bf12938e | 13477 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13478 | case '0': |
13479 | case 'S': | |
13480 | case 'R': | |
13481 | break; | |
13482 | case 'X': | |
bf12938e | 13483 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13484 | break; |
13485 | case 'Y': | |
13486 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13487 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13488 | break; |
13489 | default: | |
13490 | internalError (); | |
13491 | } | |
13492 | ||
13493 | lastregno = regno; | |
13494 | continue; | |
13495 | ||
13496 | case 'P': | |
13497 | if (strncmp (s, "$pc", 3) == 0) | |
13498 | { | |
13499 | s += 3; | |
13500 | continue; | |
13501 | } | |
13502 | break; | |
13503 | ||
252b5132 RH |
13504 | case '5': |
13505 | case 'H': | |
13506 | case 'W': | |
13507 | case 'D': | |
13508 | case 'j': | |
252b5132 RH |
13509 | case 'V': |
13510 | case 'C': | |
13511 | case 'U': | |
13512 | case 'k': | |
13513 | case 'K': | |
d6f16593 MR |
13514 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13515 | if (i > 0) | |
252b5132 | 13516 | { |
d6f16593 | 13517 | if (imm_expr.X_op != O_constant) |
252b5132 | 13518 | { |
df58fc94 | 13519 | forced_insn_length = 4; |
b34976b6 | 13520 | ip->use_extend = TRUE; |
252b5132 | 13521 | ip->extend = 0; |
252b5132 | 13522 | } |
d6f16593 MR |
13523 | else |
13524 | { | |
13525 | /* We need to relax this instruction. */ | |
13526 | *offset_reloc = *imm_reloc; | |
13527 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13528 | } | |
13529 | s = expr_end; | |
13530 | continue; | |
252b5132 | 13531 | } |
d6f16593 MR |
13532 | *imm_reloc = BFD_RELOC_UNUSED; |
13533 | /* Fall through. */ | |
13534 | case '<': | |
13535 | case '>': | |
13536 | case '[': | |
13537 | case ']': | |
13538 | case '4': | |
13539 | case '8': | |
13540 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13541 | if (imm_expr.X_op == O_register) |
13542 | { | |
13543 | /* What we thought was an expression turned out to | |
13544 | be a register. */ | |
13545 | ||
13546 | if (s[0] == '(' && args[1] == '(') | |
13547 | { | |
13548 | /* It looks like the expression was omitted | |
13549 | before a register indirection, which means | |
13550 | that the expression is implicitly zero. We | |
13551 | still set up imm_expr, so that we handle | |
13552 | explicit extensions correctly. */ | |
13553 | imm_expr.X_op = O_constant; | |
13554 | imm_expr.X_add_number = 0; | |
f6688943 | 13555 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13556 | continue; |
13557 | } | |
13558 | ||
13559 | break; | |
13560 | } | |
13561 | ||
13562 | /* We need to relax this instruction. */ | |
f6688943 | 13563 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13564 | s = expr_end; |
13565 | continue; | |
13566 | ||
13567 | case 'p': | |
13568 | case 'q': | |
13569 | case 'A': | |
13570 | case 'B': | |
13571 | case 'E': | |
13572 | /* We use offset_reloc rather than imm_reloc for the PC | |
13573 | relative operands. This lets macros with both | |
13574 | immediate and address operands work correctly. */ | |
13575 | my_getExpression (&offset_expr, s); | |
13576 | ||
13577 | if (offset_expr.X_op == O_register) | |
13578 | break; | |
13579 | ||
13580 | /* We need to relax this instruction. */ | |
f6688943 | 13581 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13582 | s = expr_end; |
13583 | continue; | |
13584 | ||
13585 | case '6': /* break code */ | |
13586 | my_getExpression (&imm_expr, s); | |
13587 | check_absolute_expr (ip, &imm_expr); | |
13588 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13589 | as_warn (_("Invalid value for `%s' (%lu)"), |
13590 | ip->insn_mo->name, | |
13591 | (unsigned long) imm_expr.X_add_number); | |
13592 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13593 | imm_expr.X_op = O_absent; |
13594 | s = expr_end; | |
13595 | continue; | |
13596 | ||
13597 | case 'a': /* 26 bit address */ | |
13598 | my_getExpression (&offset_expr, s); | |
13599 | s = expr_end; | |
f6688943 | 13600 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13601 | ip->insn_opcode <<= 16; |
13602 | continue; | |
13603 | ||
13604 | case 'l': /* register list for entry macro */ | |
13605 | case 'L': /* register list for exit macro */ | |
13606 | { | |
13607 | int mask; | |
13608 | ||
13609 | if (c == 'l') | |
13610 | mask = 0; | |
13611 | else | |
13612 | mask = 7 << 3; | |
13613 | while (*s != '\0') | |
13614 | { | |
707bfff6 | 13615 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13616 | |
13617 | while (*s == ' ' || *s == ',') | |
13618 | ++s; | |
707bfff6 | 13619 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13620 | freg = 0; |
707bfff6 TS |
13621 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13622 | freg = 1; | |
252b5132 RH |
13623 | else |
13624 | { | |
707bfff6 TS |
13625 | as_bad (_("can't parse register list")); |
13626 | break; | |
252b5132 RH |
13627 | } |
13628 | if (*s == ' ') | |
13629 | ++s; | |
13630 | if (*s != '-') | |
13631 | reg2 = reg1; | |
13632 | else | |
13633 | { | |
13634 | ++s; | |
707bfff6 TS |
13635 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13636 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13637 | { |
707bfff6 TS |
13638 | as_bad (_("invalid register list")); |
13639 | break; | |
252b5132 RH |
13640 | } |
13641 | } | |
13642 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13643 | { | |
13644 | mask &= ~ (7 << 3); | |
13645 | mask |= 5 << 3; | |
13646 | } | |
13647 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13648 | { | |
13649 | mask &= ~ (7 << 3); | |
13650 | mask |= 6 << 3; | |
13651 | } | |
13652 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13653 | mask |= (reg2 - 3) << 3; | |
13654 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13655 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13656 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13657 | mask |= 1; |
13658 | else | |
13659 | { | |
13660 | as_bad (_("invalid register list")); | |
13661 | break; | |
13662 | } | |
13663 | } | |
13664 | /* The mask is filled in in the opcode table for the | |
13665 | benefit of the disassembler. We remove it before | |
13666 | applying the actual mask. */ | |
13667 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13668 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13669 | } | |
13670 | continue; | |
13671 | ||
0499d65b TS |
13672 | case 'm': /* Register list for save insn. */ |
13673 | case 'M': /* Register list for restore insn. */ | |
13674 | { | |
13675 | int opcode = 0; | |
13676 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 13677 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13678 | |
13679 | while (*s != '\0') | |
13680 | { | |
13681 | unsigned int reg1, reg2; | |
13682 | ||
13683 | SKIP_SPACE_TABS (s); | |
13684 | while (*s == ',') | |
13685 | ++s; | |
13686 | SKIP_SPACE_TABS (s); | |
13687 | ||
13688 | my_getExpression (&imm_expr, s); | |
13689 | if (imm_expr.X_op == O_constant) | |
13690 | { | |
13691 | /* Handle the frame size. */ | |
13692 | if (seen_framesz) | |
13693 | { | |
13694 | as_bad (_("more than one frame size in list")); | |
13695 | break; | |
13696 | } | |
13697 | seen_framesz = 1; | |
13698 | framesz = imm_expr.X_add_number; | |
13699 | imm_expr.X_op = O_absent; | |
13700 | s = expr_end; | |
13701 | continue; | |
13702 | } | |
13703 | ||
707bfff6 | 13704 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13705 | { |
13706 | as_bad (_("can't parse register list")); | |
13707 | break; | |
13708 | } | |
0499d65b | 13709 | |
707bfff6 TS |
13710 | while (*s == ' ') |
13711 | ++s; | |
13712 | ||
0499d65b TS |
13713 | if (*s != '-') |
13714 | reg2 = reg1; | |
13715 | else | |
13716 | { | |
13717 | ++s; | |
707bfff6 TS |
13718 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13719 | || reg2 < reg1) | |
0499d65b TS |
13720 | { |
13721 | as_bad (_("can't parse register list")); | |
13722 | break; | |
13723 | } | |
0499d65b TS |
13724 | } |
13725 | ||
13726 | while (reg1 <= reg2) | |
13727 | { | |
13728 | if (reg1 >= 4 && reg1 <= 7) | |
13729 | { | |
3a93f742 | 13730 | if (!seen_framesz) |
0499d65b | 13731 | /* args $a0-$a3 */ |
91d6fa6a | 13732 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13733 | else |
13734 | /* statics $a0-$a3 */ | |
13735 | statics |= 1 << (reg1 - 4); | |
13736 | } | |
13737 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13738 | { | |
13739 | /* $s0-$s8 */ | |
13740 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13741 | } | |
13742 | else if (reg1 == 31) | |
13743 | { | |
13744 | /* Add $ra to insn. */ | |
13745 | opcode |= 0x40; | |
13746 | } | |
13747 | else | |
13748 | { | |
13749 | as_bad (_("unexpected register in list")); | |
13750 | break; | |
13751 | } | |
13752 | if (++reg1 == 24) | |
13753 | reg1 = 30; | |
13754 | } | |
13755 | } | |
13756 | ||
13757 | /* Encode args/statics combination. */ | |
91d6fa6a | 13758 | if (nargs & statics) |
0499d65b | 13759 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13760 | else if (nargs == 0xf) |
0499d65b TS |
13761 | /* All $a0-$a3 are args. */ |
13762 | opcode |= MIPS16_ALL_ARGS << 16; | |
13763 | else if (statics == 0xf) | |
13764 | /* All $a0-$a3 are statics. */ | |
13765 | opcode |= MIPS16_ALL_STATICS << 16; | |
13766 | else | |
13767 | { | |
13768 | int narg = 0, nstat = 0; | |
13769 | ||
13770 | /* Count arg registers. */ | |
91d6fa6a | 13771 | while (nargs & 0x1) |
0499d65b | 13772 | { |
91d6fa6a | 13773 | nargs >>= 1; |
0499d65b TS |
13774 | narg++; |
13775 | } | |
91d6fa6a | 13776 | if (nargs != 0) |
0499d65b TS |
13777 | as_bad (_("invalid arg register list")); |
13778 | ||
13779 | /* Count static registers. */ | |
13780 | while (statics & 0x8) | |
13781 | { | |
13782 | statics = (statics << 1) & 0xf; | |
13783 | nstat++; | |
13784 | } | |
13785 | if (statics != 0) | |
13786 | as_bad (_("invalid static register list")); | |
13787 | ||
13788 | /* Encode args/statics. */ | |
13789 | opcode |= ((narg << 2) | nstat) << 16; | |
13790 | } | |
13791 | ||
13792 | /* Encode $s0/$s1. */ | |
13793 | if (sregs & (1 << 0)) /* $s0 */ | |
13794 | opcode |= 0x20; | |
13795 | if (sregs & (1 << 1)) /* $s1 */ | |
13796 | opcode |= 0x10; | |
13797 | sregs >>= 2; | |
13798 | ||
13799 | if (sregs != 0) | |
13800 | { | |
13801 | /* Count regs $s2-$s8. */ | |
13802 | int nsreg = 0; | |
13803 | while (sregs & 1) | |
13804 | { | |
13805 | sregs >>= 1; | |
13806 | nsreg++; | |
13807 | } | |
13808 | if (sregs != 0) | |
13809 | as_bad (_("invalid static register list")); | |
13810 | /* Encode $s2-$s8. */ | |
13811 | opcode |= nsreg << 24; | |
13812 | } | |
13813 | ||
13814 | /* Encode frame size. */ | |
13815 | if (!seen_framesz) | |
13816 | as_bad (_("missing frame size")); | |
13817 | else if ((framesz & 7) != 0 || framesz < 0 | |
13818 | || framesz > 0xff * 8) | |
13819 | as_bad (_("invalid frame size")); | |
13820 | else if (framesz != 128 || (opcode >> 16) != 0) | |
13821 | { | |
13822 | framesz /= 8; | |
13823 | opcode |= (((framesz & 0xf0) << 16) | |
13824 | | (framesz & 0x0f)); | |
13825 | } | |
13826 | ||
13827 | /* Finally build the instruction. */ | |
13828 | if ((opcode >> 16) != 0 || framesz == 0) | |
13829 | { | |
13830 | ip->use_extend = TRUE; | |
13831 | ip->extend = opcode >> 16; | |
13832 | } | |
13833 | ip->insn_opcode |= opcode & 0x7f; | |
13834 | } | |
13835 | continue; | |
13836 | ||
252b5132 RH |
13837 | case 'e': /* extend code */ |
13838 | my_getExpression (&imm_expr, s); | |
13839 | check_absolute_expr (ip, &imm_expr); | |
13840 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
13841 | { | |
13842 | as_warn (_("Invalid value for `%s' (%lu)"), | |
13843 | ip->insn_mo->name, | |
13844 | (unsigned long) imm_expr.X_add_number); | |
13845 | imm_expr.X_add_number &= 0x7ff; | |
13846 | } | |
13847 | ip->insn_opcode |= imm_expr.X_add_number; | |
13848 | imm_expr.X_op = O_absent; | |
13849 | s = expr_end; | |
13850 | continue; | |
13851 | ||
13852 | default: | |
13853 | internalError (); | |
13854 | } | |
13855 | break; | |
13856 | } | |
13857 | ||
13858 | /* Args don't match. */ | |
13859 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
13860 | strcmp (insn->name, insn[1].name) == 0) | |
13861 | { | |
13862 | ++insn; | |
13863 | s = argsstart; | |
13864 | continue; | |
13865 | } | |
13866 | ||
13867 | insn_error = _("illegal operands"); | |
13868 | ||
13869 | return; | |
13870 | } | |
13871 | } | |
13872 | ||
13873 | /* This structure holds information we know about a mips16 immediate | |
13874 | argument type. */ | |
13875 | ||
e972090a NC |
13876 | struct mips16_immed_operand |
13877 | { | |
252b5132 RH |
13878 | /* The type code used in the argument string in the opcode table. */ |
13879 | int type; | |
13880 | /* The number of bits in the short form of the opcode. */ | |
13881 | int nbits; | |
13882 | /* The number of bits in the extended form of the opcode. */ | |
13883 | int extbits; | |
13884 | /* The amount by which the short form is shifted when it is used; | |
13885 | for example, the sw instruction has a shift count of 2. */ | |
13886 | int shift; | |
13887 | /* The amount by which the short form is shifted when it is stored | |
13888 | into the instruction code. */ | |
13889 | int op_shift; | |
13890 | /* Non-zero if the short form is unsigned. */ | |
13891 | int unsp; | |
13892 | /* Non-zero if the extended form is unsigned. */ | |
13893 | int extu; | |
13894 | /* Non-zero if the value is PC relative. */ | |
13895 | int pcrel; | |
13896 | }; | |
13897 | ||
13898 | /* The mips16 immediate operand types. */ | |
13899 | ||
13900 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
13901 | { | |
13902 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13903 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13904 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13905 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13906 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
13907 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13908 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13909 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13910 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13911 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
13912 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13913 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13914 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13915 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
13916 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13917 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13918 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13919 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13920 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
13921 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
13922 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
13923 | }; | |
13924 | ||
13925 | #define MIPS16_NUM_IMMED \ | |
13926 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
13927 | ||
13928 | /* Handle a mips16 instruction with an immediate value. This or's the | |
13929 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
13930 | whether an extended value is needed; if one is needed, it sets | |
13931 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
13932 | If SMALL is true, an unextended opcode was explicitly requested. | |
13933 | If EXT is true, an extended opcode was explicitly requested. If | |
13934 | WARN is true, warn if EXT does not match reality. */ | |
13935 | ||
13936 | static void | |
17a2f251 TS |
13937 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
13938 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
13939 | unsigned long *insn, bfd_boolean *use_extend, | |
13940 | unsigned short *extend) | |
252b5132 | 13941 | { |
3994f87e | 13942 | const struct mips16_immed_operand *op; |
252b5132 | 13943 | int mintiny, maxtiny; |
b34976b6 | 13944 | bfd_boolean needext; |
252b5132 RH |
13945 | |
13946 | op = mips16_immed_operands; | |
13947 | while (op->type != type) | |
13948 | { | |
13949 | ++op; | |
9c2799c2 | 13950 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13951 | } |
13952 | ||
13953 | if (op->unsp) | |
13954 | { | |
13955 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13956 | { | |
13957 | mintiny = 1; | |
13958 | maxtiny = 1 << op->nbits; | |
13959 | } | |
13960 | else | |
13961 | { | |
13962 | mintiny = 0; | |
13963 | maxtiny = (1 << op->nbits) - 1; | |
13964 | } | |
13965 | } | |
13966 | else | |
13967 | { | |
13968 | mintiny = - (1 << (op->nbits - 1)); | |
13969 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13970 | } | |
13971 | ||
13972 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13973 | if (type == 'p' || type == 'q') | |
13974 | val /= 2; | |
13975 | ||
13976 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13977 | || val < (mintiny << op->shift) | |
13978 | || val > (maxtiny << op->shift)) | |
b34976b6 | 13979 | needext = TRUE; |
252b5132 | 13980 | else |
b34976b6 | 13981 | needext = FALSE; |
252b5132 RH |
13982 | |
13983 | if (warn && ext && ! needext) | |
beae10d5 KH |
13984 | as_warn_where (file, line, |
13985 | _("extended operand requested but not required")); | |
252b5132 RH |
13986 | if (small && needext) |
13987 | as_bad_where (file, line, _("invalid unextended operand value")); | |
13988 | ||
13989 | if (small || (! ext && ! needext)) | |
13990 | { | |
13991 | int insnval; | |
13992 | ||
b34976b6 | 13993 | *use_extend = FALSE; |
252b5132 RH |
13994 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
13995 | insnval <<= op->op_shift; | |
13996 | *insn |= insnval; | |
13997 | } | |
13998 | else | |
13999 | { | |
14000 | long minext, maxext; | |
14001 | int extval; | |
14002 | ||
14003 | if (op->extu) | |
14004 | { | |
14005 | minext = 0; | |
14006 | maxext = (1 << op->extbits) - 1; | |
14007 | } | |
14008 | else | |
14009 | { | |
14010 | minext = - (1 << (op->extbits - 1)); | |
14011 | maxext = (1 << (op->extbits - 1)) - 1; | |
14012 | } | |
14013 | if (val < minext || val > maxext) | |
14014 | as_bad_where (file, line, | |
14015 | _("operand value out of range for instruction")); | |
14016 | ||
b34976b6 | 14017 | *use_extend = TRUE; |
252b5132 RH |
14018 | if (op->extbits == 16) |
14019 | { | |
14020 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14021 | val &= 0x1f; | |
14022 | } | |
14023 | else if (op->extbits == 15) | |
14024 | { | |
14025 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14026 | val &= 0xf; | |
14027 | } | |
14028 | else | |
14029 | { | |
14030 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14031 | val = 0; | |
14032 | } | |
14033 | ||
14034 | *extend = (unsigned short) extval; | |
14035 | *insn |= val; | |
14036 | } | |
14037 | } | |
14038 | \f | |
d6f16593 | 14039 | struct percent_op_match |
ad8d3bb3 | 14040 | { |
5e0116d5 RS |
14041 | const char *str; |
14042 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14043 | }; |
14044 | ||
14045 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14046 | { |
5e0116d5 | 14047 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14048 | #ifdef OBJ_ELF |
5e0116d5 RS |
14049 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14050 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14051 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14052 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14053 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14054 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14055 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14056 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14057 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14058 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14059 | {"%half", BFD_RELOC_16}, | |
14060 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14061 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14062 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14063 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14064 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14065 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14066 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14067 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14068 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14069 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14070 | #endif |
5e0116d5 | 14071 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14072 | }; |
14073 | ||
d6f16593 MR |
14074 | static const struct percent_op_match mips16_percent_op[] = |
14075 | { | |
14076 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14077 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14078 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14079 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14080 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14081 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14082 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14083 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14084 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14085 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14086 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14087 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14088 | }; |
14089 | ||
252b5132 | 14090 | |
5e0116d5 RS |
14091 | /* Return true if *STR points to a relocation operator. When returning true, |
14092 | move *STR over the operator and store its relocation code in *RELOC. | |
14093 | Leave both *STR and *RELOC alone when returning false. */ | |
14094 | ||
14095 | static bfd_boolean | |
17a2f251 | 14096 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14097 | { |
d6f16593 MR |
14098 | const struct percent_op_match *percent_op; |
14099 | size_t limit, i; | |
14100 | ||
14101 | if (mips_opts.mips16) | |
14102 | { | |
14103 | percent_op = mips16_percent_op; | |
14104 | limit = ARRAY_SIZE (mips16_percent_op); | |
14105 | } | |
14106 | else | |
14107 | { | |
14108 | percent_op = mips_percent_op; | |
14109 | limit = ARRAY_SIZE (mips_percent_op); | |
14110 | } | |
76b3015f | 14111 | |
d6f16593 | 14112 | for (i = 0; i < limit; i++) |
5e0116d5 | 14113 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14114 | { |
3f98094e DJ |
14115 | int len = strlen (percent_op[i].str); |
14116 | ||
14117 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14118 | continue; | |
14119 | ||
5e0116d5 RS |
14120 | *str += strlen (percent_op[i].str); |
14121 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14122 | |
5e0116d5 RS |
14123 | /* Check whether the output BFD supports this relocation. |
14124 | If not, issue an error and fall back on something safe. */ | |
14125 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14126 | { |
20203fb9 | 14127 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14128 | percent_op[i].str); |
01a3f561 | 14129 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14130 | } |
5e0116d5 | 14131 | return TRUE; |
394f9b3a | 14132 | } |
5e0116d5 | 14133 | return FALSE; |
394f9b3a | 14134 | } |
ad8d3bb3 | 14135 | |
ad8d3bb3 | 14136 | |
5e0116d5 RS |
14137 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14138 | expression in *EP and the relocations in the array starting | |
14139 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14140 | |
01a3f561 | 14141 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14142 | |
5e0116d5 | 14143 | static size_t |
17a2f251 TS |
14144 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14145 | char *str) | |
ad8d3bb3 | 14146 | { |
5e0116d5 RS |
14147 | bfd_reloc_code_real_type reversed_reloc[3]; |
14148 | size_t reloc_index, i; | |
09b8f35a RS |
14149 | int crux_depth, str_depth; |
14150 | char *crux; | |
5e0116d5 RS |
14151 | |
14152 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14153 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14154 | of the main expression and with CRUX_DEPTH containing the number | |
14155 | of open brackets at that point. */ | |
14156 | reloc_index = -1; | |
14157 | str_depth = 0; | |
14158 | do | |
fb1b3232 | 14159 | { |
09b8f35a RS |
14160 | reloc_index++; |
14161 | crux = str; | |
14162 | crux_depth = str_depth; | |
14163 | ||
14164 | /* Skip over whitespace and brackets, keeping count of the number | |
14165 | of brackets. */ | |
14166 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14167 | if (*str++ == '(') | |
14168 | str_depth++; | |
5e0116d5 | 14169 | } |
09b8f35a RS |
14170 | while (*str == '%' |
14171 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14172 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14173 | |
09b8f35a | 14174 | my_getExpression (ep, crux); |
5e0116d5 | 14175 | str = expr_end; |
394f9b3a | 14176 | |
5e0116d5 | 14177 | /* Match every open bracket. */ |
09b8f35a | 14178 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14179 | if (*str++ == ')') |
09b8f35a | 14180 | crux_depth--; |
394f9b3a | 14181 | |
09b8f35a | 14182 | if (crux_depth > 0) |
20203fb9 | 14183 | as_bad (_("unclosed '('")); |
394f9b3a | 14184 | |
5e0116d5 | 14185 | expr_end = str; |
252b5132 | 14186 | |
01a3f561 | 14187 | if (reloc_index != 0) |
64bdfcaf RS |
14188 | { |
14189 | prev_reloc_op_frag = frag_now; | |
14190 | for (i = 0; i < reloc_index; i++) | |
14191 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14192 | } | |
fb1b3232 | 14193 | |
5e0116d5 | 14194 | return reloc_index; |
252b5132 RH |
14195 | } |
14196 | ||
14197 | static void | |
17a2f251 | 14198 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14199 | { |
14200 | char *save_in; | |
14201 | ||
14202 | save_in = input_line_pointer; | |
14203 | input_line_pointer = str; | |
14204 | expression (ep); | |
14205 | expr_end = input_line_pointer; | |
14206 | input_line_pointer = save_in; | |
252b5132 RH |
14207 | } |
14208 | ||
252b5132 | 14209 | char * |
17a2f251 | 14210 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14211 | { |
499ac353 | 14212 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14213 | } |
14214 | ||
14215 | void | |
17a2f251 | 14216 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14217 | { |
14218 | if (target_big_endian) | |
14219 | number_to_chars_bigendian (buf, val, n); | |
14220 | else | |
14221 | number_to_chars_littleendian (buf, val, n); | |
14222 | } | |
14223 | \f | |
ae948b86 | 14224 | #ifdef OBJ_ELF |
e013f690 TS |
14225 | static int support_64bit_objects(void) |
14226 | { | |
14227 | const char **list, **l; | |
aa3d8fdf | 14228 | int yes; |
e013f690 TS |
14229 | |
14230 | list = bfd_target_list (); | |
14231 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14232 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14233 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14234 | break; |
aa3d8fdf | 14235 | yes = (*l != NULL); |
e013f690 | 14236 | free (list); |
aa3d8fdf | 14237 | return yes; |
e013f690 | 14238 | } |
ae948b86 | 14239 | #endif /* OBJ_ELF */ |
e013f690 | 14240 | |
78849248 | 14241 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14242 | |
23fce1e3 NC |
14243 | enum options |
14244 | { | |
14245 | OPTION_MARCH = OPTION_MD_BASE, | |
14246 | OPTION_MTUNE, | |
14247 | OPTION_MIPS1, | |
14248 | OPTION_MIPS2, | |
14249 | OPTION_MIPS3, | |
14250 | OPTION_MIPS4, | |
14251 | OPTION_MIPS5, | |
14252 | OPTION_MIPS32, | |
14253 | OPTION_MIPS64, | |
14254 | OPTION_MIPS32R2, | |
14255 | OPTION_MIPS64R2, | |
14256 | OPTION_MIPS16, | |
14257 | OPTION_NO_MIPS16, | |
14258 | OPTION_MIPS3D, | |
14259 | OPTION_NO_MIPS3D, | |
14260 | OPTION_MDMX, | |
14261 | OPTION_NO_MDMX, | |
14262 | OPTION_DSP, | |
14263 | OPTION_NO_DSP, | |
14264 | OPTION_MT, | |
14265 | OPTION_NO_MT, | |
14266 | OPTION_SMARTMIPS, | |
14267 | OPTION_NO_SMARTMIPS, | |
14268 | OPTION_DSPR2, | |
14269 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14270 | OPTION_MICROMIPS, |
14271 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14272 | OPTION_MCU, |
14273 | OPTION_NO_MCU, | |
23fce1e3 NC |
14274 | OPTION_COMPAT_ARCH_BASE, |
14275 | OPTION_M4650, | |
14276 | OPTION_NO_M4650, | |
14277 | OPTION_M4010, | |
14278 | OPTION_NO_M4010, | |
14279 | OPTION_M4100, | |
14280 | OPTION_NO_M4100, | |
14281 | OPTION_M3900, | |
14282 | OPTION_NO_M3900, | |
14283 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14284 | OPTION_MNO_7000_HILO_FIX, |
14285 | OPTION_FIX_24K, | |
14286 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14287 | OPTION_FIX_LOONGSON2F_JUMP, |
14288 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14289 | OPTION_FIX_LOONGSON2F_NOP, | |
14290 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14291 | OPTION_FIX_VR4120, |
14292 | OPTION_NO_FIX_VR4120, | |
14293 | OPTION_FIX_VR4130, | |
14294 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14295 | OPTION_FIX_CN63XXP1, |
14296 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14297 | OPTION_TRAP, |
14298 | OPTION_BREAK, | |
14299 | OPTION_EB, | |
14300 | OPTION_EL, | |
14301 | OPTION_FP32, | |
14302 | OPTION_GP32, | |
14303 | OPTION_CONSTRUCT_FLOATS, | |
14304 | OPTION_NO_CONSTRUCT_FLOATS, | |
14305 | OPTION_FP64, | |
14306 | OPTION_GP64, | |
14307 | OPTION_RELAX_BRANCH, | |
14308 | OPTION_NO_RELAX_BRANCH, | |
14309 | OPTION_MSHARED, | |
14310 | OPTION_MNO_SHARED, | |
14311 | OPTION_MSYM32, | |
14312 | OPTION_MNO_SYM32, | |
14313 | OPTION_SOFT_FLOAT, | |
14314 | OPTION_HARD_FLOAT, | |
14315 | OPTION_SINGLE_FLOAT, | |
14316 | OPTION_DOUBLE_FLOAT, | |
14317 | OPTION_32, | |
14318 | #ifdef OBJ_ELF | |
14319 | OPTION_CALL_SHARED, | |
14320 | OPTION_CALL_NONPIC, | |
14321 | OPTION_NON_SHARED, | |
14322 | OPTION_XGOT, | |
14323 | OPTION_MABI, | |
14324 | OPTION_N32, | |
14325 | OPTION_64, | |
14326 | OPTION_MDEBUG, | |
14327 | OPTION_NO_MDEBUG, | |
14328 | OPTION_PDR, | |
14329 | OPTION_NO_PDR, | |
14330 | OPTION_MVXWORKS_PIC, | |
14331 | #endif /* OBJ_ELF */ | |
14332 | OPTION_END_OF_ENUM | |
14333 | }; | |
14334 | ||
e972090a NC |
14335 | struct option md_longopts[] = |
14336 | { | |
f9b4148d | 14337 | /* Options which specify architecture. */ |
f9b4148d | 14338 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14339 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14340 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14341 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14342 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14343 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14344 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14345 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14346 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14347 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14348 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14349 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14350 | |
14351 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14352 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14353 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14354 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14355 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14356 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14357 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14358 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14359 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14360 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14361 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14362 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14363 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14364 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14365 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14366 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14367 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14368 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14369 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
f9b4148d CD |
14370 | |
14371 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14372 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14373 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14374 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14375 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14376 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14377 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14378 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14379 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14380 | ||
14381 | /* Options which enable bug fixes. */ | |
f9b4148d | 14382 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14383 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14384 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14385 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14386 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14387 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14388 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14389 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14390 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14391 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14392 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14393 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14394 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14395 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14396 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14397 | |
14398 | /* Miscellaneous options. */ | |
252b5132 RH |
14399 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14400 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14401 | {"break", no_argument, NULL, OPTION_BREAK}, |
14402 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14403 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14404 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14405 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14406 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14407 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14408 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14409 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14410 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14411 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14412 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14413 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14414 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14415 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14416 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14417 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14418 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14419 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14420 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14421 | |
14422 | /* Strictly speaking this next option is ELF specific, | |
14423 | but we allow it for other ports as well in order to | |
14424 | make testing easier. */ | |
14425 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14426 | |
f9b4148d | 14427 | /* ELF-specific options. */ |
156c2f8b | 14428 | #ifdef OBJ_ELF |
156c2f8b NC |
14429 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14430 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14431 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14432 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14433 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14434 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14435 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14436 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14437 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14438 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14439 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14440 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14441 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14442 | #endif /* OBJ_ELF */ |
f9b4148d | 14443 | |
252b5132 RH |
14444 | {NULL, no_argument, NULL, 0} |
14445 | }; | |
156c2f8b | 14446 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14447 | |
316f5878 RS |
14448 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14449 | NEW_VALUE. Warn if another value was already specified. Note: | |
14450 | we have to defer parsing the -march and -mtune arguments in order | |
14451 | to handle 'from-abi' correctly, since the ABI might be specified | |
14452 | in a later argument. */ | |
14453 | ||
14454 | static void | |
17a2f251 | 14455 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14456 | { |
14457 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14458 | as_warn (_("A different %s was already specified, is now %s"), | |
14459 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14460 | new_value); | |
14461 | ||
14462 | *string_ptr = new_value; | |
14463 | } | |
14464 | ||
252b5132 | 14465 | int |
17a2f251 | 14466 | md_parse_option (int c, char *arg) |
252b5132 RH |
14467 | { |
14468 | switch (c) | |
14469 | { | |
119d663a NC |
14470 | case OPTION_CONSTRUCT_FLOATS: |
14471 | mips_disable_float_construction = 0; | |
14472 | break; | |
bdaaa2e1 | 14473 | |
119d663a NC |
14474 | case OPTION_NO_CONSTRUCT_FLOATS: |
14475 | mips_disable_float_construction = 1; | |
14476 | break; | |
bdaaa2e1 | 14477 | |
252b5132 RH |
14478 | case OPTION_TRAP: |
14479 | mips_trap = 1; | |
14480 | break; | |
14481 | ||
14482 | case OPTION_BREAK: | |
14483 | mips_trap = 0; | |
14484 | break; | |
14485 | ||
14486 | case OPTION_EB: | |
14487 | target_big_endian = 1; | |
14488 | break; | |
14489 | ||
14490 | case OPTION_EL: | |
14491 | target_big_endian = 0; | |
14492 | break; | |
14493 | ||
14494 | case 'O': | |
4ffff32f TS |
14495 | if (arg == NULL) |
14496 | mips_optimize = 1; | |
14497 | else if (arg[0] == '0') | |
14498 | mips_optimize = 0; | |
14499 | else if (arg[0] == '1') | |
252b5132 RH |
14500 | mips_optimize = 1; |
14501 | else | |
14502 | mips_optimize = 2; | |
14503 | break; | |
14504 | ||
14505 | case 'g': | |
14506 | if (arg == NULL) | |
14507 | mips_debug = 2; | |
14508 | else | |
14509 | mips_debug = atoi (arg); | |
252b5132 RH |
14510 | break; |
14511 | ||
14512 | case OPTION_MIPS1: | |
316f5878 | 14513 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14514 | break; |
14515 | ||
14516 | case OPTION_MIPS2: | |
316f5878 | 14517 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14518 | break; |
14519 | ||
14520 | case OPTION_MIPS3: | |
316f5878 | 14521 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14522 | break; |
14523 | ||
14524 | case OPTION_MIPS4: | |
316f5878 | 14525 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14526 | break; |
14527 | ||
84ea6cf2 | 14528 | case OPTION_MIPS5: |
316f5878 | 14529 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14530 | break; |
14531 | ||
e7af610e | 14532 | case OPTION_MIPS32: |
316f5878 | 14533 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14534 | break; |
14535 | ||
af7ee8bf CD |
14536 | case OPTION_MIPS32R2: |
14537 | file_mips_isa = ISA_MIPS32R2; | |
14538 | break; | |
14539 | ||
5f74bc13 CD |
14540 | case OPTION_MIPS64R2: |
14541 | file_mips_isa = ISA_MIPS64R2; | |
14542 | break; | |
14543 | ||
84ea6cf2 | 14544 | case OPTION_MIPS64: |
316f5878 | 14545 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14546 | break; |
14547 | ||
ec68c924 | 14548 | case OPTION_MTUNE: |
316f5878 RS |
14549 | mips_set_option_string (&mips_tune_string, arg); |
14550 | break; | |
ec68c924 | 14551 | |
316f5878 RS |
14552 | case OPTION_MARCH: |
14553 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14554 | break; |
14555 | ||
14556 | case OPTION_M4650: | |
316f5878 RS |
14557 | mips_set_option_string (&mips_arch_string, "4650"); |
14558 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14559 | break; |
14560 | ||
14561 | case OPTION_NO_M4650: | |
14562 | break; | |
14563 | ||
14564 | case OPTION_M4010: | |
316f5878 RS |
14565 | mips_set_option_string (&mips_arch_string, "4010"); |
14566 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14567 | break; |
14568 | ||
14569 | case OPTION_NO_M4010: | |
14570 | break; | |
14571 | ||
14572 | case OPTION_M4100: | |
316f5878 RS |
14573 | mips_set_option_string (&mips_arch_string, "4100"); |
14574 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14575 | break; |
14576 | ||
14577 | case OPTION_NO_M4100: | |
14578 | break; | |
14579 | ||
252b5132 | 14580 | case OPTION_M3900: |
316f5878 RS |
14581 | mips_set_option_string (&mips_arch_string, "3900"); |
14582 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14583 | break; |
bdaaa2e1 | 14584 | |
252b5132 RH |
14585 | case OPTION_NO_M3900: |
14586 | break; | |
14587 | ||
deec1734 CD |
14588 | case OPTION_MDMX: |
14589 | mips_opts.ase_mdmx = 1; | |
14590 | break; | |
14591 | ||
14592 | case OPTION_NO_MDMX: | |
14593 | mips_opts.ase_mdmx = 0; | |
14594 | break; | |
14595 | ||
74cd071d CF |
14596 | case OPTION_DSP: |
14597 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14598 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14599 | break; |
14600 | ||
14601 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14602 | mips_opts.ase_dsp = 0; |
14603 | mips_opts.ase_dspr2 = 0; | |
14604 | break; | |
14605 | ||
14606 | case OPTION_DSPR2: | |
14607 | mips_opts.ase_dspr2 = 1; | |
14608 | mips_opts.ase_dsp = 1; | |
14609 | break; | |
14610 | ||
14611 | case OPTION_NO_DSPR2: | |
14612 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14613 | mips_opts.ase_dsp = 0; |
14614 | break; | |
14615 | ||
ef2e4d86 CF |
14616 | case OPTION_MT: |
14617 | mips_opts.ase_mt = 1; | |
14618 | break; | |
14619 | ||
14620 | case OPTION_NO_MT: | |
14621 | mips_opts.ase_mt = 0; | |
14622 | break; | |
14623 | ||
dec0624d MR |
14624 | case OPTION_MCU: |
14625 | mips_opts.ase_mcu = 1; | |
14626 | break; | |
14627 | ||
14628 | case OPTION_NO_MCU: | |
14629 | mips_opts.ase_mcu = 0; | |
14630 | break; | |
14631 | ||
df58fc94 RS |
14632 | case OPTION_MICROMIPS: |
14633 | if (mips_opts.mips16 == 1) | |
14634 | { | |
14635 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14636 | return 0; | |
14637 | } | |
14638 | mips_opts.micromips = 1; | |
14639 | mips_no_prev_insn (); | |
14640 | break; | |
14641 | ||
14642 | case OPTION_NO_MICROMIPS: | |
14643 | mips_opts.micromips = 0; | |
14644 | mips_no_prev_insn (); | |
14645 | break; | |
14646 | ||
252b5132 | 14647 | case OPTION_MIPS16: |
df58fc94 RS |
14648 | if (mips_opts.micromips == 1) |
14649 | { | |
14650 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14651 | return 0; | |
14652 | } | |
252b5132 | 14653 | mips_opts.mips16 = 1; |
7d10b47d | 14654 | mips_no_prev_insn (); |
252b5132 RH |
14655 | break; |
14656 | ||
14657 | case OPTION_NO_MIPS16: | |
14658 | mips_opts.mips16 = 0; | |
7d10b47d | 14659 | mips_no_prev_insn (); |
252b5132 RH |
14660 | break; |
14661 | ||
1f25f5d3 CD |
14662 | case OPTION_MIPS3D: |
14663 | mips_opts.ase_mips3d = 1; | |
14664 | break; | |
14665 | ||
14666 | case OPTION_NO_MIPS3D: | |
14667 | mips_opts.ase_mips3d = 0; | |
14668 | break; | |
14669 | ||
e16bfa71 TS |
14670 | case OPTION_SMARTMIPS: |
14671 | mips_opts.ase_smartmips = 1; | |
14672 | break; | |
14673 | ||
14674 | case OPTION_NO_SMARTMIPS: | |
14675 | mips_opts.ase_smartmips = 0; | |
14676 | break; | |
14677 | ||
6a32d874 CM |
14678 | case OPTION_FIX_24K: |
14679 | mips_fix_24k = 1; | |
14680 | break; | |
14681 | ||
14682 | case OPTION_NO_FIX_24K: | |
14683 | mips_fix_24k = 0; | |
14684 | break; | |
14685 | ||
c67a084a NC |
14686 | case OPTION_FIX_LOONGSON2F_JUMP: |
14687 | mips_fix_loongson2f_jump = TRUE; | |
14688 | break; | |
14689 | ||
14690 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14691 | mips_fix_loongson2f_jump = FALSE; | |
14692 | break; | |
14693 | ||
14694 | case OPTION_FIX_LOONGSON2F_NOP: | |
14695 | mips_fix_loongson2f_nop = TRUE; | |
14696 | break; | |
14697 | ||
14698 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14699 | mips_fix_loongson2f_nop = FALSE; | |
14700 | break; | |
14701 | ||
d766e8ec RS |
14702 | case OPTION_FIX_VR4120: |
14703 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14704 | break; |
14705 | ||
d766e8ec RS |
14706 | case OPTION_NO_FIX_VR4120: |
14707 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14708 | break; |
14709 | ||
7d8e00cf RS |
14710 | case OPTION_FIX_VR4130: |
14711 | mips_fix_vr4130 = 1; | |
14712 | break; | |
14713 | ||
14714 | case OPTION_NO_FIX_VR4130: | |
14715 | mips_fix_vr4130 = 0; | |
14716 | break; | |
14717 | ||
d954098f DD |
14718 | case OPTION_FIX_CN63XXP1: |
14719 | mips_fix_cn63xxp1 = TRUE; | |
14720 | break; | |
14721 | ||
14722 | case OPTION_NO_FIX_CN63XXP1: | |
14723 | mips_fix_cn63xxp1 = FALSE; | |
14724 | break; | |
14725 | ||
4a6a3df4 AO |
14726 | case OPTION_RELAX_BRANCH: |
14727 | mips_relax_branch = 1; | |
14728 | break; | |
14729 | ||
14730 | case OPTION_NO_RELAX_BRANCH: | |
14731 | mips_relax_branch = 0; | |
14732 | break; | |
14733 | ||
aa6975fb ILT |
14734 | case OPTION_MSHARED: |
14735 | mips_in_shared = TRUE; | |
14736 | break; | |
14737 | ||
14738 | case OPTION_MNO_SHARED: | |
14739 | mips_in_shared = FALSE; | |
14740 | break; | |
14741 | ||
aed1a261 RS |
14742 | case OPTION_MSYM32: |
14743 | mips_opts.sym32 = TRUE; | |
14744 | break; | |
14745 | ||
14746 | case OPTION_MNO_SYM32: | |
14747 | mips_opts.sym32 = FALSE; | |
14748 | break; | |
14749 | ||
0f074f60 | 14750 | #ifdef OBJ_ELF |
252b5132 RH |
14751 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14752 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14753 | intended to be compatible with Irix 5. */ | |
14754 | case OPTION_CALL_SHARED: | |
f43abd2b | 14755 | if (!IS_ELF) |
252b5132 RH |
14756 | { |
14757 | as_bad (_("-call_shared is supported only for ELF format")); | |
14758 | return 0; | |
14759 | } | |
14760 | mips_pic = SVR4_PIC; | |
143d77c5 | 14761 | mips_abicalls = TRUE; |
252b5132 RH |
14762 | break; |
14763 | ||
861fb55a DJ |
14764 | case OPTION_CALL_NONPIC: |
14765 | if (!IS_ELF) | |
14766 | { | |
14767 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14768 | return 0; | |
14769 | } | |
14770 | mips_pic = NO_PIC; | |
14771 | mips_abicalls = TRUE; | |
14772 | break; | |
14773 | ||
252b5132 | 14774 | case OPTION_NON_SHARED: |
f43abd2b | 14775 | if (!IS_ELF) |
252b5132 RH |
14776 | { |
14777 | as_bad (_("-non_shared is supported only for ELF format")); | |
14778 | return 0; | |
14779 | } | |
14780 | mips_pic = NO_PIC; | |
143d77c5 | 14781 | mips_abicalls = FALSE; |
252b5132 RH |
14782 | break; |
14783 | ||
44075ae2 TS |
14784 | /* The -xgot option tells the assembler to use 32 bit offsets |
14785 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14786 | compatibility. */ |
14787 | case OPTION_XGOT: | |
14788 | mips_big_got = 1; | |
14789 | break; | |
0f074f60 | 14790 | #endif /* OBJ_ELF */ |
252b5132 RH |
14791 | |
14792 | case 'G': | |
6caf9ef4 TS |
14793 | g_switch_value = atoi (arg); |
14794 | g_switch_seen = 1; | |
252b5132 RH |
14795 | break; |
14796 | ||
34ba82a8 TS |
14797 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14798 | and -mabi=64. */ | |
252b5132 | 14799 | case OPTION_32: |
23fce1e3 NC |
14800 | if (IS_ELF) |
14801 | mips_abi = O32_ABI; | |
14802 | /* We silently ignore -32 for non-ELF targets. This greatly | |
14803 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
14804 | break; |
14805 | ||
23fce1e3 | 14806 | #ifdef OBJ_ELF |
e013f690 | 14807 | case OPTION_N32: |
f43abd2b | 14808 | if (!IS_ELF) |
34ba82a8 TS |
14809 | { |
14810 | as_bad (_("-n32 is supported for ELF format only")); | |
14811 | return 0; | |
14812 | } | |
316f5878 | 14813 | mips_abi = N32_ABI; |
e013f690 | 14814 | break; |
252b5132 | 14815 | |
e013f690 | 14816 | case OPTION_64: |
f43abd2b | 14817 | if (!IS_ELF) |
34ba82a8 TS |
14818 | { |
14819 | as_bad (_("-64 is supported for ELF format only")); | |
14820 | return 0; | |
14821 | } | |
316f5878 | 14822 | mips_abi = N64_ABI; |
f43abd2b | 14823 | if (!support_64bit_objects()) |
e013f690 | 14824 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 14825 | break; |
ae948b86 | 14826 | #endif /* OBJ_ELF */ |
252b5132 | 14827 | |
c97ef257 | 14828 | case OPTION_GP32: |
a325df1d | 14829 | file_mips_gp32 = 1; |
c97ef257 AH |
14830 | break; |
14831 | ||
14832 | case OPTION_GP64: | |
a325df1d | 14833 | file_mips_gp32 = 0; |
c97ef257 | 14834 | break; |
252b5132 | 14835 | |
ca4e0257 | 14836 | case OPTION_FP32: |
a325df1d | 14837 | file_mips_fp32 = 1; |
316f5878 RS |
14838 | break; |
14839 | ||
14840 | case OPTION_FP64: | |
14841 | file_mips_fp32 = 0; | |
ca4e0257 RS |
14842 | break; |
14843 | ||
037b32b9 AN |
14844 | case OPTION_SINGLE_FLOAT: |
14845 | file_mips_single_float = 1; | |
14846 | break; | |
14847 | ||
14848 | case OPTION_DOUBLE_FLOAT: | |
14849 | file_mips_single_float = 0; | |
14850 | break; | |
14851 | ||
14852 | case OPTION_SOFT_FLOAT: | |
14853 | file_mips_soft_float = 1; | |
14854 | break; | |
14855 | ||
14856 | case OPTION_HARD_FLOAT: | |
14857 | file_mips_soft_float = 0; | |
14858 | break; | |
14859 | ||
ae948b86 | 14860 | #ifdef OBJ_ELF |
252b5132 | 14861 | case OPTION_MABI: |
f43abd2b | 14862 | if (!IS_ELF) |
34ba82a8 TS |
14863 | { |
14864 | as_bad (_("-mabi is supported for ELF format only")); | |
14865 | return 0; | |
14866 | } | |
e013f690 | 14867 | if (strcmp (arg, "32") == 0) |
316f5878 | 14868 | mips_abi = O32_ABI; |
e013f690 | 14869 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14870 | mips_abi = O64_ABI; |
e013f690 | 14871 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14872 | mips_abi = N32_ABI; |
e013f690 TS |
14873 | else if (strcmp (arg, "64") == 0) |
14874 | { | |
316f5878 | 14875 | mips_abi = N64_ABI; |
e013f690 TS |
14876 | if (! support_64bit_objects()) |
14877 | as_fatal (_("No compiled in support for 64 bit object file " | |
14878 | "format")); | |
14879 | } | |
14880 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14881 | mips_abi = EABI_ABI; |
e013f690 | 14882 | else |
da0e507f TS |
14883 | { |
14884 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14885 | return 0; | |
14886 | } | |
252b5132 | 14887 | break; |
e013f690 | 14888 | #endif /* OBJ_ELF */ |
252b5132 | 14889 | |
6b76fefe | 14890 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14891 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14892 | break; |
14893 | ||
9ee72ff1 | 14894 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14895 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14896 | break; |
14897 | ||
ecb4347a DJ |
14898 | #ifdef OBJ_ELF |
14899 | case OPTION_MDEBUG: | |
b34976b6 | 14900 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14901 | break; |
14902 | ||
14903 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14904 | mips_flag_mdebug = FALSE; |
ecb4347a | 14905 | break; |
dcd410fe RO |
14906 | |
14907 | case OPTION_PDR: | |
14908 | mips_flag_pdr = TRUE; | |
14909 | break; | |
14910 | ||
14911 | case OPTION_NO_PDR: | |
14912 | mips_flag_pdr = FALSE; | |
14913 | break; | |
0a44bf69 RS |
14914 | |
14915 | case OPTION_MVXWORKS_PIC: | |
14916 | mips_pic = VXWORKS_PIC; | |
14917 | break; | |
ecb4347a DJ |
14918 | #endif /* OBJ_ELF */ |
14919 | ||
252b5132 RH |
14920 | default: |
14921 | return 0; | |
14922 | } | |
14923 | ||
c67a084a NC |
14924 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14925 | ||
252b5132 RH |
14926 | return 1; |
14927 | } | |
316f5878 RS |
14928 | \f |
14929 | /* Set up globals to generate code for the ISA or processor | |
14930 | described by INFO. */ | |
252b5132 | 14931 | |
252b5132 | 14932 | static void |
17a2f251 | 14933 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 14934 | { |
316f5878 | 14935 | if (info != 0) |
252b5132 | 14936 | { |
fef14a42 TS |
14937 | file_mips_arch = info->cpu; |
14938 | mips_opts.arch = info->cpu; | |
316f5878 | 14939 | mips_opts.isa = info->isa; |
252b5132 | 14940 | } |
252b5132 RH |
14941 | } |
14942 | ||
252b5132 | 14943 | |
316f5878 | 14944 | /* Likewise for tuning. */ |
252b5132 | 14945 | |
316f5878 | 14946 | static void |
17a2f251 | 14947 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14948 | { |
14949 | if (info != 0) | |
fef14a42 | 14950 | mips_tune = info->cpu; |
316f5878 | 14951 | } |
80cc45a5 | 14952 | |
34ba82a8 | 14953 | |
252b5132 | 14954 | void |
17a2f251 | 14955 | mips_after_parse_args (void) |
e9670677 | 14956 | { |
fef14a42 TS |
14957 | const struct mips_cpu_info *arch_info = 0; |
14958 | const struct mips_cpu_info *tune_info = 0; | |
14959 | ||
e9670677 | 14960 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14961 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14962 | { |
6caf9ef4 | 14963 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
14964 | as_bad (_("-G not supported in this configuration.")); |
14965 | g_switch_value = 0; | |
14966 | } | |
14967 | ||
cac012d6 AO |
14968 | if (mips_abi == NO_ABI) |
14969 | mips_abi = MIPS_DEFAULT_ABI; | |
14970 | ||
22923709 RS |
14971 | /* The following code determines the architecture and register size. |
14972 | Similar code was added to GCC 3.3 (see override_options() in | |
14973 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14974 | as much as possible. */ | |
e9670677 | 14975 | |
316f5878 | 14976 | if (mips_arch_string != 0) |
fef14a42 | 14977 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14978 | |
316f5878 | 14979 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 14980 | { |
316f5878 | 14981 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 14982 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14983 | the -march selection (if any). */ |
fef14a42 | 14984 | if (arch_info != 0) |
e9670677 | 14985 | { |
316f5878 RS |
14986 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14987 | There's no harm in specifying both as long as the ISA levels | |
14988 | are the same. */ | |
fef14a42 | 14989 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
14990 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
14991 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 14992 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14993 | } |
316f5878 | 14994 | else |
fef14a42 | 14995 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
14996 | } |
14997 | ||
fef14a42 TS |
14998 | if (arch_info == 0) |
14999 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 15000 | |
fef14a42 | 15001 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15002 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15003 | arch_info->name); |
15004 | ||
15005 | mips_set_architecture (arch_info); | |
15006 | ||
15007 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15008 | if (mips_tune_string != 0) | |
15009 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15010 | |
fef14a42 TS |
15011 | if (tune_info == 0) |
15012 | mips_set_tune (arch_info); | |
15013 | else | |
15014 | mips_set_tune (tune_info); | |
e9670677 | 15015 | |
316f5878 | 15016 | if (file_mips_gp32 >= 0) |
e9670677 | 15017 | { |
316f5878 RS |
15018 | /* The user specified the size of the integer registers. Make sure |
15019 | it agrees with the ABI and ISA. */ | |
15020 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15021 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15022 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15023 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15024 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15025 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15026 | } |
15027 | else | |
15028 | { | |
316f5878 RS |
15029 | /* Infer the integer register size from the ABI and processor. |
15030 | Restrict ourselves to 32-bit registers if that's all the | |
15031 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15032 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15033 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15034 | } |
15035 | ||
ad3fea08 TS |
15036 | switch (file_mips_fp32) |
15037 | { | |
15038 | default: | |
15039 | case -1: | |
15040 | /* No user specified float register size. | |
15041 | ??? GAS treats single-float processors as though they had 64-bit | |
15042 | float registers (although it complains when double-precision | |
15043 | instructions are used). As things stand, saying they have 32-bit | |
15044 | registers would lead to spurious "register must be even" messages. | |
15045 | So here we assume float registers are never smaller than the | |
15046 | integer ones. */ | |
15047 | if (file_mips_gp32 == 0) | |
15048 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15049 | file_mips_fp32 = 0; | |
15050 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15051 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15052 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15053 | file_mips_fp32 = 0; | |
15054 | else | |
15055 | /* 32-bit float registers. */ | |
15056 | file_mips_fp32 = 1; | |
15057 | break; | |
15058 | ||
15059 | /* The user specified the size of the float registers. Check if it | |
15060 | agrees with the ABI and ISA. */ | |
15061 | case 0: | |
15062 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15063 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15064 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15065 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15066 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15067 | break; | |
15068 | case 1: | |
15069 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15070 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15071 | break; | |
15072 | } | |
e9670677 | 15073 | |
316f5878 | 15074 | /* End of GCC-shared inference code. */ |
e9670677 | 15075 | |
17a2f251 TS |
15076 | /* This flag is set when we have a 64-bit capable CPU but use only |
15077 | 32-bit wide registers. Note that EABI does not use it. */ | |
15078 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15079 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15080 | || mips_abi == O32_ABI)) | |
316f5878 | 15081 | mips_32bitmode = 1; |
e9670677 MR |
15082 | |
15083 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15084 | as_bad (_("trap exception not supported at ISA 1")); | |
15085 | ||
e9670677 MR |
15086 | /* If the selected architecture includes support for ASEs, enable |
15087 | generation of code for them. */ | |
a4672219 | 15088 | if (mips_opts.mips16 == -1) |
fef14a42 | 15089 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15090 | if (mips_opts.micromips == -1) |
15091 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15092 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15093 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15094 | && file_mips_fp32 == 0) ? 1 : 0; |
15095 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15096 | as_bad (_("-mfp32 used with -mips3d")); | |
15097 | ||
ffdefa66 | 15098 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15099 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15100 | && file_mips_fp32 == 0) ? 1 : 0; |
15101 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15102 | as_bad (_("-mfp32 used with -mdmx")); | |
15103 | ||
15104 | if (mips_opts.ase_smartmips == -1) | |
15105 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15106 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15107 | as_warn (_("%s ISA does not support SmartMIPS"), |
15108 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15109 | |
74cd071d | 15110 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15111 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15112 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15113 | as_warn (_("%s ISA does not support DSP ASE"), |
15114 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15115 | |
8b082fb1 TS |
15116 | if (mips_opts.ase_dspr2 == -1) |
15117 | { | |
15118 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15119 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15120 | } | |
15121 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15122 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15123 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15124 | |
ef2e4d86 | 15125 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15126 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15127 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15128 | as_warn (_("%s ISA does not support MT ASE"), |
15129 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15130 | |
dec0624d MR |
15131 | if (mips_opts.ase_mcu == -1) |
15132 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15133 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15134 | as_warn (_("%s ISA does not support MCU ASE"), | |
15135 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15136 | ||
e9670677 | 15137 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15138 | file_ase_mips3d = mips_opts.ase_mips3d; |
15139 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15140 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15141 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15142 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15143 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15144 | mips_opts.gp32 = file_mips_gp32; |
15145 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15146 | mips_opts.soft_float = file_mips_soft_float; |
15147 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15148 | |
ecb4347a DJ |
15149 | if (mips_flag_mdebug < 0) |
15150 | { | |
15151 | #ifdef OBJ_MAYBE_ECOFF | |
15152 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15153 | mips_flag_mdebug = 1; | |
15154 | else | |
15155 | #endif /* OBJ_MAYBE_ECOFF */ | |
15156 | mips_flag_mdebug = 0; | |
15157 | } | |
e9670677 MR |
15158 | } |
15159 | \f | |
15160 | void | |
17a2f251 | 15161 | mips_init_after_args (void) |
252b5132 RH |
15162 | { |
15163 | /* initialize opcodes */ | |
15164 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15165 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15166 | } |
15167 | ||
15168 | long | |
17a2f251 | 15169 | md_pcrel_from (fixS *fixP) |
252b5132 | 15170 | { |
a7ebbfdf TS |
15171 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15172 | switch (fixP->fx_r_type) | |
15173 | { | |
df58fc94 RS |
15174 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15175 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15176 | /* Return the address of the delay slot. */ | |
15177 | return addr + 2; | |
15178 | ||
15179 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15180 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15181 | case BFD_RELOC_16_PCREL_S2: |
15182 | case BFD_RELOC_MIPS_JMP: | |
15183 | /* Return the address of the delay slot. */ | |
15184 | return addr + 4; | |
df58fc94 | 15185 | |
a7ebbfdf | 15186 | default: |
58ea3d6a | 15187 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15188 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15189 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15190 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15191 | return addr; |
15192 | } | |
252b5132 RH |
15193 | } |
15194 | ||
252b5132 RH |
15195 | /* This is called before the symbol table is processed. In order to |
15196 | work with gcc when using mips-tfile, we must keep all local labels. | |
15197 | However, in other cases, we want to discard them. If we were | |
15198 | called with -g, but we didn't see any debugging information, it may | |
15199 | mean that gcc is smuggling debugging information through to | |
15200 | mips-tfile, in which case we must generate all local labels. */ | |
15201 | ||
15202 | void | |
17a2f251 | 15203 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15204 | { |
15205 | #ifndef NO_ECOFF_DEBUGGING | |
15206 | if (ECOFF_DEBUGGING | |
15207 | && mips_debug != 0 | |
15208 | && ! ecoff_debugging_seen) | |
15209 | flag_keep_locals = 1; | |
15210 | #endif | |
15211 | } | |
15212 | ||
3b91255e | 15213 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15214 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15215 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15216 | relocation operators. | |
15217 | ||
15218 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15219 | expression if: | |
15220 | ||
15221 | (a) it refers to the same symbol; and | |
15222 | (b) the offset applied in the %lo() expression is no lower than | |
15223 | the offset applied in the %got() or %hi(). | |
15224 | ||
15225 | (b) allows us to cope with code like: | |
15226 | ||
15227 | lui $4,%hi(foo) | |
15228 | lh $4,%lo(foo+2)($4) | |
15229 | ||
15230 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15231 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15232 | the high 16 bits. | |
15233 | ||
15234 | When several %lo()s match a particular %got() or %hi(), we use the | |
15235 | following rules to distinguish them: | |
15236 | ||
15237 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15238 | higher offsets. | |
15239 | ||
15240 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15241 | that already have a matching %got() or %hi(). | |
15242 | ||
15243 | (3) later %lo()s are better than earlier %lo()s. | |
15244 | ||
15245 | These rules are applied in order. | |
15246 | ||
15247 | (1) means, among other things, that %lo()s with identical offsets are | |
15248 | chosen if they exist. | |
15249 | ||
15250 | (2) means that we won't associate several high-part relocations with | |
15251 | the same low-part relocation unless there's no alternative. Having | |
15252 | several high parts for the same low part is a GNU extension; this rule | |
15253 | allows careful users to avoid it. | |
15254 | ||
15255 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15256 | with the last high-part relocation being at the front of the list. | |
15257 | It therefore makes sense to choose the last matching low-part | |
15258 | relocation, all other things being equal. It's also easier | |
15259 | to code that way. */ | |
252b5132 RH |
15260 | |
15261 | void | |
17a2f251 | 15262 | mips_frob_file (void) |
252b5132 RH |
15263 | { |
15264 | struct mips_hi_fixup *l; | |
35903be0 | 15265 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15266 | |
15267 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15268 | { | |
15269 | segment_info_type *seginfo; | |
3b91255e RS |
15270 | bfd_boolean matched_lo_p; |
15271 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15272 | |
9c2799c2 | 15273 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15274 | |
5919d012 RS |
15275 | /* If a GOT16 relocation turns out to be against a global symbol, |
15276 | there isn't supposed to be a matching LO. */ | |
738e5348 | 15277 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
15278 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
15279 | continue; | |
15280 | ||
15281 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15282 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15283 | continue; |
15284 | ||
252b5132 | 15285 | seginfo = seg_info (l->seg); |
252b5132 | 15286 | |
3b91255e RS |
15287 | /* Set HI_POS to the position of this relocation in the chain. |
15288 | Set LO_POS to the position of the chosen low-part relocation. | |
15289 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15290 | relocation that matches an immediately-preceding high-part | |
15291 | relocation. */ | |
15292 | hi_pos = NULL; | |
15293 | lo_pos = NULL; | |
15294 | matched_lo_p = FALSE; | |
738e5348 | 15295 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15296 | |
3b91255e RS |
15297 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15298 | { | |
15299 | if (*pos == l->fixp) | |
15300 | hi_pos = pos; | |
15301 | ||
35903be0 | 15302 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15303 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15304 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15305 | && (lo_pos == NULL | |
15306 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15307 | || (!matched_lo_p | |
15308 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15309 | lo_pos = pos; | |
15310 | ||
15311 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15312 | && fixup_has_matching_lo_p (*pos)); | |
15313 | } | |
15314 | ||
15315 | /* If we found a match, remove the high-part relocation from its | |
15316 | current position and insert it before the low-part relocation. | |
15317 | Make the offsets match so that fixup_has_matching_lo_p() | |
15318 | will return true. | |
15319 | ||
15320 | We don't warn about unmatched high-part relocations since some | |
15321 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15322 | instructions. */ | |
15323 | if (lo_pos != NULL) | |
15324 | { | |
15325 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15326 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15327 | { |
3b91255e RS |
15328 | *hi_pos = l->fixp->fx_next; |
15329 | l->fixp->fx_next = *lo_pos; | |
15330 | *lo_pos = l->fixp; | |
252b5132 | 15331 | } |
252b5132 RH |
15332 | } |
15333 | } | |
15334 | } | |
15335 | ||
3e722fb5 | 15336 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 15337 | We have to prevent gas from dropping them. */ |
252b5132 | 15338 | |
252b5132 | 15339 | int |
17a2f251 | 15340 | mips_force_relocation (fixS *fixp) |
252b5132 | 15341 | { |
ae6063d4 | 15342 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15343 | return 1; |
15344 | ||
df58fc94 RS |
15345 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15346 | so that the linker relaxation can update targets. */ | |
15347 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15348 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15349 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15350 | return 1; | |
15351 | ||
f6688943 TS |
15352 | if (HAVE_NEWABI |
15353 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
15354 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
15355 | || hi16_reloc_p (fixp->fx_r_type) |
15356 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
15357 | return 1; |
15358 | ||
3e722fb5 | 15359 | return 0; |
252b5132 RH |
15360 | } |
15361 | ||
15362 | /* Apply a fixup to the object file. */ | |
15363 | ||
94f592af | 15364 | void |
55cf6793 | 15365 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15366 | { |
874e8986 | 15367 | bfd_byte *buf; |
98aa84af | 15368 | long insn; |
a7ebbfdf | 15369 | reloc_howto_type *howto; |
252b5132 | 15370 | |
a7ebbfdf TS |
15371 | /* We ignore generic BFD relocations we don't know about. */ |
15372 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15373 | if (! howto) | |
15374 | return; | |
65551fa4 | 15375 | |
df58fc94 RS |
15376 | gas_assert (fixP->fx_size == 2 |
15377 | || fixP->fx_size == 4 | |
90ecf173 MR |
15378 | || fixP->fx_r_type == BFD_RELOC_16 |
15379 | || fixP->fx_r_type == BFD_RELOC_64 | |
15380 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15381 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15382 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15383 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15384 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15385 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15386 | |
a7ebbfdf | 15387 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 15388 | |
df58fc94 RS |
15389 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15390 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15391 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15392 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15393 | |
15394 | /* Don't treat parts of a composite relocation as done. There are two | |
15395 | reasons for this: | |
15396 | ||
15397 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15398 | should nevertheless be emitted if the first part is. | |
15399 | ||
15400 | (2) In normal usage, composite relocations are never assembly-time | |
15401 | constants. The easiest way of dealing with the pathological | |
15402 | exceptions is to generate a relocation against STN_UNDEF and | |
15403 | leave everything up to the linker. */ | |
3994f87e | 15404 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15405 | fixP->fx_done = 1; |
15406 | ||
15407 | switch (fixP->fx_r_type) | |
15408 | { | |
3f98094e DJ |
15409 | case BFD_RELOC_MIPS_TLS_GD: |
15410 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15411 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15412 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15413 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15414 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15415 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15416 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15417 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15418 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15419 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15420 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15421 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15422 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15423 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15424 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15425 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15426 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15427 | case BFD_RELOC_MIPS16_TLS_GD: |
15428 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15429 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15430 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15431 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15432 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15433 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
3f98094e DJ |
15434 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15435 | /* fall through */ | |
15436 | ||
252b5132 | 15437 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15438 | case BFD_RELOC_MIPS_SHIFT5: |
15439 | case BFD_RELOC_MIPS_SHIFT6: | |
15440 | case BFD_RELOC_MIPS_GOT_DISP: | |
15441 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15442 | case BFD_RELOC_MIPS_GOT_OFST: | |
15443 | case BFD_RELOC_MIPS_SUB: | |
15444 | case BFD_RELOC_MIPS_INSERT_A: | |
15445 | case BFD_RELOC_MIPS_INSERT_B: | |
15446 | case BFD_RELOC_MIPS_DELETE: | |
15447 | case BFD_RELOC_MIPS_HIGHEST: | |
15448 | case BFD_RELOC_MIPS_HIGHER: | |
15449 | case BFD_RELOC_MIPS_SCN_DISP: | |
15450 | case BFD_RELOC_MIPS_REL16: | |
15451 | case BFD_RELOC_MIPS_RELGOT: | |
15452 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15453 | case BFD_RELOC_HI16: |
15454 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 15455 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15456 | case BFD_RELOC_MIPS_LITERAL: |
15457 | case BFD_RELOC_MIPS_CALL16: | |
15458 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15459 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15460 | case BFD_RELOC_MIPS_GOT_HI16: |
15461 | case BFD_RELOC_MIPS_GOT_LO16: | |
15462 | case BFD_RELOC_MIPS_CALL_HI16: | |
15463 | case BFD_RELOC_MIPS_CALL_LO16: | |
15464 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15465 | case BFD_RELOC_MIPS16_GOT16: |
15466 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15467 | case BFD_RELOC_MIPS16_HI16: |
15468 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 15469 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15470 | case BFD_RELOC_MICROMIPS_JMP: |
15471 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15472 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15473 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15474 | case BFD_RELOC_MICROMIPS_SUB: | |
15475 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15476 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15477 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15478 | case BFD_RELOC_MICROMIPS_JALR: | |
15479 | case BFD_RELOC_MICROMIPS_HI16: | |
15480 | case BFD_RELOC_MICROMIPS_HI16_S: | |
15481 | case BFD_RELOC_MICROMIPS_GPREL16: | |
15482 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15483 | case BFD_RELOC_MICROMIPS_CALL16: | |
15484 | case BFD_RELOC_MICROMIPS_GOT16: | |
15485 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15486 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15487 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15488 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
54f4ddb3 | 15489 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
15490 | break; |
15491 | ||
252b5132 RH |
15492 | case BFD_RELOC_64: |
15493 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15494 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15495 | if (fixP->fx_done) |
252b5132 RH |
15496 | { |
15497 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 15498 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
15499 | else |
15500 | { | |
a7ebbfdf | 15501 | valueT hiv; |
252b5132 | 15502 | |
a7ebbfdf | 15503 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15504 | hiv = 0xffffffff; |
15505 | else | |
15506 | hiv = 0; | |
b215186b | 15507 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 15508 | *valP, 4); |
b215186b | 15509 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 15510 | hiv, 4); |
252b5132 RH |
15511 | } |
15512 | } | |
15513 | break; | |
15514 | ||
056350c6 | 15515 | case BFD_RELOC_RVA: |
252b5132 | 15516 | case BFD_RELOC_32: |
252b5132 RH |
15517 | case BFD_RELOC_16: |
15518 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15519 | value now. This can happen if we have a .word which is not |
15520 | resolved when it appears but is later defined. */ | |
252b5132 | 15521 | if (fixP->fx_done) |
54f4ddb3 | 15522 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
15523 | break; |
15524 | ||
15525 | case BFD_RELOC_LO16: | |
d6f16593 | 15526 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 | 15527 | case BFD_RELOC_MICROMIPS_LO16: |
3e722fb5 CD |
15528 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
15529 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
15530 | /* When handling an embedded PIC switch statement, we can wind |
15531 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
15532 | if (fixP->fx_done) | |
15533 | { | |
a7ebbfdf | 15534 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
15535 | as_bad_where (fixP->fx_file, fixP->fx_line, |
15536 | _("relocation overflow")); | |
df58fc94 RS |
15537 | /* 32-bit microMIPS instructions are divided into two halfwords. |
15538 | Relocations always refer to the second halfword, regardless | |
15539 | of endianness. */ | |
15540 | if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16) | |
252b5132 | 15541 | buf += 2; |
2132e3a3 | 15542 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
15543 | } |
15544 | break; | |
15545 | ||
15546 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 15547 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15548 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15549 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15550 | |
54f4ddb3 TS |
15551 | /* We need to save the bits in the instruction since fixup_segment() |
15552 | might be deleting the relocation entry (i.e., a branch within | |
15553 | the current segment). */ | |
a7ebbfdf | 15554 | if (! fixP->fx_done) |
bb2d6cd7 | 15555 | break; |
252b5132 | 15556 | |
54f4ddb3 | 15557 | /* Update old instruction data. */ |
252b5132 RH |
15558 | if (target_big_endian) |
15559 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
15560 | else | |
15561 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
15562 | ||
a7ebbfdf TS |
15563 | if (*valP + 0x20000 <= 0x3ffff) |
15564 | { | |
15565 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 15566 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15567 | } |
15568 | else if (mips_pic == NO_PIC | |
15569 | && fixP->fx_done | |
15570 | && fixP->fx_frag->fr_address >= text_section->vma | |
15571 | && (fixP->fx_frag->fr_address | |
587aac4e | 15572 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15573 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15574 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15575 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15576 | { |
15577 | /* The branch offset is too large. If this is an | |
15578 | unconditional branch, and we are not generating PIC code, | |
15579 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15580 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15581 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15582 | else |
a7ebbfdf TS |
15583 | insn = 0x08000000; /* j */ |
15584 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15585 | fixP->fx_done = 0; | |
15586 | fixP->fx_addsy = section_symbol (text_section); | |
15587 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 15588 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15589 | } |
15590 | else | |
15591 | { | |
15592 | /* If we got here, we have branch-relaxation disabled, | |
15593 | and there's nothing we can do to fix this instruction | |
15594 | without turning it into a longer sequence. */ | |
15595 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15596 | _("Branch out of range")); | |
252b5132 | 15597 | } |
252b5132 RH |
15598 | break; |
15599 | ||
df58fc94 RS |
15600 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15601 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15602 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15603 | /* We adjust the offset back to even. */ | |
15604 | if ((*valP & 0x1) != 0) | |
15605 | --(*valP); | |
15606 | ||
15607 | if (! fixP->fx_done) | |
15608 | break; | |
15609 | ||
15610 | /* Should never visit here, because we keep the relocation. */ | |
15611 | abort (); | |
15612 | break; | |
15613 | ||
252b5132 RH |
15614 | case BFD_RELOC_VTABLE_INHERIT: |
15615 | fixP->fx_done = 0; | |
15616 | if (fixP->fx_addsy | |
15617 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15618 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15619 | S_SET_WEAK (fixP->fx_addsy); | |
15620 | break; | |
15621 | ||
15622 | case BFD_RELOC_VTABLE_ENTRY: | |
15623 | fixP->fx_done = 0; | |
15624 | break; | |
15625 | ||
15626 | default: | |
15627 | internalError (); | |
15628 | } | |
a7ebbfdf TS |
15629 | |
15630 | /* Remember value for tc_gen_reloc. */ | |
15631 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15632 | } |
15633 | ||
252b5132 | 15634 | static symbolS * |
17a2f251 | 15635 | get_symbol (void) |
252b5132 RH |
15636 | { |
15637 | int c; | |
15638 | char *name; | |
15639 | symbolS *p; | |
15640 | ||
15641 | name = input_line_pointer; | |
15642 | c = get_symbol_end (); | |
15643 | p = (symbolS *) symbol_find_or_make (name); | |
15644 | *input_line_pointer = c; | |
15645 | return p; | |
15646 | } | |
15647 | ||
742a56fe RS |
15648 | /* Align the current frag to a given power of two. If a particular |
15649 | fill byte should be used, FILL points to an integer that contains | |
15650 | that byte, otherwise FILL is null. | |
15651 | ||
15652 | The MIPS assembler also automatically adjusts any preceding | |
15653 | label. */ | |
252b5132 RH |
15654 | |
15655 | static void | |
742a56fe | 15656 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 15657 | { |
7d10b47d | 15658 | mips_emit_delays (); |
df58fc94 | 15659 | mips_record_compressed_mode (); |
742a56fe RS |
15660 | if (fill == NULL && subseg_text_p (now_seg)) |
15661 | frag_align_code (to, 0); | |
15662 | else | |
15663 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
15664 | record_alignment (now_seg, to); |
15665 | if (label != NULL) | |
15666 | { | |
9c2799c2 | 15667 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 15668 | symbol_set_frag (label, frag_now); |
252b5132 RH |
15669 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
15670 | } | |
15671 | } | |
15672 | ||
15673 | /* Align to a given power of two. .align 0 turns off the automatic | |
15674 | alignment used by the data creating pseudo-ops. */ | |
15675 | ||
15676 | static void | |
17a2f251 | 15677 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15678 | { |
742a56fe | 15679 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15680 | long max_alignment = 28; |
252b5132 | 15681 | |
54f4ddb3 | 15682 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15683 | to the aligned address. |
54f4ddb3 | 15684 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15685 | a .align pseudo instruction. |
54f4ddb3 | 15686 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15687 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15688 | We don't. */ |
252b5132 RH |
15689 | |
15690 | temp = get_absolute_expression (); | |
15691 | if (temp > max_alignment) | |
15692 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15693 | else if (temp < 0) | |
15694 | { | |
15695 | as_warn (_("Alignment negative: 0 assumed.")); | |
15696 | temp = 0; | |
15697 | } | |
15698 | if (*input_line_pointer == ',') | |
15699 | { | |
f9419b05 | 15700 | ++input_line_pointer; |
742a56fe RS |
15701 | fill_value = get_absolute_expression (); |
15702 | fill_ptr = &fill_value; | |
252b5132 RH |
15703 | } |
15704 | else | |
742a56fe | 15705 | fill_ptr = 0; |
252b5132 RH |
15706 | if (temp) |
15707 | { | |
a8dbcb85 TS |
15708 | segment_info_type *si = seg_info (now_seg); |
15709 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15710 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15711 | auto_align = 1; |
742a56fe | 15712 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
15713 | } |
15714 | else | |
15715 | { | |
15716 | auto_align = 0; | |
15717 | } | |
15718 | ||
15719 | demand_empty_rest_of_line (); | |
15720 | } | |
15721 | ||
252b5132 | 15722 | static void |
17a2f251 | 15723 | s_change_sec (int sec) |
252b5132 RH |
15724 | { |
15725 | segT seg; | |
15726 | ||
252b5132 RH |
15727 | #ifdef OBJ_ELF |
15728 | /* The ELF backend needs to know that we are changing sections, so | |
15729 | that .previous works correctly. We could do something like check | |
b6ff326e | 15730 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15731 | as it would not be appropriate to use it in the section changing |
15732 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15733 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15734 | if (IS_ELF) |
15735 | obj_elf_section_change_hook (); | |
252b5132 RH |
15736 | #endif |
15737 | ||
7d10b47d | 15738 | mips_emit_delays (); |
6a32d874 | 15739 | |
252b5132 RH |
15740 | switch (sec) |
15741 | { | |
15742 | case 't': | |
15743 | s_text (0); | |
15744 | break; | |
15745 | case 'd': | |
15746 | s_data (0); | |
15747 | break; | |
15748 | case 'b': | |
15749 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15750 | demand_empty_rest_of_line (); | |
15751 | break; | |
15752 | ||
15753 | case 'r': | |
4d0d148d TS |
15754 | seg = subseg_new (RDATA_SECTION_NAME, |
15755 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 15756 | if (IS_ELF) |
252b5132 | 15757 | { |
4d0d148d TS |
15758 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15759 | | SEC_READONLY | SEC_RELOC | |
15760 | | SEC_DATA)); | |
c41e87e3 | 15761 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15762 | record_alignment (seg, 4); |
252b5132 | 15763 | } |
4d0d148d | 15764 | demand_empty_rest_of_line (); |
252b5132 RH |
15765 | break; |
15766 | ||
15767 | case 's': | |
4d0d148d | 15768 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 15769 | if (IS_ELF) |
252b5132 | 15770 | { |
4d0d148d TS |
15771 | bfd_set_section_flags (stdoutput, seg, |
15772 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 15773 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15774 | record_alignment (seg, 4); |
252b5132 | 15775 | } |
4d0d148d TS |
15776 | demand_empty_rest_of_line (); |
15777 | break; | |
998b3c36 MR |
15778 | |
15779 | case 'B': | |
15780 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
15781 | if (IS_ELF) | |
15782 | { | |
15783 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
15784 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15785 | record_alignment (seg, 4); | |
15786 | } | |
15787 | demand_empty_rest_of_line (); | |
15788 | break; | |
252b5132 RH |
15789 | } |
15790 | ||
15791 | auto_align = 1; | |
15792 | } | |
b34976b6 | 15793 | |
cca86cc8 | 15794 | void |
17a2f251 | 15795 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15796 | { |
7ed4a06a | 15797 | #ifdef OBJ_ELF |
cca86cc8 SC |
15798 | char *section_name; |
15799 | char c; | |
684022ea | 15800 | char next_c = 0; |
cca86cc8 SC |
15801 | int section_type; |
15802 | int section_flag; | |
15803 | int section_entry_size; | |
15804 | int section_alignment; | |
b34976b6 | 15805 | |
f43abd2b | 15806 | if (!IS_ELF) |
7ed4a06a TS |
15807 | return; |
15808 | ||
cca86cc8 SC |
15809 | section_name = input_line_pointer; |
15810 | c = get_symbol_end (); | |
a816d1ed AO |
15811 | if (c) |
15812 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 15813 | |
4cf0dd0d TS |
15814 | /* Do we have .section Name<,"flags">? */ |
15815 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15816 | { |
4cf0dd0d TS |
15817 | /* just after name is now '\0'. */ |
15818 | *input_line_pointer = c; | |
cca86cc8 SC |
15819 | input_line_pointer = section_name; |
15820 | obj_elf_section (ignore); | |
15821 | return; | |
15822 | } | |
15823 | input_line_pointer++; | |
15824 | ||
15825 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15826 | if (c == ',') | |
15827 | section_type = get_absolute_expression (); | |
15828 | else | |
15829 | section_type = 0; | |
15830 | if (*input_line_pointer++ == ',') | |
15831 | section_flag = get_absolute_expression (); | |
15832 | else | |
15833 | section_flag = 0; | |
15834 | if (*input_line_pointer++ == ',') | |
15835 | section_entry_size = get_absolute_expression (); | |
15836 | else | |
15837 | section_entry_size = 0; | |
15838 | if (*input_line_pointer++ == ',') | |
15839 | section_alignment = get_absolute_expression (); | |
15840 | else | |
15841 | section_alignment = 0; | |
87975d2a AM |
15842 | /* FIXME: really ignore? */ |
15843 | (void) section_alignment; | |
cca86cc8 | 15844 | |
a816d1ed AO |
15845 | section_name = xstrdup (section_name); |
15846 | ||
8ab8a5c8 RS |
15847 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15848 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15849 | traditionally had to fall back on the more common @progbits instead. | |
15850 | ||
15851 | There's nothing really harmful in this, since bfd will correct | |
15852 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15853 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15854 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15855 | ||
15856 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15857 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15858 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15859 | generic type-checking code. */ | |
15860 | if (section_type == SHT_MIPS_DWARF) | |
15861 | section_type = SHT_PROGBITS; | |
15862 | ||
cca86cc8 SC |
15863 | obj_elf_change_section (section_name, section_type, section_flag, |
15864 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
15865 | |
15866 | if (now_seg->name != section_name) | |
15867 | free (section_name); | |
7ed4a06a | 15868 | #endif /* OBJ_ELF */ |
cca86cc8 | 15869 | } |
252b5132 RH |
15870 | |
15871 | void | |
17a2f251 | 15872 | mips_enable_auto_align (void) |
252b5132 RH |
15873 | { |
15874 | auto_align = 1; | |
15875 | } | |
15876 | ||
15877 | static void | |
17a2f251 | 15878 | s_cons (int log_size) |
252b5132 | 15879 | { |
a8dbcb85 TS |
15880 | segment_info_type *si = seg_info (now_seg); |
15881 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15882 | symbolS *label; |
15883 | ||
a8dbcb85 | 15884 | label = l != NULL ? l->label : NULL; |
7d10b47d | 15885 | mips_emit_delays (); |
252b5132 RH |
15886 | if (log_size > 0 && auto_align) |
15887 | mips_align (log_size, 0, label); | |
252b5132 | 15888 | cons (1 << log_size); |
a1facbec | 15889 | mips_clear_insn_labels (); |
252b5132 RH |
15890 | } |
15891 | ||
15892 | static void | |
17a2f251 | 15893 | s_float_cons (int type) |
252b5132 | 15894 | { |
a8dbcb85 TS |
15895 | segment_info_type *si = seg_info (now_seg); |
15896 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15897 | symbolS *label; |
15898 | ||
a8dbcb85 | 15899 | label = l != NULL ? l->label : NULL; |
252b5132 | 15900 | |
7d10b47d | 15901 | mips_emit_delays (); |
252b5132 RH |
15902 | |
15903 | if (auto_align) | |
49309057 ILT |
15904 | { |
15905 | if (type == 'd') | |
15906 | mips_align (3, 0, label); | |
15907 | else | |
15908 | mips_align (2, 0, label); | |
15909 | } | |
252b5132 | 15910 | |
252b5132 | 15911 | float_cons (type); |
a1facbec | 15912 | mips_clear_insn_labels (); |
252b5132 RH |
15913 | } |
15914 | ||
15915 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15916 | permitted to say | |
15917 | .globl foo .text | |
15918 | where foo is an undefined symbol, to mean that foo should be | |
15919 | considered to be the address of a function. */ | |
15920 | ||
15921 | static void | |
17a2f251 | 15922 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15923 | { |
15924 | char *name; | |
15925 | int c; | |
15926 | symbolS *symbolP; | |
15927 | flagword flag; | |
15928 | ||
8a06b769 | 15929 | do |
252b5132 | 15930 | { |
8a06b769 | 15931 | name = input_line_pointer; |
252b5132 | 15932 | c = get_symbol_end (); |
8a06b769 TS |
15933 | symbolP = symbol_find_or_make (name); |
15934 | S_SET_EXTERNAL (symbolP); | |
15935 | ||
252b5132 | 15936 | *input_line_pointer = c; |
8a06b769 | 15937 | SKIP_WHITESPACE (); |
252b5132 | 15938 | |
8a06b769 TS |
15939 | /* On Irix 5, every global symbol that is not explicitly labelled as |
15940 | being a function is apparently labelled as being an object. */ | |
15941 | flag = BSF_OBJECT; | |
252b5132 | 15942 | |
8a06b769 TS |
15943 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
15944 | && (*input_line_pointer != ',')) | |
15945 | { | |
15946 | char *secname; | |
15947 | asection *sec; | |
15948 | ||
15949 | secname = input_line_pointer; | |
15950 | c = get_symbol_end (); | |
15951 | sec = bfd_get_section_by_name (stdoutput, secname); | |
15952 | if (sec == NULL) | |
15953 | as_bad (_("%s: no such section"), secname); | |
15954 | *input_line_pointer = c; | |
15955 | ||
15956 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
15957 | flag = BSF_FUNCTION; | |
15958 | } | |
15959 | ||
15960 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
15961 | ||
15962 | c = *input_line_pointer; | |
15963 | if (c == ',') | |
15964 | { | |
15965 | input_line_pointer++; | |
15966 | SKIP_WHITESPACE (); | |
15967 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
15968 | c = '\n'; | |
15969 | } | |
15970 | } | |
15971 | while (c == ','); | |
252b5132 | 15972 | |
252b5132 RH |
15973 | demand_empty_rest_of_line (); |
15974 | } | |
15975 | ||
15976 | static void | |
17a2f251 | 15977 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15978 | { |
15979 | char *opt; | |
15980 | char c; | |
15981 | ||
15982 | opt = input_line_pointer; | |
15983 | c = get_symbol_end (); | |
15984 | ||
15985 | if (*opt == 'O') | |
15986 | { | |
15987 | /* FIXME: What does this mean? */ | |
15988 | } | |
15989 | else if (strncmp (opt, "pic", 3) == 0) | |
15990 | { | |
15991 | int i; | |
15992 | ||
15993 | i = atoi (opt + 3); | |
15994 | if (i == 0) | |
15995 | mips_pic = NO_PIC; | |
15996 | else if (i == 2) | |
143d77c5 | 15997 | { |
8b828383 | 15998 | mips_pic = SVR4_PIC; |
143d77c5 EC |
15999 | mips_abicalls = TRUE; |
16000 | } | |
252b5132 RH |
16001 | else |
16002 | as_bad (_(".option pic%d not supported"), i); | |
16003 | ||
4d0d148d | 16004 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16005 | { |
16006 | if (g_switch_seen && g_switch_value != 0) | |
16007 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16008 | g_switch_value = 0; | |
16009 | bfd_set_gp_size (stdoutput, 0); | |
16010 | } | |
16011 | } | |
16012 | else | |
16013 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16014 | ||
16015 | *input_line_pointer = c; | |
16016 | demand_empty_rest_of_line (); | |
16017 | } | |
16018 | ||
16019 | /* This structure is used to hold a stack of .set values. */ | |
16020 | ||
e972090a NC |
16021 | struct mips_option_stack |
16022 | { | |
252b5132 RH |
16023 | struct mips_option_stack *next; |
16024 | struct mips_set_options options; | |
16025 | }; | |
16026 | ||
16027 | static struct mips_option_stack *mips_opts_stack; | |
16028 | ||
16029 | /* Handle the .set pseudo-op. */ | |
16030 | ||
16031 | static void | |
17a2f251 | 16032 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16033 | { |
16034 | char *name = input_line_pointer, ch; | |
16035 | ||
16036 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16037 | ++input_line_pointer; |
252b5132 RH |
16038 | ch = *input_line_pointer; |
16039 | *input_line_pointer = '\0'; | |
16040 | ||
16041 | if (strcmp (name, "reorder") == 0) | |
16042 | { | |
7d10b47d RS |
16043 | if (mips_opts.noreorder) |
16044 | end_noreorder (); | |
252b5132 RH |
16045 | } |
16046 | else if (strcmp (name, "noreorder") == 0) | |
16047 | { | |
7d10b47d RS |
16048 | if (!mips_opts.noreorder) |
16049 | start_noreorder (); | |
252b5132 | 16050 | } |
741fe287 MR |
16051 | else if (strncmp (name, "at=", 3) == 0) |
16052 | { | |
16053 | char *s = name + 3; | |
16054 | ||
16055 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16056 | as_bad (_("Unrecognized register name `%s'"), s); | |
16057 | } | |
252b5132 RH |
16058 | else if (strcmp (name, "at") == 0) |
16059 | { | |
741fe287 | 16060 | mips_opts.at = ATREG; |
252b5132 RH |
16061 | } |
16062 | else if (strcmp (name, "noat") == 0) | |
16063 | { | |
741fe287 | 16064 | mips_opts.at = ZERO; |
252b5132 RH |
16065 | } |
16066 | else if (strcmp (name, "macro") == 0) | |
16067 | { | |
16068 | mips_opts.warn_about_macros = 0; | |
16069 | } | |
16070 | else if (strcmp (name, "nomacro") == 0) | |
16071 | { | |
16072 | if (mips_opts.noreorder == 0) | |
16073 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16074 | mips_opts.warn_about_macros = 1; | |
16075 | } | |
16076 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16077 | { | |
16078 | mips_opts.nomove = 0; | |
16079 | } | |
16080 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16081 | { | |
16082 | mips_opts.nomove = 1; | |
16083 | } | |
16084 | else if (strcmp (name, "bopt") == 0) | |
16085 | { | |
16086 | mips_opts.nobopt = 0; | |
16087 | } | |
16088 | else if (strcmp (name, "nobopt") == 0) | |
16089 | { | |
16090 | mips_opts.nobopt = 1; | |
16091 | } | |
ad3fea08 TS |
16092 | else if (strcmp (name, "gp=default") == 0) |
16093 | mips_opts.gp32 = file_mips_gp32; | |
16094 | else if (strcmp (name, "gp=32") == 0) | |
16095 | mips_opts.gp32 = 1; | |
16096 | else if (strcmp (name, "gp=64") == 0) | |
16097 | { | |
16098 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16099 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16100 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16101 | mips_opts.gp32 = 0; | |
16102 | } | |
16103 | else if (strcmp (name, "fp=default") == 0) | |
16104 | mips_opts.fp32 = file_mips_fp32; | |
16105 | else if (strcmp (name, "fp=32") == 0) | |
16106 | mips_opts.fp32 = 1; | |
16107 | else if (strcmp (name, "fp=64") == 0) | |
16108 | { | |
16109 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16110 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16111 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16112 | mips_opts.fp32 = 0; | |
16113 | } | |
037b32b9 AN |
16114 | else if (strcmp (name, "softfloat") == 0) |
16115 | mips_opts.soft_float = 1; | |
16116 | else if (strcmp (name, "hardfloat") == 0) | |
16117 | mips_opts.soft_float = 0; | |
16118 | else if (strcmp (name, "singlefloat") == 0) | |
16119 | mips_opts.single_float = 1; | |
16120 | else if (strcmp (name, "doublefloat") == 0) | |
16121 | mips_opts.single_float = 0; | |
252b5132 RH |
16122 | else if (strcmp (name, "mips16") == 0 |
16123 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16124 | { |
16125 | if (mips_opts.micromips == 1) | |
16126 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16127 | mips_opts.mips16 = 1; | |
16128 | } | |
252b5132 RH |
16129 | else if (strcmp (name, "nomips16") == 0 |
16130 | || strcmp (name, "noMIPS-16") == 0) | |
16131 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16132 | else if (strcmp (name, "micromips") == 0) |
16133 | { | |
16134 | if (mips_opts.mips16 == 1) | |
16135 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16136 | mips_opts.micromips = 1; | |
16137 | } | |
16138 | else if (strcmp (name, "nomicromips") == 0) | |
16139 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16140 | else if (strcmp (name, "smartmips") == 0) |
16141 | { | |
ad3fea08 | 16142 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16143 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16144 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16145 | mips_opts.ase_smartmips = 1; | |
16146 | } | |
16147 | else if (strcmp (name, "nosmartmips") == 0) | |
16148 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16149 | else if (strcmp (name, "mips3d") == 0) |
16150 | mips_opts.ase_mips3d = 1; | |
16151 | else if (strcmp (name, "nomips3d") == 0) | |
16152 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16153 | else if (strcmp (name, "mdmx") == 0) |
16154 | mips_opts.ase_mdmx = 1; | |
16155 | else if (strcmp (name, "nomdmx") == 0) | |
16156 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16157 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16158 | { |
16159 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16160 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16161 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16162 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16163 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16164 | } |
74cd071d | 16165 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16166 | { |
16167 | mips_opts.ase_dsp = 0; | |
16168 | mips_opts.ase_dspr2 = 0; | |
16169 | } | |
16170 | else if (strcmp (name, "dspr2") == 0) | |
16171 | { | |
16172 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16173 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16174 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16175 | mips_opts.ase_dspr2 = 1; | |
16176 | mips_opts.ase_dsp = 1; | |
16177 | } | |
16178 | else if (strcmp (name, "nodspr2") == 0) | |
16179 | { | |
16180 | mips_opts.ase_dspr2 = 0; | |
16181 | mips_opts.ase_dsp = 0; | |
16182 | } | |
ef2e4d86 | 16183 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16184 | { |
16185 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16186 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16187 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16188 | mips_opts.ase_mt = 1; | |
16189 | } | |
ef2e4d86 CF |
16190 | else if (strcmp (name, "nomt") == 0) |
16191 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16192 | else if (strcmp (name, "mcu") == 0) |
16193 | mips_opts.ase_mcu = 1; | |
16194 | else if (strcmp (name, "nomcu") == 0) | |
16195 | mips_opts.ase_mcu = 0; | |
1a2c1fad | 16196 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16197 | { |
af7ee8bf | 16198 | int reset = 0; |
252b5132 | 16199 | |
1a2c1fad CD |
16200 | /* Permit the user to change the ISA and architecture on the fly. |
16201 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16202 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16203 | { |
16204 | reset = 1; | |
16205 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16206 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16207 | } |
16208 | else if (strncmp (name, "arch=", 5) == 0) | |
16209 | { | |
16210 | const struct mips_cpu_info *p; | |
16211 | ||
16212 | p = mips_parse_cpu("internal use", name + 5); | |
16213 | if (!p) | |
16214 | as_bad (_("unknown architecture %s"), name + 5); | |
16215 | else | |
16216 | { | |
16217 | mips_opts.arch = p->cpu; | |
16218 | mips_opts.isa = p->isa; | |
16219 | } | |
16220 | } | |
81a21e38 TS |
16221 | else if (strncmp (name, "mips", 4) == 0) |
16222 | { | |
16223 | const struct mips_cpu_info *p; | |
16224 | ||
16225 | p = mips_parse_cpu("internal use", name); | |
16226 | if (!p) | |
16227 | as_bad (_("unknown ISA level %s"), name + 4); | |
16228 | else | |
16229 | { | |
16230 | mips_opts.arch = p->cpu; | |
16231 | mips_opts.isa = p->isa; | |
16232 | } | |
16233 | } | |
af7ee8bf | 16234 | else |
81a21e38 | 16235 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16236 | |
16237 | switch (mips_opts.isa) | |
98d3f06f KH |
16238 | { |
16239 | case 0: | |
98d3f06f | 16240 | break; |
af7ee8bf CD |
16241 | case ISA_MIPS1: |
16242 | case ISA_MIPS2: | |
16243 | case ISA_MIPS32: | |
16244 | case ISA_MIPS32R2: | |
98d3f06f KH |
16245 | mips_opts.gp32 = 1; |
16246 | mips_opts.fp32 = 1; | |
16247 | break; | |
af7ee8bf CD |
16248 | case ISA_MIPS3: |
16249 | case ISA_MIPS4: | |
16250 | case ISA_MIPS5: | |
16251 | case ISA_MIPS64: | |
5f74bc13 | 16252 | case ISA_MIPS64R2: |
98d3f06f KH |
16253 | mips_opts.gp32 = 0; |
16254 | mips_opts.fp32 = 0; | |
16255 | break; | |
16256 | default: | |
16257 | as_bad (_("unknown ISA level %s"), name + 4); | |
16258 | break; | |
16259 | } | |
af7ee8bf | 16260 | if (reset) |
98d3f06f | 16261 | { |
af7ee8bf CD |
16262 | mips_opts.gp32 = file_mips_gp32; |
16263 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16264 | } |
252b5132 RH |
16265 | } |
16266 | else if (strcmp (name, "autoextend") == 0) | |
16267 | mips_opts.noautoextend = 0; | |
16268 | else if (strcmp (name, "noautoextend") == 0) | |
16269 | mips_opts.noautoextend = 1; | |
16270 | else if (strcmp (name, "push") == 0) | |
16271 | { | |
16272 | struct mips_option_stack *s; | |
16273 | ||
16274 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16275 | s->next = mips_opts_stack; | |
16276 | s->options = mips_opts; | |
16277 | mips_opts_stack = s; | |
16278 | } | |
16279 | else if (strcmp (name, "pop") == 0) | |
16280 | { | |
16281 | struct mips_option_stack *s; | |
16282 | ||
16283 | s = mips_opts_stack; | |
16284 | if (s == NULL) | |
16285 | as_bad (_(".set pop with no .set push")); | |
16286 | else | |
16287 | { | |
16288 | /* If we're changing the reorder mode we need to handle | |
16289 | delay slots correctly. */ | |
16290 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16291 | start_noreorder (); |
252b5132 | 16292 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16293 | end_noreorder (); |
252b5132 RH |
16294 | |
16295 | mips_opts = s->options; | |
16296 | mips_opts_stack = s->next; | |
16297 | free (s); | |
16298 | } | |
16299 | } | |
aed1a261 RS |
16300 | else if (strcmp (name, "sym32") == 0) |
16301 | mips_opts.sym32 = TRUE; | |
16302 | else if (strcmp (name, "nosym32") == 0) | |
16303 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16304 | else if (strchr (name, ',')) |
16305 | { | |
16306 | /* Generic ".set" directive; use the generic handler. */ | |
16307 | *input_line_pointer = ch; | |
16308 | input_line_pointer = name; | |
16309 | s_set (0); | |
16310 | return; | |
16311 | } | |
252b5132 RH |
16312 | else |
16313 | { | |
16314 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16315 | } | |
16316 | *input_line_pointer = ch; | |
16317 | demand_empty_rest_of_line (); | |
16318 | } | |
16319 | ||
16320 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16321 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16322 | ||
16323 | static void | |
17a2f251 | 16324 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16325 | { |
16326 | mips_pic = SVR4_PIC; | |
143d77c5 | 16327 | mips_abicalls = TRUE; |
4d0d148d TS |
16328 | |
16329 | if (g_switch_seen && g_switch_value != 0) | |
16330 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16331 | g_switch_value = 0; | |
16332 | ||
252b5132 RH |
16333 | bfd_set_gp_size (stdoutput, 0); |
16334 | demand_empty_rest_of_line (); | |
16335 | } | |
16336 | ||
16337 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16338 | PIC code. It sets the $gp register for the function based on the | |
16339 | function address, which is in the register named in the argument. | |
16340 | This uses a relocation against _gp_disp, which is handled specially | |
16341 | by the linker. The result is: | |
16342 | lui $gp,%hi(_gp_disp) | |
16343 | addiu $gp,$gp,%lo(_gp_disp) | |
16344 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16345 | The .cpload argument is normally $25 == $t9. |
16346 | ||
16347 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16348 | lui $gp,%hi(__gnu_local_gp) |
16349 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16350 | and the argument is ignored. This saves an instruction, but the |
16351 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16352 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16353 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16354 | |
16355 | static void | |
17a2f251 | 16356 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16357 | { |
16358 | expressionS ex; | |
aa6975fb ILT |
16359 | int reg; |
16360 | int in_shared; | |
252b5132 | 16361 | |
6478892d TS |
16362 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16363 | .cpload is ignored. */ | |
16364 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16365 | { |
16366 | s_ignore (0); | |
16367 | return; | |
16368 | } | |
16369 | ||
d3ecfc59 | 16370 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16371 | if (mips_opts.noreorder == 0) |
16372 | as_warn (_(".cpload not in noreorder section")); | |
16373 | ||
aa6975fb ILT |
16374 | reg = tc_get_register (0); |
16375 | ||
16376 | /* If we need to produce a 64-bit address, we are better off using | |
16377 | the default instruction sequence. */ | |
aed1a261 | 16378 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16379 | |
252b5132 | 16380 | ex.X_op = O_symbol; |
bbe506e8 TS |
16381 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16382 | "__gnu_local_gp"); | |
252b5132 RH |
16383 | ex.X_op_symbol = NULL; |
16384 | ex.X_add_number = 0; | |
16385 | ||
16386 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16387 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16388 | |
584892a6 | 16389 | macro_start (); |
67c0d1eb RS |
16390 | macro_build_lui (&ex, mips_gp_register); |
16391 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16392 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16393 | if (in_shared) |
16394 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16395 | mips_gp_register, reg); | |
584892a6 | 16396 | macro_end (); |
252b5132 RH |
16397 | |
16398 | demand_empty_rest_of_line (); | |
16399 | } | |
16400 | ||
6478892d TS |
16401 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16402 | .cpsetup $reg1, offset|$reg2, label | |
16403 | ||
16404 | If offset is given, this results in: | |
16405 | sd $gp, offset($sp) | |
956cd1d6 | 16406 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16407 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16408 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16409 | |
16410 | If $reg2 is given, this results in: | |
16411 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16412 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16413 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16414 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16415 | $reg1 is normally $25 == $t9. |
16416 | ||
16417 | The -mno-shared option replaces the last three instructions with | |
16418 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16419 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16420 | |
6478892d | 16421 | static void |
17a2f251 | 16422 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16423 | { |
16424 | expressionS ex_off; | |
16425 | expressionS ex_sym; | |
16426 | int reg1; | |
6478892d | 16427 | |
8586fc66 | 16428 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16429 | We also need NewABI support. */ |
16430 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16431 | { | |
16432 | s_ignore (0); | |
16433 | return; | |
16434 | } | |
16435 | ||
16436 | reg1 = tc_get_register (0); | |
16437 | SKIP_WHITESPACE (); | |
16438 | if (*input_line_pointer != ',') | |
16439 | { | |
16440 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16441 | return; | |
16442 | } | |
16443 | else | |
80245285 | 16444 | ++input_line_pointer; |
6478892d TS |
16445 | SKIP_WHITESPACE (); |
16446 | if (*input_line_pointer == '$') | |
80245285 TS |
16447 | { |
16448 | mips_cpreturn_register = tc_get_register (0); | |
16449 | mips_cpreturn_offset = -1; | |
16450 | } | |
6478892d | 16451 | else |
80245285 TS |
16452 | { |
16453 | mips_cpreturn_offset = get_absolute_expression (); | |
16454 | mips_cpreturn_register = -1; | |
16455 | } | |
6478892d TS |
16456 | SKIP_WHITESPACE (); |
16457 | if (*input_line_pointer != ',') | |
16458 | { | |
16459 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16460 | return; | |
16461 | } | |
16462 | else | |
f9419b05 | 16463 | ++input_line_pointer; |
6478892d | 16464 | SKIP_WHITESPACE (); |
f21f8242 | 16465 | expression (&ex_sym); |
6478892d | 16466 | |
584892a6 | 16467 | macro_start (); |
6478892d TS |
16468 | if (mips_cpreturn_register == -1) |
16469 | { | |
16470 | ex_off.X_op = O_constant; | |
16471 | ex_off.X_add_symbol = NULL; | |
16472 | ex_off.X_op_symbol = NULL; | |
16473 | ex_off.X_add_number = mips_cpreturn_offset; | |
16474 | ||
67c0d1eb | 16475 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16476 | BFD_RELOC_LO16, SP); |
6478892d TS |
16477 | } |
16478 | else | |
67c0d1eb | 16479 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16480 | mips_gp_register, 0); |
6478892d | 16481 | |
aed1a261 | 16482 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16483 | { |
df58fc94 | 16484 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16485 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16486 | BFD_RELOC_HI16_S); | |
16487 | ||
16488 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16489 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16490 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16491 | ||
16492 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16493 | mips_gp_register, reg1); | |
16494 | } | |
16495 | else | |
16496 | { | |
16497 | expressionS ex; | |
16498 | ||
16499 | ex.X_op = O_symbol; | |
4184909a | 16500 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16501 | ex.X_op_symbol = NULL; |
16502 | ex.X_add_number = 0; | |
6e1304d8 | 16503 | |
aa6975fb ILT |
16504 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16505 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16506 | ||
16507 | macro_build_lui (&ex, mips_gp_register); | |
16508 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16509 | mips_gp_register, BFD_RELOC_LO16); | |
16510 | } | |
f21f8242 | 16511 | |
584892a6 | 16512 | macro_end (); |
6478892d TS |
16513 | |
16514 | demand_empty_rest_of_line (); | |
16515 | } | |
16516 | ||
16517 | static void | |
17a2f251 | 16518 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16519 | { |
16520 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16521 | .cplocal is ignored. */ |
6478892d TS |
16522 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16523 | { | |
16524 | s_ignore (0); | |
16525 | return; | |
16526 | } | |
16527 | ||
16528 | mips_gp_register = tc_get_register (0); | |
85b51719 | 16529 | demand_empty_rest_of_line (); |
6478892d TS |
16530 | } |
16531 | ||
252b5132 RH |
16532 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16533 | offset from $sp. The offset is remembered, and after making a PIC | |
16534 | call $gp is restored from that location. */ | |
16535 | ||
16536 | static void | |
17a2f251 | 16537 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16538 | { |
16539 | expressionS ex; | |
252b5132 | 16540 | |
6478892d | 16541 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16542 | .cprestore is ignored. */ |
6478892d | 16543 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16544 | { |
16545 | s_ignore (0); | |
16546 | return; | |
16547 | } | |
16548 | ||
16549 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 16550 | mips_cprestore_valid = 1; |
252b5132 RH |
16551 | |
16552 | ex.X_op = O_constant; | |
16553 | ex.X_add_symbol = NULL; | |
16554 | ex.X_op_symbol = NULL; | |
16555 | ex.X_add_number = mips_cprestore_offset; | |
16556 | ||
584892a6 | 16557 | macro_start (); |
67c0d1eb RS |
16558 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16559 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16560 | macro_end (); |
252b5132 RH |
16561 | |
16562 | demand_empty_rest_of_line (); | |
16563 | } | |
16564 | ||
6478892d | 16565 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16566 | was given in the preceding .cpsetup, it results in: |
6478892d | 16567 | ld $gp, offset($sp) |
76b3015f | 16568 | |
6478892d | 16569 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16570 | daddu $gp, $reg2, $0 */ |
16571 | ||
6478892d | 16572 | static void |
17a2f251 | 16573 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16574 | { |
16575 | expressionS ex; | |
6478892d TS |
16576 | |
16577 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16578 | We also need NewABI support. */ | |
16579 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16580 | { | |
16581 | s_ignore (0); | |
16582 | return; | |
16583 | } | |
16584 | ||
584892a6 | 16585 | macro_start (); |
6478892d TS |
16586 | if (mips_cpreturn_register == -1) |
16587 | { | |
16588 | ex.X_op = O_constant; | |
16589 | ex.X_add_symbol = NULL; | |
16590 | ex.X_op_symbol = NULL; | |
16591 | ex.X_add_number = mips_cpreturn_offset; | |
16592 | ||
67c0d1eb | 16593 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16594 | } |
16595 | else | |
67c0d1eb | 16596 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16597 | mips_cpreturn_register, 0); |
584892a6 | 16598 | macro_end (); |
6478892d TS |
16599 | |
16600 | demand_empty_rest_of_line (); | |
16601 | } | |
16602 | ||
d0f13682 CLT |
16603 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16604 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16605 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16606 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16607 | |
16608 | static void | |
d0f13682 CLT |
16609 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16610 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16611 | { |
16612 | expressionS ex; | |
16613 | char *p; | |
16614 | ||
16615 | expression (&ex); | |
16616 | ||
16617 | if (ex.X_op != O_symbol) | |
16618 | { | |
d0f13682 | 16619 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
16620 | ignore_rest_of_line (); |
16621 | } | |
16622 | ||
16623 | p = frag_more (bytes); | |
16624 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16625 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 JM |
16626 | demand_empty_rest_of_line (); |
16627 | } | |
16628 | ||
16629 | /* Handle .dtprelword. */ | |
16630 | ||
16631 | static void | |
16632 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16633 | { | |
d0f13682 | 16634 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16635 | } |
16636 | ||
16637 | /* Handle .dtpreldword. */ | |
16638 | ||
16639 | static void | |
16640 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16641 | { | |
d0f13682 CLT |
16642 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16643 | } | |
16644 | ||
16645 | /* Handle .tprelword. */ | |
16646 | ||
16647 | static void | |
16648 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16649 | { | |
16650 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16651 | } | |
16652 | ||
16653 | /* Handle .tpreldword. */ | |
16654 | ||
16655 | static void | |
16656 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16657 | { | |
16658 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16659 | } |
16660 | ||
6478892d TS |
16661 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16662 | code. It sets the offset to use in gp_rel relocations. */ | |
16663 | ||
16664 | static void | |
17a2f251 | 16665 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16666 | { |
16667 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16668 | We also need NewABI support. */ | |
16669 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16670 | { | |
16671 | s_ignore (0); | |
16672 | return; | |
16673 | } | |
16674 | ||
def2e0dd | 16675 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16676 | |
16677 | demand_empty_rest_of_line (); | |
16678 | } | |
16679 | ||
252b5132 RH |
16680 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16681 | code. It generates a 32 bit GP relative reloc. */ | |
16682 | ||
16683 | static void | |
17a2f251 | 16684 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16685 | { |
a8dbcb85 TS |
16686 | segment_info_type *si; |
16687 | struct insn_label_list *l; | |
252b5132 RH |
16688 | symbolS *label; |
16689 | expressionS ex; | |
16690 | char *p; | |
16691 | ||
16692 | /* When not generating PIC code, this is treated as .word. */ | |
16693 | if (mips_pic != SVR4_PIC) | |
16694 | { | |
16695 | s_cons (2); | |
16696 | return; | |
16697 | } | |
16698 | ||
a8dbcb85 TS |
16699 | si = seg_info (now_seg); |
16700 | l = si->label_list; | |
16701 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16702 | mips_emit_delays (); |
252b5132 RH |
16703 | if (auto_align) |
16704 | mips_align (2, 0, label); | |
252b5132 RH |
16705 | |
16706 | expression (&ex); | |
a1facbec | 16707 | mips_clear_insn_labels (); |
252b5132 RH |
16708 | |
16709 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16710 | { | |
16711 | as_bad (_("Unsupported use of .gpword")); | |
16712 | ignore_rest_of_line (); | |
16713 | } | |
16714 | ||
16715 | p = frag_more (4); | |
17a2f251 | 16716 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16717 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16718 | BFD_RELOC_GPREL32); |
252b5132 RH |
16719 | |
16720 | demand_empty_rest_of_line (); | |
16721 | } | |
16722 | ||
10181a0d | 16723 | static void |
17a2f251 | 16724 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16725 | { |
a8dbcb85 TS |
16726 | segment_info_type *si; |
16727 | struct insn_label_list *l; | |
10181a0d AO |
16728 | symbolS *label; |
16729 | expressionS ex; | |
16730 | char *p; | |
16731 | ||
16732 | /* When not generating PIC code, this is treated as .dword. */ | |
16733 | if (mips_pic != SVR4_PIC) | |
16734 | { | |
16735 | s_cons (3); | |
16736 | return; | |
16737 | } | |
16738 | ||
a8dbcb85 TS |
16739 | si = seg_info (now_seg); |
16740 | l = si->label_list; | |
16741 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16742 | mips_emit_delays (); |
10181a0d AO |
16743 | if (auto_align) |
16744 | mips_align (3, 0, label); | |
10181a0d AO |
16745 | |
16746 | expression (&ex); | |
a1facbec | 16747 | mips_clear_insn_labels (); |
10181a0d AO |
16748 | |
16749 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16750 | { | |
16751 | as_bad (_("Unsupported use of .gpdword")); | |
16752 | ignore_rest_of_line (); | |
16753 | } | |
16754 | ||
16755 | p = frag_more (8); | |
17a2f251 | 16756 | md_number_to_chars (p, 0, 8); |
a105a300 | 16757 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16758 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16759 | |
16760 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16761 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16762 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16763 | |
16764 | demand_empty_rest_of_line (); | |
16765 | } | |
16766 | ||
252b5132 RH |
16767 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16768 | tables in SVR4 PIC code. */ | |
16769 | ||
16770 | static void | |
17a2f251 | 16771 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16772 | { |
252b5132 RH |
16773 | int reg; |
16774 | ||
10181a0d AO |
16775 | /* This is ignored when not generating SVR4 PIC code. */ |
16776 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16777 | { |
16778 | s_ignore (0); | |
16779 | return; | |
16780 | } | |
16781 | ||
16782 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 16783 | macro_start (); |
252b5132 | 16784 | reg = tc_get_register (0); |
67c0d1eb | 16785 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16786 | macro_end (); |
252b5132 | 16787 | |
bdaaa2e1 | 16788 | demand_empty_rest_of_line (); |
252b5132 RH |
16789 | } |
16790 | ||
16791 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16792 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16793 | such as generating jalx instructions when needed. We also make |
16794 | them odd for the duration of the assembly, in order to generate the | |
16795 | right sort of code. We will make them even in the adjust_symtab | |
16796 | routine, while leaving them marked. This is convenient for the | |
16797 | debugger and the disassembler. The linker knows to make them odd | |
16798 | again. */ | |
16799 | ||
16800 | static void | |
17a2f251 | 16801 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16802 | { |
df58fc94 | 16803 | mips_mark_labels (); |
252b5132 RH |
16804 | |
16805 | demand_empty_rest_of_line (); | |
16806 | } | |
16807 | ||
16808 | /* Handle a .stabn directive. We need these in order to mark a label | |
16809 | as being a mips16 text label correctly. Sometimes the compiler | |
16810 | will emit a label, followed by a .stabn, and then switch sections. | |
16811 | If the label and .stabn are in mips16 mode, then the label is | |
16812 | really a mips16 text label. */ | |
16813 | ||
16814 | static void | |
17a2f251 | 16815 | s_mips_stab (int type) |
252b5132 | 16816 | { |
f9419b05 | 16817 | if (type == 'n') |
df58fc94 | 16818 | mips_mark_labels (); |
252b5132 RH |
16819 | |
16820 | s_stab (type); | |
16821 | } | |
16822 | ||
54f4ddb3 | 16823 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
16824 | |
16825 | static void | |
17a2f251 | 16826 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16827 | { |
16828 | char *name; | |
16829 | int c; | |
16830 | symbolS *symbolP; | |
16831 | expressionS exp; | |
16832 | ||
16833 | name = input_line_pointer; | |
16834 | c = get_symbol_end (); | |
16835 | symbolP = symbol_find_or_make (name); | |
16836 | S_SET_WEAK (symbolP); | |
16837 | *input_line_pointer = c; | |
16838 | ||
16839 | SKIP_WHITESPACE (); | |
16840 | ||
16841 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
16842 | { | |
16843 | if (S_IS_DEFINED (symbolP)) | |
16844 | { | |
20203fb9 | 16845 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
16846 | S_GET_NAME (symbolP)); |
16847 | ignore_rest_of_line (); | |
16848 | return; | |
16849 | } | |
bdaaa2e1 | 16850 | |
252b5132 RH |
16851 | if (*input_line_pointer == ',') |
16852 | { | |
16853 | ++input_line_pointer; | |
16854 | SKIP_WHITESPACE (); | |
16855 | } | |
bdaaa2e1 | 16856 | |
252b5132 RH |
16857 | expression (&exp); |
16858 | if (exp.X_op != O_symbol) | |
16859 | { | |
20203fb9 | 16860 | as_bad (_("bad .weakext directive")); |
98d3f06f | 16861 | ignore_rest_of_line (); |
252b5132 RH |
16862 | return; |
16863 | } | |
49309057 | 16864 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
16865 | } |
16866 | ||
16867 | demand_empty_rest_of_line (); | |
16868 | } | |
16869 | ||
16870 | /* Parse a register string into a number. Called from the ECOFF code | |
16871 | to parse .frame. The argument is non-zero if this is the frame | |
16872 | register, so that we can record it in mips_frame_reg. */ | |
16873 | ||
16874 | int | |
17a2f251 | 16875 | tc_get_register (int frame) |
252b5132 | 16876 | { |
707bfff6 | 16877 | unsigned int reg; |
252b5132 RH |
16878 | |
16879 | SKIP_WHITESPACE (); | |
707bfff6 TS |
16880 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
16881 | reg = 0; | |
252b5132 | 16882 | if (frame) |
7a621144 DJ |
16883 | { |
16884 | mips_frame_reg = reg != 0 ? reg : SP; | |
16885 | mips_frame_reg_valid = 1; | |
16886 | mips_cprestore_valid = 0; | |
16887 | } | |
252b5132 RH |
16888 | return reg; |
16889 | } | |
16890 | ||
16891 | valueT | |
17a2f251 | 16892 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
16893 | { |
16894 | int align = bfd_get_section_alignment (stdoutput, seg); | |
16895 | ||
b4c71f56 TS |
16896 | if (IS_ELF) |
16897 | { | |
16898 | /* We don't need to align ELF sections to the full alignment. | |
16899 | However, Irix 5 may prefer that we align them at least to a 16 | |
16900 | byte boundary. We don't bother to align the sections if we | |
16901 | are targeted for an embedded system. */ | |
c41e87e3 | 16902 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
16903 | return addr; |
16904 | if (align > 4) | |
16905 | align = 4; | |
16906 | } | |
252b5132 RH |
16907 | |
16908 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
16909 | } | |
16910 | ||
16911 | /* Utility routine, called from above as well. If called while the | |
16912 | input file is still being read, it's only an approximation. (For | |
16913 | example, a symbol may later become defined which appeared to be | |
16914 | undefined earlier.) */ | |
16915 | ||
16916 | static int | |
17a2f251 | 16917 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
16918 | { |
16919 | if (sym == 0) | |
16920 | return 0; | |
16921 | ||
4d0d148d | 16922 | if (g_switch_value > 0) |
252b5132 RH |
16923 | { |
16924 | const char *symname; | |
16925 | int change; | |
16926 | ||
c9914766 | 16927 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
16928 | register. It can be if it is smaller than the -G size or if |
16929 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 16930 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
16931 | they can. */ |
16932 | symname = S_GET_NAME (sym); | |
16933 | if (symname != (const char *) NULL | |
16934 | && (strcmp (symname, "eprol") == 0 | |
16935 | || strcmp (symname, "etext") == 0 | |
16936 | || strcmp (symname, "_gp") == 0 | |
16937 | || strcmp (symname, "edata") == 0 | |
16938 | || strcmp (symname, "_fbss") == 0 | |
16939 | || strcmp (symname, "_fdata") == 0 | |
16940 | || strcmp (symname, "_ftext") == 0 | |
16941 | || strcmp (symname, "end") == 0 | |
16942 | || strcmp (symname, "_gp_disp") == 0)) | |
16943 | change = 1; | |
16944 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
16945 | && (0 | |
16946 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
16947 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
16948 | && (symbol_get_obj (sym)->ecoff_extern_size | |
16949 | <= g_switch_value)) | |
252b5132 RH |
16950 | #endif |
16951 | /* We must defer this decision until after the whole | |
16952 | file has been read, since there might be a .extern | |
16953 | after the first use of this symbol. */ | |
16954 | || (before_relaxing | |
16955 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 16956 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
16957 | #endif |
16958 | && S_GET_VALUE (sym) == 0) | |
16959 | || (S_GET_VALUE (sym) != 0 | |
16960 | && S_GET_VALUE (sym) <= g_switch_value))) | |
16961 | change = 0; | |
16962 | else | |
16963 | { | |
16964 | const char *segname; | |
16965 | ||
16966 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 16967 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
16968 | && strcmp (segname, ".lit4") != 0); |
16969 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
16970 | && strcmp (segname, ".sbss") != 0 |
16971 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
16972 | && strncmp (segname, ".sbss.", 6) != 0 |
16973 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 16974 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
16975 | } |
16976 | return change; | |
16977 | } | |
16978 | else | |
c9914766 | 16979 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
16980 | return 1; |
16981 | } | |
16982 | ||
5919d012 RS |
16983 | |
16984 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
16985 | ||
16986 | static bfd_boolean | |
17a2f251 | 16987 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
16988 | { |
16989 | asection *symsec; | |
5919d012 RS |
16990 | |
16991 | /* Handle the case of a symbol equated to another symbol. */ | |
16992 | while (symbol_equated_reloc_p (sym)) | |
16993 | { | |
16994 | symbolS *n; | |
16995 | ||
5f0fe04b | 16996 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
16997 | n = symbol_get_value_expression (sym)->X_add_symbol; |
16998 | if (n == sym) | |
16999 | break; | |
17000 | sym = n; | |
17001 | } | |
17002 | ||
df1f3cda DD |
17003 | if (symbol_section_p (sym)) |
17004 | return TRUE; | |
17005 | ||
5919d012 RS |
17006 | symsec = S_GET_SEGMENT (sym); |
17007 | ||
5919d012 RS |
17008 | /* This must duplicate the test in adjust_reloc_syms. */ |
17009 | return (symsec != &bfd_und_section | |
17010 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
17011 | && !bfd_is_com_section (symsec) |
17012 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
17013 | #ifdef OBJ_ELF |
17014 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 17015 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
17016 | #endif |
17017 | ); | |
17018 | } | |
17019 | ||
17020 | ||
252b5132 RH |
17021 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17022 | extended opcode. SEC is the section the frag is in. */ | |
17023 | ||
17024 | static int | |
17a2f251 | 17025 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17026 | { |
17027 | int type; | |
3994f87e | 17028 | const struct mips16_immed_operand *op; |
252b5132 RH |
17029 | offsetT val; |
17030 | int mintiny, maxtiny; | |
17031 | segT symsec; | |
98aa84af | 17032 | fragS *sym_frag; |
252b5132 RH |
17033 | |
17034 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17035 | return 0; | |
17036 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17037 | return 1; | |
17038 | ||
17039 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17040 | op = mips16_immed_operands; | |
17041 | while (op->type != type) | |
17042 | { | |
17043 | ++op; | |
9c2799c2 | 17044 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17045 | } |
17046 | ||
17047 | if (op->unsp) | |
17048 | { | |
17049 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17050 | { | |
17051 | mintiny = 1; | |
17052 | maxtiny = 1 << op->nbits; | |
17053 | } | |
17054 | else | |
17055 | { | |
17056 | mintiny = 0; | |
17057 | maxtiny = (1 << op->nbits) - 1; | |
17058 | } | |
17059 | } | |
17060 | else | |
17061 | { | |
17062 | mintiny = - (1 << (op->nbits - 1)); | |
17063 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17064 | } | |
17065 | ||
98aa84af | 17066 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17067 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17068 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17069 | |
17070 | if (op->pcrel) | |
17071 | { | |
17072 | addressT addr; | |
17073 | ||
17074 | /* We won't have the section when we are called from | |
17075 | mips_relax_frag. However, we will always have been called | |
17076 | from md_estimate_size_before_relax first. If this is a | |
17077 | branch to a different section, we mark it as such. If SEC is | |
17078 | NULL, and the frag is not marked, then it must be a branch to | |
17079 | the same section. */ | |
17080 | if (sec == NULL) | |
17081 | { | |
17082 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17083 | return 1; | |
17084 | } | |
17085 | else | |
17086 | { | |
98aa84af | 17087 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17088 | if (symsec != sec) |
17089 | { | |
17090 | fragp->fr_subtype = | |
17091 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17092 | ||
17093 | /* FIXME: We should support this, and let the linker | |
17094 | catch branches and loads that are out of range. */ | |
17095 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17096 | _("unsupported PC relative reference to different section")); | |
17097 | ||
17098 | return 1; | |
17099 | } | |
98aa84af AM |
17100 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17101 | /* Assume non-extended on the first relaxation pass. | |
17102 | The address we have calculated will be bogus if this is | |
17103 | a forward branch to another frag, as the forward frag | |
17104 | will have fr_address == 0. */ | |
17105 | return 0; | |
252b5132 RH |
17106 | } |
17107 | ||
17108 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17109 | the same section. If the relax_marker of the symbol fragment |
17110 | differs from the relax_marker of this fragment, we have not | |
17111 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17112 | in STRETCH in order to get a better estimate of the address. |
17113 | This particularly matters because of the shift bits. */ | |
17114 | if (stretch != 0 | |
98aa84af | 17115 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17116 | { |
17117 | fragS *f; | |
17118 | ||
17119 | /* Adjust stretch for any alignment frag. Note that if have | |
17120 | been expanding the earlier code, the symbol may be | |
17121 | defined in what appears to be an earlier frag. FIXME: | |
17122 | This doesn't handle the fr_subtype field, which specifies | |
17123 | a maximum number of bytes to skip when doing an | |
17124 | alignment. */ | |
98aa84af | 17125 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17126 | { |
17127 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17128 | { | |
17129 | if (stretch < 0) | |
17130 | stretch = - ((- stretch) | |
17131 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17132 | else | |
17133 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17134 | if (stretch == 0) | |
17135 | break; | |
17136 | } | |
17137 | } | |
17138 | if (f != NULL) | |
17139 | val += stretch; | |
17140 | } | |
17141 | ||
17142 | addr = fragp->fr_address + fragp->fr_fix; | |
17143 | ||
17144 | /* The base address rules are complicated. The base address of | |
17145 | a branch is the following instruction. The base address of a | |
17146 | PC relative load or add is the instruction itself, but if it | |
17147 | is in a delay slot (in which case it can not be extended) use | |
17148 | the address of the instruction whose delay slot it is in. */ | |
17149 | if (type == 'p' || type == 'q') | |
17150 | { | |
17151 | addr += 2; | |
17152 | ||
17153 | /* If we are currently assuming that this frag should be | |
17154 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17155 | higher. */ |
252b5132 RH |
17156 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17157 | addr += 2; | |
17158 | ||
17159 | /* Ignore the low bit in the target, since it will be set | |
17160 | for a text label. */ | |
17161 | if ((val & 1) != 0) | |
17162 | --val; | |
17163 | } | |
17164 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17165 | addr -= 4; | |
17166 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17167 | addr -= 2; | |
17168 | ||
17169 | val -= addr & ~ ((1 << op->shift) - 1); | |
17170 | ||
17171 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17172 | if (type == 'p' || type == 'q') | |
17173 | val /= 2; | |
17174 | ||
17175 | /* If any of the shifted bits are set, we must use an extended | |
17176 | opcode. If the address depends on the size of this | |
17177 | instruction, this can lead to a loop, so we arrange to always | |
17178 | use an extended opcode. We only check this when we are in | |
17179 | the main relaxation loop, when SEC is NULL. */ | |
17180 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17181 | { | |
17182 | fragp->fr_subtype = | |
17183 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17184 | return 1; | |
17185 | } | |
17186 | ||
17187 | /* If we are about to mark a frag as extended because the value | |
17188 | is precisely maxtiny + 1, then there is a chance of an | |
17189 | infinite loop as in the following code: | |
17190 | la $4,foo | |
17191 | .skip 1020 | |
17192 | .align 2 | |
17193 | foo: | |
17194 | In this case when the la is extended, foo is 0x3fc bytes | |
17195 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17196 | the la must be extended. To avoid this loop, we mark the | |
17197 | frag as extended if it was small, and is about to become | |
17198 | extended with a value of maxtiny + 1. */ | |
17199 | if (val == ((maxtiny + 1) << op->shift) | |
17200 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17201 | && sec == NULL) | |
17202 | { | |
17203 | fragp->fr_subtype = | |
17204 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17205 | return 1; | |
17206 | } | |
17207 | } | |
17208 | else if (symsec != absolute_section && sec != NULL) | |
17209 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17210 | ||
17211 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17212 | || val < (mintiny << op->shift) | |
17213 | || val > (maxtiny << op->shift)) | |
17214 | return 1; | |
17215 | else | |
17216 | return 0; | |
17217 | } | |
17218 | ||
4a6a3df4 AO |
17219 | /* Compute the length of a branch sequence, and adjust the |
17220 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17221 | worst-case length is computed, with UPDATE being used to indicate | |
17222 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17223 | branch is to be computed. */ | |
17224 | static int | |
17a2f251 | 17225 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17226 | { |
b34976b6 | 17227 | bfd_boolean toofar; |
4a6a3df4 AO |
17228 | int length; |
17229 | ||
17230 | if (fragp | |
17231 | && S_IS_DEFINED (fragp->fr_symbol) | |
17232 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17233 | { | |
17234 | addressT addr; | |
17235 | offsetT val; | |
17236 | ||
17237 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17238 | ||
17239 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17240 | ||
17241 | val -= addr; | |
17242 | ||
17243 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17244 | } | |
17245 | else if (fragp) | |
17246 | /* If the symbol is not defined or it's in a different segment, | |
17247 | assume the user knows what's going on and emit a short | |
17248 | branch. */ | |
b34976b6 | 17249 | toofar = FALSE; |
4a6a3df4 | 17250 | else |
b34976b6 | 17251 | toofar = TRUE; |
4a6a3df4 AO |
17252 | |
17253 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17254 | fragp->fr_subtype | |
66b3e8da MR |
17255 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17256 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17257 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17258 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17259 | toofar); | |
17260 | ||
17261 | length = 4; | |
17262 | if (toofar) | |
17263 | { | |
17264 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17265 | length += 8; | |
17266 | ||
17267 | if (mips_pic != NO_PIC) | |
17268 | { | |
17269 | /* Additional space for PIC loading of target address. */ | |
17270 | length += 8; | |
17271 | if (mips_opts.isa == ISA_MIPS1) | |
17272 | /* Additional space for $at-stabilizing nop. */ | |
17273 | length += 4; | |
17274 | } | |
17275 | ||
17276 | /* If branch is conditional. */ | |
17277 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17278 | length += 8; | |
17279 | } | |
b34976b6 | 17280 | |
4a6a3df4 AO |
17281 | return length; |
17282 | } | |
17283 | ||
df58fc94 RS |
17284 | /* Compute the length of a branch sequence, and adjust the |
17285 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17286 | worst-case length is computed, with UPDATE being used to indicate | |
17287 | whether an unconditional (-1), or regular (0) branch is to be | |
17288 | computed. */ | |
17289 | ||
17290 | static int | |
17291 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17292 | { | |
17293 | bfd_boolean toofar; | |
17294 | int length; | |
17295 | ||
17296 | if (fragp | |
17297 | && S_IS_DEFINED (fragp->fr_symbol) | |
17298 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17299 | { | |
17300 | addressT addr; | |
17301 | offsetT val; | |
17302 | ||
17303 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17304 | /* Ignore the low bit in the target, since it will be set | |
17305 | for a text label. */ | |
17306 | if ((val & 1) != 0) | |
17307 | --val; | |
17308 | ||
17309 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17310 | ||
17311 | val -= addr; | |
17312 | ||
17313 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17314 | } | |
17315 | else if (fragp) | |
17316 | /* If the symbol is not defined or it's in a different segment, | |
17317 | assume the user knows what's going on and emit a short | |
17318 | branch. */ | |
17319 | toofar = FALSE; | |
17320 | else | |
17321 | toofar = TRUE; | |
17322 | ||
17323 | if (fragp && update | |
17324 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17325 | fragp->fr_subtype = (toofar | |
17326 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17327 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17328 | ||
17329 | length = 4; | |
17330 | if (toofar) | |
17331 | { | |
17332 | bfd_boolean compact_known = fragp != NULL; | |
17333 | bfd_boolean compact = FALSE; | |
17334 | bfd_boolean uncond; | |
17335 | ||
17336 | if (compact_known) | |
17337 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17338 | if (fragp) | |
17339 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17340 | else | |
17341 | uncond = update < 0; | |
17342 | ||
17343 | /* If label is out of range, we turn branch <br>: | |
17344 | ||
17345 | <br> label # 4 bytes | |
17346 | 0: | |
17347 | ||
17348 | into: | |
17349 | ||
17350 | j label # 4 bytes | |
17351 | nop # 2 bytes if compact && !PIC | |
17352 | 0: | |
17353 | */ | |
17354 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17355 | length += 2; | |
17356 | ||
17357 | /* If assembling PIC code, we further turn: | |
17358 | ||
17359 | j label # 4 bytes | |
17360 | ||
17361 | into: | |
17362 | ||
17363 | lw/ld at, %got(label)(gp) # 4 bytes | |
17364 | d/addiu at, %lo(label) # 4 bytes | |
17365 | jr/c at # 2 bytes | |
17366 | */ | |
17367 | if (mips_pic != NO_PIC) | |
17368 | length += 6; | |
17369 | ||
17370 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17371 | ||
17372 | <brneg> 0f # 4 bytes | |
17373 | nop # 2 bytes if !compact | |
17374 | */ | |
17375 | if (!uncond) | |
17376 | length += (compact_known && compact) ? 4 : 6; | |
17377 | } | |
17378 | ||
17379 | return length; | |
17380 | } | |
17381 | ||
17382 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17383 | bit accordingly. */ | |
17384 | ||
17385 | static int | |
17386 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17387 | { | |
17388 | bfd_boolean toofar; | |
17389 | ||
df58fc94 RS |
17390 | if (fragp |
17391 | && S_IS_DEFINED (fragp->fr_symbol) | |
17392 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17393 | { | |
17394 | addressT addr; | |
17395 | offsetT val; | |
17396 | int type; | |
17397 | ||
17398 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17399 | /* Ignore the low bit in the target, since it will be set | |
17400 | for a text label. */ | |
17401 | if ((val & 1) != 0) | |
17402 | --val; | |
17403 | ||
17404 | /* Assume this is a 2-byte branch. */ | |
17405 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17406 | ||
17407 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17408 | long branches. */ | |
17409 | ||
17410 | val -= addr; | |
17411 | ||
17412 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17413 | if (type == 'D') | |
17414 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17415 | else if (type == 'E') | |
17416 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17417 | else | |
17418 | abort (); | |
17419 | } | |
17420 | else | |
17421 | /* If the symbol is not defined or it's in a different segment, | |
17422 | we emit a normal 32-bit branch. */ | |
17423 | toofar = TRUE; | |
17424 | ||
17425 | if (fragp && update | |
17426 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17427 | fragp->fr_subtype | |
17428 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17429 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17430 | ||
17431 | if (toofar) | |
17432 | return 4; | |
17433 | ||
17434 | return 2; | |
17435 | } | |
17436 | ||
252b5132 RH |
17437 | /* Estimate the size of a frag before relaxing. Unless this is the |
17438 | mips16, we are not really relaxing here, and the final size is | |
17439 | encoded in the subtype information. For the mips16, we have to | |
17440 | decide whether we are using an extended opcode or not. */ | |
17441 | ||
252b5132 | 17442 | int |
17a2f251 | 17443 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17444 | { |
5919d012 | 17445 | int change; |
252b5132 | 17446 | |
4a6a3df4 AO |
17447 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17448 | { | |
17449 | ||
b34976b6 AM |
17450 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17451 | ||
4a6a3df4 AO |
17452 | return fragp->fr_var; |
17453 | } | |
17454 | ||
252b5132 | 17455 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17456 | /* We don't want to modify the EXTENDED bit here; it might get us |
17457 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17458 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17459 | |
df58fc94 RS |
17460 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17461 | { | |
17462 | int length = 4; | |
17463 | ||
17464 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17465 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17466 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17467 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17468 | fragp->fr_var = length; | |
17469 | ||
17470 | return length; | |
17471 | } | |
17472 | ||
252b5132 | 17473 | if (mips_pic == NO_PIC) |
5919d012 | 17474 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17475 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17476 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17477 | else if (mips_pic == VXWORKS_PIC) |
17478 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17479 | change = 0; | |
252b5132 RH |
17480 | else |
17481 | abort (); | |
17482 | ||
17483 | if (change) | |
17484 | { | |
4d7206a2 | 17485 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17486 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17487 | } |
4d7206a2 RS |
17488 | else |
17489 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17490 | } |
17491 | ||
17492 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17493 | should be converted into a reloc against a section. */ |
252b5132 RH |
17494 | |
17495 | int | |
17a2f251 | 17496 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17497 | { |
252b5132 RH |
17498 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17499 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17500 | return 0; | |
a161fe53 | 17501 | |
252b5132 RH |
17502 | if (fixp->fx_addsy == NULL) |
17503 | return 1; | |
a161fe53 | 17504 | |
de7e6852 RS |
17505 | /* If symbol SYM is in a mergeable section, relocations of the form |
17506 | SYM + 0 can usually be made section-relative. The mergeable data | |
17507 | is then identified by the section offset rather than by the symbol. | |
17508 | ||
17509 | However, if we're generating REL LO16 relocations, the offset is split | |
17510 | between the LO16 and parterning high part relocation. The linker will | |
17511 | need to recalculate the complete offset in order to correctly identify | |
17512 | the merge data. | |
17513 | ||
17514 | The linker has traditionally not looked for the parterning high part | |
17515 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17516 | placed anywhere. Rather than break backwards compatibility by changing | |
17517 | this, it seems better not to force the issue, and instead keep the | |
17518 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17519 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17520 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17521 | && HAVE_IN_PLACE_ADDENDS |
17522 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17523 | return 0; | |
17524 | ||
ce70d90a MR |
17525 | /* There is no place to store an in-place offset for JALR relocations. |
17526 | Likewise an in-range offset of PC-relative relocations may overflow | |
17527 | the in-place relocatable field if recalculated against the start | |
17528 | address of the symbol's containing section. */ | |
17529 | if (HAVE_IN_PLACE_ADDENDS | |
df58fc94 | 17530 | && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type))) |
1180b5a4 RS |
17531 | return 0; |
17532 | ||
252b5132 | 17533 | #ifdef OBJ_ELF |
b314ec0e RS |
17534 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17535 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17536 | relocations against MIPS16 functions; in this case, the stub becomes | |
17537 | the function's canonical address. | |
17538 | ||
17539 | Floating-point stubs are stored in unique .mips16.call.* or | |
17540 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17541 | the first relocation in section S must be against F; this is how the | |
17542 | linker determines the target function. All relocations that might | |
17543 | resolve to T must also be against F. We therefore have the following | |
17544 | restrictions, which are given in an intentionally-redundant way: | |
17545 | ||
17546 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17547 | symbols. | |
17548 | ||
17549 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17550 | if that stub might be used. | |
17551 | ||
17552 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17553 | symbols. | |
17554 | ||
17555 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17556 | that stub might be used. | |
17557 | ||
17558 | There is a further restriction: | |
17559 | ||
df58fc94 RS |
17560 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17561 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17562 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17563 | encode the low bit. |
17564 | ||
df58fc94 RS |
17565 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17566 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17567 | such relocations on REL targets. | |
b314ec0e RS |
17568 | |
17569 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17570 | relocation against some symbol R, no relocation against R may be | |
17571 | reduced. (Note that this deals with (2) as well as (1) because | |
17572 | relocations against global symbols will never be reduced on ELF | |
17573 | targets.) This approach is a little simpler than trying to detect | |
17574 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17575 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17576 | if (IS_ELF |
b314ec0e | 17577 | && fixp->fx_subsy == NULL |
30c09090 | 17578 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17579 | || *symbol_get_tc (fixp->fx_addsy) |
17580 | || (HAVE_IN_PLACE_ADDENDS | |
17581 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17582 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17583 | return 0; |
17584 | #endif | |
a161fe53 | 17585 | |
252b5132 RH |
17586 | return 1; |
17587 | } | |
17588 | ||
17589 | /* Translate internal representation of relocation info to BFD target | |
17590 | format. */ | |
17591 | ||
17592 | arelent ** | |
17a2f251 | 17593 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17594 | { |
17595 | static arelent *retval[4]; | |
17596 | arelent *reloc; | |
17597 | bfd_reloc_code_real_type code; | |
17598 | ||
4b0cff4e TS |
17599 | memset (retval, 0, sizeof(retval)); |
17600 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17601 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17602 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17603 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17604 | ||
bad36eac DJ |
17605 | if (fixp->fx_pcrel) |
17606 | { | |
df58fc94 RS |
17607 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17608 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17609 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17610 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17611 | |
17612 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17613 | Relocations want only the symbol offset. */ | |
17614 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17615 | if (!IS_ELF) |
bad36eac DJ |
17616 | { |
17617 | /* A gruesome hack which is a result of the gruesome gas | |
17618 | reloc handling. What's worse, for COFF (as opposed to | |
17619 | ECOFF), we might need yet another copy of reloc->address. | |
17620 | See bfd_install_relocation. */ | |
17621 | reloc->addend += reloc->address; | |
17622 | } | |
17623 | } | |
17624 | else | |
17625 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17626 | |
438c16b8 TS |
17627 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17628 | entry to be used in the relocation's section offset. */ | |
17629 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17630 | { |
17631 | reloc->address = reloc->addend; | |
17632 | reloc->addend = 0; | |
17633 | } | |
17634 | ||
252b5132 | 17635 | code = fixp->fx_r_type; |
252b5132 | 17636 | |
bad36eac | 17637 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17638 | if (reloc->howto == NULL) |
17639 | { | |
17640 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17641 | _("Can not represent %s relocation in this object file format"), | |
17642 | bfd_get_reloc_code_name (code)); | |
17643 | retval[0] = NULL; | |
17644 | } | |
17645 | ||
17646 | return retval; | |
17647 | } | |
17648 | ||
17649 | /* Relax a machine dependent frag. This returns the amount by which | |
17650 | the current size of the frag should change. */ | |
17651 | ||
17652 | int | |
17a2f251 | 17653 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17654 | { |
4a6a3df4 AO |
17655 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17656 | { | |
17657 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17658 | |
17659 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17660 | |
17661 | return fragp->fr_var - old_var; | |
17662 | } | |
17663 | ||
df58fc94 RS |
17664 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17665 | { | |
17666 | offsetT old_var = fragp->fr_var; | |
17667 | offsetT new_var = 4; | |
17668 | ||
17669 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17670 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17671 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17672 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17673 | fragp->fr_var = new_var; | |
17674 | ||
17675 | return new_var - old_var; | |
17676 | } | |
17677 | ||
252b5132 RH |
17678 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17679 | return 0; | |
17680 | ||
c4e7957c | 17681 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17682 | { |
17683 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17684 | return 0; | |
17685 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17686 | return 2; | |
17687 | } | |
17688 | else | |
17689 | { | |
17690 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17691 | return 0; | |
17692 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17693 | return -2; | |
17694 | } | |
17695 | ||
17696 | return 0; | |
17697 | } | |
17698 | ||
17699 | /* Convert a machine dependent frag. */ | |
17700 | ||
17701 | void | |
17a2f251 | 17702 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17703 | { |
4a6a3df4 AO |
17704 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17705 | { | |
17706 | bfd_byte *buf; | |
17707 | unsigned long insn; | |
17708 | expressionS exp; | |
17709 | fixS *fixp; | |
b34976b6 | 17710 | |
4a6a3df4 AO |
17711 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
17712 | ||
17713 | if (target_big_endian) | |
17714 | insn = bfd_getb32 (buf); | |
17715 | else | |
17716 | insn = bfd_getl32 (buf); | |
b34976b6 | 17717 | |
4a6a3df4 AO |
17718 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17719 | { | |
17720 | /* We generate a fixup instead of applying it right now | |
17721 | because, if there are linker relaxations, we're going to | |
17722 | need the relocations. */ | |
17723 | exp.X_op = O_symbol; | |
17724 | exp.X_add_symbol = fragp->fr_symbol; | |
17725 | exp.X_add_number = fragp->fr_offset; | |
17726 | ||
17727 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17728 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
17729 | fixp->fx_file = fragp->fr_file; |
17730 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17731 | |
2132e3a3 | 17732 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17733 | buf += 4; |
17734 | } | |
17735 | else | |
17736 | { | |
17737 | int i; | |
17738 | ||
17739 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 17740 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
17741 | |
17742 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
17743 | goto uncond; | |
17744 | ||
17745 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17746 | { | |
17747 | /* Reverse the branch. */ | |
17748 | switch ((insn >> 28) & 0xf) | |
17749 | { | |
17750 | case 4: | |
17751 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
17752 | have the condition reversed by tweaking a single | |
17753 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 17754 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
17755 | insn ^= 0x00010000; |
17756 | break; | |
17757 | ||
17758 | case 0: | |
17759 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 17760 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 17761 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
17762 | insn ^= 0x00010000; |
17763 | break; | |
b34976b6 | 17764 | |
4a6a3df4 AO |
17765 | case 1: |
17766 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 17767 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
17768 | insn ^= 0x04000000; |
17769 | break; | |
17770 | ||
17771 | default: | |
17772 | abort (); | |
17773 | } | |
17774 | } | |
17775 | ||
17776 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
17777 | { | |
17778 | /* Clear the and-link bit. */ | |
9c2799c2 | 17779 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 17780 | |
54f4ddb3 TS |
17781 | /* bltzal 0x04100000 bgezal 0x04110000 |
17782 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
17783 | insn &= ~0x00100000; |
17784 | } | |
17785 | ||
17786 | /* Branch over the branch (if the branch was likely) or the | |
17787 | full jump (not likely case). Compute the offset from the | |
17788 | current instruction to branch to. */ | |
17789 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17790 | i = 16; | |
17791 | else | |
17792 | { | |
17793 | /* How many bytes in instructions we've already emitted? */ | |
17794 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17795 | /* How many bytes in instructions from here to the end? */ | |
17796 | i = fragp->fr_var - i; | |
17797 | } | |
17798 | /* Convert to instruction count. */ | |
17799 | i >>= 2; | |
17800 | /* Branch counts from the next instruction. */ | |
b34976b6 | 17801 | i--; |
4a6a3df4 AO |
17802 | insn |= i; |
17803 | /* Branch over the jump. */ | |
2132e3a3 | 17804 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17805 | buf += 4; |
17806 | ||
54f4ddb3 | 17807 | /* nop */ |
2132e3a3 | 17808 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17809 | buf += 4; |
17810 | ||
17811 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17812 | { | |
17813 | /* beql $0, $0, 2f */ | |
17814 | insn = 0x50000000; | |
17815 | /* Compute the PC offset from the current instruction to | |
17816 | the end of the variable frag. */ | |
17817 | /* How many bytes in instructions we've already emitted? */ | |
17818 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17819 | /* How many bytes in instructions from here to the end? */ | |
17820 | i = fragp->fr_var - i; | |
17821 | /* Convert to instruction count. */ | |
17822 | i >>= 2; | |
17823 | /* Don't decrement i, because we want to branch over the | |
17824 | delay slot. */ | |
17825 | ||
17826 | insn |= i; | |
2132e3a3 | 17827 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17828 | buf += 4; |
17829 | ||
2132e3a3 | 17830 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17831 | buf += 4; |
17832 | } | |
17833 | ||
17834 | uncond: | |
17835 | if (mips_pic == NO_PIC) | |
17836 | { | |
17837 | /* j or jal. */ | |
17838 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
17839 | ? 0x0c000000 : 0x08000000); | |
17840 | exp.X_op = O_symbol; | |
17841 | exp.X_add_symbol = fragp->fr_symbol; | |
17842 | exp.X_add_number = fragp->fr_offset; | |
17843 | ||
17844 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17845 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
17846 | fixp->fx_file = fragp->fr_file; |
17847 | fixp->fx_line = fragp->fr_line; | |
17848 | ||
2132e3a3 | 17849 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17850 | buf += 4; |
17851 | } | |
17852 | else | |
17853 | { | |
66b3e8da MR |
17854 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
17855 | ||
4a6a3df4 | 17856 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
17857 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
17858 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
17859 | exp.X_op = O_symbol; |
17860 | exp.X_add_symbol = fragp->fr_symbol; | |
17861 | exp.X_add_number = fragp->fr_offset; | |
17862 | ||
17863 | if (fragp->fr_offset) | |
17864 | { | |
17865 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17866 | exp.X_add_number = 0; | |
17867 | } | |
17868 | ||
17869 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17870 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
17871 | fixp->fx_file = fragp->fr_file; |
17872 | fixp->fx_line = fragp->fr_line; | |
17873 | ||
2132e3a3 | 17874 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 17875 | buf += 4; |
b34976b6 | 17876 | |
4a6a3df4 AO |
17877 | if (mips_opts.isa == ISA_MIPS1) |
17878 | { | |
17879 | /* nop */ | |
2132e3a3 | 17880 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17881 | buf += 4; |
17882 | } | |
17883 | ||
17884 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
17885 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
17886 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
17887 | |
17888 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17889 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
17890 | fixp->fx_file = fragp->fr_file; |
17891 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17892 | |
2132e3a3 | 17893 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17894 | buf += 4; |
17895 | ||
17896 | /* j(al)r $at. */ | |
17897 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 17898 | insn = 0x0000f809; |
4a6a3df4 | 17899 | else |
66b3e8da MR |
17900 | insn = 0x00000008; |
17901 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 17902 | |
2132e3a3 | 17903 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17904 | buf += 4; |
17905 | } | |
17906 | } | |
17907 | ||
9c2799c2 | 17908 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
17909 | + fragp->fr_fix + fragp->fr_var); |
17910 | ||
17911 | fragp->fr_fix += fragp->fr_var; | |
17912 | ||
17913 | return; | |
17914 | } | |
17915 | ||
df58fc94 RS |
17916 | /* Relax microMIPS branches. */ |
17917 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
17918 | { | |
17919 | bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
17920 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17921 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
17922 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 17923 | bfd_boolean short_ds; |
df58fc94 RS |
17924 | unsigned long insn; |
17925 | expressionS exp; | |
17926 | fixS *fixp; | |
17927 | ||
17928 | exp.X_op = O_symbol; | |
17929 | exp.X_add_symbol = fragp->fr_symbol; | |
17930 | exp.X_add_number = fragp->fr_offset; | |
17931 | ||
17932 | fragp->fr_fix += fragp->fr_var; | |
17933 | ||
17934 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
17935 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17936 | { | |
17937 | /* We generate a fixup instead of applying it right now, | |
17938 | because if there is linker relaxation, we're going to | |
17939 | need the relocations. */ | |
17940 | if (type == 'D') | |
17941 | fixp = fix_new_exp (fragp, | |
17942 | buf - (bfd_byte *) fragp->fr_literal, | |
17943 | 2, &exp, TRUE, | |
17944 | BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
17945 | else if (type == 'E') | |
17946 | fixp = fix_new_exp (fragp, | |
17947 | buf - (bfd_byte *) fragp->fr_literal, | |
17948 | 2, &exp, TRUE, | |
17949 | BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
17950 | else | |
17951 | abort (); | |
17952 | ||
17953 | fixp->fx_file = fragp->fr_file; | |
17954 | fixp->fx_line = fragp->fr_line; | |
17955 | ||
17956 | /* These relocations can have an addend that won't fit in | |
17957 | 2 octets. */ | |
17958 | fixp->fx_no_overflow = 1; | |
17959 | ||
17960 | return; | |
17961 | } | |
17962 | ||
2309ddf2 | 17963 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
17964 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
17965 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17966 | { | |
17967 | /* We generate a fixup instead of applying it right now, | |
17968 | because if there is linker relaxation, we're going to | |
17969 | need the relocations. */ | |
17970 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17971 | 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
17972 | fixp->fx_file = fragp->fr_file; | |
17973 | fixp->fx_line = fragp->fr_line; | |
17974 | ||
17975 | if (type == 0) | |
17976 | return; | |
17977 | } | |
17978 | ||
17979 | /* Relax 16-bit branches to 32-bit branches. */ | |
17980 | if (type != 0) | |
17981 | { | |
17982 | if (target_big_endian) | |
17983 | insn = bfd_getb16 (buf); | |
17984 | else | |
17985 | insn = bfd_getl16 (buf); | |
17986 | ||
17987 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
17988 | insn = 0x94000000; /* beq */ | |
17989 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
17990 | { | |
17991 | unsigned long regno; | |
17992 | ||
17993 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
17994 | regno = micromips_to_32_reg_d_map [regno]; | |
17995 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
17996 | insn |= regno << MICROMIPSOP_SH_RS; | |
17997 | } | |
17998 | else | |
17999 | abort (); | |
18000 | ||
18001 | /* Nothing else to do, just write it out. */ | |
18002 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18003 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18004 | { | |
18005 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18006 | buf += 2; | |
18007 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18008 | buf += 2; | |
18009 | ||
18010 | gas_assert (buf == ((bfd_byte *) fragp->fr_literal | |
18011 | + fragp->fr_fix)); | |
18012 | return; | |
18013 | } | |
18014 | } | |
18015 | else | |
18016 | { | |
18017 | unsigned long next; | |
18018 | ||
18019 | if (target_big_endian) | |
18020 | { | |
18021 | insn = bfd_getb16 (buf); | |
18022 | next = bfd_getb16 (buf + 2); | |
18023 | } | |
18024 | else | |
18025 | { | |
18026 | insn = bfd_getl16 (buf); | |
18027 | next = bfd_getl16 (buf + 2); | |
18028 | } | |
18029 | insn = (insn << 16) | next; | |
18030 | } | |
18031 | ||
18032 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18033 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18034 | _("Relaxed out-of-range branch into a jump")); | |
18035 | ||
2309ddf2 MR |
18036 | /* Set the short-delay-slot bit. */ |
18037 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18038 | |
18039 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18040 | { | |
18041 | symbolS *l; | |
18042 | ||
18043 | /* Reverse the branch. */ | |
18044 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18045 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18046 | insn ^= 0x20000000; | |
18047 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18048 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18049 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18050 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18051 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18052 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18053 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18054 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18055 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18056 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18057 | insn ^= 0x00400000; | |
18058 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18059 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18060 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18061 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18062 | insn ^= 0x00200000; | |
18063 | else | |
18064 | abort (); | |
18065 | ||
18066 | if (al) | |
18067 | { | |
18068 | /* Clear the and-link and short-delay-slot bits. */ | |
18069 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18070 | ||
18071 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18072 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18073 | insn &= ~0x02200000; | |
18074 | } | |
18075 | ||
18076 | /* Make a label at the end for use with the branch. */ | |
18077 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18078 | micromips_label_inc (); | |
18079 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18080 | if (IS_ELF) | |
18081 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18082 | #endif | |
18083 | ||
18084 | /* Refer to it. */ | |
18085 | fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18086 | 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
18087 | fixp->fx_file = fragp->fr_file; | |
18088 | fixp->fx_line = fragp->fr_line; | |
18089 | ||
18090 | /* Branch over the jump. */ | |
18091 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18092 | buf += 2; | |
18093 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18094 | buf += 2; | |
18095 | ||
18096 | if (!compact) | |
18097 | { | |
18098 | /* nop */ | |
18099 | insn = 0x0c00; | |
18100 | md_number_to_chars ((char *) buf, insn, 2); | |
18101 | buf += 2; | |
18102 | } | |
18103 | } | |
18104 | ||
18105 | if (mips_pic == NO_PIC) | |
18106 | { | |
2309ddf2 MR |
18107 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18108 | ||
df58fc94 RS |
18109 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18110 | insn = al ? jal : 0xd4000000; | |
18111 | ||
18112 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18113 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP); | |
18114 | fixp->fx_file = fragp->fr_file; | |
18115 | fixp->fx_line = fragp->fr_line; | |
18116 | ||
18117 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18118 | buf += 2; | |
18119 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18120 | buf += 2; | |
18121 | ||
18122 | if (compact) | |
18123 | { | |
18124 | /* nop */ | |
18125 | insn = 0x0c00; | |
18126 | md_number_to_chars ((char *) buf, insn, 2); | |
18127 | buf += 2; | |
18128 | } | |
18129 | } | |
18130 | else | |
18131 | { | |
18132 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18133 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18134 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18135 | |
18136 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18137 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18138 | insn |= at << MICROMIPSOP_SH_RT; | |
18139 | ||
18140 | if (exp.X_add_number) | |
18141 | { | |
18142 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18143 | exp.X_add_number = 0; | |
18144 | } | |
18145 | ||
18146 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18147 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
18148 | fixp->fx_file = fragp->fr_file; | |
18149 | fixp->fx_line = fragp->fr_line; | |
18150 | ||
18151 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18152 | buf += 2; | |
18153 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18154 | buf += 2; | |
18155 | ||
18156 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18157 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18158 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18159 | ||
18160 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18161 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16); | |
18162 | fixp->fx_file = fragp->fr_file; | |
18163 | fixp->fx_line = fragp->fr_line; | |
18164 | ||
18165 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18166 | buf += 2; | |
18167 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18168 | buf += 2; | |
18169 | ||
18170 | /* jr/jrc/jalr/jalrs $at */ | |
18171 | insn = al ? jalr : jr; | |
18172 | insn |= at << MICROMIPSOP_SH_MJ; | |
18173 | ||
18174 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18175 | buf += 2; | |
18176 | } | |
18177 | ||
18178 | gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix); | |
18179 | return; | |
18180 | } | |
18181 | ||
252b5132 RH |
18182 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18183 | { | |
18184 | int type; | |
3994f87e | 18185 | const struct mips16_immed_operand *op; |
b34976b6 | 18186 | bfd_boolean small, ext; |
252b5132 RH |
18187 | offsetT val; |
18188 | bfd_byte *buf; | |
18189 | unsigned long insn; | |
b34976b6 | 18190 | bfd_boolean use_extend; |
252b5132 RH |
18191 | unsigned short extend; |
18192 | ||
18193 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18194 | op = mips16_immed_operands; | |
18195 | while (op->type != type) | |
18196 | ++op; | |
18197 | ||
18198 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18199 | { | |
b34976b6 AM |
18200 | small = FALSE; |
18201 | ext = TRUE; | |
252b5132 RH |
18202 | } |
18203 | else | |
18204 | { | |
b34976b6 AM |
18205 | small = TRUE; |
18206 | ext = FALSE; | |
252b5132 RH |
18207 | } |
18208 | ||
5f5f22c0 | 18209 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18210 | if (op->pcrel) |
18211 | { | |
18212 | addressT addr; | |
18213 | ||
18214 | addr = fragp->fr_address + fragp->fr_fix; | |
18215 | ||
18216 | /* The rules for the base address of a PC relative reloc are | |
18217 | complicated; see mips16_extended_frag. */ | |
18218 | if (type == 'p' || type == 'q') | |
18219 | { | |
18220 | addr += 2; | |
18221 | if (ext) | |
18222 | addr += 2; | |
18223 | /* Ignore the low bit in the target, since it will be | |
18224 | set for a text label. */ | |
18225 | if ((val & 1) != 0) | |
18226 | --val; | |
18227 | } | |
18228 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18229 | addr -= 4; | |
18230 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18231 | addr -= 2; | |
18232 | ||
18233 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18234 | val -= addr; | |
18235 | ||
18236 | /* Make sure the section winds up with the alignment we have | |
18237 | assumed. */ | |
18238 | if (op->shift > 0) | |
18239 | record_alignment (asec, op->shift); | |
18240 | } | |
18241 | ||
18242 | if (ext | |
18243 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18244 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18245 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18246 | _("extended instruction in delay slot")); | |
18247 | ||
18248 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
18249 | ||
18250 | if (target_big_endian) | |
18251 | insn = bfd_getb16 (buf); | |
18252 | else | |
18253 | insn = bfd_getl16 (buf); | |
18254 | ||
18255 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
18256 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
18257 | small, ext, &insn, &use_extend, &extend); | |
18258 | ||
18259 | if (use_extend) | |
18260 | { | |
2132e3a3 | 18261 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
18262 | fragp->fr_fix += 2; |
18263 | buf += 2; | |
18264 | } | |
18265 | ||
2132e3a3 | 18266 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
18267 | fragp->fr_fix += 2; |
18268 | buf += 2; | |
18269 | } | |
18270 | else | |
18271 | { | |
df58fc94 RS |
18272 | relax_substateT subtype = fragp->fr_subtype; |
18273 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18274 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18275 | int first, second; |
18276 | fixS *fixp; | |
252b5132 | 18277 | |
df58fc94 RS |
18278 | first = RELAX_FIRST (subtype); |
18279 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18280 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18281 | |
df58fc94 RS |
18282 | /* If the delay slot chosen does not match the size of the instruction, |
18283 | then emit a warning. */ | |
18284 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18285 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18286 | { | |
18287 | relax_substateT s; | |
18288 | const char *msg; | |
18289 | ||
18290 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18291 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18292 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18293 | msg = macro_warning (s); | |
18294 | if (msg != NULL) | |
db9b2be4 | 18295 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18296 | subtype &= ~s; |
18297 | } | |
18298 | ||
584892a6 | 18299 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18300 | if (use_second == second_longer) |
584892a6 | 18301 | { |
df58fc94 RS |
18302 | relax_substateT s; |
18303 | const char *msg; | |
18304 | ||
18305 | s = (subtype | |
18306 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18307 | msg = macro_warning (s); | |
18308 | if (msg != NULL) | |
db9b2be4 | 18309 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18310 | subtype &= ~s; |
584892a6 RS |
18311 | } |
18312 | ||
4d7206a2 RS |
18313 | /* Go through all the fixups for the first sequence. Disable them |
18314 | (by marking them as done) if we're going to use the second | |
18315 | sequence instead. */ | |
18316 | while (fixp | |
18317 | && fixp->fx_frag == fragp | |
18318 | && fixp->fx_where < fragp->fr_fix - second) | |
18319 | { | |
df58fc94 | 18320 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18321 | fixp->fx_done = 1; |
18322 | fixp = fixp->fx_next; | |
18323 | } | |
252b5132 | 18324 | |
4d7206a2 RS |
18325 | /* Go through the fixups for the second sequence. Disable them if |
18326 | we're going to use the first sequence, otherwise adjust their | |
18327 | addresses to account for the relaxation. */ | |
18328 | while (fixp && fixp->fx_frag == fragp) | |
18329 | { | |
df58fc94 | 18330 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18331 | fixp->fx_where -= first; |
18332 | else | |
18333 | fixp->fx_done = 1; | |
18334 | fixp = fixp->fx_next; | |
18335 | } | |
18336 | ||
18337 | /* Now modify the frag contents. */ | |
df58fc94 | 18338 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18339 | { |
18340 | char *start; | |
18341 | ||
18342 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18343 | memmove (start, start + first, second); | |
18344 | fragp->fr_fix -= first; | |
18345 | } | |
18346 | else | |
18347 | fragp->fr_fix -= second; | |
252b5132 RH |
18348 | } |
18349 | } | |
18350 | ||
18351 | #ifdef OBJ_ELF | |
18352 | ||
18353 | /* This function is called after the relocs have been generated. | |
18354 | We've been storing mips16 text labels as odd. Here we convert them | |
18355 | back to even for the convenience of the debugger. */ | |
18356 | ||
18357 | void | |
17a2f251 | 18358 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18359 | { |
18360 | asymbol **syms; | |
18361 | unsigned int count, i; | |
18362 | ||
f43abd2b | 18363 | if (!IS_ELF) |
252b5132 RH |
18364 | return; |
18365 | ||
18366 | syms = bfd_get_outsymbols (stdoutput); | |
18367 | count = bfd_get_symcount (stdoutput); | |
18368 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18369 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18370 | && ((*syms)->value & 1) != 0) | |
18371 | { | |
18372 | (*syms)->value &= ~1; | |
18373 | /* If the symbol has an odd size, it was probably computed | |
18374 | incorrectly, so adjust that as well. */ | |
18375 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18376 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18377 | } | |
252b5132 RH |
18378 | } |
18379 | ||
18380 | #endif | |
18381 | ||
a1facbec MR |
18382 | /* This function is called whenever a label is defined, including fake |
18383 | labels instantiated off the dot special symbol. It is used when | |
18384 | handling branch delays; if a branch has a label, we assume we cannot | |
18385 | move it. This also bumps the value of the symbol by 1 in compressed | |
18386 | code. */ | |
252b5132 RH |
18387 | |
18388 | void | |
a1facbec | 18389 | mips_record_label (symbolS *sym) |
252b5132 | 18390 | { |
a8dbcb85 | 18391 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18392 | struct insn_label_list *l; |
18393 | ||
18394 | if (free_insn_labels == NULL) | |
18395 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18396 | else | |
18397 | { | |
18398 | l = free_insn_labels; | |
18399 | free_insn_labels = l->next; | |
18400 | } | |
18401 | ||
18402 | l->label = sym; | |
a8dbcb85 TS |
18403 | l->next = si->label_list; |
18404 | si->label_list = l; | |
a1facbec | 18405 | } |
07a53e5c | 18406 | |
a1facbec MR |
18407 | /* This function is called as tc_frob_label() whenever a label is defined |
18408 | and adds a DWARF-2 record we only want for true labels. */ | |
18409 | ||
18410 | void | |
18411 | mips_define_label (symbolS *sym) | |
18412 | { | |
18413 | mips_record_label (sym); | |
07a53e5c RH |
18414 | #ifdef OBJ_ELF |
18415 | dwarf2_emit_label (sym); | |
18416 | #endif | |
252b5132 RH |
18417 | } |
18418 | \f | |
18419 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18420 | ||
18421 | /* Some special processing for a MIPS ELF file. */ | |
18422 | ||
18423 | void | |
17a2f251 | 18424 | mips_elf_final_processing (void) |
252b5132 RH |
18425 | { |
18426 | /* Write out the register information. */ | |
316f5878 | 18427 | if (mips_abi != N64_ABI) |
252b5132 RH |
18428 | { |
18429 | Elf32_RegInfo s; | |
18430 | ||
18431 | s.ri_gprmask = mips_gprmask; | |
18432 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18433 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18434 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18435 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18436 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18437 | ||
18438 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18439 | ((Elf32_External_RegInfo *) | |
18440 | mips_regmask_frag)); | |
18441 | } | |
18442 | else | |
18443 | { | |
18444 | Elf64_Internal_RegInfo s; | |
18445 | ||
18446 | s.ri_gprmask = mips_gprmask; | |
18447 | s.ri_pad = 0; | |
18448 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18449 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18450 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18451 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18452 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18453 | ||
18454 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18455 | ((Elf64_External_RegInfo *) | |
18456 | mips_regmask_frag)); | |
18457 | } | |
18458 | ||
18459 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18460 | sort of BFD interface for this. */ | |
18461 | if (mips_any_noreorder) | |
18462 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18463 | if (mips_pic != NO_PIC) | |
143d77c5 | 18464 | { |
8b828383 | 18465 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18466 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18467 | } | |
18468 | if (mips_abicalls) | |
18469 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18470 | |
98d3f06f | 18471 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18472 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18473 | file_ase_dsp is true. */ | |
8b082fb1 | 18474 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18475 | /* We may need to define a new flag for MT ASE, and set this flag when |
18476 | file_ase_mt is true. */ | |
a4672219 TS |
18477 | if (file_ase_mips16) |
18478 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18479 | if (file_ase_micromips) |
18480 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18481 | #if 0 /* XXX FIXME */ |
18482 | if (file_ase_mips3d) | |
18483 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18484 | #endif | |
deec1734 CD |
18485 | if (file_ase_mdmx) |
18486 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18487 | |
bdaaa2e1 | 18488 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18489 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18490 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18491 | else if (mips_abi == O64_ABI) |
252b5132 | 18492 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18493 | else if (mips_abi == EABI_ABI) |
252b5132 | 18494 | { |
316f5878 | 18495 | if (!file_mips_gp32) |
252b5132 RH |
18496 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18497 | else | |
18498 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18499 | } | |
316f5878 | 18500 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18501 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18502 | ||
c9914766 | 18503 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18504 | |
18505 | if (mips_32bitmode) | |
18506 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18507 | |
18508 | #if 0 /* XXX FIXME */ | |
18509 | /* 32 bit code with 64 bit FP registers. */ | |
18510 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18511 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18512 | #endif | |
252b5132 RH |
18513 | } |
18514 | ||
18515 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18516 | \f | |
beae10d5 | 18517 | typedef struct proc { |
9b2f1d35 EC |
18518 | symbolS *func_sym; |
18519 | symbolS *func_end_sym; | |
beae10d5 KH |
18520 | unsigned long reg_mask; |
18521 | unsigned long reg_offset; | |
18522 | unsigned long fpreg_mask; | |
18523 | unsigned long fpreg_offset; | |
18524 | unsigned long frame_offset; | |
18525 | unsigned long frame_reg; | |
18526 | unsigned long pc_reg; | |
18527 | } procS; | |
252b5132 RH |
18528 | |
18529 | static procS cur_proc; | |
18530 | static procS *cur_proc_ptr; | |
18531 | static int numprocs; | |
18532 | ||
df58fc94 RS |
18533 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18534 | as "2", and a normal nop as "0". */ | |
18535 | ||
18536 | #define NOP_OPCODE_MIPS 0 | |
18537 | #define NOP_OPCODE_MIPS16 1 | |
18538 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18539 | |
18540 | char | |
18541 | mips_nop_opcode (void) | |
18542 | { | |
df58fc94 RS |
18543 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18544 | return NOP_OPCODE_MICROMIPS; | |
18545 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18546 | return NOP_OPCODE_MIPS16; | |
18547 | else | |
18548 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18549 | } |
18550 | ||
df58fc94 RS |
18551 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18552 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18553 | |
0a9ef439 | 18554 | void |
17a2f251 | 18555 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18556 | { |
df58fc94 | 18557 | char nop_opcode; |
742a56fe | 18558 | char *p; |
c67a084a NC |
18559 | int bytes, size, excess; |
18560 | valueT opcode; | |
742a56fe | 18561 | |
0a9ef439 RH |
18562 | if (fragp->fr_type != rs_align_code) |
18563 | return; | |
18564 | ||
742a56fe | 18565 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18566 | nop_opcode = *p; |
18567 | switch (nop_opcode) | |
a19d8eb0 | 18568 | { |
df58fc94 RS |
18569 | case NOP_OPCODE_MICROMIPS: |
18570 | opcode = micromips_nop32_insn.insn_opcode; | |
18571 | size = 4; | |
18572 | break; | |
18573 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18574 | opcode = mips16_nop_insn.insn_opcode; |
18575 | size = 2; | |
df58fc94 RS |
18576 | break; |
18577 | case NOP_OPCODE_MIPS: | |
18578 | default: | |
c67a084a NC |
18579 | opcode = nop_insn.insn_opcode; |
18580 | size = 4; | |
df58fc94 | 18581 | break; |
c67a084a | 18582 | } |
a19d8eb0 | 18583 | |
c67a084a NC |
18584 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18585 | excess = bytes % size; | |
df58fc94 RS |
18586 | |
18587 | /* Handle the leading part if we're not inserting a whole number of | |
18588 | instructions, and make it the end of the fixed part of the frag. | |
18589 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18590 | and use zeroes otherwise. */ | |
18591 | gas_assert (excess < 4); | |
18592 | fragp->fr_fix += excess; | |
18593 | switch (excess) | |
c67a084a | 18594 | { |
df58fc94 RS |
18595 | case 3: |
18596 | *p++ = '\0'; | |
18597 | /* Fall through. */ | |
18598 | case 2: | |
18599 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18600 | { | |
18601 | md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2); | |
18602 | p += 2; | |
18603 | break; | |
18604 | } | |
18605 | *p++ = '\0'; | |
18606 | /* Fall through. */ | |
18607 | case 1: | |
18608 | *p++ = '\0'; | |
18609 | /* Fall through. */ | |
18610 | case 0: | |
18611 | break; | |
a19d8eb0 | 18612 | } |
c67a084a NC |
18613 | |
18614 | md_number_to_chars (p, opcode, size); | |
18615 | fragp->fr_var = size; | |
a19d8eb0 CP |
18616 | } |
18617 | ||
252b5132 | 18618 | static void |
17a2f251 | 18619 | md_obj_begin (void) |
252b5132 RH |
18620 | { |
18621 | } | |
18622 | ||
18623 | static void | |
17a2f251 | 18624 | md_obj_end (void) |
252b5132 | 18625 | { |
54f4ddb3 | 18626 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18627 | if (cur_proc_ptr) |
9a41af64 | 18628 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18629 | } |
18630 | ||
18631 | static long | |
17a2f251 | 18632 | get_number (void) |
252b5132 RH |
18633 | { |
18634 | int negative = 0; | |
18635 | long val = 0; | |
18636 | ||
18637 | if (*input_line_pointer == '-') | |
18638 | { | |
18639 | ++input_line_pointer; | |
18640 | negative = 1; | |
18641 | } | |
3882b010 | 18642 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18643 | as_bad (_("expected simple number")); |
252b5132 RH |
18644 | if (input_line_pointer[0] == '0') |
18645 | { | |
18646 | if (input_line_pointer[1] == 'x') | |
18647 | { | |
18648 | input_line_pointer += 2; | |
3882b010 | 18649 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18650 | { |
18651 | val <<= 4; | |
18652 | val |= hex_value (*input_line_pointer++); | |
18653 | } | |
18654 | return negative ? -val : val; | |
18655 | } | |
18656 | else | |
18657 | { | |
18658 | ++input_line_pointer; | |
3882b010 | 18659 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18660 | { |
18661 | val <<= 3; | |
18662 | val |= *input_line_pointer++ - '0'; | |
18663 | } | |
18664 | return negative ? -val : val; | |
18665 | } | |
18666 | } | |
3882b010 | 18667 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18668 | { |
18669 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18670 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18671 | as_warn (_("invalid number")); |
252b5132 RH |
18672 | return -1; |
18673 | } | |
3882b010 | 18674 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18675 | { |
18676 | val *= 10; | |
18677 | val += *input_line_pointer++ - '0'; | |
18678 | } | |
18679 | return negative ? -val : val; | |
18680 | } | |
18681 | ||
18682 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18683 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18684 | case .file implies DWARF-2. */ | |
18685 | ||
18686 | static void | |
17a2f251 | 18687 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18688 | { |
ecb4347a DJ |
18689 | static int first_file_directive = 0; |
18690 | ||
c5dd6aab DJ |
18691 | if (ECOFF_DEBUGGING) |
18692 | { | |
18693 | get_number (); | |
18694 | s_app_file (0); | |
18695 | } | |
18696 | else | |
ecb4347a DJ |
18697 | { |
18698 | char *filename; | |
18699 | ||
18700 | filename = dwarf2_directive_file (0); | |
18701 | ||
18702 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18703 | directive even for stabs output. Make sure that this | |
18704 | ".file" is handled. Note that you need a version of GCC | |
18705 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18706 | if (filename != NULL && ! first_file_directive) | |
18707 | { | |
18708 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18709 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18710 | } |
18711 | first_file_directive = 1; | |
18712 | } | |
c5dd6aab DJ |
18713 | } |
18714 | ||
18715 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18716 | |
18717 | static void | |
17a2f251 | 18718 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18719 | { |
c5dd6aab DJ |
18720 | if (!ECOFF_DEBUGGING) |
18721 | dwarf2_directive_loc (0); | |
252b5132 RH |
18722 | } |
18723 | ||
252b5132 RH |
18724 | /* The .end directive. */ |
18725 | ||
18726 | static void | |
17a2f251 | 18727 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18728 | { |
18729 | symbolS *p; | |
252b5132 | 18730 | |
7a621144 DJ |
18731 | /* Following functions need their own .frame and .cprestore directives. */ |
18732 | mips_frame_reg_valid = 0; | |
18733 | mips_cprestore_valid = 0; | |
18734 | ||
252b5132 RH |
18735 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18736 | { | |
18737 | p = get_symbol (); | |
18738 | demand_empty_rest_of_line (); | |
18739 | } | |
18740 | else | |
18741 | p = NULL; | |
18742 | ||
14949570 | 18743 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18744 | as_warn (_(".end not in text section")); |
18745 | ||
18746 | if (!cur_proc_ptr) | |
18747 | { | |
18748 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18749 | demand_empty_rest_of_line (); | |
18750 | return; | |
18751 | } | |
18752 | ||
18753 | if (p != NULL) | |
18754 | { | |
9c2799c2 | 18755 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18756 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18757 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18758 | |
18759 | if (debug_type == DEBUG_STABS) | |
18760 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18761 | S_GET_NAME (p)); | |
252b5132 RH |
18762 | } |
18763 | else | |
18764 | as_warn (_(".end directive missing or unknown symbol")); | |
18765 | ||
2132e3a3 | 18766 | #ifdef OBJ_ELF |
9b2f1d35 EC |
18767 | /* Create an expression to calculate the size of the function. */ |
18768 | if (p && cur_proc_ptr) | |
18769 | { | |
18770 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18771 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18772 | ||
18773 | obj->size = exp; | |
18774 | exp->X_op = O_subtract; | |
18775 | exp->X_add_symbol = symbol_temp_new_now (); | |
18776 | exp->X_op_symbol = p; | |
18777 | exp->X_add_number = 0; | |
18778 | ||
18779 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18780 | } | |
18781 | ||
ecb4347a | 18782 | /* Generate a .pdr section. */ |
f43abd2b | 18783 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18784 | { |
18785 | segT saved_seg = now_seg; | |
18786 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18787 | expressionS exp; |
18788 | char *fragp; | |
252b5132 | 18789 | |
252b5132 | 18790 | #ifdef md_flush_pending_output |
ecb4347a | 18791 | md_flush_pending_output (); |
252b5132 RH |
18792 | #endif |
18793 | ||
9c2799c2 | 18794 | gas_assert (pdr_seg); |
ecb4347a | 18795 | subseg_set (pdr_seg, 0); |
252b5132 | 18796 | |
ecb4347a DJ |
18797 | /* Write the symbol. */ |
18798 | exp.X_op = O_symbol; | |
18799 | exp.X_add_symbol = p; | |
18800 | exp.X_add_number = 0; | |
18801 | emit_expr (&exp, 4); | |
252b5132 | 18802 | |
ecb4347a | 18803 | fragp = frag_more (7 * 4); |
252b5132 | 18804 | |
17a2f251 TS |
18805 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18806 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
18807 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
18808 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
18809 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
18810 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
18811 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 18812 | |
ecb4347a DJ |
18813 | subseg_set (saved_seg, saved_subseg); |
18814 | } | |
18815 | #endif /* OBJ_ELF */ | |
252b5132 RH |
18816 | |
18817 | cur_proc_ptr = NULL; | |
18818 | } | |
18819 | ||
18820 | /* The .aent and .ent directives. */ | |
18821 | ||
18822 | static void | |
17a2f251 | 18823 | s_mips_ent (int aent) |
252b5132 | 18824 | { |
252b5132 | 18825 | symbolS *symbolP; |
252b5132 RH |
18826 | |
18827 | symbolP = get_symbol (); | |
18828 | if (*input_line_pointer == ',') | |
f9419b05 | 18829 | ++input_line_pointer; |
252b5132 | 18830 | SKIP_WHITESPACE (); |
3882b010 | 18831 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 18832 | || *input_line_pointer == '-') |
874e8986 | 18833 | get_number (); |
252b5132 | 18834 | |
14949570 | 18835 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18836 | as_warn (_(".ent or .aent not in text section.")); |
18837 | ||
18838 | if (!aent && cur_proc_ptr) | |
9a41af64 | 18839 | as_warn (_("missing .end")); |
252b5132 RH |
18840 | |
18841 | if (!aent) | |
18842 | { | |
7a621144 DJ |
18843 | /* This function needs its own .frame and .cprestore directives. */ |
18844 | mips_frame_reg_valid = 0; | |
18845 | mips_cprestore_valid = 0; | |
18846 | ||
252b5132 RH |
18847 | cur_proc_ptr = &cur_proc; |
18848 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
18849 | ||
9b2f1d35 | 18850 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 18851 | |
f9419b05 | 18852 | ++numprocs; |
ecb4347a DJ |
18853 | |
18854 | if (debug_type == DEBUG_STABS) | |
18855 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
18856 | S_GET_NAME (symbolP)); | |
252b5132 RH |
18857 | } |
18858 | ||
7c0fc524 MR |
18859 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
18860 | ||
252b5132 RH |
18861 | demand_empty_rest_of_line (); |
18862 | } | |
18863 | ||
18864 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 18865 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 18866 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 18867 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
18868 | symbol table (in the mdebug section). */ |
18869 | ||
18870 | static void | |
17a2f251 | 18871 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 18872 | { |
ecb4347a | 18873 | #ifdef OBJ_ELF |
f43abd2b | 18874 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
18875 | { |
18876 | long val; | |
252b5132 | 18877 | |
ecb4347a DJ |
18878 | if (cur_proc_ptr == (procS *) NULL) |
18879 | { | |
18880 | as_warn (_(".frame outside of .ent")); | |
18881 | demand_empty_rest_of_line (); | |
18882 | return; | |
18883 | } | |
252b5132 | 18884 | |
ecb4347a DJ |
18885 | cur_proc_ptr->frame_reg = tc_get_register (1); |
18886 | ||
18887 | SKIP_WHITESPACE (); | |
18888 | if (*input_line_pointer++ != ',' | |
18889 | || get_absolute_expression_and_terminator (&val) != ',') | |
18890 | { | |
18891 | as_warn (_("Bad .frame directive")); | |
18892 | --input_line_pointer; | |
18893 | demand_empty_rest_of_line (); | |
18894 | return; | |
18895 | } | |
252b5132 | 18896 | |
ecb4347a DJ |
18897 | cur_proc_ptr->frame_offset = val; |
18898 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 18899 | |
252b5132 | 18900 | demand_empty_rest_of_line (); |
252b5132 | 18901 | } |
ecb4347a DJ |
18902 | else |
18903 | #endif /* OBJ_ELF */ | |
18904 | s_ignore (ignore); | |
252b5132 RH |
18905 | } |
18906 | ||
bdaaa2e1 KH |
18907 | /* The .fmask and .mask directives. If the mdebug section is present |
18908 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 18909 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 18910 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
18911 | make reference to the ecoff symbol table (in the mdebug section). */ |
18912 | ||
18913 | static void | |
17a2f251 | 18914 | s_mips_mask (int reg_type) |
252b5132 | 18915 | { |
ecb4347a | 18916 | #ifdef OBJ_ELF |
f43abd2b | 18917 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 18918 | { |
ecb4347a | 18919 | long mask, off; |
252b5132 | 18920 | |
ecb4347a DJ |
18921 | if (cur_proc_ptr == (procS *) NULL) |
18922 | { | |
18923 | as_warn (_(".mask/.fmask outside of .ent")); | |
18924 | demand_empty_rest_of_line (); | |
18925 | return; | |
18926 | } | |
252b5132 | 18927 | |
ecb4347a DJ |
18928 | if (get_absolute_expression_and_terminator (&mask) != ',') |
18929 | { | |
18930 | as_warn (_("Bad .mask/.fmask directive")); | |
18931 | --input_line_pointer; | |
18932 | demand_empty_rest_of_line (); | |
18933 | return; | |
18934 | } | |
252b5132 | 18935 | |
ecb4347a DJ |
18936 | off = get_absolute_expression (); |
18937 | ||
18938 | if (reg_type == 'F') | |
18939 | { | |
18940 | cur_proc_ptr->fpreg_mask = mask; | |
18941 | cur_proc_ptr->fpreg_offset = off; | |
18942 | } | |
18943 | else | |
18944 | { | |
18945 | cur_proc_ptr->reg_mask = mask; | |
18946 | cur_proc_ptr->reg_offset = off; | |
18947 | } | |
18948 | ||
18949 | demand_empty_rest_of_line (); | |
252b5132 RH |
18950 | } |
18951 | else | |
ecb4347a DJ |
18952 | #endif /* OBJ_ELF */ |
18953 | s_ignore (reg_type); | |
252b5132 RH |
18954 | } |
18955 | ||
316f5878 RS |
18956 | /* A table describing all the processors gas knows about. Names are |
18957 | matched in the order listed. | |
e7af610e | 18958 | |
316f5878 RS |
18959 | To ease comparison, please keep this table in the same order as |
18960 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
18961 | static const struct mips_cpu_info mips_cpu_info_table[] = |
18962 | { | |
316f5878 | 18963 | /* Entries for generic ISAs */ |
ad3fea08 TS |
18964 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
18965 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
18966 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
18967 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
18968 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
18969 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
18970 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18971 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
18972 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
18973 | |
18974 | /* MIPS I */ | |
ad3fea08 TS |
18975 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
18976 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
18977 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
18978 | |
18979 | /* MIPS II */ | |
ad3fea08 | 18980 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
18981 | |
18982 | /* MIPS III */ | |
ad3fea08 TS |
18983 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
18984 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
18985 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
18986 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
18987 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
18988 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
18989 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
18990 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
18991 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
18992 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
18993 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
18994 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
18995 | /* ST Microelectronics Loongson 2E and 2F cores */ |
18996 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
18997 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
18998 | |
18999 | /* MIPS IV */ | |
ad3fea08 TS |
19000 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
19001 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
19002 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
19003 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
19004 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
19005 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
19006 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
19007 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
19008 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
19009 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
19010 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
19011 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
19012 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
19013 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
19014 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19015 | |
19016 | /* MIPS 32 */ | |
ad3fea08 TS |
19017 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
19018 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19019 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
19020 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
19021 | ||
19022 | /* MIPS 32 Release 2 */ | |
19023 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19024 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19025 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19026 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19027 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19028 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
19029 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19030 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
7a795ef4 MR |
19031 | { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, |
19032 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19033 | { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU, | |
19034 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19035 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19036 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19037 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19038 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19039 | /* Deprecated forms of the above. */ | |
19040 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 19041 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19042 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 19043 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 19044 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 19045 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
19046 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19047 | /* Deprecated forms of the above. */ | |
19048 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 19049 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19050 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
19051 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19052 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19053 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19054 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19055 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19056 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19057 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19058 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19059 | /* Deprecated forms of the above. */ | |
19060 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19061 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
19062 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
19063 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19064 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
19065 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19066 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19067 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19068 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19069 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19070 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19071 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19072 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19073 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19074 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19075 | /* Deprecated forms of the above. */ | |
19076 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19077 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19078 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19079 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19080 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19081 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19082 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19083 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19084 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19085 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19086 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19087 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19088 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19089 | |
316f5878 | 19090 | /* MIPS 64 */ |
ad3fea08 TS |
19091 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19092 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19093 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19094 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19095 | |
c7a23324 | 19096 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19097 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19098 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19099 | /* Broadcom SB-1A CPU core */ |
19100 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19101 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19102 | |
19103 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19104 | |
ed163775 MR |
19105 | /* MIPS 64 Release 2 */ |
19106 | ||
967344c6 AN |
19107 | /* Cavium Networks Octeon CPU core */ |
19108 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
dd6a37e7 | 19109 | { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP }, |
432233b3 | 19110 | { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
967344c6 | 19111 | |
52b6b6b9 JM |
19112 | /* RMI Xlr */ |
19113 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19114 | ||
316f5878 RS |
19115 | /* End marker */ |
19116 | { NULL, 0, 0, 0 } | |
19117 | }; | |
e7af610e | 19118 | |
84ea6cf2 | 19119 | |
316f5878 RS |
19120 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19121 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19122 | |
316f5878 | 19123 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19124 | |
b34976b6 | 19125 | static bfd_boolean |
17a2f251 | 19126 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19127 | { |
19128 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19129 | given++, canonical++; | |
19130 | ||
19131 | return ((*given == 0 && *canonical == 0) | |
19132 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19133 | } | |
19134 | ||
19135 | ||
19136 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19137 | CPU name. We've traditionally allowed a lot of variation here. | |
19138 | ||
19139 | Note: this function is shared between GCC and GAS. */ | |
19140 | ||
b34976b6 | 19141 | static bfd_boolean |
17a2f251 | 19142 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19143 | { |
19144 | /* First see if the name matches exactly, or with a final "000" | |
19145 | turned into "k". */ | |
19146 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19147 | return TRUE; |
316f5878 RS |
19148 | |
19149 | /* If not, try comparing based on numerical designation alone. | |
19150 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19151 | if (TOLOWER (*given) == 'r') | |
19152 | given++; | |
19153 | if (!ISDIGIT (*given)) | |
b34976b6 | 19154 | return FALSE; |
316f5878 RS |
19155 | |
19156 | /* Skip over some well-known prefixes in the canonical name, | |
19157 | hoping to find a number there too. */ | |
19158 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19159 | canonical += 2; | |
19160 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19161 | canonical += 2; | |
19162 | else if (TOLOWER (canonical[0]) == 'r') | |
19163 | canonical += 1; | |
19164 | ||
19165 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19166 | } | |
19167 | ||
19168 | ||
19169 | /* Parse an option that takes the name of a processor as its argument. | |
19170 | OPTION is the name of the option and CPU_STRING is the argument. | |
19171 | Return the corresponding processor enumeration if the CPU_STRING is | |
19172 | recognized, otherwise report an error and return null. | |
19173 | ||
19174 | A similar function exists in GCC. */ | |
e7af610e NC |
19175 | |
19176 | static const struct mips_cpu_info * | |
17a2f251 | 19177 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19178 | { |
316f5878 | 19179 | const struct mips_cpu_info *p; |
e7af610e | 19180 | |
316f5878 RS |
19181 | /* 'from-abi' selects the most compatible architecture for the given |
19182 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19183 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19184 | version. Look first at the -mgp options, if given, otherwise base | |
19185 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19186 | |
316f5878 RS |
19187 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19188 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19189 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19190 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19191 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19192 | { | |
19193 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19194 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19195 | ||
19196 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19197 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19198 | ||
19199 | if (file_mips_gp32 >= 0) | |
19200 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19201 | ||
19202 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19203 | ? ISA_MIPS3 | |
19204 | : ISA_MIPS1); | |
19205 | } | |
19206 | ||
19207 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19208 | if (strcasecmp (cpu_string, "default") == 0) | |
19209 | return 0; | |
19210 | ||
19211 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19212 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19213 | return p; | |
19214 | ||
20203fb9 | 19215 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19216 | return 0; |
e7af610e NC |
19217 | } |
19218 | ||
316f5878 RS |
19219 | /* Return the canonical processor information for ISA (a member of the |
19220 | ISA_MIPS* enumeration). */ | |
19221 | ||
e7af610e | 19222 | static const struct mips_cpu_info * |
17a2f251 | 19223 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19224 | { |
19225 | int i; | |
19226 | ||
19227 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19228 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19229 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19230 | return (&mips_cpu_info_table[i]); |
19231 | ||
e972090a | 19232 | return NULL; |
e7af610e | 19233 | } |
fef14a42 TS |
19234 | |
19235 | static const struct mips_cpu_info * | |
17a2f251 | 19236 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19237 | { |
19238 | int i; | |
19239 | ||
19240 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19241 | if (arch == mips_cpu_info_table[i].cpu) | |
19242 | return (&mips_cpu_info_table[i]); | |
19243 | ||
19244 | return NULL; | |
19245 | } | |
316f5878 RS |
19246 | \f |
19247 | static void | |
17a2f251 | 19248 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19249 | { |
19250 | if (*first_p) | |
19251 | { | |
19252 | fprintf (stream, "%24s", ""); | |
19253 | *col_p = 24; | |
19254 | } | |
19255 | else | |
19256 | { | |
19257 | fprintf (stream, ", "); | |
19258 | *col_p += 2; | |
19259 | } | |
e7af610e | 19260 | |
316f5878 RS |
19261 | if (*col_p + strlen (string) > 72) |
19262 | { | |
19263 | fprintf (stream, "\n%24s", ""); | |
19264 | *col_p = 24; | |
19265 | } | |
19266 | ||
19267 | fprintf (stream, "%s", string); | |
19268 | *col_p += strlen (string); | |
19269 | ||
19270 | *first_p = 0; | |
19271 | } | |
19272 | ||
19273 | void | |
17a2f251 | 19274 | md_show_usage (FILE *stream) |
e7af610e | 19275 | { |
316f5878 RS |
19276 | int column, first; |
19277 | size_t i; | |
19278 | ||
19279 | fprintf (stream, _("\ | |
19280 | MIPS options:\n\ | |
316f5878 RS |
19281 | -EB generate big endian output\n\ |
19282 | -EL generate little endian output\n\ | |
19283 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19284 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19285 | implicitly with the gp register [default 8]\n")); | |
19286 | fprintf (stream, _("\ | |
19287 | -mips1 generate MIPS ISA I instructions\n\ | |
19288 | -mips2 generate MIPS ISA II instructions\n\ | |
19289 | -mips3 generate MIPS ISA III instructions\n\ | |
19290 | -mips4 generate MIPS ISA IV instructions\n\ | |
19291 | -mips5 generate MIPS ISA V instructions\n\ | |
19292 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19293 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19294 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19295 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19296 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19297 | ||
19298 | first = 1; | |
e7af610e NC |
19299 | |
19300 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19301 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19302 | show (stream, "from-abi", &column, &first); | |
19303 | fputc ('\n', stream); | |
e7af610e | 19304 | |
316f5878 RS |
19305 | fprintf (stream, _("\ |
19306 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19307 | -no-mCPU don't generate code specific to CPU.\n\ | |
19308 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19309 | ||
19310 | first = 1; | |
19311 | ||
19312 | show (stream, "3900", &column, &first); | |
19313 | show (stream, "4010", &column, &first); | |
19314 | show (stream, "4100", &column, &first); | |
19315 | show (stream, "4650", &column, &first); | |
19316 | fputc ('\n', stream); | |
19317 | ||
19318 | fprintf (stream, _("\ | |
19319 | -mips16 generate mips16 instructions\n\ | |
19320 | -no-mips16 do not generate mips16 instructions\n")); | |
19321 | fprintf (stream, _("\ | |
df58fc94 RS |
19322 | -mmicromips generate microMIPS instructions\n\ |
19323 | -mno-micromips do not generate microMIPS instructions\n")); | |
19324 | fprintf (stream, _("\ | |
e16bfa71 TS |
19325 | -msmartmips generate smartmips instructions\n\ |
19326 | -mno-smartmips do not generate smartmips instructions\n")); | |
19327 | fprintf (stream, _("\ | |
74cd071d CF |
19328 | -mdsp generate DSP instructions\n\ |
19329 | -mno-dsp do not generate DSP instructions\n")); | |
19330 | fprintf (stream, _("\ | |
8b082fb1 TS |
19331 | -mdspr2 generate DSP R2 instructions\n\ |
19332 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19333 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19334 | -mmt generate MT instructions\n\ |
19335 | -mno-mt do not generate MT instructions\n")); | |
19336 | fprintf (stream, _("\ | |
dec0624d MR |
19337 | -mmcu generate MCU instructions\n\ |
19338 | -mno-mcu do not generate MCU instructions\n")); | |
19339 | fprintf (stream, _("\ | |
c67a084a NC |
19340 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19341 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19342 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19343 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19344 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19345 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19346 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19347 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19348 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19349 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19350 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19351 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19352 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19353 | fprintf (stream, _("\ |
19354 | -mhard-float allow floating-point instructions\n\ | |
19355 | -msoft-float do not allow floating-point instructions\n\ | |
19356 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19357 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19358 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19359 | )); | |
316f5878 RS |
19360 | #ifdef OBJ_ELF |
19361 | fprintf (stream, _("\ | |
19362 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19363 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19364 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19365 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19366 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19367 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19368 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19369 | position dependent (non shared) code\n\ |
316f5878 RS |
19370 | -mabi=ABI create ABI conformant object file for:\n")); |
19371 | ||
19372 | first = 1; | |
19373 | ||
19374 | show (stream, "32", &column, &first); | |
19375 | show (stream, "o64", &column, &first); | |
19376 | show (stream, "n32", &column, &first); | |
19377 | show (stream, "64", &column, &first); | |
19378 | show (stream, "eabi", &column, &first); | |
19379 | ||
19380 | fputc ('\n', stream); | |
19381 | ||
19382 | fprintf (stream, _("\ | |
19383 | -32 create o32 ABI object file (default)\n\ | |
19384 | -n32 create n32 ABI object file\n\ | |
19385 | -64 create 64 ABI object file\n")); | |
19386 | #endif | |
e7af610e | 19387 | } |
14e777e0 | 19388 | |
1575952e | 19389 | #ifdef TE_IRIX |
14e777e0 | 19390 | enum dwarf2_format |
413a266c | 19391 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19392 | { |
369943fe | 19393 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19394 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19395 | else |
19396 | return dwarf2_format_32bit; | |
19397 | } | |
1575952e | 19398 | #endif |
73369e65 EC |
19399 | |
19400 | int | |
19401 | mips_dwarf2_addr_size (void) | |
19402 | { | |
6b6b3450 | 19403 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19404 | return 8; |
73369e65 EC |
19405 | else |
19406 | return 4; | |
19407 | } | |
5862107c EC |
19408 | |
19409 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19410 | void | |
19411 | mips_cfi_frame_initial_instructions (void) | |
19412 | { | |
19413 | cfi_add_CFA_def_cfa_register (SP); | |
19414 | } | |
19415 | ||
707bfff6 TS |
19416 | int |
19417 | tc_mips_regname_to_dw2regnum (char *regname) | |
19418 | { | |
19419 | unsigned int regnum = -1; | |
19420 | unsigned int reg; | |
19421 | ||
19422 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19423 | regnum = reg; | |
19424 | ||
19425 | return regnum; | |
19426 | } |