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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
f2a663d3 | 71 | #include "elf/mips.h" |
1dc1e798 | 72 | #endif |
f2a663d3 | 73 | |
739708fa | 74 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 75 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
76 | #define ECOFF_DEBUGGING 0 |
77 | #endif | |
78 | ||
22ba90ce ILT |
79 | #include "ecoff.h" |
80 | ||
a8aed9dd | 81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 82 | static char *mips_regmask_frag; |
a8aed9dd | 83 | #endif |
f2a663d3 | 84 | |
3d3c5039 | 85 | #define AT 1 |
cc5703cd | 86 | #define TREG 24 |
9226253a | 87 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
88 | #define KT0 26 |
89 | #define KT1 27 | |
670a50eb | 90 | #define GP 28 |
9226253a ILT |
91 | #define SP 29 |
92 | #define FP 30 | |
3d3c5039 ILT |
93 | #define RA 31 |
94 | ||
cc5703cd ILT |
95 | #define ILLEGAL_REG (32) |
96 | ||
af942793 SS |
97 | /* Allow override of standard little-endian ECOFF format. */ |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
1dc1e798 | 103 | extern int target_big_endian; |
88225433 | 104 | |
7f9880e5 ILT |
105 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
106 | 32 bit ABI. This has no meaning for ECOFF. */ | |
107 | static int mips_64; | |
108 | ||
04cb3372 | 109 | /* The default target format to use. */ |
1dc1e798 KR |
110 | const char * |
111 | mips_target_format () | |
112 | { | |
113 | switch (OUTPUT_FLAVOR) | |
114 | { | |
115 | case bfd_target_aout_flavour: | |
116 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
117 | case bfd_target_ecoff_flavour: | |
af942793 | 118 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 119 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
120 | return (target_big_endian |
121 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
122 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
123 | default: |
124 | abort (); | |
125 | } | |
126 | } | |
04cb3372 | 127 | |
d2c71068 | 128 | /* The name of the readonly data section. */ |
1dc1e798 KR |
129 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
130 | ? ".data" \ | |
131 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
132 | ? ".rdata" \ | |
133 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
134 | ? ".rodata" \ | |
135 | : (abort (), "")) | |
d2c71068 | 136 | |
3c83da8a JW |
137 | /* This is the set of options which may be modified by the .set |
138 | pseudo-op. We use a struct so that .set push and .set pop are more | |
139 | reliable. */ | |
140 | ||
141 | struct mips_set_options | |
142 | { | |
143 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
144 | if it has not been initialized. Changed by `.set mipsN', and the | |
145 | -mipsN command line option, and the default CPU. */ | |
146 | int isa; | |
147 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
148 | not, 1 if we are, and -1 if the value has not been initialized. | |
149 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
150 | -nomips16 command line options, and the default CPU. */ | |
151 | int mips16; | |
152 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
153 | reorder' and `.set noreorder'. */ | |
154 | int noreorder; | |
155 | /* Non-zero if we should not permit the $at ($1) register to be used | |
156 | in instructions. Changed by `.set at' and `.set noat'. */ | |
157 | int noat; | |
158 | /* Non-zero if we should warn when a macro instruction expands into | |
159 | more than one machine instruction. Changed by `.set nomacro' and | |
160 | `.set macro'. */ | |
161 | int warn_about_macros; | |
162 | /* Non-zero if we should not move instructions. Changed by `.set | |
163 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
164 | int nomove; | |
165 | /* Non-zero if we should not optimize branches by moving the target | |
166 | of the branch into the delay slot. Actually, we don't perform | |
167 | this optimization anyhow. Changed by `.set bopt' and `.set | |
168 | nobopt'. */ | |
169 | int nobopt; | |
170 | /* Non-zero if we should not autoextend mips16 instructions. | |
171 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
172 | int noautoextend; | |
173 | }; | |
174 | ||
175 | /* This is the struct we use to hold the current set of options. Note | |
176 | that we must set the isa and mips16 fields to -1 to indicate that | |
177 | they have not been initialized. */ | |
178 | ||
179 | static struct mips_set_options mips_opts = { -1, -1 }; | |
180 | ||
1aa6938e ILT |
181 | /* These variables are filled in with the masks of registers used. |
182 | The object format code reads them and puts them in the appropriate | |
183 | place. */ | |
184 | unsigned long mips_gprmask; | |
185 | unsigned long mips_cprmask[4]; | |
186 | ||
1051c97f ILT |
187 | /* MIPS ISA we are using for this output file. */ |
188 | static int file_mips_isa; | |
189 | ||
8c63448a | 190 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 191 | static int mips_cpu = -1; |
8c63448a | 192 | |
b2b8c24e ILT |
193 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
194 | static int mips_4650 = -1; | |
195 | ||
e532b44c ILT |
196 | /* Whether the 4010 instructions are permitted. */ |
197 | static int mips_4010 = -1; | |
198 | ||
c625fc23 JSC |
199 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
200 | static int mips_4100 = -1; | |
201 | ||
276c2d7d GRK |
202 | /* start-sanitize-r5900 */ |
203 | /* Whether Toshiba r5900 instructions are permitted. */ | |
204 | static int mips_5900 = -1; | |
205 | /* end-sanitize-r5900 */ | |
206 | ||
5c6f5923 GRK |
207 | /* Whether Toshiba r3900 instructions are permitted. */ |
208 | static int mips_3900 = -1; | |
209 | ||
210 | /* Whether the processor uses hardware interlocks to protect | |
211 | reads from the HI and LO registers, and thus does not | |
212 | require nops to be inserted. */ | |
213 | static int hilo_interlocks = -1; | |
214 | ||
215 | /* Whether the processor uses hardware interlocks to protect | |
216 | reads from the GPRs, and thus does not | |
e532b44c | 217 | require nops to be inserted. */ |
5c6f5923 | 218 | static int gpr_interlocks = -1; |
e532b44c | 219 | |
5c6f5923 | 220 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 221 | (co-processor) interlocks. */ |
efec4a28 | 222 | /* Itbl support may require additional care here. */ |
344a8d61 JSC |
223 | static int cop_interlocks = -1; |
224 | ||
d9aba805 ILT |
225 | /* MIPS PIC level. */ |
226 | ||
227 | enum mips_pic_level | |
228 | { | |
229 | /* Do not generate PIC code. */ | |
230 | NO_PIC, | |
231 | ||
232 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
233 | not sure what it is supposed to do. */ | |
234 | IRIX4_PIC, | |
235 | ||
236 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
237 | SVR4_PIC, | |
238 | ||
239 | /* Generate PIC code without using a global offset table: the data | |
240 | segment has a maximum size of 64K, all data references are off | |
241 | the $gp register, and all text references are PC relative. This | |
242 | is used on some embedded systems. */ | |
243 | EMBEDDED_PIC | |
244 | }; | |
245 | ||
246 | static enum mips_pic_level mips_pic; | |
9226253a | 247 | |
fb251650 ILT |
248 | /* 1 if we should generate 32 bit offsets from the GP register in |
249 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
250 | static int mips_big_got; | |
251 | ||
8ea7f4e8 ILT |
252 | /* 1 if trap instructions should used for overflow rather than break |
253 | instructions. */ | |
254 | static int mips_trap; | |
255 | ||
3c83da8a | 256 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 257 | |
0dd2d296 | 258 | static int mips_any_noreorder; |
3d3c5039 | 259 | |
670a50eb ILT |
260 | /* The size of the small data section. */ |
261 | static int g_switch_value = 8; | |
42562568 ILT |
262 | /* Whether the -G option was used. */ |
263 | static int g_switch_seen = 0; | |
670a50eb | 264 | |
3d3c5039 ILT |
265 | #define N_RMASK 0xc4 |
266 | #define N_VFP 0xd4 | |
267 | ||
d8a1c247 KR |
268 | /* If we can determine in advance that GP optimization won't be |
269 | possible, we can skip the relaxation stuff that tries to produce | |
270 | GP-relative references. This makes delay slot optimization work | |
271 | better. | |
272 | ||
273 | This function can only provide a guess, but it seems to work for | |
274 | gcc output. If it guesses wrong, the only loss should be in | |
275 | efficiency; it shouldn't introduce any bugs. | |
276 | ||
277 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
278 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 279 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 280 | |
3d3c5039 ILT |
281 | /* handle of the OPCODE hash table */ |
282 | static struct hash_control *op_hash = NULL; | |
283 | ||
cc5703cd ILT |
284 | /* The opcode hash table we use for the mips16. */ |
285 | static struct hash_control *mips16_op_hash = NULL; | |
286 | ||
3d3c5039 ILT |
287 | /* This array holds the chars that always start a comment. If the |
288 | pre-processor is disabled, these aren't very useful */ | |
289 | const char comment_chars[] = "#"; | |
290 | ||
291 | /* This array holds the chars that only start a comment at the beginning of | |
292 | a line. If the line seems to have the form '# 123 filename' | |
293 | .line and .file directives will appear in the pre-processed output */ | |
294 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
295 | first line of the input file. This is because the compiler outputs | |
296 | #NO_APP at the beginning of its output. */ | |
297 | /* Also note that C style comments are always supported. */ | |
298 | const char line_comment_chars[] = "#"; | |
299 | ||
300 | /* This array holds machine specific line separator characters. */ | |
301 | const char line_separator_chars[] = ""; | |
302 | ||
303 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
304 | const char EXP_CHARS[] = "eE"; | |
305 | ||
306 | /* Chars that mean this number is a floating point constant */ | |
307 | /* As in 0f12.456 */ | |
308 | /* or 0d1.2345e12 */ | |
309 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
310 | ||
311 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
312 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
313 | but nothing is ideal around here. | |
314 | */ | |
315 | ||
670a50eb | 316 | static char *insn_error; |
3d3c5039 | 317 | |
3d3c5039 | 318 | static int auto_align = 1; |
becfe05e | 319 | |
9226253a ILT |
320 | /* When outputting SVR4 PIC code, the assembler needs to know the |
321 | offset in the stack frame from which to restore the $gp register. | |
322 | This is set by the .cprestore pseudo-op, and saved in this | |
323 | variable. */ | |
0dd2d296 ILT |
324 | static offsetT mips_cprestore_offset = -1; |
325 | ||
326 | /* This is the register which holds the stack frame, as set by the | |
327 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
328 | static int mips_frame_reg = SP; | |
9226253a | 329 | |
becfe05e ILT |
330 | /* To output NOP instructions correctly, we need to keep information |
331 | about the previous two instructions. */ | |
332 | ||
0aa07269 ILT |
333 | /* Whether we are optimizing. The default value of 2 means to remove |
334 | unneeded NOPs and swap branch instructions when possible. A value | |
335 | of 1 means to not swap branches. A value of 0 means to always | |
336 | insert NOPs. */ | |
337 | static int mips_optimize = 2; | |
4e95866e | 338 | |
22ba90ce ILT |
339 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
340 | equivalent to seeing no -g option at all. */ | |
341 | static int mips_debug = 0; | |
342 | ||
becfe05e ILT |
343 | /* The previous instruction. */ |
344 | static struct mips_cl_insn prev_insn; | |
345 | ||
346 | /* The instruction before prev_insn. */ | |
347 | static struct mips_cl_insn prev_prev_insn; | |
348 | ||
349 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
350 | point the insn_mo field at this dummy integer. */ | |
351 | static const struct mips_opcode dummy_opcode = { 0 }; | |
352 | ||
353 | /* Non-zero if prev_insn is valid. */ | |
354 | static int prev_insn_valid; | |
355 | ||
356 | /* The frag for the previous instruction. */ | |
357 | static struct frag *prev_insn_frag; | |
358 | ||
359 | /* The offset into prev_insn_frag for the previous instruction. */ | |
360 | static long prev_insn_where; | |
361 | ||
a677feeb ILT |
362 | /* The reloc type for the previous instruction, if any. */ |
363 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
364 | ||
becfe05e ILT |
365 | /* The reloc for the previous instruction, if any. */ |
366 | static fixS *prev_insn_fixp; | |
367 | ||
368 | /* Non-zero if the previous instruction was in a delay slot. */ | |
369 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
370 | |
371 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
372 | static int prev_insn_unreordered; | |
373 | ||
cc5703cd ILT |
374 | /* Non-zero if the previous instruction uses an extend opcode (if |
375 | mips16). */ | |
376 | static int prev_insn_extended; | |
377 | ||
4e95866e ILT |
378 | /* Non-zero if the previous previous instruction was in a .set |
379 | noreorder. */ | |
380 | static int prev_prev_insn_unreordered; | |
867a58b3 | 381 | |
4a1cb507 ILT |
382 | /* If this is set, it points to a frag holding nop instructions which |
383 | were inserted before the start of a noreorder section. If those | |
384 | nops turn out to be unnecessary, the size of the frag can be | |
385 | decreased. */ | |
386 | static fragS *prev_nop_frag; | |
387 | ||
388 | /* The number of nop instructions we created in prev_nop_frag. */ | |
389 | static int prev_nop_frag_holds; | |
390 | ||
391 | /* The number of nop instructions that we know we need in | |
392 | prev_nop_frag. */ | |
393 | static int prev_nop_frag_required; | |
394 | ||
395 | /* The number of instructions we've seen since prev_nop_frag. */ | |
396 | static int prev_nop_frag_since; | |
397 | ||
867a58b3 ILT |
398 | /* For ECOFF and ELF, relocations against symbols are done in two |
399 | parts, with a HI relocation and a LO relocation. Each relocation | |
400 | has only 16 bits of space to store an addend. This means that in | |
401 | order for the linker to handle carries correctly, it must be able | |
402 | to locate both the HI and the LO relocation. This means that the | |
403 | relocations must appear in order in the relocation table. | |
404 | ||
405 | In order to implement this, we keep track of each unmatched HI | |
406 | relocation. We then sort them so that they immediately precede the | |
407 | corresponding LO relocation. */ | |
408 | ||
409 | struct mips_hi_fixup | |
410 | { | |
411 | /* Next HI fixup. */ | |
412 | struct mips_hi_fixup *next; | |
413 | /* This fixup. */ | |
414 | fixS *fixp; | |
415 | /* The section this fixup is in. */ | |
416 | segT seg; | |
417 | }; | |
418 | ||
419 | /* The list of unmatched HI relocs. */ | |
420 | ||
421 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
422 | |
423 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
424 | ||
425 | #define X ILLEGAL_REG | |
426 | static const int mips32_to_16_reg_map[] = | |
427 | { | |
428 | X, X, 2, 3, 4, 5, 6, 7, | |
429 | X, X, X, X, X, X, X, X, | |
430 | 0, 1, X, X, X, X, X, X, | |
431 | X, X, X, X, X, X, X, X | |
432 | }; | |
433 | #undef X | |
434 | ||
435 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
436 | ||
437 | static const int mips16_to_32_reg_map[] = | |
438 | { | |
439 | 16, 17, 2, 3, 4, 5, 6, 7 | |
440 | }; | |
3d3c5039 | 441 | \f |
0dd2d296 ILT |
442 | /* Since the MIPS does not have multiple forms of PC relative |
443 | instructions, we do not have to do relaxing as is done on other | |
444 | platforms. However, we do have to handle GP relative addressing | |
445 | correctly, which turns out to be a similar problem. | |
446 | ||
447 | Every macro that refers to a symbol can occur in (at least) two | |
448 | forms, one with GP relative addressing and one without. For | |
449 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 450 | a macro instruction like this: |
0dd2d296 ILT |
451 | lw $4,i |
452 | If i can be addressed off the GP register (this is true if it is in | |
453 | the .sbss or .sdata section, or if it is known to be smaller than | |
454 | the -G argument) this will generate the following instruction: | |
455 | lw $4,i($gp) | |
456 | This instruction will use a GPREL reloc. If i can not be addressed | |
457 | off the GP register, the following instruction sequence will be used: | |
458 | lui $at,i | |
459 | lw $4,i($at) | |
460 | In this case the first instruction will have a HI16 reloc, and the | |
461 | second reloc will have a LO16 reloc. Both relocs will be against | |
462 | the symbol i. | |
463 | ||
464 | The issue here is that we may not know whether i is GP addressable | |
465 | until after we see the instruction that uses it. Therefore, we | |
466 | want to be able to choose the final instruction sequence only at | |
467 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 468 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
469 | end of assembly. |
470 | ||
471 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
472 | addressing in quite the same way, but the issue still arises as |
473 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
474 | |
475 | We handle these issues by actually generating both possible | |
476 | instruction sequences. The longer one is put in a frag_var with | |
477 | type rs_machine_dependent. We encode what to do with the frag in | |
478 | the subtype field. We encode (1) the number of existing bytes to | |
479 | replace, (2) the number of new bytes to use, (3) the offset from | |
480 | the start of the existing bytes to the first reloc we must generate | |
481 | (that is, the offset is applied from the start of the existing | |
482 | bytes after they are replaced by the new bytes, if any), (4) the | |
483 | offset from the start of the existing bytes to the second reloc, | |
484 | (5) whether a third reloc is needed (the third reloc is always four | |
485 | bytes after the second reloc), and (6) whether to warn if this | |
486 | variant is used (this is sometimes needed if .set nomacro or .set | |
487 | noat is in effect). All these numbers are reasonably small. | |
488 | ||
489 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
490 | ensure that delay slots are handled correctly. Fortunately, there |
491 | are a limited number of cases. When the second instruction | |
492 | sequence is generated, append_insn is directed to maintain the | |
493 | existing delay slot information, so it continues to apply to any | |
494 | code after the second instruction sequence. This means that the | |
495 | second instruction sequence must not impose any requirements not | |
496 | required by the first instruction sequence. | |
0dd2d296 ILT |
497 | |
498 | These variant frags are then handled in functions called by the | |
499 | machine independent code. md_estimate_size_before_relax returns | |
500 | the final size of the frag. md_convert_frag sets up the final form | |
501 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
502 | one if needed. */ | |
503 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
504 | ((relax_substateT) \ | |
cc5703cd | 505 | (((old) << 23) \ |
0dd2d296 ILT |
506 | | ((new) << 16) \ |
507 | | (((reloc1) + 64) << 9) \ | |
508 | | (((reloc2) + 64) << 2) \ | |
509 | | ((reloc3) ? (1 << 1) : 0) \ | |
510 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
511 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
512 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
513 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
514 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
515 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
516 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
517 | |
518 | /* For mips16 code, we use an entirely different form of relaxation. | |
519 | mips16 supports two versions of most instructions which take | |
520 | immediate values: a small one which takes some small value, and a | |
521 | larger one which takes a 16 bit value. Since branches also follow | |
522 | this pattern, relaxing these values is required. | |
523 | ||
524 | We can assemble both mips16 and normal MIPS code in a single | |
525 | object. Therefore, we need to support this type of relaxation at | |
526 | the same time that we support the relaxation described above. We | |
527 | use the high bit of the subtype field to distinguish these cases. | |
528 | ||
a677feeb ILT |
529 | The information we store for this type of relaxation is the |
530 | argument code found in the opcode file for this relocation, whether | |
531 | the user explicitly requested a small or extended form, and whether | |
532 | the relocation is in a jump or jal delay slot. That tells us the | |
533 | size of the value, and how it should be stored. We also store | |
534 | whether the fragment is considered to be extended or not. We also | |
535 | store whether this is known to be a branch to a different section, | |
536 | whether we have tried to relax this frag yet, and whether we have | |
537 | ever extended a PC relative fragment because of a shift count. */ | |
538 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
539 | (0x80000000 \ | |
540 | | ((type) & 0xff) \ | |
541 | | ((small) ? 0x100 : 0) \ | |
542 | | ((ext) ? 0x200 : 0) \ | |
543 | | ((dslot) ? 0x400 : 0) \ | |
544 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
545 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
546 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
547 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
548 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
549 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
550 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
551 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
552 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
553 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
554 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
555 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
556 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 557 | \f |
3d3c5039 ILT |
558 | /* Prototypes for static functions. */ |
559 | ||
560 | #ifdef __STDC__ | |
561 | #define internalError() \ | |
562 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
563 | #else | |
564 | #define internalError() as_fatal ("MIPS internal Error"); | |
565 | #endif | |
566 | ||
cc5703cd ILT |
567 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
568 | ||
becfe05e | 569 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 570 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 571 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 572 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
573 | static void append_insn PARAMS ((char *place, |
574 | struct mips_cl_insn * ip, | |
670a50eb | 575 | expressionS * p, |
867a58b3 ILT |
576 | bfd_reloc_code_real_type r, |
577 | boolean)); | |
4a1cb507 | 578 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 579 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 580 | #ifdef USE_STDARG |
0dd2d296 | 581 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
582 | const char *name, const char *fmt, |
583 | ...)); | |
c625fc23 JSC |
584 | #else |
585 | static void macro_build (); | |
586 | #endif | |
cc5703cd ILT |
587 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
588 | const char *, const char *, | |
589 | va_list)); | |
0dd2d296 ILT |
590 | static void macro_build_lui PARAMS ((char *place, int *counter, |
591 | expressionS * ep, int regnum)); | |
6e8dda9c | 592 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 593 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 594 | expressionS *)); |
d8a1c247 | 595 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 596 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 597 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 598 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
599 | #ifdef LOSING_COMPILER |
600 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
601 | #endif | |
670a50eb | 602 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 603 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
604 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
605 | boolean, boolean, unsigned long *, | |
606 | boolean *, unsigned short *)); | |
670a50eb ILT |
607 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
608 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 609 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 610 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
611 | static void s_align PARAMS ((int)); |
612 | static void s_change_sec PARAMS ((int)); | |
613 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 614 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 615 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
616 | static void s_option PARAMS ((int)); |
617 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
618 | static void s_abicalls PARAMS ((int)); |
619 | static void s_cpload PARAMS ((int)); | |
620 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
621 | static void s_gpword PARAMS ((int)); |
622 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 623 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
624 | static void md_obj_begin PARAMS ((void)); |
625 | static void md_obj_end PARAMS ((void)); | |
626 | static long get_number PARAMS ((void)); | |
627 | static void s_ent PARAMS ((int)); | |
628 | static void s_mipsend PARAMS ((int)); | |
629 | static void s_file PARAMS ((int)); | |
3c83da8a | 630 | static void s_mips_stab PARAMS ((int)); |
cc5703cd | 631 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
632 | \f |
633 | /* Pseudo-op table. | |
634 | ||
635 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
636 | should be defined here, but are currently unsupported: .alias, | |
637 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
638 | ||
639 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
640 | specific to the type of debugging information being generated, and | |
641 | should be defined by the object format: .aent, .begin, .bend, | |
642 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
643 | .vreg. | |
644 | ||
645 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
646 | not MIPS CPU specific, but are also not specific to the object file | |
647 | format. This file is probably the best place to define them, but | |
648 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
649 | .struct, .weakext. */ | |
650 | ||
739708fa | 651 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 652 | { |
670a50eb ILT |
653 | /* MIPS specific pseudo-ops. */ |
654 | {"option", s_option, 0}, | |
655 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
656 | {"rdata", s_change_sec, 'r'}, |
657 | {"sdata", s_change_sec, 's'}, | |
658 | {"livereg", s_ignore, 0}, | |
739708fa KR |
659 | {"abicalls", s_abicalls, 0}, |
660 | {"cpload", s_cpload, 0}, | |
661 | {"cprestore", s_cprestore, 0}, | |
662 | {"gpword", s_gpword, 0}, | |
663 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 664 | {"insn", s_insn, 0}, |
3d3c5039 | 665 | |
670a50eb | 666 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 667 | chips. */ |
739708fa | 668 | {"asciiz", stringer, 1}, |
670a50eb ILT |
669 | {"bss", s_change_sec, 'b'}, |
670 | {"err", s_err, 0}, | |
671 | {"half", s_cons, 1}, | |
52aa70b5 | 672 | {"dword", s_cons, 3}, |
3d3c5039 | 673 | |
670a50eb | 674 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 675 | here for one reason or another. */ |
670a50eb ILT |
676 | {"align", s_align, 0}, |
677 | {"byte", s_cons, 0}, | |
678 | {"data", s_change_sec, 'd'}, | |
becfe05e | 679 | {"double", s_float_cons, 'd'}, |
becfe05e | 680 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
681 | {"globl", s_mips_globl, 0}, |
682 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
683 | {"hword", s_cons, 1}, |
684 | {"int", s_cons, 2}, | |
685 | {"long", s_cons, 2}, | |
686 | {"octa", s_cons, 4}, | |
687 | {"quad", s_cons, 3}, | |
688 | {"short", s_cons, 1}, | |
689 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 690 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
691 | {"text", s_change_sec, 't'}, |
692 | {"word", s_cons, 2}, | |
739708fa KR |
693 | { 0 }, |
694 | }; | |
3d3c5039 | 695 | |
739708fa | 696 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 697 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 698 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 699 | {"aent", s_ent, 1}, |
9226253a | 700 | {"bgnb", s_ignore, 0}, |
670a50eb | 701 | {"end", s_mipsend, 0}, |
9226253a | 702 | {"endb", s_ignore, 0}, |
670a50eb ILT |
703 | {"ent", s_ent, 0}, |
704 | {"file", s_file, 0}, | |
705 | {"fmask", s_ignore, 'F'}, | |
706 | {"frame", s_ignore, 0}, | |
707 | {"loc", s_ignore, 0}, | |
708 | {"mask", s_ignore, 'R'}, | |
709 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
710 | { 0 }, |
711 | }; | |
61420a20 | 712 | |
739708fa KR |
713 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
714 | ||
715 | void | |
716 | mips_pop_insert () | |
717 | { | |
718 | pop_insert (mips_pseudo_table); | |
719 | if (! ECOFF_DEBUGGING) | |
720 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 721 | } |
3d3c5039 | 722 | \f |
fbcfacb7 ILT |
723 | /* Symbols labelling the current insn. */ |
724 | ||
725 | struct insn_label_list | |
726 | { | |
727 | struct insn_label_list *next; | |
728 | symbolS *label; | |
729 | }; | |
730 | ||
731 | static struct insn_label_list *insn_labels; | |
732 | static struct insn_label_list *free_insn_labels; | |
733 | ||
734 | static void mips_clear_insn_labels PARAMS ((void)); | |
735 | ||
736 | static inline void | |
737 | mips_clear_insn_labels () | |
738 | { | |
739 | register struct insn_label_list **pl; | |
740 | ||
741 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
742 | ; | |
743 | *pl = insn_labels; | |
744 | insn_labels = NULL; | |
745 | } | |
746 | \f | |
3d3c5039 ILT |
747 | static char *expr_end; |
748 | ||
867a58b3 ILT |
749 | /* Expressions which appear in instructions. These are set by |
750 | mips_ip. */ | |
751 | ||
3d3c5039 ILT |
752 | static expressionS imm_expr; |
753 | static expressionS offset_expr; | |
867a58b3 ILT |
754 | |
755 | /* Relocs associated with imm_expr and offset_expr. */ | |
756 | ||
3d3c5039 ILT |
757 | static bfd_reloc_code_real_type imm_reloc; |
758 | static bfd_reloc_code_real_type offset_reloc; | |
759 | ||
867a58b3 ILT |
760 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
761 | ||
762 | static boolean imm_unmatched_hi; | |
763 | ||
8728fa92 ILT |
764 | /* These are set by mips16_ip if an explicit extension is used. */ |
765 | ||
766 | static boolean mips16_small, mips16_ext; | |
767 | ||
3d3c5039 ILT |
768 | /* |
769 | * This function is called once, at assembler startup time. It should | |
770 | * set up all the tables, etc. that the MD part of the assembler will need. | |
771 | */ | |
772 | void | |
670a50eb | 773 | md_begin () |
3d3c5039 | 774 | { |
0dd2d296 | 775 | boolean ok = false; |
604633ae | 776 | register const char *retval = NULL; |
670a50eb | 777 | register unsigned int i = 0; |
3d3c5039 | 778 | |
3c83da8a | 779 | if (mips_opts.isa == -1) |
8358c818 | 780 | { |
8c63448a ILT |
781 | const char *cpu; |
782 | char *a = NULL; | |
783 | ||
784 | cpu = TARGET_CPU; | |
785 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
786 | { | |
787 | a = xmalloc (sizeof TARGET_CPU); | |
788 | strcpy (a, TARGET_CPU); | |
789 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
790 | cpu = a; | |
791 | } | |
792 | ||
793 | if (strcmp (cpu, "mips") == 0) | |
794 | { | |
3c83da8a | 795 | mips_opts.isa = 1; |
4bb0cc41 ILT |
796 | if (mips_cpu == -1) |
797 | mips_cpu = 3000; | |
8c63448a | 798 | } |
5c6f5923 GRK |
799 | else if (strcmp (cpu, "r3900") == 0 |
800 | || strcmp (cpu, "mipsr3900") == 0) | |
801 | { | |
802 | mips_opts.isa = 1; | |
803 | if (mips_cpu == -1) | |
804 | mips_cpu = 3900; | |
805 | if (mips_3900 == -1) | |
806 | mips_3900 = 1; | |
807 | } | |
8c63448a ILT |
808 | else if (strcmp (cpu, "r6000") == 0 |
809 | || strcmp (cpu, "mips2") == 0) | |
810 | { | |
3c83da8a | 811 | mips_opts.isa = 2; |
4bb0cc41 ILT |
812 | if (mips_cpu == -1) |
813 | mips_cpu = 6000; | |
8c63448a ILT |
814 | } |
815 | else if (strcmp (cpu, "mips64") == 0 | |
816 | || strcmp (cpu, "r4000") == 0 | |
817 | || strcmp (cpu, "mips3") == 0) | |
818 | { | |
3c83da8a | 819 | mips_opts.isa = 3; |
4bb0cc41 ILT |
820 | if (mips_cpu == -1) |
821 | mips_cpu = 4000; | |
8c63448a ILT |
822 | } |
823 | else if (strcmp (cpu, "r4400") == 0) | |
824 | { | |
3c83da8a | 825 | mips_opts.isa = 3; |
4bb0cc41 ILT |
826 | if (mips_cpu == -1) |
827 | mips_cpu = 4400; | |
8c63448a ILT |
828 | } |
829 | else if (strcmp (cpu, "mips64orion") == 0 | |
830 | || strcmp (cpu, "r4600") == 0) | |
831 | { | |
3c83da8a | 832 | mips_opts.isa = 3; |
4bb0cc41 ILT |
833 | if (mips_cpu == -1) |
834 | mips_cpu = 4600; | |
8c63448a | 835 | } |
b2b8c24e ILT |
836 | else if (strcmp (cpu, "r4650") == 0) |
837 | { | |
3c83da8a | 838 | mips_opts.isa = 3; |
b2b8c24e ILT |
839 | if (mips_cpu == -1) |
840 | mips_cpu = 4650; | |
841 | if (mips_4650 == -1) | |
842 | mips_4650 = 1; | |
843 | } | |
c625fc23 JSC |
844 | else if (strcmp (cpu, "mips64vr4300") == 0) |
845 | { | |
3c83da8a | 846 | mips_opts.isa = 3; |
c625fc23 JSC |
847 | if (mips_cpu == -1) |
848 | mips_cpu = 4300; | |
849 | } | |
850 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
851 | { | |
3c83da8a | 852 | mips_opts.isa = 3; |
c625fc23 JSC |
853 | if (mips_cpu == -1) |
854 | mips_cpu = 4100; | |
855 | if (mips_4100 == -1) | |
856 | mips_4100 = 1; | |
857 | } | |
e532b44c ILT |
858 | else if (strcmp (cpu, "r4010") == 0) |
859 | { | |
3c83da8a | 860 | mips_opts.isa = 2; |
e532b44c ILT |
861 | if (mips_cpu == -1) |
862 | mips_cpu = 4010; | |
863 | if (mips_4010 == -1) | |
864 | mips_4010 = 1; | |
865 | } | |
517078c1 ILT |
866 | else if (strcmp (cpu, "r5000") == 0 |
867 | || strcmp (cpu, "mips64vr5000") == 0) | |
868 | { | |
3c83da8a | 869 | mips_opts.isa = 4; |
517078c1 ILT |
870 | if (mips_cpu == -1) |
871 | mips_cpu = 5000; | |
872 | } | |
276c2d7d GRK |
873 | /* start-sanitize-r5900 */ |
874 | else if (strcmp (cpu, "r5900") == 0 | |
875 | || strcmp (cpu, "mips64vr5900") == 0 | |
876 | || strcmp (cpu, "mips64vr5900el") == 0) | |
877 | { | |
3c83da8a | 878 | mips_opts.isa = 3; |
276c2d7d GRK |
879 | if (mips_cpu == -1) |
880 | mips_cpu = 5900; | |
16262668 | 881 | if (mips_5900 == -1) |
276c2d7d GRK |
882 | mips_5900 = 1; |
883 | } | |
884 | /* end-sanitize-r5900 */ | |
d8a1c247 KR |
885 | else if (strcmp (cpu, "r8000") == 0 |
886 | || strcmp (cpu, "mips4") == 0) | |
887 | { | |
3c83da8a | 888 | mips_opts.isa = 4; |
d8a1c247 KR |
889 | if (mips_cpu == -1) |
890 | mips_cpu = 8000; | |
891 | } | |
892 | else if (strcmp (cpu, "r10000") == 0) | |
893 | { | |
3c83da8a | 894 | mips_opts.isa = 4; |
d8a1c247 KR |
895 | if (mips_cpu == -1) |
896 | mips_cpu = 10000; | |
897 | } | |
cc5703cd ILT |
898 | else if (strcmp (cpu, "mips16") == 0) |
899 | { | |
3c83da8a | 900 | mips_opts.isa = 3; |
cc5703cd ILT |
901 | if (mips_cpu == -1) |
902 | mips_cpu = 0; /* FIXME */ | |
903 | } | |
8358c818 | 904 | else |
8c63448a | 905 | { |
3c83da8a | 906 | mips_opts.isa = 1; |
4bb0cc41 ILT |
907 | if (mips_cpu == -1) |
908 | mips_cpu = 3000; | |
8c63448a ILT |
909 | } |
910 | ||
911 | if (a != NULL) | |
912 | free (a); | |
8358c818 ILT |
913 | } |
914 | ||
3c83da8a | 915 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
916 | { |
917 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 918 | mips_opts.mips16 = 1; |
cc5703cd | 919 | else |
3c83da8a | 920 | mips_opts.mips16 = 0; |
cc5703cd ILT |
921 | } |
922 | ||
b2b8c24e ILT |
923 | if (mips_4650 < 0) |
924 | mips_4650 = 0; | |
925 | ||
e532b44c ILT |
926 | if (mips_4010 < 0) |
927 | mips_4010 = 0; | |
928 | ||
c625fc23 JSC |
929 | if (mips_4100 < 0) |
930 | mips_4100 = 0; | |
931 | ||
276c2d7d GRK |
932 | /* start-sanitize-r5900 */ |
933 | if (mips_5900 < 0) | |
934 | mips_5900 = 0; | |
935 | /* end-sanitize-r5900 */ | |
936 | ||
5c6f5923 GRK |
937 | if (mips_3900 < 0) |
938 | mips_3900 = 0; | |
939 | ||
940 | if (mips_4010 | |
941 | || mips_cpu == 4300 | |
942 | || mips_3900 | |
943 | ) | |
944 | hilo_interlocks = 1; | |
e532b44c | 945 | else |
5c6f5923 GRK |
946 | hilo_interlocks = 0; |
947 | ||
948 | if (mips_opts.isa >= 2 | |
949 | || mips_3900 | |
950 | ) | |
951 | gpr_interlocks = 1; | |
952 | else | |
953 | gpr_interlocks = 0; | |
e532b44c | 954 | |
efec4a28 | 955 | /* Itbl support may require additional care here. */ |
ca296aab | 956 | if (mips_cpu == 4300) |
344a8d61 JSC |
957 | cop_interlocks = 1; |
958 | else | |
959 | cop_interlocks = 0; | |
960 | ||
3c83da8a | 961 | if (mips_opts.isa < 2 && mips_trap) |
8ea7f4e8 ILT |
962 | as_bad ("trap exception not supported at ISA 1"); |
963 | ||
3c83da8a | 964 | switch (mips_opts.isa) |
97f99d11 ILT |
965 | { |
966 | case 1: | |
967 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
968 | break; | |
969 | case 2: | |
970 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
971 | break; | |
972 | case 3: | |
973 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
974 | break; | |
d8a1c247 KR |
975 | case 4: |
976 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
977 | break; | |
97f99d11 ILT |
978 | } |
979 | if (! ok) | |
980 | as_warn ("Could not set architecture and machine"); | |
981 | ||
3c83da8a | 982 | file_mips_isa = mips_opts.isa; |
1051c97f | 983 | |
13fe1379 ILT |
984 | op_hash = hash_new (); |
985 | ||
670a50eb ILT |
986 | for (i = 0; i < NUMOPCODES;) |
987 | { | |
988 | const char *name = mips_opcodes[i].name; | |
989 | ||
604633ae | 990 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 991 | if (retval != NULL) |
670a50eb ILT |
992 | { |
993 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
994 | mips_opcodes[i].name, retval); | |
995 | as_fatal ("Broken assembler. No assembly attempted."); | |
996 | } | |
997 | do | |
998 | { | |
8358c818 ILT |
999 | if (mips_opcodes[i].pinfo != INSN_MACRO |
1000 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
1001 | != mips_opcodes[i].match)) | |
670a50eb ILT |
1002 | { |
1003 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
1004 | mips_opcodes[i].name, mips_opcodes[i].args); | |
1005 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 1006 | } |
670a50eb ILT |
1007 | ++i; |
1008 | } | |
1009 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1010 | } |
1011 | ||
cc5703cd ILT |
1012 | mips16_op_hash = hash_new (); |
1013 | ||
1014 | i = 0; | |
1015 | while (i < bfd_mips16_num_opcodes) | |
1016 | { | |
1017 | const char *name = mips16_opcodes[i].name; | |
1018 | ||
1019 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1020 | if (retval != NULL) | |
1021 | as_fatal ("internal error: can't hash `%s': %s\n", | |
1022 | mips16_opcodes[i].name, retval); | |
1023 | do | |
1024 | { | |
1025 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1026 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1027 | != mips16_opcodes[i].match)) | |
1028 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
1029 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1030 | ++i; | |
1031 | } | |
1032 | while (i < bfd_mips16_num_opcodes | |
1033 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1034 | } | |
1035 | ||
ebf28372 ILT |
1036 | /* We add all the general register names to the symbol table. This |
1037 | helps us detect invalid uses of them. */ | |
1038 | for (i = 0; i < 32; i++) | |
1039 | { | |
1040 | char buf[5]; | |
1041 | ||
1042 | sprintf (buf, "$%d", i); | |
1043 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1044 | &zero_address_frag)); | |
1045 | } | |
1046 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1047 | &zero_address_frag)); | |
1048 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1049 | &zero_address_frag)); | |
1050 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1051 | &zero_address_frag)); | |
1052 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1053 | &zero_address_frag)); | |
1054 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1055 | &zero_address_frag)); | |
1056 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1057 | &zero_address_frag)); | |
1058 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1059 | &zero_address_frag)); | |
1060 | ||
4a1cb507 | 1061 | mips_no_prev_insn (false); |
becfe05e | 1062 | |
1aa6938e ILT |
1063 | mips_gprmask = 0; |
1064 | mips_cprmask[0] = 0; | |
1065 | mips_cprmask[1] = 0; | |
1066 | mips_cprmask[2] = 0; | |
1067 | mips_cprmask[3] = 0; | |
1068 | ||
8358c818 | 1069 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1070 | record_alignment (text_section, 2); |
8358c818 | 1071 | |
1dc1e798 KR |
1072 | if (USE_GLOBAL_POINTER_OPT) |
1073 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1074 | |
1dc1e798 KR |
1075 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1076 | { | |
08e17202 ILT |
1077 | /* On a native system, sections must be aligned to 16 byte |
1078 | boundaries. When configured for an embedded ELF target, we | |
1079 | don't bother. */ | |
1080 | if (strcmp (TARGET_OS, "elf") != 0) | |
1081 | { | |
1082 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1083 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1084 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1085 | } | |
1dc1e798 KR |
1086 | |
1087 | /* Create a .reginfo section for register masks and a .mdebug | |
1088 | section for debugging information. */ | |
1089 | { | |
1090 | segT seg; | |
1091 | subsegT subseg; | |
b3a64736 | 1092 | flagword flags; |
1dc1e798 KR |
1093 | segT sec; |
1094 | ||
1095 | seg = now_seg; | |
1096 | subseg = now_subseg; | |
1dc1e798 | 1097 | |
b3a64736 ILT |
1098 | /* The ABI says this section should be loaded so that the |
1099 | running program can access it. However, we don't load it | |
1100 | if we are configured for an embedded target */ | |
1101 | flags = SEC_READONLY | SEC_DATA; | |
1102 | if (strcmp (TARGET_OS, "elf") != 0) | |
1103 | flags |= SEC_ALLOC | SEC_LOAD; | |
1104 | ||
87178180 ILT |
1105 | if (! mips_64) |
1106 | { | |
1107 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1108 | |
b3a64736 ILT |
1109 | |
1110 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1111 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1112 | ||
f2a663d3 | 1113 | #ifdef OBJ_ELF |
87178180 | 1114 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1115 | #endif |
87178180 ILT |
1116 | } |
1117 | else | |
1118 | { | |
1119 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1120 | .reginfo section. */ | |
1121 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1122 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1123 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1124 | ||
1125 | #ifdef OBJ_ELF | |
1126 | /* Set up the option header. */ | |
1127 | { | |
1128 | Elf_Internal_Options opthdr; | |
1129 | char *f; | |
1130 | ||
1131 | opthdr.kind = ODK_REGINFO; | |
1132 | opthdr.size = (sizeof (Elf_External_Options) | |
1133 | + sizeof (Elf64_External_RegInfo)); | |
1134 | opthdr.section = 0; | |
1135 | opthdr.info = 0; | |
1136 | f = frag_more (sizeof (Elf_External_Options)); | |
1137 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1138 | (Elf_External_Options *) f); | |
1139 | ||
1140 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1141 | } | |
1142 | #endif | |
1143 | } | |
f2a663d3 | 1144 | |
739708fa KR |
1145 | if (ECOFF_DEBUGGING) |
1146 | { | |
1147 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1148 | (void) bfd_set_section_flags (stdoutput, sec, | |
1149 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1150 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1151 | } | |
0dd2d296 | 1152 | |
1dc1e798 KR |
1153 | subseg_set (seg, subseg); |
1154 | } | |
1155 | } | |
f2a663d3 | 1156 | |
739708fa KR |
1157 | if (! ECOFF_DEBUGGING) |
1158 | md_obj_begin (); | |
3d3c5039 ILT |
1159 | } |
1160 | ||
1161 | void | |
13fe1379 | 1162 | md_mips_end () |
3d3c5039 | 1163 | { |
739708fa KR |
1164 | if (! ECOFF_DEBUGGING) |
1165 | md_obj_end (); | |
3d3c5039 ILT |
1166 | } |
1167 | ||
1168 | void | |
670a50eb ILT |
1169 | md_assemble (str) |
1170 | char *str; | |
3d3c5039 | 1171 | { |
670a50eb | 1172 | struct mips_cl_insn insn; |
3d3c5039 | 1173 | |
5ac34ac3 | 1174 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1175 | imm_reloc = BFD_RELOC_UNUSED; |
1176 | imm_unmatched_hi = false; | |
5ac34ac3 | 1177 | offset_expr.X_op = O_absent; |
867a58b3 | 1178 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1179 | |
3c83da8a | 1180 | if (mips_opts.mips16) |
cc5703cd ILT |
1181 | mips16_ip (str, &insn); |
1182 | else | |
efec4a28 | 1183 | { |
9218cee0 | 1184 | mips_ip (str, &insn); |
efec4a28 DP |
1185 | DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", |
1186 | str, insn.insn_opcode)); | |
1187 | } | |
cc5703cd | 1188 | |
670a50eb ILT |
1189 | if (insn_error) |
1190 | { | |
1191 | as_bad ("%s `%s'", insn_error, str); | |
1192 | return; | |
1193 | } | |
cc5703cd | 1194 | |
670a50eb ILT |
1195 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1196 | { | |
3c83da8a | 1197 | if (mips_opts.mips16) |
cc5703cd ILT |
1198 | mips16_macro (&insn); |
1199 | else | |
1200 | macro (&insn); | |
3d3c5039 | 1201 | } |
670a50eb ILT |
1202 | else |
1203 | { | |
5ac34ac3 | 1204 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1205 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1206 | imm_unmatched_hi); | |
5ac34ac3 | 1207 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1208 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1209 | else |
867a58b3 | 1210 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1211 | } |
1212 | } | |
1213 | ||
cc5703cd ILT |
1214 | /* See whether instruction IP reads register REG. CLASS is the type |
1215 | of register. */ | |
becfe05e ILT |
1216 | |
1217 | static int | |
cc5703cd | 1218 | insn_uses_reg (ip, reg, class) |
becfe05e | 1219 | struct mips_cl_insn *ip; |
604633ae | 1220 | unsigned int reg; |
cc5703cd | 1221 | enum mips_regclass class; |
becfe05e | 1222 | { |
cc5703cd ILT |
1223 | if (class == MIPS16_REG) |
1224 | { | |
3c83da8a | 1225 | assert (mips_opts.mips16); |
cc5703cd ILT |
1226 | reg = mips16_to_32_reg_map[reg]; |
1227 | class = MIPS_GR_REG; | |
1228 | } | |
1229 | ||
becfe05e | 1230 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1231 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1232 | return 0; |
1233 | ||
cc5703cd | 1234 | if (class == MIPS_FP_REG) |
becfe05e | 1235 | { |
3c83da8a | 1236 | assert (! mips_opts.mips16); |
becfe05e ILT |
1237 | /* If we are called with either $f0 or $f1, we must check $f0. |
1238 | This is not optimal, because it will introduce an unnecessary | |
1239 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1240 | need to distinguish reading both $f0 and $f1 or just one of | |
1241 | them. Note that we don't have to check the other way, | |
1242 | because there is no instruction that sets both $f0 and $f1 | |
1243 | and requires a delay. */ | |
1244 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1245 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1246 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1247 | return 1; |
1248 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1249 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1250 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1251 | return 1; |
1252 | } | |
3c83da8a | 1253 | else if (! mips_opts.mips16) |
becfe05e ILT |
1254 | { |
1255 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1256 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1257 | return 1; | |
1258 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1259 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1260 | return 1; | |
1261 | } | |
cc5703cd ILT |
1262 | else |
1263 | { | |
1264 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1265 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1266 | & MIPS16OP_MASK_RX)] | |
1267 | == reg)) | |
cc5703cd ILT |
1268 | return 1; |
1269 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1270 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1271 | & MIPS16OP_MASK_RY)] | |
1272 | == reg)) | |
cc5703cd ILT |
1273 | return 1; |
1274 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1275 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1276 | & MIPS16OP_MASK_MOVE32Z)] | |
1277 | == reg)) | |
cc5703cd ILT |
1278 | return 1; |
1279 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1280 | return 1; | |
1281 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1282 | return 1; | |
1283 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1284 | return 1; | |
1285 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1286 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1287 | & MIPS16OP_MASK_REGR32) == reg) | |
1288 | return 1; | |
1289 | } | |
becfe05e ILT |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
fb251650 ILT |
1294 | /* This function returns true if modifying a register requires a |
1295 | delay. */ | |
1296 | ||
1297 | static int | |
1298 | reg_needs_delay (reg) | |
1299 | int reg; | |
1300 | { | |
1301 | unsigned long prev_pinfo; | |
1302 | ||
1303 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1304 | if (! mips_opts.noreorder |
1305 | && mips_opts.isa < 4 | |
fb251650 | 1306 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1307 | || (! gpr_interlocks |
fb251650 ILT |
1308 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1309 | { | |
1310 | /* A load from a coprocessor or from memory. All load | |
1311 | delays delay the use of general register rt for one | |
1312 | instruction on the r3000. The r6000 and r4000 use | |
1313 | interlocks. */ | |
efec4a28 | 1314 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1315 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1316 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1317 | return 1; | |
1318 | } | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | ||
3c83da8a JW |
1323 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1324 | handle them specially, such as generating jalx instructions when | |
1325 | needed. We also make them odd for the duration of the assembly, in | |
1326 | order to generate the right sort of code. We will make them even | |
1327 | in the adjust_symtab routine, while leaving them marked. This is | |
1328 | convenient for the debugger and the disassembler. The linker knows | |
1329 | to make them odd again. */ | |
1330 | ||
1331 | static void | |
1332 | mips16_mark_labels () | |
1333 | { | |
1334 | if (mips_opts.mips16) | |
1335 | { | |
1336 | struct insn_label_list *l; | |
1337 | ||
1338 | for (l = insn_labels; l != NULL; l = l->next) | |
1339 | { | |
68952421 | 1340 | #ifdef OBJ_ELF |
3c83da8a JW |
1341 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1342 | S_SET_OTHER (l->label, STO_MIPS16); | |
1343 | #endif | |
1344 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1345 | ++l->label->sy_value.X_add_number; | |
1346 | } | |
1347 | } | |
1348 | } | |
1349 | ||
0dd2d296 ILT |
1350 | /* Output an instruction. PLACE is where to put the instruction; if |
1351 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1352 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1353 | used with RELOC_TYPE. */ | |
3d3c5039 | 1354 | |
3d3c5039 | 1355 | static void |
867a58b3 | 1356 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1357 | char *place; |
670a50eb ILT |
1358 | struct mips_cl_insn *ip; |
1359 | expressionS *address_expr; | |
1360 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1361 | boolean unmatched_hi; |
3d3c5039 | 1362 | { |
1aa6938e | 1363 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1364 | char *f; |
becfe05e ILT |
1365 | fixS *fixp; |
1366 | int nops = 0; | |
3d3c5039 | 1367 | |
3c83da8a JW |
1368 | /* Mark instruction labels in mips16 mode. */ |
1369 | if (mips_opts.mips16) | |
1370 | mips16_mark_labels (); | |
fbcfacb7 | 1371 | |
1aa6938e ILT |
1372 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1373 | pinfo = ip->insn_mo->pinfo; | |
1374 | ||
3c83da8a | 1375 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1376 | { |
4a1cb507 ILT |
1377 | int prev_prev_nop; |
1378 | ||
becfe05e | 1379 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1380 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1381 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1382 | (1) a load from memory delay |
1383 | (2) a load from a coprocessor delay | |
1384 | (3) an unconditional branch delay | |
1385 | (4) a conditional branch delay | |
1386 | (5) a move to coprocessor register delay | |
1387 | (6) a load coprocessor register from memory delay | |
1388 | (7) a coprocessor condition code delay | |
1389 | (8) a HI/LO special register delay | |
becfe05e ILT |
1390 | |
1391 | There are a lot of optimizations we could do that we don't. | |
1392 | In particular, we do not, in general, reorder instructions. | |
1393 | If you use gcc with optimization, it will reorder | |
1394 | instructions and generally do much more optimization then we | |
1395 | do here; repeating all that work in the assembler would only | |
1396 | benefit hand written assembly code, and does not seem worth | |
1397 | it. */ | |
1398 | ||
1399 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1400 | #define emit_nop() \ |
3c83da8a | 1401 | (mips_opts.mips16 \ |
cc5703cd ILT |
1402 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1403 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1404 | |
1405 | /* The previous insn might require a delay slot, depending upon | |
1406 | the contents of the current insn. */ | |
3c83da8a JW |
1407 | if (! mips_opts.mips16 |
1408 | && mips_opts.isa < 4 | |
5af96dce ILT |
1409 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1410 | && ! cop_interlocks) | |
5c6f5923 | 1411 | || (! gpr_interlocks |
d8a1c247 | 1412 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1413 | { |
1414 | /* A load from a coprocessor or from memory. All load | |
1415 | delays delay the use of general register rt for one | |
1416 | instruction on the r3000. The r6000 and r4000 use | |
1417 | interlocks. */ | |
efec4a28 | 1418 | /* Itbl support may require additional care here. */ |
1aa6938e | 1419 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1420 | if (mips_optimize == 0 |
1421 | || insn_uses_reg (ip, | |
1422 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1423 | & OP_MASK_RT), | |
cc5703cd | 1424 | MIPS_GR_REG)) |
becfe05e ILT |
1425 | ++nops; |
1426 | } | |
3c83da8a JW |
1427 | else if (! mips_opts.mips16 |
1428 | && mips_opts.isa < 4 | |
5af96dce ILT |
1429 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1430 | && ! cop_interlocks) | |
3c83da8a | 1431 | || (mips_opts.isa < 2 |
d8a1c247 | 1432 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1433 | { |
1434 | /* A generic coprocessor delay. The previous instruction | |
1435 | modified a coprocessor general or control register. If | |
1436 | it modified a control register, we need to avoid any | |
1437 | coprocessor instruction (this is probably not always | |
1438 | required, but it sometimes is). If it modified a general | |
1439 | register, we avoid using that register. | |
1440 | ||
8358c818 ILT |
1441 | On the r6000 and r4000 loading a coprocessor register |
1442 | from memory is interlocked, and does not require a delay. | |
1443 | ||
becfe05e ILT |
1444 | This case is not handled very well. There is no special |
1445 | knowledge of CP0 handling, and the coprocessors other | |
1446 | than the floating point unit are not distinguished at | |
1447 | all. */ | |
efec4a28 DP |
1448 | /* Itbl support may require additional care here. FIXME! |
1449 | Need to modify this to include knowledge about | |
1450 | user specified delays! */ | |
1aa6938e | 1451 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1452 | { |
0aa07269 ILT |
1453 | if (mips_optimize == 0 |
1454 | || insn_uses_reg (ip, | |
8358c818 ILT |
1455 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1456 | & OP_MASK_FT), | |
cc5703cd | 1457 | MIPS_FP_REG)) |
becfe05e ILT |
1458 | ++nops; |
1459 | } | |
1aa6938e | 1460 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1461 | { |
0aa07269 ILT |
1462 | if (mips_optimize == 0 |
1463 | || insn_uses_reg (ip, | |
8358c818 ILT |
1464 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1465 | & OP_MASK_FS), | |
cc5703cd | 1466 | MIPS_FP_REG)) |
becfe05e ILT |
1467 | ++nops; |
1468 | } | |
1469 | else | |
1470 | { | |
1471 | /* We don't know exactly what the previous instruction | |
1472 | does. If the current instruction uses a coprocessor | |
1473 | register, we must insert a NOP. If previous | |
1474 | instruction may set the condition codes, and the | |
1475 | current instruction uses them, we must insert two | |
1476 | NOPS. */ | |
efec4a28 | 1477 | /* Itbl support may require additional care here. */ |
0aa07269 | 1478 | if (mips_optimize == 0 |
1aa6938e ILT |
1479 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1480 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1481 | nops += 2; |
1aa6938e | 1482 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1483 | ++nops; |
1484 | } | |
1485 | } | |
3c83da8a JW |
1486 | else if (! mips_opts.mips16 |
1487 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1488 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1489 | && ! cop_interlocks) | |
becfe05e ILT |
1490 | { |
1491 | /* The previous instruction sets the coprocessor condition | |
1492 | codes, but does not require a general coprocessor delay | |
1493 | (this means it is a floating point comparison | |
1494 | instruction). If this instruction uses the condition | |
1495 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1496 | /* Itbl support may require additional care here. */ |
0aa07269 | 1497 | if (mips_optimize == 0 |
1aa6938e | 1498 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1499 | ++nops; |
1500 | } | |
1aa6938e | 1501 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1502 | { |
1503 | /* The previous instruction reads the LO register; if the | |
1504 | current instruction writes to the LO register, we must | |
517078c1 | 1505 | insert two NOPS. Some newer processors have interlocks. */ |
5c6f5923 | 1506 | if (! hilo_interlocks |
b2b8c24e ILT |
1507 | && (mips_optimize == 0 |
1508 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1509 | nops += 2; |
1510 | } | |
1511 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1512 | { | |
1513 | /* The previous instruction reads the HI register; if the | |
1514 | current instruction writes to the HI register, we must | |
517078c1 | 1515 | insert a NOP. Some newer processors have interlocks. */ |
5c6f5923 | 1516 | if (! hilo_interlocks |
b2b8c24e ILT |
1517 | && (mips_optimize == 0 |
1518 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1519 | nops += 2; |
1520 | } | |
1521 | ||
4a1cb507 ILT |
1522 | /* If the previous instruction was in a noreorder section, then |
1523 | we don't want to insert the nop after all. */ | |
efec4a28 | 1524 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1525 | if (prev_insn_unreordered) |
1526 | nops = 0; | |
1527 | ||
becfe05e ILT |
1528 | /* There are two cases which require two intervening |
1529 | instructions: 1) setting the condition codes using a move to | |
1530 | coprocessor instruction which requires a general coprocessor | |
1531 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1532 | or LO register and then writing to it (except on processors |
1533 | which have interlocks). If we are not already emitting a NOP | |
1534 | instruction, we must check for these cases compared to the | |
1535 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1536 | if ((! mips_opts.mips16 |
1537 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1538 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1539 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1540 | && (pinfo & INSN_READ_COND_CODE) | |
1541 | && ! cop_interlocks) | |
1542 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1543 | && (pinfo & INSN_WRITE_LO) | |
5c6f5923 | 1544 | && ! hilo_interlocks) |
4a1cb507 ILT |
1545 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1546 | && (pinfo & INSN_WRITE_HI) | |
5c6f5923 | 1547 | && ! hilo_interlocks)) |
4a1cb507 ILT |
1548 | prev_prev_nop = 1; |
1549 | else | |
1550 | prev_prev_nop = 0; | |
1551 | ||
1552 | if (prev_prev_insn_unreordered) | |
1553 | prev_prev_nop = 0; | |
1554 | ||
1555 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1556 | ++nops; |
1557 | ||
0dd2d296 ILT |
1558 | /* If we are being given a nop instruction, don't bother with |
1559 | one of the nops we would otherwise output. This will only | |
1560 | happen when a nop instruction is used with mips_optimize set | |
1561 | to 0. */ | |
4a1cb507 | 1562 | if (nops > 0 |
3c83da8a JW |
1563 | && ! mips_opts.noreorder |
1564 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1565 | --nops; |
1566 | ||
becfe05e | 1567 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1568 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1569 | { |
5af96dce ILT |
1570 | fragS *old_frag; |
1571 | unsigned long old_frag_offset; | |
8c63448a | 1572 | int i; |
fbcfacb7 | 1573 | struct insn_label_list *l; |
8c63448a | 1574 | |
5af96dce ILT |
1575 | old_frag = frag_now; |
1576 | old_frag_offset = frag_now_fix (); | |
1577 | ||
8c63448a | 1578 | for (i = 0; i < nops; i++) |
becfe05e | 1579 | emit_nop (); |
5af96dce | 1580 | |
af255ca0 | 1581 | if (listing) |
546f5536 ILT |
1582 | { |
1583 | listing_prev_line (); | |
1584 | /* We may be at the start of a variant frag. In case we | |
1585 | are, make sure there is enough space for the frag | |
1586 | after the frags created by listing_prev_line. The | |
1587 | argument to frag_grow here must be at least as large | |
1588 | as the argument to all other calls to frag_grow in | |
1589 | this file. We don't have to worry about being in the | |
1590 | middle of a variant frag, because the variants insert | |
1591 | all needed nop instructions themselves. */ | |
1592 | frag_grow (40); | |
1593 | } | |
5af96dce | 1594 | |
fbcfacb7 | 1595 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1596 | { |
fbcfacb7 ILT |
1597 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1598 | l->label->sy_frag = frag_now; | |
1599 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1600 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1601 | if (mips_opts.mips16) |
fbcfacb7 | 1602 | ++l->label->sy_value.X_add_number; |
becfe05e | 1603 | } |
5af96dce ILT |
1604 | |
1605 | #ifndef NO_ECOFF_DEBUGGING | |
1606 | if (ECOFF_DEBUGGING) | |
1607 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1608 | #endif | |
becfe05e | 1609 | } |
4a1cb507 ILT |
1610 | else if (prev_nop_frag != NULL) |
1611 | { | |
1612 | /* We have a frag holding nops we may be able to remove. If | |
1613 | we don't need any nops, we can decrease the size of | |
1614 | prev_nop_frag by the size of one instruction. If we do | |
1615 | need some nops, we count them in prev_nops_required. */ | |
1616 | if (prev_nop_frag_since == 0) | |
1617 | { | |
1618 | if (nops == 0) | |
1619 | { | |
3c83da8a | 1620 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1621 | --prev_nop_frag_holds; |
1622 | } | |
1623 | else | |
1624 | prev_nop_frag_required += nops; | |
1625 | } | |
1626 | else | |
1627 | { | |
1628 | if (prev_prev_nop == 0) | |
1629 | { | |
3c83da8a | 1630 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1631 | --prev_nop_frag_holds; |
1632 | } | |
1633 | else | |
1634 | ++prev_nop_frag_required; | |
1635 | } | |
1636 | ||
1637 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1638 | prev_nop_frag = NULL; | |
1639 | ||
1640 | ++prev_nop_frag_since; | |
1641 | ||
1642 | /* Sanity check: by the time we reach the second instruction | |
1643 | after prev_nop_frag, we should have used up all the nops | |
1644 | one way or another. */ | |
1645 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1646 | } | |
becfe05e | 1647 | } |
4a1cb507 | 1648 | |
cc5703cd ILT |
1649 | if (reloc_type > BFD_RELOC_UNUSED) |
1650 | { | |
1651 | /* We need to set up a variant frag. */ | |
3c83da8a | 1652 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1653 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1654 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1655 | mips16_small, mips16_ext, |
1656 | (prev_pinfo | |
1657 | & INSN_UNCOND_BRANCH_DELAY), | |
1658 | (prev_insn_reloc_type | |
1659 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1660 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1661 | (char *) NULL); |
1662 | } | |
1663 | else if (place != NULL) | |
0dd2d296 | 1664 | f = place; |
3c83da8a JW |
1665 | else if (mips_opts.mips16 |
1666 | && ! ip->use_extend | |
1667 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1668 | { |
1669 | /* Make sure there is enough room to swap this instruction with | |
1670 | a following jump instruction. */ | |
1671 | frag_grow (6); | |
1672 | f = frag_more (2); | |
1673 | } | |
cc5703cd | 1674 | else |
035936da | 1675 | { |
3c83da8a JW |
1676 | if (mips_opts.mips16 |
1677 | && mips_opts.noreorder | |
035936da ILT |
1678 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
1679 | as_warn ("extended instruction in delay slot"); | |
1680 | ||
1681 | f = frag_more (4); | |
1682 | } | |
1683 | ||
becfe05e | 1684 | fixp = NULL; |
cc5703cd | 1685 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1686 | { |
5ac34ac3 | 1687 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1688 | { |
1689 | switch (reloc_type) | |
1690 | { | |
3d3c5039 | 1691 | case BFD_RELOC_32: |
670a50eb ILT |
1692 | ip->insn_opcode |= address_expr->X_add_number; |
1693 | break; | |
3d3c5039 ILT |
1694 | |
1695 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1696 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1697 | break; | |
3d3c5039 ILT |
1698 | |
1699 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1700 | if ((address_expr->X_add_number & 3) != 0) |
1701 | as_bad ("jump to misaligned address (0x%lx)", | |
1702 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1703 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1704 | break; | |
1705 | ||
cc5703cd | 1706 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1707 | if ((address_expr->X_add_number & 3) != 0) |
1708 | as_bad ("jump to misaligned address (0x%lx)", | |
1709 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1710 | ip->insn_opcode |= |
1711 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1712 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1713 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1714 | break; | |
1715 | ||
3d3c5039 | 1716 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1717 | goto need_reloc; |
3d3c5039 ILT |
1718 | |
1719 | default: | |
670a50eb | 1720 | internalError (); |
3d3c5039 | 1721 | } |
670a50eb ILT |
1722 | } |
1723 | else | |
1724 | { | |
3d3c5039 | 1725 | need_reloc: |
0dd2d296 ILT |
1726 | /* Don't generate a reloc if we are writing into a variant |
1727 | frag. */ | |
1728 | if (place == NULL) | |
867a58b3 ILT |
1729 | { |
1730 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1731 | address_expr, | |
1732 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1733 | reloc_type); | |
1734 | if (unmatched_hi) | |
1735 | { | |
1736 | struct mips_hi_fixup *hi_fixup; | |
1737 | ||
1738 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1739 | hi_fixup = ((struct mips_hi_fixup *) | |
1740 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1741 | hi_fixup->fixp = fixp; | |
1742 | hi_fixup->seg = now_seg; | |
1743 | hi_fixup->next = mips_hi_fixup_list; | |
1744 | mips_hi_fixup_list = hi_fixup; | |
1745 | } | |
1746 | } | |
3d3c5039 ILT |
1747 | } |
1748 | } | |
becfe05e | 1749 | |
3c83da8a | 1750 | if (! mips_opts.mips16) |
cc5703cd | 1751 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1752 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1753 | { | |
1754 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1755 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1756 | } | |
cc5703cd ILT |
1757 | else |
1758 | { | |
1759 | if (ip->use_extend) | |
1760 | { | |
1761 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1762 | f += 2; | |
1763 | } | |
1764 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1765 | } | |
670a50eb | 1766 | |
1aa6938e | 1767 | /* Update the register mask information. */ |
3c83da8a | 1768 | if (! mips_opts.mips16) |
cc5703cd ILT |
1769 | { |
1770 | if (pinfo & INSN_WRITE_GPR_D) | |
1771 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1772 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1773 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1774 | if (pinfo & INSN_READ_GPR_S) | |
1775 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1776 | if (pinfo & INSN_WRITE_GPR_31) | |
1777 | mips_gprmask |= 1 << 31; | |
1778 | if (pinfo & INSN_WRITE_FPR_D) | |
1779 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1780 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1781 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1782 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1783 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1784 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1785 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1786 | if (pinfo & INSN_COP) | |
1787 | { | |
efec4a28 DP |
1788 | /* We don't keep enough information to sort these cases out. |
1789 | The itbl support does keep this information however, although | |
1790 | we currently don't support itbl fprmats as part of the cop | |
1791 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1792 | } |
1793 | /* Never set the bit for $0, which is always zero. */ | |
1794 | mips_gprmask &=~ 1 << 0; | |
1795 | } | |
1796 | else | |
1aa6938e | 1797 | { |
cc5703cd ILT |
1798 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1799 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1800 | & MIPS16OP_MASK_RX); | |
1801 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1802 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1803 | & MIPS16OP_MASK_RY); | |
1804 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1805 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1806 | & MIPS16OP_MASK_RZ); | |
1807 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1808 | mips_gprmask |= 1 << TREG; | |
1809 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1810 | mips_gprmask |= 1 << SP; | |
1811 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1812 | mips_gprmask |= 1 << RA; | |
1813 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1814 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1815 | if (pinfo & MIPS16_INSN_READ_Z) | |
1816 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1817 | & MIPS16OP_MASK_MOVE32Z); | |
1818 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1819 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1820 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1821 | } |
1aa6938e | 1822 | |
3c83da8a | 1823 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1824 | { |
becfe05e ILT |
1825 | /* Filling the branch delay slot is more complex. We try to |
1826 | switch the branch with the previous instruction, which we can | |
1827 | do if the previous instruction does not set up a condition | |
1828 | that the branch tests and if the branch is not itself the | |
1829 | target of any branch. */ | |
1aa6938e ILT |
1830 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1831 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1832 | { |
0aa07269 | 1833 | if (mips_optimize < 2 |
19ed8960 ILT |
1834 | /* If we have seen .set volatile or .set nomove, don't |
1835 | optimize. */ | |
3c83da8a | 1836 | || mips_opts.nomove != 0 |
4e95866e ILT |
1837 | /* If we had to emit any NOP instructions, then we |
1838 | already know we can not swap. */ | |
1839 | || nops != 0 | |
becfe05e ILT |
1840 | /* If we don't even know the previous insn, we can not |
1841 | swap. */ | |
1842 | || ! prev_insn_valid | |
1843 | /* If the previous insn is already in a branch delay | |
1844 | slot, then we can not swap. */ | |
1845 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1846 | /* If the previous previous insn was in a .set |
1847 | noreorder, we can't swap. Actually, the MIPS | |
1848 | assembler will swap in this situation. However, gcc | |
1849 | configured -with-gnu-as will generate code like | |
1850 | .set noreorder | |
1851 | lw $4,XXX | |
1852 | .set reorder | |
1853 | INSN | |
1854 | bne $4,$0,foo | |
1855 | in which we can not swap the bne and INSN. If gcc is | |
1856 | not configured -with-gnu-as, it does not output the | |
1857 | .set pseudo-ops. We don't have to check | |
1858 | prev_insn_unreordered, because prev_insn_valid will | |
1859 | be 0 in that case. We don't want to use | |
1860 | prev_prev_insn_valid, because we do want to be able | |
1861 | to swap at the start of a function. */ | |
1862 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1863 | /* If the branch is itself the target of a branch, we |
1864 | can not swap. We cheat on this; all we check for is | |
1865 | whether there is a label on this instruction. If | |
1866 | there are any branches to anything other than a | |
1867 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1868 | || insn_labels != NULL |
777ad64d | 1869 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1870 | can not do the swap. This does not apply to the |
1871 | mips16, which uses variant frags for different | |
1872 | purposes. */ | |
3c83da8a | 1873 | || (! mips_opts.mips16 |
cc5703cd | 1874 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
1875 | /* If the branch reads the condition codes, we don't |
1876 | even try to swap, because in the sequence | |
1877 | ctc1 $X,$31 | |
1878 | INSN | |
1879 | INSN | |
1880 | bc1t LABEL | |
1881 | we can not swap, and I don't feel like handling that | |
1882 | case. */ | |
3c83da8a JW |
1883 | || (! mips_opts.mips16 |
1884 | && mips_opts.isa < 4 | |
d8a1c247 | 1885 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1886 | /* We can not swap with an instruction that requires a |
1887 | delay slot, becase the target of the branch might | |
1888 | interfere with that instruction. */ | |
3c83da8a JW |
1889 | || (! mips_opts.mips16 |
1890 | && mips_opts.isa < 4 | |
d8a1c247 | 1891 | && (prev_pinfo |
efec4a28 | 1892 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1893 | & (INSN_LOAD_COPROC_DELAY |
1894 | | INSN_COPROC_MOVE_DELAY | |
1895 | | INSN_WRITE_COND_CODE))) | |
5c6f5923 | 1896 | || (! hilo_interlocks |
b2b8c24e ILT |
1897 | && (prev_pinfo |
1898 | & (INSN_READ_LO | |
1899 | | INSN_READ_HI))) | |
5c6f5923 GRK |
1900 | || (! mips_opts.mips16 |
1901 | && ! gpr_interlocks | |
1902 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
1903 | || (! mips_opts.mips16 |
1904 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
1905 | /* Itbl support may require additional care here. */ |
1906 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 1907 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1908 | || (prev_pinfo |
6e8dda9c ILT |
1909 | & (INSN_UNCOND_BRANCH_DELAY |
1910 | | INSN_COND_BRANCH_DELAY | |
1911 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1912 | /* We do not swap with a trap instruction, since it |
1913 | complicates trap handlers to have the trap | |
1914 | instruction be in a delay slot. */ | |
1aa6938e | 1915 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1916 | /* If the branch reads a register that the previous |
1917 | instruction sets, we can not swap. */ | |
3c83da8a | 1918 | || (! mips_opts.mips16 |
cc5703cd | 1919 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
1920 | && insn_uses_reg (ip, |
1921 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1922 | & OP_MASK_RT), | |
cc5703cd | 1923 | MIPS_GR_REG)) |
3c83da8a | 1924 | || (! mips_opts.mips16 |
cc5703cd | 1925 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1926 | && insn_uses_reg (ip, |
1927 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1928 | & OP_MASK_RD), | |
cc5703cd | 1929 | MIPS_GR_REG)) |
3c83da8a | 1930 | || (mips_opts.mips16 |
cc5703cd ILT |
1931 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
1932 | && insn_uses_reg (ip, | |
1933 | ((prev_insn.insn_opcode | |
1934 | >> MIPS16OP_SH_RX) | |
1935 | & MIPS16OP_MASK_RX), | |
1936 | MIPS16_REG)) | |
1937 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1938 | && insn_uses_reg (ip, | |
1939 | ((prev_insn.insn_opcode | |
1940 | >> MIPS16OP_SH_RY) | |
1941 | & MIPS16OP_MASK_RY), | |
1942 | MIPS16_REG)) | |
1943 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1944 | && insn_uses_reg (ip, | |
1945 | ((prev_insn.insn_opcode | |
1946 | >> MIPS16OP_SH_RZ) | |
1947 | & MIPS16OP_MASK_RZ), | |
1948 | MIPS16_REG)) | |
1949 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1950 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1951 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1952 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1953 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1954 | && insn_uses_reg (ip, | |
1955 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1956 | insn_opcode), | |
1957 | MIPS_GR_REG)))) | |
1849d646 ILT |
1958 | /* If the branch writes a register that the previous |
1959 | instruction sets, we can not swap (we know that | |
1960 | branches write only to RD or to $31). */ | |
3c83da8a | 1961 | || (! mips_opts.mips16 |
cc5703cd | 1962 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 1963 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1964 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1965 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1966 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1967 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1968 | & OP_MASK_RT) | |
1969 | == 31)))) | |
3c83da8a | 1970 | || (! mips_opts.mips16 |
cc5703cd | 1971 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 1972 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1973 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1974 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1975 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1976 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1977 | & OP_MASK_RD) | |
1978 | == 31)))) | |
3c83da8a | 1979 | || (mips_opts.mips16 |
cc5703cd ILT |
1980 | && (pinfo & MIPS16_INSN_WRITE_31) |
1981 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1982 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1983 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1984 | == RA)))) | |
becfe05e ILT |
1985 | /* If the branch writes a register that the previous |
1986 | instruction reads, we can not swap (we know that | |
1987 | branches only write to RD or to $31). */ | |
3c83da8a | 1988 | || (! mips_opts.mips16 |
cc5703cd | 1989 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1990 | && insn_uses_reg (&prev_insn, |
1991 | ((ip->insn_opcode >> OP_SH_RD) | |
1992 | & OP_MASK_RD), | |
cc5703cd | 1993 | MIPS_GR_REG)) |
3c83da8a | 1994 | || (! mips_opts.mips16 |
cc5703cd ILT |
1995 | && (pinfo & INSN_WRITE_GPR_31) |
1996 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 1997 | || (mips_opts.mips16 |
cc5703cd ILT |
1998 | && (pinfo & MIPS16_INSN_WRITE_31) |
1999 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2000 | /* If we are generating embedded PIC code, the branch |
2001 | might be expanded into a sequence which uses $at, so | |
2002 | we can't swap with an instruction which reads it. */ | |
2003 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2004 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2005 | /* If the previous previous instruction has a load |
2006 | delay, and sets a register that the branch reads, we | |
2007 | can not swap. */ | |
3c83da8a JW |
2008 | || (! mips_opts.mips16 |
2009 | && mips_opts.isa < 4 | |
efec4a28 | 2010 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2011 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2012 | || (! gpr_interlocks |
d8a1c247 KR |
2013 | && (prev_prev_insn.insn_mo->pinfo |
2014 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2015 | && insn_uses_reg (ip, |
2016 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2017 | & OP_MASK_RT), | |
cc5703cd | 2018 | MIPS_GR_REG)) |
d31a3f5e ILT |
2019 | /* If one instruction sets a condition code and the |
2020 | other one uses a condition code, we can not swap. */ | |
2021 | || ((pinfo & INSN_READ_COND_CODE) | |
2022 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2023 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2024 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2025 | /* If the previous instruction uses the PC, we can not | |
2026 | swap. */ | |
3c83da8a | 2027 | || (mips_opts.mips16 |
cc5703cd ILT |
2028 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2029 | /* If the previous instruction was extended, we can not | |
2030 | swap. */ | |
3c83da8a | 2031 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2032 | /* If the previous instruction had a fixup in mips16 |
2033 | mode, we can not swap. This normally means that the | |
2034 | previous instruction was a 4 byte branch anyhow. */ | |
3c83da8a | 2035 | || (mips_opts.mips16 && prev_insn_fixp)) |
becfe05e ILT |
2036 | { |
2037 | /* We could do even better for unconditional branches to | |
2038 | portions of this object file; we could pick up the | |
2039 | instruction at the destination, put it in the delay | |
2040 | slot, and bump the destination address. */ | |
2041 | emit_nop (); | |
2042 | /* Update the previous insn information. */ | |
2043 | prev_prev_insn = *ip; | |
2044 | prev_insn.insn_mo = &dummy_opcode; | |
2045 | } | |
2046 | else | |
2047 | { | |
becfe05e | 2048 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2049 | if (! mips_opts.mips16) |
cc5703cd ILT |
2050 | { |
2051 | char *prev_f; | |
2052 | char temp[4]; | |
2053 | ||
2054 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2055 | memcpy (temp, prev_f, 4); | |
2056 | memcpy (prev_f, f, 4); | |
2057 | memcpy (f, temp, 4); | |
2058 | if (prev_insn_fixp) | |
2059 | { | |
2060 | prev_insn_fixp->fx_frag = frag_now; | |
2061 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2062 | } | |
2063 | if (fixp) | |
2064 | { | |
2065 | fixp->fx_frag = prev_insn_frag; | |
2066 | fixp->fx_where = prev_insn_where; | |
2067 | } | |
2068 | } | |
cc5703cd | 2069 | else |
becfe05e | 2070 | { |
cc5703cd ILT |
2071 | char *prev_f; |
2072 | char temp[2]; | |
2073 | ||
2074 | assert (prev_insn_fixp == NULL); | |
2075 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2076 | memcpy (temp, prev_f, 2); | |
2077 | memcpy (prev_f, f, 2); | |
2078 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2079 | { |
2080 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2081 | memcpy (f, temp, 2); | |
2082 | } | |
cc5703cd ILT |
2083 | else |
2084 | { | |
2085 | memcpy (f, f + 2, 2); | |
2086 | memcpy (f + 2, temp, 2); | |
2087 | } | |
2088 | if (fixp) | |
2089 | { | |
2090 | fixp->fx_frag = prev_insn_frag; | |
2091 | fixp->fx_where = prev_insn_where; | |
2092 | } | |
becfe05e | 2093 | } |
cc5703cd | 2094 | |
becfe05e ILT |
2095 | /* Update the previous insn information; leave prev_insn |
2096 | unchanged. */ | |
2097 | prev_prev_insn = *ip; | |
2098 | } | |
2099 | prev_insn_is_delay_slot = 1; | |
2100 | ||
2101 | /* If that was an unconditional branch, forget the previous | |
2102 | insn information. */ | |
1aa6938e | 2103 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2104 | { |
2105 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2106 | prev_insn.insn_mo = &dummy_opcode; | |
2107 | } | |
a677feeb ILT |
2108 | |
2109 | prev_insn_fixp = NULL; | |
2110 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2111 | prev_insn_extended = 0; | |
becfe05e | 2112 | } |
1aa6938e | 2113 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2114 | { |
2115 | /* We don't yet optimize a branch likely. What we should do | |
2116 | is look at the target, copy the instruction found there | |
2117 | into the delay slot, and increment the branch to jump to | |
2118 | the next instruction. */ | |
2119 | emit_nop (); | |
2120 | /* Update the previous insn information. */ | |
2121 | prev_prev_insn = *ip; | |
2122 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2123 | prev_insn_fixp = NULL; |
2124 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2125 | prev_insn_extended = 0; | |
8358c818 | 2126 | } |
becfe05e | 2127 | else |
670a50eb | 2128 | { |
becfe05e ILT |
2129 | /* Update the previous insn information. */ |
2130 | if (nops > 0) | |
2131 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2132 | else | |
2133 | prev_prev_insn = prev_insn; | |
2134 | prev_insn = *ip; | |
2135 | ||
2136 | /* Any time we see a branch, we always fill the delay slot | |
2137 | immediately; since this insn is not a branch, we know it | |
2138 | is not in a delay slot. */ | |
2139 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2140 | |
2141 | prev_insn_fixp = fixp; | |
2142 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2143 | if (mips_opts.mips16) |
a677feeb ILT |
2144 | prev_insn_extended = (ip->use_extend |
2145 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2146 | } |
2147 | ||
4e95866e ILT |
2148 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2149 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2150 | prev_insn_frag = frag_now; |
2151 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2152 | prev_insn_valid = 1; |
2153 | } | |
fbcfacb7 | 2154 | else if (place == NULL) |
a677feeb | 2155 | { |
fbcfacb7 | 2156 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2157 | reordering, in order to determine the base address for mips16 |
2158 | PC relative relocs. */ | |
4a1cb507 | 2159 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2160 | prev_insn = *ip; |
2161 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2162 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2163 | prev_insn_unreordered = 1; | |
a677feeb | 2164 | } |
3d3c5039 | 2165 | |
becfe05e | 2166 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2167 | mips_clear_insn_labels (); |
becfe05e ILT |
2168 | } |
2169 | ||
2170 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2171 | label. If PRESERVE is non-zero, it remembers enough information to |
2172 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2173 | |
2174 | static void | |
4a1cb507 ILT |
2175 | mips_no_prev_insn (preserve) |
2176 | int preserve; | |
becfe05e | 2177 | { |
4a1cb507 ILT |
2178 | if (! preserve) |
2179 | { | |
2180 | prev_insn.insn_mo = &dummy_opcode; | |
2181 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2182 | prev_nop_frag = NULL; | |
2183 | prev_nop_frag_holds = 0; | |
2184 | prev_nop_frag_required = 0; | |
2185 | prev_nop_frag_since = 0; | |
2186 | } | |
becfe05e ILT |
2187 | prev_insn_valid = 0; |
2188 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2189 | prev_insn_unreordered = 0; |
cc5703cd | 2190 | prev_insn_extended = 0; |
a677feeb | 2191 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2192 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2193 | mips_clear_insn_labels (); |
becfe05e ILT |
2194 | } |
2195 | ||
2196 | /* This function must be called whenever we turn on noreorder or emit | |
2197 | something other than instructions. It inserts any NOPS which might | |
2198 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2199 | kept for the previous instructions. The INSNS parameter is true if |
2200 | instructions are to follow. */ | |
becfe05e ILT |
2201 | |
2202 | static void | |
fbcfacb7 ILT |
2203 | mips_emit_delays (insns) |
2204 | boolean insns; | |
becfe05e | 2205 | { |
3c83da8a | 2206 | if (! mips_opts.noreorder) |
becfe05e | 2207 | { |
4a1cb507 | 2208 | int nops; |
becfe05e | 2209 | |
4a1cb507 | 2210 | nops = 0; |
3c83da8a JW |
2211 | if ((! mips_opts.mips16 |
2212 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2213 | && (! cop_interlocks |
2214 | && (prev_insn.insn_mo->pinfo | |
2215 | & (INSN_LOAD_COPROC_DELAY | |
2216 | | INSN_COPROC_MOVE_DELAY | |
2217 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2218 | || (! hilo_interlocks |
b2b8c24e ILT |
2219 | && (prev_insn.insn_mo->pinfo |
2220 | & (INSN_READ_LO | |
2221 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2222 | || (! mips_opts.mips16 |
2223 | && ! gpr_interlocks | |
2224 | && (prev_insn.insn_mo->pinfo | |
2225 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2226 | || (! mips_opts.mips16 |
2227 | && mips_opts.isa < 2 | |
8358c818 | 2228 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2229 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2230 | { |
efec4a28 | 2231 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2232 | ++nops; |
3c83da8a JW |
2233 | if ((! mips_opts.mips16 |
2234 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2235 | && (! cop_interlocks |
2236 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2237 | || (! hilo_interlocks |
b2b8c24e ILT |
2238 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2239 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2240 | ++nops; |
2241 | ||
2242 | if (prev_insn_unreordered) | |
2243 | nops = 0; | |
becfe05e | 2244 | } |
3c83da8a JW |
2245 | else if ((! mips_opts.mips16 |
2246 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2247 | && (! cop_interlocks |
2248 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2249 | || (! hilo_interlocks |
b2b8c24e ILT |
2250 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2251 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2252 | { |
efec4a28 | 2253 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2254 | if (! prev_prev_insn_unreordered) |
2255 | ++nops; | |
2256 | } | |
2257 | ||
2258 | if (nops > 0) | |
670a50eb | 2259 | { |
fbcfacb7 ILT |
2260 | struct insn_label_list *l; |
2261 | ||
4a1cb507 ILT |
2262 | if (insns) |
2263 | { | |
2264 | /* Record the frag which holds the nop instructions, so | |
2265 | that we can remove them if we don't need them. */ | |
3c83da8a | 2266 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2267 | prev_nop_frag = frag_now; |
2268 | prev_nop_frag_holds = nops; | |
2269 | prev_nop_frag_required = 0; | |
2270 | prev_nop_frag_since = 0; | |
2271 | } | |
2272 | ||
2273 | for (; nops > 0; --nops) | |
2274 | emit_nop (); | |
2275 | ||
2276 | if (insns) | |
2277 | { | |
2278 | /* Move on to a new frag, so that it is safe to simply | |
2279 | decrease the size of prev_nop_frag. */ | |
2280 | frag_wane (frag_now); | |
2281 | frag_new (0); | |
2282 | } | |
2283 | ||
fbcfacb7 | 2284 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2285 | { |
fbcfacb7 ILT |
2286 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2287 | l->label->sy_frag = frag_now; | |
2288 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2289 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2290 | if (mips_opts.mips16) |
fbcfacb7 | 2291 | ++l->label->sy_value.X_add_number; |
becfe05e | 2292 | } |
3d3c5039 ILT |
2293 | } |
2294 | } | |
0221ddf7 | 2295 | |
3c83da8a JW |
2296 | /* Mark instruction labels in mips16 mode. */ |
2297 | if (mips_opts.mips16 && insns) | |
2298 | mips16_mark_labels (); | |
fbcfacb7 | 2299 | |
4a1cb507 | 2300 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2301 | } |
2302 | ||
670a50eb ILT |
2303 | /* Build an instruction created by a macro expansion. This is passed |
2304 | a pointer to the count of instructions created so far, an | |
2305 | expression, the name of the instruction to build, an operand format | |
2306 | string, and corresponding arguments. */ | |
2307 | ||
1dc1e798 | 2308 | #ifdef USE_STDARG |
3d3c5039 | 2309 | static void |
0dd2d296 ILT |
2310 | macro_build (char *place, |
2311 | int *counter, | |
670a50eb | 2312 | expressionS * ep, |
3d3c5039 ILT |
2313 | const char *name, |
2314 | const char *fmt, | |
2315 | ...) | |
1dc1e798 | 2316 | #else |
3d3c5039 | 2317 | static void |
0dd2d296 ILT |
2318 | macro_build (place, counter, ep, name, fmt, va_alist) |
2319 | char *place; | |
3d3c5039 ILT |
2320 | int *counter; |
2321 | expressionS *ep; | |
2322 | const char *name; | |
2323 | const char *fmt; | |
2324 | va_dcl | |
1dc1e798 | 2325 | #endif |
3d3c5039 | 2326 | { |
670a50eb ILT |
2327 | struct mips_cl_insn insn; |
2328 | bfd_reloc_code_real_type r; | |
2329 | va_list args; | |
3d3c5039 | 2330 | |
1dc1e798 | 2331 | #ifdef USE_STDARG |
670a50eb | 2332 | va_start (args, fmt); |
3d3c5039 | 2333 | #else |
670a50eb | 2334 | va_start (args); |
3d3c5039 ILT |
2335 | #endif |
2336 | ||
670a50eb ILT |
2337 | /* |
2338 | * If the macro is about to expand into a second instruction, | |
2339 | * print a warning if needed. We need to pass ip as a parameter | |
2340 | * to generate a better warning message here... | |
2341 | */ | |
3c83da8a | 2342 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2343 | as_warn ("Macro instruction expanded into multiple instructions"); |
2344 | ||
0dd2d296 ILT |
2345 | if (place == NULL) |
2346 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2347 | |
3c83da8a | 2348 | if (mips_opts.mips16) |
cc5703cd ILT |
2349 | { |
2350 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2351 | va_end (args); | |
2352 | return; | |
2353 | } | |
2354 | ||
670a50eb ILT |
2355 | r = BFD_RELOC_UNUSED; |
2356 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2357 | assert (insn.insn_mo); | |
2358 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2359 | ||
9226253a | 2360 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 | 2361 | || insn.insn_mo->pinfo == INSN_MACRO |
5c6f5923 | 2362 | || ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2 |
3c83da8a | 2363 | && mips_opts.isa < 2) |
5c6f5923 | 2364 | || ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3 |
3c83da8a | 2365 | && mips_opts.isa < 3) |
5c6f5923 | 2366 | || ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4 |
3c83da8a | 2367 | && mips_opts.isa < 4) |
5c6f5923 GRK |
2368 | || ((insn.insn_mo->membership & INSN_ISA) == INSN_3900 |
2369 | && ! mips_3900) | |
2370 | || ((insn.insn_mo->membership & INSN_ISA) == INSN_4650 | |
c625fc23 | 2371 | && ! mips_4650) |
5c6f5923 | 2372 | || ((insn.insn_mo->membership & INSN_ISA) == INSN_4010 |
c625fc23 | 2373 | && ! mips_4010) |
5c6f5923 | 2374 | || ((insn.insn_mo->membership & INSN_ISA) == INSN_4100 |
276c2d7d GRK |
2375 | && ! mips_4100) |
2376 | /* start-sanitize-r5900 */ | |
5c6f5923 | 2377 | || ((insn.insn_mo->membership & INSN_ISA) == INSN_5900 |
276c2d7d GRK |
2378 | && ! mips_5900) |
2379 | /* end-sanitize-r5900 */ | |
2380 | ) | |
670a50eb ILT |
2381 | { |
2382 | ++insn.insn_mo; | |
2383 | assert (insn.insn_mo->name); | |
2384 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2385 | } |
670a50eb ILT |
2386 | insn.insn_opcode = insn.insn_mo->match; |
2387 | for (;;) | |
2388 | { | |
2389 | switch (*fmt++) | |
2390 | { | |
3d3c5039 | 2391 | case '\0': |
670a50eb | 2392 | break; |
3d3c5039 ILT |
2393 | |
2394 | case ',': | |
2395 | case '(': | |
2396 | case ')': | |
670a50eb | 2397 | continue; |
3d3c5039 ILT |
2398 | |
2399 | case 't': | |
2400 | case 'w': | |
918692a5 | 2401 | case 'E': |
670a50eb ILT |
2402 | insn.insn_opcode |= va_arg (args, int) << 16; |
2403 | continue; | |
3d3c5039 ILT |
2404 | |
2405 | case 'c': | |
2406 | case 'T': | |
2407 | case 'W': | |
670a50eb ILT |
2408 | insn.insn_opcode |= va_arg (args, int) << 16; |
2409 | continue; | |
3d3c5039 ILT |
2410 | |
2411 | case 'd': | |
918692a5 | 2412 | case 'G': |
670a50eb ILT |
2413 | insn.insn_opcode |= va_arg (args, int) << 11; |
2414 | continue; | |
3d3c5039 ILT |
2415 | |
2416 | case 'V': | |
2417 | case 'S': | |
670a50eb ILT |
2418 | insn.insn_opcode |= va_arg (args, int) << 11; |
2419 | continue; | |
3d3c5039 | 2420 | |
ff3a5c18 ILT |
2421 | case 'z': |
2422 | continue; | |
2423 | ||
3d3c5039 | 2424 | case '<': |
670a50eb ILT |
2425 | insn.insn_opcode |= va_arg (args, int) << 6; |
2426 | continue; | |
3d3c5039 ILT |
2427 | |
2428 | case 'D': | |
670a50eb ILT |
2429 | insn.insn_opcode |= va_arg (args, int) << 6; |
2430 | continue; | |
3d3c5039 | 2431 | |
918692a5 ILT |
2432 | case 'B': |
2433 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2434 | continue; | |
2435 | ||
3d3c5039 ILT |
2436 | case 'b': |
2437 | case 's': | |
2438 | case 'r': | |
2439 | case 'v': | |
670a50eb ILT |
2440 | insn.insn_opcode |= va_arg (args, int) << 21; |
2441 | continue; | |
3d3c5039 ILT |
2442 | |
2443 | case 'i': | |
2444 | case 'j': | |
2445 | case 'o': | |
9226253a | 2446 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2447 | assert (r == BFD_RELOC_MIPS_GPREL |
2448 | || r == BFD_RELOC_MIPS_LITERAL | |
2449 | || r == BFD_RELOC_LO16 | |
2450 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2451 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2452 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2453 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2454 | || (ep->X_op == O_subtract |
2455 | && now_seg == text_section | |
ecd4ca1c | 2456 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2457 | continue; |
3d3c5039 | 2458 | |
6e8dda9c | 2459 | case 'u': |
ecd4ca1c ILT |
2460 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2461 | assert (ep != NULL | |
2462 | && (ep->X_op == O_constant | |
2463 | || (ep->X_op == O_symbol | |
2464 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2465 | || r == BFD_RELOC_HI16 |
2466 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2467 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2468 | || (ep->X_op == O_subtract |
2469 | && now_seg == text_section | |
ecd4ca1c ILT |
2470 | && r == BFD_RELOC_PCREL_HI16_S))); |
2471 | if (ep->X_op == O_constant) | |
2472 | { | |
2473 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2474 | ep = NULL; | |
2475 | r = BFD_RELOC_UNUSED; | |
2476 | } | |
6e8dda9c ILT |
2477 | continue; |
2478 | ||
3d3c5039 | 2479 | case 'p': |
670a50eb ILT |
2480 | assert (ep != NULL); |
2481 | /* | |
2482 | * This allows macro() to pass an immediate expression for | |
2483 | * creating short branches without creating a symbol. | |
2484 | * Note that the expression still might come from the assembly | |
2485 | * input, in which case the value is not checked for range nor | |
2486 | * is a relocation entry generated (yuck). | |
2487 | */ | |
5ac34ac3 | 2488 | if (ep->X_op == O_constant) |
670a50eb ILT |
2489 | { |
2490 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2491 | ep = NULL; | |
2492 | } | |
2493 | else | |
2494 | r = BFD_RELOC_16_PCREL_S2; | |
2495 | continue; | |
3d3c5039 | 2496 | |
9226253a ILT |
2497 | case 'a': |
2498 | assert (ep != NULL); | |
2499 | r = BFD_RELOC_MIPS_JMP; | |
2500 | continue; | |
2501 | ||
3d3c5039 | 2502 | default: |
670a50eb | 2503 | internalError (); |
3d3c5039 | 2504 | } |
670a50eb | 2505 | break; |
3d3c5039 | 2506 | } |
670a50eb ILT |
2507 | va_end (args); |
2508 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2509 | ||
867a58b3 | 2510 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2511 | } |
2512 | ||
cc5703cd ILT |
2513 | static void |
2514 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2515 | char *place; | |
2516 | int *counter; | |
2517 | expressionS *ep; | |
2518 | const char *name; | |
2519 | const char *fmt; | |
2520 | va_list args; | |
2521 | { | |
2522 | struct mips_cl_insn insn; | |
2523 | bfd_reloc_code_real_type r; | |
2524 | ||
2525 | r = BFD_RELOC_UNUSED; | |
2526 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2527 | assert (insn.insn_mo); | |
2528 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2529 | ||
2530 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2531 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2532 | { | |
2533 | ++insn.insn_mo; | |
2534 | assert (insn.insn_mo->name); | |
2535 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2536 | } | |
2537 | ||
2538 | insn.insn_opcode = insn.insn_mo->match; | |
2539 | insn.use_extend = false; | |
2540 | ||
2541 | for (;;) | |
2542 | { | |
2543 | int c; | |
2544 | ||
2545 | c = *fmt++; | |
2546 | switch (c) | |
2547 | { | |
2548 | case '\0': | |
2549 | break; | |
2550 | ||
2551 | case ',': | |
2552 | case '(': | |
2553 | case ')': | |
2554 | continue; | |
2555 | ||
2556 | case 'y': | |
2557 | case 'w': | |
2558 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2559 | continue; | |
2560 | ||
2561 | case 'x': | |
2562 | case 'v': | |
2563 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2564 | continue; | |
2565 | ||
2566 | case 'z': | |
2567 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2568 | continue; | |
2569 | ||
2570 | case 'Z': | |
2571 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2572 | continue; | |
2573 | ||
2574 | case '0': | |
2575 | case 'S': | |
2576 | case 'P': | |
2577 | case 'R': | |
2578 | continue; | |
2579 | ||
2580 | case 'X': | |
2581 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2582 | continue; | |
2583 | ||
2584 | case 'Y': | |
2585 | { | |
2586 | int regno; | |
2587 | ||
2588 | regno = va_arg (args, int); | |
2589 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2590 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2591 | } | |
2592 | continue; | |
2593 | ||
2594 | case '<': | |
2595 | case '>': | |
2596 | case '4': | |
2597 | case '5': | |
2598 | case 'H': | |
2599 | case 'W': | |
2600 | case 'D': | |
2601 | case 'j': | |
2602 | case '8': | |
2603 | case 'V': | |
2604 | case 'C': | |
2605 | case 'U': | |
2606 | case 'k': | |
2607 | case 'K': | |
2608 | case 'p': | |
2609 | case 'q': | |
2610 | { | |
2611 | assert (ep != NULL); | |
2612 | ||
2613 | if (ep->X_op != O_constant) | |
2614 | r = BFD_RELOC_UNUSED + c; | |
2615 | else | |
2616 | { | |
15e69f98 ILT |
2617 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2618 | false, false, &insn.insn_opcode, | |
2619 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2620 | ep = NULL; |
2621 | r = BFD_RELOC_UNUSED; | |
2622 | } | |
2623 | } | |
2624 | continue; | |
2625 | ||
2626 | case '6': | |
2627 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2628 | continue; | |
2629 | } | |
2630 | ||
2631 | break; | |
2632 | } | |
2633 | ||
2634 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2635 | ||
2636 | append_insn (place, &insn, ep, r, false); | |
2637 | } | |
2638 | ||
3d3c5039 ILT |
2639 | /* |
2640 | * Generate a "lui" instruction. | |
2641 | */ | |
2642 | static void | |
0dd2d296 ILT |
2643 | macro_build_lui (place, counter, ep, regnum) |
2644 | char *place; | |
3d3c5039 ILT |
2645 | int *counter; |
2646 | expressionS *ep; | |
2647 | int regnum; | |
2648 | { | |
670a50eb ILT |
2649 | expressionS high_expr; |
2650 | struct mips_cl_insn insn; | |
2651 | bfd_reloc_code_real_type r; | |
2652 | CONST char *name = "lui"; | |
2653 | CONST char *fmt = "t,u"; | |
2654 | ||
3c83da8a | 2655 | assert (! mips_opts.mips16); |
cc5703cd | 2656 | |
0dd2d296 ILT |
2657 | if (place == NULL) |
2658 | high_expr = *ep; | |
2659 | else | |
2660 | { | |
2661 | high_expr.X_op = O_constant; | |
fb251650 | 2662 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2663 | } |
670a50eb | 2664 | |
5ac34ac3 | 2665 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2666 | { |
2667 | /* we can compute the instruction now without a relocation entry */ | |
2668 | if (high_expr.X_add_number & 0x8000) | |
2669 | high_expr.X_add_number += 0x10000; | |
2670 | high_expr.X_add_number = | |
2671 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2672 | r = BFD_RELOC_UNUSED; | |
2673 | } | |
2674 | else | |
0dd2d296 ILT |
2675 | { |
2676 | assert (ep->X_op == O_symbol); | |
2677 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2678 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2679 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2680 | r = BFD_RELOC_HI16_S; | |
2681 | } | |
670a50eb ILT |
2682 | |
2683 | /* | |
2684 | * If the macro is about to expand into a second instruction, | |
2685 | * print a warning if needed. We need to pass ip as a parameter | |
2686 | * to generate a better warning message here... | |
2687 | */ | |
3c83da8a | 2688 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2689 | as_warn ("Macro instruction expanded into multiple instructions"); |
2690 | ||
0dd2d296 ILT |
2691 | if (place == NULL) |
2692 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2693 | |
2694 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2695 | assert (insn.insn_mo); | |
2696 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2697 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2698 | ||
0dd2d296 | 2699 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2700 | if (r == BFD_RELOC_UNUSED) |
2701 | { | |
2702 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2703 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2704 | } |
2705 | else | |
867a58b3 | 2706 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2707 | } |
2708 | ||
2709 | /* set_at() | |
2710 | * Generates code to set the $at register to true (one) | |
2711 | * if reg is less than the immediate expression. | |
2712 | */ | |
2713 | static void | |
6e8dda9c | 2714 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2715 | int *counter; |
2716 | int reg; | |
6e8dda9c | 2717 | int unsignedp; |
3d3c5039 | 2718 | { |
5c6f5923 GRK |
2719 | if (imm_expr.X_op == O_constant |
2720 | && imm_expr.X_add_number >= -0x8000 | |
2721 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2722 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2723 | unsignedp ? "sltiu" : "slti", |
9226253a | 2724 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2725 | else |
670a50eb | 2726 | { |
d8a1c247 | 2727 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2728 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2729 | unsignedp ? "sltu" : "slt", |
2730 | "d,v,t", AT, reg, AT); | |
670a50eb | 2731 | } |
3d3c5039 ILT |
2732 | } |
2733 | ||
6e8dda9c | 2734 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2735 | |
2736 | static void | |
19ed8960 | 2737 | check_absolute_expr (ip, ex) |
3d3c5039 | 2738 | struct mips_cl_insn *ip; |
19ed8960 | 2739 | expressionS *ex; |
3d3c5039 | 2740 | { |
5c6f5923 GRK |
2741 | if (ex->X_op == O_big) |
2742 | as_bad ("unsupported large constant"); | |
2743 | else if (ex->X_op != O_constant) | |
670a50eb | 2744 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2745 | } |
2746 | ||
ff8716f5 JSC |
2747 | /* Count the leading zeroes by performing a binary chop. This is a |
2748 | bulky bit of source, but performance is a LOT better for the | |
2749 | majority of values than a simple loop to count the bits: | |
2750 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2751 | if ((v) & (1 << (31 - lcnt))) | |
2752 | break; | |
2753 | However it is not code size friendly, and the gain will drop a bit | |
2754 | on certain cached systems. | |
2755 | */ | |
2756 | #define COUNT_TOP_ZEROES(v) \ | |
2757 | (((v) & ~0xffff) == 0 \ | |
2758 | ? ((v) & ~0xff) == 0 \ | |
2759 | ? ((v) & ~0xf) == 0 \ | |
2760 | ? ((v) & ~0x3) == 0 \ | |
2761 | ? ((v) & ~0x1) == 0 \ | |
2762 | ? !(v) \ | |
2763 | ? 32 \ | |
2764 | : 31 \ | |
2765 | : 30 \ | |
2766 | : ((v) & ~0x7) == 0 \ | |
2767 | ? 29 \ | |
2768 | : 28 \ | |
2769 | : ((v) & ~0x3f) == 0 \ | |
2770 | ? ((v) & ~0x1f) == 0 \ | |
2771 | ? 27 \ | |
2772 | : 26 \ | |
2773 | : ((v) & ~0x7f) == 0 \ | |
2774 | ? 25 \ | |
2775 | : 24 \ | |
2776 | : ((v) & ~0xfff) == 0 \ | |
2777 | ? ((v) & ~0x3ff) == 0 \ | |
2778 | ? ((v) & ~0x1ff) == 0 \ | |
2779 | ? 23 \ | |
2780 | : 22 \ | |
2781 | : ((v) & ~0x7ff) == 0 \ | |
2782 | ? 21 \ | |
2783 | : 20 \ | |
2784 | : ((v) & ~0x3fff) == 0 \ | |
2785 | ? ((v) & ~0x1fff) == 0 \ | |
2786 | ? 19 \ | |
2787 | : 18 \ | |
2788 | : ((v) & ~0x7fff) == 0 \ | |
2789 | ? 17 \ | |
2790 | : 16 \ | |
2791 | : ((v) & ~0xffffff) == 0 \ | |
2792 | ? ((v) & ~0xfffff) == 0 \ | |
2793 | ? ((v) & ~0x3ffff) == 0 \ | |
2794 | ? ((v) & ~0x1ffff) == 0 \ | |
2795 | ? 15 \ | |
2796 | : 14 \ | |
2797 | : ((v) & ~0x7ffff) == 0 \ | |
2798 | ? 13 \ | |
2799 | : 12 \ | |
2800 | : ((v) & ~0x3fffff) == 0 \ | |
2801 | ? ((v) & ~0x1fffff) == 0 \ | |
2802 | ? 11 \ | |
2803 | : 10 \ | |
2804 | : ((v) & ~0x7fffff) == 0 \ | |
2805 | ? 9 \ | |
2806 | : 8 \ | |
2807 | : ((v) & ~0xfffffff) == 0 \ | |
2808 | ? ((v) & ~0x3ffffff) == 0 \ | |
2809 | ? ((v) & ~0x1ffffff) == 0 \ | |
2810 | ? 7 \ | |
2811 | : 6 \ | |
2812 | : ((v) & ~0x7ffffff) == 0 \ | |
2813 | ? 5 \ | |
2814 | : 4 \ | |
2815 | : ((v) & ~0x3fffffff) == 0 \ | |
2816 | ? ((v) & ~0x1fffffff) == 0 \ | |
2817 | ? 3 \ | |
2818 | : 2 \ | |
2819 | : ((v) & ~0x7fffffff) == 0 \ | |
2820 | ? 1 \ | |
2821 | : 0) | |
2822 | ||
3d3c5039 ILT |
2823 | /* load_register() |
2824 | * This routine generates the least number of instructions neccessary to load | |
2825 | * an absolute expression value into a register. | |
2826 | */ | |
2827 | static void | |
d8a1c247 | 2828 | load_register (counter, reg, ep, dbl) |
670a50eb | 2829 | int *counter; |
670a50eb ILT |
2830 | int reg; |
2831 | expressionS *ep; | |
d8a1c247 | 2832 | int dbl; |
3d3c5039 | 2833 | { |
c36a90ef ILT |
2834 | int freg; |
2835 | expressionS hi32, lo32; | |
847a01cd ILT |
2836 | |
2837 | if (ep->X_op != O_big) | |
6e8dda9c | 2838 | { |
847a01cd | 2839 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2840 | if (ep->X_add_number < 0x8000 |
2841 | && (ep->X_add_number >= 0 | |
2842 | || (ep->X_add_number >= -0x8000 | |
2843 | && (! dbl | |
2844 | || ! ep->X_unsigned | |
2845 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2846 | { |
2847 | /* We can handle 16 bit signed values with an addiu to | |
2848 | $zero. No need to ever use daddiu here, since $zero and | |
2849 | the result are always correct in 32 bit mode. */ | |
2850 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2851 | (int) BFD_RELOC_LO16); | |
2852 | return; | |
2853 | } | |
2854 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2855 | { | |
2856 | /* We can handle 16 bit unsigned values with an ori to | |
2857 | $zero. */ | |
2858 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2859 | (int) BFD_RELOC_LO16); | |
2860 | return; | |
2861 | } | |
98bfd087 ILT |
2862 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2863 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2864 | == ~ (offsetT) 0x7fffffff)) | |
2865 | && (! dbl | |
2866 | || ! ep->X_unsigned | |
2867 | || sizeof (ep->X_add_number) > 4 | |
2868 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 2869 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 2870 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 2871 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
2872 | && ! dbl |
2873 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
2874 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
2875 | { |
2876 | /* 32 bit values require an lui. */ | |
2877 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2878 | (int) BFD_RELOC_HI16); | |
2879 | if ((ep->X_add_number & 0xffff) != 0) | |
2880 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2881 | (int) BFD_RELOC_LO16); | |
2882 | return; | |
2883 | } | |
6e8dda9c | 2884 | } |
847a01cd ILT |
2885 | |
2886 | /* The value is larger than 32 bits. */ | |
2887 | ||
3c83da8a | 2888 | if (mips_opts.isa < 3) |
670a50eb | 2889 | { |
6e8dda9c | 2890 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2891 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2892 | (int) BFD_RELOC_LO16); |
847a01cd | 2893 | return; |
6e8dda9c | 2894 | } |
6e8dda9c | 2895 | |
847a01cd ILT |
2896 | if (ep->X_op != O_big) |
2897 | { | |
6e8dda9c | 2898 | hi32 = *ep; |
c36a90ef ILT |
2899 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2900 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2901 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2902 | lo32 = *ep; |
2903 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2904 | } |
847a01cd ILT |
2905 | else |
2906 | { | |
2907 | assert (ep->X_add_number > 2); | |
2908 | if (ep->X_add_number == 3) | |
2909 | generic_bignum[3] = 0; | |
2910 | else if (ep->X_add_number > 4) | |
2911 | as_bad ("Number larger than 64 bits"); | |
2912 | lo32.X_op = O_constant; | |
2913 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2914 | hi32.X_op = O_constant; | |
2915 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2916 | } | |
2917 | ||
d8a1c247 KR |
2918 | if (hi32.X_add_number == 0) |
2919 | freg = 0; | |
2920 | else | |
2921 | { | |
c36a90ef ILT |
2922 | int shift, bit; |
2923 | unsigned long hi, lo; | |
2924 | ||
fb251650 ILT |
2925 | if (hi32.X_add_number == 0xffffffff) |
2926 | { | |
2927 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2928 | { | |
c36a90ef ILT |
2929 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2930 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2931 | return; |
2932 | } | |
2933 | if (lo32.X_add_number & 0x80000000) | |
2934 | { | |
2935 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2936 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2937 | if (lo32.X_add_number & 0xffff) |
2938 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2939 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2940 | return; |
2941 | } | |
2942 | } | |
ff8716f5 | 2943 | |
c36a90ef ILT |
2944 | /* Check for 16bit shifted constant. We know that hi32 is |
2945 | non-zero, so start the mask on the first bit of the hi32 | |
2946 | value. */ | |
ff8716f5 JSC |
2947 | shift = 17; |
2948 | do | |
2949 | { | |
c36a90ef ILT |
2950 | unsigned long himask, lomask; |
2951 | ||
2952 | if (shift < 32) | |
2953 | { | |
2954 | himask = 0xffff >> (32 - shift); | |
2955 | lomask = (0xffff << shift) & 0xffffffff; | |
2956 | } | |
2957 | else | |
2958 | { | |
2959 | himask = 0xffff << (shift - 32); | |
2960 | lomask = 0; | |
2961 | } | |
2962 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2963 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2964 | { | |
2965 | expressionS tmp; | |
2966 | ||
2967 | tmp.X_op = O_constant; | |
2968 | if (shift < 32) | |
2969 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2970 | | (lo32.X_add_number >> shift)); | |
2971 | else | |
2972 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2973 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2974 | (int) BFD_RELOC_LO16); | |
2975 | macro_build ((char *) NULL, counter, NULL, | |
2976 | (shift >= 32) ? "dsll32" : "dsll", | |
2977 | "d,w,<", reg, reg, | |
2978 | (shift >= 32) ? shift - 32 : shift); | |
2979 | return; | |
2980 | } | |
ff8716f5 JSC |
2981 | shift++; |
2982 | } while (shift <= (64 - 16)); | |
2983 | ||
c36a90ef ILT |
2984 | /* Find the bit number of the lowest one bit, and store the |
2985 | shifted value in hi/lo. */ | |
2986 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
2987 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
2988 | if (lo != 0) | |
2989 | { | |
2990 | bit = 0; | |
2991 | while ((lo & 1) == 0) | |
2992 | { | |
2993 | lo >>= 1; | |
2994 | ++bit; | |
2995 | } | |
2996 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
2997 | hi >>= bit; | |
2998 | } | |
2999 | else | |
3000 | { | |
3001 | bit = 32; | |
3002 | while ((hi & 1) == 0) | |
3003 | { | |
3004 | hi >>= 1; | |
3005 | ++bit; | |
3006 | } | |
3007 | lo = hi; | |
3008 | hi = 0; | |
3009 | } | |
3010 | ||
3011 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3012 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3013 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3014 | { |
c36a90ef | 3015 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3016 | if (shift != 0) |
3017 | { | |
c36a90ef ILT |
3018 | expressionS tmp; |
3019 | ||
3020 | /* This instruction will set the register to be all | |
3021 | ones. */ | |
ff8716f5 | 3022 | tmp.X_op = O_constant; |
c36a90ef ILT |
3023 | tmp.X_add_number = (offsetT) -1; |
3024 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3025 | reg, 0, (int) BFD_RELOC_LO16); | |
3026 | if (bit != 0) | |
ff8716f5 | 3027 | { |
c36a90ef | 3028 | bit += shift; |
ff8716f5 | 3029 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3030 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3031 | "d,w,<", reg, reg, |
c36a90ef | 3032 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3033 | } |
c36a90ef ILT |
3034 | macro_build ((char *) NULL, counter, NULL, |
3035 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3036 | "d,w,<", reg, reg, | |
3037 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3038 | return; |
3039 | } | |
3040 | } | |
c36a90ef ILT |
3041 | |
3042 | /* Sign extend hi32 before calling load_register, because we can | |
3043 | generally get better code when we load a sign extended value. */ | |
3044 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3045 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3046 | load_register (counter, reg, &hi32, 0); |
3047 | freg = reg; | |
3048 | } | |
847a01cd | 3049 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3050 | { |
3051 | if (freg != 0) | |
3052 | { | |
3053 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3054 | freg, 0); | |
3055 | freg = reg; | |
3056 | } | |
3057 | } | |
847a01cd ILT |
3058 | else |
3059 | { | |
3060 | expressionS mid16; | |
3061 | ||
fb251650 ILT |
3062 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3063 | { | |
3064 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3065 | (int) BFD_RELOC_HI16); | |
3066 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3067 | reg, 0); |
fb251650 ILT |
3068 | return; |
3069 | } | |
3070 | ||
d8a1c247 KR |
3071 | if (freg != 0) |
3072 | { | |
3073 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3074 | freg, 16); | |
3075 | freg = reg; | |
3076 | } | |
847a01cd ILT |
3077 | mid16 = lo32; |
3078 | mid16.X_add_number >>= 16; | |
3079 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3080 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3081 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3082 | reg, 16); | |
d8a1c247 | 3083 | freg = reg; |
847a01cd ILT |
3084 | } |
3085 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3086 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3087 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3088 | } |
3089 | ||
0dd2d296 ILT |
3090 | /* Load an address into a register. */ |
3091 | ||
3092 | static void | |
3093 | load_address (counter, reg, ep) | |
3094 | int *counter; | |
3095 | int reg; | |
3096 | expressionS *ep; | |
3097 | { | |
3098 | char *p; | |
3099 | ||
3100 | if (ep->X_op != O_constant | |
3101 | && ep->X_op != O_symbol) | |
3102 | { | |
3103 | as_bad ("expression too complex"); | |
3104 | ep->X_op = O_constant; | |
3105 | } | |
3106 | ||
3107 | if (ep->X_op == O_constant) | |
d9aba805 | 3108 | { |
d8a1c247 | 3109 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3110 | return; |
3111 | } | |
3112 | ||
3113 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3114 | { |
3115 | /* If this is a reference to a GP relative symbol, we want | |
3116 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3117 | Otherwise we want | |
04cb3372 | 3118 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3119 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3120 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3121 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3122 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3123 | p = NULL; |
3124 | else | |
3125 | { | |
8ea7f4e8 | 3126 | frag_grow (20); |
0dd2d296 | 3127 | macro_build ((char *) NULL, counter, ep, |
3c83da8a | 3128 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3129 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3130 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3131 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3132 | mips_opts.warn_about_macros), | |
f59fb6ca | 3133 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3134 | } |
3135 | macro_build_lui (p, counter, ep, reg); | |
3136 | if (p != NULL) | |
3137 | p += 4; | |
3138 | macro_build (p, counter, ep, | |
3c83da8a | 3139 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3140 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3141 | } | |
fb251650 | 3142 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3143 | { |
3144 | expressionS ex; | |
3145 | ||
3146 | /* If this is a reference to an external symbol, we want | |
3147 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3148 | Otherwise we want | |
3149 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3150 | nop | |
3151 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3152 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3153 | ex.X_add_number = ep->X_add_number; |
3154 | ep->X_add_number = 0; | |
8ea7f4e8 | 3155 | frag_grow (20); |
0dd2d296 | 3156 | macro_build ((char *) NULL, counter, ep, |
3c83da8a | 3157 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
3158 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3159 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3160 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3161 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3162 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3163 | macro_build (p, counter, ep, |
3c83da8a | 3164 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3165 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3166 | if (ex.X_add_number != 0) | |
3167 | { | |
3168 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3169 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3170 | ex.X_op = O_constant; | |
fb251650 | 3171 | macro_build ((char *) NULL, counter, &ex, |
3c83da8a | 3172 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
3173 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3174 | } | |
3175 | } | |
3176 | else if (mips_pic == SVR4_PIC) | |
3177 | { | |
3178 | expressionS ex; | |
3179 | int off; | |
3180 | ||
3181 | /* This is the large GOT case. If this is a reference to an | |
3182 | external symbol, we want | |
3183 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3184 | addu $reg,$reg,$gp | |
3185 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3186 | Otherwise, for a reference to a local symbol, we want | |
3187 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3188 | nop | |
3189 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3190 | If there is a constant, it must be added in after. */ | |
3191 | ex.X_add_number = ep->X_add_number; | |
3192 | ep->X_add_number = 0; | |
3193 | if (reg_needs_delay (GP)) | |
3194 | off = 4; | |
3195 | else | |
3196 | off = 0; | |
3197 | frag_grow (32); | |
3198 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3199 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3200 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3c83da8a | 3201 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
3202 | "d,v,t", reg, reg, GP); |
3203 | macro_build ((char *) NULL, counter, ep, | |
3c83da8a | 3204 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
3205 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3206 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3207 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3208 | mips_opts.warn_about_macros), |
f59fb6ca | 3209 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3210 | if (off > 0) |
3211 | { | |
3212 | /* We need a nop before loading from $gp. This special | |
3213 | check is required because the lui which starts the main | |
3214 | instruction stream does not refer to $gp, and so will not | |
3215 | insert the nop which may be required. */ | |
3216 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3217 | p += 4; | |
3218 | } | |
3219 | macro_build (p, counter, ep, | |
3c83da8a | 3220 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
3221 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3222 | p += 4; | |
3223 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3224 | p += 4; | |
3225 | macro_build (p, counter, ep, | |
3c83da8a | 3226 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
3227 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3228 | if (ex.X_add_number != 0) | |
3229 | { | |
3230 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3231 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3232 | ex.X_op = O_constant; | |
3233 | macro_build ((char *) NULL, counter, &ex, | |
3c83da8a | 3234 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3235 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3236 | } | |
d9aba805 ILT |
3237 | } |
3238 | else if (mips_pic == EMBEDDED_PIC) | |
3239 | { | |
3240 | /* We always do | |
3241 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3242 | */ | |
3243 | macro_build ((char *) NULL, counter, ep, | |
3c83da8a | 3244 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
3245 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3246 | } | |
3247 | else | |
3248 | abort (); | |
0dd2d296 ILT |
3249 | } |
3250 | ||
3d3c5039 ILT |
3251 | /* |
3252 | * Build macros | |
3253 | * This routine implements the seemingly endless macro or synthesized | |
3254 | * instructions and addressing modes in the mips assembly language. Many | |
3255 | * of these macros are simple and are similar to each other. These could | |
3256 | * probably be handled by some kind of table or grammer aproach instead of | |
3257 | * this verbose method. Others are not simple macros but are more like | |
3258 | * optimizing code generation. | |
3259 | * One interesting optimization is when several store macros appear | |
3260 | * consecutivly that would load AT with the upper half of the same address. | |
3261 | * The ensuing load upper instructions are ommited. This implies some kind | |
3262 | * of global optimization. We currently only optimize within a single macro. | |
3263 | * For many of the load and store macros if the address is specified as a | |
3264 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3265 | * first load register 'at' with zero and use it as the base register. The | |
3266 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3267 | * we're missing. | |
3268 | */ | |
3269 | static void | |
3270 | macro (ip) | |
3271 | struct mips_cl_insn *ip; | |
3272 | { | |
670a50eb ILT |
3273 | register int treg, sreg, dreg, breg; |
3274 | int tempreg; | |
3275 | int mask; | |
3276 | int icnt = 0; | |
3277 | int used_at; | |
670a50eb ILT |
3278 | expressionS expr1; |
3279 | const char *s; | |
8358c818 | 3280 | const char *s2; |
670a50eb | 3281 | const char *fmt; |
8358c818 ILT |
3282 | int likely = 0; |
3283 | int dbl = 0; | |
3284 | int coproc = 0; | |
b2b8c24e | 3285 | int lr = 0; |
6e8dda9c | 3286 | offsetT maxnum; |
adcf2b9d | 3287 | int off; |
9226253a | 3288 | bfd_reloc_code_real_type r; |
0dd2d296 | 3289 | char *p; |
55933a58 | 3290 | int hold_mips_optimize; |
670a50eb | 3291 | |
3c83da8a | 3292 | assert (! mips_opts.mips16); |
cc5703cd | 3293 | |
670a50eb ILT |
3294 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3295 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3296 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3297 | mask = ip->insn_mo->mask; | |
3298 | ||
5ac34ac3 ILT |
3299 | expr1.X_op = O_constant; |
3300 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3301 | expr1.X_add_symbol = NULL; |
3302 | expr1.X_add_number = 1; | |
3303 | ||
3304 | switch (mask) | |
3305 | { | |
6e8dda9c ILT |
3306 | case M_DABS: |
3307 | dbl = 1; | |
3d3c5039 | 3308 | case M_ABS: |
6e8dda9c ILT |
3309 | /* bgez $a0,.+12 |
3310 | move v0,$a0 | |
3311 | sub v0,$zero,$a0 | |
3312 | */ | |
3d3c5039 | 3313 | |
fbcfacb7 | 3314 | mips_emit_delays (true); |
3c83da8a | 3315 | ++mips_opts.noreorder; |
0dd2d296 | 3316 | mips_any_noreorder = 1; |
3d3c5039 | 3317 | |
670a50eb | 3318 | expr1.X_add_number = 8; |
0dd2d296 | 3319 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3320 | if (dreg == sreg) |
0dd2d296 | 3321 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3322 | else |
0dd2d296 ILT |
3323 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3324 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3325 | dbl ? "dsub" : "sub", |
3326 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3327 | |
3c83da8a | 3328 | --mips_opts.noreorder; |
670a50eb | 3329 | return; |
3d3c5039 ILT |
3330 | |
3331 | case M_ADD_I: | |
8358c818 ILT |
3332 | s = "addi"; |
3333 | s2 = "add"; | |
3334 | goto do_addi; | |
3d3c5039 | 3335 | case M_ADDU_I: |
8358c818 ILT |
3336 | s = "addiu"; |
3337 | s2 = "addu"; | |
3338 | goto do_addi; | |
3339 | case M_DADD_I: | |
6e8dda9c | 3340 | dbl = 1; |
8358c818 ILT |
3341 | s = "daddi"; |
3342 | s2 = "dadd"; | |
3343 | goto do_addi; | |
3344 | case M_DADDU_I: | |
6e8dda9c | 3345 | dbl = 1; |
8358c818 ILT |
3346 | s = "daddiu"; |
3347 | s2 = "daddu"; | |
3348 | do_addi: | |
5c6f5923 GRK |
3349 | if (imm_expr.X_op == O_constant |
3350 | && imm_expr.X_add_number >= -0x8000 | |
3351 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3352 | { |
0dd2d296 | 3353 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3354 | (int) BFD_RELOC_LO16); |
670a50eb | 3355 | return; |
3d3c5039 | 3356 | } |
d8a1c247 | 3357 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3358 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3359 | break; |
3d3c5039 ILT |
3360 | |
3361 | case M_AND_I: | |
6e8dda9c ILT |
3362 | s = "andi"; |
3363 | s2 = "and"; | |
3364 | goto do_bit; | |
3d3c5039 | 3365 | case M_OR_I: |
6e8dda9c ILT |
3366 | s = "ori"; |
3367 | s2 = "or"; | |
3368 | goto do_bit; | |
3d3c5039 | 3369 | case M_NOR_I: |
6e8dda9c ILT |
3370 | s = ""; |
3371 | s2 = "nor"; | |
3372 | goto do_bit; | |
3d3c5039 | 3373 | case M_XOR_I: |
6e8dda9c ILT |
3374 | s = "xori"; |
3375 | s2 = "xor"; | |
3376 | do_bit: | |
5c6f5923 GRK |
3377 | if (imm_expr.X_op == O_constant |
3378 | && imm_expr.X_add_number >= 0 | |
3379 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3380 | { |
6e8dda9c | 3381 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3382 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3383 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3384 | else |
670a50eb | 3385 | { |
0dd2d296 ILT |
3386 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3387 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3388 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3389 | treg, treg, 0); |
3d3c5039 | 3390 | } |
6e8dda9c | 3391 | return; |
3d3c5039 | 3392 | } |
6e8dda9c | 3393 | |
d8a1c247 | 3394 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3395 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3396 | break; |
3d3c5039 ILT |
3397 | |
3398 | case M_BEQ_I: | |
8358c818 ILT |
3399 | s = "beq"; |
3400 | goto beq_i; | |
3401 | case M_BEQL_I: | |
3402 | s = "beql"; | |
3403 | likely = 1; | |
3404 | goto beq_i; | |
3d3c5039 | 3405 | case M_BNE_I: |
8358c818 ILT |
3406 | s = "bne"; |
3407 | goto beq_i; | |
3408 | case M_BNEL_I: | |
3409 | s = "bnel"; | |
3410 | likely = 1; | |
3411 | beq_i: | |
5c6f5923 | 3412 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3413 | { |
0dd2d296 ILT |
3414 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3415 | 0); | |
670a50eb ILT |
3416 | return; |
3417 | } | |
d8a1c247 | 3418 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3419 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3420 | break; |
3d3c5039 | 3421 | |
8358c818 ILT |
3422 | case M_BGEL: |
3423 | likely = 1; | |
3d3c5039 | 3424 | case M_BGE: |
670a50eb ILT |
3425 | if (treg == 0) |
3426 | { | |
0dd2d296 | 3427 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3428 | likely ? "bgezl" : "bgez", |
3429 | "s,p", sreg); | |
670a50eb | 3430 | return; |
3d3c5039 | 3431 | } |
9a7d824a ILT |
3432 | if (sreg == 0) |
3433 | { | |
0dd2d296 | 3434 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3435 | likely ? "blezl" : "blez", |
3436 | "s,p", treg); | |
9a7d824a ILT |
3437 | return; |
3438 | } | |
0dd2d296 ILT |
3439 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3440 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3441 | likely ? "beql" : "beq", |
3442 | "s,t,p", AT, 0); | |
670a50eb | 3443 | break; |
3d3c5039 | 3444 | |
8358c818 ILT |
3445 | case M_BGTL_I: |
3446 | likely = 1; | |
3d3c5039 | 3447 | case M_BGT_I: |
9a7d824a | 3448 | /* check for > max integer */ |
6e8dda9c | 3449 | maxnum = 0x7fffffff; |
5c6f5923 | 3450 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3451 | { |
3452 | maxnum <<= 16; | |
3453 | maxnum |= 0xffff; | |
3454 | maxnum <<= 16; | |
3455 | maxnum |= 0xffff; | |
3456 | } | |
5c6f5923 GRK |
3457 | if (imm_expr.X_op == O_constant |
3458 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3459 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3460 | { |
3461 | do_false: | |
3462 | /* result is always false */ | |
8358c818 ILT |
3463 | if (! likely) |
3464 | { | |
3465 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3466 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3467 | } |
3468 | else | |
3469 | { | |
3470 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3471 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3472 | "s,t,p", 0, 0); | |
8358c818 | 3473 | } |
9a7d824a ILT |
3474 | return; |
3475 | } | |
5c6f5923 GRK |
3476 | if (imm_expr.X_op != O_constant) |
3477 | as_bad ("Unsupported large constant"); | |
670a50eb ILT |
3478 | imm_expr.X_add_number++; |
3479 | /* FALLTHROUGH */ | |
3d3c5039 | 3480 | case M_BGE_I: |
8358c818 ILT |
3481 | case M_BGEL_I: |
3482 | if (mask == M_BGEL_I) | |
3483 | likely = 1; | |
5c6f5923 | 3484 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3485 | { |
0dd2d296 | 3486 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3487 | likely ? "bgezl" : "bgez", |
3488 | "s,p", sreg); | |
670a50eb | 3489 | return; |
3d3c5039 | 3490 | } |
5c6f5923 | 3491 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3492 | { |
0dd2d296 | 3493 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3494 | likely ? "bgtzl" : "bgtz", |
3495 | "s,p", sreg); | |
670a50eb | 3496 | return; |
3d3c5039 | 3497 | } |
6e8dda9c | 3498 | maxnum = 0x7fffffff; |
5c6f5923 | 3499 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3500 | { |
3501 | maxnum <<= 16; | |
3502 | maxnum |= 0xffff; | |
3503 | maxnum <<= 16; | |
3504 | maxnum |= 0xffff; | |
3505 | } | |
3506 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3507 | if (imm_expr.X_op == O_constant |
3508 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3509 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3510 | { |
3511 | do_true: | |
3512 | /* result is always true */ | |
3513 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3514 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3515 | return; |
3516 | } | |
6e8dda9c | 3517 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3518 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3519 | likely ? "beql" : "beq", |
3520 | "s,t,p", AT, 0); | |
670a50eb | 3521 | break; |
3d3c5039 | 3522 | |
8358c818 ILT |
3523 | case M_BGEUL: |
3524 | likely = 1; | |
3d3c5039 | 3525 | case M_BGEU: |
670a50eb | 3526 | if (treg == 0) |
9a7d824a ILT |
3527 | goto do_true; |
3528 | if (sreg == 0) | |
670a50eb | 3529 | { |
0dd2d296 | 3530 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3531 | likely ? "beql" : "beq", |
3532 | "s,t,p", 0, treg); | |
670a50eb | 3533 | return; |
3d3c5039 | 3534 | } |
0dd2d296 ILT |
3535 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3536 | treg); | |
3537 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3538 | likely ? "beql" : "beq", |
3539 | "s,t,p", AT, 0); | |
670a50eb | 3540 | break; |
3d3c5039 | 3541 | |
8358c818 ILT |
3542 | case M_BGTUL_I: |
3543 | likely = 1; | |
9a7d824a | 3544 | case M_BGTU_I: |
5c6f5923 GRK |
3545 | if (sreg == 0 |
3546 | || (mips_opts.isa < 3 | |
3547 | && imm_expr.X_op == O_constant | |
3548 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3549 | goto do_false; |
5c6f5923 GRK |
3550 | if (imm_expr.X_op != O_constant) |
3551 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3552 | imm_expr.X_add_number++; |
3553 | /* FALLTHROUGH */ | |
3d3c5039 | 3554 | case M_BGEU_I: |
8358c818 ILT |
3555 | case M_BGEUL_I: |
3556 | if (mask == M_BGEUL_I) | |
3557 | likely = 1; | |
5c6f5923 | 3558 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3559 | goto do_true; |
5c6f5923 | 3560 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3561 | { |
0dd2d296 | 3562 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3563 | likely ? "bnel" : "bne", |
3564 | "s,t,p", sreg, 0); | |
670a50eb | 3565 | return; |
3d3c5039 | 3566 | } |
6e8dda9c | 3567 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3568 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3569 | likely ? "beql" : "beq", |
3570 | "s,t,p", AT, 0); | |
670a50eb | 3571 | break; |
3d3c5039 | 3572 | |
8358c818 ILT |
3573 | case M_BGTL: |
3574 | likely = 1; | |
3d3c5039 | 3575 | case M_BGT: |
670a50eb ILT |
3576 | if (treg == 0) |
3577 | { | |
0dd2d296 | 3578 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3579 | likely ? "bgtzl" : "bgtz", |
3580 | "s,p", sreg); | |
670a50eb | 3581 | return; |
3d3c5039 | 3582 | } |
9a7d824a ILT |
3583 | if (sreg == 0) |
3584 | { | |
0dd2d296 | 3585 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3586 | likely ? "bltzl" : "bltz", |
3587 | "s,p", treg); | |
9a7d824a ILT |
3588 | return; |
3589 | } | |
0dd2d296 ILT |
3590 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3591 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3592 | likely ? "bnel" : "bne", |
3593 | "s,t,p", AT, 0); | |
670a50eb | 3594 | break; |
3d3c5039 | 3595 | |
8358c818 ILT |
3596 | case M_BGTUL: |
3597 | likely = 1; | |
3d3c5039 | 3598 | case M_BGTU: |
670a50eb ILT |
3599 | if (treg == 0) |
3600 | { | |
0dd2d296 | 3601 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3602 | likely ? "bnel" : "bne", |
3603 | "s,t,p", sreg, 0); | |
670a50eb | 3604 | return; |
3d3c5039 | 3605 | } |
9a7d824a ILT |
3606 | if (sreg == 0) |
3607 | goto do_false; | |
0dd2d296 ILT |
3608 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3609 | sreg); | |
3610 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3611 | likely ? "bnel" : "bne", |
3612 | "s,t,p", AT, 0); | |
670a50eb | 3613 | break; |
3d3c5039 | 3614 | |
8358c818 ILT |
3615 | case M_BLEL: |
3616 | likely = 1; | |
3d3c5039 | 3617 | case M_BLE: |
670a50eb ILT |
3618 | if (treg == 0) |
3619 | { | |
0dd2d296 | 3620 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3621 | likely ? "blezl" : "blez", |
3622 | "s,p", sreg); | |
670a50eb ILT |
3623 | return; |
3624 | } | |
9a7d824a ILT |
3625 | if (sreg == 0) |
3626 | { | |
0dd2d296 | 3627 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3628 | likely ? "bgezl" : "bgez", |
3629 | "s,p", treg); | |
9a7d824a ILT |
3630 | return; |
3631 | } | |
0dd2d296 ILT |
3632 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3633 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3634 | likely ? "beql" : "beq", |
3635 | "s,t,p", AT, 0); | |
670a50eb | 3636 | break; |
3d3c5039 | 3637 | |
8358c818 ILT |
3638 | case M_BLEL_I: |
3639 | likely = 1; | |
3d3c5039 | 3640 | case M_BLE_I: |
6e8dda9c | 3641 | maxnum = 0x7fffffff; |
5c6f5923 | 3642 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3643 | { |
3644 | maxnum <<= 16; | |
3645 | maxnum |= 0xffff; | |
3646 | maxnum <<= 16; | |
3647 | maxnum |= 0xffff; | |
3648 | } | |
5c6f5923 GRK |
3649 | if (imm_expr.X_op == O_constant |
3650 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3651 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3652 | goto do_true; |
5c6f5923 GRK |
3653 | if (imm_expr.X_op != O_constant) |
3654 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3655 | imm_expr.X_add_number++; |
3656 | /* FALLTHROUGH */ | |
9a7d824a | 3657 | case M_BLT_I: |
8358c818 ILT |
3658 | case M_BLTL_I: |
3659 | if (mask == M_BLTL_I) | |
3660 | likely = 1; | |
5c6f5923 | 3661 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3662 | { |
0dd2d296 | 3663 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3664 | likely ? "bltzl" : "bltz", |
3665 | "s,p", sreg); | |
670a50eb ILT |
3666 | return; |
3667 | } | |
5c6f5923 | 3668 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3669 | { |
0dd2d296 | 3670 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3671 | likely ? "blezl" : "blez", |
3672 | "s,p", sreg); | |
670a50eb ILT |
3673 | return; |
3674 | } | |
6e8dda9c | 3675 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3676 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3677 | likely ? "bnel" : "bne", |
3678 | "s,t,p", AT, 0); | |
670a50eb | 3679 | break; |
3d3c5039 | 3680 | |
8358c818 ILT |
3681 | case M_BLEUL: |
3682 | likely = 1; | |
3d3c5039 | 3683 | case M_BLEU: |
670a50eb ILT |
3684 | if (treg == 0) |
3685 | { | |
0dd2d296 | 3686 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3687 | likely ? "beql" : "beq", |
3688 | "s,t,p", sreg, 0); | |
670a50eb | 3689 | return; |
3d3c5039 | 3690 | } |
9a7d824a ILT |
3691 | if (sreg == 0) |
3692 | goto do_true; | |
0dd2d296 ILT |
3693 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3694 | sreg); | |
3695 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3696 | likely ? "beql" : "beq", |
3697 | "s,t,p", AT, 0); | |
670a50eb | 3698 | break; |
3d3c5039 | 3699 | |
8358c818 ILT |
3700 | case M_BLEUL_I: |
3701 | likely = 1; | |
3d3c5039 | 3702 | case M_BLEU_I: |
5c6f5923 GRK |
3703 | if (sreg == 0 |
3704 | || (mips_opts.isa < 3 | |
3705 | && imm_expr.X_op == O_constant | |
3706 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3707 | goto do_true; |
5c6f5923 GRK |
3708 | if (imm_expr.X_op != O_constant) |
3709 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3710 | imm_expr.X_add_number++; |
3711 | /* FALLTHROUGH */ | |
9a7d824a | 3712 | case M_BLTU_I: |
8358c818 ILT |
3713 | case M_BLTUL_I: |
3714 | if (mask == M_BLTUL_I) | |
3715 | likely = 1; | |
5c6f5923 | 3716 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3717 | goto do_false; |
5c6f5923 | 3718 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3719 | { |
0dd2d296 | 3720 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3721 | likely ? "beql" : "beq", |
3722 | "s,t,p", sreg, 0); | |
670a50eb | 3723 | return; |
3d3c5039 | 3724 | } |
6e8dda9c | 3725 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3726 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3727 | likely ? "bnel" : "bne", |
3728 | "s,t,p", AT, 0); | |
670a50eb | 3729 | break; |
3d3c5039 | 3730 | |
8358c818 ILT |
3731 | case M_BLTL: |
3732 | likely = 1; | |
3d3c5039 | 3733 | case M_BLT: |
670a50eb ILT |
3734 | if (treg == 0) |
3735 | { | |
0dd2d296 | 3736 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3737 | likely ? "bltzl" : "bltz", |
3738 | "s,p", sreg); | |
670a50eb | 3739 | return; |
3d3c5039 | 3740 | } |
9a7d824a | 3741 | if (sreg == 0) |
670a50eb | 3742 | { |
0dd2d296 | 3743 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3744 | likely ? "bgtzl" : "bgtz", |
3745 | "s,p", treg); | |
670a50eb | 3746 | return; |
3d3c5039 | 3747 | } |
0dd2d296 ILT |
3748 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3749 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3750 | likely ? "bnel" : "bne", |
3751 | "s,t,p", AT, 0); | |
670a50eb | 3752 | break; |
3d3c5039 | 3753 | |
8358c818 ILT |
3754 | case M_BLTUL: |
3755 | likely = 1; | |
3d3c5039 | 3756 | case M_BLTU: |
670a50eb | 3757 | if (treg == 0) |
9a7d824a ILT |
3758 | goto do_false; |
3759 | if (sreg == 0) | |
670a50eb | 3760 | { |
0dd2d296 | 3761 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3762 | likely ? "bnel" : "bne", |
3763 | "s,t,p", 0, treg); | |
670a50eb ILT |
3764 | return; |
3765 | } | |
0dd2d296 ILT |
3766 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3767 | treg); | |
3768 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3769 | likely ? "bnel" : "bne", |
3770 | "s,t,p", AT, 0); | |
670a50eb | 3771 | break; |
3d3c5039 | 3772 | |
8358c818 ILT |
3773 | case M_DDIV_3: |
3774 | dbl = 1; | |
3d3c5039 | 3775 | case M_DIV_3: |
8358c818 ILT |
3776 | s = "mflo"; |
3777 | goto do_div3; | |
3778 | case M_DREM_3: | |
3779 | dbl = 1; | |
3d3c5039 | 3780 | case M_REM_3: |
8358c818 ILT |
3781 | s = "mfhi"; |
3782 | do_div3: | |
670a50eb ILT |
3783 | if (treg == 0) |
3784 | { | |
3785 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3786 | if (mips_trap) |
3787 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3788 | else | |
3789 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3790 | return; |
3791 | } | |
3792 | ||
fbcfacb7 | 3793 | mips_emit_delays (true); |
3c83da8a | 3794 | ++mips_opts.noreorder; |
0dd2d296 ILT |
3795 | mips_any_noreorder = 1; |
3796 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3797 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3798 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3799 | if (mips_trap) |
3800 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3801 | else | |
3802 | { | |
3803 | expr1.X_add_number = 8; | |
3804 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3805 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3806 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3807 | } | |
670a50eb | 3808 | expr1.X_add_number = -1; |
0dd2d296 | 3809 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3810 | dbl ? "daddiu" : "addiu", |
9226253a | 3811 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3812 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3813 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3814 | if (dbl) |
3815 | { | |
3816 | expr1.X_add_number = 1; | |
0dd2d296 | 3817 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3818 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3819 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3820 | 31); | |
8358c818 ILT |
3821 | } |
3822 | else | |
3823 | { | |
3824 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3825 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3826 | (int) BFD_RELOC_HI16); | |
8358c818 | 3827 | } |
8ea7f4e8 ILT |
3828 | if (mips_trap) |
3829 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3830 | else | |
3831 | { | |
3832 | expr1.X_add_number = 8; | |
3833 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3834 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3835 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3836 | } | |
3c83da8a | 3837 | --mips_opts.noreorder; |
0dd2d296 | 3838 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3839 | break; |
3d3c5039 ILT |
3840 | |
3841 | case M_DIV_3I: | |
8358c818 ILT |
3842 | s = "div"; |
3843 | s2 = "mflo"; | |
3844 | goto do_divi; | |
3d3c5039 | 3845 | case M_DIVU_3I: |
8358c818 ILT |
3846 | s = "divu"; |
3847 | s2 = "mflo"; | |
3848 | goto do_divi; | |
3d3c5039 | 3849 | case M_REM_3I: |
8358c818 ILT |
3850 | s = "div"; |
3851 | s2 = "mfhi"; | |
3852 | goto do_divi; | |
3d3c5039 | 3853 | case M_REMU_3I: |
8358c818 ILT |
3854 | s = "divu"; |
3855 | s2 = "mfhi"; | |
3856 | goto do_divi; | |
3857 | case M_DDIV_3I: | |
3858 | dbl = 1; | |
3859 | s = "ddiv"; | |
3860 | s2 = "mflo"; | |
3861 | goto do_divi; | |
3862 | case M_DDIVU_3I: | |
3863 | dbl = 1; | |
3864 | s = "ddivu"; | |
3865 | s2 = "mflo"; | |
3866 | goto do_divi; | |
3867 | case M_DREM_3I: | |
3868 | dbl = 1; | |
3869 | s = "ddiv"; | |
3870 | s2 = "mfhi"; | |
3871 | goto do_divi; | |
3872 | case M_DREMU_3I: | |
3873 | dbl = 1; | |
3874 | s = "ddivu"; | |
3875 | s2 = "mfhi"; | |
3876 | do_divi: | |
5c6f5923 | 3877 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb ILT |
3878 | { |
3879 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3880 | if (mips_trap) |
3881 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3882 | else | |
3883 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3884 | return; |
3885 | } | |
5c6f5923 | 3886 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3887 | { |
8358c818 | 3888 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3889 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3890 | sreg); | |
3d3c5039 | 3891 | else |
0dd2d296 | 3892 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3893 | return; |
3894 | } | |
5c6f5923 GRK |
3895 | if (imm_expr.X_op == O_constant |
3896 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
3897 | && s[strlen (s) - 1] != 'u') |
3898 | { | |
3899 | if (strcmp (s2, "mflo") == 0) | |
3900 | { | |
3901 | if (dbl) | |
0dd2d296 ILT |
3902 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3903 | sreg); | |
8358c818 | 3904 | else |
0dd2d296 ILT |
3905 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3906 | sreg); | |
8358c818 ILT |
3907 | } |
3908 | else | |
0dd2d296 | 3909 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3910 | return; |
3911 | } | |
3d3c5039 | 3912 | |
d8a1c247 | 3913 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3914 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3915 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3916 | break; |
3917 | ||
3918 | case M_DIVU_3: | |
8358c818 ILT |
3919 | s = "divu"; |
3920 | s2 = "mflo"; | |
3921 | goto do_divu3; | |
670a50eb | 3922 | case M_REMU_3: |
8358c818 ILT |
3923 | s = "divu"; |
3924 | s2 = "mfhi"; | |
3925 | goto do_divu3; | |
3926 | case M_DDIVU_3: | |
3927 | s = "ddivu"; | |
3928 | s2 = "mflo"; | |
3929 | goto do_divu3; | |
3930 | case M_DREMU_3: | |
3931 | s = "ddivu"; | |
3932 | s2 = "mfhi"; | |
3933 | do_divu3: | |
fbcfacb7 | 3934 | mips_emit_delays (true); |
3c83da8a | 3935 | ++mips_opts.noreorder; |
0dd2d296 ILT |
3936 | mips_any_noreorder = 1; |
3937 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3938 | if (mips_trap) |
3939 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3940 | else | |
3941 | { | |
3942 | expr1.X_add_number = 8; | |
3943 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3944 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3945 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3946 | } | |
3c83da8a | 3947 | --mips_opts.noreorder; |
0dd2d296 | 3948 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3949 | return; |
3d3c5039 | 3950 | |
d8a1c247 KR |
3951 | case M_DLA_AB: |
3952 | dbl = 1; | |
0dd2d296 | 3953 | case M_LA_AB: |
d9aba805 ILT |
3954 | /* Load the address of a symbol into a register. If breg is not |
3955 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3956 | |
3957 | /* When generating embedded PIC code, we permit expressions of | |
3958 | the form | |
3959 | la $4,foo-bar | |
3960 | where bar is an address in the .text section. These are used | |
3961 | when getting the addresses of functions. We don't permit | |
3962 | X_add_number to be non-zero, because if the symbol is | |
3963 | external the relaxing code needs to know that any addend is | |
3964 | purely the offset to X_op_symbol. */ | |
3965 | if (mips_pic == EMBEDDED_PIC | |
3966 | && offset_expr.X_op == O_subtract | |
3967 | && now_seg == text_section | |
847a01cd ILT |
3968 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3969 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3970 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3971 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3972 | ->sy_value.X_add_symbol) | |
3973 | == text_section))) | |
ecd4ca1c ILT |
3974 | && breg == 0 |
3975 | && offset_expr.X_add_number == 0) | |
3976 | { | |
3977 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3978 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3979 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 3980 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
ecd4ca1c ILT |
3981 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
3982 | return; | |
3983 | } | |
3984 | ||
0dd2d296 ILT |
3985 | if (offset_expr.X_op != O_symbol |
3986 | && offset_expr.X_op != O_constant) | |
670a50eb | 3987 | { |
0dd2d296 ILT |
3988 | as_bad ("expression too complex"); |
3989 | offset_expr.X_op = O_constant; | |
3990 | } | |
3991 | ||
3992 | if (treg == breg) | |
3993 | { | |
3994 | tempreg = AT; | |
3995 | used_at = 1; | |
3d3c5039 | 3996 | } |
670a50eb ILT |
3997 | else |
3998 | { | |
0dd2d296 ILT |
3999 | tempreg = treg; |
4000 | used_at = 0; | |
670a50eb | 4001 | } |
3d3c5039 | 4002 | |
5ac34ac3 | 4003 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4004 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4005 | else if (mips_pic == NO_PIC) |
670a50eb | 4006 | { |
0dd2d296 ILT |
4007 | /* If this is a reference to an GP relative symbol, we want |
4008 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4009 | Otherwise we want | |
4010 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4011 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4012 | If we have a constant, we need two instructions anyhow, | |
4013 | so we may as well always use the latter form. */ | |
7a15a226 | 4014 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4015 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4016 | p = NULL; |
4017 | else | |
4018 | { | |
8ea7f4e8 | 4019 | frag_grow (20); |
0dd2d296 | 4020 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 4021 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4022 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4023 | p = frag_var (rs_machine_dependent, 8, 0, | |
4024 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4025 | mips_opts.warn_about_macros), |
f59fb6ca | 4026 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4027 | (char *) NULL); |
4028 | } | |
4029 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4030 | if (p != NULL) | |
4031 | p += 4; | |
4032 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4033 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4034 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4035 | } | |
fb251650 | 4036 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4037 | { |
4038 | /* If this is a reference to an external symbol, and there | |
4039 | is no constant, we want | |
4040 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4041 | For a local symbol, we want | |
4042 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4043 | nop | |
4044 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4045 | ||
4046 | If we have a small constant, and this is a reference to | |
4047 | an external symbol, we want | |
4048 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4049 | nop | |
4050 | addiu $tempreg,$tempreg,<constant> | |
4051 | For a local symbol, we want the same instruction | |
4052 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4053 | addiu instruction. | |
4054 | ||
4055 | If we have a large constant, and this is a reference to | |
4056 | an external symbol, we want | |
4057 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4058 | lui $at,<hiconstant> | |
4059 | addiu $at,$at,<loconstant> | |
4060 | addu $tempreg,$tempreg,$at | |
4061 | For a local symbol, we want the same instruction | |
4062 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4063 | addiu instruction. */ | |
4064 | expr1.X_add_number = offset_expr.X_add_number; | |
4065 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4066 | frag_grow (32); |
0dd2d296 | 4067 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4068 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4069 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4070 | if (expr1.X_add_number == 0) | |
4071 | { | |
4072 | int off; | |
4073 | ||
4074 | if (breg == 0) | |
4075 | off = 0; | |
4076 | else | |
4077 | { | |
4078 | /* We're going to put in an addu instruction using | |
4079 | tempreg, so we may as well insert the nop right | |
4080 | now. */ | |
4081 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4082 | "nop", ""); | |
4083 | off = 4; | |
4084 | } | |
4085 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4086 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4087 | (breg == 0 | |
3c83da8a | 4088 | ? mips_opts.warn_about_macros |
0dd2d296 | 4089 | : 0)), |
f59fb6ca | 4090 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4091 | (char *) NULL); |
4092 | if (breg == 0) | |
4093 | { | |
4094 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4095 | p += 4; | |
4096 | } | |
4097 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4098 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4099 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4100 | /* FIXME: If breg == 0, and the next instruction uses | |
4101 | $tempreg, then if this variant case is used an extra | |
4102 | nop will be generated. */ | |
4103 | } | |
4104 | else if (expr1.X_add_number >= -0x8000 | |
4105 | && expr1.X_add_number < 0x8000) | |
4106 | { | |
4107 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4108 | "nop", ""); | |
4109 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4110 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4111 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4112 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4113 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4114 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4115 | (char *) NULL); |
4116 | } | |
4117 | else | |
4118 | { | |
4119 | int off1; | |
4120 | ||
4121 | /* If we are going to add in a base register, and the | |
4122 | target register and the base register are the same, | |
4123 | then we are using AT as a temporary register. Since | |
4124 | we want to load the constant into AT, we add our | |
4125 | current AT (from the global offset table) and the | |
4126 | register into the register now, and pretend we were | |
4127 | not using a base register. */ | |
4128 | if (breg != treg) | |
4129 | off1 = 0; | |
4130 | else | |
4131 | { | |
4132 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4133 | "nop", ""); | |
4134 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4135 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4136 | "d,v,t", treg, AT, breg); |
4137 | breg = 0; | |
4138 | tempreg = treg; | |
4139 | off1 = -8; | |
4140 | } | |
4141 | ||
55933a58 ILT |
4142 | /* Set mips_optimize around the lui instruction to avoid |
4143 | inserting an unnecessary nop after the lw. */ | |
4144 | hold_mips_optimize = mips_optimize; | |
4145 | mips_optimize = 2; | |
0dd2d296 | 4146 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4147 | mips_optimize = hold_mips_optimize; |
4148 | ||
0dd2d296 | 4149 | macro_build ((char *) NULL, &icnt, &expr1, |
3c83da8a | 4150 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4151 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4152 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4153 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4154 | "d,v,t", tempreg, tempreg, AT); |
4155 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4156 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4157 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4158 | (char *) NULL); |
4159 | used_at = 1; | |
4160 | } | |
670a50eb | 4161 | } |
fb251650 ILT |
4162 | else if (mips_pic == SVR4_PIC) |
4163 | { | |
4164 | int gpdel; | |
4165 | ||
4166 | /* This is the large GOT case. If this is a reference to an | |
4167 | external symbol, and there is no constant, we want | |
4168 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4169 | addu $tempreg,$tempreg,$gp | |
4170 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4171 | For a local symbol, we want | |
4172 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4173 | nop | |
4174 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4175 | ||
4176 | If we have a small constant, and this is a reference to | |
4177 | an external symbol, we want | |
4178 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4179 | addu $tempreg,$tempreg,$gp | |
4180 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4181 | nop | |
4182 | addiu $tempreg,$tempreg,<constant> | |
4183 | For a local symbol, we want | |
4184 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4185 | nop | |
4186 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4187 | ||
4188 | If we have a large constant, and this is a reference to | |
4189 | an external symbol, we want | |
4190 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4191 | addu $tempreg,$tempreg,$gp | |
4192 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4193 | lui $at,<hiconstant> | |
4194 | addiu $at,$at,<loconstant> | |
4195 | addu $tempreg,$tempreg,$at | |
4196 | For a local symbol, we want | |
4197 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4198 | lui $at,<hiconstant> | |
4199 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4200 | addu $tempreg,$tempreg,$at | |
4201 | */ | |
4202 | expr1.X_add_number = offset_expr.X_add_number; | |
4203 | offset_expr.X_add_number = 0; | |
4204 | frag_grow (52); | |
4205 | if (reg_needs_delay (GP)) | |
4206 | gpdel = 4; | |
4207 | else | |
4208 | gpdel = 0; | |
4209 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4210 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4211 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4212 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4213 | "d,v,t", tempreg, tempreg, GP); |
4214 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4215 | dbl ? "ld" : "lw", | |
4216 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4217 | tempreg); | |
4218 | if (expr1.X_add_number == 0) | |
4219 | { | |
4220 | int off; | |
4221 | ||
4222 | if (breg == 0) | |
4223 | off = 0; | |
4224 | else | |
4225 | { | |
4226 | /* We're going to put in an addu instruction using | |
4227 | tempreg, so we may as well insert the nop right | |
4228 | now. */ | |
4229 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4230 | "nop", ""); | |
4231 | off = 4; | |
4232 | } | |
4233 | ||
4234 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4235 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4236 | 8 + gpdel, 0, | |
4237 | (breg == 0 | |
3c83da8a | 4238 | ? mips_opts.warn_about_macros |
fb251650 | 4239 | : 0)), |
f59fb6ca | 4240 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4241 | (char *) NULL); |
4242 | } | |
4243 | else if (expr1.X_add_number >= -0x8000 | |
4244 | && expr1.X_add_number < 0x8000) | |
4245 | { | |
4246 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4247 | "nop", ""); | |
4248 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4249 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4250 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4251 | ||
4252 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4253 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4254 | (breg == 0 | |
3c83da8a | 4255 | ? mips_opts.warn_about_macros |
fb251650 | 4256 | : 0)), |
f59fb6ca | 4257 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4258 | (char *) NULL); |
4259 | } | |
4260 | else | |
4261 | { | |
4262 | int adj, dreg; | |
4263 | ||
4264 | /* If we are going to add in a base register, and the | |
4265 | target register and the base register are the same, | |
4266 | then we are using AT as a temporary register. Since | |
4267 | we want to load the constant into AT, we add our | |
4268 | current AT (from the global offset table) and the | |
4269 | register into the register now, and pretend we were | |
4270 | not using a base register. */ | |
4271 | if (breg != treg) | |
4272 | { | |
4273 | adj = 0; | |
4274 | dreg = tempreg; | |
4275 | } | |
4276 | else | |
4277 | { | |
4278 | assert (tempreg == AT); | |
4279 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4280 | "nop", ""); | |
4281 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4282 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4283 | "d,v,t", treg, AT, breg); |
4284 | dreg = treg; | |
4285 | adj = 8; | |
4286 | } | |
4287 | ||
4288 | /* Set mips_optimize around the lui instruction to avoid | |
4289 | inserting an unnecessary nop after the lw. */ | |
4290 | hold_mips_optimize = mips_optimize; | |
4291 | mips_optimize = 2; | |
4292 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4293 | mips_optimize = hold_mips_optimize; | |
4294 | ||
4295 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4296 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4297 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4298 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4299 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4300 | "d,v,t", dreg, dreg, AT); |
4301 | ||
4302 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4303 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4304 | 8 + gpdel, 0, | |
4305 | (breg == 0 | |
3c83da8a | 4306 | ? mips_opts.warn_about_macros |
fb251650 | 4307 | : 0)), |
f59fb6ca | 4308 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4309 | (char *) NULL); |
4310 | ||
4311 | used_at = 1; | |
4312 | } | |
4313 | ||
4314 | if (gpdel > 0) | |
4315 | { | |
4316 | /* This is needed because this instruction uses $gp, but | |
4317 | the first instruction on the main stream does not. */ | |
4318 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4319 | p += 4; | |
4320 | } | |
4321 | macro_build (p, &icnt, &offset_expr, | |
4322 | dbl ? "ld" : "lw", | |
4323 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4324 | p += 4; | |
4325 | if (expr1.X_add_number >= -0x8000 | |
4326 | && expr1.X_add_number < 0x8000) | |
4327 | { | |
4328 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4329 | p += 4; | |
4330 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4331 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4332 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4333 | /* FIXME: If add_number is 0, and there was no base | |
4334 | register, the external symbol case ended with a load, | |
4335 | so if the symbol turns out to not be external, and | |
4336 | the next instruction uses tempreg, an unnecessary nop | |
4337 | will be inserted. */ | |
4338 | } | |
4339 | else | |
4340 | { | |
4341 | if (breg == treg) | |
4342 | { | |
4343 | /* We must add in the base register now, as in the | |
4344 | external symbol case. */ | |
4345 | assert (tempreg == AT); | |
4346 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4347 | p += 4; | |
4348 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4349 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4350 | "d,v,t", treg, AT, breg); |
4351 | p += 4; | |
4352 | tempreg = treg; | |
4353 | /* We set breg to 0 because we have arranged to add | |
4354 | it in in both cases. */ | |
4355 | breg = 0; | |
4356 | } | |
4357 | ||
4358 | macro_build_lui (p, &icnt, &expr1, AT); | |
4359 | p += 4; | |
4360 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4361 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4362 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4363 | p += 4; | |
4364 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4365 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4366 | "d,v,t", tempreg, tempreg, AT); |
4367 | p += 4; | |
4368 | } | |
4369 | } | |
d9aba805 ILT |
4370 | else if (mips_pic == EMBEDDED_PIC) |
4371 | { | |
4372 | /* We use | |
4373 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4374 | */ | |
4375 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4376 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
4377 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4378 | } | |
4379 | else | |
4380 | abort (); | |
0dd2d296 | 4381 | |
670a50eb | 4382 | if (breg != 0) |
0dd2d296 | 4383 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4384 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4385 | "d,v,t", treg, tempreg, breg); |
4386 | ||
4387 | if (! used_at) | |
4388 | return; | |
4389 | ||
4390 | break; | |
4391 | ||
4392 | case M_J_A: | |
4393 | /* The j instruction may not be used in PIC code, since it | |
4394 | requires an absolute address. We convert it to a b | |
4395 | instruction. */ | |
d9aba805 | 4396 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4397 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4398 | else | |
4399 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4400 | return; |
3d3c5039 | 4401 | |
9226253a ILT |
4402 | /* The jal instructions must be handled as macros because when |
4403 | generating PIC code they expand to multi-instruction | |
4404 | sequences. Normally they are simple instructions. */ | |
4405 | case M_JAL_1: | |
4406 | dreg = RA; | |
4407 | /* Fall through. */ | |
4408 | case M_JAL_2: | |
d9aba805 ILT |
4409 | if (mips_pic == NO_PIC |
4410 | || mips_pic == EMBEDDED_PIC) | |
4411 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4412 | "d,s", dreg, sreg); | |
4413 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4414 | { |
d9aba805 ILT |
4415 | if (sreg != PIC_CALL_REG) |
4416 | as_warn ("MIPS PIC call to register other than $25"); | |
4417 | ||
0dd2d296 ILT |
4418 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4419 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4420 | if (mips_cprestore_offset < 0) |
4421 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4422 | else | |
4423 | { | |
4424 | expr1.X_add_number = mips_cprestore_offset; | |
4425 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4426 | mips_opts.isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
4427 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4428 | } | |
9226253a | 4429 | } |
0dd2d296 | 4430 | else |
d9aba805 ILT |
4431 | abort (); |
4432 | ||
9226253a ILT |
4433 | return; |
4434 | ||
4435 | case M_JAL_A: | |
d9aba805 ILT |
4436 | if (mips_pic == NO_PIC) |
4437 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4438 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4439 | { |
fb251650 ILT |
4440 | /* If this is a reference to an external symbol, and we are |
4441 | using a small GOT, we want | |
d9aba805 ILT |
4442 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4443 | nop | |
4444 | jalr $25 | |
4445 | nop | |
4446 | lw $gp,cprestore($sp) | |
4447 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4448 | pseudo-op. If we are using a big GOT, we want |
4449 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4450 | addu $25,$25,$gp | |
4451 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4452 | nop | |
4453 | jalr $25 | |
4454 | nop | |
4455 | lw $gp,cprestore($sp) | |
4456 | If the symbol is not external, we want | |
d9aba805 ILT |
4457 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4458 | nop | |
4459 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4460 | jalr $25 | |
4461 | nop | |
fb251650 ILT |
4462 | lw $gp,cprestore($sp) */ |
4463 | frag_grow (40); | |
4464 | if (! mips_big_got) | |
4465 | { | |
4466 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4467 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4468 | "t,o(b)", PIC_CALL_REG, |
4469 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4470 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4471 | "nop", ""); | |
4472 | p = frag_var (rs_machine_dependent, 4, 0, | |
4473 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4474 | offset_expr.X_add_symbol, (offsetT) 0, |
4475 | (char *) NULL); | |
fb251650 ILT |
4476 | } |
4477 | else | |
4478 | { | |
4479 | int gpdel; | |
4480 | ||
4481 | if (reg_needs_delay (GP)) | |
4482 | gpdel = 4; | |
4483 | else | |
4484 | gpdel = 0; | |
4485 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4486 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4487 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4488 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4489 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4490 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4491 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4492 | "t,o(b)", PIC_CALL_REG, |
4493 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4494 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4495 | "nop", ""); | |
4496 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4497 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4498 | 0, 0), | |
f59fb6ca ILT |
4499 | offset_expr.X_add_symbol, (offsetT) 0, |
4500 | (char *) NULL); | |
fb251650 ILT |
4501 | if (gpdel > 0) |
4502 | { | |
4503 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4504 | p += 4; | |
4505 | } | |
4506 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4507 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4508 | "t,o(b)", PIC_CALL_REG, |
4509 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4510 | p += 4; | |
4511 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4512 | p += 4; | |
4513 | } | |
d9aba805 | 4514 | macro_build (p, &icnt, &offset_expr, |
3c83da8a | 4515 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
4516 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4517 | (int) BFD_RELOC_LO16); | |
4518 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4519 | "jalr", "s", PIC_CALL_REG); | |
4520 | if (mips_cprestore_offset < 0) | |
4521 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4522 | else | |
4523 | { | |
3c83da8a | 4524 | if (mips_opts.noreorder) |
d9aba805 ILT |
4525 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4526 | "nop", ""); | |
4527 | expr1.X_add_number = mips_cprestore_offset; | |
4528 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4529 | mips_opts.isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
4530 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4531 | mips_frame_reg); | |
4532 | } | |
0dd2d296 | 4533 | } |
d9aba805 | 4534 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4535 | { |
4536 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4537 | /* The linker may expand the call to a longer sequence which | |
4538 | uses $at, so we must break rather than return. */ | |
4539 | break; | |
4540 | } | |
d9aba805 ILT |
4541 | else |
4542 | abort (); | |
4543 | ||
9226253a ILT |
4544 | return; |
4545 | ||
3d3c5039 | 4546 | case M_LB_AB: |
670a50eb ILT |
4547 | s = "lb"; |
4548 | goto ld; | |
3d3c5039 | 4549 | case M_LBU_AB: |
670a50eb ILT |
4550 | s = "lbu"; |
4551 | goto ld; | |
3d3c5039 | 4552 | case M_LH_AB: |
670a50eb ILT |
4553 | s = "lh"; |
4554 | goto ld; | |
3d3c5039 | 4555 | case M_LHU_AB: |
670a50eb ILT |
4556 | s = "lhu"; |
4557 | goto ld; | |
3d3c5039 | 4558 | case M_LW_AB: |
670a50eb ILT |
4559 | s = "lw"; |
4560 | goto ld; | |
3d3c5039 | 4561 | case M_LWC0_AB: |
670a50eb | 4562 | s = "lwc0"; |
efec4a28 | 4563 | /* Itbl support may require additional care here. */ |
8358c818 | 4564 | coproc = 1; |
670a50eb | 4565 | goto ld; |
3d3c5039 | 4566 | case M_LWC1_AB: |
670a50eb | 4567 | s = "lwc1"; |
efec4a28 | 4568 | /* Itbl support may require additional care here. */ |
8358c818 | 4569 | coproc = 1; |
670a50eb | 4570 | goto ld; |
3d3c5039 | 4571 | case M_LWC2_AB: |
670a50eb | 4572 | s = "lwc2"; |
efec4a28 | 4573 | /* Itbl support may require additional care here. */ |
8358c818 | 4574 | coproc = 1; |
670a50eb | 4575 | goto ld; |
3d3c5039 | 4576 | case M_LWC3_AB: |
670a50eb | 4577 | s = "lwc3"; |
efec4a28 | 4578 | /* Itbl support may require additional care here. */ |
8358c818 | 4579 | coproc = 1; |
670a50eb | 4580 | goto ld; |
3d3c5039 | 4581 | case M_LWL_AB: |
670a50eb | 4582 | s = "lwl"; |
b2b8c24e | 4583 | lr = 1; |
670a50eb | 4584 | goto ld; |
3d3c5039 | 4585 | case M_LWR_AB: |
670a50eb | 4586 | s = "lwr"; |
b2b8c24e | 4587 | lr = 1; |
8358c818 ILT |
4588 | goto ld; |
4589 | case M_LDC1_AB: | |
4590 | s = "ldc1"; | |
efec4a28 | 4591 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4592 | coproc = 1; |
4593 | goto ld; | |
4594 | case M_LDC2_AB: | |
4595 | s = "ldc2"; | |
efec4a28 | 4596 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4597 | coproc = 1; |
4598 | goto ld; | |
4599 | case M_LDC3_AB: | |
4600 | s = "ldc3"; | |
efec4a28 | 4601 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4602 | coproc = 1; |
4603 | goto ld; | |
4604 | case M_LDL_AB: | |
4605 | s = "ldl"; | |
b2b8c24e | 4606 | lr = 1; |
8358c818 ILT |
4607 | goto ld; |
4608 | case M_LDR_AB: | |
4609 | s = "ldr"; | |
b2b8c24e | 4610 | lr = 1; |
8358c818 ILT |
4611 | goto ld; |
4612 | case M_LL_AB: | |
4613 | s = "ll"; | |
4614 | goto ld; | |
4615 | case M_LLD_AB: | |
4616 | s = "lld"; | |
4617 | goto ld; | |
4618 | case M_LWU_AB: | |
4619 | s = "lwu"; | |
3d3c5039 | 4620 | ld: |
b2b8c24e | 4621 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4622 | { |
4623 | tempreg = AT; | |
4624 | used_at = 1; | |
4625 | } | |
4626 | else | |
4627 | { | |
4628 | tempreg = treg; | |
4629 | used_at = 0; | |
4630 | } | |
4631 | goto ld_st; | |
3d3c5039 | 4632 | case M_SB_AB: |
670a50eb ILT |
4633 | s = "sb"; |
4634 | goto st; | |
3d3c5039 | 4635 | case M_SH_AB: |
670a50eb ILT |
4636 | s = "sh"; |
4637 | goto st; | |
3d3c5039 | 4638 | case M_SW_AB: |
670a50eb ILT |
4639 | s = "sw"; |
4640 | goto st; | |
3d3c5039 | 4641 | case M_SWC0_AB: |
670a50eb | 4642 | s = "swc0"; |
efec4a28 | 4643 | /* Itbl support may require additional care here. */ |
8358c818 | 4644 | coproc = 1; |
670a50eb | 4645 | goto st; |
3d3c5039 | 4646 | case M_SWC1_AB: |
670a50eb | 4647 | s = "swc1"; |
efec4a28 | 4648 | /* Itbl support may require additional care here. */ |
8358c818 | 4649 | coproc = 1; |
670a50eb | 4650 | goto st; |
3d3c5039 | 4651 | case M_SWC2_AB: |
670a50eb | 4652 | s = "swc2"; |
efec4a28 | 4653 | /* Itbl support may require additional care here. */ |
8358c818 | 4654 | coproc = 1; |
670a50eb | 4655 | goto st; |
3d3c5039 | 4656 | case M_SWC3_AB: |
670a50eb | 4657 | s = "swc3"; |
efec4a28 | 4658 | /* Itbl support may require additional care here. */ |
8358c818 | 4659 | coproc = 1; |
670a50eb | 4660 | goto st; |
3d3c5039 | 4661 | case M_SWL_AB: |
670a50eb ILT |
4662 | s = "swl"; |
4663 | goto st; | |
3d3c5039 | 4664 | case M_SWR_AB: |
670a50eb | 4665 | s = "swr"; |
8358c818 ILT |
4666 | goto st; |
4667 | case M_SC_AB: | |
4668 | s = "sc"; | |
4669 | goto st; | |
4670 | case M_SCD_AB: | |
4671 | s = "scd"; | |
4672 | goto st; | |
4673 | case M_SDC1_AB: | |
4674 | s = "sdc1"; | |
4675 | coproc = 1; | |
efec4a28 | 4676 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4677 | goto st; |
4678 | case M_SDC2_AB: | |
4679 | s = "sdc2"; | |
efec4a28 | 4680 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4681 | coproc = 1; |
4682 | goto st; | |
4683 | case M_SDC3_AB: | |
4684 | s = "sdc3"; | |
efec4a28 | 4685 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4686 | coproc = 1; |
4687 | goto st; | |
4688 | case M_SDL_AB: | |
4689 | s = "sdl"; | |
4690 | goto st; | |
4691 | case M_SDR_AB: | |
4692 | s = "sdr"; | |
3d3c5039 | 4693 | st: |
670a50eb ILT |
4694 | tempreg = AT; |
4695 | used_at = 1; | |
3d3c5039 | 4696 | ld_st: |
efec4a28 | 4697 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4698 | if (mask == M_LWC1_AB |
4699 | || mask == M_SWC1_AB | |
8358c818 | 4700 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4701 | || mask == M_SDC1_AB |
4702 | || mask == M_L_DAB | |
4703 | || mask == M_S_DAB) | |
670a50eb | 4704 | fmt = "T,o(b)"; |
8358c818 | 4705 | else if (coproc) |
19ed8960 | 4706 | fmt = "E,o(b)"; |
670a50eb ILT |
4707 | else |
4708 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4709 | |
4710 | if (offset_expr.X_op != O_constant | |
4711 | && offset_expr.X_op != O_symbol) | |
4712 | { | |
4713 | as_bad ("expression too complex"); | |
4714 | offset_expr.X_op = O_constant; | |
4715 | } | |
4716 | ||
4717 | /* A constant expression in PIC code can be handled just as it | |
4718 | is in non PIC code. */ | |
d9aba805 | 4719 | if (mips_pic == NO_PIC |
0dd2d296 | 4720 | || offset_expr.X_op == O_constant) |
670a50eb | 4721 | { |
0dd2d296 ILT |
4722 | /* If this is a reference to a GP relative symbol, and there |
4723 | is no base register, we want | |
4724 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4725 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4726 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4727 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4728 | If we have a constant, we need two instructions anyhow, | |
4729 | so we always use the latter form. | |
4730 | ||
4731 | If we have a base register, and this is a reference to a | |
4732 | GP relative symbol, we want | |
4733 | addu $tempreg,$breg,$gp | |
4734 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4735 | Otherwise we want | |
4736 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4737 | addu $tempreg,$tempreg,$breg | |
4738 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4739 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4740 | if (breg == 0) |
4741 | { | |
7a15a226 | 4742 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4743 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4744 | p = NULL; |
4745 | else | |
4746 | { | |
8ea7f4e8 | 4747 | frag_grow (20); |
0dd2d296 ILT |
4748 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4749 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4750 | p = frag_var (rs_machine_dependent, 8, 0, | |
4751 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
4752 | (mips_opts.warn_about_macros |
4753 | || (used_at | |
4754 | && mips_opts.noat))), | |
f59fb6ca | 4755 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 4756 | (char *) NULL); |
8197b589 | 4757 | used_at = 0; |
0dd2d296 ILT |
4758 | } |
4759 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4760 | if (p != NULL) | |
4761 | p += 4; | |
4762 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4763 | (int) BFD_RELOC_LO16, tempreg); | |
4764 | } | |
4765 | else | |
4766 | { | |
7a15a226 | 4767 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4768 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4769 | p = NULL; |
4770 | else | |
4771 | { | |
8ea7f4e8 | 4772 | frag_grow (28); |
0dd2d296 | 4773 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4774 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4775 | "d,v,t", tempreg, breg, GP); |
4776 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4777 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4778 | p = frag_var (rs_machine_dependent, 12, 0, | |
4779 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 4780 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4781 | (char *) NULL); |
4782 | } | |
4783 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4784 | if (p != NULL) | |
4785 | p += 4; | |
4786 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4787 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4788 | "d,v,t", tempreg, tempreg, breg); |
4789 | if (p != NULL) | |
4790 | p += 4; | |
4791 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4792 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4793 | } |
670a50eb | 4794 | } |
fb251650 | 4795 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4796 | { |
0dd2d296 ILT |
4797 | /* If this is a reference to an external symbol, we want |
4798 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4799 | nop | |
4800 | <op> $treg,0($tempreg) | |
4801 | Otherwise we want | |
4802 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4803 | nop | |
4804 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4805 | <op> $treg,0($tempreg) | |
4806 | If there is a base register, we add it to $tempreg before | |
4807 | the <op>. If there is a constant, we stick it in the | |
4808 | <op> instruction. We don't handle constants larger than | |
4809 | 16 bits, because we have no way to load the upper 16 bits | |
4810 | (actually, we could handle them for the subset of cases | |
4811 | in which we are not using $at). */ | |
4812 | assert (offset_expr.X_op == O_symbol); | |
4813 | expr1.X_add_number = offset_expr.X_add_number; | |
4814 | offset_expr.X_add_number = 0; | |
4815 | if (expr1.X_add_number < -0x8000 | |
4816 | || expr1.X_add_number >= 0x8000) | |
4817 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4818 | frag_grow (20); |
0dd2d296 | 4819 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 4820 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
4821 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4822 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4823 | p = frag_var (rs_machine_dependent, 4, 0, | |
4824 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 4825 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4826 | (char *) NULL); |
4827 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4828 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 | 4829 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 4830 | if (breg != 0) |
0dd2d296 | 4831 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4832 | mips_opts.isa < 3 ? "addu" : "daddu", |
6e8dda9c | 4833 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
4834 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4835 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4836 | } |
fb251650 ILT |
4837 | else if (mips_pic == SVR4_PIC) |
4838 | { | |
4839 | int gpdel; | |
4840 | ||
4841 | /* If this is a reference to an external symbol, we want | |
4842 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4843 | addu $tempreg,$tempreg,$gp | |
4844 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4845 | <op> $treg,0($tempreg) | |
4846 | Otherwise we want | |
4847 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4848 | nop | |
4849 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4850 | <op> $treg,0($tempreg) | |
4851 | If there is a base register, we add it to $tempreg before | |
4852 | the <op>. If there is a constant, we stick it in the | |
4853 | <op> instruction. We don't handle constants larger than | |
4854 | 16 bits, because we have no way to load the upper 16 bits | |
4855 | (actually, we could handle them for the subset of cases | |
4856 | in which we are not using $at). */ | |
4857 | assert (offset_expr.X_op == O_symbol); | |
4858 | expr1.X_add_number = offset_expr.X_add_number; | |
4859 | offset_expr.X_add_number = 0; | |
4860 | if (expr1.X_add_number < -0x8000 | |
4861 | || expr1.X_add_number >= 0x8000) | |
4862 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4863 | if (reg_needs_delay (GP)) | |
4864 | gpdel = 4; | |
4865 | else | |
4866 | gpdel = 0; | |
4867 | frag_grow (36); | |
4868 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4869 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4870 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4871 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4872 | "d,v,t", tempreg, tempreg, GP); |
4873 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4874 | mips_opts.isa < 3 ? "lw" : "ld", |
867a58b3 ILT |
4875 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4876 | tempreg); | |
fb251650 ILT |
4877 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4878 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 4879 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
4880 | if (gpdel > 0) |
4881 | { | |
4882 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4883 | p += 4; | |
4884 | } | |
4885 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4886 | mips_opts.isa < 3 ? "lw" : "ld", |
867a58b3 | 4887 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4888 | p += 4; |
4889 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4890 | p += 4; | |
4891 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4892 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4893 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4894 | if (breg != 0) | |
4895 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4896 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4897 | "d,v,t", tempreg, tempreg, breg); |
4898 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4899 | (int) BFD_RELOC_LO16, tempreg); | |
4900 | } | |
d9aba805 ILT |
4901 | else if (mips_pic == EMBEDDED_PIC) |
4902 | { | |
4903 | /* If there is no base register, we want | |
4904 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4905 | If there is a base register, we want | |
4906 | addu $tempreg,$breg,$gp | |
4907 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4908 | */ | |
4909 | assert (offset_expr.X_op == O_symbol); | |
4910 | if (breg == 0) | |
4911 | { | |
4912 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4913 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4914 | used_at = 0; | |
4915 | } | |
4916 | else | |
4917 | { | |
4918 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4919 | mips_opts.isa < 3 ? "addu" : "daddu", |
d9aba805 ILT |
4920 | "d,v,t", tempreg, breg, GP); |
4921 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4922 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4923 | } | |
4924 | } | |
4925 | else | |
4926 | abort (); | |
0dd2d296 ILT |
4927 | |
4928 | if (! used_at) | |
4929 | return; | |
4930 | ||
4931 | break; | |
3d3c5039 ILT |
4932 | |
4933 | case M_LI: | |
19ed8960 | 4934 | case M_LI_S: |
d8a1c247 KR |
4935 | load_register (&icnt, treg, &imm_expr, 0); |
4936 | return; | |
4937 | ||
4938 | case M_DLI: | |
4939 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4940 | return; |
3d3c5039 | 4941 | |
0dd2d296 | 4942 | case M_LI_SS: |
55933a58 | 4943 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4944 | { |
d8a1c247 | 4945 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4946 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4947 | "mtc1", "t,G", AT, treg); | |
4948 | break; | |
0dd2d296 | 4949 | } |
d9aba805 | 4950 | else |
d2c71068 | 4951 | { |
55933a58 ILT |
4952 | assert (offset_expr.X_op == O_symbol |
4953 | && strcmp (segment_name (S_GET_SEGMENT | |
4954 | (offset_expr.X_add_symbol)), | |
4955 | ".lit4") == 0 | |
4956 | && offset_expr.X_add_number == 0); | |
4957 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4958 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4959 | return; |
4960 | } | |
0dd2d296 | 4961 | |
3d3c5039 | 4962 | case M_LI_D: |
a5586bdc ILT |
4963 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
4964 | the entire value, and in mips1 mode it is the high order 32 | |
4965 | bits of the value and the low order 32 bits are either zero | |
4966 | or in offset_expr. */ | |
4967 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
4968 | { | |
4969 | load_register (&icnt, treg, &imm_expr, mips_opts.isa >= 3); | |
4970 | if (mips_opts.isa < 3 && treg != 31) | |
4971 | { | |
4972 | if (offset_expr.X_op == O_absent) | |
4973 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
4974 | treg + 1, 0); | |
4975 | else | |
4976 | { | |
4977 | assert (offset_expr.X_op == O_constant); | |
4978 | load_register (&icnt, treg + 1, &offset_expr, 0); | |
4979 | } | |
4980 | } | |
4981 | return; | |
4982 | } | |
4983 | ||
d9aba805 ILT |
4984 | /* We know that sym is in the .rdata section. First we get the |
4985 | upper 16 bits of the address. */ | |
4986 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4987 | { |
4988 | /* FIXME: This won't work for a 64 bit address. */ | |
4989 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4990 | } | |
d9aba805 | 4991 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4992 | { |
4993 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4994 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
4995 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
4996 | } | |
d9aba805 ILT |
4997 | else if (mips_pic == EMBEDDED_PIC) |
4998 | { | |
4999 | /* For embedded PIC we pick up the entire address off $gp in | |
5000 | a single instruction. */ | |
5001 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5002 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
5003 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5004 | offset_expr.X_op = O_constant; | |
5005 | offset_expr.X_add_number = 0; | |
5006 | } | |
5007 | else | |
5008 | abort (); | |
5009 | ||
0dd2d296 | 5010 | /* Now we load the register(s). */ |
3c83da8a | 5011 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5012 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5013 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5014 | else |
5015 | { | |
0dd2d296 ILT |
5016 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5017 | treg, (int) BFD_RELOC_LO16, AT); | |
5018 | if (treg != 31) | |
5019 | { | |
5020 | /* FIXME: How in the world do we deal with the possible | |
5021 | overflow here? */ | |
5022 | offset_expr.X_add_number += 4; | |
5023 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5024 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5025 | } | |
8358c818 | 5026 | } |
d2c71068 ILT |
5027 | |
5028 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5029 | does not become a variant frag. */ | |
5030 | frag_wane (frag_now); | |
5031 | frag_new (0); | |
5032 | ||
670a50eb | 5033 | break; |
3d3c5039 ILT |
5034 | |
5035 | case M_LI_DD: | |
a5586bdc ILT |
5036 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5037 | the entire value, and in mips1 mode it is the high order 32 | |
5038 | bits of the value and the low order 32 bits are either zero | |
5039 | or in offset_expr. */ | |
5040 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5041 | { | |
5042 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5043 | if (mips_opts.isa >= 3) | |
5044 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5045 | "dmtc1", "t,S", AT, treg); | |
5046 | else | |
5047 | { | |
5048 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5049 | "mtc1", "t,G", AT, treg + 1); | |
5050 | if (offset_expr.X_op == O_absent) | |
5051 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5052 | "mtc1", "t,G", 0, treg); | |
5053 | else | |
5054 | { | |
5055 | assert (offset_expr.X_op == O_constant); | |
5056 | load_register (&icnt, AT, &offset_expr, 0); | |
5057 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5058 | "mtc1", "t,G", AT, treg); | |
5059 | } | |
5060 | } | |
5061 | break; | |
5062 | } | |
5063 | ||
55933a58 ILT |
5064 | assert (offset_expr.X_op == O_symbol |
5065 | && offset_expr.X_add_number == 0); | |
5066 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5067 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5068 | { |
3c83da8a | 5069 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5070 | { |
5071 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5072 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5073 | return; | |
5074 | } | |
5075 | breg = GP; | |
5076 | r = BFD_RELOC_MIPS_LITERAL; | |
5077 | goto dob; | |
5078 | } | |
55933a58 | 5079 | else |
0dd2d296 | 5080 | { |
55933a58 ILT |
5081 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5082 | if (mips_pic == SVR4_PIC) | |
5083 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5084 | mips_opts.isa < 3 ? "lw" : "ld", |
55933a58 ILT |
5085 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5086 | else | |
5087 | { | |
5088 | /* FIXME: This won't work for a 64 bit address. */ | |
5089 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5090 | } | |
5091 | ||
3c83da8a | 5092 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5093 | { |
5094 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5095 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5096 | |
5097 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5098 | that this does not become a variant frag. */ | |
5099 | frag_wane (frag_now); | |
5100 | frag_new (0); | |
5101 | ||
0dd2d296 ILT |
5102 | break; |
5103 | } | |
5104 | breg = AT; | |
5105 | r = BFD_RELOC_LO16; | |
5106 | goto dob; | |
8358c818 | 5107 | } |
9226253a | 5108 | |
3d3c5039 | 5109 | case M_L_DOB: |
9a7d824a ILT |
5110 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5111 | to adjust when loading from memory. */ | |
9226253a ILT |
5112 | r = BFD_RELOC_LO16; |
5113 | dob: | |
3c83da8a | 5114 | assert (mips_opts.isa < 2); |
0dd2d296 | 5115 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5116 | target_big_endian ? treg + 1 : treg, |
9226253a | 5117 | (int) r, breg); |
0dd2d296 ILT |
5118 | /* FIXME: A possible overflow which I don't know how to deal |
5119 | with. */ | |
670a50eb | 5120 | offset_expr.X_add_number += 4; |
0dd2d296 | 5121 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5122 | target_big_endian ? treg : treg + 1, |
9226253a | 5123 | (int) r, breg); |
d2c71068 ILT |
5124 | |
5125 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5126 | does not become a variant frag. */ | |
5127 | frag_wane (frag_now); | |
5128 | frag_new (0); | |
5129 | ||
0dd2d296 ILT |
5130 | if (breg != AT) |
5131 | return; | |
5132 | break; | |
3d3c5039 ILT |
5133 | |
5134 | case M_L_DAB: | |
670a50eb ILT |
5135 | /* |
5136 | * The MIPS assembler seems to check for X_add_number not | |
5137 | * being double aligned and generating: | |
5138 | * lui at,%hi(foo+1) | |
5139 | * addu at,at,v1 | |
5140 | * addiu at,at,%lo(foo+1) | |
5141 | * lwc1 f2,0(at) | |
5142 | * lwc1 f3,4(at) | |
5143 | * But, the resulting address is the same after relocation so why | |
5144 | * generate the extra instruction? | |
5145 | */ | |
efec4a28 | 5146 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5147 | coproc = 1; |
3c83da8a | 5148 | if (mips_opts.isa >= 2) |
670a50eb | 5149 | { |
0dd2d296 ILT |
5150 | s = "ldc1"; |
5151 | goto ld; | |
670a50eb | 5152 | } |
0dd2d296 ILT |
5153 | |
5154 | s = "lwc1"; | |
5155 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5156 | goto ldd_std; |
5157 | ||
5158 | case M_S_DAB: | |
3c83da8a | 5159 | if (mips_opts.isa >= 2) |
8358c818 | 5160 | { |
0dd2d296 ILT |
5161 | s = "sdc1"; |
5162 | goto st; | |
8358c818 | 5163 | } |
3d3c5039 | 5164 | |
0dd2d296 ILT |
5165 | s = "swc1"; |
5166 | fmt = "T,o(b)"; | |
efec4a28 | 5167 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5168 | coproc = 1; |
5169 | goto ldd_std; | |
3d3c5039 ILT |
5170 | |
5171 | case M_LD_AB: | |
3c83da8a | 5172 | if (mips_opts.isa >= 3) |
670a50eb | 5173 | { |
0dd2d296 ILT |
5174 | s = "ld"; |
5175 | goto ld; | |
670a50eb | 5176 | } |
0dd2d296 ILT |
5177 | |
5178 | s = "lw"; | |
5179 | fmt = "t,o(b)"; | |
5180 | goto ldd_std; | |
5181 | ||
5182 | case M_SD_AB: | |
3c83da8a | 5183 | if (mips_opts.isa >= 3) |
670a50eb | 5184 | { |
0dd2d296 ILT |
5185 | s = "sd"; |
5186 | goto st; | |
670a50eb | 5187 | } |
0dd2d296 | 5188 | |
670a50eb | 5189 | s = "sw"; |
0dd2d296 ILT |
5190 | fmt = "t,o(b)"; |
5191 | ||
5192 | ldd_std: | |
5193 | if (offset_expr.X_op != O_symbol | |
5194 | && offset_expr.X_op != O_constant) | |
670a50eb | 5195 | { |
0dd2d296 ILT |
5196 | as_bad ("expression too complex"); |
5197 | offset_expr.X_op = O_constant; | |
5198 | } | |
5199 | ||
5200 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5201 | to adjust when loading from memory. We set coproc if we must | |
5202 | load $fn+1 first. */ | |
efec4a28 | 5203 | /* Itbl support may require additional care here. */ |
b9129c6f | 5204 | if (! target_big_endian) |
0dd2d296 ILT |
5205 | coproc = 0; |
5206 | ||
d9aba805 | 5207 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5208 | || offset_expr.X_op == O_constant) |
5209 | { | |
5210 | /* If this is a reference to a GP relative symbol, we want | |
5211 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5212 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5213 | If we have a base register, we use this | |
5214 | addu $at,$breg,$gp | |
5215 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5216 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5217 | If this is not a GP relative symbol, we want | |
5218 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5219 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5220 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5221 | If there is a base register, we add it to $at after the | |
5222 | lui instruction. If there is a constant, we always use | |
5223 | the last case. */ | |
7a15a226 | 5224 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5225 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5226 | { |
0dd2d296 ILT |
5227 | p = NULL; |
5228 | used_at = 1; | |
670a50eb ILT |
5229 | } |
5230 | else | |
0dd2d296 ILT |
5231 | { |
5232 | int off; | |
5233 | ||
5234 | if (breg == 0) | |
5235 | { | |
8ea7f4e8 | 5236 | frag_grow (28); |
0dd2d296 ILT |
5237 | tempreg = GP; |
5238 | off = 0; | |
5239 | used_at = 0; | |
5240 | } | |
5241 | else | |
5242 | { | |
8ea7f4e8 | 5243 | frag_grow (36); |
0dd2d296 | 5244 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 5245 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5246 | "d,v,t", AT, breg, GP); |
5247 | tempreg = AT; | |
5248 | off = 4; | |
5249 | used_at = 1; | |
5250 | } | |
5251 | ||
efec4a28 | 5252 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5253 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5254 | coproc ? treg + 1 : treg, | |
5255 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5256 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5257 | |
5258 | /* Set mips_optimize to 2 to avoid inserting an | |
5259 | undesired nop. */ | |
5260 | hold_mips_optimize = mips_optimize; | |
5261 | mips_optimize = 2; | |
efec4a28 | 5262 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5263 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5264 | coproc ? treg : treg + 1, | |
5265 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5266 | mips_optimize = hold_mips_optimize; |
5267 | ||
0dd2d296 ILT |
5268 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5269 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5270 | used_at && mips_opts.noat), |
f59fb6ca | 5271 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5272 | (char *) NULL); |
777ad64d ILT |
5273 | |
5274 | /* We just generated two relocs. When tc_gen_reloc | |
5275 | handles this case, it will skip the first reloc and | |
5276 | handle the second. The second reloc already has an | |
5277 | extra addend of 4, which we added above. We must | |
5278 | subtract it out, and then subtract another 4 to make | |
5279 | the first reloc come out right. The second reloc | |
5280 | will come out right because we are going to add 4 to | |
5281 | offset_expr when we build its instruction below. */ | |
5282 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
5283 | offset_expr.X_op = O_constant; |
5284 | } | |
5285 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5286 | if (p != NULL) | |
5287 | p += 4; | |
5288 | if (breg != 0) | |
5289 | { | |
5290 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 5291 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5292 | "d,v,t", AT, breg, AT); |
5293 | if (p != NULL) | |
5294 | p += 4; | |
5295 | } | |
efec4a28 | 5296 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5297 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5298 | coproc ? treg + 1 : treg, | |
5299 | (int) BFD_RELOC_LO16, AT); | |
5300 | if (p != NULL) | |
5301 | p += 4; | |
5302 | /* FIXME: How do we handle overflow here? */ | |
5303 | offset_expr.X_add_number += 4; | |
efec4a28 | 5304 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5305 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5306 | coproc ? treg : treg + 1, | |
5307 | (int) BFD_RELOC_LO16, AT); | |
5308 | } | |
fb251650 | 5309 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5310 | { |
0dd2d296 ILT |
5311 | int off; |
5312 | ||
5313 | /* If this is a reference to an external symbol, we want | |
5314 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5315 | nop | |
5316 | <op> $treg,0($at) | |
5317 | <op> $treg+1,4($at) | |
5318 | Otherwise we want | |
5319 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5320 | nop | |
5321 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5322 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5323 | If there is a base register we add it to $at before the | |
5324 | lwc1 instructions. If there is a constant we include it | |
5325 | in the lwc1 instructions. */ | |
5326 | used_at = 1; | |
5327 | expr1.X_add_number = offset_expr.X_add_number; | |
5328 | offset_expr.X_add_number = 0; | |
5329 | if (expr1.X_add_number < -0x8000 | |
5330 | || expr1.X_add_number >= 0x8000 - 4) | |
5331 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5332 | if (breg == 0) | |
5333 | off = 0; | |
5334 | else | |
5335 | off = 4; | |
8ea7f4e8 | 5336 | frag_grow (24 + off); |
0dd2d296 | 5337 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 5338 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
5339 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5340 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5341 | if (breg != 0) |
0dd2d296 | 5342 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 5343 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 | 5344 | "d,v,t", AT, breg, AT); |
efec4a28 | 5345 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5346 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5347 | coproc ? treg + 1 : treg, | |
5348 | (int) BFD_RELOC_LO16, AT); | |
5349 | expr1.X_add_number += 4; | |
55933a58 ILT |
5350 | |
5351 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5352 | nop. */ | |
5353 | hold_mips_optimize = mips_optimize; | |
5354 | mips_optimize = 2; | |
efec4a28 | 5355 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5356 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5357 | coproc ? treg : treg + 1, | |
5358 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5359 | mips_optimize = hold_mips_optimize; |
5360 | ||
0dd2d296 ILT |
5361 | (void) frag_var (rs_machine_dependent, 0, 0, |
5362 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5363 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5364 | (char *) NULL); |
8358c818 | 5365 | } |
fb251650 ILT |
5366 | else if (mips_pic == SVR4_PIC) |
5367 | { | |
5368 | int gpdel, off; | |
5369 | ||
5370 | /* If this is a reference to an external symbol, we want | |
5371 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5372 | addu $at,$at,$gp | |
5373 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5374 | nop | |
5375 | <op> $treg,0($at) | |
5376 | <op> $treg+1,4($at) | |
5377 | Otherwise we want | |
5378 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5379 | nop | |
5380 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5381 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5382 | If there is a base register we add it to $at before the | |
5383 | lwc1 instructions. If there is a constant we include it | |
5384 | in the lwc1 instructions. */ | |
5385 | used_at = 1; | |
5386 | expr1.X_add_number = offset_expr.X_add_number; | |
5387 | offset_expr.X_add_number = 0; | |
5388 | if (expr1.X_add_number < -0x8000 | |
5389 | || expr1.X_add_number >= 0x8000 - 4) | |
5390 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5391 | if (reg_needs_delay (GP)) | |
5392 | gpdel = 4; | |
5393 | else | |
5394 | gpdel = 0; | |
5395 | if (breg == 0) | |
5396 | off = 0; | |
5397 | else | |
5398 | off = 4; | |
5399 | frag_grow (56); | |
5400 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5401 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5402 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5403 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
5404 | "d,v,t", AT, AT, GP); |
5405 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5406 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
5407 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5408 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5409 | if (breg != 0) | |
5410 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5411 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 | 5412 | "d,v,t", AT, breg, AT); |
efec4a28 | 5413 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5414 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5415 | coproc ? treg + 1 : treg, | |
5416 | (int) BFD_RELOC_LO16, AT); | |
5417 | expr1.X_add_number += 4; | |
5418 | ||
5419 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5420 | nop. */ | |
5421 | hold_mips_optimize = mips_optimize; | |
5422 | mips_optimize = 2; | |
efec4a28 | 5423 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5424 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5425 | coproc ? treg : treg + 1, | |
5426 | (int) BFD_RELOC_LO16, AT); | |
5427 | mips_optimize = hold_mips_optimize; | |
5428 | expr1.X_add_number -= 4; | |
5429 | ||
5430 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5431 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5432 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5433 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5434 | (char *) NULL); |
5435 | if (gpdel > 0) | |
5436 | { | |
5437 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5438 | p += 4; | |
5439 | } | |
5440 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 5441 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
5442 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5443 | p += 4; | |
5444 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5445 | p += 4; | |
5446 | if (breg != 0) | |
5447 | { | |
5448 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 5449 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
5450 | "d,v,t", AT, breg, AT); |
5451 | p += 4; | |
5452 | } | |
efec4a28 | 5453 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5454 | macro_build (p, &icnt, &expr1, s, fmt, |
5455 | coproc ? treg + 1 : treg, | |
5456 | (int) BFD_RELOC_LO16, AT); | |
5457 | p += 4; | |
5458 | expr1.X_add_number += 4; | |
5459 | ||
5460 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5461 | nop. */ | |
5462 | hold_mips_optimize = mips_optimize; | |
5463 | mips_optimize = 2; | |
efec4a28 | 5464 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5465 | macro_build (p, &icnt, &expr1, s, fmt, |
5466 | coproc ? treg : treg + 1, | |
5467 | (int) BFD_RELOC_LO16, AT); | |
5468 | mips_optimize = hold_mips_optimize; | |
5469 | } | |
d9aba805 ILT |
5470 | else if (mips_pic == EMBEDDED_PIC) |
5471 | { | |
5472 | /* If there is no base register, we use | |
5473 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5474 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5475 | If we have a base register, we use | |
5476 | addu $at,$breg,$gp | |
5477 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5478 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5479 | */ | |
5480 | if (breg == 0) | |
5481 | { | |
5482 | tempreg = GP; | |
5483 | used_at = 0; | |
5484 | } | |
5485 | else | |
5486 | { | |
5487 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5488 | mips_opts.isa < 3 ? "addu" : "daddu", |
d9aba805 ILT |
5489 | "d,v,t", AT, breg, GP); |
5490 | tempreg = AT; | |
5491 | used_at = 1; | |
5492 | } | |
5493 | ||
efec4a28 | 5494 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5495 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5496 | coproc ? treg + 1 : treg, | |
5497 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5498 | offset_expr.X_add_number += 4; | |
efec4a28 | 5499 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5500 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5501 | coproc ? treg : treg + 1, | |
5502 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5503 | } | |
5504 | else | |
5505 | abort (); | |
0dd2d296 ILT |
5506 | |
5507 | if (! used_at) | |
5508 | return; | |
5509 | ||
5510 | break; | |
5511 | ||
5512 | case M_LD_OB: | |
5513 | s = "lw"; | |
5514 | goto sd_ob; | |
5515 | case M_SD_OB: | |
5516 | s = "sw"; | |
5517 | sd_ob: | |
3c83da8a | 5518 | assert (mips_opts.isa < 3); |
0dd2d296 ILT |
5519 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5520 | (int) BFD_RELOC_LO16, breg); | |
5521 | offset_expr.X_add_number += 4; | |
5522 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5523 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5524 | return; |
efec4a28 DP |
5525 | |
5526 | /* New code added to support COPZ instructions. | |
5527 | This code builds table entries out of the macros in mip_opcodes. | |
5528 | R4000 uses interlocks to handle coproc delays. | |
5529 | Other chips (like the R3000) require nops to be inserted for delays. | |
5530 | ||
5531 | FIXME: Currently, we require that the user handle delays. | |
5532 | In order to fill delay slots for non-interlocked chips, | |
5533 | we must have a way to specify delays based on the coprocessor. | |
5534 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5535 | What are the side-effects of the cop instruction? | |
5536 | What cache support might we have and what are its effects? | |
5537 | Both coprocessor & memory require delays. how long??? | |
5538 | What registers are read/set/modified? | |
5539 | ||
5540 | If an itbl is provided to interpret cop instructions, | |
5541 | this knowledge can be encoded in the itbl spec. */ | |
5542 | ||
5543 | case M_COP0: | |
5544 | s = "cop0"; | |
5545 | goto copz; | |
5546 | case M_COP1: | |
5547 | s = "cop1"; | |
5548 | goto copz; | |
5549 | case M_COP2: | |
5550 | s = "cop2"; | |
5551 | goto copz; | |
5552 | case M_COP3: | |
5553 | s = "cop3"; | |
5554 | copz: | |
5555 | /* For now we just do C (same as Cz). */ | |
9218cee0 | 5556 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "C"); |
efec4a28 DP |
5557 | return; |
5558 | ||
917fae09 SS |
5559 | #ifdef LOSING_COMPILER |
5560 | default: | |
efec4a28 DP |
5561 | /* Try and see if this is a new itbl instruction. |
5562 | This code builds table entries out of the macros in mip_opcodes. | |
5563 | FIXME: For now we just assemble the expression and pass it's | |
5564 | value along as a 32-bit immediate. | |
5565 | We may want to have the assembler assemble this value, | |
5566 | so that we gain the assembler's knowledge of delay slots, | |
5567 | symbols, etc. | |
5568 | Would it be more efficient to use mask (id) here? */ | |
5569 | if (itbl_have_entries | |
9218cee0 | 5570 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
5571 | { |
5572 | s = ip->insn_mo->name; | |
5573 | s2 = "cop3"; | |
9218cee0 | 5574 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
5575 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
5576 | return; | |
5577 | } | |
917fae09 SS |
5578 | macro2 (ip); |
5579 | return; | |
5580 | } | |
3c83da8a | 5581 | if (mips_opts.noat) |
917fae09 SS |
5582 | as_warn ("Macro used $at after \".set noat\""); |
5583 | } | |
5584 | ||
5585 | static void | |
5586 | macro2 (ip) | |
5587 | struct mips_cl_insn *ip; | |
5588 | { | |
5589 | register int treg, sreg, dreg, breg; | |
5590 | int tempreg; | |
5591 | int mask; | |
5592 | int icnt = 0; | |
5593 | int used_at; | |
5594 | expressionS expr1; | |
5595 | const char *s; | |
5596 | const char *s2; | |
5597 | const char *fmt; | |
5598 | int likely = 0; | |
5599 | int dbl = 0; | |
5600 | int coproc = 0; | |
adcf2b9d ILT |
5601 | int lr = 0; |
5602 | int off; | |
917fae09 SS |
5603 | offsetT maxnum; |
5604 | bfd_reloc_code_real_type r; | |
5605 | char *p; | |
5606 | ||
5607 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5608 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5609 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5610 | mask = ip->insn_mo->mask; | |
5611 | ||
5612 | expr1.X_op = O_constant; | |
5613 | expr1.X_op_symbol = NULL; | |
5614 | expr1.X_add_symbol = NULL; | |
5615 | expr1.X_add_number = 1; | |
5616 | ||
5617 | switch (mask) | |
5618 | { | |
5619 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5620 | |
8358c818 ILT |
5621 | case M_DMUL: |
5622 | dbl = 1; | |
3d3c5039 | 5623 | case M_MUL: |
0dd2d296 | 5624 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5625 | dbl ? "dmultu" : "multu", |
5626 | "s,t", sreg, treg); | |
0dd2d296 | 5627 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5628 | return; |
3d3c5039 | 5629 | |
8358c818 ILT |
5630 | case M_DMUL_I: |
5631 | dbl = 1; | |
3d3c5039 | 5632 | case M_MUL_I: |
8358c818 ILT |
5633 | /* The MIPS assembler some times generates shifts and adds. I'm |
5634 | not trying to be that fancy. GCC should do this for us | |
5635 | anyway. */ | |
d8a1c247 | 5636 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5637 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5638 | dbl ? "dmult" : "mult", |
5639 | "s,t", sreg, AT); | |
0dd2d296 | 5640 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5641 | break; |
3d3c5039 | 5642 | |
8358c818 ILT |
5643 | case M_DMULO: |
5644 | dbl = 1; | |
5645 | case M_MULO: | |
fbcfacb7 | 5646 | mips_emit_delays (true); |
3c83da8a | 5647 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5648 | mips_any_noreorder = 1; |
5649 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5650 | dbl ? "dmult" : "mult", |
5651 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5652 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5653 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5654 | dbl ? "dsra32" : "sra", |
5655 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5656 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5657 | if (mips_trap) |
5658 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5659 | else | |
5660 | { | |
5661 | expr1.X_add_number = 8; | |
5662 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5663 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5664 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5665 | } | |
3c83da8a | 5666 | --mips_opts.noreorder; |
0dd2d296 | 5667 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5668 | break; |
5669 | ||
5670 | case M_DMULOU: | |
5671 | dbl = 1; | |
5672 | case M_MULOU: | |
fbcfacb7 | 5673 | mips_emit_delays (true); |
3c83da8a | 5674 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5675 | mips_any_noreorder = 1; |
5676 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5677 | dbl ? "dmultu" : "multu", |
5678 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5679 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5680 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5681 | if (mips_trap) |
5682 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5683 | else | |
5684 | { | |
5685 | expr1.X_add_number = 8; | |
5686 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5687 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5688 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5689 | } | |
3c83da8a | 5690 | --mips_opts.noreorder; |
8358c818 ILT |
5691 | break; |
5692 | ||
3d3c5039 | 5693 | case M_ROL: |
0dd2d296 ILT |
5694 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5695 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5696 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5697 | treg); | |
5698 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5699 | break; |
3d3c5039 ILT |
5700 | |
5701 | case M_ROL_I: | |
5c6f5923 GRK |
5702 | if (imm_expr.X_op != O_constant) |
5703 | as_bad ("rotate count too large"); | |
0dd2d296 | 5704 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5705 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5706 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5707 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5708 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5709 | break; |
3d3c5039 ILT |
5710 | |
5711 | case M_ROR: | |
0dd2d296 ILT |
5712 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5713 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5714 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5715 | treg); | |
5716 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5717 | break; |
3d3c5039 ILT |
5718 | |
5719 | case M_ROR_I: | |
5c6f5923 GRK |
5720 | if (imm_expr.X_op != O_constant) |
5721 | as_bad ("rotate count too large"); | |
0dd2d296 | 5722 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5723 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5724 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5725 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5726 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5727 | break; |
3d3c5039 ILT |
5728 | |
5729 | case M_S_DOB: | |
3c83da8a | 5730 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
5731 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5732 | to adjust when storing to memory. */ | |
0dd2d296 | 5733 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5734 | target_big_endian ? treg + 1 : treg, |
9226253a | 5735 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5736 | offset_expr.X_add_number += 4; |
0dd2d296 | 5737 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5738 | target_big_endian ? treg : treg + 1, |
9226253a | 5739 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5740 | return; |
3d3c5039 | 5741 | |
3d3c5039 | 5742 | case M_SEQ: |
670a50eb | 5743 | if (sreg == 0) |
0dd2d296 ILT |
5744 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5745 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5746 | else if (treg == 0) |
0dd2d296 ILT |
5747 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5748 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5749 | else |
5750 | { | |
0dd2d296 ILT |
5751 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5752 | sreg, treg); | |
5753 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5754 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5755 | } |
670a50eb | 5756 | return; |
3d3c5039 ILT |
5757 | |
5758 | case M_SEQ_I: | |
5c6f5923 | 5759 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 5760 | { |
0dd2d296 ILT |
5761 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5762 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5763 | return; |
3d3c5039 | 5764 | } |
670a50eb ILT |
5765 | if (sreg == 0) |
5766 | { | |
9a7d824a | 5767 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5768 | ip->insn_mo->name); |
0dd2d296 | 5769 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5770 | return; |
3d3c5039 | 5771 | } |
5c6f5923 GRK |
5772 | if (imm_expr.X_op == O_constant |
5773 | && imm_expr.X_add_number >= 0 | |
5774 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 5775 | { |
0dd2d296 ILT |
5776 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5777 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5778 | used_at = 0; |
6e8dda9c | 5779 | } |
5c6f5923 GRK |
5780 | else if (imm_expr.X_op == O_constant |
5781 | && imm_expr.X_add_number > -0x8000 | |
5782 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
5783 | { |
5784 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5785 | macro_build ((char *) NULL, &icnt, &imm_expr, |
3c83da8a | 5786 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5787 | "t,r,j", dreg, sreg, |
5788 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5789 | used_at = 0; |
5790 | } | |
5791 | else | |
5792 | { | |
d8a1c247 | 5793 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5794 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5795 | sreg, AT); | |
670a50eb ILT |
5796 | used_at = 1; |
5797 | } | |
0dd2d296 | 5798 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5799 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5800 | if (used_at) |
5801 | break; | |
5802 | return; | |
3d3c5039 ILT |
5803 | |
5804 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5805 | s = "slt"; |
5806 | goto sge; | |
3d3c5039 | 5807 | case M_SGEU: |
670a50eb | 5808 | s = "sltu"; |
3d3c5039 | 5809 | sge: |
0dd2d296 ILT |
5810 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5811 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5812 | (int) BFD_RELOC_LO16); |
670a50eb | 5813 | return; |
3d3c5039 | 5814 | |
670a50eb | 5815 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5816 | case M_SGEU_I: |
5c6f5923 GRK |
5817 | if (imm_expr.X_op == O_constant |
5818 | && imm_expr.X_add_number >= -0x8000 | |
5819 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 5820 | { |
0dd2d296 | 5821 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5822 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5823 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5824 | used_at = 0; |
5825 | } | |
5826 | else | |
5827 | { | |
d8a1c247 | 5828 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5829 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5830 | mask == M_SGE_I ? "slt" : "sltu", |
5831 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5832 | used_at = 1; |
5833 | } | |
0dd2d296 | 5834 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5835 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5836 | if (used_at) |
5837 | break; | |
5838 | return; | |
3d3c5039 ILT |
5839 | |
5840 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5841 | s = "slt"; |
5842 | goto sgt; | |
3d3c5039 | 5843 | case M_SGTU: |
670a50eb | 5844 | s = "sltu"; |
3d3c5039 | 5845 | sgt: |
0dd2d296 | 5846 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5847 | return; |
3d3c5039 | 5848 | |
670a50eb ILT |
5849 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5850 | s = "slt"; | |
5851 | goto sgti; | |
3d3c5039 | 5852 | case M_SGTU_I: |
670a50eb | 5853 | s = "sltu"; |
3d3c5039 | 5854 | sgti: |
d8a1c247 | 5855 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5856 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5857 | break; |
3d3c5039 | 5858 | |
670a50eb ILT |
5859 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5860 | s = "slt"; | |
5861 | goto sle; | |
3d3c5039 | 5862 | case M_SLEU: |
670a50eb | 5863 | s = "sltu"; |
3d3c5039 | 5864 | sle: |
0dd2d296 ILT |
5865 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5866 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5867 | (int) BFD_RELOC_LO16); |
670a50eb | 5868 | return; |
3d3c5039 | 5869 | |
670a50eb ILT |
5870 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5871 | s = "slt"; | |
5872 | goto slei; | |
3d3c5039 | 5873 | case M_SLEU_I: |
670a50eb | 5874 | s = "sltu"; |
3d3c5039 | 5875 | slei: |
d8a1c247 | 5876 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5877 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5878 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5879 | (int) BFD_RELOC_LO16); |
670a50eb | 5880 | break; |
3d3c5039 ILT |
5881 | |
5882 | case M_SLT_I: | |
5c6f5923 GRK |
5883 | if (imm_expr.X_op == O_constant |
5884 | && imm_expr.X_add_number >= -0x8000 | |
5885 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 5886 | { |
0dd2d296 ILT |
5887 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5888 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5889 | return; |
3d3c5039 | 5890 | } |
d8a1c247 | 5891 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5892 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5893 | break; |
3d3c5039 ILT |
5894 | |
5895 | case M_SLTU_I: | |
5c6f5923 GRK |
5896 | if (imm_expr.X_op == O_constant |
5897 | && imm_expr.X_add_number >= -0x8000 | |
5898 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 5899 | { |
0dd2d296 ILT |
5900 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5901 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5902 | return; |
3d3c5039 | 5903 | } |
d8a1c247 | 5904 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5905 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5906 | AT); | |
670a50eb | 5907 | break; |
3d3c5039 ILT |
5908 | |
5909 | case M_SNE: | |
670a50eb | 5910 | if (sreg == 0) |
0dd2d296 ILT |
5911 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5912 | treg); | |
670a50eb | 5913 | else if (treg == 0) |
0dd2d296 ILT |
5914 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5915 | sreg); | |
670a50eb ILT |
5916 | else |
5917 | { | |
0dd2d296 ILT |
5918 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5919 | sreg, treg); | |
5920 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5921 | dreg); | |
3d3c5039 | 5922 | } |
670a50eb | 5923 | return; |
3d3c5039 ILT |
5924 | |
5925 | case M_SNE_I: | |
5c6f5923 | 5926 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 5927 | { |
0dd2d296 ILT |
5928 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5929 | sreg); | |
670a50eb | 5930 | return; |
3d3c5039 | 5931 | } |
670a50eb ILT |
5932 | if (sreg == 0) |
5933 | { | |
9a7d824a | 5934 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5935 | ip->insn_mo->name); |
0dd2d296 | 5936 | macro_build ((char *) NULL, &icnt, &expr1, |
3c83da8a | 5937 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a | 5938 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5939 | return; |
3d3c5039 | 5940 | } |
5c6f5923 GRK |
5941 | if (imm_expr.X_op == O_constant |
5942 | && imm_expr.X_add_number >= 0 | |
5943 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 5944 | { |
0dd2d296 ILT |
5945 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5946 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5947 | used_at = 0; |
6e8dda9c | 5948 | } |
5c6f5923 GRK |
5949 | else if (imm_expr.X_op == O_constant |
5950 | && imm_expr.X_add_number > -0x8000 | |
5951 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
5952 | { |
5953 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5954 | macro_build ((char *) NULL, &icnt, &imm_expr, |
3c83da8a | 5955 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a | 5956 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5957 | used_at = 0; |
5958 | } | |
5959 | else | |
5960 | { | |
d8a1c247 | 5961 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5962 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5963 | sreg, AT); | |
670a50eb ILT |
5964 | used_at = 1; |
5965 | } | |
0dd2d296 | 5966 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5967 | if (used_at) |
5968 | break; | |
5969 | return; | |
3d3c5039 | 5970 | |
8358c818 ILT |
5971 | case M_DSUB_I: |
5972 | dbl = 1; | |
3d3c5039 | 5973 | case M_SUB_I: |
5c6f5923 GRK |
5974 | if (imm_expr.X_op == O_constant |
5975 | && imm_expr.X_add_number > -0x8000 | |
5976 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
5977 | { |
5978 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5979 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5980 | dbl ? "daddi" : "addi", |
9226253a | 5981 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5982 | return; |
3d3c5039 | 5983 | } |
d8a1c247 | 5984 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5985 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5986 | dbl ? "dsub" : "sub", |
5987 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5988 | break; |
3d3c5039 | 5989 | |
8358c818 ILT |
5990 | case M_DSUBU_I: |
5991 | dbl = 1; | |
3d3c5039 | 5992 | case M_SUBU_I: |
5c6f5923 GRK |
5993 | if (imm_expr.X_op == O_constant |
5994 | && imm_expr.X_add_number > -0x8000 | |
5995 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
5996 | { |
5997 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5998 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5999 | dbl ? "daddiu" : "addiu", |
9226253a | 6000 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6001 | return; |
3d3c5039 | 6002 | } |
d8a1c247 | 6003 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6004 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6005 | dbl ? "dsubu" : "subu", |
6006 | "d,v,t", dreg, sreg, AT); | |
6007 | break; | |
6008 | ||
6009 | case M_TEQ_I: | |
6010 | s = "teq"; | |
6011 | goto trap; | |
6012 | case M_TGE_I: | |
6013 | s = "tge"; | |
6014 | goto trap; | |
6015 | case M_TGEU_I: | |
6016 | s = "tgeu"; | |
6017 | goto trap; | |
6018 | case M_TLT_I: | |
6019 | s = "tlt"; | |
6020 | goto trap; | |
6021 | case M_TLTU_I: | |
6022 | s = "tltu"; | |
6023 | goto trap; | |
6024 | case M_TNE_I: | |
6025 | s = "tne"; | |
6026 | trap: | |
d8a1c247 | 6027 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6028 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6029 | break; |
3d3c5039 ILT |
6030 | |
6031 | case M_TRUNCWD: | |
6032 | case M_TRUNCWS: | |
3c83da8a | 6033 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6034 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6035 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6036 | ||
6037 | /* | |
6038 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6039 | * or is there a reason for it? | |
6040 | */ | |
fbcfacb7 | 6041 | mips_emit_delays (true); |
3c83da8a | 6042 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6043 | mips_any_noreorder = 1; |
6044 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6045 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6046 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6047 | expr1.X_add_number = 3; |
0dd2d296 | 6048 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6049 | (int) BFD_RELOC_LO16); |
670a50eb | 6050 | expr1.X_add_number = 2; |
0dd2d296 | 6051 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6052 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6053 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6054 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6055 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6056 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6057 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6058 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6059 | --mips_opts.noreorder; |
670a50eb | 6060 | break; |
3d3c5039 ILT |
6061 | |
6062 | case M_ULH: | |
670a50eb ILT |
6063 | s = "lb"; |
6064 | goto ulh; | |
3d3c5039 | 6065 | case M_ULHU: |
670a50eb | 6066 | s = "lbu"; |
3d3c5039 | 6067 | ulh: |
8ea7f4e8 ILT |
6068 | if (offset_expr.X_add_number >= 0x7fff) |
6069 | as_bad ("operand overflow"); | |
670a50eb | 6070 | /* avoid load delay */ |
b9129c6f | 6071 | if (! target_big_endian) |
8ea7f4e8 | 6072 | offset_expr.X_add_number += 1; |
0dd2d296 | 6073 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6074 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6075 | if (! target_big_endian) |
8ea7f4e8 ILT |
6076 | offset_expr.X_add_number -= 1; |
6077 | else | |
6078 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6079 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6080 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6081 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6082 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6083 | break; |
3d3c5039 | 6084 | |
adcf2b9d ILT |
6085 | case M_ULD: |
6086 | s = "ldl"; | |
6087 | s2 = "ldr"; | |
6088 | off = 7; | |
6089 | goto ulw; | |
3d3c5039 | 6090 | case M_ULW: |
adcf2b9d ILT |
6091 | s = "lwl"; |
6092 | s2 = "lwr"; | |
6093 | off = 3; | |
6094 | ulw: | |
6095 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6096 | as_bad ("operand overflow"); |
b9129c6f | 6097 | if (! target_big_endian) |
adcf2b9d ILT |
6098 | offset_expr.X_add_number += off; |
6099 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6100 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6101 | if (! target_big_endian) |
adcf2b9d | 6102 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6103 | else |
adcf2b9d ILT |
6104 | offset_expr.X_add_number += off; |
6105 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6106 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6107 | return; |
3d3c5039 | 6108 | |
adcf2b9d ILT |
6109 | case M_ULD_A: |
6110 | s = "ldl"; | |
6111 | s2 = "ldr"; | |
6112 | off = 7; | |
6113 | goto ulwa; | |
6114 | case M_ULW_A: | |
6115 | s = "lwl"; | |
6116 | s2 = "lwr"; | |
6117 | off = 3; | |
6118 | ulwa: | |
6119 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6120 | if (breg != 0) |
6121 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6122 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6123 | "d,v,t", AT, AT, breg); |
b9129c6f | 6124 | if (! target_big_endian) |
adcf2b9d ILT |
6125 | expr1.X_add_number = off; |
6126 | else | |
6127 | expr1.X_add_number = 0; | |
6128 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6129 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6130 | if (! target_big_endian) |
adcf2b9d ILT |
6131 | expr1.X_add_number = 0; |
6132 | else | |
6133 | expr1.X_add_number = off; | |
6134 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6135 | (int) BFD_RELOC_LO16, AT); | |
6136 | break; | |
6137 | ||
3d3c5039 ILT |
6138 | case M_ULH_A: |
6139 | case M_ULHU_A: | |
0dd2d296 | 6140 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6141 | if (breg != 0) |
6142 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6143 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6144 | "d,v,t", AT, AT, breg); |
b9129c6f | 6145 | if (target_big_endian) |
adcf2b9d ILT |
6146 | expr1.X_add_number = 0; |
6147 | macro_build ((char *) NULL, &icnt, &expr1, | |
6148 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6149 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6150 | if (target_big_endian) |
adcf2b9d | 6151 | expr1.X_add_number = 1; |
670a50eb | 6152 | else |
adcf2b9d ILT |
6153 | expr1.X_add_number = 0; |
6154 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6155 | (int) BFD_RELOC_LO16, AT); | |
6156 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6157 | treg, 8); | |
6158 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6159 | treg, AT); | |
670a50eb | 6160 | break; |
3d3c5039 ILT |
6161 | |
6162 | case M_USH: | |
8ea7f4e8 ILT |
6163 | if (offset_expr.X_add_number >= 0x7fff) |
6164 | as_bad ("operand overflow"); | |
b9129c6f | 6165 | if (target_big_endian) |
8ea7f4e8 | 6166 | offset_expr.X_add_number += 1; |
0dd2d296 | 6167 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6168 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6169 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6170 | if (target_big_endian) |
8ea7f4e8 ILT |
6171 | offset_expr.X_add_number -= 1; |
6172 | else | |
6173 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6174 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6175 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6176 | break; |
3d3c5039 | 6177 | |
adcf2b9d ILT |
6178 | case M_USD: |
6179 | s = "sdl"; | |
6180 | s2 = "sdr"; | |
6181 | off = 7; | |
6182 | goto usw; | |
3d3c5039 | 6183 | case M_USW: |
adcf2b9d ILT |
6184 | s = "swl"; |
6185 | s2 = "swr"; | |
6186 | off = 3; | |
6187 | usw: | |
6188 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6189 | as_bad ("operand overflow"); |
b9129c6f | 6190 | if (! target_big_endian) |
adcf2b9d ILT |
6191 | offset_expr.X_add_number += off; |
6192 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6193 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6194 | if (! target_big_endian) |
adcf2b9d | 6195 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6196 | else |
adcf2b9d ILT |
6197 | offset_expr.X_add_number += off; |
6198 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6199 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6200 | return; |
3d3c5039 | 6201 | |
adcf2b9d ILT |
6202 | case M_USD_A: |
6203 | s = "sdl"; | |
6204 | s2 = "sdr"; | |
6205 | off = 7; | |
6206 | goto uswa; | |
3d3c5039 | 6207 | case M_USW_A: |
adcf2b9d ILT |
6208 | s = "swl"; |
6209 | s2 = "swr"; | |
6210 | off = 3; | |
6211 | uswa: | |
0dd2d296 | 6212 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6213 | if (breg != 0) |
6214 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6215 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6216 | "d,v,t", AT, AT, breg); |
b9129c6f | 6217 | if (! target_big_endian) |
adcf2b9d | 6218 | expr1.X_add_number = off; |
670a50eb | 6219 | else |
adcf2b9d ILT |
6220 | expr1.X_add_number = 0; |
6221 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6222 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6223 | if (! target_big_endian) |
adcf2b9d ILT |
6224 | expr1.X_add_number = 0; |
6225 | else | |
6226 | expr1.X_add_number = off; | |
6227 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6228 | (int) BFD_RELOC_LO16, AT); | |
6229 | break; | |
6230 | ||
6231 | case M_USH_A: | |
6232 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6233 | if (breg != 0) |
6234 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6235 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6236 | "d,v,t", AT, AT, breg); |
b9129c6f | 6237 | if (! target_big_endian) |
adcf2b9d ILT |
6238 | expr1.X_add_number = 0; |
6239 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6240 | (int) BFD_RELOC_LO16, AT); | |
6241 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6242 | treg, 8); | |
b9129c6f | 6243 | if (! target_big_endian) |
adcf2b9d ILT |
6244 | expr1.X_add_number = 1; |
6245 | else | |
6246 | expr1.X_add_number = 0; | |
6247 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6248 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6249 | if (! target_big_endian) |
adcf2b9d ILT |
6250 | expr1.X_add_number = 0; |
6251 | else | |
6252 | expr1.X_add_number = 1; | |
6253 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6254 | (int) BFD_RELOC_LO16, AT); | |
6255 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6256 | treg, 8); | |
6257 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6258 | treg, AT); | |
670a50eb | 6259 | break; |
3d3c5039 ILT |
6260 | |
6261 | default: | |
9218cee0 ILT |
6262 | /* FIXME: Check if this is one of the itbl macros, since they |
6263 | are added dynamically. */ | |
670a50eb | 6264 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 6265 | break; |
3d3c5039 | 6266 | } |
3c83da8a | 6267 | if (mips_opts.noat) |
670a50eb | 6268 | as_warn ("Macro used $at after \".set noat\""); |
3d3c5039 ILT |
6269 | } |
6270 | ||
cc5703cd | 6271 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6272 | |
3d3c5039 | 6273 | static void |
cc5703cd | 6274 | mips16_macro (ip) |
3d3c5039 ILT |
6275 | struct mips_cl_insn *ip; |
6276 | { | |
cc5703cd ILT |
6277 | int mask; |
6278 | int xreg, yreg, zreg, tmp; | |
6279 | int icnt; | |
6280 | expressionS expr1; | |
6281 | int dbl; | |
6282 | const char *s, *s2, *s3; | |
3d3c5039 | 6283 | |
cc5703cd | 6284 | mask = ip->insn_mo->mask; |
3d3c5039 | 6285 | |
cc5703cd ILT |
6286 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6287 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6288 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6289 | |
cc5703cd | 6290 | icnt = 0; |
8358c818 | 6291 | |
cc5703cd ILT |
6292 | expr1.X_op = O_constant; |
6293 | expr1.X_op_symbol = NULL; | |
6294 | expr1.X_add_symbol = NULL; | |
6295 | expr1.X_add_number = 1; | |
8358c818 | 6296 | |
cc5703cd | 6297 | dbl = 0; |
517078c1 | 6298 | |
cc5703cd ILT |
6299 | switch (mask) |
6300 | { | |
6301 | default: | |
6302 | internalError (); | |
6303 | ||
6304 | case M_DDIV_3: | |
6305 | dbl = 1; | |
6306 | case M_DIV_3: | |
6307 | s = "mflo"; | |
6308 | goto do_div3; | |
6309 | case M_DREM_3: | |
6310 | dbl = 1; | |
6311 | case M_REM_3: | |
6312 | s = "mfhi"; | |
6313 | do_div3: | |
fbcfacb7 | 6314 | mips_emit_delays (true); |
3c83da8a | 6315 | ++mips_opts.noreorder; |
cc5703cd ILT |
6316 | mips_any_noreorder = 1; |
6317 | macro_build ((char *) NULL, &icnt, NULL, | |
6318 | dbl ? "ddiv" : "div", | |
6319 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6320 | expr1.X_add_number = 2; |
cc5703cd | 6321 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6322 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6323 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6324 | since that causes an overflow. We should do that as well, | |
6325 | but I don't see how to do the comparisons without a temporary | |
6326 | register. */ | |
3c83da8a | 6327 | --mips_opts.noreorder; |
cc5703cd ILT |
6328 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6329 | break; | |
6330 | ||
6331 | case M_DIVU_3: | |
6332 | s = "divu"; | |
6333 | s2 = "mflo"; | |
6334 | goto do_divu3; | |
6335 | case M_REMU_3: | |
6336 | s = "divu"; | |
6337 | s2 = "mfhi"; | |
6338 | goto do_divu3; | |
6339 | case M_DDIVU_3: | |
6340 | s = "ddivu"; | |
6341 | s2 = "mflo"; | |
6342 | goto do_divu3; | |
6343 | case M_DREMU_3: | |
6344 | s = "ddivu"; | |
6345 | s2 = "mfhi"; | |
6346 | do_divu3: | |
fbcfacb7 | 6347 | mips_emit_delays (true); |
3c83da8a | 6348 | ++mips_opts.noreorder; |
cc5703cd ILT |
6349 | mips_any_noreorder = 1; |
6350 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6351 | expr1.X_add_number = 2; |
cc5703cd | 6352 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd | 6353 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
3c83da8a | 6354 | --mips_opts.noreorder; |
cc5703cd ILT |
6355 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6356 | break; | |
6357 | ||
08438bef ILT |
6358 | case M_DMUL: |
6359 | dbl = 1; | |
6360 | case M_MUL: | |
6361 | macro_build ((char *) NULL, &icnt, NULL, | |
6362 | dbl ? "dmultu" : "multu", | |
6363 | "x,y", xreg, yreg); | |
6364 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6365 | return; | |
6366 | ||
cc5703cd ILT |
6367 | case M_DSUBU_I: |
6368 | dbl = 1; | |
6369 | goto do_subu; | |
6370 | case M_SUBU_I: | |
6371 | do_subu: | |
5c6f5923 GRK |
6372 | if (imm_expr.X_op != O_constant) |
6373 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6374 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6375 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6376 | dbl ? "daddiu" : "addiu", | |
6377 | "y,x,4", yreg, xreg); | |
6378 | break; | |
6379 | ||
6380 | case M_SUBU_I_2: | |
5c6f5923 GRK |
6381 | if (imm_expr.X_op != O_constant) |
6382 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6383 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6384 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6385 | "x,k", xreg); | |
6386 | break; | |
6387 | ||
6388 | case M_DSUBU_I_2: | |
5c6f5923 GRK |
6389 | if (imm_expr.X_op != O_constant) |
6390 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6391 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6392 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6393 | "y,j", yreg); | |
6394 | break; | |
6395 | ||
6396 | case M_BEQ: | |
6397 | s = "cmp"; | |
6398 | s2 = "bteqz"; | |
6399 | goto do_branch; | |
6400 | case M_BNE: | |
6401 | s = "cmp"; | |
6402 | s2 = "btnez"; | |
6403 | goto do_branch; | |
6404 | case M_BLT: | |
6405 | s = "slt"; | |
6406 | s2 = "btnez"; | |
6407 | goto do_branch; | |
6408 | case M_BLTU: | |
6409 | s = "sltu"; | |
6410 | s2 = "btnez"; | |
6411 | goto do_branch; | |
6412 | case M_BLE: | |
6413 | s = "slt"; | |
6414 | s2 = "bteqz"; | |
6415 | goto do_reverse_branch; | |
6416 | case M_BLEU: | |
6417 | s = "sltu"; | |
6418 | s2 = "bteqz"; | |
6419 | goto do_reverse_branch; | |
6420 | case M_BGE: | |
6421 | s = "slt"; | |
6422 | s2 = "bteqz"; | |
6423 | goto do_branch; | |
6424 | case M_BGEU: | |
6425 | s = "sltu"; | |
6426 | s2 = "bteqz"; | |
6427 | goto do_branch; | |
6428 | case M_BGT: | |
6429 | s = "slt"; | |
6430 | s2 = "btnez"; | |
6431 | goto do_reverse_branch; | |
6432 | case M_BGTU: | |
6433 | s = "sltu"; | |
6434 | s2 = "btnez"; | |
6435 | ||
6436 | do_reverse_branch: | |
6437 | tmp = xreg; | |
6438 | xreg = yreg; | |
6439 | yreg = tmp; | |
6440 | ||
6441 | do_branch: | |
6442 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6443 | xreg, yreg); | |
6444 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6445 | break; | |
6446 | ||
6447 | case M_BEQ_I: | |
6448 | s = "cmpi"; | |
6449 | s2 = "bteqz"; | |
6450 | s3 = "x,U"; | |
6451 | goto do_branch_i; | |
6452 | case M_BNE_I: | |
6453 | s = "cmpi"; | |
6454 | s2 = "btnez"; | |
6455 | s3 = "x,U"; | |
6456 | goto do_branch_i; | |
6457 | case M_BLT_I: | |
6458 | s = "slti"; | |
6459 | s2 = "btnez"; | |
6460 | s3 = "x,8"; | |
6461 | goto do_branch_i; | |
6462 | case M_BLTU_I: | |
6463 | s = "sltiu"; | |
6464 | s2 = "btnez"; | |
6465 | s3 = "x,8"; | |
6466 | goto do_branch_i; | |
6467 | case M_BLE_I: | |
6468 | s = "slti"; | |
6469 | s2 = "btnez"; | |
6470 | s3 = "x,8"; | |
6471 | goto do_addone_branch_i; | |
6472 | case M_BLEU_I: | |
6473 | s = "sltiu"; | |
6474 | s2 = "btnez"; | |
6475 | s3 = "x,8"; | |
6476 | goto do_addone_branch_i; | |
6477 | case M_BGE_I: | |
6478 | s = "slti"; | |
6479 | s2 = "bteqz"; | |
6480 | s3 = "x,8"; | |
6481 | goto do_branch_i; | |
6482 | case M_BGEU_I: | |
6483 | s = "sltiu"; | |
6484 | s2 = "bteqz"; | |
6485 | s3 = "x,8"; | |
6486 | goto do_branch_i; | |
6487 | case M_BGT_I: | |
6488 | s = "slti"; | |
6489 | s2 = "bteqz"; | |
6490 | s3 = "x,8"; | |
6491 | goto do_addone_branch_i; | |
6492 | case M_BGTU_I: | |
6493 | s = "sltiu"; | |
6494 | s2 = "bteqz"; | |
6495 | s3 = "x,8"; | |
6496 | ||
6497 | do_addone_branch_i: | |
5c6f5923 GRK |
6498 | if (imm_expr.X_op != O_constant) |
6499 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6500 | ++imm_expr.X_add_number; |
6501 | ||
6502 | do_branch_i: | |
6503 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6504 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6505 | break; | |
18e0764d ILT |
6506 | |
6507 | case M_ABS: | |
6508 | expr1.X_add_number = 0; | |
6509 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6510 | if (xreg != yreg) | |
6511 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6512 | "move", "y,X", xreg, yreg); | |
6513 | expr1.X_add_number = 2; | |
6514 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6515 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6516 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6517 | } |
6518 | } | |
6519 | ||
6520 | /* This routine assembles an instruction into its binary format. As a | |
6521 | side effect, it sets one of the global variables imm_reloc or | |
6522 | offset_reloc to the type of relocation to do if one of the operands | |
6523 | is an address expression. */ | |
6524 | ||
6525 | static void | |
6526 | mips_ip (str, ip) | |
6527 | char *str; | |
6528 | struct mips_cl_insn *ip; | |
6529 | { | |
6530 | char *s; | |
6531 | const char *args; | |
6532 | char c; | |
6533 | struct mips_opcode *insn; | |
6534 | char *argsStart; | |
6535 | unsigned int regno; | |
6536 | unsigned int lastregno = 0; | |
6537 | char *s_reset; | |
6538 | ||
6539 | insn_error = NULL; | |
6540 | ||
e2e5acfa | 6541 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 6542 | continue; |
1857d1e6 | 6543 | if (isspace (*s)) |
e2e5acfa | 6544 | *s++ = '\0'; |
1857d1e6 | 6545 | |
cc5703cd ILT |
6546 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
6547 | { | |
6548 | insn_error = "unrecognized opcode"; | |
6549 | return; | |
6550 | } | |
6551 | argsStart = s; | |
6552 | for (;;) | |
6553 | { | |
6554 | int insn_isa; | |
6555 | ||
6556 | assert (strcmp (insn->name, str) == 0); | |
6557 | ||
6558 | if (insn->pinfo == INSN_MACRO) | |
6559 | insn_isa = insn->match; | |
5c6f5923 | 6560 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 6561 | insn_isa = 2; |
5c6f5923 | 6562 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 6563 | insn_isa = 3; |
5c6f5923 | 6564 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
6565 | insn_isa = 4; |
6566 | else | |
6567 | insn_isa = 1; | |
6568 | ||
3c83da8a | 6569 | if (insn_isa > mips_opts.isa |
16262668 | 6570 | || (insn->pinfo != INSN_MACRO |
5c6f5923 GRK |
6571 | && (((insn->membership & INSN_ISA) == INSN_4650 |
6572 | && ! mips_4650) | |
6573 | || ((insn->membership & INSN_ISA) == INSN_4010 | |
16262668 | 6574 | && ! mips_4010) |
5c6f5923 | 6575 | || ((insn->membership & INSN_ISA) == INSN_4100 |
16262668 ILT |
6576 | && ! mips_4100) |
6577 | /* start-sanitize-r5900 */ | |
5c6f5923 | 6578 | || ((insn->membership & INSN_ISA) == INSN_5900 |
16262668 ILT |
6579 | && ! mips_5900) |
6580 | /* end-sanitize-r5900 */ | |
5c6f5923 GRK |
6581 | || ((insn->membership & INSN_ISA) == INSN_3900 |
6582 | && ! mips_3900) | |
6583 | ))) | |
cc5703cd ILT |
6584 | { |
6585 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6586 | && strcmp (insn->name, insn[1].name) == 0) | |
6587 | { | |
6588 | ++insn; | |
6589 | continue; | |
6590 | } | |
3c83da8a | 6591 | if (insn_isa <= mips_opts.isa) |
cc5703cd ILT |
6592 | insn_error = "opcode not supported on this processor"; |
6593 | else | |
6594 | { | |
6595 | static char buf[100]; | |
6596 | ||
6597 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6598 | insn_error = buf; | |
6599 | } | |
6600 | return; | |
6601 | } | |
8358c818 | 6602 | |
670a50eb ILT |
6603 | ip->insn_mo = insn; |
6604 | ip->insn_opcode = insn->match; | |
6605 | for (args = insn->args;; ++args) | |
6606 | { | |
6607 | if (*s == ' ') | |
6608 | ++s; | |
6609 | switch (*args) | |
6610 | { | |
6611 | case '\0': /* end of args */ | |
6612 | if (*s == '\0') | |
6613 | return; | |
6614 | break; | |
3d3c5039 ILT |
6615 | |
6616 | case ',': | |
670a50eb ILT |
6617 | if (*s++ == *args) |
6618 | continue; | |
6619 | s--; | |
6620 | switch (*++args) | |
6621 | { | |
3d3c5039 ILT |
6622 | case 'r': |
6623 | case 'v': | |
670a50eb ILT |
6624 | ip->insn_opcode |= lastregno << 21; |
6625 | continue; | |
3d3c5039 ILT |
6626 | |
6627 | case 'w': | |
6628 | case 'W': | |
670a50eb ILT |
6629 | ip->insn_opcode |= lastregno << 16; |
6630 | continue; | |
3d3c5039 ILT |
6631 | |
6632 | case 'V': | |
670a50eb ILT |
6633 | ip->insn_opcode |= lastregno << 11; |
6634 | continue; | |
3d3c5039 | 6635 | } |
670a50eb | 6636 | break; |
3d3c5039 ILT |
6637 | |
6638 | case '(': | |
670a50eb ILT |
6639 | /* handle optional base register. |
6640 | Either the base register is omitted or | |
6641 | we must have a left paren. */ | |
6642 | /* this is dependent on the next operand specifier | |
6643 | is a 'b' for base register */ | |
6644 | assert (args[1] == 'b'); | |
6645 | if (*s == '\0') | |
6646 | return; | |
3d3c5039 | 6647 | |
670a50eb ILT |
6648 | case ')': /* these must match exactly */ |
6649 | if (*s++ == *args) | |
3d3c5039 | 6650 | continue; |
670a50eb ILT |
6651 | break; |
6652 | ||
6653 | case '<': /* must be at least one digit */ | |
6654 | /* | |
6655 | * According to the manual, if the shift amount is greater | |
6656 | * than 31 or less than 0 the the shift amount should be | |
6657 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6658 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6659 | */ |
6660 | my_getExpression (&imm_expr, s); | |
6661 | check_absolute_expr (ip, &imm_expr); | |
6662 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6663 | { | |
58d4951d ILT |
6664 | as_warn ("Improper shift amount (%ld)", |
6665 | (long) imm_expr.X_add_number); | |
9226253a | 6666 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6667 | } |
6668 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6669 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6670 | s = expr_end; |
6671 | continue; | |
6672 | ||
56c96faa ILT |
6673 | case '>': /* shift amount minus 32 */ |
6674 | my_getExpression (&imm_expr, s); | |
6675 | check_absolute_expr (ip, &imm_expr); | |
6676 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6677 | || (unsigned long) imm_expr.X_add_number > 63) | |
6678 | break; | |
6679 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6680 | imm_expr.X_op = O_absent; | |
6681 | s = expr_end; | |
6682 | continue; | |
6683 | ||
9226253a | 6684 | case 'k': /* cache code */ |
d8a1c247 | 6685 | case 'h': /* prefx code */ |
9226253a ILT |
6686 | my_getExpression (&imm_expr, s); |
6687 | check_absolute_expr (ip, &imm_expr); | |
6688 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6689 | { | |
d8a1c247 KR |
6690 | as_warn ("Invalid value for `%s' (%lu)", |
6691 | ip->insn_mo->name, | |
9226253a ILT |
6692 | (unsigned long) imm_expr.X_add_number); |
6693 | imm_expr.X_add_number &= 0x1f; | |
6694 | } | |
d8a1c247 KR |
6695 | if (*args == 'k') |
6696 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6697 | else | |
6698 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6699 | imm_expr.X_op = O_absent; |
6700 | s = expr_end; | |
6701 | continue; | |
6702 | ||
670a50eb ILT |
6703 | case 'c': /* break code */ |
6704 | my_getExpression (&imm_expr, s); | |
6705 | check_absolute_expr (ip, &imm_expr); | |
6706 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6707 | as_warn ("Illegal break code (%ld)", |
6708 | (long) imm_expr.X_add_number); | |
670a50eb | 6709 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6710 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6711 | s = expr_end; |
6712 | continue; | |
6713 | ||
918692a5 ILT |
6714 | case 'B': /* syscall code */ |
6715 | my_getExpression (&imm_expr, s); | |
6716 | check_absolute_expr (ip, &imm_expr); | |
6717 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6718 | as_warn ("Illegal syscall code (%ld)", |
6719 | (long) imm_expr.X_add_number); | |
918692a5 | 6720 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6721 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6722 | s = expr_end; |
6723 | continue; | |
6724 | ||
0aa07269 ILT |
6725 | case 'C': /* Coprocessor code */ |
6726 | my_getExpression (&imm_expr, s); | |
6727 | check_absolute_expr (ip, &imm_expr); | |
6728 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6729 | { | |
58d4951d ILT |
6730 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6731 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6732 | imm_expr.X_add_number &= ((1<<25) - 1); |
6733 | } | |
6734 | ip->insn_opcode |= imm_expr.X_add_number; | |
6735 | imm_expr.X_op = O_absent; | |
6736 | s = expr_end; | |
6737 | continue; | |
6738 | ||
670a50eb ILT |
6739 | case 'b': /* base register */ |
6740 | case 'd': /* destination register */ | |
6741 | case 's': /* source register */ | |
6742 | case 't': /* target register */ | |
6743 | case 'r': /* both target and source */ | |
6744 | case 'v': /* both dest and source */ | |
6745 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6746 | case 'E': /* coprocessor target register */ |
6747 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6748 | case 'x': /* ignore register name */ |
ff3a5c18 | 6749 | case 'z': /* must be zero register */ |
670a50eb ILT |
6750 | s_reset = s; |
6751 | if (s[0] == '$') | |
6752 | { | |
6753 | if (isdigit (s[1])) | |
6754 | { | |
6755 | ++s; | |
6756 | regno = 0; | |
6757 | do | |
6758 | { | |
6759 | regno *= 10; | |
6760 | regno += *s - '0'; | |
6761 | ++s; | |
6762 | } | |
6763 | while (isdigit (*s)); | |
0aa07269 ILT |
6764 | if (regno > 31) |
6765 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6766 | } |
0dd2d296 ILT |
6767 | else if (*args == 'E' || *args == 'G') |
6768 | goto notreg; | |
6769 | else | |
670a50eb | 6770 | { |
0aa07269 ILT |
6771 | if (s[1] == 'f' && s[2] == 'p') |
6772 | { | |
6773 | s += 3; | |
9226253a | 6774 | regno = FP; |
0aa07269 ILT |
6775 | } |
6776 | else if (s[1] == 's' && s[2] == 'p') | |
6777 | { | |
6778 | s += 3; | |
9226253a | 6779 | regno = SP; |
0aa07269 ILT |
6780 | } |
6781 | else if (s[1] == 'g' && s[2] == 'p') | |
6782 | { | |
6783 | s += 3; | |
9226253a | 6784 | regno = GP; |
0aa07269 ILT |
6785 | } |
6786 | else if (s[1] == 'a' && s[2] == 't') | |
6787 | { | |
6788 | s += 3; | |
9226253a | 6789 | regno = AT; |
0aa07269 | 6790 | } |
b2b8c24e ILT |
6791 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6792 | { | |
6793 | s += 4; | |
6794 | regno = KT0; | |
6795 | } | |
6796 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6797 | { | |
6798 | s += 4; | |
6799 | regno = KT1; | |
6800 | } | |
efec4a28 DP |
6801 | else if (itbl_have_entries) |
6802 | { | |
6803 | char *p, *n; | |
6804 | int r; | |
6805 | ||
6806 | p = s+1; /* advance past '$' */ | |
9218cee0 | 6807 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
6808 | |
6809 | /* See if this is a register defined in an | |
6810 | itbl entry */ | |
9218cee0 ILT |
6811 | r = itbl_get_reg_val (n); |
6812 | if (r) | |
efec4a28 | 6813 | { |
9218cee0 ILT |
6814 | /* Get_field advances to the start of |
6815 | the next field, so we need to back | |
6816 | rack to the end of the last field. */ | |
efec4a28 | 6817 | if (p) |
9218cee0 | 6818 | s = p - 1; |
efec4a28 | 6819 | else |
9218cee0 | 6820 | s = strchr (s,'\0'); |
efec4a28 DP |
6821 | regno = r; |
6822 | } | |
6823 | else | |
6824 | goto notreg; | |
6825 | } | |
0aa07269 ILT |
6826 | else |
6827 | goto notreg; | |
670a50eb | 6828 | } |
9753202d | 6829 | if (regno == AT |
3c83da8a | 6830 | && ! mips_opts.noat |
9753202d ILT |
6831 | && *args != 'E' |
6832 | && *args != 'G') | |
13fe1379 | 6833 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6834 | c = *args; |
6835 | if (*s == ' ') | |
6836 | s++; | |
6837 | if (args[1] != *s) | |
6838 | { | |
6839 | if (c == 'r' || c == 'v' || c == 'w') | |
6840 | { | |
6841 | regno = lastregno; | |
6842 | s = s_reset; | |
6843 | args++; | |
6844 | } | |
6845 | } | |
ff3a5c18 ILT |
6846 | /* 'z' only matches $0. */ |
6847 | if (c == 'z' && regno != 0) | |
6848 | break; | |
efec4a28 DP |
6849 | |
6850 | /* Now that we have assembled one operand, we use the args string | |
6851 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
6852 | switch (c) |
6853 | { | |
3d3c5039 ILT |
6854 | case 'r': |
6855 | case 's': | |
6856 | case 'v': | |
6857 | case 'b': | |
670a50eb ILT |
6858 | ip->insn_opcode |= regno << 21; |
6859 | break; | |
3d3c5039 | 6860 | case 'd': |
918692a5 | 6861 | case 'G': |
670a50eb ILT |
6862 | ip->insn_opcode |= regno << 11; |
6863 | break; | |
3d3c5039 ILT |
6864 | case 'w': |
6865 | case 't': | |
918692a5 | 6866 | case 'E': |
670a50eb | 6867 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6868 | break; |
6869 | case 'x': | |
6870 | /* This case exists because on the r3000 trunc | |
6871 | expands into a macro which requires a gp | |
6872 | register. On the r6000 or r4000 it is | |
6873 | assembled into a single instruction which | |
6874 | ignores the register. Thus the insn version | |
6875 | is MIPS_ISA2 and uses 'x', and the macro | |
6876 | version is MIPS_ISA1 and uses 't'. */ | |
6877 | break; | |
ff3a5c18 ILT |
6878 | case 'z': |
6879 | /* This case is for the div instruction, which | |
6880 | acts differently if the destination argument | |
6881 | is $0. This only matches $0, and is checked | |
6882 | outside the switch. */ | |
6883 | break; | |
efec4a28 DP |
6884 | case 'D': |
6885 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
6886 | break; | |
9218cee0 ILT |
6887 | /* What about all other operands like 'i', which |
6888 | can be specified in the opcode table? */ | |
3d3c5039 | 6889 | } |
670a50eb ILT |
6890 | lastregno = regno; |
6891 | continue; | |
3d3c5039 ILT |
6892 | } |
6893 | notreg: | |
670a50eb ILT |
6894 | switch (*args++) |
6895 | { | |
3d3c5039 ILT |
6896 | case 'r': |
6897 | case 'v': | |
670a50eb ILT |
6898 | ip->insn_opcode |= lastregno << 21; |
6899 | continue; | |
3d3c5039 | 6900 | case 'w': |
670a50eb ILT |
6901 | ip->insn_opcode |= lastregno << 16; |
6902 | continue; | |
3d3c5039 | 6903 | } |
670a50eb | 6904 | break; |
3d3c5039 | 6905 | |
670a50eb ILT |
6906 | case 'D': /* floating point destination register */ |
6907 | case 'S': /* floating point source register */ | |
6908 | case 'T': /* floating point target register */ | |
d8a1c247 | 6909 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6910 | case 'V': |
6911 | case 'W': | |
670a50eb ILT |
6912 | s_reset = s; |
6913 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6914 | { | |
6915 | s += 2; | |
6916 | regno = 0; | |
6917 | do | |
6918 | { | |
6919 | regno *= 10; | |
6920 | regno += *s - '0'; | |
6921 | ++s; | |
6922 | } | |
6923 | while (isdigit (*s)); | |
6924 | ||
6925 | if (regno > 31) | |
6926 | as_bad ("Invalid float register number (%d)", regno); | |
6927 | ||
9226253a | 6928 | if ((regno & 1) != 0 |
3c83da8a | 6929 | && mips_opts.isa < 3 |
538034cf ILT |
6930 | && ! (strcmp (str, "mtc1") == 0 |
6931 | || strcmp (str, "mfc1") == 0 | |
6932 | || strcmp (str, "lwc1") == 0 | |
6933 | || strcmp (str, "swc1") == 0 | |
6934 | || strcmp (str, "l.s") == 0 | |
6935 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6936 | as_warn ("Float register should be even, was %d", |
6937 | regno); | |
6938 | ||
6939 | c = *args; | |
6940 | if (*s == ' ') | |
6941 | s++; | |
6942 | if (args[1] != *s) | |
6943 | { | |
6944 | if (c == 'V' || c == 'W') | |
6945 | { | |
6946 | regno = lastregno; | |
6947 | s = s_reset; | |
6948 | args++; | |
3d3c5039 ILT |
6949 | } |
6950 | } | |
670a50eb ILT |
6951 | switch (c) |
6952 | { | |
3d3c5039 | 6953 | case 'D': |
670a50eb ILT |
6954 | ip->insn_opcode |= regno << 6; |
6955 | break; | |
3d3c5039 ILT |
6956 | case 'V': |
6957 | case 'S': | |
670a50eb ILT |
6958 | ip->insn_opcode |= regno << 11; |
6959 | break; | |
3d3c5039 ILT |
6960 | case 'W': |
6961 | case 'T': | |
670a50eb | 6962 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6963 | break; |
6964 | case 'R': | |
6965 | ip->insn_opcode |= regno << 21; | |
6966 | break; | |
3d3c5039 | 6967 | } |
670a50eb ILT |
6968 | lastregno = regno; |
6969 | continue; | |
3d3c5039 | 6970 | } |
670a50eb ILT |
6971 | switch (*args++) |
6972 | { | |
3d3c5039 | 6973 | case 'V': |
670a50eb ILT |
6974 | ip->insn_opcode |= lastregno << 11; |
6975 | continue; | |
3d3c5039 | 6976 | case 'W': |
670a50eb ILT |
6977 | ip->insn_opcode |= lastregno << 16; |
6978 | continue; | |
3d3c5039 | 6979 | } |
670a50eb | 6980 | break; |
3d3c5039 ILT |
6981 | |
6982 | case 'I': | |
670a50eb | 6983 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6984 | if (imm_expr.X_op != O_big |
6985 | && imm_expr.X_op != O_constant) | |
6986 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6987 | s = expr_end; |
6988 | continue; | |
3d3c5039 ILT |
6989 | |
6990 | case 'A': | |
670a50eb ILT |
6991 | my_getExpression (&offset_expr, s); |
6992 | imm_reloc = BFD_RELOC_32; | |
6993 | s = expr_end; | |
6994 | continue; | |
3d3c5039 ILT |
6995 | |
6996 | case 'F': | |
19ed8960 ILT |
6997 | case 'L': |
6998 | case 'f': | |
6999 | case 'l': | |
7000 | { | |
7001 | int f64; | |
7002 | char *save_in; | |
7003 | char *err; | |
7004 | unsigned char temp[8]; | |
604633ae ILT |
7005 | int len; |
7006 | unsigned int length; | |
19ed8960 ILT |
7007 | segT seg; |
7008 | subsegT subseg; | |
7009 | char *p; | |
7010 | ||
7011 | /* These only appear as the last operand in an | |
7012 | instruction, and every instruction that accepts | |
7013 | them in any variant accepts them in all variants. | |
7014 | This means we don't have to worry about backing out | |
7015 | any changes if the instruction does not match. | |
7016 | ||
7017 | The difference between them is the size of the | |
7018 | floating point constant and where it goes. For 'F' | |
7019 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7020 | is 32 bits. Where the constant is placed is based | |
7021 | on how the MIPS assembler does things: | |
7022 | F -- .rdata | |
7023 | L -- .lit8 | |
7024 | f -- immediate value | |
7025 | l -- .lit4 | |
0dd2d296 | 7026 | |
55933a58 ILT |
7027 | The .lit4 and .lit8 sections are only used if |
7028 | permitted by the -G argument. | |
7029 | ||
7030 | When generating embedded PIC code, we use the | |
7031 | .lit8 section but not the .lit4 section (we can do | |
7032 | .lit4 inline easily; we need to put .lit8 | |
7033 | somewhere in the data segment, and using .lit8 | |
7034 | permits the linker to eventually combine identical | |
7035 | .lit8 entries). */ | |
19ed8960 ILT |
7036 | |
7037 | f64 = *args == 'F' || *args == 'L'; | |
7038 | ||
7039 | save_in = input_line_pointer; | |
7040 | input_line_pointer = s; | |
604633ae ILT |
7041 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
7042 | length = len; | |
19ed8960 ILT |
7043 | s = input_line_pointer; |
7044 | input_line_pointer = save_in; | |
7045 | if (err != NULL && *err != '\0') | |
7046 | { | |
7047 | as_bad ("Bad floating point constant: %s", err); | |
7048 | memset (temp, '\0', sizeof temp); | |
7049 | length = f64 ? 8 : 4; | |
7050 | } | |
7051 | ||
7052 | assert (length == (f64 ? 8 : 4)); | |
7053 | ||
0dd2d296 | 7054 | if (*args == 'f' |
55933a58 | 7055 | || (*args == 'l' |
1dc1e798 KR |
7056 | && (! USE_GLOBAL_POINTER_OPT |
7057 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
7058 | || g_switch_value < 4 |
7059 | || (temp[0] == 0 && temp[1] == 0) | |
7060 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
7061 | { |
7062 | imm_expr.X_op = O_constant; | |
b9129c6f | 7063 | if (! target_big_endian) |
a5586bdc | 7064 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 7065 | else |
a5586bdc ILT |
7066 | imm_expr.X_add_number = bfd_getb32 (temp); |
7067 | } | |
7068 | else if (length > 4 | |
7069 | && ((temp[0] == 0 && temp[1] == 0) | |
7070 | || (temp[2] == 0 && temp[3] == 0)) | |
7071 | && ((temp[4] == 0 && temp[5] == 0) | |
7072 | || (temp[6] == 0 && temp[7] == 0))) | |
7073 | { | |
7074 | /* The value is simple enough to load with a | |
7075 | couple of instructions. In mips1 mode, set | |
7076 | imm_expr to the high order 32 bits and | |
7077 | offset_expr to the low order 32 bits. | |
7078 | Otherwise, set imm_expr to the entire 64 bit | |
7079 | constant. */ | |
7080 | if (mips_opts.isa < 3) | |
7081 | { | |
7082 | imm_expr.X_op = O_constant; | |
7083 | offset_expr.X_op = O_constant; | |
7084 | if (! target_big_endian) | |
7085 | { | |
7086 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7087 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7088 | } | |
7089 | else | |
7090 | { | |
7091 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7092 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7093 | } | |
7094 | if (offset_expr.X_add_number == 0) | |
7095 | offset_expr.X_op = O_absent; | |
7096 | } | |
7097 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7098 | { | |
7099 | imm_expr.X_op = O_constant; | |
7100 | if (! target_big_endian) | |
7101 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7102 | else | |
7103 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7104 | } | |
7105 | else | |
7106 | { | |
7107 | imm_expr.X_op = O_big; | |
7108 | imm_expr.X_add_number = 4; | |
7109 | if (! target_big_endian) | |
7110 | { | |
7111 | generic_bignum[0] = bfd_getl16 (temp); | |
7112 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7113 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7114 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7115 | } | |
7116 | else | |
7117 | { | |
7118 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7119 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7120 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7121 | generic_bignum[3] = bfd_getb16 (temp); | |
7122 | } | |
7123 | } | |
19ed8960 ILT |
7124 | } |
7125 | else | |
7126 | { | |
0dd2d296 ILT |
7127 | const char *newname; |
7128 | segT new_seg; | |
7129 | ||
19ed8960 ILT |
7130 | /* Switch to the right section. */ |
7131 | seg = now_seg; | |
7132 | subseg = now_subseg; | |
7133 | switch (*args) | |
7134 | { | |
0dd2d296 | 7135 | default: /* unused default case avoids warnings. */ |
19ed8960 | 7136 | case 'L': |
1113140a | 7137 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 7138 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 7139 | newname = ".lit8"; |
0dd2d296 ILT |
7140 | break; |
7141 | case 'F': | |
d2c71068 | 7142 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
7143 | break; |
7144 | case 'l': | |
1dc1e798 KR |
7145 | assert (!USE_GLOBAL_POINTER_OPT |
7146 | || g_switch_value >= 4); | |
0dd2d296 | 7147 | newname = ".lit4"; |
19ed8960 ILT |
7148 | break; |
7149 | } | |
0dd2d296 | 7150 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
7151 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
7152 | bfd_set_section_flags (stdoutput, new_seg, | |
7153 | (SEC_ALLOC | |
7154 | | SEC_LOAD | |
7155 | | SEC_READONLY | |
7156 | | SEC_DATA)); | |
e2e5acfa JW |
7157 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
7158 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7159 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
7160 | record_alignment (new_seg, 4); |
7161 | else | |
7162 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
7163 | if (seg == now_seg) |
7164 | as_bad ("Can't use floating point insn in this section"); | |
7165 | ||
7166 | /* Set the argument to the current address in the | |
6e8dda9c | 7167 | section. */ |
19ed8960 ILT |
7168 | offset_expr.X_op = O_symbol; |
7169 | offset_expr.X_add_symbol = | |
7170 | symbol_new ("L0\001", now_seg, | |
7171 | (valueT) frag_now_fix (), frag_now); | |
7172 | offset_expr.X_add_number = 0; | |
7173 | ||
7174 | /* Put the floating point number into the section. */ | |
604633ae | 7175 | p = frag_more ((int) length); |
19ed8960 ILT |
7176 | memcpy (p, temp, length); |
7177 | ||
7178 | /* Switch back to the original section. */ | |
7179 | subseg_set (seg, subseg); | |
7180 | } | |
7181 | } | |
670a50eb ILT |
7182 | continue; |
7183 | ||
7184 | case 'i': /* 16 bit unsigned immediate */ | |
7185 | case 'j': /* 16 bit signed immediate */ | |
7186 | imm_reloc = BFD_RELOC_LO16; | |
7187 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 7188 | if (c != '\0') |
670a50eb ILT |
7189 | { |
7190 | if (c != 'l') | |
7191 | { | |
5ac34ac3 | 7192 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
7193 | imm_expr.X_add_number = |
7194 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7195 | else if (c == 'h') | |
867a58b3 ILT |
7196 | { |
7197 | imm_reloc = BFD_RELOC_HI16_S; | |
7198 | imm_unmatched_hi = true; | |
7199 | } | |
670a50eb ILT |
7200 | else |
7201 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 7202 | } |
670a50eb | 7203 | } |
670a50eb ILT |
7204 | if (*args == 'i') |
7205 | { | |
344a8d61 | 7206 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7207 | || ((imm_expr.X_add_number < 0 |
7208 | || imm_expr.X_add_number >= 0x10000) | |
7209 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
7210 | { |
7211 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7212 | !strcmp (insn->name, insn[1].name)) | |
7213 | break; | |
9753202d ILT |
7214 | if (imm_expr.X_op != O_constant |
7215 | && imm_expr.X_op != O_big) | |
7216 | insn_error = "absolute expression required"; | |
7217 | else | |
7218 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 7219 | } |
670a50eb ILT |
7220 | } |
7221 | else | |
7222 | { | |
d9aba805 ILT |
7223 | int more; |
7224 | offsetT max; | |
7225 | ||
be22008b ILT |
7226 | /* The upper bound should be 0x8000, but |
7227 | unfortunately the MIPS assembler accepts numbers | |
7228 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
7229 | we want to be compatible. We only permit this |
7230 | extended range for an instruction which does not | |
7231 | provide any further alternates, since those | |
7232 | alternates may handle other cases. People should | |
7233 | use the numbers they mean, rather than relying on | |
7234 | a mysterious sign extension. */ | |
7235 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7236 | strcmp (insn->name, insn[1].name) == 0); | |
7237 | if (more) | |
7238 | max = 0x8000; | |
7239 | else | |
7240 | max = 0x10000; | |
344a8d61 | 7241 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7242 | || ((imm_expr.X_add_number < -0x8000 |
7243 | || imm_expr.X_add_number >= max) | |
7244 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
7245 | || (more |
7246 | && imm_expr.X_add_number < 0 | |
3c83da8a | 7247 | && mips_opts.isa >= 3 |
d8a1c247 KR |
7248 | && imm_expr.X_unsigned |
7249 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 7250 | { |
d9aba805 | 7251 | if (more) |
99c24539 | 7252 | break; |
9753202d ILT |
7253 | if (imm_expr.X_op != O_constant |
7254 | && imm_expr.X_op != O_big) | |
7255 | insn_error = "absolute expression required"; | |
7256 | else | |
7257 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 7258 | } |
3d3c5039 | 7259 | } |
670a50eb ILT |
7260 | s = expr_end; |
7261 | continue; | |
7262 | ||
7263 | case 'o': /* 16 bit offset */ | |
7264 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
7265 | |
7266 | /* If this value won't fit into a 16 bit offset, then go | |
7267 | find a macro that will generate the 32 bit offset | |
7268 | code pattern. As a special hack, we accept the | |
7269 | difference of two local symbols as a constant. This | |
7270 | is required to suppose embedded PIC switches, which | |
7271 | use an instruction which looks like | |
7272 | lw $4,$L12-$LS12($4) | |
7273 | The problem with handling this in a more general | |
7274 | fashion is that the macro function doesn't expect to | |
7275 | see anything which can be handled in a single | |
7276 | constant instruction. */ | |
6f0b87c3 SS |
7277 | if (c == 0 |
7278 | && (offset_expr.X_op != O_constant | |
7279 | || offset_expr.X_add_number >= 0x8000 | |
7280 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
7281 | && (mips_pic != EMBEDDED_PIC |
7282 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
7283 | || now_seg != text_section |
7284 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7285 | != text_section))) | |
670a50eb | 7286 | break; |
3d3c5039 | 7287 | |
670a50eb ILT |
7288 | offset_reloc = BFD_RELOC_LO16; |
7289 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
7290 | { |
7291 | assert (offset_expr.X_op == O_constant); | |
7292 | offset_expr.X_add_number = | |
7293 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7294 | } | |
cc5703cd ILT |
7295 | s = expr_end; |
7296 | continue; | |
7297 | ||
7298 | case 'p': /* pc relative offset */ | |
7299 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7300 | my_getExpression (&offset_expr, s); | |
7301 | s = expr_end; | |
7302 | continue; | |
7303 | ||
7304 | case 'u': /* upper 16 bits */ | |
7305 | c = my_getSmallExpression (&imm_expr, s); | |
7306 | if (imm_expr.X_op == O_constant | |
7307 | && (imm_expr.X_add_number < 0 | |
7308 | || imm_expr.X_add_number >= 0x10000)) | |
7309 | as_bad ("lui expression not in range 0..65535"); | |
7310 | imm_reloc = BFD_RELOC_LO16; | |
7311 | if (c) | |
7312 | { | |
7313 | if (c != 'l') | |
7314 | { | |
7315 | if (imm_expr.X_op == O_constant) | |
7316 | imm_expr.X_add_number = | |
7317 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7318 | else if (c == 'h') | |
7319 | { | |
7320 | imm_reloc = BFD_RELOC_HI16_S; | |
7321 | imm_unmatched_hi = true; | |
7322 | } | |
7323 | else | |
7324 | imm_reloc = BFD_RELOC_HI16; | |
7325 | } | |
7326 | } | |
7327 | s = expr_end; | |
7328 | continue; | |
7329 | ||
7330 | case 'a': /* 26 bit address */ | |
7331 | my_getExpression (&offset_expr, s); | |
7332 | s = expr_end; | |
7333 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7334 | continue; | |
7335 | ||
7336 | case 'N': /* 3 bit branch condition code */ | |
7337 | case 'M': /* 3 bit compare condition code */ | |
7338 | if (strncmp (s, "$fcc", 4) != 0) | |
7339 | break; | |
7340 | s += 4; | |
7341 | regno = 0; | |
7342 | do | |
7343 | { | |
7344 | regno *= 10; | |
7345 | regno += *s - '0'; | |
7346 | ++s; | |
7347 | } | |
7348 | while (isdigit (*s)); | |
7349 | if (regno > 7) | |
7350 | as_bad ("invalid condition code register $fcc%d", regno); | |
7351 | if (*args == 'N') | |
7352 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7353 | else | |
7354 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7355 | continue; | |
7356 | ||
7357 | default: | |
7358 | fprintf (stderr, "bad char = '%c'\n", *args); | |
7359 | internalError (); | |
7360 | } | |
7361 | break; | |
7362 | } | |
7363 | /* Args don't match. */ | |
7364 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7365 | !strcmp (insn->name, insn[1].name)) | |
7366 | { | |
7367 | ++insn; | |
7368 | s = argsStart; | |
7369 | continue; | |
7370 | } | |
7371 | insn_error = "illegal operands"; | |
7372 | return; | |
7373 | } | |
7374 | } | |
7375 | ||
7376 | /* This routine assembles an instruction into its binary format when | |
7377 | assembling for the mips16. As a side effect, it sets one of the | |
7378 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
7379 | relocation to do if one of the operands is an address expression. |
7380 | It also sets mips16_small and mips16_ext if the user explicitly | |
7381 | requested a small or extended instruction. */ | |
cc5703cd ILT |
7382 | |
7383 | static void | |
7384 | mips16_ip (str, ip) | |
7385 | char *str; | |
7386 | struct mips_cl_insn *ip; | |
7387 | { | |
7388 | char *s; | |
cc5703cd ILT |
7389 | const char *args; |
7390 | struct mips_opcode *insn; | |
7391 | char *argsstart; | |
7392 | unsigned int regno; | |
7393 | unsigned int lastregno = 0; | |
7394 | char *s_reset; | |
7395 | ||
7396 | insn_error = NULL; | |
7397 | ||
8728fa92 ILT |
7398 | mips16_small = false; |
7399 | mips16_ext = false; | |
cc5703cd ILT |
7400 | |
7401 | for (s = str; islower (*s); ++s) | |
7402 | ; | |
7403 | switch (*s) | |
7404 | { | |
7405 | case '\0': | |
7406 | break; | |
7407 | ||
7408 | case ' ': | |
7409 | *s++ = '\0'; | |
7410 | break; | |
7411 | ||
7412 | case '.': | |
7413 | if (s[1] == 't' && s[2] == ' ') | |
7414 | { | |
7415 | *s = '\0'; | |
8728fa92 | 7416 | mips16_small = true; |
cc5703cd ILT |
7417 | s += 3; |
7418 | break; | |
7419 | } | |
7420 | else if (s[1] == 'e' && s[2] == ' ') | |
7421 | { | |
7422 | *s = '\0'; | |
8728fa92 | 7423 | mips16_ext = true; |
cc5703cd ILT |
7424 | s += 3; |
7425 | break; | |
7426 | } | |
7427 | /* Fall through. */ | |
7428 | default: | |
7429 | insn_error = "unknown opcode"; | |
7430 | return; | |
7431 | } | |
7432 | ||
3c83da8a | 7433 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
7434 | mips16_small = true; |
7435 | ||
cc5703cd ILT |
7436 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
7437 | { | |
7438 | insn_error = "unrecognized opcode"; | |
7439 | return; | |
7440 | } | |
7441 | ||
7442 | argsstart = s; | |
7443 | for (;;) | |
7444 | { | |
7445 | assert (strcmp (insn->name, str) == 0); | |
7446 | ||
7447 | ip->insn_mo = insn; | |
7448 | ip->insn_opcode = insn->match; | |
7449 | ip->use_extend = false; | |
7450 | imm_expr.X_op = O_absent; | |
7451 | imm_reloc = BFD_RELOC_UNUSED; | |
7452 | offset_expr.X_op = O_absent; | |
7453 | offset_reloc = BFD_RELOC_UNUSED; | |
7454 | for (args = insn->args; 1; ++args) | |
7455 | { | |
7456 | int c; | |
7457 | ||
7458 | if (*s == ' ') | |
7459 | ++s; | |
7460 | ||
7461 | /* In this switch statement we call break if we did not find | |
7462 | a match, continue if we did find a match, or return if we | |
7463 | are done. */ | |
7464 | ||
7465 | c = *args; | |
7466 | switch (c) | |
7467 | { | |
7468 | case '\0': | |
7469 | if (*s == '\0') | |
7470 | { | |
7471 | /* Stuff the immediate value in now, if we can. */ | |
7472 | if (imm_expr.X_op == O_constant | |
7473 | && imm_reloc > BFD_RELOC_UNUSED | |
7474 | && insn->pinfo != INSN_MACRO) | |
7475 | { | |
15e69f98 ILT |
7476 | mips16_immed ((char *) NULL, 0, |
7477 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
7478 | imm_expr.X_add_number, true, mips16_small, |
7479 | mips16_ext, &ip->insn_opcode, | |
7480 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7481 | imm_expr.X_op = O_absent; |
7482 | imm_reloc = BFD_RELOC_UNUSED; | |
7483 | } | |
7484 | ||
7485 | return; | |
7486 | } | |
7487 | break; | |
7488 | ||
7489 | case ',': | |
7490 | if (*s++ == c) | |
7491 | continue; | |
7492 | s--; | |
7493 | switch (*++args) | |
7494 | { | |
7495 | case 'v': | |
7496 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7497 | continue; | |
7498 | case 'w': | |
7499 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7500 | continue; | |
7501 | } | |
7502 | break; | |
7503 | ||
7504 | case '(': | |
7505 | case ')': | |
7506 | if (*s++ == c) | |
7507 | continue; | |
7508 | break; | |
7509 | ||
7510 | case 'v': | |
7511 | case 'w': | |
7512 | if (s[0] != '$') | |
7513 | { | |
7514 | if (c == 'v') | |
7515 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7516 | else | |
7517 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7518 | ++args; | |
7519 | continue; | |
7520 | } | |
7521 | /* Fall through. */ | |
7522 | case 'x': | |
7523 | case 'y': | |
7524 | case 'z': | |
7525 | case 'Z': | |
7526 | case '0': | |
7527 | case 'S': | |
7528 | case 'R': | |
7529 | case 'X': | |
7530 | case 'Y': | |
7531 | if (s[0] != '$') | |
7532 | break; | |
7533 | s_reset = s; | |
7534 | if (isdigit (s[1])) | |
7535 | { | |
7536 | ++s; | |
7537 | regno = 0; | |
7538 | do | |
7539 | { | |
7540 | regno *= 10; | |
7541 | regno += *s - '0'; | |
7542 | ++s; | |
7543 | } | |
7544 | while (isdigit (*s)); | |
7545 | if (regno > 31) | |
7546 | { | |
7547 | as_bad ("invalid register number (%d)", regno); | |
7548 | regno = 2; | |
7549 | } | |
7550 | } | |
7551 | else | |
7552 | { | |
7553 | if (s[1] == 'f' && s[2] == 'p') | |
7554 | { | |
7555 | s += 3; | |
7556 | regno = FP; | |
7557 | } | |
7558 | else if (s[1] == 's' && s[2] == 'p') | |
7559 | { | |
7560 | s += 3; | |
7561 | regno = SP; | |
7562 | } | |
7563 | else if (s[1] == 'g' && s[2] == 'p') | |
7564 | { | |
7565 | s += 3; | |
7566 | regno = GP; | |
7567 | } | |
7568 | else if (s[1] == 'a' && s[2] == 't') | |
7569 | { | |
7570 | s += 3; | |
7571 | regno = AT; | |
7572 | } | |
7573 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7574 | { | |
7575 | s += 4; | |
7576 | regno = KT0; | |
7577 | } | |
7578 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7579 | { | |
7580 | s += 4; | |
7581 | regno = KT1; | |
7582 | } | |
7583 | else | |
7584 | break; | |
7585 | } | |
7586 | ||
7587 | if (*s == ' ') | |
7588 | ++s; | |
7589 | if (args[1] != *s) | |
7590 | { | |
7591 | if (c == 'v' || c == 'w') | |
7592 | { | |
7593 | regno = mips16_to_32_reg_map[lastregno]; | |
7594 | s = s_reset; | |
7595 | args++; | |
7596 | } | |
7597 | } | |
7598 | ||
7599 | switch (c) | |
7600 | { | |
7601 | case 'x': | |
7602 | case 'y': | |
7603 | case 'z': | |
7604 | case 'v': | |
7605 | case 'w': | |
7606 | case 'Z': | |
7607 | regno = mips32_to_16_reg_map[regno]; | |
7608 | break; | |
7609 | ||
7610 | case '0': | |
7611 | if (regno != 0) | |
7612 | regno = ILLEGAL_REG; | |
7613 | break; | |
7614 | ||
7615 | case 'S': | |
7616 | if (regno != SP) | |
7617 | regno = ILLEGAL_REG; | |
7618 | break; | |
7619 | ||
7620 | case 'R': | |
7621 | if (regno != RA) | |
7622 | regno = ILLEGAL_REG; | |
7623 | break; | |
7624 | ||
7625 | case 'X': | |
7626 | case 'Y': | |
3c83da8a | 7627 | if (regno == AT && ! mips_opts.noat) |
cc5703cd ILT |
7628 | as_warn ("used $at without \".set noat\""); |
7629 | break; | |
7630 | ||
7631 | default: | |
7632 | internalError (); | |
7633 | } | |
7634 | ||
7635 | if (regno == ILLEGAL_REG) | |
7636 | break; | |
7637 | ||
7638 | switch (c) | |
7639 | { | |
7640 | case 'x': | |
7641 | case 'v': | |
7642 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7643 | break; | |
7644 | case 'y': | |
7645 | case 'w': | |
7646 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7647 | break; | |
7648 | case 'z': | |
7649 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7650 | break; | |
7651 | case 'Z': | |
7652 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7653 | case '0': | |
7654 | case 'S': | |
7655 | case 'R': | |
7656 | break; | |
7657 | case 'X': | |
7658 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7659 | break; | |
7660 | case 'Y': | |
7661 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7662 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7663 | break; | |
7664 | default: | |
7665 | internalError (); | |
7666 | } | |
7667 | ||
7668 | lastregno = regno; | |
7669 | continue; | |
7670 | ||
7671 | case 'P': | |
7672 | if (strncmp (s, "$pc", 3) == 0) | |
7673 | { | |
7674 | s += 3; | |
7675 | continue; | |
7676 | } | |
7677 | break; | |
7678 | ||
7679 | case '<': | |
7680 | case '>': | |
7681 | case '[': | |
7682 | case ']': | |
7683 | case '4': | |
7684 | case '5': | |
7685 | case 'H': | |
7686 | case 'W': | |
7687 | case 'D': | |
7688 | case 'j': | |
7689 | case '8': | |
7690 | case 'V': | |
7691 | case 'C': | |
7692 | case 'U': | |
7693 | case 'k': | |
7694 | case 'K': | |
16262668 ILT |
7695 | if (s[0] == '%' |
7696 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
7697 | { | |
7698 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
7699 | and generate the appropriate reloc. If the text | |
7700 | inside %gprel is not a symbol name with an | |
7701 | optional offset, then we generate a normal reloc | |
7702 | and will probably fail later. */ | |
7703 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
7704 | if (imm_expr.X_op == O_symbol) | |
7705 | { | |
7706 | mips16_ext = true; | |
7707 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
7708 | s = expr_end; | |
7709 | ip->use_extend = true; | |
7710 | ip->extend = 0; | |
7711 | continue; | |
7712 | } | |
7713 | } | |
7714 | else | |
7715 | { | |
7716 | /* Just pick up a normal expression. */ | |
7717 | my_getExpression (&imm_expr, s); | |
7718 | } | |
7719 | ||
ebf28372 ILT |
7720 | if (imm_expr.X_op == O_register) |
7721 | { | |
7722 | /* What we thought was an expression turned out to | |
7723 | be a register. */ | |
7724 | ||
7725 | if (s[0] == '(' && args[1] == '(') | |
7726 | { | |
7727 | /* It looks like the expression was omitted | |
7728 | before a register indirection, which means | |
7729 | that the expression is implicitly zero. We | |
7730 | still set up imm_expr, so that we handle | |
7731 | explicit extensions correctly. */ | |
7732 | imm_expr.X_op = O_constant; | |
7733 | imm_expr.X_add_number = 0; | |
7734 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7735 | continue; | |
7736 | } | |
7737 | ||
7738 | break; | |
7739 | } | |
7740 | ||
cc5703cd ILT |
7741 | /* We need to relax this instruction. */ |
7742 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7743 | s = expr_end; | |
7744 | continue; | |
7745 | ||
7746 | case 'p': | |
7747 | case 'q': | |
7748 | case 'A': | |
7749 | case 'B': | |
7750 | case 'E': | |
7751 | /* We use offset_reloc rather than imm_reloc for the PC | |
7752 | relative operands. This lets macros with both | |
7753 | immediate and address operands work correctly. */ | |
670a50eb | 7754 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
7755 | |
7756 | if (offset_expr.X_op == O_register) | |
7757 | break; | |
7758 | ||
cc5703cd ILT |
7759 | /* We need to relax this instruction. */ |
7760 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7761 | s = expr_end; |
7762 | continue; | |
7763 | ||
cc5703cd ILT |
7764 | case '6': /* break code */ |
7765 | my_getExpression (&imm_expr, s); | |
7766 | check_absolute_expr (ip, &imm_expr); | |
7767 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7768 | { |
cc5703cd ILT |
7769 | as_warn ("Invalid value for `%s' (%lu)", |
7770 | ip->insn_mo->name, | |
7771 | (unsigned long) imm_expr.X_add_number); | |
7772 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7773 | } |
cc5703cd ILT |
7774 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7775 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7776 | s = expr_end; |
7777 | continue; | |
3d3c5039 | 7778 | |
670a50eb ILT |
7779 | case 'a': /* 26 bit address */ |
7780 | my_getExpression (&offset_expr, s); | |
7781 | s = expr_end; | |
cc5703cd ILT |
7782 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7783 | ip->insn_opcode <<= 16; | |
670a50eb | 7784 | continue; |
3d3c5039 | 7785 | |
cc5703cd ILT |
7786 | case 'l': /* register list for entry macro */ |
7787 | case 'L': /* register list for exit macro */ | |
7788 | { | |
7789 | int mask; | |
7790 | ||
7791 | if (c == 'l') | |
7792 | mask = 0; | |
7793 | else | |
7794 | mask = 7 << 3; | |
7795 | while (*s != '\0') | |
7796 | { | |
c9167640 | 7797 | int freg, reg1, reg2; |
cc5703cd ILT |
7798 | |
7799 | while (*s == ' ' || *s == ',') | |
7800 | ++s; | |
7801 | if (*s != '$') | |
7802 | { | |
7803 | as_bad ("can't parse register list"); | |
7804 | break; | |
7805 | } | |
7806 | ++s; | |
c9167640 ILT |
7807 | if (*s != 'f') |
7808 | freg = 0; | |
7809 | else | |
7810 | { | |
7811 | freg = 1; | |
7812 | ++s; | |
7813 | } | |
cc5703cd ILT |
7814 | reg1 = 0; |
7815 | while (isdigit (*s)) | |
7816 | { | |
7817 | reg1 *= 10; | |
7818 | reg1 += *s - '0'; | |
7819 | ++s; | |
7820 | } | |
7821 | if (*s == ' ') | |
7822 | ++s; | |
7823 | if (*s != '-') | |
7824 | reg2 = reg1; | |
7825 | else | |
7826 | { | |
7827 | ++s; | |
7828 | if (*s != '$') | |
7829 | break; | |
7830 | ++s; | |
c9167640 ILT |
7831 | if (freg) |
7832 | { | |
7833 | if (*s == 'f') | |
7834 | ++s; | |
7835 | else | |
7836 | { | |
7837 | as_bad ("invalid register list"); | |
7838 | break; | |
7839 | } | |
7840 | } | |
cc5703cd ILT |
7841 | reg2 = 0; |
7842 | while (isdigit (*s)) | |
7843 | { | |
7844 | reg2 *= 10; | |
7845 | reg2 += *s - '0'; | |
7846 | ++s; | |
7847 | } | |
7848 | } | |
c9167640 ILT |
7849 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
7850 | { | |
7851 | mask &= ~ (7 << 3); | |
7852 | mask |= 5 << 3; | |
7853 | } | |
7854 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
7855 | { | |
7856 | mask &= ~ (7 << 3); | |
7857 | mask |= 6 << 3; | |
7858 | } | |
7859 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
7860 | mask |= (reg2 - 3) << 3; |
7861 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7862 | mask |= (reg2 - 15) << 1; | |
7863 | else if (reg1 == 31 && reg2 == 31) | |
7864 | mask |= 1; | |
7865 | else | |
c9167640 ILT |
7866 | { |
7867 | as_bad ("invalid register list"); | |
7868 | break; | |
7869 | } | |
cc5703cd | 7870 | } |
c9167640 ILT |
7871 | /* The mask is filled in in the opcode table for the |
7872 | benefit of the disassembler. We remove it before | |
7873 | applying the actual mask. */ | |
7874 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
7875 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
7876 | } | |
7877 | continue; | |
d8a1c247 | 7878 | |
56bb6eee ILT |
7879 | case 'e': /* extend code */ |
7880 | my_getExpression (&imm_expr, s); | |
7881 | check_absolute_expr (ip, &imm_expr); | |
7882 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
7883 | { | |
7884 | as_warn ("Invalid value for `%s' (%lu)", | |
7885 | ip->insn_mo->name, | |
7886 | (unsigned long) imm_expr.X_add_number); | |
7887 | imm_expr.X_add_number &= 0x7ff; | |
7888 | } | |
7889 | ip->insn_opcode |= imm_expr.X_add_number; | |
7890 | imm_expr.X_op = O_absent; | |
7891 | s = expr_end; | |
7892 | continue; | |
7893 | ||
3d3c5039 | 7894 | default: |
670a50eb | 7895 | internalError (); |
3d3c5039 | 7896 | } |
670a50eb | 7897 | break; |
3d3c5039 | 7898 | } |
cc5703cd | 7899 | |
670a50eb | 7900 | /* Args don't match. */ |
cc5703cd ILT |
7901 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7902 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7903 | { |
7904 | ++insn; | |
cc5703cd | 7905 | s = argsstart; |
670a50eb | 7906 | continue; |
3d3c5039 | 7907 | } |
cc5703cd | 7908 | |
9753202d | 7909 | insn_error = "illegal operands"; |
cc5703cd | 7910 | |
670a50eb | 7911 | return; |
3d3c5039 ILT |
7912 | } |
7913 | } | |
7914 | ||
cc5703cd ILT |
7915 | /* This structure holds information we know about a mips16 immediate |
7916 | argument type. */ | |
7917 | ||
7918 | struct mips16_immed_operand | |
7919 | { | |
7920 | /* The type code used in the argument string in the opcode table. */ | |
7921 | int type; | |
7922 | /* The number of bits in the short form of the opcode. */ | |
7923 | int nbits; | |
7924 | /* The number of bits in the extended form of the opcode. */ | |
7925 | int extbits; | |
7926 | /* The amount by which the short form is shifted when it is used; | |
7927 | for example, the sw instruction has a shift count of 2. */ | |
7928 | int shift; | |
7929 | /* The amount by which the short form is shifted when it is stored | |
7930 | into the instruction code. */ | |
7931 | int op_shift; | |
7932 | /* Non-zero if the short form is unsigned. */ | |
7933 | int unsp; | |
7934 | /* Non-zero if the extended form is unsigned. */ | |
7935 | int extu; | |
7936 | /* Non-zero if the value is PC relative. */ | |
7937 | int pcrel; | |
7938 | }; | |
7939 | ||
7940 | /* The mips16 immediate operand types. */ | |
7941 | ||
7942 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7943 | { | |
7944 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7945 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7946 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7947 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7948 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7949 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7950 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7951 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7952 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7953 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7954 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7955 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7956 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7957 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7958 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7959 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7960 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7961 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7962 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7963 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7964 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7965 | }; | |
7966 | ||
7967 | #define MIPS16_NUM_IMMED \ | |
7968 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7969 | ||
7970 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7971 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7972 | whether an extended value is needed; if one is needed, it sets | |
7973 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7974 | If SMALL is true, an unextended opcode was explicitly requested. | |
7975 | If EXT is true, an extended opcode was explicitly requested. If | |
7976 | WARN is true, warn if EXT does not match reality. */ | |
7977 | ||
7978 | static void | |
15e69f98 ILT |
7979 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7980 | extend) | |
7981 | char *file; | |
7982 | unsigned int line; | |
cc5703cd ILT |
7983 | int type; |
7984 | offsetT val; | |
7985 | boolean warn; | |
7986 | boolean small; | |
7987 | boolean ext; | |
7988 | unsigned long *insn; | |
7989 | boolean *use_extend; | |
7990 | unsigned short *extend; | |
7991 | { | |
7992 | register const struct mips16_immed_operand *op; | |
7993 | int mintiny, maxtiny; | |
7994 | boolean needext; | |
7995 | ||
7996 | op = mips16_immed_operands; | |
7997 | while (op->type != type) | |
7998 | { | |
7999 | ++op; | |
8000 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8001 | } | |
8002 | ||
8003 | if (op->unsp) | |
8004 | { | |
8005 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8006 | { | |
8007 | mintiny = 1; | |
8008 | maxtiny = 1 << op->nbits; | |
8009 | } | |
8010 | else | |
8011 | { | |
8012 | mintiny = 0; | |
8013 | maxtiny = (1 << op->nbits) - 1; | |
8014 | } | |
8015 | } | |
8016 | else | |
8017 | { | |
8018 | mintiny = - (1 << (op->nbits - 1)); | |
8019 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8020 | } | |
8021 | ||
8022 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8023 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 8024 | val /= 2; |
cc5703cd ILT |
8025 | |
8026 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8027 | || val < (mintiny << op->shift) | |
8028 | || val > (maxtiny << op->shift)) | |
8029 | needext = true; | |
8030 | else | |
8031 | needext = false; | |
8032 | ||
8033 | if (warn && ext && ! needext) | |
15e69f98 | 8034 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 8035 | if (small && needext) |
15e69f98 | 8036 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
8037 | |
8038 | if (small || (! ext && ! needext)) | |
8039 | { | |
8040 | int insnval; | |
8041 | ||
8042 | *use_extend = false; | |
8043 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8044 | insnval <<= op->op_shift; | |
8045 | *insn |= insnval; | |
8046 | } | |
8047 | else | |
8048 | { | |
8049 | long minext, maxext; | |
8050 | int extval; | |
8051 | ||
8052 | if (op->extu) | |
8053 | { | |
8054 | minext = 0; | |
8055 | maxext = (1 << op->extbits) - 1; | |
8056 | } | |
8057 | else | |
8058 | { | |
8059 | minext = - (1 << (op->extbits - 1)); | |
8060 | maxext = (1 << (op->extbits - 1)) - 1; | |
8061 | } | |
8062 | if (val < minext || val > maxext) | |
15e69f98 ILT |
8063 | as_bad_where (file, line, |
8064 | "operand value out of range for instruction"); | |
cc5703cd ILT |
8065 | |
8066 | *use_extend = true; | |
8067 | if (op->extbits == 16) | |
8068 | { | |
8069 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8070 | val &= 0x1f; | |
8071 | } | |
8072 | else if (op->extbits == 15) | |
8073 | { | |
8074 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8075 | val &= 0xf; | |
8076 | } | |
8077 | else | |
8078 | { | |
8079 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8080 | val = 0; | |
8081 | } | |
8082 | ||
8083 | *extend = (unsigned short) extval; | |
8084 | *insn |= val; | |
8085 | } | |
8086 | } | |
8087 | \f | |
3d3c5039 ILT |
8088 | #define LP '(' |
8089 | #define RP ')' | |
8090 | ||
8091 | static int | |
8092 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
8093 | expressionS *ep; |
8094 | char *str; | |
3d3c5039 | 8095 | { |
670a50eb ILT |
8096 | char *sp; |
8097 | int c = 0; | |
8098 | ||
8099 | if (*str == ' ') | |
8100 | str++; | |
8101 | if (*str == LP | |
8102 | || (*str == '%' && | |
8103 | ((str[1] == 'h' && str[2] == 'i') | |
8104 | || (str[1] == 'H' && str[2] == 'I') | |
8105 | || (str[1] == 'l' && str[2] == 'o')) | |
8106 | && str[3] == LP)) | |
8107 | { | |
8108 | if (*str == LP) | |
8109 | c = 0; | |
8110 | else | |
8111 | { | |
8112 | c = str[1]; | |
8113 | str += 3; | |
8114 | } | |
8115 | ||
8116 | /* | |
8117 | * A small expression may be followed by a base register. | |
8118 | * Scan to the end of this operand, and then back over a possible | |
8119 | * base register. Then scan the small expression up to that | |
8120 | * point. (Based on code in sparc.c...) | |
8121 | */ | |
8122 | for (sp = str; *sp && *sp != ','; sp++) | |
8123 | ; | |
8124 | if (sp - 4 >= str && sp[-1] == RP) | |
8125 | { | |
8126 | if (isdigit (sp[-2])) | |
8127 | { | |
8128 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
8129 | ; | |
8130 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8131 | { | |
8132 | sp--; | |
8133 | goto do_it; | |
3d3c5039 | 8134 | } |
670a50eb ILT |
8135 | } |
8136 | else if (sp - 5 >= str | |
8137 | && sp[-5] == LP | |
8138 | && sp[-4] == '$' | |
8139 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8140 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8141 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8142 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8143 | { | |
8144 | sp -= 5; | |
3d3c5039 | 8145 | do_it: |
670a50eb ILT |
8146 | if (sp == str) |
8147 | { | |
8148 | /* no expression means zero offset */ | |
8149 | if (c) | |
8150 | { | |
8151 | /* %xx(reg) is an error */ | |
5ac34ac3 | 8152 | ep->X_op = O_absent; |
670a50eb | 8153 | expr_end = str - 3; |
3d3c5039 | 8154 | } |
670a50eb ILT |
8155 | else |
8156 | { | |
52aa70b5 | 8157 | ep->X_op = O_constant; |
670a50eb ILT |
8158 | expr_end = sp; |
8159 | } | |
8160 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 8161 | ep->X_op_symbol = NULL; |
670a50eb ILT |
8162 | ep->X_add_number = 0; |
8163 | } | |
8164 | else | |
8165 | { | |
8166 | *sp = '\0'; | |
8167 | my_getExpression (ep, str); | |
8168 | *sp = LP; | |
3d3c5039 | 8169 | } |
670a50eb | 8170 | return c; |
3d3c5039 ILT |
8171 | } |
8172 | } | |
8173 | } | |
670a50eb ILT |
8174 | my_getExpression (ep, str); |
8175 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
8176 | } |
8177 | ||
8178 | static void | |
8179 | my_getExpression (ep, str) | |
670a50eb ILT |
8180 | expressionS *ep; |
8181 | char *str; | |
3d3c5039 | 8182 | { |
670a50eb | 8183 | char *save_in; |
670a50eb ILT |
8184 | |
8185 | save_in = input_line_pointer; | |
8186 | input_line_pointer = str; | |
5ac34ac3 | 8187 | expression (ep); |
670a50eb ILT |
8188 | expr_end = input_line_pointer; |
8189 | input_line_pointer = save_in; | |
eb17f56c ILT |
8190 | |
8191 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8192 | then we bump the value of the symbol by 1 since that is how other | |
8193 | text symbols are handled. We don't bother to handle complex | |
8194 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 8195 | if (mips_opts.mips16 |
eb17f56c ILT |
8196 | && ep->X_op == O_symbol |
8197 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8198 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
8199 | && ep->X_add_symbol->sy_frag == frag_now | |
8200 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
8201 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
8202 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
8203 | } |
8204 | ||
becfe05e ILT |
8205 | /* Turn a string in input_line_pointer into a floating point constant |
8206 | of type type, and store the appropriate bytes in *litP. The number | |
8207 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
8208 | returned, or NULL on OK. */ | |
8209 | ||
3d3c5039 | 8210 | char * |
670a50eb | 8211 | md_atof (type, litP, sizeP) |
becfe05e | 8212 | int type; |
3d3c5039 ILT |
8213 | char *litP; |
8214 | int *sizeP; | |
8215 | { | |
becfe05e ILT |
8216 | int prec; |
8217 | LITTLENUM_TYPE words[4]; | |
8218 | char *t; | |
8219 | int i; | |
8220 | ||
8221 | switch (type) | |
8222 | { | |
8223 | case 'f': | |
8224 | prec = 2; | |
8225 | break; | |
8226 | ||
8227 | case 'd': | |
8228 | prec = 4; | |
8229 | break; | |
8230 | ||
8231 | default: | |
8232 | *sizeP = 0; | |
8233 | return "bad call to md_atof"; | |
8234 | } | |
8235 | ||
8236 | t = atof_ieee (input_line_pointer, type, words); | |
8237 | if (t) | |
8238 | input_line_pointer = t; | |
8239 | ||
8240 | *sizeP = prec * 2; | |
8241 | ||
b9129c6f | 8242 | if (! target_big_endian) |
becfe05e ILT |
8243 | { |
8244 | for (i = prec - 1; i >= 0; i--) | |
8245 | { | |
8246 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8247 | litP += 2; | |
8248 | } | |
8249 | } | |
8250 | else | |
8251 | { | |
8252 | for (i = 0; i < prec; i++) | |
8253 | { | |
8254 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8255 | litP += 2; | |
8256 | } | |
8257 | } | |
8258 | ||
670a50eb | 8259 | return NULL; |
3d3c5039 ILT |
8260 | } |
8261 | ||
8262 | void | |
8263 | md_number_to_chars (buf, val, n) | |
8264 | char *buf; | |
918692a5 | 8265 | valueT val; |
3d3c5039 ILT |
8266 | int n; |
8267 | { | |
b9129c6f ILT |
8268 | if (target_big_endian) |
8269 | number_to_chars_bigendian (buf, val, n); | |
8270 | else | |
8271 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 8272 | } |
f3d817d8 | 8273 | \f |
e8d4d475 | 8274 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 8275 | |
f3d817d8 DM |
8276 | struct option md_longopts[] = { |
8277 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8278 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8279 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8280 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8281 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8282 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8283 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
8284 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
8285 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8286 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 8287 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 8288 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 8289 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 8290 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
8291 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8292 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 8293 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
8294 | {"break", no_argument, NULL, OPTION_BREAK}, |
8295 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 8296 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 8297 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 8298 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 8299 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 8300 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 8301 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 8302 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 8303 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
8304 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
8305 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8306 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8307 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
8308 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
8309 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8310 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8311 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 8312 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 8313 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 8314 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 8315 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 8316 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
8317 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
8318 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
8319 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
8320 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 8321 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
8322 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
8323 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
8324 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
8325 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
8326 | ||
f3d817d8 | 8327 | |
d8a1c247 | 8328 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 8329 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 8330 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
8331 | #define OPTION_32 (OPTION_MD_BASE + 20) |
8332 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 8333 | #ifdef OBJ_ELF |
f3d817d8 | 8334 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 8335 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 8336 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 8337 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
8338 | {"32", no_argument, NULL, OPTION_32}, |
8339 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
8340 | #endif |
8341 | ||
8342 | {NULL, no_argument, NULL, 0} | |
8343 | }; | |
8344 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
8345 | |
8346 | int | |
f3d817d8 DM |
8347 | md_parse_option (c, arg) |
8348 | int c; | |
8349 | char *arg; | |
3d3c5039 | 8350 | { |
f3d817d8 | 8351 | switch (c) |
670a50eb | 8352 | { |
f3d817d8 DM |
8353 | case OPTION_TRAP: |
8354 | mips_trap = 1; | |
8355 | break; | |
670a50eb | 8356 | |
f3d817d8 DM |
8357 | case OPTION_BREAK: |
8358 | mips_trap = 0; | |
8359 | break; | |
8360 | ||
e8d4d475 | 8361 | case OPTION_EB: |
1dc1e798 | 8362 | target_big_endian = 1; |
e8d4d475 | 8363 | break; |
04cb3372 | 8364 | |
e8d4d475 | 8365 | case OPTION_EL: |
1dc1e798 | 8366 | target_big_endian = 0; |
f3d817d8 | 8367 | break; |
670a50eb | 8368 | |
f3d817d8 DM |
8369 | case 'O': |
8370 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
8371 | mips_optimize = 1; |
8372 | else | |
8373 | mips_optimize = 2; | |
f3d817d8 | 8374 | break; |
0aa07269 | 8375 | |
f3d817d8 | 8376 | case 'g': |
22ba90ce ILT |
8377 | if (arg == NULL) |
8378 | mips_debug = 2; | |
8379 | else | |
8380 | mips_debug = atoi (arg); | |
8381 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8382 | optimizations which limit full symbolic debugging. We take | |
8383 | that to be equivalent to -O0. */ | |
8384 | if (mips_debug == 2) | |
05874c2e | 8385 | mips_optimize = 1; |
f3d817d8 | 8386 | break; |
4e95866e | 8387 | |
f3d817d8 | 8388 | case OPTION_MIPS1: |
3c83da8a | 8389 | mips_opts.isa = 1; |
4bb0cc41 ILT |
8390 | if (mips_cpu == -1) |
8391 | mips_cpu = 3000; | |
f3d817d8 | 8392 | break; |
8358c818 | 8393 | |
f3d817d8 | 8394 | case OPTION_MIPS2: |
3c83da8a | 8395 | mips_opts.isa = 2; |
4bb0cc41 ILT |
8396 | if (mips_cpu == -1) |
8397 | mips_cpu = 6000; | |
f3d817d8 | 8398 | break; |
8358c818 | 8399 | |
f3d817d8 | 8400 | case OPTION_MIPS3: |
3c83da8a | 8401 | mips_opts.isa = 3; |
4bb0cc41 ILT |
8402 | if (mips_cpu == -1) |
8403 | mips_cpu = 4000; | |
f3d817d8 | 8404 | break; |
8358c818 | 8405 | |
d8a1c247 | 8406 | case OPTION_MIPS4: |
3c83da8a | 8407 | mips_opts.isa = 4; |
d8a1c247 KR |
8408 | if (mips_cpu == -1) |
8409 | mips_cpu = 8000; | |
8410 | break; | |
8411 | ||
f3d817d8 DM |
8412 | case OPTION_MCPU: |
8413 | { | |
8414 | char *p; | |
8415 | ||
8416 | /* Identify the processor type */ | |
8417 | p = arg; | |
8418 | if (strcmp (p, "default") == 0 | |
8419 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 8420 | mips_cpu = -1; |
f3d817d8 DM |
8421 | else |
8422 | { | |
c625fc23 JSC |
8423 | int sv = 0; |
8424 | ||
8425 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8426 | processor. */ | |
8427 | if (*p == 'v' || *p == 'V') | |
8428 | { | |
8429 | sv = 1; | |
8430 | p++; | |
8431 | } | |
8432 | ||
f3d817d8 DM |
8433 | if (*p == 'r' || *p == 'R') |
8434 | p++; | |
8358c818 | 8435 | |
4bb0cc41 | 8436 | mips_cpu = -1; |
f3d817d8 DM |
8437 | switch (*p) |
8438 | { | |
d8a1c247 KR |
8439 | case '1': |
8440 | if (strcmp (p, "10000") == 0 | |
8441 | || strcmp (p, "10k") == 0 | |
8442 | || strcmp (p, "10K") == 0) | |
8443 | mips_cpu = 10000; | |
8444 | break; | |
8445 | ||
f3d817d8 DM |
8446 | case '2': |
8447 | if (strcmp (p, "2000") == 0 | |
8448 | || strcmp (p, "2k") == 0 | |
8449 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 8450 | mips_cpu = 2000; |
f3d817d8 | 8451 | break; |
8358c818 | 8452 | |
f3d817d8 DM |
8453 | case '3': |
8454 | if (strcmp (p, "3000") == 0 | |
8455 | || strcmp (p, "3k") == 0 | |
8456 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 8457 | mips_cpu = 3000; |
5c6f5923 GRK |
8458 | else if (strcmp (p, "3900") == 0) |
8459 | mips_cpu = 3900; | |
f3d817d8 | 8460 | break; |
8358c818 | 8461 | |
f3d817d8 DM |
8462 | case '4': |
8463 | if (strcmp (p, "4000") == 0 | |
8464 | || strcmp (p, "4k") == 0 | |
8c63448a | 8465 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 8466 | mips_cpu = 4000; |
c625fc23 JSC |
8467 | else if (strcmp (p, "4100") == 0) |
8468 | { | |
8469 | mips_cpu = 4100; | |
8470 | if (mips_4100 < 0) | |
8471 | mips_4100 = 1; | |
8472 | } | |
8473 | else if (strcmp (p, "4300") == 0) | |
8474 | mips_cpu = 4300; | |
8c63448a | 8475 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 8476 | mips_cpu = 4400; |
8c63448a | 8477 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 8478 | mips_cpu = 4600; |
b2b8c24e ILT |
8479 | else if (strcmp (p, "4650") == 0) |
8480 | { | |
8481 | mips_cpu = 4650; | |
8482 | if (mips_4650 < 0) | |
8483 | mips_4650 = 1; | |
8484 | } | |
e532b44c ILT |
8485 | else if (strcmp (p, "4010") == 0) |
8486 | { | |
8487 | mips_cpu = 4010; | |
8488 | if (mips_4010 < 0) | |
8489 | mips_4010 = 1; | |
8490 | } | |
f3d817d8 | 8491 | break; |
8358c818 | 8492 | |
517078c1 ILT |
8493 | case '5': |
8494 | if (strcmp (p, "5000") == 0 | |
8495 | || strcmp (p, "5k") == 0 | |
8496 | || strcmp (p, "5K") == 0) | |
8497 | mips_cpu = 5000; | |
276c2d7d GRK |
8498 | /* start-sanitize-r5900 */ |
8499 | else if (strcmp (p, "5900") == 0) | |
8500 | mips_cpu = 5900; | |
8501 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
8502 | break; |
8503 | ||
f3d817d8 DM |
8504 | case '6': |
8505 | if (strcmp (p, "6000") == 0 | |
8506 | || strcmp (p, "6k") == 0 | |
8507 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 8508 | mips_cpu = 6000; |
f3d817d8 | 8509 | break; |
55933a58 | 8510 | |
d8a1c247 KR |
8511 | case '8': |
8512 | if (strcmp (p, "8000") == 0 | |
8513 | || strcmp (p, "8k") == 0 | |
8514 | || strcmp (p, "8K") == 0) | |
8515 | mips_cpu = 8000; | |
8516 | break; | |
8517 | ||
55933a58 ILT |
8518 | case 'o': |
8519 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 8520 | mips_cpu = 4600; |
55933a58 | 8521 | break; |
f3d817d8 | 8522 | } |
8358c818 | 8523 | |
517078c1 | 8524 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
8525 | { |
8526 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
8527 | return 0; | |
8528 | } | |
8529 | ||
4bb0cc41 | 8530 | if (mips_cpu == -1) |
f3d817d8 DM |
8531 | { |
8532 | as_bad ("invalid architecture -mcpu=%s", arg); | |
8533 | return 0; | |
8534 | } | |
8535 | } | |
8536 | } | |
8537 | break; | |
8358c818 | 8538 | |
b2b8c24e ILT |
8539 | case OPTION_M4650: |
8540 | mips_4650 = 1; | |
8541 | break; | |
8542 | ||
8543 | case OPTION_NO_M4650: | |
8544 | mips_4650 = 0; | |
8545 | break; | |
8546 | ||
e532b44c ILT |
8547 | case OPTION_M4010: |
8548 | mips_4010 = 1; | |
8549 | break; | |
8550 | ||
8551 | case OPTION_NO_M4010: | |
8552 | mips_4010 = 0; | |
8553 | break; | |
8554 | ||
c625fc23 JSC |
8555 | case OPTION_M4100: |
8556 | mips_4100 = 1; | |
8557 | break; | |
8558 | ||
8559 | case OPTION_NO_M4100: | |
8560 | mips_4100 = 0; | |
8561 | break; | |
8562 | ||
276c2d7d GRK |
8563 | /* start-sanitize-r5900 */ |
8564 | case OPTION_M5900: | |
8565 | mips_5900 = 1; | |
8566 | break; | |
8567 | ||
8568 | case OPTION_NO_M5900: | |
8569 | mips_5900 = 0; | |
8570 | break; | |
8571 | /* end-sanitize-r5900 */ | |
8572 | ||
5c6f5923 GRK |
8573 | case OPTION_M3900: |
8574 | mips_3900 = 1; | |
8575 | break; | |
8576 | ||
8577 | case OPTION_NO_M3900: | |
8578 | mips_3900 = 0; | |
8579 | break; | |
8580 | ||
cc5703cd | 8581 | case OPTION_MIPS16: |
3c83da8a | 8582 | mips_opts.mips16 = 1; |
4a1cb507 | 8583 | mips_no_prev_insn (false); |
cc5703cd ILT |
8584 | break; |
8585 | ||
8586 | case OPTION_NO_MIPS16: | |
3c83da8a | 8587 | mips_opts.mips16 = 0; |
4a1cb507 | 8588 | mips_no_prev_insn (false); |
cc5703cd ILT |
8589 | break; |
8590 | ||
f3d817d8 | 8591 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8592 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8593 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8594 | { |
8595 | as_bad ("-G may not be used with embedded PIC code"); | |
8596 | return 0; | |
8597 | } | |
5b63f465 | 8598 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8599 | break; |
d9aba805 | 8600 | |
fb251650 ILT |
8601 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8602 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8603 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8604 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8605 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8606 | { | |
8607 | as_bad ("-call_shared is supported only for ELF format"); | |
8608 | return 0; | |
8609 | } | |
d9aba805 ILT |
8610 | mips_pic = SVR4_PIC; |
8611 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8612 | { |
8613 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8614 | return 0; | |
8615 | } | |
d9aba805 | 8616 | g_switch_value = 0; |
f3d817d8 DM |
8617 | break; |
8618 | ||
8619 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8620 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8621 | { | |
8622 | as_bad ("-non_shared is supported only for ELF format"); | |
8623 | return 0; | |
8624 | } | |
d9aba805 | 8625 | mips_pic = NO_PIC; |
f3d817d8 | 8626 | break; |
8358c818 | 8627 | |
fb251650 ILT |
8628 | /* The -xgot option tells the assembler to use 32 offsets when |
8629 | accessing the got in SVR4_PIC mode. It is for Irix | |
8630 | compatibility. */ | |
8631 | case OPTION_XGOT: | |
8632 | mips_big_got = 1; | |
8633 | break; | |
8634 | ||
f3d817d8 | 8635 | case 'G': |
1dc1e798 KR |
8636 | if (! USE_GLOBAL_POINTER_OPT) |
8637 | { | |
8638 | as_bad ("-G is not supported for this configuration"); | |
8639 | return 0; | |
8640 | } | |
8641 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8642 | { |
f3d817d8 DM |
8643 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8644 | return 0; | |
670a50eb ILT |
8645 | } |
8646 | else | |
f3d817d8 | 8647 | g_switch_value = atoi (arg); |
42562568 | 8648 | g_switch_seen = 1; |
f3d817d8 | 8649 | break; |
4e95866e | 8650 | |
7f9880e5 ILT |
8651 | /* The -32 and -64 options tell the assembler to output the 32 |
8652 | bit or the 64 bit MIPS ELF format. */ | |
8653 | case OPTION_32: | |
8654 | mips_64 = 0; | |
8655 | break; | |
8656 | ||
8657 | case OPTION_64: | |
9c44af60 ILT |
8658 | { |
8659 | const char **list, **l; | |
8660 | ||
8661 | list = bfd_target_list (); | |
8662 | for (l = list; *l != NULL; l++) | |
8663 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8664 | || strcmp (*l, "elf64-littlemips") == 0) | |
8665 | break; | |
8666 | if (*l == NULL) | |
8667 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8668 | free (list); | |
8669 | mips_64 = 1; | |
8670 | } | |
7f9880e5 ILT |
8671 | break; |
8672 | ||
f3d817d8 DM |
8673 | default: |
8674 | return 0; | |
8ea7f4e8 ILT |
8675 | } |
8676 | ||
f3d817d8 | 8677 | return 1; |
8ea7f4e8 ILT |
8678 | } |
8679 | ||
f3d817d8 DM |
8680 | void |
8681 | md_show_usage (stream) | |
8682 | FILE *stream; | |
8683 | { | |
8684 | fprintf(stream, "\ | |
8685 | MIPS options:\n\ | |
8686 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8687 | -EB generate big endian output\n\ |
8688 | -EL generate little endian output\n\ | |
8689 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8690 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8691 | implicitly with the gp register [default 8]\n"); |
8692 | fprintf(stream, "\ | |
f3d817d8 DM |
8693 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8694 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8695 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8696 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8697 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8698 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8699 | -m4650 permit R4650 instructions\n\ |
8700 | -no-m4650 do not permit R4650 instructions\n\ | |
8701 | -m4010 permit R4010 instructions\n\ | |
8702 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8703 | -m4100 permit VR4100 instructions\n\ |
8704 | -no-m4100 do not permit VR4100 instructions\n"); | |
8705 | fprintf(stream, "\ | |
cc5703cd ILT |
8706 | -mips16 generate mips16 instructions\n\ |
8707 | -no-mips16 do not generate mips16 instructions\n"); | |
8708 | fprintf(stream, "\ | |
f3d817d8 DM |
8709 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8710 | -O remove unneeded NOPs and swap branches\n\ | |
8711 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8712 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8713 | #ifdef OBJ_ELF | |
8714 | fprintf(stream, "\ | |
8715 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8716 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8717 | -xgot assume a 32 bit GOT\n\ |
8718 | -32 create 32 bit object file (default)\n\ | |
8719 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8720 | #endif |
8721 | } | |
8722 | \f | |
efec4a28 DP |
8723 | void |
8724 | mips_init_after_args () | |
8725 | { | |
af942793 SS |
8726 | /* initialize opcodes */ |
8727 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
8728 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
8729 | } |
8730 | ||
3d3c5039 ILT |
8731 | long |
8732 | md_pcrel_from (fixP) | |
8733 | fixS *fixP; | |
8734 | { | |
1dc1e798 KR |
8735 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8736 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8737 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8738 | { | |
8739 | /* This makes a branch to an undefined symbol be a branch to the | |
8740 | current location. */ | |
8741 | return 4; | |
8742 | } | |
5b63f465 | 8743 | |
670a50eb ILT |
8744 | /* return the address of the delay slot */ |
8745 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8746 | } |
8747 | ||
abdad6bc ILT |
8748 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8749 | reloc for a cons. We could use the definition there, except that | |
8750 | we want to handle 64 bit relocs specially. */ | |
8751 | ||
8752 | void | |
8753 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8754 | fragS *frag; | |
8755 | int where; | |
8756 | unsigned int nbytes; | |
8757 | expressionS *exp; | |
8758 | { | |
bf39474f | 8759 | #ifndef OBJ_ELF |
abdad6bc | 8760 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8761 | 4 byte reloc. */ |
8762 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8763 | { |
b9129c6f | 8764 | if (target_big_endian) |
abdad6bc ILT |
8765 | where += 4; |
8766 | nbytes = 4; | |
8767 | } | |
bf39474f | 8768 | #endif |
abdad6bc | 8769 | |
7f9880e5 | 8770 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8771 | as_bad ("Unsupported reloc size %d", nbytes); |
8772 | ||
8773 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8774 | (nbytes == 2 |
8775 | ? BFD_RELOC_16 | |
8776 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8777 | } |
8778 | ||
23604921 ILT |
8779 | /* This is called before the symbol table is processed. In order to |
8780 | work with gcc when using mips-tfile, we must keep all local labels. | |
8781 | However, in other cases, we want to discard them. If we were | |
8782 | called with -g, but we didn't see any debugging information, it may | |
8783 | mean that gcc is smuggling debugging information through to | |
8784 | mips-tfile, in which case we must generate all local labels. */ | |
8785 | ||
8786 | void | |
8787 | mips_frob_file_before_adjust () | |
8788 | { | |
8789 | #ifndef NO_ECOFF_DEBUGGING | |
8790 | if (ECOFF_DEBUGGING | |
8791 | && mips_debug != 0 | |
8792 | && ! ecoff_debugging_seen) | |
8793 | flag_keep_locals = 1; | |
8794 | #endif | |
8795 | } | |
8796 | ||
867a58b3 ILT |
8797 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8798 | the corresponding LO reloc. This is called before md_apply_fix and | |
8799 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8800 | explicit use of the %hi modifier. */ | |
8801 | ||
8802 | void | |
8803 | mips_frob_file () | |
8804 | { | |
8805 | struct mips_hi_fixup *l; | |
8806 | ||
8807 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8808 | { | |
8809 | segment_info_type *seginfo; | |
9b61d62b | 8810 | int pass; |
867a58b3 ILT |
8811 | |
8812 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8813 | ||
8814 | /* Check quickly whether the next fixup happens to be a matching | |
8815 | %lo. */ | |
8816 | if (l->fixp->fx_next != NULL | |
8817 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8818 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8819 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8820 | continue; | |
8821 | ||
8822 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8823 | When we find one, move the %hi just in front of it. We do |
8824 | this in two passes. In the first pass, we try to find a | |
8825 | unique %lo. In the second pass, we permit multiple %hi | |
8826 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8827 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8828 | for (pass = 0; pass < 2; pass++) |
8829 | { | |
8830 | fixS *f, *prev; | |
8831 | ||
8832 | prev = NULL; | |
8833 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8834 | { |
9b61d62b ILT |
8835 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8836 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8837 | && f->fx_addsy == l->fixp->fx_addsy | |
8838 | && f->fx_offset == l->fixp->fx_offset | |
8839 | && (pass == 1 | |
8840 | || prev == NULL | |
8841 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8842 | || prev->fx_addsy != f->fx_addsy | |
8843 | || prev->fx_offset != f->fx_offset)) | |
8844 | { | |
8845 | fixS **pf; | |
867a58b3 | 8846 | |
9b61d62b ILT |
8847 | /* Move l->fixp before f. */ |
8848 | for (pf = &seginfo->fix_root; | |
8849 | *pf != l->fixp; | |
8850 | pf = &(*pf)->fx_next) | |
8851 | assert (*pf != NULL); | |
867a58b3 | 8852 | |
9b61d62b | 8853 | *pf = l->fixp->fx_next; |
867a58b3 | 8854 | |
9b61d62b ILT |
8855 | l->fixp->fx_next = f; |
8856 | if (prev == NULL) | |
8857 | seginfo->fix_root = l->fixp; | |
8858 | else | |
8859 | prev->fx_next = l->fixp; | |
867a58b3 | 8860 | |
9b61d62b ILT |
8861 | break; |
8862 | } | |
8863 | ||
8864 | prev = f; | |
867a58b3 ILT |
8865 | } |
8866 | ||
9b61d62b ILT |
8867 | if (f != NULL) |
8868 | break; | |
867a58b3 | 8869 | |
9b61d62b ILT |
8870 | if (pass == 1) |
8871 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8872 | "Unmatched %%hi reloc"); | |
8873 | } | |
867a58b3 ILT |
8874 | } |
8875 | } | |
8876 | ||
1c803e52 ILT |
8877 | /* When generating embedded PIC code we need to use a special |
8878 | relocation to represent the difference of two symbols in the .text | |
8879 | section (switch tables use a difference of this sort). See | |
8880 | include/coff/mips.h for details. This macro checks whether this | |
8881 | fixup requires the special reloc. */ | |
8882 | #define SWITCH_TABLE(fixp) \ | |
8883 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8884 | && (fixp)->fx_addsy != NULL \ | |
8885 | && (fixp)->fx_subsy != NULL \ | |
8886 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8887 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8888 | ||
5b63f465 | 8889 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8890 | relocations, in case the linker has to relax a call. We also need |
8891 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8892 | |
8893 | /*ARGSUSED*/ | |
8894 | int | |
8895 | mips_force_relocation (fixp) | |
8896 | fixS *fixp; | |
8897 | { | |
1c803e52 | 8898 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8899 | && (fixp->fx_pcrel |
8900 | || SWITCH_TABLE (fixp) | |
8901 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8902 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8903 | } |
8904 | ||
8905 | /* Apply a fixup to the object file. */ | |
8906 | ||
3d3c5039 ILT |
8907 | int |
8908 | md_apply_fix (fixP, valueP) | |
8909 | fixS *fixP; | |
918692a5 | 8910 | valueT *valueP; |
3d3c5039 | 8911 | { |
670a50eb ILT |
8912 | unsigned char *buf; |
8913 | long insn, value; | |
3d3c5039 | 8914 | |
bf39474f ILT |
8915 | assert (fixP->fx_size == 4 |
8916 | || fixP->fx_r_type == BFD_RELOC_16 | |
8917 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8918 | |
670a50eb | 8919 | value = *valueP; |
1748b9d8 ILT |
8920 | |
8921 | /* If we aren't adjusting this fixup to be against the section | |
8922 | symbol, we need to adjust the value. */ | |
68952421 | 8923 | #ifdef OBJ_ELF |
1748b9d8 | 8924 | if (fixP->fx_addsy != NULL |
1748b9d8 ILT |
8925 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
8926 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
8927 | { | |
8928 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8929 | if (value != 0 && ! fixP->fx_pcrel) | |
8930 | { | |
8931 | /* In this case, the bfd_install_relocation routine will | |
8932 | incorrectly add the symbol value back in. We just want | |
8933 | the addend to appear in the object file. */ | |
8934 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8935 | } | |
8936 | } | |
8937 | #endif | |
8938 | ||
670a50eb | 8939 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 8940 | |
5b63f465 ILT |
8941 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8942 | fixP->fx_done = 1; | |
8943 | ||
670a50eb ILT |
8944 | switch (fixP->fx_r_type) |
8945 | { | |
3d3c5039 ILT |
8946 | case BFD_RELOC_MIPS_JMP: |
8947 | case BFD_RELOC_HI16: | |
8948 | case BFD_RELOC_HI16_S: | |
670a50eb | 8949 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8950 | case BFD_RELOC_MIPS_LITERAL: |
8951 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8952 | case BFD_RELOC_MIPS_GOT16: |
8953 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8954 | case BFD_RELOC_MIPS_GOT_HI16: |
8955 | case BFD_RELOC_MIPS_GOT_LO16: | |
8956 | case BFD_RELOC_MIPS_CALL_HI16: | |
8957 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 8958 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 8959 | if (fixP->fx_pcrel) |
7b777690 ILT |
8960 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8961 | "Invalid PC relative reloc"); | |
670a50eb | 8962 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8963 | break; |
3d3c5039 | 8964 | |
cc5703cd ILT |
8965 | case BFD_RELOC_MIPS16_JMP: |
8966 | /* We currently always generate a reloc against a symbol, which | |
8967 | means that we don't want an addend even if the symbol is | |
8968 | defined. */ | |
8969 | fixP->fx_addnumber = 0; | |
8970 | break; | |
8971 | ||
ecd4ca1c ILT |
8972 | case BFD_RELOC_PCREL_HI16_S: |
8973 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8974 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8975 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8976 | { | |
8977 | /* For an external symbol adjust by the address to make it | |
8978 | pcrel_offset. We use the address of the RELLO reloc | |
8979 | which follows this one. */ | |
8980 | value += (fixP->fx_next->fx_frag->fr_address | |
8981 | + fixP->fx_next->fx_where); | |
8982 | } | |
8983 | if (value & 0x8000) | |
8984 | value += 0x10000; | |
8985 | value >>= 16; | |
0221ddf7 | 8986 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8987 | if (target_big_endian) |
ecd4ca1c ILT |
8988 | buf += 2; |
8989 | md_number_to_chars (buf, value, 2); | |
8990 | break; | |
8991 | ||
8992 | case BFD_RELOC_PCREL_LO16: | |
8993 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8994 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8995 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8996 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8997 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 8998 | if (target_big_endian) |
ecd4ca1c ILT |
8999 | buf += 2; |
9000 | md_number_to_chars (buf, value, 2); | |
9001 | break; | |
9002 | ||
bf39474f ILT |
9003 | case BFD_RELOC_64: |
9004 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9005 | extended value if we are only 32 bits. */ | |
9006 | if (fixP->fx_done | |
9007 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9008 | { | |
9009 | if (8 <= sizeof (valueT)) | |
9010 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9011 | value, 8); | |
9012 | else | |
9013 | { | |
9014 | long w1, w2; | |
9015 | long hiv; | |
9016 | ||
9017 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 9018 | if (target_big_endian) |
bf39474f ILT |
9019 | w1 += 4; |
9020 | else | |
9021 | w2 += 4; | |
9022 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9023 | if ((value & 0x80000000) != 0) | |
9024 | hiv = 0xffffffff; | |
9025 | else | |
9026 | hiv = 0; | |
9027 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9028 | } | |
9029 | } | |
9030 | break; | |
9031 | ||
f3645945 ILT |
9032 | case BFD_RELOC_32: |
9033 | /* If we are deleting this reloc entry, we must fill in the | |
9034 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
9035 | resolved when it appears but is later defined. We also need |
9036 | to fill in the value if this is an embedded PIC switch table | |
9037 | entry. */ | |
9038 | if (fixP->fx_done | |
9039 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
9040 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
9041 | value, 4); | |
9042 | break; | |
9043 | ||
49ad0c4c ILT |
9044 | case BFD_RELOC_16: |
9045 | /* If we are deleting this reloc entry, we must fill in the | |
9046 | value now. */ | |
9047 | assert (fixP->fx_size == 2); | |
9048 | if (fixP->fx_done) | |
9049 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9050 | value, 2); | |
9051 | break; | |
9052 | ||
f3645945 ILT |
9053 | case BFD_RELOC_LO16: |
9054 | /* When handling an embedded PIC switch statement, we can wind | |
9055 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9056 | if (fixP->fx_done) | |
9057 | { | |
9058 | if (value < -0x8000 || value > 0x7fff) | |
9059 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9060 | "relocation overflow"); | |
0221ddf7 | 9061 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9062 | if (target_big_endian) |
f3645945 ILT |
9063 | buf += 2; |
9064 | md_number_to_chars (buf, value, 2); | |
9065 | } | |
9066 | break; | |
9067 | ||
3d3c5039 | 9068 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
9069 | /* |
9070 | * We need to save the bits in the instruction since fixup_segment() | |
9071 | * might be deleting the relocation entry (i.e., a branch within | |
9072 | * the current segment). | |
9073 | */ | |
fbcfacb7 | 9074 | if ((value & 0x3) != 0) |
3b320c48 ILT |
9075 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9076 | "Branch to odd address (%lx)", value); | |
670a50eb | 9077 | value >>= 2; |
670a50eb ILT |
9078 | |
9079 | /* update old instruction data */ | |
9080 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
9081 | if (target_big_endian) |
9082 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9083 | else | |
9084 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
9085 | |
9086 | if (value >= -0x8000 && value < 0x8000) | |
9087 | insn |= value & 0xffff; | |
9088 | else | |
9089 | { | |
9090 | /* The branch offset is too large. If this is an | |
9091 | unconditional branch, and we are not generating PIC code, | |
9092 | we can convert it to an absolute jump instruction. */ | |
9093 | if (mips_pic == NO_PIC | |
9094 | && fixP->fx_done | |
9095 | && fixP->fx_frag->fr_address >= text_section->vma | |
9096 | && (fixP->fx_frag->fr_address | |
9097 | < text_section->vma + text_section->_raw_size) | |
9098 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9099 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9100 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9101 | { | |
9102 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9103 | insn = 0x0c000000; /* jal */ | |
9104 | else | |
9105 | insn = 0x08000000; /* j */ | |
9106 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9107 | fixP->fx_done = 0; | |
9108 | fixP->fx_addsy = section_symbol (text_section); | |
9109 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9110 | } | |
9111 | else | |
9112 | { | |
9113 | /* FIXME. It would be possible in principle to handle | |
9114 | conditional branches which overflow. They could be | |
9115 | transformed into a branch around a jump. This would | |
9116 | require setting up variant frags for each different | |
9117 | branch type. The native MIPS assembler attempts to | |
9118 | handle these cases, but it appears to do it | |
9119 | incorrectly. */ | |
9120 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18f7e3dc | 9121 | "Branch out of range"); |
9da4c5d1 ILT |
9122 | } |
9123 | } | |
9124 | ||
604633ae | 9125 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 9126 | break; |
3d3c5039 ILT |
9127 | |
9128 | default: | |
670a50eb | 9129 | internalError (); |
3d3c5039 | 9130 | } |
5b63f465 | 9131 | |
670a50eb | 9132 | return 1; |
3d3c5039 ILT |
9133 | } |
9134 | ||
9135 | #if 0 | |
9136 | void | |
670a50eb ILT |
9137 | printInsn (oc) |
9138 | unsigned long oc; | |
3d3c5039 | 9139 | { |
670a50eb ILT |
9140 | const struct mips_opcode *p; |
9141 | int treg, sreg, dreg, shamt; | |
9142 | short imm; | |
9143 | const char *args; | |
9144 | int i; | |
3d3c5039 | 9145 | |
670a50eb ILT |
9146 | for (i = 0; i < NUMOPCODES; ++i) |
9147 | { | |
9148 | p = &mips_opcodes[i]; | |
9149 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9150 | { | |
9151 | printf ("%08lx %s\t", oc, p->name); | |
9152 | treg = (oc >> 16) & 0x1f; | |
9153 | sreg = (oc >> 21) & 0x1f; | |
9154 | dreg = (oc >> 11) & 0x1f; | |
9155 | shamt = (oc >> 6) & 0x1f; | |
9156 | imm = oc; | |
9157 | for (args = p->args;; ++args) | |
9158 | { | |
9159 | switch (*args) | |
9160 | { | |
3d3c5039 | 9161 | case '\0': |
670a50eb ILT |
9162 | printf ("\n"); |
9163 | break; | |
3d3c5039 ILT |
9164 | |
9165 | case ',': | |
9166 | case '(': | |
9167 | case ')': | |
670a50eb ILT |
9168 | printf ("%c", *args); |
9169 | continue; | |
3d3c5039 ILT |
9170 | |
9171 | case 'r': | |
670a50eb ILT |
9172 | assert (treg == sreg); |
9173 | printf ("$%d,$%d", treg, sreg); | |
9174 | continue; | |
3d3c5039 ILT |
9175 | |
9176 | case 'd': | |
918692a5 | 9177 | case 'G': |
670a50eb ILT |
9178 | printf ("$%d", dreg); |
9179 | continue; | |
3d3c5039 ILT |
9180 | |
9181 | case 't': | |
918692a5 | 9182 | case 'E': |
670a50eb ILT |
9183 | printf ("$%d", treg); |
9184 | continue; | |
3d3c5039 | 9185 | |
9226253a ILT |
9186 | case 'k': |
9187 | printf ("0x%x", treg); | |
9188 | continue; | |
9189 | ||
3d3c5039 ILT |
9190 | case 'b': |
9191 | case 's': | |
670a50eb ILT |
9192 | printf ("$%d", sreg); |
9193 | continue; | |
3d3c5039 ILT |
9194 | |
9195 | case 'a': | |
670a50eb ILT |
9196 | printf ("0x%08lx", oc & 0x1ffffff); |
9197 | continue; | |
3d3c5039 ILT |
9198 | |
9199 | case 'i': | |
9200 | case 'j': | |
9201 | case 'o': | |
9202 | case 'u': | |
670a50eb ILT |
9203 | printf ("%d", imm); |
9204 | continue; | |
3d3c5039 ILT |
9205 | |
9206 | case '<': | |
56c96faa | 9207 | case '>': |
670a50eb ILT |
9208 | printf ("$%d", shamt); |
9209 | continue; | |
3d3c5039 ILT |
9210 | |
9211 | default: | |
670a50eb | 9212 | internalError (); |
3d3c5039 | 9213 | } |
670a50eb | 9214 | break; |
3d3c5039 | 9215 | } |
670a50eb | 9216 | return; |
3d3c5039 ILT |
9217 | } |
9218 | } | |
670a50eb | 9219 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
9220 | } |
9221 | #endif | |
9222 | ||
9223 | static symbolS * | |
9224 | get_symbol () | |
9225 | { | |
670a50eb ILT |
9226 | int c; |
9227 | char *name; | |
9228 | symbolS *p; | |
9229 | ||
9230 | name = input_line_pointer; | |
9231 | c = get_symbol_end (); | |
9232 | p = (symbolS *) symbol_find_or_make (name); | |
9233 | *input_line_pointer = c; | |
9234 | return p; | |
3d3c5039 ILT |
9235 | } |
9236 | ||
becfe05e ILT |
9237 | /* Align the current frag to a given power of two. The MIPS assembler |
9238 | also automatically adjusts any preceding label. */ | |
9239 | ||
9240 | static void | |
23dc1ae3 | 9241 | mips_align (to, fill, label) |
becfe05e ILT |
9242 | int to; |
9243 | int fill; | |
23dc1ae3 | 9244 | symbolS *label; |
becfe05e | 9245 | { |
fbcfacb7 | 9246 | mips_emit_delays (false); |
e2e5acfa | 9247 | frag_align (to, fill, 0); |
becfe05e | 9248 | record_alignment (now_seg, to); |
23dc1ae3 | 9249 | if (label != NULL) |
becfe05e | 9250 | { |
23dc1ae3 ILT |
9251 | assert (S_GET_SEGMENT (label) == now_seg); |
9252 | label->sy_frag = frag_now; | |
9253 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
9254 | } |
9255 | } | |
9256 | ||
9257 | /* Align to a given power of two. .align 0 turns off the automatic | |
9258 | alignment used by the data creating pseudo-ops. */ | |
9259 | ||
3d3c5039 ILT |
9260 | static void |
9261 | s_align (x) | |
9262 | int x; | |
9263 | { | |
670a50eb ILT |
9264 | register int temp; |
9265 | register long temp_fill; | |
9266 | long max_alignment = 15; | |
3d3c5039 | 9267 | |
670a50eb | 9268 | /* |
3d3c5039 ILT |
9269 | |
9270 | o Note that the assembler pulls down any immediately preceeding label | |
9271 | to the aligned address. | |
9272 | o It's not documented but auto alignment is reinstated by | |
9273 | a .align pseudo instruction. | |
9274 | o Note also that after auto alignment is turned off the mips assembler | |
9275 | issues an error on attempt to assemble an improperly aligned data item. | |
9276 | We don't. | |
9277 | ||
9278 | */ | |
9279 | ||
670a50eb ILT |
9280 | temp = get_absolute_expression (); |
9281 | if (temp > max_alignment) | |
9282 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
9283 | else if (temp < 0) | |
9284 | { | |
9285 | as_warn ("Alignment negative: 0 assumed."); | |
9286 | temp = 0; | |
9287 | } | |
9288 | if (*input_line_pointer == ',') | |
9289 | { | |
9290 | input_line_pointer++; | |
9291 | temp_fill = get_absolute_expression (); | |
9292 | } | |
9293 | else | |
9294 | temp_fill = 0; | |
9295 | if (temp) | |
9296 | { | |
9297 | auto_align = 1; | |
fbcfacb7 ILT |
9298 | mips_align (temp, (int) temp_fill, |
9299 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 9300 | } |
670a50eb ILT |
9301 | else |
9302 | { | |
9303 | auto_align = 0; | |
3d3c5039 ILT |
9304 | } |
9305 | ||
670a50eb | 9306 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9307 | } |
9308 | ||
739708fa KR |
9309 | void |
9310 | mips_flush_pending_output () | |
becfe05e | 9311 | { |
fbcfacb7 ILT |
9312 | mips_emit_delays (false); |
9313 | mips_clear_insn_labels (); | |
becfe05e ILT |
9314 | } |
9315 | ||
3d3c5039 ILT |
9316 | static void |
9317 | s_change_sec (sec) | |
9318 | int sec; | |
9319 | { | |
88225433 | 9320 | segT seg; |
becfe05e | 9321 | |
5b63f465 ILT |
9322 | /* When generating embedded PIC code, we only use the .text, .lit8, |
9323 | .sdata and .sbss sections. We change the .data and .rdata | |
9324 | pseudo-ops to use .sdata. */ | |
9325 | if (mips_pic == EMBEDDED_PIC | |
9326 | && (sec == 'd' || sec == 'r')) | |
9327 | sec = 's'; | |
9328 | ||
acdc7ce3 ILT |
9329 | #ifdef OBJ_ELF |
9330 | /* The ELF backend needs to know that we are changing sections, so | |
9331 | that .previous works correctly. We could do something like check | |
9332 | for a obj_section_change_hook macro, but that might be confusing | |
9333 | as it would not be appropriate to use it in the section changing | |
9334 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
9335 | This should be cleaner, somehow. */ | |
9336 | obj_elf_section_change_hook (); | |
9337 | #endif | |
9338 | ||
fbcfacb7 | 9339 | mips_emit_delays (false); |
670a50eb ILT |
9340 | switch (sec) |
9341 | { | |
3d3c5039 | 9342 | case 't': |
604633ae | 9343 | s_text (0); |
670a50eb | 9344 | break; |
3d3c5039 | 9345 | case 'd': |
604633ae | 9346 | s_data (0); |
670a50eb | 9347 | break; |
3d3c5039 | 9348 | case 'b': |
670a50eb | 9349 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
9350 | demand_empty_rest_of_line (); |
9351 | break; | |
88225433 ILT |
9352 | |
9353 | case 'r': | |
1dc1e798 KR |
9354 | if (USE_GLOBAL_POINTER_OPT) |
9355 | { | |
9356 | seg = subseg_new (RDATA_SECTION_NAME, | |
9357 | (subsegT) get_absolute_expression ()); | |
9358 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9359 | { | |
9360 | bfd_set_section_flags (stdoutput, seg, | |
9361 | (SEC_ALLOC | |
9362 | | SEC_LOAD | |
9363 | | SEC_READONLY | |
9364 | | SEC_RELOC | |
9365 | | SEC_DATA)); | |
08e17202 ILT |
9366 | if (strcmp (TARGET_OS, "elf") != 0) |
9367 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9368 | } |
9369 | demand_empty_rest_of_line (); | |
9370 | } | |
9371 | else | |
9372 | { | |
9373 | as_bad ("No read only data section in this object file format"); | |
9374 | demand_empty_rest_of_line (); | |
9375 | return; | |
9376 | } | |
88225433 | 9377 | break; |
88225433 ILT |
9378 | |
9379 | case 's': | |
1dc1e798 KR |
9380 | if (USE_GLOBAL_POINTER_OPT) |
9381 | { | |
9382 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9383 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9384 | { | |
9385 | bfd_set_section_flags (stdoutput, seg, | |
9386 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9387 | | SEC_DATA); | |
08e17202 ILT |
9388 | if (strcmp (TARGET_OS, "elf") != 0) |
9389 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9390 | } |
9391 | demand_empty_rest_of_line (); | |
9392 | break; | |
9393 | } | |
9394 | else | |
9395 | { | |
9396 | as_bad ("Global pointers not supported; recompile -G 0"); | |
9397 | demand_empty_rest_of_line (); | |
9398 | return; | |
9399 | } | |
3d3c5039 | 9400 | } |
88225433 | 9401 | |
670a50eb | 9402 | auto_align = 1; |
3d3c5039 ILT |
9403 | } |
9404 | ||
739708fa KR |
9405 | void |
9406 | mips_enable_auto_align () | |
9da4c5d1 | 9407 | { |
9da4c5d1 ILT |
9408 | auto_align = 1; |
9409 | } | |
9410 | ||
3d3c5039 ILT |
9411 | static void |
9412 | s_cons (log_size) | |
9413 | int log_size; | |
9414 | { | |
23dc1ae3 ILT |
9415 | symbolS *label; |
9416 | ||
fbcfacb7 ILT |
9417 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9418 | mips_emit_delays (false); | |
670a50eb | 9419 | if (log_size > 0 && auto_align) |
23dc1ae3 | 9420 | mips_align (log_size, 0, label); |
fbcfacb7 | 9421 | mips_clear_insn_labels (); |
670a50eb | 9422 | cons (1 << log_size); |
3d3c5039 ILT |
9423 | } |
9424 | ||
3d3c5039 | 9425 | static void |
becfe05e ILT |
9426 | s_float_cons (type) |
9427 | int type; | |
3d3c5039 | 9428 | { |
23dc1ae3 ILT |
9429 | symbolS *label; |
9430 | ||
fbcfacb7 | 9431 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 9432 | |
fbcfacb7 | 9433 | mips_emit_delays (false); |
670a50eb ILT |
9434 | |
9435 | if (auto_align) | |
becfe05e | 9436 | if (type == 'd') |
23dc1ae3 | 9437 | mips_align (3, 0, label); |
670a50eb | 9438 | else |
23dc1ae3 | 9439 | mips_align (2, 0, label); |
670a50eb | 9440 | |
fbcfacb7 | 9441 | mips_clear_insn_labels (); |
1849d646 | 9442 | |
becfe05e | 9443 | float_cons (type); |
3d3c5039 ILT |
9444 | } |
9445 | ||
c1444ec4 ILT |
9446 | /* Handle .globl. We need to override it because on Irix 5 you are |
9447 | permitted to say | |
9448 | .globl foo .text | |
9449 | where foo is an undefined symbol, to mean that foo should be | |
9450 | considered to be the address of a function. */ | |
9451 | ||
9452 | static void | |
9453 | s_mips_globl (x) | |
9454 | int x; | |
9455 | { | |
9456 | char *name; | |
9457 | int c; | |
9458 | symbolS *symbolP; | |
fb251650 | 9459 | flagword flag; |
c1444ec4 ILT |
9460 | |
9461 | name = input_line_pointer; | |
9462 | c = get_symbol_end (); | |
9463 | symbolP = symbol_find_or_make (name); | |
9464 | *input_line_pointer = c; | |
9465 | SKIP_WHITESPACE (); | |
fb251650 ILT |
9466 | |
9467 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
9468 | being a function is apparently labelled as being an object. */ | |
9469 | flag = BSF_OBJECT; | |
9470 | ||
c1444ec4 ILT |
9471 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
9472 | { | |
9473 | char *secname; | |
9474 | asection *sec; | |
9475 | ||
9476 | secname = input_line_pointer; | |
9477 | c = get_symbol_end (); | |
9478 | sec = bfd_get_section_by_name (stdoutput, secname); | |
9479 | if (sec == NULL) | |
9480 | as_bad ("%s: no such section", secname); | |
9481 | *input_line_pointer = c; | |
9482 | ||
9483 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 9484 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
9485 | } |
9486 | ||
fb251650 ILT |
9487 | symbolP->bsym->flags |= flag; |
9488 | ||
c1444ec4 ILT |
9489 | S_SET_EXTERNAL (symbolP); |
9490 | demand_empty_rest_of_line (); | |
9491 | } | |
9492 | ||
3d3c5039 ILT |
9493 | static void |
9494 | s_option (x) | |
9495 | int x; | |
9496 | { | |
dd3f1f76 ILT |
9497 | char *opt; |
9498 | char c; | |
9499 | ||
9500 | opt = input_line_pointer; | |
9501 | c = get_symbol_end (); | |
9502 | ||
dd3f1f76 | 9503 | if (*opt == 'O') |
9226253a ILT |
9504 | { |
9505 | /* FIXME: What does this mean? */ | |
9506 | } | |
dd3f1f76 | 9507 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 9508 | { |
d9aba805 | 9509 | int i; |
42562568 | 9510 | |
d9aba805 ILT |
9511 | i = atoi (opt + 3); |
9512 | if (i == 0) | |
9513 | mips_pic = NO_PIC; | |
9514 | else if (i == 2) | |
9515 | mips_pic = SVR4_PIC; | |
9516 | else | |
9517 | as_bad (".option pic%d not supported", i); | |
9518 | ||
1dc1e798 | 9519 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
9520 | { |
9521 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 9522 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
9523 | g_switch_value = 0; |
9524 | bfd_set_gp_size (stdoutput, 0); | |
9525 | } | |
9226253a | 9526 | } |
dd3f1f76 ILT |
9527 | else |
9528 | as_warn ("Unrecognized option \"%s\"", opt); | |
9529 | ||
9530 | *input_line_pointer = c; | |
670a50eb | 9531 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9532 | } |
9533 | ||
3c83da8a JW |
9534 | /* This structure is used to hold a stack of .set values. */ |
9535 | ||
9536 | struct mips_option_stack | |
9537 | { | |
9538 | struct mips_option_stack *next; | |
9539 | struct mips_set_options options; | |
9540 | }; | |
9541 | ||
9542 | static struct mips_option_stack *mips_opts_stack; | |
9543 | ||
9544 | /* Handle the .set pseudo-op. */ | |
9545 | ||
3d3c5039 ILT |
9546 | static void |
9547 | s_mipsset (x) | |
9548 | int x; | |
9549 | { | |
670a50eb ILT |
9550 | char *name = input_line_pointer, ch; |
9551 | ||
9552 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
9553 | input_line_pointer++; | |
9554 | ch = *input_line_pointer; | |
9555 | *input_line_pointer = '\0'; | |
9556 | ||
9557 | if (strcmp (name, "reorder") == 0) | |
9558 | { | |
3c83da8a | 9559 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 9560 | { |
4a1cb507 ILT |
9561 | /* If we still have pending nops, we can discard them. The |
9562 | usual nop handling will insert any that are still | |
9563 | needed. */ | |
3c83da8a JW |
9564 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
9565 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 9566 | prev_nop_frag = NULL; |
4e95866e | 9567 | } |
3c83da8a | 9568 | mips_opts.noreorder = 0; |
670a50eb ILT |
9569 | } |
9570 | else if (strcmp (name, "noreorder") == 0) | |
9571 | { | |
fbcfacb7 | 9572 | mips_emit_delays (true); |
3c83da8a | 9573 | mips_opts.noreorder = 1; |
0dd2d296 | 9574 | mips_any_noreorder = 1; |
670a50eb ILT |
9575 | } |
9576 | else if (strcmp (name, "at") == 0) | |
9577 | { | |
3c83da8a | 9578 | mips_opts.noat = 0; |
670a50eb ILT |
9579 | } |
9580 | else if (strcmp (name, "noat") == 0) | |
9581 | { | |
3c83da8a | 9582 | mips_opts.noat = 1; |
3d3c5039 | 9583 | } |
670a50eb ILT |
9584 | else if (strcmp (name, "macro") == 0) |
9585 | { | |
3c83da8a | 9586 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
9587 | } |
9588 | else if (strcmp (name, "nomacro") == 0) | |
9589 | { | |
3c83da8a | 9590 | if (mips_opts.noreorder == 0) |
670a50eb | 9591 | as_bad ("`noreorder' must be set before `nomacro'"); |
3c83da8a | 9592 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
9593 | } |
9594 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
9595 | { | |
3c83da8a | 9596 | mips_opts.nomove = 0; |
670a50eb ILT |
9597 | } |
9598 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
9599 | { | |
3c83da8a | 9600 | mips_opts.nomove = 1; |
670a50eb ILT |
9601 | } |
9602 | else if (strcmp (name, "bopt") == 0) | |
9603 | { | |
3c83da8a | 9604 | mips_opts.nobopt = 0; |
670a50eb ILT |
9605 | } |
9606 | else if (strcmp (name, "nobopt") == 0) | |
9607 | { | |
3c83da8a | 9608 | mips_opts.nobopt = 1; |
670a50eb | 9609 | } |
943321c0 ILT |
9610 | else if (strcmp (name, "mips16") == 0 |
9611 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 9612 | mips_opts.mips16 = 1; |
943321c0 ILT |
9613 | else if (strcmp (name, "nomips16") == 0 |
9614 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 9615 | mips_opts.mips16 = 0; |
1051c97f ILT |
9616 | else if (strncmp (name, "mips", 4) == 0) |
9617 | { | |
9618 | int isa; | |
9619 | ||
9620 | /* Permit the user to change the ISA on the fly. Needless to | |
9621 | say, misuse can cause serious problems. */ | |
9622 | isa = atoi (name + 4); | |
9623 | if (isa == 0) | |
3c83da8a | 9624 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 9625 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
9626 | as_bad ("unknown ISA level"); |
9627 | else | |
3c83da8a | 9628 | mips_opts.isa = isa; |
1051c97f | 9629 | } |
cc5703cd | 9630 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 9631 | mips_opts.noautoextend = 0; |
cc5703cd | 9632 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
9633 | mips_opts.noautoextend = 1; |
9634 | else if (strcmp (name, "push") == 0) | |
9635 | { | |
9636 | struct mips_option_stack *s; | |
9637 | ||
9638 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
9639 | s->next = mips_opts_stack; | |
9640 | s->options = mips_opts; | |
9641 | mips_opts_stack = s; | |
9642 | } | |
9643 | else if (strcmp (name, "pop") == 0) | |
9644 | { | |
9645 | struct mips_option_stack *s; | |
9646 | ||
9647 | s = mips_opts_stack; | |
9648 | if (s == NULL) | |
9649 | as_bad (".set pop with no .set push"); | |
9650 | else | |
9651 | { | |
9652 | /* If we're changing the reorder mode we need to handle | |
9653 | delay slots correctly. */ | |
9654 | if (s->options.noreorder && ! mips_opts.noreorder) | |
9655 | mips_emit_delays (true); | |
9656 | else if (! s->options.noreorder && mips_opts.noreorder) | |
9657 | { | |
9658 | if (prev_nop_frag != NULL) | |
9659 | { | |
9660 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
9661 | * (mips_opts.mips16 ? 2 : 4)); | |
9662 | prev_nop_frag = NULL; | |
9663 | } | |
9664 | } | |
9665 | ||
9666 | mips_opts = s->options; | |
9667 | mips_opts_stack = s->next; | |
9668 | free (s); | |
9669 | } | |
9670 | } | |
670a50eb ILT |
9671 | else |
9672 | { | |
9673 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
9674 | } | |
9675 | *input_line_pointer = ch; | |
9676 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
9677 | } |
9678 | ||
9226253a ILT |
9679 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
9680 | .option pic2. It means to generate SVR4 PIC calls. */ | |
9681 | ||
9682 | static void | |
9683 | s_abicalls (ignore) | |
9684 | int ignore; | |
9685 | { | |
d9aba805 | 9686 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
9687 | if (USE_GLOBAL_POINTER_OPT) |
9688 | { | |
9689 | if (g_switch_seen && g_switch_value != 0) | |
9690 | as_warn ("-G may not be used with SVR4 PIC code"); | |
9691 | g_switch_value = 0; | |
9692 | } | |
d9aba805 | 9693 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
9694 | demand_empty_rest_of_line (); |
9695 | } | |
9696 | ||
9697 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
9698 | PIC code. It sets the $gp register for the function based on the | |
9699 | function address, which is in the register named in the argument. | |
9700 | This uses a relocation against _gp_disp, which is handled specially | |
9701 | by the linker. The result is: | |
9702 | lui $gp,%hi(_gp_disp) | |
9703 | addiu $gp,$gp,%lo(_gp_disp) | |
9704 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 9705 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
9706 | |
9707 | static void | |
9708 | s_cpload (ignore) | |
9709 | int ignore; | |
9710 | { | |
9711 | expressionS ex; | |
9712 | int icnt = 0; | |
9713 | ||
d9aba805 ILT |
9714 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
9715 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9716 | { |
9717 | s_ignore (0); | |
9718 | return; | |
9719 | } | |
9720 | ||
9721 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 9722 | if (mips_opts.noreorder == 0) |
0dd2d296 ILT |
9723 | as_warn (".cpload not in noreorder section"); |
9724 | ||
9226253a ILT |
9725 | ex.X_op = O_symbol; |
9726 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
9727 | ex.X_op_symbol = NULL; | |
9728 | ex.X_add_number = 0; | |
9729 | ||
fb251650 ILT |
9730 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
9731 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
9732 | ||
0dd2d296 ILT |
9733 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
9734 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
9735 | (int) BFD_RELOC_LO16); |
9736 | ||
0dd2d296 ILT |
9737 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
9738 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
9739 | |
9740 | demand_empty_rest_of_line (); | |
9741 | } | |
9742 | ||
9743 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
9744 | offset from $sp. The offset is remembered, and after making a PIC | |
9745 | call $gp is restored from that location. */ | |
9746 | ||
9747 | static void | |
9748 | s_cprestore (ignore) | |
9749 | int ignore; | |
9750 | { | |
9751 | expressionS ex; | |
9752 | int icnt = 0; | |
9753 | ||
d9aba805 ILT |
9754 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
9755 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9756 | { |
9757 | s_ignore (0); | |
9758 | return; | |
9759 | } | |
9760 | ||
9226253a ILT |
9761 | mips_cprestore_offset = get_absolute_expression (); |
9762 | ||
9763 | ex.X_op = O_constant; | |
9764 | ex.X_add_symbol = NULL; | |
9765 | ex.X_op_symbol = NULL; | |
9766 | ex.X_add_number = mips_cprestore_offset; | |
9767 | ||
0dd2d296 | 9768 | macro_build ((char *) NULL, &icnt, &ex, |
3c83da8a | 9769 | mips_opts.isa < 3 ? "sw" : "sd", |
9226253a ILT |
9770 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
9771 | ||
9772 | demand_empty_rest_of_line (); | |
9773 | } | |
9774 | ||
0dd2d296 ILT |
9775 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
9776 | code. It generates a 32 bit GP relative reloc. */ | |
9777 | ||
9778 | static void | |
9779 | s_gpword (ignore) | |
9780 | int ignore; | |
9781 | { | |
23dc1ae3 | 9782 | symbolS *label; |
0dd2d296 ILT |
9783 | expressionS ex; |
9784 | char *p; | |
9785 | ||
9786 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 9787 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9788 | { |
9789 | s_cons (2); | |
9790 | return; | |
9791 | } | |
9792 | ||
fbcfacb7 ILT |
9793 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9794 | mips_emit_delays (true); | |
0dd2d296 | 9795 | if (auto_align) |
23dc1ae3 | 9796 | mips_align (2, 0, label); |
fbcfacb7 | 9797 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9798 | |
9799 | expression (&ex); | |
9800 | ||
9801 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9802 | { | |
9803 | as_bad ("Unsupported use of .gpword"); | |
9804 | ignore_rest_of_line (); | |
9805 | } | |
9806 | ||
9807 | p = frag_more (4); | |
9808 | md_number_to_chars (p, (valueT) 0, 4); | |
9809 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9810 | BFD_RELOC_MIPS_GPREL32); | |
9811 | ||
9812 | demand_empty_rest_of_line (); | |
9813 | } | |
9814 | ||
9815 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9816 | tables in SVR4 PIC code. */ | |
9817 | ||
9818 | static void | |
9819 | s_cpadd (ignore) | |
9820 | int ignore; | |
9821 | { | |
9822 | int icnt = 0; | |
9823 | int reg; | |
9824 | ||
9825 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9826 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9827 | { |
9828 | s_ignore (0); | |
9829 | return; | |
9830 | } | |
9831 | ||
9832 | /* Add $gp to the register named as an argument. */ | |
9833 | reg = tc_get_register (0); | |
9834 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 9835 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
9836 | "d,v,t", reg, reg, GP); |
9837 | ||
9838 | demand_empty_rest_of_line (); | |
9839 | } | |
9840 | ||
ed3eb786 ILT |
9841 | /* Handle the .insn pseudo-op. This marks instruction labels in |
9842 | mips16 mode. This permits the linker to handle them specially, | |
9843 | such as generating jalx instructions when needed. We also make | |
9844 | them odd for the duration of the assembly, in order to generate the | |
9845 | right sort of code. We will make them even in the adjust_symtab | |
9846 | routine, while leaving them marked. This is convenient for the | |
9847 | debugger and the disassembler. The linker knows to make them odd | |
9848 | again. */ | |
9849 | ||
9850 | static void | |
9851 | s_insn (ignore) | |
9852 | int ignore; | |
9853 | { | |
3c83da8a JW |
9854 | if (mips_opts.mips16) |
9855 | mips16_mark_labels (); | |
ed3eb786 | 9856 | |
3c83da8a JW |
9857 | demand_empty_rest_of_line (); |
9858 | } | |
ed3eb786 | 9859 | |
3c83da8a JW |
9860 | /* Handle a .stabn directive. We need these in order to mark a label |
9861 | as being a mips16 text label correctly. Sometimes the compiler | |
9862 | will emit a label, followed by a .stabn, and then switch sections. | |
9863 | If the label and .stabn are in mips16 mode, then the label is | |
9864 | really a mips16 text label. */ | |
ed3eb786 | 9865 | |
3c83da8a JW |
9866 | static void |
9867 | s_mips_stab (type) | |
9868 | int type; | |
9869 | { | |
9870 | if (type == 'n' && mips_opts.mips16) | |
9871 | mips16_mark_labels (); | |
9872 | ||
9873 | s_stab (type); | |
ed3eb786 ILT |
9874 | } |
9875 | ||
9226253a | 9876 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9877 | to parse .frame. The argument is non-zero if this is the frame |
9878 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9879 | |
3d3c5039 | 9880 | int |
0dd2d296 ILT |
9881 | tc_get_register (frame) |
9882 | int frame; | |
3d3c5039 ILT |
9883 | { |
9884 | int reg; | |
9885 | ||
9886 | SKIP_WHITESPACE (); | |
9887 | if (*input_line_pointer++ != '$') | |
9888 | { | |
9889 | as_warn ("expected `$'"); | |
0dd2d296 | 9890 | reg = 0; |
3d3c5039 | 9891 | } |
0dd2d296 | 9892 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9893 | { |
9894 | reg = get_absolute_expression (); | |
9895 | if (reg < 0 || reg >= 32) | |
9896 | { | |
9897 | as_warn ("Bad register number"); | |
9898 | reg = 0; | |
9899 | } | |
9900 | } | |
9901 | else | |
9902 | { | |
9903 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9904 | reg = FP; |
3d3c5039 | 9905 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9906 | reg = SP; |
3d3c5039 | 9907 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9908 | reg = GP; |
3d3c5039 | 9909 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9910 | reg = AT; |
3d3c5039 ILT |
9911 | else |
9912 | { | |
9913 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9914 | reg = 0; |
3d3c5039 ILT |
9915 | } |
9916 | input_line_pointer += 2; | |
9917 | } | |
0dd2d296 ILT |
9918 | if (frame) |
9919 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9920 | return reg; |
9921 | } | |
9922 | ||
0dd2d296 ILT |
9923 | valueT |
9924 | md_section_align (seg, addr) | |
9925 | asection *seg; | |
9926 | valueT addr; | |
9927 | { | |
9928 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9929 | ||
cf32394d ILT |
9930 | #ifdef OBJ_ELF |
9931 | /* We don't need to align ELF sections to the full alignment. | |
9932 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9933 | byte boundary. We don't bother to align the sections if we are |
9934 | targeted for an embedded system. */ | |
9935 | if (strcmp (TARGET_OS, "elf") == 0) | |
9936 | return addr; | |
943321c0 ILT |
9937 | if (align > 4) |
9938 | align = 4; | |
10a14e36 | 9939 | #endif |
cf32394d ILT |
9940 | |
9941 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9942 | } |
9943 | ||
d8a1c247 KR |
9944 | /* Utility routine, called from above as well. If called while the |
9945 | input file is still being read, it's only an approximation. (For | |
9946 | example, a symbol may later become defined which appeared to be | |
9947 | undefined earlier.) */ | |
22ba90ce ILT |
9948 | |
9949 | static int | |
85ce5635 | 9950 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 9951 | symbolS *sym; |
85ce5635 | 9952 | int before_relaxing; |
d8a1c247 KR |
9953 | { |
9954 | if (sym == 0) | |
9955 | return 0; | |
9956 | ||
1dc1e798 KR |
9957 | if (USE_GLOBAL_POINTER_OPT) |
9958 | { | |
9959 | const char *symname; | |
9960 | int change; | |
9961 | ||
9962 | /* Find out whether this symbol can be referenced off the GP | |
9963 | register. It can be if it is smaller than the -G size or if | |
9964 | it is in the .sdata or .sbss section. Certain symbols can | |
9965 | not be referenced off the GP, although it appears as though | |
9966 | they can. */ | |
9967 | symname = S_GET_NAME (sym); | |
9968 | if (symname != (const char *) NULL | |
9969 | && (strcmp (symname, "eprol") == 0 | |
9970 | || strcmp (symname, "etext") == 0 | |
9971 | || strcmp (symname, "_gp") == 0 | |
9972 | || strcmp (symname, "edata") == 0 | |
9973 | || strcmp (symname, "_fbss") == 0 | |
9974 | || strcmp (symname, "_fdata") == 0 | |
9975 | || strcmp (symname, "_ftext") == 0 | |
9976 | || strcmp (symname, "end") == 0 | |
9977 | || strcmp (symname, "_gp_disp") == 0)) | |
9978 | change = 1; | |
23ac3ca1 | 9979 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
9980 | && (0 |
9981 | #ifndef NO_ECOFF_DEBUGGING | |
9982 | || (sym->ecoff_extern_size != 0 | |
9983 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 9984 | #endif |
85ce5635 ILT |
9985 | /* We must defer this decision until after the whole |
9986 | file has been read, since there might be a .extern | |
9987 | after the first use of this symbol. */ | |
a5586bdc ILT |
9988 | || (before_relaxing |
9989 | #ifndef NO_ECOFF_DEBUGGING | |
9990 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 9991 | #endif |
a5586bdc | 9992 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
9993 | || (S_GET_VALUE (sym) != 0 |
9994 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9995 | change = 0; | |
9996 | else | |
9997 | { | |
9998 | const char *segname; | |
d8a1c247 | 9999 | |
1dc1e798 KR |
10000 | segname = segment_name (S_GET_SEGMENT (sym)); |
10001 | assert (strcmp (segname, ".lit8") != 0 | |
10002 | && strcmp (segname, ".lit4") != 0); | |
10003 | change = (strcmp (segname, ".sdata") != 0 | |
10004 | && strcmp (segname, ".sbss") != 0); | |
10005 | } | |
10006 | return change; | |
10007 | } | |
10008 | else | |
10009 | /* We are not optimizing for the GP register. */ | |
10010 | return 1; | |
d8a1c247 KR |
10011 | } |
10012 | ||
cc5703cd ILT |
10013 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
10014 | extended opcode. SEC is the section the frag is in. */ | |
10015 | ||
10016 | static int | |
10017 | mips16_extended_frag (fragp, sec, stretch) | |
10018 | fragS *fragp; | |
10019 | asection *sec; | |
10020 | long stretch; | |
10021 | { | |
10022 | int type; | |
10023 | register const struct mips16_immed_operand *op; | |
10024 | offsetT val; | |
10025 | int mintiny, maxtiny; | |
f74ba7a3 | 10026 | segT symsec; |
cc5703cd | 10027 | |
8728fa92 ILT |
10028 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
10029 | return 0; | |
10030 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10031 | return 1; | |
10032 | ||
cc5703cd ILT |
10033 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
10034 | op = mips16_immed_operands; | |
10035 | while (op->type != type) | |
10036 | { | |
10037 | ++op; | |
10038 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10039 | } | |
10040 | ||
10041 | if (op->unsp) | |
10042 | { | |
10043 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10044 | { | |
10045 | mintiny = 1; | |
10046 | maxtiny = 1 << op->nbits; | |
10047 | } | |
10048 | else | |
10049 | { | |
10050 | mintiny = 0; | |
10051 | maxtiny = (1 << op->nbits) - 1; | |
10052 | } | |
10053 | } | |
10054 | else | |
10055 | { | |
10056 | mintiny = - (1 << (op->nbits - 1)); | |
10057 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10058 | } | |
10059 | ||
f74ba7a3 ILT |
10060 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
10061 | a particular frag address. */ | |
10062 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
10063 | { | |
10064 | val = (fragp->fr_symbol->sy_value.X_add_number | |
10065 | + fragp->fr_symbol->sy_frag->fr_address); | |
10066 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
10067 | } | |
10068 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
10069 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
10070 | == O_constant)) | |
10071 | { | |
10072 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
10073 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
10074 | + fragp->fr_symbol->sy_value.X_add_number | |
10075 | + fragp->fr_symbol->sy_frag->fr_address); | |
10076 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
10077 | } | |
10078 | else | |
10079 | return 1; | |
cc5703cd ILT |
10080 | |
10081 | if (op->pcrel) | |
10082 | { | |
10083 | addressT addr; | |
10084 | ||
10085 | /* We won't have the section when we are called from | |
10086 | mips_relax_frag. However, we will always have been called | |
10087 | from md_estimate_size_before_relax first. If this is a | |
10088 | branch to a different section, we mark it as such. If SEC is | |
10089 | NULL, and the frag is not marked, then it must be a branch to | |
10090 | the same section. */ | |
10091 | if (sec == NULL) | |
10092 | { | |
10093 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10094 | return 1; | |
10095 | } | |
10096 | else | |
10097 | { | |
f74ba7a3 | 10098 | if (symsec != sec) |
cc5703cd ILT |
10099 | { |
10100 | fragp->fr_subtype = | |
10101 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10102 | ||
10103 | /* FIXME: We should support this, and let the linker | |
10104 | catch branches and loads that are out of range. */ | |
10105 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10106 | "unsupported PC relative reference to different section"); | |
10107 | ||
10108 | return 1; | |
10109 | } | |
10110 | } | |
10111 | ||
10112 | /* In this case, we know for sure that the symbol fragment is in | |
10113 | the same section. If the fr_address of the symbol fragment | |
10114 | is greater then the address of this fragment we want to add | |
10115 | in STRETCH in order to get a better estimate of the address. | |
10116 | This particularly matters because of the shift bits. */ | |
10117 | if (stretch != 0 | |
10118 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
10119 | { | |
10120 | fragS *f; | |
10121 | ||
a941619c ILT |
10122 | /* Adjust stretch for any alignment frag. Note that if have |
10123 | been expanding the earlier code, the symbol may be | |
10124 | defined in what appears to be an earlier frag. FIXME: | |
10125 | This doesn't handle the fr_subtype field, which specifies | |
10126 | a maximum number of bytes to skip when doing an | |
10127 | alignment. */ | |
10128 | for (f = fragp; | |
10129 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
10130 | f = f->fr_next) | |
cc5703cd | 10131 | { |
cc5703cd ILT |
10132 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
10133 | { | |
10134 | if (stretch < 0) | |
10135 | stretch = - ((- stretch) | |
10136 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10137 | else | |
10138 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10139 | if (stretch == 0) | |
10140 | break; | |
10141 | } | |
10142 | } | |
a941619c ILT |
10143 | if (f != NULL) |
10144 | val += stretch; | |
cc5703cd ILT |
10145 | } |
10146 | ||
a677feeb ILT |
10147 | addr = fragp->fr_address + fragp->fr_fix; |
10148 | ||
10149 | /* The base address rules are complicated. The base address of | |
10150 | a branch is the following instruction. The base address of a | |
10151 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
10152 | is in a delay slot (in which case it can not be extended) use |
10153 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 10154 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
10155 | { |
10156 | addr += 2; | |
319305a7 ILT |
10157 | |
10158 | /* If we are currently assuming that this frag should be | |
10159 | extended, then, the current address is two bytes | |
10160 | higher. */ | |
10161 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10162 | addr += 2; | |
10163 | ||
fbcfacb7 ILT |
10164 | /* Ignore the low bit in the target, since it will be set |
10165 | for a text label. */ | |
10166 | if ((val & 1) != 0) | |
10167 | --val; | |
10168 | } | |
a677feeb ILT |
10169 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10170 | addr -= 4; | |
10171 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10172 | addr -= 2; | |
cc5703cd | 10173 | |
cc5703cd ILT |
10174 | val -= addr & ~ ((1 << op->shift) - 1); |
10175 | ||
10176 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10177 | if (type == 'p' || type == 'q') | |
10178 | val /= 2; | |
10179 | ||
10180 | /* If any of the shifted bits are set, we must use an extended | |
10181 | opcode. If the address depends on the size of this | |
10182 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
10183 | use an extended opcode. We only check this when we are in |
10184 | the main relaxation loop, when SEC is NULL. */ | |
10185 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10186 | { | |
10187 | fragp->fr_subtype = | |
10188 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10189 | return 1; | |
10190 | } | |
10191 | ||
10192 | /* If we are about to mark a frag as extended because the value | |
10193 | is precisely maxtiny + 1, then there is a chance of an | |
10194 | infinite loop as in the following code: | |
10195 | la $4,foo | |
10196 | .skip 1020 | |
10197 | .align 2 | |
10198 | foo: | |
10199 | In this case when the la is extended, foo is 0x3fc bytes | |
10200 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10201 | the la must be extended. To avoid this loop, we mark the | |
10202 | frag as extended if it was small, and is about to become | |
10203 | extended with a value of maxtiny + 1. */ | |
10204 | if (val == ((maxtiny + 1) << op->shift) | |
10205 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10206 | && sec == NULL) | |
cc5703cd ILT |
10207 | { |
10208 | fragp->fr_subtype = | |
10209 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10210 | return 1; | |
10211 | } | |
10212 | } | |
41a0ed22 ILT |
10213 | else if (symsec != absolute_section && sec != NULL) |
10214 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
10215 | |
10216 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10217 | || val < (mintiny << op->shift) | |
10218 | || val > (maxtiny << op->shift)) | |
10219 | return 1; | |
10220 | else | |
10221 | return 0; | |
10222 | } | |
10223 | ||
10224 | /* Estimate the size of a frag before relaxing. Unless this is the | |
10225 | mips16, we are not really relaxing here, and the final size is | |
10226 | encoded in the subtype information. For the mips16, we have to | |
10227 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 10228 | |
0dd2d296 ILT |
10229 | /*ARGSUSED*/ |
10230 | int | |
10231 | md_estimate_size_before_relax (fragp, segtype) | |
10232 | fragS *fragp; | |
10233 | asection *segtype; | |
10234 | { | |
10235 | int change; | |
10236 | ||
cc5703cd ILT |
10237 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10238 | { | |
10239 | if (mips16_extended_frag (fragp, segtype, 0)) | |
10240 | { | |
10241 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10242 | return 4; | |
10243 | } | |
10244 | else | |
10245 | { | |
10246 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10247 | return 2; | |
10248 | } | |
10249 | } | |
10250 | ||
d9aba805 | 10251 | if (mips_pic == NO_PIC) |
0dd2d296 | 10252 | { |
85ce5635 | 10253 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 10254 | } |
d9aba805 | 10255 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10256 | { |
46a92fde ILT |
10257 | symbolS *sym; |
10258 | asection *symsec; | |
10259 | ||
10260 | sym = fragp->fr_symbol; | |
10261 | ||
10262 | /* Handle the case of a symbol equated to another symbol. */ | |
10263 | while (sym->sy_value.X_op == O_symbol | |
10264 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
10265 | { | |
10266 | symbolS *n; | |
10267 | ||
10268 | /* It's possible to get a loop here in a badly written | |
10269 | program. */ | |
10270 | n = sym->sy_value.X_add_symbol; | |
10271 | if (n == sym) | |
10272 | break; | |
10273 | sym = n; | |
10274 | } | |
10275 | ||
10276 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
10277 | |
10278 | /* This must duplicate the test in adjust_reloc_syms. */ | |
10279 | change = (symsec != &bfd_und_section | |
10280 | && symsec != &bfd_abs_section | |
10281 | && ! bfd_is_com_section (symsec)); | |
10282 | } | |
d9aba805 ILT |
10283 | else |
10284 | abort (); | |
0dd2d296 ILT |
10285 | |
10286 | if (change) | |
10287 | { | |
10288 | /* Record the offset to the first reloc in the fr_opcode field. | |
10289 | This lets md_convert_frag and tc_gen_reloc know that the code | |
10290 | must be expanded. */ | |
10291 | fragp->fr_opcode = (fragp->fr_literal | |
10292 | + fragp->fr_fix | |
10293 | - RELAX_OLD (fragp->fr_subtype) | |
10294 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
10295 | /* FIXME: This really needs as_warn_where. */ | |
10296 | if (RELAX_WARN (fragp->fr_subtype)) | |
10297 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
10298 | } | |
10299 | ||
10300 | if (! change) | |
10301 | return 0; | |
10302 | else | |
10303 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
10304 | } | |
10305 | ||
0d7f9025 ILT |
10306 | /* This is called to see whether a reloc against a defined symbol |
10307 | should be converted into a reloc against a section. Don't adjust | |
10308 | MIPS16 jump relocations, so we don't have to worry about the format | |
10309 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
10310 | mips16 symbols, so that the linker can find them if it needs to set |
10311 | up a stub. */ | |
0d7f9025 ILT |
10312 | |
10313 | int | |
10314 | mips_fix_adjustable (fixp) | |
10315 | fixS *fixp; | |
10316 | { | |
10317 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
10318 | return 0; | |
10319 | if (fixp->fx_addsy == NULL) | |
10320 | return 1; | |
68952421 | 10321 | #ifdef OBJ_ELF |
0d7f9025 | 10322 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
10323 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
10324 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
10325 | return 0; |
10326 | #endif | |
10327 | return 1; | |
10328 | } | |
10329 | ||
0dd2d296 ILT |
10330 | /* Translate internal representation of relocation info to BFD target |
10331 | format. */ | |
10332 | ||
10333 | arelent ** | |
3d3c5039 ILT |
10334 | tc_gen_reloc (section, fixp) |
10335 | asection *section; | |
10336 | fixS *fixp; | |
10337 | { | |
0dd2d296 | 10338 | static arelent *retval[4]; |
3d3c5039 | 10339 | arelent *reloc; |
a8aed9dd | 10340 | bfd_reloc_code_real_type code; |
3d3c5039 | 10341 | |
0dd2d296 ILT |
10342 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
10343 | retval[1] = NULL; | |
3d3c5039 ILT |
10344 | |
10345 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10346 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
10347 | |
10348 | if (mips_pic == EMBEDDED_PIC | |
10349 | && SWITCH_TABLE (fixp)) | |
10350 | { | |
10351 | /* For a switch table entry we use a special reloc. The addend | |
10352 | is actually the difference between the reloc address and the | |
10353 | subtrahend. */ | |
10354 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
10355 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
10356 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
10357 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
10358 | } | |
ecd4ca1c ILT |
10359 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
10360 | { | |
10361 | /* We use a special addend for an internal RELLO reloc. */ | |
10362 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10363 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
10364 | else | |
10365 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
10366 | } | |
10367 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
10368 | { | |
10369 | assert (fixp->fx_next != NULL | |
10370 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
10371 | /* We use a special addend for an internal RELHI reloc. The | |
10372 | reloc is relative to the RELLO; adjust the addend | |
10373 | accordingly. */ | |
10374 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10375 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
10376 | + fixp->fx_next->fx_where | |
10377 | - S_GET_VALUE (fixp->fx_subsy)); | |
10378 | else | |
10379 | reloc->addend = (fixp->fx_addnumber | |
10380 | + fixp->fx_next->fx_frag->fr_address | |
10381 | + fixp->fx_next->fx_where); | |
10382 | } | |
1c803e52 | 10383 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
10384 | reloc->addend = fixp->fx_addnumber; |
10385 | else | |
5b63f465 | 10386 | { |
1dc1e798 KR |
10387 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
10388 | /* A gruesome hack which is a result of the gruesome gas reloc | |
10389 | handling. */ | |
10390 | reloc->addend = reloc->address; | |
10391 | else | |
10392 | reloc->addend = -reloc->address; | |
5b63f465 | 10393 | } |
0dd2d296 ILT |
10394 | |
10395 | /* If this is a variant frag, we may need to adjust the existing | |
10396 | reloc and generate a new one. */ | |
10397 | if (fixp->fx_frag->fr_opcode != NULL | |
10398 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
10399 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
10400 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
10401 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10402 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
10403 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10404 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
10405 | { |
10406 | arelent *reloc2; | |
10407 | ||
cc5703cd ILT |
10408 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
10409 | ||
0dd2d296 | 10410 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
10411 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
10412 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
10413 | the second one handle all of them. */ | |
0dd2d296 ILT |
10414 | if (fixp->fx_next != NULL |
10415 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
10416 | { | |
fb251650 ILT |
10417 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
10418 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
10419 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10420 | && (fixp->fx_next->fx_r_type | |
10421 | == BFD_RELOC_MIPS_GOT_LO16)) | |
10422 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10423 | && (fixp->fx_next->fx_r_type | |
10424 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
10425 | retval[0] = NULL; |
10426 | return retval; | |
10427 | } | |
10428 | ||
10429 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
10430 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10431 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
10432 | retval[2] = NULL; | |
10433 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10434 | reloc2->address = (reloc->address | |
10435 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
10436 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
10437 | reloc2->addend = fixp->fx_addnumber; | |
10438 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
10439 | assert (reloc2->howto != NULL); | |
10440 | ||
10441 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
10442 | { | |
10443 | arelent *reloc3; | |
10444 | ||
10445 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
10446 | retval[3] = NULL; | |
10447 | *reloc3 = *reloc2; | |
10448 | reloc3->address += 4; | |
10449 | } | |
10450 | ||
d9aba805 | 10451 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
10452 | { |
10453 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
10454 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
10455 | } | |
d9aba805 | 10456 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10457 | { |
fb251650 | 10458 | switch (fixp->fx_r_type) |
0dd2d296 | 10459 | { |
fb251650 ILT |
10460 | default: |
10461 | abort (); | |
10462 | case BFD_RELOC_MIPS_GOT16: | |
10463 | break; | |
10464 | case BFD_RELOC_MIPS_CALL16: | |
10465 | case BFD_RELOC_MIPS_GOT_LO16: | |
10466 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 10467 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 10468 | break; |
0dd2d296 ILT |
10469 | } |
10470 | } | |
d9aba805 ILT |
10471 | else |
10472 | abort (); | |
0dd2d296 ILT |
10473 | } |
10474 | ||
a8aed9dd ILT |
10475 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
10476 | fixup_segment converted a non-PC relative reloc into a PC | |
10477 | relative reloc. In such a case, we need to convert the reloc | |
10478 | code. */ | |
10479 | code = fixp->fx_r_type; | |
10480 | if (fixp->fx_pcrel) | |
10481 | { | |
10482 | switch (code) | |
10483 | { | |
10484 | case BFD_RELOC_8: | |
10485 | code = BFD_RELOC_8_PCREL; | |
10486 | break; | |
10487 | case BFD_RELOC_16: | |
10488 | code = BFD_RELOC_16_PCREL; | |
10489 | break; | |
10490 | case BFD_RELOC_32: | |
10491 | code = BFD_RELOC_32_PCREL; | |
10492 | break; | |
bf39474f ILT |
10493 | case BFD_RELOC_64: |
10494 | code = BFD_RELOC_64_PCREL; | |
10495 | break; | |
a8aed9dd ILT |
10496 | case BFD_RELOC_8_PCREL: |
10497 | case BFD_RELOC_16_PCREL: | |
10498 | case BFD_RELOC_32_PCREL: | |
bf39474f | 10499 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 10500 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
10501 | case BFD_RELOC_PCREL_HI16_S: |
10502 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
10503 | break; |
10504 | default: | |
10505 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10506 | "Cannot make %s relocation PC relative", | |
10507 | bfd_get_reloc_code_name (code)); | |
10508 | } | |
10509 | } | |
10510 | ||
d9aba805 ILT |
10511 | /* To support a PC relative reloc when generating embedded PIC code |
10512 | for ECOFF, we use a Cygnus extension. We check for that here to | |
10513 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 10514 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 10515 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
10516 | && mips_pic != EMBEDDED_PIC) |
10517 | reloc->howto = NULL; | |
10518 | else | |
a8aed9dd | 10519 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 10520 | |
52aa70b5 JW |
10521 | if (reloc->howto == NULL) |
10522 | { | |
10523 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
10524 | "Can not represent %s relocation in this object file format", |
10525 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 10526 | retval[0] = NULL; |
52aa70b5 | 10527 | } |
3d3c5039 | 10528 | |
0dd2d296 | 10529 | return retval; |
3d3c5039 ILT |
10530 | } |
10531 | ||
cc5703cd ILT |
10532 | /* Relax a machine dependent frag. This returns the amount by which |
10533 | the current size of the frag should change. */ | |
10534 | ||
10535 | int | |
10536 | mips_relax_frag (fragp, stretch) | |
10537 | fragS *fragp; | |
10538 | long stretch; | |
10539 | { | |
10540 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
10541 | return 0; | |
10542 | ||
10543 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
10544 | { | |
10545 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10546 | return 0; | |
10547 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10548 | return 2; | |
10549 | } | |
10550 | else | |
10551 | { | |
10552 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10553 | return 0; | |
10554 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10555 | return -2; | |
10556 | } | |
10557 | ||
10558 | return 0; | |
10559 | } | |
10560 | ||
0dd2d296 ILT |
10561 | /* Convert a machine dependent frag. */ |
10562 | ||
10563 | void | |
10564 | md_convert_frag (abfd, asec, fragp) | |
10565 | bfd *abfd; | |
10566 | segT asec; | |
10567 | fragS *fragp; | |
3d3c5039 | 10568 | { |
0dd2d296 ILT |
10569 | int old, new; |
10570 | char *fixptr; | |
3d3c5039 | 10571 | |
cc5703cd ILT |
10572 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10573 | { | |
10574 | int type; | |
10575 | register const struct mips16_immed_operand *op; | |
10576 | boolean small, ext; | |
10577 | offsetT val; | |
10578 | bfd_byte *buf; | |
10579 | unsigned long insn; | |
10580 | boolean use_extend; | |
10581 | unsigned short extend; | |
10582 | ||
10583 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10584 | op = mips16_immed_operands; | |
10585 | while (op->type != type) | |
10586 | ++op; | |
10587 | ||
10588 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10589 | { | |
10590 | small = false; | |
10591 | ext = true; | |
10592 | } | |
10593 | else | |
10594 | { | |
10595 | small = true; | |
10596 | ext = false; | |
10597 | } | |
10598 | ||
f74ba7a3 | 10599 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 10600 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
10601 | if (op->pcrel) |
10602 | { | |
10603 | addressT addr; | |
10604 | ||
a677feeb ILT |
10605 | addr = fragp->fr_address + fragp->fr_fix; |
10606 | ||
10607 | /* The rules for the base address of a PC relative reloc are | |
10608 | complicated; see mips16_extended_frag. */ | |
10609 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
10610 | { |
10611 | addr += 2; | |
319305a7 ILT |
10612 | if (ext) |
10613 | addr += 2; | |
fbcfacb7 ILT |
10614 | /* Ignore the low bit in the target, since it will be |
10615 | set for a text label. */ | |
10616 | if ((val & 1) != 0) | |
10617 | --val; | |
10618 | } | |
a677feeb ILT |
10619 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10620 | addr -= 4; | |
10621 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10622 | addr -= 2; | |
10623 | ||
cc5703cd ILT |
10624 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
10625 | val -= addr; | |
a677feeb ILT |
10626 | |
10627 | /* Make sure the section winds up with the alignment we have | |
10628 | assumed. */ | |
10629 | if (op->shift > 0) | |
10630 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
10631 | } |
10632 | ||
035936da ILT |
10633 | if (ext |
10634 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
10635 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
10636 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
10637 | "extended instruction in delay slot"); | |
10638 | ||
cc5703cd ILT |
10639 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
10640 | ||
b9129c6f ILT |
10641 | if (target_big_endian) |
10642 | insn = bfd_getb16 (buf); | |
10643 | else | |
10644 | insn = bfd_getl16 (buf); | |
cc5703cd | 10645 | |
31a2c6ff ILT |
10646 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
10647 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
10648 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
10649 | |
10650 | if (use_extend) | |
10651 | { | |
10652 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
10653 | fragp->fr_fix += 2; | |
10654 | buf += 2; | |
10655 | } | |
3d3c5039 | 10656 | |
cc5703cd ILT |
10657 | md_number_to_chars (buf, insn, 2); |
10658 | fragp->fr_fix += 2; | |
10659 | buf += 2; | |
10660 | } | |
10661 | else | |
10662 | { | |
10663 | if (fragp->fr_opcode == NULL) | |
10664 | return; | |
0dd2d296 | 10665 | |
cc5703cd ILT |
10666 | old = RELAX_OLD (fragp->fr_subtype); |
10667 | new = RELAX_NEW (fragp->fr_subtype); | |
10668 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 10669 | |
cc5703cd ILT |
10670 | if (new > 0) |
10671 | memcpy (fixptr - old, fixptr, new); | |
10672 | ||
10673 | fragp->fr_fix += new - old; | |
10674 | } | |
0dd2d296 | 10675 | } |
becfe05e | 10676 | |
fbcfacb7 ILT |
10677 | #ifdef OBJ_ELF |
10678 | ||
10679 | /* This function is called after the relocs have been generated. | |
10680 | We've been storing mips16 text labels as odd. Here we convert them | |
10681 | back to even for the convenience of the debugger. */ | |
10682 | ||
10683 | void | |
10684 | mips_frob_file_after_relocs () | |
10685 | { | |
10686 | asymbol **syms; | |
10687 | unsigned int count, i; | |
10688 | ||
10689 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10690 | return; | |
10691 | ||
10692 | syms = bfd_get_outsymbols (stdoutput); | |
10693 | count = bfd_get_symcount (stdoutput); | |
10694 | for (i = 0; i < count; i++, syms++) | |
10695 | { | |
10696 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
10697 | && ((*syms)->value & 1) != 0) | |
10698 | { | |
10699 | (*syms)->value &= ~1; | |
10700 | /* If the symbol has an odd size, it was probably computed | |
10701 | incorrectly, so adjust that as well. */ | |
10702 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
10703 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
10704 | } | |
10705 | } | |
10706 | } | |
10707 | ||
10708 | #endif | |
10709 | ||
becfe05e ILT |
10710 | /* This function is called whenever a label is defined. It is used |
10711 | when handling branch delays; if a branch has a label, we assume we | |
10712 | can not move it. */ | |
10713 | ||
10714 | void | |
10715 | mips_define_label (sym) | |
10716 | symbolS *sym; | |
10717 | { | |
fbcfacb7 ILT |
10718 | struct insn_label_list *l; |
10719 | ||
10720 | if (free_insn_labels == NULL) | |
10721 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
10722 | else | |
10723 | { | |
10724 | l = free_insn_labels; | |
10725 | free_insn_labels = l->next; | |
10726 | } | |
10727 | ||
10728 | l->label = sym; | |
10729 | l->next = insn_labels; | |
10730 | insn_labels = l; | |
becfe05e | 10731 | } |
3d3c5039 | 10732 | \f |
739708fa | 10733 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 10734 | |
0dd2d296 | 10735 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
10736 | |
10737 | void | |
10738 | mips_elf_final_processing () | |
10739 | { | |
87178180 ILT |
10740 | /* Write out the register information. */ |
10741 | if (! mips_64) | |
10742 | { | |
10743 | Elf32_RegInfo s; | |
10744 | ||
10745 | s.ri_gprmask = mips_gprmask; | |
10746 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10747 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10748 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10749 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10750 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10751 | ||
10752 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
10753 | ((Elf32_External_RegInfo *) | |
10754 | mips_regmask_frag)); | |
10755 | } | |
10756 | else | |
10757 | { | |
10758 | Elf64_Internal_RegInfo s; | |
10759 | ||
10760 | s.ri_gprmask = mips_gprmask; | |
10761 | s.ri_pad = 0; | |
10762 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10763 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10764 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10765 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10766 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10767 | ||
10768 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
10769 | ((Elf64_External_RegInfo *) | |
10770 | mips_regmask_frag)); | |
10771 | } | |
0dd2d296 ILT |
10772 | |
10773 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
10774 | sort of BFD interface for this. */ | |
10775 | if (mips_any_noreorder) | |
10776 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 10777 | if (mips_pic != NO_PIC) |
0dd2d296 | 10778 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
10779 | } |
10780 | ||
739708fa | 10781 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 10782 | \f |
3d3c5039 ILT |
10783 | /* These functions should really be defined by the object file format, |
10784 | since they are related to debugging information. However, this | |
10785 | code has to work for the a.out format, which does not define them, | |
10786 | so we provide simple versions here. These don't actually generate | |
10787 | any debugging information, but they do simple checking and someday | |
10788 | somebody may make them useful. */ | |
10789 | ||
670a50eb ILT |
10790 | typedef struct loc |
10791 | { | |
10792 | struct loc *loc_next; | |
10793 | unsigned long loc_fileno; | |
10794 | unsigned long loc_lineno; | |
10795 | unsigned long loc_offset; | |
10796 | unsigned short loc_delta; | |
10797 | unsigned short loc_count; | |
3d3c5039 | 10798 | #if 0 |
670a50eb | 10799 | fragS *loc_frag; |
3d3c5039 | 10800 | #endif |
670a50eb ILT |
10801 | } |
10802 | locS; | |
3d3c5039 | 10803 | |
670a50eb ILT |
10804 | typedef struct proc |
10805 | { | |
3d3c5039 ILT |
10806 | struct proc *proc_next; |
10807 | struct symbol *proc_isym; | |
10808 | struct symbol *proc_end; | |
10809 | unsigned long proc_reg_mask; | |
10810 | unsigned long proc_reg_offset; | |
10811 | unsigned long proc_fpreg_mask; | |
10812 | unsigned long proc_fpreg_offset; | |
10813 | unsigned long proc_frameoffset; | |
10814 | unsigned long proc_framereg; | |
10815 | unsigned long proc_pcreg; | |
10816 | locS *proc_iline; | |
10817 | struct file *proc_file; | |
10818 | int proc_index; | |
670a50eb ILT |
10819 | } |
10820 | procS; | |
3d3c5039 | 10821 | |
670a50eb ILT |
10822 | typedef struct file |
10823 | { | |
3d3c5039 ILT |
10824 | struct file *file_next; |
10825 | unsigned long file_fileno; | |
10826 | struct symbol *file_symbol; | |
10827 | struct symbol *file_end; | |
10828 | struct proc *file_proc; | |
10829 | int file_numprocs; | |
670a50eb ILT |
10830 | } |
10831 | fileS; | |
3d3c5039 ILT |
10832 | |
10833 | static struct obstack proc_frags; | |
10834 | static procS *proc_lastP; | |
10835 | static procS *proc_rootP; | |
10836 | static int numprocs; | |
10837 | ||
10838 | static void | |
10839 | md_obj_begin () | |
10840 | { | |
670a50eb | 10841 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
10842 | } |
10843 | ||
10844 | static void | |
10845 | md_obj_end () | |
10846 | { | |
10847 | /* check for premature end, nesting errors, etc */ | |
10848 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 10849 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
10850 | } |
10851 | ||
3d3c5039 ILT |
10852 | static long |
10853 | get_number () | |
10854 | { | |
670a50eb ILT |
10855 | int negative = 0; |
10856 | long val = 0; | |
3d3c5039 | 10857 | |
670a50eb ILT |
10858 | if (*input_line_pointer == '-') |
10859 | { | |
10860 | ++input_line_pointer; | |
10861 | negative = 1; | |
3d3c5039 | 10862 | } |
670a50eb ILT |
10863 | if (!isdigit (*input_line_pointer)) |
10864 | as_bad ("Expected simple number."); | |
10865 | if (input_line_pointer[0] == '0') | |
10866 | { | |
10867 | if (input_line_pointer[1] == 'x') | |
10868 | { | |
10869 | input_line_pointer += 2; | |
10870 | while (isxdigit (*input_line_pointer)) | |
10871 | { | |
10872 | val <<= 4; | |
3a762a0b | 10873 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10874 | } |
670a50eb ILT |
10875 | return negative ? -val : val; |
10876 | } | |
10877 | else | |
10878 | { | |
10879 | ++input_line_pointer; | |
10880 | while (isdigit (*input_line_pointer)) | |
10881 | { | |
10882 | val <<= 3; | |
10883 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10884 | } |
670a50eb | 10885 | return negative ? -val : val; |
3d3c5039 ILT |
10886 | } |
10887 | } | |
670a50eb ILT |
10888 | if (!isdigit (*input_line_pointer)) |
10889 | { | |
10890 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10891 | *input_line_pointer, *input_line_pointer); | |
10892 | as_warn ("Invalid number"); | |
10893 | return -1; | |
3d3c5039 | 10894 | } |
670a50eb ILT |
10895 | while (isdigit (*input_line_pointer)) |
10896 | { | |
10897 | val *= 10; | |
10898 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10899 | } |
670a50eb | 10900 | return negative ? -val : val; |
3d3c5039 ILT |
10901 | } |
10902 | ||
10903 | /* The .file directive; just like the usual .file directive, but there | |
10904 | is an initial number which is the ECOFF file index. */ | |
10905 | ||
10906 | static void | |
10907 | s_file (x) | |
10908 | int x; | |
10909 | { | |
670a50eb | 10910 | int line; |
3d3c5039 | 10911 | |
670a50eb | 10912 | line = get_number (); |
9a7d824a | 10913 | s_app_file (0); |
3d3c5039 ILT |
10914 | } |
10915 | ||
10916 | ||
10917 | /* The .end directive. */ | |
10918 | ||
10919 | static void | |
10920 | s_mipsend (x) | |
10921 | int x; | |
10922 | { | |
670a50eb ILT |
10923 | symbolS *p; |
10924 | ||
10925 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10926 | { | |
10927 | p = get_symbol (); | |
10928 | demand_empty_rest_of_line (); | |
10929 | } | |
10930 | else | |
10931 | p = NULL; | |
10932 | if (now_seg != text_section) | |
10933 | as_warn (".end not in text section"); | |
10934 | if (!proc_lastP) | |
10935 | { | |
10936 | as_warn (".end and no .ent seen yet."); | |
10937 | return; | |
3d3c5039 ILT |
10938 | } |
10939 | ||
670a50eb ILT |
10940 | if (p != NULL) |
10941 | { | |
10942 | assert (S_GET_NAME (p)); | |
10943 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10944 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10945 | } |
10946 | ||
670a50eb | 10947 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10948 | } |
10949 | ||
10950 | /* The .aent and .ent directives. */ | |
10951 | ||
10952 | static void | |
10953 | s_ent (aent) | |
10954 | int aent; | |
10955 | { | |
670a50eb ILT |
10956 | int number = 0; |
10957 | procS *procP; | |
10958 | symbolS *symbolP; | |
10959 | ||
10960 | symbolP = get_symbol (); | |
10961 | if (*input_line_pointer == ',') | |
10962 | input_line_pointer++; | |
dd3f1f76 | 10963 | SKIP_WHITESPACE (); |
670a50eb ILT |
10964 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10965 | number = get_number (); | |
10966 | if (now_seg != text_section) | |
10967 | as_warn (".ent or .aent not in text section."); | |
10968 | ||
10969 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10970 | as_warn ("missing `.end'"); | |
10971 | ||
10972 | if (!aent) | |
10973 | { | |
10974 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10975 | procP->proc_isym = symbolP; | |
10976 | procP->proc_reg_mask = 0; | |
10977 | procP->proc_reg_offset = 0; | |
10978 | procP->proc_fpreg_mask = 0; | |
10979 | procP->proc_fpreg_offset = 0; | |
10980 | procP->proc_frameoffset = 0; | |
10981 | procP->proc_framereg = 0; | |
10982 | procP->proc_pcreg = 0; | |
10983 | procP->proc_end = NULL; | |
10984 | procP->proc_next = NULL; | |
10985 | if (proc_lastP) | |
10986 | proc_lastP->proc_next = procP; | |
10987 | else | |
10988 | proc_rootP = procP; | |
10989 | proc_lastP = procP; | |
10990 | numprocs++; | |
3d3c5039 | 10991 | } |
670a50eb | 10992 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10993 | } |
10994 | ||
10995 | /* The .frame directive. */ | |
10996 | ||
88225433 | 10997 | #if 0 |
3d3c5039 ILT |
10998 | static void |
10999 | s_frame (x) | |
670a50eb | 11000 | int x; |
3d3c5039 | 11001 | { |
670a50eb ILT |
11002 | char str[100]; |
11003 | symbolS *symP; | |
11004 | int frame_reg; | |
11005 | int frame_off; | |
11006 | int pcreg; | |
11007 | ||
0dd2d296 | 11008 | frame_reg = tc_get_register (1); |
670a50eb ILT |
11009 | if (*input_line_pointer == ',') |
11010 | input_line_pointer++; | |
5ac34ac3 | 11011 | frame_off = get_absolute_expression (); |
670a50eb ILT |
11012 | if (*input_line_pointer == ',') |
11013 | input_line_pointer++; | |
0dd2d296 | 11014 | pcreg = tc_get_register (0); |
670a50eb ILT |
11015 | |
11016 | /* bob third eye */ | |
11017 | assert (proc_rootP); | |
11018 | proc_rootP->proc_framereg = frame_reg; | |
11019 | proc_rootP->proc_frameoffset = frame_off; | |
11020 | proc_rootP->proc_pcreg = pcreg; | |
11021 | /* bob macho .frame */ | |
11022 | ||
11023 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 11024 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
11025 | { |
11026 | if (!proc_lastP) | |
11027 | as_warn ("No .ent for .frame to use."); | |
11028 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
11029 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
11030 | S_SET_TYPE (symP, N_RMASK); | |
11031 | S_SET_OTHER (symP, 0); | |
11032 | S_SET_DESC (symP, 0); | |
11033 | symP->sy_forward = proc_lastP->proc_isym; | |
11034 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11035 | } |
670a50eb | 11036 | demand_empty_rest_of_line (); |
3d3c5039 | 11037 | } |
88225433 | 11038 | #endif |
3d3c5039 ILT |
11039 | |
11040 | /* The .fmask and .mask directives. */ | |
11041 | ||
88225433 | 11042 | #if 0 |
3d3c5039 ILT |
11043 | static void |
11044 | s_mask (reg_type) | |
11045 | char reg_type; | |
11046 | { | |
670a50eb ILT |
11047 | char str[100], *strP; |
11048 | symbolS *symP; | |
11049 | int i; | |
11050 | unsigned int mask; | |
11051 | int off; | |
11052 | ||
11053 | mask = get_number (); | |
11054 | if (*input_line_pointer == ',') | |
11055 | input_line_pointer++; | |
11056 | off = get_absolute_expression (); | |
11057 | ||
11058 | /* bob only for coff */ | |
11059 | assert (proc_rootP); | |
11060 | if (reg_type == 'F') | |
11061 | { | |
11062 | proc_rootP->proc_fpreg_mask = mask; | |
11063 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 11064 | } |
670a50eb ILT |
11065 | else |
11066 | { | |
11067 | proc_rootP->proc_reg_mask = mask; | |
11068 | proc_rootP->proc_reg_offset = off; | |
11069 | } | |
11070 | ||
11071 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 11072 | |
670a50eb ILT |
11073 | /* We don't have to write out a mask stab if no saved regs. */ |
11074 | if (!(mask == 0)) | |
11075 | { | |
11076 | if (!proc_lastP) | |
11077 | as_warn ("No .ent for .mask to use."); | |
11078 | strP = str; | |
11079 | for (i = 0; i < 32; i++) | |
11080 | { | |
11081 | if (mask % 2) | |
11082 | { | |
11083 | sprintf (strP, "%c%d,", reg_type, i); | |
11084 | strP += strlen (strP); | |
11085 | } | |
3d3c5039 | 11086 | mask /= 2; |
670a50eb ILT |
11087 | } |
11088 | sprintf (strP, ";%d,", off); | |
11089 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
11090 | S_SET_TYPE (symP, N_RMASK); | |
11091 | S_SET_OTHER (symP, 0); | |
11092 | S_SET_DESC (symP, 0); | |
11093 | symP->sy_forward = proc_lastP->proc_isym; | |
11094 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11095 | } |
3d3c5039 | 11096 | } |
88225433 | 11097 | #endif |
3d3c5039 ILT |
11098 | |
11099 | /* The .loc directive. */ | |
11100 | ||
88225433 | 11101 | #if 0 |
3d3c5039 ILT |
11102 | static void |
11103 | s_loc (x) | |
11104 | int x; | |
11105 | { | |
670a50eb ILT |
11106 | symbolS *symbolP; |
11107 | int lineno; | |
11108 | int addroff; | |
3d3c5039 | 11109 | |
670a50eb | 11110 | assert (now_seg == text_section); |
3d3c5039 | 11111 | |
670a50eb | 11112 | lineno = get_number (); |
87e48495 | 11113 | addroff = frag_now_fix (); |
3d3c5039 | 11114 | |
670a50eb ILT |
11115 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
11116 | S_SET_TYPE (symbolP, N_SLINE); | |
11117 | S_SET_OTHER (symbolP, 0); | |
11118 | S_SET_DESC (symbolP, lineno); | |
11119 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 11120 | } |
88225433 | 11121 | #endif |