]>
Commit | Line | Data |
---|---|---|
3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
a3e8c5b7 | 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
739708fa KR |
64 | |
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
f2a663d3 | 72 | #include "elf/mips.h" |
1dc1e798 | 73 | #endif |
f2a663d3 | 74 | |
739708fa | 75 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 76 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
77 | #define ECOFF_DEBUGGING 0 |
78 | #endif | |
79 | ||
22ba90ce ILT |
80 | #include "ecoff.h" |
81 | ||
a8aed9dd | 82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 83 | static char *mips_regmask_frag; |
a8aed9dd | 84 | #endif |
f2a663d3 | 85 | |
3d3c5039 | 86 | #define AT 1 |
cc5703cd | 87 | #define TREG 24 |
9226253a | 88 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
89 | #define KT0 26 |
90 | #define KT1 27 | |
670a50eb | 91 | #define GP 28 |
9226253a ILT |
92 | #define SP 29 |
93 | #define FP 30 | |
3d3c5039 ILT |
94 | #define RA 31 |
95 | ||
cc5703cd ILT |
96 | #define ILLEGAL_REG (32) |
97 | ||
af942793 SS |
98 | /* Allow override of standard little-endian ECOFF format. */ |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
1dc1e798 | 104 | extern int target_big_endian; |
88225433 | 105 | |
7f9880e5 | 106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
6fd819cf GRK |
107 | 32 bit ABI. This has no meaning for ECOFF. |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
7f9880e5 ILT |
110 | static int mips_64; |
111 | ||
04cb3372 | 112 | /* The default target format to use. */ |
1dc1e798 KR |
113 | const char * |
114 | mips_target_format () | |
115 | { | |
116 | switch (OUTPUT_FLAVOR) | |
117 | { | |
118 | case bfd_target_aout_flavour: | |
119 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
120 | case bfd_target_ecoff_flavour: | |
af942793 | 121 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 122 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
123 | return (target_big_endian |
124 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
125 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
126 | default: |
127 | abort (); | |
a3e8c5b7 | 128 | return NULL; |
1dc1e798 KR |
129 | } |
130 | } | |
04cb3372 | 131 | |
d2c71068 | 132 | /* The name of the readonly data section. */ |
1dc1e798 KR |
133 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
134 | ? ".data" \ | |
135 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
136 | ? ".rdata" \ | |
137 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
138 | ? ".rodata" \ | |
139 | : (abort (), "")) | |
d2c71068 | 140 | |
3c83da8a JW |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
145 | struct mips_set_options | |
146 | { | |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
151 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
152 | not, 1 if we are, and -1 if the value has not been initialized. | |
153 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
154 | -nomips16 command line options, and the default CPU. */ | |
155 | int mips16; | |
156 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
157 | reorder' and `.set noreorder'. */ | |
158 | int noreorder; | |
159 | /* Non-zero if we should not permit the $at ($1) register to be used | |
160 | in instructions. Changed by `.set at' and `.set noat'. */ | |
161 | int noat; | |
162 | /* Non-zero if we should warn when a macro instruction expands into | |
163 | more than one machine instruction. Changed by `.set nomacro' and | |
164 | `.set macro'. */ | |
165 | int warn_about_macros; | |
166 | /* Non-zero if we should not move instructions. Changed by `.set | |
167 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
168 | int nomove; | |
169 | /* Non-zero if we should not optimize branches by moving the target | |
170 | of the branch into the delay slot. Actually, we don't perform | |
171 | this optimization anyhow. Changed by `.set bopt' and `.set | |
172 | nobopt'. */ | |
173 | int nobopt; | |
174 | /* Non-zero if we should not autoextend mips16 instructions. | |
175 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
176 | int noautoextend; | |
177 | }; | |
178 | ||
179 | /* This is the struct we use to hold the current set of options. Note | |
180 | that we must set the isa and mips16 fields to -1 to indicate that | |
181 | they have not been initialized. */ | |
182 | ||
183 | static struct mips_set_options mips_opts = { -1, -1 }; | |
184 | ||
1aa6938e ILT |
185 | /* These variables are filled in with the masks of registers used. |
186 | The object format code reads them and puts them in the appropriate | |
187 | place. */ | |
188 | unsigned long mips_gprmask; | |
189 | unsigned long mips_cprmask[4]; | |
190 | ||
1051c97f ILT |
191 | /* MIPS ISA we are using for this output file. */ |
192 | static int file_mips_isa; | |
193 | ||
8c63448a | 194 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 195 | static int mips_cpu = -1; |
8c63448a | 196 | |
b2b8c24e ILT |
197 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
198 | static int mips_4650 = -1; | |
199 | ||
e532b44c ILT |
200 | /* Whether the 4010 instructions are permitted. */ |
201 | static int mips_4010 = -1; | |
202 | ||
c625fc23 JSC |
203 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
204 | static int mips_4100 = -1; | |
205 | ||
aa2e0460 KR |
206 | /* start-sanitize-vr5400 */ |
207 | /* Whether NEC vr5400 instructions are permitted. */ | |
208 | static int mips_5400 = -1; | |
209 | ||
210 | /* end-sanitize-vr5400 */ | |
276c2d7d GRK |
211 | /* start-sanitize-r5900 */ |
212 | /* Whether Toshiba r5900 instructions are permitted. */ | |
213 | static int mips_5900 = -1; | |
276c2d7d | 214 | |
aa2e0460 | 215 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
216 | /* Whether Toshiba r3900 instructions are permitted. */ |
217 | static int mips_3900 = -1; | |
218 | ||
42444087 GRK |
219 | /* start-sanitize-tx49 */ |
220 | /* Whether Toshiba r4900 instructions are permitted. */ | |
221 | static int mips_4900 = -1; | |
222 | ||
223 | /* end-sanitize-tx49 */ | |
4e96260f JL |
224 | /* start-sanitize-tx19 */ |
225 | /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it. | |
226 | The tx19 related options and configuration bits are handled by | |
227 | the tx39 flags. */ | |
228 | /* end-sanitize-tx19 */ | |
229 | ||
5c6f5923 GRK |
230 | /* Whether the processor uses hardware interlocks to protect |
231 | reads from the HI and LO registers, and thus does not | |
232 | require nops to be inserted. */ | |
4ebda395 GRK |
233 | #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \ |
234 | /* start-sanitize-tx49 */ \ | |
42444087 | 235 | || mips_cpu == 4900 || mips_4900 \ |
4ebda395 | 236 | /* end-sanitize-tx49 */ \ |
b3ed1af3 KR |
237 | /* start-sanitize-vr5400 */ \ |
238 | || mips_cpu == 5400 \ | |
239 | /* end-sanitize-vr5400 */ \ | |
4ebda395 | 240 | ) |
5c6f5923 | 241 | |
a3e8c5b7 ILT |
242 | /* Whether the processor uses hardware interlocks to protect reads |
243 | from the GPRs, and thus does not require nops to be inserted. */ | |
244 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900) | |
1c6f3441 ILT |
245 | /* start-sanitize-vr5400 */ |
246 | #undef gpr_interlocks | |
247 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400) | |
248 | /* end-sanitize-vr5400 */ | |
249 | ||
e532b44c | 250 | |
5c6f5923 | 251 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 252 | (co-processor) interlocks. */ |
efec4a28 | 253 | /* Itbl support may require additional care here. */ |
a3e8c5b7 | 254 | #define cop_interlocks (mips_cpu == 4300) |
1c6f3441 ILT |
255 | /* start-sanitize-vr5400 */ |
256 | #undef cop_interlocks | |
257 | #define cop_interlocks (mips_cpu == 4300 || mips_cpu == 5400) | |
258 | /* end-sanitize-vr5400 */ | |
344a8d61 | 259 | |
d9aba805 ILT |
260 | /* MIPS PIC level. */ |
261 | ||
262 | enum mips_pic_level | |
263 | { | |
264 | /* Do not generate PIC code. */ | |
265 | NO_PIC, | |
266 | ||
267 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
268 | not sure what it is supposed to do. */ | |
269 | IRIX4_PIC, | |
270 | ||
271 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
272 | SVR4_PIC, | |
273 | ||
274 | /* Generate PIC code without using a global offset table: the data | |
275 | segment has a maximum size of 64K, all data references are off | |
276 | the $gp register, and all text references are PC relative. This | |
277 | is used on some embedded systems. */ | |
278 | EMBEDDED_PIC | |
279 | }; | |
280 | ||
281 | static enum mips_pic_level mips_pic; | |
9226253a | 282 | |
fb251650 ILT |
283 | /* 1 if we should generate 32 bit offsets from the GP register in |
284 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
285 | static int mips_big_got; | |
286 | ||
8ea7f4e8 ILT |
287 | /* 1 if trap instructions should used for overflow rather than break |
288 | instructions. */ | |
289 | static int mips_trap; | |
290 | ||
3c83da8a | 291 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 292 | |
0dd2d296 | 293 | static int mips_any_noreorder; |
3d3c5039 | 294 | |
670a50eb ILT |
295 | /* The size of the small data section. */ |
296 | static int g_switch_value = 8; | |
42562568 ILT |
297 | /* Whether the -G option was used. */ |
298 | static int g_switch_seen = 0; | |
670a50eb | 299 | |
3d3c5039 ILT |
300 | #define N_RMASK 0xc4 |
301 | #define N_VFP 0xd4 | |
302 | ||
d8a1c247 KR |
303 | /* If we can determine in advance that GP optimization won't be |
304 | possible, we can skip the relaxation stuff that tries to produce | |
305 | GP-relative references. This makes delay slot optimization work | |
306 | better. | |
307 | ||
308 | This function can only provide a guess, but it seems to work for | |
309 | gcc output. If it guesses wrong, the only loss should be in | |
310 | efficiency; it shouldn't introduce any bugs. | |
311 | ||
312 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
313 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 314 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 315 | |
3d3c5039 ILT |
316 | /* handle of the OPCODE hash table */ |
317 | static struct hash_control *op_hash = NULL; | |
318 | ||
cc5703cd ILT |
319 | /* The opcode hash table we use for the mips16. */ |
320 | static struct hash_control *mips16_op_hash = NULL; | |
321 | ||
3d3c5039 ILT |
322 | /* This array holds the chars that always start a comment. If the |
323 | pre-processor is disabled, these aren't very useful */ | |
324 | const char comment_chars[] = "#"; | |
325 | ||
326 | /* This array holds the chars that only start a comment at the beginning of | |
327 | a line. If the line seems to have the form '# 123 filename' | |
328 | .line and .file directives will appear in the pre-processed output */ | |
329 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
330 | first line of the input file. This is because the compiler outputs | |
331 | #NO_APP at the beginning of its output. */ | |
332 | /* Also note that C style comments are always supported. */ | |
333 | const char line_comment_chars[] = "#"; | |
334 | ||
335 | /* This array holds machine specific line separator characters. */ | |
336 | const char line_separator_chars[] = ""; | |
337 | ||
338 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
339 | const char EXP_CHARS[] = "eE"; | |
340 | ||
341 | /* Chars that mean this number is a floating point constant */ | |
342 | /* As in 0f12.456 */ | |
343 | /* or 0d1.2345e12 */ | |
344 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
345 | ||
346 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
347 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
348 | but nothing is ideal around here. | |
349 | */ | |
350 | ||
670a50eb | 351 | static char *insn_error; |
3d3c5039 | 352 | |
3d3c5039 | 353 | static int auto_align = 1; |
becfe05e | 354 | |
9226253a ILT |
355 | /* When outputting SVR4 PIC code, the assembler needs to know the |
356 | offset in the stack frame from which to restore the $gp register. | |
357 | This is set by the .cprestore pseudo-op, and saved in this | |
358 | variable. */ | |
0dd2d296 ILT |
359 | static offsetT mips_cprestore_offset = -1; |
360 | ||
361 | /* This is the register which holds the stack frame, as set by the | |
362 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
363 | static int mips_frame_reg = SP; | |
9226253a | 364 | |
becfe05e ILT |
365 | /* To output NOP instructions correctly, we need to keep information |
366 | about the previous two instructions. */ | |
367 | ||
0aa07269 ILT |
368 | /* Whether we are optimizing. The default value of 2 means to remove |
369 | unneeded NOPs and swap branch instructions when possible. A value | |
370 | of 1 means to not swap branches. A value of 0 means to always | |
371 | insert NOPs. */ | |
372 | static int mips_optimize = 2; | |
4e95866e | 373 | |
22ba90ce ILT |
374 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
375 | equivalent to seeing no -g option at all. */ | |
376 | static int mips_debug = 0; | |
377 | ||
becfe05e ILT |
378 | /* The previous instruction. */ |
379 | static struct mips_cl_insn prev_insn; | |
380 | ||
381 | /* The instruction before prev_insn. */ | |
382 | static struct mips_cl_insn prev_prev_insn; | |
383 | ||
384 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
385 | point the insn_mo field at this dummy integer. */ | |
386 | static const struct mips_opcode dummy_opcode = { 0 }; | |
387 | ||
388 | /* Non-zero if prev_insn is valid. */ | |
389 | static int prev_insn_valid; | |
390 | ||
391 | /* The frag for the previous instruction. */ | |
392 | static struct frag *prev_insn_frag; | |
393 | ||
394 | /* The offset into prev_insn_frag for the previous instruction. */ | |
395 | static long prev_insn_where; | |
396 | ||
a677feeb ILT |
397 | /* The reloc type for the previous instruction, if any. */ |
398 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
399 | ||
becfe05e ILT |
400 | /* The reloc for the previous instruction, if any. */ |
401 | static fixS *prev_insn_fixp; | |
402 | ||
403 | /* Non-zero if the previous instruction was in a delay slot. */ | |
404 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
405 | |
406 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
407 | static int prev_insn_unreordered; | |
408 | ||
cc5703cd ILT |
409 | /* Non-zero if the previous instruction uses an extend opcode (if |
410 | mips16). */ | |
411 | static int prev_insn_extended; | |
412 | ||
4e95866e ILT |
413 | /* Non-zero if the previous previous instruction was in a .set |
414 | noreorder. */ | |
415 | static int prev_prev_insn_unreordered; | |
867a58b3 | 416 | |
4a1cb507 ILT |
417 | /* If this is set, it points to a frag holding nop instructions which |
418 | were inserted before the start of a noreorder section. If those | |
419 | nops turn out to be unnecessary, the size of the frag can be | |
420 | decreased. */ | |
421 | static fragS *prev_nop_frag; | |
422 | ||
423 | /* The number of nop instructions we created in prev_nop_frag. */ | |
424 | static int prev_nop_frag_holds; | |
425 | ||
426 | /* The number of nop instructions that we know we need in | |
427 | prev_nop_frag. */ | |
428 | static int prev_nop_frag_required; | |
429 | ||
430 | /* The number of instructions we've seen since prev_nop_frag. */ | |
431 | static int prev_nop_frag_since; | |
432 | ||
867a58b3 ILT |
433 | /* For ECOFF and ELF, relocations against symbols are done in two |
434 | parts, with a HI relocation and a LO relocation. Each relocation | |
435 | has only 16 bits of space to store an addend. This means that in | |
436 | order for the linker to handle carries correctly, it must be able | |
437 | to locate both the HI and the LO relocation. This means that the | |
438 | relocations must appear in order in the relocation table. | |
439 | ||
440 | In order to implement this, we keep track of each unmatched HI | |
441 | relocation. We then sort them so that they immediately precede the | |
442 | corresponding LO relocation. */ | |
443 | ||
444 | struct mips_hi_fixup | |
445 | { | |
446 | /* Next HI fixup. */ | |
447 | struct mips_hi_fixup *next; | |
448 | /* This fixup. */ | |
449 | fixS *fixp; | |
450 | /* The section this fixup is in. */ | |
451 | segT seg; | |
452 | }; | |
453 | ||
454 | /* The list of unmatched HI relocs. */ | |
455 | ||
456 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
457 | |
458 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
459 | ||
460 | #define X ILLEGAL_REG | |
461 | static const int mips32_to_16_reg_map[] = | |
462 | { | |
463 | X, X, 2, 3, 4, 5, 6, 7, | |
464 | X, X, X, X, X, X, X, X, | |
465 | 0, 1, X, X, X, X, X, X, | |
466 | X, X, X, X, X, X, X, X | |
467 | }; | |
468 | #undef X | |
469 | ||
470 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
471 | ||
472 | static const int mips16_to_32_reg_map[] = | |
473 | { | |
474 | 16, 17, 2, 3, 4, 5, 6, 7 | |
475 | }; | |
3d3c5039 | 476 | \f |
0dd2d296 ILT |
477 | /* Since the MIPS does not have multiple forms of PC relative |
478 | instructions, we do not have to do relaxing as is done on other | |
479 | platforms. However, we do have to handle GP relative addressing | |
480 | correctly, which turns out to be a similar problem. | |
481 | ||
482 | Every macro that refers to a symbol can occur in (at least) two | |
483 | forms, one with GP relative addressing and one without. For | |
484 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 485 | a macro instruction like this: |
0dd2d296 ILT |
486 | lw $4,i |
487 | If i can be addressed off the GP register (this is true if it is in | |
488 | the .sbss or .sdata section, or if it is known to be smaller than | |
489 | the -G argument) this will generate the following instruction: | |
490 | lw $4,i($gp) | |
491 | This instruction will use a GPREL reloc. If i can not be addressed | |
492 | off the GP register, the following instruction sequence will be used: | |
493 | lui $at,i | |
494 | lw $4,i($at) | |
495 | In this case the first instruction will have a HI16 reloc, and the | |
496 | second reloc will have a LO16 reloc. Both relocs will be against | |
497 | the symbol i. | |
498 | ||
499 | The issue here is that we may not know whether i is GP addressable | |
500 | until after we see the instruction that uses it. Therefore, we | |
501 | want to be able to choose the final instruction sequence only at | |
502 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 503 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
504 | end of assembly. |
505 | ||
506 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
507 | addressing in quite the same way, but the issue still arises as |
508 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
509 | |
510 | We handle these issues by actually generating both possible | |
511 | instruction sequences. The longer one is put in a frag_var with | |
512 | type rs_machine_dependent. We encode what to do with the frag in | |
513 | the subtype field. We encode (1) the number of existing bytes to | |
514 | replace, (2) the number of new bytes to use, (3) the offset from | |
515 | the start of the existing bytes to the first reloc we must generate | |
516 | (that is, the offset is applied from the start of the existing | |
517 | bytes after they are replaced by the new bytes, if any), (4) the | |
518 | offset from the start of the existing bytes to the second reloc, | |
519 | (5) whether a third reloc is needed (the third reloc is always four | |
520 | bytes after the second reloc), and (6) whether to warn if this | |
521 | variant is used (this is sometimes needed if .set nomacro or .set | |
522 | noat is in effect). All these numbers are reasonably small. | |
523 | ||
524 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
525 | ensure that delay slots are handled correctly. Fortunately, there |
526 | are a limited number of cases. When the second instruction | |
527 | sequence is generated, append_insn is directed to maintain the | |
528 | existing delay slot information, so it continues to apply to any | |
529 | code after the second instruction sequence. This means that the | |
530 | second instruction sequence must not impose any requirements not | |
531 | required by the first instruction sequence. | |
0dd2d296 ILT |
532 | |
533 | These variant frags are then handled in functions called by the | |
534 | machine independent code. md_estimate_size_before_relax returns | |
535 | the final size of the frag. md_convert_frag sets up the final form | |
536 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
537 | one if needed. */ | |
538 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
539 | ((relax_substateT) \ | |
cc5703cd | 540 | (((old) << 23) \ |
0dd2d296 ILT |
541 | | ((new) << 16) \ |
542 | | (((reloc1) + 64) << 9) \ | |
543 | | (((reloc2) + 64) << 2) \ | |
544 | | ((reloc3) ? (1 << 1) : 0) \ | |
545 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
546 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
547 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
548 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
549 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
550 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
551 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
552 | |
553 | /* For mips16 code, we use an entirely different form of relaxation. | |
554 | mips16 supports two versions of most instructions which take | |
555 | immediate values: a small one which takes some small value, and a | |
556 | larger one which takes a 16 bit value. Since branches also follow | |
557 | this pattern, relaxing these values is required. | |
558 | ||
559 | We can assemble both mips16 and normal MIPS code in a single | |
560 | object. Therefore, we need to support this type of relaxation at | |
561 | the same time that we support the relaxation described above. We | |
562 | use the high bit of the subtype field to distinguish these cases. | |
563 | ||
a677feeb ILT |
564 | The information we store for this type of relaxation is the |
565 | argument code found in the opcode file for this relocation, whether | |
566 | the user explicitly requested a small or extended form, and whether | |
567 | the relocation is in a jump or jal delay slot. That tells us the | |
568 | size of the value, and how it should be stored. We also store | |
569 | whether the fragment is considered to be extended or not. We also | |
570 | store whether this is known to be a branch to a different section, | |
571 | whether we have tried to relax this frag yet, and whether we have | |
572 | ever extended a PC relative fragment because of a shift count. */ | |
573 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
574 | (0x80000000 \ | |
575 | | ((type) & 0xff) \ | |
576 | | ((small) ? 0x100 : 0) \ | |
577 | | ((ext) ? 0x200 : 0) \ | |
578 | | ((dslot) ? 0x400 : 0) \ | |
579 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
580 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
581 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
582 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
583 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
584 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
585 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
586 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
587 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
588 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
589 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
590 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
591 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 592 | \f |
3d3c5039 ILT |
593 | /* Prototypes for static functions. */ |
594 | ||
595 | #ifdef __STDC__ | |
596 | #define internalError() \ | |
597 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
598 | #else | |
599 | #define internalError() as_fatal ("MIPS internal Error"); | |
600 | #endif | |
601 | ||
cc5703cd ILT |
602 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
603 | ||
becfe05e | 604 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 605 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 606 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 607 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
608 | static void append_insn PARAMS ((char *place, |
609 | struct mips_cl_insn * ip, | |
670a50eb | 610 | expressionS * p, |
867a58b3 ILT |
611 | bfd_reloc_code_real_type r, |
612 | boolean)); | |
4a1cb507 | 613 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 614 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 615 | #ifdef USE_STDARG |
0dd2d296 | 616 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
617 | const char *name, const char *fmt, |
618 | ...)); | |
c625fc23 JSC |
619 | #else |
620 | static void macro_build (); | |
621 | #endif | |
cc5703cd ILT |
622 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
623 | const char *, const char *, | |
624 | va_list)); | |
0dd2d296 ILT |
625 | static void macro_build_lui PARAMS ((char *place, int *counter, |
626 | expressionS * ep, int regnum)); | |
6e8dda9c | 627 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 628 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 629 | expressionS *)); |
d8a1c247 | 630 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 631 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 632 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 633 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
634 | #ifdef LOSING_COMPILER |
635 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
636 | #endif | |
670a50eb | 637 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 638 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
639 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
640 | boolean, boolean, unsigned long *, | |
641 | boolean *, unsigned short *)); | |
670a50eb ILT |
642 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
643 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 644 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 645 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
646 | static void s_align PARAMS ((int)); |
647 | static void s_change_sec PARAMS ((int)); | |
648 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 649 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 650 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
651 | static void s_option PARAMS ((int)); |
652 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
653 | static void s_abicalls PARAMS ((int)); |
654 | static void s_cpload PARAMS ((int)); | |
655 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
656 | static void s_gpword PARAMS ((int)); |
657 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 658 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
659 | static void md_obj_begin PARAMS ((void)); |
660 | static void md_obj_end PARAMS ((void)); | |
661 | static long get_number PARAMS ((void)); | |
662 | static void s_ent PARAMS ((int)); | |
663 | static void s_mipsend PARAMS ((int)); | |
664 | static void s_file PARAMS ((int)); | |
3c83da8a | 665 | static void s_mips_stab PARAMS ((int)); |
cc5703cd | 666 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
aa2e0460 KR |
667 | |
668 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); | |
3d3c5039 ILT |
669 | \f |
670 | /* Pseudo-op table. | |
671 | ||
672 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
673 | should be defined here, but are currently unsupported: .alias, | |
674 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
675 | ||
676 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
677 | specific to the type of debugging information being generated, and | |
678 | should be defined by the object format: .aent, .begin, .bend, | |
679 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
680 | .vreg. | |
681 | ||
682 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
683 | not MIPS CPU specific, but are also not specific to the object file | |
684 | format. This file is probably the best place to define them, but | |
685 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
686 | .struct, .weakext. */ | |
687 | ||
739708fa | 688 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 689 | { |
670a50eb ILT |
690 | /* MIPS specific pseudo-ops. */ |
691 | {"option", s_option, 0}, | |
692 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
693 | {"rdata", s_change_sec, 'r'}, |
694 | {"sdata", s_change_sec, 's'}, | |
695 | {"livereg", s_ignore, 0}, | |
739708fa KR |
696 | {"abicalls", s_abicalls, 0}, |
697 | {"cpload", s_cpload, 0}, | |
698 | {"cprestore", s_cprestore, 0}, | |
699 | {"gpword", s_gpword, 0}, | |
700 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 701 | {"insn", s_insn, 0}, |
3d3c5039 | 702 | |
670a50eb | 703 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 704 | chips. */ |
739708fa | 705 | {"asciiz", stringer, 1}, |
670a50eb ILT |
706 | {"bss", s_change_sec, 'b'}, |
707 | {"err", s_err, 0}, | |
708 | {"half", s_cons, 1}, | |
52aa70b5 | 709 | {"dword", s_cons, 3}, |
3d3c5039 | 710 | |
670a50eb | 711 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 712 | here for one reason or another. */ |
670a50eb ILT |
713 | {"align", s_align, 0}, |
714 | {"byte", s_cons, 0}, | |
715 | {"data", s_change_sec, 'd'}, | |
becfe05e | 716 | {"double", s_float_cons, 'd'}, |
becfe05e | 717 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
718 | {"globl", s_mips_globl, 0}, |
719 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
720 | {"hword", s_cons, 1}, |
721 | {"int", s_cons, 2}, | |
722 | {"long", s_cons, 2}, | |
723 | {"octa", s_cons, 4}, | |
724 | {"quad", s_cons, 3}, | |
725 | {"short", s_cons, 1}, | |
726 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 727 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
728 | {"text", s_change_sec, 't'}, |
729 | {"word", s_cons, 2}, | |
739708fa KR |
730 | { 0 }, |
731 | }; | |
3d3c5039 | 732 | |
739708fa | 733 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 734 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 735 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 736 | {"aent", s_ent, 1}, |
9226253a | 737 | {"bgnb", s_ignore, 0}, |
670a50eb | 738 | {"end", s_mipsend, 0}, |
9226253a | 739 | {"endb", s_ignore, 0}, |
670a50eb ILT |
740 | {"ent", s_ent, 0}, |
741 | {"file", s_file, 0}, | |
742 | {"fmask", s_ignore, 'F'}, | |
743 | {"frame", s_ignore, 0}, | |
744 | {"loc", s_ignore, 0}, | |
745 | {"mask", s_ignore, 'R'}, | |
746 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
747 | { 0 }, |
748 | }; | |
61420a20 | 749 | |
739708fa KR |
750 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
751 | ||
752 | void | |
753 | mips_pop_insert () | |
754 | { | |
755 | pop_insert (mips_pseudo_table); | |
756 | if (! ECOFF_DEBUGGING) | |
757 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 758 | } |
3d3c5039 | 759 | \f |
fbcfacb7 ILT |
760 | /* Symbols labelling the current insn. */ |
761 | ||
762 | struct insn_label_list | |
763 | { | |
764 | struct insn_label_list *next; | |
765 | symbolS *label; | |
766 | }; | |
767 | ||
768 | static struct insn_label_list *insn_labels; | |
769 | static struct insn_label_list *free_insn_labels; | |
770 | ||
771 | static void mips_clear_insn_labels PARAMS ((void)); | |
772 | ||
773 | static inline void | |
774 | mips_clear_insn_labels () | |
775 | { | |
776 | register struct insn_label_list **pl; | |
777 | ||
778 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
779 | ; | |
780 | *pl = insn_labels; | |
781 | insn_labels = NULL; | |
782 | } | |
783 | \f | |
3d3c5039 ILT |
784 | static char *expr_end; |
785 | ||
867a58b3 ILT |
786 | /* Expressions which appear in instructions. These are set by |
787 | mips_ip. */ | |
788 | ||
3d3c5039 ILT |
789 | static expressionS imm_expr; |
790 | static expressionS offset_expr; | |
867a58b3 ILT |
791 | |
792 | /* Relocs associated with imm_expr and offset_expr. */ | |
793 | ||
3d3c5039 ILT |
794 | static bfd_reloc_code_real_type imm_reloc; |
795 | static bfd_reloc_code_real_type offset_reloc; | |
796 | ||
867a58b3 ILT |
797 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
798 | ||
799 | static boolean imm_unmatched_hi; | |
800 | ||
8728fa92 ILT |
801 | /* These are set by mips16_ip if an explicit extension is used. */ |
802 | ||
803 | static boolean mips16_small, mips16_ext; | |
804 | ||
3d3c5039 ILT |
805 | /* |
806 | * This function is called once, at assembler startup time. It should | |
807 | * set up all the tables, etc. that the MD part of the assembler will need. | |
808 | */ | |
809 | void | |
670a50eb | 810 | md_begin () |
3d3c5039 | 811 | { |
0dd2d296 | 812 | boolean ok = false; |
604633ae | 813 | register const char *retval = NULL; |
670a50eb | 814 | register unsigned int i = 0; |
1724c79e GRK |
815 | const char *cpu; |
816 | char *a = NULL; | |
aa2e0460 | 817 | int broken = 0; |
3d3c5039 | 818 | |
1724c79e GRK |
819 | cpu = TARGET_CPU; |
820 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
8358c818 | 821 | { |
1724c79e GRK |
822 | a = xmalloc (sizeof TARGET_CPU); |
823 | strcpy (a, TARGET_CPU); | |
824 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
825 | cpu = a; | |
826 | } | |
8c63448a | 827 | |
1724c79e GRK |
828 | if (mips_cpu < 0) |
829 | { | |
830 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
831 | just the generic 'mips', in which case set mips_cpu based | |
832 | on the given ISA, if any. */ | |
8c63448a ILT |
833 | |
834 | if (strcmp (cpu, "mips") == 0) | |
1724c79e GRK |
835 | { |
836 | if (mips_opts.isa < 0) | |
837 | mips_cpu = 3000; | |
838 | ||
839 | else if (mips_opts.isa == 2) | |
840 | mips_cpu = 6000; | |
841 | ||
842 | else if (mips_opts.isa == 3) | |
843 | mips_cpu = 4000; | |
844 | ||
845 | else if (mips_opts.isa == 4) | |
846 | mips_cpu = 8000; | |
847 | ||
848 | else | |
849 | mips_cpu = 3000; | |
850 | } | |
851 | ||
5c6f5923 | 852 | else if (strcmp (cpu, "r3900") == 0 |
6fd819cf | 853 | || strcmp (cpu, "mipstx39") == 0 |
4e96260f JL |
854 | /* start-sanitize-tx19 */ |
855 | || strcmp (cpu, "r1900") == 0 | |
856 | || strcmp (cpu, "mipstx19") == 0 | |
857 | /* end-sanitize-tx19 */ | |
858 | ) | |
1724c79e GRK |
859 | mips_cpu = 3900; |
860 | ||
8c63448a ILT |
861 | else if (strcmp (cpu, "r6000") == 0 |
862 | || strcmp (cpu, "mips2") == 0) | |
1724c79e GRK |
863 | mips_cpu = 6000; |
864 | ||
8c63448a ILT |
865 | else if (strcmp (cpu, "mips64") == 0 |
866 | || strcmp (cpu, "r4000") == 0 | |
867 | || strcmp (cpu, "mips3") == 0) | |
1724c79e GRK |
868 | mips_cpu = 4000; |
869 | ||
8c63448a | 870 | else if (strcmp (cpu, "r4400") == 0) |
1724c79e GRK |
871 | mips_cpu = 4400; |
872 | ||
8c63448a ILT |
873 | else if (strcmp (cpu, "mips64orion") == 0 |
874 | || strcmp (cpu, "r4600") == 0) | |
1724c79e GRK |
875 | mips_cpu = 4600; |
876 | ||
b2b8c24e | 877 | else if (strcmp (cpu, "r4650") == 0) |
1724c79e GRK |
878 | mips_cpu = 4650; |
879 | ||
c625fc23 | 880 | else if (strcmp (cpu, "mips64vr4300") == 0) |
1724c79e GRK |
881 | mips_cpu = 4300; |
882 | ||
c625fc23 | 883 | else if (strcmp (cpu, "mips64vr4100") == 0) |
1724c79e GRK |
884 | mips_cpu = 4100; |
885 | ||
e532b44c | 886 | else if (strcmp (cpu, "r4010") == 0) |
1724c79e GRK |
887 | mips_cpu = 4010; |
888 | ||
4ebda395 GRK |
889 | /* start-sanitize-tx49 */ |
890 | else if (strcmp (cpu, "mips64tx49") == 0) | |
1724c79e | 891 | mips_cpu = 4900; |
4ebda395 | 892 | /* end-sanitize-tx49 */ |
1724c79e | 893 | |
517078c1 ILT |
894 | else if (strcmp (cpu, "r5000") == 0 |
895 | || strcmp (cpu, "mips64vr5000") == 0) | |
1724c79e GRK |
896 | mips_cpu = 5000; |
897 | ||
aa2e0460 KR |
898 | /* start-sanitize-vr5400 */ |
899 | else if (strcmp (cpu, "r5400") == 0 | |
b3ed1af3 KR |
900 | || strcmp (cpu, "mips64vr5400") == 0) |
901 | mips_cpu = 5400; | |
aa2e0460 | 902 | /* end-sanitize-vr5400 */ |
1724c79e | 903 | |
276c2d7d GRK |
904 | /* start-sanitize-r5900 */ |
905 | else if (strcmp (cpu, "r5900") == 0 | |
1724c79e GRK |
906 | || strcmp (cpu, "mips64r5900") == 0) |
907 | mips_cpu = 5900; | |
276c2d7d | 908 | /* end-sanitize-r5900 */ |
1724c79e | 909 | |
d8a1c247 KR |
910 | else if (strcmp (cpu, "r8000") == 0 |
911 | || strcmp (cpu, "mips4") == 0) | |
1724c79e GRK |
912 | mips_cpu = 8000; |
913 | ||
d8a1c247 | 914 | else if (strcmp (cpu, "r10000") == 0) |
1724c79e GRK |
915 | mips_cpu = 10000; |
916 | ||
cc5703cd | 917 | else if (strcmp (cpu, "mips16") == 0) |
1724c79e GRK |
918 | mips_cpu = 0; /* FIXME */ |
919 | ||
8358c818 | 920 | else |
1724c79e GRK |
921 | mips_cpu = 3000; |
922 | } | |
8c63448a | 923 | |
1724c79e GRK |
924 | if (mips_opts.isa == -1) |
925 | { | |
926 | if (mips_cpu == 3000 | |
927 | || mips_cpu == 3900) | |
928 | mips_opts.isa = 1; | |
929 | ||
930 | else if (mips_cpu == 6000 | |
931 | || mips_cpu == 4010) | |
932 | mips_opts.isa = 2; | |
933 | ||
934 | else if (mips_cpu == 4000 | |
935 | || mips_cpu == 4100 | |
936 | || mips_cpu == 4400 | |
937 | || mips_cpu == 4300 | |
938 | || mips_cpu == 4600 | |
939 | /* start-sanitize-tx49 */ | |
940 | || mips_cpu == 4900 | |
941 | /* end-sanitize-tx49 */ | |
942 | /* start-sanitize-r5900 */ | |
943 | || mips_cpu == 5900 | |
944 | /* end-sanitize-r5900 */ | |
945 | || mips_cpu == 4650) | |
946 | mips_opts.isa = 3; | |
947 | ||
948 | else if (mips_cpu == 5000 | |
949 | /* start-sanitize-vr5400 */ | |
950 | || mips_cpu == 5400 | |
951 | /* end-sanitize-vr5400 */ | |
952 | || mips_cpu == 8000 | |
953 | || mips_cpu == 10000) | |
954 | mips_opts.isa = 4; | |
955 | ||
956 | else | |
957 | mips_opts.isa = 1; | |
8358c818 ILT |
958 | } |
959 | ||
3c83da8a | 960 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
961 | { |
962 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 963 | mips_opts.mips16 = 1; |
cc5703cd | 964 | else |
3c83da8a | 965 | mips_opts.mips16 = 0; |
cc5703cd ILT |
966 | } |
967 | ||
b2b8c24e | 968 | if (mips_4650 < 0) |
1724c79e | 969 | mips_4650 = (mips_cpu == 4650); |
b2b8c24e | 970 | |
e532b44c | 971 | if (mips_4010 < 0) |
1724c79e | 972 | mips_4010 = (mips_cpu == 4010); |
e532b44c | 973 | |
c625fc23 | 974 | if (mips_4100 < 0) |
1724c79e | 975 | mips_4100 = (mips_cpu == 4100); |
c625fc23 | 976 | |
aa2e0460 KR |
977 | /* start-sanitize-vr5400 */ |
978 | if (mips_5400 < 0) | |
1724c79e | 979 | mips_5400 = (mips_cpu == 5400); |
aa2e0460 | 980 | /* end-sanitize-vr5400 */ |
1724c79e | 981 | |
276c2d7d GRK |
982 | /* start-sanitize-r5900 */ |
983 | if (mips_5900 < 0) | |
1724c79e | 984 | mips_5900 = (mips_cpu == 5900); |
aa2e0460 | 985 | /* end-sanitize-r5900 */ |
1724c79e | 986 | |
5c6f5923 | 987 | if (mips_3900 < 0) |
1724c79e GRK |
988 | mips_3900 = (mips_cpu == 3900); |
989 | ||
42444087 GRK |
990 | /* start-sanitize-tx49 */ |
991 | if (mips_4900 < 0) | |
992 | mips_4900 = (mips_cpu == 4900); | |
1724c79e | 993 | |
42444087 | 994 | /* end-sanitize-tx49 */ |
1724c79e GRK |
995 | |
996 | /* End of TARGET_CPU processing, get rid of malloced memory | |
997 | if necessary. */ | |
998 | cpu = NULL; | |
999 | if (a != NULL) | |
1000 | { | |
1001 | free (a); | |
1002 | a = NULL; | |
1003 | } | |
1004 | ||
3c83da8a | 1005 | if (mips_opts.isa < 2 && mips_trap) |
8ea7f4e8 ILT |
1006 | as_bad ("trap exception not supported at ISA 1"); |
1007 | ||
3c83da8a | 1008 | switch (mips_opts.isa) |
97f99d11 ILT |
1009 | { |
1010 | case 1: | |
1011 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1012 | break; | |
1013 | case 2: | |
1014 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1015 | break; | |
1016 | case 3: | |
1017 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1018 | break; | |
d8a1c247 KR |
1019 | case 4: |
1020 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1021 | break; | |
97f99d11 ILT |
1022 | } |
1023 | if (! ok) | |
1024 | as_warn ("Could not set architecture and machine"); | |
1025 | ||
3c83da8a | 1026 | file_mips_isa = mips_opts.isa; |
1051c97f | 1027 | |
13fe1379 ILT |
1028 | op_hash = hash_new (); |
1029 | ||
670a50eb ILT |
1030 | for (i = 0; i < NUMOPCODES;) |
1031 | { | |
1032 | const char *name = mips_opcodes[i].name; | |
1033 | ||
604633ae | 1034 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 1035 | if (retval != NULL) |
670a50eb ILT |
1036 | { |
1037 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
1038 | mips_opcodes[i].name, retval); | |
aa2e0460 | 1039 | /* Probably a memory allocation problem? Give up now. */ |
670a50eb ILT |
1040 | as_fatal ("Broken assembler. No assembly attempted."); |
1041 | } | |
1042 | do | |
1043 | { | |
aa2e0460 | 1044 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
670a50eb | 1045 | { |
aa2e0460 KR |
1046 | if (!validate_mips_insn (&mips_opcodes[i])) |
1047 | broken = 1; | |
3d3c5039 | 1048 | } |
670a50eb ILT |
1049 | ++i; |
1050 | } | |
1051 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1052 | } |
1053 | ||
cc5703cd ILT |
1054 | mips16_op_hash = hash_new (); |
1055 | ||
1056 | i = 0; | |
1057 | while (i < bfd_mips16_num_opcodes) | |
1058 | { | |
1059 | const char *name = mips16_opcodes[i].name; | |
1060 | ||
1061 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1062 | if (retval != NULL) | |
aa2e0460 | 1063 | as_fatal ("internal: can't hash `%s': %s", |
cc5703cd ILT |
1064 | mips16_opcodes[i].name, retval); |
1065 | do | |
1066 | { | |
1067 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1068 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1069 | != mips16_opcodes[i].match)) | |
aa2e0460 KR |
1070 | { |
1071 | fprintf (stderr, "internal error: bad mips16 opcode: %s %s\n", | |
1072 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1073 | broken = 1; | |
1074 | } | |
cc5703cd ILT |
1075 | ++i; |
1076 | } | |
1077 | while (i < bfd_mips16_num_opcodes | |
1078 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1079 | } | |
1080 | ||
aa2e0460 KR |
1081 | if (broken) |
1082 | as_fatal ("Broken assembler. No assembly attempted."); | |
1083 | ||
ebf28372 ILT |
1084 | /* We add all the general register names to the symbol table. This |
1085 | helps us detect invalid uses of them. */ | |
1086 | for (i = 0; i < 32; i++) | |
1087 | { | |
1088 | char buf[5]; | |
1089 | ||
1090 | sprintf (buf, "$%d", i); | |
1091 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1092 | &zero_address_frag)); | |
1093 | } | |
1094 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1095 | &zero_address_frag)); | |
1096 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1097 | &zero_address_frag)); | |
1098 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1099 | &zero_address_frag)); | |
1100 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1101 | &zero_address_frag)); | |
1102 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1103 | &zero_address_frag)); | |
1104 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1105 | &zero_address_frag)); | |
1106 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1107 | &zero_address_frag)); | |
1108 | ||
4a1cb507 | 1109 | mips_no_prev_insn (false); |
becfe05e | 1110 | |
1aa6938e ILT |
1111 | mips_gprmask = 0; |
1112 | mips_cprmask[0] = 0; | |
1113 | mips_cprmask[1] = 0; | |
1114 | mips_cprmask[2] = 0; | |
1115 | mips_cprmask[3] = 0; | |
1116 | ||
8358c818 | 1117 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1118 | record_alignment (text_section, 2); |
8358c818 | 1119 | |
1dc1e798 KR |
1120 | if (USE_GLOBAL_POINTER_OPT) |
1121 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1122 | |
1dc1e798 KR |
1123 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1124 | { | |
08e17202 ILT |
1125 | /* On a native system, sections must be aligned to 16 byte |
1126 | boundaries. When configured for an embedded ELF target, we | |
1127 | don't bother. */ | |
1128 | if (strcmp (TARGET_OS, "elf") != 0) | |
1129 | { | |
1130 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1131 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1132 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1133 | } | |
1dc1e798 KR |
1134 | |
1135 | /* Create a .reginfo section for register masks and a .mdebug | |
1136 | section for debugging information. */ | |
1137 | { | |
1138 | segT seg; | |
1139 | subsegT subseg; | |
b3a64736 | 1140 | flagword flags; |
1dc1e798 KR |
1141 | segT sec; |
1142 | ||
1143 | seg = now_seg; | |
1144 | subseg = now_subseg; | |
1dc1e798 | 1145 | |
b3a64736 ILT |
1146 | /* The ABI says this section should be loaded so that the |
1147 | running program can access it. However, we don't load it | |
1148 | if we are configured for an embedded target */ | |
1149 | flags = SEC_READONLY | SEC_DATA; | |
1150 | if (strcmp (TARGET_OS, "elf") != 0) | |
1151 | flags |= SEC_ALLOC | SEC_LOAD; | |
1152 | ||
87178180 ILT |
1153 | if (! mips_64) |
1154 | { | |
1155 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1156 | |
b3a64736 ILT |
1157 | |
1158 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1159 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1160 | ||
f2a663d3 | 1161 | #ifdef OBJ_ELF |
87178180 | 1162 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1163 | #endif |
87178180 ILT |
1164 | } |
1165 | else | |
1166 | { | |
1167 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1168 | .reginfo section. */ | |
1169 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1170 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1171 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1172 | ||
1173 | #ifdef OBJ_ELF | |
1174 | /* Set up the option header. */ | |
1175 | { | |
1176 | Elf_Internal_Options opthdr; | |
1177 | char *f; | |
1178 | ||
1179 | opthdr.kind = ODK_REGINFO; | |
1180 | opthdr.size = (sizeof (Elf_External_Options) | |
1181 | + sizeof (Elf64_External_RegInfo)); | |
1182 | opthdr.section = 0; | |
1183 | opthdr.info = 0; | |
1184 | f = frag_more (sizeof (Elf_External_Options)); | |
1185 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1186 | (Elf_External_Options *) f); | |
1187 | ||
1188 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1189 | } | |
1190 | #endif | |
1191 | } | |
f2a663d3 | 1192 | |
739708fa KR |
1193 | if (ECOFF_DEBUGGING) |
1194 | { | |
1195 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1196 | (void) bfd_set_section_flags (stdoutput, sec, | |
1197 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1198 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1199 | } | |
0dd2d296 | 1200 | |
1dc1e798 KR |
1201 | subseg_set (seg, subseg); |
1202 | } | |
1203 | } | |
f2a663d3 | 1204 | |
739708fa KR |
1205 | if (! ECOFF_DEBUGGING) |
1206 | md_obj_begin (); | |
3d3c5039 ILT |
1207 | } |
1208 | ||
1209 | void | |
13fe1379 | 1210 | md_mips_end () |
3d3c5039 | 1211 | { |
739708fa KR |
1212 | if (! ECOFF_DEBUGGING) |
1213 | md_obj_end (); | |
3d3c5039 ILT |
1214 | } |
1215 | ||
1216 | void | |
670a50eb ILT |
1217 | md_assemble (str) |
1218 | char *str; | |
3d3c5039 | 1219 | { |
670a50eb | 1220 | struct mips_cl_insn insn; |
3d3c5039 | 1221 | |
5ac34ac3 | 1222 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1223 | imm_reloc = BFD_RELOC_UNUSED; |
1224 | imm_unmatched_hi = false; | |
5ac34ac3 | 1225 | offset_expr.X_op = O_absent; |
867a58b3 | 1226 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1227 | |
3c83da8a | 1228 | if (mips_opts.mips16) |
cc5703cd ILT |
1229 | mips16_ip (str, &insn); |
1230 | else | |
efec4a28 | 1231 | { |
9218cee0 | 1232 | mips_ip (str, &insn); |
efec4a28 DP |
1233 | DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", |
1234 | str, insn.insn_opcode)); | |
1235 | } | |
cc5703cd | 1236 | |
670a50eb ILT |
1237 | if (insn_error) |
1238 | { | |
1239 | as_bad ("%s `%s'", insn_error, str); | |
1240 | return; | |
1241 | } | |
cc5703cd | 1242 | |
670a50eb ILT |
1243 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1244 | { | |
3c83da8a | 1245 | if (mips_opts.mips16) |
cc5703cd ILT |
1246 | mips16_macro (&insn); |
1247 | else | |
1248 | macro (&insn); | |
3d3c5039 | 1249 | } |
670a50eb ILT |
1250 | else |
1251 | { | |
5ac34ac3 | 1252 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1253 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1254 | imm_unmatched_hi); | |
5ac34ac3 | 1255 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1256 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1257 | else |
867a58b3 | 1258 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1259 | } |
1260 | } | |
1261 | ||
cc5703cd ILT |
1262 | /* See whether instruction IP reads register REG. CLASS is the type |
1263 | of register. */ | |
becfe05e ILT |
1264 | |
1265 | static int | |
cc5703cd | 1266 | insn_uses_reg (ip, reg, class) |
becfe05e | 1267 | struct mips_cl_insn *ip; |
604633ae | 1268 | unsigned int reg; |
cc5703cd | 1269 | enum mips_regclass class; |
becfe05e | 1270 | { |
cc5703cd ILT |
1271 | if (class == MIPS16_REG) |
1272 | { | |
3c83da8a | 1273 | assert (mips_opts.mips16); |
cc5703cd ILT |
1274 | reg = mips16_to_32_reg_map[reg]; |
1275 | class = MIPS_GR_REG; | |
1276 | } | |
1277 | ||
becfe05e | 1278 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1279 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1280 | return 0; |
1281 | ||
cc5703cd | 1282 | if (class == MIPS_FP_REG) |
becfe05e | 1283 | { |
3c83da8a | 1284 | assert (! mips_opts.mips16); |
becfe05e ILT |
1285 | /* If we are called with either $f0 or $f1, we must check $f0. |
1286 | This is not optimal, because it will introduce an unnecessary | |
1287 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1288 | need to distinguish reading both $f0 and $f1 or just one of | |
1289 | them. Note that we don't have to check the other way, | |
1290 | because there is no instruction that sets both $f0 and $f1 | |
1291 | and requires a delay. */ | |
1292 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1293 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1294 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1295 | return 1; |
1296 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1297 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1298 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1299 | return 1; |
1300 | } | |
3c83da8a | 1301 | else if (! mips_opts.mips16) |
becfe05e ILT |
1302 | { |
1303 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1304 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1305 | return 1; | |
1306 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1307 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1308 | return 1; | |
1309 | } | |
cc5703cd ILT |
1310 | else |
1311 | { | |
1312 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1313 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1314 | & MIPS16OP_MASK_RX)] | |
1315 | == reg)) | |
cc5703cd ILT |
1316 | return 1; |
1317 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1318 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1319 | & MIPS16OP_MASK_RY)] | |
1320 | == reg)) | |
cc5703cd ILT |
1321 | return 1; |
1322 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1323 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1324 | & MIPS16OP_MASK_MOVE32Z)] | |
1325 | == reg)) | |
cc5703cd ILT |
1326 | return 1; |
1327 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1328 | return 1; | |
1329 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1330 | return 1; | |
1331 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1332 | return 1; | |
1333 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1334 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1335 | & MIPS16OP_MASK_REGR32) == reg) | |
1336 | return 1; | |
1337 | } | |
becfe05e ILT |
1338 | |
1339 | return 0; | |
1340 | } | |
1341 | ||
fb251650 ILT |
1342 | /* This function returns true if modifying a register requires a |
1343 | delay. */ | |
1344 | ||
1345 | static int | |
1346 | reg_needs_delay (reg) | |
1347 | int reg; | |
1348 | { | |
1349 | unsigned long prev_pinfo; | |
1350 | ||
1351 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1352 | if (! mips_opts.noreorder |
1353 | && mips_opts.isa < 4 | |
fb251650 | 1354 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1355 | || (! gpr_interlocks |
fb251650 ILT |
1356 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1357 | { | |
1358 | /* A load from a coprocessor or from memory. All load | |
1359 | delays delay the use of general register rt for one | |
1360 | instruction on the r3000. The r6000 and r4000 use | |
1361 | interlocks. */ | |
efec4a28 | 1362 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1363 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1364 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1365 | return 1; | |
1366 | } | |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
3c83da8a JW |
1371 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1372 | handle them specially, such as generating jalx instructions when | |
1373 | needed. We also make them odd for the duration of the assembly, in | |
1374 | order to generate the right sort of code. We will make them even | |
1375 | in the adjust_symtab routine, while leaving them marked. This is | |
1376 | convenient for the debugger and the disassembler. The linker knows | |
1377 | to make them odd again. */ | |
1378 | ||
1379 | static void | |
1380 | mips16_mark_labels () | |
1381 | { | |
1382 | if (mips_opts.mips16) | |
1383 | { | |
1384 | struct insn_label_list *l; | |
1385 | ||
1386 | for (l = insn_labels; l != NULL; l = l->next) | |
1387 | { | |
68952421 | 1388 | #ifdef OBJ_ELF |
3c83da8a JW |
1389 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1390 | S_SET_OTHER (l->label, STO_MIPS16); | |
1391 | #endif | |
1392 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1393 | ++l->label->sy_value.X_add_number; | |
1394 | } | |
1395 | } | |
1396 | } | |
1397 | ||
0dd2d296 ILT |
1398 | /* Output an instruction. PLACE is where to put the instruction; if |
1399 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1400 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1401 | used with RELOC_TYPE. */ | |
3d3c5039 | 1402 | |
3d3c5039 | 1403 | static void |
867a58b3 | 1404 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1405 | char *place; |
670a50eb ILT |
1406 | struct mips_cl_insn *ip; |
1407 | expressionS *address_expr; | |
1408 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1409 | boolean unmatched_hi; |
3d3c5039 | 1410 | { |
1aa6938e | 1411 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1412 | char *f; |
becfe05e ILT |
1413 | fixS *fixp; |
1414 | int nops = 0; | |
3d3c5039 | 1415 | |
3c83da8a JW |
1416 | /* Mark instruction labels in mips16 mode. */ |
1417 | if (mips_opts.mips16) | |
1418 | mips16_mark_labels (); | |
fbcfacb7 | 1419 | |
1aa6938e ILT |
1420 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1421 | pinfo = ip->insn_mo->pinfo; | |
1422 | ||
3c83da8a | 1423 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1424 | { |
4a1cb507 ILT |
1425 | int prev_prev_nop; |
1426 | ||
becfe05e | 1427 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1428 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1429 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1430 | (1) a load from memory delay |
1431 | (2) a load from a coprocessor delay | |
1432 | (3) an unconditional branch delay | |
1433 | (4) a conditional branch delay | |
1434 | (5) a move to coprocessor register delay | |
1435 | (6) a load coprocessor register from memory delay | |
1436 | (7) a coprocessor condition code delay | |
1437 | (8) a HI/LO special register delay | |
becfe05e ILT |
1438 | |
1439 | There are a lot of optimizations we could do that we don't. | |
1440 | In particular, we do not, in general, reorder instructions. | |
1441 | If you use gcc with optimization, it will reorder | |
1442 | instructions and generally do much more optimization then we | |
1443 | do here; repeating all that work in the assembler would only | |
1444 | benefit hand written assembly code, and does not seem worth | |
1445 | it. */ | |
1446 | ||
1447 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1448 | #define emit_nop() \ |
3c83da8a | 1449 | (mips_opts.mips16 \ |
cc5703cd ILT |
1450 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1451 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1452 | |
1453 | /* The previous insn might require a delay slot, depending upon | |
1454 | the contents of the current insn. */ | |
3c83da8a JW |
1455 | if (! mips_opts.mips16 |
1456 | && mips_opts.isa < 4 | |
5af96dce ILT |
1457 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1458 | && ! cop_interlocks) | |
5c6f5923 | 1459 | || (! gpr_interlocks |
d8a1c247 | 1460 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1461 | { |
1462 | /* A load from a coprocessor or from memory. All load | |
1463 | delays delay the use of general register rt for one | |
1464 | instruction on the r3000. The r6000 and r4000 use | |
1465 | interlocks. */ | |
efec4a28 | 1466 | /* Itbl support may require additional care here. */ |
1aa6938e | 1467 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1468 | if (mips_optimize == 0 |
1469 | || insn_uses_reg (ip, | |
1470 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1471 | & OP_MASK_RT), | |
cc5703cd | 1472 | MIPS_GR_REG)) |
becfe05e ILT |
1473 | ++nops; |
1474 | } | |
3c83da8a JW |
1475 | else if (! mips_opts.mips16 |
1476 | && mips_opts.isa < 4 | |
5af96dce ILT |
1477 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1478 | && ! cop_interlocks) | |
3c83da8a | 1479 | || (mips_opts.isa < 2 |
d8a1c247 | 1480 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1481 | { |
1482 | /* A generic coprocessor delay. The previous instruction | |
1483 | modified a coprocessor general or control register. If | |
1484 | it modified a control register, we need to avoid any | |
1485 | coprocessor instruction (this is probably not always | |
1486 | required, but it sometimes is). If it modified a general | |
1487 | register, we avoid using that register. | |
1488 | ||
8358c818 ILT |
1489 | On the r6000 and r4000 loading a coprocessor register |
1490 | from memory is interlocked, and does not require a delay. | |
1491 | ||
becfe05e ILT |
1492 | This case is not handled very well. There is no special |
1493 | knowledge of CP0 handling, and the coprocessors other | |
1494 | than the floating point unit are not distinguished at | |
1495 | all. */ | |
efec4a28 DP |
1496 | /* Itbl support may require additional care here. FIXME! |
1497 | Need to modify this to include knowledge about | |
1498 | user specified delays! */ | |
1aa6938e | 1499 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1500 | { |
0aa07269 ILT |
1501 | if (mips_optimize == 0 |
1502 | || insn_uses_reg (ip, | |
8358c818 ILT |
1503 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1504 | & OP_MASK_FT), | |
cc5703cd | 1505 | MIPS_FP_REG)) |
becfe05e ILT |
1506 | ++nops; |
1507 | } | |
1aa6938e | 1508 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1509 | { |
0aa07269 ILT |
1510 | if (mips_optimize == 0 |
1511 | || insn_uses_reg (ip, | |
8358c818 ILT |
1512 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1513 | & OP_MASK_FS), | |
cc5703cd | 1514 | MIPS_FP_REG)) |
becfe05e ILT |
1515 | ++nops; |
1516 | } | |
1517 | else | |
1518 | { | |
1519 | /* We don't know exactly what the previous instruction | |
1520 | does. If the current instruction uses a coprocessor | |
1521 | register, we must insert a NOP. If previous | |
1522 | instruction may set the condition codes, and the | |
1523 | current instruction uses them, we must insert two | |
1524 | NOPS. */ | |
efec4a28 | 1525 | /* Itbl support may require additional care here. */ |
0aa07269 | 1526 | if (mips_optimize == 0 |
1aa6938e ILT |
1527 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1528 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1529 | nops += 2; |
1aa6938e | 1530 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1531 | ++nops; |
1532 | } | |
1533 | } | |
3c83da8a JW |
1534 | else if (! mips_opts.mips16 |
1535 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1536 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1537 | && ! cop_interlocks) | |
becfe05e ILT |
1538 | { |
1539 | /* The previous instruction sets the coprocessor condition | |
1540 | codes, but does not require a general coprocessor delay | |
1541 | (this means it is a floating point comparison | |
1542 | instruction). If this instruction uses the condition | |
1543 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1544 | /* Itbl support may require additional care here. */ |
0aa07269 | 1545 | if (mips_optimize == 0 |
1aa6938e | 1546 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1547 | ++nops; |
1548 | } | |
1aa6938e | 1549 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1550 | { |
1551 | /* The previous instruction reads the LO register; if the | |
1552 | current instruction writes to the LO register, we must | |
517078c1 | 1553 | insert two NOPS. Some newer processors have interlocks. */ |
5c6f5923 | 1554 | if (! hilo_interlocks |
b2b8c24e ILT |
1555 | && (mips_optimize == 0 |
1556 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1557 | nops += 2; |
1558 | } | |
1559 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1560 | { | |
1561 | /* The previous instruction reads the HI register; if the | |
1562 | current instruction writes to the HI register, we must | |
517078c1 | 1563 | insert a NOP. Some newer processors have interlocks. */ |
5c6f5923 | 1564 | if (! hilo_interlocks |
b2b8c24e ILT |
1565 | && (mips_optimize == 0 |
1566 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1567 | nops += 2; |
1568 | } | |
1569 | ||
4a1cb507 ILT |
1570 | /* If the previous instruction was in a noreorder section, then |
1571 | we don't want to insert the nop after all. */ | |
efec4a28 | 1572 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1573 | if (prev_insn_unreordered) |
1574 | nops = 0; | |
1575 | ||
becfe05e ILT |
1576 | /* There are two cases which require two intervening |
1577 | instructions: 1) setting the condition codes using a move to | |
1578 | coprocessor instruction which requires a general coprocessor | |
1579 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1580 | or LO register and then writing to it (except on processors |
1581 | which have interlocks). If we are not already emitting a NOP | |
1582 | instruction, we must check for these cases compared to the | |
1583 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1584 | if ((! mips_opts.mips16 |
1585 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1586 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1587 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1588 | && (pinfo & INSN_READ_COND_CODE) | |
1589 | && ! cop_interlocks) | |
1590 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1591 | && (pinfo & INSN_WRITE_LO) | |
5c6f5923 | 1592 | && ! hilo_interlocks) |
4a1cb507 ILT |
1593 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1594 | && (pinfo & INSN_WRITE_HI) | |
5c6f5923 | 1595 | && ! hilo_interlocks)) |
4a1cb507 ILT |
1596 | prev_prev_nop = 1; |
1597 | else | |
1598 | prev_prev_nop = 0; | |
1599 | ||
1600 | if (prev_prev_insn_unreordered) | |
1601 | prev_prev_nop = 0; | |
1602 | ||
1603 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1604 | ++nops; |
1605 | ||
0dd2d296 ILT |
1606 | /* If we are being given a nop instruction, don't bother with |
1607 | one of the nops we would otherwise output. This will only | |
1608 | happen when a nop instruction is used with mips_optimize set | |
1609 | to 0. */ | |
4a1cb507 | 1610 | if (nops > 0 |
3c83da8a JW |
1611 | && ! mips_opts.noreorder |
1612 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1613 | --nops; |
1614 | ||
becfe05e | 1615 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1616 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1617 | { |
5af96dce ILT |
1618 | fragS *old_frag; |
1619 | unsigned long old_frag_offset; | |
8c63448a | 1620 | int i; |
fbcfacb7 | 1621 | struct insn_label_list *l; |
8c63448a | 1622 | |
5af96dce ILT |
1623 | old_frag = frag_now; |
1624 | old_frag_offset = frag_now_fix (); | |
1625 | ||
8c63448a | 1626 | for (i = 0; i < nops; i++) |
becfe05e | 1627 | emit_nop (); |
5af96dce | 1628 | |
af255ca0 | 1629 | if (listing) |
546f5536 ILT |
1630 | { |
1631 | listing_prev_line (); | |
1632 | /* We may be at the start of a variant frag. In case we | |
1633 | are, make sure there is enough space for the frag | |
1634 | after the frags created by listing_prev_line. The | |
1635 | argument to frag_grow here must be at least as large | |
1636 | as the argument to all other calls to frag_grow in | |
1637 | this file. We don't have to worry about being in the | |
1638 | middle of a variant frag, because the variants insert | |
1639 | all needed nop instructions themselves. */ | |
1640 | frag_grow (40); | |
1641 | } | |
5af96dce | 1642 | |
fbcfacb7 | 1643 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1644 | { |
fbcfacb7 ILT |
1645 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1646 | l->label->sy_frag = frag_now; | |
1647 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1648 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1649 | if (mips_opts.mips16) |
fbcfacb7 | 1650 | ++l->label->sy_value.X_add_number; |
becfe05e | 1651 | } |
5af96dce ILT |
1652 | |
1653 | #ifndef NO_ECOFF_DEBUGGING | |
1654 | if (ECOFF_DEBUGGING) | |
1655 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1656 | #endif | |
becfe05e | 1657 | } |
4a1cb507 ILT |
1658 | else if (prev_nop_frag != NULL) |
1659 | { | |
1660 | /* We have a frag holding nops we may be able to remove. If | |
1661 | we don't need any nops, we can decrease the size of | |
1662 | prev_nop_frag by the size of one instruction. If we do | |
1663 | need some nops, we count them in prev_nops_required. */ | |
1664 | if (prev_nop_frag_since == 0) | |
1665 | { | |
1666 | if (nops == 0) | |
1667 | { | |
3c83da8a | 1668 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1669 | --prev_nop_frag_holds; |
1670 | } | |
1671 | else | |
1672 | prev_nop_frag_required += nops; | |
1673 | } | |
1674 | else | |
1675 | { | |
1676 | if (prev_prev_nop == 0) | |
1677 | { | |
3c83da8a | 1678 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1679 | --prev_nop_frag_holds; |
1680 | } | |
1681 | else | |
1682 | ++prev_nop_frag_required; | |
1683 | } | |
1684 | ||
1685 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1686 | prev_nop_frag = NULL; | |
1687 | ||
1688 | ++prev_nop_frag_since; | |
1689 | ||
1690 | /* Sanity check: by the time we reach the second instruction | |
1691 | after prev_nop_frag, we should have used up all the nops | |
1692 | one way or another. */ | |
1693 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1694 | } | |
becfe05e | 1695 | } |
4a1cb507 | 1696 | |
cc5703cd ILT |
1697 | if (reloc_type > BFD_RELOC_UNUSED) |
1698 | { | |
1699 | /* We need to set up a variant frag. */ | |
3c83da8a | 1700 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1701 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1702 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1703 | mips16_small, mips16_ext, |
1704 | (prev_pinfo | |
1705 | & INSN_UNCOND_BRANCH_DELAY), | |
1706 | (prev_insn_reloc_type | |
1707 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1708 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1709 | (char *) NULL); |
1710 | } | |
1711 | else if (place != NULL) | |
0dd2d296 | 1712 | f = place; |
3c83da8a JW |
1713 | else if (mips_opts.mips16 |
1714 | && ! ip->use_extend | |
1715 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1716 | { |
1717 | /* Make sure there is enough room to swap this instruction with | |
1718 | a following jump instruction. */ | |
1719 | frag_grow (6); | |
1720 | f = frag_more (2); | |
1721 | } | |
cc5703cd | 1722 | else |
035936da | 1723 | { |
3c83da8a JW |
1724 | if (mips_opts.mips16 |
1725 | && mips_opts.noreorder | |
035936da ILT |
1726 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
1727 | as_warn ("extended instruction in delay slot"); | |
1728 | ||
1729 | f = frag_more (4); | |
1730 | } | |
1731 | ||
becfe05e | 1732 | fixp = NULL; |
cc5703cd | 1733 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1734 | { |
5ac34ac3 | 1735 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1736 | { |
1737 | switch (reloc_type) | |
1738 | { | |
3d3c5039 | 1739 | case BFD_RELOC_32: |
670a50eb ILT |
1740 | ip->insn_opcode |= address_expr->X_add_number; |
1741 | break; | |
3d3c5039 ILT |
1742 | |
1743 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1744 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1745 | break; | |
3d3c5039 ILT |
1746 | |
1747 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1748 | if ((address_expr->X_add_number & 3) != 0) |
1749 | as_bad ("jump to misaligned address (0x%lx)", | |
1750 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1751 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1752 | break; | |
1753 | ||
cc5703cd | 1754 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1755 | if ((address_expr->X_add_number & 3) != 0) |
1756 | as_bad ("jump to misaligned address (0x%lx)", | |
1757 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1758 | ip->insn_opcode |= |
1759 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1760 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1761 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1762 | break; | |
1763 | ||
3d3c5039 | 1764 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1765 | goto need_reloc; |
3d3c5039 ILT |
1766 | |
1767 | default: | |
670a50eb | 1768 | internalError (); |
3d3c5039 | 1769 | } |
670a50eb ILT |
1770 | } |
1771 | else | |
1772 | { | |
3d3c5039 | 1773 | need_reloc: |
0dd2d296 ILT |
1774 | /* Don't generate a reloc if we are writing into a variant |
1775 | frag. */ | |
1776 | if (place == NULL) | |
867a58b3 ILT |
1777 | { |
1778 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1779 | address_expr, | |
1780 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1781 | reloc_type); | |
1782 | if (unmatched_hi) | |
1783 | { | |
1784 | struct mips_hi_fixup *hi_fixup; | |
1785 | ||
1786 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1787 | hi_fixup = ((struct mips_hi_fixup *) | |
1788 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1789 | hi_fixup->fixp = fixp; | |
1790 | hi_fixup->seg = now_seg; | |
1791 | hi_fixup->next = mips_hi_fixup_list; | |
1792 | mips_hi_fixup_list = hi_fixup; | |
1793 | } | |
1794 | } | |
3d3c5039 ILT |
1795 | } |
1796 | } | |
becfe05e | 1797 | |
3c83da8a | 1798 | if (! mips_opts.mips16) |
cc5703cd | 1799 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1800 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1801 | { | |
1802 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1803 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1804 | } | |
cc5703cd ILT |
1805 | else |
1806 | { | |
1807 | if (ip->use_extend) | |
1808 | { | |
1809 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1810 | f += 2; | |
1811 | } | |
1812 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1813 | } | |
670a50eb | 1814 | |
1aa6938e | 1815 | /* Update the register mask information. */ |
3c83da8a | 1816 | if (! mips_opts.mips16) |
cc5703cd ILT |
1817 | { |
1818 | if (pinfo & INSN_WRITE_GPR_D) | |
1819 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1820 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1821 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1822 | if (pinfo & INSN_READ_GPR_S) | |
1823 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1824 | if (pinfo & INSN_WRITE_GPR_31) | |
1825 | mips_gprmask |= 1 << 31; | |
1826 | if (pinfo & INSN_WRITE_FPR_D) | |
1827 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1828 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1829 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1830 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1831 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1832 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1833 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1834 | if (pinfo & INSN_COP) | |
1835 | { | |
efec4a28 DP |
1836 | /* We don't keep enough information to sort these cases out. |
1837 | The itbl support does keep this information however, although | |
1838 | we currently don't support itbl fprmats as part of the cop | |
1839 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1840 | } |
1841 | /* Never set the bit for $0, which is always zero. */ | |
1842 | mips_gprmask &=~ 1 << 0; | |
1843 | } | |
1844 | else | |
1aa6938e | 1845 | { |
cc5703cd ILT |
1846 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1847 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1848 | & MIPS16OP_MASK_RX); | |
1849 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1850 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1851 | & MIPS16OP_MASK_RY); | |
1852 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1853 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1854 | & MIPS16OP_MASK_RZ); | |
1855 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1856 | mips_gprmask |= 1 << TREG; | |
1857 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1858 | mips_gprmask |= 1 << SP; | |
1859 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1860 | mips_gprmask |= 1 << RA; | |
1861 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1862 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1863 | if (pinfo & MIPS16_INSN_READ_Z) | |
1864 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1865 | & MIPS16OP_MASK_MOVE32Z); | |
1866 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1867 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1868 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1869 | } |
1aa6938e | 1870 | |
3c83da8a | 1871 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1872 | { |
becfe05e ILT |
1873 | /* Filling the branch delay slot is more complex. We try to |
1874 | switch the branch with the previous instruction, which we can | |
1875 | do if the previous instruction does not set up a condition | |
1876 | that the branch tests and if the branch is not itself the | |
1877 | target of any branch. */ | |
1aa6938e ILT |
1878 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1879 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1880 | { |
0aa07269 | 1881 | if (mips_optimize < 2 |
19ed8960 ILT |
1882 | /* If we have seen .set volatile or .set nomove, don't |
1883 | optimize. */ | |
3c83da8a | 1884 | || mips_opts.nomove != 0 |
4e95866e ILT |
1885 | /* If we had to emit any NOP instructions, then we |
1886 | already know we can not swap. */ | |
1887 | || nops != 0 | |
becfe05e ILT |
1888 | /* If we don't even know the previous insn, we can not |
1889 | swap. */ | |
1890 | || ! prev_insn_valid | |
1891 | /* If the previous insn is already in a branch delay | |
1892 | slot, then we can not swap. */ | |
1893 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1894 | /* If the previous previous insn was in a .set |
1895 | noreorder, we can't swap. Actually, the MIPS | |
1896 | assembler will swap in this situation. However, gcc | |
1897 | configured -with-gnu-as will generate code like | |
1898 | .set noreorder | |
1899 | lw $4,XXX | |
1900 | .set reorder | |
1901 | INSN | |
1902 | bne $4,$0,foo | |
1903 | in which we can not swap the bne and INSN. If gcc is | |
1904 | not configured -with-gnu-as, it does not output the | |
1905 | .set pseudo-ops. We don't have to check | |
1906 | prev_insn_unreordered, because prev_insn_valid will | |
1907 | be 0 in that case. We don't want to use | |
1908 | prev_prev_insn_valid, because we do want to be able | |
1909 | to swap at the start of a function. */ | |
1910 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1911 | /* If the branch is itself the target of a branch, we |
1912 | can not swap. We cheat on this; all we check for is | |
1913 | whether there is a label on this instruction. If | |
1914 | there are any branches to anything other than a | |
1915 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1916 | || insn_labels != NULL |
777ad64d | 1917 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1918 | can not do the swap. This does not apply to the |
1919 | mips16, which uses variant frags for different | |
1920 | purposes. */ | |
3c83da8a | 1921 | || (! mips_opts.mips16 |
cc5703cd | 1922 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
1923 | /* If the branch reads the condition codes, we don't |
1924 | even try to swap, because in the sequence | |
1925 | ctc1 $X,$31 | |
1926 | INSN | |
1927 | INSN | |
1928 | bc1t LABEL | |
1929 | we can not swap, and I don't feel like handling that | |
1930 | case. */ | |
3c83da8a JW |
1931 | || (! mips_opts.mips16 |
1932 | && mips_opts.isa < 4 | |
d8a1c247 | 1933 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1934 | /* We can not swap with an instruction that requires a |
1935 | delay slot, becase the target of the branch might | |
1936 | interfere with that instruction. */ | |
3c83da8a JW |
1937 | || (! mips_opts.mips16 |
1938 | && mips_opts.isa < 4 | |
d8a1c247 | 1939 | && (prev_pinfo |
efec4a28 | 1940 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1941 | & (INSN_LOAD_COPROC_DELAY |
1942 | | INSN_COPROC_MOVE_DELAY | |
1943 | | INSN_WRITE_COND_CODE))) | |
5c6f5923 | 1944 | || (! hilo_interlocks |
b2b8c24e ILT |
1945 | && (prev_pinfo |
1946 | & (INSN_READ_LO | |
1947 | | INSN_READ_HI))) | |
5c6f5923 GRK |
1948 | || (! mips_opts.mips16 |
1949 | && ! gpr_interlocks | |
1950 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
1951 | || (! mips_opts.mips16 |
1952 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
1953 | /* Itbl support may require additional care here. */ |
1954 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 1955 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1956 | || (prev_pinfo |
6e8dda9c ILT |
1957 | & (INSN_UNCOND_BRANCH_DELAY |
1958 | | INSN_COND_BRANCH_DELAY | |
1959 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1960 | /* We do not swap with a trap instruction, since it |
1961 | complicates trap handlers to have the trap | |
1962 | instruction be in a delay slot. */ | |
1aa6938e | 1963 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1964 | /* If the branch reads a register that the previous |
1965 | instruction sets, we can not swap. */ | |
3c83da8a | 1966 | || (! mips_opts.mips16 |
cc5703cd | 1967 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
1968 | && insn_uses_reg (ip, |
1969 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1970 | & OP_MASK_RT), | |
cc5703cd | 1971 | MIPS_GR_REG)) |
3c83da8a | 1972 | || (! mips_opts.mips16 |
cc5703cd | 1973 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1974 | && insn_uses_reg (ip, |
1975 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1976 | & OP_MASK_RD), | |
cc5703cd | 1977 | MIPS_GR_REG)) |
3c83da8a | 1978 | || (mips_opts.mips16 |
cc5703cd ILT |
1979 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
1980 | && insn_uses_reg (ip, | |
1981 | ((prev_insn.insn_opcode | |
1982 | >> MIPS16OP_SH_RX) | |
1983 | & MIPS16OP_MASK_RX), | |
1984 | MIPS16_REG)) | |
1985 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1986 | && insn_uses_reg (ip, | |
1987 | ((prev_insn.insn_opcode | |
1988 | >> MIPS16OP_SH_RY) | |
1989 | & MIPS16OP_MASK_RY), | |
1990 | MIPS16_REG)) | |
1991 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1992 | && insn_uses_reg (ip, | |
1993 | ((prev_insn.insn_opcode | |
1994 | >> MIPS16OP_SH_RZ) | |
1995 | & MIPS16OP_MASK_RZ), | |
1996 | MIPS16_REG)) | |
1997 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1998 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1999 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2000 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2001 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2002 | && insn_uses_reg (ip, | |
2003 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2004 | insn_opcode), | |
2005 | MIPS_GR_REG)))) | |
1849d646 ILT |
2006 | /* If the branch writes a register that the previous |
2007 | instruction sets, we can not swap (we know that | |
2008 | branches write only to RD or to $31). */ | |
3c83da8a | 2009 | || (! mips_opts.mips16 |
cc5703cd | 2010 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 2011 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2012 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
2013 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2014 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2015 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
2016 | & OP_MASK_RT) | |
2017 | == 31)))) | |
3c83da8a | 2018 | || (! mips_opts.mips16 |
cc5703cd | 2019 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 2020 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2021 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
2022 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2023 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2024 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
2025 | & OP_MASK_RD) | |
2026 | == 31)))) | |
3c83da8a | 2027 | || (mips_opts.mips16 |
cc5703cd ILT |
2028 | && (pinfo & MIPS16_INSN_WRITE_31) |
2029 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2030 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2031 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2032 | == RA)))) | |
becfe05e ILT |
2033 | /* If the branch writes a register that the previous |
2034 | instruction reads, we can not swap (we know that | |
2035 | branches only write to RD or to $31). */ | |
3c83da8a | 2036 | || (! mips_opts.mips16 |
cc5703cd | 2037 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2038 | && insn_uses_reg (&prev_insn, |
2039 | ((ip->insn_opcode >> OP_SH_RD) | |
2040 | & OP_MASK_RD), | |
cc5703cd | 2041 | MIPS_GR_REG)) |
3c83da8a | 2042 | || (! mips_opts.mips16 |
cc5703cd ILT |
2043 | && (pinfo & INSN_WRITE_GPR_31) |
2044 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 2045 | || (mips_opts.mips16 |
cc5703cd ILT |
2046 | && (pinfo & MIPS16_INSN_WRITE_31) |
2047 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2048 | /* If we are generating embedded PIC code, the branch |
2049 | might be expanded into a sequence which uses $at, so | |
2050 | we can't swap with an instruction which reads it. */ | |
2051 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2052 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2053 | /* If the previous previous instruction has a load |
2054 | delay, and sets a register that the branch reads, we | |
2055 | can not swap. */ | |
3c83da8a JW |
2056 | || (! mips_opts.mips16 |
2057 | && mips_opts.isa < 4 | |
efec4a28 | 2058 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2059 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2060 | || (! gpr_interlocks |
d8a1c247 KR |
2061 | && (prev_prev_insn.insn_mo->pinfo |
2062 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2063 | && insn_uses_reg (ip, |
2064 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2065 | & OP_MASK_RT), | |
cc5703cd | 2066 | MIPS_GR_REG)) |
d31a3f5e ILT |
2067 | /* If one instruction sets a condition code and the |
2068 | other one uses a condition code, we can not swap. */ | |
2069 | || ((pinfo & INSN_READ_COND_CODE) | |
2070 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2071 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2072 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2073 | /* If the previous instruction uses the PC, we can not | |
2074 | swap. */ | |
3c83da8a | 2075 | || (mips_opts.mips16 |
cc5703cd ILT |
2076 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2077 | /* If the previous instruction was extended, we can not | |
2078 | swap. */ | |
3c83da8a | 2079 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2080 | /* If the previous instruction had a fixup in mips16 |
2081 | mode, we can not swap. This normally means that the | |
2082 | previous instruction was a 4 byte branch anyhow. */ | |
3c83da8a | 2083 | || (mips_opts.mips16 && prev_insn_fixp)) |
becfe05e ILT |
2084 | { |
2085 | /* We could do even better for unconditional branches to | |
2086 | portions of this object file; we could pick up the | |
2087 | instruction at the destination, put it in the delay | |
2088 | slot, and bump the destination address. */ | |
2089 | emit_nop (); | |
2090 | /* Update the previous insn information. */ | |
2091 | prev_prev_insn = *ip; | |
2092 | prev_insn.insn_mo = &dummy_opcode; | |
2093 | } | |
2094 | else | |
2095 | { | |
becfe05e | 2096 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2097 | if (! mips_opts.mips16) |
cc5703cd ILT |
2098 | { |
2099 | char *prev_f; | |
2100 | char temp[4]; | |
2101 | ||
2102 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2103 | memcpy (temp, prev_f, 4); | |
2104 | memcpy (prev_f, f, 4); | |
2105 | memcpy (f, temp, 4); | |
2106 | if (prev_insn_fixp) | |
2107 | { | |
2108 | prev_insn_fixp->fx_frag = frag_now; | |
2109 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2110 | } | |
2111 | if (fixp) | |
2112 | { | |
2113 | fixp->fx_frag = prev_insn_frag; | |
2114 | fixp->fx_where = prev_insn_where; | |
2115 | } | |
2116 | } | |
cc5703cd | 2117 | else |
becfe05e | 2118 | { |
cc5703cd ILT |
2119 | char *prev_f; |
2120 | char temp[2]; | |
2121 | ||
2122 | assert (prev_insn_fixp == NULL); | |
2123 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2124 | memcpy (temp, prev_f, 2); | |
2125 | memcpy (prev_f, f, 2); | |
2126 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2127 | { |
2128 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2129 | memcpy (f, temp, 2); | |
2130 | } | |
cc5703cd ILT |
2131 | else |
2132 | { | |
2133 | memcpy (f, f + 2, 2); | |
2134 | memcpy (f + 2, temp, 2); | |
2135 | } | |
2136 | if (fixp) | |
2137 | { | |
2138 | fixp->fx_frag = prev_insn_frag; | |
2139 | fixp->fx_where = prev_insn_where; | |
2140 | } | |
becfe05e | 2141 | } |
cc5703cd | 2142 | |
becfe05e ILT |
2143 | /* Update the previous insn information; leave prev_insn |
2144 | unchanged. */ | |
2145 | prev_prev_insn = *ip; | |
2146 | } | |
2147 | prev_insn_is_delay_slot = 1; | |
2148 | ||
2149 | /* If that was an unconditional branch, forget the previous | |
2150 | insn information. */ | |
1aa6938e | 2151 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2152 | { |
2153 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2154 | prev_insn.insn_mo = &dummy_opcode; | |
2155 | } | |
a677feeb ILT |
2156 | |
2157 | prev_insn_fixp = NULL; | |
2158 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2159 | prev_insn_extended = 0; | |
becfe05e | 2160 | } |
1aa6938e | 2161 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2162 | { |
2163 | /* We don't yet optimize a branch likely. What we should do | |
2164 | is look at the target, copy the instruction found there | |
2165 | into the delay slot, and increment the branch to jump to | |
2166 | the next instruction. */ | |
2167 | emit_nop (); | |
2168 | /* Update the previous insn information. */ | |
2169 | prev_prev_insn = *ip; | |
2170 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2171 | prev_insn_fixp = NULL; |
2172 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2173 | prev_insn_extended = 0; | |
8358c818 | 2174 | } |
becfe05e | 2175 | else |
670a50eb | 2176 | { |
becfe05e ILT |
2177 | /* Update the previous insn information. */ |
2178 | if (nops > 0) | |
2179 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2180 | else | |
2181 | prev_prev_insn = prev_insn; | |
2182 | prev_insn = *ip; | |
2183 | ||
2184 | /* Any time we see a branch, we always fill the delay slot | |
2185 | immediately; since this insn is not a branch, we know it | |
2186 | is not in a delay slot. */ | |
2187 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2188 | |
2189 | prev_insn_fixp = fixp; | |
2190 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2191 | if (mips_opts.mips16) |
a677feeb ILT |
2192 | prev_insn_extended = (ip->use_extend |
2193 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2194 | } |
2195 | ||
4e95866e ILT |
2196 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2197 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2198 | prev_insn_frag = frag_now; |
2199 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2200 | prev_insn_valid = 1; |
2201 | } | |
fbcfacb7 | 2202 | else if (place == NULL) |
a677feeb | 2203 | { |
fbcfacb7 | 2204 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2205 | reordering, in order to determine the base address for mips16 |
2206 | PC relative relocs. */ | |
4a1cb507 | 2207 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2208 | prev_insn = *ip; |
2209 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2210 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2211 | prev_insn_unreordered = 1; | |
a677feeb | 2212 | } |
3d3c5039 | 2213 | |
becfe05e | 2214 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2215 | mips_clear_insn_labels (); |
becfe05e ILT |
2216 | } |
2217 | ||
2218 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2219 | label. If PRESERVE is non-zero, it remembers enough information to |
2220 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2221 | |
2222 | static void | |
4a1cb507 ILT |
2223 | mips_no_prev_insn (preserve) |
2224 | int preserve; | |
becfe05e | 2225 | { |
4a1cb507 ILT |
2226 | if (! preserve) |
2227 | { | |
2228 | prev_insn.insn_mo = &dummy_opcode; | |
2229 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2230 | prev_nop_frag = NULL; | |
2231 | prev_nop_frag_holds = 0; | |
2232 | prev_nop_frag_required = 0; | |
2233 | prev_nop_frag_since = 0; | |
2234 | } | |
becfe05e ILT |
2235 | prev_insn_valid = 0; |
2236 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2237 | prev_insn_unreordered = 0; |
cc5703cd | 2238 | prev_insn_extended = 0; |
a677feeb | 2239 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2240 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2241 | mips_clear_insn_labels (); |
becfe05e ILT |
2242 | } |
2243 | ||
2244 | /* This function must be called whenever we turn on noreorder or emit | |
2245 | something other than instructions. It inserts any NOPS which might | |
2246 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2247 | kept for the previous instructions. The INSNS parameter is true if |
2248 | instructions are to follow. */ | |
becfe05e ILT |
2249 | |
2250 | static void | |
fbcfacb7 ILT |
2251 | mips_emit_delays (insns) |
2252 | boolean insns; | |
becfe05e | 2253 | { |
3c83da8a | 2254 | if (! mips_opts.noreorder) |
becfe05e | 2255 | { |
4a1cb507 | 2256 | int nops; |
becfe05e | 2257 | |
4a1cb507 | 2258 | nops = 0; |
3c83da8a JW |
2259 | if ((! mips_opts.mips16 |
2260 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2261 | && (! cop_interlocks |
2262 | && (prev_insn.insn_mo->pinfo | |
2263 | & (INSN_LOAD_COPROC_DELAY | |
2264 | | INSN_COPROC_MOVE_DELAY | |
2265 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2266 | || (! hilo_interlocks |
b2b8c24e ILT |
2267 | && (prev_insn.insn_mo->pinfo |
2268 | & (INSN_READ_LO | |
2269 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2270 | || (! mips_opts.mips16 |
2271 | && ! gpr_interlocks | |
2272 | && (prev_insn.insn_mo->pinfo | |
2273 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2274 | || (! mips_opts.mips16 |
2275 | && mips_opts.isa < 2 | |
8358c818 | 2276 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2277 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2278 | { |
efec4a28 | 2279 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2280 | ++nops; |
3c83da8a JW |
2281 | if ((! mips_opts.mips16 |
2282 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2283 | && (! cop_interlocks |
2284 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2285 | || (! hilo_interlocks |
b2b8c24e ILT |
2286 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2287 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2288 | ++nops; |
2289 | ||
2290 | if (prev_insn_unreordered) | |
2291 | nops = 0; | |
becfe05e | 2292 | } |
3c83da8a JW |
2293 | else if ((! mips_opts.mips16 |
2294 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2295 | && (! cop_interlocks |
2296 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2297 | || (! hilo_interlocks |
b2b8c24e ILT |
2298 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2299 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2300 | { |
efec4a28 | 2301 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2302 | if (! prev_prev_insn_unreordered) |
2303 | ++nops; | |
2304 | } | |
2305 | ||
2306 | if (nops > 0) | |
670a50eb | 2307 | { |
fbcfacb7 ILT |
2308 | struct insn_label_list *l; |
2309 | ||
4a1cb507 ILT |
2310 | if (insns) |
2311 | { | |
2312 | /* Record the frag which holds the nop instructions, so | |
2313 | that we can remove them if we don't need them. */ | |
3c83da8a | 2314 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2315 | prev_nop_frag = frag_now; |
2316 | prev_nop_frag_holds = nops; | |
2317 | prev_nop_frag_required = 0; | |
2318 | prev_nop_frag_since = 0; | |
2319 | } | |
2320 | ||
2321 | for (; nops > 0; --nops) | |
2322 | emit_nop (); | |
2323 | ||
2324 | if (insns) | |
2325 | { | |
2326 | /* Move on to a new frag, so that it is safe to simply | |
2327 | decrease the size of prev_nop_frag. */ | |
2328 | frag_wane (frag_now); | |
2329 | frag_new (0); | |
2330 | } | |
2331 | ||
fbcfacb7 | 2332 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2333 | { |
fbcfacb7 ILT |
2334 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2335 | l->label->sy_frag = frag_now; | |
2336 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2337 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2338 | if (mips_opts.mips16) |
fbcfacb7 | 2339 | ++l->label->sy_value.X_add_number; |
becfe05e | 2340 | } |
3d3c5039 ILT |
2341 | } |
2342 | } | |
0221ddf7 | 2343 | |
3c83da8a JW |
2344 | /* Mark instruction labels in mips16 mode. */ |
2345 | if (mips_opts.mips16 && insns) | |
2346 | mips16_mark_labels (); | |
fbcfacb7 | 2347 | |
4a1cb507 | 2348 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2349 | } |
2350 | ||
670a50eb ILT |
2351 | /* Build an instruction created by a macro expansion. This is passed |
2352 | a pointer to the count of instructions created so far, an | |
2353 | expression, the name of the instruction to build, an operand format | |
2354 | string, and corresponding arguments. */ | |
2355 | ||
1dc1e798 | 2356 | #ifdef USE_STDARG |
3d3c5039 | 2357 | static void |
0dd2d296 ILT |
2358 | macro_build (char *place, |
2359 | int *counter, | |
670a50eb | 2360 | expressionS * ep, |
3d3c5039 ILT |
2361 | const char *name, |
2362 | const char *fmt, | |
2363 | ...) | |
1dc1e798 | 2364 | #else |
3d3c5039 | 2365 | static void |
0dd2d296 ILT |
2366 | macro_build (place, counter, ep, name, fmt, va_alist) |
2367 | char *place; | |
3d3c5039 ILT |
2368 | int *counter; |
2369 | expressionS *ep; | |
2370 | const char *name; | |
2371 | const char *fmt; | |
2372 | va_dcl | |
1dc1e798 | 2373 | #endif |
3d3c5039 | 2374 | { |
670a50eb ILT |
2375 | struct mips_cl_insn insn; |
2376 | bfd_reloc_code_real_type r; | |
2377 | va_list args; | |
931a1858 | 2378 | int insn_isa; |
3d3c5039 | 2379 | |
1dc1e798 | 2380 | #ifdef USE_STDARG |
670a50eb | 2381 | va_start (args, fmt); |
3d3c5039 | 2382 | #else |
670a50eb | 2383 | va_start (args); |
3d3c5039 ILT |
2384 | #endif |
2385 | ||
670a50eb ILT |
2386 | /* |
2387 | * If the macro is about to expand into a second instruction, | |
2388 | * print a warning if needed. We need to pass ip as a parameter | |
2389 | * to generate a better warning message here... | |
2390 | */ | |
3c83da8a | 2391 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2392 | as_warn ("Macro instruction expanded into multiple instructions"); |
2393 | ||
0dd2d296 ILT |
2394 | if (place == NULL) |
2395 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2396 | |
3c83da8a | 2397 | if (mips_opts.mips16) |
cc5703cd ILT |
2398 | { |
2399 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2400 | va_end (args); | |
2401 | return; | |
2402 | } | |
2403 | ||
670a50eb ILT |
2404 | r = BFD_RELOC_UNUSED; |
2405 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2406 | assert (insn.insn_mo); | |
2407 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2408 | ||
931a1858 JL |
2409 | /* Search until we get a match for NAME. */ |
2410 | while (1) | |
670a50eb | 2411 | { |
1c6f3441 | 2412 | if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) |
931a1858 JL |
2413 | insn_isa = 1; |
2414 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) | |
2415 | insn_isa = 2; | |
2416 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) | |
2417 | insn_isa = 3; | |
2418 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) | |
2419 | insn_isa = 4; | |
2420 | else | |
2421 | insn_isa = 15; | |
2422 | ||
a652f74c ILT |
2423 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2424 | && insn.insn_mo->pinfo != INSN_MACRO | |
2425 | && (insn_isa <= mips_opts.isa | |
2426 | || (mips_4650 | |
2427 | && (insn.insn_mo->membership & INSN_4650) != 0) | |
2428 | || (mips_4010 | |
2429 | && (insn.insn_mo->membership & INSN_4010) != 0) | |
2430 | || (mips_4100 | |
2431 | && (insn.insn_mo->membership & INSN_4100) != 0) | |
42444087 GRK |
2432 | /* start-sanitize-tx49 */ |
2433 | || (mips_4900 | |
2434 | && (insn.insn_mo->membership & INSN_4900) != 0) | |
2435 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
2436 | /* start-sanitize-r5900 */ |
2437 | || (mips_5900 | |
2438 | && (insn.insn_mo->membership & INSN_5900) != 0) | |
2439 | /* end-sanitize-r5900 */ | |
aa2e0460 KR |
2440 | /* start-sanitize-vr5400 */ |
2441 | || (mips_5400 | |
2442 | && (insn.insn_mo->membership & INSN_5400) != 0) | |
2443 | /* end-sanitize-vr5400 */ | |
a652f74c ILT |
2444 | || (mips_3900 |
2445 | && (insn.insn_mo->membership & INSN_3900) != 0)) | |
2446 | /* start-sanitize-r5900 */ | |
2447 | && (! mips_5900 || (insn.insn_mo->pinfo & FP_D) == 0) | |
2448 | /* end-sanitize-r5900 */ | |
2449 | && (! mips_4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
2450 | break; | |
931a1858 | 2451 | |
a652f74c ILT |
2452 | ++insn.insn_mo; |
2453 | assert (insn.insn_mo->name); | |
2454 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2455 | } |
931a1858 | 2456 | |
670a50eb ILT |
2457 | insn.insn_opcode = insn.insn_mo->match; |
2458 | for (;;) | |
2459 | { | |
2460 | switch (*fmt++) | |
2461 | { | |
3d3c5039 | 2462 | case '\0': |
670a50eb | 2463 | break; |
3d3c5039 ILT |
2464 | |
2465 | case ',': | |
2466 | case '(': | |
2467 | case ')': | |
670a50eb | 2468 | continue; |
3d3c5039 ILT |
2469 | |
2470 | case 't': | |
2471 | case 'w': | |
918692a5 | 2472 | case 'E': |
670a50eb ILT |
2473 | insn.insn_opcode |= va_arg (args, int) << 16; |
2474 | continue; | |
3d3c5039 ILT |
2475 | |
2476 | case 'c': | |
2477 | case 'T': | |
2478 | case 'W': | |
670a50eb ILT |
2479 | insn.insn_opcode |= va_arg (args, int) << 16; |
2480 | continue; | |
3d3c5039 ILT |
2481 | |
2482 | case 'd': | |
918692a5 | 2483 | case 'G': |
670a50eb ILT |
2484 | insn.insn_opcode |= va_arg (args, int) << 11; |
2485 | continue; | |
3d3c5039 ILT |
2486 | |
2487 | case 'V': | |
2488 | case 'S': | |
670a50eb ILT |
2489 | insn.insn_opcode |= va_arg (args, int) << 11; |
2490 | continue; | |
3d3c5039 | 2491 | |
ff3a5c18 ILT |
2492 | case 'z': |
2493 | continue; | |
2494 | ||
3d3c5039 | 2495 | case '<': |
670a50eb ILT |
2496 | insn.insn_opcode |= va_arg (args, int) << 6; |
2497 | continue; | |
3d3c5039 ILT |
2498 | |
2499 | case 'D': | |
670a50eb ILT |
2500 | insn.insn_opcode |= va_arg (args, int) << 6; |
2501 | continue; | |
3d3c5039 | 2502 | |
918692a5 ILT |
2503 | case 'B': |
2504 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2505 | continue; | |
2506 | ||
3d3c5039 ILT |
2507 | case 'b': |
2508 | case 's': | |
2509 | case 'r': | |
2510 | case 'v': | |
670a50eb ILT |
2511 | insn.insn_opcode |= va_arg (args, int) << 21; |
2512 | continue; | |
3d3c5039 ILT |
2513 | |
2514 | case 'i': | |
2515 | case 'j': | |
2516 | case 'o': | |
9226253a | 2517 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2518 | assert (r == BFD_RELOC_MIPS_GPREL |
2519 | || r == BFD_RELOC_MIPS_LITERAL | |
2520 | || r == BFD_RELOC_LO16 | |
2521 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2522 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2523 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2524 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2525 | || (ep->X_op == O_subtract |
2526 | && now_seg == text_section | |
ecd4ca1c | 2527 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2528 | continue; |
3d3c5039 | 2529 | |
6e8dda9c | 2530 | case 'u': |
ecd4ca1c ILT |
2531 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2532 | assert (ep != NULL | |
2533 | && (ep->X_op == O_constant | |
2534 | || (ep->X_op == O_symbol | |
2535 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2536 | || r == BFD_RELOC_HI16 |
2537 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2538 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2539 | || (ep->X_op == O_subtract |
2540 | && now_seg == text_section | |
ecd4ca1c ILT |
2541 | && r == BFD_RELOC_PCREL_HI16_S))); |
2542 | if (ep->X_op == O_constant) | |
2543 | { | |
2544 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2545 | ep = NULL; | |
2546 | r = BFD_RELOC_UNUSED; | |
2547 | } | |
6e8dda9c ILT |
2548 | continue; |
2549 | ||
3d3c5039 | 2550 | case 'p': |
670a50eb ILT |
2551 | assert (ep != NULL); |
2552 | /* | |
2553 | * This allows macro() to pass an immediate expression for | |
2554 | * creating short branches without creating a symbol. | |
2555 | * Note that the expression still might come from the assembly | |
2556 | * input, in which case the value is not checked for range nor | |
2557 | * is a relocation entry generated (yuck). | |
2558 | */ | |
5ac34ac3 | 2559 | if (ep->X_op == O_constant) |
670a50eb ILT |
2560 | { |
2561 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2562 | ep = NULL; | |
2563 | } | |
2564 | else | |
2565 | r = BFD_RELOC_16_PCREL_S2; | |
2566 | continue; | |
3d3c5039 | 2567 | |
9226253a ILT |
2568 | case 'a': |
2569 | assert (ep != NULL); | |
2570 | r = BFD_RELOC_MIPS_JMP; | |
2571 | continue; | |
2572 | ||
3d3c5039 | 2573 | default: |
670a50eb | 2574 | internalError (); |
3d3c5039 | 2575 | } |
670a50eb | 2576 | break; |
3d3c5039 | 2577 | } |
670a50eb ILT |
2578 | va_end (args); |
2579 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2580 | ||
867a58b3 | 2581 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2582 | } |
2583 | ||
cc5703cd ILT |
2584 | static void |
2585 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2586 | char *place; | |
2587 | int *counter; | |
2588 | expressionS *ep; | |
2589 | const char *name; | |
2590 | const char *fmt; | |
2591 | va_list args; | |
2592 | { | |
2593 | struct mips_cl_insn insn; | |
2594 | bfd_reloc_code_real_type r; | |
2595 | ||
2596 | r = BFD_RELOC_UNUSED; | |
2597 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2598 | assert (insn.insn_mo); | |
2599 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2600 | ||
2601 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2602 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2603 | { | |
2604 | ++insn.insn_mo; | |
2605 | assert (insn.insn_mo->name); | |
2606 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2607 | } | |
2608 | ||
2609 | insn.insn_opcode = insn.insn_mo->match; | |
2610 | insn.use_extend = false; | |
2611 | ||
2612 | for (;;) | |
2613 | { | |
2614 | int c; | |
2615 | ||
2616 | c = *fmt++; | |
2617 | switch (c) | |
2618 | { | |
2619 | case '\0': | |
2620 | break; | |
2621 | ||
2622 | case ',': | |
2623 | case '(': | |
2624 | case ')': | |
2625 | continue; | |
2626 | ||
2627 | case 'y': | |
2628 | case 'w': | |
2629 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2630 | continue; | |
2631 | ||
2632 | case 'x': | |
2633 | case 'v': | |
2634 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2635 | continue; | |
2636 | ||
2637 | case 'z': | |
2638 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2639 | continue; | |
2640 | ||
2641 | case 'Z': | |
2642 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2643 | continue; | |
2644 | ||
2645 | case '0': | |
2646 | case 'S': | |
2647 | case 'P': | |
2648 | case 'R': | |
2649 | continue; | |
2650 | ||
2651 | case 'X': | |
2652 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2653 | continue; | |
2654 | ||
2655 | case 'Y': | |
2656 | { | |
2657 | int regno; | |
2658 | ||
2659 | regno = va_arg (args, int); | |
2660 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2661 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2662 | } | |
2663 | continue; | |
2664 | ||
2665 | case '<': | |
2666 | case '>': | |
2667 | case '4': | |
2668 | case '5': | |
2669 | case 'H': | |
2670 | case 'W': | |
2671 | case 'D': | |
2672 | case 'j': | |
2673 | case '8': | |
2674 | case 'V': | |
2675 | case 'C': | |
2676 | case 'U': | |
2677 | case 'k': | |
2678 | case 'K': | |
2679 | case 'p': | |
2680 | case 'q': | |
2681 | { | |
2682 | assert (ep != NULL); | |
2683 | ||
2684 | if (ep->X_op != O_constant) | |
2685 | r = BFD_RELOC_UNUSED + c; | |
2686 | else | |
2687 | { | |
15e69f98 ILT |
2688 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2689 | false, false, &insn.insn_opcode, | |
2690 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2691 | ep = NULL; |
2692 | r = BFD_RELOC_UNUSED; | |
2693 | } | |
2694 | } | |
2695 | continue; | |
2696 | ||
2697 | case '6': | |
2698 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2699 | continue; | |
2700 | } | |
2701 | ||
2702 | break; | |
2703 | } | |
2704 | ||
2705 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2706 | ||
2707 | append_insn (place, &insn, ep, r, false); | |
2708 | } | |
2709 | ||
3d3c5039 ILT |
2710 | /* |
2711 | * Generate a "lui" instruction. | |
2712 | */ | |
2713 | static void | |
0dd2d296 ILT |
2714 | macro_build_lui (place, counter, ep, regnum) |
2715 | char *place; | |
3d3c5039 ILT |
2716 | int *counter; |
2717 | expressionS *ep; | |
2718 | int regnum; | |
2719 | { | |
670a50eb ILT |
2720 | expressionS high_expr; |
2721 | struct mips_cl_insn insn; | |
2722 | bfd_reloc_code_real_type r; | |
2723 | CONST char *name = "lui"; | |
2724 | CONST char *fmt = "t,u"; | |
2725 | ||
3c83da8a | 2726 | assert (! mips_opts.mips16); |
cc5703cd | 2727 | |
0dd2d296 ILT |
2728 | if (place == NULL) |
2729 | high_expr = *ep; | |
2730 | else | |
2731 | { | |
2732 | high_expr.X_op = O_constant; | |
fb251650 | 2733 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2734 | } |
670a50eb | 2735 | |
5ac34ac3 | 2736 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2737 | { |
2738 | /* we can compute the instruction now without a relocation entry */ | |
2739 | if (high_expr.X_add_number & 0x8000) | |
2740 | high_expr.X_add_number += 0x10000; | |
2741 | high_expr.X_add_number = | |
2742 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2743 | r = BFD_RELOC_UNUSED; | |
2744 | } | |
2745 | else | |
0dd2d296 ILT |
2746 | { |
2747 | assert (ep->X_op == O_symbol); | |
2748 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2749 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2750 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2751 | r = BFD_RELOC_HI16_S; | |
2752 | } | |
670a50eb ILT |
2753 | |
2754 | /* | |
2755 | * If the macro is about to expand into a second instruction, | |
2756 | * print a warning if needed. We need to pass ip as a parameter | |
2757 | * to generate a better warning message here... | |
2758 | */ | |
3c83da8a | 2759 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2760 | as_warn ("Macro instruction expanded into multiple instructions"); |
2761 | ||
0dd2d296 ILT |
2762 | if (place == NULL) |
2763 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2764 | |
2765 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2766 | assert (insn.insn_mo); | |
2767 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2768 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2769 | ||
0dd2d296 | 2770 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2771 | if (r == BFD_RELOC_UNUSED) |
2772 | { | |
2773 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2774 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2775 | } |
2776 | else | |
867a58b3 | 2777 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2778 | } |
2779 | ||
2780 | /* set_at() | |
2781 | * Generates code to set the $at register to true (one) | |
2782 | * if reg is less than the immediate expression. | |
2783 | */ | |
2784 | static void | |
6e8dda9c | 2785 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2786 | int *counter; |
2787 | int reg; | |
6e8dda9c | 2788 | int unsignedp; |
3d3c5039 | 2789 | { |
5c6f5923 GRK |
2790 | if (imm_expr.X_op == O_constant |
2791 | && imm_expr.X_add_number >= -0x8000 | |
2792 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2793 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2794 | unsignedp ? "sltiu" : "slti", |
9226253a | 2795 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2796 | else |
670a50eb | 2797 | { |
d8a1c247 | 2798 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2799 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2800 | unsignedp ? "sltu" : "slt", |
2801 | "d,v,t", AT, reg, AT); | |
670a50eb | 2802 | } |
3d3c5039 ILT |
2803 | } |
2804 | ||
6e8dda9c | 2805 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2806 | |
2807 | static void | |
19ed8960 | 2808 | check_absolute_expr (ip, ex) |
3d3c5039 | 2809 | struct mips_cl_insn *ip; |
19ed8960 | 2810 | expressionS *ex; |
3d3c5039 | 2811 | { |
5c6f5923 GRK |
2812 | if (ex->X_op == O_big) |
2813 | as_bad ("unsupported large constant"); | |
2814 | else if (ex->X_op != O_constant) | |
4dc85508 | 2815 | as_bad ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2816 | } |
2817 | ||
ff8716f5 JSC |
2818 | /* Count the leading zeroes by performing a binary chop. This is a |
2819 | bulky bit of source, but performance is a LOT better for the | |
2820 | majority of values than a simple loop to count the bits: | |
2821 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2822 | if ((v) & (1 << (31 - lcnt))) | |
2823 | break; | |
2824 | However it is not code size friendly, and the gain will drop a bit | |
2825 | on certain cached systems. | |
2826 | */ | |
2827 | #define COUNT_TOP_ZEROES(v) \ | |
2828 | (((v) & ~0xffff) == 0 \ | |
2829 | ? ((v) & ~0xff) == 0 \ | |
2830 | ? ((v) & ~0xf) == 0 \ | |
2831 | ? ((v) & ~0x3) == 0 \ | |
2832 | ? ((v) & ~0x1) == 0 \ | |
2833 | ? !(v) \ | |
2834 | ? 32 \ | |
2835 | : 31 \ | |
2836 | : 30 \ | |
2837 | : ((v) & ~0x7) == 0 \ | |
2838 | ? 29 \ | |
2839 | : 28 \ | |
2840 | : ((v) & ~0x3f) == 0 \ | |
2841 | ? ((v) & ~0x1f) == 0 \ | |
2842 | ? 27 \ | |
2843 | : 26 \ | |
2844 | : ((v) & ~0x7f) == 0 \ | |
2845 | ? 25 \ | |
2846 | : 24 \ | |
2847 | : ((v) & ~0xfff) == 0 \ | |
2848 | ? ((v) & ~0x3ff) == 0 \ | |
2849 | ? ((v) & ~0x1ff) == 0 \ | |
2850 | ? 23 \ | |
2851 | : 22 \ | |
2852 | : ((v) & ~0x7ff) == 0 \ | |
2853 | ? 21 \ | |
2854 | : 20 \ | |
2855 | : ((v) & ~0x3fff) == 0 \ | |
2856 | ? ((v) & ~0x1fff) == 0 \ | |
2857 | ? 19 \ | |
2858 | : 18 \ | |
2859 | : ((v) & ~0x7fff) == 0 \ | |
2860 | ? 17 \ | |
2861 | : 16 \ | |
2862 | : ((v) & ~0xffffff) == 0 \ | |
2863 | ? ((v) & ~0xfffff) == 0 \ | |
2864 | ? ((v) & ~0x3ffff) == 0 \ | |
2865 | ? ((v) & ~0x1ffff) == 0 \ | |
2866 | ? 15 \ | |
2867 | : 14 \ | |
2868 | : ((v) & ~0x7ffff) == 0 \ | |
2869 | ? 13 \ | |
2870 | : 12 \ | |
2871 | : ((v) & ~0x3fffff) == 0 \ | |
2872 | ? ((v) & ~0x1fffff) == 0 \ | |
2873 | ? 11 \ | |
2874 | : 10 \ | |
2875 | : ((v) & ~0x7fffff) == 0 \ | |
2876 | ? 9 \ | |
2877 | : 8 \ | |
2878 | : ((v) & ~0xfffffff) == 0 \ | |
2879 | ? ((v) & ~0x3ffffff) == 0 \ | |
2880 | ? ((v) & ~0x1ffffff) == 0 \ | |
2881 | ? 7 \ | |
2882 | : 6 \ | |
2883 | : ((v) & ~0x7ffffff) == 0 \ | |
2884 | ? 5 \ | |
2885 | : 4 \ | |
2886 | : ((v) & ~0x3fffffff) == 0 \ | |
2887 | ? ((v) & ~0x1fffffff) == 0 \ | |
2888 | ? 3 \ | |
2889 | : 2 \ | |
2890 | : ((v) & ~0x7fffffff) == 0 \ | |
2891 | ? 1 \ | |
2892 | : 0) | |
2893 | ||
3d3c5039 ILT |
2894 | /* load_register() |
2895 | * This routine generates the least number of instructions neccessary to load | |
2896 | * an absolute expression value into a register. | |
2897 | */ | |
2898 | static void | |
d8a1c247 | 2899 | load_register (counter, reg, ep, dbl) |
670a50eb | 2900 | int *counter; |
670a50eb ILT |
2901 | int reg; |
2902 | expressionS *ep; | |
d8a1c247 | 2903 | int dbl; |
3d3c5039 | 2904 | { |
c36a90ef ILT |
2905 | int freg; |
2906 | expressionS hi32, lo32; | |
847a01cd ILT |
2907 | |
2908 | if (ep->X_op != O_big) | |
6e8dda9c | 2909 | { |
847a01cd | 2910 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2911 | if (ep->X_add_number < 0x8000 |
2912 | && (ep->X_add_number >= 0 | |
2913 | || (ep->X_add_number >= -0x8000 | |
2914 | && (! dbl | |
2915 | || ! ep->X_unsigned | |
2916 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2917 | { |
2918 | /* We can handle 16 bit signed values with an addiu to | |
2919 | $zero. No need to ever use daddiu here, since $zero and | |
2920 | the result are always correct in 32 bit mode. */ | |
2921 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2922 | (int) BFD_RELOC_LO16); | |
2923 | return; | |
2924 | } | |
2925 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2926 | { | |
2927 | /* We can handle 16 bit unsigned values with an ori to | |
2928 | $zero. */ | |
2929 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2930 | (int) BFD_RELOC_LO16); | |
2931 | return; | |
2932 | } | |
98bfd087 ILT |
2933 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2934 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2935 | == ~ (offsetT) 0x7fffffff)) | |
2936 | && (! dbl | |
2937 | || ! ep->X_unsigned | |
2938 | || sizeof (ep->X_add_number) > 4 | |
2939 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 2940 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 2941 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 2942 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
2943 | && ! dbl |
2944 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
2945 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
2946 | { |
2947 | /* 32 bit values require an lui. */ | |
2948 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2949 | (int) BFD_RELOC_HI16); | |
2950 | if ((ep->X_add_number & 0xffff) != 0) | |
2951 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2952 | (int) BFD_RELOC_LO16); | |
2953 | return; | |
2954 | } | |
6e8dda9c | 2955 | } |
847a01cd ILT |
2956 | |
2957 | /* The value is larger than 32 bits. */ | |
2958 | ||
3c83da8a | 2959 | if (mips_opts.isa < 3) |
670a50eb | 2960 | { |
6e8dda9c | 2961 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2962 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2963 | (int) BFD_RELOC_LO16); |
847a01cd | 2964 | return; |
6e8dda9c | 2965 | } |
6e8dda9c | 2966 | |
847a01cd ILT |
2967 | if (ep->X_op != O_big) |
2968 | { | |
6e8dda9c | 2969 | hi32 = *ep; |
c36a90ef ILT |
2970 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2971 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2972 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2973 | lo32 = *ep; |
2974 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2975 | } |
847a01cd ILT |
2976 | else |
2977 | { | |
2978 | assert (ep->X_add_number > 2); | |
2979 | if (ep->X_add_number == 3) | |
2980 | generic_bignum[3] = 0; | |
2981 | else if (ep->X_add_number > 4) | |
2982 | as_bad ("Number larger than 64 bits"); | |
2983 | lo32.X_op = O_constant; | |
2984 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2985 | hi32.X_op = O_constant; | |
2986 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2987 | } | |
2988 | ||
d8a1c247 KR |
2989 | if (hi32.X_add_number == 0) |
2990 | freg = 0; | |
2991 | else | |
2992 | { | |
c36a90ef ILT |
2993 | int shift, bit; |
2994 | unsigned long hi, lo; | |
2995 | ||
fb251650 ILT |
2996 | if (hi32.X_add_number == 0xffffffff) |
2997 | { | |
2998 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2999 | { | |
c36a90ef ILT |
3000 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
3001 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3002 | return; |
3003 | } | |
3004 | if (lo32.X_add_number & 0x80000000) | |
3005 | { | |
3006 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3007 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
3008 | if (lo32.X_add_number & 0xffff) |
3009 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3010 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3011 | return; |
3012 | } | |
3013 | } | |
ff8716f5 | 3014 | |
c36a90ef ILT |
3015 | /* Check for 16bit shifted constant. We know that hi32 is |
3016 | non-zero, so start the mask on the first bit of the hi32 | |
3017 | value. */ | |
ff8716f5 JSC |
3018 | shift = 17; |
3019 | do | |
3020 | { | |
c36a90ef ILT |
3021 | unsigned long himask, lomask; |
3022 | ||
3023 | if (shift < 32) | |
3024 | { | |
3025 | himask = 0xffff >> (32 - shift); | |
3026 | lomask = (0xffff << shift) & 0xffffffff; | |
3027 | } | |
3028 | else | |
3029 | { | |
3030 | himask = 0xffff << (shift - 32); | |
3031 | lomask = 0; | |
3032 | } | |
3033 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3034 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3035 | { | |
3036 | expressionS tmp; | |
3037 | ||
3038 | tmp.X_op = O_constant; | |
3039 | if (shift < 32) | |
3040 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3041 | | (lo32.X_add_number >> shift)); | |
3042 | else | |
3043 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3044 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3045 | (int) BFD_RELOC_LO16); | |
3046 | macro_build ((char *) NULL, counter, NULL, | |
3047 | (shift >= 32) ? "dsll32" : "dsll", | |
3048 | "d,w,<", reg, reg, | |
3049 | (shift >= 32) ? shift - 32 : shift); | |
3050 | return; | |
3051 | } | |
ff8716f5 JSC |
3052 | shift++; |
3053 | } while (shift <= (64 - 16)); | |
3054 | ||
c36a90ef ILT |
3055 | /* Find the bit number of the lowest one bit, and store the |
3056 | shifted value in hi/lo. */ | |
3057 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3058 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3059 | if (lo != 0) | |
3060 | { | |
3061 | bit = 0; | |
3062 | while ((lo & 1) == 0) | |
3063 | { | |
3064 | lo >>= 1; | |
3065 | ++bit; | |
3066 | } | |
3067 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3068 | hi >>= bit; | |
3069 | } | |
3070 | else | |
3071 | { | |
3072 | bit = 32; | |
3073 | while ((hi & 1) == 0) | |
3074 | { | |
3075 | hi >>= 1; | |
3076 | ++bit; | |
3077 | } | |
3078 | lo = hi; | |
3079 | hi = 0; | |
3080 | } | |
3081 | ||
3082 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3083 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3084 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3085 | { |
c36a90ef | 3086 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3087 | if (shift != 0) |
3088 | { | |
c36a90ef ILT |
3089 | expressionS tmp; |
3090 | ||
3091 | /* This instruction will set the register to be all | |
3092 | ones. */ | |
ff8716f5 | 3093 | tmp.X_op = O_constant; |
c36a90ef ILT |
3094 | tmp.X_add_number = (offsetT) -1; |
3095 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3096 | reg, 0, (int) BFD_RELOC_LO16); | |
3097 | if (bit != 0) | |
ff8716f5 | 3098 | { |
c36a90ef | 3099 | bit += shift; |
ff8716f5 | 3100 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3101 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3102 | "d,w,<", reg, reg, |
c36a90ef | 3103 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3104 | } |
c36a90ef ILT |
3105 | macro_build ((char *) NULL, counter, NULL, |
3106 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3107 | "d,w,<", reg, reg, | |
3108 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3109 | return; |
3110 | } | |
3111 | } | |
c36a90ef ILT |
3112 | |
3113 | /* Sign extend hi32 before calling load_register, because we can | |
3114 | generally get better code when we load a sign extended value. */ | |
3115 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3116 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3117 | load_register (counter, reg, &hi32, 0); |
3118 | freg = reg; | |
3119 | } | |
847a01cd | 3120 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3121 | { |
3122 | if (freg != 0) | |
3123 | { | |
3124 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3125 | freg, 0); | |
3126 | freg = reg; | |
3127 | } | |
3128 | } | |
847a01cd ILT |
3129 | else |
3130 | { | |
3131 | expressionS mid16; | |
3132 | ||
fb251650 ILT |
3133 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3134 | { | |
3135 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3136 | (int) BFD_RELOC_HI16); | |
3137 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3138 | reg, 0); |
fb251650 ILT |
3139 | return; |
3140 | } | |
3141 | ||
d8a1c247 KR |
3142 | if (freg != 0) |
3143 | { | |
3144 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3145 | freg, 16); | |
3146 | freg = reg; | |
3147 | } | |
847a01cd ILT |
3148 | mid16 = lo32; |
3149 | mid16.X_add_number >>= 16; | |
3150 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3151 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3152 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3153 | reg, 16); | |
d8a1c247 | 3154 | freg = reg; |
847a01cd ILT |
3155 | } |
3156 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3157 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3158 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3159 | } |
3160 | ||
0dd2d296 ILT |
3161 | /* Load an address into a register. */ |
3162 | ||
3163 | static void | |
3164 | load_address (counter, reg, ep) | |
3165 | int *counter; | |
3166 | int reg; | |
3167 | expressionS *ep; | |
3168 | { | |
3169 | char *p; | |
3170 | ||
3171 | if (ep->X_op != O_constant | |
3172 | && ep->X_op != O_symbol) | |
3173 | { | |
3174 | as_bad ("expression too complex"); | |
3175 | ep->X_op = O_constant; | |
3176 | } | |
3177 | ||
3178 | if (ep->X_op == O_constant) | |
d9aba805 | 3179 | { |
d8a1c247 | 3180 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3181 | return; |
3182 | } | |
3183 | ||
3184 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3185 | { |
3186 | /* If this is a reference to a GP relative symbol, we want | |
3187 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3188 | Otherwise we want | |
04cb3372 | 3189 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3190 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3191 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3192 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3193 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3194 | p = NULL; |
3195 | else | |
3196 | { | |
8ea7f4e8 | 3197 | frag_grow (20); |
0dd2d296 | 3198 | macro_build ((char *) NULL, counter, ep, |
3c83da8a | 3199 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3200 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3201 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3202 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3203 | mips_opts.warn_about_macros), | |
f59fb6ca | 3204 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3205 | } |
3206 | macro_build_lui (p, counter, ep, reg); | |
3207 | if (p != NULL) | |
3208 | p += 4; | |
3209 | macro_build (p, counter, ep, | |
3c83da8a | 3210 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3211 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3212 | } | |
fb251650 | 3213 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3214 | { |
3215 | expressionS ex; | |
3216 | ||
3217 | /* If this is a reference to an external symbol, we want | |
3218 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3219 | Otherwise we want | |
3220 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3221 | nop | |
3222 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3223 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3224 | ex.X_add_number = ep->X_add_number; |
3225 | ep->X_add_number = 0; | |
8ea7f4e8 | 3226 | frag_grow (20); |
0dd2d296 | 3227 | macro_build ((char *) NULL, counter, ep, |
3c83da8a | 3228 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
3229 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3230 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3231 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3232 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3233 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3234 | macro_build (p, counter, ep, |
3c83da8a | 3235 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3236 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3237 | if (ex.X_add_number != 0) | |
3238 | { | |
3239 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3240 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3241 | ex.X_op = O_constant; | |
fb251650 | 3242 | macro_build ((char *) NULL, counter, &ex, |
3c83da8a | 3243 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
3244 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3245 | } | |
3246 | } | |
3247 | else if (mips_pic == SVR4_PIC) | |
3248 | { | |
3249 | expressionS ex; | |
3250 | int off; | |
3251 | ||
3252 | /* This is the large GOT case. If this is a reference to an | |
3253 | external symbol, we want | |
3254 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3255 | addu $reg,$reg,$gp | |
3256 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3257 | Otherwise, for a reference to a local symbol, we want | |
3258 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3259 | nop | |
3260 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3261 | If there is a constant, it must be added in after. */ | |
3262 | ex.X_add_number = ep->X_add_number; | |
3263 | ep->X_add_number = 0; | |
3264 | if (reg_needs_delay (GP)) | |
3265 | off = 4; | |
3266 | else | |
3267 | off = 0; | |
3268 | frag_grow (32); | |
3269 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3270 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3271 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3c83da8a | 3272 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
3273 | "d,v,t", reg, reg, GP); |
3274 | macro_build ((char *) NULL, counter, ep, | |
3c83da8a | 3275 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
3276 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3277 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3278 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3279 | mips_opts.warn_about_macros), |
f59fb6ca | 3280 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3281 | if (off > 0) |
3282 | { | |
3283 | /* We need a nop before loading from $gp. This special | |
3284 | check is required because the lui which starts the main | |
3285 | instruction stream does not refer to $gp, and so will not | |
3286 | insert the nop which may be required. */ | |
3287 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3288 | p += 4; | |
3289 | } | |
3290 | macro_build (p, counter, ep, | |
3c83da8a | 3291 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
3292 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3293 | p += 4; | |
3294 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3295 | p += 4; | |
3296 | macro_build (p, counter, ep, | |
3c83da8a | 3297 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
3298 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3299 | if (ex.X_add_number != 0) | |
3300 | { | |
3301 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3302 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3303 | ex.X_op = O_constant; | |
3304 | macro_build ((char *) NULL, counter, &ex, | |
3c83da8a | 3305 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3306 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3307 | } | |
d9aba805 ILT |
3308 | } |
3309 | else if (mips_pic == EMBEDDED_PIC) | |
3310 | { | |
3311 | /* We always do | |
3312 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3313 | */ | |
3314 | macro_build ((char *) NULL, counter, ep, | |
3c83da8a | 3315 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
3316 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3317 | } | |
3318 | else | |
3319 | abort (); | |
0dd2d296 ILT |
3320 | } |
3321 | ||
3d3c5039 ILT |
3322 | /* |
3323 | * Build macros | |
3324 | * This routine implements the seemingly endless macro or synthesized | |
3325 | * instructions and addressing modes in the mips assembly language. Many | |
3326 | * of these macros are simple and are similar to each other. These could | |
3327 | * probably be handled by some kind of table or grammer aproach instead of | |
3328 | * this verbose method. Others are not simple macros but are more like | |
3329 | * optimizing code generation. | |
3330 | * One interesting optimization is when several store macros appear | |
3331 | * consecutivly that would load AT with the upper half of the same address. | |
3332 | * The ensuing load upper instructions are ommited. This implies some kind | |
3333 | * of global optimization. We currently only optimize within a single macro. | |
3334 | * For many of the load and store macros if the address is specified as a | |
3335 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3336 | * first load register 'at' with zero and use it as the base register. The | |
3337 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3338 | * we're missing. | |
3339 | */ | |
3340 | static void | |
3341 | macro (ip) | |
3342 | struct mips_cl_insn *ip; | |
3343 | { | |
670a50eb ILT |
3344 | register int treg, sreg, dreg, breg; |
3345 | int tempreg; | |
3346 | int mask; | |
3347 | int icnt = 0; | |
3348 | int used_at; | |
670a50eb ILT |
3349 | expressionS expr1; |
3350 | const char *s; | |
8358c818 | 3351 | const char *s2; |
670a50eb | 3352 | const char *fmt; |
8358c818 ILT |
3353 | int likely = 0; |
3354 | int dbl = 0; | |
3355 | int coproc = 0; | |
b2b8c24e | 3356 | int lr = 0; |
6e8dda9c | 3357 | offsetT maxnum; |
adcf2b9d | 3358 | int off; |
9226253a | 3359 | bfd_reloc_code_real_type r; |
0dd2d296 | 3360 | char *p; |
55933a58 | 3361 | int hold_mips_optimize; |
670a50eb | 3362 | |
3c83da8a | 3363 | assert (! mips_opts.mips16); |
cc5703cd | 3364 | |
670a50eb ILT |
3365 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3366 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3367 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3368 | mask = ip->insn_mo->mask; | |
3369 | ||
5ac34ac3 ILT |
3370 | expr1.X_op = O_constant; |
3371 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3372 | expr1.X_add_symbol = NULL; |
3373 | expr1.X_add_number = 1; | |
3374 | ||
3375 | switch (mask) | |
3376 | { | |
6e8dda9c ILT |
3377 | case M_DABS: |
3378 | dbl = 1; | |
3d3c5039 | 3379 | case M_ABS: |
6e8dda9c ILT |
3380 | /* bgez $a0,.+12 |
3381 | move v0,$a0 | |
3382 | sub v0,$zero,$a0 | |
3383 | */ | |
3d3c5039 | 3384 | |
fbcfacb7 | 3385 | mips_emit_delays (true); |
3c83da8a | 3386 | ++mips_opts.noreorder; |
0dd2d296 | 3387 | mips_any_noreorder = 1; |
3d3c5039 | 3388 | |
670a50eb | 3389 | expr1.X_add_number = 8; |
0dd2d296 | 3390 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3391 | if (dreg == sreg) |
0dd2d296 | 3392 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3393 | else |
0dd2d296 ILT |
3394 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3395 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3396 | dbl ? "dsub" : "sub", |
3397 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3398 | |
3c83da8a | 3399 | --mips_opts.noreorder; |
670a50eb | 3400 | return; |
3d3c5039 ILT |
3401 | |
3402 | case M_ADD_I: | |
8358c818 ILT |
3403 | s = "addi"; |
3404 | s2 = "add"; | |
3405 | goto do_addi; | |
3d3c5039 | 3406 | case M_ADDU_I: |
8358c818 ILT |
3407 | s = "addiu"; |
3408 | s2 = "addu"; | |
3409 | goto do_addi; | |
3410 | case M_DADD_I: | |
6e8dda9c | 3411 | dbl = 1; |
8358c818 ILT |
3412 | s = "daddi"; |
3413 | s2 = "dadd"; | |
3414 | goto do_addi; | |
3415 | case M_DADDU_I: | |
6e8dda9c | 3416 | dbl = 1; |
8358c818 ILT |
3417 | s = "daddiu"; |
3418 | s2 = "daddu"; | |
3419 | do_addi: | |
5c6f5923 GRK |
3420 | if (imm_expr.X_op == O_constant |
3421 | && imm_expr.X_add_number >= -0x8000 | |
3422 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3423 | { |
0dd2d296 | 3424 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3425 | (int) BFD_RELOC_LO16); |
670a50eb | 3426 | return; |
3d3c5039 | 3427 | } |
d8a1c247 | 3428 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3429 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3430 | break; |
3d3c5039 ILT |
3431 | |
3432 | case M_AND_I: | |
6e8dda9c ILT |
3433 | s = "andi"; |
3434 | s2 = "and"; | |
3435 | goto do_bit; | |
3d3c5039 | 3436 | case M_OR_I: |
6e8dda9c ILT |
3437 | s = "ori"; |
3438 | s2 = "or"; | |
3439 | goto do_bit; | |
3d3c5039 | 3440 | case M_NOR_I: |
6e8dda9c ILT |
3441 | s = ""; |
3442 | s2 = "nor"; | |
3443 | goto do_bit; | |
3d3c5039 | 3444 | case M_XOR_I: |
6e8dda9c ILT |
3445 | s = "xori"; |
3446 | s2 = "xor"; | |
3447 | do_bit: | |
5c6f5923 GRK |
3448 | if (imm_expr.X_op == O_constant |
3449 | && imm_expr.X_add_number >= 0 | |
3450 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3451 | { |
6e8dda9c | 3452 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3453 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3454 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3455 | else |
670a50eb | 3456 | { |
0dd2d296 ILT |
3457 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3458 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3459 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3460 | treg, treg, 0); |
3d3c5039 | 3461 | } |
6e8dda9c | 3462 | return; |
3d3c5039 | 3463 | } |
6e8dda9c | 3464 | |
d8a1c247 | 3465 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3466 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3467 | break; |
3d3c5039 ILT |
3468 | |
3469 | case M_BEQ_I: | |
8358c818 ILT |
3470 | s = "beq"; |
3471 | goto beq_i; | |
3472 | case M_BEQL_I: | |
3473 | s = "beql"; | |
3474 | likely = 1; | |
3475 | goto beq_i; | |
3d3c5039 | 3476 | case M_BNE_I: |
8358c818 ILT |
3477 | s = "bne"; |
3478 | goto beq_i; | |
3479 | case M_BNEL_I: | |
3480 | s = "bnel"; | |
3481 | likely = 1; | |
3482 | beq_i: | |
5c6f5923 | 3483 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3484 | { |
0dd2d296 ILT |
3485 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3486 | 0); | |
670a50eb ILT |
3487 | return; |
3488 | } | |
d8a1c247 | 3489 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3490 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3491 | break; |
3d3c5039 | 3492 | |
8358c818 ILT |
3493 | case M_BGEL: |
3494 | likely = 1; | |
3d3c5039 | 3495 | case M_BGE: |
670a50eb ILT |
3496 | if (treg == 0) |
3497 | { | |
0dd2d296 | 3498 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3499 | likely ? "bgezl" : "bgez", |
3500 | "s,p", sreg); | |
670a50eb | 3501 | return; |
3d3c5039 | 3502 | } |
9a7d824a ILT |
3503 | if (sreg == 0) |
3504 | { | |
0dd2d296 | 3505 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3506 | likely ? "blezl" : "blez", |
3507 | "s,p", treg); | |
9a7d824a ILT |
3508 | return; |
3509 | } | |
0dd2d296 ILT |
3510 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3511 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3512 | likely ? "beql" : "beq", |
3513 | "s,t,p", AT, 0); | |
670a50eb | 3514 | break; |
3d3c5039 | 3515 | |
8358c818 ILT |
3516 | case M_BGTL_I: |
3517 | likely = 1; | |
3d3c5039 | 3518 | case M_BGT_I: |
9a7d824a | 3519 | /* check for > max integer */ |
6e8dda9c | 3520 | maxnum = 0x7fffffff; |
5c6f5923 | 3521 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3522 | { |
3523 | maxnum <<= 16; | |
3524 | maxnum |= 0xffff; | |
3525 | maxnum <<= 16; | |
3526 | maxnum |= 0xffff; | |
3527 | } | |
5c6f5923 GRK |
3528 | if (imm_expr.X_op == O_constant |
3529 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3530 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3531 | { |
3532 | do_false: | |
3533 | /* result is always false */ | |
8358c818 ILT |
3534 | if (! likely) |
3535 | { | |
3536 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3537 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3538 | } |
3539 | else | |
3540 | { | |
3541 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3542 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3543 | "s,t,p", 0, 0); | |
8358c818 | 3544 | } |
9a7d824a ILT |
3545 | return; |
3546 | } | |
5c6f5923 GRK |
3547 | if (imm_expr.X_op != O_constant) |
3548 | as_bad ("Unsupported large constant"); | |
670a50eb ILT |
3549 | imm_expr.X_add_number++; |
3550 | /* FALLTHROUGH */ | |
3d3c5039 | 3551 | case M_BGE_I: |
8358c818 ILT |
3552 | case M_BGEL_I: |
3553 | if (mask == M_BGEL_I) | |
3554 | likely = 1; | |
5c6f5923 | 3555 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3556 | { |
0dd2d296 | 3557 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3558 | likely ? "bgezl" : "bgez", |
3559 | "s,p", sreg); | |
670a50eb | 3560 | return; |
3d3c5039 | 3561 | } |
5c6f5923 | 3562 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3563 | { |
0dd2d296 | 3564 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3565 | likely ? "bgtzl" : "bgtz", |
3566 | "s,p", sreg); | |
670a50eb | 3567 | return; |
3d3c5039 | 3568 | } |
6e8dda9c | 3569 | maxnum = 0x7fffffff; |
5c6f5923 | 3570 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3571 | { |
3572 | maxnum <<= 16; | |
3573 | maxnum |= 0xffff; | |
3574 | maxnum <<= 16; | |
3575 | maxnum |= 0xffff; | |
3576 | } | |
3577 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3578 | if (imm_expr.X_op == O_constant |
3579 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3580 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3581 | { |
3582 | do_true: | |
3583 | /* result is always true */ | |
3584 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3585 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3586 | return; |
3587 | } | |
6e8dda9c | 3588 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3589 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3590 | likely ? "beql" : "beq", |
3591 | "s,t,p", AT, 0); | |
670a50eb | 3592 | break; |
3d3c5039 | 3593 | |
8358c818 ILT |
3594 | case M_BGEUL: |
3595 | likely = 1; | |
3d3c5039 | 3596 | case M_BGEU: |
670a50eb | 3597 | if (treg == 0) |
9a7d824a ILT |
3598 | goto do_true; |
3599 | if (sreg == 0) | |
670a50eb | 3600 | { |
0dd2d296 | 3601 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3602 | likely ? "beql" : "beq", |
3603 | "s,t,p", 0, treg); | |
670a50eb | 3604 | return; |
3d3c5039 | 3605 | } |
0dd2d296 ILT |
3606 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3607 | treg); | |
3608 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3609 | likely ? "beql" : "beq", |
3610 | "s,t,p", AT, 0); | |
670a50eb | 3611 | break; |
3d3c5039 | 3612 | |
8358c818 ILT |
3613 | case M_BGTUL_I: |
3614 | likely = 1; | |
9a7d824a | 3615 | case M_BGTU_I: |
5c6f5923 GRK |
3616 | if (sreg == 0 |
3617 | || (mips_opts.isa < 3 | |
3618 | && imm_expr.X_op == O_constant | |
3619 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3620 | goto do_false; |
5c6f5923 GRK |
3621 | if (imm_expr.X_op != O_constant) |
3622 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3623 | imm_expr.X_add_number++; |
3624 | /* FALLTHROUGH */ | |
3d3c5039 | 3625 | case M_BGEU_I: |
8358c818 ILT |
3626 | case M_BGEUL_I: |
3627 | if (mask == M_BGEUL_I) | |
3628 | likely = 1; | |
5c6f5923 | 3629 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3630 | goto do_true; |
5c6f5923 | 3631 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3632 | { |
0dd2d296 | 3633 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3634 | likely ? "bnel" : "bne", |
3635 | "s,t,p", sreg, 0); | |
670a50eb | 3636 | return; |
3d3c5039 | 3637 | } |
6e8dda9c | 3638 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3639 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3640 | likely ? "beql" : "beq", |
3641 | "s,t,p", AT, 0); | |
670a50eb | 3642 | break; |
3d3c5039 | 3643 | |
8358c818 ILT |
3644 | case M_BGTL: |
3645 | likely = 1; | |
3d3c5039 | 3646 | case M_BGT: |
670a50eb ILT |
3647 | if (treg == 0) |
3648 | { | |
0dd2d296 | 3649 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3650 | likely ? "bgtzl" : "bgtz", |
3651 | "s,p", sreg); | |
670a50eb | 3652 | return; |
3d3c5039 | 3653 | } |
9a7d824a ILT |
3654 | if (sreg == 0) |
3655 | { | |
0dd2d296 | 3656 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3657 | likely ? "bltzl" : "bltz", |
3658 | "s,p", treg); | |
9a7d824a ILT |
3659 | return; |
3660 | } | |
0dd2d296 ILT |
3661 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3662 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3663 | likely ? "bnel" : "bne", |
3664 | "s,t,p", AT, 0); | |
670a50eb | 3665 | break; |
3d3c5039 | 3666 | |
8358c818 ILT |
3667 | case M_BGTUL: |
3668 | likely = 1; | |
3d3c5039 | 3669 | case M_BGTU: |
670a50eb ILT |
3670 | if (treg == 0) |
3671 | { | |
0dd2d296 | 3672 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3673 | likely ? "bnel" : "bne", |
3674 | "s,t,p", sreg, 0); | |
670a50eb | 3675 | return; |
3d3c5039 | 3676 | } |
9a7d824a ILT |
3677 | if (sreg == 0) |
3678 | goto do_false; | |
0dd2d296 ILT |
3679 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3680 | sreg); | |
3681 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3682 | likely ? "bnel" : "bne", |
3683 | "s,t,p", AT, 0); | |
670a50eb | 3684 | break; |
3d3c5039 | 3685 | |
8358c818 ILT |
3686 | case M_BLEL: |
3687 | likely = 1; | |
3d3c5039 | 3688 | case M_BLE: |
670a50eb ILT |
3689 | if (treg == 0) |
3690 | { | |
0dd2d296 | 3691 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3692 | likely ? "blezl" : "blez", |
3693 | "s,p", sreg); | |
670a50eb ILT |
3694 | return; |
3695 | } | |
9a7d824a ILT |
3696 | if (sreg == 0) |
3697 | { | |
0dd2d296 | 3698 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3699 | likely ? "bgezl" : "bgez", |
3700 | "s,p", treg); | |
9a7d824a ILT |
3701 | return; |
3702 | } | |
0dd2d296 ILT |
3703 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3704 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3705 | likely ? "beql" : "beq", |
3706 | "s,t,p", AT, 0); | |
670a50eb | 3707 | break; |
3d3c5039 | 3708 | |
8358c818 ILT |
3709 | case M_BLEL_I: |
3710 | likely = 1; | |
3d3c5039 | 3711 | case M_BLE_I: |
6e8dda9c | 3712 | maxnum = 0x7fffffff; |
5c6f5923 | 3713 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3714 | { |
3715 | maxnum <<= 16; | |
3716 | maxnum |= 0xffff; | |
3717 | maxnum <<= 16; | |
3718 | maxnum |= 0xffff; | |
3719 | } | |
5c6f5923 GRK |
3720 | if (imm_expr.X_op == O_constant |
3721 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3722 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3723 | goto do_true; |
5c6f5923 GRK |
3724 | if (imm_expr.X_op != O_constant) |
3725 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3726 | imm_expr.X_add_number++; |
3727 | /* FALLTHROUGH */ | |
9a7d824a | 3728 | case M_BLT_I: |
8358c818 ILT |
3729 | case M_BLTL_I: |
3730 | if (mask == M_BLTL_I) | |
3731 | likely = 1; | |
5c6f5923 | 3732 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3733 | { |
0dd2d296 | 3734 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3735 | likely ? "bltzl" : "bltz", |
3736 | "s,p", sreg); | |
670a50eb ILT |
3737 | return; |
3738 | } | |
5c6f5923 | 3739 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3740 | { |
0dd2d296 | 3741 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3742 | likely ? "blezl" : "blez", |
3743 | "s,p", sreg); | |
670a50eb ILT |
3744 | return; |
3745 | } | |
6e8dda9c | 3746 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3747 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3748 | likely ? "bnel" : "bne", |
3749 | "s,t,p", AT, 0); | |
670a50eb | 3750 | break; |
3d3c5039 | 3751 | |
8358c818 ILT |
3752 | case M_BLEUL: |
3753 | likely = 1; | |
3d3c5039 | 3754 | case M_BLEU: |
670a50eb ILT |
3755 | if (treg == 0) |
3756 | { | |
0dd2d296 | 3757 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3758 | likely ? "beql" : "beq", |
3759 | "s,t,p", sreg, 0); | |
670a50eb | 3760 | return; |
3d3c5039 | 3761 | } |
9a7d824a ILT |
3762 | if (sreg == 0) |
3763 | goto do_true; | |
0dd2d296 ILT |
3764 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3765 | sreg); | |
3766 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3767 | likely ? "beql" : "beq", |
3768 | "s,t,p", AT, 0); | |
670a50eb | 3769 | break; |
3d3c5039 | 3770 | |
8358c818 ILT |
3771 | case M_BLEUL_I: |
3772 | likely = 1; | |
3d3c5039 | 3773 | case M_BLEU_I: |
5c6f5923 GRK |
3774 | if (sreg == 0 |
3775 | || (mips_opts.isa < 3 | |
3776 | && imm_expr.X_op == O_constant | |
3777 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3778 | goto do_true; |
5c6f5923 GRK |
3779 | if (imm_expr.X_op != O_constant) |
3780 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3781 | imm_expr.X_add_number++; |
3782 | /* FALLTHROUGH */ | |
9a7d824a | 3783 | case M_BLTU_I: |
8358c818 ILT |
3784 | case M_BLTUL_I: |
3785 | if (mask == M_BLTUL_I) | |
3786 | likely = 1; | |
5c6f5923 | 3787 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3788 | goto do_false; |
5c6f5923 | 3789 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3790 | { |
0dd2d296 | 3791 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3792 | likely ? "beql" : "beq", |
3793 | "s,t,p", sreg, 0); | |
670a50eb | 3794 | return; |
3d3c5039 | 3795 | } |
6e8dda9c | 3796 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3797 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3798 | likely ? "bnel" : "bne", |
3799 | "s,t,p", AT, 0); | |
670a50eb | 3800 | break; |
3d3c5039 | 3801 | |
8358c818 ILT |
3802 | case M_BLTL: |
3803 | likely = 1; | |
3d3c5039 | 3804 | case M_BLT: |
670a50eb ILT |
3805 | if (treg == 0) |
3806 | { | |
0dd2d296 | 3807 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3808 | likely ? "bltzl" : "bltz", |
3809 | "s,p", sreg); | |
670a50eb | 3810 | return; |
3d3c5039 | 3811 | } |
9a7d824a | 3812 | if (sreg == 0) |
670a50eb | 3813 | { |
0dd2d296 | 3814 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3815 | likely ? "bgtzl" : "bgtz", |
3816 | "s,p", treg); | |
670a50eb | 3817 | return; |
3d3c5039 | 3818 | } |
0dd2d296 ILT |
3819 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3820 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3821 | likely ? "bnel" : "bne", |
3822 | "s,t,p", AT, 0); | |
670a50eb | 3823 | break; |
3d3c5039 | 3824 | |
8358c818 ILT |
3825 | case M_BLTUL: |
3826 | likely = 1; | |
3d3c5039 | 3827 | case M_BLTU: |
670a50eb | 3828 | if (treg == 0) |
9a7d824a ILT |
3829 | goto do_false; |
3830 | if (sreg == 0) | |
670a50eb | 3831 | { |
0dd2d296 | 3832 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3833 | likely ? "bnel" : "bne", |
3834 | "s,t,p", 0, treg); | |
670a50eb ILT |
3835 | return; |
3836 | } | |
0dd2d296 ILT |
3837 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3838 | treg); | |
3839 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3840 | likely ? "bnel" : "bne", |
3841 | "s,t,p", AT, 0); | |
670a50eb | 3842 | break; |
3d3c5039 | 3843 | |
8358c818 ILT |
3844 | case M_DDIV_3: |
3845 | dbl = 1; | |
3d3c5039 | 3846 | case M_DIV_3: |
8358c818 ILT |
3847 | s = "mflo"; |
3848 | goto do_div3; | |
3849 | case M_DREM_3: | |
3850 | dbl = 1; | |
3d3c5039 | 3851 | case M_REM_3: |
8358c818 ILT |
3852 | s = "mfhi"; |
3853 | do_div3: | |
670a50eb ILT |
3854 | if (treg == 0) |
3855 | { | |
3856 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3857 | if (mips_trap) |
3858 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3859 | else | |
3860 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3861 | return; |
3862 | } | |
3863 | ||
fbcfacb7 | 3864 | mips_emit_delays (true); |
3c83da8a | 3865 | ++mips_opts.noreorder; |
0dd2d296 ILT |
3866 | mips_any_noreorder = 1; |
3867 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3868 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3869 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3870 | if (mips_trap) |
3871 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3872 | else | |
3873 | { | |
3874 | expr1.X_add_number = 8; | |
3875 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3876 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3877 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3878 | } | |
670a50eb | 3879 | expr1.X_add_number = -1; |
0dd2d296 | 3880 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3881 | dbl ? "daddiu" : "addiu", |
9226253a | 3882 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3883 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3884 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3885 | if (dbl) |
3886 | { | |
3887 | expr1.X_add_number = 1; | |
0dd2d296 | 3888 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3889 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3890 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3891 | 31); | |
8358c818 ILT |
3892 | } |
3893 | else | |
3894 | { | |
3895 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3896 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3897 | (int) BFD_RELOC_HI16); | |
8358c818 | 3898 | } |
8ea7f4e8 ILT |
3899 | if (mips_trap) |
3900 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3901 | else | |
3902 | { | |
3903 | expr1.X_add_number = 8; | |
3904 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3905 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3906 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3907 | } | |
3c83da8a | 3908 | --mips_opts.noreorder; |
0dd2d296 | 3909 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3910 | break; |
3d3c5039 ILT |
3911 | |
3912 | case M_DIV_3I: | |
8358c818 ILT |
3913 | s = "div"; |
3914 | s2 = "mflo"; | |
3915 | goto do_divi; | |
3d3c5039 | 3916 | case M_DIVU_3I: |
8358c818 ILT |
3917 | s = "divu"; |
3918 | s2 = "mflo"; | |
3919 | goto do_divi; | |
3d3c5039 | 3920 | case M_REM_3I: |
8358c818 ILT |
3921 | s = "div"; |
3922 | s2 = "mfhi"; | |
3923 | goto do_divi; | |
3d3c5039 | 3924 | case M_REMU_3I: |
8358c818 ILT |
3925 | s = "divu"; |
3926 | s2 = "mfhi"; | |
3927 | goto do_divi; | |
3928 | case M_DDIV_3I: | |
3929 | dbl = 1; | |
3930 | s = "ddiv"; | |
3931 | s2 = "mflo"; | |
3932 | goto do_divi; | |
3933 | case M_DDIVU_3I: | |
3934 | dbl = 1; | |
3935 | s = "ddivu"; | |
3936 | s2 = "mflo"; | |
3937 | goto do_divi; | |
3938 | case M_DREM_3I: | |
3939 | dbl = 1; | |
3940 | s = "ddiv"; | |
3941 | s2 = "mfhi"; | |
3942 | goto do_divi; | |
3943 | case M_DREMU_3I: | |
3944 | dbl = 1; | |
3945 | s = "ddivu"; | |
3946 | s2 = "mfhi"; | |
3947 | do_divi: | |
5c6f5923 | 3948 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb ILT |
3949 | { |
3950 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3951 | if (mips_trap) |
3952 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3953 | else | |
3954 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3955 | return; |
3956 | } | |
5c6f5923 | 3957 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3958 | { |
8358c818 | 3959 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3960 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3961 | sreg); | |
3d3c5039 | 3962 | else |
0dd2d296 | 3963 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3964 | return; |
3965 | } | |
5c6f5923 GRK |
3966 | if (imm_expr.X_op == O_constant |
3967 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
3968 | && s[strlen (s) - 1] != 'u') |
3969 | { | |
3970 | if (strcmp (s2, "mflo") == 0) | |
3971 | { | |
3972 | if (dbl) | |
0dd2d296 ILT |
3973 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3974 | sreg); | |
8358c818 | 3975 | else |
0dd2d296 ILT |
3976 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3977 | sreg); | |
8358c818 ILT |
3978 | } |
3979 | else | |
0dd2d296 | 3980 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3981 | return; |
3982 | } | |
3d3c5039 | 3983 | |
d8a1c247 | 3984 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3985 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3986 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3987 | break; |
3988 | ||
3989 | case M_DIVU_3: | |
8358c818 ILT |
3990 | s = "divu"; |
3991 | s2 = "mflo"; | |
3992 | goto do_divu3; | |
670a50eb | 3993 | case M_REMU_3: |
8358c818 ILT |
3994 | s = "divu"; |
3995 | s2 = "mfhi"; | |
3996 | goto do_divu3; | |
3997 | case M_DDIVU_3: | |
3998 | s = "ddivu"; | |
3999 | s2 = "mflo"; | |
4000 | goto do_divu3; | |
4001 | case M_DREMU_3: | |
4002 | s = "ddivu"; | |
4003 | s2 = "mfhi"; | |
4004 | do_divu3: | |
fbcfacb7 | 4005 | mips_emit_delays (true); |
3c83da8a | 4006 | ++mips_opts.noreorder; |
0dd2d296 ILT |
4007 | mips_any_noreorder = 1; |
4008 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
4009 | if (mips_trap) |
4010 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4011 | else | |
4012 | { | |
4013 | expr1.X_add_number = 8; | |
4014 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
4015 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
4016 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
4017 | } | |
3c83da8a | 4018 | --mips_opts.noreorder; |
0dd2d296 | 4019 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 4020 | return; |
3d3c5039 | 4021 | |
d8a1c247 KR |
4022 | case M_DLA_AB: |
4023 | dbl = 1; | |
0dd2d296 | 4024 | case M_LA_AB: |
d9aba805 ILT |
4025 | /* Load the address of a symbol into a register. If breg is not |
4026 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
4027 | |
4028 | /* When generating embedded PIC code, we permit expressions of | |
4029 | the form | |
4030 | la $4,foo-bar | |
4031 | where bar is an address in the .text section. These are used | |
4032 | when getting the addresses of functions. We don't permit | |
4033 | X_add_number to be non-zero, because if the symbol is | |
4034 | external the relaxing code needs to know that any addend is | |
4035 | purely the offset to X_op_symbol. */ | |
4036 | if (mips_pic == EMBEDDED_PIC | |
4037 | && offset_expr.X_op == O_subtract | |
4038 | && now_seg == text_section | |
847a01cd ILT |
4039 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
4040 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
4041 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
4042 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
4043 | ->sy_value.X_add_symbol) | |
4044 | == text_section))) | |
ecd4ca1c ILT |
4045 | && breg == 0 |
4046 | && offset_expr.X_add_number == 0) | |
4047 | { | |
4048 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4049 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4050 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4051 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
ecd4ca1c ILT |
4052 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4053 | return; | |
4054 | } | |
4055 | ||
0dd2d296 ILT |
4056 | if (offset_expr.X_op != O_symbol |
4057 | && offset_expr.X_op != O_constant) | |
670a50eb | 4058 | { |
0dd2d296 ILT |
4059 | as_bad ("expression too complex"); |
4060 | offset_expr.X_op = O_constant; | |
4061 | } | |
4062 | ||
4063 | if (treg == breg) | |
4064 | { | |
4065 | tempreg = AT; | |
4066 | used_at = 1; | |
3d3c5039 | 4067 | } |
670a50eb ILT |
4068 | else |
4069 | { | |
0dd2d296 ILT |
4070 | tempreg = treg; |
4071 | used_at = 0; | |
670a50eb | 4072 | } |
3d3c5039 | 4073 | |
5ac34ac3 | 4074 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4075 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4076 | else if (mips_pic == NO_PIC) |
670a50eb | 4077 | { |
0dd2d296 ILT |
4078 | /* If this is a reference to an GP relative symbol, we want |
4079 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4080 | Otherwise we want | |
4081 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4082 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4083 | If we have a constant, we need two instructions anyhow, | |
4084 | so we may as well always use the latter form. */ | |
7a15a226 | 4085 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4086 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4087 | p = NULL; |
4088 | else | |
4089 | { | |
8ea7f4e8 | 4090 | frag_grow (20); |
0dd2d296 | 4091 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 4092 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4093 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4094 | p = frag_var (rs_machine_dependent, 8, 0, | |
4095 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4096 | mips_opts.warn_about_macros), |
f59fb6ca | 4097 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4098 | (char *) NULL); |
4099 | } | |
4100 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4101 | if (p != NULL) | |
4102 | p += 4; | |
4103 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4104 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4105 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4106 | } | |
fb251650 | 4107 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4108 | { |
4109 | /* If this is a reference to an external symbol, and there | |
4110 | is no constant, we want | |
4111 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4112 | For a local symbol, we want | |
4113 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4114 | nop | |
4115 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4116 | ||
4117 | If we have a small constant, and this is a reference to | |
4118 | an external symbol, we want | |
4119 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4120 | nop | |
4121 | addiu $tempreg,$tempreg,<constant> | |
4122 | For a local symbol, we want the same instruction | |
4123 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4124 | addiu instruction. | |
4125 | ||
4126 | If we have a large constant, and this is a reference to | |
4127 | an external symbol, we want | |
4128 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4129 | lui $at,<hiconstant> | |
4130 | addiu $at,$at,<loconstant> | |
4131 | addu $tempreg,$tempreg,$at | |
4132 | For a local symbol, we want the same instruction | |
4133 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4134 | addiu instruction. */ | |
4135 | expr1.X_add_number = offset_expr.X_add_number; | |
4136 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4137 | frag_grow (32); |
0dd2d296 | 4138 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4139 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4140 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4141 | if (expr1.X_add_number == 0) | |
4142 | { | |
4143 | int off; | |
4144 | ||
4145 | if (breg == 0) | |
4146 | off = 0; | |
4147 | else | |
4148 | { | |
4149 | /* We're going to put in an addu instruction using | |
4150 | tempreg, so we may as well insert the nop right | |
4151 | now. */ | |
4152 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4153 | "nop", ""); | |
4154 | off = 4; | |
4155 | } | |
4156 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4157 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4158 | (breg == 0 | |
3c83da8a | 4159 | ? mips_opts.warn_about_macros |
0dd2d296 | 4160 | : 0)), |
f59fb6ca | 4161 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4162 | (char *) NULL); |
4163 | if (breg == 0) | |
4164 | { | |
4165 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4166 | p += 4; | |
4167 | } | |
4168 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4169 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4170 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4171 | /* FIXME: If breg == 0, and the next instruction uses | |
4172 | $tempreg, then if this variant case is used an extra | |
4173 | nop will be generated. */ | |
4174 | } | |
4175 | else if (expr1.X_add_number >= -0x8000 | |
4176 | && expr1.X_add_number < 0x8000) | |
4177 | { | |
4178 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4179 | "nop", ""); | |
4180 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4181 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4182 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4183 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4184 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4185 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4186 | (char *) NULL); |
4187 | } | |
4188 | else | |
4189 | { | |
4190 | int off1; | |
4191 | ||
4192 | /* If we are going to add in a base register, and the | |
4193 | target register and the base register are the same, | |
4194 | then we are using AT as a temporary register. Since | |
4195 | we want to load the constant into AT, we add our | |
4196 | current AT (from the global offset table) and the | |
4197 | register into the register now, and pretend we were | |
4198 | not using a base register. */ | |
4199 | if (breg != treg) | |
4200 | off1 = 0; | |
4201 | else | |
4202 | { | |
4203 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4204 | "nop", ""); | |
4205 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4206 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4207 | "d,v,t", treg, AT, breg); |
4208 | breg = 0; | |
4209 | tempreg = treg; | |
4210 | off1 = -8; | |
4211 | } | |
4212 | ||
55933a58 ILT |
4213 | /* Set mips_optimize around the lui instruction to avoid |
4214 | inserting an unnecessary nop after the lw. */ | |
4215 | hold_mips_optimize = mips_optimize; | |
4216 | mips_optimize = 2; | |
0dd2d296 | 4217 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4218 | mips_optimize = hold_mips_optimize; |
4219 | ||
0dd2d296 | 4220 | macro_build ((char *) NULL, &icnt, &expr1, |
3c83da8a | 4221 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4222 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4223 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4224 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4225 | "d,v,t", tempreg, tempreg, AT); |
4226 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4227 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4228 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4229 | (char *) NULL); |
4230 | used_at = 1; | |
4231 | } | |
670a50eb | 4232 | } |
fb251650 ILT |
4233 | else if (mips_pic == SVR4_PIC) |
4234 | { | |
4235 | int gpdel; | |
4236 | ||
4237 | /* This is the large GOT case. If this is a reference to an | |
4238 | external symbol, and there is no constant, we want | |
4239 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4240 | addu $tempreg,$tempreg,$gp | |
4241 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4242 | For a local symbol, we want | |
4243 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4244 | nop | |
4245 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4246 | ||
4247 | If we have a small constant, and this is a reference to | |
4248 | an external symbol, we want | |
4249 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4250 | addu $tempreg,$tempreg,$gp | |
4251 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4252 | nop | |
4253 | addiu $tempreg,$tempreg,<constant> | |
4254 | For a local symbol, we want | |
4255 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4256 | nop | |
4257 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4258 | ||
4259 | If we have a large constant, and this is a reference to | |
4260 | an external symbol, we want | |
4261 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4262 | addu $tempreg,$tempreg,$gp | |
4263 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4264 | lui $at,<hiconstant> | |
4265 | addiu $at,$at,<loconstant> | |
4266 | addu $tempreg,$tempreg,$at | |
4267 | For a local symbol, we want | |
4268 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4269 | lui $at,<hiconstant> | |
4270 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4271 | addu $tempreg,$tempreg,$at | |
4272 | */ | |
4273 | expr1.X_add_number = offset_expr.X_add_number; | |
4274 | offset_expr.X_add_number = 0; | |
4275 | frag_grow (52); | |
4276 | if (reg_needs_delay (GP)) | |
4277 | gpdel = 4; | |
4278 | else | |
4279 | gpdel = 0; | |
4280 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4281 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4282 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4283 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4284 | "d,v,t", tempreg, tempreg, GP); |
4285 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4286 | dbl ? "ld" : "lw", | |
4287 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4288 | tempreg); | |
4289 | if (expr1.X_add_number == 0) | |
4290 | { | |
4291 | int off; | |
4292 | ||
4293 | if (breg == 0) | |
4294 | off = 0; | |
4295 | else | |
4296 | { | |
4297 | /* We're going to put in an addu instruction using | |
4298 | tempreg, so we may as well insert the nop right | |
4299 | now. */ | |
4300 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4301 | "nop", ""); | |
4302 | off = 4; | |
4303 | } | |
4304 | ||
4305 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4306 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4307 | 8 + gpdel, 0, | |
4308 | (breg == 0 | |
3c83da8a | 4309 | ? mips_opts.warn_about_macros |
fb251650 | 4310 | : 0)), |
f59fb6ca | 4311 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4312 | (char *) NULL); |
4313 | } | |
4314 | else if (expr1.X_add_number >= -0x8000 | |
4315 | && expr1.X_add_number < 0x8000) | |
4316 | { | |
4317 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4318 | "nop", ""); | |
4319 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4320 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4321 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4322 | ||
4323 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4324 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4325 | (breg == 0 | |
3c83da8a | 4326 | ? mips_opts.warn_about_macros |
fb251650 | 4327 | : 0)), |
f59fb6ca | 4328 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4329 | (char *) NULL); |
4330 | } | |
4331 | else | |
4332 | { | |
4333 | int adj, dreg; | |
4334 | ||
4335 | /* If we are going to add in a base register, and the | |
4336 | target register and the base register are the same, | |
4337 | then we are using AT as a temporary register. Since | |
4338 | we want to load the constant into AT, we add our | |
4339 | current AT (from the global offset table) and the | |
4340 | register into the register now, and pretend we were | |
4341 | not using a base register. */ | |
4342 | if (breg != treg) | |
4343 | { | |
4344 | adj = 0; | |
4345 | dreg = tempreg; | |
4346 | } | |
4347 | else | |
4348 | { | |
4349 | assert (tempreg == AT); | |
4350 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4351 | "nop", ""); | |
4352 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4353 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4354 | "d,v,t", treg, AT, breg); |
4355 | dreg = treg; | |
4356 | adj = 8; | |
4357 | } | |
4358 | ||
4359 | /* Set mips_optimize around the lui instruction to avoid | |
4360 | inserting an unnecessary nop after the lw. */ | |
4361 | hold_mips_optimize = mips_optimize; | |
4362 | mips_optimize = 2; | |
4363 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4364 | mips_optimize = hold_mips_optimize; | |
4365 | ||
4366 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4367 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4368 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4369 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4370 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4371 | "d,v,t", dreg, dreg, AT); |
4372 | ||
4373 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4374 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4375 | 8 + gpdel, 0, | |
4376 | (breg == 0 | |
3c83da8a | 4377 | ? mips_opts.warn_about_macros |
fb251650 | 4378 | : 0)), |
f59fb6ca | 4379 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4380 | (char *) NULL); |
4381 | ||
4382 | used_at = 1; | |
4383 | } | |
4384 | ||
4385 | if (gpdel > 0) | |
4386 | { | |
4387 | /* This is needed because this instruction uses $gp, but | |
4388 | the first instruction on the main stream does not. */ | |
4389 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4390 | p += 4; | |
4391 | } | |
4392 | macro_build (p, &icnt, &offset_expr, | |
4393 | dbl ? "ld" : "lw", | |
4394 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4395 | p += 4; | |
4396 | if (expr1.X_add_number >= -0x8000 | |
4397 | && expr1.X_add_number < 0x8000) | |
4398 | { | |
4399 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4400 | p += 4; | |
4401 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4402 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4403 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4404 | /* FIXME: If add_number is 0, and there was no base | |
4405 | register, the external symbol case ended with a load, | |
4406 | so if the symbol turns out to not be external, and | |
4407 | the next instruction uses tempreg, an unnecessary nop | |
4408 | will be inserted. */ | |
4409 | } | |
4410 | else | |
4411 | { | |
4412 | if (breg == treg) | |
4413 | { | |
4414 | /* We must add in the base register now, as in the | |
4415 | external symbol case. */ | |
4416 | assert (tempreg == AT); | |
4417 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4418 | p += 4; | |
4419 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4420 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4421 | "d,v,t", treg, AT, breg); |
4422 | p += 4; | |
4423 | tempreg = treg; | |
4424 | /* We set breg to 0 because we have arranged to add | |
4425 | it in in both cases. */ | |
4426 | breg = 0; | |
4427 | } | |
4428 | ||
4429 | macro_build_lui (p, &icnt, &expr1, AT); | |
4430 | p += 4; | |
4431 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4432 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4433 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4434 | p += 4; | |
4435 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4436 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4437 | "d,v,t", tempreg, tempreg, AT); |
4438 | p += 4; | |
4439 | } | |
4440 | } | |
d9aba805 ILT |
4441 | else if (mips_pic == EMBEDDED_PIC) |
4442 | { | |
4443 | /* We use | |
4444 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4445 | */ | |
4446 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4447 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
4448 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4449 | } | |
4450 | else | |
4451 | abort (); | |
0dd2d296 | 4452 | |
670a50eb | 4453 | if (breg != 0) |
0dd2d296 | 4454 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4455 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4456 | "d,v,t", treg, tempreg, breg); |
4457 | ||
4458 | if (! used_at) | |
4459 | return; | |
4460 | ||
4461 | break; | |
4462 | ||
4463 | case M_J_A: | |
4464 | /* The j instruction may not be used in PIC code, since it | |
4465 | requires an absolute address. We convert it to a b | |
4466 | instruction. */ | |
d9aba805 | 4467 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4468 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4469 | else | |
4470 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4471 | return; |
3d3c5039 | 4472 | |
9226253a ILT |
4473 | /* The jal instructions must be handled as macros because when |
4474 | generating PIC code they expand to multi-instruction | |
4475 | sequences. Normally they are simple instructions. */ | |
4476 | case M_JAL_1: | |
4477 | dreg = RA; | |
4478 | /* Fall through. */ | |
4479 | case M_JAL_2: | |
d9aba805 ILT |
4480 | if (mips_pic == NO_PIC |
4481 | || mips_pic == EMBEDDED_PIC) | |
4482 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4483 | "d,s", dreg, sreg); | |
4484 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4485 | { |
d9aba805 ILT |
4486 | if (sreg != PIC_CALL_REG) |
4487 | as_warn ("MIPS PIC call to register other than $25"); | |
4488 | ||
0dd2d296 ILT |
4489 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4490 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4491 | if (mips_cprestore_offset < 0) |
4492 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4493 | else | |
4494 | { | |
4495 | expr1.X_add_number = mips_cprestore_offset; | |
4496 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4497 | mips_opts.isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
4498 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4499 | } | |
9226253a | 4500 | } |
0dd2d296 | 4501 | else |
d9aba805 ILT |
4502 | abort (); |
4503 | ||
9226253a ILT |
4504 | return; |
4505 | ||
4506 | case M_JAL_A: | |
d9aba805 ILT |
4507 | if (mips_pic == NO_PIC) |
4508 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4509 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4510 | { |
fb251650 ILT |
4511 | /* If this is a reference to an external symbol, and we are |
4512 | using a small GOT, we want | |
d9aba805 ILT |
4513 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4514 | nop | |
4515 | jalr $25 | |
4516 | nop | |
4517 | lw $gp,cprestore($sp) | |
4518 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4519 | pseudo-op. If we are using a big GOT, we want |
4520 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4521 | addu $25,$25,$gp | |
4522 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4523 | nop | |
4524 | jalr $25 | |
4525 | nop | |
4526 | lw $gp,cprestore($sp) | |
4527 | If the symbol is not external, we want | |
d9aba805 ILT |
4528 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4529 | nop | |
4530 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4531 | jalr $25 | |
4532 | nop | |
fb251650 ILT |
4533 | lw $gp,cprestore($sp) */ |
4534 | frag_grow (40); | |
4535 | if (! mips_big_got) | |
4536 | { | |
4537 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4538 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4539 | "t,o(b)", PIC_CALL_REG, |
4540 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4541 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4542 | "nop", ""); | |
4543 | p = frag_var (rs_machine_dependent, 4, 0, | |
4544 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4545 | offset_expr.X_add_symbol, (offsetT) 0, |
4546 | (char *) NULL); | |
fb251650 ILT |
4547 | } |
4548 | else | |
4549 | { | |
4550 | int gpdel; | |
4551 | ||
4552 | if (reg_needs_delay (GP)) | |
4553 | gpdel = 4; | |
4554 | else | |
4555 | gpdel = 0; | |
4556 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4557 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4558 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4559 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4560 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4561 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4562 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4563 | "t,o(b)", PIC_CALL_REG, |
4564 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4565 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4566 | "nop", ""); | |
4567 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4568 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4569 | 0, 0), | |
f59fb6ca ILT |
4570 | offset_expr.X_add_symbol, (offsetT) 0, |
4571 | (char *) NULL); | |
fb251650 ILT |
4572 | if (gpdel > 0) |
4573 | { | |
4574 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4575 | p += 4; | |
4576 | } | |
4577 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4578 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4579 | "t,o(b)", PIC_CALL_REG, |
4580 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4581 | p += 4; | |
4582 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4583 | p += 4; | |
4584 | } | |
d9aba805 | 4585 | macro_build (p, &icnt, &offset_expr, |
3c83da8a | 4586 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
4587 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4588 | (int) BFD_RELOC_LO16); | |
4589 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4590 | "jalr", "s", PIC_CALL_REG); | |
4591 | if (mips_cprestore_offset < 0) | |
4592 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4593 | else | |
4594 | { | |
3c83da8a | 4595 | if (mips_opts.noreorder) |
d9aba805 ILT |
4596 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4597 | "nop", ""); | |
4598 | expr1.X_add_number = mips_cprestore_offset; | |
4599 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4600 | mips_opts.isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
4601 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4602 | mips_frame_reg); | |
4603 | } | |
0dd2d296 | 4604 | } |
d9aba805 | 4605 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4606 | { |
4607 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4608 | /* The linker may expand the call to a longer sequence which | |
4609 | uses $at, so we must break rather than return. */ | |
4610 | break; | |
4611 | } | |
d9aba805 ILT |
4612 | else |
4613 | abort (); | |
4614 | ||
9226253a ILT |
4615 | return; |
4616 | ||
3d3c5039 | 4617 | case M_LB_AB: |
670a50eb ILT |
4618 | s = "lb"; |
4619 | goto ld; | |
3d3c5039 | 4620 | case M_LBU_AB: |
670a50eb ILT |
4621 | s = "lbu"; |
4622 | goto ld; | |
3d3c5039 | 4623 | case M_LH_AB: |
670a50eb ILT |
4624 | s = "lh"; |
4625 | goto ld; | |
3d3c5039 | 4626 | case M_LHU_AB: |
670a50eb ILT |
4627 | s = "lhu"; |
4628 | goto ld; | |
3d3c5039 | 4629 | case M_LW_AB: |
670a50eb ILT |
4630 | s = "lw"; |
4631 | goto ld; | |
3d3c5039 | 4632 | case M_LWC0_AB: |
670a50eb | 4633 | s = "lwc0"; |
efec4a28 | 4634 | /* Itbl support may require additional care here. */ |
8358c818 | 4635 | coproc = 1; |
670a50eb | 4636 | goto ld; |
3d3c5039 | 4637 | case M_LWC1_AB: |
670a50eb | 4638 | s = "lwc1"; |
efec4a28 | 4639 | /* Itbl support may require additional care here. */ |
8358c818 | 4640 | coproc = 1; |
670a50eb | 4641 | goto ld; |
3d3c5039 | 4642 | case M_LWC2_AB: |
670a50eb | 4643 | s = "lwc2"; |
efec4a28 | 4644 | /* Itbl support may require additional care here. */ |
8358c818 | 4645 | coproc = 1; |
670a50eb | 4646 | goto ld; |
3d3c5039 | 4647 | case M_LWC3_AB: |
670a50eb | 4648 | s = "lwc3"; |
efec4a28 | 4649 | /* Itbl support may require additional care here. */ |
8358c818 | 4650 | coproc = 1; |
670a50eb | 4651 | goto ld; |
3d3c5039 | 4652 | case M_LWL_AB: |
670a50eb | 4653 | s = "lwl"; |
b2b8c24e | 4654 | lr = 1; |
670a50eb | 4655 | goto ld; |
3d3c5039 | 4656 | case M_LWR_AB: |
670a50eb | 4657 | s = "lwr"; |
b2b8c24e | 4658 | lr = 1; |
8358c818 ILT |
4659 | goto ld; |
4660 | case M_LDC1_AB: | |
1c6f3441 ILT |
4661 | if (mips_4650) |
4662 | { | |
4663 | as_bad ("opcode not supported on this processor"); | |
4664 | return; | |
4665 | } | |
8358c818 | 4666 | s = "ldc1"; |
efec4a28 | 4667 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4668 | coproc = 1; |
4669 | goto ld; | |
4670 | case M_LDC2_AB: | |
4671 | s = "ldc2"; | |
efec4a28 | 4672 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4673 | coproc = 1; |
4674 | goto ld; | |
4675 | case M_LDC3_AB: | |
4676 | s = "ldc3"; | |
efec4a28 | 4677 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4678 | coproc = 1; |
4679 | goto ld; | |
4680 | case M_LDL_AB: | |
4681 | s = "ldl"; | |
b2b8c24e | 4682 | lr = 1; |
8358c818 ILT |
4683 | goto ld; |
4684 | case M_LDR_AB: | |
4685 | s = "ldr"; | |
b2b8c24e | 4686 | lr = 1; |
8358c818 ILT |
4687 | goto ld; |
4688 | case M_LL_AB: | |
4689 | s = "ll"; | |
4690 | goto ld; | |
4691 | case M_LLD_AB: | |
4692 | s = "lld"; | |
4693 | goto ld; | |
4694 | case M_LWU_AB: | |
4695 | s = "lwu"; | |
3d3c5039 | 4696 | ld: |
b2b8c24e | 4697 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4698 | { |
4699 | tempreg = AT; | |
4700 | used_at = 1; | |
4701 | } | |
4702 | else | |
4703 | { | |
4704 | tempreg = treg; | |
4705 | used_at = 0; | |
4706 | } | |
4707 | goto ld_st; | |
3d3c5039 | 4708 | case M_SB_AB: |
670a50eb ILT |
4709 | s = "sb"; |
4710 | goto st; | |
3d3c5039 | 4711 | case M_SH_AB: |
670a50eb ILT |
4712 | s = "sh"; |
4713 | goto st; | |
3d3c5039 | 4714 | case M_SW_AB: |
670a50eb ILT |
4715 | s = "sw"; |
4716 | goto st; | |
3d3c5039 | 4717 | case M_SWC0_AB: |
670a50eb | 4718 | s = "swc0"; |
efec4a28 | 4719 | /* Itbl support may require additional care here. */ |
8358c818 | 4720 | coproc = 1; |
670a50eb | 4721 | goto st; |
3d3c5039 | 4722 | case M_SWC1_AB: |
670a50eb | 4723 | s = "swc1"; |
efec4a28 | 4724 | /* Itbl support may require additional care here. */ |
8358c818 | 4725 | coproc = 1; |
670a50eb | 4726 | goto st; |
3d3c5039 | 4727 | case M_SWC2_AB: |
670a50eb | 4728 | s = "swc2"; |
efec4a28 | 4729 | /* Itbl support may require additional care here. */ |
8358c818 | 4730 | coproc = 1; |
670a50eb | 4731 | goto st; |
3d3c5039 | 4732 | case M_SWC3_AB: |
670a50eb | 4733 | s = "swc3"; |
efec4a28 | 4734 | /* Itbl support may require additional care here. */ |
8358c818 | 4735 | coproc = 1; |
670a50eb | 4736 | goto st; |
3d3c5039 | 4737 | case M_SWL_AB: |
670a50eb ILT |
4738 | s = "swl"; |
4739 | goto st; | |
3d3c5039 | 4740 | case M_SWR_AB: |
670a50eb | 4741 | s = "swr"; |
8358c818 ILT |
4742 | goto st; |
4743 | case M_SC_AB: | |
4744 | s = "sc"; | |
4745 | goto st; | |
4746 | case M_SCD_AB: | |
4747 | s = "scd"; | |
4748 | goto st; | |
4749 | case M_SDC1_AB: | |
1c6f3441 ILT |
4750 | if (mips_4650) |
4751 | { | |
4752 | as_bad ("opcode not supported on this processor"); | |
4753 | return; | |
4754 | } | |
8358c818 ILT |
4755 | s = "sdc1"; |
4756 | coproc = 1; | |
efec4a28 | 4757 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4758 | goto st; |
4759 | case M_SDC2_AB: | |
4760 | s = "sdc2"; | |
efec4a28 | 4761 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4762 | coproc = 1; |
4763 | goto st; | |
4764 | case M_SDC3_AB: | |
4765 | s = "sdc3"; | |
efec4a28 | 4766 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4767 | coproc = 1; |
4768 | goto st; | |
4769 | case M_SDL_AB: | |
4770 | s = "sdl"; | |
4771 | goto st; | |
4772 | case M_SDR_AB: | |
4773 | s = "sdr"; | |
3d3c5039 | 4774 | st: |
670a50eb ILT |
4775 | tempreg = AT; |
4776 | used_at = 1; | |
3d3c5039 | 4777 | ld_st: |
efec4a28 | 4778 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4779 | if (mask == M_LWC1_AB |
4780 | || mask == M_SWC1_AB | |
8358c818 | 4781 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4782 | || mask == M_SDC1_AB |
4783 | || mask == M_L_DAB | |
4784 | || mask == M_S_DAB) | |
670a50eb | 4785 | fmt = "T,o(b)"; |
8358c818 | 4786 | else if (coproc) |
19ed8960 | 4787 | fmt = "E,o(b)"; |
670a50eb ILT |
4788 | else |
4789 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4790 | |
4791 | if (offset_expr.X_op != O_constant | |
4792 | && offset_expr.X_op != O_symbol) | |
4793 | { | |
4794 | as_bad ("expression too complex"); | |
4795 | offset_expr.X_op = O_constant; | |
4796 | } | |
4797 | ||
4798 | /* A constant expression in PIC code can be handled just as it | |
4799 | is in non PIC code. */ | |
d9aba805 | 4800 | if (mips_pic == NO_PIC |
0dd2d296 | 4801 | || offset_expr.X_op == O_constant) |
670a50eb | 4802 | { |
0dd2d296 ILT |
4803 | /* If this is a reference to a GP relative symbol, and there |
4804 | is no base register, we want | |
4805 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4806 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4807 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4808 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4809 | If we have a constant, we need two instructions anyhow, | |
4810 | so we always use the latter form. | |
4811 | ||
4812 | If we have a base register, and this is a reference to a | |
4813 | GP relative symbol, we want | |
4814 | addu $tempreg,$breg,$gp | |
4815 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4816 | Otherwise we want | |
4817 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4818 | addu $tempreg,$tempreg,$breg | |
4819 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4820 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4821 | if (breg == 0) |
4822 | { | |
7a15a226 | 4823 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4824 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4825 | p = NULL; |
4826 | else | |
4827 | { | |
8ea7f4e8 | 4828 | frag_grow (20); |
0dd2d296 ILT |
4829 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4830 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4831 | p = frag_var (rs_machine_dependent, 8, 0, | |
4832 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
4833 | (mips_opts.warn_about_macros |
4834 | || (used_at | |
4835 | && mips_opts.noat))), | |
f59fb6ca | 4836 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 4837 | (char *) NULL); |
8197b589 | 4838 | used_at = 0; |
0dd2d296 ILT |
4839 | } |
4840 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4841 | if (p != NULL) | |
4842 | p += 4; | |
4843 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4844 | (int) BFD_RELOC_LO16, tempreg); | |
4845 | } | |
4846 | else | |
4847 | { | |
7a15a226 | 4848 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4849 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4850 | p = NULL; |
4851 | else | |
4852 | { | |
8ea7f4e8 | 4853 | frag_grow (28); |
0dd2d296 | 4854 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4855 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4856 | "d,v,t", tempreg, breg, GP); |
4857 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4858 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4859 | p = frag_var (rs_machine_dependent, 12, 0, | |
4860 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 4861 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4862 | (char *) NULL); |
4863 | } | |
4864 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4865 | if (p != NULL) | |
4866 | p += 4; | |
4867 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4868 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4869 | "d,v,t", tempreg, tempreg, breg); |
4870 | if (p != NULL) | |
4871 | p += 4; | |
4872 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4873 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4874 | } |
670a50eb | 4875 | } |
fb251650 | 4876 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4877 | { |
0dd2d296 ILT |
4878 | /* If this is a reference to an external symbol, we want |
4879 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4880 | nop | |
4881 | <op> $treg,0($tempreg) | |
4882 | Otherwise we want | |
4883 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4884 | nop | |
4885 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4886 | <op> $treg,0($tempreg) | |
4887 | If there is a base register, we add it to $tempreg before | |
4888 | the <op>. If there is a constant, we stick it in the | |
4889 | <op> instruction. We don't handle constants larger than | |
4890 | 16 bits, because we have no way to load the upper 16 bits | |
4891 | (actually, we could handle them for the subset of cases | |
4892 | in which we are not using $at). */ | |
4893 | assert (offset_expr.X_op == O_symbol); | |
4894 | expr1.X_add_number = offset_expr.X_add_number; | |
4895 | offset_expr.X_add_number = 0; | |
4896 | if (expr1.X_add_number < -0x8000 | |
4897 | || expr1.X_add_number >= 0x8000) | |
4898 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4899 | frag_grow (20); |
0dd2d296 | 4900 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 4901 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
4902 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4903 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4904 | p = frag_var (rs_machine_dependent, 4, 0, | |
4905 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 4906 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4907 | (char *) NULL); |
4908 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4909 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 | 4910 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 4911 | if (breg != 0) |
0dd2d296 | 4912 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4913 | mips_opts.isa < 3 ? "addu" : "daddu", |
6e8dda9c | 4914 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
4915 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4916 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4917 | } |
fb251650 ILT |
4918 | else if (mips_pic == SVR4_PIC) |
4919 | { | |
4920 | int gpdel; | |
4921 | ||
4922 | /* If this is a reference to an external symbol, we want | |
4923 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4924 | addu $tempreg,$tempreg,$gp | |
4925 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4926 | <op> $treg,0($tempreg) | |
4927 | Otherwise we want | |
4928 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4929 | nop | |
4930 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4931 | <op> $treg,0($tempreg) | |
4932 | If there is a base register, we add it to $tempreg before | |
4933 | the <op>. If there is a constant, we stick it in the | |
4934 | <op> instruction. We don't handle constants larger than | |
4935 | 16 bits, because we have no way to load the upper 16 bits | |
4936 | (actually, we could handle them for the subset of cases | |
4937 | in which we are not using $at). */ | |
4938 | assert (offset_expr.X_op == O_symbol); | |
4939 | expr1.X_add_number = offset_expr.X_add_number; | |
4940 | offset_expr.X_add_number = 0; | |
4941 | if (expr1.X_add_number < -0x8000 | |
4942 | || expr1.X_add_number >= 0x8000) | |
4943 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4944 | if (reg_needs_delay (GP)) | |
4945 | gpdel = 4; | |
4946 | else | |
4947 | gpdel = 0; | |
4948 | frag_grow (36); | |
4949 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4950 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4951 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4952 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4953 | "d,v,t", tempreg, tempreg, GP); |
4954 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4955 | mips_opts.isa < 3 ? "lw" : "ld", |
867a58b3 ILT |
4956 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4957 | tempreg); | |
fb251650 ILT |
4958 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4959 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 4960 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
4961 | if (gpdel > 0) |
4962 | { | |
4963 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4964 | p += 4; | |
4965 | } | |
4966 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4967 | mips_opts.isa < 3 ? "lw" : "ld", |
867a58b3 | 4968 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4969 | p += 4; |
4970 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4971 | p += 4; | |
4972 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4973 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4974 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4975 | if (breg != 0) | |
4976 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4977 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4978 | "d,v,t", tempreg, tempreg, breg); |
4979 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4980 | (int) BFD_RELOC_LO16, tempreg); | |
4981 | } | |
d9aba805 ILT |
4982 | else if (mips_pic == EMBEDDED_PIC) |
4983 | { | |
4984 | /* If there is no base register, we want | |
4985 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4986 | If there is a base register, we want | |
4987 | addu $tempreg,$breg,$gp | |
4988 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4989 | */ | |
4990 | assert (offset_expr.X_op == O_symbol); | |
4991 | if (breg == 0) | |
4992 | { | |
4993 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4994 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4995 | used_at = 0; | |
4996 | } | |
4997 | else | |
4998 | { | |
4999 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5000 | mips_opts.isa < 3 ? "addu" : "daddu", |
d9aba805 ILT |
5001 | "d,v,t", tempreg, breg, GP); |
5002 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5003 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5004 | } | |
5005 | } | |
5006 | else | |
5007 | abort (); | |
0dd2d296 ILT |
5008 | |
5009 | if (! used_at) | |
5010 | return; | |
5011 | ||
5012 | break; | |
3d3c5039 ILT |
5013 | |
5014 | case M_LI: | |
19ed8960 | 5015 | case M_LI_S: |
d8a1c247 KR |
5016 | load_register (&icnt, treg, &imm_expr, 0); |
5017 | return; | |
5018 | ||
5019 | case M_DLI: | |
5020 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 5021 | return; |
3d3c5039 | 5022 | |
0dd2d296 | 5023 | case M_LI_SS: |
55933a58 | 5024 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 5025 | { |
d8a1c247 | 5026 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
5027 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5028 | "mtc1", "t,G", AT, treg); | |
5029 | break; | |
0dd2d296 | 5030 | } |
d9aba805 | 5031 | else |
d2c71068 | 5032 | { |
55933a58 ILT |
5033 | assert (offset_expr.X_op == O_symbol |
5034 | && strcmp (segment_name (S_GET_SEGMENT | |
5035 | (offset_expr.X_add_symbol)), | |
5036 | ".lit4") == 0 | |
5037 | && offset_expr.X_add_number == 0); | |
5038 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5039 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
5040 | return; |
5041 | } | |
0dd2d296 | 5042 | |
3d3c5039 | 5043 | case M_LI_D: |
a5586bdc ILT |
5044 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5045 | the entire value, and in mips1 mode it is the high order 32 | |
5046 | bits of the value and the low order 32 bits are either zero | |
5047 | or in offset_expr. */ | |
5048 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5049 | { | |
517640d9 ILT |
5050 | if (mips_opts.isa >= 3) |
5051 | load_register (&icnt, treg, &imm_expr, 1); | |
5052 | else | |
a5586bdc | 5053 | { |
517640d9 ILT |
5054 | int hreg, lreg; |
5055 | ||
5056 | if (target_big_endian) | |
5057 | { | |
5058 | hreg = treg; | |
5059 | lreg = treg + 1; | |
5060 | } | |
a5586bdc ILT |
5061 | else |
5062 | { | |
517640d9 ILT |
5063 | hreg = treg + 1; |
5064 | lreg = treg; | |
5065 | } | |
5066 | ||
5067 | if (hreg <= 31) | |
5068 | load_register (&icnt, hreg, &imm_expr, 0); | |
5069 | if (lreg <= 31) | |
5070 | { | |
5071 | if (offset_expr.X_op == O_absent) | |
5072 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5073 | lreg, 0); | |
5074 | else | |
5075 | { | |
5076 | assert (offset_expr.X_op == O_constant); | |
5077 | load_register (&icnt, lreg, &offset_expr, 0); | |
5078 | } | |
a5586bdc ILT |
5079 | } |
5080 | } | |
5081 | return; | |
5082 | } | |
5083 | ||
d9aba805 ILT |
5084 | /* We know that sym is in the .rdata section. First we get the |
5085 | upper 16 bits of the address. */ | |
5086 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
5087 | { |
5088 | /* FIXME: This won't work for a 64 bit address. */ | |
5089 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5090 | } | |
d9aba805 | 5091 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
5092 | { |
5093 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5094 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
5095 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5096 | } | |
d9aba805 ILT |
5097 | else if (mips_pic == EMBEDDED_PIC) |
5098 | { | |
5099 | /* For embedded PIC we pick up the entire address off $gp in | |
5100 | a single instruction. */ | |
5101 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5102 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
5103 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5104 | offset_expr.X_op = O_constant; | |
5105 | offset_expr.X_add_number = 0; | |
5106 | } | |
5107 | else | |
5108 | abort (); | |
5109 | ||
0dd2d296 | 5110 | /* Now we load the register(s). */ |
3c83da8a | 5111 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5112 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5113 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5114 | else |
5115 | { | |
0dd2d296 ILT |
5116 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5117 | treg, (int) BFD_RELOC_LO16, AT); | |
5118 | if (treg != 31) | |
5119 | { | |
5120 | /* FIXME: How in the world do we deal with the possible | |
5121 | overflow here? */ | |
5122 | offset_expr.X_add_number += 4; | |
5123 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5124 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5125 | } | |
8358c818 | 5126 | } |
d2c71068 ILT |
5127 | |
5128 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5129 | does not become a variant frag. */ | |
5130 | frag_wane (frag_now); | |
5131 | frag_new (0); | |
5132 | ||
670a50eb | 5133 | break; |
3d3c5039 ILT |
5134 | |
5135 | case M_LI_DD: | |
a5586bdc ILT |
5136 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5137 | the entire value, and in mips1 mode it is the high order 32 | |
5138 | bits of the value and the low order 32 bits are either zero | |
5139 | or in offset_expr. */ | |
5140 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5141 | { | |
5142 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5143 | if (mips_opts.isa >= 3) | |
5144 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5145 | "dmtc1", "t,S", AT, treg); | |
5146 | else | |
5147 | { | |
5148 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5149 | "mtc1", "t,G", AT, treg + 1); | |
5150 | if (offset_expr.X_op == O_absent) | |
5151 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5152 | "mtc1", "t,G", 0, treg); | |
5153 | else | |
5154 | { | |
5155 | assert (offset_expr.X_op == O_constant); | |
5156 | load_register (&icnt, AT, &offset_expr, 0); | |
5157 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5158 | "mtc1", "t,G", AT, treg); | |
5159 | } | |
5160 | } | |
5161 | break; | |
5162 | } | |
5163 | ||
55933a58 ILT |
5164 | assert (offset_expr.X_op == O_symbol |
5165 | && offset_expr.X_add_number == 0); | |
5166 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5167 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5168 | { |
3c83da8a | 5169 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5170 | { |
5171 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5172 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5173 | return; | |
5174 | } | |
5175 | breg = GP; | |
5176 | r = BFD_RELOC_MIPS_LITERAL; | |
5177 | goto dob; | |
5178 | } | |
55933a58 | 5179 | else |
0dd2d296 | 5180 | { |
55933a58 ILT |
5181 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5182 | if (mips_pic == SVR4_PIC) | |
5183 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5184 | mips_opts.isa < 3 ? "lw" : "ld", |
55933a58 ILT |
5185 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5186 | else | |
5187 | { | |
5188 | /* FIXME: This won't work for a 64 bit address. */ | |
5189 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5190 | } | |
5191 | ||
3c83da8a | 5192 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5193 | { |
5194 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5195 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5196 | |
5197 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5198 | that this does not become a variant frag. */ | |
5199 | frag_wane (frag_now); | |
5200 | frag_new (0); | |
5201 | ||
0dd2d296 ILT |
5202 | break; |
5203 | } | |
5204 | breg = AT; | |
5205 | r = BFD_RELOC_LO16; | |
5206 | goto dob; | |
8358c818 | 5207 | } |
9226253a | 5208 | |
3d3c5039 | 5209 | case M_L_DOB: |
1c6f3441 ILT |
5210 | if (mips_4650) |
5211 | { | |
5212 | as_bad ("opcode not supported on this processor"); | |
5213 | return; | |
5214 | } | |
9a7d824a ILT |
5215 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5216 | to adjust when loading from memory. */ | |
9226253a ILT |
5217 | r = BFD_RELOC_LO16; |
5218 | dob: | |
3c83da8a | 5219 | assert (mips_opts.isa < 2); |
0dd2d296 | 5220 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5221 | target_big_endian ? treg + 1 : treg, |
9226253a | 5222 | (int) r, breg); |
0dd2d296 ILT |
5223 | /* FIXME: A possible overflow which I don't know how to deal |
5224 | with. */ | |
670a50eb | 5225 | offset_expr.X_add_number += 4; |
0dd2d296 | 5226 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5227 | target_big_endian ? treg : treg + 1, |
9226253a | 5228 | (int) r, breg); |
d2c71068 ILT |
5229 | |
5230 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5231 | does not become a variant frag. */ | |
5232 | frag_wane (frag_now); | |
5233 | frag_new (0); | |
5234 | ||
0dd2d296 ILT |
5235 | if (breg != AT) |
5236 | return; | |
5237 | break; | |
3d3c5039 ILT |
5238 | |
5239 | case M_L_DAB: | |
670a50eb ILT |
5240 | /* |
5241 | * The MIPS assembler seems to check for X_add_number not | |
5242 | * being double aligned and generating: | |
5243 | * lui at,%hi(foo+1) | |
5244 | * addu at,at,v1 | |
5245 | * addiu at,at,%lo(foo+1) | |
5246 | * lwc1 f2,0(at) | |
5247 | * lwc1 f3,4(at) | |
5248 | * But, the resulting address is the same after relocation so why | |
5249 | * generate the extra instruction? | |
5250 | */ | |
1c6f3441 ILT |
5251 | if (mips_4650) |
5252 | { | |
5253 | as_bad ("opcode not supported on this processor"); | |
5254 | return; | |
5255 | } | |
efec4a28 | 5256 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5257 | coproc = 1; |
3c83da8a | 5258 | if (mips_opts.isa >= 2) |
670a50eb | 5259 | { |
0dd2d296 ILT |
5260 | s = "ldc1"; |
5261 | goto ld; | |
670a50eb | 5262 | } |
0dd2d296 ILT |
5263 | |
5264 | s = "lwc1"; | |
5265 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5266 | goto ldd_std; |
5267 | ||
5268 | case M_S_DAB: | |
1c6f3441 ILT |
5269 | if (mips_4650) |
5270 | { | |
5271 | as_bad ("opcode not supported on this processor"); | |
5272 | return; | |
5273 | } | |
5274 | ||
3c83da8a | 5275 | if (mips_opts.isa >= 2) |
8358c818 | 5276 | { |
0dd2d296 ILT |
5277 | s = "sdc1"; |
5278 | goto st; | |
8358c818 | 5279 | } |
3d3c5039 | 5280 | |
0dd2d296 ILT |
5281 | s = "swc1"; |
5282 | fmt = "T,o(b)"; | |
efec4a28 | 5283 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5284 | coproc = 1; |
5285 | goto ldd_std; | |
3d3c5039 ILT |
5286 | |
5287 | case M_LD_AB: | |
3c83da8a | 5288 | if (mips_opts.isa >= 3) |
670a50eb | 5289 | { |
0dd2d296 ILT |
5290 | s = "ld"; |
5291 | goto ld; | |
670a50eb | 5292 | } |
0dd2d296 ILT |
5293 | |
5294 | s = "lw"; | |
5295 | fmt = "t,o(b)"; | |
5296 | goto ldd_std; | |
5297 | ||
5298 | case M_SD_AB: | |
3c83da8a | 5299 | if (mips_opts.isa >= 3) |
670a50eb | 5300 | { |
0dd2d296 ILT |
5301 | s = "sd"; |
5302 | goto st; | |
670a50eb | 5303 | } |
0dd2d296 | 5304 | |
670a50eb | 5305 | s = "sw"; |
0dd2d296 ILT |
5306 | fmt = "t,o(b)"; |
5307 | ||
5308 | ldd_std: | |
5309 | if (offset_expr.X_op != O_symbol | |
5310 | && offset_expr.X_op != O_constant) | |
670a50eb | 5311 | { |
0dd2d296 ILT |
5312 | as_bad ("expression too complex"); |
5313 | offset_expr.X_op = O_constant; | |
5314 | } | |
5315 | ||
5316 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5317 | to adjust when loading from memory. We set coproc if we must | |
5318 | load $fn+1 first. */ | |
efec4a28 | 5319 | /* Itbl support may require additional care here. */ |
b9129c6f | 5320 | if (! target_big_endian) |
0dd2d296 ILT |
5321 | coproc = 0; |
5322 | ||
d9aba805 | 5323 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5324 | || offset_expr.X_op == O_constant) |
5325 | { | |
5326 | /* If this is a reference to a GP relative symbol, we want | |
5327 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5328 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5329 | If we have a base register, we use this | |
5330 | addu $at,$breg,$gp | |
5331 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5332 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5333 | If this is not a GP relative symbol, we want | |
5334 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5335 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5336 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5337 | If there is a base register, we add it to $at after the | |
5338 | lui instruction. If there is a constant, we always use | |
5339 | the last case. */ | |
7a15a226 | 5340 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5341 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5342 | { |
0dd2d296 ILT |
5343 | p = NULL; |
5344 | used_at = 1; | |
670a50eb ILT |
5345 | } |
5346 | else | |
0dd2d296 ILT |
5347 | { |
5348 | int off; | |
5349 | ||
5350 | if (breg == 0) | |
5351 | { | |
8ea7f4e8 | 5352 | frag_grow (28); |
0dd2d296 ILT |
5353 | tempreg = GP; |
5354 | off = 0; | |
5355 | used_at = 0; | |
5356 | } | |
5357 | else | |
5358 | { | |
8ea7f4e8 | 5359 | frag_grow (36); |
0dd2d296 | 5360 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 5361 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5362 | "d,v,t", AT, breg, GP); |
5363 | tempreg = AT; | |
5364 | off = 4; | |
5365 | used_at = 1; | |
5366 | } | |
5367 | ||
efec4a28 | 5368 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5369 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5370 | coproc ? treg + 1 : treg, | |
5371 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5372 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5373 | |
5374 | /* Set mips_optimize to 2 to avoid inserting an | |
5375 | undesired nop. */ | |
5376 | hold_mips_optimize = mips_optimize; | |
5377 | mips_optimize = 2; | |
efec4a28 | 5378 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5379 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5380 | coproc ? treg : treg + 1, | |
5381 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5382 | mips_optimize = hold_mips_optimize; |
5383 | ||
0dd2d296 ILT |
5384 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5385 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5386 | used_at && mips_opts.noat), |
f59fb6ca | 5387 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5388 | (char *) NULL); |
777ad64d ILT |
5389 | |
5390 | /* We just generated two relocs. When tc_gen_reloc | |
5391 | handles this case, it will skip the first reloc and | |
5392 | handle the second. The second reloc already has an | |
5393 | extra addend of 4, which we added above. We must | |
5394 | subtract it out, and then subtract another 4 to make | |
5395 | the first reloc come out right. The second reloc | |
5396 | will come out right because we are going to add 4 to | |
703f5e6e ILT |
5397 | offset_expr when we build its instruction below. |
5398 | ||
5399 | If we have a symbol, then we don't want to include | |
5400 | the offset, because it will wind up being included | |
5401 | when we generate the reloc. */ | |
5402 | ||
5403 | if (offset_expr.X_op == O_constant) | |
5404 | offset_expr.X_add_number -= 8; | |
5405 | else | |
5406 | { | |
5407 | offset_expr.X_add_number = -4; | |
5408 | offset_expr.X_op = O_constant; | |
5409 | } | |
0dd2d296 ILT |
5410 | } |
5411 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5412 | if (p != NULL) | |
5413 | p += 4; | |
5414 | if (breg != 0) | |
5415 | { | |
5416 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 5417 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5418 | "d,v,t", AT, breg, AT); |
5419 | if (p != NULL) | |
5420 | p += 4; | |
5421 | } | |
efec4a28 | 5422 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5423 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5424 | coproc ? treg + 1 : treg, | |
5425 | (int) BFD_RELOC_LO16, AT); | |
5426 | if (p != NULL) | |
5427 | p += 4; | |
5428 | /* FIXME: How do we handle overflow here? */ | |
5429 | offset_expr.X_add_number += 4; | |
efec4a28 | 5430 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5431 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5432 | coproc ? treg : treg + 1, | |
5433 | (int) BFD_RELOC_LO16, AT); | |
5434 | } | |
fb251650 | 5435 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5436 | { |
0dd2d296 ILT |
5437 | int off; |
5438 | ||
5439 | /* If this is a reference to an external symbol, we want | |
5440 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5441 | nop | |
5442 | <op> $treg,0($at) | |
5443 | <op> $treg+1,4($at) | |
5444 | Otherwise we want | |
5445 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5446 | nop | |
5447 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5448 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5449 | If there is a base register we add it to $at before the | |
5450 | lwc1 instructions. If there is a constant we include it | |
5451 | in the lwc1 instructions. */ | |
5452 | used_at = 1; | |
5453 | expr1.X_add_number = offset_expr.X_add_number; | |
5454 | offset_expr.X_add_number = 0; | |
5455 | if (expr1.X_add_number < -0x8000 | |
5456 | || expr1.X_add_number >= 0x8000 - 4) | |
5457 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5458 | if (breg == 0) | |
5459 | off = 0; | |
5460 | else | |
5461 | off = 4; | |
8ea7f4e8 | 5462 | frag_grow (24 + off); |
0dd2d296 | 5463 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 5464 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
5465 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5466 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5467 | if (breg != 0) |
0dd2d296 | 5468 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 5469 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 | 5470 | "d,v,t", AT, breg, AT); |
efec4a28 | 5471 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5472 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5473 | coproc ? treg + 1 : treg, | |
5474 | (int) BFD_RELOC_LO16, AT); | |
5475 | expr1.X_add_number += 4; | |
55933a58 ILT |
5476 | |
5477 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5478 | nop. */ | |
5479 | hold_mips_optimize = mips_optimize; | |
5480 | mips_optimize = 2; | |
efec4a28 | 5481 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5482 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5483 | coproc ? treg : treg + 1, | |
5484 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5485 | mips_optimize = hold_mips_optimize; |
5486 | ||
0dd2d296 ILT |
5487 | (void) frag_var (rs_machine_dependent, 0, 0, |
5488 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5489 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5490 | (char *) NULL); |
8358c818 | 5491 | } |
fb251650 ILT |
5492 | else if (mips_pic == SVR4_PIC) |
5493 | { | |
5494 | int gpdel, off; | |
5495 | ||
5496 | /* If this is a reference to an external symbol, we want | |
5497 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5498 | addu $at,$at,$gp | |
5499 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5500 | nop | |
5501 | <op> $treg,0($at) | |
5502 | <op> $treg+1,4($at) | |
5503 | Otherwise we want | |
5504 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5505 | nop | |
5506 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5507 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5508 | If there is a base register we add it to $at before the | |
5509 | lwc1 instructions. If there is a constant we include it | |
5510 | in the lwc1 instructions. */ | |
5511 | used_at = 1; | |
5512 | expr1.X_add_number = offset_expr.X_add_number; | |
5513 | offset_expr.X_add_number = 0; | |
5514 | if (expr1.X_add_number < -0x8000 | |
5515 | || expr1.X_add_number >= 0x8000 - 4) | |
5516 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5517 | if (reg_needs_delay (GP)) | |
5518 | gpdel = 4; | |
5519 | else | |
5520 | gpdel = 0; | |
5521 | if (breg == 0) | |
5522 | off = 0; | |
5523 | else | |
5524 | off = 4; | |
5525 | frag_grow (56); | |
5526 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5527 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5528 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5529 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
5530 | "d,v,t", AT, AT, GP); |
5531 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5532 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
5533 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5534 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5535 | if (breg != 0) | |
5536 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5537 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 | 5538 | "d,v,t", AT, breg, AT); |
efec4a28 | 5539 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5540 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5541 | coproc ? treg + 1 : treg, | |
5542 | (int) BFD_RELOC_LO16, AT); | |
5543 | expr1.X_add_number += 4; | |
5544 | ||
5545 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5546 | nop. */ | |
5547 | hold_mips_optimize = mips_optimize; | |
5548 | mips_optimize = 2; | |
efec4a28 | 5549 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5550 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5551 | coproc ? treg : treg + 1, | |
5552 | (int) BFD_RELOC_LO16, AT); | |
5553 | mips_optimize = hold_mips_optimize; | |
5554 | expr1.X_add_number -= 4; | |
5555 | ||
5556 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5557 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5558 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5559 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5560 | (char *) NULL); |
5561 | if (gpdel > 0) | |
5562 | { | |
5563 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5564 | p += 4; | |
5565 | } | |
5566 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 5567 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
5568 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5569 | p += 4; | |
5570 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5571 | p += 4; | |
5572 | if (breg != 0) | |
5573 | { | |
5574 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 5575 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
5576 | "d,v,t", AT, breg, AT); |
5577 | p += 4; | |
5578 | } | |
efec4a28 | 5579 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5580 | macro_build (p, &icnt, &expr1, s, fmt, |
5581 | coproc ? treg + 1 : treg, | |
5582 | (int) BFD_RELOC_LO16, AT); | |
5583 | p += 4; | |
5584 | expr1.X_add_number += 4; | |
5585 | ||
5586 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5587 | nop. */ | |
5588 | hold_mips_optimize = mips_optimize; | |
5589 | mips_optimize = 2; | |
efec4a28 | 5590 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5591 | macro_build (p, &icnt, &expr1, s, fmt, |
5592 | coproc ? treg : treg + 1, | |
5593 | (int) BFD_RELOC_LO16, AT); | |
5594 | mips_optimize = hold_mips_optimize; | |
5595 | } | |
d9aba805 ILT |
5596 | else if (mips_pic == EMBEDDED_PIC) |
5597 | { | |
5598 | /* If there is no base register, we use | |
5599 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5600 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5601 | If we have a base register, we use | |
5602 | addu $at,$breg,$gp | |
5603 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5604 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5605 | */ | |
5606 | if (breg == 0) | |
5607 | { | |
5608 | tempreg = GP; | |
5609 | used_at = 0; | |
5610 | } | |
5611 | else | |
5612 | { | |
5613 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5614 | mips_opts.isa < 3 ? "addu" : "daddu", |
d9aba805 ILT |
5615 | "d,v,t", AT, breg, GP); |
5616 | tempreg = AT; | |
5617 | used_at = 1; | |
5618 | } | |
5619 | ||
efec4a28 | 5620 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5621 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5622 | coproc ? treg + 1 : treg, | |
5623 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5624 | offset_expr.X_add_number += 4; | |
efec4a28 | 5625 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5626 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5627 | coproc ? treg : treg + 1, | |
5628 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5629 | } | |
5630 | else | |
5631 | abort (); | |
0dd2d296 ILT |
5632 | |
5633 | if (! used_at) | |
5634 | return; | |
5635 | ||
5636 | break; | |
5637 | ||
5638 | case M_LD_OB: | |
5639 | s = "lw"; | |
5640 | goto sd_ob; | |
5641 | case M_SD_OB: | |
5642 | s = "sw"; | |
5643 | sd_ob: | |
3c83da8a | 5644 | assert (mips_opts.isa < 3); |
0dd2d296 ILT |
5645 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5646 | (int) BFD_RELOC_LO16, breg); | |
5647 | offset_expr.X_add_number += 4; | |
5648 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5649 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5650 | return; |
efec4a28 DP |
5651 | |
5652 | /* New code added to support COPZ instructions. | |
5653 | This code builds table entries out of the macros in mip_opcodes. | |
5654 | R4000 uses interlocks to handle coproc delays. | |
5655 | Other chips (like the R3000) require nops to be inserted for delays. | |
5656 | ||
5657 | FIXME: Currently, we require that the user handle delays. | |
5658 | In order to fill delay slots for non-interlocked chips, | |
5659 | we must have a way to specify delays based on the coprocessor. | |
5660 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5661 | What are the side-effects of the cop instruction? | |
5662 | What cache support might we have and what are its effects? | |
5663 | Both coprocessor & memory require delays. how long??? | |
5664 | What registers are read/set/modified? | |
5665 | ||
5666 | If an itbl is provided to interpret cop instructions, | |
5667 | this knowledge can be encoded in the itbl spec. */ | |
5668 | ||
5669 | case M_COP0: | |
5670 | s = "cop0"; | |
5671 | goto copz; | |
5672 | case M_COP1: | |
5673 | s = "cop1"; | |
5674 | goto copz; | |
5675 | case M_COP2: | |
5676 | s = "cop2"; | |
5677 | goto copz; | |
5678 | case M_COP3: | |
5679 | s = "cop3"; | |
5680 | copz: | |
5681 | /* For now we just do C (same as Cz). */ | |
9218cee0 | 5682 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "C"); |
efec4a28 DP |
5683 | return; |
5684 | ||
917fae09 SS |
5685 | #ifdef LOSING_COMPILER |
5686 | default: | |
efec4a28 DP |
5687 | /* Try and see if this is a new itbl instruction. |
5688 | This code builds table entries out of the macros in mip_opcodes. | |
5689 | FIXME: For now we just assemble the expression and pass it's | |
5690 | value along as a 32-bit immediate. | |
5691 | We may want to have the assembler assemble this value, | |
5692 | so that we gain the assembler's knowledge of delay slots, | |
5693 | symbols, etc. | |
5694 | Would it be more efficient to use mask (id) here? */ | |
5695 | if (itbl_have_entries | |
9218cee0 | 5696 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
5697 | { |
5698 | s = ip->insn_mo->name; | |
5699 | s2 = "cop3"; | |
9218cee0 | 5700 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
5701 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
5702 | return; | |
5703 | } | |
917fae09 SS |
5704 | macro2 (ip); |
5705 | return; | |
5706 | } | |
3c83da8a | 5707 | if (mips_opts.noat) |
917fae09 SS |
5708 | as_warn ("Macro used $at after \".set noat\""); |
5709 | } | |
5710 | ||
5711 | static void | |
5712 | macro2 (ip) | |
5713 | struct mips_cl_insn *ip; | |
5714 | { | |
5715 | register int treg, sreg, dreg, breg; | |
5716 | int tempreg; | |
5717 | int mask; | |
5718 | int icnt = 0; | |
5719 | int used_at; | |
5720 | expressionS expr1; | |
5721 | const char *s; | |
5722 | const char *s2; | |
5723 | const char *fmt; | |
5724 | int likely = 0; | |
5725 | int dbl = 0; | |
5726 | int coproc = 0; | |
adcf2b9d ILT |
5727 | int lr = 0; |
5728 | int off; | |
917fae09 SS |
5729 | offsetT maxnum; |
5730 | bfd_reloc_code_real_type r; | |
5731 | char *p; | |
5732 | ||
5733 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5734 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5735 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5736 | mask = ip->insn_mo->mask; | |
5737 | ||
5738 | expr1.X_op = O_constant; | |
5739 | expr1.X_op_symbol = NULL; | |
5740 | expr1.X_add_symbol = NULL; | |
5741 | expr1.X_add_number = 1; | |
5742 | ||
5743 | switch (mask) | |
5744 | { | |
5745 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5746 | |
8358c818 ILT |
5747 | case M_DMUL: |
5748 | dbl = 1; | |
3d3c5039 | 5749 | case M_MUL: |
0dd2d296 | 5750 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5751 | dbl ? "dmultu" : "multu", |
5752 | "s,t", sreg, treg); | |
0dd2d296 | 5753 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5754 | return; |
3d3c5039 | 5755 | |
8358c818 ILT |
5756 | case M_DMUL_I: |
5757 | dbl = 1; | |
3d3c5039 | 5758 | case M_MUL_I: |
8358c818 ILT |
5759 | /* The MIPS assembler some times generates shifts and adds. I'm |
5760 | not trying to be that fancy. GCC should do this for us | |
5761 | anyway. */ | |
d8a1c247 | 5762 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5763 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5764 | dbl ? "dmult" : "mult", |
5765 | "s,t", sreg, AT); | |
0dd2d296 | 5766 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5767 | break; |
3d3c5039 | 5768 | |
8358c818 ILT |
5769 | case M_DMULO: |
5770 | dbl = 1; | |
5771 | case M_MULO: | |
fbcfacb7 | 5772 | mips_emit_delays (true); |
3c83da8a | 5773 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5774 | mips_any_noreorder = 1; |
5775 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5776 | dbl ? "dmult" : "mult", |
5777 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5778 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5779 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5780 | dbl ? "dsra32" : "sra", |
5781 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5782 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5783 | if (mips_trap) |
5784 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5785 | else | |
5786 | { | |
5787 | expr1.X_add_number = 8; | |
5788 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5789 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5790 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5791 | } | |
3c83da8a | 5792 | --mips_opts.noreorder; |
0dd2d296 | 5793 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5794 | break; |
5795 | ||
5796 | case M_DMULOU: | |
5797 | dbl = 1; | |
5798 | case M_MULOU: | |
fbcfacb7 | 5799 | mips_emit_delays (true); |
3c83da8a | 5800 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5801 | mips_any_noreorder = 1; |
5802 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5803 | dbl ? "dmultu" : "multu", |
5804 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5805 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5806 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5807 | if (mips_trap) |
5808 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5809 | else | |
5810 | { | |
5811 | expr1.X_add_number = 8; | |
5812 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5813 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5814 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5815 | } | |
3c83da8a | 5816 | --mips_opts.noreorder; |
8358c818 ILT |
5817 | break; |
5818 | ||
3d3c5039 | 5819 | case M_ROL: |
0dd2d296 ILT |
5820 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5821 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5822 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5823 | treg); | |
5824 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5825 | break; |
3d3c5039 ILT |
5826 | |
5827 | case M_ROL_I: | |
5c6f5923 GRK |
5828 | if (imm_expr.X_op != O_constant) |
5829 | as_bad ("rotate count too large"); | |
0dd2d296 | 5830 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5831 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5832 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5833 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5834 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5835 | break; |
3d3c5039 ILT |
5836 | |
5837 | case M_ROR: | |
0dd2d296 ILT |
5838 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5839 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5840 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5841 | treg); | |
5842 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5843 | break; |
3d3c5039 ILT |
5844 | |
5845 | case M_ROR_I: | |
5c6f5923 GRK |
5846 | if (imm_expr.X_op != O_constant) |
5847 | as_bad ("rotate count too large"); | |
0dd2d296 | 5848 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5849 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5850 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5851 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5852 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5853 | break; |
3d3c5039 ILT |
5854 | |
5855 | case M_S_DOB: | |
1c6f3441 ILT |
5856 | if (mips_4650) |
5857 | { | |
5858 | as_bad ("opcode not supported on this processor"); | |
5859 | return; | |
5860 | } | |
3c83da8a | 5861 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
5862 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5863 | to adjust when storing to memory. */ | |
0dd2d296 | 5864 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5865 | target_big_endian ? treg + 1 : treg, |
9226253a | 5866 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5867 | offset_expr.X_add_number += 4; |
0dd2d296 | 5868 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5869 | target_big_endian ? treg : treg + 1, |
9226253a | 5870 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5871 | return; |
3d3c5039 | 5872 | |
3d3c5039 | 5873 | case M_SEQ: |
670a50eb | 5874 | if (sreg == 0) |
0dd2d296 ILT |
5875 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5876 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5877 | else if (treg == 0) |
0dd2d296 ILT |
5878 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5879 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5880 | else |
5881 | { | |
0dd2d296 ILT |
5882 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5883 | sreg, treg); | |
5884 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5885 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5886 | } |
670a50eb | 5887 | return; |
3d3c5039 ILT |
5888 | |
5889 | case M_SEQ_I: | |
5c6f5923 | 5890 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 5891 | { |
0dd2d296 ILT |
5892 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5893 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5894 | return; |
3d3c5039 | 5895 | } |
670a50eb ILT |
5896 | if (sreg == 0) |
5897 | { | |
9a7d824a | 5898 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5899 | ip->insn_mo->name); |
0dd2d296 | 5900 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5901 | return; |
3d3c5039 | 5902 | } |
5c6f5923 GRK |
5903 | if (imm_expr.X_op == O_constant |
5904 | && imm_expr.X_add_number >= 0 | |
5905 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 5906 | { |
0dd2d296 ILT |
5907 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5908 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5909 | used_at = 0; |
6e8dda9c | 5910 | } |
5c6f5923 GRK |
5911 | else if (imm_expr.X_op == O_constant |
5912 | && imm_expr.X_add_number > -0x8000 | |
5913 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
5914 | { |
5915 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5916 | macro_build ((char *) NULL, &icnt, &imm_expr, |
3c83da8a | 5917 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5918 | "t,r,j", dreg, sreg, |
5919 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5920 | used_at = 0; |
5921 | } | |
5922 | else | |
5923 | { | |
d8a1c247 | 5924 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5925 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5926 | sreg, AT); | |
670a50eb ILT |
5927 | used_at = 1; |
5928 | } | |
0dd2d296 | 5929 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5930 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5931 | if (used_at) |
5932 | break; | |
5933 | return; | |
3d3c5039 ILT |
5934 | |
5935 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5936 | s = "slt"; |
5937 | goto sge; | |
3d3c5039 | 5938 | case M_SGEU: |
670a50eb | 5939 | s = "sltu"; |
3d3c5039 | 5940 | sge: |
0dd2d296 ILT |
5941 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5942 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5943 | (int) BFD_RELOC_LO16); |
670a50eb | 5944 | return; |
3d3c5039 | 5945 | |
670a50eb | 5946 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5947 | case M_SGEU_I: |
5c6f5923 GRK |
5948 | if (imm_expr.X_op == O_constant |
5949 | && imm_expr.X_add_number >= -0x8000 | |
5950 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 5951 | { |
0dd2d296 | 5952 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5953 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5954 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5955 | used_at = 0; |
5956 | } | |
5957 | else | |
5958 | { | |
d8a1c247 | 5959 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5960 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5961 | mask == M_SGE_I ? "slt" : "sltu", |
5962 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5963 | used_at = 1; |
5964 | } | |
0dd2d296 | 5965 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5966 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5967 | if (used_at) |
5968 | break; | |
5969 | return; | |
3d3c5039 ILT |
5970 | |
5971 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5972 | s = "slt"; |
5973 | goto sgt; | |
3d3c5039 | 5974 | case M_SGTU: |
670a50eb | 5975 | s = "sltu"; |
3d3c5039 | 5976 | sgt: |
0dd2d296 | 5977 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5978 | return; |
3d3c5039 | 5979 | |
670a50eb ILT |
5980 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5981 | s = "slt"; | |
5982 | goto sgti; | |
3d3c5039 | 5983 | case M_SGTU_I: |
670a50eb | 5984 | s = "sltu"; |
3d3c5039 | 5985 | sgti: |
d8a1c247 | 5986 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5987 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5988 | break; |
3d3c5039 | 5989 | |
670a50eb ILT |
5990 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5991 | s = "slt"; | |
5992 | goto sle; | |
3d3c5039 | 5993 | case M_SLEU: |
670a50eb | 5994 | s = "sltu"; |
3d3c5039 | 5995 | sle: |
0dd2d296 ILT |
5996 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5997 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5998 | (int) BFD_RELOC_LO16); |
670a50eb | 5999 | return; |
3d3c5039 | 6000 | |
670a50eb ILT |
6001 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
6002 | s = "slt"; | |
6003 | goto slei; | |
3d3c5039 | 6004 | case M_SLEU_I: |
670a50eb | 6005 | s = "sltu"; |
3d3c5039 | 6006 | slei: |
d8a1c247 | 6007 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6008 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
6009 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6010 | (int) BFD_RELOC_LO16); |
670a50eb | 6011 | break; |
3d3c5039 ILT |
6012 | |
6013 | case M_SLT_I: | |
5c6f5923 GRK |
6014 | if (imm_expr.X_op == O_constant |
6015 | && imm_expr.X_add_number >= -0x8000 | |
6016 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6017 | { |
0dd2d296 ILT |
6018 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
6019 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6020 | return; |
3d3c5039 | 6021 | } |
d8a1c247 | 6022 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6023 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 6024 | break; |
3d3c5039 ILT |
6025 | |
6026 | case M_SLTU_I: | |
5c6f5923 GRK |
6027 | if (imm_expr.X_op == O_constant |
6028 | && imm_expr.X_add_number >= -0x8000 | |
6029 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6030 | { |
0dd2d296 ILT |
6031 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
6032 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6033 | return; |
3d3c5039 | 6034 | } |
d8a1c247 | 6035 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6036 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
6037 | AT); | |
670a50eb | 6038 | break; |
3d3c5039 ILT |
6039 | |
6040 | case M_SNE: | |
670a50eb | 6041 | if (sreg == 0) |
0dd2d296 ILT |
6042 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6043 | treg); | |
670a50eb | 6044 | else if (treg == 0) |
0dd2d296 ILT |
6045 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6046 | sreg); | |
670a50eb ILT |
6047 | else |
6048 | { | |
0dd2d296 ILT |
6049 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6050 | sreg, treg); | |
6051 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6052 | dreg); | |
3d3c5039 | 6053 | } |
670a50eb | 6054 | return; |
3d3c5039 ILT |
6055 | |
6056 | case M_SNE_I: | |
5c6f5923 | 6057 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6058 | { |
0dd2d296 ILT |
6059 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6060 | sreg); | |
670a50eb | 6061 | return; |
3d3c5039 | 6062 | } |
670a50eb ILT |
6063 | if (sreg == 0) |
6064 | { | |
9a7d824a | 6065 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 6066 | ip->insn_mo->name); |
0dd2d296 | 6067 | macro_build ((char *) NULL, &icnt, &expr1, |
3c83da8a | 6068 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a | 6069 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 6070 | return; |
3d3c5039 | 6071 | } |
5c6f5923 GRK |
6072 | if (imm_expr.X_op == O_constant |
6073 | && imm_expr.X_add_number >= 0 | |
6074 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6075 | { |
0dd2d296 ILT |
6076 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
6077 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6078 | used_at = 0; |
6e8dda9c | 6079 | } |
5c6f5923 GRK |
6080 | else if (imm_expr.X_op == O_constant |
6081 | && imm_expr.X_add_number > -0x8000 | |
6082 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6083 | { |
6084 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6085 | macro_build ((char *) NULL, &icnt, &imm_expr, |
3c83da8a | 6086 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a | 6087 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
6088 | used_at = 0; |
6089 | } | |
6090 | else | |
6091 | { | |
d8a1c247 | 6092 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6093 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6094 | sreg, AT); | |
670a50eb ILT |
6095 | used_at = 1; |
6096 | } | |
0dd2d296 | 6097 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
6098 | if (used_at) |
6099 | break; | |
6100 | return; | |
3d3c5039 | 6101 | |
8358c818 ILT |
6102 | case M_DSUB_I: |
6103 | dbl = 1; | |
3d3c5039 | 6104 | case M_SUB_I: |
5c6f5923 GRK |
6105 | if (imm_expr.X_op == O_constant |
6106 | && imm_expr.X_add_number > -0x8000 | |
6107 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6108 | { |
6109 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6110 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6111 | dbl ? "daddi" : "addi", |
9226253a | 6112 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6113 | return; |
3d3c5039 | 6114 | } |
d8a1c247 | 6115 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6116 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6117 | dbl ? "dsub" : "sub", |
6118 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 6119 | break; |
3d3c5039 | 6120 | |
8358c818 ILT |
6121 | case M_DSUBU_I: |
6122 | dbl = 1; | |
3d3c5039 | 6123 | case M_SUBU_I: |
5c6f5923 GRK |
6124 | if (imm_expr.X_op == O_constant |
6125 | && imm_expr.X_add_number > -0x8000 | |
6126 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6127 | { |
6128 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6129 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6130 | dbl ? "daddiu" : "addiu", |
9226253a | 6131 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6132 | return; |
3d3c5039 | 6133 | } |
d8a1c247 | 6134 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6135 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6136 | dbl ? "dsubu" : "subu", |
6137 | "d,v,t", dreg, sreg, AT); | |
6138 | break; | |
6139 | ||
6140 | case M_TEQ_I: | |
6141 | s = "teq"; | |
6142 | goto trap; | |
6143 | case M_TGE_I: | |
6144 | s = "tge"; | |
6145 | goto trap; | |
6146 | case M_TGEU_I: | |
6147 | s = "tgeu"; | |
6148 | goto trap; | |
6149 | case M_TLT_I: | |
6150 | s = "tlt"; | |
6151 | goto trap; | |
6152 | case M_TLTU_I: | |
6153 | s = "tltu"; | |
6154 | goto trap; | |
6155 | case M_TNE_I: | |
6156 | s = "tne"; | |
6157 | trap: | |
d8a1c247 | 6158 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6159 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6160 | break; |
3d3c5039 ILT |
6161 | |
6162 | case M_TRUNCWD: | |
6163 | case M_TRUNCWS: | |
3c83da8a | 6164 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6165 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6166 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6167 | ||
6168 | /* | |
6169 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6170 | * or is there a reason for it? | |
6171 | */ | |
fbcfacb7 | 6172 | mips_emit_delays (true); |
3c83da8a | 6173 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6174 | mips_any_noreorder = 1; |
6175 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6176 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6177 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6178 | expr1.X_add_number = 3; |
0dd2d296 | 6179 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6180 | (int) BFD_RELOC_LO16); |
670a50eb | 6181 | expr1.X_add_number = 2; |
0dd2d296 | 6182 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6183 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6184 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6185 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6186 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6187 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6188 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6189 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6190 | --mips_opts.noreorder; |
670a50eb | 6191 | break; |
3d3c5039 ILT |
6192 | |
6193 | case M_ULH: | |
670a50eb ILT |
6194 | s = "lb"; |
6195 | goto ulh; | |
3d3c5039 | 6196 | case M_ULHU: |
670a50eb | 6197 | s = "lbu"; |
3d3c5039 | 6198 | ulh: |
8ea7f4e8 ILT |
6199 | if (offset_expr.X_add_number >= 0x7fff) |
6200 | as_bad ("operand overflow"); | |
670a50eb | 6201 | /* avoid load delay */ |
b9129c6f | 6202 | if (! target_big_endian) |
8ea7f4e8 | 6203 | offset_expr.X_add_number += 1; |
0dd2d296 | 6204 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6205 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6206 | if (! target_big_endian) |
8ea7f4e8 ILT |
6207 | offset_expr.X_add_number -= 1; |
6208 | else | |
6209 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6210 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6211 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6212 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6213 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6214 | break; |
3d3c5039 | 6215 | |
adcf2b9d ILT |
6216 | case M_ULD: |
6217 | s = "ldl"; | |
6218 | s2 = "ldr"; | |
6219 | off = 7; | |
6220 | goto ulw; | |
3d3c5039 | 6221 | case M_ULW: |
adcf2b9d ILT |
6222 | s = "lwl"; |
6223 | s2 = "lwr"; | |
6224 | off = 3; | |
6225 | ulw: | |
6226 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6227 | as_bad ("operand overflow"); |
b9129c6f | 6228 | if (! target_big_endian) |
adcf2b9d ILT |
6229 | offset_expr.X_add_number += off; |
6230 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6231 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6232 | if (! target_big_endian) |
adcf2b9d | 6233 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6234 | else |
adcf2b9d ILT |
6235 | offset_expr.X_add_number += off; |
6236 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6237 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6238 | return; |
3d3c5039 | 6239 | |
adcf2b9d ILT |
6240 | case M_ULD_A: |
6241 | s = "ldl"; | |
6242 | s2 = "ldr"; | |
6243 | off = 7; | |
6244 | goto ulwa; | |
6245 | case M_ULW_A: | |
6246 | s = "lwl"; | |
6247 | s2 = "lwr"; | |
6248 | off = 3; | |
6249 | ulwa: | |
6250 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6251 | if (breg != 0) |
6252 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6253 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6254 | "d,v,t", AT, AT, breg); |
b9129c6f | 6255 | if (! target_big_endian) |
adcf2b9d ILT |
6256 | expr1.X_add_number = off; |
6257 | else | |
6258 | expr1.X_add_number = 0; | |
6259 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6260 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6261 | if (! target_big_endian) |
adcf2b9d ILT |
6262 | expr1.X_add_number = 0; |
6263 | else | |
6264 | expr1.X_add_number = off; | |
6265 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6266 | (int) BFD_RELOC_LO16, AT); | |
6267 | break; | |
6268 | ||
3d3c5039 ILT |
6269 | case M_ULH_A: |
6270 | case M_ULHU_A: | |
0dd2d296 | 6271 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6272 | if (breg != 0) |
6273 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6274 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6275 | "d,v,t", AT, AT, breg); |
b9129c6f | 6276 | if (target_big_endian) |
adcf2b9d ILT |
6277 | expr1.X_add_number = 0; |
6278 | macro_build ((char *) NULL, &icnt, &expr1, | |
6279 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6280 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6281 | if (target_big_endian) |
adcf2b9d | 6282 | expr1.X_add_number = 1; |
670a50eb | 6283 | else |
adcf2b9d ILT |
6284 | expr1.X_add_number = 0; |
6285 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6286 | (int) BFD_RELOC_LO16, AT); | |
6287 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6288 | treg, 8); | |
6289 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6290 | treg, AT); | |
670a50eb | 6291 | break; |
3d3c5039 ILT |
6292 | |
6293 | case M_USH: | |
8ea7f4e8 ILT |
6294 | if (offset_expr.X_add_number >= 0x7fff) |
6295 | as_bad ("operand overflow"); | |
b9129c6f | 6296 | if (target_big_endian) |
8ea7f4e8 | 6297 | offset_expr.X_add_number += 1; |
0dd2d296 | 6298 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6299 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6300 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6301 | if (target_big_endian) |
8ea7f4e8 ILT |
6302 | offset_expr.X_add_number -= 1; |
6303 | else | |
6304 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6305 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6306 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6307 | break; |
3d3c5039 | 6308 | |
adcf2b9d ILT |
6309 | case M_USD: |
6310 | s = "sdl"; | |
6311 | s2 = "sdr"; | |
6312 | off = 7; | |
6313 | goto usw; | |
3d3c5039 | 6314 | case M_USW: |
adcf2b9d ILT |
6315 | s = "swl"; |
6316 | s2 = "swr"; | |
6317 | off = 3; | |
6318 | usw: | |
6319 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6320 | as_bad ("operand overflow"); |
b9129c6f | 6321 | if (! target_big_endian) |
adcf2b9d ILT |
6322 | offset_expr.X_add_number += off; |
6323 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6324 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6325 | if (! target_big_endian) |
adcf2b9d | 6326 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6327 | else |
adcf2b9d ILT |
6328 | offset_expr.X_add_number += off; |
6329 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6330 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6331 | return; |
3d3c5039 | 6332 | |
adcf2b9d ILT |
6333 | case M_USD_A: |
6334 | s = "sdl"; | |
6335 | s2 = "sdr"; | |
6336 | off = 7; | |
6337 | goto uswa; | |
3d3c5039 | 6338 | case M_USW_A: |
adcf2b9d ILT |
6339 | s = "swl"; |
6340 | s2 = "swr"; | |
6341 | off = 3; | |
6342 | uswa: | |
0dd2d296 | 6343 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6344 | if (breg != 0) |
6345 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6346 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6347 | "d,v,t", AT, AT, breg); |
b9129c6f | 6348 | if (! target_big_endian) |
adcf2b9d | 6349 | expr1.X_add_number = off; |
670a50eb | 6350 | else |
adcf2b9d ILT |
6351 | expr1.X_add_number = 0; |
6352 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6353 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6354 | if (! target_big_endian) |
adcf2b9d ILT |
6355 | expr1.X_add_number = 0; |
6356 | else | |
6357 | expr1.X_add_number = off; | |
6358 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6359 | (int) BFD_RELOC_LO16, AT); | |
6360 | break; | |
6361 | ||
6362 | case M_USH_A: | |
6363 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6364 | if (breg != 0) |
6365 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6366 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6367 | "d,v,t", AT, AT, breg); |
b9129c6f | 6368 | if (! target_big_endian) |
adcf2b9d ILT |
6369 | expr1.X_add_number = 0; |
6370 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6371 | (int) BFD_RELOC_LO16, AT); | |
6372 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6373 | treg, 8); | |
b9129c6f | 6374 | if (! target_big_endian) |
adcf2b9d ILT |
6375 | expr1.X_add_number = 1; |
6376 | else | |
6377 | expr1.X_add_number = 0; | |
6378 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6379 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6380 | if (! target_big_endian) |
adcf2b9d ILT |
6381 | expr1.X_add_number = 0; |
6382 | else | |
6383 | expr1.X_add_number = 1; | |
6384 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6385 | (int) BFD_RELOC_LO16, AT); | |
6386 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6387 | treg, 8); | |
6388 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6389 | treg, AT); | |
670a50eb | 6390 | break; |
3d3c5039 ILT |
6391 | |
6392 | default: | |
9218cee0 ILT |
6393 | /* FIXME: Check if this is one of the itbl macros, since they |
6394 | are added dynamically. */ | |
670a50eb | 6395 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 6396 | break; |
3d3c5039 | 6397 | } |
3c83da8a | 6398 | if (mips_opts.noat) |
670a50eb | 6399 | as_warn ("Macro used $at after \".set noat\""); |
3d3c5039 ILT |
6400 | } |
6401 | ||
cc5703cd | 6402 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6403 | |
3d3c5039 | 6404 | static void |
cc5703cd | 6405 | mips16_macro (ip) |
3d3c5039 ILT |
6406 | struct mips_cl_insn *ip; |
6407 | { | |
cc5703cd ILT |
6408 | int mask; |
6409 | int xreg, yreg, zreg, tmp; | |
6410 | int icnt; | |
6411 | expressionS expr1; | |
6412 | int dbl; | |
6413 | const char *s, *s2, *s3; | |
3d3c5039 | 6414 | |
cc5703cd | 6415 | mask = ip->insn_mo->mask; |
3d3c5039 | 6416 | |
cc5703cd ILT |
6417 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6418 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6419 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6420 | |
cc5703cd | 6421 | icnt = 0; |
8358c818 | 6422 | |
cc5703cd ILT |
6423 | expr1.X_op = O_constant; |
6424 | expr1.X_op_symbol = NULL; | |
6425 | expr1.X_add_symbol = NULL; | |
6426 | expr1.X_add_number = 1; | |
8358c818 | 6427 | |
cc5703cd | 6428 | dbl = 0; |
517078c1 | 6429 | |
cc5703cd ILT |
6430 | switch (mask) |
6431 | { | |
6432 | default: | |
6433 | internalError (); | |
6434 | ||
6435 | case M_DDIV_3: | |
6436 | dbl = 1; | |
6437 | case M_DIV_3: | |
6438 | s = "mflo"; | |
6439 | goto do_div3; | |
6440 | case M_DREM_3: | |
6441 | dbl = 1; | |
6442 | case M_REM_3: | |
6443 | s = "mfhi"; | |
6444 | do_div3: | |
fbcfacb7 | 6445 | mips_emit_delays (true); |
3c83da8a | 6446 | ++mips_opts.noreorder; |
cc5703cd ILT |
6447 | mips_any_noreorder = 1; |
6448 | macro_build ((char *) NULL, &icnt, NULL, | |
6449 | dbl ? "ddiv" : "div", | |
6450 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6451 | expr1.X_add_number = 2; |
cc5703cd | 6452 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6453 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6454 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6455 | since that causes an overflow. We should do that as well, | |
6456 | but I don't see how to do the comparisons without a temporary | |
6457 | register. */ | |
3c83da8a | 6458 | --mips_opts.noreorder; |
cc5703cd ILT |
6459 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6460 | break; | |
6461 | ||
6462 | case M_DIVU_3: | |
6463 | s = "divu"; | |
6464 | s2 = "mflo"; | |
6465 | goto do_divu3; | |
6466 | case M_REMU_3: | |
6467 | s = "divu"; | |
6468 | s2 = "mfhi"; | |
6469 | goto do_divu3; | |
6470 | case M_DDIVU_3: | |
6471 | s = "ddivu"; | |
6472 | s2 = "mflo"; | |
6473 | goto do_divu3; | |
6474 | case M_DREMU_3: | |
6475 | s = "ddivu"; | |
6476 | s2 = "mfhi"; | |
6477 | do_divu3: | |
fbcfacb7 | 6478 | mips_emit_delays (true); |
3c83da8a | 6479 | ++mips_opts.noreorder; |
cc5703cd ILT |
6480 | mips_any_noreorder = 1; |
6481 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6482 | expr1.X_add_number = 2; |
cc5703cd | 6483 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd | 6484 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
3c83da8a | 6485 | --mips_opts.noreorder; |
cc5703cd ILT |
6486 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6487 | break; | |
6488 | ||
08438bef ILT |
6489 | case M_DMUL: |
6490 | dbl = 1; | |
6491 | case M_MUL: | |
6492 | macro_build ((char *) NULL, &icnt, NULL, | |
6493 | dbl ? "dmultu" : "multu", | |
6494 | "x,y", xreg, yreg); | |
6495 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6496 | return; | |
6497 | ||
cc5703cd ILT |
6498 | case M_DSUBU_I: |
6499 | dbl = 1; | |
6500 | goto do_subu; | |
6501 | case M_SUBU_I: | |
6502 | do_subu: | |
5c6f5923 GRK |
6503 | if (imm_expr.X_op != O_constant) |
6504 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6505 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6506 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6507 | dbl ? "daddiu" : "addiu", | |
6508 | "y,x,4", yreg, xreg); | |
6509 | break; | |
6510 | ||
6511 | case M_SUBU_I_2: | |
5c6f5923 GRK |
6512 | if (imm_expr.X_op != O_constant) |
6513 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6514 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6515 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6516 | "x,k", xreg); | |
6517 | break; | |
6518 | ||
6519 | case M_DSUBU_I_2: | |
5c6f5923 GRK |
6520 | if (imm_expr.X_op != O_constant) |
6521 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6522 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6523 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6524 | "y,j", yreg); | |
6525 | break; | |
6526 | ||
6527 | case M_BEQ: | |
6528 | s = "cmp"; | |
6529 | s2 = "bteqz"; | |
6530 | goto do_branch; | |
6531 | case M_BNE: | |
6532 | s = "cmp"; | |
6533 | s2 = "btnez"; | |
6534 | goto do_branch; | |
6535 | case M_BLT: | |
6536 | s = "slt"; | |
6537 | s2 = "btnez"; | |
6538 | goto do_branch; | |
6539 | case M_BLTU: | |
6540 | s = "sltu"; | |
6541 | s2 = "btnez"; | |
6542 | goto do_branch; | |
6543 | case M_BLE: | |
6544 | s = "slt"; | |
6545 | s2 = "bteqz"; | |
6546 | goto do_reverse_branch; | |
6547 | case M_BLEU: | |
6548 | s = "sltu"; | |
6549 | s2 = "bteqz"; | |
6550 | goto do_reverse_branch; | |
6551 | case M_BGE: | |
6552 | s = "slt"; | |
6553 | s2 = "bteqz"; | |
6554 | goto do_branch; | |
6555 | case M_BGEU: | |
6556 | s = "sltu"; | |
6557 | s2 = "bteqz"; | |
6558 | goto do_branch; | |
6559 | case M_BGT: | |
6560 | s = "slt"; | |
6561 | s2 = "btnez"; | |
6562 | goto do_reverse_branch; | |
6563 | case M_BGTU: | |
6564 | s = "sltu"; | |
6565 | s2 = "btnez"; | |
6566 | ||
6567 | do_reverse_branch: | |
6568 | tmp = xreg; | |
6569 | xreg = yreg; | |
6570 | yreg = tmp; | |
6571 | ||
6572 | do_branch: | |
6573 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6574 | xreg, yreg); | |
6575 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6576 | break; | |
6577 | ||
6578 | case M_BEQ_I: | |
6579 | s = "cmpi"; | |
6580 | s2 = "bteqz"; | |
6581 | s3 = "x,U"; | |
6582 | goto do_branch_i; | |
6583 | case M_BNE_I: | |
6584 | s = "cmpi"; | |
6585 | s2 = "btnez"; | |
6586 | s3 = "x,U"; | |
6587 | goto do_branch_i; | |
6588 | case M_BLT_I: | |
6589 | s = "slti"; | |
6590 | s2 = "btnez"; | |
6591 | s3 = "x,8"; | |
6592 | goto do_branch_i; | |
6593 | case M_BLTU_I: | |
6594 | s = "sltiu"; | |
6595 | s2 = "btnez"; | |
6596 | s3 = "x,8"; | |
6597 | goto do_branch_i; | |
6598 | case M_BLE_I: | |
6599 | s = "slti"; | |
6600 | s2 = "btnez"; | |
6601 | s3 = "x,8"; | |
6602 | goto do_addone_branch_i; | |
6603 | case M_BLEU_I: | |
6604 | s = "sltiu"; | |
6605 | s2 = "btnez"; | |
6606 | s3 = "x,8"; | |
6607 | goto do_addone_branch_i; | |
6608 | case M_BGE_I: | |
6609 | s = "slti"; | |
6610 | s2 = "bteqz"; | |
6611 | s3 = "x,8"; | |
6612 | goto do_branch_i; | |
6613 | case M_BGEU_I: | |
6614 | s = "sltiu"; | |
6615 | s2 = "bteqz"; | |
6616 | s3 = "x,8"; | |
6617 | goto do_branch_i; | |
6618 | case M_BGT_I: | |
6619 | s = "slti"; | |
6620 | s2 = "bteqz"; | |
6621 | s3 = "x,8"; | |
6622 | goto do_addone_branch_i; | |
6623 | case M_BGTU_I: | |
6624 | s = "sltiu"; | |
6625 | s2 = "bteqz"; | |
6626 | s3 = "x,8"; | |
6627 | ||
6628 | do_addone_branch_i: | |
5c6f5923 GRK |
6629 | if (imm_expr.X_op != O_constant) |
6630 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6631 | ++imm_expr.X_add_number; |
6632 | ||
6633 | do_branch_i: | |
6634 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6635 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6636 | break; | |
18e0764d ILT |
6637 | |
6638 | case M_ABS: | |
6639 | expr1.X_add_number = 0; | |
6640 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6641 | if (xreg != yreg) | |
6642 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6643 | "move", "y,X", xreg, yreg); | |
6644 | expr1.X_add_number = 2; | |
6645 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6646 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6647 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6648 | } |
6649 | } | |
6650 | ||
aa2e0460 KR |
6651 | /* For consistency checking, verify that all bits are specified either |
6652 | by the match/mask part of the instruction definition, or by the | |
6653 | operand list. */ | |
6654 | static int | |
6655 | validate_mips_insn (opc) | |
6656 | const struct mips_opcode *opc; | |
6657 | { | |
6658 | const char *p = opc->args; | |
6659 | char c; | |
6660 | unsigned long used_bits = opc->mask; | |
6661 | ||
6662 | if ((used_bits & opc->match) != opc->match) | |
6663 | { | |
6664 | as_bad ("internal: bad mips opcode (mask error): %s %s", | |
6665 | opc->name, opc->args); | |
6666 | return 0; | |
6667 | } | |
6668 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6669 | while (*p) | |
6670 | switch (c = *p++) | |
6671 | { | |
6672 | case ',': break; | |
6673 | case '(': break; | |
6674 | case ')': break; | |
6675 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6676 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6677 | case 'A': break; | |
6678 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
6679 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
6680 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6681 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6682 | case 'F': break; | |
6683 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6684 | case 'I': break; | |
6685 | case 'L': break; | |
6686 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6687 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6688 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6689 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6690 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6691 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6692 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6693 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6694 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6695 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6696 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6697 | case 'f': break; | |
6698 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6699 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6700 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6701 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6702 | case 'l': break; | |
6703 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6704 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6705 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6706 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6707 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6708 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6709 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6710 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6711 | case 'x': break; | |
6712 | case 'z': break; | |
aa2e0460 | 6713 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
1c6f3441 | 6714 | /* start-sanitize-vr5400 */ |
aa2e0460 KR |
6715 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
6716 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
6717 | case '[': break; | |
6718 | case ']': break; | |
6719 | /* end-sanitize-vr5400 */ | |
6720 | default: | |
6721 | as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s", | |
6722 | c, opc->name, opc->args); | |
6723 | return 0; | |
6724 | } | |
6725 | #undef USE_BITS | |
6726 | /* Some of the trapping instructions (break, t*, sdbbp) have "code" | |
6727 | fields that cannot currently be set by assembly code. Ignore them | |
6728 | for now. */ | |
6729 | if (opc->pinfo & INSN_TRAP) | |
6730 | { | |
6731 | static const char *const trap_insns[] = { | |
6732 | "break", "sdbbp", | |
6733 | "teq", "tge", "tgeu", "tlt", "tltu", "tne", | |
6734 | }; | |
6735 | int i; | |
6736 | for (i = sizeof(trap_insns)/sizeof(trap_insns[0]) - 1; i >= 0; i--) | |
6737 | if (!strcmp (trap_insns[i], opc->name)) | |
6738 | { | |
6739 | used_bits |= 0xffc0; | |
6740 | break; | |
6741 | } | |
6742 | } | |
6743 | if (used_bits != 0xffffffff) | |
6744 | { | |
6745 | as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s", | |
6746 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
6747 | return 0; | |
6748 | } | |
6749 | return 1; | |
6750 | } | |
6751 | ||
cc5703cd ILT |
6752 | /* This routine assembles an instruction into its binary format. As a |
6753 | side effect, it sets one of the global variables imm_reloc or | |
6754 | offset_reloc to the type of relocation to do if one of the operands | |
6755 | is an address expression. */ | |
6756 | ||
6757 | static void | |
6758 | mips_ip (str, ip) | |
6759 | char *str; | |
6760 | struct mips_cl_insn *ip; | |
6761 | { | |
6762 | char *s; | |
6763 | const char *args; | |
6764 | char c; | |
6765 | struct mips_opcode *insn; | |
6766 | char *argsStart; | |
6767 | unsigned int regno; | |
6768 | unsigned int lastregno = 0; | |
6769 | char *s_reset; | |
6770 | ||
6771 | insn_error = NULL; | |
6772 | ||
e2e5acfa | 6773 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 6774 | continue; |
1857d1e6 | 6775 | if (isspace (*s)) |
e2e5acfa | 6776 | *s++ = '\0'; |
1857d1e6 | 6777 | |
cc5703cd ILT |
6778 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
6779 | { | |
6780 | insn_error = "unrecognized opcode"; | |
6781 | return; | |
6782 | } | |
6783 | argsStart = s; | |
6784 | for (;;) | |
6785 | { | |
6786 | int insn_isa; | |
a652f74c | 6787 | boolean ok; |
cc5703cd ILT |
6788 | |
6789 | assert (strcmp (insn->name, str) == 0); | |
6790 | ||
1c6f3441 | 6791 | if ((insn->membership & INSN_ISA) == INSN_ISA1) |
931a1858 | 6792 | insn_isa = 1; |
5c6f5923 | 6793 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 6794 | insn_isa = 2; |
5c6f5923 | 6795 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 6796 | insn_isa = 3; |
5c6f5923 | 6797 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
6798 | insn_isa = 4; |
6799 | else | |
931a1858 | 6800 | insn_isa = 15; |
cc5703cd | 6801 | |
a652f74c ILT |
6802 | if (insn_isa <= mips_opts.isa) |
6803 | ok = true; | |
6804 | else if (insn->pinfo == INSN_MACRO) | |
6805 | ok = false; | |
6806 | else if ((mips_4650 && (insn->membership & INSN_4650) != 0) | |
6807 | || (mips_4010 && (insn->membership & INSN_4010) != 0) | |
6808 | || (mips_4100 && (insn->membership & INSN_4100) != 0) | |
42444087 GRK |
6809 | /* start-sanitize-tx49 */ |
6810 | || (mips_4900 && (insn->membership & INSN_4900) != 0) | |
6811 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
6812 | /* start-sanitize-r5900 */ |
6813 | || (mips_5900 && (insn->membership & INSN_5900) != 0) | |
6814 | /* end-sanitize-r5900 */ | |
aa2e0460 KR |
6815 | /* start-sanitize-vr5400 */ |
6816 | || (mips_5400 && (insn->membership & INSN_5400) != 0) | |
6817 | /* end-sanitize-vr5400 */ | |
a652f74c | 6818 | || (mips_3900 && (insn->membership & INSN_3900) != 0)) |
1c6f3441 | 6819 | ok = true; |
a652f74c ILT |
6820 | else |
6821 | ok = false; | |
6822 | ||
b2cf4548 DE |
6823 | if (insn->pinfo != INSN_MACRO) |
6824 | { | |
6825 | if (mips_4650 && (insn->pinfo & FP_D) != 0) | |
6826 | ok = false; | |
6827 | /* start-sanitize-r5900 */ | |
6828 | if (mips_5900 && (insn->pinfo & FP_D) != 0) | |
6829 | ok = false; | |
6830 | /* end-sanitize-r5900 */ | |
6831 | } | |
1c6f3441 | 6832 | |
a652f74c | 6833 | if (! ok) |
cc5703cd ILT |
6834 | { |
6835 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6836 | && strcmp (insn->name, insn[1].name) == 0) | |
6837 | { | |
6838 | ++insn; | |
6839 | continue; | |
6840 | } | |
6fd819cf GRK |
6841 | if (insn_isa == 15 |
6842 | || insn_isa <= mips_opts.isa) | |
cc5703cd ILT |
6843 | insn_error = "opcode not supported on this processor"; |
6844 | else | |
6845 | { | |
6846 | static char buf[100]; | |
6847 | ||
6848 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6849 | insn_error = buf; | |
6850 | } | |
6851 | return; | |
6852 | } | |
8358c818 | 6853 | |
670a50eb ILT |
6854 | ip->insn_mo = insn; |
6855 | ip->insn_opcode = insn->match; | |
6856 | for (args = insn->args;; ++args) | |
6857 | { | |
6858 | if (*s == ' ') | |
6859 | ++s; | |
6860 | switch (*args) | |
6861 | { | |
6862 | case '\0': /* end of args */ | |
6863 | if (*s == '\0') | |
6864 | return; | |
6865 | break; | |
3d3c5039 ILT |
6866 | |
6867 | case ',': | |
670a50eb ILT |
6868 | if (*s++ == *args) |
6869 | continue; | |
6870 | s--; | |
6871 | switch (*++args) | |
6872 | { | |
3d3c5039 ILT |
6873 | case 'r': |
6874 | case 'v': | |
670a50eb ILT |
6875 | ip->insn_opcode |= lastregno << 21; |
6876 | continue; | |
3d3c5039 ILT |
6877 | |
6878 | case 'w': | |
6879 | case 'W': | |
670a50eb ILT |
6880 | ip->insn_opcode |= lastregno << 16; |
6881 | continue; | |
3d3c5039 ILT |
6882 | |
6883 | case 'V': | |
670a50eb ILT |
6884 | ip->insn_opcode |= lastregno << 11; |
6885 | continue; | |
3d3c5039 | 6886 | } |
670a50eb | 6887 | break; |
3d3c5039 ILT |
6888 | |
6889 | case '(': | |
670a50eb ILT |
6890 | /* handle optional base register. |
6891 | Either the base register is omitted or | |
6892 | we must have a left paren. */ | |
6893 | /* this is dependent on the next operand specifier | |
6894 | is a 'b' for base register */ | |
6895 | assert (args[1] == 'b'); | |
6896 | if (*s == '\0') | |
6897 | return; | |
3d3c5039 | 6898 | |
670a50eb | 6899 | case ')': /* these must match exactly */ |
aa2e0460 KR |
6900 | /* start-sanitize-vr5400 */ |
6901 | case '[': | |
6902 | case ']': | |
6903 | /* end-sanitize-vr5400 */ | |
670a50eb | 6904 | if (*s++ == *args) |
3d3c5039 | 6905 | continue; |
670a50eb ILT |
6906 | break; |
6907 | ||
6908 | case '<': /* must be at least one digit */ | |
6909 | /* | |
6910 | * According to the manual, if the shift amount is greater | |
6911 | * than 31 or less than 0 the the shift amount should be | |
6912 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6913 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6914 | */ |
6915 | my_getExpression (&imm_expr, s); | |
6916 | check_absolute_expr (ip, &imm_expr); | |
6917 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6918 | { | |
58d4951d ILT |
6919 | as_warn ("Improper shift amount (%ld)", |
6920 | (long) imm_expr.X_add_number); | |
9226253a | 6921 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6922 | } |
6923 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6924 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6925 | s = expr_end; |
6926 | continue; | |
6927 | ||
56c96faa ILT |
6928 | case '>': /* shift amount minus 32 */ |
6929 | my_getExpression (&imm_expr, s); | |
6930 | check_absolute_expr (ip, &imm_expr); | |
6931 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6932 | || (unsigned long) imm_expr.X_add_number > 63) | |
6933 | break; | |
6934 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6935 | imm_expr.X_op = O_absent; | |
6936 | s = expr_end; | |
6937 | continue; | |
6938 | ||
9226253a | 6939 | case 'k': /* cache code */ |
d8a1c247 | 6940 | case 'h': /* prefx code */ |
9226253a ILT |
6941 | my_getExpression (&imm_expr, s); |
6942 | check_absolute_expr (ip, &imm_expr); | |
6943 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6944 | { | |
d8a1c247 KR |
6945 | as_warn ("Invalid value for `%s' (%lu)", |
6946 | ip->insn_mo->name, | |
9226253a ILT |
6947 | (unsigned long) imm_expr.X_add_number); |
6948 | imm_expr.X_add_number &= 0x1f; | |
6949 | } | |
d8a1c247 KR |
6950 | if (*args == 'k') |
6951 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6952 | else | |
6953 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6954 | imm_expr.X_op = O_absent; |
6955 | s = expr_end; | |
6956 | continue; | |
6957 | ||
670a50eb ILT |
6958 | case 'c': /* break code */ |
6959 | my_getExpression (&imm_expr, s); | |
6960 | check_absolute_expr (ip, &imm_expr); | |
6961 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6962 | as_warn ("Illegal break code (%ld)", |
6963 | (long) imm_expr.X_add_number); | |
670a50eb | 6964 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6965 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6966 | s = expr_end; |
6967 | continue; | |
6968 | ||
918692a5 ILT |
6969 | case 'B': /* syscall code */ |
6970 | my_getExpression (&imm_expr, s); | |
6971 | check_absolute_expr (ip, &imm_expr); | |
6972 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6973 | as_warn ("Illegal syscall code (%ld)", |
6974 | (long) imm_expr.X_add_number); | |
918692a5 | 6975 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6976 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6977 | s = expr_end; |
6978 | continue; | |
6979 | ||
0aa07269 ILT |
6980 | case 'C': /* Coprocessor code */ |
6981 | my_getExpression (&imm_expr, s); | |
6982 | check_absolute_expr (ip, &imm_expr); | |
6983 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6984 | { | |
58d4951d ILT |
6985 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6986 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6987 | imm_expr.X_add_number &= ((1<<25) - 1); |
6988 | } | |
6989 | ip->insn_opcode |= imm_expr.X_add_number; | |
6990 | imm_expr.X_op = O_absent; | |
6991 | s = expr_end; | |
6992 | continue; | |
6993 | ||
670a50eb ILT |
6994 | case 'b': /* base register */ |
6995 | case 'd': /* destination register */ | |
6996 | case 's': /* source register */ | |
6997 | case 't': /* target register */ | |
6998 | case 'r': /* both target and source */ | |
6999 | case 'v': /* both dest and source */ | |
7000 | case 'w': /* both dest and target */ | |
918692a5 ILT |
7001 | case 'E': /* coprocessor target register */ |
7002 | case 'G': /* coprocessor destination register */ | |
8358c818 | 7003 | case 'x': /* ignore register name */ |
ff3a5c18 | 7004 | case 'z': /* must be zero register */ |
b3ed1af3 | 7005 | case 'P': /* performance register */ |
670a50eb ILT |
7006 | s_reset = s; |
7007 | if (s[0] == '$') | |
7008 | { | |
7009 | if (isdigit (s[1])) | |
7010 | { | |
7011 | ++s; | |
7012 | regno = 0; | |
7013 | do | |
7014 | { | |
7015 | regno *= 10; | |
7016 | regno += *s - '0'; | |
7017 | ++s; | |
7018 | } | |
7019 | while (isdigit (*s)); | |
0aa07269 ILT |
7020 | if (regno > 31) |
7021 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 7022 | } |
0dd2d296 ILT |
7023 | else if (*args == 'E' || *args == 'G') |
7024 | goto notreg; | |
7025 | else | |
670a50eb | 7026 | { |
0aa07269 ILT |
7027 | if (s[1] == 'f' && s[2] == 'p') |
7028 | { | |
7029 | s += 3; | |
9226253a | 7030 | regno = FP; |
0aa07269 ILT |
7031 | } |
7032 | else if (s[1] == 's' && s[2] == 'p') | |
7033 | { | |
7034 | s += 3; | |
9226253a | 7035 | regno = SP; |
0aa07269 ILT |
7036 | } |
7037 | else if (s[1] == 'g' && s[2] == 'p') | |
7038 | { | |
7039 | s += 3; | |
9226253a | 7040 | regno = GP; |
0aa07269 ILT |
7041 | } |
7042 | else if (s[1] == 'a' && s[2] == 't') | |
7043 | { | |
7044 | s += 3; | |
9226253a | 7045 | regno = AT; |
0aa07269 | 7046 | } |
b2b8c24e ILT |
7047 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
7048 | { | |
7049 | s += 4; | |
7050 | regno = KT0; | |
7051 | } | |
7052 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7053 | { | |
7054 | s += 4; | |
7055 | regno = KT1; | |
7056 | } | |
efec4a28 DP |
7057 | else if (itbl_have_entries) |
7058 | { | |
7059 | char *p, *n; | |
7060 | int r; | |
7061 | ||
7062 | p = s+1; /* advance past '$' */ | |
9218cee0 | 7063 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
7064 | |
7065 | /* See if this is a register defined in an | |
7066 | itbl entry */ | |
9218cee0 ILT |
7067 | r = itbl_get_reg_val (n); |
7068 | if (r) | |
efec4a28 | 7069 | { |
9218cee0 ILT |
7070 | /* Get_field advances to the start of |
7071 | the next field, so we need to back | |
7072 | rack to the end of the last field. */ | |
efec4a28 | 7073 | if (p) |
9218cee0 | 7074 | s = p - 1; |
efec4a28 | 7075 | else |
9218cee0 | 7076 | s = strchr (s,'\0'); |
efec4a28 DP |
7077 | regno = r; |
7078 | } | |
7079 | else | |
7080 | goto notreg; | |
7081 | } | |
0aa07269 ILT |
7082 | else |
7083 | goto notreg; | |
670a50eb | 7084 | } |
9753202d | 7085 | if (regno == AT |
3c83da8a | 7086 | && ! mips_opts.noat |
9753202d | 7087 | && *args != 'E' |
1c6f3441 | 7088 | && *args != 'P' |
9753202d | 7089 | && *args != 'G') |
13fe1379 | 7090 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
7091 | c = *args; |
7092 | if (*s == ' ') | |
7093 | s++; | |
7094 | if (args[1] != *s) | |
7095 | { | |
7096 | if (c == 'r' || c == 'v' || c == 'w') | |
7097 | { | |
7098 | regno = lastregno; | |
7099 | s = s_reset; | |
7100 | args++; | |
7101 | } | |
7102 | } | |
ff3a5c18 ILT |
7103 | /* 'z' only matches $0. */ |
7104 | if (c == 'z' && regno != 0) | |
7105 | break; | |
efec4a28 DP |
7106 | |
7107 | /* Now that we have assembled one operand, we use the args string | |
7108 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
7109 | switch (c) |
7110 | { | |
3d3c5039 ILT |
7111 | case 'r': |
7112 | case 's': | |
7113 | case 'v': | |
7114 | case 'b': | |
670a50eb ILT |
7115 | ip->insn_opcode |= regno << 21; |
7116 | break; | |
3d3c5039 | 7117 | case 'd': |
918692a5 | 7118 | case 'G': |
670a50eb ILT |
7119 | ip->insn_opcode |= regno << 11; |
7120 | break; | |
3d3c5039 ILT |
7121 | case 'w': |
7122 | case 't': | |
918692a5 | 7123 | case 'E': |
670a50eb | 7124 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
7125 | break; |
7126 | case 'x': | |
7127 | /* This case exists because on the r3000 trunc | |
7128 | expands into a macro which requires a gp | |
7129 | register. On the r6000 or r4000 it is | |
7130 | assembled into a single instruction which | |
7131 | ignores the register. Thus the insn version | |
7132 | is MIPS_ISA2 and uses 'x', and the macro | |
7133 | version is MIPS_ISA1 and uses 't'. */ | |
7134 | break; | |
ff3a5c18 ILT |
7135 | case 'z': |
7136 | /* This case is for the div instruction, which | |
7137 | acts differently if the destination argument | |
7138 | is $0. This only matches $0, and is checked | |
7139 | outside the switch. */ | |
7140 | break; | |
efec4a28 DP |
7141 | case 'D': |
7142 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7143 | break; | |
1c6f3441 ILT |
7144 | case 'P': |
7145 | ip->insn_opcode |= regno << 1; | |
7146 | break; | |
9218cee0 ILT |
7147 | /* What about all other operands like 'i', which |
7148 | can be specified in the opcode table? */ | |
3d3c5039 | 7149 | } |
670a50eb ILT |
7150 | lastregno = regno; |
7151 | continue; | |
3d3c5039 ILT |
7152 | } |
7153 | notreg: | |
670a50eb ILT |
7154 | switch (*args++) |
7155 | { | |
3d3c5039 ILT |
7156 | case 'r': |
7157 | case 'v': | |
670a50eb ILT |
7158 | ip->insn_opcode |= lastregno << 21; |
7159 | continue; | |
3d3c5039 | 7160 | case 'w': |
670a50eb ILT |
7161 | ip->insn_opcode |= lastregno << 16; |
7162 | continue; | |
3d3c5039 | 7163 | } |
670a50eb | 7164 | break; |
3d3c5039 | 7165 | |
670a50eb ILT |
7166 | case 'D': /* floating point destination register */ |
7167 | case 'S': /* floating point source register */ | |
7168 | case 'T': /* floating point target register */ | |
d8a1c247 | 7169 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
7170 | case 'V': |
7171 | case 'W': | |
670a50eb ILT |
7172 | s_reset = s; |
7173 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
7174 | { | |
7175 | s += 2; | |
7176 | regno = 0; | |
7177 | do | |
7178 | { | |
7179 | regno *= 10; | |
7180 | regno += *s - '0'; | |
7181 | ++s; | |
7182 | } | |
7183 | while (isdigit (*s)); | |
7184 | ||
7185 | if (regno > 31) | |
7186 | as_bad ("Invalid float register number (%d)", regno); | |
7187 | ||
9226253a | 7188 | if ((regno & 1) != 0 |
3c83da8a | 7189 | && mips_opts.isa < 3 |
538034cf ILT |
7190 | && ! (strcmp (str, "mtc1") == 0 |
7191 | || strcmp (str, "mfc1") == 0 | |
7192 | || strcmp (str, "lwc1") == 0 | |
7193 | || strcmp (str, "swc1") == 0 | |
7194 | || strcmp (str, "l.s") == 0 | |
7195 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
7196 | as_warn ("Float register should be even, was %d", |
7197 | regno); | |
7198 | ||
7199 | c = *args; | |
7200 | if (*s == ' ') | |
7201 | s++; | |
7202 | if (args[1] != *s) | |
7203 | { | |
7204 | if (c == 'V' || c == 'W') | |
7205 | { | |
7206 | regno = lastregno; | |
7207 | s = s_reset; | |
7208 | args++; | |
3d3c5039 ILT |
7209 | } |
7210 | } | |
670a50eb ILT |
7211 | switch (c) |
7212 | { | |
3d3c5039 | 7213 | case 'D': |
670a50eb ILT |
7214 | ip->insn_opcode |= regno << 6; |
7215 | break; | |
3d3c5039 ILT |
7216 | case 'V': |
7217 | case 'S': | |
670a50eb ILT |
7218 | ip->insn_opcode |= regno << 11; |
7219 | break; | |
3d3c5039 ILT |
7220 | case 'W': |
7221 | case 'T': | |
670a50eb | 7222 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
7223 | break; |
7224 | case 'R': | |
7225 | ip->insn_opcode |= regno << 21; | |
7226 | break; | |
3d3c5039 | 7227 | } |
670a50eb ILT |
7228 | lastregno = regno; |
7229 | continue; | |
3d3c5039 | 7230 | } |
670a50eb ILT |
7231 | switch (*args++) |
7232 | { | |
3d3c5039 | 7233 | case 'V': |
670a50eb ILT |
7234 | ip->insn_opcode |= lastregno << 11; |
7235 | continue; | |
3d3c5039 | 7236 | case 'W': |
670a50eb ILT |
7237 | ip->insn_opcode |= lastregno << 16; |
7238 | continue; | |
3d3c5039 | 7239 | } |
670a50eb | 7240 | break; |
3d3c5039 ILT |
7241 | |
7242 | case 'I': | |
670a50eb | 7243 | my_getExpression (&imm_expr, s); |
9753202d ILT |
7244 | if (imm_expr.X_op != O_big |
7245 | && imm_expr.X_op != O_constant) | |
7246 | insn_error = "absolute expression required"; | |
670a50eb ILT |
7247 | s = expr_end; |
7248 | continue; | |
3d3c5039 ILT |
7249 | |
7250 | case 'A': | |
670a50eb ILT |
7251 | my_getExpression (&offset_expr, s); |
7252 | imm_reloc = BFD_RELOC_32; | |
7253 | s = expr_end; | |
7254 | continue; | |
3d3c5039 ILT |
7255 | |
7256 | case 'F': | |
19ed8960 ILT |
7257 | case 'L': |
7258 | case 'f': | |
7259 | case 'l': | |
7260 | { | |
7261 | int f64; | |
7262 | char *save_in; | |
7263 | char *err; | |
7264 | unsigned char temp[8]; | |
604633ae ILT |
7265 | int len; |
7266 | unsigned int length; | |
19ed8960 ILT |
7267 | segT seg; |
7268 | subsegT subseg; | |
7269 | char *p; | |
7270 | ||
7271 | /* These only appear as the last operand in an | |
7272 | instruction, and every instruction that accepts | |
7273 | them in any variant accepts them in all variants. | |
7274 | This means we don't have to worry about backing out | |
7275 | any changes if the instruction does not match. | |
7276 | ||
7277 | The difference between them is the size of the | |
7278 | floating point constant and where it goes. For 'F' | |
7279 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7280 | is 32 bits. Where the constant is placed is based | |
7281 | on how the MIPS assembler does things: | |
7282 | F -- .rdata | |
7283 | L -- .lit8 | |
7284 | f -- immediate value | |
7285 | l -- .lit4 | |
0dd2d296 | 7286 | |
55933a58 ILT |
7287 | The .lit4 and .lit8 sections are only used if |
7288 | permitted by the -G argument. | |
7289 | ||
7290 | When generating embedded PIC code, we use the | |
7291 | .lit8 section but not the .lit4 section (we can do | |
7292 | .lit4 inline easily; we need to put .lit8 | |
7293 | somewhere in the data segment, and using .lit8 | |
7294 | permits the linker to eventually combine identical | |
7295 | .lit8 entries). */ | |
19ed8960 ILT |
7296 | |
7297 | f64 = *args == 'F' || *args == 'L'; | |
7298 | ||
7299 | save_in = input_line_pointer; | |
7300 | input_line_pointer = s; | |
604633ae ILT |
7301 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
7302 | length = len; | |
19ed8960 ILT |
7303 | s = input_line_pointer; |
7304 | input_line_pointer = save_in; | |
7305 | if (err != NULL && *err != '\0') | |
7306 | { | |
7307 | as_bad ("Bad floating point constant: %s", err); | |
7308 | memset (temp, '\0', sizeof temp); | |
7309 | length = f64 ? 8 : 4; | |
7310 | } | |
7311 | ||
7312 | assert (length == (f64 ? 8 : 4)); | |
7313 | ||
0dd2d296 | 7314 | if (*args == 'f' |
55933a58 | 7315 | || (*args == 'l' |
1dc1e798 KR |
7316 | && (! USE_GLOBAL_POINTER_OPT |
7317 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
7318 | || g_switch_value < 4 |
7319 | || (temp[0] == 0 && temp[1] == 0) | |
7320 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
7321 | { |
7322 | imm_expr.X_op = O_constant; | |
b9129c6f | 7323 | if (! target_big_endian) |
a5586bdc | 7324 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 7325 | else |
a5586bdc ILT |
7326 | imm_expr.X_add_number = bfd_getb32 (temp); |
7327 | } | |
7328 | else if (length > 4 | |
7329 | && ((temp[0] == 0 && temp[1] == 0) | |
7330 | || (temp[2] == 0 && temp[3] == 0)) | |
7331 | && ((temp[4] == 0 && temp[5] == 0) | |
7332 | || (temp[6] == 0 && temp[7] == 0))) | |
7333 | { | |
7334 | /* The value is simple enough to load with a | |
7335 | couple of instructions. In mips1 mode, set | |
7336 | imm_expr to the high order 32 bits and | |
7337 | offset_expr to the low order 32 bits. | |
7338 | Otherwise, set imm_expr to the entire 64 bit | |
7339 | constant. */ | |
7340 | if (mips_opts.isa < 3) | |
7341 | { | |
7342 | imm_expr.X_op = O_constant; | |
7343 | offset_expr.X_op = O_constant; | |
7344 | if (! target_big_endian) | |
7345 | { | |
7346 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7347 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7348 | } | |
7349 | else | |
7350 | { | |
7351 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7352 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7353 | } | |
7354 | if (offset_expr.X_add_number == 0) | |
7355 | offset_expr.X_op = O_absent; | |
7356 | } | |
7357 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7358 | { | |
7359 | imm_expr.X_op = O_constant; | |
7360 | if (! target_big_endian) | |
7361 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7362 | else | |
7363 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7364 | } | |
7365 | else | |
7366 | { | |
7367 | imm_expr.X_op = O_big; | |
7368 | imm_expr.X_add_number = 4; | |
7369 | if (! target_big_endian) | |
7370 | { | |
7371 | generic_bignum[0] = bfd_getl16 (temp); | |
7372 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7373 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7374 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7375 | } | |
7376 | else | |
7377 | { | |
7378 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7379 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7380 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7381 | generic_bignum[3] = bfd_getb16 (temp); | |
7382 | } | |
7383 | } | |
19ed8960 ILT |
7384 | } |
7385 | else | |
7386 | { | |
0dd2d296 ILT |
7387 | const char *newname; |
7388 | segT new_seg; | |
7389 | ||
19ed8960 ILT |
7390 | /* Switch to the right section. */ |
7391 | seg = now_seg; | |
7392 | subseg = now_subseg; | |
7393 | switch (*args) | |
7394 | { | |
0dd2d296 | 7395 | default: /* unused default case avoids warnings. */ |
19ed8960 | 7396 | case 'L': |
1113140a | 7397 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 7398 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 7399 | newname = ".lit8"; |
0dd2d296 ILT |
7400 | break; |
7401 | case 'F': | |
d2c71068 | 7402 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
7403 | break; |
7404 | case 'l': | |
1dc1e798 KR |
7405 | assert (!USE_GLOBAL_POINTER_OPT |
7406 | || g_switch_value >= 4); | |
0dd2d296 | 7407 | newname = ".lit4"; |
19ed8960 ILT |
7408 | break; |
7409 | } | |
0dd2d296 | 7410 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
7411 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
7412 | bfd_set_section_flags (stdoutput, new_seg, | |
7413 | (SEC_ALLOC | |
7414 | | SEC_LOAD | |
7415 | | SEC_READONLY | |
7416 | | SEC_DATA)); | |
e2e5acfa JW |
7417 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
7418 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7419 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
7420 | record_alignment (new_seg, 4); |
7421 | else | |
7422 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
7423 | if (seg == now_seg) |
7424 | as_bad ("Can't use floating point insn in this section"); | |
7425 | ||
7426 | /* Set the argument to the current address in the | |
6e8dda9c | 7427 | section. */ |
19ed8960 ILT |
7428 | offset_expr.X_op = O_symbol; |
7429 | offset_expr.X_add_symbol = | |
7430 | symbol_new ("L0\001", now_seg, | |
7431 | (valueT) frag_now_fix (), frag_now); | |
7432 | offset_expr.X_add_number = 0; | |
7433 | ||
7434 | /* Put the floating point number into the section. */ | |
604633ae | 7435 | p = frag_more ((int) length); |
19ed8960 ILT |
7436 | memcpy (p, temp, length); |
7437 | ||
7438 | /* Switch back to the original section. */ | |
7439 | subseg_set (seg, subseg); | |
7440 | } | |
7441 | } | |
670a50eb ILT |
7442 | continue; |
7443 | ||
7444 | case 'i': /* 16 bit unsigned immediate */ | |
7445 | case 'j': /* 16 bit signed immediate */ | |
7446 | imm_reloc = BFD_RELOC_LO16; | |
7447 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 7448 | if (c != '\0') |
670a50eb ILT |
7449 | { |
7450 | if (c != 'l') | |
7451 | { | |
5ac34ac3 | 7452 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
7453 | imm_expr.X_add_number = |
7454 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7455 | else if (c == 'h') | |
867a58b3 ILT |
7456 | { |
7457 | imm_reloc = BFD_RELOC_HI16_S; | |
7458 | imm_unmatched_hi = true; | |
7459 | } | |
670a50eb ILT |
7460 | else |
7461 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 7462 | } |
670a50eb | 7463 | } |
670a50eb ILT |
7464 | if (*args == 'i') |
7465 | { | |
344a8d61 | 7466 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7467 | || ((imm_expr.X_add_number < 0 |
7468 | || imm_expr.X_add_number >= 0x10000) | |
7469 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
7470 | { |
7471 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7472 | !strcmp (insn->name, insn[1].name)) | |
7473 | break; | |
9753202d ILT |
7474 | if (imm_expr.X_op != O_constant |
7475 | && imm_expr.X_op != O_big) | |
7476 | insn_error = "absolute expression required"; | |
7477 | else | |
7478 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 7479 | } |
670a50eb ILT |
7480 | } |
7481 | else | |
7482 | { | |
d9aba805 ILT |
7483 | int more; |
7484 | offsetT max; | |
7485 | ||
be22008b ILT |
7486 | /* The upper bound should be 0x8000, but |
7487 | unfortunately the MIPS assembler accepts numbers | |
7488 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
7489 | we want to be compatible. We only permit this |
7490 | extended range for an instruction which does not | |
7491 | provide any further alternates, since those | |
7492 | alternates may handle other cases. People should | |
7493 | use the numbers they mean, rather than relying on | |
7494 | a mysterious sign extension. */ | |
7495 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7496 | strcmp (insn->name, insn[1].name) == 0); | |
7497 | if (more) | |
7498 | max = 0x8000; | |
7499 | else | |
7500 | max = 0x10000; | |
344a8d61 | 7501 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7502 | || ((imm_expr.X_add_number < -0x8000 |
7503 | || imm_expr.X_add_number >= max) | |
7504 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
7505 | || (more |
7506 | && imm_expr.X_add_number < 0 | |
3c83da8a | 7507 | && mips_opts.isa >= 3 |
d8a1c247 KR |
7508 | && imm_expr.X_unsigned |
7509 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 7510 | { |
d9aba805 | 7511 | if (more) |
99c24539 | 7512 | break; |
9753202d ILT |
7513 | if (imm_expr.X_op != O_constant |
7514 | && imm_expr.X_op != O_big) | |
7515 | insn_error = "absolute expression required"; | |
7516 | else | |
7517 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 7518 | } |
3d3c5039 | 7519 | } |
670a50eb ILT |
7520 | s = expr_end; |
7521 | continue; | |
7522 | ||
7523 | case 'o': /* 16 bit offset */ | |
7524 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
7525 | |
7526 | /* If this value won't fit into a 16 bit offset, then go | |
7527 | find a macro that will generate the 32 bit offset | |
7528 | code pattern. As a special hack, we accept the | |
7529 | difference of two local symbols as a constant. This | |
7530 | is required to suppose embedded PIC switches, which | |
7531 | use an instruction which looks like | |
7532 | lw $4,$L12-$LS12($4) | |
7533 | The problem with handling this in a more general | |
7534 | fashion is that the macro function doesn't expect to | |
7535 | see anything which can be handled in a single | |
7536 | constant instruction. */ | |
6f0b87c3 SS |
7537 | if (c == 0 |
7538 | && (offset_expr.X_op != O_constant | |
7539 | || offset_expr.X_add_number >= 0x8000 | |
7540 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
7541 | && (mips_pic != EMBEDDED_PIC |
7542 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
7543 | || now_seg != text_section |
7544 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7545 | != text_section))) | |
670a50eb | 7546 | break; |
3d3c5039 | 7547 | |
670a50eb ILT |
7548 | offset_reloc = BFD_RELOC_LO16; |
7549 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
7550 | { |
7551 | assert (offset_expr.X_op == O_constant); | |
7552 | offset_expr.X_add_number = | |
7553 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7554 | } | |
cc5703cd ILT |
7555 | s = expr_end; |
7556 | continue; | |
7557 | ||
7558 | case 'p': /* pc relative offset */ | |
7559 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7560 | my_getExpression (&offset_expr, s); | |
7561 | s = expr_end; | |
7562 | continue; | |
7563 | ||
7564 | case 'u': /* upper 16 bits */ | |
7565 | c = my_getSmallExpression (&imm_expr, s); | |
7566 | if (imm_expr.X_op == O_constant | |
7567 | && (imm_expr.X_add_number < 0 | |
7568 | || imm_expr.X_add_number >= 0x10000)) | |
7569 | as_bad ("lui expression not in range 0..65535"); | |
7570 | imm_reloc = BFD_RELOC_LO16; | |
7571 | if (c) | |
7572 | { | |
7573 | if (c != 'l') | |
7574 | { | |
7575 | if (imm_expr.X_op == O_constant) | |
7576 | imm_expr.X_add_number = | |
7577 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7578 | else if (c == 'h') | |
7579 | { | |
7580 | imm_reloc = BFD_RELOC_HI16_S; | |
7581 | imm_unmatched_hi = true; | |
7582 | } | |
7583 | else | |
7584 | imm_reloc = BFD_RELOC_HI16; | |
7585 | } | |
7586 | } | |
7587 | s = expr_end; | |
7588 | continue; | |
7589 | ||
7590 | case 'a': /* 26 bit address */ | |
7591 | my_getExpression (&offset_expr, s); | |
7592 | s = expr_end; | |
7593 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7594 | continue; | |
7595 | ||
7596 | case 'N': /* 3 bit branch condition code */ | |
7597 | case 'M': /* 3 bit compare condition code */ | |
7598 | if (strncmp (s, "$fcc", 4) != 0) | |
7599 | break; | |
7600 | s += 4; | |
7601 | regno = 0; | |
7602 | do | |
7603 | { | |
7604 | regno *= 10; | |
7605 | regno += *s - '0'; | |
7606 | ++s; | |
7607 | } | |
7608 | while (isdigit (*s)); | |
7609 | if (regno > 7) | |
7610 | as_bad ("invalid condition code register $fcc%d", regno); | |
7611 | if (*args == 'N') | |
7612 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7613 | else | |
7614 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7615 | continue; | |
7616 | ||
b3ed1af3 KR |
7617 | /* start-sanitize-vr5400 */ |
7618 | case 'e': /* must be at least one digit */ | |
7619 | my_getExpression (&imm_expr, s); | |
7620 | check_absolute_expr (ip, &imm_expr); | |
7621 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECBYTE) | |
7622 | { | |
7623 | as_bad ("bad byte vector index (%ld)", | |
7624 | (long) imm_expr.X_add_number); | |
7625 | imm_expr.X_add_number = imm_expr.X_add_number; | |
7626 | } | |
7627 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
7628 | imm_expr.X_op = O_absent; | |
7629 | s = expr_end; | |
7630 | continue; | |
7631 | ||
7632 | case '%': | |
7633 | my_getExpression (&imm_expr, s); | |
7634 | check_absolute_expr (ip, &imm_expr); | |
7635 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECALIGN) | |
7636 | { | |
7637 | as_bad ("bad byte vector index (%ld)", | |
7638 | (long) imm_expr.X_add_number); | |
7639 | imm_expr.X_add_number = imm_expr.X_add_number; | |
7640 | } | |
7641 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
7642 | imm_expr.X_op = O_absent; | |
7643 | s = expr_end; | |
7644 | continue; | |
7645 | ||
7646 | /* end-sanitize-vr5400 */ | |
cc5703cd | 7647 | default: |
b3ed1af3 | 7648 | as_bad ("bad char = '%c'\n", *args); |
cc5703cd ILT |
7649 | internalError (); |
7650 | } | |
7651 | break; | |
7652 | } | |
7653 | /* Args don't match. */ | |
7654 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7655 | !strcmp (insn->name, insn[1].name)) | |
7656 | { | |
7657 | ++insn; | |
7658 | s = argsStart; | |
7659 | continue; | |
7660 | } | |
7661 | insn_error = "illegal operands"; | |
7662 | return; | |
7663 | } | |
7664 | } | |
7665 | ||
7666 | /* This routine assembles an instruction into its binary format when | |
7667 | assembling for the mips16. As a side effect, it sets one of the | |
7668 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
7669 | relocation to do if one of the operands is an address expression. |
7670 | It also sets mips16_small and mips16_ext if the user explicitly | |
7671 | requested a small or extended instruction. */ | |
cc5703cd ILT |
7672 | |
7673 | static void | |
7674 | mips16_ip (str, ip) | |
7675 | char *str; | |
7676 | struct mips_cl_insn *ip; | |
7677 | { | |
7678 | char *s; | |
cc5703cd ILT |
7679 | const char *args; |
7680 | struct mips_opcode *insn; | |
7681 | char *argsstart; | |
7682 | unsigned int regno; | |
7683 | unsigned int lastregno = 0; | |
7684 | char *s_reset; | |
7685 | ||
7686 | insn_error = NULL; | |
7687 | ||
8728fa92 ILT |
7688 | mips16_small = false; |
7689 | mips16_ext = false; | |
cc5703cd ILT |
7690 | |
7691 | for (s = str; islower (*s); ++s) | |
7692 | ; | |
7693 | switch (*s) | |
7694 | { | |
7695 | case '\0': | |
7696 | break; | |
7697 | ||
7698 | case ' ': | |
7699 | *s++ = '\0'; | |
7700 | break; | |
7701 | ||
7702 | case '.': | |
7703 | if (s[1] == 't' && s[2] == ' ') | |
7704 | { | |
7705 | *s = '\0'; | |
8728fa92 | 7706 | mips16_small = true; |
cc5703cd ILT |
7707 | s += 3; |
7708 | break; | |
7709 | } | |
7710 | else if (s[1] == 'e' && s[2] == ' ') | |
7711 | { | |
7712 | *s = '\0'; | |
8728fa92 | 7713 | mips16_ext = true; |
cc5703cd ILT |
7714 | s += 3; |
7715 | break; | |
7716 | } | |
7717 | /* Fall through. */ | |
7718 | default: | |
7719 | insn_error = "unknown opcode"; | |
7720 | return; | |
7721 | } | |
7722 | ||
3c83da8a | 7723 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
7724 | mips16_small = true; |
7725 | ||
cc5703cd ILT |
7726 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
7727 | { | |
7728 | insn_error = "unrecognized opcode"; | |
7729 | return; | |
7730 | } | |
7731 | ||
7732 | argsstart = s; | |
7733 | for (;;) | |
7734 | { | |
7735 | assert (strcmp (insn->name, str) == 0); | |
7736 | ||
7737 | ip->insn_mo = insn; | |
7738 | ip->insn_opcode = insn->match; | |
7739 | ip->use_extend = false; | |
7740 | imm_expr.X_op = O_absent; | |
7741 | imm_reloc = BFD_RELOC_UNUSED; | |
7742 | offset_expr.X_op = O_absent; | |
7743 | offset_reloc = BFD_RELOC_UNUSED; | |
7744 | for (args = insn->args; 1; ++args) | |
7745 | { | |
7746 | int c; | |
7747 | ||
7748 | if (*s == ' ') | |
7749 | ++s; | |
7750 | ||
7751 | /* In this switch statement we call break if we did not find | |
7752 | a match, continue if we did find a match, or return if we | |
7753 | are done. */ | |
7754 | ||
7755 | c = *args; | |
7756 | switch (c) | |
7757 | { | |
7758 | case '\0': | |
7759 | if (*s == '\0') | |
7760 | { | |
7761 | /* Stuff the immediate value in now, if we can. */ | |
7762 | if (imm_expr.X_op == O_constant | |
7763 | && imm_reloc > BFD_RELOC_UNUSED | |
7764 | && insn->pinfo != INSN_MACRO) | |
7765 | { | |
15e69f98 ILT |
7766 | mips16_immed ((char *) NULL, 0, |
7767 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
7768 | imm_expr.X_add_number, true, mips16_small, |
7769 | mips16_ext, &ip->insn_opcode, | |
7770 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7771 | imm_expr.X_op = O_absent; |
7772 | imm_reloc = BFD_RELOC_UNUSED; | |
7773 | } | |
7774 | ||
7775 | return; | |
7776 | } | |
7777 | break; | |
7778 | ||
7779 | case ',': | |
7780 | if (*s++ == c) | |
7781 | continue; | |
7782 | s--; | |
7783 | switch (*++args) | |
7784 | { | |
7785 | case 'v': | |
7786 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7787 | continue; | |
7788 | case 'w': | |
7789 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7790 | continue; | |
7791 | } | |
7792 | break; | |
7793 | ||
7794 | case '(': | |
7795 | case ')': | |
7796 | if (*s++ == c) | |
7797 | continue; | |
7798 | break; | |
7799 | ||
7800 | case 'v': | |
7801 | case 'w': | |
7802 | if (s[0] != '$') | |
7803 | { | |
7804 | if (c == 'v') | |
7805 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7806 | else | |
7807 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7808 | ++args; | |
7809 | continue; | |
7810 | } | |
7811 | /* Fall through. */ | |
7812 | case 'x': | |
7813 | case 'y': | |
7814 | case 'z': | |
7815 | case 'Z': | |
7816 | case '0': | |
7817 | case 'S': | |
7818 | case 'R': | |
7819 | case 'X': | |
7820 | case 'Y': | |
7821 | if (s[0] != '$') | |
7822 | break; | |
7823 | s_reset = s; | |
7824 | if (isdigit (s[1])) | |
7825 | { | |
7826 | ++s; | |
7827 | regno = 0; | |
7828 | do | |
7829 | { | |
7830 | regno *= 10; | |
7831 | regno += *s - '0'; | |
7832 | ++s; | |
7833 | } | |
7834 | while (isdigit (*s)); | |
7835 | if (regno > 31) | |
7836 | { | |
7837 | as_bad ("invalid register number (%d)", regno); | |
7838 | regno = 2; | |
7839 | } | |
7840 | } | |
7841 | else | |
7842 | { | |
7843 | if (s[1] == 'f' && s[2] == 'p') | |
7844 | { | |
7845 | s += 3; | |
7846 | regno = FP; | |
7847 | } | |
7848 | else if (s[1] == 's' && s[2] == 'p') | |
7849 | { | |
7850 | s += 3; | |
7851 | regno = SP; | |
7852 | } | |
7853 | else if (s[1] == 'g' && s[2] == 'p') | |
7854 | { | |
7855 | s += 3; | |
7856 | regno = GP; | |
7857 | } | |
7858 | else if (s[1] == 'a' && s[2] == 't') | |
7859 | { | |
7860 | s += 3; | |
7861 | regno = AT; | |
7862 | } | |
7863 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7864 | { | |
7865 | s += 4; | |
7866 | regno = KT0; | |
7867 | } | |
7868 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7869 | { | |
7870 | s += 4; | |
7871 | regno = KT1; | |
7872 | } | |
7873 | else | |
7874 | break; | |
7875 | } | |
7876 | ||
7877 | if (*s == ' ') | |
7878 | ++s; | |
7879 | if (args[1] != *s) | |
7880 | { | |
7881 | if (c == 'v' || c == 'w') | |
7882 | { | |
7883 | regno = mips16_to_32_reg_map[lastregno]; | |
7884 | s = s_reset; | |
7885 | args++; | |
7886 | } | |
7887 | } | |
7888 | ||
7889 | switch (c) | |
7890 | { | |
7891 | case 'x': | |
7892 | case 'y': | |
7893 | case 'z': | |
7894 | case 'v': | |
7895 | case 'w': | |
7896 | case 'Z': | |
7897 | regno = mips32_to_16_reg_map[regno]; | |
7898 | break; | |
7899 | ||
7900 | case '0': | |
7901 | if (regno != 0) | |
7902 | regno = ILLEGAL_REG; | |
7903 | break; | |
7904 | ||
7905 | case 'S': | |
7906 | if (regno != SP) | |
7907 | regno = ILLEGAL_REG; | |
7908 | break; | |
7909 | ||
7910 | case 'R': | |
7911 | if (regno != RA) | |
7912 | regno = ILLEGAL_REG; | |
7913 | break; | |
7914 | ||
7915 | case 'X': | |
7916 | case 'Y': | |
3c83da8a | 7917 | if (regno == AT && ! mips_opts.noat) |
cc5703cd ILT |
7918 | as_warn ("used $at without \".set noat\""); |
7919 | break; | |
7920 | ||
7921 | default: | |
7922 | internalError (); | |
7923 | } | |
7924 | ||
7925 | if (regno == ILLEGAL_REG) | |
7926 | break; | |
7927 | ||
7928 | switch (c) | |
7929 | { | |
7930 | case 'x': | |
7931 | case 'v': | |
7932 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7933 | break; | |
7934 | case 'y': | |
7935 | case 'w': | |
7936 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7937 | break; | |
7938 | case 'z': | |
7939 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7940 | break; | |
7941 | case 'Z': | |
7942 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7943 | case '0': | |
7944 | case 'S': | |
7945 | case 'R': | |
7946 | break; | |
7947 | case 'X': | |
7948 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7949 | break; | |
7950 | case 'Y': | |
7951 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7952 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7953 | break; | |
7954 | default: | |
7955 | internalError (); | |
7956 | } | |
7957 | ||
7958 | lastregno = regno; | |
7959 | continue; | |
7960 | ||
7961 | case 'P': | |
7962 | if (strncmp (s, "$pc", 3) == 0) | |
7963 | { | |
7964 | s += 3; | |
7965 | continue; | |
7966 | } | |
7967 | break; | |
7968 | ||
7969 | case '<': | |
7970 | case '>': | |
7971 | case '[': | |
7972 | case ']': | |
7973 | case '4': | |
7974 | case '5': | |
7975 | case 'H': | |
7976 | case 'W': | |
7977 | case 'D': | |
7978 | case 'j': | |
7979 | case '8': | |
7980 | case 'V': | |
7981 | case 'C': | |
7982 | case 'U': | |
7983 | case 'k': | |
7984 | case 'K': | |
16262668 ILT |
7985 | if (s[0] == '%' |
7986 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
7987 | { | |
7988 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
7989 | and generate the appropriate reloc. If the text | |
7990 | inside %gprel is not a symbol name with an | |
7991 | optional offset, then we generate a normal reloc | |
7992 | and will probably fail later. */ | |
7993 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
7994 | if (imm_expr.X_op == O_symbol) | |
7995 | { | |
7996 | mips16_ext = true; | |
7997 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
7998 | s = expr_end; | |
7999 | ip->use_extend = true; | |
8000 | ip->extend = 0; | |
8001 | continue; | |
8002 | } | |
8003 | } | |
8004 | else | |
8005 | { | |
8006 | /* Just pick up a normal expression. */ | |
8007 | my_getExpression (&imm_expr, s); | |
8008 | } | |
8009 | ||
ebf28372 ILT |
8010 | if (imm_expr.X_op == O_register) |
8011 | { | |
8012 | /* What we thought was an expression turned out to | |
8013 | be a register. */ | |
8014 | ||
8015 | if (s[0] == '(' && args[1] == '(') | |
8016 | { | |
8017 | /* It looks like the expression was omitted | |
8018 | before a register indirection, which means | |
8019 | that the expression is implicitly zero. We | |
8020 | still set up imm_expr, so that we handle | |
8021 | explicit extensions correctly. */ | |
8022 | imm_expr.X_op = O_constant; | |
8023 | imm_expr.X_add_number = 0; | |
8024 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8025 | continue; | |
8026 | } | |
8027 | ||
8028 | break; | |
8029 | } | |
8030 | ||
cc5703cd ILT |
8031 | /* We need to relax this instruction. */ |
8032 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8033 | s = expr_end; | |
8034 | continue; | |
8035 | ||
8036 | case 'p': | |
8037 | case 'q': | |
8038 | case 'A': | |
8039 | case 'B': | |
8040 | case 'E': | |
8041 | /* We use offset_reloc rather than imm_reloc for the PC | |
8042 | relative operands. This lets macros with both | |
8043 | immediate and address operands work correctly. */ | |
670a50eb | 8044 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
8045 | |
8046 | if (offset_expr.X_op == O_register) | |
8047 | break; | |
8048 | ||
cc5703cd ILT |
8049 | /* We need to relax this instruction. */ |
8050 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
8051 | s = expr_end; |
8052 | continue; | |
8053 | ||
cc5703cd ILT |
8054 | case '6': /* break code */ |
8055 | my_getExpression (&imm_expr, s); | |
8056 | check_absolute_expr (ip, &imm_expr); | |
8057 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 8058 | { |
cc5703cd ILT |
8059 | as_warn ("Invalid value for `%s' (%lu)", |
8060 | ip->insn_mo->name, | |
8061 | (unsigned long) imm_expr.X_add_number); | |
8062 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 8063 | } |
cc5703cd ILT |
8064 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
8065 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
8066 | s = expr_end; |
8067 | continue; | |
3d3c5039 | 8068 | |
670a50eb ILT |
8069 | case 'a': /* 26 bit address */ |
8070 | my_getExpression (&offset_expr, s); | |
8071 | s = expr_end; | |
cc5703cd ILT |
8072 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
8073 | ip->insn_opcode <<= 16; | |
670a50eb | 8074 | continue; |
3d3c5039 | 8075 | |
cc5703cd ILT |
8076 | case 'l': /* register list for entry macro */ |
8077 | case 'L': /* register list for exit macro */ | |
8078 | { | |
8079 | int mask; | |
8080 | ||
8081 | if (c == 'l') | |
8082 | mask = 0; | |
8083 | else | |
8084 | mask = 7 << 3; | |
8085 | while (*s != '\0') | |
8086 | { | |
c9167640 | 8087 | int freg, reg1, reg2; |
cc5703cd ILT |
8088 | |
8089 | while (*s == ' ' || *s == ',') | |
8090 | ++s; | |
8091 | if (*s != '$') | |
8092 | { | |
8093 | as_bad ("can't parse register list"); | |
8094 | break; | |
8095 | } | |
8096 | ++s; | |
c9167640 ILT |
8097 | if (*s != 'f') |
8098 | freg = 0; | |
8099 | else | |
8100 | { | |
8101 | freg = 1; | |
8102 | ++s; | |
8103 | } | |
cc5703cd ILT |
8104 | reg1 = 0; |
8105 | while (isdigit (*s)) | |
8106 | { | |
8107 | reg1 *= 10; | |
8108 | reg1 += *s - '0'; | |
8109 | ++s; | |
8110 | } | |
8111 | if (*s == ' ') | |
8112 | ++s; | |
8113 | if (*s != '-') | |
8114 | reg2 = reg1; | |
8115 | else | |
8116 | { | |
8117 | ++s; | |
8118 | if (*s != '$') | |
8119 | break; | |
8120 | ++s; | |
c9167640 ILT |
8121 | if (freg) |
8122 | { | |
8123 | if (*s == 'f') | |
8124 | ++s; | |
8125 | else | |
8126 | { | |
8127 | as_bad ("invalid register list"); | |
8128 | break; | |
8129 | } | |
8130 | } | |
cc5703cd ILT |
8131 | reg2 = 0; |
8132 | while (isdigit (*s)) | |
8133 | { | |
8134 | reg2 *= 10; | |
8135 | reg2 += *s - '0'; | |
8136 | ++s; | |
8137 | } | |
8138 | } | |
c9167640 ILT |
8139 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
8140 | { | |
8141 | mask &= ~ (7 << 3); | |
8142 | mask |= 5 << 3; | |
8143 | } | |
8144 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8145 | { | |
8146 | mask &= ~ (7 << 3); | |
8147 | mask |= 6 << 3; | |
8148 | } | |
8149 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
8150 | mask |= (reg2 - 3) << 3; |
8151 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8152 | mask |= (reg2 - 15) << 1; | |
8153 | else if (reg1 == 31 && reg2 == 31) | |
8154 | mask |= 1; | |
8155 | else | |
c9167640 ILT |
8156 | { |
8157 | as_bad ("invalid register list"); | |
8158 | break; | |
8159 | } | |
cc5703cd | 8160 | } |
c9167640 ILT |
8161 | /* The mask is filled in in the opcode table for the |
8162 | benefit of the disassembler. We remove it before | |
8163 | applying the actual mask. */ | |
8164 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
8165 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
8166 | } | |
8167 | continue; | |
d8a1c247 | 8168 | |
56bb6eee ILT |
8169 | case 'e': /* extend code */ |
8170 | my_getExpression (&imm_expr, s); | |
8171 | check_absolute_expr (ip, &imm_expr); | |
8172 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8173 | { | |
8174 | as_warn ("Invalid value for `%s' (%lu)", | |
8175 | ip->insn_mo->name, | |
8176 | (unsigned long) imm_expr.X_add_number); | |
8177 | imm_expr.X_add_number &= 0x7ff; | |
8178 | } | |
8179 | ip->insn_opcode |= imm_expr.X_add_number; | |
8180 | imm_expr.X_op = O_absent; | |
8181 | s = expr_end; | |
8182 | continue; | |
8183 | ||
3d3c5039 | 8184 | default: |
670a50eb | 8185 | internalError (); |
3d3c5039 | 8186 | } |
670a50eb | 8187 | break; |
3d3c5039 | 8188 | } |
cc5703cd | 8189 | |
670a50eb | 8190 | /* Args don't match. */ |
cc5703cd ILT |
8191 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
8192 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
8193 | { |
8194 | ++insn; | |
cc5703cd | 8195 | s = argsstart; |
670a50eb | 8196 | continue; |
3d3c5039 | 8197 | } |
cc5703cd | 8198 | |
9753202d | 8199 | insn_error = "illegal operands"; |
cc5703cd | 8200 | |
670a50eb | 8201 | return; |
3d3c5039 ILT |
8202 | } |
8203 | } | |
8204 | ||
cc5703cd ILT |
8205 | /* This structure holds information we know about a mips16 immediate |
8206 | argument type. */ | |
8207 | ||
8208 | struct mips16_immed_operand | |
8209 | { | |
8210 | /* The type code used in the argument string in the opcode table. */ | |
8211 | int type; | |
8212 | /* The number of bits in the short form of the opcode. */ | |
8213 | int nbits; | |
8214 | /* The number of bits in the extended form of the opcode. */ | |
8215 | int extbits; | |
8216 | /* The amount by which the short form is shifted when it is used; | |
8217 | for example, the sw instruction has a shift count of 2. */ | |
8218 | int shift; | |
8219 | /* The amount by which the short form is shifted when it is stored | |
8220 | into the instruction code. */ | |
8221 | int op_shift; | |
8222 | /* Non-zero if the short form is unsigned. */ | |
8223 | int unsp; | |
8224 | /* Non-zero if the extended form is unsigned. */ | |
8225 | int extu; | |
8226 | /* Non-zero if the value is PC relative. */ | |
8227 | int pcrel; | |
8228 | }; | |
8229 | ||
8230 | /* The mips16 immediate operand types. */ | |
8231 | ||
8232 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8233 | { | |
8234 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8235 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8236 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8237 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8238 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8239 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8240 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8241 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8242 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8243 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8244 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8245 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8246 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8247 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8248 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8249 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8250 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8251 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8252 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8253 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8254 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8255 | }; | |
8256 | ||
8257 | #define MIPS16_NUM_IMMED \ | |
8258 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8259 | ||
8260 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8261 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8262 | whether an extended value is needed; if one is needed, it sets | |
8263 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8264 | If SMALL is true, an unextended opcode was explicitly requested. | |
8265 | If EXT is true, an extended opcode was explicitly requested. If | |
8266 | WARN is true, warn if EXT does not match reality. */ | |
8267 | ||
8268 | static void | |
15e69f98 ILT |
8269 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
8270 | extend) | |
8271 | char *file; | |
8272 | unsigned int line; | |
cc5703cd ILT |
8273 | int type; |
8274 | offsetT val; | |
8275 | boolean warn; | |
8276 | boolean small; | |
8277 | boolean ext; | |
8278 | unsigned long *insn; | |
8279 | boolean *use_extend; | |
8280 | unsigned short *extend; | |
8281 | { | |
8282 | register const struct mips16_immed_operand *op; | |
8283 | int mintiny, maxtiny; | |
8284 | boolean needext; | |
8285 | ||
8286 | op = mips16_immed_operands; | |
8287 | while (op->type != type) | |
8288 | { | |
8289 | ++op; | |
8290 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8291 | } | |
8292 | ||
8293 | if (op->unsp) | |
8294 | { | |
8295 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8296 | { | |
8297 | mintiny = 1; | |
8298 | maxtiny = 1 << op->nbits; | |
8299 | } | |
8300 | else | |
8301 | { | |
8302 | mintiny = 0; | |
8303 | maxtiny = (1 << op->nbits) - 1; | |
8304 | } | |
8305 | } | |
8306 | else | |
8307 | { | |
8308 | mintiny = - (1 << (op->nbits - 1)); | |
8309 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8310 | } | |
8311 | ||
8312 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8313 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 8314 | val /= 2; |
cc5703cd ILT |
8315 | |
8316 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8317 | || val < (mintiny << op->shift) | |
8318 | || val > (maxtiny << op->shift)) | |
8319 | needext = true; | |
8320 | else | |
8321 | needext = false; | |
8322 | ||
8323 | if (warn && ext && ! needext) | |
15e69f98 | 8324 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 8325 | if (small && needext) |
15e69f98 | 8326 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
8327 | |
8328 | if (small || (! ext && ! needext)) | |
8329 | { | |
8330 | int insnval; | |
8331 | ||
8332 | *use_extend = false; | |
8333 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8334 | insnval <<= op->op_shift; | |
8335 | *insn |= insnval; | |
8336 | } | |
8337 | else | |
8338 | { | |
8339 | long minext, maxext; | |
8340 | int extval; | |
8341 | ||
8342 | if (op->extu) | |
8343 | { | |
8344 | minext = 0; | |
8345 | maxext = (1 << op->extbits) - 1; | |
8346 | } | |
8347 | else | |
8348 | { | |
8349 | minext = - (1 << (op->extbits - 1)); | |
8350 | maxext = (1 << (op->extbits - 1)) - 1; | |
8351 | } | |
8352 | if (val < minext || val > maxext) | |
15e69f98 ILT |
8353 | as_bad_where (file, line, |
8354 | "operand value out of range for instruction"); | |
cc5703cd ILT |
8355 | |
8356 | *use_extend = true; | |
8357 | if (op->extbits == 16) | |
8358 | { | |
8359 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8360 | val &= 0x1f; | |
8361 | } | |
8362 | else if (op->extbits == 15) | |
8363 | { | |
8364 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8365 | val &= 0xf; | |
8366 | } | |
8367 | else | |
8368 | { | |
8369 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8370 | val = 0; | |
8371 | } | |
8372 | ||
8373 | *extend = (unsigned short) extval; | |
8374 | *insn |= val; | |
8375 | } | |
8376 | } | |
8377 | \f | |
3d3c5039 ILT |
8378 | #define LP '(' |
8379 | #define RP ')' | |
8380 | ||
8381 | static int | |
8382 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
8383 | expressionS *ep; |
8384 | char *str; | |
3d3c5039 | 8385 | { |
670a50eb ILT |
8386 | char *sp; |
8387 | int c = 0; | |
8388 | ||
8389 | if (*str == ' ') | |
8390 | str++; | |
8391 | if (*str == LP | |
8392 | || (*str == '%' && | |
8393 | ((str[1] == 'h' && str[2] == 'i') | |
8394 | || (str[1] == 'H' && str[2] == 'I') | |
8395 | || (str[1] == 'l' && str[2] == 'o')) | |
8396 | && str[3] == LP)) | |
8397 | { | |
8398 | if (*str == LP) | |
8399 | c = 0; | |
8400 | else | |
8401 | { | |
8402 | c = str[1]; | |
8403 | str += 3; | |
8404 | } | |
8405 | ||
8406 | /* | |
8407 | * A small expression may be followed by a base register. | |
8408 | * Scan to the end of this operand, and then back over a possible | |
8409 | * base register. Then scan the small expression up to that | |
8410 | * point. (Based on code in sparc.c...) | |
8411 | */ | |
8412 | for (sp = str; *sp && *sp != ','; sp++) | |
8413 | ; | |
8414 | if (sp - 4 >= str && sp[-1] == RP) | |
8415 | { | |
8416 | if (isdigit (sp[-2])) | |
8417 | { | |
8418 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
8419 | ; | |
8420 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8421 | { | |
8422 | sp--; | |
8423 | goto do_it; | |
3d3c5039 | 8424 | } |
670a50eb ILT |
8425 | } |
8426 | else if (sp - 5 >= str | |
8427 | && sp[-5] == LP | |
8428 | && sp[-4] == '$' | |
8429 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8430 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8431 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8432 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8433 | { | |
8434 | sp -= 5; | |
3d3c5039 | 8435 | do_it: |
670a50eb ILT |
8436 | if (sp == str) |
8437 | { | |
8438 | /* no expression means zero offset */ | |
8439 | if (c) | |
8440 | { | |
8441 | /* %xx(reg) is an error */ | |
5ac34ac3 | 8442 | ep->X_op = O_absent; |
670a50eb | 8443 | expr_end = str - 3; |
3d3c5039 | 8444 | } |
670a50eb ILT |
8445 | else |
8446 | { | |
52aa70b5 | 8447 | ep->X_op = O_constant; |
670a50eb ILT |
8448 | expr_end = sp; |
8449 | } | |
8450 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 8451 | ep->X_op_symbol = NULL; |
670a50eb ILT |
8452 | ep->X_add_number = 0; |
8453 | } | |
8454 | else | |
8455 | { | |
8456 | *sp = '\0'; | |
8457 | my_getExpression (ep, str); | |
8458 | *sp = LP; | |
3d3c5039 | 8459 | } |
670a50eb | 8460 | return c; |
3d3c5039 ILT |
8461 | } |
8462 | } | |
8463 | } | |
670a50eb ILT |
8464 | my_getExpression (ep, str); |
8465 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
8466 | } |
8467 | ||
8468 | static void | |
8469 | my_getExpression (ep, str) | |
670a50eb ILT |
8470 | expressionS *ep; |
8471 | char *str; | |
3d3c5039 | 8472 | { |
670a50eb | 8473 | char *save_in; |
670a50eb ILT |
8474 | |
8475 | save_in = input_line_pointer; | |
8476 | input_line_pointer = str; | |
5ac34ac3 | 8477 | expression (ep); |
670a50eb ILT |
8478 | expr_end = input_line_pointer; |
8479 | input_line_pointer = save_in; | |
eb17f56c ILT |
8480 | |
8481 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8482 | then we bump the value of the symbol by 1 since that is how other | |
8483 | text symbols are handled. We don't bother to handle complex | |
8484 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 8485 | if (mips_opts.mips16 |
eb17f56c ILT |
8486 | && ep->X_op == O_symbol |
8487 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8488 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
8489 | && ep->X_add_symbol->sy_frag == frag_now | |
8490 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
8491 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
8492 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
8493 | } |
8494 | ||
becfe05e ILT |
8495 | /* Turn a string in input_line_pointer into a floating point constant |
8496 | of type type, and store the appropriate bytes in *litP. The number | |
8497 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
8498 | returned, or NULL on OK. */ | |
8499 | ||
3d3c5039 | 8500 | char * |
670a50eb | 8501 | md_atof (type, litP, sizeP) |
becfe05e | 8502 | int type; |
3d3c5039 ILT |
8503 | char *litP; |
8504 | int *sizeP; | |
8505 | { | |
becfe05e ILT |
8506 | int prec; |
8507 | LITTLENUM_TYPE words[4]; | |
8508 | char *t; | |
8509 | int i; | |
8510 | ||
8511 | switch (type) | |
8512 | { | |
8513 | case 'f': | |
8514 | prec = 2; | |
8515 | break; | |
8516 | ||
8517 | case 'd': | |
8518 | prec = 4; | |
8519 | break; | |
8520 | ||
8521 | default: | |
8522 | *sizeP = 0; | |
8523 | return "bad call to md_atof"; | |
8524 | } | |
8525 | ||
8526 | t = atof_ieee (input_line_pointer, type, words); | |
8527 | if (t) | |
8528 | input_line_pointer = t; | |
8529 | ||
8530 | *sizeP = prec * 2; | |
8531 | ||
b9129c6f | 8532 | if (! target_big_endian) |
becfe05e ILT |
8533 | { |
8534 | for (i = prec - 1; i >= 0; i--) | |
8535 | { | |
8536 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8537 | litP += 2; | |
8538 | } | |
8539 | } | |
8540 | else | |
8541 | { | |
8542 | for (i = 0; i < prec; i++) | |
8543 | { | |
8544 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8545 | litP += 2; | |
8546 | } | |
8547 | } | |
8548 | ||
670a50eb | 8549 | return NULL; |
3d3c5039 ILT |
8550 | } |
8551 | ||
8552 | void | |
8553 | md_number_to_chars (buf, val, n) | |
8554 | char *buf; | |
918692a5 | 8555 | valueT val; |
3d3c5039 ILT |
8556 | int n; |
8557 | { | |
b9129c6f ILT |
8558 | if (target_big_endian) |
8559 | number_to_chars_bigendian (buf, val, n); | |
8560 | else | |
8561 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 8562 | } |
f3d817d8 | 8563 | \f |
e8d4d475 | 8564 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 8565 | |
f3d817d8 DM |
8566 | struct option md_longopts[] = { |
8567 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8568 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8569 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8570 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8571 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8572 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8573 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
8574 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
8575 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8576 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 8577 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 8578 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 8579 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 8580 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
8581 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8582 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 8583 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
8584 | {"break", no_argument, NULL, OPTION_BREAK}, |
8585 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 8586 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 8587 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 8588 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 8589 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 8590 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 8591 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 8592 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 8593 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
8594 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
8595 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8596 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8597 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
8598 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
8599 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8600 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8601 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 8602 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 8603 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 8604 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 8605 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 8606 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
8607 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
8608 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
8609 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
8610 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 8611 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
8612 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
8613 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
8614 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
8615 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
4e96260f JL |
8616 | |
8617 | /* start-sanitize-tx19 */ | |
8618 | {"m1900", no_argument, NULL, OPTION_M3900}, | |
8619 | {"no-m1900", no_argument, NULL, OPTION_NO_M3900}, | |
8620 | /* end-sanitize-tx19 */ | |
f3d817d8 | 8621 | |
aa2e0460 KR |
8622 | /* start-sanitize-vr5400 */ |
8623 | #define OPTION_M5400 (OPTION_MD_BASE + 28) | |
8624 | {"m5400", no_argument, NULL, OPTION_M5400}, | |
8625 | #define OPTION_NO_M5400 (OPTION_MD_BASE + 29) | |
8626 | {"no-m5400", no_argument, NULL, OPTION_NO_M5400}, | |
8627 | ||
8628 | /* end-sanitize-vr5400 */ | |
42444087 GRK |
8629 | /* start-sanitize-tx49 */ |
8630 | #define OPTION_M4900 (OPTION_MD_BASE + 30) | |
8631 | {"m4900", no_argument, NULL, OPTION_M4900}, | |
8632 | #define OPTION_NO_M4900 (OPTION_MD_BASE + 31) | |
8633 | {"no-m4900", no_argument, NULL, OPTION_NO_M4900}, | |
8634 | ||
8635 | /* end-sanitize-tx49 */ | |
d8a1c247 | 8636 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 8637 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 8638 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
8639 | #define OPTION_32 (OPTION_MD_BASE + 20) |
8640 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 8641 | #ifdef OBJ_ELF |
f3d817d8 | 8642 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 8643 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 8644 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 8645 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
8646 | {"32", no_argument, NULL, OPTION_32}, |
8647 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
8648 | #endif |
8649 | ||
8650 | {NULL, no_argument, NULL, 0} | |
8651 | }; | |
8652 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
8653 | |
8654 | int | |
f3d817d8 DM |
8655 | md_parse_option (c, arg) |
8656 | int c; | |
8657 | char *arg; | |
3d3c5039 | 8658 | { |
f3d817d8 | 8659 | switch (c) |
670a50eb | 8660 | { |
f3d817d8 DM |
8661 | case OPTION_TRAP: |
8662 | mips_trap = 1; | |
8663 | break; | |
670a50eb | 8664 | |
f3d817d8 DM |
8665 | case OPTION_BREAK: |
8666 | mips_trap = 0; | |
8667 | break; | |
8668 | ||
e8d4d475 | 8669 | case OPTION_EB: |
1dc1e798 | 8670 | target_big_endian = 1; |
e8d4d475 | 8671 | break; |
04cb3372 | 8672 | |
e8d4d475 | 8673 | case OPTION_EL: |
1dc1e798 | 8674 | target_big_endian = 0; |
f3d817d8 | 8675 | break; |
670a50eb | 8676 | |
f3d817d8 DM |
8677 | case 'O': |
8678 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
8679 | mips_optimize = 1; |
8680 | else | |
8681 | mips_optimize = 2; | |
f3d817d8 | 8682 | break; |
0aa07269 | 8683 | |
f3d817d8 | 8684 | case 'g': |
22ba90ce ILT |
8685 | if (arg == NULL) |
8686 | mips_debug = 2; | |
8687 | else | |
8688 | mips_debug = atoi (arg); | |
8689 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8690 | optimizations which limit full symbolic debugging. We take | |
8691 | that to be equivalent to -O0. */ | |
8692 | if (mips_debug == 2) | |
05874c2e | 8693 | mips_optimize = 1; |
f3d817d8 | 8694 | break; |
4e95866e | 8695 | |
f3d817d8 | 8696 | case OPTION_MIPS1: |
3c83da8a | 8697 | mips_opts.isa = 1; |
f3d817d8 | 8698 | break; |
8358c818 | 8699 | |
f3d817d8 | 8700 | case OPTION_MIPS2: |
3c83da8a | 8701 | mips_opts.isa = 2; |
f3d817d8 | 8702 | break; |
8358c818 | 8703 | |
f3d817d8 | 8704 | case OPTION_MIPS3: |
3c83da8a | 8705 | mips_opts.isa = 3; |
f3d817d8 | 8706 | break; |
8358c818 | 8707 | |
d8a1c247 | 8708 | case OPTION_MIPS4: |
3c83da8a | 8709 | mips_opts.isa = 4; |
d8a1c247 KR |
8710 | break; |
8711 | ||
f3d817d8 DM |
8712 | case OPTION_MCPU: |
8713 | { | |
8714 | char *p; | |
8715 | ||
8716 | /* Identify the processor type */ | |
8717 | p = arg; | |
8718 | if (strcmp (p, "default") == 0 | |
8719 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 8720 | mips_cpu = -1; |
f3d817d8 DM |
8721 | else |
8722 | { | |
c625fc23 JSC |
8723 | int sv = 0; |
8724 | ||
8725 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8726 | processor. */ | |
8727 | if (*p == 'v' || *p == 'V') | |
8728 | { | |
8729 | sv = 1; | |
8730 | p++; | |
8731 | } | |
8732 | ||
f3d817d8 DM |
8733 | if (*p == 'r' || *p == 'R') |
8734 | p++; | |
8358c818 | 8735 | |
4bb0cc41 | 8736 | mips_cpu = -1; |
f3d817d8 DM |
8737 | switch (*p) |
8738 | { | |
d8a1c247 KR |
8739 | case '1': |
8740 | if (strcmp (p, "10000") == 0 | |
8741 | || strcmp (p, "10k") == 0 | |
8742 | || strcmp (p, "10K") == 0) | |
8743 | mips_cpu = 10000; | |
4e96260f JL |
8744 | /* start-sanitize-tx19 */ |
8745 | else if (strcmp (p, "1900") == 0) | |
8746 | mips_cpu = 3900; | |
8747 | /* end-sanitize-tx19 */ | |
d8a1c247 KR |
8748 | break; |
8749 | ||
f3d817d8 DM |
8750 | case '2': |
8751 | if (strcmp (p, "2000") == 0 | |
8752 | || strcmp (p, "2k") == 0 | |
8753 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 8754 | mips_cpu = 2000; |
f3d817d8 | 8755 | break; |
8358c818 | 8756 | |
f3d817d8 DM |
8757 | case '3': |
8758 | if (strcmp (p, "3000") == 0 | |
8759 | || strcmp (p, "3k") == 0 | |
8760 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 8761 | mips_cpu = 3000; |
5c6f5923 GRK |
8762 | else if (strcmp (p, "3900") == 0) |
8763 | mips_cpu = 3900; | |
f3d817d8 | 8764 | break; |
8358c818 | 8765 | |
f3d817d8 DM |
8766 | case '4': |
8767 | if (strcmp (p, "4000") == 0 | |
8768 | || strcmp (p, "4k") == 0 | |
8c63448a | 8769 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 8770 | mips_cpu = 4000; |
c625fc23 | 8771 | else if (strcmp (p, "4100") == 0) |
c625fc23 | 8772 | mips_cpu = 4100; |
c625fc23 JSC |
8773 | else if (strcmp (p, "4300") == 0) |
8774 | mips_cpu = 4300; | |
8c63448a | 8775 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 8776 | mips_cpu = 4400; |
8c63448a | 8777 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 8778 | mips_cpu = 4600; |
b2b8c24e | 8779 | else if (strcmp (p, "4650") == 0) |
b2b8c24e | 8780 | mips_cpu = 4650; |
4ebda395 GRK |
8781 | /* start-sanitize-tx49 */ |
8782 | else if (strcmp (p, "4900") == 0) | |
8783 | mips_cpu = 4900; | |
8784 | /* end-sanitize-tx49 */ | |
e532b44c | 8785 | else if (strcmp (p, "4010") == 0) |
1724c79e | 8786 | mips_cpu = 4010; |
f3d817d8 | 8787 | break; |
8358c818 | 8788 | |
517078c1 ILT |
8789 | case '5': |
8790 | if (strcmp (p, "5000") == 0 | |
8791 | || strcmp (p, "5k") == 0 | |
8792 | || strcmp (p, "5K") == 0) | |
8793 | mips_cpu = 5000; | |
aa2e0460 KR |
8794 | /* start-sanitize-vr5400 */ |
8795 | else if (strcmp (p, "5400") == 0) | |
8796 | mips_cpu = 5400; | |
8797 | /* end-sanitize-vr5400 */ | |
276c2d7d GRK |
8798 | /* start-sanitize-r5900 */ |
8799 | else if (strcmp (p, "5900") == 0) | |
8800 | mips_cpu = 5900; | |
8801 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
8802 | break; |
8803 | ||
f3d817d8 DM |
8804 | case '6': |
8805 | if (strcmp (p, "6000") == 0 | |
8806 | || strcmp (p, "6k") == 0 | |
8807 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 8808 | mips_cpu = 6000; |
f3d817d8 | 8809 | break; |
55933a58 | 8810 | |
d8a1c247 KR |
8811 | case '8': |
8812 | if (strcmp (p, "8000") == 0 | |
8813 | || strcmp (p, "8k") == 0 | |
8814 | || strcmp (p, "8K") == 0) | |
8815 | mips_cpu = 8000; | |
8816 | break; | |
8817 | ||
55933a58 ILT |
8818 | case 'o': |
8819 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 8820 | mips_cpu = 4600; |
55933a58 | 8821 | break; |
f3d817d8 | 8822 | } |
8358c818 | 8823 | |
b3ed1af3 KR |
8824 | if (sv |
8825 | && (mips_cpu != 4300 | |
8826 | && mips_cpu != 4100 | |
8827 | /* start-sanitize-vr5400 */ | |
8828 | && mips_cpu != 5400 | |
8829 | /* end-sanitize-vr5400 */ | |
8830 | && mips_cpu != 5000)) | |
c625fc23 JSC |
8831 | { |
8832 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
8833 | return 0; | |
8834 | } | |
8835 | ||
4bb0cc41 | 8836 | if (mips_cpu == -1) |
f3d817d8 DM |
8837 | { |
8838 | as_bad ("invalid architecture -mcpu=%s", arg); | |
8839 | return 0; | |
8840 | } | |
8841 | } | |
8842 | } | |
8843 | break; | |
8358c818 | 8844 | |
b2b8c24e ILT |
8845 | case OPTION_M4650: |
8846 | mips_4650 = 1; | |
8847 | break; | |
8848 | ||
8849 | case OPTION_NO_M4650: | |
8850 | mips_4650 = 0; | |
8851 | break; | |
8852 | ||
e532b44c ILT |
8853 | case OPTION_M4010: |
8854 | mips_4010 = 1; | |
8855 | break; | |
8856 | ||
8857 | case OPTION_NO_M4010: | |
8858 | mips_4010 = 0; | |
8859 | break; | |
8860 | ||
c625fc23 JSC |
8861 | case OPTION_M4100: |
8862 | mips_4100 = 1; | |
8863 | break; | |
8864 | ||
8865 | case OPTION_NO_M4100: | |
8866 | mips_4100 = 0; | |
8867 | break; | |
8868 | ||
276c2d7d GRK |
8869 | /* start-sanitize-r5900 */ |
8870 | case OPTION_M5900: | |
8871 | mips_5900 = 1; | |
8872 | break; | |
8873 | ||
8874 | case OPTION_NO_M5900: | |
8875 | mips_5900 = 0; | |
8876 | break; | |
8877 | /* end-sanitize-r5900 */ | |
8878 | ||
aa2e0460 KR |
8879 | /* start-sanitize-vr5400 */ |
8880 | case OPTION_M5400: | |
8881 | mips_5400 = 1; | |
8882 | break; | |
8883 | ||
8884 | case OPTION_NO_M5400: | |
8885 | mips_5400 = 0; | |
8886 | break; | |
8887 | ||
8888 | /* end-sanitize-vr5400 */ | |
5c6f5923 GRK |
8889 | case OPTION_M3900: |
8890 | mips_3900 = 1; | |
8891 | break; | |
8892 | ||
8893 | case OPTION_NO_M3900: | |
8894 | mips_3900 = 0; | |
8895 | break; | |
8896 | ||
42444087 GRK |
8897 | /* start-sanitize-tx49 */ |
8898 | case OPTION_M4900: | |
8899 | mips_4900 = 1; | |
8900 | break; | |
8901 | ||
8902 | case OPTION_NO_M4900: | |
8903 | mips_4900 = 0; | |
8904 | break; | |
8905 | ||
8906 | /* end-sanitize-tx49 */ | |
cc5703cd | 8907 | case OPTION_MIPS16: |
3c83da8a | 8908 | mips_opts.mips16 = 1; |
4a1cb507 | 8909 | mips_no_prev_insn (false); |
cc5703cd ILT |
8910 | break; |
8911 | ||
8912 | case OPTION_NO_MIPS16: | |
3c83da8a | 8913 | mips_opts.mips16 = 0; |
4a1cb507 | 8914 | mips_no_prev_insn (false); |
cc5703cd ILT |
8915 | break; |
8916 | ||
f3d817d8 | 8917 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8918 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8919 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8920 | { |
8921 | as_bad ("-G may not be used with embedded PIC code"); | |
8922 | return 0; | |
8923 | } | |
5b63f465 | 8924 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8925 | break; |
d9aba805 | 8926 | |
fb251650 ILT |
8927 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8928 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8929 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8930 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8931 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8932 | { | |
8933 | as_bad ("-call_shared is supported only for ELF format"); | |
8934 | return 0; | |
8935 | } | |
d9aba805 ILT |
8936 | mips_pic = SVR4_PIC; |
8937 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8938 | { |
8939 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8940 | return 0; | |
8941 | } | |
d9aba805 | 8942 | g_switch_value = 0; |
f3d817d8 DM |
8943 | break; |
8944 | ||
8945 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8946 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8947 | { | |
8948 | as_bad ("-non_shared is supported only for ELF format"); | |
8949 | return 0; | |
8950 | } | |
d9aba805 | 8951 | mips_pic = NO_PIC; |
f3d817d8 | 8952 | break; |
8358c818 | 8953 | |
fb251650 ILT |
8954 | /* The -xgot option tells the assembler to use 32 offsets when |
8955 | accessing the got in SVR4_PIC mode. It is for Irix | |
8956 | compatibility. */ | |
8957 | case OPTION_XGOT: | |
8958 | mips_big_got = 1; | |
8959 | break; | |
8960 | ||
f3d817d8 | 8961 | case 'G': |
1dc1e798 KR |
8962 | if (! USE_GLOBAL_POINTER_OPT) |
8963 | { | |
8964 | as_bad ("-G is not supported for this configuration"); | |
8965 | return 0; | |
8966 | } | |
8967 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8968 | { |
f3d817d8 DM |
8969 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8970 | return 0; | |
670a50eb ILT |
8971 | } |
8972 | else | |
f3d817d8 | 8973 | g_switch_value = atoi (arg); |
42562568 | 8974 | g_switch_seen = 1; |
f3d817d8 | 8975 | break; |
4e95866e | 8976 | |
7f9880e5 ILT |
8977 | /* The -32 and -64 options tell the assembler to output the 32 |
8978 | bit or the 64 bit MIPS ELF format. */ | |
8979 | case OPTION_32: | |
8980 | mips_64 = 0; | |
8981 | break; | |
8982 | ||
8983 | case OPTION_64: | |
9c44af60 ILT |
8984 | { |
8985 | const char **list, **l; | |
8986 | ||
8987 | list = bfd_target_list (); | |
8988 | for (l = list; *l != NULL; l++) | |
8989 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8990 | || strcmp (*l, "elf64-littlemips") == 0) | |
8991 | break; | |
8992 | if (*l == NULL) | |
8993 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8994 | free (list); | |
8995 | mips_64 = 1; | |
8996 | } | |
7f9880e5 ILT |
8997 | break; |
8998 | ||
f3d817d8 DM |
8999 | default: |
9000 | return 0; | |
8ea7f4e8 ILT |
9001 | } |
9002 | ||
f3d817d8 | 9003 | return 1; |
8ea7f4e8 ILT |
9004 | } |
9005 | ||
f3d817d8 DM |
9006 | void |
9007 | md_show_usage (stream) | |
9008 | FILE *stream; | |
9009 | { | |
9010 | fprintf(stream, "\ | |
9011 | MIPS options:\n\ | |
9012 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
9013 | -EB generate big endian output\n\ |
9014 | -EL generate little endian output\n\ | |
9015 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9016 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
9017 | implicitly with the gp register [default 8]\n"); |
9018 | fprintf(stream, "\ | |
f3d817d8 DM |
9019 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
9020 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
9021 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 9022 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 9023 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 9024 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
9025 | -m4650 permit R4650 instructions\n\ |
9026 | -no-m4650 do not permit R4650 instructions\n\ | |
9027 | -m4010 permit R4010 instructions\n\ | |
9028 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
9029 | -m4100 permit VR4100 instructions\n\ |
9030 | -no-m4100 do not permit VR4100 instructions\n"); | |
9031 | fprintf(stream, "\ | |
cc5703cd ILT |
9032 | -mips16 generate mips16 instructions\n\ |
9033 | -no-mips16 do not generate mips16 instructions\n"); | |
9034 | fprintf(stream, "\ | |
f3d817d8 DM |
9035 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9036 | -O remove unneeded NOPs and swap branches\n\ | |
9037 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
9038 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
9039 | #ifdef OBJ_ELF | |
9040 | fprintf(stream, "\ | |
9041 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 9042 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
9043 | -xgot assume a 32 bit GOT\n\ |
9044 | -32 create 32 bit object file (default)\n\ | |
9045 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
9046 | #endif |
9047 | } | |
9048 | \f | |
efec4a28 DP |
9049 | void |
9050 | mips_init_after_args () | |
9051 | { | |
af942793 SS |
9052 | /* initialize opcodes */ |
9053 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
9054 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
9055 | } |
9056 | ||
3d3c5039 ILT |
9057 | long |
9058 | md_pcrel_from (fixP) | |
9059 | fixS *fixP; | |
9060 | { | |
1dc1e798 KR |
9061 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
9062 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
9063 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
9064 | { | |
9065 | /* This makes a branch to an undefined symbol be a branch to the | |
9066 | current location. */ | |
9067 | return 4; | |
9068 | } | |
5b63f465 | 9069 | |
670a50eb ILT |
9070 | /* return the address of the delay slot */ |
9071 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
9072 | } |
9073 | ||
abdad6bc ILT |
9074 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
9075 | reloc for a cons. We could use the definition there, except that | |
9076 | we want to handle 64 bit relocs specially. */ | |
9077 | ||
9078 | void | |
9079 | cons_fix_new_mips (frag, where, nbytes, exp) | |
9080 | fragS *frag; | |
9081 | int where; | |
9082 | unsigned int nbytes; | |
9083 | expressionS *exp; | |
9084 | { | |
bf39474f | 9085 | #ifndef OBJ_ELF |
abdad6bc | 9086 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
9087 | 4 byte reloc. */ |
9088 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 9089 | { |
b9129c6f | 9090 | if (target_big_endian) |
abdad6bc ILT |
9091 | where += 4; |
9092 | nbytes = 4; | |
9093 | } | |
bf39474f | 9094 | #endif |
abdad6bc | 9095 | |
7f9880e5 | 9096 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
9097 | as_bad ("Unsupported reloc size %d", nbytes); |
9098 | ||
9099 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
9100 | (nbytes == 2 |
9101 | ? BFD_RELOC_16 | |
9102 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
9103 | } |
9104 | ||
23604921 ILT |
9105 | /* This is called before the symbol table is processed. In order to |
9106 | work with gcc when using mips-tfile, we must keep all local labels. | |
9107 | However, in other cases, we want to discard them. If we were | |
9108 | called with -g, but we didn't see any debugging information, it may | |
9109 | mean that gcc is smuggling debugging information through to | |
9110 | mips-tfile, in which case we must generate all local labels. */ | |
9111 | ||
9112 | void | |
9113 | mips_frob_file_before_adjust () | |
9114 | { | |
9115 | #ifndef NO_ECOFF_DEBUGGING | |
9116 | if (ECOFF_DEBUGGING | |
9117 | && mips_debug != 0 | |
9118 | && ! ecoff_debugging_seen) | |
9119 | flag_keep_locals = 1; | |
9120 | #endif | |
9121 | } | |
9122 | ||
867a58b3 ILT |
9123 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
9124 | the corresponding LO reloc. This is called before md_apply_fix and | |
9125 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9126 | explicit use of the %hi modifier. */ | |
9127 | ||
9128 | void | |
9129 | mips_frob_file () | |
9130 | { | |
9131 | struct mips_hi_fixup *l; | |
9132 | ||
9133 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9134 | { | |
9135 | segment_info_type *seginfo; | |
9b61d62b | 9136 | int pass; |
867a58b3 ILT |
9137 | |
9138 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9139 | ||
9140 | /* Check quickly whether the next fixup happens to be a matching | |
9141 | %lo. */ | |
9142 | if (l->fixp->fx_next != NULL | |
9143 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9144 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9145 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9146 | continue; | |
9147 | ||
9148 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
9149 | When we find one, move the %hi just in front of it. We do |
9150 | this in two passes. In the first pass, we try to find a | |
9151 | unique %lo. In the second pass, we permit multiple %hi | |
9152 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 9153 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
9154 | for (pass = 0; pass < 2; pass++) |
9155 | { | |
9156 | fixS *f, *prev; | |
9157 | ||
9158 | prev = NULL; | |
9159 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 9160 | { |
9b61d62b ILT |
9161 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
9162 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9163 | && f->fx_addsy == l->fixp->fx_addsy | |
9164 | && f->fx_offset == l->fixp->fx_offset | |
9165 | && (pass == 1 | |
9166 | || prev == NULL | |
9167 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9168 | || prev->fx_addsy != f->fx_addsy | |
9169 | || prev->fx_offset != f->fx_offset)) | |
9170 | { | |
9171 | fixS **pf; | |
867a58b3 | 9172 | |
9b61d62b ILT |
9173 | /* Move l->fixp before f. */ |
9174 | for (pf = &seginfo->fix_root; | |
9175 | *pf != l->fixp; | |
9176 | pf = &(*pf)->fx_next) | |
9177 | assert (*pf != NULL); | |
867a58b3 | 9178 | |
9b61d62b | 9179 | *pf = l->fixp->fx_next; |
867a58b3 | 9180 | |
9b61d62b ILT |
9181 | l->fixp->fx_next = f; |
9182 | if (prev == NULL) | |
9183 | seginfo->fix_root = l->fixp; | |
9184 | else | |
9185 | prev->fx_next = l->fixp; | |
867a58b3 | 9186 | |
9b61d62b ILT |
9187 | break; |
9188 | } | |
9189 | ||
9190 | prev = f; | |
867a58b3 ILT |
9191 | } |
9192 | ||
9b61d62b ILT |
9193 | if (f != NULL) |
9194 | break; | |
867a58b3 | 9195 | |
9b61d62b ILT |
9196 | if (pass == 1) |
9197 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
9198 | "Unmatched %%hi reloc"); | |
9199 | } | |
867a58b3 ILT |
9200 | } |
9201 | } | |
9202 | ||
1c803e52 ILT |
9203 | /* When generating embedded PIC code we need to use a special |
9204 | relocation to represent the difference of two symbols in the .text | |
9205 | section (switch tables use a difference of this sort). See | |
9206 | include/coff/mips.h for details. This macro checks whether this | |
9207 | fixup requires the special reloc. */ | |
9208 | #define SWITCH_TABLE(fixp) \ | |
9209 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
9210 | && (fixp)->fx_addsy != NULL \ | |
9211 | && (fixp)->fx_subsy != NULL \ | |
9212 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9213 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9214 | ||
5b63f465 | 9215 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
9216 | relocations, in case the linker has to relax a call. We also need |
9217 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
9218 | |
9219 | /*ARGSUSED*/ | |
9220 | int | |
9221 | mips_force_relocation (fixp) | |
9222 | fixS *fixp; | |
9223 | { | |
1c803e52 | 9224 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
9225 | && (fixp->fx_pcrel |
9226 | || SWITCH_TABLE (fixp) | |
9227 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9228 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
9229 | } |
9230 | ||
9231 | /* Apply a fixup to the object file. */ | |
9232 | ||
3d3c5039 ILT |
9233 | int |
9234 | md_apply_fix (fixP, valueP) | |
9235 | fixS *fixP; | |
918692a5 | 9236 | valueT *valueP; |
3d3c5039 | 9237 | { |
670a50eb ILT |
9238 | unsigned char *buf; |
9239 | long insn, value; | |
3d3c5039 | 9240 | |
bf39474f ILT |
9241 | assert (fixP->fx_size == 4 |
9242 | || fixP->fx_r_type == BFD_RELOC_16 | |
9243 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 9244 | |
670a50eb | 9245 | value = *valueP; |
1748b9d8 ILT |
9246 | |
9247 | /* If we aren't adjusting this fixup to be against the section | |
9248 | symbol, we need to adjust the value. */ | |
68952421 | 9249 | #ifdef OBJ_ELF |
1748b9d8 | 9250 | if (fixP->fx_addsy != NULL |
1748b9d8 ILT |
9251 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
9252 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
9253 | { | |
9254 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9255 | if (value != 0 && ! fixP->fx_pcrel) | |
9256 | { | |
9257 | /* In this case, the bfd_install_relocation routine will | |
9258 | incorrectly add the symbol value back in. We just want | |
9259 | the addend to appear in the object file. */ | |
9260 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9261 | } | |
9262 | } | |
9263 | #endif | |
9264 | ||
670a50eb | 9265 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 9266 | |
5b63f465 ILT |
9267 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
9268 | fixP->fx_done = 1; | |
9269 | ||
670a50eb ILT |
9270 | switch (fixP->fx_r_type) |
9271 | { | |
3d3c5039 ILT |
9272 | case BFD_RELOC_MIPS_JMP: |
9273 | case BFD_RELOC_HI16: | |
9274 | case BFD_RELOC_HI16_S: | |
670a50eb | 9275 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
9276 | case BFD_RELOC_MIPS_LITERAL: |
9277 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
9278 | case BFD_RELOC_MIPS_GOT16: |
9279 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
9280 | case BFD_RELOC_MIPS_GOT_HI16: |
9281 | case BFD_RELOC_MIPS_GOT_LO16: | |
9282 | case BFD_RELOC_MIPS_CALL_HI16: | |
9283 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 9284 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 9285 | if (fixP->fx_pcrel) |
7b777690 ILT |
9286 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9287 | "Invalid PC relative reloc"); | |
670a50eb | 9288 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 9289 | break; |
3d3c5039 | 9290 | |
cc5703cd ILT |
9291 | case BFD_RELOC_MIPS16_JMP: |
9292 | /* We currently always generate a reloc against a symbol, which | |
9293 | means that we don't want an addend even if the symbol is | |
9294 | defined. */ | |
9295 | fixP->fx_addnumber = 0; | |
9296 | break; | |
9297 | ||
ecd4ca1c ILT |
9298 | case BFD_RELOC_PCREL_HI16_S: |
9299 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9300 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9301 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9302 | { | |
9303 | /* For an external symbol adjust by the address to make it | |
9304 | pcrel_offset. We use the address of the RELLO reloc | |
9305 | which follows this one. */ | |
9306 | value += (fixP->fx_next->fx_frag->fr_address | |
9307 | + fixP->fx_next->fx_where); | |
9308 | } | |
9309 | if (value & 0x8000) | |
9310 | value += 0x10000; | |
9311 | value >>= 16; | |
0221ddf7 | 9312 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9313 | if (target_big_endian) |
ecd4ca1c ILT |
9314 | buf += 2; |
9315 | md_number_to_chars (buf, value, 2); | |
9316 | break; | |
9317 | ||
9318 | case BFD_RELOC_PCREL_LO16: | |
9319 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9320 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9321 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9322 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 9323 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9324 | if (target_big_endian) |
ecd4ca1c ILT |
9325 | buf += 2; |
9326 | md_number_to_chars (buf, value, 2); | |
9327 | break; | |
9328 | ||
bf39474f ILT |
9329 | case BFD_RELOC_64: |
9330 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9331 | extended value if we are only 32 bits. */ | |
9332 | if (fixP->fx_done | |
9333 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9334 | { | |
9335 | if (8 <= sizeof (valueT)) | |
9336 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9337 | value, 8); | |
9338 | else | |
9339 | { | |
9340 | long w1, w2; | |
9341 | long hiv; | |
9342 | ||
9343 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 9344 | if (target_big_endian) |
bf39474f ILT |
9345 | w1 += 4; |
9346 | else | |
9347 | w2 += 4; | |
9348 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9349 | if ((value & 0x80000000) != 0) | |
9350 | hiv = 0xffffffff; | |
9351 | else | |
9352 | hiv = 0; | |
9353 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9354 | } | |
9355 | } | |
9356 | break; | |
9357 | ||
f3645945 ILT |
9358 | case BFD_RELOC_32: |
9359 | /* If we are deleting this reloc entry, we must fill in the | |
9360 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
9361 | resolved when it appears but is later defined. We also need |
9362 | to fill in the value if this is an embedded PIC switch table | |
9363 | entry. */ | |
9364 | if (fixP->fx_done | |
9365 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
9366 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
9367 | value, 4); | |
9368 | break; | |
9369 | ||
49ad0c4c ILT |
9370 | case BFD_RELOC_16: |
9371 | /* If we are deleting this reloc entry, we must fill in the | |
9372 | value now. */ | |
9373 | assert (fixP->fx_size == 2); | |
9374 | if (fixP->fx_done) | |
9375 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9376 | value, 2); | |
9377 | break; | |
9378 | ||
f3645945 ILT |
9379 | case BFD_RELOC_LO16: |
9380 | /* When handling an embedded PIC switch statement, we can wind | |
9381 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9382 | if (fixP->fx_done) | |
9383 | { | |
9384 | if (value < -0x8000 || value > 0x7fff) | |
9385 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9386 | "relocation overflow"); | |
0221ddf7 | 9387 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9388 | if (target_big_endian) |
f3645945 ILT |
9389 | buf += 2; |
9390 | md_number_to_chars (buf, value, 2); | |
9391 | } | |
9392 | break; | |
9393 | ||
3d3c5039 | 9394 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
9395 | /* |
9396 | * We need to save the bits in the instruction since fixup_segment() | |
9397 | * might be deleting the relocation entry (i.e., a branch within | |
9398 | * the current segment). | |
9399 | */ | |
fbcfacb7 | 9400 | if ((value & 0x3) != 0) |
3b320c48 ILT |
9401 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9402 | "Branch to odd address (%lx)", value); | |
670a50eb | 9403 | value >>= 2; |
670a50eb ILT |
9404 | |
9405 | /* update old instruction data */ | |
9406 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
9407 | if (target_big_endian) |
9408 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9409 | else | |
9410 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
9411 | |
9412 | if (value >= -0x8000 && value < 0x8000) | |
9413 | insn |= value & 0xffff; | |
9414 | else | |
9415 | { | |
9416 | /* The branch offset is too large. If this is an | |
9417 | unconditional branch, and we are not generating PIC code, | |
9418 | we can convert it to an absolute jump instruction. */ | |
9419 | if (mips_pic == NO_PIC | |
9420 | && fixP->fx_done | |
9421 | && fixP->fx_frag->fr_address >= text_section->vma | |
9422 | && (fixP->fx_frag->fr_address | |
9423 | < text_section->vma + text_section->_raw_size) | |
9424 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9425 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9426 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9427 | { | |
9428 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9429 | insn = 0x0c000000; /* jal */ | |
9430 | else | |
9431 | insn = 0x08000000; /* j */ | |
9432 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9433 | fixP->fx_done = 0; | |
9434 | fixP->fx_addsy = section_symbol (text_section); | |
9435 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9436 | } | |
9437 | else | |
9438 | { | |
9439 | /* FIXME. It would be possible in principle to handle | |
9440 | conditional branches which overflow. They could be | |
9441 | transformed into a branch around a jump. This would | |
9442 | require setting up variant frags for each different | |
9443 | branch type. The native MIPS assembler attempts to | |
9444 | handle these cases, but it appears to do it | |
9445 | incorrectly. */ | |
9446 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18f7e3dc | 9447 | "Branch out of range"); |
9da4c5d1 ILT |
9448 | } |
9449 | } | |
9450 | ||
604633ae | 9451 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 9452 | break; |
3d3c5039 ILT |
9453 | |
9454 | default: | |
670a50eb | 9455 | internalError (); |
3d3c5039 | 9456 | } |
5b63f465 | 9457 | |
670a50eb | 9458 | return 1; |
3d3c5039 ILT |
9459 | } |
9460 | ||
9461 | #if 0 | |
9462 | void | |
670a50eb ILT |
9463 | printInsn (oc) |
9464 | unsigned long oc; | |
3d3c5039 | 9465 | { |
670a50eb ILT |
9466 | const struct mips_opcode *p; |
9467 | int treg, sreg, dreg, shamt; | |
9468 | short imm; | |
9469 | const char *args; | |
9470 | int i; | |
3d3c5039 | 9471 | |
670a50eb ILT |
9472 | for (i = 0; i < NUMOPCODES; ++i) |
9473 | { | |
9474 | p = &mips_opcodes[i]; | |
9475 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9476 | { | |
9477 | printf ("%08lx %s\t", oc, p->name); | |
9478 | treg = (oc >> 16) & 0x1f; | |
9479 | sreg = (oc >> 21) & 0x1f; | |
9480 | dreg = (oc >> 11) & 0x1f; | |
9481 | shamt = (oc >> 6) & 0x1f; | |
9482 | imm = oc; | |
9483 | for (args = p->args;; ++args) | |
9484 | { | |
9485 | switch (*args) | |
9486 | { | |
3d3c5039 | 9487 | case '\0': |
670a50eb ILT |
9488 | printf ("\n"); |
9489 | break; | |
3d3c5039 ILT |
9490 | |
9491 | case ',': | |
9492 | case '(': | |
9493 | case ')': | |
670a50eb ILT |
9494 | printf ("%c", *args); |
9495 | continue; | |
3d3c5039 ILT |
9496 | |
9497 | case 'r': | |
670a50eb ILT |
9498 | assert (treg == sreg); |
9499 | printf ("$%d,$%d", treg, sreg); | |
9500 | continue; | |
3d3c5039 ILT |
9501 | |
9502 | case 'd': | |
918692a5 | 9503 | case 'G': |
670a50eb ILT |
9504 | printf ("$%d", dreg); |
9505 | continue; | |
3d3c5039 ILT |
9506 | |
9507 | case 't': | |
918692a5 | 9508 | case 'E': |
670a50eb ILT |
9509 | printf ("$%d", treg); |
9510 | continue; | |
3d3c5039 | 9511 | |
9226253a ILT |
9512 | case 'k': |
9513 | printf ("0x%x", treg); | |
9514 | continue; | |
9515 | ||
3d3c5039 ILT |
9516 | case 'b': |
9517 | case 's': | |
670a50eb ILT |
9518 | printf ("$%d", sreg); |
9519 | continue; | |
3d3c5039 ILT |
9520 | |
9521 | case 'a': | |
670a50eb ILT |
9522 | printf ("0x%08lx", oc & 0x1ffffff); |
9523 | continue; | |
3d3c5039 ILT |
9524 | |
9525 | case 'i': | |
9526 | case 'j': | |
9527 | case 'o': | |
9528 | case 'u': | |
670a50eb ILT |
9529 | printf ("%d", imm); |
9530 | continue; | |
3d3c5039 ILT |
9531 | |
9532 | case '<': | |
56c96faa | 9533 | case '>': |
670a50eb ILT |
9534 | printf ("$%d", shamt); |
9535 | continue; | |
3d3c5039 ILT |
9536 | |
9537 | default: | |
670a50eb | 9538 | internalError (); |
3d3c5039 | 9539 | } |
670a50eb | 9540 | break; |
3d3c5039 | 9541 | } |
670a50eb | 9542 | return; |
3d3c5039 ILT |
9543 | } |
9544 | } | |
670a50eb | 9545 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
9546 | } |
9547 | #endif | |
9548 | ||
9549 | static symbolS * | |
9550 | get_symbol () | |
9551 | { | |
670a50eb ILT |
9552 | int c; |
9553 | char *name; | |
9554 | symbolS *p; | |
9555 | ||
9556 | name = input_line_pointer; | |
9557 | c = get_symbol_end (); | |
9558 | p = (symbolS *) symbol_find_or_make (name); | |
9559 | *input_line_pointer = c; | |
9560 | return p; | |
3d3c5039 ILT |
9561 | } |
9562 | ||
becfe05e ILT |
9563 | /* Align the current frag to a given power of two. The MIPS assembler |
9564 | also automatically adjusts any preceding label. */ | |
9565 | ||
9566 | static void | |
23dc1ae3 | 9567 | mips_align (to, fill, label) |
becfe05e ILT |
9568 | int to; |
9569 | int fill; | |
23dc1ae3 | 9570 | symbolS *label; |
becfe05e | 9571 | { |
fbcfacb7 | 9572 | mips_emit_delays (false); |
e2e5acfa | 9573 | frag_align (to, fill, 0); |
becfe05e | 9574 | record_alignment (now_seg, to); |
23dc1ae3 | 9575 | if (label != NULL) |
becfe05e | 9576 | { |
23dc1ae3 ILT |
9577 | assert (S_GET_SEGMENT (label) == now_seg); |
9578 | label->sy_frag = frag_now; | |
9579 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
9580 | } |
9581 | } | |
9582 | ||
9583 | /* Align to a given power of two. .align 0 turns off the automatic | |
9584 | alignment used by the data creating pseudo-ops. */ | |
9585 | ||
3d3c5039 ILT |
9586 | static void |
9587 | s_align (x) | |
9588 | int x; | |
9589 | { | |
670a50eb ILT |
9590 | register int temp; |
9591 | register long temp_fill; | |
9592 | long max_alignment = 15; | |
3d3c5039 | 9593 | |
670a50eb | 9594 | /* |
3d3c5039 ILT |
9595 | |
9596 | o Note that the assembler pulls down any immediately preceeding label | |
9597 | to the aligned address. | |
9598 | o It's not documented but auto alignment is reinstated by | |
9599 | a .align pseudo instruction. | |
9600 | o Note also that after auto alignment is turned off the mips assembler | |
9601 | issues an error on attempt to assemble an improperly aligned data item. | |
9602 | We don't. | |
9603 | ||
9604 | */ | |
9605 | ||
670a50eb ILT |
9606 | temp = get_absolute_expression (); |
9607 | if (temp > max_alignment) | |
9608 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
9609 | else if (temp < 0) | |
9610 | { | |
9611 | as_warn ("Alignment negative: 0 assumed."); | |
9612 | temp = 0; | |
9613 | } | |
9614 | if (*input_line_pointer == ',') | |
9615 | { | |
9616 | input_line_pointer++; | |
9617 | temp_fill = get_absolute_expression (); | |
9618 | } | |
9619 | else | |
9620 | temp_fill = 0; | |
9621 | if (temp) | |
9622 | { | |
9623 | auto_align = 1; | |
fbcfacb7 ILT |
9624 | mips_align (temp, (int) temp_fill, |
9625 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 9626 | } |
670a50eb ILT |
9627 | else |
9628 | { | |
9629 | auto_align = 0; | |
3d3c5039 ILT |
9630 | } |
9631 | ||
670a50eb | 9632 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9633 | } |
9634 | ||
739708fa KR |
9635 | void |
9636 | mips_flush_pending_output () | |
becfe05e | 9637 | { |
fbcfacb7 ILT |
9638 | mips_emit_delays (false); |
9639 | mips_clear_insn_labels (); | |
becfe05e ILT |
9640 | } |
9641 | ||
3d3c5039 ILT |
9642 | static void |
9643 | s_change_sec (sec) | |
9644 | int sec; | |
9645 | { | |
88225433 | 9646 | segT seg; |
becfe05e | 9647 | |
5b63f465 ILT |
9648 | /* When generating embedded PIC code, we only use the .text, .lit8, |
9649 | .sdata and .sbss sections. We change the .data and .rdata | |
9650 | pseudo-ops to use .sdata. */ | |
9651 | if (mips_pic == EMBEDDED_PIC | |
9652 | && (sec == 'd' || sec == 'r')) | |
9653 | sec = 's'; | |
9654 | ||
acdc7ce3 ILT |
9655 | #ifdef OBJ_ELF |
9656 | /* The ELF backend needs to know that we are changing sections, so | |
9657 | that .previous works correctly. We could do something like check | |
9658 | for a obj_section_change_hook macro, but that might be confusing | |
9659 | as it would not be appropriate to use it in the section changing | |
9660 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
9661 | This should be cleaner, somehow. */ | |
9662 | obj_elf_section_change_hook (); | |
9663 | #endif | |
9664 | ||
fbcfacb7 | 9665 | mips_emit_delays (false); |
670a50eb ILT |
9666 | switch (sec) |
9667 | { | |
3d3c5039 | 9668 | case 't': |
604633ae | 9669 | s_text (0); |
670a50eb | 9670 | break; |
3d3c5039 | 9671 | case 'd': |
604633ae | 9672 | s_data (0); |
670a50eb | 9673 | break; |
3d3c5039 | 9674 | case 'b': |
670a50eb | 9675 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
9676 | demand_empty_rest_of_line (); |
9677 | break; | |
88225433 ILT |
9678 | |
9679 | case 'r': | |
1dc1e798 KR |
9680 | if (USE_GLOBAL_POINTER_OPT) |
9681 | { | |
9682 | seg = subseg_new (RDATA_SECTION_NAME, | |
9683 | (subsegT) get_absolute_expression ()); | |
9684 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9685 | { | |
9686 | bfd_set_section_flags (stdoutput, seg, | |
9687 | (SEC_ALLOC | |
9688 | | SEC_LOAD | |
9689 | | SEC_READONLY | |
9690 | | SEC_RELOC | |
9691 | | SEC_DATA)); | |
08e17202 ILT |
9692 | if (strcmp (TARGET_OS, "elf") != 0) |
9693 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9694 | } |
9695 | demand_empty_rest_of_line (); | |
9696 | } | |
9697 | else | |
9698 | { | |
9699 | as_bad ("No read only data section in this object file format"); | |
9700 | demand_empty_rest_of_line (); | |
9701 | return; | |
9702 | } | |
88225433 | 9703 | break; |
88225433 ILT |
9704 | |
9705 | case 's': | |
1dc1e798 KR |
9706 | if (USE_GLOBAL_POINTER_OPT) |
9707 | { | |
9708 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9709 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9710 | { | |
9711 | bfd_set_section_flags (stdoutput, seg, | |
9712 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9713 | | SEC_DATA); | |
08e17202 ILT |
9714 | if (strcmp (TARGET_OS, "elf") != 0) |
9715 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9716 | } |
9717 | demand_empty_rest_of_line (); | |
9718 | break; | |
9719 | } | |
9720 | else | |
9721 | { | |
9722 | as_bad ("Global pointers not supported; recompile -G 0"); | |
9723 | demand_empty_rest_of_line (); | |
9724 | return; | |
9725 | } | |
3d3c5039 | 9726 | } |
88225433 | 9727 | |
670a50eb | 9728 | auto_align = 1; |
3d3c5039 ILT |
9729 | } |
9730 | ||
739708fa KR |
9731 | void |
9732 | mips_enable_auto_align () | |
9da4c5d1 | 9733 | { |
9da4c5d1 ILT |
9734 | auto_align = 1; |
9735 | } | |
9736 | ||
3d3c5039 ILT |
9737 | static void |
9738 | s_cons (log_size) | |
9739 | int log_size; | |
9740 | { | |
23dc1ae3 ILT |
9741 | symbolS *label; |
9742 | ||
fbcfacb7 ILT |
9743 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9744 | mips_emit_delays (false); | |
670a50eb | 9745 | if (log_size > 0 && auto_align) |
23dc1ae3 | 9746 | mips_align (log_size, 0, label); |
fbcfacb7 | 9747 | mips_clear_insn_labels (); |
670a50eb | 9748 | cons (1 << log_size); |
3d3c5039 ILT |
9749 | } |
9750 | ||
3d3c5039 | 9751 | static void |
becfe05e ILT |
9752 | s_float_cons (type) |
9753 | int type; | |
3d3c5039 | 9754 | { |
23dc1ae3 ILT |
9755 | symbolS *label; |
9756 | ||
fbcfacb7 | 9757 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 9758 | |
fbcfacb7 | 9759 | mips_emit_delays (false); |
670a50eb ILT |
9760 | |
9761 | if (auto_align) | |
becfe05e | 9762 | if (type == 'd') |
23dc1ae3 | 9763 | mips_align (3, 0, label); |
670a50eb | 9764 | else |
23dc1ae3 | 9765 | mips_align (2, 0, label); |
670a50eb | 9766 | |
fbcfacb7 | 9767 | mips_clear_insn_labels (); |
1849d646 | 9768 | |
becfe05e | 9769 | float_cons (type); |
3d3c5039 ILT |
9770 | } |
9771 | ||
c1444ec4 ILT |
9772 | /* Handle .globl. We need to override it because on Irix 5 you are |
9773 | permitted to say | |
9774 | .globl foo .text | |
9775 | where foo is an undefined symbol, to mean that foo should be | |
9776 | considered to be the address of a function. */ | |
9777 | ||
9778 | static void | |
9779 | s_mips_globl (x) | |
9780 | int x; | |
9781 | { | |
9782 | char *name; | |
9783 | int c; | |
9784 | symbolS *symbolP; | |
fb251650 | 9785 | flagword flag; |
c1444ec4 ILT |
9786 | |
9787 | name = input_line_pointer; | |
9788 | c = get_symbol_end (); | |
9789 | symbolP = symbol_find_or_make (name); | |
9790 | *input_line_pointer = c; | |
9791 | SKIP_WHITESPACE (); | |
fb251650 ILT |
9792 | |
9793 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
9794 | being a function is apparently labelled as being an object. */ | |
9795 | flag = BSF_OBJECT; | |
9796 | ||
c1444ec4 ILT |
9797 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
9798 | { | |
9799 | char *secname; | |
9800 | asection *sec; | |
9801 | ||
9802 | secname = input_line_pointer; | |
9803 | c = get_symbol_end (); | |
9804 | sec = bfd_get_section_by_name (stdoutput, secname); | |
9805 | if (sec == NULL) | |
9806 | as_bad ("%s: no such section", secname); | |
9807 | *input_line_pointer = c; | |
9808 | ||
9809 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 9810 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
9811 | } |
9812 | ||
fb251650 ILT |
9813 | symbolP->bsym->flags |= flag; |
9814 | ||
c1444ec4 ILT |
9815 | S_SET_EXTERNAL (symbolP); |
9816 | demand_empty_rest_of_line (); | |
9817 | } | |
9818 | ||
3d3c5039 ILT |
9819 | static void |
9820 | s_option (x) | |
9821 | int x; | |
9822 | { | |
dd3f1f76 ILT |
9823 | char *opt; |
9824 | char c; | |
9825 | ||
9826 | opt = input_line_pointer; | |
9827 | c = get_symbol_end (); | |
9828 | ||
dd3f1f76 | 9829 | if (*opt == 'O') |
9226253a ILT |
9830 | { |
9831 | /* FIXME: What does this mean? */ | |
9832 | } | |
dd3f1f76 | 9833 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 9834 | { |
d9aba805 | 9835 | int i; |
42562568 | 9836 | |
d9aba805 ILT |
9837 | i = atoi (opt + 3); |
9838 | if (i == 0) | |
9839 | mips_pic = NO_PIC; | |
9840 | else if (i == 2) | |
9841 | mips_pic = SVR4_PIC; | |
9842 | else | |
9843 | as_bad (".option pic%d not supported", i); | |
9844 | ||
1dc1e798 | 9845 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
9846 | { |
9847 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 9848 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
9849 | g_switch_value = 0; |
9850 | bfd_set_gp_size (stdoutput, 0); | |
9851 | } | |
9226253a | 9852 | } |
dd3f1f76 ILT |
9853 | else |
9854 | as_warn ("Unrecognized option \"%s\"", opt); | |
9855 | ||
9856 | *input_line_pointer = c; | |
670a50eb | 9857 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9858 | } |
9859 | ||
3c83da8a JW |
9860 | /* This structure is used to hold a stack of .set values. */ |
9861 | ||
9862 | struct mips_option_stack | |
9863 | { | |
9864 | struct mips_option_stack *next; | |
9865 | struct mips_set_options options; | |
9866 | }; | |
9867 | ||
9868 | static struct mips_option_stack *mips_opts_stack; | |
9869 | ||
9870 | /* Handle the .set pseudo-op. */ | |
9871 | ||
3d3c5039 ILT |
9872 | static void |
9873 | s_mipsset (x) | |
9874 | int x; | |
9875 | { | |
670a50eb ILT |
9876 | char *name = input_line_pointer, ch; |
9877 | ||
9878 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
9879 | input_line_pointer++; | |
9880 | ch = *input_line_pointer; | |
9881 | *input_line_pointer = '\0'; | |
9882 | ||
9883 | if (strcmp (name, "reorder") == 0) | |
9884 | { | |
3c83da8a | 9885 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 9886 | { |
4a1cb507 ILT |
9887 | /* If we still have pending nops, we can discard them. The |
9888 | usual nop handling will insert any that are still | |
9889 | needed. */ | |
3c83da8a JW |
9890 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
9891 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 9892 | prev_nop_frag = NULL; |
4e95866e | 9893 | } |
3c83da8a | 9894 | mips_opts.noreorder = 0; |
670a50eb ILT |
9895 | } |
9896 | else if (strcmp (name, "noreorder") == 0) | |
9897 | { | |
fbcfacb7 | 9898 | mips_emit_delays (true); |
3c83da8a | 9899 | mips_opts.noreorder = 1; |
0dd2d296 | 9900 | mips_any_noreorder = 1; |
670a50eb ILT |
9901 | } |
9902 | else if (strcmp (name, "at") == 0) | |
9903 | { | |
3c83da8a | 9904 | mips_opts.noat = 0; |
670a50eb ILT |
9905 | } |
9906 | else if (strcmp (name, "noat") == 0) | |
9907 | { | |
3c83da8a | 9908 | mips_opts.noat = 1; |
3d3c5039 | 9909 | } |
670a50eb ILT |
9910 | else if (strcmp (name, "macro") == 0) |
9911 | { | |
3c83da8a | 9912 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
9913 | } |
9914 | else if (strcmp (name, "nomacro") == 0) | |
9915 | { | |
3c83da8a | 9916 | if (mips_opts.noreorder == 0) |
670a50eb | 9917 | as_bad ("`noreorder' must be set before `nomacro'"); |
3c83da8a | 9918 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
9919 | } |
9920 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
9921 | { | |
3c83da8a | 9922 | mips_opts.nomove = 0; |
670a50eb ILT |
9923 | } |
9924 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
9925 | { | |
3c83da8a | 9926 | mips_opts.nomove = 1; |
670a50eb ILT |
9927 | } |
9928 | else if (strcmp (name, "bopt") == 0) | |
9929 | { | |
3c83da8a | 9930 | mips_opts.nobopt = 0; |
670a50eb ILT |
9931 | } |
9932 | else if (strcmp (name, "nobopt") == 0) | |
9933 | { | |
3c83da8a | 9934 | mips_opts.nobopt = 1; |
670a50eb | 9935 | } |
943321c0 ILT |
9936 | else if (strcmp (name, "mips16") == 0 |
9937 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 9938 | mips_opts.mips16 = 1; |
943321c0 ILT |
9939 | else if (strcmp (name, "nomips16") == 0 |
9940 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 9941 | mips_opts.mips16 = 0; |
1051c97f ILT |
9942 | else if (strncmp (name, "mips", 4) == 0) |
9943 | { | |
9944 | int isa; | |
9945 | ||
9946 | /* Permit the user to change the ISA on the fly. Needless to | |
9947 | say, misuse can cause serious problems. */ | |
9948 | isa = atoi (name + 4); | |
9949 | if (isa == 0) | |
3c83da8a | 9950 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 9951 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
9952 | as_bad ("unknown ISA level"); |
9953 | else | |
3c83da8a | 9954 | mips_opts.isa = isa; |
1051c97f | 9955 | } |
cc5703cd | 9956 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 9957 | mips_opts.noautoextend = 0; |
cc5703cd | 9958 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
9959 | mips_opts.noautoextend = 1; |
9960 | else if (strcmp (name, "push") == 0) | |
9961 | { | |
9962 | struct mips_option_stack *s; | |
9963 | ||
9964 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
9965 | s->next = mips_opts_stack; | |
9966 | s->options = mips_opts; | |
9967 | mips_opts_stack = s; | |
9968 | } | |
9969 | else if (strcmp (name, "pop") == 0) | |
9970 | { | |
9971 | struct mips_option_stack *s; | |
9972 | ||
9973 | s = mips_opts_stack; | |
9974 | if (s == NULL) | |
9975 | as_bad (".set pop with no .set push"); | |
9976 | else | |
9977 | { | |
9978 | /* If we're changing the reorder mode we need to handle | |
9979 | delay slots correctly. */ | |
9980 | if (s->options.noreorder && ! mips_opts.noreorder) | |
9981 | mips_emit_delays (true); | |
9982 | else if (! s->options.noreorder && mips_opts.noreorder) | |
9983 | { | |
9984 | if (prev_nop_frag != NULL) | |
9985 | { | |
9986 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
9987 | * (mips_opts.mips16 ? 2 : 4)); | |
9988 | prev_nop_frag = NULL; | |
9989 | } | |
9990 | } | |
9991 | ||
9992 | mips_opts = s->options; | |
9993 | mips_opts_stack = s->next; | |
9994 | free (s); | |
9995 | } | |
9996 | } | |
670a50eb ILT |
9997 | else |
9998 | { | |
9999 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
10000 | } | |
10001 | *input_line_pointer = ch; | |
10002 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
10003 | } |
10004 | ||
9226253a ILT |
10005 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
10006 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10007 | ||
10008 | static void | |
10009 | s_abicalls (ignore) | |
10010 | int ignore; | |
10011 | { | |
d9aba805 | 10012 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
10013 | if (USE_GLOBAL_POINTER_OPT) |
10014 | { | |
10015 | if (g_switch_seen && g_switch_value != 0) | |
10016 | as_warn ("-G may not be used with SVR4 PIC code"); | |
10017 | g_switch_value = 0; | |
10018 | } | |
d9aba805 | 10019 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
10020 | demand_empty_rest_of_line (); |
10021 | } | |
10022 | ||
10023 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10024 | PIC code. It sets the $gp register for the function based on the | |
10025 | function address, which is in the register named in the argument. | |
10026 | This uses a relocation against _gp_disp, which is handled specially | |
10027 | by the linker. The result is: | |
10028 | lui $gp,%hi(_gp_disp) | |
10029 | addiu $gp,$gp,%lo(_gp_disp) | |
10030 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 10031 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
10032 | |
10033 | static void | |
10034 | s_cpload (ignore) | |
10035 | int ignore; | |
10036 | { | |
10037 | expressionS ex; | |
10038 | int icnt = 0; | |
10039 | ||
d9aba805 ILT |
10040 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
10041 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10042 | { |
10043 | s_ignore (0); | |
10044 | return; | |
10045 | } | |
10046 | ||
10047 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 10048 | if (mips_opts.noreorder == 0) |
0dd2d296 ILT |
10049 | as_warn (".cpload not in noreorder section"); |
10050 | ||
9226253a ILT |
10051 | ex.X_op = O_symbol; |
10052 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10053 | ex.X_op_symbol = NULL; | |
10054 | ex.X_add_number = 0; | |
10055 | ||
fb251650 ILT |
10056 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
10057 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
10058 | ||
0dd2d296 ILT |
10059 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
10060 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
10061 | (int) BFD_RELOC_LO16); |
10062 | ||
0dd2d296 ILT |
10063 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
10064 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
10065 | |
10066 | demand_empty_rest_of_line (); | |
10067 | } | |
10068 | ||
10069 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10070 | offset from $sp. The offset is remembered, and after making a PIC | |
10071 | call $gp is restored from that location. */ | |
10072 | ||
10073 | static void | |
10074 | s_cprestore (ignore) | |
10075 | int ignore; | |
10076 | { | |
10077 | expressionS ex; | |
10078 | int icnt = 0; | |
10079 | ||
d9aba805 ILT |
10080 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
10081 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10082 | { |
10083 | s_ignore (0); | |
10084 | return; | |
10085 | } | |
10086 | ||
9226253a ILT |
10087 | mips_cprestore_offset = get_absolute_expression (); |
10088 | ||
10089 | ex.X_op = O_constant; | |
10090 | ex.X_add_symbol = NULL; | |
10091 | ex.X_op_symbol = NULL; | |
10092 | ex.X_add_number = mips_cprestore_offset; | |
10093 | ||
0dd2d296 | 10094 | macro_build ((char *) NULL, &icnt, &ex, |
3c83da8a | 10095 | mips_opts.isa < 3 ? "sw" : "sd", |
9226253a ILT |
10096 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
10097 | ||
10098 | demand_empty_rest_of_line (); | |
10099 | } | |
10100 | ||
0dd2d296 ILT |
10101 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
10102 | code. It generates a 32 bit GP relative reloc. */ | |
10103 | ||
10104 | static void | |
10105 | s_gpword (ignore) | |
10106 | int ignore; | |
10107 | { | |
23dc1ae3 | 10108 | symbolS *label; |
0dd2d296 ILT |
10109 | expressionS ex; |
10110 | char *p; | |
10111 | ||
10112 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 10113 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10114 | { |
10115 | s_cons (2); | |
10116 | return; | |
10117 | } | |
10118 | ||
fbcfacb7 ILT |
10119 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10120 | mips_emit_delays (true); | |
0dd2d296 | 10121 | if (auto_align) |
23dc1ae3 | 10122 | mips_align (2, 0, label); |
fbcfacb7 | 10123 | mips_clear_insn_labels (); |
0dd2d296 ILT |
10124 | |
10125 | expression (&ex); | |
10126 | ||
10127 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10128 | { | |
10129 | as_bad ("Unsupported use of .gpword"); | |
10130 | ignore_rest_of_line (); | |
10131 | } | |
10132 | ||
10133 | p = frag_more (4); | |
10134 | md_number_to_chars (p, (valueT) 0, 4); | |
10135 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10136 | BFD_RELOC_MIPS_GPREL32); | |
10137 | ||
10138 | demand_empty_rest_of_line (); | |
10139 | } | |
10140 | ||
10141 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10142 | tables in SVR4 PIC code. */ | |
10143 | ||
10144 | static void | |
10145 | s_cpadd (ignore) | |
10146 | int ignore; | |
10147 | { | |
10148 | int icnt = 0; | |
10149 | int reg; | |
10150 | ||
10151 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 10152 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10153 | { |
10154 | s_ignore (0); | |
10155 | return; | |
10156 | } | |
10157 | ||
10158 | /* Add $gp to the register named as an argument. */ | |
10159 | reg = tc_get_register (0); | |
10160 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 10161 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
10162 | "d,v,t", reg, reg, GP); |
10163 | ||
10164 | demand_empty_rest_of_line (); | |
10165 | } | |
10166 | ||
ed3eb786 ILT |
10167 | /* Handle the .insn pseudo-op. This marks instruction labels in |
10168 | mips16 mode. This permits the linker to handle them specially, | |
10169 | such as generating jalx instructions when needed. We also make | |
10170 | them odd for the duration of the assembly, in order to generate the | |
10171 | right sort of code. We will make them even in the adjust_symtab | |
10172 | routine, while leaving them marked. This is convenient for the | |
10173 | debugger and the disassembler. The linker knows to make them odd | |
10174 | again. */ | |
10175 | ||
10176 | static void | |
10177 | s_insn (ignore) | |
10178 | int ignore; | |
10179 | { | |
3c83da8a JW |
10180 | if (mips_opts.mips16) |
10181 | mips16_mark_labels (); | |
ed3eb786 | 10182 | |
3c83da8a JW |
10183 | demand_empty_rest_of_line (); |
10184 | } | |
ed3eb786 | 10185 | |
3c83da8a JW |
10186 | /* Handle a .stabn directive. We need these in order to mark a label |
10187 | as being a mips16 text label correctly. Sometimes the compiler | |
10188 | will emit a label, followed by a .stabn, and then switch sections. | |
10189 | If the label and .stabn are in mips16 mode, then the label is | |
10190 | really a mips16 text label. */ | |
ed3eb786 | 10191 | |
3c83da8a JW |
10192 | static void |
10193 | s_mips_stab (type) | |
10194 | int type; | |
10195 | { | |
10196 | if (type == 'n' && mips_opts.mips16) | |
10197 | mips16_mark_labels (); | |
10198 | ||
10199 | s_stab (type); | |
ed3eb786 ILT |
10200 | } |
10201 | ||
9226253a | 10202 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
10203 | to parse .frame. The argument is non-zero if this is the frame |
10204 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 10205 | |
3d3c5039 | 10206 | int |
0dd2d296 ILT |
10207 | tc_get_register (frame) |
10208 | int frame; | |
3d3c5039 ILT |
10209 | { |
10210 | int reg; | |
10211 | ||
10212 | SKIP_WHITESPACE (); | |
10213 | if (*input_line_pointer++ != '$') | |
10214 | { | |
10215 | as_warn ("expected `$'"); | |
0dd2d296 | 10216 | reg = 0; |
3d3c5039 | 10217 | } |
0dd2d296 | 10218 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
10219 | { |
10220 | reg = get_absolute_expression (); | |
10221 | if (reg < 0 || reg >= 32) | |
10222 | { | |
10223 | as_warn ("Bad register number"); | |
10224 | reg = 0; | |
10225 | } | |
10226 | } | |
10227 | else | |
10228 | { | |
10229 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 10230 | reg = FP; |
3d3c5039 | 10231 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 10232 | reg = SP; |
3d3c5039 | 10233 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 10234 | reg = GP; |
3d3c5039 | 10235 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 10236 | reg = AT; |
3d3c5039 ILT |
10237 | else |
10238 | { | |
10239 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 10240 | reg = 0; |
3d3c5039 ILT |
10241 | } |
10242 | input_line_pointer += 2; | |
10243 | } | |
0dd2d296 ILT |
10244 | if (frame) |
10245 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
10246 | return reg; |
10247 | } | |
10248 | ||
0dd2d296 ILT |
10249 | valueT |
10250 | md_section_align (seg, addr) | |
10251 | asection *seg; | |
10252 | valueT addr; | |
10253 | { | |
10254 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10255 | ||
cf32394d ILT |
10256 | #ifdef OBJ_ELF |
10257 | /* We don't need to align ELF sections to the full alignment. | |
10258 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
10259 | byte boundary. We don't bother to align the sections if we are |
10260 | targeted for an embedded system. */ | |
10261 | if (strcmp (TARGET_OS, "elf") == 0) | |
10262 | return addr; | |
943321c0 ILT |
10263 | if (align > 4) |
10264 | align = 4; | |
10a14e36 | 10265 | #endif |
cf32394d ILT |
10266 | |
10267 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
10268 | } |
10269 | ||
d8a1c247 KR |
10270 | /* Utility routine, called from above as well. If called while the |
10271 | input file is still being read, it's only an approximation. (For | |
10272 | example, a symbol may later become defined which appeared to be | |
10273 | undefined earlier.) */ | |
22ba90ce ILT |
10274 | |
10275 | static int | |
85ce5635 | 10276 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 10277 | symbolS *sym; |
85ce5635 | 10278 | int before_relaxing; |
d8a1c247 KR |
10279 | { |
10280 | if (sym == 0) | |
10281 | return 0; | |
10282 | ||
1dc1e798 KR |
10283 | if (USE_GLOBAL_POINTER_OPT) |
10284 | { | |
10285 | const char *symname; | |
10286 | int change; | |
10287 | ||
10288 | /* Find out whether this symbol can be referenced off the GP | |
10289 | register. It can be if it is smaller than the -G size or if | |
10290 | it is in the .sdata or .sbss section. Certain symbols can | |
10291 | not be referenced off the GP, although it appears as though | |
10292 | they can. */ | |
10293 | symname = S_GET_NAME (sym); | |
10294 | if (symname != (const char *) NULL | |
10295 | && (strcmp (symname, "eprol") == 0 | |
10296 | || strcmp (symname, "etext") == 0 | |
10297 | || strcmp (symname, "_gp") == 0 | |
10298 | || strcmp (symname, "edata") == 0 | |
10299 | || strcmp (symname, "_fbss") == 0 | |
10300 | || strcmp (symname, "_fdata") == 0 | |
10301 | || strcmp (symname, "_ftext") == 0 | |
10302 | || strcmp (symname, "end") == 0 | |
10303 | || strcmp (symname, "_gp_disp") == 0)) | |
10304 | change = 1; | |
23ac3ca1 | 10305 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
10306 | && (0 |
10307 | #ifndef NO_ECOFF_DEBUGGING | |
10308 | || (sym->ecoff_extern_size != 0 | |
10309 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 10310 | #endif |
85ce5635 ILT |
10311 | /* We must defer this decision until after the whole |
10312 | file has been read, since there might be a .extern | |
10313 | after the first use of this symbol. */ | |
a5586bdc ILT |
10314 | || (before_relaxing |
10315 | #ifndef NO_ECOFF_DEBUGGING | |
10316 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 10317 | #endif |
a5586bdc | 10318 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
10319 | || (S_GET_VALUE (sym) != 0 |
10320 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10321 | change = 0; | |
10322 | else | |
10323 | { | |
10324 | const char *segname; | |
d8a1c247 | 10325 | |
1dc1e798 KR |
10326 | segname = segment_name (S_GET_SEGMENT (sym)); |
10327 | assert (strcmp (segname, ".lit8") != 0 | |
10328 | && strcmp (segname, ".lit4") != 0); | |
10329 | change = (strcmp (segname, ".sdata") != 0 | |
10330 | && strcmp (segname, ".sbss") != 0); | |
10331 | } | |
10332 | return change; | |
10333 | } | |
10334 | else | |
10335 | /* We are not optimizing for the GP register. */ | |
10336 | return 1; | |
d8a1c247 KR |
10337 | } |
10338 | ||
cc5703cd ILT |
10339 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
10340 | extended opcode. SEC is the section the frag is in. */ | |
10341 | ||
10342 | static int | |
10343 | mips16_extended_frag (fragp, sec, stretch) | |
10344 | fragS *fragp; | |
10345 | asection *sec; | |
10346 | long stretch; | |
10347 | { | |
10348 | int type; | |
10349 | register const struct mips16_immed_operand *op; | |
10350 | offsetT val; | |
10351 | int mintiny, maxtiny; | |
f74ba7a3 | 10352 | segT symsec; |
cc5703cd | 10353 | |
8728fa92 ILT |
10354 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
10355 | return 0; | |
10356 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10357 | return 1; | |
10358 | ||
cc5703cd ILT |
10359 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
10360 | op = mips16_immed_operands; | |
10361 | while (op->type != type) | |
10362 | { | |
10363 | ++op; | |
10364 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10365 | } | |
10366 | ||
10367 | if (op->unsp) | |
10368 | { | |
10369 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10370 | { | |
10371 | mintiny = 1; | |
10372 | maxtiny = 1 << op->nbits; | |
10373 | } | |
10374 | else | |
10375 | { | |
10376 | mintiny = 0; | |
10377 | maxtiny = (1 << op->nbits) - 1; | |
10378 | } | |
10379 | } | |
10380 | else | |
10381 | { | |
10382 | mintiny = - (1 << (op->nbits - 1)); | |
10383 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10384 | } | |
10385 | ||
f74ba7a3 ILT |
10386 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
10387 | a particular frag address. */ | |
10388 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
10389 | { | |
10390 | val = (fragp->fr_symbol->sy_value.X_add_number | |
10391 | + fragp->fr_symbol->sy_frag->fr_address); | |
10392 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
10393 | } | |
10394 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
10395 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
10396 | == O_constant)) | |
10397 | { | |
10398 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
10399 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
10400 | + fragp->fr_symbol->sy_value.X_add_number | |
10401 | + fragp->fr_symbol->sy_frag->fr_address); | |
10402 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
10403 | } | |
10404 | else | |
10405 | return 1; | |
cc5703cd ILT |
10406 | |
10407 | if (op->pcrel) | |
10408 | { | |
10409 | addressT addr; | |
10410 | ||
10411 | /* We won't have the section when we are called from | |
10412 | mips_relax_frag. However, we will always have been called | |
10413 | from md_estimate_size_before_relax first. If this is a | |
10414 | branch to a different section, we mark it as such. If SEC is | |
10415 | NULL, and the frag is not marked, then it must be a branch to | |
10416 | the same section. */ | |
10417 | if (sec == NULL) | |
10418 | { | |
10419 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10420 | return 1; | |
10421 | } | |
10422 | else | |
10423 | { | |
f74ba7a3 | 10424 | if (symsec != sec) |
cc5703cd ILT |
10425 | { |
10426 | fragp->fr_subtype = | |
10427 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10428 | ||
10429 | /* FIXME: We should support this, and let the linker | |
10430 | catch branches and loads that are out of range. */ | |
10431 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10432 | "unsupported PC relative reference to different section"); | |
10433 | ||
10434 | return 1; | |
10435 | } | |
10436 | } | |
10437 | ||
10438 | /* In this case, we know for sure that the symbol fragment is in | |
10439 | the same section. If the fr_address of the symbol fragment | |
10440 | is greater then the address of this fragment we want to add | |
10441 | in STRETCH in order to get a better estimate of the address. | |
10442 | This particularly matters because of the shift bits. */ | |
10443 | if (stretch != 0 | |
10444 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
10445 | { | |
10446 | fragS *f; | |
10447 | ||
a941619c ILT |
10448 | /* Adjust stretch for any alignment frag. Note that if have |
10449 | been expanding the earlier code, the symbol may be | |
10450 | defined in what appears to be an earlier frag. FIXME: | |
10451 | This doesn't handle the fr_subtype field, which specifies | |
10452 | a maximum number of bytes to skip when doing an | |
10453 | alignment. */ | |
10454 | for (f = fragp; | |
10455 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
10456 | f = f->fr_next) | |
cc5703cd | 10457 | { |
cc5703cd ILT |
10458 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
10459 | { | |
10460 | if (stretch < 0) | |
10461 | stretch = - ((- stretch) | |
10462 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10463 | else | |
10464 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10465 | if (stretch == 0) | |
10466 | break; | |
10467 | } | |
10468 | } | |
a941619c ILT |
10469 | if (f != NULL) |
10470 | val += stretch; | |
cc5703cd ILT |
10471 | } |
10472 | ||
a677feeb ILT |
10473 | addr = fragp->fr_address + fragp->fr_fix; |
10474 | ||
10475 | /* The base address rules are complicated. The base address of | |
10476 | a branch is the following instruction. The base address of a | |
10477 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
10478 | is in a delay slot (in which case it can not be extended) use |
10479 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 10480 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
10481 | { |
10482 | addr += 2; | |
319305a7 ILT |
10483 | |
10484 | /* If we are currently assuming that this frag should be | |
10485 | extended, then, the current address is two bytes | |
10486 | higher. */ | |
10487 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10488 | addr += 2; | |
10489 | ||
fbcfacb7 ILT |
10490 | /* Ignore the low bit in the target, since it will be set |
10491 | for a text label. */ | |
10492 | if ((val & 1) != 0) | |
10493 | --val; | |
10494 | } | |
a677feeb ILT |
10495 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10496 | addr -= 4; | |
10497 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10498 | addr -= 2; | |
cc5703cd | 10499 | |
cc5703cd ILT |
10500 | val -= addr & ~ ((1 << op->shift) - 1); |
10501 | ||
10502 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10503 | if (type == 'p' || type == 'q') | |
10504 | val /= 2; | |
10505 | ||
10506 | /* If any of the shifted bits are set, we must use an extended | |
10507 | opcode. If the address depends on the size of this | |
10508 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
10509 | use an extended opcode. We only check this when we are in |
10510 | the main relaxation loop, when SEC is NULL. */ | |
10511 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10512 | { | |
10513 | fragp->fr_subtype = | |
10514 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10515 | return 1; | |
10516 | } | |
10517 | ||
10518 | /* If we are about to mark a frag as extended because the value | |
10519 | is precisely maxtiny + 1, then there is a chance of an | |
10520 | infinite loop as in the following code: | |
10521 | la $4,foo | |
10522 | .skip 1020 | |
10523 | .align 2 | |
10524 | foo: | |
10525 | In this case when the la is extended, foo is 0x3fc bytes | |
10526 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10527 | the la must be extended. To avoid this loop, we mark the | |
10528 | frag as extended if it was small, and is about to become | |
10529 | extended with a value of maxtiny + 1. */ | |
10530 | if (val == ((maxtiny + 1) << op->shift) | |
10531 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10532 | && sec == NULL) | |
cc5703cd ILT |
10533 | { |
10534 | fragp->fr_subtype = | |
10535 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10536 | return 1; | |
10537 | } | |
10538 | } | |
41a0ed22 ILT |
10539 | else if (symsec != absolute_section && sec != NULL) |
10540 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
10541 | |
10542 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10543 | || val < (mintiny << op->shift) | |
10544 | || val > (maxtiny << op->shift)) | |
10545 | return 1; | |
10546 | else | |
10547 | return 0; | |
10548 | } | |
10549 | ||
10550 | /* Estimate the size of a frag before relaxing. Unless this is the | |
10551 | mips16, we are not really relaxing here, and the final size is | |
10552 | encoded in the subtype information. For the mips16, we have to | |
10553 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 10554 | |
0dd2d296 ILT |
10555 | /*ARGSUSED*/ |
10556 | int | |
10557 | md_estimate_size_before_relax (fragp, segtype) | |
10558 | fragS *fragp; | |
10559 | asection *segtype; | |
10560 | { | |
10561 | int change; | |
10562 | ||
cc5703cd ILT |
10563 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10564 | { | |
10565 | if (mips16_extended_frag (fragp, segtype, 0)) | |
10566 | { | |
10567 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10568 | return 4; | |
10569 | } | |
10570 | else | |
10571 | { | |
10572 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10573 | return 2; | |
10574 | } | |
10575 | } | |
10576 | ||
d9aba805 | 10577 | if (mips_pic == NO_PIC) |
0dd2d296 | 10578 | { |
85ce5635 | 10579 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 10580 | } |
d9aba805 | 10581 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10582 | { |
46a92fde ILT |
10583 | symbolS *sym; |
10584 | asection *symsec; | |
10585 | ||
10586 | sym = fragp->fr_symbol; | |
10587 | ||
10588 | /* Handle the case of a symbol equated to another symbol. */ | |
10589 | while (sym->sy_value.X_op == O_symbol | |
10590 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
10591 | { | |
10592 | symbolS *n; | |
10593 | ||
10594 | /* It's possible to get a loop here in a badly written | |
10595 | program. */ | |
10596 | n = sym->sy_value.X_add_symbol; | |
10597 | if (n == sym) | |
10598 | break; | |
10599 | sym = n; | |
10600 | } | |
10601 | ||
10602 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
10603 | |
10604 | /* This must duplicate the test in adjust_reloc_syms. */ | |
10605 | change = (symsec != &bfd_und_section | |
10606 | && symsec != &bfd_abs_section | |
10607 | && ! bfd_is_com_section (symsec)); | |
10608 | } | |
d9aba805 ILT |
10609 | else |
10610 | abort (); | |
0dd2d296 ILT |
10611 | |
10612 | if (change) | |
10613 | { | |
10614 | /* Record the offset to the first reloc in the fr_opcode field. | |
10615 | This lets md_convert_frag and tc_gen_reloc know that the code | |
10616 | must be expanded. */ | |
10617 | fragp->fr_opcode = (fragp->fr_literal | |
10618 | + fragp->fr_fix | |
10619 | - RELAX_OLD (fragp->fr_subtype) | |
10620 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
10621 | /* FIXME: This really needs as_warn_where. */ | |
10622 | if (RELAX_WARN (fragp->fr_subtype)) | |
10623 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
10624 | } | |
10625 | ||
10626 | if (! change) | |
10627 | return 0; | |
10628 | else | |
10629 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
10630 | } | |
10631 | ||
0d7f9025 ILT |
10632 | /* This is called to see whether a reloc against a defined symbol |
10633 | should be converted into a reloc against a section. Don't adjust | |
10634 | MIPS16 jump relocations, so we don't have to worry about the format | |
10635 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
10636 | mips16 symbols, so that the linker can find them if it needs to set |
10637 | up a stub. */ | |
0d7f9025 ILT |
10638 | |
10639 | int | |
10640 | mips_fix_adjustable (fixp) | |
10641 | fixS *fixp; | |
10642 | { | |
10643 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
10644 | return 0; | |
10645 | if (fixp->fx_addsy == NULL) | |
10646 | return 1; | |
68952421 | 10647 | #ifdef OBJ_ELF |
0d7f9025 | 10648 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
10649 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
10650 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
10651 | return 0; |
10652 | #endif | |
10653 | return 1; | |
10654 | } | |
10655 | ||
0dd2d296 ILT |
10656 | /* Translate internal representation of relocation info to BFD target |
10657 | format. */ | |
10658 | ||
10659 | arelent ** | |
3d3c5039 ILT |
10660 | tc_gen_reloc (section, fixp) |
10661 | asection *section; | |
10662 | fixS *fixp; | |
10663 | { | |
0dd2d296 | 10664 | static arelent *retval[4]; |
3d3c5039 | 10665 | arelent *reloc; |
a8aed9dd | 10666 | bfd_reloc_code_real_type code; |
3d3c5039 | 10667 | |
0dd2d296 ILT |
10668 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
10669 | retval[1] = NULL; | |
3d3c5039 ILT |
10670 | |
10671 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10672 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
10673 | |
10674 | if (mips_pic == EMBEDDED_PIC | |
10675 | && SWITCH_TABLE (fixp)) | |
10676 | { | |
10677 | /* For a switch table entry we use a special reloc. The addend | |
10678 | is actually the difference between the reloc address and the | |
10679 | subtrahend. */ | |
10680 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
10681 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
10682 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
10683 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
10684 | } | |
ecd4ca1c ILT |
10685 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
10686 | { | |
10687 | /* We use a special addend for an internal RELLO reloc. */ | |
10688 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10689 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
10690 | else | |
10691 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
10692 | } | |
10693 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
10694 | { | |
10695 | assert (fixp->fx_next != NULL | |
10696 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
10697 | /* We use a special addend for an internal RELHI reloc. The | |
10698 | reloc is relative to the RELLO; adjust the addend | |
10699 | accordingly. */ | |
10700 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10701 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
10702 | + fixp->fx_next->fx_where | |
10703 | - S_GET_VALUE (fixp->fx_subsy)); | |
10704 | else | |
10705 | reloc->addend = (fixp->fx_addnumber | |
10706 | + fixp->fx_next->fx_frag->fr_address | |
10707 | + fixp->fx_next->fx_where); | |
10708 | } | |
1c803e52 | 10709 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
10710 | reloc->addend = fixp->fx_addnumber; |
10711 | else | |
5b63f465 | 10712 | { |
1dc1e798 KR |
10713 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
10714 | /* A gruesome hack which is a result of the gruesome gas reloc | |
10715 | handling. */ | |
10716 | reloc->addend = reloc->address; | |
10717 | else | |
10718 | reloc->addend = -reloc->address; | |
5b63f465 | 10719 | } |
0dd2d296 ILT |
10720 | |
10721 | /* If this is a variant frag, we may need to adjust the existing | |
10722 | reloc and generate a new one. */ | |
10723 | if (fixp->fx_frag->fr_opcode != NULL | |
10724 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
10725 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
10726 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
10727 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10728 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
10729 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10730 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
10731 | { |
10732 | arelent *reloc2; | |
10733 | ||
cc5703cd ILT |
10734 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
10735 | ||
0dd2d296 | 10736 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
10737 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
10738 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
10739 | the second one handle all of them. */ | |
0dd2d296 ILT |
10740 | if (fixp->fx_next != NULL |
10741 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
10742 | { | |
fb251650 ILT |
10743 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
10744 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
10745 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10746 | && (fixp->fx_next->fx_r_type | |
10747 | == BFD_RELOC_MIPS_GOT_LO16)) | |
10748 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10749 | && (fixp->fx_next->fx_r_type | |
10750 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
10751 | retval[0] = NULL; |
10752 | return retval; | |
10753 | } | |
10754 | ||
10755 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
10756 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10757 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
10758 | retval[2] = NULL; | |
10759 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10760 | reloc2->address = (reloc->address | |
10761 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
10762 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
10763 | reloc2->addend = fixp->fx_addnumber; | |
10764 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
10765 | assert (reloc2->howto != NULL); | |
10766 | ||
10767 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
10768 | { | |
10769 | arelent *reloc3; | |
10770 | ||
10771 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
10772 | retval[3] = NULL; | |
10773 | *reloc3 = *reloc2; | |
10774 | reloc3->address += 4; | |
10775 | } | |
10776 | ||
d9aba805 | 10777 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
10778 | { |
10779 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
10780 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
10781 | } | |
d9aba805 | 10782 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10783 | { |
fb251650 | 10784 | switch (fixp->fx_r_type) |
0dd2d296 | 10785 | { |
fb251650 ILT |
10786 | default: |
10787 | abort (); | |
10788 | case BFD_RELOC_MIPS_GOT16: | |
10789 | break; | |
10790 | case BFD_RELOC_MIPS_CALL16: | |
10791 | case BFD_RELOC_MIPS_GOT_LO16: | |
10792 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 10793 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 10794 | break; |
0dd2d296 ILT |
10795 | } |
10796 | } | |
d9aba805 ILT |
10797 | else |
10798 | abort (); | |
0dd2d296 ILT |
10799 | } |
10800 | ||
a8aed9dd ILT |
10801 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
10802 | fixup_segment converted a non-PC relative reloc into a PC | |
10803 | relative reloc. In such a case, we need to convert the reloc | |
10804 | code. */ | |
10805 | code = fixp->fx_r_type; | |
10806 | if (fixp->fx_pcrel) | |
10807 | { | |
10808 | switch (code) | |
10809 | { | |
10810 | case BFD_RELOC_8: | |
10811 | code = BFD_RELOC_8_PCREL; | |
10812 | break; | |
10813 | case BFD_RELOC_16: | |
10814 | code = BFD_RELOC_16_PCREL; | |
10815 | break; | |
10816 | case BFD_RELOC_32: | |
10817 | code = BFD_RELOC_32_PCREL; | |
10818 | break; | |
bf39474f ILT |
10819 | case BFD_RELOC_64: |
10820 | code = BFD_RELOC_64_PCREL; | |
10821 | break; | |
a8aed9dd ILT |
10822 | case BFD_RELOC_8_PCREL: |
10823 | case BFD_RELOC_16_PCREL: | |
10824 | case BFD_RELOC_32_PCREL: | |
bf39474f | 10825 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 10826 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
10827 | case BFD_RELOC_PCREL_HI16_S: |
10828 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
10829 | break; |
10830 | default: | |
10831 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10832 | "Cannot make %s relocation PC relative", | |
10833 | bfd_get_reloc_code_name (code)); | |
10834 | } | |
10835 | } | |
10836 | ||
d9aba805 ILT |
10837 | /* To support a PC relative reloc when generating embedded PIC code |
10838 | for ECOFF, we use a Cygnus extension. We check for that here to | |
10839 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 10840 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 10841 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
10842 | && mips_pic != EMBEDDED_PIC) |
10843 | reloc->howto = NULL; | |
10844 | else | |
a8aed9dd | 10845 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 10846 | |
52aa70b5 JW |
10847 | if (reloc->howto == NULL) |
10848 | { | |
10849 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
10850 | "Can not represent %s relocation in this object file format", |
10851 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 10852 | retval[0] = NULL; |
52aa70b5 | 10853 | } |
3d3c5039 | 10854 | |
0dd2d296 | 10855 | return retval; |
3d3c5039 ILT |
10856 | } |
10857 | ||
cc5703cd ILT |
10858 | /* Relax a machine dependent frag. This returns the amount by which |
10859 | the current size of the frag should change. */ | |
10860 | ||
10861 | int | |
10862 | mips_relax_frag (fragp, stretch) | |
10863 | fragS *fragp; | |
10864 | long stretch; | |
10865 | { | |
10866 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
10867 | return 0; | |
10868 | ||
10869 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
10870 | { | |
10871 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10872 | return 0; | |
10873 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10874 | return 2; | |
10875 | } | |
10876 | else | |
10877 | { | |
10878 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10879 | return 0; | |
10880 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10881 | return -2; | |
10882 | } | |
10883 | ||
10884 | return 0; | |
10885 | } | |
10886 | ||
0dd2d296 ILT |
10887 | /* Convert a machine dependent frag. */ |
10888 | ||
10889 | void | |
10890 | md_convert_frag (abfd, asec, fragp) | |
10891 | bfd *abfd; | |
10892 | segT asec; | |
10893 | fragS *fragp; | |
3d3c5039 | 10894 | { |
0dd2d296 ILT |
10895 | int old, new; |
10896 | char *fixptr; | |
3d3c5039 | 10897 | |
cc5703cd ILT |
10898 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10899 | { | |
10900 | int type; | |
10901 | register const struct mips16_immed_operand *op; | |
10902 | boolean small, ext; | |
10903 | offsetT val; | |
10904 | bfd_byte *buf; | |
10905 | unsigned long insn; | |
10906 | boolean use_extend; | |
10907 | unsigned short extend; | |
10908 | ||
10909 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10910 | op = mips16_immed_operands; | |
10911 | while (op->type != type) | |
10912 | ++op; | |
10913 | ||
10914 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10915 | { | |
10916 | small = false; | |
10917 | ext = true; | |
10918 | } | |
10919 | else | |
10920 | { | |
10921 | small = true; | |
10922 | ext = false; | |
10923 | } | |
10924 | ||
b637f306 | 10925 | resolve_symbol_value (fragp->fr_symbol, 1); |
cc5703cd | 10926 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
10927 | if (op->pcrel) |
10928 | { | |
10929 | addressT addr; | |
10930 | ||
a677feeb ILT |
10931 | addr = fragp->fr_address + fragp->fr_fix; |
10932 | ||
10933 | /* The rules for the base address of a PC relative reloc are | |
10934 | complicated; see mips16_extended_frag. */ | |
10935 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
10936 | { |
10937 | addr += 2; | |
319305a7 ILT |
10938 | if (ext) |
10939 | addr += 2; | |
fbcfacb7 ILT |
10940 | /* Ignore the low bit in the target, since it will be |
10941 | set for a text label. */ | |
10942 | if ((val & 1) != 0) | |
10943 | --val; | |
10944 | } | |
a677feeb ILT |
10945 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10946 | addr -= 4; | |
10947 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10948 | addr -= 2; | |
10949 | ||
cc5703cd ILT |
10950 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
10951 | val -= addr; | |
a677feeb ILT |
10952 | |
10953 | /* Make sure the section winds up with the alignment we have | |
10954 | assumed. */ | |
10955 | if (op->shift > 0) | |
10956 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
10957 | } |
10958 | ||
035936da ILT |
10959 | if (ext |
10960 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
10961 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
10962 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
10963 | "extended instruction in delay slot"); | |
10964 | ||
cc5703cd ILT |
10965 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
10966 | ||
b9129c6f ILT |
10967 | if (target_big_endian) |
10968 | insn = bfd_getb16 (buf); | |
10969 | else | |
10970 | insn = bfd_getl16 (buf); | |
cc5703cd | 10971 | |
31a2c6ff ILT |
10972 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
10973 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
10974 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
10975 | |
10976 | if (use_extend) | |
10977 | { | |
10978 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
10979 | fragp->fr_fix += 2; | |
10980 | buf += 2; | |
10981 | } | |
3d3c5039 | 10982 | |
cc5703cd ILT |
10983 | md_number_to_chars (buf, insn, 2); |
10984 | fragp->fr_fix += 2; | |
10985 | buf += 2; | |
10986 | } | |
10987 | else | |
10988 | { | |
10989 | if (fragp->fr_opcode == NULL) | |
10990 | return; | |
0dd2d296 | 10991 | |
cc5703cd ILT |
10992 | old = RELAX_OLD (fragp->fr_subtype); |
10993 | new = RELAX_NEW (fragp->fr_subtype); | |
10994 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 10995 | |
cc5703cd ILT |
10996 | if (new > 0) |
10997 | memcpy (fixptr - old, fixptr, new); | |
10998 | ||
10999 | fragp->fr_fix += new - old; | |
11000 | } | |
0dd2d296 | 11001 | } |
becfe05e | 11002 | |
fbcfacb7 ILT |
11003 | #ifdef OBJ_ELF |
11004 | ||
11005 | /* This function is called after the relocs have been generated. | |
11006 | We've been storing mips16 text labels as odd. Here we convert them | |
11007 | back to even for the convenience of the debugger. */ | |
11008 | ||
11009 | void | |
11010 | mips_frob_file_after_relocs () | |
11011 | { | |
11012 | asymbol **syms; | |
11013 | unsigned int count, i; | |
11014 | ||
11015 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11016 | return; | |
11017 | ||
11018 | syms = bfd_get_outsymbols (stdoutput); | |
11019 | count = bfd_get_symcount (stdoutput); | |
11020 | for (i = 0; i < count; i++, syms++) | |
11021 | { | |
11022 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11023 | && ((*syms)->value & 1) != 0) | |
11024 | { | |
11025 | (*syms)->value &= ~1; | |
11026 | /* If the symbol has an odd size, it was probably computed | |
11027 | incorrectly, so adjust that as well. */ | |
11028 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11029 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11030 | } | |
11031 | } | |
11032 | } | |
11033 | ||
11034 | #endif | |
11035 | ||
becfe05e ILT |
11036 | /* This function is called whenever a label is defined. It is used |
11037 | when handling branch delays; if a branch has a label, we assume we | |
11038 | can not move it. */ | |
11039 | ||
11040 | void | |
11041 | mips_define_label (sym) | |
11042 | symbolS *sym; | |
11043 | { | |
fbcfacb7 ILT |
11044 | struct insn_label_list *l; |
11045 | ||
11046 | if (free_insn_labels == NULL) | |
11047 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11048 | else | |
11049 | { | |
11050 | l = free_insn_labels; | |
11051 | free_insn_labels = l->next; | |
11052 | } | |
11053 | ||
11054 | l->label = sym; | |
11055 | l->next = insn_labels; | |
11056 | insn_labels = l; | |
becfe05e | 11057 | } |
3d3c5039 | 11058 | \f |
739708fa | 11059 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 11060 | |
0dd2d296 | 11061 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
11062 | |
11063 | void | |
11064 | mips_elf_final_processing () | |
11065 | { | |
87178180 ILT |
11066 | /* Write out the register information. */ |
11067 | if (! mips_64) | |
11068 | { | |
11069 | Elf32_RegInfo s; | |
11070 | ||
11071 | s.ri_gprmask = mips_gprmask; | |
11072 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11073 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11074 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11075 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11076 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11077 | ||
11078 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11079 | ((Elf32_External_RegInfo *) | |
11080 | mips_regmask_frag)); | |
11081 | } | |
11082 | else | |
11083 | { | |
11084 | Elf64_Internal_RegInfo s; | |
11085 | ||
11086 | s.ri_gprmask = mips_gprmask; | |
11087 | s.ri_pad = 0; | |
11088 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11089 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11090 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11091 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11092 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11093 | ||
11094 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11095 | ((Elf64_External_RegInfo *) | |
11096 | mips_regmask_frag)); | |
11097 | } | |
0dd2d296 ILT |
11098 | |
11099 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11100 | sort of BFD interface for this. */ | |
11101 | if (mips_any_noreorder) | |
11102 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 11103 | if (mips_pic != NO_PIC) |
0dd2d296 | 11104 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
11105 | } |
11106 | ||
739708fa | 11107 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 11108 | \f |
3d3c5039 ILT |
11109 | /* These functions should really be defined by the object file format, |
11110 | since they are related to debugging information. However, this | |
11111 | code has to work for the a.out format, which does not define them, | |
11112 | so we provide simple versions here. These don't actually generate | |
11113 | any debugging information, but they do simple checking and someday | |
11114 | somebody may make them useful. */ | |
11115 | ||
670a50eb ILT |
11116 | typedef struct loc |
11117 | { | |
11118 | struct loc *loc_next; | |
11119 | unsigned long loc_fileno; | |
11120 | unsigned long loc_lineno; | |
11121 | unsigned long loc_offset; | |
11122 | unsigned short loc_delta; | |
11123 | unsigned short loc_count; | |
3d3c5039 | 11124 | #if 0 |
670a50eb | 11125 | fragS *loc_frag; |
3d3c5039 | 11126 | #endif |
670a50eb ILT |
11127 | } |
11128 | locS; | |
3d3c5039 | 11129 | |
670a50eb ILT |
11130 | typedef struct proc |
11131 | { | |
3d3c5039 ILT |
11132 | struct proc *proc_next; |
11133 | struct symbol *proc_isym; | |
11134 | struct symbol *proc_end; | |
11135 | unsigned long proc_reg_mask; | |
11136 | unsigned long proc_reg_offset; | |
11137 | unsigned long proc_fpreg_mask; | |
11138 | unsigned long proc_fpreg_offset; | |
11139 | unsigned long proc_frameoffset; | |
11140 | unsigned long proc_framereg; | |
11141 | unsigned long proc_pcreg; | |
11142 | locS *proc_iline; | |
11143 | struct file *proc_file; | |
11144 | int proc_index; | |
670a50eb ILT |
11145 | } |
11146 | procS; | |
3d3c5039 | 11147 | |
670a50eb ILT |
11148 | typedef struct file |
11149 | { | |
3d3c5039 ILT |
11150 | struct file *file_next; |
11151 | unsigned long file_fileno; | |
11152 | struct symbol *file_symbol; | |
11153 | struct symbol *file_end; | |
11154 | struct proc *file_proc; | |
11155 | int file_numprocs; | |
670a50eb ILT |
11156 | } |
11157 | fileS; | |
3d3c5039 ILT |
11158 | |
11159 | static struct obstack proc_frags; | |
11160 | static procS *proc_lastP; | |
11161 | static procS *proc_rootP; | |
11162 | static int numprocs; | |
11163 | ||
11164 | static void | |
11165 | md_obj_begin () | |
11166 | { | |
670a50eb | 11167 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
11168 | } |
11169 | ||
11170 | static void | |
11171 | md_obj_end () | |
11172 | { | |
11173 | /* check for premature end, nesting errors, etc */ | |
11174 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 11175 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
11176 | } |
11177 | ||
3d3c5039 ILT |
11178 | static long |
11179 | get_number () | |
11180 | { | |
670a50eb ILT |
11181 | int negative = 0; |
11182 | long val = 0; | |
3d3c5039 | 11183 | |
670a50eb ILT |
11184 | if (*input_line_pointer == '-') |
11185 | { | |
11186 | ++input_line_pointer; | |
11187 | negative = 1; | |
3d3c5039 | 11188 | } |
670a50eb ILT |
11189 | if (!isdigit (*input_line_pointer)) |
11190 | as_bad ("Expected simple number."); | |
11191 | if (input_line_pointer[0] == '0') | |
11192 | { | |
11193 | if (input_line_pointer[1] == 'x') | |
11194 | { | |
11195 | input_line_pointer += 2; | |
11196 | while (isxdigit (*input_line_pointer)) | |
11197 | { | |
11198 | val <<= 4; | |
3a762a0b | 11199 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 11200 | } |
670a50eb ILT |
11201 | return negative ? -val : val; |
11202 | } | |
11203 | else | |
11204 | { | |
11205 | ++input_line_pointer; | |
11206 | while (isdigit (*input_line_pointer)) | |
11207 | { | |
11208 | val <<= 3; | |
11209 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 11210 | } |
670a50eb | 11211 | return negative ? -val : val; |
3d3c5039 ILT |
11212 | } |
11213 | } | |
670a50eb ILT |
11214 | if (!isdigit (*input_line_pointer)) |
11215 | { | |
11216 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
11217 | *input_line_pointer, *input_line_pointer); | |
11218 | as_warn ("Invalid number"); | |
11219 | return -1; | |
3d3c5039 | 11220 | } |
670a50eb ILT |
11221 | while (isdigit (*input_line_pointer)) |
11222 | { | |
11223 | val *= 10; | |
11224 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 11225 | } |
670a50eb | 11226 | return negative ? -val : val; |
3d3c5039 ILT |
11227 | } |
11228 | ||
11229 | /* The .file directive; just like the usual .file directive, but there | |
11230 | is an initial number which is the ECOFF file index. */ | |
11231 | ||
11232 | static void | |
11233 | s_file (x) | |
11234 | int x; | |
11235 | { | |
670a50eb | 11236 | int line; |
3d3c5039 | 11237 | |
670a50eb | 11238 | line = get_number (); |
9a7d824a | 11239 | s_app_file (0); |
3d3c5039 ILT |
11240 | } |
11241 | ||
11242 | ||
11243 | /* The .end directive. */ | |
11244 | ||
11245 | static void | |
11246 | s_mipsend (x) | |
11247 | int x; | |
11248 | { | |
670a50eb ILT |
11249 | symbolS *p; |
11250 | ||
11251 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11252 | { | |
11253 | p = get_symbol (); | |
11254 | demand_empty_rest_of_line (); | |
11255 | } | |
11256 | else | |
11257 | p = NULL; | |
11258 | if (now_seg != text_section) | |
11259 | as_warn (".end not in text section"); | |
11260 | if (!proc_lastP) | |
11261 | { | |
11262 | as_warn (".end and no .ent seen yet."); | |
11263 | return; | |
3d3c5039 ILT |
11264 | } |
11265 | ||
670a50eb ILT |
11266 | if (p != NULL) |
11267 | { | |
11268 | assert (S_GET_NAME (p)); | |
11269 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
11270 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
11271 | } |
11272 | ||
670a50eb | 11273 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
11274 | } |
11275 | ||
11276 | /* The .aent and .ent directives. */ | |
11277 | ||
11278 | static void | |
11279 | s_ent (aent) | |
11280 | int aent; | |
11281 | { | |
670a50eb ILT |
11282 | int number = 0; |
11283 | procS *procP; | |
11284 | symbolS *symbolP; | |
11285 | ||
11286 | symbolP = get_symbol (); | |
11287 | if (*input_line_pointer == ',') | |
11288 | input_line_pointer++; | |
dd3f1f76 | 11289 | SKIP_WHITESPACE (); |
670a50eb ILT |
11290 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
11291 | number = get_number (); | |
11292 | if (now_seg != text_section) | |
11293 | as_warn (".ent or .aent not in text section."); | |
11294 | ||
11295 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
11296 | as_warn ("missing `.end'"); | |
11297 | ||
11298 | if (!aent) | |
11299 | { | |
11300 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
11301 | procP->proc_isym = symbolP; | |
11302 | procP->proc_reg_mask = 0; | |
11303 | procP->proc_reg_offset = 0; | |
11304 | procP->proc_fpreg_mask = 0; | |
11305 | procP->proc_fpreg_offset = 0; | |
11306 | procP->proc_frameoffset = 0; | |
11307 | procP->proc_framereg = 0; | |
11308 | procP->proc_pcreg = 0; | |
11309 | procP->proc_end = NULL; | |
11310 | procP->proc_next = NULL; | |
11311 | if (proc_lastP) | |
11312 | proc_lastP->proc_next = procP; | |
11313 | else | |
11314 | proc_rootP = procP; | |
11315 | proc_lastP = procP; | |
11316 | numprocs++; | |
3d3c5039 | 11317 | } |
670a50eb | 11318 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
11319 | } |
11320 | ||
11321 | /* The .frame directive. */ | |
11322 | ||
88225433 | 11323 | #if 0 |
3d3c5039 ILT |
11324 | static void |
11325 | s_frame (x) | |
670a50eb | 11326 | int x; |
3d3c5039 | 11327 | { |
670a50eb ILT |
11328 | char str[100]; |
11329 | symbolS *symP; | |
11330 | int frame_reg; | |
11331 | int frame_off; | |
11332 | int pcreg; | |
11333 | ||
0dd2d296 | 11334 | frame_reg = tc_get_register (1); |
670a50eb ILT |
11335 | if (*input_line_pointer == ',') |
11336 | input_line_pointer++; | |
5ac34ac3 | 11337 | frame_off = get_absolute_expression (); |
670a50eb ILT |
11338 | if (*input_line_pointer == ',') |
11339 | input_line_pointer++; | |
0dd2d296 | 11340 | pcreg = tc_get_register (0); |
670a50eb ILT |
11341 | |
11342 | /* bob third eye */ | |
11343 | assert (proc_rootP); | |
11344 | proc_rootP->proc_framereg = frame_reg; | |
11345 | proc_rootP->proc_frameoffset = frame_off; | |
11346 | proc_rootP->proc_pcreg = pcreg; | |
11347 | /* bob macho .frame */ | |
11348 | ||
11349 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 11350 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
11351 | { |
11352 | if (!proc_lastP) | |
11353 | as_warn ("No .ent for .frame to use."); | |
11354 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
11355 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
11356 | S_SET_TYPE (symP, N_RMASK); | |
11357 | S_SET_OTHER (symP, 0); | |
11358 | S_SET_DESC (symP, 0); | |
11359 | symP->sy_forward = proc_lastP->proc_isym; | |
11360 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11361 | } |
670a50eb | 11362 | demand_empty_rest_of_line (); |
3d3c5039 | 11363 | } |
88225433 | 11364 | #endif |
3d3c5039 ILT |
11365 | |
11366 | /* The .fmask and .mask directives. */ | |
11367 | ||
88225433 | 11368 | #if 0 |
3d3c5039 ILT |
11369 | static void |
11370 | s_mask (reg_type) | |
11371 | char reg_type; | |
11372 | { | |
670a50eb ILT |
11373 | char str[100], *strP; |
11374 | symbolS *symP; | |
11375 | int i; | |
11376 | unsigned int mask; | |
11377 | int off; | |
11378 | ||
11379 | mask = get_number (); | |
11380 | if (*input_line_pointer == ',') | |
11381 | input_line_pointer++; | |
11382 | off = get_absolute_expression (); | |
11383 | ||
11384 | /* bob only for coff */ | |
11385 | assert (proc_rootP); | |
11386 | if (reg_type == 'F') | |
11387 | { | |
11388 | proc_rootP->proc_fpreg_mask = mask; | |
11389 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 11390 | } |
670a50eb ILT |
11391 | else |
11392 | { | |
11393 | proc_rootP->proc_reg_mask = mask; | |
11394 | proc_rootP->proc_reg_offset = off; | |
11395 | } | |
11396 | ||
11397 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 11398 | |
670a50eb ILT |
11399 | /* We don't have to write out a mask stab if no saved regs. */ |
11400 | if (!(mask == 0)) | |
11401 | { | |
11402 | if (!proc_lastP) | |
11403 | as_warn ("No .ent for .mask to use."); | |
11404 | strP = str; | |
11405 | for (i = 0; i < 32; i++) | |
11406 | { | |
11407 | if (mask % 2) | |
11408 | { | |
11409 | sprintf (strP, "%c%d,", reg_type, i); | |
11410 | strP += strlen (strP); | |
11411 | } | |
3d3c5039 | 11412 | mask /= 2; |
670a50eb ILT |
11413 | } |
11414 | sprintf (strP, ";%d,", off); | |
11415 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
11416 | S_SET_TYPE (symP, N_RMASK); | |
11417 | S_SET_OTHER (symP, 0); | |
11418 | S_SET_DESC (symP, 0); | |
11419 | symP->sy_forward = proc_lastP->proc_isym; | |
11420 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11421 | } |
3d3c5039 | 11422 | } |
88225433 | 11423 | #endif |
3d3c5039 ILT |
11424 | |
11425 | /* The .loc directive. */ | |
11426 | ||
88225433 | 11427 | #if 0 |
3d3c5039 ILT |
11428 | static void |
11429 | s_loc (x) | |
11430 | int x; | |
11431 | { | |
670a50eb ILT |
11432 | symbolS *symbolP; |
11433 | int lineno; | |
11434 | int addroff; | |
3d3c5039 | 11435 | |
670a50eb | 11436 | assert (now_seg == text_section); |
3d3c5039 | 11437 | |
670a50eb | 11438 | lineno = get_number (); |
87e48495 | 11439 | addroff = frag_now_fix (); |
3d3c5039 | 11440 | |
670a50eb ILT |
11441 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
11442 | S_SET_TYPE (symbolP, N_SLINE); | |
11443 | S_SET_OTHER (symbolP, 0); | |
11444 | S_SET_DESC (symbolP, lineno); | |
11445 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 11446 | } |
88225433 | 11447 | #endif |