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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
fb251650 | 2 | Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
3d3c5039 | 39 | |
739708fa KR |
40 | #ifdef OBJ_MAYBE_ELF |
41 | /* Clean up namespace so we can include obj-elf.h too. */ | |
42 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
43 | #undef OBJ_PROCESS_STAB | |
44 | #undef OUTPUT_FLAVOR | |
45 | #undef S_GET_ALIGN | |
46 | #undef S_GET_SIZE | |
47 | #undef S_SET_ALIGN | |
48 | #undef S_SET_SIZE | |
49 | #undef TARGET_SYMBOL_FIELDS | |
50 | #undef obj_frob_file | |
cc5703cd | 51 | #undef obj_frob_file_after_relocs |
739708fa KR |
52 | #undef obj_frob_symbol |
53 | #undef obj_pop_insert | |
54 | #undef obj_sec_sym_ok_for_reloc | |
55 | ||
56 | #include "obj-elf.h" | |
57 | /* Fix any of them that we actually care about. */ | |
58 | #undef OUTPUT_FLAVOR | |
59 | #define OUTPUT_FLAVOR mips_output_flavor() | |
60 | #endif | |
61 | ||
62 | #if defined (OBJ_ELF) | |
f2a663d3 | 63 | #include "elf/mips.h" |
1dc1e798 | 64 | #endif |
f2a663d3 | 65 | |
739708fa | 66 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 67 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
68 | #define ECOFF_DEBUGGING 0 |
69 | #endif | |
70 | ||
22ba90ce ILT |
71 | #include "ecoff.h" |
72 | ||
a8aed9dd | 73 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 74 | static char *mips_regmask_frag; |
a8aed9dd | 75 | #endif |
f2a663d3 | 76 | |
3d3c5039 | 77 | #define AT 1 |
cc5703cd | 78 | #define TREG 24 |
9226253a | 79 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
80 | #define KT0 26 |
81 | #define KT1 27 | |
670a50eb | 82 | #define GP 28 |
9226253a ILT |
83 | #define SP 29 |
84 | #define FP 30 | |
3d3c5039 ILT |
85 | #define RA 31 |
86 | ||
cc5703cd ILT |
87 | #define ILLEGAL_REG (32) |
88 | ||
1dc1e798 | 89 | extern int target_big_endian; |
88225433 | 90 | |
7f9880e5 ILT |
91 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
92 | 32 bit ABI. This has no meaning for ECOFF. */ | |
93 | static int mips_64; | |
94 | ||
04cb3372 | 95 | /* The default target format to use. */ |
1dc1e798 KR |
96 | const char * |
97 | mips_target_format () | |
98 | { | |
99 | switch (OUTPUT_FLAVOR) | |
100 | { | |
101 | case bfd_target_aout_flavour: | |
102 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
103 | case bfd_target_ecoff_flavour: | |
104 | return target_big_endian ? "ecoff-bigmips" : "ecoff-littlemips"; | |
105 | case bfd_target_elf_flavour: | |
7f9880e5 ILT |
106 | return (target_big_endian |
107 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
108 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
109 | default: |
110 | abort (); | |
111 | } | |
112 | } | |
04cb3372 | 113 | |
d2c71068 | 114 | /* The name of the readonly data section. */ |
1dc1e798 KR |
115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
116 | ? ".data" \ | |
117 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
118 | ? ".rdata" \ | |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
d2c71068 | 122 | |
1aa6938e ILT |
123 | /* These variables are filled in with the masks of registers used. |
124 | The object format code reads them and puts them in the appropriate | |
125 | place. */ | |
126 | unsigned long mips_gprmask; | |
127 | unsigned long mips_cprmask[4]; | |
128 | ||
1051c97f ILT |
129 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
130 | temporarily using .set mipsN). */ | |
8358c818 ILT |
131 | static int mips_isa = -1; |
132 | ||
1051c97f ILT |
133 | /* MIPS ISA we are using for this output file. */ |
134 | static int file_mips_isa; | |
135 | ||
cc5703cd ILT |
136 | /* Whether we are assembling for the mips16 processor. */ |
137 | static int mips16 = -1; | |
138 | ||
8c63448a | 139 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 140 | static int mips_cpu = -1; |
8c63448a | 141 | |
b2b8c24e ILT |
142 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
143 | static int mips_4650 = -1; | |
144 | ||
e532b44c ILT |
145 | /* Whether the 4010 instructions are permitted. */ |
146 | static int mips_4010 = -1; | |
147 | ||
c625fc23 JSC |
148 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
149 | static int mips_4100 = -1; | |
150 | ||
e532b44c ILT |
151 | /* Whether the processor uses hardware interlocks, and thus does not |
152 | require nops to be inserted. */ | |
153 | static int interlocks = -1; | |
154 | ||
344a8d61 JSC |
155 | /* As with "interlocks" this is used by hardware that has FP |
156 | (co-processor) interlocks. */ | |
157 | static int cop_interlocks = -1; | |
158 | ||
d9aba805 ILT |
159 | /* MIPS PIC level. */ |
160 | ||
161 | enum mips_pic_level | |
162 | { | |
163 | /* Do not generate PIC code. */ | |
164 | NO_PIC, | |
165 | ||
166 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
167 | not sure what it is supposed to do. */ | |
168 | IRIX4_PIC, | |
169 | ||
170 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
171 | SVR4_PIC, | |
172 | ||
173 | /* Generate PIC code without using a global offset table: the data | |
174 | segment has a maximum size of 64K, all data references are off | |
175 | the $gp register, and all text references are PC relative. This | |
176 | is used on some embedded systems. */ | |
177 | EMBEDDED_PIC | |
178 | }; | |
179 | ||
180 | static enum mips_pic_level mips_pic; | |
9226253a | 181 | |
fb251650 ILT |
182 | /* 1 if we should generate 32 bit offsets from the GP register in |
183 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
184 | static int mips_big_got; | |
185 | ||
8ea7f4e8 ILT |
186 | /* 1 if trap instructions should used for overflow rather than break |
187 | instructions. */ | |
188 | static int mips_trap; | |
189 | ||
cc5703cd ILT |
190 | /* 1 if we should autoextend mips16 instructions. */ |
191 | static int mips16_autoextend = 1; | |
192 | ||
3d3c5039 ILT |
193 | static int mips_warn_about_macros; |
194 | static int mips_noreorder; | |
0dd2d296 | 195 | static int mips_any_noreorder; |
3d3c5039 ILT |
196 | static int mips_nomove; |
197 | static int mips_noat; | |
198 | static int mips_nobopt; | |
199 | ||
670a50eb ILT |
200 | /* The size of the small data section. */ |
201 | static int g_switch_value = 8; | |
42562568 ILT |
202 | /* Whether the -G option was used. */ |
203 | static int g_switch_seen = 0; | |
670a50eb | 204 | |
3d3c5039 ILT |
205 | #define N_RMASK 0xc4 |
206 | #define N_VFP 0xd4 | |
207 | ||
d8a1c247 KR |
208 | /* If we can determine in advance that GP optimization won't be |
209 | possible, we can skip the relaxation stuff that tries to produce | |
210 | GP-relative references. This makes delay slot optimization work | |
211 | better. | |
212 | ||
213 | This function can only provide a guess, but it seems to work for | |
214 | gcc output. If it guesses wrong, the only loss should be in | |
215 | efficiency; it shouldn't introduce any bugs. | |
216 | ||
217 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
218 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
219 | static int nopic_need_relax PARAMS ((symbolS *)); | |
220 | ||
3d3c5039 ILT |
221 | /* handle of the OPCODE hash table */ |
222 | static struct hash_control *op_hash = NULL; | |
223 | ||
cc5703cd ILT |
224 | /* The opcode hash table we use for the mips16. */ |
225 | static struct hash_control *mips16_op_hash = NULL; | |
226 | ||
3d3c5039 ILT |
227 | /* This array holds the chars that always start a comment. If the |
228 | pre-processor is disabled, these aren't very useful */ | |
229 | const char comment_chars[] = "#"; | |
230 | ||
231 | /* This array holds the chars that only start a comment at the beginning of | |
232 | a line. If the line seems to have the form '# 123 filename' | |
233 | .line and .file directives will appear in the pre-processed output */ | |
234 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
235 | first line of the input file. This is because the compiler outputs | |
236 | #NO_APP at the beginning of its output. */ | |
237 | /* Also note that C style comments are always supported. */ | |
238 | const char line_comment_chars[] = "#"; | |
239 | ||
240 | /* This array holds machine specific line separator characters. */ | |
241 | const char line_separator_chars[] = ""; | |
242 | ||
243 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
244 | const char EXP_CHARS[] = "eE"; | |
245 | ||
246 | /* Chars that mean this number is a floating point constant */ | |
247 | /* As in 0f12.456 */ | |
248 | /* or 0d1.2345e12 */ | |
249 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
250 | ||
251 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
252 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
253 | but nothing is ideal around here. | |
254 | */ | |
255 | ||
670a50eb | 256 | static char *insn_error; |
3d3c5039 | 257 | |
22ba90ce | 258 | static int byte_order; |
3d3c5039 ILT |
259 | |
260 | static int auto_align = 1; | |
becfe05e | 261 | |
9226253a ILT |
262 | /* When outputting SVR4 PIC code, the assembler needs to know the |
263 | offset in the stack frame from which to restore the $gp register. | |
264 | This is set by the .cprestore pseudo-op, and saved in this | |
265 | variable. */ | |
0dd2d296 ILT |
266 | static offsetT mips_cprestore_offset = -1; |
267 | ||
268 | /* This is the register which holds the stack frame, as set by the | |
269 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
270 | static int mips_frame_reg = SP; | |
9226253a | 271 | |
becfe05e ILT |
272 | /* To output NOP instructions correctly, we need to keep information |
273 | about the previous two instructions. */ | |
274 | ||
0aa07269 ILT |
275 | /* Whether we are optimizing. The default value of 2 means to remove |
276 | unneeded NOPs and swap branch instructions when possible. A value | |
277 | of 1 means to not swap branches. A value of 0 means to always | |
278 | insert NOPs. */ | |
279 | static int mips_optimize = 2; | |
4e95866e | 280 | |
22ba90ce ILT |
281 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
282 | equivalent to seeing no -g option at all. */ | |
283 | static int mips_debug = 0; | |
284 | ||
becfe05e ILT |
285 | /* The previous instruction. */ |
286 | static struct mips_cl_insn prev_insn; | |
287 | ||
288 | /* The instruction before prev_insn. */ | |
289 | static struct mips_cl_insn prev_prev_insn; | |
290 | ||
291 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
292 | point the insn_mo field at this dummy integer. */ | |
293 | static const struct mips_opcode dummy_opcode = { 0 }; | |
294 | ||
295 | /* Non-zero if prev_insn is valid. */ | |
296 | static int prev_insn_valid; | |
297 | ||
298 | /* The frag for the previous instruction. */ | |
299 | static struct frag *prev_insn_frag; | |
300 | ||
301 | /* The offset into prev_insn_frag for the previous instruction. */ | |
302 | static long prev_insn_where; | |
303 | ||
a677feeb ILT |
304 | /* The reloc type for the previous instruction, if any. */ |
305 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
306 | ||
becfe05e ILT |
307 | /* The reloc for the previous instruction, if any. */ |
308 | static fixS *prev_insn_fixp; | |
309 | ||
310 | /* Non-zero if the previous instruction was in a delay slot. */ | |
311 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
312 | |
313 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
314 | static int prev_insn_unreordered; | |
315 | ||
cc5703cd ILT |
316 | /* Non-zero if the previous instruction uses an extend opcode (if |
317 | mips16). */ | |
318 | static int prev_insn_extended; | |
319 | ||
4e95866e ILT |
320 | /* Non-zero if the previous previous instruction was in a .set |
321 | noreorder. */ | |
322 | static int prev_prev_insn_unreordered; | |
867a58b3 ILT |
323 | |
324 | /* For ECOFF and ELF, relocations against symbols are done in two | |
325 | parts, with a HI relocation and a LO relocation. Each relocation | |
326 | has only 16 bits of space to store an addend. This means that in | |
327 | order for the linker to handle carries correctly, it must be able | |
328 | to locate both the HI and the LO relocation. This means that the | |
329 | relocations must appear in order in the relocation table. | |
330 | ||
331 | In order to implement this, we keep track of each unmatched HI | |
332 | relocation. We then sort them so that they immediately precede the | |
333 | corresponding LO relocation. */ | |
334 | ||
335 | struct mips_hi_fixup | |
336 | { | |
337 | /* Next HI fixup. */ | |
338 | struct mips_hi_fixup *next; | |
339 | /* This fixup. */ | |
340 | fixS *fixp; | |
341 | /* The section this fixup is in. */ | |
342 | segT seg; | |
343 | }; | |
344 | ||
345 | /* The list of unmatched HI relocs. */ | |
346 | ||
347 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
348 | |
349 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
350 | ||
351 | #define X ILLEGAL_REG | |
352 | static const int mips32_to_16_reg_map[] = | |
353 | { | |
354 | X, X, 2, 3, 4, 5, 6, 7, | |
355 | X, X, X, X, X, X, X, X, | |
356 | 0, 1, X, X, X, X, X, X, | |
357 | X, X, X, X, X, X, X, X | |
358 | }; | |
359 | #undef X | |
360 | ||
361 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
362 | ||
363 | static const int mips16_to_32_reg_map[] = | |
364 | { | |
365 | 16, 17, 2, 3, 4, 5, 6, 7 | |
366 | }; | |
3d3c5039 | 367 | \f |
0dd2d296 ILT |
368 | /* Since the MIPS does not have multiple forms of PC relative |
369 | instructions, we do not have to do relaxing as is done on other | |
370 | platforms. However, we do have to handle GP relative addressing | |
371 | correctly, which turns out to be a similar problem. | |
372 | ||
373 | Every macro that refers to a symbol can occur in (at least) two | |
374 | forms, one with GP relative addressing and one without. For | |
375 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 376 | a macro instruction like this: |
0dd2d296 ILT |
377 | lw $4,i |
378 | If i can be addressed off the GP register (this is true if it is in | |
379 | the .sbss or .sdata section, or if it is known to be smaller than | |
380 | the -G argument) this will generate the following instruction: | |
381 | lw $4,i($gp) | |
382 | This instruction will use a GPREL reloc. If i can not be addressed | |
383 | off the GP register, the following instruction sequence will be used: | |
384 | lui $at,i | |
385 | lw $4,i($at) | |
386 | In this case the first instruction will have a HI16 reloc, and the | |
387 | second reloc will have a LO16 reloc. Both relocs will be against | |
388 | the symbol i. | |
389 | ||
390 | The issue here is that we may not know whether i is GP addressable | |
391 | until after we see the instruction that uses it. Therefore, we | |
392 | want to be able to choose the final instruction sequence only at | |
393 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 394 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
395 | end of assembly. |
396 | ||
397 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
398 | addressing in quite the same way, but the issue still arises as |
399 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
400 | |
401 | We handle these issues by actually generating both possible | |
402 | instruction sequences. The longer one is put in a frag_var with | |
403 | type rs_machine_dependent. We encode what to do with the frag in | |
404 | the subtype field. We encode (1) the number of existing bytes to | |
405 | replace, (2) the number of new bytes to use, (3) the offset from | |
406 | the start of the existing bytes to the first reloc we must generate | |
407 | (that is, the offset is applied from the start of the existing | |
408 | bytes after they are replaced by the new bytes, if any), (4) the | |
409 | offset from the start of the existing bytes to the second reloc, | |
410 | (5) whether a third reloc is needed (the third reloc is always four | |
411 | bytes after the second reloc), and (6) whether to warn if this | |
412 | variant is used (this is sometimes needed if .set nomacro or .set | |
413 | noat is in effect). All these numbers are reasonably small. | |
414 | ||
415 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
416 | ensure that delay slots are handled correctly. Fortunately, there |
417 | are a limited number of cases. When the second instruction | |
418 | sequence is generated, append_insn is directed to maintain the | |
419 | existing delay slot information, so it continues to apply to any | |
420 | code after the second instruction sequence. This means that the | |
421 | second instruction sequence must not impose any requirements not | |
422 | required by the first instruction sequence. | |
0dd2d296 ILT |
423 | |
424 | These variant frags are then handled in functions called by the | |
425 | machine independent code. md_estimate_size_before_relax returns | |
426 | the final size of the frag. md_convert_frag sets up the final form | |
427 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
428 | one if needed. */ | |
429 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
430 | ((relax_substateT) \ | |
cc5703cd | 431 | (((old) << 23) \ |
0dd2d296 ILT |
432 | | ((new) << 16) \ |
433 | | (((reloc1) + 64) << 9) \ | |
434 | | (((reloc2) + 64) << 2) \ | |
435 | | ((reloc3) ? (1 << 1) : 0) \ | |
436 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
437 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
438 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
439 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
440 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
441 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
442 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
443 | |
444 | /* For mips16 code, we use an entirely different form of relaxation. | |
445 | mips16 supports two versions of most instructions which take | |
446 | immediate values: a small one which takes some small value, and a | |
447 | larger one which takes a 16 bit value. Since branches also follow | |
448 | this pattern, relaxing these values is required. | |
449 | ||
450 | We can assemble both mips16 and normal MIPS code in a single | |
451 | object. Therefore, we need to support this type of relaxation at | |
452 | the same time that we support the relaxation described above. We | |
453 | use the high bit of the subtype field to distinguish these cases. | |
454 | ||
a677feeb ILT |
455 | The information we store for this type of relaxation is the |
456 | argument code found in the opcode file for this relocation, whether | |
457 | the user explicitly requested a small or extended form, and whether | |
458 | the relocation is in a jump or jal delay slot. That tells us the | |
459 | size of the value, and how it should be stored. We also store | |
460 | whether the fragment is considered to be extended or not. We also | |
461 | store whether this is known to be a branch to a different section, | |
462 | whether we have tried to relax this frag yet, and whether we have | |
463 | ever extended a PC relative fragment because of a shift count. */ | |
464 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
465 | (0x80000000 \ | |
466 | | ((type) & 0xff) \ | |
467 | | ((small) ? 0x100 : 0) \ | |
468 | | ((ext) ? 0x200 : 0) \ | |
469 | | ((dslot) ? 0x400 : 0) \ | |
470 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
471 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
472 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
473 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
474 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
475 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
476 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
477 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
478 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
479 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
480 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
481 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
482 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 483 | \f |
3d3c5039 ILT |
484 | /* Prototypes for static functions. */ |
485 | ||
486 | #ifdef __STDC__ | |
487 | #define internalError() \ | |
488 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
489 | #else | |
490 | #define internalError() as_fatal ("MIPS internal Error"); | |
491 | #endif | |
492 | ||
cc5703cd ILT |
493 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
494 | ||
becfe05e | 495 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 496 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 497 | static int reg_needs_delay PARAMS ((int)); |
0dd2d296 ILT |
498 | static void append_insn PARAMS ((char *place, |
499 | struct mips_cl_insn * ip, | |
670a50eb | 500 | expressionS * p, |
867a58b3 ILT |
501 | bfd_reloc_code_real_type r, |
502 | boolean)); | |
becfe05e | 503 | static void mips_no_prev_insn PARAMS ((void)); |
fbcfacb7 | 504 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 505 | #ifdef USE_STDARG |
0dd2d296 | 506 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
507 | const char *name, const char *fmt, |
508 | ...)); | |
c625fc23 JSC |
509 | #else |
510 | static void macro_build (); | |
511 | #endif | |
cc5703cd ILT |
512 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
513 | const char *, const char *, | |
514 | va_list)); | |
0dd2d296 ILT |
515 | static void macro_build_lui PARAMS ((char *place, int *counter, |
516 | expressionS * ep, int regnum)); | |
6e8dda9c | 517 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 518 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 519 | expressionS *)); |
d8a1c247 | 520 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 521 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 522 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 523 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
524 | #ifdef LOSING_COMPILER |
525 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
526 | #endif | |
670a50eb | 527 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 528 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
529 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
530 | boolean, boolean, unsigned long *, | |
531 | boolean *, unsigned short *)); | |
670a50eb ILT |
532 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
533 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 534 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 535 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
536 | static void s_align PARAMS ((int)); |
537 | static void s_change_sec PARAMS ((int)); | |
538 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 539 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 540 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
541 | static void s_option PARAMS ((int)); |
542 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
543 | static void s_abicalls PARAMS ((int)); |
544 | static void s_cpload PARAMS ((int)); | |
545 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
546 | static void s_gpword PARAMS ((int)); |
547 | static void s_cpadd PARAMS ((int)); | |
3d3c5039 ILT |
548 | static void md_obj_begin PARAMS ((void)); |
549 | static void md_obj_end PARAMS ((void)); | |
550 | static long get_number PARAMS ((void)); | |
551 | static void s_ent PARAMS ((int)); | |
552 | static void s_mipsend PARAMS ((int)); | |
553 | static void s_file PARAMS ((int)); | |
cc5703cd | 554 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
555 | \f |
556 | /* Pseudo-op table. | |
557 | ||
558 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
559 | should be defined here, but are currently unsupported: .alias, | |
560 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
561 | ||
562 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
563 | specific to the type of debugging information being generated, and | |
564 | should be defined by the object format: .aent, .begin, .bend, | |
565 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
566 | .vreg. | |
567 | ||
568 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
569 | not MIPS CPU specific, but are also not specific to the object file | |
570 | format. This file is probably the best place to define them, but | |
571 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
572 | .struct, .weakext. */ | |
573 | ||
739708fa | 574 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 575 | { |
670a50eb ILT |
576 | /* MIPS specific pseudo-ops. */ |
577 | {"option", s_option, 0}, | |
578 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
579 | {"rdata", s_change_sec, 'r'}, |
580 | {"sdata", s_change_sec, 's'}, | |
581 | {"livereg", s_ignore, 0}, | |
739708fa KR |
582 | {"abicalls", s_abicalls, 0}, |
583 | {"cpload", s_cpload, 0}, | |
584 | {"cprestore", s_cprestore, 0}, | |
585 | {"gpword", s_gpword, 0}, | |
586 | {"cpadd", s_cpadd, 0}, | |
3d3c5039 | 587 | |
670a50eb | 588 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 589 | chips. */ |
739708fa | 590 | {"asciiz", stringer, 1}, |
670a50eb ILT |
591 | {"bss", s_change_sec, 'b'}, |
592 | {"err", s_err, 0}, | |
593 | {"half", s_cons, 1}, | |
52aa70b5 | 594 | {"dword", s_cons, 3}, |
3d3c5039 | 595 | |
670a50eb | 596 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 597 | here for one reason or another. */ |
670a50eb ILT |
598 | {"align", s_align, 0}, |
599 | {"byte", s_cons, 0}, | |
600 | {"data", s_change_sec, 'd'}, | |
becfe05e | 601 | {"double", s_float_cons, 'd'}, |
becfe05e | 602 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
603 | {"globl", s_mips_globl, 0}, |
604 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
605 | {"hword", s_cons, 1}, |
606 | {"int", s_cons, 2}, | |
607 | {"long", s_cons, 2}, | |
608 | {"octa", s_cons, 4}, | |
609 | {"quad", s_cons, 3}, | |
610 | {"short", s_cons, 1}, | |
611 | {"single", s_float_cons, 'f'}, | |
670a50eb ILT |
612 | {"text", s_change_sec, 't'}, |
613 | {"word", s_cons, 2}, | |
739708fa KR |
614 | { 0 }, |
615 | }; | |
3d3c5039 | 616 | |
739708fa | 617 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 618 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 619 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 620 | {"aent", s_ent, 1}, |
9226253a | 621 | {"bgnb", s_ignore, 0}, |
670a50eb | 622 | {"end", s_mipsend, 0}, |
9226253a | 623 | {"endb", s_ignore, 0}, |
670a50eb ILT |
624 | {"ent", s_ent, 0}, |
625 | {"file", s_file, 0}, | |
626 | {"fmask", s_ignore, 'F'}, | |
627 | {"frame", s_ignore, 0}, | |
628 | {"loc", s_ignore, 0}, | |
629 | {"mask", s_ignore, 'R'}, | |
630 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
631 | { 0 }, |
632 | }; | |
61420a20 | 633 | |
739708fa KR |
634 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
635 | ||
636 | void | |
637 | mips_pop_insert () | |
638 | { | |
639 | pop_insert (mips_pseudo_table); | |
640 | if (! ECOFF_DEBUGGING) | |
641 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 642 | } |
3d3c5039 | 643 | \f |
fbcfacb7 ILT |
644 | /* Symbols labelling the current insn. */ |
645 | ||
646 | struct insn_label_list | |
647 | { | |
648 | struct insn_label_list *next; | |
649 | symbolS *label; | |
650 | }; | |
651 | ||
652 | static struct insn_label_list *insn_labels; | |
653 | static struct insn_label_list *free_insn_labels; | |
654 | ||
655 | static void mips_clear_insn_labels PARAMS ((void)); | |
656 | ||
657 | static inline void | |
658 | mips_clear_insn_labels () | |
659 | { | |
660 | register struct insn_label_list **pl; | |
661 | ||
662 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
663 | ; | |
664 | *pl = insn_labels; | |
665 | insn_labels = NULL; | |
666 | } | |
667 | \f | |
3d3c5039 ILT |
668 | static char *expr_end; |
669 | ||
867a58b3 ILT |
670 | /* Expressions which appear in instructions. These are set by |
671 | mips_ip. */ | |
672 | ||
3d3c5039 ILT |
673 | static expressionS imm_expr; |
674 | static expressionS offset_expr; | |
867a58b3 ILT |
675 | |
676 | /* Relocs associated with imm_expr and offset_expr. */ | |
677 | ||
3d3c5039 ILT |
678 | static bfd_reloc_code_real_type imm_reloc; |
679 | static bfd_reloc_code_real_type offset_reloc; | |
680 | ||
867a58b3 ILT |
681 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
682 | ||
683 | static boolean imm_unmatched_hi; | |
684 | ||
8728fa92 ILT |
685 | /* These are set by mips16_ip if an explicit extension is used. */ |
686 | ||
687 | static boolean mips16_small, mips16_ext; | |
688 | ||
3d3c5039 ILT |
689 | /* |
690 | * This function is called once, at assembler startup time. It should | |
691 | * set up all the tables, etc. that the MD part of the assembler will need. | |
692 | */ | |
693 | void | |
670a50eb | 694 | md_begin () |
3d3c5039 | 695 | { |
0dd2d296 | 696 | boolean ok = false; |
604633ae | 697 | register const char *retval = NULL; |
670a50eb | 698 | register unsigned int i = 0; |
3d3c5039 | 699 | |
8358c818 ILT |
700 | if (mips_isa == -1) |
701 | { | |
8c63448a ILT |
702 | const char *cpu; |
703 | char *a = NULL; | |
704 | ||
705 | cpu = TARGET_CPU; | |
706 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
707 | { | |
708 | a = xmalloc (sizeof TARGET_CPU); | |
709 | strcpy (a, TARGET_CPU); | |
710 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
711 | cpu = a; | |
712 | } | |
713 | ||
714 | if (strcmp (cpu, "mips") == 0) | |
715 | { | |
716 | mips_isa = 1; | |
4bb0cc41 ILT |
717 | if (mips_cpu == -1) |
718 | mips_cpu = 3000; | |
8c63448a ILT |
719 | } |
720 | else if (strcmp (cpu, "r6000") == 0 | |
721 | || strcmp (cpu, "mips2") == 0) | |
722 | { | |
723 | mips_isa = 2; | |
4bb0cc41 ILT |
724 | if (mips_cpu == -1) |
725 | mips_cpu = 6000; | |
8c63448a ILT |
726 | } |
727 | else if (strcmp (cpu, "mips64") == 0 | |
728 | || strcmp (cpu, "r4000") == 0 | |
729 | || strcmp (cpu, "mips3") == 0) | |
730 | { | |
731 | mips_isa = 3; | |
4bb0cc41 ILT |
732 | if (mips_cpu == -1) |
733 | mips_cpu = 4000; | |
8c63448a ILT |
734 | } |
735 | else if (strcmp (cpu, "r4400") == 0) | |
736 | { | |
737 | mips_isa = 3; | |
4bb0cc41 ILT |
738 | if (mips_cpu == -1) |
739 | mips_cpu = 4400; | |
8c63448a ILT |
740 | } |
741 | else if (strcmp (cpu, "mips64orion") == 0 | |
742 | || strcmp (cpu, "r4600") == 0) | |
743 | { | |
744 | mips_isa = 3; | |
4bb0cc41 ILT |
745 | if (mips_cpu == -1) |
746 | mips_cpu = 4600; | |
8c63448a | 747 | } |
b2b8c24e ILT |
748 | else if (strcmp (cpu, "r4650") == 0) |
749 | { | |
750 | mips_isa = 3; | |
751 | if (mips_cpu == -1) | |
752 | mips_cpu = 4650; | |
753 | if (mips_4650 == -1) | |
754 | mips_4650 = 1; | |
755 | } | |
c625fc23 JSC |
756 | else if (strcmp (cpu, "mips64vr4300") == 0) |
757 | { | |
758 | mips_isa = 3; | |
759 | if (mips_cpu == -1) | |
760 | mips_cpu = 4300; | |
761 | } | |
762 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
763 | { | |
764 | mips_isa = 3; | |
765 | if (mips_cpu == -1) | |
766 | mips_cpu = 4100; | |
767 | if (mips_4100 == -1) | |
768 | mips_4100 = 1; | |
769 | } | |
e532b44c ILT |
770 | else if (strcmp (cpu, "r4010") == 0) |
771 | { | |
772 | mips_isa = 2; | |
773 | if (mips_cpu == -1) | |
774 | mips_cpu = 4010; | |
775 | if (mips_4010 == -1) | |
776 | mips_4010 = 1; | |
777 | } | |
517078c1 ILT |
778 | else if (strcmp (cpu, "r5000") == 0 |
779 | || strcmp (cpu, "mips64vr5000") == 0) | |
780 | { | |
781 | mips_isa = 4; | |
782 | if (mips_cpu == -1) | |
783 | mips_cpu = 5000; | |
784 | } | |
d8a1c247 KR |
785 | else if (strcmp (cpu, "r8000") == 0 |
786 | || strcmp (cpu, "mips4") == 0) | |
787 | { | |
788 | mips_isa = 4; | |
789 | if (mips_cpu == -1) | |
790 | mips_cpu = 8000; | |
791 | } | |
792 | else if (strcmp (cpu, "r10000") == 0) | |
793 | { | |
794 | mips_isa = 4; | |
795 | if (mips_cpu == -1) | |
796 | mips_cpu = 10000; | |
797 | } | |
cc5703cd ILT |
798 | else if (strcmp (cpu, "mips16") == 0) |
799 | { | |
800 | mips_isa = 3; | |
801 | if (mips_cpu == -1) | |
802 | mips_cpu = 0; /* FIXME */ | |
803 | } | |
8358c818 | 804 | else |
8c63448a ILT |
805 | { |
806 | mips_isa = 1; | |
4bb0cc41 ILT |
807 | if (mips_cpu == -1) |
808 | mips_cpu = 3000; | |
8c63448a ILT |
809 | } |
810 | ||
811 | if (a != NULL) | |
812 | free (a); | |
8358c818 ILT |
813 | } |
814 | ||
cc5703cd ILT |
815 | if (mips16 < 0) |
816 | { | |
817 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
818 | mips16 = 1; | |
819 | else | |
820 | mips16 = 0; | |
821 | } | |
822 | ||
b2b8c24e ILT |
823 | if (mips_4650 < 0) |
824 | mips_4650 = 0; | |
825 | ||
e532b44c ILT |
826 | if (mips_4010 < 0) |
827 | mips_4010 = 0; | |
828 | ||
c625fc23 JSC |
829 | if (mips_4100 < 0) |
830 | mips_4100 = 0; | |
831 | ||
ca296aab | 832 | if (mips_4650 || mips_4010 || mips_4100 || mips_cpu == 4300) |
e532b44c ILT |
833 | interlocks = 1; |
834 | else | |
835 | interlocks = 0; | |
836 | ||
ca296aab | 837 | if (mips_cpu == 4300) |
344a8d61 JSC |
838 | cop_interlocks = 1; |
839 | else | |
840 | cop_interlocks = 0; | |
841 | ||
8ea7f4e8 ILT |
842 | if (mips_isa < 2 && mips_trap) |
843 | as_bad ("trap exception not supported at ISA 1"); | |
844 | ||
97f99d11 ILT |
845 | switch (mips_isa) |
846 | { | |
847 | case 1: | |
848 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
849 | break; | |
850 | case 2: | |
851 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
852 | break; | |
853 | case 3: | |
854 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
855 | break; | |
d8a1c247 KR |
856 | case 4: |
857 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
858 | break; | |
97f99d11 ILT |
859 | } |
860 | if (! ok) | |
861 | as_warn ("Could not set architecture and machine"); | |
862 | ||
1051c97f ILT |
863 | file_mips_isa = mips_isa; |
864 | ||
13fe1379 ILT |
865 | op_hash = hash_new (); |
866 | ||
670a50eb ILT |
867 | for (i = 0; i < NUMOPCODES;) |
868 | { | |
869 | const char *name = mips_opcodes[i].name; | |
870 | ||
604633ae | 871 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 872 | if (retval != NULL) |
670a50eb ILT |
873 | { |
874 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
875 | mips_opcodes[i].name, retval); | |
876 | as_fatal ("Broken assembler. No assembly attempted."); | |
877 | } | |
878 | do | |
879 | { | |
8358c818 ILT |
880 | if (mips_opcodes[i].pinfo != INSN_MACRO |
881 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
882 | != mips_opcodes[i].match)) | |
670a50eb ILT |
883 | { |
884 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
885 | mips_opcodes[i].name, mips_opcodes[i].args); | |
886 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 887 | } |
670a50eb ILT |
888 | ++i; |
889 | } | |
890 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
891 | } |
892 | ||
cc5703cd ILT |
893 | mips16_op_hash = hash_new (); |
894 | ||
895 | i = 0; | |
896 | while (i < bfd_mips16_num_opcodes) | |
897 | { | |
898 | const char *name = mips16_opcodes[i].name; | |
899 | ||
900 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
901 | if (retval != NULL) | |
902 | as_fatal ("internal error: can't hash `%s': %s\n", | |
903 | mips16_opcodes[i].name, retval); | |
904 | do | |
905 | { | |
906 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
907 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
908 | != mips16_opcodes[i].match)) | |
909 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
910 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
911 | ++i; | |
912 | } | |
913 | while (i < bfd_mips16_num_opcodes | |
914 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
915 | } | |
916 | ||
becfe05e ILT |
917 | mips_no_prev_insn (); |
918 | ||
1aa6938e ILT |
919 | mips_gprmask = 0; |
920 | mips_cprmask[0] = 0; | |
921 | mips_cprmask[1] = 0; | |
922 | mips_cprmask[2] = 0; | |
923 | mips_cprmask[3] = 0; | |
924 | ||
8358c818 | 925 | /* set the default alignment for the text section (2**2) */ |
08e17202 ILT |
926 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
927 | record_alignment (text_section, 2); | |
8358c818 | 928 | |
1dc1e798 KR |
929 | if (USE_GLOBAL_POINTER_OPT) |
930 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 931 | |
1dc1e798 KR |
932 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
933 | { | |
08e17202 ILT |
934 | /* On a native system, sections must be aligned to 16 byte |
935 | boundaries. When configured for an embedded ELF target, we | |
936 | don't bother. */ | |
937 | if (strcmp (TARGET_OS, "elf") != 0) | |
938 | { | |
939 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
940 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
941 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
942 | } | |
1dc1e798 KR |
943 | |
944 | /* Create a .reginfo section for register masks and a .mdebug | |
945 | section for debugging information. */ | |
946 | { | |
947 | segT seg; | |
948 | subsegT subseg; | |
949 | segT sec; | |
950 | ||
951 | seg = now_seg; | |
952 | subseg = now_subseg; | |
1dc1e798 | 953 | |
87178180 ILT |
954 | if (! mips_64) |
955 | { | |
956 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 957 | |
87178180 ILT |
958 | /* The ABI says this section should be loaded so that the |
959 | running program can access it. */ | |
960 | (void) bfd_set_section_flags (stdoutput, sec, | |
961 | (SEC_ALLOC | SEC_LOAD | |
962 | | SEC_READONLY | SEC_DATA)); | |
963 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
964 | ||
f2a663d3 | 965 | #ifdef OBJ_ELF |
87178180 | 966 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 967 | #endif |
87178180 ILT |
968 | } |
969 | else | |
970 | { | |
971 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
972 | .reginfo section. */ | |
973 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
974 | (void) bfd_set_section_flags (stdoutput, sec, | |
975 | (SEC_ALLOC | SEC_LOAD | |
976 | | SEC_READONLY | SEC_DATA)); | |
977 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
978 | ||
979 | #ifdef OBJ_ELF | |
980 | /* Set up the option header. */ | |
981 | { | |
982 | Elf_Internal_Options opthdr; | |
983 | char *f; | |
984 | ||
985 | opthdr.kind = ODK_REGINFO; | |
986 | opthdr.size = (sizeof (Elf_External_Options) | |
987 | + sizeof (Elf64_External_RegInfo)); | |
988 | opthdr.section = 0; | |
989 | opthdr.info = 0; | |
990 | f = frag_more (sizeof (Elf_External_Options)); | |
991 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
992 | (Elf_External_Options *) f); | |
993 | ||
994 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
995 | } | |
996 | #endif | |
997 | } | |
f2a663d3 | 998 | |
739708fa KR |
999 | if (ECOFF_DEBUGGING) |
1000 | { | |
1001 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1002 | (void) bfd_set_section_flags (stdoutput, sec, | |
1003 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1004 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1005 | } | |
0dd2d296 | 1006 | |
1dc1e798 KR |
1007 | subseg_set (seg, subseg); |
1008 | } | |
1009 | } | |
f2a663d3 | 1010 | |
739708fa KR |
1011 | if (! ECOFF_DEBUGGING) |
1012 | md_obj_begin (); | |
3d3c5039 ILT |
1013 | } |
1014 | ||
1015 | void | |
13fe1379 | 1016 | md_mips_end () |
3d3c5039 | 1017 | { |
739708fa KR |
1018 | if (! ECOFF_DEBUGGING) |
1019 | md_obj_end (); | |
3d3c5039 ILT |
1020 | } |
1021 | ||
1022 | void | |
670a50eb ILT |
1023 | md_assemble (str) |
1024 | char *str; | |
3d3c5039 | 1025 | { |
670a50eb | 1026 | struct mips_cl_insn insn; |
3d3c5039 | 1027 | |
5ac34ac3 | 1028 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1029 | imm_reloc = BFD_RELOC_UNUSED; |
1030 | imm_unmatched_hi = false; | |
5ac34ac3 | 1031 | offset_expr.X_op = O_absent; |
867a58b3 | 1032 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1033 | |
cc5703cd ILT |
1034 | if (mips16) |
1035 | mips16_ip (str, &insn); | |
1036 | else | |
1037 | mips_ip (str, &insn); | |
1038 | ||
670a50eb ILT |
1039 | if (insn_error) |
1040 | { | |
1041 | as_bad ("%s `%s'", insn_error, str); | |
1042 | return; | |
1043 | } | |
cc5703cd | 1044 | |
670a50eb ILT |
1045 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1046 | { | |
cc5703cd ILT |
1047 | if (mips16) |
1048 | mips16_macro (&insn); | |
1049 | else | |
1050 | macro (&insn); | |
3d3c5039 | 1051 | } |
670a50eb ILT |
1052 | else |
1053 | { | |
5ac34ac3 | 1054 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1055 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1056 | imm_unmatched_hi); | |
5ac34ac3 | 1057 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1058 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1059 | else |
867a58b3 | 1060 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1061 | } |
1062 | } | |
1063 | ||
cc5703cd ILT |
1064 | /* See whether instruction IP reads register REG. CLASS is the type |
1065 | of register. */ | |
becfe05e ILT |
1066 | |
1067 | static int | |
cc5703cd | 1068 | insn_uses_reg (ip, reg, class) |
becfe05e | 1069 | struct mips_cl_insn *ip; |
604633ae | 1070 | unsigned int reg; |
cc5703cd | 1071 | enum mips_regclass class; |
becfe05e | 1072 | { |
cc5703cd ILT |
1073 | if (class == MIPS16_REG) |
1074 | { | |
1075 | assert (mips16); | |
1076 | reg = mips16_to_32_reg_map[reg]; | |
1077 | class = MIPS_GR_REG; | |
1078 | } | |
1079 | ||
becfe05e | 1080 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1081 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1082 | return 0; |
1083 | ||
cc5703cd | 1084 | if (class == MIPS_FP_REG) |
becfe05e | 1085 | { |
cc5703cd | 1086 | assert (! mips16); |
becfe05e ILT |
1087 | /* If we are called with either $f0 or $f1, we must check $f0. |
1088 | This is not optimal, because it will introduce an unnecessary | |
1089 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1090 | need to distinguish reading both $f0 and $f1 or just one of | |
1091 | them. Note that we don't have to check the other way, | |
1092 | because there is no instruction that sets both $f0 and $f1 | |
1093 | and requires a delay. */ | |
1094 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
1095 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
1096 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1097 | return 1; |
1098 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
1099 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
1100 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
1101 | return 1; |
1102 | } | |
cc5703cd | 1103 | else if (! mips16) |
becfe05e ILT |
1104 | { |
1105 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1106 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1107 | return 1; | |
1108 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1109 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1110 | return 1; | |
1111 | } | |
cc5703cd ILT |
1112 | else |
1113 | { | |
1114 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1115 | && ((ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) == reg) | |
1116 | return 1; | |
1117 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1118 | && ((ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY) == reg) | |
1119 | return 1; | |
1120 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1121 | && ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1122 | & MIPS16OP_MASK_MOVE32Z) == reg) | |
1123 | return 1; | |
1124 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1125 | return 1; | |
1126 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1127 | return 1; | |
1128 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1129 | return 1; | |
1130 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1131 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1132 | & MIPS16OP_MASK_REGR32) == reg) | |
1133 | return 1; | |
1134 | } | |
becfe05e ILT |
1135 | |
1136 | return 0; | |
1137 | } | |
1138 | ||
fb251650 ILT |
1139 | /* This function returns true if modifying a register requires a |
1140 | delay. */ | |
1141 | ||
1142 | static int | |
1143 | reg_needs_delay (reg) | |
1144 | int reg; | |
1145 | { | |
1146 | unsigned long prev_pinfo; | |
1147 | ||
1148 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1149 | if (! mips_noreorder | |
1150 | && mips_isa < 4 | |
1151 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1152 | || (mips_isa < 2 | |
1153 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1154 | { | |
1155 | /* A load from a coprocessor or from memory. All load | |
1156 | delays delay the use of general register rt for one | |
1157 | instruction on the r3000. The r6000 and r4000 use | |
1158 | interlocks. */ | |
1159 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1160 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1161 | return 1; | |
1162 | } | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
0dd2d296 ILT |
1167 | /* Output an instruction. PLACE is where to put the instruction; if |
1168 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1169 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1170 | used with RELOC_TYPE. */ | |
3d3c5039 | 1171 | |
3d3c5039 | 1172 | static void |
867a58b3 | 1173 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1174 | char *place; |
670a50eb ILT |
1175 | struct mips_cl_insn *ip; |
1176 | expressionS *address_expr; | |
1177 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1178 | boolean unmatched_hi; |
3d3c5039 | 1179 | { |
1aa6938e | 1180 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1181 | char *f; |
becfe05e ILT |
1182 | fixS *fixp; |
1183 | int nops = 0; | |
3d3c5039 | 1184 | |
08e17202 ILT |
1185 | /* Make sure the section will be aligned appropriately. Note that |
1186 | we do not insert an alignment directive; it remains the user's | |
1187 | responsibility to align instructions if necessary. Here we only | |
1188 | ensure that the section will have the right default alignment, so | |
1189 | that the right thing will happen if no alignment directive is | |
1190 | used. */ | |
1191 | if (mips16) | |
1192 | record_alignment (now_seg, 1); | |
1193 | else | |
1194 | record_alignment (now_seg, 2); | |
1195 | ||
fbcfacb7 ILT |
1196 | /* Mark instruction labels in mips16 mode. This permits the linker |
1197 | to handle them specially, such as generating jalx instructions | |
1198 | when needed. We also make them odd for the duration of the | |
1199 | assembly, in order to generate the right sort of code. We will | |
1200 | make them even in the adjust_symtab routine, while leaving them | |
1201 | marked. This is convenient for the debugger and the | |
1202 | disassembler. The linker knows to make them odd again. */ | |
1203 | if (mips16) | |
1204 | { | |
1205 | struct insn_label_list *l; | |
1206 | ||
1207 | for (l = insn_labels; l != NULL; l = l->next) | |
1208 | { | |
1209 | #ifdef S_SET_OTHER | |
1210 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1211 | S_SET_OTHER (l->label, STO_MIPS16); | |
1212 | #endif | |
1213 | ++l->label->sy_value.X_add_number; | |
1214 | } | |
1215 | } | |
1216 | ||
1aa6938e ILT |
1217 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1218 | pinfo = ip->insn_mo->pinfo; | |
1219 | ||
0dd2d296 | 1220 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
1221 | { |
1222 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 1223 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1224 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1225 | (1) a load from memory delay |
1226 | (2) a load from a coprocessor delay | |
1227 | (3) an unconditional branch delay | |
1228 | (4) a conditional branch delay | |
1229 | (5) a move to coprocessor register delay | |
1230 | (6) a load coprocessor register from memory delay | |
1231 | (7) a coprocessor condition code delay | |
1232 | (8) a HI/LO special register delay | |
becfe05e ILT |
1233 | |
1234 | There are a lot of optimizations we could do that we don't. | |
1235 | In particular, we do not, in general, reorder instructions. | |
1236 | If you use gcc with optimization, it will reorder | |
1237 | instructions and generally do much more optimization then we | |
1238 | do here; repeating all that work in the assembler would only | |
1239 | benefit hand written assembly code, and does not seem worth | |
1240 | it. */ | |
1241 | ||
1242 | /* This is how a NOP is emitted. */ | |
cc5703cd ILT |
1243 | #define emit_nop() \ |
1244 | (mips16 \ | |
1245 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1246 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1247 | |
1248 | /* The previous insn might require a delay slot, depending upon | |
1249 | the contents of the current insn. */ | |
cc5703cd ILT |
1250 | if (! mips16 |
1251 | && mips_isa < 4 | |
5af96dce ILT |
1252 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1253 | && ! cop_interlocks) | |
d8a1c247 KR |
1254 | || (mips_isa < 2 |
1255 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
8358c818 ILT |
1256 | { |
1257 | /* A load from a coprocessor or from memory. All load | |
1258 | delays delay the use of general register rt for one | |
1259 | instruction on the r3000. The r6000 and r4000 use | |
1260 | interlocks. */ | |
1aa6938e | 1261 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1262 | if (mips_optimize == 0 |
1263 | || insn_uses_reg (ip, | |
1264 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1265 | & OP_MASK_RT), | |
cc5703cd | 1266 | MIPS_GR_REG)) |
becfe05e ILT |
1267 | ++nops; |
1268 | } | |
cc5703cd ILT |
1269 | else if (! mips16 |
1270 | && mips_isa < 4 | |
5af96dce ILT |
1271 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1272 | && ! cop_interlocks) | |
d8a1c247 KR |
1273 | || (mips_isa < 2 |
1274 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1275 | { |
1276 | /* A generic coprocessor delay. The previous instruction | |
1277 | modified a coprocessor general or control register. If | |
1278 | it modified a control register, we need to avoid any | |
1279 | coprocessor instruction (this is probably not always | |
1280 | required, but it sometimes is). If it modified a general | |
1281 | register, we avoid using that register. | |
1282 | ||
8358c818 ILT |
1283 | On the r6000 and r4000 loading a coprocessor register |
1284 | from memory is interlocked, and does not require a delay. | |
1285 | ||
becfe05e ILT |
1286 | This case is not handled very well. There is no special |
1287 | knowledge of CP0 handling, and the coprocessors other | |
1288 | than the floating point unit are not distinguished at | |
1289 | all. */ | |
1aa6938e | 1290 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1291 | { |
0aa07269 ILT |
1292 | if (mips_optimize == 0 |
1293 | || insn_uses_reg (ip, | |
8358c818 ILT |
1294 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1295 | & OP_MASK_FT), | |
cc5703cd | 1296 | MIPS_FP_REG)) |
becfe05e ILT |
1297 | ++nops; |
1298 | } | |
1aa6938e | 1299 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1300 | { |
0aa07269 ILT |
1301 | if (mips_optimize == 0 |
1302 | || insn_uses_reg (ip, | |
8358c818 ILT |
1303 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1304 | & OP_MASK_FS), | |
cc5703cd | 1305 | MIPS_FP_REG)) |
becfe05e ILT |
1306 | ++nops; |
1307 | } | |
1308 | else | |
1309 | { | |
1310 | /* We don't know exactly what the previous instruction | |
1311 | does. If the current instruction uses a coprocessor | |
1312 | register, we must insert a NOP. If previous | |
1313 | instruction may set the condition codes, and the | |
1314 | current instruction uses them, we must insert two | |
1315 | NOPS. */ | |
0aa07269 | 1316 | if (mips_optimize == 0 |
1aa6938e ILT |
1317 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1318 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1319 | nops += 2; |
1aa6938e | 1320 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1321 | ++nops; |
1322 | } | |
1323 | } | |
cc5703cd ILT |
1324 | else if (! mips16 |
1325 | && mips_isa < 4 | |
344a8d61 JSC |
1326 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1327 | && ! cop_interlocks) | |
becfe05e ILT |
1328 | { |
1329 | /* The previous instruction sets the coprocessor condition | |
1330 | codes, but does not require a general coprocessor delay | |
1331 | (this means it is a floating point comparison | |
1332 | instruction). If this instruction uses the condition | |
1333 | codes, we need to insert a single NOP. */ | |
0aa07269 | 1334 | if (mips_optimize == 0 |
1aa6938e | 1335 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1336 | ++nops; |
1337 | } | |
1aa6938e | 1338 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1339 | { |
1340 | /* The previous instruction reads the LO register; if the | |
1341 | current instruction writes to the LO register, we must | |
517078c1 | 1342 | insert two NOPS. Some newer processors have interlocks. */ |
e532b44c | 1343 | if (! interlocks |
b2b8c24e ILT |
1344 | && (mips_optimize == 0 |
1345 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1346 | nops += 2; |
1347 | } | |
1348 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1349 | { | |
1350 | /* The previous instruction reads the HI register; if the | |
1351 | current instruction writes to the HI register, we must | |
517078c1 | 1352 | insert a NOP. Some newer processors have interlocks. */ |
e532b44c | 1353 | if (! interlocks |
b2b8c24e ILT |
1354 | && (mips_optimize == 0 |
1355 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1356 | nops += 2; |
1357 | } | |
1358 | ||
1359 | /* There are two cases which require two intervening | |
1360 | instructions: 1) setting the condition codes using a move to | |
1361 | coprocessor instruction which requires a general coprocessor | |
1362 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1363 | or LO register and then writing to it (except on processors |
1364 | which have interlocks). If we are not already emitting a NOP | |
1365 | instruction, we must check for these cases compared to the | |
1366 | instruction previous to the previous instruction. */ | |
becfe05e | 1367 | if (nops == 0 |
cc5703cd ILT |
1368 | && ((! mips16 |
1369 | && mips_isa < 4 | |
d8a1c247 | 1370 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 1371 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
344a8d61 JSC |
1372 | && (pinfo & INSN_READ_COND_CODE) |
1373 | && ! cop_interlocks) | |
becfe05e | 1374 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
b2b8c24e | 1375 | && (pinfo & INSN_WRITE_LO) |
e532b44c | 1376 | && ! interlocks) |
becfe05e | 1377 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
b2b8c24e | 1378 | && (pinfo & INSN_WRITE_HI) |
e532b44c | 1379 | && ! interlocks))) |
becfe05e ILT |
1380 | ++nops; |
1381 | ||
0dd2d296 ILT |
1382 | /* If we are being given a nop instruction, don't bother with |
1383 | one of the nops we would otherwise output. This will only | |
1384 | happen when a nop instruction is used with mips_optimize set | |
1385 | to 0. */ | |
cc5703cd | 1386 | if (nops > 0 && ip->insn_opcode == (mips16 ? 0x6500 : 0)) |
0dd2d296 ILT |
1387 | --nops; |
1388 | ||
becfe05e ILT |
1389 | /* Now emit the right number of NOP instructions. */ |
1390 | if (nops > 0) | |
1391 | { | |
5af96dce ILT |
1392 | fragS *old_frag; |
1393 | unsigned long old_frag_offset; | |
8c63448a | 1394 | int i; |
fbcfacb7 | 1395 | struct insn_label_list *l; |
8c63448a | 1396 | |
5af96dce ILT |
1397 | old_frag = frag_now; |
1398 | old_frag_offset = frag_now_fix (); | |
1399 | ||
8c63448a | 1400 | for (i = 0; i < nops; i++) |
becfe05e | 1401 | emit_nop (); |
5af96dce | 1402 | |
af255ca0 | 1403 | if (listing) |
546f5536 ILT |
1404 | { |
1405 | listing_prev_line (); | |
1406 | /* We may be at the start of a variant frag. In case we | |
1407 | are, make sure there is enough space for the frag | |
1408 | after the frags created by listing_prev_line. The | |
1409 | argument to frag_grow here must be at least as large | |
1410 | as the argument to all other calls to frag_grow in | |
1411 | this file. We don't have to worry about being in the | |
1412 | middle of a variant frag, because the variants insert | |
1413 | all needed nop instructions themselves. */ | |
1414 | frag_grow (40); | |
1415 | } | |
5af96dce | 1416 | |
fbcfacb7 | 1417 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1418 | { |
fbcfacb7 ILT |
1419 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1420 | l->label->sy_frag = frag_now; | |
1421 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1422 | /* mips16 text labels are stored as odd. */ | |
1423 | if (mips16) | |
1424 | ++l->label->sy_value.X_add_number; | |
becfe05e | 1425 | } |
5af96dce ILT |
1426 | |
1427 | #ifndef NO_ECOFF_DEBUGGING | |
1428 | if (ECOFF_DEBUGGING) | |
1429 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1430 | #endif | |
becfe05e ILT |
1431 | } |
1432 | } | |
1433 | ||
cc5703cd ILT |
1434 | if (reloc_type > BFD_RELOC_UNUSED) |
1435 | { | |
1436 | /* We need to set up a variant frag. */ | |
1437 | assert (mips16 && address_expr != NULL); | |
1438 | f = frag_var (rs_machine_dependent, 4, 0, | |
8728fa92 | 1439 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1440 | mips16_small, mips16_ext, |
1441 | (prev_pinfo | |
1442 | & INSN_UNCOND_BRANCH_DELAY), | |
1443 | (prev_insn_reloc_type | |
1444 | == BFD_RELOC_MIPS16_JMP)), | |
cc5703cd ILT |
1445 | make_expr_symbol (address_expr), (long) 0, |
1446 | (char *) NULL); | |
1447 | } | |
1448 | else if (place != NULL) | |
0dd2d296 | 1449 | f = place; |
cc5703cd | 1450 | else if (mips16 && ! ip->use_extend && reloc_type != BFD_RELOC_MIPS16_JMP) |
08e17202 ILT |
1451 | { |
1452 | /* Make sure there is enough room to swap this instruction with | |
1453 | a following jump instruction. */ | |
1454 | frag_grow (6); | |
1455 | f = frag_more (2); | |
1456 | } | |
cc5703cd ILT |
1457 | else |
1458 | f = frag_more (4); | |
becfe05e | 1459 | fixp = NULL; |
cc5703cd | 1460 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1461 | { |
5ac34ac3 | 1462 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1463 | { |
1464 | switch (reloc_type) | |
1465 | { | |
3d3c5039 | 1466 | case BFD_RELOC_32: |
670a50eb ILT |
1467 | ip->insn_opcode |= address_expr->X_add_number; |
1468 | break; | |
3d3c5039 ILT |
1469 | |
1470 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1471 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1472 | break; | |
3d3c5039 ILT |
1473 | |
1474 | case BFD_RELOC_MIPS_JMP: | |
5e1e8f23 ILT |
1475 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1476 | break; | |
1477 | ||
cc5703cd ILT |
1478 | case BFD_RELOC_MIPS16_JMP: |
1479 | ip->insn_opcode |= | |
1480 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1481 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1482 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1483 | break; | |
1484 | ||
3d3c5039 | 1485 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1486 | goto need_reloc; |
3d3c5039 ILT |
1487 | |
1488 | default: | |
670a50eb | 1489 | internalError (); |
3d3c5039 | 1490 | } |
670a50eb ILT |
1491 | } |
1492 | else | |
1493 | { | |
3d3c5039 | 1494 | need_reloc: |
0dd2d296 ILT |
1495 | /* Don't generate a reloc if we are writing into a variant |
1496 | frag. */ | |
1497 | if (place == NULL) | |
867a58b3 ILT |
1498 | { |
1499 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1500 | address_expr, | |
1501 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1502 | reloc_type); | |
1503 | if (unmatched_hi) | |
1504 | { | |
1505 | struct mips_hi_fixup *hi_fixup; | |
1506 | ||
1507 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1508 | hi_fixup = ((struct mips_hi_fixup *) | |
1509 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1510 | hi_fixup->fixp = fixp; | |
1511 | hi_fixup->seg = now_seg; | |
1512 | hi_fixup->next = mips_hi_fixup_list; | |
1513 | mips_hi_fixup_list = hi_fixup; | |
1514 | } | |
1515 | } | |
3d3c5039 ILT |
1516 | } |
1517 | } | |
becfe05e | 1518 | |
cc5703cd ILT |
1519 | if (! mips16 || reloc_type == BFD_RELOC_MIPS16_JMP) |
1520 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1521 | else | |
1522 | { | |
1523 | if (ip->use_extend) | |
1524 | { | |
1525 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1526 | f += 2; | |
1527 | } | |
1528 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1529 | } | |
670a50eb | 1530 | |
1aa6938e | 1531 | /* Update the register mask information. */ |
cc5703cd ILT |
1532 | if (! mips16) |
1533 | { | |
1534 | if (pinfo & INSN_WRITE_GPR_D) | |
1535 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1536 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1537 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1538 | if (pinfo & INSN_READ_GPR_S) | |
1539 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1540 | if (pinfo & INSN_WRITE_GPR_31) | |
1541 | mips_gprmask |= 1 << 31; | |
1542 | if (pinfo & INSN_WRITE_FPR_D) | |
1543 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1544 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1545 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1546 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1547 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1548 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1549 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1550 | if (pinfo & INSN_COP) | |
1551 | { | |
1552 | /* We don't keep enough information to sort these cases out. */ | |
1553 | } | |
1554 | /* Never set the bit for $0, which is always zero. */ | |
1555 | mips_gprmask &=~ 1 << 0; | |
1556 | } | |
1557 | else | |
1aa6938e | 1558 | { |
cc5703cd ILT |
1559 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1560 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1561 | & MIPS16OP_MASK_RX); | |
1562 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1563 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1564 | & MIPS16OP_MASK_RY); | |
1565 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1566 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1567 | & MIPS16OP_MASK_RZ); | |
1568 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1569 | mips_gprmask |= 1 << TREG; | |
1570 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1571 | mips_gprmask |= 1 << SP; | |
1572 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1573 | mips_gprmask |= 1 << RA; | |
1574 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1575 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1576 | if (pinfo & MIPS16_INSN_READ_Z) | |
1577 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1578 | & MIPS16OP_MASK_MOVE32Z); | |
1579 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1580 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1581 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1582 | } |
1aa6938e | 1583 | |
0dd2d296 | 1584 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1585 | { |
becfe05e ILT |
1586 | /* Filling the branch delay slot is more complex. We try to |
1587 | switch the branch with the previous instruction, which we can | |
1588 | do if the previous instruction does not set up a condition | |
1589 | that the branch tests and if the branch is not itself the | |
1590 | target of any branch. */ | |
1aa6938e ILT |
1591 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1592 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1593 | { |
0aa07269 | 1594 | if (mips_optimize < 2 |
19ed8960 ILT |
1595 | /* If we have seen .set volatile or .set nomove, don't |
1596 | optimize. */ | |
1597 | || mips_nomove != 0 | |
4e95866e ILT |
1598 | /* If we had to emit any NOP instructions, then we |
1599 | already know we can not swap. */ | |
1600 | || nops != 0 | |
becfe05e ILT |
1601 | /* If we don't even know the previous insn, we can not |
1602 | swap. */ | |
1603 | || ! prev_insn_valid | |
1604 | /* If the previous insn is already in a branch delay | |
1605 | slot, then we can not swap. */ | |
1606 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1607 | /* If the previous previous insn was in a .set |
1608 | noreorder, we can't swap. Actually, the MIPS | |
1609 | assembler will swap in this situation. However, gcc | |
1610 | configured -with-gnu-as will generate code like | |
1611 | .set noreorder | |
1612 | lw $4,XXX | |
1613 | .set reorder | |
1614 | INSN | |
1615 | bne $4,$0,foo | |
1616 | in which we can not swap the bne and INSN. If gcc is | |
1617 | not configured -with-gnu-as, it does not output the | |
1618 | .set pseudo-ops. We don't have to check | |
1619 | prev_insn_unreordered, because prev_insn_valid will | |
1620 | be 0 in that case. We don't want to use | |
1621 | prev_prev_insn_valid, because we do want to be able | |
1622 | to swap at the start of a function. */ | |
1623 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1624 | /* If the branch is itself the target of a branch, we |
1625 | can not swap. We cheat on this; all we check for is | |
1626 | whether there is a label on this instruction. If | |
1627 | there are any branches to anything other than a | |
1628 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1629 | || insn_labels != NULL |
777ad64d | 1630 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1631 | can not do the swap. This does not apply to the |
1632 | mips16, which uses variant frags for different | |
1633 | purposes. */ | |
1634 | || (! mips16 | |
1635 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
becfe05e ILT |
1636 | /* If the branch reads the condition codes, we don't |
1637 | even try to swap, because in the sequence | |
1638 | ctc1 $X,$31 | |
1639 | INSN | |
1640 | INSN | |
1641 | bc1t LABEL | |
1642 | we can not swap, and I don't feel like handling that | |
1643 | case. */ | |
cc5703cd ILT |
1644 | || (! mips16 |
1645 | && mips_isa < 4 | |
d8a1c247 | 1646 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1647 | /* We can not swap with an instruction that requires a |
1648 | delay slot, becase the target of the branch might | |
1649 | interfere with that instruction. */ | |
cc5703cd ILT |
1650 | || (! mips16 |
1651 | && mips_isa < 4 | |
d8a1c247 KR |
1652 | && (prev_pinfo |
1653 | & (INSN_LOAD_COPROC_DELAY | |
1654 | | INSN_COPROC_MOVE_DELAY | |
1655 | | INSN_WRITE_COND_CODE))) | |
e532b44c | 1656 | || (! interlocks |
b2b8c24e ILT |
1657 | && (prev_pinfo |
1658 | & (INSN_READ_LO | |
1659 | | INSN_READ_HI))) | |
cc5703cd ILT |
1660 | || (! mips16 |
1661 | && mips_isa < 2 | |
1aa6938e | 1662 | && (prev_pinfo |
8358c818 ILT |
1663 | & (INSN_LOAD_MEMORY_DELAY |
1664 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1665 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1666 | || (prev_pinfo |
6e8dda9c ILT |
1667 | & (INSN_UNCOND_BRANCH_DELAY |
1668 | | INSN_COND_BRANCH_DELAY | |
1669 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1670 | /* We do not swap with a trap instruction, since it |
1671 | complicates trap handlers to have the trap | |
1672 | instruction be in a delay slot. */ | |
1aa6938e | 1673 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1674 | /* If the branch reads a register that the previous |
1675 | instruction sets, we can not swap. */ | |
cc5703cd ILT |
1676 | || (! mips16 |
1677 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
becfe05e ILT |
1678 | && insn_uses_reg (ip, |
1679 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1680 | & OP_MASK_RT), | |
cc5703cd ILT |
1681 | MIPS_GR_REG)) |
1682 | || (! mips16 | |
1683 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1684 | && insn_uses_reg (ip, |
1685 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1686 | & OP_MASK_RD), | |
cc5703cd ILT |
1687 | MIPS_GR_REG)) |
1688 | || (mips16 | |
1689 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
1690 | && insn_uses_reg (ip, | |
1691 | ((prev_insn.insn_opcode | |
1692 | >> MIPS16OP_SH_RX) | |
1693 | & MIPS16OP_MASK_RX), | |
1694 | MIPS16_REG)) | |
1695 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1696 | && insn_uses_reg (ip, | |
1697 | ((prev_insn.insn_opcode | |
1698 | >> MIPS16OP_SH_RY) | |
1699 | & MIPS16OP_MASK_RY), | |
1700 | MIPS16_REG)) | |
1701 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1702 | && insn_uses_reg (ip, | |
1703 | ((prev_insn.insn_opcode | |
1704 | >> MIPS16OP_SH_RZ) | |
1705 | & MIPS16OP_MASK_RZ), | |
1706 | MIPS16_REG)) | |
1707 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1708 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1709 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1710 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1711 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1712 | && insn_uses_reg (ip, | |
1713 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1714 | insn_opcode), | |
1715 | MIPS_GR_REG)))) | |
1849d646 ILT |
1716 | /* If the branch writes a register that the previous |
1717 | instruction sets, we can not swap (we know that | |
1718 | branches write only to RD or to $31). */ | |
cc5703cd ILT |
1719 | || (! mips16 |
1720 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
1aa6938e | 1721 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1722 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1723 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1724 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1725 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1726 | & OP_MASK_RT) | |
1727 | == 31)))) | |
cc5703cd ILT |
1728 | || (! mips16 |
1729 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
1aa6938e | 1730 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1731 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1732 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1733 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1734 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1735 | & OP_MASK_RD) | |
1736 | == 31)))) | |
cc5703cd ILT |
1737 | || (mips16 |
1738 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1739 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1740 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1741 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1742 | == RA)))) | |
becfe05e ILT |
1743 | /* If the branch writes a register that the previous |
1744 | instruction reads, we can not swap (we know that | |
1745 | branches only write to RD or to $31). */ | |
cc5703cd ILT |
1746 | || (! mips16 |
1747 | && (pinfo & INSN_WRITE_GPR_D) | |
becfe05e ILT |
1748 | && insn_uses_reg (&prev_insn, |
1749 | ((ip->insn_opcode >> OP_SH_RD) | |
1750 | & OP_MASK_RD), | |
cc5703cd ILT |
1751 | MIPS_GR_REG)) |
1752 | || (! mips16 | |
1753 | && (pinfo & INSN_WRITE_GPR_31) | |
1754 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
1755 | || (mips16 | |
1756 | && (pinfo & MIPS16_INSN_WRITE_31) | |
1757 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
1758 | /* If we are generating embedded PIC code, the branch |
1759 | might be expanded into a sequence which uses $at, so | |
1760 | we can't swap with an instruction which reads it. */ | |
1761 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 1762 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
1763 | /* If the previous previous instruction has a load |
1764 | delay, and sets a register that the branch reads, we | |
1765 | can not swap. */ | |
cc5703cd ILT |
1766 | || (! mips16 |
1767 | && mips_isa < 4 | |
d8a1c247 KR |
1768 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1769 | || (mips_isa < 2 | |
1770 | && (prev_prev_insn.insn_mo->pinfo | |
1771 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1772 | && insn_uses_reg (ip, |
1773 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1774 | & OP_MASK_RT), | |
cc5703cd | 1775 | MIPS_GR_REG)) |
d31a3f5e ILT |
1776 | /* If one instruction sets a condition code and the |
1777 | other one uses a condition code, we can not swap. */ | |
1778 | || ((pinfo & INSN_READ_COND_CODE) | |
1779 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
1780 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
1781 | && (prev_pinfo & INSN_READ_COND_CODE)) |
1782 | /* If the previous instruction uses the PC, we can not | |
1783 | swap. */ | |
1784 | || (mips16 | |
1785 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
1786 | /* If the previous instruction was extended, we can not | |
1787 | swap. */ | |
1788 | || (mips16 && prev_insn_extended) | |
1789 | /* If the previous instruction had a fixup in mips16 | |
1790 | mode, we can not swap. This normally means that the | |
1791 | previous instruction was a 4 byte branch anyhow. */ | |
1792 | || (mips16 && prev_insn_fixp)) | |
becfe05e ILT |
1793 | { |
1794 | /* We could do even better for unconditional branches to | |
1795 | portions of this object file; we could pick up the | |
1796 | instruction at the destination, put it in the delay | |
1797 | slot, and bump the destination address. */ | |
1798 | emit_nop (); | |
1799 | /* Update the previous insn information. */ | |
1800 | prev_prev_insn = *ip; | |
1801 | prev_insn.insn_mo = &dummy_opcode; | |
1802 | } | |
1803 | else | |
1804 | { | |
becfe05e | 1805 | /* It looks like we can actually do the swap. */ |
cc5703cd ILT |
1806 | if (! mips16) |
1807 | { | |
1808 | char *prev_f; | |
1809 | char temp[4]; | |
1810 | ||
1811 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1812 | memcpy (temp, prev_f, 4); | |
1813 | memcpy (prev_f, f, 4); | |
1814 | memcpy (f, temp, 4); | |
1815 | if (prev_insn_fixp) | |
1816 | { | |
1817 | prev_insn_fixp->fx_frag = frag_now; | |
1818 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1819 | } | |
1820 | if (fixp) | |
1821 | { | |
1822 | fixp->fx_frag = prev_insn_frag; | |
1823 | fixp->fx_where = prev_insn_where; | |
1824 | } | |
1825 | } | |
1826 | else if (reloc_type > BFD_RELOC_UNUSED) | |
becfe05e | 1827 | { |
cc5703cd ILT |
1828 | char *prev_f; |
1829 | char temp[2]; | |
1830 | ||
1831 | /* We are in mips16 mode, and we have just created a | |
1832 | variant frag. We need to extract the old | |
1833 | instruction from the end of the previous frag, | |
1834 | and add it to a new frag. */ | |
1835 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1836 | memcpy (temp, prev_f, 2); | |
1837 | prev_insn_frag->fr_fix -= 2; | |
1838 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
1839 | { | |
1840 | assert (prev_insn_where == prev_insn_frag->fr_fix); | |
1841 | memcpy (prev_f, prev_f + 2, 2); | |
1842 | } | |
1843 | memcpy (frag_more (2), temp, 2); | |
becfe05e | 1844 | } |
cc5703cd | 1845 | else |
becfe05e | 1846 | { |
cc5703cd ILT |
1847 | char *prev_f; |
1848 | char temp[2]; | |
1849 | ||
1850 | assert (prev_insn_fixp == NULL); | |
1851 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1852 | memcpy (temp, prev_f, 2); | |
1853 | memcpy (prev_f, f, 2); | |
1854 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
1855 | memcpy (f, temp, 2); | |
1856 | else | |
1857 | { | |
1858 | memcpy (f, f + 2, 2); | |
1859 | memcpy (f + 2, temp, 2); | |
1860 | } | |
1861 | if (fixp) | |
1862 | { | |
1863 | fixp->fx_frag = prev_insn_frag; | |
1864 | fixp->fx_where = prev_insn_where; | |
1865 | } | |
becfe05e | 1866 | } |
cc5703cd | 1867 | |
becfe05e ILT |
1868 | /* Update the previous insn information; leave prev_insn |
1869 | unchanged. */ | |
1870 | prev_prev_insn = *ip; | |
1871 | } | |
1872 | prev_insn_is_delay_slot = 1; | |
1873 | ||
1874 | /* If that was an unconditional branch, forget the previous | |
1875 | insn information. */ | |
1aa6938e | 1876 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1877 | { |
1878 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1879 | prev_insn.insn_mo = &dummy_opcode; | |
1880 | } | |
a677feeb ILT |
1881 | |
1882 | prev_insn_fixp = NULL; | |
1883 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1884 | prev_insn_extended = 0; | |
becfe05e | 1885 | } |
1aa6938e | 1886 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1887 | { |
1888 | /* We don't yet optimize a branch likely. What we should do | |
1889 | is look at the target, copy the instruction found there | |
1890 | into the delay slot, and increment the branch to jump to | |
1891 | the next instruction. */ | |
1892 | emit_nop (); | |
1893 | /* Update the previous insn information. */ | |
1894 | prev_prev_insn = *ip; | |
1895 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
1896 | prev_insn_fixp = NULL; |
1897 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
1898 | prev_insn_extended = 0; | |
8358c818 | 1899 | } |
becfe05e | 1900 | else |
670a50eb | 1901 | { |
becfe05e ILT |
1902 | /* Update the previous insn information. */ |
1903 | if (nops > 0) | |
1904 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1905 | else | |
1906 | prev_prev_insn = prev_insn; | |
1907 | prev_insn = *ip; | |
1908 | ||
1909 | /* Any time we see a branch, we always fill the delay slot | |
1910 | immediately; since this insn is not a branch, we know it | |
1911 | is not in a delay slot. */ | |
1912 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
1913 | |
1914 | prev_insn_fixp = fixp; | |
1915 | prev_insn_reloc_type = reloc_type; | |
1916 | if (mips16) | |
1917 | prev_insn_extended = (ip->use_extend | |
1918 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
1919 | } |
1920 | ||
4e95866e ILT |
1921 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1922 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1923 | prev_insn_frag = frag_now; |
1924 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
1925 | prev_insn_valid = 1; |
1926 | } | |
fbcfacb7 | 1927 | else if (place == NULL) |
a677feeb | 1928 | { |
fbcfacb7 | 1929 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
1930 | reordering, in order to determine the base address for mips16 |
1931 | PC relative relocs. */ | |
1932 | prev_insn = *ip; | |
1933 | prev_insn_reloc_type = reloc_type; | |
1934 | } | |
3d3c5039 | 1935 | |
becfe05e | 1936 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 1937 | mips_clear_insn_labels (); |
becfe05e ILT |
1938 | } |
1939 | ||
1940 | /* This function forgets that there was any previous instruction or | |
1941 | label. */ | |
1942 | ||
1943 | static void | |
1944 | mips_no_prev_insn () | |
1945 | { | |
1946 | prev_insn.insn_mo = &dummy_opcode; | |
1947 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1948 | prev_insn_valid = 0; | |
1949 | prev_insn_is_delay_slot = 0; | |
4e95866e | 1950 | prev_insn_unreordered = 0; |
cc5703cd | 1951 | prev_insn_extended = 0; |
a677feeb | 1952 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 1953 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 1954 | mips_clear_insn_labels (); |
becfe05e ILT |
1955 | } |
1956 | ||
1957 | /* This function must be called whenever we turn on noreorder or emit | |
1958 | something other than instructions. It inserts any NOPS which might | |
1959 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
1960 | kept for the previous instructions. The INSNS parameter is true if |
1961 | instructions are to follow. */ | |
becfe05e ILT |
1962 | |
1963 | static void | |
fbcfacb7 ILT |
1964 | mips_emit_delays (insns) |
1965 | boolean insns; | |
becfe05e ILT |
1966 | { |
1967 | if (! mips_noreorder) | |
1968 | { | |
1969 | int nop; | |
1970 | ||
1971 | nop = 0; | |
cc5703cd ILT |
1972 | if ((! mips16 |
1973 | && mips_isa < 4 | |
344a8d61 JSC |
1974 | && (! cop_interlocks |
1975 | && (prev_insn.insn_mo->pinfo | |
1976 | & (INSN_LOAD_COPROC_DELAY | |
1977 | | INSN_COPROC_MOVE_DELAY | |
1978 | | INSN_WRITE_COND_CODE)))) | |
e532b44c | 1979 | || (! interlocks |
b2b8c24e ILT |
1980 | && (prev_insn.insn_mo->pinfo |
1981 | & (INSN_READ_LO | |
1982 | | INSN_READ_HI))) | |
cc5703cd ILT |
1983 | || (! mips16 |
1984 | && mips_isa < 2 | |
8358c818 ILT |
1985 | && (prev_insn.insn_mo->pinfo |
1986 | & (INSN_LOAD_MEMORY_DELAY | |
1987 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1988 | { |
1989 | nop = 1; | |
cc5703cd ILT |
1990 | if ((! mips16 |
1991 | && mips_isa < 4 | |
344a8d61 JSC |
1992 | && (! cop_interlocks |
1993 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 1994 | || (! interlocks |
b2b8c24e ILT |
1995 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1996 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
1997 | emit_nop (); |
1998 | } | |
cc5703cd ILT |
1999 | else if ((! mips16 |
2000 | && mips_isa < 4 | |
344a8d61 JSC |
2001 | && (! cop_interlocks |
2002 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
e532b44c | 2003 | || (! interlocks |
b2b8c24e ILT |
2004 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2005 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
becfe05e ILT |
2006 | nop = 1; |
2007 | if (nop) | |
670a50eb | 2008 | { |
fbcfacb7 ILT |
2009 | struct insn_label_list *l; |
2010 | ||
becfe05e | 2011 | emit_nop (); |
fbcfacb7 | 2012 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2013 | { |
fbcfacb7 ILT |
2014 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2015 | l->label->sy_frag = frag_now; | |
2016 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2017 | /* mips16 text labels are stored as odd. */ | |
2018 | if (mips16) | |
2019 | ++l->label->sy_value.X_add_number; | |
becfe05e | 2020 | } |
3d3c5039 ILT |
2021 | } |
2022 | } | |
0221ddf7 | 2023 | |
fbcfacb7 ILT |
2024 | /* Mark instruction labels in mips16 mode. This permits the linker |
2025 | to handle them specially, such as generating jalx instructions | |
2026 | when needed. We also make them odd for the duration of the | |
2027 | assembly, in order to generate the right sort of code. We will | |
2028 | make them even in the adjust_symtab routine, while leaving them | |
2029 | marked. This is convenient for the debugger and the | |
2030 | disassembler. The linker knows to make them odd again. */ | |
2031 | if (mips16 && insns) | |
2032 | { | |
2033 | struct insn_label_list *l; | |
2034 | ||
2035 | for (l = insn_labels; l != NULL; l = l->next) | |
2036 | { | |
2037 | #ifdef S_SET_OTHER | |
2038 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2039 | S_SET_OTHER (l->label, STO_MIPS16); | |
2040 | #endif | |
2041 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
2042 | ++l->label->sy_value.X_add_number; | |
2043 | } | |
2044 | } | |
2045 | ||
0221ddf7 | 2046 | mips_no_prev_insn (); |
3d3c5039 ILT |
2047 | } |
2048 | ||
670a50eb ILT |
2049 | /* Build an instruction created by a macro expansion. This is passed |
2050 | a pointer to the count of instructions created so far, an | |
2051 | expression, the name of the instruction to build, an operand format | |
2052 | string, and corresponding arguments. */ | |
2053 | ||
1dc1e798 | 2054 | #ifdef USE_STDARG |
3d3c5039 | 2055 | static void |
0dd2d296 ILT |
2056 | macro_build (char *place, |
2057 | int *counter, | |
670a50eb | 2058 | expressionS * ep, |
3d3c5039 ILT |
2059 | const char *name, |
2060 | const char *fmt, | |
2061 | ...) | |
1dc1e798 | 2062 | #else |
3d3c5039 | 2063 | static void |
0dd2d296 ILT |
2064 | macro_build (place, counter, ep, name, fmt, va_alist) |
2065 | char *place; | |
3d3c5039 ILT |
2066 | int *counter; |
2067 | expressionS *ep; | |
2068 | const char *name; | |
2069 | const char *fmt; | |
2070 | va_dcl | |
1dc1e798 | 2071 | #endif |
3d3c5039 | 2072 | { |
670a50eb ILT |
2073 | struct mips_cl_insn insn; |
2074 | bfd_reloc_code_real_type r; | |
2075 | va_list args; | |
3d3c5039 | 2076 | |
1dc1e798 | 2077 | #ifdef USE_STDARG |
670a50eb | 2078 | va_start (args, fmt); |
3d3c5039 | 2079 | #else |
670a50eb | 2080 | va_start (args); |
3d3c5039 ILT |
2081 | #endif |
2082 | ||
670a50eb ILT |
2083 | /* |
2084 | * If the macro is about to expand into a second instruction, | |
2085 | * print a warning if needed. We need to pass ip as a parameter | |
2086 | * to generate a better warning message here... | |
2087 | */ | |
0dd2d296 | 2088 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2089 | as_warn ("Macro instruction expanded into multiple instructions"); |
2090 | ||
0dd2d296 ILT |
2091 | if (place == NULL) |
2092 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2093 | |
cc5703cd ILT |
2094 | if (mips16) |
2095 | { | |
2096 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2097 | va_end (args); | |
2098 | return; | |
2099 | } | |
2100 | ||
670a50eb ILT |
2101 | r = BFD_RELOC_UNUSED; |
2102 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2103 | assert (insn.insn_mo); | |
2104 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2105 | ||
9226253a | 2106 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
c625fc23 JSC |
2107 | || insn.insn_mo->pinfo == INSN_MACRO |
2108 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA2 | |
2109 | && mips_isa < 2) | |
2110 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA3 | |
2111 | && mips_isa < 3) | |
2112 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_ISA4 | |
2113 | && mips_isa < 4) | |
2114 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4650 | |
2115 | && ! mips_4650) | |
2116 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4010 | |
2117 | && ! mips_4010) | |
2118 | || ((insn.insn_mo->pinfo & INSN_ISA) == INSN_4100 | |
2119 | && ! mips_4100)) | |
670a50eb ILT |
2120 | { |
2121 | ++insn.insn_mo; | |
2122 | assert (insn.insn_mo->name); | |
2123 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2124 | } |
670a50eb ILT |
2125 | insn.insn_opcode = insn.insn_mo->match; |
2126 | for (;;) | |
2127 | { | |
2128 | switch (*fmt++) | |
2129 | { | |
3d3c5039 | 2130 | case '\0': |
670a50eb | 2131 | break; |
3d3c5039 ILT |
2132 | |
2133 | case ',': | |
2134 | case '(': | |
2135 | case ')': | |
670a50eb | 2136 | continue; |
3d3c5039 ILT |
2137 | |
2138 | case 't': | |
2139 | case 'w': | |
918692a5 | 2140 | case 'E': |
670a50eb ILT |
2141 | insn.insn_opcode |= va_arg (args, int) << 16; |
2142 | continue; | |
3d3c5039 ILT |
2143 | |
2144 | case 'c': | |
2145 | case 'T': | |
2146 | case 'W': | |
670a50eb ILT |
2147 | insn.insn_opcode |= va_arg (args, int) << 16; |
2148 | continue; | |
3d3c5039 ILT |
2149 | |
2150 | case 'd': | |
918692a5 | 2151 | case 'G': |
670a50eb ILT |
2152 | insn.insn_opcode |= va_arg (args, int) << 11; |
2153 | continue; | |
3d3c5039 ILT |
2154 | |
2155 | case 'V': | |
2156 | case 'S': | |
670a50eb ILT |
2157 | insn.insn_opcode |= va_arg (args, int) << 11; |
2158 | continue; | |
3d3c5039 | 2159 | |
ff3a5c18 ILT |
2160 | case 'z': |
2161 | continue; | |
2162 | ||
3d3c5039 | 2163 | case '<': |
670a50eb ILT |
2164 | insn.insn_opcode |= va_arg (args, int) << 6; |
2165 | continue; | |
3d3c5039 ILT |
2166 | |
2167 | case 'D': | |
670a50eb ILT |
2168 | insn.insn_opcode |= va_arg (args, int) << 6; |
2169 | continue; | |
3d3c5039 | 2170 | |
918692a5 ILT |
2171 | case 'B': |
2172 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2173 | continue; | |
2174 | ||
3d3c5039 ILT |
2175 | case 'b': |
2176 | case 's': | |
2177 | case 'r': | |
2178 | case 'v': | |
670a50eb ILT |
2179 | insn.insn_opcode |= va_arg (args, int) << 21; |
2180 | continue; | |
3d3c5039 ILT |
2181 | |
2182 | case 'i': | |
2183 | case 'j': | |
2184 | case 'o': | |
9226253a | 2185 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2186 | assert (r == BFD_RELOC_MIPS_GPREL |
2187 | || r == BFD_RELOC_MIPS_LITERAL | |
2188 | || r == BFD_RELOC_LO16 | |
2189 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2190 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2191 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2192 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2193 | || (ep->X_op == O_subtract |
2194 | && now_seg == text_section | |
ecd4ca1c | 2195 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2196 | continue; |
3d3c5039 | 2197 | |
6e8dda9c | 2198 | case 'u': |
ecd4ca1c ILT |
2199 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2200 | assert (ep != NULL | |
2201 | && (ep->X_op == O_constant | |
2202 | || (ep->X_op == O_symbol | |
2203 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2204 | || r == BFD_RELOC_HI16 |
2205 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2206 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2207 | || (ep->X_op == O_subtract |
2208 | && now_seg == text_section | |
ecd4ca1c ILT |
2209 | && r == BFD_RELOC_PCREL_HI16_S))); |
2210 | if (ep->X_op == O_constant) | |
2211 | { | |
2212 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2213 | ep = NULL; | |
2214 | r = BFD_RELOC_UNUSED; | |
2215 | } | |
6e8dda9c ILT |
2216 | continue; |
2217 | ||
3d3c5039 | 2218 | case 'p': |
670a50eb ILT |
2219 | assert (ep != NULL); |
2220 | /* | |
2221 | * This allows macro() to pass an immediate expression for | |
2222 | * creating short branches without creating a symbol. | |
2223 | * Note that the expression still might come from the assembly | |
2224 | * input, in which case the value is not checked for range nor | |
2225 | * is a relocation entry generated (yuck). | |
2226 | */ | |
5ac34ac3 | 2227 | if (ep->X_op == O_constant) |
670a50eb ILT |
2228 | { |
2229 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2230 | ep = NULL; | |
2231 | } | |
2232 | else | |
2233 | r = BFD_RELOC_16_PCREL_S2; | |
2234 | continue; | |
3d3c5039 | 2235 | |
9226253a ILT |
2236 | case 'a': |
2237 | assert (ep != NULL); | |
2238 | r = BFD_RELOC_MIPS_JMP; | |
2239 | continue; | |
2240 | ||
3d3c5039 | 2241 | default: |
670a50eb | 2242 | internalError (); |
3d3c5039 | 2243 | } |
670a50eb | 2244 | break; |
3d3c5039 | 2245 | } |
670a50eb ILT |
2246 | va_end (args); |
2247 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2248 | ||
867a58b3 | 2249 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2250 | } |
2251 | ||
cc5703cd ILT |
2252 | static void |
2253 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2254 | char *place; | |
2255 | int *counter; | |
2256 | expressionS *ep; | |
2257 | const char *name; | |
2258 | const char *fmt; | |
2259 | va_list args; | |
2260 | { | |
2261 | struct mips_cl_insn insn; | |
2262 | bfd_reloc_code_real_type r; | |
2263 | ||
2264 | r = BFD_RELOC_UNUSED; | |
2265 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2266 | assert (insn.insn_mo); | |
2267 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2268 | ||
2269 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2270 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2271 | { | |
2272 | ++insn.insn_mo; | |
2273 | assert (insn.insn_mo->name); | |
2274 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2275 | } | |
2276 | ||
2277 | insn.insn_opcode = insn.insn_mo->match; | |
2278 | insn.use_extend = false; | |
2279 | ||
2280 | for (;;) | |
2281 | { | |
2282 | int c; | |
2283 | ||
2284 | c = *fmt++; | |
2285 | switch (c) | |
2286 | { | |
2287 | case '\0': | |
2288 | break; | |
2289 | ||
2290 | case ',': | |
2291 | case '(': | |
2292 | case ')': | |
2293 | continue; | |
2294 | ||
2295 | case 'y': | |
2296 | case 'w': | |
2297 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2298 | continue; | |
2299 | ||
2300 | case 'x': | |
2301 | case 'v': | |
2302 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2303 | continue; | |
2304 | ||
2305 | case 'z': | |
2306 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2307 | continue; | |
2308 | ||
2309 | case 'Z': | |
2310 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2311 | continue; | |
2312 | ||
2313 | case '0': | |
2314 | case 'S': | |
2315 | case 'P': | |
2316 | case 'R': | |
2317 | continue; | |
2318 | ||
2319 | case 'X': | |
2320 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2321 | continue; | |
2322 | ||
2323 | case 'Y': | |
2324 | { | |
2325 | int regno; | |
2326 | ||
2327 | regno = va_arg (args, int); | |
2328 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2329 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2330 | } | |
2331 | continue; | |
2332 | ||
2333 | case '<': | |
2334 | case '>': | |
2335 | case '4': | |
2336 | case '5': | |
2337 | case 'H': | |
2338 | case 'W': | |
2339 | case 'D': | |
2340 | case 'j': | |
2341 | case '8': | |
2342 | case 'V': | |
2343 | case 'C': | |
2344 | case 'U': | |
2345 | case 'k': | |
2346 | case 'K': | |
2347 | case 'p': | |
2348 | case 'q': | |
2349 | { | |
2350 | assert (ep != NULL); | |
2351 | ||
2352 | if (ep->X_op != O_constant) | |
2353 | r = BFD_RELOC_UNUSED + c; | |
2354 | else | |
2355 | { | |
15e69f98 ILT |
2356 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2357 | false, false, &insn.insn_opcode, | |
2358 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2359 | ep = NULL; |
2360 | r = BFD_RELOC_UNUSED; | |
2361 | } | |
2362 | } | |
2363 | continue; | |
2364 | ||
2365 | case '6': | |
2366 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2367 | continue; | |
2368 | } | |
2369 | ||
2370 | break; | |
2371 | } | |
2372 | ||
2373 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2374 | ||
2375 | append_insn (place, &insn, ep, r, false); | |
2376 | } | |
2377 | ||
3d3c5039 ILT |
2378 | /* |
2379 | * Generate a "lui" instruction. | |
2380 | */ | |
2381 | static void | |
0dd2d296 ILT |
2382 | macro_build_lui (place, counter, ep, regnum) |
2383 | char *place; | |
3d3c5039 ILT |
2384 | int *counter; |
2385 | expressionS *ep; | |
2386 | int regnum; | |
2387 | { | |
670a50eb ILT |
2388 | expressionS high_expr; |
2389 | struct mips_cl_insn insn; | |
2390 | bfd_reloc_code_real_type r; | |
2391 | CONST char *name = "lui"; | |
2392 | CONST char *fmt = "t,u"; | |
2393 | ||
cc5703cd ILT |
2394 | assert (! mips16); |
2395 | ||
0dd2d296 ILT |
2396 | if (place == NULL) |
2397 | high_expr = *ep; | |
2398 | else | |
2399 | { | |
2400 | high_expr.X_op = O_constant; | |
fb251650 | 2401 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2402 | } |
670a50eb | 2403 | |
5ac34ac3 | 2404 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2405 | { |
2406 | /* we can compute the instruction now without a relocation entry */ | |
2407 | if (high_expr.X_add_number & 0x8000) | |
2408 | high_expr.X_add_number += 0x10000; | |
2409 | high_expr.X_add_number = | |
2410 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2411 | r = BFD_RELOC_UNUSED; | |
2412 | } | |
2413 | else | |
0dd2d296 ILT |
2414 | { |
2415 | assert (ep->X_op == O_symbol); | |
2416 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2417 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2418 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2419 | r = BFD_RELOC_HI16_S; | |
2420 | } | |
670a50eb ILT |
2421 | |
2422 | /* | |
2423 | * If the macro is about to expand into a second instruction, | |
2424 | * print a warning if needed. We need to pass ip as a parameter | |
2425 | * to generate a better warning message here... | |
2426 | */ | |
0dd2d296 | 2427 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2428 | as_warn ("Macro instruction expanded into multiple instructions"); |
2429 | ||
0dd2d296 ILT |
2430 | if (place == NULL) |
2431 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2432 | |
2433 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2434 | assert (insn.insn_mo); | |
2435 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2436 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2437 | ||
0dd2d296 | 2438 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2439 | if (r == BFD_RELOC_UNUSED) |
2440 | { | |
2441 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2442 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2443 | } |
2444 | else | |
867a58b3 | 2445 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2446 | } |
2447 | ||
2448 | /* set_at() | |
2449 | * Generates code to set the $at register to true (one) | |
2450 | * if reg is less than the immediate expression. | |
2451 | */ | |
2452 | static void | |
6e8dda9c | 2453 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2454 | int *counter; |
2455 | int reg; | |
6e8dda9c | 2456 | int unsignedp; |
3d3c5039 | 2457 | { |
6e8dda9c | 2458 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 2459 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2460 | unsignedp ? "sltiu" : "slti", |
9226253a | 2461 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2462 | else |
670a50eb | 2463 | { |
d8a1c247 | 2464 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2465 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2466 | unsignedp ? "sltu" : "slt", |
2467 | "d,v,t", AT, reg, AT); | |
670a50eb | 2468 | } |
3d3c5039 ILT |
2469 | } |
2470 | ||
6e8dda9c | 2471 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2472 | |
2473 | static void | |
19ed8960 | 2474 | check_absolute_expr (ip, ex) |
3d3c5039 | 2475 | struct mips_cl_insn *ip; |
19ed8960 | 2476 | expressionS *ex; |
3d3c5039 | 2477 | { |
19ed8960 | 2478 | if (ex->X_op != O_constant) |
670a50eb | 2479 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2480 | } |
2481 | ||
ff8716f5 JSC |
2482 | /* Count the leading zeroes by performing a binary chop. This is a |
2483 | bulky bit of source, but performance is a LOT better for the | |
2484 | majority of values than a simple loop to count the bits: | |
2485 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2486 | if ((v) & (1 << (31 - lcnt))) | |
2487 | break; | |
2488 | However it is not code size friendly, and the gain will drop a bit | |
2489 | on certain cached systems. | |
2490 | */ | |
2491 | #define COUNT_TOP_ZEROES(v) \ | |
2492 | (((v) & ~0xffff) == 0 \ | |
2493 | ? ((v) & ~0xff) == 0 \ | |
2494 | ? ((v) & ~0xf) == 0 \ | |
2495 | ? ((v) & ~0x3) == 0 \ | |
2496 | ? ((v) & ~0x1) == 0 \ | |
2497 | ? !(v) \ | |
2498 | ? 32 \ | |
2499 | : 31 \ | |
2500 | : 30 \ | |
2501 | : ((v) & ~0x7) == 0 \ | |
2502 | ? 29 \ | |
2503 | : 28 \ | |
2504 | : ((v) & ~0x3f) == 0 \ | |
2505 | ? ((v) & ~0x1f) == 0 \ | |
2506 | ? 27 \ | |
2507 | : 26 \ | |
2508 | : ((v) & ~0x7f) == 0 \ | |
2509 | ? 25 \ | |
2510 | : 24 \ | |
2511 | : ((v) & ~0xfff) == 0 \ | |
2512 | ? ((v) & ~0x3ff) == 0 \ | |
2513 | ? ((v) & ~0x1ff) == 0 \ | |
2514 | ? 23 \ | |
2515 | : 22 \ | |
2516 | : ((v) & ~0x7ff) == 0 \ | |
2517 | ? 21 \ | |
2518 | : 20 \ | |
2519 | : ((v) & ~0x3fff) == 0 \ | |
2520 | ? ((v) & ~0x1fff) == 0 \ | |
2521 | ? 19 \ | |
2522 | : 18 \ | |
2523 | : ((v) & ~0x7fff) == 0 \ | |
2524 | ? 17 \ | |
2525 | : 16 \ | |
2526 | : ((v) & ~0xffffff) == 0 \ | |
2527 | ? ((v) & ~0xfffff) == 0 \ | |
2528 | ? ((v) & ~0x3ffff) == 0 \ | |
2529 | ? ((v) & ~0x1ffff) == 0 \ | |
2530 | ? 15 \ | |
2531 | : 14 \ | |
2532 | : ((v) & ~0x7ffff) == 0 \ | |
2533 | ? 13 \ | |
2534 | : 12 \ | |
2535 | : ((v) & ~0x3fffff) == 0 \ | |
2536 | ? ((v) & ~0x1fffff) == 0 \ | |
2537 | ? 11 \ | |
2538 | : 10 \ | |
2539 | : ((v) & ~0x7fffff) == 0 \ | |
2540 | ? 9 \ | |
2541 | : 8 \ | |
2542 | : ((v) & ~0xfffffff) == 0 \ | |
2543 | ? ((v) & ~0x3ffffff) == 0 \ | |
2544 | ? ((v) & ~0x1ffffff) == 0 \ | |
2545 | ? 7 \ | |
2546 | : 6 \ | |
2547 | : ((v) & ~0x7ffffff) == 0 \ | |
2548 | ? 5 \ | |
2549 | : 4 \ | |
2550 | : ((v) & ~0x3fffffff) == 0 \ | |
2551 | ? ((v) & ~0x1fffffff) == 0 \ | |
2552 | ? 3 \ | |
2553 | : 2 \ | |
2554 | : ((v) & ~0x7fffffff) == 0 \ | |
2555 | ? 1 \ | |
2556 | : 0) | |
2557 | ||
3d3c5039 ILT |
2558 | /* load_register() |
2559 | * This routine generates the least number of instructions neccessary to load | |
2560 | * an absolute expression value into a register. | |
2561 | */ | |
2562 | static void | |
d8a1c247 | 2563 | load_register (counter, reg, ep, dbl) |
670a50eb | 2564 | int *counter; |
670a50eb ILT |
2565 | int reg; |
2566 | expressionS *ep; | |
d8a1c247 | 2567 | int dbl; |
3d3c5039 | 2568 | { |
d8a1c247 | 2569 | int shift, freg; |
ff8716f5 | 2570 | expressionS hi32, lo32, tmp; |
847a01cd ILT |
2571 | |
2572 | if (ep->X_op != O_big) | |
6e8dda9c | 2573 | { |
847a01cd | 2574 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2575 | if (ep->X_add_number < 0x8000 |
2576 | && (ep->X_add_number >= 0 | |
2577 | || (ep->X_add_number >= -0x8000 | |
2578 | && (! dbl | |
2579 | || ! ep->X_unsigned | |
2580 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2581 | { |
2582 | /* We can handle 16 bit signed values with an addiu to | |
2583 | $zero. No need to ever use daddiu here, since $zero and | |
2584 | the result are always correct in 32 bit mode. */ | |
2585 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2586 | (int) BFD_RELOC_LO16); | |
2587 | return; | |
2588 | } | |
2589 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2590 | { | |
2591 | /* We can handle 16 bit unsigned values with an ori to | |
2592 | $zero. */ | |
2593 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2594 | (int) BFD_RELOC_LO16); | |
2595 | return; | |
2596 | } | |
98bfd087 ILT |
2597 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2598 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2599 | == ~ (offsetT) 0x7fffffff)) | |
2600 | && (! dbl | |
2601 | || ! ep->X_unsigned | |
2602 | || sizeof (ep->X_add_number) > 4 | |
2603 | || (ep->X_add_number & 0x80000000) == 0)) | |
ff8716f5 | 2604 | || ((mips_isa < 3 || !dbl) |
0267c6c9 | 2605 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)) |
847a01cd ILT |
2606 | { |
2607 | /* 32 bit values require an lui. */ | |
2608 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2609 | (int) BFD_RELOC_HI16); | |
2610 | if ((ep->X_add_number & 0xffff) != 0) | |
2611 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2612 | (int) BFD_RELOC_LO16); | |
2613 | return; | |
2614 | } | |
6e8dda9c | 2615 | } |
847a01cd ILT |
2616 | |
2617 | /* The value is larger than 32 bits. */ | |
2618 | ||
2619 | if (mips_isa < 3) | |
670a50eb | 2620 | { |
6e8dda9c | 2621 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2622 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2623 | (int) BFD_RELOC_LO16); |
847a01cd | 2624 | return; |
6e8dda9c | 2625 | } |
6e8dda9c | 2626 | |
847a01cd ILT |
2627 | if (ep->X_op != O_big) |
2628 | { | |
6e8dda9c ILT |
2629 | hi32 = *ep; |
2630 | shift = 32; | |
2631 | hi32.X_add_number >>= shift; | |
2632 | hi32.X_add_number &= 0xffffffff; | |
2633 | if ((hi32.X_add_number & 0x80000000) != 0) | |
2634 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
6e8dda9c ILT |
2635 | lo32 = *ep; |
2636 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2637 | } |
847a01cd ILT |
2638 | else |
2639 | { | |
2640 | assert (ep->X_add_number > 2); | |
2641 | if (ep->X_add_number == 3) | |
2642 | generic_bignum[3] = 0; | |
2643 | else if (ep->X_add_number > 4) | |
2644 | as_bad ("Number larger than 64 bits"); | |
2645 | lo32.X_op = O_constant; | |
2646 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2647 | hi32.X_op = O_constant; | |
2648 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2649 | } | |
2650 | ||
d8a1c247 KR |
2651 | if (hi32.X_add_number == 0) |
2652 | freg = 0; | |
2653 | else | |
2654 | { | |
fb251650 ILT |
2655 | if (hi32.X_add_number == 0xffffffff) |
2656 | { | |
2657 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2658 | { | |
2659 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", reg, 0, | |
2660 | (int) BFD_RELOC_LO16); | |
2661 | return; | |
2662 | } | |
2663 | if (lo32.X_add_number & 0x80000000) | |
2664 | { | |
2665 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2666 | (int) BFD_RELOC_HI16); | |
2667 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, reg, | |
2668 | (int) BFD_RELOC_LO16); | |
2669 | return; | |
2670 | } | |
2671 | } | |
ff8716f5 JSC |
2672 | |
2673 | /* Check for 16bit shifted constant: */ | |
2674 | shift = 32; | |
2675 | tmp.X_add_number = hi32.X_add_number << shift | lo32.X_add_number; | |
2676 | /* We know that hi32 is non-zero, so start the mask on the first | |
2677 | bit of the hi32 value: */ | |
2678 | shift = 17; | |
2679 | do | |
2680 | { | |
2681 | if ((tmp.X_add_number & ~((offsetT)0xffff << shift)) == 0) | |
2682 | { | |
2683 | tmp.X_op = O_constant; | |
2684 | tmp.X_add_number >>= shift; | |
2685 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2686 | (int) BFD_RELOC_LO16); | |
2687 | macro_build ((char *) NULL, counter, NULL, | |
2688 | (shift >= 32) ? "dsll32" : "dsll", | |
2689 | "d,w,<", reg, reg, (shift >= 32) ? shift - 32 : shift); | |
2690 | return; | |
2691 | } | |
2692 | shift++; | |
2693 | } while (shift <= (64 - 16)); | |
2694 | ||
2695 | freg = 0; | |
2696 | shift = 32; | |
2697 | tmp.X_add_number = hi32.X_add_number << shift | lo32.X_add_number; | |
2698 | while ((tmp.X_add_number & 1) == 0) | |
2699 | { | |
2700 | tmp.X_add_number >>= 1; | |
2701 | freg++; | |
2702 | } | |
2703 | if (((tmp.X_add_number + 1) & tmp.X_add_number) == 0) /* (power-of-2 - 1) */ | |
2704 | { | |
2705 | shift = COUNT_TOP_ZEROES((unsigned int)hi32.X_add_number); | |
2706 | if (shift != 0) | |
2707 | { | |
2708 | tmp.X_op = O_constant; | |
2709 | tmp.X_add_number = (offsetT)-1; | |
2710 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", reg, 0, | |
2711 | (int) BFD_RELOC_LO16); /* set all ones */ | |
2712 | if (freg != 0) | |
2713 | { | |
2714 | freg += shift; | |
2715 | macro_build ((char *) NULL, counter, NULL, | |
2716 | (freg >= 32) ? "dsll32" : "dsll", | |
2717 | "d,w,<", reg, reg, | |
2718 | (freg >= 32) ? freg - 32 : freg); | |
2719 | } | |
2720 | macro_build ((char *) NULL, counter, NULL, (shift >= 32) ? "dsrl32" : "dsrl", | |
2721 | "d,w,<", reg, reg, (shift >= 32) ? shift - 32 : shift); | |
2722 | return; | |
2723 | } | |
2724 | } | |
d8a1c247 KR |
2725 | load_register (counter, reg, &hi32, 0); |
2726 | freg = reg; | |
2727 | } | |
847a01cd | 2728 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
2729 | { |
2730 | if (freg != 0) | |
2731 | { | |
2732 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
2733 | freg, 0); | |
2734 | freg = reg; | |
2735 | } | |
2736 | } | |
847a01cd ILT |
2737 | else |
2738 | { | |
2739 | expressionS mid16; | |
2740 | ||
fb251650 ILT |
2741 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
2742 | { | |
2743 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2744 | (int) BFD_RELOC_HI16); | |
2745 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 2746 | reg, 0); |
fb251650 ILT |
2747 | return; |
2748 | } | |
2749 | ||
d8a1c247 KR |
2750 | if (freg != 0) |
2751 | { | |
2752 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
2753 | freg, 16); | |
2754 | freg = reg; | |
2755 | } | |
847a01cd ILT |
2756 | mid16 = lo32; |
2757 | mid16.X_add_number >>= 16; | |
2758 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 2759 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
2760 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
2761 | reg, 16); | |
d8a1c247 | 2762 | freg = reg; |
847a01cd ILT |
2763 | } |
2764 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 2765 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 2766 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
2767 | } |
2768 | ||
0dd2d296 ILT |
2769 | /* Load an address into a register. */ |
2770 | ||
2771 | static void | |
2772 | load_address (counter, reg, ep) | |
2773 | int *counter; | |
2774 | int reg; | |
2775 | expressionS *ep; | |
2776 | { | |
2777 | char *p; | |
2778 | ||
2779 | if (ep->X_op != O_constant | |
2780 | && ep->X_op != O_symbol) | |
2781 | { | |
2782 | as_bad ("expression too complex"); | |
2783 | ep->X_op = O_constant; | |
2784 | } | |
2785 | ||
2786 | if (ep->X_op == O_constant) | |
d9aba805 | 2787 | { |
d8a1c247 | 2788 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
2789 | return; |
2790 | } | |
2791 | ||
2792 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
2793 | { |
2794 | /* If this is a reference to a GP relative symbol, we want | |
2795 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2796 | Otherwise we want | |
04cb3372 | 2797 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
2798 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
2799 | If we have an addend, we always use the latter form. */ | |
7a15a226 ILT |
2800 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
2801 | || nopic_need_relax (ep->X_add_symbol)) | |
0dd2d296 ILT |
2802 | p = NULL; |
2803 | else | |
2804 | { | |
8ea7f4e8 | 2805 | frag_grow (20); |
0dd2d296 ILT |
2806 | macro_build ((char *) NULL, counter, ep, |
2807 | mips_isa < 3 ? "addiu" : "daddiu", | |
2808 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2809 | p = frag_var (rs_machine_dependent, 8, 0, | |
847a01cd | 2810 | RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros), |
0dd2d296 ILT |
2811 | ep->X_add_symbol, (long) 0, (char *) NULL); |
2812 | } | |
2813 | macro_build_lui (p, counter, ep, reg); | |
2814 | if (p != NULL) | |
2815 | p += 4; | |
2816 | macro_build (p, counter, ep, | |
2817 | mips_isa < 3 ? "addiu" : "daddiu", | |
2818 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2819 | } | |
fb251650 | 2820 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
2821 | { |
2822 | expressionS ex; | |
2823 | ||
2824 | /* If this is a reference to an external symbol, we want | |
2825 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2826 | Otherwise we want | |
2827 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2828 | nop | |
2829 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 2830 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
2831 | ex.X_add_number = ep->X_add_number; |
2832 | ep->X_add_number = 0; | |
8ea7f4e8 | 2833 | frag_grow (20); |
0dd2d296 ILT |
2834 | macro_build ((char *) NULL, counter, ep, |
2835 | mips_isa < 3 ? "lw" : "ld", | |
2836 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2837 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
2838 | p = frag_var (rs_machine_dependent, 4, 0, | |
2839 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
2840 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2841 | macro_build (p, counter, ep, | |
2842 | mips_isa < 3 ? "addiu" : "daddiu", | |
2843 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2844 | if (ex.X_add_number != 0) | |
2845 | { | |
2846 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2847 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2848 | ex.X_op = O_constant; | |
fb251650 ILT |
2849 | macro_build ((char *) NULL, counter, &ex, |
2850 | mips_isa < 3 ? "addiu" : "daddiu", | |
2851 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2852 | } | |
2853 | } | |
2854 | else if (mips_pic == SVR4_PIC) | |
2855 | { | |
2856 | expressionS ex; | |
2857 | int off; | |
2858 | ||
2859 | /* This is the large GOT case. If this is a reference to an | |
2860 | external symbol, we want | |
2861 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
2862 | addu $reg,$reg,$gp | |
2863 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
2864 | Otherwise, for a reference to a local symbol, we want | |
2865 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2866 | nop | |
2867 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
2868 | If there is a constant, it must be added in after. */ | |
2869 | ex.X_add_number = ep->X_add_number; | |
2870 | ep->X_add_number = 0; | |
2871 | if (reg_needs_delay (GP)) | |
2872 | off = 4; | |
2873 | else | |
2874 | off = 0; | |
2875 | frag_grow (32); | |
2876 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2877 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
2878 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
2879 | mips_isa < 3 ? "addu" : "daddu", | |
2880 | "d,v,t", reg, reg, GP); | |
2881 | macro_build ((char *) NULL, counter, ep, | |
2882 | mips_isa < 3 ? "lw" : "ld", | |
2883 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
2884 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
2885 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
2886 | mips_warn_about_macros), | |
2887 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
2888 | if (off > 0) | |
2889 | { | |
2890 | /* We need a nop before loading from $gp. This special | |
2891 | check is required because the lui which starts the main | |
2892 | instruction stream does not refer to $gp, and so will not | |
2893 | insert the nop which may be required. */ | |
2894 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2895 | p += 4; | |
2896 | } | |
2897 | macro_build (p, counter, ep, | |
2898 | mips_isa < 3 ? "lw" : "ld", | |
2899 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2900 | p += 4; | |
2901 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
2902 | p += 4; | |
2903 | macro_build (p, counter, ep, | |
2904 | mips_isa < 3 ? "addiu" : "daddiu", | |
2905 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2906 | if (ex.X_add_number != 0) | |
2907 | { | |
2908 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
2909 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
2910 | ex.X_op = O_constant; | |
2911 | macro_build ((char *) NULL, counter, &ex, | |
0dd2d296 ILT |
2912 | mips_isa < 3 ? "addiu" : "daddiu", |
2913 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
2914 | } | |
d9aba805 ILT |
2915 | } |
2916 | else if (mips_pic == EMBEDDED_PIC) | |
2917 | { | |
2918 | /* We always do | |
2919 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2920 | */ | |
2921 | macro_build ((char *) NULL, counter, ep, | |
2922 | mips_isa < 3 ? "addiu" : "daddiu", | |
2923 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2924 | } | |
2925 | else | |
2926 | abort (); | |
0dd2d296 ILT |
2927 | } |
2928 | ||
3d3c5039 ILT |
2929 | /* |
2930 | * Build macros | |
2931 | * This routine implements the seemingly endless macro or synthesized | |
2932 | * instructions and addressing modes in the mips assembly language. Many | |
2933 | * of these macros are simple and are similar to each other. These could | |
2934 | * probably be handled by some kind of table or grammer aproach instead of | |
2935 | * this verbose method. Others are not simple macros but are more like | |
2936 | * optimizing code generation. | |
2937 | * One interesting optimization is when several store macros appear | |
2938 | * consecutivly that would load AT with the upper half of the same address. | |
2939 | * The ensuing load upper instructions are ommited. This implies some kind | |
2940 | * of global optimization. We currently only optimize within a single macro. | |
2941 | * For many of the load and store macros if the address is specified as a | |
2942 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
2943 | * first load register 'at' with zero and use it as the base register. The | |
2944 | * mips assembler simply uses register $zero. Just one tiny optimization | |
2945 | * we're missing. | |
2946 | */ | |
2947 | static void | |
2948 | macro (ip) | |
2949 | struct mips_cl_insn *ip; | |
2950 | { | |
670a50eb ILT |
2951 | register int treg, sreg, dreg, breg; |
2952 | int tempreg; | |
2953 | int mask; | |
2954 | int icnt = 0; | |
2955 | int used_at; | |
670a50eb ILT |
2956 | expressionS expr1; |
2957 | const char *s; | |
8358c818 | 2958 | const char *s2; |
670a50eb | 2959 | const char *fmt; |
8358c818 ILT |
2960 | int likely = 0; |
2961 | int dbl = 0; | |
2962 | int coproc = 0; | |
b2b8c24e | 2963 | int lr = 0; |
6e8dda9c | 2964 | offsetT maxnum; |
adcf2b9d | 2965 | int off; |
9226253a | 2966 | bfd_reloc_code_real_type r; |
0dd2d296 | 2967 | char *p; |
55933a58 | 2968 | int hold_mips_optimize; |
670a50eb | 2969 | |
cc5703cd ILT |
2970 | assert (! mips16); |
2971 | ||
670a50eb ILT |
2972 | treg = (ip->insn_opcode >> 16) & 0x1f; |
2973 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
2974 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
2975 | mask = ip->insn_mo->mask; | |
2976 | ||
5ac34ac3 ILT |
2977 | expr1.X_op = O_constant; |
2978 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
2979 | expr1.X_add_symbol = NULL; |
2980 | expr1.X_add_number = 1; | |
2981 | ||
2982 | switch (mask) | |
2983 | { | |
6e8dda9c ILT |
2984 | case M_DABS: |
2985 | dbl = 1; | |
3d3c5039 | 2986 | case M_ABS: |
6e8dda9c ILT |
2987 | /* bgez $a0,.+12 |
2988 | move v0,$a0 | |
2989 | sub v0,$zero,$a0 | |
2990 | */ | |
3d3c5039 | 2991 | |
fbcfacb7 | 2992 | mips_emit_delays (true); |
becfe05e | 2993 | ++mips_noreorder; |
0dd2d296 | 2994 | mips_any_noreorder = 1; |
3d3c5039 | 2995 | |
670a50eb | 2996 | expr1.X_add_number = 8; |
0dd2d296 | 2997 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 2998 | if (dreg == sreg) |
0dd2d296 | 2999 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3000 | else |
0dd2d296 ILT |
3001 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3002 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3003 | dbl ? "dsub" : "sub", |
3004 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3005 | |
becfe05e | 3006 | --mips_noreorder; |
670a50eb | 3007 | return; |
3d3c5039 ILT |
3008 | |
3009 | case M_ADD_I: | |
8358c818 ILT |
3010 | s = "addi"; |
3011 | s2 = "add"; | |
3012 | goto do_addi; | |
3d3c5039 | 3013 | case M_ADDU_I: |
8358c818 ILT |
3014 | s = "addiu"; |
3015 | s2 = "addu"; | |
3016 | goto do_addi; | |
3017 | case M_DADD_I: | |
6e8dda9c | 3018 | dbl = 1; |
8358c818 ILT |
3019 | s = "daddi"; |
3020 | s2 = "dadd"; | |
3021 | goto do_addi; | |
3022 | case M_DADDU_I: | |
6e8dda9c | 3023 | dbl = 1; |
8358c818 ILT |
3024 | s = "daddiu"; |
3025 | s2 = "daddu"; | |
3026 | do_addi: | |
6e8dda9c | 3027 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3028 | { |
0dd2d296 | 3029 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3030 | (int) BFD_RELOC_LO16); |
670a50eb | 3031 | return; |
3d3c5039 | 3032 | } |
d8a1c247 | 3033 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3034 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3035 | break; |
3d3c5039 ILT |
3036 | |
3037 | case M_AND_I: | |
6e8dda9c ILT |
3038 | s = "andi"; |
3039 | s2 = "and"; | |
3040 | goto do_bit; | |
3d3c5039 | 3041 | case M_OR_I: |
6e8dda9c ILT |
3042 | s = "ori"; |
3043 | s2 = "or"; | |
3044 | goto do_bit; | |
3d3c5039 | 3045 | case M_NOR_I: |
6e8dda9c ILT |
3046 | s = ""; |
3047 | s2 = "nor"; | |
3048 | goto do_bit; | |
3d3c5039 | 3049 | case M_XOR_I: |
6e8dda9c ILT |
3050 | s = "xori"; |
3051 | s2 = "xor"; | |
3052 | do_bit: | |
3053 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3054 | { |
6e8dda9c | 3055 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3056 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3057 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3058 | else |
670a50eb | 3059 | { |
0dd2d296 ILT |
3060 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3061 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3062 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3063 | treg, treg, 0); |
3d3c5039 | 3064 | } |
6e8dda9c | 3065 | return; |
3d3c5039 | 3066 | } |
6e8dda9c | 3067 | |
d8a1c247 | 3068 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3069 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3070 | break; |
3d3c5039 ILT |
3071 | |
3072 | case M_BEQ_I: | |
8358c818 ILT |
3073 | s = "beq"; |
3074 | goto beq_i; | |
3075 | case M_BEQL_I: | |
3076 | s = "beql"; | |
3077 | likely = 1; | |
3078 | goto beq_i; | |
3d3c5039 | 3079 | case M_BNE_I: |
8358c818 ILT |
3080 | s = "bne"; |
3081 | goto beq_i; | |
3082 | case M_BNEL_I: | |
3083 | s = "bnel"; | |
3084 | likely = 1; | |
3085 | beq_i: | |
670a50eb ILT |
3086 | if (imm_expr.X_add_number == 0) |
3087 | { | |
0dd2d296 ILT |
3088 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3089 | 0); | |
670a50eb ILT |
3090 | return; |
3091 | } | |
d8a1c247 | 3092 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3093 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3094 | break; |
3d3c5039 | 3095 | |
8358c818 ILT |
3096 | case M_BGEL: |
3097 | likely = 1; | |
3d3c5039 | 3098 | case M_BGE: |
670a50eb ILT |
3099 | if (treg == 0) |
3100 | { | |
0dd2d296 | 3101 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3102 | likely ? "bgezl" : "bgez", |
3103 | "s,p", sreg); | |
670a50eb | 3104 | return; |
3d3c5039 | 3105 | } |
9a7d824a ILT |
3106 | if (sreg == 0) |
3107 | { | |
0dd2d296 | 3108 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3109 | likely ? "blezl" : "blez", |
3110 | "s,p", treg); | |
9a7d824a ILT |
3111 | return; |
3112 | } | |
0dd2d296 ILT |
3113 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3114 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3115 | likely ? "beql" : "beq", |
3116 | "s,t,p", AT, 0); | |
670a50eb | 3117 | break; |
3d3c5039 | 3118 | |
8358c818 ILT |
3119 | case M_BGTL_I: |
3120 | likely = 1; | |
3d3c5039 | 3121 | case M_BGT_I: |
9a7d824a | 3122 | /* check for > max integer */ |
6e8dda9c ILT |
3123 | maxnum = 0x7fffffff; |
3124 | if (mips_isa >= 3) | |
3125 | { | |
3126 | maxnum <<= 16; | |
3127 | maxnum |= 0xffff; | |
3128 | maxnum <<= 16; | |
3129 | maxnum |= 0xffff; | |
3130 | } | |
7b777690 ILT |
3131 | if (imm_expr.X_add_number >= maxnum |
3132 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3133 | { |
3134 | do_false: | |
3135 | /* result is always false */ | |
8358c818 ILT |
3136 | if (! likely) |
3137 | { | |
3138 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3139 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3140 | } |
3141 | else | |
3142 | { | |
3143 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3144 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3145 | "s,t,p", 0, 0); | |
8358c818 | 3146 | } |
9a7d824a ILT |
3147 | return; |
3148 | } | |
670a50eb ILT |
3149 | imm_expr.X_add_number++; |
3150 | /* FALLTHROUGH */ | |
3d3c5039 | 3151 | case M_BGE_I: |
8358c818 ILT |
3152 | case M_BGEL_I: |
3153 | if (mask == M_BGEL_I) | |
3154 | likely = 1; | |
670a50eb ILT |
3155 | if (imm_expr.X_add_number == 0) |
3156 | { | |
0dd2d296 | 3157 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3158 | likely ? "bgezl" : "bgez", |
3159 | "s,p", sreg); | |
670a50eb | 3160 | return; |
3d3c5039 | 3161 | } |
670a50eb ILT |
3162 | if (imm_expr.X_add_number == 1) |
3163 | { | |
0dd2d296 | 3164 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3165 | likely ? "bgtzl" : "bgtz", |
3166 | "s,p", sreg); | |
670a50eb | 3167 | return; |
3d3c5039 | 3168 | } |
6e8dda9c ILT |
3169 | maxnum = 0x7fffffff; |
3170 | if (mips_isa >= 3) | |
3171 | { | |
3172 | maxnum <<= 16; | |
3173 | maxnum |= 0xffff; | |
3174 | maxnum <<= 16; | |
3175 | maxnum |= 0xffff; | |
3176 | } | |
3177 | maxnum = - maxnum - 1; | |
7b777690 ILT |
3178 | if (imm_expr.X_add_number <= maxnum |
3179 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3180 | { |
3181 | do_true: | |
3182 | /* result is always true */ | |
3183 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3184 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3185 | return; |
3186 | } | |
6e8dda9c | 3187 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3188 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3189 | likely ? "beql" : "beq", |
3190 | "s,t,p", AT, 0); | |
670a50eb | 3191 | break; |
3d3c5039 | 3192 | |
8358c818 ILT |
3193 | case M_BGEUL: |
3194 | likely = 1; | |
3d3c5039 | 3195 | case M_BGEU: |
670a50eb | 3196 | if (treg == 0) |
9a7d824a ILT |
3197 | goto do_true; |
3198 | if (sreg == 0) | |
670a50eb | 3199 | { |
0dd2d296 | 3200 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3201 | likely ? "beql" : "beq", |
3202 | "s,t,p", 0, treg); | |
670a50eb | 3203 | return; |
3d3c5039 | 3204 | } |
0dd2d296 ILT |
3205 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3206 | treg); | |
3207 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3208 | likely ? "beql" : "beq", |
3209 | "s,t,p", AT, 0); | |
670a50eb | 3210 | break; |
3d3c5039 | 3211 | |
8358c818 ILT |
3212 | case M_BGTUL_I: |
3213 | likely = 1; | |
9a7d824a | 3214 | case M_BGTU_I: |
6e8dda9c | 3215 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3216 | goto do_false; |
3217 | imm_expr.X_add_number++; | |
3218 | /* FALLTHROUGH */ | |
3d3c5039 | 3219 | case M_BGEU_I: |
8358c818 ILT |
3220 | case M_BGEUL_I: |
3221 | if (mask == M_BGEUL_I) | |
3222 | likely = 1; | |
670a50eb | 3223 | if (imm_expr.X_add_number == 0) |
9a7d824a | 3224 | goto do_true; |
670a50eb ILT |
3225 | if (imm_expr.X_add_number == 1) |
3226 | { | |
0dd2d296 | 3227 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3228 | likely ? "bnel" : "bne", |
3229 | "s,t,p", sreg, 0); | |
670a50eb | 3230 | return; |
3d3c5039 | 3231 | } |
6e8dda9c | 3232 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3233 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3234 | likely ? "beql" : "beq", |
3235 | "s,t,p", AT, 0); | |
670a50eb | 3236 | break; |
3d3c5039 | 3237 | |
8358c818 ILT |
3238 | case M_BGTL: |
3239 | likely = 1; | |
3d3c5039 | 3240 | case M_BGT: |
670a50eb ILT |
3241 | if (treg == 0) |
3242 | { | |
0dd2d296 | 3243 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3244 | likely ? "bgtzl" : "bgtz", |
3245 | "s,p", sreg); | |
670a50eb | 3246 | return; |
3d3c5039 | 3247 | } |
9a7d824a ILT |
3248 | if (sreg == 0) |
3249 | { | |
0dd2d296 | 3250 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3251 | likely ? "bltzl" : "bltz", |
3252 | "s,p", treg); | |
9a7d824a ILT |
3253 | return; |
3254 | } | |
0dd2d296 ILT |
3255 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3256 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3257 | likely ? "bnel" : "bne", |
3258 | "s,t,p", AT, 0); | |
670a50eb | 3259 | break; |
3d3c5039 | 3260 | |
8358c818 ILT |
3261 | case M_BGTUL: |
3262 | likely = 1; | |
3d3c5039 | 3263 | case M_BGTU: |
670a50eb ILT |
3264 | if (treg == 0) |
3265 | { | |
0dd2d296 | 3266 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3267 | likely ? "bnel" : "bne", |
3268 | "s,t,p", sreg, 0); | |
670a50eb | 3269 | return; |
3d3c5039 | 3270 | } |
9a7d824a ILT |
3271 | if (sreg == 0) |
3272 | goto do_false; | |
0dd2d296 ILT |
3273 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3274 | sreg); | |
3275 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3276 | likely ? "bnel" : "bne", |
3277 | "s,t,p", AT, 0); | |
670a50eb | 3278 | break; |
3d3c5039 | 3279 | |
8358c818 ILT |
3280 | case M_BLEL: |
3281 | likely = 1; | |
3d3c5039 | 3282 | case M_BLE: |
670a50eb ILT |
3283 | if (treg == 0) |
3284 | { | |
0dd2d296 | 3285 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3286 | likely ? "blezl" : "blez", |
3287 | "s,p", sreg); | |
670a50eb ILT |
3288 | return; |
3289 | } | |
9a7d824a ILT |
3290 | if (sreg == 0) |
3291 | { | |
0dd2d296 | 3292 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3293 | likely ? "bgezl" : "bgez", |
3294 | "s,p", treg); | |
9a7d824a ILT |
3295 | return; |
3296 | } | |
0dd2d296 ILT |
3297 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3298 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3299 | likely ? "beql" : "beq", |
3300 | "s,t,p", AT, 0); | |
670a50eb | 3301 | break; |
3d3c5039 | 3302 | |
8358c818 ILT |
3303 | case M_BLEL_I: |
3304 | likely = 1; | |
3d3c5039 | 3305 | case M_BLE_I: |
6e8dda9c ILT |
3306 | maxnum = 0x7fffffff; |
3307 | if (mips_isa >= 3) | |
3308 | { | |
3309 | maxnum <<= 16; | |
3310 | maxnum |= 0xffff; | |
3311 | maxnum <<= 16; | |
3312 | maxnum |= 0xffff; | |
3313 | } | |
7b777690 ILT |
3314 | if (imm_expr.X_add_number >= maxnum |
3315 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
3316 | goto do_true; |
3317 | imm_expr.X_add_number++; | |
3318 | /* FALLTHROUGH */ | |
9a7d824a | 3319 | case M_BLT_I: |
8358c818 ILT |
3320 | case M_BLTL_I: |
3321 | if (mask == M_BLTL_I) | |
3322 | likely = 1; | |
670a50eb ILT |
3323 | if (imm_expr.X_add_number == 0) |
3324 | { | |
0dd2d296 | 3325 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3326 | likely ? "bltzl" : "bltz", |
3327 | "s,p", sreg); | |
670a50eb ILT |
3328 | return; |
3329 | } | |
9a7d824a | 3330 | if (imm_expr.X_add_number == 1) |
670a50eb | 3331 | { |
0dd2d296 | 3332 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3333 | likely ? "blezl" : "blez", |
3334 | "s,p", sreg); | |
670a50eb ILT |
3335 | return; |
3336 | } | |
6e8dda9c | 3337 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3338 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3339 | likely ? "bnel" : "bne", |
3340 | "s,t,p", AT, 0); | |
670a50eb | 3341 | break; |
3d3c5039 | 3342 | |
8358c818 ILT |
3343 | case M_BLEUL: |
3344 | likely = 1; | |
3d3c5039 | 3345 | case M_BLEU: |
670a50eb ILT |
3346 | if (treg == 0) |
3347 | { | |
0dd2d296 | 3348 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3349 | likely ? "beql" : "beq", |
3350 | "s,t,p", sreg, 0); | |
670a50eb | 3351 | return; |
3d3c5039 | 3352 | } |
9a7d824a ILT |
3353 | if (sreg == 0) |
3354 | goto do_true; | |
0dd2d296 ILT |
3355 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3356 | sreg); | |
3357 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3358 | likely ? "beql" : "beq", |
3359 | "s,t,p", AT, 0); | |
670a50eb | 3360 | break; |
3d3c5039 | 3361 | |
8358c818 ILT |
3362 | case M_BLEUL_I: |
3363 | likely = 1; | |
3d3c5039 | 3364 | case M_BLEU_I: |
6e8dda9c | 3365 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
3366 | goto do_true; |
3367 | imm_expr.X_add_number++; | |
3368 | /* FALLTHROUGH */ | |
9a7d824a | 3369 | case M_BLTU_I: |
8358c818 ILT |
3370 | case M_BLTUL_I: |
3371 | if (mask == M_BLTUL_I) | |
3372 | likely = 1; | |
670a50eb | 3373 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
3374 | goto do_false; |
3375 | if (imm_expr.X_add_number == 1) | |
670a50eb | 3376 | { |
0dd2d296 | 3377 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3378 | likely ? "beql" : "beq", |
3379 | "s,t,p", sreg, 0); | |
670a50eb | 3380 | return; |
3d3c5039 | 3381 | } |
6e8dda9c | 3382 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3383 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3384 | likely ? "bnel" : "bne", |
3385 | "s,t,p", AT, 0); | |
670a50eb | 3386 | break; |
3d3c5039 | 3387 | |
8358c818 ILT |
3388 | case M_BLTL: |
3389 | likely = 1; | |
3d3c5039 | 3390 | case M_BLT: |
670a50eb ILT |
3391 | if (treg == 0) |
3392 | { | |
0dd2d296 | 3393 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3394 | likely ? "bltzl" : "bltz", |
3395 | "s,p", sreg); | |
670a50eb | 3396 | return; |
3d3c5039 | 3397 | } |
9a7d824a | 3398 | if (sreg == 0) |
670a50eb | 3399 | { |
0dd2d296 | 3400 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3401 | likely ? "bgtzl" : "bgtz", |
3402 | "s,p", treg); | |
670a50eb | 3403 | return; |
3d3c5039 | 3404 | } |
0dd2d296 ILT |
3405 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3406 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3407 | likely ? "bnel" : "bne", |
3408 | "s,t,p", AT, 0); | |
670a50eb | 3409 | break; |
3d3c5039 | 3410 | |
8358c818 ILT |
3411 | case M_BLTUL: |
3412 | likely = 1; | |
3d3c5039 | 3413 | case M_BLTU: |
670a50eb | 3414 | if (treg == 0) |
9a7d824a ILT |
3415 | goto do_false; |
3416 | if (sreg == 0) | |
670a50eb | 3417 | { |
0dd2d296 | 3418 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3419 | likely ? "bnel" : "bne", |
3420 | "s,t,p", 0, treg); | |
670a50eb ILT |
3421 | return; |
3422 | } | |
0dd2d296 ILT |
3423 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3424 | treg); | |
3425 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3426 | likely ? "bnel" : "bne", |
3427 | "s,t,p", AT, 0); | |
670a50eb | 3428 | break; |
3d3c5039 | 3429 | |
8358c818 ILT |
3430 | case M_DDIV_3: |
3431 | dbl = 1; | |
3d3c5039 | 3432 | case M_DIV_3: |
8358c818 ILT |
3433 | s = "mflo"; |
3434 | goto do_div3; | |
3435 | case M_DREM_3: | |
3436 | dbl = 1; | |
3d3c5039 | 3437 | case M_REM_3: |
8358c818 ILT |
3438 | s = "mfhi"; |
3439 | do_div3: | |
670a50eb ILT |
3440 | if (treg == 0) |
3441 | { | |
3442 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3443 | if (mips_trap) |
3444 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3445 | else | |
3446 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3447 | return; |
3448 | } | |
3449 | ||
fbcfacb7 | 3450 | mips_emit_delays (true); |
becfe05e | 3451 | ++mips_noreorder; |
0dd2d296 ILT |
3452 | mips_any_noreorder = 1; |
3453 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3454 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3455 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3456 | if (mips_trap) |
3457 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3458 | else | |
3459 | { | |
3460 | expr1.X_add_number = 8; | |
3461 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3462 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3463 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3464 | } | |
670a50eb | 3465 | expr1.X_add_number = -1; |
0dd2d296 | 3466 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3467 | dbl ? "daddiu" : "addiu", |
9226253a | 3468 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3469 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3470 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3471 | if (dbl) |
3472 | { | |
3473 | expr1.X_add_number = 1; | |
0dd2d296 | 3474 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3475 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3476 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3477 | 31); | |
8358c818 ILT |
3478 | } |
3479 | else | |
3480 | { | |
3481 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3482 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3483 | (int) BFD_RELOC_HI16); | |
8358c818 | 3484 | } |
8ea7f4e8 ILT |
3485 | if (mips_trap) |
3486 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3487 | else | |
3488 | { | |
3489 | expr1.X_add_number = 8; | |
3490 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3491 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3492 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3493 | } | |
becfe05e | 3494 | --mips_noreorder; |
0dd2d296 | 3495 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3496 | break; |
3d3c5039 ILT |
3497 | |
3498 | case M_DIV_3I: | |
8358c818 ILT |
3499 | s = "div"; |
3500 | s2 = "mflo"; | |
3501 | goto do_divi; | |
3d3c5039 | 3502 | case M_DIVU_3I: |
8358c818 ILT |
3503 | s = "divu"; |
3504 | s2 = "mflo"; | |
3505 | goto do_divi; | |
3d3c5039 | 3506 | case M_REM_3I: |
8358c818 ILT |
3507 | s = "div"; |
3508 | s2 = "mfhi"; | |
3509 | goto do_divi; | |
3d3c5039 | 3510 | case M_REMU_3I: |
8358c818 ILT |
3511 | s = "divu"; |
3512 | s2 = "mfhi"; | |
3513 | goto do_divi; | |
3514 | case M_DDIV_3I: | |
3515 | dbl = 1; | |
3516 | s = "ddiv"; | |
3517 | s2 = "mflo"; | |
3518 | goto do_divi; | |
3519 | case M_DDIVU_3I: | |
3520 | dbl = 1; | |
3521 | s = "ddivu"; | |
3522 | s2 = "mflo"; | |
3523 | goto do_divi; | |
3524 | case M_DREM_3I: | |
3525 | dbl = 1; | |
3526 | s = "ddiv"; | |
3527 | s2 = "mfhi"; | |
3528 | goto do_divi; | |
3529 | case M_DREMU_3I: | |
3530 | dbl = 1; | |
3531 | s = "ddivu"; | |
3532 | s2 = "mfhi"; | |
3533 | do_divi: | |
670a50eb ILT |
3534 | if (imm_expr.X_add_number == 0) |
3535 | { | |
3536 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3537 | if (mips_trap) |
3538 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3539 | else | |
3540 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3541 | return; |
3542 | } | |
3543 | if (imm_expr.X_add_number == 1) | |
3544 | { | |
8358c818 | 3545 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3546 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3547 | sreg); | |
3d3c5039 | 3548 | else |
0dd2d296 | 3549 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3550 | return; |
3551 | } | |
8358c818 ILT |
3552 | if (imm_expr.X_add_number == -1 |
3553 | && s[strlen (s) - 1] != 'u') | |
3554 | { | |
3555 | if (strcmp (s2, "mflo") == 0) | |
3556 | { | |
3557 | if (dbl) | |
0dd2d296 ILT |
3558 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3559 | sreg); | |
8358c818 | 3560 | else |
0dd2d296 ILT |
3561 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3562 | sreg); | |
8358c818 ILT |
3563 | } |
3564 | else | |
0dd2d296 | 3565 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3566 | return; |
3567 | } | |
3d3c5039 | 3568 | |
d8a1c247 | 3569 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3570 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3571 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3572 | break; |
3573 | ||
3574 | case M_DIVU_3: | |
8358c818 ILT |
3575 | s = "divu"; |
3576 | s2 = "mflo"; | |
3577 | goto do_divu3; | |
670a50eb | 3578 | case M_REMU_3: |
8358c818 ILT |
3579 | s = "divu"; |
3580 | s2 = "mfhi"; | |
3581 | goto do_divu3; | |
3582 | case M_DDIVU_3: | |
3583 | s = "ddivu"; | |
3584 | s2 = "mflo"; | |
3585 | goto do_divu3; | |
3586 | case M_DREMU_3: | |
3587 | s = "ddivu"; | |
3588 | s2 = "mfhi"; | |
3589 | do_divu3: | |
fbcfacb7 | 3590 | mips_emit_delays (true); |
becfe05e | 3591 | ++mips_noreorder; |
0dd2d296 ILT |
3592 | mips_any_noreorder = 1; |
3593 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3594 | if (mips_trap) |
3595 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3596 | else | |
3597 | { | |
3598 | expr1.X_add_number = 8; | |
3599 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3600 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3601 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3602 | } | |
becfe05e | 3603 | --mips_noreorder; |
0dd2d296 | 3604 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3605 | return; |
3d3c5039 | 3606 | |
d8a1c247 KR |
3607 | case M_DLA_AB: |
3608 | dbl = 1; | |
0dd2d296 | 3609 | case M_LA_AB: |
d9aba805 ILT |
3610 | /* Load the address of a symbol into a register. If breg is not |
3611 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3612 | |
3613 | /* When generating embedded PIC code, we permit expressions of | |
3614 | the form | |
3615 | la $4,foo-bar | |
3616 | where bar is an address in the .text section. These are used | |
3617 | when getting the addresses of functions. We don't permit | |
3618 | X_add_number to be non-zero, because if the symbol is | |
3619 | external the relaxing code needs to know that any addend is | |
3620 | purely the offset to X_op_symbol. */ | |
3621 | if (mips_pic == EMBEDDED_PIC | |
3622 | && offset_expr.X_op == O_subtract | |
3623 | && now_seg == text_section | |
847a01cd ILT |
3624 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3625 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3626 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3627 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3628 | ->sy_value.X_add_symbol) | |
3629 | == text_section))) | |
ecd4ca1c ILT |
3630 | && breg == 0 |
3631 | && offset_expr.X_add_number == 0) | |
3632 | { | |
3633 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3634 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3635 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3636 | mips_isa < 3 ? "addiu" : "daddiu", | |
3637 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
3638 | return; | |
3639 | } | |
3640 | ||
0dd2d296 ILT |
3641 | if (offset_expr.X_op != O_symbol |
3642 | && offset_expr.X_op != O_constant) | |
670a50eb | 3643 | { |
0dd2d296 ILT |
3644 | as_bad ("expression too complex"); |
3645 | offset_expr.X_op = O_constant; | |
3646 | } | |
3647 | ||
3648 | if (treg == breg) | |
3649 | { | |
3650 | tempreg = AT; | |
3651 | used_at = 1; | |
3d3c5039 | 3652 | } |
670a50eb ILT |
3653 | else |
3654 | { | |
0dd2d296 ILT |
3655 | tempreg = treg; |
3656 | used_at = 0; | |
670a50eb | 3657 | } |
3d3c5039 | 3658 | |
5ac34ac3 | 3659 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 3660 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 3661 | else if (mips_pic == NO_PIC) |
670a50eb | 3662 | { |
0dd2d296 ILT |
3663 | /* If this is a reference to an GP relative symbol, we want |
3664 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3665 | Otherwise we want | |
3666 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
3667 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3668 | If we have a constant, we need two instructions anyhow, | |
3669 | so we may as well always use the latter form. */ | |
7a15a226 | 3670 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 3671 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
3672 | p = NULL; |
3673 | else | |
3674 | { | |
8ea7f4e8 | 3675 | frag_grow (20); |
0dd2d296 ILT |
3676 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3677 | mips_isa < 3 ? "addiu" : "daddiu", | |
3678 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3679 | p = frag_var (rs_machine_dependent, 8, 0, | |
3680 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3681 | mips_warn_about_macros), | |
3682 | offset_expr.X_add_symbol, (long) 0, | |
3683 | (char *) NULL); | |
3684 | } | |
3685 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
3686 | if (p != NULL) | |
3687 | p += 4; | |
3688 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 3689 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3690 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
3691 | } | |
fb251650 | 3692 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3693 | { |
3694 | /* If this is a reference to an external symbol, and there | |
3695 | is no constant, we want | |
3696 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3697 | For a local symbol, we want | |
3698 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3699 | nop | |
3700 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3701 | ||
3702 | If we have a small constant, and this is a reference to | |
3703 | an external symbol, we want | |
3704 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3705 | nop | |
3706 | addiu $tempreg,$tempreg,<constant> | |
3707 | For a local symbol, we want the same instruction | |
3708 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3709 | addiu instruction. | |
3710 | ||
3711 | If we have a large constant, and this is a reference to | |
3712 | an external symbol, we want | |
3713 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3714 | lui $at,<hiconstant> | |
3715 | addiu $at,$at,<loconstant> | |
3716 | addu $tempreg,$tempreg,$at | |
3717 | For a local symbol, we want the same instruction | |
3718 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
3719 | addiu instruction. */ | |
3720 | expr1.X_add_number = offset_expr.X_add_number; | |
3721 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 3722 | frag_grow (32); |
0dd2d296 | 3723 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 3724 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
3725 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3726 | if (expr1.X_add_number == 0) | |
3727 | { | |
3728 | int off; | |
3729 | ||
3730 | if (breg == 0) | |
3731 | off = 0; | |
3732 | else | |
3733 | { | |
3734 | /* We're going to put in an addu instruction using | |
3735 | tempreg, so we may as well insert the nop right | |
3736 | now. */ | |
3737 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3738 | "nop", ""); | |
3739 | off = 4; | |
3740 | } | |
3741 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
3742 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
3743 | (breg == 0 | |
3744 | ? mips_warn_about_macros | |
3745 | : 0)), | |
3746 | offset_expr.X_add_symbol, (long) 0, | |
3747 | (char *) NULL); | |
3748 | if (breg == 0) | |
3749 | { | |
3750 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3751 | p += 4; | |
3752 | } | |
3753 | macro_build (p, &icnt, &expr1, | |
3754 | mips_isa < 3 ? "addiu" : "daddiu", | |
3755 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3756 | /* FIXME: If breg == 0, and the next instruction uses | |
3757 | $tempreg, then if this variant case is used an extra | |
3758 | nop will be generated. */ | |
3759 | } | |
3760 | else if (expr1.X_add_number >= -0x8000 | |
3761 | && expr1.X_add_number < 0x8000) | |
3762 | { | |
3763 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3764 | "nop", ""); | |
3765 | macro_build ((char *) NULL, &icnt, &expr1, | |
3766 | mips_isa < 3 ? "addiu" : "daddiu", | |
3767 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3768 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3769 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
3770 | offset_expr.X_add_symbol, (long) 0, | |
3771 | (char *) NULL); | |
3772 | } | |
3773 | else | |
3774 | { | |
3775 | int off1; | |
3776 | ||
3777 | /* If we are going to add in a base register, and the | |
3778 | target register and the base register are the same, | |
3779 | then we are using AT as a temporary register. Since | |
3780 | we want to load the constant into AT, we add our | |
3781 | current AT (from the global offset table) and the | |
3782 | register into the register now, and pretend we were | |
3783 | not using a base register. */ | |
3784 | if (breg != treg) | |
3785 | off1 = 0; | |
3786 | else | |
3787 | { | |
3788 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3789 | "nop", ""); | |
3790 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3791 | mips_isa < 3 ? "addu" : "daddu", | |
3792 | "d,v,t", treg, AT, breg); | |
3793 | breg = 0; | |
3794 | tempreg = treg; | |
3795 | off1 = -8; | |
3796 | } | |
3797 | ||
55933a58 ILT |
3798 | /* Set mips_optimize around the lui instruction to avoid |
3799 | inserting an unnecessary nop after the lw. */ | |
3800 | hold_mips_optimize = mips_optimize; | |
3801 | mips_optimize = 2; | |
0dd2d296 | 3802 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
3803 | mips_optimize = hold_mips_optimize; |
3804 | ||
0dd2d296 ILT |
3805 | macro_build ((char *) NULL, &icnt, &expr1, |
3806 | mips_isa < 3 ? "addiu" : "daddiu", | |
3807 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3808 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3809 | mips_isa < 3 ? "addu" : "daddu", | |
3810 | "d,v,t", tempreg, tempreg, AT); | |
3811 | (void) frag_var (rs_machine_dependent, 0, 0, | |
3812 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
3813 | offset_expr.X_add_symbol, (long) 0, | |
3814 | (char *) NULL); | |
3815 | used_at = 1; | |
3816 | } | |
670a50eb | 3817 | } |
fb251650 ILT |
3818 | else if (mips_pic == SVR4_PIC) |
3819 | { | |
3820 | int gpdel; | |
3821 | ||
3822 | /* This is the large GOT case. If this is a reference to an | |
3823 | external symbol, and there is no constant, we want | |
3824 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3825 | addu $tempreg,$tempreg,$gp | |
3826 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3827 | For a local symbol, we want | |
3828 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3829 | nop | |
3830 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
3831 | ||
3832 | If we have a small constant, and this is a reference to | |
3833 | an external symbol, we want | |
3834 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3835 | addu $tempreg,$tempreg,$gp | |
3836 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3837 | nop | |
3838 | addiu $tempreg,$tempreg,<constant> | |
3839 | For a local symbol, we want | |
3840 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3841 | nop | |
3842 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
3843 | ||
3844 | If we have a large constant, and this is a reference to | |
3845 | an external symbol, we want | |
3846 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3847 | addu $tempreg,$tempreg,$gp | |
3848 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
3849 | lui $at,<hiconstant> | |
3850 | addiu $at,$at,<loconstant> | |
3851 | addu $tempreg,$tempreg,$at | |
3852 | For a local symbol, we want | |
3853 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3854 | lui $at,<hiconstant> | |
3855 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
3856 | addu $tempreg,$tempreg,$at | |
3857 | */ | |
3858 | expr1.X_add_number = offset_expr.X_add_number; | |
3859 | offset_expr.X_add_number = 0; | |
3860 | frag_grow (52); | |
3861 | if (reg_needs_delay (GP)) | |
3862 | gpdel = 4; | |
3863 | else | |
3864 | gpdel = 0; | |
3865 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3866 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
3867 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3868 | mips_isa < 3 ? "addu" : "daddu", | |
3869 | "d,v,t", tempreg, tempreg, GP); | |
3870 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3871 | dbl ? "ld" : "lw", | |
3872 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
3873 | tempreg); | |
3874 | if (expr1.X_add_number == 0) | |
3875 | { | |
3876 | int off; | |
3877 | ||
3878 | if (breg == 0) | |
3879 | off = 0; | |
3880 | else | |
3881 | { | |
3882 | /* We're going to put in an addu instruction using | |
3883 | tempreg, so we may as well insert the nop right | |
3884 | now. */ | |
3885 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3886 | "nop", ""); | |
3887 | off = 4; | |
3888 | } | |
3889 | ||
3890 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3891 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
3892 | 8 + gpdel, 0, | |
3893 | (breg == 0 | |
3894 | ? mips_warn_about_macros | |
3895 | : 0)), | |
3896 | offset_expr.X_add_symbol, (long) 0, | |
3897 | (char *) NULL); | |
3898 | } | |
3899 | else if (expr1.X_add_number >= -0x8000 | |
3900 | && expr1.X_add_number < 0x8000) | |
3901 | { | |
3902 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3903 | "nop", ""); | |
3904 | macro_build ((char *) NULL, &icnt, &expr1, | |
3905 | mips_isa < 3 ? "addiu" : "daddiu", | |
3906 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3907 | ||
3908 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
3909 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
3910 | (breg == 0 | |
3911 | ? mips_warn_about_macros | |
3912 | : 0)), | |
3913 | offset_expr.X_add_symbol, (long) 0, | |
3914 | (char *) NULL); | |
3915 | } | |
3916 | else | |
3917 | { | |
3918 | int adj, dreg; | |
3919 | ||
3920 | /* If we are going to add in a base register, and the | |
3921 | target register and the base register are the same, | |
3922 | then we are using AT as a temporary register. Since | |
3923 | we want to load the constant into AT, we add our | |
3924 | current AT (from the global offset table) and the | |
3925 | register into the register now, and pretend we were | |
3926 | not using a base register. */ | |
3927 | if (breg != treg) | |
3928 | { | |
3929 | adj = 0; | |
3930 | dreg = tempreg; | |
3931 | } | |
3932 | else | |
3933 | { | |
3934 | assert (tempreg == AT); | |
3935 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3936 | "nop", ""); | |
3937 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3938 | mips_isa < 3 ? "addu" : "daddu", | |
3939 | "d,v,t", treg, AT, breg); | |
3940 | dreg = treg; | |
3941 | adj = 8; | |
3942 | } | |
3943 | ||
3944 | /* Set mips_optimize around the lui instruction to avoid | |
3945 | inserting an unnecessary nop after the lw. */ | |
3946 | hold_mips_optimize = mips_optimize; | |
3947 | mips_optimize = 2; | |
3948 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
3949 | mips_optimize = hold_mips_optimize; | |
3950 | ||
3951 | macro_build ((char *) NULL, &icnt, &expr1, | |
3952 | mips_isa < 3 ? "addiu" : "daddiu", | |
3953 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
3954 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3955 | mips_isa < 3 ? "addu" : "daddu", | |
3956 | "d,v,t", dreg, dreg, AT); | |
3957 | ||
3958 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
3959 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
3960 | 8 + gpdel, 0, | |
3961 | (breg == 0 | |
3962 | ? mips_warn_about_macros | |
3963 | : 0)), | |
3964 | offset_expr.X_add_symbol, (long) 0, | |
3965 | (char *) NULL); | |
3966 | ||
3967 | used_at = 1; | |
3968 | } | |
3969 | ||
3970 | if (gpdel > 0) | |
3971 | { | |
3972 | /* This is needed because this instruction uses $gp, but | |
3973 | the first instruction on the main stream does not. */ | |
3974 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3975 | p += 4; | |
3976 | } | |
3977 | macro_build (p, &icnt, &offset_expr, | |
3978 | dbl ? "ld" : "lw", | |
3979 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3980 | p += 4; | |
3981 | if (expr1.X_add_number >= -0x8000 | |
3982 | && expr1.X_add_number < 0x8000) | |
3983 | { | |
3984 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
3985 | p += 4; | |
3986 | macro_build (p, &icnt, &expr1, | |
3987 | mips_isa < 3 ? "addiu" : "daddiu", | |
3988 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
3989 | /* FIXME: If add_number is 0, and there was no base | |
3990 | register, the external symbol case ended with a load, | |
3991 | so if the symbol turns out to not be external, and | |
3992 | the next instruction uses tempreg, an unnecessary nop | |
3993 | will be inserted. */ | |
3994 | } | |
3995 | else | |
3996 | { | |
3997 | if (breg == treg) | |
3998 | { | |
3999 | /* We must add in the base register now, as in the | |
4000 | external symbol case. */ | |
4001 | assert (tempreg == AT); | |
4002 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4003 | p += 4; | |
4004 | macro_build (p, &icnt, (expressionS *) NULL, | |
4005 | mips_isa < 3 ? "addu" : "daddu", | |
4006 | "d,v,t", treg, AT, breg); | |
4007 | p += 4; | |
4008 | tempreg = treg; | |
4009 | /* We set breg to 0 because we have arranged to add | |
4010 | it in in both cases. */ | |
4011 | breg = 0; | |
4012 | } | |
4013 | ||
4014 | macro_build_lui (p, &icnt, &expr1, AT); | |
4015 | p += 4; | |
4016 | macro_build (p, &icnt, &expr1, | |
4017 | mips_isa < 3 ? "addiu" : "daddiu", | |
4018 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4019 | p += 4; | |
4020 | macro_build (p, &icnt, (expressionS *) NULL, | |
4021 | mips_isa < 3 ? "addu" : "daddu", | |
4022 | "d,v,t", tempreg, tempreg, AT); | |
4023 | p += 4; | |
4024 | } | |
4025 | } | |
d9aba805 ILT |
4026 | else if (mips_pic == EMBEDDED_PIC) |
4027 | { | |
4028 | /* We use | |
4029 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4030 | */ | |
4031 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4032 | mips_isa < 3 ? "addiu" : "daddiu", | |
4033 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4034 | } | |
4035 | else | |
4036 | abort (); | |
0dd2d296 | 4037 | |
670a50eb | 4038 | if (breg != 0) |
0dd2d296 ILT |
4039 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4040 | mips_isa < 3 ? "addu" : "daddu", | |
4041 | "d,v,t", treg, tempreg, breg); | |
4042 | ||
4043 | if (! used_at) | |
4044 | return; | |
4045 | ||
4046 | break; | |
4047 | ||
4048 | case M_J_A: | |
4049 | /* The j instruction may not be used in PIC code, since it | |
4050 | requires an absolute address. We convert it to a b | |
4051 | instruction. */ | |
d9aba805 | 4052 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4053 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4054 | else | |
4055 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4056 | return; |
3d3c5039 | 4057 | |
9226253a ILT |
4058 | /* The jal instructions must be handled as macros because when |
4059 | generating PIC code they expand to multi-instruction | |
4060 | sequences. Normally they are simple instructions. */ | |
4061 | case M_JAL_1: | |
4062 | dreg = RA; | |
4063 | /* Fall through. */ | |
4064 | case M_JAL_2: | |
d9aba805 ILT |
4065 | if (mips_pic == NO_PIC |
4066 | || mips_pic == EMBEDDED_PIC) | |
4067 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4068 | "d,s", dreg, sreg); | |
4069 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4070 | { |
d9aba805 ILT |
4071 | if (sreg != PIC_CALL_REG) |
4072 | as_warn ("MIPS PIC call to register other than $25"); | |
4073 | ||
0dd2d296 ILT |
4074 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4075 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4076 | if (mips_cprestore_offset < 0) |
4077 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4078 | else | |
4079 | { | |
4080 | expr1.X_add_number = mips_cprestore_offset; | |
4081 | macro_build ((char *) NULL, &icnt, &expr1, | |
4082 | mips_isa < 3 ? "lw" : "ld", | |
4083 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4084 | } | |
9226253a | 4085 | } |
0dd2d296 | 4086 | else |
d9aba805 ILT |
4087 | abort (); |
4088 | ||
9226253a ILT |
4089 | return; |
4090 | ||
4091 | case M_JAL_A: | |
d9aba805 ILT |
4092 | if (mips_pic == NO_PIC) |
4093 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4094 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4095 | { |
fb251650 ILT |
4096 | /* If this is a reference to an external symbol, and we are |
4097 | using a small GOT, we want | |
d9aba805 ILT |
4098 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4099 | nop | |
4100 | jalr $25 | |
4101 | nop | |
4102 | lw $gp,cprestore($sp) | |
4103 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4104 | pseudo-op. If we are using a big GOT, we want |
4105 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4106 | addu $25,$25,$gp | |
4107 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4108 | nop | |
4109 | jalr $25 | |
4110 | nop | |
4111 | lw $gp,cprestore($sp) | |
4112 | If the symbol is not external, we want | |
d9aba805 ILT |
4113 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4114 | nop | |
4115 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4116 | jalr $25 | |
4117 | nop | |
fb251650 ILT |
4118 | lw $gp,cprestore($sp) */ |
4119 | frag_grow (40); | |
4120 | if (! mips_big_got) | |
4121 | { | |
4122 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4123 | mips_isa < 3 ? "lw" : "ld", | |
4124 | "t,o(b)", PIC_CALL_REG, | |
4125 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4126 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4127 | "nop", ""); | |
4128 | p = frag_var (rs_machine_dependent, 4, 0, | |
4129 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4130 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4131 | } | |
4132 | else | |
4133 | { | |
4134 | int gpdel; | |
4135 | ||
4136 | if (reg_needs_delay (GP)) | |
4137 | gpdel = 4; | |
4138 | else | |
4139 | gpdel = 0; | |
4140 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4141 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4142 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4143 | mips_isa < 3 ? "addu" : "daddu", | |
4144 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4145 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4146 | mips_isa < 3 ? "lw" : "ld", | |
4147 | "t,o(b)", PIC_CALL_REG, | |
4148 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4149 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4150 | "nop", ""); | |
4151 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4152 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4153 | 0, 0), | |
4154 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4155 | if (gpdel > 0) | |
4156 | { | |
4157 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4158 | p += 4; | |
4159 | } | |
4160 | macro_build (p, &icnt, &offset_expr, | |
4161 | mips_isa < 3 ? "lw" : "ld", | |
4162 | "t,o(b)", PIC_CALL_REG, | |
4163 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4164 | p += 4; | |
4165 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4166 | p += 4; | |
4167 | } | |
d9aba805 ILT |
4168 | macro_build (p, &icnt, &offset_expr, |
4169 | mips_isa < 3 ? "addiu" : "daddiu", | |
4170 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4171 | (int) BFD_RELOC_LO16); | |
4172 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4173 | "jalr", "s", PIC_CALL_REG); | |
4174 | if (mips_cprestore_offset < 0) | |
4175 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4176 | else | |
4177 | { | |
4178 | if (mips_noreorder) | |
4179 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4180 | "nop", ""); | |
4181 | expr1.X_add_number = mips_cprestore_offset; | |
4182 | macro_build ((char *) NULL, &icnt, &expr1, | |
4183 | mips_isa < 3 ? "lw" : "ld", | |
4184 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4185 | mips_frame_reg); | |
4186 | } | |
0dd2d296 | 4187 | } |
d9aba805 | 4188 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4189 | { |
4190 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4191 | /* The linker may expand the call to a longer sequence which | |
4192 | uses $at, so we must break rather than return. */ | |
4193 | break; | |
4194 | } | |
d9aba805 ILT |
4195 | else |
4196 | abort (); | |
4197 | ||
9226253a ILT |
4198 | return; |
4199 | ||
3d3c5039 | 4200 | case M_LB_AB: |
670a50eb ILT |
4201 | s = "lb"; |
4202 | goto ld; | |
3d3c5039 | 4203 | case M_LBU_AB: |
670a50eb ILT |
4204 | s = "lbu"; |
4205 | goto ld; | |
3d3c5039 | 4206 | case M_LH_AB: |
670a50eb ILT |
4207 | s = "lh"; |
4208 | goto ld; | |
3d3c5039 | 4209 | case M_LHU_AB: |
670a50eb ILT |
4210 | s = "lhu"; |
4211 | goto ld; | |
3d3c5039 | 4212 | case M_LW_AB: |
670a50eb ILT |
4213 | s = "lw"; |
4214 | goto ld; | |
3d3c5039 | 4215 | case M_LWC0_AB: |
670a50eb | 4216 | s = "lwc0"; |
8358c818 | 4217 | coproc = 1; |
670a50eb | 4218 | goto ld; |
3d3c5039 | 4219 | case M_LWC1_AB: |
670a50eb | 4220 | s = "lwc1"; |
8358c818 | 4221 | coproc = 1; |
670a50eb | 4222 | goto ld; |
3d3c5039 | 4223 | case M_LWC2_AB: |
670a50eb | 4224 | s = "lwc2"; |
8358c818 | 4225 | coproc = 1; |
670a50eb | 4226 | goto ld; |
3d3c5039 | 4227 | case M_LWC3_AB: |
670a50eb | 4228 | s = "lwc3"; |
8358c818 | 4229 | coproc = 1; |
670a50eb | 4230 | goto ld; |
3d3c5039 | 4231 | case M_LWL_AB: |
670a50eb | 4232 | s = "lwl"; |
b2b8c24e | 4233 | lr = 1; |
670a50eb | 4234 | goto ld; |
3d3c5039 | 4235 | case M_LWR_AB: |
670a50eb | 4236 | s = "lwr"; |
b2b8c24e | 4237 | lr = 1; |
8358c818 ILT |
4238 | goto ld; |
4239 | case M_LDC1_AB: | |
4240 | s = "ldc1"; | |
4241 | coproc = 1; | |
4242 | goto ld; | |
4243 | case M_LDC2_AB: | |
4244 | s = "ldc2"; | |
4245 | coproc = 1; | |
4246 | goto ld; | |
4247 | case M_LDC3_AB: | |
4248 | s = "ldc3"; | |
4249 | coproc = 1; | |
4250 | goto ld; | |
4251 | case M_LDL_AB: | |
4252 | s = "ldl"; | |
b2b8c24e | 4253 | lr = 1; |
8358c818 ILT |
4254 | goto ld; |
4255 | case M_LDR_AB: | |
4256 | s = "ldr"; | |
b2b8c24e | 4257 | lr = 1; |
8358c818 ILT |
4258 | goto ld; |
4259 | case M_LL_AB: | |
4260 | s = "ll"; | |
4261 | goto ld; | |
4262 | case M_LLD_AB: | |
4263 | s = "lld"; | |
4264 | goto ld; | |
4265 | case M_LWU_AB: | |
4266 | s = "lwu"; | |
3d3c5039 | 4267 | ld: |
b2b8c24e | 4268 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4269 | { |
4270 | tempreg = AT; | |
4271 | used_at = 1; | |
4272 | } | |
4273 | else | |
4274 | { | |
4275 | tempreg = treg; | |
4276 | used_at = 0; | |
4277 | } | |
4278 | goto ld_st; | |
3d3c5039 | 4279 | case M_SB_AB: |
670a50eb ILT |
4280 | s = "sb"; |
4281 | goto st; | |
3d3c5039 | 4282 | case M_SH_AB: |
670a50eb ILT |
4283 | s = "sh"; |
4284 | goto st; | |
3d3c5039 | 4285 | case M_SW_AB: |
670a50eb ILT |
4286 | s = "sw"; |
4287 | goto st; | |
3d3c5039 | 4288 | case M_SWC0_AB: |
670a50eb | 4289 | s = "swc0"; |
8358c818 | 4290 | coproc = 1; |
670a50eb | 4291 | goto st; |
3d3c5039 | 4292 | case M_SWC1_AB: |
670a50eb | 4293 | s = "swc1"; |
8358c818 | 4294 | coproc = 1; |
670a50eb | 4295 | goto st; |
3d3c5039 | 4296 | case M_SWC2_AB: |
670a50eb | 4297 | s = "swc2"; |
8358c818 | 4298 | coproc = 1; |
670a50eb | 4299 | goto st; |
3d3c5039 | 4300 | case M_SWC3_AB: |
670a50eb | 4301 | s = "swc3"; |
8358c818 | 4302 | coproc = 1; |
670a50eb | 4303 | goto st; |
3d3c5039 | 4304 | case M_SWL_AB: |
670a50eb ILT |
4305 | s = "swl"; |
4306 | goto st; | |
3d3c5039 | 4307 | case M_SWR_AB: |
670a50eb | 4308 | s = "swr"; |
8358c818 ILT |
4309 | goto st; |
4310 | case M_SC_AB: | |
4311 | s = "sc"; | |
4312 | goto st; | |
4313 | case M_SCD_AB: | |
4314 | s = "scd"; | |
4315 | goto st; | |
4316 | case M_SDC1_AB: | |
4317 | s = "sdc1"; | |
4318 | coproc = 1; | |
4319 | goto st; | |
4320 | case M_SDC2_AB: | |
4321 | s = "sdc2"; | |
4322 | coproc = 1; | |
4323 | goto st; | |
4324 | case M_SDC3_AB: | |
4325 | s = "sdc3"; | |
4326 | coproc = 1; | |
4327 | goto st; | |
4328 | case M_SDL_AB: | |
4329 | s = "sdl"; | |
4330 | goto st; | |
4331 | case M_SDR_AB: | |
4332 | s = "sdr"; | |
3d3c5039 | 4333 | st: |
670a50eb ILT |
4334 | tempreg = AT; |
4335 | used_at = 1; | |
3d3c5039 | 4336 | ld_st: |
8358c818 ILT |
4337 | if (mask == M_LWC1_AB |
4338 | || mask == M_SWC1_AB | |
8358c818 | 4339 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4340 | || mask == M_SDC1_AB |
4341 | || mask == M_L_DAB | |
4342 | || mask == M_S_DAB) | |
670a50eb | 4343 | fmt = "T,o(b)"; |
8358c818 | 4344 | else if (coproc) |
19ed8960 | 4345 | fmt = "E,o(b)"; |
670a50eb ILT |
4346 | else |
4347 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4348 | |
4349 | if (offset_expr.X_op != O_constant | |
4350 | && offset_expr.X_op != O_symbol) | |
4351 | { | |
4352 | as_bad ("expression too complex"); | |
4353 | offset_expr.X_op = O_constant; | |
4354 | } | |
4355 | ||
4356 | /* A constant expression in PIC code can be handled just as it | |
4357 | is in non PIC code. */ | |
d9aba805 | 4358 | if (mips_pic == NO_PIC |
0dd2d296 | 4359 | || offset_expr.X_op == O_constant) |
670a50eb | 4360 | { |
0dd2d296 ILT |
4361 | /* If this is a reference to a GP relative symbol, and there |
4362 | is no base register, we want | |
4363 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4364 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4365 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4366 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4367 | If we have a constant, we need two instructions anyhow, | |
4368 | so we always use the latter form. | |
4369 | ||
4370 | If we have a base register, and this is a reference to a | |
4371 | GP relative symbol, we want | |
4372 | addu $tempreg,$breg,$gp | |
4373 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4374 | Otherwise we want | |
4375 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4376 | addu $tempreg,$tempreg,$breg | |
4377 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4378 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4379 | if (breg == 0) |
4380 | { | |
7a15a226 | 4381 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4382 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4383 | p = NULL; |
4384 | else | |
4385 | { | |
8ea7f4e8 | 4386 | frag_grow (20); |
0dd2d296 ILT |
4387 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4388 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4389 | p = frag_var (rs_machine_dependent, 8, 0, | |
4390 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
4391 | (mips_warn_about_macros |
4392 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
4393 | offset_expr.X_add_symbol, (long) 0, |
4394 | (char *) NULL); | |
8197b589 | 4395 | used_at = 0; |
0dd2d296 ILT |
4396 | } |
4397 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4398 | if (p != NULL) | |
4399 | p += 4; | |
4400 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4401 | (int) BFD_RELOC_LO16, tempreg); | |
4402 | } | |
4403 | else | |
4404 | { | |
7a15a226 | 4405 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4406 | || nopic_need_relax (offset_expr.X_add_symbol)) |
0dd2d296 ILT |
4407 | p = NULL; |
4408 | else | |
4409 | { | |
8ea7f4e8 | 4410 | frag_grow (28); |
0dd2d296 ILT |
4411 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4412 | mips_isa < 3 ? "addu" : "daddu", | |
4413 | "d,v,t", tempreg, breg, GP); | |
4414 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4415 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4416 | p = frag_var (rs_machine_dependent, 12, 0, | |
4417 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
4418 | offset_expr.X_add_symbol, (long) 0, | |
4419 | (char *) NULL); | |
4420 | } | |
4421 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4422 | if (p != NULL) | |
4423 | p += 4; | |
4424 | macro_build (p, &icnt, (expressionS *) NULL, | |
4425 | mips_isa < 3 ? "addu" : "daddu", | |
4426 | "d,v,t", tempreg, tempreg, breg); | |
4427 | if (p != NULL) | |
4428 | p += 4; | |
4429 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4430 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4431 | } |
670a50eb | 4432 | } |
fb251650 | 4433 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4434 | { |
0dd2d296 ILT |
4435 | /* If this is a reference to an external symbol, we want |
4436 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4437 | nop | |
4438 | <op> $treg,0($tempreg) | |
4439 | Otherwise we want | |
4440 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4441 | nop | |
4442 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4443 | <op> $treg,0($tempreg) | |
4444 | If there is a base register, we add it to $tempreg before | |
4445 | the <op>. If there is a constant, we stick it in the | |
4446 | <op> instruction. We don't handle constants larger than | |
4447 | 16 bits, because we have no way to load the upper 16 bits | |
4448 | (actually, we could handle them for the subset of cases | |
4449 | in which we are not using $at). */ | |
4450 | assert (offset_expr.X_op == O_symbol); | |
4451 | expr1.X_add_number = offset_expr.X_add_number; | |
4452 | offset_expr.X_add_number = 0; | |
4453 | if (expr1.X_add_number < -0x8000 | |
4454 | || expr1.X_add_number >= 0x8000) | |
4455 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4456 | frag_grow (20); |
0dd2d296 ILT |
4457 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4458 | mips_isa < 3 ? "lw" : "ld", | |
4459 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4460 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4461 | p = frag_var (rs_machine_dependent, 4, 0, | |
4462 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4463 | offset_expr.X_add_symbol, (long) 0, | |
4464 | (char *) NULL); | |
4465 | macro_build (p, &icnt, &offset_expr, | |
4466 | mips_isa < 3 ? "addiu" : "daddiu", | |
4467 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 4468 | if (breg != 0) |
0dd2d296 | 4469 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
4470 | mips_isa < 3 ? "addu" : "daddu", |
4471 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
4472 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4473 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4474 | } |
fb251650 ILT |
4475 | else if (mips_pic == SVR4_PIC) |
4476 | { | |
4477 | int gpdel; | |
4478 | ||
4479 | /* If this is a reference to an external symbol, we want | |
4480 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4481 | addu $tempreg,$tempreg,$gp | |
4482 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4483 | <op> $treg,0($tempreg) | |
4484 | Otherwise we want | |
4485 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4486 | nop | |
4487 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4488 | <op> $treg,0($tempreg) | |
4489 | If there is a base register, we add it to $tempreg before | |
4490 | the <op>. If there is a constant, we stick it in the | |
4491 | <op> instruction. We don't handle constants larger than | |
4492 | 16 bits, because we have no way to load the upper 16 bits | |
4493 | (actually, we could handle them for the subset of cases | |
4494 | in which we are not using $at). */ | |
4495 | assert (offset_expr.X_op == O_symbol); | |
4496 | expr1.X_add_number = offset_expr.X_add_number; | |
4497 | offset_expr.X_add_number = 0; | |
4498 | if (expr1.X_add_number < -0x8000 | |
4499 | || expr1.X_add_number >= 0x8000) | |
4500 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4501 | if (reg_needs_delay (GP)) | |
4502 | gpdel = 4; | |
4503 | else | |
4504 | gpdel = 0; | |
4505 | frag_grow (36); | |
4506 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4507 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4508 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4509 | mips_isa < 3 ? "addu" : "daddu", | |
4510 | "d,v,t", tempreg, tempreg, GP); | |
4511 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4512 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 ILT |
4513 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4514 | tempreg); | |
fb251650 ILT |
4515 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4516 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
4517 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
4518 | if (gpdel > 0) | |
4519 | { | |
4520 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4521 | p += 4; | |
4522 | } | |
4523 | macro_build (p, &icnt, &offset_expr, | |
4524 | mips_isa < 3 ? "lw" : "ld", | |
867a58b3 | 4525 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4526 | p += 4; |
4527 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4528 | p += 4; | |
4529 | macro_build (p, &icnt, &offset_expr, | |
4530 | mips_isa < 3 ? "addiu" : "daddiu", | |
4531 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4532 | if (breg != 0) | |
4533 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4534 | mips_isa < 3 ? "addu" : "daddu", | |
4535 | "d,v,t", tempreg, tempreg, breg); | |
4536 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4537 | (int) BFD_RELOC_LO16, tempreg); | |
4538 | } | |
d9aba805 ILT |
4539 | else if (mips_pic == EMBEDDED_PIC) |
4540 | { | |
4541 | /* If there is no base register, we want | |
4542 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4543 | If there is a base register, we want | |
4544 | addu $tempreg,$breg,$gp | |
4545 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4546 | */ | |
4547 | assert (offset_expr.X_op == O_symbol); | |
4548 | if (breg == 0) | |
4549 | { | |
4550 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4551 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4552 | used_at = 0; | |
4553 | } | |
4554 | else | |
4555 | { | |
4556 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4557 | mips_isa < 3 ? "addu" : "daddu", | |
4558 | "d,v,t", tempreg, breg, GP); | |
4559 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4560 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4561 | } | |
4562 | } | |
4563 | else | |
4564 | abort (); | |
0dd2d296 ILT |
4565 | |
4566 | if (! used_at) | |
4567 | return; | |
4568 | ||
4569 | break; | |
3d3c5039 ILT |
4570 | |
4571 | case M_LI: | |
19ed8960 | 4572 | case M_LI_S: |
d8a1c247 KR |
4573 | load_register (&icnt, treg, &imm_expr, 0); |
4574 | return; | |
4575 | ||
4576 | case M_DLI: | |
4577 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4578 | return; |
3d3c5039 | 4579 | |
0dd2d296 | 4580 | case M_LI_SS: |
55933a58 | 4581 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4582 | { |
d8a1c247 | 4583 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4584 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4585 | "mtc1", "t,G", AT, treg); | |
4586 | break; | |
0dd2d296 | 4587 | } |
d9aba805 | 4588 | else |
d2c71068 | 4589 | { |
55933a58 ILT |
4590 | assert (offset_expr.X_op == O_symbol |
4591 | && strcmp (segment_name (S_GET_SEGMENT | |
4592 | (offset_expr.X_add_symbol)), | |
4593 | ".lit4") == 0 | |
4594 | && offset_expr.X_add_number == 0); | |
4595 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4596 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4597 | return; |
4598 | } | |
0dd2d296 | 4599 | |
3d3c5039 | 4600 | case M_LI_D: |
d9aba805 ILT |
4601 | /* We know that sym is in the .rdata section. First we get the |
4602 | upper 16 bits of the address. */ | |
4603 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
4604 | { |
4605 | /* FIXME: This won't work for a 64 bit address. */ | |
4606 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4607 | } | |
d9aba805 | 4608 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
4609 | { |
4610 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4611 | mips_isa < 3 ? "lw" : "ld", | |
4612 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4613 | } | |
d9aba805 ILT |
4614 | else if (mips_pic == EMBEDDED_PIC) |
4615 | { | |
4616 | /* For embedded PIC we pick up the entire address off $gp in | |
4617 | a single instruction. */ | |
4618 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4619 | mips_isa < 3 ? "addiu" : "daddiu", | |
4620 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4621 | offset_expr.X_op = O_constant; | |
4622 | offset_expr.X_add_number = 0; | |
4623 | } | |
4624 | else | |
4625 | abort (); | |
4626 | ||
0dd2d296 | 4627 | /* Now we load the register(s). */ |
8358c818 | 4628 | if (mips_isa >= 3) |
0dd2d296 ILT |
4629 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
4630 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
4631 | else |
4632 | { | |
0dd2d296 ILT |
4633 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
4634 | treg, (int) BFD_RELOC_LO16, AT); | |
4635 | if (treg != 31) | |
4636 | { | |
4637 | /* FIXME: How in the world do we deal with the possible | |
4638 | overflow here? */ | |
4639 | offset_expr.X_add_number += 4; | |
4640 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
4641 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
4642 | } | |
8358c818 | 4643 | } |
d2c71068 ILT |
4644 | |
4645 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4646 | does not become a variant frag. */ | |
4647 | frag_wane (frag_now); | |
4648 | frag_new (0); | |
4649 | ||
670a50eb | 4650 | break; |
3d3c5039 ILT |
4651 | |
4652 | case M_LI_DD: | |
55933a58 ILT |
4653 | assert (offset_expr.X_op == O_symbol |
4654 | && offset_expr.X_add_number == 0); | |
4655 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
4656 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 4657 | { |
0dd2d296 ILT |
4658 | if (mips_isa >= 2) |
4659 | { | |
4660 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
4661 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
4662 | return; | |
4663 | } | |
4664 | breg = GP; | |
4665 | r = BFD_RELOC_MIPS_LITERAL; | |
4666 | goto dob; | |
4667 | } | |
55933a58 | 4668 | else |
0dd2d296 | 4669 | { |
55933a58 ILT |
4670 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
4671 | if (mips_pic == SVR4_PIC) | |
4672 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4673 | mips_isa < 3 ? "lw" : "ld", | |
4674 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4675 | else | |
4676 | { | |
4677 | /* FIXME: This won't work for a 64 bit address. */ | |
4678 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
4679 | } | |
4680 | ||
0dd2d296 ILT |
4681 | if (mips_isa >= 2) |
4682 | { | |
4683 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 4684 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
4685 | |
4686 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
4687 | that this does not become a variant frag. */ | |
4688 | frag_wane (frag_now); | |
4689 | frag_new (0); | |
4690 | ||
0dd2d296 ILT |
4691 | break; |
4692 | } | |
4693 | breg = AT; | |
4694 | r = BFD_RELOC_LO16; | |
4695 | goto dob; | |
8358c818 | 4696 | } |
9226253a | 4697 | |
3d3c5039 | 4698 | case M_L_DOB: |
9a7d824a ILT |
4699 | /* Even on a big endian machine $fn comes before $fn+1. We have |
4700 | to adjust when loading from memory. */ | |
9226253a ILT |
4701 | r = BFD_RELOC_LO16; |
4702 | dob: | |
8358c818 | 4703 | assert (mips_isa < 2); |
0dd2d296 | 4704 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 4705 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 4706 | (int) r, breg); |
0dd2d296 ILT |
4707 | /* FIXME: A possible overflow which I don't know how to deal |
4708 | with. */ | |
670a50eb | 4709 | offset_expr.X_add_number += 4; |
0dd2d296 | 4710 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 4711 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 4712 | (int) r, breg); |
d2c71068 ILT |
4713 | |
4714 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
4715 | does not become a variant frag. */ | |
4716 | frag_wane (frag_now); | |
4717 | frag_new (0); | |
4718 | ||
0dd2d296 ILT |
4719 | if (breg != AT) |
4720 | return; | |
4721 | break; | |
3d3c5039 ILT |
4722 | |
4723 | case M_L_DAB: | |
670a50eb ILT |
4724 | /* |
4725 | * The MIPS assembler seems to check for X_add_number not | |
4726 | * being double aligned and generating: | |
4727 | * lui at,%hi(foo+1) | |
4728 | * addu at,at,v1 | |
4729 | * addiu at,at,%lo(foo+1) | |
4730 | * lwc1 f2,0(at) | |
4731 | * lwc1 f3,4(at) | |
4732 | * But, the resulting address is the same after relocation so why | |
4733 | * generate the extra instruction? | |
4734 | */ | |
4032d3f0 | 4735 | coproc = 1; |
0dd2d296 | 4736 | if (mips_isa >= 2) |
670a50eb | 4737 | { |
0dd2d296 ILT |
4738 | s = "ldc1"; |
4739 | goto ld; | |
670a50eb | 4740 | } |
0dd2d296 ILT |
4741 | |
4742 | s = "lwc1"; | |
4743 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
4744 | goto ldd_std; |
4745 | ||
4746 | case M_S_DAB: | |
8358c818 | 4747 | if (mips_isa >= 2) |
8358c818 | 4748 | { |
0dd2d296 ILT |
4749 | s = "sdc1"; |
4750 | goto st; | |
8358c818 | 4751 | } |
3d3c5039 | 4752 | |
0dd2d296 ILT |
4753 | s = "swc1"; |
4754 | fmt = "T,o(b)"; | |
4755 | coproc = 1; | |
4756 | goto ldd_std; | |
3d3c5039 ILT |
4757 | |
4758 | case M_LD_AB: | |
0dd2d296 | 4759 | if (mips_isa >= 3) |
670a50eb | 4760 | { |
0dd2d296 ILT |
4761 | s = "ld"; |
4762 | goto ld; | |
670a50eb | 4763 | } |
0dd2d296 ILT |
4764 | |
4765 | s = "lw"; | |
4766 | fmt = "t,o(b)"; | |
4767 | goto ldd_std; | |
4768 | ||
4769 | case M_SD_AB: | |
4770 | if (mips_isa >= 3) | |
670a50eb | 4771 | { |
0dd2d296 ILT |
4772 | s = "sd"; |
4773 | goto st; | |
670a50eb | 4774 | } |
0dd2d296 | 4775 | |
670a50eb | 4776 | s = "sw"; |
0dd2d296 ILT |
4777 | fmt = "t,o(b)"; |
4778 | ||
4779 | ldd_std: | |
4780 | if (offset_expr.X_op != O_symbol | |
4781 | && offset_expr.X_op != O_constant) | |
670a50eb | 4782 | { |
0dd2d296 ILT |
4783 | as_bad ("expression too complex"); |
4784 | offset_expr.X_op = O_constant; | |
4785 | } | |
4786 | ||
4787 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
4788 | to adjust when loading from memory. We set coproc if we must | |
4789 | load $fn+1 first. */ | |
4790 | if (byte_order == LITTLE_ENDIAN) | |
4791 | coproc = 0; | |
4792 | ||
d9aba805 | 4793 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
4794 | || offset_expr.X_op == O_constant) |
4795 | { | |
4796 | /* If this is a reference to a GP relative symbol, we want | |
4797 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4798 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
4799 | If we have a base register, we use this | |
4800 | addu $at,$breg,$gp | |
4801 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
4802 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
4803 | If this is not a GP relative symbol, we want | |
4804 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4805 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4806 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4807 | If there is a base register, we add it to $at after the | |
4808 | lui instruction. If there is a constant, we always use | |
4809 | the last case. */ | |
7a15a226 | 4810 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
d8a1c247 | 4811 | || nopic_need_relax (offset_expr.X_add_symbol)) |
670a50eb | 4812 | { |
0dd2d296 ILT |
4813 | p = NULL; |
4814 | used_at = 1; | |
670a50eb ILT |
4815 | } |
4816 | else | |
0dd2d296 ILT |
4817 | { |
4818 | int off; | |
4819 | ||
4820 | if (breg == 0) | |
4821 | { | |
8ea7f4e8 | 4822 | frag_grow (28); |
0dd2d296 ILT |
4823 | tempreg = GP; |
4824 | off = 0; | |
4825 | used_at = 0; | |
4826 | } | |
4827 | else | |
4828 | { | |
8ea7f4e8 | 4829 | frag_grow (36); |
0dd2d296 ILT |
4830 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4831 | mips_isa < 3 ? "addu" : "daddu", | |
4832 | "d,v,t", AT, breg, GP); | |
4833 | tempreg = AT; | |
4834 | off = 4; | |
4835 | used_at = 1; | |
4836 | } | |
4837 | ||
4838 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4839 | coproc ? treg + 1 : treg, | |
4840 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4841 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
4842 | |
4843 | /* Set mips_optimize to 2 to avoid inserting an | |
4844 | undesired nop. */ | |
4845 | hold_mips_optimize = mips_optimize; | |
4846 | mips_optimize = 2; | |
0dd2d296 ILT |
4847 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4848 | coproc ? treg : treg + 1, | |
4849 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
4850 | mips_optimize = hold_mips_optimize; |
4851 | ||
0dd2d296 ILT |
4852 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
4853 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 4854 | used_at && mips_noat), |
0dd2d296 ILT |
4855 | offset_expr.X_add_symbol, (long) 0, |
4856 | (char *) NULL); | |
777ad64d ILT |
4857 | |
4858 | /* We just generated two relocs. When tc_gen_reloc | |
4859 | handles this case, it will skip the first reloc and | |
4860 | handle the second. The second reloc already has an | |
4861 | extra addend of 4, which we added above. We must | |
4862 | subtract it out, and then subtract another 4 to make | |
4863 | the first reloc come out right. The second reloc | |
4864 | will come out right because we are going to add 4 to | |
4865 | offset_expr when we build its instruction below. */ | |
4866 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
4867 | offset_expr.X_op = O_constant; |
4868 | } | |
4869 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
4870 | if (p != NULL) | |
4871 | p += 4; | |
4872 | if (breg != 0) | |
4873 | { | |
4874 | macro_build (p, &icnt, (expressionS *) NULL, | |
4875 | mips_isa < 3 ? "addu" : "daddu", | |
4876 | "d,v,t", AT, breg, AT); | |
4877 | if (p != NULL) | |
4878 | p += 4; | |
4879 | } | |
4880 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4881 | coproc ? treg + 1 : treg, | |
4882 | (int) BFD_RELOC_LO16, AT); | |
4883 | if (p != NULL) | |
4884 | p += 4; | |
4885 | /* FIXME: How do we handle overflow here? */ | |
4886 | offset_expr.X_add_number += 4; | |
4887 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
4888 | coproc ? treg : treg + 1, | |
4889 | (int) BFD_RELOC_LO16, AT); | |
4890 | } | |
fb251650 | 4891 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4892 | { |
0dd2d296 ILT |
4893 | int off; |
4894 | ||
4895 | /* If this is a reference to an external symbol, we want | |
4896 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4897 | nop | |
4898 | <op> $treg,0($at) | |
4899 | <op> $treg+1,4($at) | |
4900 | Otherwise we want | |
4901 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4902 | nop | |
4903 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4904 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4905 | If there is a base register we add it to $at before the | |
4906 | lwc1 instructions. If there is a constant we include it | |
4907 | in the lwc1 instructions. */ | |
4908 | used_at = 1; | |
4909 | expr1.X_add_number = offset_expr.X_add_number; | |
4910 | offset_expr.X_add_number = 0; | |
4911 | if (expr1.X_add_number < -0x8000 | |
4912 | || expr1.X_add_number >= 0x8000 - 4) | |
4913 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4914 | if (breg == 0) | |
4915 | off = 0; | |
4916 | else | |
4917 | off = 4; | |
8ea7f4e8 | 4918 | frag_grow (24 + off); |
0dd2d296 ILT |
4919 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4920 | mips_isa < 3 ? "lw" : "ld", | |
4921 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4922 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 4923 | if (breg != 0) |
0dd2d296 | 4924 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 4925 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4926 | "d,v,t", AT, breg, AT); |
4927 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4928 | coproc ? treg + 1 : treg, | |
4929 | (int) BFD_RELOC_LO16, AT); | |
4930 | expr1.X_add_number += 4; | |
55933a58 ILT |
4931 | |
4932 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4933 | nop. */ | |
4934 | hold_mips_optimize = mips_optimize; | |
4935 | mips_optimize = 2; | |
0dd2d296 ILT |
4936 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
4937 | coproc ? treg : treg + 1, | |
4938 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
4939 | mips_optimize = hold_mips_optimize; |
4940 | ||
0dd2d296 ILT |
4941 | (void) frag_var (rs_machine_dependent, 0, 0, |
4942 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
4943 | offset_expr.X_add_symbol, (long) 0, | |
4944 | (char *) NULL); | |
8358c818 | 4945 | } |
fb251650 ILT |
4946 | else if (mips_pic == SVR4_PIC) |
4947 | { | |
4948 | int gpdel, off; | |
4949 | ||
4950 | /* If this is a reference to an external symbol, we want | |
4951 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4952 | addu $at,$at,$gp | |
4953 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
4954 | nop | |
4955 | <op> $treg,0($at) | |
4956 | <op> $treg+1,4($at) | |
4957 | Otherwise we want | |
4958 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4959 | nop | |
4960 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
4961 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
4962 | If there is a base register we add it to $at before the | |
4963 | lwc1 instructions. If there is a constant we include it | |
4964 | in the lwc1 instructions. */ | |
4965 | used_at = 1; | |
4966 | expr1.X_add_number = offset_expr.X_add_number; | |
4967 | offset_expr.X_add_number = 0; | |
4968 | if (expr1.X_add_number < -0x8000 | |
4969 | || expr1.X_add_number >= 0x8000 - 4) | |
4970 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4971 | if (reg_needs_delay (GP)) | |
4972 | gpdel = 4; | |
4973 | else | |
4974 | gpdel = 0; | |
4975 | if (breg == 0) | |
4976 | off = 0; | |
4977 | else | |
4978 | off = 4; | |
4979 | frag_grow (56); | |
4980 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4981 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4982 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4983 | mips_isa < 3 ? "addu" : "daddu", | |
4984 | "d,v,t", AT, AT, GP); | |
4985 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4986 | mips_isa < 3 ? "lw" : "ld", | |
4987 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
4988 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4989 | if (breg != 0) | |
4990 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4991 | mips_isa < 3 ? "addu" : "daddu", | |
4992 | "d,v,t", AT, breg, AT); | |
4993 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
4994 | coproc ? treg + 1 : treg, | |
4995 | (int) BFD_RELOC_LO16, AT); | |
4996 | expr1.X_add_number += 4; | |
4997 | ||
4998 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
4999 | nop. */ | |
5000 | hold_mips_optimize = mips_optimize; | |
5001 | mips_optimize = 2; | |
5002 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5003 | coproc ? treg : treg + 1, | |
5004 | (int) BFD_RELOC_LO16, AT); | |
5005 | mips_optimize = hold_mips_optimize; | |
5006 | expr1.X_add_number -= 4; | |
5007 | ||
5008 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5009 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5010 | 8 + gpdel + off, 1, 0), | |
5011 | offset_expr.X_add_symbol, (long) 0, | |
5012 | (char *) NULL); | |
5013 | if (gpdel > 0) | |
5014 | { | |
5015 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5016 | p += 4; | |
5017 | } | |
5018 | macro_build (p, &icnt, &offset_expr, | |
5019 | mips_isa < 3 ? "lw" : "ld", | |
5020 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5021 | p += 4; | |
5022 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5023 | p += 4; | |
5024 | if (breg != 0) | |
5025 | { | |
5026 | macro_build (p, &icnt, (expressionS *) NULL, | |
5027 | mips_isa < 3 ? "addu" : "daddu", | |
5028 | "d,v,t", AT, breg, AT); | |
5029 | p += 4; | |
5030 | } | |
5031 | macro_build (p, &icnt, &expr1, s, fmt, | |
5032 | coproc ? treg + 1 : treg, | |
5033 | (int) BFD_RELOC_LO16, AT); | |
5034 | p += 4; | |
5035 | expr1.X_add_number += 4; | |
5036 | ||
5037 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5038 | nop. */ | |
5039 | hold_mips_optimize = mips_optimize; | |
5040 | mips_optimize = 2; | |
5041 | macro_build (p, &icnt, &expr1, s, fmt, | |
5042 | coproc ? treg : treg + 1, | |
5043 | (int) BFD_RELOC_LO16, AT); | |
5044 | mips_optimize = hold_mips_optimize; | |
5045 | } | |
d9aba805 ILT |
5046 | else if (mips_pic == EMBEDDED_PIC) |
5047 | { | |
5048 | /* If there is no base register, we use | |
5049 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5050 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5051 | If we have a base register, we use | |
5052 | addu $at,$breg,$gp | |
5053 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5054 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5055 | */ | |
5056 | if (breg == 0) | |
5057 | { | |
5058 | tempreg = GP; | |
5059 | used_at = 0; | |
5060 | } | |
5061 | else | |
5062 | { | |
5063 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5064 | mips_isa < 3 ? "addu" : "daddu", | |
5065 | "d,v,t", AT, breg, GP); | |
5066 | tempreg = AT; | |
5067 | used_at = 1; | |
5068 | } | |
5069 | ||
5070 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5071 | coproc ? treg + 1 : treg, | |
5072 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5073 | offset_expr.X_add_number += 4; | |
5074 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5075 | coproc ? treg : treg + 1, | |
5076 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5077 | } | |
5078 | else | |
5079 | abort (); | |
0dd2d296 ILT |
5080 | |
5081 | if (! used_at) | |
5082 | return; | |
5083 | ||
5084 | break; | |
5085 | ||
5086 | case M_LD_OB: | |
5087 | s = "lw"; | |
5088 | goto sd_ob; | |
5089 | case M_SD_OB: | |
5090 | s = "sw"; | |
5091 | sd_ob: | |
5092 | assert (mips_isa < 3); | |
5093 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
5094 | (int) BFD_RELOC_LO16, breg); | |
5095 | offset_expr.X_add_number += 4; | |
5096 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5097 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5098 | return; |
917fae09 SS |
5099 | #ifdef LOSING_COMPILER |
5100 | default: | |
5101 | macro2 (ip); | |
5102 | return; | |
5103 | } | |
5104 | if (mips_noat) | |
5105 | as_warn ("Macro used $at after \".set noat\""); | |
5106 | } | |
5107 | ||
5108 | static void | |
5109 | macro2 (ip) | |
5110 | struct mips_cl_insn *ip; | |
5111 | { | |
5112 | register int treg, sreg, dreg, breg; | |
5113 | int tempreg; | |
5114 | int mask; | |
5115 | int icnt = 0; | |
5116 | int used_at; | |
5117 | expressionS expr1; | |
5118 | const char *s; | |
5119 | const char *s2; | |
5120 | const char *fmt; | |
5121 | int likely = 0; | |
5122 | int dbl = 0; | |
5123 | int coproc = 0; | |
adcf2b9d ILT |
5124 | int lr = 0; |
5125 | int off; | |
917fae09 SS |
5126 | offsetT maxnum; |
5127 | bfd_reloc_code_real_type r; | |
5128 | char *p; | |
5129 | ||
5130 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5131 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5132 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5133 | mask = ip->insn_mo->mask; | |
5134 | ||
5135 | expr1.X_op = O_constant; | |
5136 | expr1.X_op_symbol = NULL; | |
5137 | expr1.X_add_symbol = NULL; | |
5138 | expr1.X_add_number = 1; | |
5139 | ||
5140 | switch (mask) | |
5141 | { | |
5142 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5143 | |
8358c818 ILT |
5144 | case M_DMUL: |
5145 | dbl = 1; | |
3d3c5039 | 5146 | case M_MUL: |
0dd2d296 | 5147 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5148 | dbl ? "dmultu" : "multu", |
5149 | "s,t", sreg, treg); | |
0dd2d296 | 5150 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5151 | return; |
3d3c5039 | 5152 | |
8358c818 ILT |
5153 | case M_DMUL_I: |
5154 | dbl = 1; | |
3d3c5039 | 5155 | case M_MUL_I: |
8358c818 ILT |
5156 | /* The MIPS assembler some times generates shifts and adds. I'm |
5157 | not trying to be that fancy. GCC should do this for us | |
5158 | anyway. */ | |
d8a1c247 | 5159 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5160 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5161 | dbl ? "dmult" : "mult", |
5162 | "s,t", sreg, AT); | |
0dd2d296 | 5163 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5164 | break; |
3d3c5039 | 5165 | |
8358c818 ILT |
5166 | case M_DMULO: |
5167 | dbl = 1; | |
5168 | case M_MULO: | |
fbcfacb7 | 5169 | mips_emit_delays (true); |
8358c818 | 5170 | ++mips_noreorder; |
0dd2d296 ILT |
5171 | mips_any_noreorder = 1; |
5172 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5173 | dbl ? "dmult" : "mult", |
5174 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5175 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5176 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5177 | dbl ? "dsra32" : "sra", |
5178 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5179 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5180 | if (mips_trap) |
5181 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5182 | else | |
5183 | { | |
5184 | expr1.X_add_number = 8; | |
5185 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5186 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5187 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5188 | } | |
8358c818 | 5189 | --mips_noreorder; |
0dd2d296 | 5190 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5191 | break; |
5192 | ||
5193 | case M_DMULOU: | |
5194 | dbl = 1; | |
5195 | case M_MULOU: | |
fbcfacb7 | 5196 | mips_emit_delays (true); |
8358c818 | 5197 | ++mips_noreorder; |
0dd2d296 ILT |
5198 | mips_any_noreorder = 1; |
5199 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5200 | dbl ? "dmultu" : "multu", |
5201 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5202 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5203 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5204 | if (mips_trap) |
5205 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5206 | else | |
5207 | { | |
5208 | expr1.X_add_number = 8; | |
5209 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5210 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5211 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5212 | } | |
8358c818 ILT |
5213 | --mips_noreorder; |
5214 | break; | |
5215 | ||
3d3c5039 | 5216 | case M_ROL: |
0dd2d296 ILT |
5217 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5218 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5219 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5220 | treg); | |
5221 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5222 | break; |
3d3c5039 ILT |
5223 | |
5224 | case M_ROL_I: | |
0dd2d296 | 5225 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5226 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5227 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5228 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5229 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5230 | break; |
3d3c5039 ILT |
5231 | |
5232 | case M_ROR: | |
0dd2d296 ILT |
5233 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5234 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5235 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5236 | treg); | |
5237 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5238 | break; |
3d3c5039 ILT |
5239 | |
5240 | case M_ROR_I: | |
0dd2d296 | 5241 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5242 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5243 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5244 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5245 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5246 | break; |
3d3c5039 ILT |
5247 | |
5248 | case M_S_DOB: | |
8358c818 | 5249 | assert (mips_isa < 2); |
9a7d824a ILT |
5250 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5251 | to adjust when storing to memory. */ | |
0dd2d296 | 5252 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 5253 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 5254 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5255 | offset_expr.X_add_number += 4; |
0dd2d296 | 5256 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 5257 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 5258 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5259 | return; |
3d3c5039 | 5260 | |
3d3c5039 | 5261 | case M_SEQ: |
670a50eb | 5262 | if (sreg == 0) |
0dd2d296 ILT |
5263 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5264 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5265 | else if (treg == 0) |
0dd2d296 ILT |
5266 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5267 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5268 | else |
5269 | { | |
0dd2d296 ILT |
5270 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5271 | sreg, treg); | |
5272 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5273 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5274 | } |
670a50eb | 5275 | return; |
3d3c5039 ILT |
5276 | |
5277 | case M_SEQ_I: | |
670a50eb ILT |
5278 | if (imm_expr.X_add_number == 0) |
5279 | { | |
0dd2d296 ILT |
5280 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5281 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5282 | return; |
3d3c5039 | 5283 | } |
670a50eb ILT |
5284 | if (sreg == 0) |
5285 | { | |
9a7d824a | 5286 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5287 | ip->insn_mo->name); |
0dd2d296 | 5288 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5289 | return; |
3d3c5039 | 5290 | } |
6e8dda9c | 5291 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5292 | { |
0dd2d296 ILT |
5293 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5294 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5295 | used_at = 0; |
6e8dda9c ILT |
5296 | } |
5297 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5298 | { | |
5299 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5300 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5301 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5302 | "t,r,j", dreg, sreg, |
5303 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5304 | used_at = 0; |
5305 | } | |
5306 | else | |
5307 | { | |
d8a1c247 | 5308 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5309 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5310 | sreg, AT); | |
670a50eb ILT |
5311 | used_at = 1; |
5312 | } | |
0dd2d296 | 5313 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5314 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5315 | if (used_at) |
5316 | break; | |
5317 | return; | |
3d3c5039 ILT |
5318 | |
5319 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5320 | s = "slt"; |
5321 | goto sge; | |
3d3c5039 | 5322 | case M_SGEU: |
670a50eb | 5323 | s = "sltu"; |
3d3c5039 | 5324 | sge: |
0dd2d296 ILT |
5325 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5326 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5327 | (int) BFD_RELOC_LO16); |
670a50eb | 5328 | return; |
3d3c5039 | 5329 | |
670a50eb | 5330 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5331 | case M_SGEU_I: |
6e8dda9c | 5332 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5333 | { |
0dd2d296 | 5334 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5335 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5336 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5337 | used_at = 0; |
5338 | } | |
5339 | else | |
5340 | { | |
d8a1c247 | 5341 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5342 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5343 | mask == M_SGE_I ? "slt" : "sltu", |
5344 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5345 | used_at = 1; |
5346 | } | |
0dd2d296 | 5347 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5348 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5349 | if (used_at) |
5350 | break; | |
5351 | return; | |
3d3c5039 ILT |
5352 | |
5353 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5354 | s = "slt"; |
5355 | goto sgt; | |
3d3c5039 | 5356 | case M_SGTU: |
670a50eb | 5357 | s = "sltu"; |
3d3c5039 | 5358 | sgt: |
0dd2d296 | 5359 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5360 | return; |
3d3c5039 | 5361 | |
670a50eb ILT |
5362 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5363 | s = "slt"; | |
5364 | goto sgti; | |
3d3c5039 | 5365 | case M_SGTU_I: |
670a50eb | 5366 | s = "sltu"; |
3d3c5039 | 5367 | sgti: |
d8a1c247 | 5368 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5369 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5370 | break; |
3d3c5039 | 5371 | |
670a50eb ILT |
5372 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5373 | s = "slt"; | |
5374 | goto sle; | |
3d3c5039 | 5375 | case M_SLEU: |
670a50eb | 5376 | s = "sltu"; |
3d3c5039 | 5377 | sle: |
0dd2d296 ILT |
5378 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5379 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5380 | (int) BFD_RELOC_LO16); |
670a50eb | 5381 | return; |
3d3c5039 | 5382 | |
670a50eb ILT |
5383 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5384 | s = "slt"; | |
5385 | goto slei; | |
3d3c5039 | 5386 | case M_SLEU_I: |
670a50eb | 5387 | s = "sltu"; |
3d3c5039 | 5388 | slei: |
d8a1c247 | 5389 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5390 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5391 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5392 | (int) BFD_RELOC_LO16); |
670a50eb | 5393 | break; |
3d3c5039 ILT |
5394 | |
5395 | case M_SLT_I: | |
6e8dda9c | 5396 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5397 | { |
0dd2d296 ILT |
5398 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5399 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5400 | return; |
3d3c5039 | 5401 | } |
d8a1c247 | 5402 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5403 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5404 | break; |
3d3c5039 ILT |
5405 | |
5406 | case M_SLTU_I: | |
6e8dda9c | 5407 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 5408 | { |
0dd2d296 ILT |
5409 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5410 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5411 | return; |
3d3c5039 | 5412 | } |
d8a1c247 | 5413 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5414 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5415 | AT); | |
670a50eb | 5416 | break; |
3d3c5039 ILT |
5417 | |
5418 | case M_SNE: | |
670a50eb | 5419 | if (sreg == 0) |
0dd2d296 ILT |
5420 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5421 | treg); | |
670a50eb | 5422 | else if (treg == 0) |
0dd2d296 ILT |
5423 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5424 | sreg); | |
670a50eb ILT |
5425 | else |
5426 | { | |
0dd2d296 ILT |
5427 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5428 | sreg, treg); | |
5429 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5430 | dreg); | |
3d3c5039 | 5431 | } |
670a50eb | 5432 | return; |
3d3c5039 ILT |
5433 | |
5434 | case M_SNE_I: | |
670a50eb ILT |
5435 | if (imm_expr.X_add_number == 0) |
5436 | { | |
0dd2d296 ILT |
5437 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5438 | sreg); | |
670a50eb | 5439 | return; |
3d3c5039 | 5440 | } |
670a50eb ILT |
5441 | if (sreg == 0) |
5442 | { | |
9a7d824a | 5443 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5444 | ip->insn_mo->name); |
0dd2d296 | 5445 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5446 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5447 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5448 | return; |
3d3c5039 | 5449 | } |
6e8dda9c | 5450 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 5451 | { |
0dd2d296 ILT |
5452 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5453 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5454 | used_at = 0; |
6e8dda9c ILT |
5455 | } |
5456 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
5457 | { | |
5458 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5459 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 5460 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 5461 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5462 | used_at = 0; |
5463 | } | |
5464 | else | |
5465 | { | |
d8a1c247 | 5466 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5467 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5468 | sreg, AT); | |
670a50eb ILT |
5469 | used_at = 1; |
5470 | } | |
0dd2d296 | 5471 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5472 | if (used_at) |
5473 | break; | |
5474 | return; | |
3d3c5039 | 5475 | |
8358c818 ILT |
5476 | case M_DSUB_I: |
5477 | dbl = 1; | |
3d3c5039 | 5478 | case M_SUB_I: |
6e8dda9c | 5479 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5480 | { |
5481 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5482 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5483 | dbl ? "daddi" : "addi", |
9226253a | 5484 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5485 | return; |
3d3c5039 | 5486 | } |
d8a1c247 | 5487 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5488 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5489 | dbl ? "dsub" : "sub", |
5490 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 5491 | break; |
3d3c5039 | 5492 | |
8358c818 ILT |
5493 | case M_DSUBU_I: |
5494 | dbl = 1; | |
3d3c5039 | 5495 | case M_SUBU_I: |
6e8dda9c | 5496 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
5497 | { |
5498 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5499 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5500 | dbl ? "daddiu" : "addiu", |
9226253a | 5501 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 5502 | return; |
3d3c5039 | 5503 | } |
d8a1c247 | 5504 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5505 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5506 | dbl ? "dsubu" : "subu", |
5507 | "d,v,t", dreg, sreg, AT); | |
5508 | break; | |
5509 | ||
5510 | case M_TEQ_I: | |
5511 | s = "teq"; | |
5512 | goto trap; | |
5513 | case M_TGE_I: | |
5514 | s = "tge"; | |
5515 | goto trap; | |
5516 | case M_TGEU_I: | |
5517 | s = "tgeu"; | |
5518 | goto trap; | |
5519 | case M_TLT_I: | |
5520 | s = "tlt"; | |
5521 | goto trap; | |
5522 | case M_TLTU_I: | |
5523 | s = "tltu"; | |
5524 | goto trap; | |
5525 | case M_TNE_I: | |
5526 | s = "tne"; | |
5527 | trap: | |
d8a1c247 | 5528 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5529 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 5530 | break; |
3d3c5039 ILT |
5531 | |
5532 | case M_TRUNCWD: | |
5533 | case M_TRUNCWS: | |
8358c818 | 5534 | assert (mips_isa < 2); |
670a50eb ILT |
5535 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
5536 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
5537 | ||
5538 | /* | |
5539 | * Is the double cfc1 instruction a bug in the mips assembler; | |
5540 | * or is there a reason for it? | |
5541 | */ | |
fbcfacb7 | 5542 | mips_emit_delays (true); |
becfe05e | 5543 | ++mips_noreorder; |
0dd2d296 ILT |
5544 | mips_any_noreorder = 1; |
5545 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5546 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
5547 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 5548 | expr1.X_add_number = 3; |
0dd2d296 | 5549 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 5550 | (int) BFD_RELOC_LO16); |
670a50eb | 5551 | expr1.X_add_number = 2; |
0dd2d296 | 5552 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 5553 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
5554 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
5555 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
5556 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 5557 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
5558 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
5559 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 5560 | --mips_noreorder; |
670a50eb | 5561 | break; |
3d3c5039 ILT |
5562 | |
5563 | case M_ULH: | |
670a50eb ILT |
5564 | s = "lb"; |
5565 | goto ulh; | |
3d3c5039 | 5566 | case M_ULHU: |
670a50eb | 5567 | s = "lbu"; |
3d3c5039 | 5568 | ulh: |
8ea7f4e8 ILT |
5569 | if (offset_expr.X_add_number >= 0x7fff) |
5570 | as_bad ("operand overflow"); | |
670a50eb | 5571 | /* avoid load delay */ |
8ea7f4e8 ILT |
5572 | if (byte_order == LITTLE_ENDIAN) |
5573 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5574 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 5575 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
5576 | if (byte_order == LITTLE_ENDIAN) |
5577 | offset_expr.X_add_number -= 1; | |
5578 | else | |
5579 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5580 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 5581 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
5582 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
5583 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 5584 | break; |
3d3c5039 | 5585 | |
adcf2b9d ILT |
5586 | case M_ULD: |
5587 | s = "ldl"; | |
5588 | s2 = "ldr"; | |
5589 | off = 7; | |
5590 | goto ulw; | |
3d3c5039 | 5591 | case M_ULW: |
adcf2b9d ILT |
5592 | s = "lwl"; |
5593 | s2 = "lwr"; | |
5594 | off = 3; | |
5595 | ulw: | |
5596 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 ILT |
5597 | as_bad ("operand overflow"); |
5598 | if (byte_order == LITTLE_ENDIAN) | |
adcf2b9d ILT |
5599 | offset_expr.X_add_number += off; |
5600 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5601 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 | 5602 | if (byte_order == LITTLE_ENDIAN) |
adcf2b9d | 5603 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5604 | else |
adcf2b9d ILT |
5605 | offset_expr.X_add_number += off; |
5606 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5607 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5608 | return; |
3d3c5039 | 5609 | |
adcf2b9d ILT |
5610 | case M_ULD_A: |
5611 | s = "ldl"; | |
5612 | s2 = "ldr"; | |
5613 | off = 7; | |
5614 | goto ulwa; | |
5615 | case M_ULW_A: | |
5616 | s = "lwl"; | |
5617 | s2 = "lwr"; | |
5618 | off = 3; | |
5619 | ulwa: | |
5620 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5621 | if (breg != 0) |
5622 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5623 | mips_isa < 3 ? "addu" : "daddu", | |
5624 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5625 | if (byte_order == LITTLE_ENDIAN) |
5626 | expr1.X_add_number = off; | |
5627 | else | |
5628 | expr1.X_add_number = 0; | |
5629 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5630 | (int) BFD_RELOC_LO16, AT); | |
5631 | if (byte_order == LITTLE_ENDIAN) | |
5632 | expr1.X_add_number = 0; | |
5633 | else | |
5634 | expr1.X_add_number = off; | |
5635 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5636 | (int) BFD_RELOC_LO16, AT); | |
5637 | break; | |
5638 | ||
3d3c5039 ILT |
5639 | case M_ULH_A: |
5640 | case M_ULHU_A: | |
0dd2d296 | 5641 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5642 | if (breg != 0) |
5643 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5644 | mips_isa < 3 ? "addu" : "daddu", | |
5645 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5646 | if (byte_order == BIG_ENDIAN) |
5647 | expr1.X_add_number = 0; | |
5648 | macro_build ((char *) NULL, &icnt, &expr1, | |
5649 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
5650 | (int) BFD_RELOC_LO16, AT); | |
5651 | if (byte_order == BIG_ENDIAN) | |
5652 | expr1.X_add_number = 1; | |
670a50eb | 5653 | else |
adcf2b9d ILT |
5654 | expr1.X_add_number = 0; |
5655 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5656 | (int) BFD_RELOC_LO16, AT); | |
5657 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5658 | treg, 8); | |
5659 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5660 | treg, AT); | |
670a50eb | 5661 | break; |
3d3c5039 ILT |
5662 | |
5663 | case M_USH: | |
8ea7f4e8 ILT |
5664 | if (offset_expr.X_add_number >= 0x7fff) |
5665 | as_bad ("operand overflow"); | |
5666 | if (byte_order == BIG_ENDIAN) | |
5667 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5668 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 5669 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 5670 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
8ea7f4e8 ILT |
5671 | if (byte_order == BIG_ENDIAN) |
5672 | offset_expr.X_add_number -= 1; | |
5673 | else | |
5674 | offset_expr.X_add_number += 1; | |
0dd2d296 | 5675 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 5676 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5677 | break; |
3d3c5039 | 5678 | |
adcf2b9d ILT |
5679 | case M_USD: |
5680 | s = "sdl"; | |
5681 | s2 = "sdr"; | |
5682 | off = 7; | |
5683 | goto usw; | |
3d3c5039 | 5684 | case M_USW: |
adcf2b9d ILT |
5685 | s = "swl"; |
5686 | s2 = "swr"; | |
5687 | off = 3; | |
5688 | usw: | |
5689 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 ILT |
5690 | as_bad ("operand overflow"); |
5691 | if (byte_order == LITTLE_ENDIAN) | |
adcf2b9d ILT |
5692 | offset_expr.X_add_number += off; |
5693 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 5694 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 | 5695 | if (byte_order == LITTLE_ENDIAN) |
adcf2b9d | 5696 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 5697 | else |
adcf2b9d ILT |
5698 | offset_expr.X_add_number += off; |
5699 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 5700 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5701 | return; |
3d3c5039 | 5702 | |
adcf2b9d ILT |
5703 | case M_USD_A: |
5704 | s = "sdl"; | |
5705 | s2 = "sdr"; | |
5706 | off = 7; | |
5707 | goto uswa; | |
3d3c5039 | 5708 | case M_USW_A: |
adcf2b9d ILT |
5709 | s = "swl"; |
5710 | s2 = "swr"; | |
5711 | off = 3; | |
5712 | uswa: | |
0dd2d296 | 5713 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
5714 | if (breg != 0) |
5715 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5716 | mips_isa < 3 ? "addu" : "daddu", | |
5717 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5718 | if (byte_order == LITTLE_ENDIAN) |
5719 | expr1.X_add_number = off; | |
670a50eb | 5720 | else |
adcf2b9d ILT |
5721 | expr1.X_add_number = 0; |
5722 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
5723 | (int) BFD_RELOC_LO16, AT); | |
5724 | if (byte_order == LITTLE_ENDIAN) | |
5725 | expr1.X_add_number = 0; | |
5726 | else | |
5727 | expr1.X_add_number = off; | |
5728 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
5729 | (int) BFD_RELOC_LO16, AT); | |
5730 | break; | |
5731 | ||
5732 | case M_USH_A: | |
5733 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
5734 | if (breg != 0) |
5735 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5736 | mips_isa < 3 ? "addu" : "daddu", | |
5737 | "d,v,t", AT, AT, breg); | |
adcf2b9d ILT |
5738 | if (byte_order == LITTLE_ENDIAN) |
5739 | expr1.X_add_number = 0; | |
5740 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5741 | (int) BFD_RELOC_LO16, AT); | |
5742 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
5743 | treg, 8); | |
5744 | if (byte_order == LITTLE_ENDIAN) | |
5745 | expr1.X_add_number = 1; | |
5746 | else | |
5747 | expr1.X_add_number = 0; | |
5748 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
5749 | (int) BFD_RELOC_LO16, AT); | |
5750 | if (byte_order == LITTLE_ENDIAN) | |
5751 | expr1.X_add_number = 0; | |
5752 | else | |
5753 | expr1.X_add_number = 1; | |
5754 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
5755 | (int) BFD_RELOC_LO16, AT); | |
5756 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
5757 | treg, 8); | |
5758 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
5759 | treg, AT); | |
670a50eb | 5760 | break; |
3d3c5039 ILT |
5761 | |
5762 | default: | |
670a50eb | 5763 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 5764 | break; |
3d3c5039 | 5765 | } |
670a50eb ILT |
5766 | if (mips_noat) |
5767 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
5768 | } |
5769 | ||
cc5703cd | 5770 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 5771 | |
3d3c5039 | 5772 | static void |
cc5703cd | 5773 | mips16_macro (ip) |
3d3c5039 ILT |
5774 | struct mips_cl_insn *ip; |
5775 | { | |
cc5703cd ILT |
5776 | int mask; |
5777 | int xreg, yreg, zreg, tmp; | |
5778 | int icnt; | |
5779 | expressionS expr1; | |
5780 | int dbl; | |
5781 | const char *s, *s2, *s3; | |
3d3c5039 | 5782 | |
cc5703cd | 5783 | mask = ip->insn_mo->mask; |
3d3c5039 | 5784 | |
cc5703cd ILT |
5785 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
5786 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
5787 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 5788 | |
cc5703cd | 5789 | icnt = 0; |
8358c818 | 5790 | |
cc5703cd ILT |
5791 | expr1.X_op = O_constant; |
5792 | expr1.X_op_symbol = NULL; | |
5793 | expr1.X_add_symbol = NULL; | |
5794 | expr1.X_add_number = 1; | |
8358c818 | 5795 | |
cc5703cd | 5796 | dbl = 0; |
517078c1 | 5797 | |
cc5703cd ILT |
5798 | switch (mask) |
5799 | { | |
5800 | default: | |
5801 | internalError (); | |
5802 | ||
5803 | case M_DDIV_3: | |
5804 | dbl = 1; | |
5805 | case M_DIV_3: | |
5806 | s = "mflo"; | |
5807 | goto do_div3; | |
5808 | case M_DREM_3: | |
5809 | dbl = 1; | |
5810 | case M_REM_3: | |
5811 | s = "mfhi"; | |
5812 | do_div3: | |
fbcfacb7 | 5813 | mips_emit_delays (true); |
cc5703cd ILT |
5814 | ++mips_noreorder; |
5815 | mips_any_noreorder = 1; | |
5816 | macro_build ((char *) NULL, &icnt, NULL, | |
5817 | dbl ? "ddiv" : "div", | |
5818 | "0,x,y", xreg, yreg); | |
8a8121d5 | 5819 | expr1.X_add_number = 2; |
cc5703cd | 5820 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5821 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5822 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
5823 | since that causes an overflow. We should do that as well, | |
5824 | but I don't see how to do the comparisons without a temporary | |
5825 | register. */ | |
5826 | --mips_noreorder; | |
5827 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
5828 | break; | |
5829 | ||
5830 | case M_DIVU_3: | |
5831 | s = "divu"; | |
5832 | s2 = "mflo"; | |
5833 | goto do_divu3; | |
5834 | case M_REMU_3: | |
5835 | s = "divu"; | |
5836 | s2 = "mfhi"; | |
5837 | goto do_divu3; | |
5838 | case M_DDIVU_3: | |
5839 | s = "ddivu"; | |
5840 | s2 = "mflo"; | |
5841 | goto do_divu3; | |
5842 | case M_DREMU_3: | |
5843 | s = "ddivu"; | |
5844 | s2 = "mfhi"; | |
5845 | do_divu3: | |
fbcfacb7 | 5846 | mips_emit_delays (true); |
cc5703cd ILT |
5847 | ++mips_noreorder; |
5848 | mips_any_noreorder = 1; | |
5849 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 5850 | expr1.X_add_number = 2; |
cc5703cd | 5851 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
5852 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
5853 | --mips_noreorder; | |
5854 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
5855 | break; | |
5856 | ||
5857 | case M_DSUBU_I: | |
5858 | dbl = 1; | |
5859 | goto do_subu; | |
5860 | case M_SUBU_I: | |
5861 | do_subu: | |
5862 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5863 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
5864 | dbl ? "daddiu" : "addiu", | |
5865 | "y,x,4", yreg, xreg); | |
5866 | break; | |
5867 | ||
5868 | case M_SUBU_I_2: | |
5869 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5870 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
5871 | "x,k", xreg); | |
5872 | break; | |
5873 | ||
5874 | case M_DSUBU_I_2: | |
5875 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
5876 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
5877 | "y,j", yreg); | |
5878 | break; | |
5879 | ||
5880 | case M_BEQ: | |
5881 | s = "cmp"; | |
5882 | s2 = "bteqz"; | |
5883 | goto do_branch; | |
5884 | case M_BNE: | |
5885 | s = "cmp"; | |
5886 | s2 = "btnez"; | |
5887 | goto do_branch; | |
5888 | case M_BLT: | |
5889 | s = "slt"; | |
5890 | s2 = "btnez"; | |
5891 | goto do_branch; | |
5892 | case M_BLTU: | |
5893 | s = "sltu"; | |
5894 | s2 = "btnez"; | |
5895 | goto do_branch; | |
5896 | case M_BLE: | |
5897 | s = "slt"; | |
5898 | s2 = "bteqz"; | |
5899 | goto do_reverse_branch; | |
5900 | case M_BLEU: | |
5901 | s = "sltu"; | |
5902 | s2 = "bteqz"; | |
5903 | goto do_reverse_branch; | |
5904 | case M_BGE: | |
5905 | s = "slt"; | |
5906 | s2 = "bteqz"; | |
5907 | goto do_branch; | |
5908 | case M_BGEU: | |
5909 | s = "sltu"; | |
5910 | s2 = "bteqz"; | |
5911 | goto do_branch; | |
5912 | case M_BGT: | |
5913 | s = "slt"; | |
5914 | s2 = "btnez"; | |
5915 | goto do_reverse_branch; | |
5916 | case M_BGTU: | |
5917 | s = "sltu"; | |
5918 | s2 = "btnez"; | |
5919 | ||
5920 | do_reverse_branch: | |
5921 | tmp = xreg; | |
5922 | xreg = yreg; | |
5923 | yreg = tmp; | |
5924 | ||
5925 | do_branch: | |
5926 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
5927 | xreg, yreg); | |
5928 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
5929 | break; | |
5930 | ||
5931 | case M_BEQ_I: | |
5932 | s = "cmpi"; | |
5933 | s2 = "bteqz"; | |
5934 | s3 = "x,U"; | |
5935 | goto do_branch_i; | |
5936 | case M_BNE_I: | |
5937 | s = "cmpi"; | |
5938 | s2 = "btnez"; | |
5939 | s3 = "x,U"; | |
5940 | goto do_branch_i; | |
5941 | case M_BLT_I: | |
5942 | s = "slti"; | |
5943 | s2 = "btnez"; | |
5944 | s3 = "x,8"; | |
5945 | goto do_branch_i; | |
5946 | case M_BLTU_I: | |
5947 | s = "sltiu"; | |
5948 | s2 = "btnez"; | |
5949 | s3 = "x,8"; | |
5950 | goto do_branch_i; | |
5951 | case M_BLE_I: | |
5952 | s = "slti"; | |
5953 | s2 = "btnez"; | |
5954 | s3 = "x,8"; | |
5955 | goto do_addone_branch_i; | |
5956 | case M_BLEU_I: | |
5957 | s = "sltiu"; | |
5958 | s2 = "btnez"; | |
5959 | s3 = "x,8"; | |
5960 | goto do_addone_branch_i; | |
5961 | case M_BGE_I: | |
5962 | s = "slti"; | |
5963 | s2 = "bteqz"; | |
5964 | s3 = "x,8"; | |
5965 | goto do_branch_i; | |
5966 | case M_BGEU_I: | |
5967 | s = "sltiu"; | |
5968 | s2 = "bteqz"; | |
5969 | s3 = "x,8"; | |
5970 | goto do_branch_i; | |
5971 | case M_BGT_I: | |
5972 | s = "slti"; | |
5973 | s2 = "bteqz"; | |
5974 | s3 = "x,8"; | |
5975 | goto do_addone_branch_i; | |
5976 | case M_BGTU_I: | |
5977 | s = "sltiu"; | |
5978 | s2 = "bteqz"; | |
5979 | s3 = "x,8"; | |
5980 | ||
5981 | do_addone_branch_i: | |
5982 | ++imm_expr.X_add_number; | |
5983 | ||
5984 | do_branch_i: | |
5985 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
5986 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
5987 | break; | |
5988 | } | |
5989 | } | |
5990 | ||
5991 | /* This routine assembles an instruction into its binary format. As a | |
5992 | side effect, it sets one of the global variables imm_reloc or | |
5993 | offset_reloc to the type of relocation to do if one of the operands | |
5994 | is an address expression. */ | |
5995 | ||
5996 | static void | |
5997 | mips_ip (str, ip) | |
5998 | char *str; | |
5999 | struct mips_cl_insn *ip; | |
6000 | { | |
6001 | char *s; | |
6002 | const char *args; | |
6003 | char c; | |
6004 | struct mips_opcode *insn; | |
6005 | char *argsStart; | |
6006 | unsigned int regno; | |
6007 | unsigned int lastregno = 0; | |
6008 | char *s_reset; | |
6009 | ||
6010 | insn_error = NULL; | |
6011 | ||
6012 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '6' || *s == '.'; ++s) | |
6013 | continue; | |
6014 | switch (*s) | |
6015 | { | |
6016 | case '\0': | |
6017 | break; | |
6018 | ||
6019 | case ' ': | |
6020 | *s++ = '\0'; | |
6021 | break; | |
6022 | ||
6023 | default: | |
6024 | as_fatal ("Unknown opcode: `%s'", str); | |
6025 | } | |
6026 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
6027 | { | |
6028 | insn_error = "unrecognized opcode"; | |
6029 | return; | |
6030 | } | |
6031 | argsStart = s; | |
6032 | for (;;) | |
6033 | { | |
6034 | int insn_isa; | |
6035 | ||
6036 | assert (strcmp (insn->name, str) == 0); | |
6037 | ||
6038 | if (insn->pinfo == INSN_MACRO) | |
6039 | insn_isa = insn->match; | |
6040 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA2) | |
6041 | insn_isa = 2; | |
6042 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA3) | |
6043 | insn_isa = 3; | |
6044 | else if ((insn->pinfo & INSN_ISA) == INSN_ISA4) | |
6045 | insn_isa = 4; | |
6046 | else | |
6047 | insn_isa = 1; | |
6048 | ||
6049 | if (insn_isa > mips_isa | |
6050 | || ((insn->pinfo & INSN_ISA) == INSN_4650 | |
6051 | && ! mips_4650) | |
6052 | || ((insn->pinfo & INSN_ISA) == INSN_4010 | |
6053 | && ! mips_4010) | |
6054 | || ((insn->pinfo & INSN_ISA) == INSN_4100 | |
6055 | && ! mips_4100)) | |
6056 | { | |
6057 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6058 | && strcmp (insn->name, insn[1].name) == 0) | |
6059 | { | |
6060 | ++insn; | |
6061 | continue; | |
6062 | } | |
6063 | if (insn_isa <= mips_isa) | |
6064 | insn_error = "opcode not supported on this processor"; | |
6065 | else | |
6066 | { | |
6067 | static char buf[100]; | |
6068 | ||
6069 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6070 | insn_error = buf; | |
6071 | } | |
6072 | return; | |
6073 | } | |
8358c818 | 6074 | |
670a50eb ILT |
6075 | ip->insn_mo = insn; |
6076 | ip->insn_opcode = insn->match; | |
6077 | for (args = insn->args;; ++args) | |
6078 | { | |
6079 | if (*s == ' ') | |
6080 | ++s; | |
6081 | switch (*args) | |
6082 | { | |
6083 | case '\0': /* end of args */ | |
6084 | if (*s == '\0') | |
6085 | return; | |
6086 | break; | |
3d3c5039 ILT |
6087 | |
6088 | case ',': | |
670a50eb ILT |
6089 | if (*s++ == *args) |
6090 | continue; | |
6091 | s--; | |
6092 | switch (*++args) | |
6093 | { | |
3d3c5039 ILT |
6094 | case 'r': |
6095 | case 'v': | |
670a50eb ILT |
6096 | ip->insn_opcode |= lastregno << 21; |
6097 | continue; | |
3d3c5039 ILT |
6098 | |
6099 | case 'w': | |
6100 | case 'W': | |
670a50eb ILT |
6101 | ip->insn_opcode |= lastregno << 16; |
6102 | continue; | |
3d3c5039 ILT |
6103 | |
6104 | case 'V': | |
670a50eb ILT |
6105 | ip->insn_opcode |= lastregno << 11; |
6106 | continue; | |
3d3c5039 | 6107 | } |
670a50eb | 6108 | break; |
3d3c5039 ILT |
6109 | |
6110 | case '(': | |
670a50eb ILT |
6111 | /* handle optional base register. |
6112 | Either the base register is omitted or | |
6113 | we must have a left paren. */ | |
6114 | /* this is dependent on the next operand specifier | |
6115 | is a 'b' for base register */ | |
6116 | assert (args[1] == 'b'); | |
6117 | if (*s == '\0') | |
6118 | return; | |
3d3c5039 | 6119 | |
670a50eb ILT |
6120 | case ')': /* these must match exactly */ |
6121 | if (*s++ == *args) | |
3d3c5039 | 6122 | continue; |
670a50eb ILT |
6123 | break; |
6124 | ||
6125 | case '<': /* must be at least one digit */ | |
6126 | /* | |
6127 | * According to the manual, if the shift amount is greater | |
6128 | * than 31 or less than 0 the the shift amount should be | |
6129 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6130 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6131 | */ |
6132 | my_getExpression (&imm_expr, s); | |
6133 | check_absolute_expr (ip, &imm_expr); | |
6134 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6135 | { | |
58d4951d ILT |
6136 | as_warn ("Improper shift amount (%ld)", |
6137 | (long) imm_expr.X_add_number); | |
9226253a | 6138 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6139 | } |
6140 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6141 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6142 | s = expr_end; |
6143 | continue; | |
6144 | ||
56c96faa ILT |
6145 | case '>': /* shift amount minus 32 */ |
6146 | my_getExpression (&imm_expr, s); | |
6147 | check_absolute_expr (ip, &imm_expr); | |
6148 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6149 | || (unsigned long) imm_expr.X_add_number > 63) | |
6150 | break; | |
6151 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6152 | imm_expr.X_op = O_absent; | |
6153 | s = expr_end; | |
6154 | continue; | |
6155 | ||
9226253a | 6156 | case 'k': /* cache code */ |
d8a1c247 | 6157 | case 'h': /* prefx code */ |
9226253a ILT |
6158 | my_getExpression (&imm_expr, s); |
6159 | check_absolute_expr (ip, &imm_expr); | |
6160 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6161 | { | |
d8a1c247 KR |
6162 | as_warn ("Invalid value for `%s' (%lu)", |
6163 | ip->insn_mo->name, | |
9226253a ILT |
6164 | (unsigned long) imm_expr.X_add_number); |
6165 | imm_expr.X_add_number &= 0x1f; | |
6166 | } | |
d8a1c247 KR |
6167 | if (*args == 'k') |
6168 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6169 | else | |
6170 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6171 | imm_expr.X_op = O_absent; |
6172 | s = expr_end; | |
6173 | continue; | |
6174 | ||
670a50eb ILT |
6175 | case 'c': /* break code */ |
6176 | my_getExpression (&imm_expr, s); | |
6177 | check_absolute_expr (ip, &imm_expr); | |
6178 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6179 | as_warn ("Illegal break code (%ld)", |
6180 | (long) imm_expr.X_add_number); | |
670a50eb | 6181 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6182 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6183 | s = expr_end; |
6184 | continue; | |
6185 | ||
918692a5 ILT |
6186 | case 'B': /* syscall code */ |
6187 | my_getExpression (&imm_expr, s); | |
6188 | check_absolute_expr (ip, &imm_expr); | |
6189 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6190 | as_warn ("Illegal syscall code (%ld)", |
6191 | (long) imm_expr.X_add_number); | |
918692a5 | 6192 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6193 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6194 | s = expr_end; |
6195 | continue; | |
6196 | ||
0aa07269 ILT |
6197 | case 'C': /* Coprocessor code */ |
6198 | my_getExpression (&imm_expr, s); | |
6199 | check_absolute_expr (ip, &imm_expr); | |
6200 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6201 | { | |
58d4951d ILT |
6202 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6203 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6204 | imm_expr.X_add_number &= ((1<<25) - 1); |
6205 | } | |
6206 | ip->insn_opcode |= imm_expr.X_add_number; | |
6207 | imm_expr.X_op = O_absent; | |
6208 | s = expr_end; | |
6209 | continue; | |
6210 | ||
670a50eb ILT |
6211 | case 'b': /* base register */ |
6212 | case 'd': /* destination register */ | |
6213 | case 's': /* source register */ | |
6214 | case 't': /* target register */ | |
6215 | case 'r': /* both target and source */ | |
6216 | case 'v': /* both dest and source */ | |
6217 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6218 | case 'E': /* coprocessor target register */ |
6219 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6220 | case 'x': /* ignore register name */ |
ff3a5c18 | 6221 | case 'z': /* must be zero register */ |
670a50eb ILT |
6222 | s_reset = s; |
6223 | if (s[0] == '$') | |
6224 | { | |
6225 | if (isdigit (s[1])) | |
6226 | { | |
6227 | ++s; | |
6228 | regno = 0; | |
6229 | do | |
6230 | { | |
6231 | regno *= 10; | |
6232 | regno += *s - '0'; | |
6233 | ++s; | |
6234 | } | |
6235 | while (isdigit (*s)); | |
0aa07269 ILT |
6236 | if (regno > 31) |
6237 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6238 | } |
0dd2d296 ILT |
6239 | else if (*args == 'E' || *args == 'G') |
6240 | goto notreg; | |
6241 | else | |
670a50eb | 6242 | { |
0aa07269 ILT |
6243 | if (s[1] == 'f' && s[2] == 'p') |
6244 | { | |
6245 | s += 3; | |
9226253a | 6246 | regno = FP; |
0aa07269 ILT |
6247 | } |
6248 | else if (s[1] == 's' && s[2] == 'p') | |
6249 | { | |
6250 | s += 3; | |
9226253a | 6251 | regno = SP; |
0aa07269 ILT |
6252 | } |
6253 | else if (s[1] == 'g' && s[2] == 'p') | |
6254 | { | |
6255 | s += 3; | |
9226253a | 6256 | regno = GP; |
0aa07269 ILT |
6257 | } |
6258 | else if (s[1] == 'a' && s[2] == 't') | |
6259 | { | |
6260 | s += 3; | |
9226253a | 6261 | regno = AT; |
0aa07269 | 6262 | } |
b2b8c24e ILT |
6263 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6264 | { | |
6265 | s += 4; | |
6266 | regno = KT0; | |
6267 | } | |
6268 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6269 | { | |
6270 | s += 4; | |
6271 | regno = KT1; | |
6272 | } | |
0aa07269 ILT |
6273 | else |
6274 | goto notreg; | |
670a50eb | 6275 | } |
9753202d ILT |
6276 | if (regno == AT |
6277 | && ! mips_noat | |
6278 | && *args != 'E' | |
6279 | && *args != 'G') | |
13fe1379 | 6280 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6281 | c = *args; |
6282 | if (*s == ' ') | |
6283 | s++; | |
6284 | if (args[1] != *s) | |
6285 | { | |
6286 | if (c == 'r' || c == 'v' || c == 'w') | |
6287 | { | |
6288 | regno = lastregno; | |
6289 | s = s_reset; | |
6290 | args++; | |
6291 | } | |
6292 | } | |
ff3a5c18 ILT |
6293 | /* 'z' only matches $0. */ |
6294 | if (c == 'z' && regno != 0) | |
6295 | break; | |
670a50eb ILT |
6296 | switch (c) |
6297 | { | |
3d3c5039 ILT |
6298 | case 'r': |
6299 | case 's': | |
6300 | case 'v': | |
6301 | case 'b': | |
670a50eb ILT |
6302 | ip->insn_opcode |= regno << 21; |
6303 | break; | |
3d3c5039 | 6304 | case 'd': |
918692a5 | 6305 | case 'G': |
670a50eb ILT |
6306 | ip->insn_opcode |= regno << 11; |
6307 | break; | |
3d3c5039 ILT |
6308 | case 'w': |
6309 | case 't': | |
918692a5 | 6310 | case 'E': |
670a50eb | 6311 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6312 | break; |
6313 | case 'x': | |
6314 | /* This case exists because on the r3000 trunc | |
6315 | expands into a macro which requires a gp | |
6316 | register. On the r6000 or r4000 it is | |
6317 | assembled into a single instruction which | |
6318 | ignores the register. Thus the insn version | |
6319 | is MIPS_ISA2 and uses 'x', and the macro | |
6320 | version is MIPS_ISA1 and uses 't'. */ | |
6321 | break; | |
ff3a5c18 ILT |
6322 | case 'z': |
6323 | /* This case is for the div instruction, which | |
6324 | acts differently if the destination argument | |
6325 | is $0. This only matches $0, and is checked | |
6326 | outside the switch. */ | |
6327 | break; | |
3d3c5039 | 6328 | } |
670a50eb ILT |
6329 | lastregno = regno; |
6330 | continue; | |
3d3c5039 ILT |
6331 | } |
6332 | notreg: | |
670a50eb ILT |
6333 | switch (*args++) |
6334 | { | |
3d3c5039 ILT |
6335 | case 'r': |
6336 | case 'v': | |
670a50eb ILT |
6337 | ip->insn_opcode |= lastregno << 21; |
6338 | continue; | |
3d3c5039 | 6339 | case 'w': |
670a50eb ILT |
6340 | ip->insn_opcode |= lastregno << 16; |
6341 | continue; | |
3d3c5039 | 6342 | } |
670a50eb | 6343 | break; |
3d3c5039 | 6344 | |
670a50eb ILT |
6345 | case 'D': /* floating point destination register */ |
6346 | case 'S': /* floating point source register */ | |
6347 | case 'T': /* floating point target register */ | |
d8a1c247 | 6348 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6349 | case 'V': |
6350 | case 'W': | |
670a50eb ILT |
6351 | s_reset = s; |
6352 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6353 | { | |
6354 | s += 2; | |
6355 | regno = 0; | |
6356 | do | |
6357 | { | |
6358 | regno *= 10; | |
6359 | regno += *s - '0'; | |
6360 | ++s; | |
6361 | } | |
6362 | while (isdigit (*s)); | |
6363 | ||
6364 | if (regno > 31) | |
6365 | as_bad ("Invalid float register number (%d)", regno); | |
6366 | ||
9226253a ILT |
6367 | if ((regno & 1) != 0 |
6368 | && mips_isa < 3 | |
538034cf ILT |
6369 | && ! (strcmp (str, "mtc1") == 0 |
6370 | || strcmp (str, "mfc1") == 0 | |
6371 | || strcmp (str, "lwc1") == 0 | |
6372 | || strcmp (str, "swc1") == 0 | |
6373 | || strcmp (str, "l.s") == 0 | |
6374 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6375 | as_warn ("Float register should be even, was %d", |
6376 | regno); | |
6377 | ||
6378 | c = *args; | |
6379 | if (*s == ' ') | |
6380 | s++; | |
6381 | if (args[1] != *s) | |
6382 | { | |
6383 | if (c == 'V' || c == 'W') | |
6384 | { | |
6385 | regno = lastregno; | |
6386 | s = s_reset; | |
6387 | args++; | |
3d3c5039 ILT |
6388 | } |
6389 | } | |
670a50eb ILT |
6390 | switch (c) |
6391 | { | |
3d3c5039 | 6392 | case 'D': |
670a50eb ILT |
6393 | ip->insn_opcode |= regno << 6; |
6394 | break; | |
3d3c5039 ILT |
6395 | case 'V': |
6396 | case 'S': | |
670a50eb ILT |
6397 | ip->insn_opcode |= regno << 11; |
6398 | break; | |
3d3c5039 ILT |
6399 | case 'W': |
6400 | case 'T': | |
670a50eb | 6401 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6402 | break; |
6403 | case 'R': | |
6404 | ip->insn_opcode |= regno << 21; | |
6405 | break; | |
3d3c5039 | 6406 | } |
670a50eb ILT |
6407 | lastregno = regno; |
6408 | continue; | |
3d3c5039 | 6409 | } |
670a50eb ILT |
6410 | switch (*args++) |
6411 | { | |
3d3c5039 | 6412 | case 'V': |
670a50eb ILT |
6413 | ip->insn_opcode |= lastregno << 11; |
6414 | continue; | |
3d3c5039 | 6415 | case 'W': |
670a50eb ILT |
6416 | ip->insn_opcode |= lastregno << 16; |
6417 | continue; | |
3d3c5039 | 6418 | } |
670a50eb | 6419 | break; |
3d3c5039 ILT |
6420 | |
6421 | case 'I': | |
670a50eb | 6422 | my_getExpression (&imm_expr, s); |
9753202d ILT |
6423 | if (imm_expr.X_op != O_big |
6424 | && imm_expr.X_op != O_constant) | |
6425 | insn_error = "absolute expression required"; | |
670a50eb ILT |
6426 | s = expr_end; |
6427 | continue; | |
3d3c5039 ILT |
6428 | |
6429 | case 'A': | |
670a50eb ILT |
6430 | my_getExpression (&offset_expr, s); |
6431 | imm_reloc = BFD_RELOC_32; | |
6432 | s = expr_end; | |
6433 | continue; | |
3d3c5039 ILT |
6434 | |
6435 | case 'F': | |
19ed8960 ILT |
6436 | case 'L': |
6437 | case 'f': | |
6438 | case 'l': | |
6439 | { | |
6440 | int f64; | |
6441 | char *save_in; | |
6442 | char *err; | |
6443 | unsigned char temp[8]; | |
604633ae ILT |
6444 | int len; |
6445 | unsigned int length; | |
19ed8960 ILT |
6446 | segT seg; |
6447 | subsegT subseg; | |
6448 | char *p; | |
6449 | ||
6450 | /* These only appear as the last operand in an | |
6451 | instruction, and every instruction that accepts | |
6452 | them in any variant accepts them in all variants. | |
6453 | This means we don't have to worry about backing out | |
6454 | any changes if the instruction does not match. | |
6455 | ||
6456 | The difference between them is the size of the | |
6457 | floating point constant and where it goes. For 'F' | |
6458 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
6459 | is 32 bits. Where the constant is placed is based | |
6460 | on how the MIPS assembler does things: | |
6461 | F -- .rdata | |
6462 | L -- .lit8 | |
6463 | f -- immediate value | |
6464 | l -- .lit4 | |
0dd2d296 | 6465 | |
55933a58 ILT |
6466 | The .lit4 and .lit8 sections are only used if |
6467 | permitted by the -G argument. | |
6468 | ||
6469 | When generating embedded PIC code, we use the | |
6470 | .lit8 section but not the .lit4 section (we can do | |
6471 | .lit4 inline easily; we need to put .lit8 | |
6472 | somewhere in the data segment, and using .lit8 | |
6473 | permits the linker to eventually combine identical | |
6474 | .lit8 entries). */ | |
19ed8960 ILT |
6475 | |
6476 | f64 = *args == 'F' || *args == 'L'; | |
6477 | ||
6478 | save_in = input_line_pointer; | |
6479 | input_line_pointer = s; | |
604633ae ILT |
6480 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
6481 | length = len; | |
19ed8960 ILT |
6482 | s = input_line_pointer; |
6483 | input_line_pointer = save_in; | |
6484 | if (err != NULL && *err != '\0') | |
6485 | { | |
6486 | as_bad ("Bad floating point constant: %s", err); | |
6487 | memset (temp, '\0', sizeof temp); | |
6488 | length = f64 ? 8 : 4; | |
6489 | } | |
6490 | ||
6491 | assert (length == (f64 ? 8 : 4)); | |
6492 | ||
0dd2d296 | 6493 | if (*args == 'f' |
55933a58 | 6494 | || (*args == 'l' |
1dc1e798 KR |
6495 | && (! USE_GLOBAL_POINTER_OPT |
6496 | || mips_pic == EMBEDDED_PIC | |
1113140a | 6497 | || g_switch_value < 4) |
1113140a | 6498 | )) |
19ed8960 ILT |
6499 | { |
6500 | imm_expr.X_op = O_constant; | |
6501 | if (byte_order == LITTLE_ENDIAN) | |
6502 | imm_expr.X_add_number = | |
6503 | (((((((int) temp[3] << 8) | |
6504 | | temp[2]) << 8) | |
6505 | | temp[1]) << 8) | |
6506 | | temp[0]); | |
6507 | else | |
6508 | imm_expr.X_add_number = | |
6509 | (((((((int) temp[0] << 8) | |
6510 | | temp[1]) << 8) | |
6511 | | temp[2]) << 8) | |
6512 | | temp[3]); | |
6513 | } | |
6514 | else | |
6515 | { | |
0dd2d296 ILT |
6516 | const char *newname; |
6517 | segT new_seg; | |
6518 | ||
19ed8960 ILT |
6519 | /* Switch to the right section. */ |
6520 | seg = now_seg; | |
6521 | subseg = now_subseg; | |
6522 | switch (*args) | |
6523 | { | |
0dd2d296 | 6524 | default: /* unused default case avoids warnings. */ |
19ed8960 | 6525 | case 'L': |
1113140a | 6526 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 6527 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 6528 | newname = ".lit8"; |
0dd2d296 ILT |
6529 | break; |
6530 | case 'F': | |
d2c71068 | 6531 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
6532 | break; |
6533 | case 'l': | |
1dc1e798 KR |
6534 | assert (!USE_GLOBAL_POINTER_OPT |
6535 | || g_switch_value >= 4); | |
0dd2d296 | 6536 | newname = ".lit4"; |
19ed8960 ILT |
6537 | break; |
6538 | } | |
0dd2d296 | 6539 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
6540 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6541 | bfd_set_section_flags (stdoutput, new_seg, | |
6542 | (SEC_ALLOC | |
6543 | | SEC_LOAD | |
6544 | | SEC_READONLY | |
6545 | | SEC_DATA)); | |
0221ddf7 | 6546 | frag_align (*args == 'l' ? 2 : 3, 0); |
1dc1e798 KR |
6547 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
6548 | record_alignment (new_seg, 4); | |
6549 | else | |
6550 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
6551 | if (seg == now_seg) |
6552 | as_bad ("Can't use floating point insn in this section"); | |
6553 | ||
6554 | /* Set the argument to the current address in the | |
6e8dda9c | 6555 | section. */ |
19ed8960 ILT |
6556 | offset_expr.X_op = O_symbol; |
6557 | offset_expr.X_add_symbol = | |
6558 | symbol_new ("L0\001", now_seg, | |
6559 | (valueT) frag_now_fix (), frag_now); | |
6560 | offset_expr.X_add_number = 0; | |
6561 | ||
6562 | /* Put the floating point number into the section. */ | |
604633ae | 6563 | p = frag_more ((int) length); |
19ed8960 ILT |
6564 | memcpy (p, temp, length); |
6565 | ||
6566 | /* Switch back to the original section. */ | |
6567 | subseg_set (seg, subseg); | |
6568 | } | |
6569 | } | |
670a50eb ILT |
6570 | continue; |
6571 | ||
6572 | case 'i': /* 16 bit unsigned immediate */ | |
6573 | case 'j': /* 16 bit signed immediate */ | |
6574 | imm_reloc = BFD_RELOC_LO16; | |
6575 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 6576 | if (c != '\0') |
670a50eb ILT |
6577 | { |
6578 | if (c != 'l') | |
6579 | { | |
5ac34ac3 | 6580 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
6581 | imm_expr.X_add_number = |
6582 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6583 | else if (c == 'h') | |
867a58b3 ILT |
6584 | { |
6585 | imm_reloc = BFD_RELOC_HI16_S; | |
6586 | imm_unmatched_hi = true; | |
6587 | } | |
670a50eb ILT |
6588 | else |
6589 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 6590 | } |
670a50eb | 6591 | } |
670a50eb ILT |
6592 | if (*args == 'i') |
6593 | { | |
344a8d61 | 6594 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6595 | || ((imm_expr.X_add_number < 0 |
6596 | || imm_expr.X_add_number >= 0x10000) | |
6597 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
6598 | { |
6599 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6600 | !strcmp (insn->name, insn[1].name)) | |
6601 | break; | |
9753202d ILT |
6602 | if (imm_expr.X_op != O_constant |
6603 | && imm_expr.X_op != O_big) | |
6604 | insn_error = "absolute expression required"; | |
6605 | else | |
6606 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 6607 | } |
670a50eb ILT |
6608 | } |
6609 | else | |
6610 | { | |
d9aba805 ILT |
6611 | int more; |
6612 | offsetT max; | |
6613 | ||
be22008b ILT |
6614 | /* The upper bound should be 0x8000, but |
6615 | unfortunately the MIPS assembler accepts numbers | |
6616 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
6617 | we want to be compatible. We only permit this |
6618 | extended range for an instruction which does not | |
6619 | provide any further alternates, since those | |
6620 | alternates may handle other cases. People should | |
6621 | use the numbers they mean, rather than relying on | |
6622 | a mysterious sign extension. */ | |
6623 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6624 | strcmp (insn->name, insn[1].name) == 0); | |
6625 | if (more) | |
6626 | max = 0x8000; | |
6627 | else | |
6628 | max = 0x10000; | |
344a8d61 | 6629 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
6630 | || ((imm_expr.X_add_number < -0x8000 |
6631 | || imm_expr.X_add_number >= max) | |
6632 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
6633 | || (more |
6634 | && imm_expr.X_add_number < 0 | |
6635 | && mips_isa >= 3 | |
6636 | && imm_expr.X_unsigned | |
6637 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 6638 | { |
d9aba805 | 6639 | if (more) |
99c24539 | 6640 | break; |
9753202d ILT |
6641 | if (imm_expr.X_op != O_constant |
6642 | && imm_expr.X_op != O_big) | |
6643 | insn_error = "absolute expression required"; | |
6644 | else | |
6645 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 6646 | } |
3d3c5039 | 6647 | } |
670a50eb ILT |
6648 | s = expr_end; |
6649 | continue; | |
6650 | ||
6651 | case 'o': /* 16 bit offset */ | |
6652 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
6653 | |
6654 | /* If this value won't fit into a 16 bit offset, then go | |
6655 | find a macro that will generate the 32 bit offset | |
6656 | code pattern. As a special hack, we accept the | |
6657 | difference of two local symbols as a constant. This | |
6658 | is required to suppose embedded PIC switches, which | |
6659 | use an instruction which looks like | |
6660 | lw $4,$L12-$LS12($4) | |
6661 | The problem with handling this in a more general | |
6662 | fashion is that the macro function doesn't expect to | |
6663 | see anything which can be handled in a single | |
6664 | constant instruction. */ | |
6f0b87c3 SS |
6665 | if (c == 0 |
6666 | && (offset_expr.X_op != O_constant | |
6667 | || offset_expr.X_add_number >= 0x8000 | |
6668 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
6669 | && (mips_pic != EMBEDDED_PIC |
6670 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
6671 | || now_seg != text_section |
6672 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
6673 | != text_section))) | |
670a50eb | 6674 | break; |
3d3c5039 | 6675 | |
670a50eb ILT |
6676 | offset_reloc = BFD_RELOC_LO16; |
6677 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
6678 | { |
6679 | assert (offset_expr.X_op == O_constant); | |
6680 | offset_expr.X_add_number = | |
6681 | (offset_expr.X_add_number >> 16) & 0xffff; | |
6682 | } | |
cc5703cd ILT |
6683 | s = expr_end; |
6684 | continue; | |
6685 | ||
6686 | case 'p': /* pc relative offset */ | |
6687 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
6688 | my_getExpression (&offset_expr, s); | |
6689 | s = expr_end; | |
6690 | continue; | |
6691 | ||
6692 | case 'u': /* upper 16 bits */ | |
6693 | c = my_getSmallExpression (&imm_expr, s); | |
6694 | if (imm_expr.X_op == O_constant | |
6695 | && (imm_expr.X_add_number < 0 | |
6696 | || imm_expr.X_add_number >= 0x10000)) | |
6697 | as_bad ("lui expression not in range 0..65535"); | |
6698 | imm_reloc = BFD_RELOC_LO16; | |
6699 | if (c) | |
6700 | { | |
6701 | if (c != 'l') | |
6702 | { | |
6703 | if (imm_expr.X_op == O_constant) | |
6704 | imm_expr.X_add_number = | |
6705 | (imm_expr.X_add_number >> 16) & 0xffff; | |
6706 | else if (c == 'h') | |
6707 | { | |
6708 | imm_reloc = BFD_RELOC_HI16_S; | |
6709 | imm_unmatched_hi = true; | |
6710 | } | |
6711 | else | |
6712 | imm_reloc = BFD_RELOC_HI16; | |
6713 | } | |
6714 | } | |
6715 | s = expr_end; | |
6716 | continue; | |
6717 | ||
6718 | case 'a': /* 26 bit address */ | |
6719 | my_getExpression (&offset_expr, s); | |
6720 | s = expr_end; | |
6721 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
6722 | continue; | |
6723 | ||
6724 | case 'N': /* 3 bit branch condition code */ | |
6725 | case 'M': /* 3 bit compare condition code */ | |
6726 | if (strncmp (s, "$fcc", 4) != 0) | |
6727 | break; | |
6728 | s += 4; | |
6729 | regno = 0; | |
6730 | do | |
6731 | { | |
6732 | regno *= 10; | |
6733 | regno += *s - '0'; | |
6734 | ++s; | |
6735 | } | |
6736 | while (isdigit (*s)); | |
6737 | if (regno > 7) | |
6738 | as_bad ("invalid condition code register $fcc%d", regno); | |
6739 | if (*args == 'N') | |
6740 | ip->insn_opcode |= regno << OP_SH_BCC; | |
6741 | else | |
6742 | ip->insn_opcode |= regno << OP_SH_CCC; | |
6743 | continue; | |
6744 | ||
6745 | default: | |
6746 | fprintf (stderr, "bad char = '%c'\n", *args); | |
6747 | internalError (); | |
6748 | } | |
6749 | break; | |
6750 | } | |
6751 | /* Args don't match. */ | |
6752 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
6753 | !strcmp (insn->name, insn[1].name)) | |
6754 | { | |
6755 | ++insn; | |
6756 | s = argsStart; | |
6757 | continue; | |
6758 | } | |
6759 | insn_error = "illegal operands"; | |
6760 | return; | |
6761 | } | |
6762 | } | |
6763 | ||
6764 | /* This routine assembles an instruction into its binary format when | |
6765 | assembling for the mips16. As a side effect, it sets one of the | |
6766 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
6767 | relocation to do if one of the operands is an address expression. |
6768 | It also sets mips16_small and mips16_ext if the user explicitly | |
6769 | requested a small or extended instruction. */ | |
cc5703cd ILT |
6770 | |
6771 | static void | |
6772 | mips16_ip (str, ip) | |
6773 | char *str; | |
6774 | struct mips_cl_insn *ip; | |
6775 | { | |
6776 | char *s; | |
cc5703cd ILT |
6777 | const char *args; |
6778 | struct mips_opcode *insn; | |
6779 | char *argsstart; | |
6780 | unsigned int regno; | |
6781 | unsigned int lastregno = 0; | |
6782 | char *s_reset; | |
6783 | ||
6784 | insn_error = NULL; | |
6785 | ||
8728fa92 ILT |
6786 | mips16_small = false; |
6787 | mips16_ext = false; | |
cc5703cd ILT |
6788 | |
6789 | for (s = str; islower (*s); ++s) | |
6790 | ; | |
6791 | switch (*s) | |
6792 | { | |
6793 | case '\0': | |
6794 | break; | |
6795 | ||
6796 | case ' ': | |
6797 | *s++ = '\0'; | |
6798 | break; | |
6799 | ||
6800 | case '.': | |
6801 | if (s[1] == 't' && s[2] == ' ') | |
6802 | { | |
6803 | *s = '\0'; | |
8728fa92 | 6804 | mips16_small = true; |
cc5703cd ILT |
6805 | s += 3; |
6806 | break; | |
6807 | } | |
6808 | else if (s[1] == 'e' && s[2] == ' ') | |
6809 | { | |
6810 | *s = '\0'; | |
8728fa92 | 6811 | mips16_ext = true; |
cc5703cd ILT |
6812 | s += 3; |
6813 | break; | |
6814 | } | |
6815 | /* Fall through. */ | |
6816 | default: | |
6817 | insn_error = "unknown opcode"; | |
6818 | return; | |
6819 | } | |
6820 | ||
8728fa92 ILT |
6821 | if (! mips16_autoextend && ! mips16_ext) |
6822 | mips16_small = true; | |
6823 | ||
cc5703cd ILT |
6824 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
6825 | { | |
6826 | insn_error = "unrecognized opcode"; | |
6827 | return; | |
6828 | } | |
6829 | ||
6830 | argsstart = s; | |
6831 | for (;;) | |
6832 | { | |
6833 | assert (strcmp (insn->name, str) == 0); | |
6834 | ||
6835 | ip->insn_mo = insn; | |
6836 | ip->insn_opcode = insn->match; | |
6837 | ip->use_extend = false; | |
6838 | imm_expr.X_op = O_absent; | |
6839 | imm_reloc = BFD_RELOC_UNUSED; | |
6840 | offset_expr.X_op = O_absent; | |
6841 | offset_reloc = BFD_RELOC_UNUSED; | |
6842 | for (args = insn->args; 1; ++args) | |
6843 | { | |
6844 | int c; | |
6845 | ||
6846 | if (*s == ' ') | |
6847 | ++s; | |
6848 | ||
6849 | /* In this switch statement we call break if we did not find | |
6850 | a match, continue if we did find a match, or return if we | |
6851 | are done. */ | |
6852 | ||
6853 | c = *args; | |
6854 | switch (c) | |
6855 | { | |
6856 | case '\0': | |
6857 | if (*s == '\0') | |
6858 | { | |
6859 | /* Stuff the immediate value in now, if we can. */ | |
6860 | if (imm_expr.X_op == O_constant | |
6861 | && imm_reloc > BFD_RELOC_UNUSED | |
6862 | && insn->pinfo != INSN_MACRO) | |
6863 | { | |
15e69f98 ILT |
6864 | mips16_immed ((char *) NULL, 0, |
6865 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
6866 | imm_expr.X_add_number, true, mips16_small, |
6867 | mips16_ext, &ip->insn_opcode, | |
6868 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
6869 | imm_expr.X_op = O_absent; |
6870 | imm_reloc = BFD_RELOC_UNUSED; | |
6871 | } | |
6872 | ||
6873 | return; | |
6874 | } | |
6875 | break; | |
6876 | ||
6877 | case ',': | |
6878 | if (*s++ == c) | |
6879 | continue; | |
6880 | s--; | |
6881 | switch (*++args) | |
6882 | { | |
6883 | case 'v': | |
6884 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6885 | continue; | |
6886 | case 'w': | |
6887 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6888 | continue; | |
6889 | } | |
6890 | break; | |
6891 | ||
6892 | case '(': | |
6893 | case ')': | |
6894 | if (*s++ == c) | |
6895 | continue; | |
6896 | break; | |
6897 | ||
6898 | case 'v': | |
6899 | case 'w': | |
6900 | if (s[0] != '$') | |
6901 | { | |
6902 | if (c == 'v') | |
6903 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
6904 | else | |
6905 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
6906 | ++args; | |
6907 | continue; | |
6908 | } | |
6909 | /* Fall through. */ | |
6910 | case 'x': | |
6911 | case 'y': | |
6912 | case 'z': | |
6913 | case 'Z': | |
6914 | case '0': | |
6915 | case 'S': | |
6916 | case 'R': | |
6917 | case 'X': | |
6918 | case 'Y': | |
6919 | if (s[0] != '$') | |
6920 | break; | |
6921 | s_reset = s; | |
6922 | if (isdigit (s[1])) | |
6923 | { | |
6924 | ++s; | |
6925 | regno = 0; | |
6926 | do | |
6927 | { | |
6928 | regno *= 10; | |
6929 | regno += *s - '0'; | |
6930 | ++s; | |
6931 | } | |
6932 | while (isdigit (*s)); | |
6933 | if (regno > 31) | |
6934 | { | |
6935 | as_bad ("invalid register number (%d)", regno); | |
6936 | regno = 2; | |
6937 | } | |
6938 | } | |
6939 | else | |
6940 | { | |
6941 | if (s[1] == 'f' && s[2] == 'p') | |
6942 | { | |
6943 | s += 3; | |
6944 | regno = FP; | |
6945 | } | |
6946 | else if (s[1] == 's' && s[2] == 'p') | |
6947 | { | |
6948 | s += 3; | |
6949 | regno = SP; | |
6950 | } | |
6951 | else if (s[1] == 'g' && s[2] == 'p') | |
6952 | { | |
6953 | s += 3; | |
6954 | regno = GP; | |
6955 | } | |
6956 | else if (s[1] == 'a' && s[2] == 't') | |
6957 | { | |
6958 | s += 3; | |
6959 | regno = AT; | |
6960 | } | |
6961 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
6962 | { | |
6963 | s += 4; | |
6964 | regno = KT0; | |
6965 | } | |
6966 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6967 | { | |
6968 | s += 4; | |
6969 | regno = KT1; | |
6970 | } | |
6971 | else | |
6972 | break; | |
6973 | } | |
6974 | ||
6975 | if (*s == ' ') | |
6976 | ++s; | |
6977 | if (args[1] != *s) | |
6978 | { | |
6979 | if (c == 'v' || c == 'w') | |
6980 | { | |
6981 | regno = mips16_to_32_reg_map[lastregno]; | |
6982 | s = s_reset; | |
6983 | args++; | |
6984 | } | |
6985 | } | |
6986 | ||
6987 | switch (c) | |
6988 | { | |
6989 | case 'x': | |
6990 | case 'y': | |
6991 | case 'z': | |
6992 | case 'v': | |
6993 | case 'w': | |
6994 | case 'Z': | |
6995 | regno = mips32_to_16_reg_map[regno]; | |
6996 | break; | |
6997 | ||
6998 | case '0': | |
6999 | if (regno != 0) | |
7000 | regno = ILLEGAL_REG; | |
7001 | break; | |
7002 | ||
7003 | case 'S': | |
7004 | if (regno != SP) | |
7005 | regno = ILLEGAL_REG; | |
7006 | break; | |
7007 | ||
7008 | case 'R': | |
7009 | if (regno != RA) | |
7010 | regno = ILLEGAL_REG; | |
7011 | break; | |
7012 | ||
7013 | case 'X': | |
7014 | case 'Y': | |
7015 | if (regno == AT && ! mips_noat) | |
7016 | as_warn ("used $at without \".set noat\""); | |
7017 | break; | |
7018 | ||
7019 | default: | |
7020 | internalError (); | |
7021 | } | |
7022 | ||
7023 | if (regno == ILLEGAL_REG) | |
7024 | break; | |
7025 | ||
7026 | switch (c) | |
7027 | { | |
7028 | case 'x': | |
7029 | case 'v': | |
7030 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7031 | break; | |
7032 | case 'y': | |
7033 | case 'w': | |
7034 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7035 | break; | |
7036 | case 'z': | |
7037 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7038 | break; | |
7039 | case 'Z': | |
7040 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7041 | case '0': | |
7042 | case 'S': | |
7043 | case 'R': | |
7044 | break; | |
7045 | case 'X': | |
7046 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7047 | break; | |
7048 | case 'Y': | |
7049 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7050 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7051 | break; | |
7052 | default: | |
7053 | internalError (); | |
7054 | } | |
7055 | ||
7056 | lastregno = regno; | |
7057 | continue; | |
7058 | ||
7059 | case 'P': | |
7060 | if (strncmp (s, "$pc", 3) == 0) | |
7061 | { | |
7062 | s += 3; | |
7063 | continue; | |
7064 | } | |
7065 | break; | |
7066 | ||
7067 | case '<': | |
7068 | case '>': | |
7069 | case '[': | |
7070 | case ']': | |
7071 | case '4': | |
7072 | case '5': | |
7073 | case 'H': | |
7074 | case 'W': | |
7075 | case 'D': | |
7076 | case 'j': | |
7077 | case '8': | |
7078 | case 'V': | |
7079 | case 'C': | |
7080 | case 'U': | |
7081 | case 'k': | |
7082 | case 'K': | |
7083 | if (s[0] == '$' && isdigit (s[1])) | |
7084 | { | |
7085 | /* Looks like a register name. */ | |
7086 | break; | |
7087 | } | |
c0dea495 ILT |
7088 | |
7089 | if (s[0] == '(' | |
7090 | && args[1] == '(' | |
7091 | && s[1] == '$') | |
7092 | { | |
7093 | /* It looks like the expression was omitted before a | |
7094 | register indirection, which means that the | |
7095 | expression is implicitly zero. */ | |
7096 | continue; | |
7097 | } | |
7098 | ||
cc5703cd ILT |
7099 | my_getExpression (&imm_expr, s); |
7100 | /* We need to relax this instruction. */ | |
7101 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7102 | s = expr_end; | |
7103 | continue; | |
7104 | ||
7105 | case 'p': | |
7106 | case 'q': | |
7107 | case 'A': | |
7108 | case 'B': | |
7109 | case 'E': | |
7110 | /* We use offset_reloc rather than imm_reloc for the PC | |
7111 | relative operands. This lets macros with both | |
7112 | immediate and address operands work correctly. */ | |
7113 | if (s[0] == '$' && isdigit (s[1])) | |
7114 | { | |
7115 | /* Looks like a register name. */ | |
7116 | break; | |
7117 | } | |
670a50eb | 7118 | my_getExpression (&offset_expr, s); |
cc5703cd ILT |
7119 | /* We need to relax this instruction. */ |
7120 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7121 | s = expr_end; |
7122 | continue; | |
7123 | ||
cc5703cd ILT |
7124 | case '6': /* break code */ |
7125 | my_getExpression (&imm_expr, s); | |
7126 | check_absolute_expr (ip, &imm_expr); | |
7127 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7128 | { |
cc5703cd ILT |
7129 | as_warn ("Invalid value for `%s' (%lu)", |
7130 | ip->insn_mo->name, | |
7131 | (unsigned long) imm_expr.X_add_number); | |
7132 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7133 | } |
cc5703cd ILT |
7134 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7135 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7136 | s = expr_end; |
7137 | continue; | |
3d3c5039 | 7138 | |
670a50eb ILT |
7139 | case 'a': /* 26 bit address */ |
7140 | my_getExpression (&offset_expr, s); | |
7141 | s = expr_end; | |
cc5703cd ILT |
7142 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7143 | ip->insn_opcode <<= 16; | |
670a50eb | 7144 | continue; |
3d3c5039 | 7145 | |
cc5703cd ILT |
7146 | case 'l': /* register list for entry macro */ |
7147 | case 'L': /* register list for exit macro */ | |
7148 | { | |
7149 | int mask; | |
7150 | ||
7151 | if (c == 'l') | |
7152 | mask = 0; | |
7153 | else | |
7154 | mask = 7 << 3; | |
7155 | while (*s != '\0') | |
7156 | { | |
7157 | int reg1, reg2; | |
7158 | ||
7159 | while (*s == ' ' || *s == ',') | |
7160 | ++s; | |
7161 | if (*s != '$') | |
7162 | { | |
7163 | as_bad ("can't parse register list"); | |
7164 | break; | |
7165 | } | |
7166 | ++s; | |
7167 | reg1 = 0; | |
7168 | while (isdigit (*s)) | |
7169 | { | |
7170 | reg1 *= 10; | |
7171 | reg1 += *s - '0'; | |
7172 | ++s; | |
7173 | } | |
7174 | if (*s == ' ') | |
7175 | ++s; | |
7176 | if (*s != '-') | |
7177 | reg2 = reg1; | |
7178 | else | |
7179 | { | |
7180 | ++s; | |
7181 | if (*s != '$') | |
7182 | break; | |
7183 | ++s; | |
7184 | reg2 = 0; | |
7185 | while (isdigit (*s)) | |
7186 | { | |
7187 | reg2 *= 10; | |
7188 | reg2 += *s - '0'; | |
7189 | ++s; | |
7190 | } | |
7191 | } | |
7192 | if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
7193 | mask |= (reg2 - 3) << 3; | |
7194 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7195 | mask |= (reg2 - 15) << 1; | |
7196 | else if (reg1 == 31 && reg2 == 31) | |
7197 | mask |= 1; | |
7198 | else | |
7199 | as_bad ("invalid register list"); | |
7200 | } | |
7201 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
7202 | } | |
7203 | continue; | |
d8a1c247 | 7204 | |
3d3c5039 | 7205 | default: |
670a50eb | 7206 | internalError (); |
3d3c5039 | 7207 | } |
670a50eb | 7208 | break; |
3d3c5039 | 7209 | } |
cc5703cd | 7210 | |
670a50eb | 7211 | /* Args don't match. */ |
cc5703cd ILT |
7212 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7213 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7214 | { |
7215 | ++insn; | |
cc5703cd | 7216 | s = argsstart; |
670a50eb | 7217 | continue; |
3d3c5039 | 7218 | } |
cc5703cd | 7219 | |
9753202d | 7220 | insn_error = "illegal operands"; |
cc5703cd | 7221 | |
670a50eb | 7222 | return; |
3d3c5039 ILT |
7223 | } |
7224 | } | |
7225 | ||
cc5703cd ILT |
7226 | /* This structure holds information we know about a mips16 immediate |
7227 | argument type. */ | |
7228 | ||
7229 | struct mips16_immed_operand | |
7230 | { | |
7231 | /* The type code used in the argument string in the opcode table. */ | |
7232 | int type; | |
7233 | /* The number of bits in the short form of the opcode. */ | |
7234 | int nbits; | |
7235 | /* The number of bits in the extended form of the opcode. */ | |
7236 | int extbits; | |
7237 | /* The amount by which the short form is shifted when it is used; | |
7238 | for example, the sw instruction has a shift count of 2. */ | |
7239 | int shift; | |
7240 | /* The amount by which the short form is shifted when it is stored | |
7241 | into the instruction code. */ | |
7242 | int op_shift; | |
7243 | /* Non-zero if the short form is unsigned. */ | |
7244 | int unsp; | |
7245 | /* Non-zero if the extended form is unsigned. */ | |
7246 | int extu; | |
7247 | /* Non-zero if the value is PC relative. */ | |
7248 | int pcrel; | |
7249 | }; | |
7250 | ||
7251 | /* The mips16 immediate operand types. */ | |
7252 | ||
7253 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7254 | { | |
7255 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7256 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7257 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7258 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7259 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7260 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7261 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7262 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7263 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7264 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7265 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7266 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7267 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7268 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7269 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7270 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7271 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7272 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7273 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7274 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7275 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7276 | }; | |
7277 | ||
7278 | #define MIPS16_NUM_IMMED \ | |
7279 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7280 | ||
7281 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7282 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7283 | whether an extended value is needed; if one is needed, it sets | |
7284 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7285 | If SMALL is true, an unextended opcode was explicitly requested. | |
7286 | If EXT is true, an extended opcode was explicitly requested. If | |
7287 | WARN is true, warn if EXT does not match reality. */ | |
7288 | ||
7289 | static void | |
15e69f98 ILT |
7290 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
7291 | extend) | |
7292 | char *file; | |
7293 | unsigned int line; | |
cc5703cd ILT |
7294 | int type; |
7295 | offsetT val; | |
7296 | boolean warn; | |
7297 | boolean small; | |
7298 | boolean ext; | |
7299 | unsigned long *insn; | |
7300 | boolean *use_extend; | |
7301 | unsigned short *extend; | |
7302 | { | |
7303 | register const struct mips16_immed_operand *op; | |
7304 | int mintiny, maxtiny; | |
7305 | boolean needext; | |
7306 | ||
7307 | op = mips16_immed_operands; | |
7308 | while (op->type != type) | |
7309 | { | |
7310 | ++op; | |
7311 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
7312 | } | |
7313 | ||
7314 | if (op->unsp) | |
7315 | { | |
7316 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
7317 | { | |
7318 | mintiny = 1; | |
7319 | maxtiny = 1 << op->nbits; | |
7320 | } | |
7321 | else | |
7322 | { | |
7323 | mintiny = 0; | |
7324 | maxtiny = (1 << op->nbits) - 1; | |
7325 | } | |
7326 | } | |
7327 | else | |
7328 | { | |
7329 | mintiny = - (1 << (op->nbits - 1)); | |
7330 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
7331 | } | |
7332 | ||
7333 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
7334 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 7335 | val /= 2; |
cc5703cd ILT |
7336 | |
7337 | if ((val & ((1 << op->shift) - 1)) != 0 | |
7338 | || val < (mintiny << op->shift) | |
7339 | || val > (maxtiny << op->shift)) | |
7340 | needext = true; | |
7341 | else | |
7342 | needext = false; | |
7343 | ||
7344 | if (warn && ext && ! needext) | |
15e69f98 | 7345 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 7346 | if (small && needext) |
15e69f98 | 7347 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
7348 | |
7349 | if (small || (! ext && ! needext)) | |
7350 | { | |
7351 | int insnval; | |
7352 | ||
7353 | *use_extend = false; | |
7354 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
7355 | insnval <<= op->op_shift; | |
7356 | *insn |= insnval; | |
7357 | } | |
7358 | else | |
7359 | { | |
7360 | long minext, maxext; | |
7361 | int extval; | |
7362 | ||
7363 | if (op->extu) | |
7364 | { | |
7365 | minext = 0; | |
7366 | maxext = (1 << op->extbits) - 1; | |
7367 | } | |
7368 | else | |
7369 | { | |
7370 | minext = - (1 << (op->extbits - 1)); | |
7371 | maxext = (1 << (op->extbits - 1)) - 1; | |
7372 | } | |
7373 | if (val < minext || val > maxext) | |
15e69f98 ILT |
7374 | as_bad_where (file, line, |
7375 | "operand value out of range for instruction"); | |
cc5703cd ILT |
7376 | |
7377 | *use_extend = true; | |
7378 | if (op->extbits == 16) | |
7379 | { | |
7380 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
7381 | val &= 0x1f; | |
7382 | } | |
7383 | else if (op->extbits == 15) | |
7384 | { | |
7385 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
7386 | val &= 0xf; | |
7387 | } | |
7388 | else | |
7389 | { | |
7390 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
7391 | val = 0; | |
7392 | } | |
7393 | ||
7394 | *extend = (unsigned short) extval; | |
7395 | *insn |= val; | |
7396 | } | |
7397 | } | |
7398 | \f | |
3d3c5039 ILT |
7399 | #define LP '(' |
7400 | #define RP ')' | |
7401 | ||
7402 | static int | |
7403 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
7404 | expressionS *ep; |
7405 | char *str; | |
3d3c5039 | 7406 | { |
670a50eb ILT |
7407 | char *sp; |
7408 | int c = 0; | |
7409 | ||
7410 | if (*str == ' ') | |
7411 | str++; | |
7412 | if (*str == LP | |
7413 | || (*str == '%' && | |
7414 | ((str[1] == 'h' && str[2] == 'i') | |
7415 | || (str[1] == 'H' && str[2] == 'I') | |
7416 | || (str[1] == 'l' && str[2] == 'o')) | |
7417 | && str[3] == LP)) | |
7418 | { | |
7419 | if (*str == LP) | |
7420 | c = 0; | |
7421 | else | |
7422 | { | |
7423 | c = str[1]; | |
7424 | str += 3; | |
7425 | } | |
7426 | ||
7427 | /* | |
7428 | * A small expression may be followed by a base register. | |
7429 | * Scan to the end of this operand, and then back over a possible | |
7430 | * base register. Then scan the small expression up to that | |
7431 | * point. (Based on code in sparc.c...) | |
7432 | */ | |
7433 | for (sp = str; *sp && *sp != ','; sp++) | |
7434 | ; | |
7435 | if (sp - 4 >= str && sp[-1] == RP) | |
7436 | { | |
7437 | if (isdigit (sp[-2])) | |
7438 | { | |
7439 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
7440 | ; | |
7441 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
7442 | { | |
7443 | sp--; | |
7444 | goto do_it; | |
3d3c5039 | 7445 | } |
670a50eb ILT |
7446 | } |
7447 | else if (sp - 5 >= str | |
7448 | && sp[-5] == LP | |
7449 | && sp[-4] == '$' | |
7450 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
7451 | || (sp[-3] == 's' && sp[-2] == 'p') | |
7452 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
7453 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
7454 | { | |
7455 | sp -= 5; | |
3d3c5039 | 7456 | do_it: |
670a50eb ILT |
7457 | if (sp == str) |
7458 | { | |
7459 | /* no expression means zero offset */ | |
7460 | if (c) | |
7461 | { | |
7462 | /* %xx(reg) is an error */ | |
5ac34ac3 | 7463 | ep->X_op = O_absent; |
670a50eb | 7464 | expr_end = str - 3; |
3d3c5039 | 7465 | } |
670a50eb ILT |
7466 | else |
7467 | { | |
52aa70b5 | 7468 | ep->X_op = O_constant; |
670a50eb ILT |
7469 | expr_end = sp; |
7470 | } | |
7471 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 7472 | ep->X_op_symbol = NULL; |
670a50eb ILT |
7473 | ep->X_add_number = 0; |
7474 | } | |
7475 | else | |
7476 | { | |
7477 | *sp = '\0'; | |
7478 | my_getExpression (ep, str); | |
7479 | *sp = LP; | |
3d3c5039 | 7480 | } |
670a50eb | 7481 | return c; |
3d3c5039 ILT |
7482 | } |
7483 | } | |
7484 | } | |
670a50eb ILT |
7485 | my_getExpression (ep, str); |
7486 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
7487 | } |
7488 | ||
7489 | static void | |
7490 | my_getExpression (ep, str) | |
670a50eb ILT |
7491 | expressionS *ep; |
7492 | char *str; | |
3d3c5039 | 7493 | { |
670a50eb | 7494 | char *save_in; |
670a50eb ILT |
7495 | |
7496 | save_in = input_line_pointer; | |
7497 | input_line_pointer = str; | |
5ac34ac3 | 7498 | expression (ep); |
670a50eb ILT |
7499 | expr_end = input_line_pointer; |
7500 | input_line_pointer = save_in; | |
3d3c5039 ILT |
7501 | } |
7502 | ||
becfe05e ILT |
7503 | /* Turn a string in input_line_pointer into a floating point constant |
7504 | of type type, and store the appropriate bytes in *litP. The number | |
7505 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
7506 | returned, or NULL on OK. */ | |
7507 | ||
3d3c5039 | 7508 | char * |
670a50eb | 7509 | md_atof (type, litP, sizeP) |
becfe05e | 7510 | int type; |
3d3c5039 ILT |
7511 | char *litP; |
7512 | int *sizeP; | |
7513 | { | |
becfe05e ILT |
7514 | int prec; |
7515 | LITTLENUM_TYPE words[4]; | |
7516 | char *t; | |
7517 | int i; | |
7518 | ||
7519 | switch (type) | |
7520 | { | |
7521 | case 'f': | |
7522 | prec = 2; | |
7523 | break; | |
7524 | ||
7525 | case 'd': | |
7526 | prec = 4; | |
7527 | break; | |
7528 | ||
7529 | default: | |
7530 | *sizeP = 0; | |
7531 | return "bad call to md_atof"; | |
7532 | } | |
7533 | ||
7534 | t = atof_ieee (input_line_pointer, type, words); | |
7535 | if (t) | |
7536 | input_line_pointer = t; | |
7537 | ||
7538 | *sizeP = prec * 2; | |
7539 | ||
7540 | if (byte_order == LITTLE_ENDIAN) | |
7541 | { | |
7542 | for (i = prec - 1; i >= 0; i--) | |
7543 | { | |
7544 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7545 | litP += 2; | |
7546 | } | |
7547 | } | |
7548 | else | |
7549 | { | |
7550 | for (i = 0; i < prec; i++) | |
7551 | { | |
7552 | md_number_to_chars (litP, (valueT) words[i], 2); | |
7553 | litP += 2; | |
7554 | } | |
7555 | } | |
7556 | ||
670a50eb | 7557 | return NULL; |
3d3c5039 ILT |
7558 | } |
7559 | ||
7560 | void | |
7561 | md_number_to_chars (buf, val, n) | |
7562 | char *buf; | |
918692a5 | 7563 | valueT val; |
3d3c5039 ILT |
7564 | int n; |
7565 | { | |
670a50eb ILT |
7566 | switch (byte_order) |
7567 | { | |
3d3c5039 | 7568 | case LITTLE_ENDIAN: |
13fe1379 ILT |
7569 | number_to_chars_littleendian (buf, val, n); |
7570 | break; | |
3d3c5039 ILT |
7571 | |
7572 | case BIG_ENDIAN: | |
13fe1379 ILT |
7573 | number_to_chars_bigendian (buf, val, n); |
7574 | break; | |
3d3c5039 ILT |
7575 | |
7576 | default: | |
670a50eb | 7577 | internalError (); |
3d3c5039 ILT |
7578 | } |
7579 | } | |
f3d817d8 | 7580 | \f |
e8d4d475 | 7581 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 7582 | |
f3d817d8 DM |
7583 | struct option md_longopts[] = { |
7584 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
7585 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
7586 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
7587 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
7588 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
7589 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
7590 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
7591 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
7592 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
7593 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 7594 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 7595 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 7596 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 7597 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
7598 | {"trap", no_argument, NULL, OPTION_TRAP}, |
7599 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 7600 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
7601 | {"break", no_argument, NULL, OPTION_BREAK}, |
7602 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 7603 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 7604 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 7605 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 7606 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 7607 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 7608 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 7609 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 7610 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
7611 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
7612 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
7613 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
7614 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
7615 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
7616 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
7617 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
7618 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 7619 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 7620 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 7621 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 7622 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f3d817d8 | 7623 | |
d8a1c247 | 7624 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 7625 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 7626 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
7627 | #define OPTION_32 (OPTION_MD_BASE + 20) |
7628 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 7629 | #ifdef OBJ_ELF |
f3d817d8 | 7630 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 7631 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 7632 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 7633 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
7634 | {"32", no_argument, NULL, OPTION_32}, |
7635 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
7636 | #endif |
7637 | ||
7638 | {NULL, no_argument, NULL, 0} | |
7639 | }; | |
7640 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
7641 | |
7642 | int | |
f3d817d8 DM |
7643 | md_parse_option (c, arg) |
7644 | int c; | |
7645 | char *arg; | |
3d3c5039 | 7646 | { |
f3d817d8 | 7647 | switch (c) |
670a50eb | 7648 | { |
f3d817d8 DM |
7649 | case OPTION_TRAP: |
7650 | mips_trap = 1; | |
7651 | break; | |
670a50eb | 7652 | |
f3d817d8 DM |
7653 | case OPTION_BREAK: |
7654 | mips_trap = 0; | |
7655 | break; | |
7656 | ||
e8d4d475 | 7657 | case OPTION_EB: |
1dc1e798 | 7658 | target_big_endian = 1; |
e8d4d475 | 7659 | break; |
04cb3372 | 7660 | |
e8d4d475 | 7661 | case OPTION_EL: |
1dc1e798 | 7662 | target_big_endian = 0; |
f3d817d8 | 7663 | break; |
670a50eb | 7664 | |
f3d817d8 DM |
7665 | case 'O': |
7666 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
7667 | mips_optimize = 1; |
7668 | else | |
7669 | mips_optimize = 2; | |
f3d817d8 | 7670 | break; |
0aa07269 | 7671 | |
f3d817d8 | 7672 | case 'g': |
22ba90ce ILT |
7673 | if (arg == NULL) |
7674 | mips_debug = 2; | |
7675 | else | |
7676 | mips_debug = atoi (arg); | |
7677 | /* When the MIPS assembler sees -g or -g2, it does not do | |
7678 | optimizations which limit full symbolic debugging. We take | |
7679 | that to be equivalent to -O0. */ | |
7680 | if (mips_debug == 2) | |
0aa07269 | 7681 | mips_optimize = 0; |
f3d817d8 | 7682 | break; |
4e95866e | 7683 | |
f3d817d8 DM |
7684 | case OPTION_MIPS1: |
7685 | mips_isa = 1; | |
4bb0cc41 ILT |
7686 | if (mips_cpu == -1) |
7687 | mips_cpu = 3000; | |
f3d817d8 | 7688 | break; |
8358c818 | 7689 | |
f3d817d8 DM |
7690 | case OPTION_MIPS2: |
7691 | mips_isa = 2; | |
4bb0cc41 ILT |
7692 | if (mips_cpu == -1) |
7693 | mips_cpu = 6000; | |
f3d817d8 | 7694 | break; |
8358c818 | 7695 | |
f3d817d8 DM |
7696 | case OPTION_MIPS3: |
7697 | mips_isa = 3; | |
4bb0cc41 ILT |
7698 | if (mips_cpu == -1) |
7699 | mips_cpu = 4000; | |
f3d817d8 | 7700 | break; |
8358c818 | 7701 | |
d8a1c247 KR |
7702 | case OPTION_MIPS4: |
7703 | mips_isa = 4; | |
7704 | if (mips_cpu == -1) | |
7705 | mips_cpu = 8000; | |
7706 | break; | |
7707 | ||
f3d817d8 DM |
7708 | case OPTION_MCPU: |
7709 | { | |
7710 | char *p; | |
7711 | ||
7712 | /* Identify the processor type */ | |
7713 | p = arg; | |
7714 | if (strcmp (p, "default") == 0 | |
7715 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 7716 | mips_cpu = -1; |
f3d817d8 DM |
7717 | else |
7718 | { | |
c625fc23 JSC |
7719 | int sv = 0; |
7720 | ||
7721 | /* We need to cope with the various "vr" prefixes for the 4300 | |
7722 | processor. */ | |
7723 | if (*p == 'v' || *p == 'V') | |
7724 | { | |
7725 | sv = 1; | |
7726 | p++; | |
7727 | } | |
7728 | ||
f3d817d8 DM |
7729 | if (*p == 'r' || *p == 'R') |
7730 | p++; | |
8358c818 | 7731 | |
4bb0cc41 | 7732 | mips_cpu = -1; |
f3d817d8 DM |
7733 | switch (*p) |
7734 | { | |
d8a1c247 KR |
7735 | case '1': |
7736 | if (strcmp (p, "10000") == 0 | |
7737 | || strcmp (p, "10k") == 0 | |
7738 | || strcmp (p, "10K") == 0) | |
7739 | mips_cpu = 10000; | |
7740 | break; | |
7741 | ||
f3d817d8 DM |
7742 | case '2': |
7743 | if (strcmp (p, "2000") == 0 | |
7744 | || strcmp (p, "2k") == 0 | |
7745 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 7746 | mips_cpu = 2000; |
f3d817d8 | 7747 | break; |
8358c818 | 7748 | |
f3d817d8 DM |
7749 | case '3': |
7750 | if (strcmp (p, "3000") == 0 | |
7751 | || strcmp (p, "3k") == 0 | |
7752 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 7753 | mips_cpu = 3000; |
f3d817d8 | 7754 | break; |
8358c818 | 7755 | |
f3d817d8 DM |
7756 | case '4': |
7757 | if (strcmp (p, "4000") == 0 | |
7758 | || strcmp (p, "4k") == 0 | |
8c63448a | 7759 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 7760 | mips_cpu = 4000; |
c625fc23 JSC |
7761 | else if (strcmp (p, "4100") == 0) |
7762 | { | |
7763 | mips_cpu = 4100; | |
7764 | if (mips_4100 < 0) | |
7765 | mips_4100 = 1; | |
7766 | } | |
7767 | else if (strcmp (p, "4300") == 0) | |
7768 | mips_cpu = 4300; | |
8c63448a | 7769 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 7770 | mips_cpu = 4400; |
8c63448a | 7771 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 7772 | mips_cpu = 4600; |
b2b8c24e ILT |
7773 | else if (strcmp (p, "4650") == 0) |
7774 | { | |
7775 | mips_cpu = 4650; | |
7776 | if (mips_4650 < 0) | |
7777 | mips_4650 = 1; | |
7778 | } | |
e532b44c ILT |
7779 | else if (strcmp (p, "4010") == 0) |
7780 | { | |
7781 | mips_cpu = 4010; | |
7782 | if (mips_4010 < 0) | |
7783 | mips_4010 = 1; | |
7784 | } | |
f3d817d8 | 7785 | break; |
8358c818 | 7786 | |
517078c1 ILT |
7787 | case '5': |
7788 | if (strcmp (p, "5000") == 0 | |
7789 | || strcmp (p, "5k") == 0 | |
7790 | || strcmp (p, "5K") == 0) | |
7791 | mips_cpu = 5000; | |
7792 | break; | |
7793 | ||
f3d817d8 DM |
7794 | case '6': |
7795 | if (strcmp (p, "6000") == 0 | |
7796 | || strcmp (p, "6k") == 0 | |
7797 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 7798 | mips_cpu = 6000; |
f3d817d8 | 7799 | break; |
55933a58 | 7800 | |
d8a1c247 KR |
7801 | case '8': |
7802 | if (strcmp (p, "8000") == 0 | |
7803 | || strcmp (p, "8k") == 0 | |
7804 | || strcmp (p, "8K") == 0) | |
7805 | mips_cpu = 8000; | |
7806 | break; | |
7807 | ||
55933a58 ILT |
7808 | case 'o': |
7809 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 7810 | mips_cpu = 4600; |
55933a58 | 7811 | break; |
f3d817d8 | 7812 | } |
8358c818 | 7813 | |
517078c1 | 7814 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
7815 | { |
7816 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
7817 | return 0; | |
7818 | } | |
7819 | ||
4bb0cc41 | 7820 | if (mips_cpu == -1) |
f3d817d8 DM |
7821 | { |
7822 | as_bad ("invalid architecture -mcpu=%s", arg); | |
7823 | return 0; | |
7824 | } | |
7825 | } | |
7826 | } | |
7827 | break; | |
8358c818 | 7828 | |
b2b8c24e ILT |
7829 | case OPTION_M4650: |
7830 | mips_4650 = 1; | |
7831 | break; | |
7832 | ||
7833 | case OPTION_NO_M4650: | |
7834 | mips_4650 = 0; | |
7835 | break; | |
7836 | ||
e532b44c ILT |
7837 | case OPTION_M4010: |
7838 | mips_4010 = 1; | |
7839 | break; | |
7840 | ||
7841 | case OPTION_NO_M4010: | |
7842 | mips_4010 = 0; | |
7843 | break; | |
7844 | ||
c625fc23 JSC |
7845 | case OPTION_M4100: |
7846 | mips_4100 = 1; | |
7847 | break; | |
7848 | ||
7849 | case OPTION_NO_M4100: | |
7850 | mips_4100 = 0; | |
7851 | break; | |
7852 | ||
cc5703cd ILT |
7853 | case OPTION_MIPS16: |
7854 | mips16 = 1; | |
7855 | mips_no_prev_insn (); | |
7856 | break; | |
7857 | ||
7858 | case OPTION_NO_MIPS16: | |
7859 | mips16 = 0; | |
7860 | mips_no_prev_insn (); | |
7861 | break; | |
7862 | ||
f3d817d8 | 7863 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 7864 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 7865 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
7866 | { |
7867 | as_bad ("-G may not be used with embedded PIC code"); | |
7868 | return 0; | |
7869 | } | |
5b63f465 | 7870 | g_switch_value = 0x7fffffff; |
f3d817d8 | 7871 | break; |
d9aba805 | 7872 | |
fb251650 ILT |
7873 | /* When generating ELF code, we permit -KPIC and -call_shared to |
7874 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
7875 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 7876 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
7877 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
7878 | { | |
7879 | as_bad ("-call_shared is supported only for ELF format"); | |
7880 | return 0; | |
7881 | } | |
d9aba805 ILT |
7882 | mips_pic = SVR4_PIC; |
7883 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
7884 | { |
7885 | as_bad ("-G may not be used with SVR4 PIC code"); | |
7886 | return 0; | |
7887 | } | |
d9aba805 | 7888 | g_switch_value = 0; |
f3d817d8 DM |
7889 | break; |
7890 | ||
7891 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
7892 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
7893 | { | |
7894 | as_bad ("-non_shared is supported only for ELF format"); | |
7895 | return 0; | |
7896 | } | |
d9aba805 | 7897 | mips_pic = NO_PIC; |
f3d817d8 | 7898 | break; |
8358c818 | 7899 | |
fb251650 ILT |
7900 | /* The -xgot option tells the assembler to use 32 offsets when |
7901 | accessing the got in SVR4_PIC mode. It is for Irix | |
7902 | compatibility. */ | |
7903 | case OPTION_XGOT: | |
7904 | mips_big_got = 1; | |
7905 | break; | |
7906 | ||
f3d817d8 | 7907 | case 'G': |
1dc1e798 KR |
7908 | if (! USE_GLOBAL_POINTER_OPT) |
7909 | { | |
7910 | as_bad ("-G is not supported for this configuration"); | |
7911 | return 0; | |
7912 | } | |
7913 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 7914 | { |
f3d817d8 DM |
7915 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
7916 | return 0; | |
670a50eb ILT |
7917 | } |
7918 | else | |
f3d817d8 | 7919 | g_switch_value = atoi (arg); |
42562568 | 7920 | g_switch_seen = 1; |
f3d817d8 | 7921 | break; |
4e95866e | 7922 | |
7f9880e5 ILT |
7923 | /* The -32 and -64 options tell the assembler to output the 32 |
7924 | bit or the 64 bit MIPS ELF format. */ | |
7925 | case OPTION_32: | |
7926 | mips_64 = 0; | |
7927 | break; | |
7928 | ||
7929 | case OPTION_64: | |
9c44af60 ILT |
7930 | { |
7931 | const char **list, **l; | |
7932 | ||
7933 | list = bfd_target_list (); | |
7934 | for (l = list; *l != NULL; l++) | |
7935 | if (strcmp (*l, "elf64-bigmips") == 0 | |
7936 | || strcmp (*l, "elf64-littlemips") == 0) | |
7937 | break; | |
7938 | if (*l == NULL) | |
7939 | as_fatal ("No compiled in support for 64 bit object file format"); | |
7940 | free (list); | |
7941 | mips_64 = 1; | |
7942 | } | |
7f9880e5 ILT |
7943 | break; |
7944 | ||
f3d817d8 DM |
7945 | default: |
7946 | return 0; | |
8ea7f4e8 ILT |
7947 | } |
7948 | ||
f3d817d8 | 7949 | return 1; |
8ea7f4e8 ILT |
7950 | } |
7951 | ||
f3d817d8 DM |
7952 | void |
7953 | md_show_usage (stream) | |
7954 | FILE *stream; | |
7955 | { | |
7956 | fprintf(stream, "\ | |
7957 | MIPS options:\n\ | |
7958 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
7959 | -EB generate big endian output\n\ |
7960 | -EL generate little endian output\n\ | |
7961 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
7962 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
7963 | implicitly with the gp register [default 8]\n"); |
7964 | fprintf(stream, "\ | |
f3d817d8 DM |
7965 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
7966 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
7967 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 7968 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 7969 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 7970 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
7971 | -m4650 permit R4650 instructions\n\ |
7972 | -no-m4650 do not permit R4650 instructions\n\ | |
7973 | -m4010 permit R4010 instructions\n\ | |
7974 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
7975 | -m4100 permit VR4100 instructions\n\ |
7976 | -no-m4100 do not permit VR4100 instructions\n"); | |
7977 | fprintf(stream, "\ | |
cc5703cd ILT |
7978 | -mips16 generate mips16 instructions\n\ |
7979 | -no-mips16 do not generate mips16 instructions\n"); | |
7980 | fprintf(stream, "\ | |
f3d817d8 DM |
7981 | -O0 remove unneeded NOPs, do not swap branches\n\ |
7982 | -O remove unneeded NOPs and swap branches\n\ | |
7983 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
7984 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
7985 | #ifdef OBJ_ELF | |
7986 | fprintf(stream, "\ | |
7987 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 7988 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
7989 | -xgot assume a 32 bit GOT\n\ |
7990 | -32 create 32 bit object file (default)\n\ | |
7991 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
7992 | #endif |
7993 | } | |
22ba90ce ILT |
7994 | |
7995 | void | |
7996 | mips_init_after_args () | |
7997 | { | |
7998 | if (target_big_endian) | |
7999 | byte_order = BIG_ENDIAN; | |
8000 | else | |
8001 | byte_order = LITTLE_ENDIAN; | |
8002 | } | |
f3d817d8 | 8003 | \f |
3d3c5039 ILT |
8004 | long |
8005 | md_pcrel_from (fixP) | |
8006 | fixS *fixP; | |
8007 | { | |
1dc1e798 KR |
8008 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8009 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8010 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8011 | { | |
8012 | /* This makes a branch to an undefined symbol be a branch to the | |
8013 | current location. */ | |
8014 | return 4; | |
8015 | } | |
5b63f465 | 8016 | |
670a50eb ILT |
8017 | /* return the address of the delay slot */ |
8018 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8019 | } |
8020 | ||
abdad6bc ILT |
8021 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8022 | reloc for a cons. We could use the definition there, except that | |
8023 | we want to handle 64 bit relocs specially. */ | |
8024 | ||
8025 | void | |
8026 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8027 | fragS *frag; | |
8028 | int where; | |
8029 | unsigned int nbytes; | |
8030 | expressionS *exp; | |
8031 | { | |
bf39474f | 8032 | #ifndef OBJ_ELF |
abdad6bc | 8033 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8034 | 4 byte reloc. */ |
8035 | if (nbytes == 8 && ! mips_64) | |
abdad6bc ILT |
8036 | { |
8037 | if (byte_order == BIG_ENDIAN) | |
8038 | where += 4; | |
8039 | nbytes = 4; | |
8040 | } | |
bf39474f | 8041 | #endif |
abdad6bc | 8042 | |
7f9880e5 | 8043 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8044 | as_bad ("Unsupported reloc size %d", nbytes); |
8045 | ||
8046 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8047 | (nbytes == 2 |
8048 | ? BFD_RELOC_16 | |
8049 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8050 | } |
8051 | ||
867a58b3 ILT |
8052 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8053 | the corresponding LO reloc. This is called before md_apply_fix and | |
8054 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8055 | explicit use of the %hi modifier. */ | |
8056 | ||
8057 | void | |
8058 | mips_frob_file () | |
8059 | { | |
8060 | struct mips_hi_fixup *l; | |
8061 | ||
8062 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8063 | { | |
8064 | segment_info_type *seginfo; | |
9b61d62b | 8065 | int pass; |
867a58b3 ILT |
8066 | |
8067 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8068 | ||
8069 | /* Check quickly whether the next fixup happens to be a matching | |
8070 | %lo. */ | |
8071 | if (l->fixp->fx_next != NULL | |
8072 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8073 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8074 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8075 | continue; | |
8076 | ||
8077 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8078 | When we find one, move the %hi just in front of it. We do |
8079 | this in two passes. In the first pass, we try to find a | |
8080 | unique %lo. In the second pass, we permit multiple %hi | |
8081 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8082 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8083 | for (pass = 0; pass < 2; pass++) |
8084 | { | |
8085 | fixS *f, *prev; | |
8086 | ||
8087 | prev = NULL; | |
8088 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8089 | { |
9b61d62b ILT |
8090 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8091 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8092 | && f->fx_addsy == l->fixp->fx_addsy | |
8093 | && f->fx_offset == l->fixp->fx_offset | |
8094 | && (pass == 1 | |
8095 | || prev == NULL | |
8096 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8097 | || prev->fx_addsy != f->fx_addsy | |
8098 | || prev->fx_offset != f->fx_offset)) | |
8099 | { | |
8100 | fixS **pf; | |
867a58b3 | 8101 | |
9b61d62b ILT |
8102 | /* Move l->fixp before f. */ |
8103 | for (pf = &seginfo->fix_root; | |
8104 | *pf != l->fixp; | |
8105 | pf = &(*pf)->fx_next) | |
8106 | assert (*pf != NULL); | |
867a58b3 | 8107 | |
9b61d62b | 8108 | *pf = l->fixp->fx_next; |
867a58b3 | 8109 | |
9b61d62b ILT |
8110 | l->fixp->fx_next = f; |
8111 | if (prev == NULL) | |
8112 | seginfo->fix_root = l->fixp; | |
8113 | else | |
8114 | prev->fx_next = l->fixp; | |
867a58b3 | 8115 | |
9b61d62b ILT |
8116 | break; |
8117 | } | |
8118 | ||
8119 | prev = f; | |
867a58b3 ILT |
8120 | } |
8121 | ||
9b61d62b ILT |
8122 | if (f != NULL) |
8123 | break; | |
867a58b3 | 8124 | |
9b61d62b ILT |
8125 | if (pass == 1) |
8126 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8127 | "Unmatched %%hi reloc"); | |
8128 | } | |
867a58b3 ILT |
8129 | } |
8130 | } | |
8131 | ||
1c803e52 ILT |
8132 | /* When generating embedded PIC code we need to use a special |
8133 | relocation to represent the difference of two symbols in the .text | |
8134 | section (switch tables use a difference of this sort). See | |
8135 | include/coff/mips.h for details. This macro checks whether this | |
8136 | fixup requires the special reloc. */ | |
8137 | #define SWITCH_TABLE(fixp) \ | |
8138 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8139 | && (fixp)->fx_addsy != NULL \ | |
8140 | && (fixp)->fx_subsy != NULL \ | |
8141 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8142 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8143 | ||
5b63f465 | 8144 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8145 | relocations, in case the linker has to relax a call. We also need |
8146 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8147 | |
8148 | /*ARGSUSED*/ | |
8149 | int | |
8150 | mips_force_relocation (fixp) | |
8151 | fixS *fixp; | |
8152 | { | |
1c803e52 | 8153 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8154 | && (fixp->fx_pcrel |
8155 | || SWITCH_TABLE (fixp) | |
8156 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8157 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8158 | } |
8159 | ||
8160 | /* Apply a fixup to the object file. */ | |
8161 | ||
3d3c5039 ILT |
8162 | int |
8163 | md_apply_fix (fixP, valueP) | |
8164 | fixS *fixP; | |
918692a5 | 8165 | valueT *valueP; |
3d3c5039 | 8166 | { |
670a50eb ILT |
8167 | unsigned char *buf; |
8168 | long insn, value; | |
3d3c5039 | 8169 | |
bf39474f ILT |
8170 | assert (fixP->fx_size == 4 |
8171 | || fixP->fx_r_type == BFD_RELOC_16 | |
8172 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8173 | |
670a50eb ILT |
8174 | value = *valueP; |
8175 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 8176 | |
5b63f465 ILT |
8177 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8178 | fixP->fx_done = 1; | |
8179 | ||
670a50eb ILT |
8180 | switch (fixP->fx_r_type) |
8181 | { | |
3d3c5039 ILT |
8182 | case BFD_RELOC_MIPS_JMP: |
8183 | case BFD_RELOC_HI16: | |
8184 | case BFD_RELOC_HI16_S: | |
670a50eb | 8185 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8186 | case BFD_RELOC_MIPS_LITERAL: |
8187 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8188 | case BFD_RELOC_MIPS_GOT16: |
8189 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8190 | case BFD_RELOC_MIPS_GOT_HI16: |
8191 | case BFD_RELOC_MIPS_GOT_LO16: | |
8192 | case BFD_RELOC_MIPS_CALL_HI16: | |
8193 | case BFD_RELOC_MIPS_CALL_LO16: | |
ecd4ca1c | 8194 | if (fixP->fx_pcrel) |
7b777690 ILT |
8195 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8196 | "Invalid PC relative reloc"); | |
670a50eb | 8197 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8198 | break; |
3d3c5039 | 8199 | |
cc5703cd ILT |
8200 | case BFD_RELOC_MIPS16_JMP: |
8201 | /* We currently always generate a reloc against a symbol, which | |
8202 | means that we don't want an addend even if the symbol is | |
8203 | defined. */ | |
8204 | fixP->fx_addnumber = 0; | |
8205 | break; | |
8206 | ||
ecd4ca1c ILT |
8207 | case BFD_RELOC_PCREL_HI16_S: |
8208 | /* The addend for this is tricky if it is internal, so we just | |
8209 | do everything here rather than in bfd_perform_relocation. */ | |
8210 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8211 | { | |
8212 | /* For an external symbol adjust by the address to make it | |
8213 | pcrel_offset. We use the address of the RELLO reloc | |
8214 | which follows this one. */ | |
8215 | value += (fixP->fx_next->fx_frag->fr_address | |
8216 | + fixP->fx_next->fx_where); | |
8217 | } | |
8218 | if (value & 0x8000) | |
8219 | value += 0x10000; | |
8220 | value >>= 16; | |
0221ddf7 | 8221 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
8222 | if (byte_order == BIG_ENDIAN) |
8223 | buf += 2; | |
8224 | md_number_to_chars (buf, value, 2); | |
8225 | break; | |
8226 | ||
8227 | case BFD_RELOC_PCREL_LO16: | |
8228 | /* The addend for this is tricky if it is internal, so we just | |
8229 | do everything here rather than in bfd_perform_relocation. */ | |
8230 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
8231 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 8232 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
8233 | if (byte_order == BIG_ENDIAN) |
8234 | buf += 2; | |
8235 | md_number_to_chars (buf, value, 2); | |
8236 | break; | |
8237 | ||
bf39474f ILT |
8238 | case BFD_RELOC_64: |
8239 | /* This is handled like BFD_RELOC_32, but we output a sign | |
8240 | extended value if we are only 32 bits. */ | |
8241 | if (fixP->fx_done | |
8242 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
8243 | { | |
8244 | if (8 <= sizeof (valueT)) | |
8245 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8246 | value, 8); | |
8247 | else | |
8248 | { | |
8249 | long w1, w2; | |
8250 | long hiv; | |
8251 | ||
8252 | w1 = w2 = fixP->fx_where; | |
8253 | if (byte_order == BIG_ENDIAN) | |
8254 | w1 += 4; | |
8255 | else | |
8256 | w2 += 4; | |
8257 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
8258 | if ((value & 0x80000000) != 0) | |
8259 | hiv = 0xffffffff; | |
8260 | else | |
8261 | hiv = 0; | |
8262 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
8263 | } | |
8264 | } | |
8265 | break; | |
8266 | ||
f3645945 ILT |
8267 | case BFD_RELOC_32: |
8268 | /* If we are deleting this reloc entry, we must fill in the | |
8269 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
8270 | resolved when it appears but is later defined. We also need |
8271 | to fill in the value if this is an embedded PIC switch table | |
8272 | entry. */ | |
8273 | if (fixP->fx_done | |
8274 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
8275 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
8276 | value, 4); | |
8277 | break; | |
8278 | ||
49ad0c4c ILT |
8279 | case BFD_RELOC_16: |
8280 | /* If we are deleting this reloc entry, we must fill in the | |
8281 | value now. */ | |
8282 | assert (fixP->fx_size == 2); | |
8283 | if (fixP->fx_done) | |
8284 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
8285 | value, 2); | |
8286 | break; | |
8287 | ||
f3645945 ILT |
8288 | case BFD_RELOC_LO16: |
8289 | /* When handling an embedded PIC switch statement, we can wind | |
8290 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
8291 | if (fixP->fx_done) | |
8292 | { | |
8293 | if (value < -0x8000 || value > 0x7fff) | |
8294 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8295 | "relocation overflow"); | |
0221ddf7 | 8296 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
f3645945 ILT |
8297 | if (byte_order == BIG_ENDIAN) |
8298 | buf += 2; | |
8299 | md_number_to_chars (buf, value, 2); | |
8300 | } | |
8301 | break; | |
8302 | ||
3d3c5039 | 8303 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
8304 | /* |
8305 | * We need to save the bits in the instruction since fixup_segment() | |
8306 | * might be deleting the relocation entry (i.e., a branch within | |
8307 | * the current segment). | |
8308 | */ | |
fbcfacb7 | 8309 | if ((value & 0x3) != 0) |
7b777690 ILT |
8310 | as_warn_where (fixP->fx_file, fixP->fx_line, |
8311 | "Branch to odd address (%lx)", value); | |
670a50eb | 8312 | value >>= 2; |
670a50eb ILT |
8313 | |
8314 | /* update old instruction data */ | |
8315 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
8316 | switch (byte_order) | |
8317 | { | |
3d3c5039 | 8318 | case LITTLE_ENDIAN: |
670a50eb ILT |
8319 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
8320 | break; | |
3d3c5039 ILT |
8321 | |
8322 | case BIG_ENDIAN: | |
670a50eb ILT |
8323 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
8324 | break; | |
3d3c5039 ILT |
8325 | |
8326 | default: | |
670a50eb ILT |
8327 | internalError (); |
8328 | return 0; | |
3d3c5039 | 8329 | } |
9da4c5d1 ILT |
8330 | |
8331 | if (value >= -0x8000 && value < 0x8000) | |
8332 | insn |= value & 0xffff; | |
8333 | else | |
8334 | { | |
8335 | /* The branch offset is too large. If this is an | |
8336 | unconditional branch, and we are not generating PIC code, | |
8337 | we can convert it to an absolute jump instruction. */ | |
8338 | if (mips_pic == NO_PIC | |
8339 | && fixP->fx_done | |
8340 | && fixP->fx_frag->fr_address >= text_section->vma | |
8341 | && (fixP->fx_frag->fr_address | |
8342 | < text_section->vma + text_section->_raw_size) | |
8343 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
8344 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
8345 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
8346 | { | |
8347 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
8348 | insn = 0x0c000000; /* jal */ | |
8349 | else | |
8350 | insn = 0x08000000; /* j */ | |
8351 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
8352 | fixP->fx_done = 0; | |
8353 | fixP->fx_addsy = section_symbol (text_section); | |
8354 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
8355 | } | |
8356 | else | |
8357 | { | |
8358 | /* FIXME. It would be possible in principle to handle | |
8359 | conditional branches which overflow. They could be | |
8360 | transformed into a branch around a jump. This would | |
8361 | require setting up variant frags for each different | |
8362 | branch type. The native MIPS assembler attempts to | |
8363 | handle these cases, but it appears to do it | |
8364 | incorrectly. */ | |
8365 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
8366 | "Relocation overflow"); | |
8367 | } | |
8368 | } | |
8369 | ||
604633ae | 8370 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 8371 | break; |
3d3c5039 ILT |
8372 | |
8373 | default: | |
670a50eb | 8374 | internalError (); |
3d3c5039 | 8375 | } |
5b63f465 | 8376 | |
670a50eb | 8377 | return 1; |
3d3c5039 ILT |
8378 | } |
8379 | ||
8380 | #if 0 | |
8381 | void | |
670a50eb ILT |
8382 | printInsn (oc) |
8383 | unsigned long oc; | |
3d3c5039 | 8384 | { |
670a50eb ILT |
8385 | const struct mips_opcode *p; |
8386 | int treg, sreg, dreg, shamt; | |
8387 | short imm; | |
8388 | const char *args; | |
8389 | int i; | |
3d3c5039 | 8390 | |
670a50eb ILT |
8391 | for (i = 0; i < NUMOPCODES; ++i) |
8392 | { | |
8393 | p = &mips_opcodes[i]; | |
8394 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
8395 | { | |
8396 | printf ("%08lx %s\t", oc, p->name); | |
8397 | treg = (oc >> 16) & 0x1f; | |
8398 | sreg = (oc >> 21) & 0x1f; | |
8399 | dreg = (oc >> 11) & 0x1f; | |
8400 | shamt = (oc >> 6) & 0x1f; | |
8401 | imm = oc; | |
8402 | for (args = p->args;; ++args) | |
8403 | { | |
8404 | switch (*args) | |
8405 | { | |
3d3c5039 | 8406 | case '\0': |
670a50eb ILT |
8407 | printf ("\n"); |
8408 | break; | |
3d3c5039 ILT |
8409 | |
8410 | case ',': | |
8411 | case '(': | |
8412 | case ')': | |
670a50eb ILT |
8413 | printf ("%c", *args); |
8414 | continue; | |
3d3c5039 ILT |
8415 | |
8416 | case 'r': | |
670a50eb ILT |
8417 | assert (treg == sreg); |
8418 | printf ("$%d,$%d", treg, sreg); | |
8419 | continue; | |
3d3c5039 ILT |
8420 | |
8421 | case 'd': | |
918692a5 | 8422 | case 'G': |
670a50eb ILT |
8423 | printf ("$%d", dreg); |
8424 | continue; | |
3d3c5039 ILT |
8425 | |
8426 | case 't': | |
918692a5 | 8427 | case 'E': |
670a50eb ILT |
8428 | printf ("$%d", treg); |
8429 | continue; | |
3d3c5039 | 8430 | |
9226253a ILT |
8431 | case 'k': |
8432 | printf ("0x%x", treg); | |
8433 | continue; | |
8434 | ||
3d3c5039 ILT |
8435 | case 'b': |
8436 | case 's': | |
670a50eb ILT |
8437 | printf ("$%d", sreg); |
8438 | continue; | |
3d3c5039 ILT |
8439 | |
8440 | case 'a': | |
670a50eb ILT |
8441 | printf ("0x%08lx", oc & 0x1ffffff); |
8442 | continue; | |
3d3c5039 ILT |
8443 | |
8444 | case 'i': | |
8445 | case 'j': | |
8446 | case 'o': | |
8447 | case 'u': | |
670a50eb ILT |
8448 | printf ("%d", imm); |
8449 | continue; | |
3d3c5039 ILT |
8450 | |
8451 | case '<': | |
56c96faa | 8452 | case '>': |
670a50eb ILT |
8453 | printf ("$%d", shamt); |
8454 | continue; | |
3d3c5039 ILT |
8455 | |
8456 | default: | |
670a50eb | 8457 | internalError (); |
3d3c5039 | 8458 | } |
670a50eb | 8459 | break; |
3d3c5039 | 8460 | } |
670a50eb | 8461 | return; |
3d3c5039 ILT |
8462 | } |
8463 | } | |
670a50eb | 8464 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
8465 | } |
8466 | #endif | |
8467 | ||
8468 | static symbolS * | |
8469 | get_symbol () | |
8470 | { | |
670a50eb ILT |
8471 | int c; |
8472 | char *name; | |
8473 | symbolS *p; | |
8474 | ||
8475 | name = input_line_pointer; | |
8476 | c = get_symbol_end (); | |
8477 | p = (symbolS *) symbol_find_or_make (name); | |
8478 | *input_line_pointer = c; | |
8479 | return p; | |
3d3c5039 ILT |
8480 | } |
8481 | ||
becfe05e ILT |
8482 | /* Align the current frag to a given power of two. The MIPS assembler |
8483 | also automatically adjusts any preceding label. */ | |
8484 | ||
8485 | static void | |
23dc1ae3 | 8486 | mips_align (to, fill, label) |
becfe05e ILT |
8487 | int to; |
8488 | int fill; | |
23dc1ae3 | 8489 | symbolS *label; |
becfe05e | 8490 | { |
fbcfacb7 | 8491 | mips_emit_delays (false); |
becfe05e ILT |
8492 | frag_align (to, fill); |
8493 | record_alignment (now_seg, to); | |
23dc1ae3 | 8494 | if (label != NULL) |
becfe05e | 8495 | { |
23dc1ae3 ILT |
8496 | assert (S_GET_SEGMENT (label) == now_seg); |
8497 | label->sy_frag = frag_now; | |
8498 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
8499 | } |
8500 | } | |
8501 | ||
8502 | /* Align to a given power of two. .align 0 turns off the automatic | |
8503 | alignment used by the data creating pseudo-ops. */ | |
8504 | ||
3d3c5039 ILT |
8505 | static void |
8506 | s_align (x) | |
8507 | int x; | |
8508 | { | |
670a50eb ILT |
8509 | register int temp; |
8510 | register long temp_fill; | |
8511 | long max_alignment = 15; | |
3d3c5039 | 8512 | |
670a50eb | 8513 | /* |
3d3c5039 ILT |
8514 | |
8515 | o Note that the assembler pulls down any immediately preceeding label | |
8516 | to the aligned address. | |
8517 | o It's not documented but auto alignment is reinstated by | |
8518 | a .align pseudo instruction. | |
8519 | o Note also that after auto alignment is turned off the mips assembler | |
8520 | issues an error on attempt to assemble an improperly aligned data item. | |
8521 | We don't. | |
8522 | ||
8523 | */ | |
8524 | ||
670a50eb ILT |
8525 | temp = get_absolute_expression (); |
8526 | if (temp > max_alignment) | |
8527 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
8528 | else if (temp < 0) | |
8529 | { | |
8530 | as_warn ("Alignment negative: 0 assumed."); | |
8531 | temp = 0; | |
8532 | } | |
8533 | if (*input_line_pointer == ',') | |
8534 | { | |
8535 | input_line_pointer++; | |
8536 | temp_fill = get_absolute_expression (); | |
8537 | } | |
8538 | else | |
8539 | temp_fill = 0; | |
8540 | if (temp) | |
8541 | { | |
8542 | auto_align = 1; | |
fbcfacb7 ILT |
8543 | mips_align (temp, (int) temp_fill, |
8544 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 8545 | } |
670a50eb ILT |
8546 | else |
8547 | { | |
8548 | auto_align = 0; | |
3d3c5039 ILT |
8549 | } |
8550 | ||
670a50eb | 8551 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8552 | } |
8553 | ||
739708fa KR |
8554 | void |
8555 | mips_flush_pending_output () | |
becfe05e | 8556 | { |
fbcfacb7 ILT |
8557 | mips_emit_delays (false); |
8558 | mips_clear_insn_labels (); | |
becfe05e ILT |
8559 | } |
8560 | ||
3d3c5039 ILT |
8561 | static void |
8562 | s_change_sec (sec) | |
8563 | int sec; | |
8564 | { | |
88225433 | 8565 | segT seg; |
becfe05e | 8566 | |
5b63f465 ILT |
8567 | /* When generating embedded PIC code, we only use the .text, .lit8, |
8568 | .sdata and .sbss sections. We change the .data and .rdata | |
8569 | pseudo-ops to use .sdata. */ | |
8570 | if (mips_pic == EMBEDDED_PIC | |
8571 | && (sec == 'd' || sec == 'r')) | |
8572 | sec = 's'; | |
8573 | ||
fbcfacb7 | 8574 | mips_emit_delays (false); |
670a50eb ILT |
8575 | switch (sec) |
8576 | { | |
3d3c5039 | 8577 | case 't': |
604633ae | 8578 | s_text (0); |
670a50eb | 8579 | break; |
3d3c5039 | 8580 | case 'd': |
604633ae | 8581 | s_data (0); |
670a50eb | 8582 | break; |
3d3c5039 | 8583 | case 'b': |
670a50eb | 8584 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
8585 | demand_empty_rest_of_line (); |
8586 | break; | |
88225433 ILT |
8587 | |
8588 | case 'r': | |
1dc1e798 KR |
8589 | if (USE_GLOBAL_POINTER_OPT) |
8590 | { | |
8591 | seg = subseg_new (RDATA_SECTION_NAME, | |
8592 | (subsegT) get_absolute_expression ()); | |
8593 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8594 | { | |
8595 | bfd_set_section_flags (stdoutput, seg, | |
8596 | (SEC_ALLOC | |
8597 | | SEC_LOAD | |
8598 | | SEC_READONLY | |
8599 | | SEC_RELOC | |
8600 | | SEC_DATA)); | |
08e17202 ILT |
8601 | if (strcmp (TARGET_OS, "elf") != 0) |
8602 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8603 | } |
8604 | demand_empty_rest_of_line (); | |
8605 | } | |
8606 | else | |
8607 | { | |
8608 | as_bad ("No read only data section in this object file format"); | |
8609 | demand_empty_rest_of_line (); | |
8610 | return; | |
8611 | } | |
88225433 | 8612 | break; |
88225433 ILT |
8613 | |
8614 | case 's': | |
1dc1e798 KR |
8615 | if (USE_GLOBAL_POINTER_OPT) |
8616 | { | |
8617 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
8618 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8619 | { | |
8620 | bfd_set_section_flags (stdoutput, seg, | |
8621 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
8622 | | SEC_DATA); | |
08e17202 ILT |
8623 | if (strcmp (TARGET_OS, "elf") != 0) |
8624 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
8625 | } |
8626 | demand_empty_rest_of_line (); | |
8627 | break; | |
8628 | } | |
8629 | else | |
8630 | { | |
8631 | as_bad ("Global pointers not supported; recompile -G 0"); | |
8632 | demand_empty_rest_of_line (); | |
8633 | return; | |
8634 | } | |
3d3c5039 | 8635 | } |
88225433 | 8636 | |
670a50eb | 8637 | auto_align = 1; |
3d3c5039 ILT |
8638 | } |
8639 | ||
739708fa KR |
8640 | void |
8641 | mips_enable_auto_align () | |
9da4c5d1 | 8642 | { |
9da4c5d1 ILT |
8643 | auto_align = 1; |
8644 | } | |
8645 | ||
3d3c5039 ILT |
8646 | static void |
8647 | s_cons (log_size) | |
8648 | int log_size; | |
8649 | { | |
23dc1ae3 ILT |
8650 | symbolS *label; |
8651 | ||
fbcfacb7 ILT |
8652 | label = insn_labels != NULL ? insn_labels->label : NULL; |
8653 | mips_emit_delays (false); | |
670a50eb | 8654 | if (log_size > 0 && auto_align) |
23dc1ae3 | 8655 | mips_align (log_size, 0, label); |
fbcfacb7 | 8656 | mips_clear_insn_labels (); |
670a50eb | 8657 | cons (1 << log_size); |
3d3c5039 ILT |
8658 | } |
8659 | ||
3d3c5039 | 8660 | static void |
becfe05e ILT |
8661 | s_float_cons (type) |
8662 | int type; | |
3d3c5039 | 8663 | { |
23dc1ae3 ILT |
8664 | symbolS *label; |
8665 | ||
fbcfacb7 | 8666 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 8667 | |
fbcfacb7 | 8668 | mips_emit_delays (false); |
670a50eb ILT |
8669 | |
8670 | if (auto_align) | |
becfe05e | 8671 | if (type == 'd') |
23dc1ae3 | 8672 | mips_align (3, 0, label); |
670a50eb | 8673 | else |
23dc1ae3 | 8674 | mips_align (2, 0, label); |
670a50eb | 8675 | |
fbcfacb7 | 8676 | mips_clear_insn_labels (); |
1849d646 | 8677 | |
becfe05e | 8678 | float_cons (type); |
3d3c5039 ILT |
8679 | } |
8680 | ||
c1444ec4 ILT |
8681 | /* Handle .globl. We need to override it because on Irix 5 you are |
8682 | permitted to say | |
8683 | .globl foo .text | |
8684 | where foo is an undefined symbol, to mean that foo should be | |
8685 | considered to be the address of a function. */ | |
8686 | ||
8687 | static void | |
8688 | s_mips_globl (x) | |
8689 | int x; | |
8690 | { | |
8691 | char *name; | |
8692 | int c; | |
8693 | symbolS *symbolP; | |
fb251650 | 8694 | flagword flag; |
c1444ec4 ILT |
8695 | |
8696 | name = input_line_pointer; | |
8697 | c = get_symbol_end (); | |
8698 | symbolP = symbol_find_or_make (name); | |
8699 | *input_line_pointer = c; | |
8700 | SKIP_WHITESPACE (); | |
fb251650 ILT |
8701 | |
8702 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
8703 | being a function is apparently labelled as being an object. */ | |
8704 | flag = BSF_OBJECT; | |
8705 | ||
c1444ec4 ILT |
8706 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
8707 | { | |
8708 | char *secname; | |
8709 | asection *sec; | |
8710 | ||
8711 | secname = input_line_pointer; | |
8712 | c = get_symbol_end (); | |
8713 | sec = bfd_get_section_by_name (stdoutput, secname); | |
8714 | if (sec == NULL) | |
8715 | as_bad ("%s: no such section", secname); | |
8716 | *input_line_pointer = c; | |
8717 | ||
8718 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 8719 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
8720 | } |
8721 | ||
fb251650 ILT |
8722 | symbolP->bsym->flags |= flag; |
8723 | ||
c1444ec4 ILT |
8724 | S_SET_EXTERNAL (symbolP); |
8725 | demand_empty_rest_of_line (); | |
8726 | } | |
8727 | ||
3d3c5039 ILT |
8728 | static void |
8729 | s_option (x) | |
8730 | int x; | |
8731 | { | |
dd3f1f76 ILT |
8732 | char *opt; |
8733 | char c; | |
8734 | ||
8735 | opt = input_line_pointer; | |
8736 | c = get_symbol_end (); | |
8737 | ||
dd3f1f76 | 8738 | if (*opt == 'O') |
9226253a ILT |
8739 | { |
8740 | /* FIXME: What does this mean? */ | |
8741 | } | |
dd3f1f76 | 8742 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 8743 | { |
d9aba805 | 8744 | int i; |
42562568 | 8745 | |
d9aba805 ILT |
8746 | i = atoi (opt + 3); |
8747 | if (i == 0) | |
8748 | mips_pic = NO_PIC; | |
8749 | else if (i == 2) | |
8750 | mips_pic = SVR4_PIC; | |
8751 | else | |
8752 | as_bad (".option pic%d not supported", i); | |
8753 | ||
1dc1e798 | 8754 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
8755 | { |
8756 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 8757 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
8758 | g_switch_value = 0; |
8759 | bfd_set_gp_size (stdoutput, 0); | |
8760 | } | |
9226253a | 8761 | } |
dd3f1f76 ILT |
8762 | else |
8763 | as_warn ("Unrecognized option \"%s\"", opt); | |
8764 | ||
8765 | *input_line_pointer = c; | |
670a50eb | 8766 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
8767 | } |
8768 | ||
8769 | static void | |
8770 | s_mipsset (x) | |
8771 | int x; | |
8772 | { | |
670a50eb ILT |
8773 | char *name = input_line_pointer, ch; |
8774 | ||
8775 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
8776 | input_line_pointer++; | |
8777 | ch = *input_line_pointer; | |
8778 | *input_line_pointer = '\0'; | |
8779 | ||
8780 | if (strcmp (name, "reorder") == 0) | |
8781 | { | |
4e95866e ILT |
8782 | if (mips_noreorder) |
8783 | { | |
8784 | prev_insn_unreordered = 1; | |
8785 | prev_prev_insn_unreordered = 1; | |
8786 | } | |
670a50eb ILT |
8787 | mips_noreorder = 0; |
8788 | } | |
8789 | else if (strcmp (name, "noreorder") == 0) | |
8790 | { | |
fbcfacb7 | 8791 | mips_emit_delays (true); |
670a50eb | 8792 | mips_noreorder = 1; |
0dd2d296 | 8793 | mips_any_noreorder = 1; |
670a50eb ILT |
8794 | } |
8795 | else if (strcmp (name, "at") == 0) | |
8796 | { | |
8797 | mips_noat = 0; | |
8798 | } | |
8799 | else if (strcmp (name, "noat") == 0) | |
8800 | { | |
8801 | mips_noat = 1; | |
3d3c5039 | 8802 | } |
670a50eb ILT |
8803 | else if (strcmp (name, "macro") == 0) |
8804 | { | |
8805 | mips_warn_about_macros = 0; | |
8806 | } | |
8807 | else if (strcmp (name, "nomacro") == 0) | |
8808 | { | |
8809 | if (mips_noreorder == 0) | |
8810 | as_bad ("`noreorder' must be set before `nomacro'"); | |
8811 | mips_warn_about_macros = 1; | |
8812 | } | |
8813 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
8814 | { | |
8815 | mips_nomove = 0; | |
8816 | } | |
8817 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
8818 | { | |
8819 | mips_nomove = 1; | |
8820 | } | |
8821 | else if (strcmp (name, "bopt") == 0) | |
8822 | { | |
8823 | mips_nobopt = 0; | |
8824 | } | |
8825 | else if (strcmp (name, "nobopt") == 0) | |
8826 | { | |
8827 | mips_nobopt = 1; | |
8828 | } | |
943321c0 ILT |
8829 | else if (strcmp (name, "mips16") == 0 |
8830 | || strcmp (name, "MIPS-16") == 0) | |
8831 | mips16 = 1; | |
8832 | else if (strcmp (name, "nomips16") == 0 | |
8833 | || strcmp (name, "noMIPS-16") == 0) | |
8834 | mips16 = 0; | |
1051c97f ILT |
8835 | else if (strncmp (name, "mips", 4) == 0) |
8836 | { | |
8837 | int isa; | |
8838 | ||
8839 | /* Permit the user to change the ISA on the fly. Needless to | |
8840 | say, misuse can cause serious problems. */ | |
8841 | isa = atoi (name + 4); | |
8842 | if (isa == 0) | |
8843 | mips_isa = file_mips_isa; | |
d8a1c247 | 8844 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
8845 | as_bad ("unknown ISA level"); |
8846 | else | |
8847 | mips_isa = isa; | |
8848 | } | |
cc5703cd ILT |
8849 | else if (strcmp (name, "autoextend") == 0) |
8850 | mips16_autoextend = 1; | |
8851 | else if (strcmp (name, "noautoextend") == 0) | |
8852 | mips16_autoextend = 0; | |
670a50eb ILT |
8853 | else |
8854 | { | |
8855 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
8856 | } | |
8857 | *input_line_pointer = ch; | |
8858 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
8859 | } |
8860 | ||
9226253a ILT |
8861 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
8862 | .option pic2. It means to generate SVR4 PIC calls. */ | |
8863 | ||
8864 | static void | |
8865 | s_abicalls (ignore) | |
8866 | int ignore; | |
8867 | { | |
d9aba805 | 8868 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
8869 | if (USE_GLOBAL_POINTER_OPT) |
8870 | { | |
8871 | if (g_switch_seen && g_switch_value != 0) | |
8872 | as_warn ("-G may not be used with SVR4 PIC code"); | |
8873 | g_switch_value = 0; | |
8874 | } | |
d9aba805 | 8875 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
8876 | demand_empty_rest_of_line (); |
8877 | } | |
8878 | ||
8879 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
8880 | PIC code. It sets the $gp register for the function based on the | |
8881 | function address, which is in the register named in the argument. | |
8882 | This uses a relocation against _gp_disp, which is handled specially | |
8883 | by the linker. The result is: | |
8884 | lui $gp,%hi(_gp_disp) | |
8885 | addiu $gp,$gp,%lo(_gp_disp) | |
8886 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 8887 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
8888 | |
8889 | static void | |
8890 | s_cpload (ignore) | |
8891 | int ignore; | |
8892 | { | |
8893 | expressionS ex; | |
8894 | int icnt = 0; | |
8895 | ||
d9aba805 ILT |
8896 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
8897 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
8898 | { |
8899 | s_ignore (0); | |
8900 | return; | |
8901 | } | |
8902 | ||
8903 | /* .cpload should be a in .set noreorder section. */ | |
8904 | if (mips_noreorder == 0) | |
8905 | as_warn (".cpload not in noreorder section"); | |
8906 | ||
9226253a ILT |
8907 | ex.X_op = O_symbol; |
8908 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
8909 | ex.X_op_symbol = NULL; | |
8910 | ex.X_add_number = 0; | |
8911 | ||
fb251650 ILT |
8912 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
8913 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
8914 | ||
0dd2d296 ILT |
8915 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
8916 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
8917 | (int) BFD_RELOC_LO16); |
8918 | ||
0dd2d296 ILT |
8919 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
8920 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
8921 | |
8922 | demand_empty_rest_of_line (); | |
8923 | } | |
8924 | ||
8925 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
8926 | offset from $sp. The offset is remembered, and after making a PIC | |
8927 | call $gp is restored from that location. */ | |
8928 | ||
8929 | static void | |
8930 | s_cprestore (ignore) | |
8931 | int ignore; | |
8932 | { | |
8933 | expressionS ex; | |
8934 | int icnt = 0; | |
8935 | ||
d9aba805 ILT |
8936 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
8937 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
8938 | { |
8939 | s_ignore (0); | |
8940 | return; | |
8941 | } | |
8942 | ||
9226253a ILT |
8943 | mips_cprestore_offset = get_absolute_expression (); |
8944 | ||
8945 | ex.X_op = O_constant; | |
8946 | ex.X_add_symbol = NULL; | |
8947 | ex.X_op_symbol = NULL; | |
8948 | ex.X_add_number = mips_cprestore_offset; | |
8949 | ||
0dd2d296 | 8950 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
8951 | mips_isa < 3 ? "sw" : "sd", |
8952 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
8953 | ||
8954 | demand_empty_rest_of_line (); | |
8955 | } | |
8956 | ||
0dd2d296 ILT |
8957 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
8958 | code. It generates a 32 bit GP relative reloc. */ | |
8959 | ||
8960 | static void | |
8961 | s_gpword (ignore) | |
8962 | int ignore; | |
8963 | { | |
23dc1ae3 | 8964 | symbolS *label; |
0dd2d296 ILT |
8965 | expressionS ex; |
8966 | char *p; | |
8967 | ||
8968 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 8969 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
8970 | { |
8971 | s_cons (2); | |
8972 | return; | |
8973 | } | |
8974 | ||
fbcfacb7 ILT |
8975 | label = insn_labels != NULL ? insn_labels->label : NULL; |
8976 | mips_emit_delays (true); | |
0dd2d296 | 8977 | if (auto_align) |
23dc1ae3 | 8978 | mips_align (2, 0, label); |
fbcfacb7 | 8979 | mips_clear_insn_labels (); |
0dd2d296 ILT |
8980 | |
8981 | expression (&ex); | |
8982 | ||
8983 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
8984 | { | |
8985 | as_bad ("Unsupported use of .gpword"); | |
8986 | ignore_rest_of_line (); | |
8987 | } | |
8988 | ||
8989 | p = frag_more (4); | |
8990 | md_number_to_chars (p, (valueT) 0, 4); | |
8991 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
8992 | BFD_RELOC_MIPS_GPREL32); | |
8993 | ||
8994 | demand_empty_rest_of_line (); | |
8995 | } | |
8996 | ||
8997 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
8998 | tables in SVR4 PIC code. */ | |
8999 | ||
9000 | static void | |
9001 | s_cpadd (ignore) | |
9002 | int ignore; | |
9003 | { | |
9004 | int icnt = 0; | |
9005 | int reg; | |
9006 | ||
9007 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9008 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9009 | { |
9010 | s_ignore (0); | |
9011 | return; | |
9012 | } | |
9013 | ||
9014 | /* Add $gp to the register named as an argument. */ | |
9015 | reg = tc_get_register (0); | |
9016 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9017 | mips_isa < 3 ? "addu" : "daddu", | |
9018 | "d,v,t", reg, reg, GP); | |
9019 | ||
9020 | demand_empty_rest_of_line (); | |
9021 | } | |
9022 | ||
9226253a | 9023 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9024 | to parse .frame. The argument is non-zero if this is the frame |
9025 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9026 | |
3d3c5039 | 9027 | int |
0dd2d296 ILT |
9028 | tc_get_register (frame) |
9029 | int frame; | |
3d3c5039 ILT |
9030 | { |
9031 | int reg; | |
9032 | ||
9033 | SKIP_WHITESPACE (); | |
9034 | if (*input_line_pointer++ != '$') | |
9035 | { | |
9036 | as_warn ("expected `$'"); | |
0dd2d296 | 9037 | reg = 0; |
3d3c5039 | 9038 | } |
0dd2d296 | 9039 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9040 | { |
9041 | reg = get_absolute_expression (); | |
9042 | if (reg < 0 || reg >= 32) | |
9043 | { | |
9044 | as_warn ("Bad register number"); | |
9045 | reg = 0; | |
9046 | } | |
9047 | } | |
9048 | else | |
9049 | { | |
9050 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9051 | reg = FP; |
3d3c5039 | 9052 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9053 | reg = SP; |
3d3c5039 | 9054 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9055 | reg = GP; |
3d3c5039 | 9056 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9057 | reg = AT; |
3d3c5039 ILT |
9058 | else |
9059 | { | |
9060 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9061 | reg = 0; |
3d3c5039 ILT |
9062 | } |
9063 | input_line_pointer += 2; | |
9064 | } | |
0dd2d296 ILT |
9065 | if (frame) |
9066 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9067 | return reg; |
9068 | } | |
9069 | ||
0dd2d296 ILT |
9070 | valueT |
9071 | md_section_align (seg, addr) | |
9072 | asection *seg; | |
9073 | valueT addr; | |
9074 | { | |
9075 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9076 | ||
cf32394d ILT |
9077 | #ifdef OBJ_ELF |
9078 | /* We don't need to align ELF sections to the full alignment. | |
9079 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9080 | byte boundary. We don't bother to align the sections if we are |
9081 | targeted for an embedded system. */ | |
9082 | if (strcmp (TARGET_OS, "elf") == 0) | |
9083 | return addr; | |
943321c0 ILT |
9084 | if (align > 4) |
9085 | align = 4; | |
10a14e36 | 9086 | #endif |
cf32394d ILT |
9087 | |
9088 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9089 | } |
9090 | ||
d8a1c247 KR |
9091 | /* Utility routine, called from above as well. If called while the |
9092 | input file is still being read, it's only an approximation. (For | |
9093 | example, a symbol may later become defined which appeared to be | |
9094 | undefined earlier.) */ | |
22ba90ce ILT |
9095 | |
9096 | static int | |
9097 | nopic_need_relax (sym) | |
d8a1c247 KR |
9098 | symbolS *sym; |
9099 | { | |
9100 | if (sym == 0) | |
9101 | return 0; | |
9102 | ||
1dc1e798 KR |
9103 | if (USE_GLOBAL_POINTER_OPT) |
9104 | { | |
9105 | const char *symname; | |
9106 | int change; | |
9107 | ||
9108 | /* Find out whether this symbol can be referenced off the GP | |
9109 | register. It can be if it is smaller than the -G size or if | |
9110 | it is in the .sdata or .sbss section. Certain symbols can | |
9111 | not be referenced off the GP, although it appears as though | |
9112 | they can. */ | |
9113 | symname = S_GET_NAME (sym); | |
9114 | if (symname != (const char *) NULL | |
9115 | && (strcmp (symname, "eprol") == 0 | |
9116 | || strcmp (symname, "etext") == 0 | |
9117 | || strcmp (symname, "_gp") == 0 | |
9118 | || strcmp (symname, "edata") == 0 | |
9119 | || strcmp (symname, "_fbss") == 0 | |
9120 | || strcmp (symname, "_fdata") == 0 | |
9121 | || strcmp (symname, "_ftext") == 0 | |
9122 | || strcmp (symname, "end") == 0 | |
9123 | || strcmp (symname, "_gp_disp") == 0)) | |
9124 | change = 1; | |
9125 | else if (! S_IS_DEFINED (sym) | |
c625fc23 JSC |
9126 | && (0 |
9127 | #ifndef NO_ECOFF_DEBUGGING | |
9128 | || (sym->ecoff_extern_size != 0 | |
9129 | && sym->ecoff_extern_size <= g_switch_value) | |
9130 | #endif | |
1dc1e798 KR |
9131 | || (S_GET_VALUE (sym) != 0 |
9132 | && S_GET_VALUE (sym) <= g_switch_value))) | |
9133 | change = 0; | |
9134 | else | |
9135 | { | |
9136 | const char *segname; | |
d8a1c247 | 9137 | |
1dc1e798 KR |
9138 | segname = segment_name (S_GET_SEGMENT (sym)); |
9139 | assert (strcmp (segname, ".lit8") != 0 | |
9140 | && strcmp (segname, ".lit4") != 0); | |
9141 | change = (strcmp (segname, ".sdata") != 0 | |
9142 | && strcmp (segname, ".sbss") != 0); | |
9143 | } | |
9144 | return change; | |
9145 | } | |
9146 | else | |
9147 | /* We are not optimizing for the GP register. */ | |
9148 | return 1; | |
d8a1c247 KR |
9149 | } |
9150 | ||
cc5703cd ILT |
9151 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
9152 | extended opcode. SEC is the section the frag is in. */ | |
9153 | ||
9154 | static int | |
9155 | mips16_extended_frag (fragp, sec, stretch) | |
9156 | fragS *fragp; | |
9157 | asection *sec; | |
9158 | long stretch; | |
9159 | { | |
9160 | int type; | |
9161 | register const struct mips16_immed_operand *op; | |
9162 | offsetT val; | |
9163 | int mintiny, maxtiny; | |
f74ba7a3 | 9164 | segT symsec; |
cc5703cd | 9165 | |
8728fa92 ILT |
9166 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
9167 | return 0; | |
9168 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
9169 | return 1; | |
9170 | ||
cc5703cd ILT |
9171 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
9172 | op = mips16_immed_operands; | |
9173 | while (op->type != type) | |
9174 | { | |
9175 | ++op; | |
9176 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9177 | } | |
9178 | ||
9179 | if (op->unsp) | |
9180 | { | |
9181 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9182 | { | |
9183 | mintiny = 1; | |
9184 | maxtiny = 1 << op->nbits; | |
9185 | } | |
9186 | else | |
9187 | { | |
9188 | mintiny = 0; | |
9189 | maxtiny = (1 << op->nbits) - 1; | |
9190 | } | |
9191 | } | |
9192 | else | |
9193 | { | |
9194 | mintiny = - (1 << (op->nbits - 1)); | |
9195 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9196 | } | |
9197 | ||
f74ba7a3 ILT |
9198 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
9199 | a particular frag address. */ | |
9200 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
9201 | { | |
9202 | val = (fragp->fr_symbol->sy_value.X_add_number | |
9203 | + fragp->fr_symbol->sy_frag->fr_address); | |
9204 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
9205 | } | |
9206 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
9207 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
9208 | == O_constant)) | |
9209 | { | |
9210 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
9211 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
9212 | + fragp->fr_symbol->sy_value.X_add_number | |
9213 | + fragp->fr_symbol->sy_frag->fr_address); | |
9214 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
9215 | } | |
9216 | else | |
9217 | return 1; | |
cc5703cd ILT |
9218 | |
9219 | if (op->pcrel) | |
9220 | { | |
9221 | addressT addr; | |
9222 | ||
9223 | /* We won't have the section when we are called from | |
9224 | mips_relax_frag. However, we will always have been called | |
9225 | from md_estimate_size_before_relax first. If this is a | |
9226 | branch to a different section, we mark it as such. If SEC is | |
9227 | NULL, and the frag is not marked, then it must be a branch to | |
9228 | the same section. */ | |
9229 | if (sec == NULL) | |
9230 | { | |
9231 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
9232 | return 1; | |
9233 | } | |
9234 | else | |
9235 | { | |
f74ba7a3 | 9236 | if (symsec != sec) |
cc5703cd ILT |
9237 | { |
9238 | fragp->fr_subtype = | |
9239 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9240 | ||
9241 | /* FIXME: We should support this, and let the linker | |
9242 | catch branches and loads that are out of range. */ | |
9243 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
9244 | "unsupported PC relative reference to different section"); | |
9245 | ||
9246 | return 1; | |
9247 | } | |
9248 | } | |
9249 | ||
9250 | /* In this case, we know for sure that the symbol fragment is in | |
9251 | the same section. If the fr_address of the symbol fragment | |
9252 | is greater then the address of this fragment we want to add | |
9253 | in STRETCH in order to get a better estimate of the address. | |
9254 | This particularly matters because of the shift bits. */ | |
9255 | if (stretch != 0 | |
9256 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
9257 | { | |
9258 | fragS *f; | |
9259 | ||
9260 | /* Adjust stretch for any alignment frag. */ | |
9261 | for (f = fragp; f != fragp->fr_symbol->sy_frag; f = f->fr_next) | |
9262 | { | |
9263 | assert (f != NULL); | |
9264 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
9265 | { | |
9266 | if (stretch < 0) | |
9267 | stretch = - ((- stretch) | |
9268 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
9269 | else | |
9270 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
9271 | if (stretch == 0) | |
9272 | break; | |
9273 | } | |
9274 | } | |
9275 | val += stretch; | |
9276 | } | |
9277 | ||
a677feeb ILT |
9278 | addr = fragp->fr_address + fragp->fr_fix; |
9279 | ||
9280 | /* The base address rules are complicated. The base address of | |
9281 | a branch is the following instruction. The base address of a | |
9282 | PC relative load or add is the instruction itself, but if it | |
9283 | is extended add 2, and if it is in a delay slot (in which | |
9284 | case it can not be extended) use the address of the | |
9285 | instruction whose delay slot it is in. */ | |
9286 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9287 | { |
9288 | addr += 2; | |
9289 | /* Ignore the low bit in the target, since it will be set | |
9290 | for a text label. */ | |
9291 | if ((val & 1) != 0) | |
9292 | --val; | |
9293 | } | |
a677feeb ILT |
9294 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9295 | addr -= 4; | |
9296 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9297 | addr -= 2; | |
cc5703cd ILT |
9298 | |
9299 | /* If we are currently assuming that this frag should be | |
9300 | extended, then the current address is two bytes higher. */ | |
9301 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9302 | addr += 2; | |
9303 | ||
9304 | val -= addr & ~ ((1 << op->shift) - 1); | |
9305 | ||
9306 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9307 | if (type == 'p' || type == 'q') | |
9308 | val /= 2; | |
9309 | ||
9310 | /* If any of the shifted bits are set, we must use an extended | |
9311 | opcode. If the address depends on the size of this | |
9312 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
9313 | use an extended opcode. We only check this when we are in |
9314 | the main relaxation loop, when SEC is NULL. */ | |
9315 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
9316 | { | |
9317 | fragp->fr_subtype = | |
9318 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9319 | return 1; | |
9320 | } | |
9321 | ||
9322 | /* If we are about to mark a frag as extended because the value | |
9323 | is precisely maxtiny + 1, then there is a chance of an | |
9324 | infinite loop as in the following code: | |
9325 | la $4,foo | |
9326 | .skip 1020 | |
9327 | .align 2 | |
9328 | foo: | |
9329 | In this case when the la is extended, foo is 0x3fc bytes | |
9330 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
9331 | the la must be extended. To avoid this loop, we mark the | |
9332 | frag as extended if it was small, and is about to become | |
9333 | extended with a value of maxtiny + 1. */ | |
9334 | if (val == ((maxtiny + 1) << op->shift) | |
9335 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
9336 | && sec == NULL) | |
cc5703cd ILT |
9337 | { |
9338 | fragp->fr_subtype = | |
9339 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
9340 | return 1; | |
9341 | } | |
9342 | } | |
41a0ed22 ILT |
9343 | else if (symsec != absolute_section && sec != NULL) |
9344 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
9345 | |
9346 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9347 | || val < (mintiny << op->shift) | |
9348 | || val > (maxtiny << op->shift)) | |
9349 | return 1; | |
9350 | else | |
9351 | return 0; | |
9352 | } | |
9353 | ||
9354 | /* Estimate the size of a frag before relaxing. Unless this is the | |
9355 | mips16, we are not really relaxing here, and the final size is | |
9356 | encoded in the subtype information. For the mips16, we have to | |
9357 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 9358 | |
0dd2d296 ILT |
9359 | /*ARGSUSED*/ |
9360 | int | |
9361 | md_estimate_size_before_relax (fragp, segtype) | |
9362 | fragS *fragp; | |
9363 | asection *segtype; | |
9364 | { | |
9365 | int change; | |
9366 | ||
cc5703cd ILT |
9367 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9368 | { | |
9369 | if (mips16_extended_frag (fragp, segtype, 0)) | |
9370 | { | |
9371 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9372 | return 4; | |
9373 | } | |
9374 | else | |
9375 | { | |
9376 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9377 | return 2; | |
9378 | } | |
9379 | } | |
9380 | ||
d9aba805 | 9381 | if (mips_pic == NO_PIC) |
0dd2d296 | 9382 | { |
d8a1c247 | 9383 | change = nopic_need_relax (fragp->fr_symbol); |
0dd2d296 | 9384 | } |
d9aba805 | 9385 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
9386 | { |
9387 | asection *symsec = fragp->fr_symbol->bsym->section; | |
9388 | ||
9389 | /* This must duplicate the test in adjust_reloc_syms. */ | |
9390 | change = (symsec != &bfd_und_section | |
9391 | && symsec != &bfd_abs_section | |
9392 | && ! bfd_is_com_section (symsec)); | |
9393 | } | |
d9aba805 ILT |
9394 | else |
9395 | abort (); | |
0dd2d296 ILT |
9396 | |
9397 | if (change) | |
9398 | { | |
9399 | /* Record the offset to the first reloc in the fr_opcode field. | |
9400 | This lets md_convert_frag and tc_gen_reloc know that the code | |
9401 | must be expanded. */ | |
9402 | fragp->fr_opcode = (fragp->fr_literal | |
9403 | + fragp->fr_fix | |
9404 | - RELAX_OLD (fragp->fr_subtype) | |
9405 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
9406 | /* FIXME: This really needs as_warn_where. */ | |
9407 | if (RELAX_WARN (fragp->fr_subtype)) | |
9408 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
9409 | } | |
9410 | ||
9411 | if (! change) | |
9412 | return 0; | |
9413 | else | |
9414 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
9415 | } | |
9416 | ||
9417 | /* Translate internal representation of relocation info to BFD target | |
9418 | format. */ | |
9419 | ||
9420 | arelent ** | |
3d3c5039 ILT |
9421 | tc_gen_reloc (section, fixp) |
9422 | asection *section; | |
9423 | fixS *fixp; | |
9424 | { | |
0dd2d296 | 9425 | static arelent *retval[4]; |
3d3c5039 | 9426 | arelent *reloc; |
a8aed9dd | 9427 | bfd_reloc_code_real_type code; |
3d3c5039 | 9428 | |
0dd2d296 ILT |
9429 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
9430 | retval[1] = NULL; | |
3d3c5039 ILT |
9431 | |
9432 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9433 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
9434 | |
9435 | if (mips_pic == EMBEDDED_PIC | |
9436 | && SWITCH_TABLE (fixp)) | |
9437 | { | |
9438 | /* For a switch table entry we use a special reloc. The addend | |
9439 | is actually the difference between the reloc address and the | |
9440 | subtrahend. */ | |
9441 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
9442 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
9443 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
9444 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
9445 | } | |
ecd4ca1c ILT |
9446 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
9447 | { | |
9448 | /* We use a special addend for an internal RELLO reloc. */ | |
9449 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9450 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
9451 | else | |
9452 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
9453 | } | |
9454 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
9455 | { | |
9456 | assert (fixp->fx_next != NULL | |
9457 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
9458 | /* We use a special addend for an internal RELHI reloc. The | |
9459 | reloc is relative to the RELLO; adjust the addend | |
9460 | accordingly. */ | |
9461 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
9462 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
9463 | + fixp->fx_next->fx_where | |
9464 | - S_GET_VALUE (fixp->fx_subsy)); | |
9465 | else | |
9466 | reloc->addend = (fixp->fx_addnumber | |
9467 | + fixp->fx_next->fx_frag->fr_address | |
9468 | + fixp->fx_next->fx_where); | |
9469 | } | |
1c803e52 | 9470 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
9471 | reloc->addend = fixp->fx_addnumber; |
9472 | else | |
5b63f465 | 9473 | { |
1dc1e798 KR |
9474 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
9475 | /* A gruesome hack which is a result of the gruesome gas reloc | |
9476 | handling. */ | |
9477 | reloc->addend = reloc->address; | |
9478 | else | |
9479 | reloc->addend = -reloc->address; | |
5b63f465 | 9480 | } |
0dd2d296 ILT |
9481 | |
9482 | /* If this is a variant frag, we may need to adjust the existing | |
9483 | reloc and generate a new one. */ | |
9484 | if (fixp->fx_frag->fr_opcode != NULL | |
9485 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
9486 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
9487 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
9488 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9489 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
9490 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9491 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
9492 | { |
9493 | arelent *reloc2; | |
9494 | ||
cc5703cd ILT |
9495 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
9496 | ||
0dd2d296 | 9497 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
9498 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
9499 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
9500 | the second one handle all of them. */ | |
0dd2d296 ILT |
9501 | if (fixp->fx_next != NULL |
9502 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
9503 | { | |
fb251650 ILT |
9504 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
9505 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
9506 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
9507 | && (fixp->fx_next->fx_r_type | |
9508 | == BFD_RELOC_MIPS_GOT_LO16)) | |
9509 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
9510 | && (fixp->fx_next->fx_r_type | |
9511 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
9512 | retval[0] = NULL; |
9513 | return retval; | |
9514 | } | |
9515 | ||
9516 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
9517 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
9518 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
9519 | retval[2] = NULL; | |
9520 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
9521 | reloc2->address = (reloc->address | |
9522 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
9523 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
9524 | reloc2->addend = fixp->fx_addnumber; | |
9525 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
9526 | assert (reloc2->howto != NULL); | |
9527 | ||
9528 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
9529 | { | |
9530 | arelent *reloc3; | |
9531 | ||
9532 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
9533 | retval[3] = NULL; | |
9534 | *reloc3 = *reloc2; | |
9535 | reloc3->address += 4; | |
9536 | } | |
9537 | ||
d9aba805 | 9538 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
9539 | { |
9540 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
9541 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
9542 | } | |
d9aba805 | 9543 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 9544 | { |
fb251650 | 9545 | switch (fixp->fx_r_type) |
0dd2d296 | 9546 | { |
fb251650 ILT |
9547 | default: |
9548 | abort (); | |
9549 | case BFD_RELOC_MIPS_GOT16: | |
9550 | break; | |
9551 | case BFD_RELOC_MIPS_CALL16: | |
9552 | case BFD_RELOC_MIPS_GOT_LO16: | |
9553 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 9554 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 9555 | break; |
0dd2d296 ILT |
9556 | } |
9557 | } | |
d9aba805 ILT |
9558 | else |
9559 | abort (); | |
0dd2d296 ILT |
9560 | } |
9561 | ||
a8aed9dd ILT |
9562 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
9563 | fixup_segment converted a non-PC relative reloc into a PC | |
9564 | relative reloc. In such a case, we need to convert the reloc | |
9565 | code. */ | |
9566 | code = fixp->fx_r_type; | |
9567 | if (fixp->fx_pcrel) | |
9568 | { | |
9569 | switch (code) | |
9570 | { | |
9571 | case BFD_RELOC_8: | |
9572 | code = BFD_RELOC_8_PCREL; | |
9573 | break; | |
9574 | case BFD_RELOC_16: | |
9575 | code = BFD_RELOC_16_PCREL; | |
9576 | break; | |
9577 | case BFD_RELOC_32: | |
9578 | code = BFD_RELOC_32_PCREL; | |
9579 | break; | |
bf39474f ILT |
9580 | case BFD_RELOC_64: |
9581 | code = BFD_RELOC_64_PCREL; | |
9582 | break; | |
a8aed9dd ILT |
9583 | case BFD_RELOC_8_PCREL: |
9584 | case BFD_RELOC_16_PCREL: | |
9585 | case BFD_RELOC_32_PCREL: | |
bf39474f | 9586 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 9587 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
9588 | case BFD_RELOC_PCREL_HI16_S: |
9589 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
9590 | break; |
9591 | default: | |
9592 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9593 | "Cannot make %s relocation PC relative", | |
9594 | bfd_get_reloc_code_name (code)); | |
9595 | } | |
9596 | } | |
9597 | ||
d9aba805 ILT |
9598 | /* To support a PC relative reloc when generating embedded PIC code |
9599 | for ECOFF, we use a Cygnus extension. We check for that here to | |
9600 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 9601 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 9602 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
9603 | && mips_pic != EMBEDDED_PIC) |
9604 | reloc->howto = NULL; | |
9605 | else | |
a8aed9dd | 9606 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 9607 | |
52aa70b5 JW |
9608 | if (reloc->howto == NULL) |
9609 | { | |
9610 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
9611 | "Can not represent %s relocation in this object file format", |
9612 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 9613 | retval[0] = NULL; |
52aa70b5 | 9614 | } |
3d3c5039 | 9615 | |
0dd2d296 | 9616 | return retval; |
3d3c5039 ILT |
9617 | } |
9618 | ||
cc5703cd ILT |
9619 | /* Relax a machine dependent frag. This returns the amount by which |
9620 | the current size of the frag should change. */ | |
9621 | ||
9622 | int | |
9623 | mips_relax_frag (fragp, stretch) | |
9624 | fragS *fragp; | |
9625 | long stretch; | |
9626 | { | |
9627 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
9628 | return 0; | |
9629 | ||
9630 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
9631 | { | |
9632 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9633 | return 0; | |
9634 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
9635 | return 2; | |
9636 | } | |
9637 | else | |
9638 | { | |
9639 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9640 | return 0; | |
9641 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
9642 | return -2; | |
9643 | } | |
9644 | ||
9645 | return 0; | |
9646 | } | |
9647 | ||
0dd2d296 ILT |
9648 | /* Convert a machine dependent frag. */ |
9649 | ||
9650 | void | |
9651 | md_convert_frag (abfd, asec, fragp) | |
9652 | bfd *abfd; | |
9653 | segT asec; | |
9654 | fragS *fragp; | |
3d3c5039 | 9655 | { |
0dd2d296 ILT |
9656 | int old, new; |
9657 | char *fixptr; | |
3d3c5039 | 9658 | |
cc5703cd ILT |
9659 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
9660 | { | |
9661 | int type; | |
9662 | register const struct mips16_immed_operand *op; | |
9663 | boolean small, ext; | |
9664 | offsetT val; | |
9665 | bfd_byte *buf; | |
9666 | unsigned long insn; | |
9667 | boolean use_extend; | |
9668 | unsigned short extend; | |
9669 | ||
9670 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
9671 | op = mips16_immed_operands; | |
9672 | while (op->type != type) | |
9673 | ++op; | |
9674 | ||
9675 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
9676 | { | |
9677 | small = false; | |
9678 | ext = true; | |
9679 | } | |
9680 | else | |
9681 | { | |
9682 | small = true; | |
9683 | ext = false; | |
9684 | } | |
9685 | ||
f74ba7a3 | 9686 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 9687 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
9688 | if (op->pcrel) |
9689 | { | |
9690 | addressT addr; | |
9691 | ||
a677feeb ILT |
9692 | addr = fragp->fr_address + fragp->fr_fix; |
9693 | ||
9694 | /* The rules for the base address of a PC relative reloc are | |
9695 | complicated; see mips16_extended_frag. */ | |
9696 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
9697 | { |
9698 | addr += 2; | |
9699 | /* Ignore the low bit in the target, since it will be | |
9700 | set for a text label. */ | |
9701 | if ((val & 1) != 0) | |
9702 | --val; | |
9703 | } | |
a677feeb ILT |
9704 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
9705 | addr -= 4; | |
9706 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
9707 | addr -= 2; | |
9708 | ||
cc5703cd ILT |
9709 | if (ext) |
9710 | addr += 2; | |
9711 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
9712 | val -= addr; | |
a677feeb ILT |
9713 | |
9714 | /* Make sure the section winds up with the alignment we have | |
9715 | assumed. */ | |
9716 | if (op->shift > 0) | |
9717 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
9718 | } |
9719 | ||
9720 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
9721 | ||
9722 | switch (byte_order) | |
9723 | { | |
9724 | default: | |
9725 | internalError (); | |
9726 | case LITTLE_ENDIAN: | |
9727 | insn = bfd_getl16 (buf); | |
9728 | break; | |
9729 | case BIG_ENDIAN: | |
9730 | insn = bfd_getb16 (buf); | |
9731 | break; | |
9732 | } | |
9733 | ||
15e69f98 ILT |
9734 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, false, small, |
9735 | ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
9736 | |
9737 | if (use_extend) | |
9738 | { | |
9739 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
9740 | fragp->fr_fix += 2; | |
9741 | buf += 2; | |
9742 | } | |
3d3c5039 | 9743 | |
cc5703cd ILT |
9744 | md_number_to_chars (buf, insn, 2); |
9745 | fragp->fr_fix += 2; | |
9746 | buf += 2; | |
9747 | } | |
9748 | else | |
9749 | { | |
9750 | if (fragp->fr_opcode == NULL) | |
9751 | return; | |
0dd2d296 | 9752 | |
cc5703cd ILT |
9753 | old = RELAX_OLD (fragp->fr_subtype); |
9754 | new = RELAX_NEW (fragp->fr_subtype); | |
9755 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 9756 | |
cc5703cd ILT |
9757 | if (new > 0) |
9758 | memcpy (fixptr - old, fixptr, new); | |
9759 | ||
9760 | fragp->fr_fix += new - old; | |
9761 | } | |
0dd2d296 | 9762 | } |
becfe05e | 9763 | |
fbcfacb7 ILT |
9764 | #ifdef OBJ_ELF |
9765 | ||
9766 | /* This function is called after the relocs have been generated. | |
9767 | We've been storing mips16 text labels as odd. Here we convert them | |
9768 | back to even for the convenience of the debugger. */ | |
9769 | ||
9770 | void | |
9771 | mips_frob_file_after_relocs () | |
9772 | { | |
9773 | asymbol **syms; | |
9774 | unsigned int count, i; | |
9775 | ||
9776 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9777 | return; | |
9778 | ||
9779 | syms = bfd_get_outsymbols (stdoutput); | |
9780 | count = bfd_get_symcount (stdoutput); | |
9781 | for (i = 0; i < count; i++, syms++) | |
9782 | { | |
9783 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
9784 | && ((*syms)->value & 1) != 0) | |
9785 | { | |
9786 | (*syms)->value &= ~1; | |
9787 | /* If the symbol has an odd size, it was probably computed | |
9788 | incorrectly, so adjust that as well. */ | |
9789 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
9790 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
9791 | } | |
9792 | } | |
9793 | } | |
9794 | ||
9795 | #endif | |
9796 | ||
becfe05e ILT |
9797 | /* This function is called whenever a label is defined. It is used |
9798 | when handling branch delays; if a branch has a label, we assume we | |
9799 | can not move it. */ | |
9800 | ||
9801 | void | |
9802 | mips_define_label (sym) | |
9803 | symbolS *sym; | |
9804 | { | |
fbcfacb7 ILT |
9805 | struct insn_label_list *l; |
9806 | ||
9807 | if (free_insn_labels == NULL) | |
9808 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
9809 | else | |
9810 | { | |
9811 | l = free_insn_labels; | |
9812 | free_insn_labels = l->next; | |
9813 | } | |
9814 | ||
9815 | l->label = sym; | |
9816 | l->next = insn_labels; | |
9817 | insn_labels = l; | |
becfe05e | 9818 | } |
22ba90ce ILT |
9819 | |
9820 | /* Decide whether a label is local. This is called by LOCAL_LABEL. | |
9821 | In order to work with gcc when using mips-tfile, we must keep all | |
9822 | local labels. However, in other cases, we want to discard them, | |
9823 | since they are useless. */ | |
9824 | ||
9825 | int | |
9826 | mips_local_label (name) | |
9827 | const char *name; | |
9828 | { | |
c625fc23 | 9829 | #ifndef NO_ECOFF_DEBUGGING |
22ba90ce ILT |
9830 | if (ECOFF_DEBUGGING |
9831 | && mips_debug != 0 | |
9832 | && ! ecoff_debugging_seen) | |
9833 | { | |
9834 | /* We were called with -g, but we didn't see any debugging | |
9835 | information. That may mean that gcc is smuggling debugging | |
9836 | information through to mips-tfile, in which case we must | |
9837 | generate all local labels. */ | |
9838 | return 0; | |
9839 | } | |
c625fc23 | 9840 | #endif |
22ba90ce ILT |
9841 | |
9842 | /* Here it's OK to discard local labels. */ | |
9843 | ||
3af584b4 | 9844 | return name[0] == '$'; |
22ba90ce | 9845 | } |
3d3c5039 | 9846 | \f |
739708fa | 9847 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 9848 | |
0dd2d296 | 9849 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
9850 | |
9851 | void | |
9852 | mips_elf_final_processing () | |
9853 | { | |
87178180 ILT |
9854 | /* Write out the register information. */ |
9855 | if (! mips_64) | |
9856 | { | |
9857 | Elf32_RegInfo s; | |
9858 | ||
9859 | s.ri_gprmask = mips_gprmask; | |
9860 | s.ri_cprmask[0] = mips_cprmask[0]; | |
9861 | s.ri_cprmask[1] = mips_cprmask[1]; | |
9862 | s.ri_cprmask[2] = mips_cprmask[2]; | |
9863 | s.ri_cprmask[3] = mips_cprmask[3]; | |
9864 | /* The gp_value field is set by the MIPS ELF backend. */ | |
9865 | ||
9866 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
9867 | ((Elf32_External_RegInfo *) | |
9868 | mips_regmask_frag)); | |
9869 | } | |
9870 | else | |
9871 | { | |
9872 | Elf64_Internal_RegInfo s; | |
9873 | ||
9874 | s.ri_gprmask = mips_gprmask; | |
9875 | s.ri_pad = 0; | |
9876 | s.ri_cprmask[0] = mips_cprmask[0]; | |
9877 | s.ri_cprmask[1] = mips_cprmask[1]; | |
9878 | s.ri_cprmask[2] = mips_cprmask[2]; | |
9879 | s.ri_cprmask[3] = mips_cprmask[3]; | |
9880 | /* The gp_value field is set by the MIPS ELF backend. */ | |
9881 | ||
9882 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
9883 | ((Elf64_External_RegInfo *) | |
9884 | mips_regmask_frag)); | |
9885 | } | |
0dd2d296 ILT |
9886 | |
9887 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
9888 | sort of BFD interface for this. */ | |
9889 | if (mips_any_noreorder) | |
9890 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 9891 | if (mips_pic != NO_PIC) |
0dd2d296 | 9892 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
9893 | } |
9894 | ||
739708fa | 9895 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 9896 | \f |
3d3c5039 ILT |
9897 | /* These functions should really be defined by the object file format, |
9898 | since they are related to debugging information. However, this | |
9899 | code has to work for the a.out format, which does not define them, | |
9900 | so we provide simple versions here. These don't actually generate | |
9901 | any debugging information, but they do simple checking and someday | |
9902 | somebody may make them useful. */ | |
9903 | ||
670a50eb ILT |
9904 | typedef struct loc |
9905 | { | |
9906 | struct loc *loc_next; | |
9907 | unsigned long loc_fileno; | |
9908 | unsigned long loc_lineno; | |
9909 | unsigned long loc_offset; | |
9910 | unsigned short loc_delta; | |
9911 | unsigned short loc_count; | |
3d3c5039 | 9912 | #if 0 |
670a50eb | 9913 | fragS *loc_frag; |
3d3c5039 | 9914 | #endif |
670a50eb ILT |
9915 | } |
9916 | locS; | |
3d3c5039 | 9917 | |
670a50eb ILT |
9918 | typedef struct proc |
9919 | { | |
3d3c5039 ILT |
9920 | struct proc *proc_next; |
9921 | struct symbol *proc_isym; | |
9922 | struct symbol *proc_end; | |
9923 | unsigned long proc_reg_mask; | |
9924 | unsigned long proc_reg_offset; | |
9925 | unsigned long proc_fpreg_mask; | |
9926 | unsigned long proc_fpreg_offset; | |
9927 | unsigned long proc_frameoffset; | |
9928 | unsigned long proc_framereg; | |
9929 | unsigned long proc_pcreg; | |
9930 | locS *proc_iline; | |
9931 | struct file *proc_file; | |
9932 | int proc_index; | |
670a50eb ILT |
9933 | } |
9934 | procS; | |
3d3c5039 | 9935 | |
670a50eb ILT |
9936 | typedef struct file |
9937 | { | |
3d3c5039 ILT |
9938 | struct file *file_next; |
9939 | unsigned long file_fileno; | |
9940 | struct symbol *file_symbol; | |
9941 | struct symbol *file_end; | |
9942 | struct proc *file_proc; | |
9943 | int file_numprocs; | |
670a50eb ILT |
9944 | } |
9945 | fileS; | |
3d3c5039 ILT |
9946 | |
9947 | static struct obstack proc_frags; | |
9948 | static procS *proc_lastP; | |
9949 | static procS *proc_rootP; | |
9950 | static int numprocs; | |
9951 | ||
9952 | static void | |
9953 | md_obj_begin () | |
9954 | { | |
670a50eb | 9955 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
9956 | } |
9957 | ||
9958 | static void | |
9959 | md_obj_end () | |
9960 | { | |
9961 | /* check for premature end, nesting errors, etc */ | |
9962 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 9963 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
9964 | } |
9965 | ||
3d3c5039 ILT |
9966 | static long |
9967 | get_number () | |
9968 | { | |
670a50eb ILT |
9969 | int negative = 0; |
9970 | long val = 0; | |
3d3c5039 | 9971 | |
670a50eb ILT |
9972 | if (*input_line_pointer == '-') |
9973 | { | |
9974 | ++input_line_pointer; | |
9975 | negative = 1; | |
3d3c5039 | 9976 | } |
670a50eb ILT |
9977 | if (!isdigit (*input_line_pointer)) |
9978 | as_bad ("Expected simple number."); | |
9979 | if (input_line_pointer[0] == '0') | |
9980 | { | |
9981 | if (input_line_pointer[1] == 'x') | |
9982 | { | |
9983 | input_line_pointer += 2; | |
9984 | while (isxdigit (*input_line_pointer)) | |
9985 | { | |
9986 | val <<= 4; | |
3a762a0b | 9987 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 9988 | } |
670a50eb ILT |
9989 | return negative ? -val : val; |
9990 | } | |
9991 | else | |
9992 | { | |
9993 | ++input_line_pointer; | |
9994 | while (isdigit (*input_line_pointer)) | |
9995 | { | |
9996 | val <<= 3; | |
9997 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 9998 | } |
670a50eb | 9999 | return negative ? -val : val; |
3d3c5039 ILT |
10000 | } |
10001 | } | |
670a50eb ILT |
10002 | if (!isdigit (*input_line_pointer)) |
10003 | { | |
10004 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10005 | *input_line_pointer, *input_line_pointer); | |
10006 | as_warn ("Invalid number"); | |
10007 | return -1; | |
3d3c5039 | 10008 | } |
670a50eb ILT |
10009 | while (isdigit (*input_line_pointer)) |
10010 | { | |
10011 | val *= 10; | |
10012 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10013 | } |
670a50eb | 10014 | return negative ? -val : val; |
3d3c5039 ILT |
10015 | } |
10016 | ||
10017 | /* The .file directive; just like the usual .file directive, but there | |
10018 | is an initial number which is the ECOFF file index. */ | |
10019 | ||
10020 | static void | |
10021 | s_file (x) | |
10022 | int x; | |
10023 | { | |
670a50eb | 10024 | int line; |
3d3c5039 | 10025 | |
670a50eb | 10026 | line = get_number (); |
9a7d824a | 10027 | s_app_file (0); |
3d3c5039 ILT |
10028 | } |
10029 | ||
10030 | ||
10031 | /* The .end directive. */ | |
10032 | ||
10033 | static void | |
10034 | s_mipsend (x) | |
10035 | int x; | |
10036 | { | |
670a50eb ILT |
10037 | symbolS *p; |
10038 | ||
10039 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10040 | { | |
10041 | p = get_symbol (); | |
10042 | demand_empty_rest_of_line (); | |
10043 | } | |
10044 | else | |
10045 | p = NULL; | |
10046 | if (now_seg != text_section) | |
10047 | as_warn (".end not in text section"); | |
10048 | if (!proc_lastP) | |
10049 | { | |
10050 | as_warn (".end and no .ent seen yet."); | |
10051 | return; | |
3d3c5039 ILT |
10052 | } |
10053 | ||
670a50eb ILT |
10054 | if (p != NULL) |
10055 | { | |
10056 | assert (S_GET_NAME (p)); | |
10057 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10058 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10059 | } |
10060 | ||
670a50eb | 10061 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10062 | } |
10063 | ||
10064 | /* The .aent and .ent directives. */ | |
10065 | ||
10066 | static void | |
10067 | s_ent (aent) | |
10068 | int aent; | |
10069 | { | |
670a50eb ILT |
10070 | int number = 0; |
10071 | procS *procP; | |
10072 | symbolS *symbolP; | |
10073 | ||
10074 | symbolP = get_symbol (); | |
10075 | if (*input_line_pointer == ',') | |
10076 | input_line_pointer++; | |
dd3f1f76 | 10077 | SKIP_WHITESPACE (); |
670a50eb ILT |
10078 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10079 | number = get_number (); | |
10080 | if (now_seg != text_section) | |
10081 | as_warn (".ent or .aent not in text section."); | |
10082 | ||
10083 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10084 | as_warn ("missing `.end'"); | |
10085 | ||
10086 | if (!aent) | |
10087 | { | |
10088 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10089 | procP->proc_isym = symbolP; | |
10090 | procP->proc_reg_mask = 0; | |
10091 | procP->proc_reg_offset = 0; | |
10092 | procP->proc_fpreg_mask = 0; | |
10093 | procP->proc_fpreg_offset = 0; | |
10094 | procP->proc_frameoffset = 0; | |
10095 | procP->proc_framereg = 0; | |
10096 | procP->proc_pcreg = 0; | |
10097 | procP->proc_end = NULL; | |
10098 | procP->proc_next = NULL; | |
10099 | if (proc_lastP) | |
10100 | proc_lastP->proc_next = procP; | |
10101 | else | |
10102 | proc_rootP = procP; | |
10103 | proc_lastP = procP; | |
10104 | numprocs++; | |
3d3c5039 | 10105 | } |
670a50eb | 10106 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10107 | } |
10108 | ||
10109 | /* The .frame directive. */ | |
10110 | ||
88225433 | 10111 | #if 0 |
3d3c5039 ILT |
10112 | static void |
10113 | s_frame (x) | |
670a50eb | 10114 | int x; |
3d3c5039 | 10115 | { |
670a50eb ILT |
10116 | char str[100]; |
10117 | symbolS *symP; | |
10118 | int frame_reg; | |
10119 | int frame_off; | |
10120 | int pcreg; | |
10121 | ||
0dd2d296 | 10122 | frame_reg = tc_get_register (1); |
670a50eb ILT |
10123 | if (*input_line_pointer == ',') |
10124 | input_line_pointer++; | |
5ac34ac3 | 10125 | frame_off = get_absolute_expression (); |
670a50eb ILT |
10126 | if (*input_line_pointer == ',') |
10127 | input_line_pointer++; | |
0dd2d296 | 10128 | pcreg = tc_get_register (0); |
670a50eb ILT |
10129 | |
10130 | /* bob third eye */ | |
10131 | assert (proc_rootP); | |
10132 | proc_rootP->proc_framereg = frame_reg; | |
10133 | proc_rootP->proc_frameoffset = frame_off; | |
10134 | proc_rootP->proc_pcreg = pcreg; | |
10135 | /* bob macho .frame */ | |
10136 | ||
10137 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 10138 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
10139 | { |
10140 | if (!proc_lastP) | |
10141 | as_warn ("No .ent for .frame to use."); | |
10142 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
10143 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
10144 | S_SET_TYPE (symP, N_RMASK); | |
10145 | S_SET_OTHER (symP, 0); | |
10146 | S_SET_DESC (symP, 0); | |
10147 | symP->sy_forward = proc_lastP->proc_isym; | |
10148 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10149 | } |
670a50eb | 10150 | demand_empty_rest_of_line (); |
3d3c5039 | 10151 | } |
88225433 | 10152 | #endif |
3d3c5039 ILT |
10153 | |
10154 | /* The .fmask and .mask directives. */ | |
10155 | ||
88225433 | 10156 | #if 0 |
3d3c5039 ILT |
10157 | static void |
10158 | s_mask (reg_type) | |
10159 | char reg_type; | |
10160 | { | |
670a50eb ILT |
10161 | char str[100], *strP; |
10162 | symbolS *symP; | |
10163 | int i; | |
10164 | unsigned int mask; | |
10165 | int off; | |
10166 | ||
10167 | mask = get_number (); | |
10168 | if (*input_line_pointer == ',') | |
10169 | input_line_pointer++; | |
10170 | off = get_absolute_expression (); | |
10171 | ||
10172 | /* bob only for coff */ | |
10173 | assert (proc_rootP); | |
10174 | if (reg_type == 'F') | |
10175 | { | |
10176 | proc_rootP->proc_fpreg_mask = mask; | |
10177 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 10178 | } |
670a50eb ILT |
10179 | else |
10180 | { | |
10181 | proc_rootP->proc_reg_mask = mask; | |
10182 | proc_rootP->proc_reg_offset = off; | |
10183 | } | |
10184 | ||
10185 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 10186 | |
670a50eb ILT |
10187 | /* We don't have to write out a mask stab if no saved regs. */ |
10188 | if (!(mask == 0)) | |
10189 | { | |
10190 | if (!proc_lastP) | |
10191 | as_warn ("No .ent for .mask to use."); | |
10192 | strP = str; | |
10193 | for (i = 0; i < 32; i++) | |
10194 | { | |
10195 | if (mask % 2) | |
10196 | { | |
10197 | sprintf (strP, "%c%d,", reg_type, i); | |
10198 | strP += strlen (strP); | |
10199 | } | |
3d3c5039 | 10200 | mask /= 2; |
670a50eb ILT |
10201 | } |
10202 | sprintf (strP, ";%d,", off); | |
10203 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
10204 | S_SET_TYPE (symP, N_RMASK); | |
10205 | S_SET_OTHER (symP, 0); | |
10206 | S_SET_DESC (symP, 0); | |
10207 | symP->sy_forward = proc_lastP->proc_isym; | |
10208 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 10209 | } |
3d3c5039 | 10210 | } |
88225433 | 10211 | #endif |
3d3c5039 ILT |
10212 | |
10213 | /* The .loc directive. */ | |
10214 | ||
88225433 | 10215 | #if 0 |
3d3c5039 ILT |
10216 | static void |
10217 | s_loc (x) | |
10218 | int x; | |
10219 | { | |
670a50eb ILT |
10220 | symbolS *symbolP; |
10221 | int lineno; | |
10222 | int addroff; | |
3d3c5039 | 10223 | |
670a50eb | 10224 | assert (now_seg == text_section); |
3d3c5039 | 10225 | |
670a50eb | 10226 | lineno = get_number (); |
87e48495 | 10227 | addroff = frag_now_fix (); |
3d3c5039 | 10228 | |
670a50eb ILT |
10229 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
10230 | S_SET_TYPE (symbolP, N_SLINE); | |
10231 | S_SET_OTHER (symbolP, 0); | |
10232 | S_SET_DESC (symbolP, lineno); | |
10233 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 10234 | } |
88225433 | 10235 | #endif |