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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
65d2c7d3 | 2 | Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
a3e8c5b7 | 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
739708fa KR |
64 | |
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
f2a663d3 | 72 | #include "elf/mips.h" |
1dc1e798 | 73 | #endif |
f2a663d3 | 74 | |
739708fa | 75 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 76 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
77 | #define ECOFF_DEBUGGING 0 |
78 | #endif | |
79 | ||
22ba90ce ILT |
80 | #include "ecoff.h" |
81 | ||
a8aed9dd | 82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 83 | static char *mips_regmask_frag; |
a8aed9dd | 84 | #endif |
f2a663d3 | 85 | |
3d3c5039 | 86 | #define AT 1 |
cc5703cd | 87 | #define TREG 24 |
9226253a | 88 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
89 | #define KT0 26 |
90 | #define KT1 27 | |
670a50eb | 91 | #define GP 28 |
9226253a ILT |
92 | #define SP 29 |
93 | #define FP 30 | |
3d3c5039 ILT |
94 | #define RA 31 |
95 | ||
cc5703cd ILT |
96 | #define ILLEGAL_REG (32) |
97 | ||
af942793 SS |
98 | /* Allow override of standard little-endian ECOFF format. */ |
99 | ||
100 | #ifndef ECOFF_LITTLE_FORMAT | |
101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
102 | #endif | |
103 | ||
1dc1e798 | 104 | extern int target_big_endian; |
88225433 | 105 | |
7f9880e5 | 106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
6fd819cf GRK |
107 | 32 bit ABI. This has no meaning for ECOFF. |
108 | Note that the default is always 32 bit, even if "configured" for | |
109 | 64 bit [e.g. --target=mips64-elf]. */ | |
7f9880e5 ILT |
110 | static int mips_64; |
111 | ||
04cb3372 | 112 | /* The default target format to use. */ |
1dc1e798 KR |
113 | const char * |
114 | mips_target_format () | |
115 | { | |
116 | switch (OUTPUT_FLAVOR) | |
117 | { | |
118 | case bfd_target_aout_flavour: | |
119 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
120 | case bfd_target_ecoff_flavour: | |
af942793 | 121 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 122 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
123 | return (target_big_endian |
124 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
125 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
126 | default: |
127 | abort (); | |
a3e8c5b7 | 128 | return NULL; |
1dc1e798 KR |
129 | } |
130 | } | |
04cb3372 | 131 | |
d2c71068 | 132 | /* The name of the readonly data section. */ |
1dc1e798 KR |
133 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
134 | ? ".data" \ | |
135 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
136 | ? ".rdata" \ | |
137 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
138 | ? ".rodata" \ | |
139 | : (abort (), "")) | |
d2c71068 | 140 | |
3c83da8a JW |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
145 | struct mips_set_options | |
146 | { | |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
151 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
152 | not, 1 if we are, and -1 if the value has not been initialized. | |
153 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
154 | -nomips16 command line options, and the default CPU. */ | |
155 | int mips16; | |
156 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
157 | reorder' and `.set noreorder'. */ | |
158 | int noreorder; | |
159 | /* Non-zero if we should not permit the $at ($1) register to be used | |
160 | in instructions. Changed by `.set at' and `.set noat'. */ | |
161 | int noat; | |
162 | /* Non-zero if we should warn when a macro instruction expands into | |
163 | more than one machine instruction. Changed by `.set nomacro' and | |
164 | `.set macro'. */ | |
165 | int warn_about_macros; | |
166 | /* Non-zero if we should not move instructions. Changed by `.set | |
167 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
168 | int nomove; | |
169 | /* Non-zero if we should not optimize branches by moving the target | |
170 | of the branch into the delay slot. Actually, we don't perform | |
171 | this optimization anyhow. Changed by `.set bopt' and `.set | |
172 | nobopt'. */ | |
173 | int nobopt; | |
174 | /* Non-zero if we should not autoextend mips16 instructions. | |
175 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
176 | int noautoextend; | |
177 | }; | |
178 | ||
179 | /* This is the struct we use to hold the current set of options. Note | |
180 | that we must set the isa and mips16 fields to -1 to indicate that | |
181 | they have not been initialized. */ | |
182 | ||
183 | static struct mips_set_options mips_opts = { -1, -1 }; | |
184 | ||
1aa6938e ILT |
185 | /* These variables are filled in with the masks of registers used. |
186 | The object format code reads them and puts them in the appropriate | |
187 | place. */ | |
188 | unsigned long mips_gprmask; | |
189 | unsigned long mips_cprmask[4]; | |
190 | ||
1051c97f ILT |
191 | /* MIPS ISA we are using for this output file. */ |
192 | static int file_mips_isa; | |
193 | ||
8c63448a | 194 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 195 | static int mips_cpu = -1; |
8c63448a | 196 | |
b2b8c24e ILT |
197 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
198 | static int mips_4650 = -1; | |
199 | ||
e532b44c ILT |
200 | /* Whether the 4010 instructions are permitted. */ |
201 | static int mips_4010 = -1; | |
202 | ||
c625fc23 JSC |
203 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
204 | static int mips_4100 = -1; | |
205 | ||
2d035a50 GRK |
206 | /* start-sanitize-vr4320 */ |
207 | /* Whether NEC vr4320 instructions are permitted. */ | |
208 | static int mips_4320 = -1; | |
209 | ||
210 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
211 | /* start-sanitize-vr5400 */ |
212 | /* Whether NEC vr5400 instructions are permitted. */ | |
213 | static int mips_5400 = -1; | |
214 | ||
215 | /* end-sanitize-vr5400 */ | |
276c2d7d GRK |
216 | /* start-sanitize-r5900 */ |
217 | /* Whether Toshiba r5900 instructions are permitted. */ | |
218 | static int mips_5900 = -1; | |
276c2d7d | 219 | |
aa2e0460 | 220 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
221 | /* Whether Toshiba r3900 instructions are permitted. */ |
222 | static int mips_3900 = -1; | |
223 | ||
42444087 GRK |
224 | /* start-sanitize-tx49 */ |
225 | /* Whether Toshiba r4900 instructions are permitted. */ | |
226 | static int mips_4900 = -1; | |
227 | ||
228 | /* end-sanitize-tx49 */ | |
4e96260f JL |
229 | /* start-sanitize-tx19 */ |
230 | /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it. | |
231 | The tx19 related options and configuration bits are handled by | |
232 | the tx39 flags. */ | |
233 | /* end-sanitize-tx19 */ | |
234 | ||
5c6f5923 GRK |
235 | /* Whether the processor uses hardware interlocks to protect |
236 | reads from the HI and LO registers, and thus does not | |
237 | require nops to be inserted. */ | |
4ebda395 GRK |
238 | #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \ |
239 | /* start-sanitize-tx49 */ \ | |
42444087 | 240 | || mips_cpu == 4900 || mips_4900 \ |
4ebda395 | 241 | /* end-sanitize-tx49 */ \ |
2d035a50 GRK |
242 | /* start-sanitize-vr4320 */ \ |
243 | || mips_cpu == 4320 \ | |
244 | /* end-sanitize-vr4320 */ \ | |
b3ed1af3 KR |
245 | /* start-sanitize-vr5400 */ \ |
246 | || mips_cpu == 5400 \ | |
247 | /* end-sanitize-vr5400 */ \ | |
4ebda395 | 248 | ) |
5c6f5923 | 249 | |
a3e8c5b7 ILT |
250 | /* Whether the processor uses hardware interlocks to protect reads |
251 | from the GPRs, and thus does not require nops to be inserted. */ | |
252 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900) | |
1c6f3441 ILT |
253 | /* start-sanitize-vr5400 */ |
254 | #undef gpr_interlocks | |
255 | #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400) | |
256 | /* end-sanitize-vr5400 */ | |
257 | ||
e532b44c | 258 | |
5c6f5923 | 259 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 260 | (co-processor) interlocks. */ |
efec4a28 | 261 | /* Itbl support may require additional care here. */ |
2d035a50 GRK |
262 | #define cop_interlocks (mips_cpu == 4300 \ |
263 | /* start-sanitize-vr4320 */ \ | |
264 | || mips_cpu == 4320 \ | |
265 | /* end-sanitize-vr4320 */ \ | |
266 | /* start-sanitize-vr5400 */ \ | |
267 | || mips_cpu == 5400 \ | |
268 | /* end-sanitize-vr5400 */ \ | |
269 | ) | |
344a8d61 | 270 | |
d9aba805 ILT |
271 | /* MIPS PIC level. */ |
272 | ||
273 | enum mips_pic_level | |
274 | { | |
275 | /* Do not generate PIC code. */ | |
276 | NO_PIC, | |
277 | ||
278 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
279 | not sure what it is supposed to do. */ | |
280 | IRIX4_PIC, | |
281 | ||
282 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
283 | SVR4_PIC, | |
284 | ||
285 | /* Generate PIC code without using a global offset table: the data | |
286 | segment has a maximum size of 64K, all data references are off | |
287 | the $gp register, and all text references are PC relative. This | |
288 | is used on some embedded systems. */ | |
289 | EMBEDDED_PIC | |
290 | }; | |
291 | ||
292 | static enum mips_pic_level mips_pic; | |
9226253a | 293 | |
fb251650 ILT |
294 | /* 1 if we should generate 32 bit offsets from the GP register in |
295 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
296 | static int mips_big_got; | |
297 | ||
8ea7f4e8 ILT |
298 | /* 1 if trap instructions should used for overflow rather than break |
299 | instructions. */ | |
300 | static int mips_trap; | |
301 | ||
3c83da8a | 302 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 303 | |
0dd2d296 | 304 | static int mips_any_noreorder; |
3d3c5039 | 305 | |
670a50eb ILT |
306 | /* The size of the small data section. */ |
307 | static int g_switch_value = 8; | |
42562568 ILT |
308 | /* Whether the -G option was used. */ |
309 | static int g_switch_seen = 0; | |
670a50eb | 310 | |
3d3c5039 ILT |
311 | #define N_RMASK 0xc4 |
312 | #define N_VFP 0xd4 | |
313 | ||
d8a1c247 KR |
314 | /* If we can determine in advance that GP optimization won't be |
315 | possible, we can skip the relaxation stuff that tries to produce | |
316 | GP-relative references. This makes delay slot optimization work | |
317 | better. | |
318 | ||
319 | This function can only provide a guess, but it seems to work for | |
320 | gcc output. If it guesses wrong, the only loss should be in | |
321 | efficiency; it shouldn't introduce any bugs. | |
322 | ||
323 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
324 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 325 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 326 | |
3d3c5039 ILT |
327 | /* handle of the OPCODE hash table */ |
328 | static struct hash_control *op_hash = NULL; | |
329 | ||
cc5703cd ILT |
330 | /* The opcode hash table we use for the mips16. */ |
331 | static struct hash_control *mips16_op_hash = NULL; | |
332 | ||
3d3c5039 ILT |
333 | /* This array holds the chars that always start a comment. If the |
334 | pre-processor is disabled, these aren't very useful */ | |
335 | const char comment_chars[] = "#"; | |
336 | ||
337 | /* This array holds the chars that only start a comment at the beginning of | |
338 | a line. If the line seems to have the form '# 123 filename' | |
339 | .line and .file directives will appear in the pre-processed output */ | |
340 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
341 | first line of the input file. This is because the compiler outputs | |
342 | #NO_APP at the beginning of its output. */ | |
343 | /* Also note that C style comments are always supported. */ | |
344 | const char line_comment_chars[] = "#"; | |
345 | ||
346 | /* This array holds machine specific line separator characters. */ | |
347 | const char line_separator_chars[] = ""; | |
348 | ||
349 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
350 | const char EXP_CHARS[] = "eE"; | |
351 | ||
352 | /* Chars that mean this number is a floating point constant */ | |
353 | /* As in 0f12.456 */ | |
354 | /* or 0d1.2345e12 */ | |
355 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
356 | ||
357 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
358 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
359 | but nothing is ideal around here. | |
360 | */ | |
361 | ||
670a50eb | 362 | static char *insn_error; |
3d3c5039 | 363 | |
3d3c5039 | 364 | static int auto_align = 1; |
becfe05e | 365 | |
9226253a ILT |
366 | /* When outputting SVR4 PIC code, the assembler needs to know the |
367 | offset in the stack frame from which to restore the $gp register. | |
368 | This is set by the .cprestore pseudo-op, and saved in this | |
369 | variable. */ | |
0dd2d296 ILT |
370 | static offsetT mips_cprestore_offset = -1; |
371 | ||
372 | /* This is the register which holds the stack frame, as set by the | |
373 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
374 | static int mips_frame_reg = SP; | |
9226253a | 375 | |
becfe05e ILT |
376 | /* To output NOP instructions correctly, we need to keep information |
377 | about the previous two instructions. */ | |
378 | ||
0aa07269 ILT |
379 | /* Whether we are optimizing. The default value of 2 means to remove |
380 | unneeded NOPs and swap branch instructions when possible. A value | |
381 | of 1 means to not swap branches. A value of 0 means to always | |
382 | insert NOPs. */ | |
383 | static int mips_optimize = 2; | |
4e95866e | 384 | |
22ba90ce ILT |
385 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
386 | equivalent to seeing no -g option at all. */ | |
387 | static int mips_debug = 0; | |
388 | ||
becfe05e ILT |
389 | /* The previous instruction. */ |
390 | static struct mips_cl_insn prev_insn; | |
391 | ||
392 | /* The instruction before prev_insn. */ | |
393 | static struct mips_cl_insn prev_prev_insn; | |
394 | ||
395 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
396 | point the insn_mo field at this dummy integer. */ | |
397 | static const struct mips_opcode dummy_opcode = { 0 }; | |
398 | ||
399 | /* Non-zero if prev_insn is valid. */ | |
400 | static int prev_insn_valid; | |
401 | ||
402 | /* The frag for the previous instruction. */ | |
403 | static struct frag *prev_insn_frag; | |
404 | ||
405 | /* The offset into prev_insn_frag for the previous instruction. */ | |
406 | static long prev_insn_where; | |
407 | ||
a677feeb ILT |
408 | /* The reloc type for the previous instruction, if any. */ |
409 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
410 | ||
becfe05e ILT |
411 | /* The reloc for the previous instruction, if any. */ |
412 | static fixS *prev_insn_fixp; | |
413 | ||
414 | /* Non-zero if the previous instruction was in a delay slot. */ | |
415 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
416 | |
417 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
418 | static int prev_insn_unreordered; | |
419 | ||
cc5703cd ILT |
420 | /* Non-zero if the previous instruction uses an extend opcode (if |
421 | mips16). */ | |
422 | static int prev_insn_extended; | |
423 | ||
4e95866e ILT |
424 | /* Non-zero if the previous previous instruction was in a .set |
425 | noreorder. */ | |
426 | static int prev_prev_insn_unreordered; | |
867a58b3 | 427 | |
4a1cb507 ILT |
428 | /* If this is set, it points to a frag holding nop instructions which |
429 | were inserted before the start of a noreorder section. If those | |
430 | nops turn out to be unnecessary, the size of the frag can be | |
431 | decreased. */ | |
432 | static fragS *prev_nop_frag; | |
433 | ||
434 | /* The number of nop instructions we created in prev_nop_frag. */ | |
435 | static int prev_nop_frag_holds; | |
436 | ||
437 | /* The number of nop instructions that we know we need in | |
438 | prev_nop_frag. */ | |
439 | static int prev_nop_frag_required; | |
440 | ||
441 | /* The number of instructions we've seen since prev_nop_frag. */ | |
442 | static int prev_nop_frag_since; | |
443 | ||
867a58b3 ILT |
444 | /* For ECOFF and ELF, relocations against symbols are done in two |
445 | parts, with a HI relocation and a LO relocation. Each relocation | |
446 | has only 16 bits of space to store an addend. This means that in | |
447 | order for the linker to handle carries correctly, it must be able | |
448 | to locate both the HI and the LO relocation. This means that the | |
449 | relocations must appear in order in the relocation table. | |
450 | ||
451 | In order to implement this, we keep track of each unmatched HI | |
452 | relocation. We then sort them so that they immediately precede the | |
453 | corresponding LO relocation. */ | |
454 | ||
455 | struct mips_hi_fixup | |
456 | { | |
457 | /* Next HI fixup. */ | |
458 | struct mips_hi_fixup *next; | |
459 | /* This fixup. */ | |
460 | fixS *fixp; | |
461 | /* The section this fixup is in. */ | |
462 | segT seg; | |
463 | }; | |
464 | ||
465 | /* The list of unmatched HI relocs. */ | |
466 | ||
467 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
468 | |
469 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
470 | ||
471 | #define X ILLEGAL_REG | |
472 | static const int mips32_to_16_reg_map[] = | |
473 | { | |
474 | X, X, 2, 3, 4, 5, 6, 7, | |
475 | X, X, X, X, X, X, X, X, | |
476 | 0, 1, X, X, X, X, X, X, | |
477 | X, X, X, X, X, X, X, X | |
478 | }; | |
479 | #undef X | |
480 | ||
481 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
482 | ||
483 | static const int mips16_to_32_reg_map[] = | |
484 | { | |
485 | 16, 17, 2, 3, 4, 5, 6, 7 | |
486 | }; | |
3d3c5039 | 487 | \f |
0dd2d296 ILT |
488 | /* Since the MIPS does not have multiple forms of PC relative |
489 | instructions, we do not have to do relaxing as is done on other | |
490 | platforms. However, we do have to handle GP relative addressing | |
491 | correctly, which turns out to be a similar problem. | |
492 | ||
493 | Every macro that refers to a symbol can occur in (at least) two | |
494 | forms, one with GP relative addressing and one without. For | |
495 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 496 | a macro instruction like this: |
0dd2d296 ILT |
497 | lw $4,i |
498 | If i can be addressed off the GP register (this is true if it is in | |
499 | the .sbss or .sdata section, or if it is known to be smaller than | |
500 | the -G argument) this will generate the following instruction: | |
501 | lw $4,i($gp) | |
502 | This instruction will use a GPREL reloc. If i can not be addressed | |
503 | off the GP register, the following instruction sequence will be used: | |
504 | lui $at,i | |
505 | lw $4,i($at) | |
506 | In this case the first instruction will have a HI16 reloc, and the | |
507 | second reloc will have a LO16 reloc. Both relocs will be against | |
508 | the symbol i. | |
509 | ||
510 | The issue here is that we may not know whether i is GP addressable | |
511 | until after we see the instruction that uses it. Therefore, we | |
512 | want to be able to choose the final instruction sequence only at | |
513 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 514 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
515 | end of assembly. |
516 | ||
517 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
518 | addressing in quite the same way, but the issue still arises as |
519 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
520 | |
521 | We handle these issues by actually generating both possible | |
522 | instruction sequences. The longer one is put in a frag_var with | |
523 | type rs_machine_dependent. We encode what to do with the frag in | |
524 | the subtype field. We encode (1) the number of existing bytes to | |
525 | replace, (2) the number of new bytes to use, (3) the offset from | |
526 | the start of the existing bytes to the first reloc we must generate | |
527 | (that is, the offset is applied from the start of the existing | |
528 | bytes after they are replaced by the new bytes, if any), (4) the | |
529 | offset from the start of the existing bytes to the second reloc, | |
530 | (5) whether a third reloc is needed (the third reloc is always four | |
531 | bytes after the second reloc), and (6) whether to warn if this | |
532 | variant is used (this is sometimes needed if .set nomacro or .set | |
533 | noat is in effect). All these numbers are reasonably small. | |
534 | ||
535 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
536 | ensure that delay slots are handled correctly. Fortunately, there |
537 | are a limited number of cases. When the second instruction | |
538 | sequence is generated, append_insn is directed to maintain the | |
539 | existing delay slot information, so it continues to apply to any | |
540 | code after the second instruction sequence. This means that the | |
541 | second instruction sequence must not impose any requirements not | |
542 | required by the first instruction sequence. | |
0dd2d296 ILT |
543 | |
544 | These variant frags are then handled in functions called by the | |
545 | machine independent code. md_estimate_size_before_relax returns | |
546 | the final size of the frag. md_convert_frag sets up the final form | |
547 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
548 | one if needed. */ | |
549 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
550 | ((relax_substateT) \ | |
cc5703cd | 551 | (((old) << 23) \ |
0dd2d296 ILT |
552 | | ((new) << 16) \ |
553 | | (((reloc1) + 64) << 9) \ | |
554 | | (((reloc2) + 64) << 2) \ | |
555 | | ((reloc3) ? (1 << 1) : 0) \ | |
556 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
557 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
558 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
559 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
560 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
561 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
562 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
563 | |
564 | /* For mips16 code, we use an entirely different form of relaxation. | |
565 | mips16 supports two versions of most instructions which take | |
566 | immediate values: a small one which takes some small value, and a | |
567 | larger one which takes a 16 bit value. Since branches also follow | |
568 | this pattern, relaxing these values is required. | |
569 | ||
570 | We can assemble both mips16 and normal MIPS code in a single | |
571 | object. Therefore, we need to support this type of relaxation at | |
572 | the same time that we support the relaxation described above. We | |
573 | use the high bit of the subtype field to distinguish these cases. | |
574 | ||
a677feeb ILT |
575 | The information we store for this type of relaxation is the |
576 | argument code found in the opcode file for this relocation, whether | |
577 | the user explicitly requested a small or extended form, and whether | |
578 | the relocation is in a jump or jal delay slot. That tells us the | |
579 | size of the value, and how it should be stored. We also store | |
580 | whether the fragment is considered to be extended or not. We also | |
581 | store whether this is known to be a branch to a different section, | |
582 | whether we have tried to relax this frag yet, and whether we have | |
583 | ever extended a PC relative fragment because of a shift count. */ | |
584 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
585 | (0x80000000 \ | |
586 | | ((type) & 0xff) \ | |
587 | | ((small) ? 0x100 : 0) \ | |
588 | | ((ext) ? 0x200 : 0) \ | |
589 | | ((dslot) ? 0x400 : 0) \ | |
590 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
591 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
592 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
593 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
594 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
595 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
596 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
597 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
598 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
599 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
600 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
601 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
602 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 603 | \f |
3d3c5039 ILT |
604 | /* Prototypes for static functions. */ |
605 | ||
606 | #ifdef __STDC__ | |
607 | #define internalError() \ | |
608 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
609 | #else | |
610 | #define internalError() as_fatal ("MIPS internal Error"); | |
611 | #endif | |
612 | ||
cc5703cd ILT |
613 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
614 | ||
becfe05e | 615 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 616 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 617 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 618 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
619 | static void append_insn PARAMS ((char *place, |
620 | struct mips_cl_insn * ip, | |
670a50eb | 621 | expressionS * p, |
867a58b3 ILT |
622 | bfd_reloc_code_real_type r, |
623 | boolean)); | |
4a1cb507 | 624 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 625 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 626 | #ifdef USE_STDARG |
0dd2d296 | 627 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
628 | const char *name, const char *fmt, |
629 | ...)); | |
c625fc23 JSC |
630 | #else |
631 | static void macro_build (); | |
632 | #endif | |
cc5703cd ILT |
633 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
634 | const char *, const char *, | |
635 | va_list)); | |
0dd2d296 ILT |
636 | static void macro_build_lui PARAMS ((char *place, int *counter, |
637 | expressionS * ep, int regnum)); | |
6e8dda9c | 638 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 639 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 640 | expressionS *)); |
d8a1c247 | 641 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 642 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 643 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 644 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
645 | #ifdef LOSING_COMPILER |
646 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
647 | #endif | |
670a50eb | 648 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 649 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
650 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
651 | boolean, boolean, unsigned long *, | |
652 | boolean *, unsigned short *)); | |
670a50eb ILT |
653 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
654 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 655 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 656 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
657 | static void s_align PARAMS ((int)); |
658 | static void s_change_sec PARAMS ((int)); | |
659 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 660 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 661 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
662 | static void s_option PARAMS ((int)); |
663 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
664 | static void s_abicalls PARAMS ((int)); |
665 | static void s_cpload PARAMS ((int)); | |
666 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
667 | static void s_gpword PARAMS ((int)); |
668 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 669 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
670 | static void md_obj_begin PARAMS ((void)); |
671 | static void md_obj_end PARAMS ((void)); | |
672 | static long get_number PARAMS ((void)); | |
673 | static void s_ent PARAMS ((int)); | |
674 | static void s_mipsend PARAMS ((int)); | |
675 | static void s_file PARAMS ((int)); | |
3c83da8a | 676 | static void s_mips_stab PARAMS ((int)); |
cc5703cd | 677 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
aa2e0460 KR |
678 | |
679 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); | |
3d3c5039 ILT |
680 | \f |
681 | /* Pseudo-op table. | |
682 | ||
683 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
684 | should be defined here, but are currently unsupported: .alias, | |
685 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
686 | ||
687 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
688 | specific to the type of debugging information being generated, and | |
689 | should be defined by the object format: .aent, .begin, .bend, | |
690 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
691 | .vreg. | |
692 | ||
693 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
694 | not MIPS CPU specific, but are also not specific to the object file | |
695 | format. This file is probably the best place to define them, but | |
696 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
697 | .struct, .weakext. */ | |
698 | ||
739708fa | 699 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 700 | { |
670a50eb ILT |
701 | /* MIPS specific pseudo-ops. */ |
702 | {"option", s_option, 0}, | |
703 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
704 | {"rdata", s_change_sec, 'r'}, |
705 | {"sdata", s_change_sec, 's'}, | |
706 | {"livereg", s_ignore, 0}, | |
739708fa KR |
707 | {"abicalls", s_abicalls, 0}, |
708 | {"cpload", s_cpload, 0}, | |
709 | {"cprestore", s_cprestore, 0}, | |
710 | {"gpword", s_gpword, 0}, | |
711 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 712 | {"insn", s_insn, 0}, |
3d3c5039 | 713 | |
670a50eb | 714 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 715 | chips. */ |
739708fa | 716 | {"asciiz", stringer, 1}, |
670a50eb ILT |
717 | {"bss", s_change_sec, 'b'}, |
718 | {"err", s_err, 0}, | |
719 | {"half", s_cons, 1}, | |
52aa70b5 | 720 | {"dword", s_cons, 3}, |
3d3c5039 | 721 | |
670a50eb | 722 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 723 | here for one reason or another. */ |
670a50eb ILT |
724 | {"align", s_align, 0}, |
725 | {"byte", s_cons, 0}, | |
726 | {"data", s_change_sec, 'd'}, | |
becfe05e | 727 | {"double", s_float_cons, 'd'}, |
becfe05e | 728 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
729 | {"globl", s_mips_globl, 0}, |
730 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
731 | {"hword", s_cons, 1}, |
732 | {"int", s_cons, 2}, | |
733 | {"long", s_cons, 2}, | |
734 | {"octa", s_cons, 4}, | |
735 | {"quad", s_cons, 3}, | |
736 | {"short", s_cons, 1}, | |
737 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 738 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
739 | {"text", s_change_sec, 't'}, |
740 | {"word", s_cons, 2}, | |
739708fa KR |
741 | { 0 }, |
742 | }; | |
3d3c5039 | 743 | |
739708fa | 744 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 745 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 746 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 747 | {"aent", s_ent, 1}, |
9226253a | 748 | {"bgnb", s_ignore, 0}, |
670a50eb | 749 | {"end", s_mipsend, 0}, |
9226253a | 750 | {"endb", s_ignore, 0}, |
670a50eb ILT |
751 | {"ent", s_ent, 0}, |
752 | {"file", s_file, 0}, | |
753 | {"fmask", s_ignore, 'F'}, | |
754 | {"frame", s_ignore, 0}, | |
755 | {"loc", s_ignore, 0}, | |
756 | {"mask", s_ignore, 'R'}, | |
757 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
758 | { 0 }, |
759 | }; | |
61420a20 | 760 | |
739708fa KR |
761 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
762 | ||
763 | void | |
764 | mips_pop_insert () | |
765 | { | |
766 | pop_insert (mips_pseudo_table); | |
767 | if (! ECOFF_DEBUGGING) | |
768 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 769 | } |
3d3c5039 | 770 | \f |
fbcfacb7 ILT |
771 | /* Symbols labelling the current insn. */ |
772 | ||
773 | struct insn_label_list | |
774 | { | |
775 | struct insn_label_list *next; | |
776 | symbolS *label; | |
777 | }; | |
778 | ||
779 | static struct insn_label_list *insn_labels; | |
780 | static struct insn_label_list *free_insn_labels; | |
781 | ||
782 | static void mips_clear_insn_labels PARAMS ((void)); | |
783 | ||
784 | static inline void | |
785 | mips_clear_insn_labels () | |
786 | { | |
787 | register struct insn_label_list **pl; | |
788 | ||
789 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
790 | ; | |
791 | *pl = insn_labels; | |
792 | insn_labels = NULL; | |
793 | } | |
794 | \f | |
3d3c5039 ILT |
795 | static char *expr_end; |
796 | ||
867a58b3 ILT |
797 | /* Expressions which appear in instructions. These are set by |
798 | mips_ip. */ | |
799 | ||
3d3c5039 ILT |
800 | static expressionS imm_expr; |
801 | static expressionS offset_expr; | |
867a58b3 ILT |
802 | |
803 | /* Relocs associated with imm_expr and offset_expr. */ | |
804 | ||
3d3c5039 ILT |
805 | static bfd_reloc_code_real_type imm_reloc; |
806 | static bfd_reloc_code_real_type offset_reloc; | |
807 | ||
867a58b3 ILT |
808 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
809 | ||
810 | static boolean imm_unmatched_hi; | |
811 | ||
8728fa92 ILT |
812 | /* These are set by mips16_ip if an explicit extension is used. */ |
813 | ||
814 | static boolean mips16_small, mips16_ext; | |
815 | ||
3d3c5039 ILT |
816 | /* |
817 | * This function is called once, at assembler startup time. It should | |
818 | * set up all the tables, etc. that the MD part of the assembler will need. | |
819 | */ | |
820 | void | |
670a50eb | 821 | md_begin () |
3d3c5039 | 822 | { |
0dd2d296 | 823 | boolean ok = false; |
604633ae | 824 | register const char *retval = NULL; |
670a50eb | 825 | register unsigned int i = 0; |
1724c79e GRK |
826 | const char *cpu; |
827 | char *a = NULL; | |
aa2e0460 | 828 | int broken = 0; |
3d3c5039 | 829 | |
1724c79e GRK |
830 | cpu = TARGET_CPU; |
831 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
8358c818 | 832 | { |
1724c79e GRK |
833 | a = xmalloc (sizeof TARGET_CPU); |
834 | strcpy (a, TARGET_CPU); | |
835 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
836 | cpu = a; | |
837 | } | |
8c63448a | 838 | |
1724c79e GRK |
839 | if (mips_cpu < 0) |
840 | { | |
841 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
842 | just the generic 'mips', in which case set mips_cpu based | |
843 | on the given ISA, if any. */ | |
8c63448a ILT |
844 | |
845 | if (strcmp (cpu, "mips") == 0) | |
1724c79e GRK |
846 | { |
847 | if (mips_opts.isa < 0) | |
848 | mips_cpu = 3000; | |
849 | ||
850 | else if (mips_opts.isa == 2) | |
851 | mips_cpu = 6000; | |
852 | ||
853 | else if (mips_opts.isa == 3) | |
854 | mips_cpu = 4000; | |
855 | ||
856 | else if (mips_opts.isa == 4) | |
857 | mips_cpu = 8000; | |
858 | ||
859 | else | |
860 | mips_cpu = 3000; | |
861 | } | |
862 | ||
5c6f5923 | 863 | else if (strcmp (cpu, "r3900") == 0 |
6fd819cf | 864 | || strcmp (cpu, "mipstx39") == 0 |
4e96260f JL |
865 | /* start-sanitize-tx19 */ |
866 | || strcmp (cpu, "r1900") == 0 | |
867 | || strcmp (cpu, "mipstx19") == 0 | |
868 | /* end-sanitize-tx19 */ | |
869 | ) | |
1724c79e GRK |
870 | mips_cpu = 3900; |
871 | ||
8c63448a ILT |
872 | else if (strcmp (cpu, "r6000") == 0 |
873 | || strcmp (cpu, "mips2") == 0) | |
1724c79e GRK |
874 | mips_cpu = 6000; |
875 | ||
8c63448a ILT |
876 | else if (strcmp (cpu, "mips64") == 0 |
877 | || strcmp (cpu, "r4000") == 0 | |
878 | || strcmp (cpu, "mips3") == 0) | |
1724c79e GRK |
879 | mips_cpu = 4000; |
880 | ||
8c63448a | 881 | else if (strcmp (cpu, "r4400") == 0) |
1724c79e GRK |
882 | mips_cpu = 4400; |
883 | ||
8c63448a ILT |
884 | else if (strcmp (cpu, "mips64orion") == 0 |
885 | || strcmp (cpu, "r4600") == 0) | |
1724c79e GRK |
886 | mips_cpu = 4600; |
887 | ||
b2b8c24e | 888 | else if (strcmp (cpu, "r4650") == 0) |
1724c79e GRK |
889 | mips_cpu = 4650; |
890 | ||
c625fc23 | 891 | else if (strcmp (cpu, "mips64vr4300") == 0) |
1724c79e GRK |
892 | mips_cpu = 4300; |
893 | ||
2d035a50 GRK |
894 | /* start-sanitize-vr4320 */ |
895 | else if (strcmp (cpu, "r4320") == 0 | |
896 | || strcmp (cpu, "mips64vr4320") == 0) | |
897 | mips_cpu = 4320; | |
898 | ||
899 | /* end-sanitize-vr4320 */ | |
b073d428 ILT |
900 | else if (strcmp (cpu, "mips64vr4100") == 0 |
901 | /* start-sanitize-vr4111 */ | |
902 | || strcmp (cpu, "mips64vr4111") == 0 | |
903 | /* end-sanitize-vr4111 */ | |
904 | ) | |
1724c79e GRK |
905 | mips_cpu = 4100; |
906 | ||
e532b44c | 907 | else if (strcmp (cpu, "r4010") == 0) |
1724c79e GRK |
908 | mips_cpu = 4010; |
909 | ||
4ebda395 GRK |
910 | /* start-sanitize-tx49 */ |
911 | else if (strcmp (cpu, "mips64tx49") == 0) | |
1724c79e | 912 | mips_cpu = 4900; |
4ebda395 | 913 | /* end-sanitize-tx49 */ |
1724c79e | 914 | |
517078c1 ILT |
915 | else if (strcmp (cpu, "r5000") == 0 |
916 | || strcmp (cpu, "mips64vr5000") == 0) | |
1724c79e GRK |
917 | mips_cpu = 5000; |
918 | ||
aa2e0460 KR |
919 | /* start-sanitize-vr5400 */ |
920 | else if (strcmp (cpu, "r5400") == 0 | |
b3ed1af3 KR |
921 | || strcmp (cpu, "mips64vr5400") == 0) |
922 | mips_cpu = 5400; | |
aa2e0460 | 923 | /* end-sanitize-vr5400 */ |
1724c79e | 924 | |
276c2d7d GRK |
925 | /* start-sanitize-r5900 */ |
926 | else if (strcmp (cpu, "r5900") == 0 | |
1724c79e GRK |
927 | || strcmp (cpu, "mips64r5900") == 0) |
928 | mips_cpu = 5900; | |
276c2d7d | 929 | /* end-sanitize-r5900 */ |
1724c79e | 930 | |
d8a1c247 KR |
931 | else if (strcmp (cpu, "r8000") == 0 |
932 | || strcmp (cpu, "mips4") == 0) | |
1724c79e GRK |
933 | mips_cpu = 8000; |
934 | ||
d8a1c247 | 935 | else if (strcmp (cpu, "r10000") == 0) |
1724c79e GRK |
936 | mips_cpu = 10000; |
937 | ||
cc5703cd | 938 | else if (strcmp (cpu, "mips16") == 0) |
1724c79e GRK |
939 | mips_cpu = 0; /* FIXME */ |
940 | ||
8358c818 | 941 | else |
1724c79e GRK |
942 | mips_cpu = 3000; |
943 | } | |
8c63448a | 944 | |
1724c79e GRK |
945 | if (mips_opts.isa == -1) |
946 | { | |
947 | if (mips_cpu == 3000 | |
948 | || mips_cpu == 3900) | |
949 | mips_opts.isa = 1; | |
950 | ||
951 | else if (mips_cpu == 6000 | |
952 | || mips_cpu == 4010) | |
953 | mips_opts.isa = 2; | |
954 | ||
955 | else if (mips_cpu == 4000 | |
956 | || mips_cpu == 4100 | |
957 | || mips_cpu == 4400 | |
958 | || mips_cpu == 4300 | |
2d035a50 GRK |
959 | /* start-sanitize-vr4320 */ |
960 | || mips_cpu == 4320 | |
961 | /* end-sanitize-4320 */ | |
1724c79e GRK |
962 | || mips_cpu == 4600 |
963 | /* start-sanitize-tx49 */ | |
964 | || mips_cpu == 4900 | |
965 | /* end-sanitize-tx49 */ | |
966 | /* start-sanitize-r5900 */ | |
967 | || mips_cpu == 5900 | |
968 | /* end-sanitize-r5900 */ | |
969 | || mips_cpu == 4650) | |
970 | mips_opts.isa = 3; | |
971 | ||
972 | else if (mips_cpu == 5000 | |
973 | /* start-sanitize-vr5400 */ | |
974 | || mips_cpu == 5400 | |
975 | /* end-sanitize-vr5400 */ | |
976 | || mips_cpu == 8000 | |
977 | || mips_cpu == 10000) | |
978 | mips_opts.isa = 4; | |
979 | ||
980 | else | |
981 | mips_opts.isa = 1; | |
8358c818 ILT |
982 | } |
983 | ||
3c83da8a | 984 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
985 | { |
986 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 987 | mips_opts.mips16 = 1; |
cc5703cd | 988 | else |
3c83da8a | 989 | mips_opts.mips16 = 0; |
cc5703cd ILT |
990 | } |
991 | ||
b2b8c24e | 992 | if (mips_4650 < 0) |
1724c79e | 993 | mips_4650 = (mips_cpu == 4650); |
b2b8c24e | 994 | |
e532b44c | 995 | if (mips_4010 < 0) |
1724c79e | 996 | mips_4010 = (mips_cpu == 4010); |
e532b44c | 997 | |
c625fc23 | 998 | if (mips_4100 < 0) |
1724c79e | 999 | mips_4100 = (mips_cpu == 4100); |
c625fc23 | 1000 | |
2d035a50 GRK |
1001 | /* start-sanitize-vr4320 */ |
1002 | if (mips_4320 < 0) | |
1003 | mips_4320 = (mips_cpu == 4320); | |
1004 | ||
1005 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
1006 | /* start-sanitize-vr5400 */ |
1007 | if (mips_5400 < 0) | |
1724c79e | 1008 | mips_5400 = (mips_cpu == 5400); |
aa2e0460 | 1009 | /* end-sanitize-vr5400 */ |
1724c79e | 1010 | |
276c2d7d GRK |
1011 | /* start-sanitize-r5900 */ |
1012 | if (mips_5900 < 0) | |
1724c79e | 1013 | mips_5900 = (mips_cpu == 5900); |
aa2e0460 | 1014 | /* end-sanitize-r5900 */ |
1724c79e | 1015 | |
5c6f5923 | 1016 | if (mips_3900 < 0) |
1724c79e GRK |
1017 | mips_3900 = (mips_cpu == 3900); |
1018 | ||
42444087 GRK |
1019 | /* start-sanitize-tx49 */ |
1020 | if (mips_4900 < 0) | |
1021 | mips_4900 = (mips_cpu == 4900); | |
1724c79e | 1022 | |
42444087 | 1023 | /* end-sanitize-tx49 */ |
1724c79e GRK |
1024 | |
1025 | /* End of TARGET_CPU processing, get rid of malloced memory | |
1026 | if necessary. */ | |
1027 | cpu = NULL; | |
1028 | if (a != NULL) | |
1029 | { | |
1030 | free (a); | |
1031 | a = NULL; | |
1032 | } | |
1033 | ||
3c83da8a | 1034 | if (mips_opts.isa < 2 && mips_trap) |
8ea7f4e8 ILT |
1035 | as_bad ("trap exception not supported at ISA 1"); |
1036 | ||
9a1f3160 | 1037 | if (mips_cpu != 0 && mips_cpu != -1) |
97f99d11 | 1038 | { |
9a1f3160 JL |
1039 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); |
1040 | } | |
1041 | else | |
1042 | { | |
1043 | switch (mips_opts.isa) | |
1044 | { | |
1045 | case 1: | |
1046 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1047 | break; | |
1048 | case 2: | |
1049 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1050 | break; | |
1051 | case 3: | |
1052 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1053 | break; | |
1054 | case 4: | |
1055 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1056 | break; | |
1057 | } | |
97f99d11 | 1058 | } |
9a1f3160 | 1059 | |
97f99d11 ILT |
1060 | if (! ok) |
1061 | as_warn ("Could not set architecture and machine"); | |
1062 | ||
3c83da8a | 1063 | file_mips_isa = mips_opts.isa; |
1051c97f | 1064 | |
13fe1379 ILT |
1065 | op_hash = hash_new (); |
1066 | ||
670a50eb ILT |
1067 | for (i = 0; i < NUMOPCODES;) |
1068 | { | |
1069 | const char *name = mips_opcodes[i].name; | |
1070 | ||
604633ae | 1071 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 1072 | if (retval != NULL) |
670a50eb ILT |
1073 | { |
1074 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
1075 | mips_opcodes[i].name, retval); | |
aa2e0460 | 1076 | /* Probably a memory allocation problem? Give up now. */ |
670a50eb ILT |
1077 | as_fatal ("Broken assembler. No assembly attempted."); |
1078 | } | |
1079 | do | |
1080 | { | |
aa2e0460 | 1081 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
670a50eb | 1082 | { |
aa2e0460 KR |
1083 | if (!validate_mips_insn (&mips_opcodes[i])) |
1084 | broken = 1; | |
3d3c5039 | 1085 | } |
670a50eb ILT |
1086 | ++i; |
1087 | } | |
1088 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1089 | } |
1090 | ||
cc5703cd ILT |
1091 | mips16_op_hash = hash_new (); |
1092 | ||
1093 | i = 0; | |
1094 | while (i < bfd_mips16_num_opcodes) | |
1095 | { | |
1096 | const char *name = mips16_opcodes[i].name; | |
1097 | ||
1098 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1099 | if (retval != NULL) | |
aa2e0460 | 1100 | as_fatal ("internal: can't hash `%s': %s", |
cc5703cd ILT |
1101 | mips16_opcodes[i].name, retval); |
1102 | do | |
1103 | { | |
1104 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1105 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1106 | != mips16_opcodes[i].match)) | |
aa2e0460 KR |
1107 | { |
1108 | fprintf (stderr, "internal error: bad mips16 opcode: %s %s\n", | |
1109 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1110 | broken = 1; | |
1111 | } | |
cc5703cd ILT |
1112 | ++i; |
1113 | } | |
1114 | while (i < bfd_mips16_num_opcodes | |
1115 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1116 | } | |
1117 | ||
aa2e0460 KR |
1118 | if (broken) |
1119 | as_fatal ("Broken assembler. No assembly attempted."); | |
1120 | ||
ebf28372 ILT |
1121 | /* We add all the general register names to the symbol table. This |
1122 | helps us detect invalid uses of them. */ | |
1123 | for (i = 0; i < 32; i++) | |
1124 | { | |
1125 | char buf[5]; | |
1126 | ||
1127 | sprintf (buf, "$%d", i); | |
1128 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1129 | &zero_address_frag)); | |
1130 | } | |
1131 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1132 | &zero_address_frag)); | |
1133 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1134 | &zero_address_frag)); | |
1135 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1136 | &zero_address_frag)); | |
1137 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1138 | &zero_address_frag)); | |
1139 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1140 | &zero_address_frag)); | |
1141 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1142 | &zero_address_frag)); | |
1143 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1144 | &zero_address_frag)); | |
1145 | ||
4a1cb507 | 1146 | mips_no_prev_insn (false); |
becfe05e | 1147 | |
1aa6938e ILT |
1148 | mips_gprmask = 0; |
1149 | mips_cprmask[0] = 0; | |
1150 | mips_cprmask[1] = 0; | |
1151 | mips_cprmask[2] = 0; | |
1152 | mips_cprmask[3] = 0; | |
1153 | ||
8358c818 | 1154 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1155 | record_alignment (text_section, 2); |
8358c818 | 1156 | |
1dc1e798 KR |
1157 | if (USE_GLOBAL_POINTER_OPT) |
1158 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1159 | |
1dc1e798 KR |
1160 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1161 | { | |
08e17202 ILT |
1162 | /* On a native system, sections must be aligned to 16 byte |
1163 | boundaries. When configured for an embedded ELF target, we | |
1164 | don't bother. */ | |
1165 | if (strcmp (TARGET_OS, "elf") != 0) | |
1166 | { | |
1167 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1168 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1169 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1170 | } | |
1dc1e798 KR |
1171 | |
1172 | /* Create a .reginfo section for register masks and a .mdebug | |
1173 | section for debugging information. */ | |
1174 | { | |
1175 | segT seg; | |
1176 | subsegT subseg; | |
b3a64736 | 1177 | flagword flags; |
1dc1e798 KR |
1178 | segT sec; |
1179 | ||
1180 | seg = now_seg; | |
1181 | subseg = now_subseg; | |
1dc1e798 | 1182 | |
b3a64736 ILT |
1183 | /* The ABI says this section should be loaded so that the |
1184 | running program can access it. However, we don't load it | |
1185 | if we are configured for an embedded target */ | |
1186 | flags = SEC_READONLY | SEC_DATA; | |
1187 | if (strcmp (TARGET_OS, "elf") != 0) | |
1188 | flags |= SEC_ALLOC | SEC_LOAD; | |
1189 | ||
87178180 ILT |
1190 | if (! mips_64) |
1191 | { | |
1192 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1193 | |
b3a64736 ILT |
1194 | |
1195 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1196 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1197 | ||
f2a663d3 | 1198 | #ifdef OBJ_ELF |
87178180 | 1199 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1200 | #endif |
87178180 ILT |
1201 | } |
1202 | else | |
1203 | { | |
1204 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1205 | .reginfo section. */ | |
1206 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1207 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1208 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1209 | ||
1210 | #ifdef OBJ_ELF | |
1211 | /* Set up the option header. */ | |
1212 | { | |
1213 | Elf_Internal_Options opthdr; | |
1214 | char *f; | |
1215 | ||
1216 | opthdr.kind = ODK_REGINFO; | |
1217 | opthdr.size = (sizeof (Elf_External_Options) | |
1218 | + sizeof (Elf64_External_RegInfo)); | |
1219 | opthdr.section = 0; | |
1220 | opthdr.info = 0; | |
1221 | f = frag_more (sizeof (Elf_External_Options)); | |
1222 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1223 | (Elf_External_Options *) f); | |
1224 | ||
1225 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1226 | } | |
1227 | #endif | |
1228 | } | |
f2a663d3 | 1229 | |
739708fa KR |
1230 | if (ECOFF_DEBUGGING) |
1231 | { | |
1232 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1233 | (void) bfd_set_section_flags (stdoutput, sec, | |
1234 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1235 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1236 | } | |
0dd2d296 | 1237 | |
1dc1e798 KR |
1238 | subseg_set (seg, subseg); |
1239 | } | |
1240 | } | |
f2a663d3 | 1241 | |
739708fa KR |
1242 | if (! ECOFF_DEBUGGING) |
1243 | md_obj_begin (); | |
3d3c5039 ILT |
1244 | } |
1245 | ||
1246 | void | |
13fe1379 | 1247 | md_mips_end () |
3d3c5039 | 1248 | { |
739708fa KR |
1249 | if (! ECOFF_DEBUGGING) |
1250 | md_obj_end (); | |
3d3c5039 ILT |
1251 | } |
1252 | ||
1253 | void | |
670a50eb ILT |
1254 | md_assemble (str) |
1255 | char *str; | |
3d3c5039 | 1256 | { |
670a50eb | 1257 | struct mips_cl_insn insn; |
3d3c5039 | 1258 | |
5ac34ac3 | 1259 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1260 | imm_reloc = BFD_RELOC_UNUSED; |
1261 | imm_unmatched_hi = false; | |
5ac34ac3 | 1262 | offset_expr.X_op = O_absent; |
867a58b3 | 1263 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1264 | |
3c83da8a | 1265 | if (mips_opts.mips16) |
cc5703cd ILT |
1266 | mips16_ip (str, &insn); |
1267 | else | |
efec4a28 | 1268 | { |
9218cee0 | 1269 | mips_ip (str, &insn); |
efec4a28 DP |
1270 | DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", |
1271 | str, insn.insn_opcode)); | |
1272 | } | |
cc5703cd | 1273 | |
670a50eb ILT |
1274 | if (insn_error) |
1275 | { | |
1276 | as_bad ("%s `%s'", insn_error, str); | |
1277 | return; | |
1278 | } | |
cc5703cd | 1279 | |
670a50eb ILT |
1280 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1281 | { | |
3c83da8a | 1282 | if (mips_opts.mips16) |
cc5703cd ILT |
1283 | mips16_macro (&insn); |
1284 | else | |
1285 | macro (&insn); | |
3d3c5039 | 1286 | } |
670a50eb ILT |
1287 | else |
1288 | { | |
5ac34ac3 | 1289 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1290 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1291 | imm_unmatched_hi); | |
5ac34ac3 | 1292 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1293 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1294 | else |
867a58b3 | 1295 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1296 | } |
1297 | } | |
1298 | ||
cc5703cd ILT |
1299 | /* See whether instruction IP reads register REG. CLASS is the type |
1300 | of register. */ | |
becfe05e ILT |
1301 | |
1302 | static int | |
cc5703cd | 1303 | insn_uses_reg (ip, reg, class) |
becfe05e | 1304 | struct mips_cl_insn *ip; |
604633ae | 1305 | unsigned int reg; |
cc5703cd | 1306 | enum mips_regclass class; |
becfe05e | 1307 | { |
cc5703cd ILT |
1308 | if (class == MIPS16_REG) |
1309 | { | |
3c83da8a | 1310 | assert (mips_opts.mips16); |
cc5703cd ILT |
1311 | reg = mips16_to_32_reg_map[reg]; |
1312 | class = MIPS_GR_REG; | |
1313 | } | |
1314 | ||
becfe05e | 1315 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1316 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1317 | return 0; |
1318 | ||
cc5703cd | 1319 | if (class == MIPS_FP_REG) |
becfe05e | 1320 | { |
3c83da8a | 1321 | assert (! mips_opts.mips16); |
becfe05e ILT |
1322 | /* If we are called with either $f0 or $f1, we must check $f0. |
1323 | This is not optimal, because it will introduce an unnecessary | |
1324 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1325 | need to distinguish reading both $f0 and $f1 or just one of | |
1326 | them. Note that we don't have to check the other way, | |
1327 | because there is no instruction that sets both $f0 and $f1 | |
1328 | and requires a delay. */ | |
1329 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1330 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1331 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1332 | return 1; |
1333 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1334 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1335 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1336 | return 1; |
1337 | } | |
3c83da8a | 1338 | else if (! mips_opts.mips16) |
becfe05e ILT |
1339 | { |
1340 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1341 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1342 | return 1; | |
1343 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1344 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1345 | return 1; | |
1346 | } | |
cc5703cd ILT |
1347 | else |
1348 | { | |
1349 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1350 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1351 | & MIPS16OP_MASK_RX)] | |
1352 | == reg)) | |
cc5703cd ILT |
1353 | return 1; |
1354 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1355 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1356 | & MIPS16OP_MASK_RY)] | |
1357 | == reg)) | |
cc5703cd ILT |
1358 | return 1; |
1359 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1360 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1361 | & MIPS16OP_MASK_MOVE32Z)] | |
1362 | == reg)) | |
cc5703cd ILT |
1363 | return 1; |
1364 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1365 | return 1; | |
1366 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1367 | return 1; | |
1368 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1369 | return 1; | |
1370 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1371 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1372 | & MIPS16OP_MASK_REGR32) == reg) | |
1373 | return 1; | |
1374 | } | |
becfe05e ILT |
1375 | |
1376 | return 0; | |
1377 | } | |
1378 | ||
fb251650 ILT |
1379 | /* This function returns true if modifying a register requires a |
1380 | delay. */ | |
1381 | ||
1382 | static int | |
1383 | reg_needs_delay (reg) | |
1384 | int reg; | |
1385 | { | |
1386 | unsigned long prev_pinfo; | |
1387 | ||
1388 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1389 | if (! mips_opts.noreorder |
1390 | && mips_opts.isa < 4 | |
fb251650 | 1391 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1392 | || (! gpr_interlocks |
fb251650 ILT |
1393 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1394 | { | |
1395 | /* A load from a coprocessor or from memory. All load | |
1396 | delays delay the use of general register rt for one | |
1397 | instruction on the r3000. The r6000 and r4000 use | |
1398 | interlocks. */ | |
efec4a28 | 1399 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1400 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1401 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1402 | return 1; | |
1403 | } | |
1404 | ||
1405 | return 0; | |
1406 | } | |
1407 | ||
3c83da8a JW |
1408 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1409 | handle them specially, such as generating jalx instructions when | |
1410 | needed. We also make them odd for the duration of the assembly, in | |
1411 | order to generate the right sort of code. We will make them even | |
1412 | in the adjust_symtab routine, while leaving them marked. This is | |
1413 | convenient for the debugger and the disassembler. The linker knows | |
1414 | to make them odd again. */ | |
1415 | ||
1416 | static void | |
1417 | mips16_mark_labels () | |
1418 | { | |
1419 | if (mips_opts.mips16) | |
1420 | { | |
1421 | struct insn_label_list *l; | |
1422 | ||
1423 | for (l = insn_labels; l != NULL; l = l->next) | |
1424 | { | |
68952421 | 1425 | #ifdef OBJ_ELF |
3c83da8a JW |
1426 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1427 | S_SET_OTHER (l->label, STO_MIPS16); | |
1428 | #endif | |
1429 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1430 | ++l->label->sy_value.X_add_number; | |
1431 | } | |
1432 | } | |
1433 | } | |
1434 | ||
0dd2d296 ILT |
1435 | /* Output an instruction. PLACE is where to put the instruction; if |
1436 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1437 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1438 | used with RELOC_TYPE. */ | |
3d3c5039 | 1439 | |
3d3c5039 | 1440 | static void |
867a58b3 | 1441 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1442 | char *place; |
670a50eb ILT |
1443 | struct mips_cl_insn *ip; |
1444 | expressionS *address_expr; | |
1445 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1446 | boolean unmatched_hi; |
3d3c5039 | 1447 | { |
1aa6938e | 1448 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1449 | char *f; |
becfe05e ILT |
1450 | fixS *fixp; |
1451 | int nops = 0; | |
3d3c5039 | 1452 | |
3c83da8a JW |
1453 | /* Mark instruction labels in mips16 mode. */ |
1454 | if (mips_opts.mips16) | |
1455 | mips16_mark_labels (); | |
fbcfacb7 | 1456 | |
1aa6938e ILT |
1457 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1458 | pinfo = ip->insn_mo->pinfo; | |
1459 | ||
3c83da8a | 1460 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1461 | { |
4a1cb507 ILT |
1462 | int prev_prev_nop; |
1463 | ||
becfe05e | 1464 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1465 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1466 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1467 | (1) a load from memory delay |
1468 | (2) a load from a coprocessor delay | |
1469 | (3) an unconditional branch delay | |
1470 | (4) a conditional branch delay | |
1471 | (5) a move to coprocessor register delay | |
1472 | (6) a load coprocessor register from memory delay | |
1473 | (7) a coprocessor condition code delay | |
1474 | (8) a HI/LO special register delay | |
becfe05e ILT |
1475 | |
1476 | There are a lot of optimizations we could do that we don't. | |
1477 | In particular, we do not, in general, reorder instructions. | |
1478 | If you use gcc with optimization, it will reorder | |
1479 | instructions and generally do much more optimization then we | |
1480 | do here; repeating all that work in the assembler would only | |
1481 | benefit hand written assembly code, and does not seem worth | |
1482 | it. */ | |
1483 | ||
1484 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1485 | #define emit_nop() \ |
3c83da8a | 1486 | (mips_opts.mips16 \ |
cc5703cd ILT |
1487 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1488 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1489 | |
1490 | /* The previous insn might require a delay slot, depending upon | |
1491 | the contents of the current insn. */ | |
3c83da8a JW |
1492 | if (! mips_opts.mips16 |
1493 | && mips_opts.isa < 4 | |
5af96dce ILT |
1494 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1495 | && ! cop_interlocks) | |
5c6f5923 | 1496 | || (! gpr_interlocks |
d8a1c247 | 1497 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1498 | { |
1499 | /* A load from a coprocessor or from memory. All load | |
1500 | delays delay the use of general register rt for one | |
1501 | instruction on the r3000. The r6000 and r4000 use | |
1502 | interlocks. */ | |
efec4a28 | 1503 | /* Itbl support may require additional care here. */ |
1aa6938e | 1504 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1505 | if (mips_optimize == 0 |
1506 | || insn_uses_reg (ip, | |
1507 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1508 | & OP_MASK_RT), | |
cc5703cd | 1509 | MIPS_GR_REG)) |
becfe05e ILT |
1510 | ++nops; |
1511 | } | |
3c83da8a JW |
1512 | else if (! mips_opts.mips16 |
1513 | && mips_opts.isa < 4 | |
5af96dce ILT |
1514 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1515 | && ! cop_interlocks) | |
3c83da8a | 1516 | || (mips_opts.isa < 2 |
d8a1c247 | 1517 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1518 | { |
1519 | /* A generic coprocessor delay. The previous instruction | |
1520 | modified a coprocessor general or control register. If | |
1521 | it modified a control register, we need to avoid any | |
1522 | coprocessor instruction (this is probably not always | |
1523 | required, but it sometimes is). If it modified a general | |
1524 | register, we avoid using that register. | |
1525 | ||
8358c818 ILT |
1526 | On the r6000 and r4000 loading a coprocessor register |
1527 | from memory is interlocked, and does not require a delay. | |
1528 | ||
becfe05e ILT |
1529 | This case is not handled very well. There is no special |
1530 | knowledge of CP0 handling, and the coprocessors other | |
1531 | than the floating point unit are not distinguished at | |
1532 | all. */ | |
efec4a28 DP |
1533 | /* Itbl support may require additional care here. FIXME! |
1534 | Need to modify this to include knowledge about | |
1535 | user specified delays! */ | |
1aa6938e | 1536 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1537 | { |
0aa07269 ILT |
1538 | if (mips_optimize == 0 |
1539 | || insn_uses_reg (ip, | |
8358c818 ILT |
1540 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1541 | & OP_MASK_FT), | |
cc5703cd | 1542 | MIPS_FP_REG)) |
becfe05e ILT |
1543 | ++nops; |
1544 | } | |
1aa6938e | 1545 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1546 | { |
0aa07269 ILT |
1547 | if (mips_optimize == 0 |
1548 | || insn_uses_reg (ip, | |
8358c818 ILT |
1549 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1550 | & OP_MASK_FS), | |
cc5703cd | 1551 | MIPS_FP_REG)) |
becfe05e ILT |
1552 | ++nops; |
1553 | } | |
1554 | else | |
1555 | { | |
1556 | /* We don't know exactly what the previous instruction | |
1557 | does. If the current instruction uses a coprocessor | |
1558 | register, we must insert a NOP. If previous | |
1559 | instruction may set the condition codes, and the | |
1560 | current instruction uses them, we must insert two | |
1561 | NOPS. */ | |
efec4a28 | 1562 | /* Itbl support may require additional care here. */ |
0aa07269 | 1563 | if (mips_optimize == 0 |
1aa6938e ILT |
1564 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1565 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1566 | nops += 2; |
1aa6938e | 1567 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1568 | ++nops; |
1569 | } | |
1570 | } | |
3c83da8a JW |
1571 | else if (! mips_opts.mips16 |
1572 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1573 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1574 | && ! cop_interlocks) | |
becfe05e ILT |
1575 | { |
1576 | /* The previous instruction sets the coprocessor condition | |
1577 | codes, but does not require a general coprocessor delay | |
1578 | (this means it is a floating point comparison | |
1579 | instruction). If this instruction uses the condition | |
1580 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1581 | /* Itbl support may require additional care here. */ |
0aa07269 | 1582 | if (mips_optimize == 0 |
1aa6938e | 1583 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1584 | ++nops; |
1585 | } | |
1aa6938e | 1586 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1587 | { |
1588 | /* The previous instruction reads the LO register; if the | |
1589 | current instruction writes to the LO register, we must | |
517078c1 | 1590 | insert two NOPS. Some newer processors have interlocks. */ |
5c6f5923 | 1591 | if (! hilo_interlocks |
b2b8c24e ILT |
1592 | && (mips_optimize == 0 |
1593 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1594 | nops += 2; |
1595 | } | |
1596 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1597 | { | |
1598 | /* The previous instruction reads the HI register; if the | |
1599 | current instruction writes to the HI register, we must | |
517078c1 | 1600 | insert a NOP. Some newer processors have interlocks. */ |
5c6f5923 | 1601 | if (! hilo_interlocks |
b2b8c24e ILT |
1602 | && (mips_optimize == 0 |
1603 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1604 | nops += 2; |
1605 | } | |
1606 | ||
4a1cb507 ILT |
1607 | /* If the previous instruction was in a noreorder section, then |
1608 | we don't want to insert the nop after all. */ | |
efec4a28 | 1609 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1610 | if (prev_insn_unreordered) |
1611 | nops = 0; | |
1612 | ||
becfe05e ILT |
1613 | /* There are two cases which require two intervening |
1614 | instructions: 1) setting the condition codes using a move to | |
1615 | coprocessor instruction which requires a general coprocessor | |
1616 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1617 | or LO register and then writing to it (except on processors |
1618 | which have interlocks). If we are not already emitting a NOP | |
1619 | instruction, we must check for these cases compared to the | |
1620 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1621 | if ((! mips_opts.mips16 |
1622 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1623 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1624 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1625 | && (pinfo & INSN_READ_COND_CODE) | |
1626 | && ! cop_interlocks) | |
1627 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1628 | && (pinfo & INSN_WRITE_LO) | |
5c6f5923 | 1629 | && ! hilo_interlocks) |
4a1cb507 ILT |
1630 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1631 | && (pinfo & INSN_WRITE_HI) | |
5c6f5923 | 1632 | && ! hilo_interlocks)) |
4a1cb507 ILT |
1633 | prev_prev_nop = 1; |
1634 | else | |
1635 | prev_prev_nop = 0; | |
1636 | ||
1637 | if (prev_prev_insn_unreordered) | |
1638 | prev_prev_nop = 0; | |
1639 | ||
1640 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1641 | ++nops; |
1642 | ||
0dd2d296 ILT |
1643 | /* If we are being given a nop instruction, don't bother with |
1644 | one of the nops we would otherwise output. This will only | |
1645 | happen when a nop instruction is used with mips_optimize set | |
1646 | to 0. */ | |
4a1cb507 | 1647 | if (nops > 0 |
3c83da8a JW |
1648 | && ! mips_opts.noreorder |
1649 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1650 | --nops; |
1651 | ||
becfe05e | 1652 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1653 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1654 | { |
5af96dce ILT |
1655 | fragS *old_frag; |
1656 | unsigned long old_frag_offset; | |
8c63448a | 1657 | int i; |
fbcfacb7 | 1658 | struct insn_label_list *l; |
8c63448a | 1659 | |
5af96dce ILT |
1660 | old_frag = frag_now; |
1661 | old_frag_offset = frag_now_fix (); | |
1662 | ||
8c63448a | 1663 | for (i = 0; i < nops; i++) |
becfe05e | 1664 | emit_nop (); |
5af96dce | 1665 | |
af255ca0 | 1666 | if (listing) |
546f5536 ILT |
1667 | { |
1668 | listing_prev_line (); | |
1669 | /* We may be at the start of a variant frag. In case we | |
1670 | are, make sure there is enough space for the frag | |
1671 | after the frags created by listing_prev_line. The | |
1672 | argument to frag_grow here must be at least as large | |
1673 | as the argument to all other calls to frag_grow in | |
1674 | this file. We don't have to worry about being in the | |
1675 | middle of a variant frag, because the variants insert | |
1676 | all needed nop instructions themselves. */ | |
1677 | frag_grow (40); | |
1678 | } | |
5af96dce | 1679 | |
fbcfacb7 | 1680 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1681 | { |
fbcfacb7 ILT |
1682 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1683 | l->label->sy_frag = frag_now; | |
1684 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1685 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1686 | if (mips_opts.mips16) |
fbcfacb7 | 1687 | ++l->label->sy_value.X_add_number; |
becfe05e | 1688 | } |
5af96dce ILT |
1689 | |
1690 | #ifndef NO_ECOFF_DEBUGGING | |
1691 | if (ECOFF_DEBUGGING) | |
1692 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1693 | #endif | |
becfe05e | 1694 | } |
4a1cb507 ILT |
1695 | else if (prev_nop_frag != NULL) |
1696 | { | |
1697 | /* We have a frag holding nops we may be able to remove. If | |
1698 | we don't need any nops, we can decrease the size of | |
1699 | prev_nop_frag by the size of one instruction. If we do | |
1700 | need some nops, we count them in prev_nops_required. */ | |
1701 | if (prev_nop_frag_since == 0) | |
1702 | { | |
1703 | if (nops == 0) | |
1704 | { | |
3c83da8a | 1705 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1706 | --prev_nop_frag_holds; |
1707 | } | |
1708 | else | |
1709 | prev_nop_frag_required += nops; | |
1710 | } | |
1711 | else | |
1712 | { | |
1713 | if (prev_prev_nop == 0) | |
1714 | { | |
3c83da8a | 1715 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1716 | --prev_nop_frag_holds; |
1717 | } | |
1718 | else | |
1719 | ++prev_nop_frag_required; | |
1720 | } | |
1721 | ||
1722 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1723 | prev_nop_frag = NULL; | |
1724 | ||
1725 | ++prev_nop_frag_since; | |
1726 | ||
1727 | /* Sanity check: by the time we reach the second instruction | |
1728 | after prev_nop_frag, we should have used up all the nops | |
1729 | one way or another. */ | |
1730 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1731 | } | |
becfe05e | 1732 | } |
4a1cb507 | 1733 | |
cc5703cd ILT |
1734 | if (reloc_type > BFD_RELOC_UNUSED) |
1735 | { | |
1736 | /* We need to set up a variant frag. */ | |
3c83da8a | 1737 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1738 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1739 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1740 | mips16_small, mips16_ext, |
1741 | (prev_pinfo | |
1742 | & INSN_UNCOND_BRANCH_DELAY), | |
1743 | (prev_insn_reloc_type | |
1744 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1745 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1746 | (char *) NULL); |
1747 | } | |
1748 | else if (place != NULL) | |
0dd2d296 | 1749 | f = place; |
3c83da8a JW |
1750 | else if (mips_opts.mips16 |
1751 | && ! ip->use_extend | |
1752 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1753 | { |
1754 | /* Make sure there is enough room to swap this instruction with | |
1755 | a following jump instruction. */ | |
1756 | frag_grow (6); | |
1757 | f = frag_more (2); | |
1758 | } | |
cc5703cd | 1759 | else |
035936da | 1760 | { |
3c83da8a JW |
1761 | if (mips_opts.mips16 |
1762 | && mips_opts.noreorder | |
035936da ILT |
1763 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
1764 | as_warn ("extended instruction in delay slot"); | |
1765 | ||
1766 | f = frag_more (4); | |
1767 | } | |
1768 | ||
becfe05e | 1769 | fixp = NULL; |
cc5703cd | 1770 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1771 | { |
5ac34ac3 | 1772 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1773 | { |
1774 | switch (reloc_type) | |
1775 | { | |
3d3c5039 | 1776 | case BFD_RELOC_32: |
670a50eb ILT |
1777 | ip->insn_opcode |= address_expr->X_add_number; |
1778 | break; | |
3d3c5039 ILT |
1779 | |
1780 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1781 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1782 | break; | |
3d3c5039 ILT |
1783 | |
1784 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1785 | if ((address_expr->X_add_number & 3) != 0) |
1786 | as_bad ("jump to misaligned address (0x%lx)", | |
1787 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1788 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1789 | break; | |
1790 | ||
cc5703cd | 1791 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1792 | if ((address_expr->X_add_number & 3) != 0) |
1793 | as_bad ("jump to misaligned address (0x%lx)", | |
1794 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1795 | ip->insn_opcode |= |
1796 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1797 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1798 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1799 | break; | |
1800 | ||
3d3c5039 | 1801 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1802 | goto need_reloc; |
3d3c5039 ILT |
1803 | |
1804 | default: | |
670a50eb | 1805 | internalError (); |
3d3c5039 | 1806 | } |
670a50eb ILT |
1807 | } |
1808 | else | |
1809 | { | |
3d3c5039 | 1810 | need_reloc: |
0dd2d296 ILT |
1811 | /* Don't generate a reloc if we are writing into a variant |
1812 | frag. */ | |
1813 | if (place == NULL) | |
867a58b3 ILT |
1814 | { |
1815 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1816 | address_expr, | |
1817 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1818 | reloc_type); | |
1819 | if (unmatched_hi) | |
1820 | { | |
1821 | struct mips_hi_fixup *hi_fixup; | |
1822 | ||
1823 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1824 | hi_fixup = ((struct mips_hi_fixup *) | |
1825 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1826 | hi_fixup->fixp = fixp; | |
1827 | hi_fixup->seg = now_seg; | |
1828 | hi_fixup->next = mips_hi_fixup_list; | |
1829 | mips_hi_fixup_list = hi_fixup; | |
1830 | } | |
1831 | } | |
3d3c5039 ILT |
1832 | } |
1833 | } | |
becfe05e | 1834 | |
3c83da8a | 1835 | if (! mips_opts.mips16) |
cc5703cd | 1836 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1837 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1838 | { | |
1839 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1840 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1841 | } | |
cc5703cd ILT |
1842 | else |
1843 | { | |
1844 | if (ip->use_extend) | |
1845 | { | |
1846 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1847 | f += 2; | |
1848 | } | |
1849 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1850 | } | |
670a50eb | 1851 | |
1aa6938e | 1852 | /* Update the register mask information. */ |
3c83da8a | 1853 | if (! mips_opts.mips16) |
cc5703cd ILT |
1854 | { |
1855 | if (pinfo & INSN_WRITE_GPR_D) | |
1856 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1857 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1858 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1859 | if (pinfo & INSN_READ_GPR_S) | |
1860 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1861 | if (pinfo & INSN_WRITE_GPR_31) | |
1862 | mips_gprmask |= 1 << 31; | |
1863 | if (pinfo & INSN_WRITE_FPR_D) | |
1864 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1865 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1866 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1867 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1868 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1869 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1870 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1871 | if (pinfo & INSN_COP) | |
1872 | { | |
efec4a28 DP |
1873 | /* We don't keep enough information to sort these cases out. |
1874 | The itbl support does keep this information however, although | |
1875 | we currently don't support itbl fprmats as part of the cop | |
1876 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1877 | } |
1878 | /* Never set the bit for $0, which is always zero. */ | |
1879 | mips_gprmask &=~ 1 << 0; | |
1880 | } | |
1881 | else | |
1aa6938e | 1882 | { |
cc5703cd ILT |
1883 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1884 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1885 | & MIPS16OP_MASK_RX); | |
1886 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1887 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1888 | & MIPS16OP_MASK_RY); | |
1889 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1890 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1891 | & MIPS16OP_MASK_RZ); | |
1892 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1893 | mips_gprmask |= 1 << TREG; | |
1894 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1895 | mips_gprmask |= 1 << SP; | |
1896 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1897 | mips_gprmask |= 1 << RA; | |
1898 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1899 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1900 | if (pinfo & MIPS16_INSN_READ_Z) | |
1901 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1902 | & MIPS16OP_MASK_MOVE32Z); | |
1903 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1904 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1905 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1906 | } |
1aa6938e | 1907 | |
3c83da8a | 1908 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1909 | { |
becfe05e ILT |
1910 | /* Filling the branch delay slot is more complex. We try to |
1911 | switch the branch with the previous instruction, which we can | |
1912 | do if the previous instruction does not set up a condition | |
1913 | that the branch tests and if the branch is not itself the | |
1914 | target of any branch. */ | |
1aa6938e ILT |
1915 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1916 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1917 | { |
0aa07269 | 1918 | if (mips_optimize < 2 |
19ed8960 ILT |
1919 | /* If we have seen .set volatile or .set nomove, don't |
1920 | optimize. */ | |
3c83da8a | 1921 | || mips_opts.nomove != 0 |
4e95866e ILT |
1922 | /* If we had to emit any NOP instructions, then we |
1923 | already know we can not swap. */ | |
1924 | || nops != 0 | |
becfe05e ILT |
1925 | /* If we don't even know the previous insn, we can not |
1926 | swap. */ | |
1927 | || ! prev_insn_valid | |
1928 | /* If the previous insn is already in a branch delay | |
1929 | slot, then we can not swap. */ | |
1930 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1931 | /* If the previous previous insn was in a .set |
1932 | noreorder, we can't swap. Actually, the MIPS | |
1933 | assembler will swap in this situation. However, gcc | |
1934 | configured -with-gnu-as will generate code like | |
1935 | .set noreorder | |
1936 | lw $4,XXX | |
1937 | .set reorder | |
1938 | INSN | |
1939 | bne $4,$0,foo | |
1940 | in which we can not swap the bne and INSN. If gcc is | |
1941 | not configured -with-gnu-as, it does not output the | |
1942 | .set pseudo-ops. We don't have to check | |
1943 | prev_insn_unreordered, because prev_insn_valid will | |
1944 | be 0 in that case. We don't want to use | |
1945 | prev_prev_insn_valid, because we do want to be able | |
1946 | to swap at the start of a function. */ | |
1947 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1948 | /* If the branch is itself the target of a branch, we |
1949 | can not swap. We cheat on this; all we check for is | |
1950 | whether there is a label on this instruction. If | |
1951 | there are any branches to anything other than a | |
1952 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1953 | || insn_labels != NULL |
777ad64d | 1954 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1955 | can not do the swap. This does not apply to the |
1956 | mips16, which uses variant frags for different | |
1957 | purposes. */ | |
3c83da8a | 1958 | || (! mips_opts.mips16 |
cc5703cd | 1959 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
1960 | /* If the branch reads the condition codes, we don't |
1961 | even try to swap, because in the sequence | |
1962 | ctc1 $X,$31 | |
1963 | INSN | |
1964 | INSN | |
1965 | bc1t LABEL | |
1966 | we can not swap, and I don't feel like handling that | |
1967 | case. */ | |
3c83da8a JW |
1968 | || (! mips_opts.mips16 |
1969 | && mips_opts.isa < 4 | |
d8a1c247 | 1970 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1971 | /* We can not swap with an instruction that requires a |
1972 | delay slot, becase the target of the branch might | |
1973 | interfere with that instruction. */ | |
3c83da8a JW |
1974 | || (! mips_opts.mips16 |
1975 | && mips_opts.isa < 4 | |
d8a1c247 | 1976 | && (prev_pinfo |
efec4a28 | 1977 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1978 | & (INSN_LOAD_COPROC_DELAY |
1979 | | INSN_COPROC_MOVE_DELAY | |
1980 | | INSN_WRITE_COND_CODE))) | |
5c6f5923 | 1981 | || (! hilo_interlocks |
b2b8c24e ILT |
1982 | && (prev_pinfo |
1983 | & (INSN_READ_LO | |
1984 | | INSN_READ_HI))) | |
5c6f5923 GRK |
1985 | || (! mips_opts.mips16 |
1986 | && ! gpr_interlocks | |
1987 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
1988 | || (! mips_opts.mips16 |
1989 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
1990 | /* Itbl support may require additional care here. */ |
1991 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 1992 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1993 | || (prev_pinfo |
6e8dda9c ILT |
1994 | & (INSN_UNCOND_BRANCH_DELAY |
1995 | | INSN_COND_BRANCH_DELAY | |
1996 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1997 | /* We do not swap with a trap instruction, since it |
1998 | complicates trap handlers to have the trap | |
1999 | instruction be in a delay slot. */ | |
1aa6938e | 2000 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
2001 | /* If the branch reads a register that the previous |
2002 | instruction sets, we can not swap. */ | |
3c83da8a | 2003 | || (! mips_opts.mips16 |
cc5703cd | 2004 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
2005 | && insn_uses_reg (ip, |
2006 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2007 | & OP_MASK_RT), | |
cc5703cd | 2008 | MIPS_GR_REG)) |
3c83da8a | 2009 | || (! mips_opts.mips16 |
cc5703cd | 2010 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2011 | && insn_uses_reg (ip, |
2012 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2013 | & OP_MASK_RD), | |
cc5703cd | 2014 | MIPS_GR_REG)) |
3c83da8a | 2015 | || (mips_opts.mips16 |
cc5703cd ILT |
2016 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
2017 | && insn_uses_reg (ip, | |
2018 | ((prev_insn.insn_opcode | |
2019 | >> MIPS16OP_SH_RX) | |
2020 | & MIPS16OP_MASK_RX), | |
2021 | MIPS16_REG)) | |
2022 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2023 | && insn_uses_reg (ip, | |
2024 | ((prev_insn.insn_opcode | |
2025 | >> MIPS16OP_SH_RY) | |
2026 | & MIPS16OP_MASK_RY), | |
2027 | MIPS16_REG)) | |
2028 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2029 | && insn_uses_reg (ip, | |
2030 | ((prev_insn.insn_opcode | |
2031 | >> MIPS16OP_SH_RZ) | |
2032 | & MIPS16OP_MASK_RZ), | |
2033 | MIPS16_REG)) | |
2034 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2035 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2036 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2037 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2038 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2039 | && insn_uses_reg (ip, | |
2040 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2041 | insn_opcode), | |
2042 | MIPS_GR_REG)))) | |
1849d646 ILT |
2043 | /* If the branch writes a register that the previous |
2044 | instruction sets, we can not swap (we know that | |
2045 | branches write only to RD or to $31). */ | |
3c83da8a | 2046 | || (! mips_opts.mips16 |
cc5703cd | 2047 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 2048 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2049 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
2050 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2051 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2052 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
2053 | & OP_MASK_RT) | |
2054 | == 31)))) | |
3c83da8a | 2055 | || (! mips_opts.mips16 |
cc5703cd | 2056 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 2057 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
2058 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
2059 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 2060 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
2061 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
2062 | & OP_MASK_RD) | |
2063 | == 31)))) | |
3c83da8a | 2064 | || (mips_opts.mips16 |
cc5703cd ILT |
2065 | && (pinfo & MIPS16_INSN_WRITE_31) |
2066 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2067 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2068 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2069 | == RA)))) | |
becfe05e ILT |
2070 | /* If the branch writes a register that the previous |
2071 | instruction reads, we can not swap (we know that | |
2072 | branches only write to RD or to $31). */ | |
3c83da8a | 2073 | || (! mips_opts.mips16 |
cc5703cd | 2074 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
2075 | && insn_uses_reg (&prev_insn, |
2076 | ((ip->insn_opcode >> OP_SH_RD) | |
2077 | & OP_MASK_RD), | |
cc5703cd | 2078 | MIPS_GR_REG)) |
3c83da8a | 2079 | || (! mips_opts.mips16 |
cc5703cd ILT |
2080 | && (pinfo & INSN_WRITE_GPR_31) |
2081 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 2082 | || (mips_opts.mips16 |
cc5703cd ILT |
2083 | && (pinfo & MIPS16_INSN_WRITE_31) |
2084 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2085 | /* If we are generating embedded PIC code, the branch |
2086 | might be expanded into a sequence which uses $at, so | |
2087 | we can't swap with an instruction which reads it. */ | |
2088 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2089 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2090 | /* If the previous previous instruction has a load |
2091 | delay, and sets a register that the branch reads, we | |
2092 | can not swap. */ | |
3c83da8a JW |
2093 | || (! mips_opts.mips16 |
2094 | && mips_opts.isa < 4 | |
efec4a28 | 2095 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2096 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2097 | || (! gpr_interlocks |
d8a1c247 KR |
2098 | && (prev_prev_insn.insn_mo->pinfo |
2099 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2100 | && insn_uses_reg (ip, |
2101 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2102 | & OP_MASK_RT), | |
cc5703cd | 2103 | MIPS_GR_REG)) |
d31a3f5e ILT |
2104 | /* If one instruction sets a condition code and the |
2105 | other one uses a condition code, we can not swap. */ | |
2106 | || ((pinfo & INSN_READ_COND_CODE) | |
2107 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2108 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2109 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2110 | /* If the previous instruction uses the PC, we can not | |
2111 | swap. */ | |
3c83da8a | 2112 | || (mips_opts.mips16 |
cc5703cd ILT |
2113 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2114 | /* If the previous instruction was extended, we can not | |
2115 | swap. */ | |
3c83da8a | 2116 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2117 | /* If the previous instruction had a fixup in mips16 |
2118 | mode, we can not swap. This normally means that the | |
2119 | previous instruction was a 4 byte branch anyhow. */ | |
3c83da8a | 2120 | || (mips_opts.mips16 && prev_insn_fixp)) |
becfe05e ILT |
2121 | { |
2122 | /* We could do even better for unconditional branches to | |
2123 | portions of this object file; we could pick up the | |
2124 | instruction at the destination, put it in the delay | |
2125 | slot, and bump the destination address. */ | |
2126 | emit_nop (); | |
2127 | /* Update the previous insn information. */ | |
2128 | prev_prev_insn = *ip; | |
2129 | prev_insn.insn_mo = &dummy_opcode; | |
2130 | } | |
2131 | else | |
2132 | { | |
becfe05e | 2133 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2134 | if (! mips_opts.mips16) |
cc5703cd ILT |
2135 | { |
2136 | char *prev_f; | |
2137 | char temp[4]; | |
2138 | ||
2139 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2140 | memcpy (temp, prev_f, 4); | |
2141 | memcpy (prev_f, f, 4); | |
2142 | memcpy (f, temp, 4); | |
2143 | if (prev_insn_fixp) | |
2144 | { | |
2145 | prev_insn_fixp->fx_frag = frag_now; | |
2146 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2147 | } | |
2148 | if (fixp) | |
2149 | { | |
2150 | fixp->fx_frag = prev_insn_frag; | |
2151 | fixp->fx_where = prev_insn_where; | |
2152 | } | |
2153 | } | |
cc5703cd | 2154 | else |
becfe05e | 2155 | { |
cc5703cd ILT |
2156 | char *prev_f; |
2157 | char temp[2]; | |
2158 | ||
2159 | assert (prev_insn_fixp == NULL); | |
2160 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2161 | memcpy (temp, prev_f, 2); | |
2162 | memcpy (prev_f, f, 2); | |
2163 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2164 | { |
2165 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2166 | memcpy (f, temp, 2); | |
2167 | } | |
cc5703cd ILT |
2168 | else |
2169 | { | |
2170 | memcpy (f, f + 2, 2); | |
2171 | memcpy (f + 2, temp, 2); | |
2172 | } | |
2173 | if (fixp) | |
2174 | { | |
2175 | fixp->fx_frag = prev_insn_frag; | |
2176 | fixp->fx_where = prev_insn_where; | |
2177 | } | |
becfe05e | 2178 | } |
cc5703cd | 2179 | |
becfe05e ILT |
2180 | /* Update the previous insn information; leave prev_insn |
2181 | unchanged. */ | |
2182 | prev_prev_insn = *ip; | |
2183 | } | |
2184 | prev_insn_is_delay_slot = 1; | |
2185 | ||
2186 | /* If that was an unconditional branch, forget the previous | |
2187 | insn information. */ | |
1aa6938e | 2188 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2189 | { |
2190 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2191 | prev_insn.insn_mo = &dummy_opcode; | |
2192 | } | |
a677feeb ILT |
2193 | |
2194 | prev_insn_fixp = NULL; | |
2195 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2196 | prev_insn_extended = 0; | |
becfe05e | 2197 | } |
1aa6938e | 2198 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2199 | { |
2200 | /* We don't yet optimize a branch likely. What we should do | |
2201 | is look at the target, copy the instruction found there | |
2202 | into the delay slot, and increment the branch to jump to | |
2203 | the next instruction. */ | |
2204 | emit_nop (); | |
2205 | /* Update the previous insn information. */ | |
2206 | prev_prev_insn = *ip; | |
2207 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2208 | prev_insn_fixp = NULL; |
2209 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2210 | prev_insn_extended = 0; | |
8358c818 | 2211 | } |
becfe05e | 2212 | else |
670a50eb | 2213 | { |
becfe05e ILT |
2214 | /* Update the previous insn information. */ |
2215 | if (nops > 0) | |
2216 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2217 | else | |
2218 | prev_prev_insn = prev_insn; | |
2219 | prev_insn = *ip; | |
2220 | ||
2221 | /* Any time we see a branch, we always fill the delay slot | |
2222 | immediately; since this insn is not a branch, we know it | |
2223 | is not in a delay slot. */ | |
2224 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2225 | |
2226 | prev_insn_fixp = fixp; | |
2227 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2228 | if (mips_opts.mips16) |
a677feeb ILT |
2229 | prev_insn_extended = (ip->use_extend |
2230 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2231 | } |
2232 | ||
4e95866e ILT |
2233 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2234 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2235 | prev_insn_frag = frag_now; |
2236 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2237 | prev_insn_valid = 1; |
2238 | } | |
fbcfacb7 | 2239 | else if (place == NULL) |
a677feeb | 2240 | { |
fbcfacb7 | 2241 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2242 | reordering, in order to determine the base address for mips16 |
2243 | PC relative relocs. */ | |
4a1cb507 | 2244 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2245 | prev_insn = *ip; |
2246 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2247 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2248 | prev_insn_unreordered = 1; | |
a677feeb | 2249 | } |
3d3c5039 | 2250 | |
becfe05e | 2251 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2252 | mips_clear_insn_labels (); |
b073d428 ILT |
2253 | |
2254 | /* We must ensure that a fixup associated with an unmatched %hi | |
2255 | reloc does not become a variant frag. Otherwise, the | |
2256 | rearrangement of %hi relocs in frob_file may confuse | |
2257 | tc_gen_reloc. */ | |
2258 | if (unmatched_hi) | |
2259 | { | |
2260 | frag_wane (frag_now); | |
2261 | frag_new (0); | |
2262 | } | |
becfe05e ILT |
2263 | } |
2264 | ||
2265 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2266 | label. If PRESERVE is non-zero, it remembers enough information to |
2267 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2268 | |
2269 | static void | |
4a1cb507 ILT |
2270 | mips_no_prev_insn (preserve) |
2271 | int preserve; | |
becfe05e | 2272 | { |
4a1cb507 ILT |
2273 | if (! preserve) |
2274 | { | |
2275 | prev_insn.insn_mo = &dummy_opcode; | |
2276 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2277 | prev_nop_frag = NULL; | |
2278 | prev_nop_frag_holds = 0; | |
2279 | prev_nop_frag_required = 0; | |
2280 | prev_nop_frag_since = 0; | |
2281 | } | |
becfe05e ILT |
2282 | prev_insn_valid = 0; |
2283 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2284 | prev_insn_unreordered = 0; |
cc5703cd | 2285 | prev_insn_extended = 0; |
a677feeb | 2286 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2287 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2288 | mips_clear_insn_labels (); |
becfe05e ILT |
2289 | } |
2290 | ||
2291 | /* This function must be called whenever we turn on noreorder or emit | |
2292 | something other than instructions. It inserts any NOPS which might | |
2293 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2294 | kept for the previous instructions. The INSNS parameter is true if |
2295 | instructions are to follow. */ | |
becfe05e ILT |
2296 | |
2297 | static void | |
fbcfacb7 ILT |
2298 | mips_emit_delays (insns) |
2299 | boolean insns; | |
becfe05e | 2300 | { |
3c83da8a | 2301 | if (! mips_opts.noreorder) |
becfe05e | 2302 | { |
4a1cb507 | 2303 | int nops; |
becfe05e | 2304 | |
4a1cb507 | 2305 | nops = 0; |
3c83da8a JW |
2306 | if ((! mips_opts.mips16 |
2307 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2308 | && (! cop_interlocks |
2309 | && (prev_insn.insn_mo->pinfo | |
2310 | & (INSN_LOAD_COPROC_DELAY | |
2311 | | INSN_COPROC_MOVE_DELAY | |
2312 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2313 | || (! hilo_interlocks |
b2b8c24e ILT |
2314 | && (prev_insn.insn_mo->pinfo |
2315 | & (INSN_READ_LO | |
2316 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2317 | || (! mips_opts.mips16 |
2318 | && ! gpr_interlocks | |
2319 | && (prev_insn.insn_mo->pinfo | |
2320 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2321 | || (! mips_opts.mips16 |
2322 | && mips_opts.isa < 2 | |
8358c818 | 2323 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2324 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2325 | { |
efec4a28 | 2326 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2327 | ++nops; |
3c83da8a JW |
2328 | if ((! mips_opts.mips16 |
2329 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2330 | && (! cop_interlocks |
2331 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2332 | || (! hilo_interlocks |
b2b8c24e ILT |
2333 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2334 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2335 | ++nops; |
2336 | ||
2337 | if (prev_insn_unreordered) | |
2338 | nops = 0; | |
becfe05e | 2339 | } |
3c83da8a JW |
2340 | else if ((! mips_opts.mips16 |
2341 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2342 | && (! cop_interlocks |
2343 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2344 | || (! hilo_interlocks |
b2b8c24e ILT |
2345 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2346 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2347 | { |
efec4a28 | 2348 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2349 | if (! prev_prev_insn_unreordered) |
2350 | ++nops; | |
2351 | } | |
2352 | ||
2353 | if (nops > 0) | |
670a50eb | 2354 | { |
fbcfacb7 ILT |
2355 | struct insn_label_list *l; |
2356 | ||
4a1cb507 ILT |
2357 | if (insns) |
2358 | { | |
2359 | /* Record the frag which holds the nop instructions, so | |
2360 | that we can remove them if we don't need them. */ | |
3c83da8a | 2361 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2362 | prev_nop_frag = frag_now; |
2363 | prev_nop_frag_holds = nops; | |
2364 | prev_nop_frag_required = 0; | |
2365 | prev_nop_frag_since = 0; | |
2366 | } | |
2367 | ||
2368 | for (; nops > 0; --nops) | |
2369 | emit_nop (); | |
2370 | ||
2371 | if (insns) | |
2372 | { | |
2373 | /* Move on to a new frag, so that it is safe to simply | |
2374 | decrease the size of prev_nop_frag. */ | |
2375 | frag_wane (frag_now); | |
2376 | frag_new (0); | |
2377 | } | |
2378 | ||
fbcfacb7 | 2379 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2380 | { |
fbcfacb7 ILT |
2381 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2382 | l->label->sy_frag = frag_now; | |
2383 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2384 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2385 | if (mips_opts.mips16) |
fbcfacb7 | 2386 | ++l->label->sy_value.X_add_number; |
becfe05e | 2387 | } |
3d3c5039 ILT |
2388 | } |
2389 | } | |
0221ddf7 | 2390 | |
3c83da8a JW |
2391 | /* Mark instruction labels in mips16 mode. */ |
2392 | if (mips_opts.mips16 && insns) | |
2393 | mips16_mark_labels (); | |
fbcfacb7 | 2394 | |
4a1cb507 | 2395 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2396 | } |
2397 | ||
670a50eb ILT |
2398 | /* Build an instruction created by a macro expansion. This is passed |
2399 | a pointer to the count of instructions created so far, an | |
2400 | expression, the name of the instruction to build, an operand format | |
2401 | string, and corresponding arguments. */ | |
2402 | ||
1dc1e798 | 2403 | #ifdef USE_STDARG |
3d3c5039 | 2404 | static void |
0dd2d296 ILT |
2405 | macro_build (char *place, |
2406 | int *counter, | |
670a50eb | 2407 | expressionS * ep, |
3d3c5039 ILT |
2408 | const char *name, |
2409 | const char *fmt, | |
2410 | ...) | |
1dc1e798 | 2411 | #else |
3d3c5039 | 2412 | static void |
0dd2d296 ILT |
2413 | macro_build (place, counter, ep, name, fmt, va_alist) |
2414 | char *place; | |
3d3c5039 ILT |
2415 | int *counter; |
2416 | expressionS *ep; | |
2417 | const char *name; | |
2418 | const char *fmt; | |
2419 | va_dcl | |
1dc1e798 | 2420 | #endif |
3d3c5039 | 2421 | { |
670a50eb ILT |
2422 | struct mips_cl_insn insn; |
2423 | bfd_reloc_code_real_type r; | |
2424 | va_list args; | |
931a1858 | 2425 | int insn_isa; |
3d3c5039 | 2426 | |
1dc1e798 | 2427 | #ifdef USE_STDARG |
670a50eb | 2428 | va_start (args, fmt); |
3d3c5039 | 2429 | #else |
670a50eb | 2430 | va_start (args); |
3d3c5039 ILT |
2431 | #endif |
2432 | ||
670a50eb ILT |
2433 | /* |
2434 | * If the macro is about to expand into a second instruction, | |
2435 | * print a warning if needed. We need to pass ip as a parameter | |
2436 | * to generate a better warning message here... | |
2437 | */ | |
3c83da8a | 2438 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2439 | as_warn ("Macro instruction expanded into multiple instructions"); |
2440 | ||
0dd2d296 ILT |
2441 | if (place == NULL) |
2442 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2443 | |
3c83da8a | 2444 | if (mips_opts.mips16) |
cc5703cd ILT |
2445 | { |
2446 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2447 | va_end (args); | |
2448 | return; | |
2449 | } | |
2450 | ||
670a50eb ILT |
2451 | r = BFD_RELOC_UNUSED; |
2452 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2453 | assert (insn.insn_mo); | |
2454 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2455 | ||
931a1858 JL |
2456 | /* Search until we get a match for NAME. */ |
2457 | while (1) | |
670a50eb | 2458 | { |
1c6f3441 | 2459 | if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) |
931a1858 JL |
2460 | insn_isa = 1; |
2461 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) | |
2462 | insn_isa = 2; | |
2463 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) | |
2464 | insn_isa = 3; | |
2465 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) | |
2466 | insn_isa = 4; | |
2467 | else | |
2468 | insn_isa = 15; | |
2469 | ||
a652f74c ILT |
2470 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2471 | && insn.insn_mo->pinfo != INSN_MACRO | |
2472 | && (insn_isa <= mips_opts.isa | |
2473 | || (mips_4650 | |
2474 | && (insn.insn_mo->membership & INSN_4650) != 0) | |
2475 | || (mips_4010 | |
2476 | && (insn.insn_mo->membership & INSN_4010) != 0) | |
2477 | || (mips_4100 | |
2478 | && (insn.insn_mo->membership & INSN_4100) != 0) | |
2d035a50 GRK |
2479 | /* start-sanitize-vr4320 */ |
2480 | || (mips_4320 | |
2481 | && (insn.insn_mo->membership & INSN_4320) != 0) | |
2482 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
2483 | /* start-sanitize-tx49 */ |
2484 | || (mips_4900 | |
2485 | && (insn.insn_mo->membership & INSN_4900) != 0) | |
2486 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
2487 | /* start-sanitize-r5900 */ |
2488 | || (mips_5900 | |
2489 | && (insn.insn_mo->membership & INSN_5900) != 0) | |
2490 | /* end-sanitize-r5900 */ | |
aa2e0460 KR |
2491 | /* start-sanitize-vr5400 */ |
2492 | || (mips_5400 | |
2493 | && (insn.insn_mo->membership & INSN_5400) != 0) | |
2494 | /* end-sanitize-vr5400 */ | |
a652f74c ILT |
2495 | || (mips_3900 |
2496 | && (insn.insn_mo->membership & INSN_3900) != 0)) | |
2497 | /* start-sanitize-r5900 */ | |
2498 | && (! mips_5900 || (insn.insn_mo->pinfo & FP_D) == 0) | |
2499 | /* end-sanitize-r5900 */ | |
2500 | && (! mips_4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
2501 | break; | |
931a1858 | 2502 | |
a652f74c ILT |
2503 | ++insn.insn_mo; |
2504 | assert (insn.insn_mo->name); | |
2505 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 2506 | } |
931a1858 | 2507 | |
670a50eb ILT |
2508 | insn.insn_opcode = insn.insn_mo->match; |
2509 | for (;;) | |
2510 | { | |
2511 | switch (*fmt++) | |
2512 | { | |
3d3c5039 | 2513 | case '\0': |
670a50eb | 2514 | break; |
3d3c5039 ILT |
2515 | |
2516 | case ',': | |
2517 | case '(': | |
2518 | case ')': | |
670a50eb | 2519 | continue; |
3d3c5039 ILT |
2520 | |
2521 | case 't': | |
2522 | case 'w': | |
918692a5 | 2523 | case 'E': |
670a50eb ILT |
2524 | insn.insn_opcode |= va_arg (args, int) << 16; |
2525 | continue; | |
3d3c5039 ILT |
2526 | |
2527 | case 'c': | |
2528 | case 'T': | |
2529 | case 'W': | |
670a50eb ILT |
2530 | insn.insn_opcode |= va_arg (args, int) << 16; |
2531 | continue; | |
3d3c5039 ILT |
2532 | |
2533 | case 'd': | |
918692a5 | 2534 | case 'G': |
670a50eb ILT |
2535 | insn.insn_opcode |= va_arg (args, int) << 11; |
2536 | continue; | |
3d3c5039 ILT |
2537 | |
2538 | case 'V': | |
2539 | case 'S': | |
670a50eb ILT |
2540 | insn.insn_opcode |= va_arg (args, int) << 11; |
2541 | continue; | |
3d3c5039 | 2542 | |
ff3a5c18 ILT |
2543 | case 'z': |
2544 | continue; | |
2545 | ||
3d3c5039 | 2546 | case '<': |
670a50eb ILT |
2547 | insn.insn_opcode |= va_arg (args, int) << 6; |
2548 | continue; | |
3d3c5039 ILT |
2549 | |
2550 | case 'D': | |
670a50eb ILT |
2551 | insn.insn_opcode |= va_arg (args, int) << 6; |
2552 | continue; | |
3d3c5039 | 2553 | |
918692a5 ILT |
2554 | case 'B': |
2555 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2556 | continue; | |
2557 | ||
3d3c5039 ILT |
2558 | case 'b': |
2559 | case 's': | |
2560 | case 'r': | |
2561 | case 'v': | |
670a50eb ILT |
2562 | insn.insn_opcode |= va_arg (args, int) << 21; |
2563 | continue; | |
3d3c5039 ILT |
2564 | |
2565 | case 'i': | |
2566 | case 'j': | |
2567 | case 'o': | |
9226253a | 2568 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2569 | assert (r == BFD_RELOC_MIPS_GPREL |
2570 | || r == BFD_RELOC_MIPS_LITERAL | |
2571 | || r == BFD_RELOC_LO16 | |
2572 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2573 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2574 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2575 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2576 | || (ep->X_op == O_subtract |
2577 | && now_seg == text_section | |
ecd4ca1c | 2578 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2579 | continue; |
3d3c5039 | 2580 | |
6e8dda9c | 2581 | case 'u': |
ecd4ca1c ILT |
2582 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2583 | assert (ep != NULL | |
2584 | && (ep->X_op == O_constant | |
2585 | || (ep->X_op == O_symbol | |
2586 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2587 | || r == BFD_RELOC_HI16 |
2588 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2589 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2590 | || (ep->X_op == O_subtract |
2591 | && now_seg == text_section | |
ecd4ca1c ILT |
2592 | && r == BFD_RELOC_PCREL_HI16_S))); |
2593 | if (ep->X_op == O_constant) | |
2594 | { | |
2595 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2596 | ep = NULL; | |
2597 | r = BFD_RELOC_UNUSED; | |
2598 | } | |
6e8dda9c ILT |
2599 | continue; |
2600 | ||
3d3c5039 | 2601 | case 'p': |
670a50eb ILT |
2602 | assert (ep != NULL); |
2603 | /* | |
2604 | * This allows macro() to pass an immediate expression for | |
2605 | * creating short branches without creating a symbol. | |
2606 | * Note that the expression still might come from the assembly | |
2607 | * input, in which case the value is not checked for range nor | |
2608 | * is a relocation entry generated (yuck). | |
2609 | */ | |
5ac34ac3 | 2610 | if (ep->X_op == O_constant) |
670a50eb ILT |
2611 | { |
2612 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2613 | ep = NULL; | |
2614 | } | |
2615 | else | |
2616 | r = BFD_RELOC_16_PCREL_S2; | |
2617 | continue; | |
3d3c5039 | 2618 | |
9226253a ILT |
2619 | case 'a': |
2620 | assert (ep != NULL); | |
2621 | r = BFD_RELOC_MIPS_JMP; | |
2622 | continue; | |
2623 | ||
65d2c7d3 JL |
2624 | case 'C': |
2625 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2626 | continue; | |
2627 | ||
3d3c5039 | 2628 | default: |
670a50eb | 2629 | internalError (); |
3d3c5039 | 2630 | } |
670a50eb | 2631 | break; |
3d3c5039 | 2632 | } |
670a50eb ILT |
2633 | va_end (args); |
2634 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2635 | ||
867a58b3 | 2636 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2637 | } |
2638 | ||
cc5703cd ILT |
2639 | static void |
2640 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2641 | char *place; | |
2642 | int *counter; | |
2643 | expressionS *ep; | |
2644 | const char *name; | |
2645 | const char *fmt; | |
2646 | va_list args; | |
2647 | { | |
2648 | struct mips_cl_insn insn; | |
2649 | bfd_reloc_code_real_type r; | |
2650 | ||
2651 | r = BFD_RELOC_UNUSED; | |
2652 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2653 | assert (insn.insn_mo); | |
2654 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2655 | ||
2656 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2657 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2658 | { | |
2659 | ++insn.insn_mo; | |
2660 | assert (insn.insn_mo->name); | |
2661 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2662 | } | |
2663 | ||
2664 | insn.insn_opcode = insn.insn_mo->match; | |
2665 | insn.use_extend = false; | |
2666 | ||
2667 | for (;;) | |
2668 | { | |
2669 | int c; | |
2670 | ||
2671 | c = *fmt++; | |
2672 | switch (c) | |
2673 | { | |
2674 | case '\0': | |
2675 | break; | |
2676 | ||
2677 | case ',': | |
2678 | case '(': | |
2679 | case ')': | |
2680 | continue; | |
2681 | ||
2682 | case 'y': | |
2683 | case 'w': | |
2684 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2685 | continue; | |
2686 | ||
2687 | case 'x': | |
2688 | case 'v': | |
2689 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2690 | continue; | |
2691 | ||
2692 | case 'z': | |
2693 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2694 | continue; | |
2695 | ||
2696 | case 'Z': | |
2697 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2698 | continue; | |
2699 | ||
2700 | case '0': | |
2701 | case 'S': | |
2702 | case 'P': | |
2703 | case 'R': | |
2704 | continue; | |
2705 | ||
2706 | case 'X': | |
2707 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2708 | continue; | |
2709 | ||
2710 | case 'Y': | |
2711 | { | |
2712 | int regno; | |
2713 | ||
2714 | regno = va_arg (args, int); | |
2715 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2716 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2717 | } | |
2718 | continue; | |
2719 | ||
2720 | case '<': | |
2721 | case '>': | |
2722 | case '4': | |
2723 | case '5': | |
2724 | case 'H': | |
2725 | case 'W': | |
2726 | case 'D': | |
2727 | case 'j': | |
2728 | case '8': | |
2729 | case 'V': | |
2730 | case 'C': | |
2731 | case 'U': | |
2732 | case 'k': | |
2733 | case 'K': | |
2734 | case 'p': | |
2735 | case 'q': | |
2736 | { | |
2737 | assert (ep != NULL); | |
2738 | ||
2739 | if (ep->X_op != O_constant) | |
2740 | r = BFD_RELOC_UNUSED + c; | |
2741 | else | |
2742 | { | |
15e69f98 ILT |
2743 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2744 | false, false, &insn.insn_opcode, | |
2745 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2746 | ep = NULL; |
2747 | r = BFD_RELOC_UNUSED; | |
2748 | } | |
2749 | } | |
2750 | continue; | |
2751 | ||
2752 | case '6': | |
2753 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2754 | continue; | |
2755 | } | |
2756 | ||
2757 | break; | |
2758 | } | |
2759 | ||
2760 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2761 | ||
2762 | append_insn (place, &insn, ep, r, false); | |
2763 | } | |
2764 | ||
3d3c5039 ILT |
2765 | /* |
2766 | * Generate a "lui" instruction. | |
2767 | */ | |
2768 | static void | |
0dd2d296 ILT |
2769 | macro_build_lui (place, counter, ep, regnum) |
2770 | char *place; | |
3d3c5039 ILT |
2771 | int *counter; |
2772 | expressionS *ep; | |
2773 | int regnum; | |
2774 | { | |
670a50eb ILT |
2775 | expressionS high_expr; |
2776 | struct mips_cl_insn insn; | |
2777 | bfd_reloc_code_real_type r; | |
2778 | CONST char *name = "lui"; | |
2779 | CONST char *fmt = "t,u"; | |
2780 | ||
3c83da8a | 2781 | assert (! mips_opts.mips16); |
cc5703cd | 2782 | |
0dd2d296 ILT |
2783 | if (place == NULL) |
2784 | high_expr = *ep; | |
2785 | else | |
2786 | { | |
2787 | high_expr.X_op = O_constant; | |
fb251650 | 2788 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2789 | } |
670a50eb | 2790 | |
5ac34ac3 | 2791 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2792 | { |
2793 | /* we can compute the instruction now without a relocation entry */ | |
2794 | if (high_expr.X_add_number & 0x8000) | |
2795 | high_expr.X_add_number += 0x10000; | |
2796 | high_expr.X_add_number = | |
2797 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2798 | r = BFD_RELOC_UNUSED; | |
2799 | } | |
2800 | else | |
0dd2d296 ILT |
2801 | { |
2802 | assert (ep->X_op == O_symbol); | |
2803 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2804 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2805 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2806 | r = BFD_RELOC_HI16_S; | |
2807 | } | |
670a50eb ILT |
2808 | |
2809 | /* | |
2810 | * If the macro is about to expand into a second instruction, | |
2811 | * print a warning if needed. We need to pass ip as a parameter | |
2812 | * to generate a better warning message here... | |
2813 | */ | |
3c83da8a | 2814 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2815 | as_warn ("Macro instruction expanded into multiple instructions"); |
2816 | ||
0dd2d296 ILT |
2817 | if (place == NULL) |
2818 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2819 | |
2820 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2821 | assert (insn.insn_mo); | |
2822 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2823 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2824 | ||
0dd2d296 | 2825 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2826 | if (r == BFD_RELOC_UNUSED) |
2827 | { | |
2828 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2829 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2830 | } |
2831 | else | |
867a58b3 | 2832 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2833 | } |
2834 | ||
2835 | /* set_at() | |
2836 | * Generates code to set the $at register to true (one) | |
2837 | * if reg is less than the immediate expression. | |
2838 | */ | |
2839 | static void | |
6e8dda9c | 2840 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2841 | int *counter; |
2842 | int reg; | |
6e8dda9c | 2843 | int unsignedp; |
3d3c5039 | 2844 | { |
5c6f5923 GRK |
2845 | if (imm_expr.X_op == O_constant |
2846 | && imm_expr.X_add_number >= -0x8000 | |
2847 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2848 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2849 | unsignedp ? "sltiu" : "slti", |
9226253a | 2850 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2851 | else |
670a50eb | 2852 | { |
d8a1c247 | 2853 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2854 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2855 | unsignedp ? "sltu" : "slt", |
2856 | "d,v,t", AT, reg, AT); | |
670a50eb | 2857 | } |
3d3c5039 ILT |
2858 | } |
2859 | ||
6e8dda9c | 2860 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2861 | |
2862 | static void | |
19ed8960 | 2863 | check_absolute_expr (ip, ex) |
3d3c5039 | 2864 | struct mips_cl_insn *ip; |
19ed8960 | 2865 | expressionS *ex; |
3d3c5039 | 2866 | { |
5c6f5923 GRK |
2867 | if (ex->X_op == O_big) |
2868 | as_bad ("unsupported large constant"); | |
2869 | else if (ex->X_op != O_constant) | |
4dc85508 | 2870 | as_bad ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2871 | } |
2872 | ||
ff8716f5 JSC |
2873 | /* Count the leading zeroes by performing a binary chop. This is a |
2874 | bulky bit of source, but performance is a LOT better for the | |
2875 | majority of values than a simple loop to count the bits: | |
2876 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2877 | if ((v) & (1 << (31 - lcnt))) | |
2878 | break; | |
2879 | However it is not code size friendly, and the gain will drop a bit | |
2880 | on certain cached systems. | |
2881 | */ | |
2882 | #define COUNT_TOP_ZEROES(v) \ | |
2883 | (((v) & ~0xffff) == 0 \ | |
2884 | ? ((v) & ~0xff) == 0 \ | |
2885 | ? ((v) & ~0xf) == 0 \ | |
2886 | ? ((v) & ~0x3) == 0 \ | |
2887 | ? ((v) & ~0x1) == 0 \ | |
2888 | ? !(v) \ | |
2889 | ? 32 \ | |
2890 | : 31 \ | |
2891 | : 30 \ | |
2892 | : ((v) & ~0x7) == 0 \ | |
2893 | ? 29 \ | |
2894 | : 28 \ | |
2895 | : ((v) & ~0x3f) == 0 \ | |
2896 | ? ((v) & ~0x1f) == 0 \ | |
2897 | ? 27 \ | |
2898 | : 26 \ | |
2899 | : ((v) & ~0x7f) == 0 \ | |
2900 | ? 25 \ | |
2901 | : 24 \ | |
2902 | : ((v) & ~0xfff) == 0 \ | |
2903 | ? ((v) & ~0x3ff) == 0 \ | |
2904 | ? ((v) & ~0x1ff) == 0 \ | |
2905 | ? 23 \ | |
2906 | : 22 \ | |
2907 | : ((v) & ~0x7ff) == 0 \ | |
2908 | ? 21 \ | |
2909 | : 20 \ | |
2910 | : ((v) & ~0x3fff) == 0 \ | |
2911 | ? ((v) & ~0x1fff) == 0 \ | |
2912 | ? 19 \ | |
2913 | : 18 \ | |
2914 | : ((v) & ~0x7fff) == 0 \ | |
2915 | ? 17 \ | |
2916 | : 16 \ | |
2917 | : ((v) & ~0xffffff) == 0 \ | |
2918 | ? ((v) & ~0xfffff) == 0 \ | |
2919 | ? ((v) & ~0x3ffff) == 0 \ | |
2920 | ? ((v) & ~0x1ffff) == 0 \ | |
2921 | ? 15 \ | |
2922 | : 14 \ | |
2923 | : ((v) & ~0x7ffff) == 0 \ | |
2924 | ? 13 \ | |
2925 | : 12 \ | |
2926 | : ((v) & ~0x3fffff) == 0 \ | |
2927 | ? ((v) & ~0x1fffff) == 0 \ | |
2928 | ? 11 \ | |
2929 | : 10 \ | |
2930 | : ((v) & ~0x7fffff) == 0 \ | |
2931 | ? 9 \ | |
2932 | : 8 \ | |
2933 | : ((v) & ~0xfffffff) == 0 \ | |
2934 | ? ((v) & ~0x3ffffff) == 0 \ | |
2935 | ? ((v) & ~0x1ffffff) == 0 \ | |
2936 | ? 7 \ | |
2937 | : 6 \ | |
2938 | : ((v) & ~0x7ffffff) == 0 \ | |
2939 | ? 5 \ | |
2940 | : 4 \ | |
2941 | : ((v) & ~0x3fffffff) == 0 \ | |
2942 | ? ((v) & ~0x1fffffff) == 0 \ | |
2943 | ? 3 \ | |
2944 | : 2 \ | |
2945 | : ((v) & ~0x7fffffff) == 0 \ | |
2946 | ? 1 \ | |
2947 | : 0) | |
2948 | ||
3d3c5039 ILT |
2949 | /* load_register() |
2950 | * This routine generates the least number of instructions neccessary to load | |
2951 | * an absolute expression value into a register. | |
2952 | */ | |
2953 | static void | |
d8a1c247 | 2954 | load_register (counter, reg, ep, dbl) |
670a50eb | 2955 | int *counter; |
670a50eb ILT |
2956 | int reg; |
2957 | expressionS *ep; | |
d8a1c247 | 2958 | int dbl; |
3d3c5039 | 2959 | { |
c36a90ef ILT |
2960 | int freg; |
2961 | expressionS hi32, lo32; | |
847a01cd ILT |
2962 | |
2963 | if (ep->X_op != O_big) | |
6e8dda9c | 2964 | { |
847a01cd | 2965 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2966 | if (ep->X_add_number < 0x8000 |
2967 | && (ep->X_add_number >= 0 | |
2968 | || (ep->X_add_number >= -0x8000 | |
2969 | && (! dbl | |
2970 | || ! ep->X_unsigned | |
2971 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2972 | { |
2973 | /* We can handle 16 bit signed values with an addiu to | |
2974 | $zero. No need to ever use daddiu here, since $zero and | |
2975 | the result are always correct in 32 bit mode. */ | |
2976 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2977 | (int) BFD_RELOC_LO16); | |
2978 | return; | |
2979 | } | |
2980 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2981 | { | |
2982 | /* We can handle 16 bit unsigned values with an ori to | |
2983 | $zero. */ | |
2984 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2985 | (int) BFD_RELOC_LO16); | |
2986 | return; | |
2987 | } | |
98bfd087 ILT |
2988 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2989 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2990 | == ~ (offsetT) 0x7fffffff)) | |
2991 | && (! dbl | |
2992 | || ! ep->X_unsigned | |
2993 | || sizeof (ep->X_add_number) > 4 | |
2994 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 2995 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 2996 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 2997 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
2998 | && ! dbl |
2999 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3000 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
3001 | { |
3002 | /* 32 bit values require an lui. */ | |
3003 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3004 | (int) BFD_RELOC_HI16); | |
3005 | if ((ep->X_add_number & 0xffff) != 0) | |
3006 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3007 | (int) BFD_RELOC_LO16); | |
3008 | return; | |
3009 | } | |
6e8dda9c | 3010 | } |
847a01cd ILT |
3011 | |
3012 | /* The value is larger than 32 bits. */ | |
3013 | ||
3c83da8a | 3014 | if (mips_opts.isa < 3) |
670a50eb | 3015 | { |
6e8dda9c | 3016 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 3017 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 3018 | (int) BFD_RELOC_LO16); |
847a01cd | 3019 | return; |
6e8dda9c | 3020 | } |
6e8dda9c | 3021 | |
847a01cd ILT |
3022 | if (ep->X_op != O_big) |
3023 | { | |
6e8dda9c | 3024 | hi32 = *ep; |
c36a90ef ILT |
3025 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
3026 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 3027 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
3028 | lo32 = *ep; |
3029 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 3030 | } |
847a01cd ILT |
3031 | else |
3032 | { | |
3033 | assert (ep->X_add_number > 2); | |
3034 | if (ep->X_add_number == 3) | |
3035 | generic_bignum[3] = 0; | |
3036 | else if (ep->X_add_number > 4) | |
3037 | as_bad ("Number larger than 64 bits"); | |
3038 | lo32.X_op = O_constant; | |
3039 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3040 | hi32.X_op = O_constant; | |
3041 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3042 | } | |
3043 | ||
d8a1c247 KR |
3044 | if (hi32.X_add_number == 0) |
3045 | freg = 0; | |
3046 | else | |
3047 | { | |
c36a90ef ILT |
3048 | int shift, bit; |
3049 | unsigned long hi, lo; | |
3050 | ||
fb251650 ILT |
3051 | if (hi32.X_add_number == 0xffffffff) |
3052 | { | |
3053 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3054 | { | |
c36a90ef ILT |
3055 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
3056 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3057 | return; |
3058 | } | |
3059 | if (lo32.X_add_number & 0x80000000) | |
3060 | { | |
3061 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3062 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
3063 | if (lo32.X_add_number & 0xffff) |
3064 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3065 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
3066 | return; |
3067 | } | |
3068 | } | |
ff8716f5 | 3069 | |
c36a90ef ILT |
3070 | /* Check for 16bit shifted constant. We know that hi32 is |
3071 | non-zero, so start the mask on the first bit of the hi32 | |
3072 | value. */ | |
ff8716f5 JSC |
3073 | shift = 17; |
3074 | do | |
3075 | { | |
c36a90ef ILT |
3076 | unsigned long himask, lomask; |
3077 | ||
3078 | if (shift < 32) | |
3079 | { | |
3080 | himask = 0xffff >> (32 - shift); | |
3081 | lomask = (0xffff << shift) & 0xffffffff; | |
3082 | } | |
3083 | else | |
3084 | { | |
3085 | himask = 0xffff << (shift - 32); | |
3086 | lomask = 0; | |
3087 | } | |
3088 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3089 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3090 | { | |
3091 | expressionS tmp; | |
3092 | ||
3093 | tmp.X_op = O_constant; | |
3094 | if (shift < 32) | |
3095 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3096 | | (lo32.X_add_number >> shift)); | |
3097 | else | |
3098 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3099 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3100 | (int) BFD_RELOC_LO16); | |
3101 | macro_build ((char *) NULL, counter, NULL, | |
3102 | (shift >= 32) ? "dsll32" : "dsll", | |
3103 | "d,w,<", reg, reg, | |
3104 | (shift >= 32) ? shift - 32 : shift); | |
3105 | return; | |
3106 | } | |
ff8716f5 JSC |
3107 | shift++; |
3108 | } while (shift <= (64 - 16)); | |
3109 | ||
c36a90ef ILT |
3110 | /* Find the bit number of the lowest one bit, and store the |
3111 | shifted value in hi/lo. */ | |
3112 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3113 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3114 | if (lo != 0) | |
3115 | { | |
3116 | bit = 0; | |
3117 | while ((lo & 1) == 0) | |
3118 | { | |
3119 | lo >>= 1; | |
3120 | ++bit; | |
3121 | } | |
3122 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3123 | hi >>= bit; | |
3124 | } | |
3125 | else | |
3126 | { | |
3127 | bit = 32; | |
3128 | while ((hi & 1) == 0) | |
3129 | { | |
3130 | hi >>= 1; | |
3131 | ++bit; | |
3132 | } | |
3133 | lo = hi; | |
3134 | hi = 0; | |
3135 | } | |
3136 | ||
3137 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3138 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3139 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3140 | { |
c36a90ef | 3141 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3142 | if (shift != 0) |
3143 | { | |
c36a90ef ILT |
3144 | expressionS tmp; |
3145 | ||
3146 | /* This instruction will set the register to be all | |
3147 | ones. */ | |
ff8716f5 | 3148 | tmp.X_op = O_constant; |
c36a90ef ILT |
3149 | tmp.X_add_number = (offsetT) -1; |
3150 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3151 | reg, 0, (int) BFD_RELOC_LO16); | |
3152 | if (bit != 0) | |
ff8716f5 | 3153 | { |
c36a90ef | 3154 | bit += shift; |
ff8716f5 | 3155 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3156 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3157 | "d,w,<", reg, reg, |
c36a90ef | 3158 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3159 | } |
c36a90ef ILT |
3160 | macro_build ((char *) NULL, counter, NULL, |
3161 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3162 | "d,w,<", reg, reg, | |
3163 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3164 | return; |
3165 | } | |
3166 | } | |
c36a90ef ILT |
3167 | |
3168 | /* Sign extend hi32 before calling load_register, because we can | |
3169 | generally get better code when we load a sign extended value. */ | |
3170 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3171 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3172 | load_register (counter, reg, &hi32, 0); |
3173 | freg = reg; | |
3174 | } | |
847a01cd | 3175 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3176 | { |
3177 | if (freg != 0) | |
3178 | { | |
3179 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3180 | freg, 0); | |
3181 | freg = reg; | |
3182 | } | |
3183 | } | |
847a01cd ILT |
3184 | else |
3185 | { | |
3186 | expressionS mid16; | |
3187 | ||
fb251650 ILT |
3188 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3189 | { | |
3190 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3191 | (int) BFD_RELOC_HI16); | |
3192 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3193 | reg, 0); |
fb251650 ILT |
3194 | return; |
3195 | } | |
3196 | ||
d8a1c247 KR |
3197 | if (freg != 0) |
3198 | { | |
3199 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3200 | freg, 16); | |
3201 | freg = reg; | |
3202 | } | |
847a01cd ILT |
3203 | mid16 = lo32; |
3204 | mid16.X_add_number >>= 16; | |
3205 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3206 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3207 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3208 | reg, 16); | |
d8a1c247 | 3209 | freg = reg; |
847a01cd ILT |
3210 | } |
3211 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3212 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3213 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3214 | } |
3215 | ||
0dd2d296 ILT |
3216 | /* Load an address into a register. */ |
3217 | ||
3218 | static void | |
3219 | load_address (counter, reg, ep) | |
3220 | int *counter; | |
3221 | int reg; | |
3222 | expressionS *ep; | |
3223 | { | |
3224 | char *p; | |
3225 | ||
3226 | if (ep->X_op != O_constant | |
3227 | && ep->X_op != O_symbol) | |
3228 | { | |
3229 | as_bad ("expression too complex"); | |
3230 | ep->X_op = O_constant; | |
3231 | } | |
3232 | ||
3233 | if (ep->X_op == O_constant) | |
d9aba805 | 3234 | { |
d8a1c247 | 3235 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3236 | return; |
3237 | } | |
3238 | ||
3239 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3240 | { |
3241 | /* If this is a reference to a GP relative symbol, we want | |
3242 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3243 | Otherwise we want | |
04cb3372 | 3244 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3245 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3246 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3247 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3248 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3249 | p = NULL; |
3250 | else | |
3251 | { | |
8ea7f4e8 | 3252 | frag_grow (20); |
0dd2d296 | 3253 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3254 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3255 | || mips_opts.isa < 3) | |
3256 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3257 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3258 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3259 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3260 | mips_opts.warn_about_macros), | |
f59fb6ca | 3261 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3262 | } |
3263 | macro_build_lui (p, counter, ep, reg); | |
3264 | if (p != NULL) | |
3265 | p += 4; | |
3266 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3267 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3268 | || mips_opts.isa < 3) | |
3269 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3270 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3271 | } | |
fb251650 | 3272 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3273 | { |
3274 | expressionS ex; | |
3275 | ||
3276 | /* If this is a reference to an external symbol, we want | |
3277 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3278 | Otherwise we want | |
3279 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3280 | nop | |
3281 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3282 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3283 | ex.X_add_number = ep->X_add_number; |
3284 | ep->X_add_number = 0; | |
8ea7f4e8 | 3285 | frag_grow (20); |
0dd2d296 | 3286 | macro_build ((char *) NULL, counter, ep, |
9a1f3160 JL |
3287 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3288 | || mips_opts.isa < 3) | |
3289 | ? "lw" : "ld"), | |
0dd2d296 ILT |
3290 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3291 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3292 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3293 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3294 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3295 | macro_build (p, counter, ep, |
9a1f3160 JL |
3296 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3297 | || mips_opts.isa < 3) | |
3298 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3299 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3300 | if (ex.X_add_number != 0) | |
3301 | { | |
3302 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3303 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3304 | ex.X_op = O_constant; | |
fb251650 | 3305 | macro_build ((char *) NULL, counter, &ex, |
9a1f3160 JL |
3306 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3307 | || mips_opts.isa < 3) | |
3308 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3309 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3310 | } | |
3311 | } | |
3312 | else if (mips_pic == SVR4_PIC) | |
3313 | { | |
3314 | expressionS ex; | |
3315 | int off; | |
3316 | ||
3317 | /* This is the large GOT case. If this is a reference to an | |
3318 | external symbol, we want | |
3319 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3320 | addu $reg,$reg,$gp | |
3321 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3322 | Otherwise, for a reference to a local symbol, we want | |
3323 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3324 | nop | |
3325 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3326 | If there is a constant, it must be added in after. */ | |
3327 | ex.X_add_number = ep->X_add_number; | |
3328 | ep->X_add_number = 0; | |
3329 | if (reg_needs_delay (GP)) | |
3330 | off = 4; | |
3331 | else | |
3332 | off = 0; | |
3333 | frag_grow (32); | |
3334 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3335 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3336 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
9a1f3160 JL |
3337 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3338 | || mips_opts.isa < 3) | |
3339 | ? "addu" : "daddu"), | |
fb251650 ILT |
3340 | "d,v,t", reg, reg, GP); |
3341 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3342 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3343 | || mips_opts.isa < 3) | |
3344 | ? "lw" : "ld"), | |
fb251650 ILT |
3345 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3346 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3347 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3348 | mips_opts.warn_about_macros), |
f59fb6ca | 3349 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3350 | if (off > 0) |
3351 | { | |
3352 | /* We need a nop before loading from $gp. This special | |
3353 | check is required because the lui which starts the main | |
3354 | instruction stream does not refer to $gp, and so will not | |
3355 | insert the nop which may be required. */ | |
3356 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3357 | p += 4; | |
3358 | } | |
3359 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3360 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3361 | || mips_opts.isa < 3) | |
3362 | ? "lw" : "ld"), | |
fb251650 ILT |
3363 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3364 | p += 4; | |
3365 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3366 | p += 4; | |
3367 | macro_build (p, counter, ep, | |
9a1f3160 JL |
3368 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3369 | || mips_opts.isa < 3) | |
3370 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
3371 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3372 | if (ex.X_add_number != 0) | |
3373 | { | |
3374 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3375 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3376 | ex.X_op = O_constant; | |
3377 | macro_build ((char *) NULL, counter, &ex, | |
9a1f3160 JL |
3378 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3379 | || mips_opts.isa < 3) | |
3380 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
3381 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3382 | } | |
d9aba805 ILT |
3383 | } |
3384 | else if (mips_pic == EMBEDDED_PIC) | |
3385 | { | |
3386 | /* We always do | |
3387 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3388 | */ | |
3389 | macro_build ((char *) NULL, counter, ep, | |
9a1f3160 JL |
3390 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
3391 | || mips_opts.isa < 3) | |
3392 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
3393 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3394 | } | |
3395 | else | |
3396 | abort (); | |
0dd2d296 ILT |
3397 | } |
3398 | ||
3d3c5039 ILT |
3399 | /* |
3400 | * Build macros | |
3401 | * This routine implements the seemingly endless macro or synthesized | |
3402 | * instructions and addressing modes in the mips assembly language. Many | |
3403 | * of these macros are simple and are similar to each other. These could | |
3404 | * probably be handled by some kind of table or grammer aproach instead of | |
3405 | * this verbose method. Others are not simple macros but are more like | |
3406 | * optimizing code generation. | |
3407 | * One interesting optimization is when several store macros appear | |
3408 | * consecutivly that would load AT with the upper half of the same address. | |
3409 | * The ensuing load upper instructions are ommited. This implies some kind | |
3410 | * of global optimization. We currently only optimize within a single macro. | |
3411 | * For many of the load and store macros if the address is specified as a | |
3412 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3413 | * first load register 'at' with zero and use it as the base register. The | |
3414 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3415 | * we're missing. | |
3416 | */ | |
3417 | static void | |
3418 | macro (ip) | |
3419 | struct mips_cl_insn *ip; | |
3420 | { | |
670a50eb ILT |
3421 | register int treg, sreg, dreg, breg; |
3422 | int tempreg; | |
3423 | int mask; | |
3424 | int icnt = 0; | |
3425 | int used_at; | |
670a50eb ILT |
3426 | expressionS expr1; |
3427 | const char *s; | |
8358c818 | 3428 | const char *s2; |
670a50eb | 3429 | const char *fmt; |
8358c818 ILT |
3430 | int likely = 0; |
3431 | int dbl = 0; | |
3432 | int coproc = 0; | |
b2b8c24e | 3433 | int lr = 0; |
6e8dda9c | 3434 | offsetT maxnum; |
adcf2b9d | 3435 | int off; |
9226253a | 3436 | bfd_reloc_code_real_type r; |
0dd2d296 | 3437 | char *p; |
55933a58 | 3438 | int hold_mips_optimize; |
670a50eb | 3439 | |
3c83da8a | 3440 | assert (! mips_opts.mips16); |
cc5703cd | 3441 | |
670a50eb ILT |
3442 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3443 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3444 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3445 | mask = ip->insn_mo->mask; | |
3446 | ||
5ac34ac3 ILT |
3447 | expr1.X_op = O_constant; |
3448 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3449 | expr1.X_add_symbol = NULL; |
3450 | expr1.X_add_number = 1; | |
3451 | ||
3452 | switch (mask) | |
3453 | { | |
6e8dda9c ILT |
3454 | case M_DABS: |
3455 | dbl = 1; | |
3d3c5039 | 3456 | case M_ABS: |
6e8dda9c ILT |
3457 | /* bgez $a0,.+12 |
3458 | move v0,$a0 | |
3459 | sub v0,$zero,$a0 | |
3460 | */ | |
3d3c5039 | 3461 | |
fbcfacb7 | 3462 | mips_emit_delays (true); |
3c83da8a | 3463 | ++mips_opts.noreorder; |
0dd2d296 | 3464 | mips_any_noreorder = 1; |
3d3c5039 | 3465 | |
670a50eb | 3466 | expr1.X_add_number = 8; |
0dd2d296 | 3467 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3468 | if (dreg == sreg) |
0dd2d296 | 3469 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3470 | else |
0dd2d296 ILT |
3471 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3472 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3473 | dbl ? "dsub" : "sub", |
3474 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3475 | |
3c83da8a | 3476 | --mips_opts.noreorder; |
670a50eb | 3477 | return; |
3d3c5039 ILT |
3478 | |
3479 | case M_ADD_I: | |
8358c818 ILT |
3480 | s = "addi"; |
3481 | s2 = "add"; | |
3482 | goto do_addi; | |
3d3c5039 | 3483 | case M_ADDU_I: |
8358c818 ILT |
3484 | s = "addiu"; |
3485 | s2 = "addu"; | |
3486 | goto do_addi; | |
3487 | case M_DADD_I: | |
6e8dda9c | 3488 | dbl = 1; |
8358c818 ILT |
3489 | s = "daddi"; |
3490 | s2 = "dadd"; | |
3491 | goto do_addi; | |
3492 | case M_DADDU_I: | |
6e8dda9c | 3493 | dbl = 1; |
8358c818 ILT |
3494 | s = "daddiu"; |
3495 | s2 = "daddu"; | |
3496 | do_addi: | |
5c6f5923 GRK |
3497 | if (imm_expr.X_op == O_constant |
3498 | && imm_expr.X_add_number >= -0x8000 | |
3499 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3500 | { |
0dd2d296 | 3501 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3502 | (int) BFD_RELOC_LO16); |
670a50eb | 3503 | return; |
3d3c5039 | 3504 | } |
d8a1c247 | 3505 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3506 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3507 | break; |
3d3c5039 ILT |
3508 | |
3509 | case M_AND_I: | |
6e8dda9c ILT |
3510 | s = "andi"; |
3511 | s2 = "and"; | |
3512 | goto do_bit; | |
3d3c5039 | 3513 | case M_OR_I: |
6e8dda9c ILT |
3514 | s = "ori"; |
3515 | s2 = "or"; | |
3516 | goto do_bit; | |
3d3c5039 | 3517 | case M_NOR_I: |
6e8dda9c ILT |
3518 | s = ""; |
3519 | s2 = "nor"; | |
3520 | goto do_bit; | |
3d3c5039 | 3521 | case M_XOR_I: |
6e8dda9c ILT |
3522 | s = "xori"; |
3523 | s2 = "xor"; | |
3524 | do_bit: | |
5c6f5923 GRK |
3525 | if (imm_expr.X_op == O_constant |
3526 | && imm_expr.X_add_number >= 0 | |
3527 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3528 | { |
6e8dda9c | 3529 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3530 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3531 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3532 | else |
670a50eb | 3533 | { |
0dd2d296 ILT |
3534 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3535 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3536 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3537 | treg, treg, 0); |
3d3c5039 | 3538 | } |
6e8dda9c | 3539 | return; |
3d3c5039 | 3540 | } |
6e8dda9c | 3541 | |
d8a1c247 | 3542 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3543 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3544 | break; |
3d3c5039 ILT |
3545 | |
3546 | case M_BEQ_I: | |
8358c818 ILT |
3547 | s = "beq"; |
3548 | goto beq_i; | |
3549 | case M_BEQL_I: | |
3550 | s = "beql"; | |
3551 | likely = 1; | |
3552 | goto beq_i; | |
3d3c5039 | 3553 | case M_BNE_I: |
8358c818 ILT |
3554 | s = "bne"; |
3555 | goto beq_i; | |
3556 | case M_BNEL_I: | |
3557 | s = "bnel"; | |
3558 | likely = 1; | |
3559 | beq_i: | |
5c6f5923 | 3560 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3561 | { |
0dd2d296 ILT |
3562 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3563 | 0); | |
670a50eb ILT |
3564 | return; |
3565 | } | |
d8a1c247 | 3566 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3567 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3568 | break; |
3d3c5039 | 3569 | |
8358c818 ILT |
3570 | case M_BGEL: |
3571 | likely = 1; | |
3d3c5039 | 3572 | case M_BGE: |
670a50eb ILT |
3573 | if (treg == 0) |
3574 | { | |
0dd2d296 | 3575 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3576 | likely ? "bgezl" : "bgez", |
3577 | "s,p", sreg); | |
670a50eb | 3578 | return; |
3d3c5039 | 3579 | } |
9a7d824a ILT |
3580 | if (sreg == 0) |
3581 | { | |
0dd2d296 | 3582 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3583 | likely ? "blezl" : "blez", |
3584 | "s,p", treg); | |
9a7d824a ILT |
3585 | return; |
3586 | } | |
0dd2d296 ILT |
3587 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3588 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3589 | likely ? "beql" : "beq", |
3590 | "s,t,p", AT, 0); | |
670a50eb | 3591 | break; |
3d3c5039 | 3592 | |
8358c818 ILT |
3593 | case M_BGTL_I: |
3594 | likely = 1; | |
3d3c5039 | 3595 | case M_BGT_I: |
9a7d824a | 3596 | /* check for > max integer */ |
6e8dda9c | 3597 | maxnum = 0x7fffffff; |
5c6f5923 | 3598 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3599 | { |
3600 | maxnum <<= 16; | |
3601 | maxnum |= 0xffff; | |
3602 | maxnum <<= 16; | |
3603 | maxnum |= 0xffff; | |
3604 | } | |
5c6f5923 GRK |
3605 | if (imm_expr.X_op == O_constant |
3606 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3607 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3608 | { |
3609 | do_false: | |
3610 | /* result is always false */ | |
8358c818 ILT |
3611 | if (! likely) |
3612 | { | |
3613 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3614 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3615 | } |
3616 | else | |
3617 | { | |
3618 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3619 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3620 | "s,t,p", 0, 0); | |
8358c818 | 3621 | } |
9a7d824a ILT |
3622 | return; |
3623 | } | |
5c6f5923 GRK |
3624 | if (imm_expr.X_op != O_constant) |
3625 | as_bad ("Unsupported large constant"); | |
670a50eb ILT |
3626 | imm_expr.X_add_number++; |
3627 | /* FALLTHROUGH */ | |
3d3c5039 | 3628 | case M_BGE_I: |
8358c818 ILT |
3629 | case M_BGEL_I: |
3630 | if (mask == M_BGEL_I) | |
3631 | likely = 1; | |
5c6f5923 | 3632 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3633 | { |
0dd2d296 | 3634 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3635 | likely ? "bgezl" : "bgez", |
3636 | "s,p", sreg); | |
670a50eb | 3637 | return; |
3d3c5039 | 3638 | } |
5c6f5923 | 3639 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3640 | { |
0dd2d296 | 3641 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3642 | likely ? "bgtzl" : "bgtz", |
3643 | "s,p", sreg); | |
670a50eb | 3644 | return; |
3d3c5039 | 3645 | } |
6e8dda9c | 3646 | maxnum = 0x7fffffff; |
5c6f5923 | 3647 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3648 | { |
3649 | maxnum <<= 16; | |
3650 | maxnum |= 0xffff; | |
3651 | maxnum <<= 16; | |
3652 | maxnum |= 0xffff; | |
3653 | } | |
3654 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3655 | if (imm_expr.X_op == O_constant |
3656 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3657 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3658 | { |
3659 | do_true: | |
3660 | /* result is always true */ | |
3661 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3662 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3663 | return; |
3664 | } | |
6e8dda9c | 3665 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3666 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3667 | likely ? "beql" : "beq", |
3668 | "s,t,p", AT, 0); | |
670a50eb | 3669 | break; |
3d3c5039 | 3670 | |
8358c818 ILT |
3671 | case M_BGEUL: |
3672 | likely = 1; | |
3d3c5039 | 3673 | case M_BGEU: |
670a50eb | 3674 | if (treg == 0) |
9a7d824a ILT |
3675 | goto do_true; |
3676 | if (sreg == 0) | |
670a50eb | 3677 | { |
0dd2d296 | 3678 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3679 | likely ? "beql" : "beq", |
3680 | "s,t,p", 0, treg); | |
670a50eb | 3681 | return; |
3d3c5039 | 3682 | } |
0dd2d296 ILT |
3683 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3684 | treg); | |
3685 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3686 | likely ? "beql" : "beq", |
3687 | "s,t,p", AT, 0); | |
670a50eb | 3688 | break; |
3d3c5039 | 3689 | |
8358c818 ILT |
3690 | case M_BGTUL_I: |
3691 | likely = 1; | |
9a7d824a | 3692 | case M_BGTU_I: |
5c6f5923 GRK |
3693 | if (sreg == 0 |
3694 | || (mips_opts.isa < 3 | |
3695 | && imm_expr.X_op == O_constant | |
3696 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3697 | goto do_false; |
5c6f5923 GRK |
3698 | if (imm_expr.X_op != O_constant) |
3699 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3700 | imm_expr.X_add_number++; |
3701 | /* FALLTHROUGH */ | |
3d3c5039 | 3702 | case M_BGEU_I: |
8358c818 ILT |
3703 | case M_BGEUL_I: |
3704 | if (mask == M_BGEUL_I) | |
3705 | likely = 1; | |
5c6f5923 | 3706 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3707 | goto do_true; |
5c6f5923 | 3708 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3709 | { |
0dd2d296 | 3710 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3711 | likely ? "bnel" : "bne", |
3712 | "s,t,p", sreg, 0); | |
670a50eb | 3713 | return; |
3d3c5039 | 3714 | } |
6e8dda9c | 3715 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3716 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3717 | likely ? "beql" : "beq", |
3718 | "s,t,p", AT, 0); | |
670a50eb | 3719 | break; |
3d3c5039 | 3720 | |
8358c818 ILT |
3721 | case M_BGTL: |
3722 | likely = 1; | |
3d3c5039 | 3723 | case M_BGT: |
670a50eb ILT |
3724 | if (treg == 0) |
3725 | { | |
0dd2d296 | 3726 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3727 | likely ? "bgtzl" : "bgtz", |
3728 | "s,p", sreg); | |
670a50eb | 3729 | return; |
3d3c5039 | 3730 | } |
9a7d824a ILT |
3731 | if (sreg == 0) |
3732 | { | |
0dd2d296 | 3733 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3734 | likely ? "bltzl" : "bltz", |
3735 | "s,p", treg); | |
9a7d824a ILT |
3736 | return; |
3737 | } | |
0dd2d296 ILT |
3738 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3739 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3740 | likely ? "bnel" : "bne", |
3741 | "s,t,p", AT, 0); | |
670a50eb | 3742 | break; |
3d3c5039 | 3743 | |
8358c818 ILT |
3744 | case M_BGTUL: |
3745 | likely = 1; | |
3d3c5039 | 3746 | case M_BGTU: |
670a50eb ILT |
3747 | if (treg == 0) |
3748 | { | |
0dd2d296 | 3749 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3750 | likely ? "bnel" : "bne", |
3751 | "s,t,p", sreg, 0); | |
670a50eb | 3752 | return; |
3d3c5039 | 3753 | } |
9a7d824a ILT |
3754 | if (sreg == 0) |
3755 | goto do_false; | |
0dd2d296 ILT |
3756 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3757 | sreg); | |
3758 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3759 | likely ? "bnel" : "bne", |
3760 | "s,t,p", AT, 0); | |
670a50eb | 3761 | break; |
3d3c5039 | 3762 | |
8358c818 ILT |
3763 | case M_BLEL: |
3764 | likely = 1; | |
3d3c5039 | 3765 | case M_BLE: |
670a50eb ILT |
3766 | if (treg == 0) |
3767 | { | |
0dd2d296 | 3768 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3769 | likely ? "blezl" : "blez", |
3770 | "s,p", sreg); | |
670a50eb ILT |
3771 | return; |
3772 | } | |
9a7d824a ILT |
3773 | if (sreg == 0) |
3774 | { | |
0dd2d296 | 3775 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3776 | likely ? "bgezl" : "bgez", |
3777 | "s,p", treg); | |
9a7d824a ILT |
3778 | return; |
3779 | } | |
0dd2d296 ILT |
3780 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3781 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3782 | likely ? "beql" : "beq", |
3783 | "s,t,p", AT, 0); | |
670a50eb | 3784 | break; |
3d3c5039 | 3785 | |
8358c818 ILT |
3786 | case M_BLEL_I: |
3787 | likely = 1; | |
3d3c5039 | 3788 | case M_BLE_I: |
6e8dda9c | 3789 | maxnum = 0x7fffffff; |
5c6f5923 | 3790 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3791 | { |
3792 | maxnum <<= 16; | |
3793 | maxnum |= 0xffff; | |
3794 | maxnum <<= 16; | |
3795 | maxnum |= 0xffff; | |
3796 | } | |
5c6f5923 GRK |
3797 | if (imm_expr.X_op == O_constant |
3798 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3799 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3800 | goto do_true; |
5c6f5923 GRK |
3801 | if (imm_expr.X_op != O_constant) |
3802 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3803 | imm_expr.X_add_number++; |
3804 | /* FALLTHROUGH */ | |
9a7d824a | 3805 | case M_BLT_I: |
8358c818 ILT |
3806 | case M_BLTL_I: |
3807 | if (mask == M_BLTL_I) | |
3808 | likely = 1; | |
5c6f5923 | 3809 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3810 | { |
0dd2d296 | 3811 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3812 | likely ? "bltzl" : "bltz", |
3813 | "s,p", sreg); | |
670a50eb ILT |
3814 | return; |
3815 | } | |
5c6f5923 | 3816 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3817 | { |
0dd2d296 | 3818 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3819 | likely ? "blezl" : "blez", |
3820 | "s,p", sreg); | |
670a50eb ILT |
3821 | return; |
3822 | } | |
6e8dda9c | 3823 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3824 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3825 | likely ? "bnel" : "bne", |
3826 | "s,t,p", AT, 0); | |
670a50eb | 3827 | break; |
3d3c5039 | 3828 | |
8358c818 ILT |
3829 | case M_BLEUL: |
3830 | likely = 1; | |
3d3c5039 | 3831 | case M_BLEU: |
670a50eb ILT |
3832 | if (treg == 0) |
3833 | { | |
0dd2d296 | 3834 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3835 | likely ? "beql" : "beq", |
3836 | "s,t,p", sreg, 0); | |
670a50eb | 3837 | return; |
3d3c5039 | 3838 | } |
9a7d824a ILT |
3839 | if (sreg == 0) |
3840 | goto do_true; | |
0dd2d296 ILT |
3841 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3842 | sreg); | |
3843 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3844 | likely ? "beql" : "beq", |
3845 | "s,t,p", AT, 0); | |
670a50eb | 3846 | break; |
3d3c5039 | 3847 | |
8358c818 ILT |
3848 | case M_BLEUL_I: |
3849 | likely = 1; | |
3d3c5039 | 3850 | case M_BLEU_I: |
5c6f5923 GRK |
3851 | if (sreg == 0 |
3852 | || (mips_opts.isa < 3 | |
3853 | && imm_expr.X_op == O_constant | |
3854 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3855 | goto do_true; |
5c6f5923 GRK |
3856 | if (imm_expr.X_op != O_constant) |
3857 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3858 | imm_expr.X_add_number++; |
3859 | /* FALLTHROUGH */ | |
9a7d824a | 3860 | case M_BLTU_I: |
8358c818 ILT |
3861 | case M_BLTUL_I: |
3862 | if (mask == M_BLTUL_I) | |
3863 | likely = 1; | |
5c6f5923 | 3864 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3865 | goto do_false; |
5c6f5923 | 3866 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3867 | { |
0dd2d296 | 3868 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3869 | likely ? "beql" : "beq", |
3870 | "s,t,p", sreg, 0); | |
670a50eb | 3871 | return; |
3d3c5039 | 3872 | } |
6e8dda9c | 3873 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3874 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3875 | likely ? "bnel" : "bne", |
3876 | "s,t,p", AT, 0); | |
670a50eb | 3877 | break; |
3d3c5039 | 3878 | |
8358c818 ILT |
3879 | case M_BLTL: |
3880 | likely = 1; | |
3d3c5039 | 3881 | case M_BLT: |
670a50eb ILT |
3882 | if (treg == 0) |
3883 | { | |
0dd2d296 | 3884 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3885 | likely ? "bltzl" : "bltz", |
3886 | "s,p", sreg); | |
670a50eb | 3887 | return; |
3d3c5039 | 3888 | } |
9a7d824a | 3889 | if (sreg == 0) |
670a50eb | 3890 | { |
0dd2d296 | 3891 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3892 | likely ? "bgtzl" : "bgtz", |
3893 | "s,p", treg); | |
670a50eb | 3894 | return; |
3d3c5039 | 3895 | } |
0dd2d296 ILT |
3896 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3897 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3898 | likely ? "bnel" : "bne", |
3899 | "s,t,p", AT, 0); | |
670a50eb | 3900 | break; |
3d3c5039 | 3901 | |
8358c818 ILT |
3902 | case M_BLTUL: |
3903 | likely = 1; | |
3d3c5039 | 3904 | case M_BLTU: |
670a50eb | 3905 | if (treg == 0) |
9a7d824a ILT |
3906 | goto do_false; |
3907 | if (sreg == 0) | |
670a50eb | 3908 | { |
0dd2d296 | 3909 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3910 | likely ? "bnel" : "bne", |
3911 | "s,t,p", 0, treg); | |
670a50eb ILT |
3912 | return; |
3913 | } | |
0dd2d296 ILT |
3914 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3915 | treg); | |
3916 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3917 | likely ? "bnel" : "bne", |
3918 | "s,t,p", AT, 0); | |
670a50eb | 3919 | break; |
3d3c5039 | 3920 | |
8358c818 ILT |
3921 | case M_DDIV_3: |
3922 | dbl = 1; | |
3d3c5039 | 3923 | case M_DIV_3: |
8358c818 ILT |
3924 | s = "mflo"; |
3925 | goto do_div3; | |
3926 | case M_DREM_3: | |
3927 | dbl = 1; | |
3d3c5039 | 3928 | case M_REM_3: |
8358c818 ILT |
3929 | s = "mfhi"; |
3930 | do_div3: | |
670a50eb ILT |
3931 | if (treg == 0) |
3932 | { | |
3933 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3934 | if (mips_trap) |
3935 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3936 | else | |
3937 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3938 | return; |
3939 | } | |
3940 | ||
fbcfacb7 | 3941 | mips_emit_delays (true); |
3c83da8a | 3942 | ++mips_opts.noreorder; |
0dd2d296 | 3943 | mips_any_noreorder = 1; |
8ea7f4e8 | 3944 | if (mips_trap) |
6c4b811d JL |
3945 | { |
3946 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3947 | macro_build ((char *) NULL, &icnt, NULL, | |
3948 | dbl ? "ddiv" : "div", | |
3949 | "z,s,t", sreg, treg); | |
3950 | } | |
8ea7f4e8 ILT |
3951 | else |
3952 | { | |
3953 | expr1.X_add_number = 8; | |
3954 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d JL |
3955 | macro_build ((char *) NULL, &icnt, NULL, |
3956 | dbl ? "ddiv" : "div", | |
3957 | "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3958 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
3959 | } | |
670a50eb | 3960 | expr1.X_add_number = -1; |
0dd2d296 | 3961 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3962 | dbl ? "daddiu" : "addiu", |
9226253a | 3963 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3964 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3965 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3966 | if (dbl) |
3967 | { | |
3968 | expr1.X_add_number = 1; | |
0dd2d296 | 3969 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3970 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3971 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3972 | 31); | |
8358c818 ILT |
3973 | } |
3974 | else | |
3975 | { | |
3976 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3977 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3978 | (int) BFD_RELOC_HI16); | |
8358c818 | 3979 | } |
8ea7f4e8 ILT |
3980 | if (mips_trap) |
3981 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3982 | else | |
3983 | { | |
3984 | expr1.X_add_number = 8; | |
3985 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3986 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3987 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3988 | } | |
3c83da8a | 3989 | --mips_opts.noreorder; |
0dd2d296 | 3990 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3991 | break; |
3d3c5039 ILT |
3992 | |
3993 | case M_DIV_3I: | |
8358c818 ILT |
3994 | s = "div"; |
3995 | s2 = "mflo"; | |
3996 | goto do_divi; | |
3d3c5039 | 3997 | case M_DIVU_3I: |
8358c818 ILT |
3998 | s = "divu"; |
3999 | s2 = "mflo"; | |
4000 | goto do_divi; | |
3d3c5039 | 4001 | case M_REM_3I: |
8358c818 ILT |
4002 | s = "div"; |
4003 | s2 = "mfhi"; | |
4004 | goto do_divi; | |
3d3c5039 | 4005 | case M_REMU_3I: |
8358c818 ILT |
4006 | s = "divu"; |
4007 | s2 = "mfhi"; | |
4008 | goto do_divi; | |
4009 | case M_DDIV_3I: | |
4010 | dbl = 1; | |
4011 | s = "ddiv"; | |
4012 | s2 = "mflo"; | |
4013 | goto do_divi; | |
4014 | case M_DDIVU_3I: | |
4015 | dbl = 1; | |
4016 | s = "ddivu"; | |
4017 | s2 = "mflo"; | |
4018 | goto do_divi; | |
4019 | case M_DREM_3I: | |
4020 | dbl = 1; | |
4021 | s = "ddiv"; | |
4022 | s2 = "mfhi"; | |
4023 | goto do_divi; | |
4024 | case M_DREMU_3I: | |
4025 | dbl = 1; | |
4026 | s = "ddivu"; | |
4027 | s2 = "mfhi"; | |
4028 | do_divi: | |
5c6f5923 | 4029 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb ILT |
4030 | { |
4031 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
4032 | if (mips_trap) |
4033 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4034 | else | |
4035 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
4036 | return; |
4037 | } | |
5c6f5923 | 4038 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 4039 | { |
8358c818 | 4040 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
4041 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
4042 | sreg); | |
3d3c5039 | 4043 | else |
0dd2d296 | 4044 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
4045 | return; |
4046 | } | |
5c6f5923 GRK |
4047 | if (imm_expr.X_op == O_constant |
4048 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
4049 | && s[strlen (s) - 1] != 'u') |
4050 | { | |
4051 | if (strcmp (s2, "mflo") == 0) | |
4052 | { | |
4053 | if (dbl) | |
0dd2d296 ILT |
4054 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
4055 | sreg); | |
8358c818 | 4056 | else |
0dd2d296 ILT |
4057 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
4058 | sreg); | |
8358c818 ILT |
4059 | } |
4060 | else | |
0dd2d296 | 4061 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
4062 | return; |
4063 | } | |
3d3c5039 | 4064 | |
d8a1c247 | 4065 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
4066 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
4067 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
4068 | break; |
4069 | ||
4070 | case M_DIVU_3: | |
8358c818 ILT |
4071 | s = "divu"; |
4072 | s2 = "mflo"; | |
4073 | goto do_divu3; | |
670a50eb | 4074 | case M_REMU_3: |
8358c818 ILT |
4075 | s = "divu"; |
4076 | s2 = "mfhi"; | |
4077 | goto do_divu3; | |
4078 | case M_DDIVU_3: | |
4079 | s = "ddivu"; | |
4080 | s2 = "mflo"; | |
4081 | goto do_divu3; | |
4082 | case M_DREMU_3: | |
4083 | s = "ddivu"; | |
4084 | s2 = "mfhi"; | |
4085 | do_divu3: | |
fbcfacb7 | 4086 | mips_emit_delays (true); |
3c83da8a | 4087 | ++mips_opts.noreorder; |
0dd2d296 | 4088 | mips_any_noreorder = 1; |
8ea7f4e8 | 4089 | if (mips_trap) |
6c4b811d JL |
4090 | { |
4091 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4092 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4093 | } | |
8ea7f4e8 ILT |
4094 | else |
4095 | { | |
4096 | expr1.X_add_number = 8; | |
4097 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
6c4b811d | 4098 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
4099 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
4100 | } | |
3c83da8a | 4101 | --mips_opts.noreorder; |
0dd2d296 | 4102 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 4103 | return; |
3d3c5039 | 4104 | |
d8a1c247 KR |
4105 | case M_DLA_AB: |
4106 | dbl = 1; | |
0dd2d296 | 4107 | case M_LA_AB: |
d9aba805 ILT |
4108 | /* Load the address of a symbol into a register. If breg is not |
4109 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
4110 | |
4111 | /* When generating embedded PIC code, we permit expressions of | |
4112 | the form | |
4113 | la $4,foo-bar | |
4114 | where bar is an address in the .text section. These are used | |
4115 | when getting the addresses of functions. We don't permit | |
4116 | X_add_number to be non-zero, because if the symbol is | |
4117 | external the relaxing code needs to know that any addend is | |
4118 | purely the offset to X_op_symbol. */ | |
4119 | if (mips_pic == EMBEDDED_PIC | |
4120 | && offset_expr.X_op == O_subtract | |
4121 | && now_seg == text_section | |
847a01cd ILT |
4122 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
4123 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
4124 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
4125 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
4126 | ->sy_value.X_add_symbol) | |
4127 | == text_section))) | |
ecd4ca1c ILT |
4128 | && breg == 0 |
4129 | && offset_expr.X_add_number == 0) | |
4130 | { | |
4131 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4132 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4133 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4134 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4135 | || mips_opts.isa < 3) | |
4136 | ? "addiu" : "daddiu"), | |
ecd4ca1c ILT |
4137 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4138 | return; | |
4139 | } | |
4140 | ||
0dd2d296 ILT |
4141 | if (offset_expr.X_op != O_symbol |
4142 | && offset_expr.X_op != O_constant) | |
670a50eb | 4143 | { |
0dd2d296 ILT |
4144 | as_bad ("expression too complex"); |
4145 | offset_expr.X_op = O_constant; | |
4146 | } | |
4147 | ||
4148 | if (treg == breg) | |
4149 | { | |
4150 | tempreg = AT; | |
4151 | used_at = 1; | |
3d3c5039 | 4152 | } |
670a50eb ILT |
4153 | else |
4154 | { | |
0dd2d296 ILT |
4155 | tempreg = treg; |
4156 | used_at = 0; | |
670a50eb | 4157 | } |
3d3c5039 | 4158 | |
5ac34ac3 | 4159 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4160 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4161 | else if (mips_pic == NO_PIC) |
670a50eb | 4162 | { |
0dd2d296 ILT |
4163 | /* If this is a reference to an GP relative symbol, we want |
4164 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4165 | Otherwise we want | |
4166 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4167 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4168 | If we have a constant, we need two instructions anyhow, | |
4169 | so we may as well always use the latter form. */ | |
7a15a226 | 4170 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4171 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4172 | p = NULL; |
4173 | else | |
4174 | { | |
8ea7f4e8 | 4175 | frag_grow (20); |
0dd2d296 | 4176 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
4177 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4178 | || mips_opts.isa < 3) | |
4179 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4180 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4181 | p = frag_var (rs_machine_dependent, 8, 0, | |
4182 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4183 | mips_opts.warn_about_macros), |
f59fb6ca | 4184 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4185 | (char *) NULL); |
4186 | } | |
4187 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4188 | if (p != NULL) | |
4189 | p += 4; | |
4190 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4191 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4192 | || mips_opts.isa < 3) | |
4193 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4194 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4195 | } | |
fb251650 | 4196 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4197 | { |
4198 | /* If this is a reference to an external symbol, and there | |
4199 | is no constant, we want | |
4200 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4201 | For a local symbol, we want | |
4202 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4203 | nop | |
4204 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4205 | ||
4206 | If we have a small constant, and this is a reference to | |
4207 | an external symbol, we want | |
4208 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4209 | nop | |
4210 | addiu $tempreg,$tempreg,<constant> | |
4211 | For a local symbol, we want the same instruction | |
4212 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4213 | addiu instruction. | |
4214 | ||
4215 | If we have a large constant, and this is a reference to | |
4216 | an external symbol, we want | |
4217 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4218 | lui $at,<hiconstant> | |
4219 | addiu $at,$at,<loconstant> | |
4220 | addu $tempreg,$tempreg,$at | |
4221 | For a local symbol, we want the same instruction | |
4222 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4223 | addiu instruction. */ | |
4224 | expr1.X_add_number = offset_expr.X_add_number; | |
4225 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4226 | frag_grow (32); |
0dd2d296 | 4227 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4228 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4229 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4230 | if (expr1.X_add_number == 0) | |
4231 | { | |
4232 | int off; | |
4233 | ||
4234 | if (breg == 0) | |
4235 | off = 0; | |
4236 | else | |
4237 | { | |
4238 | /* We're going to put in an addu instruction using | |
4239 | tempreg, so we may as well insert the nop right | |
4240 | now. */ | |
4241 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4242 | "nop", ""); | |
4243 | off = 4; | |
4244 | } | |
4245 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4246 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4247 | (breg == 0 | |
3c83da8a | 4248 | ? mips_opts.warn_about_macros |
0dd2d296 | 4249 | : 0)), |
f59fb6ca | 4250 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4251 | (char *) NULL); |
4252 | if (breg == 0) | |
4253 | { | |
4254 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4255 | p += 4; | |
4256 | } | |
4257 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4258 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4259 | || mips_opts.isa < 3) | |
4260 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4261 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4262 | /* FIXME: If breg == 0, and the next instruction uses | |
4263 | $tempreg, then if this variant case is used an extra | |
4264 | nop will be generated. */ | |
4265 | } | |
4266 | else if (expr1.X_add_number >= -0x8000 | |
4267 | && expr1.X_add_number < 0x8000) | |
4268 | { | |
4269 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4270 | "nop", ""); | |
4271 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4272 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4273 | || mips_opts.isa < 3) | |
4274 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4275 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4276 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4277 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4278 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4279 | (char *) NULL); |
4280 | } | |
4281 | else | |
4282 | { | |
4283 | int off1; | |
4284 | ||
4285 | /* If we are going to add in a base register, and the | |
4286 | target register and the base register are the same, | |
4287 | then we are using AT as a temporary register. Since | |
4288 | we want to load the constant into AT, we add our | |
4289 | current AT (from the global offset table) and the | |
4290 | register into the register now, and pretend we were | |
4291 | not using a base register. */ | |
4292 | if (breg != treg) | |
4293 | off1 = 0; | |
4294 | else | |
4295 | { | |
4296 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4297 | "nop", ""); | |
4298 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4299 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4300 | || mips_opts.isa < 3) | |
4301 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4302 | "d,v,t", treg, AT, breg); |
4303 | breg = 0; | |
4304 | tempreg = treg; | |
4305 | off1 = -8; | |
4306 | } | |
4307 | ||
55933a58 ILT |
4308 | /* Set mips_optimize around the lui instruction to avoid |
4309 | inserting an unnecessary nop after the lw. */ | |
4310 | hold_mips_optimize = mips_optimize; | |
4311 | mips_optimize = 2; | |
0dd2d296 | 4312 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4313 | mips_optimize = hold_mips_optimize; |
4314 | ||
0dd2d296 | 4315 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
4316 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4317 | || mips_opts.isa < 3) | |
4318 | ? "addiu" : "daddiu"), | |
0dd2d296 ILT |
4319 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4320 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4321 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4322 | || mips_opts.isa < 3) | |
4323 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4324 | "d,v,t", tempreg, tempreg, AT); |
4325 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4326 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4327 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4328 | (char *) NULL); |
4329 | used_at = 1; | |
4330 | } | |
670a50eb | 4331 | } |
fb251650 ILT |
4332 | else if (mips_pic == SVR4_PIC) |
4333 | { | |
4334 | int gpdel; | |
4335 | ||
4336 | /* This is the large GOT case. If this is a reference to an | |
4337 | external symbol, and there is no constant, we want | |
4338 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4339 | addu $tempreg,$tempreg,$gp | |
4340 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4341 | For a local symbol, we want | |
4342 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4343 | nop | |
4344 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4345 | ||
4346 | If we have a small constant, and this is a reference to | |
4347 | an external symbol, we want | |
4348 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4349 | addu $tempreg,$tempreg,$gp | |
4350 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4351 | nop | |
4352 | addiu $tempreg,$tempreg,<constant> | |
4353 | For a local symbol, we want | |
4354 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4355 | nop | |
4356 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4357 | ||
4358 | If we have a large constant, and this is a reference to | |
4359 | an external symbol, we want | |
4360 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4361 | addu $tempreg,$tempreg,$gp | |
4362 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4363 | lui $at,<hiconstant> | |
4364 | addiu $at,$at,<loconstant> | |
4365 | addu $tempreg,$tempreg,$at | |
4366 | For a local symbol, we want | |
4367 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4368 | lui $at,<hiconstant> | |
4369 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4370 | addu $tempreg,$tempreg,$at | |
4371 | */ | |
4372 | expr1.X_add_number = offset_expr.X_add_number; | |
4373 | offset_expr.X_add_number = 0; | |
4374 | frag_grow (52); | |
4375 | if (reg_needs_delay (GP)) | |
4376 | gpdel = 4; | |
4377 | else | |
4378 | gpdel = 0; | |
4379 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4380 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4381 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4382 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4383 | || mips_opts.isa < 3) | |
4384 | ? "addu" : "daddu"), | |
fb251650 ILT |
4385 | "d,v,t", tempreg, tempreg, GP); |
4386 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4387 | dbl ? "ld" : "lw", | |
4388 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4389 | tempreg); | |
4390 | if (expr1.X_add_number == 0) | |
4391 | { | |
4392 | int off; | |
4393 | ||
4394 | if (breg == 0) | |
4395 | off = 0; | |
4396 | else | |
4397 | { | |
4398 | /* We're going to put in an addu instruction using | |
4399 | tempreg, so we may as well insert the nop right | |
4400 | now. */ | |
4401 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4402 | "nop", ""); | |
4403 | off = 4; | |
4404 | } | |
4405 | ||
4406 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4407 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4408 | 8 + gpdel, 0, | |
4409 | (breg == 0 | |
3c83da8a | 4410 | ? mips_opts.warn_about_macros |
fb251650 | 4411 | : 0)), |
f59fb6ca | 4412 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4413 | (char *) NULL); |
4414 | } | |
4415 | else if (expr1.X_add_number >= -0x8000 | |
4416 | && expr1.X_add_number < 0x8000) | |
4417 | { | |
4418 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4419 | "nop", ""); | |
4420 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4421 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4422 | || mips_opts.isa < 3) | |
4423 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4424 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4425 | ||
4426 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4427 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4428 | (breg == 0 | |
3c83da8a | 4429 | ? mips_opts.warn_about_macros |
fb251650 | 4430 | : 0)), |
f59fb6ca | 4431 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4432 | (char *) NULL); |
4433 | } | |
4434 | else | |
4435 | { | |
4436 | int adj, dreg; | |
4437 | ||
4438 | /* If we are going to add in a base register, and the | |
4439 | target register and the base register are the same, | |
4440 | then we are using AT as a temporary register. Since | |
4441 | we want to load the constant into AT, we add our | |
4442 | current AT (from the global offset table) and the | |
4443 | register into the register now, and pretend we were | |
4444 | not using a base register. */ | |
4445 | if (breg != treg) | |
4446 | { | |
4447 | adj = 0; | |
4448 | dreg = tempreg; | |
4449 | } | |
4450 | else | |
4451 | { | |
4452 | assert (tempreg == AT); | |
4453 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4454 | "nop", ""); | |
4455 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4456 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4457 | || mips_opts.isa < 3) | |
4458 | ? "addu" : "daddu"), | |
fb251650 ILT |
4459 | "d,v,t", treg, AT, breg); |
4460 | dreg = treg; | |
4461 | adj = 8; | |
4462 | } | |
4463 | ||
4464 | /* Set mips_optimize around the lui instruction to avoid | |
4465 | inserting an unnecessary nop after the lw. */ | |
4466 | hold_mips_optimize = mips_optimize; | |
4467 | mips_optimize = 2; | |
4468 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4469 | mips_optimize = hold_mips_optimize; | |
4470 | ||
4471 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4472 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4473 | || mips_opts.isa < 3) | |
4474 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4475 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4476 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4477 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4478 | || mips_opts.isa < 3) | |
4479 | ? "addu" : "daddu"), | |
fb251650 ILT |
4480 | "d,v,t", dreg, dreg, AT); |
4481 | ||
4482 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4483 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4484 | 8 + gpdel, 0, | |
4485 | (breg == 0 | |
3c83da8a | 4486 | ? mips_opts.warn_about_macros |
fb251650 | 4487 | : 0)), |
f59fb6ca | 4488 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4489 | (char *) NULL); |
4490 | ||
4491 | used_at = 1; | |
4492 | } | |
4493 | ||
4494 | if (gpdel > 0) | |
4495 | { | |
4496 | /* This is needed because this instruction uses $gp, but | |
4497 | the first instruction on the main stream does not. */ | |
4498 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4499 | p += 4; | |
4500 | } | |
4501 | macro_build (p, &icnt, &offset_expr, | |
4502 | dbl ? "ld" : "lw", | |
4503 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4504 | p += 4; | |
4505 | if (expr1.X_add_number >= -0x8000 | |
4506 | && expr1.X_add_number < 0x8000) | |
4507 | { | |
4508 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4509 | p += 4; | |
4510 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4511 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4512 | || mips_opts.isa < 3) | |
4513 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4514 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4515 | /* FIXME: If add_number is 0, and there was no base | |
4516 | register, the external symbol case ended with a load, | |
4517 | so if the symbol turns out to not be external, and | |
4518 | the next instruction uses tempreg, an unnecessary nop | |
4519 | will be inserted. */ | |
4520 | } | |
4521 | else | |
4522 | { | |
4523 | if (breg == treg) | |
4524 | { | |
4525 | /* We must add in the base register now, as in the | |
4526 | external symbol case. */ | |
4527 | assert (tempreg == AT); | |
4528 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4529 | p += 4; | |
4530 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4531 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4532 | || mips_opts.isa < 3) | |
4533 | ? "addu" : "daddu"), | |
fb251650 ILT |
4534 | "d,v,t", treg, AT, breg); |
4535 | p += 4; | |
4536 | tempreg = treg; | |
4537 | /* We set breg to 0 because we have arranged to add | |
4538 | it in in both cases. */ | |
4539 | breg = 0; | |
4540 | } | |
4541 | ||
4542 | macro_build_lui (p, &icnt, &expr1, AT); | |
4543 | p += 4; | |
4544 | macro_build (p, &icnt, &expr1, | |
9a1f3160 JL |
4545 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4546 | || mips_opts.isa < 3) | |
4547 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
4548 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4549 | p += 4; | |
4550 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4551 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4552 | || mips_opts.isa < 3) | |
4553 | ? "addu" : "daddu"), | |
fb251650 ILT |
4554 | "d,v,t", tempreg, tempreg, AT); |
4555 | p += 4; | |
4556 | } | |
4557 | } | |
d9aba805 ILT |
4558 | else if (mips_pic == EMBEDDED_PIC) |
4559 | { | |
4560 | /* We use | |
4561 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4562 | */ | |
4563 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4564 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4565 | || mips_opts.isa < 3) | |
4566 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4567 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4568 | } | |
4569 | else | |
4570 | abort (); | |
0dd2d296 | 4571 | |
670a50eb | 4572 | if (breg != 0) |
0dd2d296 | 4573 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
4574 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4575 | || mips_opts.isa < 3) | |
4576 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4577 | "d,v,t", treg, tempreg, breg); |
4578 | ||
4579 | if (! used_at) | |
4580 | return; | |
4581 | ||
4582 | break; | |
4583 | ||
4584 | case M_J_A: | |
4585 | /* The j instruction may not be used in PIC code, since it | |
4586 | requires an absolute address. We convert it to a b | |
4587 | instruction. */ | |
d9aba805 | 4588 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4589 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4590 | else | |
4591 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4592 | return; |
3d3c5039 | 4593 | |
9226253a ILT |
4594 | /* The jal instructions must be handled as macros because when |
4595 | generating PIC code they expand to multi-instruction | |
4596 | sequences. Normally they are simple instructions. */ | |
4597 | case M_JAL_1: | |
4598 | dreg = RA; | |
4599 | /* Fall through. */ | |
4600 | case M_JAL_2: | |
d9aba805 ILT |
4601 | if (mips_pic == NO_PIC |
4602 | || mips_pic == EMBEDDED_PIC) | |
4603 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4604 | "d,s", dreg, sreg); | |
4605 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4606 | { |
d9aba805 ILT |
4607 | if (sreg != PIC_CALL_REG) |
4608 | as_warn ("MIPS PIC call to register other than $25"); | |
4609 | ||
0dd2d296 ILT |
4610 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4611 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4612 | if (mips_cprestore_offset < 0) |
4613 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4614 | else | |
4615 | { | |
4616 | expr1.X_add_number = mips_cprestore_offset; | |
4617 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4618 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4619 | || mips_opts.isa < 3) | |
4620 | ? "lw" : "ld"), | |
d9aba805 ILT |
4621 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4622 | } | |
9226253a | 4623 | } |
0dd2d296 | 4624 | else |
d9aba805 ILT |
4625 | abort (); |
4626 | ||
9226253a ILT |
4627 | return; |
4628 | ||
4629 | case M_JAL_A: | |
d9aba805 ILT |
4630 | if (mips_pic == NO_PIC) |
4631 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4632 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4633 | { |
fb251650 ILT |
4634 | /* If this is a reference to an external symbol, and we are |
4635 | using a small GOT, we want | |
d9aba805 ILT |
4636 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4637 | nop | |
4638 | jalr $25 | |
4639 | nop | |
4640 | lw $gp,cprestore($sp) | |
4641 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4642 | pseudo-op. If we are using a big GOT, we want |
4643 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4644 | addu $25,$25,$gp | |
4645 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4646 | nop | |
4647 | jalr $25 | |
4648 | nop | |
4649 | lw $gp,cprestore($sp) | |
4650 | If the symbol is not external, we want | |
d9aba805 ILT |
4651 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4652 | nop | |
4653 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4654 | jalr $25 | |
4655 | nop | |
fb251650 ILT |
4656 | lw $gp,cprestore($sp) */ |
4657 | frag_grow (40); | |
4658 | if (! mips_big_got) | |
4659 | { | |
4660 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4661 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4662 | || mips_opts.isa < 3) | |
4663 | ? "lw" : "ld"), | |
fb251650 ILT |
4664 | "t,o(b)", PIC_CALL_REG, |
4665 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4666 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4667 | "nop", ""); | |
4668 | p = frag_var (rs_machine_dependent, 4, 0, | |
4669 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4670 | offset_expr.X_add_symbol, (offsetT) 0, |
4671 | (char *) NULL); | |
fb251650 ILT |
4672 | } |
4673 | else | |
4674 | { | |
4675 | int gpdel; | |
4676 | ||
4677 | if (reg_needs_delay (GP)) | |
4678 | gpdel = 4; | |
4679 | else | |
4680 | gpdel = 0; | |
4681 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4682 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4683 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
4684 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4685 | || mips_opts.isa < 3) | |
4686 | ? "addu" : "daddu"), | |
fb251650 ILT |
4687 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4688 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
4689 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4690 | || mips_opts.isa < 3) | |
4691 | ? "lw" : "ld"), | |
fb251650 ILT |
4692 | "t,o(b)", PIC_CALL_REG, |
4693 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4694 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4695 | "nop", ""); | |
4696 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4697 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4698 | 0, 0), | |
f59fb6ca ILT |
4699 | offset_expr.X_add_symbol, (offsetT) 0, |
4700 | (char *) NULL); | |
fb251650 ILT |
4701 | if (gpdel > 0) |
4702 | { | |
4703 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4704 | p += 4; | |
4705 | } | |
4706 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
4707 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4708 | || mips_opts.isa < 3) | |
4709 | ? "lw" : "ld"), | |
fb251650 ILT |
4710 | "t,o(b)", PIC_CALL_REG, |
4711 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4712 | p += 4; | |
4713 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4714 | p += 4; | |
4715 | } | |
d9aba805 | 4716 | macro_build (p, &icnt, &offset_expr, |
9a1f3160 JL |
4717 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4718 | || mips_opts.isa < 3) | |
4719 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
4720 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4721 | (int) BFD_RELOC_LO16); | |
4722 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4723 | "jalr", "s", PIC_CALL_REG); | |
4724 | if (mips_cprestore_offset < 0) | |
4725 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4726 | else | |
4727 | { | |
3c83da8a | 4728 | if (mips_opts.noreorder) |
d9aba805 ILT |
4729 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4730 | "nop", ""); | |
4731 | expr1.X_add_number = mips_cprestore_offset; | |
4732 | macro_build ((char *) NULL, &icnt, &expr1, | |
9a1f3160 JL |
4733 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4734 | || mips_opts.isa < 3) | |
4735 | ? "lw" : "ld"), | |
d9aba805 ILT |
4736 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4737 | mips_frame_reg); | |
4738 | } | |
0dd2d296 | 4739 | } |
d9aba805 | 4740 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4741 | { |
4742 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4743 | /* The linker may expand the call to a longer sequence which | |
4744 | uses $at, so we must break rather than return. */ | |
4745 | break; | |
4746 | } | |
d9aba805 ILT |
4747 | else |
4748 | abort (); | |
4749 | ||
9226253a ILT |
4750 | return; |
4751 | ||
3d3c5039 | 4752 | case M_LB_AB: |
670a50eb ILT |
4753 | s = "lb"; |
4754 | goto ld; | |
3d3c5039 | 4755 | case M_LBU_AB: |
670a50eb ILT |
4756 | s = "lbu"; |
4757 | goto ld; | |
3d3c5039 | 4758 | case M_LH_AB: |
670a50eb ILT |
4759 | s = "lh"; |
4760 | goto ld; | |
3d3c5039 | 4761 | case M_LHU_AB: |
670a50eb ILT |
4762 | s = "lhu"; |
4763 | goto ld; | |
3d3c5039 | 4764 | case M_LW_AB: |
670a50eb ILT |
4765 | s = "lw"; |
4766 | goto ld; | |
3d3c5039 | 4767 | case M_LWC0_AB: |
670a50eb | 4768 | s = "lwc0"; |
efec4a28 | 4769 | /* Itbl support may require additional care here. */ |
8358c818 | 4770 | coproc = 1; |
670a50eb | 4771 | goto ld; |
3d3c5039 | 4772 | case M_LWC1_AB: |
670a50eb | 4773 | s = "lwc1"; |
efec4a28 | 4774 | /* Itbl support may require additional care here. */ |
8358c818 | 4775 | coproc = 1; |
670a50eb | 4776 | goto ld; |
3d3c5039 | 4777 | case M_LWC2_AB: |
670a50eb | 4778 | s = "lwc2"; |
efec4a28 | 4779 | /* Itbl support may require additional care here. */ |
8358c818 | 4780 | coproc = 1; |
670a50eb | 4781 | goto ld; |
3d3c5039 | 4782 | case M_LWC3_AB: |
670a50eb | 4783 | s = "lwc3"; |
efec4a28 | 4784 | /* Itbl support may require additional care here. */ |
8358c818 | 4785 | coproc = 1; |
670a50eb | 4786 | goto ld; |
3d3c5039 | 4787 | case M_LWL_AB: |
670a50eb | 4788 | s = "lwl"; |
b2b8c24e | 4789 | lr = 1; |
670a50eb | 4790 | goto ld; |
3d3c5039 | 4791 | case M_LWR_AB: |
670a50eb | 4792 | s = "lwr"; |
b2b8c24e | 4793 | lr = 1; |
8358c818 ILT |
4794 | goto ld; |
4795 | case M_LDC1_AB: | |
1c6f3441 ILT |
4796 | if (mips_4650) |
4797 | { | |
4798 | as_bad ("opcode not supported on this processor"); | |
4799 | return; | |
4800 | } | |
8358c818 | 4801 | s = "ldc1"; |
efec4a28 | 4802 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4803 | coproc = 1; |
4804 | goto ld; | |
4805 | case M_LDC2_AB: | |
4806 | s = "ldc2"; | |
efec4a28 | 4807 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4808 | coproc = 1; |
4809 | goto ld; | |
4810 | case M_LDC3_AB: | |
4811 | s = "ldc3"; | |
efec4a28 | 4812 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4813 | coproc = 1; |
4814 | goto ld; | |
4815 | case M_LDL_AB: | |
4816 | s = "ldl"; | |
b2b8c24e | 4817 | lr = 1; |
8358c818 ILT |
4818 | goto ld; |
4819 | case M_LDR_AB: | |
4820 | s = "ldr"; | |
b2b8c24e | 4821 | lr = 1; |
8358c818 ILT |
4822 | goto ld; |
4823 | case M_LL_AB: | |
4824 | s = "ll"; | |
4825 | goto ld; | |
4826 | case M_LLD_AB: | |
4827 | s = "lld"; | |
4828 | goto ld; | |
4829 | case M_LWU_AB: | |
4830 | s = "lwu"; | |
3d3c5039 | 4831 | ld: |
b2b8c24e | 4832 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4833 | { |
4834 | tempreg = AT; | |
4835 | used_at = 1; | |
4836 | } | |
4837 | else | |
4838 | { | |
4839 | tempreg = treg; | |
4840 | used_at = 0; | |
4841 | } | |
4842 | goto ld_st; | |
3d3c5039 | 4843 | case M_SB_AB: |
670a50eb ILT |
4844 | s = "sb"; |
4845 | goto st; | |
3d3c5039 | 4846 | case M_SH_AB: |
670a50eb ILT |
4847 | s = "sh"; |
4848 | goto st; | |
3d3c5039 | 4849 | case M_SW_AB: |
670a50eb ILT |
4850 | s = "sw"; |
4851 | goto st; | |
3d3c5039 | 4852 | case M_SWC0_AB: |
670a50eb | 4853 | s = "swc0"; |
efec4a28 | 4854 | /* Itbl support may require additional care here. */ |
8358c818 | 4855 | coproc = 1; |
670a50eb | 4856 | goto st; |
3d3c5039 | 4857 | case M_SWC1_AB: |
670a50eb | 4858 | s = "swc1"; |
efec4a28 | 4859 | /* Itbl support may require additional care here. */ |
8358c818 | 4860 | coproc = 1; |
670a50eb | 4861 | goto st; |
3d3c5039 | 4862 | case M_SWC2_AB: |
670a50eb | 4863 | s = "swc2"; |
efec4a28 | 4864 | /* Itbl support may require additional care here. */ |
8358c818 | 4865 | coproc = 1; |
670a50eb | 4866 | goto st; |
3d3c5039 | 4867 | case M_SWC3_AB: |
670a50eb | 4868 | s = "swc3"; |
efec4a28 | 4869 | /* Itbl support may require additional care here. */ |
8358c818 | 4870 | coproc = 1; |
670a50eb | 4871 | goto st; |
3d3c5039 | 4872 | case M_SWL_AB: |
670a50eb ILT |
4873 | s = "swl"; |
4874 | goto st; | |
3d3c5039 | 4875 | case M_SWR_AB: |
670a50eb | 4876 | s = "swr"; |
8358c818 ILT |
4877 | goto st; |
4878 | case M_SC_AB: | |
4879 | s = "sc"; | |
4880 | goto st; | |
4881 | case M_SCD_AB: | |
4882 | s = "scd"; | |
4883 | goto st; | |
4884 | case M_SDC1_AB: | |
1c6f3441 ILT |
4885 | if (mips_4650) |
4886 | { | |
4887 | as_bad ("opcode not supported on this processor"); | |
4888 | return; | |
4889 | } | |
8358c818 ILT |
4890 | s = "sdc1"; |
4891 | coproc = 1; | |
efec4a28 | 4892 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4893 | goto st; |
4894 | case M_SDC2_AB: | |
4895 | s = "sdc2"; | |
efec4a28 | 4896 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4897 | coproc = 1; |
4898 | goto st; | |
4899 | case M_SDC3_AB: | |
4900 | s = "sdc3"; | |
efec4a28 | 4901 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4902 | coproc = 1; |
4903 | goto st; | |
4904 | case M_SDL_AB: | |
4905 | s = "sdl"; | |
4906 | goto st; | |
4907 | case M_SDR_AB: | |
4908 | s = "sdr"; | |
3d3c5039 | 4909 | st: |
670a50eb ILT |
4910 | tempreg = AT; |
4911 | used_at = 1; | |
3d3c5039 | 4912 | ld_st: |
efec4a28 | 4913 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4914 | if (mask == M_LWC1_AB |
4915 | || mask == M_SWC1_AB | |
8358c818 | 4916 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4917 | || mask == M_SDC1_AB |
4918 | || mask == M_L_DAB | |
4919 | || mask == M_S_DAB) | |
670a50eb | 4920 | fmt = "T,o(b)"; |
8358c818 | 4921 | else if (coproc) |
19ed8960 | 4922 | fmt = "E,o(b)"; |
670a50eb ILT |
4923 | else |
4924 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4925 | |
4926 | if (offset_expr.X_op != O_constant | |
4927 | && offset_expr.X_op != O_symbol) | |
4928 | { | |
4929 | as_bad ("expression too complex"); | |
4930 | offset_expr.X_op = O_constant; | |
4931 | } | |
4932 | ||
4933 | /* A constant expression in PIC code can be handled just as it | |
4934 | is in non PIC code. */ | |
d9aba805 | 4935 | if (mips_pic == NO_PIC |
0dd2d296 | 4936 | || offset_expr.X_op == O_constant) |
670a50eb | 4937 | { |
0dd2d296 ILT |
4938 | /* If this is a reference to a GP relative symbol, and there |
4939 | is no base register, we want | |
4940 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4941 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4942 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4943 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4944 | If we have a constant, we need two instructions anyhow, | |
4945 | so we always use the latter form. | |
4946 | ||
4947 | If we have a base register, and this is a reference to a | |
4948 | GP relative symbol, we want | |
4949 | addu $tempreg,$breg,$gp | |
4950 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4951 | Otherwise we want | |
4952 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4953 | addu $tempreg,$tempreg,$breg | |
4954 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4955 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4956 | if (breg == 0) |
4957 | { | |
7a15a226 | 4958 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4959 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4960 | p = NULL; |
4961 | else | |
4962 | { | |
8ea7f4e8 | 4963 | frag_grow (20); |
0dd2d296 ILT |
4964 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4965 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4966 | p = frag_var (rs_machine_dependent, 8, 0, | |
4967 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
4968 | (mips_opts.warn_about_macros |
4969 | || (used_at | |
4970 | && mips_opts.noat))), | |
f59fb6ca | 4971 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 4972 | (char *) NULL); |
8197b589 | 4973 | used_at = 0; |
0dd2d296 ILT |
4974 | } |
4975 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4976 | if (p != NULL) | |
4977 | p += 4; | |
4978 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4979 | (int) BFD_RELOC_LO16, tempreg); | |
4980 | } | |
4981 | else | |
4982 | { | |
7a15a226 | 4983 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4984 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4985 | p = NULL; |
4986 | else | |
4987 | { | |
8ea7f4e8 | 4988 | frag_grow (28); |
0dd2d296 | 4989 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
4990 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
4991 | || mips_opts.isa < 3) | |
4992 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
4993 | "d,v,t", tempreg, breg, GP); |
4994 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4995 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4996 | p = frag_var (rs_machine_dependent, 12, 0, | |
4997 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 4998 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4999 | (char *) NULL); |
5000 | } | |
5001 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5002 | if (p != NULL) | |
5003 | p += 4; | |
5004 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5005 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5006 | || mips_opts.isa < 3) | |
5007 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5008 | "d,v,t", tempreg, tempreg, breg); |
5009 | if (p != NULL) | |
5010 | p += 4; | |
5011 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5012 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5013 | } |
670a50eb | 5014 | } |
fb251650 | 5015 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5016 | { |
0dd2d296 ILT |
5017 | /* If this is a reference to an external symbol, we want |
5018 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5019 | nop | |
5020 | <op> $treg,0($tempreg) | |
5021 | Otherwise we want | |
5022 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5023 | nop | |
5024 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5025 | <op> $treg,0($tempreg) | |
5026 | If there is a base register, we add it to $tempreg before | |
5027 | the <op>. If there is a constant, we stick it in the | |
5028 | <op> instruction. We don't handle constants larger than | |
5029 | 16 bits, because we have no way to load the upper 16 bits | |
5030 | (actually, we could handle them for the subset of cases | |
5031 | in which we are not using $at). */ | |
5032 | assert (offset_expr.X_op == O_symbol); | |
5033 | expr1.X_add_number = offset_expr.X_add_number; | |
5034 | offset_expr.X_add_number = 0; | |
5035 | if (expr1.X_add_number < -0x8000 | |
5036 | || expr1.X_add_number >= 0x8000) | |
5037 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 5038 | frag_grow (20); |
0dd2d296 | 5039 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5040 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5041 | || mips_opts.isa < 3) | |
5042 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5043 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
5044 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5045 | p = frag_var (rs_machine_dependent, 4, 0, | |
5046 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 5047 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
5048 | (char *) NULL); |
5049 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5050 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5051 | || mips_opts.isa < 3) | |
5052 | ? "addiu" : "daddiu"), | |
0dd2d296 | 5053 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 5054 | if (breg != 0) |
0dd2d296 | 5055 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5056 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5057 | || mips_opts.isa < 3) | |
5058 | ? "addu" : "daddu"), | |
6e8dda9c | 5059 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
5060 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
5061 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 5062 | } |
fb251650 ILT |
5063 | else if (mips_pic == SVR4_PIC) |
5064 | { | |
5065 | int gpdel; | |
5066 | ||
5067 | /* If this is a reference to an external symbol, we want | |
5068 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5069 | addu $tempreg,$tempreg,$gp | |
5070 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5071 | <op> $treg,0($tempreg) | |
5072 | Otherwise we want | |
5073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5074 | nop | |
5075 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5076 | <op> $treg,0($tempreg) | |
5077 | If there is a base register, we add it to $tempreg before | |
5078 | the <op>. If there is a constant, we stick it in the | |
5079 | <op> instruction. We don't handle constants larger than | |
5080 | 16 bits, because we have no way to load the upper 16 bits | |
5081 | (actually, we could handle them for the subset of cases | |
5082 | in which we are not using $at). */ | |
5083 | assert (offset_expr.X_op == O_symbol); | |
5084 | expr1.X_add_number = offset_expr.X_add_number; | |
5085 | offset_expr.X_add_number = 0; | |
5086 | if (expr1.X_add_number < -0x8000 | |
5087 | || expr1.X_add_number >= 0x8000) | |
5088 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5089 | if (reg_needs_delay (GP)) | |
5090 | gpdel = 4; | |
5091 | else | |
5092 | gpdel = 0; | |
5093 | frag_grow (36); | |
5094 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5095 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5096 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5097 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5098 | || mips_opts.isa < 3) | |
5099 | ? "addu" : "daddu"), | |
fb251650 ILT |
5100 | "d,v,t", tempreg, tempreg, GP); |
5101 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5102 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5103 | || mips_opts.isa < 3) | |
5104 | ? "lw" : "ld"), | |
867a58b3 ILT |
5105 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5106 | tempreg); | |
fb251650 ILT |
5107 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
5108 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 5109 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
5110 | if (gpdel > 0) |
5111 | { | |
5112 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5113 | p += 4; | |
5114 | } | |
5115 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5116 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5117 | || mips_opts.isa < 3) | |
5118 | ? "lw" : "ld"), | |
867a58b3 | 5119 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
5120 | p += 4; |
5121 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5122 | p += 4; | |
5123 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5124 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5125 | || mips_opts.isa < 3) | |
5126 | ? "addiu" : "daddiu"), | |
fb251650 ILT |
5127 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5128 | if (breg != 0) | |
5129 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5130 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5131 | || mips_opts.isa < 3) | |
5132 | ? "addu" : "daddu"), | |
fb251650 ILT |
5133 | "d,v,t", tempreg, tempreg, breg); |
5134 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5135 | (int) BFD_RELOC_LO16, tempreg); | |
5136 | } | |
d9aba805 ILT |
5137 | else if (mips_pic == EMBEDDED_PIC) |
5138 | { | |
5139 | /* If there is no base register, we want | |
5140 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5141 | If there is a base register, we want | |
5142 | addu $tempreg,$breg,$gp | |
5143 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5144 | */ | |
5145 | assert (offset_expr.X_op == O_symbol); | |
5146 | if (breg == 0) | |
5147 | { | |
5148 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5149 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5150 | used_at = 0; | |
5151 | } | |
5152 | else | |
5153 | { | |
5154 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5155 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5156 | || mips_opts.isa < 3) | |
5157 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5158 | "d,v,t", tempreg, breg, GP); |
5159 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5160 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5161 | } | |
5162 | } | |
5163 | else | |
5164 | abort (); | |
0dd2d296 ILT |
5165 | |
5166 | if (! used_at) | |
5167 | return; | |
5168 | ||
5169 | break; | |
3d3c5039 ILT |
5170 | |
5171 | case M_LI: | |
19ed8960 | 5172 | case M_LI_S: |
d8a1c247 KR |
5173 | load_register (&icnt, treg, &imm_expr, 0); |
5174 | return; | |
5175 | ||
5176 | case M_DLI: | |
5177 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 5178 | return; |
3d3c5039 | 5179 | |
0dd2d296 | 5180 | case M_LI_SS: |
55933a58 | 5181 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 5182 | { |
d8a1c247 | 5183 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
5184 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5185 | "mtc1", "t,G", AT, treg); | |
5186 | break; | |
0dd2d296 | 5187 | } |
d9aba805 | 5188 | else |
d2c71068 | 5189 | { |
55933a58 ILT |
5190 | assert (offset_expr.X_op == O_symbol |
5191 | && strcmp (segment_name (S_GET_SEGMENT | |
5192 | (offset_expr.X_add_symbol)), | |
5193 | ".lit4") == 0 | |
5194 | && offset_expr.X_add_number == 0); | |
5195 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5196 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
5197 | return; |
5198 | } | |
0dd2d296 | 5199 | |
3d3c5039 | 5200 | case M_LI_D: |
a5586bdc ILT |
5201 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5202 | the entire value, and in mips1 mode it is the high order 32 | |
5203 | bits of the value and the low order 32 bits are either zero | |
5204 | or in offset_expr. */ | |
5205 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5206 | { | |
517640d9 ILT |
5207 | if (mips_opts.isa >= 3) |
5208 | load_register (&icnt, treg, &imm_expr, 1); | |
5209 | else | |
a5586bdc | 5210 | { |
517640d9 ILT |
5211 | int hreg, lreg; |
5212 | ||
5213 | if (target_big_endian) | |
5214 | { | |
5215 | hreg = treg; | |
5216 | lreg = treg + 1; | |
5217 | } | |
a5586bdc ILT |
5218 | else |
5219 | { | |
517640d9 ILT |
5220 | hreg = treg + 1; |
5221 | lreg = treg; | |
5222 | } | |
5223 | ||
5224 | if (hreg <= 31) | |
5225 | load_register (&icnt, hreg, &imm_expr, 0); | |
5226 | if (lreg <= 31) | |
5227 | { | |
5228 | if (offset_expr.X_op == O_absent) | |
5229 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5230 | lreg, 0); | |
5231 | else | |
5232 | { | |
5233 | assert (offset_expr.X_op == O_constant); | |
5234 | load_register (&icnt, lreg, &offset_expr, 0); | |
5235 | } | |
a5586bdc ILT |
5236 | } |
5237 | } | |
5238 | return; | |
5239 | } | |
5240 | ||
d9aba805 ILT |
5241 | /* We know that sym is in the .rdata section. First we get the |
5242 | upper 16 bits of the address. */ | |
5243 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
5244 | { |
5245 | /* FIXME: This won't work for a 64 bit address. */ | |
5246 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5247 | } | |
d9aba805 | 5248 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
5249 | { |
5250 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5251 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5252 | || mips_opts.isa < 3) | |
5253 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5254 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5255 | } | |
d9aba805 ILT |
5256 | else if (mips_pic == EMBEDDED_PIC) |
5257 | { | |
5258 | /* For embedded PIC we pick up the entire address off $gp in | |
5259 | a single instruction. */ | |
5260 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5261 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5262 | || mips_opts.isa < 3) | |
5263 | ? "addiu" : "daddiu"), | |
d9aba805 ILT |
5264 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5265 | offset_expr.X_op = O_constant; | |
5266 | offset_expr.X_add_number = 0; | |
5267 | } | |
5268 | else | |
5269 | abort (); | |
5270 | ||
0dd2d296 | 5271 | /* Now we load the register(s). */ |
3c83da8a | 5272 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5273 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5274 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5275 | else |
5276 | { | |
0dd2d296 ILT |
5277 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5278 | treg, (int) BFD_RELOC_LO16, AT); | |
5279 | if (treg != 31) | |
5280 | { | |
5281 | /* FIXME: How in the world do we deal with the possible | |
5282 | overflow here? */ | |
5283 | offset_expr.X_add_number += 4; | |
5284 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5285 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5286 | } | |
8358c818 | 5287 | } |
d2c71068 ILT |
5288 | |
5289 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5290 | does not become a variant frag. */ | |
5291 | frag_wane (frag_now); | |
5292 | frag_new (0); | |
5293 | ||
670a50eb | 5294 | break; |
3d3c5039 ILT |
5295 | |
5296 | case M_LI_DD: | |
a5586bdc ILT |
5297 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5298 | the entire value, and in mips1 mode it is the high order 32 | |
5299 | bits of the value and the low order 32 bits are either zero | |
5300 | or in offset_expr. */ | |
5301 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5302 | { | |
5303 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5304 | if (mips_opts.isa >= 3) | |
5305 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5306 | "dmtc1", "t,S", AT, treg); | |
5307 | else | |
5308 | { | |
5309 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5310 | "mtc1", "t,G", AT, treg + 1); | |
5311 | if (offset_expr.X_op == O_absent) | |
5312 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5313 | "mtc1", "t,G", 0, treg); | |
5314 | else | |
5315 | { | |
5316 | assert (offset_expr.X_op == O_constant); | |
5317 | load_register (&icnt, AT, &offset_expr, 0); | |
5318 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5319 | "mtc1", "t,G", AT, treg); | |
5320 | } | |
5321 | } | |
5322 | break; | |
5323 | } | |
5324 | ||
55933a58 ILT |
5325 | assert (offset_expr.X_op == O_symbol |
5326 | && offset_expr.X_add_number == 0); | |
5327 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5328 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5329 | { |
3c83da8a | 5330 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5331 | { |
5332 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5333 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5334 | return; | |
5335 | } | |
5336 | breg = GP; | |
5337 | r = BFD_RELOC_MIPS_LITERAL; | |
5338 | goto dob; | |
5339 | } | |
55933a58 | 5340 | else |
0dd2d296 | 5341 | { |
55933a58 ILT |
5342 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5343 | if (mips_pic == SVR4_PIC) | |
5344 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5345 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5346 | || mips_opts.isa < 3) | |
5347 | ? "lw" : "ld"), | |
55933a58 ILT |
5348 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5349 | else | |
5350 | { | |
5351 | /* FIXME: This won't work for a 64 bit address. */ | |
5352 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5353 | } | |
5354 | ||
3c83da8a | 5355 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5356 | { |
5357 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5358 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5359 | |
5360 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5361 | that this does not become a variant frag. */ | |
5362 | frag_wane (frag_now); | |
5363 | frag_new (0); | |
5364 | ||
0dd2d296 ILT |
5365 | break; |
5366 | } | |
5367 | breg = AT; | |
5368 | r = BFD_RELOC_LO16; | |
5369 | goto dob; | |
8358c818 | 5370 | } |
9226253a | 5371 | |
3d3c5039 | 5372 | case M_L_DOB: |
1c6f3441 ILT |
5373 | if (mips_4650) |
5374 | { | |
5375 | as_bad ("opcode not supported on this processor"); | |
5376 | return; | |
5377 | } | |
9a7d824a ILT |
5378 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5379 | to adjust when loading from memory. */ | |
9226253a ILT |
5380 | r = BFD_RELOC_LO16; |
5381 | dob: | |
3c83da8a | 5382 | assert (mips_opts.isa < 2); |
0dd2d296 | 5383 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5384 | target_big_endian ? treg + 1 : treg, |
9226253a | 5385 | (int) r, breg); |
0dd2d296 ILT |
5386 | /* FIXME: A possible overflow which I don't know how to deal |
5387 | with. */ | |
670a50eb | 5388 | offset_expr.X_add_number += 4; |
0dd2d296 | 5389 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5390 | target_big_endian ? treg : treg + 1, |
9226253a | 5391 | (int) r, breg); |
d2c71068 ILT |
5392 | |
5393 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5394 | does not become a variant frag. */ | |
5395 | frag_wane (frag_now); | |
5396 | frag_new (0); | |
5397 | ||
0dd2d296 ILT |
5398 | if (breg != AT) |
5399 | return; | |
5400 | break; | |
3d3c5039 ILT |
5401 | |
5402 | case M_L_DAB: | |
670a50eb ILT |
5403 | /* |
5404 | * The MIPS assembler seems to check for X_add_number not | |
5405 | * being double aligned and generating: | |
5406 | * lui at,%hi(foo+1) | |
5407 | * addu at,at,v1 | |
5408 | * addiu at,at,%lo(foo+1) | |
5409 | * lwc1 f2,0(at) | |
5410 | * lwc1 f3,4(at) | |
5411 | * But, the resulting address is the same after relocation so why | |
5412 | * generate the extra instruction? | |
5413 | */ | |
1c6f3441 ILT |
5414 | if (mips_4650) |
5415 | { | |
5416 | as_bad ("opcode not supported on this processor"); | |
5417 | return; | |
5418 | } | |
efec4a28 | 5419 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5420 | coproc = 1; |
3c83da8a | 5421 | if (mips_opts.isa >= 2) |
670a50eb | 5422 | { |
0dd2d296 ILT |
5423 | s = "ldc1"; |
5424 | goto ld; | |
670a50eb | 5425 | } |
0dd2d296 ILT |
5426 | |
5427 | s = "lwc1"; | |
5428 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5429 | goto ldd_std; |
5430 | ||
5431 | case M_S_DAB: | |
1c6f3441 ILT |
5432 | if (mips_4650) |
5433 | { | |
5434 | as_bad ("opcode not supported on this processor"); | |
5435 | return; | |
5436 | } | |
5437 | ||
3c83da8a | 5438 | if (mips_opts.isa >= 2) |
8358c818 | 5439 | { |
0dd2d296 ILT |
5440 | s = "sdc1"; |
5441 | goto st; | |
8358c818 | 5442 | } |
3d3c5039 | 5443 | |
0dd2d296 ILT |
5444 | s = "swc1"; |
5445 | fmt = "T,o(b)"; | |
efec4a28 | 5446 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5447 | coproc = 1; |
5448 | goto ldd_std; | |
3d3c5039 ILT |
5449 | |
5450 | case M_LD_AB: | |
3c83da8a | 5451 | if (mips_opts.isa >= 3) |
670a50eb | 5452 | { |
0dd2d296 ILT |
5453 | s = "ld"; |
5454 | goto ld; | |
670a50eb | 5455 | } |
0dd2d296 ILT |
5456 | |
5457 | s = "lw"; | |
5458 | fmt = "t,o(b)"; | |
5459 | goto ldd_std; | |
5460 | ||
5461 | case M_SD_AB: | |
3c83da8a | 5462 | if (mips_opts.isa >= 3) |
670a50eb | 5463 | { |
0dd2d296 ILT |
5464 | s = "sd"; |
5465 | goto st; | |
670a50eb | 5466 | } |
0dd2d296 | 5467 | |
670a50eb | 5468 | s = "sw"; |
0dd2d296 ILT |
5469 | fmt = "t,o(b)"; |
5470 | ||
5471 | ldd_std: | |
5472 | if (offset_expr.X_op != O_symbol | |
5473 | && offset_expr.X_op != O_constant) | |
670a50eb | 5474 | { |
0dd2d296 ILT |
5475 | as_bad ("expression too complex"); |
5476 | offset_expr.X_op = O_constant; | |
5477 | } | |
5478 | ||
5479 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5480 | to adjust when loading from memory. We set coproc if we must | |
5481 | load $fn+1 first. */ | |
efec4a28 | 5482 | /* Itbl support may require additional care here. */ |
b9129c6f | 5483 | if (! target_big_endian) |
0dd2d296 ILT |
5484 | coproc = 0; |
5485 | ||
d9aba805 | 5486 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5487 | || offset_expr.X_op == O_constant) |
5488 | { | |
5489 | /* If this is a reference to a GP relative symbol, we want | |
5490 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5491 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5492 | If we have a base register, we use this | |
5493 | addu $at,$breg,$gp | |
5494 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5495 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5496 | If this is not a GP relative symbol, we want | |
5497 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5498 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5499 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5500 | If there is a base register, we add it to $at after the | |
5501 | lui instruction. If there is a constant, we always use | |
5502 | the last case. */ | |
7a15a226 | 5503 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5504 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5505 | { |
0dd2d296 ILT |
5506 | p = NULL; |
5507 | used_at = 1; | |
670a50eb ILT |
5508 | } |
5509 | else | |
0dd2d296 ILT |
5510 | { |
5511 | int off; | |
5512 | ||
5513 | if (breg == 0) | |
5514 | { | |
8ea7f4e8 | 5515 | frag_grow (28); |
0dd2d296 ILT |
5516 | tempreg = GP; |
5517 | off = 0; | |
5518 | used_at = 0; | |
5519 | } | |
5520 | else | |
5521 | { | |
8ea7f4e8 | 5522 | frag_grow (36); |
0dd2d296 | 5523 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5524 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5525 | || mips_opts.isa < 3) | |
5526 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5527 | "d,v,t", AT, breg, GP); |
5528 | tempreg = AT; | |
5529 | off = 4; | |
5530 | used_at = 1; | |
5531 | } | |
5532 | ||
efec4a28 | 5533 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5534 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5535 | coproc ? treg + 1 : treg, | |
5536 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5537 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5538 | |
5539 | /* Set mips_optimize to 2 to avoid inserting an | |
5540 | undesired nop. */ | |
5541 | hold_mips_optimize = mips_optimize; | |
5542 | mips_optimize = 2; | |
efec4a28 | 5543 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5544 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5545 | coproc ? treg : treg + 1, | |
5546 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5547 | mips_optimize = hold_mips_optimize; |
5548 | ||
0dd2d296 ILT |
5549 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5550 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5551 | used_at && mips_opts.noat), |
f59fb6ca | 5552 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5553 | (char *) NULL); |
777ad64d ILT |
5554 | |
5555 | /* We just generated two relocs. When tc_gen_reloc | |
5556 | handles this case, it will skip the first reloc and | |
5557 | handle the second. The second reloc already has an | |
5558 | extra addend of 4, which we added above. We must | |
5559 | subtract it out, and then subtract another 4 to make | |
5560 | the first reloc come out right. The second reloc | |
5561 | will come out right because we are going to add 4 to | |
703f5e6e ILT |
5562 | offset_expr when we build its instruction below. |
5563 | ||
5564 | If we have a symbol, then we don't want to include | |
5565 | the offset, because it will wind up being included | |
5566 | when we generate the reloc. */ | |
5567 | ||
5568 | if (offset_expr.X_op == O_constant) | |
5569 | offset_expr.X_add_number -= 8; | |
5570 | else | |
5571 | { | |
5572 | offset_expr.X_add_number = -4; | |
5573 | offset_expr.X_op = O_constant; | |
5574 | } | |
0dd2d296 ILT |
5575 | } |
5576 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5577 | if (p != NULL) | |
5578 | p += 4; | |
5579 | if (breg != 0) | |
5580 | { | |
5581 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5582 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5583 | || mips_opts.isa < 3) | |
5584 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
5585 | "d,v,t", AT, breg, AT); |
5586 | if (p != NULL) | |
5587 | p += 4; | |
5588 | } | |
efec4a28 | 5589 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5590 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5591 | coproc ? treg + 1 : treg, | |
5592 | (int) BFD_RELOC_LO16, AT); | |
5593 | if (p != NULL) | |
5594 | p += 4; | |
5595 | /* FIXME: How do we handle overflow here? */ | |
5596 | offset_expr.X_add_number += 4; | |
efec4a28 | 5597 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5598 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5599 | coproc ? treg : treg + 1, | |
5600 | (int) BFD_RELOC_LO16, AT); | |
5601 | } | |
fb251650 | 5602 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5603 | { |
0dd2d296 ILT |
5604 | int off; |
5605 | ||
5606 | /* If this is a reference to an external symbol, we want | |
5607 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5608 | nop | |
5609 | <op> $treg,0($at) | |
5610 | <op> $treg+1,4($at) | |
5611 | Otherwise we want | |
5612 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5613 | nop | |
5614 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5615 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5616 | If there is a base register we add it to $at before the | |
5617 | lwc1 instructions. If there is a constant we include it | |
5618 | in the lwc1 instructions. */ | |
5619 | used_at = 1; | |
5620 | expr1.X_add_number = offset_expr.X_add_number; | |
5621 | offset_expr.X_add_number = 0; | |
5622 | if (expr1.X_add_number < -0x8000 | |
5623 | || expr1.X_add_number >= 0x8000 - 4) | |
5624 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5625 | if (breg == 0) | |
5626 | off = 0; | |
5627 | else | |
5628 | off = 4; | |
8ea7f4e8 | 5629 | frag_grow (24 + off); |
0dd2d296 | 5630 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a1f3160 JL |
5631 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5632 | || mips_opts.isa < 3) | |
5633 | ? "lw" : "ld"), | |
0dd2d296 ILT |
5634 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5635 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5636 | if (breg != 0) |
0dd2d296 | 5637 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a1f3160 JL |
5638 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5639 | || mips_opts.isa < 3) | |
5640 | ? "addu" : "daddu"), | |
0dd2d296 | 5641 | "d,v,t", AT, breg, AT); |
efec4a28 | 5642 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5643 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5644 | coproc ? treg + 1 : treg, | |
5645 | (int) BFD_RELOC_LO16, AT); | |
5646 | expr1.X_add_number += 4; | |
55933a58 ILT |
5647 | |
5648 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5649 | nop. */ | |
5650 | hold_mips_optimize = mips_optimize; | |
5651 | mips_optimize = 2; | |
efec4a28 | 5652 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5653 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5654 | coproc ? treg : treg + 1, | |
5655 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5656 | mips_optimize = hold_mips_optimize; |
5657 | ||
0dd2d296 ILT |
5658 | (void) frag_var (rs_machine_dependent, 0, 0, |
5659 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5660 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5661 | (char *) NULL); |
8358c818 | 5662 | } |
fb251650 ILT |
5663 | else if (mips_pic == SVR4_PIC) |
5664 | { | |
5665 | int gpdel, off; | |
5666 | ||
5667 | /* If this is a reference to an external symbol, we want | |
5668 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5669 | addu $at,$at,$gp | |
5670 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5671 | nop | |
5672 | <op> $treg,0($at) | |
5673 | <op> $treg+1,4($at) | |
5674 | Otherwise we want | |
5675 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5676 | nop | |
5677 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5678 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5679 | If there is a base register we add it to $at before the | |
5680 | lwc1 instructions. If there is a constant we include it | |
5681 | in the lwc1 instructions. */ | |
5682 | used_at = 1; | |
5683 | expr1.X_add_number = offset_expr.X_add_number; | |
5684 | offset_expr.X_add_number = 0; | |
5685 | if (expr1.X_add_number < -0x8000 | |
5686 | || expr1.X_add_number >= 0x8000 - 4) | |
5687 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5688 | if (reg_needs_delay (GP)) | |
5689 | gpdel = 4; | |
5690 | else | |
5691 | gpdel = 0; | |
5692 | if (breg == 0) | |
5693 | off = 0; | |
5694 | else | |
5695 | off = 4; | |
5696 | frag_grow (56); | |
5697 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5698 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5699 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5700 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5701 | || mips_opts.isa < 3) | |
5702 | ? "addu" : "daddu"), | |
fb251650 ILT |
5703 | "d,v,t", AT, AT, GP); |
5704 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a1f3160 JL |
5705 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5706 | || mips_opts.isa < 3) | |
5707 | ? "lw" : "ld"), | |
fb251650 ILT |
5708 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5709 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5710 | if (breg != 0) | |
5711 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5712 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5713 | || mips_opts.isa < 3) | |
5714 | ? "addu" : "daddu"), | |
fb251650 | 5715 | "d,v,t", AT, breg, AT); |
efec4a28 | 5716 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5717 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5718 | coproc ? treg + 1 : treg, | |
5719 | (int) BFD_RELOC_LO16, AT); | |
5720 | expr1.X_add_number += 4; | |
5721 | ||
5722 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5723 | nop. */ | |
5724 | hold_mips_optimize = mips_optimize; | |
5725 | mips_optimize = 2; | |
efec4a28 | 5726 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5727 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5728 | coproc ? treg : treg + 1, | |
5729 | (int) BFD_RELOC_LO16, AT); | |
5730 | mips_optimize = hold_mips_optimize; | |
5731 | expr1.X_add_number -= 4; | |
5732 | ||
5733 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5734 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5735 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5736 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5737 | (char *) NULL); |
5738 | if (gpdel > 0) | |
5739 | { | |
5740 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5741 | p += 4; | |
5742 | } | |
5743 | macro_build (p, &icnt, &offset_expr, | |
9a1f3160 JL |
5744 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5745 | || mips_opts.isa < 3) | |
5746 | ? "lw" : "ld"), | |
fb251650 ILT |
5747 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5748 | p += 4; | |
5749 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5750 | p += 4; | |
5751 | if (breg != 0) | |
5752 | { | |
5753 | macro_build (p, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5754 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5755 | || mips_opts.isa < 3) | |
5756 | ? "addu" : "daddu"), | |
fb251650 ILT |
5757 | "d,v,t", AT, breg, AT); |
5758 | p += 4; | |
5759 | } | |
efec4a28 | 5760 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5761 | macro_build (p, &icnt, &expr1, s, fmt, |
5762 | coproc ? treg + 1 : treg, | |
5763 | (int) BFD_RELOC_LO16, AT); | |
5764 | p += 4; | |
5765 | expr1.X_add_number += 4; | |
5766 | ||
5767 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5768 | nop. */ | |
5769 | hold_mips_optimize = mips_optimize; | |
5770 | mips_optimize = 2; | |
efec4a28 | 5771 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5772 | macro_build (p, &icnt, &expr1, s, fmt, |
5773 | coproc ? treg : treg + 1, | |
5774 | (int) BFD_RELOC_LO16, AT); | |
5775 | mips_optimize = hold_mips_optimize; | |
5776 | } | |
d9aba805 ILT |
5777 | else if (mips_pic == EMBEDDED_PIC) |
5778 | { | |
5779 | /* If there is no base register, we use | |
5780 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5781 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5782 | If we have a base register, we use | |
5783 | addu $at,$breg,$gp | |
5784 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5785 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5786 | */ | |
5787 | if (breg == 0) | |
5788 | { | |
5789 | tempreg = GP; | |
5790 | used_at = 0; | |
5791 | } | |
5792 | else | |
5793 | { | |
5794 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
5795 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
5796 | || mips_opts.isa < 3) | |
5797 | ? "addu" : "daddu"), | |
d9aba805 ILT |
5798 | "d,v,t", AT, breg, GP); |
5799 | tempreg = AT; | |
5800 | used_at = 1; | |
5801 | } | |
5802 | ||
efec4a28 | 5803 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5804 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5805 | coproc ? treg + 1 : treg, | |
5806 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5807 | offset_expr.X_add_number += 4; | |
efec4a28 | 5808 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5809 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5810 | coproc ? treg : treg + 1, | |
5811 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5812 | } | |
5813 | else | |
5814 | abort (); | |
0dd2d296 ILT |
5815 | |
5816 | if (! used_at) | |
5817 | return; | |
5818 | ||
5819 | break; | |
5820 | ||
5821 | case M_LD_OB: | |
5822 | s = "lw"; | |
5823 | goto sd_ob; | |
5824 | case M_SD_OB: | |
5825 | s = "sw"; | |
5826 | sd_ob: | |
9a1f3160 | 5827 | assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3); |
0dd2d296 ILT |
5828 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5829 | (int) BFD_RELOC_LO16, breg); | |
5830 | offset_expr.X_add_number += 4; | |
5831 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5832 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5833 | return; |
efec4a28 DP |
5834 | |
5835 | /* New code added to support COPZ instructions. | |
5836 | This code builds table entries out of the macros in mip_opcodes. | |
5837 | R4000 uses interlocks to handle coproc delays. | |
5838 | Other chips (like the R3000) require nops to be inserted for delays. | |
5839 | ||
5840 | FIXME: Currently, we require that the user handle delays. | |
5841 | In order to fill delay slots for non-interlocked chips, | |
5842 | we must have a way to specify delays based on the coprocessor. | |
5843 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5844 | What are the side-effects of the cop instruction? | |
5845 | What cache support might we have and what are its effects? | |
5846 | Both coprocessor & memory require delays. how long??? | |
5847 | What registers are read/set/modified? | |
5848 | ||
5849 | If an itbl is provided to interpret cop instructions, | |
5850 | this knowledge can be encoded in the itbl spec. */ | |
5851 | ||
5852 | case M_COP0: | |
65d2c7d3 | 5853 | s = "c0"; |
efec4a28 DP |
5854 | goto copz; |
5855 | case M_COP1: | |
65d2c7d3 | 5856 | s = "c1"; |
efec4a28 DP |
5857 | goto copz; |
5858 | case M_COP2: | |
65d2c7d3 | 5859 | s = "c2"; |
efec4a28 DP |
5860 | goto copz; |
5861 | case M_COP3: | |
65d2c7d3 | 5862 | s = "c3"; |
efec4a28 | 5863 | copz: |
65d2c7d3 JL |
5864 | /* For now we just do C (same as Cz). The parameter will be |
5865 | stored in insn_opcode by mips_ip. */ | |
5866 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5867 | ip->insn_opcode); | |
efec4a28 DP |
5868 | return; |
5869 | ||
917fae09 SS |
5870 | #ifdef LOSING_COMPILER |
5871 | default: | |
efec4a28 DP |
5872 | /* Try and see if this is a new itbl instruction. |
5873 | This code builds table entries out of the macros in mip_opcodes. | |
5874 | FIXME: For now we just assemble the expression and pass it's | |
5875 | value along as a 32-bit immediate. | |
5876 | We may want to have the assembler assemble this value, | |
5877 | so that we gain the assembler's knowledge of delay slots, | |
5878 | symbols, etc. | |
5879 | Would it be more efficient to use mask (id) here? */ | |
5880 | if (itbl_have_entries | |
9218cee0 | 5881 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
5882 | { |
5883 | s = ip->insn_mo->name; | |
5884 | s2 = "cop3"; | |
9218cee0 | 5885 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
5886 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
5887 | return; | |
5888 | } | |
917fae09 SS |
5889 | macro2 (ip); |
5890 | return; | |
5891 | } | |
3c83da8a | 5892 | if (mips_opts.noat) |
917fae09 SS |
5893 | as_warn ("Macro used $at after \".set noat\""); |
5894 | } | |
5895 | ||
5896 | static void | |
5897 | macro2 (ip) | |
5898 | struct mips_cl_insn *ip; | |
5899 | { | |
5900 | register int treg, sreg, dreg, breg; | |
5901 | int tempreg; | |
5902 | int mask; | |
5903 | int icnt = 0; | |
5904 | int used_at; | |
5905 | expressionS expr1; | |
5906 | const char *s; | |
5907 | const char *s2; | |
5908 | const char *fmt; | |
5909 | int likely = 0; | |
5910 | int dbl = 0; | |
5911 | int coproc = 0; | |
adcf2b9d ILT |
5912 | int lr = 0; |
5913 | int off; | |
917fae09 SS |
5914 | offsetT maxnum; |
5915 | bfd_reloc_code_real_type r; | |
5916 | char *p; | |
5917 | ||
5918 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5919 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5920 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5921 | mask = ip->insn_mo->mask; | |
5922 | ||
5923 | expr1.X_op = O_constant; | |
5924 | expr1.X_op_symbol = NULL; | |
5925 | expr1.X_add_symbol = NULL; | |
5926 | expr1.X_add_number = 1; | |
5927 | ||
5928 | switch (mask) | |
5929 | { | |
5930 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5931 | |
8358c818 ILT |
5932 | case M_DMUL: |
5933 | dbl = 1; | |
3d3c5039 | 5934 | case M_MUL: |
0dd2d296 | 5935 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5936 | dbl ? "dmultu" : "multu", |
5937 | "s,t", sreg, treg); | |
0dd2d296 | 5938 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5939 | return; |
3d3c5039 | 5940 | |
8358c818 ILT |
5941 | case M_DMUL_I: |
5942 | dbl = 1; | |
3d3c5039 | 5943 | case M_MUL_I: |
8358c818 ILT |
5944 | /* The MIPS assembler some times generates shifts and adds. I'm |
5945 | not trying to be that fancy. GCC should do this for us | |
5946 | anyway. */ | |
d8a1c247 | 5947 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5948 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5949 | dbl ? "dmult" : "mult", |
5950 | "s,t", sreg, AT); | |
0dd2d296 | 5951 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5952 | break; |
3d3c5039 | 5953 | |
8358c818 ILT |
5954 | case M_DMULO: |
5955 | dbl = 1; | |
5956 | case M_MULO: | |
fbcfacb7 | 5957 | mips_emit_delays (true); |
3c83da8a | 5958 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5959 | mips_any_noreorder = 1; |
5960 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5961 | dbl ? "dmult" : "mult", |
5962 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5963 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5964 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5965 | dbl ? "dsra32" : "sra", |
5966 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5967 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5968 | if (mips_trap) |
5969 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5970 | else | |
5971 | { | |
5972 | expr1.X_add_number = 8; | |
5973 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5974 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5975 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5976 | } | |
3c83da8a | 5977 | --mips_opts.noreorder; |
0dd2d296 | 5978 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5979 | break; |
5980 | ||
5981 | case M_DMULOU: | |
5982 | dbl = 1; | |
5983 | case M_MULOU: | |
fbcfacb7 | 5984 | mips_emit_delays (true); |
3c83da8a | 5985 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5986 | mips_any_noreorder = 1; |
5987 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5988 | dbl ? "dmultu" : "multu", |
5989 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5990 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5991 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5992 | if (mips_trap) |
5993 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5994 | else | |
5995 | { | |
5996 | expr1.X_add_number = 8; | |
5997 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5998 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5999 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
6000 | } | |
3c83da8a | 6001 | --mips_opts.noreorder; |
8358c818 ILT |
6002 | break; |
6003 | ||
3d3c5039 | 6004 | case M_ROL: |
0dd2d296 ILT |
6005 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6006 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6007 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6008 | treg); | |
6009 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6010 | break; |
3d3c5039 ILT |
6011 | |
6012 | case M_ROL_I: | |
5c6f5923 GRK |
6013 | if (imm_expr.X_op != O_constant) |
6014 | as_bad ("rotate count too large"); | |
0dd2d296 | 6015 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 6016 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6017 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 6018 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6019 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6020 | break; |
3d3c5039 ILT |
6021 | |
6022 | case M_ROR: | |
0dd2d296 ILT |
6023 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
6024 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6025 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6026 | treg); | |
6027 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 6028 | break; |
3d3c5039 ILT |
6029 | |
6030 | case M_ROR_I: | |
5c6f5923 GRK |
6031 | if (imm_expr.X_op != O_constant) |
6032 | as_bad ("rotate count too large"); | |
0dd2d296 | 6033 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 6034 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 6035 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 6036 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 6037 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 6038 | break; |
3d3c5039 ILT |
6039 | |
6040 | case M_S_DOB: | |
1c6f3441 ILT |
6041 | if (mips_4650) |
6042 | { | |
6043 | as_bad ("opcode not supported on this processor"); | |
6044 | return; | |
6045 | } | |
3c83da8a | 6046 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
6047 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6048 | to adjust when storing to memory. */ | |
0dd2d296 | 6049 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6050 | target_big_endian ? treg + 1 : treg, |
9226253a | 6051 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6052 | offset_expr.X_add_number += 4; |
0dd2d296 | 6053 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 6054 | target_big_endian ? treg : treg + 1, |
9226253a | 6055 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6056 | return; |
3d3c5039 | 6057 | |
3d3c5039 | 6058 | case M_SEQ: |
670a50eb | 6059 | if (sreg == 0) |
0dd2d296 ILT |
6060 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6061 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 6062 | else if (treg == 0) |
0dd2d296 ILT |
6063 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6064 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
6065 | else |
6066 | { | |
0dd2d296 ILT |
6067 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6068 | sreg, treg); | |
6069 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6070 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 6071 | } |
670a50eb | 6072 | return; |
3d3c5039 ILT |
6073 | |
6074 | case M_SEQ_I: | |
5c6f5923 | 6075 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6076 | { |
0dd2d296 ILT |
6077 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6078 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6079 | return; |
3d3c5039 | 6080 | } |
670a50eb ILT |
6081 | if (sreg == 0) |
6082 | { | |
9a7d824a | 6083 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 6084 | ip->insn_mo->name); |
0dd2d296 | 6085 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 6086 | return; |
3d3c5039 | 6087 | } |
5c6f5923 GRK |
6088 | if (imm_expr.X_op == O_constant |
6089 | && imm_expr.X_add_number >= 0 | |
6090 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6091 | { |
0dd2d296 ILT |
6092 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
6093 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6094 | used_at = 0; |
6e8dda9c | 6095 | } |
5c6f5923 GRK |
6096 | else if (imm_expr.X_op == O_constant |
6097 | && imm_expr.X_add_number > -0x8000 | |
6098 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6099 | { |
6100 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6101 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6102 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6103 | || mips_opts.isa < 3) | |
6104 | ? "addiu" : "daddiu"), | |
9226253a ILT |
6105 | "t,r,j", dreg, sreg, |
6106 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
6107 | used_at = 0; |
6108 | } | |
6109 | else | |
6110 | { | |
d8a1c247 | 6111 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6112 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6113 | sreg, AT); | |
670a50eb ILT |
6114 | used_at = 1; |
6115 | } | |
0dd2d296 | 6116 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 6117 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6118 | if (used_at) |
6119 | break; | |
6120 | return; | |
3d3c5039 ILT |
6121 | |
6122 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
6123 | s = "slt"; |
6124 | goto sge; | |
3d3c5039 | 6125 | case M_SGEU: |
670a50eb | 6126 | s = "sltu"; |
3d3c5039 | 6127 | sge: |
0dd2d296 ILT |
6128 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
6129 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6130 | (int) BFD_RELOC_LO16); |
670a50eb | 6131 | return; |
3d3c5039 | 6132 | |
670a50eb | 6133 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 6134 | case M_SGEU_I: |
5c6f5923 GRK |
6135 | if (imm_expr.X_op == O_constant |
6136 | && imm_expr.X_add_number >= -0x8000 | |
6137 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6138 | { |
0dd2d296 | 6139 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 6140 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 6141 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
6142 | used_at = 0; |
6143 | } | |
6144 | else | |
6145 | { | |
d8a1c247 | 6146 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6147 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
6148 | mask == M_SGE_I ? "slt" : "sltu", |
6149 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
6150 | used_at = 1; |
6151 | } | |
0dd2d296 | 6152 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 6153 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
6154 | if (used_at) |
6155 | break; | |
6156 | return; | |
3d3c5039 ILT |
6157 | |
6158 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
6159 | s = "slt"; |
6160 | goto sgt; | |
3d3c5039 | 6161 | case M_SGTU: |
670a50eb | 6162 | s = "sltu"; |
3d3c5039 | 6163 | sgt: |
0dd2d296 | 6164 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 6165 | return; |
3d3c5039 | 6166 | |
670a50eb ILT |
6167 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
6168 | s = "slt"; | |
6169 | goto sgti; | |
3d3c5039 | 6170 | case M_SGTU_I: |
670a50eb | 6171 | s = "sltu"; |
3d3c5039 | 6172 | sgti: |
d8a1c247 | 6173 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6174 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 6175 | break; |
3d3c5039 | 6176 | |
670a50eb ILT |
6177 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
6178 | s = "slt"; | |
6179 | goto sle; | |
3d3c5039 | 6180 | case M_SLEU: |
670a50eb | 6181 | s = "sltu"; |
3d3c5039 | 6182 | sle: |
0dd2d296 ILT |
6183 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
6184 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6185 | (int) BFD_RELOC_LO16); |
670a50eb | 6186 | return; |
3d3c5039 | 6187 | |
670a50eb ILT |
6188 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
6189 | s = "slt"; | |
6190 | goto slei; | |
3d3c5039 | 6191 | case M_SLEU_I: |
670a50eb | 6192 | s = "sltu"; |
3d3c5039 | 6193 | slei: |
d8a1c247 | 6194 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6195 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
6196 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 6197 | (int) BFD_RELOC_LO16); |
670a50eb | 6198 | break; |
3d3c5039 ILT |
6199 | |
6200 | case M_SLT_I: | |
5c6f5923 GRK |
6201 | if (imm_expr.X_op == O_constant |
6202 | && imm_expr.X_add_number >= -0x8000 | |
6203 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6204 | { |
0dd2d296 ILT |
6205 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
6206 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6207 | return; |
3d3c5039 | 6208 | } |
d8a1c247 | 6209 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6210 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 6211 | break; |
3d3c5039 ILT |
6212 | |
6213 | case M_SLTU_I: | |
5c6f5923 GRK |
6214 | if (imm_expr.X_op == O_constant |
6215 | && imm_expr.X_add_number >= -0x8000 | |
6216 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 6217 | { |
0dd2d296 ILT |
6218 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
6219 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6220 | return; |
3d3c5039 | 6221 | } |
d8a1c247 | 6222 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6223 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
6224 | AT); | |
670a50eb | 6225 | break; |
3d3c5039 ILT |
6226 | |
6227 | case M_SNE: | |
670a50eb | 6228 | if (sreg == 0) |
0dd2d296 ILT |
6229 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6230 | treg); | |
670a50eb | 6231 | else if (treg == 0) |
0dd2d296 ILT |
6232 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6233 | sreg); | |
670a50eb ILT |
6234 | else |
6235 | { | |
0dd2d296 ILT |
6236 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6237 | sreg, treg); | |
6238 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6239 | dreg); | |
3d3c5039 | 6240 | } |
670a50eb | 6241 | return; |
3d3c5039 ILT |
6242 | |
6243 | case M_SNE_I: | |
5c6f5923 | 6244 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 6245 | { |
0dd2d296 ILT |
6246 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
6247 | sreg); | |
670a50eb | 6248 | return; |
3d3c5039 | 6249 | } |
670a50eb ILT |
6250 | if (sreg == 0) |
6251 | { | |
9a7d824a | 6252 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 6253 | ip->insn_mo->name); |
0dd2d296 | 6254 | macro_build ((char *) NULL, &icnt, &expr1, |
9a1f3160 JL |
6255 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6256 | || mips_opts.isa < 3) | |
6257 | ? "addiu" : "daddiu"), | |
9226253a | 6258 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 6259 | return; |
3d3c5039 | 6260 | } |
5c6f5923 GRK |
6261 | if (imm_expr.X_op == O_constant |
6262 | && imm_expr.X_add_number >= 0 | |
6263 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 6264 | { |
0dd2d296 ILT |
6265 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
6266 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 6267 | used_at = 0; |
6e8dda9c | 6268 | } |
5c6f5923 GRK |
6269 | else if (imm_expr.X_op == O_constant |
6270 | && imm_expr.X_add_number > -0x8000 | |
6271 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
6272 | { |
6273 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6274 | macro_build ((char *) NULL, &icnt, &imm_expr, |
9a1f3160 JL |
6275 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6276 | || mips_opts.isa < 3) | |
6277 | ? "addiu" : "daddiu"), | |
9226253a | 6278 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
6279 | used_at = 0; |
6280 | } | |
6281 | else | |
6282 | { | |
d8a1c247 | 6283 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
6284 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
6285 | sreg, AT); | |
670a50eb ILT |
6286 | used_at = 1; |
6287 | } | |
0dd2d296 | 6288 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
6289 | if (used_at) |
6290 | break; | |
6291 | return; | |
3d3c5039 | 6292 | |
8358c818 ILT |
6293 | case M_DSUB_I: |
6294 | dbl = 1; | |
3d3c5039 | 6295 | case M_SUB_I: |
5c6f5923 GRK |
6296 | if (imm_expr.X_op == O_constant |
6297 | && imm_expr.X_add_number > -0x8000 | |
6298 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6299 | { |
6300 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6301 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6302 | dbl ? "daddi" : "addi", |
9226253a | 6303 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6304 | return; |
3d3c5039 | 6305 | } |
d8a1c247 | 6306 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6307 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6308 | dbl ? "dsub" : "sub", |
6309 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 6310 | break; |
3d3c5039 | 6311 | |
8358c818 ILT |
6312 | case M_DSUBU_I: |
6313 | dbl = 1; | |
3d3c5039 | 6314 | case M_SUBU_I: |
5c6f5923 GRK |
6315 | if (imm_expr.X_op == O_constant |
6316 | && imm_expr.X_add_number > -0x8000 | |
6317 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6318 | { |
6319 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6320 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6321 | dbl ? "daddiu" : "addiu", |
9226253a | 6322 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6323 | return; |
3d3c5039 | 6324 | } |
d8a1c247 | 6325 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6326 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6327 | dbl ? "dsubu" : "subu", |
6328 | "d,v,t", dreg, sreg, AT); | |
6329 | break; | |
6330 | ||
6331 | case M_TEQ_I: | |
6332 | s = "teq"; | |
6333 | goto trap; | |
6334 | case M_TGE_I: | |
6335 | s = "tge"; | |
6336 | goto trap; | |
6337 | case M_TGEU_I: | |
6338 | s = "tgeu"; | |
6339 | goto trap; | |
6340 | case M_TLT_I: | |
6341 | s = "tlt"; | |
6342 | goto trap; | |
6343 | case M_TLTU_I: | |
6344 | s = "tltu"; | |
6345 | goto trap; | |
6346 | case M_TNE_I: | |
6347 | s = "tne"; | |
6348 | trap: | |
d8a1c247 | 6349 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6350 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6351 | break; |
3d3c5039 ILT |
6352 | |
6353 | case M_TRUNCWD: | |
6354 | case M_TRUNCWS: | |
3c83da8a | 6355 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6356 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6357 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6358 | ||
6359 | /* | |
6360 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6361 | * or is there a reason for it? | |
6362 | */ | |
fbcfacb7 | 6363 | mips_emit_delays (true); |
3c83da8a | 6364 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6365 | mips_any_noreorder = 1; |
6366 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6367 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6368 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6369 | expr1.X_add_number = 3; |
0dd2d296 | 6370 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6371 | (int) BFD_RELOC_LO16); |
670a50eb | 6372 | expr1.X_add_number = 2; |
0dd2d296 | 6373 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6374 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6375 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6376 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6377 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6378 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6379 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6380 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6381 | --mips_opts.noreorder; |
670a50eb | 6382 | break; |
3d3c5039 ILT |
6383 | |
6384 | case M_ULH: | |
670a50eb ILT |
6385 | s = "lb"; |
6386 | goto ulh; | |
3d3c5039 | 6387 | case M_ULHU: |
670a50eb | 6388 | s = "lbu"; |
3d3c5039 | 6389 | ulh: |
8ea7f4e8 ILT |
6390 | if (offset_expr.X_add_number >= 0x7fff) |
6391 | as_bad ("operand overflow"); | |
670a50eb | 6392 | /* avoid load delay */ |
b9129c6f | 6393 | if (! target_big_endian) |
8ea7f4e8 | 6394 | offset_expr.X_add_number += 1; |
0dd2d296 | 6395 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6396 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6397 | if (! target_big_endian) |
8ea7f4e8 ILT |
6398 | offset_expr.X_add_number -= 1; |
6399 | else | |
6400 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6401 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6402 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6403 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6404 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6405 | break; |
3d3c5039 | 6406 | |
adcf2b9d ILT |
6407 | case M_ULD: |
6408 | s = "ldl"; | |
6409 | s2 = "ldr"; | |
6410 | off = 7; | |
6411 | goto ulw; | |
3d3c5039 | 6412 | case M_ULW: |
adcf2b9d ILT |
6413 | s = "lwl"; |
6414 | s2 = "lwr"; | |
6415 | off = 3; | |
6416 | ulw: | |
6417 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6418 | as_bad ("operand overflow"); |
b9129c6f | 6419 | if (! target_big_endian) |
adcf2b9d ILT |
6420 | offset_expr.X_add_number += off; |
6421 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6422 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6423 | if (! target_big_endian) |
adcf2b9d | 6424 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6425 | else |
adcf2b9d ILT |
6426 | offset_expr.X_add_number += off; |
6427 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6428 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6429 | return; |
3d3c5039 | 6430 | |
adcf2b9d ILT |
6431 | case M_ULD_A: |
6432 | s = "ldl"; | |
6433 | s2 = "ldr"; | |
6434 | off = 7; | |
6435 | goto ulwa; | |
6436 | case M_ULW_A: | |
6437 | s = "lwl"; | |
6438 | s2 = "lwr"; | |
6439 | off = 3; | |
6440 | ulwa: | |
6441 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6442 | if (breg != 0) |
6443 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6444 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6445 | || mips_opts.isa < 3) | |
6446 | ? "addu" : "daddu"), | |
c625fc23 | 6447 | "d,v,t", AT, AT, breg); |
b9129c6f | 6448 | if (! target_big_endian) |
adcf2b9d ILT |
6449 | expr1.X_add_number = off; |
6450 | else | |
6451 | expr1.X_add_number = 0; | |
6452 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6453 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6454 | if (! target_big_endian) |
adcf2b9d ILT |
6455 | expr1.X_add_number = 0; |
6456 | else | |
6457 | expr1.X_add_number = off; | |
6458 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6459 | (int) BFD_RELOC_LO16, AT); | |
6460 | break; | |
6461 | ||
3d3c5039 ILT |
6462 | case M_ULH_A: |
6463 | case M_ULHU_A: | |
0dd2d296 | 6464 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6465 | if (breg != 0) |
6466 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6467 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6468 | || mips_opts.isa < 3) | |
6469 | ? "addu" : "daddu"), | |
c625fc23 | 6470 | "d,v,t", AT, AT, breg); |
b9129c6f | 6471 | if (target_big_endian) |
adcf2b9d ILT |
6472 | expr1.X_add_number = 0; |
6473 | macro_build ((char *) NULL, &icnt, &expr1, | |
6474 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6475 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6476 | if (target_big_endian) |
adcf2b9d | 6477 | expr1.X_add_number = 1; |
670a50eb | 6478 | else |
adcf2b9d ILT |
6479 | expr1.X_add_number = 0; |
6480 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6481 | (int) BFD_RELOC_LO16, AT); | |
6482 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6483 | treg, 8); | |
6484 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6485 | treg, AT); | |
670a50eb | 6486 | break; |
3d3c5039 ILT |
6487 | |
6488 | case M_USH: | |
8ea7f4e8 ILT |
6489 | if (offset_expr.X_add_number >= 0x7fff) |
6490 | as_bad ("operand overflow"); | |
b9129c6f | 6491 | if (target_big_endian) |
8ea7f4e8 | 6492 | offset_expr.X_add_number += 1; |
0dd2d296 | 6493 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6494 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6495 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6496 | if (target_big_endian) |
8ea7f4e8 ILT |
6497 | offset_expr.X_add_number -= 1; |
6498 | else | |
6499 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6500 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6501 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6502 | break; |
3d3c5039 | 6503 | |
adcf2b9d ILT |
6504 | case M_USD: |
6505 | s = "sdl"; | |
6506 | s2 = "sdr"; | |
6507 | off = 7; | |
6508 | goto usw; | |
3d3c5039 | 6509 | case M_USW: |
adcf2b9d ILT |
6510 | s = "swl"; |
6511 | s2 = "swr"; | |
6512 | off = 3; | |
6513 | usw: | |
6514 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6515 | as_bad ("operand overflow"); |
b9129c6f | 6516 | if (! target_big_endian) |
adcf2b9d ILT |
6517 | offset_expr.X_add_number += off; |
6518 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6519 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6520 | if (! target_big_endian) |
adcf2b9d | 6521 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6522 | else |
adcf2b9d ILT |
6523 | offset_expr.X_add_number += off; |
6524 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6525 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6526 | return; |
3d3c5039 | 6527 | |
adcf2b9d ILT |
6528 | case M_USD_A: |
6529 | s = "sdl"; | |
6530 | s2 = "sdr"; | |
6531 | off = 7; | |
6532 | goto uswa; | |
3d3c5039 | 6533 | case M_USW_A: |
adcf2b9d ILT |
6534 | s = "swl"; |
6535 | s2 = "swr"; | |
6536 | off = 3; | |
6537 | uswa: | |
0dd2d296 | 6538 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6539 | if (breg != 0) |
6540 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6541 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6542 | || mips_opts.isa < 3) | |
6543 | ? "addu" : "daddu"), | |
c625fc23 | 6544 | "d,v,t", AT, AT, breg); |
b9129c6f | 6545 | if (! target_big_endian) |
adcf2b9d | 6546 | expr1.X_add_number = off; |
670a50eb | 6547 | else |
adcf2b9d ILT |
6548 | expr1.X_add_number = 0; |
6549 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6550 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6551 | if (! target_big_endian) |
adcf2b9d ILT |
6552 | expr1.X_add_number = 0; |
6553 | else | |
6554 | expr1.X_add_number = off; | |
6555 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6556 | (int) BFD_RELOC_LO16, AT); | |
6557 | break; | |
6558 | ||
6559 | case M_USH_A: | |
6560 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6561 | if (breg != 0) |
6562 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
6563 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
6564 | || mips_opts.isa < 3) | |
6565 | ? "addu" : "daddu"), | |
c625fc23 | 6566 | "d,v,t", AT, AT, breg); |
b9129c6f | 6567 | if (! target_big_endian) |
adcf2b9d ILT |
6568 | expr1.X_add_number = 0; |
6569 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6570 | (int) BFD_RELOC_LO16, AT); | |
6571 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6572 | treg, 8); | |
b9129c6f | 6573 | if (! target_big_endian) |
adcf2b9d ILT |
6574 | expr1.X_add_number = 1; |
6575 | else | |
6576 | expr1.X_add_number = 0; | |
6577 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6578 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6579 | if (! target_big_endian) |
adcf2b9d ILT |
6580 | expr1.X_add_number = 0; |
6581 | else | |
6582 | expr1.X_add_number = 1; | |
6583 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6584 | (int) BFD_RELOC_LO16, AT); | |
6585 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6586 | treg, 8); | |
6587 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6588 | treg, AT); | |
670a50eb | 6589 | break; |
3d3c5039 ILT |
6590 | |
6591 | default: | |
9218cee0 ILT |
6592 | /* FIXME: Check if this is one of the itbl macros, since they |
6593 | are added dynamically. */ | |
670a50eb | 6594 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 6595 | break; |
3d3c5039 | 6596 | } |
3c83da8a | 6597 | if (mips_opts.noat) |
670a50eb | 6598 | as_warn ("Macro used $at after \".set noat\""); |
3d3c5039 ILT |
6599 | } |
6600 | ||
cc5703cd | 6601 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6602 | |
3d3c5039 | 6603 | static void |
cc5703cd | 6604 | mips16_macro (ip) |
3d3c5039 ILT |
6605 | struct mips_cl_insn *ip; |
6606 | { | |
cc5703cd ILT |
6607 | int mask; |
6608 | int xreg, yreg, zreg, tmp; | |
6609 | int icnt; | |
6610 | expressionS expr1; | |
6611 | int dbl; | |
6612 | const char *s, *s2, *s3; | |
3d3c5039 | 6613 | |
cc5703cd | 6614 | mask = ip->insn_mo->mask; |
3d3c5039 | 6615 | |
cc5703cd ILT |
6616 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6617 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6618 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6619 | |
cc5703cd | 6620 | icnt = 0; |
8358c818 | 6621 | |
cc5703cd ILT |
6622 | expr1.X_op = O_constant; |
6623 | expr1.X_op_symbol = NULL; | |
6624 | expr1.X_add_symbol = NULL; | |
6625 | expr1.X_add_number = 1; | |
8358c818 | 6626 | |
cc5703cd | 6627 | dbl = 0; |
517078c1 | 6628 | |
cc5703cd ILT |
6629 | switch (mask) |
6630 | { | |
6631 | default: | |
6632 | internalError (); | |
6633 | ||
6634 | case M_DDIV_3: | |
6635 | dbl = 1; | |
6636 | case M_DIV_3: | |
6637 | s = "mflo"; | |
6638 | goto do_div3; | |
6639 | case M_DREM_3: | |
6640 | dbl = 1; | |
6641 | case M_REM_3: | |
6642 | s = "mfhi"; | |
6643 | do_div3: | |
fbcfacb7 | 6644 | mips_emit_delays (true); |
3c83da8a | 6645 | ++mips_opts.noreorder; |
cc5703cd ILT |
6646 | mips_any_noreorder = 1; |
6647 | macro_build ((char *) NULL, &icnt, NULL, | |
6648 | dbl ? "ddiv" : "div", | |
6649 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6650 | expr1.X_add_number = 2; |
cc5703cd | 6651 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6652 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6653 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6654 | since that causes an overflow. We should do that as well, | |
6655 | but I don't see how to do the comparisons without a temporary | |
6656 | register. */ | |
3c83da8a | 6657 | --mips_opts.noreorder; |
cc5703cd ILT |
6658 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6659 | break; | |
6660 | ||
6661 | case M_DIVU_3: | |
6662 | s = "divu"; | |
6663 | s2 = "mflo"; | |
6664 | goto do_divu3; | |
6665 | case M_REMU_3: | |
6666 | s = "divu"; | |
6667 | s2 = "mfhi"; | |
6668 | goto do_divu3; | |
6669 | case M_DDIVU_3: | |
6670 | s = "ddivu"; | |
6671 | s2 = "mflo"; | |
6672 | goto do_divu3; | |
6673 | case M_DREMU_3: | |
6674 | s = "ddivu"; | |
6675 | s2 = "mfhi"; | |
6676 | do_divu3: | |
fbcfacb7 | 6677 | mips_emit_delays (true); |
3c83da8a | 6678 | ++mips_opts.noreorder; |
cc5703cd ILT |
6679 | mips_any_noreorder = 1; |
6680 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6681 | expr1.X_add_number = 2; |
cc5703cd | 6682 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd | 6683 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
3c83da8a | 6684 | --mips_opts.noreorder; |
cc5703cd ILT |
6685 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6686 | break; | |
6687 | ||
08438bef ILT |
6688 | case M_DMUL: |
6689 | dbl = 1; | |
6690 | case M_MUL: | |
6691 | macro_build ((char *) NULL, &icnt, NULL, | |
6692 | dbl ? "dmultu" : "multu", | |
6693 | "x,y", xreg, yreg); | |
6694 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6695 | return; | |
6696 | ||
cc5703cd ILT |
6697 | case M_DSUBU_I: |
6698 | dbl = 1; | |
6699 | goto do_subu; | |
6700 | case M_SUBU_I: | |
6701 | do_subu: | |
5c6f5923 GRK |
6702 | if (imm_expr.X_op != O_constant) |
6703 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6704 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6705 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6706 | dbl ? "daddiu" : "addiu", | |
6707 | "y,x,4", yreg, xreg); | |
6708 | break; | |
6709 | ||
6710 | case M_SUBU_I_2: | |
5c6f5923 GRK |
6711 | if (imm_expr.X_op != O_constant) |
6712 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6713 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6714 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6715 | "x,k", xreg); | |
6716 | break; | |
6717 | ||
6718 | case M_DSUBU_I_2: | |
5c6f5923 GRK |
6719 | if (imm_expr.X_op != O_constant) |
6720 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6721 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6722 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6723 | "y,j", yreg); | |
6724 | break; | |
6725 | ||
6726 | case M_BEQ: | |
6727 | s = "cmp"; | |
6728 | s2 = "bteqz"; | |
6729 | goto do_branch; | |
6730 | case M_BNE: | |
6731 | s = "cmp"; | |
6732 | s2 = "btnez"; | |
6733 | goto do_branch; | |
6734 | case M_BLT: | |
6735 | s = "slt"; | |
6736 | s2 = "btnez"; | |
6737 | goto do_branch; | |
6738 | case M_BLTU: | |
6739 | s = "sltu"; | |
6740 | s2 = "btnez"; | |
6741 | goto do_branch; | |
6742 | case M_BLE: | |
6743 | s = "slt"; | |
6744 | s2 = "bteqz"; | |
6745 | goto do_reverse_branch; | |
6746 | case M_BLEU: | |
6747 | s = "sltu"; | |
6748 | s2 = "bteqz"; | |
6749 | goto do_reverse_branch; | |
6750 | case M_BGE: | |
6751 | s = "slt"; | |
6752 | s2 = "bteqz"; | |
6753 | goto do_branch; | |
6754 | case M_BGEU: | |
6755 | s = "sltu"; | |
6756 | s2 = "bteqz"; | |
6757 | goto do_branch; | |
6758 | case M_BGT: | |
6759 | s = "slt"; | |
6760 | s2 = "btnez"; | |
6761 | goto do_reverse_branch; | |
6762 | case M_BGTU: | |
6763 | s = "sltu"; | |
6764 | s2 = "btnez"; | |
6765 | ||
6766 | do_reverse_branch: | |
6767 | tmp = xreg; | |
6768 | xreg = yreg; | |
6769 | yreg = tmp; | |
6770 | ||
6771 | do_branch: | |
6772 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6773 | xreg, yreg); | |
6774 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6775 | break; | |
6776 | ||
6777 | case M_BEQ_I: | |
6778 | s = "cmpi"; | |
6779 | s2 = "bteqz"; | |
6780 | s3 = "x,U"; | |
6781 | goto do_branch_i; | |
6782 | case M_BNE_I: | |
6783 | s = "cmpi"; | |
6784 | s2 = "btnez"; | |
6785 | s3 = "x,U"; | |
6786 | goto do_branch_i; | |
6787 | case M_BLT_I: | |
6788 | s = "slti"; | |
6789 | s2 = "btnez"; | |
6790 | s3 = "x,8"; | |
6791 | goto do_branch_i; | |
6792 | case M_BLTU_I: | |
6793 | s = "sltiu"; | |
6794 | s2 = "btnez"; | |
6795 | s3 = "x,8"; | |
6796 | goto do_branch_i; | |
6797 | case M_BLE_I: | |
6798 | s = "slti"; | |
6799 | s2 = "btnez"; | |
6800 | s3 = "x,8"; | |
6801 | goto do_addone_branch_i; | |
6802 | case M_BLEU_I: | |
6803 | s = "sltiu"; | |
6804 | s2 = "btnez"; | |
6805 | s3 = "x,8"; | |
6806 | goto do_addone_branch_i; | |
6807 | case M_BGE_I: | |
6808 | s = "slti"; | |
6809 | s2 = "bteqz"; | |
6810 | s3 = "x,8"; | |
6811 | goto do_branch_i; | |
6812 | case M_BGEU_I: | |
6813 | s = "sltiu"; | |
6814 | s2 = "bteqz"; | |
6815 | s3 = "x,8"; | |
6816 | goto do_branch_i; | |
6817 | case M_BGT_I: | |
6818 | s = "slti"; | |
6819 | s2 = "bteqz"; | |
6820 | s3 = "x,8"; | |
6821 | goto do_addone_branch_i; | |
6822 | case M_BGTU_I: | |
6823 | s = "sltiu"; | |
6824 | s2 = "bteqz"; | |
6825 | s3 = "x,8"; | |
6826 | ||
6827 | do_addone_branch_i: | |
5c6f5923 GRK |
6828 | if (imm_expr.X_op != O_constant) |
6829 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6830 | ++imm_expr.X_add_number; |
6831 | ||
6832 | do_branch_i: | |
6833 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6834 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6835 | break; | |
18e0764d ILT |
6836 | |
6837 | case M_ABS: | |
6838 | expr1.X_add_number = 0; | |
6839 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6840 | if (xreg != yreg) | |
6841 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6842 | "move", "y,X", xreg, yreg); | |
6843 | expr1.X_add_number = 2; | |
6844 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6845 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6846 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6847 | } |
6848 | } | |
6849 | ||
aa2e0460 KR |
6850 | /* For consistency checking, verify that all bits are specified either |
6851 | by the match/mask part of the instruction definition, or by the | |
6852 | operand list. */ | |
6853 | static int | |
6854 | validate_mips_insn (opc) | |
6855 | const struct mips_opcode *opc; | |
6856 | { | |
6857 | const char *p = opc->args; | |
6858 | char c; | |
6859 | unsigned long used_bits = opc->mask; | |
6860 | ||
6861 | if ((used_bits & opc->match) != opc->match) | |
6862 | { | |
6863 | as_bad ("internal: bad mips opcode (mask error): %s %s", | |
6864 | opc->name, opc->args); | |
6865 | return 0; | |
6866 | } | |
6867 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6868 | while (*p) | |
6869 | switch (c = *p++) | |
6870 | { | |
6871 | case ',': break; | |
6872 | case '(': break; | |
6873 | case ')': break; | |
6874 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6875 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6876 | case 'A': break; | |
6877 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
6878 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
6879 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6880 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6881 | case 'F': break; | |
6882 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6883 | case 'I': break; | |
6884 | case 'L': break; | |
6885 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6886 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6887 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6888 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6889 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6890 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6891 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6892 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6893 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6894 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6895 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6896 | case 'f': break; | |
6897 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6898 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6899 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6900 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6901 | case 'l': break; | |
6902 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6903 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6904 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6905 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6906 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6907 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6908 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6909 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6910 | case 'x': break; | |
6911 | case 'z': break; | |
aa2e0460 | 6912 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
1c6f3441 | 6913 | /* start-sanitize-vr5400 */ |
aa2e0460 KR |
6914 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
6915 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
6916 | case '[': break; | |
6917 | case ']': break; | |
6918 | /* end-sanitize-vr5400 */ | |
6919 | default: | |
6920 | as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s", | |
6921 | c, opc->name, opc->args); | |
6922 | return 0; | |
6923 | } | |
6924 | #undef USE_BITS | |
6925 | /* Some of the trapping instructions (break, t*, sdbbp) have "code" | |
6926 | fields that cannot currently be set by assembly code. Ignore them | |
6927 | for now. */ | |
6928 | if (opc->pinfo & INSN_TRAP) | |
6929 | { | |
6930 | static const char *const trap_insns[] = { | |
6931 | "break", "sdbbp", | |
6932 | "teq", "tge", "tgeu", "tlt", "tltu", "tne", | |
6933 | }; | |
6934 | int i; | |
6935 | for (i = sizeof(trap_insns)/sizeof(trap_insns[0]) - 1; i >= 0; i--) | |
6936 | if (!strcmp (trap_insns[i], opc->name)) | |
6937 | { | |
6938 | used_bits |= 0xffc0; | |
6939 | break; | |
6940 | } | |
6941 | } | |
6942 | if (used_bits != 0xffffffff) | |
6943 | { | |
6944 | as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s", | |
6945 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
6946 | return 0; | |
6947 | } | |
6948 | return 1; | |
6949 | } | |
6950 | ||
cc5703cd ILT |
6951 | /* This routine assembles an instruction into its binary format. As a |
6952 | side effect, it sets one of the global variables imm_reloc or | |
6953 | offset_reloc to the type of relocation to do if one of the operands | |
6954 | is an address expression. */ | |
6955 | ||
6956 | static void | |
6957 | mips_ip (str, ip) | |
6958 | char *str; | |
6959 | struct mips_cl_insn *ip; | |
6960 | { | |
6961 | char *s; | |
6962 | const char *args; | |
6963 | char c; | |
6964 | struct mips_opcode *insn; | |
6965 | char *argsStart; | |
6966 | unsigned int regno; | |
6967 | unsigned int lastregno = 0; | |
6968 | char *s_reset; | |
6969 | ||
6970 | insn_error = NULL; | |
6971 | ||
e2e5acfa | 6972 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 6973 | continue; |
1857d1e6 | 6974 | if (isspace (*s)) |
e2e5acfa | 6975 | *s++ = '\0'; |
1857d1e6 | 6976 | |
cc5703cd ILT |
6977 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
6978 | { | |
6979 | insn_error = "unrecognized opcode"; | |
6980 | return; | |
6981 | } | |
6982 | argsStart = s; | |
6983 | for (;;) | |
6984 | { | |
6985 | int insn_isa; | |
a652f74c | 6986 | boolean ok; |
cc5703cd ILT |
6987 | |
6988 | assert (strcmp (insn->name, str) == 0); | |
6989 | ||
1c6f3441 | 6990 | if ((insn->membership & INSN_ISA) == INSN_ISA1) |
931a1858 | 6991 | insn_isa = 1; |
5c6f5923 | 6992 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 6993 | insn_isa = 2; |
5c6f5923 | 6994 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 6995 | insn_isa = 3; |
5c6f5923 | 6996 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
6997 | insn_isa = 4; |
6998 | else | |
931a1858 | 6999 | insn_isa = 15; |
cc5703cd | 7000 | |
a652f74c ILT |
7001 | if (insn_isa <= mips_opts.isa) |
7002 | ok = true; | |
7003 | else if (insn->pinfo == INSN_MACRO) | |
7004 | ok = false; | |
7005 | else if ((mips_4650 && (insn->membership & INSN_4650) != 0) | |
7006 | || (mips_4010 && (insn->membership & INSN_4010) != 0) | |
7007 | || (mips_4100 && (insn->membership & INSN_4100) != 0) | |
2d035a50 GRK |
7008 | /* start-sanitize-vr4320 */ |
7009 | || (mips_4320 && (insn->membership & INSN_4320) != 0) | |
7010 | /* end-sanitize-vr4320 */ | |
42444087 GRK |
7011 | /* start-sanitize-tx49 */ |
7012 | || (mips_4900 && (insn->membership & INSN_4900) != 0) | |
7013 | /* end-sanitize-tx49 */ | |
a652f74c ILT |
7014 | /* start-sanitize-r5900 */ |
7015 | || (mips_5900 && (insn->membership & INSN_5900) != 0) | |
7016 | /* end-sanitize-r5900 */ | |
aa2e0460 KR |
7017 | /* start-sanitize-vr5400 */ |
7018 | || (mips_5400 && (insn->membership & INSN_5400) != 0) | |
7019 | /* end-sanitize-vr5400 */ | |
a652f74c | 7020 | || (mips_3900 && (insn->membership & INSN_3900) != 0)) |
1c6f3441 | 7021 | ok = true; |
a652f74c ILT |
7022 | else |
7023 | ok = false; | |
7024 | ||
b2cf4548 DE |
7025 | if (insn->pinfo != INSN_MACRO) |
7026 | { | |
7027 | if (mips_4650 && (insn->pinfo & FP_D) != 0) | |
7028 | ok = false; | |
7029 | /* start-sanitize-r5900 */ | |
7030 | if (mips_5900 && (insn->pinfo & FP_D) != 0) | |
7031 | ok = false; | |
7032 | /* end-sanitize-r5900 */ | |
7033 | } | |
1c6f3441 | 7034 | |
a652f74c | 7035 | if (! ok) |
cc5703cd ILT |
7036 | { |
7037 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7038 | && strcmp (insn->name, insn[1].name) == 0) | |
7039 | { | |
7040 | ++insn; | |
7041 | continue; | |
7042 | } | |
6fd819cf GRK |
7043 | if (insn_isa == 15 |
7044 | || insn_isa <= mips_opts.isa) | |
cc5703cd ILT |
7045 | insn_error = "opcode not supported on this processor"; |
7046 | else | |
7047 | { | |
7048 | static char buf[100]; | |
7049 | ||
7050 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
7051 | insn_error = buf; | |
7052 | } | |
7053 | return; | |
7054 | } | |
8358c818 | 7055 | |
670a50eb ILT |
7056 | ip->insn_mo = insn; |
7057 | ip->insn_opcode = insn->match; | |
7058 | for (args = insn->args;; ++args) | |
7059 | { | |
7060 | if (*s == ' ') | |
7061 | ++s; | |
7062 | switch (*args) | |
7063 | { | |
7064 | case '\0': /* end of args */ | |
7065 | if (*s == '\0') | |
7066 | return; | |
7067 | break; | |
3d3c5039 ILT |
7068 | |
7069 | case ',': | |
670a50eb ILT |
7070 | if (*s++ == *args) |
7071 | continue; | |
7072 | s--; | |
7073 | switch (*++args) | |
7074 | { | |
3d3c5039 ILT |
7075 | case 'r': |
7076 | case 'v': | |
670a50eb ILT |
7077 | ip->insn_opcode |= lastregno << 21; |
7078 | continue; | |
3d3c5039 ILT |
7079 | |
7080 | case 'w': | |
7081 | case 'W': | |
670a50eb ILT |
7082 | ip->insn_opcode |= lastregno << 16; |
7083 | continue; | |
3d3c5039 ILT |
7084 | |
7085 | case 'V': | |
670a50eb ILT |
7086 | ip->insn_opcode |= lastregno << 11; |
7087 | continue; | |
3d3c5039 | 7088 | } |
670a50eb | 7089 | break; |
3d3c5039 ILT |
7090 | |
7091 | case '(': | |
670a50eb ILT |
7092 | /* handle optional base register. |
7093 | Either the base register is omitted or | |
7094 | we must have a left paren. */ | |
7095 | /* this is dependent on the next operand specifier | |
7096 | is a 'b' for base register */ | |
7097 | assert (args[1] == 'b'); | |
7098 | if (*s == '\0') | |
7099 | return; | |
3d3c5039 | 7100 | |
670a50eb | 7101 | case ')': /* these must match exactly */ |
aa2e0460 KR |
7102 | /* start-sanitize-vr5400 */ |
7103 | case '[': | |
7104 | case ']': | |
7105 | /* end-sanitize-vr5400 */ | |
670a50eb | 7106 | if (*s++ == *args) |
3d3c5039 | 7107 | continue; |
670a50eb ILT |
7108 | break; |
7109 | ||
7110 | case '<': /* must be at least one digit */ | |
7111 | /* | |
7112 | * According to the manual, if the shift amount is greater | |
7113 | * than 31 or less than 0 the the shift amount should be | |
7114 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 7115 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
7116 | */ |
7117 | my_getExpression (&imm_expr, s); | |
7118 | check_absolute_expr (ip, &imm_expr); | |
7119 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7120 | { | |
58d4951d ILT |
7121 | as_warn ("Improper shift amount (%ld)", |
7122 | (long) imm_expr.X_add_number); | |
9226253a | 7123 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
7124 | } |
7125 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 7126 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7127 | s = expr_end; |
7128 | continue; | |
7129 | ||
56c96faa ILT |
7130 | case '>': /* shift amount minus 32 */ |
7131 | my_getExpression (&imm_expr, s); | |
7132 | check_absolute_expr (ip, &imm_expr); | |
7133 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7134 | || (unsigned long) imm_expr.X_add_number > 63) | |
7135 | break; | |
7136 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7137 | imm_expr.X_op = O_absent; | |
7138 | s = expr_end; | |
7139 | continue; | |
7140 | ||
9226253a | 7141 | case 'k': /* cache code */ |
d8a1c247 | 7142 | case 'h': /* prefx code */ |
9226253a ILT |
7143 | my_getExpression (&imm_expr, s); |
7144 | check_absolute_expr (ip, &imm_expr); | |
7145 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7146 | { | |
d8a1c247 KR |
7147 | as_warn ("Invalid value for `%s' (%lu)", |
7148 | ip->insn_mo->name, | |
9226253a ILT |
7149 | (unsigned long) imm_expr.X_add_number); |
7150 | imm_expr.X_add_number &= 0x1f; | |
7151 | } | |
d8a1c247 KR |
7152 | if (*args == 'k') |
7153 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7154 | else | |
7155 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
7156 | imm_expr.X_op = O_absent; |
7157 | s = expr_end; | |
7158 | continue; | |
7159 | ||
670a50eb ILT |
7160 | case 'c': /* break code */ |
7161 | my_getExpression (&imm_expr, s); | |
7162 | check_absolute_expr (ip, &imm_expr); | |
7163 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
7164 | as_warn ("Illegal break code (%ld)", |
7165 | (long) imm_expr.X_add_number); | |
670a50eb | 7166 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 7167 | imm_expr.X_op = O_absent; |
670a50eb ILT |
7168 | s = expr_end; |
7169 | continue; | |
7170 | ||
918692a5 ILT |
7171 | case 'B': /* syscall code */ |
7172 | my_getExpression (&imm_expr, s); | |
7173 | check_absolute_expr (ip, &imm_expr); | |
7174 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
7175 | as_warn ("Illegal syscall code (%ld)", |
7176 | (long) imm_expr.X_add_number); | |
918692a5 | 7177 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 7178 | imm_expr.X_op = O_absent; |
918692a5 ILT |
7179 | s = expr_end; |
7180 | continue; | |
7181 | ||
0aa07269 ILT |
7182 | case 'C': /* Coprocessor code */ |
7183 | my_getExpression (&imm_expr, s); | |
7184 | check_absolute_expr (ip, &imm_expr); | |
7185 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
7186 | { | |
58d4951d ILT |
7187 | as_warn ("Coproccesor code > 25 bits (%ld)", |
7188 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
7189 | imm_expr.X_add_number &= ((1<<25) - 1); |
7190 | } | |
7191 | ip->insn_opcode |= imm_expr.X_add_number; | |
7192 | imm_expr.X_op = O_absent; | |
7193 | s = expr_end; | |
7194 | continue; | |
7195 | ||
65d2c7d3 JL |
7196 | case 'P': /* Performance register */ |
7197 | my_getExpression (&imm_expr, s); | |
7198 | check_absolute_expr (ip, &imm_expr); | |
7199 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) | |
7200 | { | |
7201 | as_warn ("Invalidate performance regster (%ld)", | |
7202 | (long) imm_expr.X_add_number); | |
7203 | imm_expr.X_add_number &= 1; | |
7204 | } | |
7205 | ip->insn_opcode |= (imm_expr.X_add_number << 1); | |
7206 | imm_expr.X_op = O_absent; | |
7207 | s = expr_end; | |
7208 | continue; | |
7209 | ||
670a50eb ILT |
7210 | case 'b': /* base register */ |
7211 | case 'd': /* destination register */ | |
7212 | case 's': /* source register */ | |
7213 | case 't': /* target register */ | |
7214 | case 'r': /* both target and source */ | |
7215 | case 'v': /* both dest and source */ | |
7216 | case 'w': /* both dest and target */ | |
918692a5 ILT |
7217 | case 'E': /* coprocessor target register */ |
7218 | case 'G': /* coprocessor destination register */ | |
8358c818 | 7219 | case 'x': /* ignore register name */ |
ff3a5c18 | 7220 | case 'z': /* must be zero register */ |
670a50eb ILT |
7221 | s_reset = s; |
7222 | if (s[0] == '$') | |
7223 | { | |
7224 | if (isdigit (s[1])) | |
7225 | { | |
7226 | ++s; | |
7227 | regno = 0; | |
7228 | do | |
7229 | { | |
7230 | regno *= 10; | |
7231 | regno += *s - '0'; | |
7232 | ++s; | |
7233 | } | |
7234 | while (isdigit (*s)); | |
0aa07269 ILT |
7235 | if (regno > 31) |
7236 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 7237 | } |
0dd2d296 ILT |
7238 | else if (*args == 'E' || *args == 'G') |
7239 | goto notreg; | |
7240 | else | |
670a50eb | 7241 | { |
0aa07269 ILT |
7242 | if (s[1] == 'f' && s[2] == 'p') |
7243 | { | |
7244 | s += 3; | |
9226253a | 7245 | regno = FP; |
0aa07269 ILT |
7246 | } |
7247 | else if (s[1] == 's' && s[2] == 'p') | |
7248 | { | |
7249 | s += 3; | |
9226253a | 7250 | regno = SP; |
0aa07269 ILT |
7251 | } |
7252 | else if (s[1] == 'g' && s[2] == 'p') | |
7253 | { | |
7254 | s += 3; | |
9226253a | 7255 | regno = GP; |
0aa07269 ILT |
7256 | } |
7257 | else if (s[1] == 'a' && s[2] == 't') | |
7258 | { | |
7259 | s += 3; | |
9226253a | 7260 | regno = AT; |
0aa07269 | 7261 | } |
b2b8c24e ILT |
7262 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
7263 | { | |
7264 | s += 4; | |
7265 | regno = KT0; | |
7266 | } | |
7267 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7268 | { | |
7269 | s += 4; | |
7270 | regno = KT1; | |
7271 | } | |
efec4a28 DP |
7272 | else if (itbl_have_entries) |
7273 | { | |
7274 | char *p, *n; | |
7275 | int r; | |
7276 | ||
7277 | p = s+1; /* advance past '$' */ | |
9218cee0 | 7278 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
7279 | |
7280 | /* See if this is a register defined in an | |
7281 | itbl entry */ | |
9218cee0 ILT |
7282 | r = itbl_get_reg_val (n); |
7283 | if (r) | |
efec4a28 | 7284 | { |
9218cee0 ILT |
7285 | /* Get_field advances to the start of |
7286 | the next field, so we need to back | |
7287 | rack to the end of the last field. */ | |
efec4a28 | 7288 | if (p) |
9218cee0 | 7289 | s = p - 1; |
efec4a28 | 7290 | else |
9218cee0 | 7291 | s = strchr (s,'\0'); |
efec4a28 DP |
7292 | regno = r; |
7293 | } | |
7294 | else | |
7295 | goto notreg; | |
7296 | } | |
0aa07269 ILT |
7297 | else |
7298 | goto notreg; | |
670a50eb | 7299 | } |
9753202d | 7300 | if (regno == AT |
3c83da8a | 7301 | && ! mips_opts.noat |
9753202d ILT |
7302 | && *args != 'E' |
7303 | && *args != 'G') | |
13fe1379 | 7304 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
7305 | c = *args; |
7306 | if (*s == ' ') | |
7307 | s++; | |
7308 | if (args[1] != *s) | |
7309 | { | |
7310 | if (c == 'r' || c == 'v' || c == 'w') | |
7311 | { | |
7312 | regno = lastregno; | |
7313 | s = s_reset; | |
7314 | args++; | |
7315 | } | |
7316 | } | |
ff3a5c18 ILT |
7317 | /* 'z' only matches $0. */ |
7318 | if (c == 'z' && regno != 0) | |
7319 | break; | |
efec4a28 DP |
7320 | |
7321 | /* Now that we have assembled one operand, we use the args string | |
7322 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
7323 | switch (c) |
7324 | { | |
3d3c5039 ILT |
7325 | case 'r': |
7326 | case 's': | |
7327 | case 'v': | |
7328 | case 'b': | |
670a50eb ILT |
7329 | ip->insn_opcode |= regno << 21; |
7330 | break; | |
3d3c5039 | 7331 | case 'd': |
918692a5 | 7332 | case 'G': |
670a50eb ILT |
7333 | ip->insn_opcode |= regno << 11; |
7334 | break; | |
3d3c5039 ILT |
7335 | case 'w': |
7336 | case 't': | |
918692a5 | 7337 | case 'E': |
670a50eb | 7338 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
7339 | break; |
7340 | case 'x': | |
7341 | /* This case exists because on the r3000 trunc | |
7342 | expands into a macro which requires a gp | |
7343 | register. On the r6000 or r4000 it is | |
7344 | assembled into a single instruction which | |
7345 | ignores the register. Thus the insn version | |
7346 | is MIPS_ISA2 and uses 'x', and the macro | |
7347 | version is MIPS_ISA1 and uses 't'. */ | |
7348 | break; | |
ff3a5c18 ILT |
7349 | case 'z': |
7350 | /* This case is for the div instruction, which | |
7351 | acts differently if the destination argument | |
7352 | is $0. This only matches $0, and is checked | |
7353 | outside the switch. */ | |
7354 | break; | |
efec4a28 DP |
7355 | case 'D': |
7356 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7357 | break; | |
9218cee0 ILT |
7358 | /* What about all other operands like 'i', which |
7359 | can be specified in the opcode table? */ | |
3d3c5039 | 7360 | } |
670a50eb ILT |
7361 | lastregno = regno; |
7362 | continue; | |
3d3c5039 ILT |
7363 | } |
7364 | notreg: | |
670a50eb ILT |
7365 | switch (*args++) |
7366 | { | |
3d3c5039 ILT |
7367 | case 'r': |
7368 | case 'v': | |
670a50eb ILT |
7369 | ip->insn_opcode |= lastregno << 21; |
7370 | continue; | |
3d3c5039 | 7371 | case 'w': |
670a50eb ILT |
7372 | ip->insn_opcode |= lastregno << 16; |
7373 | continue; | |
3d3c5039 | 7374 | } |
670a50eb | 7375 | break; |
3d3c5039 | 7376 | |
670a50eb ILT |
7377 | case 'D': /* floating point destination register */ |
7378 | case 'S': /* floating point source register */ | |
7379 | case 'T': /* floating point target register */ | |
d8a1c247 | 7380 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
7381 | case 'V': |
7382 | case 'W': | |
670a50eb ILT |
7383 | s_reset = s; |
7384 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
7385 | { | |
7386 | s += 2; | |
7387 | regno = 0; | |
7388 | do | |
7389 | { | |
7390 | regno *= 10; | |
7391 | regno += *s - '0'; | |
7392 | ++s; | |
7393 | } | |
7394 | while (isdigit (*s)); | |
7395 | ||
7396 | if (regno > 31) | |
7397 | as_bad ("Invalid float register number (%d)", regno); | |
7398 | ||
9226253a | 7399 | if ((regno & 1) != 0 |
3c83da8a | 7400 | && mips_opts.isa < 3 |
538034cf ILT |
7401 | && ! (strcmp (str, "mtc1") == 0 |
7402 | || strcmp (str, "mfc1") == 0 | |
7403 | || strcmp (str, "lwc1") == 0 | |
7404 | || strcmp (str, "swc1") == 0 | |
7405 | || strcmp (str, "l.s") == 0 | |
7406 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
7407 | as_warn ("Float register should be even, was %d", |
7408 | regno); | |
7409 | ||
7410 | c = *args; | |
7411 | if (*s == ' ') | |
7412 | s++; | |
7413 | if (args[1] != *s) | |
7414 | { | |
7415 | if (c == 'V' || c == 'W') | |
7416 | { | |
7417 | regno = lastregno; | |
7418 | s = s_reset; | |
7419 | args++; | |
3d3c5039 ILT |
7420 | } |
7421 | } | |
670a50eb ILT |
7422 | switch (c) |
7423 | { | |
3d3c5039 | 7424 | case 'D': |
670a50eb ILT |
7425 | ip->insn_opcode |= regno << 6; |
7426 | break; | |
3d3c5039 ILT |
7427 | case 'V': |
7428 | case 'S': | |
670a50eb ILT |
7429 | ip->insn_opcode |= regno << 11; |
7430 | break; | |
3d3c5039 ILT |
7431 | case 'W': |
7432 | case 'T': | |
670a50eb | 7433 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
7434 | break; |
7435 | case 'R': | |
7436 | ip->insn_opcode |= regno << 21; | |
7437 | break; | |
3d3c5039 | 7438 | } |
670a50eb ILT |
7439 | lastregno = regno; |
7440 | continue; | |
3d3c5039 | 7441 | } |
670a50eb ILT |
7442 | switch (*args++) |
7443 | { | |
3d3c5039 | 7444 | case 'V': |
670a50eb ILT |
7445 | ip->insn_opcode |= lastregno << 11; |
7446 | continue; | |
3d3c5039 | 7447 | case 'W': |
670a50eb ILT |
7448 | ip->insn_opcode |= lastregno << 16; |
7449 | continue; | |
3d3c5039 | 7450 | } |
670a50eb | 7451 | break; |
3d3c5039 ILT |
7452 | |
7453 | case 'I': | |
670a50eb | 7454 | my_getExpression (&imm_expr, s); |
9753202d ILT |
7455 | if (imm_expr.X_op != O_big |
7456 | && imm_expr.X_op != O_constant) | |
7457 | insn_error = "absolute expression required"; | |
670a50eb ILT |
7458 | s = expr_end; |
7459 | continue; | |
3d3c5039 ILT |
7460 | |
7461 | case 'A': | |
670a50eb ILT |
7462 | my_getExpression (&offset_expr, s); |
7463 | imm_reloc = BFD_RELOC_32; | |
7464 | s = expr_end; | |
7465 | continue; | |
3d3c5039 ILT |
7466 | |
7467 | case 'F': | |
19ed8960 ILT |
7468 | case 'L': |
7469 | case 'f': | |
7470 | case 'l': | |
7471 | { | |
7472 | int f64; | |
7473 | char *save_in; | |
7474 | char *err; | |
7475 | unsigned char temp[8]; | |
604633ae ILT |
7476 | int len; |
7477 | unsigned int length; | |
19ed8960 ILT |
7478 | segT seg; |
7479 | subsegT subseg; | |
7480 | char *p; | |
7481 | ||
7482 | /* These only appear as the last operand in an | |
7483 | instruction, and every instruction that accepts | |
7484 | them in any variant accepts them in all variants. | |
7485 | This means we don't have to worry about backing out | |
7486 | any changes if the instruction does not match. | |
7487 | ||
7488 | The difference between them is the size of the | |
7489 | floating point constant and where it goes. For 'F' | |
7490 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7491 | is 32 bits. Where the constant is placed is based | |
7492 | on how the MIPS assembler does things: | |
7493 | F -- .rdata | |
7494 | L -- .lit8 | |
7495 | f -- immediate value | |
7496 | l -- .lit4 | |
0dd2d296 | 7497 | |
55933a58 ILT |
7498 | The .lit4 and .lit8 sections are only used if |
7499 | permitted by the -G argument. | |
7500 | ||
7501 | When generating embedded PIC code, we use the | |
7502 | .lit8 section but not the .lit4 section (we can do | |
7503 | .lit4 inline easily; we need to put .lit8 | |
7504 | somewhere in the data segment, and using .lit8 | |
7505 | permits the linker to eventually combine identical | |
7506 | .lit8 entries). */ | |
19ed8960 ILT |
7507 | |
7508 | f64 = *args == 'F' || *args == 'L'; | |
7509 | ||
7510 | save_in = input_line_pointer; | |
7511 | input_line_pointer = s; | |
604633ae ILT |
7512 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
7513 | length = len; | |
19ed8960 ILT |
7514 | s = input_line_pointer; |
7515 | input_line_pointer = save_in; | |
7516 | if (err != NULL && *err != '\0') | |
7517 | { | |
7518 | as_bad ("Bad floating point constant: %s", err); | |
7519 | memset (temp, '\0', sizeof temp); | |
7520 | length = f64 ? 8 : 4; | |
7521 | } | |
7522 | ||
7523 | assert (length == (f64 ? 8 : 4)); | |
7524 | ||
0dd2d296 | 7525 | if (*args == 'f' |
55933a58 | 7526 | || (*args == 'l' |
1dc1e798 KR |
7527 | && (! USE_GLOBAL_POINTER_OPT |
7528 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
7529 | || g_switch_value < 4 |
7530 | || (temp[0] == 0 && temp[1] == 0) | |
7531 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
7532 | { |
7533 | imm_expr.X_op = O_constant; | |
b9129c6f | 7534 | if (! target_big_endian) |
a5586bdc | 7535 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 7536 | else |
a5586bdc ILT |
7537 | imm_expr.X_add_number = bfd_getb32 (temp); |
7538 | } | |
7539 | else if (length > 4 | |
7540 | && ((temp[0] == 0 && temp[1] == 0) | |
7541 | || (temp[2] == 0 && temp[3] == 0)) | |
7542 | && ((temp[4] == 0 && temp[5] == 0) | |
7543 | || (temp[6] == 0 && temp[7] == 0))) | |
7544 | { | |
7545 | /* The value is simple enough to load with a | |
7546 | couple of instructions. In mips1 mode, set | |
7547 | imm_expr to the high order 32 bits and | |
7548 | offset_expr to the low order 32 bits. | |
7549 | Otherwise, set imm_expr to the entire 64 bit | |
7550 | constant. */ | |
7551 | if (mips_opts.isa < 3) | |
7552 | { | |
7553 | imm_expr.X_op = O_constant; | |
7554 | offset_expr.X_op = O_constant; | |
7555 | if (! target_big_endian) | |
7556 | { | |
7557 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7558 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7559 | } | |
7560 | else | |
7561 | { | |
7562 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7563 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7564 | } | |
7565 | if (offset_expr.X_add_number == 0) | |
7566 | offset_expr.X_op = O_absent; | |
7567 | } | |
7568 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7569 | { | |
7570 | imm_expr.X_op = O_constant; | |
7571 | if (! target_big_endian) | |
7572 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7573 | else | |
7574 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7575 | } | |
7576 | else | |
7577 | { | |
7578 | imm_expr.X_op = O_big; | |
7579 | imm_expr.X_add_number = 4; | |
7580 | if (! target_big_endian) | |
7581 | { | |
7582 | generic_bignum[0] = bfd_getl16 (temp); | |
7583 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7584 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7585 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7586 | } | |
7587 | else | |
7588 | { | |
7589 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7590 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7591 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7592 | generic_bignum[3] = bfd_getb16 (temp); | |
7593 | } | |
7594 | } | |
19ed8960 ILT |
7595 | } |
7596 | else | |
7597 | { | |
0dd2d296 ILT |
7598 | const char *newname; |
7599 | segT new_seg; | |
7600 | ||
19ed8960 ILT |
7601 | /* Switch to the right section. */ |
7602 | seg = now_seg; | |
7603 | subseg = now_subseg; | |
7604 | switch (*args) | |
7605 | { | |
0dd2d296 | 7606 | default: /* unused default case avoids warnings. */ |
19ed8960 | 7607 | case 'L': |
1113140a | 7608 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 7609 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 7610 | newname = ".lit8"; |
0dd2d296 ILT |
7611 | break; |
7612 | case 'F': | |
d2c71068 | 7613 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
7614 | break; |
7615 | case 'l': | |
1dc1e798 KR |
7616 | assert (!USE_GLOBAL_POINTER_OPT |
7617 | || g_switch_value >= 4); | |
0dd2d296 | 7618 | newname = ".lit4"; |
19ed8960 ILT |
7619 | break; |
7620 | } | |
0dd2d296 | 7621 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
7622 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
7623 | bfd_set_section_flags (stdoutput, new_seg, | |
7624 | (SEC_ALLOC | |
7625 | | SEC_LOAD | |
7626 | | SEC_READONLY | |
7627 | | SEC_DATA)); | |
e2e5acfa JW |
7628 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
7629 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7630 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
7631 | record_alignment (new_seg, 4); |
7632 | else | |
7633 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
7634 | if (seg == now_seg) |
7635 | as_bad ("Can't use floating point insn in this section"); | |
7636 | ||
7637 | /* Set the argument to the current address in the | |
6e8dda9c | 7638 | section. */ |
19ed8960 ILT |
7639 | offset_expr.X_op = O_symbol; |
7640 | offset_expr.X_add_symbol = | |
7641 | symbol_new ("L0\001", now_seg, | |
7642 | (valueT) frag_now_fix (), frag_now); | |
7643 | offset_expr.X_add_number = 0; | |
7644 | ||
7645 | /* Put the floating point number into the section. */ | |
604633ae | 7646 | p = frag_more ((int) length); |
19ed8960 ILT |
7647 | memcpy (p, temp, length); |
7648 | ||
7649 | /* Switch back to the original section. */ | |
7650 | subseg_set (seg, subseg); | |
7651 | } | |
7652 | } | |
670a50eb ILT |
7653 | continue; |
7654 | ||
7655 | case 'i': /* 16 bit unsigned immediate */ | |
7656 | case 'j': /* 16 bit signed immediate */ | |
7657 | imm_reloc = BFD_RELOC_LO16; | |
7658 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 7659 | if (c != '\0') |
670a50eb ILT |
7660 | { |
7661 | if (c != 'l') | |
7662 | { | |
5ac34ac3 | 7663 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
7664 | imm_expr.X_add_number = |
7665 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7666 | else if (c == 'h') | |
867a58b3 ILT |
7667 | { |
7668 | imm_reloc = BFD_RELOC_HI16_S; | |
7669 | imm_unmatched_hi = true; | |
7670 | } | |
670a50eb ILT |
7671 | else |
7672 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 7673 | } |
670a50eb | 7674 | } |
670a50eb ILT |
7675 | if (*args == 'i') |
7676 | { | |
344a8d61 | 7677 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7678 | || ((imm_expr.X_add_number < 0 |
7679 | || imm_expr.X_add_number >= 0x10000) | |
7680 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
7681 | { |
7682 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7683 | !strcmp (insn->name, insn[1].name)) | |
7684 | break; | |
9753202d ILT |
7685 | if (imm_expr.X_op != O_constant |
7686 | && imm_expr.X_op != O_big) | |
7687 | insn_error = "absolute expression required"; | |
7688 | else | |
7689 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 7690 | } |
670a50eb ILT |
7691 | } |
7692 | else | |
7693 | { | |
d9aba805 ILT |
7694 | int more; |
7695 | offsetT max; | |
7696 | ||
be22008b ILT |
7697 | /* The upper bound should be 0x8000, but |
7698 | unfortunately the MIPS assembler accepts numbers | |
7699 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
7700 | we want to be compatible. We only permit this |
7701 | extended range for an instruction which does not | |
7702 | provide any further alternates, since those | |
7703 | alternates may handle other cases. People should | |
7704 | use the numbers they mean, rather than relying on | |
7705 | a mysterious sign extension. */ | |
7706 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7707 | strcmp (insn->name, insn[1].name) == 0); | |
7708 | if (more) | |
7709 | max = 0x8000; | |
7710 | else | |
7711 | max = 0x10000; | |
344a8d61 | 7712 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7713 | || ((imm_expr.X_add_number < -0x8000 |
7714 | || imm_expr.X_add_number >= max) | |
7715 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
7716 | || (more |
7717 | && imm_expr.X_add_number < 0 | |
3c83da8a | 7718 | && mips_opts.isa >= 3 |
d8a1c247 KR |
7719 | && imm_expr.X_unsigned |
7720 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 7721 | { |
d9aba805 | 7722 | if (more) |
99c24539 | 7723 | break; |
9753202d ILT |
7724 | if (imm_expr.X_op != O_constant |
7725 | && imm_expr.X_op != O_big) | |
7726 | insn_error = "absolute expression required"; | |
7727 | else | |
7728 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 7729 | } |
3d3c5039 | 7730 | } |
670a50eb ILT |
7731 | s = expr_end; |
7732 | continue; | |
7733 | ||
7734 | case 'o': /* 16 bit offset */ | |
7735 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
7736 | |
7737 | /* If this value won't fit into a 16 bit offset, then go | |
7738 | find a macro that will generate the 32 bit offset | |
7739 | code pattern. As a special hack, we accept the | |
7740 | difference of two local symbols as a constant. This | |
7741 | is required to suppose embedded PIC switches, which | |
7742 | use an instruction which looks like | |
7743 | lw $4,$L12-$LS12($4) | |
7744 | The problem with handling this in a more general | |
7745 | fashion is that the macro function doesn't expect to | |
7746 | see anything which can be handled in a single | |
7747 | constant instruction. */ | |
6f0b87c3 SS |
7748 | if (c == 0 |
7749 | && (offset_expr.X_op != O_constant | |
7750 | || offset_expr.X_add_number >= 0x8000 | |
7751 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
7752 | && (mips_pic != EMBEDDED_PIC |
7753 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
7754 | || now_seg != text_section |
7755 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7756 | != text_section))) | |
670a50eb | 7757 | break; |
3d3c5039 | 7758 | |
670a50eb ILT |
7759 | offset_reloc = BFD_RELOC_LO16; |
7760 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
7761 | { |
7762 | assert (offset_expr.X_op == O_constant); | |
7763 | offset_expr.X_add_number = | |
7764 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7765 | } | |
cc5703cd ILT |
7766 | s = expr_end; |
7767 | continue; | |
7768 | ||
7769 | case 'p': /* pc relative offset */ | |
7770 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7771 | my_getExpression (&offset_expr, s); | |
7772 | s = expr_end; | |
7773 | continue; | |
7774 | ||
7775 | case 'u': /* upper 16 bits */ | |
7776 | c = my_getSmallExpression (&imm_expr, s); | |
7777 | if (imm_expr.X_op == O_constant | |
7778 | && (imm_expr.X_add_number < 0 | |
7779 | || imm_expr.X_add_number >= 0x10000)) | |
7780 | as_bad ("lui expression not in range 0..65535"); | |
7781 | imm_reloc = BFD_RELOC_LO16; | |
7782 | if (c) | |
7783 | { | |
7784 | if (c != 'l') | |
7785 | { | |
7786 | if (imm_expr.X_op == O_constant) | |
7787 | imm_expr.X_add_number = | |
7788 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7789 | else if (c == 'h') | |
7790 | { | |
7791 | imm_reloc = BFD_RELOC_HI16_S; | |
7792 | imm_unmatched_hi = true; | |
7793 | } | |
7794 | else | |
7795 | imm_reloc = BFD_RELOC_HI16; | |
7796 | } | |
7797 | } | |
7798 | s = expr_end; | |
7799 | continue; | |
7800 | ||
7801 | case 'a': /* 26 bit address */ | |
7802 | my_getExpression (&offset_expr, s); | |
7803 | s = expr_end; | |
7804 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7805 | continue; | |
7806 | ||
7807 | case 'N': /* 3 bit branch condition code */ | |
7808 | case 'M': /* 3 bit compare condition code */ | |
7809 | if (strncmp (s, "$fcc", 4) != 0) | |
7810 | break; | |
7811 | s += 4; | |
7812 | regno = 0; | |
7813 | do | |
7814 | { | |
7815 | regno *= 10; | |
7816 | regno += *s - '0'; | |
7817 | ++s; | |
7818 | } | |
7819 | while (isdigit (*s)); | |
7820 | if (regno > 7) | |
7821 | as_bad ("invalid condition code register $fcc%d", regno); | |
7822 | if (*args == 'N') | |
7823 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7824 | else | |
7825 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7826 | continue; | |
7827 | ||
b3ed1af3 KR |
7828 | /* start-sanitize-vr5400 */ |
7829 | case 'e': /* must be at least one digit */ | |
7830 | my_getExpression (&imm_expr, s); | |
7831 | check_absolute_expr (ip, &imm_expr); | |
7832 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECBYTE) | |
7833 | { | |
7834 | as_bad ("bad byte vector index (%ld)", | |
7835 | (long) imm_expr.X_add_number); | |
7836 | imm_expr.X_add_number = imm_expr.X_add_number; | |
7837 | } | |
7838 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
7839 | imm_expr.X_op = O_absent; | |
7840 | s = expr_end; | |
7841 | continue; | |
7842 | ||
7843 | case '%': | |
7844 | my_getExpression (&imm_expr, s); | |
7845 | check_absolute_expr (ip, &imm_expr); | |
7846 | if ((unsigned long) imm_expr.X_add_number > (unsigned long) OP_MASK_VECALIGN) | |
7847 | { | |
7848 | as_bad ("bad byte vector index (%ld)", | |
7849 | (long) imm_expr.X_add_number); | |
7850 | imm_expr.X_add_number = imm_expr.X_add_number; | |
7851 | } | |
7852 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
7853 | imm_expr.X_op = O_absent; | |
7854 | s = expr_end; | |
7855 | continue; | |
7856 | ||
7857 | /* end-sanitize-vr5400 */ | |
cc5703cd | 7858 | default: |
b3ed1af3 | 7859 | as_bad ("bad char = '%c'\n", *args); |
cc5703cd ILT |
7860 | internalError (); |
7861 | } | |
7862 | break; | |
7863 | } | |
7864 | /* Args don't match. */ | |
7865 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7866 | !strcmp (insn->name, insn[1].name)) | |
7867 | { | |
7868 | ++insn; | |
7869 | s = argsStart; | |
7870 | continue; | |
7871 | } | |
7872 | insn_error = "illegal operands"; | |
7873 | return; | |
7874 | } | |
7875 | } | |
7876 | ||
7877 | /* This routine assembles an instruction into its binary format when | |
7878 | assembling for the mips16. As a side effect, it sets one of the | |
7879 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
7880 | relocation to do if one of the operands is an address expression. |
7881 | It also sets mips16_small and mips16_ext if the user explicitly | |
7882 | requested a small or extended instruction. */ | |
cc5703cd ILT |
7883 | |
7884 | static void | |
7885 | mips16_ip (str, ip) | |
7886 | char *str; | |
7887 | struct mips_cl_insn *ip; | |
7888 | { | |
7889 | char *s; | |
cc5703cd ILT |
7890 | const char *args; |
7891 | struct mips_opcode *insn; | |
7892 | char *argsstart; | |
7893 | unsigned int regno; | |
7894 | unsigned int lastregno = 0; | |
7895 | char *s_reset; | |
7896 | ||
7897 | insn_error = NULL; | |
7898 | ||
8728fa92 ILT |
7899 | mips16_small = false; |
7900 | mips16_ext = false; | |
cc5703cd ILT |
7901 | |
7902 | for (s = str; islower (*s); ++s) | |
7903 | ; | |
7904 | switch (*s) | |
7905 | { | |
7906 | case '\0': | |
7907 | break; | |
7908 | ||
7909 | case ' ': | |
7910 | *s++ = '\0'; | |
7911 | break; | |
7912 | ||
7913 | case '.': | |
7914 | if (s[1] == 't' && s[2] == ' ') | |
7915 | { | |
7916 | *s = '\0'; | |
8728fa92 | 7917 | mips16_small = true; |
cc5703cd ILT |
7918 | s += 3; |
7919 | break; | |
7920 | } | |
7921 | else if (s[1] == 'e' && s[2] == ' ') | |
7922 | { | |
7923 | *s = '\0'; | |
8728fa92 | 7924 | mips16_ext = true; |
cc5703cd ILT |
7925 | s += 3; |
7926 | break; | |
7927 | } | |
7928 | /* Fall through. */ | |
7929 | default: | |
7930 | insn_error = "unknown opcode"; | |
7931 | return; | |
7932 | } | |
7933 | ||
3c83da8a | 7934 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
7935 | mips16_small = true; |
7936 | ||
cc5703cd ILT |
7937 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
7938 | { | |
7939 | insn_error = "unrecognized opcode"; | |
7940 | return; | |
7941 | } | |
7942 | ||
7943 | argsstart = s; | |
7944 | for (;;) | |
7945 | { | |
7946 | assert (strcmp (insn->name, str) == 0); | |
7947 | ||
7948 | ip->insn_mo = insn; | |
7949 | ip->insn_opcode = insn->match; | |
7950 | ip->use_extend = false; | |
7951 | imm_expr.X_op = O_absent; | |
7952 | imm_reloc = BFD_RELOC_UNUSED; | |
7953 | offset_expr.X_op = O_absent; | |
7954 | offset_reloc = BFD_RELOC_UNUSED; | |
7955 | for (args = insn->args; 1; ++args) | |
7956 | { | |
7957 | int c; | |
7958 | ||
7959 | if (*s == ' ') | |
7960 | ++s; | |
7961 | ||
7962 | /* In this switch statement we call break if we did not find | |
7963 | a match, continue if we did find a match, or return if we | |
7964 | are done. */ | |
7965 | ||
7966 | c = *args; | |
7967 | switch (c) | |
7968 | { | |
7969 | case '\0': | |
7970 | if (*s == '\0') | |
7971 | { | |
7972 | /* Stuff the immediate value in now, if we can. */ | |
7973 | if (imm_expr.X_op == O_constant | |
7974 | && imm_reloc > BFD_RELOC_UNUSED | |
7975 | && insn->pinfo != INSN_MACRO) | |
7976 | { | |
15e69f98 ILT |
7977 | mips16_immed ((char *) NULL, 0, |
7978 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
7979 | imm_expr.X_add_number, true, mips16_small, |
7980 | mips16_ext, &ip->insn_opcode, | |
7981 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7982 | imm_expr.X_op = O_absent; |
7983 | imm_reloc = BFD_RELOC_UNUSED; | |
7984 | } | |
7985 | ||
7986 | return; | |
7987 | } | |
7988 | break; | |
7989 | ||
7990 | case ',': | |
7991 | if (*s++ == c) | |
7992 | continue; | |
7993 | s--; | |
7994 | switch (*++args) | |
7995 | { | |
7996 | case 'v': | |
7997 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7998 | continue; | |
7999 | case 'w': | |
8000 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8001 | continue; | |
8002 | } | |
8003 | break; | |
8004 | ||
8005 | case '(': | |
8006 | case ')': | |
8007 | if (*s++ == c) | |
8008 | continue; | |
8009 | break; | |
8010 | ||
8011 | case 'v': | |
8012 | case 'w': | |
8013 | if (s[0] != '$') | |
8014 | { | |
8015 | if (c == 'v') | |
8016 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8017 | else | |
8018 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8019 | ++args; | |
8020 | continue; | |
8021 | } | |
8022 | /* Fall through. */ | |
8023 | case 'x': | |
8024 | case 'y': | |
8025 | case 'z': | |
8026 | case 'Z': | |
8027 | case '0': | |
8028 | case 'S': | |
8029 | case 'R': | |
8030 | case 'X': | |
8031 | case 'Y': | |
8032 | if (s[0] != '$') | |
8033 | break; | |
8034 | s_reset = s; | |
8035 | if (isdigit (s[1])) | |
8036 | { | |
8037 | ++s; | |
8038 | regno = 0; | |
8039 | do | |
8040 | { | |
8041 | regno *= 10; | |
8042 | regno += *s - '0'; | |
8043 | ++s; | |
8044 | } | |
8045 | while (isdigit (*s)); | |
8046 | if (regno > 31) | |
8047 | { | |
8048 | as_bad ("invalid register number (%d)", regno); | |
8049 | regno = 2; | |
8050 | } | |
8051 | } | |
8052 | else | |
8053 | { | |
8054 | if (s[1] == 'f' && s[2] == 'p') | |
8055 | { | |
8056 | s += 3; | |
8057 | regno = FP; | |
8058 | } | |
8059 | else if (s[1] == 's' && s[2] == 'p') | |
8060 | { | |
8061 | s += 3; | |
8062 | regno = SP; | |
8063 | } | |
8064 | else if (s[1] == 'g' && s[2] == 'p') | |
8065 | { | |
8066 | s += 3; | |
8067 | regno = GP; | |
8068 | } | |
8069 | else if (s[1] == 'a' && s[2] == 't') | |
8070 | { | |
8071 | s += 3; | |
8072 | regno = AT; | |
8073 | } | |
8074 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8075 | { | |
8076 | s += 4; | |
8077 | regno = KT0; | |
8078 | } | |
8079 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8080 | { | |
8081 | s += 4; | |
8082 | regno = KT1; | |
8083 | } | |
8084 | else | |
8085 | break; | |
8086 | } | |
8087 | ||
8088 | if (*s == ' ') | |
8089 | ++s; | |
8090 | if (args[1] != *s) | |
8091 | { | |
8092 | if (c == 'v' || c == 'w') | |
8093 | { | |
8094 | regno = mips16_to_32_reg_map[lastregno]; | |
8095 | s = s_reset; | |
8096 | args++; | |
8097 | } | |
8098 | } | |
8099 | ||
8100 | switch (c) | |
8101 | { | |
8102 | case 'x': | |
8103 | case 'y': | |
8104 | case 'z': | |
8105 | case 'v': | |
8106 | case 'w': | |
8107 | case 'Z': | |
8108 | regno = mips32_to_16_reg_map[regno]; | |
8109 | break; | |
8110 | ||
8111 | case '0': | |
8112 | if (regno != 0) | |
8113 | regno = ILLEGAL_REG; | |
8114 | break; | |
8115 | ||
8116 | case 'S': | |
8117 | if (regno != SP) | |
8118 | regno = ILLEGAL_REG; | |
8119 | break; | |
8120 | ||
8121 | case 'R': | |
8122 | if (regno != RA) | |
8123 | regno = ILLEGAL_REG; | |
8124 | break; | |
8125 | ||
8126 | case 'X': | |
8127 | case 'Y': | |
3c83da8a | 8128 | if (regno == AT && ! mips_opts.noat) |
cc5703cd ILT |
8129 | as_warn ("used $at without \".set noat\""); |
8130 | break; | |
8131 | ||
8132 | default: | |
8133 | internalError (); | |
8134 | } | |
8135 | ||
8136 | if (regno == ILLEGAL_REG) | |
8137 | break; | |
8138 | ||
8139 | switch (c) | |
8140 | { | |
8141 | case 'x': | |
8142 | case 'v': | |
8143 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8144 | break; | |
8145 | case 'y': | |
8146 | case 'w': | |
8147 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8148 | break; | |
8149 | case 'z': | |
8150 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8151 | break; | |
8152 | case 'Z': | |
8153 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8154 | case '0': | |
8155 | case 'S': | |
8156 | case 'R': | |
8157 | break; | |
8158 | case 'X': | |
8159 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8160 | break; | |
8161 | case 'Y': | |
8162 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8163 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8164 | break; | |
8165 | default: | |
8166 | internalError (); | |
8167 | } | |
8168 | ||
8169 | lastregno = regno; | |
8170 | continue; | |
8171 | ||
8172 | case 'P': | |
8173 | if (strncmp (s, "$pc", 3) == 0) | |
8174 | { | |
8175 | s += 3; | |
8176 | continue; | |
8177 | } | |
8178 | break; | |
8179 | ||
8180 | case '<': | |
8181 | case '>': | |
8182 | case '[': | |
8183 | case ']': | |
8184 | case '4': | |
8185 | case '5': | |
8186 | case 'H': | |
8187 | case 'W': | |
8188 | case 'D': | |
8189 | case 'j': | |
8190 | case '8': | |
8191 | case 'V': | |
8192 | case 'C': | |
8193 | case 'U': | |
8194 | case 'k': | |
8195 | case 'K': | |
16262668 ILT |
8196 | if (s[0] == '%' |
8197 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8198 | { | |
8199 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8200 | and generate the appropriate reloc. If the text | |
8201 | inside %gprel is not a symbol name with an | |
8202 | optional offset, then we generate a normal reloc | |
8203 | and will probably fail later. */ | |
8204 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8205 | if (imm_expr.X_op == O_symbol) | |
8206 | { | |
8207 | mips16_ext = true; | |
8208 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8209 | s = expr_end; | |
8210 | ip->use_extend = true; | |
8211 | ip->extend = 0; | |
8212 | continue; | |
8213 | } | |
8214 | } | |
8215 | else | |
8216 | { | |
8217 | /* Just pick up a normal expression. */ | |
8218 | my_getExpression (&imm_expr, s); | |
8219 | } | |
8220 | ||
ebf28372 ILT |
8221 | if (imm_expr.X_op == O_register) |
8222 | { | |
8223 | /* What we thought was an expression turned out to | |
8224 | be a register. */ | |
8225 | ||
8226 | if (s[0] == '(' && args[1] == '(') | |
8227 | { | |
8228 | /* It looks like the expression was omitted | |
8229 | before a register indirection, which means | |
8230 | that the expression is implicitly zero. We | |
8231 | still set up imm_expr, so that we handle | |
8232 | explicit extensions correctly. */ | |
8233 | imm_expr.X_op = O_constant; | |
8234 | imm_expr.X_add_number = 0; | |
8235 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8236 | continue; | |
8237 | } | |
8238 | ||
8239 | break; | |
8240 | } | |
8241 | ||
cc5703cd ILT |
8242 | /* We need to relax this instruction. */ |
8243 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8244 | s = expr_end; | |
8245 | continue; | |
8246 | ||
8247 | case 'p': | |
8248 | case 'q': | |
8249 | case 'A': | |
8250 | case 'B': | |
8251 | case 'E': | |
8252 | /* We use offset_reloc rather than imm_reloc for the PC | |
8253 | relative operands. This lets macros with both | |
8254 | immediate and address operands work correctly. */ | |
670a50eb | 8255 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
8256 | |
8257 | if (offset_expr.X_op == O_register) | |
8258 | break; | |
8259 | ||
cc5703cd ILT |
8260 | /* We need to relax this instruction. */ |
8261 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
8262 | s = expr_end; |
8263 | continue; | |
8264 | ||
cc5703cd ILT |
8265 | case '6': /* break code */ |
8266 | my_getExpression (&imm_expr, s); | |
8267 | check_absolute_expr (ip, &imm_expr); | |
8268 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 8269 | { |
cc5703cd ILT |
8270 | as_warn ("Invalid value for `%s' (%lu)", |
8271 | ip->insn_mo->name, | |
8272 | (unsigned long) imm_expr.X_add_number); | |
8273 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 8274 | } |
cc5703cd ILT |
8275 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
8276 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
8277 | s = expr_end; |
8278 | continue; | |
3d3c5039 | 8279 | |
670a50eb ILT |
8280 | case 'a': /* 26 bit address */ |
8281 | my_getExpression (&offset_expr, s); | |
8282 | s = expr_end; | |
cc5703cd ILT |
8283 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
8284 | ip->insn_opcode <<= 16; | |
670a50eb | 8285 | continue; |
3d3c5039 | 8286 | |
cc5703cd ILT |
8287 | case 'l': /* register list for entry macro */ |
8288 | case 'L': /* register list for exit macro */ | |
8289 | { | |
8290 | int mask; | |
8291 | ||
8292 | if (c == 'l') | |
8293 | mask = 0; | |
8294 | else | |
8295 | mask = 7 << 3; | |
8296 | while (*s != '\0') | |
8297 | { | |
c9167640 | 8298 | int freg, reg1, reg2; |
cc5703cd ILT |
8299 | |
8300 | while (*s == ' ' || *s == ',') | |
8301 | ++s; | |
8302 | if (*s != '$') | |
8303 | { | |
8304 | as_bad ("can't parse register list"); | |
8305 | break; | |
8306 | } | |
8307 | ++s; | |
c9167640 ILT |
8308 | if (*s != 'f') |
8309 | freg = 0; | |
8310 | else | |
8311 | { | |
8312 | freg = 1; | |
8313 | ++s; | |
8314 | } | |
cc5703cd ILT |
8315 | reg1 = 0; |
8316 | while (isdigit (*s)) | |
8317 | { | |
8318 | reg1 *= 10; | |
8319 | reg1 += *s - '0'; | |
8320 | ++s; | |
8321 | } | |
8322 | if (*s == ' ') | |
8323 | ++s; | |
8324 | if (*s != '-') | |
8325 | reg2 = reg1; | |
8326 | else | |
8327 | { | |
8328 | ++s; | |
8329 | if (*s != '$') | |
8330 | break; | |
8331 | ++s; | |
c9167640 ILT |
8332 | if (freg) |
8333 | { | |
8334 | if (*s == 'f') | |
8335 | ++s; | |
8336 | else | |
8337 | { | |
8338 | as_bad ("invalid register list"); | |
8339 | break; | |
8340 | } | |
8341 | } | |
cc5703cd ILT |
8342 | reg2 = 0; |
8343 | while (isdigit (*s)) | |
8344 | { | |
8345 | reg2 *= 10; | |
8346 | reg2 += *s - '0'; | |
8347 | ++s; | |
8348 | } | |
8349 | } | |
c9167640 ILT |
8350 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
8351 | { | |
8352 | mask &= ~ (7 << 3); | |
8353 | mask |= 5 << 3; | |
8354 | } | |
8355 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8356 | { | |
8357 | mask &= ~ (7 << 3); | |
8358 | mask |= 6 << 3; | |
8359 | } | |
8360 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
8361 | mask |= (reg2 - 3) << 3; |
8362 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8363 | mask |= (reg2 - 15) << 1; | |
8364 | else if (reg1 == 31 && reg2 == 31) | |
8365 | mask |= 1; | |
8366 | else | |
c9167640 ILT |
8367 | { |
8368 | as_bad ("invalid register list"); | |
8369 | break; | |
8370 | } | |
cc5703cd | 8371 | } |
c9167640 ILT |
8372 | /* The mask is filled in in the opcode table for the |
8373 | benefit of the disassembler. We remove it before | |
8374 | applying the actual mask. */ | |
8375 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
8376 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
8377 | } | |
8378 | continue; | |
d8a1c247 | 8379 | |
56bb6eee ILT |
8380 | case 'e': /* extend code */ |
8381 | my_getExpression (&imm_expr, s); | |
8382 | check_absolute_expr (ip, &imm_expr); | |
8383 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8384 | { | |
8385 | as_warn ("Invalid value for `%s' (%lu)", | |
8386 | ip->insn_mo->name, | |
8387 | (unsigned long) imm_expr.X_add_number); | |
8388 | imm_expr.X_add_number &= 0x7ff; | |
8389 | } | |
8390 | ip->insn_opcode |= imm_expr.X_add_number; | |
8391 | imm_expr.X_op = O_absent; | |
8392 | s = expr_end; | |
8393 | continue; | |
8394 | ||
3d3c5039 | 8395 | default: |
670a50eb | 8396 | internalError (); |
3d3c5039 | 8397 | } |
670a50eb | 8398 | break; |
3d3c5039 | 8399 | } |
cc5703cd | 8400 | |
670a50eb | 8401 | /* Args don't match. */ |
cc5703cd ILT |
8402 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
8403 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
8404 | { |
8405 | ++insn; | |
cc5703cd | 8406 | s = argsstart; |
670a50eb | 8407 | continue; |
3d3c5039 | 8408 | } |
cc5703cd | 8409 | |
9753202d | 8410 | insn_error = "illegal operands"; |
cc5703cd | 8411 | |
670a50eb | 8412 | return; |
3d3c5039 ILT |
8413 | } |
8414 | } | |
8415 | ||
cc5703cd ILT |
8416 | /* This structure holds information we know about a mips16 immediate |
8417 | argument type. */ | |
8418 | ||
8419 | struct mips16_immed_operand | |
8420 | { | |
8421 | /* The type code used in the argument string in the opcode table. */ | |
8422 | int type; | |
8423 | /* The number of bits in the short form of the opcode. */ | |
8424 | int nbits; | |
8425 | /* The number of bits in the extended form of the opcode. */ | |
8426 | int extbits; | |
8427 | /* The amount by which the short form is shifted when it is used; | |
8428 | for example, the sw instruction has a shift count of 2. */ | |
8429 | int shift; | |
8430 | /* The amount by which the short form is shifted when it is stored | |
8431 | into the instruction code. */ | |
8432 | int op_shift; | |
8433 | /* Non-zero if the short form is unsigned. */ | |
8434 | int unsp; | |
8435 | /* Non-zero if the extended form is unsigned. */ | |
8436 | int extu; | |
8437 | /* Non-zero if the value is PC relative. */ | |
8438 | int pcrel; | |
8439 | }; | |
8440 | ||
8441 | /* The mips16 immediate operand types. */ | |
8442 | ||
8443 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8444 | { | |
8445 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8446 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8447 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8448 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8449 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8450 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8451 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8452 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8453 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8454 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8455 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8456 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8457 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8458 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8459 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8460 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8461 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8462 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8463 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8464 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8465 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8466 | }; | |
8467 | ||
8468 | #define MIPS16_NUM_IMMED \ | |
8469 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8470 | ||
8471 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8472 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8473 | whether an extended value is needed; if one is needed, it sets | |
8474 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8475 | If SMALL is true, an unextended opcode was explicitly requested. | |
8476 | If EXT is true, an extended opcode was explicitly requested. If | |
8477 | WARN is true, warn if EXT does not match reality. */ | |
8478 | ||
8479 | static void | |
15e69f98 ILT |
8480 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
8481 | extend) | |
8482 | char *file; | |
8483 | unsigned int line; | |
cc5703cd ILT |
8484 | int type; |
8485 | offsetT val; | |
8486 | boolean warn; | |
8487 | boolean small; | |
8488 | boolean ext; | |
8489 | unsigned long *insn; | |
8490 | boolean *use_extend; | |
8491 | unsigned short *extend; | |
8492 | { | |
8493 | register const struct mips16_immed_operand *op; | |
8494 | int mintiny, maxtiny; | |
8495 | boolean needext; | |
8496 | ||
8497 | op = mips16_immed_operands; | |
8498 | while (op->type != type) | |
8499 | { | |
8500 | ++op; | |
8501 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8502 | } | |
8503 | ||
8504 | if (op->unsp) | |
8505 | { | |
8506 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8507 | { | |
8508 | mintiny = 1; | |
8509 | maxtiny = 1 << op->nbits; | |
8510 | } | |
8511 | else | |
8512 | { | |
8513 | mintiny = 0; | |
8514 | maxtiny = (1 << op->nbits) - 1; | |
8515 | } | |
8516 | } | |
8517 | else | |
8518 | { | |
8519 | mintiny = - (1 << (op->nbits - 1)); | |
8520 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8521 | } | |
8522 | ||
8523 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8524 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 8525 | val /= 2; |
cc5703cd ILT |
8526 | |
8527 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8528 | || val < (mintiny << op->shift) | |
8529 | || val > (maxtiny << op->shift)) | |
8530 | needext = true; | |
8531 | else | |
8532 | needext = false; | |
8533 | ||
8534 | if (warn && ext && ! needext) | |
15e69f98 | 8535 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 8536 | if (small && needext) |
15e69f98 | 8537 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
8538 | |
8539 | if (small || (! ext && ! needext)) | |
8540 | { | |
8541 | int insnval; | |
8542 | ||
8543 | *use_extend = false; | |
8544 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8545 | insnval <<= op->op_shift; | |
8546 | *insn |= insnval; | |
8547 | } | |
8548 | else | |
8549 | { | |
8550 | long minext, maxext; | |
8551 | int extval; | |
8552 | ||
8553 | if (op->extu) | |
8554 | { | |
8555 | minext = 0; | |
8556 | maxext = (1 << op->extbits) - 1; | |
8557 | } | |
8558 | else | |
8559 | { | |
8560 | minext = - (1 << (op->extbits - 1)); | |
8561 | maxext = (1 << (op->extbits - 1)) - 1; | |
8562 | } | |
8563 | if (val < minext || val > maxext) | |
15e69f98 ILT |
8564 | as_bad_where (file, line, |
8565 | "operand value out of range for instruction"); | |
cc5703cd ILT |
8566 | |
8567 | *use_extend = true; | |
8568 | if (op->extbits == 16) | |
8569 | { | |
8570 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8571 | val &= 0x1f; | |
8572 | } | |
8573 | else if (op->extbits == 15) | |
8574 | { | |
8575 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8576 | val &= 0xf; | |
8577 | } | |
8578 | else | |
8579 | { | |
8580 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8581 | val = 0; | |
8582 | } | |
8583 | ||
8584 | *extend = (unsigned short) extval; | |
8585 | *insn |= val; | |
8586 | } | |
8587 | } | |
8588 | \f | |
3d3c5039 ILT |
8589 | #define LP '(' |
8590 | #define RP ')' | |
8591 | ||
8592 | static int | |
8593 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
8594 | expressionS *ep; |
8595 | char *str; | |
3d3c5039 | 8596 | { |
670a50eb ILT |
8597 | char *sp; |
8598 | int c = 0; | |
8599 | ||
8600 | if (*str == ' ') | |
8601 | str++; | |
8602 | if (*str == LP | |
8603 | || (*str == '%' && | |
8604 | ((str[1] == 'h' && str[2] == 'i') | |
8605 | || (str[1] == 'H' && str[2] == 'I') | |
8606 | || (str[1] == 'l' && str[2] == 'o')) | |
8607 | && str[3] == LP)) | |
8608 | { | |
8609 | if (*str == LP) | |
8610 | c = 0; | |
8611 | else | |
8612 | { | |
8613 | c = str[1]; | |
8614 | str += 3; | |
8615 | } | |
8616 | ||
8617 | /* | |
8618 | * A small expression may be followed by a base register. | |
8619 | * Scan to the end of this operand, and then back over a possible | |
8620 | * base register. Then scan the small expression up to that | |
8621 | * point. (Based on code in sparc.c...) | |
8622 | */ | |
8623 | for (sp = str; *sp && *sp != ','; sp++) | |
8624 | ; | |
8625 | if (sp - 4 >= str && sp[-1] == RP) | |
8626 | { | |
8627 | if (isdigit (sp[-2])) | |
8628 | { | |
8629 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
8630 | ; | |
8631 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8632 | { | |
8633 | sp--; | |
8634 | goto do_it; | |
3d3c5039 | 8635 | } |
670a50eb ILT |
8636 | } |
8637 | else if (sp - 5 >= str | |
8638 | && sp[-5] == LP | |
8639 | && sp[-4] == '$' | |
8640 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8641 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8642 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8643 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8644 | { | |
8645 | sp -= 5; | |
3d3c5039 | 8646 | do_it: |
670a50eb ILT |
8647 | if (sp == str) |
8648 | { | |
8649 | /* no expression means zero offset */ | |
8650 | if (c) | |
8651 | { | |
8652 | /* %xx(reg) is an error */ | |
5ac34ac3 | 8653 | ep->X_op = O_absent; |
670a50eb | 8654 | expr_end = str - 3; |
3d3c5039 | 8655 | } |
670a50eb ILT |
8656 | else |
8657 | { | |
52aa70b5 | 8658 | ep->X_op = O_constant; |
670a50eb ILT |
8659 | expr_end = sp; |
8660 | } | |
8661 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 8662 | ep->X_op_symbol = NULL; |
670a50eb ILT |
8663 | ep->X_add_number = 0; |
8664 | } | |
8665 | else | |
8666 | { | |
8667 | *sp = '\0'; | |
8668 | my_getExpression (ep, str); | |
8669 | *sp = LP; | |
3d3c5039 | 8670 | } |
670a50eb | 8671 | return c; |
3d3c5039 ILT |
8672 | } |
8673 | } | |
8674 | } | |
670a50eb ILT |
8675 | my_getExpression (ep, str); |
8676 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
8677 | } |
8678 | ||
8679 | static void | |
8680 | my_getExpression (ep, str) | |
670a50eb ILT |
8681 | expressionS *ep; |
8682 | char *str; | |
3d3c5039 | 8683 | { |
670a50eb | 8684 | char *save_in; |
670a50eb ILT |
8685 | |
8686 | save_in = input_line_pointer; | |
8687 | input_line_pointer = str; | |
5ac34ac3 | 8688 | expression (ep); |
670a50eb ILT |
8689 | expr_end = input_line_pointer; |
8690 | input_line_pointer = save_in; | |
eb17f56c ILT |
8691 | |
8692 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8693 | then we bump the value of the symbol by 1 since that is how other | |
8694 | text symbols are handled. We don't bother to handle complex | |
8695 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 8696 | if (mips_opts.mips16 |
eb17f56c ILT |
8697 | && ep->X_op == O_symbol |
8698 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8699 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
8700 | && ep->X_add_symbol->sy_frag == frag_now | |
8701 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
8702 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
8703 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
8704 | } |
8705 | ||
becfe05e ILT |
8706 | /* Turn a string in input_line_pointer into a floating point constant |
8707 | of type type, and store the appropriate bytes in *litP. The number | |
8708 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
8709 | returned, or NULL on OK. */ | |
8710 | ||
3d3c5039 | 8711 | char * |
670a50eb | 8712 | md_atof (type, litP, sizeP) |
becfe05e | 8713 | int type; |
3d3c5039 ILT |
8714 | char *litP; |
8715 | int *sizeP; | |
8716 | { | |
becfe05e ILT |
8717 | int prec; |
8718 | LITTLENUM_TYPE words[4]; | |
8719 | char *t; | |
8720 | int i; | |
8721 | ||
8722 | switch (type) | |
8723 | { | |
8724 | case 'f': | |
8725 | prec = 2; | |
8726 | break; | |
8727 | ||
8728 | case 'd': | |
8729 | prec = 4; | |
8730 | break; | |
8731 | ||
8732 | default: | |
8733 | *sizeP = 0; | |
8734 | return "bad call to md_atof"; | |
8735 | } | |
8736 | ||
8737 | t = atof_ieee (input_line_pointer, type, words); | |
8738 | if (t) | |
8739 | input_line_pointer = t; | |
8740 | ||
8741 | *sizeP = prec * 2; | |
8742 | ||
b9129c6f | 8743 | if (! target_big_endian) |
becfe05e ILT |
8744 | { |
8745 | for (i = prec - 1; i >= 0; i--) | |
8746 | { | |
8747 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8748 | litP += 2; | |
8749 | } | |
8750 | } | |
8751 | else | |
8752 | { | |
8753 | for (i = 0; i < prec; i++) | |
8754 | { | |
8755 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8756 | litP += 2; | |
8757 | } | |
8758 | } | |
8759 | ||
670a50eb | 8760 | return NULL; |
3d3c5039 ILT |
8761 | } |
8762 | ||
8763 | void | |
8764 | md_number_to_chars (buf, val, n) | |
8765 | char *buf; | |
918692a5 | 8766 | valueT val; |
3d3c5039 ILT |
8767 | int n; |
8768 | { | |
b9129c6f ILT |
8769 | if (target_big_endian) |
8770 | number_to_chars_bigendian (buf, val, n); | |
8771 | else | |
8772 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 8773 | } |
f3d817d8 | 8774 | \f |
e8d4d475 | 8775 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 8776 | |
f3d817d8 DM |
8777 | struct option md_longopts[] = { |
8778 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8779 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8780 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8781 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8782 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8783 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8784 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
8785 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
8786 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8787 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 8788 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 8789 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 8790 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 8791 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
8792 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8793 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 8794 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
8795 | {"break", no_argument, NULL, OPTION_BREAK}, |
8796 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 8797 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 8798 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 8799 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 8800 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 8801 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 8802 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 8803 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 8804 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
8805 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
8806 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8807 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8808 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
8809 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
8810 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8811 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8812 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 8813 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 8814 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 8815 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 8816 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 8817 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
8818 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
8819 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
8820 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
8821 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 8822 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
8823 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
8824 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
8825 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
8826 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
4e96260f JL |
8827 | |
8828 | /* start-sanitize-tx19 */ | |
8829 | {"m1900", no_argument, NULL, OPTION_M3900}, | |
8830 | {"no-m1900", no_argument, NULL, OPTION_NO_M3900}, | |
8831 | /* end-sanitize-tx19 */ | |
f3d817d8 | 8832 | |
aa2e0460 KR |
8833 | /* start-sanitize-vr5400 */ |
8834 | #define OPTION_M5400 (OPTION_MD_BASE + 28) | |
8835 | {"m5400", no_argument, NULL, OPTION_M5400}, | |
8836 | #define OPTION_NO_M5400 (OPTION_MD_BASE + 29) | |
8837 | {"no-m5400", no_argument, NULL, OPTION_NO_M5400}, | |
8838 | ||
8839 | /* end-sanitize-vr5400 */ | |
42444087 GRK |
8840 | /* start-sanitize-tx49 */ |
8841 | #define OPTION_M4900 (OPTION_MD_BASE + 30) | |
8842 | {"m4900", no_argument, NULL, OPTION_M4900}, | |
8843 | #define OPTION_NO_M4900 (OPTION_MD_BASE + 31) | |
8844 | {"no-m4900", no_argument, NULL, OPTION_NO_M4900}, | |
8845 | ||
8846 | /* end-sanitize-tx49 */ | |
2d035a50 GRK |
8847 | /* start-sanitize-vr4320 */ |
8848 | #define OPTION_M4320 (OPTION_MD_BASE + 32) | |
8849 | {"m4320", no_argument, NULL, OPTION_M4320}, | |
8850 | #define OPTION_NO_M4320 (OPTION_MD_BASE + 33) | |
8851 | {"no-m4320", no_argument, NULL, OPTION_NO_M4320}, | |
8852 | ||
8853 | /* end-sanitize-vr4320 */ | |
d8a1c247 | 8854 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 8855 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 8856 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
8857 | #define OPTION_32 (OPTION_MD_BASE + 20) |
8858 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 8859 | #ifdef OBJ_ELF |
f3d817d8 | 8860 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 8861 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 8862 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 8863 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
8864 | {"32", no_argument, NULL, OPTION_32}, |
8865 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
8866 | #endif |
8867 | ||
8868 | {NULL, no_argument, NULL, 0} | |
8869 | }; | |
8870 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
8871 | |
8872 | int | |
f3d817d8 DM |
8873 | md_parse_option (c, arg) |
8874 | int c; | |
8875 | char *arg; | |
3d3c5039 | 8876 | { |
f3d817d8 | 8877 | switch (c) |
670a50eb | 8878 | { |
f3d817d8 DM |
8879 | case OPTION_TRAP: |
8880 | mips_trap = 1; | |
8881 | break; | |
670a50eb | 8882 | |
f3d817d8 DM |
8883 | case OPTION_BREAK: |
8884 | mips_trap = 0; | |
8885 | break; | |
8886 | ||
e8d4d475 | 8887 | case OPTION_EB: |
1dc1e798 | 8888 | target_big_endian = 1; |
e8d4d475 | 8889 | break; |
04cb3372 | 8890 | |
e8d4d475 | 8891 | case OPTION_EL: |
1dc1e798 | 8892 | target_big_endian = 0; |
f3d817d8 | 8893 | break; |
670a50eb | 8894 | |
f3d817d8 DM |
8895 | case 'O': |
8896 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
8897 | mips_optimize = 1; |
8898 | else | |
8899 | mips_optimize = 2; | |
f3d817d8 | 8900 | break; |
0aa07269 | 8901 | |
f3d817d8 | 8902 | case 'g': |
22ba90ce ILT |
8903 | if (arg == NULL) |
8904 | mips_debug = 2; | |
8905 | else | |
8906 | mips_debug = atoi (arg); | |
8907 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8908 | optimizations which limit full symbolic debugging. We take | |
8909 | that to be equivalent to -O0. */ | |
8910 | if (mips_debug == 2) | |
05874c2e | 8911 | mips_optimize = 1; |
f3d817d8 | 8912 | break; |
4e95866e | 8913 | |
f3d817d8 | 8914 | case OPTION_MIPS1: |
3c83da8a | 8915 | mips_opts.isa = 1; |
f3d817d8 | 8916 | break; |
8358c818 | 8917 | |
f3d817d8 | 8918 | case OPTION_MIPS2: |
3c83da8a | 8919 | mips_opts.isa = 2; |
f3d817d8 | 8920 | break; |
8358c818 | 8921 | |
f3d817d8 | 8922 | case OPTION_MIPS3: |
3c83da8a | 8923 | mips_opts.isa = 3; |
f3d817d8 | 8924 | break; |
8358c818 | 8925 | |
d8a1c247 | 8926 | case OPTION_MIPS4: |
3c83da8a | 8927 | mips_opts.isa = 4; |
d8a1c247 KR |
8928 | break; |
8929 | ||
f3d817d8 DM |
8930 | case OPTION_MCPU: |
8931 | { | |
8932 | char *p; | |
8933 | ||
8934 | /* Identify the processor type */ | |
8935 | p = arg; | |
8936 | if (strcmp (p, "default") == 0 | |
8937 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 8938 | mips_cpu = -1; |
f3d817d8 DM |
8939 | else |
8940 | { | |
c625fc23 JSC |
8941 | int sv = 0; |
8942 | ||
8943 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8944 | processor. */ | |
8945 | if (*p == 'v' || *p == 'V') | |
8946 | { | |
8947 | sv = 1; | |
8948 | p++; | |
8949 | } | |
8950 | ||
f3d817d8 DM |
8951 | if (*p == 'r' || *p == 'R') |
8952 | p++; | |
8358c818 | 8953 | |
4bb0cc41 | 8954 | mips_cpu = -1; |
f3d817d8 DM |
8955 | switch (*p) |
8956 | { | |
d8a1c247 KR |
8957 | case '1': |
8958 | if (strcmp (p, "10000") == 0 | |
8959 | || strcmp (p, "10k") == 0 | |
8960 | || strcmp (p, "10K") == 0) | |
8961 | mips_cpu = 10000; | |
4e96260f JL |
8962 | /* start-sanitize-tx19 */ |
8963 | else if (strcmp (p, "1900") == 0) | |
8964 | mips_cpu = 3900; | |
8965 | /* end-sanitize-tx19 */ | |
d8a1c247 KR |
8966 | break; |
8967 | ||
f3d817d8 DM |
8968 | case '2': |
8969 | if (strcmp (p, "2000") == 0 | |
8970 | || strcmp (p, "2k") == 0 | |
8971 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 8972 | mips_cpu = 2000; |
f3d817d8 | 8973 | break; |
8358c818 | 8974 | |
f3d817d8 DM |
8975 | case '3': |
8976 | if (strcmp (p, "3000") == 0 | |
8977 | || strcmp (p, "3k") == 0 | |
8978 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 8979 | mips_cpu = 3000; |
5c6f5923 GRK |
8980 | else if (strcmp (p, "3900") == 0) |
8981 | mips_cpu = 3900; | |
f3d817d8 | 8982 | break; |
8358c818 | 8983 | |
f3d817d8 DM |
8984 | case '4': |
8985 | if (strcmp (p, "4000") == 0 | |
8986 | || strcmp (p, "4k") == 0 | |
8c63448a | 8987 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 8988 | mips_cpu = 4000; |
c625fc23 | 8989 | else if (strcmp (p, "4100") == 0) |
c625fc23 | 8990 | mips_cpu = 4100; |
c625fc23 JSC |
8991 | else if (strcmp (p, "4300") == 0) |
8992 | mips_cpu = 4300; | |
2d035a50 GRK |
8993 | /* start-sanitize-vr4320 */ |
8994 | else if (strcmp (p, "4320") == 0) | |
8995 | mips_cpu = 4320; | |
8996 | /* end-sanitize-vr4320 */ | |
8c63448a | 8997 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 8998 | mips_cpu = 4400; |
8c63448a | 8999 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 9000 | mips_cpu = 4600; |
b2b8c24e | 9001 | else if (strcmp (p, "4650") == 0) |
b2b8c24e | 9002 | mips_cpu = 4650; |
4ebda395 GRK |
9003 | /* start-sanitize-tx49 */ |
9004 | else if (strcmp (p, "4900") == 0) | |
9005 | mips_cpu = 4900; | |
9006 | /* end-sanitize-tx49 */ | |
e532b44c | 9007 | else if (strcmp (p, "4010") == 0) |
1724c79e | 9008 | mips_cpu = 4010; |
f3d817d8 | 9009 | break; |
8358c818 | 9010 | |
517078c1 ILT |
9011 | case '5': |
9012 | if (strcmp (p, "5000") == 0 | |
9013 | || strcmp (p, "5k") == 0 | |
9014 | || strcmp (p, "5K") == 0) | |
9015 | mips_cpu = 5000; | |
aa2e0460 KR |
9016 | /* start-sanitize-vr5400 */ |
9017 | else if (strcmp (p, "5400") == 0) | |
9018 | mips_cpu = 5400; | |
9019 | /* end-sanitize-vr5400 */ | |
276c2d7d GRK |
9020 | /* start-sanitize-r5900 */ |
9021 | else if (strcmp (p, "5900") == 0) | |
9022 | mips_cpu = 5900; | |
9023 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
9024 | break; |
9025 | ||
f3d817d8 DM |
9026 | case '6': |
9027 | if (strcmp (p, "6000") == 0 | |
9028 | || strcmp (p, "6k") == 0 | |
9029 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 9030 | mips_cpu = 6000; |
f3d817d8 | 9031 | break; |
55933a58 | 9032 | |
d8a1c247 KR |
9033 | case '8': |
9034 | if (strcmp (p, "8000") == 0 | |
9035 | || strcmp (p, "8k") == 0 | |
9036 | || strcmp (p, "8K") == 0) | |
9037 | mips_cpu = 8000; | |
9038 | break; | |
9039 | ||
55933a58 ILT |
9040 | case 'o': |
9041 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 9042 | mips_cpu = 4600; |
55933a58 | 9043 | break; |
f3d817d8 | 9044 | } |
8358c818 | 9045 | |
b3ed1af3 KR |
9046 | if (sv |
9047 | && (mips_cpu != 4300 | |
9048 | && mips_cpu != 4100 | |
2d035a50 GRK |
9049 | /* start-sanitize-vr4320 */ |
9050 | && mips_cpu != 4320 | |
9051 | /* end-sanitize-vr4320 */ | |
b3ed1af3 KR |
9052 | /* start-sanitize-vr5400 */ |
9053 | && mips_cpu != 5400 | |
9054 | /* end-sanitize-vr5400 */ | |
9055 | && mips_cpu != 5000)) | |
c625fc23 JSC |
9056 | { |
9057 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
9058 | return 0; | |
9059 | } | |
9060 | ||
4bb0cc41 | 9061 | if (mips_cpu == -1) |
f3d817d8 DM |
9062 | { |
9063 | as_bad ("invalid architecture -mcpu=%s", arg); | |
9064 | return 0; | |
9065 | } | |
9066 | } | |
9067 | } | |
9068 | break; | |
8358c818 | 9069 | |
b2b8c24e ILT |
9070 | case OPTION_M4650: |
9071 | mips_4650 = 1; | |
9072 | break; | |
9073 | ||
9074 | case OPTION_NO_M4650: | |
9075 | mips_4650 = 0; | |
9076 | break; | |
9077 | ||
e532b44c ILT |
9078 | case OPTION_M4010: |
9079 | mips_4010 = 1; | |
9080 | break; | |
9081 | ||
9082 | case OPTION_NO_M4010: | |
9083 | mips_4010 = 0; | |
9084 | break; | |
9085 | ||
c625fc23 JSC |
9086 | case OPTION_M4100: |
9087 | mips_4100 = 1; | |
9088 | break; | |
9089 | ||
9090 | case OPTION_NO_M4100: | |
9091 | mips_4100 = 0; | |
9092 | break; | |
9093 | ||
276c2d7d GRK |
9094 | /* start-sanitize-r5900 */ |
9095 | case OPTION_M5900: | |
9096 | mips_5900 = 1; | |
9097 | break; | |
9098 | ||
9099 | case OPTION_NO_M5900: | |
9100 | mips_5900 = 0; | |
9101 | break; | |
9102 | /* end-sanitize-r5900 */ | |
9103 | ||
2d035a50 GRK |
9104 | /* start-sanitize-vr4320 */ |
9105 | case OPTION_M4320: | |
9106 | mips_4320 = 1; | |
9107 | break; | |
9108 | ||
9109 | case OPTION_NO_M4320: | |
9110 | mips_4320 = 0; | |
9111 | break; | |
9112 | ||
9113 | /* end-sanitize-vr4320 */ | |
aa2e0460 KR |
9114 | /* start-sanitize-vr5400 */ |
9115 | case OPTION_M5400: | |
9116 | mips_5400 = 1; | |
9117 | break; | |
9118 | ||
9119 | case OPTION_NO_M5400: | |
9120 | mips_5400 = 0; | |
9121 | break; | |
9122 | ||
9123 | /* end-sanitize-vr5400 */ | |
5c6f5923 GRK |
9124 | case OPTION_M3900: |
9125 | mips_3900 = 1; | |
9126 | break; | |
9127 | ||
9128 | case OPTION_NO_M3900: | |
9129 | mips_3900 = 0; | |
9130 | break; | |
9131 | ||
42444087 GRK |
9132 | /* start-sanitize-tx49 */ |
9133 | case OPTION_M4900: | |
9134 | mips_4900 = 1; | |
9135 | break; | |
9136 | ||
9137 | case OPTION_NO_M4900: | |
9138 | mips_4900 = 0; | |
9139 | break; | |
9140 | ||
9141 | /* end-sanitize-tx49 */ | |
cc5703cd | 9142 | case OPTION_MIPS16: |
3c83da8a | 9143 | mips_opts.mips16 = 1; |
4a1cb507 | 9144 | mips_no_prev_insn (false); |
cc5703cd ILT |
9145 | break; |
9146 | ||
9147 | case OPTION_NO_MIPS16: | |
3c83da8a | 9148 | mips_opts.mips16 = 0; |
4a1cb507 | 9149 | mips_no_prev_insn (false); |
cc5703cd ILT |
9150 | break; |
9151 | ||
f3d817d8 | 9152 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 9153 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 9154 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
9155 | { |
9156 | as_bad ("-G may not be used with embedded PIC code"); | |
9157 | return 0; | |
9158 | } | |
5b63f465 | 9159 | g_switch_value = 0x7fffffff; |
f3d817d8 | 9160 | break; |
d9aba805 | 9161 | |
fb251650 ILT |
9162 | /* When generating ELF code, we permit -KPIC and -call_shared to |
9163 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9164 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 9165 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
9166 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9167 | { | |
9168 | as_bad ("-call_shared is supported only for ELF format"); | |
9169 | return 0; | |
9170 | } | |
d9aba805 ILT |
9171 | mips_pic = SVR4_PIC; |
9172 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
9173 | { |
9174 | as_bad ("-G may not be used with SVR4 PIC code"); | |
9175 | return 0; | |
9176 | } | |
d9aba805 | 9177 | g_switch_value = 0; |
f3d817d8 DM |
9178 | break; |
9179 | ||
9180 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
9181 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
9182 | { | |
9183 | as_bad ("-non_shared is supported only for ELF format"); | |
9184 | return 0; | |
9185 | } | |
d9aba805 | 9186 | mips_pic = NO_PIC; |
f3d817d8 | 9187 | break; |
8358c818 | 9188 | |
fb251650 ILT |
9189 | /* The -xgot option tells the assembler to use 32 offsets when |
9190 | accessing the got in SVR4_PIC mode. It is for Irix | |
9191 | compatibility. */ | |
9192 | case OPTION_XGOT: | |
9193 | mips_big_got = 1; | |
9194 | break; | |
9195 | ||
f3d817d8 | 9196 | case 'G': |
1dc1e798 KR |
9197 | if (! USE_GLOBAL_POINTER_OPT) |
9198 | { | |
9199 | as_bad ("-G is not supported for this configuration"); | |
9200 | return 0; | |
9201 | } | |
9202 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 9203 | { |
f3d817d8 DM |
9204 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
9205 | return 0; | |
670a50eb ILT |
9206 | } |
9207 | else | |
f3d817d8 | 9208 | g_switch_value = atoi (arg); |
42562568 | 9209 | g_switch_seen = 1; |
f3d817d8 | 9210 | break; |
4e95866e | 9211 | |
7f9880e5 ILT |
9212 | /* The -32 and -64 options tell the assembler to output the 32 |
9213 | bit or the 64 bit MIPS ELF format. */ | |
9214 | case OPTION_32: | |
9215 | mips_64 = 0; | |
9216 | break; | |
9217 | ||
9218 | case OPTION_64: | |
9c44af60 ILT |
9219 | { |
9220 | const char **list, **l; | |
9221 | ||
9222 | list = bfd_target_list (); | |
9223 | for (l = list; *l != NULL; l++) | |
9224 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9225 | || strcmp (*l, "elf64-littlemips") == 0) | |
9226 | break; | |
9227 | if (*l == NULL) | |
9228 | as_fatal ("No compiled in support for 64 bit object file format"); | |
9229 | free (list); | |
9230 | mips_64 = 1; | |
9231 | } | |
7f9880e5 ILT |
9232 | break; |
9233 | ||
f3d817d8 DM |
9234 | default: |
9235 | return 0; | |
8ea7f4e8 ILT |
9236 | } |
9237 | ||
f3d817d8 | 9238 | return 1; |
8ea7f4e8 ILT |
9239 | } |
9240 | ||
f3d817d8 DM |
9241 | void |
9242 | md_show_usage (stream) | |
9243 | FILE *stream; | |
9244 | { | |
9245 | fprintf(stream, "\ | |
9246 | MIPS options:\n\ | |
9247 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
9248 | -EB generate big endian output\n\ |
9249 | -EL generate little endian output\n\ | |
9250 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9251 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
9252 | implicitly with the gp register [default 8]\n"); |
9253 | fprintf(stream, "\ | |
f3d817d8 DM |
9254 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
9255 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
9256 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 9257 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 9258 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 9259 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
9260 | -m4650 permit R4650 instructions\n\ |
9261 | -no-m4650 do not permit R4650 instructions\n\ | |
9262 | -m4010 permit R4010 instructions\n\ | |
9263 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
9264 | -m4100 permit VR4100 instructions\n\ |
9265 | -no-m4100 do not permit VR4100 instructions\n"); | |
9266 | fprintf(stream, "\ | |
cc5703cd ILT |
9267 | -mips16 generate mips16 instructions\n\ |
9268 | -no-mips16 do not generate mips16 instructions\n"); | |
9269 | fprintf(stream, "\ | |
f3d817d8 DM |
9270 | -O0 remove unneeded NOPs, do not swap branches\n\ |
9271 | -O remove unneeded NOPs and swap branches\n\ | |
9272 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
9273 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
9274 | #ifdef OBJ_ELF | |
9275 | fprintf(stream, "\ | |
9276 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 9277 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
9278 | -xgot assume a 32 bit GOT\n\ |
9279 | -32 create 32 bit object file (default)\n\ | |
9280 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
9281 | #endif |
9282 | } | |
9283 | \f | |
efec4a28 DP |
9284 | void |
9285 | mips_init_after_args () | |
9286 | { | |
af942793 SS |
9287 | /* initialize opcodes */ |
9288 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
9289 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
9290 | } |
9291 | ||
3d3c5039 ILT |
9292 | long |
9293 | md_pcrel_from (fixP) | |
9294 | fixS *fixP; | |
9295 | { | |
1dc1e798 KR |
9296 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
9297 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
9298 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
9299 | { | |
9300 | /* This makes a branch to an undefined symbol be a branch to the | |
9301 | current location. */ | |
9302 | return 4; | |
9303 | } | |
5b63f465 | 9304 | |
670a50eb ILT |
9305 | /* return the address of the delay slot */ |
9306 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
9307 | } |
9308 | ||
abdad6bc ILT |
9309 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
9310 | reloc for a cons. We could use the definition there, except that | |
9311 | we want to handle 64 bit relocs specially. */ | |
9312 | ||
9313 | void | |
9314 | cons_fix_new_mips (frag, where, nbytes, exp) | |
9315 | fragS *frag; | |
9316 | int where; | |
9317 | unsigned int nbytes; | |
9318 | expressionS *exp; | |
9319 | { | |
bf39474f | 9320 | #ifndef OBJ_ELF |
abdad6bc | 9321 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
9322 | 4 byte reloc. */ |
9323 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 9324 | { |
b9129c6f | 9325 | if (target_big_endian) |
abdad6bc ILT |
9326 | where += 4; |
9327 | nbytes = 4; | |
9328 | } | |
bf39474f | 9329 | #endif |
abdad6bc | 9330 | |
7f9880e5 | 9331 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
9332 | as_bad ("Unsupported reloc size %d", nbytes); |
9333 | ||
9334 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
9335 | (nbytes == 2 |
9336 | ? BFD_RELOC_16 | |
9337 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
9338 | } |
9339 | ||
23604921 ILT |
9340 | /* This is called before the symbol table is processed. In order to |
9341 | work with gcc when using mips-tfile, we must keep all local labels. | |
9342 | However, in other cases, we want to discard them. If we were | |
9343 | called with -g, but we didn't see any debugging information, it may | |
9344 | mean that gcc is smuggling debugging information through to | |
9345 | mips-tfile, in which case we must generate all local labels. */ | |
9346 | ||
9347 | void | |
9348 | mips_frob_file_before_adjust () | |
9349 | { | |
9350 | #ifndef NO_ECOFF_DEBUGGING | |
9351 | if (ECOFF_DEBUGGING | |
9352 | && mips_debug != 0 | |
9353 | && ! ecoff_debugging_seen) | |
9354 | flag_keep_locals = 1; | |
9355 | #endif | |
9356 | } | |
9357 | ||
867a58b3 ILT |
9358 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
9359 | the corresponding LO reloc. This is called before md_apply_fix and | |
9360 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9361 | explicit use of the %hi modifier. */ | |
9362 | ||
9363 | void | |
9364 | mips_frob_file () | |
9365 | { | |
9366 | struct mips_hi_fixup *l; | |
9367 | ||
9368 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9369 | { | |
9370 | segment_info_type *seginfo; | |
9b61d62b | 9371 | int pass; |
867a58b3 ILT |
9372 | |
9373 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9374 | ||
9375 | /* Check quickly whether the next fixup happens to be a matching | |
9376 | %lo. */ | |
9377 | if (l->fixp->fx_next != NULL | |
9378 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9379 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9380 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9381 | continue; | |
9382 | ||
9383 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
9384 | When we find one, move the %hi just in front of it. We do |
9385 | this in two passes. In the first pass, we try to find a | |
9386 | unique %lo. In the second pass, we permit multiple %hi | |
9387 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 9388 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
9389 | for (pass = 0; pass < 2; pass++) |
9390 | { | |
9391 | fixS *f, *prev; | |
9392 | ||
9393 | prev = NULL; | |
9394 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 9395 | { |
9b61d62b ILT |
9396 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
9397 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9398 | && f->fx_addsy == l->fixp->fx_addsy | |
9399 | && f->fx_offset == l->fixp->fx_offset | |
9400 | && (pass == 1 | |
9401 | || prev == NULL | |
9402 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9403 | || prev->fx_addsy != f->fx_addsy | |
9404 | || prev->fx_offset != f->fx_offset)) | |
9405 | { | |
9406 | fixS **pf; | |
867a58b3 | 9407 | |
9b61d62b ILT |
9408 | /* Move l->fixp before f. */ |
9409 | for (pf = &seginfo->fix_root; | |
9410 | *pf != l->fixp; | |
9411 | pf = &(*pf)->fx_next) | |
9412 | assert (*pf != NULL); | |
867a58b3 | 9413 | |
9b61d62b | 9414 | *pf = l->fixp->fx_next; |
867a58b3 | 9415 | |
9b61d62b ILT |
9416 | l->fixp->fx_next = f; |
9417 | if (prev == NULL) | |
9418 | seginfo->fix_root = l->fixp; | |
9419 | else | |
9420 | prev->fx_next = l->fixp; | |
867a58b3 | 9421 | |
9b61d62b ILT |
9422 | break; |
9423 | } | |
9424 | ||
9425 | prev = f; | |
867a58b3 ILT |
9426 | } |
9427 | ||
9b61d62b ILT |
9428 | if (f != NULL) |
9429 | break; | |
867a58b3 | 9430 | |
9b61d62b ILT |
9431 | if (pass == 1) |
9432 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
9433 | "Unmatched %%hi reloc"); | |
9434 | } | |
867a58b3 ILT |
9435 | } |
9436 | } | |
9437 | ||
1c803e52 ILT |
9438 | /* When generating embedded PIC code we need to use a special |
9439 | relocation to represent the difference of two symbols in the .text | |
9440 | section (switch tables use a difference of this sort). See | |
9441 | include/coff/mips.h for details. This macro checks whether this | |
9442 | fixup requires the special reloc. */ | |
9443 | #define SWITCH_TABLE(fixp) \ | |
9444 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
9445 | && (fixp)->fx_addsy != NULL \ | |
9446 | && (fixp)->fx_subsy != NULL \ | |
9447 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9448 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9449 | ||
5b63f465 | 9450 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
9451 | relocations, in case the linker has to relax a call. We also need |
9452 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
9453 | |
9454 | /*ARGSUSED*/ | |
9455 | int | |
9456 | mips_force_relocation (fixp) | |
9457 | fixS *fixp; | |
9458 | { | |
1c803e52 | 9459 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
9460 | && (fixp->fx_pcrel |
9461 | || SWITCH_TABLE (fixp) | |
9462 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9463 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
9464 | } |
9465 | ||
9466 | /* Apply a fixup to the object file. */ | |
9467 | ||
3d3c5039 ILT |
9468 | int |
9469 | md_apply_fix (fixP, valueP) | |
9470 | fixS *fixP; | |
918692a5 | 9471 | valueT *valueP; |
3d3c5039 | 9472 | { |
670a50eb ILT |
9473 | unsigned char *buf; |
9474 | long insn, value; | |
3d3c5039 | 9475 | |
bf39474f ILT |
9476 | assert (fixP->fx_size == 4 |
9477 | || fixP->fx_r_type == BFD_RELOC_16 | |
9478 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 9479 | |
670a50eb | 9480 | value = *valueP; |
1748b9d8 ILT |
9481 | |
9482 | /* If we aren't adjusting this fixup to be against the section | |
9483 | symbol, we need to adjust the value. */ | |
68952421 | 9484 | #ifdef OBJ_ELF |
1748b9d8 | 9485 | if (fixP->fx_addsy != NULL |
1748b9d8 ILT |
9486 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
9487 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
9488 | { | |
9489 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9490 | if (value != 0 && ! fixP->fx_pcrel) | |
9491 | { | |
9492 | /* In this case, the bfd_install_relocation routine will | |
9493 | incorrectly add the symbol value back in. We just want | |
9494 | the addend to appear in the object file. */ | |
9495 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9496 | } | |
9497 | } | |
9498 | #endif | |
9499 | ||
670a50eb | 9500 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 9501 | |
5b63f465 ILT |
9502 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
9503 | fixP->fx_done = 1; | |
9504 | ||
670a50eb ILT |
9505 | switch (fixP->fx_r_type) |
9506 | { | |
3d3c5039 ILT |
9507 | case BFD_RELOC_MIPS_JMP: |
9508 | case BFD_RELOC_HI16: | |
9509 | case BFD_RELOC_HI16_S: | |
670a50eb | 9510 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
9511 | case BFD_RELOC_MIPS_LITERAL: |
9512 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
9513 | case BFD_RELOC_MIPS_GOT16: |
9514 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
9515 | case BFD_RELOC_MIPS_GOT_HI16: |
9516 | case BFD_RELOC_MIPS_GOT_LO16: | |
9517 | case BFD_RELOC_MIPS_CALL_HI16: | |
9518 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 9519 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 9520 | if (fixP->fx_pcrel) |
7b777690 ILT |
9521 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9522 | "Invalid PC relative reloc"); | |
670a50eb | 9523 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 9524 | break; |
3d3c5039 | 9525 | |
cc5703cd ILT |
9526 | case BFD_RELOC_MIPS16_JMP: |
9527 | /* We currently always generate a reloc against a symbol, which | |
9528 | means that we don't want an addend even if the symbol is | |
9529 | defined. */ | |
9530 | fixP->fx_addnumber = 0; | |
9531 | break; | |
9532 | ||
ecd4ca1c ILT |
9533 | case BFD_RELOC_PCREL_HI16_S: |
9534 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9535 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9536 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9537 | { | |
9538 | /* For an external symbol adjust by the address to make it | |
9539 | pcrel_offset. We use the address of the RELLO reloc | |
9540 | which follows this one. */ | |
9541 | value += (fixP->fx_next->fx_frag->fr_address | |
9542 | + fixP->fx_next->fx_where); | |
9543 | } | |
9544 | if (value & 0x8000) | |
9545 | value += 0x10000; | |
9546 | value >>= 16; | |
0221ddf7 | 9547 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9548 | if (target_big_endian) |
ecd4ca1c ILT |
9549 | buf += 2; |
9550 | md_number_to_chars (buf, value, 2); | |
9551 | break; | |
9552 | ||
9553 | case BFD_RELOC_PCREL_LO16: | |
9554 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9555 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9556 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9557 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 9558 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9559 | if (target_big_endian) |
ecd4ca1c ILT |
9560 | buf += 2; |
9561 | md_number_to_chars (buf, value, 2); | |
9562 | break; | |
9563 | ||
bf39474f ILT |
9564 | case BFD_RELOC_64: |
9565 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9566 | extended value if we are only 32 bits. */ | |
9567 | if (fixP->fx_done | |
9568 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9569 | { | |
9570 | if (8 <= sizeof (valueT)) | |
9571 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9572 | value, 8); | |
9573 | else | |
9574 | { | |
9575 | long w1, w2; | |
9576 | long hiv; | |
9577 | ||
9578 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 9579 | if (target_big_endian) |
bf39474f ILT |
9580 | w1 += 4; |
9581 | else | |
9582 | w2 += 4; | |
9583 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9584 | if ((value & 0x80000000) != 0) | |
9585 | hiv = 0xffffffff; | |
9586 | else | |
9587 | hiv = 0; | |
9588 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9589 | } | |
9590 | } | |
9591 | break; | |
9592 | ||
f3645945 ILT |
9593 | case BFD_RELOC_32: |
9594 | /* If we are deleting this reloc entry, we must fill in the | |
9595 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
9596 | resolved when it appears but is later defined. We also need |
9597 | to fill in the value if this is an embedded PIC switch table | |
9598 | entry. */ | |
9599 | if (fixP->fx_done | |
9600 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
9601 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
9602 | value, 4); | |
9603 | break; | |
9604 | ||
49ad0c4c ILT |
9605 | case BFD_RELOC_16: |
9606 | /* If we are deleting this reloc entry, we must fill in the | |
9607 | value now. */ | |
9608 | assert (fixP->fx_size == 2); | |
9609 | if (fixP->fx_done) | |
9610 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9611 | value, 2); | |
9612 | break; | |
9613 | ||
f3645945 ILT |
9614 | case BFD_RELOC_LO16: |
9615 | /* When handling an embedded PIC switch statement, we can wind | |
9616 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9617 | if (fixP->fx_done) | |
9618 | { | |
9619 | if (value < -0x8000 || value > 0x7fff) | |
9620 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9621 | "relocation overflow"); | |
0221ddf7 | 9622 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9623 | if (target_big_endian) |
f3645945 ILT |
9624 | buf += 2; |
9625 | md_number_to_chars (buf, value, 2); | |
9626 | } | |
9627 | break; | |
9628 | ||
3d3c5039 | 9629 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
9630 | /* |
9631 | * We need to save the bits in the instruction since fixup_segment() | |
9632 | * might be deleting the relocation entry (i.e., a branch within | |
9633 | * the current segment). | |
9634 | */ | |
fbcfacb7 | 9635 | if ((value & 0x3) != 0) |
3b320c48 ILT |
9636 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9637 | "Branch to odd address (%lx)", value); | |
670a50eb | 9638 | value >>= 2; |
670a50eb ILT |
9639 | |
9640 | /* update old instruction data */ | |
9641 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
9642 | if (target_big_endian) |
9643 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9644 | else | |
9645 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
9646 | |
9647 | if (value >= -0x8000 && value < 0x8000) | |
9648 | insn |= value & 0xffff; | |
9649 | else | |
9650 | { | |
9651 | /* The branch offset is too large. If this is an | |
9652 | unconditional branch, and we are not generating PIC code, | |
9653 | we can convert it to an absolute jump instruction. */ | |
9654 | if (mips_pic == NO_PIC | |
9655 | && fixP->fx_done | |
9656 | && fixP->fx_frag->fr_address >= text_section->vma | |
9657 | && (fixP->fx_frag->fr_address | |
9658 | < text_section->vma + text_section->_raw_size) | |
9659 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9660 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9661 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9662 | { | |
9663 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9664 | insn = 0x0c000000; /* jal */ | |
9665 | else | |
9666 | insn = 0x08000000; /* j */ | |
9667 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9668 | fixP->fx_done = 0; | |
9669 | fixP->fx_addsy = section_symbol (text_section); | |
9670 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9671 | } | |
9672 | else | |
9673 | { | |
9674 | /* FIXME. It would be possible in principle to handle | |
9675 | conditional branches which overflow. They could be | |
9676 | transformed into a branch around a jump. This would | |
9677 | require setting up variant frags for each different | |
9678 | branch type. The native MIPS assembler attempts to | |
9679 | handle these cases, but it appears to do it | |
9680 | incorrectly. */ | |
9681 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18f7e3dc | 9682 | "Branch out of range"); |
9da4c5d1 ILT |
9683 | } |
9684 | } | |
9685 | ||
604633ae | 9686 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 9687 | break; |
3d3c5039 ILT |
9688 | |
9689 | default: | |
670a50eb | 9690 | internalError (); |
3d3c5039 | 9691 | } |
5b63f465 | 9692 | |
670a50eb | 9693 | return 1; |
3d3c5039 ILT |
9694 | } |
9695 | ||
9696 | #if 0 | |
9697 | void | |
670a50eb ILT |
9698 | printInsn (oc) |
9699 | unsigned long oc; | |
3d3c5039 | 9700 | { |
670a50eb ILT |
9701 | const struct mips_opcode *p; |
9702 | int treg, sreg, dreg, shamt; | |
9703 | short imm; | |
9704 | const char *args; | |
9705 | int i; | |
3d3c5039 | 9706 | |
670a50eb ILT |
9707 | for (i = 0; i < NUMOPCODES; ++i) |
9708 | { | |
9709 | p = &mips_opcodes[i]; | |
9710 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9711 | { | |
9712 | printf ("%08lx %s\t", oc, p->name); | |
9713 | treg = (oc >> 16) & 0x1f; | |
9714 | sreg = (oc >> 21) & 0x1f; | |
9715 | dreg = (oc >> 11) & 0x1f; | |
9716 | shamt = (oc >> 6) & 0x1f; | |
9717 | imm = oc; | |
9718 | for (args = p->args;; ++args) | |
9719 | { | |
9720 | switch (*args) | |
9721 | { | |
3d3c5039 | 9722 | case '\0': |
670a50eb ILT |
9723 | printf ("\n"); |
9724 | break; | |
3d3c5039 ILT |
9725 | |
9726 | case ',': | |
9727 | case '(': | |
9728 | case ')': | |
670a50eb ILT |
9729 | printf ("%c", *args); |
9730 | continue; | |
3d3c5039 ILT |
9731 | |
9732 | case 'r': | |
670a50eb ILT |
9733 | assert (treg == sreg); |
9734 | printf ("$%d,$%d", treg, sreg); | |
9735 | continue; | |
3d3c5039 ILT |
9736 | |
9737 | case 'd': | |
918692a5 | 9738 | case 'G': |
670a50eb ILT |
9739 | printf ("$%d", dreg); |
9740 | continue; | |
3d3c5039 ILT |
9741 | |
9742 | case 't': | |
918692a5 | 9743 | case 'E': |
670a50eb ILT |
9744 | printf ("$%d", treg); |
9745 | continue; | |
3d3c5039 | 9746 | |
9226253a ILT |
9747 | case 'k': |
9748 | printf ("0x%x", treg); | |
9749 | continue; | |
9750 | ||
3d3c5039 ILT |
9751 | case 'b': |
9752 | case 's': | |
670a50eb ILT |
9753 | printf ("$%d", sreg); |
9754 | continue; | |
3d3c5039 ILT |
9755 | |
9756 | case 'a': | |
670a50eb ILT |
9757 | printf ("0x%08lx", oc & 0x1ffffff); |
9758 | continue; | |
3d3c5039 ILT |
9759 | |
9760 | case 'i': | |
9761 | case 'j': | |
9762 | case 'o': | |
9763 | case 'u': | |
670a50eb ILT |
9764 | printf ("%d", imm); |
9765 | continue; | |
3d3c5039 ILT |
9766 | |
9767 | case '<': | |
56c96faa | 9768 | case '>': |
670a50eb ILT |
9769 | printf ("$%d", shamt); |
9770 | continue; | |
3d3c5039 ILT |
9771 | |
9772 | default: | |
670a50eb | 9773 | internalError (); |
3d3c5039 | 9774 | } |
670a50eb | 9775 | break; |
3d3c5039 | 9776 | } |
670a50eb | 9777 | return; |
3d3c5039 ILT |
9778 | } |
9779 | } | |
670a50eb | 9780 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
9781 | } |
9782 | #endif | |
9783 | ||
9784 | static symbolS * | |
9785 | get_symbol () | |
9786 | { | |
670a50eb ILT |
9787 | int c; |
9788 | char *name; | |
9789 | symbolS *p; | |
9790 | ||
9791 | name = input_line_pointer; | |
9792 | c = get_symbol_end (); | |
9793 | p = (symbolS *) symbol_find_or_make (name); | |
9794 | *input_line_pointer = c; | |
9795 | return p; | |
3d3c5039 ILT |
9796 | } |
9797 | ||
becfe05e ILT |
9798 | /* Align the current frag to a given power of two. The MIPS assembler |
9799 | also automatically adjusts any preceding label. */ | |
9800 | ||
9801 | static void | |
23dc1ae3 | 9802 | mips_align (to, fill, label) |
becfe05e ILT |
9803 | int to; |
9804 | int fill; | |
23dc1ae3 | 9805 | symbolS *label; |
becfe05e | 9806 | { |
fbcfacb7 | 9807 | mips_emit_delays (false); |
e2e5acfa | 9808 | frag_align (to, fill, 0); |
becfe05e | 9809 | record_alignment (now_seg, to); |
23dc1ae3 | 9810 | if (label != NULL) |
becfe05e | 9811 | { |
23dc1ae3 ILT |
9812 | assert (S_GET_SEGMENT (label) == now_seg); |
9813 | label->sy_frag = frag_now; | |
9814 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
9815 | } |
9816 | } | |
9817 | ||
9818 | /* Align to a given power of two. .align 0 turns off the automatic | |
9819 | alignment used by the data creating pseudo-ops. */ | |
9820 | ||
3d3c5039 ILT |
9821 | static void |
9822 | s_align (x) | |
9823 | int x; | |
9824 | { | |
670a50eb ILT |
9825 | register int temp; |
9826 | register long temp_fill; | |
9827 | long max_alignment = 15; | |
3d3c5039 | 9828 | |
670a50eb | 9829 | /* |
3d3c5039 ILT |
9830 | |
9831 | o Note that the assembler pulls down any immediately preceeding label | |
9832 | to the aligned address. | |
9833 | o It's not documented but auto alignment is reinstated by | |
9834 | a .align pseudo instruction. | |
9835 | o Note also that after auto alignment is turned off the mips assembler | |
9836 | issues an error on attempt to assemble an improperly aligned data item. | |
9837 | We don't. | |
9838 | ||
9839 | */ | |
9840 | ||
670a50eb ILT |
9841 | temp = get_absolute_expression (); |
9842 | if (temp > max_alignment) | |
9843 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
9844 | else if (temp < 0) | |
9845 | { | |
9846 | as_warn ("Alignment negative: 0 assumed."); | |
9847 | temp = 0; | |
9848 | } | |
9849 | if (*input_line_pointer == ',') | |
9850 | { | |
9851 | input_line_pointer++; | |
9852 | temp_fill = get_absolute_expression (); | |
9853 | } | |
9854 | else | |
9855 | temp_fill = 0; | |
9856 | if (temp) | |
9857 | { | |
9858 | auto_align = 1; | |
fbcfacb7 ILT |
9859 | mips_align (temp, (int) temp_fill, |
9860 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 9861 | } |
670a50eb ILT |
9862 | else |
9863 | { | |
9864 | auto_align = 0; | |
3d3c5039 ILT |
9865 | } |
9866 | ||
670a50eb | 9867 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9868 | } |
9869 | ||
739708fa KR |
9870 | void |
9871 | mips_flush_pending_output () | |
becfe05e | 9872 | { |
fbcfacb7 ILT |
9873 | mips_emit_delays (false); |
9874 | mips_clear_insn_labels (); | |
becfe05e ILT |
9875 | } |
9876 | ||
3d3c5039 ILT |
9877 | static void |
9878 | s_change_sec (sec) | |
9879 | int sec; | |
9880 | { | |
88225433 | 9881 | segT seg; |
becfe05e | 9882 | |
5b63f465 ILT |
9883 | /* When generating embedded PIC code, we only use the .text, .lit8, |
9884 | .sdata and .sbss sections. We change the .data and .rdata | |
9885 | pseudo-ops to use .sdata. */ | |
9886 | if (mips_pic == EMBEDDED_PIC | |
9887 | && (sec == 'd' || sec == 'r')) | |
9888 | sec = 's'; | |
9889 | ||
acdc7ce3 ILT |
9890 | #ifdef OBJ_ELF |
9891 | /* The ELF backend needs to know that we are changing sections, so | |
9892 | that .previous works correctly. We could do something like check | |
9893 | for a obj_section_change_hook macro, but that might be confusing | |
9894 | as it would not be appropriate to use it in the section changing | |
9895 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
9896 | This should be cleaner, somehow. */ | |
9897 | obj_elf_section_change_hook (); | |
9898 | #endif | |
9899 | ||
fbcfacb7 | 9900 | mips_emit_delays (false); |
670a50eb ILT |
9901 | switch (sec) |
9902 | { | |
3d3c5039 | 9903 | case 't': |
604633ae | 9904 | s_text (0); |
670a50eb | 9905 | break; |
3d3c5039 | 9906 | case 'd': |
604633ae | 9907 | s_data (0); |
670a50eb | 9908 | break; |
3d3c5039 | 9909 | case 'b': |
670a50eb | 9910 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
9911 | demand_empty_rest_of_line (); |
9912 | break; | |
88225433 ILT |
9913 | |
9914 | case 'r': | |
1dc1e798 KR |
9915 | if (USE_GLOBAL_POINTER_OPT) |
9916 | { | |
9917 | seg = subseg_new (RDATA_SECTION_NAME, | |
9918 | (subsegT) get_absolute_expression ()); | |
9919 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9920 | { | |
9921 | bfd_set_section_flags (stdoutput, seg, | |
9922 | (SEC_ALLOC | |
9923 | | SEC_LOAD | |
9924 | | SEC_READONLY | |
9925 | | SEC_RELOC | |
9926 | | SEC_DATA)); | |
08e17202 ILT |
9927 | if (strcmp (TARGET_OS, "elf") != 0) |
9928 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9929 | } |
9930 | demand_empty_rest_of_line (); | |
9931 | } | |
9932 | else | |
9933 | { | |
9934 | as_bad ("No read only data section in this object file format"); | |
9935 | demand_empty_rest_of_line (); | |
9936 | return; | |
9937 | } | |
88225433 | 9938 | break; |
88225433 ILT |
9939 | |
9940 | case 's': | |
1dc1e798 KR |
9941 | if (USE_GLOBAL_POINTER_OPT) |
9942 | { | |
9943 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9944 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9945 | { | |
9946 | bfd_set_section_flags (stdoutput, seg, | |
9947 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9948 | | SEC_DATA); | |
08e17202 ILT |
9949 | if (strcmp (TARGET_OS, "elf") != 0) |
9950 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9951 | } |
9952 | demand_empty_rest_of_line (); | |
9953 | break; | |
9954 | } | |
9955 | else | |
9956 | { | |
9957 | as_bad ("Global pointers not supported; recompile -G 0"); | |
9958 | demand_empty_rest_of_line (); | |
9959 | return; | |
9960 | } | |
3d3c5039 | 9961 | } |
88225433 | 9962 | |
670a50eb | 9963 | auto_align = 1; |
3d3c5039 ILT |
9964 | } |
9965 | ||
739708fa KR |
9966 | void |
9967 | mips_enable_auto_align () | |
9da4c5d1 | 9968 | { |
9da4c5d1 ILT |
9969 | auto_align = 1; |
9970 | } | |
9971 | ||
3d3c5039 ILT |
9972 | static void |
9973 | s_cons (log_size) | |
9974 | int log_size; | |
9975 | { | |
23dc1ae3 ILT |
9976 | symbolS *label; |
9977 | ||
fbcfacb7 ILT |
9978 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9979 | mips_emit_delays (false); | |
670a50eb | 9980 | if (log_size > 0 && auto_align) |
23dc1ae3 | 9981 | mips_align (log_size, 0, label); |
fbcfacb7 | 9982 | mips_clear_insn_labels (); |
670a50eb | 9983 | cons (1 << log_size); |
3d3c5039 ILT |
9984 | } |
9985 | ||
3d3c5039 | 9986 | static void |
becfe05e ILT |
9987 | s_float_cons (type) |
9988 | int type; | |
3d3c5039 | 9989 | { |
23dc1ae3 ILT |
9990 | symbolS *label; |
9991 | ||
fbcfacb7 | 9992 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 9993 | |
fbcfacb7 | 9994 | mips_emit_delays (false); |
670a50eb ILT |
9995 | |
9996 | if (auto_align) | |
becfe05e | 9997 | if (type == 'd') |
23dc1ae3 | 9998 | mips_align (3, 0, label); |
670a50eb | 9999 | else |
23dc1ae3 | 10000 | mips_align (2, 0, label); |
670a50eb | 10001 | |
fbcfacb7 | 10002 | mips_clear_insn_labels (); |
1849d646 | 10003 | |
becfe05e | 10004 | float_cons (type); |
3d3c5039 ILT |
10005 | } |
10006 | ||
c1444ec4 ILT |
10007 | /* Handle .globl. We need to override it because on Irix 5 you are |
10008 | permitted to say | |
10009 | .globl foo .text | |
10010 | where foo is an undefined symbol, to mean that foo should be | |
10011 | considered to be the address of a function. */ | |
10012 | ||
10013 | static void | |
10014 | s_mips_globl (x) | |
10015 | int x; | |
10016 | { | |
10017 | char *name; | |
10018 | int c; | |
10019 | symbolS *symbolP; | |
fb251650 | 10020 | flagword flag; |
c1444ec4 ILT |
10021 | |
10022 | name = input_line_pointer; | |
10023 | c = get_symbol_end (); | |
10024 | symbolP = symbol_find_or_make (name); | |
10025 | *input_line_pointer = c; | |
10026 | SKIP_WHITESPACE (); | |
fb251650 ILT |
10027 | |
10028 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10029 | being a function is apparently labelled as being an object. */ | |
10030 | flag = BSF_OBJECT; | |
10031 | ||
c1444ec4 ILT |
10032 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
10033 | { | |
10034 | char *secname; | |
10035 | asection *sec; | |
10036 | ||
10037 | secname = input_line_pointer; | |
10038 | c = get_symbol_end (); | |
10039 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10040 | if (sec == NULL) | |
10041 | as_bad ("%s: no such section", secname); | |
10042 | *input_line_pointer = c; | |
10043 | ||
10044 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 10045 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
10046 | } |
10047 | ||
fb251650 ILT |
10048 | symbolP->bsym->flags |= flag; |
10049 | ||
c1444ec4 ILT |
10050 | S_SET_EXTERNAL (symbolP); |
10051 | demand_empty_rest_of_line (); | |
10052 | } | |
10053 | ||
3d3c5039 ILT |
10054 | static void |
10055 | s_option (x) | |
10056 | int x; | |
10057 | { | |
dd3f1f76 ILT |
10058 | char *opt; |
10059 | char c; | |
10060 | ||
10061 | opt = input_line_pointer; | |
10062 | c = get_symbol_end (); | |
10063 | ||
dd3f1f76 | 10064 | if (*opt == 'O') |
9226253a ILT |
10065 | { |
10066 | /* FIXME: What does this mean? */ | |
10067 | } | |
dd3f1f76 | 10068 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 10069 | { |
d9aba805 | 10070 | int i; |
42562568 | 10071 | |
d9aba805 ILT |
10072 | i = atoi (opt + 3); |
10073 | if (i == 0) | |
10074 | mips_pic = NO_PIC; | |
10075 | else if (i == 2) | |
10076 | mips_pic = SVR4_PIC; | |
10077 | else | |
10078 | as_bad (".option pic%d not supported", i); | |
10079 | ||
1dc1e798 | 10080 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
10081 | { |
10082 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 10083 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
10084 | g_switch_value = 0; |
10085 | bfd_set_gp_size (stdoutput, 0); | |
10086 | } | |
9226253a | 10087 | } |
dd3f1f76 ILT |
10088 | else |
10089 | as_warn ("Unrecognized option \"%s\"", opt); | |
10090 | ||
10091 | *input_line_pointer = c; | |
670a50eb | 10092 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
10093 | } |
10094 | ||
3c83da8a JW |
10095 | /* This structure is used to hold a stack of .set values. */ |
10096 | ||
10097 | struct mips_option_stack | |
10098 | { | |
10099 | struct mips_option_stack *next; | |
10100 | struct mips_set_options options; | |
10101 | }; | |
10102 | ||
10103 | static struct mips_option_stack *mips_opts_stack; | |
10104 | ||
10105 | /* Handle the .set pseudo-op. */ | |
10106 | ||
3d3c5039 ILT |
10107 | static void |
10108 | s_mipsset (x) | |
10109 | int x; | |
10110 | { | |
670a50eb ILT |
10111 | char *name = input_line_pointer, ch; |
10112 | ||
10113 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10114 | input_line_pointer++; | |
10115 | ch = *input_line_pointer; | |
10116 | *input_line_pointer = '\0'; | |
10117 | ||
10118 | if (strcmp (name, "reorder") == 0) | |
10119 | { | |
3c83da8a | 10120 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 10121 | { |
4a1cb507 ILT |
10122 | /* If we still have pending nops, we can discard them. The |
10123 | usual nop handling will insert any that are still | |
10124 | needed. */ | |
3c83da8a JW |
10125 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
10126 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 10127 | prev_nop_frag = NULL; |
4e95866e | 10128 | } |
3c83da8a | 10129 | mips_opts.noreorder = 0; |
670a50eb ILT |
10130 | } |
10131 | else if (strcmp (name, "noreorder") == 0) | |
10132 | { | |
fbcfacb7 | 10133 | mips_emit_delays (true); |
3c83da8a | 10134 | mips_opts.noreorder = 1; |
0dd2d296 | 10135 | mips_any_noreorder = 1; |
670a50eb ILT |
10136 | } |
10137 | else if (strcmp (name, "at") == 0) | |
10138 | { | |
3c83da8a | 10139 | mips_opts.noat = 0; |
670a50eb ILT |
10140 | } |
10141 | else if (strcmp (name, "noat") == 0) | |
10142 | { | |
3c83da8a | 10143 | mips_opts.noat = 1; |
3d3c5039 | 10144 | } |
670a50eb ILT |
10145 | else if (strcmp (name, "macro") == 0) |
10146 | { | |
3c83da8a | 10147 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
10148 | } |
10149 | else if (strcmp (name, "nomacro") == 0) | |
10150 | { | |
3c83da8a | 10151 | if (mips_opts.noreorder == 0) |
670a50eb | 10152 | as_bad ("`noreorder' must be set before `nomacro'"); |
3c83da8a | 10153 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
10154 | } |
10155 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10156 | { | |
3c83da8a | 10157 | mips_opts.nomove = 0; |
670a50eb ILT |
10158 | } |
10159 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10160 | { | |
3c83da8a | 10161 | mips_opts.nomove = 1; |
670a50eb ILT |
10162 | } |
10163 | else if (strcmp (name, "bopt") == 0) | |
10164 | { | |
3c83da8a | 10165 | mips_opts.nobopt = 0; |
670a50eb ILT |
10166 | } |
10167 | else if (strcmp (name, "nobopt") == 0) | |
10168 | { | |
3c83da8a | 10169 | mips_opts.nobopt = 1; |
670a50eb | 10170 | } |
943321c0 ILT |
10171 | else if (strcmp (name, "mips16") == 0 |
10172 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 10173 | mips_opts.mips16 = 1; |
943321c0 ILT |
10174 | else if (strcmp (name, "nomips16") == 0 |
10175 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 10176 | mips_opts.mips16 = 0; |
1051c97f ILT |
10177 | else if (strncmp (name, "mips", 4) == 0) |
10178 | { | |
10179 | int isa; | |
10180 | ||
10181 | /* Permit the user to change the ISA on the fly. Needless to | |
10182 | say, misuse can cause serious problems. */ | |
10183 | isa = atoi (name + 4); | |
10184 | if (isa == 0) | |
3c83da8a | 10185 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 10186 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
10187 | as_bad ("unknown ISA level"); |
10188 | else | |
3c83da8a | 10189 | mips_opts.isa = isa; |
1051c97f | 10190 | } |
cc5703cd | 10191 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 10192 | mips_opts.noautoextend = 0; |
cc5703cd | 10193 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
10194 | mips_opts.noautoextend = 1; |
10195 | else if (strcmp (name, "push") == 0) | |
10196 | { | |
10197 | struct mips_option_stack *s; | |
10198 | ||
10199 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10200 | s->next = mips_opts_stack; | |
10201 | s->options = mips_opts; | |
10202 | mips_opts_stack = s; | |
10203 | } | |
10204 | else if (strcmp (name, "pop") == 0) | |
10205 | { | |
10206 | struct mips_option_stack *s; | |
10207 | ||
10208 | s = mips_opts_stack; | |
10209 | if (s == NULL) | |
10210 | as_bad (".set pop with no .set push"); | |
10211 | else | |
10212 | { | |
10213 | /* If we're changing the reorder mode we need to handle | |
10214 | delay slots correctly. */ | |
10215 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10216 | mips_emit_delays (true); | |
10217 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10218 | { | |
10219 | if (prev_nop_frag != NULL) | |
10220 | { | |
10221 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10222 | * (mips_opts.mips16 ? 2 : 4)); | |
10223 | prev_nop_frag = NULL; | |
10224 | } | |
10225 | } | |
10226 | ||
10227 | mips_opts = s->options; | |
10228 | mips_opts_stack = s->next; | |
10229 | free (s); | |
10230 | } | |
10231 | } | |
670a50eb ILT |
10232 | else |
10233 | { | |
10234 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
10235 | } | |
10236 | *input_line_pointer = ch; | |
10237 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
10238 | } |
10239 | ||
9226253a ILT |
10240 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
10241 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10242 | ||
10243 | static void | |
10244 | s_abicalls (ignore) | |
10245 | int ignore; | |
10246 | { | |
d9aba805 | 10247 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
10248 | if (USE_GLOBAL_POINTER_OPT) |
10249 | { | |
10250 | if (g_switch_seen && g_switch_value != 0) | |
10251 | as_warn ("-G may not be used with SVR4 PIC code"); | |
10252 | g_switch_value = 0; | |
10253 | } | |
d9aba805 | 10254 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
10255 | demand_empty_rest_of_line (); |
10256 | } | |
10257 | ||
10258 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10259 | PIC code. It sets the $gp register for the function based on the | |
10260 | function address, which is in the register named in the argument. | |
10261 | This uses a relocation against _gp_disp, which is handled specially | |
10262 | by the linker. The result is: | |
10263 | lui $gp,%hi(_gp_disp) | |
10264 | addiu $gp,$gp,%lo(_gp_disp) | |
10265 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 10266 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
10267 | |
10268 | static void | |
10269 | s_cpload (ignore) | |
10270 | int ignore; | |
10271 | { | |
10272 | expressionS ex; | |
10273 | int icnt = 0; | |
10274 | ||
d9aba805 ILT |
10275 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
10276 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10277 | { |
10278 | s_ignore (0); | |
10279 | return; | |
10280 | } | |
10281 | ||
10282 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 10283 | if (mips_opts.noreorder == 0) |
0dd2d296 ILT |
10284 | as_warn (".cpload not in noreorder section"); |
10285 | ||
9226253a ILT |
10286 | ex.X_op = O_symbol; |
10287 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10288 | ex.X_op_symbol = NULL; | |
10289 | ex.X_add_number = 0; | |
10290 | ||
fb251650 ILT |
10291 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
10292 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
10293 | ||
0dd2d296 ILT |
10294 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
10295 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
10296 | (int) BFD_RELOC_LO16); |
10297 | ||
0dd2d296 ILT |
10298 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
10299 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
10300 | |
10301 | demand_empty_rest_of_line (); | |
10302 | } | |
10303 | ||
10304 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10305 | offset from $sp. The offset is remembered, and after making a PIC | |
10306 | call $gp is restored from that location. */ | |
10307 | ||
10308 | static void | |
10309 | s_cprestore (ignore) | |
10310 | int ignore; | |
10311 | { | |
10312 | expressionS ex; | |
10313 | int icnt = 0; | |
10314 | ||
d9aba805 ILT |
10315 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
10316 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
10317 | { |
10318 | s_ignore (0); | |
10319 | return; | |
10320 | } | |
10321 | ||
9226253a ILT |
10322 | mips_cprestore_offset = get_absolute_expression (); |
10323 | ||
10324 | ex.X_op = O_constant; | |
10325 | ex.X_add_symbol = NULL; | |
10326 | ex.X_op_symbol = NULL; | |
10327 | ex.X_add_number = mips_cprestore_offset; | |
10328 | ||
0dd2d296 | 10329 | macro_build ((char *) NULL, &icnt, &ex, |
9a1f3160 JL |
10330 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10331 | || mips_opts.isa < 3) | |
10332 | ? "sw" : "sd"), | |
9226253a ILT |
10333 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
10334 | ||
10335 | demand_empty_rest_of_line (); | |
10336 | } | |
10337 | ||
0dd2d296 ILT |
10338 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
10339 | code. It generates a 32 bit GP relative reloc. */ | |
10340 | ||
10341 | static void | |
10342 | s_gpword (ignore) | |
10343 | int ignore; | |
10344 | { | |
23dc1ae3 | 10345 | symbolS *label; |
0dd2d296 ILT |
10346 | expressionS ex; |
10347 | char *p; | |
10348 | ||
10349 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 10350 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10351 | { |
10352 | s_cons (2); | |
10353 | return; | |
10354 | } | |
10355 | ||
fbcfacb7 ILT |
10356 | label = insn_labels != NULL ? insn_labels->label : NULL; |
10357 | mips_emit_delays (true); | |
0dd2d296 | 10358 | if (auto_align) |
23dc1ae3 | 10359 | mips_align (2, 0, label); |
fbcfacb7 | 10360 | mips_clear_insn_labels (); |
0dd2d296 ILT |
10361 | |
10362 | expression (&ex); | |
10363 | ||
10364 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10365 | { | |
10366 | as_bad ("Unsupported use of .gpword"); | |
10367 | ignore_rest_of_line (); | |
10368 | } | |
10369 | ||
10370 | p = frag_more (4); | |
10371 | md_number_to_chars (p, (valueT) 0, 4); | |
10372 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10373 | BFD_RELOC_MIPS_GPREL32); | |
10374 | ||
10375 | demand_empty_rest_of_line (); | |
10376 | } | |
10377 | ||
10378 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10379 | tables in SVR4 PIC code. */ | |
10380 | ||
10381 | static void | |
10382 | s_cpadd (ignore) | |
10383 | int ignore; | |
10384 | { | |
10385 | int icnt = 0; | |
10386 | int reg; | |
10387 | ||
10388 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 10389 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
10390 | { |
10391 | s_ignore (0); | |
10392 | return; | |
10393 | } | |
10394 | ||
10395 | /* Add $gp to the register named as an argument. */ | |
10396 | reg = tc_get_register (0); | |
10397 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
9a1f3160 JL |
10398 | ((bfd_arch_bits_per_address (stdoutput) == 32 |
10399 | || mips_opts.isa < 3) | |
10400 | ? "addu" : "daddu"), | |
0dd2d296 ILT |
10401 | "d,v,t", reg, reg, GP); |
10402 | ||
10403 | demand_empty_rest_of_line (); | |
10404 | } | |
10405 | ||
ed3eb786 ILT |
10406 | /* Handle the .insn pseudo-op. This marks instruction labels in |
10407 | mips16 mode. This permits the linker to handle them specially, | |
10408 | such as generating jalx instructions when needed. We also make | |
10409 | them odd for the duration of the assembly, in order to generate the | |
10410 | right sort of code. We will make them even in the adjust_symtab | |
10411 | routine, while leaving them marked. This is convenient for the | |
10412 | debugger and the disassembler. The linker knows to make them odd | |
10413 | again. */ | |
10414 | ||
10415 | static void | |
10416 | s_insn (ignore) | |
10417 | int ignore; | |
10418 | { | |
3c83da8a JW |
10419 | if (mips_opts.mips16) |
10420 | mips16_mark_labels (); | |
ed3eb786 | 10421 | |
3c83da8a JW |
10422 | demand_empty_rest_of_line (); |
10423 | } | |
ed3eb786 | 10424 | |
3c83da8a JW |
10425 | /* Handle a .stabn directive. We need these in order to mark a label |
10426 | as being a mips16 text label correctly. Sometimes the compiler | |
10427 | will emit a label, followed by a .stabn, and then switch sections. | |
10428 | If the label and .stabn are in mips16 mode, then the label is | |
10429 | really a mips16 text label. */ | |
ed3eb786 | 10430 | |
3c83da8a JW |
10431 | static void |
10432 | s_mips_stab (type) | |
10433 | int type; | |
10434 | { | |
10435 | if (type == 'n' && mips_opts.mips16) | |
10436 | mips16_mark_labels (); | |
10437 | ||
10438 | s_stab (type); | |
ed3eb786 ILT |
10439 | } |
10440 | ||
9226253a | 10441 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
10442 | to parse .frame. The argument is non-zero if this is the frame |
10443 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 10444 | |
3d3c5039 | 10445 | int |
0dd2d296 ILT |
10446 | tc_get_register (frame) |
10447 | int frame; | |
3d3c5039 ILT |
10448 | { |
10449 | int reg; | |
10450 | ||
10451 | SKIP_WHITESPACE (); | |
10452 | if (*input_line_pointer++ != '$') | |
10453 | { | |
10454 | as_warn ("expected `$'"); | |
0dd2d296 | 10455 | reg = 0; |
3d3c5039 | 10456 | } |
0dd2d296 | 10457 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
10458 | { |
10459 | reg = get_absolute_expression (); | |
10460 | if (reg < 0 || reg >= 32) | |
10461 | { | |
10462 | as_warn ("Bad register number"); | |
10463 | reg = 0; | |
10464 | } | |
10465 | } | |
10466 | else | |
10467 | { | |
10468 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 10469 | reg = FP; |
3d3c5039 | 10470 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 10471 | reg = SP; |
3d3c5039 | 10472 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 10473 | reg = GP; |
3d3c5039 | 10474 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 10475 | reg = AT; |
3d3c5039 ILT |
10476 | else |
10477 | { | |
10478 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 10479 | reg = 0; |
3d3c5039 ILT |
10480 | } |
10481 | input_line_pointer += 2; | |
10482 | } | |
0dd2d296 ILT |
10483 | if (frame) |
10484 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
10485 | return reg; |
10486 | } | |
10487 | ||
0dd2d296 ILT |
10488 | valueT |
10489 | md_section_align (seg, addr) | |
10490 | asection *seg; | |
10491 | valueT addr; | |
10492 | { | |
10493 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10494 | ||
cf32394d ILT |
10495 | #ifdef OBJ_ELF |
10496 | /* We don't need to align ELF sections to the full alignment. | |
10497 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
10498 | byte boundary. We don't bother to align the sections if we are |
10499 | targeted for an embedded system. */ | |
10500 | if (strcmp (TARGET_OS, "elf") == 0) | |
10501 | return addr; | |
943321c0 ILT |
10502 | if (align > 4) |
10503 | align = 4; | |
10a14e36 | 10504 | #endif |
cf32394d ILT |
10505 | |
10506 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
10507 | } |
10508 | ||
d8a1c247 KR |
10509 | /* Utility routine, called from above as well. If called while the |
10510 | input file is still being read, it's only an approximation. (For | |
10511 | example, a symbol may later become defined which appeared to be | |
10512 | undefined earlier.) */ | |
22ba90ce ILT |
10513 | |
10514 | static int | |
85ce5635 | 10515 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 10516 | symbolS *sym; |
85ce5635 | 10517 | int before_relaxing; |
d8a1c247 KR |
10518 | { |
10519 | if (sym == 0) | |
10520 | return 0; | |
10521 | ||
1dc1e798 KR |
10522 | if (USE_GLOBAL_POINTER_OPT) |
10523 | { | |
10524 | const char *symname; | |
10525 | int change; | |
10526 | ||
10527 | /* Find out whether this symbol can be referenced off the GP | |
10528 | register. It can be if it is smaller than the -G size or if | |
10529 | it is in the .sdata or .sbss section. Certain symbols can | |
10530 | not be referenced off the GP, although it appears as though | |
10531 | they can. */ | |
10532 | symname = S_GET_NAME (sym); | |
10533 | if (symname != (const char *) NULL | |
10534 | && (strcmp (symname, "eprol") == 0 | |
10535 | || strcmp (symname, "etext") == 0 | |
10536 | || strcmp (symname, "_gp") == 0 | |
10537 | || strcmp (symname, "edata") == 0 | |
10538 | || strcmp (symname, "_fbss") == 0 | |
10539 | || strcmp (symname, "_fdata") == 0 | |
10540 | || strcmp (symname, "_ftext") == 0 | |
10541 | || strcmp (symname, "end") == 0 | |
10542 | || strcmp (symname, "_gp_disp") == 0)) | |
10543 | change = 1; | |
23ac3ca1 | 10544 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
10545 | && (0 |
10546 | #ifndef NO_ECOFF_DEBUGGING | |
10547 | || (sym->ecoff_extern_size != 0 | |
10548 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 10549 | #endif |
85ce5635 ILT |
10550 | /* We must defer this decision until after the whole |
10551 | file has been read, since there might be a .extern | |
10552 | after the first use of this symbol. */ | |
a5586bdc ILT |
10553 | || (before_relaxing |
10554 | #ifndef NO_ECOFF_DEBUGGING | |
10555 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 10556 | #endif |
a5586bdc | 10557 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
10558 | || (S_GET_VALUE (sym) != 0 |
10559 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10560 | change = 0; | |
10561 | else | |
10562 | { | |
10563 | const char *segname; | |
d8a1c247 | 10564 | |
1dc1e798 KR |
10565 | segname = segment_name (S_GET_SEGMENT (sym)); |
10566 | assert (strcmp (segname, ".lit8") != 0 | |
10567 | && strcmp (segname, ".lit4") != 0); | |
10568 | change = (strcmp (segname, ".sdata") != 0 | |
10569 | && strcmp (segname, ".sbss") != 0); | |
10570 | } | |
10571 | return change; | |
10572 | } | |
10573 | else | |
10574 | /* We are not optimizing for the GP register. */ | |
10575 | return 1; | |
d8a1c247 KR |
10576 | } |
10577 | ||
cc5703cd ILT |
10578 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
10579 | extended opcode. SEC is the section the frag is in. */ | |
10580 | ||
10581 | static int | |
10582 | mips16_extended_frag (fragp, sec, stretch) | |
10583 | fragS *fragp; | |
10584 | asection *sec; | |
10585 | long stretch; | |
10586 | { | |
10587 | int type; | |
10588 | register const struct mips16_immed_operand *op; | |
10589 | offsetT val; | |
10590 | int mintiny, maxtiny; | |
f74ba7a3 | 10591 | segT symsec; |
cc5703cd | 10592 | |
8728fa92 ILT |
10593 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
10594 | return 0; | |
10595 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10596 | return 1; | |
10597 | ||
cc5703cd ILT |
10598 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
10599 | op = mips16_immed_operands; | |
10600 | while (op->type != type) | |
10601 | { | |
10602 | ++op; | |
10603 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10604 | } | |
10605 | ||
10606 | if (op->unsp) | |
10607 | { | |
10608 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10609 | { | |
10610 | mintiny = 1; | |
10611 | maxtiny = 1 << op->nbits; | |
10612 | } | |
10613 | else | |
10614 | { | |
10615 | mintiny = 0; | |
10616 | maxtiny = (1 << op->nbits) - 1; | |
10617 | } | |
10618 | } | |
10619 | else | |
10620 | { | |
10621 | mintiny = - (1 << (op->nbits - 1)); | |
10622 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10623 | } | |
10624 | ||
f74ba7a3 ILT |
10625 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
10626 | a particular frag address. */ | |
10627 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
10628 | { | |
10629 | val = (fragp->fr_symbol->sy_value.X_add_number | |
10630 | + fragp->fr_symbol->sy_frag->fr_address); | |
10631 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
10632 | } | |
10633 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
10634 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
10635 | == O_constant)) | |
10636 | { | |
10637 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
10638 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
10639 | + fragp->fr_symbol->sy_value.X_add_number | |
10640 | + fragp->fr_symbol->sy_frag->fr_address); | |
10641 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
10642 | } | |
10643 | else | |
10644 | return 1; | |
cc5703cd ILT |
10645 | |
10646 | if (op->pcrel) | |
10647 | { | |
10648 | addressT addr; | |
10649 | ||
10650 | /* We won't have the section when we are called from | |
10651 | mips_relax_frag. However, we will always have been called | |
10652 | from md_estimate_size_before_relax first. If this is a | |
10653 | branch to a different section, we mark it as such. If SEC is | |
10654 | NULL, and the frag is not marked, then it must be a branch to | |
10655 | the same section. */ | |
10656 | if (sec == NULL) | |
10657 | { | |
10658 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10659 | return 1; | |
10660 | } | |
10661 | else | |
10662 | { | |
f74ba7a3 | 10663 | if (symsec != sec) |
cc5703cd ILT |
10664 | { |
10665 | fragp->fr_subtype = | |
10666 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10667 | ||
10668 | /* FIXME: We should support this, and let the linker | |
10669 | catch branches and loads that are out of range. */ | |
10670 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10671 | "unsupported PC relative reference to different section"); | |
10672 | ||
10673 | return 1; | |
10674 | } | |
10675 | } | |
10676 | ||
10677 | /* In this case, we know for sure that the symbol fragment is in | |
10678 | the same section. If the fr_address of the symbol fragment | |
10679 | is greater then the address of this fragment we want to add | |
10680 | in STRETCH in order to get a better estimate of the address. | |
10681 | This particularly matters because of the shift bits. */ | |
10682 | if (stretch != 0 | |
10683 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
10684 | { | |
10685 | fragS *f; | |
10686 | ||
a941619c ILT |
10687 | /* Adjust stretch for any alignment frag. Note that if have |
10688 | been expanding the earlier code, the symbol may be | |
10689 | defined in what appears to be an earlier frag. FIXME: | |
10690 | This doesn't handle the fr_subtype field, which specifies | |
10691 | a maximum number of bytes to skip when doing an | |
10692 | alignment. */ | |
10693 | for (f = fragp; | |
10694 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
10695 | f = f->fr_next) | |
cc5703cd | 10696 | { |
cc5703cd ILT |
10697 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
10698 | { | |
10699 | if (stretch < 0) | |
10700 | stretch = - ((- stretch) | |
10701 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10702 | else | |
10703 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10704 | if (stretch == 0) | |
10705 | break; | |
10706 | } | |
10707 | } | |
a941619c ILT |
10708 | if (f != NULL) |
10709 | val += stretch; | |
cc5703cd ILT |
10710 | } |
10711 | ||
a677feeb ILT |
10712 | addr = fragp->fr_address + fragp->fr_fix; |
10713 | ||
10714 | /* The base address rules are complicated. The base address of | |
10715 | a branch is the following instruction. The base address of a | |
10716 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
10717 | is in a delay slot (in which case it can not be extended) use |
10718 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 10719 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
10720 | { |
10721 | addr += 2; | |
319305a7 ILT |
10722 | |
10723 | /* If we are currently assuming that this frag should be | |
10724 | extended, then, the current address is two bytes | |
10725 | higher. */ | |
10726 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10727 | addr += 2; | |
10728 | ||
fbcfacb7 ILT |
10729 | /* Ignore the low bit in the target, since it will be set |
10730 | for a text label. */ | |
10731 | if ((val & 1) != 0) | |
10732 | --val; | |
10733 | } | |
a677feeb ILT |
10734 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10735 | addr -= 4; | |
10736 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10737 | addr -= 2; | |
cc5703cd | 10738 | |
cc5703cd ILT |
10739 | val -= addr & ~ ((1 << op->shift) - 1); |
10740 | ||
10741 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10742 | if (type == 'p' || type == 'q') | |
10743 | val /= 2; | |
10744 | ||
10745 | /* If any of the shifted bits are set, we must use an extended | |
10746 | opcode. If the address depends on the size of this | |
10747 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
10748 | use an extended opcode. We only check this when we are in |
10749 | the main relaxation loop, when SEC is NULL. */ | |
10750 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10751 | { | |
10752 | fragp->fr_subtype = | |
10753 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10754 | return 1; | |
10755 | } | |
10756 | ||
10757 | /* If we are about to mark a frag as extended because the value | |
10758 | is precisely maxtiny + 1, then there is a chance of an | |
10759 | infinite loop as in the following code: | |
10760 | la $4,foo | |
10761 | .skip 1020 | |
10762 | .align 2 | |
10763 | foo: | |
10764 | In this case when the la is extended, foo is 0x3fc bytes | |
10765 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10766 | the la must be extended. To avoid this loop, we mark the | |
10767 | frag as extended if it was small, and is about to become | |
10768 | extended with a value of maxtiny + 1. */ | |
10769 | if (val == ((maxtiny + 1) << op->shift) | |
10770 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10771 | && sec == NULL) | |
cc5703cd ILT |
10772 | { |
10773 | fragp->fr_subtype = | |
10774 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10775 | return 1; | |
10776 | } | |
10777 | } | |
41a0ed22 ILT |
10778 | else if (symsec != absolute_section && sec != NULL) |
10779 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
10780 | |
10781 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10782 | || val < (mintiny << op->shift) | |
10783 | || val > (maxtiny << op->shift)) | |
10784 | return 1; | |
10785 | else | |
10786 | return 0; | |
10787 | } | |
10788 | ||
10789 | /* Estimate the size of a frag before relaxing. Unless this is the | |
10790 | mips16, we are not really relaxing here, and the final size is | |
10791 | encoded in the subtype information. For the mips16, we have to | |
10792 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 10793 | |
0dd2d296 ILT |
10794 | /*ARGSUSED*/ |
10795 | int | |
10796 | md_estimate_size_before_relax (fragp, segtype) | |
10797 | fragS *fragp; | |
10798 | asection *segtype; | |
10799 | { | |
10800 | int change; | |
10801 | ||
cc5703cd ILT |
10802 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10803 | { | |
10804 | if (mips16_extended_frag (fragp, segtype, 0)) | |
10805 | { | |
10806 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10807 | return 4; | |
10808 | } | |
10809 | else | |
10810 | { | |
10811 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10812 | return 2; | |
10813 | } | |
10814 | } | |
10815 | ||
d9aba805 | 10816 | if (mips_pic == NO_PIC) |
0dd2d296 | 10817 | { |
85ce5635 | 10818 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 10819 | } |
d9aba805 | 10820 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10821 | { |
46a92fde ILT |
10822 | symbolS *sym; |
10823 | asection *symsec; | |
10824 | ||
10825 | sym = fragp->fr_symbol; | |
10826 | ||
10827 | /* Handle the case of a symbol equated to another symbol. */ | |
10828 | while (sym->sy_value.X_op == O_symbol | |
10829 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
10830 | { | |
10831 | symbolS *n; | |
10832 | ||
10833 | /* It's possible to get a loop here in a badly written | |
10834 | program. */ | |
10835 | n = sym->sy_value.X_add_symbol; | |
10836 | if (n == sym) | |
10837 | break; | |
10838 | sym = n; | |
10839 | } | |
10840 | ||
10841 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
10842 | |
10843 | /* This must duplicate the test in adjust_reloc_syms. */ | |
10844 | change = (symsec != &bfd_und_section | |
10845 | && symsec != &bfd_abs_section | |
10846 | && ! bfd_is_com_section (symsec)); | |
10847 | } | |
d9aba805 ILT |
10848 | else |
10849 | abort (); | |
0dd2d296 ILT |
10850 | |
10851 | if (change) | |
10852 | { | |
10853 | /* Record the offset to the first reloc in the fr_opcode field. | |
10854 | This lets md_convert_frag and tc_gen_reloc know that the code | |
10855 | must be expanded. */ | |
10856 | fragp->fr_opcode = (fragp->fr_literal | |
10857 | + fragp->fr_fix | |
10858 | - RELAX_OLD (fragp->fr_subtype) | |
10859 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
10860 | /* FIXME: This really needs as_warn_where. */ | |
10861 | if (RELAX_WARN (fragp->fr_subtype)) | |
10862 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
10863 | } | |
10864 | ||
10865 | if (! change) | |
10866 | return 0; | |
10867 | else | |
10868 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
10869 | } | |
10870 | ||
0d7f9025 ILT |
10871 | /* This is called to see whether a reloc against a defined symbol |
10872 | should be converted into a reloc against a section. Don't adjust | |
10873 | MIPS16 jump relocations, so we don't have to worry about the format | |
10874 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
10875 | mips16 symbols, so that the linker can find them if it needs to set |
10876 | up a stub. */ | |
0d7f9025 ILT |
10877 | |
10878 | int | |
10879 | mips_fix_adjustable (fixp) | |
10880 | fixS *fixp; | |
10881 | { | |
10882 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
10883 | return 0; | |
10884 | if (fixp->fx_addsy == NULL) | |
10885 | return 1; | |
68952421 | 10886 | #ifdef OBJ_ELF |
0d7f9025 | 10887 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
10888 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
10889 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
10890 | return 0; |
10891 | #endif | |
10892 | return 1; | |
10893 | } | |
10894 | ||
0dd2d296 ILT |
10895 | /* Translate internal representation of relocation info to BFD target |
10896 | format. */ | |
10897 | ||
10898 | arelent ** | |
3d3c5039 ILT |
10899 | tc_gen_reloc (section, fixp) |
10900 | asection *section; | |
10901 | fixS *fixp; | |
10902 | { | |
0dd2d296 | 10903 | static arelent *retval[4]; |
3d3c5039 | 10904 | arelent *reloc; |
a8aed9dd | 10905 | bfd_reloc_code_real_type code; |
3d3c5039 | 10906 | |
0dd2d296 ILT |
10907 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
10908 | retval[1] = NULL; | |
3d3c5039 ILT |
10909 | |
10910 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10911 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
10912 | |
10913 | if (mips_pic == EMBEDDED_PIC | |
10914 | && SWITCH_TABLE (fixp)) | |
10915 | { | |
10916 | /* For a switch table entry we use a special reloc. The addend | |
10917 | is actually the difference between the reloc address and the | |
10918 | subtrahend. */ | |
10919 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
10920 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
10921 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
10922 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
10923 | } | |
ecd4ca1c ILT |
10924 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
10925 | { | |
10926 | /* We use a special addend for an internal RELLO reloc. */ | |
10927 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10928 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
10929 | else | |
10930 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
10931 | } | |
10932 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
10933 | { | |
10934 | assert (fixp->fx_next != NULL | |
10935 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
10936 | /* We use a special addend for an internal RELHI reloc. The | |
10937 | reloc is relative to the RELLO; adjust the addend | |
10938 | accordingly. */ | |
10939 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10940 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
10941 | + fixp->fx_next->fx_where | |
10942 | - S_GET_VALUE (fixp->fx_subsy)); | |
10943 | else | |
10944 | reloc->addend = (fixp->fx_addnumber | |
10945 | + fixp->fx_next->fx_frag->fr_address | |
10946 | + fixp->fx_next->fx_where); | |
10947 | } | |
1c803e52 | 10948 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
10949 | reloc->addend = fixp->fx_addnumber; |
10950 | else | |
5b63f465 | 10951 | { |
1dc1e798 KR |
10952 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
10953 | /* A gruesome hack which is a result of the gruesome gas reloc | |
10954 | handling. */ | |
10955 | reloc->addend = reloc->address; | |
10956 | else | |
10957 | reloc->addend = -reloc->address; | |
5b63f465 | 10958 | } |
0dd2d296 ILT |
10959 | |
10960 | /* If this is a variant frag, we may need to adjust the existing | |
10961 | reloc and generate a new one. */ | |
10962 | if (fixp->fx_frag->fr_opcode != NULL | |
10963 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
10964 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
10965 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
10966 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10967 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
10968 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10969 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
10970 | { |
10971 | arelent *reloc2; | |
10972 | ||
cc5703cd ILT |
10973 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
10974 | ||
0dd2d296 | 10975 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
10976 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
10977 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
10978 | the second one handle all of them. */ | |
0dd2d296 ILT |
10979 | if (fixp->fx_next != NULL |
10980 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
10981 | { | |
fb251650 ILT |
10982 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
10983 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
10984 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10985 | && (fixp->fx_next->fx_r_type | |
10986 | == BFD_RELOC_MIPS_GOT_LO16)) | |
10987 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10988 | && (fixp->fx_next->fx_r_type | |
10989 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
10990 | retval[0] = NULL; |
10991 | return retval; | |
10992 | } | |
10993 | ||
10994 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
10995 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10996 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
10997 | retval[2] = NULL; | |
10998 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10999 | reloc2->address = (reloc->address | |
11000 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11001 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11002 | reloc2->addend = fixp->fx_addnumber; | |
11003 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11004 | assert (reloc2->howto != NULL); | |
11005 | ||
11006 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11007 | { | |
11008 | arelent *reloc3; | |
11009 | ||
11010 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11011 | retval[3] = NULL; | |
11012 | *reloc3 = *reloc2; | |
11013 | reloc3->address += 4; | |
11014 | } | |
11015 | ||
d9aba805 | 11016 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
11017 | { |
11018 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11019 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11020 | } | |
d9aba805 | 11021 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 11022 | { |
fb251650 | 11023 | switch (fixp->fx_r_type) |
0dd2d296 | 11024 | { |
fb251650 ILT |
11025 | default: |
11026 | abort (); | |
11027 | case BFD_RELOC_MIPS_GOT16: | |
11028 | break; | |
11029 | case BFD_RELOC_MIPS_CALL16: | |
11030 | case BFD_RELOC_MIPS_GOT_LO16: | |
11031 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 11032 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 11033 | break; |
0dd2d296 ILT |
11034 | } |
11035 | } | |
d9aba805 ILT |
11036 | else |
11037 | abort (); | |
0dd2d296 ILT |
11038 | } |
11039 | ||
a8aed9dd ILT |
11040 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
11041 | fixup_segment converted a non-PC relative reloc into a PC | |
11042 | relative reloc. In such a case, we need to convert the reloc | |
11043 | code. */ | |
11044 | code = fixp->fx_r_type; | |
11045 | if (fixp->fx_pcrel) | |
11046 | { | |
11047 | switch (code) | |
11048 | { | |
11049 | case BFD_RELOC_8: | |
11050 | code = BFD_RELOC_8_PCREL; | |
11051 | break; | |
11052 | case BFD_RELOC_16: | |
11053 | code = BFD_RELOC_16_PCREL; | |
11054 | break; | |
11055 | case BFD_RELOC_32: | |
11056 | code = BFD_RELOC_32_PCREL; | |
11057 | break; | |
bf39474f ILT |
11058 | case BFD_RELOC_64: |
11059 | code = BFD_RELOC_64_PCREL; | |
11060 | break; | |
a8aed9dd ILT |
11061 | case BFD_RELOC_8_PCREL: |
11062 | case BFD_RELOC_16_PCREL: | |
11063 | case BFD_RELOC_32_PCREL: | |
bf39474f | 11064 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 11065 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
11066 | case BFD_RELOC_PCREL_HI16_S: |
11067 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
11068 | break; |
11069 | default: | |
11070 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11071 | "Cannot make %s relocation PC relative", | |
11072 | bfd_get_reloc_code_name (code)); | |
11073 | } | |
11074 | } | |
11075 | ||
d9aba805 ILT |
11076 | /* To support a PC relative reloc when generating embedded PIC code |
11077 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11078 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 11079 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 11080 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
11081 | && mips_pic != EMBEDDED_PIC) |
11082 | reloc->howto = NULL; | |
11083 | else | |
a8aed9dd | 11084 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 11085 | |
52aa70b5 JW |
11086 | if (reloc->howto == NULL) |
11087 | { | |
11088 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
11089 | "Can not represent %s relocation in this object file format", |
11090 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 11091 | retval[0] = NULL; |
52aa70b5 | 11092 | } |
3d3c5039 | 11093 | |
0dd2d296 | 11094 | return retval; |
3d3c5039 ILT |
11095 | } |
11096 | ||
cc5703cd ILT |
11097 | /* Relax a machine dependent frag. This returns the amount by which |
11098 | the current size of the frag should change. */ | |
11099 | ||
11100 | int | |
11101 | mips_relax_frag (fragp, stretch) | |
11102 | fragS *fragp; | |
11103 | long stretch; | |
11104 | { | |
11105 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11106 | return 0; | |
11107 | ||
11108 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11109 | { | |
11110 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11111 | return 0; | |
11112 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11113 | return 2; | |
11114 | } | |
11115 | else | |
11116 | { | |
11117 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11118 | return 0; | |
11119 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11120 | return -2; | |
11121 | } | |
11122 | ||
11123 | return 0; | |
11124 | } | |
11125 | ||
0dd2d296 ILT |
11126 | /* Convert a machine dependent frag. */ |
11127 | ||
11128 | void | |
11129 | md_convert_frag (abfd, asec, fragp) | |
11130 | bfd *abfd; | |
11131 | segT asec; | |
11132 | fragS *fragp; | |
3d3c5039 | 11133 | { |
0dd2d296 ILT |
11134 | int old, new; |
11135 | char *fixptr; | |
3d3c5039 | 11136 | |
cc5703cd ILT |
11137 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
11138 | { | |
11139 | int type; | |
11140 | register const struct mips16_immed_operand *op; | |
11141 | boolean small, ext; | |
11142 | offsetT val; | |
11143 | bfd_byte *buf; | |
11144 | unsigned long insn; | |
11145 | boolean use_extend; | |
11146 | unsigned short extend; | |
11147 | ||
11148 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11149 | op = mips16_immed_operands; | |
11150 | while (op->type != type) | |
11151 | ++op; | |
11152 | ||
11153 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11154 | { | |
11155 | small = false; | |
11156 | ext = true; | |
11157 | } | |
11158 | else | |
11159 | { | |
11160 | small = true; | |
11161 | ext = false; | |
11162 | } | |
11163 | ||
b637f306 | 11164 | resolve_symbol_value (fragp->fr_symbol, 1); |
cc5703cd | 11165 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
11166 | if (op->pcrel) |
11167 | { | |
11168 | addressT addr; | |
11169 | ||
a677feeb ILT |
11170 | addr = fragp->fr_address + fragp->fr_fix; |
11171 | ||
11172 | /* The rules for the base address of a PC relative reloc are | |
11173 | complicated; see mips16_extended_frag. */ | |
11174 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
11175 | { |
11176 | addr += 2; | |
319305a7 ILT |
11177 | if (ext) |
11178 | addr += 2; | |
fbcfacb7 ILT |
11179 | /* Ignore the low bit in the target, since it will be |
11180 | set for a text label. */ | |
11181 | if ((val & 1) != 0) | |
11182 | --val; | |
11183 | } | |
a677feeb ILT |
11184 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
11185 | addr -= 4; | |
11186 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11187 | addr -= 2; | |
11188 | ||
cc5703cd ILT |
11189 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
11190 | val -= addr; | |
a677feeb ILT |
11191 | |
11192 | /* Make sure the section winds up with the alignment we have | |
11193 | assumed. */ | |
11194 | if (op->shift > 0) | |
11195 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
11196 | } |
11197 | ||
035936da ILT |
11198 | if (ext |
11199 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11200 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11201 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
11202 | "extended instruction in delay slot"); | |
11203 | ||
cc5703cd ILT |
11204 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
11205 | ||
b9129c6f ILT |
11206 | if (target_big_endian) |
11207 | insn = bfd_getb16 (buf); | |
11208 | else | |
11209 | insn = bfd_getl16 (buf); | |
cc5703cd | 11210 | |
31a2c6ff ILT |
11211 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
11212 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11213 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
11214 | |
11215 | if (use_extend) | |
11216 | { | |
11217 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11218 | fragp->fr_fix += 2; | |
11219 | buf += 2; | |
11220 | } | |
3d3c5039 | 11221 | |
cc5703cd ILT |
11222 | md_number_to_chars (buf, insn, 2); |
11223 | fragp->fr_fix += 2; | |
11224 | buf += 2; | |
11225 | } | |
11226 | else | |
11227 | { | |
11228 | if (fragp->fr_opcode == NULL) | |
11229 | return; | |
0dd2d296 | 11230 | |
cc5703cd ILT |
11231 | old = RELAX_OLD (fragp->fr_subtype); |
11232 | new = RELAX_NEW (fragp->fr_subtype); | |
11233 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 11234 | |
cc5703cd ILT |
11235 | if (new > 0) |
11236 | memcpy (fixptr - old, fixptr, new); | |
11237 | ||
11238 | fragp->fr_fix += new - old; | |
11239 | } | |
0dd2d296 | 11240 | } |
becfe05e | 11241 | |
fbcfacb7 ILT |
11242 | #ifdef OBJ_ELF |
11243 | ||
11244 | /* This function is called after the relocs have been generated. | |
11245 | We've been storing mips16 text labels as odd. Here we convert them | |
11246 | back to even for the convenience of the debugger. */ | |
11247 | ||
11248 | void | |
11249 | mips_frob_file_after_relocs () | |
11250 | { | |
11251 | asymbol **syms; | |
11252 | unsigned int count, i; | |
11253 | ||
11254 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11255 | return; | |
11256 | ||
11257 | syms = bfd_get_outsymbols (stdoutput); | |
11258 | count = bfd_get_symcount (stdoutput); | |
11259 | for (i = 0; i < count; i++, syms++) | |
11260 | { | |
11261 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11262 | && ((*syms)->value & 1) != 0) | |
11263 | { | |
11264 | (*syms)->value &= ~1; | |
11265 | /* If the symbol has an odd size, it was probably computed | |
11266 | incorrectly, so adjust that as well. */ | |
11267 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11268 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11269 | } | |
11270 | } | |
11271 | } | |
11272 | ||
11273 | #endif | |
11274 | ||
becfe05e ILT |
11275 | /* This function is called whenever a label is defined. It is used |
11276 | when handling branch delays; if a branch has a label, we assume we | |
11277 | can not move it. */ | |
11278 | ||
11279 | void | |
11280 | mips_define_label (sym) | |
11281 | symbolS *sym; | |
11282 | { | |
fbcfacb7 ILT |
11283 | struct insn_label_list *l; |
11284 | ||
11285 | if (free_insn_labels == NULL) | |
11286 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11287 | else | |
11288 | { | |
11289 | l = free_insn_labels; | |
11290 | free_insn_labels = l->next; | |
11291 | } | |
11292 | ||
11293 | l->label = sym; | |
11294 | l->next = insn_labels; | |
11295 | insn_labels = l; | |
becfe05e | 11296 | } |
3d3c5039 | 11297 | \f |
739708fa | 11298 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 11299 | |
0dd2d296 | 11300 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
11301 | |
11302 | void | |
11303 | mips_elf_final_processing () | |
11304 | { | |
87178180 ILT |
11305 | /* Write out the register information. */ |
11306 | if (! mips_64) | |
11307 | { | |
11308 | Elf32_RegInfo s; | |
11309 | ||
11310 | s.ri_gprmask = mips_gprmask; | |
11311 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11312 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11313 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11314 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11315 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11316 | ||
11317 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11318 | ((Elf32_External_RegInfo *) | |
11319 | mips_regmask_frag)); | |
11320 | } | |
11321 | else | |
11322 | { | |
11323 | Elf64_Internal_RegInfo s; | |
11324 | ||
11325 | s.ri_gprmask = mips_gprmask; | |
11326 | s.ri_pad = 0; | |
11327 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11328 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11329 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11330 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11331 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11332 | ||
11333 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11334 | ((Elf64_External_RegInfo *) | |
11335 | mips_regmask_frag)); | |
11336 | } | |
0dd2d296 ILT |
11337 | |
11338 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11339 | sort of BFD interface for this. */ | |
11340 | if (mips_any_noreorder) | |
11341 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 11342 | if (mips_pic != NO_PIC) |
0dd2d296 | 11343 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
11344 | } |
11345 | ||
739708fa | 11346 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 11347 | \f |
3d3c5039 ILT |
11348 | /* These functions should really be defined by the object file format, |
11349 | since they are related to debugging information. However, this | |
11350 | code has to work for the a.out format, which does not define them, | |
11351 | so we provide simple versions here. These don't actually generate | |
11352 | any debugging information, but they do simple checking and someday | |
11353 | somebody may make them useful. */ | |
11354 | ||
670a50eb ILT |
11355 | typedef struct loc |
11356 | { | |
11357 | struct loc *loc_next; | |
11358 | unsigned long loc_fileno; | |
11359 | unsigned long loc_lineno; | |
11360 | unsigned long loc_offset; | |
11361 | unsigned short loc_delta; | |
11362 | unsigned short loc_count; | |
3d3c5039 | 11363 | #if 0 |
670a50eb | 11364 | fragS *loc_frag; |
3d3c5039 | 11365 | #endif |
670a50eb ILT |
11366 | } |
11367 | locS; | |
3d3c5039 | 11368 | |
670a50eb ILT |
11369 | typedef struct proc |
11370 | { | |
3d3c5039 ILT |
11371 | struct proc *proc_next; |
11372 | struct symbol *proc_isym; | |
11373 | struct symbol *proc_end; | |
11374 | unsigned long proc_reg_mask; | |
11375 | unsigned long proc_reg_offset; | |
11376 | unsigned long proc_fpreg_mask; | |
11377 | unsigned long proc_fpreg_offset; | |
11378 | unsigned long proc_frameoffset; | |
11379 | unsigned long proc_framereg; | |
11380 | unsigned long proc_pcreg; | |
11381 | locS *proc_iline; | |
11382 | struct file *proc_file; | |
11383 | int proc_index; | |
670a50eb ILT |
11384 | } |
11385 | procS; | |
3d3c5039 | 11386 | |
670a50eb ILT |
11387 | typedef struct file |
11388 | { | |
3d3c5039 ILT |
11389 | struct file *file_next; |
11390 | unsigned long file_fileno; | |
11391 | struct symbol *file_symbol; | |
11392 | struct symbol *file_end; | |
11393 | struct proc *file_proc; | |
11394 | int file_numprocs; | |
670a50eb ILT |
11395 | } |
11396 | fileS; | |
3d3c5039 ILT |
11397 | |
11398 | static struct obstack proc_frags; | |
11399 | static procS *proc_lastP; | |
11400 | static procS *proc_rootP; | |
11401 | static int numprocs; | |
11402 | ||
11403 | static void | |
11404 | md_obj_begin () | |
11405 | { | |
670a50eb | 11406 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
11407 | } |
11408 | ||
11409 | static void | |
11410 | md_obj_end () | |
11411 | { | |
11412 | /* check for premature end, nesting errors, etc */ | |
11413 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 11414 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
11415 | } |
11416 | ||
3d3c5039 ILT |
11417 | static long |
11418 | get_number () | |
11419 | { | |
670a50eb ILT |
11420 | int negative = 0; |
11421 | long val = 0; | |
3d3c5039 | 11422 | |
670a50eb ILT |
11423 | if (*input_line_pointer == '-') |
11424 | { | |
11425 | ++input_line_pointer; | |
11426 | negative = 1; | |
3d3c5039 | 11427 | } |
670a50eb ILT |
11428 | if (!isdigit (*input_line_pointer)) |
11429 | as_bad ("Expected simple number."); | |
11430 | if (input_line_pointer[0] == '0') | |
11431 | { | |
11432 | if (input_line_pointer[1] == 'x') | |
11433 | { | |
11434 | input_line_pointer += 2; | |
11435 | while (isxdigit (*input_line_pointer)) | |
11436 | { | |
11437 | val <<= 4; | |
3a762a0b | 11438 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 11439 | } |
670a50eb ILT |
11440 | return negative ? -val : val; |
11441 | } | |
11442 | else | |
11443 | { | |
11444 | ++input_line_pointer; | |
11445 | while (isdigit (*input_line_pointer)) | |
11446 | { | |
11447 | val <<= 3; | |
11448 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 11449 | } |
670a50eb | 11450 | return negative ? -val : val; |
3d3c5039 ILT |
11451 | } |
11452 | } | |
670a50eb ILT |
11453 | if (!isdigit (*input_line_pointer)) |
11454 | { | |
11455 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
11456 | *input_line_pointer, *input_line_pointer); | |
11457 | as_warn ("Invalid number"); | |
11458 | return -1; | |
3d3c5039 | 11459 | } |
670a50eb ILT |
11460 | while (isdigit (*input_line_pointer)) |
11461 | { | |
11462 | val *= 10; | |
11463 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 11464 | } |
670a50eb | 11465 | return negative ? -val : val; |
3d3c5039 ILT |
11466 | } |
11467 | ||
11468 | /* The .file directive; just like the usual .file directive, but there | |
11469 | is an initial number which is the ECOFF file index. */ | |
11470 | ||
11471 | static void | |
11472 | s_file (x) | |
11473 | int x; | |
11474 | { | |
670a50eb | 11475 | int line; |
3d3c5039 | 11476 | |
670a50eb | 11477 | line = get_number (); |
9a7d824a | 11478 | s_app_file (0); |
3d3c5039 ILT |
11479 | } |
11480 | ||
11481 | ||
11482 | /* The .end directive. */ | |
11483 | ||
11484 | static void | |
11485 | s_mipsend (x) | |
11486 | int x; | |
11487 | { | |
670a50eb ILT |
11488 | symbolS *p; |
11489 | ||
11490 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11491 | { | |
11492 | p = get_symbol (); | |
11493 | demand_empty_rest_of_line (); | |
11494 | } | |
11495 | else | |
11496 | p = NULL; | |
11497 | if (now_seg != text_section) | |
11498 | as_warn (".end not in text section"); | |
11499 | if (!proc_lastP) | |
11500 | { | |
11501 | as_warn (".end and no .ent seen yet."); | |
11502 | return; | |
3d3c5039 ILT |
11503 | } |
11504 | ||
670a50eb ILT |
11505 | if (p != NULL) |
11506 | { | |
11507 | assert (S_GET_NAME (p)); | |
11508 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
11509 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
11510 | } |
11511 | ||
670a50eb | 11512 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
11513 | } |
11514 | ||
11515 | /* The .aent and .ent directives. */ | |
11516 | ||
11517 | static void | |
11518 | s_ent (aent) | |
11519 | int aent; | |
11520 | { | |
670a50eb ILT |
11521 | int number = 0; |
11522 | procS *procP; | |
11523 | symbolS *symbolP; | |
11524 | ||
11525 | symbolP = get_symbol (); | |
11526 | if (*input_line_pointer == ',') | |
11527 | input_line_pointer++; | |
dd3f1f76 | 11528 | SKIP_WHITESPACE (); |
670a50eb ILT |
11529 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
11530 | number = get_number (); | |
11531 | if (now_seg != text_section) | |
11532 | as_warn (".ent or .aent not in text section."); | |
11533 | ||
11534 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
11535 | as_warn ("missing `.end'"); | |
11536 | ||
11537 | if (!aent) | |
11538 | { | |
11539 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
11540 | procP->proc_isym = symbolP; | |
11541 | procP->proc_reg_mask = 0; | |
11542 | procP->proc_reg_offset = 0; | |
11543 | procP->proc_fpreg_mask = 0; | |
11544 | procP->proc_fpreg_offset = 0; | |
11545 | procP->proc_frameoffset = 0; | |
11546 | procP->proc_framereg = 0; | |
11547 | procP->proc_pcreg = 0; | |
11548 | procP->proc_end = NULL; | |
11549 | procP->proc_next = NULL; | |
11550 | if (proc_lastP) | |
11551 | proc_lastP->proc_next = procP; | |
11552 | else | |
11553 | proc_rootP = procP; | |
11554 | proc_lastP = procP; | |
11555 | numprocs++; | |
3d3c5039 | 11556 | } |
670a50eb | 11557 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
11558 | } |
11559 | ||
11560 | /* The .frame directive. */ | |
11561 | ||
88225433 | 11562 | #if 0 |
3d3c5039 ILT |
11563 | static void |
11564 | s_frame (x) | |
670a50eb | 11565 | int x; |
3d3c5039 | 11566 | { |
670a50eb ILT |
11567 | char str[100]; |
11568 | symbolS *symP; | |
11569 | int frame_reg; | |
11570 | int frame_off; | |
11571 | int pcreg; | |
11572 | ||
0dd2d296 | 11573 | frame_reg = tc_get_register (1); |
670a50eb ILT |
11574 | if (*input_line_pointer == ',') |
11575 | input_line_pointer++; | |
5ac34ac3 | 11576 | frame_off = get_absolute_expression (); |
670a50eb ILT |
11577 | if (*input_line_pointer == ',') |
11578 | input_line_pointer++; | |
0dd2d296 | 11579 | pcreg = tc_get_register (0); |
670a50eb ILT |
11580 | |
11581 | /* bob third eye */ | |
11582 | assert (proc_rootP); | |
11583 | proc_rootP->proc_framereg = frame_reg; | |
11584 | proc_rootP->proc_frameoffset = frame_off; | |
11585 | proc_rootP->proc_pcreg = pcreg; | |
11586 | /* bob macho .frame */ | |
11587 | ||
11588 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 11589 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
11590 | { |
11591 | if (!proc_lastP) | |
11592 | as_warn ("No .ent for .frame to use."); | |
11593 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
11594 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
11595 | S_SET_TYPE (symP, N_RMASK); | |
11596 | S_SET_OTHER (symP, 0); | |
11597 | S_SET_DESC (symP, 0); | |
11598 | symP->sy_forward = proc_lastP->proc_isym; | |
11599 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11600 | } |
670a50eb | 11601 | demand_empty_rest_of_line (); |
3d3c5039 | 11602 | } |
88225433 | 11603 | #endif |
3d3c5039 ILT |
11604 | |
11605 | /* The .fmask and .mask directives. */ | |
11606 | ||
88225433 | 11607 | #if 0 |
3d3c5039 ILT |
11608 | static void |
11609 | s_mask (reg_type) | |
11610 | char reg_type; | |
11611 | { | |
670a50eb ILT |
11612 | char str[100], *strP; |
11613 | symbolS *symP; | |
11614 | int i; | |
11615 | unsigned int mask; | |
11616 | int off; | |
11617 | ||
11618 | mask = get_number (); | |
11619 | if (*input_line_pointer == ',') | |
11620 | input_line_pointer++; | |
11621 | off = get_absolute_expression (); | |
11622 | ||
11623 | /* bob only for coff */ | |
11624 | assert (proc_rootP); | |
11625 | if (reg_type == 'F') | |
11626 | { | |
11627 | proc_rootP->proc_fpreg_mask = mask; | |
11628 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 11629 | } |
670a50eb ILT |
11630 | else |
11631 | { | |
11632 | proc_rootP->proc_reg_mask = mask; | |
11633 | proc_rootP->proc_reg_offset = off; | |
11634 | } | |
11635 | ||
11636 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 11637 | |
670a50eb ILT |
11638 | /* We don't have to write out a mask stab if no saved regs. */ |
11639 | if (!(mask == 0)) | |
11640 | { | |
11641 | if (!proc_lastP) | |
11642 | as_warn ("No .ent for .mask to use."); | |
11643 | strP = str; | |
11644 | for (i = 0; i < 32; i++) | |
11645 | { | |
11646 | if (mask % 2) | |
11647 | { | |
11648 | sprintf (strP, "%c%d,", reg_type, i); | |
11649 | strP += strlen (strP); | |
11650 | } | |
3d3c5039 | 11651 | mask /= 2; |
670a50eb ILT |
11652 | } |
11653 | sprintf (strP, ";%d,", off); | |
11654 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
11655 | S_SET_TYPE (symP, N_RMASK); | |
11656 | S_SET_OTHER (symP, 0); | |
11657 | S_SET_DESC (symP, 0); | |
11658 | symP->sy_forward = proc_lastP->proc_isym; | |
11659 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11660 | } |
3d3c5039 | 11661 | } |
88225433 | 11662 | #endif |
3d3c5039 ILT |
11663 | |
11664 | /* The .loc directive. */ | |
11665 | ||
88225433 | 11666 | #if 0 |
3d3c5039 ILT |
11667 | static void |
11668 | s_loc (x) | |
11669 | int x; | |
11670 | { | |
670a50eb ILT |
11671 | symbolS *symbolP; |
11672 | int lineno; | |
11673 | int addroff; | |
3d3c5039 | 11674 | |
670a50eb | 11675 | assert (now_seg == text_section); |
3d3c5039 | 11676 | |
670a50eb | 11677 | lineno = get_number (); |
87e48495 | 11678 | addroff = frag_now_fix (); |
3d3c5039 | 11679 | |
670a50eb ILT |
11680 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
11681 | S_SET_TYPE (symbolP, N_SLINE); | |
11682 | S_SET_OTHER (symbolP, 0); | |
11683 | S_SET_DESC (symbolP, lineno); | |
11684 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 11685 | } |
88225433 | 11686 | #endif |